<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>fulafel</author><text>&amp;gt; RISC was a set of design principles developed in the 1980’s that enabled hardware to get much faster and more efficient. We tend to still call modern-looking instruction sets “RISC-y”, but really, a bunch of the original design principles of RISC CPU’s have not stood the test of time. So let’s look at the things that have worked and not worked between the 1980’s and 2022.&lt;p&gt;I think the design principles of RISC were actually on a meta level above this: take the quantitative approach, use your transistors to best serve the software you have and compilers you can build. &amp;quot;Nice ISA to write assembly code for&amp;quot; was thrown out, or at least demoted significantly.&lt;p&gt;In that 80s moment in the transistor count curve, it meant simplifying the ISA very radically in order to implement fewer instructions in hard coded way without microcode, to the point of ditching HW multiply instructions. The microarchitecture could either do fast, pipelined execution or large instruction set in the transitor budget, you optimized for bang for the buck in the whole-system sense. You could make simple fast machines  that were designed to run Unix (so had just enough VM, exception, etc support).</text><parent_chain></parent_chain></comment><story><title>RISC in 2022</title><url>https://wiki.alopex.li/RiscIn2022</url></story>
<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>rwmj</author><text>Should be &amp;quot;32-ish &lt;i&gt;architectural&lt;/i&gt; registers&amp;quot;.  Real processors have a lot more registers but they are not directly visible.  This is the whole reason why x86-64 is usable despite having only 16 architectural integer registers (or actually a little less than that).&lt;p&gt;The article doesn&amp;#x27;t get RISC-V instruction encoding right.  It mentions compressed instructions, but instructions can also be longer than 32 bits.  The important thing about RISC-V is that the instruction stream can easily be divided at instruction boundaries (unlike, say, x86 which is horrific to decode).  This gives you most of the benefits of fixed size instructions and the benefits of extensibility when you need it.</text><parent_chain></parent_chain></comment><story><title>RISC in 2022</title><url>https://wiki.alopex.li/RiscIn2022</url></story>