<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>johnklos</author><text>There were lots of computers in the &amp;#x27;80s which claimed official MS-DOS compatibility through emulation or added hardware. There were the Solution and Conqueror emulators for the Sinclair QL, there was Amiga Transformer from Commodore for the Amiga, there were ST Outlook and pc-ditto for the Atari ST.&lt;p&gt;Not long afterwards, hardware made MS-DOS compatibility much better because the speed of MS-DOS could easily be as fast as or faster than real IBM hardware. There were many options including the Sidecar, BridgeBoards, KCS PowerPC, and more on Amigas. Later, there were DOS compatibility cards for Macs.&lt;p&gt;Often these options had advantages over having a separate DOS compatible computer, like the ability to still run the native system at the same time, and often to share files &amp;#x2F; drives and other resources. It was an interesting time, for sure.</text><parent_chain><item><author>derefr</author><text>How about the opposite: PC-compatible non-x86 computers?&lt;p&gt;Like how the Transmeta Crusoe was an x86-compatible CPU... but moreso.&lt;p&gt;The Crusoe was a thing marketed as a &amp;quot;CPU&amp;quot;, that was actually internally an SoC (with the CPU inside it being non-x86.) This SoC had its own internal RAM and storage, and booted itself into internal software that then emulated an x86 CPU. All of the &amp;quot;CPU&amp;quot; data pins on the Crusoe SoC, routed to the virtual CPU inputs and outputs of this software. So, as far as other devices in the system were concerned, they were speaking to an x86 CPU.&lt;p&gt;Did anyone ever try taking this concept further? Maybe in the context of an industrial embedded computer?&lt;p&gt;I could imagine someone taking e.g. a modern ARM SoC with onboard RAM + eMMC; setting it up to boot into e.g. Bochs to emulate a virtual x86 (CPU + BIOS + other memory-mapped ROMs + platform controller hub + IO controllers + timer chips + TPM + etc — all the stuff on an x86 motherboard) — and then just setting up the SoC&amp;#x27;s GPIO pins to directly expose all the virtual buses of that virtual motherboard. You could then take such a chip, and design a physical &amp;quot;motherboard&amp;quot; for it to sit in, that&amp;#x27;s just a bunch of ports (e.g. PS2) and slots (e.g. ISA or &lt;i&gt;maybe&lt;/i&gt; very slow PCI) routing directly to the SoC&amp;#x27;s GPIO pins.&lt;p&gt;This would be a very effective strategy, I think, for producing low-cost host platforms for the many industrial-automation ISA cards that still exist. So I have a feeling some OEM has at least &lt;i&gt;tried&lt;/i&gt; to do this.&lt;p&gt;Probably there wouldn&amp;#x27;t be enough GPIO pins for most busses — x86 CPUs have &lt;i&gt;tons&lt;/i&gt; of pins compared to almost any other architecture. So I wouldn&amp;#x27;t consider it cheating to feed parallel busses out serially at higher clock rates than those busses natively run at, and then to require the use of an external ser&amp;#x2F;des chip or two to flatten the signals back out. As long as it&amp;#x27;s the SoC itself speaking the protocol and the chip is &amp;quot;dumb&amp;quot;, I think that&amp;#x27;d still count.&lt;p&gt;Also keep in mind that unlike with the Crusoe, an &amp;quot;x86-on-ARM SoC&amp;quot; &lt;i&gt;wouldn&amp;#x27;t&lt;/i&gt; need to have GPIO fast and wide enough to talk to external DRAM — as any memory could be internal to the SoC without breaking the contract. So the main constraint bottlenecking the Crusoe&amp;#x27;s CPU performance, wouldn&amp;#x27;t apply here. This thing &lt;i&gt;could&lt;/i&gt; actually perform decently well — possibly well enough to run hard-realtime industrial control software coded in the 1990s, and to speak to ISA cards built in the 1990s. Which is all it would need to be able to do, for the obvious use-case.</text></item></parent_chain></comment><story><title>Non-PC compatible x86 computers (2007)</title><url>https://lproven.livejournal.com/189791.html</url></story>
<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>yjftsjthsd-h</author><text>I&amp;#x27;ve also been interested in a different kind of &amp;quot;PC-compatible non-x86&amp;quot;, as in building a standardized architecture with all the normal pieces and just swapping out the CPU. It is 100% possible to make a machine with an arch64 CPU that boots using UEFI, handles device enumeration like a PC, has the usual buses and everything, lives in an ATX case, and in every way it looks and acts like a regular PC that just happens to have a different CPU.</text><parent_chain><item><author>derefr</author><text>How about the opposite: PC-compatible non-x86 computers?&lt;p&gt;Like how the Transmeta Crusoe was an x86-compatible CPU... but moreso.&lt;p&gt;The Crusoe was a thing marketed as a &amp;quot;CPU&amp;quot;, that was actually internally an SoC (with the CPU inside it being non-x86.) This SoC had its own internal RAM and storage, and booted itself into internal software that then emulated an x86 CPU. All of the &amp;quot;CPU&amp;quot; data pins on the Crusoe SoC, routed to the virtual CPU inputs and outputs of this software. So, as far as other devices in the system were concerned, they were speaking to an x86 CPU.&lt;p&gt;Did anyone ever try taking this concept further? Maybe in the context of an industrial embedded computer?&lt;p&gt;I could imagine someone taking e.g. a modern ARM SoC with onboard RAM + eMMC; setting it up to boot into e.g. Bochs to emulate a virtual x86 (CPU + BIOS + other memory-mapped ROMs + platform controller hub + IO controllers + timer chips + TPM + etc — all the stuff on an x86 motherboard) — and then just setting up the SoC&amp;#x27;s GPIO pins to directly expose all the virtual buses of that virtual motherboard. You could then take such a chip, and design a physical &amp;quot;motherboard&amp;quot; for it to sit in, that&amp;#x27;s just a bunch of ports (e.g. PS2) and slots (e.g. ISA or &lt;i&gt;maybe&lt;/i&gt; very slow PCI) routing directly to the SoC&amp;#x27;s GPIO pins.&lt;p&gt;This would be a very effective strategy, I think, for producing low-cost host platforms for the many industrial-automation ISA cards that still exist. So I have a feeling some OEM has at least &lt;i&gt;tried&lt;/i&gt; to do this.&lt;p&gt;Probably there wouldn&amp;#x27;t be enough GPIO pins for most busses — x86 CPUs have &lt;i&gt;tons&lt;/i&gt; of pins compared to almost any other architecture. So I wouldn&amp;#x27;t consider it cheating to feed parallel busses out serially at higher clock rates than those busses natively run at, and then to require the use of an external ser&amp;#x2F;des chip or two to flatten the signals back out. As long as it&amp;#x27;s the SoC itself speaking the protocol and the chip is &amp;quot;dumb&amp;quot;, I think that&amp;#x27;d still count.&lt;p&gt;Also keep in mind that unlike with the Crusoe, an &amp;quot;x86-on-ARM SoC&amp;quot; &lt;i&gt;wouldn&amp;#x27;t&lt;/i&gt; need to have GPIO fast and wide enough to talk to external DRAM — as any memory could be internal to the SoC without breaking the contract. So the main constraint bottlenecking the Crusoe&amp;#x27;s CPU performance, wouldn&amp;#x27;t apply here. This thing &lt;i&gt;could&lt;/i&gt; actually perform decently well — possibly well enough to run hard-realtime industrial control software coded in the 1990s, and to speak to ISA cards built in the 1990s. Which is all it would need to be able to do, for the obvious use-case.</text></item></parent_chain></comment><story><title>Non-PC compatible x86 computers (2007)</title><url>https://lproven.livejournal.com/189791.html</url></story>