<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>Tuna-Fish</author><text>&amp;gt; (ARM has 16. So does x86-64.)&lt;p&gt;64-bit ARM has 32 GPRs.&lt;p&gt;&amp;gt; Fixed-length instructions instead of variable-length.&lt;p&gt;This is the big legacy of RISC that helps &amp;quot;RISC&amp;quot; cpus most against x86. M1 has 8-wide decode, with very few stages and low power consumption. Nothing like it can be done for an x86 cpu. The way modern x86 handles this is typically with a uop cache. But this costs a lot of power, area and only provides full decode width for a relatively small pool of insns -- 4k on modern Zen, for example.&lt;p&gt;&amp;gt; &amp;gt; One of the key ideas of RISC was to push a lot of heavy lifting over to the compiler. That is still the case. Micro-ops cannot be re-arranged by the compiler for optimal execution.&lt;p&gt;&amp;gt; Modern compilers do use instruction scheduling to optimize execution, and instruction scheduling for microcoded execution is well-understood.&lt;p&gt;Compiler-level instruction scheduling is mostly irrelevant for modern OoO architectures. Most of the time the CPU is operating from mostly full queues, so it will be doing the scheduling from the past 10-~16 instructions. Compilers are mostly still doing it out of inertia.&lt;p&gt;&amp;gt; &amp;quot;precious silicon&amp;quot;&lt;p&gt;The big difference from that 25 years ago to today is indeed that silicon is now the opposite of precious. We have so many transistors available that we are looking for ways to effectively use more of them, rather than saving precious silicon.</text><parent_chain><item><author>jcranmer</author><text>The better explanation of RISC v CISC is this old discussion from comp.arch: &lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;yarchive.net&amp;#x2F;comp&amp;#x2F;risc_definition.html&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;yarchive.net&amp;#x2F;comp&amp;#x2F;risc_definition.html&lt;/a&gt;&lt;p&gt;In short, the term RISC comes from a new set of architecture designs in the late 80s&amp;#x2F;early 90s. CISC is not so much an architecture design as it is lacking many of the features. The major features that RISC adds are:&lt;p&gt;* Avoid complex operations, which may include things such as multiply and divide. (Although note that &amp;quot;modern&amp;quot; RISCs have these nowadays).&lt;p&gt;* More registers (32 registers instead of 8 or 16). (ARM has 16. So does x86-64.)&lt;p&gt;* Fixed-length instructions instead of variable-length.&lt;p&gt;* Avoid indirect memory references or a lot of memory accessing types (note that x86 also does this).&lt;p&gt;Functionally speaking, x86 itself is pretty close to RISC, especially in terms of how the operations themselves need to be implemented. The implementation benefits of RISC (especially in allowing pipelining) are largely applicable to x86 as well, since x86 really skips the problematic instructions that other CISCs have.&lt;p&gt;&amp;gt; One of the key ideas of RISC was to push a lot of heavy lifting over to the compiler. That is still the case. Micro-ops cannot be re-arranged by the compiler for optimal execution.&lt;p&gt;Modern compilers do use instruction scheduling to optimize execution, and instruction scheduling for microcoded execution is well-understood.&lt;p&gt;&amp;gt; Time is more critical when running micro-ops than when compiling. It is an obvious advantage in making it possible for advance compiler to rearrange code rather than relying on precious silicon to do it.&lt;p&gt;All modern high-performance chips are out-of-order execution, because some instructions (especially memory!) take longer than others to execute. The &amp;quot;precious silicon&amp;quot; is silicon that&amp;#x27;s already been used for that reason, whether RISC or CISC.</text></item></parent_chain></comment><story><title>What do RISC and CISC mean in 2020?</title><url>https://erik-engheim.medium.com/what-does-risc-and-cisc-mean-in-2020-7b4d42c9a9de</url></story>
<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>fanf2</author><text>I am also a fan of John Mashey’s analysis that you linked to! The key thing is that he counts things like instruction formats, addressing modes, memory ops per instruction, registers, and so on. There is a clear separation in the numbers between the RISCs and the CISCs.&lt;p&gt;What stuck out to me when I first read it 25 years ago is that the ARM is the least RISCy RISC, and x86 is the least CISCy CISC. At that time the Pentium was killing the 68060 and many of the RISCs, and it seemed clear that x86 had a big advantage in the relatively small number of memory ops per instruction.</text><parent_chain><item><author>jcranmer</author><text>The better explanation of RISC v CISC is this old discussion from comp.arch: &lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;yarchive.net&amp;#x2F;comp&amp;#x2F;risc_definition.html&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;yarchive.net&amp;#x2F;comp&amp;#x2F;risc_definition.html&lt;/a&gt;&lt;p&gt;In short, the term RISC comes from a new set of architecture designs in the late 80s&amp;#x2F;early 90s. CISC is not so much an architecture design as it is lacking many of the features. The major features that RISC adds are:&lt;p&gt;* Avoid complex operations, which may include things such as multiply and divide. (Although note that &amp;quot;modern&amp;quot; RISCs have these nowadays).&lt;p&gt;* More registers (32 registers instead of 8 or 16). (ARM has 16. So does x86-64.)&lt;p&gt;* Fixed-length instructions instead of variable-length.&lt;p&gt;* Avoid indirect memory references or a lot of memory accessing types (note that x86 also does this).&lt;p&gt;Functionally speaking, x86 itself is pretty close to RISC, especially in terms of how the operations themselves need to be implemented. The implementation benefits of RISC (especially in allowing pipelining) are largely applicable to x86 as well, since x86 really skips the problematic instructions that other CISCs have.&lt;p&gt;&amp;gt; One of the key ideas of RISC was to push a lot of heavy lifting over to the compiler. That is still the case. Micro-ops cannot be re-arranged by the compiler for optimal execution.&lt;p&gt;Modern compilers do use instruction scheduling to optimize execution, and instruction scheduling for microcoded execution is well-understood.&lt;p&gt;&amp;gt; Time is more critical when running micro-ops than when compiling. It is an obvious advantage in making it possible for advance compiler to rearrange code rather than relying on precious silicon to do it.&lt;p&gt;All modern high-performance chips are out-of-order execution, because some instructions (especially memory!) take longer than others to execute. The &amp;quot;precious silicon&amp;quot; is silicon that&amp;#x27;s already been used for that reason, whether RISC or CISC.</text></item></parent_chain></comment><story><title>What do RISC and CISC mean in 2020?</title><url>https://erik-engheim.medium.com/what-does-risc-and-cisc-mean-in-2020-7b4d42c9a9de</url></story>