<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>elihu</author><text>&amp;gt; integrate DRAM on the wafer. This will be painful as we&amp;#x27;re used to being able to simply add DIMM&amp;#x27;s, but the upside is massively higher bandwidth.&lt;p&gt;One way I imagine this working out is that, instead of just replacing the plastic motherboard with a silicon motherboard, you eventually do away with a single monolithic motherboard entirely.  Instead, you have &amp;quot;compute blocks&amp;quot; (comprised of chiplets bonded to a silicon chip, or conventional chips on a conventional circuitboard) that connect with each other via copper or fiber optic point-to-point communication cables, and you can just wire them together arbitrarily to build a complete computer.  Like, you might have a couple blocks that house CPUs, one or two that have memory controllers and DRAM, and maybe one with a PCI bus so you can connect peripherals, and you can connect them all in a ring bus.  You could house these blocks in a case and call it a server, or connect a lot more blocks and call it a cluster.&lt;p&gt;The main advantage of such a setup is that you don&amp;#x27;t have a single component (the motherboard) that determines how much memory, how many processors, or what sort of peripherals you can have.</text><parent_chain><item><author>jabl</author><text>I agree this looks promising, though I&amp;#x27;m not an expert in this field.&lt;p&gt;But the title is a bit, well, overpromising or broad. I don&amp;#x27;t think we&amp;#x27;ll replace traditional motherboards anytime soon (except maybe in smartphones?). Rather, it will be an incremental progress.&lt;p&gt;- first, SoC&amp;#x27;s will be replaced with chiplets&lt;p&gt;- then we&amp;#x27;ll start seeing more and more stuff being integrated on this wafer.&lt;p&gt;- say, instead of a server motherboard with multiple sockets, have all the CPU chiplets on the same wafer and enjoy much better bandwidth than you get with a PCB&lt;p&gt;- integrate DRAM on the wafer. This will be painful as we&amp;#x27;re used to being able to simply add DIMM&amp;#x27;s, but the upside is massively higher bandwidth.&lt;p&gt;The motherboard pcb per se will live for a long time still, if nothing else then as the place to mount all the external connectors (network, display, pcie, usb, power, whatnot).</text></item><item><author>craigjb</author><text>It&amp;#x27;s been fun to see Dr. Subu present this concept and prototypes at several conferences, and the level of integration possible is absolutely insane. I think the industry is definitely moving toward chiplets, such as the latest AMD release.&lt;p&gt;I definitely think we will see more chiplets and more standardization on interfaces between chiplets. The focus will be on how to minimize energy per bit transferred (a big topic in Subu&amp;#x27;s talks) and how to minimize the die area used for inter-chiplet communication. In monolithic silicon, you don&amp;#x27;t have to think about die area, since your parallel wires between sections might just need a register or two along the way. With chiplets, you typically can&amp;#x27;t run wires at that density yet, so you still have some serialization&amp;#x2F;deserialization hardware. But, since it&amp;#x27;s not crossing multiple high inductance solder balls and PCB traces, you can get away with less. Hopefully also you can get away without area-intensive resynchronization, PLLS, etc.&lt;p&gt;I think it will definitely be awhile before this kind of integration is used outside of niche cases though. The costs are just insane. You have to pre-test all manufactured chiplets before integration, and that test engineering is nothing to sneeze at. If you don&amp;#x27;t then you have all kinds of commercials issues about who is liable for the $500k prototype one bad chip broke.&lt;p&gt;On the bright side, I see the chiplet approach benefitting other integration technologies. For example, wafer level and panel level embedded packaging technologies can be used for 1-2um interconnects now. You won&amp;#x27;t get a wafer sized system out of it with any kind of yield, but it&amp;#x27;s probably the direction mobile chips and wearables will go.&lt;p&gt;Anyway, disorganized info-dump over.</text></item></parent_chain></comment><story><title>Goodbye, Motherboard. Hello, Silicon-Interconnect Fabric</title><url>https://spectrum.ieee.org/computing/hardware/goodbye-motherboard-hello-siliconinterconnect-fabric</url></story>
<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>craigjb</author><text>I think the embedded wafer level or &amp;quot;panel&amp;quot; level packaging technologies are the mid-ground. These technologies don&amp;#x27;t use expensive silicon, and instead surround the die with cheaper epoxy. Then the interconnects are built on top of that, and can connect multiple die together. Yield and interconnect pitch are the big issues here though, and that&amp;#x27;s why I think you&amp;#x27;re right, that we will see SoCs or mobile systems first, not whole motherboards.&lt;p&gt;With that said, some of these technologies can have a layer of surface mount pads on top. So you have a substrate of epoxy with all your chips and interconnects embedded in it, and then surface mount parts on top. For example, passives, connectors, etc. It would look almost like a motherboard, but with all the chips inside. Of course, for cost and yield reasons, this will be for mobile devices only at first.</text><parent_chain><item><author>jabl</author><text>I agree this looks promising, though I&amp;#x27;m not an expert in this field.&lt;p&gt;But the title is a bit, well, overpromising or broad. I don&amp;#x27;t think we&amp;#x27;ll replace traditional motherboards anytime soon (except maybe in smartphones?). Rather, it will be an incremental progress.&lt;p&gt;- first, SoC&amp;#x27;s will be replaced with chiplets&lt;p&gt;- then we&amp;#x27;ll start seeing more and more stuff being integrated on this wafer.&lt;p&gt;- say, instead of a server motherboard with multiple sockets, have all the CPU chiplets on the same wafer and enjoy much better bandwidth than you get with a PCB&lt;p&gt;- integrate DRAM on the wafer. This will be painful as we&amp;#x27;re used to being able to simply add DIMM&amp;#x27;s, but the upside is massively higher bandwidth.&lt;p&gt;The motherboard pcb per se will live for a long time still, if nothing else then as the place to mount all the external connectors (network, display, pcie, usb, power, whatnot).</text></item><item><author>craigjb</author><text>It&amp;#x27;s been fun to see Dr. Subu present this concept and prototypes at several conferences, and the level of integration possible is absolutely insane. I think the industry is definitely moving toward chiplets, such as the latest AMD release.&lt;p&gt;I definitely think we will see more chiplets and more standardization on interfaces between chiplets. The focus will be on how to minimize energy per bit transferred (a big topic in Subu&amp;#x27;s talks) and how to minimize the die area used for inter-chiplet communication. In monolithic silicon, you don&amp;#x27;t have to think about die area, since your parallel wires between sections might just need a register or two along the way. With chiplets, you typically can&amp;#x27;t run wires at that density yet, so you still have some serialization&amp;#x2F;deserialization hardware. But, since it&amp;#x27;s not crossing multiple high inductance solder balls and PCB traces, you can get away with less. Hopefully also you can get away without area-intensive resynchronization, PLLS, etc.&lt;p&gt;I think it will definitely be awhile before this kind of integration is used outside of niche cases though. The costs are just insane. You have to pre-test all manufactured chiplets before integration, and that test engineering is nothing to sneeze at. If you don&amp;#x27;t then you have all kinds of commercials issues about who is liable for the $500k prototype one bad chip broke.&lt;p&gt;On the bright side, I see the chiplet approach benefitting other integration technologies. For example, wafer level and panel level embedded packaging technologies can be used for 1-2um interconnects now. You won&amp;#x27;t get a wafer sized system out of it with any kind of yield, but it&amp;#x27;s probably the direction mobile chips and wearables will go.&lt;p&gt;Anyway, disorganized info-dump over.</text></item></parent_chain></comment><story><title>Goodbye, Motherboard. Hello, Silicon-Interconnect Fabric</title><url>https://spectrum.ieee.org/computing/hardware/goodbye-motherboard-hello-siliconinterconnect-fabric</url></story>