<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>amirhirsch</author><text>here&amp;#x27;s a few good reasons why it&amp;#x27;s hard to make easy-to-use vendor-neutral FPGA tools:&lt;p&gt;- all the devices&amp;#x2F;bitstream formats are proprietary with little or no documentation of the logic blocks or programmable interconnect structures. it is probably technically easier to build a new FPGA from scratch and design tools for that, than to reverse engineer existing chips [1]&lt;p&gt;- there is very little cross-compatibility between vendor products (a 4-lut here, a 6-lut there, some carry-chain logic here, a DSP block there)&lt;p&gt;- all the optimizations (synthesis, place-and-route) are NP-hard problems&lt;p&gt;- sequential imperative (C-like) thinking is not the correct way to make parallel systems&lt;p&gt;- the FPGA vendors compete on tools and offer their software for free to push hardware. hard for an independent vendor to compete.&lt;p&gt;[1] some reverse engineering efforts exist. see &amp;quot;From the bitstream to the netlist&amp;quot; &lt;a href=&quot;http:&amp;#x2F;&amp;#x2F;citeseerx.ist.psu.edu&amp;#x2F;viewdoc&amp;#x2F;download?doi=10.1.1.117.6043&amp;amp;rep=rep1&amp;amp;type=pdf&quot; rel=&quot;nofollow&quot;&gt;http:&amp;#x2F;&amp;#x2F;citeseerx.ist.psu.edu&amp;#x2F;viewdoc&amp;#x2F;download?doi=10.1.1.117...&lt;/a&gt; &amp;#x2F; &lt;a href=&quot;http:&amp;#x2F;&amp;#x2F;code.google.com&amp;#x2F;p&amp;#x2F;debit&amp;#x2F;&quot; rel=&quot;nofollow&quot;&gt;http:&amp;#x2F;&amp;#x2F;code.google.com&amp;#x2F;p&amp;#x2F;debit&amp;#x2F;&lt;/a&gt;</text><parent_chain><item><author>_yosefk</author><text>It&amp;#x27;s genuinely complicated; if Xilinx could disrupt Altera by making easier-to-use tools, it would. (In fact it tries with AutoESL.)&lt;p&gt;I hope to explain why FPGA tooling is intrinsically hard in my next write-up.</text></item><item><author>alok-g</author><text>I seriously want someone to disrupt FPGA tooling.&lt;p&gt;In my understanding the tooling for FPGAs has been made purposefully complicated to achieve a lock-in.  The issue is that adoption of new tooling practically requires compatibility with the existing tools from the two key market holders, and I do not think even they themselves could do that anymore.</text></item><item><author>schabernakk</author><text>&amp;gt; I&amp;#x27;m continually surprised by how few software engineers in industry spend the time to pick up HDL and FPGA programming in general.&lt;p&gt;unsufficient tooling? I did some programming with FPGAs once and it seemed the best option I had for programming was proprietary software by altera (quartus). I never got debugging to work or perhaps I did and I didnt understand the stuff it was showing me (I am no hardware guy)&lt;p&gt;My impression was that an eclipse-like ide, perhaps with a built in HW simulator would make things A LOT easier, especially for beginners like me. Of course this could be completely unrealistic and impractical for hardware design in which case I will show myself out.</text></item><item><author>bhb916</author><text>This is a solid article. I&amp;#x27;m continually surprised by how few software engineers in industry spend the time to pick up HDL and FPGA programming in general. In my mind, it is an easy way to expand your breadth of knowledge and make you a touch more valuable to future employers. They say that when all you have is a hammer, everything looks like a nail and I&amp;#x27;m certainly inflicted with that same disease as I see the utility of FPGAs everywhere I look. Prices have plummeted while densities have skyrocketed. A simple $25 part gets you quite a bit of fabric and some $90 eval hardware will give you a sweet little platform. [1]&lt;p&gt;With that said, since I began working with them there have been two &amp;quot;Holy Grails&amp;quot; of FPGA design: (1) Partial Reconfiguration and (2) High Level Synthesis.&lt;p&gt;The first, Partial Reconfiguration, has been more-or-less solved although the tools have a long way to go. One current design I&amp;#x27;m working on loads it&amp;#x27;s PCIe endpoint and DDR3 controller first, establishes communication with the application running on the host PC, then based on user input loads the rest of the FPGA.&lt;p&gt;The second, High Level Synthesis, isn&amp;#x27;t here yet. The goal is to turn a company&amp;#x27;s vast army of software engineers into FPGA programmers overnight. A worthy cause. Every foray into this field has failed (although the jury is still out on Xilinx&amp;#x27;s purchase of autoESL) Honestly, I&amp;#x27;m not sure it will ever get there. The point of optimized, custom hardware is to make use of it. Abstracting it all away seems counterproductive, not to mention very hard.&lt;p&gt;[1] &lt;a href=&quot;http:&amp;#x2F;&amp;#x2F;www.xilinx.com&amp;#x2F;products&amp;#x2F;boards-and-kits&amp;#x2F;AES-S6MB-LX9.htm&quot; rel=&quot;nofollow&quot;&gt;http:&amp;#x2F;&amp;#x2F;www.xilinx.com&amp;#x2F;products&amp;#x2F;boards-and-kits&amp;#x2F;AES-S6MB-LX9....&lt;/a&gt;</text></item></parent_chain></comment><story><title>How FPGAs work, and why you&apos;ll buy one</title><url>http://www.yosefk.com/blog/how-fpgas-work-and-why-youll-buy-one.html</url></story>
<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>mjn</author><text>I&amp;#x27;m waiting for Chuck Moore to release 2kb of Forth that he claims replaces the only parts you need...</text><parent_chain><item><author>_yosefk</author><text>It&amp;#x27;s genuinely complicated; if Xilinx could disrupt Altera by making easier-to-use tools, it would. (In fact it tries with AutoESL.)&lt;p&gt;I hope to explain why FPGA tooling is intrinsically hard in my next write-up.</text></item><item><author>alok-g</author><text>I seriously want someone to disrupt FPGA tooling.&lt;p&gt;In my understanding the tooling for FPGAs has been made purposefully complicated to achieve a lock-in.  The issue is that adoption of new tooling practically requires compatibility with the existing tools from the two key market holders, and I do not think even they themselves could do that anymore.</text></item><item><author>schabernakk</author><text>&amp;gt; I&amp;#x27;m continually surprised by how few software engineers in industry spend the time to pick up HDL and FPGA programming in general.&lt;p&gt;unsufficient tooling? I did some programming with FPGAs once and it seemed the best option I had for programming was proprietary software by altera (quartus). I never got debugging to work or perhaps I did and I didnt understand the stuff it was showing me (I am no hardware guy)&lt;p&gt;My impression was that an eclipse-like ide, perhaps with a built in HW simulator would make things A LOT easier, especially for beginners like me. Of course this could be completely unrealistic and impractical for hardware design in which case I will show myself out.</text></item><item><author>bhb916</author><text>This is a solid article. I&amp;#x27;m continually surprised by how few software engineers in industry spend the time to pick up HDL and FPGA programming in general. In my mind, it is an easy way to expand your breadth of knowledge and make you a touch more valuable to future employers. They say that when all you have is a hammer, everything looks like a nail and I&amp;#x27;m certainly inflicted with that same disease as I see the utility of FPGAs everywhere I look. Prices have plummeted while densities have skyrocketed. A simple $25 part gets you quite a bit of fabric and some $90 eval hardware will give you a sweet little platform. [1]&lt;p&gt;With that said, since I began working with them there have been two &amp;quot;Holy Grails&amp;quot; of FPGA design: (1) Partial Reconfiguration and (2) High Level Synthesis.&lt;p&gt;The first, Partial Reconfiguration, has been more-or-less solved although the tools have a long way to go. One current design I&amp;#x27;m working on loads it&amp;#x27;s PCIe endpoint and DDR3 controller first, establishes communication with the application running on the host PC, then based on user input loads the rest of the FPGA.&lt;p&gt;The second, High Level Synthesis, isn&amp;#x27;t here yet. The goal is to turn a company&amp;#x27;s vast army of software engineers into FPGA programmers overnight. A worthy cause. Every foray into this field has failed (although the jury is still out on Xilinx&amp;#x27;s purchase of autoESL) Honestly, I&amp;#x27;m not sure it will ever get there. The point of optimized, custom hardware is to make use of it. Abstracting it all away seems counterproductive, not to mention very hard.&lt;p&gt;[1] &lt;a href=&quot;http:&amp;#x2F;&amp;#x2F;www.xilinx.com&amp;#x2F;products&amp;#x2F;boards-and-kits&amp;#x2F;AES-S6MB-LX9.htm&quot; rel=&quot;nofollow&quot;&gt;http:&amp;#x2F;&amp;#x2F;www.xilinx.com&amp;#x2F;products&amp;#x2F;boards-and-kits&amp;#x2F;AES-S6MB-LX9....&lt;/a&gt;</text></item></parent_chain></comment><story><title>How FPGAs work, and why you&apos;ll buy one</title><url>http://www.yosefk.com/blog/how-fpgas-work-and-why-youll-buy-one.html</url></story>