<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>dgacmu</author><text>The article is conflating three separate issues:&lt;p&gt;(1) The amount of compute and&amp;#x2F;or data motion that can be achieved with a single instruction. This is really about amortizing the cost of decode and allowing the pipeline to be kept full by producing a lot of work from a single instruction.&lt;p&gt;(2) efficiency gains from vector processing. This both amortizes the cost of decode and produces the amount of control circuitry relative to the number of ALUs --&amp;gt; more flops&amp;#x2F;area. it also generally favors larger sequential memory accesses which is good for bandwidth.&lt;p&gt;(3) extracting parallelism from the instruction stream. The VLIW debate is about whether that should be done by the CPU itself, e.g., in the form of out-of-order execution, or whether it should be handled by the compiler. VLIW allows the compiler to do this work, which keeps the CPU simpler.&lt;p&gt;It&amp;#x27;s been clear for several years that larger vectors are a win, and that&amp;#x27;s been happening in the Intel and arm space, not to mention GPU.  The VLIW debate is less clear, and has been going back and forth.  I think that we have been doing a better job of getting a handle on when instruction complexity and diversity is beneficial versus not - remember that the initial RISC proposal was in contrast to the PDP instruction set, which was kind of ridiculously over specialized for the technology of the time.</text><parent_chain></parent_chain></comment><story><title>RISC Is Unscalable</title><url>https://blackhole12.com/blog/risc-is-fundamentally-unscalable/</url></story>
<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>teton_ferb</author><text>The author fundamentally misunderstands what RISC is, what CISC is, what SIMD is and what VLIW is apart from misunderstanding every major computer architecture concept&lt;p&gt;RISC was invented as an alternative approach in an era when processors had really complex instructions, with an idea that high level languages could be efficiently compiled to them and assembly programmers would be efficient if they can do many things with one instruction. RISC philosophy was to make simpler instructions, let compilers figure out how to map high level languages to simple instructions, and therefore fit the processor on one die (yes, &amp;quot;processors&amp;quot; used to be several chips) and therefore run it at high clock speeds. RISC is not a dogma, it is a design philosophy.&lt;p&gt;On top of that exception handling in complex instructions is hard. Implementing complex instructions in hardware consumes considerable design and validation effort. RISC has won for these reasons.&lt;p&gt;Some things have changed, we can fit really complicated processors on a single die. Memory access is the bottleneck. The downsides of RISC in this reality is well known: It takes many more instructions to do the same thing, which means instruction cache is used inefficiently (anyone remember the THUMB instruction set of ARM?). It might be useful to add application-specific hardware acceleration features, because we now have the transistors to do it. How does that make RISC unscalable?&lt;p&gt;Many CISC machines (eg Intel&amp;#x27;s) are CISC in name only. The instructions are translated to micro-ops in the hardware. The micro-ops and the hardware itself, is RISC.&lt;p&gt;Register re-naming was invented to ensure that we enjoy the benefits of improvements in hardware without having to recompile. Let us assume you have a processor with 16 registers. You compiled software for it. Now we can put in 32. What do you do? Recompile everything out there or implement register re-naming?&lt;p&gt;VLIW failed because they took the stance that if we remove hardware-based scheduling, the extra transistors can be used for computation and cache. Scheduling can be done by compilers anyway. The reason they werent successful is because if a load misses the cache, you wait. Instead of superscalars which would have found other instructions to execute. On top of it, if you had a 4-wide VLIW and then you wanted to make a 8-wide one, you had to recompile. And oh, the &amp;quot;rotating registers&amp;quot; in VLIW is a form of register re-naming.&lt;p&gt;Poorly informed article.</text><parent_chain></parent_chain></comment><story><title>RISC Is Unscalable</title><url>https://blackhole12.com/blog/risc-is-fundamentally-unscalable/</url></story>