<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>Nokinside</author><text>The number 7nm 5nm etc. ceased to refer anything physical after the technology moved on from planar transistors. Now it&amp;#x27;s just  a commercial name for a generation.&lt;p&gt;The most important dimensions are the gate pitch and metal pitch. For TSMC&amp;#x27;s 7nm process they are something like 60 and 40 nm and go down in the future to something like 30 nm and 20 nm in the 2nm process. Fin width might be the closest thing to commercial name.&lt;p&gt;They are not even comparable across companies.  For example, TSMC 7nm process technology has 91 MTr&amp;#x2F;mm², Intel&amp;#x27;s 10 nm prosess technology has 100 MTr&amp;#x2F;mm². Samsung 10nm has 52 MTr&amp;#x2F;mm².   (MTr&amp;#x2F;mm² refers to millions of transistors per mm²).</text><parent_chain><item><author>jmt_</author><text>Can someone ELI5 how TSMC is able to produce sub-7nm chips? I know quantum tunneling and the like becomes an issue at this size. I don&amp;#x27;t have a great physics background so I&amp;#x27;m struggling to find a simple enough explanation for how they are dealing with this. Is it not as big a deal as I may think?</text></item></parent_chain></comment><story><title>TSMC to Mass Produce Breakthrough 2nm Mbcfet Transistors in 2024</title><url>https://wccftech.com/ssmc-mass-produce-2nm-2024/</url></story>
<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>robert_dipaolo</author><text>der8auer recently did a 3 part video on YouTube where he cut up AMD and Intel chips and looked at the transistors with an electron microscope. It sheads some light on meaning (or non-meaning) of the node names. Is also really interesting;&lt;p&gt;&lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;youtu.be&amp;#x2F;uEMDkbF3hu0&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;youtu.be&amp;#x2F;uEMDkbF3hu0&lt;/a&gt;
&lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;youtu.be&amp;#x2F;uXu_1zXOZdY&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;youtu.be&amp;#x2F;uXu_1zXOZdY&lt;/a&gt;
&lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;youtu.be&amp;#x2F;_wAeL3f3iV4&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;youtu.be&amp;#x2F;_wAeL3f3iV4&lt;/a&gt;</text><parent_chain><item><author>jmt_</author><text>Can someone ELI5 how TSMC is able to produce sub-7nm chips? I know quantum tunneling and the like becomes an issue at this size. I don&amp;#x27;t have a great physics background so I&amp;#x27;m struggling to find a simple enough explanation for how they are dealing with this. Is it not as big a deal as I may think?</text></item></parent_chain></comment><story><title>TSMC to Mass Produce Breakthrough 2nm Mbcfet Transistors in 2024</title><url>https://wccftech.com/ssmc-mass-produce-2nm-2024/</url></story>