<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>JoachimS</author><text>Good points. One thing I would like to emphasize is the issue with clocks not arriving everywhere at the same time. Balancing the clock tree over a chip gets harder and harder.&lt;p&gt;But the clock setup, hold times also gets shorter and shorter when the clock frequency goes up. The clock signal will have jitter. The end result is that less and less time of the clock edge is usable to sample the signal into the register.&lt;p&gt;And this in turn put a strain on how well balanced the logic between the registers are. To allow all signals traverse the logic paths through the gates and stabilize in time to be sampled.&lt;p&gt;To add to the complexity, as we move down the geometries, the difference in performance of different transistors becomes relatively larger. One rason for this is that oxide layers consist of (in average) fewer and fewer molecules. When the layer was made up of 100 molecules, 101 or 102 didn&amp;#x27;t really make much of a difference. But when the average is 4 molecule one more or less will have a huge impact on the performance.&lt;p&gt;So controlling variance (clock tree balance, jitter in clock generatiom, imbalances between paths and variance in chip production) becomes ever more problematic and important.</text><parent_chain><item><author>Symmetry</author><text>That was a bit misleading in some ways.  First, in pipelining you&amp;#x27;ll typically measure how long a pipeline steps in FO4s, which is to say the delay required for one transistor to drive 4 other transistors of the same width.  Intel will typically design its pipeline stages to have 16 FO4s of delay.  IBM is more aggressive and will try to work it down to 10.  But of those 10, 2 are there for the latches you added to create the stage and 2 are there to account for the fact that a clock edge doesn&amp;#x27;t arrive everywhere at exactly the same time.  So if you take one of those 16 FO4 Intel stages and cut it in half you won&amp;#x27;t have a two 8 FO4 stages but two 10 FO4 stages.  And since those latch transistors take up space and energy you&amp;#x27;re got some severe diminishing returns problems.&lt;p&gt;One thing that&amp;#x27;s changed as transistors have gotten smaller is that leakage has gotten to be more of a problem.  You used to just worry about active switching power but now you have to balance using higher voltage and lower thresholds to switch your transistors quickly with the leakage power that that will generate.&lt;p&gt;And finally velocity saturation is more of a problem on shorter channels making current go up more linearly with the gate voltage than quadratically.</text></item></parent_chain></comment><story><title>Why has CPU frequency ceased to grow? (2014)</title><url>https://software.intel.com/en-us/blogs/2014/02/19/why-has-cpu-frequency-ceased-to-grow</url></story>
<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>nullbyte</author><text>How do you know all this stuff?</text><parent_chain><item><author>Symmetry</author><text>That was a bit misleading in some ways.  First, in pipelining you&amp;#x27;ll typically measure how long a pipeline steps in FO4s, which is to say the delay required for one transistor to drive 4 other transistors of the same width.  Intel will typically design its pipeline stages to have 16 FO4s of delay.  IBM is more aggressive and will try to work it down to 10.  But of those 10, 2 are there for the latches you added to create the stage and 2 are there to account for the fact that a clock edge doesn&amp;#x27;t arrive everywhere at exactly the same time.  So if you take one of those 16 FO4 Intel stages and cut it in half you won&amp;#x27;t have a two 8 FO4 stages but two 10 FO4 stages.  And since those latch transistors take up space and energy you&amp;#x27;re got some severe diminishing returns problems.&lt;p&gt;One thing that&amp;#x27;s changed as transistors have gotten smaller is that leakage has gotten to be more of a problem.  You used to just worry about active switching power but now you have to balance using higher voltage and lower thresholds to switch your transistors quickly with the leakage power that that will generate.&lt;p&gt;And finally velocity saturation is more of a problem on shorter channels making current go up more linearly with the gate voltage than quadratically.</text></item></parent_chain></comment><story><title>Why has CPU frequency ceased to grow? (2014)</title><url>https://software.intel.com/en-us/blogs/2014/02/19/why-has-cpu-frequency-ceased-to-grow</url></story>