<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>carterschonwald</author><text>The AVX &amp;#x2F; SIMD part of x86 instruction set is probably the most understandable subset to focus on learning! And i&amp;#x27;m very excited about AVX-512&lt;p&gt;I&amp;#x27;ll actually going to be spending some of my time over the next year adding proper SIMD support (including all the shuffles) to the main Haskell compiler, GHC!&lt;p&gt;Theres some really interesting constraints on the SIMD shuffle primops that need some type system cleverness to compile correctly!&lt;p&gt;Namely, you need to know &amp;quot;statically, at code gen time&amp;quot;, the shuffle constants that are given as &amp;quot;immediates&amp;quot; to the instructions! Normal values don&amp;#x27;t quite have the right semantics, and accordingly the simd intrinsics in C compilers kinda lie about the types they expect (ie if you give them a variable of the right type, they&amp;#x27;ll give you an error saying they need an actual constant literal).&lt;p&gt;tl;dr I&amp;#x27;m going to make sure the GHC (and haskell) can support AVX 512 by the time thusly equipped CPUs are made available</text><parent_chain></parent_chain></comment><story><title>Future instruction set: AVX-512</title><url>http://agner.org/optimize/blog/read.php?i=288</url></story>
<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>tachyonbeam</author><text>Seems to me like Intel and AMD aren&amp;#x27;t very forward thinking, adding new instructions and registers every year or two. As if the x86 instruction set wasn&amp;#x27;t bloated enough, now they&amp;#x27;re going to have instructions with 4-byte prefixes, and new registers you can only access with AVX. What&amp;#x27;s next after that, AVX-1024 with 6-byte prefixes? Meanwhile this renders MMX and SSE sort of redundant. Seems to me we might be better served with some kind of vector coprocessor and instructions that can operate directly on large vectors in memory, instead of doubling the size of the vector registers all the time and making x86 an ever harder target to generate efficient code for.&lt;p&gt;Maybe this is another area where ARM can beat x86. Have a better planned out vector instruction set that can be expanded without adding hundreds of new instructions all the time, and more compact machine code.</text><parent_chain></parent_chain></comment><story><title>Future instruction set: AVX-512</title><url>http://agner.org/optimize/blog/read.php?i=288</url></story>