<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>DanWaterworth</author><text>I&amp;#x27;ve recently started writing my own HDL as an embedded language within Idris. The idea behind it is that you can take advantage of the rich type system and you have the option to prove theorems about your circuits to gain confidence in them. There are also bindings to picosat, so that you can automatically prove some properties. Here&amp;#x27;s a snippet of how it looks so far (though things are changing rapidly):&lt;p&gt;&lt;pre&gt;&lt;code&gt;    lt : BoolOperation op =&amp;gt; Vect n v -&amp;gt; Vect n v -&amp;gt; SSA op v v
    lt [] [] = constOp False
    lt (x :: xs) (y :: ys) = do
      nX &amp;lt;- notOp x
      t1 &amp;lt;- andOp [nX, y]
      t2 &amp;lt;- xnorOp x y
      t3 &amp;lt;- lt xs ys
      t4 &amp;lt;- andOp [t2, t3]
      orOp [t1, t4]&lt;/code&gt;&lt;/pre&gt;</text><parent_chain></parent_chain></comment><story><title>MyHDL – Design hardware with Python – Examples</title><url>http://www.myhdl.org/examples/</url></story>
<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>ioseph</author><text>Always great to see new developments in HDLs.&lt;p&gt;It seems there is no synthesis (which is to be expected without vendor support).
With &amp;#x27;limited&amp;#x27; conversion to VHDL&amp;#x2F;Verilog, I wonder how useful  this is for actual implementation.&lt;p&gt;Also from the site I couldn&amp;#x27;t find any mention of higher level functionality such as generics, etc.</text><parent_chain></parent_chain></comment><story><title>MyHDL – Design hardware with Python – Examples</title><url>http://www.myhdl.org/examples/</url></story>