<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>titzer</author><text>Did anyone actually look at the machine code generated here? 0.30ns per value? That is basically 1 cycle. Of course, there is no way that a processor can compute so many dependent instructions in one cycle, simply because they generate so many dependent micro-ops, and every micro-op is at least one cycle to go through an execution unit. So this must mean that either the compiler is unrolling the (benchmarking) loop, or the processor is speculating many loop iterations into the future, so that the latencies can be overlapped and it works out to 1 cycle &lt;i&gt;on average&lt;/i&gt;. 1 cycle &lt;i&gt;on average&lt;/i&gt; for any kind of loop is just flat out suspicious.&lt;p&gt;This requires a lot more digging to understand.&lt;p&gt;Simply put, I don&amp;#x27;t accept the hastily arrived-at conclusion, and wish Daniel would put more effort into investigation in the future. This experiment is a poor example of how to investigate performance on small kernels. You should be looking at the assembly code output by the compiler at this point instead of spitballing.</text><parent_chain></parent_chain></comment><story><title>Apple’s M1 processor and the full 128-bit integer product</title><url>https://lemire.me/blog/2021/03/17/apples-m1-processor-and-the-full-128-bit-integer-product/</url></story>
<instructions>Your goal is to analyze the following comment and estimate how highly it will be upvoted by the Hacker News community.</instructions><comment><author>p1mrx</author><text>RISC-V does this too: &lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;five-embeddev.com&amp;#x2F;riscv-isa-manual&amp;#x2F;latest&amp;#x2F;m.html&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;five-embeddev.com&amp;#x2F;riscv-isa-manual&amp;#x2F;latest&amp;#x2F;m.html&lt;/a&gt;&lt;p&gt;&amp;quot;If both the high and low bits of the same product are required, then the recommended code sequence is [...]. Microarchitectures can then fuse these into a single multiply operation instead of performing two separate multiplies.&amp;quot;</text><parent_chain></parent_chain></comment><story><title>Apple’s M1 processor and the full 128-bit integer product</title><url>https://lemire.me/blog/2021/03/17/apples-m1-processor-and-the-full-128-bit-integer-product/</url></story>