New Multi-Scale Simulation Framework for Next-Generation Electronic Design Automation with Application to the Junctionless Transistor
In this paper we present a new multi-scale simulation scheme for next-generation electronic design automation for nano-electronics. The scheme features a combination of the first-principles quantum mechanical calculation, semi-classical semiconductor device simulation, compact model generation and circuit simulation. To demonstrate the feasibility of the proposed scheme, we apply our newly developed quantum mechanics/electromagnetics method to simulate the junctionless transistors. The simulation results are consistent with the experimental measurements and provide new insights on the depletion effect of the hetero-doped gate on the drain current. Based on the calculated I-V curves, a compact model is then constructed for the junctionless transistors. The validity of the compact model is further verified by the transient circuit simulation of an inverter.