	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mmal_component_create_scheduler
_mmal_component_create_scheduler:       ## @mmal_component_create_scheduler
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %rbx
	movq	%rdi, %r12
	movq	_MMAL_ENOMEM@GOTPCREL(%rip), %r14
	movq	(%r14), %r15
	leaq	L_.str(%rip), %rdx
	movl	$1, %edi
	movl	$4, %esi
	callq	_vcos_calloc
	movq	32(%rbx), %rcx
	movq	%rax, 8(%rcx)
	testq	%rax, %rax
	je	LBB0_17
## %bb.1:
	movq	_scheduler_component_destroy@GOTPCREL(%rip), %rax
	movq	%rax, (%rcx)
	movq	_SCHEDULER_INPUT_PORTS_NUM@GOTPCREL(%rip), %r14
	movq	(%r14), %rsi
	movq	_MMAL_PORT_TYPE_INPUT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	movl	$4, %ecx
	callq	_mmal_ports_alloc
	movq	%rax, 24(%rbx)
	testq	%rax, %rax
	je	LBB0_21
## %bb.2:
	movq	%r12, -56(%rbp)                 ## 8-byte Spill
	movq	%r15, -48(%rbp)                 ## 8-byte Spill
	movl	(%r14), %ecx
	movl	%ecx, (%rbx)
	testl	%ecx, %ecx
	je	LBB0_6
## %bb.3:
	movq	_scheduler_port_parameter_set@GOTPCREL(%rip), %r12
	movq	_MMAL_PORT_CAPABILITY_SUPPORTS_EVENT_FORMAT_CHANGE@GOTPCREL(%rip), %r13
	movq	_MMAL_TIME_UNKNOWN@GOTPCREL(%rip), %r15
	xorl	%r14d, %r14d
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movq	_scheduler_port_enable@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	(%rax,%r14,8), %rdx
	movq	8(%rdx), %rdx
	movq	%rcx, 48(%rdx)
	movq	_scheduler_port_disable@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	(%rax,%r14,8), %rdx
	movq	8(%rdx), %rdx
	movq	%rcx, 40(%rdx)
	movq	_scheduler_port_flush@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	(%rax,%r14,8), %rdx
	movq	8(%rdx), %rdx
	movq	%rcx, 32(%rdx)
	movq	_scheduler_port_send@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	(%rax,%r14,8), %rdx
	movq	8(%rdx), %rdx
	movq	%rcx, 24(%rdx)
	movq	_scheduler_input_port_format_commit@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	(%rax,%r14,8), %rdx
	movq	8(%rdx), %rdx
	movl	%ecx, 16(%rdx)
	movq	(%r12), %rcx
	movq	%rcx, 8(%rdx)
	movq	(%rax,%r14,8), %rax
	movl	$1, (%rax)
	movq	$0, 24(%rax)
	movl	(%r13), %ecx
	movl	%ecx, 16(%rax)
	xorl	%eax, %eax
	callq	_mmal_queue_create
	movq	%rax, %rcx
	movq	24(%rbx), %rax
	movq	(%rax,%r14,8), %rdx
	movq	8(%rdx), %rdx
	movq	(%rdx), %rdx
	movq	%rcx, 8(%rdx)
	movq	(%rax,%r14,8), %rcx
	movq	8(%rcx), %rcx
	movq	(%rcx), %rcx
	cmpq	$0, 8(%rcx)
	je	LBB0_20
## %bb.5:                               ##   in Loop: Header=BB0_4 Depth=1
	movl	(%r15), %edx
	movl	%edx, (%rcx)
	incq	%r14
	movl	(%rbx), %ecx
	cmpq	%rcx, %r14
	jb	LBB0_4
LBB0_6:
	leaq	L_.str.1(%rip), %rsi
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_strstr
	movq	%rax, %r15
	testq	%rax, %rax
	je	LBB0_8
## %bb.7:
	leaq	L_.str.2(%rip), %rdi
	callq	_LOG_TRACE
LBB0_8:
	movq	_SCHEDULER_OUTPUT_PORTS_NUM@GOTPCREL(%rip), %r14
	movq	(%r14), %rsi
	movq	_MMAL_PORT_TYPE_OUTPUT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	movl	$4, %ecx
	callq	_mmal_ports_alloc
	movq	%rax, 16(%rbx)
	testq	%rax, %rax
	je	LBB0_20
## %bb.9:
	movl	(%r14), %ecx
	movl	%ecx, 4(%rbx)
	testl	%ecx, %ecx
	je	LBB0_15
## %bb.10:
	movq	_scheduler_output_port_format_commit@GOTPCREL(%rip), %r13
	movq	_scheduler_port_parameter_set@GOTPCREL(%rip), %r14
	xorl	%r12d, %r12d
	.p2align	4, 0x90
LBB0_11:                                ## =>This Inner Loop Header: Depth=1
	movq	_scheduler_port_enable@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	(%rax,%r12,8), %rdx
	movq	8(%rdx), %rdx
	movq	%rcx, 48(%rdx)
	movq	_scheduler_port_disable@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	(%rax,%r12,8), %rdx
	movq	8(%rdx), %rdx
	movq	%rcx, 40(%rdx)
	movq	_scheduler_port_flush@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	(%rax,%r12,8), %rdx
	movq	8(%rdx), %rdx
	movq	%rcx, 32(%rdx)
	movq	_scheduler_port_send@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	(%rax,%r12,8), %rdx
	movq	8(%rdx), %rdx
	movq	%rcx, 24(%rdx)
	movl	(%r13), %ecx
	movq	(%rax,%r12,8), %rdx
	movq	8(%rdx), %rdx
	movl	%ecx, 16(%rdx)
	movq	(%r14), %rcx
	movq	%rcx, 8(%rdx)
	movq	(%rax,%r12,8), %rax
	movl	$1, (%rax)
	movq	$0, 24(%rax)
	movl	$0, %ecx
	testq	%r15, %r15
	jne	LBB0_13
## %bb.12:                              ##   in Loop: Header=BB0_11 Depth=1
	movq	_MMAL_PORT_CAPABILITY_PASSTHROUGH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_13:                                ##   in Loop: Header=BB0_11 Depth=1
	movl	%ecx, 16(%rax)
	xorl	%eax, %eax
	callq	_mmal_queue_create
	movq	%rax, %rcx
	movq	16(%rbx), %rax
	movq	(%rax,%r12,8), %rdx
	movq	8(%rdx), %rdx
	movq	(%rdx), %rdx
	movq	%rcx, (%rdx)
	movq	(%rax,%r12,8), %rcx
	movq	8(%rcx), %rcx
	movq	(%rcx), %rcx
	cmpq	$0, (%rcx)
	je	LBB0_20
## %bb.14:                              ##   in Loop: Header=BB0_11 Depth=1
	incq	%r12
	movl	4(%rbx), %ecx
	cmpq	%rcx, %r12
	jb	LBB0_11
LBB0_15:
	movq	_SCHEDULER_CLOCK_PORTS_NUM@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	callq	_mmal_ports_clock_alloc
	movl	%eax, 12(%rbx)
	testl	%eax, %eax
	movq	-48(%rbp), %r15                 ## 8-byte Reload
	je	LBB0_21
## %bb.16:
	movl	(%r14), %eax
	movl	%eax, 8(%rbx)
	movq	_scheduler_component_action@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_mmal_component_action_register
	movq	%rax, %r15
	movq	_MMAL_SUCCESS@GOTPCREL(%rip), %rax
	cmpq	(%rax), %r15
	jne	LBB0_21
	jmp	LBB0_22
LBB0_17:
	movq	(%r14), %r15
	jmp	LBB0_22
LBB0_20:
	movq	-48(%rbp), %r15                 ## 8-byte Reload
LBB0_21:
	movq	%rbx, %rdi
	callq	_scheduler_component_destroy
LBB0_22:
	movq	%r15, %rax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MMAL_ENOMEM,8,3                ## @MMAL_ENOMEM
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"mmal module"

	.comm	_SCHEDULER_INPUT_PORTS_NUM,8,3  ## @SCHEDULER_INPUT_PORTS_NUM
	.comm	_MMAL_PORT_TYPE_INPUT,4,2       ## @MMAL_PORT_TYPE_INPUT
	.comm	_scheduler_port_enable,8,3      ## @scheduler_port_enable
	.comm	_scheduler_port_disable,8,3     ## @scheduler_port_disable
	.comm	_scheduler_port_flush,8,3       ## @scheduler_port_flush
	.comm	_scheduler_port_send,8,3        ## @scheduler_port_send
	.comm	_scheduler_input_port_format_commit,4,2 ## @scheduler_input_port_format_commit
	.comm	_scheduler_port_parameter_set,8,3 ## @scheduler_port_parameter_set
	.comm	_MMAL_PORT_CAPABILITY_SUPPORTS_EVENT_FORMAT_CHANGE,4,2 ## @MMAL_PORT_CAPABILITY_SUPPORTS_EVENT_FORMAT_CHANGE
	.comm	_MMAL_TIME_UNKNOWN,4,2          ## @MMAL_TIME_UNKNOWN
L_.str.1:                               ## @.str.1
	.asciz	".copy"

L_.str.2:                               ## @.str.2
	.asciz	"disable passthrough on output ports"

	.comm	_SCHEDULER_OUTPUT_PORTS_NUM,8,3 ## @SCHEDULER_OUTPUT_PORTS_NUM
	.comm	_MMAL_PORT_TYPE_OUTPUT,4,2      ## @MMAL_PORT_TYPE_OUTPUT
	.comm	_scheduler_output_port_format_commit,4,2 ## @scheduler_output_port_format_commit
	.comm	_MMAL_PORT_CAPABILITY_PASSTHROUGH,4,2 ## @MMAL_PORT_CAPABILITY_PASSTHROUGH
	.comm	_SCHEDULER_CLOCK_PORTS_NUM,4,2  ## @SCHEDULER_CLOCK_PORTS_NUM
	.comm	_scheduler_component_action,4,2 ## @scheduler_component_action
	.comm	_MMAL_SUCCESS,8,3               ## @MMAL_SUCCESS
	.no_dead_strip	_mmal_component_create_scheduler
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mmal_component_create_scheduler
_mmal_component_create_scheduler:       ; @mmal_component_create_scheduler
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x1
	mov	x22, x0
Lloh0:
	adrp	x20, _MMAL_ENOMEM@GOTPAGE
Lloh1:
	ldr	x20, [x20, _MMAL_ENOMEM@GOTPAGEOFF]
	ldr	x21, [x20]
Lloh2:
	adrp	x2, l_.str@PAGE
Lloh3:
	add	x2, x2, l_.str@PAGEOFF
	mov	w0, #1
	mov	w1, #4
	bl	_vcos_calloc
	ldr	x8, [x19, #32]
	str	x0, [x8, #8]
	cbz	x0, LBB0_15
; %bb.1:
Lloh4:
	adrp	x9, _scheduler_component_destroy@GOTPAGE
Lloh5:
	ldr	x9, [x9, _scheduler_component_destroy@GOTPAGEOFF]
	str	x9, [x8]
Lloh6:
	adrp	x20, _SCHEDULER_INPUT_PORTS_NUM@GOTPAGE
Lloh7:
	ldr	x20, [x20, _SCHEDULER_INPUT_PORTS_NUM@GOTPAGEOFF]
	ldr	x1, [x20]
Lloh8:
	adrp	x8, _MMAL_PORT_TYPE_INPUT@GOTPAGE
Lloh9:
	ldr	x8, [x8, _MMAL_PORT_TYPE_INPUT@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #4
	bl	_mmal_ports_alloc
	str	x0, [x19, #24]
	cbz	x0, LBB0_17
; %bb.2:
	stp	x22, x21, [sp]                  ; 16-byte Folded Spill
	ldr	w8, [x20]
	str	w8, [x19]
	cbz	w8, LBB0_6
; %bb.3:
	mov	x22, #0
Lloh11:
	adrp	x25, _scheduler_port_flush@GOTPAGE
Lloh12:
	ldr	x25, [x25, _scheduler_port_flush@GOTPAGEOFF]
Lloh13:
	adrp	x26, _scheduler_port_send@GOTPAGE
Lloh14:
	ldr	x26, [x26, _scheduler_port_send@GOTPAGEOFF]
Lloh15:
	adrp	x27, _scheduler_input_port_format_commit@GOTPAGE
Lloh16:
	ldr	x27, [x27, _scheduler_input_port_format_commit@GOTPAGEOFF]
Lloh17:
	adrp	x28, _scheduler_port_parameter_set@GOTPAGE
Lloh18:
	ldr	x28, [x28, _scheduler_port_parameter_set@GOTPAGEOFF]
	mov	w20, #1
Lloh19:
	adrp	x21, _MMAL_PORT_CAPABILITY_SUPPORTS_EVENT_FORMAT_CHANGE@GOTPAGE
Lloh20:
	ldr	x21, [x21, _MMAL_PORT_CAPABILITY_SUPPORTS_EVENT_FORMAT_CHANGE@GOTPAGEOFF]
Lloh21:
	adrp	x23, _MMAL_TIME_UNKNOWN@GOTPAGE
Lloh22:
	ldr	x23, [x23, _MMAL_TIME_UNKNOWN@GOTPAGEOFF]
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
Lloh23:
	adrp	x8, _scheduler_port_enable@GOTPAGE
Lloh24:
	ldr	x8, [x8, _scheduler_port_enable@GOTPAGEOFF]
Lloh25:
	ldr	x8, [x8]
	lsl	x24, x22, #3
	ldr	x9, [x0, x24]
	ldr	x9, [x9, #8]
	str	x8, [x9, #48]
Lloh26:
	adrp	x8, _scheduler_port_disable@GOTPAGE
Lloh27:
	ldr	x8, [x8, _scheduler_port_disable@GOTPAGEOFF]
Lloh28:
	ldr	x8, [x8]
	ldr	x9, [x0, x24]
	ldr	x9, [x9, #8]
	str	x8, [x9, #40]
	ldr	x8, [x25]
	ldr	x9, [x0, x24]
	ldr	x9, [x9, #8]
	str	x8, [x9, #32]
	ldr	x8, [x26]
	ldr	x9, [x0, x24]
	ldr	x9, [x9, #8]
	str	x8, [x9, #24]
	ldr	w8, [x27]
	ldr	x9, [x0, x24]
	ldr	x9, [x9, #8]
	str	w8, [x9, #16]
	ldr	x8, [x28]
	str	x8, [x9, #8]
	ldr	x8, [x0, x24]
	str	w20, [x8]
	str	xzr, [x8, #24]
	ldr	w9, [x21]
	str	w9, [x8, #16]
	bl	_mmal_queue_create
	mov	x8, x0
	ldr	x0, [x19, #24]
	ldr	x9, [x0, x24]
	ldr	x9, [x9, #8]
	ldr	x9, [x9]
	str	x8, [x9, #8]
	ldr	x8, [x0, x24]
	ldr	x8, [x8, #8]
	ldr	x8, [x8]
	ldr	x9, [x8, #8]
	cbz	x9, LBB0_16
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	ldr	w9, [x23]
	str	w9, [x8]
	add	x22, x22, #1
	ldr	w8, [x19]
	cmp	x22, x8
	b.lo	LBB0_4
LBB0_6:
Lloh29:
	adrp	x1, l_.str.1@PAGE
Lloh30:
	add	x1, x1, l_.str.1@PAGEOFF
	ldr	x0, [sp]                        ; 8-byte Folded Reload
	bl	_strstr
	mov	x21, x0
	cbz	x0, LBB0_8
; %bb.7:
Lloh31:
	adrp	x0, l_.str.2@PAGE
Lloh32:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	_LOG_TRACE
LBB0_8:
Lloh33:
	adrp	x20, _SCHEDULER_OUTPUT_PORTS_NUM@GOTPAGE
Lloh34:
	ldr	x20, [x20, _SCHEDULER_OUTPUT_PORTS_NUM@GOTPAGEOFF]
	ldr	x1, [x20]
Lloh35:
	adrp	x8, _MMAL_PORT_TYPE_OUTPUT@GOTPAGE
Lloh36:
	ldr	x8, [x8, _MMAL_PORT_TYPE_OUTPUT@GOTPAGEOFF]
Lloh37:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #4
	bl	_mmal_ports_alloc
	str	x0, [x19, #16]
	cbz	x0, LBB0_16
; %bb.9:
	ldr	w8, [x20]
	str	w8, [x19, #4]
	cbz	w8, LBB0_13
; %bb.10:
	mov	x22, #0
Lloh38:
	adrp	x25, _scheduler_port_flush@GOTPAGE
Lloh39:
	ldr	x25, [x25, _scheduler_port_flush@GOTPAGEOFF]
Lloh40:
	adrp	x26, _scheduler_port_send@GOTPAGE
Lloh41:
	ldr	x26, [x26, _scheduler_port_send@GOTPAGEOFF]
Lloh42:
	adrp	x27, _scheduler_output_port_format_commit@GOTPAGE
Lloh43:
	ldr	x27, [x27, _scheduler_output_port_format_commit@GOTPAGEOFF]
Lloh44:
	adrp	x28, _scheduler_port_parameter_set@GOTPAGE
Lloh45:
	ldr	x28, [x28, _scheduler_port_parameter_set@GOTPAGEOFF]
	mov	w20, #1
Lloh46:
	adrp	x23, _MMAL_PORT_CAPABILITY_PASSTHROUGH@GOTPAGE
Lloh47:
	ldr	x23, [x23, _MMAL_PORT_CAPABILITY_PASSTHROUGH@GOTPAGEOFF]
LBB0_11:                                ; =>This Inner Loop Header: Depth=1
Lloh48:
	adrp	x8, _scheduler_port_enable@GOTPAGE
Lloh49:
	ldr	x8, [x8, _scheduler_port_enable@GOTPAGEOFF]
Lloh50:
	ldr	x8, [x8]
	lsl	x24, x22, #3
	ldr	x9, [x0, x24]
	ldr	x9, [x9, #8]
	str	x8, [x9, #48]
Lloh51:
	adrp	x8, _scheduler_port_disable@GOTPAGE
Lloh52:
	ldr	x8, [x8, _scheduler_port_disable@GOTPAGEOFF]
Lloh53:
	ldr	x8, [x8]
	ldr	x9, [x0, x24]
	ldr	x9, [x9, #8]
	str	x8, [x9, #40]
	ldr	x8, [x25]
	ldr	x9, [x0, x24]
	ldr	x9, [x9, #8]
	str	x8, [x9, #32]
	ldr	x8, [x0, x24]
	ldr	x9, [x26]
	ldr	x8, [x8, #8]
	str	x9, [x8, #24]
	ldr	w8, [x27]
	ldr	x9, [x0, x24]
	ldr	x9, [x9, #8]
	str	w8, [x9, #16]
	ldr	x8, [x28]
	str	x8, [x9, #8]
	ldr	x8, [x0, x24]
	str	w20, [x8]
	str	xzr, [x8, #24]
	ldr	w9, [x23]
	cmp	x21, #0
	csel	w9, w9, wzr, eq
	str	w9, [x8, #16]
	bl	_mmal_queue_create
	mov	x8, x0
	ldr	x0, [x19, #16]
	ldr	x9, [x0, x24]
	ldr	x9, [x9, #8]
	ldr	x9, [x9]
	str	x8, [x9]
	ldr	x8, [x0, x24]
	ldr	x8, [x8, #8]
	ldr	x8, [x8]
	ldr	x8, [x8]
	cbz	x8, LBB0_16
; %bb.12:                               ;   in Loop: Header=BB0_11 Depth=1
	add	x22, x22, #1
	ldr	w8, [x19, #4]
	cmp	x22, x8
	b.lo	LBB0_11
LBB0_13:
Lloh54:
	adrp	x20, _SCHEDULER_CLOCK_PORTS_NUM@GOTPAGE
Lloh55:
	ldr	x20, [x20, _SCHEDULER_CLOCK_PORTS_NUM@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	mov	w2, #0
	mov	x3, #0
	bl	_mmal_ports_clock_alloc
	str	w0, [x19, #12]
	ldr	x21, [sp, #8]                   ; 8-byte Folded Reload
	cbz	w0, LBB0_17
; %bb.14:
	ldr	w8, [x20]
	str	w8, [x19, #8]
Lloh56:
	adrp	x8, _scheduler_component_action@GOTPAGE
Lloh57:
	ldr	x8, [x8, _scheduler_component_action@GOTPAGEOFF]
Lloh58:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_mmal_component_action_register
	mov	x21, x0
Lloh59:
	adrp	x8, _MMAL_SUCCESS@GOTPAGE
Lloh60:
	ldr	x8, [x8, _MMAL_SUCCESS@GOTPAGEOFF]
Lloh61:
	ldr	x8, [x8]
	cmp	x0, x8
	b.ne	LBB0_17
	b	LBB0_18
LBB0_15:
	ldr	x21, [x20]
	b	LBB0_18
LBB0_16:
	ldr	x21, [sp, #8]                   ; 8-byte Folded Reload
LBB0_17:
	mov	x0, x19
	bl	_scheduler_component_destroy
LBB0_18:
	mov	x0, x21
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpAdd	Lloh29, Lloh30
	.loh AdrpAdd	Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.cfi_endproc
                                        ; -- End function
	.comm	_MMAL_ENOMEM,8,3                ; @MMAL_ENOMEM
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"mmal module"

	.comm	_SCHEDULER_INPUT_PORTS_NUM,8,3  ; @SCHEDULER_INPUT_PORTS_NUM
	.comm	_MMAL_PORT_TYPE_INPUT,4,2       ; @MMAL_PORT_TYPE_INPUT
	.comm	_scheduler_port_enable,8,3      ; @scheduler_port_enable
	.comm	_scheduler_port_disable,8,3     ; @scheduler_port_disable
	.comm	_scheduler_port_flush,8,3       ; @scheduler_port_flush
	.comm	_scheduler_port_send,8,3        ; @scheduler_port_send
	.comm	_scheduler_input_port_format_commit,4,2 ; @scheduler_input_port_format_commit
	.comm	_scheduler_port_parameter_set,8,3 ; @scheduler_port_parameter_set
	.comm	_MMAL_PORT_CAPABILITY_SUPPORTS_EVENT_FORMAT_CHANGE,4,2 ; @MMAL_PORT_CAPABILITY_SUPPORTS_EVENT_FORMAT_CHANGE
	.comm	_MMAL_TIME_UNKNOWN,4,2          ; @MMAL_TIME_UNKNOWN
l_.str.1:                               ; @.str.1
	.asciz	".copy"

l_.str.2:                               ; @.str.2
	.asciz	"disable passthrough on output ports"

	.comm	_SCHEDULER_OUTPUT_PORTS_NUM,8,3 ; @SCHEDULER_OUTPUT_PORTS_NUM
	.comm	_MMAL_PORT_TYPE_OUTPUT,4,2      ; @MMAL_PORT_TYPE_OUTPUT
	.comm	_scheduler_output_port_format_commit,4,2 ; @scheduler_output_port_format_commit
	.comm	_MMAL_PORT_CAPABILITY_PASSTHROUGH,4,2 ; @MMAL_PORT_CAPABILITY_PASSTHROUGH
	.comm	_SCHEDULER_CLOCK_PORTS_NUM,4,2  ; @SCHEDULER_CLOCK_PORTS_NUM
	.comm	_scheduler_component_action,4,2 ; @scheduler_component_action
	.comm	_MMAL_SUCCESS,8,3               ; @MMAL_SUCCESS
	.no_dead_strip	_mmal_component_create_scheduler
.subsections_via_symbols
