	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function put_obmc
_put_obmc:                              ## @put_obmc
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	(%rsi), %r11
	movq	8(%rsi), %rcx
	movq	16(%rsi), %r10
	movq	24(%rsi), %r8
	movq	32(%rsi), %r9
	movl	(%r10), %esi
	addl	(%rcx), %esi
	addl	%esi, %esi
	movl	(%r11), %eax
	leal	(%rsi,%rax,4), %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, (%rdi)
	movl	4(%rcx), %eax
	addl	%eax, %eax
	movl	4(%r11), %esi
	leal	(%rsi,%rsi,4), %esi
	addl	4(%r10), %eax
	addl	%esi, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 4(%rdi)
	movl	8(%rcx), %eax
	addl	%eax, %eax
	movl	8(%r11), %esi
	leal	(%rsi,%rsi,4), %esi
	addl	8(%r10), %eax
	addl	%esi, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 8(%rdi)
	movl	12(%rcx), %eax
	addl	%eax, %eax
	movl	12(%r11), %esi
	addl	12(%r10), %eax
	leal	(%rsi,%rsi,4), %esi
	addl	%esi, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 12(%rdi)
	movslq	%edx, %rdx
	movl	8(%rcx,%rdx,4), %eax
	addl	%eax, %eax
	movl	8(%r11,%rdx,4), %esi
	leal	(%rsi,%rsi,4), %esi
	addl	8(%r10,%rdx,4), %eax
	addl	%esi, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 8(%rdi,%rdx,4)
	movl	12(%rcx,%rdx,4), %eax
	addl	%eax, %eax
	movl	12(%r11,%rdx,4), %esi
	leal	(%rsi,%rsi,4), %esi
	addl	12(%r10,%rdx,4), %eax
	addl	%esi, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 12(%rdi,%rdx,4)
	movl	16(%rcx), %eax
	movl	16(%r11), %esi
	leal	(%rsi,%rsi,4), %esi
	movl	16(%r8), %ebx
	leal	(%rsi,%rax,2), %eax
	addl	%ebx, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 16(%rdi)
	movl	20(%rcx), %eax
	movl	20(%r11), %esi
	leal	(%rsi,%rsi,4), %esi
	movl	20(%r8), %ebx
	leal	(%rsi,%rax,2), %eax
	addl	%ebx, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 20(%rdi)
	movl	16(%rcx,%rdx,4), %eax
	movl	16(%r11,%rdx,4), %esi
	leal	(%rsi,%rsi,4), %esi
	movl	16(%r8,%rdx,4), %ebx
	leal	(%rsi,%rax,2), %eax
	addl	%ebx, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 16(%rdi,%rdx,4)
	movl	20(%rcx,%rdx,4), %eax
	movl	20(%r11,%rdx,4), %esi
	leal	(%rsi,%rsi,4), %esi
	movl	20(%r8,%rdx,4), %ebx
	leal	(%rsi,%rax,2), %eax
	addl	%ebx, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 20(%rdi,%rdx,4)
	movl	24(%rcx), %eax
	movl	24(%r11), %esi
	leal	(%rsi,%rsi,4), %esi
	movl	24(%r8), %ebx
	leal	(%rsi,%rax,2), %eax
	addl	%ebx, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 24(%rdi)
	movl	28(%r11), %eax
	movl	28(%r8), %esi
	addl	28(%rcx), %esi
	addl	%esi, %esi
	leal	(%rsi,%rax,4), %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 28(%rdi)
	movl	(%r10,%rdx,4), %eax
	addl	%eax, %eax
	movl	(%r11,%rdx,4), %esi
	addl	(%rcx,%rdx,4), %eax
	leal	(%rsi,%rsi,4), %esi
	addl	%esi, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, (%rdi,%rdx,4)
	movl	4(%r10,%rdx,4), %eax
	addl	%eax, %eax
	movl	4(%r11,%rdx,4), %esi
	leal	(%rsi,%rsi,4), %esi
	addl	4(%rcx,%rdx,4), %eax
	addl	%esi, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 4(%rdi,%rdx,4)
	movl	24(%r11,%rdx,4), %eax
	leal	(%rax,%rax,4), %eax
	movl	24(%r8,%rdx,4), %esi
	addl	24(%rcx,%rdx,4), %eax
	leal	(%rax,%rsi,2), %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 24(%rdi,%rdx,4)
	movl	28(%r11,%rdx,4), %eax
	leal	(%rax,%rax,4), %eax
	movl	28(%r8,%rdx,4), %esi
	addl	28(%rcx,%rdx,4), %eax
	leal	(%rax,%rsi,2), %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 28(%rdi,%rdx,4)
	leal	(%rdx,%rdx), %eax
	movslq	%eax, %r14
	movl	(%r10,%r14,4), %eax
	addl	%eax, %eax
	movl	(%r11,%r14,4), %ebx
	addl	(%rcx,%r14,4), %eax
	leal	(%rbx,%rbx,4), %ebx
	addl	%ebx, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, (%rdi,%r14,4)
	leal	(%rdx,%rdx), %eax
	incl	%eax
	cltq
	movl	(%r10,%rax,4), %ebx
	addl	%ebx, %ebx
	movl	(%r11,%rax,4), %esi
	leal	(%rsi,%rsi,4), %esi
	addl	(%rcx,%rax,4), %ebx
	addl	%ebx, %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	leal	(%rdx,%rdx,2), %eax
	cltq
	movl	(%r10,%rax,4), %esi
	addl	%esi, %esi
	movl	(%r11,%rax,4), %ebx
	leal	(%rbx,%rbx,4), %ebx
	addl	(%rcx,%rax,4), %esi
	addl	%ebx, %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	leal	(%rdx,%rdx,2), %eax
	incl	%eax
	cltq
	movl	(%r10,%rax,4), %esi
	addl	%esi, %esi
	movl	(%r11,%rax,4), %ebx
	leal	(%rbx,%rbx,4), %ebx
	addl	(%rcx,%rax,4), %esi
	addl	%ebx, %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	movl	8(%rcx,%r14,4), %eax
	movl	8(%r11,%r14,4), %esi
	leal	(%rsi,%rsi,2), %esi
	addl	8(%r10,%r14,4), %eax
	leal	(%rax,%rsi,2), %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 8(%rdi,%r14,4)
	movl	12(%rcx,%r14,4), %eax
	movl	12(%r11,%r14,4), %esi
	leal	(%rsi,%rsi,2), %esi
	addl	12(%r10,%r14,4), %eax
	leal	(%rax,%rsi,2), %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 12(%rdi,%r14,4)
	leal	(%rdx,%rdx,2), %eax
	addl	$2, %eax
	cltq
	movl	(%rcx,%rax,4), %esi
	movl	(%r11,%rax,4), %ebx
	leal	(%rbx,%rbx,2), %ebx
	addl	(%r10,%rax,4), %esi
	leal	(%rsi,%rbx,2), %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	leal	(%rdx,%rdx,2), %eax
	addl	$3, %eax
	cltq
	movl	(%rcx,%rax,4), %esi
	movl	(%r11,%rax,4), %ebx
	leal	(%rbx,%rbx,2), %ebx
	addl	(%r10,%rax,4), %esi
	leal	(%rsi,%rbx,2), %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	movl	16(%r11,%r14,4), %eax
	leal	(%rax,%rax,2), %eax
	addl	%eax, %eax
	movl	16(%r8,%r14,4), %esi
	addl	16(%rcx,%r14,4), %eax
	addl	%esi, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 16(%rdi,%r14,4)
	movl	20(%r11,%r14,4), %eax
	leal	(%rax,%rax,2), %eax
	addl	%eax, %eax
	movl	20(%r8,%r14,4), %esi
	addl	20(%rcx,%r14,4), %eax
	addl	%esi, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 20(%rdi,%r14,4)
	leal	(%rdx,%rdx,2), %eax
	addl	$4, %eax
	cltq
	movl	(%r11,%rax,4), %esi
	leal	(%rsi,%rsi,2), %esi
	addl	%esi, %esi
	movl	(%r8,%rax,4), %ebx
	addl	(%rcx,%rax,4), %esi
	addl	%ebx, %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	leal	(%rdx,%rdx,2), %eax
	addl	$5, %eax
	cltq
	movl	(%r11,%rax,4), %esi
	leal	(%rsi,%rsi,2), %esi
	addl	%esi, %esi
	movl	(%r8,%rax,4), %ebx
	addl	(%rcx,%rax,4), %esi
	addl	%ebx, %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	movl	24(%r11,%r14,4), %eax
	leal	(%rax,%rax,4), %eax
	movl	24(%r8,%r14,4), %esi
	addl	24(%rcx,%r14,4), %eax
	leal	(%rax,%rsi,2), %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 24(%rdi,%r14,4)
	movl	28(%r11,%r14,4), %eax
	leal	(%rax,%rax,4), %eax
	movl	28(%r8,%r14,4), %esi
	addl	28(%rcx,%r14,4), %eax
	leal	(%rax,%rsi,2), %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 28(%rdi,%r14,4)
	leal	(%rdx,%rdx,2), %eax
	addl	$6, %eax
	cltq
	movl	(%r11,%rax,4), %esi
	leal	(%rsi,%rsi,4), %esi
	movl	(%r8,%rax,4), %ebx
	addl	(%rcx,%rax,4), %esi
	leal	(%rsi,%rbx,2), %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	leal	(%rdx,%rdx,2), %eax
	addl	$7, %eax
	cltq
	movl	(%r11,%rax,4), %esi
	leal	(%rsi,%rsi,4), %esi
	movl	(%r8,%rax,4), %ebx
	addl	(%rcx,%rax,4), %esi
	leal	(%rsi,%rbx,2), %ecx
	addl	$4, %ecx
	sarl	$3, %ecx
	movl	%ecx, (%rdi,%rax,4)
	leal	(,%rdx,4), %eax
	movslq	%eax, %rcx
	movl	(%r10,%rcx,4), %eax
	movl	(%r11,%rcx,4), %esi
	leal	(%rsi,%rsi,4), %esi
	movl	(%r9,%rcx,4), %ebx
	leal	(%rsi,%rax,2), %eax
	addl	%ebx, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, (%rdi,%rcx,4)
	leal	1(,%rdx,4), %eax
	cltq
	movl	(%r10,%rax,4), %r15d
	movl	(%r11,%rax,4), %ebx
	leal	(%rbx,%rbx,4), %ebx
	movl	(%r9,%rax,4), %esi
	leal	(%rbx,%r15,2), %ebx
	addl	%ebx, %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	leal	(%rdx,%rdx,4), %eax
	cltq
	movl	(%r10,%rax,4), %r15d
	movl	(%r11,%rax,4), %ebx
	leal	(%rbx,%rbx,4), %ebx
	movl	(%r9,%rax,4), %esi
	leal	(%rbx,%r15,2), %ebx
	addl	%ebx, %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	leal	(%rdx,%rdx,4), %eax
	incl	%eax
	cltq
	movl	(%r10,%rax,4), %r15d
	movl	(%r11,%rax,4), %ebx
	leal	(%rbx,%rbx,4), %ebx
	movl	(%r9,%rax,4), %esi
	leal	(%rbx,%r15,2), %ebx
	addl	%ebx, %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	leal	2(,%rdx,4), %eax
	cltq
	movl	(%r11,%rax,4), %esi
	leal	(%rsi,%rsi,2), %esi
	addl	%esi, %esi
	addl	(%r10,%rax,4), %esi
	movl	(%r9,%rax,4), %ebx
	addl	%ebx, %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	leal	3(,%rdx,4), %eax
	cltq
	movl	(%r11,%rax,4), %esi
	leal	(%rsi,%rsi,2), %esi
	addl	%esi, %esi
	movl	(%r9,%rax,4), %ebx
	addl	(%r10,%rax,4), %esi
	addl	%ebx, %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	leal	(%rdx,%rdx,4), %eax
	addl	$2, %eax
	cltq
	movl	(%r11,%rax,4), %esi
	leal	(%rsi,%rsi,2), %esi
	addl	%esi, %esi
	movl	(%r9,%rax,4), %ebx
	addl	(%r10,%rax,4), %esi
	addl	%ebx, %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	leal	(%rdx,%rdx,4), %eax
	addl	$3, %eax
	cltq
	movl	(%r11,%rax,4), %esi
	leal	(%rsi,%rsi,2), %esi
	addl	%esi, %esi
	movl	(%r9,%rax,4), %ebx
	addl	(%r10,%rax,4), %esi
	addl	%ebx, %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	movl	16(%r11,%rcx,4), %eax
	leal	(%rax,%rax,2), %eax
	addl	%eax, %eax
	movl	16(%r9,%rcx,4), %esi
	addl	16(%r8,%rcx,4), %eax
	addl	%esi, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 16(%rdi,%rcx,4)
	movl	20(%r11,%rcx,4), %eax
	leal	(%rax,%rax,2), %eax
	addl	%eax, %eax
	movl	20(%r9,%rcx,4), %esi
	addl	20(%r8,%rcx,4), %eax
	addl	%esi, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 20(%rdi,%rcx,4)
	leal	(%rdx,%rdx,4), %eax
	addl	$4, %eax
	cltq
	movl	(%r11,%rax,4), %esi
	leal	(%rsi,%rsi,2), %esi
	addl	%esi, %esi
	movl	(%r9,%rax,4), %ebx
	addl	(%r8,%rax,4), %esi
	addl	%ebx, %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	leal	(%rdx,%rdx,4), %eax
	addl	$5, %eax
	cltq
	movl	(%r11,%rax,4), %esi
	leal	(%rsi,%rsi,2), %esi
	addl	%esi, %esi
	movl	(%r9,%rax,4), %ebx
	addl	(%r8,%rax,4), %esi
	addl	%ebx, %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	movl	24(%r11,%rcx,4), %eax
	leal	(%rax,%rax,4), %eax
	movl	24(%r8,%rcx,4), %esi
	movl	24(%r9,%rcx,4), %ebx
	leal	(%rax,%rsi,2), %eax
	addl	%ebx, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 24(%rdi,%rcx,4)
	movl	28(%r11,%rcx,4), %eax
	leal	(%rax,%rax,4), %eax
	movl	28(%r8,%rcx,4), %esi
	movl	28(%r9,%rcx,4), %ebx
	leal	(%rax,%rsi,2), %eax
	addl	%ebx, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 28(%rdi,%rcx,4)
	leal	(%rdx,%rdx,4), %eax
	addl	$6, %eax
	cltq
	movl	(%r11,%rax,4), %ecx
	leal	(%rcx,%rcx,4), %ecx
	movl	(%r8,%rax,4), %esi
	movl	(%r9,%rax,4), %ebx
	leal	(%rcx,%rsi,2), %ecx
	addl	%ebx, %ecx
	addl	$4, %ecx
	sarl	$3, %ecx
	movl	%ecx, (%rdi,%rax,4)
	leal	(%rdx,%rdx,4), %eax
	addl	$7, %eax
	cltq
	movl	(%r11,%rax,4), %ecx
	leal	(%rcx,%rcx,4), %ecx
	movl	(%r8,%rax,4), %esi
	movl	(%r9,%rax,4), %ebx
	leal	(%rcx,%rsi,2), %ecx
	addl	%ebx, %ecx
	addl	$4, %ecx
	sarl	$3, %ecx
	movl	%ecx, (%rdi,%rax,4)
	leal	(%r14,%r14,2), %eax
	movslq	%eax, %rcx
	movl	(%r10,%rcx,4), %eax
	movl	(%r11,%rcx,4), %esi
	leal	(%rsi,%rsi,4), %esi
	movl	(%r9,%rcx,4), %ebx
	leal	(%rsi,%rax,2), %eax
	addl	%ebx, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, (%rdi,%rcx,4)
	movl	%ecx, %eax
	orl	$1, %eax
	cltq
	movl	(%r10,%rax,4), %r14d
	movl	(%r11,%rax,4), %ebx
	leal	(%rbx,%rbx,4), %ebx
	movl	(%r9,%rax,4), %esi
	leal	(%rbx,%r14,2), %ebx
	addl	%ebx, %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	movl	8(%r11,%rcx,4), %eax
	leal	(%rax,%rax,4), %eax
	movl	8(%r9,%rcx,4), %esi
	addl	8(%r10,%rcx,4), %eax
	leal	(%rax,%rsi,2), %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 8(%rdi,%rcx,4)
	movl	12(%r11,%rcx,4), %eax
	leal	(%rax,%rax,4), %eax
	movl	12(%r9,%rcx,4), %esi
	addl	12(%r10,%rcx,4), %eax
	leal	(%rax,%rsi,2), %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 12(%rdi,%rcx,4)
	leal	(%rdx,%rcx), %eax
	addl	$2, %eax
	cltq
	movl	(%r11,%rax,4), %esi
	leal	(%rsi,%rsi,4), %esi
	movl	(%r9,%rax,4), %ebx
	addl	(%r10,%rax,4), %esi
	leal	(%rsi,%rbx,2), %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	leal	(%rdx,%rcx), %eax
	addl	$3, %eax
	cltq
	movl	(%r11,%rax,4), %esi
	leal	(%rsi,%rsi,4), %esi
	movl	(%r9,%rax,4), %ebx
	addl	(%r10,%rax,4), %esi
	leal	(%rsi,%rbx,2), %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	movl	16(%r11,%rcx,4), %eax
	leal	(%rax,%rax,4), %eax
	movl	16(%r9,%rcx,4), %esi
	addl	16(%r8,%rcx,4), %eax
	leal	(%rax,%rsi,2), %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 16(%rdi,%rcx,4)
	movl	20(%r11,%rcx,4), %eax
	leal	(%rax,%rax,4), %eax
	movl	20(%r9,%rcx,4), %esi
	addl	20(%r8,%rcx,4), %eax
	leal	(%rax,%rsi,2), %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 20(%rdi,%rcx,4)
	leal	(%rdx,%rcx), %eax
	addl	$4, %eax
	cltq
	movl	(%r11,%rax,4), %esi
	leal	(%rsi,%rsi,4), %esi
	movl	(%r9,%rax,4), %ebx
	addl	(%r8,%rax,4), %esi
	leal	(%rsi,%rbx,2), %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	leal	(%rdx,%rcx), %eax
	addl	$5, %eax
	cltq
	movl	(%r11,%rax,4), %esi
	leal	(%rsi,%rsi,4), %esi
	movl	(%r9,%rax,4), %ebx
	addl	(%r8,%rax,4), %esi
	leal	(%rsi,%rbx,2), %esi
	addl	$4, %esi
	sarl	$3, %esi
	movl	%esi, (%rdi,%rax,4)
	movl	24(%r11,%rcx,4), %eax
	leal	(%rax,%rax,4), %eax
	movl	24(%r8,%rcx,4), %esi
	movl	24(%r9,%rcx,4), %ebx
	leal	(%rax,%rsi,2), %eax
	addl	%ebx, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 24(%rdi,%rcx,4)
	movl	28(%r11,%rcx,4), %eax
	leal	(%rax,%rax,4), %eax
	movl	28(%r8,%rcx,4), %esi
	movl	28(%r9,%rcx,4), %ebx
	leal	(%rax,%rsi,2), %eax
	addl	%ebx, %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 28(%rdi,%rcx,4)
	leal	(,%rdx,8), %eax
	subl	%edx, %eax
	movslq	%eax, %rcx
	movl	(%r11,%rcx,4), %eax
	movl	(%r9,%rcx,4), %edx
	addl	(%r10,%rcx,4), %edx
	addl	%edx, %edx
	leal	(%rdx,%rax,4), %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, (%rdi,%rcx,4)
	movl	4(%r11,%rcx,4), %eax
	leal	(%rax,%rax,4), %eax
	addl	4(%r10,%rcx,4), %eax
	movl	4(%r9,%rcx,4), %edx
	leal	(%rax,%rdx,2), %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 4(%rdi,%rcx,4)
	movl	24(%r11,%rcx,4), %eax
	leal	(%rax,%rax,4), %eax
	addl	24(%r8,%rcx,4), %eax
	movl	24(%r9,%rcx,4), %edx
	leal	(%rax,%rdx,2), %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 24(%rdi,%rcx,4)
	movl	28(%r11,%rcx,4), %eax
	movl	28(%r9,%rcx,4), %edx
	addl	28(%r8,%rcx,4), %edx
	addl	%edx, %edx
	leal	(%rdx,%rax,4), %eax
	addl	$4, %eax
	sarl	$3, %eax
	movl	%eax, 28(%rdi,%rcx,4)
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.no_dead_strip	_put_obmc
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function put_obmc
_put_obmc:                              ; @put_obmc
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-16]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 16
	.cfi_offset w19, -8
	.cfi_offset w20, -16
                                        ; kill: def $w2 killed $w2 def $x2
	ldp	x9, x13, [x1]
	ldp	x10, x8, [x1, #16]
	ldr	w11, [x13]
	ldr	w12, [x10]
	add	w11, w12, w11
	ldr	w12, [x9]
	lsl	w12, w12, #2
	add	w11, w12, w11, lsl #1
	add	w11, w11, #4
	asr	w11, w11, #3
	str	w11, [x0]
	ldr	w11, [x13, #4]
	ldr	w12, [x10, #4]
	ldr	w14, [x9, #4]
	add	w14, w14, w14, lsl #2
	add	w11, w12, w11, lsl #1
	add	w11, w11, w14
	add	w11, w11, #4
	asr	w11, w11, #3
	str	w11, [x0, #4]
	ldr	w11, [x13, #8]
	ldr	w12, [x10, #8]
	ldr	w14, [x9, #8]
	add	w14, w14, w14, lsl #2
	add	w11, w12, w11, lsl #1
	add	w11, w11, w14
	add	w11, w11, #4
	asr	w11, w11, #3
	str	w11, [x0, #8]
	ldr	w11, [x13, #12]
	ldr	w12, [x10, #12]
	ldr	w14, [x9, #12]
	add	w14, w14, w14, lsl #2
	add	w11, w12, w11, lsl #1
	add	w11, w11, w14
	add	w11, w11, #4
	asr	w11, w11, #3
	str	w11, [x0, #12]
	sbfiz	x15, x2, #2, #32
	add	x11, x15, #8
	ldr	w12, [x13, x11]
	ldr	w14, [x10, x11]
	ldr	w16, [x9, x11]
	add	w16, w16, w16, lsl #2
	add	w12, w14, w12, lsl #1
	add	w12, w12, w16
	add	w12, w12, #4
	asr	w12, w12, #3
	str	w12, [x0, x11]
	add	x11, x15, #12
	ldr	w12, [x13, x11]
	ldr	w14, [x10, x11]
	ldr	w16, [x9, x11]
	add	w16, w16, w16, lsl #2
	add	w12, w14, w12, lsl #1
	add	w12, w12, w16
	add	w12, w12, #4
	asr	w12, w12, #3
	str	w12, [x0, x11]
	ldr	w11, [x13, #16]
	ldr	w12, [x9, #16]
	add	w12, w12, w12, lsl #2
	ldr	w14, [x8, #16]
	add	w11, w12, w11, lsl #1
	add	w11, w11, w14
	add	w11, w11, #4
	asr	w11, w11, #3
	str	w11, [x0, #16]
	ldr	w11, [x13, #20]
	ldr	w12, [x9, #20]
	add	w12, w12, w12, lsl #2
	ldr	w14, [x8, #20]
	add	w11, w12, w11, lsl #1
	add	w11, w11, w14
	add	w11, w11, #4
	asr	w11, w11, #3
	str	w11, [x0, #20]
	add	x11, x15, #16
	ldr	w12, [x13, x11]
	ldr	w14, [x9, x11]
	add	w14, w14, w14, lsl #2
	ldr	w16, [x8, x11]
	add	w12, w14, w12, lsl #1
	add	w12, w12, w16
	add	w12, w12, #4
	asr	w12, w12, #3
	str	w12, [x0, x11]
	add	x11, x15, #20
	ldr	w12, [x13, x11]
	ldr	w14, [x9, x11]
	add	w14, w14, w14, lsl #2
	ldr	w16, [x8, x11]
	add	w12, w14, w12, lsl #1
	add	w12, w12, w16
	add	w12, w12, #4
	asr	w12, w12, #3
	str	w12, [x0, x11]
	ldr	w11, [x13, #24]
	ldr	w12, [x9, #24]
	add	w12, w12, w12, lsl #2
	ldr	w14, [x8, #24]
	add	w11, w12, w11, lsl #1
	add	w11, w11, w14
	add	w11, w11, #4
	asr	w11, w11, #3
	str	w11, [x0, #24]
	ldr	w11, [x13, #28]
	ldr	w12, [x9, #28]
	lsl	w12, w12, #2
	ldr	w14, [x8, #28]
	add	w11, w14, w11
	add	w11, w12, w11, lsl #1
	add	w11, w11, #4
	asr	w11, w11, #3
	str	w11, [x0, #28]
	ldr	w11, [x13, x15]
	ldr	w12, [x10, x15]
	ldr	w14, [x9, x15]
	add	w14, w14, w14, lsl #2
	add	w11, w11, w12, lsl #1
	add	w11, w11, w14
	add	w11, w11, #4
	asr	w11, w11, #3
	str	w11, [x0, x15]
	add	x11, x15, #4
	ldr	w12, [x13, x11]
	ldr	w14, [x10, x11]
	ldr	w16, [x9, x11]
	add	w16, w16, w16, lsl #2
	add	w12, w12, w14, lsl #1
	add	w12, w12, w16
	add	w12, w12, #4
	asr	w12, w12, #3
	str	w12, [x0, x11]
	add	x11, x15, #24
	ldr	w12, [x13, x11]
	ldr	w14, [x9, x11]
	add	w14, w14, w14, lsl #2
	ldr	w16, [x8, x11]
	add	w12, w12, w14
	add	w12, w12, w16, lsl #1
	add	w12, w12, #4
	asr	w12, w12, #3
	str	w12, [x0, x11]
	add	x11, x15, #28
	ldr	w12, [x13, x11]
	ldr	w14, [x9, x11]
	add	w14, w14, w14, lsl #2
	ldr	w16, [x8, x11]
	add	w12, w12, w14
	add	w12, w12, w16, lsl #1
	add	w12, w12, #4
	asr	w12, w12, #3
	str	w12, [x0, x11]
	sbfiz	x11, x2, #3, #32
	ldr	w12, [x13, x11]
	ldr	w14, [x10, x11]
	ldr	w16, [x9, x11]
	add	w16, w16, w16, lsl #2
	add	w12, w12, w14, lsl #1
	add	w12, w12, w16
	add	w12, w12, #4
	asr	w12, w12, #3
	str	w12, [x0, x11]
	lsl	w12, w2, #1
	sxtw	x17, w12
	orr	x16, x17, #0x1
	lsl	x14, x16, #2
	ldr	w3, [x13, x14]
	sxtw	x12, w2
	ldr	w4, [x10, x14]
	ldr	w5, [x9, x14]
	add	w5, w5, w5, lsl #2
	add	w3, w3, w4, lsl #1
	add	w3, w3, w5
	add	w3, w3, #4
	asr	w3, w3, #3
	str	w3, [x0, x14]
	add	x14, x12, w2, sxtw #1
	lsl	x3, x14, #2
	ldr	w4, [x13, x3]
	ldr	w5, [x10, x3]
	ldr	w6, [x9, x3]
	add	w6, w6, w6, lsl #2
	add	w4, w4, w5, lsl #1
	add	w4, w4, w6
	add	w4, w4, #4
	asr	w4, w4, #3
	str	w4, [x0, x3]
	add	w16, w16, w2
	sbfiz	x16, x16, #2, #32
	ldr	w3, [x13, x16]
	ldr	w4, [x10, x16]
	ldr	w5, [x9, x16]
	add	w5, w5, w5, lsl #2
	add	w3, w3, w4, lsl #1
	add	w3, w3, w5
	add	w3, w3, #4
	asr	w3, w3, #3
	str	w3, [x0, x16]
	add	x3, x17, #2
	lsl	x4, x3, #2
	ldr	w5, [x13, x4]
	ldr	w6, [x10, x4]
	ldr	w7, [x9, x4]
	mov	w16, #6
	add	w5, w5, w6
	madd	w5, w7, w16, w5
	add	w5, w5, #4
	asr	w5, w5, #3
	str	w5, [x0, x4]
	add	x4, x17, #3
	lsl	x5, x4, #2
	ldr	w6, [x13, x5]
	ldr	w7, [x10, x5]
	ldr	w19, [x9, x5]
	add	w6, w6, w7
	madd	w6, w19, w16, w6
	add	w6, w6, #4
	asr	w6, w6, #3
	str	w6, [x0, x5]
	add	w3, w3, w2
	sbfiz	x3, x3, #2, #32
	ldr	w5, [x13, x3]
	ldr	w6, [x10, x3]
	ldr	w7, [x9, x3]
	add	w5, w5, w6
	madd	w5, w7, w16, w5
	add	w5, w5, #4
	asr	w5, w5, #3
	str	w5, [x0, x3]
	add	w3, w4, w2
	sbfiz	x3, x3, #2, #32
	ldr	w4, [x13, x3]
	ldr	w5, [x10, x3]
	ldr	w6, [x9, x3]
	add	w4, w4, w5
	madd	w4, w6, w16, w4
	add	w4, w4, #4
	asr	w4, w4, #3
	str	w4, [x0, x3]
	add	x3, x17, #4
	lsl	x4, x3, #2
	ldr	w5, [x13, x4]
	ldr	w6, [x9, x4]
	ldr	w7, [x8, x4]
	madd	w5, w6, w16, w5
	add	w5, w5, w7
	add	w5, w5, #4
	asr	w5, w5, #3
	str	w5, [x0, x4]
	add	x4, x17, #5
	lsl	x5, x4, #2
	ldr	w6, [x13, x5]
	ldr	w7, [x9, x5]
	ldr	w19, [x8, x5]
	madd	w6, w7, w16, w6
	add	w6, w6, w19
	add	w6, w6, #4
	asr	w6, w6, #3
	str	w6, [x0, x5]
	add	w3, w3, w2
	sbfiz	x3, x3, #2, #32
	ldr	w5, [x13, x3]
	ldr	w6, [x9, x3]
	ldr	w7, [x8, x3]
	madd	w5, w6, w16, w5
	add	w5, w5, w7
	add	w5, w5, #4
	asr	w5, w5, #3
	str	w5, [x0, x3]
	add	w3, w4, w2
	sbfiz	x3, x3, #2, #32
	ldr	w4, [x13, x3]
	ldr	w5, [x9, x3]
	ldr	w6, [x8, x3]
	madd	w4, w5, w16, w4
	add	w4, w4, w6
	add	w4, w4, #4
	asr	w4, w4, #3
	str	w4, [x0, x3]
	add	x3, x17, #6
	lsl	x4, x3, #2
	ldr	w5, [x13, x4]
	ldr	w6, [x9, x4]
	add	w6, w6, w6, lsl #2
	ldr	w7, [x8, x4]
	add	w5, w5, w6
	add	w5, w5, w7, lsl #1
	add	w5, w5, #4
	asr	w5, w5, #3
	str	w5, [x0, x4]
	add	x17, x17, #7
	lsl	x4, x17, #2
	ldr	w5, [x13, x4]
	ldr	w6, [x9, x4]
	add	w6, w6, w6, lsl #2
	ldr	w7, [x8, x4]
	add	w5, w5, w6
	add	w5, w5, w7, lsl #1
	add	w5, w5, #4
	asr	w5, w5, #3
	str	w5, [x0, x4]
	add	w3, w3, w2
	sbfiz	x3, x3, #2, #32
	ldr	w4, [x13, x3]
	ldr	w5, [x9, x3]
	add	w5, w5, w5, lsl #2
	ldr	w6, [x8, x3]
	add	w4, w4, w5
	add	w4, w4, w6, lsl #1
	add	w4, w4, #4
	asr	w4, w4, #3
	str	w4, [x0, x3]
	add	w17, w17, w2
	sbfiz	x17, x17, #2, #32
	ldr	w13, [x13, x17]
	ldr	w3, [x9, x17]
	add	w3, w3, w3, lsl #2
	ldr	w4, [x8, x17]
	add	w13, w13, w3
	add	w13, w13, w4, lsl #1
	add	w13, w13, #4
	asr	w13, w13, #3
	str	w13, [x0, x17]
	sbfiz	x17, x2, #4, #32
	ldr	w3, [x10, x17]
	ldr	x13, [x1, #32]
	ldr	w1, [x9, x17]
	add	w1, w1, w1, lsl #2
	ldr	w4, [x13, x17]
	add	w1, w1, w3, lsl #1
	add	w1, w1, w4
	add	w1, w1, #4
	asr	w1, w1, #3
	str	w1, [x0, x17]
	sxtw	x17, w15
	orr	x1, x17, #0x1
	lsl	x3, x1, #2
	ldr	w4, [x10, x3]
	ldr	w5, [x9, x3]
	add	w5, w5, w5, lsl #2
	ldr	w6, [x13, x3]
	add	w4, w5, w4, lsl #1
	add	w4, w4, w6
	add	w4, w4, #4
	asr	w4, w4, #3
	str	w4, [x0, x3]
	add	x15, x15, x12
	lsl	x15, x15, #2
	ldr	w3, [x10, x15]
	ldr	w4, [x9, x15]
	add	w4, w4, w4, lsl #2
	ldr	w5, [x13, x15]
	add	w3, w4, w3, lsl #1
	add	w3, w3, w5
	add	w3, w3, #4
	asr	w3, w3, #3
	str	w3, [x0, x15]
	add	w15, w1, w2
	sbfiz	x15, x15, #2, #32
	ldr	w1, [x10, x15]
	ldr	w3, [x9, x15]
	add	w3, w3, w3, lsl #2
	ldr	w4, [x13, x15]
	add	w1, w3, w1, lsl #1
	add	w1, w1, w4
	add	w1, w1, #4
	asr	w1, w1, #3
	str	w1, [x0, x15]
	orr	x15, x17, #0x2
	lsl	x1, x15, #2
	ldr	w3, [x10, x1]
	ldr	w4, [x9, x1]
	ldr	w5, [x13, x1]
	madd	w3, w4, w16, w3
	add	w3, w3, w5
	add	w3, w3, #4
	asr	w3, w3, #3
	str	w3, [x0, x1]
	orr	x1, x17, #0x3
	lsl	x3, x1, #2
	ldr	w4, [x10, x3]
	ldr	w5, [x9, x3]
	ldr	w6, [x13, x3]
	madd	w4, w5, w16, w4
	add	w4, w4, w6
	add	w4, w4, #4
	asr	w4, w4, #3
	str	w4, [x0, x3]
	add	w15, w15, w2
	sbfiz	x15, x15, #2, #32
	ldr	w3, [x10, x15]
	ldr	w4, [x9, x15]
	ldr	w5, [x13, x15]
	madd	w3, w4, w16, w3
	add	w3, w3, w5
	add	w3, w3, #4
	asr	w3, w3, #3
	str	w3, [x0, x15]
	add	w15, w1, w2
	sbfiz	x15, x15, #2, #32
	ldr	w1, [x10, x15]
	ldr	w3, [x9, x15]
	ldr	w4, [x13, x15]
	madd	w1, w3, w16, w1
	add	w1, w1, w4
	add	w1, w1, #4
	asr	w1, w1, #3
	str	w1, [x0, x15]
	add	x15, x17, #4
	lsl	x1, x15, #2
	ldr	w3, [x9, x1]
	ldr	w4, [x8, x1]
	ldr	w5, [x13, x1]
	madd	w3, w3, w16, w4
	add	w3, w3, w5
	add	w3, w3, #4
	asr	w3, w3, #3
	str	w3, [x0, x1]
	add	x1, x17, #5
	lsl	x3, x1, #2
	ldr	w4, [x9, x3]
	ldr	w5, [x8, x3]
	ldr	w6, [x13, x3]
	madd	w4, w4, w16, w5
	add	w4, w4, w6
	add	w4, w4, #4
	asr	w4, w4, #3
	str	w4, [x0, x3]
	add	w15, w15, w2
	sbfiz	x15, x15, #2, #32
	ldr	w3, [x9, x15]
	ldr	w4, [x8, x15]
	ldr	w5, [x13, x15]
	madd	w3, w3, w16, w4
	add	w3, w3, w5
	add	w3, w3, #4
	asr	w3, w3, #3
	str	w3, [x0, x15]
	add	w15, w1, w2
	sbfiz	x15, x15, #2, #32
	ldr	w1, [x9, x15]
	ldr	w3, [x8, x15]
	ldr	w4, [x13, x15]
	madd	w16, w1, w16, w3
	add	w16, w16, w4
	add	w16, w16, #4
	asr	w16, w16, #3
	str	w16, [x0, x15]
	add	x15, x17, #6
	lsl	x16, x15, #2
	ldr	w1, [x9, x16]
	add	w1, w1, w1, lsl #2
	ldr	w3, [x8, x16]
	ldr	w4, [x13, x16]
	add	w1, w1, w3, lsl #1
	add	w1, w1, w4
	add	w1, w1, #4
	asr	w1, w1, #3
	str	w1, [x0, x16]
	add	x16, x17, #7
	lsl	x17, x16, #2
	ldr	w1, [x9, x17]
	add	w1, w1, w1, lsl #2
	ldr	w3, [x8, x17]
	ldr	w4, [x13, x17]
	add	w1, w1, w3, lsl #1
	add	w1, w1, w4
	add	w1, w1, #4
	asr	w1, w1, #3
	str	w1, [x0, x17]
	add	w15, w15, w2
	sbfiz	x15, x15, #2, #32
	ldr	w17, [x9, x15]
	add	w17, w17, w17, lsl #2
	ldr	w1, [x8, x15]
	ldr	w3, [x13, x15]
	add	w17, w17, w1, lsl #1
	add	w17, w17, w3
	add	w17, w17, #4
	asr	w17, w17, #3
	str	w17, [x0, x15]
	add	w15, w16, w2
	sbfiz	x15, x15, #2, #32
	ldr	w16, [x9, x15]
	add	w16, w16, w16, lsl #2
	ldr	w17, [x8, x15]
	ldr	w1, [x13, x15]
	add	w16, w16, w17, lsl #1
	add	w16, w16, w1
	add	w16, w16, #4
	asr	w16, w16, #3
	str	w16, [x0, x15]
	lsl	x15, x14, #1
	lsl	x14, x14, #3
	ldr	w16, [x10, x14]
	ldr	w17, [x9, x14]
	add	w17, w17, w17, lsl #2
	ldr	w1, [x13, x14]
	add	w16, w17, w16, lsl #1
	add	w16, w16, w1
	add	w16, w16, #4
	asr	w16, w16, #3
	str	w16, [x0, x14]
	sxtw	x14, w15
	lsr	x15, x14, #1
	mov	w16, #4
	bfi	x16, x15, #3, #61
	ldr	w15, [x10, x16]
	ldr	w17, [x9, x16]
	add	w17, w17, w17, lsl #2
	ldr	w1, [x13, x16]
	add	w15, w17, w15, lsl #1
	add	w15, w15, w1
	add	w15, w15, #4
	asr	w15, w15, #3
	str	w15, [x0, x16]
	add	x15, x14, #2
	lsl	x16, x15, #2
	ldr	w17, [x10, x16]
	ldr	w1, [x9, x16]
	add	w1, w1, w1, lsl #2
	ldr	w3, [x13, x16]
	add	w17, w17, w1
	add	w17, w17, w3, lsl #1
	add	w17, w17, #4
	asr	w17, w17, #3
	str	w17, [x0, x16]
	add	x16, x14, #3
	lsl	x17, x16, #2
	ldr	w1, [x10, x17]
	ldr	w3, [x9, x17]
	add	w3, w3, w3, lsl #2
	ldr	w4, [x13, x17]
	add	w1, w1, w3
	add	w1, w1, w4, lsl #1
	add	w1, w1, #4
	asr	w1, w1, #3
	str	w1, [x0, x17]
	add	w15, w15, w2
	sbfiz	x15, x15, #2, #32
	ldr	w17, [x10, x15]
	ldr	w1, [x9, x15]
	add	w1, w1, w1, lsl #2
	ldr	w3, [x13, x15]
	add	w17, w17, w1
	add	w17, w17, w3, lsl #1
	add	w17, w17, #4
	asr	w17, w17, #3
	str	w17, [x0, x15]
	add	w15, w16, w2
	sbfiz	x15, x15, #2, #32
	ldr	w16, [x10, x15]
	ldr	w17, [x9, x15]
	add	w17, w17, w17, lsl #2
	ldr	w1, [x13, x15]
	add	w16, w16, w17
	add	w16, w16, w1, lsl #1
	add	w16, w16, #4
	asr	w16, w16, #3
	str	w16, [x0, x15]
	add	x15, x14, #4
	lsl	x16, x15, #2
	ldr	w17, [x9, x16]
	add	w17, w17, w17, lsl #2
	ldr	w1, [x8, x16]
	ldr	w3, [x13, x16]
	add	w17, w1, w17
	add	w17, w17, w3, lsl #1
	add	w17, w17, #4
	asr	w17, w17, #3
	str	w17, [x0, x16]
	add	x16, x14, #5
	lsl	x17, x16, #2
	ldr	w1, [x9, x17]
	add	w1, w1, w1, lsl #2
	ldr	w3, [x8, x17]
	ldr	w4, [x13, x17]
	add	w1, w3, w1
	add	w1, w1, w4, lsl #1
	add	w1, w1, #4
	asr	w1, w1, #3
	str	w1, [x0, x17]
	add	w15, w15, w2
	sbfiz	x15, x15, #2, #32
	ldr	w17, [x9, x15]
	add	w17, w17, w17, lsl #2
	ldr	w1, [x8, x15]
	ldr	w3, [x13, x15]
	add	w17, w1, w17
	add	w17, w17, w3, lsl #1
	add	w17, w17, #4
	asr	w17, w17, #3
	str	w17, [x0, x15]
	add	w15, w16, w2
	sbfiz	x15, x15, #2, #32
	ldr	w16, [x9, x15]
	add	w16, w16, w16, lsl #2
	ldr	w17, [x8, x15]
	ldr	w1, [x13, x15]
	add	w16, w17, w16
	add	w16, w16, w1, lsl #1
	add	w16, w16, #4
	asr	w16, w16, #3
	str	w16, [x0, x15]
	lsl	x14, x14, #2
	add	x15, x14, #24
	ldr	w16, [x9, x15]
	add	w16, w16, w16, lsl #2
	ldr	w17, [x8, x15]
	ldr	w1, [x13, x15]
	add	w16, w16, w17, lsl #1
	add	w16, w16, w1
	add	w16, w16, #4
	asr	w16, w16, #3
	str	w16, [x0, x15]
	add	x14, x14, #28
	ldr	w15, [x9, x14]
	add	w15, w15, w15, lsl #2
	ldr	w16, [x8, x14]
	ldr	w17, [x13, x14]
	add	w15, w15, w16, lsl #1
	add	w15, w15, w17
	add	w15, w15, #4
	asr	w15, w15, #3
	str	w15, [x0, x14]
	sub	x11, x11, x12
	lsl	x12, x11, #2
	ldr	w14, [x10, x12]
	ldr	w15, [x9, x12]
	lsl	w15, w15, #2
	ldr	w16, [x13, x12]
	add	w14, w16, w14
	add	w14, w15, w14, lsl #1
	add	w14, w14, #4
	asr	w14, w14, #3
	str	w14, [x0, x12]
	sxtw	x11, w11
	lsl	x11, x11, #2
	add	x12, x11, #4
	ldr	w10, [x10, x12]
	ldr	w14, [x9, x12]
	add	w14, w14, w14, lsl #2
	ldr	w15, [x13, x12]
	add	w10, w10, w14
	add	w10, w10, w15, lsl #1
	add	w10, w10, #4
	asr	w10, w10, #3
	str	w10, [x0, x12]
	add	x10, x11, #24
	ldr	w12, [x9, x10]
	ldr	w14, [x8, x10]
	add	w12, w12, w12, lsl #2
	ldr	w15, [x13, x10]
	add	w12, w14, w12
	add	w12, w12, w15, lsl #1
	add	w12, w12, #4
	asr	w12, w12, #3
	str	w12, [x0, x10]
	add	x10, x11, #28
	ldr	w9, [x9, x10]
	lsl	w9, w9, #2
	ldr	w8, [x8, x10]
	ldr	w11, [x13, x10]
	add	w8, w11, w8
	add	w8, w9, w8, lsl #1
	add	w8, w8, #4
	asr	w8, w8, #3
	str	w8, [x0, x10]
	ldp	x20, x19, [sp], #16             ; 16-byte Folded Reload
	ret
	.cfi_endproc
                                        ; -- End function
	.no_dead_strip	_put_obmc
.subsections_via_symbols
