	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function svq3_luma_dc_dequant_idct_c
_svq3_luma_dc_dequant_idct_c:           ## @svq3_luma_dc_dequant_idct_c
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r10
	movq	_svq3_dequant_coeff@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movslq	%edx, %rcx
	movl	(%rax,%rcx,4), %r12d
	movl	8(%rsi), %eax
	movl	(%rsi), %ecx
	movl	4(%rsi), %edx
	leal	(%rax,%rcx), %ebx
	leal	(%rbx,%rbx,2), %edi
	leal	(%rbx,%rdi,4), %ebx
	subl	%eax, %ecx
	leal	(%rcx,%rcx,2), %eax
	leal	(%rcx,%rax,4), %r13d
	leal	(,%rdx,8), %eax
	subl	%edx, %eax
	movl	12(%rsi), %ecx
	movl	%ecx, %edi
	shll	$4, %edi
	addl	%ecx, %edi
	subl	%edi, %eax
	movl	%edx, %edi
	shll	$4, %edi
	addl	%edx, %edi
	leal	(,%rcx,8), %edx
	subl	%ecx, %edx
	addl	%edi, %edx
	leal	(%rdx,%rbx), %r9d
	leal	(%rax,%r13), %r15d
	subl	%eax, %r13d
	subl	%edx, %ebx
	movq	%rbx, -88(%rbp)                 ## 8-byte Spill
	movl	16(%rsi), %eax
	movl	24(%rsi), %ecx
	leal	(%rcx,%rax), %edx
	leal	(%rdx,%rdx,2), %edi
	leal	(%rdx,%rdi,4), %ebx
	subl	%ecx, %eax
	leal	(%rax,%rax,2), %ecx
	leal	(%rax,%rcx,4), %r14d
	movl	20(%rsi), %eax
	leal	(,%rax,8), %ecx
	subl	%eax, %ecx
	movl	28(%rsi), %edx
	movl	%edx, %edi
	shll	$4, %edi
	addl	%edx, %edi
	subl	%edi, %ecx
	movl	%eax, %edi
	shll	$4, %edi
	addl	%eax, %edi
	leal	(,%rdx,8), %eax
	subl	%edx, %eax
	addl	%edi, %eax
	leal	(%rax,%rbx), %r8d
	leal	(%rcx,%r14), %edx
	movq	%rdx, -56(%rbp)                 ## 8-byte Spill
	subl	%ecx, %r14d
	subl	%eax, %ebx
	movq	%rbx, -80(%rbp)                 ## 8-byte Spill
	movl	32(%rsi), %eax
	movl	40(%rsi), %ecx
	leal	(%rcx,%rax), %edx
	leal	(%rdx,%rdx,2), %edi
	leal	(%rdx,%rdi,4), %edi
	subl	%ecx, %eax
	leal	(%rax,%rax,2), %ecx
	leal	(%rax,%rcx,4), %r11d
	movl	36(%rsi), %eax
	leal	(,%rax,8), %ecx
	subl	%eax, %ecx
	movl	44(%rsi), %edx
	movl	%edx, %ebx
	shll	$4, %ebx
	addl	%edx, %ebx
	subl	%ebx, %ecx
	movl	%eax, %ebx
	shll	$4, %ebx
	addl	%eax, %ebx
	leal	(,%rdx,8), %eax
	subl	%edx, %eax
	addl	%ebx, %eax
	leal	(%rcx,%r11), %edx
	movq	%rdx, -48(%rbp)                 ## 8-byte Spill
	subl	%ecx, %r11d
	movq	%r11, -64(%rbp)                 ## 8-byte Spill
	leal	(%rax,%rdi), %ecx
	subl	%eax, %edi
	movq	%rdi, -72(%rbp)                 ## 8-byte Spill
	movl	48(%rsi), %eax
	movl	56(%rsi), %edx
	leal	(%rdx,%rax), %ebx
	leal	(%rbx,%rbx,2), %edi
	leal	(%rbx,%rdi,4), %r11d
	subl	%edx, %eax
	leal	(%rax,%rax,2), %edx
	leal	(%rax,%rdx,4), %ebx
	movl	52(%rsi), %eax
	leal	(,%rax,8), %edx
	subl	%eax, %edx
	movl	60(%rsi), %esi
	movl	%esi, %edi
	shll	$4, %edi
	addl	%esi, %edi
	subl	%edi, %edx
	movl	%eax, %edi
	shll	$4, %edi
	addl	%eax, %edi
	leal	(,%rsi,8), %eax
	subl	%esi, %eax
	addl	%edi, %eax
	leal	(%rdx,%rbx), %esi
	subl	%edx, %ebx
	leal	(%rax,%r11), %edx
	subl	%eax, %r11d
	leal	(%rcx,%r9), %eax
	leal	(%rax,%rax,2), %edi
	leal	(%rax,%rdi,4), %eax
	subl	%ecx, %r9d
	leal	(%r9,%r9,2), %ecx
	leal	(%r9,%rcx,4), %ecx
	leal	(,%r8,8), %r9d
	subl	%r8d, %r9d
	movl	%edx, %edi
	shll	$4, %edi
	addl	%edx, %edi
	subl	%edi, %r9d
	movl	%r8d, %edi
	shll	$4, %edi
	addl	%r8d, %edi
	leal	(,%rdx,8), %r8d
	subl	%edx, %r8d
	addl	%edi, %r8d
	leal	(%r8,%rax), %edx
	imull	%r12d, %edx
	addl	$524288, %edx                   ## imm = 0x80000
	sarl	$20, %edx
	movl	%edx, (%r10)
	leal	(%r9,%rcx), %edx
	imull	%r12d, %edx
	addl	$524288, %edx                   ## imm = 0x80000
	sarl	$20, %edx
	movl	%edx, 128(%r10)
	subl	%r9d, %ecx
	imull	%r12d, %ecx
	addl	$524288, %ecx                   ## imm = 0x80000
	sarl	$20, %ecx
	movl	%ecx, 512(%r10)
	subl	%r8d, %eax
	imull	%r12d, %eax
	addl	$524288, %eax                   ## imm = 0x80000
	sarl	$20, %eax
	movl	%eax, 640(%r10)
	movq	-48(%rbp), %rdx                 ## 8-byte Reload
	leal	(%rdx,%r15), %eax
	leal	(%rax,%rax,2), %ecx
	leal	(%rax,%rcx,4), %eax
	subl	%edx, %r15d
	leal	(%r15,%r15,2), %ecx
	leal	(%r15,%rcx,4), %ecx
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	leal	(,%rdi,8), %r8d
	subl	%edi, %r8d
	movl	%esi, %edx
	shll	$4, %edx
	addl	%esi, %edx
	subl	%edx, %r8d
	movl	%edi, %edx
	shll	$4, %edx
	addl	%edi, %edx
	leal	(,%rsi,8), %r9d
	subl	%esi, %r9d
	addl	%edx, %r9d
	leal	(%r9,%rax), %edx
	imull	%r12d, %edx
	addl	$524288, %edx                   ## imm = 0x80000
	sarl	$20, %edx
	movl	%edx, 64(%r10)
	leal	(%r8,%rcx), %edx
	imull	%r12d, %edx
	addl	$524288, %edx                   ## imm = 0x80000
	sarl	$20, %edx
	movl	%edx, 192(%r10)
	subl	%r8d, %ecx
	imull	%r12d, %ecx
	addl	$524288, %ecx                   ## imm = 0x80000
	sarl	$20, %ecx
	movl	%ecx, 576(%r10)
	subl	%r9d, %eax
	imull	%r12d, %eax
	addl	$524288, %eax                   ## imm = 0x80000
	sarl	$20, %eax
	movl	%eax, 704(%r10)
	movq	-64(%rbp), %rdx                 ## 8-byte Reload
	leal	(%rdx,%r13), %eax
	leal	(%rax,%rax,2), %ecx
	leal	(%rax,%rcx,4), %eax
	subl	%edx, %r13d
	leal	(%r13,%r13,2), %ecx
	leal	(%r13,%rcx,4), %ecx
	leal	(,%r14,8), %r8d
	subl	%r14d, %r8d
	movl	%ebx, %edx
	shll	$4, %edx
	addl	%ebx, %edx
	subl	%edx, %r8d
	movl	%r14d, %edx
	shll	$4, %edx
	addl	%r14d, %edx
	leal	(,%rbx,8), %esi
	subl	%ebx, %esi
	addl	%edx, %esi
	leal	(%rsi,%rax), %edx
	imull	%r12d, %edx
	addl	$524288, %edx                   ## imm = 0x80000
	sarl	$20, %edx
	movl	%edx, 256(%r10)
	leal	(%r8,%rcx), %edx
	imull	%r12d, %edx
	addl	$524288, %edx                   ## imm = 0x80000
	sarl	$20, %edx
	movl	%edx, 384(%r10)
	subl	%r8d, %ecx
	imull	%r12d, %ecx
	addl	$524288, %ecx                   ## imm = 0x80000
	sarl	$20, %ecx
	movl	%ecx, 768(%r10)
	subl	%esi, %eax
	imull	%r12d, %eax
	addl	$524288, %eax                   ## imm = 0x80000
	sarl	$20, %eax
	movl	%eax, 896(%r10)
	movq	-88(%rbp), %rdx                 ## 8-byte Reload
	movq	-72(%rbp), %rsi                 ## 8-byte Reload
	leal	(%rsi,%rdx), %eax
	leal	(%rax,%rax,2), %ecx
	leal	(%rax,%rcx,4), %eax
	subl	%esi, %edx
	leal	(%rdx,%rdx,2), %ecx
	leal	(%rdx,%rcx,4), %ecx
	movq	-80(%rbp), %rdi                 ## 8-byte Reload
	leal	(,%rdi,8), %esi
	subl	%edi, %esi
	movl	%r11d, %edx
	shll	$4, %edx
	addl	%r11d, %edx
	subl	%edx, %esi
	movl	%edi, %edx
	shll	$4, %edx
	addl	%edi, %edx
	leal	(,%r11,8), %ebx
	subl	%r11d, %ebx
	addl	%edx, %ebx
	leal	(%rbx,%rax), %edx
	imull	%r12d, %edx
	addl	$524288, %edx                   ## imm = 0x80000
	sarl	$20, %edx
	movl	%edx, 320(%r10)
	leal	(%rsi,%rcx), %edx
	imull	%r12d, %edx
	addl	$524288, %edx                   ## imm = 0x80000
	sarl	$20, %edx
	movl	%edx, 448(%r10)
	subl	%esi, %ecx
	imull	%r12d, %ecx
	addl	$524288, %ecx                   ## imm = 0x80000
	sarl	$20, %ecx
	movl	%ecx, 832(%r10)
	subl	%ebx, %eax
	imull	%r12d, %eax
	addl	$524288, %eax                   ## imm = 0x80000
	sarl	$20, %eax
	movl	%eax, 960(%r10)
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_svq3_dequant_coeff,8,3         ## @svq3_dequant_coeff
	.no_dead_strip	_svq3_luma_dc_dequant_idct_c
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function svq3_luma_dc_dequant_idct_c
_svq3_luma_dc_dequant_idct_c:           ; @svq3_luma_dc_dequant_idct_c
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	.cfi_offset w19, -8
	.cfi_offset w20, -16
	.cfi_offset w21, -24
	.cfi_offset w22, -32
	.cfi_offset w23, -40
	.cfi_offset w24, -48
	.cfi_offset w25, -56
	.cfi_offset w26, -64
Lloh0:
	adrp	x8, _svq3_dequant_coeff@GOTPAGE
Lloh1:
	ldr	x8, [x8, _svq3_dequant_coeff@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	ldr	w8, [x8, w2, sxtw #2]
	ldp	w10, w11, [x1, #8]
	add	w12, w11, w11, lsl #4
	ldp	w13, w14, [x1]
	add	w15, w10, w13
	mov	w9, #13
	mul	w15, w15, w9
	sub	w10, w13, w10
	mul	w10, w10, w9
	lsl	w13, w14, #3
	sub	w13, w13, w14
	sub	w12, w13, w12
	add	w13, w14, w14, lsl #4
	lsl	w14, w11, #3
	sub	w11, w14, w11
	add	w11, w11, w13
	add	w7, w11, w15
	add	w3, w12, w10
	sub	w13, w10, w12
	sub	w10, w15, w11
	ldp	w12, w14, [x1, #16]
	ldp	w15, w17, [x1, #24]
	add	w11, w15, w12
	mul	w11, w11, w9
	sub	w6, w12, w15
	lsl	w12, w14, #3
	add	w15, w17, w17, lsl #4
	sub	w12, w12, w14
	sub	w16, w12, w15
	add	w12, w14, w14, lsl #4
	lsl	w14, w17, #3
	sub	w14, w14, w17
	add	w12, w14, w12
	ldp	w15, w17, [x1, #32]
	ldp	w2, w5, [x1, #40]
	add	w14, w2, w15
	mul	w14, w14, w9
	sub	w19, w15, w2
	lsl	w15, w17, #3
	add	w2, w5, w5, lsl #4
	sub	w15, w15, w17
	sub	w4, w15, w2
	add	w15, w17, w17, lsl #4
	lsl	w17, w5, #3
	sub	w17, w17, w5
	add	w15, w17, w15
	ldp	w2, w20, [x1, #48]
	ldp	w5, w1, [x1, #56]
	add	w17, w5, w2
	mul	w17, w17, w9
	sub	w21, w2, w5
	lsl	w2, w20, #3
	add	w5, w1, w1, lsl #4
	sub	w2, w2, w20
	sub	w5, w2, w5
	add	w2, w20, w20, lsl #4
	lsl	w20, w1, #3
	sub	w1, w20, w1
	add	w2, w1, w2
	add	w1, w15, w14
	add	w20, w1, w7
	mul	w20, w20, w9
	sub	w7, w7, w1
	add	w1, w12, w11
	lsl	w22, w1, #3
	sub	w22, w22, w1
	add	w1, w1, w1, lsl #4
	add	w23, w2, w17
	lsl	w24, w23, #3
	sub	w24, w24, w23
	add	w24, w24, w1
	add	w25, w24, w20
	orr	w1, wzr, #0x80000
	madd	w25, w25, w8, w1
	asr	w25, w25, #20
	str	w25, [x0]
	mul	w6, w6, w9
	mul	w19, w19, w9
	mul	w21, w21, w9
	mul	w7, w7, w9
	add	w23, w23, w23, lsl #4
	sub	w22, w22, w23
	add	w23, w22, w7
	madd	w23, w23, w8, w1
	asr	w23, w23, #20
	str	w23, [x0, #128]
	sub	w7, w7, w22
	madd	w7, w7, w8, w1
	asr	w7, w7, #20
	str	w7, [x0, #512]
	sub	w7, w20, w24
	madd	w7, w7, w8, w1
	asr	w7, w7, #20
	str	w7, [x0, #640]
	add	w7, w4, w19
	add	w20, w7, w3
	mul	w20, w20, w9
	sub	w3, w3, w7
	add	w7, w16, w6
	lsl	w22, w7, #3
	sub	w22, w22, w7
	add	w7, w7, w7, lsl #4
	add	w23, w5, w21
	lsl	w24, w23, #3
	sub	w24, w24, w23
	add	w7, w24, w7
	add	w24, w7, w20
	madd	w24, w24, w8, w1
	asr	w24, w24, #20
	str	w24, [x0, #64]
	mul	w3, w3, w9
	add	w23, w23, w23, lsl #4
	sub	w22, w22, w23
	add	w23, w22, w3
	madd	w23, w23, w8, w1
	asr	w23, w23, #20
	str	w23, [x0, #192]
	sub	w3, w3, w22
	madd	w3, w3, w8, w1
	asr	w3, w3, #20
	str	w3, [x0, #576]
	sub	w3, w20, w7
	madd	w3, w3, w8, w1
	asr	w3, w3, #20
	str	w3, [x0, #704]
	sub	w3, w19, w4
	add	w4, w3, w13
	mul	w4, w4, w9
	sub	w13, w13, w3
	mul	w13, w13, w9
	sub	w16, w6, w16
	lsl	w3, w16, #3
	sub	w3, w3, w16
	sub	w5, w21, w5
	lsl	w6, w5, #3
	sub	w6, w6, w5
	add	w5, w5, w5, lsl #4
	add	w16, w16, w16, lsl #4
	add	w16, w6, w16
	add	w6, w16, w4
	madd	w6, w6, w8, w1
	asr	w6, w6, #20
	str	w6, [x0, #256]
	sub	w3, w3, w5
	add	w5, w3, w13
	madd	w5, w5, w8, w1
	asr	w5, w5, #20
	str	w5, [x0, #384]
	sub	w13, w13, w3
	madd	w13, w13, w8, w1
	asr	w13, w13, #20
	str	w13, [x0, #768]
	sub	w13, w4, w16
	madd	w13, w13, w8, w1
	asr	w13, w13, #20
	str	w13, [x0, #896]
	sub	w13, w14, w15
	add	w14, w13, w10
	mul	w14, w14, w9
	sub	w11, w11, w12
	lsl	w12, w11, #3
	sub	w12, w12, w11
	sub	w15, w17, w2
	lsl	w16, w15, #3
	sub	w16, w16, w15
	add	w11, w11, w11, lsl #4
	add	w11, w16, w11
	add	w16, w11, w14
	madd	w16, w16, w8, w1
	asr	w16, w16, #20
	str	w16, [x0, #320]
	sub	w10, w10, w13
	mul	w9, w10, w9
	add	w10, w15, w15, lsl #4
	sub	w10, w12, w10
	add	w12, w10, w9
	madd	w12, w12, w8, w1
	asr	w12, w12, #20
	str	w12, [x0, #448]
	sub	w9, w9, w10
	madd	w9, w9, w8, w1
	asr	w9, w9, #20
	str	w9, [x0, #832]
	sub	w9, w14, w11
	madd	w8, w9, w8, w1
	asr	w8, w8, #20
	str	w8, [x0, #960]
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_svq3_dequant_coeff,8,3         ; @svq3_dequant_coeff
	.no_dead_strip	_svq3_luma_dc_dequant_idct_c
.subsections_via_symbols
