	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function config_pcie
_config_pcie:                           ## @config_pcie
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movl	16(%rdi), %edi
	movq	_PCI_EXP_DEVCTL@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	leaq	-44(%rbp), %rdx
	callq	_pcie_capability_read_word
	movq	_PCI_EXP_DEVCTL_PAYLOAD@GOTPCREL(%rip), %rbx
	movl	(%rbx), %r12d
	andl	-44(%rbp), %r12d
	movl	16(%r15), %edi
	leaq	-48(%rbp), %rdx
	movl	$2, %esi
	callq	_pci_read_config_word
	cmpl	$55, -48(%rbp)
	jne	LBB0_1
## %bb.2:
	movl	16(%r15), %edi
	movq	_PCI_EXP_DEVCTL_READRQ@GOTPCREL(%rip), %rax
	movl	(%rbx), %edx
	orl	(%rax), %edx
	movl	(%r14), %esi
	notl	%edx
	andl	-44(%rbp), %edx
	callq	_pcie_capability_write_word
	xorl	%r12d, %r12d
	jmp	LBB0_3
LBB0_1:
	sarl	$5, %r12d
LBB0_3:
	movl	16(%r15), %edi
	movq	_PCI_EXP_LNKCTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-44(%rbp), %rdx
	callq	_pcie_capability_read_word
	movq	_A_PCIE_PEX_CTRL0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_t3_read_reg
	movl	%eax, %edi
	callq	_G_NUMFSTTRNSEQ
	movl	%eax, %ebx
	cmpq	$0, (%r15)
	je	LBB0_4
## %bb.5:
	movq	_A_PCIE_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_t3_read_reg
	movl	%eax, %edi
	callq	_G_NUMFSTTRNSEQRX
                                        ## kill: def $eax killed $eax def $rax
	jmp	LBB0_6
LBB0_4:
	movl	%ebx, %eax
LBB0_6:
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
	movl	8(%r15), %edi
	callq	_fls
                                        ## kill: def $eax killed $eax def $rax
	decl	%eax
	movl	%r12d, %ecx
	shlq	$3, %rax
	leaq	(%rax,%rax,2), %rax
	leaq	_config_pcie.ack_lat(%rip), %rdx
	addq	%rax, %rdx
	movl	-44(%rbp), %esi
	andl	$1, %esi
	negl	%esi
	shll	$2, %ebx
	andl	%esi, %ebx
	leaq	_config_pcie.rpl_tmr(%rip), %rsi
	addq	%rax, %rsi
	movl	(%rsi,%rcx,4), %r14d
	movq	_A_PCIE_PEX_CTRL1@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	addl	(%rdx,%rcx,4), %ebx
	cmpq	$0, (%r15)
	je	LBB0_7
## %bb.8:
	movq	_M_ACKLAT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_V_ACKLAT
	movl	%eax, %r13d
	movl	%ebx, %edi
	callq	_V_ACKLAT
	jmp	LBB0_9
LBB0_7:
	movq	_M_T3A_ACKLAT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_V_T3A_ACKLAT
	movl	%eax, %r13d
	movl	%ebx, %edi
	callq	_V_T3A_ACKLAT
LBB0_9:
	movq	%r15, %rdi
	movl	%r12d, %esi
	movl	%r13d, %edx
	movl	%eax, %ecx
	callq	_t3_set_reg_field
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	leal	(%r14,%rax,4), %r12d
	movq	_A_PCIE_PEX_CTRL0@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_M_REPLAYLMT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_V_REPLAYLMT
	movl	%eax, %ebx
	movl	%r12d, %edi
	callq	_V_REPLAYLMT
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%ebx, %edx
	movl	%eax, %ecx
	callq	_t3_set_reg_field
	movq	_A_PCIE_PEX_ERR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$-1, %edx
	callq	_t3_write_reg
	movq	_F_ENABLELINKDWNDRST@GOTPCREL(%rip), %rax
	movq	_F_ENABLELINKDOWNRST@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	_A_PCIE_CFG@GOTPCREL(%rip), %rax
	movq	_F_PCIE_DMASTOPEN@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movl	(%rax), %esi
	movq	_F_PCIE_CLIDECEN@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_t3_set_reg_field
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__const
	.p2align	4                               ## @config_pcie.ack_lat
_config_pcie.ack_lat:
	.long	237                             ## 0xed
	.long	416                             ## 0x1a0
	.long	559                             ## 0x22f
	.long	1071                            ## 0x42f
	.long	2095                            ## 0x82f
	.long	4143                            ## 0x102f
	.long	128                             ## 0x80
	.long	217                             ## 0xd9
	.long	289                             ## 0x121
	.long	545                             ## 0x221
	.long	1057                            ## 0x421
	.long	2081                            ## 0x821
	.long	73                              ## 0x49
	.long	118                             ## 0x76
	.long	154                             ## 0x9a
	.long	282                             ## 0x11a
	.long	538                             ## 0x21a
	.long	1050                            ## 0x41a
	.long	67                              ## 0x43
	.long	107                             ## 0x6b
	.long	86                              ## 0x56
	.long	150                             ## 0x96
	.long	278                             ## 0x116
	.long	534                             ## 0x216

	.p2align	4                               ## @config_pcie.rpl_tmr
_config_pcie.rpl_tmr:
	.long	711                             ## 0x2c7
	.long	1248                            ## 0x4e0
	.long	1677                            ## 0x68d
	.long	3213                            ## 0xc8d
	.long	6285                            ## 0x188d
	.long	12429                           ## 0x308d
	.long	384                             ## 0x180
	.long	651                             ## 0x28b
	.long	867                             ## 0x363
	.long	1635                            ## 0x663
	.long	3171                            ## 0xc63
	.long	6243                            ## 0x1863
	.long	219                             ## 0xdb
	.long	354                             ## 0x162
	.long	462                             ## 0x1ce
	.long	846                             ## 0x34e
	.long	1614                            ## 0x64e
	.long	3150                            ## 0xc4e
	.long	201                             ## 0xc9
	.long	321                             ## 0x141
	.long	258                             ## 0x102
	.long	450                             ## 0x1c2
	.long	834                             ## 0x342
	.long	1602                            ## 0x642

	.comm	_PCI_EXP_DEVCTL,4,2             ## @PCI_EXP_DEVCTL
	.comm	_PCI_EXP_DEVCTL_PAYLOAD,4,2     ## @PCI_EXP_DEVCTL_PAYLOAD
	.comm	_PCI_EXP_DEVCTL_READRQ,4,2      ## @PCI_EXP_DEVCTL_READRQ
	.comm	_PCI_EXP_LNKCTL,4,2             ## @PCI_EXP_LNKCTL
	.comm	_A_PCIE_PEX_CTRL0,4,2           ## @A_PCIE_PEX_CTRL0
	.comm	_A_PCIE_MODE,4,2                ## @A_PCIE_MODE
	.comm	_A_PCIE_PEX_CTRL1,4,2           ## @A_PCIE_PEX_CTRL1
	.comm	_M_T3A_ACKLAT,4,2               ## @M_T3A_ACKLAT
	.comm	_M_ACKLAT,4,2                   ## @M_ACKLAT
	.comm	_M_REPLAYLMT,4,2                ## @M_REPLAYLMT
	.comm	_A_PCIE_PEX_ERR,4,2             ## @A_PCIE_PEX_ERR
	.comm	_A_PCIE_CFG,4,2                 ## @A_PCIE_CFG
	.comm	_F_ENABLELINKDWNDRST,4,2        ## @F_ENABLELINKDWNDRST
	.comm	_F_ENABLELINKDOWNRST,4,2        ## @F_ENABLELINKDOWNRST
	.comm	_F_PCIE_DMASTOPEN,4,2           ## @F_PCIE_DMASTOPEN
	.comm	_F_PCIE_CLIDECEN,4,2            ## @F_PCIE_CLIDECEN
	.no_dead_strip	_config_pcie
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function config_pcie
_config_pcie:                           ; @config_pcie
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldr	w0, [x0, #16]
Lloh0:
	adrp	x20, _PCI_EXP_DEVCTL@GOTPAGE
Lloh1:
	ldr	x20, [x20, _PCI_EXP_DEVCTL@GOTPAGEOFF]
	ldr	w1, [x20]
	add	x2, sp, #12
	bl	_pcie_capability_read_word
	ldr	w22, [sp, #12]
Lloh2:
	adrp	x21, _PCI_EXP_DEVCTL_PAYLOAD@GOTPAGE
Lloh3:
	ldr	x21, [x21, _PCI_EXP_DEVCTL_PAYLOAD@GOTPAGEOFF]
	ldr	w23, [x21]
	ldr	w0, [x19, #16]
	add	x2, sp, #8
	mov	w1, #2
	bl	_pci_read_config_word
	ldr	w8, [sp, #8]
	cmp	w8, #55
	b.ne	LBB0_2
; %bb.1:
	ldr	w0, [x19, #16]
	ldr	w1, [x20]
	ldr	w8, [sp, #12]
Lloh4:
	adrp	x9, _PCI_EXP_DEVCTL_READRQ@GOTPAGE
Lloh5:
	ldr	x9, [x9, _PCI_EXP_DEVCTL_READRQ@GOTPAGEOFF]
Lloh6:
	ldr	w9, [x9]
	ldr	w10, [x21]
	orr	w9, w10, w9
	bic	w2, w8, w9
	bl	_pcie_capability_write_word
	mov	w22, #0
	b	LBB0_3
LBB0_2:
	and	w8, w23, w22
	asr	w22, w8, #5
LBB0_3:
	ldr	w0, [x19, #16]
Lloh7:
	adrp	x8, _PCI_EXP_LNKCTL@GOTPAGE
Lloh8:
	ldr	x8, [x8, _PCI_EXP_LNKCTL@GOTPAGEOFF]
Lloh9:
	ldr	w1, [x8]
	add	x2, sp, #12
	bl	_pcie_capability_read_word
Lloh10:
	adrp	x24, _A_PCIE_PEX_CTRL0@GOTPAGE
Lloh11:
	ldr	x24, [x24, _A_PCIE_PEX_CTRL0@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	x0, x19
	bl	_t3_read_reg
	bl	_G_NUMFSTTRNSEQ
	mov	x21, x0
	ldr	x8, [x19]
	cbz	x8, LBB0_5
; %bb.4:
Lloh12:
	adrp	x8, _A_PCIE_MODE@GOTPAGE
Lloh13:
	ldr	x8, [x8, _A_PCIE_MODE@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_t3_read_reg
	bl	_G_NUMFSTTRNSEQRX
	mov	x20, x0
	b	LBB0_6
LBB0_5:
	mov	x20, x21
LBB0_6:
	ldr	w0, [x19, #8]
	bl	_fls
	sub	w8, w0, #1
	mov	w9, w22
Lloh15:
	adrp	x10, _config_pcie.ack_lat@PAGE
Lloh16:
	add	x10, x10, _config_pcie.ack_lat@PAGEOFF
	mov	w11, #24
	umaddl	x10, w8, w11, x10
	lsl	x9, x9, #2
	ldr	w10, [x10, x9]
	ldrb	w12, [sp, #12]
	sbfx	w12, w12, #0, #1
	and	w12, w12, w21, lsl #2
	add	w22, w12, w10
Lloh17:
	adrp	x10, _config_pcie.rpl_tmr@PAGE
Lloh18:
	add	x10, x10, _config_pcie.rpl_tmr@PAGEOFF
	umaddl	x8, w8, w11, x10
	ldr	w25, [x8, x9]
	ldr	x8, [x19]
Lloh19:
	adrp	x9, _A_PCIE_PEX_CTRL1@GOTPAGE
Lloh20:
	ldr	x9, [x9, _A_PCIE_PEX_CTRL1@GOTPAGEOFF]
Lloh21:
	ldr	w21, [x9]
	cbz	x8, LBB0_8
; %bb.7:
Lloh22:
	adrp	x8, _M_ACKLAT@GOTPAGE
Lloh23:
	ldr	x8, [x8, _M_ACKLAT@GOTPAGEOFF]
Lloh24:
	ldr	w0, [x8]
	bl	_V_ACKLAT
	mov	x23, x0
	mov	x0, x22
	bl	_V_ACKLAT
	b	LBB0_9
LBB0_8:
Lloh25:
	adrp	x8, _M_T3A_ACKLAT@GOTPAGE
Lloh26:
	ldr	x8, [x8, _M_T3A_ACKLAT@GOTPAGEOFF]
Lloh27:
	ldr	w0, [x8]
	bl	_V_T3A_ACKLAT
	mov	x23, x0
	mov	x0, x22
	bl	_V_T3A_ACKLAT
LBB0_9:
	mov	x3, x0
	mov	x0, x19
	mov	x1, x21
	mov	x2, x23
	bl	_t3_set_reg_field
	add	w20, w25, w20, lsl #2
	ldr	w21, [x24]
Lloh28:
	adrp	x8, _M_REPLAYLMT@GOTPAGE
Lloh29:
	ldr	x8, [x8, _M_REPLAYLMT@GOTPAGEOFF]
Lloh30:
	ldr	w0, [x8]
	bl	_V_REPLAYLMT
	mov	x22, x0
	mov	x0, x20
	bl	_V_REPLAYLMT
	mov	x3, x0
	mov	x0, x19
	mov	x1, x21
	mov	x2, x22
	bl	_t3_set_reg_field
Lloh31:
	adrp	x8, _A_PCIE_PEX_ERR@GOTPAGE
Lloh32:
	ldr	x8, [x8, _A_PCIE_PEX_ERR@GOTPAGEOFF]
Lloh33:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1
	bl	_t3_write_reg
Lloh34:
	adrp	x8, _A_PCIE_CFG@GOTPAGE
Lloh35:
	ldr	x8, [x8, _A_PCIE_CFG@GOTPAGEOFF]
Lloh36:
	ldr	w1, [x8]
Lloh37:
	adrp	x8, _F_ENABLELINKDWNDRST@GOTPAGE
Lloh38:
	ldr	x8, [x8, _F_ENABLELINKDWNDRST@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
Lloh40:
	adrp	x9, _F_ENABLELINKDOWNRST@GOTPAGE
Lloh41:
	ldr	x9, [x9, _F_ENABLELINKDOWNRST@GOTPAGEOFF]
Lloh42:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh43:
	adrp	x9, _F_PCIE_DMASTOPEN@GOTPAGE
Lloh44:
	ldr	x9, [x9, _F_PCIE_DMASTOPEN@GOTPAGEOFF]
Lloh45:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh46:
	adrp	x9, _F_PCIE_CLIDECEN@GOTPAGE
Lloh47:
	ldr	x9, [x9, _F_PCIE_CLIDECEN@GOTPAGEOFF]
Lloh48:
	ldr	w9, [x9]
	orr	w3, w8, w9
	mov	x0, x19
	mov	w2, #0
	bl	_t3_set_reg_field
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpAdd	Lloh17, Lloh18
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__const
	.p2align	2                               ; @config_pcie.ack_lat
_config_pcie.ack_lat:
	.long	237                             ; 0xed
	.long	416                             ; 0x1a0
	.long	559                             ; 0x22f
	.long	1071                            ; 0x42f
	.long	2095                            ; 0x82f
	.long	4143                            ; 0x102f
	.long	128                             ; 0x80
	.long	217                             ; 0xd9
	.long	289                             ; 0x121
	.long	545                             ; 0x221
	.long	1057                            ; 0x421
	.long	2081                            ; 0x821
	.long	73                              ; 0x49
	.long	118                             ; 0x76
	.long	154                             ; 0x9a
	.long	282                             ; 0x11a
	.long	538                             ; 0x21a
	.long	1050                            ; 0x41a
	.long	67                              ; 0x43
	.long	107                             ; 0x6b
	.long	86                              ; 0x56
	.long	150                             ; 0x96
	.long	278                             ; 0x116
	.long	534                             ; 0x216

	.p2align	2                               ; @config_pcie.rpl_tmr
_config_pcie.rpl_tmr:
	.long	711                             ; 0x2c7
	.long	1248                            ; 0x4e0
	.long	1677                            ; 0x68d
	.long	3213                            ; 0xc8d
	.long	6285                            ; 0x188d
	.long	12429                           ; 0x308d
	.long	384                             ; 0x180
	.long	651                             ; 0x28b
	.long	867                             ; 0x363
	.long	1635                            ; 0x663
	.long	3171                            ; 0xc63
	.long	6243                            ; 0x1863
	.long	219                             ; 0xdb
	.long	354                             ; 0x162
	.long	462                             ; 0x1ce
	.long	846                             ; 0x34e
	.long	1614                            ; 0x64e
	.long	3150                            ; 0xc4e
	.long	201                             ; 0xc9
	.long	321                             ; 0x141
	.long	258                             ; 0x102
	.long	450                             ; 0x1c2
	.long	834                             ; 0x342
	.long	1602                            ; 0x642

	.comm	_PCI_EXP_DEVCTL,4,2             ; @PCI_EXP_DEVCTL
	.comm	_PCI_EXP_DEVCTL_PAYLOAD,4,2     ; @PCI_EXP_DEVCTL_PAYLOAD
	.comm	_PCI_EXP_DEVCTL_READRQ,4,2      ; @PCI_EXP_DEVCTL_READRQ
	.comm	_PCI_EXP_LNKCTL,4,2             ; @PCI_EXP_LNKCTL
	.comm	_A_PCIE_PEX_CTRL0,4,2           ; @A_PCIE_PEX_CTRL0
	.comm	_A_PCIE_MODE,4,2                ; @A_PCIE_MODE
	.comm	_A_PCIE_PEX_CTRL1,4,2           ; @A_PCIE_PEX_CTRL1
	.comm	_M_T3A_ACKLAT,4,2               ; @M_T3A_ACKLAT
	.comm	_M_ACKLAT,4,2                   ; @M_ACKLAT
	.comm	_M_REPLAYLMT,4,2                ; @M_REPLAYLMT
	.comm	_A_PCIE_PEX_ERR,4,2             ; @A_PCIE_PEX_ERR
	.comm	_A_PCIE_CFG,4,2                 ; @A_PCIE_CFG
	.comm	_F_ENABLELINKDWNDRST,4,2        ; @F_ENABLELINKDWNDRST
	.comm	_F_ENABLELINKDOWNRST,4,2        ; @F_ENABLELINKDOWNRST
	.comm	_F_PCIE_DMASTOPEN,4,2           ; @F_PCIE_DMASTOPEN
	.comm	_F_PCIE_CLIDECEN,4,2            ; @F_PCIE_CLIDECEN
	.no_dead_strip	_config_pcie
.subsections_via_symbols
