	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function bnx2x_link_settings_supported
_bnx2x_link_settings_supported:         ## @bnx2x_link_settings_supported
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r15d
	movq	%rdi, %r13
	callq	_BP_PORT
	movl	%eax, %r14d
	movq	(%r13), %rax
	movq	$0, (%rax)
	movl	24(%r13), %ecx
	cmpl	$3, %ecx
	je	LBB0_6
## %bb.1:
	cmpl	$2, %ecx
	je	LBB0_5
## %bb.2:
	cmpl	$1, %ecx
	jne	LBB0_38
## %bb.3:
	movq	40(%r13), %rcx
	movq	_INT_PHY@GOTPCREL(%rip), %rdx
	jmp	LBB0_4
LBB0_6:
	movq	_PORT_HW_CFG_PHY_SWAPPED_ENABLED@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	40(%r13), %rsi
	movq	_EXT_PHY1@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	(%rsi,%rcx,4), %ecx
	testl	%edx, 28(%r13)
	je	LBB0_8
## %bb.7:
	movl	%ecx, 4(%rax)
	movq	_EXT_PHY2@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdi
	movl	%ecx, %edx
	movl	(%rsi,%rdi,4), %ecx
	movl	%ecx, (%rax)
	jmp	LBB0_9
LBB0_5:
	movq	40(%r13), %rcx
	movq	_EXT_PHY1@GOTPCREL(%rip), %rdx
LBB0_4:
	movq	(%rdx), %rdx
	movl	(%rcx,%rdx,4), %ecx
	movl	%ecx, (%rax)
	movl	$1, %r12d
	xorl	%edx, %edx
	orl	%ecx, %edx
	jne	LBB0_11
LBB0_38:
	movq	_dev_info@GOTPCREL(%rip), %r15
	movq	(%r15), %rax
	movslq	%r14d, %rbx
	movl	4(%rax,%rbx,8), %esi
	movq	%r13, %rdi
	callq	_SHMEM_RD
	movl	%eax, %r14d
	movq	(%r15), %rax
	movl	(%rax,%rbx,8), %esi
	movq	%r13, %rdi
	callq	_SHMEM_RD
	leaq	L_.str(%rip), %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_BNX2X_ERR                      ## TAILCALL
LBB0_8:
	movl	%ecx, (%rax)
	movq	_EXT_PHY2@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdx
	movl	(%rsi,%rdx,4), %edx
	movl	%edx, 4(%rax)
LBB0_9:
	movl	$2, %r12d
	orl	%ecx, %edx
	je	LBB0_38
LBB0_11:
	movq	%r13, %rdi
	callq	_CHIP_IS_E3
	testq	%rax, %rax
	je	LBB0_13
## %bb.12:
	movq	_MISC_REG_WC0_CTRL_PHY_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	jmp	LBB0_19
LBB0_13:
	cmpl	$129, %r15d
	je	LBB0_17
## %bb.14:
	cmpl	$128, %r15d
	jne	LBB0_16
## %bb.15:
	movq	_NIG_REG_SERDES0_CTRL_PHY_ADDR@GOTPCREL(%rip), %rax
	shll	$4, %r14d
	jmp	LBB0_18
LBB0_17:
	movq	_NIG_REG_XGXS0_CTRL_PHY_ADDR@GOTPCREL(%rip), %rax
	leal	(%r14,%r14,2), %r14d
	shll	$3, %r14d
LBB0_18:
	addl	(%rax), %r14d
LBB0_19:
	movq	%r13, %rdi
	movl	%r14d, %esi
	callq	_REG_RD
	movq	%rax, 8(%r13)
	leaq	L_.str.2(%rip), %rdi
	xorl	%ebx, %ebx
	movl	%eax, %esi
	xorl	%eax, %eax
	callq	_BNX2X_DEV_INFO
	movq	32(%r13), %rax
	movq	_PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL@GOTPCREL(%rip), %r10
	movq	_PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF@GOTPCREL(%rip), %r14
	movq	_PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL@GOTPCREL(%rip), %rdi
	movq	_PORT_HW_CFG_SPEED_CAPABILITY_D0_1G@GOTPCREL(%rip), %rcx
	movq	_PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G@GOTPCREL(%rip), %r9
	movq	_PORT_HW_CFG_SPEED_CAPABILITY_D0_10G@GOTPCREL(%rip), %r11
	movq	_PORT_HW_CFG_SPEED_CAPABILITY_D0_20G@GOTPCREL(%rip), %r8
	jmp	LBB0_20
	.p2align	4, 0x90
LBB0_36:                                ##   in Loop: Header=BB0_20 Depth=1
	incq	%rbx
	cmpq	%rbx, %r12
	je	LBB0_37
LBB0_20:                                ## =>This Inner Loop Header: Depth=1
	movl	(%rax,%rbx,4), %r15d
	movq	_PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF@GOTPCREL(%rip), %rdx
	testl	%r15d, (%rdx)
	je	LBB0_21
## %bb.22:                              ##   in Loop: Header=BB0_20 Depth=1
	testl	%r15d, (%r10)
	je	LBB0_23
LBB0_24:                                ##   in Loop: Header=BB0_20 Depth=1
	testl	%r15d, (%r14)
	je	LBB0_25
LBB0_26:                                ##   in Loop: Header=BB0_20 Depth=1
	testl	%r15d, (%rdi)
	je	LBB0_27
LBB0_28:                                ##   in Loop: Header=BB0_20 Depth=1
	testl	%r15d, (%rcx)
	je	LBB0_29
LBB0_30:                                ##   in Loop: Header=BB0_20 Depth=1
	testl	%r15d, (%r9)
	je	LBB0_31
LBB0_32:                                ##   in Loop: Header=BB0_20 Depth=1
	testl	%r15d, (%r11)
	je	LBB0_33
LBB0_34:                                ##   in Loop: Header=BB0_20 Depth=1
	testl	%r15d, (%r8)
	jne	LBB0_36
	jmp	LBB0_35
	.p2align	4, 0x90
LBB0_21:                                ##   in Loop: Header=BB0_20 Depth=1
	movq	_SUPPORTED_10baseT_Half@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	notl	%esi
	movq	(%r13), %rdx
	andl	%esi, (%rdx,%rbx,4)
	movl	(%rax,%rbx,4), %r15d
	testl	%r15d, (%r10)
	jne	LBB0_24
LBB0_23:                                ##   in Loop: Header=BB0_20 Depth=1
	movq	_SUPPORTED_10baseT_Full@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	notl	%edx
	movq	(%r13), %rsi
	andl	%edx, (%rsi,%rbx,4)
	movl	(%rax,%rbx,4), %r15d
	testl	%r15d, (%r14)
	jne	LBB0_26
LBB0_25:                                ##   in Loop: Header=BB0_20 Depth=1
	movq	_SUPPORTED_100baseT_Half@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	notl	%edx
	movq	(%r13), %rsi
	andl	%edx, (%rsi,%rbx,4)
	movl	(%rax,%rbx,4), %r15d
	testl	%r15d, (%rdi)
	jne	LBB0_28
LBB0_27:                                ##   in Loop: Header=BB0_20 Depth=1
	movq	_SUPPORTED_100baseT_Full@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	notl	%edx
	movq	(%r13), %rsi
	andl	%edx, (%rsi,%rbx,4)
	movl	(%rax,%rbx,4), %r15d
	testl	%r15d, (%rcx)
	jne	LBB0_30
LBB0_29:                                ##   in Loop: Header=BB0_20 Depth=1
	movq	_SUPPORTED_1000baseT_Full@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movq	_SUPPORTED_1000baseT_Half@GOTPCREL(%rip), %rsi
	orl	(%rsi), %edx
	notl	%edx
	movq	(%r13), %rsi
	andl	%edx, (%rsi,%rbx,4)
	movl	(%rax,%rbx,4), %r15d
	testl	%r15d, (%r9)
	jne	LBB0_32
LBB0_31:                                ##   in Loop: Header=BB0_20 Depth=1
	movq	_SUPPORTED_2500baseX_Full@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	notl	%edx
	movq	(%r13), %rsi
	andl	%edx, (%rsi,%rbx,4)
	movl	(%rax,%rbx,4), %r15d
	testl	%r15d, (%r11)
	jne	LBB0_34
LBB0_33:                                ##   in Loop: Header=BB0_20 Depth=1
	movq	_SUPPORTED_10000baseT_Full@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	notl	%edx
	movq	(%r13), %rsi
	andl	%edx, (%rsi,%rbx,4)
	movl	(%rax,%rbx,4), %r15d
	testl	%r15d, (%r8)
	jne	LBB0_36
LBB0_35:                                ##   in Loop: Header=BB0_20 Depth=1
	movq	_SUPPORTED_20000baseKR2_Full@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	notl	%edx
	movq	(%r13), %rsi
	andl	%edx, (%rsi,%rbx,4)
	jmp	LBB0_36
LBB0_37:
	movq	(%r13), %rax
	movl	(%rax), %esi
	movl	4(%rax), %edx
	leaq	L_.str.3(%rip), %rdi
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_BNX2X_DEV_INFO                 ## TAILCALL
LBB0_16:
	movq	16(%r13), %rax
	movl	(%rax), %esi
	leaq	L_.str.1(%rip), %rdi
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_BNX2X_ERR                      ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_INT_PHY,8,3                    ## @INT_PHY
	.comm	_EXT_PHY1,8,3                   ## @EXT_PHY1
	.comm	_PORT_HW_CFG_PHY_SWAPPED_ENABLED,4,2 ## @PORT_HW_CFG_PHY_SWAPPED_ENABLED
	.comm	_EXT_PHY2,8,3                   ## @EXT_PHY2
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n"

	.comm	_dev_info,8,3                   ## @dev_info
	.comm	_MISC_REG_WC0_CTRL_PHY_ADDR,4,2 ## @MISC_REG_WC0_CTRL_PHY_ADDR
	.comm	_NIG_REG_SERDES0_CTRL_PHY_ADDR,4,2 ## @NIG_REG_SERDES0_CTRL_PHY_ADDR
	.comm	_NIG_REG_XGXS0_CTRL_PHY_ADDR,4,2 ## @NIG_REG_XGXS0_CTRL_PHY_ADDR
L_.str.1:                               ## @.str.1
	.asciz	"BAD switch_cfg link_config 0x%x\n"

L_.str.2:                               ## @.str.2
	.asciz	"phy_addr 0x%x\n"

	.comm	_PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF,4,2 ## @PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
	.comm	_SUPPORTED_10baseT_Half,4,2     ## @SUPPORTED_10baseT_Half
	.comm	_PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL,4,2 ## @PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
	.comm	_SUPPORTED_10baseT_Full,4,2     ## @SUPPORTED_10baseT_Full
	.comm	_PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF,4,2 ## @PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
	.comm	_SUPPORTED_100baseT_Half,4,2    ## @SUPPORTED_100baseT_Half
	.comm	_PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL,4,2 ## @PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
	.comm	_SUPPORTED_100baseT_Full,4,2    ## @SUPPORTED_100baseT_Full
	.comm	_PORT_HW_CFG_SPEED_CAPABILITY_D0_1G,4,2 ## @PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
	.comm	_SUPPORTED_1000baseT_Half,4,2   ## @SUPPORTED_1000baseT_Half
	.comm	_SUPPORTED_1000baseT_Full,4,2   ## @SUPPORTED_1000baseT_Full
	.comm	_PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G,4,2 ## @PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
	.comm	_SUPPORTED_2500baseX_Full,4,2   ## @SUPPORTED_2500baseX_Full
	.comm	_PORT_HW_CFG_SPEED_CAPABILITY_D0_10G,4,2 ## @PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
	.comm	_SUPPORTED_10000baseT_Full,4,2  ## @SUPPORTED_10000baseT_Full
	.comm	_PORT_HW_CFG_SPEED_CAPABILITY_D0_20G,4,2 ## @PORT_HW_CFG_SPEED_CAPABILITY_D0_20G
	.comm	_SUPPORTED_20000baseKR2_Full,4,2 ## @SUPPORTED_20000baseKR2_Full
L_.str.3:                               ## @.str.3
	.asciz	"supported 0x%x 0x%x\n"

	.no_dead_strip	_bnx2x_link_settings_supported
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function bnx2x_link_settings_supported
_bnx2x_link_settings_supported:         ; @bnx2x_link_settings_supported
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x21, x1
	mov	x19, x0
	bl	_BP_PORT
	mov	x20, x0
	ldr	x8, [x19]
	str	xzr, [x8]
	ldr	w9, [x19, #24]
	cmp	w9, #3
	b.eq	LBB0_4
; %bb.1:
	cmp	w9, #2
	b.eq	LBB0_6
; %bb.2:
	cmp	w9, #1
	b.ne	LBB0_8
; %bb.3:
	mov	w10, #0
Lloh0:
	adrp	x9, _INT_PHY@GOTPAGE
Lloh1:
	ldr	x9, [x9, _INT_PHY@GOTPAGEOFF]
	b	LBB0_7
LBB0_4:
	ldr	w10, [x19, #28]
Lloh2:
	adrp	x9, _PORT_HW_CFG_PHY_SWAPPED_ENABLED@GOTPAGE
Lloh3:
	ldr	x9, [x9, _PORT_HW_CFG_PHY_SWAPPED_ENABLED@GOTPAGEOFF]
Lloh4:
	ldr	w12, [x9]
	ldr	x11, [x19, #40]
Lloh5:
	adrp	x9, _EXT_PHY1@GOTPAGE
Lloh6:
	ldr	x9, [x9, _EXT_PHY1@GOTPAGEOFF]
Lloh7:
	ldr	x9, [x9]
	ldr	w9, [x11, x9, lsl #2]
	tst	w12, w10
	b.eq	LBB0_9
; %bb.5:
	str	w9, [x8, #4]
Lloh8:
	adrp	x10, _EXT_PHY2@GOTPAGE
Lloh9:
	ldr	x10, [x10, _EXT_PHY2@GOTPAGEOFF]
Lloh10:
	ldr	x12, [x10]
	mov	x10, x9
	ldr	w9, [x11, x12, lsl #2]
	str	w9, [x8]
	b	LBB0_10
LBB0_6:
	mov	w10, #0
Lloh11:
	adrp	x9, _EXT_PHY1@GOTPAGE
Lloh12:
	ldr	x9, [x9, _EXT_PHY1@GOTPAGEOFF]
LBB0_7:
	ldr	x11, [x19, #40]
	ldr	x9, [x9]
	ldr	w9, [x11, x9, lsl #2]
	str	w9, [x8]
	mov	w22, #1
	orr	w8, w9, w10
	cbnz	w8, LBB0_11
LBB0_8:
Lloh13:
	adrp	x21, _dev_info@GOTPAGE
Lloh14:
	ldr	x21, [x21, _dev_info@GOTPAGEOFF]
	ldr	x8, [x21]
	sbfiz	x22, x20, #3, #32
	add	x8, x8, x22
	ldr	w1, [x8, #4]
	mov	x0, x19
	bl	_SHMEM_RD
	mov	x20, x0
	ldr	x8, [x21]
	ldr	w1, [x8, x22]
	mov	x0, x19
	bl	_SHMEM_RD
                                        ; kill: def $w0 killed $w0 def $x0
	str	x0, [sp]
Lloh15:
	adrp	x0, l_.str@PAGE
Lloh16:
	add	x0, x0, l_.str@PAGEOFF
	mov	x1, x20
	bl	_BNX2X_ERR
	b	LBB0_32
LBB0_9:
Lloh17:
	adrp	x10, _EXT_PHY2@GOTPAGE
Lloh18:
	ldr	x10, [x10, _EXT_PHY2@GOTPAGEOFF]
	str	w9, [x8]
Lloh19:
	ldr	x10, [x10]
	ldr	w10, [x11, x10, lsl #2]
	str	w10, [x8, #4]
LBB0_10:
	mov	w22, #2
	orr	w8, w9, w10
	cbz	w8, LBB0_8
LBB0_11:
	mov	x0, x19
	bl	_CHIP_IS_E3
	cbz	x0, LBB0_33
; %bb.12:
Lloh20:
	adrp	x8, _MISC_REG_WC0_CTRL_PHY_ADDR@GOTPAGE
Lloh21:
	ldr	x8, [x8, _MISC_REG_WC0_CTRL_PHY_ADDR@GOTPAGEOFF]
Lloh22:
	ldr	w1, [x8]
LBB0_13:
	mov	x0, x19
	bl	_REG_RD
	mov	x1, x0
	str	x0, [x19, #8]
Lloh23:
	adrp	x0, l_.str.2@PAGE
Lloh24:
	add	x0, x0, l_.str.2@PAGEOFF
                                        ; kill: def $w1 killed $w1 killed $x1
	bl	_BNX2X_DEV_INFO
	mov	x8, #0
	ldr	x9, [x19, #32]
	lsl	x10, x22, #2
Lloh25:
	adrp	x11, _PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF@GOTPAGE
Lloh26:
	ldr	x11, [x11, _PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF@GOTPAGEOFF]
Lloh27:
	adrp	x12, _SUPPORTED_10baseT_Half@GOTPAGE
Lloh28:
	ldr	x12, [x12, _SUPPORTED_10baseT_Half@GOTPAGEOFF]
Lloh29:
	adrp	x13, _PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL@GOTPAGE
Lloh30:
	ldr	x13, [x13, _PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL@GOTPAGEOFF]
Lloh31:
	adrp	x14, _SUPPORTED_10baseT_Full@GOTPAGE
Lloh32:
	ldr	x14, [x14, _SUPPORTED_10baseT_Full@GOTPAGEOFF]
Lloh33:
	adrp	x15, _PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF@GOTPAGE
Lloh34:
	ldr	x15, [x15, _PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF@GOTPAGEOFF]
Lloh35:
	adrp	x16, _SUPPORTED_100baseT_Half@GOTPAGE
Lloh36:
	ldr	x16, [x16, _SUPPORTED_100baseT_Half@GOTPAGEOFF]
Lloh37:
	adrp	x17, _PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL@GOTPAGE
Lloh38:
	ldr	x17, [x17, _PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL@GOTPAGEOFF]
Lloh39:
	adrp	x0, _SUPPORTED_100baseT_Full@GOTPAGE
Lloh40:
	ldr	x0, [x0, _SUPPORTED_100baseT_Full@GOTPAGEOFF]
Lloh41:
	adrp	x1, _PORT_HW_CFG_SPEED_CAPABILITY_D0_1G@GOTPAGE
Lloh42:
	ldr	x1, [x1, _PORT_HW_CFG_SPEED_CAPABILITY_D0_1G@GOTPAGEOFF]
Lloh43:
	adrp	x2, _SUPPORTED_1000baseT_Half@GOTPAGE
Lloh44:
	ldr	x2, [x2, _SUPPORTED_1000baseT_Half@GOTPAGEOFF]
Lloh45:
	adrp	x3, _SUPPORTED_1000baseT_Full@GOTPAGE
Lloh46:
	ldr	x3, [x3, _SUPPORTED_1000baseT_Full@GOTPAGEOFF]
Lloh47:
	adrp	x4, _PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G@GOTPAGE
Lloh48:
	ldr	x4, [x4, _PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G@GOTPAGEOFF]
Lloh49:
	adrp	x5, _SUPPORTED_2500baseX_Full@GOTPAGE
Lloh50:
	ldr	x5, [x5, _SUPPORTED_2500baseX_Full@GOTPAGEOFF]
Lloh51:
	adrp	x6, _PORT_HW_CFG_SPEED_CAPABILITY_D0_10G@GOTPAGE
Lloh52:
	ldr	x6, [x6, _PORT_HW_CFG_SPEED_CAPABILITY_D0_10G@GOTPAGEOFF]
Lloh53:
	adrp	x7, _SUPPORTED_10000baseT_Full@GOTPAGE
Lloh54:
	ldr	x7, [x7, _SUPPORTED_10000baseT_Full@GOTPAGEOFF]
Lloh55:
	adrp	x20, _PORT_HW_CFG_SPEED_CAPABILITY_D0_20G@GOTPAGE
Lloh56:
	ldr	x20, [x20, _PORT_HW_CFG_SPEED_CAPABILITY_D0_20G@GOTPAGEOFF]
Lloh57:
	adrp	x21, _SUPPORTED_20000baseKR2_Full@GOTPAGE
Lloh58:
	ldr	x21, [x21, _SUPPORTED_20000baseKR2_Full@GOTPAGEOFF]
	b	LBB0_15
LBB0_14:                                ;   in Loop: Header=BB0_15 Depth=1
	add	x8, x8, #4
	cmp	x10, x8
	b.eq	LBB0_31
LBB0_15:                                ; =>This Inner Loop Header: Depth=1
	ldr	w22, [x9, x8]
	ldr	w23, [x11]
	tst	w23, w22
	b.ne	LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_15 Depth=1
	ldr	x22, [x19]
	ldr	w23, [x22, x8]
	ldr	w24, [x12]
	bic	w23, w23, w24
	str	w23, [x22, x8]
	ldr	w22, [x9, x8]
LBB0_17:                                ;   in Loop: Header=BB0_15 Depth=1
	ldr	w23, [x13]
	tst	w23, w22
	b.ne	LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_15 Depth=1
	ldr	x22, [x19]
	ldr	w23, [x22, x8]
	ldr	w24, [x14]
	bic	w23, w23, w24
	str	w23, [x22, x8]
	ldr	w22, [x9, x8]
LBB0_19:                                ;   in Loop: Header=BB0_15 Depth=1
	ldr	w23, [x15]
	tst	w23, w22
	b.ne	LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_15 Depth=1
	ldr	x22, [x19]
	ldr	w23, [x22, x8]
	ldr	w24, [x16]
	bic	w23, w23, w24
	str	w23, [x22, x8]
	ldr	w22, [x9, x8]
LBB0_21:                                ;   in Loop: Header=BB0_15 Depth=1
	ldr	w23, [x17]
	tst	w23, w22
	b.ne	LBB0_23
; %bb.22:                               ;   in Loop: Header=BB0_15 Depth=1
	ldr	x22, [x19]
	ldr	w23, [x22, x8]
	ldr	w24, [x0]
	bic	w23, w23, w24
	str	w23, [x22, x8]
	ldr	w22, [x9, x8]
LBB0_23:                                ;   in Loop: Header=BB0_15 Depth=1
	ldr	w23, [x1]
	tst	w23, w22
	b.ne	LBB0_25
; %bb.24:                               ;   in Loop: Header=BB0_15 Depth=1
	ldr	w22, [x2]
	ldr	w23, [x3]
	ldr	x24, [x19]
	ldr	w25, [x24, x8]
	orr	w22, w23, w22
	bic	w22, w25, w22
	str	w22, [x24, x8]
	ldr	w22, [x9, x8]
LBB0_25:                                ;   in Loop: Header=BB0_15 Depth=1
	ldr	w23, [x4]
	tst	w23, w22
	b.ne	LBB0_27
; %bb.26:                               ;   in Loop: Header=BB0_15 Depth=1
	ldr	x22, [x19]
	ldr	w23, [x22, x8]
	ldr	w24, [x5]
	bic	w23, w23, w24
	str	w23, [x22, x8]
	ldr	w22, [x9, x8]
LBB0_27:                                ;   in Loop: Header=BB0_15 Depth=1
	ldr	w23, [x6]
	tst	w23, w22
	b.ne	LBB0_29
; %bb.28:                               ;   in Loop: Header=BB0_15 Depth=1
	ldr	x22, [x19]
	ldr	w23, [x22, x8]
	ldr	w24, [x7]
	bic	w23, w23, w24
	str	w23, [x22, x8]
	ldr	w22, [x9, x8]
LBB0_29:                                ;   in Loop: Header=BB0_15 Depth=1
	ldr	w23, [x20]
	tst	w23, w22
	b.ne	LBB0_14
; %bb.30:                               ;   in Loop: Header=BB0_15 Depth=1
	ldr	w22, [x21]
	ldr	x23, [x19]
	ldr	w24, [x23, x8]
	bic	w22, w24, w22
	str	w22, [x23, x8]
	b	LBB0_14
LBB0_31:
	ldr	x8, [x19]
	ldp	w1, w8, [x8]
	str	x8, [sp]
Lloh59:
	adrp	x0, l_.str.3@PAGE
Lloh60:
	add	x0, x0, l_.str.3@PAGEOFF
	bl	_BNX2X_DEV_INFO
LBB0_32:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_33:
	cmp	w21, #129
	b.eq	LBB0_36
; %bb.34:
	cmp	w21, #128
	b.ne	LBB0_37
; %bb.35:
Lloh61:
	adrp	x8, _NIG_REG_SERDES0_CTRL_PHY_ADDR@GOTPAGE
Lloh62:
	ldr	x8, [x8, _NIG_REG_SERDES0_CTRL_PHY_ADDR@GOTPAGEOFF]
Lloh63:
	ldr	w8, [x8]
	add	w1, w8, w20, lsl #4
	b	LBB0_13
LBB0_36:
Lloh64:
	adrp	x8, _NIG_REG_XGXS0_CTRL_PHY_ADDR@GOTPAGE
Lloh65:
	ldr	x8, [x8, _NIG_REG_XGXS0_CTRL_PHY_ADDR@GOTPAGEOFF]
Lloh66:
	ldr	w8, [x8]
	mov	w9, #24
	madd	w1, w20, w9, w8
	b	LBB0_13
LBB0_37:
	ldr	x8, [x19, #16]
	ldr	w1, [x8]
Lloh67:
	adrp	x0, l_.str.1@PAGE
Lloh68:
	add	x0, x0, l_.str.1@PAGEOFF
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	b	_BNX2X_ERR
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpAdd	Lloh23, Lloh24
	.loh AdrpAdd	Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpAdd	Lloh67, Lloh68
	.cfi_endproc
                                        ; -- End function
	.comm	_INT_PHY,8,3                    ; @INT_PHY
	.comm	_EXT_PHY1,8,3                   ; @EXT_PHY1
	.comm	_PORT_HW_CFG_PHY_SWAPPED_ENABLED,4,2 ; @PORT_HW_CFG_PHY_SWAPPED_ENABLED
	.comm	_EXT_PHY2,8,3                   ; @EXT_PHY2
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n"

	.comm	_dev_info,8,3                   ; @dev_info
	.comm	_MISC_REG_WC0_CTRL_PHY_ADDR,4,2 ; @MISC_REG_WC0_CTRL_PHY_ADDR
	.comm	_NIG_REG_SERDES0_CTRL_PHY_ADDR,4,2 ; @NIG_REG_SERDES0_CTRL_PHY_ADDR
	.comm	_NIG_REG_XGXS0_CTRL_PHY_ADDR,4,2 ; @NIG_REG_XGXS0_CTRL_PHY_ADDR
l_.str.1:                               ; @.str.1
	.asciz	"BAD switch_cfg link_config 0x%x\n"

l_.str.2:                               ; @.str.2
	.asciz	"phy_addr 0x%x\n"

	.comm	_PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF,4,2 ; @PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
	.comm	_SUPPORTED_10baseT_Half,4,2     ; @SUPPORTED_10baseT_Half
	.comm	_PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL,4,2 ; @PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
	.comm	_SUPPORTED_10baseT_Full,4,2     ; @SUPPORTED_10baseT_Full
	.comm	_PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF,4,2 ; @PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
	.comm	_SUPPORTED_100baseT_Half,4,2    ; @SUPPORTED_100baseT_Half
	.comm	_PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL,4,2 ; @PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
	.comm	_SUPPORTED_100baseT_Full,4,2    ; @SUPPORTED_100baseT_Full
	.comm	_PORT_HW_CFG_SPEED_CAPABILITY_D0_1G,4,2 ; @PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
	.comm	_SUPPORTED_1000baseT_Half,4,2   ; @SUPPORTED_1000baseT_Half
	.comm	_SUPPORTED_1000baseT_Full,4,2   ; @SUPPORTED_1000baseT_Full
	.comm	_PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G,4,2 ; @PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
	.comm	_SUPPORTED_2500baseX_Full,4,2   ; @SUPPORTED_2500baseX_Full
	.comm	_PORT_HW_CFG_SPEED_CAPABILITY_D0_10G,4,2 ; @PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
	.comm	_SUPPORTED_10000baseT_Full,4,2  ; @SUPPORTED_10000baseT_Full
	.comm	_PORT_HW_CFG_SPEED_CAPABILITY_D0_20G,4,2 ; @PORT_HW_CFG_SPEED_CAPABILITY_D0_20G
	.comm	_SUPPORTED_20000baseKR2_Full,4,2 ; @SUPPORTED_20000baseKR2_Full
l_.str.3:                               ; @.str.3
	.asciz	"supported 0x%x 0x%x\n"

	.no_dead_strip	_bnx2x_link_settings_supported
.subsections_via_symbols
