	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_emit_state
_radeon_emit_state:                     ## @radeon_emit_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%r8d, %r13d
	movq	%rcx, %r12
	movq	%rdx, %rbx
	movq	%rsi, %r14
	movq	%rdi, %r15
	leaq	L_.str(%rip), %rdi
	movl	%r8d, %esi
	callq	_DRM_DEBUG
	movq	_RADEON_UPLOAD_CONTEXT@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_6
## %bb.1:
	leaq	100(%rbx), %rdx
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_radeon_check_and_fixup_offset
	testq	%rax, %rax
	jne	LBB0_2
## %bb.4:
	leaq	80(%rbx), %rdx
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_radeon_check_and_fixup_offset
	testq	%rax, %rax
	je	LBB0_5
LBB0_2:
	leaq	L_.str.1(%rip), %rdi
	jmp	LBB0_3
LBB0_5:
	movl	$14, %edi
	callq	_BEGIN_RING
	movq	_RADEON_PP_MISC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$6, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movl	116(%rbx), %edi
	callq	_OUT_RING
	movl	112(%rbx), %edi
	callq	_OUT_RING
	movl	108(%rbx), %edi
	callq	_OUT_RING
	movl	104(%rbx), %edi
	callq	_OUT_RING
	movl	100(%rbx), %edi
	callq	_OUT_RING
	movl	96(%rbx), %edi
	callq	_OUT_RING
	movl	92(%rbx), %edi
	callq	_OUT_RING
	movq	_RADEON_PP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$2, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movl	88(%rbx), %edi
	callq	_OUT_RING
	movl	84(%rbx), %edi
	callq	_OUT_RING
	movl	80(%rbx), %edi
	callq	_OUT_RING
	movq	_RADEON_RB3D_COLORPITCH@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movl	76(%rbx), %edi
	callq	_OUT_RING
	xorl	%eax, %eax
	callq	_ADVANCE_RING
LBB0_6:
	movq	_RADEON_UPLOAD_VERTFMT@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_8
## %bb.7:
	movl	$2, %edi
	callq	_BEGIN_RING
	movq	_RADEON_SE_COORD_FMT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movl	72(%rbx), %edi
	callq	_OUT_RING
	xorl	%eax, %eax
	callq	_ADVANCE_RING
LBB0_8:
	movq	_RADEON_UPLOAD_LINE@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_10
## %bb.9:
	movl	$5, %edi
	callq	_BEGIN_RING
	movq	_RADEON_RE_LINE_PATTERN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movl	68(%rbx), %edi
	callq	_OUT_RING
	movl	64(%rbx), %edi
	callq	_OUT_RING
	movq	_RADEON_SE_LINE_WIDTH@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movl	60(%rbx), %edi
	callq	_OUT_RING
	xorl	%eax, %eax
	callq	_ADVANCE_RING
LBB0_10:
	movq	_RADEON_UPLOAD_BUMPMAP@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_12
## %bb.11:
	movl	$5, %edi
	callq	_BEGIN_RING
	movq	_RADEON_PP_LUM_MATRIX@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movl	56(%rbx), %edi
	callq	_OUT_RING
	movq	_RADEON_PP_ROT_MATRIX_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movl	52(%rbx), %edi
	callq	_OUT_RING
	movl	48(%rbx), %edi
	callq	_OUT_RING
	xorl	%eax, %eax
	callq	_ADVANCE_RING
LBB0_12:
	movq	_RADEON_UPLOAD_MASKS@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_14
## %bb.13:
	movl	$4, %edi
	callq	_BEGIN_RING
	movq	_RADEON_RB3D_STENCILREFMASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$2, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movl	44(%rbx), %edi
	callq	_OUT_RING
	movl	40(%rbx), %edi
	callq	_OUT_RING
	movl	36(%rbx), %edi
	callq	_OUT_RING
	xorl	%eax, %eax
	callq	_ADVANCE_RING
LBB0_14:
	movq	_RADEON_UPLOAD_VIEWPORT@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_16
## %bb.15:
	movl	$7, %edi
	callq	_BEGIN_RING
	movq	_RADEON_SE_VPORT_XSCALE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$5, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movl	32(%rbx), %edi
	callq	_OUT_RING
	movl	28(%rbx), %edi
	callq	_OUT_RING
	movl	24(%rbx), %edi
	callq	_OUT_RING
	movl	20(%rbx), %edi
	callq	_OUT_RING
	movl	16(%rbx), %edi
	callq	_OUT_RING
	movl	12(%rbx), %edi
	callq	_OUT_RING
	xorl	%eax, %eax
	callq	_ADVANCE_RING
LBB0_16:
	movq	_RADEON_UPLOAD_SETUP@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_18
## %bb.17:
	movl	$4, %edi
	callq	_BEGIN_RING
	movq	_RADEON_SE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movl	8(%rbx), %edi
	callq	_OUT_RING
	movq	_RADEON_SE_CNTL_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movl	4(%rbx), %edi
	callq	_OUT_RING
	xorl	%eax, %eax
	callq	_ADVANCE_RING
LBB0_18:
	movq	_RADEON_UPLOAD_MISC@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_20
## %bb.19:
	movl	$2, %edi
	callq	_BEGIN_RING
	movq	_RADEON_RE_MISC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movl	(%rbx), %edi
	callq	_OUT_RING
	xorl	%eax, %eax
	callq	_ADVANCE_RING
LBB0_20:
	movq	_RADEON_UPLOAD_TEX0@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_24
## %bb.21:
	leaq	16(%r12), %rdx
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_radeon_check_and_fixup_offset
	testq	%rax, %rax
	je	LBB0_23
## %bb.22:
	leaq	L_.str.2(%rip), %rdi
	jmp	LBB0_3
LBB0_23:
	movl	$9, %edi
	callq	_BEGIN_RING
	movq	_RADEON_PP_TXFILTER_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$5, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movl	24(%r12), %edi
	callq	_OUT_RING
	movl	20(%r12), %edi
	callq	_OUT_RING
	movl	16(%r12), %edi
	callq	_OUT_RING
	movl	12(%r12), %edi
	callq	_OUT_RING
	movl	8(%r12), %edi
	callq	_OUT_RING
	movl	4(%r12), %edi
	callq	_OUT_RING
	movq	_RADEON_PP_BORDER_COLOR_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movl	(%r12), %edi
	callq	_OUT_RING
	xorl	%eax, %eax
	callq	_ADVANCE_RING
LBB0_24:
	movq	_RADEON_UPLOAD_TEX1@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_28
## %bb.25:
	leaq	44(%r12), %rdx
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_radeon_check_and_fixup_offset
	testq	%rax, %rax
	je	LBB0_27
## %bb.26:
	leaq	L_.str.3(%rip), %rdi
	jmp	LBB0_3
LBB0_27:
	movl	$9, %edi
	callq	_BEGIN_RING
	movq	_RADEON_PP_TXFILTER_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$5, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movl	52(%r12), %edi
	callq	_OUT_RING
	movl	48(%r12), %edi
	callq	_OUT_RING
	movl	44(%r12), %edi
	callq	_OUT_RING
	movl	40(%r12), %edi
	callq	_OUT_RING
	movl	36(%r12), %edi
	callq	_OUT_RING
	movl	32(%r12), %edi
	callq	_OUT_RING
	movq	_RADEON_PP_BORDER_COLOR_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movl	28(%r12), %edi
	callq	_OUT_RING
	xorl	%eax, %eax
	callq	_ADVANCE_RING
LBB0_28:
	movq	_RADEON_UPLOAD_TEX2@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_29
## %bb.30:
	leaq	72(%r12), %rdx
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_radeon_check_and_fixup_offset
	testq	%rax, %rax
	je	LBB0_32
## %bb.31:
	leaq	L_.str.4(%rip), %rdi
LBB0_3:
	callq	_DRM_ERROR
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
LBB0_33:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_29:
	xorl	%ebx, %ebx
	jmp	LBB0_33
LBB0_32:
	movl	$9, %edi
	callq	_BEGIN_RING
	movq	_RADEON_PP_TXFILTER_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$5, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movl	80(%r12), %edi
	callq	_OUT_RING
	movl	76(%r12), %edi
	callq	_OUT_RING
	movl	72(%r12), %edi
	callq	_OUT_RING
	movl	68(%r12), %edi
	callq	_OUT_RING
	movl	64(%r12), %edi
	callq	_OUT_RING
	movl	60(%r12), %edi
	callq	_OUT_RING
	movq	_RADEON_PP_BORDER_COLOR_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%ebx, %ebx
	xorl	%esi, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movl	56(%r12), %edi
	callq	_OUT_RING
	xorl	%eax, %eax
	callq	_ADVANCE_RING
	jmp	LBB0_33
	.cfi_endproc
                                        ## -- End function
	.comm	_RING_LOCALS,4,2                ## @RING_LOCALS
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"dirty=0x%08x\n"

	.comm	_RADEON_UPLOAD_CONTEXT,4,2      ## @RADEON_UPLOAD_CONTEXT
L_.str.1:                               ## @.str.1
	.asciz	"Invalid depth buffer offset\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_RADEON_PP_MISC,4,2             ## @RADEON_PP_MISC
	.comm	_RADEON_PP_CNTL,4,2             ## @RADEON_PP_CNTL
	.comm	_RADEON_RB3D_COLORPITCH,4,2     ## @RADEON_RB3D_COLORPITCH
	.comm	_RADEON_UPLOAD_VERTFMT,4,2      ## @RADEON_UPLOAD_VERTFMT
	.comm	_RADEON_SE_COORD_FMT,4,2        ## @RADEON_SE_COORD_FMT
	.comm	_RADEON_UPLOAD_LINE,4,2         ## @RADEON_UPLOAD_LINE
	.comm	_RADEON_RE_LINE_PATTERN,4,2     ## @RADEON_RE_LINE_PATTERN
	.comm	_RADEON_SE_LINE_WIDTH,4,2       ## @RADEON_SE_LINE_WIDTH
	.comm	_RADEON_UPLOAD_BUMPMAP,4,2      ## @RADEON_UPLOAD_BUMPMAP
	.comm	_RADEON_PP_LUM_MATRIX,4,2       ## @RADEON_PP_LUM_MATRIX
	.comm	_RADEON_PP_ROT_MATRIX_0,4,2     ## @RADEON_PP_ROT_MATRIX_0
	.comm	_RADEON_UPLOAD_MASKS,4,2        ## @RADEON_UPLOAD_MASKS
	.comm	_RADEON_RB3D_STENCILREFMASK,4,2 ## @RADEON_RB3D_STENCILREFMASK
	.comm	_RADEON_UPLOAD_VIEWPORT,4,2     ## @RADEON_UPLOAD_VIEWPORT
	.comm	_RADEON_SE_VPORT_XSCALE,4,2     ## @RADEON_SE_VPORT_XSCALE
	.comm	_RADEON_UPLOAD_SETUP,4,2        ## @RADEON_UPLOAD_SETUP
	.comm	_RADEON_SE_CNTL,4,2             ## @RADEON_SE_CNTL
	.comm	_RADEON_SE_CNTL_STATUS,4,2      ## @RADEON_SE_CNTL_STATUS
	.comm	_RADEON_UPLOAD_MISC,4,2         ## @RADEON_UPLOAD_MISC
	.comm	_RADEON_RE_MISC,4,2             ## @RADEON_RE_MISC
	.comm	_RADEON_UPLOAD_TEX0,4,2         ## @RADEON_UPLOAD_TEX0
L_.str.2:                               ## @.str.2
	.asciz	"Invalid texture offset for unit 0\n"

	.comm	_RADEON_PP_TXFILTER_0,4,2       ## @RADEON_PP_TXFILTER_0
	.comm	_RADEON_PP_BORDER_COLOR_0,4,2   ## @RADEON_PP_BORDER_COLOR_0
	.comm	_RADEON_UPLOAD_TEX1,4,2         ## @RADEON_UPLOAD_TEX1
L_.str.3:                               ## @.str.3
	.asciz	"Invalid texture offset for unit 1\n"

	.comm	_RADEON_PP_TXFILTER_1,4,2       ## @RADEON_PP_TXFILTER_1
	.comm	_RADEON_PP_BORDER_COLOR_1,4,2   ## @RADEON_PP_BORDER_COLOR_1
	.comm	_RADEON_UPLOAD_TEX2,4,2         ## @RADEON_UPLOAD_TEX2
L_.str.4:                               ## @.str.4
	.asciz	"Invalid texture offset for unit 2\n"

	.comm	_RADEON_PP_TXFILTER_2,4,2       ## @RADEON_PP_TXFILTER_2
	.comm	_RADEON_PP_BORDER_COLOR_2,4,2   ## @RADEON_PP_BORDER_COLOR_2
	.no_dead_strip	_radeon_emit_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_emit_state
_radeon_emit_state:                     ; @radeon_emit_state
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x22, x4
	mov	x19, x3
	mov	x23, x2
	mov	x20, x1
	mov	x21, x0
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	mov	x1, x4
	bl	_DRM_DEBUG
Lloh2:
	adrp	x8, _RADEON_UPLOAD_CONTEXT@GOTPAGE
Lloh3:
	ldr	x8, [x8, _RADEON_UPLOAD_CONTEXT@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_5
; %bb.1:
	add	x2, x23, #100
	mov	x0, x21
	mov	x1, x20
	bl	_radeon_check_and_fixup_offset
	cbnz	x0, LBB0_3
; %bb.2:
	add	x2, x23, #80
	mov	x0, x21
	mov	x1, x20
	bl	_radeon_check_and_fixup_offset
	cbz	x0, LBB0_4
LBB0_3:
Lloh5:
	adrp	x0, l_.str.1@PAGE
Lloh6:
	add	x0, x0, l_.str.1@PAGEOFF
	b	LBB0_30
LBB0_4:
	mov	w0, #14
	bl	_BEGIN_RING
Lloh7:
	adrp	x8, _RADEON_PP_MISC@GOTPAGE
Lloh8:
	ldr	x8, [x8, _RADEON_PP_MISC@GOTPAGEOFF]
Lloh9:
	ldr	w0, [x8]
	mov	w1, #6
	bl	_CP_PACKET0
	bl	_OUT_RING
	ldr	w0, [x23, #116]
	bl	_OUT_RING
	ldr	w0, [x23, #112]
	bl	_OUT_RING
	ldr	w0, [x23, #108]
	bl	_OUT_RING
	ldr	w0, [x23, #104]
	bl	_OUT_RING
	ldr	w0, [x23, #100]
	bl	_OUT_RING
	ldr	w0, [x23, #96]
	bl	_OUT_RING
	ldr	w0, [x23, #92]
	bl	_OUT_RING
Lloh10:
	adrp	x8, _RADEON_PP_CNTL@GOTPAGE
Lloh11:
	ldr	x8, [x8, _RADEON_PP_CNTL@GOTPAGEOFF]
Lloh12:
	ldr	w0, [x8]
	mov	w1, #2
	bl	_CP_PACKET0
	bl	_OUT_RING
	ldr	w0, [x23, #88]
	bl	_OUT_RING
	ldr	w0, [x23, #84]
	bl	_OUT_RING
	ldr	w0, [x23, #80]
	bl	_OUT_RING
Lloh13:
	adrp	x8, _RADEON_RB3D_COLORPITCH@GOTPAGE
Lloh14:
	ldr	x8, [x8, _RADEON_RB3D_COLORPITCH@GOTPAGEOFF]
Lloh15:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_CP_PACKET0
	bl	_OUT_RING
	ldr	w0, [x23, #76]
	bl	_OUT_RING
	bl	_ADVANCE_RING
LBB0_5:
Lloh16:
	adrp	x8, _RADEON_UPLOAD_VERTFMT@GOTPAGE
Lloh17:
	ldr	x8, [x8, _RADEON_UPLOAD_VERTFMT@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_7
; %bb.6:
	mov	w0, #2
	bl	_BEGIN_RING
Lloh19:
	adrp	x8, _RADEON_SE_COORD_FMT@GOTPAGE
Lloh20:
	ldr	x8, [x8, _RADEON_SE_COORD_FMT@GOTPAGEOFF]
Lloh21:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_CP_PACKET0
	bl	_OUT_RING
	ldr	w0, [x23, #72]
	bl	_OUT_RING
	bl	_ADVANCE_RING
LBB0_7:
Lloh22:
	adrp	x8, _RADEON_UPLOAD_LINE@GOTPAGE
Lloh23:
	ldr	x8, [x8, _RADEON_UPLOAD_LINE@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_9
; %bb.8:
	mov	w0, #5
	bl	_BEGIN_RING
Lloh25:
	adrp	x8, _RADEON_RE_LINE_PATTERN@GOTPAGE
Lloh26:
	ldr	x8, [x8, _RADEON_RE_LINE_PATTERN@GOTPAGEOFF]
Lloh27:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_CP_PACKET0
	bl	_OUT_RING
	ldr	w0, [x23, #68]
	bl	_OUT_RING
	ldr	w0, [x23, #64]
	bl	_OUT_RING
Lloh28:
	adrp	x8, _RADEON_SE_LINE_WIDTH@GOTPAGE
Lloh29:
	ldr	x8, [x8, _RADEON_SE_LINE_WIDTH@GOTPAGEOFF]
Lloh30:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_CP_PACKET0
	bl	_OUT_RING
	ldr	w0, [x23, #60]
	bl	_OUT_RING
	bl	_ADVANCE_RING
LBB0_9:
Lloh31:
	adrp	x8, _RADEON_UPLOAD_BUMPMAP@GOTPAGE
Lloh32:
	ldr	x8, [x8, _RADEON_UPLOAD_BUMPMAP@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_11
; %bb.10:
	mov	w0, #5
	bl	_BEGIN_RING
Lloh34:
	adrp	x8, _RADEON_PP_LUM_MATRIX@GOTPAGE
Lloh35:
	ldr	x8, [x8, _RADEON_PP_LUM_MATRIX@GOTPAGEOFF]
Lloh36:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_CP_PACKET0
	bl	_OUT_RING
	ldr	w0, [x23, #56]
	bl	_OUT_RING
Lloh37:
	adrp	x8, _RADEON_PP_ROT_MATRIX_0@GOTPAGE
Lloh38:
	ldr	x8, [x8, _RADEON_PP_ROT_MATRIX_0@GOTPAGEOFF]
Lloh39:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_CP_PACKET0
	bl	_OUT_RING
	ldr	w0, [x23, #52]
	bl	_OUT_RING
	ldr	w0, [x23, #48]
	bl	_OUT_RING
	bl	_ADVANCE_RING
LBB0_11:
Lloh40:
	adrp	x8, _RADEON_UPLOAD_MASKS@GOTPAGE
Lloh41:
	ldr	x8, [x8, _RADEON_UPLOAD_MASKS@GOTPAGEOFF]
Lloh42:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_13
; %bb.12:
	mov	w0, #4
	bl	_BEGIN_RING
Lloh43:
	adrp	x8, _RADEON_RB3D_STENCILREFMASK@GOTPAGE
Lloh44:
	ldr	x8, [x8, _RADEON_RB3D_STENCILREFMASK@GOTPAGEOFF]
Lloh45:
	ldr	w0, [x8]
	mov	w1, #2
	bl	_CP_PACKET0
	bl	_OUT_RING
	ldr	w0, [x23, #44]
	bl	_OUT_RING
	ldr	w0, [x23, #40]
	bl	_OUT_RING
	ldr	w0, [x23, #36]
	bl	_OUT_RING
	bl	_ADVANCE_RING
LBB0_13:
Lloh46:
	adrp	x8, _RADEON_UPLOAD_VIEWPORT@GOTPAGE
Lloh47:
	ldr	x8, [x8, _RADEON_UPLOAD_VIEWPORT@GOTPAGEOFF]
Lloh48:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_15
; %bb.14:
	mov	w0, #7
	bl	_BEGIN_RING
Lloh49:
	adrp	x8, _RADEON_SE_VPORT_XSCALE@GOTPAGE
Lloh50:
	ldr	x8, [x8, _RADEON_SE_VPORT_XSCALE@GOTPAGEOFF]
Lloh51:
	ldr	w0, [x8]
	mov	w1, #5
	bl	_CP_PACKET0
	bl	_OUT_RING
	ldr	w0, [x23, #32]
	bl	_OUT_RING
	ldr	w0, [x23, #28]
	bl	_OUT_RING
	ldr	w0, [x23, #24]
	bl	_OUT_RING
	ldr	w0, [x23, #20]
	bl	_OUT_RING
	ldr	w0, [x23, #16]
	bl	_OUT_RING
	ldr	w0, [x23, #12]
	bl	_OUT_RING
	bl	_ADVANCE_RING
LBB0_15:
Lloh52:
	adrp	x8, _RADEON_UPLOAD_SETUP@GOTPAGE
Lloh53:
	ldr	x8, [x8, _RADEON_UPLOAD_SETUP@GOTPAGEOFF]
Lloh54:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_17
; %bb.16:
	mov	w0, #4
	bl	_BEGIN_RING
Lloh55:
	adrp	x8, _RADEON_SE_CNTL@GOTPAGE
Lloh56:
	ldr	x8, [x8, _RADEON_SE_CNTL@GOTPAGEOFF]
Lloh57:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_CP_PACKET0
	bl	_OUT_RING
	ldr	w0, [x23, #8]
	bl	_OUT_RING
Lloh58:
	adrp	x8, _RADEON_SE_CNTL_STATUS@GOTPAGE
Lloh59:
	ldr	x8, [x8, _RADEON_SE_CNTL_STATUS@GOTPAGEOFF]
Lloh60:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_CP_PACKET0
	bl	_OUT_RING
	ldr	w0, [x23, #4]
	bl	_OUT_RING
	bl	_ADVANCE_RING
LBB0_17:
Lloh61:
	adrp	x8, _RADEON_UPLOAD_MISC@GOTPAGE
Lloh62:
	ldr	x8, [x8, _RADEON_UPLOAD_MISC@GOTPAGEOFF]
Lloh63:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_19
; %bb.18:
	mov	w0, #2
	bl	_BEGIN_RING
Lloh64:
	adrp	x8, _RADEON_RE_MISC@GOTPAGE
Lloh65:
	ldr	x8, [x8, _RADEON_RE_MISC@GOTPAGEOFF]
Lloh66:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_CP_PACKET0
	bl	_OUT_RING
	ldr	w0, [x23]
	bl	_OUT_RING
	bl	_ADVANCE_RING
LBB0_19:
Lloh67:
	adrp	x8, _RADEON_UPLOAD_TEX0@GOTPAGE
Lloh68:
	ldr	x8, [x8, _RADEON_UPLOAD_TEX0@GOTPAGEOFF]
Lloh69:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_23
; %bb.20:
	add	x2, x19, #16
	mov	x0, x21
	mov	x1, x20
	bl	_radeon_check_and_fixup_offset
	cbz	x0, LBB0_22
; %bb.21:
Lloh70:
	adrp	x0, l_.str.2@PAGE
Lloh71:
	add	x0, x0, l_.str.2@PAGEOFF
	b	LBB0_30
LBB0_22:
	mov	w0, #9
	bl	_BEGIN_RING
Lloh72:
	adrp	x8, _RADEON_PP_TXFILTER_0@GOTPAGE
Lloh73:
	ldr	x8, [x8, _RADEON_PP_TXFILTER_0@GOTPAGEOFF]
Lloh74:
	ldr	w0, [x8]
	mov	w1, #5
	bl	_CP_PACKET0
	bl	_OUT_RING
	ldr	w0, [x19, #24]
	bl	_OUT_RING
	ldr	w0, [x19, #20]
	bl	_OUT_RING
	ldr	w0, [x19, #16]
	bl	_OUT_RING
	ldr	w0, [x19, #12]
	bl	_OUT_RING
	ldr	w0, [x19, #8]
	bl	_OUT_RING
	ldr	w0, [x19, #4]
	bl	_OUT_RING
Lloh75:
	adrp	x8, _RADEON_PP_BORDER_COLOR_0@GOTPAGE
Lloh76:
	ldr	x8, [x8, _RADEON_PP_BORDER_COLOR_0@GOTPAGEOFF]
Lloh77:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_CP_PACKET0
	bl	_OUT_RING
	ldr	w0, [x19]
	bl	_OUT_RING
	bl	_ADVANCE_RING
LBB0_23:
Lloh78:
	adrp	x8, _RADEON_UPLOAD_TEX1@GOTPAGE
Lloh79:
	ldr	x8, [x8, _RADEON_UPLOAD_TEX1@GOTPAGEOFF]
Lloh80:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_27
; %bb.24:
	add	x2, x19, #44
	mov	x0, x21
	mov	x1, x20
	bl	_radeon_check_and_fixup_offset
	cbz	x0, LBB0_26
; %bb.25:
Lloh81:
	adrp	x0, l_.str.3@PAGE
Lloh82:
	add	x0, x0, l_.str.3@PAGEOFF
	b	LBB0_30
LBB0_26:
	mov	w0, #9
	bl	_BEGIN_RING
Lloh83:
	adrp	x8, _RADEON_PP_TXFILTER_1@GOTPAGE
Lloh84:
	ldr	x8, [x8, _RADEON_PP_TXFILTER_1@GOTPAGEOFF]
Lloh85:
	ldr	w0, [x8]
	mov	w1, #5
	bl	_CP_PACKET0
	bl	_OUT_RING
	ldr	w0, [x19, #52]
	bl	_OUT_RING
	ldr	w0, [x19, #48]
	bl	_OUT_RING
	ldr	w0, [x19, #44]
	bl	_OUT_RING
	ldr	w0, [x19, #40]
	bl	_OUT_RING
	ldr	w0, [x19, #36]
	bl	_OUT_RING
	ldr	w0, [x19, #32]
	bl	_OUT_RING
Lloh86:
	adrp	x8, _RADEON_PP_BORDER_COLOR_1@GOTPAGE
Lloh87:
	ldr	x8, [x8, _RADEON_PP_BORDER_COLOR_1@GOTPAGEOFF]
Lloh88:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_CP_PACKET0
	bl	_OUT_RING
	ldr	w0, [x19, #28]
	bl	_OUT_RING
	bl	_ADVANCE_RING
LBB0_27:
Lloh89:
	adrp	x8, _RADEON_UPLOAD_TEX2@GOTPAGE
Lloh90:
	ldr	x8, [x8, _RADEON_UPLOAD_TEX2@GOTPAGEOFF]
Lloh91:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_33
; %bb.28:
	add	x2, x19, #72
	mov	x0, x21
	mov	x1, x20
	bl	_radeon_check_and_fixup_offset
	cbz	x0, LBB0_32
; %bb.29:
Lloh92:
	adrp	x0, l_.str.4@PAGE
Lloh93:
	add	x0, x0, l_.str.4@PAGEOFF
LBB0_30:
	bl	_DRM_ERROR
Lloh94:
	adrp	x8, _EINVAL@GOTPAGE
Lloh95:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh96:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_31:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_32:
	mov	w0, #9
	bl	_BEGIN_RING
Lloh97:
	adrp	x8, _RADEON_PP_TXFILTER_2@GOTPAGE
Lloh98:
	ldr	x8, [x8, _RADEON_PP_TXFILTER_2@GOTPAGEOFF]
Lloh99:
	ldr	w0, [x8]
	mov	w1, #5
	bl	_CP_PACKET0
	bl	_OUT_RING
	ldr	w0, [x19, #80]
	bl	_OUT_RING
	ldr	w0, [x19, #76]
	bl	_OUT_RING
	ldr	w0, [x19, #72]
	bl	_OUT_RING
	ldr	w0, [x19, #68]
	bl	_OUT_RING
	ldr	w0, [x19, #64]
	bl	_OUT_RING
	ldr	w0, [x19, #60]
	bl	_OUT_RING
Lloh100:
	adrp	x8, _RADEON_PP_BORDER_COLOR_2@GOTPAGE
Lloh101:
	ldr	x8, [x8, _RADEON_PP_BORDER_COLOR_2@GOTPAGEOFF]
Lloh102:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_CP_PACKET0
	bl	_OUT_RING
	ldr	w0, [x19, #56]
	bl	_OUT_RING
	bl	_ADVANCE_RING
LBB0_33:
	mov	w0, #0
	b	LBB0_31
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpAdd	Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpAdd	Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpAdd	Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.cfi_endproc
                                        ; -- End function
	.comm	_RING_LOCALS,4,2                ; @RING_LOCALS
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"dirty=0x%08x\n"

	.comm	_RADEON_UPLOAD_CONTEXT,4,2      ; @RADEON_UPLOAD_CONTEXT
l_.str.1:                               ; @.str.1
	.asciz	"Invalid depth buffer offset\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_RADEON_PP_MISC,4,2             ; @RADEON_PP_MISC
	.comm	_RADEON_PP_CNTL,4,2             ; @RADEON_PP_CNTL
	.comm	_RADEON_RB3D_COLORPITCH,4,2     ; @RADEON_RB3D_COLORPITCH
	.comm	_RADEON_UPLOAD_VERTFMT,4,2      ; @RADEON_UPLOAD_VERTFMT
	.comm	_RADEON_SE_COORD_FMT,4,2        ; @RADEON_SE_COORD_FMT
	.comm	_RADEON_UPLOAD_LINE,4,2         ; @RADEON_UPLOAD_LINE
	.comm	_RADEON_RE_LINE_PATTERN,4,2     ; @RADEON_RE_LINE_PATTERN
	.comm	_RADEON_SE_LINE_WIDTH,4,2       ; @RADEON_SE_LINE_WIDTH
	.comm	_RADEON_UPLOAD_BUMPMAP,4,2      ; @RADEON_UPLOAD_BUMPMAP
	.comm	_RADEON_PP_LUM_MATRIX,4,2       ; @RADEON_PP_LUM_MATRIX
	.comm	_RADEON_PP_ROT_MATRIX_0,4,2     ; @RADEON_PP_ROT_MATRIX_0
	.comm	_RADEON_UPLOAD_MASKS,4,2        ; @RADEON_UPLOAD_MASKS
	.comm	_RADEON_RB3D_STENCILREFMASK,4,2 ; @RADEON_RB3D_STENCILREFMASK
	.comm	_RADEON_UPLOAD_VIEWPORT,4,2     ; @RADEON_UPLOAD_VIEWPORT
	.comm	_RADEON_SE_VPORT_XSCALE,4,2     ; @RADEON_SE_VPORT_XSCALE
	.comm	_RADEON_UPLOAD_SETUP,4,2        ; @RADEON_UPLOAD_SETUP
	.comm	_RADEON_SE_CNTL,4,2             ; @RADEON_SE_CNTL
	.comm	_RADEON_SE_CNTL_STATUS,4,2      ; @RADEON_SE_CNTL_STATUS
	.comm	_RADEON_UPLOAD_MISC,4,2         ; @RADEON_UPLOAD_MISC
	.comm	_RADEON_RE_MISC,4,2             ; @RADEON_RE_MISC
	.comm	_RADEON_UPLOAD_TEX0,4,2         ; @RADEON_UPLOAD_TEX0
l_.str.2:                               ; @.str.2
	.asciz	"Invalid texture offset for unit 0\n"

	.comm	_RADEON_PP_TXFILTER_0,4,2       ; @RADEON_PP_TXFILTER_0
	.comm	_RADEON_PP_BORDER_COLOR_0,4,2   ; @RADEON_PP_BORDER_COLOR_0
	.comm	_RADEON_UPLOAD_TEX1,4,2         ; @RADEON_UPLOAD_TEX1
l_.str.3:                               ; @.str.3
	.asciz	"Invalid texture offset for unit 1\n"

	.comm	_RADEON_PP_TXFILTER_1,4,2       ; @RADEON_PP_TXFILTER_1
	.comm	_RADEON_PP_BORDER_COLOR_1,4,2   ; @RADEON_PP_BORDER_COLOR_1
	.comm	_RADEON_UPLOAD_TEX2,4,2         ; @RADEON_UPLOAD_TEX2
l_.str.4:                               ; @.str.4
	.asciz	"Invalid texture offset for unit 2\n"

	.comm	_RADEON_PP_TXFILTER_2,4,2       ; @RADEON_PP_TXFILTER_2
	.comm	_RADEON_PP_BORDER_COLOR_2,4,2   ; @RADEON_PP_BORDER_COLOR_2
	.no_dead_strip	_radeon_emit_state
.subsections_via_symbols
