	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_wb_init                 ## -- Begin function radeon_wb_init
	.p2align	4, 0x90
_radeon_wb_init:                        ## @radeon_wb_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	32(%rdi), %rdi
	testq	%rdi, %rdi
	je	LBB0_1
LBB0_3:
	xorl	%esi, %esi
	callq	_radeon_bo_reserve
	movl	%eax, %ebx
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	callq	_unlikely
	testq	%rax, %rax
	jne	LBB0_4
## %bb.5:
	movq	32(%r14), %rdi
	movq	_RADEON_GEM_DOMAIN_GTT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	40(%r14), %rdx
	callq	_radeon_bo_pin
	movq	32(%r14), %rdi
	testl	%eax, %eax
	je	LBB0_7
## %bb.6:
	movl	%eax, %ebx
	callq	_radeon_bo_unreserve
	movl	48(%r14), %edi
	leaq	L_.str.1(%rip), %rsi
	jmp	LBB0_9
LBB0_1:
	leaq	32(%r14), %r15
	movq	_RADEON_GPU_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_RADEON_GEM_DOMAIN_GTT@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	movq	%r15, (%rsp)
	movq	%r14, %rdi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	_radeon_bo_create
	testl	%eax, %eax
	je	LBB0_2
## %bb.20:
	movl	%eax, %ebx
	movl	48(%r14), %edi
	leaq	L_.str(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_warn
	jmp	LBB0_19
LBB0_2:
	movq	(%r15), %rdi
	jmp	LBB0_3
LBB0_7:
	leaq	24(%r14), %rsi
	callq	_radeon_bo_kmap
	movl	%eax, %ebx
	movq	32(%r14), %rdi
	callq	_radeon_bo_unreserve
	testl	%ebx, %ebx
	je	LBB0_10
## %bb.8:
	movl	48(%r14), %edi
	leaq	L_.str.2(%rip), %rsi
LBB0_9:
	movl	%ebx, %edx
	callq	_dev_warn
LBB0_4:
	movq	%r14, %rdi
	callq	_radeon_wb_fini
LBB0_19:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_10:
	movq	24(%r14), %rdi
	movq	_RADEON_GPU_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_memset
	movl	$0, 16(%r14)
	movq	_radeon_no_wb@GOTPCREL(%rip), %rax
	cmpl	$1, (%rax)
	je	LBB0_11
## %bb.12:
	movq	_RADEON_IS_AGP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r14)
	jne	LBB0_11
## %bb.13:
	movq	8(%r14), %rax
	movq	_CHIP_R300@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_14
LBB0_11:
	movl	$0, 20(%r14)
	leaq	L_.str.5(%rip), %rdx
LBB0_16:
	movq	8(%r14), %rax
	movq	_CHIP_PALM@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_18
## %bb.17:
	movabsq	$4294967297, %rax               ## imm = 0x100000001
	movq	%rax, 16(%r14)
	leaq	L_.str.4(%rip), %rdx
LBB0_18:
	movl	48(%r14), %edi
	leaq	L_.str.3(%rip), %rsi
	callq	_dev_info
	xorl	%ebx, %ebx
	jmp	LBB0_19
LBB0_14:
	movl	$1, 20(%r14)
	movq	_CHIP_R600@GOTPCREL(%rip), %rcx
	leaq	L_.str.4(%rip), %rdx
	cmpq	(%rcx), %rax
	jl	LBB0_16
## %bb.15:
	movl	$1, 16(%r14)
	jmp	LBB0_16
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_GPU_PAGE_SIZE,4,2       ## @RADEON_GPU_PAGE_SIZE
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
	.comm	_RADEON_GEM_DOMAIN_GTT,4,2      ## @RADEON_GEM_DOMAIN_GTT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"(%d) create WB bo failed\n"

L_.str.1:                               ## @.str.1
	.asciz	"(%d) pin WB bo failed\n"

L_.str.2:                               ## @.str.2
	.asciz	"(%d) map WB bo failed\n"

	.comm	_radeon_no_wb,4,2               ## @radeon_no_wb
	.comm	_RADEON_IS_AGP,4,2              ## @RADEON_IS_AGP
	.comm	_CHIP_R300,8,3                  ## @CHIP_R300
	.comm	_CHIP_R600,8,3                  ## @CHIP_R600
	.comm	_CHIP_PALM,8,3                  ## @CHIP_PALM
L_.str.3:                               ## @.str.3
	.asciz	"WB %sabled\n"

L_.str.4:                               ## @.str.4
	.asciz	"en"

L_.str.5:                               ## @.str.5
	.asciz	"dis"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_wb_init                 ; -- Begin function radeon_wb_init
	.p2align	2
_radeon_wb_init:                        ; @radeon_wb_init
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	mov	x21, x0
	ldr	x0, [x21, #32]!
	cbz	x0, LBB0_4
LBB0_1:
	mov	w1, #0
	bl	_radeon_bo_reserve
	mov	x20, x0
	cmp	w0, #0
	cset	w0, ne
	bl	_unlikely
	cbnz	x0, LBB0_10
; %bb.2:
	ldr	x0, [x19, #32]
Lloh0:
	adrp	x8, _RADEON_GEM_DOMAIN_GTT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_GEM_DOMAIN_GTT@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	add	x2, x19, #40
	bl	_radeon_bo_pin
	mov	x20, x0
	ldr	x0, [x19, #32]
	cbz	w20, LBB0_7
; %bb.3:
	bl	_radeon_bo_unreserve
	ldr	w0, [x19, #48]
Lloh3:
	adrp	x1, l_.str.1@PAGE
Lloh4:
	add	x1, x1, l_.str.1@PAGEOFF
	b	LBB0_9
LBB0_4:
Lloh5:
	adrp	x8, _RADEON_GPU_PAGE_SIZE@GOTPAGE
Lloh6:
	ldr	x8, [x8, _RADEON_GPU_PAGE_SIZE@GOTPAGEOFF]
Lloh7:
	ldr	w1, [x8]
Lloh8:
	adrp	x8, _PAGE_SIZE@GOTPAGE
Lloh9:
	ldr	x8, [x8, _PAGE_SIZE@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
Lloh11:
	adrp	x8, _RADEON_GEM_DOMAIN_GTT@GOTPAGE
Lloh12:
	ldr	x8, [x8, _RADEON_GEM_DOMAIN_GTT@GOTPAGEOFF]
Lloh13:
	ldr	w4, [x8]
	mov	x0, x19
	mov	w3, #1
	mov	x5, #0
	mov	x6, x21
	bl	_radeon_bo_create
	cbz	w0, LBB0_6
; %bb.5:
	mov	x20, x0
	ldr	w0, [x19, #48]
Lloh14:
	adrp	x1, l_.str@PAGE
Lloh15:
	add	x1, x1, l_.str@PAGEOFF
	mov	x2, x20
	bl	_dev_warn
	b	LBB0_11
LBB0_6:
	ldr	x0, [x21]
	b	LBB0_1
LBB0_7:
	add	x1, x19, #24
	bl	_radeon_bo_kmap
	mov	x20, x0
	ldr	x0, [x19, #32]
	bl	_radeon_bo_unreserve
	cbz	w20, LBB0_12
; %bb.8:
	ldr	w0, [x19, #48]
Lloh16:
	adrp	x1, l_.str.2@PAGE
Lloh17:
	add	x1, x1, l_.str.2@PAGEOFF
LBB0_9:
	mov	x2, x20
	bl	_dev_warn
LBB0_10:
	mov	x0, x19
	bl	_radeon_wb_fini
LBB0_11:
	mov	x0, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_12:
	ldr	x0, [x19, #24]
Lloh18:
	adrp	x8, _RADEON_GPU_PAGE_SIZE@GOTPAGE
Lloh19:
	ldr	x8, [x8, _RADEON_GPU_PAGE_SIZE@GOTPAGEOFF]
Lloh20:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_memset
	str	wzr, [x19, #16]
Lloh21:
	adrp	x8, _radeon_no_wb@GOTPAGE
Lloh22:
	ldr	x8, [x8, _radeon_no_wb@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	cmp	w8, #1
	b.eq	LBB0_15
; %bb.13:
	ldr	w8, [x19]
Lloh24:
	adrp	x9, _RADEON_IS_AGP@GOTPAGE
Lloh25:
	ldr	x9, [x9, _RADEON_IS_AGP@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_15
; %bb.14:
	ldr	x8, [x19, #8]
Lloh27:
	adrp	x9, _CHIP_R300@GOTPAGE
Lloh28:
	ldr	x9, [x9, _CHIP_R300@GOTPAGEOFF]
Lloh29:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_19
LBB0_15:
	str	wzr, [x19, #20]
Lloh30:
	adrp	x2, l_.str.5@PAGE
Lloh31:
	add	x2, x2, l_.str.5@PAGEOFF
LBB0_16:
	ldr	x8, [x19, #8]
Lloh32:
	adrp	x9, _CHIP_PALM@GOTPAGE
Lloh33:
	ldr	x9, [x9, _CHIP_PALM@GOTPAGEOFF]
Lloh34:
	ldr	x9, [x9]
	cmp	x8, x9
	b.lt	LBB0_18
; %bb.17:
	movi.2s	v0, #1
	str	d0, [x19, #16]
Lloh35:
	adrp	x2, l_.str.4@PAGE
Lloh36:
	add	x2, x2, l_.str.4@PAGEOFF
LBB0_18:
	ldr	w0, [x19, #48]
Lloh37:
	adrp	x1, l_.str.3@PAGE
Lloh38:
	add	x1, x1, l_.str.3@PAGEOFF
	bl	_dev_info
	mov	w20, #0
	b	LBB0_11
LBB0_19:
	mov	w9, #1
	str	w9, [x19, #20]
Lloh39:
	adrp	x10, _CHIP_R600@GOTPAGE
Lloh40:
	ldr	x10, [x10, _CHIP_R600@GOTPAGEOFF]
Lloh41:
	ldr	x10, [x10]
	cmp	x8, x10
	b.lt	LBB0_21
; %bb.20:
	str	w9, [x19, #16]
LBB0_21:
Lloh42:
	adrp	x2, l_.str.4@PAGE
Lloh43:
	add	x2, x2, l_.str.4@PAGEOFF
	b	LBB0_16
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpAdd	Lloh14, Lloh15
	.loh AdrpAdd	Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpAdd	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpAdd	Lloh35, Lloh36
	.loh AdrpAdd	Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpAdd	Lloh42, Lloh43
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_GPU_PAGE_SIZE,4,2       ; @RADEON_GPU_PAGE_SIZE
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
	.comm	_RADEON_GEM_DOMAIN_GTT,4,2      ; @RADEON_GEM_DOMAIN_GTT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"(%d) create WB bo failed\n"

l_.str.1:                               ; @.str.1
	.asciz	"(%d) pin WB bo failed\n"

l_.str.2:                               ; @.str.2
	.asciz	"(%d) map WB bo failed\n"

	.comm	_radeon_no_wb,4,2               ; @radeon_no_wb
	.comm	_RADEON_IS_AGP,4,2              ; @RADEON_IS_AGP
	.comm	_CHIP_R300,8,3                  ; @CHIP_R300
	.comm	_CHIP_R600,8,3                  ; @CHIP_R600
	.comm	_CHIP_PALM,8,3                  ; @CHIP_PALM
l_.str.3:                               ; @.str.3
	.asciz	"WB %sabled\n"

l_.str.4:                               ; @.str.4
	.asciz	"en"

l_.str.5:                               ; @.str.5
	.asciz	"dis"

.subsections_via_symbols
