	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vlv_update_pll
_vlv_update_pll:                        ## @vlv_update_pll
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rcx, %r12
	movq	%rdx, -56(%rbp)                 ## 8-byte Spill
	movq	%rsi, -72(%rbp)                 ## 8-byte Spill
	movq	%rdi, %r15
	movq	(%rdi), %rax
	movq	(%rax), %rbx
	callq	_to_intel_crtc
	movl	(%rax), %r14d
	movq	%rbx, -80(%rbp)                 ## 8-byte Spill
	movq	%rbx, %rdi
	callq	_mutex_lock
	movq	_INTEL_OUTPUT_SDVO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_intel_pipe_has_type
	movb	$1, %cl
	testq	%rax, %rax
	jne	LBB0_2
## %bb.1:
	movq	_INTEL_OUTPUT_HDMI@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_intel_pipe_has_type
	testq	%rax, %rax
	setne	%cl
LBB0_2:
	movb	%cl, -41(%rbp)                  ## 1-byte Spill
	movq	%r15, -64(%rbp)                 ## 8-byte Spill
	movq	_DPLL_VGA_MODE_DIS@GOTPCREL(%rip), %rax
	movq	_DPLL_EXT_BUFFER_ENABLE_VLV@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r13d
	orl	(%rax), %r13d
	movq	_DPLL_REFA_CLK_ENABLE_VLV@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	movq	_DPLL_INTEGRATED_CLOCK_VLV@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	movl	%r14d, %edi
	callq	_DPLL
	movl	%eax, %edi
	movl	%r13d, %esi
	callq	_I915_WRITE
	movl	%r14d, %edi
	callq	_DPLL
	movl	%eax, %edi
	callq	_POSTING_READ
	movl	(%r12), %r15d
	movl	4(%r12), %edx
	movl	12(%r12), %eax
	movq	_DPIO_M1DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	movq	_DPIO_M2DIV_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	andl	8(%r12), %esi
	movq	_DPIO_P1_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	movl	16(%r12), %edi
	orl	%edx, %esi
	movq	_DPIO_P2_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edi
	movq	_DPIO_N_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r15d
	orl	%eax, %edi
	orl	%esi, %edi
	orl	%edi, %r15d
	movq	_DPIO_POST_DIV_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	movq	_DPIO_K_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movq	_DPIO_ENABLE_CALIBRATION@GOTPCREL(%rip), %rdx
	btsl	%eax, %r15d
	btsl	%ecx, %r15d
	orl	(%rdx), %r15d
	movl	%r14d, %edi
	callq	_DPIO_DIV
	movq	-80(%rbp), %r12                 ## 8-byte Reload
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	%r15d, %edx
	callq	_intel_dpio_write
	movl	%r14d, %edi
	callq	_DPIO_CORE_CLK
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$16777216, %edx                 ## imm = 0x1000000
	callq	_intel_dpio_write
	movq	_DPIO_PLL_MODESEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$5, %ebx
	shll	%cl, %ebx
	movq	_DPIO_BIAS_CURRENT_CTL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$3, %eax
	shll	%cl, %eax
	movq	_DPIO_PLL_REFCLK_SEL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$7, %edx
	shll	%cl, %edx
	movq	_DPIO_REFSEL_OVERRIDE@GOTPCREL(%rip), %rcx
	movb	(%rcx), %r8b
	movq	_DPIO_DRIVER_CTL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$8, %edi
	shll	%cl, %edi
	movl	$5, %esi
	orl	%eax, %edx
	movq	_DPIO_CLK_BIAS_CTL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %esi
	orl	%edi, %esi
	btsl	%r8d, %ebx
	orl	%edx, %ebx
	orl	%esi, %ebx
	orl	$1048576, %ebx                  ## imm = 0x100000
	movl	%r14d, %edi
	callq	_DPIO_REFSFR
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	%ebx, %edx
	callq	_intel_dpio_write
	movl	%r14d, %edi
	callq	_DPIO_LFP_COEFF
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$6225979, %edx                  ## imm = 0x5F003B
	callq	_intel_dpio_write
	movq	_DPLL_VCO_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	movl	%r14d, %edi
	callq	_DPLL
	movl	%eax, %edi
	movl	%r13d, %esi
	callq	_I915_WRITE
	movl	%r14d, %edi
	callq	_DPLL
	movl	%eax, %edi
	callq	_POSTING_READ
	movl	%r14d, %edi
	callq	_DPLL
	movl	%eax, %edi
	callq	_I915_READ
	movq	_DPLL_LOCK_VLV@GOTPCREL(%rip), %rcx
	notl	%eax
	xorl	%edi, %edi
	andl	(%rcx), %eax
	sete	%dil
	movl	$1, %esi
	callq	_wait_for
	testq	%rax, %rax
	je	LBB0_4
## %bb.3:
	leaq	L_.str(%rip), %rdi
	movl	%r14d, %esi
	callq	_DRM_ERROR
LBB0_4:
	movq	_DPIO_FASTCLK_DISABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$1568, %edx                     ## imm = 0x620
	callq	_intel_dpio_write
	movq	_INTEL_OUTPUT_DISPLAYPORT@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	callq	_intel_pipe_has_type
	testq	%rax, %rax
	je	LBB0_6
## %bb.5:
	movq	%rbx, %rdi
	movq	-72(%rbp), %rsi                 ## 8-byte Reload
	movq	-56(%rbp), %rdx                 ## 8-byte Reload
	callq	_intel_dp_set_m_n
LBB0_6:
	movl	%r14d, %edi
	callq	_DPLL
	movl	%eax, %edi
	movl	%r13d, %esi
	callq	_I915_WRITE
	movl	%r14d, %edi
	callq	_DPLL
	movl	%eax, %edi
	callq	_POSTING_READ
	movl	$150, %edi
	callq	_udelay
	xorl	%ebx, %ebx
	cmpb	$0, -41(%rbp)                   ## 1-byte Folded Reload
	je	LBB0_9
## %bb.7:
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_intel_mode_get_pixel_multiplier
	cmpl	$2, %eax
	jl	LBB0_9
## %bb.8:
	decl	%eax
	movq	_DPLL_MD_UDI_MULTIPLIER_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	movl	%eax, %ebx
LBB0_9:
	movl	%r14d, %edi
	callq	_DPLL_MD
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movl	%r14d, %edi
	callq	_DPLL_MD
	movl	%eax, %edi
	callq	_POSTING_READ
	movl	(%r15), %esi
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	callq	_intel_pipe_has_type
	testq	%rax, %rax
	jne	LBB0_11
## %bb.10:
	movq	_INTEL_OUTPUT_HDMI@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_intel_pipe_has_type
	testq	%rax, %rax
	je	LBB0_12
LBB0_11:
	xorl	%edx, %edx
	cmpl	$1, %r14d
	sete	%dl
	shll	$21, %edx
	orl	$1048772, %edx                  ## imm = 0x1000C4
	movq	_DPIO_DATA_CHANNEL1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_intel_dpio_write
LBB0_12:
	movq	_INTEL_OUTPUT_EDP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_intel_pipe_has_type
	testq	%rax, %rax
	je	LBB0_14
## %bb.13:
	xorl	%edx, %edx
	cmpl	$1, %r14d
	sete	%dl
	shll	$21, %edx
	orl	$1048772, %edx                  ## imm = 0x1000C4
	movq	_DPIO_DATA_CHANNEL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_intel_dpio_write
LBB0_14:
	movq	%r12, %rdi
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_mutex_unlock                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_INTEL_OUTPUT_SDVO,4,2          ## @INTEL_OUTPUT_SDVO
	.comm	_INTEL_OUTPUT_HDMI,4,2          ## @INTEL_OUTPUT_HDMI
	.comm	_DPLL_VGA_MODE_DIS,4,2          ## @DPLL_VGA_MODE_DIS
	.comm	_DPLL_EXT_BUFFER_ENABLE_VLV,4,2 ## @DPLL_EXT_BUFFER_ENABLE_VLV
	.comm	_DPLL_REFA_CLK_ENABLE_VLV,4,2   ## @DPLL_REFA_CLK_ENABLE_VLV
	.comm	_DPLL_INTEGRATED_CLOCK_VLV,4,2  ## @DPLL_INTEGRATED_CLOCK_VLV
	.comm	_DPIO_M1DIV_SHIFT,4,2           ## @DPIO_M1DIV_SHIFT
	.comm	_DPIO_M2DIV_MASK,4,2            ## @DPIO_M2DIV_MASK
	.comm	_DPIO_P1_SHIFT,4,2              ## @DPIO_P1_SHIFT
	.comm	_DPIO_P2_SHIFT,4,2              ## @DPIO_P2_SHIFT
	.comm	_DPIO_N_SHIFT,4,2               ## @DPIO_N_SHIFT
	.comm	_DPIO_POST_DIV_SHIFT,4,2        ## @DPIO_POST_DIV_SHIFT
	.comm	_DPIO_K_SHIFT,4,2               ## @DPIO_K_SHIFT
	.comm	_DPIO_ENABLE_CALIBRATION,4,2    ## @DPIO_ENABLE_CALIBRATION
	.comm	_DPIO_REFSEL_OVERRIDE,4,2       ## @DPIO_REFSEL_OVERRIDE
	.comm	_DPIO_PLL_MODESEL_SHIFT,4,2     ## @DPIO_PLL_MODESEL_SHIFT
	.comm	_DPIO_BIAS_CURRENT_CTL_SHIFT,4,2 ## @DPIO_BIAS_CURRENT_CTL_SHIFT
	.comm	_DPIO_PLL_REFCLK_SEL_SHIFT,4,2  ## @DPIO_PLL_REFCLK_SEL_SHIFT
	.comm	_DPIO_DRIVER_CTL_SHIFT,4,2      ## @DPIO_DRIVER_CTL_SHIFT
	.comm	_DPIO_CLK_BIAS_CTL_SHIFT,4,2    ## @DPIO_CLK_BIAS_CTL_SHIFT
	.comm	_DPLL_VCO_ENABLE,4,2            ## @DPLL_VCO_ENABLE
	.comm	_DPLL_LOCK_VLV,4,2              ## @DPLL_LOCK_VLV
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"DPLL %d failed to lock\n"

	.comm	_DPIO_FASTCLK_DISABLE,4,2       ## @DPIO_FASTCLK_DISABLE
	.comm	_INTEL_OUTPUT_DISPLAYPORT,4,2   ## @INTEL_OUTPUT_DISPLAYPORT
	.comm	_DPLL_MD_UDI_MULTIPLIER_SHIFT,4,2 ## @DPLL_MD_UDI_MULTIPLIER_SHIFT
	.comm	_DPIO_DATA_CHANNEL1,4,2         ## @DPIO_DATA_CHANNEL1
	.comm	_INTEL_OUTPUT_EDP,4,2           ## @INTEL_OUTPUT_EDP
	.comm	_DPIO_DATA_CHANNEL2,4,2         ## @DPIO_DATA_CHANNEL2
	.no_dead_strip	_vlv_update_pll
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vlv_update_pll
_vlv_update_pll:                        ; @vlv_update_pll
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x25, x3
	mov	x22, x2
	mov	x23, x1
	mov	x21, x0
	ldr	x8, [x0]
	ldr	x19, [x8]
	bl	_to_intel_crtc
	ldr	w20, [x0]
	mov	x0, x19
	bl	_mutex_lock
Lloh0:
	adrp	x8, _INTEL_OUTPUT_SDVO@GOTPAGE
Lloh1:
	ldr	x8, [x8, _INTEL_OUTPUT_SDVO@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x21
	bl	_intel_pipe_has_type
	mov	w27, #1
	mov	w26, #1
	cbnz	x0, LBB0_2
; %bb.1:
Lloh3:
	adrp	x8, _INTEL_OUTPUT_HDMI@GOTPAGE
Lloh4:
	ldr	x8, [x8, _INTEL_OUTPUT_HDMI@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x21
	bl	_intel_pipe_has_type
	cmp	x0, #0
	cset	w26, ne
LBB0_2:
Lloh6:
	adrp	x8, _DPLL_VGA_MODE_DIS@GOTPAGE
Lloh7:
	ldr	x8, [x8, _DPLL_VGA_MODE_DIS@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
Lloh9:
	adrp	x9, _DPLL_EXT_BUFFER_ENABLE_VLV@GOTPAGE
Lloh10:
	ldr	x9, [x9, _DPLL_EXT_BUFFER_ENABLE_VLV@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh12:
	adrp	x9, _DPLL_REFA_CLK_ENABLE_VLV@GOTPAGE
Lloh13:
	ldr	x9, [x9, _DPLL_REFA_CLK_ENABLE_VLV@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh15:
	adrp	x9, _DPLL_INTEGRATED_CLOCK_VLV@GOTPAGE
Lloh16:
	ldr	x9, [x9, _DPLL_INTEGRATED_CLOCK_VLV@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	orr	w24, w8, w9
	mov	x0, x20
	bl	_DPLL
	mov	x1, x24
	bl	_I915_WRITE
	mov	x0, x20
	bl	_DPLL
	bl	_POSTING_READ
	ldp	w8, w9, [x25]
	ldp	w10, w11, [x25, #8]
	ldr	w12, [x25, #16]
Lloh18:
	adrp	x13, _DPIO_M1DIV_SHIFT@GOTPAGE
Lloh19:
	ldr	x13, [x13, _DPIO_M1DIV_SHIFT@GOTPAGEOFF]
Lloh20:
	ldr	w13, [x13]
	lsl	w9, w9, w13
Lloh21:
	adrp	x13, _DPIO_M2DIV_MASK@GOTPAGE
Lloh22:
	ldr	x13, [x13, _DPIO_M2DIV_MASK@GOTPAGEOFF]
Lloh23:
	ldr	w13, [x13]
	and	w10, w13, w10
Lloh24:
	adrp	x13, _DPIO_P1_SHIFT@GOTPAGE
Lloh25:
	ldr	x13, [x13, _DPIO_P1_SHIFT@GOTPAGEOFF]
Lloh26:
	ldr	w13, [x13]
	lsl	w11, w11, w13
Lloh27:
	adrp	x13, _DPIO_P2_SHIFT@GOTPAGE
Lloh28:
	ldr	x13, [x13, _DPIO_P2_SHIFT@GOTPAGEOFF]
Lloh29:
	ldr	w13, [x13]
	lsl	w12, w12, w13
Lloh30:
	adrp	x13, _DPIO_N_SHIFT@GOTPAGE
Lloh31:
	ldr	x13, [x13, _DPIO_N_SHIFT@GOTPAGEOFF]
Lloh32:
	ldr	w13, [x13]
	lsl	w8, w8, w13
Lloh33:
	adrp	x13, _DPIO_POST_DIV_SHIFT@GOTPAGE
Lloh34:
	ldr	x13, [x13, _DPIO_POST_DIV_SHIFT@GOTPAGEOFF]
Lloh35:
	ldr	w13, [x13]
	lsl	w13, w27, w13
Lloh36:
	adrp	x14, _DPIO_K_SHIFT@GOTPAGE
Lloh37:
	ldr	x14, [x14, _DPIO_K_SHIFT@GOTPAGEOFF]
Lloh38:
	ldr	w14, [x14]
	lsl	w14, w27, w14
Lloh39:
	adrp	x15, _DPIO_ENABLE_CALIBRATION@GOTPAGE
Lloh40:
	ldr	x15, [x15, _DPIO_ENABLE_CALIBRATION@GOTPAGEOFF]
Lloh41:
	ldr	w15, [x15]
	orr	w9, w10, w9
	orr	w9, w9, w11
	orr	w9, w9, w12
	orr	w8, w9, w8
	orr	w8, w8, w13
	orr	w8, w8, w14
	orr	w25, w8, w15
	mov	x0, x20
	bl	_DPIO_DIV
	mov	x1, x0
	mov	x0, x19
	mov	x2, x25
	bl	_intel_dpio_write
	mov	x0, x20
	bl	_DPIO_CORE_CLK
	mov	x1, x0
	mov	x0, x19
	mov	w2, #16777216
	bl	_intel_dpio_write
Lloh42:
	adrp	x8, _DPIO_REFSEL_OVERRIDE@GOTPAGE
Lloh43:
	ldr	x8, [x8, _DPIO_REFSEL_OVERRIDE@GOTPAGEOFF]
Lloh44:
	ldr	w8, [x8]
	lsl	w8, w27, w8
Lloh45:
	adrp	x9, _DPIO_PLL_MODESEL_SHIFT@GOTPAGE
Lloh46:
	ldr	x9, [x9, _DPIO_PLL_MODESEL_SHIFT@GOTPAGEOFF]
Lloh47:
	ldr	w9, [x9]
	mov	w10, #5
Lloh48:
	adrp	x11, _DPIO_BIAS_CURRENT_CTL_SHIFT@GOTPAGE
Lloh49:
	ldr	x11, [x11, _DPIO_BIAS_CURRENT_CTL_SHIFT@GOTPAGEOFF]
	lsl	w9, w10, w9
Lloh50:
	ldr	w11, [x11]
	mov	w12, #3
	lsl	w11, w12, w11
Lloh51:
	adrp	x12, _DPIO_PLL_REFCLK_SEL_SHIFT@GOTPAGE
Lloh52:
	ldr	x12, [x12, _DPIO_PLL_REFCLK_SEL_SHIFT@GOTPAGEOFF]
Lloh53:
	ldr	w12, [x12]
	mov	w13, #7
	lsl	w12, w13, w12
Lloh54:
	adrp	x13, _DPIO_DRIVER_CTL_SHIFT@GOTPAGE
Lloh55:
	ldr	x13, [x13, _DPIO_DRIVER_CTL_SHIFT@GOTPAGEOFF]
Lloh56:
	ldr	w13, [x13]
	mov	w14, #8
	lsl	w13, w14, w13
Lloh57:
	adrp	x14, _DPIO_CLK_BIAS_CTL_SHIFT@GOTPAGE
Lloh58:
	ldr	x14, [x14, _DPIO_CLK_BIAS_CTL_SHIFT@GOTPAGEOFF]
Lloh59:
	ldr	w14, [x14]
	lsl	w10, w10, w14
	orr	w8, w8, w9
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w8, w8, w13
	orr	w8, w8, w10
	orr	w25, w8, #0x100000
	mov	x0, x20
	bl	_DPIO_REFSFR
	mov	x1, x0
	mov	x0, x19
	mov	x2, x25
	bl	_intel_dpio_write
	mov	x0, x20
	bl	_DPIO_LFP_COEFF
	mov	x1, x0
	mov	x0, x19
	mov	w2, #59
	movk	w2, #95, lsl #16
	bl	_intel_dpio_write
Lloh60:
	adrp	x8, _DPLL_VCO_ENABLE@GOTPAGE
Lloh61:
	ldr	x8, [x8, _DPLL_VCO_ENABLE@GOTPAGEOFF]
Lloh62:
	ldr	w8, [x8]
	orr	w24, w8, w24
	mov	x0, x20
	bl	_DPLL
	mov	x1, x24
	bl	_I915_WRITE
	mov	x0, x20
	bl	_DPLL
	bl	_POSTING_READ
	mov	x0, x20
	bl	_DPLL
	bl	_I915_READ
Lloh63:
	adrp	x8, _DPLL_LOCK_VLV@GOTPAGE
Lloh64:
	ldr	x8, [x8, _DPLL_LOCK_VLV@GOTPAGEOFF]
Lloh65:
	ldr	w8, [x8]
	bics	wzr, w8, w0
	cset	w0, eq
	mov	w1, #1
	bl	_wait_for
	cbz	x0, LBB0_4
; %bb.3:
Lloh66:
	adrp	x0, l_.str@PAGE
Lloh67:
	add	x0, x0, l_.str@PAGEOFF
	mov	x1, x20
	bl	_DRM_ERROR
LBB0_4:
Lloh68:
	adrp	x8, _DPIO_FASTCLK_DISABLE@GOTPAGE
Lloh69:
	ldr	x8, [x8, _DPIO_FASTCLK_DISABLE@GOTPAGEOFF]
Lloh70:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1568
	bl	_intel_dpio_write
Lloh71:
	adrp	x25, _INTEL_OUTPUT_DISPLAYPORT@GOTPAGE
Lloh72:
	ldr	x25, [x25, _INTEL_OUTPUT_DISPLAYPORT@GOTPAGEOFF]
	ldr	w1, [x25]
	mov	x0, x21
	bl	_intel_pipe_has_type
	cbz	x0, LBB0_6
; %bb.5:
	mov	x0, x21
	mov	x1, x23
	mov	x2, x22
	bl	_intel_dp_set_m_n
LBB0_6:
	mov	x0, x20
	bl	_DPLL
	mov	x1, x24
	bl	_I915_WRITE
	mov	x0, x20
	bl	_DPLL
	bl	_POSTING_READ
	mov	w0, #150
	bl	_udelay
	cbz	w26, LBB0_9
; %bb.7:
	mov	x0, x22
	bl	_intel_mode_get_pixel_multiplier
	cmp	w0, #2
	b.lt	LBB0_9
; %bb.8:
	sub	w8, w0, #1
Lloh73:
	adrp	x9, _DPLL_MD_UDI_MULTIPLIER_SHIFT@GOTPAGE
Lloh74:
	ldr	x9, [x9, _DPLL_MD_UDI_MULTIPLIER_SHIFT@GOTPAGEOFF]
Lloh75:
	ldr	w9, [x9]
	lsl	w22, w8, w9
	b	LBB0_10
LBB0_9:
	mov	w22, #0
LBB0_10:
	mov	w23, #196
	movk	w23, #16, lsl #16
	mov	x0, x20
	bl	_DPLL_MD
	mov	x1, x22
	bl	_I915_WRITE
	mov	x0, x20
	bl	_DPLL_MD
	bl	_POSTING_READ
	ldr	w1, [x25]
	mov	x0, x21
	bl	_intel_pipe_has_type
	cbnz	x0, LBB0_12
; %bb.11:
Lloh76:
	adrp	x8, _INTEL_OUTPUT_HDMI@GOTPAGE
Lloh77:
	ldr	x8, [x8, _INTEL_OUTPUT_HDMI@GOTPAGEOFF]
Lloh78:
	ldr	w1, [x8]
	mov	x0, x21
	bl	_intel_pipe_has_type
	cbz	x0, LBB0_13
LBB0_12:
	orr	w8, w23, #0x200000
	cmp	w20, #1
	csel	w2, w8, w23, eq
Lloh79:
	adrp	x8, _DPIO_DATA_CHANNEL1@GOTPAGE
Lloh80:
	ldr	x8, [x8, _DPIO_DATA_CHANNEL1@GOTPAGEOFF]
Lloh81:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_intel_dpio_write
LBB0_13:
Lloh82:
	adrp	x8, _INTEL_OUTPUT_EDP@GOTPAGE
Lloh83:
	ldr	x8, [x8, _INTEL_OUTPUT_EDP@GOTPAGEOFF]
Lloh84:
	ldr	w1, [x8]
	mov	x0, x21
	bl	_intel_pipe_has_type
	cbz	x0, LBB0_15
; %bb.14:
	orr	w8, w23, #0x200000
	cmp	w20, #1
	csel	w2, w8, w23, eq
Lloh85:
	adrp	x8, _DPIO_DATA_CHANNEL2@GOTPAGE
Lloh86:
	ldr	x8, [x8, _DPIO_DATA_CHANNEL2@GOTPAGEOFF]
Lloh87:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_intel_dpio_write
LBB0_15:
	mov	x0, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_mutex_unlock
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpAdd	Lloh66, Lloh67
	.loh AdrpLdrGot	Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.cfi_endproc
                                        ; -- End function
	.comm	_INTEL_OUTPUT_SDVO,4,2          ; @INTEL_OUTPUT_SDVO
	.comm	_INTEL_OUTPUT_HDMI,4,2          ; @INTEL_OUTPUT_HDMI
	.comm	_DPLL_VGA_MODE_DIS,4,2          ; @DPLL_VGA_MODE_DIS
	.comm	_DPLL_EXT_BUFFER_ENABLE_VLV,4,2 ; @DPLL_EXT_BUFFER_ENABLE_VLV
	.comm	_DPLL_REFA_CLK_ENABLE_VLV,4,2   ; @DPLL_REFA_CLK_ENABLE_VLV
	.comm	_DPLL_INTEGRATED_CLOCK_VLV,4,2  ; @DPLL_INTEGRATED_CLOCK_VLV
	.comm	_DPIO_M1DIV_SHIFT,4,2           ; @DPIO_M1DIV_SHIFT
	.comm	_DPIO_M2DIV_MASK,4,2            ; @DPIO_M2DIV_MASK
	.comm	_DPIO_P1_SHIFT,4,2              ; @DPIO_P1_SHIFT
	.comm	_DPIO_P2_SHIFT,4,2              ; @DPIO_P2_SHIFT
	.comm	_DPIO_N_SHIFT,4,2               ; @DPIO_N_SHIFT
	.comm	_DPIO_POST_DIV_SHIFT,4,2        ; @DPIO_POST_DIV_SHIFT
	.comm	_DPIO_K_SHIFT,4,2               ; @DPIO_K_SHIFT
	.comm	_DPIO_ENABLE_CALIBRATION,4,2    ; @DPIO_ENABLE_CALIBRATION
	.comm	_DPIO_REFSEL_OVERRIDE,4,2       ; @DPIO_REFSEL_OVERRIDE
	.comm	_DPIO_PLL_MODESEL_SHIFT,4,2     ; @DPIO_PLL_MODESEL_SHIFT
	.comm	_DPIO_BIAS_CURRENT_CTL_SHIFT,4,2 ; @DPIO_BIAS_CURRENT_CTL_SHIFT
	.comm	_DPIO_PLL_REFCLK_SEL_SHIFT,4,2  ; @DPIO_PLL_REFCLK_SEL_SHIFT
	.comm	_DPIO_DRIVER_CTL_SHIFT,4,2      ; @DPIO_DRIVER_CTL_SHIFT
	.comm	_DPIO_CLK_BIAS_CTL_SHIFT,4,2    ; @DPIO_CLK_BIAS_CTL_SHIFT
	.comm	_DPLL_VCO_ENABLE,4,2            ; @DPLL_VCO_ENABLE
	.comm	_DPLL_LOCK_VLV,4,2              ; @DPLL_LOCK_VLV
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"DPLL %d failed to lock\n"

	.comm	_DPIO_FASTCLK_DISABLE,4,2       ; @DPIO_FASTCLK_DISABLE
	.comm	_INTEL_OUTPUT_DISPLAYPORT,4,2   ; @INTEL_OUTPUT_DISPLAYPORT
	.comm	_DPLL_MD_UDI_MULTIPLIER_SHIFT,4,2 ; @DPLL_MD_UDI_MULTIPLIER_SHIFT
	.comm	_DPIO_DATA_CHANNEL1,4,2         ; @DPIO_DATA_CHANNEL1
	.comm	_INTEL_OUTPUT_EDP,4,2           ; @INTEL_OUTPUT_EDP
	.comm	_DPIO_DATA_CHANNEL2,4,2         ; @DPIO_DATA_CHANNEL2
	.no_dead_strip	_vlv_update_pll
.subsections_via_symbols
