	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_legacy_lvds_update
_radeon_legacy_lvds_update:             ## @radeon_legacy_lvds_update
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r12d
	movq	%rdi, %r14
	movq	(%rdi), %rax
	movq	(%rax), %r13
	callq	_to_radeon_encoder
	movq	%rax, %rbx
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	movq	_RADEON_LVDS_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r15d
	movq	_RADEON_LVDS_BL_MOD_LEVEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	%r15d, %eax
	sarl	%cl, %eax
	movzbl	%al, %edi
	movq	(%rbx), %rax
	testq	%rax, %rax
	je	LBB0_1
## %bb.2:
	movl	(%rax), %ebx
	cmpq	$0, 8(%rax)
	je	LBB0_4
## %bb.3:
	movl	4(%rax), %edi
	jmp	LBB0_4
LBB0_1:
	movl	$2000, %ebx                     ## imm = 0x7D0
LBB0_4:
	movq	%r13, -72(%rbp)                 ## 8-byte Spill
	movq	8(%r13), %rax
	movq	_CT_IBOOK@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	setne	%cl
	movq	_CT_POWERBOOK_EXTERNAL@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rax
	setne	%dl
	andb	%cl, %dl
	movq	_CT_POWERBOOK_INTERNAL@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	setne	%cl
	movq	_CT_POWERBOOK_VGA@GOTPCREL(%rip), %rsi
	cmpq	(%rsi), %rax
	setne	%r13b
	andb	%cl, %r13b
	andb	%dl, %r13b
	leal	-128(%r12), %eax
	cmpl	$2, %eax
	jb	LBB0_10
## %bb.5:
	cmpl	$131, %r12d
	je	LBB0_10
## %bb.6:
	cmpl	$130, %r12d
	jne	LBB0_14
## %bb.7:
	movl	%ebx, -44(%rbp)                 ## 4-byte Spill
	movq	_RADEON_DISP_PWR_MAN@GOTPCREL(%rip), %rbx
	movl	%edi, -56(%rbp)                 ## 4-byte Spill
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_RADEON_AUTO_PWRUP_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_RADEON_LVDS_PLL_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_RADEON_LVDS_PLL_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movl	$1, %edi
	callq	_mdelay
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_RADEON_LVDS_PLL_RESET@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32
	movl	-56(%rbp), %esi                 ## 4-byte Reload
	movq	_RADEON_LVDS_DISPLAY_DIS@GOTPCREL(%rip), %rax
	movq	_RADEON_LVDS_BL_MOD_LEVEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	notl	%ecx
	andl	%ecx, %r15d
	movq	_RADEON_LVDS_ON@GOTPCREL(%rip), %rax
	movq	_RADEON_LVDS_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	_RADEON_LVDS_BL_MOD_LEVEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %esi
	movq	_RADEON_LVDS_DIGON@GOTPCREL(%rip), %rdx
	movq	_RADEON_LVDS_BLON@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	testb	%r13b, %r13b
	jne	LBB0_9
## %bb.8:
	movq	_RADEON_LVDS_BL_MOD_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_9:
	orl	%r15d, %ebx
	orl	(%rdx), %ebx
	orl	(%rcx), %ebx
	orl	%esi, %ebx
	orl	%eax, %ebx
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	callq	_mdelay
	movq	_RADEON_LVDS_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	jmp	LBB0_14
LBB0_10:
	movq	%r12, -56(%rbp)                 ## 8-byte Spill
	movq	_RADEON_PIXCLKS_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_RREG32_PLL
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movl	(%r12), %edi
	movq	_RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	xorl	%esi, %esi
	callq	_WREG32_PLL_P
	movq	_RADEON_LVDS_DISPLAY_DIS@GOTPCREL(%rip), %rax
	orl	(%rax), %r15d
	testb	%r13b, %r13b
	movq	%r14, -64(%rbp)                 ## 8-byte Spill
	movl	%ebx, %r14d
	je	LBB0_11
## %bb.12:
	movq	_RADEON_LVDS_GEN_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movq	_RADEON_LVDS_ON@GOTPCREL(%rip), %rax
	movq	_RADEON_LVDS_BLON@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	_RADEON_LVDS_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_RADEON_LVDS_DIGON@GOTPCREL(%rip), %rax
	jmp	LBB0_13
LBB0_11:
	movq	_RADEON_LVDS_BL_MOD_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r15d
	movq	_RADEON_LVDS_GEN_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movq	_RADEON_LVDS_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_RADEON_LVDS_ON@GOTPCREL(%rip), %rax
LBB0_13:
	movq	-56(%rbp), %r12                 ## 8-byte Reload
	orl	(%rax), %ebx
	notl	%ebx
	andl	%r15d, %ebx
	movl	%r14d, %edi
	callq	_mdelay
	movl	(%r13), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_RADEON_PIXCLKS_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32_PLL
	movl	%r14d, %edi
	callq	_mdelay
	movq	-64(%rbp), %r14                 ## 8-byte Reload
LBB0_14:
	xorl	%esi, %esi
	cmpl	$130, %r12d
	sete	%sil
	movq	-72(%rbp), %rax                 ## 8-byte Reload
	cmpq	$0, (%rax)
	je	LBB0_16
## %bb.15:
	movq	%r14, %rdi
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_atombios_encoder_dpms_scratch_regs ## TAILCALL
LBB0_16:
	movq	%r14, %rdi
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_combios_encoder_dpms_scratch_regs ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"\n"

	.comm	_RADEON_LVDS_GEN_CNTL,4,2       ## @RADEON_LVDS_GEN_CNTL
	.comm	_RADEON_LVDS_BL_MOD_LEVEL_SHIFT,4,2 ## @RADEON_LVDS_BL_MOD_LEVEL_SHIFT
	.comm	_CT_IBOOK,8,3                   ## @CT_IBOOK
	.comm	_CT_POWERBOOK_EXTERNAL,8,3      ## @CT_POWERBOOK_EXTERNAL
	.comm	_CT_POWERBOOK_INTERNAL,8,3      ## @CT_POWERBOOK_INTERNAL
	.comm	_CT_POWERBOOK_VGA,8,3           ## @CT_POWERBOOK_VGA
	.comm	_RADEON_DISP_PWR_MAN,4,2        ## @RADEON_DISP_PWR_MAN
	.comm	_RADEON_AUTO_PWRUP_EN,4,2       ## @RADEON_AUTO_PWRUP_EN
	.comm	_RADEON_LVDS_PLL_CNTL,4,2       ## @RADEON_LVDS_PLL_CNTL
	.comm	_RADEON_LVDS_PLL_EN,4,2         ## @RADEON_LVDS_PLL_EN
	.comm	_RADEON_LVDS_PLL_RESET,4,2      ## @RADEON_LVDS_PLL_RESET
	.comm	_RADEON_LVDS_DISPLAY_DIS,4,2    ## @RADEON_LVDS_DISPLAY_DIS
	.comm	_RADEON_LVDS_BL_MOD_LEVEL_MASK,4,2 ## @RADEON_LVDS_BL_MOD_LEVEL_MASK
	.comm	_RADEON_LVDS_ON,4,2             ## @RADEON_LVDS_ON
	.comm	_RADEON_LVDS_EN,4,2             ## @RADEON_LVDS_EN
	.comm	_RADEON_LVDS_DIGON,4,2          ## @RADEON_LVDS_DIGON
	.comm	_RADEON_LVDS_BLON,4,2           ## @RADEON_LVDS_BLON
	.comm	_RADEON_LVDS_BL_MOD_EN,4,2      ## @RADEON_LVDS_BL_MOD_EN
	.comm	_RADEON_PIXCLKS_CNTL,4,2        ## @RADEON_PIXCLKS_CNTL
	.comm	_RADEON_PIXCLK_LVDS_ALWAYS_ONb,4,2 ## @RADEON_PIXCLK_LVDS_ALWAYS_ONb
	.no_dead_strip	_radeon_legacy_lvds_update
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_legacy_lvds_update
_radeon_legacy_lvds_update:             ; @radeon_legacy_lvds_update
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x20, x1
	mov	x19, x0
	ldr	x8, [x0]
	ldr	x24, [x8]
	bl	_to_radeon_encoder
	mov	x21, x0
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_KMS
Lloh2:
	adrp	x25, _RADEON_LVDS_GEN_CNTL@GOTPAGE
Lloh3:
	ldr	x25, [x25, _RADEON_LVDS_GEN_CNTL@GOTPAGEOFF]
	ldr	w0, [x25]
	bl	_RREG32
	mov	x22, x0
Lloh4:
	adrp	x23, _RADEON_LVDS_BL_MOD_LEVEL_SHIFT@GOTPAGE
Lloh5:
	ldr	x23, [x23, _RADEON_LVDS_BL_MOD_LEVEL_SHIFT@GOTPAGEOFF]
	ldr	w8, [x23]
	asr	w8, w0, w8
	and	w26, w8, #0xff
	ldr	x8, [x21]
	cbz	x8, LBB0_3
; %bb.1:
	ldr	w21, [x8]
	ldr	x9, [x8, #8]
	cbz	x9, LBB0_4
; %bb.2:
	ldr	w26, [x8, #4]
	b	LBB0_4
LBB0_3:
	mov	w21, #2000
LBB0_4:
Lloh6:
	adrp	x8, _CT_IBOOK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _CT_IBOOK@GOTPAGEOFF]
	ldr	x9, [x24, #8]
Lloh8:
	ldr	x8, [x8]
	cmp	x9, x8
Lloh9:
	adrp	x8, _CT_POWERBOOK_EXTERNAL@GOTPAGE
Lloh10:
	ldr	x8, [x8, _CT_POWERBOOK_EXTERNAL@GOTPAGEOFF]
Lloh11:
	ldr	x8, [x8]
	ccmp	x9, x8, #4, ne
Lloh12:
	adrp	x8, _CT_POWERBOOK_INTERNAL@GOTPAGE
Lloh13:
	ldr	x8, [x8, _CT_POWERBOOK_INTERNAL@GOTPAGEOFF]
Lloh14:
	ldr	x8, [x8]
Lloh15:
	adrp	x10, _CT_POWERBOOK_VGA@GOTPAGE
Lloh16:
	ldr	x10, [x10, _CT_POWERBOOK_VGA@GOTPAGEOFF]
	ccmp	x9, x8, #4, ne
Lloh17:
	ldr	x8, [x10]
	ccmp	x9, x8, #4, ne
	cset	w27, ne
	sub	w8, w20, #128
	cmp	w8, #2
	b.lo	LBB0_8
; %bb.5:
	cmp	w20, #131
	b.eq	LBB0_8
; %bb.6:
	cmp	w20, #130
	b.ne	LBB0_12
; %bb.7:
Lloh18:
	adrp	x28, _RADEON_DISP_PWR_MAN@GOTPAGE
Lloh19:
	ldr	x28, [x28, _RADEON_DISP_PWR_MAN@GOTPAGEOFF]
	ldr	w0, [x28]
	bl	_RREG32
Lloh20:
	adrp	x8, _RADEON_AUTO_PWRUP_EN@GOTPAGE
Lloh21:
	ldr	x8, [x8, _RADEON_AUTO_PWRUP_EN@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x28]
	bl	_WREG32
Lloh23:
	adrp	x28, _RADEON_LVDS_PLL_CNTL@GOTPAGE
Lloh24:
	ldr	x28, [x28, _RADEON_LVDS_PLL_CNTL@GOTPAGEOFF]
	ldr	w0, [x28]
	bl	_RREG32
Lloh25:
	adrp	x8, _RADEON_LVDS_PLL_EN@GOTPAGE
Lloh26:
	ldr	x8, [x8, _RADEON_LVDS_PLL_EN@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x28]
	bl	_WREG32
	mov	w0, #1
	bl	_mdelay
	ldr	w0, [x28]
	bl	_RREG32
Lloh28:
	adrp	x8, _RADEON_LVDS_PLL_RESET@GOTPAGE
Lloh29:
	ldr	x8, [x8, _RADEON_LVDS_PLL_RESET@GOTPAGEOFF]
Lloh30:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w0, [x28]
	bl	_WREG32
Lloh31:
	adrp	x8, _RADEON_LVDS_DISPLAY_DIS@GOTPAGE
Lloh32:
	ldr	x8, [x8, _RADEON_LVDS_DISPLAY_DIS@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
Lloh34:
	adrp	x9, _RADEON_LVDS_BL_MOD_LEVEL_MASK@GOTPAGE
Lloh35:
	ldr	x9, [x9, _RADEON_LVDS_BL_MOD_LEVEL_MASK@GOTPAGEOFF]
Lloh36:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh37:
	adrp	x9, _RADEON_LVDS_ON@GOTPAGE
Lloh38:
	ldr	x9, [x9, _RADEON_LVDS_ON@GOTPAGEOFF]
	bic	w8, w22, w8
Lloh39:
	ldr	w9, [x9]
Lloh40:
	adrp	x10, _RADEON_LVDS_EN@GOTPAGE
Lloh41:
	ldr	x10, [x10, _RADEON_LVDS_EN@GOTPAGEOFF]
Lloh42:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh43:
	adrp	x10, _RADEON_LVDS_DIGON@GOTPAGE
Lloh44:
	ldr	x10, [x10, _RADEON_LVDS_DIGON@GOTPAGEOFF]
Lloh45:
	ldr	w10, [x10]
Lloh46:
	adrp	x11, _RADEON_LVDS_BLON@GOTPAGE
Lloh47:
	ldr	x11, [x11, _RADEON_LVDS_BLON@GOTPAGEOFF]
Lloh48:
	ldr	w11, [x11]
	ldr	w12, [x23]
	lsl	w12, w26, w12
Lloh49:
	adrp	x13, _RADEON_LVDS_BL_MOD_EN@GOTPAGE
Lloh50:
	ldr	x13, [x13, _RADEON_LVDS_BL_MOD_EN@GOTPAGEOFF]
Lloh51:
	ldr	w13, [x13]
	cmp	w27, #0
	csel	w13, wzr, w13, ne
	orr	w8, w9, w8
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w22, w8, w13
	mov	x0, x21
	bl	_mdelay
	ldr	w0, [x25]
	mov	x1, x22
	bl	_WREG32
	b	LBB0_12
LBB0_8:
Lloh52:
	adrp	x26, _RADEON_PIXCLKS_CNTL@GOTPAGE
Lloh53:
	ldr	x26, [x26, _RADEON_PIXCLKS_CNTL@GOTPAGEOFF]
	ldr	w0, [x26]
	bl	_RREG32_PLL
	mov	x23, x0
	ldr	w0, [x26]
Lloh54:
	adrp	x8, _RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPAGE
Lloh55:
	ldr	x8, [x8, _RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPAGEOFF]
Lloh56:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_PLL_P
Lloh57:
	adrp	x8, _RADEON_LVDS_DISPLAY_DIS@GOTPAGE
Lloh58:
	ldr	x8, [x8, _RADEON_LVDS_DISPLAY_DIS@GOTPAGEOFF]
Lloh59:
	ldr	w8, [x8]
	orr	w22, w8, w22
	tbz	w27, #0, LBB0_10
; %bb.9:
	ldr	w0, [x25]
	mov	x1, x22
	bl	_WREG32
Lloh60:
	adrp	x8, _RADEON_LVDS_ON@GOTPAGE
Lloh61:
	ldr	x8, [x8, _RADEON_LVDS_ON@GOTPAGEOFF]
Lloh62:
	ldr	w8, [x8]
Lloh63:
	adrp	x9, _RADEON_LVDS_BLON@GOTPAGE
Lloh64:
	ldr	x9, [x9, _RADEON_LVDS_BLON@GOTPAGEOFF]
Lloh65:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh66:
	adrp	x9, _RADEON_LVDS_EN@GOTPAGE
Lloh67:
	ldr	x9, [x9, _RADEON_LVDS_EN@GOTPAGEOFF]
Lloh68:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh69:
	adrp	x9, _RADEON_LVDS_DIGON@GOTPAGE
Lloh70:
	ldr	x9, [x9, _RADEON_LVDS_DIGON@GOTPAGEOFF]
	b	LBB0_11
LBB0_10:
Lloh71:
	adrp	x8, _RADEON_LVDS_BL_MOD_EN@GOTPAGE
Lloh72:
	ldr	x8, [x8, _RADEON_LVDS_BL_MOD_EN@GOTPAGEOFF]
Lloh73:
	ldr	w8, [x8]
	bic	w22, w22, w8
	ldr	w0, [x25]
	mov	x1, x22
	bl	_WREG32
Lloh74:
	adrp	x8, _RADEON_LVDS_EN@GOTPAGE
Lloh75:
	ldr	x8, [x8, _RADEON_LVDS_EN@GOTPAGEOFF]
Lloh76:
	ldr	w8, [x8]
Lloh77:
	adrp	x9, _RADEON_LVDS_ON@GOTPAGE
Lloh78:
	ldr	x9, [x9, _RADEON_LVDS_ON@GOTPAGEOFF]
LBB0_11:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w22, w22, w8
	mov	x0, x21
	bl	_mdelay
	ldr	w0, [x25]
	mov	x1, x22
	bl	_WREG32
	ldr	w0, [x26]
	mov	x1, x23
	bl	_WREG32_PLL
	mov	x0, x21
	bl	_mdelay
LBB0_12:
	ldr	x8, [x24]
	cmp	w20, #130
	cset	w1, eq
	mov	x0, x19
	cbz	x8, LBB0_14
; %bb.13:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_radeon_atombios_encoder_dpms_scratch_regs
LBB0_14:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_radeon_combios_encoder_dpms_scratch_regs
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGot	Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"\n"

	.comm	_RADEON_LVDS_GEN_CNTL,4,2       ; @RADEON_LVDS_GEN_CNTL
	.comm	_RADEON_LVDS_BL_MOD_LEVEL_SHIFT,4,2 ; @RADEON_LVDS_BL_MOD_LEVEL_SHIFT
	.comm	_CT_IBOOK,8,3                   ; @CT_IBOOK
	.comm	_CT_POWERBOOK_EXTERNAL,8,3      ; @CT_POWERBOOK_EXTERNAL
	.comm	_CT_POWERBOOK_INTERNAL,8,3      ; @CT_POWERBOOK_INTERNAL
	.comm	_CT_POWERBOOK_VGA,8,3           ; @CT_POWERBOOK_VGA
	.comm	_RADEON_DISP_PWR_MAN,4,2        ; @RADEON_DISP_PWR_MAN
	.comm	_RADEON_AUTO_PWRUP_EN,4,2       ; @RADEON_AUTO_PWRUP_EN
	.comm	_RADEON_LVDS_PLL_CNTL,4,2       ; @RADEON_LVDS_PLL_CNTL
	.comm	_RADEON_LVDS_PLL_EN,4,2         ; @RADEON_LVDS_PLL_EN
	.comm	_RADEON_LVDS_PLL_RESET,4,2      ; @RADEON_LVDS_PLL_RESET
	.comm	_RADEON_LVDS_DISPLAY_DIS,4,2    ; @RADEON_LVDS_DISPLAY_DIS
	.comm	_RADEON_LVDS_BL_MOD_LEVEL_MASK,4,2 ; @RADEON_LVDS_BL_MOD_LEVEL_MASK
	.comm	_RADEON_LVDS_ON,4,2             ; @RADEON_LVDS_ON
	.comm	_RADEON_LVDS_EN,4,2             ; @RADEON_LVDS_EN
	.comm	_RADEON_LVDS_DIGON,4,2          ; @RADEON_LVDS_DIGON
	.comm	_RADEON_LVDS_BLON,4,2           ; @RADEON_LVDS_BLON
	.comm	_RADEON_LVDS_BL_MOD_EN,4,2      ; @RADEON_LVDS_BL_MOD_EN
	.comm	_RADEON_PIXCLKS_CNTL,4,2        ; @RADEON_PIXCLKS_CNTL
	.comm	_RADEON_PIXCLK_LVDS_ALWAYS_ONb,4,2 ; @RADEON_PIXCLK_LVDS_ALWAYS_ONb
	.no_dead_strip	_radeon_legacy_lvds_update
.subsections_via_symbols
