	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_legacy_rmx_mode_set
_radeon_legacy_rmx_mode_set:            ## @radeon_legacy_rmx_mode_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$104, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	(%rdi), %rax
	movq	(%rax), %r13
	callq	_to_radeon_crtc
	movq	%rax, %rbx
	movl	(%r14), %r15d
	movl	4(%r14), %eax
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_RADEON_FP_VERT_STRETCH@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r12d
	movq	_RADEON_VERT_STRETCH_RESERVED@GOTPCREL(%rip), %rax
	movq	_RADEON_VERT_AUTO_RATIO_INC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movl	%ecx, -88(%rbp)                 ## 4-byte Spill
	movq	_RADEON_FP_HORZ_STRETCH@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -104(%rbp)                ## 4-byte Spill
	movq	(%r13), %rcx
	movq	_CHIP_RS200@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	movq	_CHIP_RS100@GOTPCREL(%rip), %rdx
	movq	_RADEON_CRTC_H_CUTOFF_ACTIVE_EN@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	movl	$0, %edi
	cmovel	%esi, %edi
	cmpq	(%rdx), %rcx
	movq	_RADEON_HORZ_FP_LOOP_STRETCH@GOTPCREL(%rip), %rdx
	cmovel	%esi, %edi
	movl	%edi, -84(%rbp)                 ## 4-byte Spill
	movl	8(%r14), %ecx
	leal	7(%rcx), %r13d
	testl	%ecx, %ecx
	cmovnsl	%ecx, %r13d
	movq	_RADEON_HORZ_AUTO_RATIO_INC@GOTPCREL(%rip), %rsi
	sarl	$3, %r13d
	movl	20(%r14), %eax
	movq	%rax, -96(%rbp)                 ## 8-byte Spill
	movq	_DRM_MODE_FLAG_NHSYNC@GOTPCREL(%rip), %r9
	movq	_RADEON_CRTC_H_SYNC_POL@GOTPCREL(%rip), %rdi
	movl	$65535, %r8d                    ## imm = 0xFFFF
	movl	40(%r14), %eax
	movq	%rbx, -56(%rbp)                 ## 8-byte Spill
	movl	4(%rbx), %r10d
	testl	%r10d, %r10d
	movq	%rax, -128(%rbp)                ## 8-byte Spill
	je	LBB0_1
## %bb.2:
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	movl	8(%rcx), %ecx
	testl	%ecx, %ecx
	je	LBB0_1
## %bb.3:
	cmpl	%r10d, %r15d
	movl	%r10d, %ebx
	cmovll	%r15d, %ebx
	movq	%rdi, %rax
	movl	-48(%rbp), %edi                 ## 4-byte Reload
	cmpl	%ecx, %edi
	movq	%r9, %rdx
	movl	%ecx, %r9d
	cmovll	%edi, %r9d
	xorl	%r11d, %r11d
	cmpl	%r15d, %r10d
	setg	%r11b
	cmpl	%edi, %ecx
	movq	%rax, %rdi
	setle	-41(%rbp)                       ## 1-byte Folded Spill
	movl	%r9d, -48(%rbp)                 ## 4-byte Spill
	movq	%rdx, %r9
	movq	_RADEON_HORZ_FP_LOOP_STRETCH@GOTPCREL(%rip), %rdx
	movq	-128(%rbp), %rax                ## 8-byte Reload
	movl	%ebx, %r15d
	jmp	LBB0_4
LBB0_1:
	xorl	%r11d, %r11d
	movb	$1, -41(%rbp)                   ## 1-byte Folded Spill
LBB0_4:
	andl	%r12d, -88(%rbp)                ## 4-byte Folded Spill
	movl	(%rdx), %ecx
	movl	%ecx, -64(%rbp)                 ## 4-byte Spill
	movl	(%rsi), %esi
	movl	12(%r14), %ecx
	movq	%rcx, -112(%rbp)                ## 8-byte Spill
	addl	$1023, %r13d                    ## imm = 0x3FF
	movl	16(%r14), %r12d
	movq	-96(%rbp), %rcx                 ## 8-byte Reload
	addl	$8184, %ecx                     ## imm = 0x1FF8
	movl	%ecx, -100(%rbp)                ## 4-byte Spill
	movl	24(%r14), %ecx
	movl	%ecx, -72(%rbp)                 ## 4-byte Spill
	movl	(%r9), %ecx
	movl	%ecx, -76(%rbp)                 ## 4-byte Spill
	addl	28(%r14), %r8d
	movl	(%rdi), %edi
	movl	32(%r14), %ecx
	movl	36(%r14), %edx
	movl	%edx, -60(%rbp)                 ## 4-byte Spill
	leal	4095(%rax), %r9d
	movq	_DRM_MODE_FLAG_NVSYNC@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	movq	_RADEON_CRTC_V_SYNC_POL@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movl	%edx, -68(%rbp)                 ## 4-byte Spill
	movq	-56(%rbp), %rdx                 ## 8-byte Reload
	movl	(%rdx), %edx
	cmpl	$131, %edx
	movl	%edi, -120(%rbp)                ## 4-byte Spill
	movq	%rcx, -136(%rbp)                ## 8-byte Spill
	movl	%ebx, -116(%rbp)                ## 4-byte Spill
	je	LBB0_7
## %bb.5:
	cmpl	$130, %edx
	je	LBB0_13
## %bb.6:
	cmpl	$129, %edx
	jne	LBB0_14
LBB0_7:
	movl	%r9d, %r14d
	testl	%r11d, %r11d
	je	LBB0_8
## %bb.9:
	movl	%esi, %eax
	andl	-104(%rbp), %eax                ## 4-byte Folded Reload
	cmpl	$1, %eax
	sbbl	$-1, %r15d
	movq	_RADEON_HORZ_STRETCH_RATIO_MAX@GOTPCREL(%rip), %rax
	imull	(%rax), %r15d
	movl	%r15d, %eax
	cltd
	idivl	%r10d
	incl	%eax
	movq	_RADEON_HORZ_STRETCH_RATIO_MASK@GOTPCREL(%rip), %rdx
	andl	(%rdx), %eax
	movq	_RADEON_HORZ_STRETCH_BLEND@GOTPCREL(%rip), %rdx
	leal	7(%r10), %r9d
	testl	%r10d, %r10d
	cmovnsl	%r10d, %r9d
	andl	$-8, %r9d
	shll	$13, %r9d
	addl	$-65536, %r9d                   ## imm = 0xFFFF0000
	orl	(%rdx), %r9d
	movq	_RADEON_HORZ_STRETCH_ENABLE@GOTPCREL(%rip), %rdx
	orl	%eax, %r9d
	orl	(%rdx), %r9d
	jmp	LBB0_10
LBB0_13:
	movq	%rax, %rbx
	leal	7(%r15), %r9d
	testl	%r15d, %r15d
	cmovnsl	%r15d, %r9d
	andl	$-8, %r9d
	shll	$13, %r9d
	addl	$-65536, %r9d                   ## imm = 0xFFFF0000
	movl	-48(%rbp), %eax                 ## 4-byte Reload
	shll	$12, %eax
	addl	$-4096, %eax                    ## imm = 0xF000
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_RADEON_CRTC_AUTO_HORZ_CENTER_EN@GOTPCREL(%rip), %rax
	movl	-84(%rbp), %edx                 ## 4-byte Reload
	orl	(%rax), %edx
	movq	_RADEON_CRTC_AUTO_VERT_CENTER_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	%edx, -84(%rbp)                 ## 4-byte Spill
	movl	44(%r14), %eax
	movl	48(%r14), %edx
	subl	%edx, %eax
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	cmpl	$110, %edi
	movl	$110, %r13d
	cmovll	%edi, %r13d
	movq	-96(%rbp), %rax                 ## 8-byte Reload
                                        ## kill: def $eax killed $eax killed $rax def $rax
	subl	%edx, %eax
	leal	7(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$3, %ecx
	movl	%ecx, -100(%rbp)                ## 4-byte Spill
	movl	52(%r14), %edx
	movl	56(%r14), %eax
	subl	%eax, %edx
	movl	%edx, -80(%rbp)                 ## 4-byte Spill
	movl	%ebx, %r14d
	subl	%eax, %r14d
	movl	$4095, %eax                     ## imm = 0xFFF
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	andl	8(%rcx), %eax
	leal	7(%r10), %ecx
	testl	%r10d, %r10d
	cmovnsl	%r10d, %ecx
	shll	$13, %ecx
	andl	$33488896, %ecx                 ## imm = 0x1FF0000
	orl	%eax, %ecx
	movl	%ecx, -56(%rbp)                 ## 4-byte Spill
	jmp	LBB0_16
LBB0_14:
	movl	%r9d, %r14d
	movl	%r8d, -80(%rbp)                 ## 4-byte Spill
	leal	7(%r15), %r9d
	testl	%r15d, %r15d
	cmovnsl	%r15d, %r9d
	andl	$-8, %r9d
	shll	$13, %r9d
	addl	$-65536, %r9d                   ## imm = 0xFFFF0000
	movl	-48(%rbp), %eax                 ## 4-byte Reload
	shll	$12, %eax
	addl	$-4096, %eax                    ## imm = 0xF000
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	jmp	LBB0_15
LBB0_8:
	leal	7(%r15), %r9d
	testl	%r15d, %r15d
	cmovnsl	%r15d, %r9d
	andl	$-8, %r9d
	shll	$13, %r9d
	addl	$-65536, %r9d                   ## imm = 0xFFFF0000
LBB0_10:
	movb	-41(%rbp), %al                  ## 1-byte Reload
	testb	%al, %al
	movl	-48(%rbp), %ecx                 ## 4-byte Reload
	movl	%r8d, -80(%rbp)                 ## 4-byte Spill
	je	LBB0_12
## %bb.11:
	shll	$12, %ecx
	addl	$-4096, %ecx                    ## imm = 0xF000
	movl	%ecx, -48(%rbp)                 ## 4-byte Spill
LBB0_15:
	movl	$0, -56(%rbp)                   ## 4-byte Folded Spill
	jmp	LBB0_16
LBB0_12:
	movq	_RADEON_VERT_AUTO_RATIO_INC@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	-88(%rbp), %eax                 ## 4-byte Folded Reload
	cmpl	$1, %eax
	sbbl	$-1, %ecx
	movq	_RADEON_VERT_STRETCH_RATIO_MAX@GOTPCREL(%rip), %rax
	imull	(%rax), %ecx
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	8(%rax), %edi
	movl	%ecx, %eax
	cltd
	idivl	%edi
	incl	%eax
	movq	_RADEON_VERT_STRETCH_RATIO_MASK@GOTPCREL(%rip), %rdx
	andl	(%rdx), %eax
	movq	_RADEON_VERT_STRETCH_ENABLE@GOTPCREL(%rip), %rdx
	movq	_RADEON_VERT_STRETCH_BLEND@GOTPCREL(%rip), %r10
	shll	$12, %edi
	addl	$-4096, %edi                    ## imm = 0xF000
	orl	(%rdx), %edi
	orl	%eax, %edi
	orl	(%r10), %edi
	movl	$0, -56(%rbp)                   ## 4-byte Folded Spill
	movl	%edi, -48(%rbp)                 ## 4-byte Spill
LBB0_16:
	movl	-76(%rbp), %r11d                ## 4-byte Reload
	movl	-72(%rbp), %r15d                ## 4-byte Reload
	movq	-112(%rbp), %rbx                ## 8-byte Reload
	movl	-68(%rbp), %edi                 ## 4-byte Reload
	movl	-64(%rbp), %r8d                 ## 4-byte Reload
	movl	-60(%rbp), %ecx                 ## 4-byte Reload
	movl	%ecx, %edx
	movq	-128(%rbp), %rax                ## 8-byte Reload
	subl	%eax, %edx
	andl	$31, %edx
	shll	$16, %edx
	cmpl	%eax, %ecx
	movl	$65536, %eax                    ## imm = 0x10000
	cmovel	%eax, %edx
	orl	%r8d, %esi
	andl	-104(%rbp), %esi                ## 4-byte Folded Reload
	movq	-136(%rbp), %r8                 ## 8-byte Reload
	shll	$16, %r8d
	movl	-116(%rbp), %r10d               ## 4-byte Reload
	andl	%r15d, %r10d
	cmovel	%r10d, %edi
	andl	$4095, %r14d                    ## imm = 0xFFF
	orl	%edx, %r14d
	orl	%edi, %r14d
	leal	7(%rbx), %edx
	testl	%ebx, %ebx
	cmovnsl	%ebx, %edx
	shll	$13, %edx
	andl	$33488896, %edx                 ## imm = 0x1FF0000
	addl	$33488896, %edx                 ## imm = 0x1FF0000
	andl	$33488896, %edx                 ## imm = 0x1FF0000
	andl	$1023, %r13d                    ## imm = 0x3FF
	orl	%edx, %r13d
	andl	%r15d, %r11d
	movl	-120(%rbp), %ebx                ## 4-byte Reload
	cmovel	%r11d, %ebx
	movzwl	-80(%rbp), %edx                 ## 2-byte Folded Reload
	subl	-96(%rbp), %r12d                ## 4-byte Folded Reload
	leal	7(%r12), %edi
	testl	%r12d, %r12d
	cmovsl	%edi, %r12d
	leal	(%r8,%rdx), %ecx
	addl	$-65536, %ecx                   ## imm = 0xFFFF0000
	movl	%ecx, -96(%rbp)                 ## 4-byte Spill
	shll	$13, %r12d
	andl	$4128768, %r12d                 ## imm = 0x3F0000
	cmpl	$15, %edi
	cmovbl	%eax, %r12d
	movl	-100(%rbp), %r15d               ## 4-byte Reload
	andl	$8191, %r15d                    ## imm = 0x1FFF
	orl	%r12d, %r15d
	orl	%ebx, %r15d
	orl	%r9d, %esi
	movl	-48(%rbp), %ebx                 ## 4-byte Reload
	orl	-88(%rbp), %ebx                 ## 4-byte Folded Reload
	movq	_RADEON_FP_HORZ_STRETCH@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32
	movq	_RADEON_FP_VERT_STRETCH@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_RADEON_CRTC_MORE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-84(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_FP_HORZ_VERT_ACTIVE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-56(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_FP_H_SYNC_STRT_WID@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movq	_RADEON_FP_V_SYNC_STRT_WID@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_RADEON_FP_CRTC_H_TOTAL_DISP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r13d, %esi
	callq	_WREG32
	movq	_RADEON_FP_CRTC_V_TOTAL_DISP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-96(%rbp), %esi                 ## 4-byte Reload
	addq	$104, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_FP_VERT_STRETCH,4,2     ## @RADEON_FP_VERT_STRETCH
	.comm	_RADEON_VERT_STRETCH_RESERVED,4,2 ## @RADEON_VERT_STRETCH_RESERVED
	.comm	_RADEON_VERT_AUTO_RATIO_INC,4,2 ## @RADEON_VERT_AUTO_RATIO_INC
	.comm	_RADEON_FP_HORZ_STRETCH,4,2     ## @RADEON_FP_HORZ_STRETCH
	.comm	_RADEON_HORZ_FP_LOOP_STRETCH,4,2 ## @RADEON_HORZ_FP_LOOP_STRETCH
	.comm	_RADEON_HORZ_AUTO_RATIO_INC,4,2 ## @RADEON_HORZ_AUTO_RATIO_INC
	.comm	_CHIP_RS100,8,3                 ## @CHIP_RS100
	.comm	_CHIP_RS200,8,3                 ## @CHIP_RS200
	.comm	_RADEON_CRTC_H_CUTOFF_ACTIVE_EN,4,2 ## @RADEON_CRTC_H_CUTOFF_ACTIVE_EN
	.comm	_DRM_MODE_FLAG_NHSYNC,4,2       ## @DRM_MODE_FLAG_NHSYNC
	.comm	_RADEON_CRTC_H_SYNC_POL,4,2     ## @RADEON_CRTC_H_SYNC_POL
	.comm	_DRM_MODE_FLAG_NVSYNC,4,2       ## @DRM_MODE_FLAG_NVSYNC
	.comm	_RADEON_CRTC_V_SYNC_POL,4,2     ## @RADEON_CRTC_V_SYNC_POL
	.comm	_RADEON_HORZ_STRETCH_RATIO_MAX,4,2 ## @RADEON_HORZ_STRETCH_RATIO_MAX
	.comm	_RADEON_HORZ_STRETCH_RATIO_MASK,4,2 ## @RADEON_HORZ_STRETCH_RATIO_MASK
	.comm	_RADEON_HORZ_STRETCH_BLEND,4,2  ## @RADEON_HORZ_STRETCH_BLEND
	.comm	_RADEON_HORZ_STRETCH_ENABLE,4,2 ## @RADEON_HORZ_STRETCH_ENABLE
	.comm	_RADEON_VERT_STRETCH_RATIO_MAX,4,2 ## @RADEON_VERT_STRETCH_RATIO_MAX
	.comm	_RADEON_VERT_STRETCH_RATIO_MASK,4,2 ## @RADEON_VERT_STRETCH_RATIO_MASK
	.comm	_RADEON_VERT_STRETCH_ENABLE,4,2 ## @RADEON_VERT_STRETCH_ENABLE
	.comm	_RADEON_VERT_STRETCH_BLEND,4,2  ## @RADEON_VERT_STRETCH_BLEND
	.comm	_RADEON_CRTC_AUTO_HORZ_CENTER_EN,4,2 ## @RADEON_CRTC_AUTO_HORZ_CENTER_EN
	.comm	_RADEON_CRTC_AUTO_VERT_CENTER_EN,4,2 ## @RADEON_CRTC_AUTO_VERT_CENTER_EN
	.comm	_RADEON_CRTC_MORE_CNTL,4,2      ## @RADEON_CRTC_MORE_CNTL
	.comm	_RADEON_FP_HORZ_VERT_ACTIVE,4,2 ## @RADEON_FP_HORZ_VERT_ACTIVE
	.comm	_RADEON_FP_H_SYNC_STRT_WID,4,2  ## @RADEON_FP_H_SYNC_STRT_WID
	.comm	_RADEON_FP_V_SYNC_STRT_WID,4,2  ## @RADEON_FP_V_SYNC_STRT_WID
	.comm	_RADEON_FP_CRTC_H_TOTAL_DISP,4,2 ## @RADEON_FP_CRTC_H_TOTAL_DISP
	.comm	_RADEON_FP_CRTC_V_TOTAL_DISP,4,2 ## @RADEON_FP_CRTC_V_TOTAL_DISP
	.no_dead_strip	_radeon_legacy_rmx_mode_set
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_legacy_rmx_mode_set
_radeon_legacy_rmx_mode_set:            ; @radeon_legacy_rmx_mode_set
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x1
	ldr	x8, [x0]
	ldr	x19, [x8]
	bl	_to_radeon_crtc
	mov	x20, x0
	ldp	w25, w23, [x21]
Lloh0:
	adrp	x8, _RADEON_FP_VERT_STRETCH@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_FP_VERT_STRETCH@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x22, x0
Lloh3:
	adrp	x8, _RADEON_VERT_STRETCH_RESERVED@GOTPAGE
Lloh4:
	ldr	x8, [x8, _RADEON_VERT_STRETCH_RESERVED@GOTPAGEOFF]
Lloh5:
	adrp	x9, _RADEON_VERT_AUTO_RATIO_INC@GOTPAGE
Lloh6:
	ldr	x9, [x9, _RADEON_VERT_AUTO_RATIO_INC@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
Lloh8:
	ldr	w9, [x9]
	orr	w26, w9, w8
Lloh9:
	adrp	x8, _RADEON_FP_HORZ_STRETCH@GOTPAGE
Lloh10:
	ldr	x8, [x8, _RADEON_FP_HORZ_STRETCH@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	bl	_RREG32
Lloh12:
	adrp	x13, _RADEON_HORZ_FP_LOOP_STRETCH@GOTPAGE
Lloh13:
	ldr	x13, [x13, _RADEON_HORZ_FP_LOOP_STRETCH@GOTPAGEOFF]
Lloh14:
	adrp	x14, _RADEON_HORZ_AUTO_RATIO_INC@GOTPAGE
Lloh15:
	ldr	x14, [x14, _RADEON_HORZ_AUTO_RATIO_INC@GOTPAGEOFF]
	ldr	x8, [x19]
Lloh16:
	adrp	x9, _CHIP_RS100@GOTPAGE
Lloh17:
	ldr	x9, [x9, _CHIP_RS100@GOTPAGEOFF]
Lloh18:
	ldr	x9, [x9]
Lloh19:
	adrp	x10, _CHIP_RS200@GOTPAGE
Lloh20:
	ldr	x10, [x10, _CHIP_RS200@GOTPAGEOFF]
Lloh21:
	ldr	x10, [x10]
	cmp	x8, x10
	ccmp	x8, x9, #4, ne
Lloh22:
	adrp	x8, _RADEON_CRTC_H_CUTOFF_ACTIVE_EN@GOTPAGE
Lloh23:
	ldr	x8, [x8, _RADEON_CRTC_H_CUTOFF_ACTIVE_EN@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	csel	w19, w8, wzr, eq
	ldr	w8, [x21, #8]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w8, w8, #3
	add	w11, w8, #1023
	ldr	w8, [x21, #20]
	mov	w9, #8184
	add	w10, w8, w9
Lloh25:
	adrp	x15, _DRM_MODE_FLAG_NHSYNC@GOTPAGE
Lloh26:
	ldr	x15, [x15, _DRM_MODE_FLAG_NHSYNC@GOTPAGEOFF]
Lloh27:
	adrp	x16, _RADEON_CRTC_H_SYNC_POL@GOTPAGE
Lloh28:
	ldr	x16, [x16, _RADEON_CRTC_H_SYNC_POL@GOTPAGEOFF]
	ldr	w9, [x21, #28]
	mov	w12, #65535
	add	w2, w9, w12
	ldr	w9, [x21, #40]
	add	w17, w9, #4095
Lloh29:
	adrp	x7, _DRM_MODE_FLAG_NVSYNC@GOTPAGE
Lloh30:
	ldr	x7, [x7, _DRM_MODE_FLAG_NVSYNC@GOTPAGEOFF]
Lloh31:
	adrp	x27, _RADEON_CRTC_V_SYNC_POL@GOTPAGE
Lloh32:
	ldr	x27, [x27, _RADEON_CRTC_V_SYNC_POL@GOTPAGEOFF]
	ldr	w30, [x20, #4]
	cbz	w30, LBB0_2
; %bb.1:
	ldr	w12, [x20, #8]
	mov	w1, #1
	cmp	w25, w30
	csel	w3, w25, w30, lt
	cmp	w23, w12
	csel	w4, w23, w12, lt
	cmp	w30, w25
	cset	w5, gt
	cmp	w12, w23
	cset	w6, le
	cmp	w12, #0
	csel	w28, w1, w6, eq
	csel	w24, wzr, w5, eq
	csel	w23, w23, w4, eq
	csel	w25, w25, w3, eq
	b	LBB0_3
LBB0_2:
	mov	w24, #0
	mov	w28, #1
LBB0_3:
	and	w12, w26, w22
	ldr	w3, [x13]
	ldr	w4, [x14]
	ldp	w1, w13, [x21, #12]
	ldr	w14, [x21, #24]
	ldr	w15, [x15]
	ldr	w16, [x16]
	ldp	w6, w5, [x21, #32]
	ldr	w22, [x7]
	ldr	w7, [x27]
	ldr	w26, [x20]
	cmp	w26, #131
	b.eq	LBB0_6
; %bb.4:
	cmp	w26, #130
	b.eq	LBB0_8
; %bb.5:
	cmp	w26, #129
	b.ne	LBB0_9
LBB0_6:
	cbz	w24, LBB0_11
; %bb.7:
	tst	w4, w0
Lloh33:
	adrp	x21, _RADEON_HORZ_STRETCH_RATIO_MAX@GOTPAGE
Lloh34:
	ldr	x21, [x21, _RADEON_HORZ_STRETCH_RATIO_MAX@GOTPAGEOFF]
	cinc	w24, w25, ne
Lloh35:
	ldr	w21, [x21]
	mul	w21, w21, w24
	sdiv	w21, w21, w30
Lloh36:
	adrp	x24, _RADEON_HORZ_STRETCH_RATIO_MASK@GOTPAGE
Lloh37:
	ldr	x24, [x24, _RADEON_HORZ_STRETCH_RATIO_MASK@GOTPAGEOFF]
	add	w21, w21, #1
Lloh38:
	ldr	w24, [x24]
	and	w21, w21, w24
Lloh39:
	adrp	x24, _RADEON_HORZ_STRETCH_BLEND@GOTPAGE
Lloh40:
	ldr	x24, [x24, _RADEON_HORZ_STRETCH_BLEND@GOTPAGEOFF]
Lloh41:
	ldr	w24, [x24]
Lloh42:
	adrp	x25, _RADEON_HORZ_STRETCH_ENABLE@GOTPAGE
Lloh43:
	ldr	x25, [x25, _RADEON_HORZ_STRETCH_ENABLE@GOTPAGEOFF]
Lloh44:
	ldr	w25, [x25]
	add	w26, w30, #7
	cmp	w30, #0
	csel	w26, w26, w30, lt
	lsl	w26, w26, #13
	and	w26, w26, #0xffff0000
	sub	w26, w26, #16, lsl #12          ; =65536
	orr	w24, w24, w26
	orr	w21, w24, w21
	orr	w25, w21, w25
	b	LBB0_12
LBB0_8:
	add	w10, w25, #7
	cmp	w25, #0
	csel	w10, w10, w25, lt
	lsl	w10, w10, #13
	and	w10, w10, #0xffff0000
	sub	w25, w10, #16, lsl #12          ; =65536
	lsl	w10, w23, #12
	sub	w28, w10, #1, lsl #12           ; =4096
Lloh45:
	adrp	x10, _RADEON_CRTC_AUTO_HORZ_CENTER_EN@GOTPAGE
Lloh46:
	ldr	x10, [x10, _RADEON_CRTC_AUTO_HORZ_CENTER_EN@GOTPAGEOFF]
Lloh47:
	adrp	x11, _RADEON_CRTC_AUTO_VERT_CENTER_EN@GOTPAGE
Lloh48:
	ldr	x11, [x11, _RADEON_CRTC_AUTO_VERT_CENTER_EN@GOTPAGEOFF]
Lloh49:
	ldr	w10, [x10]
Lloh50:
	ldr	w11, [x11]
	orr	w10, w10, w19
	orr	w19, w10, w11
	ldp	w10, w17, [x21, #44]
	sub	w10, w10, w17
	add	w11, w10, #7
	cmp	w10, #0
	csel	w10, w11, w10, lt
	asr	w10, w10, #3
	mov	w11, #110
	cmp	w10, #110
	csel	w11, w10, w11, lt
	sub	w10, w8, w17
	add	w17, w10, #7
	cmp	w10, #0
	csel	w10, w17, w10, lt
	asr	w10, w10, #3
	ldp	w17, w21, [x21, #52]
	sub	w2, w17, w21
	sub	w17, w9, w21
	ldr	w20, [x20, #8]
	add	w21, w30, #7
	cmp	w30, #0
	csel	w21, w21, w30, lt
	lsl	w21, w21, #13
	and	w21, w21, #0x1ff0000
	bfxil	w21, w20, #0, #12
	b	LBB0_10
LBB0_9:
	mov	w21, #0
	add	w20, w25, #7
	cmp	w25, #0
	csel	w20, w20, w25, lt
	lsl	w20, w20, #13
	and	w20, w20, #0xffff0000
	sub	w25, w20, #16, lsl #12          ; =65536
	lsl	w20, w23, #12
	sub	w28, w20, #1, lsl #12           ; =4096
LBB0_10:
Lloh51:
	adrp	x26, _RADEON_FP_VERT_STRETCH@GOTPAGE
Lloh52:
	ldr	x26, [x26, _RADEON_FP_VERT_STRETCH@GOTPAGEOFF]
Lloh53:
	adrp	x27, _RADEON_FP_HORZ_STRETCH@GOTPAGE
Lloh54:
	ldr	x27, [x27, _RADEON_FP_HORZ_STRETCH@GOTPAGEOFF]
	b	LBB0_15
LBB0_11:
	add	w21, w25, #7
	cmp	w25, #0
	csel	w21, w21, w25, lt
	lsl	w21, w21, #13
	and	w21, w21, #0xffff0000
	sub	w25, w21, #16, lsl #12          ; =65536
LBB0_12:
Lloh55:
	adrp	x26, _RADEON_FP_VERT_STRETCH@GOTPAGE
Lloh56:
	ldr	x26, [x26, _RADEON_FP_VERT_STRETCH@GOTPAGEOFF]
Lloh57:
	adrp	x27, _RADEON_FP_HORZ_STRETCH@GOTPAGE
Lloh58:
	ldr	x27, [x27, _RADEON_FP_HORZ_STRETCH@GOTPAGEOFF]
	mov	w21, #0
	cbz	w28, LBB0_14
; %bb.13:
	lsl	w20, w23, #12
	sub	w28, w20, #1, lsl #12           ; =4096
	b	LBB0_15
LBB0_14:
Lloh59:
	adrp	x24, _RADEON_VERT_AUTO_RATIO_INC@GOTPAGE
Lloh60:
	ldr	x24, [x24, _RADEON_VERT_AUTO_RATIO_INC@GOTPAGEOFF]
Lloh61:
	ldr	w24, [x24]
	tst	w24, w12
	cinc	w23, w23, ne
Lloh62:
	adrp	x24, _RADEON_VERT_STRETCH_RATIO_MAX@GOTPAGE
Lloh63:
	ldr	x24, [x24, _RADEON_VERT_STRETCH_RATIO_MAX@GOTPAGEOFF]
Lloh64:
	ldr	w24, [x24]
	mul	w23, w23, w24
	ldr	w20, [x20, #8]
	sdiv	w23, w23, w20
	add	w23, w23, #1
Lloh65:
	adrp	x24, _RADEON_VERT_STRETCH_RATIO_MASK@GOTPAGE
Lloh66:
	ldr	x24, [x24, _RADEON_VERT_STRETCH_RATIO_MASK@GOTPAGEOFF]
Lloh67:
	ldr	w24, [x24]
	and	w23, w23, w24
Lloh68:
	adrp	x24, _RADEON_VERT_STRETCH_ENABLE@GOTPAGE
Lloh69:
	ldr	x24, [x24, _RADEON_VERT_STRETCH_ENABLE@GOTPAGEOFF]
Lloh70:
	ldr	w24, [x24]
	lsl	w20, w20, #12
	sub	w20, w20, #1, lsl #12           ; =4096
	orr	w20, w24, w20
Lloh71:
	adrp	x24, _RADEON_VERT_STRETCH_BLEND@GOTPAGE
Lloh72:
	ldr	x24, [x24, _RADEON_VERT_STRETCH_BLEND@GOTPAGEOFF]
Lloh73:
	ldr	w24, [x24]
	orr	w20, w20, w23
	orr	w28, w20, w24
LBB0_15:
	orr	w3, w4, w3
	and	w0, w3, w0
	bfi	w2, w6, #16, #16
	sub	w20, w2, #16, lsl #12           ; =65536
	tst	w22, w14
	csel	w2, wzr, w7, eq
	subs	w9, w5, w9
	ubfiz	w9, w9, #16, #5
	mov	w3, #65536
	csel	w9, w3, w9, eq
	and	w17, w17, #0xfff
	orr	w9, w2, w9
	orr	w22, w9, w17
	add	w9, w1, #7
	cmp	w1, #0
	csel	w9, w9, w1, lt
	lsl	w9, w9, #13
	and	w9, w9, #0x1ff0000
	mov	w17, #33488896
	add	w9, w9, w17
	and	w23, w9, #0x1ff0000
	bfxil	w23, w11, #0, #10
	tst	w15, w14
	csel	w9, wzr, w16, eq
	sub	w8, w13, w8
	add	w11, w8, #7
	cmp	w8, #0
	csel	w8, w11, w8, lt
	lsl	w8, w8, #13
	and	w8, w8, #0x3f0000
	cmp	w11, #15
	csel	w8, w3, w8, lo
	and	w10, w10, #0x1fff
	orr	w8, w9, w8
	orr	w24, w8, w10
	orr	w1, w25, w0
	orr	w25, w28, w12
	ldr	w0, [x27]
	bl	_WREG32
	ldr	w0, [x26]
	mov	x1, x25
	bl	_WREG32
Lloh74:
	adrp	x8, _RADEON_CRTC_MORE_CNTL@GOTPAGE
Lloh75:
	ldr	x8, [x8, _RADEON_CRTC_MORE_CNTL@GOTPAGEOFF]
Lloh76:
	ldr	w0, [x8]
	mov	x1, x19
	bl	_WREG32
Lloh77:
	adrp	x8, _RADEON_FP_HORZ_VERT_ACTIVE@GOTPAGE
Lloh78:
	ldr	x8, [x8, _RADEON_FP_HORZ_VERT_ACTIVE@GOTPAGEOFF]
Lloh79:
	ldr	w0, [x8]
	mov	x1, x21
	bl	_WREG32
Lloh80:
	adrp	x8, _RADEON_FP_H_SYNC_STRT_WID@GOTPAGE
Lloh81:
	ldr	x8, [x8, _RADEON_FP_H_SYNC_STRT_WID@GOTPAGEOFF]
Lloh82:
	ldr	w0, [x8]
	mov	x1, x24
	bl	_WREG32
Lloh83:
	adrp	x8, _RADEON_FP_V_SYNC_STRT_WID@GOTPAGE
Lloh84:
	ldr	x8, [x8, _RADEON_FP_V_SYNC_STRT_WID@GOTPAGEOFF]
Lloh85:
	ldr	w0, [x8]
	mov	x1, x22
	bl	_WREG32
Lloh86:
	adrp	x8, _RADEON_FP_CRTC_H_TOTAL_DISP@GOTPAGE
Lloh87:
	ldr	x8, [x8, _RADEON_FP_CRTC_H_TOTAL_DISP@GOTPAGEOFF]
Lloh88:
	ldr	w0, [x8]
	mov	x1, x23
	bl	_WREG32
Lloh89:
	adrp	x8, _RADEON_FP_CRTC_V_TOTAL_DISP@GOTPAGE
Lloh90:
	ldr	x8, [x8, _RADEON_FP_CRTC_V_TOTAL_DISP@GOTPAGEOFF]
Lloh91:
	ldr	w0, [x8]
	mov	x1, x20
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_WREG32
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh7
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh49
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_FP_VERT_STRETCH,4,2     ; @RADEON_FP_VERT_STRETCH
	.comm	_RADEON_VERT_STRETCH_RESERVED,4,2 ; @RADEON_VERT_STRETCH_RESERVED
	.comm	_RADEON_VERT_AUTO_RATIO_INC,4,2 ; @RADEON_VERT_AUTO_RATIO_INC
	.comm	_RADEON_FP_HORZ_STRETCH,4,2     ; @RADEON_FP_HORZ_STRETCH
	.comm	_RADEON_HORZ_FP_LOOP_STRETCH,4,2 ; @RADEON_HORZ_FP_LOOP_STRETCH
	.comm	_RADEON_HORZ_AUTO_RATIO_INC,4,2 ; @RADEON_HORZ_AUTO_RATIO_INC
	.comm	_CHIP_RS100,8,3                 ; @CHIP_RS100
	.comm	_CHIP_RS200,8,3                 ; @CHIP_RS200
	.comm	_RADEON_CRTC_H_CUTOFF_ACTIVE_EN,4,2 ; @RADEON_CRTC_H_CUTOFF_ACTIVE_EN
	.comm	_DRM_MODE_FLAG_NHSYNC,4,2       ; @DRM_MODE_FLAG_NHSYNC
	.comm	_RADEON_CRTC_H_SYNC_POL,4,2     ; @RADEON_CRTC_H_SYNC_POL
	.comm	_DRM_MODE_FLAG_NVSYNC,4,2       ; @DRM_MODE_FLAG_NVSYNC
	.comm	_RADEON_CRTC_V_SYNC_POL,4,2     ; @RADEON_CRTC_V_SYNC_POL
	.comm	_RADEON_HORZ_STRETCH_RATIO_MAX,4,2 ; @RADEON_HORZ_STRETCH_RATIO_MAX
	.comm	_RADEON_HORZ_STRETCH_RATIO_MASK,4,2 ; @RADEON_HORZ_STRETCH_RATIO_MASK
	.comm	_RADEON_HORZ_STRETCH_BLEND,4,2  ; @RADEON_HORZ_STRETCH_BLEND
	.comm	_RADEON_HORZ_STRETCH_ENABLE,4,2 ; @RADEON_HORZ_STRETCH_ENABLE
	.comm	_RADEON_VERT_STRETCH_RATIO_MAX,4,2 ; @RADEON_VERT_STRETCH_RATIO_MAX
	.comm	_RADEON_VERT_STRETCH_RATIO_MASK,4,2 ; @RADEON_VERT_STRETCH_RATIO_MASK
	.comm	_RADEON_VERT_STRETCH_ENABLE,4,2 ; @RADEON_VERT_STRETCH_ENABLE
	.comm	_RADEON_VERT_STRETCH_BLEND,4,2  ; @RADEON_VERT_STRETCH_BLEND
	.comm	_RADEON_CRTC_AUTO_HORZ_CENTER_EN,4,2 ; @RADEON_CRTC_AUTO_HORZ_CENTER_EN
	.comm	_RADEON_CRTC_AUTO_VERT_CENTER_EN,4,2 ; @RADEON_CRTC_AUTO_VERT_CENTER_EN
	.comm	_RADEON_CRTC_MORE_CNTL,4,2      ; @RADEON_CRTC_MORE_CNTL
	.comm	_RADEON_FP_HORZ_VERT_ACTIVE,4,2 ; @RADEON_FP_HORZ_VERT_ACTIVE
	.comm	_RADEON_FP_H_SYNC_STRT_WID,4,2  ; @RADEON_FP_H_SYNC_STRT_WID
	.comm	_RADEON_FP_V_SYNC_STRT_WID,4,2  ; @RADEON_FP_V_SYNC_STRT_WID
	.comm	_RADEON_FP_CRTC_H_TOTAL_DISP,4,2 ; @RADEON_FP_CRTC_H_TOTAL_DISP
	.comm	_RADEON_FP_CRTC_V_TOTAL_DISP,4,2 ; @RADEON_FP_CRTC_V_TOTAL_DISP
	.no_dead_strip	_radeon_legacy_rmx_mode_set
.subsections_via_symbols
