	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function set_vtx_resource
_set_vtx_resource:                      ## @set_vtx_resource
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r15d
	movq	%rdi, -48(%rbp)                 ## 8-byte Spill
	movq	_RADEON_RING_TYPE_GFX_INDEX@GOTPCREL(%rip), %rax
	movq	(%rax), %rbx
	shlq	$2, %rbx
	addq	8(%rdi), %rbx
	movl	%esi, %edi
	callq	_upper_32_bits
	movzbl	%al, %edi
	callq	_SQ_VTXC_BASE_ADDR_HI
	movl	%eax, %r12d
	movl	$16, %edi
	callq	_SQ_VTXC_STRIDE
	orl	%eax, %r12d
	movq	_SQ_SEL_X@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_SQ_VTCX_SEL_X
	movl	%eax, %r14d
	movq	_SQ_SEL_Y@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_SQ_VTCX_SEL_Y
	orl	%eax, %r14d
	movq	_SQ_SEL_Z@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_SQ_VTCX_SEL_Z
	movl	%eax, %r13d
	movq	_SQ_SEL_W@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_SQ_VTCX_SEL_W
	orl	%eax, %r13d
	orl	%r14d, %r13d
	movq	_PACKET3_SET_RESOURCE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$8, %esi
	callq	_PACKET3
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movq	%rbx, %rdi
	movl	$1408, %esi                     ## imm = 0x580
	callq	_radeon_ring_write
	movq	%rbx, %rdi
	movl	%r15d, %esi
	callq	_radeon_ring_write
	movq	%rbx, %rdi
	movl	$47, %esi
	callq	_radeon_ring_write
	movq	%rbx, %rdi
	movl	%r12d, %esi
	callq	_radeon_ring_write
	movq	%rbx, %rdi
	movl	%r13d, %esi
	callq	_radeon_ring_write
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_radeon_ring_write
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_radeon_ring_write
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_radeon_ring_write
	movq	_SQ_TEX_VTX_VALID_BUFFER@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_S__SQ_CONSTANT_TYPE
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movq	(%rdi), %rax
	movq	_CHIP_CEDAR@GOTPCREL(%rip), %r8
	movq	_CHIP_PALM@GOTPCREL(%rip), %r9
	movq	_CHIP_SUMO@GOTPCREL(%rip), %r10
	movq	_CHIP_SUMO2@GOTPCREL(%rip), %rcx
	movq	_CHIP_CAICOS@GOTPCREL(%rip), %rdx
	movq	_PACKET3_TC_ACTION_ENA@GOTPCREL(%rip), %rbx
	movq	%rbx, %rsi
	cmpq	(%rdx), %rax
	je	LBB0_2
## %bb.1:
	movq	_PACKET3_VC_ACTION_ENA@GOTPCREL(%rip), %rsi
LBB0_2:
	cmpq	(%rcx), %rax
	cmoveq	%rbx, %rsi
	cmpq	(%r10), %rax
	cmoveq	%rbx, %rsi
	cmpq	(%r9), %rax
	cmoveq	%rbx, %rsi
	cmpq	(%r8), %rax
	cmoveq	%rbx, %rsi
	movl	(%rsi), %esi
	movl	$48, %edx
	movl	%r15d, %ecx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_cp_set_surface_sync            ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_RING_TYPE_GFX_INDEX,8,3 ## @RADEON_RING_TYPE_GFX_INDEX
	.comm	_SQ_SEL_X,4,2                   ## @SQ_SEL_X
	.comm	_SQ_SEL_Y,4,2                   ## @SQ_SEL_Y
	.comm	_SQ_SEL_Z,4,2                   ## @SQ_SEL_Z
	.comm	_SQ_SEL_W,4,2                   ## @SQ_SEL_W
	.comm	_PACKET3_SET_RESOURCE,4,2       ## @PACKET3_SET_RESOURCE
	.comm	_SQ_TEX_VTX_VALID_BUFFER,4,2    ## @SQ_TEX_VTX_VALID_BUFFER
	.comm	_CHIP_CEDAR,8,3                 ## @CHIP_CEDAR
	.comm	_CHIP_PALM,8,3                  ## @CHIP_PALM
	.comm	_CHIP_SUMO,8,3                  ## @CHIP_SUMO
	.comm	_CHIP_SUMO2,8,3                 ## @CHIP_SUMO2
	.comm	_CHIP_CAICOS,8,3                ## @CHIP_CAICOS
	.comm	_PACKET3_TC_ACTION_ENA,4,2      ## @PACKET3_TC_ACTION_ENA
	.comm	_PACKET3_VC_ACTION_ENA,4,2      ## @PACKET3_VC_ACTION_ENA
	.comm	_SQ_ENDIAN_8IN32,4,2            ## @SQ_ENDIAN_8IN32
	.no_dead_strip	_set_vtx_resource
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function set_vtx_resource
_set_vtx_resource:                      ; @set_vtx_resource
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x1
	mov	x20, x0
	ldr	x8, [x0, #8]
Lloh0:
	adrp	x9, _RADEON_RING_TYPE_GFX_INDEX@GOTPAGE
Lloh1:
	ldr	x9, [x9, _RADEON_RING_TYPE_GFX_INDEX@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	add	x21, x8, x9, lsl #2
	mov	x0, x1
	bl	_upper_32_bits
	and	w0, w0, #0xff
	bl	_SQ_VTXC_BASE_ADDR_HI
	mov	x22, x0
	mov	w0, #16
	bl	_SQ_VTXC_STRIDE
	orr	w22, w0, w22
Lloh3:
	adrp	x8, _SQ_SEL_X@GOTPAGE
Lloh4:
	ldr	x8, [x8, _SQ_SEL_X@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	bl	_SQ_VTCX_SEL_X
	mov	x23, x0
Lloh6:
	adrp	x8, _SQ_SEL_Y@GOTPAGE
Lloh7:
	ldr	x8, [x8, _SQ_SEL_Y@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	bl	_SQ_VTCX_SEL_Y
	orr	w23, w0, w23
Lloh9:
	adrp	x8, _SQ_SEL_Z@GOTPAGE
Lloh10:
	ldr	x8, [x8, _SQ_SEL_Z@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	bl	_SQ_VTCX_SEL_Z
	orr	w23, w23, w0
Lloh12:
	adrp	x8, _SQ_SEL_W@GOTPAGE
Lloh13:
	ldr	x8, [x8, _SQ_SEL_W@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	bl	_SQ_VTCX_SEL_W
	orr	w23, w23, w0
Lloh15:
	adrp	x8, _PACKET3_SET_RESOURCE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _PACKET3_SET_RESOURCE@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	mov	w1, #8
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x21
	bl	_radeon_ring_write
	mov	x0, x21
	mov	w1, #1408
	bl	_radeon_ring_write
	mov	x0, x21
	mov	x1, x19
	bl	_radeon_ring_write
	mov	x0, x21
	mov	w1, #47
	bl	_radeon_ring_write
	mov	x0, x21
	mov	x1, x22
	bl	_radeon_ring_write
	mov	x0, x21
	mov	x1, x23
	bl	_radeon_ring_write
	mov	x0, x21
	mov	w1, #0
	bl	_radeon_ring_write
	mov	x0, x21
	mov	w1, #0
	bl	_radeon_ring_write
	mov	x0, x21
	mov	w1, #0
	bl	_radeon_ring_write
Lloh18:
	adrp	x8, _SQ_TEX_VTX_VALID_BUFFER@GOTPAGE
Lloh19:
	ldr	x8, [x8, _SQ_TEX_VTX_VALID_BUFFER@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
	bl	_S__SQ_CONSTANT_TYPE
	mov	x1, x0
	mov	x0, x21
	bl	_radeon_ring_write
	ldr	x8, [x20]
Lloh21:
	adrp	x9, _CHIP_CEDAR@GOTPAGE
Lloh22:
	ldr	x9, [x9, _CHIP_CEDAR@GOTPAGEOFF]
Lloh23:
	ldr	x9, [x9]
Lloh24:
	adrp	x10, _CHIP_PALM@GOTPAGE
Lloh25:
	ldr	x10, [x10, _CHIP_PALM@GOTPAGEOFF]
Lloh26:
	ldr	x10, [x10]
Lloh27:
	adrp	x11, _CHIP_SUMO@GOTPAGE
Lloh28:
	ldr	x11, [x11, _CHIP_SUMO@GOTPAGEOFF]
Lloh29:
	ldr	x11, [x11]
Lloh30:
	adrp	x12, _CHIP_SUMO2@GOTPAGE
Lloh31:
	ldr	x12, [x12, _CHIP_SUMO2@GOTPAGEOFF]
Lloh32:
	ldr	x12, [x12]
Lloh33:
	adrp	x13, _CHIP_CAICOS@GOTPAGE
Lloh34:
	ldr	x13, [x13, _CHIP_CAICOS@GOTPAGEOFF]
Lloh35:
	ldr	x13, [x13]
	cmp	x8, x13
	ccmp	x8, x12, #4, ne
	ccmp	x8, x11, #4, ne
	ccmp	x8, x10, #4, ne
	ccmp	x8, x9, #4, ne
Lloh36:
	adrp	x8, _PACKET3_TC_ACTION_ENA@GOTPAGE
Lloh37:
	ldr	x8, [x8, _PACKET3_TC_ACTION_ENA@GOTPAGEOFF]
Lloh38:
	adrp	x9, _PACKET3_VC_ACTION_ENA@GOTPAGE
Lloh39:
	ldr	x9, [x9, _PACKET3_VC_ACTION_ENA@GOTPAGEOFF]
	csel	x8, x8, x9, eq
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #48
	mov	x3, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_cp_set_surface_sync
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_RING_TYPE_GFX_INDEX,8,3 ; @RADEON_RING_TYPE_GFX_INDEX
	.comm	_SQ_SEL_X,4,2                   ; @SQ_SEL_X
	.comm	_SQ_SEL_Y,4,2                   ; @SQ_SEL_Y
	.comm	_SQ_SEL_Z,4,2                   ; @SQ_SEL_Z
	.comm	_SQ_SEL_W,4,2                   ; @SQ_SEL_W
	.comm	_PACKET3_SET_RESOURCE,4,2       ; @PACKET3_SET_RESOURCE
	.comm	_SQ_TEX_VTX_VALID_BUFFER,4,2    ; @SQ_TEX_VTX_VALID_BUFFER
	.comm	_CHIP_CEDAR,8,3                 ; @CHIP_CEDAR
	.comm	_CHIP_PALM,8,3                  ; @CHIP_PALM
	.comm	_CHIP_SUMO,8,3                  ; @CHIP_SUMO
	.comm	_CHIP_SUMO2,8,3                 ; @CHIP_SUMO2
	.comm	_CHIP_CAICOS,8,3                ; @CHIP_CAICOS
	.comm	_PACKET3_TC_ACTION_ENA,4,2      ; @PACKET3_TC_ACTION_ENA
	.comm	_PACKET3_VC_ACTION_ENA,4,2      ; @PACKET3_VC_ACTION_ENA
	.comm	_SQ_ENDIAN_8IN32,4,2            ; @SQ_ENDIAN_8IN32
	.no_dead_strip	_set_vtx_resource
.subsections_via_symbols
