	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_legacy_tv_mode_set      ## -- Begin function radeon_legacy_tv_mode_set
	.p2align	4, 0x90
_radeon_legacy_tv_mode_set:             ## @radeon_legacy_tv_mode_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$104, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	8(%rdi), %rax
	movq	(%rax), %r15
	callq	_to_radeon_encoder
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	leaq	-76(%rbp), %rsi
	movq	%rbx, %rdi
	callq	_radeon_legacy_tv_get_std_mode
	testq	%rax, %rax
	je	LBB0_36
## %bb.1:
	movq	%rax, %r13
	movq	%rbx, -136(%rbp)                ## 8-byte Spill
	movq	%r14, -128(%rbp)                ## 8-byte Spill
	movl	(%r14), %edi
	callq	_to_radeon_crtc
	movq	_RADEON_VIN_ASYNC_RST@GOTPCREL(%rip), %rcx
	movq	_RADEON_CRT_FIFO_CE_EN@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	movq	_RADEON_TV_FIFO_CE_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	%rax, %r14
	movq	_RADEON_TV_ON@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	%edx, -60(%rbp)                 ## 4-byte Spill
	movq	%r15, %rdi
	callq	_ASIC_IS_R300
	xorl	%ecx, %ecx
	movl	$0, %edx
	testl	%eax, %eax
	jne	LBB0_3
## %bb.2:
	movq	_RADEON_TVCLK_ALWAYS_ONb@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
LBB0_3:
	movl	%edx, -52(%rbp)                 ## 4-byte Spill
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rdx
	movq	_TV_STD_NTSC@GOTPCREL(%rip), %rax
	cmpq	(%rax), %rdx
	sete	%al
	movq	_TV_STD_NTSC_J@GOTPCREL(%rip), %rsi
	cmpq	(%rsi), %rdx
	sete	%bl
	orb	%al, %bl
	je	LBB0_5
## %bb.4:
	movq	_RADEON_RESTART_PHASE_FIX@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
LBB0_5:
	movl	%ecx, -88(%rbp)                 ## 4-byte Spill
	movq	_RADEON_SLEW_RATE_LIMIT@GOTPCREL(%rip), %rax
	movq	_RADEON_SYNC_TIP_LEVEL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	orl	(%rax), %edi
	movq	_RADEON_YFLT_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	_RADEON_UVFLT_EN@GOTPCREL(%rip), %rax
	movq	_RADEON_CY_FILT_BLEND_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$6, %esi
	shll	%cl, %esi
	movl	%esi, -64(%rbp)                 ## 4-byte Spill
	cmpb	$1, %bl
	jne	LBB0_7
## %bb.6:
	movq	_RADEON_SET_UP_LEVEL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$70, %edx
	shll	%cl, %edx
	movq	_RADEON_BLANK_LEVEL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$59, %esi
	shll	%cl, %esi
	orl	%edx, %esi
	movl	%esi, -68(%rbp)                 ## 4-byte Spill
	movq	_RADEON_TV_U_BURST_LEVEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	$-111, %ecx
	movl	%ecx, -72(%rbp)                 ## 4-byte Spill
	jmp	LBB0_10
LBB0_7:
	movq	_TV_STD_SCART_PAL@GOTPCREL(%rip), %rcx
	movq	_RADEON_ALT_PHASE_EN@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	cmpq	(%rcx), %rdx
	jne	LBB0_9
## %bb.8:
	movl	%esi, -68(%rbp)                 ## 4-byte Spill
	movl	$0, -72(%rbp)                   ## 4-byte Folded Spill
	jmp	LBB0_10
LBB0_9:
	movq	_RADEON_SET_UP_LEVEL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$59, %edx
	shll	%cl, %edx
	orl	%esi, %edx
	movl	$59, %esi
	movq	_RADEON_BLANK_LEVEL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %esi
	orl	%edx, %esi
	movq	_RADEON_TV_U_BURST_LEVEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	andl	$-78, %edx
	movq	_RADEON_TV_V_BURST_LEVEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	andl	$62, %ebx
	movq	_RADEON_TV_V_BURST_LEVEL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %ebx
	orl	%edx, %ebx
	movl	%ebx, -72(%rbp)                 ## 4-byte Spill
	movl	%esi, -68(%rbp)                 ## 4-byte Spill
LBB0_10:
	orl	(%rax), %edi
	movl	%edi, -56(%rbp)                 ## 4-byte Spill
	movq	_RADEON_RGB_DITHER_EN@GOTPCREL(%rip), %rax
	movq	_RADEON_TVOUT_SCALE_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	_RADEON_UVRAM_READ_MARGIN_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$11, %r15d
	shll	%cl, %r15d
	orl	%edx, %r15d
	movq	_RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$7, %r12d
	shll	%cl, %r12d
	movl	$3, %edi
	callq	_RADEON_RGB_ATTEN_SEL
	movl	%eax, %ebx
	orl	%r12d, %ebx
	orl	%r15d, %ebx
	movl	$12, %edi
	callq	_RADEON_RGB_ATTEN_VAL
	orl	%ebx, %eax
	cmpl	$1, (%r14)
	jne	LBB0_12
## %bb.11:
	movq	_RADEON_RGB_SRC_SEL_CRTC2@GOTPCREL(%rip), %rcx
	jmp	LBB0_15
LBB0_12:
	movq	8(%r14), %rdx
	movq	_RMX_OFF@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rdx
	jne	LBB0_13
## %bb.14:
	movq	_RADEON_RGB_SRC_SEL_CRTC1@GOTPCREL(%rip), %rcx
	jmp	LBB0_15
LBB0_13:
	movq	_RADEON_RGB_SRC_SEL_RMX@GOTPCREL(%rip), %rcx
LBB0_15:
	orl	(%rcx), %eax
	movl	%eax, -100(%rbp)                ## 4-byte Spill
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rcx
	movq	_TV_STD_PAL_M@GOTPCREL(%rip), %rdi
	movq	_TV_STD_PAL_60@GOTPCREL(%rip), %rdx
	movq	%r13, -120(%rbp)                ## 8-byte Spill
	imull	$20000, (%r13), %eax            ## imm = 0x4E20
	cmpq	(%rdx), %rcx
	movq	_NTSC_TV_LINES_PER_FRAME@GOTPCREL(%rip), %r13
	movq	_PAL_TV_LINES_PER_FRAME@GOTPCREL(%rip), %r14
	movq	%r14, %rsi
	cmoveq	%r13, %rsi
	cmpq	(%rdi), %rcx
	cmoveq	%r13, %rsi
	movq	_TV_STD_NTSC_J@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	cmoveq	%r13, %rsi
	movq	_TV_STD_NTSC@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	cmoveq	%r13, %rsi
	cltd
	idivl	(%rsi)
	movl	%eax, %r12d
	movq	_RADEON_TV_VSCALER_CNTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	andl	$-469827584, %eax               ## imm = 0xE3FF0000
	movq	_FRAC_BITS@GOTPCREL(%rip), %r15
	movb	(%r15), %cl
	movl	%r12d, %edx
	shll	%cl, %edx
	movslq	%edx, %rcx
	imulq	$1759218605, %rcx, %rdi         ## imm = 0x68DB8BAD
	movq	%rdi, %rcx
	shrq	$63, %rcx
	sarq	$44, %rdi
	addl	%ecx, %edi
	xorl	%ebx, %ebx
	cmpl	$2700, -76(%rbp)                ## imm = 0xA8C
	movl	$0, %ecx
	jne	LBB0_17
## %bb.16:
	movq	_RADEON_RESTART_FIELD@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_17:
	orl	%ecx, %eax
	xorl	%edx, %edx
	movq	-120(%rbp), %rsi                ## 8-byte Reload
	cmpl	$1024, 4(%rsi)                  ## imm = 0x400
	sete	%dl
	movq	_RADEON_Y_DEL_W_SIG_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	addl	%edx, %edx
	addl	$2, %edx
	shll	%cl, %edx
	orl	%eax, %edx
	orl	%edx, %edi
	movq	%rdi, -112(%rbp)                ## 8-byte Spill
	imull	$2000, (%rsi), %eax             ## imm = 0x7D0
	movq	-48(%rbp), %rcx                 ## 8-byte Reload
	movq	(%rcx), %rcx
	movq	_TV_STD_PAL_60@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	cmoveq	%r13, %r14
	movq	_TV_STD_PAL_M@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	cmoveq	%r13, %r14
	movq	_TV_STD_NTSC_J@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	cmoveq	%r13, %r14
	movq	_TV_STD_NTSC@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	cmoveq	%r13, %r14
	cltd
	idivl	(%r14)
	addl	$500, %eax                      ## imm = 0x1F4
	cltq
	imulq	$274877907, %rax, %rax          ## imm = 0x10624DD3
	movq	%rax, %rcx
	shrq	$63, %rcx
	sarq	$38, %rax
	addl	%ecx, %eax
	cmpl	$4, %eax
	movl	$3, %r14d
	cmovgel	%eax, %r14d
	movq	_SLOPE_limit@GOTPCREL(%rip), %r13
	movq	(%r13), %rdi
	callq	_ARRAY_SIZE
	testl	%eax, %eax
	jle	LBB0_21
## %bb.18:
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_19:                                ## =>This Inner Loop Header: Depth=1
	movq	(%r13), %rdi
	cmpl	(%rdi,%rbx,4), %r14d
	je	LBB0_21
## %bb.20:                              ##   in Loop: Header=BB0_19 Depth=1
	incq	%rbx
	callq	_ARRAY_SIZE
	cltq
	cmpq	%rax, %rbx
	jl	LBB0_19
LBB0_21:
	movq	_SLOPE_value@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movl	%ebx, %edx
	shlq	$2, %rdx
	movl	(%rax,%rdx), %eax
	imull	%eax, %r12d
	movb	(%r15), %cl
	decb	%cl
	shll	%cl, %r12d
	addl	$5001, %r12d                    ## imm = 0x1389
	movslq	%r12d, %rsi
	imulq	$1759218605, %rsi, %r15         ## imm = 0x68DB8BAD
	movq	%r15, %r13
	shrq	$63, %r13
	sarq	$47, %r15
	movl	%eax, %esi
	shll	%cl, %esi
	leal	7(%rsi), %r12d
	testl	%esi, %esi
	cmovnsl	%esi, %r12d
	movq	_YCOEF_EN_value@GOTPCREL(%rip), %rsi
	movq	(%rsi), %rsi
	movl	(%rsi,%rdx), %esi
	shll	$17, %esi
	movq	_YCOEF_value@GOTPCREL(%rip), %rdi
	movq	(%rdi), %rdi
	movl	(%rdi,%rdx), %edi
	movl	%eax, %edx
	shll	$5, %edx
	leal	(%rdx,%rax,2), %edx
	shll	%cl, %edx
	shll	$29, %edi
	movq	_RADEON_Y_FALL_PING_PONG@GOTPCREL(%rip), %r8
	leal	1023(%rdx), %ebx
	testl	%edx, %edx
	cmovnsl	%edx, %ebx
	sarl	$10, %ebx
	orl	%esi, %edi
	orl	%ebx, %edi
	orl	(%r8), %edi
	movl	%edi, -96(%rbp)                 ## 4-byte Spill
	movq	_RADEON_Y_RISE_PING_PONG@GOTPCREL(%rip), %rdx
	shll	$10, %r14d
	addl	$-272, %r14d                    ## imm = 0xFEF0
	imull	%eax, %r14d
	sarl	$3, %r14d
	shll	%cl, %r14d
	leal	1023(%r14), %eax
	testl	%r14d, %r14d
	cmovnsl	%r14d, %eax
	sarl	$10, %eax
	orl	(%rdx), %eax
	movl	%eax, -92(%rbp)                 ## 4-byte Spill
	movq	_RADEON_TV_VSCALER_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r14d
	andl	$16777200, %r14d                ## imm = 0xFFFFF0
	movq	_RADEON_DITHER_MODE@GOTPCREL(%rip), %rax
	movq	_RADEON_Y_OUTPUT_DITHER_EN@GOTPCREL(%rip), %rcx
	movq	_RADEON_UV_OUTPUT_DITHER_EN@GOTPCREL(%rip), %rdx
	orl	(%rax), %r14d
	orl	(%rcx), %r14d
	orl	(%rdx), %r14d
	movq	_RADEON_UV_TO_BUF_DITHER_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
	movq	_RADEON_UV_INC_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movq	-112(%rbp), %rax                ## 8-byte Reload
	movl	%eax, %esi
	sarl	%cl, %esi
	movq	_RADEON_UV_INC_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %esi
	movl	$41943040, %eax                 ## imm = 0x2800000
	xorl	%edx, %edx
	idivl	%esi
	addl	$5, %eax
	cltq
	imulq	$1717986919, %rax, %rax         ## imm = 0x66666667
	movq	%rax, %rcx
	shrq	$63, %rcx
	sarq	$34, %rax
	addl	%ecx, %eax
	movq	_RADEON_UV_OUTPUT_POST_SCALE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	orl	$720896, %eax                   ## imm = 0xB0000
	movq	-48(%rbp), %rcx                 ## 8-byte Reload
	movl	%eax, 16(%rcx)
	movq	(%rcx), %rax
	movq	_TV_STD_NTSC@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	sete	%cl
	movq	_TV_STD_NTSC_J@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rax
	sete	%dl
	orb	%cl, %dl
	movq	_TV_STD_PAL_M@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	sete	%cl
	movq	_TV_STD_PAL_60@GOTPCREL(%rip), %rsi
	cmpq	(%rsi), %rax
	sete	%al
	orb	%cl, %al
	orb	%dl, %al
	movl	%eax, %ecx
	xorb	$1, %cl
	movzbl	%cl, %esi
	movq	_RADEON_TV_DAC_NBLANK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	_RADEON_TV_DAC_NHOLD@GOTPCREL(%rip), %rdi
	testb	%dl, %dl
	je	LBB0_22
## %bb.23:
	movq	_RADEON_TV_DAC_STD_NTSC@GOTPCREL(%rip), %r9
	jmp	LBB0_24
LBB0_22:
	movq	_RADEON_TV_DAC_STD_PAL@GOTPCREL(%rip), %r9
LBB0_24:
	movl	-60(%rbp), %r10d                ## 4-byte Reload
	movl	-56(%rbp), %r11d                ## 4-byte Reload
	andl	$-8, %r12d
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	orl	8(%rbx,%rsi,4), %ecx
	orl	(%rdi), %ecx
	movl	-76(%rbp), %esi
	testb	%dl, %dl
	je	LBB0_26
## %bb.25:
	cmpl	$2700, %esi                     ## imm = 0xA8C
	movq	_NTSC_TV_PLL_M_14@GOTPCREL(%rip), %rsi
	cmoveq	_NTSC_TV_PLL_M_27@GOTPCREL(%rip), %rsi
	movq	_NTSC_TV_PLL_N_14@GOTPCREL(%rip), %rdi
	cmoveq	_NTSC_TV_PLL_N_27@GOTPCREL(%rip), %rdi
	movq	_NTSC_TV_PLL_P_14@GOTPCREL(%rip), %r8
	cmoveq	_NTSC_TV_PLL_P_27@GOTPCREL(%rip), %r8
	jmp	LBB0_27
LBB0_26:
	cmpl	$2700, %esi                     ## imm = 0xA8C
	movq	_PAL_TV_PLL_M_14@GOTPCREL(%rip), %rsi
	cmoveq	_PAL_TV_PLL_M_27@GOTPCREL(%rip), %rsi
	movq	_PAL_TV_PLL_N_14@GOTPCREL(%rip), %rdi
	cmoveq	_PAL_TV_PLL_N_27@GOTPCREL(%rip), %rdi
	movq	_PAL_TV_PLL_P_14@GOTPCREL(%rip), %r8
	cmoveq	_PAL_TV_PLL_P_27@GOTPCREL(%rip), %r8
LBB0_27:
	movl	-52(%rbp), %edx                 ## 4-byte Reload
	orl	%edx, %r10d
	orl	-64(%rbp), %r11d                ## 4-byte Folded Reload
	addl	%r13d, %r15d
	shll	$13, %r12d
	orl	(%r9), %ecx
	movl	%ecx, -52(%rbp)                 ## 4-byte Spill
	movl	(%rdi), %edi
	movl	(%rsi), %esi
	movq	_RADEON_TV_M0LO_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	andl	%esi, %ebx
	sarl	$8, %esi
	movq	_RADEON_TV_M0HI_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %esi
	movq	_RADEON_TV_M0HI_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %esi
	movq	_RADEON_TV_N0LO_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movq	_RADEON_TV_N0LO_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r13d
	andl	%edi, %r13d
	shll	%cl, %r13d
	orl	%ebx, %r13d
	orl	%esi, %r13d
	sarl	$9, %edi
	movq	_RADEON_TV_N0HI_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %edi
	movq	_RADEON_TV_N0HI_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edi
	movq	_RADEON_TV_P_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r9d
	andl	(%r8), %r9d
	movq	_RADEON_TV_P_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r9d
	orl	%edi, %r9d
	movq	-48(%rbp), %rcx                 ## 8-byte Reload
	movl	$200, 20(%rcx)
	movq	_vert_timing_PAL@GOTPCREL(%rip), %rcx
	testb	%al, %al
	cmovneq	_vert_timing_NTSC@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rax
	movq	_hor_timing_PAL@GOTPCREL(%rip), %rdx
	cmovneq	_hor_timing_NTSC@GOTPCREL(%rip), %rdx
	movq	_PAL_TV_VFTOTAL@GOTPCREL(%rip), %rcx
	cmovneq	_NTSC_TV_VFTOTAL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, -64(%rbp)                 ## 4-byte Spill
	movq	_MAX_H_CODE_TIMING_LEN@GOTPCREL(%rip), %rcx
	cmpl	$0, (%rcx)
	jle	LBB0_31
## %bb.28:
	movq	(%rdx), %rdx
	movq	-48(%rbp), %rsi                 ## 8-byte Reload
	movq	24(%rsi), %rdi
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_30:                                ## =>This Inner Loop Header: Depth=1
	movl	(%rdx,%rbx,4), %esi
	movl	%esi, (%rdi,%rbx,4)
	testl	%esi, %esi
	je	LBB0_31
## %bb.29:                              ##   in Loop: Header=BB0_30 Depth=1
	incq	%rbx
	movslq	(%rcx), %rsi
	cmpq	%rsi, %rbx
	jl	LBB0_30
LBB0_31:
	orl	-88(%rbp), %r10d                ## 4-byte Folded Reload
	movl	%r10d, %ebx
	orl	-68(%rbp), %r11d                ## 4-byte Folded Reload
	movl	%r11d, -56(%rbp)                ## 4-byte Spill
	orl	%r12d, %r15d
	movq	%r15, -88(%rbp)                 ## 8-byte Spill
	orl	$268435456, %r14d               ## imm = 0x10000000
	orl	%r9d, %r13d
	movq	_MAX_V_CODE_TIMING_LEN@GOTPCREL(%rip), %rcx
	cmpl	$0, (%rcx)
	jle	LBB0_35
## %bb.32:
	movq	-48(%rbp), %rdx                 ## 8-byte Reload
	movq	32(%rdx), %rdx
	xorl	%esi, %esi
	.p2align	4, 0x90
LBB0_34:                                ## =>This Inner Loop Header: Depth=1
	movl	(%rax,%rsi,4), %edi
	movl	%edi, (%rdx,%rsi,4)
	testl	%edi, %edi
	je	LBB0_35
## %bb.33:                              ##   in Loop: Header=BB0_34 Depth=1
	incq	%rsi
	movslq	(%rcx), %rdi
	cmpq	%rdi, %rsi
	jl	LBB0_34
LBB0_35:
	movq	-128(%rbp), %r15                ## 8-byte Reload
	movq	%r15, %rdi
	callq	_radeon_legacy_tv_init_restarts
	movq	_RADEON_TV_MASTER_CNTL@GOTPCREL(%rip), %rcx
	movq	_RADEON_TV_ASYNC_RST@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%ebx, -60(%rbp)                 ## 4-byte Spill
	orl	%ebx, %esi
	movq	_RADEON_CRT_ASYNC_RST@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	(%rcx), %edi
	movq	_RADEON_TV_FIFO_ASYNC_RST@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	callq	_WREG32
	movq	_RADEON_TV_DAC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	%rax, %rbx
	callq	_RREG32
	movq	_RADEON_TV_DAC_NBLANK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_RADEON_TV_DAC_BGSLEEP@GOTPCREL(%rip), %rax
	movq	_RADEON_TV_DAC_RDACPD@GOTPCREL(%rip), %rcx
	movq	_RADEON_TV_DAC_GDACPD@GOTPCREL(%rip), %rdx
	orl	(%rax), %esi
	orl	(%rcx), %esi
	orl	(%rdx), %esi
	movq	_RADEON_TV_DAC_BDACPD@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	(%rbx), %edi
	callq	_WREG32
	movq	_RADEON_TV_PLL_CNTL1@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	movq	_RADEON_TVCLK_SRC_SEL_TVPLL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	xorl	%esi, %esi
	callq	_WREG32_PLL_P
	movq	_RADEON_TV_PLL_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r13d, %esi
	callq	_WREG32_PLL
	movl	(%r12), %edi
	movq	_RADEON_TVPLL_RESET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movl	%esi, %edx
	notl	%edx
	callq	_WREG32_PLL_P
	movq	%r15, %rdi
	movl	$200, %esi
	movl	$800, %edx                      ## imm = 0x320
	movl	$135, %ecx
	callq	_radeon_wait_pll_lock
	movl	(%r12), %edi
	movl	(%rbx), %edx
	notl	%edx
	xorl	%esi, %esi
	callq	_WREG32_PLL_P
	movq	%r15, %rdi
	movl	$300, %esi                      ## imm = 0x12C
	movl	$160, %edx
	movl	$27, %ecx
	callq	_radeon_wait_pll_lock
	movq	%r15, %rdi
	movl	$200, %esi
	movl	$800, %edx                      ## imm = 0x320
	movl	$135, %ecx
	callq	_radeon_wait_pll_lock
	movl	(%r12), %edi
	xorl	%esi, %esi
	movl	$-16, %edx
	callq	_WREG32_PLL_P
	movl	(%r12), %edi
	movq	_RADEON_TVCLK_SRC_SEL_TVPLL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%esi, %edx
	notl	%edx
	callq	_WREG32_PLL_P
	movq	_RADEON_TVPDC_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$1, %esi
	shll	%cl, %esi
	movl	(%r12), %edi
	movq	_RADEON_TVPDC_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	callq	_WREG32_PLL_P
	movl	(%r12), %edi
	movq	_RADEON_TVPLL_SLEEP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	xorl	%esi, %esi
	callq	_WREG32_PLL_P
	movq	_RADEON_TV_RGB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-100(%rbp), %esi                ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_TV_HTOTAL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	-120(%rbp), %rbx                ## 8-byte Reload
	movl	8(%rbx), %esi
	decl	%esi
	callq	_WREG32
	movq	_RADEON_TV_HDISP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	4(%rbx), %esi
	decl	%esi
	callq	_WREG32
	movq	_RADEON_TV_HSTART@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	12(%rbx), %esi
	callq	_WREG32
	movq	_RADEON_TV_VTOTAL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%rbx), %esi
	decl	%esi
	callq	_WREG32
	movq	_RADEON_TV_VDISP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	16(%rbx), %esi
	decl	%esi
	callq	_WREG32
	movq	_RADEON_TV_FTOTAL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-64(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_TV_VSCALER_CNTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	-112(%rbp), %rsi                ## 8-byte Reload
                                        ## kill: def $esi killed $esi killed $rsi
	callq	_WREG32
	movq	_RADEON_TV_VSCALER_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_RADEON_TV_Y_FALL_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-96(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_TV_Y_RISE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-92(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_TV_Y_SAW_TOOTH_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	-88(%rbp), %rsi                 ## 8-byte Reload
                                        ## kill: def $esi killed $esi killed $rsi
	callq	_WREG32
	movq	_RADEON_TV_MASTER_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movq	_RADEON_TV_ASYNC_RST@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movl	-60(%rbp), %r15d                ## 4-byte Reload
	orl	%r15d, %esi
	movq	_RADEON_CRT_ASYNC_RST@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	callq	_WREG32
	movq	-136(%rbp), %rbx                ## 8-byte Reload
	movq	%rbx, %rdi
	callq	_radeon_legacy_write_tv_restarts
	movq	%rbx, %rdi
	callq	_radeon_restore_tv_timing_tables
	movl	(%r14), %edi
	movl	(%r12), %esi
	orl	%r15d, %esi
	movl	%r15d, %ebx
	callq	_WREG32
	movq	_RADEON_TV_SYNC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_SYNC_PUB@GOTPCREL(%rip), %rax
	movq	_RADEON_TV_SYNC_IO_DRIVE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	callq	_WREG32
	movq	_RADEON_TV_TIMING_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movl	16(%rax), %esi
	callq	_WREG32
	movq	_RADEON_TV_MODULATOR_CNTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-56(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_TV_MODULATOR_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-72(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_Y_RED_EN@GOTPCREL(%rip), %rax
	movq	_RADEON_C_GRN_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movq	_RADEON_TV_PRE_DAC_MUX_CNTL@GOTPCREL(%rip), %rax
	movq	_RADEON_CMP_BLU_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movl	(%rax), %edi
	movq	_RADEON_DAC_DITHER_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	callq	_WREG32
	movq	_RADEON_TV_CRC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r14), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movq	_RADEON_TV_GAIN_LIMIT_SETTINGS@GOTPCREL(%rip), %rax
	movq	_RADEON_UV_GAIN_LIMIT_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$383, %edx                      ## imm = 0x17F
	shll	%cl, %edx
	movl	(%rax), %edi
	movq	_RADEON_Y_GAIN_LIMIT_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$1535, %esi                     ## imm = 0x5FF
	shll	%cl, %esi
	orl	%edx, %esi
	callq	_WREG32
	movq	_RADEON_TV_LINEAR_GAIN_SETTINGS@GOTPCREL(%rip), %rax
	movq	_RADEON_UV_GAIN_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$256, %edx                      ## imm = 0x100
	shll	%cl, %edx
	movl	(%rax), %edi
	movl	$256, %esi                      ## imm = 0x100
	movq	_RADEON_Y_GAIN_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %esi
	orl	%edx, %esi
	callq	_WREG32
	movq	_RADEON_TV_DAC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-52(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
LBB0_36:
	addq	$104, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_VIN_ASYNC_RST,4,2       ## @RADEON_VIN_ASYNC_RST
	.comm	_RADEON_CRT_FIFO_CE_EN,4,2      ## @RADEON_CRT_FIFO_CE_EN
	.comm	_RADEON_TV_FIFO_CE_EN,4,2       ## @RADEON_TV_FIFO_CE_EN
	.comm	_RADEON_TV_ON,4,2               ## @RADEON_TV_ON
	.comm	_RADEON_TVCLK_ALWAYS_ONb,4,2    ## @RADEON_TVCLK_ALWAYS_ONb
	.comm	_TV_STD_NTSC,8,3                ## @TV_STD_NTSC
	.comm	_TV_STD_NTSC_J,8,3              ## @TV_STD_NTSC_J
	.comm	_RADEON_RESTART_PHASE_FIX,4,2   ## @RADEON_RESTART_PHASE_FIX
	.comm	_RADEON_SLEW_RATE_LIMIT,4,2     ## @RADEON_SLEW_RATE_LIMIT
	.comm	_RADEON_SYNC_TIP_LEVEL,4,2      ## @RADEON_SYNC_TIP_LEVEL
	.comm	_RADEON_YFLT_EN,4,2             ## @RADEON_YFLT_EN
	.comm	_RADEON_UVFLT_EN,4,2            ## @RADEON_UVFLT_EN
	.comm	_RADEON_CY_FILT_BLEND_SHIFT,4,2 ## @RADEON_CY_FILT_BLEND_SHIFT
	.comm	_RADEON_SET_UP_LEVEL_SHIFT,4,2  ## @RADEON_SET_UP_LEVEL_SHIFT
	.comm	_RADEON_BLANK_LEVEL_SHIFT,4,2   ## @RADEON_BLANK_LEVEL_SHIFT
	.comm	_RADEON_TV_U_BURST_LEVEL_MASK,4,2 ## @RADEON_TV_U_BURST_LEVEL_MASK
	.comm	_RADEON_TV_V_BURST_LEVEL_MASK,4,2 ## @RADEON_TV_V_BURST_LEVEL_MASK
	.comm	_RADEON_TV_V_BURST_LEVEL_SHIFT,4,2 ## @RADEON_TV_V_BURST_LEVEL_SHIFT
	.comm	_TV_STD_SCART_PAL,8,3           ## @TV_STD_SCART_PAL
	.comm	_RADEON_ALT_PHASE_EN,4,2        ## @RADEON_ALT_PHASE_EN
	.comm	_RADEON_RGB_DITHER_EN,4,2       ## @RADEON_RGB_DITHER_EN
	.comm	_RADEON_TVOUT_SCALE_EN,4,2      ## @RADEON_TVOUT_SCALE_EN
	.comm	_RADEON_UVRAM_READ_MARGIN_SHIFT,4,2 ## @RADEON_UVRAM_READ_MARGIN_SHIFT
	.comm	_RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT,4,2 ## @RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT
	.comm	_RADEON_RGB_SRC_SEL_CRTC2,4,2   ## @RADEON_RGB_SRC_SEL_CRTC2
	.comm	_RMX_OFF,8,3                    ## @RMX_OFF
	.comm	_RADEON_RGB_SRC_SEL_RMX,4,2     ## @RADEON_RGB_SRC_SEL_RMX
	.comm	_RADEON_RGB_SRC_SEL_CRTC1,4,2   ## @RADEON_RGB_SRC_SEL_CRTC1
	.comm	_TV_STD_PAL_M,8,3               ## @TV_STD_PAL_M
	.comm	_TV_STD_PAL_60,8,3              ## @TV_STD_PAL_60
	.comm	_NTSC_TV_LINES_PER_FRAME,4,2    ## @NTSC_TV_LINES_PER_FRAME
	.comm	_PAL_TV_LINES_PER_FRAME,4,2     ## @PAL_TV_LINES_PER_FRAME
	.comm	_RADEON_TV_VSCALER_CNTL1,4,2    ## @RADEON_TV_VSCALER_CNTL1
	.comm	_FRAC_BITS,4,2                  ## @FRAC_BITS
	.comm	_RADEON_RESTART_FIELD,4,2       ## @RADEON_RESTART_FIELD
	.comm	_RADEON_Y_DEL_W_SIG_SHIFT,4,2   ## @RADEON_Y_DEL_W_SIG_SHIFT
	.comm	_SLOPE_limit,8,3                ## @SLOPE_limit
	.comm	_SLOPE_value,8,3                ## @SLOPE_value
	.comm	_YCOEF_EN_value,8,3             ## @YCOEF_EN_value
	.comm	_YCOEF_value,8,3                ## @YCOEF_value
	.comm	_RADEON_Y_FALL_PING_PONG,4,2    ## @RADEON_Y_FALL_PING_PONG
	.comm	_RADEON_Y_RISE_PING_PONG,4,2    ## @RADEON_Y_RISE_PING_PONG
	.comm	_RADEON_TV_VSCALER_CNTL2,4,2    ## @RADEON_TV_VSCALER_CNTL2
	.comm	_RADEON_DITHER_MODE,4,2         ## @RADEON_DITHER_MODE
	.comm	_RADEON_Y_OUTPUT_DITHER_EN,4,2  ## @RADEON_Y_OUTPUT_DITHER_EN
	.comm	_RADEON_UV_OUTPUT_DITHER_EN,4,2 ## @RADEON_UV_OUTPUT_DITHER_EN
	.comm	_RADEON_UV_TO_BUF_DITHER_EN,4,2 ## @RADEON_UV_TO_BUF_DITHER_EN
	.comm	_RADEON_UV_INC_SHIFT,4,2        ## @RADEON_UV_INC_SHIFT
	.comm	_RADEON_UV_INC_MASK,4,2         ## @RADEON_UV_INC_MASK
	.comm	_RADEON_UV_OUTPUT_POST_SCALE_SHIFT,4,2 ## @RADEON_UV_OUTPUT_POST_SCALE_SHIFT
	.comm	_RADEON_TV_DAC_NBLANK,4,2       ## @RADEON_TV_DAC_NBLANK
	.comm	_RADEON_TV_DAC_NHOLD,4,2        ## @RADEON_TV_DAC_NHOLD
	.comm	_RADEON_TV_DAC_STD_NTSC,4,2     ## @RADEON_TV_DAC_STD_NTSC
	.comm	_RADEON_TV_DAC_STD_PAL,4,2      ## @RADEON_TV_DAC_STD_PAL
	.comm	_NTSC_TV_PLL_M_27,4,2           ## @NTSC_TV_PLL_M_27
	.comm	_NTSC_TV_PLL_N_27,4,2           ## @NTSC_TV_PLL_N_27
	.comm	_NTSC_TV_PLL_P_27,4,2           ## @NTSC_TV_PLL_P_27
	.comm	_NTSC_TV_PLL_M_14,4,2           ## @NTSC_TV_PLL_M_14
	.comm	_NTSC_TV_PLL_N_14,4,2           ## @NTSC_TV_PLL_N_14
	.comm	_NTSC_TV_PLL_P_14,4,2           ## @NTSC_TV_PLL_P_14
	.comm	_PAL_TV_PLL_M_27,4,2            ## @PAL_TV_PLL_M_27
	.comm	_PAL_TV_PLL_N_27,4,2            ## @PAL_TV_PLL_N_27
	.comm	_PAL_TV_PLL_P_27,4,2            ## @PAL_TV_PLL_P_27
	.comm	_PAL_TV_PLL_M_14,4,2            ## @PAL_TV_PLL_M_14
	.comm	_PAL_TV_PLL_N_14,4,2            ## @PAL_TV_PLL_N_14
	.comm	_PAL_TV_PLL_P_14,4,2            ## @PAL_TV_PLL_P_14
	.comm	_RADEON_TV_M0LO_MASK,4,2        ## @RADEON_TV_M0LO_MASK
	.comm	_RADEON_TV_M0HI_MASK,4,2        ## @RADEON_TV_M0HI_MASK
	.comm	_RADEON_TV_M0HI_SHIFT,4,2       ## @RADEON_TV_M0HI_SHIFT
	.comm	_RADEON_TV_N0LO_MASK,4,2        ## @RADEON_TV_N0LO_MASK
	.comm	_RADEON_TV_N0LO_SHIFT,4,2       ## @RADEON_TV_N0LO_SHIFT
	.comm	_RADEON_TV_N0HI_MASK,4,2        ## @RADEON_TV_N0HI_MASK
	.comm	_RADEON_TV_N0HI_SHIFT,4,2       ## @RADEON_TV_N0HI_SHIFT
	.comm	_RADEON_TV_P_MASK,4,2           ## @RADEON_TV_P_MASK
	.comm	_RADEON_TV_P_SHIFT,4,2          ## @RADEON_TV_P_SHIFT
	.comm	_RADEON_TVPCP_MASK,4,2          ## @RADEON_TVPCP_MASK
	.comm	_RADEON_TVPCP_SHIFT,4,2         ## @RADEON_TVPCP_SHIFT
	.comm	_RADEON_TVPVG_MASK,4,2          ## @RADEON_TVPVG_MASK
	.comm	_RADEON_TVPVG_SHIFT,4,2         ## @RADEON_TVPVG_SHIFT
	.comm	_RADEON_TVPDC_MASK,4,2          ## @RADEON_TVPDC_MASK
	.comm	_RADEON_TVPDC_SHIFT,4,2         ## @RADEON_TVPDC_SHIFT
	.comm	_RADEON_TVCLK_SRC_SEL_TVPLL,4,2 ## @RADEON_TVCLK_SRC_SEL_TVPLL
	.comm	_RADEON_TVPLL_TEST_DIS,4,2      ## @RADEON_TVPLL_TEST_DIS
	.comm	_NTSC_TV_VFTOTAL,4,2            ## @NTSC_TV_VFTOTAL
	.comm	_hor_timing_NTSC,8,3            ## @hor_timing_NTSC
	.comm	_vert_timing_NTSC,8,3           ## @vert_timing_NTSC
	.comm	_hor_timing_PAL,8,3             ## @hor_timing_PAL
	.comm	_vert_timing_PAL,8,3            ## @vert_timing_PAL
	.comm	_PAL_TV_VFTOTAL,4,2             ## @PAL_TV_VFTOTAL
	.comm	_MAX_H_CODE_TIMING_LEN,4,2      ## @MAX_H_CODE_TIMING_LEN
	.comm	_MAX_V_CODE_TIMING_LEN,4,2      ## @MAX_V_CODE_TIMING_LEN
	.comm	_RADEON_TV_MASTER_CNTL,4,2      ## @RADEON_TV_MASTER_CNTL
	.comm	_RADEON_TV_ASYNC_RST,4,2        ## @RADEON_TV_ASYNC_RST
	.comm	_RADEON_CRT_ASYNC_RST,4,2       ## @RADEON_CRT_ASYNC_RST
	.comm	_RADEON_TV_FIFO_ASYNC_RST,4,2   ## @RADEON_TV_FIFO_ASYNC_RST
	.comm	_RADEON_TV_DAC_CNTL,4,2         ## @RADEON_TV_DAC_CNTL
	.comm	_RADEON_TV_DAC_BGSLEEP,4,2      ## @RADEON_TV_DAC_BGSLEEP
	.comm	_RADEON_TV_DAC_RDACPD,4,2       ## @RADEON_TV_DAC_RDACPD
	.comm	_RADEON_TV_DAC_GDACPD,4,2       ## @RADEON_TV_DAC_GDACPD
	.comm	_RADEON_TV_DAC_BDACPD,4,2       ## @RADEON_TV_DAC_BDACPD
	.comm	_RADEON_TV_PLL_CNTL1,4,2        ## @RADEON_TV_PLL_CNTL1
	.comm	_RADEON_TV_PLL_CNTL,4,2         ## @RADEON_TV_PLL_CNTL
	.comm	_RADEON_TVPLL_RESET,4,2         ## @RADEON_TVPLL_RESET
	.comm	_RADEON_TVPLL_SLEEP,4,2         ## @RADEON_TVPLL_SLEEP
	.comm	_RADEON_TV_RGB_CNTL,4,2         ## @RADEON_TV_RGB_CNTL
	.comm	_RADEON_TV_HTOTAL,4,2           ## @RADEON_TV_HTOTAL
	.comm	_RADEON_TV_HDISP,4,2            ## @RADEON_TV_HDISP
	.comm	_RADEON_TV_HSTART,4,2           ## @RADEON_TV_HSTART
	.comm	_RADEON_TV_VTOTAL,4,2           ## @RADEON_TV_VTOTAL
	.comm	_RADEON_TV_VDISP,4,2            ## @RADEON_TV_VDISP
	.comm	_RADEON_TV_FTOTAL,4,2           ## @RADEON_TV_FTOTAL
	.comm	_RADEON_TV_Y_FALL_CNTL,4,2      ## @RADEON_TV_Y_FALL_CNTL
	.comm	_RADEON_TV_Y_RISE_CNTL,4,2      ## @RADEON_TV_Y_RISE_CNTL
	.comm	_RADEON_TV_Y_SAW_TOOTH_CNTL,4,2 ## @RADEON_TV_Y_SAW_TOOTH_CNTL
	.comm	_RADEON_TV_SYNC_CNTL,4,2        ## @RADEON_TV_SYNC_CNTL
	.comm	_RADEON_SYNC_PUB,4,2            ## @RADEON_SYNC_PUB
	.comm	_RADEON_TV_SYNC_IO_DRIVE,4,2    ## @RADEON_TV_SYNC_IO_DRIVE
	.comm	_RADEON_TV_TIMING_CNTL,4,2      ## @RADEON_TV_TIMING_CNTL
	.comm	_RADEON_TV_MODULATOR_CNTL1,4,2  ## @RADEON_TV_MODULATOR_CNTL1
	.comm	_RADEON_TV_MODULATOR_CNTL2,4,2  ## @RADEON_TV_MODULATOR_CNTL2
	.comm	_RADEON_TV_PRE_DAC_MUX_CNTL,4,2 ## @RADEON_TV_PRE_DAC_MUX_CNTL
	.comm	_RADEON_Y_RED_EN,4,2            ## @RADEON_Y_RED_EN
	.comm	_RADEON_C_GRN_EN,4,2            ## @RADEON_C_GRN_EN
	.comm	_RADEON_CMP_BLU_EN,4,2          ## @RADEON_CMP_BLU_EN
	.comm	_RADEON_DAC_DITHER_EN,4,2       ## @RADEON_DAC_DITHER_EN
	.comm	_RADEON_TV_CRC_CNTL,4,2         ## @RADEON_TV_CRC_CNTL
	.comm	_RADEON_TV_GAIN_LIMIT_SETTINGS,4,2 ## @RADEON_TV_GAIN_LIMIT_SETTINGS
	.comm	_RADEON_UV_GAIN_LIMIT_SHIFT,4,2 ## @RADEON_UV_GAIN_LIMIT_SHIFT
	.comm	_RADEON_Y_GAIN_LIMIT_SHIFT,4,2  ## @RADEON_Y_GAIN_LIMIT_SHIFT
	.comm	_RADEON_TV_LINEAR_GAIN_SETTINGS,4,2 ## @RADEON_TV_LINEAR_GAIN_SETTINGS
	.comm	_RADEON_UV_GAIN_SHIFT,4,2       ## @RADEON_UV_GAIN_SHIFT
	.comm	_RADEON_Y_GAIN_SHIFT,4,2        ## @RADEON_Y_GAIN_SHIFT
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_legacy_tv_mode_set      ; -- Begin function radeon_legacy_tv_mode_set
	.p2align	2
_radeon_legacy_tv_mode_set:             ; @radeon_legacy_tv_mode_set
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #176
	.cfi_def_cfa_offset 176
	stp	x28, x27, [sp, #80]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #96]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #112]            ; 16-byte Folded Spill
	stp	x22, x21, [sp, #128]            ; 16-byte Folded Spill
	stp	x20, x19, [sp, #144]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #160]            ; 16-byte Folded Spill
	add	x29, sp, #160
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x20, x0
	ldr	x8, [x0, #8]
	ldr	x21, [x8]
	bl	_to_radeon_encoder
	mov	x23, x0
	ldr	x19, [x0]
	add	x1, sp, #76
	bl	_radeon_legacy_tv_get_std_mode
	str	x0, [sp, #64]                   ; 8-byte Folded Spill
	cbz	x0, LBB0_27
; %bb.1:
	str	x23, [sp, #40]                  ; 8-byte Folded Spill
	ldr	w0, [x20]
	bl	_to_radeon_crtc
	mov	x23, x0
Lloh0:
	adrp	x8, _RADEON_VIN_ASYNC_RST@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_VIN_ASYNC_RST@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _RADEON_CRT_FIFO_CE_EN@GOTPAGE
Lloh4:
	ldr	x9, [x9, _RADEON_CRT_FIFO_CE_EN@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	orr	w24, w9, w8
Lloh6:
	adrp	x8, _RADEON_TV_FIFO_CE_EN@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_TV_FIFO_CE_EN@GOTPAGEOFF]
Lloh8:
	ldr	w25, [x8]
Lloh9:
	adrp	x8, _RADEON_TV_ON@GOTPAGE
Lloh10:
	ldr	x8, [x8, _RADEON_TV_ON@GOTPAGEOFF]
Lloh11:
	ldr	w27, [x8]
	mov	x0, x21
	bl	_ASIC_IS_R300
Lloh12:
	adrp	x8, _RADEON_TVCLK_ALWAYS_ONb@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RADEON_TVCLK_ALWAYS_ONb@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	cmp	w0, #0
	csel	w8, w8, wzr, eq
	str	w8, [sp, #20]                   ; 4-byte Folded Spill
	ldr	x11, [x19]
Lloh15:
	adrp	x8, _TV_STD_NTSC@GOTPAGE
Lloh16:
	ldr	x8, [x8, _TV_STD_NTSC@GOTPAGEOFF]
Lloh17:
	ldr	x8, [x8]
	cmp	x11, x8
Lloh18:
	adrp	x8, _TV_STD_NTSC_J@GOTPAGE
Lloh19:
	ldr	x8, [x8, _TV_STD_NTSC_J@GOTPAGEOFF]
Lloh20:
	ldr	x8, [x8]
Lloh21:
	adrp	x9, _RADEON_RESTART_PHASE_FIX@GOTPAGE
Lloh22:
	ldr	x9, [x9, _RADEON_RESTART_PHASE_FIX@GOTPAGEOFF]
	ccmp	x11, x8, #4, ne
Lloh23:
	ldr	w8, [x9]
	csel	w8, w8, wzr, eq
	str	w8, [sp, #32]                   ; 4-byte Folded Spill
Lloh24:
	adrp	x8, _RADEON_SLEW_RATE_LIMIT@GOTPAGE
Lloh25:
	ldr	x8, [x8, _RADEON_SLEW_RATE_LIMIT@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
Lloh27:
	adrp	x9, _RADEON_SYNC_TIP_LEVEL@GOTPAGE
Lloh28:
	ldr	x9, [x9, _RADEON_SYNC_TIP_LEVEL@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh30:
	adrp	x9, _RADEON_YFLT_EN@GOTPAGE
Lloh31:
	ldr	x9, [x9, _RADEON_YFLT_EN@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
Lloh33:
	adrp	x10, _RADEON_UVFLT_EN@GOTPAGE
Lloh34:
	ldr	x10, [x10, _RADEON_UVFLT_EN@GOTPAGEOFF]
Lloh35:
	adrp	x12, _RADEON_CY_FILT_BLEND_SHIFT@GOTPAGE
Lloh36:
	ldr	x12, [x12, _RADEON_CY_FILT_BLEND_SHIFT@GOTPAGEOFF]
Lloh37:
	ldr	w12, [x12]
	stp	x12, x19, [sp, #48]             ; 16-byte Folded Spill
	b.ne	LBB0_3
; %bb.2:
Lloh38:
	adrp	x11, _RADEON_SET_UP_LEVEL_SHIFT@GOTPAGE
Lloh39:
	ldr	x11, [x11, _RADEON_SET_UP_LEVEL_SHIFT@GOTPAGEOFF]
Lloh40:
	ldr	w11, [x11]
	mov	w12, #70
	lsl	w11, w12, w11
Lloh41:
	adrp	x12, _RADEON_BLANK_LEVEL_SHIFT@GOTPAGE
Lloh42:
	ldr	x12, [x12, _RADEON_BLANK_LEVEL_SHIFT@GOTPAGEOFF]
Lloh43:
	ldr	w12, [x12]
	mov	w13, #59
	lsl	w12, w13, w12
	orr	w11, w12, w11
	str	w11, [sp, #28]                  ; 4-byte Folded Spill
Lloh44:
	adrp	x11, _RADEON_TV_U_BURST_LEVEL_MASK@GOTPAGE
Lloh45:
	ldr	x11, [x11, _RADEON_TV_U_BURST_LEVEL_MASK@GOTPAGEOFF]
Lloh46:
	ldr	w11, [x11]
	mov	w12, #-111
	and	w11, w11, w12
	b	LBB0_6
LBB0_3:
Lloh47:
	adrp	x12, _TV_STD_SCART_PAL@GOTPAGE
Lloh48:
	ldr	x12, [x12, _TV_STD_SCART_PAL@GOTPAGEOFF]
Lloh49:
	ldr	x12, [x12]
Lloh50:
	adrp	x13, _RADEON_ALT_PHASE_EN@GOTPAGE
Lloh51:
	ldr	x13, [x13, _RADEON_ALT_PHASE_EN@GOTPAGEOFF]
Lloh52:
	ldr	w14, [x13]
	cmp	x11, x12
	b.ne	LBB0_5
; %bb.4:
	str	w14, [sp, #28]                  ; 4-byte Folded Spill
	str	wzr, [sp, #36]                  ; 4-byte Folded Spill
	b	LBB0_7
LBB0_5:
Lloh53:
	adrp	x11, _RADEON_SET_UP_LEVEL_SHIFT@GOTPAGE
Lloh54:
	ldr	x11, [x11, _RADEON_SET_UP_LEVEL_SHIFT@GOTPAGEOFF]
Lloh55:
	ldr	w11, [x11]
	mov	w12, #59
	lsl	w11, w12, w11
Lloh56:
	adrp	x13, _RADEON_BLANK_LEVEL_SHIFT@GOTPAGE
Lloh57:
	ldr	x13, [x13, _RADEON_BLANK_LEVEL_SHIFT@GOTPAGEOFF]
	orr	w11, w11, w14
Lloh58:
	ldr	w13, [x13]
	lsl	w12, w12, w13
	orr	w11, w11, w12
	str	w11, [sp, #28]                  ; 4-byte Folded Spill
Lloh59:
	adrp	x11, _RADEON_TV_U_BURST_LEVEL_MASK@GOTPAGE
Lloh60:
	ldr	x11, [x11, _RADEON_TV_U_BURST_LEVEL_MASK@GOTPAGEOFF]
Lloh61:
	ldr	w11, [x11]
	mov	w12, #-78
	and	w11, w11, w12
Lloh62:
	adrp	x12, _RADEON_TV_V_BURST_LEVEL_MASK@GOTPAGE
Lloh63:
	ldr	x12, [x12, _RADEON_TV_V_BURST_LEVEL_MASK@GOTPAGEOFF]
Lloh64:
	ldr	w12, [x12]
	and	w12, w12, #0x3e
Lloh65:
	adrp	x13, _RADEON_TV_V_BURST_LEVEL_SHIFT@GOTPAGE
Lloh66:
	ldr	x13, [x13, _RADEON_TV_V_BURST_LEVEL_SHIFT@GOTPAGEOFF]
Lloh67:
	ldr	w13, [x13]
	lsl	w12, w12, w13
	orr	w11, w12, w11
LBB0_6:
	str	w11, [sp, #36]                  ; 4-byte Folded Spill
LBB0_7:
	orr	w21, w24, w25
	orr	w25, w8, w9
	ldr	w26, [x10]
Lloh68:
	adrp	x8, _RADEON_RGB_DITHER_EN@GOTPAGE
Lloh69:
	ldr	x8, [x8, _RADEON_RGB_DITHER_EN@GOTPAGEOFF]
	mov	w28, #6
Lloh70:
	ldr	w8, [x8]
Lloh71:
	adrp	x9, _RADEON_TVOUT_SCALE_EN@GOTPAGE
Lloh72:
	ldr	x9, [x9, _RADEON_TVOUT_SCALE_EN@GOTPAGEOFF]
Lloh73:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh74:
	adrp	x9, _RADEON_UVRAM_READ_MARGIN_SHIFT@GOTPAGE
Lloh75:
	ldr	x9, [x9, _RADEON_UVRAM_READ_MARGIN_SHIFT@GOTPAGEOFF]
Lloh76:
	ldr	w9, [x9]
	mov	w10, #11
	lsl	w9, w10, w9
	orr	w8, w8, w9
Lloh77:
	adrp	x9, _RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT@GOTPAGE
Lloh78:
	ldr	x9, [x9, _RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT@GOTPAGEOFF]
Lloh79:
	ldr	w9, [x9]
	mov	w10, #7
	lsl	w9, w10, w9
	orr	w19, w8, w9
	mov	w0, #3
	bl	_RADEON_RGB_ATTEN_SEL
	mov	x24, x0
	mov	w0, #12
	bl	_RADEON_RGB_ATTEN_VAL
	str	w0, [sp, #12]                   ; 4-byte Folded Spill
	ldr	w8, [x23]
	cmp	w8, #1
	b.ne	LBB0_9
; %bb.8:
Lloh80:
	adrp	x8, _RADEON_RGB_SRC_SEL_CRTC2@GOTPAGE
Lloh81:
	ldr	x8, [x8, _RADEON_RGB_SRC_SEL_CRTC2@GOTPAGEOFF]
	b	LBB0_10
LBB0_9:
	ldr	x8, [x23, #8]
Lloh82:
	adrp	x9, _RMX_OFF@GOTPAGE
Lloh83:
	ldr	x9, [x9, _RMX_OFF@GOTPAGEOFF]
Lloh84:
	ldr	x9, [x9]
Lloh85:
	adrp	x10, _RADEON_RGB_SRC_SEL_RMX@GOTPAGE
Lloh86:
	ldr	x10, [x10, _RADEON_RGB_SRC_SEL_RMX@GOTPAGEOFF]
Lloh87:
	adrp	x11, _RADEON_RGB_SRC_SEL_CRTC1@GOTPAGE
Lloh88:
	ldr	x11, [x11, _RADEON_RGB_SRC_SEL_CRTC1@GOTPAGEOFF]
	cmp	x8, x9
	csel	x8, x11, x10, eq
LBB0_10:
	orr	w9, w21, w27
	str	w9, [sp, #16]                   ; 4-byte Folded Spill
	orr	w9, w25, w26
	str	w9, [sp, #4]                    ; 4-byte Folded Spill
	ldr	x9, [sp, #48]                   ; 8-byte Folded Reload
	lsl	w9, w28, w9
	str	w9, [sp]                        ; 4-byte Folded Spill
	orr	w9, w19, w24
	str	w9, [sp, #8]                    ; 4-byte Folded Spill
	ldr	w8, [x8]
	str	w8, [sp, #24]                   ; 4-byte Folded Spill
	ldp	x28, x26, [sp, #56]             ; 16-byte Folded Reload
	ldr	x8, [x28]
Lloh89:
	adrp	x19, _TV_STD_NTSC@GOTPAGE
Lloh90:
	ldr	x19, [x19, _TV_STD_NTSC@GOTPAGEOFF]
	ldr	x9, [x19]
Lloh91:
	adrp	x23, _TV_STD_NTSC_J@GOTPAGE
Lloh92:
	ldr	x23, [x23, _TV_STD_NTSC_J@GOTPAGEOFF]
	ldr	x10, [x23]
Lloh93:
	adrp	x22, _TV_STD_PAL_M@GOTPAGE
Lloh94:
	ldr	x22, [x22, _TV_STD_PAL_M@GOTPAGEOFF]
	ldr	x11, [x22]
Lloh95:
	adrp	x27, _TV_STD_PAL_60@GOTPAGE
Lloh96:
	ldr	x27, [x27, _TV_STD_PAL_60@GOTPAGEOFF]
	ldr	x12, [x27]
	cmp	x8, x12
	ccmp	x8, x11, #4, ne
	ccmp	x8, x10, #4, ne
	ccmp	x8, x9, #4, ne
	ldr	w8, [x26]
	mov	w9, #20000
	mul	w8, w8, w9
Lloh97:
	adrp	x21, _NTSC_TV_LINES_PER_FRAME@GOTPAGE
Lloh98:
	ldr	x21, [x21, _NTSC_TV_LINES_PER_FRAME@GOTPAGEOFF]
Lloh99:
	adrp	x25, _PAL_TV_LINES_PER_FRAME@GOTPAGE
Lloh100:
	ldr	x25, [x25, _PAL_TV_LINES_PER_FRAME@GOTPAGEOFF]
	csel	x9, x21, x25, eq
	ldr	w9, [x9]
	sdiv	w24, w8, w9
Lloh101:
	adrp	x8, _RADEON_TV_VSCALER_CNTL1@GOTPAGE
Lloh102:
	ldr	x8, [x8, _RADEON_TV_VSCALER_CNTL1@GOTPAGEOFF]
Lloh103:
	ldr	w0, [x8]
	bl	_RREG32
	mov	w8, #-469827584
	and	w8, w0, w8
Lloh104:
	adrp	x9, _FRAC_BITS@GOTPAGE
Lloh105:
	ldr	x9, [x9, _FRAC_BITS@GOTPAGEOFF]
Lloh106:
	ldr	w9, [x9]
	lsl	w9, w24, w9
	mov	w10, #35757
	movk	w10, #26843, lsl #16
	smull	x9, w9, w10
	lsr	x10, x9, #63
	asr	x9, x9, #44
	add	w9, w9, w10
	orr	w8, w9, w8
	ldr	w9, [sp, #76]
Lloh107:
	adrp	x10, _RADEON_RESTART_FIELD@GOTPAGE
Lloh108:
	ldr	x10, [x10, _RADEON_RESTART_FIELD@GOTPAGEOFF]
Lloh109:
	ldr	w10, [x10]
	cmp	w9, #2700
	csel	w9, w10, wzr, eq
	orr	w8, w8, w9
Lloh110:
	adrp	x9, _RADEON_Y_DEL_W_SIG_SHIFT@GOTPAGE
Lloh111:
	ldr	x9, [x9, _RADEON_Y_DEL_W_SIG_SHIFT@GOTPAGEOFF]
Lloh112:
	ldr	w9, [x9]
	mov	w10, #2
	mov	w11, #4
	ldp	w13, w12, [x26]
	cmp	w12, #1024
	csel	w10, w11, w10, eq
	lsl	w9, w10, w9
	orr	w8, w8, w9
	str	w8, [sp, #48]                   ; 4-byte Folded Spill
	mov	w8, #2000
	mul	w8, w13, w8
	ldr	x9, [x28]
	ldr	x10, [x19]
	ldr	x11, [x23]
	ldr	x12, [x22]
	ldr	x13, [x27]
	cmp	x9, x13
	ccmp	x9, x12, #4, ne
	ccmp	x9, x11, #4, ne
	ccmp	x9, x10, #4, ne
	csel	x9, x21, x25, eq
	ldr	w9, [x9]
	sdiv	w8, w8, w9
	add	w8, w8, #500
	mov	w9, #19923
	movk	w9, #4194, lsl #16
	smull	x8, w8, w9
	lsr	x9, x8, #63
	asr	x8, x8, #38
	add	w8, w8, w9
	cmp	w8, #3
	mov	w9, #3
	csel	w21, w8, w9, gt
Lloh113:
	adrp	x28, _SLOPE_limit@GOTPAGE
Lloh114:
	ldr	x28, [x28, _SLOPE_limit@GOTPAGEOFF]
	ldr	x0, [x28]
	bl	_ARRAY_SIZE
	cmp	w0, #1
	b.lt	LBB0_14
; %bb.11:
	mov	x25, #0
	mov	x22, x20
LBB0_12:                                ; =>This Inner Loop Header: Depth=1
	ldr	x0, [x28]
	ldr	w8, [x0, x25, lsl #2]
	cmp	w21, w8
	b.eq	LBB0_15
; %bb.13:                               ;   in Loop: Header=BB0_12 Depth=1
	add	x25, x25, #1
	bl	_ARRAY_SIZE
	cmp	x25, w0, sxtw
	b.lt	LBB0_12
	b	LBB0_15
LBB0_14:
	mov	x25, #0
	mov	x22, x20
LBB0_15:
	ldp	w9, w8, [sp, #16]               ; 8-byte Folded Reload
	orr	w8, w9, w8
	str	w8, [sp, #20]                   ; 4-byte Folded Spill
	ldp	w9, w8, [sp]                    ; 8-byte Folded Reload
	orr	w8, w8, w9
	str	w8, [sp, #16]                   ; 4-byte Folded Spill
Lloh115:
	adrp	x8, _SLOPE_value@GOTPAGE
Lloh116:
	ldr	x8, [x8, _SLOPE_value@GOTPAGEOFF]
	ldp	w10, w9, [sp, #8]               ; 8-byte Folded Reload
	orr	w9, w10, w9
	str	w9, [sp, #12]                   ; 4-byte Folded Spill
Lloh117:
	ldr	x8, [x8]
	ubfiz	x9, x25, #2, #32
	ldr	w8, [x8, x9]
	mul	w10, w8, w24
Lloh118:
	adrp	x11, _FRAC_BITS@GOTPAGE
Lloh119:
	ldr	x11, [x11, _FRAC_BITS@GOTPAGEOFF]
Lloh120:
	ldr	w11, [x11]
	sub	w11, w11, #1
	lsl	w10, w10, w11
	mov	w12, #5001
	add	w10, w10, w12
	mov	w12, #35757
	movk	w12, #26843, lsl #16
	smull	x10, w10, w12
	lsr	x12, x10, #63
	asr	x10, x10, #47
	add	w19, w10, w12
	lsl	w10, w8, w11
	add	w12, w10, #7
	cmp	w10, #0
	csel	w10, w12, w10, lt
Lloh121:
	adrp	x12, _YCOEF_EN_value@GOTPAGE
Lloh122:
	ldr	x12, [x12, _YCOEF_EN_value@GOTPAGEOFF]
Lloh123:
	ldr	x12, [x12]
	ldr	w12, [x12, x9]
	lsl	w10, w10, #13
Lloh124:
	adrp	x13, _YCOEF_value@GOTPAGE
Lloh125:
	ldr	x13, [x13, _YCOEF_value@GOTPAGEOFF]
Lloh126:
	ldr	x13, [x13]
	ldr	w9, [x13, x9]
	and	w24, w10, #0xffff0000
Lloh127:
	adrp	x10, _RADEON_Y_FALL_PING_PONG@GOTPAGE
Lloh128:
	ldr	x10, [x10, _RADEON_Y_FALL_PING_PONG@GOTPAGEOFF]
Lloh129:
	ldr	w23, [x10]
	add	w10, w8, w8, lsl #4
	lsl	w10, w10, #1
	lsl	w10, w10, w11
	add	w13, w10, #1023
	cmp	w10, #0
	csel	w10, w13, w10, lt
	asr	w10, w10, #10
	orr	w10, w10, w12, lsl #17
	orr	w26, w10, w9, lsl #29
Lloh130:
	adrp	x9, _RADEON_Y_RISE_PING_PONG@GOTPAGE
Lloh131:
	ldr	x9, [x9, _RADEON_Y_RISE_PING_PONG@GOTPAGEOFF]
Lloh132:
	ldr	w27, [x9]
	lsl	w9, w21, #10
	sub	w9, w9, #272
	mul	w8, w8, w9
	orr	w9, w8, #0x7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w8, w8, #3
	lsl	w8, w8, w11
	add	w9, w8, #1023
	cmp	w8, #0
	csel	w21, w9, w8, lt
Lloh133:
	adrp	x8, _RADEON_TV_VSCALER_CNTL2@GOTPAGE
Lloh134:
	ldr	x8, [x8, _RADEON_TV_VSCALER_CNTL2@GOTPAGEOFF]
Lloh135:
	ldr	w0, [x8]
	bl	_RREG32
	and	w8, w0, #0xfffff0
Lloh136:
	adrp	x9, _RADEON_DITHER_MODE@GOTPAGE
Lloh137:
	ldr	x9, [x9, _RADEON_DITHER_MODE@GOTPAGEOFF]
Lloh138:
	ldr	w9, [x9]
Lloh139:
	adrp	x10, _RADEON_Y_OUTPUT_DITHER_EN@GOTPAGE
Lloh140:
	ldr	x10, [x10, _RADEON_Y_OUTPUT_DITHER_EN@GOTPAGEOFF]
Lloh141:
	ldr	w10, [x10]
Lloh142:
	adrp	x11, _RADEON_UV_OUTPUT_DITHER_EN@GOTPAGE
Lloh143:
	ldr	x11, [x11, _RADEON_UV_OUTPUT_DITHER_EN@GOTPAGEOFF]
Lloh144:
	ldr	w11, [x11]
Lloh145:
	adrp	x12, _RADEON_UV_TO_BUF_DITHER_EN@GOTPAGE
Lloh146:
	ldr	x12, [x12, _RADEON_UV_TO_BUF_DITHER_EN@GOTPAGEOFF]
Lloh147:
	ldr	w12, [x12]
	orr	w8, w9, w8
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w9, w8, w12
Lloh148:
	adrp	x8, _RADEON_UV_INC_SHIFT@GOTPAGE
Lloh149:
	ldr	x8, [x8, _RADEON_UV_INC_SHIFT@GOTPAGEOFF]
Lloh150:
	ldr	w8, [x8]
Lloh151:
	adrp	x10, _RADEON_UV_INC_MASK@GOTPAGE
Lloh152:
	ldr	x10, [x10, _RADEON_UV_INC_MASK@GOTPAGEOFF]
	ldr	w11, [sp, #48]                  ; 4-byte Folded Reload
	asr	w8, w11, w8
Lloh153:
	ldr	w10, [x10]
	and	w8, w8, w10
	mov	w10, #41943040
	sdiv	w8, w10, w8
	add	w8, w8, #5
	mov	w10, #26215
	movk	w10, #26214, lsl #16
	smull	x8, w8, w10
	lsr	x10, x8, #63
	asr	x8, x8, #34
Lloh154:
	adrp	x11, _RADEON_UV_OUTPUT_POST_SCALE_SHIFT@GOTPAGE
Lloh155:
	ldr	x11, [x11, _RADEON_UV_OUTPUT_POST_SCALE_SHIFT@GOTPAGEOFF]
	add	w8, w8, w10
Lloh156:
	ldr	w10, [x11]
	lsl	w8, w8, w10
	mov	w10, #720896
	orr	w8, w8, w10
	ldr	x28, [sp, #56]                  ; 8-byte Folded Reload
	str	w8, [x28, #16]
	ldr	x8, [x28]
Lloh157:
	adrp	x10, _TV_STD_NTSC@GOTPAGE
Lloh158:
	ldr	x10, [x10, _TV_STD_NTSC@GOTPAGEOFF]
Lloh159:
	ldr	x10, [x10]
	cmp	x8, x10
Lloh160:
	adrp	x10, _TV_STD_NTSC_J@GOTPAGE
Lloh161:
	ldr	x10, [x10, _TV_STD_NTSC_J@GOTPAGEOFF]
Lloh162:
	ldr	x10, [x10]
	ccmp	x8, x10, #4, ne
	cset	w13, eq
Lloh163:
	adrp	x10, _TV_STD_PAL_M@GOTPAGE
Lloh164:
	ldr	x10, [x10, _TV_STD_PAL_M@GOTPAGEOFF]
Lloh165:
	ldr	x10, [x10]
	cmp	x8, x10
	cset	w10, eq
	orr	w10, w13, w10
Lloh166:
	adrp	x11, _TV_STD_PAL_60@GOTPAGE
Lloh167:
	ldr	x11, [x11, _TV_STD_PAL_60@GOTPAGEOFF]
Lloh168:
	ldr	x11, [x11]
	cmp	x8, x11
	cset	w8, eq
	orr	w8, w10, w8
	cmp	w8, #0
	mov	w10, #12
	mov	w11, #8
	csel	x10, x11, x10, ne
	ldr	w11, [x28, x10]
Lloh169:
	adrp	x20, _RADEON_TV_DAC_NBLANK@GOTPAGE
Lloh170:
	ldr	x20, [x20, _RADEON_TV_DAC_NBLANK@GOTPAGEOFF]
Lloh171:
	adrp	x10, _RADEON_TV_DAC_NHOLD@GOTPAGE
Lloh172:
	ldr	x10, [x10, _RADEON_TV_DAC_NHOLD@GOTPAGEOFF]
	ldr	w12, [x20]
Lloh173:
	ldr	w14, [x10]
Lloh174:
	adrp	x10, _RADEON_TV_DAC_STD_NTSC@GOTPAGE
Lloh175:
	ldr	x10, [x10, _RADEON_TV_DAC_STD_NTSC@GOTPAGEOFF]
Lloh176:
	adrp	x15, _RADEON_TV_DAC_STD_PAL@GOTPAGE
Lloh177:
	ldr	x15, [x15, _RADEON_TV_DAC_STD_PAL@GOTPAGEOFF]
	cmp	w13, #0
	csel	x10, x10, x15, ne
	ldr	w10, [x10]
	orr	w11, w12, w11
	orr	w11, w11, w14
	ldr	w12, [sp, #76]
	cbz	w13, LBB0_17
; %bb.16:
Lloh178:
	adrp	x13, _NTSC_TV_PLL_M_14@GOTPAGE
Lloh179:
	ldr	x13, [x13, _NTSC_TV_PLL_M_14@GOTPAGEOFF]
Lloh180:
	adrp	x14, _NTSC_TV_PLL_M_27@GOTPAGE
Lloh181:
	ldr	x14, [x14, _NTSC_TV_PLL_M_27@GOTPAGEOFF]
	cmp	w12, #2700
	csel	x12, x14, x13, eq
Lloh182:
	adrp	x13, _NTSC_TV_PLL_N_14@GOTPAGE
Lloh183:
	ldr	x13, [x13, _NTSC_TV_PLL_N_14@GOTPAGEOFF]
Lloh184:
	adrp	x14, _NTSC_TV_PLL_N_27@GOTPAGE
Lloh185:
	ldr	x14, [x14, _NTSC_TV_PLL_N_27@GOTPAGEOFF]
	csel	x13, x14, x13, eq
Lloh186:
	adrp	x14, _NTSC_TV_PLL_P_14@GOTPAGE
Lloh187:
	ldr	x14, [x14, _NTSC_TV_PLL_P_14@GOTPAGEOFF]
Lloh188:
	adrp	x15, _NTSC_TV_PLL_P_27@GOTPAGE
Lloh189:
	ldr	x15, [x15, _NTSC_TV_PLL_P_27@GOTPAGEOFF]
	b	LBB0_18
LBB0_17:
Lloh190:
	adrp	x13, _PAL_TV_PLL_M_14@GOTPAGE
Lloh191:
	ldr	x13, [x13, _PAL_TV_PLL_M_14@GOTPAGEOFF]
Lloh192:
	adrp	x14, _PAL_TV_PLL_M_27@GOTPAGE
Lloh193:
	ldr	x14, [x14, _PAL_TV_PLL_M_27@GOTPAGEOFF]
	cmp	w12, #2700
	csel	x12, x14, x13, eq
Lloh194:
	adrp	x13, _PAL_TV_PLL_N_14@GOTPAGE
Lloh195:
	ldr	x13, [x13, _PAL_TV_PLL_N_14@GOTPAGEOFF]
Lloh196:
	adrp	x14, _PAL_TV_PLL_N_27@GOTPAGE
Lloh197:
	ldr	x14, [x14, _PAL_TV_PLL_N_27@GOTPAGEOFF]
	csel	x13, x14, x13, eq
Lloh198:
	adrp	x14, _PAL_TV_PLL_P_14@GOTPAGE
Lloh199:
	ldr	x14, [x14, _PAL_TV_PLL_P_14@GOTPAGEOFF]
Lloh200:
	adrp	x15, _PAL_TV_PLL_P_27@GOTPAGE
Lloh201:
	ldr	x15, [x15, _PAL_TV_PLL_P_27@GOTPAGEOFF]
LBB0_18:
	csel	x14, x15, x14, eq
	ldr	w15, [sp, #32]                  ; 4-byte Folded Reload
	ldr	w16, [sp, #20]                  ; 4-byte Folded Reload
	orr	w25, w16, w15
	ldr	w15, [sp, #28]                  ; 4-byte Folded Reload
	ldr	w16, [sp, #16]                  ; 4-byte Folded Reload
	orr	w15, w16, w15
	str	w15, [sp, #28]                  ; 4-byte Folded Spill
	ldr	w15, [sp, #24]                  ; 4-byte Folded Reload
	ldr	w16, [sp, #12]                  ; 4-byte Folded Reload
	orr	w15, w16, w15
	str	w15, [sp, #8]                   ; 4-byte Folded Spill
	orr	w15, w19, w24
	str	w15, [sp, #24]                  ; 4-byte Folded Spill
	orr	w15, w26, w23
	str	w15, [sp, #16]                  ; 4-byte Folded Spill
	orr	w15, w27, w21, asr #10
	str	w15, [sp, #20]                  ; 4-byte Folded Spill
	orr	w9, w9, #0x10000000
	str	w9, [sp, #12]                   ; 4-byte Folded Spill
	orr	w9, w11, w10
	str	w9, [sp, #32]                   ; 4-byte Folded Spill
	ldr	w9, [x14]
	ldr	w10, [x13]
	ldr	w11, [x12]
Lloh202:
	adrp	x12, _RADEON_TV_M0LO_MASK@GOTPAGE
Lloh203:
	ldr	x12, [x12, _RADEON_TV_M0LO_MASK@GOTPAGEOFF]
Lloh204:
	ldr	w12, [x12]
	and	w12, w12, w11
Lloh205:
	adrp	x13, _RADEON_TV_M0HI_MASK@GOTPAGE
Lloh206:
	ldr	x13, [x13, _RADEON_TV_M0HI_MASK@GOTPAGEOFF]
Lloh207:
	ldr	w13, [x13]
	and	w11, w13, w11, asr #8
Lloh208:
	adrp	x13, _RADEON_TV_M0HI_SHIFT@GOTPAGE
Lloh209:
	ldr	x13, [x13, _RADEON_TV_M0HI_SHIFT@GOTPAGEOFF]
Lloh210:
	ldr	w13, [x13]
	lsl	w11, w11, w13
	orr	w11, w11, w12
Lloh211:
	adrp	x12, _RADEON_TV_N0LO_MASK@GOTPAGE
Lloh212:
	ldr	x12, [x12, _RADEON_TV_N0LO_MASK@GOTPAGEOFF]
Lloh213:
	ldr	w12, [x12]
	and	w12, w12, w10
Lloh214:
	adrp	x13, _RADEON_TV_N0LO_SHIFT@GOTPAGE
Lloh215:
	ldr	x13, [x13, _RADEON_TV_N0LO_SHIFT@GOTPAGEOFF]
Lloh216:
	ldr	w13, [x13]
	lsl	w12, w12, w13
	orr	w11, w11, w12
Lloh217:
	adrp	x12, _RADEON_TV_N0HI_MASK@GOTPAGE
Lloh218:
	ldr	x12, [x12, _RADEON_TV_N0HI_MASK@GOTPAGEOFF]
Lloh219:
	ldr	w12, [x12]
	and	w10, w12, w10, asr #9
Lloh220:
	adrp	x12, _RADEON_TV_N0HI_SHIFT@GOTPAGE
Lloh221:
	ldr	x12, [x12, _RADEON_TV_N0HI_SHIFT@GOTPAGEOFF]
Lloh222:
	ldr	w12, [x12]
	lsl	w10, w10, w12
	orr	w10, w11, w10
Lloh223:
	adrp	x11, _RADEON_TV_P_MASK@GOTPAGE
Lloh224:
	ldr	x11, [x11, _RADEON_TV_P_MASK@GOTPAGEOFF]
Lloh225:
	ldr	w11, [x11]
	and	w9, w11, w9
Lloh226:
	adrp	x11, _RADEON_TV_P_SHIFT@GOTPAGE
Lloh227:
	ldr	x11, [x11, _RADEON_TV_P_SHIFT@GOTPAGEOFF]
Lloh228:
	ldr	w11, [x11]
	lsl	w9, w9, w11
	orr	w27, w10, w9
	mov	w9, #200
	str	w9, [x28, #20]
Lloh229:
	adrp	x9, _vert_timing_NTSC@GOTPAGE
Lloh230:
	ldr	x9, [x9, _vert_timing_NTSC@GOTPAGEOFF]
Lloh231:
	adrp	x10, _vert_timing_PAL@GOTPAGE
Lloh232:
	ldr	x10, [x10, _vert_timing_PAL@GOTPAGEOFF]
	cmp	w8, #0
	csel	x8, x9, x10, ne
Lloh233:
	adrp	x9, _hor_timing_NTSC@GOTPAGE
Lloh234:
	ldr	x9, [x9, _hor_timing_NTSC@GOTPAGEOFF]
Lloh235:
	adrp	x10, _hor_timing_PAL@GOTPAGE
Lloh236:
	ldr	x10, [x10, _hor_timing_PAL@GOTPAGEOFF]
	ldr	x8, [x8]
	csel	x11, x9, x10, ne
Lloh237:
	adrp	x9, _NTSC_TV_VFTOTAL@GOTPAGE
Lloh238:
	ldr	x9, [x9, _NTSC_TV_VFTOTAL@GOTPAGEOFF]
Lloh239:
	adrp	x10, _PAL_TV_VFTOTAL@GOTPAGE
Lloh240:
	ldr	x10, [x10, _PAL_TV_VFTOTAL@GOTPAGEOFF]
	csel	x9, x9, x10, ne
	ldr	w23, [x9]
Lloh241:
	adrp	x9, _MAX_H_CODE_TIMING_LEN@GOTPAGE
Lloh242:
	ldr	x9, [x9, _MAX_H_CODE_TIMING_LEN@GOTPAGEOFF]
	ldr	w10, [x9]
	cmp	w10, #1
	b.lt	LBB0_22
; %bb.19:
	mov	x10, #0
	ldr	x11, [x11]
	ldr	x12, [x28, #24]
LBB0_20:                                ; =>This Inner Loop Header: Depth=1
	lsl	x13, x10, #2
	ldr	w14, [x11, x13]
	str	w14, [x12, x13]
	cbz	w14, LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_20 Depth=1
	add	x10, x10, #1
	ldrsw	x13, [x9]
	cmp	x10, x13
	b.lt	LBB0_20
LBB0_22:
Lloh243:
	adrp	x9, _MAX_V_CODE_TIMING_LEN@GOTPAGE
Lloh244:
	ldr	x9, [x9, _MAX_V_CODE_TIMING_LEN@GOTPAGEOFF]
	ldr	w10, [x9]
	cmp	w10, #1
	b.lt	LBB0_26
; %bb.23:
	mov	x10, #0
	ldr	x11, [x28, #32]
LBB0_24:                                ; =>This Inner Loop Header: Depth=1
	lsl	x12, x10, #2
	ldr	w13, [x8, x12]
	str	w13, [x11, x12]
	cbz	w13, LBB0_26
; %bb.25:                               ;   in Loop: Header=BB0_24 Depth=1
	add	x10, x10, #1
	ldrsw	x12, [x9]
	cmp	x10, x12
	b.lt	LBB0_24
LBB0_26:
	mov	x0, x22
	bl	_radeon_legacy_tv_init_restarts
Lloh245:
	adrp	x21, _RADEON_TV_MASTER_CNTL@GOTPAGE
Lloh246:
	ldr	x21, [x21, _RADEON_TV_MASTER_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
Lloh247:
	adrp	x24, _RADEON_TV_ASYNC_RST@GOTPAGE
Lloh248:
	ldr	x24, [x24, _RADEON_TV_ASYNC_RST@GOTPAGEOFF]
	ldr	w8, [x24]
	orr	w8, w8, w25
Lloh249:
	adrp	x9, _RADEON_CRT_ASYNC_RST@GOTPAGE
Lloh250:
	ldr	x9, [x9, _RADEON_CRT_ASYNC_RST@GOTPAGEOFF]
Lloh251:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh252:
	adrp	x9, _RADEON_TV_FIFO_ASYNC_RST@GOTPAGE
Lloh253:
	ldr	x9, [x9, _RADEON_TV_FIFO_ASYNC_RST@GOTPAGEOFF]
Lloh254:
	ldr	w9, [x9]
	orr	w1, w8, w9
	bl	_WREG32
Lloh255:
	adrp	x8, _RADEON_TV_DAC_CNTL@GOTPAGE
Lloh256:
	ldr	x8, [x8, _RADEON_TV_DAC_CNTL@GOTPAGEOFF]
	ldr	w0, [x8]
	mov	x19, x8
	bl	_RREG32
	ldr	w8, [x20]
	bic	w8, w0, w8
Lloh257:
	adrp	x9, _RADEON_TV_DAC_BGSLEEP@GOTPAGE
Lloh258:
	ldr	x9, [x9, _RADEON_TV_DAC_BGSLEEP@GOTPAGEOFF]
Lloh259:
	ldr	w9, [x9]
Lloh260:
	adrp	x10, _RADEON_TV_DAC_RDACPD@GOTPAGE
Lloh261:
	ldr	x10, [x10, _RADEON_TV_DAC_RDACPD@GOTPAGEOFF]
Lloh262:
	ldr	w10, [x10]
Lloh263:
	adrp	x11, _RADEON_TV_DAC_GDACPD@GOTPAGE
Lloh264:
	ldr	x11, [x11, _RADEON_TV_DAC_GDACPD@GOTPAGEOFF]
Lloh265:
	ldr	w11, [x11]
Lloh266:
	adrp	x12, _RADEON_TV_DAC_BDACPD@GOTPAGE
Lloh267:
	ldr	x12, [x12, _RADEON_TV_DAC_BDACPD@GOTPAGEOFF]
Lloh268:
	ldr	w12, [x12]
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w1, w8, w12
	ldr	w0, [x19]
	bl	_WREG32
Lloh269:
	adrp	x19, _RADEON_TV_PLL_CNTL1@GOTPAGE
Lloh270:
	ldr	x19, [x19, _RADEON_TV_PLL_CNTL1@GOTPAGEOFF]
	ldr	w0, [x19]
Lloh271:
	adrp	x26, _RADEON_TVCLK_SRC_SEL_TVPLL@GOTPAGE
Lloh272:
	ldr	x26, [x26, _RADEON_TVCLK_SRC_SEL_TVPLL@GOTPAGEOFF]
	ldr	w8, [x26]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_PLL_P
Lloh273:
	adrp	x8, _RADEON_TV_PLL_CNTL@GOTPAGE
Lloh274:
	ldr	x8, [x8, _RADEON_TV_PLL_CNTL@GOTPAGEOFF]
Lloh275:
	ldr	w0, [x8]
	mov	x1, x27
	bl	_WREG32_PLL
	ldr	w0, [x19]
Lloh276:
	adrp	x27, _RADEON_TVPLL_RESET@GOTPAGE
Lloh277:
	ldr	x27, [x27, _RADEON_TVPLL_RESET@GOTPAGEOFF]
	ldr	w1, [x27]
	mvn	w2, w1
	bl	_WREG32_PLL_P
	mov	x0, x22
	mov	w1, #200
	mov	w2, #800
	mov	w3, #135
	bl	_radeon_wait_pll_lock
	ldr	w0, [x19]
	ldr	w8, [x27]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_PLL_P
	mov	x0, x22
	mov	w1, #300
	mov	w2, #160
	mov	w3, #27
	bl	_radeon_wait_pll_lock
	mov	x0, x22
	mov	w1, #200
	mov	w2, #800
	mov	w3, #135
	bl	_radeon_wait_pll_lock
	ldr	w0, [x19]
	mov	w1, #0
	mov	w2, #-16
	bl	_WREG32_PLL_P
	ldr	w0, [x19]
	ldr	w1, [x26]
	mvn	w2, w1
	bl	_WREG32_PLL_P
	ldr	w0, [x19]
Lloh278:
	adrp	x8, _RADEON_TVPDC_SHIFT@GOTPAGE
Lloh279:
	ldr	x8, [x8, _RADEON_TVPDC_SHIFT@GOTPAGEOFF]
Lloh280:
	ldr	w8, [x8]
	mov	w9, #1
	lsl	w1, w9, w8
Lloh281:
	adrp	x8, _RADEON_TVPDC_MASK@GOTPAGE
Lloh282:
	ldr	x8, [x8, _RADEON_TVPDC_MASK@GOTPAGEOFF]
Lloh283:
	ldr	w8, [x8]
	mvn	w2, w8
	bl	_WREG32_PLL_P
	ldr	w0, [x19]
Lloh284:
	adrp	x8, _RADEON_TVPLL_SLEEP@GOTPAGE
Lloh285:
	ldr	x8, [x8, _RADEON_TVPLL_SLEEP@GOTPAGEOFF]
Lloh286:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_PLL_P
Lloh287:
	adrp	x8, _RADEON_TV_RGB_CNTL@GOTPAGE
Lloh288:
	ldr	x8, [x8, _RADEON_TV_RGB_CNTL@GOTPAGEOFF]
Lloh289:
	ldr	w0, [x8]
	ldr	w1, [sp, #8]                    ; 4-byte Folded Reload
	bl	_WREG32
Lloh290:
	adrp	x8, _RADEON_TV_HTOTAL@GOTPAGE
Lloh291:
	ldr	x8, [x8, _RADEON_TV_HTOTAL@GOTPAGEOFF]
Lloh292:
	ldr	w0, [x8]
	ldr	x19, [sp, #64]                  ; 8-byte Folded Reload
	ldr	w8, [x19, #8]
	sub	w1, w8, #1
	bl	_WREG32
Lloh293:
	adrp	x8, _RADEON_TV_HDISP@GOTPAGE
Lloh294:
	ldr	x8, [x8, _RADEON_TV_HDISP@GOTPAGEOFF]
Lloh295:
	ldr	w0, [x8]
	ldr	w8, [x19, #4]
	sub	w1, w8, #1
	bl	_WREG32
Lloh296:
	adrp	x8, _RADEON_TV_HSTART@GOTPAGE
Lloh297:
	ldr	x8, [x8, _RADEON_TV_HSTART@GOTPAGEOFF]
Lloh298:
	ldr	w0, [x8]
	ldr	w1, [x19, #12]
	bl	_WREG32
Lloh299:
	adrp	x8, _RADEON_TV_VTOTAL@GOTPAGE
Lloh300:
	ldr	x8, [x8, _RADEON_TV_VTOTAL@GOTPAGEOFF]
Lloh301:
	ldr	w0, [x8]
	ldr	w8, [x19]
	sub	w1, w8, #1
	bl	_WREG32
Lloh302:
	adrp	x8, _RADEON_TV_VDISP@GOTPAGE
Lloh303:
	ldr	x8, [x8, _RADEON_TV_VDISP@GOTPAGEOFF]
Lloh304:
	ldr	w0, [x8]
	ldr	w8, [x19, #16]
	sub	w1, w8, #1
	bl	_WREG32
Lloh305:
	adrp	x8, _RADEON_TV_FTOTAL@GOTPAGE
Lloh306:
	ldr	x8, [x8, _RADEON_TV_FTOTAL@GOTPAGEOFF]
Lloh307:
	ldr	w0, [x8]
	mov	x1, x23
	bl	_WREG32
Lloh308:
	adrp	x8, _RADEON_TV_VSCALER_CNTL1@GOTPAGE
Lloh309:
	ldr	x8, [x8, _RADEON_TV_VSCALER_CNTL1@GOTPAGEOFF]
Lloh310:
	ldr	w0, [x8]
	ldr	w1, [sp, #48]                   ; 4-byte Folded Reload
	bl	_WREG32
Lloh311:
	adrp	x8, _RADEON_TV_VSCALER_CNTL2@GOTPAGE
Lloh312:
	ldr	x8, [x8, _RADEON_TV_VSCALER_CNTL2@GOTPAGEOFF]
Lloh313:
	ldr	w0, [x8]
	ldr	w1, [sp, #12]                   ; 4-byte Folded Reload
	bl	_WREG32
Lloh314:
	adrp	x8, _RADEON_TV_Y_FALL_CNTL@GOTPAGE
Lloh315:
	ldr	x8, [x8, _RADEON_TV_Y_FALL_CNTL@GOTPAGEOFF]
Lloh316:
	ldr	w0, [x8]
	ldr	w1, [sp, #16]                   ; 4-byte Folded Reload
	bl	_WREG32
Lloh317:
	adrp	x8, _RADEON_TV_Y_RISE_CNTL@GOTPAGE
Lloh318:
	ldr	x8, [x8, _RADEON_TV_Y_RISE_CNTL@GOTPAGEOFF]
Lloh319:
	ldr	w0, [x8]
	ldr	w1, [sp, #20]                   ; 4-byte Folded Reload
	bl	_WREG32
Lloh320:
	adrp	x8, _RADEON_TV_Y_SAW_TOOTH_CNTL@GOTPAGE
Lloh321:
	ldr	x8, [x8, _RADEON_TV_Y_SAW_TOOTH_CNTL@GOTPAGEOFF]
Lloh322:
	ldr	w0, [x8]
	ldr	w1, [sp, #24]                   ; 4-byte Folded Reload
	bl	_WREG32
	ldr	w0, [x21]
	ldr	w8, [x24]
	orr	w8, w8, w25
Lloh323:
	adrp	x9, _RADEON_CRT_ASYNC_RST@GOTPAGE
Lloh324:
	ldr	x9, [x9, _RADEON_CRT_ASYNC_RST@GOTPAGEOFF]
Lloh325:
	ldr	w9, [x9]
	orr	w1, w8, w9
	bl	_WREG32
	ldr	x19, [sp, #40]                  ; 8-byte Folded Reload
	mov	x0, x19
	bl	_radeon_legacy_write_tv_restarts
	mov	x0, x19
	bl	_radeon_restore_tv_timing_tables
	ldr	w0, [x21]
	ldr	w8, [x24]
	orr	w1, w8, w25
	bl	_WREG32
Lloh326:
	adrp	x8, _RADEON_TV_SYNC_CNTL@GOTPAGE
Lloh327:
	ldr	x8, [x8, _RADEON_TV_SYNC_CNTL@GOTPAGEOFF]
Lloh328:
	adrp	x9, _RADEON_SYNC_PUB@GOTPAGE
Lloh329:
	ldr	x9, [x9, _RADEON_SYNC_PUB@GOTPAGEOFF]
Lloh330:
	ldr	w0, [x8]
Lloh331:
	ldr	w8, [x9]
Lloh332:
	adrp	x9, _RADEON_TV_SYNC_IO_DRIVE@GOTPAGE
Lloh333:
	ldr	x9, [x9, _RADEON_TV_SYNC_IO_DRIVE@GOTPAGEOFF]
Lloh334:
	ldr	w9, [x9]
	orr	w1, w9, w8
	bl	_WREG32
Lloh335:
	adrp	x8, _RADEON_TV_TIMING_CNTL@GOTPAGE
Lloh336:
	ldr	x8, [x8, _RADEON_TV_TIMING_CNTL@GOTPAGEOFF]
Lloh337:
	ldr	w0, [x8]
	ldr	w1, [x28, #16]
	bl	_WREG32
Lloh338:
	adrp	x8, _RADEON_TV_MODULATOR_CNTL1@GOTPAGE
Lloh339:
	ldr	x8, [x8, _RADEON_TV_MODULATOR_CNTL1@GOTPAGEOFF]
Lloh340:
	ldr	w0, [x8]
	ldr	w1, [sp, #28]                   ; 4-byte Folded Reload
	bl	_WREG32
Lloh341:
	adrp	x8, _RADEON_TV_MODULATOR_CNTL2@GOTPAGE
Lloh342:
	ldr	x8, [x8, _RADEON_TV_MODULATOR_CNTL2@GOTPAGEOFF]
Lloh343:
	ldr	w0, [x8]
	ldr	w1, [sp, #36]                   ; 4-byte Folded Reload
	bl	_WREG32
Lloh344:
	adrp	x8, _RADEON_TV_PRE_DAC_MUX_CNTL@GOTPAGE
Lloh345:
	ldr	x8, [x8, _RADEON_TV_PRE_DAC_MUX_CNTL@GOTPAGEOFF]
Lloh346:
	ldr	w0, [x8]
Lloh347:
	adrp	x8, _RADEON_Y_RED_EN@GOTPAGE
Lloh348:
	ldr	x8, [x8, _RADEON_Y_RED_EN@GOTPAGEOFF]
Lloh349:
	ldr	w8, [x8]
Lloh350:
	adrp	x9, _RADEON_C_GRN_EN@GOTPAGE
Lloh351:
	ldr	x9, [x9, _RADEON_C_GRN_EN@GOTPAGEOFF]
Lloh352:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh353:
	adrp	x9, _RADEON_CMP_BLU_EN@GOTPAGE
Lloh354:
	ldr	x9, [x9, _RADEON_CMP_BLU_EN@GOTPAGEOFF]
Lloh355:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh356:
	adrp	x9, _RADEON_DAC_DITHER_EN@GOTPAGE
Lloh357:
	ldr	x9, [x9, _RADEON_DAC_DITHER_EN@GOTPAGEOFF]
Lloh358:
	ldr	w9, [x9]
	orr	w1, w8, w9
	bl	_WREG32
Lloh359:
	adrp	x8, _RADEON_TV_CRC_CNTL@GOTPAGE
Lloh360:
	ldr	x8, [x8, _RADEON_TV_CRC_CNTL@GOTPAGEOFF]
Lloh361:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x21]
	mov	x1, x25
	bl	_WREG32
Lloh362:
	adrp	x8, _RADEON_TV_GAIN_LIMIT_SETTINGS@GOTPAGE
Lloh363:
	ldr	x8, [x8, _RADEON_TV_GAIN_LIMIT_SETTINGS@GOTPAGEOFF]
Lloh364:
	ldr	w0, [x8]
Lloh365:
	adrp	x8, _RADEON_UV_GAIN_LIMIT_SHIFT@GOTPAGE
Lloh366:
	ldr	x8, [x8, _RADEON_UV_GAIN_LIMIT_SHIFT@GOTPAGEOFF]
Lloh367:
	ldr	w8, [x8]
	mov	w9, #383
	lsl	w8, w9, w8
Lloh368:
	adrp	x9, _RADEON_Y_GAIN_LIMIT_SHIFT@GOTPAGE
Lloh369:
	ldr	x9, [x9, _RADEON_Y_GAIN_LIMIT_SHIFT@GOTPAGEOFF]
Lloh370:
	ldr	w9, [x9]
	mov	w10, #1535
	lsl	w9, w10, w9
	orr	w1, w9, w8
	bl	_WREG32
Lloh371:
	adrp	x8, _RADEON_TV_LINEAR_GAIN_SETTINGS@GOTPAGE
Lloh372:
	ldr	x8, [x8, _RADEON_TV_LINEAR_GAIN_SETTINGS@GOTPAGEOFF]
Lloh373:
	ldr	w0, [x8]
Lloh374:
	adrp	x8, _RADEON_UV_GAIN_SHIFT@GOTPAGE
Lloh375:
	ldr	x8, [x8, _RADEON_UV_GAIN_SHIFT@GOTPAGEOFF]
Lloh376:
	ldr	w8, [x8]
	mov	w9, #256
	lsl	w8, w9, w8
Lloh377:
	adrp	x10, _RADEON_Y_GAIN_SHIFT@GOTPAGE
Lloh378:
	ldr	x10, [x10, _RADEON_Y_GAIN_SHIFT@GOTPAGEOFF]
Lloh379:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w1, w9, w8
	bl	_WREG32
Lloh380:
	adrp	x8, _RADEON_TV_DAC_CNTL@GOTPAGE
Lloh381:
	ldr	x8, [x8, _RADEON_TV_DAC_CNTL@GOTPAGEOFF]
Lloh382:
	ldr	w0, [x8]
	ldr	w1, [sp, #32]                   ; 4-byte Folded Reload
	bl	_WREG32
LBB0_27:
	ldp	x29, x30, [sp, #160]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #144]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #128]            ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #112]            ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #96]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #80]             ; 16-byte Folded Reload
	add	sp, sp, #176
	ret
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGot	Lloh80, Lloh81
	.loh AdrpLdrGot	Lloh87, Lloh88
	.loh AdrpLdrGot	Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGot	Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGot	Lloh99, Lloh100
	.loh AdrpLdrGot	Lloh97, Lloh98
	.loh AdrpLdrGot	Lloh95, Lloh96
	.loh AdrpLdrGot	Lloh93, Lloh94
	.loh AdrpLdrGot	Lloh91, Lloh92
	.loh AdrpLdrGot	Lloh89, Lloh90
	.loh AdrpLdrGot	Lloh176, Lloh177
	.loh AdrpLdrGot	Lloh174, Lloh175
	.loh AdrpLdrGotLdr	Lloh171, Lloh172, Lloh173
	.loh AdrpLdrGot	Lloh169, Lloh170
	.loh AdrpLdrGotLdr	Lloh166, Lloh167, Lloh168
	.loh AdrpLdrGotLdr	Lloh163, Lloh164, Lloh165
	.loh AdrpLdrGotLdr	Lloh160, Lloh161, Lloh162
	.loh AdrpLdrGotLdr	Lloh157, Lloh158, Lloh159
	.loh AdrpLdrGotLdr	Lloh154, Lloh155, Lloh156
	.loh AdrpLdrGotLdr	Lloh151, Lloh152, Lloh153
	.loh AdrpLdrGotLdr	Lloh148, Lloh149, Lloh150
	.loh AdrpLdrGotLdr	Lloh145, Lloh146, Lloh147
	.loh AdrpLdrGotLdr	Lloh142, Lloh143, Lloh144
	.loh AdrpLdrGotLdr	Lloh139, Lloh140, Lloh141
	.loh AdrpLdrGotLdr	Lloh136, Lloh137, Lloh138
	.loh AdrpLdrGotLdr	Lloh133, Lloh134, Lloh135
	.loh AdrpLdrGotLdr	Lloh130, Lloh131, Lloh132
	.loh AdrpLdrGotLdr	Lloh127, Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.loh AdrpLdrGot	Lloh188, Lloh189
	.loh AdrpLdrGot	Lloh186, Lloh187
	.loh AdrpLdrGot	Lloh184, Lloh185
	.loh AdrpLdrGot	Lloh182, Lloh183
	.loh AdrpLdrGot	Lloh180, Lloh181
	.loh AdrpLdrGot	Lloh178, Lloh179
	.loh AdrpLdrGot	Lloh200, Lloh201
	.loh AdrpLdrGot	Lloh198, Lloh199
	.loh AdrpLdrGot	Lloh196, Lloh197
	.loh AdrpLdrGot	Lloh194, Lloh195
	.loh AdrpLdrGot	Lloh192, Lloh193
	.loh AdrpLdrGot	Lloh190, Lloh191
	.loh AdrpLdrGot	Lloh241, Lloh242
	.loh AdrpLdrGot	Lloh239, Lloh240
	.loh AdrpLdrGot	Lloh237, Lloh238
	.loh AdrpLdrGot	Lloh235, Lloh236
	.loh AdrpLdrGot	Lloh233, Lloh234
	.loh AdrpLdrGot	Lloh231, Lloh232
	.loh AdrpLdrGot	Lloh229, Lloh230
	.loh AdrpLdrGotLdr	Lloh226, Lloh227, Lloh228
	.loh AdrpLdrGotLdr	Lloh223, Lloh224, Lloh225
	.loh AdrpLdrGotLdr	Lloh220, Lloh221, Lloh222
	.loh AdrpLdrGotLdr	Lloh217, Lloh218, Lloh219
	.loh AdrpLdrGotLdr	Lloh214, Lloh215, Lloh216
	.loh AdrpLdrGotLdr	Lloh211, Lloh212, Lloh213
	.loh AdrpLdrGotLdr	Lloh208, Lloh209, Lloh210
	.loh AdrpLdrGotLdr	Lloh205, Lloh206, Lloh207
	.loh AdrpLdrGotLdr	Lloh202, Lloh203, Lloh204
	.loh AdrpLdrGot	Lloh243, Lloh244
	.loh AdrpLdrGotLdr	Lloh380, Lloh381, Lloh382
	.loh AdrpLdrGotLdr	Lloh377, Lloh378, Lloh379
	.loh AdrpLdrGotLdr	Lloh374, Lloh375, Lloh376
	.loh AdrpLdrGotLdr	Lloh371, Lloh372, Lloh373
	.loh AdrpLdrGotLdr	Lloh368, Lloh369, Lloh370
	.loh AdrpLdrGotLdr	Lloh365, Lloh366, Lloh367
	.loh AdrpLdrGotLdr	Lloh362, Lloh363, Lloh364
	.loh AdrpLdrGotLdr	Lloh359, Lloh360, Lloh361
	.loh AdrpLdrGotLdr	Lloh356, Lloh357, Lloh358
	.loh AdrpLdrGotLdr	Lloh353, Lloh354, Lloh355
	.loh AdrpLdrGotLdr	Lloh350, Lloh351, Lloh352
	.loh AdrpLdrGotLdr	Lloh347, Lloh348, Lloh349
	.loh AdrpLdrGotLdr	Lloh344, Lloh345, Lloh346
	.loh AdrpLdrGotLdr	Lloh341, Lloh342, Lloh343
	.loh AdrpLdrGotLdr	Lloh338, Lloh339, Lloh340
	.loh AdrpLdrGotLdr	Lloh335, Lloh336, Lloh337
	.loh AdrpLdrGotLdr	Lloh332, Lloh333, Lloh334
	.loh AdrpLdrGotLdr	Lloh328, Lloh329, Lloh331
	.loh AdrpLdrGotLdr	Lloh326, Lloh327, Lloh330
	.loh AdrpLdrGotLdr	Lloh323, Lloh324, Lloh325
	.loh AdrpLdrGotLdr	Lloh320, Lloh321, Lloh322
	.loh AdrpLdrGotLdr	Lloh317, Lloh318, Lloh319
	.loh AdrpLdrGotLdr	Lloh314, Lloh315, Lloh316
	.loh AdrpLdrGotLdr	Lloh311, Lloh312, Lloh313
	.loh AdrpLdrGotLdr	Lloh308, Lloh309, Lloh310
	.loh AdrpLdrGotLdr	Lloh305, Lloh306, Lloh307
	.loh AdrpLdrGotLdr	Lloh302, Lloh303, Lloh304
	.loh AdrpLdrGotLdr	Lloh299, Lloh300, Lloh301
	.loh AdrpLdrGotLdr	Lloh296, Lloh297, Lloh298
	.loh AdrpLdrGotLdr	Lloh293, Lloh294, Lloh295
	.loh AdrpLdrGotLdr	Lloh290, Lloh291, Lloh292
	.loh AdrpLdrGotLdr	Lloh287, Lloh288, Lloh289
	.loh AdrpLdrGotLdr	Lloh284, Lloh285, Lloh286
	.loh AdrpLdrGotLdr	Lloh281, Lloh282, Lloh283
	.loh AdrpLdrGotLdr	Lloh278, Lloh279, Lloh280
	.loh AdrpLdrGot	Lloh276, Lloh277
	.loh AdrpLdrGotLdr	Lloh273, Lloh274, Lloh275
	.loh AdrpLdrGot	Lloh271, Lloh272
	.loh AdrpLdrGot	Lloh269, Lloh270
	.loh AdrpLdrGotLdr	Lloh266, Lloh267, Lloh268
	.loh AdrpLdrGotLdr	Lloh263, Lloh264, Lloh265
	.loh AdrpLdrGotLdr	Lloh260, Lloh261, Lloh262
	.loh AdrpLdrGotLdr	Lloh257, Lloh258, Lloh259
	.loh AdrpLdrGot	Lloh255, Lloh256
	.loh AdrpLdrGotLdr	Lloh252, Lloh253, Lloh254
	.loh AdrpLdrGotLdr	Lloh249, Lloh250, Lloh251
	.loh AdrpLdrGot	Lloh247, Lloh248
	.loh AdrpLdrGot	Lloh245, Lloh246
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_VIN_ASYNC_RST,4,2       ; @RADEON_VIN_ASYNC_RST
	.comm	_RADEON_CRT_FIFO_CE_EN,4,2      ; @RADEON_CRT_FIFO_CE_EN
	.comm	_RADEON_TV_FIFO_CE_EN,4,2       ; @RADEON_TV_FIFO_CE_EN
	.comm	_RADEON_TV_ON,4,2               ; @RADEON_TV_ON
	.comm	_RADEON_TVCLK_ALWAYS_ONb,4,2    ; @RADEON_TVCLK_ALWAYS_ONb
	.comm	_TV_STD_NTSC,8,3                ; @TV_STD_NTSC
	.comm	_TV_STD_NTSC_J,8,3              ; @TV_STD_NTSC_J
	.comm	_RADEON_RESTART_PHASE_FIX,4,2   ; @RADEON_RESTART_PHASE_FIX
	.comm	_RADEON_SLEW_RATE_LIMIT,4,2     ; @RADEON_SLEW_RATE_LIMIT
	.comm	_RADEON_SYNC_TIP_LEVEL,4,2      ; @RADEON_SYNC_TIP_LEVEL
	.comm	_RADEON_YFLT_EN,4,2             ; @RADEON_YFLT_EN
	.comm	_RADEON_UVFLT_EN,4,2            ; @RADEON_UVFLT_EN
	.comm	_RADEON_CY_FILT_BLEND_SHIFT,4,2 ; @RADEON_CY_FILT_BLEND_SHIFT
	.comm	_RADEON_SET_UP_LEVEL_SHIFT,4,2  ; @RADEON_SET_UP_LEVEL_SHIFT
	.comm	_RADEON_BLANK_LEVEL_SHIFT,4,2   ; @RADEON_BLANK_LEVEL_SHIFT
	.comm	_RADEON_TV_U_BURST_LEVEL_MASK,4,2 ; @RADEON_TV_U_BURST_LEVEL_MASK
	.comm	_RADEON_TV_V_BURST_LEVEL_MASK,4,2 ; @RADEON_TV_V_BURST_LEVEL_MASK
	.comm	_RADEON_TV_V_BURST_LEVEL_SHIFT,4,2 ; @RADEON_TV_V_BURST_LEVEL_SHIFT
	.comm	_TV_STD_SCART_PAL,8,3           ; @TV_STD_SCART_PAL
	.comm	_RADEON_ALT_PHASE_EN,4,2        ; @RADEON_ALT_PHASE_EN
	.comm	_RADEON_RGB_DITHER_EN,4,2       ; @RADEON_RGB_DITHER_EN
	.comm	_RADEON_TVOUT_SCALE_EN,4,2      ; @RADEON_TVOUT_SCALE_EN
	.comm	_RADEON_UVRAM_READ_MARGIN_SHIFT,4,2 ; @RADEON_UVRAM_READ_MARGIN_SHIFT
	.comm	_RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT,4,2 ; @RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT
	.comm	_RADEON_RGB_SRC_SEL_CRTC2,4,2   ; @RADEON_RGB_SRC_SEL_CRTC2
	.comm	_RMX_OFF,8,3                    ; @RMX_OFF
	.comm	_RADEON_RGB_SRC_SEL_RMX,4,2     ; @RADEON_RGB_SRC_SEL_RMX
	.comm	_RADEON_RGB_SRC_SEL_CRTC1,4,2   ; @RADEON_RGB_SRC_SEL_CRTC1
	.comm	_TV_STD_PAL_M,8,3               ; @TV_STD_PAL_M
	.comm	_TV_STD_PAL_60,8,3              ; @TV_STD_PAL_60
	.comm	_NTSC_TV_LINES_PER_FRAME,4,2    ; @NTSC_TV_LINES_PER_FRAME
	.comm	_PAL_TV_LINES_PER_FRAME,4,2     ; @PAL_TV_LINES_PER_FRAME
	.comm	_RADEON_TV_VSCALER_CNTL1,4,2    ; @RADEON_TV_VSCALER_CNTL1
	.comm	_FRAC_BITS,4,2                  ; @FRAC_BITS
	.comm	_RADEON_RESTART_FIELD,4,2       ; @RADEON_RESTART_FIELD
	.comm	_RADEON_Y_DEL_W_SIG_SHIFT,4,2   ; @RADEON_Y_DEL_W_SIG_SHIFT
	.comm	_SLOPE_limit,8,3                ; @SLOPE_limit
	.comm	_SLOPE_value,8,3                ; @SLOPE_value
	.comm	_YCOEF_EN_value,8,3             ; @YCOEF_EN_value
	.comm	_YCOEF_value,8,3                ; @YCOEF_value
	.comm	_RADEON_Y_FALL_PING_PONG,4,2    ; @RADEON_Y_FALL_PING_PONG
	.comm	_RADEON_Y_RISE_PING_PONG,4,2    ; @RADEON_Y_RISE_PING_PONG
	.comm	_RADEON_TV_VSCALER_CNTL2,4,2    ; @RADEON_TV_VSCALER_CNTL2
	.comm	_RADEON_DITHER_MODE,4,2         ; @RADEON_DITHER_MODE
	.comm	_RADEON_Y_OUTPUT_DITHER_EN,4,2  ; @RADEON_Y_OUTPUT_DITHER_EN
	.comm	_RADEON_UV_OUTPUT_DITHER_EN,4,2 ; @RADEON_UV_OUTPUT_DITHER_EN
	.comm	_RADEON_UV_TO_BUF_DITHER_EN,4,2 ; @RADEON_UV_TO_BUF_DITHER_EN
	.comm	_RADEON_UV_INC_SHIFT,4,2        ; @RADEON_UV_INC_SHIFT
	.comm	_RADEON_UV_INC_MASK,4,2         ; @RADEON_UV_INC_MASK
	.comm	_RADEON_UV_OUTPUT_POST_SCALE_SHIFT,4,2 ; @RADEON_UV_OUTPUT_POST_SCALE_SHIFT
	.comm	_RADEON_TV_DAC_NBLANK,4,2       ; @RADEON_TV_DAC_NBLANK
	.comm	_RADEON_TV_DAC_NHOLD,4,2        ; @RADEON_TV_DAC_NHOLD
	.comm	_RADEON_TV_DAC_STD_NTSC,4,2     ; @RADEON_TV_DAC_STD_NTSC
	.comm	_RADEON_TV_DAC_STD_PAL,4,2      ; @RADEON_TV_DAC_STD_PAL
	.comm	_NTSC_TV_PLL_M_27,4,2           ; @NTSC_TV_PLL_M_27
	.comm	_NTSC_TV_PLL_N_27,4,2           ; @NTSC_TV_PLL_N_27
	.comm	_NTSC_TV_PLL_P_27,4,2           ; @NTSC_TV_PLL_P_27
	.comm	_NTSC_TV_PLL_M_14,4,2           ; @NTSC_TV_PLL_M_14
	.comm	_NTSC_TV_PLL_N_14,4,2           ; @NTSC_TV_PLL_N_14
	.comm	_NTSC_TV_PLL_P_14,4,2           ; @NTSC_TV_PLL_P_14
	.comm	_PAL_TV_PLL_M_27,4,2            ; @PAL_TV_PLL_M_27
	.comm	_PAL_TV_PLL_N_27,4,2            ; @PAL_TV_PLL_N_27
	.comm	_PAL_TV_PLL_P_27,4,2            ; @PAL_TV_PLL_P_27
	.comm	_PAL_TV_PLL_M_14,4,2            ; @PAL_TV_PLL_M_14
	.comm	_PAL_TV_PLL_N_14,4,2            ; @PAL_TV_PLL_N_14
	.comm	_PAL_TV_PLL_P_14,4,2            ; @PAL_TV_PLL_P_14
	.comm	_RADEON_TV_M0LO_MASK,4,2        ; @RADEON_TV_M0LO_MASK
	.comm	_RADEON_TV_M0HI_MASK,4,2        ; @RADEON_TV_M0HI_MASK
	.comm	_RADEON_TV_M0HI_SHIFT,4,2       ; @RADEON_TV_M0HI_SHIFT
	.comm	_RADEON_TV_N0LO_MASK,4,2        ; @RADEON_TV_N0LO_MASK
	.comm	_RADEON_TV_N0LO_SHIFT,4,2       ; @RADEON_TV_N0LO_SHIFT
	.comm	_RADEON_TV_N0HI_MASK,4,2        ; @RADEON_TV_N0HI_MASK
	.comm	_RADEON_TV_N0HI_SHIFT,4,2       ; @RADEON_TV_N0HI_SHIFT
	.comm	_RADEON_TV_P_MASK,4,2           ; @RADEON_TV_P_MASK
	.comm	_RADEON_TV_P_SHIFT,4,2          ; @RADEON_TV_P_SHIFT
	.comm	_RADEON_TVPCP_MASK,4,2          ; @RADEON_TVPCP_MASK
	.comm	_RADEON_TVPCP_SHIFT,4,2         ; @RADEON_TVPCP_SHIFT
	.comm	_RADEON_TVPVG_MASK,4,2          ; @RADEON_TVPVG_MASK
	.comm	_RADEON_TVPVG_SHIFT,4,2         ; @RADEON_TVPVG_SHIFT
	.comm	_RADEON_TVPDC_MASK,4,2          ; @RADEON_TVPDC_MASK
	.comm	_RADEON_TVPDC_SHIFT,4,2         ; @RADEON_TVPDC_SHIFT
	.comm	_RADEON_TVCLK_SRC_SEL_TVPLL,4,2 ; @RADEON_TVCLK_SRC_SEL_TVPLL
	.comm	_RADEON_TVPLL_TEST_DIS,4,2      ; @RADEON_TVPLL_TEST_DIS
	.comm	_NTSC_TV_VFTOTAL,4,2            ; @NTSC_TV_VFTOTAL
	.comm	_hor_timing_NTSC,8,3            ; @hor_timing_NTSC
	.comm	_vert_timing_NTSC,8,3           ; @vert_timing_NTSC
	.comm	_hor_timing_PAL,8,3             ; @hor_timing_PAL
	.comm	_vert_timing_PAL,8,3            ; @vert_timing_PAL
	.comm	_PAL_TV_VFTOTAL,4,2             ; @PAL_TV_VFTOTAL
	.comm	_MAX_H_CODE_TIMING_LEN,4,2      ; @MAX_H_CODE_TIMING_LEN
	.comm	_MAX_V_CODE_TIMING_LEN,4,2      ; @MAX_V_CODE_TIMING_LEN
	.comm	_RADEON_TV_MASTER_CNTL,4,2      ; @RADEON_TV_MASTER_CNTL
	.comm	_RADEON_TV_ASYNC_RST,4,2        ; @RADEON_TV_ASYNC_RST
	.comm	_RADEON_CRT_ASYNC_RST,4,2       ; @RADEON_CRT_ASYNC_RST
	.comm	_RADEON_TV_FIFO_ASYNC_RST,4,2   ; @RADEON_TV_FIFO_ASYNC_RST
	.comm	_RADEON_TV_DAC_CNTL,4,2         ; @RADEON_TV_DAC_CNTL
	.comm	_RADEON_TV_DAC_BGSLEEP,4,2      ; @RADEON_TV_DAC_BGSLEEP
	.comm	_RADEON_TV_DAC_RDACPD,4,2       ; @RADEON_TV_DAC_RDACPD
	.comm	_RADEON_TV_DAC_GDACPD,4,2       ; @RADEON_TV_DAC_GDACPD
	.comm	_RADEON_TV_DAC_BDACPD,4,2       ; @RADEON_TV_DAC_BDACPD
	.comm	_RADEON_TV_PLL_CNTL1,4,2        ; @RADEON_TV_PLL_CNTL1
	.comm	_RADEON_TV_PLL_CNTL,4,2         ; @RADEON_TV_PLL_CNTL
	.comm	_RADEON_TVPLL_RESET,4,2         ; @RADEON_TVPLL_RESET
	.comm	_RADEON_TVPLL_SLEEP,4,2         ; @RADEON_TVPLL_SLEEP
	.comm	_RADEON_TV_RGB_CNTL,4,2         ; @RADEON_TV_RGB_CNTL
	.comm	_RADEON_TV_HTOTAL,4,2           ; @RADEON_TV_HTOTAL
	.comm	_RADEON_TV_HDISP,4,2            ; @RADEON_TV_HDISP
	.comm	_RADEON_TV_HSTART,4,2           ; @RADEON_TV_HSTART
	.comm	_RADEON_TV_VTOTAL,4,2           ; @RADEON_TV_VTOTAL
	.comm	_RADEON_TV_VDISP,4,2            ; @RADEON_TV_VDISP
	.comm	_RADEON_TV_FTOTAL,4,2           ; @RADEON_TV_FTOTAL
	.comm	_RADEON_TV_Y_FALL_CNTL,4,2      ; @RADEON_TV_Y_FALL_CNTL
	.comm	_RADEON_TV_Y_RISE_CNTL,4,2      ; @RADEON_TV_Y_RISE_CNTL
	.comm	_RADEON_TV_Y_SAW_TOOTH_CNTL,4,2 ; @RADEON_TV_Y_SAW_TOOTH_CNTL
	.comm	_RADEON_TV_SYNC_CNTL,4,2        ; @RADEON_TV_SYNC_CNTL
	.comm	_RADEON_SYNC_PUB,4,2            ; @RADEON_SYNC_PUB
	.comm	_RADEON_TV_SYNC_IO_DRIVE,4,2    ; @RADEON_TV_SYNC_IO_DRIVE
	.comm	_RADEON_TV_TIMING_CNTL,4,2      ; @RADEON_TV_TIMING_CNTL
	.comm	_RADEON_TV_MODULATOR_CNTL1,4,2  ; @RADEON_TV_MODULATOR_CNTL1
	.comm	_RADEON_TV_MODULATOR_CNTL2,4,2  ; @RADEON_TV_MODULATOR_CNTL2
	.comm	_RADEON_TV_PRE_DAC_MUX_CNTL,4,2 ; @RADEON_TV_PRE_DAC_MUX_CNTL
	.comm	_RADEON_Y_RED_EN,4,2            ; @RADEON_Y_RED_EN
	.comm	_RADEON_C_GRN_EN,4,2            ; @RADEON_C_GRN_EN
	.comm	_RADEON_CMP_BLU_EN,4,2          ; @RADEON_CMP_BLU_EN
	.comm	_RADEON_DAC_DITHER_EN,4,2       ; @RADEON_DAC_DITHER_EN
	.comm	_RADEON_TV_CRC_CNTL,4,2         ; @RADEON_TV_CRC_CNTL
	.comm	_RADEON_TV_GAIN_LIMIT_SETTINGS,4,2 ; @RADEON_TV_GAIN_LIMIT_SETTINGS
	.comm	_RADEON_UV_GAIN_LIMIT_SHIFT,4,2 ; @RADEON_UV_GAIN_LIMIT_SHIFT
	.comm	_RADEON_Y_GAIN_LIMIT_SHIFT,4,2  ; @RADEON_Y_GAIN_LIMIT_SHIFT
	.comm	_RADEON_TV_LINEAR_GAIN_SETTINGS,4,2 ; @RADEON_TV_LINEAR_GAIN_SETTINGS
	.comm	_RADEON_UV_GAIN_SHIFT,4,2       ; @RADEON_UV_GAIN_SHIFT
	.comm	_RADEON_Y_GAIN_SHIFT,4,2        ; @RADEON_Y_GAIN_SHIFT
.subsections_via_symbols
