	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function avivo_read_disabled_bios
_avivo_read_disabled_bios:              ## @avivo_read_disabled_bios
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, -80(%rbp)                 ## 8-byte Spill
	movq	_RADEON_SEPROM_CNTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r12d
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_RADEON_VIPH_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r13d
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	_RV370_BUS_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %ebx
	movq	_AVIVO_D1VGA_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movq	_AVIVO_D2VGA_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	movq	_AVIVO_VGA_RENDER_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -60(%rbp)                 ## 4-byte Spill
	movq	_RADEON_GPIOPAD_A@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	%rax, %r15
	callq	_RREG32
	movl	%eax, -72(%rbp)                 ## 4-byte Spill
	movq	_RADEON_GPIOPAD_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -68(%rbp)                 ## 4-byte Spill
	movq	_RADEON_GPIOPAD_MASK@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32
	movl	%eax, -64(%rbp)                 ## 4-byte Spill
	movq	_RADEON_SEPROM_CNTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_SCK_PRESCALE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%r12d, %eax
	movq	_RADEON_SCK_PRESCALE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$12, %esi
	shll	%cl, %esi
	orl	%eax, %esi
	callq	_WREG32
	movl	(%r15), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_RADEON_GPIOPAD_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r14), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_RADEON_VIPH_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_VIPH_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	%r13d, %esi
	callq	_WREG32
	movq	_RV370_BUS_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RV370_BUS_BIOS_DIS_ROM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	%ebx, %esi
	movl	%ebx, %r15d
	callq	_WREG32
	movq	_AVIVO_D1VGA_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_AVIVO_DVGA_CONTROL_MODE_ENABLE@GOTPCREL(%rip), %r12
	movq	_AVIVO_DVGA_CONTROL_TIMING_SELECT@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	orl	(%r12), %esi
	notl	%esi
	movl	-52(%rbp), %r14d                ## 4-byte Reload
	andl	%r14d, %esi
	callq	_WREG32
	movq	_AVIVO_D2VGA_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%rbx), %esi
	orl	(%r12), %esi
	notl	%esi
	movl	-56(%rbp), %ebx                 ## 4-byte Reload
	andl	%ebx, %esi
	callq	_WREG32
	movq	_AVIVO_VGA_RENDER_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_AVIVO_VGA_VSTATUS_CNTL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	movl	-60(%rbp), %r13d                ## 4-byte Reload
	andl	%r13d, %esi
	callq	_WREG32
	movq	-80(%rbp), %rdi                 ## 8-byte Reload
	callq	_radeon_read_bios
	movl	%eax, %r12d
	movq	_RADEON_SEPROM_CNTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-48(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_VIPH_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RV370_BUS_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movq	_AVIVO_D1VGA_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_AVIVO_D2VGA_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_AVIVO_VGA_RENDER_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r13d, %esi
	callq	_WREG32
	movq	_RADEON_GPIOPAD_A@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-72(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_GPIOPAD_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-68(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_GPIOPAD_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-64(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movl	%r12d, %eax
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_SEPROM_CNTL1,4,2        ## @RADEON_SEPROM_CNTL1
	.comm	_RADEON_VIPH_CONTROL,4,2        ## @RADEON_VIPH_CONTROL
	.comm	_RV370_BUS_CNTL,4,2             ## @RV370_BUS_CNTL
	.comm	_AVIVO_D1VGA_CONTROL,4,2        ## @AVIVO_D1VGA_CONTROL
	.comm	_AVIVO_D2VGA_CONTROL,4,2        ## @AVIVO_D2VGA_CONTROL
	.comm	_AVIVO_VGA_RENDER_CONTROL,4,2   ## @AVIVO_VGA_RENDER_CONTROL
	.comm	_RADEON_GPIOPAD_A,4,2           ## @RADEON_GPIOPAD_A
	.comm	_RADEON_GPIOPAD_EN,4,2          ## @RADEON_GPIOPAD_EN
	.comm	_RADEON_GPIOPAD_MASK,4,2        ## @RADEON_GPIOPAD_MASK
	.comm	_RADEON_SCK_PRESCALE_MASK,4,2   ## @RADEON_SCK_PRESCALE_MASK
	.comm	_RADEON_SCK_PRESCALE_SHIFT,4,2  ## @RADEON_SCK_PRESCALE_SHIFT
	.comm	_RADEON_VIPH_EN,4,2             ## @RADEON_VIPH_EN
	.comm	_RV370_BUS_BIOS_DIS_ROM,4,2     ## @RV370_BUS_BIOS_DIS_ROM
	.comm	_AVIVO_DVGA_CONTROL_MODE_ENABLE,4,2 ## @AVIVO_DVGA_CONTROL_MODE_ENABLE
	.comm	_AVIVO_DVGA_CONTROL_TIMING_SELECT,4,2 ## @AVIVO_DVGA_CONTROL_TIMING_SELECT
	.comm	_AVIVO_VGA_VSTATUS_CNTL_MASK,4,2 ## @AVIVO_VGA_VSTATUS_CNTL_MASK
	.no_dead_strip	_avivo_read_disabled_bios
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function avivo_read_disabled_bios
_avivo_read_disabled_bios:              ; @avivo_read_disabled_bios
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #128
	.cfi_def_cfa_offset 128
	stp	x28, x27, [sp, #32]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #48]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #64]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #80]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #96]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #112]            ; 16-byte Folded Spill
	add	x29, sp, #112
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	str	x0, [sp, #24]                   ; 8-byte Folded Spill
Lloh0:
	adrp	x8, _RADEON_SEPROM_CNTL1@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_SEPROM_CNTL1@GOTPAGEOFF]
	ldr	w0, [x8]
	mov	x19, x8
	bl	_RREG32
	mov	x20, x0
Lloh2:
	adrp	x8, _RADEON_VIPH_CONTROL@GOTPAGE
Lloh3:
	ldr	x8, [x8, _RADEON_VIPH_CONTROL@GOTPAGEOFF]
Lloh4:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x21, x0
Lloh5:
	adrp	x8, _RV370_BUS_CNTL@GOTPAGE
Lloh6:
	ldr	x8, [x8, _RV370_BUS_CNTL@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x22, x0
Lloh8:
	adrp	x8, _AVIVO_D1VGA_CONTROL@GOTPAGE
Lloh9:
	ldr	x8, [x8, _AVIVO_D1VGA_CONTROL@GOTPAGEOFF]
Lloh10:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x23, x0
Lloh11:
	adrp	x8, _AVIVO_D2VGA_CONTROL@GOTPAGE
Lloh12:
	ldr	x8, [x8, _AVIVO_D2VGA_CONTROL@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x24, x0
Lloh14:
	adrp	x8, _AVIVO_VGA_RENDER_CONTROL@GOTPAGE
Lloh15:
	ldr	x8, [x8, _AVIVO_VGA_RENDER_CONTROL@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x25, x0
Lloh17:
	adrp	x28, _RADEON_GPIOPAD_A@GOTPAGE
Lloh18:
	ldr	x28, [x28, _RADEON_GPIOPAD_A@GOTPAGEOFF]
	ldr	w0, [x28]
	bl	_RREG32
	str	w0, [sp, #20]                   ; 4-byte Folded Spill
Lloh19:
	adrp	x27, _RADEON_GPIOPAD_EN@GOTPAGE
Lloh20:
	ldr	x27, [x27, _RADEON_GPIOPAD_EN@GOTPAGEOFF]
	ldr	w0, [x27]
	bl	_RREG32
	str	w0, [sp, #16]                   ; 4-byte Folded Spill
Lloh21:
	adrp	x26, _RADEON_GPIOPAD_MASK@GOTPAGE
Lloh22:
	ldr	x26, [x26, _RADEON_GPIOPAD_MASK@GOTPAGEOFF]
	ldr	w0, [x26]
	bl	_RREG32
	str	w0, [sp, #12]                   ; 4-byte Folded Spill
	ldr	w0, [x19]
Lloh23:
	adrp	x8, _RADEON_SCK_PRESCALE_MASK@GOTPAGE
Lloh24:
	ldr	x8, [x8, _RADEON_SCK_PRESCALE_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
	bic	w8, w20, w8
Lloh26:
	adrp	x9, _RADEON_SCK_PRESCALE_SHIFT@GOTPAGE
Lloh27:
	ldr	x9, [x9, _RADEON_SCK_PRESCALE_SHIFT@GOTPAGEOFF]
Lloh28:
	ldr	w9, [x9]
	mov	w10, #12
	lsl	w9, w10, w9
	orr	w1, w9, w8
	bl	_WREG32
	ldr	w0, [x28]
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x27]
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x26]
	mov	x28, x26
	mov	w1, #0
	bl	_WREG32
Lloh29:
	adrp	x8, _RADEON_VIPH_CONTROL@GOTPAGE
Lloh30:
	ldr	x8, [x8, _RADEON_VIPH_CONTROL@GOTPAGEOFF]
Lloh31:
	ldr	w0, [x8]
Lloh32:
	adrp	x8, _RADEON_VIPH_EN@GOTPAGE
Lloh33:
	ldr	x8, [x8, _RADEON_VIPH_EN@GOTPAGEOFF]
Lloh34:
	ldr	w8, [x8]
	bic	w1, w21, w8
	bl	_WREG32
Lloh35:
	adrp	x8, _RV370_BUS_CNTL@GOTPAGE
Lloh36:
	ldr	x8, [x8, _RV370_BUS_CNTL@GOTPAGEOFF]
Lloh37:
	ldr	w0, [x8]
Lloh38:
	adrp	x8, _RV370_BUS_BIOS_DIS_ROM@GOTPAGE
Lloh39:
	ldr	x8, [x8, _RV370_BUS_BIOS_DIS_ROM@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
	bic	w1, w22, w8
	bl	_WREG32
Lloh41:
	adrp	x8, _AVIVO_D1VGA_CONTROL@GOTPAGE
Lloh42:
	ldr	x8, [x8, _AVIVO_D1VGA_CONTROL@GOTPAGEOFF]
Lloh43:
	ldr	w0, [x8]
Lloh44:
	adrp	x19, _AVIVO_DVGA_CONTROL_MODE_ENABLE@GOTPAGE
Lloh45:
	ldr	x19, [x19, _AVIVO_DVGA_CONTROL_MODE_ENABLE@GOTPAGEOFF]
	ldr	w8, [x19]
Lloh46:
	adrp	x26, _AVIVO_DVGA_CONTROL_TIMING_SELECT@GOTPAGE
Lloh47:
	ldr	x26, [x26, _AVIVO_DVGA_CONTROL_TIMING_SELECT@GOTPAGEOFF]
	ldr	w9, [x26]
	orr	w8, w9, w8
	bic	w1, w23, w8
	bl	_WREG32
Lloh48:
	adrp	x8, _AVIVO_D2VGA_CONTROL@GOTPAGE
Lloh49:
	ldr	x8, [x8, _AVIVO_D2VGA_CONTROL@GOTPAGEOFF]
Lloh50:
	ldr	w0, [x8]
	ldr	w8, [x19]
	ldr	w9, [x26]
	orr	w8, w9, w8
	bic	w1, w24, w8
	bl	_WREG32
Lloh51:
	adrp	x26, _AVIVO_VGA_RENDER_CONTROL@GOTPAGE
Lloh52:
	ldr	x26, [x26, _AVIVO_VGA_RENDER_CONTROL@GOTPAGEOFF]
	ldr	w0, [x26]
Lloh53:
	adrp	x8, _AVIVO_VGA_VSTATUS_CNTL_MASK@GOTPAGE
Lloh54:
	ldr	x8, [x8, _AVIVO_VGA_VSTATUS_CNTL_MASK@GOTPAGEOFF]
Lloh55:
	ldr	w8, [x8]
	bic	w1, w25, w8
	bl	_WREG32
	ldr	x0, [sp, #24]                   ; 8-byte Folded Reload
	bl	_radeon_read_bios
	mov	x19, x0
Lloh56:
	adrp	x8, _RADEON_SEPROM_CNTL1@GOTPAGE
Lloh57:
	ldr	x8, [x8, _RADEON_SEPROM_CNTL1@GOTPAGEOFF]
Lloh58:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh59:
	adrp	x8, _RADEON_VIPH_CONTROL@GOTPAGE
Lloh60:
	ldr	x8, [x8, _RADEON_VIPH_CONTROL@GOTPAGEOFF]
Lloh61:
	ldr	w0, [x8]
	mov	x1, x21
	bl	_WREG32
Lloh62:
	adrp	x8, _RV370_BUS_CNTL@GOTPAGE
Lloh63:
	ldr	x8, [x8, _RV370_BUS_CNTL@GOTPAGEOFF]
Lloh64:
	ldr	w0, [x8]
	mov	x1, x22
	bl	_WREG32
Lloh65:
	adrp	x8, _AVIVO_D1VGA_CONTROL@GOTPAGE
Lloh66:
	ldr	x8, [x8, _AVIVO_D1VGA_CONTROL@GOTPAGEOFF]
Lloh67:
	ldr	w0, [x8]
	mov	x1, x23
	bl	_WREG32
Lloh68:
	adrp	x8, _AVIVO_D2VGA_CONTROL@GOTPAGE
Lloh69:
	ldr	x8, [x8, _AVIVO_D2VGA_CONTROL@GOTPAGEOFF]
Lloh70:
	ldr	w0, [x8]
	mov	x1, x24
	bl	_WREG32
	ldr	w0, [x26]
	mov	x1, x25
	bl	_WREG32
Lloh71:
	adrp	x8, _RADEON_GPIOPAD_A@GOTPAGE
Lloh72:
	ldr	x8, [x8, _RADEON_GPIOPAD_A@GOTPAGEOFF]
Lloh73:
	ldr	w0, [x8]
	ldr	w1, [sp, #20]                   ; 4-byte Folded Reload
	bl	_WREG32
	ldr	w0, [x27]
	ldr	w1, [sp, #16]                   ; 4-byte Folded Reload
	bl	_WREG32
	ldr	w0, [x28]
	ldr	w1, [sp, #12]                   ; 4-byte Folded Reload
	bl	_WREG32
	mov	x0, x19
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	ret
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGot	Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_SEPROM_CNTL1,4,2        ; @RADEON_SEPROM_CNTL1
	.comm	_RADEON_VIPH_CONTROL,4,2        ; @RADEON_VIPH_CONTROL
	.comm	_RV370_BUS_CNTL,4,2             ; @RV370_BUS_CNTL
	.comm	_AVIVO_D1VGA_CONTROL,4,2        ; @AVIVO_D1VGA_CONTROL
	.comm	_AVIVO_D2VGA_CONTROL,4,2        ; @AVIVO_D2VGA_CONTROL
	.comm	_AVIVO_VGA_RENDER_CONTROL,4,2   ; @AVIVO_VGA_RENDER_CONTROL
	.comm	_RADEON_GPIOPAD_A,4,2           ; @RADEON_GPIOPAD_A
	.comm	_RADEON_GPIOPAD_EN,4,2          ; @RADEON_GPIOPAD_EN
	.comm	_RADEON_GPIOPAD_MASK,4,2        ; @RADEON_GPIOPAD_MASK
	.comm	_RADEON_SCK_PRESCALE_MASK,4,2   ; @RADEON_SCK_PRESCALE_MASK
	.comm	_RADEON_SCK_PRESCALE_SHIFT,4,2  ; @RADEON_SCK_PRESCALE_SHIFT
	.comm	_RADEON_VIPH_EN,4,2             ; @RADEON_VIPH_EN
	.comm	_RV370_BUS_BIOS_DIS_ROM,4,2     ; @RV370_BUS_BIOS_DIS_ROM
	.comm	_AVIVO_DVGA_CONTROL_MODE_ENABLE,4,2 ; @AVIVO_DVGA_CONTROL_MODE_ENABLE
	.comm	_AVIVO_DVGA_CONTROL_TIMING_SELECT,4,2 ; @AVIVO_DVGA_CONTROL_TIMING_SELECT
	.comm	_AVIVO_VGA_VSTATUS_CNTL_MASK,4,2 ; @AVIVO_VGA_VSTATUS_CNTL_MASK
	.no_dead_strip	_avivo_read_disabled_bios
.subsections_via_symbols
