	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r600_dma_resume                ## -- Begin function r600_dma_resume
	.p2align	4, 0x90
_r600_dma_resume:                       ## @r600_dma_resume
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rdx
	movq	(%rdi), %rax
	movq	32(%rdi), %r13
	movq	_R600_RING_TYPE_DMA_INDEX@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	leaq	(%rcx,%rcx,4), %r14
	movq	_CHIP_RV770@GOTPCREL(%rip), %rcx
	movq	_SRBM_SOFT_RESET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	cmpq	(%rcx), %rax
	movq	%rdx, -56(%rbp)                 ## 8-byte Spill
	jge	LBB0_1
## %bb.2:
	movq	_SOFT_RESET_DMA@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_1:
	movq	_RV770_SOFT_RESET_DMA@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %esi
	callq	_WREG32
	movl	(%rbx), %edi
	callq	_RREG32
	movl	$50, %edi
	callq	_udelay
	movl	(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_DMA_SEM_INCOMPLETE_TIMER_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_DMA_SEM_WAIT_FAIL_TIMER_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r13,%r14,4), %eax
	leal	3(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$2, %edi
	callq	_drm_order
	movl	%eax, %ebx
	addl	%eax, %ebx
	movq	_DMA_RB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_DMA_RB_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_DMA_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_DMA_RB_RPTR_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_R600_WB_DMA_RPTR_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	-56(%rbp), %r12                 ## 8-byte Reload
	addl	16(%r12), %edi
	callq	_upper_32_bits
	movzbl	%al, %esi
	movl	%r15d, %edi
	callq	_WREG32
	movq	_DMA_RB_RPTR_ADDR_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_R600_WB_DMA_RPTR_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	16(%r12), %esi
	andl	$-4, %esi
	callq	_WREG32
	xorl	%r15d, %r15d
	cmpq	$0, 24(%r12)
	je	LBB0_5
## %bb.4:
	movq	_DMA_RPTR_WRITEBACK_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
LBB0_5:
	leaq	(,%r14,4), %rax
	addq	%r13, %rax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	orl	%ebx, %r15d
	movq	_DMA_RB_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	4(%r13,%r14,4), %esi
	sarl	$8, %esi
	callq	_WREG32
	movq	_DMA_IB_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DMA_IB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32
	movq	_DMA_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_CTXEMPTY_INT_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32
	movq	(%r12), %rax
	movq	_CHIP_RV770@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_7
## %bb.6:
	movq	_DMA_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_WREG32
LBB0_7:
	movl	$0, 8(%r13,%r14,4)
	movq	_DMA_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_DMA_RB_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	sarl	$2, %eax
	movl	%eax, 12(%r13,%r14,4)
	movq	_DMA_RB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_DMA_RB_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %r15d
	movl	%r15d, %esi
	callq	_WREG32
	movl	$1, 16(%r13,%r14,4)
	movq	_R600_RING_TYPE_DMA_INDEX@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r12, %rdi
	movq	-48(%rbp), %rdx                 ## 8-byte Reload
	callq	_radeon_ring_test
	movl	%eax, %ebx
	testl	%eax, %eax
	je	LBB0_9
## %bb.8:
	leaq	16(,%r14,4), %rax
	addq	%r13, %rax
	movl	$0, (%rax)
	jmp	LBB0_10
LBB0_9:
	movl	8(%r12), %esi
	movq	%r12, %rdi
	callq	_radeon_ttm_set_active_vram_size
LBB0_10:
	movl	%ebx, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_R600_RING_TYPE_DMA_INDEX,8,3   ## @R600_RING_TYPE_DMA_INDEX
	.comm	_CHIP_RV770,8,3                 ## @CHIP_RV770
	.comm	_SRBM_SOFT_RESET,4,2            ## @SRBM_SOFT_RESET
	.comm	_RV770_SOFT_RESET_DMA,4,2       ## @RV770_SOFT_RESET_DMA
	.comm	_SOFT_RESET_DMA,4,2             ## @SOFT_RESET_DMA
	.comm	_DMA_SEM_INCOMPLETE_TIMER_CNTL,4,2 ## @DMA_SEM_INCOMPLETE_TIMER_CNTL
	.comm	_DMA_SEM_WAIT_FAIL_TIMER_CNTL,4,2 ## @DMA_SEM_WAIT_FAIL_TIMER_CNTL
	.comm	_DMA_RB_CNTL,4,2                ## @DMA_RB_CNTL
	.comm	_DMA_RB_RPTR,4,2                ## @DMA_RB_RPTR
	.comm	_DMA_RB_WPTR,4,2                ## @DMA_RB_WPTR
	.comm	_DMA_RB_RPTR_ADDR_HI,4,2        ## @DMA_RB_RPTR_ADDR_HI
	.comm	_R600_WB_DMA_RPTR_OFFSET,4,2    ## @R600_WB_DMA_RPTR_OFFSET
	.comm	_DMA_RB_RPTR_ADDR_LO,4,2        ## @DMA_RB_RPTR_ADDR_LO
	.comm	_DMA_RPTR_WRITEBACK_ENABLE,4,2  ## @DMA_RPTR_WRITEBACK_ENABLE
	.comm	_DMA_RB_BASE,4,2                ## @DMA_RB_BASE
	.comm	_DMA_IB_ENABLE,4,2              ## @DMA_IB_ENABLE
	.comm	_DMA_IB_CNTL,4,2                ## @DMA_IB_CNTL
	.comm	_DMA_CNTL,4,2                   ## @DMA_CNTL
	.comm	_CTXEMPTY_INT_ENABLE,4,2        ## @CTXEMPTY_INT_ENABLE
	.comm	_DMA_MODE,4,2                   ## @DMA_MODE
	.comm	_DMA_RB_ENABLE,4,2              ## @DMA_RB_ENABLE
	.comm	_DMA_IB_SWAP_ENABLE,4,2         ## @DMA_IB_SWAP_ENABLE
	.comm	_DMA_RB_SWAP_ENABLE,4,2         ## @DMA_RB_SWAP_ENABLE
	.comm	_DMA_RPTR_WRITEBACK_SWAP_ENABLE,4,2 ## @DMA_RPTR_WRITEBACK_SWAP_ENABLE
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r600_dma_resume                ; -- Begin function r600_dma_resume
	.p2align	2
_r600_dma_resume:                       ; @r600_dma_resume
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
Lloh0:
	adrp	x8, _R600_RING_TYPE_DMA_INDEX@GOTPAGE
Lloh1:
	ldr	x8, [x8, _R600_RING_TYPE_DMA_INDEX@GOTPAGEOFF]
	ldr	x24, [x0, #32]
Lloh2:
	ldr	x25, [x8]
	mov	w8, #20
	madd	x20, x25, x8, x24
Lloh3:
	adrp	x9, _CHIP_RV770@GOTPAGE
Lloh4:
	ldr	x9, [x9, _CHIP_RV770@GOTPAGEOFF]
	ldr	x8, [x0]
Lloh5:
	ldr	x9, [x9]
Lloh6:
	adrp	x21, _SRBM_SOFT_RESET@GOTPAGE
Lloh7:
	ldr	x21, [x21, _SRBM_SOFT_RESET@GOTPAGEOFF]
Lloh8:
	adrp	x10, _SOFT_RESET_DMA@GOTPAGE
Lloh9:
	ldr	x10, [x10, _SOFT_RESET_DMA@GOTPAGEOFF]
	ldr	w0, [x21]
Lloh10:
	adrp	x11, _RV770_SOFT_RESET_DMA@GOTPAGE
Lloh11:
	ldr	x11, [x11, _RV770_SOFT_RESET_DMA@GOTPAGEOFF]
	cmp	x8, x9
	csel	x8, x10, x11, lt
	ldr	w1, [x8]
	bl	_WREG32
	ldr	w0, [x21]
	bl	_RREG32
	mov	w0, #50
	bl	_udelay
	ldr	w0, [x21]
	mov	w1, #0
	bl	_WREG32
Lloh12:
	adrp	x8, _DMA_SEM_INCOMPLETE_TIMER_CNTL@GOTPAGE
Lloh13:
	ldr	x8, [x8, _DMA_SEM_INCOMPLETE_TIMER_CNTL@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh15:
	adrp	x8, _DMA_SEM_WAIT_FAIL_TIMER_CNTL@GOTPAGE
Lloh16:
	ldr	x8, [x8, _DMA_SEM_WAIT_FAIL_TIMER_CNTL@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	ldr	w8, [x20]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #2
	bl	_drm_order
	lsl	w21, w0, #1
Lloh18:
	adrp	x27, _DMA_RB_CNTL@GOTPAGE
Lloh19:
	ldr	x27, [x27, _DMA_RB_CNTL@GOTPAGEOFF]
	ldr	w0, [x27]
	mov	x1, x21
	bl	_WREG32
Lloh20:
	adrp	x28, _DMA_RB_RPTR@GOTPAGE
Lloh21:
	ldr	x28, [x28, _DMA_RB_RPTR@GOTPAGEOFF]
	ldr	w0, [x28]
	mov	w1, #0
	bl	_WREG32
Lloh22:
	adrp	x23, _DMA_RB_WPTR@GOTPAGE
Lloh23:
	ldr	x23, [x23, _DMA_RB_WPTR@GOTPAGEOFF]
	ldr	w0, [x23]
	mov	w1, #0
	bl	_WREG32
Lloh24:
	adrp	x8, _DMA_RB_RPTR_ADDR_HI@GOTPAGE
Lloh25:
	ldr	x8, [x8, _DMA_RB_RPTR_ADDR_HI@GOTPAGEOFF]
Lloh26:
	ldr	w22, [x8]
	ldr	w8, [x19, #16]
Lloh27:
	adrp	x26, _R600_WB_DMA_RPTR_OFFSET@GOTPAGE
Lloh28:
	ldr	x26, [x26, _R600_WB_DMA_RPTR_OFFSET@GOTPAGEOFF]
	ldr	w9, [x26]
	add	w0, w9, w8
	bl	_upper_32_bits
	and	w1, w0, #0xff
	mov	x0, x22
	bl	_WREG32
Lloh29:
	adrp	x8, _DMA_RB_RPTR_ADDR_LO@GOTPAGE
Lloh30:
	ldr	x8, [x8, _DMA_RB_RPTR_ADDR_LO@GOTPAGEOFF]
Lloh31:
	ldr	w0, [x8]
	ldr	w8, [x19, #16]
	ldr	w9, [x26]
	add	w8, w9, w8
	and	w1, w8, #0xfffffffc
	bl	_WREG32
	ldr	x8, [x19, #24]
Lloh32:
	adrp	x9, _DMA_RPTR_WRITEBACK_ENABLE@GOTPAGE
Lloh33:
	ldr	x9, [x9, _DMA_RPTR_WRITEBACK_ENABLE@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	cmp	x8, #0
	csel	w8, wzr, w9, eq
	orr	w21, w8, w21
Lloh35:
	adrp	x8, _DMA_RB_BASE@GOTPAGE
Lloh36:
	ldr	x8, [x8, _DMA_RB_BASE@GOTPAGEOFF]
Lloh37:
	ldr	w0, [x8]
	ldr	w8, [x20, #4]
	asr	w1, w8, #8
	bl	_WREG32
Lloh38:
	adrp	x8, _DMA_IB_ENABLE@GOTPAGE
Lloh39:
	ldr	x8, [x8, _DMA_IB_ENABLE@GOTPAGEOFF]
Lloh40:
	ldr	w1, [x8]
Lloh41:
	adrp	x8, _DMA_IB_CNTL@GOTPAGE
Lloh42:
	ldr	x8, [x8, _DMA_IB_CNTL@GOTPAGEOFF]
Lloh43:
	ldr	w0, [x8]
	bl	_WREG32
Lloh44:
	adrp	x22, _DMA_CNTL@GOTPAGE
Lloh45:
	ldr	x22, [x22, _DMA_CNTL@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_RREG32
Lloh46:
	adrp	x8, _CTXEMPTY_INT_ENABLE@GOTPAGE
Lloh47:
	ldr	x8, [x8, _CTXEMPTY_INT_ENABLE@GOTPAGEOFF]
Lloh48:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w0, [x22]
	bl	_WREG32
	ldr	x8, [x19]
Lloh49:
	adrp	x9, _CHIP_RV770@GOTPAGE
Lloh50:
	ldr	x9, [x9, _CHIP_RV770@GOTPAGEOFF]
Lloh51:
	ldr	x9, [x9]
	cmp	x8, x9
	b.lt	LBB0_2
; %bb.1:
Lloh52:
	adrp	x8, _DMA_MODE@GOTPAGE
Lloh53:
	ldr	x8, [x8, _DMA_MODE@GOTPAGEOFF]
Lloh54:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_WREG32
LBB0_2:
	mov	w8, #20
	madd	x22, x25, x8, x24
	str	wzr, [x22, #8]
	ldr	w0, [x23]
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x28]
	bl	_RREG32
	asr	w8, w0, #2
	str	w8, [x22, #12]
	ldr	w0, [x27]
Lloh55:
	adrp	x8, _DMA_RB_ENABLE@GOTPAGE
Lloh56:
	ldr	x8, [x8, _DMA_RB_ENABLE@GOTPAGEOFF]
Lloh57:
	ldr	w8, [x8]
	orr	w1, w21, w8
	bl	_WREG32
	mov	w8, #1
	str	w8, [x22, #16]!
Lloh58:
	adrp	x8, _R600_RING_TYPE_DMA_INDEX@GOTPAGE
Lloh59:
	ldr	x8, [x8, _R600_RING_TYPE_DMA_INDEX@GOTPAGEOFF]
Lloh60:
	ldr	x1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_radeon_ring_test
	mov	x20, x0
	cbz	w0, LBB0_4
; %bb.3:
	str	wzr, [x22]
	b	LBB0_5
LBB0_4:
	ldr	w1, [x19, #8]
	mov	x0, x19
	bl	_radeon_ttm_set_active_vram_size
LBB0_5:
	mov	x0, x20
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.cfi_endproc
                                        ; -- End function
	.comm	_R600_RING_TYPE_DMA_INDEX,8,3   ; @R600_RING_TYPE_DMA_INDEX
	.comm	_CHIP_RV770,8,3                 ; @CHIP_RV770
	.comm	_SRBM_SOFT_RESET,4,2            ; @SRBM_SOFT_RESET
	.comm	_RV770_SOFT_RESET_DMA,4,2       ; @RV770_SOFT_RESET_DMA
	.comm	_SOFT_RESET_DMA,4,2             ; @SOFT_RESET_DMA
	.comm	_DMA_SEM_INCOMPLETE_TIMER_CNTL,4,2 ; @DMA_SEM_INCOMPLETE_TIMER_CNTL
	.comm	_DMA_SEM_WAIT_FAIL_TIMER_CNTL,4,2 ; @DMA_SEM_WAIT_FAIL_TIMER_CNTL
	.comm	_DMA_RB_CNTL,4,2                ; @DMA_RB_CNTL
	.comm	_DMA_RB_RPTR,4,2                ; @DMA_RB_RPTR
	.comm	_DMA_RB_WPTR,4,2                ; @DMA_RB_WPTR
	.comm	_DMA_RB_RPTR_ADDR_HI,4,2        ; @DMA_RB_RPTR_ADDR_HI
	.comm	_R600_WB_DMA_RPTR_OFFSET,4,2    ; @R600_WB_DMA_RPTR_OFFSET
	.comm	_DMA_RB_RPTR_ADDR_LO,4,2        ; @DMA_RB_RPTR_ADDR_LO
	.comm	_DMA_RPTR_WRITEBACK_ENABLE,4,2  ; @DMA_RPTR_WRITEBACK_ENABLE
	.comm	_DMA_RB_BASE,4,2                ; @DMA_RB_BASE
	.comm	_DMA_IB_ENABLE,4,2              ; @DMA_IB_ENABLE
	.comm	_DMA_IB_CNTL,4,2                ; @DMA_IB_CNTL
	.comm	_DMA_CNTL,4,2                   ; @DMA_CNTL
	.comm	_CTXEMPTY_INT_ENABLE,4,2        ; @CTXEMPTY_INT_ENABLE
	.comm	_DMA_MODE,4,2                   ; @DMA_MODE
	.comm	_DMA_RB_ENABLE,4,2              ; @DMA_RB_ENABLE
	.comm	_DMA_IB_SWAP_ENABLE,4,2         ; @DMA_IB_SWAP_ENABLE
	.comm	_DMA_RB_SWAP_ENABLE,4,2         ; @DMA_RB_SWAP_ENABLE
	.comm	_DMA_RPTR_WRITEBACK_SWAP_ENABLE,4,2 ; @DMA_RPTR_WRITEBACK_SWAP_ENABLE
.subsections_via_symbols
