	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_card_posted             ## -- Begin function radeon_card_posted
	.p2align	4, 0x90
_radeon_card_posted:                    ## @radeon_card_posted
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_efi_enabled@GOTPCREL(%rip), %rax
	cmpq	$0, (%rax)
	je	LBB0_2
## %bb.1:
	movq	16(%r14), %rax
	movq	(%rax), %rcx
	movq	_PCI_VENDOR_ID_APPLE@GOTPCREL(%rip), %rdx
	xorl	%eax, %eax
	cmpq	(%rdx), %rcx
	je	LBB0_15
LBB0_2:
	movq	%r14, %rdi
	callq	_ASIC_IS_DCE4
	testq	%rax, %rax
	je	LBB0_7
## %bb.3:
	movq	_EVERGREEN_CRTC_CONTROL@GOTPCREL(%rip), %r12
	movq	_EVERGREEN_CRTC0_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r12), %rdi
	callq	_RREG32
	movl	%eax, %r15d
	movq	_EVERGREEN_CRTC1_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r12), %rdi
	callq	_RREG32
	movl	%eax, %ebx
	orl	%r15d, %ebx
	cmpl	$4, (%r14)
	jl	LBB0_6
## %bb.4:
	movq	_EVERGREEN_CRTC2_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r12), %rdi
	callq	_RREG32
	movl	%eax, %r15d
	movq	_EVERGREEN_CRTC3_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r12), %rdi
	callq	_RREG32
	orl	%r15d, %ebx
	orl	%eax, %ebx
	cmpl	$6, (%r14)
	jl	LBB0_6
## %bb.5:
	movq	_EVERGREEN_CRTC4_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r12), %rdi
	callq	_RREG32
	movl	%eax, %r15d
	movq	_EVERGREEN_CRTC5_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r12), %rdi
	callq	_RREG32
	orl	%ebx, %r15d
	orl	%eax, %r15d
	movl	%r15d, %ebx
LBB0_6:
	movq	_EVERGREEN_CRTC_MASTER_EN@GOTPCREL(%rip), %rcx
	movl	$1, %eax
	testl	%ebx, (%rcx)
	jne	LBB0_15
	jmp	LBB0_11
LBB0_7:
	movq	%r14, %rdi
	callq	_ASIC_IS_AVIVO
	testq	%rax, %rax
	je	LBB0_9
## %bb.8:
	movq	_AVIVO_D1CRTC_CONTROL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %ebx
	movq	_AVIVO_D2CRTC_CONTROL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %ecx
	orl	%ebx, %ecx
	movq	_AVIVO_CRTC_EN@GOTPCREL(%rip), %rdx
	jmp	LBB0_10
LBB0_9:
	movq	_RADEON_CRTC_GEN_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %ebx
	movq	_RADEON_CRTC2_GEN_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %ecx
	orl	%ebx, %ecx
	movq	_RADEON_CRTC_EN@GOTPCREL(%rip), %rdx
LBB0_10:
	movl	$1, %eax
	testl	%ecx, (%rdx)
	jne	LBB0_15
LBB0_11:
	movq	8(%r14), %rax
	movq	_CHIP_R600@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_12
## %bb.13:
	movq	_RADEON_CONFIG_MEMSIZE@GOTPCREL(%rip), %rax
	jmp	LBB0_14
LBB0_12:
	movq	_R600_CONFIG_MEMSIZE@GOTPCREL(%rip), %rax
LBB0_14:
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %ecx
	xorl	%eax, %eax
	testl	%ecx, %ecx
	setne	%al
LBB0_15:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_efi_enabled,8,3                ## @efi_enabled
	.comm	_PCI_VENDOR_ID_APPLE,8,3        ## @PCI_VENDOR_ID_APPLE
	.comm	_EVERGREEN_CRTC_CONTROL,8,3     ## @EVERGREEN_CRTC_CONTROL
	.comm	_EVERGREEN_CRTC0_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC0_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC1_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC1_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC2_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC2_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC3_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC3_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC4_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC4_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC5_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC5_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC_MASTER_EN,4,2   ## @EVERGREEN_CRTC_MASTER_EN
	.comm	_AVIVO_D1CRTC_CONTROL,8,3       ## @AVIVO_D1CRTC_CONTROL
	.comm	_AVIVO_D2CRTC_CONTROL,8,3       ## @AVIVO_D2CRTC_CONTROL
	.comm	_AVIVO_CRTC_EN,4,2              ## @AVIVO_CRTC_EN
	.comm	_RADEON_CRTC_GEN_CNTL,8,3       ## @RADEON_CRTC_GEN_CNTL
	.comm	_RADEON_CRTC2_GEN_CNTL,8,3      ## @RADEON_CRTC2_GEN_CNTL
	.comm	_RADEON_CRTC_EN,4,2             ## @RADEON_CRTC_EN
	.comm	_CHIP_R600,8,3                  ## @CHIP_R600
	.comm	_R600_CONFIG_MEMSIZE,8,3        ## @R600_CONFIG_MEMSIZE
	.comm	_RADEON_CONFIG_MEMSIZE,8,3      ## @RADEON_CONFIG_MEMSIZE
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_card_posted             ; -- Begin function radeon_card_posted
	.p2align	2
_radeon_card_posted:                    ; @radeon_card_posted
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, _efi_enabled@GOTPAGE
Lloh1:
	ldr	x8, [x8, _efi_enabled@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	cbz	x8, LBB0_3
; %bb.1:
	ldr	x8, [x19, #16]
	ldr	x8, [x8]
Lloh3:
	adrp	x9, _PCI_VENDOR_ID_APPLE@GOTPAGE
Lloh4:
	ldr	x9, [x9, _PCI_VENDOR_ID_APPLE@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_3
; %bb.2:
	mov	w0, #0
	b	LBB0_14
LBB0_3:
	mov	x0, x19
	bl	_ASIC_IS_DCE4
	cbz	x0, LBB0_9
; %bb.4:
Lloh6:
	adrp	x21, _EVERGREEN_CRTC_CONTROL@GOTPAGE
Lloh7:
	ldr	x21, [x21, _EVERGREEN_CRTC_CONTROL@GOTPAGEOFF]
	ldr	x8, [x21]
Lloh8:
	adrp	x9, _EVERGREEN_CRTC0_REGISTER_OFFSET@GOTPAGE
Lloh9:
	ldr	x9, [x9, _EVERGREEN_CRTC0_REGISTER_OFFSET@GOTPAGEOFF]
Lloh10:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_RREG32
	mov	x20, x0
	ldr	x8, [x21]
Lloh11:
	adrp	x9, _EVERGREEN_CRTC1_REGISTER_OFFSET@GOTPAGE
Lloh12:
	ldr	x9, [x9, _EVERGREEN_CRTC1_REGISTER_OFFSET@GOTPAGEOFF]
Lloh13:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_RREG32
	orr	w22, w0, w20
	ldr	w8, [x19]
	cmp	w8, #4
	b.lt	LBB0_7
; %bb.5:
	ldr	x8, [x21]
Lloh14:
	adrp	x9, _EVERGREEN_CRTC2_REGISTER_OFFSET@GOTPAGE
Lloh15:
	ldr	x9, [x9, _EVERGREEN_CRTC2_REGISTER_OFFSET@GOTPAGEOFF]
Lloh16:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_RREG32
	mov	x20, x0
	ldr	x8, [x21]
Lloh17:
	adrp	x9, _EVERGREEN_CRTC3_REGISTER_OFFSET@GOTPAGE
Lloh18:
	ldr	x9, [x9, _EVERGREEN_CRTC3_REGISTER_OFFSET@GOTPAGEOFF]
Lloh19:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_RREG32
	orr	w8, w20, w22
	orr	w22, w8, w0
	ldr	w8, [x19]
	cmp	w8, #6
	b.lt	LBB0_7
; %bb.6:
	ldr	x8, [x21]
Lloh20:
	adrp	x9, _EVERGREEN_CRTC4_REGISTER_OFFSET@GOTPAGE
Lloh21:
	ldr	x9, [x9, _EVERGREEN_CRTC4_REGISTER_OFFSET@GOTPAGEOFF]
Lloh22:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_RREG32
	mov	x20, x0
	ldr	x8, [x21]
Lloh23:
	adrp	x9, _EVERGREEN_CRTC5_REGISTER_OFFSET@GOTPAGE
Lloh24:
	ldr	x9, [x9, _EVERGREEN_CRTC5_REGISTER_OFFSET@GOTPAGEOFF]
Lloh25:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_RREG32
	orr	w8, w20, w22
	orr	w22, w8, w0
LBB0_7:
Lloh26:
	adrp	x8, _EVERGREEN_CRTC_MASTER_EN@GOTPAGE
Lloh27:
	ldr	x8, [x8, _EVERGREEN_CRTC_MASTER_EN@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_13
LBB0_8:
	mov	w0, #1
	b	LBB0_14
LBB0_9:
	mov	x0, x19
	bl	_ASIC_IS_AVIVO
	cbz	x0, LBB0_11
; %bb.10:
Lloh29:
	adrp	x8, _AVIVO_D1CRTC_CONTROL@GOTPAGE
Lloh30:
	ldr	x8, [x8, _AVIVO_D1CRTC_CONTROL@GOTPAGEOFF]
Lloh31:
	ldr	x0, [x8]
	bl	_RREG32
	mov	x20, x0
Lloh32:
	adrp	x8, _AVIVO_D2CRTC_CONTROL@GOTPAGE
Lloh33:
	ldr	x8, [x8, _AVIVO_D2CRTC_CONTROL@GOTPAGEOFF]
Lloh34:
	ldr	x0, [x8]
	bl	_RREG32
	orr	w8, w0, w20
Lloh35:
	adrp	x9, _AVIVO_CRTC_EN@GOTPAGE
Lloh36:
	ldr	x9, [x9, _AVIVO_CRTC_EN@GOTPAGEOFF]
	b	LBB0_12
LBB0_11:
Lloh37:
	adrp	x8, _RADEON_CRTC_GEN_CNTL@GOTPAGE
Lloh38:
	ldr	x8, [x8, _RADEON_CRTC_GEN_CNTL@GOTPAGEOFF]
Lloh39:
	ldr	x0, [x8]
	bl	_RREG32
	mov	x20, x0
Lloh40:
	adrp	x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGE
Lloh41:
	ldr	x8, [x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGEOFF]
Lloh42:
	ldr	x0, [x8]
	bl	_RREG32
	orr	w8, w0, w20
Lloh43:
	adrp	x9, _RADEON_CRTC_EN@GOTPAGE
Lloh44:
	ldr	x9, [x9, _RADEON_CRTC_EN@GOTPAGEOFF]
LBB0_12:
	ldr	w9, [x9]
	tst	w8, w9
	b.ne	LBB0_8
LBB0_13:
	ldr	x8, [x19, #8]
Lloh45:
	adrp	x9, _CHIP_R600@GOTPAGE
Lloh46:
	ldr	x9, [x9, _CHIP_R600@GOTPAGEOFF]
Lloh47:
	adrp	x10, _RADEON_CONFIG_MEMSIZE@GOTPAGE
Lloh48:
	ldr	x10, [x10, _RADEON_CONFIG_MEMSIZE@GOTPAGEOFF]
Lloh49:
	ldr	x9, [x9]
Lloh50:
	adrp	x11, _R600_CONFIG_MEMSIZE@GOTPAGE
Lloh51:
	ldr	x11, [x11, _R600_CONFIG_MEMSIZE@GOTPAGEOFF]
	cmp	x8, x9
	csel	x8, x10, x11, lt
	ldr	x0, [x8]
	bl	_RREG32
	cmp	w0, #0
	cset	w0, ne
LBB0_14:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh49
	.cfi_endproc
                                        ; -- End function
	.comm	_efi_enabled,8,3                ; @efi_enabled
	.comm	_PCI_VENDOR_ID_APPLE,8,3        ; @PCI_VENDOR_ID_APPLE
	.comm	_EVERGREEN_CRTC_CONTROL,8,3     ; @EVERGREEN_CRTC_CONTROL
	.comm	_EVERGREEN_CRTC0_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC0_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC1_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC1_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC2_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC2_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC3_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC3_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC4_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC4_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC5_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC5_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC_MASTER_EN,4,2   ; @EVERGREEN_CRTC_MASTER_EN
	.comm	_AVIVO_D1CRTC_CONTROL,8,3       ; @AVIVO_D1CRTC_CONTROL
	.comm	_AVIVO_D2CRTC_CONTROL,8,3       ; @AVIVO_D2CRTC_CONTROL
	.comm	_AVIVO_CRTC_EN,4,2              ; @AVIVO_CRTC_EN
	.comm	_RADEON_CRTC_GEN_CNTL,8,3       ; @RADEON_CRTC_GEN_CNTL
	.comm	_RADEON_CRTC2_GEN_CNTL,8,3      ; @RADEON_CRTC2_GEN_CNTL
	.comm	_RADEON_CRTC_EN,4,2             ; @RADEON_CRTC_EN
	.comm	_CHIP_R600,8,3                  ; @CHIP_R600
	.comm	_R600_CONFIG_MEMSIZE,8,3        ; @R600_CONFIG_MEMSIZE
	.comm	_RADEON_CONFIG_MEMSIZE,8,3      ; @RADEON_CONFIG_MEMSIZE
.subsections_via_symbols
