	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_legacy_primary_dac_mode_set
_radeon_legacy_primary_dac_mode_set:    ## @radeon_legacy_primary_dac_mode_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r13
	movq	8(%rdi), %rax
	movq	(%rax), %r14
	movl	(%rdi), %edi
	callq	_to_radeon_crtc
	movq	%rax, %r15
	movq	%r13, %rdi
	callq	_to_radeon_encoder
	movq	%rax, %r12
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	cmpq	$0, (%r15)
	movq	(%r14), %rax
	movq	_CHIP_R200@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	je	LBB0_1
## %bb.6:
	cmpq	%rcx, %rax
	je	LBB0_8
## %bb.7:
	movq	%r14, %rdi
	callq	_ASIC_IS_R300
	testq	%rax, %rax
	je	LBB0_9
LBB0_8:
	movq	_RADEON_DISP_OUTPUT_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_RADEON_DISP_DAC_SOURCE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_RADEON_DISP_DAC_SOURCE_CRTC2@GOTPCREL(%rip), %rax
LBB0_10:
	orl	(%rax), %esi
	jmp	LBB0_11
LBB0_1:
	cmpq	%rcx, %rax
	je	LBB0_3
## %bb.2:
	movq	%r14, %rdi
	callq	_ASIC_IS_R300
	testq	%rax, %rax
	je	LBB0_5
LBB0_3:
	movq	_RADEON_DISP_OUTPUT_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_RADEON_DISP_DAC_SOURCE_MASK@GOTPCREL(%rip), %rcx
	jmp	LBB0_4
LBB0_9:
	movq	_RADEON_DAC_CNTL2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movl	%eax, %esi
	movq	_RADEON_DAC2_DAC_CLK_SEL@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_5:
	movq	_RADEON_DAC_CNTL2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_RADEON_DAC2_DAC_CLK_SEL@GOTPCREL(%rip), %rcx
LBB0_4:
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
LBB0_11:
	movl	(%rbx), %edi
	callq	_WREG32
	movq	_RADEON_DAC_MASK_ALL@GOTPCREL(%rip), %rax
	movq	_RADEON_DAC_VGA_ADR_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movq	_RADEON_DAC_8BIT_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_RADEON_DAC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_DAC_RANGE_CNTL@GOTPCREL(%rip), %rax
	movq	_RADEON_DAC_BLANKING@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	callq	_WREG32_P
	movq	(%r12), %rax
	testq	%rax, %rax
	je	LBB0_13
## %bb.12:
	movl	(%rax), %esi
	jmp	LBB0_14
LBB0_13:
	movq	_RADEON_DAC_MACRO_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %esi
LBB0_14:
	movq	_RADEON_DAC_PDWN_R@GOTPCREL(%rip), %rax
	movq	_RADEON_DAC_PDWN_G@GOTPCREL(%rip), %rcx
	movq	_RADEON_DAC_PDWN_B@GOTPCREL(%rip), %rdx
	orl	(%rax), %esi
	orl	(%rcx), %esi
	orl	(%rdx), %esi
	movq	_RADEON_DAC_MACRO_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32
	cmpq	$0, 8(%r14)
	movq	(%r15), %rsi
	movq	%r13, %rdi
	je	LBB0_16
## %bb.15:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_atombios_encoder_crtc_scratch_regs ## TAILCALL
LBB0_16:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_combios_encoder_crtc_scratch_regs ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"\n"

	.comm	_CHIP_R200,8,3                  ## @CHIP_R200
	.comm	_RADEON_DISP_OUTPUT_CNTL,4,2    ## @RADEON_DISP_OUTPUT_CNTL
	.comm	_RADEON_DISP_DAC_SOURCE_MASK,4,2 ## @RADEON_DISP_DAC_SOURCE_MASK
	.comm	_RADEON_DAC_CNTL2,4,2           ## @RADEON_DAC_CNTL2
	.comm	_RADEON_DAC2_DAC_CLK_SEL,4,2    ## @RADEON_DAC2_DAC_CLK_SEL
	.comm	_RADEON_DISP_DAC_SOURCE_CRTC2,4,2 ## @RADEON_DISP_DAC_SOURCE_CRTC2
	.comm	_RADEON_DAC_MASK_ALL,4,2        ## @RADEON_DAC_MASK_ALL
	.comm	_RADEON_DAC_VGA_ADR_EN,4,2      ## @RADEON_DAC_VGA_ADR_EN
	.comm	_RADEON_DAC_8BIT_EN,4,2         ## @RADEON_DAC_8BIT_EN
	.comm	_RADEON_DAC_CNTL,4,2            ## @RADEON_DAC_CNTL
	.comm	_RADEON_DAC_RANGE_CNTL,4,2      ## @RADEON_DAC_RANGE_CNTL
	.comm	_RADEON_DAC_BLANKING,4,2        ## @RADEON_DAC_BLANKING
	.comm	_RADEON_DAC_MACRO_CNTL,4,2      ## @RADEON_DAC_MACRO_CNTL
	.comm	_RADEON_DAC_PDWN_R,4,2          ## @RADEON_DAC_PDWN_R
	.comm	_RADEON_DAC_PDWN_G,4,2          ## @RADEON_DAC_PDWN_G
	.comm	_RADEON_DAC_PDWN_B,4,2          ## @RADEON_DAC_PDWN_B
	.no_dead_strip	_radeon_legacy_primary_dac_mode_set
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_legacy_primary_dac_mode_set
_radeon_legacy_primary_dac_mode_set:    ; @radeon_legacy_primary_dac_mode_set
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	x8, [x0, #8]
	ldr	x20, [x8]
	ldr	w0, [x0]
	bl	_to_radeon_crtc
	mov	x21, x0
	mov	x0, x19
	bl	_to_radeon_encoder
	mov	x22, x0
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_KMS
	ldr	x10, [x21]
	ldr	x8, [x20]
Lloh2:
	adrp	x9, _CHIP_R200@GOTPAGE
Lloh3:
	ldr	x9, [x9, _CHIP_R200@GOTPAGEOFF]
Lloh4:
	ldr	x9, [x9]
	cmp	x8, x9
	cbz	x10, LBB0_4
; %bb.1:
	b.eq	LBB0_3
; %bb.2:
	mov	x0, x20
	bl	_ASIC_IS_R300
	cbz	x0, LBB0_7
LBB0_3:
Lloh5:
	adrp	x23, _RADEON_DISP_OUTPUT_CNTL@GOTPAGE
Lloh6:
	ldr	x23, [x23, _RADEON_DISP_OUTPUT_CNTL@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32
Lloh7:
	adrp	x8, _RADEON_DISP_DAC_SOURCE_MASK@GOTPAGE
Lloh8:
	ldr	x8, [x8, _RADEON_DISP_DAC_SOURCE_MASK@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh10:
	adrp	x9, _RADEON_DISP_DAC_SOURCE_CRTC2@GOTPAGE
Lloh11:
	ldr	x9, [x9, _RADEON_DISP_DAC_SOURCE_CRTC2@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
	orr	w1, w8, w9
	b	LBB0_10
LBB0_4:
	b.eq	LBB0_6
; %bb.5:
	mov	x0, x20
	bl	_ASIC_IS_R300
	cbz	x0, LBB0_8
LBB0_6:
Lloh13:
	adrp	x23, _RADEON_DISP_OUTPUT_CNTL@GOTPAGE
Lloh14:
	ldr	x23, [x23, _RADEON_DISP_OUTPUT_CNTL@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32
Lloh15:
	adrp	x8, _RADEON_DISP_DAC_SOURCE_MASK@GOTPAGE
Lloh16:
	ldr	x8, [x8, _RADEON_DISP_DAC_SOURCE_MASK@GOTPAGEOFF]
	b	LBB0_9
LBB0_7:
Lloh17:
	adrp	x23, _RADEON_DAC_CNTL2@GOTPAGE
Lloh18:
	ldr	x23, [x23, _RADEON_DAC_CNTL2@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32
Lloh19:
	adrp	x8, _RADEON_DAC2_DAC_CLK_SEL@GOTPAGE
Lloh20:
	ldr	x8, [x8, _RADEON_DAC2_DAC_CLK_SEL@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
	orr	w1, w8, w0
	b	LBB0_10
LBB0_8:
Lloh22:
	adrp	x23, _RADEON_DAC_CNTL2@GOTPAGE
Lloh23:
	ldr	x23, [x23, _RADEON_DAC_CNTL2@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32
Lloh24:
	adrp	x8, _RADEON_DAC2_DAC_CLK_SEL@GOTPAGE
Lloh25:
	ldr	x8, [x8, _RADEON_DAC2_DAC_CLK_SEL@GOTPAGEOFF]
LBB0_9:
	ldr	w8, [x8]
	bic	w1, w0, w8
LBB0_10:
	ldr	w0, [x23]
	bl	_WREG32
Lloh26:
	adrp	x8, _RADEON_DAC_MASK_ALL@GOTPAGE
Lloh27:
	ldr	x8, [x8, _RADEON_DAC_MASK_ALL@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
Lloh29:
	adrp	x9, _RADEON_DAC_VGA_ADR_EN@GOTPAGE
Lloh30:
	ldr	x9, [x9, _RADEON_DAC_VGA_ADR_EN@GOTPAGEOFF]
Lloh31:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh32:
	adrp	x9, _RADEON_DAC_8BIT_EN@GOTPAGE
Lloh33:
	ldr	x9, [x9, _RADEON_DAC_8BIT_EN@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	orr	w1, w8, w9
Lloh35:
	adrp	x8, _RADEON_DAC_CNTL@GOTPAGE
Lloh36:
	ldr	x8, [x8, _RADEON_DAC_CNTL@GOTPAGEOFF]
Lloh37:
	adrp	x9, _RADEON_DAC_RANGE_CNTL@GOTPAGE
Lloh38:
	ldr	x9, [x9, _RADEON_DAC_RANGE_CNTL@GOTPAGEOFF]
Lloh39:
	ldr	w0, [x8]
Lloh40:
	ldr	w8, [x9]
Lloh41:
	adrp	x9, _RADEON_DAC_BLANKING@GOTPAGE
Lloh42:
	ldr	x9, [x9, _RADEON_DAC_BLANKING@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
	orr	w2, w9, w8
	bl	_WREG32_P
	ldr	x8, [x22]
Lloh44:
	adrp	x22, _RADEON_DAC_MACRO_CNTL@GOTPAGE
Lloh45:
	ldr	x22, [x22, _RADEON_DAC_MACRO_CNTL@GOTPAGEOFF]
	cbz	x8, LBB0_12
; %bb.11:
	ldr	w0, [x8]
	b	LBB0_13
LBB0_12:
	ldr	w0, [x22]
	bl	_RREG32
LBB0_13:
Lloh46:
	adrp	x8, _RADEON_DAC_PDWN_R@GOTPAGE
Lloh47:
	ldr	x8, [x8, _RADEON_DAC_PDWN_R@GOTPAGEOFF]
Lloh48:
	ldr	w8, [x8]
Lloh49:
	adrp	x9, _RADEON_DAC_PDWN_G@GOTPAGE
Lloh50:
	ldr	x9, [x9, _RADEON_DAC_PDWN_G@GOTPAGEOFF]
Lloh51:
	adrp	x10, _RADEON_DAC_PDWN_B@GOTPAGE
Lloh52:
	ldr	x10, [x10, _RADEON_DAC_PDWN_B@GOTPAGEOFF]
Lloh53:
	ldr	w9, [x9]
Lloh54:
	ldr	w10, [x10]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w1, w8, w10
	ldr	w0, [x22]
	bl	_WREG32
	ldr	x8, [x20, #8]
	ldr	x1, [x21]
	mov	x0, x19
	cbz	x8, LBB0_15
; %bb.14:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_radeon_atombios_encoder_crtc_scratch_regs
LBB0_15:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_radeon_combios_encoder_crtc_scratch_regs
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh39
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh53
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"\n"

	.comm	_CHIP_R200,8,3                  ; @CHIP_R200
	.comm	_RADEON_DISP_OUTPUT_CNTL,4,2    ; @RADEON_DISP_OUTPUT_CNTL
	.comm	_RADEON_DISP_DAC_SOURCE_MASK,4,2 ; @RADEON_DISP_DAC_SOURCE_MASK
	.comm	_RADEON_DAC_CNTL2,4,2           ; @RADEON_DAC_CNTL2
	.comm	_RADEON_DAC2_DAC_CLK_SEL,4,2    ; @RADEON_DAC2_DAC_CLK_SEL
	.comm	_RADEON_DISP_DAC_SOURCE_CRTC2,4,2 ; @RADEON_DISP_DAC_SOURCE_CRTC2
	.comm	_RADEON_DAC_MASK_ALL,4,2        ; @RADEON_DAC_MASK_ALL
	.comm	_RADEON_DAC_VGA_ADR_EN,4,2      ; @RADEON_DAC_VGA_ADR_EN
	.comm	_RADEON_DAC_8BIT_EN,4,2         ; @RADEON_DAC_8BIT_EN
	.comm	_RADEON_DAC_CNTL,4,2            ; @RADEON_DAC_CNTL
	.comm	_RADEON_DAC_RANGE_CNTL,4,2      ; @RADEON_DAC_RANGE_CNTL
	.comm	_RADEON_DAC_BLANKING,4,2        ; @RADEON_DAC_BLANKING
	.comm	_RADEON_DAC_MACRO_CNTL,4,2      ; @RADEON_DAC_MACRO_CNTL
	.comm	_RADEON_DAC_PDWN_R,4,2          ; @RADEON_DAC_PDWN_R
	.comm	_RADEON_DAC_PDWN_G,4,2          ; @RADEON_DAC_PDWN_G
	.comm	_RADEON_DAC_PDWN_B,4,2          ; @RADEON_DAC_PDWN_B
	.no_dead_strip	_radeon_legacy_primary_dac_mode_set
.subsections_via_symbols
