	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_dp_update_vs_emph
_radeon_dp_update_vs_emph:              ## @radeon_dp_update_vs_emph
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	movl	20(%rdi), %edi
	movq	_ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	8(%rbx), %rax
	movl	(%rax), %ecx
	xorl	%edx, %edx
	callq	_atombios_dig_transmitter_setup
	movl	16(%rbx), %edi
	movq	_DP_TRAINING_LANE0_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	8(%rbx), %rdx
	movl	(%rbx), %ecx
	xorl	%r8d, %r8d
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_radeon_dp_aux_native_write     ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,4,2 ## @ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
	.comm	_DP_TRAINING_LANE0_SET,4,2      ## @DP_TRAINING_LANE0_SET
	.no_dead_strip	_radeon_dp_update_vs_emph
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_dp_update_vs_emph
_radeon_dp_update_vs_emph:              ; @radeon_dp_update_vs_emph
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	w0, [x0, #20]
Lloh0:
	adrp	x8, _ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH@GOTPAGE
Lloh1:
	ldr	x8, [x8, _ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	ldr	x8, [x19, #8]
	ldr	w3, [x8]
	mov	w2, #0
	bl	_atombios_dig_transmitter_setup
	ldr	w0, [x19, #16]
Lloh3:
	adrp	x8, _DP_TRAINING_LANE0_SET@GOTPAGE
Lloh4:
	ldr	x8, [x8, _DP_TRAINING_LANE0_SET@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	ldr	x2, [x19, #8]
	ldr	w3, [x19]
	mov	w4, #0
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_radeon_dp_aux_native_write
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,4,2 ; @ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
	.comm	_DP_TRAINING_LANE0_SET,4,2      ; @DP_TRAINING_LANE0_SET
	.no_dead_strip	_radeon_dp_update_vs_emph
.subsections_via_symbols
