	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function intel_dp_pre_emphasis_max
_intel_dp_pre_emphasis_max:             ## @intel_dp_pre_emphasis_max
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %ebx
	movq	%rdi, %r15
	callq	_intel_dp_to_dev
	movq	%rax, %r14
	movq	%rax, %rdi
	callq	_IS_HASWELL
	testq	%rax, %rax
	je	LBB0_3
## %bb.1:
	movq	_DP_TRAIN_VOLTAGE_SWING_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %ebx
	addl	$-128, %ebx
	cmpl	$3, %ebx
	jae	LBB0_10
## %bb.2:
	movslq	%ebx, %rax
	leaq	l_switch.table.intel_dp_pre_emphasis_max(%rip), %rcx
	jmp	LBB0_8
LBB0_3:
	movq	%r14, %rdi
	callq	_IS_GEN7
	testq	%rax, %rax
	je	LBB0_6
## %bb.4:
	movq	%r15, %rdi
	callq	_is_cpu_edp
	testq	%rax, %rax
	je	LBB0_6
## %bb.5:
	movq	%r14, %rdi
	callq	_IS_VALLEYVIEW
	testl	%eax, %eax
	je	LBB0_12
LBB0_6:
	movq	_DP_TRAIN_VOLTAGE_SWING_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %ebx
	addl	$-128, %ebx
	cmpl	$3, %ebx
	jae	LBB0_10
## %bb.7:
	movslq	%ebx, %rax
	leaq	l_switch.table.intel_dp_pre_emphasis_max.2(%rip), %rcx
LBB0_8:
	leaq	(%rcx,%rax,8), %rax
	movq	(%rax), %rax
	jmp	LBB0_11
LBB0_12:
	movq	_DP_TRAIN_VOLTAGE_SWING_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %ebx
	addl	$-128, %ebx
	cmpl	$3, %ebx
	jae	LBB0_10
## %bb.13:
	movslq	%ebx, %rax
	leaq	l_switch.table.intel_dp_pre_emphasis_max.1(%rip), %rcx
	jmp	LBB0_8
LBB0_10:
	movq	_DP_TRAIN_PRE_EMPHASIS_0@GOTPCREL(%rip), %rax
LBB0_11:
	movl	(%rax), %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DP_TRAIN_VOLTAGE_SWING_MASK,4,2 ## @DP_TRAIN_VOLTAGE_SWING_MASK
	.comm	_DP_TRAIN_PRE_EMPHASIS_9_5,4,2  ## @DP_TRAIN_PRE_EMPHASIS_9_5
	.comm	_DP_TRAIN_PRE_EMPHASIS_6,4,2    ## @DP_TRAIN_PRE_EMPHASIS_6
	.comm	_DP_TRAIN_PRE_EMPHASIS_3_5,4,2  ## @DP_TRAIN_PRE_EMPHASIS_3_5
	.comm	_DP_TRAIN_PRE_EMPHASIS_0,4,2    ## @DP_TRAIN_PRE_EMPHASIS_0
	.no_dead_strip	_intel_dp_pre_emphasis_max
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.intel_dp_pre_emphasis_max
l_switch.table.intel_dp_pre_emphasis_max:
	.quad	_DP_TRAIN_PRE_EMPHASIS_3_5
	.quad	_DP_TRAIN_PRE_EMPHASIS_6
	.quad	_DP_TRAIN_PRE_EMPHASIS_9_5

	.p2align	3                               ## @switch.table.intel_dp_pre_emphasis_max.1
l_switch.table.intel_dp_pre_emphasis_max.1:
	.quad	_DP_TRAIN_PRE_EMPHASIS_3_5
	.quad	_DP_TRAIN_PRE_EMPHASIS_3_5
	.quad	_DP_TRAIN_PRE_EMPHASIS_6

	.p2align	3                               ## @switch.table.intel_dp_pre_emphasis_max.2
l_switch.table.intel_dp_pre_emphasis_max.2:
	.quad	_DP_TRAIN_PRE_EMPHASIS_3_5
	.quad	_DP_TRAIN_PRE_EMPHASIS_6
	.quad	_DP_TRAIN_PRE_EMPHASIS_6

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function intel_dp_pre_emphasis_max
_intel_dp_pre_emphasis_max:             ; @intel_dp_pre_emphasis_max
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x1
	mov	x21, x0
	bl	_intel_dp_to_dev
	mov	x20, x0
	bl	_IS_HASWELL
	cbz	x0, LBB0_3
; %bb.1:
Lloh0:
	adrp	x8, _DP_TRAIN_VOLTAGE_SWING_MASK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DP_TRAIN_VOLTAGE_SWING_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	and	w8, w8, w19
	sub	w8, w8, #128
	cmp	w8, #3
	b.hs	LBB0_11
; %bb.2:
Lloh3:
	adrp	x9, l_switch.table.intel_dp_pre_emphasis_max@PAGE
Lloh4:
	add	x9, x9, l_switch.table.intel_dp_pre_emphasis_max@PAGEOFF
	b	LBB0_8
LBB0_3:
	mov	x0, x20
	bl	_IS_GEN7
	cbz	x0, LBB0_6
; %bb.4:
	mov	x0, x21
	bl	_is_cpu_edp
	cbz	x0, LBB0_6
; %bb.5:
	mov	x0, x20
	bl	_IS_VALLEYVIEW
	cbz	w0, LBB0_9
LBB0_6:
Lloh5:
	adrp	x8, _DP_TRAIN_VOLTAGE_SWING_MASK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _DP_TRAIN_VOLTAGE_SWING_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	and	w8, w8, w19
	sub	w8, w8, #128
	cmp	w8, #2
	b.hi	LBB0_11
; %bb.7:
Lloh8:
	adrp	x9, l_switch.table.intel_dp_pre_emphasis_max.2@PAGE
Lloh9:
	add	x9, x9, l_switch.table.intel_dp_pre_emphasis_max.2@PAGEOFF
LBB0_8:
	ldr	x8, [x9, w8, sxtw #3]
	b	LBB0_12
LBB0_9:
Lloh10:
	adrp	x8, _DP_TRAIN_VOLTAGE_SWING_MASK@GOTPAGE
Lloh11:
	ldr	x8, [x8, _DP_TRAIN_VOLTAGE_SWING_MASK@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	and	w8, w8, w19
	sub	w8, w8, #128
	cmp	w8, #3
	b.hs	LBB0_11
; %bb.10:
Lloh13:
	adrp	x9, l_switch.table.intel_dp_pre_emphasis_max.1@PAGE
Lloh14:
	add	x9, x9, l_switch.table.intel_dp_pre_emphasis_max.1@PAGEOFF
	b	LBB0_8
LBB0_11:
Lloh15:
	adrp	x8, _DP_TRAIN_PRE_EMPHASIS_0@GOTPAGE
Lloh16:
	ldr	x8, [x8, _DP_TRAIN_PRE_EMPHASIS_0@GOTPAGEOFF]
LBB0_12:
	ldr	w0, [x8]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpAdd	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh15, Lloh16
	.cfi_endproc
                                        ; -- End function
	.comm	_DP_TRAIN_VOLTAGE_SWING_MASK,4,2 ; @DP_TRAIN_VOLTAGE_SWING_MASK
	.comm	_DP_TRAIN_PRE_EMPHASIS_9_5,4,2  ; @DP_TRAIN_PRE_EMPHASIS_9_5
	.comm	_DP_TRAIN_PRE_EMPHASIS_6,4,2    ; @DP_TRAIN_PRE_EMPHASIS_6
	.comm	_DP_TRAIN_PRE_EMPHASIS_3_5,4,2  ; @DP_TRAIN_PRE_EMPHASIS_3_5
	.comm	_DP_TRAIN_PRE_EMPHASIS_0,4,2    ; @DP_TRAIN_PRE_EMPHASIS_0
	.no_dead_strip	_intel_dp_pre_emphasis_max
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.intel_dp_pre_emphasis_max
l_switch.table.intel_dp_pre_emphasis_max:
	.quad	_DP_TRAIN_PRE_EMPHASIS_3_5
	.quad	_DP_TRAIN_PRE_EMPHASIS_6
	.quad	_DP_TRAIN_PRE_EMPHASIS_9_5

	.p2align	3                               ; @switch.table.intel_dp_pre_emphasis_max.1
l_switch.table.intel_dp_pre_emphasis_max.1:
	.quad	_DP_TRAIN_PRE_EMPHASIS_3_5
	.quad	_DP_TRAIN_PRE_EMPHASIS_3_5
	.quad	_DP_TRAIN_PRE_EMPHASIS_6

	.p2align	3                               ; @switch.table.intel_dp_pre_emphasis_max.2
l_switch.table.intel_dp_pre_emphasis_max.2:
	.quad	_DP_TRAIN_PRE_EMPHASIS_3_5
	.quad	_DP_TRAIN_PRE_EMPHASIS_6
	.quad	_DP_TRAIN_PRE_EMPHASIS_6

.subsections_via_symbols
