	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_bo_pin_restricted       ## -- Begin function radeon_bo_pin_restricted
	.p2align	4, 0x90
_radeon_bo_pin_restricted:              ## @radeon_bo_pin_restricted
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rcx, %r14
	movq	%rdx, %r15
	movq	%rsi, %r13
	movq	%rdi, %rbx
	movl	(%rdi), %eax
	testl	%eax, %eax
	je	LBB0_5
## %bb.1:
	incl	%eax
	movl	%eax, (%rbx)
	testq	%r14, %r14
	je	LBB0_3
## %bb.2:
	movq	%rbx, %rdi
	callq	_radeon_bo_gpu_offset
	movq	%rax, (%r14)
LBB0_3:
	xorl	%r12d, %r12d
	testq	%r15, %r15
	je	LBB0_20
## %bb.4:
	movq	_RADEON_GEM_DOMAIN_VRAM@GOTPCREL(%rip), %rax
	xorl	%ecx, %ecx
	cmpq	%r13, (%rax)
	setne	%cl
	movq	8(%rbx), %rax
	movq	8(%rax,%rcx,8), %r14
	movq	%rbx, %rdi
	callq	_radeon_bo_gpu_offset
	subq	%r14, %rax
	xorl	%edi, %edi
	cmpq	%r15, %rax
	setg	%dil
	callq	_WARN_ON_ONCE
	jmp	LBB0_20
LBB0_5:
	movq	%rbx, %rdi
	movq	%r13, %rsi
	callq	_radeon_ttm_placement_from_domain
	movq	_RADEON_GEM_DOMAIN_VRAM@GOTPCREL(%rip), %rax
	cmpq	%r13, (%rax)
	jne	LBB0_7
## %bb.6:
	movq	8(%rbx), %rax
	movq	24(%rax), %rax
	movq	_PAGE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarq	%cl, %rax
	movq	%rax, 16(%rbx)
LBB0_7:
	testq	%r15, %r15
	je	LBB0_12
## %bb.8:
	movq	_PAGE_SHIFT@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	sarq	%cl, %r15
	movq	16(%rbx), %rax
	testq	%rax, %rax
	je	LBB0_9
## %bb.10:
	cmpq	%rax, %r15
	jge	LBB0_12
LBB0_11:
	movq	%r15, 16(%rbx)
LBB0_12:
	cmpl	$0, 24(%rbx)
	jle	LBB0_15
## %bb.13:
	movq	40(%rbx), %rax
	xorl	%ecx, %ecx
	movq	_TTM_PL_FLAG_NO_EVICT@GOTPCREL(%rip), %rdx
	.p2align	4, 0x90
LBB0_14:                                ## =>This Inner Loop Header: Depth=1
	movl	(%rdx), %esi
	orl	%esi, (%rax,%rcx,4)
	incq	%rcx
	movslq	24(%rbx), %rsi
	cmpq	%rsi, %rcx
	jl	LBB0_14
LBB0_15:
	leaq	16(%rbx), %rsi
	leaq	32(%rbx), %rdi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	callq	_ttm_bo_validate
	movl	%eax, %r12d
	xorl	%edi, %edi
	testl	%eax, %eax
	sete	%dil
	callq	_likely
	testq	%rax, %rax
	je	LBB0_18
## %bb.16:
	movl	$1, (%rbx)
	testq	%r14, %r14
	je	LBB0_18
## %bb.17:
	movq	%rbx, %rdi
	callq	_radeon_bo_gpu_offset
	movq	%rax, (%r14)
LBB0_18:
	xorl	%edi, %edi
	testl	%r12d, %r12d
	setne	%dil
	callq	_unlikely
	testq	%rax, %rax
	je	LBB0_20
## %bb.19:
	movq	8(%rbx), %rax
	movl	(%rax), %edi
	leaq	L_.str(%rip), %rsi
	movq	%rbx, %rdx
	callq	_dev_err
LBB0_20:
	movl	%r12d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_9:
	movq	8(%rbx), %rax
	movq	32(%rax), %rax
                                        ## kill: def $cl killed $cl killed $rcx
	sarq	%cl, %rax
	movq	%rax, 16(%rbx)
	cmpq	%rax, %r15
	jl	LBB0_11
	jmp	LBB0_12
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_GEM_DOMAIN_VRAM,8,3     ## @RADEON_GEM_DOMAIN_VRAM
	.comm	_PAGE_SHIFT,8,3                 ## @PAGE_SHIFT
	.comm	_TTM_PL_FLAG_NO_EVICT,4,2       ## @TTM_PL_FLAG_NO_EVICT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"%p pin failed\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_bo_pin_restricted       ; -- Begin function radeon_bo_pin_restricted
	.p2align	2
_radeon_bo_pin_restricted:              ; @radeon_bo_pin_restricted
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x3
	mov	x21, x2
	mov	x22, x1
	mov	x19, x0
	ldr	w8, [x0]
	cbz	w8, LBB0_5
; %bb.1:
	add	w8, w8, #1
	str	w8, [x19]
	cbz	x20, LBB0_3
; %bb.2:
	mov	x0, x19
	bl	_radeon_bo_gpu_offset
	str	x0, [x20]
LBB0_3:
	cbz	x21, LBB0_19
; %bb.4:
Lloh0:
	adrp	x8, _RADEON_GEM_DOMAIN_VRAM@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_GEM_DOMAIN_VRAM@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	ldr	x9, [x19, #8]
	mov	w10, #16
	mov	w11, #8
	cmp	x8, x22
	csel	x8, x11, x10, eq
	ldr	x20, [x9, x8]
	mov	x0, x19
	bl	_radeon_bo_gpu_offset
	sub	x8, x0, x20
	cmp	x8, x21
	cset	w0, gt
	bl	_WARN_ON_ONCE
	mov	w21, #0
	b	LBB0_19
LBB0_5:
	mov	x0, x19
	mov	x1, x22
	bl	_radeon_ttm_placement_from_domain
Lloh3:
	adrp	x8, _RADEON_GEM_DOMAIN_VRAM@GOTPAGE
Lloh4:
	ldr	x8, [x8, _RADEON_GEM_DOMAIN_VRAM@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x8]
Lloh6:
	adrp	x8, _PAGE_SHIFT@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PAGE_SHIFT@GOTPAGEOFF]
	cmp	x9, x22
	b.ne	LBB0_7
; %bb.6:
	ldr	x9, [x19, #8]
	ldr	x9, [x9, #24]
	ldr	x10, [x8]
	asr	x9, x9, x10
	str	x9, [x19, #16]
LBB0_7:
	cbz	x21, LBB0_11
; %bb.8:
	ldr	x10, [x8]
	asr	x8, x21, x10
	ldr	x9, [x19, #16]
	cbz	x9, LBB0_20
; %bb.9:
	cmp	x8, x9
	b.ge	LBB0_11
LBB0_10:
	str	x8, [x19, #16]
LBB0_11:
	ldr	w8, [x19, #24]
	cmp	w8, #1
	b.lt	LBB0_14
; %bb.12:
	mov	x8, #0
	ldr	x9, [x19, #40]
Lloh8:
	adrp	x10, _TTM_PL_FLAG_NO_EVICT@GOTPAGE
Lloh9:
	ldr	x10, [x10, _TTM_PL_FLAG_NO_EVICT@GOTPAGEOFF]
LBB0_13:                                ; =>This Inner Loop Header: Depth=1
	ldr	w11, [x10]
	lsl	x12, x8, #2
	ldr	w13, [x9, x12]
	orr	w11, w13, w11
	str	w11, [x9, x12]
	add	x8, x8, #1
	ldrsw	x11, [x19, #24]
	cmp	x8, x11
	b.lt	LBB0_13
LBB0_14:
	add	x1, x19, #16
	add	x0, x19, #32
	mov	w2, #0
	mov	w3, #0
	bl	_ttm_bo_validate
	mov	x21, x0
	cmp	w0, #0
	cset	w0, eq
	bl	_likely
	cbz	x0, LBB0_17
; %bb.15:
	mov	w8, #1
	str	w8, [x19]
	cbz	x20, LBB0_17
; %bb.16:
	mov	x0, x19
	bl	_radeon_bo_gpu_offset
	str	x0, [x20]
LBB0_17:
	cmp	w21, #0
	cset	w0, ne
	bl	_unlikely
	cbz	x0, LBB0_19
; %bb.18:
	ldr	x8, [x19, #8]
	ldr	w0, [x8]
Lloh10:
	adrp	x1, l_.str@PAGE
Lloh11:
	add	x1, x1, l_.str@PAGEOFF
	mov	x2, x19
	bl	_dev_err
LBB0_19:
	mov	x0, x21
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_20:
	ldr	x9, [x19, #8]
	ldr	x9, [x9, #32]
	asr	x9, x9, x10
	str	x9, [x19, #16]
	cmp	x8, x9
	b.lt	LBB0_10
	b	LBB0_11
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpAdd	Lloh10, Lloh11
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_GEM_DOMAIN_VRAM,8,3     ; @RADEON_GEM_DOMAIN_VRAM
	.comm	_PAGE_SHIFT,8,3                 ; @PAGE_SHIFT
	.comm	_TTM_PL_FLAG_NO_EVICT,4,2       ; @TTM_PL_FLAG_NO_EVICT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"%p pin failed\n"

.subsections_via_symbols
