	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function nv40_fifo_ctor
_nv40_fifo_ctor:                        ## @nv40_fifo_ctor
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%r9, %r12
	movq	%rdx, %r14
	movq	%rsi, %r13
	movq	%rdi, %rbx
	callq	_nv04_instmem
	movq	%rax, %r15
	leaq	-48(%rbp), %r9
	movq	%rbx, %rdi
	movq	%r13, %rsi
	movq	%r14, %rdx
	xorl	%ecx, %ecx
	movl	$31, %r8d
	callq	_nouveau_fifo_create
	movl	%eax, %r14d
	movq	-48(%rbp), %rdi
	callq	_nv_object
	movq	%rax, (%r12)
	testl	%r14d, %r14d
	jne	LBB0_2
## %bb.1:
	movl	8(%r15), %edi
	movq	-48(%rbp), %rsi
	addq	$20, %rsi
	callq	_nouveau_ramht_ref
	movl	4(%r15), %edi
	movq	-48(%rbp), %rsi
	addq	$16, %rsi
	callq	_nouveau_gpuobj_ref
	movl	(%r15), %edi
	movq	-48(%rbp), %rsi
	addq	$12, %rsi
	callq	_nouveau_gpuobj_ref
	movq	-48(%rbp), %rdi
	callq	_nv_subdev
	movl	$256, (%rax)                    ## imm = 0x100
	movq	_nv04_fifo_intr@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	-48(%rbp), %rdi
	callq	_nv_subdev
	movl	%ebx, 4(%rax)
	movq	-48(%rbp), %rdi
	callq	_nv_engine
	movq	_nv40_fifo_cclass@GOTPCREL(%rip), %rcx
	movq	%rcx, 8(%rax)
	movq	_nv40_fifo_sclass@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	-48(%rbp), %rdi
	callq	_nv_engine
	movl	%ebx, (%rax)
	movq	_nv04_fifo_pause@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	-48(%rbp), %rcx
	movl	%eax, 8(%rcx)
	movq	_nv04_fifo_start@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 4(%rcx)
	movq	_nv40_ramfc@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, (%rcx)
LBB0_2:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_nv04_fifo_intr,4,2             ## @nv04_fifo_intr
	.comm	_nv40_fifo_cclass,4,2           ## @nv40_fifo_cclass
	.comm	_nv40_fifo_sclass,4,2           ## @nv40_fifo_sclass
	.comm	_nv04_fifo_pause,4,2            ## @nv04_fifo_pause
	.comm	_nv04_fifo_start,4,2            ## @nv04_fifo_start
	.comm	_nv40_ramfc,4,2                 ## @nv40_ramfc
	.no_dead_strip	_nv40_fifo_ctor
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function nv40_fifo_ctor
_nv40_fifo_ctor:                        ; @nv40_fifo_ctor
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x21, x5
	mov	x19, x2
	mov	x22, x1
	mov	x23, x0
	bl	_nv04_instmem
	mov	x20, x0
	add	x5, sp, #8
	mov	x0, x23
	mov	x1, x22
	mov	x2, x19
	mov	w3, #0
	mov	w4, #31
	bl	_nouveau_fifo_create
	mov	x19, x0
	ldr	x0, [sp, #8]
	bl	_nv_object
	str	x0, [x21]
	cbnz	w19, LBB0_2
; %bb.1:
	ldr	w0, [x20, #8]
	ldr	x8, [sp, #8]
	add	x1, x8, #20
	bl	_nouveau_ramht_ref
	ldr	w0, [x20, #4]
	ldr	x8, [sp, #8]
	add	x1, x8, #16
	bl	_nouveau_gpuobj_ref
	ldr	w0, [x20]
	ldr	x8, [sp, #8]
	add	x1, x8, #12
	bl	_nouveau_gpuobj_ref
	ldr	x0, [sp, #8]
	bl	_nv_subdev
	mov	w8, #256
	str	w8, [x0]
Lloh0:
	adrp	x8, _nv04_fifo_intr@GOTPAGE
Lloh1:
	ldr	x8, [x8, _nv04_fifo_intr@GOTPAGEOFF]
Lloh2:
	ldr	w20, [x8]
	ldr	x0, [sp, #8]
	bl	_nv_subdev
	str	w20, [x0, #4]
	ldr	x0, [sp, #8]
	bl	_nv_engine
Lloh3:
	adrp	x8, _nv40_fifo_cclass@GOTPAGE
Lloh4:
	ldr	x8, [x8, _nv40_fifo_cclass@GOTPAGEOFF]
	str	x8, [x0, #8]
Lloh5:
	adrp	x8, _nv40_fifo_sclass@GOTPAGE
Lloh6:
	ldr	x8, [x8, _nv40_fifo_sclass@GOTPAGEOFF]
Lloh7:
	ldr	w20, [x8]
	ldr	x0, [sp, #8]
	bl	_nv_engine
Lloh8:
	adrp	x8, _nv04_fifo_pause@GOTPAGE
Lloh9:
	ldr	x8, [x8, _nv04_fifo_pause@GOTPAGEOFF]
	str	w20, [x0]
Lloh10:
	ldr	w8, [x8]
	ldr	x9, [sp, #8]
	str	w8, [x9, #8]
Lloh11:
	adrp	x8, _nv04_fifo_start@GOTPAGE
Lloh12:
	ldr	x8, [x8, _nv04_fifo_start@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
Lloh14:
	adrp	x10, _nv40_ramfc@GOTPAGE
Lloh15:
	ldr	x10, [x10, _nv40_ramfc@GOTPAGEOFF]
Lloh16:
	ldr	w10, [x10]
	stp	w10, w8, [x9]
LBB0_2:
	mov	x0, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_nv04_fifo_intr,4,2             ; @nv04_fifo_intr
	.comm	_nv40_fifo_cclass,4,2           ; @nv40_fifo_cclass
	.comm	_nv40_fifo_sclass,4,2           ; @nv40_fifo_sclass
	.comm	_nv04_fifo_pause,4,2            ; @nv04_fifo_pause
	.comm	_nv04_fifo_start,4,2            ; @nv04_fifo_start
	.comm	_nv40_ramfc,4,2                 ; @nv40_ramfc
	.no_dead_strip	_nv40_fifo_ctor
.subsections_via_symbols
