	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_get_crtc_scanoutpos     ## -- Begin function radeon_get_crtc_scanoutpos
	.p2align	4, 0x90
_radeon_get_crtc_scanoutpos:            ## @radeon_get_crtc_scanoutpos
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rcx, %rbx
	movq	%rdx, %r13
	movl	%esi, %r14d
	movq	(%rdi), %r12
	movq	%r12, %rdi
	callq	_ASIC_IS_DCE4
	testq	%rax, %rax
	je	LBB0_10
## %bb.1:
	cmpl	$5, %r14d
	ja	LBB0_25
## %bb.2:
	movl	%r14d, %eax
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	movq	%r12, -48(%rbp)                 ## 8-byte Spill
	jmpq	*%rax
LBB0_3:
	movq	_EVERGREEN_CRTC_V_BLANK_START_END@GOTPCREL(%rip), %rax
	movq	_EVERGREEN_CRTC0_REGISTER_OFFSET@GOTPCREL(%rip), %r12
	jmp	LBB0_4
LBB0_10:
	movq	%r12, %rdi
	callq	_ASIC_IS_AVIVO
	testq	%rax, %rax
	je	LBB0_17
## %bb.11:
	cmpl	$1, %r14d
	je	LBB0_16
## %bb.12:
	testl	%r14d, %r14d
	jne	LBB0_25
## %bb.13:
	movq	%r12, -48(%rbp)                 ## 8-byte Spill
	movq	_AVIVO_D1CRTC_V_BLANK_START_END@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %r15d
	movq	_AVIVO_D1CRTC_STATUS_POSITION@GOTPCREL(%rip), %rax
	jmp	LBB0_14
LBB0_17:
	cmpl	$1, %r14d
	je	LBB0_23
## %bb.18:
	testl	%r14d, %r14d
	jne	LBB0_25
## %bb.19:
	movq	%r12, -48(%rbp)                 ## 8-byte Spill
	movq	_RADEON_CRTC_V_TOTAL_DISP@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %r15d
	movq	_RADEON_CRTC_V_DISP@GOTPCREL(%rip), %rax
	andl	(%rax), %r15d
	movq	_RADEON_CRTC_V_DISP_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarl	%cl, %r15d
	movq	_RADEON_CRTC_VLINE_CRNT_VLINE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %r12d
	sarl	$16, %r12d
	movq	_RADEON_CRTC_V_TOTAL@GOTPCREL(%rip), %rax
	andl	(%rax), %r12d
	movq	_RADEON_CRTC_STATUS@GOTPCREL(%rip), %rax
	jmp	LBB0_20
LBB0_25:
	movl	$0, (%r13)
	movl	$0, (%rbx)
	xorl	%r8d, %r8d
	movl	$1, %eax
	jmp	LBB0_26
LBB0_5:
	movq	_EVERGREEN_CRTC_V_BLANK_START_END@GOTPCREL(%rip), %rax
	movq	_EVERGREEN_CRTC1_REGISTER_OFFSET@GOTPCREL(%rip), %r12
	jmp	LBB0_4
LBB0_6:
	movq	_EVERGREEN_CRTC_V_BLANK_START_END@GOTPCREL(%rip), %rax
	movq	_EVERGREEN_CRTC2_REGISTER_OFFSET@GOTPCREL(%rip), %r12
	jmp	LBB0_4
LBB0_7:
	movq	_EVERGREEN_CRTC_V_BLANK_START_END@GOTPCREL(%rip), %rax
	movq	_EVERGREEN_CRTC3_REGISTER_OFFSET@GOTPCREL(%rip), %r12
	jmp	LBB0_4
LBB0_8:
	movq	_EVERGREEN_CRTC_V_BLANK_START_END@GOTPCREL(%rip), %rax
	movq	_EVERGREEN_CRTC4_REGISTER_OFFSET@GOTPCREL(%rip), %r12
	jmp	LBB0_4
LBB0_9:
	movq	_EVERGREEN_CRTC_V_BLANK_START_END@GOTPCREL(%rip), %rax
	movq	_EVERGREEN_CRTC5_REGISTER_OFFSET@GOTPCREL(%rip), %r12
LBB0_4:
	movq	(%r12), %rdi
	addq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %r15d
	movq	_EVERGREEN_CRTC_STATUS_POSITION@GOTPCREL(%rip), %rax
	movq	(%r12), %rdi
	addq	(%rax), %rdi
	jmp	LBB0_15
LBB0_16:
	movq	%r12, -48(%rbp)                 ## 8-byte Spill
	movq	_AVIVO_D2CRTC_V_BLANK_START_END@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %r15d
	movq	_AVIVO_D2CRTC_STATUS_POSITION@GOTPCREL(%rip), %rax
LBB0_14:
	movq	(%rax), %rdi
LBB0_15:
	callq	_RREG32
	movl	%eax, %r12d
	movl	$1, %eax
LBB0_21:
	movq	_DRM_SCANOUTPOS_VALID@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r8d
	movl	%r12d, %edx
	andl	$8191, %edx                     ## imm = 0x1FFF
	movl	%edx, (%r13)
	shrl	$16, %r12d
	andl	$8191, %r12d                    ## imm = 0x1FFF
	movl	%r12d, (%rbx)
	testl	%r15d, %r15d
	jle	LBB0_22
## %bb.24:
	movq	_DRM_SCANOUTPOS_ACCURATE@GOTPCREL(%rip), %rdx
	orl	(%rdx), %r8d
	movl	%r15d, %edx
	andl	$8191, %edx                     ## imm = 0x1FFF
	shrl	$16, %r15d
	andl	$8191, %r15d                    ## imm = 0x1FFF
	movq	-48(%rbp), %r12                 ## 8-byte Reload
	jmp	LBB0_27
LBB0_22:
	movq	-48(%rbp), %r12                 ## 8-byte Reload
LBB0_26:
	movq	(%r12), %rdx
	movslq	%r14d, %rsi
	movq	(%rdx,%rsi,8), %rdx
	movl	(%rdx), %edx
	xorl	%r15d, %r15d
LBB0_27:
	movl	(%r13), %esi
	cmpl	%edx, %esi
	setl	%bl
	movl	%esi, %edi
	subl	%r15d, %edi
	setge	%cl
	testb	%cl, %bl
	jne	LBB0_32
## %bb.28:
	testl	%eax, %eax
	je	LBB0_32
## %bb.29:
	cmpl	%edx, %esi
	jl	LBB0_31
## %bb.30:
	movq	(%r12), %rax
	movslq	%r14d, %rcx
	movq	(%rax,%rcx,8), %rax
	subl	4(%rax), %esi
LBB0_31:
	subl	%r15d, %esi
	movl	%esi, (%r13)
	movq	_DRM_SCANOUTPOS_INVBL@GOTPCREL(%rip), %rax
	orl	(%rax), %r8d
	jmp	LBB0_33
LBB0_32:
	movl	%edi, (%r13)
LBB0_33:
	movl	%r8d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_23:
	movq	%r12, -48(%rbp)                 ## 8-byte Spill
	movq	_RADEON_CRTC2_V_TOTAL_DISP@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %r15d
	movq	_RADEON_CRTC_V_DISP@GOTPCREL(%rip), %rax
	andl	(%rax), %r15d
	movq	_RADEON_CRTC_V_DISP_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarl	%cl, %r15d
	movq	_RADEON_CRTC2_VLINE_CRNT_VLINE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %r12d
	sarl	$16, %r12d
	movq	_RADEON_CRTC_V_TOTAL@GOTPCREL(%rip), %rax
	andl	(%rax), %r12d
	movq	_RADEON_CRTC2_STATUS@GOTPCREL(%rip), %rax
LBB0_20:
	movq	(%rax), %rdi
	callq	_RREG32
	andl	$1, %eax
	jmp	LBB0_21
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_3, LBB0_3-LJTI0_0
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_6, LBB0_6-LJTI0_0
.set L0_0_set_7, LBB0_7-LJTI0_0
.set L0_0_set_8, LBB0_8-LJTI0_0
.set L0_0_set_9, LBB0_9-LJTI0_0
LJTI0_0:
	.long	L0_0_set_3
	.long	L0_0_set_5
	.long	L0_0_set_6
	.long	L0_0_set_7
	.long	L0_0_set_8
	.long	L0_0_set_9
	.end_data_region
                                        ## -- End function
	.comm	_EVERGREEN_CRTC_V_BLANK_START_END,8,3 ## @EVERGREEN_CRTC_V_BLANK_START_END
	.comm	_EVERGREEN_CRTC0_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC0_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC_STATUS_POSITION,8,3 ## @EVERGREEN_CRTC_STATUS_POSITION
	.comm	_DRM_SCANOUTPOS_VALID,4,2       ## @DRM_SCANOUTPOS_VALID
	.comm	_EVERGREEN_CRTC1_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC1_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC2_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC2_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC3_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC3_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC4_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC4_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC5_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC5_REGISTER_OFFSET
	.comm	_AVIVO_D1CRTC_V_BLANK_START_END,8,3 ## @AVIVO_D1CRTC_V_BLANK_START_END
	.comm	_AVIVO_D1CRTC_STATUS_POSITION,8,3 ## @AVIVO_D1CRTC_STATUS_POSITION
	.comm	_AVIVO_D2CRTC_V_BLANK_START_END,8,3 ## @AVIVO_D2CRTC_V_BLANK_START_END
	.comm	_AVIVO_D2CRTC_STATUS_POSITION,8,3 ## @AVIVO_D2CRTC_STATUS_POSITION
	.comm	_RADEON_CRTC_V_TOTAL_DISP,8,3   ## @RADEON_CRTC_V_TOTAL_DISP
	.comm	_RADEON_CRTC_V_DISP,4,2         ## @RADEON_CRTC_V_DISP
	.comm	_RADEON_CRTC_V_DISP_SHIFT,4,2   ## @RADEON_CRTC_V_DISP_SHIFT
	.comm	_RADEON_CRTC_VLINE_CRNT_VLINE,8,3 ## @RADEON_CRTC_VLINE_CRNT_VLINE
	.comm	_RADEON_CRTC_V_TOTAL,4,2        ## @RADEON_CRTC_V_TOTAL
	.comm	_RADEON_CRTC_STATUS,8,3         ## @RADEON_CRTC_STATUS
	.comm	_RADEON_CRTC2_V_TOTAL_DISP,8,3  ## @RADEON_CRTC2_V_TOTAL_DISP
	.comm	_RADEON_CRTC2_VLINE_CRNT_VLINE,8,3 ## @RADEON_CRTC2_VLINE_CRNT_VLINE
	.comm	_RADEON_CRTC2_STATUS,8,3        ## @RADEON_CRTC2_STATUS
	.comm	_DRM_SCANOUTPOS_ACCURATE,4,2    ## @DRM_SCANOUTPOS_ACCURATE
	.comm	_DRM_SCANOUTPOS_INVBL,4,2       ## @DRM_SCANOUTPOS_INVBL
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_get_crtc_scanoutpos     ; -- Begin function radeon_get_crtc_scanoutpos
	.p2align	2
_radeon_get_crtc_scanoutpos:            ; @radeon_get_crtc_scanoutpos
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x22, x3
	mov	x19, x2
	mov	x20, x1
	ldr	x21, [x0]
	mov	x0, x21
	bl	_ASIC_IS_DCE4
	cbz	x0, LBB0_4
; %bb.1:
	cmp	w20, #5
	b.hi	LBB0_11
; %bb.2:
	mov	w8, w20
Lloh0:
	adrp	x9, lJTI0_0@PAGE
Lloh1:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_3
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_3:
Lloh2:
	adrp	x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGE
Lloh3:
	ldr	x8, [x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGEOFF]
Lloh4:
	ldr	x8, [x8]
Lloh5:
	adrp	x24, _EVERGREEN_CRTC0_REGISTER_OFFSET@GOTPAGE
Lloh6:
	ldr	x24, [x24, _EVERGREEN_CRTC0_REGISTER_OFFSET@GOTPAGEOFF]
	b	LBB0_17
LBB0_4:
	mov	x0, x21
	bl	_ASIC_IS_AVIVO
	cmp	w20, #1
	cbz	x0, LBB0_8
; %bb.5:
	b.eq	LBB0_18
; %bb.6:
	cbnz	w20, LBB0_11
; %bb.7:
Lloh7:
	adrp	x8, _AVIVO_D1CRTC_V_BLANK_START_END@GOTPAGE
Lloh8:
	ldr	x8, [x8, _AVIVO_D1CRTC_V_BLANK_START_END@GOTPAGEOFF]
Lloh9:
	ldr	x0, [x8]
	bl	_RREG32
	mov	x23, x0
Lloh10:
	adrp	x8, _AVIVO_D1CRTC_STATUS_POSITION@GOTPAGE
Lloh11:
	ldr	x8, [x8, _AVIVO_D1CRTC_STATUS_POSITION@GOTPAGEOFF]
	b	LBB0_19
LBB0_8:
	b.eq	LBB0_30
; %bb.9:
	cbnz	w20, LBB0_11
; %bb.10:
Lloh12:
	adrp	x8, _RADEON_CRTC_V_TOTAL_DISP@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RADEON_CRTC_V_TOTAL_DISP@GOTPAGEOFF]
Lloh14:
	ldr	x0, [x8]
	bl	_RREG32
Lloh15:
	adrp	x8, _RADEON_CRTC_V_DISP@GOTPAGE
Lloh16:
	ldr	x8, [x8, _RADEON_CRTC_V_DISP@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
Lloh18:
	adrp	x9, _RADEON_CRTC_V_DISP_SHIFT@GOTPAGE
Lloh19:
	ldr	x9, [x9, _RADEON_CRTC_V_DISP_SHIFT@GOTPAGEOFF]
	and	w8, w8, w0
Lloh20:
	ldr	w9, [x9]
	asr	w23, w8, w9
Lloh21:
	adrp	x8, _RADEON_CRTC_VLINE_CRNT_VLINE@GOTPAGE
Lloh22:
	ldr	x8, [x8, _RADEON_CRTC_VLINE_CRNT_VLINE@GOTPAGEOFF]
Lloh23:
	ldr	x0, [x8]
	bl	_RREG32
Lloh24:
	adrp	x8, _RADEON_CRTC_V_TOTAL@GOTPAGE
Lloh25:
	ldr	x8, [x8, _RADEON_CRTC_V_TOTAL@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	and	w24, w8, w0, asr #16
Lloh27:
	adrp	x8, _RADEON_CRTC_STATUS@GOTPAGE
Lloh28:
	ldr	x8, [x8, _RADEON_CRTC_STATUS@GOTPAGEOFF]
	b	LBB0_31
LBB0_11:
	mov	w0, #0
	str	wzr, [x19]
	str	wzr, [x22]
	mov	w8, #1
	b	LBB0_23
LBB0_12:
Lloh29:
	adrp	x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGE
Lloh30:
	ldr	x8, [x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGEOFF]
Lloh31:
	ldr	x8, [x8]
Lloh32:
	adrp	x24, _EVERGREEN_CRTC1_REGISTER_OFFSET@GOTPAGE
Lloh33:
	ldr	x24, [x24, _EVERGREEN_CRTC1_REGISTER_OFFSET@GOTPAGEOFF]
	b	LBB0_17
LBB0_13:
Lloh34:
	adrp	x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGE
Lloh35:
	ldr	x8, [x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGEOFF]
Lloh36:
	ldr	x8, [x8]
Lloh37:
	adrp	x24, _EVERGREEN_CRTC2_REGISTER_OFFSET@GOTPAGE
Lloh38:
	ldr	x24, [x24, _EVERGREEN_CRTC2_REGISTER_OFFSET@GOTPAGEOFF]
	b	LBB0_17
LBB0_14:
Lloh39:
	adrp	x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGE
Lloh40:
	ldr	x8, [x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGEOFF]
Lloh41:
	ldr	x8, [x8]
Lloh42:
	adrp	x24, _EVERGREEN_CRTC3_REGISTER_OFFSET@GOTPAGE
Lloh43:
	ldr	x24, [x24, _EVERGREEN_CRTC3_REGISTER_OFFSET@GOTPAGEOFF]
	b	LBB0_17
LBB0_15:
Lloh44:
	adrp	x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGE
Lloh45:
	ldr	x8, [x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGEOFF]
Lloh46:
	ldr	x8, [x8]
Lloh47:
	adrp	x24, _EVERGREEN_CRTC4_REGISTER_OFFSET@GOTPAGE
Lloh48:
	ldr	x24, [x24, _EVERGREEN_CRTC4_REGISTER_OFFSET@GOTPAGEOFF]
	b	LBB0_17
LBB0_16:
Lloh49:
	adrp	x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGE
Lloh50:
	ldr	x8, [x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGEOFF]
Lloh51:
	ldr	x8, [x8]
Lloh52:
	adrp	x24, _EVERGREEN_CRTC5_REGISTER_OFFSET@GOTPAGE
Lloh53:
	ldr	x24, [x24, _EVERGREEN_CRTC5_REGISTER_OFFSET@GOTPAGEOFF]
LBB0_17:
	ldr	x9, [x24]
	add	x0, x9, x8
	bl	_RREG32
	mov	x23, x0
Lloh54:
	adrp	x8, _EVERGREEN_CRTC_STATUS_POSITION@GOTPAGE
Lloh55:
	ldr	x8, [x8, _EVERGREEN_CRTC_STATUS_POSITION@GOTPAGEOFF]
Lloh56:
	ldr	x8, [x8]
	ldr	x9, [x24]
	add	x0, x9, x8
	b	LBB0_20
LBB0_18:
Lloh57:
	adrp	x8, _AVIVO_D2CRTC_V_BLANK_START_END@GOTPAGE
Lloh58:
	ldr	x8, [x8, _AVIVO_D2CRTC_V_BLANK_START_END@GOTPAGEOFF]
Lloh59:
	ldr	x0, [x8]
	bl	_RREG32
	mov	x23, x0
Lloh60:
	adrp	x8, _AVIVO_D2CRTC_STATUS_POSITION@GOTPAGE
Lloh61:
	ldr	x8, [x8, _AVIVO_D2CRTC_STATUS_POSITION@GOTPAGEOFF]
LBB0_19:
	ldr	x0, [x8]
LBB0_20:
	bl	_RREG32
	mov	x24, x0
	mov	w8, #1
LBB0_21:
Lloh62:
	adrp	x9, _DRM_SCANOUTPOS_VALID@GOTPAGE
Lloh63:
	ldr	x9, [x9, _DRM_SCANOUTPOS_VALID@GOTPAGEOFF]
Lloh64:
	ldr	w0, [x9]
	and	w9, w24, #0x1fff
	str	w9, [x19]
	ubfx	w9, w24, #16, #13
	str	w9, [x22]
	cmp	w23, #1
	b.lt	LBB0_23
; %bb.22:
Lloh65:
	adrp	x9, _DRM_SCANOUTPOS_ACCURATE@GOTPAGE
Lloh66:
	ldr	x9, [x9, _DRM_SCANOUTPOS_ACCURATE@GOTPAGEOFF]
Lloh67:
	ldr	w9, [x9]
	orr	w0, w9, w0
	and	w10, w23, #0x1fff
	ubfx	w9, w23, #16, #13
	b	LBB0_24
LBB0_23:
	mov	w9, #0
	ldr	x10, [x21]
	ldr	x10, [x10, w20, sxtw #3]
	ldr	w10, [x10]
LBB0_24:
	ldr	w11, [x19]
	subs	w12, w11, w9
	ccmp	w11, w10, #0, ge
	ccmp	w8, #0, #4, ge
	b.ne	LBB0_26
; %bb.25:
	str	w12, [x19]
	b	LBB0_29
LBB0_26:
	cmp	w11, w10
	b.lt	LBB0_28
; %bb.27:
	ldr	x8, [x21]
	ldr	x8, [x8, w20, sxtw #3]
	ldr	w8, [x8, #4]
	sub	w11, w11, w8
LBB0_28:
	sub	w8, w11, w9
	str	w8, [x19]
Lloh68:
	adrp	x8, _DRM_SCANOUTPOS_INVBL@GOTPAGE
Lloh69:
	ldr	x8, [x8, _DRM_SCANOUTPOS_INVBL@GOTPAGEOFF]
Lloh70:
	ldr	w8, [x8]
	orr	w0, w8, w0
LBB0_29:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_30:
Lloh71:
	adrp	x8, _RADEON_CRTC2_V_TOTAL_DISP@GOTPAGE
Lloh72:
	ldr	x8, [x8, _RADEON_CRTC2_V_TOTAL_DISP@GOTPAGEOFF]
Lloh73:
	ldr	x0, [x8]
	bl	_RREG32
Lloh74:
	adrp	x8, _RADEON_CRTC_V_DISP@GOTPAGE
Lloh75:
	ldr	x8, [x8, _RADEON_CRTC_V_DISP@GOTPAGEOFF]
Lloh76:
	ldr	w8, [x8]
Lloh77:
	adrp	x9, _RADEON_CRTC_V_DISP_SHIFT@GOTPAGE
Lloh78:
	ldr	x9, [x9, _RADEON_CRTC_V_DISP_SHIFT@GOTPAGEOFF]
	and	w8, w8, w0
Lloh79:
	ldr	w9, [x9]
	asr	w23, w8, w9
Lloh80:
	adrp	x8, _RADEON_CRTC2_VLINE_CRNT_VLINE@GOTPAGE
Lloh81:
	ldr	x8, [x8, _RADEON_CRTC2_VLINE_CRNT_VLINE@GOTPAGEOFF]
Lloh82:
	ldr	x0, [x8]
	bl	_RREG32
Lloh83:
	adrp	x8, _RADEON_CRTC_V_TOTAL@GOTPAGE
Lloh84:
	ldr	x8, [x8, _RADEON_CRTC_V_TOTAL@GOTPAGEOFF]
Lloh85:
	ldr	w8, [x8]
	and	w24, w8, w0, asr #16
Lloh86:
	adrp	x8, _RADEON_CRTC2_STATUS@GOTPAGE
Lloh87:
	ldr	x8, [x8, _RADEON_CRTC2_STATUS@GOTPAGEOFF]
LBB0_31:
	ldr	x0, [x8]
	bl	_RREG32
	and	w8, w0, #0x1
	b	LBB0_21
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGot	Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_3-LBB0_3)>>2
	.byte	(LBB0_12-LBB0_3)>>2
	.byte	(LBB0_13-LBB0_3)>>2
	.byte	(LBB0_14-LBB0_3)>>2
	.byte	(LBB0_15-LBB0_3)>>2
	.byte	(LBB0_16-LBB0_3)>>2
                                        ; -- End function
	.comm	_EVERGREEN_CRTC_V_BLANK_START_END,8,3 ; @EVERGREEN_CRTC_V_BLANK_START_END
	.comm	_EVERGREEN_CRTC0_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC0_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC_STATUS_POSITION,8,3 ; @EVERGREEN_CRTC_STATUS_POSITION
	.comm	_DRM_SCANOUTPOS_VALID,4,2       ; @DRM_SCANOUTPOS_VALID
	.comm	_EVERGREEN_CRTC1_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC1_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC2_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC2_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC3_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC3_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC4_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC4_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC5_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC5_REGISTER_OFFSET
	.comm	_AVIVO_D1CRTC_V_BLANK_START_END,8,3 ; @AVIVO_D1CRTC_V_BLANK_START_END
	.comm	_AVIVO_D1CRTC_STATUS_POSITION,8,3 ; @AVIVO_D1CRTC_STATUS_POSITION
	.comm	_AVIVO_D2CRTC_V_BLANK_START_END,8,3 ; @AVIVO_D2CRTC_V_BLANK_START_END
	.comm	_AVIVO_D2CRTC_STATUS_POSITION,8,3 ; @AVIVO_D2CRTC_STATUS_POSITION
	.comm	_RADEON_CRTC_V_TOTAL_DISP,8,3   ; @RADEON_CRTC_V_TOTAL_DISP
	.comm	_RADEON_CRTC_V_DISP,4,2         ; @RADEON_CRTC_V_DISP
	.comm	_RADEON_CRTC_V_DISP_SHIFT,4,2   ; @RADEON_CRTC_V_DISP_SHIFT
	.comm	_RADEON_CRTC_VLINE_CRNT_VLINE,8,3 ; @RADEON_CRTC_VLINE_CRNT_VLINE
	.comm	_RADEON_CRTC_V_TOTAL,4,2        ; @RADEON_CRTC_V_TOTAL
	.comm	_RADEON_CRTC_STATUS,8,3         ; @RADEON_CRTC_STATUS
	.comm	_RADEON_CRTC2_V_TOTAL_DISP,8,3  ; @RADEON_CRTC2_V_TOTAL_DISP
	.comm	_RADEON_CRTC2_VLINE_CRNT_VLINE,8,3 ; @RADEON_CRTC2_VLINE_CRNT_VLINE
	.comm	_RADEON_CRTC2_STATUS,8,3        ; @RADEON_CRTC2_STATUS
	.comm	_DRM_SCANOUTPOS_ACCURATE,4,2    ; @DRM_SCANOUTPOS_ACCURATE
	.comm	_DRM_SCANOUTPOS_INVBL,4,2       ; @DRM_SCANOUTPOS_INVBL
.subsections_via_symbols
