	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_do_pixcache_flush
_radeon_do_pixcache_flush:              ## @radeon_do_pixcache_flush
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_RADEON_BOX_WAIT_IDLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, 8(%rdi)
	movq	_RADEON_FAMILY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%rdi), %eax
	movq	_CHIP_RV280@GOTPCREL(%rip), %rcx
	xorl	%r14d, %r14d
	cmpl	(%rcx), %eax
	jg	LBB0_6
## %bb.1:
	movq	%rdi, %r13
	movq	_RADEON_RB3D_DSTCACHE_CTLSTAT@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RADEON_READ
	movq	_RADEON_RB3D_DC_FLUSH_ALL@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r15), %edi
	movl	%eax, %esi
	callq	_RADEON_WRITE
	cmpl	$0, 4(%r13)
	jle	LBB0_5
## %bb.2:
	xorl	%r14d, %r14d
	movq	_RADEON_RB3D_DC_BUSY@GOTPCREL(%rip), %r12
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r15), %edi
	callq	_RADEON_READ
	testl	%eax, (%r12)
	je	LBB0_6
## %bb.4:                               ##   in Loop: Header=BB0_3 Depth=1
	movl	$1, %edi
	callq	_DRM_UDELAY
	incl	%ebx
	cmpl	4(%r13), %ebx
	jl	LBB0_3
LBB0_5:
	movq	_EBUSY@GOTPCREL(%rip), %rax
	xorl	%r14d, %r14d
	subl	(%rax), %r14d
LBB0_6:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_BOX_WAIT_IDLE,4,2       ## @RADEON_BOX_WAIT_IDLE
	.comm	_RADEON_FAMILY_MASK,4,2         ## @RADEON_FAMILY_MASK
	.comm	_CHIP_RV280,4,2                 ## @CHIP_RV280
	.comm	_RADEON_RB3D_DSTCACHE_CTLSTAT,4,2 ## @RADEON_RB3D_DSTCACHE_CTLSTAT
	.comm	_RADEON_RB3D_DC_FLUSH_ALL,4,2   ## @RADEON_RB3D_DC_FLUSH_ALL
	.comm	_RADEON_RB3D_DC_BUSY,4,2        ## @RADEON_RB3D_DC_BUSY
	.comm	_EBUSY,4,2                      ## @EBUSY
	.no_dead_strip	_radeon_do_pixcache_flush
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_do_pixcache_flush
_radeon_do_pixcache_flush:              ; @radeon_do_pixcache_flush
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
Lloh0:
	adrp	x8, _RADEON_BOX_WAIT_IDLE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_BOX_WAIT_IDLE@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	ldr	w9, [x0, #8]
	orr	w8, w9, w8
	str	w8, [x0, #8]
	ldr	w8, [x0]
Lloh3:
	adrp	x9, _RADEON_FAMILY_MASK@GOTPAGE
Lloh4:
	ldr	x9, [x9, _RADEON_FAMILY_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	and	w8, w9, w8
Lloh6:
	adrp	x9, _CHIP_RV280@GOTPAGE
Lloh7:
	ldr	x9, [x9, _CHIP_RV280@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	cmp	w8, w9
	b.le	LBB0_2
LBB0_1:
	mov	w0, #0
	b	LBB0_7
LBB0_2:
	mov	x19, x0
Lloh9:
	adrp	x20, _RADEON_RB3D_DSTCACHE_CTLSTAT@GOTPAGE
Lloh10:
	ldr	x20, [x20, _RADEON_RB3D_DSTCACHE_CTLSTAT@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RADEON_READ
Lloh11:
	adrp	x8, _RADEON_RB3D_DC_FLUSH_ALL@GOTPAGE
Lloh12:
	ldr	x8, [x8, _RADEON_RB3D_DC_FLUSH_ALL@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x20]
	bl	_RADEON_WRITE
	ldr	w8, [x19, #4]
	cmp	w8, #1
	b.lt	LBB0_6
; %bb.3:
	mov	w21, #0
Lloh14:
	adrp	x22, _RADEON_RB3D_DC_BUSY@GOTPAGE
Lloh15:
	ldr	x22, [x22, _RADEON_RB3D_DC_BUSY@GOTPAGEOFF]
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x20]
	bl	_RADEON_READ
	ldr	w8, [x22]
	tst	w8, w0
	b.eq	LBB0_1
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	mov	w0, #1
	bl	_DRM_UDELAY
	add	w21, w21, #1
	ldr	w8, [x19, #4]
	cmp	w21, w8
	b.lt	LBB0_4
LBB0_6:
Lloh16:
	adrp	x8, _EBUSY@GOTPAGE
Lloh17:
	ldr	x8, [x8, _EBUSY@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_7:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_BOX_WAIT_IDLE,4,2       ; @RADEON_BOX_WAIT_IDLE
	.comm	_RADEON_FAMILY_MASK,4,2         ; @RADEON_FAMILY_MASK
	.comm	_CHIP_RV280,4,2                 ; @CHIP_RV280
	.comm	_RADEON_RB3D_DSTCACHE_CTLSTAT,4,2 ; @RADEON_RB3D_DSTCACHE_CTLSTAT
	.comm	_RADEON_RB3D_DC_FLUSH_ALL,4,2   ; @RADEON_RB3D_DC_FLUSH_ALL
	.comm	_RADEON_RB3D_DC_BUSY,4,2        ; @RADEON_RB3D_DC_BUSY
	.comm	_EBUSY,4,2                      ; @EBUSY
	.no_dead_strip	_radeon_do_pixcache_flush
.subsections_via_symbols
