	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_init_pipes
_radeon_init_pipes:                     ## @radeon_init_pipes
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	8(%rdi), %r14
	movq	_RADEON_FAMILY_MASK@GOTPCREL(%rip), %r13
	movl	(%r13), %eax
	andl	(%r14), %eax
	movq	_CHIP_RV530@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_3
## %bb.1:
	movq	_RV530_GB_PIPE_SELECT2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RADEON_READ
	notl	%eax
	testb	$3, %al
	jne	LBB0_3
## %bb.2:
	movl	$2, 4(%r14)
	jmp	LBB0_4
LBB0_3:
	movl	$1, 4(%r14)
LBB0_4:
	movl	(%r13), %eax
	andl	(%r14), %eax
	movq	_CHIP_R420@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jge	LBB0_5
## %bb.8:
	movq	_CHIP_R300@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_10
## %bb.9:
	movq	(%r15), %rcx
	cmpl	$16708, (%rcx)                  ## imm = 0x4144
	jne	LBB0_12
LBB0_10:
	movq	_CHIP_R350@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_13
## %bb.11:
	movq	(%r15), %rax
	cmpl	$16712, (%rax)                  ## imm = 0x4148
	jne	LBB0_12
LBB0_13:
	movl	$1, 8(%r14)
	xorl	%r12d, %r12d
	jmp	LBB0_14
LBB0_5:
	movq	_R400_GB_PIPE_SELECT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RADEON_READ
	movl	%eax, %r12d
	movl	%eax, %esi
	shrl	$12, %esi
	andl	$3, %esi
	incl	%esi
	movl	%esi, 8(%r14)
	movq	(%r15), %rax
	movl	(%rax), %eax
	cmpl	$24143, %eax                    ## imm = 0x5E4F
	je	LBB0_7
## %bb.6:
	cmpl	$24140, %eax                    ## imm = 0x5E4C
	jne	LBB0_15
LBB0_7:
	movl	$1, 8(%r14)
LBB0_14:
	movl	$1, %esi
	jmp	LBB0_15
LBB0_12:
	movl	$2, 8(%r14)
	xorl	%r12d, %r12d
	movl	$2, %esi
LBB0_15:
	leaq	L_.str(%rip), %rdi
	callq	_DRM_INFO
	movq	_R300_ENABLE_TILING@GOTPCREL(%rip), %rax
	movq	_R300_TILE_SIZE_16@GOTPCREL(%rip), %rcx
	movl	8(%r14), %edx
	addl	$-2, %edx
	cmpl	$2, %edx
	ja	LBB0_16
## %bb.17:
	movslq	%edx, %rdx
	leaq	l_switch.table.radeon_init_pipes(%rip), %rsi
	movq	(%rsi,%rdx,8), %rdx
	jmp	LBB0_18
LBB0_16:
	movq	_R300_PIPE_COUNT_RV350@GOTPCREL(%rip), %rdx
LBB0_18:
	movl	(%rax), %r15d
	movl	(%rcx), %ebx
	movl	(%r13), %eax
	andl	(%r14), %eax
	movl	(%rdx), %r13d
	movq	_CHIP_RV515@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jl	LBB0_20
## %bb.19:
	movq	_R500_DYN_SCLK_PWMEM_PIPE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	shrl	$4, %r12d
	andl	$240, %r12d
	orl	$1, %r12d
	movl	%r12d, %esi
	callq	_RADEON_WRITE_PLL
	movq	_R300_SU_REG_DEST@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movb	8(%r14), %cl
	movl	$-1, %esi
	shll	%cl, %esi
	notl	%esi
	callq	_RADEON_WRITE
LBB0_20:
	orl	%r15d, %ebx
	orl	%r13d, %ebx
	movq	_R300_GB_TILE_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_RADEON_WRITE
	movq	%r14, %rdi
	callq	_radeon_do_wait_for_idle
	movq	_R300_DST_PIPE_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%ebx, %edi
	callq	_RADEON_READ
	movq	_R300_PIPE_AUTO_CONFIG@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_RADEON_WRITE
	movq	_R300_RB2D_DSTCACHE_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%ebx, %edi
	callq	_RADEON_READ
	movq	_R300_DC_AUTOFLUSH_ENABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_DC_DC_DISABLE_IGNORE_PE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%ebx, %edi
	movl	%eax, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_RADEON_WRITE                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_FAMILY_MASK,4,2         ## @RADEON_FAMILY_MASK
	.comm	_CHIP_RV530,4,2                 ## @CHIP_RV530
	.comm	_RV530_GB_PIPE_SELECT2,4,2      ## @RV530_GB_PIPE_SELECT2
	.comm	_CHIP_R420,4,2                  ## @CHIP_R420
	.comm	_R400_GB_PIPE_SELECT,4,2        ## @R400_GB_PIPE_SELECT
	.comm	_CHIP_R300,4,2                  ## @CHIP_R300
	.comm	_CHIP_R350,4,2                  ## @CHIP_R350
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Num pipes: %d\n"

	.comm	_R300_ENABLE_TILING,4,2         ## @R300_ENABLE_TILING
	.comm	_R300_TILE_SIZE_16,4,2          ## @R300_TILE_SIZE_16
	.comm	_R300_PIPE_COUNT_R300,4,2       ## @R300_PIPE_COUNT_R300
	.comm	_R300_PIPE_COUNT_R420_3P,4,2    ## @R300_PIPE_COUNT_R420_3P
	.comm	_R300_PIPE_COUNT_R420,4,2       ## @R300_PIPE_COUNT_R420
	.comm	_R300_PIPE_COUNT_RV350,4,2      ## @R300_PIPE_COUNT_RV350
	.comm	_CHIP_RV515,4,2                 ## @CHIP_RV515
	.comm	_R500_DYN_SCLK_PWMEM_PIPE,4,2   ## @R500_DYN_SCLK_PWMEM_PIPE
	.comm	_R300_SU_REG_DEST,4,2           ## @R300_SU_REG_DEST
	.comm	_R300_GB_TILE_CONFIG,4,2        ## @R300_GB_TILE_CONFIG
	.comm	_R300_DST_PIPE_CONFIG,4,2       ## @R300_DST_PIPE_CONFIG
	.comm	_R300_PIPE_AUTO_CONFIG,4,2      ## @R300_PIPE_AUTO_CONFIG
	.comm	_R300_RB2D_DSTCACHE_MODE,4,2    ## @R300_RB2D_DSTCACHE_MODE
	.comm	_R300_DC_AUTOFLUSH_ENABLE,4,2   ## @R300_DC_AUTOFLUSH_ENABLE
	.comm	_R300_DC_DC_DISABLE_IGNORE_PE,4,2 ## @R300_DC_DC_DISABLE_IGNORE_PE
	.no_dead_strip	_radeon_init_pipes
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.radeon_init_pipes
l_switch.table.radeon_init_pipes:
	.quad	_R300_PIPE_COUNT_R300
	.quad	_R300_PIPE_COUNT_R420_3P
	.quad	_R300_PIPE_COUNT_R420

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_init_pipes
_radeon_init_pipes:                     ; @radeon_init_pipes
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x21, x0
	ldr	x19, [x0, #8]
	ldr	w8, [x19]
Lloh0:
	adrp	x22, _RADEON_FAMILY_MASK@GOTPAGE
Lloh1:
	ldr	x22, [x22, _RADEON_FAMILY_MASK@GOTPAGEOFF]
	ldr	w9, [x22]
	and	w8, w9, w8
Lloh2:
	adrp	x9, _CHIP_RV530@GOTPAGE
Lloh3:
	ldr	x9, [x9, _CHIP_RV530@GOTPAGEOFF]
Lloh4:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_3
; %bb.1:
Lloh5:
	adrp	x8, _RV530_GB_PIPE_SELECT2@GOTPAGE
Lloh6:
	ldr	x8, [x8, _RV530_GB_PIPE_SELECT2@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
	bl	_RADEON_READ
	mvn	w8, w0
	tst	w8, #0x3
	b.ne	LBB0_3
; %bb.2:
	mov	w8, #2
	b	LBB0_4
LBB0_3:
	mov	w8, #1
LBB0_4:
	str	w8, [x19, #4]
	ldr	w8, [x19]
	ldr	w9, [x22]
	and	w8, w9, w8
Lloh8:
	adrp	x9, _CHIP_R420@GOTPAGE
Lloh9:
	ldr	x9, [x9, _CHIP_R420@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ge	LBB0_10
; %bb.5:
Lloh11:
	adrp	x9, _CHIP_R300@GOTPAGE
Lloh12:
	ldr	x9, [x9, _CHIP_R300@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_7
; %bb.6:
	ldr	x9, [x21]
	ldr	w9, [x9]
	mov	w10, #16708
	cmp	w9, w10
	b.ne	LBB0_12
LBB0_7:
Lloh14:
	adrp	x9, _CHIP_R350@GOTPAGE
Lloh15:
	ldr	x9, [x9, _CHIP_R350@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_9
; %bb.8:
	ldr	x8, [x21]
	ldr	w8, [x8]
	mov	w9, #16712
	cmp	w8, w9
	b.ne	LBB0_12
LBB0_9:
	mov	w20, #0
	b	LBB0_11
LBB0_10:
Lloh17:
	adrp	x8, _R400_GB_PIPE_SELECT@GOTPAGE
Lloh18:
	ldr	x8, [x8, _R400_GB_PIPE_SELECT@GOTPAGEOFF]
Lloh19:
	ldr	w0, [x8]
	bl	_RADEON_READ
	mov	x20, x0
	ubfx	w8, w0, #12, #2
	add	w1, w8, #1
	str	w1, [x19, #8]
	ldr	x8, [x21]
	ldr	w8, [x8]
	mov	w9, #24143
	cmp	w8, w9
	mov	w9, #24140
	ccmp	w8, w9, #4, ne
	b.ne	LBB0_14
LBB0_11:
	mov	w1, #1
	b	LBB0_13
LBB0_12:
	mov	w20, #0
	mov	w1, #2
LBB0_13:
	str	w1, [x19, #8]
LBB0_14:
Lloh20:
	adrp	x0, l_.str@PAGE
Lloh21:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_INFO
Lloh22:
	adrp	x8, _R300_ENABLE_TILING@GOTPAGE
Lloh23:
	ldr	x8, [x8, _R300_ENABLE_TILING@GOTPAGEOFF]
Lloh24:
	adrp	x9, _R300_TILE_SIZE_16@GOTPAGE
Lloh25:
	ldr	x9, [x9, _R300_TILE_SIZE_16@GOTPAGEOFF]
	ldr	w10, [x19, #8]
	sub	w10, w10, #2
	cmp	w10, #2
	b.hi	LBB0_16
; %bb.15:
Lloh26:
	adrp	x11, l_switch.table.radeon_init_pipes@PAGE
Lloh27:
	add	x11, x11, l_switch.table.radeon_init_pipes@PAGEOFF
	ldr	x10, [x11, w10, sxtw #3]
	b	LBB0_17
LBB0_16:
Lloh28:
	adrp	x10, _R300_PIPE_COUNT_RV350@GOTPAGE
Lloh29:
	ldr	x10, [x10, _R300_PIPE_COUNT_RV350@GOTPAGEOFF]
LBB0_17:
	ldr	w21, [x8]
	ldr	w23, [x9]
	ldr	w24, [x10]
	ldr	w8, [x19]
	ldr	w9, [x22]
	and	w8, w9, w8
Lloh30:
	adrp	x9, _CHIP_RV515@GOTPAGE
Lloh31:
	ldr	x9, [x9, _CHIP_RV515@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	cmp	w8, w9
	b.lt	LBB0_19
; %bb.18:
Lloh33:
	adrp	x8, _R500_DYN_SCLK_PWMEM_PIPE@GOTPAGE
Lloh34:
	ldr	x8, [x8, _R500_DYN_SCLK_PWMEM_PIPE@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	lsr	w8, w20, #4
	and	w8, w8, #0xf0
	orr	w1, w8, #0x1
	bl	_RADEON_WRITE_PLL
Lloh36:
	adrp	x8, _R300_SU_REG_DEST@GOTPAGE
Lloh37:
	ldr	x8, [x8, _R300_SU_REG_DEST@GOTPAGEOFF]
Lloh38:
	ldr	w0, [x8]
	ldr	w8, [x19, #8]
	mov	w9, #-1
	lsl	w8, w9, w8
	mvn	w1, w8
	bl	_RADEON_WRITE
LBB0_19:
	orr	w8, w23, w21
	orr	w1, w8, w24
Lloh39:
	adrp	x8, _R300_GB_TILE_CONFIG@GOTPAGE
Lloh40:
	ldr	x8, [x8, _R300_GB_TILE_CONFIG@GOTPAGEOFF]
Lloh41:
	ldr	w0, [x8]
	bl	_RADEON_WRITE
	mov	x0, x19
	bl	_radeon_do_wait_for_idle
Lloh42:
	adrp	x8, _R300_DST_PIPE_CONFIG@GOTPAGE
Lloh43:
	ldr	x8, [x8, _R300_DST_PIPE_CONFIG@GOTPAGEOFF]
Lloh44:
	ldr	w19, [x8]
	mov	x0, x19
	bl	_RADEON_READ
Lloh45:
	adrp	x8, _R300_PIPE_AUTO_CONFIG@GOTPAGE
Lloh46:
	ldr	x8, [x8, _R300_PIPE_AUTO_CONFIG@GOTPAGEOFF]
Lloh47:
	ldr	w8, [x8]
	orr	w1, w8, w0
	mov	x0, x19
	bl	_RADEON_WRITE
Lloh48:
	adrp	x8, _R300_RB2D_DSTCACHE_MODE@GOTPAGE
Lloh49:
	ldr	x8, [x8, _R300_RB2D_DSTCACHE_MODE@GOTPAGEOFF]
Lloh50:
	ldr	w19, [x8]
	mov	x0, x19
	bl	_RADEON_READ
Lloh51:
	adrp	x8, _R300_DC_AUTOFLUSH_ENABLE@GOTPAGE
Lloh52:
	ldr	x8, [x8, _R300_DC_AUTOFLUSH_ENABLE@GOTPAGEOFF]
Lloh53:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh54:
	adrp	x9, _R300_DC_DC_DISABLE_IGNORE_PE@GOTPAGE
Lloh55:
	ldr	x9, [x9, _R300_DC_DC_DISABLE_IGNORE_PE@GOTPAGEOFF]
Lloh56:
	ldr	w9, [x9]
	orr	w1, w8, w9
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_RADEON_WRITE
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpAdd	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_FAMILY_MASK,4,2         ; @RADEON_FAMILY_MASK
	.comm	_CHIP_RV530,4,2                 ; @CHIP_RV530
	.comm	_RV530_GB_PIPE_SELECT2,4,2      ; @RV530_GB_PIPE_SELECT2
	.comm	_CHIP_R420,4,2                  ; @CHIP_R420
	.comm	_R400_GB_PIPE_SELECT,4,2        ; @R400_GB_PIPE_SELECT
	.comm	_CHIP_R300,4,2                  ; @CHIP_R300
	.comm	_CHIP_R350,4,2                  ; @CHIP_R350
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Num pipes: %d\n"

	.comm	_R300_ENABLE_TILING,4,2         ; @R300_ENABLE_TILING
	.comm	_R300_TILE_SIZE_16,4,2          ; @R300_TILE_SIZE_16
	.comm	_R300_PIPE_COUNT_R300,4,2       ; @R300_PIPE_COUNT_R300
	.comm	_R300_PIPE_COUNT_R420_3P,4,2    ; @R300_PIPE_COUNT_R420_3P
	.comm	_R300_PIPE_COUNT_R420,4,2       ; @R300_PIPE_COUNT_R420
	.comm	_R300_PIPE_COUNT_RV350,4,2      ; @R300_PIPE_COUNT_RV350
	.comm	_CHIP_RV515,4,2                 ; @CHIP_RV515
	.comm	_R500_DYN_SCLK_PWMEM_PIPE,4,2   ; @R500_DYN_SCLK_PWMEM_PIPE
	.comm	_R300_SU_REG_DEST,4,2           ; @R300_SU_REG_DEST
	.comm	_R300_GB_TILE_CONFIG,4,2        ; @R300_GB_TILE_CONFIG
	.comm	_R300_DST_PIPE_CONFIG,4,2       ; @R300_DST_PIPE_CONFIG
	.comm	_R300_PIPE_AUTO_CONFIG,4,2      ; @R300_PIPE_AUTO_CONFIG
	.comm	_R300_RB2D_DSTCACHE_MODE,4,2    ; @R300_RB2D_DSTCACHE_MODE
	.comm	_R300_DC_AUTOFLUSH_ENABLE,4,2   ; @R300_DC_AUTOFLUSH_ENABLE
	.comm	_R300_DC_DC_DISABLE_IGNORE_PE,4,2 ; @R300_DC_DC_DISABLE_IGNORE_PE
	.no_dead_strip	_radeon_init_pipes
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.radeon_init_pipes
l_switch.table.radeon_init_pipes:
	.quad	_R300_PIPE_COUNT_R300
	.quad	_R300_PIPE_COUNT_R420_3P
	.quad	_R300_PIPE_COUNT_R420

.subsections_via_symbols
