	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mmci_set_clkreg
_mmci_set_clkreg:                       ## @mmci_set_clkreg
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	xorl	%r8d, %r8d
	movl	$0, %eax
	testl	%esi, %esi
	je	LBB0_7
## %bb.1:
	movl	(%rdi), %ecx
	cmpl	%esi, %ecx
	jbe	LBB0_2
## %bb.3:
	addl	%esi, %esi
	movl	%ecx, %eax
	xorl	%edx, %edx
	divl	%esi
	decl	%eax
	cmpl	$255, %eax
	movl	$255, %esi
	cmovll	%eax, %esi
	leal	(%rsi,%rsi), %r9d
	addl	$2, %r9d
	movl	%ecx, %eax
	xorl	%edx, %edx
	divl	%r9d
	movl	%eax, %ecx
	jmp	LBB0_4
LBB0_2:
	movq	_MCI_CLK_BYPASS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
LBB0_4:
	movl	%ecx, 4(%rdi)
	xorl	%eax, %eax
	cmpl	$128, 8(%rdi)
	jne	LBB0_6
## %bb.5:
	movq	_MCI_FCEN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_6:
	orl	%esi, %eax
	movq	_MCI_CLK_ENABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
LBB0_7:
	movq	24(%rdi), %rcx
	movq	(%rcx), %rcx
	movq	_MMC_BUS_WIDTH_4@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_9
## %bb.8:
	movq	_MCI_WIDE_BUS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r8d
LBB0_9:
	orl	%eax, %r8d
	movq	_MMCICLOCK@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	16(%rdi), %rsi
	movl	%r8d, %edi
	popq	%rbp
	jmp	_writel                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_MCI_CLK_BYPASS,4,2             ## @MCI_CLK_BYPASS
	.comm	_MCI_FCEN,4,2                   ## @MCI_FCEN
	.comm	_MCI_CLK_ENABLE,4,2             ## @MCI_CLK_ENABLE
	.comm	_MMC_BUS_WIDTH_4,8,3            ## @MMC_BUS_WIDTH_4
	.comm	_MCI_WIDE_BUS,4,2               ## @MCI_WIDE_BUS
	.comm	_MMCICLOCK,8,3                  ## @MMCICLOCK
	.no_dead_strip	_mmci_set_clkreg
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mmci_set_clkreg
_mmci_set_clkreg:                       ; @mmci_set_clkreg
	.cfi_startproc
; %bb.0:
	cbz	w1, LBB0_3
; %bb.1:
	ldr	w8, [x0]
	cmp	w8, w1
	b.ls	LBB0_4
; %bb.2:
	lsl	w9, w1, #1
	udiv	w9, w8, w9
	sub	w9, w9, #1
	mov	w10, #255
	cmp	w9, #255
	csel	w9, w9, w10, lt
	lsl	w10, w9, #1
	add	w10, w10, #2
	udiv	w8, w8, w10
	b	LBB0_5
LBB0_3:
	mov	w8, #0
	b	LBB0_6
LBB0_4:
Lloh0:
	adrp	x9, _MCI_CLK_BYPASS@GOTPAGE
Lloh1:
	ldr	x9, [x9, _MCI_CLK_BYPASS@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
LBB0_5:
	str	w8, [x0, #4]
	ldr	w8, [x0, #8]
Lloh3:
	adrp	x10, _MCI_FCEN@GOTPAGE
Lloh4:
	ldr	x10, [x10, _MCI_FCEN@GOTPAGEOFF]
Lloh5:
	ldr	w10, [x10]
	cmp	w8, #128
	csel	w8, w10, wzr, eq
	orr	w8, w8, w9
Lloh6:
	adrp	x9, _MCI_CLK_ENABLE@GOTPAGE
Lloh7:
	ldr	x9, [x9, _MCI_CLK_ENABLE@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	orr	w8, w8, w9
LBB0_6:
	ldp	x10, x9, [x0, #16]
	ldr	x9, [x9]
Lloh9:
	adrp	x11, _MMC_BUS_WIDTH_4@GOTPAGE
Lloh10:
	ldr	x11, [x11, _MMC_BUS_WIDTH_4@GOTPAGEOFF]
Lloh11:
	ldr	x11, [x11]
Lloh12:
	adrp	x12, _MCI_WIDE_BUS@GOTPAGE
Lloh13:
	ldr	x12, [x12, _MCI_WIDE_BUS@GOTPAGEOFF]
Lloh14:
	ldr	w12, [x12]
	cmp	x9, x11
	csel	w9, w12, wzr, eq
	orr	w0, w9, w8
Lloh15:
	adrp	x8, _MMCICLOCK@GOTPAGE
Lloh16:
	ldr	x8, [x8, _MMCICLOCK@GOTPAGEOFF]
Lloh17:
	ldr	x8, [x8]
	add	x1, x8, x10
	b	_writel
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.cfi_endproc
                                        ; -- End function
	.comm	_MCI_CLK_BYPASS,4,2             ; @MCI_CLK_BYPASS
	.comm	_MCI_FCEN,4,2                   ; @MCI_FCEN
	.comm	_MCI_CLK_ENABLE,4,2             ; @MCI_CLK_ENABLE
	.comm	_MMC_BUS_WIDTH_4,8,3            ; @MMC_BUS_WIDTH_4
	.comm	_MCI_WIDE_BUS,4,2               ; @MCI_WIDE_BUS
	.comm	_MMCICLOCK,8,3                  ; @MMCICLOCK
	.no_dead_strip	_mmci_set_clkreg
.subsections_via_symbols
