	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function r600_pcie_gart_enable
_r600_pcie_gart_enable:                 ## @r600_pcie_gart_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	cmpq	$0, 8(%rdi)
	je	LBB0_1
## %bb.2:
	movq	%r15, %rdi
	callq	_radeon_gart_table_vram_pin
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	LBB0_4
## %bb.3:
	movq	%r15, %rdi
	callq	_radeon_gart_restore
	movq	_VM_L2_CNTL@GOTPCREL(%rip), %rax
	movq	_ENABLE_L2_CACHE@GOTPCREL(%rip), %rcx
	movq	_ENABLE_L2_FRAGMENT_PROCESSING@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	movq	(%rax), %r14
	movq	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	$7, %edi
	callq	_EFFECTIVE_L2_QUEUE_SIZE
	orl	%eax, %ebx
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_VM_L2_CNTL2@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%r14d, %r14d
	xorl	%esi, %esi
	callq	_WREG32
	movq	_VM_L2_CNTL3@GOTPCREL(%rip), %rax
	movq	(%rax), %r12
	xorl	%edi, %edi
	callq	_BANK_SELECT_0
	movl	%eax, %ebx
	movl	$1, %edi
	callq	_BANK_SELECT_1
	orl	%eax, %ebx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_ENABLE_L1_TLB@GOTPCREL(%rip), %rax
	movq	_ENABLE_L1_FRAGMENT_PROCESSING@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r12d
	orl	(%rax), %r12d
	movq	_SYSTEM_ACCESS_MODE_NOT_IN_SYS@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
	movl	$5, %edi
	callq	_EFFECTIVE_L1_TLB_SIZE
	movl	%eax, %ebx
	movl	$5, %edi
	callq	_EFFECTIVE_L1_QUEUE_SIZE
	orl	%eax, %ebx
	orl	%r12d, %ebx
	movq	_ENABLE_WAIT_L2_QUERY@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_MC_VM_L1_TLB_MCB_RD_SYS_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_WR_SYS_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_RD_HDP_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movq	_ENABLE_L1_STRICT_ORDERING@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_WR_HDP_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCD_RD_A_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCD_WR_A_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCD_RD_B_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCD_WR_B_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_RD_GFX_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_WR_GFX_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_RD_PDMA_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_WR_PDMA_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_RD_SEM_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movq	_ENABLE_SEMAPHORE_MODE@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	orl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_WR_SEM_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	orl	(%r12), %ebx
	movl	%ebx, %esi
	callq	_WREG32
	movq	_VM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	16(%r15), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_VM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	20(%r15), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	(%r15), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_VM_CONTEXT0_CNTL@GOTPCREL(%rip), %r13
	movq	(%r13), %r12
	movq	_ENABLE_CONTEXT@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	xorl	%edi, %edi
	callq	_PAGE_TABLE_DEPTH
	orl	%eax, %ebx
	movq	_RANGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	28(%r15), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	(%r13), %rdi
	addq	$4, %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%r13), %rdi
	addq	$8, %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%r13), %rdi
	addq	$12, %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%r13), %rdi
	addq	$16, %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%r13), %rdi
	addq	$20, %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%r13), %rdi
	addq	$24, %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	%r15, %rdi
	callq	_r600_pcie_gart_tlb_flush
	movl	24(%r15), %esi
	sarl	$20, %esi
	movslq	(%r15), %rdx
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_INFO
	movl	$1, 4(%r15)
	jmp	LBB0_4
LBB0_1:
	movl	32(%r15), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r14d, %r14d
	subl	(%rax), %r14d
LBB0_4:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"No VRAM object for PCIE GART.\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_VM_L2_CNTL,8,3                 ## @VM_L2_CNTL
	.comm	_ENABLE_L2_CACHE,4,2            ## @ENABLE_L2_CACHE
	.comm	_ENABLE_L2_FRAGMENT_PROCESSING,4,2 ## @ENABLE_L2_FRAGMENT_PROCESSING
	.comm	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE,4,2 ## @ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_VM_L2_CNTL2,8,3                ## @VM_L2_CNTL2
	.comm	_VM_L2_CNTL3,8,3                ## @VM_L2_CNTL3
	.comm	_ENABLE_L1_TLB,4,2              ## @ENABLE_L1_TLB
	.comm	_ENABLE_L1_FRAGMENT_PROCESSING,4,2 ## @ENABLE_L1_FRAGMENT_PROCESSING
	.comm	_SYSTEM_ACCESS_MODE_NOT_IN_SYS,4,2 ## @SYSTEM_ACCESS_MODE_NOT_IN_SYS
	.comm	_ENABLE_WAIT_L2_QUERY,4,2       ## @ENABLE_WAIT_L2_QUERY
	.comm	_MC_VM_L1_TLB_MCB_RD_SYS_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_RD_SYS_CNTL
	.comm	_MC_VM_L1_TLB_MCB_WR_SYS_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_WR_SYS_CNTL
	.comm	_MC_VM_L1_TLB_MCB_RD_HDP_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_RD_HDP_CNTL
	.comm	_ENABLE_L1_STRICT_ORDERING,4,2  ## @ENABLE_L1_STRICT_ORDERING
	.comm	_MC_VM_L1_TLB_MCB_WR_HDP_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_WR_HDP_CNTL
	.comm	_MC_VM_L1_TLB_MCD_RD_A_CNTL,8,3 ## @MC_VM_L1_TLB_MCD_RD_A_CNTL
	.comm	_MC_VM_L1_TLB_MCD_WR_A_CNTL,8,3 ## @MC_VM_L1_TLB_MCD_WR_A_CNTL
	.comm	_MC_VM_L1_TLB_MCD_RD_B_CNTL,8,3 ## @MC_VM_L1_TLB_MCD_RD_B_CNTL
	.comm	_MC_VM_L1_TLB_MCD_WR_B_CNTL,8,3 ## @MC_VM_L1_TLB_MCD_WR_B_CNTL
	.comm	_MC_VM_L1_TLB_MCB_RD_GFX_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_RD_GFX_CNTL
	.comm	_MC_VM_L1_TLB_MCB_WR_GFX_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_WR_GFX_CNTL
	.comm	_MC_VM_L1_TLB_MCB_RD_PDMA_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
	.comm	_MC_VM_L1_TLB_MCB_WR_PDMA_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
	.comm	_MC_VM_L1_TLB_MCB_RD_SEM_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_RD_SEM_CNTL
	.comm	_ENABLE_SEMAPHORE_MODE,4,2      ## @ENABLE_SEMAPHORE_MODE
	.comm	_MC_VM_L1_TLB_MCB_WR_SEM_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_WR_SEM_CNTL
	.comm	_VM_CONTEXT0_PAGE_TABLE_START_ADDR,8,3 ## @VM_CONTEXT0_PAGE_TABLE_START_ADDR
	.comm	_VM_CONTEXT0_PAGE_TABLE_END_ADDR,8,3 ## @VM_CONTEXT0_PAGE_TABLE_END_ADDR
	.comm	_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR,8,3 ## @VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
	.comm	_VM_CONTEXT0_CNTL,8,3           ## @VM_CONTEXT0_CNTL
	.comm	_ENABLE_CONTEXT,4,2             ## @ENABLE_CONTEXT
	.comm	_RANGE_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ## @RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,8,3 ## @VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
L_.str.1:                               ## @.str.1
	.asciz	"PCIE GART of %uM enabled (table at 0x%016llX).\n"

	.no_dead_strip	_r600_pcie_gart_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function r600_pcie_gart_enable
_r600_pcie_gart_enable:                 ; @r600_pcie_gart_enable
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	x8, [x0, #8]
	cbz	x8, LBB0_3
; %bb.1:
	mov	x0, x19
	bl	_radeon_gart_table_vram_pin
	cbnz	w0, LBB0_4
; %bb.2:
	mov	x0, x19
	bl	_radeon_gart_restore
Lloh0:
	adrp	x8, _VM_L2_CNTL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _VM_L2_CNTL@GOTPAGEOFF]
Lloh2:
	ldr	x20, [x8]
Lloh3:
	adrp	x8, _ENABLE_L2_CACHE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _ENABLE_L2_CACHE@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
Lloh6:
	adrp	x9, _ENABLE_L2_FRAGMENT_PROCESSING@GOTPAGE
Lloh7:
	ldr	x9, [x9, _ENABLE_L2_FRAGMENT_PROCESSING@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh9:
	adrp	x9, _ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGE
Lloh10:
	ldr	x9, [x9, _ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	orr	w21, w8, w9
	mov	w0, #7
	bl	_EFFECTIVE_L2_QUEUE_SIZE
	orr	w1, w21, w0
	mov	x0, x20
	bl	_WREG32
Lloh12:
	adrp	x8, _VM_L2_CNTL2@GOTPAGE
Lloh13:
	ldr	x8, [x8, _VM_L2_CNTL2@GOTPAGEOFF]
Lloh14:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh15:
	adrp	x8, _VM_L2_CNTL3@GOTPAGE
Lloh16:
	ldr	x8, [x8, _VM_L2_CNTL3@GOTPAGEOFF]
Lloh17:
	ldr	x20, [x8]
	mov	w0, #0
	bl	_BANK_SELECT_0
	mov	x21, x0
	mov	w22, #1
	mov	w0, #1
	bl	_BANK_SELECT_1
	orr	w1, w0, w21
	mov	x0, x20
	bl	_WREG32
Lloh18:
	adrp	x8, _ENABLE_L1_TLB@GOTPAGE
Lloh19:
	ldr	x8, [x8, _ENABLE_L1_TLB@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
Lloh21:
	adrp	x9, _ENABLE_L1_FRAGMENT_PROCESSING@GOTPAGE
Lloh22:
	ldr	x9, [x9, _ENABLE_L1_FRAGMENT_PROCESSING@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh24:
	adrp	x9, _SYSTEM_ACCESS_MODE_NOT_IN_SYS@GOTPAGE
Lloh25:
	ldr	x9, [x9, _SYSTEM_ACCESS_MODE_NOT_IN_SYS@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	orr	w20, w8, w9
	mov	w0, #5
	bl	_EFFECTIVE_L1_TLB_SIZE
	orr	w20, w20, w0
	mov	w0, #5
	bl	_EFFECTIVE_L1_QUEUE_SIZE
Lloh27:
	adrp	x8, _ENABLE_WAIT_L2_QUERY@GOTPAGE
Lloh28:
	ldr	x8, [x8, _ENABLE_WAIT_L2_QUERY@GOTPAGEOFF]
	orr	w9, w20, w0
Lloh29:
	ldr	w8, [x8]
	orr	w20, w9, w8
Lloh30:
	adrp	x8, _MC_VM_L1_TLB_MCB_RD_SYS_CNTL@GOTPAGE
Lloh31:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_RD_SYS_CNTL@GOTPAGEOFF]
Lloh32:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh33:
	adrp	x8, _MC_VM_L1_TLB_MCB_WR_SYS_CNTL@GOTPAGE
Lloh34:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_WR_SYS_CNTL@GOTPAGEOFF]
Lloh35:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh36:
	adrp	x8, _MC_VM_L1_TLB_MCB_RD_HDP_CNTL@GOTPAGE
Lloh37:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_RD_HDP_CNTL@GOTPAGEOFF]
Lloh38:
	ldr	x0, [x8]
Lloh39:
	adrp	x8, _ENABLE_L1_STRICT_ORDERING@GOTPAGE
Lloh40:
	ldr	x8, [x8, _ENABLE_L1_STRICT_ORDERING@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
	orr	w1, w8, w20
	bl	_WREG32
Lloh42:
	adrp	x8, _MC_VM_L1_TLB_MCB_WR_HDP_CNTL@GOTPAGE
Lloh43:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_WR_HDP_CNTL@GOTPAGEOFF]
Lloh44:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh45:
	adrp	x8, _MC_VM_L1_TLB_MCD_RD_A_CNTL@GOTPAGE
Lloh46:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCD_RD_A_CNTL@GOTPAGEOFF]
Lloh47:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh48:
	adrp	x8, _MC_VM_L1_TLB_MCD_WR_A_CNTL@GOTPAGE
Lloh49:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCD_WR_A_CNTL@GOTPAGEOFF]
Lloh50:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh51:
	adrp	x8, _MC_VM_L1_TLB_MCD_RD_B_CNTL@GOTPAGE
Lloh52:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCD_RD_B_CNTL@GOTPAGEOFF]
Lloh53:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh54:
	adrp	x8, _MC_VM_L1_TLB_MCD_WR_B_CNTL@GOTPAGE
Lloh55:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCD_WR_B_CNTL@GOTPAGEOFF]
Lloh56:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh57:
	adrp	x8, _MC_VM_L1_TLB_MCB_RD_GFX_CNTL@GOTPAGE
Lloh58:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_RD_GFX_CNTL@GOTPAGEOFF]
Lloh59:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh60:
	adrp	x8, _MC_VM_L1_TLB_MCB_WR_GFX_CNTL@GOTPAGE
Lloh61:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_WR_GFX_CNTL@GOTPAGEOFF]
Lloh62:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh63:
	adrp	x8, _MC_VM_L1_TLB_MCB_RD_PDMA_CNTL@GOTPAGE
Lloh64:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_RD_PDMA_CNTL@GOTPAGEOFF]
Lloh65:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh66:
	adrp	x8, _MC_VM_L1_TLB_MCB_WR_PDMA_CNTL@GOTPAGE
Lloh67:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_WR_PDMA_CNTL@GOTPAGEOFF]
Lloh68:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh69:
	adrp	x8, _MC_VM_L1_TLB_MCB_RD_SEM_CNTL@GOTPAGE
Lloh70:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_RD_SEM_CNTL@GOTPAGEOFF]
Lloh71:
	ldr	x0, [x8]
Lloh72:
	adrp	x21, _ENABLE_SEMAPHORE_MODE@GOTPAGE
Lloh73:
	ldr	x21, [x21, _ENABLE_SEMAPHORE_MODE@GOTPAGEOFF]
	ldr	w8, [x21]
	orr	w1, w8, w20
	bl	_WREG32
Lloh74:
	adrp	x8, _MC_VM_L1_TLB_MCB_WR_SEM_CNTL@GOTPAGE
Lloh75:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_WR_SEM_CNTL@GOTPAGEOFF]
Lloh76:
	ldr	x0, [x8]
	ldr	w8, [x21]
	orr	w1, w8, w20
	bl	_WREG32
Lloh77:
	adrp	x8, _VM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPAGE
Lloh78:
	ldr	x8, [x8, _VM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPAGEOFF]
Lloh79:
	ldr	x0, [x8]
	ldr	w8, [x19, #16]
	asr	w1, w8, #12
	bl	_WREG32
Lloh80:
	adrp	x8, _VM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPAGE
Lloh81:
	ldr	x8, [x8, _VM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPAGEOFF]
Lloh82:
	ldr	x0, [x8]
	ldr	w8, [x19, #20]
	asr	w1, w8, #12
	bl	_WREG32
Lloh83:
	adrp	x8, _VM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPAGE
Lloh84:
	ldr	x8, [x8, _VM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPAGEOFF]
Lloh85:
	ldr	x0, [x8]
	ldr	w8, [x19]
	asr	w1, w8, #12
	bl	_WREG32
Lloh86:
	adrp	x21, _VM_CONTEXT0_CNTL@GOTPAGE
Lloh87:
	ldr	x21, [x21, _VM_CONTEXT0_CNTL@GOTPAGEOFF]
	ldr	x20, [x21]
Lloh88:
	adrp	x8, _ENABLE_CONTEXT@GOTPAGE
Lloh89:
	ldr	x8, [x8, _ENABLE_CONTEXT@GOTPAGEOFF]
Lloh90:
	ldr	w23, [x8]
	mov	w0, #0
	bl	_PAGE_TABLE_DEPTH
	orr	w8, w0, w23
Lloh91:
	adrp	x9, _RANGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGE
Lloh92:
	ldr	x9, [x9, _RANGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGEOFF]
Lloh93:
	ldr	w9, [x9]
	orr	w1, w8, w9
	mov	x0, x20
	bl	_WREG32
Lloh94:
	adrp	x8, _VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR@GOTPAGE
Lloh95:
	ldr	x8, [x8, _VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR@GOTPAGEOFF]
Lloh96:
	ldr	x0, [x8]
	ldr	w8, [x19, #28]
	asr	w1, w8, #12
	bl	_WREG32
	ldr	x8, [x21]
	add	x0, x8, #4
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x21]
	add	x0, x8, #8
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x21]
	add	x0, x8, #12
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x21]
	add	x0, x8, #16
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x21]
	add	x0, x8, #20
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x21]
	add	x0, x8, #24
	mov	w1, #0
	bl	_WREG32
	mov	x0, x19
	bl	_r600_pcie_gart_tlb_flush
	ldr	w8, [x19, #24]
	asr	w1, w8, #20
	ldrsw	x2, [x19]
Lloh97:
	adrp	x0, l_.str.1@PAGE
Lloh98:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_INFO
	mov	w0, #0
	str	w22, [x19, #4]
	b	LBB0_4
LBB0_3:
	ldr	w0, [x19, #32]
Lloh99:
	adrp	x1, l_.str@PAGE
Lloh100:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
Lloh101:
	adrp	x8, _EINVAL@GOTPAGE
Lloh102:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh103:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_4:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGot	Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGot	Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpAdd	Lloh99, Lloh100
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"No VRAM object for PCIE GART.\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_VM_L2_CNTL,8,3                 ; @VM_L2_CNTL
	.comm	_ENABLE_L2_CACHE,4,2            ; @ENABLE_L2_CACHE
	.comm	_ENABLE_L2_FRAGMENT_PROCESSING,4,2 ; @ENABLE_L2_FRAGMENT_PROCESSING
	.comm	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE,4,2 ; @ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_VM_L2_CNTL2,8,3                ; @VM_L2_CNTL2
	.comm	_VM_L2_CNTL3,8,3                ; @VM_L2_CNTL3
	.comm	_ENABLE_L1_TLB,4,2              ; @ENABLE_L1_TLB
	.comm	_ENABLE_L1_FRAGMENT_PROCESSING,4,2 ; @ENABLE_L1_FRAGMENT_PROCESSING
	.comm	_SYSTEM_ACCESS_MODE_NOT_IN_SYS,4,2 ; @SYSTEM_ACCESS_MODE_NOT_IN_SYS
	.comm	_ENABLE_WAIT_L2_QUERY,4,2       ; @ENABLE_WAIT_L2_QUERY
	.comm	_MC_VM_L1_TLB_MCB_RD_SYS_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_RD_SYS_CNTL
	.comm	_MC_VM_L1_TLB_MCB_WR_SYS_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_WR_SYS_CNTL
	.comm	_MC_VM_L1_TLB_MCB_RD_HDP_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_RD_HDP_CNTL
	.comm	_ENABLE_L1_STRICT_ORDERING,4,2  ; @ENABLE_L1_STRICT_ORDERING
	.comm	_MC_VM_L1_TLB_MCB_WR_HDP_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_WR_HDP_CNTL
	.comm	_MC_VM_L1_TLB_MCD_RD_A_CNTL,8,3 ; @MC_VM_L1_TLB_MCD_RD_A_CNTL
	.comm	_MC_VM_L1_TLB_MCD_WR_A_CNTL,8,3 ; @MC_VM_L1_TLB_MCD_WR_A_CNTL
	.comm	_MC_VM_L1_TLB_MCD_RD_B_CNTL,8,3 ; @MC_VM_L1_TLB_MCD_RD_B_CNTL
	.comm	_MC_VM_L1_TLB_MCD_WR_B_CNTL,8,3 ; @MC_VM_L1_TLB_MCD_WR_B_CNTL
	.comm	_MC_VM_L1_TLB_MCB_RD_GFX_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_RD_GFX_CNTL
	.comm	_MC_VM_L1_TLB_MCB_WR_GFX_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_WR_GFX_CNTL
	.comm	_MC_VM_L1_TLB_MCB_RD_PDMA_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
	.comm	_MC_VM_L1_TLB_MCB_WR_PDMA_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
	.comm	_MC_VM_L1_TLB_MCB_RD_SEM_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_RD_SEM_CNTL
	.comm	_ENABLE_SEMAPHORE_MODE,4,2      ; @ENABLE_SEMAPHORE_MODE
	.comm	_MC_VM_L1_TLB_MCB_WR_SEM_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_WR_SEM_CNTL
	.comm	_VM_CONTEXT0_PAGE_TABLE_START_ADDR,8,3 ; @VM_CONTEXT0_PAGE_TABLE_START_ADDR
	.comm	_VM_CONTEXT0_PAGE_TABLE_END_ADDR,8,3 ; @VM_CONTEXT0_PAGE_TABLE_END_ADDR
	.comm	_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR,8,3 ; @VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
	.comm	_VM_CONTEXT0_CNTL,8,3           ; @VM_CONTEXT0_CNTL
	.comm	_ENABLE_CONTEXT,4,2             ; @ENABLE_CONTEXT
	.comm	_RANGE_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ; @RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,8,3 ; @VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
l_.str.1:                               ; @.str.1
	.asciz	"PCIE GART of %uM enabled (table at 0x%016llX).\n"

	.no_dead_strip	_r600_pcie_gart_enable
.subsections_via_symbols
