	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_driver_irq_preinstall   ## -- Begin function radeon_driver_irq_preinstall
	.p2align	4, 0x90
_radeon_driver_irq_preinstall:          ## @radeon_driver_irq_preinstall
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	(%rdi), %rbx
	movq	_RADEON_FAMILY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%rbx), %eax
	movq	_CHIP_R600@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jge	LBB0_4
## %bb.1:
	movq	_CHIP_RS600@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jl	LBB0_3
## %bb.2:
	movq	_R500_DxMODE_INT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_RADEON_WRITE
LBB0_3:
	movq	_RADEON_GEN_INT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_RADEON_WRITE
	leaq	-12(%rbp), %rsi
	movq	%rbx, %rdi
	callq	_radeon_acknowledge_irqs
LBB0_4:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_FAMILY_MASK,4,2         ## @RADEON_FAMILY_MASK
	.comm	_CHIP_R600,4,2                  ## @CHIP_R600
	.comm	_CHIP_RS600,4,2                 ## @CHIP_RS600
	.comm	_R500_DxMODE_INT_MASK,4,2       ## @R500_DxMODE_INT_MASK
	.comm	_RADEON_GEN_INT_CNTL,4,2        ## @RADEON_GEN_INT_CNTL
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_driver_irq_preinstall   ; -- Begin function radeon_driver_irq_preinstall
	.p2align	2
_radeon_driver_irq_preinstall:          ; @radeon_driver_irq_preinstall
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #48
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	x19, [x0]
	ldr	w8, [x19]
Lloh0:
	adrp	x9, _RADEON_FAMILY_MASK@GOTPAGE
Lloh1:
	ldr	x9, [x9, _RADEON_FAMILY_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	and	w8, w9, w8
Lloh3:
	adrp	x9, _CHIP_R600@GOTPAGE
Lloh4:
	ldr	x9, [x9, _CHIP_R600@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ge	LBB0_4
; %bb.1:
Lloh6:
	adrp	x9, _CHIP_RS600@GOTPAGE
Lloh7:
	ldr	x9, [x9, _CHIP_RS600@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	cmp	w8, w9
	b.lt	LBB0_3
; %bb.2:
Lloh9:
	adrp	x8, _R500_DxMODE_INT_MASK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _R500_DxMODE_INT_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_RADEON_WRITE
LBB0_3:
Lloh12:
	adrp	x8, _RADEON_GEN_INT_CNTL@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RADEON_GEN_INT_CNTL@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_RADEON_WRITE
	add	x1, sp, #12
	mov	x0, x19
	bl	_radeon_acknowledge_irqs
LBB0_4:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_FAMILY_MASK,4,2         ; @RADEON_FAMILY_MASK
	.comm	_CHIP_R600,4,2                  ; @CHIP_R600
	.comm	_CHIP_RS600,4,2                 ; @CHIP_RS600
	.comm	_R500_DxMODE_INT_MASK,4,2       ; @R500_DxMODE_INT_MASK
	.comm	_RADEON_GEN_INT_CNTL,4,2        ; @RADEON_GEN_INT_CNTL
.subsections_via_symbols
