	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_bo_check_tiling         ## -- Begin function radeon_bo_check_tiling
	.p2align	4, 0x90
_radeon_bo_check_tiling:                ## @radeon_bo_check_tiling
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %ebx
	movl	%esi, %r14d
	movq	%rdi, %r15
	callq	_radeon_bo_is_reserved
	xorl	%edi, %edi
	orl	%ebx, %eax
	sete	%dil
	callq	_BUG_ON
	movq	_RADEON_TILING_SURFACE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r15)
	je	LBB0_8
## %bb.1:
	testl	%ebx, %ebx
	je	LBB0_3
LBB0_2:
	movq	%r15, %rdi
	callq	_radeon_bo_clear_surface_reg
LBB0_8:
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_3:
	movq	16(%r15), %rax
	movq	_TTM_PL_VRAM@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_4
## %bb.6:
	testl	%r14d, %r14d
	jne	LBB0_9
## %bb.7:
	cmpq	$0, 8(%r15)
	jns	LBB0_8
LBB0_9:
	movq	%r15, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_bo_get_surface_reg      ## TAILCALL
LBB0_4:
	testl	%r14d, %r14d
	je	LBB0_8
## %bb.5:
	cmpq	$0, 8(%r15)
	jns	LBB0_2
	jmp	LBB0_8
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_TILING_SURFACE,4,2      ## @RADEON_TILING_SURFACE
	.comm	_TTM_PL_VRAM,8,3                ## @TTM_PL_VRAM
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_bo_check_tiling         ; -- Begin function radeon_bo_check_tiling
	.p2align	2
_radeon_bo_check_tiling:                ; @radeon_bo_check_tiling
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x21, x2
	mov	x20, x1
	mov	x19, x0
	bl	_radeon_bo_is_reserved
	orr	w8, w0, w21
	cmp	w8, #0
	cset	w0, eq
	bl	_BUG_ON
	ldr	w8, [x19]
Lloh0:
	adrp	x9, _RADEON_TILING_SURFACE@GOTPAGE
Lloh1:
	ldr	x9, [x9, _RADEON_TILING_SURFACE@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_3
; %bb.1:
	cbz	w21, LBB0_4
LBB0_2:
	mov	x0, x19
	bl	_radeon_bo_clear_surface_reg
LBB0_3:
	mov	w0, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_4:
	ldr	x8, [x19, #16]
Lloh3:
	adrp	x9, _TTM_PL_VRAM@GOTPAGE
Lloh4:
	ldr	x9, [x9, _TTM_PL_VRAM@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_8
; %bb.5:
	cbnz	w20, LBB0_7
; %bb.6:
	ldr	x8, [x19, #8]
	tbz	x8, #63, LBB0_3
LBB0_7:
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_radeon_bo_get_surface_reg
LBB0_8:
	cbz	w20, LBB0_3
; %bb.9:
	ldr	x8, [x19, #8]
	tbz	x8, #63, LBB0_2
	b	LBB0_3
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_TILING_SURFACE,4,2      ; @RADEON_TILING_SURFACE
	.comm	_TTM_PL_VRAM,8,3                ; @TTM_PL_VRAM
.subsections_via_symbols
