	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function i915_save_display
_i915_save_display:                     ## @i915_save_display
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	(%rdi), %r14
	callq	_INTEL_INFO
	cmpl	$4, (%rax)
	jg	LBB0_2
## %bb.1:
	movq	_DSPARB@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	%rax, 136(%r14)
LBB0_2:
	movq	_DRIVER_MODESET@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r12, %rdi
	callq	_drm_core_check_feature
	testl	%eax, %eax
	jne	LBB0_4
## %bb.3:
	movq	%r12, %rdi
	callq	_i915_save_display_reg
LBB0_4:
	movq	%r12, %rdi
	callq	_HAS_PCH_SPLIT
	testq	%rax, %rax
	je	LBB0_6
## %bb.5:
	movq	_PCH_PP_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	%rax, 112(%r14)
	movq	_BLC_PWM_PCH_CTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	%rax, 96(%r14)
	movq	_BLC_PWM_PCH_CTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	%rax, 80(%r14)
	movq	_BLC_PWM_CPU_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	%rax, 128(%r14)
	movq	_BLC_PWM_CPU_CTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	%rax, 120(%r14)
	movq	_PCH_LVDS@GOTPCREL(%rip), %rax
LBB0_11:
	movl	(%rax), %edi
	callq	_I915_READ
	movq	%rax, 72(%r14)
LBB0_12:
	movq	%r12, %rdi
	callq	_IS_I830
	testl	%eax, %eax
	jne	LBB0_16
## %bb.13:
	movq	%r12, %rdi
	callq	_IS_845G
	testl	%eax, %eax
	jne	LBB0_16
## %bb.14:
	movq	%r12, %rdi
	callq	_HAS_PCH_SPLIT
	testq	%rax, %rax
	jne	LBB0_16
## %bb.15:
	movq	_PFIT_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	%rax, 64(%r14)
LBB0_16:
	movq	%r12, %rdi
	callq	_HAS_PCH_SPLIT
	testq	%rax, %rax
	movq	_PCH_PP_ON_DELAYS@GOTPCREL(%rip), %rax
	cmoveq	_PP_ON_DELAYS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_PCH_PP_OFF_DELAYS@GOTPCREL(%rip), %rbx
	cmoveq	_PP_OFF_DELAYS@GOTPCREL(%rip), %rbx
	movq	_PCH_PP_DIVISOR@GOTPCREL(%rip), %r13
	cmoveq	_PP_DIVISOR@GOTPCREL(%rip), %r13
	callq	_I915_READ
	movq	%rax, 56(%r14)
	movl	(%rbx), %edi
	callq	_I915_READ
	movq	%rax, 48(%r14)
	movl	(%r13), %edi
	callq	_I915_READ
	movq	%rax, 40(%r14)
	movq	%r12, %rdi
	callq	_I915_HAS_FBC
	testq	%rax, %rax
	je	LBB0_23
## %bb.17:
	movq	%r12, %rdi
	callq	_HAS_PCH_SPLIT
	testq	%rax, %rax
	je	LBB0_20
## %bb.18:
	movq	_ILK_DPFC_CB_BASE@GOTPCREL(%rip), %rax
	jmp	LBB0_19
LBB0_6:
	movq	_PP_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	%rax, 112(%r14)
	movq	_PFIT_PGM_RATIOS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	%rax, 104(%r14)
	movq	_BLC_PWM_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	%rax, 96(%r14)
	movq	_BLC_HIST_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	%rax, 88(%r14)
	movq	%r12, %rdi
	callq	_INTEL_INFO
	cmpl	$4, (%rax)
	jl	LBB0_8
## %bb.7:
	movq	_BLC_PWM_CTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	%rax, 80(%r14)
LBB0_8:
	movq	%r12, %rdi
	callq	_IS_MOBILE
	testq	%rax, %rax
	je	LBB0_12
## %bb.9:
	movq	%r12, %rdi
	callq	_IS_I830
	testl	%eax, %eax
	jne	LBB0_12
## %bb.10:
	movq	_LVDS@GOTPCREL(%rip), %rax
	jmp	LBB0_11
LBB0_20:
	movq	%r12, %rdi
	callq	_IS_GM45
	testq	%rax, %rax
	je	LBB0_22
## %bb.21:
	movq	_DPFC_CB_BASE@GOTPCREL(%rip), %rax
LBB0_19:
	movl	(%rax), %edi
	callq	_I915_READ
	movq	%rax, 32(%r14)
LBB0_23:
	movl	(%r15), %esi
	movq	%r12, %rdi
	callq	_drm_core_check_feature
	testl	%eax, %eax
	je	LBB0_25
## %bb.24:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_25:
	movq	%r12, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_i915_save_vga                  ## TAILCALL
LBB0_22:
	movq	_FBC_CFB_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	%rax, 24(%r14)
	movq	_FBC_LL_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	%rax, 16(%r14)
	movq	_FBC_CONTROL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	%rax, 8(%r14)
	movq	_FBC_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	%rax, (%r14)
	jmp	LBB0_23
	.cfi_endproc
                                        ## -- End function
	.comm	_DSPARB,4,2                     ## @DSPARB
	.comm	_DRIVER_MODESET,4,2             ## @DRIVER_MODESET
	.comm	_PCH_PP_CONTROL,4,2             ## @PCH_PP_CONTROL
	.comm	_BLC_PWM_PCH_CTL1,4,2           ## @BLC_PWM_PCH_CTL1
	.comm	_BLC_PWM_PCH_CTL2,4,2           ## @BLC_PWM_PCH_CTL2
	.comm	_BLC_PWM_CPU_CTL,4,2            ## @BLC_PWM_CPU_CTL
	.comm	_BLC_PWM_CPU_CTL2,4,2           ## @BLC_PWM_CPU_CTL2
	.comm	_PCH_LVDS,4,2                   ## @PCH_LVDS
	.comm	_PP_CONTROL,4,2                 ## @PP_CONTROL
	.comm	_PFIT_PGM_RATIOS,4,2            ## @PFIT_PGM_RATIOS
	.comm	_BLC_PWM_CTL,4,2                ## @BLC_PWM_CTL
	.comm	_BLC_HIST_CTL,4,2               ## @BLC_HIST_CTL
	.comm	_BLC_PWM_CTL2,4,2               ## @BLC_PWM_CTL2
	.comm	_LVDS,4,2                       ## @LVDS
	.comm	_PFIT_CONTROL,4,2               ## @PFIT_CONTROL
	.comm	_PCH_PP_ON_DELAYS,4,2           ## @PCH_PP_ON_DELAYS
	.comm	_PCH_PP_OFF_DELAYS,4,2          ## @PCH_PP_OFF_DELAYS
	.comm	_PCH_PP_DIVISOR,4,2             ## @PCH_PP_DIVISOR
	.comm	_PP_ON_DELAYS,4,2               ## @PP_ON_DELAYS
	.comm	_PP_OFF_DELAYS,4,2              ## @PP_OFF_DELAYS
	.comm	_PP_DIVISOR,4,2                 ## @PP_DIVISOR
	.comm	_ILK_DPFC_CB_BASE,4,2           ## @ILK_DPFC_CB_BASE
	.comm	_DPFC_CB_BASE,4,2               ## @DPFC_CB_BASE
	.comm	_FBC_CFB_BASE,4,2               ## @FBC_CFB_BASE
	.comm	_FBC_LL_BASE,4,2                ## @FBC_LL_BASE
	.comm	_FBC_CONTROL2,4,2               ## @FBC_CONTROL2
	.comm	_FBC_CONTROL,4,2                ## @FBC_CONTROL
	.no_dead_strip	_i915_save_display
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function i915_save_display
_i915_save_display:                     ; @i915_save_display
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	x20, [x0]
	bl	_INTEL_INFO
	ldr	w8, [x0]
	cmp	w8, #4
	b.gt	LBB0_2
; %bb.1:
Lloh0:
	adrp	x8, _DSPARB@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DSPARB@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_I915_READ
	str	x0, [x20, #136]
LBB0_2:
Lloh3:
	adrp	x21, _DRIVER_MODESET@GOTPAGE
Lloh4:
	ldr	x21, [x21, _DRIVER_MODESET@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_drm_core_check_feature
	cbnz	w0, LBB0_4
; %bb.3:
	mov	x0, x19
	bl	_i915_save_display_reg
LBB0_4:
	mov	x0, x19
	bl	_HAS_PCH_SPLIT
	cbz	x0, LBB0_14
; %bb.5:
Lloh5:
	adrp	x8, _PCH_PP_CONTROL@GOTPAGE
Lloh6:
	ldr	x8, [x8, _PCH_PP_CONTROL@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
	bl	_I915_READ
	str	x0, [x20, #112]
Lloh8:
	adrp	x8, _BLC_PWM_PCH_CTL1@GOTPAGE
Lloh9:
	ldr	x8, [x8, _BLC_PWM_PCH_CTL1@GOTPAGEOFF]
Lloh10:
	ldr	w0, [x8]
	bl	_I915_READ
	str	x0, [x20, #96]
Lloh11:
	adrp	x8, _BLC_PWM_PCH_CTL2@GOTPAGE
Lloh12:
	ldr	x8, [x8, _BLC_PWM_PCH_CTL2@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
	bl	_I915_READ
	str	x0, [x20, #80]
Lloh14:
	adrp	x8, _BLC_PWM_CPU_CTL@GOTPAGE
Lloh15:
	ldr	x8, [x8, _BLC_PWM_CPU_CTL@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
	bl	_I915_READ
	str	x0, [x20, #128]
Lloh17:
	adrp	x8, _BLC_PWM_CPU_CTL2@GOTPAGE
Lloh18:
	ldr	x8, [x8, _BLC_PWM_CPU_CTL2@GOTPAGEOFF]
Lloh19:
	ldr	w0, [x8]
	bl	_I915_READ
	str	x0, [x20, #120]
Lloh20:
	adrp	x8, _PCH_LVDS@GOTPAGE
Lloh21:
	ldr	x8, [x8, _PCH_LVDS@GOTPAGEOFF]
LBB0_6:
	ldr	w0, [x8]
	bl	_I915_READ
	str	x0, [x20, #72]
LBB0_7:
	mov	x0, x19
	bl	_IS_I830
	cbnz	w0, LBB0_11
; %bb.8:
	mov	x0, x19
	bl	_IS_845G
	cbnz	w0, LBB0_11
; %bb.9:
	mov	x0, x19
	bl	_HAS_PCH_SPLIT
	cbnz	x0, LBB0_11
; %bb.10:
Lloh22:
	adrp	x8, _PFIT_CONTROL@GOTPAGE
Lloh23:
	ldr	x8, [x8, _PFIT_CONTROL@GOTPAGEOFF]
Lloh24:
	ldr	w0, [x8]
	bl	_I915_READ
	str	x0, [x20, #64]
LBB0_11:
	mov	x0, x19
	bl	_HAS_PCH_SPLIT
Lloh25:
	adrp	x8, _PP_ON_DELAYS@GOTPAGE
Lloh26:
	ldr	x8, [x8, _PP_ON_DELAYS@GOTPAGEOFF]
Lloh27:
	adrp	x9, _PCH_PP_ON_DELAYS@GOTPAGE
Lloh28:
	ldr	x9, [x9, _PCH_PP_ON_DELAYS@GOTPAGEOFF]
	cmp	x0, #0
	csel	x8, x8, x9, eq
	ldr	w0, [x8]
Lloh29:
	adrp	x8, _PP_OFF_DELAYS@GOTPAGE
Lloh30:
	ldr	x8, [x8, _PP_OFF_DELAYS@GOTPAGEOFF]
Lloh31:
	adrp	x9, _PCH_PP_OFF_DELAYS@GOTPAGE
Lloh32:
	ldr	x9, [x9, _PCH_PP_OFF_DELAYS@GOTPAGEOFF]
	csel	x22, x8, x9, eq
Lloh33:
	adrp	x8, _PP_DIVISOR@GOTPAGE
Lloh34:
	ldr	x8, [x8, _PP_DIVISOR@GOTPAGEOFF]
Lloh35:
	adrp	x9, _PCH_PP_DIVISOR@GOTPAGE
Lloh36:
	ldr	x9, [x9, _PCH_PP_DIVISOR@GOTPAGEOFF]
	csel	x23, x8, x9, eq
	bl	_I915_READ
	str	x0, [x20, #56]
	ldr	w0, [x22]
	bl	_I915_READ
	str	x0, [x20, #48]
	ldr	w0, [x23]
	bl	_I915_READ
	str	x0, [x20, #40]
	mov	x0, x19
	bl	_I915_HAS_FBC
	cbz	x0, LBB0_22
; %bb.12:
	mov	x0, x19
	bl	_HAS_PCH_SPLIT
	cbz	x0, LBB0_19
; %bb.13:
Lloh37:
	adrp	x8, _ILK_DPFC_CB_BASE@GOTPAGE
Lloh38:
	ldr	x8, [x8, _ILK_DPFC_CB_BASE@GOTPAGEOFF]
	b	LBB0_21
LBB0_14:
Lloh39:
	adrp	x8, _PP_CONTROL@GOTPAGE
Lloh40:
	ldr	x8, [x8, _PP_CONTROL@GOTPAGEOFF]
Lloh41:
	ldr	w0, [x8]
	bl	_I915_READ
	str	x0, [x20, #112]
Lloh42:
	adrp	x8, _PFIT_PGM_RATIOS@GOTPAGE
Lloh43:
	ldr	x8, [x8, _PFIT_PGM_RATIOS@GOTPAGEOFF]
Lloh44:
	ldr	w0, [x8]
	bl	_I915_READ
	str	x0, [x20, #104]
Lloh45:
	adrp	x8, _BLC_PWM_CTL@GOTPAGE
Lloh46:
	ldr	x8, [x8, _BLC_PWM_CTL@GOTPAGEOFF]
Lloh47:
	ldr	w0, [x8]
	bl	_I915_READ
	str	x0, [x20, #96]
Lloh48:
	adrp	x8, _BLC_HIST_CTL@GOTPAGE
Lloh49:
	ldr	x8, [x8, _BLC_HIST_CTL@GOTPAGEOFF]
Lloh50:
	ldr	w0, [x8]
	bl	_I915_READ
	str	x0, [x20, #88]
	mov	x0, x19
	bl	_INTEL_INFO
	ldr	w8, [x0]
	cmp	w8, #4
	b.lt	LBB0_16
; %bb.15:
Lloh51:
	adrp	x8, _BLC_PWM_CTL2@GOTPAGE
Lloh52:
	ldr	x8, [x8, _BLC_PWM_CTL2@GOTPAGEOFF]
Lloh53:
	ldr	w0, [x8]
	bl	_I915_READ
	str	x0, [x20, #80]
LBB0_16:
	mov	x0, x19
	bl	_IS_MOBILE
	cbz	x0, LBB0_7
; %bb.17:
	mov	x0, x19
	bl	_IS_I830
	cbnz	w0, LBB0_7
; %bb.18:
Lloh54:
	adrp	x8, _LVDS@GOTPAGE
Lloh55:
	ldr	x8, [x8, _LVDS@GOTPAGEOFF]
	b	LBB0_6
LBB0_19:
	mov	x0, x19
	bl	_IS_GM45
	cbz	x0, LBB0_25
; %bb.20:
Lloh56:
	adrp	x8, _DPFC_CB_BASE@GOTPAGE
Lloh57:
	ldr	x8, [x8, _DPFC_CB_BASE@GOTPAGEOFF]
LBB0_21:
	ldr	w0, [x8]
	bl	_I915_READ
	str	x0, [x20, #32]
LBB0_22:
	ldr	w1, [x21]
	mov	x0, x19
	bl	_drm_core_check_feature
	cbz	w0, LBB0_24
; %bb.23:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_24:
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_i915_save_vga
LBB0_25:
Lloh58:
	adrp	x8, _FBC_CFB_BASE@GOTPAGE
Lloh59:
	ldr	x8, [x8, _FBC_CFB_BASE@GOTPAGEOFF]
Lloh60:
	ldr	w0, [x8]
	bl	_I915_READ
	str	x0, [x20, #24]
Lloh61:
	adrp	x8, _FBC_LL_BASE@GOTPAGE
Lloh62:
	ldr	x8, [x8, _FBC_LL_BASE@GOTPAGEOFF]
Lloh63:
	ldr	w0, [x8]
	bl	_I915_READ
	str	x0, [x20, #16]
Lloh64:
	adrp	x8, _FBC_CONTROL2@GOTPAGE
Lloh65:
	ldr	x8, [x8, _FBC_CONTROL2@GOTPAGEOFF]
Lloh66:
	ldr	w0, [x8]
	bl	_I915_READ
	str	x0, [x20, #8]
Lloh67:
	adrp	x8, _FBC_CONTROL@GOTPAGE
Lloh68:
	ldr	x8, [x8, _FBC_CONTROL@GOTPAGEOFF]
Lloh69:
	ldr	w0, [x8]
	bl	_I915_READ
	str	x0, [x20]
	b	LBB0_22
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh54, Lloh55
	.loh AdrpLdrGot	Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.cfi_endproc
                                        ; -- End function
	.comm	_DSPARB,4,2                     ; @DSPARB
	.comm	_DRIVER_MODESET,4,2             ; @DRIVER_MODESET
	.comm	_PCH_PP_CONTROL,4,2             ; @PCH_PP_CONTROL
	.comm	_BLC_PWM_PCH_CTL1,4,2           ; @BLC_PWM_PCH_CTL1
	.comm	_BLC_PWM_PCH_CTL2,4,2           ; @BLC_PWM_PCH_CTL2
	.comm	_BLC_PWM_CPU_CTL,4,2            ; @BLC_PWM_CPU_CTL
	.comm	_BLC_PWM_CPU_CTL2,4,2           ; @BLC_PWM_CPU_CTL2
	.comm	_PCH_LVDS,4,2                   ; @PCH_LVDS
	.comm	_PP_CONTROL,4,2                 ; @PP_CONTROL
	.comm	_PFIT_PGM_RATIOS,4,2            ; @PFIT_PGM_RATIOS
	.comm	_BLC_PWM_CTL,4,2                ; @BLC_PWM_CTL
	.comm	_BLC_HIST_CTL,4,2               ; @BLC_HIST_CTL
	.comm	_BLC_PWM_CTL2,4,2               ; @BLC_PWM_CTL2
	.comm	_LVDS,4,2                       ; @LVDS
	.comm	_PFIT_CONTROL,4,2               ; @PFIT_CONTROL
	.comm	_PCH_PP_ON_DELAYS,4,2           ; @PCH_PP_ON_DELAYS
	.comm	_PCH_PP_OFF_DELAYS,4,2          ; @PCH_PP_OFF_DELAYS
	.comm	_PCH_PP_DIVISOR,4,2             ; @PCH_PP_DIVISOR
	.comm	_PP_ON_DELAYS,4,2               ; @PP_ON_DELAYS
	.comm	_PP_OFF_DELAYS,4,2              ; @PP_OFF_DELAYS
	.comm	_PP_DIVISOR,4,2                 ; @PP_DIVISOR
	.comm	_ILK_DPFC_CB_BASE,4,2           ; @ILK_DPFC_CB_BASE
	.comm	_DPFC_CB_BASE,4,2               ; @DPFC_CB_BASE
	.comm	_FBC_CFB_BASE,4,2               ; @FBC_CFB_BASE
	.comm	_FBC_LL_BASE,4,2                ; @FBC_LL_BASE
	.comm	_FBC_CONTROL2,4,2               ; @FBC_CONTROL2
	.comm	_FBC_CONTROL,4,2                ; @FBC_CONTROL
	.no_dead_strip	_i915_save_display
.subsections_via_symbols
