	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function r700_vm_init
_r700_vm_init:                          ## @r700_vm_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	(%rdi), %r12
	movq	_R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	(%r12), %esi
	sarl	$12, %esi
	callq	_RADEON_WRITE
	movq	_R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	(%r12), %eax
	movl	4(%r12), %ecx
	leal	(%rax,%rcx), %esi
	decl	%esi
	sarl	$12, %esi
	callq	_RADEON_WRITE
	movq	_R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_RADEON_WRITE
	movq	_R700_ENABLE_L1_TLB@GOTPCREL(%rip), %rax
	movq	_R700_ENABLE_L1_FRAGMENT_PROCESSING@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	_R700_SYSTEM_ACCESS_MODE_IN_SYS@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	$5, %edi
	callq	_R700_EFFECTIVE_L1_TLB_SIZE
	movl	%eax, %r15d
	movl	$5, %edi
	callq	_R700_EFFECTIVE_L1_QUEUE_SIZE
	orl	%eax, %r15d
	orl	%ebx, %r15d
	movq	_R700_MC_VM_MD_L1_TLB0_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%r15d, %esi
	callq	_RADEON_WRITE
	movq	_R700_MC_VM_MD_L1_TLB1_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%r15d, %esi
	callq	_RADEON_WRITE
	movq	_R700_MC_VM_MD_L1_TLB2_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%r15d, %esi
	callq	_RADEON_WRITE
	movq	_R700_MC_VM_MB_L1_TLB0_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%r15d, %esi
	callq	_RADEON_WRITE
	movq	_R700_MC_VM_MB_L1_TLB1_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%r15d, %esi
	callq	_RADEON_WRITE
	movq	_R700_MC_VM_MB_L1_TLB2_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%r15d, %esi
	callq	_RADEON_WRITE
	movq	_R700_MC_VM_MB_L1_TLB3_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%r15d, %esi
	callq	_RADEON_WRITE
	movq	_R600_VM_L2_CACHE_EN@GOTPCREL(%rip), %rax
	movq	_R600_VM_L2_FRAG_PROC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	_R600_VM_ENABLE_PTE_CACHE_LRU_W@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	$7, %edi
	callq	_R700_VM_L2_CNTL_QUEUE_SIZE
	orl	%eax, %ebx
	movq	_R600_VM_L2_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_RADEON_WRITE
	movq	_R600_VM_L2_CNTL2@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_RADEON_WRITE
	xorl	%edi, %edi
	callq	_R700_VM_L2_CNTL3_BANK_SELECT
	movl	%eax, %ebx
	movl	$2, %edi
	callq	_R700_VM_L2_CNTL3_CACHE_UPDATE_MODE
	orl	%eax, %ebx
	movq	_R600_VM_L2_CNTL3@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_RADEON_WRITE
	movq	_R600_VM_ENABLE_CONTEXT@GOTPCREL(%rip), %rbx
	movq	_R600_VM_PAGE_TABLE_DEPTH_FLAT@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	orl	(%rbx), %r15d
	movq	_R600_VM_CONTEXT0_CNTL@GOTPCREL(%rip), %r13
	movq	(%r13), %rdi
	movl	%r15d, %esi
	callq	_RADEON_WRITE
	movl	(%rbx), %ebx
	notl	%ebx
	andl	%r15d, %ebx
	movq	(%r13), %rdi
	addq	$4, %rdi
	movl	%ebx, %esi
	callq	_RADEON_WRITE
	movq	(%r13), %rdi
	addq	$8, %rdi
	movl	%ebx, %esi
	callq	_RADEON_WRITE
	movq	(%r13), %rdi
	addq	$12, %rdi
	movl	%ebx, %esi
	callq	_RADEON_WRITE
	movq	(%r13), %rdi
	addq	$16, %rdi
	movl	%ebx, %esi
	callq	_RADEON_WRITE
	movq	(%r13), %rdi
	addq	$20, %rdi
	movl	%ebx, %esi
	callq	_RADEON_WRITE
	movq	(%r13), %rdi
	addq	$24, %rdi
	movl	%ebx, %esi
	callq	_RADEON_WRITE
	movq	(%r13), %rdi
	addq	$28, %rdi
	movl	%ebx, %esi
	callq	_RADEON_WRITE
	movq	_R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	8(%r12), %esi
	sarl	$12, %esi
	callq	_RADEON_WRITE
	movq	_R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	(%r12), %esi
	sarl	$12, %esi
	callq	_RADEON_WRITE
	movq	_R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	(%r12), %eax
	movl	4(%r12), %ecx
	leal	(%rax,%rcx), %esi
	decl	%esi
	sarl	$12, %esi
	callq	_RADEON_WRITE
	movq	%r14, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_r600_vm_flush_gart_range       ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR,8,3 ## @R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR
	.comm	_R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,8,3 ## @R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR
	.comm	_R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,8,3 ## @R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
	.comm	_R700_ENABLE_L1_TLB,4,2         ## @R700_ENABLE_L1_TLB
	.comm	_R700_ENABLE_L1_FRAGMENT_PROCESSING,4,2 ## @R700_ENABLE_L1_FRAGMENT_PROCESSING
	.comm	_R700_SYSTEM_ACCESS_MODE_IN_SYS,4,2 ## @R700_SYSTEM_ACCESS_MODE_IN_SYS
	.comm	_R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU,4,2 ## @R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
	.comm	_R700_MC_VM_MD_L1_TLB0_CNTL,8,3 ## @R700_MC_VM_MD_L1_TLB0_CNTL
	.comm	_R700_MC_VM_MD_L1_TLB1_CNTL,8,3 ## @R700_MC_VM_MD_L1_TLB1_CNTL
	.comm	_R700_MC_VM_MD_L1_TLB2_CNTL,8,3 ## @R700_MC_VM_MD_L1_TLB2_CNTL
	.comm	_R700_MC_VM_MB_L1_TLB0_CNTL,8,3 ## @R700_MC_VM_MB_L1_TLB0_CNTL
	.comm	_R700_MC_VM_MB_L1_TLB1_CNTL,8,3 ## @R700_MC_VM_MB_L1_TLB1_CNTL
	.comm	_R700_MC_VM_MB_L1_TLB2_CNTL,8,3 ## @R700_MC_VM_MB_L1_TLB2_CNTL
	.comm	_R700_MC_VM_MB_L1_TLB3_CNTL,8,3 ## @R700_MC_VM_MB_L1_TLB3_CNTL
	.comm	_R600_VM_L2_CACHE_EN,4,2        ## @R600_VM_L2_CACHE_EN
	.comm	_R600_VM_L2_FRAG_PROC,4,2       ## @R600_VM_L2_FRAG_PROC
	.comm	_R600_VM_ENABLE_PTE_CACHE_LRU_W,4,2 ## @R600_VM_ENABLE_PTE_CACHE_LRU_W
	.comm	_R600_VM_L2_CNTL,8,3            ## @R600_VM_L2_CNTL
	.comm	_R600_VM_L2_CNTL2,8,3           ## @R600_VM_L2_CNTL2
	.comm	_R600_VM_L2_CNTL3,8,3           ## @R600_VM_L2_CNTL3
	.comm	_R600_VM_ENABLE_CONTEXT,4,2     ## @R600_VM_ENABLE_CONTEXT
	.comm	_R600_VM_PAGE_TABLE_DEPTH_FLAT,4,2 ## @R600_VM_PAGE_TABLE_DEPTH_FLAT
	.comm	_R600_VM_CONTEXT0_CNTL,8,3      ## @R600_VM_CONTEXT0_CNTL
	.comm	_R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR,8,3 ## @R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
	.comm	_R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR,8,3 ## @R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR
	.comm	_R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR,8,3 ## @R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR
	.no_dead_strip	_r700_vm_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function r700_vm_init
_r700_vm_init:                          ; @r700_vm_init
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	x21, [x0]
Lloh0:
	adrp	x8, _R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR@GOTPAGE
Lloh1:
	ldr	x8, [x8, _R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR@GOTPAGEOFF]
Lloh2:
	ldr	x0, [x8]
	ldr	w8, [x21]
	asr	w1, w8, #12
	bl	_RADEON_WRITE
Lloh3:
	adrp	x8, _R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR@GOTPAGE
Lloh4:
	ldr	x8, [x8, _R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR@GOTPAGEOFF]
Lloh5:
	ldr	x0, [x8]
	ldp	w8, w9, [x21]
	add	w8, w8, w9
	sub	w8, w8, #1
	asr	w1, w8, #12
	bl	_RADEON_WRITE
Lloh6:
	adrp	x8, _R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR@GOTPAGE
Lloh7:
	ldr	x8, [x8, _R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR@GOTPAGEOFF]
Lloh8:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_RADEON_WRITE
Lloh9:
	adrp	x8, _R700_ENABLE_L1_TLB@GOTPAGE
Lloh10:
	ldr	x8, [x8, _R700_ENABLE_L1_TLB@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
Lloh12:
	adrp	x9, _R700_ENABLE_L1_FRAGMENT_PROCESSING@GOTPAGE
Lloh13:
	ldr	x9, [x9, _R700_ENABLE_L1_FRAGMENT_PROCESSING@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh15:
	adrp	x9, _R700_SYSTEM_ACCESS_MODE_IN_SYS@GOTPAGE
Lloh16:
	ldr	x9, [x9, _R700_SYSTEM_ACCESS_MODE_IN_SYS@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh18:
	adrp	x9, _R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU@GOTPAGE
Lloh19:
	ldr	x9, [x9, _R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	orr	w20, w8, w9
	mov	w0, #5
	bl	_R700_EFFECTIVE_L1_TLB_SIZE
	orr	w20, w20, w0
	mov	w0, #5
	bl	_R700_EFFECTIVE_L1_QUEUE_SIZE
	orr	w20, w20, w0
Lloh21:
	adrp	x8, _R700_MC_VM_MD_L1_TLB0_CNTL@GOTPAGE
Lloh22:
	ldr	x8, [x8, _R700_MC_VM_MD_L1_TLB0_CNTL@GOTPAGEOFF]
Lloh23:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_RADEON_WRITE
Lloh24:
	adrp	x8, _R700_MC_VM_MD_L1_TLB1_CNTL@GOTPAGE
Lloh25:
	ldr	x8, [x8, _R700_MC_VM_MD_L1_TLB1_CNTL@GOTPAGEOFF]
Lloh26:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_RADEON_WRITE
Lloh27:
	adrp	x8, _R700_MC_VM_MD_L1_TLB2_CNTL@GOTPAGE
Lloh28:
	ldr	x8, [x8, _R700_MC_VM_MD_L1_TLB2_CNTL@GOTPAGEOFF]
Lloh29:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_RADEON_WRITE
Lloh30:
	adrp	x8, _R700_MC_VM_MB_L1_TLB0_CNTL@GOTPAGE
Lloh31:
	ldr	x8, [x8, _R700_MC_VM_MB_L1_TLB0_CNTL@GOTPAGEOFF]
Lloh32:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_RADEON_WRITE
Lloh33:
	adrp	x8, _R700_MC_VM_MB_L1_TLB1_CNTL@GOTPAGE
Lloh34:
	ldr	x8, [x8, _R700_MC_VM_MB_L1_TLB1_CNTL@GOTPAGEOFF]
Lloh35:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_RADEON_WRITE
Lloh36:
	adrp	x8, _R700_MC_VM_MB_L1_TLB2_CNTL@GOTPAGE
Lloh37:
	ldr	x8, [x8, _R700_MC_VM_MB_L1_TLB2_CNTL@GOTPAGEOFF]
Lloh38:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_RADEON_WRITE
Lloh39:
	adrp	x8, _R700_MC_VM_MB_L1_TLB3_CNTL@GOTPAGE
Lloh40:
	ldr	x8, [x8, _R700_MC_VM_MB_L1_TLB3_CNTL@GOTPAGEOFF]
Lloh41:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_RADEON_WRITE
Lloh42:
	adrp	x8, _R600_VM_L2_CACHE_EN@GOTPAGE
Lloh43:
	ldr	x8, [x8, _R600_VM_L2_CACHE_EN@GOTPAGEOFF]
Lloh44:
	ldr	w8, [x8]
Lloh45:
	adrp	x9, _R600_VM_L2_FRAG_PROC@GOTPAGE
Lloh46:
	ldr	x9, [x9, _R600_VM_L2_FRAG_PROC@GOTPAGEOFF]
Lloh47:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh48:
	adrp	x9, _R600_VM_ENABLE_PTE_CACHE_LRU_W@GOTPAGE
Lloh49:
	ldr	x9, [x9, _R600_VM_ENABLE_PTE_CACHE_LRU_W@GOTPAGEOFF]
Lloh50:
	ldr	w9, [x9]
	orr	w20, w8, w9
	mov	w0, #7
	bl	_R700_VM_L2_CNTL_QUEUE_SIZE
	orr	w1, w20, w0
Lloh51:
	adrp	x8, _R600_VM_L2_CNTL@GOTPAGE
Lloh52:
	ldr	x8, [x8, _R600_VM_L2_CNTL@GOTPAGEOFF]
Lloh53:
	ldr	x0, [x8]
	bl	_RADEON_WRITE
Lloh54:
	adrp	x8, _R600_VM_L2_CNTL2@GOTPAGE
Lloh55:
	ldr	x8, [x8, _R600_VM_L2_CNTL2@GOTPAGEOFF]
Lloh56:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_RADEON_WRITE
	mov	w0, #0
	bl	_R700_VM_L2_CNTL3_BANK_SELECT
	mov	x20, x0
	mov	w0, #2
	bl	_R700_VM_L2_CNTL3_CACHE_UPDATE_MODE
	orr	w1, w0, w20
Lloh57:
	adrp	x8, _R600_VM_L2_CNTL3@GOTPAGE
Lloh58:
	ldr	x8, [x8, _R600_VM_L2_CNTL3@GOTPAGEOFF]
Lloh59:
	ldr	x0, [x8]
	bl	_RADEON_WRITE
Lloh60:
	adrp	x22, _R600_VM_ENABLE_CONTEXT@GOTPAGE
Lloh61:
	ldr	x22, [x22, _R600_VM_ENABLE_CONTEXT@GOTPAGEOFF]
Lloh62:
	adrp	x8, _R600_VM_PAGE_TABLE_DEPTH_FLAT@GOTPAGE
Lloh63:
	ldr	x8, [x8, _R600_VM_PAGE_TABLE_DEPTH_FLAT@GOTPAGEOFF]
	ldr	w9, [x22]
Lloh64:
	ldr	w8, [x8]
	orr	w20, w8, w9
Lloh65:
	adrp	x23, _R600_VM_CONTEXT0_CNTL@GOTPAGE
Lloh66:
	ldr	x23, [x23, _R600_VM_CONTEXT0_CNTL@GOTPAGEOFF]
	ldr	x0, [x23]
	mov	x1, x20
	bl	_RADEON_WRITE
	ldr	w8, [x22]
	bic	w20, w20, w8
	ldr	x8, [x23]
	add	x0, x8, #4
	mov	x1, x20
	bl	_RADEON_WRITE
	ldr	x8, [x23]
	add	x0, x8, #8
	mov	x1, x20
	bl	_RADEON_WRITE
	ldr	x8, [x23]
	add	x0, x8, #12
	mov	x1, x20
	bl	_RADEON_WRITE
	ldr	x8, [x23]
	add	x0, x8, #16
	mov	x1, x20
	bl	_RADEON_WRITE
	ldr	x8, [x23]
	add	x0, x8, #20
	mov	x1, x20
	bl	_RADEON_WRITE
	ldr	x8, [x23]
	add	x0, x8, #24
	mov	x1, x20
	bl	_RADEON_WRITE
	ldr	x8, [x23]
	add	x0, x8, #28
	mov	x1, x20
	bl	_RADEON_WRITE
Lloh67:
	adrp	x8, _R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPAGE
Lloh68:
	ldr	x8, [x8, _R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPAGEOFF]
Lloh69:
	ldr	x0, [x8]
	ldr	w8, [x21, #8]
	asr	w1, w8, #12
	bl	_RADEON_WRITE
Lloh70:
	adrp	x8, _R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPAGE
Lloh71:
	ldr	x8, [x8, _R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPAGEOFF]
Lloh72:
	ldr	x0, [x8]
	ldr	w8, [x21]
	asr	w1, w8, #12
	bl	_RADEON_WRITE
Lloh73:
	adrp	x8, _R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPAGE
Lloh74:
	ldr	x8, [x8, _R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPAGEOFF]
Lloh75:
	ldr	x0, [x8]
	ldp	w8, w9, [x21]
	add	w8, w8, w9
	sub	w8, w8, #1
	asr	w1, w8, #12
	bl	_RADEON_WRITE
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_r600_vm_flush_gart_range
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR,8,3 ; @R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR
	.comm	_R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,8,3 ; @R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR
	.comm	_R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,8,3 ; @R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
	.comm	_R700_ENABLE_L1_TLB,4,2         ; @R700_ENABLE_L1_TLB
	.comm	_R700_ENABLE_L1_FRAGMENT_PROCESSING,4,2 ; @R700_ENABLE_L1_FRAGMENT_PROCESSING
	.comm	_R700_SYSTEM_ACCESS_MODE_IN_SYS,4,2 ; @R700_SYSTEM_ACCESS_MODE_IN_SYS
	.comm	_R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU,4,2 ; @R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
	.comm	_R700_MC_VM_MD_L1_TLB0_CNTL,8,3 ; @R700_MC_VM_MD_L1_TLB0_CNTL
	.comm	_R700_MC_VM_MD_L1_TLB1_CNTL,8,3 ; @R700_MC_VM_MD_L1_TLB1_CNTL
	.comm	_R700_MC_VM_MD_L1_TLB2_CNTL,8,3 ; @R700_MC_VM_MD_L1_TLB2_CNTL
	.comm	_R700_MC_VM_MB_L1_TLB0_CNTL,8,3 ; @R700_MC_VM_MB_L1_TLB0_CNTL
	.comm	_R700_MC_VM_MB_L1_TLB1_CNTL,8,3 ; @R700_MC_VM_MB_L1_TLB1_CNTL
	.comm	_R700_MC_VM_MB_L1_TLB2_CNTL,8,3 ; @R700_MC_VM_MB_L1_TLB2_CNTL
	.comm	_R700_MC_VM_MB_L1_TLB3_CNTL,8,3 ; @R700_MC_VM_MB_L1_TLB3_CNTL
	.comm	_R600_VM_L2_CACHE_EN,4,2        ; @R600_VM_L2_CACHE_EN
	.comm	_R600_VM_L2_FRAG_PROC,4,2       ; @R600_VM_L2_FRAG_PROC
	.comm	_R600_VM_ENABLE_PTE_CACHE_LRU_W,4,2 ; @R600_VM_ENABLE_PTE_CACHE_LRU_W
	.comm	_R600_VM_L2_CNTL,8,3            ; @R600_VM_L2_CNTL
	.comm	_R600_VM_L2_CNTL2,8,3           ; @R600_VM_L2_CNTL2
	.comm	_R600_VM_L2_CNTL3,8,3           ; @R600_VM_L2_CNTL3
	.comm	_R600_VM_ENABLE_CONTEXT,4,2     ; @R600_VM_ENABLE_CONTEXT
	.comm	_R600_VM_PAGE_TABLE_DEPTH_FLAT,4,2 ; @R600_VM_PAGE_TABLE_DEPTH_FLAT
	.comm	_R600_VM_CONTEXT0_CNTL,8,3      ; @R600_VM_CONTEXT0_CNTL
	.comm	_R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR,8,3 ; @R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
	.comm	_R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR,8,3 ; @R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR
	.comm	_R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR,8,3 ; @R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR
	.no_dead_strip	_r700_vm_init
.subsections_via_symbols
