	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_legacy_tmds_int_mode_set
_radeon_legacy_tmds_int_mode_set:       ## @radeon_legacy_tmds_int_mode_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r15
	movq	%rdi, %rbx
	movq	8(%rdi), %rax
	movq	(%rax), %r14
	movl	(%rdi), %edi
	callq	_to_radeon_crtc
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
	movq	%rbx, -48(%rbp)                 ## 8-byte Spill
	movq	%rbx, %rdi
	callq	_to_radeon_encoder
	movq	%rax, %r13
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	movq	_RADEON_TMDS_PLL_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %ecx
	andl	$1048575, %ecx                  ## imm = 0xFFFFF
	movq	(%r14), %rdx
	movq	_CHIP_RV280@GOTPCREL(%rip), %rdi
	leal	4194304(%rcx), %r12d
	movl	%eax, %ebx
	xorl	$4194304, %ebx                  ## imm = 0x400000
	cmpq	(%rdi), %rdx
	cmovnel	%eax, %ebx
	cmovnel	%ecx, %r12d
	movq	%r13, -64(%rbp)                 ## 8-byte Spill
	movq	8(%r13), %rax
	testq	%rax, %rax
	je	LBB0_5
## %bb.1:
	movq	(%rax), %rax
	movq	(%rax), %rdx
	testq	%rdx, %rdx
	je	LBB0_5
## %bb.2:
	movslq	(%r15), %rcx
	imulq	$1717986919, %rcx, %rcx         ## imm = 0x66666667
	movq	%rcx, %rsi
	shrq	$63, %rsi
	sarq	$34, %rcx
	addl	%esi, %ecx
	movslq	%ecx, %rcx
	cmpq	%rcx, %rdx
	jle	LBB0_6
## %bb.3:
	movq	%rdi, %r15
	xorl	%edx, %edx
	jmp	LBB0_12
LBB0_5:
	movq	%rdi, %r15
	jmp	LBB0_13
LBB0_6:
	movq	16(%rax), %rsi
	movq	%rdi, %r15
	testq	%rsi, %rsi
	je	LBB0_13
## %bb.7:
	movl	$1, %edx
	cmpq	%rcx, %rsi
	jg	LBB0_12
## %bb.8:
	movq	32(%rax), %rsi
	testq	%rsi, %rsi
	je	LBB0_13
## %bb.9:
	movl	$2, %edx
	cmpq	%rcx, %rsi
	jg	LBB0_12
## %bb.10:
	movq	48(%rax), %rsi
	testq	%rsi, %rsi
	je	LBB0_13
## %bb.11:
	movl	$3, %edx
	cmpq	%rcx, %rsi
	jle	LBB0_13
LBB0_12:
	shlq	$4, %rdx
	movl	8(%rax,%rdx), %r12d
LBB0_13:
	movq	%r14, %rdi
	callq	_ASIC_IS_R300
	testq	%rax, %rax
	je	LBB0_15
## %bb.14:
	cmpl	$1048575, %r12d                 ## imm = 0xFFFFF
	jbe	LBB0_17
	jmp	LBB0_18
LBB0_15:
	movq	(%r14), %rax
	cmpq	(%r15), %rax
	jne	LBB0_18
## %bb.16:
	cmpl	$1048576, %r12d                 ## imm = 0x100000
	jae	LBB0_18
LBB0_17:
	andl	$-1048576, %ebx                 ## imm = 0xFFF00000
	orl	%ebx, %r12d
LBB0_18:
	movq	_RADEON_TMDS_TRANSMITTER_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_RADEON_TMDS_TRANSMITTER_PLLRST@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r13d
	notl	%r13d
	andl	%eax, %r13d
	movq	(%r14), %rax
	movq	_CHIP_R200@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_21
## %bb.19:
	movq	_CHIP_R100@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_21
## %bb.20:
	movq	%r14, %rdi
	callq	_ASIC_IS_R300
	testq	%rax, %rax
	je	LBB0_30
LBB0_21:
	movq	_RADEON_TMDS_TRANSMITTER_PLLEN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r13d
LBB0_22:
	movq	_RADEON_FP_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_RADEON_FP_CRTC_DONT_SHADOW_VPAR@GOTPCREL(%rip), %rcx
	movq	_RADEON_FP_CRTC_DONT_SHADOW_HEND@GOTPCREL(%rip), %rdx
	orl	(%rcx), %eax
	orl	(%rdx), %eax
	movq	_RADEON_FP_FPON@GOTPCREL(%rip), %rcx
	movq	_RADEON_FP_TMDS_EN@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r15d
	movq	_RADEON_FP_RMX_HVSYNC_CONTROL_EN@GOTPCREL(%rip), %rdx
	movq	_RADEON_FP_DFP_SYNC_SEL@GOTPCREL(%rip), %rsi
	movq	_RADEON_FP_CRT_SYNC_SEL@GOTPCREL(%rip), %rdi
	movq	_RADEON_FP_CRTC_LOCK_8DOT@GOTPCREL(%rip), %rbx
	movq	_RADEON_FP_USE_SHADOW_EN@GOTPCREL(%rip), %r8
	movq	_RADEON_FP_CRTC_USE_SHADOW_VEND@GOTPCREL(%rip), %r9
	movq	_RADEON_FP_CRT_SYNC_ALT@GOTPCREL(%rip), %r10
	orl	(%rcx), %r15d
	orl	(%rdx), %r15d
	orl	(%rsi), %r15d
	orl	(%rdi), %r15d
	orl	(%rbx), %r15d
	orl	(%r8), %r15d
	orl	(%r9), %r15d
	orl	(%r10), %r15d
	notl	%r15d
	andl	%eax, %r15d
	movq	_RADEON_FP_PANEL_FORMAT@GOTPCREL(%rip), %rax
	orl	(%rax), %r15d
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rbx
	movq	%r14, %rdi
	callq	_ASIC_IS_R300
	testq	%rbx, %rbx
	je	LBB0_26
## %bb.23:
	testq	%rax, %rax
	jne	LBB0_25
## %bb.24:
	movq	(%r14), %rax
	movq	_CHIP_R200@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_32
LBB0_25:
	movq	_R200_FP_SOURCE_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r15d
	movq	_R200_FP_SOURCE_SEL_CRTC2@GOTPCREL(%rip), %rax
	jmp	LBB0_33
LBB0_26:
	testq	%rax, %rax
	jne	LBB0_28
## %bb.27:
	movq	(%r14), %rax
	movq	_CHIP_R200@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_37
LBB0_28:
	movq	_R200_FP_SOURCE_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r15d
	movq	-64(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rax
	movq	_RMX_OFF@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_31
## %bb.29:
	movq	_R200_FP_SOURCE_SEL_CRTC1@GOTPCREL(%rip), %rax
	jmp	LBB0_33
LBB0_30:
	movq	_RADEON_TMDS_TRANSMITTER_PLLEN@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	jmp	LBB0_22
LBB0_31:
	movq	_R200_FP_SOURCE_SEL_RMX@GOTPCREL(%rip), %rax
	jmp	LBB0_33
LBB0_32:
	movq	_RADEON_FP_SEL_CRTC2@GOTPCREL(%rip), %rax
LBB0_33:
	orl	(%rax), %r15d
LBB0_34:
	movq	_RADEON_TMDS_PLL_CNTL@GOTPCREL(%rip), %rax
	movq	_RADEON_FP_GEN_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_RADEON_TMDS_TRANSMITTER_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r13d, %esi
	callq	_WREG32
	movl	(%rbx), %edi
	movl	%r15d, %esi
	callq	_WREG32
	cmpq	$0, 8(%r14)
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rsi
	je	LBB0_36
## %bb.35:
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_atombios_encoder_crtc_scratch_regs ## TAILCALL
LBB0_36:
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_combios_encoder_crtc_scratch_regs ## TAILCALL
LBB0_37:
	movq	_RADEON_FP_SEL_CRTC2@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r15d
	jmp	LBB0_34
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"\n"

	.comm	_RADEON_TMDS_PLL_CNTL,4,2       ## @RADEON_TMDS_PLL_CNTL
	.comm	_CHIP_RV280,8,3                 ## @CHIP_RV280
	.comm	_RADEON_TMDS_TRANSMITTER_CNTL,4,2 ## @RADEON_TMDS_TRANSMITTER_CNTL
	.comm	_RADEON_TMDS_TRANSMITTER_PLLRST,4,2 ## @RADEON_TMDS_TRANSMITTER_PLLRST
	.comm	_CHIP_R200,8,3                  ## @CHIP_R200
	.comm	_CHIP_R100,8,3                  ## @CHIP_R100
	.comm	_RADEON_TMDS_TRANSMITTER_PLLEN,4,2 ## @RADEON_TMDS_TRANSMITTER_PLLEN
	.comm	_RADEON_FP_GEN_CNTL,4,2         ## @RADEON_FP_GEN_CNTL
	.comm	_RADEON_FP_CRTC_DONT_SHADOW_VPAR,4,2 ## @RADEON_FP_CRTC_DONT_SHADOW_VPAR
	.comm	_RADEON_FP_CRTC_DONT_SHADOW_HEND,4,2 ## @RADEON_FP_CRTC_DONT_SHADOW_HEND
	.comm	_RADEON_FP_FPON,4,2             ## @RADEON_FP_FPON
	.comm	_RADEON_FP_TMDS_EN,4,2          ## @RADEON_FP_TMDS_EN
	.comm	_RADEON_FP_RMX_HVSYNC_CONTROL_EN,4,2 ## @RADEON_FP_RMX_HVSYNC_CONTROL_EN
	.comm	_RADEON_FP_DFP_SYNC_SEL,4,2     ## @RADEON_FP_DFP_SYNC_SEL
	.comm	_RADEON_FP_CRT_SYNC_SEL,4,2     ## @RADEON_FP_CRT_SYNC_SEL
	.comm	_RADEON_FP_CRTC_LOCK_8DOT,4,2   ## @RADEON_FP_CRTC_LOCK_8DOT
	.comm	_RADEON_FP_USE_SHADOW_EN,4,2    ## @RADEON_FP_USE_SHADOW_EN
	.comm	_RADEON_FP_CRTC_USE_SHADOW_VEND,4,2 ## @RADEON_FP_CRTC_USE_SHADOW_VEND
	.comm	_RADEON_FP_CRT_SYNC_ALT,4,2     ## @RADEON_FP_CRT_SYNC_ALT
	.comm	_RADEON_FP_PANEL_FORMAT,4,2     ## @RADEON_FP_PANEL_FORMAT
	.comm	_R200_FP_SOURCE_SEL_MASK,4,2    ## @R200_FP_SOURCE_SEL_MASK
	.comm	_RMX_OFF,8,3                    ## @RMX_OFF
	.comm	_R200_FP_SOURCE_SEL_RMX,4,2     ## @R200_FP_SOURCE_SEL_RMX
	.comm	_R200_FP_SOURCE_SEL_CRTC1,4,2   ## @R200_FP_SOURCE_SEL_CRTC1
	.comm	_RADEON_FP_SEL_CRTC2,4,2        ## @RADEON_FP_SEL_CRTC2
	.comm	_R200_FP_SOURCE_SEL_CRTC2,4,2   ## @R200_FP_SOURCE_SEL_CRTC2
	.no_dead_strip	_radeon_legacy_tmds_int_mode_set
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_legacy_tmds_int_mode_set
_radeon_legacy_tmds_int_mode_set:       ; @radeon_legacy_tmds_int_mode_set
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x24, x1
	mov	x19, x0
	ldr	x8, [x0, #8]
	ldr	x20, [x8]
	ldr	w0, [x0]
	bl	_to_radeon_crtc
	str	x0, [sp, #8]                    ; 8-byte Folded Spill
	mov	x0, x19
	bl	_to_radeon_encoder
	mov	x23, x0
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_KMS
Lloh2:
	adrp	x21, _RADEON_TMDS_PLL_CNTL@GOTPAGE
Lloh3:
	ldr	x21, [x21, _RADEON_TMDS_PLL_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
	and	w8, w0, #0xfffff
	ldr	x9, [x20]
Lloh4:
	adrp	x27, _CHIP_RV280@GOTPAGE
Lloh5:
	ldr	x27, [x27, _CHIP_RV280@GOTPAGEOFF]
	ldr	x10, [x27]
	mov	w11, #4194304
	bfxil	w11, w0, #0, #20
	eor	w12, w0, #0x400000
	cmp	x9, x10
	csel	w26, w12, w0, eq
	csel	w22, w11, w8, eq
	ldr	x8, [x23, #8]
	cbz	x8, LBB0_13
; %bb.1:
	ldr	x8, [x8]
	ldr	x10, [x8]
	cbz	x10, LBB0_13
; %bb.2:
	ldrsw	x9, [x24]
	mov	w11, #26215
	movk	w11, #26214, lsl #16
	mul	x9, x9, x11
	lsr	x11, x9, #63
	asr	x9, x9, #34
	add	w9, w9, w11
	sxtw	x9, w9
	cmp	x10, x9
	b.le	LBB0_4
; %bb.3:
	mov	x9, #0
	b	LBB0_12
LBB0_4:
	ldr	x10, [x8, #16]
	cbz	x10, LBB0_13
; %bb.5:
	cmp	x10, x9
	b.le	LBB0_7
; %bb.6:
	mov	w9, #1
	b	LBB0_12
LBB0_7:
	ldr	x10, [x8, #32]
	cbz	x10, LBB0_13
; %bb.8:
	cmp	x10, x9
	b.le	LBB0_10
; %bb.9:
	mov	w9, #2
	b	LBB0_12
LBB0_10:
	ldr	x10, [x8, #48]
	cmp	x10, #0
	ccmp	x10, x9, #4, ne
	b.le	LBB0_13
; %bb.11:
	mov	w9, #3
LBB0_12:
	add	x8, x8, x9, lsl #4
	ldr	w22, [x8, #8]
LBB0_13:
	mov	x0, x20
	bl	_ASIC_IS_R300
	cbz	x0, LBB0_15
; %bb.14:
	lsr	w8, w22, #20
	cbz	w8, LBB0_17
	b	LBB0_18
LBB0_15:
	ldr	x8, [x20]
	ldr	x9, [x27]
	cmp	x8, x9
	b.ne	LBB0_18
; %bb.16:
	cmp	w22, #256, lsl #12              ; =1048576
	b.hs	LBB0_18
LBB0_17:
	and	w8, w26, #0xfff00000
	orr	w22, w22, w8
LBB0_18:
Lloh6:
	adrp	x27, _RADEON_TMDS_TRANSMITTER_CNTL@GOTPAGE
Lloh7:
	ldr	x27, [x27, _RADEON_TMDS_TRANSMITTER_CNTL@GOTPAGEOFF]
	ldr	w0, [x27]
	bl	_RREG32
Lloh8:
	adrp	x8, _RADEON_TMDS_TRANSMITTER_PLLRST@GOTPAGE
Lloh9:
	ldr	x8, [x8, _RADEON_TMDS_TRANSMITTER_PLLRST@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	bic	w24, w0, w8
	ldr	x8, [x20]
Lloh11:
	adrp	x28, _CHIP_R200@GOTPAGE
Lloh12:
	ldr	x28, [x28, _CHIP_R200@GOTPAGEOFF]
	ldr	x9, [x28]
Lloh13:
	adrp	x10, _CHIP_R100@GOTPAGE
Lloh14:
	ldr	x10, [x10, _CHIP_R100@GOTPAGEOFF]
Lloh15:
	ldr	x10, [x10]
	cmp	x8, x9
	ccmp	x8, x10, #4, ne
	b.eq	LBB0_20
; %bb.19:
	mov	x0, x20
	bl	_ASIC_IS_R300
	cbz	x0, LBB0_29
LBB0_20:
Lloh16:
	adrp	x8, _RADEON_TMDS_TRANSMITTER_PLLEN@GOTPAGE
Lloh17:
	ldr	x8, [x8, _RADEON_TMDS_TRANSMITTER_PLLEN@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	bic	w24, w24, w8
LBB0_21:
Lloh19:
	adrp	x8, _RADEON_FP_GEN_CNTL@GOTPAGE
Lloh20:
	ldr	x8, [x8, _RADEON_FP_GEN_CNTL@GOTPAGEOFF]
Lloh21:
	ldr	w0, [x8]
	bl	_RREG32
Lloh22:
	adrp	x8, _RADEON_FP_CRTC_DONT_SHADOW_VPAR@GOTPAGE
Lloh23:
	ldr	x8, [x8, _RADEON_FP_CRTC_DONT_SHADOW_VPAR@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
Lloh25:
	adrp	x9, _RADEON_FP_CRTC_DONT_SHADOW_HEND@GOTPAGE
Lloh26:
	ldr	x9, [x9, _RADEON_FP_CRTC_DONT_SHADOW_HEND@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w8, w8, w9
Lloh28:
	adrp	x9, _RADEON_FP_FPON@GOTPAGE
Lloh29:
	ldr	x9, [x9, _RADEON_FP_FPON@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
Lloh31:
	adrp	x10, _RADEON_FP_TMDS_EN@GOTPAGE
Lloh32:
	ldr	x10, [x10, _RADEON_FP_TMDS_EN@GOTPAGEOFF]
Lloh33:
	ldr	w10, [x10]
Lloh34:
	adrp	x11, _RADEON_FP_RMX_HVSYNC_CONTROL_EN@GOTPAGE
Lloh35:
	ldr	x11, [x11, _RADEON_FP_RMX_HVSYNC_CONTROL_EN@GOTPAGEOFF]
Lloh36:
	ldr	w11, [x11]
Lloh37:
	adrp	x12, _RADEON_FP_DFP_SYNC_SEL@GOTPAGE
Lloh38:
	ldr	x12, [x12, _RADEON_FP_DFP_SYNC_SEL@GOTPAGEOFF]
Lloh39:
	ldr	w12, [x12]
Lloh40:
	adrp	x13, _RADEON_FP_CRT_SYNC_SEL@GOTPAGE
Lloh41:
	ldr	x13, [x13, _RADEON_FP_CRT_SYNC_SEL@GOTPAGEOFF]
Lloh42:
	ldr	w13, [x13]
Lloh43:
	adrp	x14, _RADEON_FP_CRTC_LOCK_8DOT@GOTPAGE
Lloh44:
	ldr	x14, [x14, _RADEON_FP_CRTC_LOCK_8DOT@GOTPAGEOFF]
Lloh45:
	ldr	w14, [x14]
Lloh46:
	adrp	x15, _RADEON_FP_USE_SHADOW_EN@GOTPAGE
Lloh47:
	ldr	x15, [x15, _RADEON_FP_USE_SHADOW_EN@GOTPAGEOFF]
Lloh48:
	ldr	w15, [x15]
Lloh49:
	adrp	x16, _RADEON_FP_CRTC_USE_SHADOW_VEND@GOTPAGE
Lloh50:
	ldr	x16, [x16, _RADEON_FP_CRTC_USE_SHADOW_VEND@GOTPAGEOFF]
Lloh51:
	ldr	w16, [x16]
Lloh52:
	adrp	x17, _RADEON_FP_CRT_SYNC_ALT@GOTPAGE
Lloh53:
	ldr	x17, [x17, _RADEON_FP_CRT_SYNC_ALT@GOTPAGEOFF]
Lloh54:
	ldr	w17, [x17]
	orr	w9, w10, w9
	orr	w9, w9, w11
	orr	w9, w9, w12
	orr	w9, w9, w13
	orr	w9, w9, w14
	orr	w9, w9, w15
	orr	w9, w9, w16
	orr	w9, w9, w17
	bic	w8, w8, w9
Lloh55:
	adrp	x9, _RADEON_FP_PANEL_FORMAT@GOTPAGE
Lloh56:
	ldr	x9, [x9, _RADEON_FP_PANEL_FORMAT@GOTPAGEOFF]
Lloh57:
	ldr	w9, [x9]
	orr	w25, w8, w9
	ldr	x8, [sp, #8]                    ; 8-byte Folded Reload
	ldr	x26, [x8]
	mov	x0, x20
	bl	_ASIC_IS_R300
	cbz	x26, LBB0_25
; %bb.22:
	cbnz	x0, LBB0_24
; %bb.23:
	ldr	x8, [x20]
	ldr	x9, [x28]
	cmp	x8, x9
	b.ne	LBB0_32
LBB0_24:
Lloh58:
	adrp	x8, _R200_FP_SOURCE_SEL_MASK@GOTPAGE
Lloh59:
	ldr	x8, [x8, _R200_FP_SOURCE_SEL_MASK@GOTPAGEOFF]
Lloh60:
	ldr	w8, [x8]
	bic	w8, w25, w8
Lloh61:
	adrp	x9, _R200_FP_SOURCE_SEL_CRTC2@GOTPAGE
Lloh62:
	ldr	x9, [x9, _R200_FP_SOURCE_SEL_CRTC2@GOTPAGEOFF]
Lloh63:
	ldr	w9, [x9]
	orr	w23, w8, w9
	b	LBB0_34
LBB0_25:
	cbnz	x0, LBB0_27
; %bb.26:
	ldr	x8, [x20]
	ldr	x9, [x28]
	cmp	x8, x9
	b.ne	LBB0_33
LBB0_27:
Lloh64:
	adrp	x8, _R200_FP_SOURCE_SEL_MASK@GOTPAGE
Lloh65:
	ldr	x8, [x8, _R200_FP_SOURCE_SEL_MASK@GOTPAGEOFF]
Lloh66:
	ldr	w8, [x8]
	bic	w8, w25, w8
	ldr	x9, [x23]
Lloh67:
	adrp	x10, _RMX_OFF@GOTPAGE
Lloh68:
	ldr	x10, [x10, _RMX_OFF@GOTPAGEOFF]
Lloh69:
	ldr	x10, [x10]
	cmp	x9, x10
	b.ne	LBB0_30
; %bb.28:
Lloh70:
	adrp	x9, _R200_FP_SOURCE_SEL_CRTC1@GOTPAGE
Lloh71:
	ldr	x9, [x9, _R200_FP_SOURCE_SEL_CRTC1@GOTPAGEOFF]
	b	LBB0_31
LBB0_29:
Lloh72:
	adrp	x8, _RADEON_TMDS_TRANSMITTER_PLLEN@GOTPAGE
Lloh73:
	ldr	x8, [x8, _RADEON_TMDS_TRANSMITTER_PLLEN@GOTPAGEOFF]
Lloh74:
	ldr	w8, [x8]
	orr	w24, w8, w24
	b	LBB0_21
LBB0_30:
Lloh75:
	adrp	x9, _R200_FP_SOURCE_SEL_RMX@GOTPAGE
Lloh76:
	ldr	x9, [x9, _R200_FP_SOURCE_SEL_RMX@GOTPAGEOFF]
LBB0_31:
	ldr	w9, [x9]
	orr	w23, w9, w8
	b	LBB0_34
LBB0_32:
Lloh77:
	adrp	x8, _RADEON_FP_SEL_CRTC2@GOTPAGE
Lloh78:
	ldr	x8, [x8, _RADEON_FP_SEL_CRTC2@GOTPAGEOFF]
Lloh79:
	ldr	w8, [x8]
	orr	w23, w8, w25
	b	LBB0_34
LBB0_33:
Lloh80:
	adrp	x8, _RADEON_FP_SEL_CRTC2@GOTPAGE
Lloh81:
	ldr	x8, [x8, _RADEON_FP_SEL_CRTC2@GOTPAGEOFF]
Lloh82:
	ldr	w8, [x8]
	bic	w23, w25, w8
LBB0_34:
Lloh83:
	adrp	x25, _RADEON_FP_GEN_CNTL@GOTPAGE
Lloh84:
	ldr	x25, [x25, _RADEON_FP_GEN_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	mov	x1, x22
	bl	_WREG32
	ldr	w0, [x27]
	mov	x1, x24
	bl	_WREG32
Lloh85:
	ldr	w0, [x25]
	mov	x1, x23
	bl	_WREG32
	ldr	x8, [x20, #8]
	ldr	x9, [sp, #8]                    ; 8-byte Folded Reload
	ldr	x1, [x9]
	mov	x0, x19
	cbz	x8, LBB0_36
; %bb.35:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	b	_radeon_atombios_encoder_crtc_scratch_regs
LBB0_36:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	b	_radeon_combios_encoder_crtc_scratch_regs
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGot	Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGot	Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"\n"

	.comm	_RADEON_TMDS_PLL_CNTL,4,2       ; @RADEON_TMDS_PLL_CNTL
	.comm	_CHIP_RV280,8,3                 ; @CHIP_RV280
	.comm	_RADEON_TMDS_TRANSMITTER_CNTL,4,2 ; @RADEON_TMDS_TRANSMITTER_CNTL
	.comm	_RADEON_TMDS_TRANSMITTER_PLLRST,4,2 ; @RADEON_TMDS_TRANSMITTER_PLLRST
	.comm	_CHIP_R200,8,3                  ; @CHIP_R200
	.comm	_CHIP_R100,8,3                  ; @CHIP_R100
	.comm	_RADEON_TMDS_TRANSMITTER_PLLEN,4,2 ; @RADEON_TMDS_TRANSMITTER_PLLEN
	.comm	_RADEON_FP_GEN_CNTL,4,2         ; @RADEON_FP_GEN_CNTL
	.comm	_RADEON_FP_CRTC_DONT_SHADOW_VPAR,4,2 ; @RADEON_FP_CRTC_DONT_SHADOW_VPAR
	.comm	_RADEON_FP_CRTC_DONT_SHADOW_HEND,4,2 ; @RADEON_FP_CRTC_DONT_SHADOW_HEND
	.comm	_RADEON_FP_FPON,4,2             ; @RADEON_FP_FPON
	.comm	_RADEON_FP_TMDS_EN,4,2          ; @RADEON_FP_TMDS_EN
	.comm	_RADEON_FP_RMX_HVSYNC_CONTROL_EN,4,2 ; @RADEON_FP_RMX_HVSYNC_CONTROL_EN
	.comm	_RADEON_FP_DFP_SYNC_SEL,4,2     ; @RADEON_FP_DFP_SYNC_SEL
	.comm	_RADEON_FP_CRT_SYNC_SEL,4,2     ; @RADEON_FP_CRT_SYNC_SEL
	.comm	_RADEON_FP_CRTC_LOCK_8DOT,4,2   ; @RADEON_FP_CRTC_LOCK_8DOT
	.comm	_RADEON_FP_USE_SHADOW_EN,4,2    ; @RADEON_FP_USE_SHADOW_EN
	.comm	_RADEON_FP_CRTC_USE_SHADOW_VEND,4,2 ; @RADEON_FP_CRTC_USE_SHADOW_VEND
	.comm	_RADEON_FP_CRT_SYNC_ALT,4,2     ; @RADEON_FP_CRT_SYNC_ALT
	.comm	_RADEON_FP_PANEL_FORMAT,4,2     ; @RADEON_FP_PANEL_FORMAT
	.comm	_R200_FP_SOURCE_SEL_MASK,4,2    ; @R200_FP_SOURCE_SEL_MASK
	.comm	_RMX_OFF,8,3                    ; @RMX_OFF
	.comm	_R200_FP_SOURCE_SEL_RMX,4,2     ; @R200_FP_SOURCE_SEL_RMX
	.comm	_R200_FP_SOURCE_SEL_CRTC1,4,2   ; @R200_FP_SOURCE_SEL_CRTC1
	.comm	_RADEON_FP_SEL_CRTC2,4,2        ; @RADEON_FP_SEL_CRTC2
	.comm	_R200_FP_SOURCE_SEL_CRTC2,4,2   ; @R200_FP_SOURCE_SEL_CRTC2
	.no_dead_strip	_radeon_legacy_tmds_int_mode_set
.subsections_via_symbols
