	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function r600_cp_init_ring_buffer
_r600_cp_init_ring_buffer:              ## @r600_cp_init_ring_buffer
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r12
	movq	_RADEON_FAMILY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%rsi), %eax
	movq	%rdx, -48(%rbp)                 ## 8-byte Spill
	movq	%rdi, %r15
	movq	_CHIP_RV770@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jge	LBB0_1
## %bb.2:
	movq	%r15, %rdi
	movq	%r12, %rsi
	callq	_r600_gfx_init
	jmp	LBB0_3
LBB0_1:
	movq	%r15, %rdi
	movq	%r12, %rsi
	callq	_r700_gfx_init
LBB0_3:
	movq	_R600_GRBM_SOFT_RESET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_R600_SOFT_RESET_CP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_RADEON_WRITE
	movl	(%rbx), %edi
	callq	_RADEON_READ
	movl	$15, %edi
	callq	_mdelay
	movl	(%rbx), %edi
	xorl	%esi, %esi
	callq	_RADEON_WRITE
	movq	_R600_CP_RB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	%rax, %rbx
	movq	_RADEON_RB_NO_UPDATE@GOTPCREL(%rip), %rax
	movl	24(%r12), %esi
	shll	$8, %esi
	orl	(%rax), %esi
	orl	28(%r12), %esi
	callq	_RADEON_WRITE
	movq	_R600_CP_SEM_WAIT_TIMER@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_RADEON_WRITE
	movq	_R600_CP_RB_WPTR_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_RADEON_WRITE
	movl	(%rbx), %edi
	movq	_R600_RB_NO_UPDATE@GOTPCREL(%rip), %rax
	movq	_R600_RB_RPTR_WR_ENA@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movl	24(%r12), %esi
	shll	$8, %esi
	orl	%ecx, %esi
	orl	28(%r12), %esi
	callq	_RADEON_WRITE
	movq	_R600_CP_RB_RPTR_WR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_RADEON_WRITE
	movq	_R600_CP_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_RADEON_WRITE
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	_SET_RING_HEAD
	movq	$0, 32(%r12)
	movq	40(%r12), %rax
	movl	(%rax), %ebx
	movq	(%r15), %rax
	subl	(%rax), %ebx
	addl	4(%r12), %ebx
	movq	_R600_CP_RB_RPTR_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	andl	$-4, %esi
	callq	_RADEON_WRITE
	movq	_R600_CP_RB_RPTR_ADDR_HI@GOTPCREL(%rip), %r14
	movl	(%r14), %r13d
	movl	%ebx, %edi
	callq	_upper_32_bits
	movl	%r13d, %edi
	movl	%eax, %esi
	callq	_RADEON_WRITE
	movq	_R600_CP_RB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	24(%r12), %esi
	shll	$8, %esi
	orl	28(%r12), %esi
	callq	_RADEON_WRITE
	movq	16(%r12), %rax
	movl	(%rax), %esi
	movq	(%r15), %rax
	subl	(%rax), %esi
	addl	4(%r12), %esi
	movq	_R600_CP_RB_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	sarl	$8, %esi
	callq	_RADEON_WRITE
	movq	_R600_CP_ME_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$255, %esi
	callq	_RADEON_WRITE
	movq	_R600_CP_DEBUG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$402653184, %esi                ## imm = 0x18000000
	callq	_RADEON_WRITE
	movq	_R600_CP_RB_RPTR_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RADEON_READ
	movl	(%r14), %edi
	callq	_RADEON_READ
	movq	_R600_SCRATCH_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RADEON_WRITE
	movq	_R600_SCRATCH_UMSK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$7, %esi
	callq	_RADEON_WRITE
	movq	%r12, %rdi
	callq	_radeon_enable_bm
	xorl	%edi, %edi
	callq	_R600_SCRATCHOFF
	movq	%r12, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_radeon_write_ring_rptr
	movq	_R600_LAST_FRAME_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_RADEON_WRITE
	movl	$1, %edi
	callq	_R600_SCRATCHOFF
	movq	%r12, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_radeon_write_ring_rptr
	movq	_R600_LAST_DISPATCH_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_RADEON_WRITE
	movl	$2, %edi
	callq	_R600_SCRATCHOFF
	movq	%r12, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_radeon_write_ring_rptr
	movq	_R600_LAST_CLEAR_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_RADEON_WRITE
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rax
	movq	(%rax), %rax
	movq	(%rax), %rax
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	xorps	%xmm0, %xmm0
	movups	%xmm0, (%rax)
	movq	$0, 16(%rax)
LBB0_5:
	movq	%r12, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_r600_do_wait_for_idle          ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_FAMILY_MASK,4,2         ## @RADEON_FAMILY_MASK
	.comm	_CHIP_RV770,4,2                 ## @CHIP_RV770
	.comm	_R600_GRBM_SOFT_RESET,4,2       ## @R600_GRBM_SOFT_RESET
	.comm	_R600_SOFT_RESET_CP,4,2         ## @R600_SOFT_RESET_CP
	.comm	_R600_CP_RB_CNTL,4,2            ## @R600_CP_RB_CNTL
	.comm	_RADEON_RB_NO_UPDATE,4,2        ## @RADEON_RB_NO_UPDATE
	.comm	_R600_CP_SEM_WAIT_TIMER,4,2     ## @R600_CP_SEM_WAIT_TIMER
	.comm	_R600_CP_RB_WPTR_DELAY,4,2      ## @R600_CP_RB_WPTR_DELAY
	.comm	_R600_RB_NO_UPDATE,4,2          ## @R600_RB_NO_UPDATE
	.comm	_R600_RB_RPTR_WR_ENA,4,2        ## @R600_RB_RPTR_WR_ENA
	.comm	_R600_CP_RB_RPTR_WR,4,2         ## @R600_CP_RB_RPTR_WR
	.comm	_R600_CP_RB_WPTR,4,2            ## @R600_CP_RB_WPTR
	.comm	_R600_CP_RB_RPTR_ADDR,4,2       ## @R600_CP_RB_RPTR_ADDR
	.comm	_R600_CP_RB_RPTR_ADDR_HI,4,2    ## @R600_CP_RB_RPTR_ADDR_HI
	.comm	_R600_CP_RB_BASE,4,2            ## @R600_CP_RB_BASE
	.comm	_R600_CP_ME_CNTL,4,2            ## @R600_CP_ME_CNTL
	.comm	_R600_CP_DEBUG,4,2              ## @R600_CP_DEBUG
	.comm	_R600_SCRATCH_REG_OFFSET,8,3    ## @R600_SCRATCH_REG_OFFSET
	.comm	_R600_SCRATCH_ADDR,4,2          ## @R600_SCRATCH_ADDR
	.comm	_R600_SCRATCH_UMSK,4,2          ## @R600_SCRATCH_UMSK
	.comm	_R600_LAST_FRAME_REG,4,2        ## @R600_LAST_FRAME_REG
	.comm	_R600_LAST_DISPATCH_REG,4,2     ## @R600_LAST_DISPATCH_REG
	.comm	_R600_LAST_CLEAR_REG,4,2        ## @R600_LAST_CLEAR_REG
	.comm	_R600_BUF_SWAP_32BIT,4,2        ## @R600_BUF_SWAP_32BIT
	.comm	_RADEON_BUF_SWAP_32BIT,4,2      ## @RADEON_BUF_SWAP_32BIT
	.comm	_RADEON_IS_AGP,4,2              ## @RADEON_IS_AGP
	.no_dead_strip	_r600_cp_init_ring_buffer
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function r600_cp_init_ring_buffer
_r600_cp_init_ring_buffer:              ; @r600_cp_init_ring_buffer
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x2
	mov	x19, x1
	mov	x21, x0
	ldr	w8, [x1]
Lloh0:
	adrp	x9, _RADEON_FAMILY_MASK@GOTPAGE
Lloh1:
	ldr	x9, [x9, _RADEON_FAMILY_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	and	w8, w9, w8
Lloh3:
	adrp	x9, _CHIP_RV770@GOTPAGE
Lloh4:
	ldr	x9, [x9, _CHIP_RV770@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ge	LBB0_2
; %bb.1:
	bl	_r600_gfx_init
	b	LBB0_3
LBB0_2:
	bl	_r700_gfx_init
LBB0_3:
Lloh6:
	adrp	x22, _R600_GRBM_SOFT_RESET@GOTPAGE
Lloh7:
	ldr	x22, [x22, _R600_GRBM_SOFT_RESET@GOTPAGEOFF]
	ldr	w0, [x22]
Lloh8:
	adrp	x8, _R600_SOFT_RESET_CP@GOTPAGE
Lloh9:
	ldr	x8, [x8, _R600_SOFT_RESET_CP@GOTPAGEOFF]
Lloh10:
	ldr	w1, [x8]
	bl	_RADEON_WRITE
	ldr	w0, [x22]
	bl	_RADEON_READ
	mov	w0, #15
	bl	_mdelay
	ldr	w0, [x22]
	mov	w1, #0
	bl	_RADEON_WRITE
Lloh11:
	adrp	x24, _R600_CP_RB_CNTL@GOTPAGE
Lloh12:
	ldr	x24, [x24, _R600_CP_RB_CNTL@GOTPAGEOFF]
Lloh13:
	adrp	x8, _RADEON_RB_NO_UPDATE@GOTPAGE
Lloh14:
	ldr	x8, [x8, _RADEON_RB_NO_UPDATE@GOTPAGEOFF]
	ldr	w0, [x24]
Lloh15:
	ldr	w8, [x8]
	ldp	w9, w10, [x19, #24]
	orr	w8, w8, w9, lsl #8
	orr	w1, w8, w10
	bl	_RADEON_WRITE
Lloh16:
	adrp	x8, _R600_CP_SEM_WAIT_TIMER@GOTPAGE
Lloh17:
	ldr	x8, [x8, _R600_CP_SEM_WAIT_TIMER@GOTPAGEOFF]
Lloh18:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_RADEON_WRITE
Lloh19:
	adrp	x8, _R600_CP_RB_WPTR_DELAY@GOTPAGE
Lloh20:
	ldr	x8, [x8, _R600_CP_RB_WPTR_DELAY@GOTPAGEOFF]
Lloh21:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_RADEON_WRITE
	ldr	w0, [x24]
Lloh22:
	adrp	x8, _R600_RB_NO_UPDATE@GOTPAGE
Lloh23:
	ldr	x8, [x8, _R600_RB_NO_UPDATE@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
Lloh25:
	adrp	x9, _R600_RB_RPTR_WR_ENA@GOTPAGE
Lloh26:
	ldr	x9, [x9, _R600_RB_RPTR_WR_ENA@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
	orr	w8, w9, w8
	ldp	w9, w10, [x19, #24]
	orr	w8, w8, w9, lsl #8
	orr	w1, w8, w10
	bl	_RADEON_WRITE
Lloh28:
	adrp	x8, _R600_CP_RB_RPTR_WR@GOTPAGE
Lloh29:
	ldr	x8, [x8, _R600_CP_RB_RPTR_WR@GOTPAGEOFF]
Lloh30:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_RADEON_WRITE
Lloh31:
	adrp	x8, _R600_CP_RB_WPTR@GOTPAGE
Lloh32:
	ldr	x8, [x8, _R600_CP_RB_WPTR@GOTPAGEOFF]
Lloh33:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_RADEON_WRITE
	mov	x0, x19
	mov	w1, #0
	bl	_SET_RING_HEAD
	str	xzr, [x19, #32]
	ldr	x8, [x19, #40]
	ldr	w8, [x8]
	ldr	x9, [x21]
	ldr	w9, [x9]
	ldr	w10, [x19, #4]
	sub	w8, w8, w9
	add	w22, w10, w8
Lloh34:
	adrp	x25, _R600_CP_RB_RPTR_ADDR@GOTPAGE
Lloh35:
	ldr	x25, [x25, _R600_CP_RB_RPTR_ADDR@GOTPAGEOFF]
	ldr	w0, [x25]
	and	w1, w22, #0xfffffffc
	bl	_RADEON_WRITE
Lloh36:
	adrp	x26, _R600_CP_RB_RPTR_ADDR_HI@GOTPAGE
Lloh37:
	ldr	x26, [x26, _R600_CP_RB_RPTR_ADDR_HI@GOTPAGEOFF]
	ldr	w23, [x26]
	mov	x0, x22
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x23
	bl	_RADEON_WRITE
	ldr	w0, [x24]
	ldp	w8, w9, [x19, #24]
	orr	w1, w9, w8, lsl #8
	bl	_RADEON_WRITE
	ldr	x8, [x19, #16]
	ldr	w8, [x8]
	ldr	x9, [x21]
	ldr	w9, [x9]
	ldr	w10, [x19, #4]
	sub	w8, w8, w9
	add	w8, w10, w8
Lloh38:
	adrp	x9, _R600_CP_RB_BASE@GOTPAGE
Lloh39:
	ldr	x9, [x9, _R600_CP_RB_BASE@GOTPAGEOFF]
Lloh40:
	ldr	w0, [x9]
	asr	w1, w8, #8
	bl	_RADEON_WRITE
Lloh41:
	adrp	x8, _R600_CP_ME_CNTL@GOTPAGE
Lloh42:
	ldr	x8, [x8, _R600_CP_ME_CNTL@GOTPAGEOFF]
Lloh43:
	ldr	w0, [x8]
	mov	w1, #255
	bl	_RADEON_WRITE
Lloh44:
	adrp	x8, _R600_CP_DEBUG@GOTPAGE
Lloh45:
	ldr	x8, [x8, _R600_CP_DEBUG@GOTPAGEOFF]
Lloh46:
	ldr	w0, [x8]
	mov	w1, #402653184
	bl	_RADEON_WRITE
	ldr	w0, [x25]
	bl	_RADEON_READ
	ldr	w0, [x26]
	bl	_RADEON_READ
Lloh47:
	adrp	x8, _R600_SCRATCH_ADDR@GOTPAGE
Lloh48:
	ldr	x8, [x8, _R600_SCRATCH_ADDR@GOTPAGEOFF]
Lloh49:
	ldr	w0, [x8]
	bl	_RADEON_WRITE
Lloh50:
	adrp	x8, _R600_SCRATCH_UMSK@GOTPAGE
Lloh51:
	ldr	x8, [x8, _R600_SCRATCH_UMSK@GOTPAGEOFF]
Lloh52:
	ldr	w0, [x8]
	mov	w1, #7
	bl	_RADEON_WRITE
	mov	x0, x19
	bl	_radeon_enable_bm
	mov	w0, #0
	bl	_R600_SCRATCHOFF
	mov	x1, x0
	mov	x0, x19
	mov	w2, #0
	bl	_radeon_write_ring_rptr
Lloh53:
	adrp	x8, _R600_LAST_FRAME_REG@GOTPAGE
Lloh54:
	ldr	x8, [x8, _R600_LAST_FRAME_REG@GOTPAGEOFF]
Lloh55:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_RADEON_WRITE
	mov	w0, #1
	bl	_R600_SCRATCHOFF
	mov	x1, x0
	mov	x0, x19
	mov	w2, #0
	bl	_radeon_write_ring_rptr
Lloh56:
	adrp	x8, _R600_LAST_DISPATCH_REG@GOTPAGE
Lloh57:
	ldr	x8, [x8, _R600_LAST_DISPATCH_REG@GOTPAGEOFF]
Lloh58:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_RADEON_WRITE
	mov	w0, #2
	bl	_R600_SCRATCHOFF
	mov	x1, x0
	mov	x0, x19
	mov	w2, #0
	bl	_radeon_write_ring_rptr
Lloh59:
	adrp	x8, _R600_LAST_CLEAR_REG@GOTPAGE
Lloh60:
	ldr	x8, [x8, _R600_LAST_CLEAR_REG@GOTPAGEOFF]
Lloh61:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_RADEON_WRITE
	ldr	x8, [x20]
	ldr	x8, [x8]
	ldr	x8, [x8]
	cbz	x8, LBB0_5
; %bb.4:
	stp	xzr, xzr, [x8]
	str	xzr, [x8, #16]
LBB0_5:
	mov	x0, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_r600_do_wait_for_idle
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_FAMILY_MASK,4,2         ; @RADEON_FAMILY_MASK
	.comm	_CHIP_RV770,4,2                 ; @CHIP_RV770
	.comm	_R600_GRBM_SOFT_RESET,4,2       ; @R600_GRBM_SOFT_RESET
	.comm	_R600_SOFT_RESET_CP,4,2         ; @R600_SOFT_RESET_CP
	.comm	_R600_CP_RB_CNTL,4,2            ; @R600_CP_RB_CNTL
	.comm	_RADEON_RB_NO_UPDATE,4,2        ; @RADEON_RB_NO_UPDATE
	.comm	_R600_CP_SEM_WAIT_TIMER,4,2     ; @R600_CP_SEM_WAIT_TIMER
	.comm	_R600_CP_RB_WPTR_DELAY,4,2      ; @R600_CP_RB_WPTR_DELAY
	.comm	_R600_RB_NO_UPDATE,4,2          ; @R600_RB_NO_UPDATE
	.comm	_R600_RB_RPTR_WR_ENA,4,2        ; @R600_RB_RPTR_WR_ENA
	.comm	_R600_CP_RB_RPTR_WR,4,2         ; @R600_CP_RB_RPTR_WR
	.comm	_R600_CP_RB_WPTR,4,2            ; @R600_CP_RB_WPTR
	.comm	_R600_CP_RB_RPTR_ADDR,4,2       ; @R600_CP_RB_RPTR_ADDR
	.comm	_R600_CP_RB_RPTR_ADDR_HI,4,2    ; @R600_CP_RB_RPTR_ADDR_HI
	.comm	_R600_CP_RB_BASE,4,2            ; @R600_CP_RB_BASE
	.comm	_R600_CP_ME_CNTL,4,2            ; @R600_CP_ME_CNTL
	.comm	_R600_CP_DEBUG,4,2              ; @R600_CP_DEBUG
	.comm	_R600_SCRATCH_REG_OFFSET,8,3    ; @R600_SCRATCH_REG_OFFSET
	.comm	_R600_SCRATCH_ADDR,4,2          ; @R600_SCRATCH_ADDR
	.comm	_R600_SCRATCH_UMSK,4,2          ; @R600_SCRATCH_UMSK
	.comm	_R600_LAST_FRAME_REG,4,2        ; @R600_LAST_FRAME_REG
	.comm	_R600_LAST_DISPATCH_REG,4,2     ; @R600_LAST_DISPATCH_REG
	.comm	_R600_LAST_CLEAR_REG,4,2        ; @R600_LAST_CLEAR_REG
	.comm	_R600_BUF_SWAP_32BIT,4,2        ; @R600_BUF_SWAP_32BIT
	.comm	_RADEON_BUF_SWAP_32BIT,4,2      ; @RADEON_BUF_SWAP_32BIT
	.comm	_RADEON_IS_AGP,4,2              ; @RADEON_IS_AGP
	.no_dead_strip	_r600_cp_init_ring_buffer
.subsections_via_symbols
