	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function cayman_gpu_soft_reset
_cayman_gpu_soft_reset:                 ## @cayman_gpu_soft_reset
	.cfi_startproc
## %bb.0:
	testl	%esi, %esi
	je	LBB0_21
## %bb.1:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %r15
	movl	4(%rdi), %edi
	leaq	L_.str(%rip), %rsi
	movl	%r14d, %edx
	callq	_dev_info
	movq	%r15, %rdi
	callq	_evergreen_print_gpu_status_regs
	movl	4(%r15), %ebx
	movl	$5368, %edi                     ## imm = 0x14F8
	callq	_RREG32
	leaq	L_.str.1(%rip), %rsi
	movl	%ebx, %edi
	movl	%eax, %edx
	callq	_dev_info
	movl	4(%r15), %ebx
	movl	$5336, %edi                     ## imm = 0x14D8
	callq	_RREG32
	leaq	L_.str.2(%rip), %rsi
	movl	%ebx, %edi
	movl	%eax, %edx
	callq	_dev_info
	movl	4(%r15), %ebx
	movl	$5372, %edi                     ## imm = 0x14FC
	callq	_RREG32
	leaq	L_.str.3(%rip), %rsi
	movl	%ebx, %edi
	movl	%eax, %edx
	callq	_dev_info
	movl	4(%r15), %ebx
	movl	$5340, %edi                     ## imm = 0x14DC
	callq	_RREG32
	leaq	L_.str.4(%rip), %rsi
	movl	%ebx, %edi
	movl	%eax, %edx
	callq	_dev_info
	movq	_CP_ME_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_CP_ME_HALT@GOTPCREL(%rip), %rax
	movq	_CP_PFP_HALT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	callq	_WREG32
	movq	_RADEON_RESET_DMA@GOTPCREL(%rip), %r12
	testl	%r14d, (%r12)
	je	LBB0_3
## %bb.2:
	movq	_DMA_RB_CNTL@GOTPCREL(%rip), %r13
	movq	_DMA0_REGISTER_OFFSET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	addl	(%r13), %edi
	callq	_RREG32
	movq	_DMA_RB_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	addl	(%r13), %edi
	callq	_WREG32
LBB0_3:
	movq	_RADEON_RESET_DMA1@GOTPCREL(%rip), %r13
	testl	%r14d, (%r13)
	je	LBB0_5
## %bb.4:
	movq	_DMA_RB_CNTL@GOTPCREL(%rip), %rbx
	movq	%r12, %r13
	movq	_DMA1_REGISTER_OFFSET@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	addl	(%rbx), %edi
	callq	_RREG32
	movq	_DMA_RB_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r12), %edi
	movq	%r13, %r12
	movq	_RADEON_RESET_DMA1@GOTPCREL(%rip), %r13
	addl	(%rbx), %edi
	callq	_WREG32
LBB0_5:
	movl	$50, %edi
	callq	_udelay
	leaq	-48(%rbp), %rsi
	movq	%r15, %rdi
	callq	_evergreen_mc_stop
	movq	%r15, %rdi
	callq	_evergreen_mc_wait_for_idle
	testq	%rax, %rax
	je	LBB0_7
## %bb.6:
	movl	4(%r15), %edi
	leaq	L_.str.5(%rip), %rsi
	callq	_dev_warn
LBB0_7:
	movq	_RADEON_RESET_GFX@GOTPCREL(%rip), %rax
	movq	_RADEON_RESET_COMPUTE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	testl	%r14d, %ecx
	je	LBB0_8
## %bb.9:
	movq	_SOFT_RESET_CB@GOTPCREL(%rip), %rax
	movq	_SOFT_RESET_DB@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	_SOFT_RESET_GDS@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SOFT_RESET_PA@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SOFT_RESET_SC@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SOFT_RESET_SPI@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SOFT_RESET_SH@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SOFT_RESET_SX@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SOFT_RESET_TC@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SOFT_RESET_TA@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SOFT_RESET_VGT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SOFT_RESET_IA@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	jmp	LBB0_10
LBB0_8:
	xorl	%ebx, %ebx
LBB0_10:
	movq	_RADEON_RESET_CP@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_11
## %bb.12:
	movq	_SOFT_RESET_CP@GOTPCREL(%rip), %rax
	movq	_SOFT_RESET_VGT@GOTPCREL(%rip), %rcx
	orl	(%rax), %ebx
	orl	(%rcx), %ebx
	movq	_SOFT_RESET_GRBM@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %eax
	jmp	LBB0_13
LBB0_11:
	movq	_SOFT_RESET_GRBM@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%eax, %eax
LBB0_13:
	movq	_RADEON_RESET_SEM@GOTPCREL(%rip), %rdx
	movd	(%rdx), %xmm0                   ## xmm0 = mem[0],zero,zero,zero
	movq	_RADEON_RESET_IH@GOTPCREL(%rip), %rdx
	pinsrd	$1, (%rdx), %xmm0
	movq	_RADEON_RESET_GRBM@GOTPCREL(%rip), %rdx
	pinsrd	$2, (%rdx), %xmm0
	movq	_RADEON_RESET_VMC@GOTPCREL(%rip), %rdx
	pinsrd	$3, (%rdx), %xmm0
	movd	(%r12), %xmm1                   ## xmm1 = mem[0],zero,zero,zero
	pinsrd	$1, (%r13), %xmm1
	movq	_RADEON_RESET_DISPLAY@GOTPCREL(%rip), %rdx
	pinsrd	$2, (%rdx), %xmm1
	movq	_RADEON_RESET_RLC@GOTPCREL(%rip), %rdx
	pinsrd	$3, (%rdx), %xmm1
	movq	_SOFT_RESET_DMA@GOTPCREL(%rip), %rdx
	movd	(%rdx), %xmm2                   ## xmm2 = mem[0],zero,zero,zero
	movq	_SOFT_RESET_DMA1@GOTPCREL(%rip), %rdx
	pinsrd	$1, (%rdx), %xmm2
	movq	_SOFT_RESET_DC@GOTPCREL(%rip), %rdx
	pinsrd	$2, (%rdx), %xmm2
	movq	_SOFT_RESET_RLC@GOTPCREL(%rip), %rdx
	pinsrd	$3, (%rdx), %xmm2
	movq	_SOFT_RESET_SEM@GOTPCREL(%rip), %rdx
	movd	(%rdx), %xmm3                   ## xmm3 = mem[0],zero,zero,zero
	movq	_SOFT_RESET_IH@GOTPCREL(%rip), %rdx
	pinsrd	$1, (%rdx), %xmm3
	pinsrd	$2, %ecx, %xmm3
	movq	_SOFT_RESET_VMC@GOTPCREL(%rip), %rcx
	movd	%r14d, %xmm4
	pshufd	$0, %xmm4, %xmm4                ## xmm4 = xmm4[0,0,0,0]
	pand	%xmm4, %xmm1
	pand	%xmm4, %xmm0
	pinsrd	$3, (%rcx), %xmm3
	pxor	%xmm4, %xmm4
	pcmpeqd	%xmm4, %xmm0
	pandn	%xmm3, %xmm0
	pcmpeqd	%xmm4, %xmm1
	pandn	%xmm2, %xmm1
	por	%xmm0, %xmm1
	pshufd	$238, %xmm1, %xmm0              ## xmm0 = xmm1[2,3,2,3]
	por	%xmm1, %xmm0
	pshufd	$85, %xmm0, %xmm1               ## xmm1 = xmm0[1,1,1,1]
	por	%xmm0, %xmm1
	movd	%xmm1, %r12d
	orl	%eax, %r12d
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r15)
	jne	LBB0_16
## %bb.14:
	movq	_RADEON_RESET_MC@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_16
## %bb.15:
	movq	_SOFT_RESET_MC@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
LBB0_16:
	testl	%ebx, %ebx
	je	LBB0_18
## %bb.17:
	movq	_GRBM_SOFT_RESET@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_RREG32
	movl	%eax, %r14d
	orl	%ebx, %r14d
	movl	4(%r15), %edi
	leaq	L_.str.6(%rip), %rsi
	movl	%r14d, %edx
	callq	_dev_info
	movl	(%r13), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movl	(%r13), %edi
	callq	_RREG32
	movl	%eax, %r14d
	movl	$50, %edi
	callq	_udelay
	notl	%ebx
	andl	%r14d, %ebx
	movl	(%r13), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r13), %edi
	callq	_RREG32
LBB0_18:
	testl	%r12d, %r12d
	je	LBB0_20
## %bb.19:
	movq	_SRBM_SOFT_RESET@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32
	movl	%eax, %ebx
	orl	%r12d, %ebx
	movl	4(%r15), %edi
	leaq	L_.str.7(%rip), %rsi
	movl	%ebx, %edx
	callq	_dev_info
	movl	(%r14), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r14), %edi
	callq	_RREG32
	movl	%eax, %ebx
	movl	$50, %edi
	callq	_udelay
	notl	%r12d
	andl	%ebx, %r12d
	movl	(%r14), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movl	(%r14), %edi
	callq	_RREG32
LBB0_20:
	movl	$50, %edi
	callq	_udelay
	leaq	-48(%rbp), %rsi
	movq	%r15, %rdi
	callq	_evergreen_mc_resume
	movl	$50, %edi
	callq	_udelay
	movq	%r15, %rdi
	callq	_evergreen_print_gpu_status_regs
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
LBB0_21:
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"GPU softreset: 0x%08X\n"

L_.str.1:                               ## @.str.1
	.asciz	"  VM_CONTEXT0_PROTECTION_FAULT_ADDR   0x%08X\n"

L_.str.2:                               ## @.str.2
	.asciz	"  VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n"

L_.str.3:                               ## @.str.3
	.asciz	"  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n"

L_.str.4:                               ## @.str.4
	.asciz	"  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n"

	.comm	_CP_ME_CNTL,4,2                 ## @CP_ME_CNTL
	.comm	_CP_ME_HALT,4,2                 ## @CP_ME_HALT
	.comm	_CP_PFP_HALT,4,2                ## @CP_PFP_HALT
	.comm	_RADEON_RESET_DMA,4,2           ## @RADEON_RESET_DMA
	.comm	_DMA_RB_CNTL,4,2                ## @DMA_RB_CNTL
	.comm	_DMA0_REGISTER_OFFSET,4,2       ## @DMA0_REGISTER_OFFSET
	.comm	_DMA_RB_ENABLE,4,2              ## @DMA_RB_ENABLE
	.comm	_RADEON_RESET_DMA1,4,2          ## @RADEON_RESET_DMA1
	.comm	_DMA1_REGISTER_OFFSET,4,2       ## @DMA1_REGISTER_OFFSET
L_.str.5:                               ## @.str.5
	.asciz	"Wait for MC idle timedout !\n"

	.comm	_RADEON_RESET_GFX,4,2           ## @RADEON_RESET_GFX
	.comm	_RADEON_RESET_COMPUTE,4,2       ## @RADEON_RESET_COMPUTE
	.comm	_SOFT_RESET_CB,4,2              ## @SOFT_RESET_CB
	.comm	_SOFT_RESET_DB,4,2              ## @SOFT_RESET_DB
	.comm	_SOFT_RESET_GDS,4,2             ## @SOFT_RESET_GDS
	.comm	_SOFT_RESET_PA,4,2              ## @SOFT_RESET_PA
	.comm	_SOFT_RESET_SC,4,2              ## @SOFT_RESET_SC
	.comm	_SOFT_RESET_SPI,4,2             ## @SOFT_RESET_SPI
	.comm	_SOFT_RESET_SH,4,2              ## @SOFT_RESET_SH
	.comm	_SOFT_RESET_SX,4,2              ## @SOFT_RESET_SX
	.comm	_SOFT_RESET_TC,4,2              ## @SOFT_RESET_TC
	.comm	_SOFT_RESET_TA,4,2              ## @SOFT_RESET_TA
	.comm	_SOFT_RESET_VGT,4,2             ## @SOFT_RESET_VGT
	.comm	_SOFT_RESET_IA,4,2              ## @SOFT_RESET_IA
	.comm	_RADEON_RESET_CP,4,2            ## @RADEON_RESET_CP
	.comm	_SOFT_RESET_CP,4,2              ## @SOFT_RESET_CP
	.comm	_SOFT_RESET_GRBM,4,2            ## @SOFT_RESET_GRBM
	.comm	_SOFT_RESET_DMA,4,2             ## @SOFT_RESET_DMA
	.comm	_SOFT_RESET_DMA1,4,2            ## @SOFT_RESET_DMA1
	.comm	_RADEON_RESET_DISPLAY,4,2       ## @RADEON_RESET_DISPLAY
	.comm	_SOFT_RESET_DC,4,2              ## @SOFT_RESET_DC
	.comm	_RADEON_RESET_RLC,4,2           ## @RADEON_RESET_RLC
	.comm	_SOFT_RESET_RLC,4,2             ## @SOFT_RESET_RLC
	.comm	_RADEON_RESET_SEM,4,2           ## @RADEON_RESET_SEM
	.comm	_SOFT_RESET_SEM,4,2             ## @SOFT_RESET_SEM
	.comm	_RADEON_RESET_IH,4,2            ## @RADEON_RESET_IH
	.comm	_SOFT_RESET_IH,4,2              ## @SOFT_RESET_IH
	.comm	_RADEON_RESET_GRBM,4,2          ## @RADEON_RESET_GRBM
	.comm	_RADEON_RESET_VMC,4,2           ## @RADEON_RESET_VMC
	.comm	_SOFT_RESET_VMC,4,2             ## @SOFT_RESET_VMC
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
	.comm	_RADEON_RESET_MC,4,2            ## @RADEON_RESET_MC
	.comm	_SOFT_RESET_MC,4,2              ## @SOFT_RESET_MC
	.comm	_GRBM_SOFT_RESET,4,2            ## @GRBM_SOFT_RESET
L_.str.6:                               ## @.str.6
	.asciz	"GRBM_SOFT_RESET=0x%08X\n"

	.comm	_SRBM_SOFT_RESET,4,2            ## @SRBM_SOFT_RESET
L_.str.7:                               ## @.str.7
	.asciz	"SRBM_SOFT_RESET=0x%08X\n"

	.no_dead_strip	_cayman_gpu_soft_reset
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cayman_gpu_soft_reset
_cayman_gpu_soft_reset:                 ; @cayman_gpu_soft_reset
	.cfi_startproc
; %bb.0:
	cbz	w1, LBB0_21
; %bb.1:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x1
	mov	x19, x0
	ldr	w0, [x0, #4]
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	mov	x2, x20
	bl	_dev_info
	mov	x0, x19
	bl	_evergreen_print_gpu_status_regs
	ldr	w21, [x19, #4]
	mov	w0, #5368
	bl	_RREG32
	mov	x2, x0
Lloh2:
	adrp	x1, l_.str.1@PAGE
Lloh3:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x21
	bl	_dev_info
	ldr	w21, [x19, #4]
	mov	w0, #5336
	bl	_RREG32
	mov	x2, x0
Lloh4:
	adrp	x1, l_.str.2@PAGE
Lloh5:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x0, x21
	bl	_dev_info
	ldr	w21, [x19, #4]
	mov	w0, #5372
	bl	_RREG32
	mov	x2, x0
Lloh6:
	adrp	x1, l_.str.3@PAGE
Lloh7:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x0, x21
	bl	_dev_info
	ldr	w21, [x19, #4]
	mov	w0, #5340
	bl	_RREG32
	mov	x2, x0
Lloh8:
	adrp	x1, l_.str.4@PAGE
Lloh9:
	add	x1, x1, l_.str.4@PAGEOFF
	mov	x0, x21
	bl	_dev_info
Lloh10:
	adrp	x8, _CP_ME_CNTL@GOTPAGE
Lloh11:
	ldr	x8, [x8, _CP_ME_CNTL@GOTPAGEOFF]
Lloh12:
	adrp	x9, _CP_ME_HALT@GOTPAGE
Lloh13:
	ldr	x9, [x9, _CP_ME_HALT@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
Lloh15:
	ldr	w8, [x9]
Lloh16:
	adrp	x9, _CP_PFP_HALT@GOTPAGE
Lloh17:
	ldr	x9, [x9, _CP_PFP_HALT@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	orr	w1, w9, w8
	bl	_WREG32
Lloh19:
	adrp	x21, _RADEON_RESET_DMA@GOTPAGE
Lloh20:
	ldr	x21, [x21, _RADEON_RESET_DMA@GOTPAGEOFF]
	ldr	w8, [x21]
Lloh21:
	adrp	x22, _DMA_RB_CNTL@GOTPAGE
Lloh22:
	ldr	x22, [x22, _DMA_RB_CNTL@GOTPAGEOFF]
Lloh23:
	adrp	x24, _DMA_RB_ENABLE@GOTPAGE
Lloh24:
	ldr	x24, [x24, _DMA_RB_ENABLE@GOTPAGEOFF]
	tst	w8, w20
	b.eq	LBB0_3
; %bb.2:
	ldr	w8, [x22]
Lloh25:
	adrp	x23, _DMA0_REGISTER_OFFSET@GOTPAGE
Lloh26:
	ldr	x23, [x23, _DMA0_REGISTER_OFFSET@GOTPAGEOFF]
	ldr	w9, [x23]
	add	w0, w9, w8
	bl	_RREG32
	ldr	w8, [x24]
	bic	w1, w0, w8
	ldr	w8, [x22]
	ldr	w9, [x23]
	add	w0, w9, w8
	bl	_WREG32
LBB0_3:
Lloh27:
	adrp	x23, _RADEON_RESET_DMA1@GOTPAGE
Lloh28:
	ldr	x23, [x23, _RADEON_RESET_DMA1@GOTPAGEOFF]
	ldr	w8, [x23]
	tst	w8, w20
	b.eq	LBB0_5
; %bb.4:
	ldr	w8, [x22]
Lloh29:
	adrp	x25, _DMA1_REGISTER_OFFSET@GOTPAGE
Lloh30:
	ldr	x25, [x25, _DMA1_REGISTER_OFFSET@GOTPAGEOFF]
	ldr	w9, [x25]
	add	w0, w9, w8
	bl	_RREG32
	ldr	w8, [x24]
	bic	w1, w0, w8
	ldr	w8, [x22]
	ldr	w9, [x25]
	add	w0, w9, w8
	bl	_WREG32
LBB0_5:
	mov	w0, #50
	bl	_udelay
	add	x1, sp, #8
	mov	x0, x19
	bl	_evergreen_mc_stop
	mov	x0, x19
	bl	_evergreen_mc_wait_for_idle
	cbz	x0, LBB0_7
; %bb.6:
	ldr	w0, [x19, #4]
Lloh31:
	adrp	x1, l_.str.5@PAGE
Lloh32:
	add	x1, x1, l_.str.5@PAGEOFF
	bl	_dev_warn
LBB0_7:
Lloh33:
	adrp	x8, _RADEON_RESET_GFX@GOTPAGE
Lloh34:
	ldr	x8, [x8, _RADEON_RESET_GFX@GOTPAGEOFF]
Lloh35:
	adrp	x9, _RADEON_RESET_COMPUTE@GOTPAGE
Lloh36:
	ldr	x9, [x9, _RADEON_RESET_COMPUTE@GOTPAGEOFF]
Lloh37:
	ldr	w8, [x8]
Lloh38:
	ldr	w9, [x9]
	orr	w9, w9, w8
Lloh39:
	adrp	x8, _SOFT_RESET_VGT@GOTPAGE
Lloh40:
	ldr	x8, [x8, _SOFT_RESET_VGT@GOTPAGEOFF]
	tst	w9, w20
	b.eq	LBB0_9
; %bb.8:
Lloh41:
	adrp	x9, _SOFT_RESET_CB@GOTPAGE
Lloh42:
	ldr	x9, [x9, _SOFT_RESET_CB@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
Lloh44:
	adrp	x10, _SOFT_RESET_DB@GOTPAGE
Lloh45:
	ldr	x10, [x10, _SOFT_RESET_DB@GOTPAGEOFF]
Lloh46:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh47:
	adrp	x10, _SOFT_RESET_GDS@GOTPAGE
Lloh48:
	ldr	x10, [x10, _SOFT_RESET_GDS@GOTPAGEOFF]
Lloh49:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh50:
	adrp	x10, _SOFT_RESET_PA@GOTPAGE
Lloh51:
	ldr	x10, [x10, _SOFT_RESET_PA@GOTPAGEOFF]
Lloh52:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh53:
	adrp	x10, _SOFT_RESET_SC@GOTPAGE
Lloh54:
	ldr	x10, [x10, _SOFT_RESET_SC@GOTPAGEOFF]
Lloh55:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh56:
	adrp	x10, _SOFT_RESET_SPI@GOTPAGE
Lloh57:
	ldr	x10, [x10, _SOFT_RESET_SPI@GOTPAGEOFF]
Lloh58:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh59:
	adrp	x10, _SOFT_RESET_SH@GOTPAGE
Lloh60:
	ldr	x10, [x10, _SOFT_RESET_SH@GOTPAGEOFF]
Lloh61:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh62:
	adrp	x10, _SOFT_RESET_SX@GOTPAGE
Lloh63:
	ldr	x10, [x10, _SOFT_RESET_SX@GOTPAGEOFF]
Lloh64:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh65:
	adrp	x10, _SOFT_RESET_TC@GOTPAGE
Lloh66:
	ldr	x10, [x10, _SOFT_RESET_TC@GOTPAGEOFF]
Lloh67:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh68:
	adrp	x10, _SOFT_RESET_TA@GOTPAGE
Lloh69:
	ldr	x10, [x10, _SOFT_RESET_TA@GOTPAGEOFF]
Lloh70:
	ldr	w10, [x10]
	orr	w9, w9, w10
	ldr	w10, [x8]
	orr	w9, w9, w10
Lloh71:
	adrp	x10, _SOFT_RESET_IA@GOTPAGE
Lloh72:
	ldr	x10, [x10, _SOFT_RESET_IA@GOTPAGEOFF]
Lloh73:
	ldr	w10, [x10]
	orr	w22, w9, w10
	b	LBB0_10
LBB0_9:
	mov	w22, #0
LBB0_10:
Lloh74:
	adrp	x9, _RADEON_RESET_CP@GOTPAGE
Lloh75:
	ldr	x9, [x9, _RADEON_RESET_CP@GOTPAGEOFF]
Lloh76:
	ldr	w9, [x9]
	tst	w9, w20
	b.eq	LBB0_12
; %bb.11:
Lloh77:
	adrp	x9, _SOFT_RESET_CP@GOTPAGE
Lloh78:
	ldr	x9, [x9, _SOFT_RESET_CP@GOTPAGEOFF]
Lloh79:
	ldr	w9, [x9]
	ldr	w8, [x8]
	orr	w9, w9, w22
	orr	w22, w9, w8
Lloh80:
	adrp	x8, _SOFT_RESET_GRBM@GOTPAGE
Lloh81:
	ldr	x8, [x8, _SOFT_RESET_GRBM@GOTPAGEOFF]
Lloh82:
	ldr	w8, [x8]
	mov	x9, x8
	b	LBB0_13
LBB0_12:
	mov	w9, #0
Lloh83:
	adrp	x8, _SOFT_RESET_GRBM@GOTPAGE
Lloh84:
	ldr	x8, [x8, _SOFT_RESET_GRBM@GOTPAGEOFF]
Lloh85:
	ldr	w8, [x8]
LBB0_13:
	ldr	w10, [x21]
Lloh86:
	adrp	x11, _SOFT_RESET_DMA@GOTPAGE
Lloh87:
	ldr	x11, [x11, _SOFT_RESET_DMA@GOTPAGEOFF]
Lloh88:
	ldr	w11, [x11]
	tst	w10, w20
	csel	w10, wzr, w11, eq
	orr	w9, w10, w9
	ldr	w10, [x23]
Lloh89:
	adrp	x11, _SOFT_RESET_DMA1@GOTPAGE
Lloh90:
	ldr	x11, [x11, _SOFT_RESET_DMA1@GOTPAGEOFF]
Lloh91:
	ldr	w11, [x11]
	tst	w10, w20
	csel	w10, wzr, w11, eq
	orr	w9, w9, w10
Lloh92:
	adrp	x10, _RADEON_RESET_DISPLAY@GOTPAGE
Lloh93:
	ldr	x10, [x10, _RADEON_RESET_DISPLAY@GOTPAGEOFF]
Lloh94:
	ldr	w10, [x10]
Lloh95:
	adrp	x11, _SOFT_RESET_DC@GOTPAGE
Lloh96:
	ldr	x11, [x11, _SOFT_RESET_DC@GOTPAGEOFF]
Lloh97:
	ldr	w11, [x11]
	tst	w10, w20
	csel	w10, wzr, w11, eq
	orr	w9, w9, w10
Lloh98:
	adrp	x10, _RADEON_RESET_RLC@GOTPAGE
Lloh99:
	ldr	x10, [x10, _RADEON_RESET_RLC@GOTPAGEOFF]
Lloh100:
	ldr	w10, [x10]
Lloh101:
	adrp	x11, _SOFT_RESET_RLC@GOTPAGE
Lloh102:
	ldr	x11, [x11, _SOFT_RESET_RLC@GOTPAGEOFF]
Lloh103:
	ldr	w11, [x11]
	tst	w10, w20
	csel	w10, wzr, w11, eq
	orr	w9, w9, w10
Lloh104:
	adrp	x10, _RADEON_RESET_SEM@GOTPAGE
Lloh105:
	ldr	x10, [x10, _RADEON_RESET_SEM@GOTPAGEOFF]
Lloh106:
	ldr	w10, [x10]
Lloh107:
	adrp	x11, _SOFT_RESET_SEM@GOTPAGE
Lloh108:
	ldr	x11, [x11, _SOFT_RESET_SEM@GOTPAGEOFF]
Lloh109:
	ldr	w11, [x11]
	tst	w10, w20
	csel	w10, wzr, w11, eq
	orr	w9, w9, w10
Lloh110:
	adrp	x10, _RADEON_RESET_IH@GOTPAGE
Lloh111:
	ldr	x10, [x10, _RADEON_RESET_IH@GOTPAGEOFF]
Lloh112:
	ldr	w10, [x10]
Lloh113:
	adrp	x11, _SOFT_RESET_IH@GOTPAGE
Lloh114:
	ldr	x11, [x11, _SOFT_RESET_IH@GOTPAGEOFF]
Lloh115:
	ldr	w11, [x11]
	tst	w10, w20
	csel	w10, wzr, w11, eq
	orr	w9, w9, w10
Lloh116:
	adrp	x10, _RADEON_RESET_GRBM@GOTPAGE
Lloh117:
	ldr	x10, [x10, _RADEON_RESET_GRBM@GOTPAGEOFF]
Lloh118:
	ldr	w10, [x10]
	tst	w10, w20
	csel	w8, wzr, w8, eq
	orr	w8, w9, w8
Lloh119:
	adrp	x9, _RADEON_RESET_VMC@GOTPAGE
Lloh120:
	ldr	x9, [x9, _RADEON_RESET_VMC@GOTPAGEOFF]
Lloh121:
	ldr	w9, [x9]
Lloh122:
	adrp	x10, _SOFT_RESET_VMC@GOTPAGE
Lloh123:
	ldr	x10, [x10, _SOFT_RESET_VMC@GOTPAGEOFF]
Lloh124:
	ldr	w10, [x10]
	tst	w9, w20
	csel	w9, wzr, w10, eq
	orr	w21, w8, w9
	ldr	w8, [x19]
Lloh125:
	adrp	x9, _RADEON_IS_IGP@GOTPAGE
Lloh126:
	ldr	x9, [x9, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh127:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_16
; %bb.14:
Lloh128:
	adrp	x8, _RADEON_RESET_MC@GOTPAGE
Lloh129:
	ldr	x8, [x8, _RADEON_RESET_MC@GOTPAGEOFF]
Lloh130:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_16
; %bb.15:
Lloh131:
	adrp	x8, _SOFT_RESET_MC@GOTPAGE
Lloh132:
	ldr	x8, [x8, _SOFT_RESET_MC@GOTPAGEOFF]
Lloh133:
	ldr	w8, [x8]
	orr	w21, w8, w21
LBB0_16:
	cbz	w22, LBB0_18
; %bb.17:
Lloh134:
	adrp	x23, _GRBM_SOFT_RESET@GOTPAGE
Lloh135:
	ldr	x23, [x23, _GRBM_SOFT_RESET@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32
	orr	w20, w0, w22
	ldr	w0, [x19, #4]
Lloh136:
	adrp	x1, l_.str.6@PAGE
Lloh137:
	add	x1, x1, l_.str.6@PAGEOFF
	mov	x2, x20
	bl	_dev_info
	ldr	w0, [x23]
	mov	x1, x20
	bl	_WREG32
	ldr	w0, [x23]
	bl	_RREG32
	mov	x20, x0
	mov	w0, #50
	bl	_udelay
	bic	w1, w20, w22
	ldr	w0, [x23]
	bl	_WREG32
	ldr	w0, [x23]
	bl	_RREG32
LBB0_18:
	cbz	w21, LBB0_20
; %bb.19:
Lloh138:
	adrp	x22, _SRBM_SOFT_RESET@GOTPAGE
Lloh139:
	ldr	x22, [x22, _SRBM_SOFT_RESET@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_RREG32
	orr	w20, w0, w21
	ldr	w0, [x19, #4]
Lloh140:
	adrp	x1, l_.str.7@PAGE
Lloh141:
	add	x1, x1, l_.str.7@PAGEOFF
	mov	x2, x20
	bl	_dev_info
	ldr	w0, [x22]
	mov	x1, x20
	bl	_WREG32
	ldr	w0, [x22]
	bl	_RREG32
	mov	x20, x0
	mov	w0, #50
	bl	_udelay
	bic	w1, w20, w21
	ldr	w0, [x22]
	bl	_WREG32
	ldr	w0, [x22]
	bl	_RREG32
LBB0_20:
	mov	w0, #50
	bl	_udelay
	add	x1, sp, #8
	mov	x0, x19
	bl	_evergreen_mc_resume
	mov	w0, #50
	bl	_udelay
	mov	x0, x19
	bl	_evergreen_print_gpu_status_regs
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
LBB0_21:
	.cfi_def_cfa wsp, 0
	.cfi_same_value w30
	.cfi_same_value w29
	.cfi_same_value w19
	.cfi_same_value w20
	.cfi_same_value w21
	.cfi_same_value w22
	.cfi_same_value w23
	.cfi_same_value w24
	.cfi_same_value w25
	.cfi_same_value w26
	ret
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh14
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpAdd	Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh37
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh128, Lloh129, Lloh130
	.loh AdrpLdrGotLdr	Lloh131, Lloh132, Lloh133
	.loh AdrpAdd	Lloh136, Lloh137
	.loh AdrpLdrGot	Lloh134, Lloh135
	.loh AdrpAdd	Lloh140, Lloh141
	.loh AdrpLdrGot	Lloh138, Lloh139
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"GPU softreset: 0x%08X\n"

l_.str.1:                               ; @.str.1
	.asciz	"  VM_CONTEXT0_PROTECTION_FAULT_ADDR   0x%08X\n"

l_.str.2:                               ; @.str.2
	.asciz	"  VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n"

l_.str.3:                               ; @.str.3
	.asciz	"  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n"

l_.str.4:                               ; @.str.4
	.asciz	"  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n"

	.comm	_CP_ME_CNTL,4,2                 ; @CP_ME_CNTL
	.comm	_CP_ME_HALT,4,2                 ; @CP_ME_HALT
	.comm	_CP_PFP_HALT,4,2                ; @CP_PFP_HALT
	.comm	_RADEON_RESET_DMA,4,2           ; @RADEON_RESET_DMA
	.comm	_DMA_RB_CNTL,4,2                ; @DMA_RB_CNTL
	.comm	_DMA0_REGISTER_OFFSET,4,2       ; @DMA0_REGISTER_OFFSET
	.comm	_DMA_RB_ENABLE,4,2              ; @DMA_RB_ENABLE
	.comm	_RADEON_RESET_DMA1,4,2          ; @RADEON_RESET_DMA1
	.comm	_DMA1_REGISTER_OFFSET,4,2       ; @DMA1_REGISTER_OFFSET
l_.str.5:                               ; @.str.5
	.asciz	"Wait for MC idle timedout !\n"

	.comm	_RADEON_RESET_GFX,4,2           ; @RADEON_RESET_GFX
	.comm	_RADEON_RESET_COMPUTE,4,2       ; @RADEON_RESET_COMPUTE
	.comm	_SOFT_RESET_CB,4,2              ; @SOFT_RESET_CB
	.comm	_SOFT_RESET_DB,4,2              ; @SOFT_RESET_DB
	.comm	_SOFT_RESET_GDS,4,2             ; @SOFT_RESET_GDS
	.comm	_SOFT_RESET_PA,4,2              ; @SOFT_RESET_PA
	.comm	_SOFT_RESET_SC,4,2              ; @SOFT_RESET_SC
	.comm	_SOFT_RESET_SPI,4,2             ; @SOFT_RESET_SPI
	.comm	_SOFT_RESET_SH,4,2              ; @SOFT_RESET_SH
	.comm	_SOFT_RESET_SX,4,2              ; @SOFT_RESET_SX
	.comm	_SOFT_RESET_TC,4,2              ; @SOFT_RESET_TC
	.comm	_SOFT_RESET_TA,4,2              ; @SOFT_RESET_TA
	.comm	_SOFT_RESET_VGT,4,2             ; @SOFT_RESET_VGT
	.comm	_SOFT_RESET_IA,4,2              ; @SOFT_RESET_IA
	.comm	_RADEON_RESET_CP,4,2            ; @RADEON_RESET_CP
	.comm	_SOFT_RESET_CP,4,2              ; @SOFT_RESET_CP
	.comm	_SOFT_RESET_GRBM,4,2            ; @SOFT_RESET_GRBM
	.comm	_SOFT_RESET_DMA,4,2             ; @SOFT_RESET_DMA
	.comm	_SOFT_RESET_DMA1,4,2            ; @SOFT_RESET_DMA1
	.comm	_RADEON_RESET_DISPLAY,4,2       ; @RADEON_RESET_DISPLAY
	.comm	_SOFT_RESET_DC,4,2              ; @SOFT_RESET_DC
	.comm	_RADEON_RESET_RLC,4,2           ; @RADEON_RESET_RLC
	.comm	_SOFT_RESET_RLC,4,2             ; @SOFT_RESET_RLC
	.comm	_RADEON_RESET_SEM,4,2           ; @RADEON_RESET_SEM
	.comm	_SOFT_RESET_SEM,4,2             ; @SOFT_RESET_SEM
	.comm	_RADEON_RESET_IH,4,2            ; @RADEON_RESET_IH
	.comm	_SOFT_RESET_IH,4,2              ; @SOFT_RESET_IH
	.comm	_RADEON_RESET_GRBM,4,2          ; @RADEON_RESET_GRBM
	.comm	_RADEON_RESET_VMC,4,2           ; @RADEON_RESET_VMC
	.comm	_SOFT_RESET_VMC,4,2             ; @SOFT_RESET_VMC
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
	.comm	_RADEON_RESET_MC,4,2            ; @RADEON_RESET_MC
	.comm	_SOFT_RESET_MC,4,2              ; @SOFT_RESET_MC
	.comm	_GRBM_SOFT_RESET,4,2            ; @GRBM_SOFT_RESET
l_.str.6:                               ; @.str.6
	.asciz	"GRBM_SOFT_RESET=0x%08X\n"

	.comm	_SRBM_SOFT_RESET,4,2            ; @SRBM_SOFT_RESET
l_.str.7:                               ; @.str.7
	.asciz	"SRBM_SOFT_RESET=0x%08X\n"

	.no_dead_strip	_cayman_gpu_soft_reset
.subsections_via_symbols
