	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function intel_init_display
_intel_init_display:                    ## @intel_init_display
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	(%rdi), %rbx
	callq	_HAS_DDI
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	_ironlake_update_plane@GOTPCREL(%rip), %rdi
	movq	_haswell_crtc_off@GOTPCREL(%rip), %rsi
	movq	_haswell_crtc_disable@GOTPCREL(%rip), %rdx
	movq	_haswell_crtc_enable@GOTPCREL(%rip), %rcx
	movq	_haswell_crtc_mode_set@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_2:
	movq	%r14, %rdi
	callq	_HAS_PCH_SPLIT
	testq	%rax, %rax
	movq	_ironlake_crtc_mode_set@GOTPCREL(%rip), %rax
	cmoveq	_i9xx_crtc_mode_set@GOTPCREL(%rip), %rax
	movq	_ironlake_crtc_enable@GOTPCREL(%rip), %rcx
	cmoveq	_i9xx_crtc_enable@GOTPCREL(%rip), %rcx
	movq	_ironlake_crtc_disable@GOTPCREL(%rip), %rdx
	cmoveq	_i9xx_crtc_disable@GOTPCREL(%rip), %rdx
	movq	_ironlake_crtc_off@GOTPCREL(%rip), %rsi
	cmoveq	_i9xx_crtc_off@GOTPCREL(%rip), %rsi
	movq	_ironlake_update_plane@GOTPCREL(%rip), %rdi
	cmoveq	_i9xx_update_plane@GOTPCREL(%rip), %rdi
LBB0_3:
	movl	(%rax), %eax
	movl	%eax, 52(%rbx)
	movl	(%rcx), %eax
	movl	%eax, 48(%rbx)
	movl	(%rdx), %eax
	movl	%eax, 44(%rbx)
	movl	(%rsi), %eax
	movl	%eax, 40(%rbx)
	movq	(%rdi), %rax
	movq	%rax, 32(%rbx)
	movq	%r14, %rdi
	callq	_IS_VALLEYVIEW
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	movq	_valleyview_get_display_clock_speed@GOTPCREL(%rip), %r15
	jmp	LBB0_20
LBB0_5:
	movq	%r14, %rdi
	callq	_IS_I945G
	movq	_i945_get_display_clock_speed@GOTPCREL(%rip), %r15
	testq	%rax, %rax
	jne	LBB0_20
## %bb.6:
	movq	%r14, %rdi
	callq	_IS_G33
	testq	%rax, %rax
	je	LBB0_8
## %bb.7:
	movq	%r14, %rdi
	callq	_IS_PINEVIEW_M
	testq	%rax, %rax
	je	LBB0_20
LBB0_8:
	movq	%r14, %rdi
	callq	_IS_I915G
	testq	%rax, %rax
	je	LBB0_10
## %bb.9:
	movq	_i915_get_display_clock_speed@GOTPCREL(%rip), %r15
	jmp	LBB0_20
LBB0_10:
	movq	%r14, %rdi
	callq	_IS_I945GM
	movq	_i9xx_misc_get_display_clock_speed@GOTPCREL(%rip), %r15
	testq	%rax, %rax
	jne	LBB0_20
## %bb.11:
	movq	%r14, %rdi
	callq	_IS_845G
	testq	%rax, %rax
	jne	LBB0_20
## %bb.12:
	movq	%r14, %rdi
	callq	_IS_PINEVIEW_M
	testq	%rax, %rax
	jne	LBB0_20
## %bb.13:
	movq	%r14, %rdi
	callq	_IS_I915GM
	testq	%rax, %rax
	je	LBB0_15
## %bb.14:
	movq	_i915gm_get_display_clock_speed@GOTPCREL(%rip), %r15
	jmp	LBB0_20
LBB0_15:
	movq	%r14, %rdi
	callq	_IS_I865G
	testq	%rax, %rax
	je	LBB0_17
## %bb.16:
	movq	_i865_get_display_clock_speed@GOTPCREL(%rip), %r15
	jmp	LBB0_20
LBB0_17:
	movq	%r14, %rdi
	callq	_IS_I85X
	testq	%rax, %rax
	jne	LBB0_18
## %bb.19:
	movq	_i830_get_display_clock_speed@GOTPCREL(%rip), %r15
	jmp	LBB0_20
LBB0_18:
	movq	_i855_get_display_clock_speed@GOTPCREL(%rip), %r15
LBB0_20:
	movl	(%r15), %eax
	movl	%eax, 24(%rbx)
	movq	%r14, %rdi
	callq	_HAS_PCH_SPLIT
	movq	%r14, %rdi
	testq	%rax, %rax
	je	LBB0_31
## %bb.21:
	callq	_IS_GEN5
	testq	%rax, %rax
	je	LBB0_24
## %bb.22:
	movq	_ironlake_fdi_link_train@GOTPCREL(%rip), %rax
	jmp	LBB0_23
LBB0_31:
	callq	_IS_G4X
	testq	%rax, %rax
	je	LBB0_34
## %bb.32:
	movq	_g4x_write_eld@GOTPCREL(%rip), %rax
	jmp	LBB0_33
LBB0_24:
	movq	%r14, %rdi
	callq	_IS_GEN6
	testq	%rax, %rax
	je	LBB0_26
## %bb.25:
	movq	_gen6_fdi_link_train@GOTPCREL(%rip), %rax
LBB0_23:
	movl	(%rax), %eax
	movl	%eax, 20(%rbx)
	movq	_ironlake_write_eld@GOTPCREL(%rip), %rax
LBB0_33:
	movq	(%rax), %rax
	movq	%rax, 8(%rbx)
LBB0_34:
	movq	_intel_default_queue_flip@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, (%rbx)
	movq	%r14, %rdi
	callq	_INTEL_INFO
	movl	(%rax), %eax
	addl	$-2, %eax
	cmpl	$5, %eax
	ja	LBB0_36
## %bb.35:
	cltq
	leaq	l_switch.table.intel_init_display(%rip), %rcx
	movq	(%rcx,%rax,8), %rax
	movl	(%rax), %eax
	movl	%eax, (%rbx)
LBB0_36:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_26:
	movq	%r14, %rdi
	callq	_IS_IVYBRIDGE
	testq	%rax, %rax
	je	LBB0_29
## %bb.27:
	movq	_ivb_manual_fdi_link_train@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 20(%rbx)
	movq	_ironlake_write_eld@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 8(%rbx)
	movq	_ivb_modeset_global_resources@GOTPCREL(%rip), %rax
	jmp	LBB0_28
LBB0_29:
	movq	%r14, %rdi
	callq	_IS_HASWELL
	testq	%rax, %rax
	je	LBB0_34
## %bb.30:
	movq	_hsw_fdi_link_train@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 20(%rbx)
	movq	_haswell_write_eld@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 8(%rbx)
	movq	_haswell_modeset_global_resources@GOTPCREL(%rip), %rax
LBB0_28:
	movl	(%rax), %eax
	movl	%eax, 16(%rbx)
	jmp	LBB0_34
	.cfi_endproc
                                        ## -- End function
	.comm	_haswell_crtc_mode_set,4,2      ## @haswell_crtc_mode_set
	.comm	_haswell_crtc_enable,4,2        ## @haswell_crtc_enable
	.comm	_haswell_crtc_disable,4,2       ## @haswell_crtc_disable
	.comm	_haswell_crtc_off,4,2           ## @haswell_crtc_off
	.comm	_ironlake_update_plane,8,3      ## @ironlake_update_plane
	.comm	_ironlake_crtc_mode_set,4,2     ## @ironlake_crtc_mode_set
	.comm	_ironlake_crtc_enable,4,2       ## @ironlake_crtc_enable
	.comm	_ironlake_crtc_disable,4,2      ## @ironlake_crtc_disable
	.comm	_ironlake_crtc_off,4,2          ## @ironlake_crtc_off
	.comm	_i9xx_crtc_mode_set,4,2         ## @i9xx_crtc_mode_set
	.comm	_i9xx_crtc_enable,4,2           ## @i9xx_crtc_enable
	.comm	_i9xx_crtc_disable,4,2          ## @i9xx_crtc_disable
	.comm	_i9xx_crtc_off,4,2              ## @i9xx_crtc_off
	.comm	_i9xx_update_plane,8,3          ## @i9xx_update_plane
	.comm	_valleyview_get_display_clock_speed,4,2 ## @valleyview_get_display_clock_speed
	.comm	_i945_get_display_clock_speed,4,2 ## @i945_get_display_clock_speed
	.comm	_i915_get_display_clock_speed,4,2 ## @i915_get_display_clock_speed
	.comm	_i9xx_misc_get_display_clock_speed,4,2 ## @i9xx_misc_get_display_clock_speed
	.comm	_i915gm_get_display_clock_speed,4,2 ## @i915gm_get_display_clock_speed
	.comm	_i865_get_display_clock_speed,4,2 ## @i865_get_display_clock_speed
	.comm	_i855_get_display_clock_speed,4,2 ## @i855_get_display_clock_speed
	.comm	_i830_get_display_clock_speed,4,2 ## @i830_get_display_clock_speed
	.comm	_ironlake_fdi_link_train,4,2    ## @ironlake_fdi_link_train
	.comm	_ironlake_write_eld,8,3         ## @ironlake_write_eld
	.comm	_gen6_fdi_link_train,4,2        ## @gen6_fdi_link_train
	.comm	_ivb_manual_fdi_link_train,4,2  ## @ivb_manual_fdi_link_train
	.comm	_ivb_modeset_global_resources,4,2 ## @ivb_modeset_global_resources
	.comm	_hsw_fdi_link_train,4,2         ## @hsw_fdi_link_train
	.comm	_haswell_write_eld,8,3          ## @haswell_write_eld
	.comm	_haswell_modeset_global_resources,4,2 ## @haswell_modeset_global_resources
	.comm	_g4x_write_eld,8,3              ## @g4x_write_eld
	.comm	_intel_default_queue_flip,4,2   ## @intel_default_queue_flip
	.comm	_intel_gen2_queue_flip,4,2      ## @intel_gen2_queue_flip
	.comm	_intel_gen3_queue_flip,4,2      ## @intel_gen3_queue_flip
	.comm	_intel_gen4_queue_flip,4,2      ## @intel_gen4_queue_flip
	.comm	_intel_gen6_queue_flip,4,2      ## @intel_gen6_queue_flip
	.comm	_intel_gen7_queue_flip,4,2      ## @intel_gen7_queue_flip
	.no_dead_strip	_intel_init_display
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.intel_init_display
l_switch.table.intel_init_display:
	.quad	_intel_gen2_queue_flip
	.quad	_intel_gen3_queue_flip
	.quad	_intel_gen4_queue_flip
	.quad	_intel_gen4_queue_flip
	.quad	_intel_gen6_queue_flip
	.quad	_intel_gen7_queue_flip

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function intel_init_display
_intel_init_display:                    ; @intel_init_display
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x20, [x0]
	bl	_HAS_DDI
Lloh0:
	adrp	x21, _ironlake_update_plane@GOTPAGE
Lloh1:
	ldr	x21, [x21, _ironlake_update_plane@GOTPAGEOFF]
	cbz	x0, LBB0_2
; %bb.1:
Lloh2:
	adrp	x10, _haswell_crtc_off@GOTPAGE
Lloh3:
	ldr	x10, [x10, _haswell_crtc_off@GOTPAGEOFF]
Lloh4:
	adrp	x9, _haswell_crtc_disable@GOTPAGE
Lloh5:
	ldr	x9, [x9, _haswell_crtc_disable@GOTPAGEOFF]
Lloh6:
	adrp	x11, _haswell_crtc_enable@GOTPAGE
Lloh7:
	ldr	x11, [x11, _haswell_crtc_enable@GOTPAGEOFF]
Lloh8:
	adrp	x8, _haswell_crtc_mode_set@GOTPAGE
Lloh9:
	ldr	x8, [x8, _haswell_crtc_mode_set@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:
	mov	x0, x19
	bl	_HAS_PCH_SPLIT
Lloh10:
	adrp	x8, _ironlake_crtc_mode_set@GOTPAGE
Lloh11:
	ldr	x8, [x8, _ironlake_crtc_mode_set@GOTPAGEOFF]
Lloh12:
	adrp	x9, _i9xx_crtc_mode_set@GOTPAGE
Lloh13:
	ldr	x9, [x9, _i9xx_crtc_mode_set@GOTPAGEOFF]
	cmp	x0, #0
	csel	x8, x9, x8, eq
Lloh14:
	adrp	x9, _ironlake_crtc_enable@GOTPAGE
Lloh15:
	ldr	x9, [x9, _ironlake_crtc_enable@GOTPAGEOFF]
Lloh16:
	adrp	x10, _i9xx_crtc_enable@GOTPAGE
Lloh17:
	ldr	x10, [x10, _i9xx_crtc_enable@GOTPAGEOFF]
Lloh18:
	adrp	x12, _ironlake_crtc_disable@GOTPAGE
Lloh19:
	ldr	x12, [x12, _ironlake_crtc_disable@GOTPAGEOFF]
	csel	x11, x10, x9, eq
Lloh20:
	adrp	x9, _i9xx_crtc_disable@GOTPAGE
Lloh21:
	ldr	x9, [x9, _i9xx_crtc_disable@GOTPAGEOFF]
	csel	x9, x9, x12, eq
Lloh22:
	adrp	x10, _ironlake_crtc_off@GOTPAGE
Lloh23:
	ldr	x10, [x10, _ironlake_crtc_off@GOTPAGEOFF]
Lloh24:
	adrp	x12, _i9xx_crtc_off@GOTPAGE
Lloh25:
	ldr	x12, [x12, _i9xx_crtc_off@GOTPAGEOFF]
	csel	x10, x12, x10, eq
Lloh26:
	adrp	x12, _i9xx_update_plane@GOTPAGE
Lloh27:
	ldr	x12, [x12, _i9xx_update_plane@GOTPAGEOFF]
	csel	x21, x12, x21, eq
LBB0_3:
	ldr	w8, [x8]
	ldr	w11, [x11]
	stp	w11, w8, [x20, #48]
	ldr	w8, [x9]
	ldr	w9, [x10]
	stp	w9, w8, [x20, #40]
	ldr	x8, [x21]
	str	x8, [x20, #32]
	mov	x0, x19
	bl	_IS_VALLEYVIEW
	cbz	x0, LBB0_5
; %bb.4:
Lloh28:
	adrp	x8, _valleyview_get_display_clock_speed@GOTPAGE
Lloh29:
	ldr	x8, [x8, _valleyview_get_display_clock_speed@GOTPAGEOFF]
	b	LBB0_15
LBB0_5:
	mov	x0, x19
	bl	_IS_I945G
	cbz	x0, LBB0_7
LBB0_6:
Lloh30:
	adrp	x8, _i945_get_display_clock_speed@GOTPAGE
Lloh31:
	ldr	x8, [x8, _i945_get_display_clock_speed@GOTPAGEOFF]
	b	LBB0_15
LBB0_7:
	mov	x0, x19
	bl	_IS_G33
	cbz	x0, LBB0_9
; %bb.8:
	mov	x0, x19
	bl	_IS_PINEVIEW_M
	cbz	x0, LBB0_6
LBB0_9:
	mov	x0, x19
	bl	_IS_I915G
	cbz	x0, LBB0_11
; %bb.10:
Lloh32:
	adrp	x8, _i915_get_display_clock_speed@GOTPAGE
Lloh33:
	ldr	x8, [x8, _i915_get_display_clock_speed@GOTPAGEOFF]
	b	LBB0_15
LBB0_11:
	mov	x0, x19
	bl	_IS_I945GM
	cbnz	x0, LBB0_14
; %bb.12:
	mov	x0, x19
	bl	_IS_845G
	cbnz	x0, LBB0_14
; %bb.13:
	mov	x0, x19
	bl	_IS_PINEVIEW_M
	cbz	x0, LBB0_32
LBB0_14:
Lloh34:
	adrp	x8, _i9xx_misc_get_display_clock_speed@GOTPAGE
Lloh35:
	ldr	x8, [x8, _i9xx_misc_get_display_clock_speed@GOTPAGEOFF]
LBB0_15:
	ldr	w8, [x8]
	str	w8, [x20, #24]
	mov	x0, x19
	bl	_HAS_PCH_SPLIT
	cbz	x0, LBB0_18
; %bb.16:
	mov	x0, x19
	bl	_IS_GEN5
	cbz	x0, LBB0_20
; %bb.17:
Lloh36:
	adrp	x8, _ironlake_fdi_link_train@GOTPAGE
Lloh37:
	ldr	x8, [x8, _ironlake_fdi_link_train@GOTPAGEOFF]
	b	LBB0_22
LBB0_18:
	mov	x0, x19
	bl	_IS_G4X
	cbz	x0, LBB0_24
; %bb.19:
Lloh38:
	adrp	x8, _g4x_write_eld@GOTPAGE
Lloh39:
	ldr	x8, [x8, _g4x_write_eld@GOTPAGEOFF]
	b	LBB0_23
LBB0_20:
	mov	x0, x19
	bl	_IS_GEN6
	cbz	x0, LBB0_27
; %bb.21:
Lloh40:
	adrp	x8, _gen6_fdi_link_train@GOTPAGE
Lloh41:
	ldr	x8, [x8, _gen6_fdi_link_train@GOTPAGEOFF]
LBB0_22:
	ldr	w8, [x8]
	str	w8, [x20, #20]
Lloh42:
	adrp	x8, _ironlake_write_eld@GOTPAGE
Lloh43:
	ldr	x8, [x8, _ironlake_write_eld@GOTPAGEOFF]
LBB0_23:
	ldr	x8, [x8]
	str	x8, [x20, #8]
LBB0_24:
Lloh44:
	adrp	x8, _intel_default_queue_flip@GOTPAGE
Lloh45:
	ldr	x8, [x8, _intel_default_queue_flip@GOTPAGEOFF]
Lloh46:
	ldr	w8, [x8]
	str	w8, [x20]
	mov	x0, x19
	bl	_INTEL_INFO
	ldr	w8, [x0]
	sub	w8, w8, #2
	cmp	w8, #5
	b.hi	LBB0_26
; %bb.25:
Lloh47:
	adrp	x9, l_switch.table.intel_init_display@PAGE
Lloh48:
	add	x9, x9, l_switch.table.intel_init_display@PAGEOFF
	ldr	x8, [x9, w8, sxtw #3]
	ldr	w8, [x8]
	str	w8, [x20]
LBB0_26:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_27:
	mov	x0, x19
	bl	_IS_IVYBRIDGE
	cbz	x0, LBB0_29
; %bb.28:
Lloh49:
	adrp	x8, _ivb_manual_fdi_link_train@GOTPAGE
Lloh50:
	ldr	x8, [x8, _ivb_manual_fdi_link_train@GOTPAGEOFF]
Lloh51:
	ldr	w8, [x8]
Lloh52:
	adrp	x9, _ironlake_write_eld@GOTPAGE
Lloh53:
	ldr	x9, [x9, _ironlake_write_eld@GOTPAGEOFF]
Lloh54:
	ldr	x9, [x9]
	str	x9, [x20, #8]
Lloh55:
	adrp	x9, _ivb_modeset_global_resources@GOTPAGE
Lloh56:
	ldr	x9, [x9, _ivb_modeset_global_resources@GOTPAGEOFF]
	b	LBB0_31
LBB0_29:
	mov	x0, x19
	bl	_IS_HASWELL
	cbz	x0, LBB0_24
; %bb.30:
Lloh57:
	adrp	x8, _hsw_fdi_link_train@GOTPAGE
Lloh58:
	ldr	x8, [x8, _hsw_fdi_link_train@GOTPAGEOFF]
Lloh59:
	ldr	w8, [x8]
Lloh60:
	adrp	x9, _haswell_write_eld@GOTPAGE
Lloh61:
	ldr	x9, [x9, _haswell_write_eld@GOTPAGEOFF]
Lloh62:
	ldr	x9, [x9]
	str	x9, [x20, #8]
Lloh63:
	adrp	x9, _haswell_modeset_global_resources@GOTPAGE
Lloh64:
	ldr	x9, [x9, _haswell_modeset_global_resources@GOTPAGEOFF]
LBB0_31:
	ldr	w9, [x9]
	stp	w9, w8, [x20, #16]
	b	LBB0_24
LBB0_32:
	mov	x0, x19
	bl	_IS_I915GM
	cbz	x0, LBB0_34
; %bb.33:
Lloh65:
	adrp	x8, _i915gm_get_display_clock_speed@GOTPAGE
Lloh66:
	ldr	x8, [x8, _i915gm_get_display_clock_speed@GOTPAGEOFF]
	b	LBB0_15
LBB0_34:
	mov	x0, x19
	bl	_IS_I865G
	cbz	x0, LBB0_36
; %bb.35:
Lloh67:
	adrp	x8, _i865_get_display_clock_speed@GOTPAGE
Lloh68:
	ldr	x8, [x8, _i865_get_display_clock_speed@GOTPAGEOFF]
	b	LBB0_15
LBB0_36:
	mov	x0, x19
	bl	_IS_I85X
Lloh69:
	adrp	x8, _i855_get_display_clock_speed@GOTPAGE
Lloh70:
	ldr	x8, [x8, _i855_get_display_clock_speed@GOTPAGEOFF]
Lloh71:
	adrp	x9, _i830_get_display_clock_speed@GOTPAGE
Lloh72:
	ldr	x9, [x9, _i830_get_display_clock_speed@GOTPAGEOFF]
	cmp	x0, #0
	csel	x8, x9, x8, eq
	b	LBB0_15
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpAdd	Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGot	Lloh67, Lloh68
	.loh AdrpLdrGot	Lloh71, Lloh72
	.loh AdrpLdrGot	Lloh69, Lloh70
	.cfi_endproc
                                        ; -- End function
	.comm	_haswell_crtc_mode_set,4,2      ; @haswell_crtc_mode_set
	.comm	_haswell_crtc_enable,4,2        ; @haswell_crtc_enable
	.comm	_haswell_crtc_disable,4,2       ; @haswell_crtc_disable
	.comm	_haswell_crtc_off,4,2           ; @haswell_crtc_off
	.comm	_ironlake_update_plane,8,3      ; @ironlake_update_plane
	.comm	_ironlake_crtc_mode_set,4,2     ; @ironlake_crtc_mode_set
	.comm	_ironlake_crtc_enable,4,2       ; @ironlake_crtc_enable
	.comm	_ironlake_crtc_disable,4,2      ; @ironlake_crtc_disable
	.comm	_ironlake_crtc_off,4,2          ; @ironlake_crtc_off
	.comm	_i9xx_crtc_mode_set,4,2         ; @i9xx_crtc_mode_set
	.comm	_i9xx_crtc_enable,4,2           ; @i9xx_crtc_enable
	.comm	_i9xx_crtc_disable,4,2          ; @i9xx_crtc_disable
	.comm	_i9xx_crtc_off,4,2              ; @i9xx_crtc_off
	.comm	_i9xx_update_plane,8,3          ; @i9xx_update_plane
	.comm	_valleyview_get_display_clock_speed,4,2 ; @valleyview_get_display_clock_speed
	.comm	_i945_get_display_clock_speed,4,2 ; @i945_get_display_clock_speed
	.comm	_i915_get_display_clock_speed,4,2 ; @i915_get_display_clock_speed
	.comm	_i9xx_misc_get_display_clock_speed,4,2 ; @i9xx_misc_get_display_clock_speed
	.comm	_i915gm_get_display_clock_speed,4,2 ; @i915gm_get_display_clock_speed
	.comm	_i865_get_display_clock_speed,4,2 ; @i865_get_display_clock_speed
	.comm	_i855_get_display_clock_speed,4,2 ; @i855_get_display_clock_speed
	.comm	_i830_get_display_clock_speed,4,2 ; @i830_get_display_clock_speed
	.comm	_ironlake_fdi_link_train,4,2    ; @ironlake_fdi_link_train
	.comm	_ironlake_write_eld,8,3         ; @ironlake_write_eld
	.comm	_gen6_fdi_link_train,4,2        ; @gen6_fdi_link_train
	.comm	_ivb_manual_fdi_link_train,4,2  ; @ivb_manual_fdi_link_train
	.comm	_ivb_modeset_global_resources,4,2 ; @ivb_modeset_global_resources
	.comm	_hsw_fdi_link_train,4,2         ; @hsw_fdi_link_train
	.comm	_haswell_write_eld,8,3          ; @haswell_write_eld
	.comm	_haswell_modeset_global_resources,4,2 ; @haswell_modeset_global_resources
	.comm	_g4x_write_eld,8,3              ; @g4x_write_eld
	.comm	_intel_default_queue_flip,4,2   ; @intel_default_queue_flip
	.comm	_intel_gen2_queue_flip,4,2      ; @intel_gen2_queue_flip
	.comm	_intel_gen3_queue_flip,4,2      ; @intel_gen3_queue_flip
	.comm	_intel_gen4_queue_flip,4,2      ; @intel_gen4_queue_flip
	.comm	_intel_gen6_queue_flip,4,2      ; @intel_gen6_queue_flip
	.comm	_intel_gen7_queue_flip,4,2      ; @intel_gen7_queue_flip
	.no_dead_strip	_intel_init_display
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.intel_init_display
l_switch.table.intel_init_display:
	.quad	_intel_gen2_queue_flip
	.quad	_intel_gen3_queue_flip
	.quad	_intel_gen4_queue_flip
	.quad	_intel_gen4_queue_flip
	.quad	_intel_gen6_queue_flip
	.quad	_intel_gen7_queue_flip

.subsections_via_symbols
