	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function calc_eng_mem_clock
_calc_eng_mem_clock:                    ## @calc_eng_mem_clock
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rcx, %r14
	movq	%rdx, %r15
	movl	%esi, %ebx
	movq	%rdi, %r12
	movl	(%rdi), %ecx
	testl	%ecx, %ecx
	je	LBB0_1
## %bb.2:
	cmpl	$14999, %ebx                    ## imm = 0x3A97
	jg	LBB0_4
LBB0_3:
	movl	$8, (%r14)
	shll	$3, %ebx
	jmp	LBB0_9
LBB0_1:
	movq	_RADEON_M_SPLL_REF_FB_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PLL
	movl	%eax, %ecx
	movq	_RADEON_M_SPLL_REF_DIV_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %ecx
	cmpl	$14999, %ebx                    ## imm = 0x3A97
	jle	LBB0_3
LBB0_4:
	cmpl	$29999, %ebx                    ## imm = 0x752F
	ja	LBB0_6
## %bb.5:
	movl	$4, (%r14)
	shll	$2, %ebx
	jmp	LBB0_9
LBB0_6:
	cmpl	$59999, %ebx                    ## imm = 0xEA5F
	ja	LBB0_8
## %bb.7:
	movl	$2, (%r14)
	addl	%ebx, %ebx
	jmp	LBB0_9
LBB0_8:
	movl	$1, (%r14)
LBB0_9:
	imull	%ecx, %ebx
	movl	4(%r12), %esi
	addl	%esi, %ebx
	addl	%esi, %esi
	movl	%ebx, %eax
	cltd
	idivl	%esi
	movzbl	%al, %edx
	movl	%edx, (%r15)
	movzwl	%ax, %eax
	addl	%eax, %eax
	imull	4(%r12), %eax
	cltd
	idivl	%ecx
	cltd
	idivl	(%r14)
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_M_SPLL_REF_FB_DIV,4,2   ## @RADEON_M_SPLL_REF_FB_DIV
	.comm	_RADEON_M_SPLL_REF_DIV_MASK,4,2 ## @RADEON_M_SPLL_REF_DIV_MASK
	.no_dead_strip	_calc_eng_mem_clock
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function calc_eng_mem_clock
_calc_eng_mem_clock:                    ; @calc_eng_mem_clock
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x3
	mov	x21, x2
	mov	x22, x1
	mov	x20, x0
	ldr	w8, [x0]
	cbnz	w8, LBB0_2
; %bb.1:
Lloh0:
	adrp	x8, _RADEON_M_SPLL_REF_FB_DIV@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_M_SPLL_REF_FB_DIV@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_RREG32_PLL
Lloh3:
	adrp	x8, _RADEON_M_SPLL_REF_DIV_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _RADEON_M_SPLL_REF_DIV_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	and	w8, w8, w0
LBB0_2:
	mov	w9, #14999
	cmp	w22, w9
	b.gt	LBB0_4
; %bb.3:
	mov	w9, #8
	str	w9, [x19]
	lsl	w22, w22, #3
	b	LBB0_9
LBB0_4:
	lsr	w9, w22, #4
	cmp	w9, #1874
	b.hi	LBB0_6
; %bb.5:
	mov	w9, #4
	str	w9, [x19]
	lsl	w22, w22, #2
	b	LBB0_9
LBB0_6:
	lsr	w9, w22, #5
	cmp	w9, #1874
	b.hi	LBB0_8
; %bb.7:
	mov	w9, #2
	str	w9, [x19]
	lsl	w22, w22, #1
	b	LBB0_9
LBB0_8:
	mov	w9, #1
	str	w9, [x19]
LBB0_9:
	ldr	w9, [x20, #4]
	madd	w10, w22, w8, w9
	lsl	w9, w9, #1
	sdiv	w9, w10, w9
	and	w10, w9, #0xff
	str	w10, [x21]
	ubfiz	w9, w9, #1, #16
	ldr	w10, [x20, #4]
	mul	w9, w9, w10
	sdiv	w8, w9, w8
	ldr	w9, [x19]
	sdiv	w0, w8, w9
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_M_SPLL_REF_FB_DIV,4,2   ; @RADEON_M_SPLL_REF_FB_DIV
	.comm	_RADEON_M_SPLL_REF_DIV_MASK,4,2 ; @RADEON_M_SPLL_REF_DIV_MASK
	.no_dead_strip	_calc_eng_mem_clock
.subsections_via_symbols
