	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function r600_read_disabled_bios
_r600_read_disabled_bios:               ## @r600_read_disabled_bios
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, -64(%rbp)                 ## 8-byte Spill
	movq	_RADEON_VIPH_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	%rax, %r14
	callq	_RREG32
	movl	%eax, %ebx
	movl	%eax, -96(%rbp)                 ## 4-byte Spill
	movq	_R600_BUS_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	%rax, %r13
	callq	_RREG32
	movl	%eax, %r15d
	movl	%eax, -92(%rbp)                 ## 4-byte Spill
	movq	_AVIVO_D1VGA_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r12d
	movl	%eax, -68(%rbp)                 ## 4-byte Spill
	movq	_AVIVO_D2VGA_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	movq	_AVIVO_VGA_RENDER_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movq	_R600_ROM_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_R600_GENERAL_PWRMGT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	_R600_LOW_VID_LOWER_GPIO_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -72(%rbp)                 ## 4-byte Spill
	movq	_R600_MEDIUM_VID_LOWER_GPIO_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -76(%rbp)                 ## 4-byte Spill
	movq	_R600_HIGH_VID_LOWER_GPIO_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -80(%rbp)                 ## 4-byte Spill
	movq	_R600_CTXSW_VID_LOWER_GPIO_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -84(%rbp)                 ## 4-byte Spill
	movq	_R600_LOWER_GPIO_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -88(%rbp)                 ## 4-byte Spill
	movl	(%r14), %edi
	movq	_RADEON_VIPH_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	%ebx, %esi
	callq	_WREG32
	movl	(%r13), %edi
	movq	_R600_BIOS_ROM_DIS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	%r15d, %esi
	callq	_WREG32
	movq	_AVIVO_D1VGA_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_AVIVO_DVGA_CONTROL_MODE_ENABLE@GOTPCREL(%rip), %r13
	movq	_AVIVO_DVGA_CONTROL_TIMING_SELECT@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	orl	(%r13), %esi
	notl	%esi
	andl	%r12d, %esi
	callq	_WREG32
	movq	_AVIVO_D2VGA_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%rbx), %esi
	orl	(%r13), %esi
	notl	%esi
	andl	-56(%rbp), %esi                 ## 4-byte Folded Reload
	callq	_WREG32
	movq	_AVIVO_VGA_RENDER_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_AVIVO_VGA_VSTATUS_CNTL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	-52(%rbp), %esi                 ## 4-byte Folded Reload
	callq	_WREG32
	movq	_R600_ROM_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_R600_SCK_PRESCALE_CRYSTAL_CLK_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	-48(%rbp), %esi                 ## 4-byte Folded Reload
	movq	_R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	btsl	%eax, %esi
	movq	_R600_SCK_OVERWRITE@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	callq	_WREG32
	movq	_R600_GENERAL_PWRMGT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_R600_OPEN_DRAIN_PADS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	-44(%rbp), %esi                 ## 4-byte Folded Reload
	callq	_WREG32
	movq	_R600_LOW_VID_LOWER_GPIO_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-72(%rbp), %r13d                ## 4-byte Reload
	movl	%r13d, %esi
	andl	$-1025, %esi                    ## imm = 0xFBFF
	callq	_WREG32
	movq	_R600_MEDIUM_VID_LOWER_GPIO_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-76(%rbp), %ebx                 ## 4-byte Reload
	movl	%ebx, %esi
	andl	$-1025, %esi                    ## imm = 0xFBFF
	callq	_WREG32
	movq	_R600_HIGH_VID_LOWER_GPIO_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-80(%rbp), %r12d                ## 4-byte Reload
	movl	%r12d, %esi
	andl	$-1025, %esi                    ## imm = 0xFBFF
	callq	_WREG32
	movq	_R600_CTXSW_VID_LOWER_GPIO_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-84(%rbp), %r14d                ## 4-byte Reload
	movl	%r14d, %esi
	andl	$-1025, %esi                    ## imm = 0xFBFF
	callq	_WREG32
	movq	_R600_LOWER_GPIO_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-88(%rbp), %r15d                ## 4-byte Reload
	movl	%r15d, %esi
	orl	$1024, %esi                     ## imm = 0x400
	callq	_WREG32
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	callq	_radeon_read_bios
	movl	%eax, -64(%rbp)                 ## 4-byte Spill
	movq	_RADEON_VIPH_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-96(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_R600_BUS_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-92(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_AVIVO_D1VGA_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-68(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_AVIVO_D2VGA_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-56(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_AVIVO_VGA_RENDER_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-52(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_R600_ROM_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-48(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_R600_GENERAL_PWRMGT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_R600_LOW_VID_LOWER_GPIO_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r13d, %esi
	callq	_WREG32
	movq	_R600_MEDIUM_VID_LOWER_GPIO_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_R600_HIGH_VID_LOWER_GPIO_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_R600_CTXSW_VID_LOWER_GPIO_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_R600_LOWER_GPIO_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movl	-64(%rbp), %eax                 ## 4-byte Reload
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_VIPH_CONTROL,4,2        ## @RADEON_VIPH_CONTROL
	.comm	_R600_BUS_CNTL,4,2              ## @R600_BUS_CNTL
	.comm	_AVIVO_D1VGA_CONTROL,4,2        ## @AVIVO_D1VGA_CONTROL
	.comm	_AVIVO_D2VGA_CONTROL,4,2        ## @AVIVO_D2VGA_CONTROL
	.comm	_AVIVO_VGA_RENDER_CONTROL,4,2   ## @AVIVO_VGA_RENDER_CONTROL
	.comm	_R600_ROM_CNTL,4,2              ## @R600_ROM_CNTL
	.comm	_R600_GENERAL_PWRMGT,4,2        ## @R600_GENERAL_PWRMGT
	.comm	_R600_LOW_VID_LOWER_GPIO_CNTL,4,2 ## @R600_LOW_VID_LOWER_GPIO_CNTL
	.comm	_R600_MEDIUM_VID_LOWER_GPIO_CNTL,4,2 ## @R600_MEDIUM_VID_LOWER_GPIO_CNTL
	.comm	_R600_HIGH_VID_LOWER_GPIO_CNTL,4,2 ## @R600_HIGH_VID_LOWER_GPIO_CNTL
	.comm	_R600_CTXSW_VID_LOWER_GPIO_CNTL,4,2 ## @R600_CTXSW_VID_LOWER_GPIO_CNTL
	.comm	_R600_LOWER_GPIO_ENABLE,4,2     ## @R600_LOWER_GPIO_ENABLE
	.comm	_RADEON_VIPH_EN,4,2             ## @RADEON_VIPH_EN
	.comm	_R600_BIOS_ROM_DIS,4,2          ## @R600_BIOS_ROM_DIS
	.comm	_AVIVO_DVGA_CONTROL_MODE_ENABLE,4,2 ## @AVIVO_DVGA_CONTROL_MODE_ENABLE
	.comm	_AVIVO_DVGA_CONTROL_TIMING_SELECT,4,2 ## @AVIVO_DVGA_CONTROL_TIMING_SELECT
	.comm	_AVIVO_VGA_VSTATUS_CNTL_MASK,4,2 ## @AVIVO_VGA_VSTATUS_CNTL_MASK
	.comm	_R600_SCK_PRESCALE_CRYSTAL_CLK_MASK,4,2 ## @R600_SCK_PRESCALE_CRYSTAL_CLK_MASK
	.comm	_R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT,4,2 ## @R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT
	.comm	_R600_SCK_OVERWRITE,4,2         ## @R600_SCK_OVERWRITE
	.comm	_R600_OPEN_DRAIN_PADS,4,2       ## @R600_OPEN_DRAIN_PADS
	.no_dead_strip	_r600_read_disabled_bios
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function r600_read_disabled_bios
_r600_read_disabled_bios:               ; @r600_read_disabled_bios
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #144
	.cfi_def_cfa_offset 144
	stp	x28, x27, [sp, #48]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #64]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #80]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #96]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #112]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #128]            ; 16-byte Folded Spill
	add	x29, sp, #128
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	str	x0, [sp, #40]                   ; 8-byte Folded Spill
Lloh0:
	adrp	x8, _RADEON_VIPH_CONTROL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_VIPH_CONTROL@GOTPAGEOFF]
	ldr	w0, [x8]
	mov	x22, x8
	bl	_RREG32
	mov	x24, x0
	str	w0, [sp, #36]                   ; 4-byte Folded Spill
Lloh2:
	adrp	x8, _R600_BUS_CNTL@GOTPAGE
Lloh3:
	ldr	x8, [x8, _R600_BUS_CNTL@GOTPAGEOFF]
	ldr	w0, [x8]
	mov	x23, x8
	bl	_RREG32
	mov	x25, x0
	str	w0, [sp, #32]                   ; 4-byte Folded Spill
Lloh4:
	adrp	x8, _AVIVO_D1VGA_CONTROL@GOTPAGE
Lloh5:
	ldr	x8, [x8, _AVIVO_D1VGA_CONTROL@GOTPAGEOFF]
Lloh6:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x26, x0
	str	w0, [sp, #28]                   ; 4-byte Folded Spill
Lloh7:
	adrp	x8, _AVIVO_D2VGA_CONTROL@GOTPAGE
Lloh8:
	ldr	x8, [x8, _AVIVO_D2VGA_CONTROL@GOTPAGEOFF]
Lloh9:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x27, x0
Lloh10:
	adrp	x8, _AVIVO_VGA_RENDER_CONTROL@GOTPAGE
Lloh11:
	ldr	x8, [x8, _AVIVO_VGA_RENDER_CONTROL@GOTPAGEOFF]
Lloh12:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x19, x0
Lloh13:
	adrp	x8, _R600_ROM_CNTL@GOTPAGE
Lloh14:
	ldr	x8, [x8, _R600_ROM_CNTL@GOTPAGEOFF]
Lloh15:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x28, x0
Lloh16:
	adrp	x8, _R600_GENERAL_PWRMGT@GOTPAGE
Lloh17:
	ldr	x8, [x8, _R600_GENERAL_PWRMGT@GOTPAGEOFF]
Lloh18:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x20, x0
Lloh19:
	adrp	x8, _R600_LOW_VID_LOWER_GPIO_CNTL@GOTPAGE
Lloh20:
	ldr	x8, [x8, _R600_LOW_VID_LOWER_GPIO_CNTL@GOTPAGEOFF]
Lloh21:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x21, x0
Lloh22:
	adrp	x8, _R600_MEDIUM_VID_LOWER_GPIO_CNTL@GOTPAGE
Lloh23:
	ldr	x8, [x8, _R600_MEDIUM_VID_LOWER_GPIO_CNTL@GOTPAGEOFF]
Lloh24:
	ldr	w0, [x8]
	bl	_RREG32
	str	w0, [sp, #24]                   ; 4-byte Folded Spill
Lloh25:
	adrp	x8, _R600_HIGH_VID_LOWER_GPIO_CNTL@GOTPAGE
Lloh26:
	ldr	x8, [x8, _R600_HIGH_VID_LOWER_GPIO_CNTL@GOTPAGEOFF]
Lloh27:
	ldr	w0, [x8]
	bl	_RREG32
	str	w0, [sp, #20]                   ; 4-byte Folded Spill
Lloh28:
	adrp	x8, _R600_CTXSW_VID_LOWER_GPIO_CNTL@GOTPAGE
Lloh29:
	ldr	x8, [x8, _R600_CTXSW_VID_LOWER_GPIO_CNTL@GOTPAGEOFF]
Lloh30:
	ldr	w0, [x8]
	bl	_RREG32
	str	w0, [sp, #16]                   ; 4-byte Folded Spill
Lloh31:
	adrp	x8, _R600_LOWER_GPIO_ENABLE@GOTPAGE
Lloh32:
	ldr	x8, [x8, _R600_LOWER_GPIO_ENABLE@GOTPAGEOFF]
Lloh33:
	ldr	w0, [x8]
	bl	_RREG32
	str	w0, [sp, #12]                   ; 4-byte Folded Spill
	ldr	w0, [x22]
Lloh34:
	adrp	x8, _RADEON_VIPH_EN@GOTPAGE
Lloh35:
	ldr	x8, [x8, _RADEON_VIPH_EN@GOTPAGEOFF]
Lloh36:
	ldr	w8, [x8]
	bic	w1, w24, w8
	bl	_WREG32
	ldr	w0, [x23]
Lloh37:
	adrp	x8, _R600_BIOS_ROM_DIS@GOTPAGE
Lloh38:
	ldr	x8, [x8, _R600_BIOS_ROM_DIS@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
	bic	w1, w25, w8
	bl	_WREG32
Lloh40:
	adrp	x8, _AVIVO_D1VGA_CONTROL@GOTPAGE
Lloh41:
	ldr	x8, [x8, _AVIVO_D1VGA_CONTROL@GOTPAGEOFF]
Lloh42:
	ldr	w0, [x8]
Lloh43:
	adrp	x22, _AVIVO_DVGA_CONTROL_MODE_ENABLE@GOTPAGE
Lloh44:
	ldr	x22, [x22, _AVIVO_DVGA_CONTROL_MODE_ENABLE@GOTPAGEOFF]
	ldr	w8, [x22]
Lloh45:
	adrp	x23, _AVIVO_DVGA_CONTROL_TIMING_SELECT@GOTPAGE
Lloh46:
	ldr	x23, [x23, _AVIVO_DVGA_CONTROL_TIMING_SELECT@GOTPAGEOFF]
	ldr	w9, [x23]
	orr	w8, w9, w8
	bic	w1, w26, w8
	bl	_WREG32
Lloh47:
	adrp	x8, _AVIVO_D2VGA_CONTROL@GOTPAGE
Lloh48:
	ldr	x8, [x8, _AVIVO_D2VGA_CONTROL@GOTPAGEOFF]
Lloh49:
	ldr	w0, [x8]
	ldr	w8, [x22]
	ldr	w9, [x23]
	orr	w8, w9, w8
	bic	w1, w27, w8
	mov	x23, x27
	bl	_WREG32
Lloh50:
	adrp	x8, _AVIVO_VGA_RENDER_CONTROL@GOTPAGE
Lloh51:
	ldr	x8, [x8, _AVIVO_VGA_RENDER_CONTROL@GOTPAGEOFF]
Lloh52:
	ldr	w0, [x8]
Lloh53:
	adrp	x8, _AVIVO_VGA_VSTATUS_CNTL_MASK@GOTPAGE
Lloh54:
	ldr	x8, [x8, _AVIVO_VGA_VSTATUS_CNTL_MASK@GOTPAGEOFF]
Lloh55:
	ldr	w8, [x8]
	mov	x27, x19
	bic	w1, w19, w8
	bl	_WREG32
Lloh56:
	adrp	x8, _R600_ROM_CNTL@GOTPAGE
Lloh57:
	ldr	x8, [x8, _R600_ROM_CNTL@GOTPAGEOFF]
Lloh58:
	ldr	w0, [x8]
Lloh59:
	adrp	x8, _R600_SCK_PRESCALE_CRYSTAL_CLK_MASK@GOTPAGE
Lloh60:
	ldr	x8, [x8, _R600_SCK_PRESCALE_CRYSTAL_CLK_MASK@GOTPAGEOFF]
Lloh61:
	ldr	w8, [x8]
	bic	w8, w28, w8
Lloh62:
	adrp	x9, _R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT@GOTPAGE
Lloh63:
	ldr	x9, [x9, _R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT@GOTPAGEOFF]
Lloh64:
	ldr	w9, [x9]
	mov	w10, #1
	lsl	w9, w10, w9
	orr	w8, w9, w8
Lloh65:
	adrp	x9, _R600_SCK_OVERWRITE@GOTPAGE
Lloh66:
	ldr	x9, [x9, _R600_SCK_OVERWRITE@GOTPAGEOFF]
Lloh67:
	ldr	w9, [x9]
	orr	w1, w8, w9
	bl	_WREG32
Lloh68:
	adrp	x8, _R600_GENERAL_PWRMGT@GOTPAGE
Lloh69:
	ldr	x8, [x8, _R600_GENERAL_PWRMGT@GOTPAGEOFF]
Lloh70:
	ldr	w0, [x8]
Lloh71:
	adrp	x8, _R600_OPEN_DRAIN_PADS@GOTPAGE
Lloh72:
	ldr	x8, [x8, _R600_OPEN_DRAIN_PADS@GOTPAGEOFF]
Lloh73:
	ldr	w8, [x8]
	bic	w1, w20, w8
	bl	_WREG32
Lloh74:
	adrp	x8, _R600_LOW_VID_LOWER_GPIO_CNTL@GOTPAGE
Lloh75:
	ldr	x8, [x8, _R600_LOW_VID_LOWER_GPIO_CNTL@GOTPAGEOFF]
Lloh76:
	ldr	w0, [x8]
	and	w1, w21, #0xfffffbff
	bl	_WREG32
Lloh77:
	adrp	x8, _R600_MEDIUM_VID_LOWER_GPIO_CNTL@GOTPAGE
Lloh78:
	ldr	x8, [x8, _R600_MEDIUM_VID_LOWER_GPIO_CNTL@GOTPAGEOFF]
Lloh79:
	ldr	w0, [x8]
	ldr	w24, [sp, #24]                  ; 4-byte Folded Reload
	and	w1, w24, #0xfffffbff
	bl	_WREG32
Lloh80:
	adrp	x8, _R600_HIGH_VID_LOWER_GPIO_CNTL@GOTPAGE
Lloh81:
	ldr	x8, [x8, _R600_HIGH_VID_LOWER_GPIO_CNTL@GOTPAGEOFF]
Lloh82:
	ldr	w0, [x8]
	ldr	w19, [sp, #20]                  ; 4-byte Folded Reload
	and	w1, w19, #0xfffffbff
	bl	_WREG32
Lloh83:
	adrp	x8, _R600_CTXSW_VID_LOWER_GPIO_CNTL@GOTPAGE
Lloh84:
	ldr	x8, [x8, _R600_CTXSW_VID_LOWER_GPIO_CNTL@GOTPAGEOFF]
Lloh85:
	ldr	w0, [x8]
	ldr	w25, [sp, #16]                  ; 4-byte Folded Reload
	and	w1, w25, #0xfffffbff
	bl	_WREG32
Lloh86:
	adrp	x8, _R600_LOWER_GPIO_ENABLE@GOTPAGE
Lloh87:
	ldr	x8, [x8, _R600_LOWER_GPIO_ENABLE@GOTPAGEOFF]
Lloh88:
	ldr	w0, [x8]
	ldr	w26, [sp, #12]                  ; 4-byte Folded Reload
	orr	w1, w26, #0x400
	bl	_WREG32
	ldr	x0, [sp, #40]                   ; 8-byte Folded Reload
	bl	_radeon_read_bios
	mov	x22, x0
Lloh89:
	adrp	x8, _RADEON_VIPH_CONTROL@GOTPAGE
Lloh90:
	ldr	x8, [x8, _RADEON_VIPH_CONTROL@GOTPAGEOFF]
Lloh91:
	ldr	w0, [x8]
	ldr	w1, [sp, #36]                   ; 4-byte Folded Reload
	bl	_WREG32
Lloh92:
	adrp	x8, _R600_BUS_CNTL@GOTPAGE
Lloh93:
	ldr	x8, [x8, _R600_BUS_CNTL@GOTPAGEOFF]
Lloh94:
	ldr	w0, [x8]
	ldr	w1, [sp, #32]                   ; 4-byte Folded Reload
	bl	_WREG32
Lloh95:
	adrp	x8, _AVIVO_D1VGA_CONTROL@GOTPAGE
Lloh96:
	ldr	x8, [x8, _AVIVO_D1VGA_CONTROL@GOTPAGEOFF]
Lloh97:
	ldr	w0, [x8]
	ldr	w1, [sp, #28]                   ; 4-byte Folded Reload
	bl	_WREG32
Lloh98:
	adrp	x8, _AVIVO_D2VGA_CONTROL@GOTPAGE
Lloh99:
	ldr	x8, [x8, _AVIVO_D2VGA_CONTROL@GOTPAGEOFF]
Lloh100:
	ldr	w0, [x8]
	mov	x1, x23
	bl	_WREG32
Lloh101:
	adrp	x8, _AVIVO_VGA_RENDER_CONTROL@GOTPAGE
Lloh102:
	ldr	x8, [x8, _AVIVO_VGA_RENDER_CONTROL@GOTPAGEOFF]
Lloh103:
	ldr	w0, [x8]
	mov	x1, x27
	bl	_WREG32
Lloh104:
	adrp	x8, _R600_ROM_CNTL@GOTPAGE
Lloh105:
	ldr	x8, [x8, _R600_ROM_CNTL@GOTPAGEOFF]
Lloh106:
	ldr	w0, [x8]
	mov	x1, x28
	bl	_WREG32
Lloh107:
	adrp	x8, _R600_GENERAL_PWRMGT@GOTPAGE
Lloh108:
	ldr	x8, [x8, _R600_GENERAL_PWRMGT@GOTPAGEOFF]
Lloh109:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh110:
	adrp	x8, _R600_LOW_VID_LOWER_GPIO_CNTL@GOTPAGE
Lloh111:
	ldr	x8, [x8, _R600_LOW_VID_LOWER_GPIO_CNTL@GOTPAGEOFF]
Lloh112:
	ldr	w0, [x8]
	mov	x1, x21
	bl	_WREG32
Lloh113:
	adrp	x8, _R600_MEDIUM_VID_LOWER_GPIO_CNTL@GOTPAGE
Lloh114:
	ldr	x8, [x8, _R600_MEDIUM_VID_LOWER_GPIO_CNTL@GOTPAGEOFF]
Lloh115:
	ldr	w0, [x8]
	mov	x1, x24
	bl	_WREG32
Lloh116:
	adrp	x8, _R600_HIGH_VID_LOWER_GPIO_CNTL@GOTPAGE
Lloh117:
	ldr	x8, [x8, _R600_HIGH_VID_LOWER_GPIO_CNTL@GOTPAGEOFF]
Lloh118:
	ldr	w0, [x8]
	mov	x1, x19
	bl	_WREG32
Lloh119:
	adrp	x8, _R600_CTXSW_VID_LOWER_GPIO_CNTL@GOTPAGE
Lloh120:
	ldr	x8, [x8, _R600_CTXSW_VID_LOWER_GPIO_CNTL@GOTPAGEOFF]
Lloh121:
	ldr	w0, [x8]
	mov	x1, x25
	bl	_WREG32
Lloh122:
	adrp	x8, _R600_LOWER_GPIO_ENABLE@GOTPAGE
Lloh123:
	ldr	x8, [x8, _R600_LOWER_GPIO_ENABLE@GOTPAGEOFF]
Lloh124:
	ldr	w0, [x8]
	mov	x1, x26
	bl	_WREG32
	mov	x0, x22
	ldp	x29, x30, [sp, #128]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #112]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #96]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #80]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #64]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #144
	ret
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_VIPH_CONTROL,4,2        ; @RADEON_VIPH_CONTROL
	.comm	_R600_BUS_CNTL,4,2              ; @R600_BUS_CNTL
	.comm	_AVIVO_D1VGA_CONTROL,4,2        ; @AVIVO_D1VGA_CONTROL
	.comm	_AVIVO_D2VGA_CONTROL,4,2        ; @AVIVO_D2VGA_CONTROL
	.comm	_AVIVO_VGA_RENDER_CONTROL,4,2   ; @AVIVO_VGA_RENDER_CONTROL
	.comm	_R600_ROM_CNTL,4,2              ; @R600_ROM_CNTL
	.comm	_R600_GENERAL_PWRMGT,4,2        ; @R600_GENERAL_PWRMGT
	.comm	_R600_LOW_VID_LOWER_GPIO_CNTL,4,2 ; @R600_LOW_VID_LOWER_GPIO_CNTL
	.comm	_R600_MEDIUM_VID_LOWER_GPIO_CNTL,4,2 ; @R600_MEDIUM_VID_LOWER_GPIO_CNTL
	.comm	_R600_HIGH_VID_LOWER_GPIO_CNTL,4,2 ; @R600_HIGH_VID_LOWER_GPIO_CNTL
	.comm	_R600_CTXSW_VID_LOWER_GPIO_CNTL,4,2 ; @R600_CTXSW_VID_LOWER_GPIO_CNTL
	.comm	_R600_LOWER_GPIO_ENABLE,4,2     ; @R600_LOWER_GPIO_ENABLE
	.comm	_RADEON_VIPH_EN,4,2             ; @RADEON_VIPH_EN
	.comm	_R600_BIOS_ROM_DIS,4,2          ; @R600_BIOS_ROM_DIS
	.comm	_AVIVO_DVGA_CONTROL_MODE_ENABLE,4,2 ; @AVIVO_DVGA_CONTROL_MODE_ENABLE
	.comm	_AVIVO_DVGA_CONTROL_TIMING_SELECT,4,2 ; @AVIVO_DVGA_CONTROL_TIMING_SELECT
	.comm	_AVIVO_VGA_VSTATUS_CNTL_MASK,4,2 ; @AVIVO_VGA_VSTATUS_CNTL_MASK
	.comm	_R600_SCK_PRESCALE_CRYSTAL_CLK_MASK,4,2 ; @R600_SCK_PRESCALE_CRYSTAL_CLK_MASK
	.comm	_R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT,4,2 ; @R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT
	.comm	_R600_SCK_OVERWRITE,4,2         ; @R600_SCK_OVERWRITE
	.comm	_R600_OPEN_DRAIN_PADS,4,2       ; @R600_OPEN_DRAIN_PADS
	.no_dead_strip	_r600_read_disabled_bios
.subsections_via_symbols
