	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_setup_pcigart_surface
_radeon_setup_pcigart_surface:          ## @radeon_setup_pcigart_surface
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_RADEON_MAX_SURFACES@GOTPCREL(%rip), %rax
	movl	(%rax), %r9d
	testl	%r9d, %r9d
	jle	LBB0_9
## %bb.1:
	leal	(%r9,%r9), %ecx
	movq	8(%rdi), %rax
	movq	_PCIGART_FILE_PRIV@GOTPCREL(%rip), %r8
	cmpl	$2, %ecx
	movl	$1, %edx
	cmovgel	%ecx, %edx
	movq	(%r8), %rbx
	shlq	$3, %rdx
	leaq	(%rdx,%rdx,4), %rdx
	xorl	%esi, %esi
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	(%rax,%rsi), %rcx
	testq	%rcx, %rcx
	je	LBB0_5
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	cmpq	%rbx, %rcx
	je	LBB0_5
## %bb.4:                               ##   in Loop: Header=BB0_2 Depth=1
	addq	$40, %rsi
	cmpq	%rsi, %rdx
	jne	LBB0_2
	jmp	LBB0_9
LBB0_5:
	movq	(%rdi), %r12
	shlq	$4, %r9
	xorl	%edx, %edx
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_6:                                 ## =>This Inner Loop Header: Depth=1
	cmpl	$0, (%r12,%rbx,2)
	je	LBB0_7
## %bb.8:                               ##   in Loop: Header=BB0_6 Depth=1
	addq	$16, %rbx
	incl	%edx
	cmpq	%rbx, %r9
	jne	LBB0_6
LBB0_9:
	movq	_ENOMEM@GOTPCREL(%rip), %rax
	xorl	%r15d, %r15d
	subl	(%rax), %r15d
LBB0_10:
	movl	%r15d, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_7:
	movl	%edx, 8(%rax,%rsi)
	movq	24(%rdi), %rcx
	movq	%rcx, 24(%rax,%rsi)
	movq	16(%rdi), %rdx
	addq	%rcx, %rdx
	movq	%rdx, 16(%rax,%rsi)
	movq	$0, 32(%rax,%rsi)
	movq	(%r8), %rdi
	movq	%rdi, (%rax,%rsi)
	movl	$1, (%r12,%rbx,2)
	movq	%rcx, 16(%r12,%rbx,2)
	movq	%rdx, 8(%r12,%rbx,2)
	movq	$0, 24(%r12,%rbx,2)
	movq	_RADEON_SURFACE0_INFO@GOTPCREL(%rip), %rax
	movl	%ebx, %r14d
	andl	$-16, %r14d
	movq	(%rax), %rdi
	addq	%r14, %rdi
	xorl	%r15d, %r15d
	xorl	%esi, %esi
	callq	_RADEON_WRITE
	movq	_RADEON_SURFACE0_LOWER_BOUND@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	%r14, %rdi
	movq	16(%r12,%rbx,2), %rsi
	callq	_RADEON_WRITE
	movq	_RADEON_SURFACE0_UPPER_BOUND@GOTPCREL(%rip), %rax
	addq	(%rax), %r14
	movq	8(%r12,%rbx,2), %rsi
	movq	%r14, %rdi
	callq	_RADEON_WRITE
	jmp	LBB0_10
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_MAX_SURFACES,4,2        ## @RADEON_MAX_SURFACES
	.comm	_PCIGART_FILE_PRIV,8,3          ## @PCIGART_FILE_PRIV
	.comm	_ENOMEM,4,2                     ## @ENOMEM
	.comm	_RADEON_SURFACE0_INFO,8,3       ## @RADEON_SURFACE0_INFO
	.comm	_RADEON_SURFACE0_LOWER_BOUND,8,3 ## @RADEON_SURFACE0_LOWER_BOUND
	.comm	_RADEON_SURFACE0_UPPER_BOUND,8,3 ## @RADEON_SURFACE0_UPPER_BOUND
	.no_dead_strip	_radeon_setup_pcigart_surface
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_setup_pcigart_surface
_radeon_setup_pcigart_surface:          ; @radeon_setup_pcigart_surface
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
Lloh0:
	adrp	x8, _RADEON_MAX_SURFACES@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_MAX_SURFACES@GOTPAGEOFF]
Lloh2:
	ldr	w11, [x8]
	cmp	w11, #1
	b.lt	LBB0_7
; %bb.1:
	lsl	w12, w11, #1
	ldr	x8, [x0, #8]
Lloh3:
	adrp	x9, _PCIGART_FILE_PRIV@GOTPAGE
Lloh4:
	ldr	x9, [x9, _PCIGART_FILE_PRIV@GOTPAGEOFF]
	ldr	x10, [x9]
	cmp	w12, #1
	csinc	w12, w12, wzr, gt
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x13, [x8]
	cmp	x13, #0
	ccmp	x13, x10, #4, ne
	b.eq	LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	add	x8, x8, #40
	subs	x12, x12, #1
	b.ne	LBB0_2
	b	LBB0_7
LBB0_4:
	mov	w12, #0
	mov	x10, #0
	ldr	x13, [x0]
	add	x19, x13, #16
	lsl	x11, x11, #4
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	ldur	w13, [x19, #-16]
	cbz	w13, LBB0_9
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	add	x10, x10, #16
	add	x19, x19, #32
	add	w12, w12, #1
	cmp	x11, x10
	b.ne	LBB0_5
LBB0_7:
Lloh5:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh6:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_8:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_9:
	str	w12, [x8, #8]
	ldp	x12, x11, [x0, #16]
	add	x12, x12, x11
	stp	x12, x11, [x8, #16]
	str	xzr, [x8, #32]
	ldr	x9, [x9]
	str	x9, [x8]
	mov	w8, #1
	stur	w8, [x19, #-16]
	stp	x12, x11, [x19, #-8]
	str	xzr, [x19, #8]
Lloh8:
	adrp	x8, _RADEON_SURFACE0_INFO@GOTPAGE
Lloh9:
	ldr	x8, [x8, _RADEON_SURFACE0_INFO@GOTPAGEOFF]
Lloh10:
	ldr	x8, [x8]
	and	x20, x10, #0xfffffff0
	add	x0, x8, x20
	mov	x1, #0
	bl	_RADEON_WRITE
Lloh11:
	adrp	x8, _RADEON_SURFACE0_LOWER_BOUND@GOTPAGE
Lloh12:
	ldr	x8, [x8, _RADEON_SURFACE0_LOWER_BOUND@GOTPAGEOFF]
Lloh13:
	ldr	x8, [x8]
	add	x0, x8, x20
	ldr	x1, [x19]
	bl	_RADEON_WRITE
Lloh14:
	adrp	x8, _RADEON_SURFACE0_UPPER_BOUND@GOTPAGE
Lloh15:
	ldr	x8, [x8, _RADEON_SURFACE0_UPPER_BOUND@GOTPAGEOFF]
Lloh16:
	ldr	x8, [x8]
	add	x0, x8, x20
	ldur	x1, [x19, #-8]
	bl	_RADEON_WRITE
	mov	w0, #0
	b	LBB0_8
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_MAX_SURFACES,4,2        ; @RADEON_MAX_SURFACES
	.comm	_PCIGART_FILE_PRIV,8,3          ; @PCIGART_FILE_PRIV
	.comm	_ENOMEM,4,2                     ; @ENOMEM
	.comm	_RADEON_SURFACE0_INFO,8,3       ; @RADEON_SURFACE0_INFO
	.comm	_RADEON_SURFACE0_LOWER_BOUND,8,3 ; @RADEON_SURFACE0_LOWER_BOUND
	.comm	_RADEON_SURFACE0_UPPER_BOUND,8,3 ; @RADEON_SURFACE0_UPPER_BOUND
	.no_dead_strip	_radeon_setup_pcigart_surface
.subsections_via_symbols
