	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function r420_clock_resume
_r420_clock_resume:                     ## @r420_clock_resume
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_radeon_dynclks@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	decl	%eax
	cmpl	$-3, %eax
	ja	LBB0_2
## %bb.1:
	movq	%r14, %rdi
	movl	$1, %esi
	callq	_radeon_atom_set_clock_gating
LBB0_2:
	movq	_R_00000D_SCLK_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_RREG32_PLL
	movl	%eax, %r15d
	movl	$1, %edi
	callq	_S_00000D_FORCE_CP
	movl	%eax, %r12d
	movl	$1, %edi
	callq	_S_00000D_FORCE_VIP
	movl	%eax, %ebx
	orl	%r12d, %ebx
	orl	%r15d, %ebx
	movq	(%r14), %rax
	movq	_CHIP_R420@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_4
## %bb.3:
	movl	$1, %edi
	callq	_S_00000D_FORCE_PX
	movl	%eax, %r14d
	movl	$1, %edi
	callq	_S_00000D_FORCE_TX
	orl	%ebx, %r14d
	orl	%eax, %r14d
	movl	%r14d, %ebx
LBB0_4:
	movl	(%r13), %edi
	movl	%ebx, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_PLL                     ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_radeon_dynclks,4,2             ## @radeon_dynclks
	.comm	_R_00000D_SCLK_CNTL,4,2         ## @R_00000D_SCLK_CNTL
	.comm	_CHIP_R420,8,3                  ## @CHIP_R420
	.no_dead_strip	_r420_clock_resume
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function r420_clock_resume
_r420_clock_resume:                     ; @r420_clock_resume
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, _radeon_dynclks@GOTPAGE
Lloh1:
	ldr	x8, [x8, _radeon_dynclks@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	sub	w8, w8, #1
	cmn	w8, #3
	b.hi	LBB0_2
; %bb.1:
	mov	x0, x19
	mov	w1, #1
	bl	_radeon_atom_set_clock_gating
LBB0_2:
Lloh3:
	adrp	x22, _R_00000D_SCLK_CNTL@GOTPAGE
Lloh4:
	ldr	x22, [x22, _R_00000D_SCLK_CNTL@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_RREG32_PLL
	mov	x20, x0
	mov	w0, #1
	bl	_S_00000D_FORCE_CP
	mov	x21, x0
	mov	w0, #1
	bl	_S_00000D_FORCE_VIP
	orr	w8, w21, w20
	orr	w20, w8, w0
	ldr	x8, [x19]
Lloh5:
	adrp	x9, _CHIP_R420@GOTPAGE
Lloh6:
	ldr	x9, [x9, _CHIP_R420@GOTPAGEOFF]
Lloh7:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_4
; %bb.3:
	mov	w0, #1
	bl	_S_00000D_FORCE_PX
	mov	x19, x0
	mov	w0, #1
	bl	_S_00000D_FORCE_TX
	orr	w8, w19, w20
	orr	w20, w8, w0
LBB0_4:
	ldr	w0, [x22]
	mov	x1, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32_PLL
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_radeon_dynclks,4,2             ; @radeon_dynclks
	.comm	_R_00000D_SCLK_CNTL,4,2         ; @R_00000D_SCLK_CNTL
	.comm	_CHIP_R420,8,3                  ; @CHIP_R420
	.no_dead_strip	_r420_clock_resume
.subsections_via_symbols
