	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function i915_restore_display
_i915_restore_display:                  ## @i915_restore_display
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	(%rdi), %r14
	callq	_INTEL_INFO
	cmpl	$4, (%rax)
	jg	LBB0_2
## %bb.1:
	movq	_DSPARB@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	72(%r14), %esi
	callq	_I915_WRITE
LBB0_2:
	movq	_DRIVER_MODESET@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_drm_core_check_feature
	testl	%eax, %eax
	jne	LBB0_4
## %bb.3:
	movq	%rbx, %rdi
	callq	_i915_restore_display_reg
LBB0_4:
	movq	%rbx, %rdi
	callq	_INTEL_INFO
	cmpl	$4, (%rax)
	jl	LBB0_7
## %bb.5:
	movq	%rbx, %rdi
	callq	_HAS_PCH_SPLIT
	testq	%rax, %rax
	jne	LBB0_7
## %bb.6:
	movq	_BLC_PWM_CTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	60(%r14), %esi
	callq	_I915_WRITE
LBB0_7:
	movq	%rbx, %rdi
	callq	_HAS_PCH_SPLIT
	testq	%rax, %rax
	je	LBB0_9
## %bb.8:
	movq	_PCH_LVDS@GOTPCREL(%rip), %rax
LBB0_12:
	movl	(%rax), %edi
	movl	68(%r14), %esi
	callq	_I915_WRITE
LBB0_13:
	movq	%rbx, %rdi
	callq	_IS_I830
	testl	%eax, %eax
	jne	LBB0_17
## %bb.14:
	movq	%rbx, %rdi
	callq	_IS_845G
	testl	%eax, %eax
	jne	LBB0_17
## %bb.15:
	movq	%rbx, %rdi
	callq	_HAS_PCH_SPLIT
	testq	%rax, %rax
	jne	LBB0_17
## %bb.16:
	movq	_PFIT_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	64(%r14), %esi
	callq	_I915_WRITE
LBB0_17:
	movq	%rbx, %rdi
	callq	_HAS_PCH_SPLIT
	testq	%rax, %rax
	je	LBB0_19
## %bb.18:
	movq	_BLC_PWM_PCH_CTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	40(%r14), %esi
	callq	_I915_WRITE
	movq	_BLC_PWM_PCH_CTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	60(%r14), %esi
	callq	_I915_WRITE
	movq	_BLC_PWM_CPU_CTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	56(%r14), %esi
	callq	_I915_WRITE
	movq	_BLC_PWM_CPU_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	52(%r14), %esi
	callq	_I915_WRITE
	movq	_PCH_PP_ON_DELAYS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	32(%r14), %esi
	callq	_I915_WRITE
	movq	_PCH_PP_OFF_DELAYS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	28(%r14), %esi
	callq	_I915_WRITE
	movq	_PCH_PP_DIVISOR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	24(%r14), %esi
	callq	_I915_WRITE
	movq	_PCH_PP_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	20(%r14), %esi
	callq	_I915_WRITE
	leaq	48(%r14), %rax
	movq	_RSTDBYCTL@GOTPCREL(%rip), %rcx
	jmp	LBB0_20
LBB0_9:
	movq	%rbx, %rdi
	callq	_IS_MOBILE
	testq	%rax, %rax
	je	LBB0_13
## %bb.10:
	movq	%rbx, %rdi
	callq	_IS_I830
	testl	%eax, %eax
	jne	LBB0_13
## %bb.11:
	movq	_LVDS@GOTPCREL(%rip), %rax
	jmp	LBB0_12
LBB0_19:
	movq	_PFIT_PGM_RATIOS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	44(%r14), %esi
	callq	_I915_WRITE
	movq	_BLC_PWM_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	40(%r14), %esi
	callq	_I915_WRITE
	movq	_BLC_HIST_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	36(%r14), %esi
	callq	_I915_WRITE
	movq	_PP_ON_DELAYS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	32(%r14), %esi
	callq	_I915_WRITE
	movq	_PP_OFF_DELAYS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	28(%r14), %esi
	callq	_I915_WRITE
	movq	_PP_DIVISOR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	24(%r14), %esi
	callq	_I915_WRITE
	leaq	20(%r14), %rax
	movq	_PP_CONTROL@GOTPCREL(%rip), %rcx
LBB0_20:
	movl	(%rcx), %edi
	movl	(%rax), %esi
	callq	_I915_WRITE
	movq	%rbx, %rdi
	callq	_intel_disable_fbc
	movq	%rbx, %rdi
	callq	_I915_HAS_FBC
	testq	%rax, %rax
	je	LBB0_27
## %bb.21:
	movq	%rbx, %rdi
	callq	_HAS_PCH_SPLIT
	testq	%rax, %rax
	je	LBB0_23
## %bb.22:
	addq	$16, %r14
	movq	_ILK_DPFC_CB_BASE@GOTPCREL(%rip), %rax
	jmp	LBB0_26
LBB0_23:
	movq	%rbx, %rdi
	callq	_IS_GM45
	testq	%rax, %rax
	je	LBB0_25
## %bb.24:
	addq	$16, %r14
	movq	_DPFC_CB_BASE@GOTPCREL(%rip), %rax
	jmp	LBB0_26
LBB0_25:
	movq	_FBC_CFB_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	12(%r14), %esi
	callq	_I915_WRITE
	movq	_FBC_LL_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	8(%r14), %esi
	callq	_I915_WRITE
	movq	_FBC_CONTROL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	4(%r14), %esi
	callq	_I915_WRITE
	movq	_FBC_CONTROL@GOTPCREL(%rip), %rax
LBB0_26:
	movl	(%rax), %edi
	movl	(%r14), %esi
	callq	_I915_WRITE
LBB0_27:
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_drm_core_check_feature
	movq	%rbx, %rdi
	addq	$8, %rsp
	testl	%eax, %eax
	je	LBB0_28
## %bb.29:
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_i915_redisable_vga             ## TAILCALL
LBB0_28:
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_i915_restore_vga               ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_DSPARB,4,2                     ## @DSPARB
	.comm	_DRIVER_MODESET,4,2             ## @DRIVER_MODESET
	.comm	_BLC_PWM_CTL2,4,2               ## @BLC_PWM_CTL2
	.comm	_PCH_LVDS,4,2                   ## @PCH_LVDS
	.comm	_LVDS,4,2                       ## @LVDS
	.comm	_PFIT_CONTROL,4,2               ## @PFIT_CONTROL
	.comm	_BLC_PWM_PCH_CTL1,4,2           ## @BLC_PWM_PCH_CTL1
	.comm	_BLC_PWM_PCH_CTL2,4,2           ## @BLC_PWM_PCH_CTL2
	.comm	_BLC_PWM_CPU_CTL2,4,2           ## @BLC_PWM_CPU_CTL2
	.comm	_BLC_PWM_CPU_CTL,4,2            ## @BLC_PWM_CPU_CTL
	.comm	_PCH_PP_ON_DELAYS,4,2           ## @PCH_PP_ON_DELAYS
	.comm	_PCH_PP_OFF_DELAYS,4,2          ## @PCH_PP_OFF_DELAYS
	.comm	_PCH_PP_DIVISOR,4,2             ## @PCH_PP_DIVISOR
	.comm	_PCH_PP_CONTROL,4,2             ## @PCH_PP_CONTROL
	.comm	_RSTDBYCTL,4,2                  ## @RSTDBYCTL
	.comm	_PFIT_PGM_RATIOS,4,2            ## @PFIT_PGM_RATIOS
	.comm	_BLC_PWM_CTL,4,2                ## @BLC_PWM_CTL
	.comm	_BLC_HIST_CTL,4,2               ## @BLC_HIST_CTL
	.comm	_PP_ON_DELAYS,4,2               ## @PP_ON_DELAYS
	.comm	_PP_OFF_DELAYS,4,2              ## @PP_OFF_DELAYS
	.comm	_PP_DIVISOR,4,2                 ## @PP_DIVISOR
	.comm	_PP_CONTROL,4,2                 ## @PP_CONTROL
	.comm	_ILK_DPFC_CB_BASE,4,2           ## @ILK_DPFC_CB_BASE
	.comm	_DPFC_CB_BASE,4,2               ## @DPFC_CB_BASE
	.comm	_FBC_CFB_BASE,4,2               ## @FBC_CFB_BASE
	.comm	_FBC_LL_BASE,4,2                ## @FBC_LL_BASE
	.comm	_FBC_CONTROL2,4,2               ## @FBC_CONTROL2
	.comm	_FBC_CONTROL,4,2                ## @FBC_CONTROL
	.no_dead_strip	_i915_restore_display
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function i915_restore_display
_i915_restore_display:                  ; @i915_restore_display
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x20, [x0]
	bl	_INTEL_INFO
	ldr	w8, [x0]
	cmp	w8, #4
	b.gt	LBB0_2
; %bb.1:
Lloh0:
	adrp	x8, _DSPARB@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DSPARB@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	ldr	w1, [x20, #72]
	bl	_I915_WRITE
LBB0_2:
Lloh3:
	adrp	x21, _DRIVER_MODESET@GOTPAGE
Lloh4:
	ldr	x21, [x21, _DRIVER_MODESET@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_drm_core_check_feature
	cbnz	w0, LBB0_4
; %bb.3:
	mov	x0, x19
	bl	_i915_restore_display_reg
LBB0_4:
	mov	x0, x19
	bl	_INTEL_INFO
	ldr	w8, [x0]
	cmp	w8, #4
	b.lt	LBB0_7
; %bb.5:
	mov	x0, x19
	bl	_HAS_PCH_SPLIT
	cbnz	x0, LBB0_7
; %bb.6:
Lloh5:
	adrp	x8, _BLC_PWM_CTL2@GOTPAGE
Lloh6:
	ldr	x8, [x8, _BLC_PWM_CTL2@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
	ldr	w1, [x20, #60]
	bl	_I915_WRITE
LBB0_7:
	mov	x0, x19
	bl	_HAS_PCH_SPLIT
	cbz	x0, LBB0_16
; %bb.8:
Lloh8:
	adrp	x8, _PCH_LVDS@GOTPAGE
Lloh9:
	ldr	x8, [x8, _PCH_LVDS@GOTPAGEOFF]
LBB0_9:
	ldr	w0, [x8]
	ldr	w1, [x20, #68]
	bl	_I915_WRITE
LBB0_10:
	mov	x0, x19
	bl	_IS_I830
	cbnz	w0, LBB0_14
; %bb.11:
	mov	x0, x19
	bl	_IS_845G
	cbnz	w0, LBB0_14
; %bb.12:
	mov	x0, x19
	bl	_HAS_PCH_SPLIT
	cbnz	x0, LBB0_14
; %bb.13:
Lloh10:
	adrp	x8, _PFIT_CONTROL@GOTPAGE
Lloh11:
	ldr	x8, [x8, _PFIT_CONTROL@GOTPAGEOFF]
Lloh12:
	ldr	w0, [x8]
	ldr	w1, [x20, #64]
	bl	_I915_WRITE
LBB0_14:
	mov	x0, x19
	bl	_HAS_PCH_SPLIT
	cbz	x0, LBB0_19
; %bb.15:
Lloh13:
	adrp	x8, _BLC_PWM_PCH_CTL1@GOTPAGE
Lloh14:
	ldr	x8, [x8, _BLC_PWM_PCH_CTL1@GOTPAGEOFF]
Lloh15:
	ldr	w0, [x8]
	ldr	w1, [x20, #40]
	bl	_I915_WRITE
Lloh16:
	adrp	x8, _BLC_PWM_PCH_CTL2@GOTPAGE
Lloh17:
	ldr	x8, [x8, _BLC_PWM_PCH_CTL2@GOTPAGEOFF]
Lloh18:
	ldr	w0, [x8]
	ldr	w1, [x20, #60]
	bl	_I915_WRITE
Lloh19:
	adrp	x8, _BLC_PWM_CPU_CTL2@GOTPAGE
Lloh20:
	ldr	x8, [x8, _BLC_PWM_CPU_CTL2@GOTPAGEOFF]
Lloh21:
	ldr	w0, [x8]
	ldr	w1, [x20, #56]
	bl	_I915_WRITE
Lloh22:
	adrp	x8, _BLC_PWM_CPU_CTL@GOTPAGE
Lloh23:
	ldr	x8, [x8, _BLC_PWM_CPU_CTL@GOTPAGEOFF]
Lloh24:
	ldr	w0, [x8]
	ldr	w1, [x20, #52]
	bl	_I915_WRITE
Lloh25:
	adrp	x8, _PCH_PP_ON_DELAYS@GOTPAGE
Lloh26:
	ldr	x8, [x8, _PCH_PP_ON_DELAYS@GOTPAGEOFF]
Lloh27:
	ldr	w0, [x8]
	ldr	w1, [x20, #32]
	bl	_I915_WRITE
Lloh28:
	adrp	x8, _PCH_PP_OFF_DELAYS@GOTPAGE
Lloh29:
	ldr	x8, [x8, _PCH_PP_OFF_DELAYS@GOTPAGEOFF]
Lloh30:
	ldr	w0, [x8]
	ldr	w1, [x20, #28]
	bl	_I915_WRITE
Lloh31:
	adrp	x8, _PCH_PP_DIVISOR@GOTPAGE
Lloh32:
	ldr	x8, [x8, _PCH_PP_DIVISOR@GOTPAGEOFF]
Lloh33:
	ldr	w0, [x8]
	ldr	w1, [x20, #24]
	bl	_I915_WRITE
Lloh34:
	adrp	x8, _PCH_PP_CONTROL@GOTPAGE
Lloh35:
	ldr	x8, [x8, _PCH_PP_CONTROL@GOTPAGEOFF]
Lloh36:
	ldr	w0, [x8]
	ldr	w1, [x20, #20]
	bl	_I915_WRITE
	add	x8, x20, #48
Lloh37:
	adrp	x9, _RSTDBYCTL@GOTPAGE
Lloh38:
	ldr	x9, [x9, _RSTDBYCTL@GOTPAGEOFF]
	b	LBB0_20
LBB0_16:
	mov	x0, x19
	bl	_IS_MOBILE
	cbz	x0, LBB0_10
; %bb.17:
	mov	x0, x19
	bl	_IS_I830
	cbnz	w0, LBB0_10
; %bb.18:
Lloh39:
	adrp	x8, _LVDS@GOTPAGE
Lloh40:
	ldr	x8, [x8, _LVDS@GOTPAGEOFF]
	b	LBB0_9
LBB0_19:
Lloh41:
	adrp	x8, _PFIT_PGM_RATIOS@GOTPAGE
Lloh42:
	ldr	x8, [x8, _PFIT_PGM_RATIOS@GOTPAGEOFF]
Lloh43:
	ldr	w0, [x8]
	ldr	w1, [x20, #44]
	bl	_I915_WRITE
Lloh44:
	adrp	x8, _BLC_PWM_CTL@GOTPAGE
Lloh45:
	ldr	x8, [x8, _BLC_PWM_CTL@GOTPAGEOFF]
Lloh46:
	ldr	w0, [x8]
	ldr	w1, [x20, #40]
	bl	_I915_WRITE
Lloh47:
	adrp	x8, _BLC_HIST_CTL@GOTPAGE
Lloh48:
	ldr	x8, [x8, _BLC_HIST_CTL@GOTPAGEOFF]
Lloh49:
	ldr	w0, [x8]
	ldr	w1, [x20, #36]
	bl	_I915_WRITE
Lloh50:
	adrp	x8, _PP_ON_DELAYS@GOTPAGE
Lloh51:
	ldr	x8, [x8, _PP_ON_DELAYS@GOTPAGEOFF]
Lloh52:
	ldr	w0, [x8]
	ldr	w1, [x20, #32]
	bl	_I915_WRITE
Lloh53:
	adrp	x8, _PP_OFF_DELAYS@GOTPAGE
Lloh54:
	ldr	x8, [x8, _PP_OFF_DELAYS@GOTPAGEOFF]
Lloh55:
	ldr	w0, [x8]
	ldr	w1, [x20, #28]
	bl	_I915_WRITE
Lloh56:
	adrp	x8, _PP_DIVISOR@GOTPAGE
Lloh57:
	ldr	x8, [x8, _PP_DIVISOR@GOTPAGEOFF]
Lloh58:
	ldr	w0, [x8]
	ldr	w1, [x20, #24]
	bl	_I915_WRITE
	add	x8, x20, #20
Lloh59:
	adrp	x9, _PP_CONTROL@GOTPAGE
Lloh60:
	ldr	x9, [x9, _PP_CONTROL@GOTPAGEOFF]
LBB0_20:
	ldr	w0, [x9]
	ldr	w1, [x8]
	bl	_I915_WRITE
	mov	x0, x19
	bl	_intel_disable_fbc
	mov	x0, x19
	bl	_I915_HAS_FBC
	cbz	x0, LBB0_27
; %bb.21:
	mov	x0, x19
	bl	_HAS_PCH_SPLIT
	cbz	x0, LBB0_23
; %bb.22:
	add	x20, x20, #16
Lloh61:
	adrp	x8, _ILK_DPFC_CB_BASE@GOTPAGE
Lloh62:
	ldr	x8, [x8, _ILK_DPFC_CB_BASE@GOTPAGEOFF]
	b	LBB0_26
LBB0_23:
	mov	x0, x19
	bl	_IS_GM45
	cbz	x0, LBB0_25
; %bb.24:
	add	x20, x20, #16
Lloh63:
	adrp	x8, _DPFC_CB_BASE@GOTPAGE
Lloh64:
	ldr	x8, [x8, _DPFC_CB_BASE@GOTPAGEOFF]
	b	LBB0_26
LBB0_25:
Lloh65:
	adrp	x8, _FBC_CFB_BASE@GOTPAGE
Lloh66:
	ldr	x8, [x8, _FBC_CFB_BASE@GOTPAGEOFF]
Lloh67:
	ldr	w0, [x8]
	ldr	w1, [x20, #12]
	bl	_I915_WRITE
Lloh68:
	adrp	x8, _FBC_LL_BASE@GOTPAGE
Lloh69:
	ldr	x8, [x8, _FBC_LL_BASE@GOTPAGEOFF]
Lloh70:
	ldr	w0, [x8]
	ldr	w1, [x20, #8]
	bl	_I915_WRITE
Lloh71:
	adrp	x8, _FBC_CONTROL2@GOTPAGE
Lloh72:
	ldr	x8, [x8, _FBC_CONTROL2@GOTPAGEOFF]
Lloh73:
	ldr	w0, [x8]
	ldr	w1, [x20, #4]
	bl	_I915_WRITE
Lloh74:
	adrp	x8, _FBC_CONTROL@GOTPAGE
Lloh75:
	ldr	x8, [x8, _FBC_CONTROL@GOTPAGEOFF]
LBB0_26:
	ldr	w0, [x8]
	ldr	w1, [x20]
	bl	_I915_WRITE
LBB0_27:
	ldr	w1, [x21]
	mov	x0, x19
	bl	_drm_core_check_feature
	cbz	w0, LBB0_29
; %bb.28:
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_i915_redisable_vga
LBB0_29:
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_i915_restore_vga
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpLdrGot	Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.cfi_endproc
                                        ; -- End function
	.comm	_DSPARB,4,2                     ; @DSPARB
	.comm	_DRIVER_MODESET,4,2             ; @DRIVER_MODESET
	.comm	_BLC_PWM_CTL2,4,2               ; @BLC_PWM_CTL2
	.comm	_PCH_LVDS,4,2                   ; @PCH_LVDS
	.comm	_LVDS,4,2                       ; @LVDS
	.comm	_PFIT_CONTROL,4,2               ; @PFIT_CONTROL
	.comm	_BLC_PWM_PCH_CTL1,4,2           ; @BLC_PWM_PCH_CTL1
	.comm	_BLC_PWM_PCH_CTL2,4,2           ; @BLC_PWM_PCH_CTL2
	.comm	_BLC_PWM_CPU_CTL2,4,2           ; @BLC_PWM_CPU_CTL2
	.comm	_BLC_PWM_CPU_CTL,4,2            ; @BLC_PWM_CPU_CTL
	.comm	_PCH_PP_ON_DELAYS,4,2           ; @PCH_PP_ON_DELAYS
	.comm	_PCH_PP_OFF_DELAYS,4,2          ; @PCH_PP_OFF_DELAYS
	.comm	_PCH_PP_DIVISOR,4,2             ; @PCH_PP_DIVISOR
	.comm	_PCH_PP_CONTROL,4,2             ; @PCH_PP_CONTROL
	.comm	_RSTDBYCTL,4,2                  ; @RSTDBYCTL
	.comm	_PFIT_PGM_RATIOS,4,2            ; @PFIT_PGM_RATIOS
	.comm	_BLC_PWM_CTL,4,2                ; @BLC_PWM_CTL
	.comm	_BLC_HIST_CTL,4,2               ; @BLC_HIST_CTL
	.comm	_PP_ON_DELAYS,4,2               ; @PP_ON_DELAYS
	.comm	_PP_OFF_DELAYS,4,2              ; @PP_OFF_DELAYS
	.comm	_PP_DIVISOR,4,2                 ; @PP_DIVISOR
	.comm	_PP_CONTROL,4,2                 ; @PP_CONTROL
	.comm	_ILK_DPFC_CB_BASE,4,2           ; @ILK_DPFC_CB_BASE
	.comm	_DPFC_CB_BASE,4,2               ; @DPFC_CB_BASE
	.comm	_FBC_CFB_BASE,4,2               ; @FBC_CFB_BASE
	.comm	_FBC_LL_BASE,4,2                ; @FBC_LL_BASE
	.comm	_FBC_CONTROL2,4,2               ; @FBC_CONTROL2
	.comm	_FBC_CONTROL,4,2                ; @FBC_CONTROL
	.no_dead_strip	_i915_restore_display
.subsections_via_symbols
