	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_rs400_gart_enable              ## -- Begin function rs400_gart_enable
	.p2align	4, 0x90
_rs400_gart_enable:                     ## @rs400_gart_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	callq	_radeon_gart_restore
	movq	_RS690_AIC_CTRL_SCRATCH@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_MC
	movq	_RS690_DIS_OUT_OF_PCI_GART_ACCESS@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_MC
	movl	24(%r12), %ecx
	leal	1048575(%rcx), %eax
	testl	%ecx, %ecx
	cmovnsl	%ecx, %eax
	sarl	$20, %eax
	cmpl	$255, %eax
	jg	LBB0_6
## %bb.1:
	cmpl	$32, %eax
	je	LBB0_2
## %bb.3:
	cmpl	$64, %eax
	je	LBB0_13
## %bb.4:
	cmpl	$128, %eax
	jne	LBB0_12
## %bb.5:
	movq	_RS480_VA_SIZE_128MB@GOTPCREL(%rip), %rax
	jmp	LBB0_14
LBB0_6:
	cmpl	$256, %eax                      ## imm = 0x100
	je	LBB0_10
## %bb.7:
	cmpl	$512, %eax                      ## imm = 0x200
	je	LBB0_11
## %bb.8:
	cmpl	$1024, %eax                     ## imm = 0x400
	jne	LBB0_12
## %bb.9:
	movq	_RS480_VA_SIZE_1GB@GOTPCREL(%rip), %rax
	jmp	LBB0_14
LBB0_2:
	movq	_RS480_VA_SIZE_32MB@GOTPCREL(%rip), %rax
	jmp	LBB0_14
LBB0_13:
	movq	_RS480_VA_SIZE_64MB@GOTPCREL(%rip), %rax
	jmp	LBB0_14
LBB0_10:
	movq	_RS480_VA_SIZE_256MB@GOTPCREL(%rip), %rax
	jmp	LBB0_14
LBB0_11:
	movq	_RS480_VA_SIZE_512MB@GOTPCREL(%rip), %rax
LBB0_14:
	movl	(%rax), %r14d
	movq	(%r12), %rax
	movq	_CHIP_RS690@GOTPCREL(%rip), %r15
	movq	_CHIP_RS740@GOTPCREL(%rip), %r13
	cmpq	(%r15), %rax
	je	LBB0_16
## %bb.15:
	cmpq	(%r13), %rax
	je	LBB0_16
## %bb.17:
	movq	_RADEON_AGP_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$-1, %esi
	callq	_WREG32
	movq	_RS480_AGP_BASE_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	jmp	LBB0_18
LBB0_16:
	movq	_RS690_MCCFG_AGP_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$-1, %esi
	callq	_WREG32_MC
	movq	_RS690_MCCFG_AGP_BASE_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32_MC
LBB0_18:
	movq	_RS690_MC_AGP_TOP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movswl	30(%r12), %esi
	callq	_REG_SET
	movl	%eax, %ebx
	movq	_RS690_MC_AGP_START@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movswl	34(%r12), %esi
	callq	_REG_SET
	orl	%ebx, %eax
	movq	(%r12), %rcx
	cmpq	(%r15), %rcx
	je	LBB0_20
## %bb.19:
	cmpq	(%r13), %rcx
	je	LBB0_20
## %bb.21:
	movq	_RADEON_MC_AGP_LOCATION@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_RADEON_BUS_MASTER_DIS@GOTPCREL(%rip), %rbx
	jmp	LBB0_22
LBB0_20:
	movq	_RS690_MCCFG_AGP_LOCATION@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%eax, %esi
	callq	_WREG32_MC
	movq	_RS600_BUS_MASTER_DIS@GOTPCREL(%rip), %rbx
LBB0_22:
	movq	_RADEON_BUS_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32
	movl	(%rbx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r15), %edi
	callq	_WREG32
	movq	16(%r12), %rdi
	movl	%edi, %ebx
	andl	$-4096, %ebx                    ## imm = 0xF000
	callq	_upper_32_bits
	movzbl	%al, %esi
	shll	$4, %esi
	orl	%ebx, %esi
	movq	_RS480_GART_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32_MC
	movq	_RS480_GART_FEATURE_ID@GOTPCREL(%rip), %rax
	movq	_RS480_TLB_ENABLE@GOTPCREL(%rip), %rcx
	movq	_RS480_GTW_LAC_EN@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	movl	(%rax), %edi
	movq	_RS480_1LEVEL_GART@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	callq	_WREG32_MC
	movq	_RS480_AGP_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RS480_REQ_TYPE_SNOOP_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	movq	_RS480_REQ_TYPE_SNOOP_DIS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	btsl	%eax, %esi
	callq	_WREG32_MC
	movq	(%r12), %rax
	xorl	%r15d, %r15d
	cmpq	(%r13), %rax
	movq	_RS690_BLOCK_GFX_D3_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	$0, %esi
	cmovel	%ecx, %esi
	movq	_CHIP_RS690@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rax
	movq	_RS480_MC_MISC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RS480_GART_INDEX_REG_EN@GOTPCREL(%rip), %rax
	cmovel	%ecx, %esi
	orl	(%rax), %esi
	callq	_WREG32_MC
	movq	_RS480_AGP_ADDRESS_SPACE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RS480_GART_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
	movl	%r14d, %esi
	callq	_WREG32_MC
	movq	%r12, %rdi
	callq	_rs400_gart_tlb_flush
	movl	24(%r12), %esi
	sarl	$20, %esi
	movq	16(%r12), %rdx
	leaq	L_.str(%rip), %rdi
	callq	_DRM_INFO
	movl	$1, 8(%r12)
LBB0_23:
	movl	%r15d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_12:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r15d, %r15d
	subl	(%rax), %r15d
	jmp	LBB0_23
	.cfi_endproc
                                        ## -- End function
	.comm	_RS690_AIC_CTRL_SCRATCH,4,2     ## @RS690_AIC_CTRL_SCRATCH
	.comm	_RS690_DIS_OUT_OF_PCI_GART_ACCESS,4,2 ## @RS690_DIS_OUT_OF_PCI_GART_ACCESS
	.comm	_RS480_VA_SIZE_32MB,4,2         ## @RS480_VA_SIZE_32MB
	.comm	_RS480_VA_SIZE_64MB,4,2         ## @RS480_VA_SIZE_64MB
	.comm	_RS480_VA_SIZE_128MB,4,2        ## @RS480_VA_SIZE_128MB
	.comm	_RS480_VA_SIZE_256MB,4,2        ## @RS480_VA_SIZE_256MB
	.comm	_RS480_VA_SIZE_512MB,4,2        ## @RS480_VA_SIZE_512MB
	.comm	_RS480_VA_SIZE_1GB,4,2          ## @RS480_VA_SIZE_1GB
	.comm	_RS480_VA_SIZE_2GB,4,2          ## @RS480_VA_SIZE_2GB
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_CHIP_RS690,8,3                 ## @CHIP_RS690
	.comm	_CHIP_RS740,8,3                 ## @CHIP_RS740
	.comm	_RS690_MCCFG_AGP_BASE,4,2       ## @RS690_MCCFG_AGP_BASE
	.comm	_RS690_MCCFG_AGP_BASE_2,4,2     ## @RS690_MCCFG_AGP_BASE_2
	.comm	_RADEON_AGP_BASE,4,2            ## @RADEON_AGP_BASE
	.comm	_RS480_AGP_BASE_2,4,2           ## @RS480_AGP_BASE_2
	.comm	_RS690_MC_AGP_TOP,4,2           ## @RS690_MC_AGP_TOP
	.comm	_RS690_MC_AGP_START,4,2         ## @RS690_MC_AGP_START
	.comm	_RS690_MCCFG_AGP_LOCATION,4,2   ## @RS690_MCCFG_AGP_LOCATION
	.comm	_RADEON_BUS_CNTL,4,2            ## @RADEON_BUS_CNTL
	.comm	_RS600_BUS_MASTER_DIS,4,2       ## @RS600_BUS_MASTER_DIS
	.comm	_RADEON_MC_AGP_LOCATION,4,2     ## @RADEON_MC_AGP_LOCATION
	.comm	_RADEON_BUS_MASTER_DIS,4,2      ## @RADEON_BUS_MASTER_DIS
	.comm	_RS480_GART_BASE,4,2            ## @RS480_GART_BASE
	.comm	_RS480_GART_FEATURE_ID,4,2      ## @RS480_GART_FEATURE_ID
	.comm	_RS480_TLB_ENABLE,4,2           ## @RS480_TLB_ENABLE
	.comm	_RS480_GTW_LAC_EN,4,2           ## @RS480_GTW_LAC_EN
	.comm	_RS480_1LEVEL_GART,4,2          ## @RS480_1LEVEL_GART
	.comm	_RS480_AGP_MODE_CNTL,4,2        ## @RS480_AGP_MODE_CNTL
	.comm	_RS480_REQ_TYPE_SNOOP_SHIFT,4,2 ## @RS480_REQ_TYPE_SNOOP_SHIFT
	.comm	_RS480_REQ_TYPE_SNOOP_DIS,4,2   ## @RS480_REQ_TYPE_SNOOP_DIS
	.comm	_RS480_MC_MISC_CNTL,4,2         ## @RS480_MC_MISC_CNTL
	.comm	_RS480_GART_INDEX_REG_EN,4,2    ## @RS480_GART_INDEX_REG_EN
	.comm	_RS690_BLOCK_GFX_D3_EN,4,2      ## @RS690_BLOCK_GFX_D3_EN
	.comm	_RS480_AGP_ADDRESS_SPACE_SIZE,4,2 ## @RS480_AGP_ADDRESS_SPACE_SIZE
	.comm	_RS480_GART_EN,4,2              ## @RS480_GART_EN
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"PCIE GART of %uM enabled (table at 0x%016llX).\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_rs400_gart_enable              ; -- Begin function rs400_gart_enable
	.p2align	2
_rs400_gart_enable:                     ; @rs400_gart_enable
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	bl	_radeon_gart_restore
Lloh0:
	adrp	x20, _RS690_AIC_CTRL_SCRATCH@GOTPAGE
Lloh1:
	ldr	x20, [x20, _RS690_AIC_CTRL_SCRATCH@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_MC
Lloh2:
	adrp	x8, _RS690_DIS_OUT_OF_PCI_GART_ACCESS@GOTPAGE
Lloh3:
	ldr	x8, [x8, _RS690_DIS_OUT_OF_PCI_GART_ACCESS@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x20]
	bl	_WREG32_MC
	ldr	w8, [x19, #24]
	mov	w9, #1048575
	add	w9, w8, w9
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w8, w8, #20
	cmp	w8, #255
	b.gt	LBB0_5
; %bb.1:
	cmp	w8, #32
	b.eq	LBB0_9
; %bb.2:
	cmp	w8, #64
	b.eq	LBB0_10
; %bb.3:
	cmp	w8, #128
	b.ne	LBB0_22
; %bb.4:
Lloh5:
	adrp	x8, _RS480_VA_SIZE_128MB@GOTPAGE
Lloh6:
	ldr	x8, [x8, _RS480_VA_SIZE_128MB@GOTPAGEOFF]
	b	LBB0_13
LBB0_5:
	cmp	w8, #256
	b.eq	LBB0_11
; %bb.6:
	cmp	w8, #512
	b.eq	LBB0_12
; %bb.7:
	cmp	w8, #1024
	b.ne	LBB0_22
; %bb.8:
Lloh7:
	adrp	x8, _RS480_VA_SIZE_1GB@GOTPAGE
Lloh8:
	ldr	x8, [x8, _RS480_VA_SIZE_1GB@GOTPAGEOFF]
	b	LBB0_13
LBB0_9:
Lloh9:
	adrp	x8, _RS480_VA_SIZE_32MB@GOTPAGE
Lloh10:
	ldr	x8, [x8, _RS480_VA_SIZE_32MB@GOTPAGEOFF]
	b	LBB0_13
LBB0_10:
Lloh11:
	adrp	x8, _RS480_VA_SIZE_64MB@GOTPAGE
Lloh12:
	ldr	x8, [x8, _RS480_VA_SIZE_64MB@GOTPAGEOFF]
	b	LBB0_13
LBB0_11:
Lloh13:
	adrp	x8, _RS480_VA_SIZE_256MB@GOTPAGE
Lloh14:
	ldr	x8, [x8, _RS480_VA_SIZE_256MB@GOTPAGEOFF]
	b	LBB0_13
LBB0_12:
Lloh15:
	adrp	x8, _RS480_VA_SIZE_512MB@GOTPAGE
Lloh16:
	ldr	x8, [x8, _RS480_VA_SIZE_512MB@GOTPAGEOFF]
LBB0_13:
	ldr	w21, [x8]
	ldr	x8, [x19]
Lloh17:
	adrp	x22, _CHIP_RS690@GOTPAGE
Lloh18:
	ldr	x22, [x22, _CHIP_RS690@GOTPAGEOFF]
	ldr	x9, [x22]
Lloh19:
	adrp	x23, _CHIP_RS740@GOTPAGE
Lloh20:
	ldr	x23, [x23, _CHIP_RS740@GOTPAGEOFF]
	ldr	x10, [x23]
	cmp	x8, x9
	ccmp	x8, x10, #4, ne
	b.ne	LBB0_15
; %bb.14:
Lloh21:
	adrp	x8, _RS690_MCCFG_AGP_BASE@GOTPAGE
Lloh22:
	ldr	x8, [x8, _RS690_MCCFG_AGP_BASE@GOTPAGEOFF]
Lloh23:
	ldr	w0, [x8]
	mov	w1, #-1
	bl	_WREG32_MC
Lloh24:
	adrp	x8, _RS690_MCCFG_AGP_BASE_2@GOTPAGE
Lloh25:
	ldr	x8, [x8, _RS690_MCCFG_AGP_BASE_2@GOTPAGEOFF]
Lloh26:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32_MC
	b	LBB0_16
LBB0_15:
Lloh27:
	adrp	x8, _RADEON_AGP_BASE@GOTPAGE
Lloh28:
	ldr	x8, [x8, _RADEON_AGP_BASE@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	mov	w1, #-1
	bl	_WREG32
Lloh30:
	adrp	x8, _RS480_AGP_BASE_2@GOTPAGE
Lloh31:
	ldr	x8, [x8, _RS480_AGP_BASE_2@GOTPAGEOFF]
Lloh32:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
LBB0_16:
Lloh33:
	adrp	x8, _RS690_MC_AGP_TOP@GOTPAGE
Lloh34:
	ldr	x8, [x8, _RS690_MC_AGP_TOP@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	ldrsh	w1, [x19, #30]
	bl	_REG_SET
	mov	x20, x0
Lloh36:
	adrp	x8, _RS690_MC_AGP_START@GOTPAGE
Lloh37:
	ldr	x8, [x8, _RS690_MC_AGP_START@GOTPAGEOFF]
Lloh38:
	ldr	w0, [x8]
	ldrsh	w1, [x19, #34]
	bl	_REG_SET
	orr	w1, w0, w20
	ldr	x8, [x19]
	ldr	x9, [x22]
	cmp	x8, x9
	b.eq	LBB0_19
; %bb.17:
	ldr	x9, [x23]
	cmp	x8, x9
	b.eq	LBB0_19
; %bb.18:
Lloh39:
	adrp	x8, _RADEON_MC_AGP_LOCATION@GOTPAGE
Lloh40:
	ldr	x8, [x8, _RADEON_MC_AGP_LOCATION@GOTPAGEOFF]
Lloh41:
	ldr	w0, [x8]
	bl	_WREG32
Lloh42:
	adrp	x20, _RADEON_BUS_MASTER_DIS@GOTPAGE
Lloh43:
	ldr	x20, [x20, _RADEON_BUS_MASTER_DIS@GOTPAGEOFF]
	b	LBB0_20
LBB0_19:
Lloh44:
	adrp	x8, _RS690_MCCFG_AGP_LOCATION@GOTPAGE
Lloh45:
	ldr	x8, [x8, _RS690_MCCFG_AGP_LOCATION@GOTPAGEOFF]
Lloh46:
	ldr	w0, [x8]
	bl	_WREG32_MC
Lloh47:
	adrp	x20, _RS600_BUS_MASTER_DIS@GOTPAGE
Lloh48:
	ldr	x20, [x20, _RS600_BUS_MASTER_DIS@GOTPAGEOFF]
LBB0_20:
Lloh49:
	adrp	x24, _RADEON_BUS_CNTL@GOTPAGE
Lloh50:
	ldr	x24, [x24, _RADEON_BUS_CNTL@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_RREG32
	ldr	w8, [x20]
	bic	w1, w0, w8
	ldr	w0, [x24]
	bl	_WREG32
	ldr	x0, [x19, #16]
	and	w20, w0, #0xfffff000
	bl	_upper_32_bits
	bfi	w20, w0, #4, #8
Lloh51:
	adrp	x8, _RS480_GART_BASE@GOTPAGE
Lloh52:
	ldr	x8, [x8, _RS480_GART_BASE@GOTPAGEOFF]
Lloh53:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32_MC
Lloh54:
	adrp	x8, _RS480_GART_FEATURE_ID@GOTPAGE
Lloh55:
	ldr	x8, [x8, _RS480_GART_FEATURE_ID@GOTPAGEOFF]
Lloh56:
	ldr	w0, [x8]
Lloh57:
	adrp	x8, _RS480_TLB_ENABLE@GOTPAGE
Lloh58:
	ldr	x8, [x8, _RS480_TLB_ENABLE@GOTPAGEOFF]
Lloh59:
	ldr	w8, [x8]
Lloh60:
	adrp	x9, _RS480_GTW_LAC_EN@GOTPAGE
Lloh61:
	ldr	x9, [x9, _RS480_GTW_LAC_EN@GOTPAGEOFF]
Lloh62:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh63:
	adrp	x9, _RS480_1LEVEL_GART@GOTPAGE
Lloh64:
	ldr	x9, [x9, _RS480_1LEVEL_GART@GOTPAGEOFF]
Lloh65:
	ldr	w9, [x9]
	orr	w1, w8, w9
	bl	_WREG32_MC
Lloh66:
	adrp	x8, _RS480_AGP_MODE_CNTL@GOTPAGE
Lloh67:
	ldr	x8, [x8, _RS480_AGP_MODE_CNTL@GOTPAGEOFF]
Lloh68:
	ldr	w0, [x8]
Lloh69:
	adrp	x8, _RS480_REQ_TYPE_SNOOP_SHIFT@GOTPAGE
Lloh70:
	ldr	x8, [x8, _RS480_REQ_TYPE_SNOOP_SHIFT@GOTPAGEOFF]
Lloh71:
	ldr	w8, [x8]
	mov	w20, #1
	lsl	w8, w20, w8
Lloh72:
	adrp	x9, _RS480_REQ_TYPE_SNOOP_DIS@GOTPAGE
Lloh73:
	ldr	x9, [x9, _RS480_REQ_TYPE_SNOOP_DIS@GOTPAGEOFF]
Lloh74:
	ldr	w9, [x9]
	orr	w1, w8, w9
	bl	_WREG32_MC
	ldr	x8, [x19]
	ldr	x9, [x22]
	ldr	x10, [x23]
	cmp	x8, x10
	ccmp	x8, x9, #4, ne
Lloh75:
	adrp	x8, _RS480_MC_MISC_CNTL@GOTPAGE
Lloh76:
	ldr	x8, [x8, _RS480_MC_MISC_CNTL@GOTPAGEOFF]
Lloh77:
	ldr	w0, [x8]
Lloh78:
	adrp	x8, _RS480_GART_INDEX_REG_EN@GOTPAGE
Lloh79:
	ldr	x8, [x8, _RS480_GART_INDEX_REG_EN@GOTPAGEOFF]
Lloh80:
	ldr	w8, [x8]
Lloh81:
	adrp	x9, _RS690_BLOCK_GFX_D3_EN@GOTPAGE
Lloh82:
	ldr	x9, [x9, _RS690_BLOCK_GFX_D3_EN@GOTPAGEOFF]
Lloh83:
	ldr	w9, [x9]
	csel	w9, w9, wzr, eq
	orr	w1, w8, w9
	bl	_WREG32_MC
Lloh84:
	adrp	x8, _RS480_AGP_ADDRESS_SPACE_SIZE@GOTPAGE
Lloh85:
	ldr	x8, [x8, _RS480_AGP_ADDRESS_SPACE_SIZE@GOTPAGEOFF]
Lloh86:
	ldr	w0, [x8]
Lloh87:
	adrp	x8, _RS480_GART_EN@GOTPAGE
Lloh88:
	ldr	x8, [x8, _RS480_GART_EN@GOTPAGEOFF]
Lloh89:
	ldr	w8, [x8]
	orr	w1, w8, w21
	bl	_WREG32_MC
	mov	x0, x19
	bl	_rs400_gart_tlb_flush
	ldr	w8, [x19, #24]
	asr	w1, w8, #20
	ldr	x2, [x19, #16]
Lloh90:
	adrp	x0, l_.str@PAGE
Lloh91:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_INFO
	mov	w0, #0
	str	w20, [x19, #8]
LBB0_21:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_22:
Lloh92:
	adrp	x8, _EINVAL@GOTPAGE
Lloh93:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh94:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_21
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpAdd	Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.cfi_endproc
                                        ; -- End function
	.comm	_RS690_AIC_CTRL_SCRATCH,4,2     ; @RS690_AIC_CTRL_SCRATCH
	.comm	_RS690_DIS_OUT_OF_PCI_GART_ACCESS,4,2 ; @RS690_DIS_OUT_OF_PCI_GART_ACCESS
	.comm	_RS480_VA_SIZE_32MB,4,2         ; @RS480_VA_SIZE_32MB
	.comm	_RS480_VA_SIZE_64MB,4,2         ; @RS480_VA_SIZE_64MB
	.comm	_RS480_VA_SIZE_128MB,4,2        ; @RS480_VA_SIZE_128MB
	.comm	_RS480_VA_SIZE_256MB,4,2        ; @RS480_VA_SIZE_256MB
	.comm	_RS480_VA_SIZE_512MB,4,2        ; @RS480_VA_SIZE_512MB
	.comm	_RS480_VA_SIZE_1GB,4,2          ; @RS480_VA_SIZE_1GB
	.comm	_RS480_VA_SIZE_2GB,4,2          ; @RS480_VA_SIZE_2GB
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_CHIP_RS690,8,3                 ; @CHIP_RS690
	.comm	_CHIP_RS740,8,3                 ; @CHIP_RS740
	.comm	_RS690_MCCFG_AGP_BASE,4,2       ; @RS690_MCCFG_AGP_BASE
	.comm	_RS690_MCCFG_AGP_BASE_2,4,2     ; @RS690_MCCFG_AGP_BASE_2
	.comm	_RADEON_AGP_BASE,4,2            ; @RADEON_AGP_BASE
	.comm	_RS480_AGP_BASE_2,4,2           ; @RS480_AGP_BASE_2
	.comm	_RS690_MC_AGP_TOP,4,2           ; @RS690_MC_AGP_TOP
	.comm	_RS690_MC_AGP_START,4,2         ; @RS690_MC_AGP_START
	.comm	_RS690_MCCFG_AGP_LOCATION,4,2   ; @RS690_MCCFG_AGP_LOCATION
	.comm	_RADEON_BUS_CNTL,4,2            ; @RADEON_BUS_CNTL
	.comm	_RS600_BUS_MASTER_DIS,4,2       ; @RS600_BUS_MASTER_DIS
	.comm	_RADEON_MC_AGP_LOCATION,4,2     ; @RADEON_MC_AGP_LOCATION
	.comm	_RADEON_BUS_MASTER_DIS,4,2      ; @RADEON_BUS_MASTER_DIS
	.comm	_RS480_GART_BASE,4,2            ; @RS480_GART_BASE
	.comm	_RS480_GART_FEATURE_ID,4,2      ; @RS480_GART_FEATURE_ID
	.comm	_RS480_TLB_ENABLE,4,2           ; @RS480_TLB_ENABLE
	.comm	_RS480_GTW_LAC_EN,4,2           ; @RS480_GTW_LAC_EN
	.comm	_RS480_1LEVEL_GART,4,2          ; @RS480_1LEVEL_GART
	.comm	_RS480_AGP_MODE_CNTL,4,2        ; @RS480_AGP_MODE_CNTL
	.comm	_RS480_REQ_TYPE_SNOOP_SHIFT,4,2 ; @RS480_REQ_TYPE_SNOOP_SHIFT
	.comm	_RS480_REQ_TYPE_SNOOP_DIS,4,2   ; @RS480_REQ_TYPE_SNOOP_DIS
	.comm	_RS480_MC_MISC_CNTL,4,2         ; @RS480_MC_MISC_CNTL
	.comm	_RS480_GART_INDEX_REG_EN,4,2    ; @RS480_GART_INDEX_REG_EN
	.comm	_RS690_BLOCK_GFX_D3_EN,4,2      ; @RS690_BLOCK_GFX_D3_EN
	.comm	_RS480_AGP_ADDRESS_SPACE_SIZE,4,2 ; @RS480_AGP_ADDRESS_SPACE_SIZE
	.comm	_RS480_GART_EN,4,2              ; @RS480_GART_EN
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"PCIE GART of %uM enabled (table at 0x%016llX).\n"

.subsections_via_symbols
