	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function cp_set_surface_sync
_cp_set_surface_sync:                   ## @cp_set_surface_sync
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %r14d
	movl	%edx, %r12d
	movl	%esi, %r15d
	movq	_RADEON_RING_TYPE_GFX_INDEX@GOTPCREL(%rip), %rax
	movq	(%rax), %r13
	shlq	$2, %r13
	addq	8(%rdi), %r13
	movq	(%rdi), %rax
	movq	_CHIP_CAYMAN@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_2
## %bb.1:
	movq	_PACKET3_SET_CONFIG_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_PACKET3
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movq	_PACKET3_SET_CONFIG_REG_START@GOTPCREL(%rip), %rax
	movl	$34280, %esi                    ## imm = 0x85E8
	subl	(%rax), %esi
	sarl	$2, %esi
	movq	%r13, %rdi
	callq	_radeon_ring_write
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	_radeon_ring_write
LBB0_2:
	leal	255(%r12), %ebx
	sarl	$8, %ebx
	cmpl	$-1, %r12d
	cmovel	%r12d, %ebx
	movq	_PACKET3_SURFACE_SYNC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$3, %esi
	callq	_PACKET3
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movq	%r13, %rdi
	movl	%r15d, %esi
	callq	_radeon_ring_write
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_radeon_ring_write
	sarl	$8, %r14d
	movq	%r13, %rdi
	movl	%r14d, %esi
	callq	_radeon_ring_write
	movq	%r13, %rdi
	movl	$10, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_ring_write              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_RING_TYPE_GFX_INDEX,8,3 ## @RADEON_RING_TYPE_GFX_INDEX
	.comm	_CHIP_CAYMAN,8,3                ## @CHIP_CAYMAN
	.comm	_PACKET3_SET_CONFIG_REG,4,2     ## @PACKET3_SET_CONFIG_REG
	.comm	_PACKET3_SET_CONFIG_REG_START,4,2 ## @PACKET3_SET_CONFIG_REG_START
	.comm	_PACKET3_SURFACE_SYNC,4,2       ## @PACKET3_SURFACE_SYNC
	.no_dead_strip	_cp_set_surface_sync
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cp_set_surface_sync
_cp_set_surface_sync:                   ; @cp_set_surface_sync
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x3
	mov	x22, x2
	mov	x21, x1
Lloh0:
	adrp	x8, _RADEON_RING_TYPE_GFX_INDEX@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_RING_TYPE_GFX_INDEX@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	ldp	x10, x9, [x0]
	add	x20, x9, x8, lsl #2
Lloh3:
	adrp	x8, _CHIP_CAYMAN@GOTPAGE
Lloh4:
	ldr	x8, [x8, _CHIP_CAYMAN@GOTPAGEOFF]
Lloh5:
	ldr	x8, [x8]
	cmp	x10, x8
	b.lt	LBB0_2
; %bb.1:
Lloh6:
	adrp	x8, _PACKET3_SET_CONFIG_REG@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PACKET3_SET_CONFIG_REG@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x20
	bl	_radeon_ring_write
Lloh9:
	adrp	x8, _PACKET3_SET_CONFIG_REG_START@GOTPAGE
Lloh10:
	ldr	x8, [x8, _PACKET3_SET_CONFIG_REG_START@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	mov	w9, #34280
	sub	w8, w9, w8
	asr	w1, w8, #2
	mov	x0, x20
	bl	_radeon_ring_write
	mov	x0, x20
	mov	w1, #0
	bl	_radeon_ring_write
LBB0_2:
	add	w8, w22, #255
	asr	w8, w8, #8
	cmn	w22, #1
	csinv	w22, w8, wzr, ne
Lloh12:
	adrp	x8, _PACKET3_SURFACE_SYNC@GOTPAGE
Lloh13:
	ldr	x8, [x8, _PACKET3_SURFACE_SYNC@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	mov	w1, #3
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x20
	bl	_radeon_ring_write
	mov	x0, x20
	mov	x1, x21
	bl	_radeon_ring_write
	mov	x0, x20
	mov	x1, x22
	bl	_radeon_ring_write
	asr	w1, w19, #8
	mov	x0, x20
	bl	_radeon_ring_write
	mov	x0, x20
	mov	w1, #10
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_radeon_ring_write
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_RING_TYPE_GFX_INDEX,8,3 ; @RADEON_RING_TYPE_GFX_INDEX
	.comm	_CHIP_CAYMAN,8,3                ; @CHIP_CAYMAN
	.comm	_PACKET3_SET_CONFIG_REG,4,2     ; @PACKET3_SET_CONFIG_REG
	.comm	_PACKET3_SET_CONFIG_REG_START,4,2 ; @PACKET3_SET_CONFIG_REG_START
	.comm	_PACKET3_SURFACE_SYNC,4,2       ; @PACKET3_SURFACE_SYNC
	.no_dead_strip	_cp_set_surface_sync
.subsections_via_symbols
