	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_atombios_parse_pplib_non_clock_info
_radeon_atombios_parse_pplib_non_clock_info: ## @radeon_atombios_parse_pplib_non_clock_info
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rcx, %rbx
                                        ## kill: def $edx killed $edx def $rdx
	movq	%rdx, -48(%rbp)                 ## 8-byte Spill
	movl	%esi, %r15d
	movq	%rdi, %r12
	movl	4(%rcx), %edi
	callq	_le32_to_cpu
	movl	%eax, %r13d
	movl	(%rbx), %edi
	callq	_le16_to_cpu
	movl	%eax, %ebx
	leaq	-56(%rbp), %rsi
	leaq	-64(%rbp), %rdx
	movq	%r12, %rdi
	callq	_radeon_atombios_get_default_voltages
	movq	16(%r12), %rax
	movslq	%r15d, %rcx
	leaq	(%rcx,%rcx,2), %r14
	shlq	$4, %r14
	movl	%r13d, (%rax,%r14)
	movl	%ebx, 4(%rax,%r14)
	movq	_ATOM_PPLIB_PCIE_LINK_WIDTH_MASK@GOTPCREL(%rip), %rcx
	movl	%r13d, %edx
	andl	(%rcx), %edx
	movq	_ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %edx
	incl	%edx
	movl	%edx, 8(%rax,%r14)
	movq	_ATOM_PPLIB_CLASSIFICATION_UI_MASK@GOTPCREL(%rip), %rcx
	movl	%ebx, %edx
	andl	(%rcx), %edx
	addl	$-128, %edx
	cmpl	$3, %edx
	ja	LBB0_6
## %bb.1:
	movq	_POWER_STATE_TYPE_BATTERY@GOTPCREL(%rip), %rcx
	leaq	LJTI0_0(%rip), %rsi
	movslq	(%rsi,%rdx,4), %rdx
	addq	%rsi, %rdx
	jmpq	*%rdx
LBB0_3:
	movq	_ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE@GOTPCREL(%rip), %rcx
	testl	%ebx, (%rcx)
	je	LBB0_6
LBB0_4:
	movq	_POWER_STATE_TYPE_PERFORMANCE@GOTPCREL(%rip), %rcx
	jmp	LBB0_5
LBB0_2:
	movq	_POWER_STATE_TYPE_BALANCED@GOTPCREL(%rip), %rcx
LBB0_5:
	movq	(%rcx), %rcx
	movq	%rcx, 32(%rax,%r14)
LBB0_6:
	movl	$0, 40(%rax,%r14)
	movq	_ATOM_PPLIB_SINGLE_DISPLAY_ONLY@GOTPCREL(%rip), %rcx
	testl	%r13d, (%rcx)
	je	LBB0_8
## %bb.7:
	leaq	(%rax,%r14), %rcx
	addq	$40, %rcx
	movq	_RADEON_PM_STATE_SINGLE_DISPLAY_ONLY@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movl	%edx, (%rcx)
LBB0_8:
	movq	_ATOM_PPLIB_CLASSIFICATION_BOOT@GOTPCREL(%rip), %rcx
	testl	%ebx, (%rcx)
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	je	LBB0_17
## %bb.9:
	movq	_POWER_STATE_TYPE_DEFAULT@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, 32(%rax,%r14)
	movl	%r15d, 8(%r12)
	leal	-1(%rbx), %ecx
	movslq	%ecx, %rcx
	leaq	(%rcx,%rcx,2), %rcx
	shlq	$3, %rcx
	addq	16(%rax,%r14), %rcx
	movq	%rcx, 24(%rax,%r14)
	movq	%r12, %rdi
	callq	_ASIC_IS_DCE5
	testq	%rax, %rax
	je	LBB0_12
## %bb.10:
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r12)
	je	LBB0_11
LBB0_12:
	testl	%ebx, %ebx
	jle	LBB0_17
## %bb.13:
	movl	52(%r12), %eax
	movq	16(%r12), %rcx
	movq	16(%rcx,%r14), %rcx
	movl	48(%r12), %edx
	movl	%ebx, %esi
	shlq	$3, %rsi
	leaq	(%rsi,%rsi,2), %rsi
	xorl	%edi, %edi
	jmp	LBB0_14
	.p2align	4, 0x90
LBB0_16:                                ##   in Loop: Header=BB0_14 Depth=1
	addq	$24, %rdi
	cmpq	%rdi, %rsi
	je	LBB0_17
LBB0_14:                                ## =>This Inner Loop Header: Depth=1
	movl	%eax, 20(%rcx,%rdi)
	movl	%edx, 16(%rcx,%rdi)
	movq	-56(%rbp), %rbx
	testq	%rbx, %rbx
	je	LBB0_16
## %bb.15:                              ##   in Loop: Header=BB0_14 Depth=1
	movq	%rbx, (%rcx,%rdi)
	jmp	LBB0_16
LBB0_11:
	movq	16(%r12), %rax
	movq	16(%rax,%r14), %rax
	movl	16(%rax), %ecx
	movl	%ecx, 44(%r12)
	movl	20(%rax), %ecx
	movl	%ecx, 40(%r12)
	movq	(%rax), %rcx
	movq	%rcx, 32(%r12)
	movl	8(%rax), %eax
	movl	%eax, 24(%r12)
LBB0_17:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_4, LBB0_4-LJTI0_0
.set L0_0_set_3, LBB0_3-LJTI0_0
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_2, LBB0_2-LJTI0_0
LJTI0_0:
	.long	L0_0_set_4
	.long	L0_0_set_3
	.long	L0_0_set_5
	.long	L0_0_set_2
	.end_data_region
                                        ## -- End function
	.comm	_ATOM_PPLIB_PCIE_LINK_WIDTH_MASK,4,2 ## @ATOM_PPLIB_PCIE_LINK_WIDTH_MASK
	.comm	_ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT,4,2 ## @ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT
	.comm	_ATOM_PPLIB_CLASSIFICATION_UI_MASK,4,2 ## @ATOM_PPLIB_CLASSIFICATION_UI_MASK
	.comm	_POWER_STATE_TYPE_BATTERY,8,3   ## @POWER_STATE_TYPE_BATTERY
	.comm	_POWER_STATE_TYPE_BALANCED,8,3  ## @POWER_STATE_TYPE_BALANCED
	.comm	_POWER_STATE_TYPE_PERFORMANCE,8,3 ## @POWER_STATE_TYPE_PERFORMANCE
	.comm	_ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE,4,2 ## @ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
	.comm	_ATOM_PPLIB_SINGLE_DISPLAY_ONLY,4,2 ## @ATOM_PPLIB_SINGLE_DISPLAY_ONLY
	.comm	_RADEON_PM_STATE_SINGLE_DISPLAY_ONLY,4,2 ## @RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
	.comm	_ATOM_PPLIB_CLASSIFICATION_BOOT,4,2 ## @ATOM_PPLIB_CLASSIFICATION_BOOT
	.comm	_POWER_STATE_TYPE_DEFAULT,8,3   ## @POWER_STATE_TYPE_DEFAULT
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
	.no_dead_strip	_radeon_atombios_parse_pplib_non_clock_info
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_atombios_parse_pplib_non_clock_info
_radeon_atombios_parse_pplib_non_clock_info: ; @radeon_atombios_parse_pplib_non_clock_info
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x22, x3
	mov	x20, x2
	mov	x21, x1
	mov	x19, x0
	ldr	w0, [x3, #4]
	bl	_le32_to_cpu
	mov	x23, x0
	ldr	w0, [x22]
	bl	_le16_to_cpu
	mov	x22, x0
	add	x1, sp, #8
	mov	x2, sp
	mov	x0, x19
	bl	_radeon_atombios_get_default_voltages
	ldr	x8, [x19, #16]
	sxtw	x24, w21
	mov	w9, #48
	smaddl	x9, w21, w9, x8
	stp	w23, w22, [x9]
Lloh0:
	adrp	x10, _ATOM_PPLIB_PCIE_LINK_WIDTH_MASK@GOTPAGE
Lloh1:
	ldr	x10, [x10, _ATOM_PPLIB_PCIE_LINK_WIDTH_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w10, [x10]
	and	w10, w10, w23
Lloh3:
	adrp	x11, _ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT@GOTPAGE
Lloh4:
	ldr	x11, [x11, _ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT@GOTPAGEOFF]
Lloh5:
	ldr	w11, [x11]
	asr	w10, w10, w11
	add	w10, w10, #1
	str	w10, [x9, #8]
Lloh6:
	adrp	x9, _ATOM_PPLIB_CLASSIFICATION_UI_MASK@GOTPAGE
Lloh7:
	ldr	x9, [x9, _ATOM_PPLIB_CLASSIFICATION_UI_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	and	w9, w9, w22
	sub	w10, w9, #128
	cmp	w10, #3
	b.hi	LBB0_6
; %bb.1:
Lloh9:
	adrp	x9, _POWER_STATE_TYPE_BATTERY@GOTPAGE
Lloh10:
	ldr	x9, [x9, _POWER_STATE_TYPE_BATTERY@GOTPAGEOFF]
Lloh11:
	adrp	x11, lJTI0_0@PAGE
Lloh12:
	add	x11, x11, lJTI0_0@PAGEOFF
	adr	x12, LBB0_2
	ldrb	w13, [x11, x10]
	add	x12, x12, x13, lsl #2
	br	x12
LBB0_2:
Lloh13:
	adrp	x9, _ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE@GOTPAGE
Lloh14:
	ldr	x9, [x9, _ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	tst	w9, w22
	b.eq	LBB0_6
LBB0_3:
Lloh16:
	adrp	x9, _POWER_STATE_TYPE_PERFORMANCE@GOTPAGE
Lloh17:
	ldr	x9, [x9, _POWER_STATE_TYPE_PERFORMANCE@GOTPAGEOFF]
	b	LBB0_5
LBB0_4:
Lloh18:
	adrp	x9, _POWER_STATE_TYPE_BALANCED@GOTPAGE
Lloh19:
	ldr	x9, [x9, _POWER_STATE_TYPE_BALANCED@GOTPAGEOFF]
LBB0_5:
	ldr	x9, [x9]
	mov	w10, #48
	madd	x10, x24, x10, x8
	str	x9, [x10, #32]
LBB0_6:
	mov	w9, #48
	madd	x9, x24, x9, x8
	str	wzr, [x9, #40]!
Lloh20:
	adrp	x10, _ATOM_PPLIB_SINGLE_DISPLAY_ONLY@GOTPAGE
Lloh21:
	ldr	x10, [x10, _ATOM_PPLIB_SINGLE_DISPLAY_ONLY@GOTPAGEOFF]
Lloh22:
	ldr	w10, [x10]
	tst	w10, w23
	b.eq	LBB0_8
; %bb.7:
Lloh23:
	adrp	x10, _RADEON_PM_STATE_SINGLE_DISPLAY_ONLY@GOTPAGE
Lloh24:
	ldr	x10, [x10, _RADEON_PM_STATE_SINGLE_DISPLAY_ONLY@GOTPAGEOFF]
Lloh25:
	ldr	w10, [x10]
	str	w10, [x9]
LBB0_8:
Lloh26:
	adrp	x9, _ATOM_PPLIB_CLASSIFICATION_BOOT@GOTPAGE
Lloh27:
	ldr	x9, [x9, _ATOM_PPLIB_CLASSIFICATION_BOOT@GOTPAGEOFF]
Lloh28:
	ldr	w9, [x9]
	tst	w9, w22
	b.eq	LBB0_17
; %bb.9:
Lloh29:
	adrp	x9, _POWER_STATE_TYPE_DEFAULT@GOTPAGE
Lloh30:
	ldr	x9, [x9, _POWER_STATE_TYPE_DEFAULT@GOTPAGEOFF]
Lloh31:
	ldr	x9, [x9]
	mov	w10, #48
	madd	x8, x24, x10, x8
	str	x9, [x8, #32]
	str	w21, [x19, #8]
	ldr	x9, [x8, #16]
	sub	w10, w20, #1
	mov	w11, #24
	smaddl	x9, w10, w11, x9
	str	x9, [x8, #24]
	mov	x0, x19
	bl	_ASIC_IS_DCE5
	cbz	x0, LBB0_11
; %bb.10:
	ldr	w8, [x19]
Lloh32:
	adrp	x9, _RADEON_IS_IGP@GOTPAGE
Lloh33:
	ldr	x9, [x9, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_16
LBB0_11:
	cmp	w20, #1
	b.lt	LBB0_17
; %bb.12:
	ldr	x8, [x19, #16]
	mov	w9, #48
	madd	x8, x24, x9, x8
	ldr	x9, [x8, #16]
	ldr	d0, [x19, #48]
	mov	w8, w20
	add	x9, x9, #16
	b	LBB0_14
LBB0_13:                                ;   in Loop: Header=BB0_14 Depth=1
	add	x9, x9, #24
	subs	x8, x8, #1
	b.eq	LBB0_17
LBB0_14:                                ; =>This Inner Loop Header: Depth=1
	str	d0, [x9]
	ldr	x10, [sp, #8]
	cbz	x10, LBB0_13
; %bb.15:                               ;   in Loop: Header=BB0_14 Depth=1
	stur	x10, [x9, #-16]
	b	LBB0_13
LBB0_16:
	ldr	x8, [x19, #16]
	mov	w9, #48
	madd	x8, x24, x9, x8
	ldr	x8, [x8, #16]
	ldr	d0, [x8, #16]
	rev64.2s	v0, v0
	str	d0, [x19, #40]
	ldr	x9, [x8]
	str	x9, [x19, #32]
	ldr	w8, [x8, #8]
	str	w8, [x19, #24]
LBB0_17:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_3-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
                                        ; -- End function
	.comm	_ATOM_PPLIB_PCIE_LINK_WIDTH_MASK,4,2 ; @ATOM_PPLIB_PCIE_LINK_WIDTH_MASK
	.comm	_ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT,4,2 ; @ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT
	.comm	_ATOM_PPLIB_CLASSIFICATION_UI_MASK,4,2 ; @ATOM_PPLIB_CLASSIFICATION_UI_MASK
	.comm	_POWER_STATE_TYPE_BATTERY,8,3   ; @POWER_STATE_TYPE_BATTERY
	.comm	_POWER_STATE_TYPE_BALANCED,8,3  ; @POWER_STATE_TYPE_BALANCED
	.comm	_POWER_STATE_TYPE_PERFORMANCE,8,3 ; @POWER_STATE_TYPE_PERFORMANCE
	.comm	_ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE,4,2 ; @ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
	.comm	_ATOM_PPLIB_SINGLE_DISPLAY_ONLY,4,2 ; @ATOM_PPLIB_SINGLE_DISPLAY_ONLY
	.comm	_RADEON_PM_STATE_SINGLE_DISPLAY_ONLY,4,2 ; @RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
	.comm	_ATOM_PPLIB_CLASSIFICATION_BOOT,4,2 ; @ATOM_PPLIB_CLASSIFICATION_BOOT
	.comm	_POWER_STATE_TYPE_DEFAULT,8,3   ; @POWER_STATE_TYPE_DEFAULT
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
	.no_dead_strip	_radeon_atombios_parse_pplib_non_clock_info
.subsections_via_symbols
