	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_irq_set_state           ## -- Begin function radeon_irq_set_state
	.p2align	4, 0x90
_radeon_irq_set_state:                  ## @radeon_irq_set_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	8(%rdi), %rax
	testl	%edx, %edx
	je	LBB0_2
## %bb.1:
	orl	(%rax), %esi
	jmp	LBB0_3
LBB0_2:
	notl	%esi
	andl	(%rax), %esi
LBB0_3:
	movl	%esi, (%rax)
	cmpq	$0, (%rdi)
	je	LBB0_4
## %bb.5:
	movq	_RADEON_GEN_INT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	popq	%rbp
	jmp	_RADEON_WRITE                   ## TAILCALL
LBB0_4:
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_GEN_INT_CNTL,4,2        ## @RADEON_GEN_INT_CNTL
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_irq_set_state           ; -- Begin function radeon_irq_set_state
	.p2align	2
_radeon_irq_set_state:                  ; @radeon_irq_set_state
	.cfi_startproc
; %bb.0:
	ldr	x8, [x0, #8]
	cbz	w2, LBB0_2
; %bb.1:
	ldr	w9, [x8]
	orr	w1, w9, w1
	b	LBB0_3
LBB0_2:
	ldr	w9, [x8]
	bic	w1, w9, w1
LBB0_3:
	str	w1, [x8]
	ldr	x8, [x0]
	cbz	x8, LBB0_5
; %bb.4:
Lloh0:
	adrp	x8, _RADEON_GEN_INT_CNTL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_GEN_INT_CNTL@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	b	_RADEON_WRITE
LBB0_5:
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_GEN_INT_CNTL,4,2        ; @RADEON_GEN_INT_CNTL
.subsections_via_symbols
