	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_clear_box
_radeon_clear_box:                      ## @radeon_clear_box
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%r9d, -52(%rbp)                 ## 4-byte Spill
	movl	%r8d, %r15d
	movl	%ecx, -44(%rbp)                 ## 4-byte Spill
	movl	%edx, -48(%rbp)                 ## 4-byte Spill
	movq	%rdi, %r12
	movl	32(%rbp), %r14d
	movl	24(%rbp), %eax
	movl	16(%rbp), %ecx
	movq	%rsi, -64(%rbp)                 ## 8-byte Spill
	movq	(%rsi), %rdx
	movq	8(%rdx), %rdx
	movq	(%rdx), %r13
	movq	8(%rdx), %rbx
	cmpl	$128, (%rdi)
	jne	LBB0_2
## %bb.1:
	shll	$8, %ecx
	andl	$63488, %ecx                    ## imm = 0xF800
	andl	$252, %eax
	leal	(%rcx,%rax,8), %eax
	shrl	$3, %r14d
	andl	$31, %r14d
	orl	%eax, %r14d
	jmp	LBB0_3
LBB0_2:
	shll	$16, %ecx
	shll	$8, %eax
	orl	%ecx, %eax
	orl	%r14d, %eax
	orl	$-16777216, %eax                ## imm = 0xFF000000
	movl	%eax, %r14d
LBB0_3:
	movl	$4, %edi
	callq	_BEGIN_RING
	xorl	%eax, %eax
	callq	_RADEON_WAIT_UNTIL_3D_IDLE
	movq	_RADEON_DP_WRITE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movl	$-1, %edi
	callq	_OUT_RING
	xorl	%eax, %eax
	callq	_ADVANCE_RING
	movl	$6, %edi
	callq	_BEGIN_RING
	movq	_RADEON_CNTL_PAINT_MULTI@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$4, %esi
	callq	_CP_PACKET3
	movl	%eax, %edi
	callq	_OUT_RING
	movq	_RADEON_GMC_DST_PITCH_OFFSET_CNTL@GOTPCREL(%rip), %rax
	movq	_RADEON_GMC_BRUSH_SOLID_COLOR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movl	(%r12), %edi
	shll	$8, %edi
	orl	%ecx, %edi
	movq	_RADEON_GMC_SRC_DATATYPE_COLOR@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	_RADEON_ROP3_P@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	_RADEON_GMC_CLR_CMP_CNTL_DIS@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	callq	_OUT_RING
	movq	-64(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rax
	xorl	%ecx, %ecx
	cmpl	$1, (%rax)
	setne	%cl
	movl	4(%r12,%rcx,4), %edi
	callq	_OUT_RING
	addl	-44(%rbp), %r13d                ## 4-byte Folded Reload
	addl	-48(%rbp), %ebx                 ## 4-byte Folded Reload
	movl	%r14d, %edi
	callq	_OUT_RING
	shll	$16, %ebx
	orl	%r13d, %ebx
	movl	%ebx, %edi
	callq	_OUT_RING
	shll	$16, %r15d
	orl	-52(%rbp), %r15d                ## 4-byte Folded Reload
	movl	%r15d, %edi
	callq	_OUT_RING
	xorl	%eax, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_ADVANCE_RING                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RING_LOCALS,4,2                ## @RING_LOCALS
	.comm	_RADEON_DP_WRITE_MASK,4,2       ## @RADEON_DP_WRITE_MASK
	.comm	_RADEON_CNTL_PAINT_MULTI,4,2    ## @RADEON_CNTL_PAINT_MULTI
	.comm	_RADEON_GMC_DST_PITCH_OFFSET_CNTL,4,2 ## @RADEON_GMC_DST_PITCH_OFFSET_CNTL
	.comm	_RADEON_GMC_BRUSH_SOLID_COLOR,4,2 ## @RADEON_GMC_BRUSH_SOLID_COLOR
	.comm	_RADEON_GMC_SRC_DATATYPE_COLOR,4,2 ## @RADEON_GMC_SRC_DATATYPE_COLOR
	.comm	_RADEON_ROP3_P,4,2              ## @RADEON_ROP3_P
	.comm	_RADEON_GMC_CLR_CMP_CNTL_DIS,4,2 ## @RADEON_GMC_CLR_CMP_CNTL_DIS
	.no_dead_strip	_radeon_clear_box
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_clear_box
_radeon_clear_box:                      ; @radeon_clear_box
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x5
	mov	x20, x4
	mov	x22, x3
	mov	x21, x2
	mov	x24, x1
	mov	x23, x0
	ldr	w8, [x29, #16]
	ldr	x9, [x1]
	ldr	x9, [x9, #8]
	ldp	x27, x26, [x9]
	lsl	w9, w6, #16
	orr	w9, w9, w7, lsl #8
	lsl	w10, w6, #8
	and	w10, w10, #0xf800
	lsl	w11, w7, #3
	bfxil	w10, w11, #0, #11
	ldr	w11, [x0]
	orr	w9, w9, w8
	orr	w9, w9, #0xff000000
	bfxil	w10, w8, #3, #5
	cmp	w11, #128
	csel	w25, w9, w10, ne
	mov	w28, #4
	mov	w0, #4
	bl	_BEGIN_RING
	bl	_RADEON_WAIT_UNTIL_3D_IDLE
Lloh0:
	adrp	x8, _RADEON_DP_WRITE_MASK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_DP_WRITE_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_CP_PACKET0
	bl	_OUT_RING
	mov	w0, #-1
	bl	_OUT_RING
	bl	_ADVANCE_RING
	mov	w0, #6
	bl	_BEGIN_RING
Lloh3:
	adrp	x8, _RADEON_CNTL_PAINT_MULTI@GOTPAGE
Lloh4:
	ldr	x8, [x8, _RADEON_CNTL_PAINT_MULTI@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	mov	w1, #4
	bl	_CP_PACKET3
	bl	_OUT_RING
Lloh6:
	adrp	x8, _RADEON_GMC_DST_PITCH_OFFSET_CNTL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_GMC_DST_PITCH_OFFSET_CNTL@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
Lloh9:
	adrp	x9, _RADEON_GMC_BRUSH_SOLID_COLOR@GOTPAGE
Lloh10:
	ldr	x9, [x9, _RADEON_GMC_BRUSH_SOLID_COLOR@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	orr	w8, w9, w8
	ldr	w9, [x23]
	orr	w8, w8, w9, lsl #8
Lloh12:
	adrp	x9, _RADEON_GMC_SRC_DATATYPE_COLOR@GOTPAGE
Lloh13:
	ldr	x9, [x9, _RADEON_GMC_SRC_DATATYPE_COLOR@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh15:
	adrp	x9, _RADEON_ROP3_P@GOTPAGE
Lloh16:
	ldr	x9, [x9, _RADEON_ROP3_P@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh18:
	adrp	x9, _RADEON_GMC_CLR_CMP_CNTL_DIS@GOTPAGE
Lloh19:
	ldr	x9, [x9, _RADEON_GMC_CLR_CMP_CNTL_DIS@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	orr	w0, w8, w9
	bl	_OUT_RING
	ldr	x8, [x24]
	ldr	w8, [x8]
	cmp	w8, #1
	mov	w8, #8
	csel	x8, x28, x8, eq
	ldr	w0, [x23, x8]
	bl	_OUT_RING
	add	w22, w27, w22
	add	w21, w26, w21
	mov	x0, x25
	bl	_OUT_RING
	orr	w0, w22, w21, lsl #16
	bl	_OUT_RING
	orr	w0, w19, w20, lsl #16
	bl	_OUT_RING
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_ADVANCE_RING
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_RING_LOCALS,4,2                ; @RING_LOCALS
	.comm	_RADEON_DP_WRITE_MASK,4,2       ; @RADEON_DP_WRITE_MASK
	.comm	_RADEON_CNTL_PAINT_MULTI,4,2    ; @RADEON_CNTL_PAINT_MULTI
	.comm	_RADEON_GMC_DST_PITCH_OFFSET_CNTL,4,2 ; @RADEON_GMC_DST_PITCH_OFFSET_CNTL
	.comm	_RADEON_GMC_BRUSH_SOLID_COLOR,4,2 ; @RADEON_GMC_BRUSH_SOLID_COLOR
	.comm	_RADEON_GMC_SRC_DATATYPE_COLOR,4,2 ; @RADEON_GMC_SRC_DATATYPE_COLOR
	.comm	_RADEON_ROP3_P,4,2              ; @RADEON_ROP3_P
	.comm	_RADEON_GMC_CLR_CMP_CNTL_DIS,4,2 ; @RADEON_GMC_CLR_CMP_CNTL_DIS
	.no_dead_strip	_radeon_clear_box
.subsections_via_symbols
