	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function si_gpu_init
_si_gpu_init:                           ## @si_gpu_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movl	$-129, %eax
	addl	(%rdi), %eax
	cmpl	$2, %eax
	ja	LBB0_1
## %bb.2:
	movslq	%eax, %rsi
	leaq	l_switch.table.si_gpu_init.2(%rip), %rcx
	movl	(%rcx,%rsi,4), %edx
	shll	$2, %eax
	movl	$12, %ecx
	subl	%eax, %ecx
	leaq	l_switch.table.si_gpu_init.1(%rip), %rax
	movl	(%rax,%rsi,4), %ebx
	leaq	l_switch.table.si_gpu_init.3(%rip), %rax
	movl	(%rax,%rsi,4), %eax
	leaq	l_switch.table.si_gpu_init.4(%rip), %rdi
	movl	(%rdi,%rsi,4), %r10d
	leaq	l_switch.table.si_gpu_init.5(%rip), %rdi
	movl	(%rdi,%rsi,4), %r9d
	leaq	l_switch.table.si_gpu_init.6(%rip), %rdi
	movq	(%rdi,%rsi,8), %r8
	movl	%edx, %esi
	jmp	LBB0_3
LBB0_1:
	movq	_VERDE_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %r8
	movl	$64, %r9d
	movl	$32, %r10d
	movl	$2, %esi
	movl	$5, %ebx
	movl	$4, %ecx
	movl	$1, %edx
	movl	$4, %eax
LBB0_3:
	movl	%edx, 4(%r14)
	movl	%ecx, 8(%r14)
	movl	%ebx, 12(%r14)
	movl	%esi, 16(%r14)
	movl	%eax, 20(%r14)
	movl	%ecx, 24(%r14)
	movl	$256, 28(%r14)                  ## imm = 0x100
	movl	%r10d, 32(%r14)
	movabsq	$137438953480, %rax             ## imm = 0x2000000008
	movq	%rax, 36(%r14)
	movl	%r9d, 44(%r14)
	movabsq	$1305670058032, %rax            ## imm = 0x13000000030
	movq	%rax, 48(%r14)
	movl	(%r8), %r12d
	movl	$11284, %ebx                    ## imm = 0x2C14
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movl	%ebx, %edi
	xorl	%esi, %esi
	callq	_WREG32
	leal	4(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	leal	8(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	leal	12(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	leal	16(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	addl	$24, %ebx
	cmpl	$12052, %ebx                    ## imm = 0x2F14
	jne	LBB0_4
## %bb.5:
	movq	_GRBM_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$255, %edi
	callq	_GRBM_READ_TIMEOUT
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	%r14, %rdi
	callq	_evergreen_fix_pci_max_read_req_size
	movq	_BIF_FB_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_FB_READ_EN@GOTPCREL(%rip), %rax
	movq	_FB_WRITE_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	callq	_WREG32
	movq	_MC_SHARED_CHMAP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_MC_ARB_RAMCFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r15d
	movl	8(%r14), %eax
	movl	%eax, 56(%r14)
	movl	$256, 60(%r14)                  ## imm = 0x100
	movq	_NOOFCOLS_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r15d, %eax
	movq	_NOOFCOLS_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	addb	$8, %al
	movl	$4, %edx
	movl	$4, %esi
	movl	%eax, %ecx
	shll	%cl, %esi
	cmpl	$5119, %esi                     ## imm = 0x13FF
	jg	LBB0_7
## %bb.6:
	leal	1023(%rsi), %edx
	testl	%esi, %esi
	cmovnsl	%esi, %edx
	sarl	$10, %edx
LBB0_7:
	movl	%edx, 64(%r14)
	movabsq	$4294967328, %rax               ## imm = 0x100000020
	movq	%rax, 68(%r14)
	movl	$64, 76(%r14)
	movq	_ROW_SIZE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	xorl	%eax, %eax
	cmpl	$2, %edx
	sete	%al
	cmpl	$4, %edx
	movl	$2, %edi
	cmovnel	%eax, %edi
	callq	_ROW_SIZE
	movl	%eax, %ebx
	movl	56(%r14), %ecx
	decl	%ecx
	movl	$3, %eax
	cmpl	$3, %ecx
	ja	LBB0_9
## %bb.8:
	movslq	%ecx, %rax
	leaq	L_switch.table.si_gpu_init.7(%rip), %rcx
	movl	(%rcx,%rax,4), %eax
LBB0_9:
	movq	_NOOFBANK_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %r15d
	movq	_NOOFBANK_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %r15d
	testl	%r15d, %r15d
	je	LBB0_13
## %bb.10:
	cmpl	$1, %r15d
	jne	LBB0_12
## %bb.11:
	orl	$16, %eax
	jmp	LBB0_13
LBB0_12:
	orl	$32, %eax
LBB0_13:
	notl	%r13d
	andl	%r13d, %r12d
	orl	%r12d, %ebx
	movq	_PIPE_INTERLEAVE_SIZE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	andl	%ebx, %edx
	movq	_PIPE_INTERLEAVE_SIZE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %edx
	shll	$8, %edx
	orl	%eax, %edx
	movq	_ROW_SIZE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%ebx, %eax
	movq	_ROW_SIZE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	shll	$12, %eax
	orl	%edx, %eax
	movl	%eax, 80(%r14)
	movq	_GB_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_DMIF_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_DMIF_ADDR_CALC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_HDP_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_DMA_TILING_CONFIG@GOTPCREL(%rip), %r15
	movq	_DMA0_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	addl	(%r15), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_DMA1_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	addl	(%r15), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	%r14, %rdi
	callq	_si_tiling_mode_table_init
	movl	4(%r14), %esi
	movl	16(%r14), %edx
	movl	20(%r14), %ecx
	movq	%r14, %rdi
	callq	_si_setup_rb
	movl	16(%r14), %edx
	movl	4(%r14), %esi
	movl	12(%r14), %ecx
	movq	%r14, %rdi
	callq	_si_setup_spi
	movq	_CP_QUEUE_THRESHOLDS@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	$22, %edi
	callq	_ROQ_IB1_START
	movl	%eax, %ebx
	movl	$43, %edi
	callq	_ROQ_IB2_START
	orl	%eax, %ebx
	movl	%r15d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_CP_MEQ_THRESHOLDS@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	$48, %edi
	callq	_MEQ1_START
	movl	%eax, %ebx
	movl	$96, %edi
	callq	_MEQ2_START
	orl	%eax, %ebx
	movl	%r15d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_SX_DEBUG_1@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_SPI_CONFIG_CNTL_1@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$4, %edi
	callq	_VTX_DONE_DELAY
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_PA_SC_FIFO_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	40(%r14), %edi
	callq	_SC_FRONTEND_PRIM_FIFO_SIZE
	movl	%eax, %r12d
	movl	44(%r14), %edi
	callq	_SC_BACKEND_PRIM_FIFO_SIZE
	orl	%eax, %r12d
	movl	48(%r14), %edi
	callq	_SC_HIZ_TILE_FIFO_SIZE
	movl	%eax, %ebx
	movl	52(%r14), %edi
	callq	_SC_EARLYZ_TILE_FIFO_SIZE
	orl	%eax, %ebx
	orl	%r12d, %ebx
	movl	%r15d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_VGT_NUM_INSTANCES@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_WREG32
	movq	_CP_PERFMON_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_SQ_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_PA_SC_FORCE_EOV_MAX_CNTS@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	$4095, %edi                     ## imm = 0xFFF
	callq	_FORCE_EOV_MAX_CLK_CNT
	movl	%eax, %ebx
	movl	$255, %edi
	callq	_FORCE_EOV_MAX_REZ_CNT
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_VGT_CACHE_INVALIDATION@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_VC_AND_TC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_CACHE_INVALIDATION
	movl	%eax, %ebx
	movq	_ES_AND_GS_AUTO@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_AUTO_INVLD_EN
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_VGT_GS_VERTEX_REUSE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$16, %esi
	callq	_WREG32
	movq	_PA_SC_LINE_STIPPLE_STATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CB_PERFCOUNTER0_SELECT0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CB_PERFCOUNTER0_SELECT1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CB_PERFCOUNTER1_SELECT0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CB_PERFCOUNTER1_SELECT1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CB_PERFCOUNTER2_SELECT0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CB_PERFCOUNTER2_SELECT1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CB_PERFCOUNTER3_SELECT0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CB_PERFCOUNTER3_SELECT1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_HDP_MISC_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_HDP_FLUSH_INVALIDATE_CACHE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_HDP_HOST_PATH_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_PA_CL_ENHANCE@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_CLIP_VTX_REORDER_ENA@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$3, %edi
	callq	_NUM_CLIP_SEQ
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	$50, %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_udelay                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_TAHITI_GB_ADDR_CONFIG_GOLDEN,4,2 ## @TAHITI_GB_ADDR_CONFIG_GOLDEN
	.comm	_VERDE_GB_ADDR_CONFIG_GOLDEN,4,2 ## @VERDE_GB_ADDR_CONFIG_GOLDEN
	.comm	_GRBM_CNTL,4,2                  ## @GRBM_CNTL
	.comm	_BIF_FB_EN,4,2                  ## @BIF_FB_EN
	.comm	_FB_READ_EN,4,2                 ## @FB_READ_EN
	.comm	_FB_WRITE_EN,4,2                ## @FB_WRITE_EN
	.comm	_MC_SHARED_CHMAP,4,2            ## @MC_SHARED_CHMAP
	.comm	_MC_ARB_RAMCFG,4,2              ## @MC_ARB_RAMCFG
	.comm	_NOOFCOLS_MASK,4,2              ## @NOOFCOLS_MASK
	.comm	_NOOFCOLS_SHIFT,4,2             ## @NOOFCOLS_SHIFT
	.comm	_ROW_SIZE_MASK,4,2              ## @ROW_SIZE_MASK
	.comm	_NOOFBANK_MASK,4,2              ## @NOOFBANK_MASK
	.comm	_NOOFBANK_SHIFT,4,2             ## @NOOFBANK_SHIFT
	.comm	_PIPE_INTERLEAVE_SIZE_MASK,4,2  ## @PIPE_INTERLEAVE_SIZE_MASK
	.comm	_PIPE_INTERLEAVE_SIZE_SHIFT,4,2 ## @PIPE_INTERLEAVE_SIZE_SHIFT
	.comm	_ROW_SIZE_SHIFT,4,2             ## @ROW_SIZE_SHIFT
	.comm	_GB_ADDR_CONFIG,4,2             ## @GB_ADDR_CONFIG
	.comm	_DMIF_ADDR_CONFIG,4,2           ## @DMIF_ADDR_CONFIG
	.comm	_DMIF_ADDR_CALC,4,2             ## @DMIF_ADDR_CALC
	.comm	_HDP_ADDR_CONFIG,4,2            ## @HDP_ADDR_CONFIG
	.comm	_DMA_TILING_CONFIG,4,2          ## @DMA_TILING_CONFIG
	.comm	_DMA0_REGISTER_OFFSET,4,2       ## @DMA0_REGISTER_OFFSET
	.comm	_DMA1_REGISTER_OFFSET,4,2       ## @DMA1_REGISTER_OFFSET
	.comm	_CP_QUEUE_THRESHOLDS,4,2        ## @CP_QUEUE_THRESHOLDS
	.comm	_CP_MEQ_THRESHOLDS,4,2          ## @CP_MEQ_THRESHOLDS
	.comm	_SX_DEBUG_1,4,2                 ## @SX_DEBUG_1
	.comm	_SPI_CONFIG_CNTL_1,4,2          ## @SPI_CONFIG_CNTL_1
	.comm	_PA_SC_FIFO_SIZE,4,2            ## @PA_SC_FIFO_SIZE
	.comm	_VGT_NUM_INSTANCES,4,2          ## @VGT_NUM_INSTANCES
	.comm	_CP_PERFMON_CNTL,4,2            ## @CP_PERFMON_CNTL
	.comm	_SQ_CONFIG,4,2                  ## @SQ_CONFIG
	.comm	_PA_SC_FORCE_EOV_MAX_CNTS,4,2   ## @PA_SC_FORCE_EOV_MAX_CNTS
	.comm	_VGT_CACHE_INVALIDATION,4,2     ## @VGT_CACHE_INVALIDATION
	.comm	_VC_AND_TC,4,2                  ## @VC_AND_TC
	.comm	_ES_AND_GS_AUTO,4,2             ## @ES_AND_GS_AUTO
	.comm	_VGT_GS_VERTEX_REUSE,4,2        ## @VGT_GS_VERTEX_REUSE
	.comm	_PA_SC_LINE_STIPPLE_STATE,4,2   ## @PA_SC_LINE_STIPPLE_STATE
	.comm	_CB_PERFCOUNTER0_SELECT0,4,2    ## @CB_PERFCOUNTER0_SELECT0
	.comm	_CB_PERFCOUNTER0_SELECT1,4,2    ## @CB_PERFCOUNTER0_SELECT1
	.comm	_CB_PERFCOUNTER1_SELECT0,4,2    ## @CB_PERFCOUNTER1_SELECT0
	.comm	_CB_PERFCOUNTER1_SELECT1,4,2    ## @CB_PERFCOUNTER1_SELECT1
	.comm	_CB_PERFCOUNTER2_SELECT0,4,2    ## @CB_PERFCOUNTER2_SELECT0
	.comm	_CB_PERFCOUNTER2_SELECT1,4,2    ## @CB_PERFCOUNTER2_SELECT1
	.comm	_CB_PERFCOUNTER3_SELECT0,4,2    ## @CB_PERFCOUNTER3_SELECT0
	.comm	_CB_PERFCOUNTER3_SELECT1,4,2    ## @CB_PERFCOUNTER3_SELECT1
	.comm	_HDP_MISC_CNTL,4,2              ## @HDP_MISC_CNTL
	.comm	_HDP_FLUSH_INVALIDATE_CACHE,4,2 ## @HDP_FLUSH_INVALIDATE_CACHE
	.comm	_HDP_HOST_PATH_CNTL,4,2         ## @HDP_HOST_PATH_CNTL
	.comm	_PA_CL_ENHANCE,4,2              ## @PA_CL_ENHANCE
	.comm	_CLIP_VTX_REORDER_ENA,4,2       ## @CLIP_VTX_REORDER_ENA
	.no_dead_strip	_si_gpu_init
	.section	__TEXT,__const
	.p2align	2                               ## @switch.table.si_gpu_init.1
l_switch.table.si_gpu_init.1:
	.long	8                               ## 0x8
	.long	5                               ## 0x5
	.long	6                               ## 0x6

	.p2align	2                               ## @switch.table.si_gpu_init.2
l_switch.table.si_gpu_init.2:
	.long	2                               ## 0x2
	.long	2                               ## 0x2
	.long	1                               ## 0x1

	.p2align	2                               ## @switch.table.si_gpu_init.3
l_switch.table.si_gpu_init.3:
	.long	4                               ## 0x4
	.long	4                               ## 0x4
	.long	2                               ## 0x2

	.p2align	2                               ## @switch.table.si_gpu_init.4
l_switch.table.si_gpu_init.4:
	.long	32                              ## 0x20
	.long	32                              ## 0x20
	.long	16                              ## 0x10

	.p2align	2                               ## @switch.table.si_gpu_init.5
l_switch.table.si_gpu_init.5:
	.long	256                             ## 0x100
	.long	256                             ## 0x100
	.long	64                              ## 0x40

	.section	__DATA,__const
	.p2align	3                               ## @switch.table.si_gpu_init.6
l_switch.table.si_gpu_init.6:
	.quad	_TAHITI_GB_ADDR_CONFIG_GOLDEN
	.quad	_TAHITI_GB_ADDR_CONFIG_GOLDEN
	.quad	_VERDE_GB_ADDR_CONFIG_GOLDEN

	.section	__TEXT,__literal16,16byte_literals
	.p2align	2                               ## @switch.table.si_gpu_init.7
L_switch.table.si_gpu_init.7:
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	3                               ## 0x3
	.long	2                               ## 0x2

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3                               ; -- Begin function si_gpu_init
lCPI0_0:
	.long	8                               ; 0x8
	.long	32                              ; 0x20
lCPI0_1:
	.long	48                              ; 0x30
	.long	304                             ; 0x130
lCPI0_2:
	.long	32                              ; 0x20
	.long	1                               ; 0x1
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	2
_si_gpu_init:                           ; @si_gpu_init
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	w8, [x0]
	sub	w8, w8, #129
	cmp	w8, #2
	b.hi	LBB0_2
; %bb.1:
	sbfiz	x9, x8, #2, #32
Lloh0:
	adrp	x10, l_switch.table.si_gpu_init.2@PAGE
Lloh1:
	add	x10, x10, l_switch.table.si_gpu_init.2@PAGEOFF
	ldr	w11, [x10, x9]
	mov	w13, #12
Lloh2:
	adrp	x10, l_switch.table.si_gpu_init.1@PAGE
Lloh3:
	add	x10, x10, l_switch.table.si_gpu_init.1@PAGEOFF
	ldr	w12, [x10, x9]
Lloh4:
	adrp	x10, l_switch.table.si_gpu_init.3@PAGE
Lloh5:
	add	x10, x10, l_switch.table.si_gpu_init.3@PAGEOFF
	ldr	w14, [x10, x9]
Lloh6:
	adrp	x10, l_switch.table.si_gpu_init.4@PAGE
Lloh7:
	add	x10, x10, l_switch.table.si_gpu_init.4@PAGEOFF
	ldr	w10, [x10, x9]
Lloh8:
	adrp	x15, l_switch.table.si_gpu_init.5@PAGE
Lloh9:
	add	x15, x15, l_switch.table.si_gpu_init.5@PAGEOFF
	ldr	w9, [x15, x9]
	sub	w13, w13, w8, lsl #2
Lloh10:
	adrp	x15, l_switch.table.si_gpu_init.6@PAGE
Lloh11:
	add	x15, x15, l_switch.table.si_gpu_init.6@PAGEOFF
	ldr	x8, [x15, w8, sxtw #3]
	mov	x15, x11
	b	LBB0_3
LBB0_2:
Lloh12:
	adrp	x8, _VERDE_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh13:
	ldr	x8, [x8, _VERDE_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
	mov	w9, #64
	mov	w10, #32
	mov	w15, #2
	mov	w12, #5
	mov	w13, #4
	mov	w11, #1
	mov	w14, #4
LBB0_3:
	mov	w22, #0
	stp	w11, w13, [x19, #4]
	stp	w12, w15, [x19, #12]
	stp	w14, w13, [x19, #20]
	mov	w11, #256
	stp	w11, w10, [x19, #28]
Lloh14:
	adrp	x10, lCPI0_0@PAGE
Lloh15:
	ldr	d0, [x10, lCPI0_0@PAGEOFF]
	stur	d0, [x19, #36]
	str	w9, [x19, #44]
Lloh16:
	adrp	x9, lCPI0_1@PAGE
Lloh17:
	ldr	d0, [x9, lCPI0_1@PAGEOFF]
	mov	w23, #11292
	mov	w24, #11284
	str	d0, [x19, #48]
	mov	w25, #11288
	mov	w26, #11296
	mov	w27, #11300
	ldr	w21, [x8]
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
	add	w20, w22, w23
	add	w0, w22, w24
	mov	w1, #0
	bl	_WREG32
	add	w0, w22, w25
	mov	w1, #0
	bl	_WREG32
	mov	x0, x20
	mov	w1, #0
	bl	_WREG32
	add	w0, w22, w26
	mov	w1, #0
	bl	_WREG32
	add	w0, w22, w27
	mov	w1, #0
	bl	_WREG32
	add	w22, w22, #24
	cmp	w22, #768
	b.ne	LBB0_4
; %bb.5:
Lloh18:
	adrp	x8, _GRBM_CNTL@GOTPAGE
Lloh19:
	ldr	x8, [x8, _GRBM_CNTL@GOTPAGEOFF]
Lloh20:
	ldr	w20, [x8]
	mov	w0, #255
	bl	_GRBM_READ_TIMEOUT
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
	mov	x0, x19
	bl	_evergreen_fix_pci_max_read_req_size
Lloh21:
	adrp	x8, _BIF_FB_EN@GOTPAGE
Lloh22:
	ldr	x8, [x8, _BIF_FB_EN@GOTPAGEOFF]
Lloh23:
	adrp	x9, _FB_READ_EN@GOTPAGE
Lloh24:
	ldr	x9, [x9, _FB_READ_EN@GOTPAGEOFF]
Lloh25:
	ldr	w0, [x8]
Lloh26:
	ldr	w8, [x9]
Lloh27:
	adrp	x9, _FB_WRITE_EN@GOTPAGE
Lloh28:
	ldr	x9, [x9, _FB_WRITE_EN@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	orr	w1, w9, w8
	bl	_WREG32
Lloh30:
	adrp	x8, _MC_SHARED_CHMAP@GOTPAGE
Lloh31:
	ldr	x8, [x8, _MC_SHARED_CHMAP@GOTPAGEOFF]
Lloh32:
	ldr	w0, [x8]
	bl	_RREG32
Lloh33:
	adrp	x8, _MC_ARB_RAMCFG@GOTPAGE
Lloh34:
	ldr	x8, [x8, _MC_ARB_RAMCFG@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x20, x0
	ldr	w8, [x19, #8]
	mov	w9, #256
	stp	w8, w9, [x19, #56]
Lloh36:
	adrp	x8, _NOOFCOLS_MASK@GOTPAGE
Lloh37:
	ldr	x8, [x8, _NOOFCOLS_MASK@GOTPAGEOFF]
Lloh38:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh39:
	adrp	x9, _NOOFCOLS_SHIFT@GOTPAGE
Lloh40:
	ldr	x9, [x9, _NOOFCOLS_SHIFT@GOTPAGEOFF]
Lloh41:
	ldr	w9, [x9]
	asr	w8, w8, w9
	add	w8, w8, #8
	mov	w9, #4
	lsl	w8, w9, w8
	add	w10, w8, #1023
	cmp	w8, #0
	csel	w10, w10, w8, lt
	asr	w10, w10, #10
	mov	w11, #5119
	cmp	w8, w11
	csel	w8, w9, w10, gt
	str	w8, [x19, #64]
Lloh42:
	adrp	x9, lCPI0_2@PAGE
Lloh43:
	ldr	d0, [x9, lCPI0_2@PAGEOFF]
	stur	d0, [x19, #68]
	mov	w9, #64
	str	w9, [x19, #76]
Lloh44:
	adrp	x22, _ROW_SIZE_MASK@GOTPAGE
Lloh45:
	ldr	x22, [x22, _ROW_SIZE_MASK@GOTPAGEOFF]
	ldr	w23, [x22]
	cmp	w8, #2
	cset	w9, eq
	mov	w10, #2
	cmp	w8, #4
	csel	w0, w10, w9, eq
	bl	_ROW_SIZE
	ldr	w8, [x19, #56]
	sub	w8, w8, #1
	cmp	w8, #3
	b.hi	LBB0_7
; %bb.6:
Lloh46:
	adrp	x9, l_switch.table.si_gpu_init.7@PAGE
Lloh47:
	add	x9, x9, l_switch.table.si_gpu_init.7@PAGEOFF
	ldr	w8, [x9, w8, sxtw #2]
	b	LBB0_8
LBB0_7:
	mov	w8, #3
LBB0_8:
Lloh48:
	adrp	x9, _NOOFBANK_MASK@GOTPAGE
Lloh49:
	ldr	x9, [x9, _NOOFBANK_MASK@GOTPAGEOFF]
Lloh50:
	ldr	w9, [x9]
	and	w9, w9, w20
Lloh51:
	adrp	x10, _NOOFBANK_SHIFT@GOTPAGE
Lloh52:
	ldr	x10, [x10, _NOOFBANK_SHIFT@GOTPAGEOFF]
Lloh53:
	ldr	w10, [x10]
	asr	w9, w9, w10
	cbz	w9, LBB0_12
; %bb.9:
	cmp	w9, #1
	b.ne	LBB0_11
; %bb.10:
	orr	w8, w8, #0x10
	b	LBB0_12
LBB0_11:
	orr	w8, w8, #0x20
LBB0_12:
	bic	w9, w21, w23
	orr	w20, w0, w9
Lloh54:
	adrp	x9, _PIPE_INTERLEAVE_SIZE_MASK@GOTPAGE
Lloh55:
	ldr	x9, [x9, _PIPE_INTERLEAVE_SIZE_MASK@GOTPAGEOFF]
Lloh56:
	ldr	w9, [x9]
	and	w9, w9, w20
Lloh57:
	adrp	x10, _PIPE_INTERLEAVE_SIZE_SHIFT@GOTPAGE
Lloh58:
	ldr	x10, [x10, _PIPE_INTERLEAVE_SIZE_SHIFT@GOTPAGEOFF]
Lloh59:
	ldr	w10, [x10]
	asr	w9, w9, w10
	orr	w8, w8, w9, lsl #8
	ldr	w9, [x22]
	and	w9, w9, w20
Lloh60:
	adrp	x10, _ROW_SIZE_SHIFT@GOTPAGE
Lloh61:
	ldr	x10, [x10, _ROW_SIZE_SHIFT@GOTPAGEOFF]
Lloh62:
	ldr	w10, [x10]
	asr	w9, w9, w10
	orr	w8, w8, w9, lsl #12
	str	w8, [x19, #80]
Lloh63:
	adrp	x8, _GB_ADDR_CONFIG@GOTPAGE
Lloh64:
	ldr	x8, [x8, _GB_ADDR_CONFIG@GOTPAGEOFF]
Lloh65:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh66:
	adrp	x8, _DMIF_ADDR_CONFIG@GOTPAGE
Lloh67:
	ldr	x8, [x8, _DMIF_ADDR_CONFIG@GOTPAGEOFF]
Lloh68:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh69:
	adrp	x8, _DMIF_ADDR_CALC@GOTPAGE
Lloh70:
	ldr	x8, [x8, _DMIF_ADDR_CALC@GOTPAGEOFF]
Lloh71:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh72:
	adrp	x8, _HDP_ADDR_CONFIG@GOTPAGE
Lloh73:
	ldr	x8, [x8, _HDP_ADDR_CONFIG@GOTPAGEOFF]
Lloh74:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh75:
	adrp	x21, _DMA_TILING_CONFIG@GOTPAGE
Lloh76:
	ldr	x21, [x21, _DMA_TILING_CONFIG@GOTPAGEOFF]
	ldr	w8, [x21]
Lloh77:
	adrp	x9, _DMA0_REGISTER_OFFSET@GOTPAGE
Lloh78:
	ldr	x9, [x9, _DMA0_REGISTER_OFFSET@GOTPAGEOFF]
Lloh79:
	ldr	w9, [x9]
	add	w0, w9, w8
	mov	x1, x20
	bl	_WREG32
	ldr	w8, [x21]
Lloh80:
	adrp	x9, _DMA1_REGISTER_OFFSET@GOTPAGE
Lloh81:
	ldr	x9, [x9, _DMA1_REGISTER_OFFSET@GOTPAGEOFF]
Lloh82:
	ldr	w9, [x9]
	add	w0, w9, w8
	mov	x1, x20
	bl	_WREG32
	mov	x0, x19
	bl	_si_tiling_mode_table_init
	ldr	w1, [x19, #4]
	ldp	w2, w3, [x19, #16]
	mov	x0, x19
	bl	_si_setup_rb
	ldr	w1, [x19, #4]
	ldp	w3, w2, [x19, #12]
	mov	x0, x19
	bl	_si_setup_spi
Lloh83:
	adrp	x8, _CP_QUEUE_THRESHOLDS@GOTPAGE
Lloh84:
	ldr	x8, [x8, _CP_QUEUE_THRESHOLDS@GOTPAGEOFF]
Lloh85:
	ldr	w20, [x8]
	mov	w0, #22
	bl	_ROQ_IB1_START
	mov	x21, x0
	mov	w0, #43
	bl	_ROQ_IB2_START
	orr	w1, w0, w21
	mov	x0, x20
	bl	_WREG32
Lloh86:
	adrp	x8, _CP_MEQ_THRESHOLDS@GOTPAGE
Lloh87:
	ldr	x8, [x8, _CP_MEQ_THRESHOLDS@GOTPAGEOFF]
Lloh88:
	ldr	w20, [x8]
	mov	w0, #48
	bl	_MEQ1_START
	mov	x21, x0
	mov	w0, #96
	bl	_MEQ2_START
	orr	w1, w0, w21
	mov	x0, x20
	bl	_WREG32
Lloh89:
	adrp	x20, _SX_DEBUG_1@GOTPAGE
Lloh90:
	ldr	x20, [x20, _SX_DEBUG_1@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	mov	x1, x0
	ldr	w0, [x20]
	bl	_WREG32
Lloh91:
	adrp	x8, _SPI_CONFIG_CNTL_1@GOTPAGE
Lloh92:
	ldr	x8, [x8, _SPI_CONFIG_CNTL_1@GOTPAGEOFF]
Lloh93:
	ldr	w20, [x8]
	mov	w0, #4
	bl	_VTX_DONE_DELAY
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
Lloh94:
	adrp	x8, _PA_SC_FIFO_SIZE@GOTPAGE
Lloh95:
	ldr	x8, [x8, _PA_SC_FIFO_SIZE@GOTPAGEOFF]
Lloh96:
	ldr	w20, [x8]
	ldr	w0, [x19, #40]
	bl	_SC_FRONTEND_PRIM_FIFO_SIZE
	mov	x21, x0
	ldr	w0, [x19, #44]
	bl	_SC_BACKEND_PRIM_FIFO_SIZE
	orr	w21, w0, w21
	ldr	w0, [x19, #48]
	bl	_SC_HIZ_TILE_FIFO_SIZE
	orr	w21, w21, w0
	ldr	w0, [x19, #52]
	bl	_SC_EARLYZ_TILE_FIFO_SIZE
	orr	w1, w21, w0
	mov	x0, x20
	bl	_WREG32
Lloh97:
	adrp	x8, _VGT_NUM_INSTANCES@GOTPAGE
Lloh98:
	ldr	x8, [x8, _VGT_NUM_INSTANCES@GOTPAGEOFF]
Lloh99:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_WREG32
Lloh100:
	adrp	x8, _CP_PERFMON_CNTL@GOTPAGE
Lloh101:
	ldr	x8, [x8, _CP_PERFMON_CNTL@GOTPAGEOFF]
Lloh102:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh103:
	adrp	x8, _SQ_CONFIG@GOTPAGE
Lloh104:
	ldr	x8, [x8, _SQ_CONFIG@GOTPAGEOFF]
Lloh105:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh106:
	adrp	x8, _PA_SC_FORCE_EOV_MAX_CNTS@GOTPAGE
Lloh107:
	ldr	x8, [x8, _PA_SC_FORCE_EOV_MAX_CNTS@GOTPAGEOFF]
Lloh108:
	ldr	w19, [x8]
	mov	w0, #4095
	bl	_FORCE_EOV_MAX_CLK_CNT
	mov	x20, x0
	mov	w0, #255
	bl	_FORCE_EOV_MAX_REZ_CNT
	orr	w1, w0, w20
	mov	x0, x19
	bl	_WREG32
Lloh109:
	adrp	x8, _VGT_CACHE_INVALIDATION@GOTPAGE
Lloh110:
	ldr	x8, [x8, _VGT_CACHE_INVALIDATION@GOTPAGEOFF]
Lloh111:
	ldr	w19, [x8]
Lloh112:
	adrp	x8, _VC_AND_TC@GOTPAGE
Lloh113:
	ldr	x8, [x8, _VC_AND_TC@GOTPAGEOFF]
Lloh114:
	ldr	w0, [x8]
	bl	_CACHE_INVALIDATION
	mov	x20, x0
Lloh115:
	adrp	x8, _ES_AND_GS_AUTO@GOTPAGE
Lloh116:
	ldr	x8, [x8, _ES_AND_GS_AUTO@GOTPAGEOFF]
Lloh117:
	ldr	w0, [x8]
	bl	_AUTO_INVLD_EN
	orr	w1, w0, w20
	mov	x0, x19
	bl	_WREG32
Lloh118:
	adrp	x8, _VGT_GS_VERTEX_REUSE@GOTPAGE
Lloh119:
	ldr	x8, [x8, _VGT_GS_VERTEX_REUSE@GOTPAGEOFF]
Lloh120:
	ldr	w0, [x8]
	mov	w1, #16
	bl	_WREG32
Lloh121:
	adrp	x8, _PA_SC_LINE_STIPPLE_STATE@GOTPAGE
Lloh122:
	ldr	x8, [x8, _PA_SC_LINE_STIPPLE_STATE@GOTPAGEOFF]
Lloh123:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh124:
	adrp	x8, _CB_PERFCOUNTER0_SELECT0@GOTPAGE
Lloh125:
	ldr	x8, [x8, _CB_PERFCOUNTER0_SELECT0@GOTPAGEOFF]
Lloh126:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh127:
	adrp	x8, _CB_PERFCOUNTER0_SELECT1@GOTPAGE
Lloh128:
	ldr	x8, [x8, _CB_PERFCOUNTER0_SELECT1@GOTPAGEOFF]
Lloh129:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh130:
	adrp	x8, _CB_PERFCOUNTER1_SELECT0@GOTPAGE
Lloh131:
	ldr	x8, [x8, _CB_PERFCOUNTER1_SELECT0@GOTPAGEOFF]
Lloh132:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh133:
	adrp	x8, _CB_PERFCOUNTER1_SELECT1@GOTPAGE
Lloh134:
	ldr	x8, [x8, _CB_PERFCOUNTER1_SELECT1@GOTPAGEOFF]
Lloh135:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh136:
	adrp	x8, _CB_PERFCOUNTER2_SELECT0@GOTPAGE
Lloh137:
	ldr	x8, [x8, _CB_PERFCOUNTER2_SELECT0@GOTPAGEOFF]
Lloh138:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh139:
	adrp	x8, _CB_PERFCOUNTER2_SELECT1@GOTPAGE
Lloh140:
	ldr	x8, [x8, _CB_PERFCOUNTER2_SELECT1@GOTPAGEOFF]
Lloh141:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh142:
	adrp	x8, _CB_PERFCOUNTER3_SELECT0@GOTPAGE
Lloh143:
	ldr	x8, [x8, _CB_PERFCOUNTER3_SELECT0@GOTPAGEOFF]
Lloh144:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh145:
	adrp	x8, _CB_PERFCOUNTER3_SELECT1@GOTPAGE
Lloh146:
	ldr	x8, [x8, _CB_PERFCOUNTER3_SELECT1@GOTPAGEOFF]
Lloh147:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh148:
	adrp	x19, _HDP_MISC_CNTL@GOTPAGE
Lloh149:
	ldr	x19, [x19, _HDP_MISC_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32
Lloh150:
	adrp	x8, _HDP_FLUSH_INVALIDATE_CACHE@GOTPAGE
Lloh151:
	ldr	x8, [x8, _HDP_FLUSH_INVALIDATE_CACHE@GOTPAGEOFF]
Lloh152:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x19]
	bl	_WREG32
Lloh153:
	adrp	x19, _HDP_HOST_PATH_CNTL@GOTPAGE
Lloh154:
	ldr	x19, [x19, _HDP_HOST_PATH_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32
	mov	x1, x0
	ldr	w0, [x19]
	bl	_WREG32
Lloh155:
	adrp	x8, _PA_CL_ENHANCE@GOTPAGE
Lloh156:
	ldr	x8, [x8, _PA_CL_ENHANCE@GOTPAGEOFF]
Lloh157:
	ldr	w19, [x8]
Lloh158:
	adrp	x8, _CLIP_VTX_REORDER_ENA@GOTPAGE
Lloh159:
	ldr	x8, [x8, _CLIP_VTX_REORDER_ENA@GOTPAGEOFF]
Lloh160:
	ldr	w20, [x8]
	mov	w0, #3
	bl	_NUM_CLIP_SEQ
	orr	w1, w0, w20
	mov	x0, x19
	bl	_WREG32
	mov	w0, #50
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_udelay
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdr	Lloh16, Lloh17
	.loh AdrpLdr	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdr	Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh25
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpAdd	Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh158, Lloh159, Lloh160
	.loh AdrpLdrGotLdr	Lloh155, Lloh156, Lloh157
	.loh AdrpLdrGot	Lloh153, Lloh154
	.loh AdrpLdrGotLdr	Lloh150, Lloh151, Lloh152
	.loh AdrpLdrGot	Lloh148, Lloh149
	.loh AdrpLdrGotLdr	Lloh145, Lloh146, Lloh147
	.loh AdrpLdrGotLdr	Lloh142, Lloh143, Lloh144
	.loh AdrpLdrGotLdr	Lloh139, Lloh140, Lloh141
	.loh AdrpLdrGotLdr	Lloh136, Lloh137, Lloh138
	.loh AdrpLdrGotLdr	Lloh133, Lloh134, Lloh135
	.loh AdrpLdrGotLdr	Lloh130, Lloh131, Lloh132
	.loh AdrpLdrGotLdr	Lloh127, Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.loh AdrpLdrGotLdr	Lloh112, Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGot	Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGot	Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.cfi_endproc
                                        ; -- End function
	.comm	_TAHITI_GB_ADDR_CONFIG_GOLDEN,4,2 ; @TAHITI_GB_ADDR_CONFIG_GOLDEN
	.comm	_VERDE_GB_ADDR_CONFIG_GOLDEN,4,2 ; @VERDE_GB_ADDR_CONFIG_GOLDEN
	.comm	_GRBM_CNTL,4,2                  ; @GRBM_CNTL
	.comm	_BIF_FB_EN,4,2                  ; @BIF_FB_EN
	.comm	_FB_READ_EN,4,2                 ; @FB_READ_EN
	.comm	_FB_WRITE_EN,4,2                ; @FB_WRITE_EN
	.comm	_MC_SHARED_CHMAP,4,2            ; @MC_SHARED_CHMAP
	.comm	_MC_ARB_RAMCFG,4,2              ; @MC_ARB_RAMCFG
	.comm	_NOOFCOLS_MASK,4,2              ; @NOOFCOLS_MASK
	.comm	_NOOFCOLS_SHIFT,4,2             ; @NOOFCOLS_SHIFT
	.comm	_ROW_SIZE_MASK,4,2              ; @ROW_SIZE_MASK
	.comm	_NOOFBANK_MASK,4,2              ; @NOOFBANK_MASK
	.comm	_NOOFBANK_SHIFT,4,2             ; @NOOFBANK_SHIFT
	.comm	_PIPE_INTERLEAVE_SIZE_MASK,4,2  ; @PIPE_INTERLEAVE_SIZE_MASK
	.comm	_PIPE_INTERLEAVE_SIZE_SHIFT,4,2 ; @PIPE_INTERLEAVE_SIZE_SHIFT
	.comm	_ROW_SIZE_SHIFT,4,2             ; @ROW_SIZE_SHIFT
	.comm	_GB_ADDR_CONFIG,4,2             ; @GB_ADDR_CONFIG
	.comm	_DMIF_ADDR_CONFIG,4,2           ; @DMIF_ADDR_CONFIG
	.comm	_DMIF_ADDR_CALC,4,2             ; @DMIF_ADDR_CALC
	.comm	_HDP_ADDR_CONFIG,4,2            ; @HDP_ADDR_CONFIG
	.comm	_DMA_TILING_CONFIG,4,2          ; @DMA_TILING_CONFIG
	.comm	_DMA0_REGISTER_OFFSET,4,2       ; @DMA0_REGISTER_OFFSET
	.comm	_DMA1_REGISTER_OFFSET,4,2       ; @DMA1_REGISTER_OFFSET
	.comm	_CP_QUEUE_THRESHOLDS,4,2        ; @CP_QUEUE_THRESHOLDS
	.comm	_CP_MEQ_THRESHOLDS,4,2          ; @CP_MEQ_THRESHOLDS
	.comm	_SX_DEBUG_1,4,2                 ; @SX_DEBUG_1
	.comm	_SPI_CONFIG_CNTL_1,4,2          ; @SPI_CONFIG_CNTL_1
	.comm	_PA_SC_FIFO_SIZE,4,2            ; @PA_SC_FIFO_SIZE
	.comm	_VGT_NUM_INSTANCES,4,2          ; @VGT_NUM_INSTANCES
	.comm	_CP_PERFMON_CNTL,4,2            ; @CP_PERFMON_CNTL
	.comm	_SQ_CONFIG,4,2                  ; @SQ_CONFIG
	.comm	_PA_SC_FORCE_EOV_MAX_CNTS,4,2   ; @PA_SC_FORCE_EOV_MAX_CNTS
	.comm	_VGT_CACHE_INVALIDATION,4,2     ; @VGT_CACHE_INVALIDATION
	.comm	_VC_AND_TC,4,2                  ; @VC_AND_TC
	.comm	_ES_AND_GS_AUTO,4,2             ; @ES_AND_GS_AUTO
	.comm	_VGT_GS_VERTEX_REUSE,4,2        ; @VGT_GS_VERTEX_REUSE
	.comm	_PA_SC_LINE_STIPPLE_STATE,4,2   ; @PA_SC_LINE_STIPPLE_STATE
	.comm	_CB_PERFCOUNTER0_SELECT0,4,2    ; @CB_PERFCOUNTER0_SELECT0
	.comm	_CB_PERFCOUNTER0_SELECT1,4,2    ; @CB_PERFCOUNTER0_SELECT1
	.comm	_CB_PERFCOUNTER1_SELECT0,4,2    ; @CB_PERFCOUNTER1_SELECT0
	.comm	_CB_PERFCOUNTER1_SELECT1,4,2    ; @CB_PERFCOUNTER1_SELECT1
	.comm	_CB_PERFCOUNTER2_SELECT0,4,2    ; @CB_PERFCOUNTER2_SELECT0
	.comm	_CB_PERFCOUNTER2_SELECT1,4,2    ; @CB_PERFCOUNTER2_SELECT1
	.comm	_CB_PERFCOUNTER3_SELECT0,4,2    ; @CB_PERFCOUNTER3_SELECT0
	.comm	_CB_PERFCOUNTER3_SELECT1,4,2    ; @CB_PERFCOUNTER3_SELECT1
	.comm	_HDP_MISC_CNTL,4,2              ; @HDP_MISC_CNTL
	.comm	_HDP_FLUSH_INVALIDATE_CACHE,4,2 ; @HDP_FLUSH_INVALIDATE_CACHE
	.comm	_HDP_HOST_PATH_CNTL,4,2         ; @HDP_HOST_PATH_CNTL
	.comm	_PA_CL_ENHANCE,4,2              ; @PA_CL_ENHANCE
	.comm	_CLIP_VTX_REORDER_ENA,4,2       ; @CLIP_VTX_REORDER_ENA
	.no_dead_strip	_si_gpu_init
	.section	__TEXT,__const
	.p2align	2                               ; @switch.table.si_gpu_init.1
l_switch.table.si_gpu_init.1:
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	6                               ; 0x6

	.p2align	2                               ; @switch.table.si_gpu_init.2
l_switch.table.si_gpu_init.2:
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	1                               ; 0x1

	.p2align	2                               ; @switch.table.si_gpu_init.3
l_switch.table.si_gpu_init.3:
	.long	4                               ; 0x4
	.long	4                               ; 0x4
	.long	2                               ; 0x2

	.p2align	2                               ; @switch.table.si_gpu_init.4
l_switch.table.si_gpu_init.4:
	.long	32                              ; 0x20
	.long	32                              ; 0x20
	.long	16                              ; 0x10

	.p2align	2                               ; @switch.table.si_gpu_init.5
l_switch.table.si_gpu_init.5:
	.long	256                             ; 0x100
	.long	256                             ; 0x100
	.long	64                              ; 0x40

	.section	__DATA,__const
	.p2align	3                               ; @switch.table.si_gpu_init.6
l_switch.table.si_gpu_init.6:
	.quad	_TAHITI_GB_ADDR_CONFIG_GOLDEN
	.quad	_TAHITI_GB_ADDR_CONFIG_GOLDEN
	.quad	_VERDE_GB_ADDR_CONFIG_GOLDEN

	.section	__TEXT,__literal16,16byte_literals
	.p2align	2                               ; @switch.table.si_gpu_init.7
l_switch.table.si_gpu_init.7:
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	3                               ; 0x3
	.long	2                               ; 0x2

.subsections_via_symbols
