	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_crtc_do_set_base        ## -- Begin function radeon_crtc_do_set_base
	.p2align	4, 0x90
_radeon_crtc_do_set_base:               ## @radeon_crtc_do_set_base
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$88, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%r8d, %r14d
                                        ## kill: def $ecx killed $ecx def $rcx
	movq	%rcx, -56(%rbp)                 ## 8-byte Spill
                                        ## kill: def $edx killed $edx def $rdx
	movq	%rdx, -96(%rbp)                 ## 8-byte Spill
	movq	%rsi, %r15
	movq	%rdi, %rbx
	movq	8(%rdi), %rax
	movq	(%rax), %r13
	callq	_to_radeon_crtc
	movq	%rax, %r12
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	testl	%r14d, %r14d
	je	LBB0_1
## %bb.3:
	movq	%r12, -80(%rbp)                 ## 8-byte Spill
	movq	%rbx, -112(%rbp)                ## 8-byte Spill
	movl	%r14d, -84(%rbp)                ## 4-byte Spill
	movq	%r15, %rdi
	callq	_to_radeon_framebuffer
	movq	%r15, %r12
	jmp	LBB0_5
LBB0_1:
	movq	(%rbx), %rdi
	testq	%rdi, %rdi
	je	LBB0_2
## %bb.4:
	movq	%r12, -80(%rbp)                 ## 8-byte Spill
	movl	%r14d, -84(%rbp)                ## 4-byte Spill
	callq	_to_radeon_framebuffer
	movq	%rbx, -112(%rbp)                ## 8-byte Spill
	movq	(%rbx), %r12
LBB0_5:
	movl	(%r12), %ecx
	xorl	%r14d, %r14d
	addl	$-8, %ecx
	cmpl	$24, %ecx
	ja	LBB0_49
## %bb.6:
	movq	%r15, -120(%rbp)                ## 8-byte Spill
	movl	$512, %r15d                     ## imm = 0x200
	leaq	LJTI0_0(%rip), %rdx
	movslq	(%rdx,%rcx,4), %rcx
	addq	%rdx, %rcx
	jmpq	*%rcx
LBB0_7:
	movl	$768, %r15d                     ## imm = 0x300
	jmp	LBB0_11
LBB0_8:
	movl	$1024, %r15d                    ## imm = 0x400
	jmp	LBB0_11
LBB0_9:
	movl	$1280, %r15d                    ## imm = 0x500
	jmp	LBB0_11
LBB0_10:
	movl	$1536, %r15d                    ## imm = 0x600
LBB0_11:
	movq	(%rax), %rdi
	callq	_gem_to_radeon_bo
	movq	%rax, %rbx
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	_radeon_bo_reserve
	movl	%eax, %r14d
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	callq	_unlikely
	testq	%rax, %rax
	jne	LBB0_49
## %bb.12:
	movq	_RADEON_GEM_DOMAIN_VRAM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-44(%rbp), %rcx
	movq	%rbx, %rdi
	movl	$134217728, %edx                ## imm = 0x8000000
	callq	_radeon_bo_pin_restricted
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	callq	_unlikely
	testq	%rax, %rax
	je	LBB0_14
## %bb.13:
	movq	%rbx, %rdi
	callq	_radeon_bo_unreserve
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r14d, %r14d
	subl	(%rax), %r14d
	jmp	LBB0_49
LBB0_2:
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	jmp	LBB0_48
LBB0_14:
	leaq	-64(%rbp), %rsi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_radeon_bo_get_tiling_flags
	movq	%rbx, %rdi
	callq	_radeon_bo_unreserve
	movq	_RADEON_TILING_MICRO@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, -64(%rbp)
	je	LBB0_16
## %bb.15:
	leaq	L_.str.2(%rip), %rdi
	callq	_DRM_ERROR
LBB0_16:
	movq	%r13, %rdi
	movl	(%r13), %eax
	movq	-80(%rbp), %rcx                 ## 8-byte Reload
	movl	%eax, (%rcx)
	subl	%eax, -44(%rbp)
	movq	8(%r12), %rax
	movl	(%rax), %eax
	movl	(%r12), %ecx
	leal	7(%rcx), %esi
	testl	%ecx, %ecx
	cmovnsl	%ecx, %esi
	sarl	$3, %esi
	cltd
	idivl	%esi
	movl	%eax, %r13d
	imull	%ecx, %eax
	leal	(%rax,%rcx,8), %eax
	decl	%eax
                                        ## kill: def $ecx killed $ecx killed $rcx
	shll	$3, %ecx
	cltd
	idivl	%ecx
	movl	%eax, -60(%rbp)                 ## 4-byte Spill
	movq	_RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_RADEON_TILING_MACRO@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	andl	-64(%rbp), %ebx
	movq	%rdi, -72(%rbp)                 ## 8-byte Spill
	callq	_ASIC_IS_R300
	testl	%ebx, %ebx
	je	LBB0_20
## %bb.17:
	testq	%rax, %rax
	je	LBB0_19
## %bb.18:
	movq	_R300_CRTC_X_Y_MODE_EN@GOTPCREL(%rip), %rax
	movq	_R300_CRTC_MICRO_TILE_BUFFER_DIS@GOTPCREL(%rip), %rcx
	movq	_R300_CRTC_MACRO_TILE_EN@GOTPCREL(%rip), %rdx
	movl	%r14d, %ebx
	orl	(%rax), %ebx
	orl	(%rcx), %ebx
	orl	(%rdx), %ebx
	jmp	LBB0_23
LBB0_20:
	testq	%rax, %rax
	je	LBB0_22
## %bb.21:
	movq	_R300_CRTC_X_Y_MODE_EN@GOTPCREL(%rip), %rax
	movq	_R300_CRTC_MICRO_TILE_BUFFER_DIS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	_R300_CRTC_MACRO_TILE_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	notl	%ecx
	movl	%r14d, %ebx
	andl	%ecx, %ebx
	jmp	LBB0_23
LBB0_19:
	movq	_RADEON_CRTC_TILE_EN@GOTPCREL(%rip), %rax
	movl	%r14d, %ebx
	orl	(%rax), %ebx
	jmp	LBB0_23
LBB0_22:
	movq	_RADEON_CRTC_TILE_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	movl	%r14d, %ebx
	andl	%eax, %ebx
LBB0_23:
	movq	_RADEON_TILING_MACRO@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, -64(%rbp)
	movl	%r15d, -100(%rbp)               ## 4-byte Spill
	je	LBB0_27
## %bb.24:
	movq	-72(%rbp), %rdi                 ## 8-byte Reload
	callq	_ASIC_IS_R300
	testq	%rax, %rax
	je	LBB0_26
## %bb.25:
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	shll	$16, %eax
	orl	-96(%rbp), %eax                 ## 4-byte Folded Reload
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
	movl	$-2048, %r13d                   ## imm = 0xF800
	andl	-44(%rbp), %r13d
	jmp	LBB0_34
LBB0_27:
	movl	(%r12), %eax
	xorl	%r14d, %r14d
	addl	$-8, %eax
	cmpl	$24, %eax
	ja	LBB0_49
## %bb.28:
	imull	-56(%rbp), %r13d                ## 4-byte Folded Reload
	addl	-96(%rbp), %r13d                ## 4-byte Folded Reload
	leaq	LJTI0_1(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_29:
	addl	%r13d, %r13d
	jmp	LBB0_32
LBB0_26:
	movl	(%r12), %eax
	shrl	$4, %eax
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
	movl	%esi, %ecx
	sarl	$3, %ecx
	imull	%ecx, %r13d
	movq	-96(%rbp), %rdi                 ## 8-byte Reload
	addl	%edi, %r13d
	movb	$8, %cl
	subb	%al, %cl
	sarl	%cl, %r13d
	shll	$11, %r13d
	movl	%eax, %ecx
	shll	%cl, %edi
	leal	255(%rdi), %eax
	testl	%edi, %edi
	cmovnsl	%edi, %eax
	andl	$-256, %eax
	subl	%eax, %edi
	leal	7(%rsi), %eax
	leal	15(%rsi), %ecx
	testl	%esi, %esi
	cmovnsl	%esi, %eax
	cmovnsl	%esi, %ecx
	andl	$16777208, %eax                 ## imm = 0xFFFFF8
	movl	%esi, %edx
	subl	%eax, %edx
	shll	$8, %edx
	addl	-44(%rbp), %edx
	addl	%edi, %edx
	addl	%edx, %r13d
	andl	$-16, %ecx
	subl	%ecx, %esi
	orl	%esi, %ebx
	jmp	LBB0_33
LBB0_30:
	leal	(%r13,%r13,2), %r13d
	jmp	LBB0_32
LBB0_31:
	shll	$2, %r13d
LBB0_32:
	addl	-44(%rbp), %r13d
LBB0_33:
	xorl	%eax, %eax
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
LBB0_34:
	movq	-72(%rbp), %r15                 ## 8-byte Reload
	movq	-80(%rbp), %r12                 ## 8-byte Reload
	movl	-60(%rbp), %ecx                 ## 4-byte Reload
	movl	%ecx, %r14d
	shll	$16, %r14d
	andl	$-8, %r13d
	movl	%r13d, -44(%rbp)
	cmpl	$1, 4(%r12)
	jne	LBB0_35
## %bb.36:
	movl	%ebx, %r13d
	movq	_RADEON_CRTC2_GEN_CNTL@GOTPCREL(%rip), %rax
	jmp	LBB0_37
LBB0_35:
	movl	%ebx, %r13d
	movq	_RADEON_CRTC_GEN_CNTL@GOTPCREL(%rip), %rax
LBB0_37:
	orl	%ecx, %r14d
	movl	(%rax), %ebx
	movl	%ebx, %edi
	callq	_RREG32
	andl	$-3841, %eax                    ## imm = 0xF0FF
	movl	-100(%rbp), %ecx                ## 4-byte Reload
	orl	%eax, %ecx
	movq	_RADEON_CRTC_VSTAT_MODE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	%ecx, %esi
	movl	%ebx, %edi
	callq	_WREG32
	movl	-44(%rbp), %ebx
	movq	_RADEON_DISPLAY_BASE_ADDR@GOTPCREL(%rip), %rax
	movl	(%r12), %esi
	movl	8(%r12), %edi
	addl	(%rax), %edi
	callq	_WREG32
	movq	%r15, %rdi
	callq	_ASIC_IS_R300
	testq	%rax, %rax
	je	LBB0_42
## %bb.38:
	cmpl	$0, 4(%r12)
	jne	LBB0_39
## %bb.40:
	movq	_R300_CRTC_TILE_X0_Y0@GOTPCREL(%rip), %rax
	jmp	LBB0_41
LBB0_39:
	movq	_R300_CRTC2_TILE_X0_Y0@GOTPCREL(%rip), %rax
LBB0_41:
	movl	(%rax), %edi
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
                                        ## kill: def $esi killed $esi killed $rsi
	callq	_WREG32
LBB0_42:
	movq	_RADEON_CRTC_OFFSET_CNTL@GOTPCREL(%rip), %rax
	movl	8(%r12), %edi
	addl	(%rax), %edi
	movl	%r13d, %esi
	callq	_WREG32
	movq	_RADEON_CRTC_OFFSET@GOTPCREL(%rip), %rax
	movl	8(%r12), %edi
	addl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_RADEON_CRTC_PITCH@GOTPCREL(%rip), %rax
	movl	8(%r12), %edi
	addl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	-120(%rbp), %rdi                ## 8-byte Reload
	testq	%rdi, %rdi
	je	LBB0_47
## %bb.43:
	cmpl	$0, -84(%rbp)                   ## 4-byte Folded Reload
	jne	LBB0_47
## %bb.44:
	movq	-112(%rbp), %rax                ## 8-byte Reload
	cmpq	%rdi, (%rax)
	je	LBB0_47
## %bb.45:
	callq	_to_radeon_framebuffer
	movq	(%rax), %rdi
	callq	_gem_to_radeon_bo
	movq	%rax, %rbx
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	_radeon_bo_reserve
	movl	%eax, %r14d
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	callq	_unlikely
	testq	%rax, %rax
	jne	LBB0_49
## %bb.46:
	movq	%rbx, %rdi
	callq	_radeon_bo_unpin
	movq	%rbx, %rdi
	callq	_radeon_bo_unreserve
	movq	-72(%rbp), %r15                 ## 8-byte Reload
LBB0_47:
	movq	%r15, %rdi
	callq	_radeon_bandwidth_update
LBB0_48:
	xorl	%r14d, %r14d
LBB0_49:
	movl	%r14d, %eax
	addq	$88, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_11, LBB0_11-LJTI0_0
.set L0_0_set_49, LBB0_49-LJTI0_0
.set L0_0_set_7, LBB0_7-LJTI0_0
.set L0_0_set_8, LBB0_8-LJTI0_0
.set L0_0_set_9, LBB0_9-LJTI0_0
.set L0_0_set_10, LBB0_10-LJTI0_0
LJTI0_0:
	.long	L0_0_set_11
	.long	L0_0_set_49
	.long	L0_0_set_49
	.long	L0_0_set_49
	.long	L0_0_set_49
	.long	L0_0_set_49
	.long	L0_0_set_49
	.long	L0_0_set_7
	.long	L0_0_set_8
	.long	L0_0_set_49
	.long	L0_0_set_49
	.long	L0_0_set_49
	.long	L0_0_set_49
	.long	L0_0_set_49
	.long	L0_0_set_49
	.long	L0_0_set_49
	.long	L0_0_set_9
	.long	L0_0_set_49
	.long	L0_0_set_49
	.long	L0_0_set_49
	.long	L0_0_set_49
	.long	L0_0_set_49
	.long	L0_0_set_49
	.long	L0_0_set_49
	.long	L0_0_set_10
.set L0_1_set_32, LBB0_32-LJTI0_1
.set L0_1_set_49, LBB0_49-LJTI0_1
.set L0_1_set_29, LBB0_29-LJTI0_1
.set L0_1_set_30, LBB0_30-LJTI0_1
.set L0_1_set_31, LBB0_31-LJTI0_1
LJTI0_1:
	.long	L0_1_set_32
	.long	L0_1_set_49
	.long	L0_1_set_49
	.long	L0_1_set_49
	.long	L0_1_set_49
	.long	L0_1_set_49
	.long	L0_1_set_49
	.long	L0_1_set_29
	.long	L0_1_set_29
	.long	L0_1_set_49
	.long	L0_1_set_49
	.long	L0_1_set_49
	.long	L0_1_set_49
	.long	L0_1_set_49
	.long	L0_1_set_49
	.long	L0_1_set_49
	.long	L0_1_set_30
	.long	L0_1_set_49
	.long	L0_1_set_49
	.long	L0_1_set_49
	.long	L0_1_set_49
	.long	L0_1_set_49
	.long	L0_1_set_49
	.long	L0_1_set_49
	.long	L0_1_set_31
	.end_data_region
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"\n"

L_.str.1:                               ## @.str.1
	.asciz	"No FB bound\n"

	.comm	_RADEON_GEM_DOMAIN_VRAM,4,2     ## @RADEON_GEM_DOMAIN_VRAM
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_RADEON_TILING_MICRO,4,2        ## @RADEON_TILING_MICRO
L_.str.2:                               ## @.str.2
	.asciz	"trying to scanout microtiled buffer\n"

	.comm	_RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN,4,2 ## @RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN
	.comm	_RADEON_TILING_MACRO,4,2        ## @RADEON_TILING_MACRO
	.comm	_R300_CRTC_X_Y_MODE_EN,4,2      ## @R300_CRTC_X_Y_MODE_EN
	.comm	_R300_CRTC_MICRO_TILE_BUFFER_DIS,4,2 ## @R300_CRTC_MICRO_TILE_BUFFER_DIS
	.comm	_R300_CRTC_MACRO_TILE_EN,4,2    ## @R300_CRTC_MACRO_TILE_EN
	.comm	_RADEON_CRTC_TILE_EN,4,2        ## @RADEON_CRTC_TILE_EN
	.comm	_RADEON_CRTC2_GEN_CNTL,4,2      ## @RADEON_CRTC2_GEN_CNTL
	.comm	_RADEON_CRTC_GEN_CNTL,4,2       ## @RADEON_CRTC_GEN_CNTL
	.comm	_RADEON_CRTC_VSTAT_MODE_MASK,4,2 ## @RADEON_CRTC_VSTAT_MODE_MASK
	.comm	_RADEON_DISPLAY_BASE_ADDR,4,2   ## @RADEON_DISPLAY_BASE_ADDR
	.comm	_R300_CRTC2_TILE_X0_Y0,4,2      ## @R300_CRTC2_TILE_X0_Y0
	.comm	_R300_CRTC_TILE_X0_Y0,4,2       ## @R300_CRTC_TILE_X0_Y0
	.comm	_RADEON_CRTC_OFFSET_CNTL,4,2    ## @RADEON_CRTC_OFFSET_CNTL
	.comm	_RADEON_CRTC_OFFSET,4,2         ## @RADEON_CRTC_OFFSET
	.comm	_RADEON_CRTC_PITCH,4,2          ## @RADEON_CRTC_PITCH
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_crtc_do_set_base        ; -- Begin function radeon_crtc_do_set_base
	.p2align	2
_radeon_crtc_do_set_base:               ; @radeon_crtc_do_set_base
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #128
	.cfi_def_cfa_offset 128
	stp	x28, x27, [sp, #32]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #48]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #64]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #80]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #96]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #112]            ; 16-byte Folded Spill
	add	x29, sp, #112
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x4
	mov	x24, x3
	mov	x25, x2
	mov	x19, x1
	mov	x22, x0
	ldr	x8, [x0, #8]
	ldr	x26, [x8]
	bl	_to_radeon_crtc
	mov	x23, x0
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_KMS
	cbz	w21, LBB0_2
; %bb.1:
	mov	x0, x19
	bl	_to_radeon_framebuffer
	mov	x20, x19
	b	LBB0_4
LBB0_2:
	ldr	x0, [x22]
	cbz	x0, LBB0_13
; %bb.3:
	bl	_to_radeon_framebuffer
	ldr	x20, [x22]
LBB0_4:
	mov	w27, #0
	ldr	w8, [x20]
	sub	w8, w8, #8
	cmp	w8, #24
	b.hi	LBB0_43
; %bb.5:
	str	x26, [sp, #16]                  ; 8-byte Folded Spill
	mov	w28, #512
Lloh2:
	adrp	x9, lJTI0_0@PAGE
Lloh3:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_6
	ldrh	w11, [x9, x8, lsl #1]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_6:
	mov	w28, #768
	b	LBB0_10
LBB0_7:
	mov	w28, #1024
	b	LBB0_10
LBB0_8:
	mov	w28, #1280
	b	LBB0_10
LBB0_9:
	mov	w28, #1536
LBB0_10:
	ldr	x0, [x0]
	bl	_gem_to_radeon_bo
	mov	x26, x0
	mov	w1, #0
	bl	_radeon_bo_reserve
	mov	x27, x0
	cmp	w0, #0
	cset	w0, ne
	bl	_unlikely
	cbnz	x0, LBB0_43
; %bb.11:
Lloh4:
	adrp	x8, _RADEON_GEM_DOMAIN_VRAM@GOTPAGE
Lloh5:
	ldr	x8, [x8, _RADEON_GEM_DOMAIN_VRAM@GOTPAGEOFF]
Lloh6:
	ldr	w1, [x8]
	add	x3, sp, #28
	mov	x0, x26
	mov	w2, #134217728
	bl	_radeon_bo_pin_restricted
	cmp	w0, #0
	cset	w0, ne
	bl	_unlikely
	cbz	x0, LBB0_14
; %bb.12:
	mov	x0, x26
	bl	_radeon_bo_unreserve
Lloh7:
	adrp	x8, _EINVAL@GOTPAGE
Lloh8:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	neg	w27, w8
	b	LBB0_43
LBB0_13:
Lloh10:
	adrp	x0, l_.str.1@PAGE
Lloh11:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_DEBUG_KMS
	b	LBB0_42
LBB0_14:
	add	x1, sp, #24
	mov	x0, x26
	mov	x2, #0
	bl	_radeon_bo_get_tiling_flags
	mov	x0, x26
	bl	_radeon_bo_unreserve
	ldr	w8, [sp, #24]
Lloh12:
	adrp	x9, _RADEON_TILING_MICRO@GOTPAGE
Lloh13:
	ldr	x9, [x9, _RADEON_TILING_MICRO@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_16
; %bb.15:
Lloh15:
	adrp	x0, l_.str.2@PAGE
Lloh16:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	_DRM_ERROR
LBB0_16:
	ldr	x0, [sp, #16]                   ; 8-byte Folded Reload
	ldr	w8, [x0]
	str	w8, [x23]
	ldr	w9, [sp, #28]
	sub	w8, w9, w8
	str	w8, [sp, #28]
	ldr	x8, [x20, #8]
	ldr	w9, [x8]
	ldr	w26, [x20]
	add	w8, w26, #7
	cmp	w26, #0
	csel	w8, w8, w26, lt
	asr	w8, w8, #3
	stp	w8, w9, [sp, #8]                ; 8-byte Folded Spill
Lloh17:
	adrp	x8, _RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN@GOTPAGE
Lloh18:
	ldr	x8, [x8, _RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
	str	w8, [sp, #4]                    ; 4-byte Folded Spill
	ldr	w8, [sp, #24]
Lloh20:
	adrp	x9, _RADEON_TILING_MACRO@GOTPAGE
Lloh21:
	ldr	x9, [x9, _RADEON_TILING_MACRO@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	and	w27, w9, w8
	bl	_ASIC_IS_R300
	cbz	w27, LBB0_19
; %bb.17:
	cbz	x0, LBB0_21
; %bb.18:
Lloh23:
	adrp	x8, _R300_CRTC_X_Y_MODE_EN@GOTPAGE
Lloh24:
	ldr	x8, [x8, _R300_CRTC_X_Y_MODE_EN@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
Lloh26:
	adrp	x9, _R300_CRTC_MICRO_TILE_BUFFER_DIS@GOTPAGE
Lloh27:
	ldr	x9, [x9, _R300_CRTC_MICRO_TILE_BUFFER_DIS@GOTPAGEOFF]
Lloh28:
	ldr	w9, [x9]
Lloh29:
	adrp	x10, _R300_CRTC_MACRO_TILE_EN@GOTPAGE
Lloh30:
	ldr	x10, [x10, _R300_CRTC_MACRO_TILE_EN@GOTPAGEOFF]
Lloh31:
	ldr	w10, [x10]
	ldr	w11, [sp, #4]                   ; 4-byte Folded Reload
	orr	w8, w8, w11
	orr	w8, w8, w9
	orr	w13, w8, w10
	b	LBB0_24
LBB0_19:
	cbz	x0, LBB0_22
; %bb.20:
Lloh32:
	adrp	x8, _R300_CRTC_X_Y_MODE_EN@GOTPAGE
Lloh33:
	ldr	x8, [x8, _R300_CRTC_X_Y_MODE_EN@GOTPAGEOFF]
Lloh34:
	ldr	w8, [x8]
Lloh35:
	adrp	x9, _R300_CRTC_MICRO_TILE_BUFFER_DIS@GOTPAGE
Lloh36:
	ldr	x9, [x9, _R300_CRTC_MICRO_TILE_BUFFER_DIS@GOTPAGEOFF]
Lloh37:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh38:
	adrp	x9, _R300_CRTC_MACRO_TILE_EN@GOTPAGE
Lloh39:
	ldr	x9, [x9, _R300_CRTC_MACRO_TILE_EN@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
	orr	w8, w8, w9
	b	LBB0_23
LBB0_21:
Lloh41:
	adrp	x8, _RADEON_CRTC_TILE_EN@GOTPAGE
Lloh42:
	ldr	x8, [x8, _RADEON_CRTC_TILE_EN@GOTPAGEOFF]
Lloh43:
	ldr	w8, [x8]
	ldr	w9, [sp, #4]                    ; 4-byte Folded Reload
	orr	w13, w8, w9
	b	LBB0_24
LBB0_22:
Lloh44:
	adrp	x8, _RADEON_CRTC_TILE_EN@GOTPAGE
Lloh45:
	ldr	x8, [x8, _RADEON_CRTC_TILE_EN@GOTPAGEOFF]
Lloh46:
	ldr	w8, [x8]
LBB0_23:
	ldr	w9, [sp, #4]                    ; 4-byte Folded Reload
	bic	w13, w9, w8
LBB0_24:
	ldp	w11, w10, [sp, #8]              ; 8-byte Folded Reload
Lloh47:
	adrp	x9, _RADEON_TILING_MACRO@GOTPAGE
Lloh48:
	ldr	x9, [x9, _RADEON_TILING_MACRO@GOTPAGEOFF]
	ldr	w8, [sp, #24]
Lloh49:
	ldr	w9, [x9]
	sdiv	w14, w10, w11
	tst	w9, w8
	str	w13, [sp, #12]                  ; 4-byte Folded Spill
	b.eq	LBB0_27
; %bb.25:
	mov	x27, x14
	ldr	x0, [sp, #16]                   ; 8-byte Folded Reload
	bl	_ASIC_IS_R300
	cbz	x0, LBB0_30
; %bb.26:
	orr	w8, w25, w24, lsl #16
	str	w8, [sp, #8]                    ; 4-byte Folded Spill
	ldr	w8, [sp, #28]
	and	w8, w8, #0xfffff800
	mov	x14, x27
	b	LBB0_34
LBB0_27:
	mov	w27, #0
	ldr	w8, [x20]
	sub	w9, w8, #8
	cmp	w9, #24
	b.hi	LBB0_43
; %bb.28:
	madd	w8, w14, w24, w25
Lloh50:
	adrp	x10, lJTI0_1@PAGE
Lloh51:
	add	x10, x10, lJTI0_1@PAGEOFF
	adr	x11, LBB0_29
	ldrb	w12, [x10, x9]
	add	x11, x11, x12, lsl #2
	br	x11
LBB0_29:
	lsl	w8, w8, #1
	b	LBB0_33
LBB0_30:
	str	wzr, [sp, #8]                   ; 4-byte Folded Spill
	ldr	w8, [x20]
	asr	w8, w8, #4
	asr	w9, w24, #3
	mov	x14, x27
	madd	w9, w27, w9, w25
	mov	w10, #8
	sub	w10, w10, w8
	asr	w9, w9, w10
	lsl	w8, w25, w8
	and	w10, w8, #0xff
	negs	w8, w8
	and	w8, w8, #0xff
	csneg	w8, w10, w8, mi
	negs	w10, w24
	and	w11, w10, #0x7
	and	w12, w24, #0x7
	csneg	w11, w12, w11, mi
	ldr	w12, [sp, #28]
	add	w11, w12, w11, lsl #8
	add	w8, w11, w8
	add	w8, w8, w9, lsl #11
	and	w9, w10, #0xf
	and	w10, w24, #0xf
	csneg	w9, w10, w9, mi
	ldr	w10, [sp, #12]                  ; 4-byte Folded Reload
	orr	w10, w10, w9
	str	w10, [sp, #12]                  ; 4-byte Folded Spill
	b	LBB0_34
LBB0_31:
	add	w8, w8, w8, lsl #1
	b	LBB0_33
LBB0_32:
	lsl	w8, w8, #2
LBB0_33:
	str	wzr, [sp, #8]                   ; 4-byte Folded Spill
	ldr	w9, [sp, #28]
	add	w8, w9, w8
LBB0_34:
	lsl	w9, w26, #3
	madd	w10, w14, w26, w9
	sub	w10, w10, #1
	sdiv	w9, w10, w9
	orr	w24, w9, w9, lsl #16
	and	w8, w8, #0xfffffff8
	str	w8, [sp, #28]
Lloh52:
	adrp	x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGE
Lloh53:
	ldr	x8, [x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGEOFF]
	ldr	w9, [x23, #4]
Lloh54:
	adrp	x10, _RADEON_CRTC_GEN_CNTL@GOTPAGE
Lloh55:
	ldr	x10, [x10, _RADEON_CRTC_GEN_CNTL@GOTPAGEOFF]
	cmp	w9, #1
	csel	x8, x8, x10, eq
	ldr	w25, [x8]
	mov	x0, x25
	bl	_RREG32
	and	w8, w0, #0xfffff0ff
	orr	w8, w8, w28
Lloh56:
	adrp	x9, _RADEON_CRTC_VSTAT_MODE_MASK@GOTPAGE
Lloh57:
	ldr	x9, [x9, _RADEON_CRTC_VSTAT_MODE_MASK@GOTPAGEOFF]
Lloh58:
	ldr	w9, [x9]
	bic	w1, w8, w9
	mov	x0, x25
	bl	_WREG32
	ldr	w25, [sp, #28]
Lloh59:
	adrp	x8, _RADEON_DISPLAY_BASE_ADDR@GOTPAGE
Lloh60:
	ldr	x8, [x8, _RADEON_DISPLAY_BASE_ADDR@GOTPAGEOFF]
Lloh61:
	ldr	w8, [x8]
	ldr	w9, [x23, #8]
	add	w0, w9, w8
	ldr	w1, [x23]
	bl	_WREG32
	ldr	x20, [sp, #16]                  ; 8-byte Folded Reload
	mov	x0, x20
	bl	_ASIC_IS_R300
	cbz	x0, LBB0_36
; %bb.35:
Lloh62:
	adrp	x8, _R300_CRTC_TILE_X0_Y0@GOTPAGE
Lloh63:
	ldr	x8, [x8, _R300_CRTC_TILE_X0_Y0@GOTPAGEOFF]
	ldr	w9, [x23, #4]
Lloh64:
	adrp	x10, _R300_CRTC2_TILE_X0_Y0@GOTPAGE
Lloh65:
	ldr	x10, [x10, _R300_CRTC2_TILE_X0_Y0@GOTPAGEOFF]
	cmp	w9, #0
	csel	x8, x8, x10, eq
	ldr	w0, [x8]
	ldr	w1, [sp, #8]                    ; 4-byte Folded Reload
	bl	_WREG32
LBB0_36:
Lloh66:
	adrp	x8, _RADEON_CRTC_OFFSET_CNTL@GOTPAGE
Lloh67:
	ldr	x8, [x8, _RADEON_CRTC_OFFSET_CNTL@GOTPAGEOFF]
Lloh68:
	ldr	w8, [x8]
	ldr	w9, [x23, #8]
	add	w0, w9, w8
	ldr	w1, [sp, #12]                   ; 4-byte Folded Reload
	bl	_WREG32
Lloh69:
	adrp	x8, _RADEON_CRTC_OFFSET@GOTPAGE
Lloh70:
	ldr	x8, [x8, _RADEON_CRTC_OFFSET@GOTPAGEOFF]
Lloh71:
	ldr	w8, [x8]
	ldr	w9, [x23, #8]
	add	w0, w9, w8
	mov	x1, x25
	bl	_WREG32
Lloh72:
	adrp	x8, _RADEON_CRTC_PITCH@GOTPAGE
Lloh73:
	ldr	x8, [x8, _RADEON_CRTC_PITCH@GOTPAGEOFF]
Lloh74:
	ldr	w8, [x8]
	ldr	w9, [x23, #8]
	add	w0, w9, w8
	mov	x1, x24
	bl	_WREG32
	cbz	x19, LBB0_41
; %bb.37:
	cbnz	w21, LBB0_41
; %bb.38:
	ldr	x8, [x22]
	cmp	x8, x19
	b.eq	LBB0_41
; %bb.39:
	mov	x0, x19
	bl	_to_radeon_framebuffer
	ldr	x0, [x0]
	bl	_gem_to_radeon_bo
	mov	x20, x0
	mov	w1, #0
	bl	_radeon_bo_reserve
	mov	x27, x0
	cmp	w0, #0
	cset	w0, ne
	bl	_unlikely
	cbnz	x0, LBB0_43
; %bb.40:
	mov	x0, x20
	bl	_radeon_bo_unpin
	mov	x0, x20
	bl	_radeon_bo_unreserve
	ldr	x20, [sp, #16]                  ; 8-byte Folded Reload
LBB0_41:
	mov	x0, x20
	bl	_radeon_bandwidth_update
LBB0_42:
	mov	w27, #0
LBB0_43:
	mov	x0, x27
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpAdd	Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGot	Lloh54, Lloh55
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh64, Lloh65
	.loh AdrpLdrGot	Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.cfi_endproc
	.section	__TEXT,__const
	.p2align	1
lJTI0_0:
	.short	(LBB0_10-LBB0_6)>>2
	.short	(LBB0_43-LBB0_6)>>2
	.short	(LBB0_43-LBB0_6)>>2
	.short	(LBB0_43-LBB0_6)>>2
	.short	(LBB0_43-LBB0_6)>>2
	.short	(LBB0_43-LBB0_6)>>2
	.short	(LBB0_43-LBB0_6)>>2
	.short	(LBB0_6-LBB0_6)>>2
	.short	(LBB0_7-LBB0_6)>>2
	.short	(LBB0_43-LBB0_6)>>2
	.short	(LBB0_43-LBB0_6)>>2
	.short	(LBB0_43-LBB0_6)>>2
	.short	(LBB0_43-LBB0_6)>>2
	.short	(LBB0_43-LBB0_6)>>2
	.short	(LBB0_43-LBB0_6)>>2
	.short	(LBB0_43-LBB0_6)>>2
	.short	(LBB0_8-LBB0_6)>>2
	.short	(LBB0_43-LBB0_6)>>2
	.short	(LBB0_43-LBB0_6)>>2
	.short	(LBB0_43-LBB0_6)>>2
	.short	(LBB0_43-LBB0_6)>>2
	.short	(LBB0_43-LBB0_6)>>2
	.short	(LBB0_43-LBB0_6)>>2
	.short	(LBB0_43-LBB0_6)>>2
	.short	(LBB0_9-LBB0_6)>>2
lJTI0_1:
	.byte	(LBB0_33-LBB0_29)>>2
	.byte	(LBB0_43-LBB0_29)>>2
	.byte	(LBB0_43-LBB0_29)>>2
	.byte	(LBB0_43-LBB0_29)>>2
	.byte	(LBB0_43-LBB0_29)>>2
	.byte	(LBB0_43-LBB0_29)>>2
	.byte	(LBB0_43-LBB0_29)>>2
	.byte	(LBB0_29-LBB0_29)>>2
	.byte	(LBB0_29-LBB0_29)>>2
	.byte	(LBB0_43-LBB0_29)>>2
	.byte	(LBB0_43-LBB0_29)>>2
	.byte	(LBB0_43-LBB0_29)>>2
	.byte	(LBB0_43-LBB0_29)>>2
	.byte	(LBB0_43-LBB0_29)>>2
	.byte	(LBB0_43-LBB0_29)>>2
	.byte	(LBB0_43-LBB0_29)>>2
	.byte	(LBB0_31-LBB0_29)>>2
	.byte	(LBB0_43-LBB0_29)>>2
	.byte	(LBB0_43-LBB0_29)>>2
	.byte	(LBB0_43-LBB0_29)>>2
	.byte	(LBB0_43-LBB0_29)>>2
	.byte	(LBB0_43-LBB0_29)>>2
	.byte	(LBB0_43-LBB0_29)>>2
	.byte	(LBB0_43-LBB0_29)>>2
	.byte	(LBB0_32-LBB0_29)>>2
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"\n"

l_.str.1:                               ; @.str.1
	.asciz	"No FB bound\n"

	.comm	_RADEON_GEM_DOMAIN_VRAM,4,2     ; @RADEON_GEM_DOMAIN_VRAM
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_RADEON_TILING_MICRO,4,2        ; @RADEON_TILING_MICRO
l_.str.2:                               ; @.str.2
	.asciz	"trying to scanout microtiled buffer\n"

	.comm	_RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN,4,2 ; @RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN
	.comm	_RADEON_TILING_MACRO,4,2        ; @RADEON_TILING_MACRO
	.comm	_R300_CRTC_X_Y_MODE_EN,4,2      ; @R300_CRTC_X_Y_MODE_EN
	.comm	_R300_CRTC_MICRO_TILE_BUFFER_DIS,4,2 ; @R300_CRTC_MICRO_TILE_BUFFER_DIS
	.comm	_R300_CRTC_MACRO_TILE_EN,4,2    ; @R300_CRTC_MACRO_TILE_EN
	.comm	_RADEON_CRTC_TILE_EN,4,2        ; @RADEON_CRTC_TILE_EN
	.comm	_RADEON_CRTC2_GEN_CNTL,4,2      ; @RADEON_CRTC2_GEN_CNTL
	.comm	_RADEON_CRTC_GEN_CNTL,4,2       ; @RADEON_CRTC_GEN_CNTL
	.comm	_RADEON_CRTC_VSTAT_MODE_MASK,4,2 ; @RADEON_CRTC_VSTAT_MODE_MASK
	.comm	_RADEON_DISPLAY_BASE_ADDR,4,2   ; @RADEON_DISPLAY_BASE_ADDR
	.comm	_R300_CRTC2_TILE_X0_Y0,4,2      ; @R300_CRTC2_TILE_X0_Y0
	.comm	_R300_CRTC_TILE_X0_Y0,4,2       ; @R300_CRTC_TILE_X0_Y0
	.comm	_RADEON_CRTC_OFFSET_CNTL,4,2    ; @RADEON_CRTC_OFFSET_CNTL
	.comm	_RADEON_CRTC_OFFSET,4,2         ; @RADEON_CRTC_OFFSET
	.comm	_RADEON_CRTC_PITCH,4,2          ; @RADEON_CRTC_PITCH
.subsections_via_symbols
