	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_set_pciegart
_radeon_set_pciegart:                   ## @radeon_set_pciegart
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %rbx
	movq	_RADEON_PCIE_TX_GART_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	callq	_RADEON_READ_PCIE
	testl	%r14d, %r14d
	je	LBB0_2
## %bb.1:
	movslq	8(%rbx), %rdx
	movl	(%rbx), %esi
	movl	4(%rbx), %ecx
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG
	movq	_RADEON_PCIE_TX_DISCARD_RD_ADDR_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%rbx), %esi
	callq	_RADEON_WRITE_PCIE
	movq	_RADEON_PCIE_TX_GART_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	8(%rbx), %esi
	callq	_RADEON_WRITE_PCIE
	movq	_RADEON_PCIE_TX_GART_START_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%rbx), %esi
	callq	_RADEON_WRITE_PCIE
	movq	_RADEON_PCIE_TX_GART_END_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%rbx), %eax
	movl	4(%rbx), %ecx
	leal	(%rax,%rcx), %esi
	decl	%esi
	callq	_RADEON_WRITE_PCIE
	movq	%rbx, %rdi
	movl	$-64, %esi
	callq	_radeon_write_agp_location
	movl	(%r15), %edi
	movq	_RADEON_PCIE_TX_GART_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	jmp	LBB0_3
LBB0_2:
	movl	(%r15), %edi
	movq	_RADEON_PCIE_TX_GART_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%ecx, %eax
	movl	%eax, %esi
LBB0_3:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_RADEON_WRITE_PCIE              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_PCIE_TX_GART_CNTL,4,2   ## @RADEON_PCIE_TX_GART_CNTL
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"programming pcie %08X %08lX %08X\n"

	.comm	_RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,4,2 ## @RADEON_PCIE_TX_DISCARD_RD_ADDR_LO
	.comm	_RADEON_PCIE_TX_GART_BASE,4,2   ## @RADEON_PCIE_TX_GART_BASE
	.comm	_RADEON_PCIE_TX_GART_START_LO,4,2 ## @RADEON_PCIE_TX_GART_START_LO
	.comm	_RADEON_PCIE_TX_GART_END_LO,4,2 ## @RADEON_PCIE_TX_GART_END_LO
	.comm	_RADEON_PCIE_TX_GART_EN,4,2     ## @RADEON_PCIE_TX_GART_EN
	.no_dead_strip	_radeon_set_pciegart
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_set_pciegart
_radeon_set_pciegart:                   ; @radeon_set_pciegart
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x21, _RADEON_PCIE_TX_GART_CNTL@GOTPAGE
Lloh1:
	ldr	x21, [x21, _RADEON_PCIE_TX_GART_CNTL@GOTPAGEOFF]
	ldr	w1, [x21]
	bl	_RADEON_READ_PCIE
	cbz	w20, LBB0_2
; %bb.1:
	ldp	w3, w2, [x19, #4]
                                        ; kill: def $w2 killed $w2 def $x2
	sxtw	x2, w2
	ldr	w1, [x19]
Lloh2:
	adrp	x0, l_.str@PAGE
Lloh3:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG
Lloh4:
	adrp	x8, _RADEON_PCIE_TX_DISCARD_RD_ADDR_LO@GOTPAGE
Lloh5:
	ldr	x8, [x8, _RADEON_PCIE_TX_DISCARD_RD_ADDR_LO@GOTPAGEOFF]
Lloh6:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_RADEON_WRITE_PCIE
Lloh7:
	adrp	x8, _RADEON_PCIE_TX_GART_BASE@GOTPAGE
Lloh8:
	ldr	x8, [x8, _RADEON_PCIE_TX_GART_BASE@GOTPAGEOFF]
Lloh9:
	ldr	w0, [x8]
	ldr	w1, [x19, #8]
	bl	_RADEON_WRITE_PCIE
Lloh10:
	adrp	x8, _RADEON_PCIE_TX_GART_START_LO@GOTPAGE
Lloh11:
	ldr	x8, [x8, _RADEON_PCIE_TX_GART_START_LO@GOTPAGEOFF]
Lloh12:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_RADEON_WRITE_PCIE
Lloh13:
	adrp	x8, _RADEON_PCIE_TX_GART_END_LO@GOTPAGE
Lloh14:
	ldr	x8, [x8, _RADEON_PCIE_TX_GART_END_LO@GOTPAGEOFF]
Lloh15:
	ldr	w0, [x8]
	ldp	w8, w9, [x19]
	add	w8, w8, w9
	sub	w1, w8, #1
	bl	_RADEON_WRITE_PCIE
	mov	x0, x19
	mov	w1, #-64
	bl	_radeon_write_agp_location
	ldr	w0, [x21]
Lloh16:
	adrp	x8, _RADEON_PCIE_TX_GART_EN@GOTPAGE
Lloh17:
	ldr	x8, [x8, _RADEON_PCIE_TX_GART_EN@GOTPAGEOFF]
Lloh18:
	ldr	w1, [x8]
	b	LBB0_3
LBB0_2:
	ldr	w8, [x21]
Lloh19:
	adrp	x9, _RADEON_PCIE_TX_GART_EN@GOTPAGE
Lloh20:
	ldr	x9, [x9, _RADEON_PCIE_TX_GART_EN@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	bic	w1, w0, w9
	mov	x0, x8
LBB0_3:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_RADEON_WRITE_PCIE
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_PCIE_TX_GART_CNTL,4,2   ; @RADEON_PCIE_TX_GART_CNTL
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"programming pcie %08X %08lX %08X\n"

	.comm	_RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,4,2 ; @RADEON_PCIE_TX_DISCARD_RD_ADDR_LO
	.comm	_RADEON_PCIE_TX_GART_BASE,4,2   ; @RADEON_PCIE_TX_GART_BASE
	.comm	_RADEON_PCIE_TX_GART_START_LO,4,2 ; @RADEON_PCIE_TX_GART_START_LO
	.comm	_RADEON_PCIE_TX_GART_END_LO,4,2 ; @RADEON_PCIE_TX_GART_END_LO
	.comm	_RADEON_PCIE_TX_GART_EN,4,2     ; @RADEON_PCIE_TX_GART_EN
	.no_dead_strip	_radeon_set_pciegart
.subsections_via_symbols
