	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_cp_init_ring_buffer
_radeon_cp_init_ring_buffer:            ## @radeon_cp_init_ring_buffer
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r14
	movq	%rsi, %r12
	movq	%rdi, %r15
	cmpl	$0, 48(%rsi)
	jne	LBB0_2
## %bb.1:
	movl	(%r12), %eax
	decl	%eax
	andl	$-65536, %eax                   ## imm = 0xFFFF0000
	movswl	6(%r12), %esi
	orl	%eax, %esi
	movq	%r12, %rdi
	callq	_radeon_write_fb_location
LBB0_2:
	movq	40(%r12), %rax
	movl	(%rax), %esi
	movq	(%r15), %rax
	subl	(%rax), %esi
	addl	(%r12), %esi
	movq	_RADEON_CP_RB_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RADEON_WRITE
	movq	_RADEON_CP_RB_WPTR_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_RADEON_WRITE
	movq	_RADEON_CP_RB_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RADEON_READ
	movl	%eax, %ebx
	movq	_RADEON_CP_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_RADEON_WRITE
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_SET_RING_HEAD
	movl	%ebx, 16(%r12)
	movq	_RADEON_CP_RB_RPTR_ADDR@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movq	32(%r12), %rax
	movl	(%rax), %esi
	movq	(%r15), %rax
	subl	(%rax), %esi
	addl	(%r12), %esi
	callq	_RADEON_WRITE
	movq	_RADEON_CP_RB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	20(%r12), %eax
	movl	24(%r12), %esi
	shll	$18, %eax
	shll	$8, %esi
	orl	%eax, %esi
	orl	28(%r12), %esi
	callq	_RADEON_WRITE
	movq	_RADEON_SCRATCH_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	(%r13), %edi
	callq	_RADEON_READ
	movq	_RADEON_SCRATCH_REG_OFFSET@GOTPCREL(%rip), %rcx
	addl	(%rcx), %eax
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_RADEON_WRITE
	movq	_RADEON_SCRATCH_UMSK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$7, %esi
	callq	_RADEON_WRITE
	movq	%r12, %rdi
	callq	_radeon_enable_bm
	xorl	%edi, %edi
	callq	_RADEON_SCRATCHOFF
	movq	%r12, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_radeon_write_ring_rptr
	movq	_RADEON_LAST_FRAME_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_RADEON_WRITE
	movl	$1, %edi
	callq	_RADEON_SCRATCHOFF
	movq	%r12, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_radeon_write_ring_rptr
	movq	_RADEON_LAST_DISPATCH_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_RADEON_WRITE
	movl	$2, %edi
	callq	_RADEON_SCRATCHOFF
	movq	%r12, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_radeon_write_ring_rptr
	movq	_RADEON_LAST_CLEAR_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_RADEON_WRITE
	movq	(%r14), %rax
	movq	(%rax), %rax
	movq	(%rax), %rax
	testq	%rax, %rax
	je	LBB0_4
## %bb.3:
	xorps	%xmm0, %xmm0
	movups	%xmm0, (%rax)
	movq	$0, 16(%rax)
LBB0_4:
	movq	%r12, %rdi
	callq	_radeon_do_wait_for_idle
	movq	_RADEON_ISYNC_ANY2D_IDLE3D@GOTPCREL(%rip), %rax
	movq	_RADEON_ISYNC_ANY3D_IDLE2D@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movq	_RADEON_ISYNC_CNTL@GOTPCREL(%rip), %rax
	movq	_RADEON_ISYNC_WAIT_IDLEGUI@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movl	(%rax), %edi
	movq	_RADEON_ISYNC_CPSCRATCH_IDLEGUI@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_RADEON_WRITE                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_CP_RB_BASE,4,2          ## @RADEON_CP_RB_BASE
	.comm	_RADEON_CP_RB_WPTR_DELAY,4,2    ## @RADEON_CP_RB_WPTR_DELAY
	.comm	_RADEON_CP_RB_RPTR,4,2          ## @RADEON_CP_RB_RPTR
	.comm	_RADEON_CP_RB_WPTR,4,2          ## @RADEON_CP_RB_WPTR
	.comm	_RADEON_CP_RB_RPTR_ADDR,4,2     ## @RADEON_CP_RB_RPTR_ADDR
	.comm	_RADEON_CP_RB_CNTL,4,2          ## @RADEON_CP_RB_CNTL
	.comm	_RADEON_SCRATCH_ADDR,4,2        ## @RADEON_SCRATCH_ADDR
	.comm	_RADEON_SCRATCH_REG_OFFSET,4,2  ## @RADEON_SCRATCH_REG_OFFSET
	.comm	_RADEON_SCRATCH_UMSK,4,2        ## @RADEON_SCRATCH_UMSK
	.comm	_RADEON_LAST_FRAME_REG,4,2      ## @RADEON_LAST_FRAME_REG
	.comm	_RADEON_LAST_DISPATCH_REG,4,2   ## @RADEON_LAST_DISPATCH_REG
	.comm	_RADEON_LAST_CLEAR_REG,4,2      ## @RADEON_LAST_CLEAR_REG
	.comm	_RADEON_ISYNC_CNTL,4,2          ## @RADEON_ISYNC_CNTL
	.comm	_RADEON_ISYNC_ANY2D_IDLE3D,4,2  ## @RADEON_ISYNC_ANY2D_IDLE3D
	.comm	_RADEON_ISYNC_ANY3D_IDLE2D,4,2  ## @RADEON_ISYNC_ANY3D_IDLE2D
	.comm	_RADEON_ISYNC_WAIT_IDLEGUI,4,2  ## @RADEON_ISYNC_WAIT_IDLEGUI
	.comm	_RADEON_ISYNC_CPSCRATCH_IDLEGUI,4,2 ## @RADEON_ISYNC_CPSCRATCH_IDLEGUI
	.comm	_RADEON_BUF_SWAP_32BIT,4,2      ## @RADEON_BUF_SWAP_32BIT
	.comm	_RADEON_IS_AGP,4,2              ## @RADEON_IS_AGP
	.no_dead_strip	_radeon_cp_init_ring_buffer
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_cp_init_ring_buffer
_radeon_cp_init_ring_buffer:            ; @radeon_cp_init_ring_buffer
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x2
	mov	x19, x1
	mov	x21, x0
	ldr	w8, [x1, #48]
	cbnz	w8, LBB0_2
; %bb.1:
	ldr	w8, [x19]
	sub	w8, w8, #1
	and	w8, w8, #0xffff0000
	ldrsh	w9, [x19, #6]
	orr	w1, w8, w9
	mov	x0, x19
	bl	_radeon_write_fb_location
LBB0_2:
	ldr	x8, [x19, #40]
	ldr	w8, [x8]
	ldr	x9, [x21]
	ldr	w9, [x9]
	ldr	w10, [x19]
	sub	w8, w8, w9
	add	w1, w10, w8
Lloh0:
	adrp	x8, _RADEON_CP_RB_BASE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_CP_RB_BASE@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_RADEON_WRITE
Lloh3:
	adrp	x8, _RADEON_CP_RB_WPTR_DELAY@GOTPAGE
Lloh4:
	ldr	x8, [x8, _RADEON_CP_RB_WPTR_DELAY@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_RADEON_WRITE
Lloh6:
	adrp	x8, _RADEON_CP_RB_RPTR@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_CP_RB_RPTR@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	bl	_RADEON_READ
	mov	x22, x0
Lloh9:
	adrp	x8, _RADEON_CP_RB_WPTR@GOTPAGE
Lloh10:
	ldr	x8, [x8, _RADEON_CP_RB_WPTR@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	mov	x1, x22
	bl	_RADEON_WRITE
	mov	x0, x19
	mov	x1, x22
	bl	_SET_RING_HEAD
	str	w22, [x19, #16]
Lloh12:
	adrp	x22, _RADEON_CP_RB_RPTR_ADDR@GOTPAGE
Lloh13:
	ldr	x22, [x22, _RADEON_CP_RB_RPTR_ADDR@GOTPAGEOFF]
	ldr	w0, [x22]
	ldr	x8, [x19, #32]
	ldr	w8, [x8]
	ldr	x9, [x21]
	ldr	w9, [x9]
	ldr	w10, [x19]
	sub	w8, w8, w9
	add	w1, w10, w8
	bl	_RADEON_WRITE
Lloh14:
	adrp	x8, _RADEON_CP_RB_CNTL@GOTPAGE
Lloh15:
	ldr	x8, [x8, _RADEON_CP_RB_CNTL@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
	ldp	w8, w9, [x19, #20]
	lsl	w9, w9, #8
	orr	w8, w9, w8, lsl #18
	ldr	w9, [x19, #28]
	orr	w1, w8, w9
	bl	_RADEON_WRITE
Lloh17:
	adrp	x8, _RADEON_SCRATCH_ADDR@GOTPAGE
Lloh18:
	ldr	x8, [x8, _RADEON_SCRATCH_ADDR@GOTPAGEOFF]
Lloh19:
	ldr	w21, [x8]
	ldr	w0, [x22]
	bl	_RADEON_READ
Lloh20:
	adrp	x8, _RADEON_SCRATCH_REG_OFFSET@GOTPAGE
Lloh21:
	ldr	x8, [x8, _RADEON_SCRATCH_REG_OFFSET@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
	add	w1, w8, w0
	mov	x0, x21
	bl	_RADEON_WRITE
Lloh23:
	adrp	x8, _RADEON_SCRATCH_UMSK@GOTPAGE
Lloh24:
	ldr	x8, [x8, _RADEON_SCRATCH_UMSK@GOTPAGEOFF]
Lloh25:
	ldr	w0, [x8]
	mov	w1, #7
	bl	_RADEON_WRITE
	mov	x0, x19
	bl	_radeon_enable_bm
	mov	w0, #0
	bl	_RADEON_SCRATCHOFF
	mov	x1, x0
	mov	x0, x19
	mov	w2, #0
	bl	_radeon_write_ring_rptr
Lloh26:
	adrp	x8, _RADEON_LAST_FRAME_REG@GOTPAGE
Lloh27:
	ldr	x8, [x8, _RADEON_LAST_FRAME_REG@GOTPAGEOFF]
Lloh28:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_RADEON_WRITE
	mov	w0, #1
	bl	_RADEON_SCRATCHOFF
	mov	x1, x0
	mov	x0, x19
	mov	w2, #0
	bl	_radeon_write_ring_rptr
Lloh29:
	adrp	x8, _RADEON_LAST_DISPATCH_REG@GOTPAGE
Lloh30:
	ldr	x8, [x8, _RADEON_LAST_DISPATCH_REG@GOTPAGEOFF]
Lloh31:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_RADEON_WRITE
	mov	w0, #2
	bl	_RADEON_SCRATCHOFF
	mov	x1, x0
	mov	x0, x19
	mov	w2, #0
	bl	_radeon_write_ring_rptr
Lloh32:
	adrp	x8, _RADEON_LAST_CLEAR_REG@GOTPAGE
Lloh33:
	ldr	x8, [x8, _RADEON_LAST_CLEAR_REG@GOTPAGEOFF]
Lloh34:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_RADEON_WRITE
	ldr	x8, [x20]
	ldr	x8, [x8]
	ldr	x8, [x8]
	cbz	x8, LBB0_4
; %bb.3:
	stp	xzr, xzr, [x8]
	str	xzr, [x8, #16]
LBB0_4:
	mov	x0, x19
	bl	_radeon_do_wait_for_idle
Lloh35:
	adrp	x8, _RADEON_ISYNC_CNTL@GOTPAGE
Lloh36:
	ldr	x8, [x8, _RADEON_ISYNC_CNTL@GOTPAGEOFF]
Lloh37:
	ldr	w0, [x8]
Lloh38:
	adrp	x8, _RADEON_ISYNC_ANY2D_IDLE3D@GOTPAGE
Lloh39:
	ldr	x8, [x8, _RADEON_ISYNC_ANY2D_IDLE3D@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
Lloh41:
	adrp	x9, _RADEON_ISYNC_ANY3D_IDLE2D@GOTPAGE
Lloh42:
	ldr	x9, [x9, _RADEON_ISYNC_ANY3D_IDLE2D@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh44:
	adrp	x9, _RADEON_ISYNC_WAIT_IDLEGUI@GOTPAGE
Lloh45:
	ldr	x9, [x9, _RADEON_ISYNC_WAIT_IDLEGUI@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh47:
	adrp	x9, _RADEON_ISYNC_CPSCRATCH_IDLEGUI@GOTPAGE
Lloh48:
	ldr	x9, [x9, _RADEON_ISYNC_CPSCRATCH_IDLEGUI@GOTPAGEOFF]
Lloh49:
	ldr	w9, [x9]
	orr	w1, w8, w9
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_RADEON_WRITE
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_CP_RB_BASE,4,2          ; @RADEON_CP_RB_BASE
	.comm	_RADEON_CP_RB_WPTR_DELAY,4,2    ; @RADEON_CP_RB_WPTR_DELAY
	.comm	_RADEON_CP_RB_RPTR,4,2          ; @RADEON_CP_RB_RPTR
	.comm	_RADEON_CP_RB_WPTR,4,2          ; @RADEON_CP_RB_WPTR
	.comm	_RADEON_CP_RB_RPTR_ADDR,4,2     ; @RADEON_CP_RB_RPTR_ADDR
	.comm	_RADEON_CP_RB_CNTL,4,2          ; @RADEON_CP_RB_CNTL
	.comm	_RADEON_SCRATCH_ADDR,4,2        ; @RADEON_SCRATCH_ADDR
	.comm	_RADEON_SCRATCH_REG_OFFSET,4,2  ; @RADEON_SCRATCH_REG_OFFSET
	.comm	_RADEON_SCRATCH_UMSK,4,2        ; @RADEON_SCRATCH_UMSK
	.comm	_RADEON_LAST_FRAME_REG,4,2      ; @RADEON_LAST_FRAME_REG
	.comm	_RADEON_LAST_DISPATCH_REG,4,2   ; @RADEON_LAST_DISPATCH_REG
	.comm	_RADEON_LAST_CLEAR_REG,4,2      ; @RADEON_LAST_CLEAR_REG
	.comm	_RADEON_ISYNC_CNTL,4,2          ; @RADEON_ISYNC_CNTL
	.comm	_RADEON_ISYNC_ANY2D_IDLE3D,4,2  ; @RADEON_ISYNC_ANY2D_IDLE3D
	.comm	_RADEON_ISYNC_ANY3D_IDLE2D,4,2  ; @RADEON_ISYNC_ANY3D_IDLE2D
	.comm	_RADEON_ISYNC_WAIT_IDLEGUI,4,2  ; @RADEON_ISYNC_WAIT_IDLEGUI
	.comm	_RADEON_ISYNC_CPSCRATCH_IDLEGUI,4,2 ; @RADEON_ISYNC_CPSCRATCH_IDLEGUI
	.comm	_RADEON_BUF_SWAP_32BIT,4,2      ; @RADEON_BUF_SWAP_32BIT
	.comm	_RADEON_IS_AGP,4,2              ; @RADEON_IS_AGP
	.no_dead_strip	_radeon_cp_init_ring_buffer
.subsections_via_symbols
