	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function si_gpu_soft_reset
_si_gpu_soft_reset:                     ## @si_gpu_soft_reset
	.cfi_startproc
## %bb.0:
	testl	%esi, %esi
	je	LBB0_34
## %bb.1:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r15d
	movq	%rdi, %r14
	movl	(%rdi), %edi
	leaq	L_.str(%rip), %rsi
	movl	%r15d, %edx
	callq	_dev_info
	movq	%r14, %rdi
	callq	_evergreen_print_gpu_status_regs
	movl	(%r14), %ebx
	movq	_VM_CONTEXT1_PROTECTION_FAULT_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	leaq	L_.str.1(%rip), %rsi
	movl	%ebx, %edi
	movl	%eax, %edx
	callq	_dev_info
	movl	(%r14), %ebx
	movq	_VM_CONTEXT1_PROTECTION_FAULT_STATUS@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	leaq	L_.str.2(%rip), %rsi
	movl	%ebx, %edi
	movl	%eax, %edx
	callq	_dev_info
	movq	_CP_ME_CNTL@GOTPCREL(%rip), %rax
	movq	_CP_ME_HALT@GOTPCREL(%rip), %rcx
	movq	_CP_PFP_HALT@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	movq	(%rax), %rdi
	movq	_CP_CE_HALT@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	callq	_WREG32
	movq	_RADEON_RESET_DMA@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_3
## %bb.2:
	movq	_DMA_RB_CNTL@GOTPCREL(%rip), %r13
	movq	_DMA0_REGISTER_OFFSET@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	addq	(%r13), %rdi
	callq	_RREG32
	movq	_DMA_RB_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	(%rbx), %rdi
	addq	(%r13), %rdi
	callq	_WREG32
LBB0_3:
	movq	_RADEON_RESET_DMA1@GOTPCREL(%rip), %r12
	testl	%r15d, (%r12)
	je	LBB0_5
## %bb.4:
	movq	_DMA_RB_CNTL@GOTPCREL(%rip), %r13
	movq	_DMA1_REGISTER_OFFSET@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	addq	(%r13), %rdi
	callq	_RREG32
	movq	_DMA_RB_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	(%rbx), %rdi
	addq	(%r13), %rdi
	callq	_WREG32
LBB0_5:
	movl	$50, %edi
	callq	_udelay
	leaq	-48(%rbp), %rsi
	movq	%r14, %rdi
	callq	_evergreen_mc_stop
	movq	%r14, %rdi
	callq	_evergreen_mc_wait_for_idle
	testq	%rax, %rax
	je	LBB0_7
## %bb.6:
	movl	(%r14), %edi
	leaq	L_.str.3(%rip), %rsi
	callq	_dev_warn
LBB0_7:
	movq	_RADEON_RESET_GFX@GOTPCREL(%rip), %rax
	movq	_RADEON_RESET_COMPUTE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	_RADEON_RESET_CP@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	orl	%ecx, %edx
	testl	%r15d, %edx
	je	LBB0_8
## %bb.9:
	movq	_SOFT_RESET_CB@GOTPCREL(%rip), %rdx
	movq	_SOFT_RESET_DB@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	(%rdx), %eax
	movq	_SOFT_RESET_GDS@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_SOFT_RESET_PA@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_SOFT_RESET_SC@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_SOFT_RESET_BCI@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_SOFT_RESET_SPI@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_SOFT_RESET_SX@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_SOFT_RESET_TC@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_SOFT_RESET_TA@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_SOFT_RESET_VGT@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_SOFT_RESET_IA@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	testl	%r15d, %ecx
	je	LBB0_11
LBB0_12:
	movq	_SOFT_RESET_CP@GOTPCREL(%rip), %rcx
	movq	_SOFT_RESET_VGT@GOTPCREL(%rip), %rdx
	orl	(%rcx), %eax
	orl	(%rdx), %eax
	movq	_SOFT_RESET_GRBM@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, %edx
	jmp	LBB0_13
LBB0_8:
	xorl	%eax, %eax
	testl	%r15d, %ecx
	jne	LBB0_12
LBB0_11:
	movq	_SOFT_RESET_GRBM@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	xorl	%edx, %edx
LBB0_13:
	movq	_RADEON_RESET_DMA@GOTPCREL(%rip), %rsi
	movl	(%rsi), %r13d
	andl	%r15d, %r13d
	je	LBB0_15
## %bb.14:
	movq	_SOFT_RESET_DMA@GOTPCREL(%rip), %rsi
	movl	(%rsi), %r13d
LBB0_15:
	movl	(%r12), %esi
	andl	%r15d, %esi
	je	LBB0_17
## %bb.16:
	movq	_SOFT_RESET_DMA1@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
LBB0_17:
	movq	_RADEON_RESET_DISPLAY@GOTPCREL(%rip), %rdi
	movl	(%rdi), %edi
	andl	%r15d, %edi
	je	LBB0_19
## %bb.18:
	movq	_SOFT_RESET_DC@GOTPCREL(%rip), %rdi
	movl	(%rdi), %edi
LBB0_19:
	movq	_RADEON_RESET_RLC@GOTPCREL(%rip), %rbx
	movl	(%rbx), %r12d
	andl	%r15d, %r12d
	je	LBB0_21
## %bb.20:
	movq	_SOFT_RESET_RLC@GOTPCREL(%rip), %rbx
	movl	(%rbx), %r12d
LBB0_21:
	movq	_RADEON_RESET_SEM@GOTPCREL(%rip), %rbx
	movl	(%rbx), %ebx
	andl	%r15d, %ebx
	je	LBB0_23
## %bb.22:
	movq	_SOFT_RESET_SEM@GOTPCREL(%rip), %rbx
	movl	(%rbx), %ebx
LBB0_23:
	orl	%edx, %r13d
	orl	%edi, %esi
	movq	_RADEON_RESET_IH@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	andl	%r15d, %edx
	je	LBB0_25
## %bb.24:
	movq	_SOFT_RESET_IH@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
LBB0_25:
	orl	%edx, %ebx
	orl	%esi, %r13d
	movq	_RADEON_RESET_GRBM@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	andl	%r15d, %edx
	cmovel	%edx, %ecx
	orl	%ebx, %ecx
	movq	_RADEON_RESET_VMC@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	andl	%r15d, %edx
	je	LBB0_27
## %bb.26:
	movq	_SOFT_RESET_VMC@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
LBB0_27:
	orl	%ecx, %r13d
	movq	_RADEON_RESET_MC@GOTPCREL(%rip), %rcx
	andl	(%rcx), %r15d
	je	LBB0_29
## %bb.28:
	movq	_SOFT_RESET_MC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r15d
LBB0_29:
	orl	%r15d, %edx
	orl	%edx, %r13d
	orl	%eax, %r12d
	je	LBB0_31
## %bb.30:
	movq	_GRBM_SOFT_RESET@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	callq	_RREG32
	movl	%eax, %ebx
	orl	%r12d, %ebx
	movl	(%r14), %edi
	leaq	L_.str.4(%rip), %rsi
	movl	%ebx, %edx
	callq	_dev_info
	movq	(%r15), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	(%r15), %rdi
	callq	_RREG32
	movl	%eax, %ebx
	movl	$50, %edi
	callq	_udelay
	notl	%r12d
	andl	%ebx, %r12d
	movq	(%r15), %rdi
	movl	%r12d, %esi
	callq	_WREG32
	movq	(%r15), %rdi
	callq	_RREG32
LBB0_31:
	testl	%r13d, %r13d
	je	LBB0_33
## %bb.32:
	movq	_SRBM_SOFT_RESET@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	callq	_RREG32
	movl	%eax, %ebx
	orl	%r13d, %ebx
	movl	(%r14), %edi
	leaq	L_.str.5(%rip), %rsi
	movl	%ebx, %edx
	callq	_dev_info
	movq	(%r15), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	(%r15), %rdi
	callq	_RREG32
	movl	%eax, %ebx
	movl	$50, %edi
	callq	_udelay
	notl	%r13d
	andl	%ebx, %r13d
	movq	(%r15), %rdi
	movl	%r13d, %esi
	callq	_WREG32
	movq	(%r15), %rdi
	callq	_RREG32
LBB0_33:
	movl	$50, %edi
	callq	_udelay
	leaq	-48(%rbp), %rsi
	movq	%r14, %rdi
	callq	_evergreen_mc_resume
	movl	$50, %edi
	callq	_udelay
	movq	%r14, %rdi
	callq	_evergreen_print_gpu_status_regs
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
LBB0_34:
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"GPU softreset: 0x%08X\n"

L_.str.1:                               ## @.str.1
	.asciz	"  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n"

	.comm	_VM_CONTEXT1_PROTECTION_FAULT_ADDR,8,3 ## @VM_CONTEXT1_PROTECTION_FAULT_ADDR
L_.str.2:                               ## @.str.2
	.asciz	"  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n"

	.comm	_VM_CONTEXT1_PROTECTION_FAULT_STATUS,8,3 ## @VM_CONTEXT1_PROTECTION_FAULT_STATUS
	.comm	_CP_ME_CNTL,8,3                 ## @CP_ME_CNTL
	.comm	_CP_ME_HALT,4,2                 ## @CP_ME_HALT
	.comm	_CP_PFP_HALT,4,2                ## @CP_PFP_HALT
	.comm	_CP_CE_HALT,4,2                 ## @CP_CE_HALT
	.comm	_RADEON_RESET_DMA,4,2           ## @RADEON_RESET_DMA
	.comm	_DMA_RB_CNTL,8,3                ## @DMA_RB_CNTL
	.comm	_DMA0_REGISTER_OFFSET,8,3       ## @DMA0_REGISTER_OFFSET
	.comm	_DMA_RB_ENABLE,4,2              ## @DMA_RB_ENABLE
	.comm	_RADEON_RESET_DMA1,4,2          ## @RADEON_RESET_DMA1
	.comm	_DMA1_REGISTER_OFFSET,8,3       ## @DMA1_REGISTER_OFFSET
L_.str.3:                               ## @.str.3
	.asciz	"Wait for MC idle timedout !\n"

	.comm	_RADEON_RESET_GFX,4,2           ## @RADEON_RESET_GFX
	.comm	_RADEON_RESET_COMPUTE,4,2       ## @RADEON_RESET_COMPUTE
	.comm	_RADEON_RESET_CP,4,2            ## @RADEON_RESET_CP
	.comm	_SOFT_RESET_CB,4,2              ## @SOFT_RESET_CB
	.comm	_SOFT_RESET_DB,4,2              ## @SOFT_RESET_DB
	.comm	_SOFT_RESET_GDS,4,2             ## @SOFT_RESET_GDS
	.comm	_SOFT_RESET_PA,4,2              ## @SOFT_RESET_PA
	.comm	_SOFT_RESET_SC,4,2              ## @SOFT_RESET_SC
	.comm	_SOFT_RESET_BCI,4,2             ## @SOFT_RESET_BCI
	.comm	_SOFT_RESET_SPI,4,2             ## @SOFT_RESET_SPI
	.comm	_SOFT_RESET_SX,4,2              ## @SOFT_RESET_SX
	.comm	_SOFT_RESET_TC,4,2              ## @SOFT_RESET_TC
	.comm	_SOFT_RESET_TA,4,2              ## @SOFT_RESET_TA
	.comm	_SOFT_RESET_VGT,4,2             ## @SOFT_RESET_VGT
	.comm	_SOFT_RESET_IA,4,2              ## @SOFT_RESET_IA
	.comm	_SOFT_RESET_CP,4,2              ## @SOFT_RESET_CP
	.comm	_SOFT_RESET_GRBM,4,2            ## @SOFT_RESET_GRBM
	.comm	_SOFT_RESET_DMA,4,2             ## @SOFT_RESET_DMA
	.comm	_SOFT_RESET_DMA1,4,2            ## @SOFT_RESET_DMA1
	.comm	_RADEON_RESET_DISPLAY,4,2       ## @RADEON_RESET_DISPLAY
	.comm	_SOFT_RESET_DC,4,2              ## @SOFT_RESET_DC
	.comm	_RADEON_RESET_RLC,4,2           ## @RADEON_RESET_RLC
	.comm	_SOFT_RESET_RLC,4,2             ## @SOFT_RESET_RLC
	.comm	_RADEON_RESET_SEM,4,2           ## @RADEON_RESET_SEM
	.comm	_SOFT_RESET_SEM,4,2             ## @SOFT_RESET_SEM
	.comm	_RADEON_RESET_IH,4,2            ## @RADEON_RESET_IH
	.comm	_SOFT_RESET_IH,4,2              ## @SOFT_RESET_IH
	.comm	_RADEON_RESET_GRBM,4,2          ## @RADEON_RESET_GRBM
	.comm	_RADEON_RESET_VMC,4,2           ## @RADEON_RESET_VMC
	.comm	_SOFT_RESET_VMC,4,2             ## @SOFT_RESET_VMC
	.comm	_RADEON_RESET_MC,4,2            ## @RADEON_RESET_MC
	.comm	_SOFT_RESET_MC,4,2              ## @SOFT_RESET_MC
	.comm	_GRBM_SOFT_RESET,8,3            ## @GRBM_SOFT_RESET
L_.str.4:                               ## @.str.4
	.asciz	"GRBM_SOFT_RESET=0x%08X\n"

	.comm	_SRBM_SOFT_RESET,8,3            ## @SRBM_SOFT_RESET
L_.str.5:                               ## @.str.5
	.asciz	"SRBM_SOFT_RESET=0x%08X\n"

	.no_dead_strip	_si_gpu_soft_reset
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function si_gpu_soft_reset
_si_gpu_soft_reset:                     ; @si_gpu_soft_reset
	.cfi_startproc
; %bb.0:
	cbz	w1, LBB0_17
; %bb.1:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x1
	mov	x19, x0
	ldr	w0, [x0]
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	mov	x2, x20
	bl	_dev_info
	mov	x0, x19
	bl	_evergreen_print_gpu_status_regs
	ldr	w21, [x19]
Lloh2:
	adrp	x8, _VM_CONTEXT1_PROTECTION_FAULT_ADDR@GOTPAGE
Lloh3:
	ldr	x8, [x8, _VM_CONTEXT1_PROTECTION_FAULT_ADDR@GOTPAGEOFF]
Lloh4:
	ldr	x0, [x8]
	bl	_RREG32
	mov	x2, x0
Lloh5:
	adrp	x1, l_.str.1@PAGE
Lloh6:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x21
	bl	_dev_info
	ldr	w21, [x19]
Lloh7:
	adrp	x8, _VM_CONTEXT1_PROTECTION_FAULT_STATUS@GOTPAGE
Lloh8:
	ldr	x8, [x8, _VM_CONTEXT1_PROTECTION_FAULT_STATUS@GOTPAGEOFF]
Lloh9:
	ldr	x0, [x8]
	bl	_RREG32
	mov	x2, x0
Lloh10:
	adrp	x1, l_.str.2@PAGE
Lloh11:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x0, x21
	bl	_dev_info
Lloh12:
	adrp	x8, _CP_ME_CNTL@GOTPAGE
Lloh13:
	ldr	x8, [x8, _CP_ME_CNTL@GOTPAGEOFF]
Lloh14:
	ldr	x0, [x8]
Lloh15:
	adrp	x8, _CP_ME_HALT@GOTPAGE
Lloh16:
	ldr	x8, [x8, _CP_ME_HALT@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
Lloh18:
	adrp	x9, _CP_PFP_HALT@GOTPAGE
Lloh19:
	ldr	x9, [x9, _CP_PFP_HALT@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh21:
	adrp	x9, _CP_CE_HALT@GOTPAGE
Lloh22:
	ldr	x9, [x9, _CP_CE_HALT@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	orr	w1, w8, w9
	bl	_WREG32
Lloh24:
	adrp	x21, _RADEON_RESET_DMA@GOTPAGE
Lloh25:
	ldr	x21, [x21, _RADEON_RESET_DMA@GOTPAGEOFF]
	ldr	w8, [x21]
Lloh26:
	adrp	x23, _DMA_RB_CNTL@GOTPAGE
Lloh27:
	ldr	x23, [x23, _DMA_RB_CNTL@GOTPAGEOFF]
Lloh28:
	adrp	x24, _DMA_RB_ENABLE@GOTPAGE
Lloh29:
	ldr	x24, [x24, _DMA_RB_ENABLE@GOTPAGEOFF]
	tst	w8, w20
	b.eq	LBB0_3
; %bb.2:
	ldr	x8, [x23]
Lloh30:
	adrp	x22, _DMA0_REGISTER_OFFSET@GOTPAGE
Lloh31:
	ldr	x22, [x22, _DMA0_REGISTER_OFFSET@GOTPAGEOFF]
	ldr	x9, [x22]
	add	x0, x9, x8
	bl	_RREG32
	ldr	w8, [x24]
	bic	w1, w0, w8
	ldr	x8, [x23]
	ldr	x9, [x22]
	add	x0, x9, x8
	bl	_WREG32
LBB0_3:
Lloh32:
	adrp	x22, _RADEON_RESET_DMA1@GOTPAGE
Lloh33:
	ldr	x22, [x22, _RADEON_RESET_DMA1@GOTPAGEOFF]
	ldr	w8, [x22]
	tst	w8, w20
	b.eq	LBB0_5
; %bb.4:
	ldr	x8, [x23]
Lloh34:
	adrp	x25, _DMA1_REGISTER_OFFSET@GOTPAGE
Lloh35:
	ldr	x25, [x25, _DMA1_REGISTER_OFFSET@GOTPAGEOFF]
	ldr	x9, [x25]
	add	x0, x9, x8
	bl	_RREG32
	ldr	w8, [x24]
	bic	w1, w0, w8
	ldr	x8, [x23]
	ldr	x9, [x25]
	add	x0, x9, x8
	bl	_WREG32
LBB0_5:
	mov	w0, #50
	bl	_udelay
	add	x1, sp, #8
	mov	x0, x19
	bl	_evergreen_mc_stop
	mov	x0, x19
	bl	_evergreen_mc_wait_for_idle
	cbz	x0, LBB0_7
; %bb.6:
	ldr	w0, [x19]
Lloh36:
	adrp	x1, l_.str.3@PAGE
Lloh37:
	add	x1, x1, l_.str.3@PAGEOFF
	bl	_dev_warn
LBB0_7:
Lloh38:
	adrp	x8, _RADEON_RESET_GFX@GOTPAGE
Lloh39:
	ldr	x8, [x8, _RADEON_RESET_GFX@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
Lloh41:
	adrp	x9, _RADEON_RESET_COMPUTE@GOTPAGE
Lloh42:
	ldr	x9, [x9, _RADEON_RESET_COMPUTE@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
Lloh44:
	adrp	x10, _RADEON_RESET_CP@GOTPAGE
Lloh45:
	ldr	x10, [x10, _RADEON_RESET_CP@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh46:
	ldr	w10, [x10]
	orr	w8, w8, w10
Lloh47:
	adrp	x9, _SOFT_RESET_VGT@GOTPAGE
Lloh48:
	ldr	x9, [x9, _SOFT_RESET_VGT@GOTPAGEOFF]
	tst	w8, w20
	b.eq	LBB0_10
; %bb.8:
Lloh49:
	adrp	x8, _SOFT_RESET_CB@GOTPAGE
Lloh50:
	ldr	x8, [x8, _SOFT_RESET_CB@GOTPAGEOFF]
Lloh51:
	ldr	w8, [x8]
Lloh52:
	adrp	x11, _SOFT_RESET_DB@GOTPAGE
Lloh53:
	ldr	x11, [x11, _SOFT_RESET_DB@GOTPAGEOFF]
Lloh54:
	ldr	w11, [x11]
	orr	w8, w11, w8
Lloh55:
	adrp	x11, _SOFT_RESET_GDS@GOTPAGE
Lloh56:
	ldr	x11, [x11, _SOFT_RESET_GDS@GOTPAGEOFF]
Lloh57:
	ldr	w11, [x11]
	orr	w8, w8, w11
Lloh58:
	adrp	x11, _SOFT_RESET_PA@GOTPAGE
Lloh59:
	ldr	x11, [x11, _SOFT_RESET_PA@GOTPAGEOFF]
Lloh60:
	ldr	w11, [x11]
	orr	w8, w8, w11
Lloh61:
	adrp	x11, _SOFT_RESET_SC@GOTPAGE
Lloh62:
	ldr	x11, [x11, _SOFT_RESET_SC@GOTPAGEOFF]
Lloh63:
	ldr	w11, [x11]
	orr	w8, w8, w11
Lloh64:
	adrp	x11, _SOFT_RESET_BCI@GOTPAGE
Lloh65:
	ldr	x11, [x11, _SOFT_RESET_BCI@GOTPAGEOFF]
Lloh66:
	ldr	w11, [x11]
	orr	w8, w8, w11
Lloh67:
	adrp	x11, _SOFT_RESET_SPI@GOTPAGE
Lloh68:
	ldr	x11, [x11, _SOFT_RESET_SPI@GOTPAGEOFF]
Lloh69:
	ldr	w11, [x11]
	orr	w8, w8, w11
Lloh70:
	adrp	x11, _SOFT_RESET_SX@GOTPAGE
Lloh71:
	ldr	x11, [x11, _SOFT_RESET_SX@GOTPAGEOFF]
Lloh72:
	ldr	w11, [x11]
	orr	w8, w8, w11
Lloh73:
	adrp	x11, _SOFT_RESET_TC@GOTPAGE
Lloh74:
	ldr	x11, [x11, _SOFT_RESET_TC@GOTPAGEOFF]
Lloh75:
	ldr	w11, [x11]
	orr	w8, w8, w11
Lloh76:
	adrp	x11, _SOFT_RESET_TA@GOTPAGE
Lloh77:
	ldr	x11, [x11, _SOFT_RESET_TA@GOTPAGEOFF]
Lloh78:
	ldr	w11, [x11]
	orr	w8, w8, w11
	ldr	w11, [x9]
	orr	w8, w8, w11
Lloh79:
	adrp	x11, _SOFT_RESET_IA@GOTPAGE
Lloh80:
	ldr	x11, [x11, _SOFT_RESET_IA@GOTPAGEOFF]
Lloh81:
	ldr	w11, [x11]
	orr	w8, w8, w11
	tst	w10, w20
	b.eq	LBB0_11
LBB0_9:
Lloh82:
	adrp	x10, _SOFT_RESET_CP@GOTPAGE
Lloh83:
	ldr	x10, [x10, _SOFT_RESET_CP@GOTPAGEOFF]
Lloh84:
	ldr	w10, [x10]
	ldr	w9, [x9]
	orr	w8, w10, w8
	orr	w8, w8, w9
Lloh85:
	adrp	x9, _SOFT_RESET_GRBM@GOTPAGE
Lloh86:
	ldr	x9, [x9, _SOFT_RESET_GRBM@GOTPAGEOFF]
Lloh87:
	ldr	w9, [x9]
	mov	x10, x9
	b	LBB0_12
LBB0_10:
	mov	w8, #0
	tst	w10, w20
	b.ne	LBB0_9
LBB0_11:
	mov	w10, #0
Lloh88:
	adrp	x9, _SOFT_RESET_GRBM@GOTPAGE
Lloh89:
	ldr	x9, [x9, _SOFT_RESET_GRBM@GOTPAGEOFF]
Lloh90:
	ldr	w9, [x9]
LBB0_12:
Lloh91:
	adrp	x11, _SOFT_RESET_DMA@GOTPAGE
Lloh92:
	ldr	x11, [x11, _SOFT_RESET_DMA@GOTPAGEOFF]
	ldr	w12, [x21]
Lloh93:
	ldr	w11, [x11]
	tst	w12, w20
	csel	w11, wzr, w11, eq
	orr	w10, w11, w10
	ldr	w11, [x22]
Lloh94:
	adrp	x12, _SOFT_RESET_DMA1@GOTPAGE
Lloh95:
	ldr	x12, [x12, _SOFT_RESET_DMA1@GOTPAGEOFF]
Lloh96:
	ldr	w12, [x12]
	tst	w11, w20
	csel	w11, wzr, w12, eq
	orr	w10, w10, w11
Lloh97:
	adrp	x11, _RADEON_RESET_DISPLAY@GOTPAGE
Lloh98:
	ldr	x11, [x11, _RADEON_RESET_DISPLAY@GOTPAGEOFF]
Lloh99:
	ldr	w11, [x11]
Lloh100:
	adrp	x12, _SOFT_RESET_DC@GOTPAGE
Lloh101:
	ldr	x12, [x12, _SOFT_RESET_DC@GOTPAGEOFF]
Lloh102:
	ldr	w12, [x12]
	tst	w11, w20
	csel	w11, wzr, w12, eq
	orr	w10, w10, w11
Lloh103:
	adrp	x11, _RADEON_RESET_RLC@GOTPAGE
Lloh104:
	ldr	x11, [x11, _RADEON_RESET_RLC@GOTPAGEOFF]
Lloh105:
	ldr	w11, [x11]
Lloh106:
	adrp	x12, _SOFT_RESET_RLC@GOTPAGE
Lloh107:
	ldr	x12, [x12, _SOFT_RESET_RLC@GOTPAGEOFF]
Lloh108:
	ldr	w12, [x12]
	tst	w11, w20
Lloh109:
	adrp	x11, _RADEON_RESET_SEM@GOTPAGE
Lloh110:
	ldr	x11, [x11, _RADEON_RESET_SEM@GOTPAGEOFF]
	csel	w12, wzr, w12, eq
Lloh111:
	ldr	w11, [x11]
Lloh112:
	adrp	x13, _SOFT_RESET_SEM@GOTPAGE
Lloh113:
	ldr	x13, [x13, _SOFT_RESET_SEM@GOTPAGEOFF]
Lloh114:
	ldr	w13, [x13]
	tst	w11, w20
	csel	w11, wzr, w13, eq
	orr	w10, w10, w11
Lloh115:
	adrp	x11, _RADEON_RESET_IH@GOTPAGE
Lloh116:
	ldr	x11, [x11, _RADEON_RESET_IH@GOTPAGEOFF]
Lloh117:
	adrp	x13, _SOFT_RESET_IH@GOTPAGE
Lloh118:
	ldr	x13, [x13, _SOFT_RESET_IH@GOTPAGEOFF]
Lloh119:
	ldr	w11, [x11]
Lloh120:
	ldr	w13, [x13]
	tst	w11, w20
	csel	w11, wzr, w13, eq
Lloh121:
	adrp	x13, _RADEON_RESET_GRBM@GOTPAGE
Lloh122:
	ldr	x13, [x13, _RADEON_RESET_GRBM@GOTPAGEOFF]
	orr	w10, w10, w11
Lloh123:
	ldr	w11, [x13]
	tst	w11, w20
	csel	w9, wzr, w9, eq
Lloh124:
	adrp	x11, _RADEON_RESET_VMC@GOTPAGE
Lloh125:
	ldr	x11, [x11, _RADEON_RESET_VMC@GOTPAGEOFF]
	orr	w9, w10, w9
Lloh126:
	ldr	w10, [x11]
Lloh127:
	adrp	x11, _SOFT_RESET_VMC@GOTPAGE
Lloh128:
	ldr	x11, [x11, _SOFT_RESET_VMC@GOTPAGEOFF]
Lloh129:
	ldr	w11, [x11]
	tst	w10, w20
	csel	w10, wzr, w11, eq
	orr	w9, w9, w10
Lloh130:
	adrp	x10, _RADEON_RESET_MC@GOTPAGE
Lloh131:
	ldr	x10, [x10, _RADEON_RESET_MC@GOTPAGEOFF]
Lloh132:
	adrp	x11, _SOFT_RESET_MC@GOTPAGE
Lloh133:
	ldr	x11, [x11, _SOFT_RESET_MC@GOTPAGEOFF]
Lloh134:
	ldr	w10, [x10]
Lloh135:
	ldr	w11, [x11]
	tst	w10, w20
	csel	w10, wzr, w11, eq
	orr	w21, w9, w10
	orr	w22, w12, w8
	cbz	w22, LBB0_14
; %bb.13:
Lloh136:
	adrp	x23, _GRBM_SOFT_RESET@GOTPAGE
Lloh137:
	ldr	x23, [x23, _GRBM_SOFT_RESET@GOTPAGEOFF]
	ldr	x0, [x23]
	bl	_RREG32
	orr	w20, w0, w22
	ldr	w0, [x19]
Lloh138:
	adrp	x1, l_.str.4@PAGE
Lloh139:
	add	x1, x1, l_.str.4@PAGEOFF
	mov	x2, x20
	bl	_dev_info
	ldr	x0, [x23]
	mov	x1, x20
	bl	_WREG32
	ldr	x0, [x23]
	bl	_RREG32
	mov	x20, x0
	mov	w0, #50
	bl	_udelay
	bic	w1, w20, w22
	ldr	x0, [x23]
	bl	_WREG32
	ldr	x0, [x23]
	bl	_RREG32
LBB0_14:
	cbz	w21, LBB0_16
; %bb.15:
Lloh140:
	adrp	x22, _SRBM_SOFT_RESET@GOTPAGE
Lloh141:
	ldr	x22, [x22, _SRBM_SOFT_RESET@GOTPAGEOFF]
	ldr	x0, [x22]
	bl	_RREG32
	orr	w20, w0, w21
	ldr	w0, [x19]
Lloh142:
	adrp	x1, l_.str.5@PAGE
Lloh143:
	add	x1, x1, l_.str.5@PAGEOFF
	mov	x2, x20
	bl	_dev_info
	ldr	x0, [x22]
	mov	x1, x20
	bl	_WREG32
	ldr	x0, [x22]
	bl	_RREG32
	mov	x20, x0
	mov	w0, #50
	bl	_udelay
	bic	w1, w20, w21
	ldr	x0, [x22]
	bl	_WREG32
	ldr	x0, [x22]
	bl	_RREG32
LBB0_16:
	mov	w0, #50
	bl	_udelay
	add	x1, sp, #8
	mov	x0, x19
	bl	_evergreen_mc_resume
	mov	w0, #50
	bl	_udelay
	mov	x0, x19
	bl	_evergreen_print_gpu_status_regs
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
LBB0_17:
	.cfi_def_cfa wsp, 0
	.cfi_same_value w30
	.cfi_same_value w29
	.cfi_same_value w19
	.cfi_same_value w20
	.cfi_same_value w21
	.cfi_same_value w22
	.cfi_same_value w23
	.cfi_same_value w24
	.cfi_same_value w25
	.cfi_same_value w26
	ret
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpAdd	Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh132, Lloh133, Lloh135
	.loh AdrpLdrGotLdr	Lloh130, Lloh131, Lloh134
	.loh AdrpLdrGotLdr	Lloh127, Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh120
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh119
	.loh AdrpLdrGotLdr	Lloh112, Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpAdd	Lloh138, Lloh139
	.loh AdrpLdrGot	Lloh136, Lloh137
	.loh AdrpAdd	Lloh142, Lloh143
	.loh AdrpLdrGot	Lloh140, Lloh141
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"GPU softreset: 0x%08X\n"

l_.str.1:                               ; @.str.1
	.asciz	"  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n"

	.comm	_VM_CONTEXT1_PROTECTION_FAULT_ADDR,8,3 ; @VM_CONTEXT1_PROTECTION_FAULT_ADDR
l_.str.2:                               ; @.str.2
	.asciz	"  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n"

	.comm	_VM_CONTEXT1_PROTECTION_FAULT_STATUS,8,3 ; @VM_CONTEXT1_PROTECTION_FAULT_STATUS
	.comm	_CP_ME_CNTL,8,3                 ; @CP_ME_CNTL
	.comm	_CP_ME_HALT,4,2                 ; @CP_ME_HALT
	.comm	_CP_PFP_HALT,4,2                ; @CP_PFP_HALT
	.comm	_CP_CE_HALT,4,2                 ; @CP_CE_HALT
	.comm	_RADEON_RESET_DMA,4,2           ; @RADEON_RESET_DMA
	.comm	_DMA_RB_CNTL,8,3                ; @DMA_RB_CNTL
	.comm	_DMA0_REGISTER_OFFSET,8,3       ; @DMA0_REGISTER_OFFSET
	.comm	_DMA_RB_ENABLE,4,2              ; @DMA_RB_ENABLE
	.comm	_RADEON_RESET_DMA1,4,2          ; @RADEON_RESET_DMA1
	.comm	_DMA1_REGISTER_OFFSET,8,3       ; @DMA1_REGISTER_OFFSET
l_.str.3:                               ; @.str.3
	.asciz	"Wait for MC idle timedout !\n"

	.comm	_RADEON_RESET_GFX,4,2           ; @RADEON_RESET_GFX
	.comm	_RADEON_RESET_COMPUTE,4,2       ; @RADEON_RESET_COMPUTE
	.comm	_RADEON_RESET_CP,4,2            ; @RADEON_RESET_CP
	.comm	_SOFT_RESET_CB,4,2              ; @SOFT_RESET_CB
	.comm	_SOFT_RESET_DB,4,2              ; @SOFT_RESET_DB
	.comm	_SOFT_RESET_GDS,4,2             ; @SOFT_RESET_GDS
	.comm	_SOFT_RESET_PA,4,2              ; @SOFT_RESET_PA
	.comm	_SOFT_RESET_SC,4,2              ; @SOFT_RESET_SC
	.comm	_SOFT_RESET_BCI,4,2             ; @SOFT_RESET_BCI
	.comm	_SOFT_RESET_SPI,4,2             ; @SOFT_RESET_SPI
	.comm	_SOFT_RESET_SX,4,2              ; @SOFT_RESET_SX
	.comm	_SOFT_RESET_TC,4,2              ; @SOFT_RESET_TC
	.comm	_SOFT_RESET_TA,4,2              ; @SOFT_RESET_TA
	.comm	_SOFT_RESET_VGT,4,2             ; @SOFT_RESET_VGT
	.comm	_SOFT_RESET_IA,4,2              ; @SOFT_RESET_IA
	.comm	_SOFT_RESET_CP,4,2              ; @SOFT_RESET_CP
	.comm	_SOFT_RESET_GRBM,4,2            ; @SOFT_RESET_GRBM
	.comm	_SOFT_RESET_DMA,4,2             ; @SOFT_RESET_DMA
	.comm	_SOFT_RESET_DMA1,4,2            ; @SOFT_RESET_DMA1
	.comm	_RADEON_RESET_DISPLAY,4,2       ; @RADEON_RESET_DISPLAY
	.comm	_SOFT_RESET_DC,4,2              ; @SOFT_RESET_DC
	.comm	_RADEON_RESET_RLC,4,2           ; @RADEON_RESET_RLC
	.comm	_SOFT_RESET_RLC,4,2             ; @SOFT_RESET_RLC
	.comm	_RADEON_RESET_SEM,4,2           ; @RADEON_RESET_SEM
	.comm	_SOFT_RESET_SEM,4,2             ; @SOFT_RESET_SEM
	.comm	_RADEON_RESET_IH,4,2            ; @RADEON_RESET_IH
	.comm	_SOFT_RESET_IH,4,2              ; @SOFT_RESET_IH
	.comm	_RADEON_RESET_GRBM,4,2          ; @RADEON_RESET_GRBM
	.comm	_RADEON_RESET_VMC,4,2           ; @RADEON_RESET_VMC
	.comm	_SOFT_RESET_VMC,4,2             ; @SOFT_RESET_VMC
	.comm	_RADEON_RESET_MC,4,2            ; @RADEON_RESET_MC
	.comm	_SOFT_RESET_MC,4,2              ; @SOFT_RESET_MC
	.comm	_GRBM_SOFT_RESET,8,3            ; @GRBM_SOFT_RESET
l_.str.4:                               ; @.str.4
	.asciz	"GRBM_SOFT_RESET=0x%08X\n"

	.comm	_SRBM_SOFT_RESET,8,3            ; @SRBM_SOFT_RESET
l_.str.5:                               ; @.str.5
	.asciz	"SRBM_SOFT_RESET=0x%08X\n"

	.no_dead_strip	_si_gpu_soft_reset
.subsections_via_symbols
