	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_commit_ring             ## -- Begin function radeon_commit_ring
	.p2align	4, 0x90
_radeon_commit_ring:                    ## @radeon_commit_ring
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movl	8(%rdi), %eax
	movq	_RADEON_RING_ALIGN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r14d
	leal	-1(%r14), %ecx
	andl	%eax, %ecx
	je	LBB0_7
## %bb.1:
	subl	%ecx, %r14d
	testl	%r14d, %r14d
	jle	LBB0_2
## %bb.3:
	movq	24(%r15), %r12
	movl	%r14d, %r13d
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	xorl	%eax, %eax
	callq	_CP_PACKET2
	movslq	8(%r15), %rcx
	addq	%rbx, %rcx
	movl	%eax, (%r12,%rcx,4)
	incq	%rbx
	cmpl	%ebx, %r13d
	jne	LBB0_4
## %bb.5:
	movl	8(%r15), %eax
	movl	%r14d, %ecx
	jmp	LBB0_6
LBB0_2:
	xorl	%ecx, %ecx
LBB0_6:
	addl	%ecx, %eax
	shll	$2, %r14d
	subl	%r14d, 12(%r15)
LBB0_7:
	andl	16(%r15), %eax
	movl	%eax, 8(%r15)
	xorl	%eax, %eax
	callq	_DRM_MEMORYBARRIER
	movq	%r15, %rdi
	callq	_GET_RING_HEAD
	movq	_RADEON_FAMILY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%r15), %eax
	movq	_CHIP_R600@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	movq	_R600_CP_RB_WPTR@GOTPCREL(%rip), %rax
	cmovlq	_RADEON_CP_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	8(%r15), %esi
	movq	_R600_CP_RB_RPTR@GOTPCREL(%rip), %rbx
	cmovlq	_RADEON_CP_RB_RPTR@GOTPCREL(%rip), %rbx
	callq	_RADEON_WRITE
	movl	(%rbx), %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_RADEON_READ                    ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_RING_ALIGN,4,2          ## @RADEON_RING_ALIGN
	.comm	_RADEON_FAMILY_MASK,4,2         ## @RADEON_FAMILY_MASK
	.comm	_CHIP_R600,4,2                  ## @CHIP_R600
	.comm	_R600_CP_RB_WPTR,4,2            ## @R600_CP_RB_WPTR
	.comm	_R600_CP_RB_RPTR,4,2            ## @R600_CP_RB_RPTR
	.comm	_RADEON_CP_RB_WPTR,4,2          ## @RADEON_CP_RB_WPTR
	.comm	_RADEON_CP_RB_RPTR,4,2          ## @RADEON_CP_RB_RPTR
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_commit_ring             ; -- Begin function radeon_commit_ring
	.p2align	2
_radeon_commit_ring:                    ; @radeon_commit_ring
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	w8, [x0, #8]
Lloh0:
	adrp	x9, _RADEON_RING_ALIGN@GOTPAGE
Lloh1:
	ldr	x9, [x9, _RADEON_RING_ALIGN@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	sub	w10, w9, #1
	ands	w10, w10, w8
	b.eq	LBB0_7
; %bb.1:
	sub	w20, w9, w10
	cmp	w20, #1
	b.lt	LBB0_5
; %bb.2:
	mov	x21, #0
	ldr	x22, [x19, #24]
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	bl	_CP_PACKET2
	ldrsw	x8, [x19, #8]
	add	x8, x21, x8
	str	w0, [x22, x8, lsl #2]
	add	x21, x21, #1
	cmp	w20, w21
	b.ne	LBB0_3
; %bb.4:
	ldr	w8, [x19, #8]
	mov	x9, x20
	b	LBB0_6
LBB0_5:
	mov	w9, #0
LBB0_6:
	add	w8, w8, w9
	ldr	w9, [x19, #12]
	sub	w9, w9, w20, lsl #2
	str	w9, [x19, #12]
LBB0_7:
	ldr	w9, [x19, #16]
	and	w8, w8, w9
	str	w8, [x19, #8]
	bl	_DRM_MEMORYBARRIER
	mov	x0, x19
	bl	_GET_RING_HEAD
	ldr	w8, [x19]
Lloh3:
	adrp	x9, _RADEON_FAMILY_MASK@GOTPAGE
Lloh4:
	ldr	x9, [x9, _RADEON_FAMILY_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	and	w8, w9, w8
Lloh6:
	adrp	x9, _CHIP_R600@GOTPAGE
Lloh7:
	ldr	x9, [x9, _CHIP_R600@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
Lloh9:
	adrp	x10, _RADEON_CP_RB_WPTR@GOTPAGE
Lloh10:
	ldr	x10, [x10, _RADEON_CP_RB_WPTR@GOTPAGEOFF]
Lloh11:
	adrp	x11, _R600_CP_RB_WPTR@GOTPAGE
Lloh12:
	ldr	x11, [x11, _R600_CP_RB_WPTR@GOTPAGEOFF]
	cmp	w8, w9
	csel	x8, x10, x11, lt
	ldr	w0, [x8]
	ldr	w1, [x19, #8]
Lloh13:
	adrp	x8, _RADEON_CP_RB_RPTR@GOTPAGE
Lloh14:
	ldr	x8, [x8, _RADEON_CP_RB_RPTR@GOTPAGEOFF]
Lloh15:
	adrp	x9, _R600_CP_RB_RPTR@GOTPAGE
Lloh16:
	ldr	x9, [x9, _R600_CP_RB_RPTR@GOTPAGEOFF]
	csel	x19, x8, x9, lt
	bl	_RADEON_WRITE
	ldr	w0, [x19]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_RADEON_READ
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_RING_ALIGN,4,2          ; @RADEON_RING_ALIGN
	.comm	_RADEON_FAMILY_MASK,4,2         ; @RADEON_FAMILY_MASK
	.comm	_CHIP_R600,4,2                  ; @CHIP_R600
	.comm	_R600_CP_RB_WPTR,4,2            ; @R600_CP_RB_WPTR
	.comm	_R600_CP_RB_RPTR,4,2            ; @R600_CP_RB_RPTR
	.comm	_RADEON_CP_RB_WPTR,4,2          ; @RADEON_CP_RB_WPTR
	.comm	_RADEON_CP_RB_RPTR,4,2          ; @RADEON_CP_RB_RPTR
.subsections_via_symbols
