	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function wbcir_init_hw
_wbcir_init_hw:                         ## @wbcir_init_hw
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	_WBCIR_BANK_0@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	callq	_wbcir_select_bank
	movq	_WBCIR_IRQ_NONE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_WBCIR_REG_SP3_IER@GOTPCREL(%rip), %r14
	movq	(%r14), %rsi
	addq	8(%rbx), %rsi
	callq	_outb
	movq	_protocol@GOTPCREL(%rip), %r13
	movl	(%r13), %eax
	shll	$4, %eax
	movq	_invert@GOTPCREL(%rip), %r12
	leal	8(%rax), %edi
	cmpq	$0, (%r12)
	cmovel	%eax, %edi
	movq	_WBCIR_REG_WCEIR_CTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	48(%rbx), %rsi
	callq	_outb
	movq	_WBCIR_REG_WCEIR_STS@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	48(%rbx), %rdi
	movl	$23, %esi
	movl	$23, %edx
	callq	_wbcir_set_bits
	movq	_WBCIR_REG_WCEIR_EV_EN@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	48(%rbx), %rdi
	xorl	%esi, %esi
	movl	$7, %edx
	callq	_wbcir_set_bits
	movq	_WBCIR_REG_WCEIR_CFG1@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	48(%rbx), %rdi
	movl	$74, %esi
	movl	$127, %edx
	callq	_wbcir_set_bits
	xorl	%edi, %edi
	cmpq	$0, (%r12)
	setne	%dil
	movq	_WBCIR_REG_ECEIR_CCTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%rbx), %rsi
	shll	$2, %edi
	callq	_outb
	movq	_WBCIR_REG_ECEIR_CTS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%rbx), %rsi
	movl	$16, %edi
	callq	_outb
	movq	_WBCIR_BANK_2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_wbcir_select_bank
	movq	_WBCIR_EXT_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_WBCIR_REG_SP3_EXCR1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%rbx), %rsi
	callq	_outb
	movq	_WBCIR_REG_SP3_EXCR2@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%rbx), %rsi
	movl	$48, %edi
	callq	_outb
	movl	(%r13), %eax
	addl	$-128, %eax
	cmpl	$2, %eax
	ja	LBB0_2
## %bb.1:
	cltq
	leaq	l_switch.table.wbcir_init_hw(%rip), %rcx
	movl	(%rcx,%rax,4), %edi
	movq	_WBCIR_REG_SP3_BGDL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%rbx), %rsi
	callq	_outb
LBB0_2:
	movq	_WBCIR_REG_SP3_BGDH@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%rbx), %rsi
	xorl	%edi, %edi
	callq	_outb
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_wbcir_select_bank
	movq	_WBCIR_REG_SP3_MCR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%rbx), %rsi
	movl	$192, %edi
	callq	_outb
	movq	_WBCIR_REG_SP3_LSR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	8(%rbx), %rdi
	callq	_inb
	movq	_WBCIR_REG_SP3_MSR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	8(%rbx), %rdi
	callq	_inb
	movq	_WBCIR_BANK_7@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%rbx, %rdi
	callq	_wbcir_select_bank
	movq	_WBCIR_REG_SP3_RCCFG@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%rbx), %rsi
	movl	$16, %edi
	callq	_outb
	movq	_WBCIR_BANK_4@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_wbcir_select_bank
	movq	_WBCIR_REG_SP3_IRCR1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%rbx), %rsi
	xorl	%edi, %edi
	callq	_outb
	movq	_WBCIR_BANK_5@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_wbcir_select_bank
	movq	_WBCIR_REG_SP3_IRCR2@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%rbx), %rsi
	xorl	%edi, %edi
	callq	_outb
	movq	_WBCIR_BANK_6@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_wbcir_select_bank
	movq	_WBCIR_REG_SP3_IRCR3@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%rbx), %rsi
	movl	$32, %edi
	callq	_outb
	movl	(%r13), %esi
	movq	%rbx, %rdi
	callq	_wbcir_select_bank
	movq	_WBCIR_REG_SP3_IRRXDC@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%rbx), %rsi
	movl	$242, %edi
	callq	_outb
	movq	_WBCIR_REG_SP3_IRTXMC@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%rbx), %rsi
	movl	$105, %edi
	callq	_outb
	xorl	%edi, %edi
	cmpq	$0, (%r12)
	setne	%dil
	shll	$4, %edi
	movq	_WBCIR_REG_SP3_IRCFG4@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%rbx), %rsi
	callq	_outb
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_wbcir_select_bank
	movq	_WBCIR_REG_SP3_FCR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%rbx), %rsi
	movl	$151, %edi
	callq	_outb
	movq	_WBCIR_REG_SP3_ASCR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%rbx), %rsi
	movl	$224, %edi
	callq	_outb
	movl	$0, (%rbx)
	movl	32(%rbx), %edi
	movq	_LED_OFF@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_led_trigger_event
	movl	$0, 4(%rbx)
	movq	$0, 24(%rbx)
	movl	16(%rbx), %edi
	callq	_ir_raw_event_reset
	movl	16(%rbx), %edi
	callq	_ir_raw_event_handle
	movq	_WBCIR_IRQ_RX@GOTPCREL(%rip), %rax
	movq	_WBCIR_IRQ_ERR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	orl	(%rax), %edi
	movq	(%r14), %rsi
	addq	8(%rbx), %rsi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_outb                           ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_WBCIR_BANK_0,4,2               ## @WBCIR_BANK_0
	.comm	_WBCIR_IRQ_NONE,4,2             ## @WBCIR_IRQ_NONE
	.comm	_WBCIR_REG_SP3_IER,8,3          ## @WBCIR_REG_SP3_IER
	.comm	_protocol,4,2                   ## @protocol
	.comm	_invert,8,3                     ## @invert
	.comm	_WBCIR_REG_WCEIR_CTL,8,3        ## @WBCIR_REG_WCEIR_CTL
	.comm	_WBCIR_REG_WCEIR_STS,8,3        ## @WBCIR_REG_WCEIR_STS
	.comm	_WBCIR_REG_WCEIR_EV_EN,8,3      ## @WBCIR_REG_WCEIR_EV_EN
	.comm	_WBCIR_REG_WCEIR_CFG1,8,3       ## @WBCIR_REG_WCEIR_CFG1
	.comm	_WBCIR_REG_ECEIR_CCTL,8,3       ## @WBCIR_REG_ECEIR_CCTL
	.comm	_WBCIR_REG_ECEIR_CTS,8,3        ## @WBCIR_REG_ECEIR_CTS
	.comm	_WBCIR_BANK_2,4,2               ## @WBCIR_BANK_2
	.comm	_WBCIR_EXT_ENABLE,4,2           ## @WBCIR_EXT_ENABLE
	.comm	_WBCIR_REG_SP3_EXCR1,8,3        ## @WBCIR_REG_SP3_EXCR1
	.comm	_WBCIR_REG_SP3_EXCR2,8,3        ## @WBCIR_REG_SP3_EXCR2
	.comm	_WBCIR_REG_SP3_BGDL,8,3         ## @WBCIR_REG_SP3_BGDL
	.comm	_WBCIR_REG_SP3_BGDH,8,3         ## @WBCIR_REG_SP3_BGDH
	.comm	_WBCIR_REG_SP3_MCR,8,3          ## @WBCIR_REG_SP3_MCR
	.comm	_WBCIR_REG_SP3_LSR,8,3          ## @WBCIR_REG_SP3_LSR
	.comm	_WBCIR_REG_SP3_MSR,8,3          ## @WBCIR_REG_SP3_MSR
	.comm	_WBCIR_BANK_7,4,2               ## @WBCIR_BANK_7
	.comm	_WBCIR_REG_SP3_RCCFG,8,3        ## @WBCIR_REG_SP3_RCCFG
	.comm	_WBCIR_BANK_4,4,2               ## @WBCIR_BANK_4
	.comm	_WBCIR_REG_SP3_IRCR1,8,3        ## @WBCIR_REG_SP3_IRCR1
	.comm	_WBCIR_BANK_5,4,2               ## @WBCIR_BANK_5
	.comm	_WBCIR_REG_SP3_IRCR2,8,3        ## @WBCIR_REG_SP3_IRCR2
	.comm	_WBCIR_BANK_6,4,2               ## @WBCIR_BANK_6
	.comm	_WBCIR_REG_SP3_IRCR3,8,3        ## @WBCIR_REG_SP3_IRCR3
	.comm	_WBCIR_REG_SP3_IRRXDC,8,3       ## @WBCIR_REG_SP3_IRRXDC
	.comm	_WBCIR_REG_SP3_IRTXMC,8,3       ## @WBCIR_REG_SP3_IRTXMC
	.comm	_WBCIR_REG_SP3_IRCFG4,8,3       ## @WBCIR_REG_SP3_IRCFG4
	.comm	_WBCIR_REG_SP3_FCR,8,3          ## @WBCIR_REG_SP3_FCR
	.comm	_WBCIR_REG_SP3_ASCR,8,3         ## @WBCIR_REG_SP3_ASCR
	.comm	_LED_OFF,4,2                    ## @LED_OFF
	.comm	_WBCIR_IRQ_RX,4,2               ## @WBCIR_IRQ_RX
	.comm	_WBCIR_IRQ_ERR,4,2              ## @WBCIR_IRQ_ERR
	.no_dead_strip	_wbcir_init_hw
	.section	__TEXT,__const
	.p2align	2                               ## @switch.table.wbcir_init_hw
l_switch.table.wbcir_init_hw:
	.long	83                              ## 0x53
	.long	167                             ## 0xa7
	.long	105                             ## 0x69

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function wbcir_init_hw
_wbcir_init_hw:                         ; @wbcir_init_hw
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x21, _WBCIR_BANK_0@GOTPAGE
Lloh1:
	ldr	x21, [x21, _WBCIR_BANK_0@GOTPAGEOFF]
	ldr	w1, [x21]
	bl	_wbcir_select_bank
Lloh2:
	adrp	x8, _WBCIR_IRQ_NONE@GOTPAGE
Lloh3:
	ldr	x8, [x8, _WBCIR_IRQ_NONE@GOTPAGEOFF]
Lloh4:
	ldr	w0, [x8]
	ldr	x8, [x19, #8]
Lloh5:
	adrp	x20, _WBCIR_REG_SP3_IER@GOTPAGE
Lloh6:
	ldr	x20, [x20, _WBCIR_REG_SP3_IER@GOTPAGEOFF]
	ldr	x9, [x20]
	add	x1, x9, x8
	bl	_outb
Lloh7:
	adrp	x23, _protocol@GOTPAGE
Lloh8:
	ldr	x23, [x23, _protocol@GOTPAGEOFF]
	ldr	w8, [x23]
	lsl	w9, w8, #4
Lloh9:
	adrp	x22, _invert@GOTPAGE
Lloh10:
	ldr	x22, [x22, _invert@GOTPAGEOFF]
	ldr	x10, [x22]
	mov	w11, #8
	bfi	w11, w8, #4, #28
	cmp	x10, #0
	csel	w0, w9, w11, eq
	ldr	x8, [x19, #48]
Lloh11:
	adrp	x9, _WBCIR_REG_WCEIR_CTL@GOTPAGE
Lloh12:
	ldr	x9, [x9, _WBCIR_REG_WCEIR_CTL@GOTPAGEOFF]
Lloh13:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_outb
	ldr	x8, [x19, #48]
Lloh14:
	adrp	x9, _WBCIR_REG_WCEIR_STS@GOTPAGE
Lloh15:
	ldr	x9, [x9, _WBCIR_REG_WCEIR_STS@GOTPAGEOFF]
Lloh16:
	ldr	x9, [x9]
	add	x0, x9, x8
	mov	w1, #23
	mov	w2, #23
	bl	_wbcir_set_bits
	ldr	x8, [x19, #48]
Lloh17:
	adrp	x9, _WBCIR_REG_WCEIR_EV_EN@GOTPAGE
Lloh18:
	ldr	x9, [x9, _WBCIR_REG_WCEIR_EV_EN@GOTPAGEOFF]
Lloh19:
	ldr	x9, [x9]
	add	x0, x9, x8
	mov	w1, #0
	mov	w2, #7
	bl	_wbcir_set_bits
	ldr	x8, [x19, #48]
Lloh20:
	adrp	x9, _WBCIR_REG_WCEIR_CFG1@GOTPAGE
Lloh21:
	ldr	x9, [x9, _WBCIR_REG_WCEIR_CFG1@GOTPAGEOFF]
Lloh22:
	ldr	x9, [x9]
	add	x0, x9, x8
	mov	w1, #74
	mov	w2, #127
	bl	_wbcir_set_bits
	ldr	x8, [x22]
	cmp	x8, #0
	cset	w8, ne
	ldr	x9, [x19, #40]
Lloh23:
	adrp	x10, _WBCIR_REG_ECEIR_CCTL@GOTPAGE
Lloh24:
	ldr	x10, [x10, _WBCIR_REG_ECEIR_CCTL@GOTPAGEOFF]
Lloh25:
	ldr	x10, [x10]
	add	x1, x10, x9
	lsl	w0, w8, #2
	bl	_outb
	ldr	x8, [x19, #40]
Lloh26:
	adrp	x9, _WBCIR_REG_ECEIR_CTS@GOTPAGE
Lloh27:
	ldr	x9, [x9, _WBCIR_REG_ECEIR_CTS@GOTPAGEOFF]
Lloh28:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #16
	bl	_outb
Lloh29:
	adrp	x8, _WBCIR_BANK_2@GOTPAGE
Lloh30:
	ldr	x8, [x8, _WBCIR_BANK_2@GOTPAGEOFF]
Lloh31:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_wbcir_select_bank
Lloh32:
	adrp	x8, _WBCIR_EXT_ENABLE@GOTPAGE
Lloh33:
	ldr	x8, [x8, _WBCIR_EXT_ENABLE@GOTPAGEOFF]
Lloh34:
	ldr	w0, [x8]
	ldr	x8, [x19, #8]
Lloh35:
	adrp	x9, _WBCIR_REG_SP3_EXCR1@GOTPAGE
Lloh36:
	ldr	x9, [x9, _WBCIR_REG_SP3_EXCR1@GOTPAGEOFF]
Lloh37:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_outb
	ldr	x8, [x19, #8]
Lloh38:
	adrp	x9, _WBCIR_REG_SP3_EXCR2@GOTPAGE
Lloh39:
	ldr	x9, [x9, _WBCIR_REG_SP3_EXCR2@GOTPAGEOFF]
Lloh40:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #48
	bl	_outb
	ldr	w8, [x23]
	sub	w8, w8, #128
	cmp	w8, #2
	b.hi	LBB0_2
; %bb.1:
Lloh41:
	adrp	x9, l_switch.table.wbcir_init_hw@PAGE
Lloh42:
	add	x9, x9, l_switch.table.wbcir_init_hw@PAGEOFF
	ldr	w0, [x9, w8, sxtw #2]
	ldr	x8, [x19, #8]
Lloh43:
	adrp	x9, _WBCIR_REG_SP3_BGDL@GOTPAGE
Lloh44:
	ldr	x9, [x9, _WBCIR_REG_SP3_BGDL@GOTPAGEOFF]
Lloh45:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_outb
LBB0_2:
	ldr	x8, [x19, #8]
Lloh46:
	adrp	x9, _WBCIR_REG_SP3_BGDH@GOTPAGE
Lloh47:
	ldr	x9, [x9, _WBCIR_REG_SP3_BGDH@GOTPAGEOFF]
Lloh48:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #0
	bl	_outb
	ldr	w1, [x21]
	mov	x0, x19
	bl	_wbcir_select_bank
	ldr	x8, [x19, #8]
Lloh49:
	adrp	x9, _WBCIR_REG_SP3_MCR@GOTPAGE
Lloh50:
	ldr	x9, [x9, _WBCIR_REG_SP3_MCR@GOTPAGEOFF]
Lloh51:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #192
	bl	_outb
	ldr	x8, [x19, #8]
Lloh52:
	adrp	x9, _WBCIR_REG_SP3_LSR@GOTPAGE
Lloh53:
	ldr	x9, [x9, _WBCIR_REG_SP3_LSR@GOTPAGEOFF]
Lloh54:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_inb
	ldr	x8, [x19, #8]
Lloh55:
	adrp	x9, _WBCIR_REG_SP3_MSR@GOTPAGE
Lloh56:
	ldr	x9, [x9, _WBCIR_REG_SP3_MSR@GOTPAGEOFF]
Lloh57:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_inb
Lloh58:
	adrp	x23, _WBCIR_BANK_7@GOTPAGE
Lloh59:
	ldr	x23, [x23, _WBCIR_BANK_7@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x19
	bl	_wbcir_select_bank
	ldr	x8, [x19, #8]
Lloh60:
	adrp	x9, _WBCIR_REG_SP3_RCCFG@GOTPAGE
Lloh61:
	ldr	x9, [x9, _WBCIR_REG_SP3_RCCFG@GOTPAGEOFF]
Lloh62:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #16
	bl	_outb
Lloh63:
	adrp	x8, _WBCIR_BANK_4@GOTPAGE
Lloh64:
	ldr	x8, [x8, _WBCIR_BANK_4@GOTPAGEOFF]
Lloh65:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_wbcir_select_bank
	ldr	x8, [x19, #8]
Lloh66:
	adrp	x9, _WBCIR_REG_SP3_IRCR1@GOTPAGE
Lloh67:
	ldr	x9, [x9, _WBCIR_REG_SP3_IRCR1@GOTPAGEOFF]
Lloh68:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #0
	bl	_outb
Lloh69:
	adrp	x8, _WBCIR_BANK_5@GOTPAGE
Lloh70:
	ldr	x8, [x8, _WBCIR_BANK_5@GOTPAGEOFF]
Lloh71:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_wbcir_select_bank
	ldr	x8, [x19, #8]
Lloh72:
	adrp	x9, _WBCIR_REG_SP3_IRCR2@GOTPAGE
Lloh73:
	ldr	x9, [x9, _WBCIR_REG_SP3_IRCR2@GOTPAGEOFF]
Lloh74:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #0
	bl	_outb
Lloh75:
	adrp	x8, _WBCIR_BANK_6@GOTPAGE
Lloh76:
	ldr	x8, [x8, _WBCIR_BANK_6@GOTPAGEOFF]
Lloh77:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_wbcir_select_bank
	ldr	x8, [x19, #8]
Lloh78:
	adrp	x9, _WBCIR_REG_SP3_IRCR3@GOTPAGE
Lloh79:
	ldr	x9, [x9, _WBCIR_REG_SP3_IRCR3@GOTPAGEOFF]
Lloh80:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #32
	bl	_outb
	ldr	w1, [x23]
	mov	x0, x19
	bl	_wbcir_select_bank
	ldr	x8, [x19, #8]
Lloh81:
	adrp	x9, _WBCIR_REG_SP3_IRRXDC@GOTPAGE
Lloh82:
	ldr	x9, [x9, _WBCIR_REG_SP3_IRRXDC@GOTPAGEOFF]
Lloh83:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #242
	bl	_outb
	ldr	x8, [x19, #8]
Lloh84:
	adrp	x9, _WBCIR_REG_SP3_IRTXMC@GOTPAGE
Lloh85:
	ldr	x9, [x9, _WBCIR_REG_SP3_IRTXMC@GOTPAGEOFF]
Lloh86:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #105
	bl	_outb
	ldr	x8, [x22]
	cmp	x8, #0
	cset	w8, ne
	lsl	w0, w8, #4
	ldr	x8, [x19, #8]
Lloh87:
	adrp	x9, _WBCIR_REG_SP3_IRCFG4@GOTPAGE
Lloh88:
	ldr	x9, [x9, _WBCIR_REG_SP3_IRCFG4@GOTPAGEOFF]
Lloh89:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_outb
	ldr	w1, [x21]
	mov	x0, x19
	bl	_wbcir_select_bank
	ldr	x8, [x19, #8]
Lloh90:
	adrp	x9, _WBCIR_REG_SP3_FCR@GOTPAGE
Lloh91:
	ldr	x9, [x9, _WBCIR_REG_SP3_FCR@GOTPAGEOFF]
Lloh92:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #151
	bl	_outb
	ldr	x8, [x19, #8]
Lloh93:
	adrp	x9, _WBCIR_REG_SP3_ASCR@GOTPAGE
Lloh94:
	ldr	x9, [x9, _WBCIR_REG_SP3_ASCR@GOTPAGEOFF]
Lloh95:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #224
	bl	_outb
	str	wzr, [x19]
	ldr	w0, [x19, #32]
Lloh96:
	adrp	x8, _LED_OFF@GOTPAGE
Lloh97:
	ldr	x8, [x8, _LED_OFF@GOTPAGEOFF]
Lloh98:
	ldr	w1, [x8]
	bl	_led_trigger_event
	str	wzr, [x19, #4]
	str	xzr, [x19, #24]
	ldr	w0, [x19, #16]
	bl	_ir_raw_event_reset
	ldr	w0, [x19, #16]
	bl	_ir_raw_event_handle
Lloh99:
	adrp	x8, _WBCIR_IRQ_RX@GOTPAGE
Lloh100:
	ldr	x8, [x8, _WBCIR_IRQ_RX@GOTPAGEOFF]
Lloh101:
	ldr	w8, [x8]
Lloh102:
	adrp	x9, _WBCIR_IRQ_ERR@GOTPAGE
Lloh103:
	ldr	x9, [x9, _WBCIR_IRQ_ERR@GOTPAGEOFF]
Lloh104:
	ldr	w9, [x9]
	orr	w0, w9, w8
	ldr	x8, [x19, #8]
	ldr	x9, [x20]
	add	x1, x9, x8
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_outb
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpAdd	Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.cfi_endproc
                                        ; -- End function
	.comm	_WBCIR_BANK_0,4,2               ; @WBCIR_BANK_0
	.comm	_WBCIR_IRQ_NONE,4,2             ; @WBCIR_IRQ_NONE
	.comm	_WBCIR_REG_SP3_IER,8,3          ; @WBCIR_REG_SP3_IER
	.comm	_protocol,4,2                   ; @protocol
	.comm	_invert,8,3                     ; @invert
	.comm	_WBCIR_REG_WCEIR_CTL,8,3        ; @WBCIR_REG_WCEIR_CTL
	.comm	_WBCIR_REG_WCEIR_STS,8,3        ; @WBCIR_REG_WCEIR_STS
	.comm	_WBCIR_REG_WCEIR_EV_EN,8,3      ; @WBCIR_REG_WCEIR_EV_EN
	.comm	_WBCIR_REG_WCEIR_CFG1,8,3       ; @WBCIR_REG_WCEIR_CFG1
	.comm	_WBCIR_REG_ECEIR_CCTL,8,3       ; @WBCIR_REG_ECEIR_CCTL
	.comm	_WBCIR_REG_ECEIR_CTS,8,3        ; @WBCIR_REG_ECEIR_CTS
	.comm	_WBCIR_BANK_2,4,2               ; @WBCIR_BANK_2
	.comm	_WBCIR_EXT_ENABLE,4,2           ; @WBCIR_EXT_ENABLE
	.comm	_WBCIR_REG_SP3_EXCR1,8,3        ; @WBCIR_REG_SP3_EXCR1
	.comm	_WBCIR_REG_SP3_EXCR2,8,3        ; @WBCIR_REG_SP3_EXCR2
	.comm	_WBCIR_REG_SP3_BGDL,8,3         ; @WBCIR_REG_SP3_BGDL
	.comm	_WBCIR_REG_SP3_BGDH,8,3         ; @WBCIR_REG_SP3_BGDH
	.comm	_WBCIR_REG_SP3_MCR,8,3          ; @WBCIR_REG_SP3_MCR
	.comm	_WBCIR_REG_SP3_LSR,8,3          ; @WBCIR_REG_SP3_LSR
	.comm	_WBCIR_REG_SP3_MSR,8,3          ; @WBCIR_REG_SP3_MSR
	.comm	_WBCIR_BANK_7,4,2               ; @WBCIR_BANK_7
	.comm	_WBCIR_REG_SP3_RCCFG,8,3        ; @WBCIR_REG_SP3_RCCFG
	.comm	_WBCIR_BANK_4,4,2               ; @WBCIR_BANK_4
	.comm	_WBCIR_REG_SP3_IRCR1,8,3        ; @WBCIR_REG_SP3_IRCR1
	.comm	_WBCIR_BANK_5,4,2               ; @WBCIR_BANK_5
	.comm	_WBCIR_REG_SP3_IRCR2,8,3        ; @WBCIR_REG_SP3_IRCR2
	.comm	_WBCIR_BANK_6,4,2               ; @WBCIR_BANK_6
	.comm	_WBCIR_REG_SP3_IRCR3,8,3        ; @WBCIR_REG_SP3_IRCR3
	.comm	_WBCIR_REG_SP3_IRRXDC,8,3       ; @WBCIR_REG_SP3_IRRXDC
	.comm	_WBCIR_REG_SP3_IRTXMC,8,3       ; @WBCIR_REG_SP3_IRTXMC
	.comm	_WBCIR_REG_SP3_IRCFG4,8,3       ; @WBCIR_REG_SP3_IRCFG4
	.comm	_WBCIR_REG_SP3_FCR,8,3          ; @WBCIR_REG_SP3_FCR
	.comm	_WBCIR_REG_SP3_ASCR,8,3         ; @WBCIR_REG_SP3_ASCR
	.comm	_LED_OFF,4,2                    ; @LED_OFF
	.comm	_WBCIR_IRQ_RX,4,2               ; @WBCIR_IRQ_RX
	.comm	_WBCIR_IRQ_ERR,4,2              ; @WBCIR_IRQ_ERR
	.no_dead_strip	_wbcir_init_hw
	.section	__TEXT,__const
	.p2align	2                               ; @switch.table.wbcir_init_hw
l_switch.table.wbcir_init_hw:
	.long	83                              ; 0x53
	.long	167                             ; 0xa7
	.long	105                             ; 0x69

.subsections_via_symbols
