	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_crtc_dpms
_radeon_crtc_dpms:                      ## @radeon_crtc_dpms
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %r15
	callq	_to_radeon_crtc
	movq	(%r15), %rdi
	movq	(%rdi), %r8
	movq	_RADEON_CRTC_VSYNC_DIS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	_RADEON_CRTC2_DISP_DIS@GOTPCREL(%rip), %rsi
	movq	_RADEON_CRTC2_VSYNC_DIS@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rsi), %ebx
	movq	_RADEON_CRTC_DISPLAY_DIS@GOTPCREL(%rip), %rsi
	movq	_RADEON_CRTC2_HSYNC_DIS@GOTPCREL(%rip), %rdx
	orl	(%rsi), %ecx
	orl	(%rdx), %ebx
	movq	_RADEON_CRTC_HSYNC_DIS@GOTPCREL(%rip), %rsi
	movq	_RADEON_CRTC2_DISP_REQ_EN_B@GOTPCREL(%rip), %rdx
	orl	(%rsi), %ecx
	orl	(%rdx), %ebx
	movq	%rax, %r13
	movq	8(%rax), %rsi
	testq	%rsi, %rsi
	cmovel	%ecx, %ebx
	movq	_RADEON_SINGLE_CRTC@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	andl	(%r8), %r12d
	je	LBB0_2
## %bb.1:
	movq	_RADEON_CRTC_CRT_ON@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
LBB0_2:
	leal	-128(%r14), %eax
	cmpl	$2, %eax
	jb	LBB0_9
## %bb.3:
	cmpl	$131, %r14d
	je	LBB0_9
## %bb.4:
	cmpl	$130, %r14d
	jne	LBB0_13
## %bb.5:
	movq	%rdi, -48(%rbp)                 ## 8-byte Spill
	movl	$1, (%r13)
	movq	%r8, %rdi
	callq	_radeon_pm_compute_clocks
	cmpq	$0, 8(%r13)
	je	LBB0_7
## %bb.6:
	movq	_RADEON_CRTC2_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_CRTC2_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	%esi, %ebx
	notl	%ebx
	jmp	LBB0_8
LBB0_9:
	movq	%r8, %r15
	callq	_drm_vblank_pre_modeset
	cmpq	$0, 8(%r13)
	je	LBB0_11
## %bb.10:
	movq	_RADEON_CRTC2_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	_RADEON_CRTC2_GEN_CNTL@GOTPCREL(%rip), %rax
	jmp	LBB0_12
LBB0_11:
	movq	_RADEON_CRTC_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_CRTC_DISP_REQ_EN_B@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_RADEON_CRTC_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	orl	%esi, %edx
	notl	%edx
	callq	_WREG32_P
	movq	_RADEON_CRTC_EXT_CNTL@GOTPCREL(%rip), %rax
LBB0_12:
	movl	(%rax), %edi
	orl	%ebx, %r12d
	notl	%r12d
	movl	%ebx, %esi
	movl	%r12d, %edx
	callq	_WREG32_P
	movl	$0, (%r13)
	movq	%r15, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_pm_compute_clocks       ## TAILCALL
LBB0_13:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_7:
	movq	_RADEON_CRTC_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_CRTC_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_RADEON_CRTC_DISP_REQ_EN_B@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	orl	%esi, %edx
	notl	%edx
	callq	_WREG32_P
	movq	_RADEON_CRTC_EXT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	orl	%r12d, %ebx
	notl	%ebx
	movl	%r12d, %esi
LBB0_8:
	movl	%ebx, %edx
	callq	_WREG32_P
	movq	8(%r13), %rsi
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_drm_vblank_post_modeset
	movq	%r15, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_crtc_load_lut           ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_CRTC2_DISP_DIS,4,2      ## @RADEON_CRTC2_DISP_DIS
	.comm	_RADEON_CRTC2_VSYNC_DIS,4,2     ## @RADEON_CRTC2_VSYNC_DIS
	.comm	_RADEON_CRTC2_HSYNC_DIS,4,2     ## @RADEON_CRTC2_HSYNC_DIS
	.comm	_RADEON_CRTC2_DISP_REQ_EN_B,4,2 ## @RADEON_CRTC2_DISP_REQ_EN_B
	.comm	_RADEON_CRTC_DISPLAY_DIS,4,2    ## @RADEON_CRTC_DISPLAY_DIS
	.comm	_RADEON_CRTC_VSYNC_DIS,4,2      ## @RADEON_CRTC_VSYNC_DIS
	.comm	_RADEON_CRTC_HSYNC_DIS,4,2      ## @RADEON_CRTC_HSYNC_DIS
	.comm	_RADEON_SINGLE_CRTC,4,2         ## @RADEON_SINGLE_CRTC
	.comm	_RADEON_CRTC_CRT_ON,4,2         ## @RADEON_CRTC_CRT_ON
	.comm	_RADEON_CRTC2_GEN_CNTL,4,2      ## @RADEON_CRTC2_GEN_CNTL
	.comm	_RADEON_CRTC2_EN,4,2            ## @RADEON_CRTC2_EN
	.comm	_RADEON_CRTC_GEN_CNTL,4,2       ## @RADEON_CRTC_GEN_CNTL
	.comm	_RADEON_CRTC_EN,4,2             ## @RADEON_CRTC_EN
	.comm	_RADEON_CRTC_DISP_REQ_EN_B,4,2  ## @RADEON_CRTC_DISP_REQ_EN_B
	.comm	_RADEON_CRTC_EXT_CNTL,4,2       ## @RADEON_CRTC_EXT_CNTL
	.no_dead_strip	_radeon_crtc_dpms
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_crtc_dpms
_radeon_crtc_dpms:                      ; @radeon_crtc_dpms
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x25, x1
	mov	x20, x0
	bl	_to_radeon_crtc
	mov	x19, x0
	ldr	x21, [x20]
	ldr	x22, [x21]
	ldr	x1, [x0, #8]
Lloh0:
	adrp	x8, _RADEON_CRTC_VSYNC_DIS@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_CRTC_VSYNC_DIS@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _RADEON_CRTC2_DISP_DIS@GOTPAGE
Lloh4:
	ldr	x9, [x9, _RADEON_CRTC2_DISP_DIS@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
Lloh6:
	adrp	x10, _RADEON_CRTC2_VSYNC_DIS@GOTPAGE
Lloh7:
	ldr	x10, [x10, _RADEON_CRTC2_VSYNC_DIS@GOTPAGEOFF]
Lloh8:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh9:
	adrp	x10, _RADEON_CRTC_DISPLAY_DIS@GOTPAGE
Lloh10:
	ldr	x10, [x10, _RADEON_CRTC_DISPLAY_DIS@GOTPAGEOFF]
Lloh11:
	ldr	w10, [x10]
Lloh12:
	adrp	x11, _RADEON_CRTC2_HSYNC_DIS@GOTPAGE
Lloh13:
	ldr	x11, [x11, _RADEON_CRTC2_HSYNC_DIS@GOTPAGEOFF]
Lloh14:
	ldr	w11, [x11]
	orr	w8, w8, w10
	orr	w9, w9, w11
Lloh15:
	adrp	x10, _RADEON_CRTC_HSYNC_DIS@GOTPAGE
Lloh16:
	ldr	x10, [x10, _RADEON_CRTC_HSYNC_DIS@GOTPAGEOFF]
Lloh17:
	ldr	w10, [x10]
Lloh18:
	adrp	x11, _RADEON_CRTC2_DISP_REQ_EN_B@GOTPAGE
Lloh19:
	ldr	x11, [x11, _RADEON_CRTC2_DISP_REQ_EN_B@GOTPAGEOFF]
Lloh20:
	ldr	w11, [x11]
	orr	w8, w8, w10
	orr	w9, w9, w11
	cmp	x1, #0
	csel	w23, w8, w9, eq
	ldr	w8, [x22]
Lloh21:
	adrp	x9, _RADEON_SINGLE_CRTC@GOTPAGE
Lloh22:
	ldr	x9, [x9, _RADEON_SINGLE_CRTC@GOTPAGEOFF]
Lloh23:
	adrp	x10, _RADEON_CRTC_CRT_ON@GOTPAGE
Lloh24:
	ldr	x10, [x10, _RADEON_CRTC_CRT_ON@GOTPAGEOFF]
Lloh25:
	ldr	w9, [x9]
Lloh26:
	ldr	w10, [x10]
	tst	w9, w8
	csel	w24, wzr, w10, eq
	sub	w8, w25, #128
	cmp	w8, #2
	b.lo	LBB0_5
; %bb.1:
	cmp	w25, #131
	b.eq	LBB0_5
; %bb.2:
	cmp	w25, #130
	b.ne	LBB0_9
; %bb.3:
	mov	w8, #1
	str	w8, [x19]
	mov	x0, x22
	bl	_radeon_pm_compute_clocks
	ldr	x8, [x19, #8]
	cbz	x8, LBB0_10
; %bb.4:
Lloh27:
	adrp	x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGE
Lloh28:
	ldr	x8, [x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
Lloh30:
	adrp	x8, _RADEON_CRTC2_EN@GOTPAGE
Lloh31:
	ldr	x8, [x8, _RADEON_CRTC2_EN@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
	orr	w8, w1, w23
	mvn	w2, w8
	b	LBB0_11
LBB0_5:
	mov	x0, x21
	bl	_drm_vblank_pre_modeset
	ldr	x8, [x19, #8]
	cbz	x8, LBB0_7
; %bb.6:
Lloh33:
	adrp	x8, _RADEON_CRTC2_EN@GOTPAGE
Lloh34:
	ldr	x8, [x8, _RADEON_CRTC2_EN@GOTPAGEOFF]
Lloh35:
	ldr	w24, [x8]
Lloh36:
	adrp	x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGE
Lloh37:
	ldr	x8, [x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGEOFF]
	b	LBB0_8
LBB0_7:
Lloh38:
	adrp	x8, _RADEON_CRTC_GEN_CNTL@GOTPAGE
Lloh39:
	ldr	x8, [x8, _RADEON_CRTC_GEN_CNTL@GOTPAGEOFF]
Lloh40:
	ldr	w0, [x8]
Lloh41:
	adrp	x8, _RADEON_CRTC_DISP_REQ_EN_B@GOTPAGE
Lloh42:
	ldr	x8, [x8, _RADEON_CRTC_DISP_REQ_EN_B@GOTPAGEOFF]
Lloh43:
	ldr	w1, [x8]
Lloh44:
	adrp	x8, _RADEON_CRTC_EN@GOTPAGE
Lloh45:
	ldr	x8, [x8, _RADEON_CRTC_EN@GOTPAGEOFF]
Lloh46:
	ldr	w8, [x8]
	orr	w8, w8, w1
	mvn	w2, w8
	bl	_WREG32_P
Lloh47:
	adrp	x8, _RADEON_CRTC_EXT_CNTL@GOTPAGE
Lloh48:
	ldr	x8, [x8, _RADEON_CRTC_EXT_CNTL@GOTPAGEOFF]
LBB0_8:
	ldr	w0, [x8]
	orr	w8, w24, w23
	mvn	w2, w8
	mov	x1, x23
	bl	_WREG32_P
	str	wzr, [x19]
	mov	x0, x22
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_radeon_pm_compute_clocks
LBB0_9:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_10:
Lloh49:
	adrp	x8, _RADEON_CRTC_GEN_CNTL@GOTPAGE
Lloh50:
	ldr	x8, [x8, _RADEON_CRTC_GEN_CNTL@GOTPAGEOFF]
Lloh51:
	ldr	w0, [x8]
Lloh52:
	adrp	x8, _RADEON_CRTC_EN@GOTPAGE
Lloh53:
	ldr	x8, [x8, _RADEON_CRTC_EN@GOTPAGEOFF]
Lloh54:
	ldr	w1, [x8]
Lloh55:
	adrp	x8, _RADEON_CRTC_DISP_REQ_EN_B@GOTPAGE
Lloh56:
	ldr	x8, [x8, _RADEON_CRTC_DISP_REQ_EN_B@GOTPAGEOFF]
Lloh57:
	ldr	w8, [x8]
	orr	w8, w8, w1
	mvn	w2, w8
	bl	_WREG32_P
Lloh58:
	adrp	x8, _RADEON_CRTC_EXT_CNTL@GOTPAGE
Lloh59:
	ldr	x8, [x8, _RADEON_CRTC_EXT_CNTL@GOTPAGEOFF]
Lloh60:
	ldr	w0, [x8]
	orr	w8, w24, w23
	mvn	w2, w8
	mov	x1, x24
LBB0_11:
	bl	_WREG32_P
	ldr	x1, [x19, #8]
	mov	x0, x21
	bl	_drm_vblank_post_modeset
	mov	x0, x20
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_radeon_crtc_load_lut
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh25
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_CRTC2_DISP_DIS,4,2      ; @RADEON_CRTC2_DISP_DIS
	.comm	_RADEON_CRTC2_VSYNC_DIS,4,2     ; @RADEON_CRTC2_VSYNC_DIS
	.comm	_RADEON_CRTC2_HSYNC_DIS,4,2     ; @RADEON_CRTC2_HSYNC_DIS
	.comm	_RADEON_CRTC2_DISP_REQ_EN_B,4,2 ; @RADEON_CRTC2_DISP_REQ_EN_B
	.comm	_RADEON_CRTC_DISPLAY_DIS,4,2    ; @RADEON_CRTC_DISPLAY_DIS
	.comm	_RADEON_CRTC_VSYNC_DIS,4,2      ; @RADEON_CRTC_VSYNC_DIS
	.comm	_RADEON_CRTC_HSYNC_DIS,4,2      ; @RADEON_CRTC_HSYNC_DIS
	.comm	_RADEON_SINGLE_CRTC,4,2         ; @RADEON_SINGLE_CRTC
	.comm	_RADEON_CRTC_CRT_ON,4,2         ; @RADEON_CRTC_CRT_ON
	.comm	_RADEON_CRTC2_GEN_CNTL,4,2      ; @RADEON_CRTC2_GEN_CNTL
	.comm	_RADEON_CRTC2_EN,4,2            ; @RADEON_CRTC2_EN
	.comm	_RADEON_CRTC_GEN_CNTL,4,2       ; @RADEON_CRTC_GEN_CNTL
	.comm	_RADEON_CRTC_EN,4,2             ; @RADEON_CRTC_EN
	.comm	_RADEON_CRTC_DISP_REQ_EN_B,4,2  ; @RADEON_CRTC_DISP_REQ_EN_B
	.comm	_RADEON_CRTC_EXT_CNTL,4,2       ; @RADEON_CRTC_EXT_CNTL
	.no_dead_strip	_radeon_crtc_dpms
.subsections_via_symbols
