	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function nvc0_dmaobj_bind
_nvc0_dmaobj_bind:                      ## @nvc0_dmaobj_bind
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rcx, %r14
	movq	%rdx, %r12
	movq	%rsi, %rbx
	movq	%rdx, %rdi
	callq	_nv_mclass
	movl	%eax, %r13d
	movq	_NV_ENGCTX_CLASS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_nv_iclass
	movl	%eax, %ecx
	xorl	%eax, %eax
	testl	%ecx, %ecx
	jne	LBB0_19
## %bb.1:
	movq	(%rbx), %rdi
	callq	_nv_mclass
	addl	$-136, %eax
	cmpl	$3, %eax
	jae	LBB0_2
## %bb.3:
	movl	(%r12), %r15d
	movl	4(%r12), %eax
	movq	_NVC0_DMA_CONF0_ENABLE@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	jne	LBB0_7
## %bb.4:
	cmpl	$129, %eax
	jne	LBB0_6
## %bb.5:
	movq	_NVC0_DMA_CONF0_PRIV_VM@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	%r15d, (%r12)
	movq	_NVC0_DMA_CONF0_TYPE_VM@GOTPCREL(%rip), %rax
	orl	(%rax), %r15d
	movl	%r15d, (%r12)
	movq	_NVC0_DMA_CONF0_TYPE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r15d, %eax
	shll	$22, %eax
	orl	%r13d, %eax
	movq	_NVC0_DMA_CONF0_PRIV@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r13d
	andl	%r15d, %r13d
	orl	%eax, %r13d
	movq	_NVC0_DMA_CONF0_UNKN@GOTPCREL(%rip), %rax
	andl	(%rax), %r15d
	jmp	LBB0_12
LBB0_6:
	movq	_NVC0_DMA_CONF0_PRIV_US@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r15d
	movl	%r15d, (%r12)
	movq	_NVC0_DMA_CONF0_TYPE_LINEAR@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r15d
	orl	$131072, %r15d                  ## imm = 0x20000
	movl	%r15d, (%r12)
LBB0_7:
	addl	$-128, %eax
	cmpl	$3, %eax
	ja	LBB0_2
## %bb.8:
	movq	_NVC0_DMA_CONF0_TYPE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%r15d, %ecx
	shll	$22, %ecx
	orl	%r13d, %ecx
	movq	_NVC0_DMA_CONF0_PRIV@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r13d
	andl	%r15d, %r13d
	movq	_NVC0_DMA_CONF0_UNKN@GOTPCREL(%rip), %rdx
	andl	(%rdx), %r15d
	orl	%ecx, %r13d
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_11:
	orl	$65536, %r13d                   ## imm = 0x10000
	jmp	LBB0_12
LBB0_2:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_19
LBB0_10:
	orl	$196608, %r13d                  ## imm = 0x30000
	jmp	LBB0_12
LBB0_9:
	orl	$131072, %r13d                  ## imm = 0x20000
LBB0_12:
	movl	8(%r12), %eax
	cmpl	$132, %eax
	je	LBB0_16
## %bb.13:
	cmpl	$134, %eax
	je	LBB0_16
## %bb.14:
	cmpl	$135, %eax
	jne	LBB0_17
## %bb.15:
	orl	$262144, %r13d                  ## imm = 0x40000
	jmp	LBB0_17
LBB0_16:
	orl	$524288, %r13d                  ## imm = 0x80000
LBB0_17:
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	movl	$24, %edx
	movl	$32, %ecx
	xorl	%r8d, %r8d
	movq	%r14, %r9
	callq	_nouveau_gpuobj_new
	testl	%eax, %eax
	jne	LBB0_19
## %bb.18:
	movq	(%r14), %rdi
	xorl	%esi, %esi
	movl	%r13d, %edx
	callq	_nv_wo32
	movq	(%r14), %rbx
	movl	16(%r12), %edi
	callq	_lower_32_bits
	movq	%rbx, %rdi
	movl	$4, %esi
	movl	%eax, %edx
	callq	_nv_wo32
	movq	(%r14), %rbx
	movl	12(%r12), %edi
	callq	_lower_32_bits
	movq	%rbx, %rdi
	movl	$8, %esi
	movl	%eax, %edx
	callq	_nv_wo32
	movq	(%r14), %r13
	movl	16(%r12), %edi
	callq	_upper_32_bits
	movl	%eax, %ebx
	shll	$24, %ebx
	movl	12(%r12), %edi
	callq	_upper_32_bits
	orl	%eax, %ebx
	movq	%r13, %rdi
	movl	$12, %esi
	movl	%ebx, %edx
	callq	_nv_wo32
	movq	(%r14), %rdi
	movl	$16, %esi
	xorl	%edx, %edx
	callq	_nv_wo32
	movq	(%r14), %rdi
	movl	$20, %esi
	movl	%r15d, %edx
	callq	_nv_wo32
	xorl	%eax, %eax
LBB0_19:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_11, LBB0_11-LJTI0_0
.set L0_0_set_12, LBB0_12-LJTI0_0
.set L0_0_set_10, LBB0_10-LJTI0_0
.set L0_0_set_9, LBB0_9-LJTI0_0
LJTI0_0:
	.long	L0_0_set_11
	.long	L0_0_set_12
	.long	L0_0_set_10
	.long	L0_0_set_9
	.end_data_region
                                        ## -- End function
	.comm	_NV_ENGCTX_CLASS,4,2            ## @NV_ENGCTX_CLASS
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_NVC0_DMA_CONF0_ENABLE,4,2      ## @NVC0_DMA_CONF0_ENABLE
	.comm	_NVC0_DMA_CONF0_PRIV_VM,4,2     ## @NVC0_DMA_CONF0_PRIV_VM
	.comm	_NVC0_DMA_CONF0_TYPE_VM,4,2     ## @NVC0_DMA_CONF0_TYPE_VM
	.comm	_NVC0_DMA_CONF0_PRIV_US,4,2     ## @NVC0_DMA_CONF0_PRIV_US
	.comm	_NVC0_DMA_CONF0_TYPE_LINEAR,4,2 ## @NVC0_DMA_CONF0_TYPE_LINEAR
	.comm	_NVC0_DMA_CONF0_TYPE,4,2        ## @NVC0_DMA_CONF0_TYPE
	.comm	_NVC0_DMA_CONF0_PRIV,4,2        ## @NVC0_DMA_CONF0_PRIV
	.comm	_NVC0_DMA_CONF0_UNKN,4,2        ## @NVC0_DMA_CONF0_UNKN
	.no_dead_strip	_nvc0_dmaobj_bind
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function nvc0_dmaobj_bind
_nvc0_dmaobj_bind:                      ; @nvc0_dmaobj_bind
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x3
	mov	x20, x2
	mov	x21, x1
	mov	x0, x2
	bl	_nv_mclass
	mov	x22, x0
Lloh0:
	adrp	x8, _NV_ENGCTX_CLASS@GOTPAGE
Lloh1:
	ldr	x8, [x8, _NV_ENGCTX_CLASS@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x21
	bl	_nv_iclass
	cbz	w0, LBB0_2
LBB0_1:
	mov	w0, #0
	b	LBB0_18
LBB0_2:
	ldr	x0, [x21]
	bl	_nv_mclass
	sub	w8, w0, #136
	cmp	w8, #3
	b.hs	LBB0_10
; %bb.3:
Lloh3:
	adrp	x8, _NVC0_DMA_CONF0_ENABLE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _NVC0_DMA_CONF0_ENABLE@GOTPAGEOFF]
Lloh5:
	ldr	w10, [x8]
	ldp	w9, w8, [x20]
	tst	w10, w9
	b.ne	LBB0_7
; %bb.4:
	cmp	w8, #129
	b.ne	LBB0_6
; %bb.5:
Lloh6:
	adrp	x8, _NVC0_DMA_CONF0_PRIV_VM@GOTPAGE
Lloh7:
	ldr	x8, [x8, _NVC0_DMA_CONF0_PRIV_VM@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
Lloh9:
	adrp	x9, _NVC0_DMA_CONF0_TYPE_VM@GOTPAGE
Lloh10:
	ldr	x9, [x9, _NVC0_DMA_CONF0_TYPE_VM@GOTPAGEOFF]
	str	w8, [x20]
Lloh11:
	ldr	w9, [x9]
	orr	w9, w9, w8
	str	w9, [x20]
Lloh12:
	adrp	x8, _NVC0_DMA_CONF0_TYPE@GOTPAGE
Lloh13:
	ldr	x8, [x8, _NVC0_DMA_CONF0_TYPE@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	and	w8, w8, w9
	orr	w8, w22, w8, lsl #22
Lloh15:
	adrp	x10, _NVC0_DMA_CONF0_PRIV@GOTPAGE
Lloh16:
	ldr	x10, [x10, _NVC0_DMA_CONF0_PRIV@GOTPAGEOFF]
Lloh17:
	ldr	w10, [x10]
	and	w10, w10, w9
	orr	w8, w8, w10
Lloh18:
	adrp	x10, _NVC0_DMA_CONF0_UNKN@GOTPAGE
Lloh19:
	ldr	x10, [x10, _NVC0_DMA_CONF0_UNKN@GOTPAGEOFF]
Lloh20:
	ldr	w10, [x10]
	and	w22, w10, w9
	b	LBB0_13
LBB0_6:
Lloh21:
	adrp	x9, _NVC0_DMA_CONF0_PRIV_US@GOTPAGE
Lloh22:
	ldr	x9, [x9, _NVC0_DMA_CONF0_PRIV_US@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	str	w9, [x20]
Lloh24:
	adrp	x10, _NVC0_DMA_CONF0_TYPE_LINEAR@GOTPAGE
Lloh25:
	ldr	x10, [x10, _NVC0_DMA_CONF0_TYPE_LINEAR@GOTPAGEOFF]
Lloh26:
	ldr	w10, [x10]
	orr	w9, w9, w10
	orr	w9, w9, #0x20000
	str	w9, [x20]
LBB0_7:
	sub	w10, w8, #128
	cmp	w10, #3
	b.hi	LBB0_10
; %bb.8:
Lloh27:
	adrp	x8, _NVC0_DMA_CONF0_TYPE@GOTPAGE
Lloh28:
	ldr	x8, [x8, _NVC0_DMA_CONF0_TYPE@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	and	w8, w8, w9
	orr	w8, w22, w8, lsl #22
Lloh30:
	adrp	x11, _NVC0_DMA_CONF0_PRIV@GOTPAGE
Lloh31:
	ldr	x11, [x11, _NVC0_DMA_CONF0_PRIV@GOTPAGEOFF]
Lloh32:
	ldr	w11, [x11]
	and	w11, w11, w9
Lloh33:
	adrp	x12, _NVC0_DMA_CONF0_UNKN@GOTPAGE
Lloh34:
	ldr	x12, [x12, _NVC0_DMA_CONF0_UNKN@GOTPAGEOFF]
	orr	w8, w8, w11
Lloh35:
	ldr	w11, [x12]
	and	w22, w11, w9
Lloh36:
	adrp	x9, lJTI0_0@PAGE
Lloh37:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x11, LBB0_9
	ldrb	w12, [x9, x10]
	add	x11, x11, x12, lsl #2
	br	x11
LBB0_9:
	orr	w8, w8, #0x10000
	b	LBB0_13
LBB0_10:
Lloh38:
	adrp	x8, _EINVAL@GOTPAGE
Lloh39:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_18
LBB0_11:
	orr	w8, w8, #0x30000
	b	LBB0_13
LBB0_12:
	orr	w8, w8, #0x20000
LBB0_13:
	ldr	w9, [x20, #8]
	cmp	w9, #132
	b.eq	LBB0_16
; %bb.14:
	cmp	w9, #134
	b.eq	LBB0_16
; %bb.15:
	orr	w10, w8, #0x40000
	cmp	w9, #135
	csel	w23, w8, w10, ne
	b	LBB0_17
LBB0_16:
	orr	w23, w8, #0x80000
LBB0_17:
	mov	x0, x21
	mov	x1, x21
	mov	w2, #24
	mov	w3, #32
	mov	w4, #0
	mov	x5, x19
	bl	_nouveau_gpuobj_new
	cbz	w0, LBB0_19
LBB0_18:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_19:
	ldr	x0, [x19]
	mov	w1, #0
	mov	x2, x23
	bl	_nv_wo32
	ldr	x21, [x19]
	ldr	w0, [x20, #16]
	bl	_lower_32_bits
	mov	x2, x0
	mov	x0, x21
	mov	w1, #4
	bl	_nv_wo32
	ldr	x21, [x19]
	ldr	w0, [x20, #12]
	bl	_lower_32_bits
	mov	x2, x0
	mov	x0, x21
	mov	w1, #8
	bl	_nv_wo32
	ldr	x21, [x19]
	ldr	w0, [x20, #16]
	bl	_upper_32_bits
	mov	x23, x0
	ldr	w0, [x20, #12]
	bl	_upper_32_bits
	orr	w2, w0, w23, lsl #24
	mov	x0, x21
	mov	w1, #12
	bl	_nv_wo32
	ldr	x0, [x19]
	mov	w1, #16
	mov	w2, #0
	bl	_nv_wo32
	ldr	x0, [x19]
	mov	w1, #20
	mov	x2, x22
	bl	_nv_wo32
	b	LBB0_1
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpAdd	Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_9-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_11-LBB0_9)>>2
	.byte	(LBB0_12-LBB0_9)>>2
                                        ; -- End function
	.comm	_NV_ENGCTX_CLASS,4,2            ; @NV_ENGCTX_CLASS
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_NVC0_DMA_CONF0_ENABLE,4,2      ; @NVC0_DMA_CONF0_ENABLE
	.comm	_NVC0_DMA_CONF0_PRIV_VM,4,2     ; @NVC0_DMA_CONF0_PRIV_VM
	.comm	_NVC0_DMA_CONF0_TYPE_VM,4,2     ; @NVC0_DMA_CONF0_TYPE_VM
	.comm	_NVC0_DMA_CONF0_PRIV_US,4,2     ; @NVC0_DMA_CONF0_PRIV_US
	.comm	_NVC0_DMA_CONF0_TYPE_LINEAR,4,2 ; @NVC0_DMA_CONF0_TYPE_LINEAR
	.comm	_NVC0_DMA_CONF0_TYPE,4,2        ; @NVC0_DMA_CONF0_TYPE
	.comm	_NVC0_DMA_CONF0_PRIV,4,2        ; @NVC0_DMA_CONF0_PRIV
	.comm	_NVC0_DMA_CONF0_UNKN,4,2        ; @NVC0_DMA_CONF0_UNKN
	.no_dead_strip	_nvc0_dmaobj_bind
.subsections_via_symbols
