	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_driver_irq_postinstall  ## -- Begin function radeon_driver_irq_postinstall
	.p2align	4, 0x90
_radeon_driver_irq_postinstall:         ## @radeon_driver_irq_postinstall
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %r14
	movq	8(%rdi), %rbx
	leaq	8(%rbx), %rdi
	xorl	%esi, %esi
	callq	_atomic_set
	leaq	4(%rbx), %rdi
	callq	_DRM_INIT_WAITQUEUE
	movl	$2097151, (%r14)                ## imm = 0x1FFFFF
	movq	_RADEON_FAMILY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%rbx), %eax
	movq	_CHIP_R600@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jge	LBB0_2
## %bb.1:
	movq	_RADEON_SW_INT_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$1, %edx
	callq	_radeon_irq_set_state
LBB0_2:
	xorl	%eax, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_FAMILY_MASK,4,2         ## @RADEON_FAMILY_MASK
	.comm	_CHIP_R600,4,2                  ## @CHIP_R600
	.comm	_RADEON_SW_INT_ENABLE,4,2       ## @RADEON_SW_INT_ENABLE
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_driver_irq_postinstall  ; -- Begin function radeon_driver_irq_postinstall
	.p2align	2
_radeon_driver_irq_postinstall:         ; @radeon_driver_irq_postinstall
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	x20, [x0, #8]
	add	x0, x20, #8
	mov	w1, #0
	bl	_atomic_set
	add	x0, x20, #4
	bl	_DRM_INIT_WAITQUEUE
	mov	w8, #2097151
	str	w8, [x19]
	ldr	w8, [x20]
Lloh0:
	adrp	x9, _RADEON_FAMILY_MASK@GOTPAGE
Lloh1:
	ldr	x9, [x9, _RADEON_FAMILY_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	and	w8, w9, w8
Lloh3:
	adrp	x9, _CHIP_R600@GOTPAGE
Lloh4:
	ldr	x9, [x9, _CHIP_R600@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ge	LBB0_2
; %bb.1:
Lloh6:
	adrp	x8, _RADEON_SW_INT_ENABLE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_SW_INT_ENABLE@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_radeon_irq_set_state
LBB0_2:
	mov	w0, #0
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_FAMILY_MASK,4,2         ; @RADEON_FAMILY_MASK
	.comm	_CHIP_R600,4,2                  ; @CHIP_R600
	.comm	_RADEON_SW_INT_ENABLE,4,2       ; @RADEON_SW_INT_ENABLE
.subsections_via_symbols
