	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function sdhci_set_ios
_sdhci_set_ios:                         ## @sdhci_set_ios
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r15
	callq	_mmc_priv
	movq	%rax, %r13
	leaq	24(%rax), %r14
	movq	%r14, %rdi
	callq	_spin_lock_irqsave
	movq	_SDHCI_DEVICE_DEAD@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r13)
	jne	LBB0_28
## %bb.1:
	movq	(%r15), %rax
	movq	_MMC_POWER_OFF@GOTPCREL(%rip), %rbx
	cmpq	(%rbx), %rax
	jne	LBB0_3
## %bb.2:
	movq	_SDHCI_SIGNAL_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	_sdhci_writel
	movq	%r13, %rdi
	callq	_sdhci_reinit
LBB0_3:
	movl	8(%r15), %esi
	movq	%r13, %rdi
	callq	_sdhci_set_clock
	movq	(%r15), %rax
	movl	$-1, %esi
	cmpq	(%rbx), %rax
	je	LBB0_5
## %bb.4:
	movl	12(%r15), %esi
LBB0_5:
	movq	%r13, %rdi
	callq	_sdhci_set_power
	movq	_SDHCI_HOST_CONTROL@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r13, %rdi
	callq	_sdhci_readb
	movq	_MMC_BUS_WIDTH_8@GOTPCREL(%rip), %rcx
	movq	_SDHCI_CTRL_8BITBUS@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movl	%edx, %esi
	orl	%eax, %esi
	notl	%edx
	andl	%eax, %edx
	movq	16(%r15), %rdi
	movq	24(%r15), %rax
	cmpq	(%rcx), %rdi
	cmovel	%esi, %edx
	movq	_MMC_BUS_WIDTH_4@GOTPCREL(%rip), %rcx
	movq	_SDHCI_CTRL_4BITBUS@GOTPCREL(%rip), %rsi
	movl	(%rsi), %ebx
	movl	%ebx, %esi
	orl	%edx, %esi
	notl	%ebx
	andl	%edx, %ebx
	cmpq	(%rcx), %rdi
	cmovel	%esi, %ebx
	movq	_MMC_TIMING_SD_HS@GOTPCREL(%rip), %rdx
	movq	_SDHCI_CTRL_HISPD@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, %edi
	orl	%ebx, %edi
	movl	%ecx, %esi
	notl	%esi
	andl	%ebx, %esi
	cmpq	(%rdx), %rax
	cmovel	%edi, %esi
	movq	8(%r13), %rdx
	movq	_SDHCI_SPEC_300@GOTPCREL(%rip), %rdi
	cmpq	(%rdi), %rdx
	jge	LBB0_6
## %bb.25:
	movl	(%r12), %edx
	movq	%r13, %rdi
	callq	_sdhci_writeb
	jmp	LBB0_26
LBB0_6:
	movq	_MMC_TIMING_UHS_SDR50@GOTPCREL(%rip), %r8
	movq	_MMC_TIMING_UHS_SDR104@GOTPCREL(%rip), %r9
	movq	_MMC_TIMING_UHS_DDR50@GOTPCREL(%rip), %rdx
	movq	_MMC_TIMING_UHS_SDR25@GOTPCREL(%rip), %rdi
	xorl	%ebx, %ebx
	cmpq	(%rdi), %rax
	cmovel	%ecx, %ebx
	cmpq	(%rdx), %rax
	cmovel	%ecx, %ebx
	cmpq	(%r9), %rax
	cmovel	%ecx, %ebx
	cmpq	(%r8), %rax
	cmovel	%ecx, %ebx
	orl	%esi, %ebx
	movq	_SDHCI_HOST_CONTROL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_sdhci_readw
	movl	%eax, %r12d
	movq	_SDHCI_CTRL_PRESET_VAL_ENABLE@GOTPCREL(%rip), %rax
	testl	%r12d, (%rax)
	je	LBB0_7
## %bb.12:
	movq	_SDHCI_CLOCK_CONTROL@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r13, %rdi
	callq	_sdhci_readw
	movq	_SDHCI_CLOCK_CARD_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r12), %edx
	movq	%r13, %rdi
	callq	_sdhci_writew
	movq	_SDHCI_HOST_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_sdhci_writeb
	movl	16(%r13), %esi
	movl	$0, 16(%r13)
	movq	%r13, %rdi
	callq	_sdhci_set_clock
	movq	_SDHCI_HOST_CONTROL2@GOTPCREL(%rip), %rbx
	jmp	LBB0_13
LBB0_7:
	movq	_SDHCI_HOST_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_sdhci_writeb
	movq	_SDHCI_CTRL_DRV_TYPE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r12d
	movq	32(%r15), %rax
	movq	_MMC_SET_DRIVER_TYPE_A@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_9
## %bb.8:
	movq	_SDHCI_CTRL_DRV_TYPE_A@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
	movq	_SDHCI_HOST_CONTROL2@GOTPCREL(%rip), %rbx
	jmp	LBB0_11
LBB0_9:
	movq	_MMC_SET_DRIVER_TYPE_C@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	movq	_SDHCI_HOST_CONTROL2@GOTPCREL(%rip), %rbx
	jne	LBB0_11
## %bb.10:
	movq	_SDHCI_CTRL_DRV_TYPE_C@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
LBB0_11:
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r12d, %esi
	callq	_sdhci_writew
LBB0_13:
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_sdhci_readw
	movq	_SDHCI_CTRL_UHS_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r12d
	notl	%r12d
	andl	%eax, %r12d
	movq	24(%r15), %rax
	movq	_MMC_TIMING_UHS_SDR12@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_15
## %bb.14:
	movq	_SDHCI_CTRL_UHS_SDR12@GOTPCREL(%rip), %rax
	jmp	LBB0_23
LBB0_15:
	movq	_MMC_TIMING_UHS_SDR25@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_17
## %bb.16:
	movq	_SDHCI_CTRL_UHS_SDR25@GOTPCREL(%rip), %rax
	jmp	LBB0_23
LBB0_17:
	movq	_MMC_TIMING_UHS_SDR50@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_19
## %bb.18:
	movq	_SDHCI_CTRL_UHS_SDR50@GOTPCREL(%rip), %rax
	jmp	LBB0_23
LBB0_19:
	movq	_MMC_TIMING_UHS_SDR104@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_21
## %bb.20:
	movq	_SDHCI_CTRL_UHS_SDR104@GOTPCREL(%rip), %rax
	jmp	LBB0_23
LBB0_21:
	movq	_MMC_TIMING_UHS_DDR50@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_24
## %bb.22:
	movq	_SDHCI_CTRL_UHS_DDR50@GOTPCREL(%rip), %rax
LBB0_23:
	orl	(%rax), %r12d
LBB0_24:
	movq	_SDHCI_CLOCK_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_sdhci_readw
	movq	_SDHCI_CLOCK_CARD_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edx
	movq	%r13, %rdi
	callq	_sdhci_writew
	movq	_SDHCI_HOST_CONTROL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	%r12d, %esi
	callq	_sdhci_writew
	movl	16(%r13), %esi
	movl	$0, 16(%r13)
	movq	%r13, %rdi
	callq	_sdhci_set_clock
LBB0_26:
	movq	_SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 20(%r13)
	je	LBB0_28
## %bb.27:
	movq	_SDHCI_RESET_CMD@GOTPCREL(%rip), %rax
	movq	_SDHCI_RESET_DATA@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movq	%r13, %rdi
	callq	_sdhci_reset
LBB0_28:
	xorl	%eax, %eax
	callq	_mmiowb
	movq	%r14, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_spin_unlock_irqrestore         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_SDHCI_DEVICE_DEAD,4,2          ## @SDHCI_DEVICE_DEAD
	.comm	_MMC_POWER_OFF,8,3              ## @MMC_POWER_OFF
	.comm	_SDHCI_SIGNAL_ENABLE,4,2        ## @SDHCI_SIGNAL_ENABLE
	.comm	_SDHCI_HOST_CONTROL,4,2         ## @SDHCI_HOST_CONTROL
	.comm	_MMC_BUS_WIDTH_8,8,3            ## @MMC_BUS_WIDTH_8
	.comm	_SDHCI_CTRL_8BITBUS,4,2         ## @SDHCI_CTRL_8BITBUS
	.comm	_MMC_BUS_WIDTH_4,8,3            ## @MMC_BUS_WIDTH_4
	.comm	_SDHCI_CTRL_4BITBUS,4,2         ## @SDHCI_CTRL_4BITBUS
	.comm	_MMC_TIMING_SD_HS,8,3           ## @MMC_TIMING_SD_HS
	.comm	_SDHCI_CTRL_HISPD,4,2           ## @SDHCI_CTRL_HISPD
	.comm	_SDHCI_SPEC_300,8,3             ## @SDHCI_SPEC_300
	.comm	_MMC_TIMING_UHS_SDR50,8,3       ## @MMC_TIMING_UHS_SDR50
	.comm	_MMC_TIMING_UHS_SDR104,8,3      ## @MMC_TIMING_UHS_SDR104
	.comm	_MMC_TIMING_UHS_DDR50,8,3       ## @MMC_TIMING_UHS_DDR50
	.comm	_MMC_TIMING_UHS_SDR25,8,3       ## @MMC_TIMING_UHS_SDR25
	.comm	_SDHCI_HOST_CONTROL2,4,2        ## @SDHCI_HOST_CONTROL2
	.comm	_SDHCI_CTRL_PRESET_VAL_ENABLE,4,2 ## @SDHCI_CTRL_PRESET_VAL_ENABLE
	.comm	_SDHCI_CTRL_DRV_TYPE_MASK,4,2   ## @SDHCI_CTRL_DRV_TYPE_MASK
	.comm	_MMC_SET_DRIVER_TYPE_A,8,3      ## @MMC_SET_DRIVER_TYPE_A
	.comm	_SDHCI_CTRL_DRV_TYPE_A,4,2      ## @SDHCI_CTRL_DRV_TYPE_A
	.comm	_MMC_SET_DRIVER_TYPE_C,8,3      ## @MMC_SET_DRIVER_TYPE_C
	.comm	_SDHCI_CTRL_DRV_TYPE_C,4,2      ## @SDHCI_CTRL_DRV_TYPE_C
	.comm	_SDHCI_CLOCK_CONTROL,4,2        ## @SDHCI_CLOCK_CONTROL
	.comm	_SDHCI_CLOCK_CARD_EN,4,2        ## @SDHCI_CLOCK_CARD_EN
	.comm	_SDHCI_CTRL_UHS_MASK,4,2        ## @SDHCI_CTRL_UHS_MASK
	.comm	_MMC_TIMING_UHS_SDR12,8,3       ## @MMC_TIMING_UHS_SDR12
	.comm	_SDHCI_CTRL_UHS_SDR12,4,2       ## @SDHCI_CTRL_UHS_SDR12
	.comm	_SDHCI_CTRL_UHS_SDR25,4,2       ## @SDHCI_CTRL_UHS_SDR25
	.comm	_SDHCI_CTRL_UHS_SDR50,4,2       ## @SDHCI_CTRL_UHS_SDR50
	.comm	_SDHCI_CTRL_UHS_SDR104,4,2      ## @SDHCI_CTRL_UHS_SDR104
	.comm	_SDHCI_CTRL_UHS_DDR50,4,2       ## @SDHCI_CTRL_UHS_DDR50
	.comm	_SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,4,2 ## @SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS
	.comm	_SDHCI_RESET_CMD,4,2            ## @SDHCI_RESET_CMD
	.comm	_SDHCI_RESET_DATA,4,2           ## @SDHCI_RESET_DATA
	.no_dead_strip	_sdhci_set_ios
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function sdhci_set_ios
_sdhci_set_ios:                         ; @sdhci_set_ios
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x1
	bl	_mmc_priv
	mov	x20, x0
	add	x19, x0, #24
	mov	x0, x19
	bl	_spin_lock_irqsave
	ldr	w8, [x20]
Lloh0:
	adrp	x9, _SDHCI_DEVICE_DEAD@GOTPAGE
Lloh1:
	ldr	x9, [x9, _SDHCI_DEVICE_DEAD@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_30
; %bb.1:
	ldr	x8, [x21]
Lloh3:
	adrp	x22, _MMC_POWER_OFF@GOTPAGE
Lloh4:
	ldr	x22, [x22, _MMC_POWER_OFF@GOTPAGEOFF]
	ldr	x9, [x22]
	cmp	x8, x9
	b.ne	LBB0_3
; %bb.2:
Lloh5:
	adrp	x8, _SDHCI_SIGNAL_ENABLE@GOTPAGE
Lloh6:
	ldr	x8, [x8, _SDHCI_SIGNAL_ENABLE@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	x0, x20
	mov	w1, #0
	bl	_sdhci_writel
	mov	x0, x20
	bl	_sdhci_reinit
LBB0_3:
	ldr	w1, [x21, #8]
	mov	x0, x20
	bl	_sdhci_set_clock
	ldr	x8, [x21]
	ldr	x9, [x22]
	cmp	x8, x9
	b.ne	LBB0_5
; %bb.4:
	mov	w1, #-1
	b	LBB0_6
LBB0_5:
	ldr	w1, [x21, #12]
LBB0_6:
	mov	x0, x20
	bl	_sdhci_set_power
Lloh8:
	adrp	x26, _SDHCI_HOST_CONTROL@GOTPAGE
Lloh9:
	ldr	x26, [x26, _SDHCI_HOST_CONTROL@GOTPAGEOFF]
	ldr	w1, [x26]
	mov	x0, x20
	bl	_sdhci_readb
Lloh10:
	adrp	x8, _MMC_BUS_WIDTH_8@GOTPAGE
Lloh11:
	ldr	x8, [x8, _MMC_BUS_WIDTH_8@GOTPAGEOFF]
Lloh12:
	ldr	x9, [x8]
Lloh13:
	adrp	x8, _SDHCI_CTRL_8BITBUS@GOTPAGE
Lloh14:
	ldr	x8, [x8, _SDHCI_CTRL_8BITBUS@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
	orr	w10, w8, w0
	bic	w11, w0, w8
	ldp	x12, x8, [x21, #16]
	cmp	x12, x9
Lloh16:
	adrp	x9, _SDHCI_CTRL_4BITBUS@GOTPAGE
Lloh17:
	ldr	x9, [x9, _SDHCI_CTRL_4BITBUS@GOTPAGEOFF]
	csel	w10, w10, w11, eq
Lloh18:
	ldr	w9, [x9]
	orr	w11, w9, w10
	bic	w9, w10, w9
Lloh19:
	adrp	x10, _MMC_BUS_WIDTH_4@GOTPAGE
Lloh20:
	ldr	x10, [x10, _MMC_BUS_WIDTH_4@GOTPAGEOFF]
Lloh21:
	ldr	x10, [x10]
	cmp	x12, x10
	csel	w10, w11, w9, eq
Lloh22:
	adrp	x9, _MMC_TIMING_SD_HS@GOTPAGE
Lloh23:
	ldr	x9, [x9, _MMC_TIMING_SD_HS@GOTPAGEOFF]
Lloh24:
	ldr	x11, [x9]
Lloh25:
	adrp	x9, _SDHCI_CTRL_HISPD@GOTPAGE
Lloh26:
	ldr	x9, [x9, _SDHCI_CTRL_HISPD@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
	orr	w12, w9, w10
	bic	w10, w10, w9
	cmp	x8, x11
	csel	w1, w12, w10, eq
	ldr	x10, [x20, #8]
Lloh28:
	adrp	x11, _SDHCI_SPEC_300@GOTPAGE
Lloh29:
	ldr	x11, [x11, _SDHCI_SPEC_300@GOTPAGEOFF]
Lloh30:
	ldr	x11, [x11]
	cmp	x10, x11
	b.ge	LBB0_8
; %bb.7:
	ldr	w2, [x26]
	mov	x0, x20
	bl	_sdhci_writeb
	b	LBB0_28
LBB0_8:
Lloh31:
	adrp	x10, _MMC_TIMING_UHS_SDR50@GOTPAGE
Lloh32:
	ldr	x10, [x10, _MMC_TIMING_UHS_SDR50@GOTPAGEOFF]
Lloh33:
	ldr	x10, [x10]
Lloh34:
	adrp	x11, _MMC_TIMING_UHS_SDR104@GOTPAGE
Lloh35:
	ldr	x11, [x11, _MMC_TIMING_UHS_SDR104@GOTPAGEOFF]
Lloh36:
	ldr	x11, [x11]
Lloh37:
	adrp	x12, _MMC_TIMING_UHS_DDR50@GOTPAGE
Lloh38:
	ldr	x12, [x12, _MMC_TIMING_UHS_DDR50@GOTPAGEOFF]
Lloh39:
	ldr	x12, [x12]
Lloh40:
	adrp	x28, _MMC_TIMING_UHS_SDR25@GOTPAGE
Lloh41:
	ldr	x28, [x28, _MMC_TIMING_UHS_SDR25@GOTPAGEOFF]
	ldr	x13, [x28]
	cmp	x8, x13
	ccmp	x8, x12, #4, ne
	ccmp	x8, x11, #4, ne
	ccmp	x8, x10, #4, ne
	csel	w8, w9, wzr, eq
	orr	w22, w8, w1
Lloh42:
	adrp	x24, _SDHCI_HOST_CONTROL2@GOTPAGE
Lloh43:
	ldr	x24, [x24, _SDHCI_HOST_CONTROL2@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	x0, x20
	bl	_sdhci_readw
Lloh44:
	adrp	x8, _SDHCI_CTRL_PRESET_VAL_ENABLE@GOTPAGE
Lloh45:
	ldr	x8, [x8, _SDHCI_CTRL_PRESET_VAL_ENABLE@GOTPAGEOFF]
Lloh46:
	ldr	w8, [x8]
Lloh47:
	adrp	x25, _SDHCI_CLOCK_CONTROL@GOTPAGE
Lloh48:
	ldr	x25, [x25, _SDHCI_CLOCK_CONTROL@GOTPAGEOFF]
Lloh49:
	adrp	x27, _SDHCI_CLOCK_CARD_EN@GOTPAGE
Lloh50:
	ldr	x27, [x27, _SDHCI_CLOCK_CARD_EN@GOTPAGEOFF]
	tst	w8, w0
	b.eq	LBB0_10
; %bb.9:
	ldr	w1, [x25]
	mov	x0, x20
	bl	_sdhci_readw
	ldr	w8, [x27]
	bic	w1, w0, w8
	ldr	w2, [x25]
	mov	x0, x20
	bl	_sdhci_writew
	ldr	w2, [x26]
	mov	x0, x20
	mov	x1, x22
	bl	_sdhci_writeb
	ldr	w1, [x20, #16]
	str	wzr, [x20, #16]
	mov	x0, x20
	bl	_sdhci_set_clock
	b	LBB0_16
LBB0_10:
	mov	x23, x0
	ldr	w2, [x26]
	mov	x0, x20
	mov	x1, x22
	bl	_sdhci_writeb
Lloh51:
	adrp	x8, _SDHCI_CTRL_DRV_TYPE_MASK@GOTPAGE
Lloh52:
	ldr	x8, [x8, _SDHCI_CTRL_DRV_TYPE_MASK@GOTPAGEOFF]
Lloh53:
	ldr	w8, [x8]
	bic	w1, w23, w8
	ldr	x8, [x21, #32]
Lloh54:
	adrp	x9, _MMC_SET_DRIVER_TYPE_A@GOTPAGE
Lloh55:
	ldr	x9, [x9, _MMC_SET_DRIVER_TYPE_A@GOTPAGEOFF]
Lloh56:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_12
; %bb.11:
Lloh57:
	adrp	x8, _SDHCI_CTRL_DRV_TYPE_A@GOTPAGE
Lloh58:
	ldr	x8, [x8, _SDHCI_CTRL_DRV_TYPE_A@GOTPAGEOFF]
	b	LBB0_14
LBB0_12:
Lloh59:
	adrp	x9, _MMC_SET_DRIVER_TYPE_C@GOTPAGE
Lloh60:
	ldr	x9, [x9, _MMC_SET_DRIVER_TYPE_C@GOTPAGEOFF]
Lloh61:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_15
; %bb.13:
Lloh62:
	adrp	x8, _SDHCI_CTRL_DRV_TYPE_C@GOTPAGE
Lloh63:
	ldr	x8, [x8, _SDHCI_CTRL_DRV_TYPE_C@GOTPAGEOFF]
LBB0_14:
	ldr	w8, [x8]
	orr	w1, w8, w1
LBB0_15:
	ldr	w2, [x24]
	mov	x0, x20
	bl	_sdhci_writew
LBB0_16:
	ldr	w1, [x24]
	mov	x0, x20
	bl	_sdhci_readw
Lloh64:
	adrp	x8, _SDHCI_CTRL_UHS_MASK@GOTPAGE
Lloh65:
	ldr	x8, [x8, _SDHCI_CTRL_UHS_MASK@GOTPAGEOFF]
Lloh66:
	ldr	w8, [x8]
	bic	w22, w0, w8
	ldr	x8, [x21, #24]
Lloh67:
	adrp	x9, _MMC_TIMING_UHS_SDR12@GOTPAGE
Lloh68:
	ldr	x9, [x9, _MMC_TIMING_UHS_SDR12@GOTPAGEOFF]
Lloh69:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_18
; %bb.17:
Lloh70:
	adrp	x8, _SDHCI_CTRL_UHS_SDR12@GOTPAGE
Lloh71:
	ldr	x8, [x8, _SDHCI_CTRL_UHS_SDR12@GOTPAGEOFF]
	b	LBB0_26
LBB0_18:
	ldr	x9, [x28]
	cmp	x8, x9
	b.ne	LBB0_20
; %bb.19:
Lloh72:
	adrp	x8, _SDHCI_CTRL_UHS_SDR25@GOTPAGE
Lloh73:
	ldr	x8, [x8, _SDHCI_CTRL_UHS_SDR25@GOTPAGEOFF]
	b	LBB0_26
LBB0_20:
Lloh74:
	adrp	x9, _MMC_TIMING_UHS_SDR50@GOTPAGE
Lloh75:
	ldr	x9, [x9, _MMC_TIMING_UHS_SDR50@GOTPAGEOFF]
Lloh76:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_22
; %bb.21:
Lloh77:
	adrp	x8, _SDHCI_CTRL_UHS_SDR50@GOTPAGE
Lloh78:
	ldr	x8, [x8, _SDHCI_CTRL_UHS_SDR50@GOTPAGEOFF]
	b	LBB0_26
LBB0_22:
Lloh79:
	adrp	x9, _MMC_TIMING_UHS_SDR104@GOTPAGE
Lloh80:
	ldr	x9, [x9, _MMC_TIMING_UHS_SDR104@GOTPAGEOFF]
Lloh81:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_24
; %bb.23:
Lloh82:
	adrp	x8, _SDHCI_CTRL_UHS_SDR104@GOTPAGE
Lloh83:
	ldr	x8, [x8, _SDHCI_CTRL_UHS_SDR104@GOTPAGEOFF]
	b	LBB0_26
LBB0_24:
Lloh84:
	adrp	x9, _MMC_TIMING_UHS_DDR50@GOTPAGE
Lloh85:
	ldr	x9, [x9, _MMC_TIMING_UHS_DDR50@GOTPAGEOFF]
Lloh86:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_27
; %bb.25:
Lloh87:
	adrp	x8, _SDHCI_CTRL_UHS_DDR50@GOTPAGE
Lloh88:
	ldr	x8, [x8, _SDHCI_CTRL_UHS_DDR50@GOTPAGEOFF]
LBB0_26:
	ldr	w8, [x8]
	orr	w22, w8, w22
LBB0_27:
	ldr	w1, [x25]
	mov	x0, x20
	bl	_sdhci_readw
	ldr	w8, [x27]
	bic	w1, w0, w8
	ldr	w2, [x25]
	mov	x0, x20
	bl	_sdhci_writew
	ldr	w2, [x24]
	mov	x0, x20
	mov	x1, x22
	bl	_sdhci_writew
	ldr	w1, [x20, #16]
	str	wzr, [x20, #16]
	mov	x0, x20
	bl	_sdhci_set_clock
LBB0_28:
	ldr	w8, [x20, #20]
Lloh89:
	adrp	x9, _SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS@GOTPAGE
Lloh90:
	ldr	x9, [x9, _SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS@GOTPAGEOFF]
Lloh91:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_30
; %bb.29:
Lloh92:
	adrp	x8, _SDHCI_RESET_CMD@GOTPAGE
Lloh93:
	ldr	x8, [x8, _SDHCI_RESET_CMD@GOTPAGEOFF]
Lloh94:
	ldr	w8, [x8]
Lloh95:
	adrp	x9, _SDHCI_RESET_DATA@GOTPAGE
Lloh96:
	ldr	x9, [x9, _SDHCI_RESET_DATA@GOTPAGEOFF]
Lloh97:
	ldr	w9, [x9]
	orr	w1, w9, w8
	mov	x0, x20
	bl	_sdhci_reset
LBB0_30:
	bl	_mmiowb
	mov	x0, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_spin_unlock_irqrestore
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGot	Lloh70, Lloh71
	.loh AdrpLdrGot	Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGot	Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGot	Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGot	Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.cfi_endproc
                                        ; -- End function
	.comm	_SDHCI_DEVICE_DEAD,4,2          ; @SDHCI_DEVICE_DEAD
	.comm	_MMC_POWER_OFF,8,3              ; @MMC_POWER_OFF
	.comm	_SDHCI_SIGNAL_ENABLE,4,2        ; @SDHCI_SIGNAL_ENABLE
	.comm	_SDHCI_HOST_CONTROL,4,2         ; @SDHCI_HOST_CONTROL
	.comm	_MMC_BUS_WIDTH_8,8,3            ; @MMC_BUS_WIDTH_8
	.comm	_SDHCI_CTRL_8BITBUS,4,2         ; @SDHCI_CTRL_8BITBUS
	.comm	_MMC_BUS_WIDTH_4,8,3            ; @MMC_BUS_WIDTH_4
	.comm	_SDHCI_CTRL_4BITBUS,4,2         ; @SDHCI_CTRL_4BITBUS
	.comm	_MMC_TIMING_SD_HS,8,3           ; @MMC_TIMING_SD_HS
	.comm	_SDHCI_CTRL_HISPD,4,2           ; @SDHCI_CTRL_HISPD
	.comm	_SDHCI_SPEC_300,8,3             ; @SDHCI_SPEC_300
	.comm	_MMC_TIMING_UHS_SDR50,8,3       ; @MMC_TIMING_UHS_SDR50
	.comm	_MMC_TIMING_UHS_SDR104,8,3      ; @MMC_TIMING_UHS_SDR104
	.comm	_MMC_TIMING_UHS_DDR50,8,3       ; @MMC_TIMING_UHS_DDR50
	.comm	_MMC_TIMING_UHS_SDR25,8,3       ; @MMC_TIMING_UHS_SDR25
	.comm	_SDHCI_HOST_CONTROL2,4,2        ; @SDHCI_HOST_CONTROL2
	.comm	_SDHCI_CTRL_PRESET_VAL_ENABLE,4,2 ; @SDHCI_CTRL_PRESET_VAL_ENABLE
	.comm	_SDHCI_CTRL_DRV_TYPE_MASK,4,2   ; @SDHCI_CTRL_DRV_TYPE_MASK
	.comm	_MMC_SET_DRIVER_TYPE_A,8,3      ; @MMC_SET_DRIVER_TYPE_A
	.comm	_SDHCI_CTRL_DRV_TYPE_A,4,2      ; @SDHCI_CTRL_DRV_TYPE_A
	.comm	_MMC_SET_DRIVER_TYPE_C,8,3      ; @MMC_SET_DRIVER_TYPE_C
	.comm	_SDHCI_CTRL_DRV_TYPE_C,4,2      ; @SDHCI_CTRL_DRV_TYPE_C
	.comm	_SDHCI_CLOCK_CONTROL,4,2        ; @SDHCI_CLOCK_CONTROL
	.comm	_SDHCI_CLOCK_CARD_EN,4,2        ; @SDHCI_CLOCK_CARD_EN
	.comm	_SDHCI_CTRL_UHS_MASK,4,2        ; @SDHCI_CTRL_UHS_MASK
	.comm	_MMC_TIMING_UHS_SDR12,8,3       ; @MMC_TIMING_UHS_SDR12
	.comm	_SDHCI_CTRL_UHS_SDR12,4,2       ; @SDHCI_CTRL_UHS_SDR12
	.comm	_SDHCI_CTRL_UHS_SDR25,4,2       ; @SDHCI_CTRL_UHS_SDR25
	.comm	_SDHCI_CTRL_UHS_SDR50,4,2       ; @SDHCI_CTRL_UHS_SDR50
	.comm	_SDHCI_CTRL_UHS_SDR104,4,2      ; @SDHCI_CTRL_UHS_SDR104
	.comm	_SDHCI_CTRL_UHS_DDR50,4,2       ; @SDHCI_CTRL_UHS_DDR50
	.comm	_SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,4,2 ; @SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS
	.comm	_SDHCI_RESET_CMD,4,2            ; @SDHCI_RESET_CMD
	.comm	_SDHCI_RESET_DATA,4,2           ; @SDHCI_RESET_DATA
	.no_dead_strip	_sdhci_set_ios
.subsections_via_symbols
