	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function flash_upgrade
_flash_upgrade:                         ## @flash_upgrade
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %r15
	xorl	%r13d, %r13d
	testl	%esi, %esi
	movq	_FPGA_BLOCK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	cmovel	%eax, %r13d
	cmpl	$1, %esi
	movq	_SOLOS_BLOCK@GOTPCREL(%rip), %rdx
	leaq	L_.str.1(%rip), %rcx
	leaq	L_.str(%rip), %rsi
	cmoveq	%rcx, %rsi
	movl	(%rdx), %edx
	cmovel	%edx, %r13d
	cmpl	$3, %r14d
	je	LBB0_6
## %bb.1:
	cmpl	$2, %r14d
	jne	LBB0_4
## %bb.2:
	movq	(%r15), %rcx
	movq	_LEGACY_BUFFERS@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jle	LBB0_7
## %bb.3:
	leaq	L_.str.2(%rip), %rsi
	movl	%eax, %r13d
	jmp	LBB0_4
LBB0_6:
	movq	(%r15), %rax
	movq	_LEGACY_BUFFERS@GOTPCREL(%rip), %rdi
	movq	%rcx, %rsi
	movl	%edx, %r13d
	cmpq	(%rdi), %rax
	jle	LBB0_7
LBB0_4:
	movq	8(%r15), %rdx
	leaq	-48(%rbp), %rdi
	callq	_request_firmware
	testq	%rax, %rax
	je	LBB0_8
## %bb.5:
	movq	_ENOENT@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
	jmp	LBB0_23
LBB0_7:
	movq	8(%r15), %rdi
	leaq	L_.str.3(%rip), %rsi
	xorl	%ebx, %ebx
	xorl	%eax, %eax
	callq	_dev_info
	movq	_EPERM@GOTPCREL(%rip), %rax
	subl	(%rax), %ebx
	jmp	LBB0_23
LBB0_8:
	movq	8(%r15), %rdi
	leaq	L_.str.4(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_info
	movq	-48(%rbp), %rax
	movl	(%rax), %ecx
	movl	%ecx, %eax
	cltd
	idivl	%r13d
	movl	%eax, %ebx
	movq	8(%r15), %rdi
	leaq	L_.str.5(%rip), %rsi
	movl	%ecx, %edx
	xorl	%eax, %eax
	callq	_dev_info
	movq	8(%r15), %rdi
	leaq	L_.str.6(%rip), %rsi
	movl	%ebx, %edx
	xorl	%eax, %eax
	callq	_dev_info
	movq	8(%r15), %rdi
	leaq	L_.str.7(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_info
	movq	_FPGA_MODE@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rsi
	addq	16(%r15), %rsi
	movl	$1, %edi
	callq	_iowrite32
	movq	(%rbx), %rdi
	addq	16(%r15), %rdi
	callq	_ioread32
	movl	%r14d, %eax
	andl	$-3, %eax
	je	LBB0_9
## %bb.10:
	cmpl	$1, %eax
	jne	LBB0_13
## %bb.11:
	leaq	L_.str.9(%rip), %rsi
	jmp	LBB0_12
LBB0_9:
	leaq	L_.str.8(%rip), %rsi
LBB0_12:
	movq	8(%r15), %rdi
	xorl	%eax, %eax
	callq	_dev_info
LBB0_13:
	addl	%r14d, %r14d
	movq	_FLASH_MODE@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	16(%r15), %rsi
	movl	%r14d, %edi
	callq	_iowrite32
	movq	_WRITE_FLASH@GOTPCREL(%rip), %r12
	movq	(%r12), %rsi
	addq	16(%r15), %rsi
	movl	$1, %edi
	callq	_iowrite32
	movl	24(%r15), %ebx
	movq	_FLASH_BUSY@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	16(%r15), %rdi
	callq	_ioread32
	xorl	%esi, %esi
	testl	%eax, %eax
	sete	%sil
	movl	%ebx, %edi
	movq	%r12, %rbx
	callq	_wait_event
	movq	-48(%rbp), %rdi
	cmpl	$0, (%rdi)
	jle	LBB0_22
## %bb.14:
	orl	$1, %r14d
	movslq	%r13d, %rax
	movq	%rax, -64(%rbp)                 ## 8-byte Spill
	xorl	%r12d, %r12d
	movl	%r14d, -52(%rbp)                ## 4-byte Spill
	jmp	LBB0_15
	.p2align	4, 0x90
LBB0_21:                                ##   in Loop: Header=BB0_15 Depth=1
	movl	%r12d, %eax
	cltd
	idivl	%r13d
	movq	_FLASH_BLOCK@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rsi
	addq	16(%r15), %rsi
	movl	%eax, %edi
	callq	_iowrite32
	movq	_WRITE_FLASH@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rsi
	addq	16(%r15), %rsi
	movl	$1, %edi
	callq	_iowrite32
	movl	24(%r15), %r14d
	movq	_FLASH_BUSY@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	16(%r15), %rdi
	callq	_ioread32
	xorl	%esi, %esi
	testl	%eax, %eax
	sete	%sil
	movl	%r14d, %edi
	callq	_wait_event
	addq	-64(%rbp), %r12                 ## 8-byte Folded Reload
	movq	-48(%rbp), %rdi
	movslq	(%rdi), %rax
	cmpq	%rax, %r12
	movl	-52(%rbp), %r14d                ## 4-byte Reload
	jge	LBB0_22
LBB0_15:                                ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_17 Depth 2
	movq	(%rbx), %rsi
	addq	16(%r15), %rsi
	xorl	%edi, %edi
	callq	_iowrite32
	movq	_FLASH_MODE@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	16(%r15), %rsi
	movl	%r14d, %edi
	callq	_iowrite32
	testl	%r13d, %r13d
	jle	LBB0_21
## %bb.16:                              ##   in Loop: Header=BB0_15 Depth=1
	xorl	%r14d, %r14d
	jmp	LBB0_17
	.p2align	4, 0x90
LBB0_19:                                ##   in Loop: Header=BB0_17 Depth=2
	movq	%r15, %rdi
	movl	$3, %esi
	callq	_RX_BUF
	movq	%rax, %rsi
LBB0_20:                                ##   in Loop: Header=BB0_17 Depth=2
	addq	%r14, %rsi
	movl	%ebx, %edi
	callq	_iowrite32
	addq	$4, %r14
	cmpl	%r14d, %r13d
	jle	LBB0_21
LBB0_17:                                ##   Parent Loop BB0_15 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movq	-48(%rbp), %rax
	leaq	(%r12,%r14), %rdi
	addq	8(%rax), %rdi
	callq	_swahb32p
	movl	%eax, %ebx
	movq	(%r15), %rax
	movq	_LEGACY_BUFFERS@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jle	LBB0_19
## %bb.18:                              ##   in Loop: Header=BB0_17 Depth=2
	movq	_FLASH_BUF@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	jmp	LBB0_20
LBB0_22:
	callq	_release_firmware
	movq	(%rbx), %rsi
	addq	16(%r15), %rsi
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	_iowrite32
	movq	_FPGA_MODE@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	16(%r15), %rsi
	xorl	%edi, %edi
	callq	_iowrite32
	movq	_FLASH_MODE@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	16(%r15), %rsi
	xorl	%edi, %edi
	callq	_iowrite32
	movq	8(%r15), %rdi
	leaq	L_.str.10(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_info
LBB0_23:
	movl	%ebx, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"solos-FPGA.bin"

	.comm	_FPGA_BLOCK,4,2                 ## @FPGA_BLOCK
L_.str.1:                               ## @.str.1
	.asciz	"solos-Firmware.bin"

	.comm	_SOLOS_BLOCK,4,2                ## @SOLOS_BLOCK
	.comm	_LEGACY_BUFFERS,8,3             ## @LEGACY_BUFFERS
L_.str.2:                               ## @.str.2
	.asciz	"solos-db-FPGA.bin"

L_.str.3:                               ## @.str.3
	.asciz	"FPGA version doesn't support daughter board upgrades\n"

	.comm	_EPERM,4,2                      ## @EPERM
	.comm	_ENOENT,4,2                     ## @ENOENT
L_.str.4:                               ## @.str.4
	.asciz	"Flash upgrade starting\n"

L_.str.5:                               ## @.str.5
	.asciz	"Firmware size: %zd\n"

L_.str.6:                               ## @.str.6
	.asciz	"Number of blocks: %d\n"

L_.str.7:                               ## @.str.7
	.asciz	"Changing FPGA to Update mode\n"

	.comm	_FPGA_MODE,8,3                  ## @FPGA_MODE
L_.str.8:                               ## @.str.8
	.asciz	"Set FPGA Flash mode to FPGA Chip Erase\n"

L_.str.9:                               ## @.str.9
	.asciz	"Set FPGA Flash mode to Solos Chip Erase\n"

	.comm	_FLASH_MODE,8,3                 ## @FLASH_MODE
	.comm	_WRITE_FLASH,8,3                ## @WRITE_FLASH
	.comm	_FLASH_BUSY,8,3                 ## @FLASH_BUSY
	.comm	_FLASH_BUF,8,3                  ## @FLASH_BUF
	.comm	_FLASH_BLOCK,8,3                ## @FLASH_BLOCK
L_.str.10:                              ## @.str.10
	.asciz	"Returning FPGA to Data mode\n"

	.no_dead_strip	_flash_upgrade
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function flash_upgrade
_flash_upgrade:                         ; @flash_upgrade
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x8, _FPGA_BLOCK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _FPGA_BLOCK@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cmp	w1, #0
	csel	w10, w8, wzr, eq
Lloh3:
	adrp	x9, _SOLOS_BLOCK@GOTPAGE
Lloh4:
	ldr	x9, [x9, _SOLOS_BLOCK@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
Lloh6:
	adrp	x11, l_.str@PAGE
Lloh7:
	add	x11, x11, l_.str@PAGEOFF
Lloh8:
	adrp	x12, l_.str.1@PAGE
Lloh9:
	add	x12, x12, l_.str.1@PAGEOFF
	cmp	w1, #1
	csel	w22, w9, w10, eq
	csel	x1, x12, x11, eq
	cmp	w20, #3
	b.eq	LBB0_4
; %bb.1:
	cmp	w20, #2
	b.ne	LBB0_6
; %bb.2:
	ldr	x9, [x19]
Lloh10:
	adrp	x10, _LEGACY_BUFFERS@GOTPAGE
Lloh11:
	ldr	x10, [x10, _LEGACY_BUFFERS@GOTPAGEOFF]
Lloh12:
	ldr	x10, [x10]
	cmp	x9, x10
	b.le	LBB0_8
; %bb.3:
Lloh13:
	adrp	x1, l_.str.2@PAGE
Lloh14:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x22, x8
	b	LBB0_6
LBB0_4:
	ldr	x8, [x19]
Lloh15:
	adrp	x10, _LEGACY_BUFFERS@GOTPAGE
Lloh16:
	ldr	x10, [x10, _LEGACY_BUFFERS@GOTPAGEOFF]
Lloh17:
	ldr	x10, [x10]
	cmp	x8, x10
	b.le	LBB0_8
; %bb.5:
Lloh18:
	adrp	x1, l_.str.1@PAGE
Lloh19:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x22, x9
LBB0_6:
	ldr	x2, [x19, #8]
	add	x0, sp, #8
	bl	_request_firmware
	cbz	x0, LBB0_10
; %bb.7:
Lloh20:
	adrp	x8, _ENOENT@GOTPAGE
Lloh21:
	ldr	x8, [x8, _ENOENT@GOTPAGEOFF]
	b	LBB0_9
LBB0_8:
	ldr	x0, [x19, #8]
Lloh22:
	adrp	x1, l_.str.3@PAGE
Lloh23:
	add	x1, x1, l_.str.3@PAGEOFF
	bl	_dev_info
Lloh24:
	adrp	x8, _EPERM@GOTPAGE
Lloh25:
	ldr	x8, [x8, _EPERM@GOTPAGEOFF]
LBB0_9:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_26
LBB0_10:
	ldr	x0, [x19, #8]
Lloh26:
	adrp	x1, l_.str.4@PAGE
Lloh27:
	add	x1, x1, l_.str.4@PAGEOFF
	bl	_dev_info
	ldr	x8, [sp, #8]
	ldr	w8, [x8]
	ldr	x0, [x19, #8]
	sdiv	w21, w8, w22
	str	x8, [sp]
Lloh28:
	adrp	x1, l_.str.5@PAGE
Lloh29:
	add	x1, x1, l_.str.5@PAGEOFF
	bl	_dev_info
	ldr	x0, [x19, #8]
	str	x21, [sp]
Lloh30:
	adrp	x1, l_.str.6@PAGE
Lloh31:
	add	x1, x1, l_.str.6@PAGEOFF
	bl	_dev_info
	ldr	x0, [x19, #8]
Lloh32:
	adrp	x1, l_.str.7@PAGE
Lloh33:
	add	x1, x1, l_.str.7@PAGEOFF
	bl	_dev_info
	ldr	x8, [x19, #16]
Lloh34:
	adrp	x23, _FPGA_MODE@GOTPAGE
Lloh35:
	ldr	x23, [x23, _FPGA_MODE@GOTPAGEOFF]
	ldr	x9, [x23]
	add	x1, x9, x8
	mov	w0, #1
	bl	_iowrite32
	ldr	x8, [x19, #16]
	ldr	x9, [x23]
	add	x0, x9, x8
	bl	_ioread32
	ands	w8, w20, #0xfffffffd
	b.eq	LBB0_13
; %bb.11:
	cmp	w8, #1
	b.ne	LBB0_15
; %bb.12:
Lloh36:
	adrp	x1, l_.str.9@PAGE
Lloh37:
	add	x1, x1, l_.str.9@PAGEOFF
	b	LBB0_14
LBB0_13:
Lloh38:
	adrp	x1, l_.str.8@PAGE
Lloh39:
	add	x1, x1, l_.str.8@PAGEOFF
LBB0_14:
	ldr	x0, [x19, #8]
	bl	_dev_info
LBB0_15:
	lsl	w20, w20, #1
	ldr	x8, [x19, #16]
Lloh40:
	adrp	x9, _FLASH_MODE@GOTPAGE
Lloh41:
	ldr	x9, [x9, _FLASH_MODE@GOTPAGEOFF]
Lloh42:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	x0, x20
	bl	_iowrite32
	ldr	x8, [x19, #16]
Lloh43:
	adrp	x25, _WRITE_FLASH@GOTPAGE
Lloh44:
	ldr	x25, [x25, _WRITE_FLASH@GOTPAGEOFF]
	ldr	x9, [x25]
	add	x1, x9, x8
	mov	w0, #1
	bl	_iowrite32
	ldr	w21, [x19, #24]
	ldr	x8, [x19, #16]
Lloh45:
	adrp	x9, _FLASH_BUSY@GOTPAGE
Lloh46:
	ldr	x9, [x9, _FLASH_BUSY@GOTPAGEOFF]
Lloh47:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_ioread32
	cmp	w0, #0
	cset	w1, eq
	mov	x0, x21
	bl	_wait_event
	ldr	x0, [sp, #8]
	ldr	w8, [x0]
	cmp	w8, #1
	b.lt	LBB0_25
; %bb.16:
	mov	x27, #0
	orr	w20, w20, #0x1
	sxtw	x28, w22
Lloh48:
	adrp	x23, _LEGACY_BUFFERS@GOTPAGE
Lloh49:
	ldr	x23, [x23, _LEGACY_BUFFERS@GOTPAGEOFF]
Lloh50:
	adrp	x24, _FLASH_BUF@GOTPAGE
Lloh51:
	ldr	x24, [x24, _FLASH_BUF@GOTPAGEOFF]
	b	LBB0_18
LBB0_17:                                ;   in Loop: Header=BB0_18 Depth=1
	ldr	x8, [x19, #16]
Lloh52:
	adrp	x9, _FLASH_BLOCK@GOTPAGE
Lloh53:
	ldr	x9, [x9, _FLASH_BLOCK@GOTPAGEOFF]
Lloh54:
	ldr	x9, [x9]
	add	x1, x9, x8
	sdiv	w0, w27, w22
	bl	_iowrite32
	ldr	x8, [x19, #16]
	ldr	x9, [x25]
	add	x1, x9, x8
	mov	w0, #1
	bl	_iowrite32
	ldr	w21, [x19, #24]
	ldr	x8, [x19, #16]
Lloh55:
	adrp	x9, _FLASH_BUSY@GOTPAGE
Lloh56:
	ldr	x9, [x9, _FLASH_BUSY@GOTPAGEOFF]
Lloh57:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_ioread32
	cmp	w0, #0
	cset	w1, eq
	mov	x0, x21
	bl	_wait_event
	ldr	x0, [sp, #8]
	ldrsw	x8, [x0]
	add	x27, x27, x28
	cmp	x27, x8
	b.ge	LBB0_24
LBB0_18:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_22 Depth 2
	ldr	x8, [x19, #16]
	ldr	x9, [x25]
	add	x1, x9, x8
	mov	w0, #0
	bl	_iowrite32
	ldr	x8, [x19, #16]
Lloh58:
	adrp	x9, _FLASH_MODE@GOTPAGE
Lloh59:
	ldr	x9, [x9, _FLASH_MODE@GOTPAGEOFF]
Lloh60:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	x0, x20
	bl	_iowrite32
	cmp	w22, #1
	b.lt	LBB0_17
; %bb.19:                               ;   in Loop: Header=BB0_18 Depth=1
	mov	x26, #0
	b	LBB0_22
LBB0_20:                                ;   in Loop: Header=BB0_22 Depth=2
	mov	x0, x19
	mov	w1, #3
	bl	_RX_BUF
LBB0_21:                                ;   in Loop: Header=BB0_22 Depth=2
	add	x1, x0, x26
	mov	x0, x21
	bl	_iowrite32
	add	x26, x26, #4
	cmp	w22, w26
	b.le	LBB0_17
LBB0_22:                                ;   Parent Loop BB0_18 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ldr	x8, [sp, #8]
	ldr	x8, [x8, #8]
	add	x9, x27, x26
	add	x0, x9, x8
	bl	_swahb32p
	mov	x21, x0
	ldr	x8, [x19]
	ldr	x9, [x23]
	cmp	x8, x9
	b.le	LBB0_20
; %bb.23:                               ;   in Loop: Header=BB0_22 Depth=2
	ldr	x0, [x24]
	b	LBB0_21
LBB0_24:
Lloh61:
	adrp	x23, _FPGA_MODE@GOTPAGE
Lloh62:
	ldr	x23, [x23, _FPGA_MODE@GOTPAGEOFF]
LBB0_25:
	bl	_release_firmware
	ldr	x8, [x19, #16]
	ldr	x9, [x25]
	add	x1, x9, x8
	mov	w0, #0
	bl	_iowrite32
	ldr	x8, [x19, #16]
	ldr	x9, [x23]
	add	x1, x9, x8
	mov	w0, #0
	bl	_iowrite32
	ldr	x8, [x19, #16]
Lloh63:
	adrp	x9, _FLASH_MODE@GOTPAGE
Lloh64:
	ldr	x9, [x9, _FLASH_MODE@GOTPAGEOFF]
Lloh65:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #0
	bl	_iowrite32
	ldr	x0, [x19, #8]
Lloh66:
	adrp	x1, l_.str.10@PAGE
Lloh67:
	add	x1, x1, l_.str.10@PAGEOFF
	bl	_dev_info
	mov	w0, #0
LBB0_26:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpAdd	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpAdd	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpAdd	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpAdd	Lloh32, Lloh33
	.loh AdrpAdd	Lloh30, Lloh31
	.loh AdrpAdd	Lloh28, Lloh29
	.loh AdrpAdd	Lloh26, Lloh27
	.loh AdrpAdd	Lloh36, Lloh37
	.loh AdrpAdd	Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpAdd	Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"solos-FPGA.bin"

	.comm	_FPGA_BLOCK,4,2                 ; @FPGA_BLOCK
l_.str.1:                               ; @.str.1
	.asciz	"solos-Firmware.bin"

	.comm	_SOLOS_BLOCK,4,2                ; @SOLOS_BLOCK
	.comm	_LEGACY_BUFFERS,8,3             ; @LEGACY_BUFFERS
l_.str.2:                               ; @.str.2
	.asciz	"solos-db-FPGA.bin"

l_.str.3:                               ; @.str.3
	.asciz	"FPGA version doesn't support daughter board upgrades\n"

	.comm	_EPERM,4,2                      ; @EPERM
	.comm	_ENOENT,4,2                     ; @ENOENT
l_.str.4:                               ; @.str.4
	.asciz	"Flash upgrade starting\n"

l_.str.5:                               ; @.str.5
	.asciz	"Firmware size: %zd\n"

l_.str.6:                               ; @.str.6
	.asciz	"Number of blocks: %d\n"

l_.str.7:                               ; @.str.7
	.asciz	"Changing FPGA to Update mode\n"

	.comm	_FPGA_MODE,8,3                  ; @FPGA_MODE
l_.str.8:                               ; @.str.8
	.asciz	"Set FPGA Flash mode to FPGA Chip Erase\n"

l_.str.9:                               ; @.str.9
	.asciz	"Set FPGA Flash mode to Solos Chip Erase\n"

	.comm	_FLASH_MODE,8,3                 ; @FLASH_MODE
	.comm	_WRITE_FLASH,8,3                ; @WRITE_FLASH
	.comm	_FLASH_BUSY,8,3                 ; @FLASH_BUSY
	.comm	_FLASH_BUF,8,3                  ; @FLASH_BUF
	.comm	_FLASH_BLOCK,8,3                ; @FLASH_BLOCK
l_.str.10:                              ; @.str.10
	.asciz	"Returning FPGA to Data mode\n"

	.no_dead_strip	_flash_upgrade
.subsections_via_symbols
