	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_t3_intr_enable                 ## -- Begin function t3_intr_enable
	.p2align	4, 0x90
_t3_intr_enable:                        ## @t3_intr_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	movq	_PL_INTR_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, (%rdi)
	leaq	_t3_intr_enable.intr_en_avp(%rip), %r14
	movq	%r14, %rdi
	callq	_ARRAY_SIZE
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movl	%eax, %edx
	xorl	%ecx, %ecx
	callq	_t3_write_regs
	movq	_A_TP_INT_ENABLE@GOTPCREL(%rip), %rax
	movq	8(%rbx), %rcx
	movq	_T3_REV_C@GOTPCREL(%rip), %rsi
	xorl	%edx, %edx
	cmpq	(%rsi), %rcx
	movl	(%rax), %esi
	setl	%dl
	shll	$24, %edx
	orl	$46137343, %edx                 ## imm = 0x2BFFFFF
	movq	%rbx, %rdi
	callq	_t3_write_reg
	cmpq	$0, 8(%rbx)
	movq	_A_CPL_INTR_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_CPLSW_INTR_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	jle	LBB0_2
## %bb.1:
	movq	_F_CIM_OVFL_ERROR@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_t3_write_reg
	movq	_A_ULPTX_INT_ENABLE@GOTPCREL(%rip), %rax
	movq	_ULPTX_INTR_MASK@GOTPCREL(%rip), %rcx
	movq	_F_PBL_BOUND_ERR_CH0@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	movl	(%rax), %esi
	movq	_F_PBL_BOUND_ERR_CH1@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	jmp	LBB0_3
LBB0_2:
	movq	%rbx, %rdi
	callq	_t3_write_reg
	movq	_A_ULPTX_INT_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_ULPTX_INTR_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
LBB0_3:
	movq	%rbx, %rdi
	callq	_t3_write_reg
	movq	_A_T3DBG_INT_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	%rbx, %rdi
	callq	_calc_gpio_intr
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_t3_write_reg
	movq	%rbx, %rdi
	callq	_is_pcie
	testq	%rax, %rax
	movq	_A_PCIE_INT_ENABLE@GOTPCREL(%rip), %rax
	cmoveq	_A_PCIX_INT_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PCIE_INTR_MASK@GOTPCREL(%rip), %rax
	cmoveq	_PCIX_INTR_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_t3_write_reg
	movq	_A_PL_INT_ENABLE0@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movl	(%rbx), %edx
	movq	%rbx, %rdi
	callq	_t3_write_reg
	movl	(%r14), %esi
	movq	%rbx, %rdi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_t3_read_reg                    ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__const
	.p2align	4                               ## @t3_intr_enable.intr_en_avp
_t3_intr_enable.intr_en_avp:
	.long	140                             ## 0x8c
	.space	4
	.quad	129                             ## 0x81
	.long	144                             ## 0x90
	.space	4
	.quad	135                             ## 0x87
	.long	143                             ## 0x8f
	.space	4
	.quad	135                             ## 0x87
	.long	146                             ## 0x92
	.space	4
	.quad	135                             ## 0x87
	.long	145                             ## 0x91
	.space	4
	.quad	137                             ## 0x89
	.long	139                             ## 0x8b
	.space	4
	.quad	128                             ## 0x80
	.long	141                             ## 0x8d
	.space	4
	.quad	130                             ## 0x82
	.long	142                             ## 0x8e
	.space	4
	.quad	131                             ## 0x83
	.long	146                             ## 0x92
	.space	4
	.quad	138                             ## 0x8a
	.long	143                             ## 0x8f
	.space	4
	.quad	132                             ## 0x84

	.comm	_PL_INTR_MASK,4,2               ## @PL_INTR_MASK
	.comm	_A_TP_INT_ENABLE,4,2            ## @A_TP_INT_ENABLE
	.comm	_T3_REV_C,8,3                   ## @T3_REV_C
	.comm	_A_CPL_INTR_ENABLE,4,2          ## @A_CPL_INTR_ENABLE
	.comm	_CPLSW_INTR_MASK,4,2            ## @CPLSW_INTR_MASK
	.comm	_F_CIM_OVFL_ERROR,4,2           ## @F_CIM_OVFL_ERROR
	.comm	_A_ULPTX_INT_ENABLE,4,2         ## @A_ULPTX_INT_ENABLE
	.comm	_ULPTX_INTR_MASK,4,2            ## @ULPTX_INTR_MASK
	.comm	_F_PBL_BOUND_ERR_CH0,4,2        ## @F_PBL_BOUND_ERR_CH0
	.comm	_F_PBL_BOUND_ERR_CH1,4,2        ## @F_PBL_BOUND_ERR_CH1
	.comm	_A_T3DBG_INT_ENABLE,4,2         ## @A_T3DBG_INT_ENABLE
	.comm	_A_PCIE_INT_ENABLE,4,2          ## @A_PCIE_INT_ENABLE
	.comm	_PCIE_INTR_MASK,4,2             ## @PCIE_INTR_MASK
	.comm	_A_PCIX_INT_ENABLE,4,2          ## @A_PCIX_INT_ENABLE
	.comm	_PCIX_INTR_MASK,4,2             ## @PCIX_INTR_MASK
	.comm	_A_PL_INT_ENABLE0,4,2           ## @A_PL_INT_ENABLE0
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_t3_intr_enable                 ; -- Begin function t3_intr_enable
	.p2align	2
_t3_intr_enable:                        ; @t3_intr_enable
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
Lloh0:
	adrp	x8, _PL_INTR_MASK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PL_INTR_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	str	w8, [x0]
Lloh3:
	adrp	x20, _t3_intr_enable.intr_en_avp@PAGE
Lloh4:
	add	x20, x20, _t3_intr_enable.intr_en_avp@PAGEOFF
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	mov	w3, #0
	bl	_t3_write_regs
Lloh5:
	adrp	x8, _A_TP_INT_ENABLE@GOTPAGE
Lloh6:
	ldr	x8, [x8, _A_TP_INT_ENABLE@GOTPAGEOFF]
Lloh7:
	ldr	w1, [x8]
Lloh8:
	adrp	x8, _T3_REV_C@GOTPAGE
Lloh9:
	ldr	x8, [x8, _T3_REV_C@GOTPAGEOFF]
	ldr	x9, [x19, #8]
Lloh10:
	ldr	x8, [x8]
	cmp	x9, x8
	mov	w8, #46137343
	mov	w9, #62914559
	csel	w2, w9, w8, lt
	mov	x0, x19
	bl	_t3_write_reg
Lloh11:
	adrp	x8, _A_CPL_INTR_ENABLE@GOTPAGE
Lloh12:
	ldr	x8, [x8, _A_CPL_INTR_ENABLE@GOTPAGEOFF]
	ldr	x9, [x19, #8]
Lloh13:
	ldr	w1, [x8]
Lloh14:
	adrp	x8, _CPLSW_INTR_MASK@GOTPAGE
Lloh15:
	ldr	x8, [x8, _CPLSW_INTR_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	cmp	x9, #1
	b.lt	LBB0_2
; %bb.1:
Lloh17:
	adrp	x8, _F_CIM_OVFL_ERROR@GOTPAGE
Lloh18:
	ldr	x8, [x8, _F_CIM_OVFL_ERROR@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
	orr	w2, w8, w2
	mov	x0, x19
	bl	_t3_write_reg
Lloh20:
	adrp	x8, _A_ULPTX_INT_ENABLE@GOTPAGE
Lloh21:
	ldr	x8, [x8, _A_ULPTX_INT_ENABLE@GOTPAGEOFF]
Lloh22:
	ldr	w1, [x8]
Lloh23:
	adrp	x8, _ULPTX_INTR_MASK@GOTPAGE
Lloh24:
	ldr	x8, [x8, _ULPTX_INTR_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
Lloh26:
	adrp	x9, _F_PBL_BOUND_ERR_CH0@GOTPAGE
Lloh27:
	ldr	x9, [x9, _F_PBL_BOUND_ERR_CH0@GOTPAGEOFF]
Lloh28:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh29:
	adrp	x9, _F_PBL_BOUND_ERR_CH1@GOTPAGE
Lloh30:
	ldr	x9, [x9, _F_PBL_BOUND_ERR_CH1@GOTPAGEOFF]
Lloh31:
	ldr	w9, [x9]
	orr	w2, w8, w9
	b	LBB0_3
LBB0_2:
	mov	x0, x19
	bl	_t3_write_reg
Lloh32:
	adrp	x8, _A_ULPTX_INT_ENABLE@GOTPAGE
Lloh33:
	ldr	x8, [x8, _A_ULPTX_INT_ENABLE@GOTPAGEOFF]
Lloh34:
	ldr	w1, [x8]
Lloh35:
	adrp	x8, _ULPTX_INTR_MASK@GOTPAGE
Lloh36:
	ldr	x8, [x8, _ULPTX_INTR_MASK@GOTPAGEOFF]
Lloh37:
	ldr	w2, [x8]
LBB0_3:
	mov	x0, x19
	bl	_t3_write_reg
Lloh38:
	adrp	x8, _A_T3DBG_INT_ENABLE@GOTPAGE
Lloh39:
	ldr	x8, [x8, _A_T3DBG_INT_ENABLE@GOTPAGEOFF]
Lloh40:
	ldr	w20, [x8]
	mov	x0, x19
	bl	_calc_gpio_intr
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_t3_write_reg
	mov	x0, x19
	bl	_is_pcie
Lloh41:
	adrp	x8, _A_PCIX_INT_ENABLE@GOTPAGE
Lloh42:
	ldr	x8, [x8, _A_PCIX_INT_ENABLE@GOTPAGEOFF]
Lloh43:
	adrp	x9, _A_PCIE_INT_ENABLE@GOTPAGE
Lloh44:
	ldr	x9, [x9, _A_PCIE_INT_ENABLE@GOTPAGEOFF]
	cmp	x0, #0
	csel	x8, x8, x9, eq
	ldr	w1, [x8]
Lloh45:
	adrp	x8, _PCIX_INTR_MASK@GOTPAGE
Lloh46:
	ldr	x8, [x8, _PCIX_INTR_MASK@GOTPAGEOFF]
Lloh47:
	adrp	x9, _PCIE_INTR_MASK@GOTPAGE
Lloh48:
	ldr	x9, [x9, _PCIE_INTR_MASK@GOTPAGEOFF]
	csel	x8, x8, x9, eq
	ldr	w2, [x8]
	mov	x0, x19
	bl	_t3_write_reg
Lloh49:
	adrp	x20, _A_PL_INT_ENABLE0@GOTPAGE
Lloh50:
	ldr	x20, [x20, _A_PL_INT_ENABLE0@GOTPAGEOFF]
	ldr	w1, [x20]
	ldr	w2, [x19]
	mov	x0, x19
	bl	_t3_write_reg
	ldr	w1, [x20]
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_t3_read_reg
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__const
	.p2align	3                               ; @t3_intr_enable.intr_en_avp
_t3_intr_enable.intr_en_avp:
	.long	140                             ; 0x8c
	.space	4
	.quad	129                             ; 0x81
	.long	144                             ; 0x90
	.space	4
	.quad	135                             ; 0x87
	.long	143                             ; 0x8f
	.space	4
	.quad	135                             ; 0x87
	.long	146                             ; 0x92
	.space	4
	.quad	135                             ; 0x87
	.long	145                             ; 0x91
	.space	4
	.quad	137                             ; 0x89
	.long	139                             ; 0x8b
	.space	4
	.quad	128                             ; 0x80
	.long	141                             ; 0x8d
	.space	4
	.quad	130                             ; 0x82
	.long	142                             ; 0x8e
	.space	4
	.quad	131                             ; 0x83
	.long	146                             ; 0x92
	.space	4
	.quad	138                             ; 0x8a
	.long	143                             ; 0x8f
	.space	4
	.quad	132                             ; 0x84

	.comm	_PL_INTR_MASK,4,2               ; @PL_INTR_MASK
	.comm	_A_TP_INT_ENABLE,4,2            ; @A_TP_INT_ENABLE
	.comm	_T3_REV_C,8,3                   ; @T3_REV_C
	.comm	_A_CPL_INTR_ENABLE,4,2          ; @A_CPL_INTR_ENABLE
	.comm	_CPLSW_INTR_MASK,4,2            ; @CPLSW_INTR_MASK
	.comm	_F_CIM_OVFL_ERROR,4,2           ; @F_CIM_OVFL_ERROR
	.comm	_A_ULPTX_INT_ENABLE,4,2         ; @A_ULPTX_INT_ENABLE
	.comm	_ULPTX_INTR_MASK,4,2            ; @ULPTX_INTR_MASK
	.comm	_F_PBL_BOUND_ERR_CH0,4,2        ; @F_PBL_BOUND_ERR_CH0
	.comm	_F_PBL_BOUND_ERR_CH1,4,2        ; @F_PBL_BOUND_ERR_CH1
	.comm	_A_T3DBG_INT_ENABLE,4,2         ; @A_T3DBG_INT_ENABLE
	.comm	_A_PCIE_INT_ENABLE,4,2          ; @A_PCIE_INT_ENABLE
	.comm	_PCIE_INTR_MASK,4,2             ; @PCIE_INTR_MASK
	.comm	_A_PCIX_INT_ENABLE,4,2          ; @A_PCIX_INT_ENABLE
	.comm	_PCIX_INTR_MASK,4,2             ; @PCIX_INTR_MASK
	.comm	_A_PL_INT_ENABLE0,4,2           ; @A_PL_INT_ENABLE0
.subsections_via_symbols
