	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_write_agp_base          ## -- Begin function radeon_write_agp_base
	.p2align	4, 0x90
_radeon_write_agp_base:                 ## @radeon_write_agp_base
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r13d
	movq	%rdi, %r15
	movl	%esi, %edi
	callq	_upper_32_bits
	movl	%eax, %r14d
	movl	%r13d, %esi
	sarl	$22, %esi
	movq	_RADEON_FAMILY_MASK@GOTPCREL(%rip), %r12
	movl	(%r12), %ebx
	andl	(%r15), %ebx
	andl	$262143, %esi                   ## imm = 0x3FFFF
	movq	_CHIP_RV770@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	jge	LBB0_1
## %bb.4:
	movq	_CHIP_R600@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	jge	LBB0_5
## %bb.6:
	movq	_CHIP_RV515@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	cmpl	%eax, %ebx
	jne	LBB0_9
## %bb.7:
	movq	_RV515_MC_AGP_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r13d, %esi
	callq	_R500_WRITE_MCIND
	movq	_RV515_MC_AGP_BASE_2@GOTPCREL(%rip), %rax
LBB0_8:
	movl	(%rax), %edi
	movl	%r14d, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_R500_WRITE_MCIND               ## TAILCALL
LBB0_1:
	movq	_R700_MC_VM_AGP_BASE@GOTPCREL(%rip), %rax
	jmp	LBB0_2
LBB0_5:
	movq	_R600_MC_VM_AGP_BASE@GOTPCREL(%rip), %rax
LBB0_2:
	movl	(%rax), %edi
LBB0_3:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_RADEON_WRITE                   ## TAILCALL
LBB0_9:
	movq	_CHIP_RS690@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %ebx
	je	LBB0_21
## %bb.10:
	movq	_CHIP_RS740@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %ebx
	je	LBB0_21
## %bb.11:
	movq	_CHIP_RS600@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %ebx
	jne	LBB0_12
## %bb.22:
	movq	_RS600_AGP_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r13d, %esi
	callq	_RS600_WRITE_MCIND
	movq	_RS600_AGP_BASE_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_RS600_WRITE_MCIND              ## TAILCALL
LBB0_21:
	movq	_RS690_MC_AGP_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r13d, %esi
	callq	_RS690_WRITE_MCIND
	movq	_RS690_MC_AGP_BASE_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_RS690_WRITE_MCIND              ## TAILCALL
LBB0_12:
	cmpl	%eax, %ebx
	jle	LBB0_14
## %bb.13:
	movq	_R520_MC_AGP_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r13d, %esi
	callq	_R500_WRITE_MCIND
	movq	_R520_MC_AGP_BASE_2@GOTPCREL(%rip), %rax
	jmp	LBB0_8
LBB0_14:
	movq	_CHIP_RS400@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_CHIP_RS480@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	_RADEON_AGP_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r13d, %esi
	callq	_RADEON_WRITE
	cmpl	-48(%rbp), %ebx                 ## 4-byte Folded Reload
	je	LBB0_16
## %bb.15:
	cmpl	-44(%rbp), %ebx                 ## 4-byte Folded Reload
	je	LBB0_16
## %bb.18:
	movl	(%r12), %eax
	andl	(%r15), %eax
	movq	_CHIP_R200@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jge	LBB0_19
## %bb.20:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_16:
	movq	_RS480_AGP_BASE_2@GOTPCREL(%rip), %rax
	jmp	LBB0_17
LBB0_19:
	movq	_RADEON_AGP_BASE_2@GOTPCREL(%rip), %rax
LBB0_17:
	movl	(%rax), %edi
	movl	%r14d, %esi
	jmp	LBB0_3
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_FAMILY_MASK,4,2         ## @RADEON_FAMILY_MASK
	.comm	_CHIP_RV770,4,2                 ## @CHIP_RV770
	.comm	_R700_MC_VM_AGP_BASE,4,2        ## @R700_MC_VM_AGP_BASE
	.comm	_CHIP_R600,4,2                  ## @CHIP_R600
	.comm	_R600_MC_VM_AGP_BASE,4,2        ## @R600_MC_VM_AGP_BASE
	.comm	_CHIP_RV515,4,2                 ## @CHIP_RV515
	.comm	_RV515_MC_AGP_BASE,4,2          ## @RV515_MC_AGP_BASE
	.comm	_RV515_MC_AGP_BASE_2,4,2        ## @RV515_MC_AGP_BASE_2
	.comm	_CHIP_RS690,4,2                 ## @CHIP_RS690
	.comm	_CHIP_RS740,4,2                 ## @CHIP_RS740
	.comm	_RS690_MC_AGP_BASE,4,2          ## @RS690_MC_AGP_BASE
	.comm	_RS690_MC_AGP_BASE_2,4,2        ## @RS690_MC_AGP_BASE_2
	.comm	_CHIP_RS600,4,2                 ## @CHIP_RS600
	.comm	_RS600_AGP_BASE,4,2             ## @RS600_AGP_BASE
	.comm	_RS600_AGP_BASE_2,4,2           ## @RS600_AGP_BASE_2
	.comm	_R520_MC_AGP_BASE,4,2           ## @R520_MC_AGP_BASE
	.comm	_R520_MC_AGP_BASE_2,4,2         ## @R520_MC_AGP_BASE_2
	.comm	_CHIP_RS400,4,2                 ## @CHIP_RS400
	.comm	_CHIP_RS480,4,2                 ## @CHIP_RS480
	.comm	_RADEON_AGP_BASE,4,2            ## @RADEON_AGP_BASE
	.comm	_RS480_AGP_BASE_2,4,2           ## @RS480_AGP_BASE_2
	.comm	_CHIP_R200,4,2                  ## @CHIP_R200
	.comm	_RADEON_AGP_BASE_2,4,2          ## @RADEON_AGP_BASE_2
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_write_agp_base          ; -- Begin function radeon_write_agp_base
	.p2align	2
_radeon_write_agp_base:                 ; @radeon_write_agp_base
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x1
	mov	x21, x0
	mov	x0, x1
	bl	_upper_32_bits
	asr	w8, w20, #22
	and	w1, w8, #0x3ffff
	ldr	w8, [x21]
Lloh0:
	adrp	x22, _RADEON_FAMILY_MASK@GOTPAGE
Lloh1:
	ldr	x22, [x22, _RADEON_FAMILY_MASK@GOTPAGEOFF]
	ldr	w9, [x22]
	and	w23, w9, w8
Lloh2:
	adrp	x8, _CHIP_RV770@GOTPAGE
Lloh3:
	ldr	x8, [x8, _CHIP_RV770@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	cmp	w23, w8
	b.ge	LBB0_5
; %bb.1:
Lloh5:
	adrp	x8, _CHIP_R600@GOTPAGE
Lloh6:
	ldr	x8, [x8, _CHIP_R600@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	cmp	w23, w8
	b.ge	LBB0_6
; %bb.2:
	mov	x19, x0
Lloh8:
	adrp	x8, _CHIP_RV515@GOTPAGE
Lloh9:
	ldr	x8, [x8, _CHIP_RV515@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	cmp	w23, w8
	b.ne	LBB0_9
; %bb.3:
Lloh11:
	adrp	x8, _RV515_MC_AGP_BASE@GOTPAGE
Lloh12:
	ldr	x8, [x8, _RV515_MC_AGP_BASE@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_R500_WRITE_MCIND
Lloh14:
	adrp	x8, _RV515_MC_AGP_BASE_2@GOTPAGE
Lloh15:
	ldr	x8, [x8, _RV515_MC_AGP_BASE_2@GOTPAGEOFF]
LBB0_4:
	ldr	w0, [x8]
	mov	x1, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_R500_WRITE_MCIND
LBB0_5:
Lloh16:
	adrp	x8, _R700_MC_VM_AGP_BASE@GOTPAGE
Lloh17:
	ldr	x8, [x8, _R700_MC_VM_AGP_BASE@GOTPAGEOFF]
	b	LBB0_7
LBB0_6:
Lloh18:
	adrp	x8, _R600_MC_VM_AGP_BASE@GOTPAGE
Lloh19:
	ldr	x8, [x8, _R600_MC_VM_AGP_BASE@GOTPAGEOFF]
LBB0_7:
	ldr	w0, [x8]
LBB0_8:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_RADEON_WRITE
LBB0_9:
Lloh20:
	adrp	x9, _CHIP_RS690@GOTPAGE
Lloh21:
	ldr	x9, [x9, _CHIP_RS690@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
Lloh23:
	adrp	x10, _CHIP_RS740@GOTPAGE
Lloh24:
	ldr	x10, [x10, _CHIP_RS740@GOTPAGEOFF]
Lloh25:
	ldr	w10, [x10]
	cmp	w23, w9
	ccmp	w23, w10, #4, ne
	b.ne	LBB0_11
; %bb.10:
Lloh26:
	adrp	x8, _RS690_MC_AGP_BASE@GOTPAGE
Lloh27:
	ldr	x8, [x8, _RS690_MC_AGP_BASE@GOTPAGEOFF]
Lloh28:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_RS690_WRITE_MCIND
Lloh29:
	adrp	x8, _RS690_MC_AGP_BASE_2@GOTPAGE
Lloh30:
	ldr	x8, [x8, _RS690_MC_AGP_BASE_2@GOTPAGEOFF]
Lloh31:
	ldr	w0, [x8]
	mov	x1, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_RS690_WRITE_MCIND
LBB0_11:
Lloh32:
	adrp	x9, _CHIP_RS600@GOTPAGE
Lloh33:
	ldr	x9, [x9, _CHIP_RS600@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	cmp	w23, w9
	b.ne	LBB0_13
; %bb.12:
Lloh35:
	adrp	x8, _RS600_AGP_BASE@GOTPAGE
Lloh36:
	ldr	x8, [x8, _RS600_AGP_BASE@GOTPAGEOFF]
Lloh37:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_RS600_WRITE_MCIND
Lloh38:
	adrp	x8, _RS600_AGP_BASE_2@GOTPAGE
Lloh39:
	ldr	x8, [x8, _RS600_AGP_BASE_2@GOTPAGEOFF]
Lloh40:
	ldr	w0, [x8]
	mov	x1, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_RS600_WRITE_MCIND
LBB0_13:
	cmp	w23, w8
	b.le	LBB0_15
; %bb.14:
Lloh41:
	adrp	x8, _R520_MC_AGP_BASE@GOTPAGE
Lloh42:
	ldr	x8, [x8, _R520_MC_AGP_BASE@GOTPAGEOFF]
Lloh43:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_R500_WRITE_MCIND
Lloh44:
	adrp	x8, _R520_MC_AGP_BASE_2@GOTPAGE
Lloh45:
	ldr	x8, [x8, _R520_MC_AGP_BASE_2@GOTPAGEOFF]
	b	LBB0_4
LBB0_15:
Lloh46:
	adrp	x8, _CHIP_RS400@GOTPAGE
Lloh47:
	ldr	x8, [x8, _CHIP_RS400@GOTPAGEOFF]
Lloh48:
	ldr	w24, [x8]
Lloh49:
	adrp	x8, _CHIP_RS480@GOTPAGE
Lloh50:
	ldr	x8, [x8, _CHIP_RS480@GOTPAGEOFF]
Lloh51:
	ldr	w25, [x8]
Lloh52:
	adrp	x8, _RADEON_AGP_BASE@GOTPAGE
Lloh53:
	ldr	x8, [x8, _RADEON_AGP_BASE@GOTPAGEOFF]
Lloh54:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_RADEON_WRITE
	cmp	w23, w24
	ccmp	w23, w25, #4, ne
	b.ne	LBB0_17
; %bb.16:
Lloh55:
	adrp	x8, _RS480_AGP_BASE_2@GOTPAGE
Lloh56:
	ldr	x8, [x8, _RS480_AGP_BASE_2@GOTPAGEOFF]
	b	LBB0_20
LBB0_17:
	ldr	w8, [x21]
	ldr	w9, [x22]
	and	w8, w9, w8
Lloh57:
	adrp	x9, _CHIP_R200@GOTPAGE
Lloh58:
	ldr	x9, [x9, _CHIP_R200@GOTPAGEOFF]
Lloh59:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ge	LBB0_19
; %bb.18:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_19:
Lloh60:
	adrp	x8, _RADEON_AGP_BASE_2@GOTPAGE
Lloh61:
	ldr	x8, [x8, _RADEON_AGP_BASE_2@GOTPAGEOFF]
LBB0_20:
	ldr	w0, [x8]
	mov	x1, x19
	b	LBB0_8
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGot	Lloh60, Lloh61
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_FAMILY_MASK,4,2         ; @RADEON_FAMILY_MASK
	.comm	_CHIP_RV770,4,2                 ; @CHIP_RV770
	.comm	_R700_MC_VM_AGP_BASE,4,2        ; @R700_MC_VM_AGP_BASE
	.comm	_CHIP_R600,4,2                  ; @CHIP_R600
	.comm	_R600_MC_VM_AGP_BASE,4,2        ; @R600_MC_VM_AGP_BASE
	.comm	_CHIP_RV515,4,2                 ; @CHIP_RV515
	.comm	_RV515_MC_AGP_BASE,4,2          ; @RV515_MC_AGP_BASE
	.comm	_RV515_MC_AGP_BASE_2,4,2        ; @RV515_MC_AGP_BASE_2
	.comm	_CHIP_RS690,4,2                 ; @CHIP_RS690
	.comm	_CHIP_RS740,4,2                 ; @CHIP_RS740
	.comm	_RS690_MC_AGP_BASE,4,2          ; @RS690_MC_AGP_BASE
	.comm	_RS690_MC_AGP_BASE_2,4,2        ; @RS690_MC_AGP_BASE_2
	.comm	_CHIP_RS600,4,2                 ; @CHIP_RS600
	.comm	_RS600_AGP_BASE,4,2             ; @RS600_AGP_BASE
	.comm	_RS600_AGP_BASE_2,4,2           ; @RS600_AGP_BASE_2
	.comm	_R520_MC_AGP_BASE,4,2           ; @R520_MC_AGP_BASE
	.comm	_R520_MC_AGP_BASE_2,4,2         ; @R520_MC_AGP_BASE_2
	.comm	_CHIP_RS400,4,2                 ; @CHIP_RS400
	.comm	_CHIP_RS480,4,2                 ; @CHIP_RS480
	.comm	_RADEON_AGP_BASE,4,2            ; @RADEON_AGP_BASE
	.comm	_RS480_AGP_BASE_2,4,2           ; @RS480_AGP_BASE_2
	.comm	_CHIP_R200,4,2                  ; @CHIP_R200
	.comm	_RADEON_AGP_BASE_2,4,2          ; @RADEON_AGP_BASE_2
.subsections_via_symbols
