	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_apply_surface_regs
_radeon_apply_surface_regs:             ## @radeon_apply_surface_regs
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	cmpl	$0, 8(%rsi)
	je	LBB0_1
## %bb.2:
	movq	%rsi, %r14
	movl	%edi, %ebx
	movq	%rsi, %rdi
	callq	_radeon_do_cp_idle
	movq	_RADEON_SURFACE0_INFO@GOTPCREL(%rip), %rax
	movslq	%ebx, %rcx
	shll	$4, %ebx
	movslq	%ebx, %rbx
	movq	(%rax), %rdi
	addq	%rbx, %rdi
	movq	(%r14), %rax
	shlq	$2, %rcx
	leaq	(%rcx,%rcx,2), %r15
	movl	8(%rax,%r15), %esi
	callq	_RADEON_WRITE
	movq	_RADEON_SURFACE0_LOWER_BOUND@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	%rbx, %rdi
	movq	(%r14), %rax
	movl	4(%rax,%r15), %esi
	callq	_RADEON_WRITE
	movq	_RADEON_SURFACE0_UPPER_BOUND@GOTPCREL(%rip), %rax
	addq	(%rax), %rbx
	movq	(%r14), %rax
	movl	(%rax,%r15), %esi
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_RADEON_WRITE                   ## TAILCALL
LBB0_1:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_SURFACE0_INFO,8,3       ## @RADEON_SURFACE0_INFO
	.comm	_RADEON_SURFACE0_LOWER_BOUND,8,3 ## @RADEON_SURFACE0_LOWER_BOUND
	.comm	_RADEON_SURFACE0_UPPER_BOUND,8,3 ## @RADEON_SURFACE0_UPPER_BOUND
	.no_dead_strip	_radeon_apply_surface_regs
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_apply_surface_regs
_radeon_apply_surface_regs:             ; @radeon_apply_surface_regs
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	ldr	w8, [x1, #8]
	cbz	w8, LBB0_2
; %bb.1:
	mov	x19, x1
	mov	x20, x0
	mov	x0, x1
	bl	_radeon_do_cp_idle
Lloh0:
	adrp	x8, _RADEON_SURFACE0_INFO@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_SURFACE0_INFO@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	lsl	w9, w20, #4
	sxtw	x21, w9
	add	x0, x8, x21
	ldr	x8, [x19]
	mov	w22, #12
	smaddl	x8, w20, w22, x8
	smull	x23, w20, w22
	ldr	w1, [x8, #8]
	bl	_RADEON_WRITE
Lloh3:
	adrp	x8, _RADEON_SURFACE0_LOWER_BOUND@GOTPAGE
Lloh4:
	ldr	x8, [x8, _RADEON_SURFACE0_LOWER_BOUND@GOTPAGEOFF]
Lloh5:
	ldr	x8, [x8]
	add	x0, x8, x21
	ldr	x8, [x19]
	smaddl	x8, w20, w22, x8
	ldr	w1, [x8, #4]
	bl	_RADEON_WRITE
Lloh6:
	adrp	x8, _RADEON_SURFACE0_UPPER_BOUND@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_SURFACE0_UPPER_BOUND@GOTPAGEOFF]
Lloh8:
	ldr	x8, [x8]
	add	x0, x8, x21
	ldr	x8, [x19]
	ldr	w1, [x8, x23]
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_RADEON_WRITE
LBB0_2:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_SURFACE0_INFO,8,3       ; @RADEON_SURFACE0_INFO
	.comm	_RADEON_SURFACE0_LOWER_BOUND,8,3 ; @RADEON_SURFACE0_LOWER_BOUND
	.comm	_RADEON_SURFACE0_UPPER_BOUND,8,3 ; @RADEON_SURFACE0_UPPER_BOUND
	.no_dead_strip	_radeon_apply_surface_regs
.subsections_via_symbols
