	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function r300_emit_vpu
_r300_emit_vpu:                         ## @r300_emit_vpu
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r13
	testl	%r13d, %r13d
	je	LBB0_1
## %bb.2:
	movl	%ecx, %r15d
	movq	%rsi, %r14
	movq	%rdi, %r12
	movl	%r13d, %ebx
	shll	$4, %ebx
	movl	(%rsi), %edi
	callq	_drm_buffer_unprocessed
	cmpl	%eax, %ebx
	jle	LBB0_4
## %bb.3:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r15d, %r15d
	subl	(%rax), %r15d
	jmp	LBB0_5
LBB0_1:
	xorl	%r15d, %r15d
	jmp	LBB0_5
LBB0_4:
	movq	%r13, %rbx
	shrq	$24, %rbx
	andl	$-256, %ebx
	orl	%r15d, %ebx
	movl	$6, %edi
	callq	_BEGIN_RING
	movq	_R300_RB3D_DSTCACHE_CTLSTAT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%r15d, %r15d
	xorl	%esi, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movq	_R300_RB3D_DC_FLUSH@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_OUT_RING
	movq	_RADEON_WAIT_UNTIL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movq	_RADEON_WAIT_3D_IDLECLEAN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_OUT_RING
	movq	_R300_VAP_PVS_STATE_FLUSH_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	xorl	%edi, %edi
	callq	_OUT_RING
	xorl	%eax, %eax
	callq	_ADVANCE_RING
	movq	_RADEON_FLUSH_EMITED@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r12)
	leal	(,%r13,4), %r12d
	leal	3(,%r13,4), %edi
	callq	_BEGIN_RING
	movq	_R300_VAP_PVS_UPLOAD_ADDRESS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_OUT_RING_REG
	movq	_R300_VAP_PVS_UPLOAD_DATA@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	leal	-1(,%r13,4), %esi
	callq	_CP_PACKET0_TABLE
	movl	%eax, %edi
	callq	_OUT_RING
	movl	(%r14), %edi
	movl	%r12d, %esi
	callq	_OUT_RING_DRM_BUFFER
	xorl	%eax, %eax
	callq	_ADVANCE_RING
	movl	$2, %edi
	callq	_BEGIN_RING
	movq	_R300_VAP_PVS_STATE_FLUSH_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	xorl	%edi, %edi
	callq	_OUT_RING
	xorl	%eax, %eax
	callq	_ADVANCE_RING
LBB0_5:
	movl	%r15d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RING_LOCALS,4,2                ## @RING_LOCALS
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_R300_RB3D_DSTCACHE_CTLSTAT,4,2 ## @R300_RB3D_DSTCACHE_CTLSTAT
	.comm	_R300_RB3D_DC_FLUSH,4,2         ## @R300_RB3D_DC_FLUSH
	.comm	_RADEON_WAIT_UNTIL,4,2          ## @RADEON_WAIT_UNTIL
	.comm	_RADEON_WAIT_3D_IDLECLEAN,4,2   ## @RADEON_WAIT_3D_IDLECLEAN
	.comm	_R300_VAP_PVS_STATE_FLUSH_REG,4,2 ## @R300_VAP_PVS_STATE_FLUSH_REG
	.comm	_RADEON_FLUSH_EMITED,4,2        ## @RADEON_FLUSH_EMITED
	.comm	_R300_VAP_PVS_UPLOAD_ADDRESS,4,2 ## @R300_VAP_PVS_UPLOAD_ADDRESS
	.comm	_R300_VAP_PVS_UPLOAD_DATA,4,2   ## @R300_VAP_PVS_UPLOAD_DATA
	.no_dead_strip	_r300_emit_vpu
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function r300_emit_vpu
_r300_emit_vpu:                         ; @r300_emit_vpu
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x2
	cbz	w20, LBB0_4
; %bb.1:
	mov	x22, x3
	mov	x19, x1
	mov	x21, x0
	ldr	w0, [x1]
	bl	_drm_buffer_unprocessed
	cmp	w0, w20, lsl #4
	b.ge	LBB0_3
; %bb.2:
Lloh0:
	adrp	x8, _EINVAL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_5
LBB0_3:
	lsr	x8, x20, #24
	and	w8, w8, #0xffffff00
	orr	w22, w8, w22
	mov	w0, #6
	bl	_BEGIN_RING
Lloh3:
	adrp	x8, _R300_RB3D_DSTCACHE_CTLSTAT@GOTPAGE
Lloh4:
	ldr	x8, [x8, _R300_RB3D_DSTCACHE_CTLSTAT@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_CP_PACKET0
	bl	_OUT_RING
Lloh6:
	adrp	x8, _R300_RB3D_DC_FLUSH@GOTPAGE
Lloh7:
	ldr	x8, [x8, _R300_RB3D_DC_FLUSH@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	bl	_OUT_RING
Lloh9:
	adrp	x8, _RADEON_WAIT_UNTIL@GOTPAGE
Lloh10:
	ldr	x8, [x8, _RADEON_WAIT_UNTIL@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_CP_PACKET0
	bl	_OUT_RING
Lloh12:
	adrp	x8, _RADEON_WAIT_3D_IDLECLEAN@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RADEON_WAIT_3D_IDLECLEAN@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	bl	_OUT_RING
Lloh15:
	adrp	x23, _R300_VAP_PVS_STATE_FLUSH_REG@GOTPAGE
Lloh16:
	ldr	x23, [x23, _R300_VAP_PVS_STATE_FLUSH_REG@GOTPAGEOFF]
	ldr	w0, [x23]
	mov	w1, #0
	bl	_CP_PACKET0
	bl	_OUT_RING
	mov	w0, #0
	bl	_OUT_RING
	bl	_ADVANCE_RING
Lloh17:
	adrp	x8, _RADEON_FLUSH_EMITED@GOTPAGE
Lloh18:
	ldr	x8, [x8, _RADEON_FLUSH_EMITED@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
	ldr	w9, [x21]
	orr	w8, w9, w8
	str	w8, [x21]
	lsl	w21, w20, #2
	mov	w0, #3
	bfi	w0, w20, #2, #30
	bl	_BEGIN_RING
Lloh20:
	adrp	x8, _R300_VAP_PVS_UPLOAD_ADDRESS@GOTPAGE
Lloh21:
	ldr	x8, [x8, _R300_VAP_PVS_UPLOAD_ADDRESS@GOTPAGEOFF]
Lloh22:
	ldr	w0, [x8]
	mov	x1, x22
	bl	_OUT_RING_REG
Lloh23:
	adrp	x8, _R300_VAP_PVS_UPLOAD_DATA@GOTPAGE
Lloh24:
	ldr	x8, [x8, _R300_VAP_PVS_UPLOAD_DATA@GOTPAGEOFF]
Lloh25:
	ldr	w0, [x8]
	sub	w1, w21, #1
	bl	_CP_PACKET0_TABLE
	bl	_OUT_RING
	ldr	w0, [x19]
	mov	x1, x21
	bl	_OUT_RING_DRM_BUFFER
	bl	_ADVANCE_RING
	mov	w0, #2
	bl	_BEGIN_RING
	ldr	w0, [x23]
	mov	w1, #0
	bl	_CP_PACKET0
	bl	_OUT_RING
	mov	w0, #0
	bl	_OUT_RING
	bl	_ADVANCE_RING
LBB0_4:
	mov	w0, #0
LBB0_5:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_RING_LOCALS,4,2                ; @RING_LOCALS
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_R300_RB3D_DSTCACHE_CTLSTAT,4,2 ; @R300_RB3D_DSTCACHE_CTLSTAT
	.comm	_R300_RB3D_DC_FLUSH,4,2         ; @R300_RB3D_DC_FLUSH
	.comm	_RADEON_WAIT_UNTIL,4,2          ; @RADEON_WAIT_UNTIL
	.comm	_RADEON_WAIT_3D_IDLECLEAN,4,2   ; @RADEON_WAIT_3D_IDLECLEAN
	.comm	_R300_VAP_PVS_STATE_FLUSH_REG,4,2 ; @R300_VAP_PVS_STATE_FLUSH_REG
	.comm	_RADEON_FLUSH_EMITED,4,2        ; @RADEON_FLUSH_EMITED
	.comm	_R300_VAP_PVS_UPLOAD_ADDRESS,4,2 ; @R300_VAP_PVS_UPLOAD_ADDRESS
	.comm	_R300_VAP_PVS_UPLOAD_DATA,4,2   ; @R300_VAP_PVS_UPLOAD_DATA
	.no_dead_strip	_r300_emit_vpu
.subsections_via_symbols
