	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r100_pci_gart_enable           ## -- Begin function r100_pci_gart_enable
	.p2align	4, 0x90
_r100_pci_gart_enable:                  ## @r100_pci_gart_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	callq	_radeon_gart_restore
	movq	_RADEON_AIC_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32
	movq	_RADEON_DIS_OUT_OF_PCI_GART_ACCESS@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r14), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_RADEON_AIC_LO_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	8(%rbx), %esi
	callq	_WREG32
	movq	_RADEON_AIC_HI_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	12(%rbx), %esi
	callq	_WREG32
	movq	_RADEON_AIC_PT_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%rbx), %esi
	callq	_WREG32
	movl	(%r14), %edi
	callq	_RREG32
	movq	_RADEON_PCIGART_TRANSLATE_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r14), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	%rbx, %rdi
	callq	_r100_pci_gart_tlb_flush
	movl	16(%rbx), %esi
	sarl	$20, %esi
	movslq	(%rbx), %rdx
	leaq	L_.str(%rip), %rdi
	callq	_DRM_INFO
	movl	$1, 4(%rbx)
	xorl	%eax, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_AIC_CNTL,4,2            ## @RADEON_AIC_CNTL
	.comm	_RADEON_DIS_OUT_OF_PCI_GART_ACCESS,4,2 ## @RADEON_DIS_OUT_OF_PCI_GART_ACCESS
	.comm	_RADEON_AIC_LO_ADDR,4,2         ## @RADEON_AIC_LO_ADDR
	.comm	_RADEON_AIC_HI_ADDR,4,2         ## @RADEON_AIC_HI_ADDR
	.comm	_RADEON_AIC_PT_BASE,4,2         ## @RADEON_AIC_PT_BASE
	.comm	_RADEON_PCIGART_TRANSLATE_EN,4,2 ## @RADEON_PCIGART_TRANSLATE_EN
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"PCI GART of %uM enabled (table at 0x%016llX).\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r100_pci_gart_enable           ; -- Begin function r100_pci_gart_enable
	.p2align	2
_r100_pci_gart_enable:                  ; @r100_pci_gart_enable
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_radeon_gart_restore
Lloh0:
	adrp	x20, _RADEON_AIC_CNTL@GOTPAGE
Lloh1:
	ldr	x20, [x20, _RADEON_AIC_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh2:
	adrp	x8, _RADEON_DIS_OUT_OF_PCI_GART_ACCESS@GOTPAGE
Lloh3:
	ldr	x8, [x8, _RADEON_DIS_OUT_OF_PCI_GART_ACCESS@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x20]
	bl	_WREG32
Lloh5:
	adrp	x8, _RADEON_AIC_LO_ADDR@GOTPAGE
Lloh6:
	ldr	x8, [x8, _RADEON_AIC_LO_ADDR@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
	ldr	w1, [x19, #8]
	bl	_WREG32
Lloh8:
	adrp	x8, _RADEON_AIC_HI_ADDR@GOTPAGE
Lloh9:
	ldr	x8, [x8, _RADEON_AIC_HI_ADDR@GOTPAGEOFF]
Lloh10:
	ldr	w0, [x8]
	ldr	w1, [x19, #12]
	bl	_WREG32
Lloh11:
	adrp	x8, _RADEON_AIC_PT_BASE@GOTPAGE
Lloh12:
	ldr	x8, [x8, _RADEON_AIC_PT_BASE@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_WREG32
	ldr	w0, [x20]
	bl	_RREG32
Lloh14:
	adrp	x8, _RADEON_PCIGART_TRANSLATE_EN@GOTPAGE
Lloh15:
	ldr	x8, [x8, _RADEON_PCIGART_TRANSLATE_EN@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x20]
	bl	_WREG32
	mov	x0, x19
	bl	_r100_pci_gart_tlb_flush
	ldr	w8, [x19, #16]
	asr	w1, w8, #20
	ldrsw	x2, [x19]
Lloh17:
	adrp	x0, l_.str@PAGE
Lloh18:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_INFO
	mov	w8, #1
	str	w8, [x19, #4]
	mov	w0, #0
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_AIC_CNTL,4,2            ; @RADEON_AIC_CNTL
	.comm	_RADEON_DIS_OUT_OF_PCI_GART_ACCESS,4,2 ; @RADEON_DIS_OUT_OF_PCI_GART_ACCESS
	.comm	_RADEON_AIC_LO_ADDR,4,2         ; @RADEON_AIC_LO_ADDR
	.comm	_RADEON_AIC_HI_ADDR,4,2         ; @RADEON_AIC_HI_ADDR
	.comm	_RADEON_AIC_PT_BASE,4,2         ; @RADEON_AIC_PT_BASE
	.comm	_RADEON_PCIGART_TRANSLATE_EN,4,2 ; @RADEON_PCIGART_TRANSLATE_EN
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"PCI GART of %uM enabled (table at 0x%016llX).\n"

.subsections_via_symbols
