	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_intel_ddi_pll_mode_set         ## -- Begin function intel_ddi_pll_mode_set
	.p2align	4, 0x90
_intel_ddi_pll_mode_set:                ## @intel_ddi_pll_mode_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, -48(%rbp)                 ## 4-byte Spill
	movq	%rdi, %r14
	callq	_to_intel_crtc
	movq	%rax, %r13
	movq	%r14, %rdi
	callq	_intel_ddi_get_crtc_encoder
	movq	%rax, %rbx
	movq	(%r14), %rax
	movq	(%rax), %r12
	movl	(%rbx), %r15d
	movl	(%r13), %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	%r14, %rdi
	callq	_intel_ddi_put_crtc_pll
	movq	_INTEL_OUTPUT_DISPLAYPORT@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r15d
	je	LBB0_2
## %bb.1:
	movq	_INTEL_OUTPUT_EDP@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r15d
	je	LBB0_2
## %bb.10:
	movq	_INTEL_OUTPUT_HDMI@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r15d
	jne	LBB0_17
## %bb.11:
	cmpq	$0, (%r12)
	je	LBB0_12
## %bb.13:
	cmpq	$0, 8(%r12)
	je	LBB0_14
## %bb.16:
	leaq	L_.str.3(%rip), %rdi
	xorl	%r14d, %r14d
	xorl	%eax, %eax
	callq	_DRM_ERROR
	jmp	LBB0_23
LBB0_2:
	addq	$4, %rbx
	movq	%rbx, %rdi
	callq	_enc_to_intel_dp
	movl	(%rax), %esi
	cmpl	$128, %esi
	je	LBB0_8
## %bb.3:
	cmpl	$129, %esi
	je	LBB0_7
## %bb.4:
	cmpl	$130, %esi
	jne	LBB0_9
## %bb.5:
	movq	_PORT_CLK_SEL_LCPLL_810@GOTPCREL(%rip), %rax
	jmp	LBB0_6
LBB0_17:
	movq	_INTEL_OUTPUT_ANALOG@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r15d
	jne	LBB0_24
## %bb.18:
	cmpq	$0, 16(%r12)
                                        ## implicit-def: $r14d
	jne	LBB0_20
## %bb.19:
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	callq	_pipe_name
	leaq	L_.str.5(%rip), %rdi
	movl	%eax, %esi
	callq	_DRM_DEBUG_KMS
	incq	16(%r12)
	movq	_SPLL_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_PORT_CLK_SEL_SPLL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 4(%r13)
LBB0_20:
	movl	%r14d, %edi
	callq	_I915_READ
	movq	_SPLL_PLL_ENABLE@GOTPCREL(%rip), %rbx
	andl	(%rbx), %eax
	leaq	L_.str.6(%rip), %rsi
	movl	%eax, %edi
	xorl	%eax, %eax
	callq	_WARN
	movq	_SPLL_PLL_FREQ_1350MHz@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	(%rbx), %esi
	movq	_SPLL_PLL_SSC@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	jmp	LBB0_21
LBB0_8:
	movq	_PORT_CLK_SEL_LCPLL_2700@GOTPCREL(%rip), %rax
	jmp	LBB0_6
LBB0_7:
	movq	_PORT_CLK_SEL_LCPLL_1350@GOTPCREL(%rip), %rax
LBB0_6:
	movl	(%rax), %eax
	movl	%eax, 4(%r13)
	jmp	LBB0_22
LBB0_9:
	leaq	L_.str(%rip), %rdi
	xorl	%r14d, %r14d
	xorl	%eax, %eax
	callq	_DRM_ERROR
	jmp	LBB0_23
LBB0_24:
	leaq	L_.str.7(%rip), %rsi
	xorl	%r14d, %r14d
	movl	$1, %edi
	movl	%r15d, %edx
	xorl	%eax, %eax
	callq	_WARN
	jmp	LBB0_23
LBB0_12:
	movq	_PORT_CLK_SEL_WRPLL1@GOTPCREL(%rip), %r15
	movq	_WRPLL_CTL1@GOTPCREL(%rip), %r14
	leaq	L_.str.1(%rip), %rbx
	jmp	LBB0_15
LBB0_14:
	addq	$8, %r12
	movq	_PORT_CLK_SEL_WRPLL2@GOTPCREL(%rip), %r15
	movq	_WRPLL_CTL2@GOTPCREL(%rip), %r14
	leaq	L_.str.2(%rip), %rbx
LBB0_15:
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	callq	_pipe_name
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_DRM_DEBUG_KMS
	incq	(%r12)
	movl	(%r14), %r14d
	movl	(%r15), %eax
	movl	%eax, 4(%r13)
	movl	%r14d, %edi
	callq	_I915_READ
	movq	_WRPLL_PLL_ENABLE@GOTPCREL(%rip), %rbx
	andl	(%rbx), %eax
	leaq	L_.str.4(%rip), %rsi
	movl	%eax, %edi
	xorl	%eax, %eax
	callq	_WARN
	leaq	-60(%rbp), %rsi
	leaq	-56(%rbp), %rdx
	leaq	-52(%rbp), %rcx
	movl	-48(%rbp), %edi                 ## 4-byte Reload
	callq	_intel_ddi_calculate_wrpll
	movq	_WRPLL_PLL_SELECT_LCPLL_2700@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	orl	(%rbx), %r12d
	movl	-52(%rbp), %edi
	callq	_WRPLL_DIVIDER_REFERENCE
	movl	%eax, %r15d
	movl	-56(%rbp), %edi
	callq	_WRPLL_DIVIDER_FEEDBACK
	movl	%eax, %ebx
	orl	%r15d, %ebx
	movl	-60(%rbp), %edi
	callq	_WRPLL_DIVIDER_POST
	movl	%eax, %esi
	orl	%ebx, %esi
	orl	%r12d, %esi
LBB0_21:
	movl	%r14d, %edi
	callq	_I915_WRITE
	movl	$20, %edi
	callq	_udelay
LBB0_22:
	movl	$1, %r14d
LBB0_23:
	movl	%r14d, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_INTEL_OUTPUT_DISPLAYPORT,4,2   ## @INTEL_OUTPUT_DISPLAYPORT
	.comm	_INTEL_OUTPUT_EDP,4,2           ## @INTEL_OUTPUT_EDP
	.comm	_PORT_CLK_SEL_LCPLL_810,4,2     ## @PORT_CLK_SEL_LCPLL_810
	.comm	_PORT_CLK_SEL_LCPLL_1350,4,2    ## @PORT_CLK_SEL_LCPLL_1350
	.comm	_PORT_CLK_SEL_LCPLL_2700,4,2    ## @PORT_CLK_SEL_LCPLL_2700
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Link bandwidth %d unsupported\n"

	.comm	_INTEL_OUTPUT_HDMI,4,2          ## @INTEL_OUTPUT_HDMI
L_.str.1:                               ## @.str.1
	.asciz	"Using WRPLL 1 on pipe %c\n"

	.comm	_WRPLL_CTL1,4,2                 ## @WRPLL_CTL1
	.comm	_PORT_CLK_SEL_WRPLL1,4,2        ## @PORT_CLK_SEL_WRPLL1
L_.str.2:                               ## @.str.2
	.asciz	"Using WRPLL 2 on pipe %c\n"

	.comm	_WRPLL_CTL2,4,2                 ## @WRPLL_CTL2
	.comm	_PORT_CLK_SEL_WRPLL2,4,2        ## @PORT_CLK_SEL_WRPLL2
L_.str.3:                               ## @.str.3
	.asciz	"No WRPLLs available!\n"

	.comm	_WRPLL_PLL_ENABLE,4,2           ## @WRPLL_PLL_ENABLE
L_.str.4:                               ## @.str.4
	.asciz	"WRPLL already enabled\n"

	.comm	_WRPLL_PLL_SELECT_LCPLL_2700,4,2 ## @WRPLL_PLL_SELECT_LCPLL_2700
	.comm	_INTEL_OUTPUT_ANALOG,4,2        ## @INTEL_OUTPUT_ANALOG
L_.str.5:                               ## @.str.5
	.asciz	"Using SPLL on pipe %c\n"

	.comm	_SPLL_CTL,4,2                   ## @SPLL_CTL
	.comm	_PORT_CLK_SEL_SPLL,4,2          ## @PORT_CLK_SEL_SPLL
	.comm	_SPLL_PLL_ENABLE,4,2            ## @SPLL_PLL_ENABLE
L_.str.6:                               ## @.str.6
	.asciz	"SPLL already enabled\n"

	.comm	_SPLL_PLL_FREQ_1350MHz,4,2      ## @SPLL_PLL_FREQ_1350MHz
	.comm	_SPLL_PLL_SSC,4,2               ## @SPLL_PLL_SSC
L_.str.7:                               ## @.str.7
	.asciz	"Invalid DDI encoder type %d\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_intel_ddi_pll_mode_set         ; -- Begin function intel_ddi_pll_mode_set
	.p2align	2
_intel_ddi_pll_mode_set:                ; @intel_ddi_pll_mode_set
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x1
	mov	x23, x0
	bl	_to_intel_crtc
	mov	x19, x0
	mov	x0, x23
	bl	_intel_ddi_get_crtc_encoder
	mov	x21, x0
	ldr	x8, [x23]
	ldr	x24, [x8]
	ldr	w25, [x0]
	ldr	w22, [x19]
	mov	x0, x23
	bl	_intel_ddi_put_crtc_pll
Lloh0:
	adrp	x8, _INTEL_OUTPUT_DISPLAYPORT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _INTEL_OUTPUT_DISPLAYPORT@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _INTEL_OUTPUT_EDP@GOTPAGE
Lloh4:
	ldr	x9, [x9, _INTEL_OUTPUT_EDP@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	cmp	w25, w8
	ccmp	w25, w9, #4, ne
	b.ne	LBB0_5
; %bb.1:
	add	x0, x21, #4
	bl	_enc_to_intel_dp
	ldr	w8, [x0]
	cmp	w8, #128
	b.eq	LBB0_13
; %bb.2:
	cmp	w8, #129
	b.eq	LBB0_14
; %bb.3:
	cmp	w8, #130
	b.ne	LBB0_16
; %bb.4:
Lloh6:
	adrp	x8, _PORT_CLK_SEL_LCPLL_810@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PORT_CLK_SEL_LCPLL_810@GOTPAGEOFF]
	b	LBB0_15
LBB0_5:
Lloh8:
	adrp	x8, _INTEL_OUTPUT_HDMI@GOTPAGE
Lloh9:
	ldr	x8, [x8, _INTEL_OUTPUT_HDMI@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	cmp	w25, w8
	b.ne	LBB0_9
; %bb.6:
	ldr	x8, [x24]
	cbz	x8, LBB0_19
; %bb.7:
	ldr	x8, [x24, #8]!
	cbz	x8, LBB0_20
; %bb.8:
Lloh11:
	adrp	x0, l_.str.3@PAGE
Lloh12:
	add	x0, x0, l_.str.3@PAGEOFF
	b	LBB0_17
LBB0_9:
Lloh13:
	adrp	x8, _INTEL_OUTPUT_ANALOG@GOTPAGE
Lloh14:
	ldr	x8, [x8, _INTEL_OUTPUT_ANALOG@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
	cmp	w25, w8
	b.ne	LBB0_18
; %bb.10:
	ldr	x8, [x24, #16]
                                        ; implicit-def: $w21
	cbnz	x8, LBB0_12
; %bb.11:
	mov	x0, x22
	bl	_pipe_name
	mov	x1, x0
Lloh16:
	adrp	x0, l_.str.5@PAGE
Lloh17:
	add	x0, x0, l_.str.5@PAGEOFF
	bl	_DRM_DEBUG_KMS
	ldr	x8, [x24, #16]
	add	x8, x8, #1
Lloh18:
	adrp	x9, _SPLL_CTL@GOTPAGE
Lloh19:
	ldr	x9, [x9, _SPLL_CTL@GOTPAGEOFF]
	str	x8, [x24, #16]
Lloh20:
	ldr	w21, [x9]
Lloh21:
	adrp	x8, _PORT_CLK_SEL_SPLL@GOTPAGE
Lloh22:
	ldr	x8, [x8, _PORT_CLK_SEL_SPLL@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	str	w8, [x19, #4]
LBB0_12:
	mov	x0, x21
	bl	_I915_READ
Lloh24:
	adrp	x19, _SPLL_PLL_ENABLE@GOTPAGE
Lloh25:
	ldr	x19, [x19, _SPLL_PLL_ENABLE@GOTPAGEOFF]
	ldr	w8, [x19]
	and	w0, w8, w0
Lloh26:
	adrp	x1, l_.str.6@PAGE
Lloh27:
	add	x1, x1, l_.str.6@PAGEOFF
	bl	_WARN
	ldr	w8, [x19]
Lloh28:
	adrp	x9, _SPLL_PLL_FREQ_1350MHz@GOTPAGE
Lloh29:
	ldr	x9, [x9, _SPLL_PLL_FREQ_1350MHz@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh31:
	adrp	x9, _SPLL_PLL_SSC@GOTPAGE
Lloh32:
	ldr	x9, [x9, _SPLL_PLL_SSC@GOTPAGEOFF]
Lloh33:
	ldr	w9, [x9]
	orr	w1, w8, w9
	b	LBB0_22
LBB0_13:
Lloh34:
	adrp	x8, _PORT_CLK_SEL_LCPLL_2700@GOTPAGE
Lloh35:
	ldr	x8, [x8, _PORT_CLK_SEL_LCPLL_2700@GOTPAGEOFF]
	b	LBB0_15
LBB0_14:
Lloh36:
	adrp	x8, _PORT_CLK_SEL_LCPLL_1350@GOTPAGE
Lloh37:
	ldr	x8, [x8, _PORT_CLK_SEL_LCPLL_1350@GOTPAGEOFF]
LBB0_15:
	ldr	w8, [x8]
	str	w8, [x19, #4]
	b	LBB0_23
LBB0_16:
	str	x8, [sp]
Lloh38:
	adrp	x0, l_.str@PAGE
Lloh39:
	add	x0, x0, l_.str@PAGEOFF
LBB0_17:
	bl	_DRM_ERROR
	mov	w0, #0
	b	LBB0_24
LBB0_18:
	str	x25, [sp]
Lloh40:
	adrp	x1, l_.str.7@PAGE
Lloh41:
	add	x1, x1, l_.str.7@PAGEOFF
	mov	w0, #1
	bl	_WARN
	mov	w0, #0
	b	LBB0_24
LBB0_19:
Lloh42:
	adrp	x23, _PORT_CLK_SEL_WRPLL1@GOTPAGE
Lloh43:
	ldr	x23, [x23, _PORT_CLK_SEL_WRPLL1@GOTPAGEOFF]
Lloh44:
	adrp	x25, _WRPLL_CTL1@GOTPAGE
Lloh45:
	ldr	x25, [x25, _WRPLL_CTL1@GOTPAGEOFF]
Lloh46:
	adrp	x21, l_.str.1@PAGE
Lloh47:
	add	x21, x21, l_.str.1@PAGEOFF
	b	LBB0_21
LBB0_20:
Lloh48:
	adrp	x23, _PORT_CLK_SEL_WRPLL2@GOTPAGE
Lloh49:
	ldr	x23, [x23, _PORT_CLK_SEL_WRPLL2@GOTPAGEOFF]
Lloh50:
	adrp	x25, _WRPLL_CTL2@GOTPAGE
Lloh51:
	ldr	x25, [x25, _WRPLL_CTL2@GOTPAGEOFF]
Lloh52:
	adrp	x21, l_.str.2@PAGE
Lloh53:
	add	x21, x21, l_.str.2@PAGEOFF
LBB0_21:
	mov	x0, x22
	bl	_pipe_name
	mov	x1, x0
	mov	x0, x21
	bl	_DRM_DEBUG_KMS
	ldr	x8, [x24]
	add	x8, x8, #1
	str	x8, [x24]
	ldr	w21, [x25]
	ldr	w8, [x23]
	str	w8, [x19, #4]
	mov	x0, x21
	bl	_I915_READ
Lloh54:
	adrp	x19, _WRPLL_PLL_ENABLE@GOTPAGE
Lloh55:
	ldr	x19, [x19, _WRPLL_PLL_ENABLE@GOTPAGEOFF]
	ldr	w8, [x19]
	and	w0, w8, w0
Lloh56:
	adrp	x1, l_.str.4@PAGE
Lloh57:
	add	x1, x1, l_.str.4@PAGEOFF
	bl	_WARN
	add	x1, sp, #28
	add	x2, sp, #24
	add	x3, sp, #20
	mov	x0, x20
	bl	_intel_ddi_calculate_wrpll
	ldr	w8, [x19]
Lloh58:
	adrp	x9, _WRPLL_PLL_SELECT_LCPLL_2700@GOTPAGE
Lloh59:
	ldr	x9, [x9, _WRPLL_PLL_SELECT_LCPLL_2700@GOTPAGEOFF]
Lloh60:
	ldr	w9, [x9]
	orr	w19, w9, w8
	ldr	w0, [sp, #20]
	bl	_WRPLL_DIVIDER_REFERENCE
	orr	w19, w19, w0
	ldr	w0, [sp, #24]
	bl	_WRPLL_DIVIDER_FEEDBACK
	orr	w19, w19, w0
	ldr	w0, [sp, #28]
	bl	_WRPLL_DIVIDER_POST
	orr	w1, w19, w0
LBB0_22:
	mov	x0, x21
	bl	_I915_WRITE
	mov	w0, #20
	bl	_udelay
LBB0_23:
	mov	w0, #1
LBB0_24:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpAdd	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpAdd	Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpAdd	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpAdd	Lloh38, Lloh39
	.loh AdrpAdd	Lloh40, Lloh41
	.loh AdrpAdd	Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpAdd	Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpAdd	Lloh56, Lloh57
	.loh AdrpLdrGot	Lloh54, Lloh55
	.cfi_endproc
                                        ; -- End function
	.comm	_INTEL_OUTPUT_DISPLAYPORT,4,2   ; @INTEL_OUTPUT_DISPLAYPORT
	.comm	_INTEL_OUTPUT_EDP,4,2           ; @INTEL_OUTPUT_EDP
	.comm	_PORT_CLK_SEL_LCPLL_810,4,2     ; @PORT_CLK_SEL_LCPLL_810
	.comm	_PORT_CLK_SEL_LCPLL_1350,4,2    ; @PORT_CLK_SEL_LCPLL_1350
	.comm	_PORT_CLK_SEL_LCPLL_2700,4,2    ; @PORT_CLK_SEL_LCPLL_2700
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Link bandwidth %d unsupported\n"

	.comm	_INTEL_OUTPUT_HDMI,4,2          ; @INTEL_OUTPUT_HDMI
l_.str.1:                               ; @.str.1
	.asciz	"Using WRPLL 1 on pipe %c\n"

	.comm	_WRPLL_CTL1,4,2                 ; @WRPLL_CTL1
	.comm	_PORT_CLK_SEL_WRPLL1,4,2        ; @PORT_CLK_SEL_WRPLL1
l_.str.2:                               ; @.str.2
	.asciz	"Using WRPLL 2 on pipe %c\n"

	.comm	_WRPLL_CTL2,4,2                 ; @WRPLL_CTL2
	.comm	_PORT_CLK_SEL_WRPLL2,4,2        ; @PORT_CLK_SEL_WRPLL2
l_.str.3:                               ; @.str.3
	.asciz	"No WRPLLs available!\n"

	.comm	_WRPLL_PLL_ENABLE,4,2           ; @WRPLL_PLL_ENABLE
l_.str.4:                               ; @.str.4
	.asciz	"WRPLL already enabled\n"

	.comm	_WRPLL_PLL_SELECT_LCPLL_2700,4,2 ; @WRPLL_PLL_SELECT_LCPLL_2700
	.comm	_INTEL_OUTPUT_ANALOG,4,2        ; @INTEL_OUTPUT_ANALOG
l_.str.5:                               ; @.str.5
	.asciz	"Using SPLL on pipe %c\n"

	.comm	_SPLL_CTL,4,2                   ; @SPLL_CTL
	.comm	_PORT_CLK_SEL_SPLL,4,2          ; @PORT_CLK_SEL_SPLL
	.comm	_SPLL_PLL_ENABLE,4,2            ; @SPLL_PLL_ENABLE
l_.str.6:                               ; @.str.6
	.asciz	"SPLL already enabled\n"

	.comm	_SPLL_PLL_FREQ_1350MHz,4,2      ; @SPLL_PLL_FREQ_1350MHz
	.comm	_SPLL_PLL_SSC,4,2               ; @SPLL_PLL_SSC
l_.str.7:                               ; @.str.7
	.asciz	"Invalid DDI encoder type %d\n"

.subsections_via_symbols
