	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function setup_memwin
_setup_memwin:                          ## @setup_memwin
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movl	16(%rdi), %edi
	xorl	%esi, %esi
	callq	_pci_resource_start
	movl	%eax, %r12d
	movq	_PCIE_MEM_ACCESS_BASE_WIN@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	xorl	%esi, %esi
	callq	_PCIE_MEM_ACCESS_REG
	movl	%eax, %r15d
	movq	_MEMWIN0_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	addl	%r12d, %ebx
	xorl	%edi, %edi
	callq	_BIR
	orl	%eax, %ebx
	movq	_MEMWIN0_APERTURE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_ilog2
	leaq	-10(%rax), %rdi
	callq	_WINDOW
	orl	%eax, %ebx
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_t4_write_reg
	movl	(%r13), %edi
	movl	$1, %esi
	callq	_PCIE_MEM_ACCESS_REG
	movl	%eax, %r15d
	movq	_MEMWIN1_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	addl	%r12d, %ebx
	xorl	%edi, %edi
	callq	_BIR
	orl	%eax, %ebx
	movq	_MEMWIN1_APERTURE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_ilog2
	leaq	-10(%rax), %rdi
	callq	_WINDOW
	orl	%eax, %ebx
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_t4_write_reg
	movl	(%r13), %edi
	movl	$2, %esi
	callq	_PCIE_MEM_ACCESS_REG
	movl	%eax, %ebx
	movq	_MEMWIN2_BASE@GOTPCREL(%rip), %rax
	addl	(%rax), %r12d
	xorl	%edi, %edi
	callq	_BIR
	orl	%eax, %r12d
	movq	_MEMWIN2_APERTURE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_ilog2
	leaq	-10(%rax), %rdi
	callq	_WINDOW
	orl	%eax, %r12d
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%r12d, %edx
	callq	_t4_write_reg
	cmpq	$0, 8(%r14)
	je	LBB0_1
## %bb.2:
	movl	16(%r14), %edi
	movl	$2, %esi
	callq	_pci_resource_start
	movl	%eax, %ebx
	movl	16(%r14), %edi
	movq	%r14, %rsi
	callq	_OCQ_WIN_OFFSET
	addl	%eax, %ebx
	movq	8(%r14), %rdi
	callq	_roundup_pow_of_two
	movl	%eax, %r15d
	sarl	$10, %r15d
	movl	(%r13), %edi
	movl	$3, %esi
	callq	_PCIE_MEM_ACCESS_REG
	movl	%eax, %r12d
	movl	$1, %edi
	callq	_BIR
	orl	%eax, %ebx
	movl	%r15d, %edi
	callq	_ilog2
	movq	%rax, %rdi
	callq	_WINDOW
	orl	%eax, %ebx
	movq	%r14, %rdi
	movl	%r12d, %esi
	movl	%ebx, %edx
	callq	_t4_write_reg
	movq	_PCIE_MEM_ACCESS_OFFSET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movl	$3, %esi
	callq	_PCIE_MEM_ACCESS_REG
	movl	(%r14), %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_t4_write_reg
	movl	(%rbx), %edi
	movl	$3, %esi
	callq	_PCIE_MEM_ACCESS_REG
	movq	%r14, %rdi
	movl	%eax, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_t4_read_reg                    ## TAILCALL
LBB0_1:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PCIE_MEM_ACCESS_BASE_WIN,4,2   ## @PCIE_MEM_ACCESS_BASE_WIN
	.comm	_MEMWIN0_BASE,4,2               ## @MEMWIN0_BASE
	.comm	_MEMWIN0_APERTURE,4,2           ## @MEMWIN0_APERTURE
	.comm	_MEMWIN1_BASE,4,2               ## @MEMWIN1_BASE
	.comm	_MEMWIN1_APERTURE,4,2           ## @MEMWIN1_APERTURE
	.comm	_MEMWIN2_BASE,4,2               ## @MEMWIN2_BASE
	.comm	_MEMWIN2_APERTURE,4,2           ## @MEMWIN2_APERTURE
	.comm	_PCIE_MEM_ACCESS_OFFSET,4,2     ## @PCIE_MEM_ACCESS_OFFSET
	.no_dead_strip	_setup_memwin
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function setup_memwin
_setup_memwin:                          ; @setup_memwin
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	w0, [x0, #16]
	mov	w1, #0
	bl	_pci_resource_start
	mov	x20, x0
Lloh0:
	adrp	x22, _PCIE_MEM_ACCESS_BASE_WIN@GOTPAGE
Lloh1:
	ldr	x22, [x22, _PCIE_MEM_ACCESS_BASE_WIN@GOTPAGEOFF]
	ldr	w0, [x22]
	mov	w1, #0
	bl	_PCIE_MEM_ACCESS_REG
	mov	x21, x0
Lloh2:
	adrp	x8, _MEMWIN0_BASE@GOTPAGE
Lloh3:
	ldr	x8, [x8, _MEMWIN0_BASE@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	add	w23, w8, w20
	mov	w0, #0
	bl	_BIR
	orr	w23, w23, w0
Lloh5:
	adrp	x8, _MEMWIN0_APERTURE@GOTPAGE
Lloh6:
	ldr	x8, [x8, _MEMWIN0_APERTURE@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
	bl	_ilog2
	sub	x0, x0, #10
	bl	_WINDOW
	orr	w2, w23, w0
	mov	x0, x19
	mov	x1, x21
	bl	_t4_write_reg
	ldr	w0, [x22]
	mov	w1, #1
	bl	_PCIE_MEM_ACCESS_REG
	mov	x21, x0
Lloh8:
	adrp	x8, _MEMWIN1_BASE@GOTPAGE
Lloh9:
	ldr	x8, [x8, _MEMWIN1_BASE@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	add	w23, w8, w20
	mov	w0, #0
	bl	_BIR
	orr	w23, w23, w0
Lloh11:
	adrp	x8, _MEMWIN1_APERTURE@GOTPAGE
Lloh12:
	ldr	x8, [x8, _MEMWIN1_APERTURE@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
	bl	_ilog2
	sub	x0, x0, #10
	bl	_WINDOW
	orr	w2, w23, w0
	mov	x0, x19
	mov	x1, x21
	bl	_t4_write_reg
	ldr	w0, [x22]
	mov	w1, #2
	bl	_PCIE_MEM_ACCESS_REG
	mov	x21, x0
Lloh14:
	adrp	x8, _MEMWIN2_BASE@GOTPAGE
Lloh15:
	ldr	x8, [x8, _MEMWIN2_BASE@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
	add	w20, w8, w20
	mov	w0, #0
	bl	_BIR
	orr	w20, w20, w0
Lloh17:
	adrp	x8, _MEMWIN2_APERTURE@GOTPAGE
Lloh18:
	ldr	x8, [x8, _MEMWIN2_APERTURE@GOTPAGEOFF]
Lloh19:
	ldr	w0, [x8]
	bl	_ilog2
	sub	x0, x0, #10
	bl	_WINDOW
	orr	w2, w20, w0
	mov	x0, x19
	mov	x1, x21
	bl	_t4_write_reg
	ldr	x8, [x19, #8]
	cbz	x8, LBB0_2
; %bb.1:
	ldr	w0, [x19, #16]
	mov	w1, #2
	bl	_pci_resource_start
	mov	x20, x0
	ldr	w0, [x19, #16]
	mov	x1, x19
	bl	_OCQ_WIN_OFFSET
	add	w23, w0, w20
	ldr	x0, [x19, #8]
	bl	_roundup_pow_of_two
	asr	w20, w0, #10
	ldr	w0, [x22]
	mov	w1, #3
	bl	_PCIE_MEM_ACCESS_REG
	mov	x21, x0
	mov	w0, #1
	bl	_BIR
	orr	w22, w0, w23
	mov	x0, x20
	bl	_ilog2
	bl	_WINDOW
	orr	w2, w22, w0
	mov	x0, x19
	mov	x1, x21
	bl	_t4_write_reg
Lloh20:
	adrp	x20, _PCIE_MEM_ACCESS_OFFSET@GOTPAGE
Lloh21:
	ldr	x20, [x20, _PCIE_MEM_ACCESS_OFFSET@GOTPAGEOFF]
	ldr	w0, [x20]
	mov	w1, #3
	bl	_PCIE_MEM_ACCESS_REG
	mov	x1, x0
	ldr	w2, [x19]
	mov	x0, x19
	bl	_t4_write_reg
	ldr	w0, [x20]
	mov	w1, #3
	bl	_PCIE_MEM_ACCESS_REG
	mov	x1, x0
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_t4_read_reg
LBB0_2:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh20, Lloh21
	.cfi_endproc
                                        ; -- End function
	.comm	_PCIE_MEM_ACCESS_BASE_WIN,4,2   ; @PCIE_MEM_ACCESS_BASE_WIN
	.comm	_MEMWIN0_BASE,4,2               ; @MEMWIN0_BASE
	.comm	_MEMWIN0_APERTURE,4,2           ; @MEMWIN0_APERTURE
	.comm	_MEMWIN1_BASE,4,2               ; @MEMWIN1_BASE
	.comm	_MEMWIN1_APERTURE,4,2           ; @MEMWIN1_APERTURE
	.comm	_MEMWIN2_BASE,4,2               ; @MEMWIN2_BASE
	.comm	_MEMWIN2_APERTURE,4,2           ; @MEMWIN2_APERTURE
	.comm	_PCIE_MEM_ACCESS_OFFSET,4,2     ; @PCIE_MEM_ACCESS_OFFSET
	.no_dead_strip	_setup_memwin
.subsections_via_symbols
