	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function intel_pre_pll_enable_lvds
_intel_pre_pll_enable_lvds:             ## @intel_pre_pll_enable_lvds
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	callq	_to_lvds_encoder
	movq	%rax, %r14
	movq	8(%rbx), %r15
	movq	(%r15), %rax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movl	(%rbx), %edi
	callq	_to_intel_crtc
	movq	16(%r14), %rcx
	movq	(%rcx), %r13
	movl	(%rax), %r12d
	movl	(%r14), %edi
	callq	_I915_READ
	movl	%eax, %ebx
	movq	_LVDS_PORT_EN@GOTPCREL(%rip), %rax
	movq	_LVDS_A0A2_CLKA_POWER_UP@GOTPCREL(%rip), %rcx
	orl	(%rax), %ebx
	orl	(%rcx), %ebx
	movq	%r15, %rdi
	callq	_HAS_PCH_CPT
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	_PORT_TRANS_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %ebx
	movl	%r12d, %edi
	callq	_PORT_TRANS_SEL_CPT
	orl	%ebx, %eax
	movq	%r13, %r12
	movq	-48(%rbp), %r13                 ## 8-byte Reload
	jmp	LBB0_5
LBB0_2:
	movq	_LVDS_PIPEB_SELECT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	cmpl	$1, %r12d
	movq	%r13, %r12
	movq	-48(%rbp), %r13                 ## 8-byte Reload
	jne	LBB0_4
## %bb.3:
	orl	%ebx, %eax
	jmp	LBB0_5
LBB0_4:
	notl	%eax
	andl	%ebx, %eax
LBB0_5:
	orl	(%r13), %eax
	cmpq	$0, 8(%r14)
	movq	_LVDS_B0B3_POWER_UP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	movq	_LVDS_CLKB_POWER_UP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	je	LBB0_7
## %bb.6:
	orl	%eax, %ebx
	orl	%ecx, %ebx
	jmp	LBB0_8
LBB0_7:
	orl	%ebx, %ecx
	notl	%ecx
	andl	%ecx, %eax
	movl	%eax, %ebx
LBB0_8:
	movq	%r15, %rdi
	callq	_INTEL_INFO
	cmpl	$4, (%rax)
	jne	LBB0_12
## %bb.9:
	cmpq	$0, 8(%r13)
	movq	_LVDS_ENABLE_DITHER@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	je	LBB0_11
## %bb.10:
	orl	%eax, %ebx
	jmp	LBB0_12
LBB0_11:
	notl	%eax
	andl	%eax, %ebx
LBB0_12:
	movq	_LVDS_HSYNC_POLARITY@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_LVDS_VSYNC_POLARITY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, %edx
	orl	%eax, %edx
	notl	%edx
	andl	%ebx, %edx
	movl	(%r12), %esi
	movq	_DRM_MODE_FLAG_NHSYNC@GOTPCREL(%rip), %rdi
	movl	(%rdi), %edi
	andl	%esi, %edi
	cmovnel	%eax, %edi
	movq	_DRM_MODE_FLAG_NVSYNC@GOTPCREL(%rip), %rax
	andl	(%rax), %esi
	cmovnel	%ecx, %esi
	orl	%edi, %esi
	orl	%edx, %esi
	movl	(%r14), %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_I915_WRITE                     ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_LVDS_PORT_EN,4,2               ## @LVDS_PORT_EN
	.comm	_LVDS_A0A2_CLKA_POWER_UP,4,2    ## @LVDS_A0A2_CLKA_POWER_UP
	.comm	_PORT_TRANS_SEL_MASK,4,2        ## @PORT_TRANS_SEL_MASK
	.comm	_LVDS_PIPEB_SELECT,4,2          ## @LVDS_PIPEB_SELECT
	.comm	_LVDS_B0B3_POWER_UP,4,2         ## @LVDS_B0B3_POWER_UP
	.comm	_LVDS_CLKB_POWER_UP,4,2         ## @LVDS_CLKB_POWER_UP
	.comm	_LVDS_ENABLE_DITHER,4,2         ## @LVDS_ENABLE_DITHER
	.comm	_LVDS_HSYNC_POLARITY,4,2        ## @LVDS_HSYNC_POLARITY
	.comm	_LVDS_VSYNC_POLARITY,4,2        ## @LVDS_VSYNC_POLARITY
	.comm	_DRM_MODE_FLAG_NHSYNC,4,2       ## @DRM_MODE_FLAG_NHSYNC
	.comm	_DRM_MODE_FLAG_NVSYNC,4,2       ## @DRM_MODE_FLAG_NVSYNC
	.no_dead_strip	_intel_pre_pll_enable_lvds
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function intel_pre_pll_enable_lvds
_intel_pre_pll_enable_lvds:             ; @intel_pre_pll_enable_lvds
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x21, x0
	bl	_to_lvds_encoder
	mov	x19, x0
	ldr	x20, [x21, #8]
	ldr	x23, [x20]
	ldr	w0, [x21]
	bl	_to_intel_crtc
	ldr	x8, [x19, #16]
	ldr	x22, [x8]
	ldr	w21, [x0]
	ldr	w0, [x19]
	bl	_I915_READ
Lloh0:
	adrp	x8, _LVDS_PORT_EN@GOTPAGE
Lloh1:
	ldr	x8, [x8, _LVDS_PORT_EN@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _LVDS_A0A2_CLKA_POWER_UP@GOTPAGE
Lloh4:
	ldr	x9, [x9, _LVDS_A0A2_CLKA_POWER_UP@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w24, w8, w9
	mov	x0, x20
	bl	_HAS_PCH_CPT
	cbz	x0, LBB0_2
; %bb.1:
Lloh6:
	adrp	x8, _PORT_TRANS_SEL_MASK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PORT_TRANS_SEL_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	bic	w24, w24, w8
	mov	x0, x21
	bl	_PORT_TRANS_SEL_CPT
	orr	w8, w24, w0
	b	LBB0_3
LBB0_2:
Lloh9:
	adrp	x8, _LVDS_PIPEB_SELECT@GOTPAGE
Lloh10:
	ldr	x8, [x8, _LVDS_PIPEB_SELECT@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	bic	w9, w24, w8
	orr	w8, w8, w24
	cmp	w21, #1
	csel	w8, w9, w8, ne
LBB0_3:
	ldr	w9, [x23]
	orr	w8, w9, w8
	ldr	x9, [x19, #8]
Lloh12:
	adrp	x10, _LVDS_B0B3_POWER_UP@GOTPAGE
Lloh13:
	ldr	x10, [x10, _LVDS_B0B3_POWER_UP@GOTPAGEOFF]
Lloh14:
	ldr	w10, [x10]
Lloh15:
	adrp	x11, _LVDS_CLKB_POWER_UP@GOTPAGE
Lloh16:
	ldr	x11, [x11, _LVDS_CLKB_POWER_UP@GOTPAGEOFF]
Lloh17:
	ldr	w11, [x11]
	orr	w12, w11, w10
	bic	w12, w8, w12
	orr	w8, w10, w8
	orr	w8, w8, w11
	cmp	x9, #0
	csel	w21, w12, w8, eq
	mov	x0, x20
	bl	_INTEL_INFO
	ldr	w8, [x0]
	cmp	w8, #4
	b.ne	LBB0_5
; %bb.4:
Lloh18:
	adrp	x8, _LVDS_ENABLE_DITHER@GOTPAGE
Lloh19:
	ldr	x8, [x8, _LVDS_ENABLE_DITHER@GOTPAGEOFF]
	ldr	x9, [x23, #8]
Lloh20:
	ldr	w8, [x8]
	bic	w10, w21, w8
	orr	w8, w8, w21
	cmp	x9, #0
	csel	w21, w10, w8, eq
LBB0_5:
Lloh21:
	adrp	x8, _LVDS_HSYNC_POLARITY@GOTPAGE
Lloh22:
	ldr	x8, [x8, _LVDS_HSYNC_POLARITY@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
Lloh24:
	adrp	x9, _LVDS_VSYNC_POLARITY@GOTPAGE
Lloh25:
	ldr	x9, [x9, _LVDS_VSYNC_POLARITY@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	orr	w10, w9, w8
	bic	w10, w21, w10
	ldr	w11, [x22]
Lloh27:
	adrp	x12, _DRM_MODE_FLAG_NHSYNC@GOTPAGE
Lloh28:
	ldr	x12, [x12, _DRM_MODE_FLAG_NHSYNC@GOTPAGEOFF]
Lloh29:
	ldr	w12, [x12]
	tst	w12, w11
	csel	w8, wzr, w8, eq
	orr	w8, w8, w10
Lloh30:
	adrp	x10, _DRM_MODE_FLAG_NVSYNC@GOTPAGE
Lloh31:
	ldr	x10, [x10, _DRM_MODE_FLAG_NVSYNC@GOTPAGEOFF]
Lloh32:
	ldr	w10, [x10]
	tst	w10, w11
	csel	w9, wzr, w9, eq
	orr	w1, w8, w9
	ldr	w0, [x19]
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_I915_WRITE
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.cfi_endproc
                                        ; -- End function
	.comm	_LVDS_PORT_EN,4,2               ; @LVDS_PORT_EN
	.comm	_LVDS_A0A2_CLKA_POWER_UP,4,2    ; @LVDS_A0A2_CLKA_POWER_UP
	.comm	_PORT_TRANS_SEL_MASK,4,2        ; @PORT_TRANS_SEL_MASK
	.comm	_LVDS_PIPEB_SELECT,4,2          ; @LVDS_PIPEB_SELECT
	.comm	_LVDS_B0B3_POWER_UP,4,2         ; @LVDS_B0B3_POWER_UP
	.comm	_LVDS_CLKB_POWER_UP,4,2         ; @LVDS_CLKB_POWER_UP
	.comm	_LVDS_ENABLE_DITHER,4,2         ; @LVDS_ENABLE_DITHER
	.comm	_LVDS_HSYNC_POLARITY,4,2        ; @LVDS_HSYNC_POLARITY
	.comm	_LVDS_VSYNC_POLARITY,4,2        ; @LVDS_VSYNC_POLARITY
	.comm	_DRM_MODE_FLAG_NHSYNC,4,2       ; @DRM_MODE_FLAG_NHSYNC
	.comm	_DRM_MODE_FLAG_NVSYNC,4,2       ; @DRM_MODE_FLAG_NVSYNC
	.no_dead_strip	_intel_pre_pll_enable_lvds
.subsections_via_symbols
