	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function r600_gpu_soft_reset
_r600_gpu_soft_reset:                   ## @r600_gpu_soft_reset
	.cfi_startproc
## %bb.0:
	testl	%esi, %esi
	je	LBB0_37
## %bb.1:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %edx
	movq	%rdi, %r13
	movl	12(%rdi), %edi
	leaq	L_.str(%rip), %rsi
	movl	%edx, -44(%rbp)                 ## 4-byte Spill
	callq	_dev_info
	movq	%r13, %rdi
	callq	_r600_print_gpu_status_regs
	movq	(%r13), %r14
	movq	_CHIP_RV770@GOTPCREL(%rip), %rax
	movq	(%rax), %r15
	movq	_R_0086D8_CP_ME_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	$1, %edi
	callq	_S_0086D8_CP_ME_HALT
	movl	%eax, %ebx
	cmpq	%r15, %r14
	jl	LBB0_3
## %bb.2:
	movl	$1, %edi
	callq	_S_0086D8_CP_PFP_HALT
	orl	%eax, %ebx
LBB0_3:
	movl	%r12d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_RLC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_RADEON_RESET_DMA@GOTPCREL(%rip), %rax
	movl	-44(%rbp), %r15d                ## 4-byte Reload
	testl	%r15d, (%rax)
	je	LBB0_5
## %bb.4:
	movq	_DMA_RB_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_DMA_RB_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32
LBB0_5:
	movl	$50, %edi
	callq	_mdelay
	leaq	-48(%rbp), %rsi
	movq	%r13, %rdi
	callq	_rv515_mc_stop
	movq	%r13, %rdi
	callq	_r600_mc_wait_for_idle
	testq	%rax, %rax
	je	LBB0_7
## %bb.6:
	movl	12(%r13), %edi
	leaq	L_.str.1(%rip), %rsi
	callq	_dev_warn
LBB0_7:
	movq	_RADEON_RESET_GFX@GOTPCREL(%rip), %rax
	movq	_RADEON_RESET_COMPUTE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	xorl	%r12d, %r12d
	movl	$0, %r14d
	testl	%r15d, %ecx
	je	LBB0_12
## %bb.8:
	movq	(%r13), %rax
	movq	_CHIP_RV770@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	movq	%r13, -56(%rbp)                 ## 8-byte Spill
	movl	$1, %edi
	jge	LBB0_9
## %bb.10:
	callq	_S_008020_SOFT_RESET_CR
	movl	%eax, %r13d
	movl	$1, %edi
	callq	_S_008020_SOFT_RESET_DB
	movl	%eax, %ebx
	orl	%r13d, %ebx
	movl	$1, %edi
	callq	_S_008020_SOFT_RESET_CB
	movl	%eax, %r14d
	movl	$1, %edi
	callq	_S_008020_SOFT_RESET_PA
	movl	%eax, %r13d
	orl	%r14d, %r13d
	orl	%ebx, %r13d
	movl	$1, %edi
	callq	_S_008020_SOFT_RESET_SC
	movl	%eax, %ebx
	movl	$1, %edi
	callq	_S_008020_SOFT_RESET_SMX
	jmp	LBB0_11
LBB0_9:
	callq	_S_008020_SOFT_RESET_DB
	movl	%eax, %ebx
	movl	$1, %edi
	callq	_S_008020_SOFT_RESET_CB
	movl	%eax, %r13d
	orl	%ebx, %r13d
	movl	$1, %edi
	callq	_S_008020_SOFT_RESET_PA
	movl	%eax, %ebx
	movl	$1, %edi
	callq	_S_008020_SOFT_RESET_SC
LBB0_11:
	movl	%eax, %r15d
	orl	%ebx, %r15d
	orl	%r13d, %r15d
	movl	$1, %edi
	callq	_S_008020_SOFT_RESET_SPI
	movl	%eax, %r13d
	movl	$1, %edi
	callq	_S_008020_SOFT_RESET_SX
	movl	%eax, %r14d
	orl	%r13d, %r14d
	movl	$1, %edi
	callq	_S_008020_SOFT_RESET_SH
	movl	%eax, %r13d
	orl	%r14d, %r13d
	movl	$1, %edi
	callq	_S_008020_SOFT_RESET_TC
	movl	%eax, %r14d
	orl	%r15d, %r14d
	movl	$1, %edi
	callq	_S_008020_SOFT_RESET_TA
	movl	%eax, %ebx
	orl	%r13d, %ebx
	orl	%r14d, %ebx
	movl	$1, %edi
	callq	_S_008020_SOFT_RESET_VC
	movl	%eax, %r15d
	movl	$1, %edi
	callq	_S_008020_SOFT_RESET_VGT
	movl	%eax, %r14d
	orl	%r15d, %r14d
	orl	%ebx, %r14d
	movq	-56(%rbp), %r13                 ## 8-byte Reload
	movl	-44(%rbp), %r15d                ## 4-byte Reload
LBB0_12:
	movq	_RADEON_RESET_CP@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_14
## %bb.13:
	movl	$1, %edi
	callq	_S_008020_SOFT_RESET_CP
	movl	%eax, %ebx
	movl	$1, %edi
	callq	_S_008020_SOFT_RESET_VGT
	orl	%r14d, %ebx
	orl	%eax, %ebx
	movl	$1, %edi
	callq	_S_000E60_SOFT_RESET_GRBM
	movl	%eax, %r12d
	movl	%ebx, %r14d
LBB0_14:
	movq	_RADEON_RESET_DMA@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_19
## %bb.15:
	movq	(%r13), %rax
	movq	_CHIP_RV770@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_16
## %bb.17:
	movq	_SOFT_RESET_DMA@GOTPCREL(%rip), %rax
	jmp	LBB0_18
LBB0_16:
	movq	_RV770_SOFT_RESET_DMA@GOTPCREL(%rip), %rax
LBB0_18:
	orl	(%rax), %r12d
LBB0_19:
	movq	_RADEON_RESET_RLC@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_21
## %bb.20:
	movl	$1, %edi
	callq	_S_000E60_SOFT_RESET_RLC
	orl	%eax, %r12d
LBB0_21:
	movq	_RADEON_RESET_SEM@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_23
## %bb.22:
	movl	$1, %edi
	callq	_S_000E60_SOFT_RESET_SEM
	orl	%eax, %r12d
LBB0_23:
	movq	_RADEON_RESET_IH@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_25
## %bb.24:
	movl	$1, %edi
	callq	_S_000E60_SOFT_RESET_IH
	orl	%eax, %r12d
LBB0_25:
	movq	_RADEON_RESET_GRBM@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_27
## %bb.26:
	movl	$1, %edi
	callq	_S_000E60_SOFT_RESET_GRBM
	orl	%eax, %r12d
LBB0_27:
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 8(%r13)
	jne	LBB0_30
## %bb.28:
	movq	_RADEON_RESET_MC@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_30
## %bb.29:
	movl	$1, %edi
	callq	_S_000E60_SOFT_RESET_MC
	orl	%eax, %r12d
LBB0_30:
	movq	_RADEON_RESET_VMC@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_32
## %bb.31:
	movl	$1, %edi
	callq	_S_000E60_SOFT_RESET_VMC
	orl	%eax, %r12d
LBB0_32:
	testl	%r14d, %r14d
	je	LBB0_34
## %bb.33:
	movq	_R_008020_GRBM_SOFT_RESET@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32
	movl	%eax, %ebx
	orl	%r14d, %ebx
	movl	12(%r13), %edi
	leaq	L_.str.2(%rip), %rsi
	movl	%ebx, %edx
	callq	_dev_info
	movl	(%r15), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r15), %edi
	callq	_RREG32
	movl	%eax, %ebx
	movl	$50, %edi
	callq	_udelay
	notl	%r14d
	andl	%ebx, %r14d
	movl	(%r15), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movl	(%r15), %edi
	callq	_RREG32
LBB0_34:
	testl	%r12d, %r12d
	je	LBB0_36
## %bb.35:
	movq	_SRBM_SOFT_RESET@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32
	movl	%eax, %ebx
	orl	%r12d, %ebx
	movl	12(%r13), %edi
	leaq	L_.str.3(%rip), %rsi
	movl	%ebx, %edx
	callq	_dev_info
	movl	(%r14), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r14), %edi
	callq	_RREG32
	movl	%eax, %ebx
	movl	$50, %edi
	callq	_udelay
	notl	%r12d
	andl	%ebx, %r12d
	movl	(%r14), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movl	(%r14), %edi
	callq	_RREG32
LBB0_36:
	movl	$1, %edi
	callq	_mdelay
	leaq	-48(%rbp), %rsi
	movq	%r13, %rdi
	callq	_rv515_mc_resume
	movl	$50, %edi
	callq	_udelay
	movq	%r13, %rdi
	callq	_r600_print_gpu_status_regs
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
LBB0_37:
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"GPU softreset: 0x%08X\n"

	.comm	_CHIP_RV770,8,3                 ## @CHIP_RV770
	.comm	_R_0086D8_CP_ME_CNTL,4,2        ## @R_0086D8_CP_ME_CNTL
	.comm	_RLC_CNTL,4,2                   ## @RLC_CNTL
	.comm	_RADEON_RESET_DMA,4,2           ## @RADEON_RESET_DMA
	.comm	_DMA_RB_CNTL,4,2                ## @DMA_RB_CNTL
	.comm	_DMA_RB_ENABLE,4,2              ## @DMA_RB_ENABLE
L_.str.1:                               ## @.str.1
	.asciz	"Wait for MC idle timedout !\n"

	.comm	_RADEON_RESET_GFX,4,2           ## @RADEON_RESET_GFX
	.comm	_RADEON_RESET_COMPUTE,4,2       ## @RADEON_RESET_COMPUTE
	.comm	_RADEON_RESET_CP,4,2            ## @RADEON_RESET_CP
	.comm	_RV770_SOFT_RESET_DMA,4,2       ## @RV770_SOFT_RESET_DMA
	.comm	_SOFT_RESET_DMA,4,2             ## @SOFT_RESET_DMA
	.comm	_RADEON_RESET_RLC,4,2           ## @RADEON_RESET_RLC
	.comm	_RADEON_RESET_SEM,4,2           ## @RADEON_RESET_SEM
	.comm	_RADEON_RESET_IH,4,2            ## @RADEON_RESET_IH
	.comm	_RADEON_RESET_GRBM,4,2          ## @RADEON_RESET_GRBM
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
	.comm	_RADEON_RESET_MC,4,2            ## @RADEON_RESET_MC
	.comm	_RADEON_RESET_VMC,4,2           ## @RADEON_RESET_VMC
	.comm	_R_008020_GRBM_SOFT_RESET,4,2   ## @R_008020_GRBM_SOFT_RESET
L_.str.2:                               ## @.str.2
	.asciz	"R_008020_GRBM_SOFT_RESET=0x%08X\n"

	.comm	_SRBM_SOFT_RESET,4,2            ## @SRBM_SOFT_RESET
L_.str.3:                               ## @.str.3
	.asciz	"SRBM_SOFT_RESET=0x%08X\n"

	.no_dead_strip	_r600_gpu_soft_reset
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function r600_gpu_soft_reset
_r600_gpu_soft_reset:                   ; @r600_gpu_soft_reset
	.cfi_startproc
; %bb.0:
	cbz	w1, LBB0_39
; %bb.1:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x1
	mov	x19, x0
	ldr	w0, [x0, #12]
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	mov	x2, x20
	bl	_dev_info
	mov	x0, x19
	bl	_r600_print_gpu_status_regs
	ldr	x24, [x19]
Lloh2:
	adrp	x23, _CHIP_RV770@GOTPAGE
Lloh3:
	ldr	x23, [x23, _CHIP_RV770@GOTPAGEOFF]
	ldr	x25, [x23]
Lloh4:
	adrp	x8, _R_0086D8_CP_ME_CNTL@GOTPAGE
Lloh5:
	ldr	x8, [x8, _R_0086D8_CP_ME_CNTL@GOTPAGEOFF]
Lloh6:
	ldr	w21, [x8]
	mov	w0, #1
	bl	_S_0086D8_CP_ME_HALT
	mov	x22, x0
	cmp	x24, x25
	b.lt	LBB0_3
; %bb.2:
	mov	w0, #1
	bl	_S_0086D8_CP_PFP_HALT
	orr	w22, w0, w22
LBB0_3:
	mov	x0, x21
	mov	x1, x22
	bl	_WREG32
Lloh7:
	adrp	x8, _RLC_CNTL@GOTPAGE
Lloh8:
	ldr	x8, [x8, _RLC_CNTL@GOTPAGEOFF]
Lloh9:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh10:
	adrp	x24, _RADEON_RESET_DMA@GOTPAGE
Lloh11:
	ldr	x24, [x24, _RADEON_RESET_DMA@GOTPAGEOFF]
	ldr	w8, [x24]
	tst	w8, w20
	b.eq	LBB0_5
; %bb.4:
Lloh12:
	adrp	x21, _DMA_RB_CNTL@GOTPAGE
Lloh13:
	ldr	x21, [x21, _DMA_RB_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
Lloh14:
	adrp	x8, _DMA_RB_ENABLE@GOTPAGE
Lloh15:
	ldr	x8, [x8, _DMA_RB_ENABLE@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w0, [x21]
	bl	_WREG32
LBB0_5:
	mov	w0, #50
	bl	_mdelay
	add	x1, sp, #8
	mov	x0, x19
	bl	_rv515_mc_stop
	mov	x0, x19
	bl	_r600_mc_wait_for_idle
	cbz	x0, LBB0_7
; %bb.6:
	ldr	w0, [x19, #12]
Lloh17:
	adrp	x1, l_.str.1@PAGE
Lloh18:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_warn
LBB0_7:
Lloh19:
	adrp	x8, _RADEON_RESET_GFX@GOTPAGE
Lloh20:
	ldr	x8, [x8, _RADEON_RESET_GFX@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
Lloh22:
	adrp	x9, _RADEON_RESET_COMPUTE@GOTPAGE
Lloh23:
	ldr	x9, [x9, _RADEON_RESET_COMPUTE@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	orr	w8, w9, w8
	tst	w8, w20
	b.eq	LBB0_10
; %bb.8:
	ldr	x8, [x19]
	ldr	x9, [x23]
	mov	w0, #1
	cmp	x8, x9
	b.ge	LBB0_11
; %bb.9:
	bl	_S_008020_SOFT_RESET_CR
	mov	x21, x0
	mov	w0, #1
	bl	_S_008020_SOFT_RESET_DB
	orr	w21, w0, w21
	mov	w0, #1
	bl	_S_008020_SOFT_RESET_CB
	orr	w21, w21, w0
	mov	w0, #1
	bl	_S_008020_SOFT_RESET_PA
	orr	w21, w21, w0
	mov	w0, #1
	bl	_S_008020_SOFT_RESET_SC
	orr	w21, w21, w0
	mov	w0, #1
	bl	_S_008020_SOFT_RESET_SMX
	b	LBB0_12
LBB0_10:
	mov	w22, #0
	b	LBB0_13
LBB0_11:
	bl	_S_008020_SOFT_RESET_DB
	mov	x21, x0
	mov	w0, #1
	bl	_S_008020_SOFT_RESET_CB
	orr	w21, w0, w21
	mov	w0, #1
	bl	_S_008020_SOFT_RESET_PA
	orr	w21, w21, w0
	mov	w0, #1
	bl	_S_008020_SOFT_RESET_SC
LBB0_12:
	orr	w21, w21, w0
	mov	w0, #1
	bl	_S_008020_SOFT_RESET_SPI
	orr	w21, w21, w0
	mov	w0, #1
	bl	_S_008020_SOFT_RESET_SX
	orr	w21, w21, w0
	mov	w0, #1
	bl	_S_008020_SOFT_RESET_SH
	orr	w21, w21, w0
	mov	w0, #1
	bl	_S_008020_SOFT_RESET_TC
	orr	w21, w21, w0
	mov	w0, #1
	bl	_S_008020_SOFT_RESET_TA
	orr	w21, w21, w0
	mov	w0, #1
	bl	_S_008020_SOFT_RESET_VC
	orr	w21, w21, w0
	mov	w0, #1
	bl	_S_008020_SOFT_RESET_VGT
	orr	w22, w21, w0
LBB0_13:
Lloh25:
	adrp	x8, _RADEON_RESET_CP@GOTPAGE
Lloh26:
	ldr	x8, [x8, _RADEON_RESET_CP@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_15
; %bb.14:
	mov	w0, #1
	bl	_S_008020_SOFT_RESET_CP
	mov	x21, x0
	mov	w0, #1
	bl	_S_008020_SOFT_RESET_VGT
	orr	w8, w21, w22
	orr	w22, w8, w0
	mov	w0, #1
	bl	_S_000E60_SOFT_RESET_GRBM
	mov	x21, x0
	b	LBB0_16
LBB0_15:
	mov	w21, #0
LBB0_16:
	ldr	w8, [x24]
	tst	w8, w20
	b.eq	LBB0_21
; %bb.17:
	ldr	x8, [x19]
	ldr	x9, [x23]
	cmp	x8, x9
	b.ge	LBB0_19
; %bb.18:
Lloh28:
	adrp	x8, _SOFT_RESET_DMA@GOTPAGE
Lloh29:
	ldr	x8, [x8, _SOFT_RESET_DMA@GOTPAGEOFF]
	b	LBB0_20
LBB0_19:
Lloh30:
	adrp	x8, _RV770_SOFT_RESET_DMA@GOTPAGE
Lloh31:
	ldr	x8, [x8, _RV770_SOFT_RESET_DMA@GOTPAGEOFF]
LBB0_20:
	ldr	w8, [x8]
	orr	w21, w8, w21
LBB0_21:
Lloh32:
	adrp	x8, _RADEON_RESET_RLC@GOTPAGE
Lloh33:
	ldr	x8, [x8, _RADEON_RESET_RLC@GOTPAGEOFF]
Lloh34:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_23
; %bb.22:
	mov	w0, #1
	bl	_S_000E60_SOFT_RESET_RLC
	orr	w21, w0, w21
LBB0_23:
Lloh35:
	adrp	x8, _RADEON_RESET_SEM@GOTPAGE
Lloh36:
	ldr	x8, [x8, _RADEON_RESET_SEM@GOTPAGEOFF]
Lloh37:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_25
; %bb.24:
	mov	w0, #1
	bl	_S_000E60_SOFT_RESET_SEM
	orr	w21, w0, w21
LBB0_25:
Lloh38:
	adrp	x8, _RADEON_RESET_IH@GOTPAGE
Lloh39:
	ldr	x8, [x8, _RADEON_RESET_IH@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_27
; %bb.26:
	mov	w0, #1
	bl	_S_000E60_SOFT_RESET_IH
	orr	w21, w0, w21
LBB0_27:
Lloh41:
	adrp	x8, _RADEON_RESET_GRBM@GOTPAGE
Lloh42:
	ldr	x8, [x8, _RADEON_RESET_GRBM@GOTPAGEOFF]
Lloh43:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_29
; %bb.28:
	mov	w0, #1
	bl	_S_000E60_SOFT_RESET_GRBM
	orr	w21, w0, w21
LBB0_29:
	ldr	w8, [x19, #8]
Lloh44:
	adrp	x9, _RADEON_IS_IGP@GOTPAGE
Lloh45:
	ldr	x9, [x9, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_32
; %bb.30:
Lloh47:
	adrp	x8, _RADEON_RESET_MC@GOTPAGE
Lloh48:
	ldr	x8, [x8, _RADEON_RESET_MC@GOTPAGEOFF]
Lloh49:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_32
; %bb.31:
	mov	w0, #1
	bl	_S_000E60_SOFT_RESET_MC
	orr	w21, w0, w21
LBB0_32:
Lloh50:
	adrp	x8, _RADEON_RESET_VMC@GOTPAGE
Lloh51:
	ldr	x8, [x8, _RADEON_RESET_VMC@GOTPAGEOFF]
Lloh52:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_34
; %bb.33:
	mov	w0, #1
	bl	_S_000E60_SOFT_RESET_VMC
	orr	w21, w0, w21
LBB0_34:
	cbz	w22, LBB0_36
; %bb.35:
Lloh53:
	adrp	x23, _R_008020_GRBM_SOFT_RESET@GOTPAGE
Lloh54:
	ldr	x23, [x23, _R_008020_GRBM_SOFT_RESET@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32
	orr	w20, w0, w22
	ldr	w0, [x19, #12]
Lloh55:
	adrp	x1, l_.str.2@PAGE
Lloh56:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x2, x20
	bl	_dev_info
	ldr	w0, [x23]
	mov	x1, x20
	bl	_WREG32
	ldr	w0, [x23]
	bl	_RREG32
	mov	x20, x0
	mov	w0, #50
	bl	_udelay
	bic	w1, w20, w22
	ldr	w0, [x23]
	bl	_WREG32
	ldr	w0, [x23]
	bl	_RREG32
LBB0_36:
	cbz	w21, LBB0_38
; %bb.37:
Lloh57:
	adrp	x22, _SRBM_SOFT_RESET@GOTPAGE
Lloh58:
	ldr	x22, [x22, _SRBM_SOFT_RESET@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_RREG32
	orr	w20, w0, w21
	ldr	w0, [x19, #12]
Lloh59:
	adrp	x1, l_.str.3@PAGE
Lloh60:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x2, x20
	bl	_dev_info
	ldr	w0, [x22]
	mov	x1, x20
	bl	_WREG32
	ldr	w0, [x22]
	bl	_RREG32
	mov	x20, x0
	mov	w0, #50
	bl	_udelay
	bic	w1, w20, w21
	ldr	w0, [x22]
	bl	_WREG32
	ldr	w0, [x22]
	bl	_RREG32
LBB0_38:
	mov	w0, #1
	bl	_mdelay
	add	x1, sp, #8
	mov	x0, x19
	bl	_rv515_mc_resume
	mov	w0, #50
	bl	_udelay
	mov	x0, x19
	bl	_r600_print_gpu_status_regs
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
LBB0_39:
	.cfi_def_cfa wsp, 0
	.cfi_same_value w30
	.cfi_same_value w29
	.cfi_same_value w19
	.cfi_same_value w20
	.cfi_same_value w21
	.cfi_same_value w22
	.cfi_same_value w23
	.cfi_same_value w24
	.cfi_same_value w25
	.cfi_same_value w26
	ret
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpAdd	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpAdd	Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpAdd	Lloh59, Lloh60
	.loh AdrpLdrGot	Lloh57, Lloh58
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"GPU softreset: 0x%08X\n"

	.comm	_CHIP_RV770,8,3                 ; @CHIP_RV770
	.comm	_R_0086D8_CP_ME_CNTL,4,2        ; @R_0086D8_CP_ME_CNTL
	.comm	_RLC_CNTL,4,2                   ; @RLC_CNTL
	.comm	_RADEON_RESET_DMA,4,2           ; @RADEON_RESET_DMA
	.comm	_DMA_RB_CNTL,4,2                ; @DMA_RB_CNTL
	.comm	_DMA_RB_ENABLE,4,2              ; @DMA_RB_ENABLE
l_.str.1:                               ; @.str.1
	.asciz	"Wait for MC idle timedout !\n"

	.comm	_RADEON_RESET_GFX,4,2           ; @RADEON_RESET_GFX
	.comm	_RADEON_RESET_COMPUTE,4,2       ; @RADEON_RESET_COMPUTE
	.comm	_RADEON_RESET_CP,4,2            ; @RADEON_RESET_CP
	.comm	_RV770_SOFT_RESET_DMA,4,2       ; @RV770_SOFT_RESET_DMA
	.comm	_SOFT_RESET_DMA,4,2             ; @SOFT_RESET_DMA
	.comm	_RADEON_RESET_RLC,4,2           ; @RADEON_RESET_RLC
	.comm	_RADEON_RESET_SEM,4,2           ; @RADEON_RESET_SEM
	.comm	_RADEON_RESET_IH,4,2            ; @RADEON_RESET_IH
	.comm	_RADEON_RESET_GRBM,4,2          ; @RADEON_RESET_GRBM
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
	.comm	_RADEON_RESET_MC,4,2            ; @RADEON_RESET_MC
	.comm	_RADEON_RESET_VMC,4,2           ; @RADEON_RESET_VMC
	.comm	_R_008020_GRBM_SOFT_RESET,4,2   ; @R_008020_GRBM_SOFT_RESET
l_.str.2:                               ; @.str.2
	.asciz	"R_008020_GRBM_SOFT_RESET=0x%08X\n"

	.comm	_SRBM_SOFT_RESET,4,2            ; @SRBM_SOFT_RESET
l_.str.3:                               ; @.str.3
	.asciz	"SRBM_SOFT_RESET=0x%08X\n"

	.no_dead_strip	_r600_gpu_soft_reset
.subsections_via_symbols
