	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function nforce3_agp_init
_nforce3_agp_init:                      ## @nforce3_agp_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	xorl	%ebx, %ebx
	xorl	%eax, %eax
	callq	_amd64_fetch_size
	movl	%eax, %r13d
	leaq	L_.str(%rip), %rsi
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	_dev_info
	movl	4(%r15), %r14d
	movl	$11, %edi
	xorl	%esi, %esi
	callq	_PCI_DEVFN
	movl	%r14d, %edi
	movl	%eax, %esi
	callq	_pci_get_slot
	testq	%rax, %rax
	je	LBB0_13
## %bb.1:
	movq	%rax, %r14
	movq	_nforce3_sizes@GOTPCREL(%rip), %r12
	movq	(%r12), %rdi
	callq	_ARRAY_SIZE
	testl	%eax, %eax
	jle	LBB0_5
## %bb.2:
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movq	(%r12), %rdi
	cmpl	%r13d, (%rdi,%rbx,8)
	je	LBB0_5
## %bb.4:                               ##   in Loop: Header=BB0_3 Depth=1
	incq	%rbx
	callq	_ARRAY_SIZE
	cltq
	cmpq	%rax, %rbx
	jl	LBB0_3
LBB0_5:
	movq	(%r12), %rdi
	callq	_ARRAY_SIZE
	cmpl	%eax, %ebx
	jne	LBB0_7
## %bb.6:
	leaq	L_.str.2(%rip), %rsi
	xorl	%r12d, %r12d
	movq	%r15, %rdi
	movl	%r13d, %edx
	xorl	%eax, %eax
	callq	_dev_info
	jmp	LBB0_10
LBB0_13:
	leaq	L_.str.1(%rip), %rsi
	xorl	%r12d, %r12d
	jmp	LBB0_9
LBB0_7:
	movq	_NVIDIA_X86_64_1_APSIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-48(%rbp), %rdx
	movq	%r14, %rdi
	callq	_pci_read_config_dword
	movl	-48(%rbp), %edx
	andl	$-16, %edx
	movl	%edx, -48(%rbp)
	movq	(%r12), %rax
	movl	%ebx, %ecx
	orl	4(%rax,%rcx,8), %edx
	movl	%edx, -48(%rbp)
	movq	_NVIDIA_X86_64_1_APSIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_pci_write_config_dword
	xorl	%r12d, %r12d
	xorl	%edi, %edi
	callq	_node_to_amd_nb
	movq	(%rax), %rdi
	movq	_AMD64_GARTAPERTUREBASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-44(%rbp), %rdx
	callq	_pci_read_config_dword
	movl	-44(%rbp), %eax
	testl	$32640, %eax                    ## imm = 0x7F80
	je	LBB0_11
## %bb.8:
	leaq	L_.str.3(%rip), %rsi
LBB0_9:
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	_dev_info
LBB0_10:
	movq	_ENODEV@GOTPCREL(%rip), %rax
	subl	(%rax), %r12d
LBB0_12:
	movl	%r12d, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_11:
	shll	$25, %eax
	movl	%eax, -44(%rbp)
	movq	_NVIDIA_X86_64_0_APBASE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	leaq	-52(%rbp), %rdx
	movq	%r15, %rdi
	callq	_pci_read_config_dword
	movq	_PCI_BASE_ADDRESS_MEM_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	andl	-52(%rbp), %edx
	orl	-44(%rbp), %edx
	movl	%edx, -52(%rbp)
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_pci_write_config_dword
	movl	-44(%rbp), %edx
	shll	$20, %r13d
	leal	(%rdx,%r13), %ebx
	decl	%ebx
	movq	_NVIDIA_X86_64_1_APBASE1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
                                        ## kill: def $edx killed $edx killed $rdx
	callq	_pci_write_config_dword
	movq	_NVIDIA_X86_64_1_APLIMIT1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%ebx, %edx
	callq	_pci_write_config_dword
	movq	_NVIDIA_X86_64_1_APBASE2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-44(%rbp), %edx
	movq	%r14, %rdi
	callq	_pci_write_config_dword
	movq	_NVIDIA_X86_64_1_APLIMIT2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%ebx, %edx
	callq	_pci_write_config_dword
	movq	%r14, %rdi
	callq	_pci_dev_put
	jmp	LBB0_12
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"setting up Nforce3 AGP\n"

L_.str.1:                               ## @.str.1
	.asciz	"can't find Nforce3 secondary device\n"

	.comm	_ENODEV,4,2                     ## @ENODEV
	.comm	_nforce3_sizes,8,3              ## @nforce3_sizes
L_.str.2:                               ## @.str.2
	.asciz	"no NForce3 size found for %d\n"

	.comm	_NVIDIA_X86_64_1_APSIZE,4,2     ## @NVIDIA_X86_64_1_APSIZE
	.comm	_AMD64_GARTAPERTUREBASE,4,2     ## @AMD64_GARTAPERTUREBASE
L_.str.3:                               ## @.str.3
	.asciz	"aperture base > 4G\n"

	.comm	_NVIDIA_X86_64_0_APBASE,4,2     ## @NVIDIA_X86_64_0_APBASE
	.comm	_PCI_BASE_ADDRESS_MEM_MASK,4,2  ## @PCI_BASE_ADDRESS_MEM_MASK
	.comm	_NVIDIA_X86_64_1_APBASE1,4,2    ## @NVIDIA_X86_64_1_APBASE1
	.comm	_NVIDIA_X86_64_1_APLIMIT1,4,2   ## @NVIDIA_X86_64_1_APLIMIT1
	.comm	_NVIDIA_X86_64_1_APBASE2,4,2    ## @NVIDIA_X86_64_1_APBASE2
	.comm	_NVIDIA_X86_64_1_APLIMIT2,4,2   ## @NVIDIA_X86_64_1_APLIMIT2
	.no_dead_strip	_nforce3_agp_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function nforce3_agp_init
_nforce3_agp_init:                      ; @nforce3_agp_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x0
	bl	_amd64_fetch_size
	mov	x21, x0
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x20
	bl	_dev_info
	ldr	w19, [x20, #4]
	mov	w0, #11
	mov	w1, #0
	bl	_PCI_DEVFN
	mov	x1, x0
	mov	x0, x19
	bl	_pci_get_slot
	cbz	x0, LBB0_5
; %bb.1:
	mov	x19, x0
Lloh2:
	adrp	x22, _nforce3_sizes@GOTPAGE
Lloh3:
	ldr	x22, [x22, _nforce3_sizes@GOTPAGEOFF]
	ldr	x0, [x22]
	bl	_ARRAY_SIZE
	cmp	w0, #1
	b.lt	LBB0_6
; %bb.2:
	mov	x24, #0
	mov	x23, #0
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x0, [x22]
	ldr	w8, [x0, x24]
	cmp	w8, w21
	b.eq	LBB0_7
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	add	x23, x23, #1
	bl	_ARRAY_SIZE
	add	x24, x24, #8
	cmp	x23, w0, sxtw
	b.lt	LBB0_3
	b	LBB0_7
LBB0_5:
Lloh4:
	adrp	x1, l_.str.1@PAGE
Lloh5:
	add	x1, x1, l_.str.1@PAGEOFF
	b	LBB0_11
LBB0_6:
	mov	w23, #0
LBB0_7:
	ldr	x0, [x22]
	bl	_ARRAY_SIZE
	cmp	w23, w0
	b.ne	LBB0_9
; %bb.8:
	str	x21, [sp]
Lloh6:
	adrp	x1, l_.str.2@PAGE
Lloh7:
	add	x1, x1, l_.str.2@PAGEOFF
	b	LBB0_11
LBB0_9:
Lloh8:
	adrp	x24, _NVIDIA_X86_64_1_APSIZE@GOTPAGE
Lloh9:
	ldr	x24, [x24, _NVIDIA_X86_64_1_APSIZE@GOTPAGEOFF]
	ldr	w1, [x24]
	add	x2, sp, #28
	mov	x0, x19
	bl	_pci_read_config_dword
	ldr	w8, [sp, #28]
	and	w8, w8, #0xfffffff0
	str	w8, [sp, #28]
	ldr	x9, [x22]
	add	x9, x9, w23, uxtw #3
	ldr	w9, [x9, #4]
	orr	w2, w9, w8
	str	w2, [sp, #28]
	ldr	w1, [x24]
	mov	x0, x19
	bl	_pci_write_config_dword
	mov	w0, #0
	bl	_node_to_amd_nb
	ldr	x0, [x0]
Lloh10:
	adrp	x8, _AMD64_GARTAPERTUREBASE@GOTPAGE
Lloh11:
	ldr	x8, [x8, _AMD64_GARTAPERTUREBASE@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
	add	x2, sp, #24
	bl	_pci_read_config_dword
	ldr	w8, [sp, #24]
	tst	w8, #0x7f80
	b.eq	LBB0_13
; %bb.10:
Lloh13:
	adrp	x1, l_.str.3@PAGE
Lloh14:
	add	x1, x1, l_.str.3@PAGEOFF
LBB0_11:
	mov	x0, x20
	bl	_dev_info
Lloh15:
	adrp	x8, _ENODEV@GOTPAGE
Lloh16:
	ldr	x8, [x8, _ENODEV@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_12:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_13:
	lsl	w8, w8, #25
	str	w8, [sp, #24]
Lloh18:
	adrp	x22, _NVIDIA_X86_64_0_APBASE@GOTPAGE
Lloh19:
	ldr	x22, [x22, _NVIDIA_X86_64_0_APBASE@GOTPAGEOFF]
	ldr	w1, [x22]
	add	x2, sp, #20
	mov	x0, x20
	bl	_pci_read_config_dword
Lloh20:
	adrp	x8, _PCI_BASE_ADDRESS_MEM_MASK@GOTPAGE
Lloh21:
	ldr	x8, [x8, _PCI_BASE_ADDRESS_MEM_MASK@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
	ldr	w9, [sp, #20]
	bic	w8, w9, w8
	ldr	w9, [sp, #24]
	orr	w2, w9, w8
	str	w2, [sp, #20]
	ldr	w1, [x22]
	mov	x0, x20
	bl	_pci_write_config_dword
	ldr	w2, [sp, #24]
	add	w8, w2, w21, lsl #20
	sub	w20, w8, #1
Lloh23:
	adrp	x8, _NVIDIA_X86_64_1_APBASE1@GOTPAGE
Lloh24:
	ldr	x8, [x8, _NVIDIA_X86_64_1_APBASE1@GOTPAGEOFF]
Lloh25:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_pci_write_config_dword
Lloh26:
	adrp	x8, _NVIDIA_X86_64_1_APLIMIT1@GOTPAGE
Lloh27:
	ldr	x8, [x8, _NVIDIA_X86_64_1_APLIMIT1@GOTPAGEOFF]
Lloh28:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_pci_write_config_dword
Lloh29:
	adrp	x8, _NVIDIA_X86_64_1_APBASE2@GOTPAGE
Lloh30:
	ldr	x8, [x8, _NVIDIA_X86_64_1_APBASE2@GOTPAGEOFF]
Lloh31:
	ldr	w1, [x8]
	ldr	w2, [sp, #24]
	mov	x0, x19
	bl	_pci_write_config_dword
Lloh32:
	adrp	x8, _NVIDIA_X86_64_1_APLIMIT2@GOTPAGE
Lloh33:
	ldr	x8, [x8, _NVIDIA_X86_64_1_APLIMIT2@GOTPAGEOFF]
Lloh34:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_pci_write_config_dword
	mov	x0, x19
	bl	_pci_dev_put
	mov	w0, #0
	b	LBB0_12
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpAdd	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh18, Lloh19
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"setting up Nforce3 AGP\n"

l_.str.1:                               ; @.str.1
	.asciz	"can't find Nforce3 secondary device\n"

	.comm	_ENODEV,4,2                     ; @ENODEV
	.comm	_nforce3_sizes,8,3              ; @nforce3_sizes
l_.str.2:                               ; @.str.2
	.asciz	"no NForce3 size found for %d\n"

	.comm	_NVIDIA_X86_64_1_APSIZE,4,2     ; @NVIDIA_X86_64_1_APSIZE
	.comm	_AMD64_GARTAPERTUREBASE,4,2     ; @AMD64_GARTAPERTUREBASE
l_.str.3:                               ; @.str.3
	.asciz	"aperture base > 4G\n"

	.comm	_NVIDIA_X86_64_0_APBASE,4,2     ; @NVIDIA_X86_64_0_APBASE
	.comm	_PCI_BASE_ADDRESS_MEM_MASK,4,2  ; @PCI_BASE_ADDRESS_MEM_MASK
	.comm	_NVIDIA_X86_64_1_APBASE1,4,2    ; @NVIDIA_X86_64_1_APBASE1
	.comm	_NVIDIA_X86_64_1_APLIMIT1,4,2   ; @NVIDIA_X86_64_1_APLIMIT1
	.comm	_NVIDIA_X86_64_1_APBASE2,4,2    ; @NVIDIA_X86_64_1_APBASE2
	.comm	_NVIDIA_X86_64_1_APLIMIT2,4,2   ; @NVIDIA_X86_64_1_APLIMIT2
	.no_dead_strip	_nforce3_agp_init
.subsections_via_symbols
