	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function intel_bts_constraints
_intel_bts_constraints:                 ## @intel_bts_constraints
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	xorl	%ebx, %ebx
	cmpq	$0, (%rdi)
	jne	LBB0_5
## %bb.1:
	movq	%rdi, %r14
	movq	_INTEL_ARCH_EVENT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	andl	8(%rdi), %r15d
	movq	_x86_pmu@GOTPCREL(%rip), %rax
	movq	_PERF_COUNT_HW_BRANCH_INSTRUCTIONS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	callq	*(%rax)
	cmpl	%eax, %r15d
	jne	LBB0_3
## %bb.2:
	xorl	%ebx, %ebx
	cmpl	$1, 12(%r14)
	sete	%bl
LBB0_3:
	movl	%ebx, %edi
	callq	_unlikely
	movq	%rax, %rbx
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	movq	_bts_constraint@GOTPCREL(%rip), %rbx
LBB0_5:
	movq	%rbx, %rax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_INTEL_ARCH_EVENT_MASK,4,2      ## @INTEL_ARCH_EVENT_MASK
	.comm	_x86_pmu,8,3                    ## @x86_pmu
	.comm	_PERF_COUNT_HW_BRANCH_INSTRUCTIONS,4,2 ## @PERF_COUNT_HW_BRANCH_INSTRUCTIONS
	.comm	_bts_constraint,4,2             ## @bts_constraint
	.no_dead_strip	_intel_bts_constraints
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function intel_bts_constraints
_intel_bts_constraints:                 ; @intel_bts_constraints
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	x8, [x0]
	cbz	x8, LBB0_2
; %bb.1:
	mov	x0, #0
	b	LBB0_6
LBB0_2:
	mov	x19, x0
	ldr	w8, [x0, #8]
Lloh0:
	adrp	x9, _INTEL_ARCH_EVENT_MASK@GOTPAGE
Lloh1:
	ldr	x9, [x9, _INTEL_ARCH_EVENT_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	and	w20, w9, w8
Lloh3:
	adrp	x8, _x86_pmu@GOTPAGE
Lloh4:
	ldr	x8, [x8, _x86_pmu@GOTPAGEOFF]
Lloh5:
	ldr	x8, [x8]
Lloh6:
	adrp	x9, _PERF_COUNT_HW_BRANCH_INSTRUCTIONS@GOTPAGE
Lloh7:
	ldr	x9, [x9, _PERF_COUNT_HW_BRANCH_INSTRUCTIONS@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x9]
	blr	x8
	cmp	w20, w0
	b.ne	LBB0_4
; %bb.3:
	ldr	w8, [x19, #12]
	cmp	w8, #1
	cset	w0, eq
	b	LBB0_5
LBB0_4:
	mov	w0, #0
LBB0_5:
	bl	_unlikely
Lloh9:
	adrp	x8, _bts_constraint@GOTPAGE
Lloh10:
	ldr	x8, [x8, _bts_constraint@GOTPAGEOFF]
	cmp	x0, #0
	csel	x0, xzr, x8, eq
LBB0_6:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh9, Lloh10
	.cfi_endproc
                                        ; -- End function
	.comm	_INTEL_ARCH_EVENT_MASK,4,2      ; @INTEL_ARCH_EVENT_MASK
	.comm	_x86_pmu,8,3                    ; @x86_pmu
	.comm	_PERF_COUNT_HW_BRANCH_INSTRUCTIONS,4,2 ; @PERF_COUNT_HW_BRANCH_INSTRUCTIONS
	.comm	_bts_constraint,4,2             ; @bts_constraint
	.no_dead_strip	_intel_bts_constraints
.subsections_via_symbols
