	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ironlake_set_pll_edp
_ironlake_set_pll_edp:                  ## @ironlake_set_pll_edp
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	leaq	L_.str(%rip), %rdi
	xorl	%eax, %eax
	callq	_DRM_DEBUG_KMS
	movq	_DP_A@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_I915_READ
	movl	%eax, %ebx
	movq	_DP_PLL_FREQ_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	cmpl	$199999, %r14d                  ## imm = 0x30D3F
	jg	LBB0_1
## %bb.2:
	leaq	L_.str.1(%rip), %rdi
	xorl	%eax, %eax
	callq	_DRM_DEBUG_KMS
	movq	_DP_PLL_FREQ_160MHZ@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_1:
	movq	_DP_PLL_FREQ_270MHZ@GOTPCREL(%rip), %rax
LBB0_3:
	notl	%r12d
	andl	%r12d, %ebx
	orl	(%rax), %ebx
	movl	(%r15), %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movl	(%r15), %edi
	callq	_POSTING_READ
	movl	$500, %edi                      ## imm = 0x1F4
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_udelay                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"eDP PLL enable for clock %d\n"

	.comm	_DP_A,4,2                       ## @DP_A
	.comm	_DP_PLL_FREQ_MASK,4,2           ## @DP_PLL_FREQ_MASK
L_.str.1:                               ## @.str.1
	.asciz	"160MHz cpu eDP clock, might need ilk devA w/a\n"

	.comm	_DP_PLL_FREQ_160MHZ,4,2         ## @DP_PLL_FREQ_160MHZ
	.comm	_DP_PLL_FREQ_270MHZ,4,2         ## @DP_PLL_FREQ_270MHZ
	.no_dead_strip	_ironlake_set_pll_edp
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ironlake_set_pll_edp
_ironlake_set_pll_edp:                  ; @ironlake_set_pll_edp
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	str	x20, [sp]
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_KMS
Lloh2:
	adrp	x21, _DP_A@GOTPAGE
Lloh3:
	ldr	x21, [x21, _DP_A@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_I915_READ
	mov	x19, x0
Lloh4:
	adrp	x8, _DP_PLL_FREQ_MASK@GOTPAGE
Lloh5:
	ldr	x8, [x8, _DP_PLL_FREQ_MASK@GOTPAGEOFF]
Lloh6:
	ldr	w22, [x8]
	mov	w8, #3391
	movk	w8, #3, lsl #16
	cmp	w20, w8
	b.gt	LBB0_2
; %bb.1:
Lloh7:
	adrp	x0, l_.str.1@PAGE
Lloh8:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_DEBUG_KMS
Lloh9:
	adrp	x8, _DP_PLL_FREQ_160MHZ@GOTPAGE
Lloh10:
	ldr	x8, [x8, _DP_PLL_FREQ_160MHZ@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:
Lloh11:
	adrp	x8, _DP_PLL_FREQ_270MHZ@GOTPAGE
Lloh12:
	ldr	x8, [x8, _DP_PLL_FREQ_270MHZ@GOTPAGEOFF]
LBB0_3:
	bic	w9, w19, w22
	ldr	w8, [x8]
	orr	w1, w8, w9
	ldr	w0, [x21]
	bl	_I915_WRITE
	ldr	w0, [x21]
	bl	_POSTING_READ
	mov	w0, #500
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	b	_udelay
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpAdd	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh11, Lloh12
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"eDP PLL enable for clock %d\n"

	.comm	_DP_A,4,2                       ; @DP_A
	.comm	_DP_PLL_FREQ_MASK,4,2           ; @DP_PLL_FREQ_MASK
l_.str.1:                               ; @.str.1
	.asciz	"160MHz cpu eDP clock, might need ilk devA w/a\n"

	.comm	_DP_PLL_FREQ_160MHZ,4,2         ; @DP_PLL_FREQ_160MHZ
	.comm	_DP_PLL_FREQ_270MHZ,4,2         ; @DP_PLL_FREQ_270MHZ
	.no_dead_strip	_ironlake_set_pll_edp
.subsections_via_symbols
