	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function amd_pmu_hw_config
_amd_pmu_hw_config:                     ## @amd_pmu_hw_config
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	callq	_x86_pmu_hw_config
	testl	%eax, %eax
	jne	LBB0_10
## %bb.1:
	cmpq	$0, 24(%rbx)
	movq	16(%rbx), %rcx
	je	LBB0_5
## %bb.2:
	testq	%rcx, %rcx
	je	LBB0_4
## %bb.3:
	movq	_ARCH_PERFMON_EVENTSEL_USR@GOTPCREL(%rip), %rcx
	movq	_ARCH_PERFMON_EVENTSEL_OS@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	notl	%edx
	andl	%edx, 32(%rbx)
	jmp	LBB0_8
LBB0_5:
	testq	%rcx, %rcx
	je	LBB0_8
## %bb.6:
	movq	_AMD_PERFMON_EVENTSEL_HOSTONLY@GOTPCREL(%rip), %rcx
	jmp	LBB0_7
LBB0_4:
	movq	_AMD_PERFMON_EVENTSEL_GUESTONLY@GOTPCREL(%rip), %rcx
LBB0_7:
	movl	(%rcx), %ecx
	orl	%ecx, 32(%rbx)
LBB0_8:
	movq	(%rbx), %rcx
	movq	_PERF_TYPE_RAW@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_10
## %bb.9:
	movq	_AMD64_RAW_EVENT_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	8(%rbx), %ecx
	orl	%ecx, 32(%rbx)
LBB0_10:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_ARCH_PERFMON_EVENTSEL_USR,4,2  ## @ARCH_PERFMON_EVENTSEL_USR
	.comm	_ARCH_PERFMON_EVENTSEL_OS,4,2   ## @ARCH_PERFMON_EVENTSEL_OS
	.comm	_AMD_PERFMON_EVENTSEL_GUESTONLY,4,2 ## @AMD_PERFMON_EVENTSEL_GUESTONLY
	.comm	_AMD_PERFMON_EVENTSEL_HOSTONLY,4,2 ## @AMD_PERFMON_EVENTSEL_HOSTONLY
	.comm	_PERF_TYPE_RAW,8,3              ## @PERF_TYPE_RAW
	.comm	_AMD64_RAW_EVENT_MASK,4,2       ## @AMD64_RAW_EVENT_MASK
	.no_dead_strip	_amd_pmu_hw_config
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function amd_pmu_hw_config
_amd_pmu_hw_config:                     ; @amd_pmu_hw_config
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_x86_pmu_hw_config
	cbnz	w0, LBB0_11
; %bb.1:
	ldp	x8, x9, [x19, #16]
	cbz	x9, LBB0_4
; %bb.2:
	cbz	x8, LBB0_6
; %bb.3:
Lloh0:
	adrp	x8, _ARCH_PERFMON_EVENTSEL_USR@GOTPAGE
Lloh1:
	ldr	x8, [x8, _ARCH_PERFMON_EVENTSEL_USR@GOTPAGEOFF]
Lloh2:
	adrp	x9, _ARCH_PERFMON_EVENTSEL_OS@GOTPAGE
Lloh3:
	ldr	x9, [x9, _ARCH_PERFMON_EVENTSEL_OS@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
Lloh5:
	ldr	w9, [x9]
	orr	w8, w9, w8
	ldr	w9, [x19, #32]
	bic	w8, w9, w8
	b	LBB0_8
LBB0_4:
	cbz	x8, LBB0_9
; %bb.5:
Lloh6:
	adrp	x8, _AMD_PERFMON_EVENTSEL_HOSTONLY@GOTPAGE
Lloh7:
	ldr	x8, [x8, _AMD_PERFMON_EVENTSEL_HOSTONLY@GOTPAGEOFF]
	b	LBB0_7
LBB0_6:
Lloh8:
	adrp	x8, _AMD_PERFMON_EVENTSEL_GUESTONLY@GOTPAGE
Lloh9:
	ldr	x8, [x8, _AMD_PERFMON_EVENTSEL_GUESTONLY@GOTPAGEOFF]
LBB0_7:
	ldr	w8, [x8]
	ldr	w9, [x19, #32]
	orr	w8, w9, w8
LBB0_8:
	str	w8, [x19, #32]
LBB0_9:
	ldr	x8, [x19]
Lloh10:
	adrp	x9, _PERF_TYPE_RAW@GOTPAGE
Lloh11:
	ldr	x9, [x9, _PERF_TYPE_RAW@GOTPAGEOFF]
Lloh12:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_11
; %bb.10:
Lloh13:
	adrp	x8, _AMD64_RAW_EVENT_MASK@GOTPAGE
Lloh14:
	ldr	x8, [x8, _AMD64_RAW_EVENT_MASK@GOTPAGEOFF]
	ldr	w9, [x19, #8]
Lloh15:
	ldr	w8, [x8]
	and	w8, w8, w9
	ldr	w9, [x19, #32]
	orr	w8, w9, w8
	str	w8, [x19, #32]
LBB0_11:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh4
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.cfi_endproc
                                        ; -- End function
	.comm	_ARCH_PERFMON_EVENTSEL_USR,4,2  ; @ARCH_PERFMON_EVENTSEL_USR
	.comm	_ARCH_PERFMON_EVENTSEL_OS,4,2   ; @ARCH_PERFMON_EVENTSEL_OS
	.comm	_AMD_PERFMON_EVENTSEL_GUESTONLY,4,2 ; @AMD_PERFMON_EVENTSEL_GUESTONLY
	.comm	_AMD_PERFMON_EVENTSEL_HOSTONLY,4,2 ; @AMD_PERFMON_EVENTSEL_HOSTONLY
	.comm	_PERF_TYPE_RAW,8,3              ; @PERF_TYPE_RAW
	.comm	_AMD64_RAW_EVENT_MASK,4,2       ; @AMD64_RAW_EVENT_MASK
	.no_dead_strip	_amd_pmu_hw_config
.subsections_via_symbols
