	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tg3_setup_copper_phy
_tg3_setup_copper_phy:                  ## @tg3_setup_copper_phy
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %r15
	callq	_tg3_clear_mac_status
	movl	(%r15), %esi
	movq	_MAC_MI_MODE_AUTO_POLL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%esi, %eax
	je	LBB0_2
## %bb.1:
	movq	_MAC_MI_MODE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	notl	%eax
	andl	%eax, %esi
	callq	_tw32_f
	movl	$80, %edi
	callq	_udelay
LBB0_2:
	movq	_MII_TG3_AUXCTL_SHDWSEL_PWRCTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_tg3_phy_auxctl_write
	movq	%r15, %rdi
	callq	_tg3_asic_rev
	movq	_ASIC_REV_5703@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_5
## %bb.3:
	movq	%r15, %rdi
	callq	_tg3_asic_rev
	movq	_ASIC_REV_5704@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_5
## %bb.4:
	movq	%r15, %rdi
	callq	_tg3_asic_rev
	movq	_ASIC_REV_5705@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_7
LBB0_5:
	cmpq	$0, 80(%r15)
	je	LBB0_7
## %bb.6:
	movq	_MII_BMSR@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	leaq	-44(%rbp), %r12
	movq	%r15, %rdi
	movq	%r12, %rdx
	callq	_tg3_readphy
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movq	%r12, %rdx
	callq	_tg3_readphy
	testq	%rax, %rax
	je	LBB0_10
LBB0_7:
	testl	%r14d, %r14d
	je	LBB0_12
LBB0_8:
	movq	%r15, %rdi
	callq	_tg3_phy_reset
	movb	$1, %al
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	jmp	LBB0_13
LBB0_10:
	testl	%r14d, %r14d
	jne	LBB0_8
## %bb.11:
	movq	_BMSR_LSTATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	-44(%rbp), %eax
	je	LBB0_8
LBB0_12:
	movl	$0, -56(%rbp)                   ## 4-byte Folded Spill
LBB0_13:
	movq	_TG3_PHY_ID_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	4(%r15), %eax
	movq	_TG3_PHY_ID_BCM5401@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_16
## %bb.14:
	movq	_MII_BMSR@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	leaq	-44(%rbp), %rbx
	movq	%r15, %rdi
	movq	%rbx, %rdx
	callq	_tg3_readphy
	movl	(%r14), %esi
	movq	%r15, %rdi
	movq	%rbx, %rdx
	callq	_tg3_readphy
	testq	%rax, %rax
	je	LBB0_19
LBB0_15:
	movl	$0, -44(%rbp)
	xorl	%eax, %eax
	jmp	LBB0_21
LBB0_16:
	movq	%r15, %rdi
	callq	_tg3_chip_rev_id
	movq	_CHIPREV_ID_5701_A0@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_18
## %bb.17:
	movq	%r15, %rdi
	callq	_tg3_chip_rev_id
	movq	_CHIPREV_ID_5701_B0@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_22
LBB0_18:
	movq	%r15, %rdi
	movl	$21, %esi
	movl	$2677, %edx                     ## imm = 0xA75
	callq	_tg3_writephy
	movq	_MII_TG3_MISC_SHDW@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	$35944, %edx                    ## imm = 0x8C68
	callq	_tg3_writephy
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	$36200, %edx                    ## imm = 0x8D68
	callq	_tg3_writephy
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	$35944, %edx                    ## imm = 0x8C68
	callq	_tg3_writephy
	jmp	LBB0_22
LBB0_19:
	movq	_INIT_COMPLETE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_tg3_flag
	testq	%rax, %rax
	je	LBB0_15
## %bb.20:
	movl	-44(%rbp), %eax
LBB0_21:
	movq	_BMSR_LSTATUS@GOTPCREL(%rip), %r12
	testl	%eax, (%r12)
	je	LBB0_67
LBB0_22:
	movq	_MII_TG3_ISTAT@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	leaq	-52(%rbp), %r14
	movq	%r15, %rdi
	movq	%r14, %rdx
	callq	_tg3_readphy
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movq	%r14, %rdx
	callq	_tg3_readphy
	movl	8(%r15), %eax
	movq	_TG3_PHYFLG_USE_MI_INTERRUPT@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_25
## %bb.23:
	movq	_MII_TG3_IMASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MII_TG3_INT_LINKCHG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	movq	%r15, %rdi
LBB0_24:
	callq	_tg3_writephy
	jmp	LBB0_26
LBB0_25:
	movq	_TG3_PHYFLG_IS_FET@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_78
LBB0_26:
	movq	%r15, %rdi
	callq	_tg3_asic_rev
	movq	_ASIC_REV_5700@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_28
## %bb.27:
	movq	%r15, %rdi
	callq	_tg3_asic_rev
	movq	_ASIC_REV_5701@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_31
LBB0_28:
	movq	16(%r15), %rax
	movq	_LED_CTRL_MODE_PHY_1@GOTPCREL(%rip), %rcx
	xorl	%edx, %edx
	movq	_MII_TG3_EXT_CTRL@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	cmpq	(%rcx), %rax
	jne	LBB0_30
## %bb.29:
	movq	_MII_TG3_EXT_CTRL_LNK3_LED_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
LBB0_30:
	movq	%r15, %rdi
	callq	_tg3_writephy
LBB0_31:
	movq	_SPEED_UNKNOWN@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -80(%rbp)
	movq	_DUPLEX_UNKNOWN@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -72(%rbp)
	movq	_TG3_PHYFLG_MDIX_STATE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	8(%r15), %eax
	movl	%eax, 8(%r15)
	movq	$0, 72(%r15)
	movq	_TG3_PHYFLG_CAPACITIVE_COUPLING@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_35
## %bb.32:
	movq	_MII_TG3_AUXCTL_SHDWSEL_MISCTEST@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	leaq	-52(%rbp), %rdx
	movq	%r15, %rdi
	callq	_tg3_phy_auxctl_read
	testl	%eax, %eax
	jne	LBB0_35
## %bb.33:
	movl	-52(%rbp), %edx
	testl	$1024, %edx                     ## imm = 0x400
	jne	LBB0_35
## %bb.34:
	movl	(%rbx), %esi
	orl	$1024, %edx                     ## imm = 0x400
	movq	%r15, %rdi
	callq	_tg3_phy_auxctl_write
	xorl	%r14d, %r14d
	jmp	LBB0_85
LBB0_35:
	movl	$0, -44(%rbp)
	movl	$100, %ebx
	movq	_MII_BMSR@GOTPCREL(%rip), %r12
	leaq	-44(%rbp), %r14
	movq	_BMSR_LSTATUS@GOTPCREL(%rip), %r13
	jmp	LBB0_37
	.p2align	4, 0x90
LBB0_36:                                ##   in Loop: Header=BB0_37 Depth=1
	movl	$40, %edi
	callq	_udelay
	decl	%ebx
	je	LBB0_39
LBB0_37:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r12), %esi
	movq	%r15, %rdi
	movq	%r14, %rdx
	callq	_tg3_readphy
	movl	(%r12), %esi
	movq	%r15, %rdi
	movq	%r14, %rdx
	callq	_tg3_readphy
	testq	%rax, %rax
	jne	LBB0_36
## %bb.38:                              ##   in Loop: Header=BB0_37 Depth=1
	movl	(%r13), %eax
	testl	%eax, -44(%rbp)
	je	LBB0_36
	jmp	LBB0_40
LBB0_39:
	movl	(%r13), %eax
	testl	%eax, -44(%rbp)
	je	LBB0_66
LBB0_40:
	movq	_MII_TG3_AUX_STAT@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	leaq	-84(%rbp), %r12
	movq	%r15, %rdi
	movq	%r12, %rdx
	callq	_tg3_readphy
	movl	$1999, %ebx                     ## imm = 0x7CF
	.p2align	4, 0x90
LBB0_41:                                ## =>This Inner Loop Header: Depth=1
	movl	$10, %edi
	callq	_udelay
	movl	(%r14), %esi
	movq	%r15, %rdi
	movq	%r12, %rdx
	callq	_tg3_readphy
	testq	%rax, %rax
	sete	%cl
	movl	-84(%rbp), %esi
	testl	%esi, %esi
	setne	%dl
	subl	$1, %ebx
	setb	%al
	testb	%dl, %cl
	jne	LBB0_43
## %bb.42:                              ##   in Loop: Header=BB0_41 Depth=1
	testb	%al, %al
	je	LBB0_41
LBB0_43:
	leaq	-80(%rbp), %rdx
	leaq	-72(%rbp), %rcx
	movq	%r15, %rdi
	callq	_tg3_aux_stat_to_speed_duplex
	movl	$0, -48(%rbp)
	movl	$200, %ebx
	movq	_MII_BMCR@GOTPCREL(%rip), %r12
	leaq	-48(%rbp), %r14
	jmp	LBB0_46
	.p2align	4, 0x90
LBB0_44:                                ##   in Loop: Header=BB0_46 Depth=1
	movl	$10, %edi
	callq	_udelay
LBB0_45:                                ##   in Loop: Header=BB0_46 Depth=1
	decl	%ebx
	je	LBB0_49
LBB0_46:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r12), %esi
	movq	%r15, %rdi
	movq	%r14, %rdx
	callq	_tg3_readphy
	movl	(%r12), %esi
	movq	%r15, %rdi
	movq	%r14, %rdx
	callq	_tg3_readphy
	testq	%rax, %rax
	jne	LBB0_45
## %bb.47:                              ##   in Loop: Header=BB0_46 Depth=1
	movl	-48(%rbp), %eax
	cmpl	$32767, %eax                    ## imm = 0x7FFF
	je	LBB0_44
## %bb.48:                              ##   in Loop: Header=BB0_46 Depth=1
	testl	%eax, %eax
	je	LBB0_44
LBB0_49:
	movl	$0, -64(%rbp)
	movl	$0, -60(%rbp)
	movq	-80(%rbp), %rcx
	movq	%rcx, 32(%r15)
	movq	-72(%rbp), %rax
	movq	%rax, 40(%r15)
	movq	48(%r15), %rdx
	movq	_AUTONEG_ENABLE@GOTPCREL(%rip), %rsi
	cmpq	(%rsi), %rdx
	jne	LBB0_62
## %bb.50:
	movq	%r15, %rdi
	callq	_tg3_phy_eee_config_ok
	movl	%eax, %r14d
	movq	_BMCR_ANENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	xorl	%ebx, %ebx
	testl	%eax, -48(%rbp)
	je	LBB0_54
## %bb.51:
	testl	%r14d, %r14d
	je	LBB0_54
## %bb.52:
	leaq	-64(%rbp), %rsi
	movq	%r15, %rdi
	callq	_tg3_phy_copper_an_config_ok
	testq	%rax, %rax
	je	LBB0_54
## %bb.53:
	leaq	-60(%rbp), %rsi
	movq	%r15, %rdi
	callq	_tg3_phy_copper_fetch_rmtadv
	xorl	%ebx, %ebx
	testq	%rax, %rax
	setne	%bl
LBB0_54:
	testl	%r14d, %r14d
	jne	LBB0_57
## %bb.55:
	movq	_TG3_PHYFLG_KEEP_LINK_ON_PWRDN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 8(%r15)
	sete	%al
	movl	-56(%rbp), %ecx                 ## 4-byte Reload
	orb	%al, %cl
	jne	LBB0_57
## %bb.56:
	movq	%r15, %rdi
	callq	_tg3_setup_eee
	movq	%r15, %rdi
	callq	_tg3_phy_reset
LBB0_57:
	testl	%ebx, %ebx
	je	LBB0_66
## %bb.58:
	movq	40(%r15), %rax
LBB0_59:
	movq	_DUPLEX_FULL@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_84
## %bb.60:
	movq	_TG3_PHYFLG_IS_FET@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_MII_TG3_EXT_STAT_MDIX@GOTPCREL(%rip), %rax
	movq	_MII_TG3_FET_GEN_STAT_MDIXSTAT@GOTPCREL(%rip), %rcx
	andl	8(%r15), %ebx
	jne	LBB0_79
## %bb.61:
	movq	_MII_TG3_EXT_STAT@GOTPCREL(%rip), %rdx
	jmp	LBB0_80
LBB0_62:
	movq	_BMCR_ANENABLE@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	testl	%edx, -48(%rbp)
	jne	LBB0_66
## %bb.63:
	cmpq	%rcx, 56(%r15)
	jne	LBB0_66
## %bb.64:
	cmpq	%rax, 64(%r15)
	je	LBB0_59
LBB0_66:
	xorl	%r14d, %r14d
LBB0_85:
	movq	%r15, %rdi
	callq	_tg3_phy_copper_begin
	movq	_ROBOSWITCH@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_tg3_flag
	testq	%rax, %rax
	je	LBB0_87
## %bb.86:
	movq	_SPEED_1000@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -80(%rbp)
	movq	_DUPLEX_FULL@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, -72(%rbp)
	movq	%rax, 32(%r15)
	movq	%rcx, 40(%r15)
	movl	$1, %r14d
LBB0_87:
	movq	_MII_BMSR@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	leaq	-44(%rbp), %r12
	movq	%r15, %rdi
	movq	%r12, %rdx
	callq	_tg3_readphy
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movq	%r12, %rdx
	callq	_tg3_readphy
	testq	%rax, %rax
	je	LBB0_91
LBB0_88:
	movq	_MAC_MODE_PORT_MODE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	leaq	24(%r15), %r13
	andl	24(%r15), %eax
	testl	%r14d, %r14d
	jne	LBB0_93
## %bb.89:
	movq	_TG3_PHYFLG_IS_FET@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, 8(%r15)
	jne	LBB0_96
## %bb.90:
	movq	_MAC_MODE_PORT_MODE_GMII@GOTPCREL(%rip), %rcx
	jmp	LBB0_97
LBB0_91:
	movq	_BMSR_LSTATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, -44(%rbp)
	jne	LBB0_92
	jmp	LBB0_88
LBB0_67:
	movq	%r15, %rdi
	callq	_tg3_init_5401phy_dsp
	testl	%eax, %eax
	jne	LBB0_131
## %bb.68:
	movl	(%r14), %esi
	leaq	-44(%rbp), %r13
	movq	%r15, %rdi
	movq	%r13, %rdx
	callq	_tg3_readphy
	movl	$1000, %ebx                     ## imm = 0x3E8
	jmp	LBB0_70
	.p2align	4, 0x90
LBB0_69:                                ##   in Loop: Header=BB0_70 Depth=1
	decl	%ebx
	je	LBB0_73
LBB0_70:                                ## =>This Inner Loop Header: Depth=1
	movl	$10, %edi
	callq	_udelay
	movl	(%r14), %esi
	movq	%r15, %rdi
	movq	%r13, %rdx
	callq	_tg3_readphy
	testq	%rax, %rax
	jne	LBB0_69
## %bb.71:                              ##   in Loop: Header=BB0_70 Depth=1
	movl	(%r12), %eax
	testl	%eax, -44(%rbp)
	je	LBB0_69
## %bb.72:
	movl	$40, %edi
	callq	_udelay
LBB0_73:
	movq	_TG3_PHY_ID_REV_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	4(%r15), %eax
	movq	_TG3_PHY_REV_BCM5401_B0@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_22
## %bb.74:
	movl	(%r12), %eax
	testl	%eax, -44(%rbp)
	jne	LBB0_22
## %bb.75:
	movq	32(%r15), %rax
	movq	_SPEED_1000@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_22
## %bb.76:
	movq	%r15, %rdi
	callq	_tg3_phy_reset
	testl	%eax, %eax
	jne	LBB0_131
## %bb.77:
	movq	%r15, %rdi
	callq	_tg3_init_5401phy_dsp
	testl	%eax, %eax
	jne	LBB0_131
	jmp	LBB0_22
LBB0_78:
	movq	_MII_TG3_IMASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$-1, %edx
	jmp	LBB0_24
LBB0_96:
	movq	_MAC_MODE_PORT_MODE_MII@GOTPCREL(%rip), %rcx
LBB0_97:
	xorl	%ebx, %ebx
	xorl	%r14d, %r14d
	jmp	LBB0_98
LBB0_79:
	movq	_MII_TG3_FET_GEN_STAT@GOTPCREL(%rip), %rdx
LBB0_80:
	movl	(%rax), %r14d
	movl	(%rcx), %r12d
	movl	(%rdx), %esi
	leaq	-52(%rbp), %rdx
	movq	%r15, %rdi
	callq	_tg3_readphy
	testq	%rax, %rax
	jne	LBB0_83
## %bb.81:
	testl	%ebx, %ebx
	cmovel	%r14d, %r12d
	testl	%r12d, -52(%rbp)
	je	LBB0_83
## %bb.82:
	movq	_TG3_PHYFLG_MDIX_STATE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, 8(%r15)
LBB0_83:
	movl	-64(%rbp), %esi
	movl	-60(%rbp), %edx
	movq	%r15, %rdi
	callq	_tg3_setup_flow_control
LBB0_84:
	movq	_TG3_PHYFLG_IS_LOW_POWER@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	$1, %r14d
	testl	%eax, 8(%r15)
	jne	LBB0_85
LBB0_92:
	movq	_MAC_MODE_PORT_MODE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	leaq	24(%r15), %r13
	andl	24(%r15), %eax
	movl	%eax, 24(%r15)
LBB0_93:
	movq	32(%r15), %rdx
	movq	_SPEED_100@GOTPCREL(%rip), %rsi
	movq	_SPEED_10@GOTPCREL(%rip), %rbx
	movq	_MAC_MODE_PORT_MODE_MII@GOTPCREL(%rip), %rdi
	movq	%rdi, %rcx
	cmpq	(%rbx), %rdx
	je	LBB0_95
## %bb.94:
	movq	_MAC_MODE_PORT_MODE_GMII@GOTPCREL(%rip), %rcx
LBB0_95:
	cmpq	(%rsi), %rdx
	cmoveq	%rdi, %rcx
	movl	$1, %r14d
	movb	$1, %bl
LBB0_98:
	orl	(%rcx), %eax
	movl	%eax, 24(%r15)
	movq	_RGMII_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_tg3_flag
	testq	%rax, %rax
	je	LBB0_107
## %bb.99:
	movq	_MAC_LED_CTRL@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_tr32
	movq	_LED_CTRL_1000MBPS_ON@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	_LED_CTRL_100MBPS_ON@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movl	%edx, %esi
	orl	%ecx, %esi
	notl	%esi
	andl	%eax, %esi
	movq	32(%r15), %rax
	movq	_SPEED_10@GOTPCREL(%rip), %rdi
	cmpq	(%rdi), %rax
	jne	LBB0_101
## %bb.100:
	movq	_LED_CTRL_LNKLED_OVERRIDE@GOTPCREL(%rip), %rax
	jmp	LBB0_105
LBB0_101:
	movq	_SPEED_100@GOTPCREL(%rip), %rdi
	cmpq	(%rdi), %rax
	jne	LBB0_103
## %bb.102:
	movq	_LED_CTRL_LNKLED_OVERRIDE@GOTPCREL(%rip), %rax
	orl	%edx, %esi
	jmp	LBB0_105
LBB0_103:
	movq	_SPEED_1000@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rax
	jne	LBB0_106
## %bb.104:
	movq	_LED_CTRL_LNKLED_OVERRIDE@GOTPCREL(%rip), %rax
	orl	%ecx, %esi
LBB0_105:
	orl	(%rax), %esi
LBB0_106:
	movl	(%r12), %edi
	callq	_tw32
	movl	$40, %edi
	callq	_udelay
LBB0_107:
	movq	_MAC_MODE_HALF_DUPLEX@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, %edx
	notl	%edx
	movl	24(%r15), %ecx
	andl	%ecx, %edx
	movl	%edx, 24(%r15)
	movq	40(%r15), %rdx
	movq	_DUPLEX_HALF@GOTPCREL(%rip), %rsi
	cmpq	(%rsi), %rdx
	jne	LBB0_109
## %bb.108:
	orl	%eax, %ecx
	movl	%ecx, (%r13)
LBB0_109:
	movq	%r15, %rdi
	callq	_tg3_asic_rev
	movq	_ASIC_REV_5700@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_115
## %bb.110:
	testb	%bl, %bl
	je	LBB0_113
## %bb.111:
	movq	32(%r15), %rsi
	movq	%r15, %rdi
	callq	_tg3_5700_link_polarity
	testq	%rax, %rax
	je	LBB0_113
## %bb.112:
	movq	_MAC_MODE_LINK_POLARITY@GOTPCREL(%rip), %rcx
	movl	(%r13), %eax
	orl	(%rcx), %eax
	jmp	LBB0_114
LBB0_113:
	movq	_MAC_MODE_LINK_POLARITY@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	(%r13), %eax
LBB0_114:
	movl	%eax, (%r13)
LBB0_115:
	movq	_TG3_PHY_ID_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	4(%r15), %eax
	movq	_TG3_PHY_ID_BCM5411@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_118
## %bb.116:
	movq	%r15, %rdi
	callq	_tg3_chip_rev_id
	movq	_CHIPREV_ID_5700_ALTIMA@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_118
## %bb.117:
	movl	(%r15), %esi
	movq	_MAC_MI_MODE_AUTO_POLL@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	%esi, (%r15)
	movq	_MAC_MI_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_tw32_f
	movl	$80, %edi
	callq	_udelay
LBB0_118:
	movq	_MAC_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	24(%r15), %esi
	callq	_tw32_f
	movl	$40, %edi
	callq	_udelay
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_tg3_phy_eee_adjust
	movq	_USE_LINKCHG_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_tg3_flag
	xorl	%esi, %esi
	movq	_MAC_EVENT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	testq	%rax, %rax
	jne	LBB0_120
## %bb.119:
	movq	_MAC_EVENT_LNKSTATE_CHANGED@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
LBB0_120:
	callq	_tw32_f
	movl	$40, %edi
	callq	_udelay
	movq	%r15, %rdi
	callq	_tg3_asic_rev
	movq	_ASIC_REV_5700@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	setne	%al
	xorb	$1, %bl
	orb	%al, %bl
	jne	LBB0_125
## %bb.121:
	movq	32(%r15), %rax
	movq	_SPEED_1000@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_125
## %bb.122:
	movq	_PCIX_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_tg3_flag
	testq	%rax, %rax
	jne	LBB0_124
## %bb.123:
	movq	_PCI_HIGH_SPEED@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_tg3_flag
	testq	%rax, %rax
	je	LBB0_125
LBB0_124:
	movl	$120, %edi
	callq	_udelay
	movq	_MAC_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_MAC_STATUS_SYNC_CHANGED@GOTPCREL(%rip), %rax
	movq	_MAC_STATUS_CFG_CHANGED@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	callq	_tw32_f
	movl	$40, %edi
	callq	_udelay
	movq	_NIC_SRAM_FIRMWARE_MBOX@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_NIC_SRAM_FIRMWARE_MBOX_MAGIC2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_tg3_write_mem
LBB0_125:
	movq	_CLKREQ_BUG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_tg3_flag
	testq	%rax, %rax
	je	LBB0_130
## %bb.126:
	movq	32(%r15), %rax
	movq	_SPEED_100@GOTPCREL(%rip), %rcx
	movl	28(%r15), %edi
	movq	_PCI_EXP_LNKCTL@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	movq	_PCI_EXP_LNKCTL_CLKREQ_EN@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	cmpq	(%rcx), %rax
	je	LBB0_129
## %bb.127:
	movq	_SPEED_10@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_129
## %bb.128:
	callq	_pcie_capability_set_word
	jmp	LBB0_130
LBB0_129:
	callq	_pcie_capability_clear_word
LBB0_130:
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_tg3_test_and_report_link_chg
	xorl	%eax, %eax
LBB0_131:
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MAC_MI_MODE_AUTO_POLL,4,2      ## @MAC_MI_MODE_AUTO_POLL
	.comm	_MAC_MI_MODE,4,2                ## @MAC_MI_MODE
	.comm	_MII_TG3_AUXCTL_SHDWSEL_PWRCTL,4,2 ## @MII_TG3_AUXCTL_SHDWSEL_PWRCTL
	.comm	_ASIC_REV_5703,8,3              ## @ASIC_REV_5703
	.comm	_ASIC_REV_5704,8,3              ## @ASIC_REV_5704
	.comm	_ASIC_REV_5705,8,3              ## @ASIC_REV_5705
	.comm	_MII_BMSR,4,2                   ## @MII_BMSR
	.comm	_BMSR_LSTATUS,4,2               ## @BMSR_LSTATUS
	.comm	_TG3_PHY_ID_MASK,4,2            ## @TG3_PHY_ID_MASK
	.comm	_TG3_PHY_ID_BCM5401,4,2         ## @TG3_PHY_ID_BCM5401
	.comm	_INIT_COMPLETE,4,2              ## @INIT_COMPLETE
	.comm	_TG3_PHY_ID_REV_MASK,4,2        ## @TG3_PHY_ID_REV_MASK
	.comm	_TG3_PHY_REV_BCM5401_B0,4,2     ## @TG3_PHY_REV_BCM5401_B0
	.comm	_SPEED_1000,8,3                 ## @SPEED_1000
	.comm	_CHIPREV_ID_5701_A0,8,3         ## @CHIPREV_ID_5701_A0
	.comm	_CHIPREV_ID_5701_B0,8,3         ## @CHIPREV_ID_5701_B0
	.comm	_MII_TG3_MISC_SHDW,4,2          ## @MII_TG3_MISC_SHDW
	.comm	_MII_TG3_ISTAT,4,2              ## @MII_TG3_ISTAT
	.comm	_TG3_PHYFLG_USE_MI_INTERRUPT,4,2 ## @TG3_PHYFLG_USE_MI_INTERRUPT
	.comm	_MII_TG3_IMASK,4,2              ## @MII_TG3_IMASK
	.comm	_MII_TG3_INT_LINKCHG,4,2        ## @MII_TG3_INT_LINKCHG
	.comm	_TG3_PHYFLG_IS_FET,4,2          ## @TG3_PHYFLG_IS_FET
	.comm	_ASIC_REV_5700,8,3              ## @ASIC_REV_5700
	.comm	_ASIC_REV_5701,8,3              ## @ASIC_REV_5701
	.comm	_LED_CTRL_MODE_PHY_1,8,3        ## @LED_CTRL_MODE_PHY_1
	.comm	_MII_TG3_EXT_CTRL,4,2           ## @MII_TG3_EXT_CTRL
	.comm	_MII_TG3_EXT_CTRL_LNK3_LED_MODE,4,2 ## @MII_TG3_EXT_CTRL_LNK3_LED_MODE
	.comm	_SPEED_UNKNOWN,8,3              ## @SPEED_UNKNOWN
	.comm	_DUPLEX_UNKNOWN,8,3             ## @DUPLEX_UNKNOWN
	.comm	_TG3_PHYFLG_MDIX_STATE,4,2      ## @TG3_PHYFLG_MDIX_STATE
	.comm	_TG3_PHYFLG_CAPACITIVE_COUPLING,4,2 ## @TG3_PHYFLG_CAPACITIVE_COUPLING
	.comm	_MII_TG3_AUXCTL_SHDWSEL_MISCTEST,4,2 ## @MII_TG3_AUXCTL_SHDWSEL_MISCTEST
	.comm	_MII_TG3_AUX_STAT,4,2           ## @MII_TG3_AUX_STAT
	.comm	_MII_BMCR,4,2                   ## @MII_BMCR
	.comm	_AUTONEG_ENABLE,8,3             ## @AUTONEG_ENABLE
	.comm	_BMCR_ANENABLE,4,2              ## @BMCR_ANENABLE
	.comm	_TG3_PHYFLG_KEEP_LINK_ON_PWRDN,4,2 ## @TG3_PHYFLG_KEEP_LINK_ON_PWRDN
	.comm	_DUPLEX_FULL,8,3                ## @DUPLEX_FULL
	.comm	_MII_TG3_FET_GEN_STAT,4,2       ## @MII_TG3_FET_GEN_STAT
	.comm	_MII_TG3_FET_GEN_STAT_MDIXSTAT,4,2 ## @MII_TG3_FET_GEN_STAT_MDIXSTAT
	.comm	_MII_TG3_EXT_STAT,4,2           ## @MII_TG3_EXT_STAT
	.comm	_MII_TG3_EXT_STAT_MDIX,4,2      ## @MII_TG3_EXT_STAT_MDIX
	.comm	_TG3_PHYFLG_IS_LOW_POWER,4,2    ## @TG3_PHYFLG_IS_LOW_POWER
	.comm	_ROBOSWITCH,4,2                 ## @ROBOSWITCH
	.comm	_MAC_MODE_PORT_MODE_MASK,4,2    ## @MAC_MODE_PORT_MODE_MASK
	.comm	_SPEED_100,8,3                  ## @SPEED_100
	.comm	_SPEED_10,8,3                   ## @SPEED_10
	.comm	_MAC_MODE_PORT_MODE_MII,4,2     ## @MAC_MODE_PORT_MODE_MII
	.comm	_MAC_MODE_PORT_MODE_GMII,4,2    ## @MAC_MODE_PORT_MODE_GMII
	.comm	_RGMII_MODE,4,2                 ## @RGMII_MODE
	.comm	_MAC_LED_CTRL,4,2               ## @MAC_LED_CTRL
	.comm	_LED_CTRL_1000MBPS_ON,4,2       ## @LED_CTRL_1000MBPS_ON
	.comm	_LED_CTRL_100MBPS_ON,4,2        ## @LED_CTRL_100MBPS_ON
	.comm	_LED_CTRL_LNKLED_OVERRIDE,4,2   ## @LED_CTRL_LNKLED_OVERRIDE
	.comm	_MAC_MODE_HALF_DUPLEX,4,2       ## @MAC_MODE_HALF_DUPLEX
	.comm	_DUPLEX_HALF,8,3                ## @DUPLEX_HALF
	.comm	_MAC_MODE_LINK_POLARITY,4,2     ## @MAC_MODE_LINK_POLARITY
	.comm	_TG3_PHY_ID_BCM5411,4,2         ## @TG3_PHY_ID_BCM5411
	.comm	_CHIPREV_ID_5700_ALTIMA,8,3     ## @CHIPREV_ID_5700_ALTIMA
	.comm	_MAC_MODE,4,2                   ## @MAC_MODE
	.comm	_USE_LINKCHG_REG,4,2            ## @USE_LINKCHG_REG
	.comm	_MAC_EVENT,4,2                  ## @MAC_EVENT
	.comm	_MAC_EVENT_LNKSTATE_CHANGED,4,2 ## @MAC_EVENT_LNKSTATE_CHANGED
	.comm	_PCIX_MODE,4,2                  ## @PCIX_MODE
	.comm	_PCI_HIGH_SPEED,4,2             ## @PCI_HIGH_SPEED
	.comm	_MAC_STATUS,4,2                 ## @MAC_STATUS
	.comm	_MAC_STATUS_SYNC_CHANGED,4,2    ## @MAC_STATUS_SYNC_CHANGED
	.comm	_MAC_STATUS_CFG_CHANGED,4,2     ## @MAC_STATUS_CFG_CHANGED
	.comm	_NIC_SRAM_FIRMWARE_MBOX,4,2     ## @NIC_SRAM_FIRMWARE_MBOX
	.comm	_NIC_SRAM_FIRMWARE_MBOX_MAGIC2,4,2 ## @NIC_SRAM_FIRMWARE_MBOX_MAGIC2
	.comm	_CLKREQ_BUG,4,2                 ## @CLKREQ_BUG
	.comm	_PCI_EXP_LNKCTL,4,2             ## @PCI_EXP_LNKCTL
	.comm	_PCI_EXP_LNKCTL_CLKREQ_EN,4,2   ## @PCI_EXP_LNKCTL_CLKREQ_EN
	.no_dead_strip	_tg3_setup_copper_phy
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tg3_setup_copper_phy
_tg3_setup_copper_phy:                  ; @tg3_setup_copper_phy
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #144
	.cfi_def_cfa_offset 144
	stp	x28, x27, [sp, #48]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #64]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #80]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #96]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #112]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #128]            ; 16-byte Folded Spill
	add	x29, sp, #128
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x20, x1
	mov	x19, x0
	bl	_tg3_clear_mac_status
	ldr	w8, [x19]
Lloh0:
	adrp	x9, _MAC_MI_MODE_AUTO_POLL@GOTPAGE
Lloh1:
	ldr	x9, [x9, _MAC_MI_MODE_AUTO_POLL@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
Lloh3:
	adrp	x10, _MAC_MI_MODE@GOTPAGE
Lloh4:
	ldr	x10, [x10, _MAC_MI_MODE@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x10]
	bic	w1, w8, w9
	bl	_tw32_f
	mov	w0, #80
	bl	_udelay
LBB0_2:
Lloh6:
	adrp	x8, _MII_TG3_AUXCTL_SHDWSEL_PWRCTL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _MII_TG3_AUXCTL_SHDWSEL_PWRCTL@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_tg3_phy_auxctl_write
	mov	x0, x19
	bl	_tg3_asic_rev
Lloh9:
	adrp	x8, _ASIC_REV_5703@GOTPAGE
Lloh10:
	ldr	x8, [x8, _ASIC_REV_5703@GOTPAGEOFF]
Lloh11:
	ldr	x8, [x8]
Lloh12:
	adrp	x24, _MII_BMSR@GOTPAGE
Lloh13:
	ldr	x24, [x24, _MII_BMSR@GOTPAGEOFF]
Lloh14:
	adrp	x23, _BMSR_LSTATUS@GOTPAGE
Lloh15:
	ldr	x23, [x23, _BMSR_LSTATUS@GOTPAGEOFF]
	cmp	x0, x8
	b.eq	LBB0_5
; %bb.3:
	mov	x0, x19
	bl	_tg3_asic_rev
Lloh16:
	adrp	x8, _ASIC_REV_5704@GOTPAGE
Lloh17:
	ldr	x8, [x8, _ASIC_REV_5704@GOTPAGEOFF]
Lloh18:
	ldr	x8, [x8]
	cmp	x0, x8
	b.eq	LBB0_5
; %bb.4:
	mov	x0, x19
	bl	_tg3_asic_rev
Lloh19:
	adrp	x8, _ASIC_REV_5705@GOTPAGE
Lloh20:
	ldr	x8, [x8, _ASIC_REV_5705@GOTPAGEOFF]
Lloh21:
	ldr	x8, [x8]
	cmp	x0, x8
	b.ne	LBB0_7
LBB0_5:
	ldr	x8, [x19, #80]
	cbz	x8, LBB0_7
; %bb.6:
	ldr	w1, [x24]
	add	x2, sp, #44
	mov	x0, x19
	bl	_tg3_readphy
	ldr	w1, [x24]
	add	x2, sp, #44
	mov	x0, x19
	bl	_tg3_readphy
	cbz	x0, LBB0_9
LBB0_7:
	cbz	w20, LBB0_11
LBB0_8:
	mov	x0, x19
	bl	_tg3_phy_reset
	mov	w28, #1
	b	LBB0_12
LBB0_9:
	cbnz	w20, LBB0_8
; %bb.10:
	ldr	w8, [sp, #44]
	ldr	w9, [x23]
	and	w8, w9, w8
	cbz	w8, LBB0_8
LBB0_11:
	mov	w28, #0
LBB0_12:
	ldr	w8, [x19, #4]
Lloh22:
	adrp	x22, _TG3_PHY_ID_MASK@GOTPAGE
Lloh23:
	ldr	x22, [x22, _TG3_PHY_ID_MASK@GOTPAGEOFF]
	ldr	w9, [x22]
	and	w8, w9, w8
Lloh24:
	adrp	x9, _TG3_PHY_ID_BCM5401@GOTPAGE
Lloh25:
	ldr	x9, [x9, _TG3_PHY_ID_BCM5401@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_15
; %bb.13:
	ldr	w1, [x24]
	add	x2, sp, #44
	mov	x0, x19
	bl	_tg3_readphy
	ldr	w1, [x24]
	add	x2, sp, #44
	mov	x0, x19
	bl	_tg3_readphy
	cbz	x0, LBB0_18
LBB0_14:
	mov	w8, #0
	str	wzr, [sp, #44]
	b	LBB0_20
LBB0_15:
	mov	x0, x19
	bl	_tg3_chip_rev_id
Lloh27:
	adrp	x8, _CHIPREV_ID_5701_A0@GOTPAGE
Lloh28:
	ldr	x8, [x8, _CHIPREV_ID_5701_A0@GOTPAGEOFF]
Lloh29:
	ldr	x8, [x8]
	cmp	x0, x8
	b.eq	LBB0_17
; %bb.16:
	mov	x0, x19
	bl	_tg3_chip_rev_id
Lloh30:
	adrp	x8, _CHIPREV_ID_5701_B0@GOTPAGE
Lloh31:
	ldr	x8, [x8, _CHIPREV_ID_5701_B0@GOTPAGEOFF]
Lloh32:
	ldr	x8, [x8]
	cmp	x0, x8
	b.ne	LBB0_21
LBB0_17:
	mov	x0, x19
	mov	w1, #21
	mov	w2, #2677
	bl	_tg3_writephy
Lloh33:
	adrp	x20, _MII_TG3_MISC_SHDW@GOTPAGE
Lloh34:
	ldr	x20, [x20, _MII_TG3_MISC_SHDW@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	mov	w2, #35944
	bl	_tg3_writephy
	ldr	w1, [x20]
	mov	x0, x19
	mov	w2, #36200
	bl	_tg3_writephy
	ldr	w1, [x20]
	mov	x0, x19
	mov	w2, #35944
	bl	_tg3_writephy
	b	LBB0_21
LBB0_18:
Lloh35:
	adrp	x8, _INIT_COMPLETE@GOTPAGE
Lloh36:
	ldr	x8, [x8, _INIT_COMPLETE@GOTPAGEOFF]
Lloh37:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_tg3_flag
	cbz	x0, LBB0_14
; %bb.19:
	ldr	w8, [sp, #44]
LBB0_20:
	ldr	w9, [x23]
	tst	w9, w8
	b.eq	LBB0_78
LBB0_21:
Lloh38:
	adrp	x20, _MII_TG3_ISTAT@GOTPAGE
Lloh39:
	ldr	x20, [x20, _MII_TG3_ISTAT@GOTPAGEOFF]
	ldr	w1, [x20]
	add	x2, sp, #40
	mov	x0, x19
	bl	_tg3_readphy
	ldr	w1, [x20]
	add	x2, sp, #40
	mov	x0, x19
	bl	_tg3_readphy
	ldr	w8, [x19, #8]
Lloh40:
	adrp	x9, _TG3_PHYFLG_USE_MI_INTERRUPT@GOTPAGE
Lloh41:
	ldr	x9, [x9, _TG3_PHYFLG_USE_MI_INTERRUPT@GOTPAGEOFF]
Lloh42:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_24
; %bb.22:
Lloh43:
	adrp	x8, _MII_TG3_IMASK@GOTPAGE
Lloh44:
	ldr	x8, [x8, _MII_TG3_IMASK@GOTPAGEOFF]
Lloh45:
	ldr	w1, [x8]
Lloh46:
	adrp	x8, _MII_TG3_INT_LINKCHG@GOTPAGE
Lloh47:
	ldr	x8, [x8, _MII_TG3_INT_LINKCHG@GOTPAGEOFF]
Lloh48:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	x0, x19
LBB0_23:
	bl	_tg3_writephy
	b	LBB0_25
LBB0_24:
Lloh49:
	adrp	x9, _TG3_PHYFLG_IS_FET@GOTPAGE
Lloh50:
	ldr	x9, [x9, _TG3_PHYFLG_IS_FET@GOTPAGEOFF]
Lloh51:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_115
LBB0_25:
	mov	x0, x19
	bl	_tg3_asic_rev
Lloh52:
	adrp	x27, _ASIC_REV_5700@GOTPAGE
Lloh53:
	ldr	x27, [x27, _ASIC_REV_5700@GOTPAGEOFF]
	ldr	x8, [x27]
	cmp	x0, x8
	b.eq	LBB0_27
; %bb.26:
	mov	x0, x19
	bl	_tg3_asic_rev
Lloh54:
	adrp	x8, _ASIC_REV_5701@GOTPAGE
Lloh55:
	ldr	x8, [x8, _ASIC_REV_5701@GOTPAGEOFF]
Lloh56:
	ldr	x8, [x8]
	cmp	x0, x8
	b.ne	LBB0_28
LBB0_27:
	ldr	x8, [x19, #16]
Lloh57:
	adrp	x9, _LED_CTRL_MODE_PHY_1@GOTPAGE
Lloh58:
	ldr	x9, [x9, _LED_CTRL_MODE_PHY_1@GOTPAGEOFF]
Lloh59:
	ldr	x9, [x9]
Lloh60:
	adrp	x10, _MII_TG3_EXT_CTRL@GOTPAGE
Lloh61:
	ldr	x10, [x10, _MII_TG3_EXT_CTRL@GOTPAGEOFF]
Lloh62:
	ldr	w1, [x10]
Lloh63:
	adrp	x10, _MII_TG3_EXT_CTRL_LNK3_LED_MODE@GOTPAGE
Lloh64:
	ldr	x10, [x10, _MII_TG3_EXT_CTRL_LNK3_LED_MODE@GOTPAGEOFF]
Lloh65:
	ldr	w10, [x10]
	cmp	x8, x9
	csel	w2, w10, wzr, eq
	mov	x0, x19
	bl	_tg3_writephy
LBB0_28:
Lloh66:
	adrp	x8, _SPEED_UNKNOWN@GOTPAGE
Lloh67:
	ldr	x8, [x8, _SPEED_UNKNOWN@GOTPAGEOFF]
Lloh68:
	ldr	x10, [x8]
Lloh69:
	adrp	x9, _DUPLEX_UNKNOWN@GOTPAGE
Lloh70:
	ldr	x9, [x9, _DUPLEX_UNKNOWN@GOTPAGEOFF]
Lloh71:
	ldr	x8, [x9]
	stp	x8, x10, [sp, #16]
Lloh72:
	adrp	x21, _TG3_PHYFLG_MDIX_STATE@GOTPAGE
Lloh73:
	ldr	x21, [x21, _TG3_PHYFLG_MDIX_STATE@GOTPAGEOFF]
	ldr	w8, [x21]
	ldr	w9, [x19, #8]
	bic	w8, w9, w8
	str	w8, [x19, #8]
	str	xzr, [x19, #72]
Lloh74:
	adrp	x9, _TG3_PHYFLG_CAPACITIVE_COUPLING@GOTPAGE
Lloh75:
	ldr	x9, [x9, _TG3_PHYFLG_CAPACITIVE_COUPLING@GOTPAGEOFF]
Lloh76:
	ldr	w9, [x9]
Lloh77:
	adrp	x25, _SPEED_10@GOTPAGE
Lloh78:
	ldr	x25, [x25, _SPEED_10@GOTPAGEOFF]
Lloh79:
	adrp	x26, _SPEED_100@GOTPAGE
Lloh80:
	ldr	x26, [x26, _SPEED_100@GOTPAGEOFF]
	tst	w9, w8
	b.eq	LBB0_32
; %bb.29:
Lloh81:
	adrp	x20, _MII_TG3_AUXCTL_SHDWSEL_MISCTEST@GOTPAGE
Lloh82:
	ldr	x20, [x20, _MII_TG3_AUXCTL_SHDWSEL_MISCTEST@GOTPAGEOFF]
	ldr	w1, [x20]
	add	x2, sp, #40
	mov	x0, x19
	bl	_tg3_phy_auxctl_read
	cbnz	w0, LBB0_32
; %bb.30:
	ldr	w8, [sp, #40]
	tbnz	w8, #10, LBB0_32
; %bb.31:
	ldr	w1, [x20]
	orr	w2, w8, #0x400
	mov	x0, x19
	bl	_tg3_phy_auxctl_write
	mov	w20, #0
	b	LBB0_65
LBB0_32:
	str	wzr, [sp, #44]
	mov	w20, #100
	b	LBB0_34
LBB0_33:                                ;   in Loop: Header=BB0_34 Depth=1
	mov	w0, #40
	bl	_udelay
	subs	w20, w20, #1
	b.eq	LBB0_36
LBB0_34:                                ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x24]
	add	x2, sp, #44
	mov	x0, x19
	bl	_tg3_readphy
	ldr	w1, [x24]
	add	x2, sp, #44
	mov	x0, x19
	bl	_tg3_readphy
	cbnz	x0, LBB0_33
; %bb.35:                               ;   in Loop: Header=BB0_34 Depth=1
	ldr	w8, [sp, #44]
	ldr	w9, [x23]
	tst	w9, w8
	b.eq	LBB0_33
	b	LBB0_37
LBB0_36:
	ldr	w8, [sp, #44]
	ldr	w9, [x23]
	tst	w9, w8
	b.eq	LBB0_51
LBB0_37:
	mov	x25, x22
Lloh83:
	adrp	x20, _MII_TG3_AUX_STAT@GOTPAGE
Lloh84:
	ldr	x20, [x20, _MII_TG3_AUX_STAT@GOTPAGEOFF]
	ldr	w1, [x20]
	add	x2, sp, #12
	mov	x0, x19
	bl	_tg3_readphy
	mov	w22, #1999
LBB0_38:                                ; =>This Inner Loop Header: Depth=1
	mov	w0, #10
	bl	_udelay
	ldr	w1, [x20]
	add	x2, sp, #12
	mov	x0, x19
	bl	_tg3_readphy
	ldr	w1, [sp, #12]
	cmp	w1, #0
	ccmp	x0, #0, #0, ne
	ccmp	w22, #0, #4, ne
	sub	w22, w22, #1
	b.ne	LBB0_38
; %bb.39:
	add	x2, sp, #24
	add	x3, sp, #16
	mov	x0, x19
	bl	_tg3_aux_stat_to_speed_duplex
	str	wzr, [sp, #8]
	mov	w20, #200
Lloh85:
	adrp	x26, _MII_BMCR@GOTPAGE
Lloh86:
	ldr	x26, [x26, _MII_BMCR@GOTPAGEOFF]
	mov	w22, #32767
	b	LBB0_42
LBB0_40:                                ;   in Loop: Header=BB0_42 Depth=1
	mov	w0, #10
	bl	_udelay
LBB0_41:                                ;   in Loop: Header=BB0_42 Depth=1
	subs	w20, w20, #1
	b.eq	LBB0_44
LBB0_42:                                ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x26]
	add	x2, sp, #8
	mov	x0, x19
	bl	_tg3_readphy
	ldr	w1, [x26]
	add	x2, sp, #8
	mov	x0, x19
	bl	_tg3_readphy
	cbnz	x0, LBB0_41
; %bb.43:                               ;   in Loop: Header=BB0_42 Depth=1
	ldr	w8, [sp, #8]
	cmp	w8, w22
	ccmp	w8, #0, #4, ne
	b.eq	LBB0_40
LBB0_44:
	str	xzr, [sp, #32]
	ldp	x8, x9, [sp, #16]
	stp	x9, x8, [x19, #32]
	ldr	x10, [x19, #48]
Lloh87:
	adrp	x11, _AUTONEG_ENABLE@GOTPAGE
Lloh88:
	ldr	x11, [x11, _AUTONEG_ENABLE@GOTPAGEOFF]
Lloh89:
	ldr	x11, [x11]
Lloh90:
	adrp	x22, _BMCR_ANENABLE@GOTPAGE
Lloh91:
	ldr	x22, [x22, _BMCR_ANENABLE@GOTPAGEOFF]
	cmp	x10, x11
	b.ne	LBB0_48
; %bb.45:
	mov	x0, x19
	bl	_tg3_phy_eee_config_ok
	mov	x20, x0
	ldr	w8, [sp, #8]
	ldr	w9, [x22]
	and	w8, w9, w8
	cmp	w8, #0
	ccmp	w0, #0, #4, ne
	b.eq	LBB0_52
; %bb.46:
	add	x1, sp, #36
	mov	x0, x19
	bl	_tg3_phy_copper_an_config_ok
	cbz	x0, LBB0_52
; %bb.47:
	add	x1, sp, #32
	mov	x0, x19
	bl	_tg3_phy_copper_fetch_rmtadv
	cmp	x0, #0
	cset	w22, ne
	cbnz	w20, LBB0_55
	b	LBB0_53
LBB0_48:
	ldr	w10, [sp, #8]
	ldr	w11, [x22]
	tst	w11, w10
	b.ne	LBB0_64
; %bb.49:
	ldr	x10, [x19, #56]
	cmp	x10, x9
	b.ne	LBB0_64
; %bb.50:
	ldr	x9, [x19, #64]
	cmp	x9, x8
	b.ne	LBB0_64
	b	LBB0_57
LBB0_51:
	mov	w20, #0
	b	LBB0_65
LBB0_52:
	mov	w22, #0
	cbnz	w20, LBB0_55
LBB0_53:
	ldr	w8, [x19, #8]
Lloh92:
	adrp	x9, _TG3_PHYFLG_KEEP_LINK_ON_PWRDN@GOTPAGE
Lloh93:
	ldr	x9, [x9, _TG3_PHYFLG_KEEP_LINK_ON_PWRDN@GOTPAGEOFF]
Lloh94:
	ldr	w9, [x9]
	tst	w9, w8
	cset	w8, eq
	orr	w8, w28, w8
	tbnz	w8, #0, LBB0_55
; %bb.54:
	mov	x0, x19
	bl	_tg3_setup_eee
	mov	x0, x19
	bl	_tg3_phy_reset
LBB0_55:
	cbz	w22, LBB0_64
; %bb.56:
	ldr	x8, [x19, #40]
LBB0_57:
Lloh95:
	adrp	x9, _DUPLEX_FULL@GOTPAGE
Lloh96:
	ldr	x9, [x9, _DUPLEX_FULL@GOTPAGEOFF]
Lloh97:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_62
; %bb.58:
	ldr	w8, [x19, #8]
Lloh98:
	adrp	x9, _TG3_PHYFLG_IS_FET@GOTPAGE
Lloh99:
	ldr	x9, [x9, _TG3_PHYFLG_IS_FET@GOTPAGEOFF]
Lloh100:
	ldr	w9, [x9]
	ands	w20, w9, w8
Lloh101:
	adrp	x8, _MII_TG3_EXT_STAT_MDIX@GOTPAGE
Lloh102:
	ldr	x8, [x8, _MII_TG3_EXT_STAT_MDIX@GOTPAGEOFF]
Lloh103:
	ldr	w22, [x8]
Lloh104:
	adrp	x8, _MII_TG3_FET_GEN_STAT_MDIXSTAT@GOTPAGE
Lloh105:
	ldr	x8, [x8, _MII_TG3_FET_GEN_STAT_MDIXSTAT@GOTPAGEOFF]
Lloh106:
	ldr	w26, [x8]
Lloh107:
	adrp	x8, _MII_TG3_EXT_STAT@GOTPAGE
Lloh108:
	ldr	x8, [x8, _MII_TG3_EXT_STAT@GOTPAGEOFF]
Lloh109:
	adrp	x9, _MII_TG3_FET_GEN_STAT@GOTPAGE
Lloh110:
	ldr	x9, [x9, _MII_TG3_FET_GEN_STAT@GOTPAGEOFF]
	csel	x8, x8, x9, eq
	ldr	w1, [x8]
	add	x2, sp, #40
	mov	x0, x19
	bl	_tg3_readphy
	cbnz	x0, LBB0_61
; %bb.59:
	cmp	w20, #0
	csel	w8, w22, w26, eq
	ldr	w9, [sp, #40]
	tst	w9, w8
	b.eq	LBB0_61
; %bb.60:
	ldr	w8, [x21]
	ldr	w9, [x19, #8]
	orr	w8, w9, w8
	str	w8, [x19, #8]
LBB0_61:
	ldp	w2, w1, [sp, #32]
	mov	x0, x19
	bl	_tg3_setup_flow_control
LBB0_62:
	ldr	w8, [x19, #8]
Lloh111:
	adrp	x9, _TG3_PHYFLG_IS_LOW_POWER@GOTPAGE
Lloh112:
	ldr	x9, [x9, _TG3_PHYFLG_IS_LOW_POWER@GOTPAGEOFF]
Lloh113:
	ldr	w9, [x9]
	tst	w9, w8
	mov	x22, x25
Lloh114:
	adrp	x25, _SPEED_10@GOTPAGE
Lloh115:
	ldr	x25, [x25, _SPEED_10@GOTPAGEOFF]
Lloh116:
	adrp	x26, _SPEED_100@GOTPAGE
Lloh117:
	ldr	x26, [x26, _SPEED_100@GOTPAGEOFF]
	b.eq	LBB0_71
; %bb.63:
	mov	w20, #1
	b	LBB0_65
LBB0_64:
	mov	w20, #0
	mov	x22, x25
Lloh118:
	adrp	x25, _SPEED_10@GOTPAGE
Lloh119:
	ldr	x25, [x25, _SPEED_10@GOTPAGEOFF]
Lloh120:
	adrp	x26, _SPEED_100@GOTPAGE
Lloh121:
	ldr	x26, [x26, _SPEED_100@GOTPAGEOFF]
LBB0_65:
	mov	x0, x19
	bl	_tg3_phy_copper_begin
Lloh122:
	adrp	x8, _ROBOSWITCH@GOTPAGE
Lloh123:
	ldr	x8, [x8, _ROBOSWITCH@GOTPAGEOFF]
Lloh124:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_tg3_flag
	cbz	x0, LBB0_67
; %bb.66:
Lloh125:
	adrp	x8, _SPEED_1000@GOTPAGE
Lloh126:
	ldr	x8, [x8, _SPEED_1000@GOTPAGEOFF]
Lloh127:
	ldr	x8, [x8]
Lloh128:
	adrp	x9, _DUPLEX_FULL@GOTPAGE
Lloh129:
	ldr	x9, [x9, _DUPLEX_FULL@GOTPAGEOFF]
Lloh130:
	ldr	x9, [x9]
	stp	x9, x8, [sp, #16]
	stp	x8, x9, [x19, #32]
	mov	w20, #1
LBB0_67:
	ldr	w1, [x24]
	add	x2, sp, #44
	mov	x0, x19
	bl	_tg3_readphy
	ldr	w1, [x24]
	add	x2, sp, #44
	mov	x0, x19
	bl	_tg3_readphy
	cbz	x0, LBB0_70
LBB0_68:
Lloh131:
	adrp	x8, _MAC_MODE_PORT_MODE_MASK@GOTPAGE
Lloh132:
	ldr	x8, [x8, _MAC_MODE_PORT_MODE_MASK@GOTPAGEOFF]
Lloh133:
	ldr	w8, [x8]
	mov	x21, x19
	ldr	w9, [x21, #24]!
	bic	w8, w9, w8
	cbnz	w20, LBB0_72
; %bb.69:
	ldr	w9, [x19, #8]
Lloh134:
	adrp	x10, _TG3_PHYFLG_IS_FET@GOTPAGE
Lloh135:
	ldr	x10, [x10, _TG3_PHYFLG_IS_FET@GOTPAGEOFF]
Lloh136:
	ldr	w10, [x10]
Lloh137:
	adrp	x11, _MAC_MODE_PORT_MODE_MII@GOTPAGE
Lloh138:
	ldr	x11, [x11, _MAC_MODE_PORT_MODE_MII@GOTPAGEOFF]
Lloh139:
	adrp	x12, _MAC_MODE_PORT_MODE_GMII@GOTPAGE
Lloh140:
	ldr	x12, [x12, _MAC_MODE_PORT_MODE_GMII@GOTPAGEOFF]
	tst	w10, w9
	csel	x9, x12, x11, eq
	b	LBB0_73
LBB0_70:
	ldr	w8, [sp, #44]
	ldr	w9, [x23]
	tst	w9, w8
	b.eq	LBB0_68
LBB0_71:
Lloh141:
	adrp	x8, _MAC_MODE_PORT_MODE_MASK@GOTPAGE
Lloh142:
	ldr	x8, [x8, _MAC_MODE_PORT_MODE_MASK@GOTPAGEOFF]
Lloh143:
	ldr	w8, [x8]
	mov	x21, x19
	ldr	w9, [x21, #24]!
	bic	w8, w9, w8
	str	w8, [x21]
LBB0_72:
	ldr	x9, [x19, #32]
	ldr	x10, [x26]
	ldr	x11, [x25]
	cmp	x9, x11
	ccmp	x9, x10, #4, ne
Lloh144:
	adrp	x9, _MAC_MODE_PORT_MODE_GMII@GOTPAGE
Lloh145:
	ldr	x9, [x9, _MAC_MODE_PORT_MODE_GMII@GOTPAGEOFF]
Lloh146:
	adrp	x10, _MAC_MODE_PORT_MODE_MII@GOTPAGE
Lloh147:
	ldr	x10, [x10, _MAC_MODE_PORT_MODE_MII@GOTPAGEOFF]
	csel	x9, x10, x9, eq
	mov	w20, #1
LBB0_73:
	ldr	w9, [x9]
	orr	w8, w9, w8
	str	w8, [x19, #24]
Lloh148:
	adrp	x8, _RGMII_MODE@GOTPAGE
Lloh149:
	ldr	x8, [x8, _RGMII_MODE@GOTPAGEOFF]
Lloh150:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_tg3_flag
	cbz	x0, LBB0_92
; %bb.74:
Lloh151:
	adrp	x23, _MAC_LED_CTRL@GOTPAGE
Lloh152:
	ldr	x23, [x23, _MAC_LED_CTRL@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_tr32
Lloh153:
	adrp	x8, _LED_CTRL_1000MBPS_ON@GOTPAGE
Lloh154:
	ldr	x8, [x8, _LED_CTRL_1000MBPS_ON@GOTPAGEOFF]
Lloh155:
	ldr	w8, [x8]
Lloh156:
	adrp	x9, _LED_CTRL_100MBPS_ON@GOTPAGE
Lloh157:
	ldr	x9, [x9, _LED_CTRL_100MBPS_ON@GOTPAGEOFF]
Lloh158:
	ldr	w9, [x9]
	orr	w10, w9, w8
	bic	w1, w0, w10
	ldr	x10, [x19, #32]
	ldr	x11, [x25]
	cmp	x10, x11
	b.ne	LBB0_76
; %bb.75:
Lloh159:
	adrp	x8, _LED_CTRL_LNKLED_OVERRIDE@GOTPAGE
Lloh160:
	ldr	x8, [x8, _LED_CTRL_LNKLED_OVERRIDE@GOTPAGEOFF]
Lloh161:
	ldr	w8, [x8]
	orr	w1, w8, w1
	b	LBB0_91
LBB0_76:
	ldr	x11, [x26]
	cmp	x10, x11
	b.ne	LBB0_89
; %bb.77:
Lloh162:
	adrp	x8, _LED_CTRL_LNKLED_OVERRIDE@GOTPAGE
Lloh163:
	ldr	x8, [x8, _LED_CTRL_LNKLED_OVERRIDE@GOTPAGEOFF]
Lloh164:
	ldr	w8, [x8]
	orr	w9, w1, w9
	orr	w1, w9, w8
	b	LBB0_91
LBB0_78:
	mov	x0, x19
	bl	_tg3_init_5401phy_dsp
	cbnz	w0, LBB0_114
; %bb.79:
	ldr	w1, [x24]
	add	x2, sp, #44
	mov	x0, x19
	bl	_tg3_readphy
	mov	w20, #1000
	b	LBB0_81
LBB0_80:                                ;   in Loop: Header=BB0_81 Depth=1
	subs	w20, w20, #1
	b.eq	LBB0_84
LBB0_81:                                ; =>This Inner Loop Header: Depth=1
	mov	w0, #10
	bl	_udelay
	ldr	w1, [x24]
	add	x2, sp, #44
	mov	x0, x19
	bl	_tg3_readphy
	cbnz	x0, LBB0_80
; %bb.82:                               ;   in Loop: Header=BB0_81 Depth=1
	ldr	w8, [sp, #44]
	ldr	w9, [x23]
	tst	w9, w8
	b.eq	LBB0_80
; %bb.83:
	mov	w0, #40
	bl	_udelay
LBB0_84:
	ldr	w8, [x19, #4]
Lloh165:
	adrp	x9, _TG3_PHY_ID_REV_MASK@GOTPAGE
Lloh166:
	ldr	x9, [x9, _TG3_PHY_ID_REV_MASK@GOTPAGEOFF]
Lloh167:
	ldr	w9, [x9]
	and	w8, w9, w8
Lloh168:
	adrp	x9, _TG3_PHY_REV_BCM5401_B0@GOTPAGE
Lloh169:
	ldr	x9, [x9, _TG3_PHY_REV_BCM5401_B0@GOTPAGEOFF]
Lloh170:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_21
; %bb.85:
	ldr	w8, [sp, #44]
	ldr	w9, [x23]
	tst	w9, w8
	b.ne	LBB0_21
; %bb.86:
	ldr	x8, [x19, #32]
Lloh171:
	adrp	x9, _SPEED_1000@GOTPAGE
Lloh172:
	ldr	x9, [x9, _SPEED_1000@GOTPAGEOFF]
Lloh173:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_21
; %bb.87:
	mov	x0, x19
	bl	_tg3_phy_reset
	cbnz	w0, LBB0_114
; %bb.88:
	mov	x0, x19
	bl	_tg3_init_5401phy_dsp
	cbnz	w0, LBB0_114
	b	LBB0_21
LBB0_89:
Lloh174:
	adrp	x9, _SPEED_1000@GOTPAGE
Lloh175:
	ldr	x9, [x9, _SPEED_1000@GOTPAGEOFF]
Lloh176:
	ldr	x9, [x9]
	cmp	x10, x9
	b.ne	LBB0_91
; %bb.90:
Lloh177:
	adrp	x9, _LED_CTRL_LNKLED_OVERRIDE@GOTPAGE
Lloh178:
	ldr	x9, [x9, _LED_CTRL_LNKLED_OVERRIDE@GOTPAGEOFF]
Lloh179:
	ldr	w9, [x9]
	orr	w8, w1, w8
	orr	w1, w8, w9
LBB0_91:
	ldr	w0, [x23]
	bl	_tw32
	mov	w0, #40
	bl	_udelay
LBB0_92:
Lloh180:
	adrp	x8, _MAC_MODE_HALF_DUPLEX@GOTPAGE
Lloh181:
	ldr	x8, [x8, _MAC_MODE_HALF_DUPLEX@GOTPAGEOFF]
Lloh182:
	ldr	w8, [x8]
	ldr	w9, [x19, #24]
	bic	w10, w9, w8
	str	w10, [x19, #24]
	ldr	x10, [x19, #40]
Lloh183:
	adrp	x11, _DUPLEX_HALF@GOTPAGE
Lloh184:
	ldr	x11, [x11, _DUPLEX_HALF@GOTPAGEOFF]
Lloh185:
	ldr	x11, [x11]
	cmp	x10, x11
	b.ne	LBB0_94
; %bb.93:
	orr	w8, w9, w8
	str	w8, [x21]
LBB0_94:
	mov	x0, x19
	bl	_tg3_asic_rev
	ldr	x8, [x27]
	cmp	x0, x8
	b.ne	LBB0_100
; %bb.95:
	cbz	w20, LBB0_98
; %bb.96:
	ldr	x1, [x19, #32]
	mov	x0, x19
	bl	_tg3_5700_link_polarity
	cbz	x0, LBB0_98
; %bb.97:
Lloh186:
	adrp	x8, _MAC_MODE_LINK_POLARITY@GOTPAGE
Lloh187:
	ldr	x8, [x8, _MAC_MODE_LINK_POLARITY@GOTPAGEOFF]
Lloh188:
	ldr	w8, [x8]
	ldr	w9, [x21]
	orr	w8, w9, w8
	b	LBB0_99
LBB0_98:
Lloh189:
	adrp	x8, _MAC_MODE_LINK_POLARITY@GOTPAGE
Lloh190:
	ldr	x8, [x8, _MAC_MODE_LINK_POLARITY@GOTPAGEOFF]
Lloh191:
	ldr	w8, [x8]
	ldr	w9, [x21]
	bic	w8, w9, w8
LBB0_99:
	str	w8, [x21]
LBB0_100:
	ldr	w8, [x19, #4]
	ldr	w9, [x22]
	and	w8, w9, w8
Lloh192:
	adrp	x9, _TG3_PHY_ID_BCM5411@GOTPAGE
Lloh193:
	ldr	x9, [x9, _TG3_PHY_ID_BCM5411@GOTPAGEOFF]
Lloh194:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_103
; %bb.101:
	mov	x0, x19
	bl	_tg3_chip_rev_id
Lloh195:
	adrp	x8, _CHIPREV_ID_5700_ALTIMA@GOTPAGE
Lloh196:
	ldr	x8, [x8, _CHIPREV_ID_5700_ALTIMA@GOTPAGEOFF]
Lloh197:
	ldr	x8, [x8]
	cmp	x0, x8
	b.ne	LBB0_103
; %bb.102:
Lloh198:
	adrp	x8, _MAC_MI_MODE_AUTO_POLL@GOTPAGE
Lloh199:
	ldr	x8, [x8, _MAC_MI_MODE_AUTO_POLL@GOTPAGEOFF]
Lloh200:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w1, w9, w8
	str	w1, [x19]
Lloh201:
	adrp	x8, _MAC_MI_MODE@GOTPAGE
Lloh202:
	ldr	x8, [x8, _MAC_MI_MODE@GOTPAGEOFF]
Lloh203:
	ldr	w0, [x8]
	bl	_tw32_f
	mov	w0, #80
	bl	_udelay
LBB0_103:
Lloh204:
	adrp	x8, _MAC_MODE@GOTPAGE
Lloh205:
	ldr	x8, [x8, _MAC_MODE@GOTPAGEOFF]
Lloh206:
	ldr	w0, [x8]
	ldr	w1, [x19, #24]
	bl	_tw32_f
	mov	w0, #40
	bl	_udelay
	mov	x0, x19
	mov	x1, x20
	bl	_tg3_phy_eee_adjust
Lloh207:
	adrp	x8, _USE_LINKCHG_REG@GOTPAGE
Lloh208:
	ldr	x8, [x8, _USE_LINKCHG_REG@GOTPAGEOFF]
Lloh209:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_tg3_flag
Lloh210:
	adrp	x8, _MAC_EVENT@GOTPAGE
Lloh211:
	ldr	x8, [x8, _MAC_EVENT@GOTPAGEOFF]
Lloh212:
	ldr	w8, [x8]
Lloh213:
	adrp	x9, _MAC_EVENT_LNKSTATE_CHANGED@GOTPAGE
Lloh214:
	ldr	x9, [x9, _MAC_EVENT_LNKSTATE_CHANGED@GOTPAGEOFF]
Lloh215:
	ldr	w9, [x9]
	cmp	x0, #0
	csel	w1, w9, wzr, eq
	mov	x0, x8
	bl	_tw32_f
	mov	w0, #40
	bl	_udelay
	mov	x0, x19
	bl	_tg3_asic_rev
	ldr	x8, [x27]
	cmp	x0, x8
	cset	w8, ne
	eor	w9, w20, #0x1
	orr	w8, w9, w8
	tbnz	w8, #0, LBB0_108
; %bb.104:
	ldr	x8, [x19, #32]
Lloh216:
	adrp	x9, _SPEED_1000@GOTPAGE
Lloh217:
	ldr	x9, [x9, _SPEED_1000@GOTPAGEOFF]
Lloh218:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_108
; %bb.105:
Lloh219:
	adrp	x8, _PCIX_MODE@GOTPAGE
Lloh220:
	ldr	x8, [x8, _PCIX_MODE@GOTPAGEOFF]
Lloh221:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_tg3_flag
	cbnz	x0, LBB0_107
; %bb.106:
Lloh222:
	adrp	x8, _PCI_HIGH_SPEED@GOTPAGE
Lloh223:
	ldr	x8, [x8, _PCI_HIGH_SPEED@GOTPAGEOFF]
Lloh224:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_tg3_flag
	cbz	x0, LBB0_108
LBB0_107:
	mov	w0, #120
	bl	_udelay
Lloh225:
	adrp	x8, _MAC_STATUS@GOTPAGE
Lloh226:
	ldr	x8, [x8, _MAC_STATUS@GOTPAGEOFF]
Lloh227:
	adrp	x9, _MAC_STATUS_SYNC_CHANGED@GOTPAGE
Lloh228:
	ldr	x9, [x9, _MAC_STATUS_SYNC_CHANGED@GOTPAGEOFF]
Lloh229:
	ldr	w0, [x8]
Lloh230:
	ldr	w8, [x9]
Lloh231:
	adrp	x9, _MAC_STATUS_CFG_CHANGED@GOTPAGE
Lloh232:
	ldr	x9, [x9, _MAC_STATUS_CFG_CHANGED@GOTPAGEOFF]
Lloh233:
	ldr	w9, [x9]
	orr	w1, w9, w8
	bl	_tw32_f
	mov	w0, #40
	bl	_udelay
Lloh234:
	adrp	x8, _NIC_SRAM_FIRMWARE_MBOX@GOTPAGE
Lloh235:
	ldr	x8, [x8, _NIC_SRAM_FIRMWARE_MBOX@GOTPAGEOFF]
Lloh236:
	ldr	w1, [x8]
Lloh237:
	adrp	x8, _NIC_SRAM_FIRMWARE_MBOX_MAGIC2@GOTPAGE
Lloh238:
	ldr	x8, [x8, _NIC_SRAM_FIRMWARE_MBOX_MAGIC2@GOTPAGEOFF]
Lloh239:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_tg3_write_mem
LBB0_108:
Lloh240:
	adrp	x8, _CLKREQ_BUG@GOTPAGE
Lloh241:
	ldr	x8, [x8, _CLKREQ_BUG@GOTPAGEOFF]
Lloh242:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_tg3_flag
	cbz	x0, LBB0_113
; %bb.109:
	ldr	x8, [x19, #32]
	ldr	x9, [x26]
Lloh243:
	adrp	x10, _PCI_EXP_LNKCTL@GOTPAGE
Lloh244:
	ldr	x10, [x10, _PCI_EXP_LNKCTL@GOTPAGEOFF]
	ldr	w0, [x19, #28]
Lloh245:
	ldr	w1, [x10]
Lloh246:
	adrp	x10, _PCI_EXP_LNKCTL_CLKREQ_EN@GOTPAGE
Lloh247:
	ldr	x10, [x10, _PCI_EXP_LNKCTL_CLKREQ_EN@GOTPAGEOFF]
Lloh248:
	ldr	w2, [x10]
	cmp	x8, x9
	b.eq	LBB0_112
; %bb.110:
	ldr	x9, [x25]
	cmp	x8, x9
	b.eq	LBB0_112
; %bb.111:
	bl	_pcie_capability_set_word
	b	LBB0_113
LBB0_112:
	bl	_pcie_capability_clear_word
LBB0_113:
	mov	x0, x19
	mov	x1, x20
	bl	_tg3_test_and_report_link_chg
	mov	w0, #0
LBB0_114:
	ldp	x29, x30, [sp, #128]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #112]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #96]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #80]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #64]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #144
	ret
LBB0_115:
Lloh249:
	adrp	x8, _MII_TG3_IMASK@GOTPAGE
Lloh250:
	ldr	x8, [x8, _MII_TG3_IMASK@GOTPAGEOFF]
Lloh251:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1
	b	LBB0_23
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGot	Lloh79, Lloh80
	.loh AdrpLdrGot	Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGot	Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGot	Lloh81, Lloh82
	.loh AdrpLdrGot	Lloh83, Lloh84
	.loh AdrpLdrGot	Lloh85, Lloh86
	.loh AdrpLdrGot	Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGot	Lloh109, Lloh110
	.loh AdrpLdrGot	Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGot	Lloh116, Lloh117
	.loh AdrpLdrGot	Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGot	Lloh120, Lloh121
	.loh AdrpLdrGot	Lloh118, Lloh119
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh128, Lloh129, Lloh130
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh131, Lloh132, Lloh133
	.loh AdrpLdrGot	Lloh139, Lloh140
	.loh AdrpLdrGot	Lloh137, Lloh138
	.loh AdrpLdrGotLdr	Lloh134, Lloh135, Lloh136
	.loh AdrpLdrGotLdr	Lloh141, Lloh142, Lloh143
	.loh AdrpLdrGot	Lloh146, Lloh147
	.loh AdrpLdrGot	Lloh144, Lloh145
	.loh AdrpLdrGotLdr	Lloh148, Lloh149, Lloh150
	.loh AdrpLdrGotLdr	Lloh156, Lloh157, Lloh158
	.loh AdrpLdrGotLdr	Lloh153, Lloh154, Lloh155
	.loh AdrpLdrGot	Lloh151, Lloh152
	.loh AdrpLdrGotLdr	Lloh159, Lloh160, Lloh161
	.loh AdrpLdrGotLdr	Lloh162, Lloh163, Lloh164
	.loh AdrpLdrGotLdr	Lloh168, Lloh169, Lloh170
	.loh AdrpLdrGotLdr	Lloh165, Lloh166, Lloh167
	.loh AdrpLdrGotLdr	Lloh171, Lloh172, Lloh173
	.loh AdrpLdrGotLdr	Lloh174, Lloh175, Lloh176
	.loh AdrpLdrGotLdr	Lloh177, Lloh178, Lloh179
	.loh AdrpLdrGotLdr	Lloh183, Lloh184, Lloh185
	.loh AdrpLdrGotLdr	Lloh180, Lloh181, Lloh182
	.loh AdrpLdrGotLdr	Lloh186, Lloh187, Lloh188
	.loh AdrpLdrGotLdr	Lloh189, Lloh190, Lloh191
	.loh AdrpLdrGotLdr	Lloh192, Lloh193, Lloh194
	.loh AdrpLdrGotLdr	Lloh195, Lloh196, Lloh197
	.loh AdrpLdrGotLdr	Lloh201, Lloh202, Lloh203
	.loh AdrpLdrGotLdr	Lloh198, Lloh199, Lloh200
	.loh AdrpLdrGotLdr	Lloh213, Lloh214, Lloh215
	.loh AdrpLdrGotLdr	Lloh210, Lloh211, Lloh212
	.loh AdrpLdrGotLdr	Lloh207, Lloh208, Lloh209
	.loh AdrpLdrGotLdr	Lloh204, Lloh205, Lloh206
	.loh AdrpLdrGotLdr	Lloh216, Lloh217, Lloh218
	.loh AdrpLdrGotLdr	Lloh219, Lloh220, Lloh221
	.loh AdrpLdrGotLdr	Lloh222, Lloh223, Lloh224
	.loh AdrpLdrGotLdr	Lloh237, Lloh238, Lloh239
	.loh AdrpLdrGotLdr	Lloh234, Lloh235, Lloh236
	.loh AdrpLdrGotLdr	Lloh231, Lloh232, Lloh233
	.loh AdrpLdrGotLdr	Lloh227, Lloh228, Lloh230
	.loh AdrpLdrGotLdr	Lloh225, Lloh226, Lloh229
	.loh AdrpLdrGotLdr	Lloh240, Lloh241, Lloh242
	.loh AdrpLdrGotLdr	Lloh246, Lloh247, Lloh248
	.loh AdrpLdrGotLdr	Lloh243, Lloh244, Lloh245
	.loh AdrpLdrGotLdr	Lloh249, Lloh250, Lloh251
	.cfi_endproc
                                        ; -- End function
	.comm	_MAC_MI_MODE_AUTO_POLL,4,2      ; @MAC_MI_MODE_AUTO_POLL
	.comm	_MAC_MI_MODE,4,2                ; @MAC_MI_MODE
	.comm	_MII_TG3_AUXCTL_SHDWSEL_PWRCTL,4,2 ; @MII_TG3_AUXCTL_SHDWSEL_PWRCTL
	.comm	_ASIC_REV_5703,8,3              ; @ASIC_REV_5703
	.comm	_ASIC_REV_5704,8,3              ; @ASIC_REV_5704
	.comm	_ASIC_REV_5705,8,3              ; @ASIC_REV_5705
	.comm	_MII_BMSR,4,2                   ; @MII_BMSR
	.comm	_BMSR_LSTATUS,4,2               ; @BMSR_LSTATUS
	.comm	_TG3_PHY_ID_MASK,4,2            ; @TG3_PHY_ID_MASK
	.comm	_TG3_PHY_ID_BCM5401,4,2         ; @TG3_PHY_ID_BCM5401
	.comm	_INIT_COMPLETE,4,2              ; @INIT_COMPLETE
	.comm	_TG3_PHY_ID_REV_MASK,4,2        ; @TG3_PHY_ID_REV_MASK
	.comm	_TG3_PHY_REV_BCM5401_B0,4,2     ; @TG3_PHY_REV_BCM5401_B0
	.comm	_SPEED_1000,8,3                 ; @SPEED_1000
	.comm	_CHIPREV_ID_5701_A0,8,3         ; @CHIPREV_ID_5701_A0
	.comm	_CHIPREV_ID_5701_B0,8,3         ; @CHIPREV_ID_5701_B0
	.comm	_MII_TG3_MISC_SHDW,4,2          ; @MII_TG3_MISC_SHDW
	.comm	_MII_TG3_ISTAT,4,2              ; @MII_TG3_ISTAT
	.comm	_TG3_PHYFLG_USE_MI_INTERRUPT,4,2 ; @TG3_PHYFLG_USE_MI_INTERRUPT
	.comm	_MII_TG3_IMASK,4,2              ; @MII_TG3_IMASK
	.comm	_MII_TG3_INT_LINKCHG,4,2        ; @MII_TG3_INT_LINKCHG
	.comm	_TG3_PHYFLG_IS_FET,4,2          ; @TG3_PHYFLG_IS_FET
	.comm	_ASIC_REV_5700,8,3              ; @ASIC_REV_5700
	.comm	_ASIC_REV_5701,8,3              ; @ASIC_REV_5701
	.comm	_LED_CTRL_MODE_PHY_1,8,3        ; @LED_CTRL_MODE_PHY_1
	.comm	_MII_TG3_EXT_CTRL,4,2           ; @MII_TG3_EXT_CTRL
	.comm	_MII_TG3_EXT_CTRL_LNK3_LED_MODE,4,2 ; @MII_TG3_EXT_CTRL_LNK3_LED_MODE
	.comm	_SPEED_UNKNOWN,8,3              ; @SPEED_UNKNOWN
	.comm	_DUPLEX_UNKNOWN,8,3             ; @DUPLEX_UNKNOWN
	.comm	_TG3_PHYFLG_MDIX_STATE,4,2      ; @TG3_PHYFLG_MDIX_STATE
	.comm	_TG3_PHYFLG_CAPACITIVE_COUPLING,4,2 ; @TG3_PHYFLG_CAPACITIVE_COUPLING
	.comm	_MII_TG3_AUXCTL_SHDWSEL_MISCTEST,4,2 ; @MII_TG3_AUXCTL_SHDWSEL_MISCTEST
	.comm	_MII_TG3_AUX_STAT,4,2           ; @MII_TG3_AUX_STAT
	.comm	_MII_BMCR,4,2                   ; @MII_BMCR
	.comm	_AUTONEG_ENABLE,8,3             ; @AUTONEG_ENABLE
	.comm	_BMCR_ANENABLE,4,2              ; @BMCR_ANENABLE
	.comm	_TG3_PHYFLG_KEEP_LINK_ON_PWRDN,4,2 ; @TG3_PHYFLG_KEEP_LINK_ON_PWRDN
	.comm	_DUPLEX_FULL,8,3                ; @DUPLEX_FULL
	.comm	_MII_TG3_FET_GEN_STAT,4,2       ; @MII_TG3_FET_GEN_STAT
	.comm	_MII_TG3_FET_GEN_STAT_MDIXSTAT,4,2 ; @MII_TG3_FET_GEN_STAT_MDIXSTAT
	.comm	_MII_TG3_EXT_STAT,4,2           ; @MII_TG3_EXT_STAT
	.comm	_MII_TG3_EXT_STAT_MDIX,4,2      ; @MII_TG3_EXT_STAT_MDIX
	.comm	_TG3_PHYFLG_IS_LOW_POWER,4,2    ; @TG3_PHYFLG_IS_LOW_POWER
	.comm	_ROBOSWITCH,4,2                 ; @ROBOSWITCH
	.comm	_MAC_MODE_PORT_MODE_MASK,4,2    ; @MAC_MODE_PORT_MODE_MASK
	.comm	_SPEED_100,8,3                  ; @SPEED_100
	.comm	_SPEED_10,8,3                   ; @SPEED_10
	.comm	_MAC_MODE_PORT_MODE_MII,4,2     ; @MAC_MODE_PORT_MODE_MII
	.comm	_MAC_MODE_PORT_MODE_GMII,4,2    ; @MAC_MODE_PORT_MODE_GMII
	.comm	_RGMII_MODE,4,2                 ; @RGMII_MODE
	.comm	_MAC_LED_CTRL,4,2               ; @MAC_LED_CTRL
	.comm	_LED_CTRL_1000MBPS_ON,4,2       ; @LED_CTRL_1000MBPS_ON
	.comm	_LED_CTRL_100MBPS_ON,4,2        ; @LED_CTRL_100MBPS_ON
	.comm	_LED_CTRL_LNKLED_OVERRIDE,4,2   ; @LED_CTRL_LNKLED_OVERRIDE
	.comm	_MAC_MODE_HALF_DUPLEX,4,2       ; @MAC_MODE_HALF_DUPLEX
	.comm	_DUPLEX_HALF,8,3                ; @DUPLEX_HALF
	.comm	_MAC_MODE_LINK_POLARITY,4,2     ; @MAC_MODE_LINK_POLARITY
	.comm	_TG3_PHY_ID_BCM5411,4,2         ; @TG3_PHY_ID_BCM5411
	.comm	_CHIPREV_ID_5700_ALTIMA,8,3     ; @CHIPREV_ID_5700_ALTIMA
	.comm	_MAC_MODE,4,2                   ; @MAC_MODE
	.comm	_USE_LINKCHG_REG,4,2            ; @USE_LINKCHG_REG
	.comm	_MAC_EVENT,4,2                  ; @MAC_EVENT
	.comm	_MAC_EVENT_LNKSTATE_CHANGED,4,2 ; @MAC_EVENT_LNKSTATE_CHANGED
	.comm	_PCIX_MODE,4,2                  ; @PCIX_MODE
	.comm	_PCI_HIGH_SPEED,4,2             ; @PCI_HIGH_SPEED
	.comm	_MAC_STATUS,4,2                 ; @MAC_STATUS
	.comm	_MAC_STATUS_SYNC_CHANGED,4,2    ; @MAC_STATUS_SYNC_CHANGED
	.comm	_MAC_STATUS_CFG_CHANGED,4,2     ; @MAC_STATUS_CFG_CHANGED
	.comm	_NIC_SRAM_FIRMWARE_MBOX,4,2     ; @NIC_SRAM_FIRMWARE_MBOX
	.comm	_NIC_SRAM_FIRMWARE_MBOX_MAGIC2,4,2 ; @NIC_SRAM_FIRMWARE_MBOX_MAGIC2
	.comm	_CLKREQ_BUG,4,2                 ; @CLKREQ_BUG
	.comm	_PCI_EXP_LNKCTL,4,2             ; @PCI_EXP_LNKCTL
	.comm	_PCI_EXP_LNKCTL_CLKREQ_EN,4,2   ; @PCI_EXP_LNKCTL_CLKREQ_EN
	.no_dead_strip	_tg3_setup_copper_phy
.subsections_via_symbols
