	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function bnx2x_warpcore_set_20G_DXGXS
_bnx2x_warpcore_set_20G_DXGXS:          ## @bnx2x_warpcore_set_20G_DXGXS
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, -44(%rbp)                 ## 4-byte Spill
	movq	%rsi, %r14
	movq	%rdi, %r15
	movq	_MDIO_WC_DEVAD@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	_MDIO_WC_REG_RX0_ANARXCONTROL1G@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movl	$144, %r8d
	callq	_bnx2x_cl45_write
	movl	(%rbx), %edx
	movq	_MDIO_WC_REG_RX2_ANARXCONTROL1G@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	$144, %r8d
	callq	_bnx2x_cl45_write
	movl	(%rbx), %edx
	movq	_MDIO_WC_REG_RX66_SCW0@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	$57456, %r8d                    ## imm = 0xE070
	callq	_bnx2x_cl45_write
	movl	(%rbx), %edx
	movq	_MDIO_WC_REG_RX66_SCW1@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	$49360, %r8d                    ## imm = 0xC0D0
	callq	_bnx2x_cl45_write
	movl	(%rbx), %edx
	movq	_MDIO_WC_REG_RX66_SCW2@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	$41136, %r8d                    ## imm = 0xA0B0
	callq	_bnx2x_cl45_write
	movl	(%rbx), %edx
	movq	_MDIO_WC_REG_RX66_SCW3@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	$32912, %r8d                    ## imm = 0x8090
	callq	_bnx2x_cl45_write
	movl	(%rbx), %edx
	movq	_MDIO_WC_REG_RX66_SCW0_MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	$61680, %r8d                    ## imm = 0xF0F0
	callq	_bnx2x_cl45_write
	movl	(%rbx), %edx
	movq	_MDIO_WC_REG_RX66_SCW1_MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	$61680, %r8d                    ## imm = 0xF0F0
	callq	_bnx2x_cl45_write
	movl	(%rbx), %edx
	movq	_MDIO_WC_REG_RX66_SCW2_MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	$61680, %r8d                    ## imm = 0xF0F0
	callq	_bnx2x_cl45_write
	movl	(%rbx), %edx
	movq	_MDIO_WC_REG_RX66_SCW3_MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	$61680, %r8d                    ## imm = 0xF0F0
	callq	_bnx2x_cl45_write
	movl	(%rbx), %edx
	movq	_MDIO_WC_REG_SERDESDIGITAL_MISC1@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	$24584, %r8d                    ## imm = 0x6008
	callq	_bnx2x_cl45_write
	movl	(%rbx), %edx
	movq	_MDIO_WC_REG_DIGITAL4_MISC3@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	$32904, %r8d                    ## imm = 0x8088
	callq	_bnx2x_cl45_write
	movl	(%rbx), %r12d
	movq	_MDIO_WC_REG_TX_FIR_TAP@GOTPCREL(%rip), %rax
	movq	(%rax), %r13
	movl	$18, %edi
	movl	$45, %esi
	xorl	%edx, %edx
	callq	_WC_TX_FIR
	movq	_MDIO_WC_REG_TX_FIR_TAP_ENABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%r12d, %edx
	movq	%r13, %rcx
	movl	%eax, %r8d
	callq	_bnx2x_cl45_write
	movl	(%rbx), %r12d
	movq	_MDIO_WC_REG_TX0_TX_DRIVER@GOTPCREL(%rip), %rax
	movl	-44(%rbp), %ecx                 ## 4-byte Reload
	shll	$4, %ecx
	movslq	%ecx, %rbx
	addq	(%rax), %rbx
	movl	$2, %edi
	movl	$2, %esi
	movl	$2, %edx
	callq	_WC_TX_DRIVER
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%r12d, %edx
	movq	%rbx, %rcx
	movl	%eax, %r8d
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_bnx2x_cl45_write               ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_MDIO_WC_DEVAD,4,2              ## @MDIO_WC_DEVAD
	.comm	_MDIO_WC_REG_RX0_ANARXCONTROL1G,8,3 ## @MDIO_WC_REG_RX0_ANARXCONTROL1G
	.comm	_MDIO_WC_REG_RX2_ANARXCONTROL1G,8,3 ## @MDIO_WC_REG_RX2_ANARXCONTROL1G
	.comm	_MDIO_WC_REG_RX66_SCW0,8,3      ## @MDIO_WC_REG_RX66_SCW0
	.comm	_MDIO_WC_REG_RX66_SCW1,8,3      ## @MDIO_WC_REG_RX66_SCW1
	.comm	_MDIO_WC_REG_RX66_SCW2,8,3      ## @MDIO_WC_REG_RX66_SCW2
	.comm	_MDIO_WC_REG_RX66_SCW3,8,3      ## @MDIO_WC_REG_RX66_SCW3
	.comm	_MDIO_WC_REG_RX66_SCW0_MASK,8,3 ## @MDIO_WC_REG_RX66_SCW0_MASK
	.comm	_MDIO_WC_REG_RX66_SCW1_MASK,8,3 ## @MDIO_WC_REG_RX66_SCW1_MASK
	.comm	_MDIO_WC_REG_RX66_SCW2_MASK,8,3 ## @MDIO_WC_REG_RX66_SCW2_MASK
	.comm	_MDIO_WC_REG_RX66_SCW3_MASK,8,3 ## @MDIO_WC_REG_RX66_SCW3_MASK
	.comm	_MDIO_WC_REG_SERDESDIGITAL_MISC1,8,3 ## @MDIO_WC_REG_SERDESDIGITAL_MISC1
	.comm	_MDIO_WC_REG_DIGITAL4_MISC3,8,3 ## @MDIO_WC_REG_DIGITAL4_MISC3
	.comm	_MDIO_WC_REG_TX_FIR_TAP,8,3     ## @MDIO_WC_REG_TX_FIR_TAP
	.comm	_MDIO_WC_REG_TX_FIR_TAP_ENABLE,4,2 ## @MDIO_WC_REG_TX_FIR_TAP_ENABLE
	.comm	_MDIO_WC_REG_TX0_TX_DRIVER,8,3  ## @MDIO_WC_REG_TX0_TX_DRIVER
	.no_dead_strip	_bnx2x_warpcore_set_20G_DXGXS
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function bnx2x_warpcore_set_20G_DXGXS
_bnx2x_warpcore_set_20G_DXGXS:          ; @bnx2x_warpcore_set_20G_DXGXS
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x21, x2
	mov	x19, x1
	mov	x20, x0
Lloh0:
	adrp	x24, _MDIO_WC_DEVAD@GOTPAGE
Lloh1:
	ldr	x24, [x24, _MDIO_WC_DEVAD@GOTPAGEOFF]
	ldr	w2, [x24]
Lloh2:
	adrp	x8, _MDIO_WC_REG_RX0_ANARXCONTROL1G@GOTPAGE
Lloh3:
	ldr	x8, [x8, _MDIO_WC_REG_RX0_ANARXCONTROL1G@GOTPAGEOFF]
Lloh4:
	ldr	x3, [x8]
	mov	w4, #144
	bl	_bnx2x_cl45_write
	ldr	w2, [x24]
Lloh5:
	adrp	x8, _MDIO_WC_REG_RX2_ANARXCONTROL1G@GOTPAGE
Lloh6:
	ldr	x8, [x8, _MDIO_WC_REG_RX2_ANARXCONTROL1G@GOTPAGEOFF]
Lloh7:
	ldr	x3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	w4, #144
	bl	_bnx2x_cl45_write
	ldr	w2, [x24]
Lloh8:
	adrp	x8, _MDIO_WC_REG_RX66_SCW0@GOTPAGE
Lloh9:
	ldr	x8, [x8, _MDIO_WC_REG_RX66_SCW0@GOTPAGEOFF]
Lloh10:
	ldr	x3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	w4, #57456
	bl	_bnx2x_cl45_write
	ldr	w2, [x24]
Lloh11:
	adrp	x8, _MDIO_WC_REG_RX66_SCW1@GOTPAGE
Lloh12:
	ldr	x8, [x8, _MDIO_WC_REG_RX66_SCW1@GOTPAGEOFF]
Lloh13:
	ldr	x3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	w4, #49360
	bl	_bnx2x_cl45_write
	ldr	w2, [x24]
Lloh14:
	adrp	x8, _MDIO_WC_REG_RX66_SCW2@GOTPAGE
Lloh15:
	ldr	x8, [x8, _MDIO_WC_REG_RX66_SCW2@GOTPAGEOFF]
Lloh16:
	ldr	x3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	w4, #41136
	bl	_bnx2x_cl45_write
	ldr	w2, [x24]
Lloh17:
	adrp	x8, _MDIO_WC_REG_RX66_SCW3@GOTPAGE
Lloh18:
	ldr	x8, [x8, _MDIO_WC_REG_RX66_SCW3@GOTPAGEOFF]
Lloh19:
	ldr	x3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	w4, #32912
	bl	_bnx2x_cl45_write
	ldr	w2, [x24]
Lloh20:
	adrp	x8, _MDIO_WC_REG_RX66_SCW0_MASK@GOTPAGE
Lloh21:
	ldr	x8, [x8, _MDIO_WC_REG_RX66_SCW0_MASK@GOTPAGEOFF]
Lloh22:
	ldr	x3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	w4, #61680
	bl	_bnx2x_cl45_write
	ldr	w2, [x24]
Lloh23:
	adrp	x8, _MDIO_WC_REG_RX66_SCW1_MASK@GOTPAGE
Lloh24:
	ldr	x8, [x8, _MDIO_WC_REG_RX66_SCW1_MASK@GOTPAGEOFF]
Lloh25:
	ldr	x3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	w4, #61680
	bl	_bnx2x_cl45_write
	ldr	w2, [x24]
Lloh26:
	adrp	x8, _MDIO_WC_REG_RX66_SCW2_MASK@GOTPAGE
Lloh27:
	ldr	x8, [x8, _MDIO_WC_REG_RX66_SCW2_MASK@GOTPAGEOFF]
Lloh28:
	ldr	x3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	w4, #61680
	bl	_bnx2x_cl45_write
	ldr	w2, [x24]
Lloh29:
	adrp	x8, _MDIO_WC_REG_RX66_SCW3_MASK@GOTPAGE
Lloh30:
	ldr	x8, [x8, _MDIO_WC_REG_RX66_SCW3_MASK@GOTPAGEOFF]
Lloh31:
	ldr	x3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	w4, #61680
	bl	_bnx2x_cl45_write
	ldr	w2, [x24]
Lloh32:
	adrp	x8, _MDIO_WC_REG_SERDESDIGITAL_MISC1@GOTPAGE
Lloh33:
	ldr	x8, [x8, _MDIO_WC_REG_SERDESDIGITAL_MISC1@GOTPAGEOFF]
Lloh34:
	ldr	x3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	w4, #24584
	bl	_bnx2x_cl45_write
	ldr	w2, [x24]
Lloh35:
	adrp	x8, _MDIO_WC_REG_DIGITAL4_MISC3@GOTPAGE
Lloh36:
	ldr	x8, [x8, _MDIO_WC_REG_DIGITAL4_MISC3@GOTPAGEOFF]
Lloh37:
	ldr	x3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	w4, #32904
	bl	_bnx2x_cl45_write
	ldr	w22, [x24]
Lloh38:
	adrp	x8, _MDIO_WC_REG_TX_FIR_TAP@GOTPAGE
Lloh39:
	ldr	x8, [x8, _MDIO_WC_REG_TX_FIR_TAP@GOTPAGEOFF]
Lloh40:
	ldr	x23, [x8]
	mov	w0, #18
	mov	w1, #45
	mov	w2, #0
	bl	_WC_TX_FIR
Lloh41:
	adrp	x8, _MDIO_WC_REG_TX_FIR_TAP_ENABLE@GOTPAGE
Lloh42:
	ldr	x8, [x8, _MDIO_WC_REG_TX_FIR_TAP_ENABLE@GOTPAGEOFF]
Lloh43:
	ldr	w8, [x8]
	orr	w4, w8, w0
	mov	x0, x20
	mov	x1, x19
	mov	x2, x22
	mov	x3, x23
	bl	_bnx2x_cl45_write
	ldr	w22, [x24]
Lloh44:
	adrp	x8, _MDIO_WC_REG_TX0_TX_DRIVER@GOTPAGE
Lloh45:
	ldr	x8, [x8, _MDIO_WC_REG_TX0_TX_DRIVER@GOTPAGEOFF]
Lloh46:
	ldr	x8, [x8]
	lsl	w9, w21, #4
	add	x21, x8, w9, sxtw
	mov	w0, #2
	mov	w1, #2
	mov	w2, #2
	bl	_WC_TX_DRIVER
	mov	x4, x0
	mov	x0, x20
	mov	x1, x19
	mov	x2, x22
	mov	x3, x21
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_bnx2x_cl45_write
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_MDIO_WC_DEVAD,4,2              ; @MDIO_WC_DEVAD
	.comm	_MDIO_WC_REG_RX0_ANARXCONTROL1G,8,3 ; @MDIO_WC_REG_RX0_ANARXCONTROL1G
	.comm	_MDIO_WC_REG_RX2_ANARXCONTROL1G,8,3 ; @MDIO_WC_REG_RX2_ANARXCONTROL1G
	.comm	_MDIO_WC_REG_RX66_SCW0,8,3      ; @MDIO_WC_REG_RX66_SCW0
	.comm	_MDIO_WC_REG_RX66_SCW1,8,3      ; @MDIO_WC_REG_RX66_SCW1
	.comm	_MDIO_WC_REG_RX66_SCW2,8,3      ; @MDIO_WC_REG_RX66_SCW2
	.comm	_MDIO_WC_REG_RX66_SCW3,8,3      ; @MDIO_WC_REG_RX66_SCW3
	.comm	_MDIO_WC_REG_RX66_SCW0_MASK,8,3 ; @MDIO_WC_REG_RX66_SCW0_MASK
	.comm	_MDIO_WC_REG_RX66_SCW1_MASK,8,3 ; @MDIO_WC_REG_RX66_SCW1_MASK
	.comm	_MDIO_WC_REG_RX66_SCW2_MASK,8,3 ; @MDIO_WC_REG_RX66_SCW2_MASK
	.comm	_MDIO_WC_REG_RX66_SCW3_MASK,8,3 ; @MDIO_WC_REG_RX66_SCW3_MASK
	.comm	_MDIO_WC_REG_SERDESDIGITAL_MISC1,8,3 ; @MDIO_WC_REG_SERDESDIGITAL_MISC1
	.comm	_MDIO_WC_REG_DIGITAL4_MISC3,8,3 ; @MDIO_WC_REG_DIGITAL4_MISC3
	.comm	_MDIO_WC_REG_TX_FIR_TAP,8,3     ; @MDIO_WC_REG_TX_FIR_TAP
	.comm	_MDIO_WC_REG_TX_FIR_TAP_ENABLE,4,2 ; @MDIO_WC_REG_TX_FIR_TAP_ENABLE
	.comm	_MDIO_WC_REG_TX0_TX_DRIVER,8,3  ; @MDIO_WC_REG_TX0_TX_DRIVER
	.no_dead_strip	_bnx2x_warpcore_set_20G_DXGXS
.subsections_via_symbols
