	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function avivo_crtc_do_set_base
_avivo_crtc_do_set_base:                ## @avivo_crtc_do_set_base
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%r8d, %ebx
	movl	%ecx, -68(%rbp)                 ## 4-byte Spill
	movl	%edx, -72(%rbp)                 ## 4-byte Spill
	movq	%rsi, %r12
	movq	%rdi, %r13
	callq	_to_radeon_crtc
	movq	%rax, %r15
	movq	16(%r13), %rax
	movq	(%rax), %r14
	movq	_R600_D1GRPH_SWAP_ENDIAN_NONE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%ebx, -56(%rbp)                 ## 4-byte Spill
	testl	%ebx, %ebx
	je	LBB0_1
## %bb.3:
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movq	%r12, %rdi
	callq	_to_radeon_framebuffer
	movq	%r12, -88(%rbp)                 ## 8-byte Spill
	movq	%r12, -64(%rbp)                 ## 8-byte Spill
	jmp	LBB0_5
LBB0_1:
	movq	(%r13), %rdi
	testq	%rdi, %rdi
	je	LBB0_2
## %bb.4:
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movq	%r12, -88(%rbp)                 ## 8-byte Spill
	callq	_to_radeon_framebuffer
	movq	(%r13), %rcx
	movq	%rcx, -64(%rbp)                 ## 8-byte Spill
LBB0_5:
	movq	(%rax), %rdi
	callq	_gem_to_radeon_bo
	movq	%rax, %r12
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	_radeon_bo_reserve
	movl	%eax, %ebx
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	callq	_unlikely
	testq	%rax, %rax
	jne	LBB0_41
## %bb.6:
	cmpl	$0, -56(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_10
## %bb.7:
	movq	%r12, %rdi
	callq	_radeon_bo_gpu_offset
	movq	%rax, -48(%rbp)
LBB0_8:
	xorl	%ebx, %ebx
	leaq	-76(%rbp), %rsi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_radeon_bo_get_tiling_flags
	movq	%r12, %rdi
	callq	_radeon_bo_unreserve
	movq	-64(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %esi
	leal	-8(%rsi), %edx
	cmpl	$24, %edx
	ja	LBB0_14
## %bb.9:
	movq	_AVIVO_D1GRPH_CONTROL_8BPP_INDEXED@GOTPCREL(%rip), %rax
	movq	_AVIVO_D1GRPH_CONTROL_DEPTH_8BPP@GOTPCREL(%rip), %rcx
	leaq	LJTI0_0(%rip), %rdi
	movslq	(%rdi,%rdx,4), %rdx
	addq	%rdi, %rdx
	jmpq	*%rdx
LBB0_13:
	movq	_AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888@GOTPCREL(%rip), %rax
	movq	_AVIVO_D1GRPH_CONTROL_DEPTH_32BPP@GOTPCREL(%rip), %rcx
	jmp	LBB0_17
LBB0_2:
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	jmp	LBB0_40
LBB0_10:
	movq	_RADEON_GEM_DOMAIN_VRAM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-48(%rbp), %rdx
	movq	%r12, %rdi
	callq	_radeon_bo_pin
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	callq	_unlikely
	testq	%rax, %rax
	je	LBB0_8
## %bb.11:
	movq	%r12, %rdi
	callq	_radeon_bo_unreserve
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
	jmp	LBB0_41
LBB0_14:
	leaq	L_.str.1(%rip), %rdi
                                        ## kill: def $esi killed $esi killed $rsi
	callq	_DRM_ERROR
	movq	_EINVAL@GOTPCREL(%rip), %rax
	subl	(%rax), %ebx
	jmp	LBB0_41
LBB0_15:
	movq	_AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555@GOTPCREL(%rip), %rax
	jmp	LBB0_16
LBB0_12:
	movq	_AVIVO_D1GRPH_CONTROL_16BPP_RGB565@GOTPCREL(%rip), %rax
LBB0_16:
	movq	_AVIVO_D1GRPH_CONTROL_DEPTH_16BPP@GOTPCREL(%rip), %rcx
LBB0_17:
	movl	(%rax), %r12d
	orl	(%rcx), %r12d
	movq	(%r14), %rdx
	movq	_CHIP_R600@GOTPCREL(%rip), %rbx
	movl	-76(%rbp), %eax
	movq	_RADEON_TILING_MACRO@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	cmpq	(%rbx), %rdx
	jge	LBB0_18
## %bb.22:
	andl	%eax, %ecx
	je	LBB0_24
## %bb.23:
	movq	_AVIVO_D1GRPH_MACRO_ADDRESS_MODE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_24:
	orl	%ecx, %r12d
	movq	_RADEON_TILING_MICRO@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_27
## %bb.25:
	movq	_AVIVO_D1GRPH_TILED@GOTPCREL(%rip), %rax
	jmp	LBB0_26
LBB0_18:
	testl	%eax, %ecx
	je	LBB0_20
## %bb.19:
	movq	_R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1@GOTPCREL(%rip), %rax
	jmp	LBB0_26
LBB0_20:
	movq	_RADEON_TILING_MICRO@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_27
## %bb.21:
	movq	_R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1@GOTPCREL(%rip), %rax
LBB0_26:
	orl	(%rax), %r12d
LBB0_27:
	cmpq	$0, (%r15)
	jne	LBB0_28
## %bb.29:
	movq	_AVIVO_D1VGA_CONTROL@GOTPCREL(%rip), %rax
	jmp	LBB0_30
LBB0_28:
	movq	_AVIVO_D2VGA_CONTROL@GOTPCREL(%rip), %rax
LBB0_30:
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%r14), %rax
	movq	_CHIP_RV770@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_32
## %bb.31:
	cmpq	$0, (%r15)
	movq	-48(%rbp), %rdi
	movq	_R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH@GOTPCREL(%rip), %rax
	cmoveq	_R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH@GOTPCREL(%rip), %rax
	movq	(%rax), %rbx
	movq	%r14, -96(%rbp)                 ## 8-byte Spill
	movq	_R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH@GOTPCREL(%rip), %r14
	cmoveq	_R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH@GOTPCREL(%rip), %r14
	callq	_upper_32_bits
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	(%r14), %rbx
	movq	-96(%rbp), %r14                 ## 8-byte Reload
	movq	-48(%rbp), %rdi
	callq	_upper_32_bits
	movq	%rbx, %rdi
	movq	_CHIP_R600@GOTPCREL(%rip), %rbx
	movl	%eax, %esi
	callq	_WREG32
LBB0_32:
	movq	_AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS@GOTPCREL(%rip), %rax
	movq	8(%r15), %rdi
	addq	(%rax), %rdi
	movl	-48(%rbp), %esi
	callq	_WREG32
	movq	_AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS@GOTPCREL(%rip), %rax
	movq	8(%r15), %rdi
	addq	(%rax), %rdi
	movl	-48(%rbp), %esi
	callq	_WREG32
	movq	_AVIVO_D1GRPH_CONTROL@GOTPCREL(%rip), %rax
	movq	8(%r15), %rdi
	addq	(%rax), %rdi
	movl	%r12d, %esi
	callq	_WREG32
	movq	(%r14), %rax
	cmpq	(%rbx), %rax
	jl	LBB0_34
## %bb.33:
	movq	_R600_D1GRPH_SWAP_CONTROL@GOTPCREL(%rip), %rax
	movq	8(%r15), %rdi
	addq	(%rax), %rdi
	movl	-52(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
LBB0_34:
	movq	_AVIVO_D1GRPH_SURFACE_OFFSET_X@GOTPCREL(%rip), %rax
	movq	8(%r15), %rdi
	addq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_AVIVO_D1GRPH_SURFACE_OFFSET_Y@GOTPCREL(%rip), %rax
	movq	8(%r15), %rdi
	addq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_AVIVO_D1GRPH_X_START@GOTPCREL(%rip), %rax
	movq	8(%r15), %rdi
	addq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_AVIVO_D1GRPH_Y_START@GOTPCREL(%rip), %rax
	movq	8(%r15), %rdi
	addq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_AVIVO_D1GRPH_X_END@GOTPCREL(%rip), %rax
	movq	8(%r15), %rdi
	addq	(%rax), %rdi
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	movl	4(%rbx), %esi
	callq	_WREG32
	movq	_AVIVO_D1GRPH_Y_END@GOTPCREL(%rip), %rax
	movq	8(%r15), %rdi
	addq	(%rax), %rdi
	movl	8(%rbx), %esi
	callq	_WREG32
	movq	16(%rbx), %rax
	movl	(%rbx), %ecx
	leal	7(%rcx), %esi
	testl	%ecx, %ecx
	cmovnsl	%ecx, %esi
	movl	(%rax), %eax
	sarl	$3, %esi
	cltd
	idivl	%esi
	movq	_AVIVO_D1GRPH_PITCH@GOTPCREL(%rip), %rcx
	movq	8(%r15), %rdi
	addq	(%rcx), %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	_AVIVO_D1GRPH_ENABLE@GOTPCREL(%rip), %rax
	movq	8(%r15), %rdi
	addq	(%rax), %rdi
	movl	$1, %esi
	callq	_WREG32
	movq	_AVIVO_D1MODE_DESKTOP_HEIGHT@GOTPCREL(%rip), %rax
	movq	8(%r15), %rdi
	addq	(%rax), %rdi
	movl	8(%rbx), %esi
	callq	_WREG32
	movq	_AVIVO_D1MODE_VIEWPORT_START@GOTPCREL(%rip), %rax
	movq	8(%r15), %rdi
	addq	(%rax), %rdi
	movl	-68(%rbp), %eax                 ## 4-byte Reload
	andl	$-2, %eax
	movl	-72(%rbp), %esi                 ## 4-byte Reload
	andl	$-4, %esi
	shll	$16, %esi
	orl	%eax, %esi
	callq	_WREG32
	movl	8(%r13), %esi
	movl	12(%r13), %eax
	incl	%eax
	andl	$-2, %eax
	movq	_AVIVO_D1MODE_VIEWPORT_SIZE@GOTPCREL(%rip), %rcx
	movq	8(%r15), %rdi
	addq	(%rcx), %rdi
	shll	$16, %esi
	orl	%eax, %esi
	callq	_WREG32
	movq	_AVIVO_D1GRPH_FLIP_CONTROL@GOTPCREL(%rip), %rbx
	movq	8(%r15), %rdi
	addq	(%rbx), %rdi
	callq	_RREG32
	movq	_AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	8(%r15), %rdi
	addq	(%rbx), %rdi
	callq	_WREG32
	movq	_AVIVO_D1MODE_MASTER_UPDATE_MODE@GOTPCREL(%rip), %rax
	movq	8(%r15), %rdi
	addq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	-88(%rbp), %rdi                 ## 8-byte Reload
	testq	%rdi, %rdi
	je	LBB0_39
## %bb.35:
	cmpl	$0, -56(%rbp)                   ## 4-byte Folded Reload
	jne	LBB0_39
## %bb.36:
	cmpq	%rdi, (%r13)
	je	LBB0_39
## %bb.37:
	movq	%r14, %r15
	callq	_to_radeon_framebuffer
	movq	(%rax), %rdi
	callq	_gem_to_radeon_bo
	movq	%rax, %r14
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	_radeon_bo_reserve
	movl	%eax, %ebx
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	callq	_unlikely
	testq	%rax, %rax
	jne	LBB0_41
## %bb.38:
	movq	%r14, %rdi
	callq	_radeon_bo_unpin
	movq	%r14, %rdi
	callq	_radeon_bo_unreserve
	movq	%r15, %r14
LBB0_39:
	movq	%r14, %rdi
	callq	_radeon_bandwidth_update
LBB0_40:
	xorl	%ebx, %ebx
LBB0_41:
	movl	%ebx, %eax
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_17, LBB0_17-LJTI0_0
.set L0_0_set_14, LBB0_14-LJTI0_0
.set L0_0_set_15, LBB0_15-LJTI0_0
.set L0_0_set_12, LBB0_12-LJTI0_0
.set L0_0_set_13, LBB0_13-LJTI0_0
LJTI0_0:
	.long	L0_0_set_17
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_15
	.long	L0_0_set_12
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_13
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_13
	.end_data_region
                                        ## -- End function
	.comm	_R600_D1GRPH_SWAP_ENDIAN_NONE,4,2 ## @R600_D1GRPH_SWAP_ENDIAN_NONE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"No FB bound\n"

	.comm	_RADEON_GEM_DOMAIN_VRAM,4,2     ## @RADEON_GEM_DOMAIN_VRAM
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_AVIVO_D1GRPH_CONTROL_DEPTH_8BPP,4,2 ## @AVIVO_D1GRPH_CONTROL_DEPTH_8BPP
	.comm	_AVIVO_D1GRPH_CONTROL_8BPP_INDEXED,4,2 ## @AVIVO_D1GRPH_CONTROL_8BPP_INDEXED
	.comm	_AVIVO_D1GRPH_CONTROL_DEPTH_16BPP,4,2 ## @AVIVO_D1GRPH_CONTROL_DEPTH_16BPP
	.comm	_AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555,4,2 ## @AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555
	.comm	_AVIVO_D1GRPH_CONTROL_16BPP_RGB565,4,2 ## @AVIVO_D1GRPH_CONTROL_16BPP_RGB565
	.comm	_AVIVO_D1GRPH_CONTROL_DEPTH_32BPP,4,2 ## @AVIVO_D1GRPH_CONTROL_DEPTH_32BPP
	.comm	_AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888,4,2 ## @AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888
L_.str.1:                               ## @.str.1
	.asciz	"Unsupported screen depth %d\n"

	.comm	_CHIP_R600,8,3                  ## @CHIP_R600
	.comm	_RADEON_TILING_MACRO,4,2        ## @RADEON_TILING_MACRO
	.comm	_R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1,4,2 ## @R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1
	.comm	_RADEON_TILING_MICRO,4,2        ## @RADEON_TILING_MICRO
	.comm	_R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1,4,2 ## @R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1
	.comm	_AVIVO_D1GRPH_MACRO_ADDRESS_MODE,4,2 ## @AVIVO_D1GRPH_MACRO_ADDRESS_MODE
	.comm	_AVIVO_D1GRPH_TILED,4,2         ## @AVIVO_D1GRPH_TILED
	.comm	_AVIVO_D1VGA_CONTROL,8,3        ## @AVIVO_D1VGA_CONTROL
	.comm	_AVIVO_D2VGA_CONTROL,8,3        ## @AVIVO_D2VGA_CONTROL
	.comm	_CHIP_RV770,8,3                 ## @CHIP_RV770
	.comm	_R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,8,3 ## @R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
	.comm	_R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,8,3 ## @R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
	.comm	_R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,8,3 ## @R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
	.comm	_R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,8,3 ## @R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
	.comm	_AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS,8,3 ## @AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS
	.comm	_AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS,8,3 ## @AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS
	.comm	_AVIVO_D1GRPH_CONTROL,8,3       ## @AVIVO_D1GRPH_CONTROL
	.comm	_R600_D1GRPH_SWAP_CONTROL,8,3   ## @R600_D1GRPH_SWAP_CONTROL
	.comm	_AVIVO_D1GRPH_SURFACE_OFFSET_X,8,3 ## @AVIVO_D1GRPH_SURFACE_OFFSET_X
	.comm	_AVIVO_D1GRPH_SURFACE_OFFSET_Y,8,3 ## @AVIVO_D1GRPH_SURFACE_OFFSET_Y
	.comm	_AVIVO_D1GRPH_X_START,8,3       ## @AVIVO_D1GRPH_X_START
	.comm	_AVIVO_D1GRPH_Y_START,8,3       ## @AVIVO_D1GRPH_Y_START
	.comm	_AVIVO_D1GRPH_X_END,8,3         ## @AVIVO_D1GRPH_X_END
	.comm	_AVIVO_D1GRPH_Y_END,8,3         ## @AVIVO_D1GRPH_Y_END
	.comm	_AVIVO_D1GRPH_PITCH,8,3         ## @AVIVO_D1GRPH_PITCH
	.comm	_AVIVO_D1GRPH_ENABLE,8,3        ## @AVIVO_D1GRPH_ENABLE
	.comm	_AVIVO_D1MODE_DESKTOP_HEIGHT,8,3 ## @AVIVO_D1MODE_DESKTOP_HEIGHT
	.comm	_AVIVO_D1MODE_VIEWPORT_START,8,3 ## @AVIVO_D1MODE_VIEWPORT_START
	.comm	_AVIVO_D1MODE_VIEWPORT_SIZE,8,3 ## @AVIVO_D1MODE_VIEWPORT_SIZE
	.comm	_AVIVO_D1GRPH_FLIP_CONTROL,8,3  ## @AVIVO_D1GRPH_FLIP_CONTROL
	.comm	_AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN,4,2 ## @AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN
	.comm	_AVIVO_D1MODE_MASTER_UPDATE_MODE,8,3 ## @AVIVO_D1MODE_MASTER_UPDATE_MODE
	.comm	_R600_D1GRPH_SWAP_ENDIAN_16BIT,4,2 ## @R600_D1GRPH_SWAP_ENDIAN_16BIT
	.comm	_R600_D1GRPH_SWAP_ENDIAN_32BIT,4,2 ## @R600_D1GRPH_SWAP_ENDIAN_32BIT
	.no_dead_strip	_avivo_crtc_do_set_base
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function avivo_crtc_do_set_base
_avivo_crtc_do_set_base:                ; @avivo_crtc_do_set_base
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #128
	.cfi_def_cfa_offset 128
	stp	x28, x27, [sp, #32]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #48]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #64]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #80]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #96]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #112]            ; 16-byte Folded Spill
	add	x29, sp, #112
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x4
	mov	x26, x3
	mov	x25, x2
	mov	x24, x1
	mov	x22, x0
	bl	_to_radeon_crtc
	mov	x23, x0
	ldr	x8, [x22, #16]
	ldr	x19, [x8]
Lloh0:
	adrp	x8, _R600_D1GRPH_SWAP_ENDIAN_NONE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _R600_D1GRPH_SWAP_ENDIAN_NONE@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cbz	w21, LBB0_2
; %bb.1:
	str	w8, [sp, #16]                   ; 4-byte Folded Spill
	mov	x0, x24
	bl	_to_radeon_framebuffer
	mov	x20, x24
	b	LBB0_4
LBB0_2:
	ldr	x0, [x22]
	cbz	x0, LBB0_10
; %bb.3:
	str	w8, [sp, #16]                   ; 4-byte Folded Spill
	bl	_to_radeon_framebuffer
	ldr	x20, [x22]
LBB0_4:
	ldr	x0, [x0]
	bl	_gem_to_radeon_bo
	mov	x27, x0
	mov	w1, #0
	bl	_radeon_bo_reserve
	mov	x28, x0
	cmp	w0, #0
	cset	w0, ne
	bl	_unlikely
	cbnz	x0, LBB0_37
; %bb.5:
	cbz	w21, LBB0_11
; %bb.6:
	mov	x0, x27
	bl	_radeon_bo_gpu_offset
	str	x0, [sp, #24]
LBB0_7:
	add	x1, sp, #20
	mov	x0, x27
	mov	x2, #0
	bl	_radeon_bo_get_tiling_flags
	mov	x0, x27
	bl	_radeon_bo_unreserve
	ldr	w1, [x20]
	sub	w10, w1, #8
	cmp	w10, #24
	b.hi	LBB0_13
; %bb.8:
Lloh3:
	adrp	x8, _AVIVO_D1GRPH_CONTROL_8BPP_INDEXED@GOTPAGE
Lloh4:
	ldr	x8, [x8, _AVIVO_D1GRPH_CONTROL_8BPP_INDEXED@GOTPAGEOFF]
Lloh5:
	adrp	x9, _AVIVO_D1GRPH_CONTROL_DEPTH_8BPP@GOTPAGE
Lloh6:
	ldr	x9, [x9, _AVIVO_D1GRPH_CONTROL_DEPTH_8BPP@GOTPAGEOFF]
Lloh7:
	adrp	x11, lJTI0_0@PAGE
Lloh8:
	add	x11, x11, lJTI0_0@PAGEOFF
	adr	x12, LBB0_9
	ldrb	w13, [x11, x10]
	add	x12, x12, x13, lsl #2
	br	x12
LBB0_9:
Lloh9:
	adrp	x8, _AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888@GOTPAGE
Lloh10:
	ldr	x8, [x8, _AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888@GOTPAGEOFF]
Lloh11:
	adrp	x9, _AVIVO_D1GRPH_CONTROL_DEPTH_32BPP@GOTPAGE
Lloh12:
	ldr	x9, [x9, _AVIVO_D1GRPH_CONTROL_DEPTH_32BPP@GOTPAGEOFF]
	b	LBB0_18
LBB0_10:
Lloh13:
	adrp	x0, l_.str@PAGE
Lloh14:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_KMS
	b	LBB0_36
LBB0_11:
Lloh15:
	adrp	x8, _RADEON_GEM_DOMAIN_VRAM@GOTPAGE
Lloh16:
	ldr	x8, [x8, _RADEON_GEM_DOMAIN_VRAM@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	add	x2, sp, #24
	mov	x0, x27
	bl	_radeon_bo_pin
	cmp	w0, #0
	cset	w0, ne
	bl	_unlikely
	cbz	x0, LBB0_7
; %bb.12:
	mov	x0, x27
	bl	_radeon_bo_unreserve
	b	LBB0_14
LBB0_13:
Lloh18:
	adrp	x0, l_.str.1@PAGE
Lloh19:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_ERROR
LBB0_14:
Lloh20:
	adrp	x8, _EINVAL@GOTPAGE
Lloh21:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
	neg	w28, w8
	b	LBB0_37
LBB0_15:
Lloh23:
	adrp	x8, _AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555@GOTPAGE
Lloh24:
	ldr	x8, [x8, _AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555@GOTPAGEOFF]
	b	LBB0_17
LBB0_16:
Lloh25:
	adrp	x8, _AVIVO_D1GRPH_CONTROL_16BPP_RGB565@GOTPAGE
Lloh26:
	ldr	x8, [x8, _AVIVO_D1GRPH_CONTROL_16BPP_RGB565@GOTPAGEOFF]
LBB0_17:
Lloh27:
	adrp	x9, _AVIVO_D1GRPH_CONTROL_DEPTH_16BPP@GOTPAGE
Lloh28:
	ldr	x9, [x9, _AVIVO_D1GRPH_CONTROL_DEPTH_16BPP@GOTPAGEOFF]
LBB0_18:
	ldr	w9, [x9]
	ldr	w8, [x8]
	orr	w27, w8, w9
	ldr	x10, [x19]
Lloh29:
	adrp	x28, _CHIP_R600@GOTPAGE
Lloh30:
	ldr	x28, [x28, _CHIP_R600@GOTPAGEOFF]
	ldr	x11, [x28]
	ldr	w8, [sp, #20]
Lloh31:
	adrp	x9, _RADEON_TILING_MACRO@GOTPAGE
Lloh32:
	ldr	x9, [x9, _RADEON_TILING_MACRO@GOTPAGEOFF]
Lloh33:
	ldr	w9, [x9]
	and	w9, w9, w8
	cmp	x10, x11
	b.ge	LBB0_21
; %bb.19:
Lloh34:
	adrp	x10, _AVIVO_D1GRPH_MACRO_ADDRESS_MODE@GOTPAGE
Lloh35:
	ldr	x10, [x10, _AVIVO_D1GRPH_MACRO_ADDRESS_MODE@GOTPAGEOFF]
Lloh36:
	ldr	w10, [x10]
	cmp	w9, #0
	csel	w9, wzr, w10, eq
	orr	w27, w9, w27
Lloh37:
	adrp	x9, _RADEON_TILING_MICRO@GOTPAGE
Lloh38:
	ldr	x9, [x9, _RADEON_TILING_MICRO@GOTPAGEOFF]
Lloh39:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_26
; %bb.20:
Lloh40:
	adrp	x8, _AVIVO_D1GRPH_TILED@GOTPAGE
Lloh41:
	ldr	x8, [x8, _AVIVO_D1GRPH_TILED@GOTPAGEOFF]
	b	LBB0_25
LBB0_21:
	cbz	w9, LBB0_23
; %bb.22:
Lloh42:
	adrp	x8, _R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1@GOTPAGE
Lloh43:
	ldr	x8, [x8, _R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1@GOTPAGEOFF]
	b	LBB0_25
LBB0_23:
Lloh44:
	adrp	x9, _RADEON_TILING_MICRO@GOTPAGE
Lloh45:
	ldr	x9, [x9, _RADEON_TILING_MICRO@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_26
; %bb.24:
Lloh47:
	adrp	x8, _R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1@GOTPAGE
Lloh48:
	ldr	x8, [x8, _R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1@GOTPAGEOFF]
LBB0_25:
	ldr	w8, [x8]
	orr	w27, w8, w27
LBB0_26:
Lloh49:
	adrp	x8, _AVIVO_D1VGA_CONTROL@GOTPAGE
Lloh50:
	ldr	x8, [x8, _AVIVO_D1VGA_CONTROL@GOTPAGEOFF]
	ldr	x9, [x23]
Lloh51:
	adrp	x10, _AVIVO_D2VGA_CONTROL@GOTPAGE
Lloh52:
	ldr	x10, [x10, _AVIVO_D2VGA_CONTROL@GOTPAGEOFF]
	cmp	x9, #0
	csel	x8, x8, x10, eq
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x19]
Lloh53:
	adrp	x9, _CHIP_RV770@GOTPAGE
Lloh54:
	ldr	x9, [x9, _CHIP_RV770@GOTPAGEOFF]
Lloh55:
	ldr	x9, [x9]
	cmp	x8, x9
	b.lt	LBB0_28
; %bb.27:
	ldr	x8, [x23]
Lloh56:
	adrp	x9, _R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH@GOTPAGE
Lloh57:
	ldr	x9, [x9, _R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH@GOTPAGEOFF]
	ldr	x0, [sp, #24]
Lloh58:
	adrp	x10, _R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH@GOTPAGE
Lloh59:
	ldr	x10, [x10, _R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH@GOTPAGEOFF]
	cmp	x8, #0
	csel	x8, x9, x10, eq
	ldr	x28, [x8]
Lloh60:
	adrp	x8, _R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH@GOTPAGE
Lloh61:
	ldr	x8, [x8, _R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH@GOTPAGEOFF]
Lloh62:
	adrp	x9, _R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH@GOTPAGE
Lloh63:
	ldr	x9, [x9, _R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH@GOTPAGEOFF]
	str	x20, [sp, #8]                   ; 8-byte Folded Spill
	mov	x20, x24
	mov	x24, x21
	mov	x21, x26
	mov	x26, x19
	mov	x19, x25
	csel	x25, x8, x9, eq
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x28
	bl	_WREG32
	ldr	x28, [x25]
	mov	x25, x19
	mov	x19, x26
	mov	x26, x21
	mov	x21, x24
	mov	x24, x20
	ldr	x20, [sp, #8]                   ; 8-byte Folded Reload
	ldr	x0, [sp, #24]
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x28
Lloh64:
	adrp	x28, _CHIP_R600@GOTPAGE
Lloh65:
	ldr	x28, [x28, _CHIP_R600@GOTPAGEOFF]
	bl	_WREG32
LBB0_28:
Lloh66:
	adrp	x8, _AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS@GOTPAGE
Lloh67:
	ldr	x8, [x8, _AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS@GOTPAGEOFF]
Lloh68:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	ldr	w1, [sp, #24]
	bl	_WREG32
Lloh69:
	adrp	x8, _AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS@GOTPAGE
Lloh70:
	ldr	x8, [x8, _AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS@GOTPAGEOFF]
Lloh71:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	ldr	w1, [sp, #24]
	bl	_WREG32
Lloh72:
	adrp	x8, _AVIVO_D1GRPH_CONTROL@GOTPAGE
Lloh73:
	ldr	x8, [x8, _AVIVO_D1GRPH_CONTROL@GOTPAGEOFF]
Lloh74:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	mov	x1, x27
	bl	_WREG32
	ldr	x8, [x19]
	ldr	x9, [x28]
	cmp	x8, x9
	b.lt	LBB0_30
; %bb.29:
Lloh75:
	adrp	x8, _R600_D1GRPH_SWAP_CONTROL@GOTPAGE
Lloh76:
	ldr	x8, [x8, _R600_D1GRPH_SWAP_CONTROL@GOTPAGEOFF]
Lloh77:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	ldr	w1, [sp, #16]                   ; 4-byte Folded Reload
	bl	_WREG32
LBB0_30:
Lloh78:
	adrp	x8, _AVIVO_D1GRPH_SURFACE_OFFSET_X@GOTPAGE
Lloh79:
	ldr	x8, [x8, _AVIVO_D1GRPH_SURFACE_OFFSET_X@GOTPAGEOFF]
Lloh80:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
Lloh81:
	adrp	x8, _AVIVO_D1GRPH_SURFACE_OFFSET_Y@GOTPAGE
Lloh82:
	ldr	x8, [x8, _AVIVO_D1GRPH_SURFACE_OFFSET_Y@GOTPAGEOFF]
Lloh83:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
Lloh84:
	adrp	x8, _AVIVO_D1GRPH_X_START@GOTPAGE
Lloh85:
	ldr	x8, [x8, _AVIVO_D1GRPH_X_START@GOTPAGEOFF]
Lloh86:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
Lloh87:
	adrp	x8, _AVIVO_D1GRPH_Y_START@GOTPAGE
Lloh88:
	ldr	x8, [x8, _AVIVO_D1GRPH_Y_START@GOTPAGEOFF]
Lloh89:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
Lloh90:
	adrp	x8, _AVIVO_D1GRPH_X_END@GOTPAGE
Lloh91:
	ldr	x8, [x8, _AVIVO_D1GRPH_X_END@GOTPAGEOFF]
Lloh92:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	ldr	w1, [x20, #4]
	bl	_WREG32
Lloh93:
	adrp	x8, _AVIVO_D1GRPH_Y_END@GOTPAGE
Lloh94:
	ldr	x8, [x8, _AVIVO_D1GRPH_Y_END@GOTPAGEOFF]
Lloh95:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	ldr	w1, [x20, #8]
	bl	_WREG32
	ldr	x8, [x20, #16]
	ldr	w8, [x8]
	ldr	w9, [x20]
	add	w10, w9, #7
	cmp	w9, #0
	csel	w9, w10, w9, lt
	asr	w9, w9, #3
	sdiv	w1, w8, w9
Lloh96:
	adrp	x8, _AVIVO_D1GRPH_PITCH@GOTPAGE
Lloh97:
	ldr	x8, [x8, _AVIVO_D1GRPH_PITCH@GOTPAGEOFF]
Lloh98:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	bl	_WREG32
Lloh99:
	adrp	x8, _AVIVO_D1GRPH_ENABLE@GOTPAGE
Lloh100:
	ldr	x8, [x8, _AVIVO_D1GRPH_ENABLE@GOTPAGEOFF]
Lloh101:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	mov	w1, #1
	bl	_WREG32
Lloh102:
	adrp	x8, _AVIVO_D1MODE_DESKTOP_HEIGHT@GOTPAGE
Lloh103:
	ldr	x8, [x8, _AVIVO_D1MODE_DESKTOP_HEIGHT@GOTPAGEOFF]
Lloh104:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	ldr	w1, [x20, #8]
	bl	_WREG32
	and	w8, w26, #0xfffffffe
Lloh105:
	adrp	x9, _AVIVO_D1MODE_VIEWPORT_START@GOTPAGE
Lloh106:
	ldr	x9, [x9, _AVIVO_D1MODE_VIEWPORT_START@GOTPAGEOFF]
Lloh107:
	ldr	x9, [x9]
	ldr	x10, [x23, #8]
	add	x0, x10, x9
	lsl	w9, w25, #16
	and	w9, w9, #0xfffc0000
	orr	w1, w9, w8
	bl	_WREG32
	ldp	w8, w9, [x22, #8]
	add	w9, w9, #1
	and	w9, w9, #0xfffffffe
Lloh108:
	adrp	x10, _AVIVO_D1MODE_VIEWPORT_SIZE@GOTPAGE
Lloh109:
	ldr	x10, [x10, _AVIVO_D1MODE_VIEWPORT_SIZE@GOTPAGEOFF]
Lloh110:
	ldr	x10, [x10]
	ldr	x11, [x23, #8]
	add	x0, x11, x10
	orr	w1, w9, w8, lsl #16
	bl	_WREG32
Lloh111:
	adrp	x20, _AVIVO_D1GRPH_FLIP_CONTROL@GOTPAGE
Lloh112:
	ldr	x20, [x20, _AVIVO_D1GRPH_FLIP_CONTROL@GOTPAGEOFF]
	ldr	x8, [x20]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	bl	_RREG32
Lloh113:
	adrp	x8, _AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN@GOTPAGE
Lloh114:
	ldr	x8, [x8, _AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN@GOTPAGEOFF]
Lloh115:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	x8, [x20]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	bl	_WREG32
Lloh116:
	adrp	x8, _AVIVO_D1MODE_MASTER_UPDATE_MODE@GOTPAGE
Lloh117:
	ldr	x8, [x8, _AVIVO_D1MODE_MASTER_UPDATE_MODE@GOTPAGEOFF]
Lloh118:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
	cbz	x24, LBB0_35
; %bb.31:
	cbnz	w21, LBB0_35
; %bb.32:
	ldr	x8, [x22]
	cmp	x8, x24
	b.eq	LBB0_35
; %bb.33:
	mov	x0, x24
	bl	_to_radeon_framebuffer
	ldr	x0, [x0]
	bl	_gem_to_radeon_bo
	mov	x20, x0
	mov	w1, #0
	bl	_radeon_bo_reserve
	mov	x28, x0
	cmp	w0, #0
	cset	w0, ne
	bl	_unlikely
	cbnz	x0, LBB0_37
; %bb.34:
	mov	x0, x20
	bl	_radeon_bo_unpin
	mov	x0, x20
	bl	_radeon_bo_unreserve
LBB0_35:
	mov	x0, x19
	bl	_radeon_bandwidth_update
LBB0_36:
	mov	w28, #0
LBB0_37:
	mov	x0, x28
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpAdd	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpAdd	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGot	Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh64, Lloh65
	.loh AdrpLdrGot	Lloh62, Lloh63
	.loh AdrpLdrGot	Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGot	Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGot	Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_18-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_15-LBB0_9)>>2
	.byte	(LBB0_16-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_9-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_9-LBB0_9)>>2
                                        ; -- End function
	.comm	_R600_D1GRPH_SWAP_ENDIAN_NONE,4,2 ; @R600_D1GRPH_SWAP_ENDIAN_NONE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"No FB bound\n"

	.comm	_RADEON_GEM_DOMAIN_VRAM,4,2     ; @RADEON_GEM_DOMAIN_VRAM
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_AVIVO_D1GRPH_CONTROL_DEPTH_8BPP,4,2 ; @AVIVO_D1GRPH_CONTROL_DEPTH_8BPP
	.comm	_AVIVO_D1GRPH_CONTROL_8BPP_INDEXED,4,2 ; @AVIVO_D1GRPH_CONTROL_8BPP_INDEXED
	.comm	_AVIVO_D1GRPH_CONTROL_DEPTH_16BPP,4,2 ; @AVIVO_D1GRPH_CONTROL_DEPTH_16BPP
	.comm	_AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555,4,2 ; @AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555
	.comm	_AVIVO_D1GRPH_CONTROL_16BPP_RGB565,4,2 ; @AVIVO_D1GRPH_CONTROL_16BPP_RGB565
	.comm	_AVIVO_D1GRPH_CONTROL_DEPTH_32BPP,4,2 ; @AVIVO_D1GRPH_CONTROL_DEPTH_32BPP
	.comm	_AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888,4,2 ; @AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888
l_.str.1:                               ; @.str.1
	.asciz	"Unsupported screen depth %d\n"

	.comm	_CHIP_R600,8,3                  ; @CHIP_R600
	.comm	_RADEON_TILING_MACRO,4,2        ; @RADEON_TILING_MACRO
	.comm	_R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1,4,2 ; @R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1
	.comm	_RADEON_TILING_MICRO,4,2        ; @RADEON_TILING_MICRO
	.comm	_R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1,4,2 ; @R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1
	.comm	_AVIVO_D1GRPH_MACRO_ADDRESS_MODE,4,2 ; @AVIVO_D1GRPH_MACRO_ADDRESS_MODE
	.comm	_AVIVO_D1GRPH_TILED,4,2         ; @AVIVO_D1GRPH_TILED
	.comm	_AVIVO_D1VGA_CONTROL,8,3        ; @AVIVO_D1VGA_CONTROL
	.comm	_AVIVO_D2VGA_CONTROL,8,3        ; @AVIVO_D2VGA_CONTROL
	.comm	_CHIP_RV770,8,3                 ; @CHIP_RV770
	.comm	_R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,8,3 ; @R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
	.comm	_R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,8,3 ; @R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
	.comm	_R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,8,3 ; @R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
	.comm	_R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,8,3 ; @R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
	.comm	_AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS,8,3 ; @AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS
	.comm	_AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS,8,3 ; @AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS
	.comm	_AVIVO_D1GRPH_CONTROL,8,3       ; @AVIVO_D1GRPH_CONTROL
	.comm	_R600_D1GRPH_SWAP_CONTROL,8,3   ; @R600_D1GRPH_SWAP_CONTROL
	.comm	_AVIVO_D1GRPH_SURFACE_OFFSET_X,8,3 ; @AVIVO_D1GRPH_SURFACE_OFFSET_X
	.comm	_AVIVO_D1GRPH_SURFACE_OFFSET_Y,8,3 ; @AVIVO_D1GRPH_SURFACE_OFFSET_Y
	.comm	_AVIVO_D1GRPH_X_START,8,3       ; @AVIVO_D1GRPH_X_START
	.comm	_AVIVO_D1GRPH_Y_START,8,3       ; @AVIVO_D1GRPH_Y_START
	.comm	_AVIVO_D1GRPH_X_END,8,3         ; @AVIVO_D1GRPH_X_END
	.comm	_AVIVO_D1GRPH_Y_END,8,3         ; @AVIVO_D1GRPH_Y_END
	.comm	_AVIVO_D1GRPH_PITCH,8,3         ; @AVIVO_D1GRPH_PITCH
	.comm	_AVIVO_D1GRPH_ENABLE,8,3        ; @AVIVO_D1GRPH_ENABLE
	.comm	_AVIVO_D1MODE_DESKTOP_HEIGHT,8,3 ; @AVIVO_D1MODE_DESKTOP_HEIGHT
	.comm	_AVIVO_D1MODE_VIEWPORT_START,8,3 ; @AVIVO_D1MODE_VIEWPORT_START
	.comm	_AVIVO_D1MODE_VIEWPORT_SIZE,8,3 ; @AVIVO_D1MODE_VIEWPORT_SIZE
	.comm	_AVIVO_D1GRPH_FLIP_CONTROL,8,3  ; @AVIVO_D1GRPH_FLIP_CONTROL
	.comm	_AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN,4,2 ; @AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN
	.comm	_AVIVO_D1MODE_MASTER_UPDATE_MODE,8,3 ; @AVIVO_D1MODE_MASTER_UPDATE_MODE
	.comm	_R600_D1GRPH_SWAP_ENDIAN_16BIT,4,2 ; @R600_D1GRPH_SWAP_ENDIAN_16BIT
	.comm	_R600_D1GRPH_SWAP_ENDIAN_32BIT,4,2 ; @R600_D1GRPH_SWAP_ENDIAN_32BIT
	.no_dead_strip	_avivo_crtc_do_set_base
.subsections_via_symbols
