	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function pre_xfer
_pre_xfer:                              ## @pre_xfer
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	callq	_i2c_get_adapdata
	movq	%rax, %rbx
	movq	96(%rax), %rax
	movq	(%rax), %r14
	cmpq	$0, 88(%rbx)
	je	LBB0_12
## %bb.1:
	movq	(%r14), %rax
	movq	_CHIP_R200@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_12
## %bb.2:
	movq	%r14, %rdi
	callq	_ASIC_IS_AVIVO
	testl	%eax, %eax
	jne	LBB0_12
## %bb.3:
	movq	(%r14), %rax
	movq	_CHIP_RV350@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_4
## %bb.5:
	movq	_CHIP_R300@GOTPCREL(%rip), %rdx
	movq	_CHIP_R350@GOTPCREL(%rip), %rdi
	movq	_RADEON_GPIO_DVI_DDC@GOTPCREL(%rip), %rsi
	movq	%rsi, %rcx
	cmpq	(%rdi), %rax
	je	LBB0_7
## %bb.6:
	movq	_RADEON_GPIO_CRT2_DDC@GOTPCREL(%rip), %rcx
LBB0_7:
	cmpq	(%rdx), %rax
	cmoveq	%rsi, %rcx
	jmp	LBB0_8
LBB0_4:
	movq	_RADEON_GPIO_MONID@GOTPCREL(%rip), %rcx
LBB0_8:
	movq	(%rcx), %r12
	leaq	8(%r14), %r15
	movq	%r15, %rdi
	callq	_mutex_lock
	movq	_RADEON_DVI_I2C_CNTL_0@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	_RADEON_I2C_SOFT_RST@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	cmpq	%r12, (%rbx)
	jne	LBB0_9
## %bb.10:
	movq	%rcx, %r12
	movq	_R200_SEL_DDC1@GOTPCREL(%rip), %rax
	jmp	LBB0_11
LBB0_9:
	movq	%rcx, %r12
	movq	_R200_SEL_DDC3@GOTPCREL(%rip), %rax
LBB0_11:
	movl	(%rax), %edi
	callq	_R200_DVI_I2C_PIN_SEL
	orl	%eax, %r13d
	movq	%r12, %rdi
	movl	%r13d, %esi
	callq	_WREG32
	movq	%r15, %rdi
	callq	_mutex_unlock
LBB0_12:
	movq	%r14, %rdi
	callq	_ASIC_IS_DCE3
	testq	%rax, %rax
	je	LBB0_15
## %bb.13:
	cmpq	$0, 88(%rbx)
	je	LBB0_15
## %bb.14:
	movq	8(%rbx), %rdi
	callq	_RREG32
	andl	$-65537, %eax                   ## imm = 0xFFFEFFFF
	movq	8(%rbx), %rdi
	movl	%eax, %esi
	callq	_WREG32
LBB0_15:
	movq	(%rbx), %rdi
	callq	_RREG32
	movl	16(%rbx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	(%rbx), %rdi
	callq	_WREG32
	movq	24(%rbx), %rdi
	callq	_RREG32
	movl	32(%rbx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	24(%rbx), %rdi
	callq	_WREG32
	movq	40(%rbx), %rdi
	callq	_RREG32
	movl	48(%rbx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	40(%rbx), %rdi
	callq	_WREG32
	movq	56(%rbx), %rdi
	callq	_RREG32
	movl	64(%rbx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	56(%rbx), %rdi
	callq	_WREG32
	movq	8(%rbx), %rdi
	callq	_RREG32
	orl	68(%rbx), %eax
	movq	8(%rbx), %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	8(%rbx), %rdi
	callq	_RREG32
	movq	72(%rbx), %rdi
	callq	_RREG32
	orl	80(%rbx), %eax
	movq	72(%rbx), %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	72(%rbx), %rdi
	callq	_RREG32
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CHIP_R200,8,3                  ## @CHIP_R200
	.comm	_CHIP_RV350,8,3                 ## @CHIP_RV350
	.comm	_RADEON_GPIO_MONID,8,3          ## @RADEON_GPIO_MONID
	.comm	_CHIP_R300,8,3                  ## @CHIP_R300
	.comm	_CHIP_R350,8,3                  ## @CHIP_R350
	.comm	_RADEON_GPIO_DVI_DDC,8,3        ## @RADEON_GPIO_DVI_DDC
	.comm	_RADEON_GPIO_CRT2_DDC,8,3       ## @RADEON_GPIO_CRT2_DDC
	.comm	_RADEON_DVI_I2C_CNTL_0,8,3      ## @RADEON_DVI_I2C_CNTL_0
	.comm	_RADEON_I2C_SOFT_RST,4,2        ## @RADEON_I2C_SOFT_RST
	.comm	_R200_SEL_DDC1,4,2              ## @R200_SEL_DDC1
	.comm	_R200_SEL_DDC3,4,2              ## @R200_SEL_DDC3
	.no_dead_strip	_pre_xfer
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function pre_xfer
_pre_xfer:                              ; @pre_xfer
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	bl	_i2c_get_adapdata
	mov	x19, x0
	ldp	x9, x8, [x0, #88]
	ldr	x20, [x8]
	cbz	x9, LBB0_7
; %bb.1:
	ldr	x8, [x20]
Lloh0:
	adrp	x9, _CHIP_R200@GOTPAGE
Lloh1:
	ldr	x9, [x9, _CHIP_R200@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	b.lt	LBB0_7
; %bb.2:
	mov	x0, x20
	bl	_ASIC_IS_AVIVO
	cbnz	w0, LBB0_7
; %bb.3:
	ldr	x8, [x20]
Lloh3:
	adrp	x9, _CHIP_RV350@GOTPAGE
Lloh4:
	ldr	x9, [x9, _CHIP_RV350@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_5
; %bb.4:
Lloh6:
	adrp	x9, _CHIP_R300@GOTPAGE
Lloh7:
	ldr	x9, [x9, _CHIP_R300@GOTPAGEOFF]
Lloh8:
	ldr	x9, [x9]
Lloh9:
	adrp	x10, _CHIP_R350@GOTPAGE
Lloh10:
	ldr	x10, [x10, _CHIP_R350@GOTPAGEOFF]
Lloh11:
	ldr	x10, [x10]
	cmp	x8, x10
	ccmp	x8, x9, #4, ne
Lloh12:
	adrp	x8, _RADEON_GPIO_CRT2_DDC@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RADEON_GPIO_CRT2_DDC@GOTPAGEOFF]
Lloh14:
	adrp	x9, _RADEON_GPIO_DVI_DDC@GOTPAGE
Lloh15:
	ldr	x9, [x9, _RADEON_GPIO_DVI_DDC@GOTPAGEOFF]
	csel	x8, x9, x8, eq
	b	LBB0_6
LBB0_5:
Lloh16:
	adrp	x8, _RADEON_GPIO_MONID@GOTPAGE
Lloh17:
	ldr	x8, [x8, _RADEON_GPIO_MONID@GOTPAGEOFF]
LBB0_6:
	ldr	x23, [x8]
	add	x21, x20, #8
	mov	x0, x21
	bl	_mutex_lock
Lloh18:
	adrp	x8, _RADEON_DVI_I2C_CNTL_0@GOTPAGE
Lloh19:
	ldr	x8, [x8, _RADEON_DVI_I2C_CNTL_0@GOTPAGEOFF]
	ldr	x9, [x19]
Lloh20:
	ldr	x22, [x8]
Lloh21:
	adrp	x8, _RADEON_I2C_SOFT_RST@GOTPAGE
Lloh22:
	ldr	x8, [x8, _RADEON_I2C_SOFT_RST@GOTPAGEOFF]
Lloh23:
	adrp	x10, _R200_SEL_DDC1@GOTPAGE
Lloh24:
	ldr	x10, [x10, _R200_SEL_DDC1@GOTPAGEOFF]
Lloh25:
	ldr	w24, [x8]
Lloh26:
	adrp	x8, _R200_SEL_DDC3@GOTPAGE
Lloh27:
	ldr	x8, [x8, _R200_SEL_DDC3@GOTPAGEOFF]
	cmp	x9, x23
	csel	x8, x10, x8, eq
	ldr	w0, [x8]
	bl	_R200_DVI_I2C_PIN_SEL
	orr	w1, w0, w24
	mov	x0, x22
	bl	_WREG32
	mov	x0, x21
	bl	_mutex_unlock
LBB0_7:
	mov	x0, x20
	bl	_ASIC_IS_DCE3
	cbz	x0, LBB0_10
; %bb.8:
	ldr	x8, [x19, #88]
	cbz	x8, LBB0_10
; %bb.9:
	ldr	x0, [x19, #8]
	bl	_RREG32
	and	w1, w0, #0xfffeffff
	ldr	x0, [x19, #8]
	bl	_WREG32
LBB0_10:
	ldr	x0, [x19]
	bl	_RREG32
	ldr	w8, [x19, #16]
	bic	w1, w0, w8
	ldr	x0, [x19]
	bl	_WREG32
	ldr	x0, [x19, #24]
	bl	_RREG32
	ldr	w8, [x19, #32]
	bic	w1, w0, w8
	ldr	x0, [x19, #24]
	bl	_WREG32
	ldr	x0, [x19, #40]
	bl	_RREG32
	ldr	w8, [x19, #48]
	bic	w1, w0, w8
	ldr	x0, [x19, #40]
	bl	_WREG32
	ldr	x0, [x19, #56]
	bl	_RREG32
	ldr	w8, [x19, #64]
	bic	w1, w0, w8
	ldr	x0, [x19, #56]
	bl	_WREG32
	ldr	x0, [x19, #8]
	bl	_RREG32
	ldr	w8, [x19, #68]
	orr	w1, w8, w0
	ldr	x0, [x19, #8]
	bl	_WREG32
	ldr	x0, [x19, #8]
	bl	_RREG32
	ldr	x0, [x19, #72]
	bl	_RREG32
	ldr	w8, [x19, #80]
	orr	w1, w8, w0
	ldr	x0, [x19, #72]
	bl	_WREG32
	ldr	x0, [x19, #72]
	bl	_RREG32
	mov	w0, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh25
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.cfi_endproc
                                        ; -- End function
	.comm	_CHIP_R200,8,3                  ; @CHIP_R200
	.comm	_CHIP_RV350,8,3                 ; @CHIP_RV350
	.comm	_RADEON_GPIO_MONID,8,3          ; @RADEON_GPIO_MONID
	.comm	_CHIP_R300,8,3                  ; @CHIP_R300
	.comm	_CHIP_R350,8,3                  ; @CHIP_R350
	.comm	_RADEON_GPIO_DVI_DDC,8,3        ; @RADEON_GPIO_DVI_DDC
	.comm	_RADEON_GPIO_CRT2_DDC,8,3       ; @RADEON_GPIO_CRT2_DDC
	.comm	_RADEON_DVI_I2C_CNTL_0,8,3      ; @RADEON_DVI_I2C_CNTL_0
	.comm	_RADEON_I2C_SOFT_RST,4,2        ; @RADEON_I2C_SOFT_RST
	.comm	_R200_SEL_DDC1,4,2              ; @R200_SEL_DDC1
	.comm	_R200_SEL_DDC3,4,2              ; @R200_SEL_DDC3
	.no_dead_strip	_pre_xfer
.subsections_via_symbols
