	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function atombios_adjust_pll
_atombios_adjust_pll:                   ## @atombios_adjust_pll
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$120, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r12
	movq	%rdi, %rbx
	callq	_to_radeon_crtc
	movq	%rax, %r15
	movq	(%rbx), %rax
	movq	(%rax), %r13
	movq	40(%r15), %rbx
	movq	%rbx, %rdi
	callq	_to_radeon_encoder
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movq	%rbx, %rdi
	callq	_radeon_get_connector_for_encoder
	movq	%rax, %r14
	movl	(%r12), %eax
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	movq	%rbx, %rdi
	callq	_atombios_get_encoder_mode
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movl	(%r12), %eax
	movl	%eax, -60(%rbp)                 ## 4-byte Spill
	movq	%r14, %rdi
	callq	_radeon_get_monitor_bpc
	movl	%eax, -76(%rbp)                 ## 4-byte Spill
	movl	(%r12), %esi
	movq	%rbx, -72(%rbp)                 ## 8-byte Spill
	movq	%rbx, %rdi
	movq	%r13, %rbx
	callq	_radeon_dig_monitor_is_duallink
	movl	%eax, -80(%rbp)                 ## 4-byte Spill
	leaq	4(%r15), %r13
	movq	%r15, -96(%rbp)                 ## 8-byte Spill
	movl	$0, 4(%r15)
	movq	%rbx, %rdi
	callq	_ASIC_IS_AVIVO
	testq	%rax, %rax
	je	LBB0_20
## %bb.1:
	movq	(%rbx), %rax
	movq	_CHIP_RS600@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_4
## %bb.2:
	movq	_CHIP_RS690@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_4
## %bb.3:
	movq	_CHIP_RS740@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_5
LBB0_4:
	movq	_RADEON_PLL_PREFER_CLOSEST_LOWER@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r13)
LBB0_5:
	movq	%rbx, %rdi
	callq	_ASIC_IS_DCE32
	testq	%rax, %rax
	je	LBB0_8
## %bb.6:
	cmpl	$200000, (%r12)                 ## imm = 0x30D40
	jle	LBB0_8
## %bb.7:
	movq	_RADEON_PLL_PREFER_HIGH_FB_DIV@GOTPCREL(%rip), %rcx
	jmp	LBB0_9
LBB0_8:
	movq	_RADEON_PLL_PREFER_LOW_REF_DIV@GOTPCREL(%rip), %rcx
LBB0_9:
	movl	(%r13), %eax
	orl	(%rcx), %eax
	movl	%eax, (%r13)
	movq	(%rbx), %rcx
	movq	_CHIP_RV770@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jge	LBB0_11
## %bb.10:
	movq	_RADEON_PLL_PREFER_MINM_OVER_MAXP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r13)
LBB0_11:
	movq	%rbx, %rdi
	callq	_ASIC_IS_DCE41
	testq	%rax, %rax
	jne	LBB0_13
## %bb.12:
	movq	%rbx, %rdi
	callq	_ASIC_IS_DCE61
	testq	%rax, %rax
	je	LBB0_14
LBB0_13:
	movq	_RADEON_PLL_USE_FRAC_FB_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r13)
LBB0_14:
	movq	(%rbx), %rax
	movq	_CHIP_RS780@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_16
## %bb.15:
	movq	_CHIP_RS880@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_17
LBB0_16:
	movq	_RADEON_PLL_USE_FRAC_FB_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r13)
LBB0_17:
	movq	%rbx, %rdi
	callq	_ASIC_IS_DCE32
	testq	%rax, %rax
	movq	-48(%rbp), %rdx                 ## 8-byte Reload
	je	LBB0_25
## %bb.18:
	cmpl	$165001, (%r12)                 ## imm = 0x28489
	jl	LBB0_25
## %bb.19:
	movq	_RADEON_PLL_USE_FRAC_FB_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	%r13, %rcx
	jmp	LBB0_24
LBB0_20:
	movq	_RADEON_PLL_LEGACY@GOTPCREL(%rip), %rdx
	movl	(%r13), %eax
	cmpl	$200001, (%r12)                 ## imm = 0x30D41
	jl	LBB0_21
## %bb.22:
	movq	_RADEON_PLL_PREFER_HIGH_FB_DIV@GOTPCREL(%rip), %rcx
	jmp	LBB0_23
LBB0_21:
	movq	_RADEON_PLL_PREFER_LOW_REF_DIV@GOTPCREL(%rip), %rcx
LBB0_23:
	orl	(%rdx), %eax
	movq	-48(%rbp), %rdx                 ## 8-byte Reload
LBB0_24:
	orl	(%rcx), %eax
	movl	%eax, (%r13)
LBB0_25:
	movq	_ATOM_DEVICE_LCD_SUPPORT@GOTPCREL(%rip), %r15
	movq	_ATOM_DEVICE_DFP_SUPPORT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	(%r15), %eax
	testl	%eax, (%rdx)
	je	LBB0_26
## %bb.29:
	testq	%r14, %r14
	jne	LBB0_30
	jmp	LBB0_31
LBB0_26:
	movq	-72(%rbp), %rdi                 ## 8-byte Reload
	callq	_radeon_encoder_get_dp_bridge_encoder_id
	movq	_ENCODER_OBJECT_ID_NONE@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_27
## %bb.28:
	testq	%r14, %r14
	movq	-48(%rbp), %rdx                 ## 8-byte Reload
	je	LBB0_31
LBB0_30:
	movq	%r14, %rdi
	callq	_to_radeon_connector
	movq	-48(%rbp), %rdx                 ## 8-byte Reload
	movq	(%rax), %rax
	movl	(%rax), %eax
	movl	%eax, -60(%rbp)                 ## 4-byte Spill
LBB0_31:
	movl	(%r15), %eax
	testl	%eax, (%rdx)
	movq	-96(%rbp), %r14                 ## 8-byte Reload
	je	LBB0_36
## %bb.32:
	cmpq	$0, 32(%r14)
	je	LBB0_36
## %bb.33:
	movq	24(%r14), %rax
	testq	%rax, %rax
	je	LBB0_36
## %bb.34:
	movq	_RADEON_PLL_USE_REF_DIV@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	%ecx, 4(%r14)
	movq	%rax, 8(%r14)
	movq	%rbx, %rdi
	callq	_ASIC_IS_AVIVO
	testq	%rax, %rax
	je	LBB0_36
## %bb.35:
	movq	_RADEON_PLL_USE_FRAC_FB_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r13)
LBB0_36:
	movq	%rbx, %rdi
	callq	_ASIC_IS_AVIVO
	testq	%rax, %rax
	je	LBB0_43
## %bb.37:
	movq	-48(%rbp), %rdx                 ## 8-byte Reload
	movq	8(%rdx), %rax
	movq	_ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_39
## %bb.38:
	movl	(%r12), %eax
	addl	%eax, %eax
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
LBB0_39:
	movq	_ATOM_DEVICE_TV_SUPPORT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 16(%rdx)
	je	LBB0_41
## %bb.40:
	movq	_RADEON_PLL_PREFER_CLOSEST_LOWER@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r13)
LBB0_41:
	movl	(%r15), %eax
	testl	%eax, (%rdx)
	je	LBB0_48
## %bb.42:
	movq	_RADEON_PLL_IS_LCD@GOTPCREL(%rip), %rax
	jmp	LBB0_47
LBB0_43:
	movq	-72(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rax
	movq	_DRM_MODE_ENCODER_DAC@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_45
## %bb.44:
	movq	_RADEON_PLL_NO_ODD_POST_DIV@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	%ecx, (%r13)
LBB0_45:
	movq	_DRM_MODE_ENCODER_LVDS@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_48
## %bb.46:
	movq	_RADEON_PLL_USE_REF_DIV@GOTPCREL(%rip), %rax
LBB0_47:
	movl	(%rax), %eax
	orl	%eax, (%r13)
LBB0_48:
	movq	%rbx, %rdi
	callq	_ASIC_IS_DCE3
	testq	%rax, %rax
	je	LBB0_78
## %bb.49:
	movq	_COMMAND@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_AdjustDisplayPll@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_GetIndexIntoMasterTable
	movl	%eax, %r13d
	movl	8(%rbx), %edi
	leaq	-88(%rbp), %rdx
	leaq	-84(%rbp), %rcx
	movl	%eax, %esi
	callq	_atom_parse_cmd_header
	testl	%eax, %eax
	je	LBB0_78
## %bb.50:
	leaq	-160(%rbp), %rdi
	xorl	%esi, %esi
	movl	$64, %edx
	callq	_memset
	movl	-88(%rbp), %esi
	movl	-84(%rbp), %edx
	cmpl	$1, %esi
	jne	LBB0_77
## %bb.51:
	leal	-1(%rdx), %eax
	cmpl	$2, %eax
	jae	LBB0_52
## %bb.58:
	movslq	(%r12), %rax
	imulq	$1717986919, %rax, %rdi         ## imm = 0x66666667
	movq	%rdi, %rax
	shrq	$63, %rax
	sarq	$34, %rdi
	addl	%eax, %edi
                                        ## kill: def $edi killed $edi killed $rdi
	callq	_cpu_to_le16
	movq	%rax, -144(%rbp)
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movq	8(%rax), %rax
	movq	%rax, -160(%rbp)
	movl	-52(%rbp), %eax                 ## 4-byte Reload
	movl	%eax, -152(%rbp)
	cmpq	$0, 32(%r14)
	je	LBB0_61
## %bb.59:
	cmpl	$0, 16(%r14)
	je	LBB0_61
## %bb.60:
	movq	_ADJUST_DISPLAY_CONFIG_SS_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, -136(%rbp)
LBB0_61:
	movl	8(%rbx), %edi
	leaq	-160(%rbp), %rdx
	movl	%r13d, %esi
	callq	_atom_execute_table
	movq	-144(%rbp), %rdi
	callq	_le16_to_cpu
                                        ## kill: def $eax killed $eax def $rax
	jmp	LBB0_76
LBB0_52:
	movl	$1, %esi
	cmpl	$3, %edx
	jne	LBB0_77
## %bb.53:
	movslq	(%r12), %rax
	imulq	$1717986919, %rax, %rdi         ## imm = 0x66666667
	movq	%rdi, %rax
	shrq	$63, %rax
	sarq	$34, %rdi
	addl	%eax, %edi
                                        ## kill: def $edi killed $edi killed $rdi
	callq	_cpu_to_le16
	movq	%rax, -104(%rbp)
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movq	8(%rax), %rax
	movq	%rax, -136(%rbp)
	movl	-52(%rbp), %edi                 ## 4-byte Reload
	movl	%edi, -128(%rbp)
	movl	$0, -112(%rbp)
	cmpq	$0, 32(%r14)
	je	LBB0_56
## %bb.54:
	cmpl	$0, 16(%r14)
	je	LBB0_56
## %bb.55:
	movq	_DISPPLL_CONFIG_SS_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -112(%rbp)
LBB0_56:
	callq	_ENCODER_MODE_IS_DP
	testl	%eax, %eax
	je	LBB0_62
## %bb.57:
	movq	_DISPPLL_CONFIG_COHERENT_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, -112(%rbp)
	movslq	-60(%rbp), %rax                 ## 4-byte Folded Reload
	imulq	$1717986919, %rax, %rdi         ## imm = 0x66666667
	movq	%rdi, %rax
	shrq	$63, %rax
	sarq	$34, %rdi
	addl	%eax, %edi
                                        ## kill: def $edi killed $edi killed $rdi
	callq	_cpu_to_le16
	movq	%rax, -104(%rbp)
LBB0_69:
	movq	-72(%rbp), %r15                 ## 8-byte Reload
	movq	%r15, %rdi
	callq	_radeon_encoder_get_dp_bridge_encoder_id
	movq	_ENCODER_OBJECT_ID_NONE@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_71
## %bb.70:
	xorl	%eax, %eax
	jmp	LBB0_72
LBB0_77:
	leaq	L_.str(%rip), %rdi
                                        ## kill: def $edx killed $edx killed $rdx
	callq	_DRM_ERROR
LBB0_78:
	movl	-56(%rbp), %eax                 ## 4-byte Reload
LBB0_79:
	addq	$120, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_27:
	movq	-48(%rbp), %rdx                 ## 8-byte Reload
	jmp	LBB0_31
LBB0_71:
	movq	%r15, %rdi
	callq	_radeon_encoder_get_dp_bridge_encoder_id
LBB0_72:
	movq	%rax, -120(%rbp)
	movl	8(%rbx), %edi
	leaq	-160(%rbp), %rdx
	movl	%r13d, %esi
	callq	_atom_execute_table
	movl	-144(%rbp), %edi
	callq	_le32_to_cpu
                                        ## kill: def $eax killed $eax def $rax
	cmpq	$0, -152(%rbp)
	je	LBB0_74
## %bb.73:
	movq	_RADEON_PLL_USE_FRAC_FB_DIV@GOTPCREL(%rip), %rcx
	movl	4(%r14), %edx
	orl	(%rcx), %edx
	movq	_RADEON_PLL_USE_REF_DIV@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movl	%edx, 4(%r14)
	movq	-152(%rbp), %rcx
	movq	%rcx, 8(%r14)
LBB0_74:
	movl	-160(%rbp), %ecx
	testl	%ecx, %ecx
	je	LBB0_76
## %bb.75:
	movq	_RADEON_PLL_USE_FRAC_FB_DIV@GOTPCREL(%rip), %rdx
	movl	4(%r14), %esi
	orl	(%rdx), %esi
	movq	_RADEON_PLL_USE_POST_DIV@GOTPCREL(%rip), %rdx
	orl	(%rdx), %esi
	movl	%esi, 4(%r14)
	movl	%ecx, (%r14)
LBB0_76:
	addl	%eax, %eax
	leal	(%rax,%rax,4), %eax
	jmp	LBB0_79
LBB0_62:
	movq	_ATOM_DEVICE_DFP_SUPPORT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	-48(%rbp), %rcx                 ## 8-byte Reload
	testl	%eax, (%rcx)
	je	LBB0_69
## %bb.63:
	movq	24(%rcx), %r14
	movq	_ATOM_ENCODER_MODE_HDMI@GOTPCREL(%rip), %rax
	movl	-52(%rbp), %ecx                 ## 4-byte Reload
	cmpl	(%rax), %ecx
	jne	LBB0_65
## %bb.64:
	movl	-76(%rbp), %eax                 ## 4-byte Reload
	imull	(%r12), %eax
	cltq
	imulq	$1717986919, %rax, %rdi         ## imm = 0x66666667
	movq	%rdi, %rax
	shrq	$63, %rax
	sarq	$37, %rdi
	addl	%eax, %edi
                                        ## kill: def $edi killed $edi killed $rdi
	callq	_cpu_to_le16
	movq	%rax, -104(%rbp)
LBB0_65:
	cmpl	$0, (%r14)
	je	LBB0_67
## %bb.66:
	movq	_DISPPLL_CONFIG_COHERENT_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, -112(%rbp)
LBB0_67:
	cmpl	$0, -80(%rbp)                   ## 4-byte Folded Reload
	movq	-96(%rbp), %r14                 ## 8-byte Reload
	je	LBB0_69
## %bb.68:
	movq	_DISPPLL_CONFIG_DUAL_LINK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, -112(%rbp)
	jmp	LBB0_69
	.cfi_endproc
                                        ## -- End function
	.comm	_CHIP_RS600,8,3                 ## @CHIP_RS600
	.comm	_CHIP_RS690,8,3                 ## @CHIP_RS690
	.comm	_CHIP_RS740,8,3                 ## @CHIP_RS740
	.comm	_RADEON_PLL_PREFER_CLOSEST_LOWER,4,2 ## @RADEON_PLL_PREFER_CLOSEST_LOWER
	.comm	_RADEON_PLL_PREFER_HIGH_FB_DIV,4,2 ## @RADEON_PLL_PREFER_HIGH_FB_DIV
	.comm	_RADEON_PLL_PREFER_LOW_REF_DIV,4,2 ## @RADEON_PLL_PREFER_LOW_REF_DIV
	.comm	_CHIP_RV770,8,3                 ## @CHIP_RV770
	.comm	_RADEON_PLL_PREFER_MINM_OVER_MAXP,4,2 ## @RADEON_PLL_PREFER_MINM_OVER_MAXP
	.comm	_RADEON_PLL_USE_FRAC_FB_DIV,4,2 ## @RADEON_PLL_USE_FRAC_FB_DIV
	.comm	_CHIP_RS780,8,3                 ## @CHIP_RS780
	.comm	_CHIP_RS880,8,3                 ## @CHIP_RS880
	.comm	_RADEON_PLL_LEGACY,4,2          ## @RADEON_PLL_LEGACY
	.comm	_ATOM_DEVICE_LCD_SUPPORT,4,2    ## @ATOM_DEVICE_LCD_SUPPORT
	.comm	_ATOM_DEVICE_DFP_SUPPORT,4,2    ## @ATOM_DEVICE_DFP_SUPPORT
	.comm	_ENCODER_OBJECT_ID_NONE,8,3     ## @ENCODER_OBJECT_ID_NONE
	.comm	_RADEON_PLL_USE_REF_DIV,4,2     ## @RADEON_PLL_USE_REF_DIV
	.comm	_ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1,8,3 ## @ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
	.comm	_ATOM_DEVICE_TV_SUPPORT,4,2     ## @ATOM_DEVICE_TV_SUPPORT
	.comm	_RADEON_PLL_IS_LCD,4,2          ## @RADEON_PLL_IS_LCD
	.comm	_DRM_MODE_ENCODER_DAC,8,3       ## @DRM_MODE_ENCODER_DAC
	.comm	_RADEON_PLL_NO_ODD_POST_DIV,4,2 ## @RADEON_PLL_NO_ODD_POST_DIV
	.comm	_DRM_MODE_ENCODER_LVDS,8,3      ## @DRM_MODE_ENCODER_LVDS
	.comm	_COMMAND,4,2                    ## @COMMAND
	.comm	_AdjustDisplayPll,4,2           ## @AdjustDisplayPll
	.comm	_ADJUST_DISPLAY_CONFIG_SS_ENABLE,4,2 ## @ADJUST_DISPLAY_CONFIG_SS_ENABLE
	.comm	_DISPPLL_CONFIG_SS_ENABLE,4,2   ## @DISPPLL_CONFIG_SS_ENABLE
	.comm	_DISPPLL_CONFIG_COHERENT_MODE,4,2 ## @DISPPLL_CONFIG_COHERENT_MODE
	.comm	_ATOM_ENCODER_MODE_HDMI,4,2     ## @ATOM_ENCODER_MODE_HDMI
	.comm	_DISPPLL_CONFIG_DUAL_LINK,4,2   ## @DISPPLL_CONFIG_DUAL_LINK
	.comm	_RADEON_PLL_USE_POST_DIV,4,2    ## @RADEON_PLL_USE_POST_DIV
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Unknown table version %d %d\n"

	.no_dead_strip	_atombios_adjust_pll
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function atombios_adjust_pll
_atombios_adjust_pll:                   ; @atombios_adjust_pll
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #192
	.cfi_def_cfa_offset 192
	stp	x28, x27, [sp, #96]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #112]            ; 16-byte Folded Spill
	stp	x24, x23, [sp, #128]            ; 16-byte Folded Spill
	stp	x22, x21, [sp, #144]            ; 16-byte Folded Spill
	stp	x20, x19, [sp, #160]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #176]            ; 16-byte Folded Spill
	add	x29, sp, #176
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x22, x1
	mov	x20, x0
	bl	_to_radeon_crtc
	mov	x26, x0
	ldr	x8, [x20]
	ldr	x20, [x8]
	ldr	x21, [x0, #40]
	mov	x0, x21
	bl	_to_radeon_encoder
	mov	x23, x0
	mov	x0, x21
	bl	_radeon_get_connector_for_encoder
	mov	x28, x0
	ldr	w27, [x22]
	mov	x0, x21
	bl	_atombios_get_encoder_mode
	ldr	w8, [x22]
	stp	w0, w8, [sp, #16]               ; 8-byte Folded Spill
	mov	x0, x28
	bl	_radeon_get_monitor_bpc
	str	w0, [sp, #8]                    ; 4-byte Folded Spill
	ldr	w1, [x22]
	mov	x0, x21
	bl	_radeon_dig_monitor_is_duallink
	str	w0, [sp, #12]                   ; 4-byte Folded Spill
	mov	x19, x26
	str	wzr, [x19, #4]!
	mov	x0, x20
	bl	_ASIC_IS_AVIVO
	cbz	x0, LBB0_18
; %bb.1:
	ldr	x8, [x20]
Lloh0:
	adrp	x9, _CHIP_RS600@GOTPAGE
Lloh1:
	ldr	x9, [x9, _CHIP_RS600@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
Lloh3:
	adrp	x10, _CHIP_RS690@GOTPAGE
Lloh4:
	ldr	x10, [x10, _CHIP_RS690@GOTPAGEOFF]
Lloh5:
	ldr	x10, [x10]
Lloh6:
	adrp	x11, _CHIP_RS740@GOTPAGE
Lloh7:
	ldr	x11, [x11, _CHIP_RS740@GOTPAGEOFF]
Lloh8:
	ldr	x11, [x11]
	cmp	x8, x9
	ccmp	x8, x10, #4, ne
	ccmp	x8, x11, #4, ne
	b.ne	LBB0_3
; %bb.2:
Lloh9:
	adrp	x8, _RADEON_PLL_PREFER_CLOSEST_LOWER@GOTPAGE
Lloh10:
	ldr	x8, [x8, _RADEON_PLL_PREFER_CLOSEST_LOWER@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_3:
	mov	x0, x20
	bl	_ASIC_IS_DCE32
	cbz	x0, LBB0_6
; %bb.4:
	ldr	w8, [x22]
	mov	w9, #3392
	movk	w9, #3, lsl #16
	cmp	w8, w9
	b.le	LBB0_6
; %bb.5:
Lloh12:
	adrp	x8, _RADEON_PLL_PREFER_HIGH_FB_DIV@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RADEON_PLL_PREFER_HIGH_FB_DIV@GOTPAGEOFF]
	b	LBB0_7
LBB0_6:
Lloh14:
	adrp	x8, _RADEON_PLL_PREFER_LOW_REF_DIV@GOTPAGE
Lloh15:
	ldr	x8, [x8, _RADEON_PLL_PREFER_LOW_REF_DIV@GOTPAGEOFF]
LBB0_7:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
	ldr	x9, [x20]
Lloh16:
	adrp	x10, _CHIP_RV770@GOTPAGE
Lloh17:
	ldr	x10, [x10, _CHIP_RV770@GOTPAGEOFF]
Lloh18:
	ldr	x10, [x10]
	cmp	x9, x10
	b.ge	LBB0_9
; %bb.8:
Lloh19:
	adrp	x9, _RADEON_PLL_PREFER_MINM_OVER_MAXP@GOTPAGE
Lloh20:
	ldr	x9, [x9, _RADEON_PLL_PREFER_MINM_OVER_MAXP@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_9:
	mov	x0, x20
	bl	_ASIC_IS_DCE41
Lloh22:
	adrp	x24, _RADEON_PLL_USE_FRAC_FB_DIV@GOTPAGE
Lloh23:
	ldr	x24, [x24, _RADEON_PLL_USE_FRAC_FB_DIV@GOTPAGEOFF]
	cbnz	x0, LBB0_11
; %bb.10:
	mov	x0, x20
	bl	_ASIC_IS_DCE61
	cbz	x0, LBB0_12
LBB0_11:
	ldr	w8, [x24]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_12:
	ldr	x8, [x20]
Lloh24:
	adrp	x9, _CHIP_RS780@GOTPAGE
Lloh25:
	ldr	x9, [x9, _CHIP_RS780@GOTPAGEOFF]
Lloh26:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_14
; %bb.13:
Lloh27:
	adrp	x9, _CHIP_RS880@GOTPAGE
Lloh28:
	ldr	x9, [x9, _CHIP_RS880@GOTPAGEOFF]
Lloh29:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_15
LBB0_14:
	ldr	w8, [x24]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_15:
	mov	x0, x20
	bl	_ASIC_IS_DCE32
	cbz	x0, LBB0_20
; %bb.16:
	ldr	w8, [x22]
	mov	w9, #33929
	movk	w9, #2, lsl #16
	cmp	w8, w9
	b.lt	LBB0_20
; %bb.17:
	ldr	w8, [x24]
	mov	x9, x19
	b	LBB0_19
LBB0_18:
Lloh30:
	adrp	x8, _RADEON_PLL_LEGACY@GOTPAGE
Lloh31:
	ldr	x8, [x8, _RADEON_PLL_LEGACY@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
Lloh33:
	adrp	x9, _RADEON_PLL_PREFER_LOW_REF_DIV@GOTPAGE
Lloh34:
	ldr	x9, [x9, _RADEON_PLL_PREFER_LOW_REF_DIV@GOTPAGEOFF]
	ldr	w10, [x22]
Lloh35:
	adrp	x11, _RADEON_PLL_PREFER_HIGH_FB_DIV@GOTPAGE
Lloh36:
	ldr	x11, [x11, _RADEON_PLL_PREFER_HIGH_FB_DIV@GOTPAGEOFF]
	mov	w12, #3392
	movk	w12, #3, lsl #16
	cmp	w10, w12
	csel	x9, x11, x9, gt
LBB0_19:
	ldr	w9, [x9]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_20:
	ldr	w8, [x23]
Lloh37:
	adrp	x24, _ATOM_DEVICE_LCD_SUPPORT@GOTPAGE
Lloh38:
	ldr	x24, [x24, _ATOM_DEVICE_LCD_SUPPORT@GOTPAGEOFF]
	ldr	w9, [x24]
Lloh39:
	adrp	x25, _ATOM_DEVICE_DFP_SUPPORT@GOTPAGE
Lloh40:
	ldr	x25, [x25, _ATOM_DEVICE_DFP_SUPPORT@GOTPAGEOFF]
	ldr	w10, [x25]
	orr	w9, w10, w9
	tst	w9, w8
	b.ne	LBB0_22
; %bb.21:
	mov	x0, x21
	bl	_radeon_encoder_get_dp_bridge_encoder_id
Lloh41:
	adrp	x8, _ENCODER_OBJECT_ID_NONE@GOTPAGE
Lloh42:
	ldr	x8, [x8, _ENCODER_OBJECT_ID_NONE@GOTPAGEOFF]
Lloh43:
	ldr	x8, [x8]
	cmp	x0, x8
	b.eq	LBB0_24
LBB0_22:
	cbz	x28, LBB0_24
; %bb.23:
	mov	x0, x28
	bl	_to_radeon_connector
	ldr	x8, [x0]
	ldr	w8, [x8]
	str	w8, [sp, #20]                   ; 4-byte Folded Spill
LBB0_24:
	ldr	w8, [x23]
	ldr	w9, [x24]
	tst	w9, w8
	b.eq	LBB0_29
; %bb.25:
	ldr	x8, [x26, #32]
	cbz	x8, LBB0_29
; %bb.26:
	ldr	x8, [x26, #24]
	cbz	x8, LBB0_29
; %bb.27:
Lloh44:
	adrp	x9, _RADEON_PLL_USE_REF_DIV@GOTPAGE
Lloh45:
	ldr	x9, [x9, _RADEON_PLL_USE_REF_DIV@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
	ldr	w10, [x26, #4]
	orr	w9, w10, w9
	str	w9, [x26, #4]
	str	x8, [x26, #8]
	mov	x0, x20
	bl	_ASIC_IS_AVIVO
	cbz	x0, LBB0_29
; %bb.28:
Lloh47:
	adrp	x8, _RADEON_PLL_USE_FRAC_FB_DIV@GOTPAGE
Lloh48:
	ldr	x8, [x8, _RADEON_PLL_USE_FRAC_FB_DIV@GOTPAGEOFF]
Lloh49:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_29:
	mov	x0, x20
	bl	_ASIC_IS_AVIVO
	cbz	x0, LBB0_36
; %bb.30:
	ldr	x8, [x23, #8]
Lloh50:
	adrp	x9, _ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1@GOTPAGE
Lloh51:
	ldr	x9, [x9, _ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1@GOTPAGEOFF]
Lloh52:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_32
; %bb.31:
	ldr	w8, [x22]
	lsl	w27, w8, #1
LBB0_32:
	ldr	w8, [x23, #16]
Lloh53:
	adrp	x9, _ATOM_DEVICE_TV_SUPPORT@GOTPAGE
Lloh54:
	ldr	x9, [x9, _ATOM_DEVICE_TV_SUPPORT@GOTPAGEOFF]
Lloh55:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_34
; %bb.33:
Lloh56:
	adrp	x8, _RADEON_PLL_PREFER_CLOSEST_LOWER@GOTPAGE
Lloh57:
	ldr	x8, [x8, _RADEON_PLL_PREFER_CLOSEST_LOWER@GOTPAGEOFF]
Lloh58:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_34:
	ldr	w8, [x23]
	ldr	w9, [x24]
	tst	w9, w8
	b.eq	LBB0_41
; %bb.35:
Lloh59:
	adrp	x8, _RADEON_PLL_IS_LCD@GOTPAGE
Lloh60:
	ldr	x8, [x8, _RADEON_PLL_IS_LCD@GOTPAGEOFF]
	b	LBB0_40
LBB0_36:
	ldr	x8, [x21]
Lloh61:
	adrp	x9, _DRM_MODE_ENCODER_DAC@GOTPAGE
Lloh62:
	ldr	x9, [x9, _DRM_MODE_ENCODER_DAC@GOTPAGEOFF]
Lloh63:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_38
; %bb.37:
Lloh64:
	adrp	x9, _RADEON_PLL_NO_ODD_POST_DIV@GOTPAGE
Lloh65:
	ldr	x9, [x9, _RADEON_PLL_NO_ODD_POST_DIV@GOTPAGEOFF]
Lloh66:
	ldr	w9, [x9]
	ldr	w10, [x19]
	orr	w9, w10, w9
	str	w9, [x19]
LBB0_38:
Lloh67:
	adrp	x9, _DRM_MODE_ENCODER_LVDS@GOTPAGE
Lloh68:
	ldr	x9, [x9, _DRM_MODE_ENCODER_LVDS@GOTPAGEOFF]
Lloh69:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_41
; %bb.39:
Lloh70:
	adrp	x8, _RADEON_PLL_USE_REF_DIV@GOTPAGE
Lloh71:
	ldr	x8, [x8, _RADEON_PLL_USE_REF_DIV@GOTPAGEOFF]
LBB0_40:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_41:
	mov	x0, x20
	bl	_ASIC_IS_DCE3
	cbz	x0, LBB0_65
; %bb.42:
Lloh72:
	adrp	x8, _COMMAND@GOTPAGE
Lloh73:
	ldr	x8, [x8, _COMMAND@GOTPAGEOFF]
Lloh74:
	ldr	w0, [x8]
Lloh75:
	adrp	x8, _AdjustDisplayPll@GOTPAGE
Lloh76:
	ldr	x8, [x8, _AdjustDisplayPll@GOTPAGEOFF]
Lloh77:
	ldr	w1, [x8]
	bl	_GetIndexIntoMasterTable
	mov	x28, x0
	ldr	w0, [x20, #8]
	add	x2, sp, #28
	add	x3, sp, #24
	mov	x1, x28
	bl	_atom_parse_cmd_header
	cbz	w0, LBB0_65
; %bb.43:
	add	x0, sp, #32
	mov	w1, #0
	mov	w2, #64
	bl	_memset
	ldp	w2, w1, [sp, #24]
	cmp	w1, #1
	b.ne	LBB0_58
; %bb.44:
	sub	w8, w2, #1
	cmp	w8, #2
	b.hs	LBB0_49
; %bb.45:
	ldrsw	x8, [x22]
	mov	w9, #26215
	movk	w9, #26214, lsl #16
	mul	x8, x8, x9
	lsr	x9, x8, #32
	lsr	x8, x8, #63
	add	w0, w8, w9, asr #2
	bl	_cpu_to_le16
	str	x0, [sp, #48]
	ldr	x8, [x23, #8]
	str	x8, [sp, #32]
	ldr	w8, [sp, #16]                   ; 4-byte Folded Reload
	str	w8, [sp, #40]
	ldr	x8, [x26, #32]
	cbz	x8, LBB0_48
; %bb.46:
	ldr	w8, [x26, #16]
	cbz	w8, LBB0_48
; %bb.47:
Lloh78:
	adrp	x8, _ADJUST_DISPLAY_CONFIG_SS_ENABLE@GOTPAGE
Lloh79:
	ldr	x8, [x8, _ADJUST_DISPLAY_CONFIG_SS_ENABLE@GOTPAGEOFF]
Lloh80:
	ldr	w8, [x8]
	ldr	w9, [sp, #56]
	orr	w8, w9, w8
	str	w8, [sp, #56]
LBB0_48:
	ldr	w0, [x20, #8]
	add	x2, sp, #32
	mov	x1, x28
	bl	_atom_execute_table
	ldr	x0, [sp, #48]
	bl	_le16_to_cpu
	b	LBB0_64
LBB0_49:
	cmp	w2, #3
	b.ne	LBB0_57
; %bb.50:
	ldrsw	x8, [x22]
	mov	w9, #26215
	movk	w9, #26214, lsl #16
	mul	x8, x8, x9
	lsr	x9, x8, #32
	lsr	x8, x8, #63
	add	w0, w8, w9, asr #2
	bl	_cpu_to_le16
	str	x0, [sp, #88]
	ldr	x8, [x23, #8]
	str	x8, [sp, #56]
	ldr	w24, [sp, #16]                  ; 4-byte Folded Reload
	str	w24, [sp, #64]
	str	wzr, [sp, #80]
	ldr	x8, [x26, #32]
	cbz	x8, LBB0_53
; %bb.51:
	ldr	w8, [x26, #16]
	cbz	w8, LBB0_53
; %bb.52:
Lloh81:
	adrp	x8, _DISPPLL_CONFIG_SS_ENABLE@GOTPAGE
Lloh82:
	ldr	x8, [x8, _DISPPLL_CONFIG_SS_ENABLE@GOTPAGEOFF]
Lloh83:
	ldr	w8, [x8]
	str	w8, [sp, #80]
LBB0_53:
	mov	x0, x24
	bl	_ENCODER_MODE_IS_DP
	cbz	w0, LBB0_66
; %bb.54:
Lloh84:
	adrp	x8, _DISPPLL_CONFIG_COHERENT_MODE@GOTPAGE
Lloh85:
	ldr	x8, [x8, _DISPPLL_CONFIG_COHERENT_MODE@GOTPAGEOFF]
Lloh86:
	ldr	w8, [x8]
	ldr	w9, [sp, #80]
	orr	w8, w9, w8
	str	w8, [sp, #80]
	mov	w8, #26215
	movk	w8, #26214, lsl #16
	ldr	w9, [sp, #20]                   ; 4-byte Folded Reload
	smull	x8, w9, w8
	lsr	x9, x8, #63
	asr	x8, x8, #34
	add	w0, w8, w9
	bl	_cpu_to_le16
	str	x0, [sp, #88]
LBB0_55:
	mov	x0, x21
	bl	_radeon_encoder_get_dp_bridge_encoder_id
Lloh87:
	adrp	x8, _ENCODER_OBJECT_ID_NONE@GOTPAGE
Lloh88:
	ldr	x8, [x8, _ENCODER_OBJECT_ID_NONE@GOTPAGEOFF]
Lloh89:
	ldr	x8, [x8]
	cmp	x0, x8
	b.ne	LBB0_59
; %bb.56:
	mov	x0, #0
	b	LBB0_60
LBB0_57:
	mov	w1, #1
LBB0_58:
Lloh90:
	adrp	x0, l_.str@PAGE
Lloh91:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_ERROR
	b	LBB0_65
LBB0_59:
	mov	x0, x21
	bl	_radeon_encoder_get_dp_bridge_encoder_id
LBB0_60:
	str	x0, [sp, #72]
	ldr	w0, [x20, #8]
	add	x2, sp, #32
	mov	x1, x28
	bl	_atom_execute_table
	ldr	w0, [sp, #48]
	bl	_le32_to_cpu
	ldr	x8, [sp, #40]
	cbz	x8, LBB0_62
; %bb.61:
Lloh92:
	adrp	x8, _RADEON_PLL_USE_FRAC_FB_DIV@GOTPAGE
Lloh93:
	ldr	x8, [x8, _RADEON_PLL_USE_FRAC_FB_DIV@GOTPAGEOFF]
Lloh94:
	ldr	w8, [x8]
	ldr	w9, [x26, #4]
Lloh95:
	adrp	x10, _RADEON_PLL_USE_REF_DIV@GOTPAGE
Lloh96:
	ldr	x10, [x10, _RADEON_PLL_USE_REF_DIV@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh97:
	ldr	w9, [x10]
	orr	w8, w9, w8
	str	w8, [x26, #4]
	ldr	x8, [sp, #40]
	str	x8, [x26, #8]
LBB0_62:
	ldr	w8, [sp, #32]
	cbz	w8, LBB0_64
; %bb.63:
Lloh98:
	adrp	x9, _RADEON_PLL_USE_FRAC_FB_DIV@GOTPAGE
Lloh99:
	ldr	x9, [x9, _RADEON_PLL_USE_FRAC_FB_DIV@GOTPAGEOFF]
Lloh100:
	ldr	w9, [x9]
	ldr	w10, [x26, #4]
	orr	w9, w10, w9
Lloh101:
	adrp	x10, _RADEON_PLL_USE_POST_DIV@GOTPAGE
Lloh102:
	ldr	x10, [x10, _RADEON_PLL_USE_POST_DIV@GOTPAGEOFF]
Lloh103:
	ldr	w10, [x10]
	orr	w9, w10, w9
	stp	w8, w9, [x26]
LBB0_64:
	add	w8, w0, w0, lsl #2
	lsl	w27, w8, #1
LBB0_65:
	mov	x0, x27
	ldp	x29, x30, [sp, #176]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #160]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #144]            ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #128]            ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #112]            ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #96]             ; 16-byte Folded Reload
	add	sp, sp, #192
	ret
LBB0_66:
	ldr	w8, [x23]
	ldr	w9, [x25]
	tst	w9, w8
	b.eq	LBB0_55
; %bb.67:
	ldr	x19, [x23, #24]
Lloh104:
	adrp	x8, _ATOM_ENCODER_MODE_HDMI@GOTPAGE
Lloh105:
	ldr	x8, [x8, _ATOM_ENCODER_MODE_HDMI@GOTPAGEOFF]
Lloh106:
	ldr	w8, [x8]
	cmp	w24, w8
	b.ne	LBB0_69
; %bb.68:
	ldr	w8, [x22]
	ldr	w9, [sp, #8]                    ; 4-byte Folded Reload
	mul	w8, w8, w9
	mov	w9, #26215
	movk	w9, #26214, lsl #16
	smull	x8, w8, w9
	lsr	x9, x8, #63
	asr	x8, x8, #37
	add	w0, w8, w9
	bl	_cpu_to_le16
	str	x0, [sp, #88]
LBB0_69:
	ldr	w8, [x19]
	cbz	w8, LBB0_71
; %bb.70:
Lloh107:
	adrp	x8, _DISPPLL_CONFIG_COHERENT_MODE@GOTPAGE
Lloh108:
	ldr	x8, [x8, _DISPPLL_CONFIG_COHERENT_MODE@GOTPAGEOFF]
Lloh109:
	ldr	w8, [x8]
	ldr	w9, [sp, #80]
	orr	w8, w9, w8
	str	w8, [sp, #80]
LBB0_71:
	ldr	w8, [sp, #12]                   ; 4-byte Folded Reload
	cbz	w8, LBB0_55
; %bb.72:
Lloh110:
	adrp	x8, _DISPPLL_CONFIG_DUAL_LINK@GOTPAGE
Lloh111:
	ldr	x8, [x8, _DISPPLL_CONFIG_DUAL_LINK@GOTPAGEOFF]
Lloh112:
	ldr	w8, [x8]
	ldr	w9, [sp, #80]
	orr	w8, w9, w8
	str	w8, [sp, #80]
	b	LBB0_55
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGot	Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGot	Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpAdd	Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.cfi_endproc
                                        ; -- End function
	.comm	_CHIP_RS600,8,3                 ; @CHIP_RS600
	.comm	_CHIP_RS690,8,3                 ; @CHIP_RS690
	.comm	_CHIP_RS740,8,3                 ; @CHIP_RS740
	.comm	_RADEON_PLL_PREFER_CLOSEST_LOWER,4,2 ; @RADEON_PLL_PREFER_CLOSEST_LOWER
	.comm	_RADEON_PLL_PREFER_HIGH_FB_DIV,4,2 ; @RADEON_PLL_PREFER_HIGH_FB_DIV
	.comm	_RADEON_PLL_PREFER_LOW_REF_DIV,4,2 ; @RADEON_PLL_PREFER_LOW_REF_DIV
	.comm	_CHIP_RV770,8,3                 ; @CHIP_RV770
	.comm	_RADEON_PLL_PREFER_MINM_OVER_MAXP,4,2 ; @RADEON_PLL_PREFER_MINM_OVER_MAXP
	.comm	_RADEON_PLL_USE_FRAC_FB_DIV,4,2 ; @RADEON_PLL_USE_FRAC_FB_DIV
	.comm	_CHIP_RS780,8,3                 ; @CHIP_RS780
	.comm	_CHIP_RS880,8,3                 ; @CHIP_RS880
	.comm	_RADEON_PLL_LEGACY,4,2          ; @RADEON_PLL_LEGACY
	.comm	_ATOM_DEVICE_LCD_SUPPORT,4,2    ; @ATOM_DEVICE_LCD_SUPPORT
	.comm	_ATOM_DEVICE_DFP_SUPPORT,4,2    ; @ATOM_DEVICE_DFP_SUPPORT
	.comm	_ENCODER_OBJECT_ID_NONE,8,3     ; @ENCODER_OBJECT_ID_NONE
	.comm	_RADEON_PLL_USE_REF_DIV,4,2     ; @RADEON_PLL_USE_REF_DIV
	.comm	_ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1,8,3 ; @ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
	.comm	_ATOM_DEVICE_TV_SUPPORT,4,2     ; @ATOM_DEVICE_TV_SUPPORT
	.comm	_RADEON_PLL_IS_LCD,4,2          ; @RADEON_PLL_IS_LCD
	.comm	_DRM_MODE_ENCODER_DAC,8,3       ; @DRM_MODE_ENCODER_DAC
	.comm	_RADEON_PLL_NO_ODD_POST_DIV,4,2 ; @RADEON_PLL_NO_ODD_POST_DIV
	.comm	_DRM_MODE_ENCODER_LVDS,8,3      ; @DRM_MODE_ENCODER_LVDS
	.comm	_COMMAND,4,2                    ; @COMMAND
	.comm	_AdjustDisplayPll,4,2           ; @AdjustDisplayPll
	.comm	_ADJUST_DISPLAY_CONFIG_SS_ENABLE,4,2 ; @ADJUST_DISPLAY_CONFIG_SS_ENABLE
	.comm	_DISPPLL_CONFIG_SS_ENABLE,4,2   ; @DISPPLL_CONFIG_SS_ENABLE
	.comm	_DISPPLL_CONFIG_COHERENT_MODE,4,2 ; @DISPPLL_CONFIG_COHERENT_MODE
	.comm	_ATOM_ENCODER_MODE_HDMI,4,2     ; @ATOM_ENCODER_MODE_HDMI
	.comm	_DISPPLL_CONFIG_DUAL_LINK,4,2   ; @DISPPLL_CONFIG_DUAL_LINK
	.comm	_RADEON_PLL_USE_POST_DIV,4,2    ; @RADEON_PLL_USE_POST_DIV
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Unknown table version %d %d\n"

	.no_dead_strip	_atombios_adjust_pll
.subsections_via_symbols
