	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function emulate_sysexit
_emulate_sysexit:                       ## @emulate_sysexit
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	(%rdi), %rax
	movq	_X86EMUL_MODE_REAL@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_2
## %bb.1:
	movq	_X86EMUL_MODE_VM86@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_2
## %bb.3:
	leaq	-48(%rbp), %rsi
	leaq	-64(%rbp), %rdx
	movq	%rbx, %rdi
	callq	_setup_syscalls_segments
	movb	16(%rbx), %r15b
	movl	$3, -48(%rbp)
	movl	$3, -64(%rbp)
	movq	_kvm_x86_ops@GOTPCREL(%rip), %r14
	movq	(%r14), %rax
	movq	8(%rbx), %rdi
	movq	_MSR_IA32_SYSENTER_CS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	leaq	-28(%rbp), %rdx
	callq	*8(%rax)
	movl	-28(%rbp), %eax
	testb	$8, %r15b
	jne	LBB0_7
## %bb.4:
	leal	16(%rax), %ecx
	movl	%ecx, -44(%rbp)
	testl	$65532, %eax                    ## imm = 0xFFFC
	je	LBB0_5
## %bb.6:
	addl	$24, %eax
	jmp	LBB0_9
LBB0_2:
	movq	8(%rbx), %rdi
	xorl	%esi, %esi
	callq	_kvm_inject_gp
	movq	_X86EMUL_UNHANDLEABLE@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_7:
	leal	32(%rax), %ecx
	movl	%ecx, -44(%rbp)
	testl	%eax, %eax
	je	LBB0_5
## %bb.8:
	addl	$40, %eax
	movq	$1, -40(%rbp)
LBB0_9:
	movq	_SELECTOR_RPL_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	%edx, %ecx
	movl	%ecx, -44(%rbp)
	orl	%edx, %eax
	movl	%eax, -60(%rbp)
	movq	(%r14), %rax
	movq	8(%rbx), %rdi
	movq	_VCPU_SREG_CS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	leaq	-48(%rbp), %rsi
	callq	*(%rax)
	movq	(%r14), %rax
	movq	8(%rbx), %rdi
	movq	_VCPU_SREG_SS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	leaq	-64(%rbp), %rsi
	callq	*(%rax)
	movq	8(%rbx), %rax
	movq	24(%rbx), %rcx
	movq	(%rax), %rax
	movq	_VCPU_REGS_RDX@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdx
	movl	(%rax,%rdx,4), %edx
	movl	%edx, 32(%rbx)
	movq	_VCPU_REGS_RCX@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdx
	movl	(%rax,%rdx,4), %eax
	movq	_VCPU_REGS_RSP@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdx
	movl	%eax, (%rcx,%rdx,4)
	movq	_X86EMUL_CONTINUE@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_5:
	movq	8(%rbx), %rdi
	xorl	%esi, %esi
	callq	_kvm_inject_gp
	movq	_X86EMUL_PROPAGATE_FAULT@GOTPCREL(%rip), %rax
LBB0_10:
	movl	(%rax), %eax
	addq	$40, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_X86EMUL_MODE_REAL,8,3          ## @X86EMUL_MODE_REAL
	.comm	_X86EMUL_MODE_VM86,8,3          ## @X86EMUL_MODE_VM86
	.comm	_X86EMUL_UNHANDLEABLE,4,2       ## @X86EMUL_UNHANDLEABLE
	.comm	_kvm_x86_ops,8,3                ## @kvm_x86_ops
	.comm	_MSR_IA32_SYSENTER_CS,4,2       ## @MSR_IA32_SYSENTER_CS
	.comm	_X86EMUL_PROPAGATE_FAULT,4,2    ## @X86EMUL_PROPAGATE_FAULT
	.comm	_SELECTOR_RPL_MASK,4,2          ## @SELECTOR_RPL_MASK
	.comm	_VCPU_SREG_CS,4,2               ## @VCPU_SREG_CS
	.comm	_VCPU_SREG_SS,4,2               ## @VCPU_SREG_SS
	.comm	_VCPU_REGS_RDX,8,3              ## @VCPU_REGS_RDX
	.comm	_VCPU_REGS_RCX,8,3              ## @VCPU_REGS_RCX
	.comm	_VCPU_REGS_RSP,8,3              ## @VCPU_REGS_RSP
	.comm	_X86EMUL_CONTINUE,4,2           ## @X86EMUL_CONTINUE
	.no_dead_strip	_emulate_sysexit
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3                               ; -- Begin function emulate_sysexit
lCPI0_0:
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	2
_emulate_sysexit:                       ; @emulate_sysexit
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x8, [x0]
Lloh0:
	adrp	x9, _X86EMUL_MODE_REAL@GOTPAGE
Lloh1:
	ldr	x9, [x9, _X86EMUL_MODE_REAL@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
Lloh3:
	adrp	x10, _X86EMUL_MODE_VM86@GOTPAGE
Lloh4:
	ldr	x10, [x10, _X86EMUL_MODE_VM86@GOTPAGEOFF]
Lloh5:
	ldr	x10, [x10]
	cmp	x8, x9
	ccmp	x8, x10, #4, ne
	b.ne	LBB0_2
; %bb.1:
	ldr	x0, [x19, #8]
	mov	w1, #0
	bl	_kvm_inject_gp
Lloh6:
	adrp	x8, _X86EMUL_UNHANDLEABLE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _X86EMUL_UNHANDLEABLE@GOTPAGEOFF]
	b	LBB0_9
LBB0_2:
	add	x1, sp, #32
	add	x2, sp, #16
	mov	x0, x19
	bl	_setup_syscalls_segments
	ldr	w21, [x19, #16]
	mov	w8, #3
	str	w8, [sp, #32]
	str	w8, [sp, #16]
Lloh8:
	adrp	x20, _kvm_x86_ops@GOTPAGE
Lloh9:
	ldr	x20, [x20, _kvm_x86_ops@GOTPAGEOFF]
	ldr	x8, [x20]
	ldr	x8, [x8, #8]
	ldr	x0, [x19, #8]
Lloh10:
	adrp	x9, _MSR_IA32_SYSENTER_CS@GOTPAGE
Lloh11:
	ldr	x9, [x9, _MSR_IA32_SYSENTER_CS@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x9]
	add	x2, sp, #12
	blr	x8
	ldr	w9, [sp, #12]
	tbnz	w21, #3, LBB0_5
; %bb.3:
	add	w8, w9, #16
	str	w8, [sp, #36]
	tst	w9, #0xfffc
	b.eq	LBB0_8
; %bb.4:
	add	w9, w9, #24
	b	LBB0_7
LBB0_5:
	add	w8, w9, #32
	str	w8, [sp, #36]
	cbz	w9, LBB0_8
; %bb.6:
	add	w9, w9, #40
Lloh13:
	adrp	x10, lCPI0_0@PAGE
Lloh14:
	ldr	d0, [x10, lCPI0_0@PAGEOFF]
	str	d0, [sp, #40]
LBB0_7:
Lloh15:
	adrp	x10, _SELECTOR_RPL_MASK@GOTPAGE
Lloh16:
	ldr	x10, [x10, _SELECTOR_RPL_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w10, [x10]
	orr	w8, w8, w10
	str	w8, [sp, #36]
	orr	w8, w9, w10
	str	w8, [sp, #20]
	ldr	x8, [x20]
	ldr	x8, [x8]
	ldr	x0, [x19, #8]
Lloh18:
	adrp	x9, _VCPU_SREG_CS@GOTPAGE
Lloh19:
	ldr	x9, [x9, _VCPU_SREG_CS@GOTPAGEOFF]
Lloh20:
	ldr	w2, [x9]
	add	x1, sp, #32
	blr	x8
	ldr	x8, [x20]
	ldr	x8, [x8]
	ldr	x0, [x19, #8]
Lloh21:
	adrp	x9, _VCPU_SREG_SS@GOTPAGE
Lloh22:
	ldr	x9, [x9, _VCPU_SREG_SS@GOTPAGEOFF]
Lloh23:
	ldr	w2, [x9]
	add	x1, sp, #16
	blr	x8
	ldr	x8, [x19, #8]
Lloh24:
	adrp	x9, _VCPU_REGS_RDX@GOTPAGE
Lloh25:
	ldr	x9, [x9, _VCPU_REGS_RDX@GOTPAGEOFF]
	ldr	x8, [x8]
Lloh26:
	ldr	x9, [x9]
	ldr	w9, [x8, x9, lsl #2]
Lloh27:
	adrp	x10, _VCPU_REGS_RCX@GOTPAGE
Lloh28:
	ldr	x10, [x10, _VCPU_REGS_RCX@GOTPAGEOFF]
	str	w9, [x19, #32]
Lloh29:
	ldr	x9, [x10]
	ldr	w8, [x8, x9, lsl #2]
Lloh30:
	adrp	x9, _VCPU_REGS_RSP@GOTPAGE
Lloh31:
	ldr	x9, [x9, _VCPU_REGS_RSP@GOTPAGEOFF]
	ldr	x10, [x19, #24]
Lloh32:
	ldr	x9, [x9]
	str	w8, [x10, x9, lsl #2]
Lloh33:
	adrp	x8, _X86EMUL_CONTINUE@GOTPAGE
Lloh34:
	ldr	x8, [x8, _X86EMUL_CONTINUE@GOTPAGEOFF]
	b	LBB0_9
LBB0_8:
	ldr	x0, [x19, #8]
	mov	w1, #0
	bl	_kvm_inject_gp
Lloh35:
	adrp	x8, _X86EMUL_PROPAGATE_FAULT@GOTPAGE
Lloh36:
	ldr	x8, [x8, _X86EMUL_PROPAGATE_FAULT@GOTPAGEOFF]
LBB0_9:
	ldr	w0, [x8]
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdr	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh35, Lloh36
	.cfi_endproc
                                        ; -- End function
	.comm	_X86EMUL_MODE_REAL,8,3          ; @X86EMUL_MODE_REAL
	.comm	_X86EMUL_MODE_VM86,8,3          ; @X86EMUL_MODE_VM86
	.comm	_X86EMUL_UNHANDLEABLE,4,2       ; @X86EMUL_UNHANDLEABLE
	.comm	_kvm_x86_ops,8,3                ; @kvm_x86_ops
	.comm	_MSR_IA32_SYSENTER_CS,4,2       ; @MSR_IA32_SYSENTER_CS
	.comm	_X86EMUL_PROPAGATE_FAULT,4,2    ; @X86EMUL_PROPAGATE_FAULT
	.comm	_SELECTOR_RPL_MASK,4,2          ; @SELECTOR_RPL_MASK
	.comm	_VCPU_SREG_CS,4,2               ; @VCPU_SREG_CS
	.comm	_VCPU_SREG_SS,4,2               ; @VCPU_SREG_SS
	.comm	_VCPU_REGS_RDX,8,3              ; @VCPU_REGS_RDX
	.comm	_VCPU_REGS_RCX,8,3              ; @VCPU_REGS_RCX
	.comm	_VCPU_REGS_RSP,8,3              ; @VCPU_REGS_RSP
	.comm	_X86EMUL_CONTINUE,4,2           ; @X86EMUL_CONTINUE
	.no_dead_strip	_emulate_sysexit
.subsections_via_symbols
