	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_update_bandwidth_info   ## -- Begin function radeon_update_bandwidth_info
	.p2align	4, 0x90
_radeon_update_bandwidth_info:          ## @radeon_update_bandwidth_info
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movl	8(%rdi), %r14d
	movl	12(%rdi), %r15d
	movl	$100, %edi
	callq	_dfixed_const
	movq	%rax, %r12
	movl	%r14d, %edi
	callq	_dfixed_const
	movq	%rax, 16(%rbx)
	movq	%rax, %rdi
	movq	%r12, %rsi
	callq	_dfixed_div
	movq	%rax, 16(%rbx)
	movl	%r15d, %edi
	callq	_dfixed_const
	movq	%rax, 32(%rbx)
	movq	%rax, %rdi
	movq	%r12, %rsi
	callq	_dfixed_div
	movq	%rax, 32(%rbx)
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rbx)
	je	LBB0_2
## %bb.1:
	movl	$16, %edi
	callq	_dfixed_const
	movq	16(%rbx), %rdi
	movq	%rax, %rsi
	callq	_dfixed_div
	movq	%rax, 24(%rbx)
LBB0_2:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_update_bandwidth_info   ; -- Begin function radeon_update_bandwidth_info
	.p2align	2
_radeon_update_bandwidth_info:          ; @radeon_update_bandwidth_info
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldp	w20, w21, [x0, #8]
	mov	w0, #100
	bl	_dfixed_const
	mov	x22, x0
	mov	x0, x20
	bl	_dfixed_const
	str	x0, [x19, #16]
	mov	x1, x22
	bl	_dfixed_div
	str	x0, [x19, #16]
	mov	x0, x21
	bl	_dfixed_const
	str	x0, [x19, #32]
	mov	x1, x22
	bl	_dfixed_div
	str	x0, [x19, #32]
	ldr	w8, [x19]
Lloh0:
	adrp	x9, _RADEON_IS_IGP@GOTPAGE
Lloh1:
	ldr	x9, [x9, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
	mov	w0, #16
	bl	_dfixed_const
	mov	x1, x0
	ldr	x0, [x19, #16]
	bl	_dfixed_div
	str	x0, [x19, #24]
LBB0_2:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
.subsections_via_symbols
