	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function r600_gpu_check_soft_reset
_r600_gpu_check_soft_reset:             ## @r600_gpu_check_soft_reset
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	_R_008010_GRBM_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r14d
	movq	%rbx, -64(%rbp)                 ## 8-byte Spill
	movq	(%rbx), %rax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movq	_CHIP_RV770@GOTPCREL(%rip), %rax
	movq	(%rax), %rbx
	movl	%r14d, %edi
	callq	_G_008010_PA_BUSY
	movl	%eax, %r15d
	movl	%r14d, %edi
	callq	_G_008010_SC_BUSY
	movl	%eax, %r12d
	orl	%r15d, %r12d
	movl	%r14d, %edi
	callq	_G_008010_SH_BUSY
	movl	%eax, %r13d
	movl	%r14d, %edi
	callq	_G_008010_SX_BUSY
	movl	%eax, %r15d
	orl	%r13d, %r15d
	orl	%r12d, %r15d
	cmpq	%rbx, -48(%rbp)                 ## 8-byte Folded Reload
	jge	LBB0_1
## %bb.2:
	movl	%r14d, %edi
	callq	_G_008010_TA03_BUSY
	jmp	LBB0_3
LBB0_1:
	movl	%r14d, %edi
	callq	_G_008010_TA_BUSY
LBB0_3:
	orl	%eax, %r15d
	movl	%r14d, %edi
	callq	_G_008010_VGT_BUSY
	movl	%eax, %r12d
	movl	%r14d, %edi
	callq	_G_008010_DB03_BUSY
	movl	%eax, %ebx
	orl	%r12d, %ebx
	movl	%r14d, %edi
	callq	_G_008010_CB03_BUSY
	movl	%eax, %r12d
	orl	%ebx, %r12d
	movl	%r14d, %edi
	callq	_G_008010_SPI03_BUSY
	movl	%eax, %ebx
	orl	%r12d, %ebx
	orl	%r15d, %ebx
	movl	%r14d, %edi
	callq	_G_008010_VGT_BUSY_NO_DMA
	xorl	%r15d, %r15d
	orl	%ebx, %eax
	movq	_RADEON_RESET_GFX@GOTPCREL(%rip), %rax
	movl	$0, %r13d
	je	LBB0_5
## %bb.4:
	movl	(%rax), %r13d
LBB0_5:
	movl	%r14d, %edi
	callq	_G_008010_CF_RQ_PENDING
	movl	%eax, %r12d
	movl	%r14d, %edi
	callq	_G_008010_PF_RQ_PENDING
	movl	%eax, %ebx
	orl	%r12d, %ebx
	movl	%r14d, %edi
	callq	_G_008010_CP_BUSY
	movl	%eax, %r12d
	orl	%ebx, %r12d
	movl	%r14d, %edi
	callq	_G_008010_CP_COHERENCY_BUSY
	orl	%r12d, %eax
	movq	_RADEON_RESET_CP@GOTPCREL(%rip), %r12
	je	LBB0_7
## %bb.6:
	movl	(%r12), %r15d
LBB0_7:
	orl	%r13d, %r15d
	movl	%r15d, %ebx
	movl	%r14d, %edi
	callq	_G_008010_GRBM_EE_BUSY
	testq	%rax, %rax
	je	LBB0_9
## %bb.8:
	movq	_RADEON_RESET_GRBM@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_RADEON_RESET_GFX@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	orl	(%r12), %ebx
LBB0_9:
	movq	_DMA_STATUS_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_DMA_IDLE@GOTPCREL(%rip), %rcx
	movl	$0, %edx
	andl	(%rcx), %eax
	jne	LBB0_11
## %bb.10:
	movq	_RADEON_RESET_DMA@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
LBB0_11:
	movl	%edx, -48(%rbp)                 ## 4-byte Spill
	movq	_R_000E50_SRBM_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r12d
	movl	%eax, %edi
	callq	_G_000E50_RLC_RQ_PENDING
	movl	%eax, %r14d
	movl	%r12d, %edi
	callq	_G_000E50_RLC_BUSY
	orl	%r14d, %eax
	movl	$0, %r14d
	je	LBB0_13
## %bb.12:
	movq	_RADEON_RESET_RLC@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
LBB0_13:
	movl	%r12d, %edi
	callq	_G_000E50_IH_BUSY
	movl	$0, %r13d
	testq	%rax, %rax
	je	LBB0_15
## %bb.14:
	movq	_RADEON_RESET_IH@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
LBB0_15:
	movl	%r12d, %edi
	callq	_G_000E50_SEM_BUSY
	movl	$0, %r15d
	testq	%rax, %rax
	je	LBB0_17
## %bb.16:
	movq	_RADEON_RESET_SEM@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
LBB0_17:
	movl	%r12d, %edi
	callq	_G_000E50_GRBM_RQ_PENDING
	movl	$0, %ecx
	testq	%rax, %rax
	je	LBB0_19
## %bb.18:
	movq	_RADEON_RESET_GRBM@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
LBB0_19:
	orl	%ecx, %r15d
	movl	%r12d, %edi
	callq	_G_000E50_VMC_BUSY
	movl	$0, %ecx
	testq	%rax, %rax
	je	LBB0_21
## %bb.20:
	movq	_RADEON_RESET_VMC@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
LBB0_21:
	orl	%ecx, %r15d
	orl	%r14d, %ebx
	movl	%ebx, -52(%rbp)                 ## 4-byte Spill
	orl	%r13d, -48(%rbp)                ## 4-byte Folded Spill
	movl	%r12d, %edi
	callq	_G_000E50_MCB_BUSY
	movl	%eax, %r14d
	movl	%r12d, %edi
	callq	_G_000E50_MCDZ_BUSY
	movl	%eax, %r13d
	orl	%r14d, %r13d
	movl	%r12d, %edi
	callq	_G_000E50_MCDY_BUSY
	movl	%eax, %r14d
	movl	%r12d, %edi
	callq	_G_000E50_MCDX_BUSY
	movl	%eax, %ebx
	orl	%r14d, %ebx
	orl	%r13d, %ebx
	movl	%r12d, %edi
	callq	_G_000E50_MCDW_BUSY
	orl	%ebx, %eax
	movq	_RADEON_RESET_MC@GOTPCREL(%rip), %r14
	movl	$0, %eax
	je	LBB0_23
## %bb.22:
	movl	(%r14), %eax
LBB0_23:
	orl	%eax, %r15d
	movl	-52(%rbp), %ebx                 ## 4-byte Reload
	orl	-48(%rbp), %ebx                 ## 4-byte Folded Reload
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	callq	_r600_is_display_hung
	testq	%rax, %rax
	movl	$0, %eax
	je	LBB0_25
## %bb.24:
	movq	_RADEON_RESET_DISPLAY@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_25:
	orl	%eax, %r15d
	orl	%r15d, %ebx
	testl	%ebx, (%r14)
	je	LBB0_27
## %bb.26:
	leaq	L_.str(%rip), %rdi
	movl	%ebx, %esi
	callq	_DRM_DEBUG
	movl	(%r14), %eax
	notl	%eax
	andl	%eax, %ebx
LBB0_27:
	movl	%ebx, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_R_008010_GRBM_STATUS,4,2       ## @R_008010_GRBM_STATUS
	.comm	_CHIP_RV770,8,3                 ## @CHIP_RV770
	.comm	_RADEON_RESET_GFX,4,2           ## @RADEON_RESET_GFX
	.comm	_RADEON_RESET_CP,4,2            ## @RADEON_RESET_CP
	.comm	_RADEON_RESET_GRBM,4,2          ## @RADEON_RESET_GRBM
	.comm	_DMA_STATUS_REG,4,2             ## @DMA_STATUS_REG
	.comm	_DMA_IDLE,4,2                   ## @DMA_IDLE
	.comm	_RADEON_RESET_DMA,4,2           ## @RADEON_RESET_DMA
	.comm	_R_000E50_SRBM_STATUS,4,2       ## @R_000E50_SRBM_STATUS
	.comm	_RADEON_RESET_RLC,4,2           ## @RADEON_RESET_RLC
	.comm	_RADEON_RESET_IH,4,2            ## @RADEON_RESET_IH
	.comm	_RADEON_RESET_SEM,4,2           ## @RADEON_RESET_SEM
	.comm	_RADEON_RESET_VMC,4,2           ## @RADEON_RESET_VMC
	.comm	_RADEON_RESET_MC,4,2            ## @RADEON_RESET_MC
	.comm	_RADEON_RESET_DISPLAY,4,2       ## @RADEON_RESET_DISPLAY
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"MC busy: 0x%08X, clearing.\n"

	.no_dead_strip	_r600_gpu_check_soft_reset
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function r600_gpu_check_soft_reset
_r600_gpu_check_soft_reset:             ; @r600_gpu_check_soft_reset
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x8, _R_008010_GRBM_STATUS@GOTPAGE
Lloh1:
	ldr	x8, [x8, _R_008010_GRBM_STATUS@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x20, x0
	ldr	x22, [x19]
Lloh3:
	adrp	x8, _CHIP_RV770@GOTPAGE
Lloh4:
	ldr	x8, [x8, _CHIP_RV770@GOTPAGEOFF]
Lloh5:
	ldr	x23, [x8]
	bl	_G_008010_PA_BUSY
	mov	x21, x0
	mov	x0, x20
	bl	_G_008010_SC_BUSY
	orr	w21, w0, w21
	mov	x0, x20
	bl	_G_008010_SH_BUSY
	orr	w21, w21, w0
	mov	x0, x20
	bl	_G_008010_SX_BUSY
	orr	w21, w21, w0
	mov	x0, x20
	cmp	x22, x23
	b.ge	LBB0_2
; %bb.1:
	bl	_G_008010_TA03_BUSY
	b	LBB0_3
LBB0_2:
	bl	_G_008010_TA_BUSY
LBB0_3:
	orr	w21, w21, w0
	mov	x0, x20
	bl	_G_008010_VGT_BUSY
	orr	w21, w21, w0
	mov	x0, x20
	bl	_G_008010_DB03_BUSY
	orr	w21, w21, w0
	mov	x0, x20
	bl	_G_008010_CB03_BUSY
	orr	w21, w21, w0
	mov	x0, x20
	bl	_G_008010_SPI03_BUSY
	orr	w21, w21, w0
	mov	x0, x20
	bl	_G_008010_VGT_BUSY_NO_DMA
	orr	w8, w21, w0
Lloh6:
	adrp	x23, _RADEON_RESET_GFX@GOTPAGE
Lloh7:
	ldr	x23, [x23, _RADEON_RESET_GFX@GOTPAGEOFF]
	ldr	w9, [x23]
	cmp	w8, #0
	csel	w22, wzr, w9, eq
	mov	x0, x20
	bl	_G_008010_CF_RQ_PENDING
	mov	x21, x0
	mov	x0, x20
	bl	_G_008010_PF_RQ_PENDING
	orr	w21, w0, w21
	mov	x0, x20
	bl	_G_008010_CP_BUSY
	orr	w21, w21, w0
	mov	x0, x20
	bl	_G_008010_CP_COHERENCY_BUSY
	orr	w8, w21, w0
Lloh8:
	adrp	x24, _RADEON_RESET_CP@GOTPAGE
Lloh9:
	ldr	x24, [x24, _RADEON_RESET_CP@GOTPAGEOFF]
	ldr	w9, [x24]
	cmp	w8, #0
	csel	w8, wzr, w9, eq
	orr	w21, w8, w22
	mov	x0, x20
	bl	_G_008010_GRBM_EE_BUSY
Lloh10:
	adrp	x22, _RADEON_RESET_GRBM@GOTPAGE
Lloh11:
	ldr	x22, [x22, _RADEON_RESET_GRBM@GOTPAGEOFF]
	cbz	x0, LBB0_5
; %bb.4:
	ldr	w8, [x22]
	ldr	w9, [x23]
	ldr	w10, [x24]
	orr	w8, w8, w21
	orr	w8, w8, w9
	orr	w21, w8, w10
LBB0_5:
Lloh12:
	adrp	x8, _DMA_STATUS_REG@GOTPAGE
Lloh13:
	ldr	x8, [x8, _DMA_STATUS_REG@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	bl	_RREG32
Lloh15:
	adrp	x8, _DMA_IDLE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _DMA_IDLE@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
Lloh18:
	adrp	x9, _RADEON_RESET_DMA@GOTPAGE
Lloh19:
	ldr	x9, [x9, _RADEON_RESET_DMA@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	tst	w8, w0
	csel	w8, w9, wzr, eq
	orr	w23, w8, w21
Lloh21:
	adrp	x8, _R_000E50_SRBM_STATUS@GOTPAGE
Lloh22:
	ldr	x8, [x8, _R_000E50_SRBM_STATUS@GOTPAGEOFF]
Lloh23:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x20, x0
	bl	_G_000E50_RLC_RQ_PENDING
	mov	x21, x0
	mov	x0, x20
	bl	_G_000E50_RLC_BUSY
	orr	w8, w0, w21
Lloh24:
	adrp	x9, _RADEON_RESET_RLC@GOTPAGE
Lloh25:
	ldr	x9, [x9, _RADEON_RESET_RLC@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	cmp	w8, #0
	csel	w8, wzr, w9, eq
	orr	w21, w23, w8
	mov	x0, x20
	bl	_G_000E50_IH_BUSY
Lloh27:
	adrp	x8, _RADEON_RESET_IH@GOTPAGE
Lloh28:
	ldr	x8, [x8, _RADEON_RESET_IH@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w21, w21, w8
	mov	x0, x20
	bl	_G_000E50_SEM_BUSY
Lloh30:
	adrp	x8, _RADEON_RESET_SEM@GOTPAGE
Lloh31:
	ldr	x8, [x8, _RADEON_RESET_SEM@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w21, w21, w8
	mov	x0, x20
	bl	_G_000E50_GRBM_RQ_PENDING
	ldr	w8, [x22]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w21, w21, w8
	mov	x0, x20
	bl	_G_000E50_VMC_BUSY
Lloh33:
	adrp	x8, _RADEON_RESET_VMC@GOTPAGE
Lloh34:
	ldr	x8, [x8, _RADEON_RESET_VMC@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w22, w21, w8
	mov	x0, x20
	bl	_G_000E50_MCB_BUSY
	mov	x21, x0
	mov	x0, x20
	bl	_G_000E50_MCDZ_BUSY
	orr	w21, w0, w21
	mov	x0, x20
	bl	_G_000E50_MCDY_BUSY
	orr	w21, w21, w0
	mov	x0, x20
	bl	_G_000E50_MCDX_BUSY
	orr	w21, w21, w0
	mov	x0, x20
	bl	_G_000E50_MCDW_BUSY
	orr	w8, w21, w0
Lloh36:
	adrp	x20, _RADEON_RESET_MC@GOTPAGE
Lloh37:
	ldr	x20, [x20, _RADEON_RESET_MC@GOTPAGEOFF]
	ldr	w9, [x20]
	cmp	w8, #0
	csel	w8, wzr, w9, eq
	orr	w21, w22, w8
	mov	x0, x19
	bl	_r600_is_display_hung
Lloh38:
	adrp	x8, _RADEON_RESET_DISPLAY@GOTPAGE
Lloh39:
	ldr	x8, [x8, _RADEON_RESET_DISPLAY@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w19, w21, w8
	ldr	w8, [x20]
	tst	w19, w8
	b.eq	LBB0_7
; %bb.6:
Lloh41:
	adrp	x0, l_.str@PAGE
Lloh42:
	add	x0, x0, l_.str@PAGEOFF
	mov	x1, x19
	bl	_DRM_DEBUG
	ldr	w8, [x20]
	bic	w19, w19, w8
LBB0_7:
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpAdd	Lloh41, Lloh42
	.cfi_endproc
                                        ; -- End function
	.comm	_R_008010_GRBM_STATUS,4,2       ; @R_008010_GRBM_STATUS
	.comm	_CHIP_RV770,8,3                 ; @CHIP_RV770
	.comm	_RADEON_RESET_GFX,4,2           ; @RADEON_RESET_GFX
	.comm	_RADEON_RESET_CP,4,2            ; @RADEON_RESET_CP
	.comm	_RADEON_RESET_GRBM,4,2          ; @RADEON_RESET_GRBM
	.comm	_DMA_STATUS_REG,4,2             ; @DMA_STATUS_REG
	.comm	_DMA_IDLE,4,2                   ; @DMA_IDLE
	.comm	_RADEON_RESET_DMA,4,2           ; @RADEON_RESET_DMA
	.comm	_R_000E50_SRBM_STATUS,4,2       ; @R_000E50_SRBM_STATUS
	.comm	_RADEON_RESET_RLC,4,2           ; @RADEON_RESET_RLC
	.comm	_RADEON_RESET_IH,4,2            ; @RADEON_RESET_IH
	.comm	_RADEON_RESET_SEM,4,2           ; @RADEON_RESET_SEM
	.comm	_RADEON_RESET_VMC,4,2           ; @RADEON_RESET_VMC
	.comm	_RADEON_RESET_MC,4,2            ; @RADEON_RESET_MC
	.comm	_RADEON_RESET_DISPLAY,4,2       ; @RADEON_RESET_DISPLAY
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"MC busy: 0x%08X, clearing.\n"

	.no_dead_strip	_r600_gpu_check_soft_reset
.subsections_via_symbols
