	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_set_igpgart
_radeon_set_igpgart:                    ## @radeon_set_igpgart
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	testl	%esi, %esi
	je	LBB0_1
## %bb.2:
	movq	%rdi, %r13
	movslq	12(%rdi), %rdx
	movl	(%rdi), %esi
	movl	4(%rdi), %ecx
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG
	movq	_RS480_MC_MISC_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_IGP_READ_MCIND
	movq	_RADEON_FAMILY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	8(%r13), %eax
	movq	_CHIP_RS690@GOTPCREL(%rip), %rcx
	movq	_CHIP_RS740@GOTPCREL(%rip), %rdx
	xorl	%esi, %esi
	cmpl	(%rdx), %eax
	movq	_RS690_BLOCK_GFX_D3_EN@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	cmovel	%edx, %esi
	cmpl	(%rcx), %eax
	movl	(%rbx), %edi
	movq	_RS480_GART_INDEX_REG_EN@GOTPCREL(%rip), %rax
	cmovel	%edx, %esi
	orl	(%rax), %esi
	callq	_IGP_WRITE_MCIND
	movq	_RS480_AGP_ADDRESS_SPACE_SIZE@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	movq	_RS480_GART_EN@GOTPCREL(%rip), %r14
	movq	_RS480_VA_SIZE_32MB@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	orl	(%r14), %esi
	callq	_IGP_WRITE_MCIND
	movq	_RS480_GART_FEATURE_ID@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_IGP_READ_MCIND
	movq	_RS480_HANG_EN@GOTPCREL(%rip), %rax
	movq	_RS480_TLB_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movq	_RS480_GTW_LAC_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	(%rbx), %edi
	movq	_RS480_1LEVEL_GART@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	callq	_IGP_WRITE_MCIND
	movl	12(%r13), %edi
	movl	%edi, %ebx
	andl	$-4096, %ebx                    ## imm = 0xF000
	callq	_upper_32_bits
	movzbl	%al, %esi
	shll	$4, %esi
	orl	%ebx, %esi
	movq	_RS480_GART_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_IGP_WRITE_MCIND
	movq	_RS480_AGP_MODE_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_IGP_READ_MCIND
	movl	(%rbx), %edi
	movq	_RS480_REQ_TYPE_SNOOP_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	movq	_RS480_REQ_TYPE_SNOOP_DIS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	btsl	%eax, %esi
	callq	_IGP_WRITE_MCIND
	movl	(%r13), %esi
	movq	%r13, %rdi
	callq	_radeon_write_agp_base
	movl	$33554432, 4(%r13)              ## imm = 0x2000000
	movl	(%r13), %esi
	leal	33554431(%rsi), %eax
	andl	$-65536, %eax                   ## imm = 0xFFFF0000
	sarl	$16, %esi
	orl	%eax, %esi
	movq	%r13, %rdi
                                        ## kill: def $esi killed $esi killed $rsi
	callq	_radeon_write_agp_location
	movl	(%r15), %esi
	movq	%r13, %rdi
	callq	_IGP_READ_MCIND
	movl	(%r15), %edi
	movl	(%r12), %esi
	orl	(%r14), %esi
	callq	_IGP_WRITE_MCIND
	movq	_RS480_GART_CACHE_CNTRL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_IGP_READ_MCIND
	movq	_RS480_GART_CACHE_INVALIDATE@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %esi
	testl	%eax, %esi
	je	LBB0_5
## %bb.3:                               ##   in Loop: Header=BB0_4 Depth=1
	movl	$1, %edi
	callq	_DRM_UDELAY
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_IGP_READ_MCIND
	jmp	LBB0_4
LBB0_5:
	movl	(%rbx), %edi
	callq	_IGP_WRITE_MCIND
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_IGP_READ_MCIND
	testl	%eax, (%r14)
	je	LBB0_8
## %bb.6:
	movq	_RS480_GART_CACHE_CNTRL@GOTPCREL(%rip), %rbx
	.p2align	4, 0x90
LBB0_7:                                 ## =>This Inner Loop Header: Depth=1
	movl	$1, %edi
	callq	_DRM_UDELAY
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_IGP_READ_MCIND
	testl	%eax, (%r14)
	jne	LBB0_7
	jmp	LBB0_8
LBB0_1:
	movq	_RS480_AGP_ADDRESS_SPACE_SIZE@GOTPCREL(%rip), %rbx
LBB0_8:
	movl	(%rbx), %edi
	xorl	%esi, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_IGP_WRITE_MCIND                ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"programming igp gart %08X %08lX %08X\n"

	.comm	_RS480_MC_MISC_CNTL,4,2         ## @RS480_MC_MISC_CNTL
	.comm	_RADEON_FAMILY_MASK,4,2         ## @RADEON_FAMILY_MASK
	.comm	_CHIP_RS690,4,2                 ## @CHIP_RS690
	.comm	_CHIP_RS740,4,2                 ## @CHIP_RS740
	.comm	_RS480_GART_INDEX_REG_EN,4,2    ## @RS480_GART_INDEX_REG_EN
	.comm	_RS690_BLOCK_GFX_D3_EN,4,2      ## @RS690_BLOCK_GFX_D3_EN
	.comm	_RS480_AGP_ADDRESS_SPACE_SIZE,4,2 ## @RS480_AGP_ADDRESS_SPACE_SIZE
	.comm	_RS480_GART_EN,4,2              ## @RS480_GART_EN
	.comm	_RS480_VA_SIZE_32MB,4,2         ## @RS480_VA_SIZE_32MB
	.comm	_RS480_GART_FEATURE_ID,4,2      ## @RS480_GART_FEATURE_ID
	.comm	_RS480_HANG_EN,4,2              ## @RS480_HANG_EN
	.comm	_RS480_TLB_ENABLE,4,2           ## @RS480_TLB_ENABLE
	.comm	_RS480_GTW_LAC_EN,4,2           ## @RS480_GTW_LAC_EN
	.comm	_RS480_1LEVEL_GART,4,2          ## @RS480_1LEVEL_GART
	.comm	_RS480_GART_BASE,4,2            ## @RS480_GART_BASE
	.comm	_RS480_AGP_MODE_CNTL,4,2        ## @RS480_AGP_MODE_CNTL
	.comm	_RS480_REQ_TYPE_SNOOP_SHIFT,4,2 ## @RS480_REQ_TYPE_SNOOP_SHIFT
	.comm	_RS480_REQ_TYPE_SNOOP_DIS,4,2   ## @RS480_REQ_TYPE_SNOOP_DIS
	.comm	_RS480_GART_CACHE_CNTRL,4,2     ## @RS480_GART_CACHE_CNTRL
	.comm	_RS480_GART_CACHE_INVALIDATE,4,2 ## @RS480_GART_CACHE_INVALIDATE
	.no_dead_strip	_radeon_set_igpgart
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_set_igpgart
_radeon_set_igpgart:                    ; @radeon_set_igpgart
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
Lloh0:
	adrp	x21, _RS480_AGP_ADDRESS_SPACE_SIZE@GOTPAGE
Lloh1:
	ldr	x21, [x21, _RS480_AGP_ADDRESS_SPACE_SIZE@GOTPAGEOFF]
	cbz	w1, LBB0_7
; %bb.1:
	mov	x19, x0
	ldrsw	x2, [x0, #12]
	ldp	w1, w3, [x0]
Lloh2:
	adrp	x0, l_.str@PAGE
Lloh3:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG
Lloh4:
	adrp	x20, _RS480_MC_MISC_CNTL@GOTPAGE
Lloh5:
	ldr	x20, [x20, _RS480_MC_MISC_CNTL@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_IGP_READ_MCIND
	ldr	w8, [x19, #8]
Lloh6:
	adrp	x9, _RADEON_FAMILY_MASK@GOTPAGE
Lloh7:
	ldr	x9, [x9, _RADEON_FAMILY_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	and	w8, w9, w8
Lloh9:
	adrp	x9, _CHIP_RS690@GOTPAGE
Lloh10:
	ldr	x9, [x9, _CHIP_RS690@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
Lloh12:
	adrp	x10, _CHIP_RS740@GOTPAGE
Lloh13:
	ldr	x10, [x10, _CHIP_RS740@GOTPAGEOFF]
Lloh14:
	ldr	w10, [x10]
	cmp	w8, w10
	ccmp	w8, w9, #4, ne
	ldr	w0, [x20]
Lloh15:
	adrp	x8, _RS480_GART_INDEX_REG_EN@GOTPAGE
Lloh16:
	ldr	x8, [x8, _RS480_GART_INDEX_REG_EN@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
Lloh18:
	adrp	x9, _RS690_BLOCK_GFX_D3_EN@GOTPAGE
Lloh19:
	ldr	x9, [x9, _RS690_BLOCK_GFX_D3_EN@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	csel	w9, w9, wzr, eq
	orr	w1, w8, w9
	bl	_IGP_WRITE_MCIND
Lloh21:
	adrp	x22, _RS480_GART_EN@GOTPAGE
Lloh22:
	ldr	x22, [x22, _RS480_GART_EN@GOTPAGEOFF]
	ldr	w0, [x21]
	ldr	w8, [x22]
Lloh23:
	adrp	x23, _RS480_VA_SIZE_32MB@GOTPAGE
Lloh24:
	ldr	x23, [x23, _RS480_VA_SIZE_32MB@GOTPAGEOFF]
	ldr	w9, [x23]
	orr	w1, w9, w8
	bl	_IGP_WRITE_MCIND
Lloh25:
	adrp	x20, _RS480_GART_FEATURE_ID@GOTPAGE
Lloh26:
	ldr	x20, [x20, _RS480_GART_FEATURE_ID@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_IGP_READ_MCIND
	ldr	w0, [x20]
Lloh27:
	adrp	x8, _RS480_HANG_EN@GOTPAGE
Lloh28:
	ldr	x8, [x8, _RS480_HANG_EN@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
Lloh30:
	adrp	x9, _RS480_TLB_ENABLE@GOTPAGE
Lloh31:
	ldr	x9, [x9, _RS480_TLB_ENABLE@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh33:
	adrp	x9, _RS480_GTW_LAC_EN@GOTPAGE
Lloh34:
	ldr	x9, [x9, _RS480_GTW_LAC_EN@GOTPAGEOFF]
Lloh35:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh36:
	adrp	x9, _RS480_1LEVEL_GART@GOTPAGE
Lloh37:
	ldr	x9, [x9, _RS480_1LEVEL_GART@GOTPAGEOFF]
Lloh38:
	ldr	w9, [x9]
	orr	w1, w8, w9
	bl	_IGP_WRITE_MCIND
	ldr	w0, [x19, #12]
	and	w20, w0, #0xfffff000
	bl	_upper_32_bits
	bfi	w20, w0, #4, #8
Lloh39:
	adrp	x8, _RS480_GART_BASE@GOTPAGE
Lloh40:
	ldr	x8, [x8, _RS480_GART_BASE@GOTPAGEOFF]
Lloh41:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_IGP_WRITE_MCIND
Lloh42:
	adrp	x20, _RS480_AGP_MODE_CNTL@GOTPAGE
Lloh43:
	ldr	x20, [x20, _RS480_AGP_MODE_CNTL@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_IGP_READ_MCIND
	ldr	w0, [x20]
Lloh44:
	adrp	x8, _RS480_REQ_TYPE_SNOOP_SHIFT@GOTPAGE
Lloh45:
	ldr	x8, [x8, _RS480_REQ_TYPE_SNOOP_SHIFT@GOTPAGEOFF]
Lloh46:
	ldr	w8, [x8]
	mov	w9, #1
	lsl	w8, w9, w8
Lloh47:
	adrp	x9, _RS480_REQ_TYPE_SNOOP_DIS@GOTPAGE
Lloh48:
	ldr	x9, [x9, _RS480_REQ_TYPE_SNOOP_DIS@GOTPAGEOFF]
Lloh49:
	ldr	w9, [x9]
	orr	w1, w8, w9
	bl	_IGP_WRITE_MCIND
	ldr	w1, [x19]
	mov	x0, x19
	bl	_radeon_write_agp_base
	mov	w8, #33554432
	str	w8, [x19, #4]
	ldr	w8, [x19]
	mov	w9, #33554431
	add	w9, w8, w9
	and	w9, w9, #0xffff0000
	orr	w1, w9, w8, asr #16
	mov	x0, x19
	bl	_radeon_write_agp_location
	ldr	w1, [x21]
	mov	x0, x19
	bl	_IGP_READ_MCIND
	ldr	w0, [x21]
	ldr	w8, [x22]
	ldr	w9, [x23]
	orr	w1, w9, w8
	bl	_IGP_WRITE_MCIND
Lloh50:
	adrp	x21, _RS480_GART_CACHE_CNTRL@GOTPAGE
Lloh51:
	ldr	x21, [x21, _RS480_GART_CACHE_CNTRL@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_IGP_READ_MCIND
Lloh52:
	adrp	x20, _RS480_GART_CACHE_INVALIDATE@GOTPAGE
Lloh53:
	ldr	x20, [x20, _RS480_GART_CACHE_INVALIDATE@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x20]
	tst	w1, w0
	b.eq	LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	mov	w0, #1
	bl	_DRM_UDELAY
	ldr	w1, [x21]
	mov	x0, x19
	bl	_IGP_READ_MCIND
	b	LBB0_2
LBB0_4:
	ldr	w0, [x21]
	bl	_IGP_WRITE_MCIND
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x21]
	mov	x0, x19
	bl	_IGP_READ_MCIND
	ldr	w8, [x20]
	tst	w8, w0
	b.eq	LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	mov	w0, #1
	bl	_DRM_UDELAY
	b	LBB0_5
LBB0_7:
	ldr	w0, [x21]
	mov	w1, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_IGP_WRITE_MCIND
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpAdd	Lloh2, Lloh3
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"programming igp gart %08X %08lX %08X\n"

	.comm	_RS480_MC_MISC_CNTL,4,2         ; @RS480_MC_MISC_CNTL
	.comm	_RADEON_FAMILY_MASK,4,2         ; @RADEON_FAMILY_MASK
	.comm	_CHIP_RS690,4,2                 ; @CHIP_RS690
	.comm	_CHIP_RS740,4,2                 ; @CHIP_RS740
	.comm	_RS480_GART_INDEX_REG_EN,4,2    ; @RS480_GART_INDEX_REG_EN
	.comm	_RS690_BLOCK_GFX_D3_EN,4,2      ; @RS690_BLOCK_GFX_D3_EN
	.comm	_RS480_AGP_ADDRESS_SPACE_SIZE,4,2 ; @RS480_AGP_ADDRESS_SPACE_SIZE
	.comm	_RS480_GART_EN,4,2              ; @RS480_GART_EN
	.comm	_RS480_VA_SIZE_32MB,4,2         ; @RS480_VA_SIZE_32MB
	.comm	_RS480_GART_FEATURE_ID,4,2      ; @RS480_GART_FEATURE_ID
	.comm	_RS480_HANG_EN,4,2              ; @RS480_HANG_EN
	.comm	_RS480_TLB_ENABLE,4,2           ; @RS480_TLB_ENABLE
	.comm	_RS480_GTW_LAC_EN,4,2           ; @RS480_GTW_LAC_EN
	.comm	_RS480_1LEVEL_GART,4,2          ; @RS480_1LEVEL_GART
	.comm	_RS480_GART_BASE,4,2            ; @RS480_GART_BASE
	.comm	_RS480_AGP_MODE_CNTL,4,2        ; @RS480_AGP_MODE_CNTL
	.comm	_RS480_REQ_TYPE_SNOOP_SHIFT,4,2 ; @RS480_REQ_TYPE_SNOOP_SHIFT
	.comm	_RS480_REQ_TYPE_SNOOP_DIS,4,2   ; @RS480_REQ_TYPE_SNOOP_DIS
	.comm	_RS480_GART_CACHE_CNTRL,4,2     ; @RS480_GART_CACHE_CNTRL
	.comm	_RS480_GART_CACHE_INVALIDATE,4,2 ; @RS480_GART_CACHE_INVALIDATE
	.no_dead_strip	_radeon_set_igpgart
.subsections_via_symbols
