	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_legacy_tv_adjust_pll2   ## -- Begin function radeon_legacy_tv_adjust_pll2
	.p2align	4, 0x90
_radeon_legacy_tv_adjust_pll2:          ## @radeon_legacy_tv_adjust_pll2
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%r8, %r13
	movq	%rcx, %r14
	movq	%rdx, %r15
	movq	%rsi, %r12
	callq	_to_radeon_encoder
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	_radeon_legacy_tv_get_std_mode
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movl	(%rax), %ecx
	andl	$7, %ecx
	movl	%ecx, (%r12)
	movl	4(%rax), %ecx
	movl	%ecx, (%r15)
	movl	$2047, %ebx                     ## imm = 0x7FF
	andl	8(%rax), %ebx
	movl	12(%rax), %edi
	callq	_get_post_div
	shll	$16, %eax
	orl	%ebx, %eax
	movl	%eax, (%r14)
	movq	_RADEON_PIX2CLK_SRC_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	(%r13), %eax
	movl	%eax, (%r13)
	movq	_RADEON_PIX2CLK_SRC_SEL_P2PLLCLK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_PIXCLK_TV_SRC_SEL@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r13)
LBB0_2:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_PIX2CLK_SRC_SEL_MASK,4,2 ## @RADEON_PIX2CLK_SRC_SEL_MASK
	.comm	_RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,4,2 ## @RADEON_PIX2CLK_SRC_SEL_P2PLLCLK
	.comm	_RADEON_PIXCLK_TV_SRC_SEL,4,2   ## @RADEON_PIXCLK_TV_SRC_SEL
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_legacy_tv_adjust_pll2   ; -- Begin function radeon_legacy_tv_adjust_pll2
	.p2align	2
_radeon_legacy_tv_adjust_pll2:          ; @radeon_legacy_tv_adjust_pll2
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x4
	mov	x20, x3
	mov	x21, x2
	mov	x22, x1
	bl	_to_radeon_encoder
	mov	x1, #0
	bl	_radeon_legacy_tv_get_std_mode
	cbz	x0, LBB0_2
; %bb.1:
	ldr	w8, [x0]
	and	w8, w8, #0x7
	str	w8, [x22]
	ldr	w8, [x0, #4]
	str	w8, [x21]
	ldp	w8, w0, [x0, #8]
	and	w21, w8, #0x7ff
	bl	_get_post_div
	bfi	w21, w0, #16, #16
	str	w21, [x20]
Lloh0:
	adrp	x8, _RADEON_PIX2CLK_SRC_SEL_MASK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_PIX2CLK_SRC_SEL_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	ldr	w9, [x19]
	bic	w8, w9, w8
	str	w8, [x19]
Lloh3:
	adrp	x9, _RADEON_PIX2CLK_SRC_SEL_P2PLLCLK@GOTPAGE
Lloh4:
	ldr	x9, [x9, _RADEON_PIX2CLK_SRC_SEL_P2PLLCLK@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
Lloh6:
	adrp	x10, _RADEON_PIXCLK_TV_SRC_SEL@GOTPAGE
Lloh7:
	ldr	x10, [x10, _RADEON_PIXCLK_TV_SRC_SEL@GOTPAGEOFF]
Lloh8:
	ldr	w10, [x10]
	orr	w8, w9, w8
	orr	w8, w8, w10
	str	w8, [x19]
LBB0_2:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_PIX2CLK_SRC_SEL_MASK,4,2 ; @RADEON_PIX2CLK_SRC_SEL_MASK
	.comm	_RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,4,2 ; @RADEON_PIX2CLK_SRC_SEL_P2PLLCLK
	.comm	_RADEON_PIXCLK_TV_SRC_SEL,4,2   ; @RADEON_PIXCLK_TV_SRC_SEL
.subsections_via_symbols
