	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function bnx2x_init_pxp_arb
_bnx2x_init_pxp_arb:                    ## @bnx2x_init_pxp_arb
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %ebx
	movl	%esi, %r15d
	movq	%rdi, -56(%rbp)                 ## 8-byte Spill
	movq	_MAX_RD_ORD@GOTPCREL(%rip), %r14
	movl	(%r14), %ecx
	cmpl	%esi, %ecx
	jge	LBB0_2
## %bb.1:
	movq	_NETIF_MSG_HW@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	leaq	L_.str(%rip), %rsi
	movl	%r15d, %edx
	xorl	%eax, %eax
	callq	_DP
	movl	(%r14), %r15d
LBB0_2:
	movq	_MAX_WR_ORD@GOTPCREL(%rip), %r14
	movl	(%r14), %ecx
	cmpl	%ebx, %ecx
	jge	LBB0_4
## %bb.3:
	movq	_NETIF_MSG_HW@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	leaq	L_.str.1(%rip), %rsi
	movl	%ebx, %edx
	xorl	%eax, %eax
	callq	_DP
	movl	(%r14), %ebx
LBB0_4:
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_CHIP_REV_IS_FPGA
	testq	%rax, %rax
	je	LBB0_6
## %bb.5:
	movq	_NETIF_MSG_HW@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	leaq	L_.str.2(%rip), %rsi
	xorl	%ebx, %ebx
	xorl	%eax, %eax
	callq	_DP
LBB0_6:
	movq	_NETIF_MSG_HW@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	leaq	L_.str.3(%rip), %rsi
	movl	%r15d, %edx
	movl	%ebx, -44(%rbp)                 ## 4-byte Spill
	movl	%ebx, %ecx
	xorl	%eax, %eax
	callq	_DP
	movq	_NUM_RD_Q@GOTPCREL(%rip), %rax
	cmpl	$2, (%rax)
	movl	%r15d, -60(%rbp)                ## 4-byte Spill
	movslq	%r15d, %rax
	movq	%rax, -80(%rbp)                 ## 8-byte Spill
	movq	-56(%rbp), %r12                 ## 8-byte Reload
	jl	LBB0_9
## %bb.7:
	xorl	%r13d, %r13d
	movq	-80(%rbp), %rax                 ## 8-byte Reload
	leaq	(,%rax,4), %rax
	leaq	(%rax,%rax,2), %rax
	movq	%rax, -72(%rbp)                 ## 8-byte Spill
	xorl	%ebx, %ebx
	movq	-72(%rbp), %r14                 ## 8-byte Reload
	.p2align	4, 0x90
LBB0_8:                                 ## =>This Inner Loop Header: Depth=1
	movq	_read_arb_addr@GOTPCREL(%rip), %r15
	movq	(%r15), %rax
	movq	(%rax,%r13), %rsi
	movq	_read_arb_data@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	(%rax,%rbx,8), %rax
	movl	(%rax,%r14), %edx
	movq	%r12, %rdi
	callq	_REG_WR
	movq	(%r15), %rax
	movq	8(%rax,%r13), %rsi
	movq	_read_arb_data@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	(%rax,%rbx,8), %rax
	movl	4(%rax,%r14), %edx
	movq	%r12, %rdi
	callq	_REG_WR
	movq	(%r15), %rax
	movq	16(%rax,%r13), %rsi
	movq	_read_arb_data@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	(%rax,%rbx,8), %rax
	movl	8(%rax,%r14), %edx
	movq	%r12, %rdi
	callq	_REG_WR
	incq	%rbx
	movq	_NUM_RD_Q@GOTPCREL(%rip), %rax
	movslq	(%rax), %rax
	decq	%rax
	addq	$24, %r13
	cmpq	%rax, %rbx
	jl	LBB0_8
LBB0_9:
	movq	_NUM_WR_Q@GOTPCREL(%rip), %rax
	movslq	(%rax), %rax
	cmpq	$1, %rax
	jle	LBB0_10
## %bb.11:
	movslq	-44(%rbp), %rax                 ## 4-byte Folded Reload
	xorl	%r15d, %r15d
	movq	%rax, -88(%rbp)                 ## 8-byte Spill
	leaq	(,%rax,4), %rax
	leaq	(%rax,%rax,2), %rax
	movq	%rax, -72(%rbp)                 ## 8-byte Spill
	xorl	%r13d, %r13d
	jmp	LBB0_12
	.p2align	4, 0x90
LBB0_14:                                ##   in Loop: Header=BB0_12 Depth=1
	movq	_write_arb_data@GOTPCREL(%rip), %r14
	movq	(%r14), %rax
	movq	(%rax,%r13,8), %rax
	movq	-72(%rbp), %r12                 ## 8-byte Reload
	movl	(%rax,%r12), %edx
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	callq	_REG_WR
	movq	_write_arb_addr@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	8(%rax,%r15), %rsi
	movq	(%r14), %rax
	movq	(%rax,%r13,8), %rax
	movl	4(%rax,%r12), %edx
	movq	%rbx, %rdi
	callq	_REG_WR
	movq	_write_arb_addr@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	16(%rax,%r15), %rsi
	movq	(%r14), %rax
	movq	(%rax,%r13,8), %rax
	movl	8(%rax,%r12), %edx
	movq	%rbx, %rdi
LBB0_16:                                ##   in Loop: Header=BB0_12 Depth=1
	callq	_REG_WR
	incq	%r13
	movq	_NUM_WR_Q@GOTPCREL(%rip), %rax
	movslq	(%rax), %rax
	decq	%rax
	addq	$24, %r15
	cmpq	%rax, %r13
	jge	LBB0_17
LBB0_12:                                ## =>This Inner Loop Header: Depth=1
	movq	_write_arb_addr@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	(%rax,%r15), %rsi
	movq	_PXP2_REG_RQ_BW_WR_L29@GOTPCREL(%rip), %rax
	cmpq	(%rax), %rsi
	je	LBB0_14
## %bb.13:                              ##   in Loop: Header=BB0_12 Depth=1
	movq	_PXP2_REG_RQ_BW_WR_L30@GOTPCREL(%rip), %rax
	cmpq	(%rax), %rsi
	je	LBB0_14
## %bb.15:                              ##   in Loop: Header=BB0_12 Depth=1
	movq	-56(%rbp), %r14                 ## 8-byte Reload
	movq	%r14, %rdi
	callq	_REG_RD
	movq	_write_arb_addr@GOTPCREL(%rip), %r12
	movq	(%r12), %rcx
	movq	(%rcx,%r15), %rsi
	movq	_write_arb_data@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rcx
	movq	(%rcx,%r13,8), %rcx
	movq	-72(%rbp), %rbx                 ## 8-byte Reload
	movl	(%rcx,%rbx), %edx
	shll	$10, %edx
	orl	%eax, %edx
	movq	%r14, %rdi
	callq	_REG_WR
	movq	(%r12), %rax
	movq	8(%rax,%r15), %rsi
	movq	%r14, %rdi
	callq	_REG_RD
	movq	(%r12), %rcx
	movq	8(%rcx,%r15), %rsi
	movq	_write_arb_data@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	(%rcx,%r13,8), %rcx
	movl	4(%rcx,%rbx), %edx
	shll	$10, %edx
	orl	%eax, %edx
	movq	%r14, %rdi
	callq	_REG_WR
	movq	(%r12), %rax
	movq	16(%rax,%r15), %rsi
	movq	%r14, %rdi
	callq	_REG_RD
	movq	(%r12), %rcx
	movq	16(%rcx,%r15), %rsi
	movq	_write_arb_data@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	(%rcx,%r13,8), %rcx
	movl	8(%rcx,%rbx), %edx
	shll	$7, %edx
	orl	%eax, %edx
	movq	%r14, %rdi
	jmp	LBB0_16
LBB0_10:
	decq	%rax
	movl	-44(%rbp), %r14d                ## 4-byte Reload
	movslq	%r14d, %rdx
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movl	-60(%rbp), %r15d                ## 4-byte Reload
	jmp	LBB0_18
LBB0_17:
	movl	-44(%rbp), %r14d                ## 4-byte Reload
	movl	-60(%rbp), %r15d                ## 4-byte Reload
	movq	-88(%rbp), %rdx                 ## 8-byte Reload
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
LBB0_18:
	movq	_write_arb_data@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	(%rcx,%rax,8), %rax
	leaq	(%rdx,%rdx,2), %rcx
	movl	(%rax,%rcx,4), %edx
	movl	8(%rax,%rcx,4), %esi
	shll	$10, %esi
	addl	4(%rax,%rcx,4), %esi
	shll	$17, %edx
	addl	%esi, %edx
	movq	_PXP2_REG_PSWRQ_BW_RD@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	callq	_REG_WR
	movq	_read_arb_data@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_NUM_RD_Q@GOTPCREL(%rip), %rcx
	movslq	(%rcx), %rcx
	movq	-8(%rax,%rcx,8), %rax
	movq	-80(%rbp), %r12                 ## 8-byte Reload
	leaq	(%r12,%r12,2), %rcx
	movl	(%rax,%rcx,4), %edx
	movl	8(%rax,%rcx,4), %esi
	shll	$10, %esi
	addl	4(%rax,%rcx,4), %esi
	shll	$17, %edx
	addl	%esi, %edx
	movq	_PXP2_REG_PSWRQ_BW_WR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	callq	_REG_WR
	movq	_PXP2_REG_RQ_WR_MBS0@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	movl	%r14d, %edx
	callq	_REG_WR
	movq	_PXP2_REG_RQ_WR_MBS1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	movl	%r14d, %edx
	callq	_REG_WR
	movq	_PXP2_REG_RQ_RD_MBS0@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	movl	%r12d, %edx
	callq	_REG_WR
	movq	_PXP2_REG_RQ_RD_MBS1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	movl	%r12d, %edx
	callq	_REG_WR
	movq	%rbx, %rdi
	callq	_CHIP_IS_E1
	testq	%rax, %rax
	jne	LBB0_20
## %bb.19:
	movq	%rbx, %rdi
	callq	_CHIP_IS_E1H
	testq	%rax, %rax
	je	LBB0_22
LBB0_20:
	movq	_MAX_RD_ORD@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r15d
	jne	LBB0_22
## %bb.21:
	movq	_PXP2_REG_RQ_PDR_LIMIT@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	movl	$3584, %edx                     ## imm = 0xE00
	callq	_REG_WR
LBB0_22:
	movq	%rbx, %rdi
	callq	_CHIP_IS_E3
	movl	$4, %edx
	testq	%rax, %rax
	jne	LBB0_24
## %bb.23:
	movq	%rbx, %rdi
	callq	_CHIP_IS_E2
	xorl	%edx, %edx
	testq	%rax, %rax
	sete	%dl
	shll	$4, %edx
	orl	$8, %edx
LBB0_24:
	movq	_PXP2_REG_WR_USDMDP_TH@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movl	%r14d, %ecx
	shll	%cl, %edx
	movq	%rbx, %rdi
	callq	_REG_WR
	movq	%rbx, %rdi
	callq	_CHIP_IS_E1
	testq	%rax, %rax
	jne	LBB0_26
## %bb.25:
	movq	%rbx, %rdi
	callq	_CHIP_IS_E1H
	cmpl	$1, %r14d
	movl	$3, %r15d
	sbbl	$0, %r15d
	testq	%rax, %rax
	movl	$2, %edx
	cmovel	%r14d, %edx
	cmovel	%r14d, %r15d
	movq	_PXP2_REG_WR_DMAE_MPS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	callq	_REG_WR
	movq	_PXP2_REG_WR_HC_MPS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	movl	%r15d, %edx
	callq	_REG_WR
	movq	_PXP2_REG_WR_USDM_MPS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	movl	%r15d, %edx
	callq	_REG_WR
	movq	_PXP2_REG_WR_CSDM_MPS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	movl	%r15d, %edx
	callq	_REG_WR
	movq	_PXP2_REG_WR_TSDM_MPS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	movl	%r15d, %edx
	callq	_REG_WR
	movq	_PXP2_REG_WR_XSDM_MPS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	movl	%r15d, %edx
	callq	_REG_WR
	movq	_PXP2_REG_WR_QM_MPS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	movl	%r15d, %edx
	callq	_REG_WR
	movq	_PXP2_REG_WR_TM_MPS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	movl	%r15d, %edx
	callq	_REG_WR
	movq	_PXP2_REG_WR_SRC_MPS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	movl	%r15d, %edx
	callq	_REG_WR
	movq	_PXP2_REG_WR_DBG_MPS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	movl	%r15d, %edx
	callq	_REG_WR
	movq	_PXP2_REG_WR_CDU_MPS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	movl	%r15d, %edx
	callq	_REG_WR
LBB0_26:
	movl	$10624, %esi                    ## imm = 0x2980
	movq	%rbx, %rdi
	callq	_REG_RD
	movzbl	%al, %eax
	cmpl	$32, %eax
	ja	LBB0_27
## %bb.28:
	movq	_PXP2_REG_PGL_TAGS_LIMIT@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	movl	$32, %edx
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_REG_WR                         ## TAILCALL
LBB0_27:
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MAX_RD_ORD,4,2                 ## @MAX_RD_ORD
	.comm	_NETIF_MSG_HW,4,2               ## @NETIF_MSG_HW
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"read order of %d  order adjusted to %d\n"

	.comm	_MAX_WR_ORD,4,2                 ## @MAX_WR_ORD
L_.str.1:                               ## @.str.1
	.asciz	"write order of %d  order adjusted to %d\n"

L_.str.2:                               ## @.str.2
	.asciz	"write order adjusted to 1 for FPGA\n"

L_.str.3:                               ## @.str.3
	.asciz	"read order %d  write order %d\n"

	.comm	_NUM_RD_Q,4,2                   ## @NUM_RD_Q
	.comm	_read_arb_addr,8,3              ## @read_arb_addr
	.comm	_read_arb_data,8,3              ## @read_arb_data
	.comm	_NUM_WR_Q,4,2                   ## @NUM_WR_Q
	.comm	_write_arb_addr,8,3             ## @write_arb_addr
	.comm	_PXP2_REG_RQ_BW_WR_L29,8,3      ## @PXP2_REG_RQ_BW_WR_L29
	.comm	_PXP2_REG_RQ_BW_WR_L30,8,3      ## @PXP2_REG_RQ_BW_WR_L30
	.comm	_write_arb_data,8,3             ## @write_arb_data
	.comm	_PXP2_REG_PSWRQ_BW_RD,8,3       ## @PXP2_REG_PSWRQ_BW_RD
	.comm	_PXP2_REG_PSWRQ_BW_WR,8,3       ## @PXP2_REG_PSWRQ_BW_WR
	.comm	_PXP2_REG_RQ_WR_MBS0,8,3        ## @PXP2_REG_RQ_WR_MBS0
	.comm	_PXP2_REG_RQ_WR_MBS1,8,3        ## @PXP2_REG_RQ_WR_MBS1
	.comm	_PXP2_REG_RQ_RD_MBS0,8,3        ## @PXP2_REG_RQ_RD_MBS0
	.comm	_PXP2_REG_RQ_RD_MBS1,8,3        ## @PXP2_REG_RQ_RD_MBS1
	.comm	_PXP2_REG_RQ_PDR_LIMIT,8,3      ## @PXP2_REG_RQ_PDR_LIMIT
	.comm	_PXP2_REG_WR_USDMDP_TH,8,3      ## @PXP2_REG_WR_USDMDP_TH
	.comm	_PXP2_REG_WR_DMAE_MPS,8,3       ## @PXP2_REG_WR_DMAE_MPS
	.comm	_PXP2_REG_WR_HC_MPS,8,3         ## @PXP2_REG_WR_HC_MPS
	.comm	_PXP2_REG_WR_USDM_MPS,8,3       ## @PXP2_REG_WR_USDM_MPS
	.comm	_PXP2_REG_WR_CSDM_MPS,8,3       ## @PXP2_REG_WR_CSDM_MPS
	.comm	_PXP2_REG_WR_TSDM_MPS,8,3       ## @PXP2_REG_WR_TSDM_MPS
	.comm	_PXP2_REG_WR_XSDM_MPS,8,3       ## @PXP2_REG_WR_XSDM_MPS
	.comm	_PXP2_REG_WR_QM_MPS,8,3         ## @PXP2_REG_WR_QM_MPS
	.comm	_PXP2_REG_WR_TM_MPS,8,3         ## @PXP2_REG_WR_TM_MPS
	.comm	_PXP2_REG_WR_SRC_MPS,8,3        ## @PXP2_REG_WR_SRC_MPS
	.comm	_PXP2_REG_WR_DBG_MPS,8,3        ## @PXP2_REG_WR_DBG_MPS
	.comm	_PXP2_REG_WR_CDU_MPS,8,3        ## @PXP2_REG_WR_CDU_MPS
	.comm	_PXP2_REG_PGL_TAGS_LIMIT,8,3    ## @PXP2_REG_PGL_TAGS_LIMIT
	.comm	_PCIE_REG_PCIER_TL_HDR_FC_ST,8,3 ## @PCIE_REG_PCIER_TL_HDR_FC_ST
	.no_dead_strip	_bnx2x_init_pxp_arb
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function bnx2x_init_pxp_arb
_bnx2x_init_pxp_arb:                    ; @bnx2x_init_pxp_arb
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #128
	.cfi_def_cfa_offset 128
	stp	x28, x27, [sp, #32]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #48]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #64]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #80]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #96]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #112]            ; 16-byte Folded Spill
	add	x29, sp, #112
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x27, x2
	mov	x22, x1
	mov	x19, x0
Lloh0:
	adrp	x28, _MAX_RD_ORD@GOTPAGE
Lloh1:
	ldr	x28, [x28, _MAX_RD_ORD@GOTPAGEOFF]
	ldr	w8, [x28]
Lloh2:
	adrp	x20, _NETIF_MSG_HW@GOTPAGE
Lloh3:
	ldr	x20, [x20, _NETIF_MSG_HW@GOTPAGEOFF]
	cmp	w8, w1
	b.ge	LBB0_2
; %bb.1:
	ldr	w0, [x20]
	mov	x9, x22
	stp	x9, x8, [sp]
Lloh4:
	adrp	x1, l_.str@PAGE
Lloh5:
	add	x1, x1, l_.str@PAGEOFF
	bl	_DP
	ldr	w22, [x28]
LBB0_2:
Lloh6:
	adrp	x21, _MAX_WR_ORD@GOTPAGE
Lloh7:
	ldr	x21, [x21, _MAX_WR_ORD@GOTPAGEOFF]
	ldr	w8, [x21]
	cmp	w8, w27
	b.ge	LBB0_4
; %bb.3:
	ldr	w0, [x20]
	mov	x9, x27
	stp	x9, x8, [sp]
Lloh8:
	adrp	x1, l_.str.1@PAGE
Lloh9:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_DP
	ldr	w27, [x21]
LBB0_4:
	mov	x0, x19
	bl	_CHIP_REV_IS_FPGA
	cbz	x0, LBB0_6
; %bb.5:
	ldr	w0, [x20]
Lloh10:
	adrp	x1, l_.str.2@PAGE
Lloh11:
	add	x1, x1, l_.str.2@PAGEOFF
	bl	_DP
	mov	w27, #0
LBB0_6:
	ldr	w0, [x20]
	stp	x22, x27, [sp]
	str	x22, [sp, #24]                  ; 8-byte Folded Spill
Lloh12:
	adrp	x1, l_.str.3@PAGE
Lloh13:
	add	x1, x1, l_.str.3@PAGEOFF
	bl	_DP
Lloh14:
	adrp	x8, _NUM_RD_Q@GOTPAGE
Lloh15:
	ldr	x8, [x8, _NUM_RD_Q@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
Lloh17:
	adrp	x24, _read_arb_data@GOTPAGE
Lloh18:
	ldr	x24, [x24, _read_arb_data@GOTPAGEOFF]
	cmp	w8, #2
	b.lt	LBB0_9
; %bb.7:
	mov	x20, #0
	mov	x21, #0
	ldr	x8, [sp, #24]                   ; 8-byte Folded Reload
                                        ; kill: def $w8 killed $w8 killed $x8 def $x8
	sxtw	x22, w8
Lloh19:
	adrp	x23, _read_arb_addr@GOTPAGE
Lloh20:
	ldr	x23, [x23, _read_arb_addr@GOTPAGEOFF]
LBB0_8:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x23]
	ldr	x1, [x8, x20]
	ldr	x8, [x24]
	lsl	x25, x21, #3
	ldr	x8, [x8, x25]
	add	x9, x22, x22, lsl #1
	lsl	x26, x9, #2
	ldr	w2, [x8, x26]
	mov	x0, x19
	bl	_REG_WR
	ldr	x8, [x23]
	add	x8, x8, x20
	ldr	x1, [x8, #8]
	ldr	x8, [x24]
	ldr	x8, [x8, x25]
	add	x8, x8, x26
	ldr	w2, [x8, #4]
	mov	x0, x19
	bl	_REG_WR
	ldr	x8, [x23]
	add	x8, x8, x20
	ldr	x1, [x8, #16]
	ldr	x8, [x24]
	ldr	x8, [x8, x25]
	add	x8, x8, x26
	ldr	w2, [x8, #8]
	mov	x0, x19
	bl	_REG_WR
	add	x21, x21, #1
Lloh21:
	adrp	x8, _NUM_RD_Q@GOTPAGE
Lloh22:
	ldr	x8, [x8, _NUM_RD_Q@GOTPAGEOFF]
Lloh23:
	ldrsw	x8, [x8]
	sub	x8, x8, #1
	add	x20, x20, #24
	cmp	x21, x8
	b.lt	LBB0_8
LBB0_9:
Lloh24:
	adrp	x8, _NUM_WR_Q@GOTPAGE
Lloh25:
	ldr	x8, [x8, _NUM_WR_Q@GOTPAGEOFF]
Lloh26:
	ldrsw	x8, [x8]
Lloh27:
	adrp	x25, _write_arb_data@GOTPAGE
Lloh28:
	ldr	x25, [x25, _write_arb_data@GOTPAGEOFF]
	cmp	w8, #1
	b.le	LBB0_15
; %bb.10:
	mov	x28, #0
	mov	x22, #0
	str	x27, [sp, #16]                  ; 8-byte Folded Spill
	mov	x8, x27
	sxtw	x26, w8
Lloh29:
	adrp	x21, _write_arb_addr@GOTPAGE
Lloh30:
	ldr	x21, [x21, _write_arb_addr@GOTPAGEOFF]
Lloh31:
	adrp	x23, _PXP2_REG_RQ_BW_WR_L30@GOTPAGE
Lloh32:
	ldr	x23, [x23, _PXP2_REG_RQ_BW_WR_L30@GOTPAGEOFF]
	b	LBB0_13
LBB0_11:                                ;   in Loop: Header=BB0_13 Depth=1
	mov	x0, x19
	bl	_REG_RD
	ldr	x8, [x21]
	ldr	x1, [x8, x28]
	ldr	x8, [x25]
	lsl	x20, x22, #3
	ldr	x8, [x8, x20]
	add	x9, x26, x26, lsl #1
	lsl	x27, x9, #2
	ldr	w8, [x8, x27]
	orr	w2, w0, w8, lsl #10
	mov	x0, x19
	bl	_REG_WR
	ldr	x8, [x21]
	add	x8, x8, x28
	ldr	x1, [x8, #8]
	mov	x0, x19
	bl	_REG_RD
	ldr	x8, [x21]
	add	x8, x8, x28
	ldr	x1, [x8, #8]
	ldr	x8, [x25]
	ldr	x8, [x8, x20]
	add	x8, x8, x27
	ldr	w8, [x8, #4]
	orr	w2, w0, w8, lsl #10
	mov	x0, x19
	bl	_REG_WR
	ldr	x8, [x21]
	add	x8, x8, x28
	ldr	x1, [x8, #16]
	mov	x0, x19
	bl	_REG_RD
	ldr	x8, [x21]
	add	x8, x8, x28
	ldr	x1, [x8, #16]
	ldr	x8, [x25]
	ldr	x8, [x8, x20]
	add	x8, x8, x27
	ldr	w8, [x8, #8]
	orr	w2, w0, w8, lsl #7
LBB0_12:                                ;   in Loop: Header=BB0_13 Depth=1
	mov	x0, x19
	bl	_REG_WR
	add	x22, x22, #1
Lloh33:
	adrp	x8, _NUM_WR_Q@GOTPAGE
Lloh34:
	ldr	x8, [x8, _NUM_WR_Q@GOTPAGEOFF]
Lloh35:
	ldrsw	x8, [x8]
	sub	x8, x8, #1
	add	x28, x28, #24
	cmp	x22, x8
	b.ge	LBB0_16
LBB0_13:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x21]
	ldr	x1, [x8, x28]
Lloh36:
	adrp	x8, _PXP2_REG_RQ_BW_WR_L29@GOTPAGE
Lloh37:
	ldr	x8, [x8, _PXP2_REG_RQ_BW_WR_L29@GOTPAGEOFF]
Lloh38:
	ldr	x8, [x8]
	ldr	x9, [x23]
	cmp	x1, x8
	ccmp	x1, x9, #4, ne
	b.ne	LBB0_11
; %bb.14:                               ;   in Loop: Header=BB0_13 Depth=1
	ldr	x8, [x25]
	lsl	x20, x22, #3
	ldr	x8, [x8, x20]
	add	x9, x26, x26, lsl #1
	lsl	x27, x9, #2
	ldr	w2, [x8, x27]
	mov	x0, x19
	bl	_REG_WR
	ldr	x8, [x21]
	add	x8, x8, x28
	ldr	x1, [x8, #8]
	ldr	x8, [x25]
	ldr	x8, [x8, x20]
	add	x8, x8, x27
	ldr	w2, [x8, #4]
	mov	x0, x19
	bl	_REG_WR
	ldr	x8, [x21]
	add	x8, x8, x28
	ldr	x1, [x8, #16]
	ldr	x8, [x25]
	ldr	x8, [x8, x20]
	add	x8, x8, x27
	ldr	w2, [x8, #8]
	b	LBB0_12
LBB0_15:
	sub	x8, x8, #1
	mov	x9, x27
	sxtw	x26, w9
	b	LBB0_17
LBB0_16:
	ldr	x27, [sp, #16]                  ; 8-byte Folded Reload
Lloh39:
	adrp	x28, _MAX_RD_ORD@GOTPAGE
Lloh40:
	ldr	x28, [x28, _MAX_RD_ORD@GOTPAGEOFF]
LBB0_17:
	ldr	x9, [x25]
	ldr	x8, [x9, x8, lsl #3]
	mov	w20, #12
	madd	x8, x26, x20, x8
	ldp	w10, w9, [x8, #4]
	ldr	w8, [x8]
	add	w9, w10, w9, lsl #10
	add	w2, w9, w8, lsl #17
Lloh41:
	adrp	x8, _PXP2_REG_PSWRQ_BW_RD@GOTPAGE
Lloh42:
	ldr	x8, [x8, _PXP2_REG_PSWRQ_BW_RD@GOTPAGEOFF]
Lloh43:
	ldr	x1, [x8]
	mov	x0, x19
	bl	_REG_WR
	ldr	x8, [x24]
Lloh44:
	adrp	x9, _NUM_RD_Q@GOTPAGE
Lloh45:
	ldr	x9, [x9, _NUM_RD_Q@GOTPAGEOFF]
Lloh46:
	ldrsw	x9, [x9]
	add	x8, x8, x9, lsl #3
	ldur	x8, [x8, #-8]
	ldr	x21, [sp, #24]                  ; 8-byte Folded Reload
	smaddl	x8, w21, w20, x8
	ldp	w10, w9, [x8, #4]
	ldr	w8, [x8]
	add	w9, w10, w9, lsl #10
	add	w2, w9, w8, lsl #17
Lloh47:
	adrp	x8, _PXP2_REG_PSWRQ_BW_WR@GOTPAGE
Lloh48:
	ldr	x8, [x8, _PXP2_REG_PSWRQ_BW_WR@GOTPAGEOFF]
Lloh49:
	ldr	x1, [x8]
	mov	x0, x19
	bl	_REG_WR
Lloh50:
	adrp	x8, _PXP2_REG_RQ_WR_MBS0@GOTPAGE
Lloh51:
	ldr	x8, [x8, _PXP2_REG_RQ_WR_MBS0@GOTPAGEOFF]
Lloh52:
	ldr	x1, [x8]
	mov	x0, x19
	mov	x2, x27
	bl	_REG_WR
Lloh53:
	adrp	x8, _PXP2_REG_RQ_WR_MBS1@GOTPAGE
Lloh54:
	ldr	x8, [x8, _PXP2_REG_RQ_WR_MBS1@GOTPAGEOFF]
Lloh55:
	ldr	x1, [x8]
	mov	x0, x19
	mov	x2, x27
	bl	_REG_WR
Lloh56:
	adrp	x8, _PXP2_REG_RQ_RD_MBS0@GOTPAGE
Lloh57:
	ldr	x8, [x8, _PXP2_REG_RQ_RD_MBS0@GOTPAGEOFF]
Lloh58:
	ldr	x1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_REG_WR
Lloh59:
	adrp	x8, _PXP2_REG_RQ_RD_MBS1@GOTPAGE
Lloh60:
	ldr	x8, [x8, _PXP2_REG_RQ_RD_MBS1@GOTPAGEOFF]
Lloh61:
	ldr	x1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_REG_WR
	mov	x0, x19
	bl	_CHIP_IS_E1
	cbnz	x0, LBB0_19
; %bb.18:
	mov	x0, x19
	bl	_CHIP_IS_E1H
	cbz	x0, LBB0_21
LBB0_19:
	ldr	w8, [x28]
	cmp	w21, w8
	b.ne	LBB0_21
; %bb.20:
Lloh62:
	adrp	x8, _PXP2_REG_RQ_PDR_LIMIT@GOTPAGE
Lloh63:
	ldr	x8, [x8, _PXP2_REG_RQ_PDR_LIMIT@GOTPAGEOFF]
Lloh64:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #3584
	bl	_REG_WR
LBB0_21:
	mov	x0, x19
	bl	_CHIP_IS_E3
	cbz	x0, LBB0_23
; %bb.22:
	mov	w8, #4
	b	LBB0_24
LBB0_23:
	mov	x0, x19
	bl	_CHIP_IS_E2
	cmp	x0, #0
	mov	w8, #8
	mov	w9, #24
	csel	w8, w9, w8, eq
LBB0_24:
Lloh65:
	adrp	x9, _PXP2_REG_WR_USDMDP_TH@GOTPAGE
Lloh66:
	ldr	x9, [x9, _PXP2_REG_WR_USDMDP_TH@GOTPAGEOFF]
Lloh67:
	ldr	x1, [x9]
	lsl	w2, w8, w27
	mov	x0, x19
	bl	_REG_WR
	mov	x0, x19
	bl	_CHIP_IS_E1
	cbnz	x0, LBB0_26
; %bb.25:
	mov	x0, x19
	bl	_CHIP_IS_E1H
	cmp	w27, #0
	mov	w8, #2
	cinc	w9, w8, ne
	cmp	x0, #0
	csel	w2, w27, w8, eq
	csel	w20, w27, w9, eq
Lloh68:
	adrp	x8, _PXP2_REG_WR_DMAE_MPS@GOTPAGE
Lloh69:
	ldr	x8, [x8, _PXP2_REG_WR_DMAE_MPS@GOTPAGEOFF]
Lloh70:
	ldr	x1, [x8]
	mov	x0, x19
	bl	_REG_WR
Lloh71:
	adrp	x8, _PXP2_REG_WR_HC_MPS@GOTPAGE
Lloh72:
	ldr	x8, [x8, _PXP2_REG_WR_HC_MPS@GOTPAGEOFF]
Lloh73:
	ldr	x1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_REG_WR
Lloh74:
	adrp	x8, _PXP2_REG_WR_USDM_MPS@GOTPAGE
Lloh75:
	ldr	x8, [x8, _PXP2_REG_WR_USDM_MPS@GOTPAGEOFF]
Lloh76:
	ldr	x1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_REG_WR
Lloh77:
	adrp	x8, _PXP2_REG_WR_CSDM_MPS@GOTPAGE
Lloh78:
	ldr	x8, [x8, _PXP2_REG_WR_CSDM_MPS@GOTPAGEOFF]
Lloh79:
	ldr	x1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_REG_WR
Lloh80:
	adrp	x8, _PXP2_REG_WR_TSDM_MPS@GOTPAGE
Lloh81:
	ldr	x8, [x8, _PXP2_REG_WR_TSDM_MPS@GOTPAGEOFF]
Lloh82:
	ldr	x1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_REG_WR
Lloh83:
	adrp	x8, _PXP2_REG_WR_XSDM_MPS@GOTPAGE
Lloh84:
	ldr	x8, [x8, _PXP2_REG_WR_XSDM_MPS@GOTPAGEOFF]
Lloh85:
	ldr	x1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_REG_WR
Lloh86:
	adrp	x8, _PXP2_REG_WR_QM_MPS@GOTPAGE
Lloh87:
	ldr	x8, [x8, _PXP2_REG_WR_QM_MPS@GOTPAGEOFF]
Lloh88:
	ldr	x1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_REG_WR
Lloh89:
	adrp	x8, _PXP2_REG_WR_TM_MPS@GOTPAGE
Lloh90:
	ldr	x8, [x8, _PXP2_REG_WR_TM_MPS@GOTPAGEOFF]
Lloh91:
	ldr	x1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_REG_WR
Lloh92:
	adrp	x8, _PXP2_REG_WR_SRC_MPS@GOTPAGE
Lloh93:
	ldr	x8, [x8, _PXP2_REG_WR_SRC_MPS@GOTPAGEOFF]
Lloh94:
	ldr	x1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_REG_WR
Lloh95:
	adrp	x8, _PXP2_REG_WR_DBG_MPS@GOTPAGE
Lloh96:
	ldr	x8, [x8, _PXP2_REG_WR_DBG_MPS@GOTPAGEOFF]
Lloh97:
	ldr	x1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_REG_WR
Lloh98:
	adrp	x8, _PXP2_REG_WR_CDU_MPS@GOTPAGE
Lloh99:
	ldr	x8, [x8, _PXP2_REG_WR_CDU_MPS@GOTPAGEOFF]
Lloh100:
	ldr	x1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_REG_WR
LBB0_26:
	mov	x0, x19
	mov	w1, #10624
	bl	_REG_RD
	and	w8, w0, #0xff
	cmp	w8, #32
	b.hi	LBB0_28
; %bb.27:
Lloh101:
	adrp	x8, _PXP2_REG_PGL_TAGS_LIMIT@GOTPAGE
Lloh102:
	ldr	x8, [x8, _PXP2_REG_PGL_TAGS_LIMIT@GOTPAGEOFF]
Lloh103:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #32
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	b	_REG_WR
LBB0_28:
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	ret
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpAdd	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.cfi_endproc
                                        ; -- End function
	.comm	_MAX_RD_ORD,4,2                 ; @MAX_RD_ORD
	.comm	_NETIF_MSG_HW,4,2               ; @NETIF_MSG_HW
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"read order of %d  order adjusted to %d\n"

	.comm	_MAX_WR_ORD,4,2                 ; @MAX_WR_ORD
l_.str.1:                               ; @.str.1
	.asciz	"write order of %d  order adjusted to %d\n"

l_.str.2:                               ; @.str.2
	.asciz	"write order adjusted to 1 for FPGA\n"

l_.str.3:                               ; @.str.3
	.asciz	"read order %d  write order %d\n"

	.comm	_NUM_RD_Q,4,2                   ; @NUM_RD_Q
	.comm	_read_arb_addr,8,3              ; @read_arb_addr
	.comm	_read_arb_data,8,3              ; @read_arb_data
	.comm	_NUM_WR_Q,4,2                   ; @NUM_WR_Q
	.comm	_write_arb_addr,8,3             ; @write_arb_addr
	.comm	_PXP2_REG_RQ_BW_WR_L29,8,3      ; @PXP2_REG_RQ_BW_WR_L29
	.comm	_PXP2_REG_RQ_BW_WR_L30,8,3      ; @PXP2_REG_RQ_BW_WR_L30
	.comm	_write_arb_data,8,3             ; @write_arb_data
	.comm	_PXP2_REG_PSWRQ_BW_RD,8,3       ; @PXP2_REG_PSWRQ_BW_RD
	.comm	_PXP2_REG_PSWRQ_BW_WR,8,3       ; @PXP2_REG_PSWRQ_BW_WR
	.comm	_PXP2_REG_RQ_WR_MBS0,8,3        ; @PXP2_REG_RQ_WR_MBS0
	.comm	_PXP2_REG_RQ_WR_MBS1,8,3        ; @PXP2_REG_RQ_WR_MBS1
	.comm	_PXP2_REG_RQ_RD_MBS0,8,3        ; @PXP2_REG_RQ_RD_MBS0
	.comm	_PXP2_REG_RQ_RD_MBS1,8,3        ; @PXP2_REG_RQ_RD_MBS1
	.comm	_PXP2_REG_RQ_PDR_LIMIT,8,3      ; @PXP2_REG_RQ_PDR_LIMIT
	.comm	_PXP2_REG_WR_USDMDP_TH,8,3      ; @PXP2_REG_WR_USDMDP_TH
	.comm	_PXP2_REG_WR_DMAE_MPS,8,3       ; @PXP2_REG_WR_DMAE_MPS
	.comm	_PXP2_REG_WR_HC_MPS,8,3         ; @PXP2_REG_WR_HC_MPS
	.comm	_PXP2_REG_WR_USDM_MPS,8,3       ; @PXP2_REG_WR_USDM_MPS
	.comm	_PXP2_REG_WR_CSDM_MPS,8,3       ; @PXP2_REG_WR_CSDM_MPS
	.comm	_PXP2_REG_WR_TSDM_MPS,8,3       ; @PXP2_REG_WR_TSDM_MPS
	.comm	_PXP2_REG_WR_XSDM_MPS,8,3       ; @PXP2_REG_WR_XSDM_MPS
	.comm	_PXP2_REG_WR_QM_MPS,8,3         ; @PXP2_REG_WR_QM_MPS
	.comm	_PXP2_REG_WR_TM_MPS,8,3         ; @PXP2_REG_WR_TM_MPS
	.comm	_PXP2_REG_WR_SRC_MPS,8,3        ; @PXP2_REG_WR_SRC_MPS
	.comm	_PXP2_REG_WR_DBG_MPS,8,3        ; @PXP2_REG_WR_DBG_MPS
	.comm	_PXP2_REG_WR_CDU_MPS,8,3        ; @PXP2_REG_WR_CDU_MPS
	.comm	_PXP2_REG_PGL_TAGS_LIMIT,8,3    ; @PXP2_REG_PGL_TAGS_LIMIT
	.comm	_PCIE_REG_PCIER_TL_HDR_FC_ST,8,3 ; @PCIE_REG_PCIER_TL_HDR_FC_ST
	.no_dead_strip	_bnx2x_init_pxp_arb
.subsections_via_symbols
