	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gen6_ring_flush
_gen6_ring_flush:                       ## @gen6_ring_flush
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r15d
	movq	%rdi, %rbx
	movl	$4, %esi
	callq	_intel_ring_begin
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	LBB0_4
## %bb.1:
	movq	_MI_FLUSH_DW@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_I915_GEM_GPU_DOMAINS@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_3
## %bb.2:
	movq	_MI_INVALIDATE_TLB@GOTPCREL(%rip), %rax
	movq	_MI_INVALIDATE_BSD@GOTPCREL(%rip), %rcx
	movq	_MI_FLUSH_DW_STORE_INDEX@GOTPCREL(%rip), %rdx
	movq	_MI_FLUSH_DW_OP_STOREDW@GOTPCREL(%rip), %rdi
	orl	(%rax), %esi
	orl	(%rcx), %esi
	orl	(%rdx), %esi
	orl	(%rdi), %esi
LBB0_3:
	movq	%rbx, %rdi
	callq	_intel_ring_emit
	movq	_I915_GEM_HWS_SCRATCH_ADDR@GOTPCREL(%rip), %rax
	movq	_MI_FLUSH_DW_USE_GTT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_intel_ring_emit
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_intel_ring_emit
	movq	_MI_NOOP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_intel_ring_emit
	movq	%rbx, %rdi
	callq	_intel_ring_advance
LBB0_4:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MI_FLUSH_DW,4,2                ## @MI_FLUSH_DW
	.comm	_I915_GEM_GPU_DOMAINS,4,2       ## @I915_GEM_GPU_DOMAINS
	.comm	_MI_INVALIDATE_TLB,4,2          ## @MI_INVALIDATE_TLB
	.comm	_MI_INVALIDATE_BSD,4,2          ## @MI_INVALIDATE_BSD
	.comm	_MI_FLUSH_DW_STORE_INDEX,4,2    ## @MI_FLUSH_DW_STORE_INDEX
	.comm	_MI_FLUSH_DW_OP_STOREDW,4,2     ## @MI_FLUSH_DW_OP_STOREDW
	.comm	_I915_GEM_HWS_SCRATCH_ADDR,4,2  ## @I915_GEM_HWS_SCRATCH_ADDR
	.comm	_MI_FLUSH_DW_USE_GTT,4,2        ## @MI_FLUSH_DW_USE_GTT
	.comm	_MI_NOOP,4,2                    ## @MI_NOOP
	.no_dead_strip	_gen6_ring_flush
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gen6_ring_flush
_gen6_ring_flush:                       ; @gen6_ring_flush
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x21, x1
	mov	x19, x0
	mov	w1, #4
	bl	_intel_ring_begin
	mov	x20, x0
	cbnz	w0, LBB0_4
; %bb.1:
Lloh0:
	adrp	x8, _MI_FLUSH_DW@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MI_FLUSH_DW@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
Lloh3:
	adrp	x8, _I915_GEM_GPU_DOMAINS@GOTPAGE
Lloh4:
	ldr	x8, [x8, _I915_GEM_GPU_DOMAINS@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	tst	w8, w21
	b.eq	LBB0_3
; %bb.2:
Lloh6:
	adrp	x8, _MI_INVALIDATE_TLB@GOTPAGE
Lloh7:
	ldr	x8, [x8, _MI_INVALIDATE_TLB@GOTPAGEOFF]
Lloh8:
	adrp	x9, _MI_INVALIDATE_BSD@GOTPAGE
Lloh9:
	ldr	x9, [x9, _MI_INVALIDATE_BSD@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
Lloh11:
	ldr	w9, [x9]
Lloh12:
	adrp	x10, _MI_FLUSH_DW_STORE_INDEX@GOTPAGE
Lloh13:
	ldr	x10, [x10, _MI_FLUSH_DW_STORE_INDEX@GOTPAGEOFF]
Lloh14:
	adrp	x11, _MI_FLUSH_DW_OP_STOREDW@GOTPAGE
Lloh15:
	ldr	x11, [x11, _MI_FLUSH_DW_OP_STOREDW@GOTPAGEOFF]
Lloh16:
	ldr	w10, [x10]
Lloh17:
	ldr	w11, [x11]
	orr	w8, w8, w1
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w1, w8, w11
LBB0_3:
	mov	x0, x19
	bl	_intel_ring_emit
Lloh18:
	adrp	x8, _I915_GEM_HWS_SCRATCH_ADDR@GOTPAGE
Lloh19:
	ldr	x8, [x8, _I915_GEM_HWS_SCRATCH_ADDR@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
Lloh21:
	adrp	x9, _MI_FLUSH_DW_USE_GTT@GOTPAGE
Lloh22:
	ldr	x9, [x9, _MI_FLUSH_DW_USE_GTT@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	orr	w1, w9, w8
	mov	x0, x19
	bl	_intel_ring_emit
	mov	x0, x19
	mov	w1, #0
	bl	_intel_ring_emit
Lloh24:
	adrp	x8, _MI_NOOP@GOTPAGE
Lloh25:
	ldr	x8, [x8, _MI_NOOP@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_intel_ring_emit
	mov	x0, x19
	bl	_intel_ring_advance
LBB0_4:
	mov	x0, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh16
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh10
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.cfi_endproc
                                        ; -- End function
	.comm	_MI_FLUSH_DW,4,2                ; @MI_FLUSH_DW
	.comm	_I915_GEM_GPU_DOMAINS,4,2       ; @I915_GEM_GPU_DOMAINS
	.comm	_MI_INVALIDATE_TLB,4,2          ; @MI_INVALIDATE_TLB
	.comm	_MI_INVALIDATE_BSD,4,2          ; @MI_INVALIDATE_BSD
	.comm	_MI_FLUSH_DW_STORE_INDEX,4,2    ; @MI_FLUSH_DW_STORE_INDEX
	.comm	_MI_FLUSH_DW_OP_STOREDW,4,2     ; @MI_FLUSH_DW_OP_STOREDW
	.comm	_I915_GEM_HWS_SCRATCH_ADDR,4,2  ; @I915_GEM_HWS_SCRATCH_ADDR
	.comm	_MI_FLUSH_DW_USE_GTT,4,2        ; @MI_FLUSH_DW_USE_GTT
	.comm	_MI_NOOP,4,2                    ; @MI_NOOP
	.no_dead_strip	_gen6_ring_flush
.subsections_via_symbols
