	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_intel_dp_start_link_train      ## -- Begin function intel_dp_start_link_train
	.p2align	4, 0x90
_intel_dp_start_link_train:             ## @intel_dp_start_link_train
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -48(%rbp)
	callq	_dp_to_dig_port
	movq	%rax, %r14
	movq	(%rax), %rdi
	movl	12(%r15), %ebx
	callq	_HAS_DDI
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	%r14, %rdi
	callq	_intel_ddi_prepare_link_retrain
LBB0_2:
	movq	_DP_LINK_BW_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	20(%r15), %edx
	movq	_DP_LINK_CONFIGURATION_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r15, %rdi
	callq	_intel_dp_aux_native_write
	movq	_DP_PORT_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	%ebx, -52(%rbp)
	movq	(%r15), %rdi
	xorl	%r13d, %r13d
	xorl	%esi, %esi
	movl	$4, %edx
	callq	_memset
	movq	%rsp, %r14
	movq	_DP_LINK_STATUS_SIZE@GOTPCREL(%rip), %r12
	movl	(%r12), %eax
	shlq	$2, %rax
	callq	____chkstk_darwin
	addq	$15, %rax
	andq	$-16, %rax
	subq	%rax, %rsp
	movq	%rsp, %rbx
	leaq	-52(%rbp), %rsi
	movq	%r15, %rdi
	callq	_intel_dp_set_signal_levels
	movl	-52(%rbp), %esi
	movq	_DP_TRAINING_PATTERN_1@GOTPCREL(%rip), %rax
	movq	_DP_LINK_SCRAMBLING_DISABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	%r15, %rdi
	callq	_intel_dp_set_link_train
	testl	%eax, %eax
	je	LBB0_23
## %bb.3:
	movl	$255, -60(%rbp)                 ## 4-byte Folded Spill
	movl	$0, -56(%rbp)                   ## 4-byte Folded Spill
	jmp	LBB0_6
	.p2align	4, 0x90
LBB0_4:                                 ##   in Loop: Header=BB0_6 Depth=1
	movq	%r15, %rdi
	movq	%rbx, %rsi
	callq	_intel_get_adjust_train
	movl	%r12d, -56(%rbp)                ## 4-byte Spill
	movl	%r14d, -60(%rbp)                ## 4-byte Spill
	movq	-72(%rbp), %r14                 ## 8-byte Reload
	movq	_DP_LINK_STATUS_SIZE@GOTPCREL(%rip), %r12
LBB0_5:                                 ##   in Loop: Header=BB0_6 Depth=1
	movq	%r14, %rsp
	movq	%rsp, %r14
	movl	(%r12), %eax
	shlq	$2, %rax
	callq	____chkstk_darwin
	addq	$15, %rax
	andq	$-16, %rax
	subq	%rax, %rsp
	movq	%rsp, %rbx
	movq	%r15, %rdi
	leaq	-52(%rbp), %rsi
	callq	_intel_dp_set_signal_levels
	movl	-52(%rbp), %esi
	movq	_DP_LINK_SCRAMBLING_DISABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_DP_TRAINING_PATTERN_1@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	%r15, %rdi
	callq	_intel_dp_set_link_train
	testl	%eax, %eax
	je	LBB0_23
LBB0_6:                                 ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_10 Depth 2
	movl	16(%r15), %edi
	callq	_drm_dp_link_train_clock_recovery_delay
	movq	%r15, %rdi
	movq	%rbx, %rsi
	callq	_intel_dp_get_link_status
	testl	%eax, %eax
	je	LBB0_19
## %bb.7:                               ##   in Loop: Header=BB0_6 Depth=1
	movl	8(%r15), %esi
	movq	%rbx, %rdi
	callq	_drm_dp_clock_recovery_ok
	testq	%rax, %rax
	jne	LBB0_20
## %bb.8:                               ##   in Loop: Header=BB0_6 Depth=1
	movl	8(%r15), %eax
	testl	%eax, %eax
	jle	LBB0_12
## %bb.9:                               ##   in Loop: Header=BB0_6 Depth=1
	movq	(%r15), %rdx
	movq	_DP_TRAIN_MAX_SWING_REACHED@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	xorl	%ecx, %ecx
	.p2align	4, 0x90
LBB0_10:                                ##   Parent Loop BB0_6 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	testl	%esi, (%rdx,%rcx,4)
	je	LBB0_13
## %bb.11:                              ##   in Loop: Header=BB0_10 Depth=2
	incq	%rcx
	cmpq	%rcx, %rax
	jne	LBB0_10
	jmp	LBB0_14
	.p2align	4, 0x90
LBB0_12:                                ##   in Loop: Header=BB0_6 Depth=1
	xorl	%ecx, %ecx
LBB0_13:                                ##   in Loop: Header=BB0_6 Depth=1
	cmpl	%eax, %ecx
	jne	LBB0_16
LBB0_14:                                ##   in Loop: Header=BB0_6 Depth=1
	incl	%r13d
	cmpl	$5, %r13d
	je	LBB0_21
## %bb.15:                              ##   in Loop: Header=BB0_6 Depth=1
	movq	(%r15), %rdi
	movl	$0, -56(%rbp)                   ## 4-byte Folded Spill
	xorl	%esi, %esi
	movl	$4, %edx
	callq	_memset
	jmp	LBB0_5
	.p2align	4, 0x90
LBB0_16:                                ##   in Loop: Header=BB0_6 Depth=1
	movq	%r14, -72(%rbp)                 ## 8-byte Spill
	movq	(%r15), %rax
	movq	_DP_TRAIN_VOLTAGE_SWING_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r14d
	andl	(%rax), %r14d
	xorl	%r12d, %r12d
	cmpl	-60(%rbp), %r14d                ## 4-byte Folded Reload
	jne	LBB0_4
## %bb.17:                              ##   in Loop: Header=BB0_6 Depth=1
	movl	-56(%rbp), %eax                 ## 4-byte Reload
	incl	%eax
	movl	%eax, %r12d
	cmpl	$5, %eax
	jne	LBB0_4
## %bb.18:
	leaq	L_.str.3(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	movq	-72(%rbp), %r14                 ## 8-byte Reload
	jmp	LBB0_23
LBB0_19:
	leaq	L_.str(%rip), %rdi
	callq	_DRM_ERROR
	jmp	LBB0_23
LBB0_20:
	leaq	L_.str.1(%rip), %rdi
	jmp	LBB0_22
LBB0_21:
	leaq	L_.str.2(%rip), %rdi
LBB0_22:
	callq	_DRM_DEBUG_KMS
LBB0_23:
	movq	%r14, %rsp
	movl	-52(%rbp), %eax
	movl	%eax, 12(%r15)
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	cmpq	-48(%rbp), %rax
	jne	LBB0_25
## %bb.24:
	leaq	-40(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_25:
	callq	___stack_chk_fail
	.cfi_endproc
                                        ## -- End function
	.comm	_DP_LINK_BW_SET,4,2             ## @DP_LINK_BW_SET
	.comm	_DP_LINK_CONFIGURATION_SIZE,4,2 ## @DP_LINK_CONFIGURATION_SIZE
	.comm	_DP_PORT_EN,4,2                 ## @DP_PORT_EN
	.comm	_DP_LINK_STATUS_SIZE,4,2        ## @DP_LINK_STATUS_SIZE
	.comm	_DP_TRAINING_PATTERN_1,4,2      ## @DP_TRAINING_PATTERN_1
	.comm	_DP_LINK_SCRAMBLING_DISABLE,4,2 ## @DP_LINK_SCRAMBLING_DISABLE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"failed to get link status\n"

L_.str.1:                               ## @.str.1
	.asciz	"clock recovery OK\n"

	.comm	_DP_TRAIN_MAX_SWING_REACHED,4,2 ## @DP_TRAIN_MAX_SWING_REACHED
L_.str.2:                               ## @.str.2
	.asciz	"too many full retries, give up\n"

	.comm	_DP_TRAIN_VOLTAGE_SWING_MASK,4,2 ## @DP_TRAIN_VOLTAGE_SWING_MASK
L_.str.3:                               ## @.str.3
	.asciz	"too many voltage retries, give up\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_intel_dp_start_link_train      ; -- Begin function intel_dp_start_link_train
	.p2align	2
_intel_dp_start_link_train:             ; @intel_dp_start_link_train
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	sub	sp, sp, #16
	mov	x19, x0
Lloh0:
	adrp	x8, ___stack_chk_guard@GOTPAGE
Lloh1:
	ldr	x8, [x8, ___stack_chk_guard@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	stur	x8, [x29, #-88]
	bl	_dp_to_dig_port
	mov	x20, x0
	ldr	x0, [x0]
	ldr	w21, [x19, #12]
	bl	_HAS_DDI
	cbz	x0, LBB0_2
; %bb.1:
	mov	x0, x20
	bl	_intel_ddi_prepare_link_retrain
LBB0_2:
Lloh3:
	adrp	x8, _DP_LINK_BW_SET@GOTPAGE
Lloh4:
	ldr	x8, [x8, _DP_LINK_BW_SET@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	ldr	w2, [x19, #20]
Lloh6:
	adrp	x8, _DP_LINK_CONFIGURATION_SIZE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _DP_LINK_CONFIGURATION_SIZE@GOTPAGEOFF]
Lloh8:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_intel_dp_aux_native_write
Lloh9:
	adrp	x8, _DP_PORT_EN@GOTPAGE
Lloh10:
	ldr	x8, [x8, _DP_PORT_EN@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	orr	w8, w21, w8
	stur	w8, [x29, #-92]
	ldr	x0, [x19]
	mov	w1, #0
	mov	w2, #4
	bl	_memset
	mov	x21, sp
Lloh12:
	adrp	x22, _DP_LINK_STATUS_SIZE@GOTPAGE
Lloh13:
	ldr	x22, [x22, _DP_LINK_STATUS_SIZE@GOTPAGEOFF]
	ldr	w8, [x22]
	lsl	x8, x8, #2
	mov	x9, x8
Lloh14:
	adrp	x16, ___chkstk_darwin@GOTPAGE
Lloh15:
	ldr	x16, [x16, ___chkstk_darwin@GOTPAGEOFF]
	blr	x16
	mov	x9, sp
	add	x8, x8, #15
	and	x8, x8, #0x7fffffff0
	sub	x20, x9, x8
	mov	sp, x20
	sub	x1, x29, #92
	mov	x0, x19
	bl	_intel_dp_set_signal_levels
Lloh16:
	adrp	x23, _DP_TRAINING_PATTERN_1@GOTPAGE
Lloh17:
	ldr	x23, [x23, _DP_TRAINING_PATTERN_1@GOTPAGEOFF]
	ldur	w1, [x29, #-92]
	ldr	w8, [x23]
Lloh18:
	adrp	x26, _DP_LINK_SCRAMBLING_DISABLE@GOTPAGE
Lloh19:
	ldr	x26, [x26, _DP_LINK_SCRAMBLING_DISABLE@GOTPAGEOFF]
	ldr	w9, [x26]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_intel_dp_set_link_train
	cbz	w0, LBB0_24
; %bb.3:
	mov	w25, #0
	mov	w28, #0
	mov	w8, #255
	stur	w8, [x29, #-96]                 ; 4-byte Folded Spill
Lloh20:
	adrp	x27, _DP_TRAIN_MAX_SWING_REACHED@GOTPAGE
Lloh21:
	ldr	x27, [x27, _DP_TRAIN_MAX_SWING_REACHED@GOTPAGEOFF]
	b	LBB0_7
LBB0_4:                                 ;   in Loop: Header=BB0_7 Depth=1
	mov	w28, #0
LBB0_5:                                 ;   in Loop: Header=BB0_7 Depth=1
	mov	x0, x19
	mov	x1, x20
	bl	_intel_get_adjust_train
	stur	w27, [x29, #-96]                ; 4-byte Folded Spill
	mov	x27, x22
	mov	x22, x23
	mov	x23, x24
LBB0_6:                                 ;   in Loop: Header=BB0_7 Depth=1
	mov	sp, x21
	mov	x21, sp
	ldr	w8, [x22]
	lsl	x8, x8, #2
	mov	x9, x8
Lloh22:
	adrp	x16, ___chkstk_darwin@GOTPAGE
Lloh23:
	ldr	x16, [x16, ___chkstk_darwin@GOTPAGEOFF]
	blr	x16
	mov	x9, sp
	add	x8, x8, #15
	and	x8, x8, #0x7fffffff0
	sub	x20, x9, x8
	mov	sp, x20
	sub	x1, x29, #92
	mov	x0, x19
	bl	_intel_dp_set_signal_levels
	ldur	w1, [x29, #-92]
	ldr	w8, [x23]
	ldr	w9, [x26]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_intel_dp_set_link_train
	cbz	w0, LBB0_24
LBB0_7:                                 ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_11 Depth 2
	ldr	w0, [x19, #16]
	bl	_drm_dp_link_train_clock_recovery_delay
	mov	x0, x19
	mov	x1, x20
	bl	_intel_dp_get_link_status
	cbz	w0, LBB0_20
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=1
	ldr	w1, [x19, #8]
	mov	x0, x20
	bl	_drm_dp_clock_recovery_ok
	cbnz	x0, LBB0_21
; %bb.9:                                ;   in Loop: Header=BB0_7 Depth=1
	ldr	w8, [x19, #8]
	cmp	w8, #1
	b.lt	LBB0_13
; %bb.10:                               ;   in Loop: Header=BB0_7 Depth=1
	mov	x9, #0
	ldr	x10, [x19]
	ldr	w11, [x27]
LBB0_11:                                ;   Parent Loop BB0_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ldr	w12, [x10, x9, lsl #2]
	tst	w11, w12
	b.eq	LBB0_14
; %bb.12:                               ;   in Loop: Header=BB0_11 Depth=2
	add	x9, x9, #1
	cmp	x8, x9
	b.ne	LBB0_11
	b	LBB0_15
LBB0_13:                                ;   in Loop: Header=BB0_7 Depth=1
	mov	w9, #0
LBB0_14:                                ;   in Loop: Header=BB0_7 Depth=1
	cmp	w9, w8
	b.ne	LBB0_17
LBB0_15:                                ;   in Loop: Header=BB0_7 Depth=1
	add	w25, w25, #1
	cmp	w25, #5
	b.eq	LBB0_22
; %bb.16:                               ;   in Loop: Header=BB0_7 Depth=1
	ldr	x0, [x19]
	mov	w1, #0
	mov	w2, #4
	bl	_memset
	mov	w28, #0
	b	LBB0_6
LBB0_17:                                ;   in Loop: Header=BB0_7 Depth=1
	mov	x24, x23
	mov	x23, x22
	mov	x22, x27
	ldr	x8, [x19]
	ldr	w8, [x8]
Lloh24:
	adrp	x9, _DP_TRAIN_VOLTAGE_SWING_MASK@GOTPAGE
Lloh25:
	ldr	x9, [x9, _DP_TRAIN_VOLTAGE_SWING_MASK@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	and	w27, w9, w8
	ldur	w8, [x29, #-96]                 ; 4-byte Folded Reload
	cmp	w27, w8
	b.ne	LBB0_4
; %bb.18:                               ;   in Loop: Header=BB0_7 Depth=1
	add	w28, w28, #1
	cmp	w28, #5
	b.ne	LBB0_5
; %bb.19:
Lloh27:
	adrp	x0, l_.str.3@PAGE
Lloh28:
	add	x0, x0, l_.str.3@PAGEOFF
	b	LBB0_23
LBB0_20:
Lloh29:
	adrp	x0, l_.str@PAGE
Lloh30:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_ERROR
	b	LBB0_24
LBB0_21:
Lloh31:
	adrp	x0, l_.str.1@PAGE
Lloh32:
	add	x0, x0, l_.str.1@PAGEOFF
	b	LBB0_23
LBB0_22:
Lloh33:
	adrp	x0, l_.str.2@PAGE
Lloh34:
	add	x0, x0, l_.str.2@PAGEOFF
LBB0_23:
	bl	_DRM_DEBUG_KMS
LBB0_24:
	mov	sp, x21
	ldur	w8, [x29, #-92]
	str	w8, [x19, #12]
	ldur	x8, [x29, #-88]
Lloh35:
	adrp	x9, ___stack_chk_guard@GOTPAGE
Lloh36:
	ldr	x9, [x9, ___stack_chk_guard@GOTPAGEOFF]
Lloh37:
	ldr	x9, [x9]
	cmp	x9, x8
	b.ne	LBB0_26
; %bb.25:
	sub	sp, x29, #80
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
LBB0_26:
	bl	___stack_chk_fail
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpAdd	Lloh27, Lloh28
	.loh AdrpAdd	Lloh29, Lloh30
	.loh AdrpAdd	Lloh31, Lloh32
	.loh AdrpAdd	Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.cfi_endproc
                                        ; -- End function
	.comm	_DP_LINK_BW_SET,4,2             ; @DP_LINK_BW_SET
	.comm	_DP_LINK_CONFIGURATION_SIZE,4,2 ; @DP_LINK_CONFIGURATION_SIZE
	.comm	_DP_PORT_EN,4,2                 ; @DP_PORT_EN
	.comm	_DP_LINK_STATUS_SIZE,4,2        ; @DP_LINK_STATUS_SIZE
	.comm	_DP_TRAINING_PATTERN_1,4,2      ; @DP_TRAINING_PATTERN_1
	.comm	_DP_LINK_SCRAMBLING_DISABLE,4,2 ; @DP_LINK_SCRAMBLING_DISABLE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"failed to get link status\n"

l_.str.1:                               ; @.str.1
	.asciz	"clock recovery OK\n"

	.comm	_DP_TRAIN_MAX_SWING_REACHED,4,2 ; @DP_TRAIN_MAX_SWING_REACHED
l_.str.2:                               ; @.str.2
	.asciz	"too many full retries, give up\n"

	.comm	_DP_TRAIN_VOLTAGE_SWING_MASK,4,2 ; @DP_TRAIN_VOLTAGE_SWING_MASK
l_.str.3:                               ; @.str.3
	.asciz	"too many voltage retries, give up\n"

.subsections_via_symbols
