	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function r100_get_vtx_size
_r100_get_vtx_size:                     ## @r100_get_vtx_size
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	_RADEON_SE_VTX_FMT_W0@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%edi, %eax
	movq	_RADEON_SE_VTX_FMT_FPCOLOR@GOTPCREL(%rip), %rcx
	xorl	%edx, %edx
	testl	%edi, (%rcx)
	setne	%dl
	leal	(%rdx,%rdx,2), %ecx
	cmpl	$1, %eax
	sbbl	$0, %ecx
	movq	_RADEON_SE_VTX_FMT_FPALPHA@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%edi, %eax
	cmpl	$1, %eax
	sbbl	$-1, %ecx
	movq	_RADEON_SE_VTX_FMT_PKCOLOR@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%edi, %eax
	cmpl	$1, %eax
	sbbl	$-1, %ecx
	movq	_RADEON_SE_VTX_FMT_FPSPEC@GOTPCREL(%rip), %rax
	xorl	%edx, %edx
	testl	%edi, (%rax)
	setne	%dl
	leal	(%rdx,%rdx,2), %eax
	addl	%ecx, %eax
	movq	_RADEON_SE_VTX_FMT_FPFOG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%edi, %ecx
	cmpl	$1, %ecx
	sbbl	$-1, %eax
	movq	_RADEON_SE_VTX_FMT_PKSPEC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%edi, %ecx
	cmpl	$1, %ecx
	sbbl	$-1, %eax
	movq	_RADEON_SE_VTX_FMT_ST0@GOTPCREL(%rip), %rcx
	xorl	%edx, %edx
	testl	%edi, (%rcx)
	setne	%dl
	leal	(%rax,%rdx,2), %eax
	movq	_RADEON_SE_VTX_FMT_ST1@GOTPCREL(%rip), %rcx
	xorl	%edx, %edx
	testl	%edi, (%rcx)
	setne	%dl
	leal	(%rax,%rdx,2), %eax
	movq	_RADEON_SE_VTX_FMT_Q1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%edi, %ecx
	cmpl	$1, %ecx
	sbbl	$-1, %eax
	movq	_RADEON_SE_VTX_FMT_ST2@GOTPCREL(%rip), %rcx
	xorl	%edx, %edx
	testl	%edi, (%rcx)
	setne	%dl
	leal	(%rax,%rdx,2), %r8d
	movq	_RADEON_SE_VTX_FMT_Q2@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%edi, %ecx
	cmpl	$1, %ecx
	sbbl	$-1, %r8d
	movq	_RADEON_SE_VTX_FMT_ST3@GOTPCREL(%rip), %rcx
	xorl	%r9d, %r9d
	testl	%edi, (%rcx)
	setne	%r9b
	movq	_RADEON_SE_VTX_FMT_Q3@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%edi, %ecx
	movq	_RADEON_SE_VTX_FMT_Q0@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	andl	%edi, %esi
	movl	%edi, %eax
	andl	$229376, %eax                   ## imm = 0x38000
	movl	%edi, %edx
	shrl	$15, %edx
	andl	$7, %edx
	testl	%eax, %eax
	cmovel	%eax, %edx
	leal	(%r8,%r9,2), %eax
	cmpl	$1, %ecx
	sbbl	$-1, %edx
	cmpl	$1, %esi
	sbbl	$-1, %edx
	addl	%eax, %edx
	movq	_RADEON_SE_VTX_FMT_N0@GOTPCREL(%rip), %rax
	xorl	%ecx, %ecx
	testl	%edi, (%rax)
	setne	%cl
	leal	(%rcx,%rcx,2), %eax
	addl	%edx, %eax
	movq	_RADEON_SE_VTX_FMT_XY1@GOTPCREL(%rip), %rcx
	xorl	%edx, %edx
	testl	%edi, (%rcx)
	setne	%dl
	movq	_RADEON_SE_VTX_FMT_Z1@GOTPCREL(%rip), %rcx
	movq	_RADEON_SE_VTX_FMT_W1@GOTPCREL(%rip), %rsi
	movq	_RADEON_SE_VTX_FMT_N1@GOTPCREL(%rip), %r8
	movd	(%rsi), %xmm0                   ## xmm0 = mem[0],zero,zero,zero
	movq	_RADEON_SE_VTX_FMT_Z@GOTPCREL(%rip), %rsi
	pinsrd	$1, (%rcx), %xmm0
	pinsrd	$2, (%r8), %xmm0
	pinsrd	$3, (%rsi), %xmm0
	leal	(%rax,%rdx,2), %eax
	movd	%edi, %xmm1
	pshufd	$0, %xmm1, %xmm1                ## xmm1 = xmm1[0,0,0,0]
	pand	%xmm0, %xmm1
	pxor	%xmm0, %xmm0
	pcmpeqd	%xmm1, %xmm0
	movmskps	%xmm0, %ecx
	xorl	$15, %ecx
	movl	%ecx, %edx
	shrb	%dl
	andb	$5, %dl
	subb	%dl, %cl
	movl	%ecx, %edx
	andb	$51, %dl
	shrb	$2, %cl
	andb	$51, %cl
	addb	%dl, %cl
	movl	%ecx, %edx
	shrb	$4, %dl
	addb	%cl, %dl
	andb	$15, %dl
	movzbl	%dl, %ecx
	addl	%ecx, %eax
	addl	$3, %eax
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_SE_VTX_FMT_W0,4,2       ## @RADEON_SE_VTX_FMT_W0
	.comm	_RADEON_SE_VTX_FMT_FPCOLOR,4,2  ## @RADEON_SE_VTX_FMT_FPCOLOR
	.comm	_RADEON_SE_VTX_FMT_FPALPHA,4,2  ## @RADEON_SE_VTX_FMT_FPALPHA
	.comm	_RADEON_SE_VTX_FMT_PKCOLOR,4,2  ## @RADEON_SE_VTX_FMT_PKCOLOR
	.comm	_RADEON_SE_VTX_FMT_FPSPEC,4,2   ## @RADEON_SE_VTX_FMT_FPSPEC
	.comm	_RADEON_SE_VTX_FMT_FPFOG,4,2    ## @RADEON_SE_VTX_FMT_FPFOG
	.comm	_RADEON_SE_VTX_FMT_PKSPEC,4,2   ## @RADEON_SE_VTX_FMT_PKSPEC
	.comm	_RADEON_SE_VTX_FMT_ST0,4,2      ## @RADEON_SE_VTX_FMT_ST0
	.comm	_RADEON_SE_VTX_FMT_ST1,4,2      ## @RADEON_SE_VTX_FMT_ST1
	.comm	_RADEON_SE_VTX_FMT_Q1,4,2       ## @RADEON_SE_VTX_FMT_Q1
	.comm	_RADEON_SE_VTX_FMT_ST2,4,2      ## @RADEON_SE_VTX_FMT_ST2
	.comm	_RADEON_SE_VTX_FMT_Q2,4,2       ## @RADEON_SE_VTX_FMT_Q2
	.comm	_RADEON_SE_VTX_FMT_ST3,4,2      ## @RADEON_SE_VTX_FMT_ST3
	.comm	_RADEON_SE_VTX_FMT_Q3,4,2       ## @RADEON_SE_VTX_FMT_Q3
	.comm	_RADEON_SE_VTX_FMT_Q0,4,2       ## @RADEON_SE_VTX_FMT_Q0
	.comm	_RADEON_SE_VTX_FMT_N0,4,2       ## @RADEON_SE_VTX_FMT_N0
	.comm	_RADEON_SE_VTX_FMT_XY1,4,2      ## @RADEON_SE_VTX_FMT_XY1
	.comm	_RADEON_SE_VTX_FMT_Z1,4,2       ## @RADEON_SE_VTX_FMT_Z1
	.comm	_RADEON_SE_VTX_FMT_W1,4,2       ## @RADEON_SE_VTX_FMT_W1
	.comm	_RADEON_SE_VTX_FMT_N1,4,2       ## @RADEON_SE_VTX_FMT_N1
	.comm	_RADEON_SE_VTX_FMT_Z,4,2        ## @RADEON_SE_VTX_FMT_Z
	.no_dead_strip	_r100_get_vtx_size
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function r100_get_vtx_size
_r100_get_vtx_size:                     ; @r100_get_vtx_size
	.cfi_startproc
; %bb.0:
Lloh0:
	adrp	x8, _RADEON_SE_VTX_FMT_W0@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_SE_VTX_FMT_W0@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	tst	w8, w0
	mov	w8, #2
	cinc	w8, w8, ne
Lloh3:
	adrp	x9, _RADEON_SE_VTX_FMT_FPCOLOR@GOTPAGE
Lloh4:
	ldr	x9, [x9, _RADEON_SE_VTX_FMT_FPCOLOR@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	add	w10, w8, #3
	tst	w9, w0
	csel	w8, w8, w10, eq
Lloh6:
	adrp	x9, _RADEON_SE_VTX_FMT_FPALPHA@GOTPAGE
Lloh7:
	ldr	x9, [x9, _RADEON_SE_VTX_FMT_FPALPHA@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	tst	w9, w0
Lloh9:
	adrp	x9, _RADEON_SE_VTX_FMT_PKCOLOR@GOTPAGE
Lloh10:
	ldr	x9, [x9, _RADEON_SE_VTX_FMT_PKCOLOR@GOTPAGEOFF]
	cinc	w8, w8, ne
Lloh11:
	ldr	w9, [x9]
	tst	w9, w0
	cinc	w8, w8, ne
Lloh12:
	adrp	x9, _RADEON_SE_VTX_FMT_FPSPEC@GOTPAGE
Lloh13:
	ldr	x9, [x9, _RADEON_SE_VTX_FMT_FPSPEC@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	add	w10, w8, #3
	tst	w9, w0
	csel	w8, w8, w10, eq
Lloh15:
	adrp	x9, _RADEON_SE_VTX_FMT_FPFOG@GOTPAGE
Lloh16:
	ldr	x9, [x9, _RADEON_SE_VTX_FMT_FPFOG@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	tst	w9, w0
	cinc	w8, w8, ne
Lloh18:
	adrp	x9, _RADEON_SE_VTX_FMT_PKSPEC@GOTPAGE
Lloh19:
	ldr	x9, [x9, _RADEON_SE_VTX_FMT_PKSPEC@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	tst	w9, w0
	cinc	w8, w8, ne
Lloh21:
	adrp	x9, _RADEON_SE_VTX_FMT_ST0@GOTPAGE
Lloh22:
	ldr	x9, [x9, _RADEON_SE_VTX_FMT_ST0@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	add	w10, w8, #2
	tst	w9, w0
	csel	w8, w8, w10, eq
Lloh24:
	adrp	x9, _RADEON_SE_VTX_FMT_ST1@GOTPAGE
Lloh25:
	ldr	x9, [x9, _RADEON_SE_VTX_FMT_ST1@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	add	w10, w8, #2
	tst	w9, w0
	csel	w8, w8, w10, eq
Lloh27:
	adrp	x9, _RADEON_SE_VTX_FMT_Q1@GOTPAGE
Lloh28:
	ldr	x9, [x9, _RADEON_SE_VTX_FMT_Q1@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	tst	w9, w0
	cinc	w8, w8, ne
Lloh30:
	adrp	x9, _RADEON_SE_VTX_FMT_ST2@GOTPAGE
Lloh31:
	ldr	x9, [x9, _RADEON_SE_VTX_FMT_ST2@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	add	w10, w8, #2
	tst	w9, w0
	csel	w8, w8, w10, eq
Lloh33:
	adrp	x9, _RADEON_SE_VTX_FMT_Q2@GOTPAGE
Lloh34:
	ldr	x9, [x9, _RADEON_SE_VTX_FMT_Q2@GOTPAGEOFF]
Lloh35:
	ldr	w9, [x9]
	tst	w9, w0
	cinc	w8, w8, ne
Lloh36:
	adrp	x9, _RADEON_SE_VTX_FMT_ST3@GOTPAGE
Lloh37:
	ldr	x9, [x9, _RADEON_SE_VTX_FMT_ST3@GOTPAGEOFF]
Lloh38:
	ldr	w9, [x9]
	add	w10, w8, #2
	tst	w9, w0
	csel	w8, w8, w10, eq
Lloh39:
	adrp	x9, _RADEON_SE_VTX_FMT_Q3@GOTPAGE
Lloh40:
	ldr	x9, [x9, _RADEON_SE_VTX_FMT_Q3@GOTPAGEOFF]
Lloh41:
	ldr	w9, [x9]
	ubfx	w10, w0, #15, #3
	tst	w0, #0x38000
	csel	w10, wzr, w10, eq
	tst	w9, w0
Lloh42:
	adrp	x9, _RADEON_SE_VTX_FMT_Q0@GOTPAGE
Lloh43:
	ldr	x9, [x9, _RADEON_SE_VTX_FMT_Q0@GOTPAGEOFF]
Lloh44:
	ldr	w9, [x9]
	cinc	w10, w10, ne
	tst	w9, w0
	cinc	w9, w10, ne
	add	w8, w9, w8
Lloh45:
	adrp	x9, _RADEON_SE_VTX_FMT_N0@GOTPAGE
Lloh46:
	ldr	x9, [x9, _RADEON_SE_VTX_FMT_N0@GOTPAGEOFF]
Lloh47:
	ldr	w9, [x9]
	add	w10, w8, #3
	tst	w9, w0
	csel	w8, w8, w10, eq
Lloh48:
	adrp	x9, _RADEON_SE_VTX_FMT_XY1@GOTPAGE
Lloh49:
	ldr	x9, [x9, _RADEON_SE_VTX_FMT_XY1@GOTPAGEOFF]
Lloh50:
	ldr	w9, [x9]
	add	w10, w8, #2
	tst	w9, w0
	csel	w8, w8, w10, eq
Lloh51:
	adrp	x9, _RADEON_SE_VTX_FMT_Z1@GOTPAGE
Lloh52:
	ldr	x9, [x9, _RADEON_SE_VTX_FMT_Z1@GOTPAGEOFF]
Lloh53:
	ldr	w9, [x9]
	tst	w9, w0
	cset	w9, ne
Lloh54:
	adrp	x10, _RADEON_SE_VTX_FMT_W1@GOTPAGE
Lloh55:
	ldr	x10, [x10, _RADEON_SE_VTX_FMT_W1@GOTPAGEOFF]
Lloh56:
	ldr	w10, [x10]
Lloh57:
	adrp	x11, _RADEON_SE_VTX_FMT_N1@GOTPAGE
Lloh58:
	ldr	x11, [x11, _RADEON_SE_VTX_FMT_N1@GOTPAGEOFF]
	tst	w10, w0
Lloh59:
	ldr	w10, [x11]
	cinc	w9, w9, ne
	tst	w10, w0
Lloh60:
	adrp	x10, _RADEON_SE_VTX_FMT_Z@GOTPAGE
Lloh61:
	ldr	x10, [x10, _RADEON_SE_VTX_FMT_Z@GOTPAGEOFF]
Lloh62:
	ldr	w10, [x10]
	cinc	w9, w9, ne
	tst	w10, w0
	cinc	w9, w9, ne
	add	w0, w9, w8
	ret
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_SE_VTX_FMT_W0,4,2       ; @RADEON_SE_VTX_FMT_W0
	.comm	_RADEON_SE_VTX_FMT_FPCOLOR,4,2  ; @RADEON_SE_VTX_FMT_FPCOLOR
	.comm	_RADEON_SE_VTX_FMT_FPALPHA,4,2  ; @RADEON_SE_VTX_FMT_FPALPHA
	.comm	_RADEON_SE_VTX_FMT_PKCOLOR,4,2  ; @RADEON_SE_VTX_FMT_PKCOLOR
	.comm	_RADEON_SE_VTX_FMT_FPSPEC,4,2   ; @RADEON_SE_VTX_FMT_FPSPEC
	.comm	_RADEON_SE_VTX_FMT_FPFOG,4,2    ; @RADEON_SE_VTX_FMT_FPFOG
	.comm	_RADEON_SE_VTX_FMT_PKSPEC,4,2   ; @RADEON_SE_VTX_FMT_PKSPEC
	.comm	_RADEON_SE_VTX_FMT_ST0,4,2      ; @RADEON_SE_VTX_FMT_ST0
	.comm	_RADEON_SE_VTX_FMT_ST1,4,2      ; @RADEON_SE_VTX_FMT_ST1
	.comm	_RADEON_SE_VTX_FMT_Q1,4,2       ; @RADEON_SE_VTX_FMT_Q1
	.comm	_RADEON_SE_VTX_FMT_ST2,4,2      ; @RADEON_SE_VTX_FMT_ST2
	.comm	_RADEON_SE_VTX_FMT_Q2,4,2       ; @RADEON_SE_VTX_FMT_Q2
	.comm	_RADEON_SE_VTX_FMT_ST3,4,2      ; @RADEON_SE_VTX_FMT_ST3
	.comm	_RADEON_SE_VTX_FMT_Q3,4,2       ; @RADEON_SE_VTX_FMT_Q3
	.comm	_RADEON_SE_VTX_FMT_Q0,4,2       ; @RADEON_SE_VTX_FMT_Q0
	.comm	_RADEON_SE_VTX_FMT_N0,4,2       ; @RADEON_SE_VTX_FMT_N0
	.comm	_RADEON_SE_VTX_FMT_XY1,4,2      ; @RADEON_SE_VTX_FMT_XY1
	.comm	_RADEON_SE_VTX_FMT_Z1,4,2       ; @RADEON_SE_VTX_FMT_Z1
	.comm	_RADEON_SE_VTX_FMT_W1,4,2       ; @RADEON_SE_VTX_FMT_W1
	.comm	_RADEON_SE_VTX_FMT_N1,4,2       ; @RADEON_SE_VTX_FMT_N1
	.comm	_RADEON_SE_VTX_FMT_Z,4,2        ; @RADEON_SE_VTX_FMT_Z
	.no_dead_strip	_r100_get_vtx_size
.subsections_via_symbols
