	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_enable_bm               ## -- Begin function radeon_enable_bm
	.p2align	4, 0x90
_radeon_enable_bm:                      ## @radeon_enable_bm
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	_RADEON_FAMILY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%rdi), %eax
	movq	_CHIP_RS690@GOTPCREL(%rip), %rcx
	movq	_RS600_BUS_MASTER_DIS@GOTPCREL(%rip), %rbx
	cmpl	(%rcx), %eax
	je	LBB0_7
## %bb.1:
	movq	_CHIP_RS740@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_7
## %bb.2:
	movq	_CHIP_RV350@GOTPCREL(%rip), %rcx
	movq	_RADEON_BUS_MASTER_DIS@GOTPCREL(%rip), %rbx
	cmpl	(%rcx), %eax
	jle	LBB0_7
## %bb.3:
	movq	_CHIP_R420@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_7
## %bb.4:
	movq	_CHIP_RS400@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_7
## %bb.5:
	movq	_CHIP_RS480@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_7
## %bb.6:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
LBB0_7:
	movq	_RADEON_BUS_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RADEON_READ
	movl	(%rbx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r14), %edi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_RADEON_WRITE                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_FAMILY_MASK,4,2         ## @RADEON_FAMILY_MASK
	.comm	_CHIP_RS690,4,2                 ## @CHIP_RS690
	.comm	_CHIP_RS740,4,2                 ## @CHIP_RS740
	.comm	_RADEON_BUS_CNTL,4,2            ## @RADEON_BUS_CNTL
	.comm	_RS600_BUS_MASTER_DIS,4,2       ## @RS600_BUS_MASTER_DIS
	.comm	_CHIP_RV350,4,2                 ## @CHIP_RV350
	.comm	_CHIP_R420,4,2                  ## @CHIP_R420
	.comm	_CHIP_RS400,4,2                 ## @CHIP_RS400
	.comm	_CHIP_RS480,4,2                 ## @CHIP_RS480
	.comm	_RADEON_BUS_MASTER_DIS,4,2      ## @RADEON_BUS_MASTER_DIS
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_enable_bm               ; -- Begin function radeon_enable_bm
	.p2align	2
_radeon_enable_bm:                      ; @radeon_enable_bm
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _RADEON_FAMILY_MASK@GOTPAGE
Lloh1:
	ldr	x9, [x9, _RADEON_FAMILY_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	and	w8, w9, w8
Lloh3:
	adrp	x9, _CHIP_RS690@GOTPAGE
Lloh4:
	ldr	x9, [x9, _CHIP_RS690@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
Lloh6:
	adrp	x10, _CHIP_RS740@GOTPAGE
Lloh7:
	ldr	x10, [x10, _CHIP_RS740@GOTPAGEOFF]
Lloh8:
	ldr	w10, [x10]
	cmp	w8, w9
	ccmp	w8, w10, #4, ne
	b.ne	LBB0_2
; %bb.1:
Lloh9:
	adrp	x19, _RS600_BUS_MASTER_DIS@GOTPAGE
Lloh10:
	ldr	x19, [x19, _RS600_BUS_MASTER_DIS@GOTPAGEOFF]
	b	LBB0_4
LBB0_2:
Lloh11:
	adrp	x9, _CHIP_RV350@GOTPAGE
Lloh12:
	ldr	x9, [x9, _CHIP_RV350@GOTPAGEOFF]
Lloh13:
	adrp	x10, _CHIP_R420@GOTPAGE
Lloh14:
	ldr	x10, [x10, _CHIP_R420@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
Lloh16:
	ldr	w10, [x10]
Lloh17:
	adrp	x11, _CHIP_RS400@GOTPAGE
Lloh18:
	ldr	x11, [x11, _CHIP_RS400@GOTPAGEOFF]
Lloh19:
	adrp	x12, _CHIP_RS480@GOTPAGE
Lloh20:
	ldr	x12, [x12, _CHIP_RS480@GOTPAGEOFF]
Lloh21:
	ldr	w11, [x11]
Lloh22:
	ldr	w12, [x12]
	cmp	w8, w9
	ccmp	w8, w10, #4, gt
	ccmp	w8, w11, #4, ne
	ccmp	w8, w12, #4, ne
	b.ne	LBB0_5
; %bb.3:
Lloh23:
	adrp	x19, _RADEON_BUS_MASTER_DIS@GOTPAGE
Lloh24:
	ldr	x19, [x19, _RADEON_BUS_MASTER_DIS@GOTPAGEOFF]
LBB0_4:
Lloh25:
	adrp	x20, _RADEON_BUS_CNTL@GOTPAGE
Lloh26:
	ldr	x20, [x20, _RADEON_BUS_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RADEON_READ
	ldr	w8, [x19]
	bic	w1, w0, w8
	ldr	w0, [x20]
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_RADEON_WRITE
LBB0_5:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh21
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh15
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh25, Lloh26
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_FAMILY_MASK,4,2         ; @RADEON_FAMILY_MASK
	.comm	_CHIP_RS690,4,2                 ; @CHIP_RS690
	.comm	_CHIP_RS740,4,2                 ; @CHIP_RS740
	.comm	_RADEON_BUS_CNTL,4,2            ; @RADEON_BUS_CNTL
	.comm	_RS600_BUS_MASTER_DIS,4,2       ; @RS600_BUS_MASTER_DIS
	.comm	_CHIP_RV350,4,2                 ; @CHIP_RV350
	.comm	_CHIP_R420,4,2                  ; @CHIP_R420
	.comm	_CHIP_RS400,4,2                 ; @CHIP_RS400
	.comm	_CHIP_RS480,4,2                 ; @CHIP_RS480
	.comm	_RADEON_BUS_MASTER_DIS,4,2      ; @RADEON_BUS_MASTER_DIS
.subsections_via_symbols
