	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_get_scratch             ## -- Begin function radeon_get_scratch
	.p2align	4, 0x90
_radeon_get_scratch:                    ## @radeon_get_scratch
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	_RADEON_FAMILY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_CHIP_R600@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	(%rdi), %eax
	cmpq	$0, 8(%rdi)
	je	LBB0_5
## %bb.1:
	movq	%rdi, %rbx
	movl	%esi, %edi
	cmpl	%ecx, %eax
	jge	LBB0_2
## %bb.4:
	callq	_RADEON_SCRATCHOFF
	jmp	LBB0_3
LBB0_5:
	cmpl	%ecx, %eax
	jge	LBB0_6
## %bb.8:
	movq	_RADEON_SCRATCH_REG0@GOTPCREL(%rip), %rax
	jmp	LBB0_7
LBB0_2:
	callq	_R600_SCRATCHOFF
LBB0_3:
	movq	%rbx, %rdi
	movl	%eax, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_radeon_read_ring_rptr          ## TAILCALL
LBB0_6:
	movq	_R600_SCRATCH_REG0@GOTPCREL(%rip), %rax
LBB0_7:
	shll	$2, %esi
	movslq	%esi, %rdi
	addq	(%rax), %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_RADEON_READ                    ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_FAMILY_MASK,4,2         ## @RADEON_FAMILY_MASK
	.comm	_CHIP_R600,4,2                  ## @CHIP_R600
	.comm	_R600_SCRATCH_REG0,8,3          ## @R600_SCRATCH_REG0
	.comm	_RADEON_SCRATCH_REG0,8,3        ## @RADEON_SCRATCH_REG0
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_get_scratch             ; -- Begin function radeon_get_scratch
	.p2align	2
_radeon_get_scratch:                    ; @radeon_get_scratch
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	x10, [x0, #8]
Lloh0:
	adrp	x8, _RADEON_FAMILY_MASK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_FAMILY_MASK@GOTPAGEOFF]
	ldr	w9, [x0]
Lloh2:
	ldr	w8, [x8]
	and	w8, w8, w9
Lloh3:
	adrp	x9, _CHIP_R600@GOTPAGE
Lloh4:
	ldr	x9, [x9, _CHIP_R600@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	cbz	x10, LBB0_3
; %bb.1:
	mov	x19, x0
	mov	x0, x1
	cmp	w8, w9
	b.ge	LBB0_5
; %bb.2:
	bl	_RADEON_SCRATCHOFF
	b	LBB0_6
LBB0_3:
	cmp	w8, w9
	b.ge	LBB0_7
; %bb.4:
Lloh6:
	adrp	x8, _RADEON_SCRATCH_REG0@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_SCRATCH_REG0@GOTPAGEOFF]
	b	LBB0_8
LBB0_5:
	bl	_R600_SCRATCHOFF
LBB0_6:
	mov	x1, x0
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_radeon_read_ring_rptr
LBB0_7:
Lloh8:
	adrp	x8, _R600_SCRATCH_REG0@GOTPAGE
Lloh9:
	ldr	x8, [x8, _R600_SCRATCH_REG0@GOTPAGEOFF]
LBB0_8:
	ldr	x8, [x8]
	lsl	w9, w1, #2
	add	x0, x8, w9, sxtw
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_RADEON_READ
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh8, Lloh9
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_FAMILY_MASK,4,2         ; @RADEON_FAMILY_MASK
	.comm	_CHIP_R600,4,2                  ; @CHIP_R600
	.comm	_R600_SCRATCH_REG0,8,3          ; @R600_SCRATCH_REG0
	.comm	_RADEON_SCRATCH_REG0,8,3        ; @RADEON_SCRATCH_REG0
.subsections_via_symbols
