	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function r100_vram_get_type
_r100_vram_get_type:                    ## @r100_vram_get_type
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	movl	$0, 16(%rdi)
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rdi)
	jne	LBB0_2
## %bb.1:
	movq	_RADEON_MEM_SDRAM_MODE_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_RADEON_MEM_CFG_TYPE_DDR@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_3
LBB0_2:
	movl	$1, 16(%rbx)
LBB0_3:
	movq	8(%rbx), %rax
	movq	_CHIP_RV100@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_6
## %bb.4:
	movq	_CHIP_RS100@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_6
## %bb.5:
	movq	_CHIP_RS200@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_6
## %bb.8:
	movq	_CHIP_RV280@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jg	LBB0_11
## %bb.9:
	movq	_RADEON_MEM_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_RADEON_MEM_NUM_CHANNELS_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_10
LBB0_11:
	movl	$128, 20(%rbx)
	jmp	LBB0_12
LBB0_6:
	movq	_RADEON_MEM_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_RV100_HALF_MODE@GOTPCREL(%rip), %rdx
	xorl	%ecx, %ecx
	andl	(%rdx), %eax
	sete	%cl
	shll	$5, %ecx
	addl	$32, %ecx
	movl	%ecx, 20(%rbx)
	movq	_RADEON_SINGLE_CRTC@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rbx)
	je	LBB0_12
## %bb.7:
	shrl	$2, %ecx
	movl	%ecx, 20(%rbx)
	movl	$1, 16(%rbx)
	jmp	LBB0_12
LBB0_10:
	movl	$64, 20(%rbx)
LBB0_12:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
	.comm	_RADEON_MEM_SDRAM_MODE_REG,4,2  ## @RADEON_MEM_SDRAM_MODE_REG
	.comm	_RADEON_MEM_CFG_TYPE_DDR,4,2    ## @RADEON_MEM_CFG_TYPE_DDR
	.comm	_CHIP_RV100,8,3                 ## @CHIP_RV100
	.comm	_CHIP_RS100,8,3                 ## @CHIP_RS100
	.comm	_CHIP_RS200,8,3                 ## @CHIP_RS200
	.comm	_RADEON_MEM_CNTL,4,2            ## @RADEON_MEM_CNTL
	.comm	_RV100_HALF_MODE,4,2            ## @RV100_HALF_MODE
	.comm	_RADEON_SINGLE_CRTC,4,2         ## @RADEON_SINGLE_CRTC
	.comm	_CHIP_RV280,8,3                 ## @CHIP_RV280
	.comm	_RADEON_MEM_NUM_CHANNELS_MASK,4,2 ## @RADEON_MEM_NUM_CHANNELS_MASK
	.no_dead_strip	_r100_vram_get_type
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function r100_vram_get_type
_r100_vram_get_type:                    ; @r100_vram_get_type
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	str	wzr, [x0, #16]
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _RADEON_IS_IGP@GOTPAGE
Lloh1:
	ldr	x9, [x9, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_2
; %bb.1:
Lloh3:
	adrp	x8, _RADEON_MEM_SDRAM_MODE_REG@GOTPAGE
Lloh4:
	ldr	x8, [x8, _RADEON_MEM_SDRAM_MODE_REG@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	bl	_RREG32
Lloh6:
	adrp	x8, _RADEON_MEM_CFG_TYPE_DDR@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_MEM_CFG_TYPE_DDR@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_3
LBB0_2:
	mov	w8, #1
	str	w8, [x19, #16]
LBB0_3:
	ldr	x8, [x19, #8]
Lloh9:
	adrp	x9, _CHIP_RV100@GOTPAGE
Lloh10:
	ldr	x9, [x9, _CHIP_RV100@GOTPAGEOFF]
Lloh11:
	ldr	x9, [x9]
Lloh12:
	adrp	x10, _CHIP_RS100@GOTPAGE
Lloh13:
	ldr	x10, [x10, _CHIP_RS100@GOTPAGEOFF]
Lloh14:
	ldr	x10, [x10]
Lloh15:
	adrp	x11, _CHIP_RS200@GOTPAGE
Lloh16:
	ldr	x11, [x11, _CHIP_RS200@GOTPAGEOFF]
Lloh17:
	ldr	x11, [x11]
	cmp	x8, x9
	ccmp	x8, x10, #4, ne
	ccmp	x8, x11, #4, ne
	b.ne	LBB0_6
; %bb.4:
Lloh18:
	adrp	x8, _RADEON_MEM_CNTL@GOTPAGE
Lloh19:
	ldr	x8, [x8, _RADEON_MEM_CNTL@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
	bl	_RREG32
Lloh21:
	adrp	x8, _RV100_HALF_MODE@GOTPAGE
Lloh22:
	ldr	x8, [x8, _RV100_HALF_MODE@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	tst	w8, w0
	mov	w8, #32
	mov	w9, #64
	csel	w8, w9, w8, eq
	str	w8, [x19, #20]
	ldr	w9, [x19]
Lloh24:
	adrp	x10, _RADEON_SINGLE_CRTC@GOTPAGE
Lloh25:
	ldr	x10, [x10, _RADEON_SINGLE_CRTC@GOTPAGEOFF]
Lloh26:
	ldr	w10, [x10]
	tst	w10, w9
	b.eq	LBB0_11
; %bb.5:
	lsr	w8, w8, #2
	mov	w9, #1
	stp	w9, w8, [x19, #16]
	b	LBB0_11
LBB0_6:
Lloh27:
	adrp	x9, _CHIP_RV280@GOTPAGE
Lloh28:
	ldr	x9, [x9, _CHIP_RV280@GOTPAGEOFF]
Lloh29:
	ldr	x9, [x9]
	cmp	x8, x9
	b.gt	LBB0_8
; %bb.7:
Lloh30:
	adrp	x8, _RADEON_MEM_CNTL@GOTPAGE
Lloh31:
	ldr	x8, [x8, _RADEON_MEM_CNTL@GOTPAGEOFF]
Lloh32:
	ldr	w0, [x8]
	bl	_RREG32
Lloh33:
	adrp	x8, _RADEON_MEM_NUM_CHANNELS_MASK@GOTPAGE
Lloh34:
	ldr	x8, [x8, _RADEON_MEM_NUM_CHANNELS_MASK@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_9
LBB0_8:
	mov	w8, #128
	b	LBB0_10
LBB0_9:
	mov	w8, #64
LBB0_10:
	str	w8, [x19, #20]
LBB0_11:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
	.comm	_RADEON_MEM_SDRAM_MODE_REG,4,2  ; @RADEON_MEM_SDRAM_MODE_REG
	.comm	_RADEON_MEM_CFG_TYPE_DDR,4,2    ; @RADEON_MEM_CFG_TYPE_DDR
	.comm	_CHIP_RV100,8,3                 ; @CHIP_RV100
	.comm	_CHIP_RS100,8,3                 ; @CHIP_RS100
	.comm	_CHIP_RS200,8,3                 ; @CHIP_RS200
	.comm	_RADEON_MEM_CNTL,4,2            ; @RADEON_MEM_CNTL
	.comm	_RV100_HALF_MODE,4,2            ; @RV100_HALF_MODE
	.comm	_RADEON_SINGLE_CRTC,4,2         ; @RADEON_SINGLE_CRTC
	.comm	_CHIP_RV280,8,3                 ; @CHIP_RV280
	.comm	_RADEON_MEM_NUM_CHANNELS_MASK,4,2 ; @RADEON_MEM_NUM_CHANNELS_MASK
	.no_dead_strip	_r100_vram_get_type
.subsections_via_symbols
