	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_vm_bo_update_pte        ## -- Begin function radeon_vm_bo_update_pte
	.p2align	4, 0x90
_radeon_vm_bo_update_pte:               ## @radeon_vm_bo_update_pte
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	xorl	%r12d, %r12d
	cmpq	$0, 8(%rsi)
	je	LBB0_25
## %bb.1:
	movq	%rcx, %r14
	movq	%rdx, %r13
	movq	%rsi, %r15
	movq	%rdi, %rbx
	movq	16(%rdi), %rax
	movl	(%rax), %eax
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	movq	%rsi, %rdi
	movq	%rdx, %rsi
	callq	_radeon_vm_bo_find
	movq	%rbx, %rcx
	testq	%rax, %rax
	je	LBB0_2
## %bb.4:
	movq	%rax, %rbx
	movq	%rcx, -48(%rbp)                 ## 8-byte Spill
	cmpl	$0, 12(%rax)
	je	LBB0_5
## %bb.6:
	movl	(%rbx), %eax
	testq	%r14, %r14
	je	LBB0_8
## %bb.7:
	testl	%eax, %eax
	jne	LBB0_25
LBB0_8:
	testq	%r14, %r14
	jne	LBB0_10
## %bb.9:
	testl	%eax, %eax
	je	LBB0_25
LBB0_10:
	movq	_RADEON_VM_PAGE_VALID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_RADEON_VM_PAGE_SYSTEM@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	orl	%esi, %edx
	notl	%edx
	andl	4(%rbx), %edx
	movl	%edx, 4(%rbx)
	testq	%r14, %r14
	je	LBB0_16
## %bb.11:
	movl	(%r14), %r12d
	movq	_PAGE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r12d
	movq	8(%r14), %rcx
	movq	_TTM_PL_SYSTEM@GOTPCREL(%rip), %rdi
	cmpq	(%rdi), %rcx
	je	LBB0_13
## %bb.12:
	orl	%esi, %edx
	movl	%edx, 4(%rbx)
	movl	$1, (%rbx)
LBB0_13:
	movq	_TTM_PL_TT@GOTPCREL(%rip), %rsi
	cmpq	(%rsi), %rcx
	jne	LBB0_15
## %bb.14:
	orl	(%rax), %edx
	movl	%edx, 4(%rbx)
	jmp	LBB0_17
LBB0_2:
	movl	8(%rcx), %edi
	leaq	L_.str(%rip), %rsi
	jmp	LBB0_3
LBB0_5:
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movl	8(%rax), %edi
	leaq	L_.str.1(%rip), %rsi
LBB0_3:
	movq	%r13, %rdx
	movq	%r15, %rcx
	callq	_dev_err
	movq	_EINVAL@GOTPCREL(%rip), %rax
LBB0_19:
	xorl	%r12d, %r12d
	subl	(%rax), %r12d
LBB0_25:
	movl	%r12d, %eax
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_16:
	movl	$0, (%rbx)
	xorl	%r12d, %r12d
	jmp	LBB0_17
LBB0_15:
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	addl	(%rax), %r12d
LBB0_17:
	movq	%r13, %rdi
	callq	_radeon_bo_ngpu_pages
                                        ## kill: def $eax killed $eax def $rax
	movq	_RADEON_VM_BLOCK_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%eax, %edx
	shrl	%cl, %edx
	leal	2(%rdx), %r8d
	movl	%eax, %edi
	shrl	$9, %edi
	andl	$-4, %edi
	leal	(,%rdx,4), %esi
	cmpl	$12, %ecx
	cmovael	%edi, %esi
	shrl	$11, %r8d
	leal	(%rsi,%rax,2), %eax
	leal	(%rax,%rdx,2), %eax
	addl	$4, %eax
	leal	(%rax,%r8,4), %r8d
	addl	$64, %r8d
	cmpl	$1048576, %r8d                  ## imm = 0x100000
	jb	LBB0_20
## %bb.18:
	movq	_ENOMEM@GOTPCREL(%rip), %rax
	jmp	LBB0_19
LBB0_20:
	movl	%r12d, -52(%rbp)                ## 4-byte Spill
	shll	$2, %r8d
	leaq	-72(%rbp), %r14
	movq	-48(%rbp), %r13                 ## 8-byte Reload
	movq	%r13, %rdi
	movl	-56(%rbp), %esi                 ## 4-byte Reload
	movq	%r14, %rdx
	xorl	%ecx, %ecx
	callq	_radeon_ib_get
	movq	$0, -64(%rbp)
	movl	8(%rbx), %r8d
	movl	12(%rbx), %ecx
	movq	%r13, %rdi
	movq	%r15, %rsi
	movq	%r14, %rdx
	callq	_radeon_vm_update_pdes
	testl	%eax, %eax
	je	LBB0_22
## %bb.21:
	movl	%eax, %r12d
	leaq	-72(%rbp), %rsi
	movq	%r13, %rdi
	callq	_radeon_ib_free
	jmp	LBB0_25
LBB0_22:
	movl	12(%rbx), %ecx
	movl	4(%rbx), %eax
	movl	8(%rbx), %r8d
	movl	%eax, (%rsp)
	leaq	-72(%rbp), %rbx
	movq	%r13, %rdi
	movq	%r15, %rsi
	movq	%rbx, %rdx
	movl	-52(%rbp), %r9d                 ## 4-byte Reload
	callq	_radeon_vm_update_ptes
	movl	4(%r15), %esi
	movq	%rbx, %rdi
	callq	_radeon_ib_sync_to
	xorl	%r12d, %r12d
	movq	%r13, %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	_radeon_ib_schedule
	testl	%eax, %eax
	je	LBB0_24
## %bb.23:
	movl	%eax, %ebx
	leaq	-72(%rbp), %rsi
	movq	%r13, %rdi
	callq	_radeon_ib_free
	movl	%ebx, %r12d
	jmp	LBB0_25
LBB0_24:
	leaq	4(%r15), %rdi
	callq	_radeon_fence_unref
	movl	-72(%rbp), %edi
	callq	_radeon_fence_ref
	movl	%eax, 4(%r15)
	leaq	-72(%rbp), %rsi
	movq	%r13, %rdi
	callq	_radeon_ib_free
	movq	%r15, %rdi
	callq	_radeon_fence_unref
	jmp	LBB0_25
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"bo %p not in vm %p\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
L_.str.1:                               ## @.str.1
	.asciz	"bo %p don't has a mapping in vm %p\n"

	.comm	_RADEON_VM_PAGE_VALID,4,2       ## @RADEON_VM_PAGE_VALID
	.comm	_RADEON_VM_PAGE_SYSTEM,4,2      ## @RADEON_VM_PAGE_SYSTEM
	.comm	_PAGE_SHIFT,4,2                 ## @PAGE_SHIFT
	.comm	_TTM_PL_SYSTEM,8,3              ## @TTM_PL_SYSTEM
	.comm	_TTM_PL_TT,8,3                  ## @TTM_PL_TT
	.comm	_RADEON_VM_BLOCK_SIZE,4,2       ## @RADEON_VM_BLOCK_SIZE
	.comm	_ENOMEM,4,2                     ## @ENOMEM
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_vm_bo_update_pte        ; -- Begin function radeon_vm_bo_update_pte
	.p2align	2
_radeon_vm_bo_update_pte:               ; @radeon_vm_bo_update_pte
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	ldr	x8, [x1, #8]
	cbz	x8, LBB0_7
; %bb.1:
	mov	x24, x3
	mov	x23, x2
	mov	x19, x1
	mov	x20, x0
	ldr	x8, [x0, #16]
	ldr	w22, [x8]
	mov	x0, x1
	mov	x1, x2
	bl	_radeon_vm_bo_find
	cbz	x0, LBB0_8
; %bb.2:
	mov	x21, x0
	ldr	w8, [x0, #12]
	cbz	w8, LBB0_9
; %bb.3:
	ldr	w8, [x21]
	cbz	x24, LBB0_5
; %bb.4:
	cbnz	w8, LBB0_7
LBB0_5:
	cbnz	x24, LBB0_13
; %bb.6:
	cbnz	w8, LBB0_13
LBB0_7:
	mov	w22, #0
	b	LBB0_12
LBB0_8:
	ldr	w0, [x20, #8]
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	b	LBB0_10
LBB0_9:
	ldr	w0, [x20, #8]
Lloh2:
	adrp	x1, l_.str.1@PAGE
Lloh3:
	add	x1, x1, l_.str.1@PAGEOFF
LBB0_10:
	mov	x2, x23
	mov	x3, x19
	bl	_dev_err
Lloh4:
	adrp	x8, _EINVAL@GOTPAGE
Lloh5:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
LBB0_11:
	ldr	w8, [x8]
	neg	w22, w8
LBB0_12:
	mov	x0, x22
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
LBB0_13:
Lloh6:
	adrp	x8, _RADEON_VM_PAGE_VALID@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_VM_PAGE_VALID@GOTPAGEOFF]
Lloh8:
	ldr	w10, [x8]
	ldr	w9, [x21, #4]
Lloh9:
	adrp	x8, _RADEON_VM_PAGE_SYSTEM@GOTPAGE
Lloh10:
	ldr	x8, [x8, _RADEON_VM_PAGE_SYSTEM@GOTPAGEOFF]
	ldr	w11, [x8]
	orr	w11, w10, w11
	bic	w9, w9, w11
	str	w9, [x21, #4]
	cbz	x24, LBB0_18
; %bb.14:
	ldr	w11, [x24]
Lloh11:
	adrp	x12, _PAGE_SHIFT@GOTPAGE
Lloh12:
	ldr	x12, [x12, _PAGE_SHIFT@GOTPAGEOFF]
Lloh13:
	ldr	w12, [x12]
	ldr	x13, [x24, #8]
Lloh14:
	adrp	x14, _TTM_PL_SYSTEM@GOTPAGE
Lloh15:
	ldr	x14, [x14, _TTM_PL_SYSTEM@GOTPAGEOFF]
Lloh16:
	ldr	x14, [x14]
	cmp	x13, x14
	b.eq	LBB0_16
; %bb.15:
	orr	w9, w9, w10
	mov	w10, #1
	stp	w10, w9, [x21]
LBB0_16:
	lsl	w24, w11, w12
Lloh17:
	adrp	x10, _TTM_PL_TT@GOTPAGE
Lloh18:
	ldr	x10, [x10, _TTM_PL_TT@GOTPAGEOFF]
Lloh19:
	ldr	x10, [x10]
	cmp	x13, x10
	b.ne	LBB0_19
; %bb.17:
	ldr	w8, [x8]
	orr	w8, w9, w8
	str	w8, [x21, #4]
	b	LBB0_20
LBB0_18:
	str	wzr, [x21]
	b	LBB0_20
LBB0_19:
	ldr	w8, [x20]
	add	w24, w24, w8
LBB0_20:
	mov	x0, x23
	bl	_radeon_bo_ngpu_pages
Lloh20:
	adrp	x8, _RADEON_VM_BLOCK_SIZE@GOTPAGE
Lloh21:
	ldr	x8, [x8, _RADEON_VM_BLOCK_SIZE@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
	lsr	w9, w0, w8
	add	w10, w9, #2
	lsr	w11, w0, #9
	and	w11, w11, #0x7ffffc
	lsl	w9, w9, #2
	cmp	w8, #11
	csel	w8, w11, w9, hi
	lsr	w9, w10, #9
	and	w9, w9, #0x7ffffc
	add	w8, w8, w0, lsl #1
	add	w8, w8, w10, lsl #1
	add	w8, w8, w9
	add	w8, w8, #64
	cmp	w8, #256, lsl #12               ; =1048576
	b.lo	LBB0_22
; %bb.21:
Lloh23:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh24:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
	b	LBB0_11
LBB0_22:
	lsl	w4, w8, #2
	mov	x2, sp
	mov	x0, x20
	mov	x1, x22
	mov	x3, #0
	bl	_radeon_ib_get
	str	xzr, [sp, #8]
	ldp	w4, w3, [x21, #8]
	mov	x2, sp
	mov	x0, x20
	mov	x1, x19
	bl	_radeon_vm_update_pdes
	cbz	w0, LBB0_24
; %bb.23:
	mov	x22, x0
	b	LBB0_25
LBB0_24:
	ldp	w4, w3, [x21, #8]
	ldr	w6, [x21, #4]
	mov	x2, sp
	mov	x0, x20
	mov	x1, x19
	mov	x5, x24
	bl	_radeon_vm_update_ptes
	mov	x21, x19
	ldr	w1, [x21, #4]!
	mov	x0, sp
	bl	_radeon_ib_sync_to
	mov	x1, sp
	mov	x0, x20
	mov	x2, #0
	bl	_radeon_ib_schedule
	mov	x22, x0
	cbz	w0, LBB0_26
LBB0_25:
	mov	x1, sp
	mov	x0, x20
	bl	_radeon_ib_free
	b	LBB0_12
LBB0_26:
	mov	x0, x21
	bl	_radeon_fence_unref
	ldr	w0, [sp]
	bl	_radeon_fence_ref
	str	w0, [x19, #4]
	mov	x1, sp
	mov	x0, x20
	bl	_radeon_ib_free
	mov	x0, x19
	bl	_radeon_fence_unref
	b	LBB0_12
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh23, Lloh24
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"bo %p not in vm %p\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
l_.str.1:                               ; @.str.1
	.asciz	"bo %p don't has a mapping in vm %p\n"

	.comm	_RADEON_VM_PAGE_VALID,4,2       ; @RADEON_VM_PAGE_VALID
	.comm	_RADEON_VM_PAGE_SYSTEM,4,2      ; @RADEON_VM_PAGE_SYSTEM
	.comm	_PAGE_SHIFT,4,2                 ; @PAGE_SHIFT
	.comm	_TTM_PL_SYSTEM,8,3              ; @TTM_PL_SYSTEM
	.comm	_TTM_PL_TT,8,3                  ; @TTM_PL_TT
	.comm	_RADEON_VM_BLOCK_SIZE,4,2       ; @RADEON_VM_BLOCK_SIZE
	.comm	_ENOMEM,4,2                     ; @ENOMEM
.subsections_via_symbols
