	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_write_agp_location      ## -- Begin function radeon_write_agp_location
	.p2align	4, 0x90
_radeon_write_agp_location:             ## @radeon_write_agp_location
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	_RADEON_FAMILY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%rdi), %eax
	movl	%esi, %ebx
	movq	_CHIP_RV770@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jge	LBB0_1
## %bb.4:
	movq	_CHIP_R600@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jge	LBB0_5
## %bb.6:
	movq	_CHIP_RV515@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	cmpl	%ecx, %eax
	jne	LBB0_9
## %bb.7:
	movq	_RV515_MC_AGP_LOCATION@GOTPCREL(%rip), %rax
LBB0_8:
	movl	(%rax), %edi
	movl	%ebx, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_R500_WRITE_MCIND               ## TAILCALL
LBB0_1:
	movq	_R700_MC_VM_AGP_BOT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movzwl	%bx, %esi
	callq	_RADEON_WRITE
	movq	_R700_MC_VM_AGP_TOP@GOTPCREL(%rip), %rax
	jmp	LBB0_2
LBB0_5:
	movq	_R600_MC_VM_AGP_BOT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movzwl	%bx, %esi
	callq	_RADEON_WRITE
	movq	_R600_MC_VM_AGP_TOP@GOTPCREL(%rip), %rax
LBB0_2:
	movl	(%rax), %edi
	shrl	$16, %ebx
LBB0_3:
	movl	%ebx, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_RADEON_WRITE                   ## TAILCALL
LBB0_9:
	movq	_CHIP_RS690@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %eax
	je	LBB0_15
## %bb.10:
	movq	_CHIP_RS740@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %eax
	je	LBB0_15
## %bb.11:
	movq	_CHIP_RS600@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %eax
	jne	LBB0_12
## %bb.16:
	movq	_RS600_MC_AGP_LOCATION@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_RS600_WRITE_MCIND              ## TAILCALL
LBB0_15:
	movq	_RS690_MC_AGP_LOCATION@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_RS690_WRITE_MCIND              ## TAILCALL
LBB0_12:
	cmpl	%ecx, %eax
	jle	LBB0_14
## %bb.13:
	movq	_R520_MC_AGP_LOCATION@GOTPCREL(%rip), %rax
	jmp	LBB0_8
LBB0_14:
	movq	_RADEON_MC_AGP_LOCATION@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	jmp	LBB0_3
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_FAMILY_MASK,4,2         ## @RADEON_FAMILY_MASK
	.comm	_CHIP_RV770,4,2                 ## @CHIP_RV770
	.comm	_R700_MC_VM_AGP_BOT,4,2         ## @R700_MC_VM_AGP_BOT
	.comm	_R700_MC_VM_AGP_TOP,4,2         ## @R700_MC_VM_AGP_TOP
	.comm	_CHIP_R600,4,2                  ## @CHIP_R600
	.comm	_R600_MC_VM_AGP_BOT,4,2         ## @R600_MC_VM_AGP_BOT
	.comm	_R600_MC_VM_AGP_TOP,4,2         ## @R600_MC_VM_AGP_TOP
	.comm	_CHIP_RV515,4,2                 ## @CHIP_RV515
	.comm	_RV515_MC_AGP_LOCATION,4,2      ## @RV515_MC_AGP_LOCATION
	.comm	_CHIP_RS690,4,2                 ## @CHIP_RS690
	.comm	_CHIP_RS740,4,2                 ## @CHIP_RS740
	.comm	_RS690_MC_AGP_LOCATION,4,2      ## @RS690_MC_AGP_LOCATION
	.comm	_CHIP_RS600,4,2                 ## @CHIP_RS600
	.comm	_RS600_MC_AGP_LOCATION,4,2      ## @RS600_MC_AGP_LOCATION
	.comm	_R520_MC_AGP_LOCATION,4,2       ## @R520_MC_AGP_LOCATION
	.comm	_RADEON_MC_AGP_LOCATION,4,2     ## @RADEON_MC_AGP_LOCATION
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_write_agp_location      ; -- Begin function radeon_write_agp_location
	.p2align	2
_radeon_write_agp_location:             ; @radeon_write_agp_location
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x1
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _RADEON_FAMILY_MASK@GOTPAGE
Lloh1:
	ldr	x9, [x9, _RADEON_FAMILY_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	and	w8, w9, w8
Lloh3:
	adrp	x9, _CHIP_RV770@GOTPAGE
Lloh4:
	ldr	x9, [x9, _CHIP_RV770@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ge	LBB0_5
; %bb.1:
Lloh6:
	adrp	x9, _CHIP_R600@GOTPAGE
Lloh7:
	ldr	x9, [x9, _CHIP_R600@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ge	LBB0_6
; %bb.2:
Lloh9:
	adrp	x9, _CHIP_RV515@GOTPAGE
Lloh10:
	ldr	x9, [x9, _CHIP_RV515@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_9
; %bb.3:
Lloh12:
	adrp	x8, _RV515_MC_AGP_LOCATION@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RV515_MC_AGP_LOCATION@GOTPAGEOFF]
LBB0_4:
	ldr	w0, [x8]
	mov	x1, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_R500_WRITE_MCIND
LBB0_5:
Lloh14:
	adrp	x8, _R700_MC_VM_AGP_BOT@GOTPAGE
Lloh15:
	ldr	x8, [x8, _R700_MC_VM_AGP_BOT@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
	and	w1, w19, #0xffff
	bl	_RADEON_WRITE
Lloh17:
	adrp	x8, _R700_MC_VM_AGP_TOP@GOTPAGE
Lloh18:
	ldr	x8, [x8, _R700_MC_VM_AGP_TOP@GOTPAGEOFF]
	b	LBB0_7
LBB0_6:
Lloh19:
	adrp	x8, _R600_MC_VM_AGP_BOT@GOTPAGE
Lloh20:
	ldr	x8, [x8, _R600_MC_VM_AGP_BOT@GOTPAGEOFF]
Lloh21:
	ldr	w0, [x8]
	and	w1, w19, #0xffff
	bl	_RADEON_WRITE
Lloh22:
	adrp	x8, _R600_MC_VM_AGP_TOP@GOTPAGE
Lloh23:
	ldr	x8, [x8, _R600_MC_VM_AGP_TOP@GOTPAGEOFF]
LBB0_7:
	ldr	w0, [x8]
	lsr	w1, w19, #16
LBB0_8:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_RADEON_WRITE
LBB0_9:
Lloh24:
	adrp	x10, _CHIP_RS690@GOTPAGE
Lloh25:
	ldr	x10, [x10, _CHIP_RS690@GOTPAGEOFF]
Lloh26:
	ldr	w10, [x10]
Lloh27:
	adrp	x11, _CHIP_RS740@GOTPAGE
Lloh28:
	ldr	x11, [x11, _CHIP_RS740@GOTPAGEOFF]
Lloh29:
	ldr	w11, [x11]
	cmp	w8, w10
	ccmp	w8, w11, #4, ne
	b.ne	LBB0_11
; %bb.10:
Lloh30:
	adrp	x8, _RS690_MC_AGP_LOCATION@GOTPAGE
Lloh31:
	ldr	x8, [x8, _RS690_MC_AGP_LOCATION@GOTPAGEOFF]
Lloh32:
	ldr	w0, [x8]
	mov	x1, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_RS690_WRITE_MCIND
LBB0_11:
Lloh33:
	adrp	x10, _CHIP_RS600@GOTPAGE
Lloh34:
	ldr	x10, [x10, _CHIP_RS600@GOTPAGEOFF]
Lloh35:
	ldr	w10, [x10]
	cmp	w8, w10
	b.ne	LBB0_13
; %bb.12:
Lloh36:
	adrp	x8, _RS600_MC_AGP_LOCATION@GOTPAGE
Lloh37:
	ldr	x8, [x8, _RS600_MC_AGP_LOCATION@GOTPAGEOFF]
Lloh38:
	ldr	w0, [x8]
	mov	x1, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_RS600_WRITE_MCIND
LBB0_13:
	cmp	w8, w9
	b.le	LBB0_15
; %bb.14:
Lloh39:
	adrp	x8, _R520_MC_AGP_LOCATION@GOTPAGE
Lloh40:
	ldr	x8, [x8, _R520_MC_AGP_LOCATION@GOTPAGEOFF]
	b	LBB0_4
LBB0_15:
Lloh41:
	adrp	x8, _RADEON_MC_AGP_LOCATION@GOTPAGE
Lloh42:
	ldr	x8, [x8, _RADEON_MC_AGP_LOCATION@GOTPAGEOFF]
Lloh43:
	ldr	w0, [x8]
	mov	x1, x19
	b	LBB0_8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_FAMILY_MASK,4,2         ; @RADEON_FAMILY_MASK
	.comm	_CHIP_RV770,4,2                 ; @CHIP_RV770
	.comm	_R700_MC_VM_AGP_BOT,4,2         ; @R700_MC_VM_AGP_BOT
	.comm	_R700_MC_VM_AGP_TOP,4,2         ; @R700_MC_VM_AGP_TOP
	.comm	_CHIP_R600,4,2                  ; @CHIP_R600
	.comm	_R600_MC_VM_AGP_BOT,4,2         ; @R600_MC_VM_AGP_BOT
	.comm	_R600_MC_VM_AGP_TOP,4,2         ; @R600_MC_VM_AGP_TOP
	.comm	_CHIP_RV515,4,2                 ; @CHIP_RV515
	.comm	_RV515_MC_AGP_LOCATION,4,2      ; @RV515_MC_AGP_LOCATION
	.comm	_CHIP_RS690,4,2                 ; @CHIP_RS690
	.comm	_CHIP_RS740,4,2                 ; @CHIP_RS740
	.comm	_RS690_MC_AGP_LOCATION,4,2      ; @RS690_MC_AGP_LOCATION
	.comm	_CHIP_RS600,4,2                 ; @CHIP_RS600
	.comm	_RS600_MC_AGP_LOCATION,4,2      ; @RS600_MC_AGP_LOCATION
	.comm	_R520_MC_AGP_LOCATION,4,2       ; @R520_MC_AGP_LOCATION
	.comm	_RADEON_MC_AGP_LOCATION,4,2     ; @RADEON_MC_AGP_LOCATION
.subsections_via_symbols
