	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_gem_info_ioctl          ## -- Begin function radeon_gem_info_ioctl
	.p2align	4, 0x90
_radeon_gem_info_ioctl:                 ## @radeon_gem_info_ioctl
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rsi, %r14
	movq	(%rdi), %rbx
	movq	24(%rbx), %rax
	movq	_TTM_PL_VRAM@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	12(%rbx), %edx
	movl	%edx, 8(%rsi)
	movl	(%rax,%rcx,8), %eax
	movq	_PAGE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	movl	%eax, (%rsi)
	movq	16(%rbx), %rdi
	testq	%rdi, %rdi
	je	LBB0_2
## %bb.1:
	callq	_radeon_bo_size
	subl	%eax, (%r14)
LBB0_2:
	movq	%rbx, %rdi
	callq	_radeon_fbdev_total_size
	subl	%eax, (%r14)
	movl	8(%rbx), %eax
	movq	_RADEON_IB_POOL_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	shll	$16, %ecx
	negl	%ecx
	leal	(%rax,%rcx), %esi
	addl	$-4096, %esi                    ## imm = 0xF000
	movl	%esi, 4(%r14)
	movq	_RADEON_NUM_RINGS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testq	%rax, %rax
	je	LBB0_15
## %bb.3:
	movq	(%rbx), %rcx
	cmpl	$8, %eax
	jae	LBB0_5
## %bb.4:
	xorl	%edx, %edx
	jmp	LBB0_13
LBB0_5:
	movl	%eax, %edx
	andl	$-8, %edx
	movd	%esi, %xmm0
	leaq	-8(%rdx), %rdi
	movq	%rdi, %rsi
	shrq	$3, %rsi
	incq	%rsi
	movl	%esi, %ebx
	andl	$3, %ebx
	cmpq	$24, %rdi
	jae	LBB0_7
## %bb.6:
	pxor	%xmm1, %xmm1
	xorl	%edi, %edi
	jmp	LBB0_9
LBB0_7:
	andq	$-4, %rsi
	pxor	%xmm1, %xmm1
	xorl	%edi, %edi
	.p2align	4, 0x90
LBB0_8:                                 ## =>This Inner Loop Header: Depth=1
	movdqu	(%rcx,%rdi,4), %xmm2
	movdqu	16(%rcx,%rdi,4), %xmm3
	movdqu	32(%rcx,%rdi,4), %xmm4
	paddd	%xmm2, %xmm4
	movdqu	48(%rcx,%rdi,4), %xmm2
	paddd	%xmm3, %xmm2
	movdqu	64(%rcx,%rdi,4), %xmm3
	movdqu	80(%rcx,%rdi,4), %xmm5
	movdqu	96(%rcx,%rdi,4), %xmm6
	paddd	%xmm3, %xmm6
	paddd	%xmm4, %xmm6
	psubd	%xmm6, %xmm0
	movdqu	112(%rcx,%rdi,4), %xmm3
	paddd	%xmm5, %xmm3
	paddd	%xmm2, %xmm3
	psubd	%xmm3, %xmm1
	addq	$32, %rdi
	addq	$-4, %rsi
	jne	LBB0_8
LBB0_9:
	testq	%rbx, %rbx
	je	LBB0_12
## %bb.10:
	leaq	(%rcx,%rdi,4), %rsi
	addq	$16, %rsi
	shlq	$5, %rbx
	xorl	%edi, %edi
	.p2align	4, 0x90
LBB0_11:                                ## =>This Inner Loop Header: Depth=1
	movdqu	-16(%rsi,%rdi), %xmm2
	psubd	%xmm2, %xmm0
	movdqu	(%rsi,%rdi), %xmm2
	psubd	%xmm2, %xmm1
	addq	$32, %rdi
	cmpq	%rdi, %rbx
	jne	LBB0_11
LBB0_12:
	paddd	%xmm1, %xmm0
	pshufd	$238, %xmm0, %xmm1              ## xmm1 = xmm0[2,3,2,3]
	paddd	%xmm0, %xmm1
	pshufd	$85, %xmm1, %xmm0               ## xmm0 = xmm1[1,1,1,1]
	paddd	%xmm1, %xmm0
	movd	%xmm0, %esi
	cmpq	%rax, %rdx
	je	LBB0_14
	.p2align	4, 0x90
LBB0_13:                                ## =>This Inner Loop Header: Depth=1
	subl	(%rcx,%rdx,4), %esi
	incq	%rdx
	cmpq	%rdx, %rax
	jne	LBB0_13
LBB0_14:
	movl	%esi, 4(%r14)
LBB0_15:
	xorl	%eax, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_TTM_PL_VRAM,8,3                ## @TTM_PL_VRAM
	.comm	_PAGE_SHIFT,4,2                 ## @PAGE_SHIFT
	.comm	_RADEON_IB_POOL_SIZE,4,2        ## @RADEON_IB_POOL_SIZE
	.comm	_RADEON_NUM_RINGS,4,2           ## @RADEON_NUM_RINGS
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_gem_info_ioctl          ; -- Begin function radeon_gem_info_ioctl
	.p2align	2
_radeon_gem_info_ioctl:                 ; @radeon_gem_info_ioctl
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x1
	ldr	x20, [x0]
Lloh0:
	adrp	x8, _TTM_PL_VRAM@GOTPAGE
Lloh1:
	ldr	x8, [x8, _TTM_PL_VRAM@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	ldr	w9, [x20, #12]
	ldp	x0, x10, [x20, #16]
	ldr	x8, [x10, x8, lsl #3]
	str	w9, [x1, #8]
Lloh3:
	adrp	x9, _PAGE_SHIFT@GOTPAGE
Lloh4:
	ldr	x9, [x9, _PAGE_SHIFT@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	str	w8, [x1]
	cbz	x0, LBB0_2
; %bb.1:
	bl	_radeon_bo_size
	ldr	w8, [x19]
	sub	w8, w8, w0
	str	w8, [x19]
LBB0_2:
	mov	x0, x20
	bl	_radeon_fbdev_total_size
	ldr	w8, [x19]
	sub	w8, w8, w0
	str	w8, [x19]
	ldr	w8, [x20, #8]
Lloh6:
	adrp	x9, _RADEON_IB_POOL_SIZE@GOTPAGE
Lloh7:
	ldr	x9, [x9, _RADEON_IB_POOL_SIZE@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	sub	w8, w8, w9, lsl #16
	sub	w10, w8, #1, lsl #12            ; =4096
	str	w10, [x19, #4]
Lloh9:
	adrp	x8, _RADEON_NUM_RINGS@GOTPAGE
Lloh10:
	ldr	x8, [x8, _RADEON_NUM_RINGS@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	cbz	w8, LBB0_11
; %bb.3:
	ldr	x9, [x20]
	cmp	w8, #16
	b.hs	LBB0_5
; %bb.4:
	mov	x11, #0
	b	LBB0_8
LBB0_5:
	and	x11, x8, #0xfffffff0
	movi.2d	v0, #0000000000000000
	movi.2d	v1, #0000000000000000
	mov.s	v1[0], w10
	add	x10, x9, #32
	mov	x12, x11
	movi.2d	v2, #0000000000000000
	movi.2d	v3, #0000000000000000
LBB0_6:                                 ; =>This Inner Loop Header: Depth=1
	ldp	q4, q5, [x10, #-32]
	ldp	q6, q7, [x10], #64
	sub.4s	v1, v1, v4
	sub.4s	v0, v0, v5
	sub.4s	v2, v2, v6
	sub.4s	v3, v3, v7
	subs	x12, x12, #16
	b.ne	LBB0_6
; %bb.7:
	add.4s	v0, v0, v1
	add.4s	v0, v2, v0
	add.4s	v0, v3, v0
	addv.4s	s0, v0
	fmov	w10, s0
	cmp	x11, x8
	b.eq	LBB0_10
LBB0_8:
	add	x9, x9, x11, lsl #2
	sub	x8, x8, x11
LBB0_9:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w11, [x9], #4
	sub	w10, w10, w11
	subs	x8, x8, #1
	b.ne	LBB0_9
LBB0_10:
	str	w10, [x19, #4]
LBB0_11:
	mov	w0, #0
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_TTM_PL_VRAM,8,3                ; @TTM_PL_VRAM
	.comm	_PAGE_SHIFT,4,2                 ; @PAGE_SHIFT
	.comm	_RADEON_IB_POOL_SIZE,4,2        ; @RADEON_IB_POOL_SIZE
	.comm	_RADEON_NUM_RINGS,4,2           ; @RADEON_NUM_RINGS
.subsections_via_symbols
