	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tg3_phy_autoneg_cfg
_tg3_phy_autoneg_cfg:                   ## @tg3_phy_autoneg_cfg
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r15d
	movl	%esi, %r12d
	movq	%rdi, %r14
	movq	_ADVERTISE_CSMA@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%esi, %edi
	callq	_ethtool_adv_to_mii_adv_t
	movl	%eax, %r13d
	movq	_ADVERTISE_ALL@GOTPCREL(%rip), %rax
	andl	(%rax), %r13d
	movl	%r15d, %edi
	callq	_mii_advertise_flowctrl
	orl	%eax, %ebx
	orl	%r13d, %ebx
	movq	_MII_ADVERTISE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%ebx, %edx
	callq	_tg3_writephy
	testl	%eax, %eax
	je	LBB0_1
LBB0_29:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_1:
	movl	(%r14), %eax
	movq	_TG3_PHYFLG_10_100_ONLY@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_2
LBB0_7:
	movq	_TG3_PHYFLG_EEE_CAP@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_8
## %bb.9:
	movq	_TG3_CPMU_EEE_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%ebx, %edi
	callq	_tr32
	movq	_TG3_CPMU_EEEMD_LPI_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	%ebx, %edi
	callq	_tw32
	movq	%r14, %rdi
	movl	$1, %esi
	callq	_tg3_phy_toggle_auxctl_smdsp
	testl	%eax, %eax
	jne	LBB0_29
## %bb.10:
	movl	$0, -44(%rbp)
	movq	_ADVERTISED_100baseT_Full@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%r12d, %eax
	je	LBB0_11
## %bb.12:
	movq	_MDIO_AN_EEE_ADV_100TX@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r15d
	movl	%r15d, -44(%rbp)
	jmp	LBB0_13
LBB0_2:
	movl	%r12d, %edi
	callq	_ethtool_adv_to_mii_ctrl1000_t
	movl	%eax, %r15d
	movq	%r14, %rdi
	callq	_tg3_chip_rev_id
	movq	_CHIPREV_ID_5701_A0@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_4
## %bb.3:
	movq	%r14, %rdi
	callq	_tg3_chip_rev_id
	movq	_CHIPREV_ID_5701_B0@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_5
LBB0_4:
	movq	_CTL1000_AS_MASTER@GOTPCREL(%rip), %rax
	movq	_CTL1000_ENABLE_MASTER@GOTPCREL(%rip), %rcx
	orl	(%rax), %r15d
	orl	(%rcx), %r15d
LBB0_5:
	movq	_MII_CTRL1000@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r15d, %edx
	callq	_tg3_writephy
	testl	%eax, %eax
	jne	LBB0_29
## %bb.6:
	movl	(%r14), %eax
	jmp	LBB0_7
LBB0_8:
	xorl	%eax, %eax
	jmp	LBB0_29
LBB0_11:
	xorl	%r15d, %r15d
LBB0_13:
	movq	_ADVERTISED_1000baseT_Full@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%r12d, %ecx
	je	LBB0_15
## %bb.14:
	movq	_MDIO_AN_EEE_ADV_1000T@GOTPCREL(%rip), %rdx
	orl	(%rdx), %r15d
	movl	%r15d, -44(%rbp)
LBB0_15:
	cmpl	$0, 8(%r14)
	je	LBB0_16
## %bb.17:
	orl	%eax, %ecx
	andl	%r12d, %ecx
	jmp	LBB0_18
LBB0_16:
	movl	$0, -44(%rbp)
	xorl	%r15d, %r15d
	xorl	%ecx, %ecx
LBB0_18:
	movl	%ecx, 4(%r14)
	movq	_MDIO_MMD_AN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MDIO_AN_EEE_ADV@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	movl	%r15d, %ecx
	callq	_tg3_phy_cl45_write
	movl	%eax, %ebx
	testl	%eax, %eax
	je	LBB0_20
## %bb.19:
	movl	$0, -44(%rbp)
	xorl	%r15d, %r15d
LBB0_20:
	movq	%r14, %rdi
	callq	_tg3_asic_rev
	addl	$-128, %eax
	cmpl	$5, %eax
	ja	LBB0_28
## %bb.21:
	movl	$51, %ecx
	btl	%eax, %ecx
	jae	LBB0_26
## %bb.22:
	testl	%r15d, %r15d
	je	LBB0_23
## %bb.24:
	movq	_MII_TG3_DSP_TAP26_ALNOKO@GOTPCREL(%rip), %rax
	movq	_MII_TG3_DSP_TAP26_RMRXSTO@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	_MII_TG3_DSP_TAP26_OPCSINPT@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	%edx, -44(%rbp)
	jmp	LBB0_25
LBB0_23:
	xorl	%edx, %edx
LBB0_25:
	movq	_MII_TG3_DSP_TAP26@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_tg3_phydsp_write
LBB0_26:
	movq	_MII_TG3_DSP_CH34TP2@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	leaq	-44(%rbp), %rdx
	movq	%r14, %rdi
	callq	_tg3_phydsp_read
	testl	%eax, %eax
	jne	LBB0_28
## %bb.27:
	movl	(%r15), %esi
	movq	_MII_TG3_DSP_CH34TP2_HIBW01@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	orl	-44(%rbp), %edx
	movq	%r14, %rdi
	callq	_tg3_phydsp_write
LBB0_28:
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_tg3_phy_toggle_auxctl_smdsp
	testl	%ebx, %ebx
	cmovnel	%ebx, %eax
	jmp	LBB0_29
	.cfi_endproc
                                        ## -- End function
	.comm	_ADVERTISE_CSMA,4,2             ## @ADVERTISE_CSMA
	.comm	_ADVERTISE_ALL,4,2              ## @ADVERTISE_ALL
	.comm	_MII_ADVERTISE,4,2              ## @MII_ADVERTISE
	.comm	_TG3_PHYFLG_10_100_ONLY,4,2     ## @TG3_PHYFLG_10_100_ONLY
	.comm	_CHIPREV_ID_5701_A0,8,3         ## @CHIPREV_ID_5701_A0
	.comm	_CHIPREV_ID_5701_B0,8,3         ## @CHIPREV_ID_5701_B0
	.comm	_CTL1000_AS_MASTER,4,2          ## @CTL1000_AS_MASTER
	.comm	_CTL1000_ENABLE_MASTER,4,2      ## @CTL1000_ENABLE_MASTER
	.comm	_MII_CTRL1000,4,2               ## @MII_CTRL1000
	.comm	_TG3_PHYFLG_EEE_CAP,4,2         ## @TG3_PHYFLG_EEE_CAP
	.comm	_TG3_CPMU_EEE_MODE,4,2          ## @TG3_CPMU_EEE_MODE
	.comm	_TG3_CPMU_EEEMD_LPI_ENABLE,4,2  ## @TG3_CPMU_EEEMD_LPI_ENABLE
	.comm	_ADVERTISED_100baseT_Full,4,2   ## @ADVERTISED_100baseT_Full
	.comm	_MDIO_AN_EEE_ADV_100TX,4,2      ## @MDIO_AN_EEE_ADV_100TX
	.comm	_ADVERTISED_1000baseT_Full,4,2  ## @ADVERTISED_1000baseT_Full
	.comm	_MDIO_AN_EEE_ADV_1000T,4,2      ## @MDIO_AN_EEE_ADV_1000T
	.comm	_MDIO_MMD_AN,4,2                ## @MDIO_MMD_AN
	.comm	_MDIO_AN_EEE_ADV,4,2            ## @MDIO_AN_EEE_ADV
	.comm	_MII_TG3_DSP_TAP26_ALNOKO,4,2   ## @MII_TG3_DSP_TAP26_ALNOKO
	.comm	_MII_TG3_DSP_TAP26_RMRXSTO,4,2  ## @MII_TG3_DSP_TAP26_RMRXSTO
	.comm	_MII_TG3_DSP_TAP26_OPCSINPT,4,2 ## @MII_TG3_DSP_TAP26_OPCSINPT
	.comm	_MII_TG3_DSP_TAP26,4,2          ## @MII_TG3_DSP_TAP26
	.comm	_MII_TG3_DSP_CH34TP2,4,2        ## @MII_TG3_DSP_CH34TP2
	.comm	_MII_TG3_DSP_CH34TP2_HIBW01,4,2 ## @MII_TG3_DSP_CH34TP2_HIBW01
	.no_dead_strip	_tg3_phy_autoneg_cfg
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tg3_phy_autoneg_cfg
_tg3_phy_autoneg_cfg:                   ; @tg3_phy_autoneg_cfg
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x21, x2
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x8, _ADVERTISE_CSMA@GOTPAGE
Lloh1:
	ldr	x8, [x8, _ADVERTISE_CSMA@GOTPAGEOFF]
Lloh2:
	ldr	w22, [x8]
	mov	x0, x1
	bl	_ethtool_adv_to_mii_adv_t
Lloh3:
	adrp	x8, _ADVERTISE_ALL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _ADVERTISE_ALL@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	and	w8, w8, w0
	orr	w22, w8, w22
	mov	x0, x21
	bl	_mii_advertise_flowctrl
	orr	w2, w22, w0
Lloh6:
	adrp	x8, _MII_ADVERTISE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _MII_ADVERTISE@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_tg3_writephy
	cbz	w0, LBB0_2
LBB0_1:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
LBB0_2:
	ldr	w8, [x19]
Lloh9:
	adrp	x9, _TG3_PHYFLG_10_100_ONLY@GOTPAGE
Lloh10:
	ldr	x9, [x9, _TG3_PHYFLG_10_100_ONLY@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_7
LBB0_3:
Lloh12:
	adrp	x9, _TG3_PHYFLG_EEE_CAP@GOTPAGE
Lloh13:
	ldr	x9, [x9, _TG3_PHYFLG_EEE_CAP@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_12
; %bb.4:
Lloh15:
	adrp	x8, _TG3_CPMU_EEE_MODE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _TG3_CPMU_EEE_MODE@GOTPAGEOFF]
Lloh17:
	ldr	w21, [x8]
	mov	x0, x21
	bl	_tr32
Lloh18:
	adrp	x8, _TG3_CPMU_EEEMD_LPI_ENABLE@GOTPAGE
Lloh19:
	ldr	x8, [x8, _TG3_CPMU_EEEMD_LPI_ENABLE@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	bic	w1, w0, w8
	mov	x0, x21
	bl	_tw32
	mov	x0, x19
	mov	w1, #1
	bl	_tg3_phy_toggle_auxctl_smdsp
	cbnz	w0, LBB0_1
; %bb.5:
	str	wzr, [sp, #12]
Lloh21:
	adrp	x8, _ADVERTISED_100baseT_Full@GOTPAGE
Lloh22:
	ldr	x8, [x8, _ADVERTISED_100baseT_Full@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_13
; %bb.6:
Lloh24:
	adrp	x9, _MDIO_AN_EEE_ADV_100TX@GOTPAGE
Lloh25:
	ldr	x9, [x9, _MDIO_AN_EEE_ADV_100TX@GOTPAGEOFF]
Lloh26:
	ldr	w21, [x9]
	str	w21, [sp, #12]
	b	LBB0_14
LBB0_7:
	mov	x0, x20
	bl	_ethtool_adv_to_mii_ctrl1000_t
	mov	x21, x0
	mov	x0, x19
	bl	_tg3_chip_rev_id
Lloh27:
	adrp	x8, _CHIPREV_ID_5701_A0@GOTPAGE
Lloh28:
	ldr	x8, [x8, _CHIPREV_ID_5701_A0@GOTPAGEOFF]
Lloh29:
	ldr	x8, [x8]
	cmp	x0, x8
	b.eq	LBB0_9
; %bb.8:
	mov	x0, x19
	bl	_tg3_chip_rev_id
Lloh30:
	adrp	x8, _CHIPREV_ID_5701_B0@GOTPAGE
Lloh31:
	ldr	x8, [x8, _CHIPREV_ID_5701_B0@GOTPAGEOFF]
Lloh32:
	ldr	x8, [x8]
	cmp	x0, x8
	b.ne	LBB0_10
LBB0_9:
Lloh33:
	adrp	x8, _CTL1000_AS_MASTER@GOTPAGE
Lloh34:
	ldr	x8, [x8, _CTL1000_AS_MASTER@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
Lloh36:
	adrp	x9, _CTL1000_ENABLE_MASTER@GOTPAGE
Lloh37:
	ldr	x9, [x9, _CTL1000_ENABLE_MASTER@GOTPAGEOFF]
Lloh38:
	ldr	w9, [x9]
	orr	w8, w8, w21
	orr	w21, w8, w9
LBB0_10:
Lloh39:
	adrp	x8, _MII_CTRL1000@GOTPAGE
Lloh40:
	ldr	x8, [x8, _MII_CTRL1000@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_tg3_writephy
	cbnz	w0, LBB0_1
; %bb.11:
	ldr	w8, [x19]
	b	LBB0_3
LBB0_12:
	mov	w0, #0
	b	LBB0_1
LBB0_13:
	mov	w21, #0
LBB0_14:
Lloh42:
	adrp	x9, _ADVERTISED_1000baseT_Full@GOTPAGE
Lloh43:
	ldr	x9, [x9, _ADVERTISED_1000baseT_Full@GOTPAGEOFF]
Lloh44:
	ldr	w9, [x9]
	tst	w9, w20
	b.eq	LBB0_16
; %bb.15:
Lloh45:
	adrp	x10, _MDIO_AN_EEE_ADV_1000T@GOTPAGE
Lloh46:
	ldr	x10, [x10, _MDIO_AN_EEE_ADV_1000T@GOTPAGEOFF]
Lloh47:
	ldr	w10, [x10]
	orr	w21, w21, w10
	str	w21, [sp, #12]
LBB0_16:
	ldr	w10, [x19, #8]
	cbz	w10, LBB0_18
; %bb.17:
	orr	w8, w9, w8
	and	w8, w8, w20
	b	LBB0_19
LBB0_18:
	mov	w21, #0
	mov	w8, #0
	str	wzr, [sp, #12]
LBB0_19:
	str	w8, [x19, #4]
Lloh48:
	adrp	x8, _MDIO_MMD_AN@GOTPAGE
Lloh49:
	ldr	x8, [x8, _MDIO_MMD_AN@GOTPAGEOFF]
Lloh50:
	ldr	w1, [x8]
Lloh51:
	adrp	x8, _MDIO_AN_EEE_ADV@GOTPAGE
Lloh52:
	ldr	x8, [x8, _MDIO_AN_EEE_ADV@GOTPAGEOFF]
Lloh53:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x3, x21
	bl	_tg3_phy_cl45_write
	mov	x20, x0
	cbz	w0, LBB0_21
; %bb.20:
	mov	w21, #0
	str	wzr, [sp, #12]
LBB0_21:
	mov	x0, x19
	bl	_tg3_asic_rev
	sub	w8, w0, #128
	cmp	w8, #5
	b.hi	LBB0_29
; %bb.22:
	mov	w9, #1
	lsl	w8, w9, w8
	mov	w9, #51
	tst	w8, w9
	b.eq	LBB0_27
; %bb.23:
	cbz	w21, LBB0_25
; %bb.24:
Lloh54:
	adrp	x8, _MII_TG3_DSP_TAP26_ALNOKO@GOTPAGE
Lloh55:
	ldr	x8, [x8, _MII_TG3_DSP_TAP26_ALNOKO@GOTPAGEOFF]
Lloh56:
	ldr	w8, [x8]
Lloh57:
	adrp	x9, _MII_TG3_DSP_TAP26_RMRXSTO@GOTPAGE
Lloh58:
	ldr	x9, [x9, _MII_TG3_DSP_TAP26_RMRXSTO@GOTPAGEOFF]
Lloh59:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh60:
	adrp	x9, _MII_TG3_DSP_TAP26_OPCSINPT@GOTPAGE
Lloh61:
	ldr	x9, [x9, _MII_TG3_DSP_TAP26_OPCSINPT@GOTPAGEOFF]
Lloh62:
	ldr	w9, [x9]
	orr	w2, w8, w9
	str	w2, [sp, #12]
	b	LBB0_26
LBB0_25:
	mov	w2, #0
LBB0_26:
Lloh63:
	adrp	x8, _MII_TG3_DSP_TAP26@GOTPAGE
Lloh64:
	ldr	x8, [x8, _MII_TG3_DSP_TAP26@GOTPAGEOFF]
Lloh65:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_tg3_phydsp_write
LBB0_27:
Lloh66:
	adrp	x21, _MII_TG3_DSP_CH34TP2@GOTPAGE
Lloh67:
	ldr	x21, [x21, _MII_TG3_DSP_CH34TP2@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x2, sp, #12
	mov	x0, x19
	bl	_tg3_phydsp_read
	cbnz	w0, LBB0_29
; %bb.28:
	ldr	w1, [x21]
	ldr	w8, [sp, #12]
Lloh68:
	adrp	x9, _MII_TG3_DSP_CH34TP2_HIBW01@GOTPAGE
Lloh69:
	ldr	x9, [x9, _MII_TG3_DSP_CH34TP2_HIBW01@GOTPAGEOFF]
Lloh70:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_tg3_phydsp_write
LBB0_29:
	mov	x0, x19
	mov	w1, #0
	bl	_tg3_phy_toggle_auxctl_smdsp
	cmp	w20, #0
	csel	w0, w0, w20, eq
	b	LBB0_1
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGot	Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.cfi_endproc
                                        ; -- End function
	.comm	_ADVERTISE_CSMA,4,2             ; @ADVERTISE_CSMA
	.comm	_ADVERTISE_ALL,4,2              ; @ADVERTISE_ALL
	.comm	_MII_ADVERTISE,4,2              ; @MII_ADVERTISE
	.comm	_TG3_PHYFLG_10_100_ONLY,4,2     ; @TG3_PHYFLG_10_100_ONLY
	.comm	_CHIPREV_ID_5701_A0,8,3         ; @CHIPREV_ID_5701_A0
	.comm	_CHIPREV_ID_5701_B0,8,3         ; @CHIPREV_ID_5701_B0
	.comm	_CTL1000_AS_MASTER,4,2          ; @CTL1000_AS_MASTER
	.comm	_CTL1000_ENABLE_MASTER,4,2      ; @CTL1000_ENABLE_MASTER
	.comm	_MII_CTRL1000,4,2               ; @MII_CTRL1000
	.comm	_TG3_PHYFLG_EEE_CAP,4,2         ; @TG3_PHYFLG_EEE_CAP
	.comm	_TG3_CPMU_EEE_MODE,4,2          ; @TG3_CPMU_EEE_MODE
	.comm	_TG3_CPMU_EEEMD_LPI_ENABLE,4,2  ; @TG3_CPMU_EEEMD_LPI_ENABLE
	.comm	_ADVERTISED_100baseT_Full,4,2   ; @ADVERTISED_100baseT_Full
	.comm	_MDIO_AN_EEE_ADV_100TX,4,2      ; @MDIO_AN_EEE_ADV_100TX
	.comm	_ADVERTISED_1000baseT_Full,4,2  ; @ADVERTISED_1000baseT_Full
	.comm	_MDIO_AN_EEE_ADV_1000T,4,2      ; @MDIO_AN_EEE_ADV_1000T
	.comm	_MDIO_MMD_AN,4,2                ; @MDIO_MMD_AN
	.comm	_MDIO_AN_EEE_ADV,4,2            ; @MDIO_AN_EEE_ADV
	.comm	_MII_TG3_DSP_TAP26_ALNOKO,4,2   ; @MII_TG3_DSP_TAP26_ALNOKO
	.comm	_MII_TG3_DSP_TAP26_RMRXSTO,4,2  ; @MII_TG3_DSP_TAP26_RMRXSTO
	.comm	_MII_TG3_DSP_TAP26_OPCSINPT,4,2 ; @MII_TG3_DSP_TAP26_OPCSINPT
	.comm	_MII_TG3_DSP_TAP26,4,2          ; @MII_TG3_DSP_TAP26
	.comm	_MII_TG3_DSP_CH34TP2,4,2        ; @MII_TG3_DSP_CH34TP2
	.comm	_MII_TG3_DSP_CH34TP2_HIBW01,4,2 ; @MII_TG3_DSP_CH34TP2_HIBW01
	.no_dead_strip	_tg3_phy_autoneg_cfg
.subsections_via_symbols
