	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function intel_dp_set_signal_levels
_intel_dp_set_signal_levels:            ## @intel_dp_set_signal_levels
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %r12
	callq	_dp_to_dig_port
	movq	(%rax), %rbx
	movq	(%r12), %rax
	movl	(%rax), %r15d
	movq	%rbx, %rdi
	callq	_IS_HASWELL
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movl	%r15d, %edi
	callq	_intel_hsw_signal_levels
	movl	%eax, %r15d
	movq	_DDI_BUF_EMP_MASK@GOTPCREL(%rip), %rax
LBB0_10:
	movl	(%rax), %ebx
LBB0_11:
	leaq	L_.str(%rip), %rdi
	movl	%r15d, %esi
	callq	_DRM_DEBUG_KMS
	notl	%ebx
	andl	(%r14), %ebx
	orl	%r15d, %ebx
	movl	%ebx, (%r14)
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	movq	%rbx, %rdi
	callq	_IS_GEN7
	testq	%rax, %rax
	je	LBB0_5
## %bb.3:
	movq	%r12, %rdi
	callq	_is_cpu_edp
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	movq	%rbx, %rdi
	callq	_IS_VALLEYVIEW
	testl	%eax, %eax
	je	LBB0_9
LBB0_5:
	movq	%rbx, %rdi
	callq	_IS_GEN6
	testq	%rax, %rax
	je	LBB0_8
## %bb.6:
	movq	%r12, %rdi
	callq	_is_cpu_edp
	testq	%rax, %rax
	je	LBB0_8
## %bb.7:
	movl	%r15d, %edi
	callq	_intel_gen6_edp_signal_levels
	movl	%eax, %r15d
	movq	_EDP_LINK_TRAIN_VOL_EMP_MASK_SNB@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_8:
	movl	%r15d, %edi
	callq	_intel_gen4_signal_levels
	movl	%eax, %r15d
	movq	_DP_VOLTAGE_MASK@GOTPCREL(%rip), %rax
	movq	_DP_PRE_EMPHASIS_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	jmp	LBB0_11
LBB0_9:
	movl	%r15d, %edi
	callq	_intel_gen7_edp_signal_levels
	movl	%eax, %r15d
	movq	_EDP_LINK_TRAIN_VOL_EMP_MASK_IVB@GOTPCREL(%rip), %rax
	jmp	LBB0_10
	.cfi_endproc
                                        ## -- End function
	.comm	_DDI_BUF_EMP_MASK,4,2           ## @DDI_BUF_EMP_MASK
	.comm	_EDP_LINK_TRAIN_VOL_EMP_MASK_IVB,4,2 ## @EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
	.comm	_EDP_LINK_TRAIN_VOL_EMP_MASK_SNB,4,2 ## @EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
	.comm	_DP_VOLTAGE_MASK,4,2            ## @DP_VOLTAGE_MASK
	.comm	_DP_PRE_EMPHASIS_MASK,4,2       ## @DP_PRE_EMPHASIS_MASK
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Using signal levels %08x\n"

	.no_dead_strip	_intel_dp_set_signal_levels
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function intel_dp_set_signal_levels
_intel_dp_set_signal_levels:            ; @intel_dp_set_signal_levels
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x1
	mov	x21, x0
	bl	_dp_to_dig_port
	ldr	x22, [x0]
	ldr	x8, [x21]
	ldr	w20, [x8]
	mov	x0, x22
	bl	_IS_HASWELL
	cbz	x0, LBB0_4
; %bb.1:
	mov	x0, x20
	bl	_intel_hsw_signal_levels
	mov	x20, x0
Lloh0:
	adrp	x8, _DDI_BUF_EMP_MASK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DDI_BUF_EMP_MASK@GOTPAGEOFF]
LBB0_2:
	ldr	w21, [x8]
LBB0_3:
Lloh2:
	adrp	x0, l_.str@PAGE
Lloh3:
	add	x0, x0, l_.str@PAGEOFF
	mov	x1, x20
	bl	_DRM_DEBUG_KMS
	ldr	w8, [x19]
	bic	w8, w8, w21
	orr	w8, w8, w20
	str	w8, [x19]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_4:
	mov	x0, x22
	bl	_IS_GEN7
	cbz	x0, LBB0_7
; %bb.5:
	mov	x0, x21
	bl	_is_cpu_edp
	cbz	x0, LBB0_7
; %bb.6:
	mov	x0, x22
	bl	_IS_VALLEYVIEW
	cbz	w0, LBB0_11
LBB0_7:
	mov	x0, x22
	bl	_IS_GEN6
	cbz	x0, LBB0_10
; %bb.8:
	mov	x0, x21
	bl	_is_cpu_edp
	cbz	x0, LBB0_10
; %bb.9:
	mov	x0, x20
	bl	_intel_gen6_edp_signal_levels
	mov	x20, x0
Lloh4:
	adrp	x8, _EDP_LINK_TRAIN_VOL_EMP_MASK_SNB@GOTPAGE
Lloh5:
	ldr	x8, [x8, _EDP_LINK_TRAIN_VOL_EMP_MASK_SNB@GOTPAGEOFF]
	b	LBB0_2
LBB0_10:
	mov	x0, x20
	bl	_intel_gen4_signal_levels
	mov	x20, x0
Lloh6:
	adrp	x8, _DP_VOLTAGE_MASK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _DP_VOLTAGE_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
Lloh9:
	adrp	x9, _DP_PRE_EMPHASIS_MASK@GOTPAGE
Lloh10:
	ldr	x9, [x9, _DP_PRE_EMPHASIS_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	orr	w21, w9, w8
	b	LBB0_3
LBB0_11:
	mov	x0, x20
	bl	_intel_gen7_edp_signal_levels
	mov	x20, x0
Lloh12:
	adrp	x8, _EDP_LINK_TRAIN_VOL_EMP_MASK_IVB@GOTPAGE
Lloh13:
	ldr	x8, [x8, _EDP_LINK_TRAIN_VOL_EMP_MASK_IVB@GOTPAGEOFF]
	b	LBB0_2
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh12, Lloh13
	.cfi_endproc
                                        ; -- End function
	.comm	_DDI_BUF_EMP_MASK,4,2           ; @DDI_BUF_EMP_MASK
	.comm	_EDP_LINK_TRAIN_VOL_EMP_MASK_IVB,4,2 ; @EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
	.comm	_EDP_LINK_TRAIN_VOL_EMP_MASK_SNB,4,2 ; @EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
	.comm	_DP_VOLTAGE_MASK,4,2            ; @DP_VOLTAGE_MASK
	.comm	_DP_PRE_EMPHASIS_MASK,4,2       ; @DP_PRE_EMPHASIS_MASK
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Using signal levels %08x\n"

	.no_dead_strip	_intel_dp_set_signal_levels
.subsections_via_symbols
