	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_legacy_get_lvds_info_from_regs
_radeon_legacy_get_lvds_info_from_regs: ## @radeon_legacy_get_lvds_info_from_regs
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_RADEON_LVDS_SS_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r12d
	movq	_GFP_KERNEL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$44, %edi
	callq	_kzalloc
	movq	%rax, %r15
	testq	%rax, %rax
	je	LBB0_15
## %bb.1:
	movq	_RADEON_FP_VERT_STRETCH@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %ebx
	movq	_RADEON_FP_HORZ_STRETCH@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r14d
	movabsq	$8589934592200, %rax            ## imm = 0x7D0000000C8
	movq	%rax, (%r15)
	movq	_RADEON_LVDS_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, 8(%r15)
	movq	_RADEON_LVDS_PWRSEQ_DELAY1_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	%r12d, %eax
	sarl	%cl, %eax
	andl	$15, %eax
	movl	%eax, 12(%r15)
	movq	_RADEON_LVDS_PWRSEQ_DELAY2_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarl	%cl, %r12d
	andl	$15, %r12d
	movl	%r12d, 16(%r15)
	movq	_RADEON_VERT_STRETCH_ENABLE@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_3
## %bb.2:
	movq	_RADEON_VERT_PANEL_SIZE@GOTPCREL(%rip), %rax
	andl	(%rax), %ebx
	movq	_RADEON_VERT_PANEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarl	%cl, %ebx
	jmp	LBB0_4
LBB0_3:
	movq	_RADEON_CRTC_V_TOTAL_DISP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %ebx
	sarl	$16, %ebx
LBB0_4:
	incl	%ebx
	movl	%ebx, 36(%r15)
	movq	_RADEON_HORZ_STRETCH_ENABLE@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_6
## %bb.5:
	movq	_RADEON_HORZ_PANEL_SIZE@GOTPCREL(%rip), %rax
	andl	(%rax), %r14d
	movq	_RADEON_HORZ_PANEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarl	%cl, %r14d
	leal	8(,%r14,8), %eax
	jmp	LBB0_7
LBB0_6:
	movq	_RADEON_CRTC_H_TOTAL_DISP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	sarl	$13, %eax
	addl	$8, %eax
	andl	$-8, %eax
LBB0_7:
	movl	%eax, 40(%r15)
	cmpl	$640, %eax                      ## imm = 0x280
	jl	LBB0_9
## %bb.8:
	cmpl	$479, 36(%r15)                  ## imm = 0x1DF
	jg	LBB0_10
LBB0_9:
	movabsq	$2748779069920, %rax            ## imm = 0x280000001E0
	movq	%rax, 36(%r15)
LBB0_10:
	movq	_RADEON_CLOCK_CNTL_INDEX@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	incq	%rdi
	callq	_RREG8
                                        ## kill: def $eax killed $eax def $rax
	andl	$3, %eax
	movq	_RADEON_PPLL_DIV_0@GOTPCREL(%rip), %rcx
	addq	(%rcx), %rax
	movq	%rax, %rdi
	callq	_RREG32_PLL
	movl	%eax, %ebx
	movl	%eax, %ecx
	andl	$460799, %ecx                   ## imm = 0x707FF
	xorl	%eax, %eax
	cmpl	$443, %ecx                      ## imm = 0x1BB
	je	LBB0_13
## %bb.11:
	movq	_RADEON_PPLL_REF_DIV@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32_PLL
	movl	%ebx, %ecx
	shrl	$16, %ecx
	andl	$7, %ecx
	andl	$2047, %ebx                     ## imm = 0x7FF
	andl	$1023, %eax                     ## imm = 0x3FF
	movl	%eax, 24(%r15)
	movl	%ecx, 28(%r15)
	movl	%ebx, 32(%r15)
	je	LBB0_14
## %bb.12:
	movl	$1, %eax
	cmpl	$4, %ebx
	jb	LBB0_14
LBB0_13:
	movl	%eax, 20(%r15)
LBB0_14:
	movl	$200, 4(%r15)
	leaq	L_.str(%rip), %rdi
	xorl	%eax, %eax
	callq	_DRM_INFO
	movl	36(%r15), %edx
	movl	40(%r15), %esi
	leaq	L_.str.1(%rip), %rdi
	xorl	%eax, %eax
	callq	_DRM_INFO
LBB0_15:
	movq	%r15, %rax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_LVDS_SS_GEN_CNTL,4,2    ## @RADEON_LVDS_SS_GEN_CNTL
	.comm	_GFP_KERNEL,4,2                 ## @GFP_KERNEL
	.comm	_RADEON_FP_VERT_STRETCH,4,2     ## @RADEON_FP_VERT_STRETCH
	.comm	_RADEON_FP_HORZ_STRETCH,4,2     ## @RADEON_FP_HORZ_STRETCH
	.comm	_RADEON_LVDS_GEN_CNTL,4,2       ## @RADEON_LVDS_GEN_CNTL
	.comm	_RADEON_LVDS_PWRSEQ_DELAY1_SHIFT,4,2 ## @RADEON_LVDS_PWRSEQ_DELAY1_SHIFT
	.comm	_RADEON_LVDS_PWRSEQ_DELAY2_SHIFT,4,2 ## @RADEON_LVDS_PWRSEQ_DELAY2_SHIFT
	.comm	_RADEON_VERT_STRETCH_ENABLE,4,2 ## @RADEON_VERT_STRETCH_ENABLE
	.comm	_RADEON_VERT_PANEL_SIZE,4,2     ## @RADEON_VERT_PANEL_SIZE
	.comm	_RADEON_VERT_PANEL_SHIFT,4,2    ## @RADEON_VERT_PANEL_SHIFT
	.comm	_RADEON_CRTC_V_TOTAL_DISP,4,2   ## @RADEON_CRTC_V_TOTAL_DISP
	.comm	_RADEON_HORZ_STRETCH_ENABLE,4,2 ## @RADEON_HORZ_STRETCH_ENABLE
	.comm	_RADEON_HORZ_PANEL_SIZE,4,2     ## @RADEON_HORZ_PANEL_SIZE
	.comm	_RADEON_HORZ_PANEL_SHIFT,4,2    ## @RADEON_HORZ_PANEL_SHIFT
	.comm	_RADEON_CRTC_H_TOTAL_DISP,4,2   ## @RADEON_CRTC_H_TOTAL_DISP
	.comm	_RADEON_CLOCK_CNTL_INDEX,8,3    ## @RADEON_CLOCK_CNTL_INDEX
	.comm	_RADEON_PPLL_DIV_0,8,3          ## @RADEON_PPLL_DIV_0
	.comm	_RADEON_PPLL_REF_DIV,8,3        ## @RADEON_PPLL_REF_DIV
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Panel info derived from registers\n"

L_.str.1:                               ## @.str.1
	.asciz	"Panel Size %dx%d\n"

	.no_dead_strip	_radeon_legacy_get_lvds_info_from_regs
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3                               ; -- Begin function radeon_legacy_get_lvds_info_from_regs
lCPI0_0:
	.long	200                             ; 0xc8
	.long	2000                            ; 0x7d0
lCPI0_1:
	.long	480                             ; 0x1e0
	.long	640                             ; 0x280
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	2
_radeon_legacy_get_lvds_info_from_regs: ; @radeon_legacy_get_lvds_info_from_regs
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
Lloh0:
	adrp	x8, _RADEON_LVDS_SS_GEN_CNTL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_LVDS_SS_GEN_CNTL@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x21, x0
Lloh3:
	adrp	x8, _GFP_KERNEL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _GFP_KERNEL@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	w0, #44
	bl	_kzalloc
	mov	x19, x0
	cbz	x0, LBB0_17
; %bb.1:
Lloh6:
	adrp	x8, _RADEON_FP_VERT_STRETCH@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_FP_VERT_STRETCH@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x22, x0
Lloh9:
	adrp	x8, _RADEON_FP_HORZ_STRETCH@GOTPAGE
Lloh10:
	ldr	x8, [x8, _RADEON_FP_HORZ_STRETCH@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x20, x0
Lloh12:
	adrp	x8, lCPI0_0@PAGE
Lloh13:
	ldr	d0, [x8, lCPI0_0@PAGEOFF]
	str	d0, [x19]
Lloh14:
	adrp	x8, _RADEON_LVDS_GEN_CNTL@GOTPAGE
Lloh15:
	ldr	x8, [x8, _RADEON_LVDS_GEN_CNTL@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
	bl	_RREG32
Lloh17:
	adrp	x8, _RADEON_LVDS_PWRSEQ_DELAY1_SHIFT@GOTPAGE
Lloh18:
	ldr	x8, [x8, _RADEON_LVDS_PWRSEQ_DELAY1_SHIFT@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
	asr	w8, w21, w8
	and	w8, w8, #0xf
	stp	w0, w8, [x19, #8]
Lloh20:
	adrp	x8, _RADEON_LVDS_PWRSEQ_DELAY2_SHIFT@GOTPAGE
Lloh21:
	ldr	x8, [x8, _RADEON_LVDS_PWRSEQ_DELAY2_SHIFT@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
	asr	w8, w21, w8
	and	w8, w8, #0xf
	str	w8, [x19, #16]
Lloh23:
	adrp	x8, _RADEON_VERT_STRETCH_ENABLE@GOTPAGE
Lloh24:
	ldr	x8, [x8, _RADEON_VERT_STRETCH_ENABLE@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_3
; %bb.2:
Lloh26:
	adrp	x8, _RADEON_VERT_PANEL_SIZE@GOTPAGE
Lloh27:
	ldr	x8, [x8, _RADEON_VERT_PANEL_SIZE@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
	and	w8, w8, w22
Lloh29:
	adrp	x9, _RADEON_VERT_PANEL_SHIFT@GOTPAGE
Lloh30:
	ldr	x9, [x9, _RADEON_VERT_PANEL_SHIFT@GOTPAGEOFF]
Lloh31:
	ldr	w9, [x9]
	asr	w8, w8, w9
	b	LBB0_4
LBB0_3:
Lloh32:
	adrp	x8, _RADEON_CRTC_V_TOTAL_DISP@GOTPAGE
Lloh33:
	ldr	x8, [x8, _RADEON_CRTC_V_TOTAL_DISP@GOTPAGEOFF]
Lloh34:
	ldr	w0, [x8]
	bl	_RREG32
	asr	w8, w0, #16
LBB0_4:
	add	w8, w8, #1
	str	w8, [x19, #36]
Lloh35:
	adrp	x8, _RADEON_HORZ_STRETCH_ENABLE@GOTPAGE
Lloh36:
	ldr	x8, [x8, _RADEON_HORZ_STRETCH_ENABLE@GOTPAGEOFF]
Lloh37:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_6
; %bb.5:
Lloh38:
	adrp	x8, _RADEON_HORZ_PANEL_SIZE@GOTPAGE
Lloh39:
	ldr	x8, [x8, _RADEON_HORZ_PANEL_SIZE@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
	and	w8, w8, w20
Lloh41:
	adrp	x9, _RADEON_HORZ_PANEL_SHIFT@GOTPAGE
Lloh42:
	ldr	x9, [x9, _RADEON_HORZ_PANEL_SHIFT@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
	asr	w8, w8, w9
	lsl	w8, w8, #3
	add	w8, w8, #8
	b	LBB0_7
LBB0_6:
Lloh44:
	adrp	x8, _RADEON_CRTC_H_TOTAL_DISP@GOTPAGE
Lloh45:
	ldr	x8, [x8, _RADEON_CRTC_H_TOTAL_DISP@GOTPAGEOFF]
Lloh46:
	ldr	w0, [x8]
	bl	_RREG32
	asr	w8, w0, #13
	add	w8, w8, #8
	and	w8, w8, #0xfffffff8
LBB0_7:
	str	w8, [x19, #40]
	cmp	w8, #640
	b.lt	LBB0_9
; %bb.8:
	ldr	w8, [x19, #36]
	cmp	w8, #479
	b.gt	LBB0_10
LBB0_9:
Lloh47:
	adrp	x8, lCPI0_1@PAGE
Lloh48:
	ldr	d0, [x8, lCPI0_1@PAGEOFF]
	stur	d0, [x19, #36]
LBB0_10:
Lloh49:
	adrp	x8, _RADEON_CLOCK_CNTL_INDEX@GOTPAGE
Lloh50:
	ldr	x8, [x8, _RADEON_CLOCK_CNTL_INDEX@GOTPAGEOFF]
Lloh51:
	ldr	x8, [x8]
	add	x0, x8, #1
	bl	_RREG8
	and	w8, w0, #0x3
Lloh52:
	adrp	x9, _RADEON_PPLL_DIV_0@GOTPAGE
Lloh53:
	ldr	x9, [x9, _RADEON_PPLL_DIV_0@GOTPAGEOFF]
Lloh54:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_RREG32_PLL
	and	w8, w0, #0x7ffff
	and	w8, w8, #0xffff07ff
	cmp	w8, #443
	b.ne	LBB0_12
; %bb.11:
	mov	w8, #0
	b	LBB0_15
LBB0_12:
	mov	x20, x0
Lloh55:
	adrp	x8, _RADEON_PPLL_REF_DIV@GOTPAGE
Lloh56:
	ldr	x8, [x8, _RADEON_PPLL_REF_DIV@GOTPAGEOFF]
Lloh57:
	ldr	x0, [x8]
	bl	_RREG32_PLL
	and	w8, w20, #0x7ff
	ands	w9, w0, #0x3ff
	ubfx	w10, w20, #16, #3
	str	w9, [x19, #24]
	stp	w10, w8, [x19, #28]
	b.eq	LBB0_16
; %bb.13:
	cmp	w8, #4
	b.lo	LBB0_16
; %bb.14:
	mov	w8, #1
LBB0_15:
	str	w8, [x19, #20]
LBB0_16:
	mov	w8, #200
	str	w8, [x19, #4]
Lloh58:
	adrp	x0, l_.str@PAGE
Lloh59:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_INFO
	ldp	w9, w8, [x19, #36]
	stp	x8, x9, [sp]
Lloh60:
	adrp	x0, l_.str.1@PAGE
Lloh61:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_INFO
LBB0_17:
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpAdrp	Lloh12, Lloh14
	.loh AdrpLdr	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdr	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpAdd	Lloh60, Lloh61
	.loh AdrpAdd	Lloh58, Lloh59
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_LVDS_SS_GEN_CNTL,4,2    ; @RADEON_LVDS_SS_GEN_CNTL
	.comm	_GFP_KERNEL,4,2                 ; @GFP_KERNEL
	.comm	_RADEON_FP_VERT_STRETCH,4,2     ; @RADEON_FP_VERT_STRETCH
	.comm	_RADEON_FP_HORZ_STRETCH,4,2     ; @RADEON_FP_HORZ_STRETCH
	.comm	_RADEON_LVDS_GEN_CNTL,4,2       ; @RADEON_LVDS_GEN_CNTL
	.comm	_RADEON_LVDS_PWRSEQ_DELAY1_SHIFT,4,2 ; @RADEON_LVDS_PWRSEQ_DELAY1_SHIFT
	.comm	_RADEON_LVDS_PWRSEQ_DELAY2_SHIFT,4,2 ; @RADEON_LVDS_PWRSEQ_DELAY2_SHIFT
	.comm	_RADEON_VERT_STRETCH_ENABLE,4,2 ; @RADEON_VERT_STRETCH_ENABLE
	.comm	_RADEON_VERT_PANEL_SIZE,4,2     ; @RADEON_VERT_PANEL_SIZE
	.comm	_RADEON_VERT_PANEL_SHIFT,4,2    ; @RADEON_VERT_PANEL_SHIFT
	.comm	_RADEON_CRTC_V_TOTAL_DISP,4,2   ; @RADEON_CRTC_V_TOTAL_DISP
	.comm	_RADEON_HORZ_STRETCH_ENABLE,4,2 ; @RADEON_HORZ_STRETCH_ENABLE
	.comm	_RADEON_HORZ_PANEL_SIZE,4,2     ; @RADEON_HORZ_PANEL_SIZE
	.comm	_RADEON_HORZ_PANEL_SHIFT,4,2    ; @RADEON_HORZ_PANEL_SHIFT
	.comm	_RADEON_CRTC_H_TOTAL_DISP,4,2   ; @RADEON_CRTC_H_TOTAL_DISP
	.comm	_RADEON_CLOCK_CNTL_INDEX,8,3    ; @RADEON_CLOCK_CNTL_INDEX
	.comm	_RADEON_PPLL_DIV_0,8,3          ; @RADEON_PPLL_DIV_0
	.comm	_RADEON_PPLL_REF_DIV,8,3        ; @RADEON_PPLL_REF_DIV
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Panel info derived from registers\n"

l_.str.1:                               ; @.str.1
	.asciz	"Panel Size %dx%d\n"

	.no_dead_strip	_radeon_legacy_get_lvds_info_from_regs
.subsections_via_symbols
