	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_intel_init_pm                  ## -- Begin function intel_init_pm
	.p2align	4, 0x90
_intel_init_pm:                         ## @intel_init_pm
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	movq	(%rdi), %r14
	callq	_I915_HAS_FBC
	testq	%rax, %rax
	je	LBB0_8
## %bb.1:
	movq	%rbx, %rdi
	callq	_HAS_PCH_SPLIT
	testq	%rax, %rax
	je	LBB0_3
## %bb.2:
	movq	_ironlake_disable_fbc@GOTPCREL(%rip), %rax
	movq	_ironlake_enable_fbc@GOTPCREL(%rip), %rcx
	movq	_ironlake_fbc_enabled@GOTPCREL(%rip), %rdx
	jmp	LBB0_7
LBB0_3:
	movq	%rbx, %rdi
	callq	_IS_GM45
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	movq	_g4x_disable_fbc@GOTPCREL(%rip), %rax
	movq	_g4x_enable_fbc@GOTPCREL(%rip), %rcx
	movq	_g4x_fbc_enabled@GOTPCREL(%rip), %rdx
	jmp	LBB0_7
LBB0_5:
	movq	%rbx, %rdi
	callq	_IS_CRESTLINE
	testq	%rax, %rax
	je	LBB0_8
## %bb.6:
	movq	_i8xx_disable_fbc@GOTPCREL(%rip), %rax
	movq	_i8xx_enable_fbc@GOTPCREL(%rip), %rcx
	movq	_i8xx_fbc_enabled@GOTPCREL(%rip), %rdx
LBB0_7:
	movl	(%rdx), %edx
	movl	%edx, 56(%r14)
	movl	(%rcx), %ecx
	movl	%ecx, 52(%r14)
	movl	(%rax), %eax
	movl	%eax, 48(%r14)
LBB0_8:
	movq	%rbx, %rdi
	callq	_IS_PINEVIEW
	movq	%rbx, %rdi
	testq	%rax, %rax
	je	LBB0_10
## %bb.9:
	callq	_i915_pineview_get_mem_freq
	jmp	LBB0_12
LBB0_10:
	callq	_IS_GEN5
	testq	%rax, %rax
	je	LBB0_12
## %bb.11:
	movq	%rbx, %rdi
	callq	_i915_ironlake_get_mem_freq
LBB0_12:
	movq	%rbx, %rdi
	callq	_HAS_PCH_SPLIT
	movq	%rbx, %rdi
	testq	%rax, %rax
	je	LBB0_34
## %bb.13:
	callq	_IS_GEN5
	testq	%rax, %rax
	je	LBB0_18
## %bb.14:
	movq	_MLTR_ILK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	_ILK_SRLT_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_16
## %bb.15:
	movq	_ironlake_update_wm@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	jmp	LBB0_17
LBB0_34:
	callq	_IS_VALLEYVIEW
	testq	%rax, %rax
	je	LBB0_36
## %bb.35:
	movq	_valleyview_update_wm@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 24(%r14)
	movq	_valleyview_init_clock_gating@GOTPCREL(%rip), %rax
	jmp	LBB0_42
LBB0_18:
	movq	%rbx, %rdi
	callq	_IS_GEN6
	testq	%rax, %rax
	je	LBB0_23
## %bb.19:
	xorl	%eax, %eax
	callq	_SNB_READ_WM0_LATENCY
	testq	%rax, %rax
	je	LBB0_21
## %bb.20:
	movq	_sandybridge_update_wm@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_sandybridge_update_sprite_wm@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, 40(%r14)
	jmp	LBB0_22
LBB0_16:
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	xorl	%eax, %eax
LBB0_17:
	movq	%rax, 24(%r14)
	movq	_ironlake_init_clock_gating@GOTPCREL(%rip), %rax
	jmp	LBB0_42
LBB0_36:
	movq	%rbx, %rdi
	callq	_IS_PINEVIEW
	movq	%rbx, %rdi
	testq	%rax, %rax
	je	LBB0_43
## %bb.37:
	callq	_IS_PINEVIEW_G
	movl	68(%r14), %edx
	movl	(%r14), %esi
	movl	64(%r14), %ecx
	movl	%eax, %edi
	callq	_intel_get_cxsr_latency
	testl	%eax, %eax
	je	LBB0_38
## %bb.39:
	movq	_pineview_update_wm@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	jmp	LBB0_40
LBB0_23:
	movq	%rbx, %rdi
	callq	_IS_IVYBRIDGE
	testq	%rax, %rax
	je	LBB0_28
## %bb.24:
	xorl	%eax, %eax
	callq	_SNB_READ_WM0_LATENCY
	testq	%rax, %rax
	je	LBB0_26
## %bb.25:
	movq	_ivybridge_update_wm@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_sandybridge_update_sprite_wm@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, 40(%r14)
	jmp	LBB0_27
LBB0_21:
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	xorl	%eax, %eax
LBB0_22:
	movq	%rax, 24(%r14)
	movq	_gen6_init_clock_gating@GOTPCREL(%rip), %rax
	jmp	LBB0_42
LBB0_43:
	callq	_IS_G4X
	testq	%rax, %rax
	je	LBB0_45
## %bb.44:
	movq	_g4x_update_wm@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 24(%r14)
	movq	_g4x_init_clock_gating@GOTPCREL(%rip), %rax
	jmp	LBB0_42
LBB0_38:
	movl	64(%r14), %ecx
	cmpl	$1, (%r14)
	leaq	L_.str.3(%rip), %rax
	leaq	L_.str.4(%rip), %rsi
	cmoveq	%rax, %rsi
	movl	68(%r14), %edx
	leaq	L_.str.2(%rip), %rdi
	callq	_DRM_INFO
	movq	%rbx, %rdi
	callq	_pineview_disable_cxsr
	xorl	%eax, %eax
LBB0_40:
	movq	%rax, 24(%r14)
LBB0_41:
	movq	_gen3_init_clock_gating@GOTPCREL(%rip), %rax
	jmp	LBB0_42
LBB0_28:
	movq	%rbx, %rdi
	callq	_IS_HASWELL
	testq	%rax, %rax
	je	LBB0_33
## %bb.29:
	xorl	%eax, %eax
	callq	_SNB_READ_WM0_LATENCY
	testq	%rax, %rax
	je	LBB0_31
## %bb.30:
	movq	_sandybridge_update_wm@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_sandybridge_update_sprite_wm@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, 40(%r14)
	movq	_haswell_update_linetime_wm@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, 32(%r14)
	jmp	LBB0_32
LBB0_26:
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	xorl	%eax, %eax
LBB0_27:
	movq	%rax, 24(%r14)
	movq	_ivybridge_init_clock_gating@GOTPCREL(%rip), %rax
	jmp	LBB0_42
LBB0_45:
	movq	%rbx, %rdi
	callq	_IS_GEN4
	testq	%rax, %rax
	je	LBB0_50
## %bb.46:
	movq	_i965_update_wm@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 24(%r14)
	movq	%rbx, %rdi
	callq	_IS_CRESTLINE
	testq	%rax, %rax
	je	LBB0_48
## %bb.47:
	movq	_crestline_init_clock_gating@GOTPCREL(%rip), %rax
	jmp	LBB0_42
LBB0_33:
	movq	$0, 24(%r14)
	jmp	LBB0_60
LBB0_31:
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	xorl	%eax, %eax
LBB0_32:
	movq	%rax, 24(%r14)
	movq	_haswell_init_clock_gating@GOTPCREL(%rip), %rax
LBB0_42:
	movq	(%rax), %rax
	movq	%rax, 16(%r14)
LBB0_60:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
LBB0_50:
	movq	%rbx, %rdi
	callq	_IS_GEN3
	testq	%rax, %rax
	je	LBB0_52
## %bb.51:
	movq	_i9xx_update_wm@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 24(%r14)
	movq	_i9xx_get_fifo_size@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 8(%r14)
	jmp	LBB0_41
LBB0_48:
	movq	%rbx, %rdi
	callq	_IS_BROADWATER
	testq	%rax, %rax
	je	LBB0_60
## %bb.49:
	movq	_broadwater_init_clock_gating@GOTPCREL(%rip), %rax
	jmp	LBB0_42
LBB0_52:
	movq	%rbx, %rdi
	callq	_IS_I865G
	testq	%rax, %rax
	je	LBB0_55
## %bb.53:
	movq	_i830_update_wm@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 24(%r14)
	movq	_i85x_init_clock_gating@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 16(%r14)
LBB0_54:
	movq	_i830_get_fifo_size@GOTPCREL(%rip), %rax
LBB0_59:
	movq	(%rax), %rax
	movq	%rax, 8(%r14)
	jmp	LBB0_60
LBB0_55:
	movq	%rbx, %rdi
	callq	_IS_I85X
	testq	%rax, %rax
	je	LBB0_57
## %bb.56:
	movq	_i9xx_update_wm@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 24(%r14)
	movq	_i85x_get_fifo_size@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 8(%r14)
	movq	_i85x_init_clock_gating@GOTPCREL(%rip), %rax
	jmp	LBB0_42
LBB0_57:
	movq	_i830_update_wm@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 24(%r14)
	movq	_i830_init_clock_gating@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 16(%r14)
	movq	%rbx, %rdi
	callq	_IS_845G
	testq	%rax, %rax
	je	LBB0_54
## %bb.58:
	movq	_i845_get_fifo_size@GOTPCREL(%rip), %rax
	jmp	LBB0_59
	.cfi_endproc
                                        ## -- End function
	.comm	_ironlake_fbc_enabled,4,2       ## @ironlake_fbc_enabled
	.comm	_ironlake_enable_fbc,4,2        ## @ironlake_enable_fbc
	.comm	_ironlake_disable_fbc,4,2       ## @ironlake_disable_fbc
	.comm	_g4x_fbc_enabled,4,2            ## @g4x_fbc_enabled
	.comm	_g4x_enable_fbc,4,2             ## @g4x_enable_fbc
	.comm	_g4x_disable_fbc,4,2            ## @g4x_disable_fbc
	.comm	_i8xx_fbc_enabled,4,2           ## @i8xx_fbc_enabled
	.comm	_i8xx_enable_fbc,4,2            ## @i8xx_enable_fbc
	.comm	_i8xx_disable_fbc,4,2           ## @i8xx_disable_fbc
	.comm	_MLTR_ILK,4,2                   ## @MLTR_ILK
	.comm	_ILK_SRLT_MASK,4,2              ## @ILK_SRLT_MASK
	.comm	_ironlake_update_wm,8,3         ## @ironlake_update_wm
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Failed to get proper latency. Disable CxSR\n"

	.comm	_ironlake_init_clock_gating,8,3 ## @ironlake_init_clock_gating
	.comm	_sandybridge_update_wm,8,3      ## @sandybridge_update_wm
	.comm	_sandybridge_update_sprite_wm,8,3 ## @sandybridge_update_sprite_wm
L_.str.1:                               ## @.str.1
	.asciz	"Failed to read display plane latency. Disable CxSR\n"

	.comm	_gen6_init_clock_gating,8,3     ## @gen6_init_clock_gating
	.comm	_ivybridge_update_wm,8,3        ## @ivybridge_update_wm
	.comm	_ivybridge_init_clock_gating,8,3 ## @ivybridge_init_clock_gating
	.comm	_haswell_update_linetime_wm,4,2 ## @haswell_update_linetime_wm
	.comm	_haswell_init_clock_gating,8,3  ## @haswell_init_clock_gating
	.comm	_valleyview_update_wm,8,3       ## @valleyview_update_wm
	.comm	_valleyview_init_clock_gating,8,3 ## @valleyview_init_clock_gating
L_.str.2:                               ## @.str.2
	.asciz	"failed to find known CxSR latency (found ddr%s fsb freq %d, mem freq %d), disabling CxSR\n"

L_.str.3:                               ## @.str.3
	.asciz	"3"

L_.str.4:                               ## @.str.4
	.asciz	"2"

	.comm	_pineview_update_wm,8,3         ## @pineview_update_wm
	.comm	_gen3_init_clock_gating,8,3     ## @gen3_init_clock_gating
	.comm	_g4x_update_wm,8,3              ## @g4x_update_wm
	.comm	_g4x_init_clock_gating,8,3      ## @g4x_init_clock_gating
	.comm	_i965_update_wm,8,3             ## @i965_update_wm
	.comm	_crestline_init_clock_gating,8,3 ## @crestline_init_clock_gating
	.comm	_broadwater_init_clock_gating,8,3 ## @broadwater_init_clock_gating
	.comm	_i9xx_update_wm,8,3             ## @i9xx_update_wm
	.comm	_i9xx_get_fifo_size,8,3         ## @i9xx_get_fifo_size
	.comm	_i830_update_wm,8,3             ## @i830_update_wm
	.comm	_i85x_init_clock_gating,8,3     ## @i85x_init_clock_gating
	.comm	_i830_get_fifo_size,8,3         ## @i830_get_fifo_size
	.comm	_i85x_get_fifo_size,8,3         ## @i85x_get_fifo_size
	.comm	_i830_init_clock_gating,8,3     ## @i830_init_clock_gating
	.comm	_i845_get_fifo_size,8,3         ## @i845_get_fifo_size
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_intel_init_pm                  ; -- Begin function intel_init_pm
	.p2align	2
_intel_init_pm:                         ; @intel_init_pm
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	x20, [x0]
	bl	_I915_HAS_FBC
	cbz	x0, LBB0_8
; %bb.1:
	mov	x0, x19
	bl	_HAS_PCH_SPLIT
	cbz	x0, LBB0_3
; %bb.2:
Lloh0:
	adrp	x8, _ironlake_disable_fbc@GOTPAGE
Lloh1:
	ldr	x8, [x8, _ironlake_disable_fbc@GOTPAGEOFF]
Lloh2:
	adrp	x9, _ironlake_enable_fbc@GOTPAGE
Lloh3:
	ldr	x9, [x9, _ironlake_enable_fbc@GOTPAGEOFF]
Lloh4:
	adrp	x10, _ironlake_fbc_enabled@GOTPAGE
Lloh5:
	ldr	x10, [x10, _ironlake_fbc_enabled@GOTPAGEOFF]
	b	LBB0_7
LBB0_3:
	mov	x0, x19
	bl	_IS_GM45
	cbz	x0, LBB0_5
; %bb.4:
Lloh6:
	adrp	x8, _g4x_disable_fbc@GOTPAGE
Lloh7:
	ldr	x8, [x8, _g4x_disable_fbc@GOTPAGEOFF]
Lloh8:
	adrp	x9, _g4x_enable_fbc@GOTPAGE
Lloh9:
	ldr	x9, [x9, _g4x_enable_fbc@GOTPAGEOFF]
Lloh10:
	adrp	x10, _g4x_fbc_enabled@GOTPAGE
Lloh11:
	ldr	x10, [x10, _g4x_fbc_enabled@GOTPAGEOFF]
	b	LBB0_7
LBB0_5:
	mov	x0, x19
	bl	_IS_CRESTLINE
	cbz	x0, LBB0_8
; %bb.6:
Lloh12:
	adrp	x8, _i8xx_disable_fbc@GOTPAGE
Lloh13:
	ldr	x8, [x8, _i8xx_disable_fbc@GOTPAGEOFF]
Lloh14:
	adrp	x9, _i8xx_enable_fbc@GOTPAGE
Lloh15:
	ldr	x9, [x9, _i8xx_enable_fbc@GOTPAGEOFF]
Lloh16:
	adrp	x10, _i8xx_fbc_enabled@GOTPAGE
Lloh17:
	ldr	x10, [x10, _i8xx_fbc_enabled@GOTPAGEOFF]
LBB0_7:
	ldr	w10, [x10]
	ldr	w9, [x9]
	ldr	w8, [x8]
	stp	w9, w10, [x20, #52]
	str	w8, [x20, #48]
LBB0_8:
	mov	x0, x19
	bl	_IS_PINEVIEW
	cbz	x0, LBB0_10
; %bb.9:
	mov	x0, x19
	bl	_i915_pineview_get_mem_freq
	b	LBB0_12
LBB0_10:
	mov	x0, x19
	bl	_IS_GEN5
	cbz	x0, LBB0_12
; %bb.11:
	mov	x0, x19
	bl	_i915_ironlake_get_mem_freq
LBB0_12:
	mov	x0, x19
	bl	_HAS_PCH_SPLIT
	cbz	x0, LBB0_16
; %bb.13:
	mov	x0, x19
	bl	_IS_GEN5
	cbz	x0, LBB0_18
; %bb.14:
Lloh18:
	adrp	x8, _MLTR_ILK@GOTPAGE
Lloh19:
	ldr	x8, [x8, _MLTR_ILK@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
	bl	_I915_READ
Lloh21:
	adrp	x8, _ILK_SRLT_MASK@GOTPAGE
Lloh22:
	ldr	x8, [x8, _ILK_SRLT_MASK@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_21
; %bb.15:
Lloh24:
	adrp	x8, _ironlake_update_wm@GOTPAGE
Lloh25:
	ldr	x8, [x8, _ironlake_update_wm@GOTPAGEOFF]
Lloh26:
	ldr	x8, [x8]
	b	LBB0_22
LBB0_16:
	mov	x0, x19
	bl	_IS_VALLEYVIEW
	cbz	x0, LBB0_23
; %bb.17:
Lloh27:
	adrp	x8, _valleyview_update_wm@GOTPAGE
Lloh28:
	ldr	x8, [x8, _valleyview_update_wm@GOTPAGEOFF]
Lloh29:
	ldr	x8, [x8]
Lloh30:
	adrp	x9, _valleyview_init_clock_gating@GOTPAGE
Lloh31:
	ldr	x9, [x9, _valleyview_init_clock_gating@GOTPAGEOFF]
	b	LBB0_46
LBB0_18:
	mov	x0, x19
	bl	_IS_GEN6
	cbz	x0, LBB0_26
; %bb.19:
	bl	_SNB_READ_WM0_LATENCY
	cbz	x0, LBB0_29
; %bb.20:
Lloh32:
	adrp	x8, _sandybridge_update_wm@GOTPAGE
Lloh33:
	ldr	x8, [x8, _sandybridge_update_wm@GOTPAGEOFF]
Lloh34:
	ldr	x8, [x8]
Lloh35:
	adrp	x9, _sandybridge_update_sprite_wm@GOTPAGE
Lloh36:
	ldr	x9, [x9, _sandybridge_update_sprite_wm@GOTPAGEOFF]
Lloh37:
	ldr	x9, [x9]
	str	x9, [x20, #40]
	b	LBB0_30
LBB0_21:
Lloh38:
	adrp	x0, l_.str@PAGE
Lloh39:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_KMS
	mov	x8, #0
LBB0_22:
Lloh40:
	adrp	x9, _ironlake_init_clock_gating@GOTPAGE
Lloh41:
	ldr	x9, [x9, _ironlake_init_clock_gating@GOTPAGEOFF]
	b	LBB0_46
LBB0_23:
	mov	x0, x19
	bl	_IS_PINEVIEW
	cbz	x0, LBB0_31
; %bb.24:
	mov	x0, x19
	bl	_IS_PINEVIEW_G
	ldr	w1, [x20]
	ldp	w3, w2, [x20, #64]
	bl	_intel_get_cxsr_latency
	cbz	w0, LBB0_33
; %bb.25:
Lloh42:
	adrp	x8, _pineview_update_wm@GOTPAGE
Lloh43:
	ldr	x8, [x8, _pineview_update_wm@GOTPAGEOFF]
Lloh44:
	ldr	x8, [x8]
	b	LBB0_34
LBB0_26:
	mov	x0, x19
	bl	_IS_IVYBRIDGE
	cbz	x0, LBB0_35
; %bb.27:
	bl	_SNB_READ_WM0_LATENCY
	cbz	x0, LBB0_38
; %bb.28:
Lloh45:
	adrp	x8, _ivybridge_update_wm@GOTPAGE
Lloh46:
	ldr	x8, [x8, _ivybridge_update_wm@GOTPAGEOFF]
Lloh47:
	ldr	x8, [x8]
Lloh48:
	adrp	x9, _sandybridge_update_sprite_wm@GOTPAGE
Lloh49:
	ldr	x9, [x9, _sandybridge_update_sprite_wm@GOTPAGEOFF]
Lloh50:
	ldr	x9, [x9]
	str	x9, [x20, #40]
	b	LBB0_39
LBB0_29:
Lloh51:
	adrp	x0, l_.str.1@PAGE
Lloh52:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_DEBUG_KMS
	mov	x8, #0
LBB0_30:
Lloh53:
	adrp	x9, _gen6_init_clock_gating@GOTPAGE
Lloh54:
	ldr	x9, [x9, _gen6_init_clock_gating@GOTPAGEOFF]
	b	LBB0_46
LBB0_31:
	mov	x0, x19
	bl	_IS_G4X
	cbz	x0, LBB0_40
; %bb.32:
Lloh55:
	adrp	x8, _g4x_update_wm@GOTPAGE
Lloh56:
	ldr	x8, [x8, _g4x_update_wm@GOTPAGEOFF]
Lloh57:
	ldr	x8, [x8]
Lloh58:
	adrp	x9, _g4x_init_clock_gating@GOTPAGE
Lloh59:
	ldr	x9, [x9, _g4x_init_clock_gating@GOTPAGEOFF]
	b	LBB0_46
LBB0_33:
	ldr	w8, [x20]
Lloh60:
	adrp	x9, l_.str.4@PAGE
Lloh61:
	add	x9, x9, l_.str.4@PAGEOFF
Lloh62:
	adrp	x10, l_.str.3@PAGE
Lloh63:
	add	x10, x10, l_.str.3@PAGEOFF
	cmp	w8, #1
	csel	x1, x10, x9, eq
	ldp	w3, w2, [x20, #64]
Lloh64:
	adrp	x0, l_.str.2@PAGE
Lloh65:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	_DRM_INFO
	mov	x0, x19
	bl	_pineview_disable_cxsr
	mov	x8, #0
LBB0_34:
Lloh66:
	adrp	x9, _gen3_init_clock_gating@GOTPAGE
Lloh67:
	ldr	x9, [x9, _gen3_init_clock_gating@GOTPAGEOFF]
	b	LBB0_46
LBB0_35:
	mov	x0, x19
	bl	_IS_HASWELL
	cbz	x0, LBB0_43
; %bb.36:
	bl	_SNB_READ_WM0_LATENCY
	cbz	x0, LBB0_44
; %bb.37:
Lloh68:
	adrp	x8, _sandybridge_update_wm@GOTPAGE
Lloh69:
	ldr	x8, [x8, _sandybridge_update_wm@GOTPAGEOFF]
Lloh70:
	ldr	x8, [x8]
Lloh71:
	adrp	x9, _sandybridge_update_sprite_wm@GOTPAGE
Lloh72:
	ldr	x9, [x9, _sandybridge_update_sprite_wm@GOTPAGEOFF]
Lloh73:
	ldr	x9, [x9]
	str	x9, [x20, #40]
Lloh74:
	adrp	x9, _haswell_update_linetime_wm@GOTPAGE
Lloh75:
	ldr	x9, [x9, _haswell_update_linetime_wm@GOTPAGEOFF]
Lloh76:
	ldr	w9, [x9]
	str	w9, [x20, #32]
	b	LBB0_45
LBB0_38:
Lloh77:
	adrp	x0, l_.str.1@PAGE
Lloh78:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_DEBUG_KMS
	mov	x8, #0
LBB0_39:
Lloh79:
	adrp	x9, _ivybridge_init_clock_gating@GOTPAGE
Lloh80:
	ldr	x9, [x9, _ivybridge_init_clock_gating@GOTPAGEOFF]
	b	LBB0_46
LBB0_40:
	mov	x0, x19
	bl	_IS_GEN4
	cbz	x0, LBB0_48
; %bb.41:
Lloh81:
	adrp	x8, _i965_update_wm@GOTPAGE
Lloh82:
	ldr	x8, [x8, _i965_update_wm@GOTPAGEOFF]
Lloh83:
	ldr	x8, [x8]
	str	x8, [x20, #24]
	mov	x0, x19
	bl	_IS_CRESTLINE
	cbz	x0, LBB0_51
; %bb.42:
Lloh84:
	adrp	x8, _crestline_init_clock_gating@GOTPAGE
Lloh85:
	ldr	x8, [x8, _crestline_init_clock_gating@GOTPAGEOFF]
	b	LBB0_53
LBB0_43:
	str	xzr, [x20, #24]
	b	LBB0_47
LBB0_44:
Lloh86:
	adrp	x0, l_.str.1@PAGE
Lloh87:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_DEBUG_KMS
	mov	x8, #0
LBB0_45:
Lloh88:
	adrp	x9, _haswell_init_clock_gating@GOTPAGE
Lloh89:
	ldr	x9, [x9, _haswell_init_clock_gating@GOTPAGEOFF]
LBB0_46:
	ldr	x9, [x9]
	stp	x9, x8, [x20, #16]
LBB0_47:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_48:
	mov	x0, x19
	bl	_IS_GEN3
	cbz	x0, LBB0_54
; %bb.49:
Lloh90:
	adrp	x8, _i9xx_update_wm@GOTPAGE
Lloh91:
	ldr	x8, [x8, _i9xx_update_wm@GOTPAGEOFF]
Lloh92:
	ldr	x8, [x8]
	str	x8, [x20, #24]
Lloh93:
	adrp	x8, _i9xx_get_fifo_size@GOTPAGE
Lloh94:
	ldr	x8, [x8, _i9xx_get_fifo_size@GOTPAGEOFF]
Lloh95:
	ldr	x8, [x8]
Lloh96:
	adrp	x9, _gen3_init_clock_gating@GOTPAGE
Lloh97:
	ldr	x9, [x9, _gen3_init_clock_gating@GOTPAGEOFF]
LBB0_50:
	ldr	x9, [x9]
	stp	x8, x9, [x20, #8]
	b	LBB0_47
LBB0_51:
	mov	x0, x19
	bl	_IS_BROADWATER
	cbz	x0, LBB0_47
; %bb.52:
Lloh98:
	adrp	x8, _broadwater_init_clock_gating@GOTPAGE
Lloh99:
	ldr	x8, [x8, _broadwater_init_clock_gating@GOTPAGEOFF]
LBB0_53:
	ldr	x8, [x8]
	str	x8, [x20, #16]
	b	LBB0_47
LBB0_54:
	mov	x0, x19
	bl	_IS_I865G
	cbz	x0, LBB0_56
; %bb.55:
Lloh100:
	adrp	x8, _i830_update_wm@GOTPAGE
Lloh101:
	ldr	x8, [x8, _i830_update_wm@GOTPAGEOFF]
Lloh102:
	ldr	x8, [x8]
	str	x8, [x20, #24]
Lloh103:
	adrp	x8, _i85x_init_clock_gating@GOTPAGE
Lloh104:
	ldr	x8, [x8, _i85x_init_clock_gating@GOTPAGEOFF]
Lloh105:
	ldr	x8, [x8]
Lloh106:
	adrp	x9, _i830_get_fifo_size@GOTPAGE
Lloh107:
	ldr	x9, [x9, _i830_get_fifo_size@GOTPAGEOFF]
Lloh108:
	ldr	x9, [x9]
	stp	x9, x8, [x20, #8]
	b	LBB0_47
LBB0_56:
	mov	x0, x19
	bl	_IS_I85X
	cbz	x0, LBB0_58
; %bb.57:
Lloh109:
	adrp	x8, _i9xx_update_wm@GOTPAGE
Lloh110:
	ldr	x8, [x8, _i9xx_update_wm@GOTPAGEOFF]
Lloh111:
	ldr	x8, [x8]
	str	x8, [x20, #24]
Lloh112:
	adrp	x8, _i85x_get_fifo_size@GOTPAGE
Lloh113:
	ldr	x8, [x8, _i85x_get_fifo_size@GOTPAGEOFF]
Lloh114:
	ldr	x8, [x8]
Lloh115:
	adrp	x9, _i85x_init_clock_gating@GOTPAGE
Lloh116:
	ldr	x9, [x9, _i85x_init_clock_gating@GOTPAGEOFF]
	b	LBB0_50
LBB0_58:
Lloh117:
	adrp	x8, _i830_update_wm@GOTPAGE
Lloh118:
	ldr	x8, [x8, _i830_update_wm@GOTPAGEOFF]
Lloh119:
	ldr	x8, [x8]
Lloh120:
	adrp	x9, _i830_init_clock_gating@GOTPAGE
Lloh121:
	ldr	x9, [x9, _i830_init_clock_gating@GOTPAGEOFF]
Lloh122:
	ldr	x9, [x9]
	stp	x9, x8, [x20, #16]
	mov	x0, x19
	bl	_IS_845G
	cbz	x0, LBB0_60
; %bb.59:
Lloh123:
	adrp	x8, _i845_get_fifo_size@GOTPAGE
Lloh124:
	ldr	x8, [x8, _i845_get_fifo_size@GOTPAGEOFF]
	b	LBB0_61
LBB0_60:
Lloh125:
	adrp	x8, _i830_get_fifo_size@GOTPAGE
Lloh126:
	ldr	x8, [x8, _i830_get_fifo_size@GOTPAGEOFF]
LBB0_61:
	ldr	x8, [x8]
	str	x8, [x20, #8]
	b	LBB0_47
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpAdd	Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpAdd	Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpAdd	Lloh64, Lloh65
	.loh AdrpAdd	Lloh62, Lloh63
	.loh AdrpAdd	Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpAdd	Lloh77, Lloh78
	.loh AdrpLdrGot	Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGot	Lloh84, Lloh85
	.loh AdrpAdd	Lloh86, Lloh87
	.loh AdrpLdrGot	Lloh88, Lloh89
	.loh AdrpLdrGot	Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGot	Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGot	Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh112, Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh120, Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpLdrGot	Lloh123, Lloh124
	.loh AdrpLdrGot	Lloh125, Lloh126
	.cfi_endproc
                                        ; -- End function
	.comm	_ironlake_fbc_enabled,4,2       ; @ironlake_fbc_enabled
	.comm	_ironlake_enable_fbc,4,2        ; @ironlake_enable_fbc
	.comm	_ironlake_disable_fbc,4,2       ; @ironlake_disable_fbc
	.comm	_g4x_fbc_enabled,4,2            ; @g4x_fbc_enabled
	.comm	_g4x_enable_fbc,4,2             ; @g4x_enable_fbc
	.comm	_g4x_disable_fbc,4,2            ; @g4x_disable_fbc
	.comm	_i8xx_fbc_enabled,4,2           ; @i8xx_fbc_enabled
	.comm	_i8xx_enable_fbc,4,2            ; @i8xx_enable_fbc
	.comm	_i8xx_disable_fbc,4,2           ; @i8xx_disable_fbc
	.comm	_MLTR_ILK,4,2                   ; @MLTR_ILK
	.comm	_ILK_SRLT_MASK,4,2              ; @ILK_SRLT_MASK
	.comm	_ironlake_update_wm,8,3         ; @ironlake_update_wm
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Failed to get proper latency. Disable CxSR\n"

	.comm	_ironlake_init_clock_gating,8,3 ; @ironlake_init_clock_gating
	.comm	_sandybridge_update_wm,8,3      ; @sandybridge_update_wm
	.comm	_sandybridge_update_sprite_wm,8,3 ; @sandybridge_update_sprite_wm
l_.str.1:                               ; @.str.1
	.asciz	"Failed to read display plane latency. Disable CxSR\n"

	.comm	_gen6_init_clock_gating,8,3     ; @gen6_init_clock_gating
	.comm	_ivybridge_update_wm,8,3        ; @ivybridge_update_wm
	.comm	_ivybridge_init_clock_gating,8,3 ; @ivybridge_init_clock_gating
	.comm	_haswell_update_linetime_wm,4,2 ; @haswell_update_linetime_wm
	.comm	_haswell_init_clock_gating,8,3  ; @haswell_init_clock_gating
	.comm	_valleyview_update_wm,8,3       ; @valleyview_update_wm
	.comm	_valleyview_init_clock_gating,8,3 ; @valleyview_init_clock_gating
l_.str.2:                               ; @.str.2
	.asciz	"failed to find known CxSR latency (found ddr%s fsb freq %d, mem freq %d), disabling CxSR\n"

l_.str.3:                               ; @.str.3
	.asciz	"3"

l_.str.4:                               ; @.str.4
	.asciz	"2"

	.comm	_pineview_update_wm,8,3         ; @pineview_update_wm
	.comm	_gen3_init_clock_gating,8,3     ; @gen3_init_clock_gating
	.comm	_g4x_update_wm,8,3              ; @g4x_update_wm
	.comm	_g4x_init_clock_gating,8,3      ; @g4x_init_clock_gating
	.comm	_i965_update_wm,8,3             ; @i965_update_wm
	.comm	_crestline_init_clock_gating,8,3 ; @crestline_init_clock_gating
	.comm	_broadwater_init_clock_gating,8,3 ; @broadwater_init_clock_gating
	.comm	_i9xx_update_wm,8,3             ; @i9xx_update_wm
	.comm	_i9xx_get_fifo_size,8,3         ; @i9xx_get_fifo_size
	.comm	_i830_update_wm,8,3             ; @i830_update_wm
	.comm	_i85x_init_clock_gating,8,3     ; @i85x_init_clock_gating
	.comm	_i830_get_fifo_size,8,3         ; @i830_get_fifo_size
	.comm	_i85x_get_fifo_size,8,3         ; @i85x_get_fifo_size
	.comm	_i830_init_clock_gating,8,3     ; @i830_init_clock_gating
	.comm	_i845_get_fifo_size,8,3         ; @i845_get_fifo_size
.subsections_via_symbols
