	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ironlake_pch_enable
_ironlake_pch_enable:                   ## @ironlake_pch_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r13
	movq	8(%rdi), %r15
	movq	(%r15), %rbx
	callq	_to_intel_crtc
	movq	%rax, %r14
	movl	(%rax), %r12d
	movq	%rbx, %rdi
	movl	%r12d, %esi
	callq	_assert_transcoder_disabled
	movl	%r12d, %edi
	callq	_FDI_RX_TUSIZE1
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movl	%r12d, %edi
	callq	_PIPE_DATA_M1
	movl	%eax, %edi
	callq	_I915_READ
	movq	_TU_SIZE_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movl	-48(%rbp), %edi                 ## 4-byte Reload
	movl	%eax, %esi
	callq	_I915_WRITE
	movq	%r13, -56(%rbp)                 ## 8-byte Spill
	movq	%r13, %rdi
	movq	%rbx, %r13
	movq	%r14, %rbx
	callq	*(%r13)
	movq	%r14, %rdi
	callq	_ironlake_enable_pch_pll
	movq	%r15, -48(%rbp)                 ## 8-byte Spill
	movq	%r15, %rdi
	callq	_HAS_PCH_CPT
	testq	%rax, %rax
	je	LBB0_7
## %bb.1:
	movq	_PCH_DPLL_SEL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_I915_READ
	cmpl	$2, %r12d
	je	LBB0_5
## %bb.2:
	cmpl	$1, %r12d
	jne	LBB0_3
## %bb.4:
	movq	_TRANSB_DPLL_ENABLE@GOTPCREL(%rip), %rcx
	movq	_TRANSB_DPLLB_SEL@GOTPCREL(%rip), %rdx
	jmp	LBB0_6
LBB0_5:
	movq	_TRANSC_DPLL_ENABLE@GOTPCREL(%rip), %rcx
	movq	_TRANSC_DPLLB_SEL@GOTPCREL(%rip), %rdx
	jmp	LBB0_6
LBB0_3:
	movq	_TRANSA_DPLL_ENABLE@GOTPCREL(%rip), %rcx
	movq	_TRANSA_DPLLB_SEL@GOTPCREL(%rip), %rdx
LBB0_6:
	orl	(%rcx), %eax
	movl	(%rdx), %esi
	movq	8(%rbx), %rcx
	movq	(%rcx), %rcx
	movq	__PCH_DPLL_B@GOTPCREL(%rip), %rdx
	movl	%eax, %edi
	orl	%esi, %edi
	notl	%esi
	andl	%eax, %esi
	cmpq	(%rdx), %rcx
	cmovel	%edi, %esi
	movl	(%r14), %edi
	callq	_I915_WRITE
LBB0_7:
	movq	%r13, %rdi
	movl	%r12d, %esi
	callq	_assert_panel_unlocked
	movl	%r12d, %edi
	callq	_TRANS_HTOTAL
	movl	%eax, %ebx
	movl	%r12d, %edi
	callq	_HTOTAL
	movl	%eax, %edi
	callq	_I915_READ
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_I915_WRITE
	movl	%r12d, %edi
	callq	_TRANS_HBLANK
	movl	%eax, %ebx
	movl	%r12d, %edi
	callq	_HBLANK
	movl	%eax, %edi
	callq	_I915_READ
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_I915_WRITE
	movl	%r12d, %edi
	callq	_TRANS_HSYNC
	movl	%eax, %ebx
	movl	%r12d, %edi
	callq	_HSYNC
	movl	%eax, %edi
	callq	_I915_READ
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_I915_WRITE
	movl	%r12d, %edi
	callq	_TRANS_VTOTAL
	movl	%eax, %ebx
	movl	%r12d, %edi
	callq	_VTOTAL
	movl	%eax, %edi
	callq	_I915_READ
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_I915_WRITE
	movl	%r12d, %edi
	callq	_TRANS_VBLANK
	movl	%eax, %ebx
	movl	%r12d, %edi
	callq	_VBLANK
	movl	%eax, %edi
	callq	_I915_READ
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_I915_WRITE
	movl	%r12d, %edi
	callq	_TRANS_VSYNC
	movl	%eax, %ebx
	movl	%r12d, %edi
	callq	_VSYNC
	movl	%eax, %edi
	callq	_I915_READ
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_I915_WRITE
	movl	%r12d, %edi
	callq	_TRANS_VSYNCSHIFT
	movl	%eax, %ebx
	movl	%r12d, %edi
	callq	_VSYNCSHIFT
	movl	%eax, %edi
	callq	_I915_READ
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_I915_WRITE
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	callq	_intel_fdi_normal_train
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_HAS_PCH_CPT
	testq	%rax, %rax
	je	LBB0_22
## %bb.8:
	movq	_INTEL_OUTPUT_DISPLAYPORT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_intel_pipe_has_type
	testq	%rax, %rax
	jne	LBB0_10
## %bb.9:
	movq	_INTEL_OUTPUT_EDP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_intel_pipe_has_type
	testq	%rax, %rax
	je	LBB0_22
LBB0_10:
	movq	%r13, -48(%rbp)                 ## 8-byte Spill
	movl	%r12d, %edi
	callq	_PIPECONF
	movl	%eax, %edi
	callq	_I915_READ
	movl	%eax, %r14d
	movq	_PIPECONF_BPC_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %r14d
	movl	%r12d, %edi
	callq	_TRANS_DP_CTL
	movl	%eax, %r15d
	movl	%eax, %edi
	callq	_I915_READ
	movl	%eax, %r13d
	movq	_TRANS_DP_PORT_SEL_MASK@GOTPCREL(%rip), %rax
	movq	_TRANS_DP_SYNC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	_TRANS_DP_BPC_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	notl	%edx
	andl	$-32, %r14d
	movl	(%rbx), %eax
	movq	_DRM_MODE_FLAG_PHSYNC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%eax, %ecx
	je	LBB0_12
## %bb.11:
	movq	_TRANS_DP_HSYNC_ACTIVE_HIGH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_12:
	andl	%edx, %r13d
	movq	_TRANS_DP_OUTPUT_ENABLE@GOTPCREL(%rip), %rsi
	movq	_TRANS_DP_ENH_FRAMING@GOTPCREL(%rip), %rdx
	shll	$4, %r14d
	movq	_DRM_MODE_FLAG_PVSYNC@GOTPCREL(%rip), %rdi
	andl	(%rdi), %eax
	je	LBB0_14
## %bb.13:
	movq	_TRANS_DP_VSYNC_ACTIVE_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_14:
	orl	(%rsi), %r14d
	orl	(%rdx), %r14d
	orl	%ecx, %r13d
	orl	%eax, %r13d
	orl	%r14d, %r13d
	movq	%rbx, %rdi
	callq	_intel_trans_dp_port_sel
	cmpl	$128, %eax
	je	LBB0_19
## %bb.15:
	cmpl	$129, %eax
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	je	LBB0_18
## %bb.16:
	cmpl	$130, %eax
	jne	LBB0_20
## %bb.17:
	movq	_TRANS_DP_PORT_SEL_B@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	jmp	LBB0_21
LBB0_19:
	movq	_TRANS_DP_PORT_SEL_D@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	jmp	LBB0_21
LBB0_18:
	movq	_TRANS_DP_PORT_SEL_C@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	jmp	LBB0_21
LBB0_20:
	xorl	%eax, %eax
	callq	_BUG
LBB0_21:
	movl	%r15d, %edi
	movl	%r13d, %esi
	callq	_I915_WRITE
	movq	%rbx, %r13
LBB0_22:
	movq	%r13, %rdi
	movl	%r12d, %esi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_ironlake_enable_pch_transcoder ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_TU_SIZE_MASK,4,2               ## @TU_SIZE_MASK
	.comm	_PCH_DPLL_SEL,4,2               ## @PCH_DPLL_SEL
	.comm	_TRANSA_DPLL_ENABLE,4,2         ## @TRANSA_DPLL_ENABLE
	.comm	_TRANSA_DPLLB_SEL,4,2           ## @TRANSA_DPLLB_SEL
	.comm	_TRANSB_DPLL_ENABLE,4,2         ## @TRANSB_DPLL_ENABLE
	.comm	_TRANSB_DPLLB_SEL,4,2           ## @TRANSB_DPLLB_SEL
	.comm	_TRANSC_DPLL_ENABLE,4,2         ## @TRANSC_DPLL_ENABLE
	.comm	_TRANSC_DPLLB_SEL,4,2           ## @TRANSC_DPLLB_SEL
	.comm	__PCH_DPLL_B,8,3                ## @_PCH_DPLL_B
	.comm	_INTEL_OUTPUT_DISPLAYPORT,4,2   ## @INTEL_OUTPUT_DISPLAYPORT
	.comm	_INTEL_OUTPUT_EDP,4,2           ## @INTEL_OUTPUT_EDP
	.comm	_PIPECONF_BPC_MASK,4,2          ## @PIPECONF_BPC_MASK
	.comm	_TRANS_DP_PORT_SEL_MASK,4,2     ## @TRANS_DP_PORT_SEL_MASK
	.comm	_TRANS_DP_SYNC_MASK,4,2         ## @TRANS_DP_SYNC_MASK
	.comm	_TRANS_DP_BPC_MASK,4,2          ## @TRANS_DP_BPC_MASK
	.comm	_TRANS_DP_OUTPUT_ENABLE,4,2     ## @TRANS_DP_OUTPUT_ENABLE
	.comm	_TRANS_DP_ENH_FRAMING,4,2       ## @TRANS_DP_ENH_FRAMING
	.comm	_DRM_MODE_FLAG_PHSYNC,4,2       ## @DRM_MODE_FLAG_PHSYNC
	.comm	_TRANS_DP_HSYNC_ACTIVE_HIGH,4,2 ## @TRANS_DP_HSYNC_ACTIVE_HIGH
	.comm	_DRM_MODE_FLAG_PVSYNC,4,2       ## @DRM_MODE_FLAG_PVSYNC
	.comm	_TRANS_DP_VSYNC_ACTIVE_HIGH,4,2 ## @TRANS_DP_VSYNC_ACTIVE_HIGH
	.comm	_TRANS_DP_PORT_SEL_B,4,2        ## @TRANS_DP_PORT_SEL_B
	.comm	_TRANS_DP_PORT_SEL_C,4,2        ## @TRANS_DP_PORT_SEL_C
	.comm	_TRANS_DP_PORT_SEL_D,4,2        ## @TRANS_DP_PORT_SEL_D
	.no_dead_strip	_ironlake_pch_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ironlake_pch_enable
_ironlake_pch_enable:                   ; @ironlake_pch_enable
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x21, x0
	ldr	x22, [x0, #8]
	ldr	x19, [x22]
	bl	_to_intel_crtc
	mov	x23, x0
	ldr	w20, [x0]
	mov	x0, x19
	mov	x1, x20
	bl	_assert_transcoder_disabled
	mov	x0, x20
	bl	_FDI_RX_TUSIZE1
	mov	x24, x0
	mov	x0, x20
	bl	_PIPE_DATA_M1
	bl	_I915_READ
Lloh0:
	adrp	x8, _TU_SIZE_MASK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _TU_SIZE_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	and	w1, w8, w0
	mov	x0, x24
	bl	_I915_WRITE
	ldr	x8, [x19]
	mov	x0, x21
	blr	x8
	mov	x0, x23
	bl	_ironlake_enable_pch_pll
	mov	x0, x22
	bl	_HAS_PCH_CPT
	cbz	x0, LBB0_2
; %bb.1:
Lloh3:
	adrp	x24, _PCH_DPLL_SEL@GOTPAGE
Lloh4:
	ldr	x24, [x24, _PCH_DPLL_SEL@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_I915_READ
Lloh5:
	adrp	x8, _TRANSA_DPLL_ENABLE@GOTPAGE
Lloh6:
	ldr	x8, [x8, _TRANSA_DPLL_ENABLE@GOTPAGEOFF]
Lloh7:
	adrp	x9, _TRANSA_DPLLB_SEL@GOTPAGE
Lloh8:
	ldr	x9, [x9, _TRANSA_DPLLB_SEL@GOTPAGEOFF]
Lloh9:
	adrp	x10, _TRANSC_DPLL_ENABLE@GOTPAGE
Lloh10:
	ldr	x10, [x10, _TRANSC_DPLL_ENABLE@GOTPAGEOFF]
Lloh11:
	adrp	x11, _TRANSC_DPLLB_SEL@GOTPAGE
Lloh12:
	ldr	x11, [x11, _TRANSC_DPLLB_SEL@GOTPAGEOFF]
	cmp	w20, #1
Lloh13:
	adrp	x12, _TRANSB_DPLL_ENABLE@GOTPAGE
Lloh14:
	ldr	x12, [x12, _TRANSB_DPLL_ENABLE@GOTPAGEOFF]
Lloh15:
	adrp	x13, _TRANSB_DPLLB_SEL@GOTPAGE
Lloh16:
	ldr	x13, [x13, _TRANSB_DPLLB_SEL@GOTPAGEOFF]
	csel	x9, x9, x13, ne
	csel	x8, x8, x12, ne
	cmp	w20, #2
	csel	x9, x11, x9, eq
	csel	x8, x10, x8, eq
	ldr	w8, [x8]
	orr	w8, w8, w0
	ldr	w9, [x9]
	ldr	x10, [x23, #8]
	ldr	x10, [x10]
Lloh17:
	adrp	x11, __PCH_DPLL_B@GOTPAGE
Lloh18:
	ldr	x11, [x11, __PCH_DPLL_B@GOTPAGEOFF]
Lloh19:
	ldr	x11, [x11]
	orr	w12, w8, w9
	bic	w8, w8, w9
	cmp	x10, x11
	csel	w1, w12, w8, eq
	ldr	w0, [x24]
	bl	_I915_WRITE
LBB0_2:
	mov	x0, x19
	mov	x1, x20
	bl	_assert_panel_unlocked
	mov	x0, x20
	bl	_TRANS_HTOTAL
	mov	x23, x0
	mov	x0, x20
	bl	_HTOTAL
	bl	_I915_READ
	mov	x1, x0
	mov	x0, x23
	bl	_I915_WRITE
	mov	x0, x20
	bl	_TRANS_HBLANK
	mov	x23, x0
	mov	x0, x20
	bl	_HBLANK
	bl	_I915_READ
	mov	x1, x0
	mov	x0, x23
	bl	_I915_WRITE
	mov	x0, x20
	bl	_TRANS_HSYNC
	mov	x23, x0
	mov	x0, x20
	bl	_HSYNC
	bl	_I915_READ
	mov	x1, x0
	mov	x0, x23
	bl	_I915_WRITE
	mov	x0, x20
	bl	_TRANS_VTOTAL
	mov	x23, x0
	mov	x0, x20
	bl	_VTOTAL
	bl	_I915_READ
	mov	x1, x0
	mov	x0, x23
	bl	_I915_WRITE
	mov	x0, x20
	bl	_TRANS_VBLANK
	mov	x23, x0
	mov	x0, x20
	bl	_VBLANK
	bl	_I915_READ
	mov	x1, x0
	mov	x0, x23
	bl	_I915_WRITE
	mov	x0, x20
	bl	_TRANS_VSYNC
	mov	x23, x0
	mov	x0, x20
	bl	_VSYNC
	bl	_I915_READ
	mov	x1, x0
	mov	x0, x23
	bl	_I915_WRITE
	mov	x0, x20
	bl	_TRANS_VSYNCSHIFT
	mov	x23, x0
	mov	x0, x20
	bl	_VSYNCSHIFT
	bl	_I915_READ
	mov	x1, x0
	mov	x0, x23
	bl	_I915_WRITE
	mov	x0, x21
	bl	_intel_fdi_normal_train
	mov	x0, x22
	bl	_HAS_PCH_CPT
	cbz	x0, LBB0_14
; %bb.3:
Lloh20:
	adrp	x8, _INTEL_OUTPUT_DISPLAYPORT@GOTPAGE
Lloh21:
	ldr	x8, [x8, _INTEL_OUTPUT_DISPLAYPORT@GOTPAGEOFF]
Lloh22:
	ldr	w1, [x8]
	mov	x0, x21
	bl	_intel_pipe_has_type
	cbnz	x0, LBB0_5
; %bb.4:
Lloh23:
	adrp	x8, _INTEL_OUTPUT_EDP@GOTPAGE
Lloh24:
	ldr	x8, [x8, _INTEL_OUTPUT_EDP@GOTPAGEOFF]
Lloh25:
	ldr	w1, [x8]
	mov	x0, x21
	bl	_intel_pipe_has_type
	cbz	x0, LBB0_14
LBB0_5:
	mov	x0, x20
	bl	_PIPECONF
	bl	_I915_READ
Lloh26:
	adrp	x8, _PIPECONF_BPC_MASK@GOTPAGE
Lloh27:
	ldr	x8, [x8, _PIPECONF_BPC_MASK@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
	and	w23, w8, w0
	mov	x0, x20
	bl	_TRANS_DP_CTL
	mov	x22, x0
	bl	_I915_READ
Lloh29:
	adrp	x8, _TRANS_DP_PORT_SEL_MASK@GOTPAGE
Lloh30:
	ldr	x8, [x8, _TRANS_DP_PORT_SEL_MASK@GOTPAGEOFF]
Lloh31:
	ldr	w8, [x8]
Lloh32:
	adrp	x9, _TRANS_DP_SYNC_MASK@GOTPAGE
Lloh33:
	ldr	x9, [x9, _TRANS_DP_SYNC_MASK@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh35:
	adrp	x9, _TRANS_DP_BPC_MASK@GOTPAGE
Lloh36:
	ldr	x9, [x9, _TRANS_DP_BPC_MASK@GOTPAGEOFF]
Lloh37:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w8, w0, w8
Lloh38:
	adrp	x9, _TRANS_DP_OUTPUT_ENABLE@GOTPAGE
Lloh39:
	ldr	x9, [x9, _TRANS_DP_OUTPUT_ENABLE@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
Lloh41:
	adrp	x10, _TRANS_DP_ENH_FRAMING@GOTPAGE
Lloh42:
	ldr	x10, [x10, _TRANS_DP_ENH_FRAMING@GOTPAGEOFF]
Lloh43:
	ldr	w10, [x10]
	lsl	w11, w23, #4
	and	w11, w11, #0xfffffe00
	ldr	w12, [x21]
Lloh44:
	adrp	x13, _DRM_MODE_FLAG_PHSYNC@GOTPAGE
Lloh45:
	ldr	x13, [x13, _DRM_MODE_FLAG_PHSYNC@GOTPAGEOFF]
Lloh46:
	ldr	w13, [x13]
Lloh47:
	adrp	x14, _TRANS_DP_HSYNC_ACTIVE_HIGH@GOTPAGE
Lloh48:
	ldr	x14, [x14, _TRANS_DP_HSYNC_ACTIVE_HIGH@GOTPAGEOFF]
Lloh49:
	ldr	w14, [x14]
	tst	w13, w12
Lloh50:
	adrp	x13, _DRM_MODE_FLAG_PVSYNC@GOTPAGE
Lloh51:
	ldr	x13, [x13, _DRM_MODE_FLAG_PVSYNC@GOTPAGEOFF]
	csel	w14, wzr, w14, eq
Lloh52:
	ldr	w13, [x13]
Lloh53:
	adrp	x15, _TRANS_DP_VSYNC_ACTIVE_HIGH@GOTPAGE
Lloh54:
	ldr	x15, [x15, _TRANS_DP_VSYNC_ACTIVE_HIGH@GOTPAGEOFF]
Lloh55:
	ldr	w15, [x15]
	tst	w13, w12
	csel	w12, wzr, w15, eq
	orr	w9, w9, w11
	orr	w9, w9, w10
	orr	w8, w9, w8
	orr	w8, w8, w14
	orr	w23, w8, w12
	mov	x0, x21
	bl	_intel_trans_dp_port_sel
	cmp	w0, #128
	b.eq	LBB0_9
; %bb.6:
	cmp	w0, #129
	b.eq	LBB0_10
; %bb.7:
	cmp	w0, #130
	b.ne	LBB0_12
; %bb.8:
Lloh56:
	adrp	x8, _TRANS_DP_PORT_SEL_B@GOTPAGE
Lloh57:
	ldr	x8, [x8, _TRANS_DP_PORT_SEL_B@GOTPAGEOFF]
	b	LBB0_11
LBB0_9:
Lloh58:
	adrp	x8, _TRANS_DP_PORT_SEL_D@GOTPAGE
Lloh59:
	ldr	x8, [x8, _TRANS_DP_PORT_SEL_D@GOTPAGEOFF]
	b	LBB0_11
LBB0_10:
Lloh60:
	adrp	x8, _TRANS_DP_PORT_SEL_C@GOTPAGE
Lloh61:
	ldr	x8, [x8, _TRANS_DP_PORT_SEL_C@GOTPAGEOFF]
LBB0_11:
	ldr	w8, [x8]
	orr	w23, w8, w23
	b	LBB0_13
LBB0_12:
	bl	_BUG
LBB0_13:
	mov	x0, x22
	mov	x1, x23
	bl	_I915_WRITE
LBB0_14:
	mov	x0, x19
	mov	x1, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_ironlake_enable_pch_transcoder
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh56, Lloh57
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGot	Lloh60, Lloh61
	.cfi_endproc
                                        ; -- End function
	.comm	_TU_SIZE_MASK,4,2               ; @TU_SIZE_MASK
	.comm	_PCH_DPLL_SEL,4,2               ; @PCH_DPLL_SEL
	.comm	_TRANSA_DPLL_ENABLE,4,2         ; @TRANSA_DPLL_ENABLE
	.comm	_TRANSA_DPLLB_SEL,4,2           ; @TRANSA_DPLLB_SEL
	.comm	_TRANSB_DPLL_ENABLE,4,2         ; @TRANSB_DPLL_ENABLE
	.comm	_TRANSB_DPLLB_SEL,4,2           ; @TRANSB_DPLLB_SEL
	.comm	_TRANSC_DPLL_ENABLE,4,2         ; @TRANSC_DPLL_ENABLE
	.comm	_TRANSC_DPLLB_SEL,4,2           ; @TRANSC_DPLLB_SEL
	.comm	__PCH_DPLL_B,8,3                ; @_PCH_DPLL_B
	.comm	_INTEL_OUTPUT_DISPLAYPORT,4,2   ; @INTEL_OUTPUT_DISPLAYPORT
	.comm	_INTEL_OUTPUT_EDP,4,2           ; @INTEL_OUTPUT_EDP
	.comm	_PIPECONF_BPC_MASK,4,2          ; @PIPECONF_BPC_MASK
	.comm	_TRANS_DP_PORT_SEL_MASK,4,2     ; @TRANS_DP_PORT_SEL_MASK
	.comm	_TRANS_DP_SYNC_MASK,4,2         ; @TRANS_DP_SYNC_MASK
	.comm	_TRANS_DP_BPC_MASK,4,2          ; @TRANS_DP_BPC_MASK
	.comm	_TRANS_DP_OUTPUT_ENABLE,4,2     ; @TRANS_DP_OUTPUT_ENABLE
	.comm	_TRANS_DP_ENH_FRAMING,4,2       ; @TRANS_DP_ENH_FRAMING
	.comm	_DRM_MODE_FLAG_PHSYNC,4,2       ; @DRM_MODE_FLAG_PHSYNC
	.comm	_TRANS_DP_HSYNC_ACTIVE_HIGH,4,2 ; @TRANS_DP_HSYNC_ACTIVE_HIGH
	.comm	_DRM_MODE_FLAG_PVSYNC,4,2       ; @DRM_MODE_FLAG_PVSYNC
	.comm	_TRANS_DP_VSYNC_ACTIVE_HIGH,4,2 ; @TRANS_DP_VSYNC_ACTIVE_HIGH
	.comm	_TRANS_DP_PORT_SEL_B,4,2        ; @TRANS_DP_PORT_SEL_B
	.comm	_TRANS_DP_PORT_SEL_C,4,2        ; @TRANS_DP_PORT_SEL_C
	.comm	_TRANS_DP_PORT_SEL_D,4,2        ; @TRANS_DP_PORT_SEL_D
	.no_dead_strip	_ironlake_pch_enable
.subsections_via_symbols
