	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function intel_dp_set_link_train
_intel_dp_set_link_train:               ## @intel_dp_set_link_train
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r14d
	movl	%esi, %r15d
	movq	%rdi, %r13
	callq	_dp_to_dig_port
	movq	8(%rax), %rbx
	movl	(%rax), %r12d
	movq	%rbx, %rdi
	callq	_IS_HASWELL
	testq	%rax, %rax
	je	LBB0_13
## %bb.1:
	movl	%r12d, %edi
	callq	_DP_TP_CTL
	movl	%eax, %edi
	callq	_I915_READ
	movq	_DP_LINK_SCRAMBLING_DISABLE@GOTPCREL(%rip), %rcx
	movq	_DP_TP_CTL_SCRAMBLE_DISABLE@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movl	%edx, %esi
	orl	%eax, %esi
	notl	%edx
	andl	%eax, %edx
	testl	%r14d, (%rcx)
	cmovnel	%esi, %edx
	movq	_DP_TP_CTL_LINK_TRAIN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	notl	%ebx
	andl	%edx, %ebx
	movq	_DP_TRAINING_PATTERN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r14d, %eax
	addl	$-128, %eax
	cmpl	$3, %eax
	ja	LBB0_12
## %bb.2:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_3:
	movq	_PORT_A@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r12d
	je	LBB0_7
## %bb.4:
	movq	_DP_TP_CTL_LINK_TRAIN_IDLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	%r12d, %edi
	callq	_DP_TP_CTL
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movl	%r12d, %edi
	callq	_DP_TP_STATUS
	movl	%eax, %edi
	callq	_I915_READ
	movq	_DP_TP_STATUS_IDLE_DONE@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movl	%eax, %edi
	movl	$1, %esi
	callq	_wait_for
	testl	%eax, %eax
	je	LBB0_6
## %bb.5:
	leaq	L_.str(%rip), %rdi
	callq	_DRM_ERROR
LBB0_6:
	movq	_DP_TP_CTL_LINK_TRAIN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %ebx
LBB0_7:
	movq	_DP_TP_CTL_LINK_TRAIN_NORMAL@GOTPCREL(%rip), %rax
	jmp	LBB0_11
LBB0_13:
	movq	%rbx, %rdi
	callq	_HAS_PCH_CPT
	testq	%rax, %rax
	je	LBB0_22
## %bb.14:
	movq	%rbx, %rdi
	callq	_IS_GEN7
	testq	%rax, %rax
	je	LBB0_15
LBB0_16:
	movq	_DP_LINK_TRAIN_MASK_CPT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r15d
	movq	_DP_TRAINING_PATTERN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r14d, %eax
	addl	$-128, %eax
	cmpl	$3, %eax
	ja	LBB0_29
## %bb.17:
	leaq	LJTI0_1(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_18:
	movq	_DP_LINK_TRAIN_OFF_CPT@GOTPCREL(%rip), %rax
	jmp	LBB0_28
LBB0_10:
	movq	_DP_TP_CTL_LINK_TRAIN_PAT3@GOTPCREL(%rip), %rax
	jmp	LBB0_11
LBB0_9:
	movq	_DP_TP_CTL_LINK_TRAIN_PAT2@GOTPCREL(%rip), %rax
	jmp	LBB0_11
LBB0_8:
	movq	_DP_TP_CTL_LINK_TRAIN_PAT1@GOTPCREL(%rip), %rax
LBB0_11:
	orl	(%rax), %ebx
LBB0_12:
	movl	%r12d, %edi
	callq	_DP_TP_CTL
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	jmp	LBB0_29
LBB0_15:
	movq	%r13, %rdi
	callq	_is_cpu_edp
	testl	%eax, %eax
	je	LBB0_16
LBB0_22:
	movq	_DP_LINK_TRAIN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r15d
	movq	_DP_TRAINING_PATTERN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r14d, %eax
	addl	$-128, %eax
	cmpl	$3, %eax
	ja	LBB0_29
## %bb.23:
	leaq	LJTI0_2(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_24:
	movq	_DP_LINK_TRAIN_OFF@GOTPCREL(%rip), %rax
	jmp	LBB0_28
LBB0_20:
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_ERROR
LBB0_21:
	movq	_DP_LINK_TRAIN_PAT_2_CPT@GOTPCREL(%rip), %rax
	jmp	LBB0_28
LBB0_19:
	movq	_DP_LINK_TRAIN_PAT_1_CPT@GOTPCREL(%rip), %rax
	jmp	LBB0_28
LBB0_26:
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_ERROR
LBB0_27:
	movq	_DP_LINK_TRAIN_PAT_2@GOTPCREL(%rip), %rax
	jmp	LBB0_28
LBB0_25:
	movq	_DP_LINK_TRAIN_PAT_1@GOTPCREL(%rip), %rax
LBB0_28:
	orl	(%rax), %r15d
LBB0_29:
	movl	8(%r13), %edi
	movl	%r15d, %esi
	callq	_I915_WRITE
	movl	8(%r13), %edi
	callq	_POSTING_READ
	movq	_DP_TRAINING_PATTERN_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	%r14d, %edx
	callq	_intel_dp_aux_native_write_1
	movq	_DP_TRAINING_PATTERN_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %r14d
	cmpl	$128, %r14d
	je	LBB0_31
## %bb.30:
	movq	_DP_TRAINING_LANE0_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r13), %ecx
	movl	4(%r13), %edx
	movq	%r13, %rdi
	callq	_intel_dp_aux_native_write
	movl	%eax, %ecx
	xorl	%eax, %eax
	cmpl	(%r13), %ecx
	jne	LBB0_32
LBB0_31:
	movl	$1, %eax
LBB0_32:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_3, LBB0_3-LJTI0_0
.set L0_0_set_10, LBB0_10-LJTI0_0
.set L0_0_set_9, LBB0_9-LJTI0_0
.set L0_0_set_8, LBB0_8-LJTI0_0
LJTI0_0:
	.long	L0_0_set_3
	.long	L0_0_set_10
	.long	L0_0_set_9
	.long	L0_0_set_8
.set L0_1_set_18, LBB0_18-LJTI0_1
.set L0_1_set_20, LBB0_20-LJTI0_1
.set L0_1_set_21, LBB0_21-LJTI0_1
.set L0_1_set_19, LBB0_19-LJTI0_1
LJTI0_1:
	.long	L0_1_set_18
	.long	L0_1_set_20
	.long	L0_1_set_21
	.long	L0_1_set_19
.set L0_2_set_24, LBB0_24-LJTI0_2
.set L0_2_set_26, LBB0_26-LJTI0_2
.set L0_2_set_27, LBB0_27-LJTI0_2
.set L0_2_set_25, LBB0_25-LJTI0_2
LJTI0_2:
	.long	L0_2_set_24
	.long	L0_2_set_26
	.long	L0_2_set_27
	.long	L0_2_set_25
	.end_data_region
                                        ## -- End function
	.comm	_DP_LINK_SCRAMBLING_DISABLE,4,2 ## @DP_LINK_SCRAMBLING_DISABLE
	.comm	_DP_TP_CTL_SCRAMBLE_DISABLE,4,2 ## @DP_TP_CTL_SCRAMBLE_DISABLE
	.comm	_DP_TP_CTL_LINK_TRAIN_MASK,4,2  ## @DP_TP_CTL_LINK_TRAIN_MASK
	.comm	_DP_TRAINING_PATTERN_MASK,4,2   ## @DP_TRAINING_PATTERN_MASK
	.comm	_PORT_A,4,2                     ## @PORT_A
	.comm	_DP_TP_CTL_LINK_TRAIN_IDLE,4,2  ## @DP_TP_CTL_LINK_TRAIN_IDLE
	.comm	_DP_TP_STATUS_IDLE_DONE,4,2     ## @DP_TP_STATUS_IDLE_DONE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Timed out waiting for DP idle patterns\n"

	.comm	_DP_TP_CTL_LINK_TRAIN_NORMAL,4,2 ## @DP_TP_CTL_LINK_TRAIN_NORMAL
	.comm	_DP_TP_CTL_LINK_TRAIN_PAT1,4,2  ## @DP_TP_CTL_LINK_TRAIN_PAT1
	.comm	_DP_TP_CTL_LINK_TRAIN_PAT2,4,2  ## @DP_TP_CTL_LINK_TRAIN_PAT2
	.comm	_DP_TP_CTL_LINK_TRAIN_PAT3,4,2  ## @DP_TP_CTL_LINK_TRAIN_PAT3
	.comm	_DP_LINK_TRAIN_MASK_CPT,4,2     ## @DP_LINK_TRAIN_MASK_CPT
	.comm	_DP_LINK_TRAIN_OFF_CPT,4,2      ## @DP_LINK_TRAIN_OFF_CPT
	.comm	_DP_LINK_TRAIN_PAT_1_CPT,4,2    ## @DP_LINK_TRAIN_PAT_1_CPT
	.comm	_DP_LINK_TRAIN_PAT_2_CPT,4,2    ## @DP_LINK_TRAIN_PAT_2_CPT
L_.str.1:                               ## @.str.1
	.asciz	"DP training pattern 3 not supported\n"

	.comm	_DP_LINK_TRAIN_MASK,4,2         ## @DP_LINK_TRAIN_MASK
	.comm	_DP_LINK_TRAIN_OFF,4,2          ## @DP_LINK_TRAIN_OFF
	.comm	_DP_LINK_TRAIN_PAT_1,4,2        ## @DP_LINK_TRAIN_PAT_1
	.comm	_DP_LINK_TRAIN_PAT_2,4,2        ## @DP_LINK_TRAIN_PAT_2
	.comm	_DP_TRAINING_PATTERN_SET,4,2    ## @DP_TRAINING_PATTERN_SET
	.comm	_DP_TRAINING_LANE0_SET,4,2      ## @DP_TRAINING_LANE0_SET
	.no_dead_strip	_intel_dp_set_link_train
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function intel_dp_set_link_train
_intel_dp_set_link_train:               ; @intel_dp_set_link_train
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x2
	mov	x21, x1
	mov	x19, x0
	bl	_dp_to_dig_port
	ldr	x23, [x0, #8]
	ldr	w22, [x0]
	mov	x0, x23
	bl	_IS_HASWELL
Lloh0:
	adrp	x24, _DP_TRAINING_PATTERN_MASK@GOTPAGE
Lloh1:
	ldr	x24, [x24, _DP_TRAINING_PATTERN_MASK@GOTPAGEOFF]
	cbz	x0, LBB0_8
; %bb.1:
	mov	x0, x22
	bl	_DP_TP_CTL
	bl	_I915_READ
Lloh2:
	adrp	x8, _DP_LINK_SCRAMBLING_DISABLE@GOTPAGE
Lloh3:
	ldr	x8, [x8, _DP_LINK_SCRAMBLING_DISABLE@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
Lloh5:
	adrp	x9, _DP_TP_CTL_SCRAMBLE_DISABLE@GOTPAGE
Lloh6:
	ldr	x9, [x9, _DP_TP_CTL_SCRAMBLE_DISABLE@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	orr	w10, w9, w0
	bic	w9, w0, w9
	tst	w8, w20
	csel	w8, w9, w10, eq
Lloh8:
	adrp	x25, _DP_TP_CTL_LINK_TRAIN_MASK@GOTPAGE
Lloh9:
	ldr	x25, [x25, _DP_TP_CTL_LINK_TRAIN_MASK@GOTPAGEOFF]
	ldr	w9, [x25]
	bic	w23, w8, w9
	ldr	w8, [x24]
	and	w8, w8, w20
	sub	w8, w8, #128
	cmp	w8, #3
	b.hi	LBB0_17
; %bb.2:
Lloh10:
	adrp	x9, lJTI0_0@PAGE
Lloh11:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_3
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_3:
Lloh12:
	adrp	x8, _PORT_A@GOTPAGE
Lloh13:
	ldr	x8, [x8, _PORT_A@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	cmp	w22, w8
	b.eq	LBB0_7
; %bb.4:
Lloh15:
	adrp	x8, _DP_TP_CTL_LINK_TRAIN_IDLE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _DP_TP_CTL_LINK_TRAIN_IDLE@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	orr	w23, w8, w23
	mov	x0, x22
	bl	_DP_TP_CTL
	mov	x1, x23
	bl	_I915_WRITE
	mov	x0, x22
	bl	_DP_TP_STATUS
	bl	_I915_READ
Lloh18:
	adrp	x8, _DP_TP_STATUS_IDLE_DONE@GOTPAGE
Lloh19:
	ldr	x8, [x8, _DP_TP_STATUS_IDLE_DONE@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	and	w0, w8, w0
	mov	w1, #1
	bl	_wait_for
	cbz	w0, LBB0_6
; %bb.5:
Lloh21:
	adrp	x0, l_.str@PAGE
Lloh22:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_ERROR
LBB0_6:
	ldr	w8, [x25]
	bic	w23, w23, w8
LBB0_7:
Lloh23:
	adrp	x8, _DP_TP_CTL_LINK_TRAIN_NORMAL@GOTPAGE
Lloh24:
	ldr	x8, [x8, _DP_TP_CTL_LINK_TRAIN_NORMAL@GOTPAGEOFF]
	b	LBB0_16
LBB0_8:
	mov	x0, x23
	bl	_HAS_PCH_CPT
	cbz	x0, LBB0_19
; %bb.9:
	mov	x0, x23
	bl	_IS_GEN7
	cbz	x0, LBB0_18
LBB0_10:
Lloh25:
	adrp	x8, _DP_LINK_TRAIN_MASK_CPT@GOTPAGE
Lloh26:
	ldr	x8, [x8, _DP_LINK_TRAIN_MASK_CPT@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
	bic	w21, w21, w8
	ldr	w8, [x24]
	and	w8, w8, w20
	sub	w8, w8, #128
	cmp	w8, #3
	b.hi	LBB0_29
; %bb.11:
Lloh28:
	adrp	x9, lJTI0_1@PAGE
Lloh29:
	add	x9, x9, lJTI0_1@PAGEOFF
	adr	x10, LBB0_12
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_12:
Lloh30:
	adrp	x8, _DP_LINK_TRAIN_OFF_CPT@GOTPAGE
Lloh31:
	ldr	x8, [x8, _DP_LINK_TRAIN_OFF_CPT@GOTPAGEOFF]
	b	LBB0_28
LBB0_13:
Lloh32:
	adrp	x8, _DP_TP_CTL_LINK_TRAIN_PAT3@GOTPAGE
Lloh33:
	ldr	x8, [x8, _DP_TP_CTL_LINK_TRAIN_PAT3@GOTPAGEOFF]
	b	LBB0_16
LBB0_14:
Lloh34:
	adrp	x8, _DP_TP_CTL_LINK_TRAIN_PAT2@GOTPAGE
Lloh35:
	ldr	x8, [x8, _DP_TP_CTL_LINK_TRAIN_PAT2@GOTPAGEOFF]
	b	LBB0_16
LBB0_15:
Lloh36:
	adrp	x8, _DP_TP_CTL_LINK_TRAIN_PAT1@GOTPAGE
Lloh37:
	ldr	x8, [x8, _DP_TP_CTL_LINK_TRAIN_PAT1@GOTPAGEOFF]
LBB0_16:
	ldr	w8, [x8]
	orr	w23, w8, w23
LBB0_17:
	mov	x0, x22
	bl	_DP_TP_CTL
	mov	x1, x23
	bl	_I915_WRITE
	b	LBB0_29
LBB0_18:
	mov	x0, x19
	bl	_is_cpu_edp
	cbz	w0, LBB0_10
LBB0_19:
Lloh38:
	adrp	x8, _DP_LINK_TRAIN_MASK@GOTPAGE
Lloh39:
	ldr	x8, [x8, _DP_LINK_TRAIN_MASK@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
	bic	w21, w21, w8
	ldr	w8, [x24]
	and	w8, w8, w20
	sub	w8, w8, #128
	cmp	w8, #3
	b.hi	LBB0_29
; %bb.20:
Lloh41:
	adrp	x9, lJTI0_2@PAGE
Lloh42:
	add	x9, x9, lJTI0_2@PAGEOFF
	adr	x10, LBB0_21
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_21:
Lloh43:
	adrp	x8, _DP_LINK_TRAIN_OFF@GOTPAGE
Lloh44:
	ldr	x8, [x8, _DP_LINK_TRAIN_OFF@GOTPAGEOFF]
	b	LBB0_28
LBB0_22:
Lloh45:
	adrp	x0, l_.str.1@PAGE
Lloh46:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_ERROR
LBB0_23:
Lloh47:
	adrp	x8, _DP_LINK_TRAIN_PAT_2_CPT@GOTPAGE
Lloh48:
	ldr	x8, [x8, _DP_LINK_TRAIN_PAT_2_CPT@GOTPAGEOFF]
	b	LBB0_28
LBB0_24:
Lloh49:
	adrp	x8, _DP_LINK_TRAIN_PAT_1_CPT@GOTPAGE
Lloh50:
	ldr	x8, [x8, _DP_LINK_TRAIN_PAT_1_CPT@GOTPAGEOFF]
	b	LBB0_28
LBB0_25:
Lloh51:
	adrp	x0, l_.str.1@PAGE
Lloh52:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_ERROR
LBB0_26:
Lloh53:
	adrp	x8, _DP_LINK_TRAIN_PAT_2@GOTPAGE
Lloh54:
	ldr	x8, [x8, _DP_LINK_TRAIN_PAT_2@GOTPAGEOFF]
	b	LBB0_28
LBB0_27:
Lloh55:
	adrp	x8, _DP_LINK_TRAIN_PAT_1@GOTPAGE
Lloh56:
	ldr	x8, [x8, _DP_LINK_TRAIN_PAT_1@GOTPAGEOFF]
LBB0_28:
	ldr	w8, [x8]
	orr	w21, w8, w21
LBB0_29:
	ldr	w0, [x19, #8]
	mov	x1, x21
	bl	_I915_WRITE
	ldr	w0, [x19, #8]
	bl	_POSTING_READ
Lloh57:
	adrp	x8, _DP_TRAINING_PATTERN_SET@GOTPAGE
Lloh58:
	ldr	x8, [x8, _DP_TRAINING_PATTERN_SET@GOTPAGEOFF]
Lloh59:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_intel_dp_aux_native_write_1
	ldr	w8, [x24]
	and	w8, w8, w20
	cmp	w8, #128
	b.eq	LBB0_31
; %bb.30:
Lloh60:
	adrp	x8, _DP_TRAINING_LANE0_SET@GOTPAGE
Lloh61:
	ldr	x8, [x8, _DP_TRAINING_LANE0_SET@GOTPAGEOFF]
Lloh62:
	ldr	w1, [x8]
	ldp	w3, w2, [x19]
	mov	x0, x19
	bl	_intel_dp_aux_native_write
	ldr	w8, [x19]
	cmp	w0, w8
	b.ne	LBB0_32
LBB0_31:
	mov	w0, #1
	b	LBB0_33
LBB0_32:
	mov	w0, #0
LBB0_33:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpAdd	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpAdd	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpAdd	Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpAdd	Lloh45, Lloh46
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpAdd	Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_3-LBB0_3)>>2
	.byte	(LBB0_13-LBB0_3)>>2
	.byte	(LBB0_14-LBB0_3)>>2
	.byte	(LBB0_15-LBB0_3)>>2
lJTI0_1:
	.byte	(LBB0_12-LBB0_12)>>2
	.byte	(LBB0_22-LBB0_12)>>2
	.byte	(LBB0_23-LBB0_12)>>2
	.byte	(LBB0_24-LBB0_12)>>2
lJTI0_2:
	.byte	(LBB0_21-LBB0_21)>>2
	.byte	(LBB0_25-LBB0_21)>>2
	.byte	(LBB0_26-LBB0_21)>>2
	.byte	(LBB0_27-LBB0_21)>>2
                                        ; -- End function
	.comm	_DP_LINK_SCRAMBLING_DISABLE,4,2 ; @DP_LINK_SCRAMBLING_DISABLE
	.comm	_DP_TP_CTL_SCRAMBLE_DISABLE,4,2 ; @DP_TP_CTL_SCRAMBLE_DISABLE
	.comm	_DP_TP_CTL_LINK_TRAIN_MASK,4,2  ; @DP_TP_CTL_LINK_TRAIN_MASK
	.comm	_DP_TRAINING_PATTERN_MASK,4,2   ; @DP_TRAINING_PATTERN_MASK
	.comm	_PORT_A,4,2                     ; @PORT_A
	.comm	_DP_TP_CTL_LINK_TRAIN_IDLE,4,2  ; @DP_TP_CTL_LINK_TRAIN_IDLE
	.comm	_DP_TP_STATUS_IDLE_DONE,4,2     ; @DP_TP_STATUS_IDLE_DONE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Timed out waiting for DP idle patterns\n"

	.comm	_DP_TP_CTL_LINK_TRAIN_NORMAL,4,2 ; @DP_TP_CTL_LINK_TRAIN_NORMAL
	.comm	_DP_TP_CTL_LINK_TRAIN_PAT1,4,2  ; @DP_TP_CTL_LINK_TRAIN_PAT1
	.comm	_DP_TP_CTL_LINK_TRAIN_PAT2,4,2  ; @DP_TP_CTL_LINK_TRAIN_PAT2
	.comm	_DP_TP_CTL_LINK_TRAIN_PAT3,4,2  ; @DP_TP_CTL_LINK_TRAIN_PAT3
	.comm	_DP_LINK_TRAIN_MASK_CPT,4,2     ; @DP_LINK_TRAIN_MASK_CPT
	.comm	_DP_LINK_TRAIN_OFF_CPT,4,2      ; @DP_LINK_TRAIN_OFF_CPT
	.comm	_DP_LINK_TRAIN_PAT_1_CPT,4,2    ; @DP_LINK_TRAIN_PAT_1_CPT
	.comm	_DP_LINK_TRAIN_PAT_2_CPT,4,2    ; @DP_LINK_TRAIN_PAT_2_CPT
l_.str.1:                               ; @.str.1
	.asciz	"DP training pattern 3 not supported\n"

	.comm	_DP_LINK_TRAIN_MASK,4,2         ; @DP_LINK_TRAIN_MASK
	.comm	_DP_LINK_TRAIN_OFF,4,2          ; @DP_LINK_TRAIN_OFF
	.comm	_DP_LINK_TRAIN_PAT_1,4,2        ; @DP_LINK_TRAIN_PAT_1
	.comm	_DP_LINK_TRAIN_PAT_2,4,2        ; @DP_LINK_TRAIN_PAT_2
	.comm	_DP_TRAINING_PATTERN_SET,4,2    ; @DP_TRAINING_PATTERN_SET
	.comm	_DP_TRAINING_LANE0_SET,4,2      ; @DP_TRAINING_LANE0_SET
	.no_dead_strip	_intel_dp_set_link_train
.subsections_via_symbols
