	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_evergreen_mc_program           ## -- Begin function evergreen_mc_program
	.p2align	4, 0x90
_evergreen_mc_program:                  ## @evergreen_mc_program
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movl	$11284, %ebx                    ## imm = 0x2C14
	.p2align	4, 0x90
LBB0_1:                                 ## =>This Inner Loop Header: Depth=1
	movl	%ebx, %edi
	xorl	%esi, %esi
	callq	_WREG32
	leal	4(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	leal	8(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	leal	12(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	leal	16(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	addl	$24, %ebx
	cmpl	$12052, %ebx                    ## imm = 0x2F14
	jne	LBB0_1
## %bb.2:
	movq	_HDP_REG_COHERENCY_FLUSH_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	leaq	-32(%rbp), %rsi
	movq	%r14, %rdi
	callq	_evergreen_mc_stop
	movq	%r14, %rdi
	callq	_evergreen_mc_wait_for_idle
	testq	%rax, %rax
	je	LBB0_4
## %bb.3:
	movl	16(%r14), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_warn
LBB0_4:
	movq	_VGA_HDP_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_VGA_MEMORY_DISABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_WREG32
	movq	_RADEON_IS_AGP@GOTPCREL(%rip), %r15
	movl	(%r15), %eax
	testl	%eax, (%r14)
	je	LBB0_8
## %bb.5:
	movl	20(%r14), %esi
	movl	24(%r14), %eax
	movq	_MC_VM_SYSTEM_APERTURE_LOW_ADDR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	cmpl	%eax, %esi
	jge	LBB0_7
## %bb.6:
	sarl	$12, %esi
	callq	_WREG32
	leaq	28(%r14), %rax
	jmp	LBB0_10
LBB0_8:
	movq	_MC_VM_SYSTEM_APERTURE_LOW_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	20(%r14), %esi
	sarl	$12, %esi
	jmp	LBB0_9
LBB0_7:
	sarl	$12, %eax
	movl	%eax, %esi
LBB0_9:
	callq	_WREG32
	leaq	32(%r14), %rax
LBB0_10:
	movq	_MC_VM_SYSTEM_APERTURE_HIGH_ADDR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	(%rax), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	40(%r14), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	8(%r14), %rax
	movq	_CHIP_PALM@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_13
## %bb.11:
	movq	_CHIP_SUMO@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_13
## %bb.12:
	movq	_CHIP_SUMO2@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_14
LBB0_13:
	movq	_MC_FUS_VM_FB_OFFSET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	andl	$1048575, %eax                  ## imm = 0xFFFFF
	movl	32(%r14), %ecx
	shll	$4, %ecx
	andl	$251658240, %ecx                ## imm = 0xF000000
	orl	%eax, %ecx
	movl	$15728640, %esi                 ## imm = 0xF00000
	andl	20(%r14), %esi
	orl	%ecx, %esi
	movl	(%rbx), %edi
	callq	_WREG32
LBB0_14:
	movl	32(%r14), %eax
	sarl	$8, %eax
	andl	$-65536, %eax                   ## imm = 0xFFFF0000
	movsbl	23(%r14), %ecx
	movzwl	%cx, %esi
	orl	%eax, %esi
	movq	_MC_VM_FB_LOCATION@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32
	movq	_HDP_NONSURFACE_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	20(%r14), %esi
	sarl	$8, %esi
	callq	_WREG32
	movq	_HDP_NONSURFACE_INFO@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1073742080, %esi               ## imm = 0x40000100
	callq	_WREG32
	movq	_HDP_NONSURFACE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1073741823, %esi               ## imm = 0x3FFFFFFF
	callq	_WREG32
	movl	(%r15), %eax
	testl	%eax, (%r14)
	je	LBB0_16
## %bb.15:
	movq	_MC_VM_AGP_TOP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movswl	30(%r14), %esi
	callq	_WREG32
	movq	_MC_VM_AGP_BOT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movswl	26(%r14), %esi
	callq	_WREG32
	movq	_MC_VM_AGP_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	36(%r14), %esi
	sarl	$22, %esi
	jmp	LBB0_17
LBB0_16:
	movq	_MC_VM_AGP_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_MC_VM_AGP_TOP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$268435455, %esi                ## imm = 0xFFFFFFF
	callq	_WREG32
	movq	_MC_VM_AGP_BOT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$268435455, %esi                ## imm = 0xFFFFFFF
LBB0_17:
	callq	_WREG32
	movq	%r14, %rdi
	callq	_evergreen_mc_wait_for_idle
	testq	%rax, %rax
	je	LBB0_19
## %bb.18:
	movl	16(%r14), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_warn
LBB0_19:
	leaq	-32(%rbp), %rsi
	movq	%r14, %rdi
	callq	_evergreen_mc_resume
	movq	%r14, %rdi
	callq	_rv515_vga_render_disable
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_HDP_REG_COHERENCY_FLUSH_CNTL,4,2 ## @HDP_REG_COHERENCY_FLUSH_CNTL
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Wait for MC idle timedout !\n"

	.comm	_VGA_HDP_CONTROL,4,2            ## @VGA_HDP_CONTROL
	.comm	_VGA_MEMORY_DISABLE,4,2         ## @VGA_MEMORY_DISABLE
	.comm	_RADEON_IS_AGP,4,2              ## @RADEON_IS_AGP
	.comm	_MC_VM_SYSTEM_APERTURE_LOW_ADDR,4,2 ## @MC_VM_SYSTEM_APERTURE_LOW_ADDR
	.comm	_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,4,2 ## @MC_VM_SYSTEM_APERTURE_HIGH_ADDR
	.comm	_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,4,2 ## @MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
	.comm	_CHIP_PALM,8,3                  ## @CHIP_PALM
	.comm	_CHIP_SUMO,8,3                  ## @CHIP_SUMO
	.comm	_CHIP_SUMO2,8,3                 ## @CHIP_SUMO2
	.comm	_MC_FUS_VM_FB_OFFSET,4,2        ## @MC_FUS_VM_FB_OFFSET
	.comm	_MC_VM_FB_LOCATION,4,2          ## @MC_VM_FB_LOCATION
	.comm	_HDP_NONSURFACE_BASE,4,2        ## @HDP_NONSURFACE_BASE
	.comm	_HDP_NONSURFACE_INFO,4,2        ## @HDP_NONSURFACE_INFO
	.comm	_HDP_NONSURFACE_SIZE,4,2        ## @HDP_NONSURFACE_SIZE
	.comm	_MC_VM_AGP_TOP,4,2              ## @MC_VM_AGP_TOP
	.comm	_MC_VM_AGP_BOT,4,2              ## @MC_VM_AGP_BOT
	.comm	_MC_VM_AGP_BASE,4,2             ## @MC_VM_AGP_BASE
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_evergreen_mc_program           ; -- Begin function evergreen_mc_program
	.p2align	2
_evergreen_mc_program:                  ; @evergreen_mc_program
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	mov	w21, #0
	mov	w22, #11292
	mov	w23, #11284
	mov	w24, #11288
	mov	w25, #11296
	mov	w26, #11300
LBB0_1:                                 ; =>This Inner Loop Header: Depth=1
	add	w20, w21, w22
	add	w0, w21, w23
	mov	w1, #0
	bl	_WREG32
	add	w0, w21, w24
	mov	w1, #0
	bl	_WREG32
	mov	x0, x20
	mov	w1, #0
	bl	_WREG32
	add	w0, w21, w25
	mov	w1, #0
	bl	_WREG32
	add	w0, w21, w26
	mov	w1, #0
	bl	_WREG32
	add	w21, w21, #24
	cmp	w21, #768
	b.ne	LBB0_1
; %bb.2:
Lloh0:
	adrp	x8, _HDP_REG_COHERENCY_FLUSH_CNTL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _HDP_REG_COHERENCY_FLUSH_CNTL@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	add	x1, sp, #8
	mov	x0, x19
	bl	_evergreen_mc_stop
	mov	x0, x19
	bl	_evergreen_mc_wait_for_idle
	cbz	x0, LBB0_4
; %bb.3:
	ldr	w0, [x19, #16]
Lloh3:
	adrp	x1, l_.str@PAGE
Lloh4:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_warn
LBB0_4:
Lloh5:
	adrp	x8, _VGA_HDP_CONTROL@GOTPAGE
Lloh6:
	ldr	x8, [x8, _VGA_HDP_CONTROL@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
Lloh8:
	adrp	x8, _VGA_MEMORY_DISABLE@GOTPAGE
Lloh9:
	ldr	x8, [x8, _VGA_MEMORY_DISABLE@GOTPAGEOFF]
Lloh10:
	ldr	w1, [x8]
	bl	_WREG32
	ldr	w8, [x19]
Lloh11:
	adrp	x20, _RADEON_IS_AGP@GOTPAGE
Lloh12:
	ldr	x20, [x20, _RADEON_IS_AGP@GOTPAGEOFF]
	ldr	w9, [x20]
	tst	w9, w8
	b.eq	LBB0_7
; %bb.5:
	ldp	w8, w9, [x19, #20]
Lloh13:
	adrp	x10, _MC_VM_SYSTEM_APERTURE_LOW_ADDR@GOTPAGE
Lloh14:
	ldr	x10, [x10, _MC_VM_SYSTEM_APERTURE_LOW_ADDR@GOTPAGEOFF]
Lloh15:
	ldr	w0, [x10]
	cmp	w8, w9
	b.ge	LBB0_8
; %bb.6:
	asr	w1, w8, #12
	bl	_WREG32
	add	x8, x19, #28
	b	LBB0_10
LBB0_7:
Lloh16:
	adrp	x8, _MC_VM_SYSTEM_APERTURE_LOW_ADDR@GOTPAGE
Lloh17:
	ldr	x8, [x8, _MC_VM_SYSTEM_APERTURE_LOW_ADDR@GOTPAGEOFF]
Lloh18:
	ldr	w0, [x8]
	ldr	w8, [x19, #20]
	asr	w1, w8, #12
	b	LBB0_9
LBB0_8:
	asr	w1, w9, #12
LBB0_9:
	bl	_WREG32
	add	x8, x19, #32
LBB0_10:
Lloh19:
	adrp	x9, _MC_VM_SYSTEM_APERTURE_HIGH_ADDR@GOTPAGE
Lloh20:
	ldr	x9, [x9, _MC_VM_SYSTEM_APERTURE_HIGH_ADDR@GOTPAGEOFF]
Lloh21:
	ldr	w0, [x9]
	ldr	w8, [x8]
	asr	w1, w8, #12
	bl	_WREG32
Lloh22:
	adrp	x8, _MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR@GOTPAGE
Lloh23:
	ldr	x8, [x8, _MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR@GOTPAGEOFF]
Lloh24:
	ldr	w0, [x8]
	ldr	w8, [x19, #40]
	asr	w1, w8, #12
	bl	_WREG32
	ldr	x8, [x19, #8]
Lloh25:
	adrp	x9, _CHIP_PALM@GOTPAGE
Lloh26:
	ldr	x9, [x9, _CHIP_PALM@GOTPAGEOFF]
Lloh27:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_13
; %bb.11:
Lloh28:
	adrp	x9, _CHIP_SUMO@GOTPAGE
Lloh29:
	ldr	x9, [x9, _CHIP_SUMO@GOTPAGEOFF]
Lloh30:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_13
; %bb.12:
Lloh31:
	adrp	x9, _CHIP_SUMO2@GOTPAGE
Lloh32:
	ldr	x9, [x9, _CHIP_SUMO2@GOTPAGEOFF]
Lloh33:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_14
LBB0_13:
Lloh34:
	adrp	x21, _MC_FUS_VM_FB_OFFSET@GOTPAGE
Lloh35:
	ldr	x21, [x21, _MC_FUS_VM_FB_OFFSET@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
	and	w8, w0, #0xfffff
	ldr	w9, [x19, #32]
	lsr	w9, w9, #20
	bfi	w8, w9, #24, #4
	ldr	w9, [x19, #20]
	and	w9, w9, #0xf00000
	orr	w1, w8, w9
	ldr	w0, [x21]
	bl	_WREG32
LBB0_14:
	ldr	w8, [x19, #32]
	asr	w1, w8, #8
	ldrsb	w8, [x19, #23]
	bfxil	w1, w8, #0, #16
Lloh36:
	adrp	x8, _MC_VM_FB_LOCATION@GOTPAGE
Lloh37:
	ldr	x8, [x8, _MC_VM_FB_LOCATION@GOTPAGEOFF]
Lloh38:
	ldr	w0, [x8]
	bl	_WREG32
Lloh39:
	adrp	x8, _HDP_NONSURFACE_BASE@GOTPAGE
Lloh40:
	ldr	x8, [x8, _HDP_NONSURFACE_BASE@GOTPAGEOFF]
Lloh41:
	ldr	w0, [x8]
	ldr	w8, [x19, #20]
	asr	w1, w8, #8
	bl	_WREG32
Lloh42:
	adrp	x8, _HDP_NONSURFACE_INFO@GOTPAGE
Lloh43:
	ldr	x8, [x8, _HDP_NONSURFACE_INFO@GOTPAGEOFF]
Lloh44:
	ldr	w0, [x8]
	mov	w1, #256
	movk	w1, #16384, lsl #16
	bl	_WREG32
Lloh45:
	adrp	x8, _HDP_NONSURFACE_SIZE@GOTPAGE
Lloh46:
	ldr	x8, [x8, _HDP_NONSURFACE_SIZE@GOTPAGEOFF]
Lloh47:
	ldr	w0, [x8]
	mov	w1, #1073741823
	bl	_WREG32
	ldr	w8, [x19]
	ldr	w9, [x20]
	tst	w9, w8
	b.eq	LBB0_16
; %bb.15:
Lloh48:
	adrp	x8, _MC_VM_AGP_TOP@GOTPAGE
Lloh49:
	ldr	x8, [x8, _MC_VM_AGP_TOP@GOTPAGEOFF]
Lloh50:
	ldr	w0, [x8]
	ldrsh	w1, [x19, #30]
	bl	_WREG32
Lloh51:
	adrp	x8, _MC_VM_AGP_BOT@GOTPAGE
Lloh52:
	ldr	x8, [x8, _MC_VM_AGP_BOT@GOTPAGEOFF]
Lloh53:
	ldr	w0, [x8]
	ldrsh	w1, [x19, #26]
	bl	_WREG32
Lloh54:
	adrp	x8, _MC_VM_AGP_BASE@GOTPAGE
Lloh55:
	ldr	x8, [x8, _MC_VM_AGP_BASE@GOTPAGEOFF]
Lloh56:
	ldr	w0, [x8]
	ldr	w8, [x19, #36]
	asr	w1, w8, #22
	b	LBB0_17
LBB0_16:
Lloh57:
	adrp	x8, _MC_VM_AGP_BASE@GOTPAGE
Lloh58:
	ldr	x8, [x8, _MC_VM_AGP_BASE@GOTPAGEOFF]
Lloh59:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh60:
	adrp	x8, _MC_VM_AGP_TOP@GOTPAGE
Lloh61:
	ldr	x8, [x8, _MC_VM_AGP_TOP@GOTPAGEOFF]
Lloh62:
	ldr	w0, [x8]
	mov	w1, #268435455
	bl	_WREG32
Lloh63:
	adrp	x8, _MC_VM_AGP_BOT@GOTPAGE
Lloh64:
	ldr	x8, [x8, _MC_VM_AGP_BOT@GOTPAGEOFF]
Lloh65:
	ldr	w0, [x8]
	mov	w1, #268435455
LBB0_17:
	bl	_WREG32
	mov	x0, x19
	bl	_evergreen_mc_wait_for_idle
	cbz	x0, LBB0_19
; %bb.18:
	ldr	w0, [x19, #16]
Lloh66:
	adrp	x1, l_.str@PAGE
Lloh67:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_warn
LBB0_19:
	add	x1, sp, #8
	mov	x0, x19
	bl	_evergreen_mc_resume
	mov	x0, x19
	bl	_rv515_vga_render_disable
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpAdd	Lloh66, Lloh67
	.cfi_endproc
                                        ; -- End function
	.comm	_HDP_REG_COHERENCY_FLUSH_CNTL,4,2 ; @HDP_REG_COHERENCY_FLUSH_CNTL
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Wait for MC idle timedout !\n"

	.comm	_VGA_HDP_CONTROL,4,2            ; @VGA_HDP_CONTROL
	.comm	_VGA_MEMORY_DISABLE,4,2         ; @VGA_MEMORY_DISABLE
	.comm	_RADEON_IS_AGP,4,2              ; @RADEON_IS_AGP
	.comm	_MC_VM_SYSTEM_APERTURE_LOW_ADDR,4,2 ; @MC_VM_SYSTEM_APERTURE_LOW_ADDR
	.comm	_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,4,2 ; @MC_VM_SYSTEM_APERTURE_HIGH_ADDR
	.comm	_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,4,2 ; @MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
	.comm	_CHIP_PALM,8,3                  ; @CHIP_PALM
	.comm	_CHIP_SUMO,8,3                  ; @CHIP_SUMO
	.comm	_CHIP_SUMO2,8,3                 ; @CHIP_SUMO2
	.comm	_MC_FUS_VM_FB_OFFSET,4,2        ; @MC_FUS_VM_FB_OFFSET
	.comm	_MC_VM_FB_LOCATION,4,2          ; @MC_VM_FB_LOCATION
	.comm	_HDP_NONSURFACE_BASE,4,2        ; @HDP_NONSURFACE_BASE
	.comm	_HDP_NONSURFACE_INFO,4,2        ; @HDP_NONSURFACE_INFO
	.comm	_HDP_NONSURFACE_SIZE,4,2        ; @HDP_NONSURFACE_SIZE
	.comm	_MC_VM_AGP_TOP,4,2              ; @MC_VM_AGP_TOP
	.comm	_MC_VM_AGP_BOT,4,2              ; @MC_VM_AGP_BOT
	.comm	_MC_VM_AGP_BASE,4,2             ; @MC_VM_AGP_BASE
.subsections_via_symbols
