	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function intel_gen4_signal_levels
_intel_gen4_signal_levels:              ## @intel_gen4_signal_levels
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	_DP_TRAIN_VOLTAGE_SWING_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%edi, %eax
	addl	$-128, %eax
	cmpl	$3, %eax
	ja	LBB0_1
## %bb.2:
	cltq
	leaq	l_switch.table.intel_gen4_signal_levels(%rip), %rcx
	movq	(%rcx,%rax,8), %rax
	jmp	LBB0_3
LBB0_1:
	movq	_DP_VOLTAGE_0_4@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %eax
	movq	_DP_TRAIN_PRE_EMPHASIS_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %edi
	addl	$-132, %edi
	cmpl	$2, %edi
	ja	LBB0_4
## %bb.5:
	movslq	%edi, %rcx
	leaq	l_switch.table.intel_gen4_signal_levels.1(%rip), %rdx
	movq	(%rdx,%rcx,8), %rcx
	jmp	LBB0_6
LBB0_4:
	movq	_DP_PRE_EMPHASIS_0@GOTPCREL(%rip), %rcx
LBB0_6:
	orl	(%rcx), %eax
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DP_TRAIN_VOLTAGE_SWING_MASK,4,2 ## @DP_TRAIN_VOLTAGE_SWING_MASK
	.comm	_DP_VOLTAGE_0_4,4,2             ## @DP_VOLTAGE_0_4
	.comm	_DP_VOLTAGE_0_6,4,2             ## @DP_VOLTAGE_0_6
	.comm	_DP_VOLTAGE_0_8,4,2             ## @DP_VOLTAGE_0_8
	.comm	_DP_VOLTAGE_1_2,4,2             ## @DP_VOLTAGE_1_2
	.comm	_DP_TRAIN_PRE_EMPHASIS_MASK,4,2 ## @DP_TRAIN_PRE_EMPHASIS_MASK
	.comm	_DP_PRE_EMPHASIS_0,4,2          ## @DP_PRE_EMPHASIS_0
	.comm	_DP_PRE_EMPHASIS_3_5,4,2        ## @DP_PRE_EMPHASIS_3_5
	.comm	_DP_PRE_EMPHASIS_6,4,2          ## @DP_PRE_EMPHASIS_6
	.comm	_DP_PRE_EMPHASIS_9_5,4,2        ## @DP_PRE_EMPHASIS_9_5
	.no_dead_strip	_intel_gen4_signal_levels
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.intel_gen4_signal_levels
l_switch.table.intel_gen4_signal_levels:
	.quad	_DP_VOLTAGE_0_8
	.quad	_DP_VOLTAGE_0_6
	.quad	_DP_VOLTAGE_0_4
	.quad	_DP_VOLTAGE_1_2

	.p2align	3                               ## @switch.table.intel_gen4_signal_levels.1
l_switch.table.intel_gen4_signal_levels.1:
	.quad	_DP_PRE_EMPHASIS_9_5
	.quad	_DP_PRE_EMPHASIS_6
	.quad	_DP_PRE_EMPHASIS_3_5

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function intel_gen4_signal_levels
_intel_gen4_signal_levels:              ; @intel_gen4_signal_levels
	.cfi_startproc
; %bb.0:
Lloh0:
	adrp	x8, _DP_TRAIN_VOLTAGE_SWING_MASK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DP_TRAIN_VOLTAGE_SWING_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	and	w8, w8, w0
	sub	w8, w8, #128
	cmp	w8, #3
	b.hi	LBB0_2
; %bb.1:
Lloh3:
	adrp	x9, l_switch.table.intel_gen4_signal_levels@PAGE
Lloh4:
	add	x9, x9, l_switch.table.intel_gen4_signal_levels@PAGEOFF
	ldr	x8, [x9, w8, sxtw #3]
	b	LBB0_3
LBB0_2:
Lloh5:
	adrp	x8, _DP_VOLTAGE_0_4@GOTPAGE
Lloh6:
	ldr	x8, [x8, _DP_VOLTAGE_0_4@GOTPAGEOFF]
LBB0_3:
	ldr	w8, [x8]
Lloh7:
	adrp	x9, _DP_TRAIN_PRE_EMPHASIS_MASK@GOTPAGE
Lloh8:
	ldr	x9, [x9, _DP_TRAIN_PRE_EMPHASIS_MASK@GOTPAGEOFF]
Lloh9:
	ldr	w9, [x9]
	and	w9, w9, w0
	sub	w9, w9, #132
	cmp	w9, #2
	b.hi	LBB0_5
; %bb.4:
Lloh10:
	adrp	x10, l_switch.table.intel_gen4_signal_levels.1@PAGE
Lloh11:
	add	x10, x10, l_switch.table.intel_gen4_signal_levels.1@PAGEOFF
	ldr	x9, [x10, w9, sxtw #3]
	b	LBB0_6
LBB0_5:
Lloh12:
	adrp	x9, _DP_PRE_EMPHASIS_0@GOTPAGE
Lloh13:
	ldr	x9, [x9, _DP_PRE_EMPHASIS_0@GOTPAGEOFF]
LBB0_6:
	ldr	w9, [x9]
	orr	w0, w9, w8
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh12, Lloh13
	.cfi_endproc
                                        ; -- End function
	.comm	_DP_TRAIN_VOLTAGE_SWING_MASK,4,2 ; @DP_TRAIN_VOLTAGE_SWING_MASK
	.comm	_DP_VOLTAGE_0_4,4,2             ; @DP_VOLTAGE_0_4
	.comm	_DP_VOLTAGE_0_6,4,2             ; @DP_VOLTAGE_0_6
	.comm	_DP_VOLTAGE_0_8,4,2             ; @DP_VOLTAGE_0_8
	.comm	_DP_VOLTAGE_1_2,4,2             ; @DP_VOLTAGE_1_2
	.comm	_DP_TRAIN_PRE_EMPHASIS_MASK,4,2 ; @DP_TRAIN_PRE_EMPHASIS_MASK
	.comm	_DP_PRE_EMPHASIS_0,4,2          ; @DP_PRE_EMPHASIS_0
	.comm	_DP_PRE_EMPHASIS_3_5,4,2        ; @DP_PRE_EMPHASIS_3_5
	.comm	_DP_PRE_EMPHASIS_6,4,2          ; @DP_PRE_EMPHASIS_6
	.comm	_DP_PRE_EMPHASIS_9_5,4,2        ; @DP_PRE_EMPHASIS_9_5
	.no_dead_strip	_intel_gen4_signal_levels
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.intel_gen4_signal_levels
l_switch.table.intel_gen4_signal_levels:
	.quad	_DP_VOLTAGE_0_8
	.quad	_DP_VOLTAGE_0_6
	.quad	_DP_VOLTAGE_0_4
	.quad	_DP_VOLTAGE_1_2

	.p2align	3                               ; @switch.table.intel_gen4_signal_levels.1
l_switch.table.intel_gen4_signal_levels.1:
	.quad	_DP_PRE_EMPHASIS_9_5
	.quad	_DP_PRE_EMPHASIS_6
	.quad	_DP_PRE_EMPHASIS_3_5

.subsections_via_symbols
