	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function intel_dp_mode_set
_intel_dp_mode_set:                     ## @intel_dp_mode_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r15
	movq	%rdi, %r14
	movq	8(%rdi), %r13
	callq	_enc_to_intel_dp
	movq	%rax, %rbx
	movq	(%r14), %rdi
	movq	%rdi, -48(%rbp)                 ## 8-byte Spill
	callq	_to_intel_crtc
	movq	%rax, %r12
	movl	32(%rbx), %edi
	callq	_I915_READ
	movq	_DP_DETECTED@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movl	%eax, (%rbx)
	movq	_DP_VOLTAGE_0_4@GOTPCREL(%rip), %rcx
	movq	_DP_PRE_EMPHASIS_0@GOTPCREL(%rip), %rdx
	orl	(%rcx), %eax
	orl	(%rdx), %eax
	movl	%eax, (%rbx)
	movl	4(%rbx), %ecx
	cmpl	$1, %ecx
	je	LBB0_1
## %bb.2:
	cmpl	$4, %ecx
	je	LBB0_5
## %bb.3:
	cmpl	$2, %ecx
	jne	LBB0_7
## %bb.4:
	movq	_DP_PORT_WIDTH_2@GOTPCREL(%rip), %rcx
	jmp	LBB0_6
LBB0_1:
	movq	_DP_PORT_WIDTH_1@GOTPCREL(%rip), %rcx
	jmp	LBB0_6
LBB0_5:
	movq	_DP_PORT_WIDTH_4@GOTPCREL(%rip), %rcx
LBB0_6:
	orl	(%rcx), %eax
	movl	%eax, (%rbx)
LBB0_7:
	cmpq	$0, 24(%rbx)
	je	LBB0_9
## %bb.8:
	movl	(%r12), %edi
	callq	_pipe_name
	leaq	L_.str(%rip), %rdi
	movl	%eax, %esi
	callq	_DRM_DEBUG_DRIVER
	movq	_DP_AUDIO_OUTPUT_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%rbx)
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	_intel_write_eld
LBB0_9:
	movq	%rbx, %rdi
	callq	_intel_dp_init_link_config
	movq	%rbx, %rdi
	callq	_is_cpu_edp
	testq	%rax, %rax
	je	LBB0_22
## %bb.10:
	movq	%r13, %rdi
	callq	_IS_GEN7
	testq	%rax, %rax
	je	LBB0_22
## %bb.11:
	movq	%r13, %rdi
	callq	_IS_VALLEYVIEW
	testl	%eax, %eax
	je	LBB0_12
LBB0_22:
	movq	%r13, %rdi
	callq	_HAS_PCH_CPT
	testl	%eax, %eax
	je	LBB0_24
## %bb.23:
	movq	%rbx, %rdi
	callq	_is_cpu_edp
	testq	%rax, %rax
	je	LBB0_39
LBB0_24:
	movq	%r13, %rdi
	callq	_HAS_PCH_SPLIT
	testl	%eax, %eax
	jne	LBB0_26
## %bb.25:
	movl	16(%rbx), %eax
	orl	%eax, (%rbx)
LBB0_26:
	movl	(%r15), %eax
	movq	_DRM_MODE_FLAG_PHSYNC@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_28
## %bb.27:
	movq	_DP_SYNC_HS_HIGH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	%ecx, (%rbx)
LBB0_28:
	movq	_DRM_MODE_FLAG_PVSYNC@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_29
## %bb.30:
	movq	_DP_SYNC_VS_HIGH@GOTPCREL(%rip), %rcx
	movl	(%rbx), %eax
	orl	(%rcx), %eax
	movl	%eax, (%rbx)
	jmp	LBB0_31
LBB0_29:
	movl	(%rbx), %eax
LBB0_31:
	movq	_DP_LINK_TRAIN_OFF@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%rbx)
	movq	8(%rbx), %rcx
	movq	_DP_LANE_COUNT_ENHANCED_FRAME_EN@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	testl	%edx, 4(%rcx)
	je	LBB0_33
## %bb.32:
	movq	_DP_ENHANCED_FRAMING@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%rbx)
LBB0_33:
	cmpl	$1, (%r12)
	jne	LBB0_35
## %bb.34:
	movq	_DP_PIPEB_SELECT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%rbx)
LBB0_35:
	movq	%rbx, %rdi
	callq	_is_cpu_edp
	testq	%rax, %rax
	je	LBB0_42
## %bb.36:
	cmpl	$199999, 4(%r15)                ## imm = 0x30D3F
	jg	LBB0_38
## %bb.37:
	movq	_DP_PLL_FREQ_160MHZ@GOTPCREL(%rip), %rcx
	jmp	LBB0_40
LBB0_39:
	movq	_DP_LINK_TRAIN_OFF_CPT@GOTPCREL(%rip), %rcx
	jmp	LBB0_40
LBB0_38:
	movq	_DP_PLL_FREQ_270MHZ@GOTPCREL(%rip), %rcx
LBB0_40:
	movl	(%rbx), %eax
LBB0_41:
	orl	(%rcx), %eax
	movl	%eax, (%rbx)
LBB0_42:
	movq	%rbx, %rdi
	callq	_is_cpu_edp
	testq	%rax, %rax
	je	LBB0_43
## %bb.44:
	movl	4(%r15), %esi
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_ironlake_set_pll_edp           ## TAILCALL
LBB0_43:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_12:
	movl	(%r15), %eax
	movq	_DRM_MODE_FLAG_PHSYNC@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_14
## %bb.13:
	movq	_DP_SYNC_HS_HIGH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	%ecx, (%rbx)
LBB0_14:
	movq	_DRM_MODE_FLAG_PVSYNC@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_15
## %bb.16:
	movq	_DP_SYNC_VS_HIGH@GOTPCREL(%rip), %rcx
	movl	(%rbx), %eax
	orl	(%rcx), %eax
	movl	%eax, (%rbx)
	jmp	LBB0_17
LBB0_15:
	movl	(%rbx), %eax
LBB0_17:
	movq	_DP_LINK_TRAIN_OFF_CPT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%rbx)
	movq	8(%rbx), %rdx
	movq	_DP_LANE_COUNT_ENHANCED_FRAME_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	4(%rdx), %ecx
	je	LBB0_19
## %bb.18:
	movq	_DP_ENHANCED_FRAMING@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_19:
	movl	(%r12), %edx
	shll	$29, %edx
	orl	%edx, %eax
	orl	%ecx, %eax
	movl	%eax, (%rbx)
	cmpl	$199999, 4(%r15)                ## imm = 0x30D3F
	jg	LBB0_21
## %bb.20:
	movq	_DP_PLL_FREQ_160MHZ@GOTPCREL(%rip), %rcx
	jmp	LBB0_41
LBB0_21:
	movq	_DP_PLL_FREQ_270MHZ@GOTPCREL(%rip), %rcx
	jmp	LBB0_41
	.cfi_endproc
                                        ## -- End function
	.comm	_DP_DETECTED,4,2                ## @DP_DETECTED
	.comm	_DP_VOLTAGE_0_4,4,2             ## @DP_VOLTAGE_0_4
	.comm	_DP_PRE_EMPHASIS_0,4,2          ## @DP_PRE_EMPHASIS_0
	.comm	_DP_PORT_WIDTH_1,4,2            ## @DP_PORT_WIDTH_1
	.comm	_DP_PORT_WIDTH_2,4,2            ## @DP_PORT_WIDTH_2
	.comm	_DP_PORT_WIDTH_4,4,2            ## @DP_PORT_WIDTH_4
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Enabling DP audio on pipe %c\n"

	.comm	_DP_AUDIO_OUTPUT_ENABLE,4,2     ## @DP_AUDIO_OUTPUT_ENABLE
	.comm	_DRM_MODE_FLAG_PHSYNC,4,2       ## @DRM_MODE_FLAG_PHSYNC
	.comm	_DP_SYNC_HS_HIGH,4,2            ## @DP_SYNC_HS_HIGH
	.comm	_DRM_MODE_FLAG_PVSYNC,4,2       ## @DRM_MODE_FLAG_PVSYNC
	.comm	_DP_SYNC_VS_HIGH,4,2            ## @DP_SYNC_VS_HIGH
	.comm	_DP_LINK_TRAIN_OFF_CPT,4,2      ## @DP_LINK_TRAIN_OFF_CPT
	.comm	_DP_LANE_COUNT_ENHANCED_FRAME_EN,4,2 ## @DP_LANE_COUNT_ENHANCED_FRAME_EN
	.comm	_DP_ENHANCED_FRAMING,4,2        ## @DP_ENHANCED_FRAMING
	.comm	_DP_PLL_FREQ_160MHZ,4,2         ## @DP_PLL_FREQ_160MHZ
	.comm	_DP_PLL_FREQ_270MHZ,4,2         ## @DP_PLL_FREQ_270MHZ
	.comm	_DP_LINK_TRAIN_OFF,4,2          ## @DP_LINK_TRAIN_OFF
	.comm	_DP_PIPEB_SELECT,4,2            ## @DP_PIPEB_SELECT
	.no_dead_strip	_intel_dp_mode_set
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function intel_dp_mode_set
_intel_dp_mode_set:                     ; @intel_dp_mode_set
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x2
	mov	x24, x0
	ldr	x23, [x0, #8]
	bl	_enc_to_intel_dp
	mov	x21, x0
	ldr	x20, [x24]
	mov	x0, x20
	bl	_to_intel_crtc
	mov	x22, x0
	ldr	w0, [x21, #32]
	bl	_I915_READ
Lloh0:
	adrp	x8, _DP_DETECTED@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DP_DETECTED@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	and	w8, w8, w0
	str	w8, [x21]
Lloh3:
	adrp	x9, _DP_VOLTAGE_0_4@GOTPAGE
Lloh4:
	ldr	x9, [x9, _DP_VOLTAGE_0_4@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
Lloh6:
	adrp	x10, _DP_PRE_EMPHASIS_0@GOTPAGE
Lloh7:
	ldr	x10, [x10, _DP_PRE_EMPHASIS_0@GOTPAGEOFF]
Lloh8:
	ldr	w10, [x10]
	orr	w8, w9, w8
	orr	w8, w8, w10
	str	w8, [x21]
	ldr	w9, [x21, #4]
	cmp	w9, #1
	b.eq	LBB0_4
; %bb.1:
	cmp	w9, #4
	b.eq	LBB0_5
; %bb.2:
	cmp	w9, #2
	b.ne	LBB0_7
; %bb.3:
Lloh9:
	adrp	x9, _DP_PORT_WIDTH_2@GOTPAGE
Lloh10:
	ldr	x9, [x9, _DP_PORT_WIDTH_2@GOTPAGEOFF]
	b	LBB0_6
LBB0_4:
Lloh11:
	adrp	x9, _DP_PORT_WIDTH_1@GOTPAGE
Lloh12:
	ldr	x9, [x9, _DP_PORT_WIDTH_1@GOTPAGEOFF]
	b	LBB0_6
LBB0_5:
Lloh13:
	adrp	x9, _DP_PORT_WIDTH_4@GOTPAGE
Lloh14:
	ldr	x9, [x9, _DP_PORT_WIDTH_4@GOTPAGEOFF]
LBB0_6:
	ldr	w9, [x9]
	orr	w8, w9, w8
	str	w8, [x21]
LBB0_7:
	ldr	x8, [x21, #24]
	cbz	x8, LBB0_9
; %bb.8:
	ldr	w0, [x22]
	bl	_pipe_name
	mov	x1, x0
Lloh15:
	adrp	x0, l_.str@PAGE
Lloh16:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_DRIVER
Lloh17:
	adrp	x8, _DP_AUDIO_OUTPUT_ENABLE@GOTPAGE
Lloh18:
	ldr	x8, [x8, _DP_AUDIO_OUTPUT_ENABLE@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
	ldr	w9, [x21]
	orr	w8, w9, w8
	str	w8, [x21]
	mov	x0, x24
	mov	x1, x19
	bl	_intel_write_eld
LBB0_9:
	mov	x0, x21
	bl	_intel_dp_init_link_config
	mov	x0, x21
	bl	_is_cpu_edp
	cbz	x0, LBB0_12
; %bb.10:
	mov	x0, x23
	bl	_IS_GEN7
	cbz	x0, LBB0_12
; %bb.11:
	mov	x0, x23
	bl	_IS_VALLEYVIEW
	cbz	w0, LBB0_35
LBB0_12:
	mov	x0, x23
	bl	_HAS_PCH_CPT
	cbz	w0, LBB0_14
; %bb.13:
	mov	x0, x21
	bl	_is_cpu_edp
	cbz	x0, LBB0_28
LBB0_14:
	mov	x0, x23
	bl	_HAS_PCH_SPLIT
	cbnz	w0, LBB0_16
; %bb.15:
	ldr	w8, [x21, #16]
	ldr	w9, [x21]
	orr	w8, w9, w8
	str	w8, [x21]
LBB0_16:
	ldr	w8, [x19]
Lloh20:
	adrp	x9, _DRM_MODE_FLAG_PHSYNC@GOTPAGE
Lloh21:
	ldr	x9, [x9, _DRM_MODE_FLAG_PHSYNC@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_18
; %bb.17:
Lloh23:
	adrp	x9, _DP_SYNC_HS_HIGH@GOTPAGE
Lloh24:
	ldr	x9, [x9, _DP_SYNC_HS_HIGH@GOTPAGEOFF]
Lloh25:
	ldr	w9, [x9]
	ldr	w10, [x21]
	orr	w9, w10, w9
	str	w9, [x21]
LBB0_18:
Lloh26:
	adrp	x9, _DRM_MODE_FLAG_PVSYNC@GOTPAGE
Lloh27:
	ldr	x9, [x9, _DRM_MODE_FLAG_PVSYNC@GOTPAGEOFF]
Lloh28:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_20
; %bb.19:
Lloh29:
	adrp	x8, _DP_SYNC_VS_HIGH@GOTPAGE
Lloh30:
	ldr	x8, [x8, _DP_SYNC_VS_HIGH@GOTPAGEOFF]
Lloh31:
	ldr	w8, [x8]
	ldr	w9, [x21]
	orr	w8, w9, w8
	str	w8, [x21]
	b	LBB0_21
LBB0_20:
	ldr	w8, [x21]
LBB0_21:
Lloh32:
	adrp	x9, _DP_LINK_TRAIN_OFF@GOTPAGE
Lloh33:
	ldr	x9, [x9, _DP_LINK_TRAIN_OFF@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x21]
	ldr	x9, [x21, #8]
	ldr	w9, [x9, #4]
Lloh35:
	adrp	x10, _DP_LANE_COUNT_ENHANCED_FRAME_EN@GOTPAGE
Lloh36:
	ldr	x10, [x10, _DP_LANE_COUNT_ENHANCED_FRAME_EN@GOTPAGEOFF]
Lloh37:
	ldr	w10, [x10]
	tst	w10, w9
	b.eq	LBB0_23
; %bb.22:
Lloh38:
	adrp	x9, _DP_ENHANCED_FRAMING@GOTPAGE
Lloh39:
	ldr	x9, [x9, _DP_ENHANCED_FRAMING@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
	orr	w8, w9, w8
	str	w8, [x21]
LBB0_23:
	ldr	w9, [x22]
	cmp	w9, #1
	b.ne	LBB0_25
; %bb.24:
Lloh41:
	adrp	x9, _DP_PIPEB_SELECT@GOTPAGE
Lloh42:
	ldr	x9, [x9, _DP_PIPEB_SELECT@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x21]
LBB0_25:
	mov	x0, x21
	bl	_is_cpu_edp
	cbz	x0, LBB0_32
; %bb.26:
	ldr	w8, [x19, #4]
	mov	w9, #3392
	movk	w9, #3, lsl #16
	cmp	w8, w9
	b.ge	LBB0_29
; %bb.27:
Lloh44:
	adrp	x8, _DP_PLL_FREQ_160MHZ@GOTPAGE
Lloh45:
	ldr	x8, [x8, _DP_PLL_FREQ_160MHZ@GOTPAGEOFF]
	b	LBB0_30
LBB0_28:
Lloh46:
	adrp	x8, _DP_LINK_TRAIN_OFF_CPT@GOTPAGE
Lloh47:
	ldr	x8, [x8, _DP_LINK_TRAIN_OFF_CPT@GOTPAGEOFF]
	b	LBB0_30
LBB0_29:
Lloh48:
	adrp	x8, _DP_PLL_FREQ_270MHZ@GOTPAGE
Lloh49:
	ldr	x8, [x8, _DP_PLL_FREQ_270MHZ@GOTPAGEOFF]
LBB0_30:
	ldr	w8, [x8]
	ldr	w9, [x21]
LBB0_31:
	orr	w8, w9, w8
	str	w8, [x21]
LBB0_32:
	mov	x0, x21
	bl	_is_cpu_edp
	cbz	x0, LBB0_34
; %bb.33:
	ldr	w1, [x19, #4]
	mov	x0, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_ironlake_set_pll_edp
LBB0_34:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_35:
	ldr	w8, [x19]
Lloh50:
	adrp	x9, _DRM_MODE_FLAG_PHSYNC@GOTPAGE
Lloh51:
	ldr	x9, [x9, _DRM_MODE_FLAG_PHSYNC@GOTPAGEOFF]
Lloh52:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_37
; %bb.36:
Lloh53:
	adrp	x9, _DP_SYNC_HS_HIGH@GOTPAGE
Lloh54:
	ldr	x9, [x9, _DP_SYNC_HS_HIGH@GOTPAGEOFF]
Lloh55:
	ldr	w9, [x9]
	ldr	w10, [x21]
	orr	w9, w10, w9
	str	w9, [x21]
LBB0_37:
Lloh56:
	adrp	x9, _DRM_MODE_FLAG_PVSYNC@GOTPAGE
Lloh57:
	ldr	x9, [x9, _DRM_MODE_FLAG_PVSYNC@GOTPAGEOFF]
Lloh58:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_39
; %bb.38:
Lloh59:
	adrp	x8, _DP_SYNC_VS_HIGH@GOTPAGE
Lloh60:
	ldr	x8, [x8, _DP_SYNC_VS_HIGH@GOTPAGEOFF]
Lloh61:
	ldr	w8, [x8]
	ldr	w9, [x21]
	orr	w8, w9, w8
	str	w8, [x21]
	b	LBB0_40
LBB0_39:
	ldr	w8, [x21]
LBB0_40:
Lloh62:
	adrp	x9, _DP_LINK_TRAIN_OFF_CPT@GOTPAGE
Lloh63:
	ldr	x9, [x9, _DP_LINK_TRAIN_OFF_CPT@GOTPAGEOFF]
Lloh64:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x21]
	ldr	x9, [x21, #8]
	ldr	w9, [x9, #4]
Lloh65:
	adrp	x10, _DP_LANE_COUNT_ENHANCED_FRAME_EN@GOTPAGE
Lloh66:
	ldr	x10, [x10, _DP_LANE_COUNT_ENHANCED_FRAME_EN@GOTPAGEOFF]
Lloh67:
	ldr	w10, [x10]
Lloh68:
	adrp	x11, _DP_ENHANCED_FRAMING@GOTPAGE
Lloh69:
	ldr	x11, [x11, _DP_ENHANCED_FRAMING@GOTPAGEOFF]
Lloh70:
	ldr	w11, [x11]
	tst	w10, w9
	csel	w9, wzr, w11, eq
	orr	w8, w8, w9
	ldr	w9, [x22]
	orr	w8, w8, w9, lsl #29
	str	w8, [x21]
	ldr	w9, [x19, #4]
	mov	w10, #3392
	movk	w10, #3, lsl #16
	cmp	w9, w10
	b.ge	LBB0_42
; %bb.41:
Lloh71:
	adrp	x9, _DP_PLL_FREQ_160MHZ@GOTPAGE
Lloh72:
	ldr	x9, [x9, _DP_PLL_FREQ_160MHZ@GOTPAGEOFF]
Lloh73:
	ldr	w9, [x9]
	b	LBB0_31
LBB0_42:
Lloh74:
	adrp	x9, _DP_PLL_FREQ_270MHZ@GOTPAGE
Lloh75:
	ldr	x9, [x9, _DP_PLL_FREQ_270MHZ@GOTPAGEOFF]
Lloh76:
	ldr	w9, [x9]
	b	LBB0_31
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.cfi_endproc
                                        ; -- End function
	.comm	_DP_DETECTED,4,2                ; @DP_DETECTED
	.comm	_DP_VOLTAGE_0_4,4,2             ; @DP_VOLTAGE_0_4
	.comm	_DP_PRE_EMPHASIS_0,4,2          ; @DP_PRE_EMPHASIS_0
	.comm	_DP_PORT_WIDTH_1,4,2            ; @DP_PORT_WIDTH_1
	.comm	_DP_PORT_WIDTH_2,4,2            ; @DP_PORT_WIDTH_2
	.comm	_DP_PORT_WIDTH_4,4,2            ; @DP_PORT_WIDTH_4
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Enabling DP audio on pipe %c\n"

	.comm	_DP_AUDIO_OUTPUT_ENABLE,4,2     ; @DP_AUDIO_OUTPUT_ENABLE
	.comm	_DRM_MODE_FLAG_PHSYNC,4,2       ; @DRM_MODE_FLAG_PHSYNC
	.comm	_DP_SYNC_HS_HIGH,4,2            ; @DP_SYNC_HS_HIGH
	.comm	_DRM_MODE_FLAG_PVSYNC,4,2       ; @DRM_MODE_FLAG_PVSYNC
	.comm	_DP_SYNC_VS_HIGH,4,2            ; @DP_SYNC_VS_HIGH
	.comm	_DP_LINK_TRAIN_OFF_CPT,4,2      ; @DP_LINK_TRAIN_OFF_CPT
	.comm	_DP_LANE_COUNT_ENHANCED_FRAME_EN,4,2 ; @DP_LANE_COUNT_ENHANCED_FRAME_EN
	.comm	_DP_ENHANCED_FRAMING,4,2        ; @DP_ENHANCED_FRAMING
	.comm	_DP_PLL_FREQ_160MHZ,4,2         ; @DP_PLL_FREQ_160MHZ
	.comm	_DP_PLL_FREQ_270MHZ,4,2         ; @DP_PLL_FREQ_270MHZ
	.comm	_DP_LINK_TRAIN_OFF,4,2          ; @DP_LINK_TRAIN_OFF
	.comm	_DP_PIPEB_SELECT,4,2            ; @DP_PIPEB_SELECT
	.no_dead_strip	_intel_dp_mode_set
.subsections_via_symbols
