	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_legacy_ext_dac_detect
_radeon_legacy_ext_dac_detect:          ## @radeon_legacy_ext_dac_detect
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_RADEON_GPIO_MONID@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32
	movl	%eax, -96(%rbp)                 ## 4-byte Spill
	movq	_RADEON_FP2_GEN_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movl	%eax, -92(%rbp)                 ## 4-byte Spill
	movq	_RADEON_DISP_OUTPUT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -88(%rbp)                 ## 4-byte Spill
	movq	_RADEON_CRTC2_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -84(%rbp)                 ## 4-byte Spill
	movq	_RADEON_DISP_LIN_TRANS_GRPH_A@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -80(%rbp)                 ## 4-byte Spill
	movq	_RADEON_DISP_LIN_TRANS_GRPH_B@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -76(%rbp)                 ## 4-byte Spill
	movq	_RADEON_DISP_LIN_TRANS_GRPH_C@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -72(%rbp)                 ## 4-byte Spill
	movq	_RADEON_DISP_LIN_TRANS_GRPH_D@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -68(%rbp)                 ## 4-byte Spill
	movq	_RADEON_DISP_LIN_TRANS_GRPH_E@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -64(%rbp)                 ## 4-byte Spill
	movq	_RADEON_DISP_LIN_TRANS_GRPH_F@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -60(%rbp)                 ## 4-byte Spill
	movq	_RADEON_CRTC2_H_TOTAL_DISP@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_RREG32
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	movq	_RADEON_CRTC2_V_TOTAL_DISP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movq	_RADEON_CRTC2_H_SYNC_STRT_WID@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_RADEON_CRTC2_V_SYNC_STRT_WID@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_RREG32
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movl	(%r14), %edi
	callq	_RREG32
	movq	_RADEON_GPIO_A_0@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r14), %edi
	callq	_WREG32
	movq	_RADEON_FP2_ON@GOTPCREL(%rip), %rax
	movq	_RADEON_FP2_PANEL_FORMAT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movq	_R200_FP2_SOURCE_SEL_TRANS_UNIT@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_RADEON_FP2_DVO_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	(%rbx), %edi
	movq	_R200_FP2_DVO_RATE_SEL_SDR@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	callq	_WREG32
	movq	_RADEON_DISP_OUTPUT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_DISP_DAC_SOURCE_RMX@GOTPCREL(%rip), %rax
	movq	_RADEON_DISP_TRANS_MATRIX_GRAPHICS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	callq	_WREG32
	movq	_RADEON_CRTC2_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_CRTC2_EN@GOTPCREL(%rip), %rax
	movq	_RADEON_CRTC2_DISP_REQ_EN_B@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	callq	_WREG32
	movq	_RADEON_DISP_LIN_TRANS_GRPH_A@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_RADEON_DISP_LIN_TRANS_GRPH_B@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1008, %esi                     ## imm = 0x3F0
	callq	_WREG32
	movq	_RADEON_DISP_LIN_TRANS_GRPH_C@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_RADEON_DISP_LIN_TRANS_GRPH_D@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1008, %esi                     ## imm = 0x3F0
	callq	_WREG32
	movq	_RADEON_DISP_LIN_TRANS_GRPH_E@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_RADEON_DISP_LIN_TRANS_GRPH_F@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1008, %esi                     ## imm = 0x3F0
	callq	_WREG32
	movl	(%r12), %edi
	movl	$16777224, %esi                 ## imm = 0x1000008
	callq	_WREG32
	movl	(%r15), %edi
	movl	$2048, %esi                     ## imm = 0x800
	callq	_WREG32
	movq	_RADEON_CRTC2_V_TOTAL_DISP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$524289, %esi                   ## imm = 0x80001
	callq	_WREG32
	movl	(%r13), %edi
	movl	$128, %esi
	callq	_WREG32
	movl	$200, %r15d
	movq	_RADEON_GPIO_Y_0@GOTPCREL(%rip), %r12
	movl	$1, %ebx
	jmp	LBB0_1
	.p2align	4, 0x90
LBB0_4:                                 ##   in Loop: Header=BB0_1 Depth=1
	callq	_msleep
	decl	%r15d
	je	LBB0_6
LBB0_1:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %edi
	callq	_RREG32
	testl	%eax, (%r12)
	jne	LBB0_7
## %bb.2:                               ##   in Loop: Header=BB0_1 Depth=1
	xorl	%eax, %eax
	callq	_drm_can_sleep
	movl	$1, %edi
	testl	%eax, %eax
	jne	LBB0_4
## %bb.3:                               ##   in Loop: Header=BB0_1 Depth=1
	callq	_mdelay
	decl	%r15d
	jne	LBB0_1
LBB0_6:
	xorl	%ebx, %ebx
LBB0_7:
	movq	_RADEON_DISP_LIN_TRANS_GRPH_A@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-80(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_DISP_LIN_TRANS_GRPH_B@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-76(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_DISP_LIN_TRANS_GRPH_C@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-72(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_DISP_LIN_TRANS_GRPH_D@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-68(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_DISP_LIN_TRANS_GRPH_E@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-64(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_DISP_LIN_TRANS_GRPH_F@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-60(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_CRTC2_H_TOTAL_DISP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-56(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_CRTC2_V_TOTAL_DISP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-52(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_CRTC2_H_SYNC_STRT_WID@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-48(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_CRTC2_V_SYNC_STRT_WID@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_CRTC2_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-84(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_DISP_OUTPUT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-88(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_FP2_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-92(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movl	(%r14), %edi
	movl	-96(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movl	%ebx, %eax
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_GPIO_MONID,4,2          ## @RADEON_GPIO_MONID
	.comm	_RADEON_FP2_GEN_CNTL,4,2        ## @RADEON_FP2_GEN_CNTL
	.comm	_RADEON_DISP_OUTPUT_CNTL,4,2    ## @RADEON_DISP_OUTPUT_CNTL
	.comm	_RADEON_CRTC2_GEN_CNTL,4,2      ## @RADEON_CRTC2_GEN_CNTL
	.comm	_RADEON_DISP_LIN_TRANS_GRPH_A,4,2 ## @RADEON_DISP_LIN_TRANS_GRPH_A
	.comm	_RADEON_DISP_LIN_TRANS_GRPH_B,4,2 ## @RADEON_DISP_LIN_TRANS_GRPH_B
	.comm	_RADEON_DISP_LIN_TRANS_GRPH_C,4,2 ## @RADEON_DISP_LIN_TRANS_GRPH_C
	.comm	_RADEON_DISP_LIN_TRANS_GRPH_D,4,2 ## @RADEON_DISP_LIN_TRANS_GRPH_D
	.comm	_RADEON_DISP_LIN_TRANS_GRPH_E,4,2 ## @RADEON_DISP_LIN_TRANS_GRPH_E
	.comm	_RADEON_DISP_LIN_TRANS_GRPH_F,4,2 ## @RADEON_DISP_LIN_TRANS_GRPH_F
	.comm	_RADEON_CRTC2_H_TOTAL_DISP,4,2  ## @RADEON_CRTC2_H_TOTAL_DISP
	.comm	_RADEON_CRTC2_V_TOTAL_DISP,4,2  ## @RADEON_CRTC2_V_TOTAL_DISP
	.comm	_RADEON_CRTC2_H_SYNC_STRT_WID,4,2 ## @RADEON_CRTC2_H_SYNC_STRT_WID
	.comm	_RADEON_CRTC2_V_SYNC_STRT_WID,4,2 ## @RADEON_CRTC2_V_SYNC_STRT_WID
	.comm	_RADEON_GPIO_A_0,4,2            ## @RADEON_GPIO_A_0
	.comm	_RADEON_FP2_ON,4,2              ## @RADEON_FP2_ON
	.comm	_RADEON_FP2_PANEL_FORMAT,4,2    ## @RADEON_FP2_PANEL_FORMAT
	.comm	_R200_FP2_SOURCE_SEL_TRANS_UNIT,4,2 ## @R200_FP2_SOURCE_SEL_TRANS_UNIT
	.comm	_RADEON_FP2_DVO_EN,4,2          ## @RADEON_FP2_DVO_EN
	.comm	_R200_FP2_DVO_RATE_SEL_SDR,4,2  ## @R200_FP2_DVO_RATE_SEL_SDR
	.comm	_RADEON_DISP_DAC_SOURCE_RMX,4,2 ## @RADEON_DISP_DAC_SOURCE_RMX
	.comm	_RADEON_DISP_TRANS_MATRIX_GRAPHICS,4,2 ## @RADEON_DISP_TRANS_MATRIX_GRAPHICS
	.comm	_RADEON_CRTC2_EN,4,2            ## @RADEON_CRTC2_EN
	.comm	_RADEON_CRTC2_DISP_REQ_EN_B,4,2 ## @RADEON_CRTC2_DISP_REQ_EN_B
	.comm	_RADEON_GPIO_Y_0,4,2            ## @RADEON_GPIO_Y_0
	.no_dead_strip	_radeon_legacy_ext_dac_detect
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_legacy_ext_dac_detect
_radeon_legacy_ext_dac_detect:          ; @radeon_legacy_ext_dac_detect
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #160
	.cfi_def_cfa_offset 160
	stp	x28, x27, [sp, #64]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #80]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #96]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #112]            ; 16-byte Folded Spill
	stp	x20, x19, [sp, #128]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #144]            ; 16-byte Folded Spill
	add	x29, sp, #144
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
Lloh0:
	adrp	x24, _RADEON_GPIO_MONID@GOTPAGE
Lloh1:
	ldr	x24, [x24, _RADEON_GPIO_MONID@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_RREG32
	str	w0, [sp, #60]                   ; 4-byte Folded Spill
Lloh2:
	adrp	x23, _RADEON_FP2_GEN_CNTL@GOTPAGE
Lloh3:
	ldr	x23, [x23, _RADEON_FP2_GEN_CNTL@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32
	str	w0, [sp, #56]                   ; 4-byte Folded Spill
Lloh4:
	adrp	x26, _RADEON_DISP_OUTPUT_CNTL@GOTPAGE
Lloh5:
	ldr	x26, [x26, _RADEON_DISP_OUTPUT_CNTL@GOTPAGEOFF]
	ldr	w0, [x26]
	bl	_RREG32
	str	w0, [sp, #52]                   ; 4-byte Folded Spill
Lloh6:
	adrp	x19, _RADEON_CRTC2_GEN_CNTL@GOTPAGE
Lloh7:
	ldr	x19, [x19, _RADEON_CRTC2_GEN_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32
	str	w0, [sp, #48]                   ; 4-byte Folded Spill
Lloh8:
	adrp	x8, _RADEON_DISP_LIN_TRANS_GRPH_A@GOTPAGE
Lloh9:
	ldr	x8, [x8, _RADEON_DISP_LIN_TRANS_GRPH_A@GOTPAGEOFF]
Lloh10:
	ldr	w0, [x8]
	bl	_RREG32
	str	w0, [sp, #44]                   ; 4-byte Folded Spill
Lloh11:
	adrp	x8, _RADEON_DISP_LIN_TRANS_GRPH_B@GOTPAGE
Lloh12:
	ldr	x8, [x8, _RADEON_DISP_LIN_TRANS_GRPH_B@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
	bl	_RREG32
	str	w0, [sp, #40]                   ; 4-byte Folded Spill
Lloh14:
	adrp	x8, _RADEON_DISP_LIN_TRANS_GRPH_C@GOTPAGE
Lloh15:
	ldr	x8, [x8, _RADEON_DISP_LIN_TRANS_GRPH_C@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
	bl	_RREG32
	str	w0, [sp, #36]                   ; 4-byte Folded Spill
Lloh17:
	adrp	x27, _RADEON_DISP_LIN_TRANS_GRPH_D@GOTPAGE
Lloh18:
	ldr	x27, [x27, _RADEON_DISP_LIN_TRANS_GRPH_D@GOTPAGEOFF]
	ldr	w0, [x27]
	bl	_RREG32
	str	w0, [sp, #32]                   ; 4-byte Folded Spill
Lloh19:
	adrp	x20, _RADEON_DISP_LIN_TRANS_GRPH_E@GOTPAGE
Lloh20:
	ldr	x20, [x20, _RADEON_DISP_LIN_TRANS_GRPH_E@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	str	w0, [sp, #28]                   ; 4-byte Folded Spill
Lloh21:
	adrp	x21, _RADEON_DISP_LIN_TRANS_GRPH_F@GOTPAGE
Lloh22:
	ldr	x21, [x21, _RADEON_DISP_LIN_TRANS_GRPH_F@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
	str	w0, [sp, #24]                   ; 4-byte Folded Spill
Lloh23:
	adrp	x22, _RADEON_CRTC2_H_TOTAL_DISP@GOTPAGE
Lloh24:
	ldr	x22, [x22, _RADEON_CRTC2_H_TOTAL_DISP@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_RREG32
	str	w0, [sp, #20]                   ; 4-byte Folded Spill
Lloh25:
	adrp	x25, _RADEON_CRTC2_V_TOTAL_DISP@GOTPAGE
Lloh26:
	ldr	x25, [x25, _RADEON_CRTC2_V_TOTAL_DISP@GOTPAGEOFF]
	ldr	w0, [x25]
	bl	_RREG32
	str	w0, [sp, #16]                   ; 4-byte Folded Spill
Lloh27:
	adrp	x28, _RADEON_CRTC2_H_SYNC_STRT_WID@GOTPAGE
Lloh28:
	ldr	x28, [x28, _RADEON_CRTC2_H_SYNC_STRT_WID@GOTPAGEOFF]
	ldr	w0, [x28]
	bl	_RREG32
	str	w0, [sp, #12]                   ; 4-byte Folded Spill
Lloh29:
	adrp	x8, _RADEON_CRTC2_V_SYNC_STRT_WID@GOTPAGE
Lloh30:
	ldr	x8, [x8, _RADEON_CRTC2_V_SYNC_STRT_WID@GOTPAGEOFF]
Lloh31:
	ldr	w0, [x8]
	bl	_RREG32
	str	w0, [sp, #8]                    ; 4-byte Folded Spill
	ldr	w0, [x24]
	bl	_RREG32
Lloh32:
	adrp	x8, _RADEON_GPIO_A_0@GOTPAGE
Lloh33:
	ldr	x8, [x8, _RADEON_GPIO_A_0@GOTPAGEOFF]
Lloh34:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w0, [x24]
	bl	_WREG32
Lloh35:
	adrp	x8, _RADEON_FP2_ON@GOTPAGE
Lloh36:
	ldr	x8, [x8, _RADEON_FP2_ON@GOTPAGEOFF]
	ldr	w0, [x23]
Lloh37:
	ldr	w8, [x8]
Lloh38:
	adrp	x9, _RADEON_FP2_PANEL_FORMAT@GOTPAGE
Lloh39:
	ldr	x9, [x9, _RADEON_FP2_PANEL_FORMAT@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh41:
	adrp	x9, _R200_FP2_SOURCE_SEL_TRANS_UNIT@GOTPAGE
Lloh42:
	ldr	x9, [x9, _R200_FP2_SOURCE_SEL_TRANS_UNIT@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh44:
	adrp	x9, _RADEON_FP2_DVO_EN@GOTPAGE
Lloh45:
	ldr	x9, [x9, _RADEON_FP2_DVO_EN@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh47:
	adrp	x9, _R200_FP2_DVO_RATE_SEL_SDR@GOTPAGE
Lloh48:
	ldr	x9, [x9, _R200_FP2_DVO_RATE_SEL_SDR@GOTPAGEOFF]
Lloh49:
	ldr	w9, [x9]
	orr	w1, w8, w9
	bl	_WREG32
Lloh50:
	adrp	x8, _RADEON_DISP_DAC_SOURCE_RMX@GOTPAGE
Lloh51:
	ldr	x8, [x8, _RADEON_DISP_DAC_SOURCE_RMX@GOTPAGEOFF]
	ldr	w0, [x26]
Lloh52:
	ldr	w8, [x8]
Lloh53:
	adrp	x9, _RADEON_DISP_TRANS_MATRIX_GRAPHICS@GOTPAGE
Lloh54:
	ldr	x9, [x9, _RADEON_DISP_TRANS_MATRIX_GRAPHICS@GOTPAGEOFF]
Lloh55:
	ldr	w9, [x9]
	orr	w1, w9, w8
	bl	_WREG32
Lloh56:
	adrp	x8, _RADEON_CRTC2_EN@GOTPAGE
Lloh57:
	ldr	x8, [x8, _RADEON_CRTC2_EN@GOTPAGEOFF]
	ldr	w0, [x19]
	mov	x26, x22
Lloh58:
	adrp	x22, _RADEON_DISP_LIN_TRANS_GRPH_C@GOTPAGE
Lloh59:
	ldr	x22, [x22, _RADEON_DISP_LIN_TRANS_GRPH_C@GOTPAGEOFF]
Lloh60:
	adrp	x19, _RADEON_DISP_LIN_TRANS_GRPH_A@GOTPAGE
Lloh61:
	ldr	x19, [x19, _RADEON_DISP_LIN_TRANS_GRPH_A@GOTPAGEOFF]
Lloh62:
	ldr	w8, [x8]
Lloh63:
	adrp	x9, _RADEON_CRTC2_DISP_REQ_EN_B@GOTPAGE
Lloh64:
	ldr	x9, [x9, _RADEON_CRTC2_DISP_REQ_EN_B@GOTPAGEOFF]
Lloh65:
	ldr	w9, [x9]
	orr	w1, w9, w8
	bl	_WREG32
	ldr	w0, [x19]
	mov	w1, #0
	bl	_WREG32
Lloh66:
	adrp	x8, _RADEON_DISP_LIN_TRANS_GRPH_B@GOTPAGE
Lloh67:
	ldr	x8, [x8, _RADEON_DISP_LIN_TRANS_GRPH_B@GOTPAGEOFF]
Lloh68:
	ldr	w0, [x8]
	mov	w1, #1008
	bl	_WREG32
	ldr	w0, [x22]
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x27]
	mov	w1, #1008
	bl	_WREG32
	ldr	w0, [x20]
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x21]
	mov	w1, #1008
	bl	_WREG32
	ldr	w0, [x26]
	mov	w1, #8
	movk	w1, #256, lsl #16
	bl	_WREG32
	ldr	w0, [x28]
	mov	w1, #2048
	bl	_WREG32
	ldr	w0, [x25]
Lloh69:
	adrp	x25, _RADEON_CRTC2_V_SYNC_STRT_WID@GOTPAGE
Lloh70:
	ldr	x25, [x25, _RADEON_CRTC2_V_SYNC_STRT_WID@GOTPAGEOFF]
	mov	w1, #1
	movk	w1, #8, lsl #16
	bl	_WREG32
	ldr	w0, [x25]
	mov	w1, #128
	bl	_WREG32
	mov	w23, #200
Lloh71:
	adrp	x26, _RADEON_GPIO_Y_0@GOTPAGE
Lloh72:
	ldr	x26, [x26, _RADEON_GPIO_Y_0@GOTPAGEOFF]
	b	LBB0_2
LBB0_1:                                 ;   in Loop: Header=BB0_2 Depth=1
	mov	w0, #1
	bl	_msleep
	subs	w23, w23, #1
	b.eq	LBB0_6
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x24]
	bl	_RREG32
	ldr	w8, [x26]
	tst	w8, w0
	b.ne	LBB0_5
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	bl	_drm_can_sleep
	cbnz	w0, LBB0_1
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	mov	w0, #1
	bl	_mdelay
	subs	w23, w23, #1
	b.ne	LBB0_2
	b	LBB0_6
LBB0_5:
	mov	w23, #1
LBB0_6:
	ldr	w0, [x19]
	ldr	w1, [sp, #44]                   ; 4-byte Folded Reload
	bl	_WREG32
Lloh73:
	adrp	x8, _RADEON_DISP_LIN_TRANS_GRPH_B@GOTPAGE
Lloh74:
	ldr	x8, [x8, _RADEON_DISP_LIN_TRANS_GRPH_B@GOTPAGEOFF]
Lloh75:
	ldr	w0, [x8]
	ldr	w1, [sp, #40]                   ; 4-byte Folded Reload
	bl	_WREG32
	ldr	w0, [x22]
	ldr	w1, [sp, #36]                   ; 4-byte Folded Reload
	bl	_WREG32
	ldr	w0, [x27]
	ldr	w1, [sp, #32]                   ; 4-byte Folded Reload
	bl	_WREG32
	ldr	w0, [x20]
	ldr	w1, [sp, #28]                   ; 4-byte Folded Reload
	bl	_WREG32
	ldr	w0, [x21]
	ldr	w1, [sp, #24]                   ; 4-byte Folded Reload
	bl	_WREG32
Lloh76:
	adrp	x8, _RADEON_CRTC2_H_TOTAL_DISP@GOTPAGE
Lloh77:
	ldr	x8, [x8, _RADEON_CRTC2_H_TOTAL_DISP@GOTPAGEOFF]
Lloh78:
	ldr	w0, [x8]
	ldr	w1, [sp, #20]                   ; 4-byte Folded Reload
	bl	_WREG32
Lloh79:
	adrp	x8, _RADEON_CRTC2_V_TOTAL_DISP@GOTPAGE
Lloh80:
	ldr	x8, [x8, _RADEON_CRTC2_V_TOTAL_DISP@GOTPAGEOFF]
Lloh81:
	ldr	w0, [x8]
	ldr	w1, [sp, #16]                   ; 4-byte Folded Reload
	bl	_WREG32
Lloh82:
	adrp	x8, _RADEON_CRTC2_H_SYNC_STRT_WID@GOTPAGE
Lloh83:
	ldr	x8, [x8, _RADEON_CRTC2_H_SYNC_STRT_WID@GOTPAGEOFF]
Lloh84:
	ldr	w0, [x8]
	ldr	w1, [sp, #12]                   ; 4-byte Folded Reload
	bl	_WREG32
	ldr	w0, [x25]
	ldr	w1, [sp, #8]                    ; 4-byte Folded Reload
	bl	_WREG32
Lloh85:
	adrp	x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGE
Lloh86:
	ldr	x8, [x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGEOFF]
Lloh87:
	ldr	w0, [x8]
	ldr	w1, [sp, #48]                   ; 4-byte Folded Reload
	bl	_WREG32
Lloh88:
	adrp	x8, _RADEON_DISP_OUTPUT_CNTL@GOTPAGE
Lloh89:
	ldr	x8, [x8, _RADEON_DISP_OUTPUT_CNTL@GOTPAGEOFF]
Lloh90:
	ldr	w0, [x8]
	ldr	w1, [sp, #52]                   ; 4-byte Folded Reload
	bl	_WREG32
Lloh91:
	adrp	x8, _RADEON_FP2_GEN_CNTL@GOTPAGE
Lloh92:
	ldr	x8, [x8, _RADEON_FP2_GEN_CNTL@GOTPAGEOFF]
Lloh93:
	ldr	w0, [x8]
	ldr	w1, [sp, #56]                   ; 4-byte Folded Reload
	bl	_WREG32
	ldr	w0, [x24]
	ldr	w1, [sp, #60]                   ; 4-byte Folded Reload
	bl	_WREG32
	mov	x0, x23
	ldp	x29, x30, [sp, #144]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #128]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #112]            ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #96]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #80]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #64]             ; 16-byte Folded Reload
	add	sp, sp, #160
	ret
	.loh AdrpLdrGot	Lloh71, Lloh72
	.loh AdrpLdrGot	Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGot	Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh62
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_GPIO_MONID,4,2          ; @RADEON_GPIO_MONID
	.comm	_RADEON_FP2_GEN_CNTL,4,2        ; @RADEON_FP2_GEN_CNTL
	.comm	_RADEON_DISP_OUTPUT_CNTL,4,2    ; @RADEON_DISP_OUTPUT_CNTL
	.comm	_RADEON_CRTC2_GEN_CNTL,4,2      ; @RADEON_CRTC2_GEN_CNTL
	.comm	_RADEON_DISP_LIN_TRANS_GRPH_A,4,2 ; @RADEON_DISP_LIN_TRANS_GRPH_A
	.comm	_RADEON_DISP_LIN_TRANS_GRPH_B,4,2 ; @RADEON_DISP_LIN_TRANS_GRPH_B
	.comm	_RADEON_DISP_LIN_TRANS_GRPH_C,4,2 ; @RADEON_DISP_LIN_TRANS_GRPH_C
	.comm	_RADEON_DISP_LIN_TRANS_GRPH_D,4,2 ; @RADEON_DISP_LIN_TRANS_GRPH_D
	.comm	_RADEON_DISP_LIN_TRANS_GRPH_E,4,2 ; @RADEON_DISP_LIN_TRANS_GRPH_E
	.comm	_RADEON_DISP_LIN_TRANS_GRPH_F,4,2 ; @RADEON_DISP_LIN_TRANS_GRPH_F
	.comm	_RADEON_CRTC2_H_TOTAL_DISP,4,2  ; @RADEON_CRTC2_H_TOTAL_DISP
	.comm	_RADEON_CRTC2_V_TOTAL_DISP,4,2  ; @RADEON_CRTC2_V_TOTAL_DISP
	.comm	_RADEON_CRTC2_H_SYNC_STRT_WID,4,2 ; @RADEON_CRTC2_H_SYNC_STRT_WID
	.comm	_RADEON_CRTC2_V_SYNC_STRT_WID,4,2 ; @RADEON_CRTC2_V_SYNC_STRT_WID
	.comm	_RADEON_GPIO_A_0,4,2            ; @RADEON_GPIO_A_0
	.comm	_RADEON_FP2_ON,4,2              ; @RADEON_FP2_ON
	.comm	_RADEON_FP2_PANEL_FORMAT,4,2    ; @RADEON_FP2_PANEL_FORMAT
	.comm	_R200_FP2_SOURCE_SEL_TRANS_UNIT,4,2 ; @R200_FP2_SOURCE_SEL_TRANS_UNIT
	.comm	_RADEON_FP2_DVO_EN,4,2          ; @RADEON_FP2_DVO_EN
	.comm	_R200_FP2_DVO_RATE_SEL_SDR,4,2  ; @R200_FP2_DVO_RATE_SEL_SDR
	.comm	_RADEON_DISP_DAC_SOURCE_RMX,4,2 ; @RADEON_DISP_DAC_SOURCE_RMX
	.comm	_RADEON_DISP_TRANS_MATRIX_GRAPHICS,4,2 ; @RADEON_DISP_TRANS_MATRIX_GRAPHICS
	.comm	_RADEON_CRTC2_EN,4,2            ; @RADEON_CRTC2_EN
	.comm	_RADEON_CRTC2_DISP_REQ_EN_B,4,2 ; @RADEON_CRTC2_DISP_REQ_EN_B
	.comm	_RADEON_GPIO_Y_0,4,2            ; @RADEON_GPIO_Y_0
	.no_dead_strip	_radeon_legacy_ext_dac_detect
.subsections_via_symbols
