	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function nv_load_state_ext
_nv_load_state_ext:                     ## @nv_load_state_ext
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r15
	movl	%esi, %r14d
	movq	%rdi, %rbx
	callq	_nouveau_drm
	movq	%rax, %r12
	movl	(%rax), %edi
	callq	_nv_device
	movq	%rax, -72(%rbp)                 ## 8-byte Spill
	movq	%rax, %rdi
	callq	_nouveau_timer
	movq	%rax, -64(%rbp)                 ## 8-byte Spill
	movq	(%r15), %rcx
	movslq	%r14d, %rax
	leaq	(%rax,%rax,8), %r13
	leaq	(%rcx,%r13,8), %r15
	movq	%r12, -56(%rbp)                 ## 8-byte Spill
	movl	(%r12), %edi
	movq	%rcx, %r12
	callq	_nv_device
	movq	(%rax), %rax
	movq	_NV_10@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	movq	%r13, -48(%rbp)                 ## 8-byte Spill
	jl	LBB0_7
## %bb.1:
	movq	%r12, %r13
	movq	%rbx, %rdi
	callq	_nv_two_heads
	testq	%rax, %rax
	je	LBB0_3
## %bb.2:
	movq	_NV_PCRTC_ENGINE_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	(%r15), %rcx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_NVWriteCRTC
LBB0_3:
	movq	_NV_PVIDEO_STOP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	-72(%rbp), %r12                 ## 8-byte Reload
	movq	%r12, %rdi
	movl	$1, %edx
	callq	_nv_wr32
	movq	_NV_PVIDEO_INTR_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_nv_wr32
	xorl	%edi, %edi
	callq	_NV_PVIDEO_OFFSET_BUFF
	movq	%r12, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_nv_wr32
	movl	$1, %edi
	callq	_NV_PVIDEO_OFFSET_BUFF
	movq	%r12, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_nv_wr32
	xorl	%edi, %edi
	callq	_NV_PVIDEO_LIMIT
	movq	%r12, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_nv_wr32
	movl	$1, %edi
	callq	_NV_PVIDEO_LIMIT
	movq	%r12, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_nv_wr32
	xorl	%edi, %edi
	callq	_NV_PVIDEO_UVPLANE_LIMIT
	movq	%r12, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_nv_wr32
	movl	$1, %edi
	callq	_NV_PVIDEO_UVPLANE_LIMIT
	movq	%r12, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_nv_wr32
	movq	_NV_PBUS_POWERCTRL_2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_nv_wr32
	movq	_NV_PCRTC_CURSOR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	-48(%rbp), %r12                 ## 8-byte Reload
	movq	8(%r13,%r12,8), %rcx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_NVWriteCRTC
	movq	_NV_PCRTC_830@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	16(%r13,%r12,8), %rcx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_NVWriteCRTC
	movq	_NV_PCRTC_834@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	24(%r13,%r12,8), %rcx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_NVWriteCRTC
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %edi
	callq	_nv_device
	movq	(%rax), %rax
	movq	_NV_30@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_5
## %bb.4:
	movq	_NV_PCRTC_GPIO_EXT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movq	32(%r13,%rax,8), %rcx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_NVWriteCRTC
LBB0_5:
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %edi
	callq	_nv_device
	movq	(%rax), %rax
	movq	_NV_40@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	movq	%r13, %r12
	movq	-48(%rbp), %r13                 ## 8-byte Reload
	jne	LBB0_7
## %bb.6:
	movq	_NV_PCRTC_850@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	40(%r12,%r13,8), %rcx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_NVWriteCRTC
	movq	_NV_PRAMDAC_900@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_NVReadRAMDAC
	movq	48(%r12,%r13,8), %rdx
	movq	_NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC@GOTPCREL(%rip), %rsi
	xorl	%ecx, %ecx
	cmpq	(%rsi), %rdx
	sete	%cl
	movq	_NV_PRAMDAC_900@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	andl	$-65537, %eax                   ## imm = 0xFFFEFFFF
	shll	$16, %ecx
	orl	%eax, %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_NVWriteRAMDAC
LBB0_7:
	movq	_NV_PCRTC_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	48(%r12,%r13,8), %rcx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_NVWriteCRTC
	movq	_NV_CIO_CRE_RPC0_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_RPC1_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_LSR_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_PIXEL_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_LCD__INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_HEB__INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_ENH_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_FF_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_FFLWM__INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	-56(%rbp), %r13                 ## 8-byte Reload
	movl	(%r13), %edi
	callq	_nv_device
	movq	(%rax), %rax
	movq	_NV_20@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_9
## %bb.8:
	movq	_NV_CIO_CRE_47@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
LBB0_9:
	movl	(%r13), %edi
	callq	_nv_device
	movq	(%rax), %rax
	movq	_NV_30@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_11
## %bb.10:
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	movl	$159, %ecx
	callq	_wr_cio_state
LBB0_11:
	movq	_NV_CIO_CRE_49@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_HCUR_ADDR0_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_HCUR_ADDR1_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_HCUR_ADDR2_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movl	(%r13), %edi
	callq	_nv_device
	movq	(%rax), %rax
	movq	_NV_40@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	movq	-48(%rbp), %r13                 ## 8-byte Reload
	jne	LBB0_13
## %bb.12:
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_nv_fix_nv40_hw_cursor
LBB0_13:
	movq	_NV_CIO_CRE_ILACE__INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_SCRATCH3__INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_SCRATCH4__INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %edi
	callq	_nv_device
	movq	(%rax), %rax
	movq	_NV_10@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_15
## %bb.14:
	movq	_NV_CIO_CRE_EBR_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_CSB@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_4B@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_TVOUT_LATENCY@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
LBB0_15:
	movq	%rbx, %rdi
	callq	_nv_gf4_disp_arch
	testq	%rax, %rax
	je	LBB0_19
## %bb.16:
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %edi
	callq	_nv_device
	movq	(%rax), %rax
	movq	_NV_10@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_18
## %bb.17:
	movq	%r12, %r13
	movq	_NV_PRMCIO_INP0__COLOR@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	movl	$650000000, %esi                ## imm = 0x26BE3680
	movl	$8, %ecx
	movl	$8, %r8d
	callq	_nouveau_timer_wait_eq
	movl	(%r12), %edx
	movq	%r13, %r12
	movq	-48(%rbp), %r13                 ## 8-byte Reload
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	movl	$650000000, %esi                ## imm = 0x26BE3680
	movl	$8, %ecx
	xorl	%r8d, %r8d
	callq	_nouveau_timer_wait_eq
LBB0_18:
	movq	_NV_CIO_CRE_42@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_53@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_54@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	64(%r12,%r13,8), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	xorl	%edx, %edx
	callq	_NVWriteVgaCrtc5758
	movq	64(%r12,%r13,8), %rax
	movl	4(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	$1, %edx
	callq	_NVWriteVgaCrtc5758
	movq	64(%r12,%r13,8), %rax
	movl	8(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	$2, %edx
	callq	_NVWriteVgaCrtc5758
	movq	64(%r12,%r13,8), %rax
	movl	12(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	$3, %edx
	callq	_NVWriteVgaCrtc5758
	movq	64(%r12,%r13,8), %rax
	movl	16(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	$4, %edx
	callq	_NVWriteVgaCrtc5758
	movq	64(%r12,%r13,8), %rax
	movl	20(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	$5, %edx
	callq	_NVWriteVgaCrtc5758
	movq	64(%r12,%r13,8), %rax
	movl	24(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	$6, %edx
	callq	_NVWriteVgaCrtc5758
	movq	64(%r12,%r13,8), %rax
	movl	28(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	$7, %edx
	callq	_NVWriteVgaCrtc5758
	movq	64(%r12,%r13,8), %rax
	movl	32(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	$8, %edx
	callq	_NVWriteVgaCrtc5758
	movq	64(%r12,%r13,8), %rax
	movl	36(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	$9, %edx
	callq	_NVWriteVgaCrtc5758
	movq	64(%r12,%r13,8), %rax
	movl	40(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	$10, %edx
	callq	_NVWriteVgaCrtc5758
	movq	64(%r12,%r13,8), %rax
	movl	44(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	$11, %edx
	callq	_NVWriteVgaCrtc5758
	movq	64(%r12,%r13,8), %rax
	movl	48(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	$12, %edx
	callq	_NVWriteVgaCrtc5758
	movq	64(%r12,%r13,8), %rax
	movl	52(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	$13, %edx
	callq	_NVWriteVgaCrtc5758
	movq	64(%r12,%r13,8), %rax
	movl	56(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	$14, %edx
	callq	_NVWriteVgaCrtc5758
	movq	64(%r12,%r13,8), %rax
	movl	60(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	$15, %edx
	callq	_NVWriteVgaCrtc5758
	movq	_NV_CIO_CRE_59@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_5B@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_85@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
	movq	_NV_CIO_CRE_86@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_wr_cio_state
LBB0_19:
	movq	_NV_PCRTC_START@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	56(%r12,%r13,8), %rcx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_NVWriteCRTC                    ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_NV_10,8,3                      ## @NV_10
	.comm	_NV_PCRTC_ENGINE_CTRL,4,2       ## @NV_PCRTC_ENGINE_CTRL
	.comm	_NV_PVIDEO_STOP,4,2             ## @NV_PVIDEO_STOP
	.comm	_NV_PVIDEO_INTR_EN,4,2          ## @NV_PVIDEO_INTR_EN
	.comm	_NV_PBUS_POWERCTRL_2,4,2        ## @NV_PBUS_POWERCTRL_2
	.comm	_NV_PCRTC_CURSOR_CONFIG,4,2     ## @NV_PCRTC_CURSOR_CONFIG
	.comm	_NV_PCRTC_830,4,2               ## @NV_PCRTC_830
	.comm	_NV_PCRTC_834,4,2               ## @NV_PCRTC_834
	.comm	_NV_30,8,3                      ## @NV_30
	.comm	_NV_PCRTC_GPIO_EXT,4,2          ## @NV_PCRTC_GPIO_EXT
	.comm	_NV_40,8,3                      ## @NV_40
	.comm	_NV_PCRTC_850,4,2               ## @NV_PCRTC_850
	.comm	_NV_PRAMDAC_900,4,2             ## @NV_PRAMDAC_900
	.comm	_NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC,8,3 ## @NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC
	.comm	_NV_PCRTC_CONFIG,4,2            ## @NV_PCRTC_CONFIG
	.comm	_NV_CIO_CRE_RPC0_INDEX,4,2      ## @NV_CIO_CRE_RPC0_INDEX
	.comm	_NV_CIO_CRE_RPC1_INDEX,4,2      ## @NV_CIO_CRE_RPC1_INDEX
	.comm	_NV_CIO_CRE_LSR_INDEX,4,2       ## @NV_CIO_CRE_LSR_INDEX
	.comm	_NV_CIO_CRE_PIXEL_INDEX,4,2     ## @NV_CIO_CRE_PIXEL_INDEX
	.comm	_NV_CIO_CRE_LCD__INDEX,4,2      ## @NV_CIO_CRE_LCD__INDEX
	.comm	_NV_CIO_CRE_HEB__INDEX,4,2      ## @NV_CIO_CRE_HEB__INDEX
	.comm	_NV_CIO_CRE_ENH_INDEX,4,2       ## @NV_CIO_CRE_ENH_INDEX
	.comm	_NV_CIO_CRE_FF_INDEX,4,2        ## @NV_CIO_CRE_FF_INDEX
	.comm	_NV_CIO_CRE_FFLWM__INDEX,4,2    ## @NV_CIO_CRE_FFLWM__INDEX
	.comm	_NV_20,8,3                      ## @NV_20
	.comm	_NV_CIO_CRE_47,4,2              ## @NV_CIO_CRE_47
	.comm	_NV_CIO_CRE_49,4,2              ## @NV_CIO_CRE_49
	.comm	_NV_CIO_CRE_HCUR_ADDR0_INDEX,4,2 ## @NV_CIO_CRE_HCUR_ADDR0_INDEX
	.comm	_NV_CIO_CRE_HCUR_ADDR1_INDEX,4,2 ## @NV_CIO_CRE_HCUR_ADDR1_INDEX
	.comm	_NV_CIO_CRE_HCUR_ADDR2_INDEX,4,2 ## @NV_CIO_CRE_HCUR_ADDR2_INDEX
	.comm	_NV_CIO_CRE_ILACE__INDEX,4,2    ## @NV_CIO_CRE_ILACE__INDEX
	.comm	_NV_CIO_CRE_SCRATCH3__INDEX,4,2 ## @NV_CIO_CRE_SCRATCH3__INDEX
	.comm	_NV_CIO_CRE_SCRATCH4__INDEX,4,2 ## @NV_CIO_CRE_SCRATCH4__INDEX
	.comm	_NV_CIO_CRE_EBR_INDEX,4,2       ## @NV_CIO_CRE_EBR_INDEX
	.comm	_NV_CIO_CRE_CSB,4,2             ## @NV_CIO_CRE_CSB
	.comm	_NV_CIO_CRE_4B,4,2              ## @NV_CIO_CRE_4B
	.comm	_NV_CIO_CRE_TVOUT_LATENCY,4,2   ## @NV_CIO_CRE_TVOUT_LATENCY
	.comm	_NV_PRMCIO_INP0__COLOR,4,2      ## @NV_PRMCIO_INP0__COLOR
	.comm	_NV_CIO_CRE_42,4,2              ## @NV_CIO_CRE_42
	.comm	_NV_CIO_CRE_53,4,2              ## @NV_CIO_CRE_53
	.comm	_NV_CIO_CRE_54,4,2              ## @NV_CIO_CRE_54
	.comm	_NV_CIO_CRE_59,4,2              ## @NV_CIO_CRE_59
	.comm	_NV_CIO_CRE_5B,4,2              ## @NV_CIO_CRE_5B
	.comm	_NV_CIO_CRE_85,4,2              ## @NV_CIO_CRE_85
	.comm	_NV_CIO_CRE_86,4,2              ## @NV_CIO_CRE_86
	.comm	_NV_PCRTC_START,4,2             ## @NV_PCRTC_START
	.no_dead_strip	_nv_load_state_ext
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function nv_load_state_ext
_nv_load_state_ext:                     ; @nv_load_state_ext
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x2
	mov	x19, x1
	mov	x20, x0
	bl	_nouveau_drm
	mov	x23, x0
	ldr	w0, [x0]
	bl	_nv_device
	mov	x24, x0
	bl	_nouveau_timer
	mov	x28, x0
	ldr	x25, [x21]
	sxtw	x26, w19
	mov	w8, #72
	smaddl	x21, w19, w8, x25
	ldr	w0, [x23]
	bl	_nv_device
	ldr	x8, [x0]
Lloh0:
	adrp	x27, _NV_10@GOTPAGE
Lloh1:
	ldr	x27, [x27, _NV_10@GOTPAGEOFF]
	ldr	x9, [x27]
Lloh2:
	adrp	x22, _NV_40@GOTPAGE
Lloh3:
	ldr	x22, [x22, _NV_40@GOTPAGEOFF]
	cmp	x8, x9
	b.lt	LBB0_7
; %bb.1:
	mov	x0, x20
	bl	_nv_two_heads
	cbz	x0, LBB0_3
; %bb.2:
Lloh4:
	adrp	x8, _NV_PCRTC_ENGINE_CTRL@GOTPAGE
Lloh5:
	ldr	x8, [x8, _NV_PCRTC_ENGINE_CTRL@GOTPAGEOFF]
Lloh6:
	ldr	w2, [x8]
	ldr	x3, [x21]
	mov	x0, x20
	mov	x1, x19
	bl	_NVWriteCRTC
LBB0_3:
Lloh7:
	adrp	x8, _NV_PVIDEO_STOP@GOTPAGE
Lloh8:
	ldr	x8, [x8, _NV_PVIDEO_STOP@GOTPAGEOFF]
Lloh9:
	ldr	w1, [x8]
	mov	x0, x24
	mov	w2, #1
	bl	_nv_wr32
Lloh10:
	adrp	x8, _NV_PVIDEO_INTR_EN@GOTPAGE
Lloh11:
	ldr	x8, [x8, _NV_PVIDEO_INTR_EN@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
	mov	x0, x24
	mov	w2, #0
	bl	_nv_wr32
	mov	w0, #0
	bl	_NV_PVIDEO_OFFSET_BUFF
	mov	x1, x0
	mov	x0, x24
	mov	w2, #0
	bl	_nv_wr32
	mov	w0, #1
	bl	_NV_PVIDEO_OFFSET_BUFF
	mov	x1, x0
	mov	x0, x24
	mov	w2, #0
	bl	_nv_wr32
	mov	w0, #0
	bl	_NV_PVIDEO_LIMIT
	mov	x1, x0
	mov	x0, x24
	mov	w2, #0
	bl	_nv_wr32
	mov	w0, #1
	bl	_NV_PVIDEO_LIMIT
	mov	x1, x0
	mov	x0, x24
	mov	w2, #0
	bl	_nv_wr32
	mov	w0, #0
	bl	_NV_PVIDEO_UVPLANE_LIMIT
	mov	x1, x0
	mov	x0, x24
	mov	w2, #0
	bl	_nv_wr32
	mov	w0, #1
	bl	_NV_PVIDEO_UVPLANE_LIMIT
	mov	x1, x0
	mov	x0, x24
	mov	w2, #0
	bl	_nv_wr32
Lloh13:
	adrp	x8, _NV_PBUS_POWERCTRL_2@GOTPAGE
Lloh14:
	ldr	x8, [x8, _NV_PBUS_POWERCTRL_2@GOTPAGEOFF]
Lloh15:
	ldr	w1, [x8]
	mov	x0, x24
	mov	w2, #0
	bl	_nv_wr32
Lloh16:
	adrp	x8, _NV_PCRTC_CURSOR_CONFIG@GOTPAGE
Lloh17:
	ldr	x8, [x8, _NV_PCRTC_CURSOR_CONFIG@GOTPAGEOFF]
Lloh18:
	ldr	w2, [x8]
	mov	w8, #72
	madd	x24, x26, x8, x25
	ldr	x3, [x24, #8]
	mov	x0, x20
	mov	x1, x19
	bl	_NVWriteCRTC
Lloh19:
	adrp	x8, _NV_PCRTC_830@GOTPAGE
Lloh20:
	ldr	x8, [x8, _NV_PCRTC_830@GOTPAGEOFF]
Lloh21:
	ldr	w2, [x8]
	ldr	x3, [x24, #16]
	mov	x0, x20
	mov	x1, x19
	bl	_NVWriteCRTC
Lloh22:
	adrp	x8, _NV_PCRTC_834@GOTPAGE
Lloh23:
	ldr	x8, [x8, _NV_PCRTC_834@GOTPAGEOFF]
Lloh24:
	ldr	w2, [x8]
	ldr	x3, [x24, #24]
	mov	x0, x20
	mov	x1, x19
	bl	_NVWriteCRTC
	ldr	w0, [x23]
	bl	_nv_device
	ldr	x8, [x0]
Lloh25:
	adrp	x9, _NV_30@GOTPAGE
Lloh26:
	ldr	x9, [x9, _NV_30@GOTPAGEOFF]
Lloh27:
	ldr	x9, [x9]
	cmp	x8, x9
	b.lt	LBB0_5
; %bb.4:
Lloh28:
	adrp	x8, _NV_PCRTC_GPIO_EXT@GOTPAGE
Lloh29:
	ldr	x8, [x8, _NV_PCRTC_GPIO_EXT@GOTPAGEOFF]
Lloh30:
	ldr	w2, [x8]
	mov	w8, #72
	madd	x8, x26, x8, x25
	ldr	x3, [x8, #32]
	mov	x0, x20
	mov	x1, x19
	bl	_NVWriteCRTC
LBB0_5:
	ldr	w0, [x23]
	bl	_nv_device
	ldr	x8, [x0]
	ldr	x9, [x22]
	cmp	x8, x9
	b.ne	LBB0_7
; %bb.6:
Lloh31:
	adrp	x8, _NV_PCRTC_850@GOTPAGE
Lloh32:
	ldr	x8, [x8, _NV_PCRTC_850@GOTPAGEOFF]
Lloh33:
	ldr	w2, [x8]
	mov	w8, #72
	madd	x24, x26, x8, x25
	ldr	x3, [x24, #40]
	mov	x0, x20
	mov	x1, x19
	bl	_NVWriteCRTC
	mov	x27, x22
Lloh34:
	adrp	x22, _NV_PRAMDAC_900@GOTPAGE
Lloh35:
	ldr	x22, [x22, _NV_PRAMDAC_900@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	x0, x20
	mov	x1, x19
	bl	_NVReadRAMDAC
	mov	x3, x0
Lloh36:
	adrp	x8, _NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC@GOTPAGE
Lloh37:
	ldr	x8, [x8, _NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC@GOTPAGEOFF]
	ldr	x9, [x24, #48]
Lloh38:
	ldr	x8, [x8]
	cmp	x9, x8
	cset	w8, eq
	ldr	w2, [x22]
	mov	x22, x27
Lloh39:
	adrp	x27, _NV_10@GOTPAGE
Lloh40:
	ldr	x27, [x27, _NV_10@GOTPAGEOFF]
	bfi	w3, w8, #16, #1
	mov	x0, x20
	mov	x1, x19
	bl	_NVWriteRAMDAC
LBB0_7:
Lloh41:
	adrp	x8, _NV_PCRTC_CONFIG@GOTPAGE
Lloh42:
	ldr	x8, [x8, _NV_PCRTC_CONFIG@GOTPAGEOFF]
Lloh43:
	ldr	w2, [x8]
	mov	w8, #72
	madd	x8, x26, x8, x25
	ldr	x3, [x8, #48]
	mov	x0, x20
	mov	x1, x19
	bl	_NVWriteCRTC
Lloh44:
	adrp	x8, _NV_CIO_CRE_RPC0_INDEX@GOTPAGE
Lloh45:
	ldr	x8, [x8, _NV_CIO_CRE_RPC0_INDEX@GOTPAGEOFF]
Lloh46:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh47:
	adrp	x8, _NV_CIO_CRE_RPC1_INDEX@GOTPAGE
Lloh48:
	ldr	x8, [x8, _NV_CIO_CRE_RPC1_INDEX@GOTPAGEOFF]
Lloh49:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh50:
	adrp	x8, _NV_CIO_CRE_LSR_INDEX@GOTPAGE
Lloh51:
	ldr	x8, [x8, _NV_CIO_CRE_LSR_INDEX@GOTPAGEOFF]
Lloh52:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh53:
	adrp	x8, _NV_CIO_CRE_PIXEL_INDEX@GOTPAGE
Lloh54:
	ldr	x8, [x8, _NV_CIO_CRE_PIXEL_INDEX@GOTPAGEOFF]
Lloh55:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh56:
	adrp	x8, _NV_CIO_CRE_LCD__INDEX@GOTPAGE
Lloh57:
	ldr	x8, [x8, _NV_CIO_CRE_LCD__INDEX@GOTPAGEOFF]
Lloh58:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh59:
	adrp	x8, _NV_CIO_CRE_HEB__INDEX@GOTPAGE
Lloh60:
	ldr	x8, [x8, _NV_CIO_CRE_HEB__INDEX@GOTPAGEOFF]
Lloh61:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh62:
	adrp	x8, _NV_CIO_CRE_ENH_INDEX@GOTPAGE
Lloh63:
	ldr	x8, [x8, _NV_CIO_CRE_ENH_INDEX@GOTPAGEOFF]
Lloh64:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh65:
	adrp	x8, _NV_CIO_CRE_FF_INDEX@GOTPAGE
Lloh66:
	ldr	x8, [x8, _NV_CIO_CRE_FF_INDEX@GOTPAGEOFF]
Lloh67:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh68:
	adrp	x8, _NV_CIO_CRE_FFLWM__INDEX@GOTPAGE
Lloh69:
	ldr	x8, [x8, _NV_CIO_CRE_FFLWM__INDEX@GOTPAGEOFF]
Lloh70:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
	ldr	w0, [x23]
	bl	_nv_device
	ldr	x8, [x0]
Lloh71:
	adrp	x9, _NV_20@GOTPAGE
Lloh72:
	ldr	x9, [x9, _NV_20@GOTPAGEOFF]
Lloh73:
	ldr	x9, [x9]
	cmp	x8, x9
	b.lt	LBB0_9
; %bb.8:
Lloh74:
	adrp	x8, _NV_CIO_CRE_47@GOTPAGE
Lloh75:
	ldr	x8, [x8, _NV_CIO_CRE_47@GOTPAGEOFF]
Lloh76:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
LBB0_9:
	ldr	w0, [x23]
	bl	_nv_device
	ldr	x8, [x0]
Lloh77:
	adrp	x9, _NV_30@GOTPAGE
Lloh78:
	ldr	x9, [x9, _NV_30@GOTPAGEOFF]
Lloh79:
	ldr	x9, [x9]
	cmp	x8, x9
	b.lt	LBB0_11
; %bb.10:
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	mov	w3, #159
	bl	_wr_cio_state
LBB0_11:
Lloh80:
	adrp	x8, _NV_CIO_CRE_49@GOTPAGE
Lloh81:
	ldr	x8, [x8, _NV_CIO_CRE_49@GOTPAGEOFF]
Lloh82:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh83:
	adrp	x8, _NV_CIO_CRE_HCUR_ADDR0_INDEX@GOTPAGE
Lloh84:
	ldr	x8, [x8, _NV_CIO_CRE_HCUR_ADDR0_INDEX@GOTPAGEOFF]
Lloh85:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh86:
	adrp	x8, _NV_CIO_CRE_HCUR_ADDR1_INDEX@GOTPAGE
Lloh87:
	ldr	x8, [x8, _NV_CIO_CRE_HCUR_ADDR1_INDEX@GOTPAGEOFF]
Lloh88:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh89:
	adrp	x8, _NV_CIO_CRE_HCUR_ADDR2_INDEX@GOTPAGE
Lloh90:
	ldr	x8, [x8, _NV_CIO_CRE_HCUR_ADDR2_INDEX@GOTPAGEOFF]
Lloh91:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
	ldr	w0, [x23]
	bl	_nv_device
	ldr	x8, [x0]
	ldr	x9, [x22]
	cmp	x8, x9
	b.ne	LBB0_13
; %bb.12:
	mov	x0, x20
	mov	x1, x19
	bl	_nv_fix_nv40_hw_cursor
LBB0_13:
Lloh92:
	adrp	x8, _NV_CIO_CRE_ILACE__INDEX@GOTPAGE
Lloh93:
	ldr	x8, [x8, _NV_CIO_CRE_ILACE__INDEX@GOTPAGEOFF]
Lloh94:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh95:
	adrp	x8, _NV_CIO_CRE_SCRATCH3__INDEX@GOTPAGE
Lloh96:
	ldr	x8, [x8, _NV_CIO_CRE_SCRATCH3__INDEX@GOTPAGEOFF]
Lloh97:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh98:
	adrp	x8, _NV_CIO_CRE_SCRATCH4__INDEX@GOTPAGE
Lloh99:
	ldr	x8, [x8, _NV_CIO_CRE_SCRATCH4__INDEX@GOTPAGEOFF]
Lloh100:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
	ldr	w0, [x23]
	bl	_nv_device
	ldr	x8, [x0]
	ldr	x9, [x27]
	cmp	x8, x9
	b.lt	LBB0_15
; %bb.14:
Lloh101:
	adrp	x8, _NV_CIO_CRE_EBR_INDEX@GOTPAGE
Lloh102:
	ldr	x8, [x8, _NV_CIO_CRE_EBR_INDEX@GOTPAGEOFF]
Lloh103:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh104:
	adrp	x8, _NV_CIO_CRE_CSB@GOTPAGE
Lloh105:
	ldr	x8, [x8, _NV_CIO_CRE_CSB@GOTPAGEOFF]
Lloh106:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh107:
	adrp	x8, _NV_CIO_CRE_4B@GOTPAGE
Lloh108:
	ldr	x8, [x8, _NV_CIO_CRE_4B@GOTPAGEOFF]
Lloh109:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh110:
	adrp	x8, _NV_CIO_CRE_TVOUT_LATENCY@GOTPAGE
Lloh111:
	ldr	x8, [x8, _NV_CIO_CRE_TVOUT_LATENCY@GOTPAGEOFF]
Lloh112:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
LBB0_15:
	mov	x0, x20
	bl	_nv_gf4_disp_arch
	cbz	x0, LBB0_19
; %bb.16:
	ldr	w0, [x23]
	bl	_nv_device
	ldr	x8, [x0]
	ldr	x9, [x27]
	cmp	x8, x9
	b.ne	LBB0_18
; %bb.17:
Lloh113:
	adrp	x22, _NV_PRMCIO_INP0__COLOR@GOTPAGE
Lloh114:
	ldr	x22, [x22, _NV_PRMCIO_INP0__COLOR@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	x0, x28
	mov	w1, #13952
	movk	w1, #9918, lsl #16
	mov	w3, #8
	mov	w4, #8
	bl	_nouveau_timer_wait_eq
	ldr	w2, [x22]
	mov	x0, x28
	mov	w1, #13952
	movk	w1, #9918, lsl #16
	mov	w3, #8
	mov	w4, #0
	bl	_nouveau_timer_wait_eq
LBB0_18:
Lloh115:
	adrp	x8, _NV_CIO_CRE_42@GOTPAGE
Lloh116:
	ldr	x8, [x8, _NV_CIO_CRE_42@GOTPAGEOFF]
Lloh117:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh118:
	adrp	x8, _NV_CIO_CRE_53@GOTPAGE
Lloh119:
	ldr	x8, [x8, _NV_CIO_CRE_53@GOTPAGEOFF]
Lloh120:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh121:
	adrp	x8, _NV_CIO_CRE_54@GOTPAGE
Lloh122:
	ldr	x8, [x8, _NV_CIO_CRE_54@GOTPAGEOFF]
Lloh123:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
	mov	w8, #72
	madd	x22, x26, x8, x25
	ldr	x8, [x22, #64]
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	w2, #0
	bl	_NVWriteVgaCrtc5758
	ldr	x8, [x22, #64]
	ldr	w3, [x8, #4]
	mov	x0, x20
	mov	x1, x19
	mov	w2, #1
	bl	_NVWriteVgaCrtc5758
	ldr	x8, [x22, #64]
	ldr	w3, [x8, #8]
	mov	x0, x20
	mov	x1, x19
	mov	w2, #2
	bl	_NVWriteVgaCrtc5758
	ldr	x8, [x22, #64]
	ldr	w3, [x8, #12]
	mov	x0, x20
	mov	x1, x19
	mov	w2, #3
	bl	_NVWriteVgaCrtc5758
	ldr	x8, [x22, #64]
	ldr	w3, [x8, #16]
	mov	x0, x20
	mov	x1, x19
	mov	w2, #4
	bl	_NVWriteVgaCrtc5758
	ldr	x8, [x22, #64]
	ldr	w3, [x8, #20]
	mov	x0, x20
	mov	x1, x19
	mov	w2, #5
	bl	_NVWriteVgaCrtc5758
	ldr	x8, [x22, #64]
	ldr	w3, [x8, #24]
	mov	x0, x20
	mov	x1, x19
	mov	w2, #6
	bl	_NVWriteVgaCrtc5758
	ldr	x8, [x22, #64]
	ldr	w3, [x8, #28]
	mov	x0, x20
	mov	x1, x19
	mov	w2, #7
	bl	_NVWriteVgaCrtc5758
	ldr	x8, [x22, #64]
	ldr	w3, [x8, #32]
	mov	x0, x20
	mov	x1, x19
	mov	w2, #8
	bl	_NVWriteVgaCrtc5758
	ldr	x8, [x22, #64]
	ldr	w3, [x8, #36]
	mov	x0, x20
	mov	x1, x19
	mov	w2, #9
	bl	_NVWriteVgaCrtc5758
	ldr	x8, [x22, #64]
	ldr	w3, [x8, #40]
	mov	x0, x20
	mov	x1, x19
	mov	w2, #10
	bl	_NVWriteVgaCrtc5758
	ldr	x8, [x22, #64]
	ldr	w3, [x8, #44]
	mov	x0, x20
	mov	x1, x19
	mov	w2, #11
	bl	_NVWriteVgaCrtc5758
	ldr	x8, [x22, #64]
	ldr	w3, [x8, #48]
	mov	x0, x20
	mov	x1, x19
	mov	w2, #12
	bl	_NVWriteVgaCrtc5758
	ldr	x8, [x22, #64]
	ldr	w3, [x8, #52]
	mov	x0, x20
	mov	x1, x19
	mov	w2, #13
	bl	_NVWriteVgaCrtc5758
	ldr	x8, [x22, #64]
	ldr	w3, [x8, #56]
	mov	x0, x20
	mov	x1, x19
	mov	w2, #14
	bl	_NVWriteVgaCrtc5758
	ldr	x8, [x22, #64]
	ldr	w3, [x8, #60]
	mov	x0, x20
	mov	x1, x19
	mov	w2, #15
	bl	_NVWriteVgaCrtc5758
Lloh124:
	adrp	x8, _NV_CIO_CRE_59@GOTPAGE
Lloh125:
	ldr	x8, [x8, _NV_CIO_CRE_59@GOTPAGEOFF]
Lloh126:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh127:
	adrp	x8, _NV_CIO_CRE_5B@GOTPAGE
Lloh128:
	ldr	x8, [x8, _NV_CIO_CRE_5B@GOTPAGEOFF]
Lloh129:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh130:
	adrp	x8, _NV_CIO_CRE_85@GOTPAGE
Lloh131:
	ldr	x8, [x8, _NV_CIO_CRE_85@GOTPAGEOFF]
Lloh132:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
Lloh133:
	adrp	x8, _NV_CIO_CRE_86@GOTPAGE
Lloh134:
	ldr	x8, [x8, _NV_CIO_CRE_86@GOTPAGEOFF]
Lloh135:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_wr_cio_state
LBB0_19:
Lloh136:
	adrp	x8, _NV_PCRTC_START@GOTPAGE
Lloh137:
	ldr	x8, [x8, _NV_PCRTC_START@GOTPAGEOFF]
Lloh138:
	ldr	w2, [x8]
	mov	w8, #72
	madd	x8, x26, x8, x25
	ldr	x3, [x8, #56]
	mov	x0, x20
	mov	x1, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_NVWriteCRTC
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGot	Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh133, Lloh134, Lloh135
	.loh AdrpLdrGotLdr	Lloh130, Lloh131, Lloh132
	.loh AdrpLdrGotLdr	Lloh127, Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.loh AdrpLdrGotLdr	Lloh136, Lloh137, Lloh138
	.cfi_endproc
                                        ; -- End function
	.comm	_NV_10,8,3                      ; @NV_10
	.comm	_NV_PCRTC_ENGINE_CTRL,4,2       ; @NV_PCRTC_ENGINE_CTRL
	.comm	_NV_PVIDEO_STOP,4,2             ; @NV_PVIDEO_STOP
	.comm	_NV_PVIDEO_INTR_EN,4,2          ; @NV_PVIDEO_INTR_EN
	.comm	_NV_PBUS_POWERCTRL_2,4,2        ; @NV_PBUS_POWERCTRL_2
	.comm	_NV_PCRTC_CURSOR_CONFIG,4,2     ; @NV_PCRTC_CURSOR_CONFIG
	.comm	_NV_PCRTC_830,4,2               ; @NV_PCRTC_830
	.comm	_NV_PCRTC_834,4,2               ; @NV_PCRTC_834
	.comm	_NV_30,8,3                      ; @NV_30
	.comm	_NV_PCRTC_GPIO_EXT,4,2          ; @NV_PCRTC_GPIO_EXT
	.comm	_NV_40,8,3                      ; @NV_40
	.comm	_NV_PCRTC_850,4,2               ; @NV_PCRTC_850
	.comm	_NV_PRAMDAC_900,4,2             ; @NV_PRAMDAC_900
	.comm	_NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC,8,3 ; @NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC
	.comm	_NV_PCRTC_CONFIG,4,2            ; @NV_PCRTC_CONFIG
	.comm	_NV_CIO_CRE_RPC0_INDEX,4,2      ; @NV_CIO_CRE_RPC0_INDEX
	.comm	_NV_CIO_CRE_RPC1_INDEX,4,2      ; @NV_CIO_CRE_RPC1_INDEX
	.comm	_NV_CIO_CRE_LSR_INDEX,4,2       ; @NV_CIO_CRE_LSR_INDEX
	.comm	_NV_CIO_CRE_PIXEL_INDEX,4,2     ; @NV_CIO_CRE_PIXEL_INDEX
	.comm	_NV_CIO_CRE_LCD__INDEX,4,2      ; @NV_CIO_CRE_LCD__INDEX
	.comm	_NV_CIO_CRE_HEB__INDEX,4,2      ; @NV_CIO_CRE_HEB__INDEX
	.comm	_NV_CIO_CRE_ENH_INDEX,4,2       ; @NV_CIO_CRE_ENH_INDEX
	.comm	_NV_CIO_CRE_FF_INDEX,4,2        ; @NV_CIO_CRE_FF_INDEX
	.comm	_NV_CIO_CRE_FFLWM__INDEX,4,2    ; @NV_CIO_CRE_FFLWM__INDEX
	.comm	_NV_20,8,3                      ; @NV_20
	.comm	_NV_CIO_CRE_47,4,2              ; @NV_CIO_CRE_47
	.comm	_NV_CIO_CRE_49,4,2              ; @NV_CIO_CRE_49
	.comm	_NV_CIO_CRE_HCUR_ADDR0_INDEX,4,2 ; @NV_CIO_CRE_HCUR_ADDR0_INDEX
	.comm	_NV_CIO_CRE_HCUR_ADDR1_INDEX,4,2 ; @NV_CIO_CRE_HCUR_ADDR1_INDEX
	.comm	_NV_CIO_CRE_HCUR_ADDR2_INDEX,4,2 ; @NV_CIO_CRE_HCUR_ADDR2_INDEX
	.comm	_NV_CIO_CRE_ILACE__INDEX,4,2    ; @NV_CIO_CRE_ILACE__INDEX
	.comm	_NV_CIO_CRE_SCRATCH3__INDEX,4,2 ; @NV_CIO_CRE_SCRATCH3__INDEX
	.comm	_NV_CIO_CRE_SCRATCH4__INDEX,4,2 ; @NV_CIO_CRE_SCRATCH4__INDEX
	.comm	_NV_CIO_CRE_EBR_INDEX,4,2       ; @NV_CIO_CRE_EBR_INDEX
	.comm	_NV_CIO_CRE_CSB,4,2             ; @NV_CIO_CRE_CSB
	.comm	_NV_CIO_CRE_4B,4,2              ; @NV_CIO_CRE_4B
	.comm	_NV_CIO_CRE_TVOUT_LATENCY,4,2   ; @NV_CIO_CRE_TVOUT_LATENCY
	.comm	_NV_PRMCIO_INP0__COLOR,4,2      ; @NV_PRMCIO_INP0__COLOR
	.comm	_NV_CIO_CRE_42,4,2              ; @NV_CIO_CRE_42
	.comm	_NV_CIO_CRE_53,4,2              ; @NV_CIO_CRE_53
	.comm	_NV_CIO_CRE_54,4,2              ; @NV_CIO_CRE_54
	.comm	_NV_CIO_CRE_59,4,2              ; @NV_CIO_CRE_59
	.comm	_NV_CIO_CRE_5B,4,2              ; @NV_CIO_CRE_5B
	.comm	_NV_CIO_CRE_85,4,2              ; @NV_CIO_CRE_85
	.comm	_NV_CIO_CRE_86,4,2              ; @NV_CIO_CRE_86
	.comm	_NV_PCRTC_START,4,2             ; @NV_PCRTC_START
	.no_dead_strip	_nv_load_state_ext
.subsections_via_symbols
