	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_wait_pll_lock
_radeon_wait_pll_lock:                  ## @radeon_wait_pll_lock
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %r14d
	movl	%edx, %ebx
	movl	%esi, %r15d
	movq	_RADEON_TEST_DEBUG_MUX@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	%r12d, %edi
	callq	_RREG32
                                        ## kill: def $eax killed $eax def $rax
	andl	$-40705, %eax                   ## imm = 0xFFFF60FF
	leal	256(%rax), %esi
	movl	%r12d, %edi
	callq	_WREG32
	movq	_RADEON_PLL_TEST_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_RREG32_PLL
	movl	(%r12), %edi
	movq	_RADEON_PLL_MASK_READ_B@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	andl	%eax, %esi
	callq	_WREG32_PLL
	movq	_RADEON_CLOCK_CNTL_INDEX@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	(%r12), %esi
	callq	_WREG8
	movl	%r15d, -48(%rbp)                ## 4-byte Spill
	testl	%r15d, %r15d
	je	LBB0_7
## %bb.1:
	xorl	%r13d, %r13d
	movq	_RADEON_CLOCK_CNTL_DATA@GOTPCREL(%rip), %r12
	jmp	LBB0_2
	.p2align	4, 0x90
LBB0_6:                                 ##   in Loop: Header=BB0_2 Depth=1
	incl	%r13d
	cmpl	-48(%rbp), %r13d                ## 4-byte Folded Reload
	je	LBB0_7
LBB0_2:                                 ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_4 Depth 2
	movq	(%r12), %rdi
	addq	$3, %rdi
	xorl	%esi, %esi
	callq	_WREG8
	testl	%ebx, %ebx
	je	LBB0_6
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movl	$1, %r15d
	.p2align	4, 0x90
LBB0_4:                                 ##   Parent Loop BB0_2 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movq	(%r12), %rdi
	addq	$3, %rdi
	callq	_RREG8
	cmpl	%r14d, %eax
	jae	LBB0_6
## %bb.5:                               ##   in Loop: Header=BB0_4 Depth=2
	leal	1(%r15), %eax
	cmpl	%ebx, %r15d
	movl	%eax, %r15d
	jb	LBB0_4
	jmp	LBB0_6
LBB0_7:
	movq	_RADEON_PLL_TEST_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32_PLL
	movq	_RADEON_TEST_DEBUG_MUX@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%ebx, %edi
	callq	_RREG32
	andl	$-7937, %eax                    ## imm = 0xE0FF
	movl	%ebx, %edi
	movl	%eax, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_TEST_DEBUG_MUX,4,2      ## @RADEON_TEST_DEBUG_MUX
	.comm	_RADEON_PLL_TEST_CNTL,4,2       ## @RADEON_PLL_TEST_CNTL
	.comm	_RADEON_PLL_MASK_READ_B,4,2     ## @RADEON_PLL_MASK_READ_B
	.comm	_RADEON_CLOCK_CNTL_INDEX,8,3    ## @RADEON_CLOCK_CNTL_INDEX
	.comm	_RADEON_CLOCK_CNTL_DATA,8,3     ## @RADEON_CLOCK_CNTL_DATA
	.no_dead_strip	_radeon_wait_pll_lock
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_wait_pll_lock
_radeon_wait_pll_lock:                  ; @radeon_wait_pll_lock
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x3
	mov	x20, x2
	mov	x21, x1
Lloh0:
	adrp	x23, _RADEON_TEST_DEBUG_MUX@GOTPAGE
Lloh1:
	ldr	x23, [x23, _RADEON_TEST_DEBUG_MUX@GOTPAGEOFF]
	ldr	w22, [x23]
	mov	x0, x22
	bl	_RREG32
	mov	w8, #-40705
	and	w8, w0, w8
	orr	w1, w8, #0x100
	mov	x0, x22
	bl	_WREG32
Lloh2:
	adrp	x24, _RADEON_PLL_TEST_CNTL@GOTPAGE
Lloh3:
	ldr	x24, [x24, _RADEON_PLL_TEST_CNTL@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_RREG32_PLL
	mov	x22, x0
	ldr	w0, [x24]
Lloh4:
	adrp	x8, _RADEON_PLL_MASK_READ_B@GOTPAGE
Lloh5:
	ldr	x8, [x8, _RADEON_PLL_MASK_READ_B@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
	bic	w1, w22, w8
	bl	_WREG32_PLL
Lloh7:
	adrp	x8, _RADEON_CLOCK_CNTL_INDEX@GOTPAGE
Lloh8:
	ldr	x8, [x8, _RADEON_CLOCK_CNTL_INDEX@GOTPAGEOFF]
Lloh9:
	ldr	x0, [x8]
	ldr	w1, [x24]
	bl	_WREG8
	cbz	w21, LBB0_6
; %bb.1:
	mov	w25, #0
Lloh10:
	adrp	x26, _RADEON_CLOCK_CNTL_DATA@GOTPAGE
Lloh11:
	ldr	x26, [x26, _RADEON_CLOCK_CNTL_DATA@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:                                 ;   in Loop: Header=BB0_3 Depth=1
	add	w25, w25, #1
	cmp	w25, w21
	b.eq	LBB0_6
LBB0_3:                                 ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
	ldr	x8, [x26]
	add	x0, x8, #3
	mov	w1, #0
	bl	_WREG8
	cbz	w20, LBB0_2
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	mov	w27, #1
LBB0_5:                                 ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ldr	x8, [x26]
	add	x0, x8, #3
	bl	_RREG8
	cmp	w0, w19
	ccmp	w27, w20, #2, lo
	add	w27, w27, #1
	b.lo	LBB0_5
	b	LBB0_2
LBB0_6:
	ldr	w0, [x24]
	mov	x1, x22
	bl	_WREG32_PLL
	ldr	w19, [x23]
	mov	x0, x19
	bl	_RREG32
	and	w1, w0, #0xffffe0ff
	mov	x0, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_WREG32
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh10, Lloh11
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_TEST_DEBUG_MUX,4,2      ; @RADEON_TEST_DEBUG_MUX
	.comm	_RADEON_PLL_TEST_CNTL,4,2       ; @RADEON_PLL_TEST_CNTL
	.comm	_RADEON_PLL_MASK_READ_B,4,2     ; @RADEON_PLL_MASK_READ_B
	.comm	_RADEON_CLOCK_CNTL_INDEX,8,3    ; @RADEON_CLOCK_CNTL_INDEX
	.comm	_RADEON_CLOCK_CNTL_DATA,8,3     ; @RADEON_CLOCK_CNTL_DATA
	.no_dead_strip	_radeon_wait_pll_lock
.subsections_via_symbols
