	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r300_mc_init                   ## -- Begin function r300_mc_init
	.p2align	4, 0x90
_r300_mc_init:                          ## @r300_mc_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	movl	$1, 8(%rdi)
	movq	_RADEON_MEM_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_R300_MEM_NUM_CHANNELS_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movl	$128, %ecx
	cmpl	$2, %eax
	ja	LBB0_2
## %bb.1:
	cltq
	leaq	l_switch.table.r300_mc_init(%rip), %rcx
	movl	(%rcx,%rax,4), %ecx
LBB0_2:
	leaq	8(%rbx), %r14
	movl	%ecx, 12(%rbx)
	movq	%rbx, %rdi
	callq	_r100_vram_init_sizes
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rbx)
	je	LBB0_3
## %bb.4:
	movq	_RADEON_NB_TOM@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %edx
	shll	$16, %edx
	jmp	LBB0_5
LBB0_3:
	movl	16(%rbx), %edx
LBB0_5:
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	_radeon_vram_location
	movq	$0, 24(%rbx)
	movq	_RADEON_IS_AGP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rbx)
	jne	LBB0_7
## %bb.6:
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	_radeon_gtt_location
LBB0_7:
	movq	%rbx, %rdi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_radeon_update_bandwidth_info   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_MEM_CNTL,4,2            ## @RADEON_MEM_CNTL
	.comm	_R300_MEM_NUM_CHANNELS_MASK,4,2 ## @R300_MEM_NUM_CHANNELS_MASK
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
	.comm	_RADEON_NB_TOM,4,2              ## @RADEON_NB_TOM
	.comm	_RADEON_IS_AGP,4,2              ## @RADEON_IS_AGP
	.section	__TEXT,__const
	.p2align	2                               ## @switch.table.r300_mc_init
l_switch.table.r300_mc_init:
	.long	64                              ## 0x40
	.long	128                             ## 0x80
	.long	256                             ## 0x100

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r300_mc_init                   ; -- Begin function r300_mc_init
	.p2align	2
_r300_mc_init:                          ; @r300_mc_init
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	mov	w8, #1
	mov	x20, x0
	str	w8, [x20, #8]!
Lloh0:
	adrp	x8, _RADEON_MEM_CNTL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_MEM_CNTL@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_RREG32
Lloh3:
	adrp	x8, _R300_MEM_NUM_CHANNELS_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _R300_MEM_NUM_CHANNELS_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	and	w8, w8, w0
	cmp	w8, #2
	b.hi	LBB0_2
; %bb.1:
Lloh6:
	adrp	x9, l_switch.table.r300_mc_init@PAGE
Lloh7:
	add	x9, x9, l_switch.table.r300_mc_init@PAGEOFF
	ldr	w8, [x9, w8, sxtw #2]
	b	LBB0_3
LBB0_2:
	mov	w8, #128
LBB0_3:
	str	w8, [x19, #12]
	mov	x0, x19
	bl	_r100_vram_init_sizes
	ldr	w8, [x19]
Lloh8:
	adrp	x9, _RADEON_IS_IGP@GOTPAGE
Lloh9:
	ldr	x9, [x9, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_5
; %bb.4:
Lloh11:
	adrp	x8, _RADEON_NB_TOM@GOTPAGE
Lloh12:
	ldr	x8, [x8, _RADEON_NB_TOM@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
	bl	_RREG32
	lsl	w2, w0, #16
	b	LBB0_6
LBB0_5:
	ldr	w2, [x19, #16]
LBB0_6:
	mov	x0, x19
	mov	x1, x20
	bl	_radeon_vram_location
	str	xzr, [x19, #24]
	ldr	w8, [x19]
Lloh14:
	adrp	x9, _RADEON_IS_AGP@GOTPAGE
Lloh15:
	ldr	x9, [x9, _RADEON_IS_AGP@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_8
; %bb.7:
	mov	x0, x19
	mov	x1, x20
	bl	_radeon_gtt_location
LBB0_8:
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_radeon_update_bandwidth_info
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_MEM_CNTL,4,2            ; @RADEON_MEM_CNTL
	.comm	_R300_MEM_NUM_CHANNELS_MASK,4,2 ; @R300_MEM_NUM_CHANNELS_MASK
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
	.comm	_RADEON_NB_TOM,4,2              ; @RADEON_NB_TOM
	.comm	_RADEON_IS_AGP,4,2              ; @RADEON_IS_AGP
	.section	__TEXT,__const
	.p2align	2                               ; @switch.table.r300_mc_init
l_switch.table.r300_mc_init:
	.long	64                              ; 0x40
	.long	128                             ; 0x80
	.long	256                             ; 0x100

.subsections_via_symbols
