	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function intel_crtc_clock_get
_intel_crtc_clock_get:                  ## @intel_crtc_clock_get
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	subq	$32, %rsp
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	%rsi, %rdi
	callq	_to_intel_crtc
	movl	(%rax), %r12d
	movl	%r12d, %edi
	callq	_DPLL
	movl	%eax, %edi
	callq	_I915_READ
	movl	%eax, %r15d
	movq	_DISPLAY_RATE_SELECT_FPA1@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_1
## %bb.2:
	movl	%r12d, %edi
	callq	_FP1
	jmp	LBB0_3
LBB0_1:
	movl	%r12d, %edi
	callq	_FP0
LBB0_3:
	movl	%eax, %edi
	callq	_I915_READ
	movl	%eax, %ebx
	movq	_FP_M1_DIV_MASK@GOTPCREL(%rip), %rax
	movl	%ebx, %edx
	andl	(%rax), %edx
	movq	_FP_M1_DIV_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarl	%cl, %edx
	movl	%edx, -56(%rbp)
	movq	%r14, %rdi
	callq	_IS_PINEVIEW
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	movq	_FP_N_PINEVIEW_DIV_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	andl	%ebx, %edi
	movq	_FP_N_DIV_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarl	%cl, %edi
	callq	_ffs
	decl	%eax
	movq	_FP_M2_PINEVIEW_DIV_MASK@GOTPCREL(%rip), %rcx
	jmp	LBB0_6
LBB0_5:
	movq	_FP_N_DIV_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%ebx, %eax
	movq	_FP_N_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	movq	_FP_M2_DIV_MASK@GOTPCREL(%rip), %rcx
LBB0_6:
	movl	(%rcx), %edx
	andl	%ebx, %edx
	movq	_FP_M2_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %edx
	movl	%eax, -52(%rbp)
	movl	%edx, -48(%rbp)
	movq	%r14, %rdi
	callq	_IS_GEN2
	testl	%eax, %eax
	je	LBB0_7
## %bb.13:
	cmpl	$1, %r12d
	jne	LBB0_16
## %bb.14:
	movq	_LVDS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	_LVDS_PORT_EN@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_16
## %bb.15:
	movq	_DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	andl	%r15d, %edi
	movq	_DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarl	%cl, %edi
	callq	_ffs
	movl	%eax, -44(%rbp)
	movq	_PLL_REF_INPUT_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %r15d
	movl	$14, -40(%rbp)
	movq	_PLLB_REF_INPUT_SPREADSPECTRUMIN@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r15d
	movl	$66000, %eax                    ## imm = 0x101D0
	movl	$48000, %esi                    ## imm = 0xBB80
	cmovel	%eax, %esi
	jmp	LBB0_19
LBB0_16:
	movq	_PLL_P1_DIVIDE_BY_TWO@GOTPCREL(%rip), %rcx
	movl	$2, %eax
	testl	%r15d, (%rcx)
	jne	LBB0_18
## %bb.17:
	movq	_DPLL_FPA01_P1_POST_DIV_MASK_I830@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r15d, %eax
	movq	_DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	addl	$2, %eax
LBB0_18:
	movl	%eax, -44(%rbp)
	movq	_PLL_P2_DIVIDE_BY_4@GOTPCREL(%rip), %rax
	xorl	%ecx, %ecx
	andl	(%rax), %r15d
	setne	%cl
	leal	(%rcx,%rcx), %eax
	addl	$2, %eax
	movl	%eax, -40(%rbp)
	movl	$48000, %esi                    ## imm = 0xBB80
	jmp	LBB0_19
LBB0_7:
	movq	%r14, %rdi
	callq	_IS_PINEVIEW
	testq	%rax, %rax
	movq	_DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW@GOTPCREL(%rip), %rax
	cmoveq	_DPLL_FPA01_P1_POST_DIV_MASK@GOTPCREL(%rip), %rax
	movq	_DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW@GOTPCREL(%rip), %rcx
	cmoveq	_DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movl	(%rax), %edi
	andl	%r15d, %edi
	movb	(%rcx), %cl
	sarl	%cl, %edi
	callq	_ffs
	movl	%eax, -44(%rbp)
	movq	_DPLL_MODE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	andl	%r15d, %esi
	cmpl	$128, %esi
	je	LBB0_11
## %bb.8:
	cmpl	$129, %esi
	jne	LBB0_10
## %bb.9:
	movq	_DPLL_DAC_SERIAL_P2_CLOCK_DIV_5@GOTPCREL(%rip), %rax
	xorl	%ecx, %ecx
	testl	%r15d, (%rax)
	sete	%cl
	leal	(%rcx,%rcx,4), %eax
	addl	$5, %eax
	jmp	LBB0_12
LBB0_11:
	movq	_DPLLB_LVDS_P2_CLOCK_DIV_7@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	movl	$14, %ecx
	movl	$7, %eax
	cmovel	%ecx, %eax
LBB0_12:
	movl	%eax, -40(%rbp)
	movl	$96000, %esi                    ## imm = 0x17700
LBB0_19:
	leaq	-56(%rbp), %rdx
	movq	%r14, %rdi
	callq	_intel_clock
	movl	-36(%rbp), %eax
LBB0_20:
	addq	$32, %rsp
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_10:
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	xorl	%eax, %eax
	jmp	LBB0_20
	.cfi_endproc
                                        ## -- End function
	.comm	_DISPLAY_RATE_SELECT_FPA1,4,2   ## @DISPLAY_RATE_SELECT_FPA1
	.comm	_FP_M1_DIV_MASK,4,2             ## @FP_M1_DIV_MASK
	.comm	_FP_M1_DIV_SHIFT,4,2            ## @FP_M1_DIV_SHIFT
	.comm	_FP_N_PINEVIEW_DIV_MASK,4,2     ## @FP_N_PINEVIEW_DIV_MASK
	.comm	_FP_N_DIV_SHIFT,4,2             ## @FP_N_DIV_SHIFT
	.comm	_FP_M2_PINEVIEW_DIV_MASK,4,2    ## @FP_M2_PINEVIEW_DIV_MASK
	.comm	_FP_M2_DIV_SHIFT,4,2            ## @FP_M2_DIV_SHIFT
	.comm	_FP_N_DIV_MASK,4,2              ## @FP_N_DIV_MASK
	.comm	_FP_M2_DIV_MASK,4,2             ## @FP_M2_DIV_MASK
	.comm	_DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW,4,2 ## @DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
	.comm	_DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW,4,2 ## @DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
	.comm	_DPLL_FPA01_P1_POST_DIV_MASK,4,2 ## @DPLL_FPA01_P1_POST_DIV_MASK
	.comm	_DPLL_FPA01_P1_POST_DIV_SHIFT,4,2 ## @DPLL_FPA01_P1_POST_DIV_SHIFT
	.comm	_DPLL_MODE_MASK,4,2             ## @DPLL_MODE_MASK
	.comm	_DPLL_DAC_SERIAL_P2_CLOCK_DIV_5,4,2 ## @DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
	.comm	_DPLLB_LVDS_P2_CLOCK_DIV_7,4,2  ## @DPLLB_LVDS_P2_CLOCK_DIV_7
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Unknown DPLL mode %08x in programmed mode\n"

	.comm	_LVDS,4,2                       ## @LVDS
	.comm	_LVDS_PORT_EN,4,2               ## @LVDS_PORT_EN
	.comm	_DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS,4,2 ## @DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
	.comm	_PLL_REF_INPUT_MASK,4,2         ## @PLL_REF_INPUT_MASK
	.comm	_PLLB_REF_INPUT_SPREADSPECTRUMIN,4,2 ## @PLLB_REF_INPUT_SPREADSPECTRUMIN
	.comm	_PLL_P1_DIVIDE_BY_TWO,4,2       ## @PLL_P1_DIVIDE_BY_TWO
	.comm	_DPLL_FPA01_P1_POST_DIV_MASK_I830,4,2 ## @DPLL_FPA01_P1_POST_DIV_MASK_I830
	.comm	_PLL_P2_DIVIDE_BY_4,4,2         ## @PLL_P2_DIVIDE_BY_4
	.no_dead_strip	_intel_crtc_clock_get
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function intel_crtc_clock_get
_intel_crtc_clock_get:                  ; @intel_crtc_clock_get
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	mov	x0, x1
	bl	_to_intel_crtc
	ldr	w21, [x0]
	mov	x0, x21
	bl	_DPLL
	bl	_I915_READ
	mov	x20, x0
Lloh0:
	adrp	x8, _DISPLAY_RATE_SELECT_FPA1@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DISPLAY_RATE_SELECT_FPA1@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_2
; %bb.1:
	mov	x0, x21
	bl	_FP1
	b	LBB0_3
LBB0_2:
	mov	x0, x21
	bl	_FP0
LBB0_3:
	bl	_I915_READ
	mov	x22, x0
Lloh3:
	adrp	x8, _FP_M1_DIV_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _FP_M1_DIV_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh6:
	adrp	x9, _FP_M1_DIV_SHIFT@GOTPAGE
Lloh7:
	ldr	x9, [x9, _FP_M1_DIV_SHIFT@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	asr	w8, w8, w9
	str	w8, [sp, #8]
	mov	x0, x19
	bl	_IS_PINEVIEW
	cbz	x0, LBB0_5
; %bb.4:
Lloh9:
	adrp	x8, _FP_N_PINEVIEW_DIV_MASK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _FP_N_PINEVIEW_DIV_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	and	w8, w8, w22
Lloh12:
	adrp	x9, _FP_N_DIV_SHIFT@GOTPAGE
Lloh13:
	ldr	x9, [x9, _FP_N_DIV_SHIFT@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	asr	w0, w8, w9
	bl	_ffs
	sub	w8, w0, #1
Lloh15:
	adrp	x9, _FP_M2_PINEVIEW_DIV_MASK@GOTPAGE
Lloh16:
	ldr	x9, [x9, _FP_M2_PINEVIEW_DIV_MASK@GOTPAGEOFF]
	b	LBB0_6
LBB0_5:
Lloh17:
	adrp	x8, _FP_N_DIV_MASK@GOTPAGE
Lloh18:
	ldr	x8, [x8, _FP_N_DIV_MASK@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
	and	w8, w8, w22
Lloh20:
	adrp	x9, _FP_N_DIV_SHIFT@GOTPAGE
Lloh21:
	ldr	x9, [x9, _FP_N_DIV_SHIFT@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	asr	w8, w8, w9
Lloh23:
	adrp	x9, _FP_M2_DIV_MASK@GOTPAGE
Lloh24:
	ldr	x9, [x9, _FP_M2_DIV_MASK@GOTPAGEOFF]
LBB0_6:
	ldr	w9, [x9]
	and	w9, w9, w22
Lloh25:
	adrp	x10, _FP_M2_DIV_SHIFT@GOTPAGE
Lloh26:
	ldr	x10, [x10, _FP_M2_DIV_SHIFT@GOTPAGEOFF]
Lloh27:
	ldr	w10, [x10]
	asr	w9, w9, w10
	stp	w8, w9, [sp, #12]
	mov	x0, x19
	bl	_IS_GEN2
	cbz	w0, LBB0_13
; %bb.7:
	cmp	w21, #1
	b.ne	LBB0_10
; %bb.8:
Lloh28:
	adrp	x8, _LVDS@GOTPAGE
Lloh29:
	ldr	x8, [x8, _LVDS@GOTPAGEOFF]
Lloh30:
	ldr	w0, [x8]
	bl	_I915_READ
Lloh31:
	adrp	x8, _LVDS_PORT_EN@GOTPAGE
Lloh32:
	ldr	x8, [x8, _LVDS_PORT_EN@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_10
; %bb.9:
Lloh34:
	adrp	x8, _DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS@GOTPAGE
Lloh35:
	ldr	x8, [x8, _DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS@GOTPAGEOFF]
Lloh36:
	ldr	w8, [x8]
	and	w8, w8, w20
Lloh37:
	adrp	x9, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGE
Lloh38:
	ldr	x9, [x9, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGEOFF]
Lloh39:
	ldr	w9, [x9]
	asr	w0, w8, w9
	bl	_ffs
	mov	w8, #14
	stp	w0, w8, [sp, #20]
Lloh40:
	adrp	x8, _PLL_REF_INPUT_MASK@GOTPAGE
Lloh41:
	ldr	x8, [x8, _PLL_REF_INPUT_MASK@GOTPAGEOFF]
Lloh42:
	ldr	w8, [x8]
Lloh43:
	adrp	x9, _PLLB_REF_INPUT_SPREADSPECTRUMIN@GOTPAGE
Lloh44:
	ldr	x9, [x9, _PLLB_REF_INPUT_SPREADSPECTRUMIN@GOTPAGEOFF]
	and	w8, w8, w20
Lloh45:
	ldr	w9, [x9]
	mov	w10, #48000
	mov	w11, #464
	movk	w11, #1, lsl #16
	cmp	w8, w9
	csel	w1, w11, w10, eq
	b	LBB0_18
LBB0_10:
Lloh46:
	adrp	x8, _PLL_P1_DIVIDE_BY_TWO@GOTPAGE
Lloh47:
	ldr	x8, [x8, _PLL_P1_DIVIDE_BY_TWO@GOTPAGEOFF]
Lloh48:
	ldr	w10, [x8]
	mov	w8, #2
	mov	w9, #2
	tst	w10, w20
	b.ne	LBB0_12
; %bb.11:
Lloh49:
	adrp	x9, _DPLL_FPA01_P1_POST_DIV_MASK_I830@GOTPAGE
Lloh50:
	ldr	x9, [x9, _DPLL_FPA01_P1_POST_DIV_MASK_I830@GOTPAGEOFF]
Lloh51:
	ldr	w9, [x9]
	and	w9, w9, w20
Lloh52:
	adrp	x10, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGE
Lloh53:
	ldr	x10, [x10, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGEOFF]
Lloh54:
	ldr	w10, [x10]
	asr	w9, w9, w10
	add	w9, w9, #2
LBB0_12:
Lloh55:
	adrp	x10, _PLL_P2_DIVIDE_BY_4@GOTPAGE
Lloh56:
	ldr	x10, [x10, _PLL_P2_DIVIDE_BY_4@GOTPAGEOFF]
Lloh57:
	ldr	w10, [x10]
	tst	w10, w20
	mov	w10, #4
	csel	w8, w8, w10, eq
	stp	w9, w8, [sp, #20]
	mov	w1, #48000
	b	LBB0_18
LBB0_13:
	mov	x0, x19
	bl	_IS_PINEVIEW
Lloh58:
	adrp	x8, _DPLL_FPA01_P1_POST_DIV_MASK@GOTPAGE
Lloh59:
	ldr	x8, [x8, _DPLL_FPA01_P1_POST_DIV_MASK@GOTPAGEOFF]
Lloh60:
	adrp	x9, _DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW@GOTPAGE
Lloh61:
	ldr	x9, [x9, _DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW@GOTPAGEOFF]
	cmp	x0, #0
	csel	x8, x8, x9, eq
	ldr	w8, [x8]
Lloh62:
	adrp	x9, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGE
Lloh63:
	ldr	x9, [x9, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGEOFF]
	and	w8, w8, w20
Lloh64:
	adrp	x10, _DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW@GOTPAGE
Lloh65:
	ldr	x10, [x10, _DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW@GOTPAGEOFF]
	csel	x9, x9, x10, eq
	ldr	w9, [x9]
	asr	w0, w8, w9
	bl	_ffs
	str	w0, [sp, #20]
Lloh66:
	adrp	x8, _DPLL_MODE_MASK@GOTPAGE
Lloh67:
	ldr	x8, [x8, _DPLL_MODE_MASK@GOTPAGEOFF]
Lloh68:
	ldr	w8, [x8]
	and	w1, w8, w20
	cmp	w1, #128
	b.eq	LBB0_16
; %bb.14:
	cmp	w1, #129
	b.ne	LBB0_20
; %bb.15:
Lloh69:
	adrp	x8, _DPLL_DAC_SERIAL_P2_CLOCK_DIV_5@GOTPAGE
Lloh70:
	ldr	x8, [x8, _DPLL_DAC_SERIAL_P2_CLOCK_DIV_5@GOTPAGEOFF]
Lloh71:
	ldr	w8, [x8]
	tst	w8, w20
	mov	w8, #5
	mov	w9, #10
	b	LBB0_17
LBB0_16:
Lloh72:
	adrp	x8, _DPLLB_LVDS_P2_CLOCK_DIV_7@GOTPAGE
Lloh73:
	ldr	x8, [x8, _DPLLB_LVDS_P2_CLOCK_DIV_7@GOTPAGEOFF]
Lloh74:
	ldr	w8, [x8]
	tst	w8, w20
	mov	w8, #7
	mov	w9, #14
LBB0_17:
	csel	w8, w9, w8, eq
	str	w8, [sp, #24]
	mov	w1, #30464
	movk	w1, #1, lsl #16
LBB0_18:
	add	x2, sp, #8
	mov	x0, x19
	bl	_intel_clock
	ldr	w0, [sp, #28]
LBB0_19:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
LBB0_20:
Lloh75:
	adrp	x0, l_.str@PAGE
Lloh76:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_KMS
	mov	w0, #0
	b	LBB0_19
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGot	Lloh64, Lloh65
	.loh AdrpLdrGot	Lloh62, Lloh63
	.loh AdrpLdrGot	Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpAdd	Lloh75, Lloh76
	.cfi_endproc
                                        ; -- End function
	.comm	_DISPLAY_RATE_SELECT_FPA1,4,2   ; @DISPLAY_RATE_SELECT_FPA1
	.comm	_FP_M1_DIV_MASK,4,2             ; @FP_M1_DIV_MASK
	.comm	_FP_M1_DIV_SHIFT,4,2            ; @FP_M1_DIV_SHIFT
	.comm	_FP_N_PINEVIEW_DIV_MASK,4,2     ; @FP_N_PINEVIEW_DIV_MASK
	.comm	_FP_N_DIV_SHIFT,4,2             ; @FP_N_DIV_SHIFT
	.comm	_FP_M2_PINEVIEW_DIV_MASK,4,2    ; @FP_M2_PINEVIEW_DIV_MASK
	.comm	_FP_M2_DIV_SHIFT,4,2            ; @FP_M2_DIV_SHIFT
	.comm	_FP_N_DIV_MASK,4,2              ; @FP_N_DIV_MASK
	.comm	_FP_M2_DIV_MASK,4,2             ; @FP_M2_DIV_MASK
	.comm	_DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW,4,2 ; @DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
	.comm	_DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW,4,2 ; @DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
	.comm	_DPLL_FPA01_P1_POST_DIV_MASK,4,2 ; @DPLL_FPA01_P1_POST_DIV_MASK
	.comm	_DPLL_FPA01_P1_POST_DIV_SHIFT,4,2 ; @DPLL_FPA01_P1_POST_DIV_SHIFT
	.comm	_DPLL_MODE_MASK,4,2             ; @DPLL_MODE_MASK
	.comm	_DPLL_DAC_SERIAL_P2_CLOCK_DIV_5,4,2 ; @DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
	.comm	_DPLLB_LVDS_P2_CLOCK_DIV_7,4,2  ; @DPLLB_LVDS_P2_CLOCK_DIV_7
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Unknown DPLL mode %08x in programmed mode\n"

	.comm	_LVDS,4,2                       ; @LVDS
	.comm	_LVDS_PORT_EN,4,2               ; @LVDS_PORT_EN
	.comm	_DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS,4,2 ; @DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
	.comm	_PLL_REF_INPUT_MASK,4,2         ; @PLL_REF_INPUT_MASK
	.comm	_PLLB_REF_INPUT_SPREADSPECTRUMIN,4,2 ; @PLLB_REF_INPUT_SPREADSPECTRUMIN
	.comm	_PLL_P1_DIVIDE_BY_TWO,4,2       ; @PLL_P1_DIVIDE_BY_TWO
	.comm	_DPLL_FPA01_P1_POST_DIV_MASK_I830,4,2 ; @DPLL_FPA01_P1_POST_DIV_MASK_I830
	.comm	_PLL_P2_DIVIDE_BY_4,4,2         ; @PLL_P2_DIVIDE_BY_4
	.no_dead_strip	_intel_crtc_clock_get
.subsections_via_symbols
