	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function nve0_fifo_ctor
_nve0_fifo_ctor:                        ## @nve0_fifo_ctor
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%r9, %r15
	movq	%rdi, %r14
	leaq	-32(%rbp), %r9
	xorl	%ecx, %ecx
	movl	$4095, %r8d                     ## imm = 0xFFF
	callq	_nouveau_fifo_create
	movl	%eax, %ebx
	movq	-32(%rbp), %rdi
	callq	_nv_object
	movq	%rax, (%r15)
	testl	%ebx, %ebx
	jne	LBB0_4
## %bb.1:
	movq	_NVOBJ_FLAG_ZERO_ALLOC@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	movq	-32(%rbp), %r9
	addq	$12, %r9
	movq	%r14, %rdi
	xorl	%esi, %esi
	movl	$2097152, %edx                  ## imm = 0x200000
	movl	$4096, %ecx                     ## imm = 0x1000
	callq	_nouveau_gpuobj_new
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_4
## %bb.2:
	movq	-32(%rbp), %rdx
	movl	12(%rdx), %edi
	addq	$8, %rdx
	movq	_NV_MEM_ACCESS_RW@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_nouveau_gpuobj_map
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_4
## %bb.3:
	movq	_nve0_fifo_uevent_enable@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	-32(%rbp), %rcx
	movq	(%rcx), %rdx
	movl	%eax, 12(%rdx)
	movq	_nve0_fifo_uevent_disable@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 8(%rdx)
	movq	%rcx, (%rdx)
	movq	-32(%rbp), %rdi
	callq	_nv_subdev
	movl	$256, (%rax)                    ## imm = 0x100
	movq	_nve0_fifo_intr@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	-32(%rbp), %rdi
	callq	_nv_subdev
	movl	%ebx, 4(%rax)
	movq	-32(%rbp), %rdi
	callq	_nv_engine
	movq	_nve0_fifo_cclass@GOTPCREL(%rip), %rcx
	movq	%rcx, 8(%rax)
	movq	_nve0_fifo_sclass@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	-32(%rbp), %rdi
	callq	_nv_engine
	movl	%ebx, (%rax)
	xorl	%ebx, %ebx
LBB0_4:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_NVOBJ_FLAG_ZERO_ALLOC,4,2      ## @NVOBJ_FLAG_ZERO_ALLOC
	.comm	_NV_MEM_ACCESS_RW,4,2           ## @NV_MEM_ACCESS_RW
	.comm	_nve0_fifo_uevent_enable,4,2    ## @nve0_fifo_uevent_enable
	.comm	_nve0_fifo_uevent_disable,4,2   ## @nve0_fifo_uevent_disable
	.comm	_nve0_fifo_intr,4,2             ## @nve0_fifo_intr
	.comm	_nve0_fifo_cclass,4,2           ## @nve0_fifo_cclass
	.comm	_nve0_fifo_sclass,4,2           ## @nve0_fifo_sclass
	.no_dead_strip	_nve0_fifo_ctor
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function nve0_fifo_ctor
_nve0_fifo_ctor:                        ; @nve0_fifo_ctor
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x21, x5
	mov	x19, x0
	add	x5, sp, #8
	mov	w3, #0
	mov	w4, #4095
	bl	_nouveau_fifo_create
	mov	x20, x0
	ldr	x0, [sp, #8]
	bl	_nv_object
	str	x0, [x21]
	cbnz	w20, LBB0_4
; %bb.1:
Lloh0:
	adrp	x8, _NVOBJ_FLAG_ZERO_ALLOC@GOTPAGE
Lloh1:
	ldr	x8, [x8, _NVOBJ_FLAG_ZERO_ALLOC@GOTPAGEOFF]
Lloh2:
	ldr	w4, [x8]
	ldr	x8, [sp, #8]
	add	x5, x8, #12
	mov	x0, x19
	mov	x1, #0
	mov	w2, #2097152
	mov	w3, #4096
	bl	_nouveau_gpuobj_new
	mov	x20, x0
	cbnz	w0, LBB0_4
; %bb.2:
	ldr	x8, [sp, #8]
	add	x2, x8, #8
	ldr	w0, [x8, #12]
Lloh3:
	adrp	x8, _NV_MEM_ACCESS_RW@GOTPAGE
Lloh4:
	ldr	x8, [x8, _NV_MEM_ACCESS_RW@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	bl	_nouveau_gpuobj_map
	mov	x20, x0
	cbnz	w0, LBB0_4
; %bb.3:
Lloh6:
	adrp	x8, _nve0_fifo_uevent_enable@GOTPAGE
Lloh7:
	ldr	x8, [x8, _nve0_fifo_uevent_enable@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	ldr	x9, [sp, #8]
Lloh9:
	adrp	x10, _nve0_fifo_uevent_disable@GOTPAGE
Lloh10:
	ldr	x10, [x10, _nve0_fifo_uevent_disable@GOTPAGEOFF]
	ldr	x11, [x9]
Lloh11:
	ldr	w10, [x10]
	stp	w10, w8, [x11, #8]
	str	x9, [x11]
	ldr	x0, [sp, #8]
	bl	_nv_subdev
	mov	w8, #256
	str	w8, [x0]
Lloh12:
	adrp	x8, _nve0_fifo_intr@GOTPAGE
Lloh13:
	ldr	x8, [x8, _nve0_fifo_intr@GOTPAGEOFF]
Lloh14:
	ldr	w19, [x8]
	ldr	x0, [sp, #8]
	bl	_nv_subdev
	str	w19, [x0, #4]
	ldr	x0, [sp, #8]
	bl	_nv_engine
Lloh15:
	adrp	x8, _nve0_fifo_cclass@GOTPAGE
Lloh16:
	ldr	x8, [x8, _nve0_fifo_cclass@GOTPAGEOFF]
	str	x8, [x0, #8]
Lloh17:
	adrp	x8, _nve0_fifo_sclass@GOTPAGE
Lloh18:
	ldr	x8, [x8, _nve0_fifo_sclass@GOTPAGEOFF]
Lloh19:
	ldr	w19, [x8]
	ldr	x0, [sp, #8]
	bl	_nv_engine
	str	w19, [x0]
LBB0_4:
	mov	x0, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_NVOBJ_FLAG_ZERO_ALLOC,4,2      ; @NVOBJ_FLAG_ZERO_ALLOC
	.comm	_NV_MEM_ACCESS_RW,4,2           ; @NV_MEM_ACCESS_RW
	.comm	_nve0_fifo_uevent_enable,4,2    ; @nve0_fifo_uevent_enable
	.comm	_nve0_fifo_uevent_disable,4,2   ; @nve0_fifo_uevent_disable
	.comm	_nve0_fifo_intr,4,2             ; @nve0_fifo_intr
	.comm	_nve0_fifo_cclass,4,2           ; @nve0_fifo_cclass
	.comm	_nve0_fifo_sclass,4,2           ; @nve0_fifo_sclass
	.no_dead_strip	_nve0_fifo_ctor
.subsections_via_symbols
