	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function hdlc_mode
_hdlc_mode:                             ## @hdlc_mode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	_HDLC_FLAG_TXC_DPLL@GOTPCREL(%rip), %rcx
	movq	_HDLC_FLAG_RXC_DPLL@GOTPCREL(%rip), %r12
	movl	(%r12), %eax
	addl	(%rcx), %eax
	notl	%eax
	andl	%eax, 16(%rdi)
	movq	_TXDMA@GOTPCREL(%rip), %rax
	movq	_DIR@GOTPCREL(%rip), %r15
	movq	(%r15), %rsi
	addq	(%rax), %rsi
	xorl	%r14d, %r14d
	xorl	%edx, %edx
	callq	_write_reg
	movq	_RXDMA@GOTPCREL(%rip), %rax
	movq	(%r15), %rsi
	addq	(%rax), %rsi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_write_reg
	movq	_HDLC_FLAG_AUTO_CTS@GOTPCREL(%rip), %rax
	movq	_BIT4@GOTPCREL(%rip), %r15
	movb	(%r15), %cl
	movq	_HDLC_FLAG_AUTO_DCD@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rax), %edx
	orb	$-127, %cl
	andl	16(%rbx), %edx
	movzbl	%cl, %eax
	movl	$129, %ecx
	cmovnel	%eax, %ecx
	movq	24(%rbx), %rax
	movq	_HDLC_CRC_16_CCITT@GOTPCREL(%rip), %r8
	movq	_BIT2@GOTPCREL(%rip), %rsi
	movq	_BIT1@GOTPCREL(%rip), %rdi
	movb	(%rdi), %dl
	addb	(%rsi), %dl
	cmpq	(%r8), %rax
	movzbl	%dl, %eax
	cmovnel	%r14d, %eax
	orl	%ecx, %eax
	movq	_MD0@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rsi
	movzbl	%al, %edx
	movq	%rbx, %rdi
	callq	_write_reg
	movq	_MD1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_write_reg
	movl	$-129, %eax
	addl	32(%rbx), %eax
	cmpl	$5, %eax
	ja	LBB0_8
## %bb.1:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_2:
	movq	_BIT5@GOTPCREL(%rip), %rax
	jmp	LBB0_7
LBB0_5:
	movq	_BIT7@GOTPCREL(%rip), %rax
	movq	_BIT6@GOTPCREL(%rip), %rcx
	jmp	LBB0_4
LBB0_3:
	movq	_BIT7@GOTPCREL(%rip), %rax
	movq	_BIT5@GOTPCREL(%rip), %rcx
LBB0_4:
	movb	(%rcx), %r14b
	addb	(%rax), %r14b
	jmp	LBB0_8
LBB0_6:
	movq	_BIT7@GOTPCREL(%rip), %rax
LBB0_7:
	movb	(%rax), %r14b
LBB0_8:
	movl	16(%rbx), %eax
	movq	_HDLC_FLAG_DPLL_DIV16@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_10
## %bb.9:
	movq	_BIT3@GOTPCREL(%rip), %rax
	orb	(%rax), %r14b
	movl	$16, %r13d
	jmp	LBB0_12
LBB0_10:
	movq	_HDLC_FLAG_DPLL_DIV8@GOTPCREL(%rip), %rcx
	movl	$8, %r13d
	testl	%eax, (%rcx)
	jne	LBB0_12
## %bb.11:
	orb	(%r15), %r14b
	movl	$32, %r13d
LBB0_12:
	movq	_MD2@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movzbl	%r14b, %edx
	movq	%rbx, %rdi
	callq	_write_reg
	movl	16(%rbx), %eax
	movq	_HDLC_FLAG_RXC_BRG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%eax, %ecx
	movq	_BIT6@GOTPCREL(%rip), %r15
	movzbl	(%r15), %esi
	cmovnel	%esi, %ecx
	andl	(%r12), %eax
	movq	_BIT5@GOTPCREL(%rip), %r12
	movb	(%r12), %dl
	addb	%sil, %dl
	testl	%eax, %eax
	movzbl	%dl, %edx
	cmovel	%eax, %edx
	orl	%ecx, %edx
	movq	_RXS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movzbl	%dl, %edx
	movq	%rbx, %rdi
	callq	_write_reg
	movl	16(%rbx), %eax
	movq	_HDLC_FLAG_TXC_BRG@GOTPCREL(%rip), %r14
	movl	(%r14), %ecx
	andl	%eax, %ecx
	movzbl	(%r15), %esi
	cmovnel	%esi, %ecx
	movq	_HDLC_FLAG_TXC_DPLL@GOTPCREL(%rip), %rdx
	andl	(%rdx), %eax
	movb	(%r12), %dl
	addb	%sil, %dl
	testl	%eax, %eax
	movzbl	%dl, %edx
	cmovel	%eax, %edx
	orl	%ecx, %edx
	movq	_TXS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movzbl	%dl, %edx
	movq	%rbx, %rdi
	callq	_write_reg
	movq	_HDLC_FLAG_RXC_DPLL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	16(%rbx), %eax
	movl	$1, %esi
	cmovnel	%r13d, %esi
	imull	36(%rbx), %esi
	movq	%rbx, %rdi
	callq	_set_rate
	movq	_BIT0@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movb	(%rbx), %cl
	addb	%cl, %cl
	shll	%cl, %eax
	movl	(%r14), %ecx
	testl	%ecx, 16(%rbx)
	je	LBB0_14
## %bb.13:
	movq	48(%rbx), %rcx
	movq	(%rcx), %rcx
	orl	%eax, (%rcx)
	jmp	LBB0_15
LBB0_14:
	notl	%eax
	movq	48(%rbx), %rcx
	movq	(%rcx), %rcx
	andl	%eax, (%rcx)
LBB0_15:
	movq	_TXDMA@GOTPCREL(%rip), %r15
	movq	_RXDMA@GOTPCREL(%rip), %r12
	movq	%rbx, %rdi
	callq	_write_control_reg
	movq	_RRC@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_rx_active_fifo_level@GOTPCREL(%rip), %rax
	movzbl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_write_reg
	movq	_TRC0@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_tx_active_fifo_level@GOTPCREL(%rip), %rax
	movzbl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_write_reg
	movq	_TRC1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_tx_negate_fifo_level@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	decb	%al
	movzbl	%al, %edx
	movq	%rbx, %rdi
	callq	_write_reg
	movq	_DMR@GOTPCREL(%rip), %r14
	movq	(%r14), %rsi
	addq	(%r15), %rsi
	movq	%rbx, %rdi
	movl	$20, %edx
	callq	_write_reg
	movq	(%r14), %rsi
	addq	(%r12), %rsi
	movq	%rbx, %rdi
	movl	$20, %edx
	callq	_write_reg
	movq	_CPB@GOTPCREL(%rip), %r14
	movq	(%r14), %rsi
	addq	(%r12), %rsi
	movzbl	6(%rbx), %edx
	movq	%rbx, %rdi
	callq	_write_reg
	movq	(%r14), %rsi
	addq	(%r15), %rsi
	movzbl	6(%rbx), %edx
	movq	%rbx, %rdi
	callq	_write_reg
	movq	_TXINTE@GOTPCREL(%rip), %rax
	movq	_RXINTE@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	addb	(%rax), %cl
	orb	8(%rbx), %cl
	movb	%cl, 8(%rbx)
	movq	_IE0@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movzbl	%cl, %edx
	movq	%rbx, %rdi
	callq	_write_reg
	movq	_SerialSignal_RTS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	xorl	%edx, %edx
	andl	12(%rbx), %eax
	sete	%dl
	movq	_CTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	orl	$16, %edx
	movq	%rbx, %rdi
	callq	_write_reg
	movq	%rbx, %rdi
	callq	_tx_set_idle
	movq	%rbx, %rdi
	callq	_tx_stop
	movq	%rbx, %rdi
	callq	_rx_stop
	movl	36(%rbx), %esi
	movq	%rbx, %rdi
	callq	_set_rate
	cmpq	$0, 40(%rbx)
	je	LBB0_16
## %bb.17:
	movq	%rbx, %rdi
	movl	$1, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_enable_loopback                ## TAILCALL
LBB0_16:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_2, LBB0_2-LJTI0_0
.set L0_0_set_8, LBB0_8-LJTI0_0
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_3, LBB0_3-LJTI0_0
.set L0_0_set_6, LBB0_6-LJTI0_0
LJTI0_0:
	.long	L0_0_set_2
	.long	L0_0_set_8
	.long	L0_0_set_8
	.long	L0_0_set_5
	.long	L0_0_set_3
	.long	L0_0_set_6
	.end_data_region
                                        ## -- End function
	.comm	_HDLC_FLAG_TXC_DPLL,4,2         ## @HDLC_FLAG_TXC_DPLL
	.comm	_HDLC_FLAG_RXC_DPLL,4,2         ## @HDLC_FLAG_RXC_DPLL
	.comm	_TXDMA,8,3                      ## @TXDMA
	.comm	_DIR,8,3                        ## @DIR
	.comm	_RXDMA,8,3                      ## @RXDMA
	.comm	_HDLC_FLAG_AUTO_CTS,4,2         ## @HDLC_FLAG_AUTO_CTS
	.comm	_BIT4,1,0                       ## @BIT4
	.comm	_HDLC_FLAG_AUTO_DCD,4,2         ## @HDLC_FLAG_AUTO_DCD
	.comm	_HDLC_CRC_16_CCITT,8,3          ## @HDLC_CRC_16_CCITT
	.comm	_BIT2,1,0                       ## @BIT2
	.comm	_BIT1,1,0                       ## @BIT1
	.comm	_MD0,8,3                        ## @MD0
	.comm	_MD1,8,3                        ## @MD1
	.comm	_BIT5,1,0                       ## @BIT5
	.comm	_BIT7,1,0                       ## @BIT7
	.comm	_BIT6,1,0                       ## @BIT6
	.comm	_HDLC_FLAG_DPLL_DIV16,4,2       ## @HDLC_FLAG_DPLL_DIV16
	.comm	_BIT3,1,0                       ## @BIT3
	.comm	_HDLC_FLAG_DPLL_DIV8,4,2        ## @HDLC_FLAG_DPLL_DIV8
	.comm	_MD2,8,3                        ## @MD2
	.comm	_HDLC_FLAG_RXC_BRG,4,2          ## @HDLC_FLAG_RXC_BRG
	.comm	_RXS,8,3                        ## @RXS
	.comm	_HDLC_FLAG_TXC_BRG,4,2          ## @HDLC_FLAG_TXC_BRG
	.comm	_TXS,8,3                        ## @TXS
	.comm	_BIT0,4,2                       ## @BIT0
	.comm	_RRC,8,3                        ## @RRC
	.comm	_rx_active_fifo_level,1,0       ## @rx_active_fifo_level
	.comm	_TRC0,8,3                       ## @TRC0
	.comm	_tx_active_fifo_level,1,0       ## @tx_active_fifo_level
	.comm	_TRC1,8,3                       ## @TRC1
	.comm	_tx_negate_fifo_level,4,2       ## @tx_negate_fifo_level
	.comm	_DMR,8,3                        ## @DMR
	.comm	_CPB,8,3                        ## @CPB
	.comm	_TXINTE,1,0                     ## @TXINTE
	.comm	_RXINTE,1,0                     ## @RXINTE
	.comm	_IE0,8,3                        ## @IE0
	.comm	_SerialSignal_RTS,4,2           ## @SerialSignal_RTS
	.comm	_CTL,8,3                        ## @CTL
	.no_dead_strip	_hdlc_mode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function hdlc_mode
_hdlc_mode:                             ; @hdlc_mode
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
Lloh0:
	adrp	x23, _HDLC_FLAG_TXC_DPLL@GOTPAGE
Lloh1:
	ldr	x23, [x23, _HDLC_FLAG_TXC_DPLL@GOTPAGEOFF]
	ldr	w8, [x23]
Lloh2:
	adrp	x22, _HDLC_FLAG_RXC_DPLL@GOTPAGE
Lloh3:
	ldr	x22, [x22, _HDLC_FLAG_RXC_DPLL@GOTPAGEOFF]
	ldr	w9, [x22]
	ldr	w10, [x0, #16]
	add	w8, w9, w8
	bic	w8, w10, w8
Lloh4:
	adrp	x20, _TXDMA@GOTPAGE
Lloh5:
	ldr	x20, [x20, _TXDMA@GOTPAGEOFF]
	str	w8, [x0, #16]
	ldr	x8, [x20]
Lloh6:
	adrp	x24, _DIR@GOTPAGE
Lloh7:
	ldr	x24, [x24, _DIR@GOTPAGEOFF]
	ldr	x9, [x24]
	add	x1, x9, x8
	mov	w2, #0
	bl	_write_reg
Lloh8:
	adrp	x21, _RXDMA@GOTPAGE
Lloh9:
	ldr	x21, [x21, _RXDMA@GOTPAGEOFF]
	ldr	x8, [x21]
	ldr	x9, [x24]
	add	x1, x9, x8
	mov	x0, x19
	mov	w2, #0
	bl	_write_reg
	ldr	w8, [x19, #16]
Lloh10:
	adrp	x9, _HDLC_FLAG_AUTO_CTS@GOTPAGE
Lloh11:
	ldr	x9, [x9, _HDLC_FLAG_AUTO_CTS@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
Lloh13:
	adrp	x26, _BIT4@GOTPAGE
Lloh14:
	ldr	x26, [x26, _BIT4@GOTPAGEOFF]
	ldrb	w10, [x26]
	mov	w11, #129
Lloh15:
	adrp	x12, _HDLC_FLAG_AUTO_DCD@GOTPAGE
Lloh16:
	ldr	x12, [x12, _HDLC_FLAG_AUTO_DCD@GOTPAGEOFF]
	orr	w10, w10, w11
Lloh17:
	ldr	w11, [x12]
	orr	w9, w11, w9
	tst	w9, w8
	mov	w8, #-127
	csel	w8, w8, w10, eq
	ldr	x9, [x19, #24]
Lloh18:
	adrp	x10, _HDLC_CRC_16_CCITT@GOTPAGE
Lloh19:
	ldr	x10, [x10, _HDLC_CRC_16_CCITT@GOTPAGEOFF]
Lloh20:
	ldr	x10, [x10]
Lloh21:
	adrp	x11, _BIT2@GOTPAGE
Lloh22:
	ldr	x11, [x11, _BIT2@GOTPAGEOFF]
	ldrb	w11, [x11]
Lloh23:
	adrp	x12, _BIT1@GOTPAGE
Lloh24:
	ldr	x12, [x12, _BIT1@GOTPAGEOFF]
	ldrb	w12, [x12]
	add	w11, w12, w11
	cmp	x9, x10
	csel	w9, w11, wzr, eq
	orr	w8, w9, w8
Lloh25:
	adrp	x9, _MD0@GOTPAGE
Lloh26:
	ldr	x9, [x9, _MD0@GOTPAGEOFF]
Lloh27:
	ldr	x1, [x9]
	and	w2, w8, #0xff
	mov	x0, x19
	bl	_write_reg
Lloh28:
	adrp	x8, _MD1@GOTPAGE
Lloh29:
	ldr	x8, [x8, _MD1@GOTPAGEOFF]
Lloh30:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_write_reg
	mov	w8, #0
	ldr	w9, [x19, #32]
	sub	w9, w9, #129
Lloh31:
	adrp	x25, _BIT6@GOTPAGE
Lloh32:
	ldr	x25, [x25, _BIT6@GOTPAGEOFF]
Lloh33:
	adrp	x24, _BIT5@GOTPAGE
Lloh34:
	ldr	x24, [x24, _BIT5@GOTPAGEOFF]
	cmp	w9, #5
	b.hi	LBB0_6
; %bb.1:
Lloh35:
	adrp	x10, lJTI0_0@PAGE
Lloh36:
	add	x10, x10, lJTI0_0@PAGEOFF
	adr	x11, LBB0_2
	ldrb	w12, [x10, x9]
	add	x11, x11, x12, lsl #2
	br	x11
LBB0_2:
	ldrb	w8, [x24]
	b	LBB0_6
LBB0_3:
Lloh37:
	adrp	x8, _BIT7@GOTPAGE
Lloh38:
	ldr	x8, [x8, _BIT7@GOTPAGEOFF]
	ldrb	w8, [x8]
	ldrb	w9, [x25]
	add	w8, w9, w8
	b	LBB0_6
LBB0_4:
Lloh39:
	adrp	x8, _BIT7@GOTPAGE
Lloh40:
	ldr	x8, [x8, _BIT7@GOTPAGEOFF]
	ldrb	w8, [x8]
	ldrb	w9, [x24]
	add	w8, w9, w8
	b	LBB0_6
LBB0_5:
Lloh41:
	adrp	x8, _BIT7@GOTPAGE
Lloh42:
	ldr	x8, [x8, _BIT7@GOTPAGEOFF]
	ldrb	w8, [x8]
LBB0_6:
	ldr	w9, [x19, #16]
Lloh43:
	adrp	x10, _HDLC_FLAG_DPLL_DIV16@GOTPAGE
Lloh44:
	ldr	x10, [x10, _HDLC_FLAG_DPLL_DIV16@GOTPAGEOFF]
Lloh45:
	ldr	w10, [x10]
	tst	w10, w9
	b.eq	LBB0_8
; %bb.7:
Lloh46:
	adrp	x9, _BIT3@GOTPAGE
Lloh47:
	ldr	x9, [x9, _BIT3@GOTPAGEOFF]
	ldrb	w9, [x9]
	orr	w8, w9, w8
	mov	w26, #16
	b	LBB0_11
LBB0_8:
Lloh48:
	adrp	x10, _HDLC_FLAG_DPLL_DIV8@GOTPAGE
Lloh49:
	ldr	x10, [x10, _HDLC_FLAG_DPLL_DIV8@GOTPAGEOFF]
Lloh50:
	ldr	w10, [x10]
	tst	w10, w9
	b.eq	LBB0_10
; %bb.9:
	mov	w26, #8
	b	LBB0_11
LBB0_10:
	ldrb	w9, [x26]
	orr	w8, w9, w8
	mov	w26, #32
LBB0_11:
Lloh51:
	adrp	x9, _MD2@GOTPAGE
Lloh52:
	ldr	x9, [x9, _MD2@GOTPAGEOFF]
Lloh53:
	ldr	x1, [x9]
	and	w2, w8, #0xff
	mov	x0, x19
	bl	_write_reg
	ldr	w8, [x19, #16]
Lloh54:
	adrp	x9, _HDLC_FLAG_RXC_BRG@GOTPAGE
Lloh55:
	ldr	x9, [x9, _HDLC_FLAG_RXC_BRG@GOTPAGEOFF]
Lloh56:
	ldr	w9, [x9]
	ldrb	w10, [x25]
	tst	w9, w8
	csel	w9, wzr, w10, eq
	ldr	w11, [x22]
	ldrb	w12, [x24]
	add	w10, w12, w10
	tst	w11, w8
	csel	w8, wzr, w10, eq
	orr	w8, w8, w9
Lloh57:
	adrp	x9, _RXS@GOTPAGE
Lloh58:
	ldr	x9, [x9, _RXS@GOTPAGEOFF]
Lloh59:
	ldr	x1, [x9]
	and	w2, w8, #0xff
	mov	x0, x19
	bl	_write_reg
	ldr	w8, [x19, #16]
Lloh60:
	adrp	x27, _HDLC_FLAG_TXC_BRG@GOTPAGE
Lloh61:
	ldr	x27, [x27, _HDLC_FLAG_TXC_BRG@GOTPAGEOFF]
	ldr	w9, [x27]
	ldrb	w10, [x25]
	tst	w9, w8
	csel	w9, wzr, w10, eq
	ldr	w11, [x23]
	ldrb	w12, [x24]
	add	w10, w12, w10
	tst	w11, w8
	csel	w8, wzr, w10, eq
	orr	w8, w8, w9
Lloh62:
	adrp	x9, _TXS@GOTPAGE
Lloh63:
	ldr	x9, [x9, _TXS@GOTPAGEOFF]
Lloh64:
	ldr	x1, [x9]
	and	w2, w8, #0xff
	mov	x0, x19
	bl	_write_reg
	ldr	w8, [x19, #16]
	ldr	w9, [x22]
	ldr	w10, [x19, #36]
	tst	w9, w8
	csinc	w8, w26, wzr, ne
	mul	w1, w10, w8
	mov	x0, x19
	bl	_set_rate
	ldr	w9, [x19, #16]
Lloh65:
	adrp	x8, _BIT0@GOTPAGE
Lloh66:
	ldr	x8, [x8, _BIT0@GOTPAGEOFF]
	ldr	w10, [x27]
Lloh67:
	ldr	w8, [x8]
	ldr	w11, [x19]
	lsl	w11, w11, #1
	lsl	w8, w8, w11
	tst	w10, w9
	b.eq	LBB0_13
; %bb.12:
	ldr	x9, [x19, #48]
	ldr	x9, [x9]
	ldr	w10, [x9]
	orr	w8, w10, w8
	b	LBB0_14
LBB0_13:
	ldr	x9, [x19, #48]
	ldr	x9, [x9]
	ldr	w10, [x9]
	bic	w8, w10, w8
LBB0_14:
	str	w8, [x9]
	mov	x0, x19
	bl	_write_control_reg
Lloh68:
	adrp	x8, _RRC@GOTPAGE
Lloh69:
	ldr	x8, [x8, _RRC@GOTPAGEOFF]
Lloh70:
	ldr	x1, [x8]
Lloh71:
	adrp	x8, _rx_active_fifo_level@GOTPAGE
Lloh72:
	ldr	x8, [x8, _rx_active_fifo_level@GOTPAGEOFF]
	ldrb	w2, [x8]
	mov	x0, x19
	bl	_write_reg
Lloh73:
	adrp	x8, _TRC0@GOTPAGE
Lloh74:
	ldr	x8, [x8, _TRC0@GOTPAGEOFF]
Lloh75:
	ldr	x1, [x8]
Lloh76:
	adrp	x8, _tx_active_fifo_level@GOTPAGE
Lloh77:
	ldr	x8, [x8, _tx_active_fifo_level@GOTPAGEOFF]
	ldrb	w2, [x8]
	mov	x0, x19
	bl	_write_reg
Lloh78:
	adrp	x8, _TRC1@GOTPAGE
Lloh79:
	ldr	x8, [x8, _TRC1@GOTPAGEOFF]
Lloh80:
	ldr	x1, [x8]
Lloh81:
	adrp	x8, _tx_negate_fifo_level@GOTPAGE
Lloh82:
	ldr	x8, [x8, _tx_negate_fifo_level@GOTPAGEOFF]
	ldrb	w8, [x8]
	sub	w8, w8, #1
	and	w2, w8, #0xff
	mov	x0, x19
	bl	_write_reg
	ldr	x8, [x20]
Lloh83:
	adrp	x22, _DMR@GOTPAGE
Lloh84:
	ldr	x22, [x22, _DMR@GOTPAGEOFF]
	ldr	x9, [x22]
	add	x1, x9, x8
	mov	x0, x19
	mov	w2, #20
	bl	_write_reg
	ldr	x8, [x21]
	ldr	x9, [x22]
	add	x1, x9, x8
	mov	x0, x19
	mov	w2, #20
	bl	_write_reg
	ldr	x8, [x21]
Lloh85:
	adrp	x21, _CPB@GOTPAGE
Lloh86:
	ldr	x21, [x21, _CPB@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x1, x9, x8
	ldrb	w2, [x19, #6]
	mov	x0, x19
	bl	_write_reg
	ldr	x8, [x20]
	ldr	x9, [x21]
	add	x1, x9, x8
	ldrb	w2, [x19, #6]
	mov	x0, x19
	bl	_write_reg
Lloh87:
	adrp	x8, _TXINTE@GOTPAGE
Lloh88:
	ldr	x8, [x8, _TXINTE@GOTPAGEOFF]
	ldrb	w8, [x8]
Lloh89:
	adrp	x9, _RXINTE@GOTPAGE
Lloh90:
	ldr	x9, [x9, _RXINTE@GOTPAGEOFF]
	ldrb	w9, [x9]
	ldrb	w10, [x19, #8]
	add	w8, w9, w8
	orr	w8, w8, w10
	strb	w8, [x19, #8]
Lloh91:
	adrp	x9, _IE0@GOTPAGE
Lloh92:
	ldr	x9, [x9, _IE0@GOTPAGEOFF]
Lloh93:
	ldr	x1, [x9]
	and	w2, w8, #0xff
	mov	x0, x19
	bl	_write_reg
	ldr	w8, [x19, #12]
Lloh94:
	adrp	x9, _SerialSignal_RTS@GOTPAGE
Lloh95:
	ldr	x9, [x9, _SerialSignal_RTS@GOTPAGEOFF]
Lloh96:
	ldr	w9, [x9]
Lloh97:
	adrp	x10, _CTL@GOTPAGE
Lloh98:
	ldr	x10, [x10, _CTL@GOTPAGEOFF]
Lloh99:
	ldr	x1, [x10]
	tst	w9, w8
	mov	w8, #16
	cinc	w2, w8, eq
	mov	x0, x19
	bl	_write_reg
	mov	x0, x19
	bl	_tx_set_idle
	mov	x0, x19
	bl	_tx_stop
	mov	x0, x19
	bl	_rx_stop
	ldr	w1, [x19, #36]
	mov	x0, x19
	bl	_set_rate
	ldr	x8, [x19, #40]
	cbz	x8, LBB0_16
; %bb.15:
	mov	x0, x19
	mov	w1, #1
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_enable_loopback
LBB0_16:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGot	Lloh89, Lloh90
	.loh AdrpLdrGot	Lloh87, Lloh88
	.loh AdrpLdrGot	Lloh85, Lloh86
	.loh AdrpLdrGot	Lloh83, Lloh84
	.loh AdrpLdrGot	Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGot	Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGot	Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_6-LBB0_2)>>2
	.byte	(LBB0_6-LBB0_2)>>2
	.byte	(LBB0_3-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
                                        ; -- End function
	.comm	_HDLC_FLAG_TXC_DPLL,4,2         ; @HDLC_FLAG_TXC_DPLL
	.comm	_HDLC_FLAG_RXC_DPLL,4,2         ; @HDLC_FLAG_RXC_DPLL
	.comm	_TXDMA,8,3                      ; @TXDMA
	.comm	_DIR,8,3                        ; @DIR
	.comm	_RXDMA,8,3                      ; @RXDMA
	.comm	_HDLC_FLAG_AUTO_CTS,4,2         ; @HDLC_FLAG_AUTO_CTS
	.comm	_BIT4,1,0                       ; @BIT4
	.comm	_HDLC_FLAG_AUTO_DCD,4,2         ; @HDLC_FLAG_AUTO_DCD
	.comm	_HDLC_CRC_16_CCITT,8,3          ; @HDLC_CRC_16_CCITT
	.comm	_BIT2,1,0                       ; @BIT2
	.comm	_BIT1,1,0                       ; @BIT1
	.comm	_MD0,8,3                        ; @MD0
	.comm	_MD1,8,3                        ; @MD1
	.comm	_BIT5,1,0                       ; @BIT5
	.comm	_BIT7,1,0                       ; @BIT7
	.comm	_BIT6,1,0                       ; @BIT6
	.comm	_HDLC_FLAG_DPLL_DIV16,4,2       ; @HDLC_FLAG_DPLL_DIV16
	.comm	_BIT3,1,0                       ; @BIT3
	.comm	_HDLC_FLAG_DPLL_DIV8,4,2        ; @HDLC_FLAG_DPLL_DIV8
	.comm	_MD2,8,3                        ; @MD2
	.comm	_HDLC_FLAG_RXC_BRG,4,2          ; @HDLC_FLAG_RXC_BRG
	.comm	_RXS,8,3                        ; @RXS
	.comm	_HDLC_FLAG_TXC_BRG,4,2          ; @HDLC_FLAG_TXC_BRG
	.comm	_TXS,8,3                        ; @TXS
	.comm	_BIT0,4,2                       ; @BIT0
	.comm	_RRC,8,3                        ; @RRC
	.comm	_rx_active_fifo_level,1,0       ; @rx_active_fifo_level
	.comm	_TRC0,8,3                       ; @TRC0
	.comm	_tx_active_fifo_level,1,0       ; @tx_active_fifo_level
	.comm	_TRC1,8,3                       ; @TRC1
	.comm	_tx_negate_fifo_level,4,2       ; @tx_negate_fifo_level
	.comm	_DMR,8,3                        ; @DMR
	.comm	_CPB,8,3                        ; @CPB
	.comm	_TXINTE,1,0                     ; @TXINTE
	.comm	_RXINTE,1,0                     ; @RXINTE
	.comm	_IE0,8,3                        ; @IE0
	.comm	_SerialSignal_RTS,4,2           ; @SerialSignal_RTS
	.comm	_CTL,8,3                        ; @CTL
	.no_dead_strip	_hdlc_mode
.subsections_via_symbols
