	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function qib_tune_pcie_caps
_qib_tune_pcie_caps:                    ## @qib_tune_pcie_caps
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	(%rdi), %rdi
	movq	(%rdi), %rax
	movq	8(%rax), %r12
	movq	(%r12), %rax
	cmpq	$0, (%rax)
	je	LBB0_2
## %bb.1:
	leaq	L_.str(%rip), %rsi
	callq	_qib_devinfo
	movl	$1, %ebx
LBB0_12:
	movl	%ebx, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	movq	%r12, %rdi
	callq	_pci_is_pcie
	movl	$1, %ebx
	testl	%eax, %eax
	je	LBB0_12
## %bb.3:
	movq	(%r14), %rdi
	callq	_pci_is_pcie
	testl	%eax, %eax
	je	LBB0_12
## %bb.4:
	movq	_PCI_EXP_DEVCAP@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	leaq	-56(%rbp), %rdx
	movq	%r12, %rdi
	callq	_pcie_capability_read_word
	movq	_PCI_EXP_DEVCTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rax, %rbx
	leaq	-48(%rbp), %rdx
	movq	%r12, %rdi
	callq	_pcie_capability_read_word
	movq	(%r14), %rdi
	movl	(%r15), %esi
	leaq	-52(%rbp), %rdx
	callq	_pcie_capability_read_word
	movq	(%r14), %rdi
	movl	(%rbx), %esi
	leaq	-44(%rbp), %rdx
	callq	_pcie_capability_read_word
	movl	-56(%rbp), %edi
	movq	_PCI_EXP_DEVCAP_PAYLOAD@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	callq	_fld2val
	movl	%eax, %ebx
	movl	-52(%rbp), %edi
	movl	(%r15), %esi
	callq	_fld2val
	movl	%eax, %r13d
	cmpl	%eax, %ebx
	cmovll	%ebx, %r13d
	movl	-48(%rbp), %edi
	movq	_PCI_EXP_DEVCTL_PAYLOAD@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	callq	_fld2val
	movl	%eax, %r15d
	movl	-44(%rbp), %edi
	movl	(%rbx), %esi
	callq	_fld2val
	movl	%eax, %ecx
	movq	_qib_pcie_caps@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	andl	$7, %ebx
	cmpl	%ebx, %r13d
	cmovll	%r13d, %ebx
	movq	_PCI_EXP_DEVCTL@GOTPCREL(%rip), %r13
	cmpl	%r15d, %ebx
	jle	LBB0_6
## %bb.5:
	movq	_PCI_EXP_DEVCTL_PAYLOAD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%esi, %r15d
	notl	%r15d
	andl	-48(%rbp), %r15d
	movl	%ebx, %edi
	movl	%ecx, %r13d
	callq	_val2fld
	orl	%eax, %r15d
	movl	%r15d, -48(%rbp)
	movq	_PCI_EXP_DEVCTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	%r15d, %edx
	callq	_pcie_capability_write_word
	movl	%r13d, %ecx
	movq	_PCI_EXP_DEVCTL@GOTPCREL(%rip), %r13
LBB0_6:
	movq	_PCI_EXP_DEVCTL_PAYLOAD@GOTPCREL(%rip), %rax
	cmpl	%ecx, %ebx
	jle	LBB0_8
## %bb.7:
	movl	(%rax), %esi
	movl	%esi, %r15d
	notl	%r15d
	andl	-44(%rbp), %r15d
	movl	%ebx, %edi
	callq	_val2fld
	orl	%eax, %r15d
	movl	%r15d, -44(%rbp)
	movq	(%r14), %rdi
	movl	(%r13), %esi
	movl	%r15d, %edx
	callq	_pcie_capability_write_word
LBB0_8:
	movq	_qib_pcie_caps@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	shrl	$4, %eax
	andl	$7, %eax
	cmpl	$5, %eax
	movl	$5, %r15d
	cmovbl	%eax, %r15d
	movl	-48(%rbp), %edi
	movq	_PCI_EXP_DEVCTL_READRQ@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	callq	_fld2val
	movl	%eax, %ebx
	movl	-44(%rbp), %edi
	movl	(%r13), %esi
	callq	_fld2val
	movl	%eax, %r13d
	cmpl	%ebx, %r15d
	jle	LBB0_10
## %bb.9:
	movq	_PCI_EXP_DEVCTL_READRQ@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%esi, %ebx
	notl	%ebx
	andl	-48(%rbp), %ebx
	movl	%r15d, %edi
	callq	_val2fld
	orl	%eax, %ebx
	movl	%ebx, -48(%rbp)
	movq	_PCI_EXP_DEVCTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	%ebx, %edx
	callq	_pcie_capability_write_word
LBB0_10:
	movq	_PCI_EXP_DEVCTL_READRQ@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	cmpl	%r13d, %r15d
	jle	LBB0_12
## %bb.11:
	movl	(%rax), %esi
	movl	%esi, %r12d
	notl	%r12d
	andl	-44(%rbp), %r12d
	movl	%r15d, %edi
	callq	_val2fld
	orl	%eax, %r12d
	movl	%r12d, -44(%rbp)
	movq	(%r14), %rdi
	movq	_PCI_EXP_DEVCTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r12d, %edx
	callq	_pcie_capability_write_word
	jmp	LBB0_12
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Parent not root\n"

	.comm	_PCI_EXP_DEVCAP,4,2             ## @PCI_EXP_DEVCAP
	.comm	_PCI_EXP_DEVCTL,4,2             ## @PCI_EXP_DEVCTL
	.comm	_PCI_EXP_DEVCAP_PAYLOAD,4,2     ## @PCI_EXP_DEVCAP_PAYLOAD
	.comm	_PCI_EXP_DEVCTL_PAYLOAD,4,2     ## @PCI_EXP_DEVCTL_PAYLOAD
	.comm	_qib_pcie_caps,4,2              ## @qib_pcie_caps
	.comm	_PCI_EXP_DEVCTL_READRQ,4,2      ## @PCI_EXP_DEVCTL_READRQ
	.no_dead_strip	_qib_tune_pcie_caps
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function qib_tune_pcie_caps
_qib_tune_pcie_caps:                    ; @qib_tune_pcie_caps
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldr	x0, [x0]
	ldr	x8, [x0]
	ldr	x20, [x8, #8]
	ldr	x8, [x20]
	ldr	x8, [x8]
	cbz	x8, LBB0_4
; %bb.1:
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	bl	_qib_devinfo
LBB0_2:
	mov	w0, #1
LBB0_3:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_4:
	mov	x0, x20
	bl	_pci_is_pcie
	cbz	w0, LBB0_2
; %bb.5:
	ldr	x0, [x19]
	bl	_pci_is_pcie
	cbz	w0, LBB0_2
; %bb.6:
Lloh2:
	adrp	x21, _PCI_EXP_DEVCAP@GOTPAGE
Lloh3:
	ldr	x21, [x21, _PCI_EXP_DEVCAP@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x2, sp, #12
	mov	x0, x20
	bl	_pcie_capability_read_word
Lloh4:
	adrp	x24, _PCI_EXP_DEVCTL@GOTPAGE
Lloh5:
	ldr	x24, [x24, _PCI_EXP_DEVCTL@GOTPAGEOFF]
	ldr	w1, [x24]
	add	x2, sp, #8
	mov	x0, x20
	bl	_pcie_capability_read_word
	ldr	x0, [x19]
	ldr	w1, [x21]
	add	x2, sp, #4
	bl	_pcie_capability_read_word
	ldr	x0, [x19]
	ldr	w1, [x24]
	mov	x2, sp
	bl	_pcie_capability_read_word
	ldr	w0, [sp, #12]
Lloh6:
	adrp	x22, _PCI_EXP_DEVCAP_PAYLOAD@GOTPAGE
Lloh7:
	ldr	x22, [x22, _PCI_EXP_DEVCAP_PAYLOAD@GOTPAGEOFF]
	ldr	w1, [x22]
	bl	_fld2val
	mov	x21, x0
	ldr	w0, [sp, #4]
	ldr	w1, [x22]
	bl	_fld2val
	cmp	w21, w0
	csel	w21, w21, w0, lt
	ldr	w0, [sp, #8]
Lloh8:
	adrp	x26, _PCI_EXP_DEVCTL_PAYLOAD@GOTPAGE
Lloh9:
	ldr	x26, [x26, _PCI_EXP_DEVCTL_PAYLOAD@GOTPAGEOFF]
	ldr	w1, [x26]
	bl	_fld2val
	mov	x23, x0
	ldr	w0, [sp]
	ldr	w1, [x26]
	bl	_fld2val
	mov	x22, x0
Lloh10:
	adrp	x25, _qib_pcie_caps@GOTPAGE
Lloh11:
	ldr	x25, [x25, _qib_pcie_caps@GOTPAGEOFF]
	ldr	w8, [x25]
	and	w8, w8, #0x7
	cmp	w21, w8
	csel	w21, w21, w8, lt
	cmp	w21, w23
	b.le	LBB0_8
; %bb.7:
	ldr	w8, [sp, #8]
	ldr	w1, [x26]
	bic	w23, w8, w1
	mov	x0, x21
	bl	_val2fld
	orr	w2, w23, w0
	str	w2, [sp, #8]
	ldr	w1, [x24]
	mov	x0, x20
	bl	_pcie_capability_write_word
LBB0_8:
	cmp	w21, w22
	b.le	LBB0_10
; %bb.9:
	ldr	w8, [sp]
	ldr	w1, [x26]
	bic	w22, w8, w1
	mov	x0, x21
	bl	_val2fld
	orr	w2, w22, w0
	str	w2, [sp]
	ldr	x0, [x19]
	ldr	w1, [x24]
	bl	_pcie_capability_write_word
LBB0_10:
	ldr	w8, [x25]
	ubfx	w8, w8, #4, #3
	mov	w9, #5
	cmp	w8, #5
	csel	w21, w8, w9, lo
	ldr	w0, [sp, #8]
Lloh12:
	adrp	x25, _PCI_EXP_DEVCTL_READRQ@GOTPAGE
Lloh13:
	ldr	x25, [x25, _PCI_EXP_DEVCTL_READRQ@GOTPAGEOFF]
	ldr	w1, [x25]
	bl	_fld2val
	mov	x23, x0
	ldr	w0, [sp]
	ldr	w1, [x25]
	bl	_fld2val
	mov	x22, x0
	cmp	w21, w23
	b.le	LBB0_12
; %bb.11:
	ldr	w8, [sp, #8]
	ldr	w1, [x25]
	bic	w23, w8, w1
	mov	x0, x21
	bl	_val2fld
	orr	w2, w23, w0
	str	w2, [sp, #8]
	ldr	w1, [x24]
	mov	x0, x20
	bl	_pcie_capability_write_word
LBB0_12:
	cmp	w21, w22
	b.le	LBB0_14
; %bb.13:
	ldr	w8, [sp]
	ldr	w1, [x25]
	bic	w20, w8, w1
	mov	x0, x21
	bl	_val2fld
	orr	w2, w20, w0
	str	w2, [sp]
	ldr	x0, [x19]
	ldr	w1, [x24]
	bl	_pcie_capability_write_word
LBB0_14:
	mov	w0, #0
	b	LBB0_3
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh12, Lloh13
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Parent not root\n"

	.comm	_PCI_EXP_DEVCAP,4,2             ; @PCI_EXP_DEVCAP
	.comm	_PCI_EXP_DEVCTL,4,2             ; @PCI_EXP_DEVCTL
	.comm	_PCI_EXP_DEVCAP_PAYLOAD,4,2     ; @PCI_EXP_DEVCAP_PAYLOAD
	.comm	_PCI_EXP_DEVCTL_PAYLOAD,4,2     ; @PCI_EXP_DEVCTL_PAYLOAD
	.comm	_qib_pcie_caps,4,2              ; @qib_pcie_caps
	.comm	_PCI_EXP_DEVCTL_READRQ,4,2      ; @PCI_EXP_DEVCTL_READRQ
	.no_dead_strip	_qib_tune_pcie_caps
.subsections_via_symbols
