	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_do_release              ## -- Begin function radeon_do_release
	.p2align	4, 0x90
_radeon_do_release:                     ## @radeon_do_release
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, -56(%rbp)                 ## 8-byte Spill
	movq	(%rdi), %rbx
	testq	%rbx, %rbx
	je	LBB0_22
## %bb.1:
	cmpq	$0, 40(%rbx)
	je	LBB0_12
## %bb.2:
	movq	_RADEON_FAMILY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%rbx), %eax
	movq	_CHIP_R600@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jge	LBB0_3
## %bb.6:
	movq	%rbx, %rdi
	callq	_radeon_do_cp_idle
	movl	%eax, -44(%rbp)
	testl	%eax, %eax
	je	LBB0_9
## %bb.7:
	leaq	L_.str(%rip), %r15
	movq	_PZERO@GOTPCREL(%rip), %r14
	leaq	L_.str.1(%rip), %r12
	leaq	-44(%rbp), %r13
	.p2align	4, 0x90
LBB0_8:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_DRM_DEBUG
	movl	(%r14), %esi
	movq	%r13, %rdi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	_tsleep
	movq	%rbx, %rdi
	callq	_radeon_do_cp_idle
	movl	%eax, -44(%rbp)
	testl	%eax, %eax
	jne	LBB0_8
	jmp	LBB0_9
LBB0_3:
	movq	%rbx, %rdi
	callq	_r600_do_cp_idle
	movl	%eax, -44(%rbp)
	testl	%eax, %eax
	je	LBB0_9
## %bb.4:
	leaq	L_.str(%rip), %r15
	movq	_PZERO@GOTPCREL(%rip), %r14
	leaq	L_.str.1(%rip), %r12
	leaq	-44(%rbp), %r13
	.p2align	4, 0x90
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_DRM_DEBUG
	movl	(%r14), %esi
	movq	%r13, %rdi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	_tsleep
	movq	%rbx, %rdi
	callq	_r600_do_cp_idle
	movl	%eax, -44(%rbp)
	testl	%eax, %eax
	jne	LBB0_5
LBB0_9:
	movq	_RADEON_FAMILY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%rbx), %eax
	movq	_CHIP_R600@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jge	LBB0_10
## %bb.11:
	movq	%rbx, %rdi
	callq	_radeon_do_cp_stop
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_radeon_do_engine_reset
	jmp	LBB0_12
LBB0_10:
	movq	%rbx, %rdi
	callq	_r600_do_cp_stop
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_r600_do_engine_reset
LBB0_12:
	movq	_RADEON_FAMILY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%rbx), %eax
	movq	_CHIP_R600@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jge	LBB0_18
## %bb.13:
	cmpq	$0, 32(%rbx)
	je	LBB0_18
## %bb.14:
	movq	_RADEON_GEN_INT_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_RADEON_WRITE
	cmpq	$0, 32(%rbx)
	je	LBB0_18
## %bb.15:
	movq	_RADEON_MAX_SURFACES@GOTPCREL(%rip), %r14
	cmpl	$0, (%r14)
	jle	LBB0_18
## %bb.16:
	xorl	%r15d, %r15d
	movq	_RADEON_SURFACE0_UPPER_BOUND@GOTPCREL(%rip), %r13
	xorl	%r12d, %r12d
	.p2align	4, 0x90
LBB0_17:                                ## =>This Inner Loop Header: Depth=1
	movq	_RADEON_SURFACE0_INFO@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	%r15, %rdi
	xorl	%esi, %esi
	callq	_RADEON_WRITE
	movq	_RADEON_SURFACE0_LOWER_BOUND@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	%r15, %rdi
	xorl	%esi, %esi
	callq	_RADEON_WRITE
	movq	(%r13), %rdi
	addq	%r15, %rdi
	xorl	%esi, %esi
	callq	_RADEON_WRITE
	incq	%r12
	movslq	(%r14), %rax
	addq	$16, %r15
	cmpq	%rax, %r12
	jl	LBB0_17
LBB0_18:
	leaq	28(%rbx), %rdi
	callq	_radeon_mem_takedown
	leaq	24(%rbx), %rdi
	callq	_radeon_mem_takedown
	movq	_RADEON_FAMILY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%rbx), %eax
	movq	_CHIP_R600@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jge	LBB0_19
## %bb.20:
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_radeon_do_cleanup_cp
	jmp	LBB0_21
LBB0_19:
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_r600_do_cleanup_cp
LBB0_21:
	movq	16(%rbx), %rdi
	callq	_release_firmware
	movq	$0, 16(%rbx)
	movq	8(%rbx), %rdi
	callq	_release_firmware
	movq	$0, 8(%rbx)
LBB0_22:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_FAMILY_MASK,4,2         ## @RADEON_FAMILY_MASK
	.comm	_CHIP_R600,4,2                  ## @CHIP_R600
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"radeon_do_cp_idle %d\n"

	.comm	_PZERO,4,2                      ## @PZERO
L_.str.1:                               ## @.str.1
	.asciz	"rdnrel"

	.comm	_RADEON_GEN_INT_CNTL,8,3        ## @RADEON_GEN_INT_CNTL
	.comm	_RADEON_MAX_SURFACES,4,2        ## @RADEON_MAX_SURFACES
	.comm	_RADEON_SURFACE0_INFO,8,3       ## @RADEON_SURFACE0_INFO
	.comm	_RADEON_SURFACE0_LOWER_BOUND,8,3 ## @RADEON_SURFACE0_LOWER_BOUND
	.comm	_RADEON_SURFACE0_UPPER_BOUND,8,3 ## @RADEON_SURFACE0_UPPER_BOUND
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_do_release              ; -- Begin function radeon_do_release
	.p2align	2
_radeon_do_release:                     ; @radeon_do_release
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	ldr	x19, [x0]
	cbz	x19, LBB0_21
; %bb.1:
	mov	x20, x0
	ldr	x8, [x19, #40]
Lloh0:
	adrp	x24, _RADEON_FAMILY_MASK@GOTPAGE
Lloh1:
	ldr	x24, [x24, _RADEON_FAMILY_MASK@GOTPAGEOFF]
Lloh2:
	adrp	x23, _CHIP_R600@GOTPAGE
Lloh3:
	ldr	x23, [x23, _CHIP_R600@GOTPAGEOFF]
	cbz	x8, LBB0_12
; %bb.2:
	ldr	w8, [x19]
	ldr	w9, [x24]
	and	w8, w9, w8
	ldr	w9, [x23]
	mov	x0, x19
	cmp	w8, w9
	b.ge	LBB0_6
; %bb.3:
	bl	_radeon_do_cp_idle
	str	w0, [sp, #12]
	cbz	w0, LBB0_9
; %bb.4:
	mov	x1, x0
Lloh4:
	adrp	x21, l_.str@PAGE
Lloh5:
	add	x21, x21, l_.str@PAGEOFF
Lloh6:
	adrp	x25, _PZERO@GOTPAGE
Lloh7:
	ldr	x25, [x25, _PZERO@GOTPAGEOFF]
Lloh8:
	adrp	x22, l_.str.1@PAGE
Lloh9:
	add	x22, x22, l_.str.1@PAGEOFF
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x21
	bl	_DRM_DEBUG
	ldr	w1, [x25]
	add	x0, sp, #12
	mov	x2, x22
	mov	w3, #1
	bl	_tsleep
	mov	x0, x19
	bl	_radeon_do_cp_idle
	mov	x1, x0
	str	w0, [sp, #12]
	cbnz	w0, LBB0_5
	b	LBB0_9
LBB0_6:
	bl	_r600_do_cp_idle
	str	w0, [sp, #12]
	cbz	w0, LBB0_9
; %bb.7:
	mov	x1, x0
Lloh10:
	adrp	x21, l_.str@PAGE
Lloh11:
	add	x21, x21, l_.str@PAGEOFF
Lloh12:
	adrp	x25, _PZERO@GOTPAGE
Lloh13:
	ldr	x25, [x25, _PZERO@GOTPAGEOFF]
Lloh14:
	adrp	x22, l_.str.1@PAGE
Lloh15:
	add	x22, x22, l_.str.1@PAGEOFF
LBB0_8:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x21
	bl	_DRM_DEBUG
	ldr	w1, [x25]
	add	x0, sp, #12
	mov	x2, x22
	mov	w3, #1
	bl	_tsleep
	mov	x0, x19
	bl	_r600_do_cp_idle
	mov	x1, x0
	str	w0, [sp, #12]
	cbnz	w0, LBB0_8
LBB0_9:
	ldr	w8, [x19]
	ldr	w9, [x24]
	and	w8, w9, w8
	ldr	w9, [x23]
	mov	x0, x19
	cmp	w8, w9
	b.ge	LBB0_11
; %bb.10:
	bl	_radeon_do_cp_stop
	mov	x0, x20
	bl	_radeon_do_engine_reset
	b	LBB0_12
LBB0_11:
	bl	_r600_do_cp_stop
	mov	x0, x20
	bl	_r600_do_engine_reset
LBB0_12:
	ldr	w8, [x19]
	ldr	w9, [x24]
	and	w8, w9, w8
	ldr	w9, [x23]
	cmp	w8, w9
	b.ge	LBB0_17
; %bb.13:
	ldr	x8, [x19, #32]
	cbz	x8, LBB0_17
; %bb.14:
Lloh16:
	adrp	x8, _RADEON_GEN_INT_CNTL@GOTPAGE
Lloh17:
	ldr	x8, [x8, _RADEON_GEN_INT_CNTL@GOTPAGEOFF]
Lloh18:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_RADEON_WRITE
	ldr	x8, [x19, #32]
Lloh19:
	adrp	x21, _RADEON_MAX_SURFACES@GOTPAGE
Lloh20:
	ldr	x21, [x21, _RADEON_MAX_SURFACES@GOTPAGEOFF]
	ldr	w9, [x21]
	cmp	x8, #0
	ccmp	w9, #1, #8, ne
	b.lt	LBB0_17
; %bb.15:
	mov	x22, #0
	mov	x25, #0
Lloh21:
	adrp	x26, _RADEON_SURFACE0_INFO@GOTPAGE
Lloh22:
	ldr	x26, [x26, _RADEON_SURFACE0_INFO@GOTPAGEOFF]
Lloh23:
	adrp	x27, _RADEON_SURFACE0_LOWER_BOUND@GOTPAGE
Lloh24:
	ldr	x27, [x27, _RADEON_SURFACE0_LOWER_BOUND@GOTPAGEOFF]
Lloh25:
	adrp	x28, _RADEON_SURFACE0_UPPER_BOUND@GOTPAGE
Lloh26:
	ldr	x28, [x28, _RADEON_SURFACE0_UPPER_BOUND@GOTPAGEOFF]
LBB0_16:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x26]
	add	x0, x22, x8
	mov	w1, #0
	bl	_RADEON_WRITE
	ldr	x8, [x27]
	add	x0, x22, x8
	mov	w1, #0
	bl	_RADEON_WRITE
	ldr	x8, [x28]
	add	x0, x22, x8
	mov	w1, #0
	bl	_RADEON_WRITE
	add	x25, x25, #1
	ldrsw	x8, [x21]
	add	x22, x22, #16
	cmp	x25, x8
	b.lt	LBB0_16
LBB0_17:
	add	x0, x19, #28
	bl	_radeon_mem_takedown
	add	x0, x19, #24
	bl	_radeon_mem_takedown
	ldr	w8, [x19]
	ldr	w9, [x24]
	and	w8, w9, w8
	ldr	w9, [x23]
	mov	x0, x20
	cmp	w8, w9
	b.ge	LBB0_19
; %bb.18:
	bl	_radeon_do_cleanup_cp
	b	LBB0_20
LBB0_19:
	bl	_r600_do_cleanup_cp
LBB0_20:
	ldr	x0, [x19, #16]
	bl	_release_firmware
	str	xzr, [x19, #16]
	ldr	x0, [x19, #8]
	bl	_release_firmware
	str	xzr, [x19, #8]
LBB0_21:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpAdd	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh21, Lloh22
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_FAMILY_MASK,4,2         ; @RADEON_FAMILY_MASK
	.comm	_CHIP_R600,4,2                  ; @CHIP_R600
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"radeon_do_cp_idle %d\n"

	.comm	_PZERO,4,2                      ; @PZERO
l_.str.1:                               ; @.str.1
	.asciz	"rdnrel"

	.comm	_RADEON_GEN_INT_CNTL,8,3        ; @RADEON_GEN_INT_CNTL
	.comm	_RADEON_MAX_SURFACES,4,2        ; @RADEON_MAX_SURFACES
	.comm	_RADEON_SURFACE0_INFO,8,3       ; @RADEON_SURFACE0_INFO
	.comm	_RADEON_SURFACE0_LOWER_BOUND,8,3 ; @RADEON_SURFACE0_LOWER_BOUND
	.comm	_RADEON_SURFACE0_UPPER_BOUND,8,3 ; @RADEON_SURFACE0_UPPER_BOUND
.subsections_via_symbols
