	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gen6_render_ring_flush
_gen6_render_ring_flush:                ## @gen6_render_ring_flush
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r13d
	movl	%esi, %r12d
	movq	%rdi, %r15
	movq	(%rdi), %rax
	movl	(%rax), %r14d
	callq	_intel_emit_post_sync_nonzero_flush
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_8
## %bb.1:
	testl	%r13d, %r13d
	je	LBB0_2
## %bb.3:
	movq	_PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH@GOTPCREL(%rip), %rax
	movq	_PIPE_CONTROL_DEPTH_CACHE_FLUSH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r13d
	orl	(%rax), %r13d
	movq	_PIPE_CONTROL_CS_STALL@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	testl	%r12d, %r12d
	je	LBB0_6
LBB0_5:
	movq	_PIPE_CONTROL_TLB_INVALIDATE@GOTPCREL(%rip), %rax
	movq	_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE@GOTPCREL(%rip), %rcx
	movq	_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE@GOTPCREL(%rip), %rdx
	movq	_PIPE_CONTROL_VF_CACHE_INVALIDATE@GOTPCREL(%rip), %rsi
	movq	_PIPE_CONTROL_CONST_CACHE_INVALIDATE@GOTPCREL(%rip), %rdi
	movq	_PIPE_CONTROL_STATE_CACHE_INVALIDATE@GOTPCREL(%rip), %rbx
	movq	_PIPE_CONTROL_QW_WRITE@GOTPCREL(%rip), %r8
	movq	_PIPE_CONTROL_CS_STALL@GOTPCREL(%rip), %r9
	orl	(%rax), %r13d
	orl	(%rcx), %r13d
	orl	(%rdx), %r13d
	orl	(%rsi), %r13d
	orl	(%rdi), %r13d
	orl	(%rbx), %r13d
	orl	(%r8), %r13d
	orl	(%r9), %r13d
LBB0_6:
	movq	%r15, %rdi
	movl	$4, %esi
	callq	_intel_ring_begin
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_8
## %bb.7:
	subl	$-128, %r14d
	movl	$4, %edi
	callq	_GFX_OP_PIPE_CONTROL
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_intel_ring_emit
	movq	%r15, %rdi
	movl	%r13d, %esi
	callq	_intel_ring_emit
	movq	_PIPE_CONTROL_GLOBAL_GTT@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_intel_ring_emit
	xorl	%ebx, %ebx
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_intel_ring_emit
	movq	%r15, %rdi
	callq	_intel_ring_advance
LBB0_8:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	xorl	%r13d, %r13d
	testl	%r12d, %r12d
	jne	LBB0_5
	jmp	LBB0_6
	.cfi_endproc
                                        ## -- End function
	.comm	_PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH,4,2 ## @PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
	.comm	_PIPE_CONTROL_DEPTH_CACHE_FLUSH,4,2 ## @PIPE_CONTROL_DEPTH_CACHE_FLUSH
	.comm	_PIPE_CONTROL_CS_STALL,4,2      ## @PIPE_CONTROL_CS_STALL
	.comm	_PIPE_CONTROL_TLB_INVALIDATE,4,2 ## @PIPE_CONTROL_TLB_INVALIDATE
	.comm	_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE,4,2 ## @PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
	.comm	_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE,4,2 ## @PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
	.comm	_PIPE_CONTROL_VF_CACHE_INVALIDATE,4,2 ## @PIPE_CONTROL_VF_CACHE_INVALIDATE
	.comm	_PIPE_CONTROL_CONST_CACHE_INVALIDATE,4,2 ## @PIPE_CONTROL_CONST_CACHE_INVALIDATE
	.comm	_PIPE_CONTROL_STATE_CACHE_INVALIDATE,4,2 ## @PIPE_CONTROL_STATE_CACHE_INVALIDATE
	.comm	_PIPE_CONTROL_QW_WRITE,4,2      ## @PIPE_CONTROL_QW_WRITE
	.comm	_PIPE_CONTROL_GLOBAL_GTT,4,2    ## @PIPE_CONTROL_GLOBAL_GTT
	.no_dead_strip	_gen6_render_ring_flush
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gen6_render_ring_flush
_gen6_render_ring_flush:                ; @gen6_render_ring_flush
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x2
	mov	x21, x1
	mov	x19, x0
	ldr	x8, [x0]
	ldr	w22, [x8]
	bl	_intel_emit_post_sync_nonzero_flush
	cbnz	w0, LBB0_7
; %bb.1:
Lloh0:
	adrp	x8, _PIPE_CONTROL_CS_STALL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PIPE_CONTROL_CS_STALL@GOTPAGEOFF]
	cbz	w20, LBB0_3
; %bb.2:
Lloh2:
	adrp	x9, _PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH@GOTPAGE
Lloh3:
	ldr	x9, [x9, _PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH@GOTPAGEOFF]
Lloh4:
	ldr	w9, [x9]
Lloh5:
	adrp	x10, _PIPE_CONTROL_DEPTH_CACHE_FLUSH@GOTPAGE
Lloh6:
	ldr	x10, [x10, _PIPE_CONTROL_DEPTH_CACHE_FLUSH@GOTPAGEOFF]
Lloh7:
	ldr	w10, [x10]
	orr	w9, w10, w9
	ldr	w10, [x8]
	orr	w20, w9, w10
LBB0_3:
	cbz	w21, LBB0_5
; %bb.4:
Lloh8:
	adrp	x9, _PIPE_CONTROL_TLB_INVALIDATE@GOTPAGE
Lloh9:
	ldr	x9, [x9, _PIPE_CONTROL_TLB_INVALIDATE@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
Lloh11:
	adrp	x10, _PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE@GOTPAGE
Lloh12:
	ldr	x10, [x10, _PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE@GOTPAGEOFF]
Lloh13:
	ldr	w10, [x10]
Lloh14:
	adrp	x11, _PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE@GOTPAGE
Lloh15:
	ldr	x11, [x11, _PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE@GOTPAGEOFF]
Lloh16:
	ldr	w11, [x11]
Lloh17:
	adrp	x12, _PIPE_CONTROL_VF_CACHE_INVALIDATE@GOTPAGE
Lloh18:
	ldr	x12, [x12, _PIPE_CONTROL_VF_CACHE_INVALIDATE@GOTPAGEOFF]
Lloh19:
	ldr	w12, [x12]
Lloh20:
	adrp	x13, _PIPE_CONTROL_CONST_CACHE_INVALIDATE@GOTPAGE
Lloh21:
	ldr	x13, [x13, _PIPE_CONTROL_CONST_CACHE_INVALIDATE@GOTPAGEOFF]
Lloh22:
	ldr	w13, [x13]
Lloh23:
	adrp	x14, _PIPE_CONTROL_STATE_CACHE_INVALIDATE@GOTPAGE
Lloh24:
	ldr	x14, [x14, _PIPE_CONTROL_STATE_CACHE_INVALIDATE@GOTPAGEOFF]
Lloh25:
	ldr	w14, [x14]
Lloh26:
	adrp	x15, _PIPE_CONTROL_QW_WRITE@GOTPAGE
Lloh27:
	ldr	x15, [x15, _PIPE_CONTROL_QW_WRITE@GOTPAGEOFF]
Lloh28:
	ldr	w15, [x15]
	ldr	w8, [x8]
	orr	w9, w9, w20
	orr	w9, w9, w10
	orr	w9, w9, w11
	orr	w9, w9, w12
	orr	w9, w9, w13
	orr	w9, w9, w14
	orr	w9, w9, w15
	orr	w20, w9, w8
LBB0_5:
	mov	x0, x19
	mov	w1, #4
	bl	_intel_ring_begin
	cbnz	w0, LBB0_7
; %bb.6:
	add	w21, w22, #128
	mov	w0, #4
	bl	_GFX_OP_PIPE_CONTROL
	mov	x1, x0
	mov	x0, x19
	bl	_intel_ring_emit
	mov	x0, x19
	mov	x1, x20
	bl	_intel_ring_emit
Lloh29:
	adrp	x8, _PIPE_CONTROL_GLOBAL_GTT@GOTPAGE
Lloh30:
	ldr	x8, [x8, _PIPE_CONTROL_GLOBAL_GTT@GOTPAGEOFF]
Lloh31:
	ldr	w8, [x8]
	orr	w1, w8, w21
	mov	x0, x19
	bl	_intel_ring_emit
	mov	x0, x19
	mov	w1, #0
	bl	_intel_ring_emit
	mov	x0, x19
	bl	_intel_ring_advance
	mov	w0, #0
LBB0_7:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.cfi_endproc
                                        ; -- End function
	.comm	_PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH,4,2 ; @PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
	.comm	_PIPE_CONTROL_DEPTH_CACHE_FLUSH,4,2 ; @PIPE_CONTROL_DEPTH_CACHE_FLUSH
	.comm	_PIPE_CONTROL_CS_STALL,4,2      ; @PIPE_CONTROL_CS_STALL
	.comm	_PIPE_CONTROL_TLB_INVALIDATE,4,2 ; @PIPE_CONTROL_TLB_INVALIDATE
	.comm	_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE,4,2 ; @PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
	.comm	_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE,4,2 ; @PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
	.comm	_PIPE_CONTROL_VF_CACHE_INVALIDATE,4,2 ; @PIPE_CONTROL_VF_CACHE_INVALIDATE
	.comm	_PIPE_CONTROL_CONST_CACHE_INVALIDATE,4,2 ; @PIPE_CONTROL_CONST_CACHE_INVALIDATE
	.comm	_PIPE_CONTROL_STATE_CACHE_INVALIDATE,4,2 ; @PIPE_CONTROL_STATE_CACHE_INVALIDATE
	.comm	_PIPE_CONTROL_QW_WRITE,4,2      ; @PIPE_CONTROL_QW_WRITE
	.comm	_PIPE_CONTROL_GLOBAL_GTT,4,2    ; @PIPE_CONTROL_GLOBAL_GTT
	.no_dead_strip	_gen6_render_ring_flush
.subsections_via_symbols
