	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function set_default_state
_set_default_state:                     ## @set_default_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$88, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_RADEON_FAMILY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rdi, -120(%rbp)                ## 8-byte Spill
	andl	(%rdi), %ecx
	movl	$16, %eax
	movl	$32, %r11d
	movl	$40, %r10d
	movl	$4, %r8d
	xorl	%r12d, %r12d
	leal	-128(%rcx), %esi
	cmpl	$11, %esi
	ja	LBB0_2
## %bb.1:
	movl	$144, %r14d
	movl	$192, -52(%rbp)                 ## 4-byte Folded Spill
	movl	$56, -48(%rbp)                  ## 4-byte Folded Spill
	movl	$136, %r9d
	movl	$48, -56(%rbp)                  ## 4-byte Folded Spill
	movl	$128, %r15d
	leaq	LJTI0_0(%rip), %rdi
	movslq	(%rdi,%rsi,4), %rdx
	addq	%rdi, %rdx
	movl	$40, %esi
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	movl	$0, -44(%rbp)                   ## 4-byte Folded Spill
	movl	$0, -60(%rbp)                   ## 4-byte Folded Spill
	xorl	%r13d, %r13d
	jmpq	*%rdx
LBB0_5:
	movl	$128, %r10d
	xorl	%r8d, %r8d
	movl	$60, %esi
	movl	$188, %r14d
	xorl	%r11d, %r11d
	xorl	%eax, %eax
	jmp	LBB0_6
LBB0_4:
	movl	$188, %r9d
	movl	$60, -56(%rbp)                  ## 4-byte Folded Spill
	movl	$256, %r15d                     ## imm = 0x100
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	xorl	%r8d, %r8d
	jmp	LBB0_9
LBB0_3:
	movl	$144, -52(%rbp)                 ## 4-byte Folded Spill
	movl	$40, %r15d
	movl	$32, %edi
	movl	$16, %ebx
	movl	$40, -48(%rbp)                  ## 4-byte Folded Spill
	jmp	LBB0_9
LBB0_2:
	movl	$48, %esi
	movl	$136, %r14d
LBB0_6:
	leal	-135(%rcx), %edx
	cmpl	$4, %edx
	jae	LBB0_8
## %bb.7:
	movl	$36, -48(%rbp)                  ## 4-byte Folded Spill
	movl	$84, -52(%rbp)                  ## 4-byte Folded Spill
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movl	%r11d, -60(%rbp)                ## 4-byte Spill
	movl	%r10d, %r15d
	movl	%r8d, %r13d
	movl	%esi, -56(%rbp)                 ## 4-byte Spill
	jmp	LBB0_10
LBB0_8:
	movl	$36, -48(%rbp)                  ## 4-byte Folded Spill
	movl	$84, -52(%rbp)                  ## 4-byte Folded Spill
	movl	%eax, %ebx
	movl	%r11d, %edi
	movl	%r10d, %r15d
	movl	%esi, -56(%rbp)                 ## 4-byte Spill
	movl	%r14d, %r9d
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movl	%r11d, -60(%rbp)                ## 4-byte Spill
	movl	%r8d, %r13d
	cmpl	$131, %ecx
	je	LBB0_10
LBB0_9:
	movq	_R600_VC_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	%ebx, -44(%rbp)                 ## 4-byte Spill
	movl	%edi, -60(%rbp)                 ## 4-byte Spill
	movl	%r8d, %r13d
	movl	%r9d, %r14d
LBB0_10:
	movl	%r12d, -112(%rbp)               ## 4-byte Spill
	movq	_R600_DX9_CONSTS@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	_R600_ALU_INST_PREFER_VECTOR@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -108(%rbp)                ## 4-byte Spill
	xorl	%edi, %edi
	callq	_R600_PS_PRIO
	movl	%eax, -104(%rbp)                ## 4-byte Spill
	movl	$1, %edi
	callq	_R600_VS_PRIO
	movl	%eax, -100(%rbp)                ## 4-byte Spill
	movl	$2, %edi
	callq	_R600_GS_PRIO
	movl	%eax, -96(%rbp)                 ## 4-byte Spill
	movl	$3, %edi
	callq	_R600_ES_PRIO
	movl	%eax, -92(%rbp)                 ## 4-byte Spill
	movl	-52(%rbp), %edi                 ## 4-byte Reload
	callq	_R600_NUM_PS_GPRS
	movl	%eax, -88(%rbp)                 ## 4-byte Spill
	movl	-48(%rbp), %edi                 ## 4-byte Reload
	callq	_R600_NUM_VS_GPRS
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movl	$4, %edi
	callq	_R600_NUM_CLAUSE_TEMP_GPRS
	movl	%eax, -84(%rbp)                 ## 4-byte Spill
	xorl	%edi, %edi
	callq	_R600_NUM_GS_GPRS
	movl	%eax, -80(%rbp)                 ## 4-byte Spill
	xorl	%edi, %edi
	callq	_R600_NUM_ES_GPRS
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movl	%r14d, %edi
	callq	_R600_NUM_PS_THREADS
	movl	%eax, -76(%rbp)                 ## 4-byte Spill
	movl	-56(%rbp), %edi                 ## 4-byte Reload
	callq	_R600_NUM_VS_THREADS
	movl	%eax, %r14d
	movl	%r13d, %edi
	callq	_R600_NUM_GS_THREADS
	movl	%eax, -72(%rbp)                 ## 4-byte Spill
	movl	%r13d, %edi
	callq	_R600_NUM_ES_THREADS
	movl	%eax, -68(%rbp)                 ## 4-byte Spill
	movl	%r15d, %edi
	callq	_R600_NUM_PS_STACK_ENTRIES
	movl	%eax, -64(%rbp)                 ## 4-byte Spill
	movl	%r15d, %edi
	callq	_R600_NUM_VS_STACK_ENTRIES
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	movl	-60(%rbp), %edi                 ## 4-byte Reload
	callq	_R600_NUM_GS_STACK_ENTRIES
	movl	%eax, -60(%rbp)                 ## 4-byte Spill
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	callq	_R600_NUM_ES_STACK_ENTRIES
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	_RADEON_FAMILY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	-120(%rbp), %rcx                ## 8-byte Reload
	andl	(%rcx), %eax
	cmpl	$128, %eax
	jl	LBB0_14
## %bb.11:
	movq	_r7xx_default_size@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	addl	$10, %edi
	callq	_BEGIN_RING
	cmpl	$0, (%r13)
	jle	LBB0_17
## %bb.12:
	xorl	%ebx, %ebx
	movq	_r7xx_default_state@GOTPCREL(%rip), %r15
	.p2align	4, 0x90
LBB0_13:                                ## =>This Inner Loop Header: Depth=1
	movq	(%r15), %rax
	movl	(%rax,%rbx,4), %edi
	callq	_OUT_RING
	incq	%rbx
	movslq	(%r13), %rax
	cmpq	%rax, %rbx
	jl	LBB0_13
	jmp	LBB0_17
LBB0_14:
	movq	_r6xx_default_size@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	addl	$10, %edi
	callq	_BEGIN_RING
	cmpl	$0, (%r13)
	jle	LBB0_17
## %bb.15:
	xorl	%ebx, %ebx
	movq	_r6xx_default_state@GOTPCREL(%rip), %r15
	.p2align	4, 0x90
LBB0_16:                                ## =>This Inner Loop Header: Depth=1
	movq	(%r15), %rax
	movl	(%rax,%rbx,4), %edi
	callq	_OUT_RING
	incq	%rbx
	movslq	(%r13), %rax
	cmpq	%rax, %rbx
	jl	LBB0_16
LBB0_17:
	movl	-60(%rbp), %eax                 ## 4-byte Reload
	orl	%eax, -44(%rbp)                 ## 4-byte Folded Spill
	movl	-56(%rbp), %r13d                ## 4-byte Reload
	orl	-64(%rbp), %r13d                ## 4-byte Folded Reload
	orl	-76(%rbp), %r14d                ## 4-byte Folded Reload
	orl	-72(%rbp), %r14d                ## 4-byte Folded Reload
	orl	-68(%rbp), %r14d                ## 4-byte Folded Reload
	movl	-48(%rbp), %r15d                ## 4-byte Reload
	orl	-80(%rbp), %r15d                ## 4-byte Folded Reload
	movl	-52(%rbp), %ebx                 ## 4-byte Reload
	orl	-88(%rbp), %ebx                 ## 4-byte Folded Reload
	orl	-84(%rbp), %ebx                 ## 4-byte Folded Reload
	orl	-112(%rbp), %r12d               ## 4-byte Folded Reload
	orl	-108(%rbp), %r12d               ## 4-byte Folded Reload
	orl	-104(%rbp), %r12d               ## 4-byte Folded Reload
	orl	-100(%rbp), %r12d               ## 4-byte Folded Reload
	orl	-96(%rbp), %r12d                ## 4-byte Folded Reload
	orl	-92(%rbp), %r12d                ## 4-byte Folded Reload
	movq	_R600_IT_EVENT_WRITE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_CP_PACKET3
	movl	%eax, %edi
	callq	_OUT_RING
	movq	_R600_CACHE_FLUSH_AND_INV_EVENT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_OUT_RING
	movq	_R600_IT_SET_CONFIG_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$6, %esi
	callq	_CP_PACKET3
	movl	%eax, %edi
	callq	_OUT_RING
	movq	_R600_SQ_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_R600_SET_CONFIG_REG_OFFSET@GOTPCREL(%rip), %rax
	subl	(%rax), %edi
	sarl	$2, %edi
	callq	_OUT_RING
	movl	%r12d, %edi
	callq	_OUT_RING
	movl	%ebx, %edi
	callq	_OUT_RING
	movl	%r15d, %edi
	callq	_OUT_RING
	movl	%r14d, %edi
	callq	_OUT_RING
	movl	%r13d, %edi
	callq	_OUT_RING
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	callq	_OUT_RING
	xorl	%eax, %eax
	addq	$88, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_ADVANCE_RING                   ## TAILCALL
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_4, LBB0_4-LJTI0_0
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_10, LBB0_10-LJTI0_0
.set L0_0_set_3, LBB0_3-LJTI0_0
.set L0_0_set_6, LBB0_6-LJTI0_0
.set L0_0_set_2, LBB0_2-LJTI0_0
.set L0_0_set_9, LBB0_9-LJTI0_0
LJTI0_0:
	.long	L0_0_set_4
	.long	L0_0_set_5
	.long	L0_0_set_5
	.long	L0_0_set_10
	.long	L0_0_set_3
	.long	L0_0_set_6
	.long	L0_0_set_6
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_9
	.end_data_region
                                        ## -- End function
	.comm	_RING_LOCALS,4,2                ## @RING_LOCALS
	.comm	_RADEON_FAMILY_MASK,4,2         ## @RADEON_FAMILY_MASK
	.comm	_R600_VC_ENABLE,4,2             ## @R600_VC_ENABLE
	.comm	_R600_DX9_CONSTS,4,2            ## @R600_DX9_CONSTS
	.comm	_R600_ALU_INST_PREFER_VECTOR,4,2 ## @R600_ALU_INST_PREFER_VECTOR
	.comm	_r7xx_default_size,4,2          ## @r7xx_default_size
	.comm	_r7xx_default_state,8,3         ## @r7xx_default_state
	.comm	_r6xx_default_size,4,2          ## @r6xx_default_size
	.comm	_r6xx_default_state,8,3         ## @r6xx_default_state
	.comm	_R600_IT_EVENT_WRITE,4,2        ## @R600_IT_EVENT_WRITE
	.comm	_R600_CACHE_FLUSH_AND_INV_EVENT,4,2 ## @R600_CACHE_FLUSH_AND_INV_EVENT
	.comm	_R600_IT_SET_CONFIG_REG,4,2     ## @R600_IT_SET_CONFIG_REG
	.comm	_R600_SQ_CONFIG,4,2             ## @R600_SQ_CONFIG
	.comm	_R600_SET_CONFIG_REG_OFFSET,4,2 ## @R600_SET_CONFIG_REG_OFFSET
	.no_dead_strip	_set_default_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function set_default_state
_set_default_state:                     ; @set_default_state
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #160
	.cfi_def_cfa_offset 160
	stp	x28, x27, [sp, #64]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #80]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #96]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #112]            ; 16-byte Folded Spill
	stp	x20, x19, [sp, #128]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #144]            ; 16-byte Folded Spill
	add	x29, sp, #144
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x26, x0
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _RADEON_FAMILY_MASK@GOTPAGE
Lloh1:
	ldr	x9, [x9, _RADEON_FAMILY_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	and	w9, w9, w8
	sub	w16, w9, #128
	cmp	w16, #11
	b.hi	LBB0_5
; %bb.1:
	mov	w11, #0
	mov	w10, #0
	mov	w23, #0
	mov	w25, #0
	mov	w28, #0
	mov	w2, #0
	mov	w12, #16
	mov	w13, #32
	mov	w15, #40
	mov	w24, #144
	mov	w21, #192
	mov	w27, #56
	mov	w14, #136
	mov	w22, #48
	mov	w8, #4
	mov	w20, #128
Lloh3:
	adrp	x17, lJTI0_0@PAGE
Lloh4:
	add	x17, x17, lJTI0_0@PAGEOFF
	adr	x0, LBB0_2
	ldrb	w1, [x17, x16]
	add	x0, x0, x1, lsl #2
	mov	w16, #40
	br	x0
LBB0_2:
	mov	w8, #0
	mov	w13, #0
	mov	w12, #0
	mov	w16, #128
	mov	w15, #60
	mov	w24, #188
	b	LBB0_6
LBB0_3:
	mov	w11, #0
	mov	w10, #0
	mov	w8, #0
	mov	w21, #192
	mov	w27, #56
	mov	w14, #188
	mov	w22, #60
	mov	w20, #256
	b	LBB0_9
LBB0_4:
	mov	w21, #144
	mov	w14, #136
	mov	w22, #48
	mov	w8, #4
	mov	w20, #40
	mov	w10, #32
	mov	w11, #16
	mov	w27, #40
	b	LBB0_9
LBB0_5:
	mov	w12, #16
	mov	w13, #32
	mov	w16, #40
	mov	w8, #4
	mov	w15, #48
	mov	w24, #136
LBB0_6:
	mov	w2, #0
	mov	w21, #84
	mov	w27, #36
	sub	w10, w9, #135
	cmp	w10, #4
	b.hs	LBB0_8
; %bb.7:
	mov	x23, x12
	mov	x25, x13
	mov	x20, x16
	mov	x28, x8
	mov	x22, x15
	b	LBB0_10
LBB0_8:
	mov	x11, x12
	mov	x10, x13
	mov	x20, x16
	mov	x22, x15
	mov	x14, x24
	mov	x23, x12
	mov	x25, x13
	mov	x28, x8
	cmp	w9, #131
	b.eq	LBB0_10
LBB0_9:
Lloh5:
	adrp	x9, _R600_VC_ENABLE@GOTPAGE
Lloh6:
	ldr	x9, [x9, _R600_VC_ENABLE@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x9]
	mov	x23, x11
	mov	x25, x10
	mov	x28, x8
	mov	x24, x14
LBB0_10:
	str	w2, [sp, #60]                   ; 4-byte Folded Spill
Lloh8:
	adrp	x8, _R600_DX9_CONSTS@GOTPAGE
Lloh9:
	ldr	x8, [x8, _R600_DX9_CONSTS@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	str	w8, [sp, #56]                   ; 4-byte Folded Spill
Lloh11:
	adrp	x8, _R600_ALU_INST_PREFER_VECTOR@GOTPAGE
Lloh12:
	ldr	x8, [x8, _R600_ALU_INST_PREFER_VECTOR@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
	str	w8, [sp, #52]                   ; 4-byte Folded Spill
	mov	w0, #0
	bl	_R600_PS_PRIO
	str	w0, [sp, #48]                   ; 4-byte Folded Spill
	mov	w0, #1
	bl	_R600_VS_PRIO
	str	w0, [sp, #44]                   ; 4-byte Folded Spill
	mov	w0, #2
	bl	_R600_GS_PRIO
	str	w0, [sp, #40]                   ; 4-byte Folded Spill
	mov	w0, #3
	bl	_R600_ES_PRIO
	str	w0, [sp, #36]                   ; 4-byte Folded Spill
	mov	x0, x21
	bl	_R600_NUM_PS_GPRS
	str	w0, [sp, #32]                   ; 4-byte Folded Spill
	mov	x0, x27
	bl	_R600_NUM_VS_GPRS
	str	w0, [sp, #28]                   ; 4-byte Folded Spill
	mov	w0, #4
	bl	_R600_NUM_CLAUSE_TEMP_GPRS
	str	w0, [sp, #24]                   ; 4-byte Folded Spill
	mov	w0, #0
	bl	_R600_NUM_GS_GPRS
	str	w0, [sp, #20]                   ; 4-byte Folded Spill
	mov	w0, #0
	bl	_R600_NUM_ES_GPRS
	str	w0, [sp, #16]                   ; 4-byte Folded Spill
	mov	x0, x24
	bl	_R600_NUM_PS_THREADS
	str	w0, [sp, #12]                   ; 4-byte Folded Spill
	mov	x0, x22
	bl	_R600_NUM_VS_THREADS
	mov	x22, x0
	mov	x0, x28
	bl	_R600_NUM_GS_THREADS
	mov	x27, x0
	mov	x0, x28
	bl	_R600_NUM_ES_THREADS
	mov	x28, x0
	mov	x0, x20
	bl	_R600_NUM_PS_STACK_ENTRIES
	mov	x19, x0
	mov	x0, x20
	bl	_R600_NUM_VS_STACK_ENTRIES
	mov	x20, x0
	mov	x0, x25
	bl	_R600_NUM_GS_STACK_ENTRIES
	mov	x25, x0
	mov	x0, x23
	bl	_R600_NUM_ES_STACK_ENTRIES
	mov	x23, x0
	ldr	w8, [x26]
Lloh14:
	adrp	x9, _RADEON_FAMILY_MASK@GOTPAGE
Lloh15:
	ldr	x9, [x9, _RADEON_FAMILY_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
	and	w8, w9, w8
	cmp	w8, #128
	b.lt	LBB0_14
; %bb.11:
Lloh17:
	adrp	x26, _r7xx_default_size@GOTPAGE
Lloh18:
	ldr	x26, [x26, _r7xx_default_size@GOTPAGEOFF]
	ldr	w8, [x26]
	add	w0, w8, #10
	bl	_BEGIN_RING
	ldr	w8, [x26]
	cmp	w8, #1
	b.lt	LBB0_17
; %bb.12:
	mov	x21, #0
Lloh19:
	adrp	x24, _r7xx_default_state@GOTPAGE
Lloh20:
	ldr	x24, [x24, _r7xx_default_state@GOTPAGEOFF]
LBB0_13:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x24]
	ldr	w0, [x8, x21, lsl #2]
	bl	_OUT_RING
	add	x21, x21, #1
	ldrsw	x8, [x26]
	cmp	x21, x8
	b.lt	LBB0_13
	b	LBB0_17
LBB0_14:
Lloh21:
	adrp	x26, _r6xx_default_size@GOTPAGE
Lloh22:
	ldr	x26, [x26, _r6xx_default_size@GOTPAGEOFF]
	ldr	w8, [x26]
	add	w0, w8, #10
	bl	_BEGIN_RING
	ldr	w8, [x26]
	cmp	w8, #1
	b.lt	LBB0_17
; %bb.15:
	mov	x21, #0
Lloh23:
	adrp	x24, _r6xx_default_state@GOTPAGE
Lloh24:
	ldr	x24, [x24, _r6xx_default_state@GOTPAGEOFF]
LBB0_16:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x24]
	ldr	w0, [x8, x21, lsl #2]
	bl	_OUT_RING
	add	x21, x21, #1
	ldrsw	x8, [x26]
	cmp	x21, x8
	b.lt	LBB0_16
LBB0_17:
	orr	w23, w23, w25
	orr	w19, w20, w19
	ldp	w8, w9, [sp, #12]               ; 8-byte Folded Reload
	orr	w8, w22, w8
	orr	w8, w8, w27
	orr	w20, w8, w28
	ldr	w8, [sp, #20]                   ; 4-byte Folded Reload
	orr	w21, w9, w8
	ldp	w9, w8, [sp, #28]               ; 8-byte Folded Reload
	orr	w8, w9, w8
	ldr	w9, [sp, #24]                   ; 4-byte Folded Reload
	orr	w22, w8, w9
	ldp	w9, w8, [sp, #56]               ; 8-byte Folded Reload
	orr	w8, w9, w8
	ldr	w9, [sp, #52]                   ; 4-byte Folded Reload
	orr	w8, w8, w9
	ldr	w9, [sp, #48]                   ; 4-byte Folded Reload
	orr	w8, w8, w9
	ldr	w9, [sp, #44]                   ; 4-byte Folded Reload
	orr	w8, w8, w9
	ldr	w9, [sp, #40]                   ; 4-byte Folded Reload
	orr	w8, w8, w9
	ldr	w9, [sp, #36]                   ; 4-byte Folded Reload
	orr	w24, w8, w9
Lloh25:
	adrp	x8, _R600_IT_EVENT_WRITE@GOTPAGE
Lloh26:
	ldr	x8, [x8, _R600_IT_EVENT_WRITE@GOTPAGEOFF]
Lloh27:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_CP_PACKET3
	bl	_OUT_RING
Lloh28:
	adrp	x8, _R600_CACHE_FLUSH_AND_INV_EVENT@GOTPAGE
Lloh29:
	ldr	x8, [x8, _R600_CACHE_FLUSH_AND_INV_EVENT@GOTPAGEOFF]
Lloh30:
	ldr	w0, [x8]
	bl	_OUT_RING
Lloh31:
	adrp	x8, _R600_IT_SET_CONFIG_REG@GOTPAGE
Lloh32:
	ldr	x8, [x8, _R600_IT_SET_CONFIG_REG@GOTPAGEOFF]
Lloh33:
	ldr	w0, [x8]
	mov	w1, #6
	bl	_CP_PACKET3
	bl	_OUT_RING
Lloh34:
	adrp	x8, _R600_SQ_CONFIG@GOTPAGE
Lloh35:
	ldr	x8, [x8, _R600_SQ_CONFIG@GOTPAGEOFF]
Lloh36:
	ldr	w8, [x8]
Lloh37:
	adrp	x9, _R600_SET_CONFIG_REG_OFFSET@GOTPAGE
Lloh38:
	ldr	x9, [x9, _R600_SET_CONFIG_REG_OFFSET@GOTPAGEOFF]
Lloh39:
	ldr	w9, [x9]
	sub	w8, w8, w9
	asr	w0, w8, #2
	bl	_OUT_RING
	mov	x0, x24
	bl	_OUT_RING
	mov	x0, x22
	bl	_OUT_RING
	mov	x0, x21
	bl	_OUT_RING
	mov	x0, x20
	bl	_OUT_RING
	mov	x0, x19
	bl	_OUT_RING
	mov	x0, x23
	bl	_OUT_RING
	ldp	x29, x30, [sp, #144]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #128]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #112]            ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #96]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #80]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #64]             ; 16-byte Folded Reload
	add	sp, sp, #160
	b	_ADVANCE_RING
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_3-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_10-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_6-LBB0_2)>>2
	.byte	(LBB0_6-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_9-LBB0_2)>>2
                                        ; -- End function
	.comm	_RING_LOCALS,4,2                ; @RING_LOCALS
	.comm	_RADEON_FAMILY_MASK,4,2         ; @RADEON_FAMILY_MASK
	.comm	_R600_VC_ENABLE,4,2             ; @R600_VC_ENABLE
	.comm	_R600_DX9_CONSTS,4,2            ; @R600_DX9_CONSTS
	.comm	_R600_ALU_INST_PREFER_VECTOR,4,2 ; @R600_ALU_INST_PREFER_VECTOR
	.comm	_r7xx_default_size,4,2          ; @r7xx_default_size
	.comm	_r7xx_default_state,8,3         ; @r7xx_default_state
	.comm	_r6xx_default_size,4,2          ; @r6xx_default_size
	.comm	_r6xx_default_state,8,3         ; @r6xx_default_state
	.comm	_R600_IT_EVENT_WRITE,4,2        ; @R600_IT_EVENT_WRITE
	.comm	_R600_CACHE_FLUSH_AND_INV_EVENT,4,2 ; @R600_CACHE_FLUSH_AND_INV_EVENT
	.comm	_R600_IT_SET_CONFIG_REG,4,2     ; @R600_IT_SET_CONFIG_REG
	.comm	_R600_SQ_CONFIG,4,2             ; @R600_SQ_CONFIG
	.comm	_R600_SET_CONFIG_REG_OFFSET,4,2 ; @R600_SET_CONFIG_REG_OFFSET
	.no_dead_strip	_set_default_state
.subsections_via_symbols
