	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r100_irq_process               ## -- Begin function r100_irq_process
	.p2align	4, 0x90
_r100_irq_process:                      ## @r100_irq_process
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	callq	_r100_irq_ack
	movq	_IRQ_NONE@GOTPCREL(%rip), %r14
	testl	%eax, %eax
	je	LBB0_26
## %bb.1:
	cmpq	$0, 56(%r15)
	jne	LBB0_26
## %bb.2:
	movl	%eax, %ebx
	leaq	32(%r15), %r14
	xorl	%r13d, %r13d
	movq	_RADEON_FP2_DETECT_STAT@GOTPCREL(%rip), %r12
	jmp	LBB0_3
	.p2align	4, 0x90
LBB0_18:                                ##   in Loop: Header=BB0_3 Depth=1
	movq	%r15, %rdi
	callq	_r100_irq_ack
	movl	%eax, %ebx
	testl	%eax, %eax
	je	LBB0_19
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movq	_RADEON_SW_INT_TEST@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_5
## %bb.4:                               ##   in Loop: Header=BB0_3 Depth=1
	movq	_RADEON_RING_TYPE_GFX_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_radeon_fence_process
LBB0_5:                                 ##   in Loop: Header=BB0_3 Depth=1
	movq	_RADEON_CRTC_VBLANK_STAT@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_10
## %bb.6:                               ##   in Loop: Header=BB0_3 Depth=1
	movq	40(%r15), %rax
	cmpq	$0, (%rax)
	je	LBB0_8
## %bb.7:                               ##   in Loop: Header=BB0_3 Depth=1
	movl	52(%r15), %edi
	xorl	%esi, %esi
	callq	_drm_handle_vblank
	movl	$1, 48(%r15)
	movq	%r14, %rdi
	callq	_wake_up
LBB0_8:                                 ##   in Loop: Header=BB0_3 Depth=1
	movq	24(%r15), %rdi
	callq	_atomic_read
	testq	%rax, %rax
	je	LBB0_10
## %bb.9:                               ##   in Loop: Header=BB0_3 Depth=1
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_radeon_crtc_handle_flip
LBB0_10:                                ##   in Loop: Header=BB0_3 Depth=1
	movq	_RADEON_CRTC2_VBLANK_STAT@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_15
## %bb.11:                              ##   in Loop: Header=BB0_3 Depth=1
	movq	40(%r15), %rax
	cmpq	$0, 8(%rax)
	je	LBB0_13
## %bb.12:                              ##   in Loop: Header=BB0_3 Depth=1
	movl	52(%r15), %edi
	movl	$1, %esi
	callq	_drm_handle_vblank
	movl	$1, 48(%r15)
	movq	%r14, %rdi
	callq	_wake_up
LBB0_13:                                ##   in Loop: Header=BB0_3 Depth=1
	movq	24(%r15), %rdi
	addq	$4, %rdi
	callq	_atomic_read
	testq	%rax, %rax
	je	LBB0_15
## %bb.14:                              ##   in Loop: Header=BB0_3 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	callq	_radeon_crtc_handle_flip
LBB0_15:                                ##   in Loop: Header=BB0_3 Depth=1
	movq	_RADEON_FP_DETECT_STAT@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_17
## %bb.16:                              ##   in Loop: Header=BB0_3 Depth=1
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG
	movl	$1, %r13d
LBB0_17:                                ##   in Loop: Header=BB0_3 Depth=1
	testl	%ebx, (%r12)
	je	LBB0_18
## %bb.27:                              ##   in Loop: Header=BB0_3 Depth=1
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_DEBUG
	movq	%r15, %rdi
	callq	_r100_irq_ack
	movl	%eax, %ebx
	movl	$1, %r13d
	testl	%eax, %eax
	jne	LBB0_3
	jmp	LBB0_20
LBB0_19:
	testl	%r13d, %r13d
	je	LBB0_21
LBB0_20:
	leaq	16(%r15), %rdi
	callq	_schedule_work
LBB0_21:
	movq	_IRQ_HANDLED@GOTPCREL(%rip), %r14
	cmpq	$0, 8(%r15)
	je	LBB0_26
## %bb.22:
	movl	(%r15), %eax
	andl	$-2, %eax
	cmpl	$128, %eax
	jne	LBB0_24
## %bb.23:
	movq	_RADEON_AIC_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32
	movq	_RS400_MSI_REARM@GOTPCREL(%rip), %r12
	movl	(%r12), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	(%r15), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r15), %edi
	orl	(%r12), %ebx
	movl	%ebx, %esi
	jmp	LBB0_25
LBB0_24:
	movq	_RADEON_MSI_REARM_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RV370_MSI_REARM_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
LBB0_25:
	callq	_WREG32
LBB0_26:
	movl	(%r14), %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_IRQ_NONE,4,2                   ## @IRQ_NONE
	.comm	_RADEON_SW_INT_TEST,4,2         ## @RADEON_SW_INT_TEST
	.comm	_RADEON_RING_TYPE_GFX_INDEX,4,2 ## @RADEON_RING_TYPE_GFX_INDEX
	.comm	_RADEON_CRTC_VBLANK_STAT,4,2    ## @RADEON_CRTC_VBLANK_STAT
	.comm	_RADEON_CRTC2_VBLANK_STAT,4,2   ## @RADEON_CRTC2_VBLANK_STAT
	.comm	_RADEON_FP_DETECT_STAT,4,2      ## @RADEON_FP_DETECT_STAT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"HPD1\n"

	.comm	_RADEON_FP2_DETECT_STAT,4,2     ## @RADEON_FP2_DETECT_STAT
L_.str.1:                               ## @.str.1
	.asciz	"HPD2\n"

	.comm	_RADEON_AIC_CNTL,4,2            ## @RADEON_AIC_CNTL
	.comm	_RS400_MSI_REARM,4,2            ## @RS400_MSI_REARM
	.comm	_RADEON_MSI_REARM_EN,4,2        ## @RADEON_MSI_REARM_EN
	.comm	_RV370_MSI_REARM_EN,4,2         ## @RV370_MSI_REARM_EN
	.comm	_IRQ_HANDLED,4,2                ## @IRQ_HANDLED
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r100_irq_process               ; -- Begin function r100_irq_process
	.p2align	2
_r100_irq_process:                      ; @r100_irq_process
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	bl	_r100_irq_ack
	cbz	w0, LBB0_2
; %bb.1:
	ldr	x8, [x19, #56]
	cbz	x8, LBB0_3
LBB0_2:
Lloh0:
	adrp	x8, _IRQ_NONE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _IRQ_NONE@GOTPAGEOFF]
	b	LBB0_29
LBB0_3:
	mov	x21, x0
	mov	w23, #0
Lloh2:
	adrp	x24, _RADEON_SW_INT_TEST@GOTPAGE
Lloh3:
	ldr	x24, [x24, _RADEON_SW_INT_TEST@GOTPAGEOFF]
Lloh4:
	adrp	x25, _RADEON_CRTC_VBLANK_STAT@GOTPAGE
Lloh5:
	ldr	x25, [x25, _RADEON_CRTC_VBLANK_STAT@GOTPAGEOFF]
Lloh6:
	adrp	x26, _RADEON_CRTC2_VBLANK_STAT@GOTPAGE
Lloh7:
	ldr	x26, [x26, _RADEON_CRTC2_VBLANK_STAT@GOTPAGEOFF]
Lloh8:
	adrp	x27, _RADEON_FP_DETECT_STAT@GOTPAGE
Lloh9:
	ldr	x27, [x27, _RADEON_FP_DETECT_STAT@GOTPAGEOFF]
Lloh10:
	adrp	x28, _RADEON_FP2_DETECT_STAT@GOTPAGE
Lloh11:
	ldr	x28, [x28, _RADEON_FP2_DETECT_STAT@GOTPAGEOFF]
	add	x22, x19, #32
	mov	w20, #1
	b	LBB0_5
LBB0_4:                                 ;   in Loop: Header=BB0_5 Depth=1
	mov	x0, x19
	bl	_r100_irq_ack
	mov	x21, x0
	cbz	w0, LBB0_21
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w8, [x24]
	tst	w8, w21
	b.eq	LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
Lloh12:
	adrp	x8, _RADEON_RING_TYPE_GFX_INDEX@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RADEON_RING_TYPE_GFX_INDEX@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_radeon_fence_process
LBB0_7:                                 ;   in Loop: Header=BB0_5 Depth=1
	ldr	w8, [x25]
	tst	w8, w21
	b.eq	LBB0_12
; %bb.8:                                ;   in Loop: Header=BB0_5 Depth=1
	ldr	x8, [x19, #40]
	ldr	x8, [x8]
	cbz	x8, LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_5 Depth=1
	ldr	w0, [x19, #52]
	mov	w1, #0
	bl	_drm_handle_vblank
	str	w20, [x19, #48]
	mov	x0, x22
	bl	_wake_up
LBB0_10:                                ;   in Loop: Header=BB0_5 Depth=1
	ldr	x0, [x19, #24]
	bl	_atomic_read
	cbz	x0, LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_5 Depth=1
	mov	x0, x19
	mov	w1, #0
	bl	_radeon_crtc_handle_flip
LBB0_12:                                ;   in Loop: Header=BB0_5 Depth=1
	ldr	w8, [x26]
	tst	w8, w21
	b.eq	LBB0_17
; %bb.13:                               ;   in Loop: Header=BB0_5 Depth=1
	ldr	x8, [x19, #40]
	ldr	x8, [x8, #8]
	cbz	x8, LBB0_15
; %bb.14:                               ;   in Loop: Header=BB0_5 Depth=1
	ldr	w0, [x19, #52]
	mov	w1, #1
	bl	_drm_handle_vblank
	str	w20, [x19, #48]
	mov	x0, x22
	bl	_wake_up
LBB0_15:                                ;   in Loop: Header=BB0_5 Depth=1
	ldr	x8, [x19, #24]
	add	x0, x8, #4
	bl	_atomic_read
	cbz	x0, LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_5 Depth=1
	mov	x0, x19
	mov	w1, #1
	bl	_radeon_crtc_handle_flip
LBB0_17:                                ;   in Loop: Header=BB0_5 Depth=1
	ldr	w8, [x27]
	tst	w8, w21
	b.eq	LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_5 Depth=1
Lloh15:
	adrp	x0, l_.str@PAGE
Lloh16:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG
	mov	w23, #1
LBB0_19:                                ;   in Loop: Header=BB0_5 Depth=1
	ldr	w8, [x28]
	tst	w8, w21
	b.eq	LBB0_4
; %bb.20:                               ;   in Loop: Header=BB0_5 Depth=1
Lloh17:
	adrp	x0, l_.str.1@PAGE
Lloh18:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_DEBUG
	mov	x0, x19
	bl	_r100_irq_ack
	mov	x21, x0
	mov	w23, #1
	cbnz	w0, LBB0_5
	b	LBB0_22
LBB0_21:
	cbz	w23, LBB0_23
LBB0_22:
	add	x0, x19, #16
	bl	_schedule_work
LBB0_23:
	ldr	x8, [x19, #8]
	cbz	x8, LBB0_28
; %bb.24:
	ldr	w8, [x19]
	and	w8, w8, #0xfffffffe
	cmp	w8, #128
	b.ne	LBB0_26
; %bb.25:
Lloh19:
	adrp	x20, _RADEON_AIC_CNTL@GOTPAGE
Lloh20:
	ldr	x20, [x20, _RADEON_AIC_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh21:
	adrp	x21, _RS400_MSI_REARM@GOTPAGE
Lloh22:
	ldr	x21, [x21, _RS400_MSI_REARM@GOTPAGEOFF]
	ldr	w8, [x21]
	bic	w19, w0, w8
	ldr	w0, [x20]
	mov	x1, x19
	bl	_WREG32
	ldr	w0, [x20]
	ldr	w8, [x21]
	orr	w1, w8, w19
	b	LBB0_27
LBB0_26:
Lloh23:
	adrp	x8, _RADEON_MSI_REARM_EN@GOTPAGE
Lloh24:
	ldr	x8, [x8, _RADEON_MSI_REARM_EN@GOTPAGEOFF]
Lloh25:
	ldr	w0, [x8]
Lloh26:
	adrp	x8, _RV370_MSI_REARM_EN@GOTPAGE
Lloh27:
	ldr	x8, [x8, _RV370_MSI_REARM_EN@GOTPAGEOFF]
Lloh28:
	ldr	w1, [x8]
LBB0_27:
	bl	_WREG32
LBB0_28:
Lloh29:
	adrp	x8, _IRQ_HANDLED@GOTPAGE
Lloh30:
	ldr	x8, [x8, _IRQ_HANDLED@GOTPAGEOFF]
LBB0_29:
	ldr	w0, [x8]
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpAdd	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh29, Lloh30
	.cfi_endproc
                                        ; -- End function
	.comm	_IRQ_NONE,4,2                   ; @IRQ_NONE
	.comm	_RADEON_SW_INT_TEST,4,2         ; @RADEON_SW_INT_TEST
	.comm	_RADEON_RING_TYPE_GFX_INDEX,4,2 ; @RADEON_RING_TYPE_GFX_INDEX
	.comm	_RADEON_CRTC_VBLANK_STAT,4,2    ; @RADEON_CRTC_VBLANK_STAT
	.comm	_RADEON_CRTC2_VBLANK_STAT,4,2   ; @RADEON_CRTC2_VBLANK_STAT
	.comm	_RADEON_FP_DETECT_STAT,4,2      ; @RADEON_FP_DETECT_STAT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"HPD1\n"

	.comm	_RADEON_FP2_DETECT_STAT,4,2     ; @RADEON_FP2_DETECT_STAT
l_.str.1:                               ; @.str.1
	.asciz	"HPD2\n"

	.comm	_RADEON_AIC_CNTL,4,2            ; @RADEON_AIC_CNTL
	.comm	_RS400_MSI_REARM,4,2            ; @RS400_MSI_REARM
	.comm	_RADEON_MSI_REARM_EN,4,2        ; @RADEON_MSI_REARM_EN
	.comm	_RV370_MSI_REARM_EN,4,2         ; @RV370_MSI_REARM_EN
	.comm	_IRQ_HANDLED,4,2                ; @IRQ_HANDLED
.subsections_via_symbols
