	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_emit_veclinear
_radeon_emit_veclinear:                 ## @radeon_emit_veclinear
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r15
	testl	%r15d, %r15d
	je	LBB0_1
## %bb.2:
	movq	%rcx, %r14
	movl	%edx, %r13d
	movl	%r15d, %ebx
	shll	$4, %ebx
	movl	(%rcx), %edi
	callq	_drm_buffer_unprocessed
	cmpl	%eax, %ebx
	jle	LBB0_4
## %bb.3:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r15d, %r15d
	subl	(%rax), %r15d
	jmp	LBB0_5
LBB0_1:
	xorl	%r15d, %r15d
	jmp	LBB0_5
LBB0_4:
	movq	%r15, %rax
	shrq	$32, %rax
	leal	(,%r15,4), %r12d
	shll	$8, %r13d
	orl	%eax, %r13d
	leal	5(%r12), %edi
	callq	_BEGIN_RING
	movq	_RADEON_SE_TCL_STATE_FLUSH@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%r15d, %r15d
	xorl	%esi, %esi
	callq	_OUT_RING_REG
	movq	_RADEON_SE_TCL_VECTOR_INDX_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_CP_PACKET0
	movl	%eax, %edi
	callq	_OUT_RING
	movq	_RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	btsl	%eax, %r13d
	movl	%r13d, %edi
	callq	_OUT_RING
	movq	_RADEON_SE_TCL_VECTOR_DATA_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	leal	-1(%r12), %esi
	callq	_CP_PACKET0_TABLE
	movl	%eax, %edi
	callq	_OUT_RING
	movl	(%r14), %edi
	movl	%r12d, %esi
	callq	_OUT_RING_DRM_BUFFER
	xorl	%eax, %eax
	callq	_ADVANCE_RING
LBB0_5:
	movl	%r15d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RING_LOCALS,4,2                ## @RING_LOCALS
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_RADEON_SE_TCL_STATE_FLUSH,4,2  ## @RADEON_SE_TCL_STATE_FLUSH
	.comm	_RADEON_SE_TCL_VECTOR_INDX_REG,4,2 ## @RADEON_SE_TCL_VECTOR_INDX_REG
	.comm	_RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT,4,2 ## @RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT
	.comm	_RADEON_SE_TCL_VECTOR_DATA_REG,4,2 ## @RADEON_SE_TCL_VECTOR_DATA_REG
	.no_dead_strip	_radeon_emit_veclinear
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_emit_veclinear
_radeon_emit_veclinear:                 ; @radeon_emit_veclinear
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x21, x1
	cbz	w21, LBB0_4
; %bb.1:
	mov	x19, x3
	mov	x20, x2
	ldr	w0, [x3]
	bl	_drm_buffer_unprocessed
	cmp	w0, w21, lsl #4
	b.ge	LBB0_3
; %bb.2:
Lloh0:
	adrp	x8, _EINVAL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_5
LBB0_3:
	lsr	x8, x21, #32
	lsl	w21, w21, #2
	orr	w20, w8, w20, lsl #8
	add	w0, w21, #5
	bl	_BEGIN_RING
Lloh3:
	adrp	x8, _RADEON_SE_TCL_STATE_FLUSH@GOTPAGE
Lloh4:
	ldr	x8, [x8, _RADEON_SE_TCL_STATE_FLUSH@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_OUT_RING_REG
Lloh6:
	adrp	x8, _RADEON_SE_TCL_VECTOR_INDX_REG@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_SE_TCL_VECTOR_INDX_REG@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_CP_PACKET0
	bl	_OUT_RING
Lloh9:
	adrp	x8, _RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT@GOTPAGE
Lloh10:
	ldr	x8, [x8, _RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	mov	w9, #1
	lsl	w8, w9, w8
	orr	w0, w20, w8
	bl	_OUT_RING
Lloh12:
	adrp	x8, _RADEON_SE_TCL_VECTOR_DATA_REG@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RADEON_SE_TCL_VECTOR_DATA_REG@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	sub	w1, w21, #1
	bl	_CP_PACKET0_TABLE
	bl	_OUT_RING
	ldr	w0, [x19]
	mov	x1, x21
	bl	_OUT_RING_DRM_BUFFER
	bl	_ADVANCE_RING
LBB0_4:
	mov	w0, #0
LBB0_5:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_RING_LOCALS,4,2                ; @RING_LOCALS
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_RADEON_SE_TCL_STATE_FLUSH,4,2  ; @RADEON_SE_TCL_STATE_FLUSH
	.comm	_RADEON_SE_TCL_VECTOR_INDX_REG,4,2 ; @RADEON_SE_TCL_VECTOR_INDX_REG
	.comm	_RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT,4,2 ; @RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT
	.comm	_RADEON_SE_TCL_VECTOR_DATA_REG,4,2 ; @RADEON_SE_TCL_VECTOR_DATA_REG
	.no_dead_strip	_radeon_emit_veclinear
.subsections_via_symbols
