	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_pll_wait_for_read_update_complete
_radeon_pll_wait_for_read_update_complete: ## @radeon_pll_wait_for_read_update_complete
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	$9999, %ebx                     ## imm = 0x270F
	movq	_RADEON_PPLL_REF_DIV@GOTPCREL(%rip), %r14
	movq	_RADEON_PPLL_ATOMIC_UPDATE_R@GOTPCREL(%rip), %r15
	.p2align	4, 0x90
LBB0_1:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %edi
	callq	_RREG32_PLL
	subl	$1, %ebx
	setb	%cl
	testl	%eax, (%r15)
	je	LBB0_3
## %bb.2:                               ##   in Loop: Header=BB0_1 Depth=1
	testb	%cl, %cl
	je	LBB0_1
LBB0_3:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_PPLL_REF_DIV,4,2        ## @RADEON_PPLL_REF_DIV
	.comm	_RADEON_PPLL_ATOMIC_UPDATE_R,4,2 ## @RADEON_PPLL_ATOMIC_UPDATE_R
	.no_dead_strip	_radeon_pll_wait_for_read_update_complete
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_pll_wait_for_read_update_complete
_radeon_pll_wait_for_read_update_complete: ; @radeon_pll_wait_for_read_update_complete
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	w19, #9999
Lloh0:
	adrp	x20, _RADEON_PPLL_REF_DIV@GOTPAGE
Lloh1:
	ldr	x20, [x20, _RADEON_PPLL_REF_DIV@GOTPAGEOFF]
Lloh2:
	adrp	x21, _RADEON_PPLL_ATOMIC_UPDATE_R@GOTPAGE
Lloh3:
	ldr	x21, [x21, _RADEON_PPLL_ATOMIC_UPDATE_R@GOTPAGEOFF]
LBB0_1:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x20]
	bl	_RREG32_PLL
	ldr	w8, [x21]
	and	w8, w8, w0
	cmp	w8, #0
	ccmp	w19, #0, #4, ne
	sub	w19, w19, #1
	b.ne	LBB0_1
; %bb.2:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_PPLL_REF_DIV,4,2        ; @RADEON_PPLL_REF_DIV
	.comm	_RADEON_PPLL_ATOMIC_UPDATE_R,4,2 ; @RADEON_PPLL_ATOMIC_UPDATE_R
	.no_dead_strip	_radeon_pll_wait_for_read_update_complete
.subsections_via_symbols
