	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function cayman_pcie_gart_disable
_cayman_pcie_gart_disable:              ## @cayman_pcie_gart_disable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_VM_CONTEXT0_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_VM_CONTEXT1_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_MC_VM_MX_L1_TLB_CNTL@GOTPCREL(%rip), %rax
	movq	_ENABLE_L1_FRAGMENT_PROCESSING@GOTPCREL(%rip), %rcx
	movq	_SYSTEM_ACCESS_MODE_NOT_IN_SYS@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	movl	(%rax), %edi
	movq	_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	callq	_WREG32
	movq	_VM_L2_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPCREL(%rip), %rax
	movq	_ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r12d
	orl	(%rax), %r12d
	movl	$7, %edi
	callq	_EFFECTIVE_L2_QUEUE_SIZE
	movl	%eax, %ebx
	movl	$1, %edi
	callq	_CONTEXT1_IDENTITY_ACCESS_MODE
	orl	%eax, %ebx
	orl	%r12d, %ebx
	movl	%r15d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_VM_L2_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_VM_L2_CNTL3@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_L2_CACHE_BIGK_ASSOCIATIVITY@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$6, %edi
	callq	_L2_CACHE_BIGK_FRAGMENT_SIZE
	orl	%eax, %ebx
	movl	%r15d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	%r14, %rdi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_gart_table_vram_unpin   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_VM_CONTEXT0_CNTL,4,2           ## @VM_CONTEXT0_CNTL
	.comm	_VM_CONTEXT1_CNTL,4,2           ## @VM_CONTEXT1_CNTL
	.comm	_MC_VM_MX_L1_TLB_CNTL,4,2       ## @MC_VM_MX_L1_TLB_CNTL
	.comm	_ENABLE_L1_FRAGMENT_PROCESSING,4,2 ## @ENABLE_L1_FRAGMENT_PROCESSING
	.comm	_SYSTEM_ACCESS_MODE_NOT_IN_SYS,4,2 ## @SYSTEM_ACCESS_MODE_NOT_IN_SYS
	.comm	_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU,4,2 ## @SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
	.comm	_VM_L2_CNTL,4,2                 ## @VM_L2_CNTL
	.comm	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE,4,2 ## @ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE,4,2 ## @ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_VM_L2_CNTL2,4,2                ## @VM_L2_CNTL2
	.comm	_VM_L2_CNTL3,4,2                ## @VM_L2_CNTL3
	.comm	_L2_CACHE_BIGK_ASSOCIATIVITY,4,2 ## @L2_CACHE_BIGK_ASSOCIATIVITY
	.no_dead_strip	_cayman_pcie_gart_disable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cayman_pcie_gart_disable
_cayman_pcie_gart_disable:              ; @cayman_pcie_gart_disable
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, _VM_CONTEXT0_CNTL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _VM_CONTEXT0_CNTL@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh3:
	adrp	x8, _VM_CONTEXT1_CNTL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _VM_CONTEXT1_CNTL@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh6:
	adrp	x8, _MC_VM_MX_L1_TLB_CNTL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _MC_VM_MX_L1_TLB_CNTL@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
Lloh9:
	adrp	x8, _ENABLE_L1_FRAGMENT_PROCESSING@GOTPAGE
Lloh10:
	ldr	x8, [x8, _ENABLE_L1_FRAGMENT_PROCESSING@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
Lloh12:
	adrp	x9, _SYSTEM_ACCESS_MODE_NOT_IN_SYS@GOTPAGE
Lloh13:
	ldr	x9, [x9, _SYSTEM_ACCESS_MODE_NOT_IN_SYS@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh15:
	adrp	x9, _SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU@GOTPAGE
Lloh16:
	ldr	x9, [x9, _SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	orr	w1, w8, w9
	bl	_WREG32
Lloh18:
	adrp	x8, _VM_L2_CNTL@GOTPAGE
Lloh19:
	ldr	x8, [x8, _VM_L2_CNTL@GOTPAGEOFF]
Lloh20:
	adrp	x9, _ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGE
Lloh21:
	ldr	x9, [x9, _ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGEOFF]
Lloh22:
	ldr	w20, [x8]
Lloh23:
	ldr	w8, [x9]
Lloh24:
	adrp	x9, _ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGE
Lloh25:
	ldr	x9, [x9, _ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	orr	w21, w9, w8
	mov	w0, #7
	bl	_EFFECTIVE_L2_QUEUE_SIZE
	orr	w21, w21, w0
	mov	w0, #1
	bl	_CONTEXT1_IDENTITY_ACCESS_MODE
	orr	w1, w21, w0
	mov	x0, x20
	bl	_WREG32
Lloh27:
	adrp	x8, _VM_L2_CNTL2@GOTPAGE
Lloh28:
	ldr	x8, [x8, _VM_L2_CNTL2@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh30:
	adrp	x8, _VM_L2_CNTL3@GOTPAGE
Lloh31:
	ldr	x8, [x8, _VM_L2_CNTL3@GOTPAGEOFF]
Lloh32:
	ldr	w20, [x8]
Lloh33:
	adrp	x8, _L2_CACHE_BIGK_ASSOCIATIVITY@GOTPAGE
Lloh34:
	ldr	x8, [x8, _L2_CACHE_BIGK_ASSOCIATIVITY@GOTPAGEOFF]
Lloh35:
	ldr	w21, [x8]
	mov	w0, #6
	bl	_L2_CACHE_BIGK_FRAGMENT_SIZE
	orr	w1, w0, w21
	mov	x0, x20
	bl	_WREG32
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_radeon_gart_table_vram_unpin
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh22
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_VM_CONTEXT0_CNTL,4,2           ; @VM_CONTEXT0_CNTL
	.comm	_VM_CONTEXT1_CNTL,4,2           ; @VM_CONTEXT1_CNTL
	.comm	_MC_VM_MX_L1_TLB_CNTL,4,2       ; @MC_VM_MX_L1_TLB_CNTL
	.comm	_ENABLE_L1_FRAGMENT_PROCESSING,4,2 ; @ENABLE_L1_FRAGMENT_PROCESSING
	.comm	_SYSTEM_ACCESS_MODE_NOT_IN_SYS,4,2 ; @SYSTEM_ACCESS_MODE_NOT_IN_SYS
	.comm	_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU,4,2 ; @SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
	.comm	_VM_L2_CNTL,4,2                 ; @VM_L2_CNTL
	.comm	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE,4,2 ; @ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE,4,2 ; @ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_VM_L2_CNTL2,4,2                ; @VM_L2_CNTL2
	.comm	_VM_L2_CNTL3,4,2                ; @VM_L2_CNTL3
	.comm	_L2_CACHE_BIGK_ASSOCIATIVITY,4,2 ; @L2_CACHE_BIGK_ASSOCIATIVITY
	.no_dead_strip	_cayman_pcie_gart_disable
.subsections_via_symbols
