	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_cp_discard_buffer       ## -- Begin function radeon_cp_discard_buffer
	.p2align	4, 0x90
_radeon_cp_discard_buffer:              ## @radeon_cp_discard_buffer
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdx, %r14
	movq	(%rdi), %rax
	movq	(%rsi), %rcx
	movq	16(%rdx), %rbx
	movq	(%rcx), %rcx
	movq	(%rcx), %rdx
	incq	%rdx
	movq	%rdx, (%rcx)
	movq	%rdx, (%rbx)
	movq	_RADEON_FAMILY_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	(%rax), %ecx
	movq	_CHIP_R600@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ecx
	jge	LBB0_1
## %bb.2:
	movl	$2, %edi
	callq	_BEGIN_RING
	movq	(%rbx), %rdi
	callq	_RADEON_DISPATCH_AGE
	jmp	LBB0_3
LBB0_1:
	movl	$3, %edi
	callq	_BEGIN_RING
	movq	(%rbx), %rdi
	callq	_R600_DISPATCH_AGE
LBB0_3:
	xorl	%eax, %eax
	callq	_ADVANCE_RING
	movl	$1, (%r14)
	movq	$0, 8(%r14)
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RING_LOCALS,4,2                ## @RING_LOCALS
	.comm	_RADEON_FAMILY_MASK,4,2         ## @RADEON_FAMILY_MASK
	.comm	_CHIP_R600,4,2                  ## @CHIP_R600
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_cp_discard_buffer       ; -- Begin function radeon_cp_discard_buffer
	.p2align	2
_radeon_cp_discard_buffer:              ; @radeon_cp_discard_buffer
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x2
	ldr	x8, [x0]
	ldr	x9, [x1]
	ldr	x20, [x2, #16]
	ldr	x9, [x9]
	ldr	x10, [x9]
	add	x10, x10, #1
	str	x10, [x9]
	str	x10, [x20]
	ldr	w8, [x8]
Lloh0:
	adrp	x9, _RADEON_FAMILY_MASK@GOTPAGE
Lloh1:
	ldr	x9, [x9, _RADEON_FAMILY_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	and	w8, w9, w8
Lloh3:
	adrp	x9, _CHIP_R600@GOTPAGE
Lloh4:
	ldr	x9, [x9, _CHIP_R600@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ge	LBB0_2
; %bb.1:
	mov	w0, #2
	bl	_BEGIN_RING
	ldr	x0, [x20]
	bl	_RADEON_DISPATCH_AGE
	b	LBB0_3
LBB0_2:
	mov	w0, #3
	bl	_BEGIN_RING
	ldr	x0, [x20]
	bl	_R600_DISPATCH_AGE
LBB0_3:
	bl	_ADVANCE_RING
	mov	w8, #1
	str	w8, [x19]
	str	xzr, [x19, #8]
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_RING_LOCALS,4,2                ; @RING_LOCALS
	.comm	_RADEON_FAMILY_MASK,4,2         ; @RADEON_FAMILY_MASK
	.comm	_CHIP_R600,4,2                  ; @CHIP_R600
.subsections_via_symbols
