	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_combios_encoder_crtc_scratch_regs ## -- Begin function radeon_combios_encoder_crtc_scratch_regs
	.p2align	4, 0x90
_radeon_combios_encoder_crtc_scratch_regs: ## @radeon_combios_encoder_crtc_scratch_regs
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	callq	_to_radeon_encoder
	movq	%rax, %rbx
	movq	_RADEON_BIOS_5_SCRATCH@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32
	movl	(%rbx), %edx
	movq	_ATOM_DEVICE_TV1_SUPPORT@GOTPCREL(%rip), %rcx
	testl	%edx, (%rcx)
	je	LBB0_2
## %bb.1:
	movq	_RADEON_TV1_CRTC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%ecx, %eax
	movq	_RADEON_TV1_CRTC_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	%r14d, %esi
	shll	%cl, %esi
	orl	%esi, %eax
LBB0_2:
	movq	_ATOM_DEVICE_CRT1_SUPPORT@GOTPCREL(%rip), %rcx
	testl	%edx, (%rcx)
	je	LBB0_4
## %bb.3:
	movq	_RADEON_CRT1_CRTC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%ecx, %eax
	movq	_RADEON_CRT1_CRTC_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	%r14d, %esi
	shll	%cl, %esi
	orl	%esi, %eax
LBB0_4:
	movq	_ATOM_DEVICE_CRT2_SUPPORT@GOTPCREL(%rip), %rcx
	testl	%edx, (%rcx)
	je	LBB0_6
## %bb.5:
	movq	_RADEON_CRT2_CRTC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%ecx, %eax
	movq	_RADEON_CRT2_CRTC_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	%r14d, %esi
	shll	%cl, %esi
	orl	%esi, %eax
LBB0_6:
	movq	_ATOM_DEVICE_LCD1_SUPPORT@GOTPCREL(%rip), %rcx
	testl	%edx, (%rcx)
	je	LBB0_8
## %bb.7:
	movq	_RADEON_LCD1_CRTC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%ecx, %eax
	movq	_RADEON_LCD1_CRTC_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	%r14d, %esi
	shll	%cl, %esi
	orl	%esi, %eax
LBB0_8:
	movq	_ATOM_DEVICE_DFP1_SUPPORT@GOTPCREL(%rip), %rcx
	testl	%edx, (%rcx)
	je	LBB0_10
## %bb.9:
	movq	_RADEON_DFP1_CRTC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%ecx, %eax
	movq	_RADEON_DFP1_CRTC_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	%r14d, %esi
	shll	%cl, %esi
	orl	%esi, %eax
LBB0_10:
	movq	_ATOM_DEVICE_DFP2_SUPPORT@GOTPCREL(%rip), %rcx
	testl	%edx, (%rcx)
	je	LBB0_12
## %bb.11:
	movq	_RADEON_DFP2_CRTC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%ecx, %eax
	movq	_RADEON_DFP2_CRTC_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r14d
	orl	%r14d, %eax
LBB0_12:
	movl	(%r15), %edi
	movl	%eax, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_BIOS_5_SCRATCH,4,2      ## @RADEON_BIOS_5_SCRATCH
	.comm	_ATOM_DEVICE_TV1_SUPPORT,4,2    ## @ATOM_DEVICE_TV1_SUPPORT
	.comm	_RADEON_TV1_CRTC_MASK,4,2       ## @RADEON_TV1_CRTC_MASK
	.comm	_RADEON_TV1_CRTC_SHIFT,4,2      ## @RADEON_TV1_CRTC_SHIFT
	.comm	_ATOM_DEVICE_CRT1_SUPPORT,4,2   ## @ATOM_DEVICE_CRT1_SUPPORT
	.comm	_RADEON_CRT1_CRTC_MASK,4,2      ## @RADEON_CRT1_CRTC_MASK
	.comm	_RADEON_CRT1_CRTC_SHIFT,4,2     ## @RADEON_CRT1_CRTC_SHIFT
	.comm	_ATOM_DEVICE_CRT2_SUPPORT,4,2   ## @ATOM_DEVICE_CRT2_SUPPORT
	.comm	_RADEON_CRT2_CRTC_MASK,4,2      ## @RADEON_CRT2_CRTC_MASK
	.comm	_RADEON_CRT2_CRTC_SHIFT,4,2     ## @RADEON_CRT2_CRTC_SHIFT
	.comm	_ATOM_DEVICE_LCD1_SUPPORT,4,2   ## @ATOM_DEVICE_LCD1_SUPPORT
	.comm	_RADEON_LCD1_CRTC_MASK,4,2      ## @RADEON_LCD1_CRTC_MASK
	.comm	_RADEON_LCD1_CRTC_SHIFT,4,2     ## @RADEON_LCD1_CRTC_SHIFT
	.comm	_ATOM_DEVICE_DFP1_SUPPORT,4,2   ## @ATOM_DEVICE_DFP1_SUPPORT
	.comm	_RADEON_DFP1_CRTC_MASK,4,2      ## @RADEON_DFP1_CRTC_MASK
	.comm	_RADEON_DFP1_CRTC_SHIFT,4,2     ## @RADEON_DFP1_CRTC_SHIFT
	.comm	_ATOM_DEVICE_DFP2_SUPPORT,4,2   ## @ATOM_DEVICE_DFP2_SUPPORT
	.comm	_RADEON_DFP2_CRTC_MASK,4,2      ## @RADEON_DFP2_CRTC_MASK
	.comm	_RADEON_DFP2_CRTC_SHIFT,4,2     ## @RADEON_DFP2_CRTC_SHIFT
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_combios_encoder_crtc_scratch_regs ; -- Begin function radeon_combios_encoder_crtc_scratch_regs
	.p2align	2
_radeon_combios_encoder_crtc_scratch_regs: ; @radeon_combios_encoder_crtc_scratch_regs
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x1
	bl	_to_radeon_encoder
	mov	x20, x0
Lloh0:
	adrp	x21, _RADEON_BIOS_5_SCRATCH@GOTPAGE
Lloh1:
	ldr	x21, [x21, _RADEON_BIOS_5_SCRATCH@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
	mov	x1, x0
	ldr	w8, [x20]
Lloh2:
	adrp	x9, _ATOM_DEVICE_TV1_SUPPORT@GOTPAGE
Lloh3:
	ldr	x9, [x9, _ATOM_DEVICE_TV1_SUPPORT@GOTPAGEOFF]
Lloh4:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
Lloh5:
	adrp	x9, _RADEON_TV1_CRTC_MASK@GOTPAGE
Lloh6:
	ldr	x9, [x9, _RADEON_TV1_CRTC_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	bic	w9, w1, w9
Lloh8:
	adrp	x10, _RADEON_TV1_CRTC_SHIFT@GOTPAGE
Lloh9:
	ldr	x10, [x10, _RADEON_TV1_CRTC_SHIFT@GOTPAGEOFF]
Lloh10:
	ldr	w10, [x10]
	lsl	w10, w19, w10
	orr	w1, w10, w9
LBB0_2:
Lloh11:
	adrp	x9, _ATOM_DEVICE_CRT1_SUPPORT@GOTPAGE
Lloh12:
	ldr	x9, [x9, _ATOM_DEVICE_CRT1_SUPPORT@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_4
; %bb.3:
Lloh14:
	adrp	x9, _RADEON_CRT1_CRTC_MASK@GOTPAGE
Lloh15:
	ldr	x9, [x9, _RADEON_CRT1_CRTC_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
	bic	w9, w1, w9
Lloh17:
	adrp	x10, _RADEON_CRT1_CRTC_SHIFT@GOTPAGE
Lloh18:
	ldr	x10, [x10, _RADEON_CRT1_CRTC_SHIFT@GOTPAGEOFF]
Lloh19:
	ldr	w10, [x10]
	lsl	w10, w19, w10
	orr	w1, w10, w9
LBB0_4:
Lloh20:
	adrp	x9, _ATOM_DEVICE_CRT2_SUPPORT@GOTPAGE
Lloh21:
	ldr	x9, [x9, _ATOM_DEVICE_CRT2_SUPPORT@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_6
; %bb.5:
Lloh23:
	adrp	x9, _RADEON_CRT2_CRTC_MASK@GOTPAGE
Lloh24:
	ldr	x9, [x9, _RADEON_CRT2_CRTC_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w9, [x9]
	bic	w9, w1, w9
Lloh26:
	adrp	x10, _RADEON_CRT2_CRTC_SHIFT@GOTPAGE
Lloh27:
	ldr	x10, [x10, _RADEON_CRT2_CRTC_SHIFT@GOTPAGEOFF]
Lloh28:
	ldr	w10, [x10]
	lsl	w10, w19, w10
	orr	w1, w10, w9
LBB0_6:
Lloh29:
	adrp	x9, _ATOM_DEVICE_LCD1_SUPPORT@GOTPAGE
Lloh30:
	ldr	x9, [x9, _ATOM_DEVICE_LCD1_SUPPORT@GOTPAGEOFF]
Lloh31:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_8
; %bb.7:
Lloh32:
	adrp	x9, _RADEON_LCD1_CRTC_MASK@GOTPAGE
Lloh33:
	ldr	x9, [x9, _RADEON_LCD1_CRTC_MASK@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	bic	w9, w1, w9
Lloh35:
	adrp	x10, _RADEON_LCD1_CRTC_SHIFT@GOTPAGE
Lloh36:
	ldr	x10, [x10, _RADEON_LCD1_CRTC_SHIFT@GOTPAGEOFF]
Lloh37:
	ldr	w10, [x10]
	lsl	w10, w19, w10
	orr	w1, w10, w9
LBB0_8:
Lloh38:
	adrp	x9, _ATOM_DEVICE_DFP1_SUPPORT@GOTPAGE
Lloh39:
	ldr	x9, [x9, _ATOM_DEVICE_DFP1_SUPPORT@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_10
; %bb.9:
Lloh41:
	adrp	x9, _RADEON_DFP1_CRTC_MASK@GOTPAGE
Lloh42:
	ldr	x9, [x9, _RADEON_DFP1_CRTC_MASK@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
	bic	w9, w1, w9
Lloh44:
	adrp	x10, _RADEON_DFP1_CRTC_SHIFT@GOTPAGE
Lloh45:
	ldr	x10, [x10, _RADEON_DFP1_CRTC_SHIFT@GOTPAGEOFF]
Lloh46:
	ldr	w10, [x10]
	lsl	w10, w19, w10
	orr	w1, w10, w9
LBB0_10:
Lloh47:
	adrp	x9, _ATOM_DEVICE_DFP2_SUPPORT@GOTPAGE
Lloh48:
	ldr	x9, [x9, _ATOM_DEVICE_DFP2_SUPPORT@GOTPAGEOFF]
Lloh49:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_12
; %bb.11:
Lloh50:
	adrp	x8, _RADEON_DFP2_CRTC_MASK@GOTPAGE
Lloh51:
	ldr	x8, [x8, _RADEON_DFP2_CRTC_MASK@GOTPAGEOFF]
Lloh52:
	ldr	w8, [x8]
	bic	w8, w1, w8
Lloh53:
	adrp	x9, _RADEON_DFP2_CRTC_SHIFT@GOTPAGE
Lloh54:
	ldr	x9, [x9, _RADEON_DFP2_CRTC_SHIFT@GOTPAGEOFF]
Lloh55:
	ldr	w9, [x9]
	lsl	w9, w19, w9
	orr	w1, w9, w8
LBB0_12:
	ldr	w0, [x21]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_BIOS_5_SCRATCH,4,2      ; @RADEON_BIOS_5_SCRATCH
	.comm	_ATOM_DEVICE_TV1_SUPPORT,4,2    ; @ATOM_DEVICE_TV1_SUPPORT
	.comm	_RADEON_TV1_CRTC_MASK,4,2       ; @RADEON_TV1_CRTC_MASK
	.comm	_RADEON_TV1_CRTC_SHIFT,4,2      ; @RADEON_TV1_CRTC_SHIFT
	.comm	_ATOM_DEVICE_CRT1_SUPPORT,4,2   ; @ATOM_DEVICE_CRT1_SUPPORT
	.comm	_RADEON_CRT1_CRTC_MASK,4,2      ; @RADEON_CRT1_CRTC_MASK
	.comm	_RADEON_CRT1_CRTC_SHIFT,4,2     ; @RADEON_CRT1_CRTC_SHIFT
	.comm	_ATOM_DEVICE_CRT2_SUPPORT,4,2   ; @ATOM_DEVICE_CRT2_SUPPORT
	.comm	_RADEON_CRT2_CRTC_MASK,4,2      ; @RADEON_CRT2_CRTC_MASK
	.comm	_RADEON_CRT2_CRTC_SHIFT,4,2     ; @RADEON_CRT2_CRTC_SHIFT
	.comm	_ATOM_DEVICE_LCD1_SUPPORT,4,2   ; @ATOM_DEVICE_LCD1_SUPPORT
	.comm	_RADEON_LCD1_CRTC_MASK,4,2      ; @RADEON_LCD1_CRTC_MASK
	.comm	_RADEON_LCD1_CRTC_SHIFT,4,2     ; @RADEON_LCD1_CRTC_SHIFT
	.comm	_ATOM_DEVICE_DFP1_SUPPORT,4,2   ; @ATOM_DEVICE_DFP1_SUPPORT
	.comm	_RADEON_DFP1_CRTC_MASK,4,2      ; @RADEON_DFP1_CRTC_MASK
	.comm	_RADEON_DFP1_CRTC_SHIFT,4,2     ; @RADEON_DFP1_CRTC_SHIFT
	.comm	_ATOM_DEVICE_DFP2_SUPPORT,4,2   ; @ATOM_DEVICE_DFP2_SUPPORT
	.comm	_RADEON_DFP2_CRTC_MASK,4,2      ; @RADEON_DFP2_CRTC_MASK
	.comm	_RADEON_DFP2_CRTC_SHIFT,4,2     ; @RADEON_DFP2_CRTC_SHIFT
.subsections_via_symbols
