	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function bnx2_test_and_enable_2g5
_bnx2_test_and_enable_2g5:              ## @bnx2_test_and_enable_2g5
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_BNX2_PHY_FLAG_2_5G_CAPABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rdi)
	je	LBB0_1
## %bb.2:
	movq	%rdi, %rbx
	movq	_AUTONEG_SPEED@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 4(%rdi)
	je	LBB0_4
## %bb.3:
	movq	_ADVERTISED_2500baseX_Full@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, 12(%rbx)
LBB0_4:
	movq	%rbx, %rdi
	callq	_BNX2_CHIP
	movq	_BNX2_CHIP_5709@GOTPCREL(%rip), %r15
	cmpq	(%r15), %rax
	jne	LBB0_6
## %bb.5:
	movq	_MII_BNX2_BLK_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MII_BNX2_BLK_ADDR_OVER1G@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_bnx2_write_phy
LBB0_6:
	movl	8(%rbx), %esi
	leaq	-28(%rbp), %rdx
	movq	%rbx, %rdi
	callq	_bnx2_read_phy
	movl	-28(%rbp), %eax
	movq	_BCM5708S_UP1_2G5@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	$1, %r14d
	testl	%eax, %edx
	jne	LBB0_8
## %bb.7:
	orl	%eax, %edx
	movl	%edx, -28(%rbp)
	movl	8(%rbx), %esi
	movq	%rbx, %rdi
	callq	_bnx2_write_phy
	xorl	%r14d, %r14d
LBB0_8:
	movq	%rbx, %rdi
	callq	_BNX2_CHIP
	cmpq	(%r15), %rax
	jne	LBB0_10
## %bb.9:
	movq	_MII_BNX2_BLK_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MII_BNX2_BLK_ADDR_COMBO_IEEEB0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_bnx2_write_phy
	jmp	LBB0_10
LBB0_1:
	xorl	%r14d, %r14d
LBB0_10:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_BNX2_PHY_FLAG_2_5G_CAPABLE,4,2 ## @BNX2_PHY_FLAG_2_5G_CAPABLE
	.comm	_AUTONEG_SPEED,4,2              ## @AUTONEG_SPEED
	.comm	_ADVERTISED_2500baseX_Full,4,2  ## @ADVERTISED_2500baseX_Full
	.comm	_BNX2_CHIP_5709,8,3             ## @BNX2_CHIP_5709
	.comm	_MII_BNX2_BLK_ADDR,4,2          ## @MII_BNX2_BLK_ADDR
	.comm	_MII_BNX2_BLK_ADDR_OVER1G,4,2   ## @MII_BNX2_BLK_ADDR_OVER1G
	.comm	_BCM5708S_UP1_2G5,4,2           ## @BCM5708S_UP1_2G5
	.comm	_MII_BNX2_BLK_ADDR_COMBO_IEEEB0,4,2 ## @MII_BNX2_BLK_ADDR_COMBO_IEEEB0
	.no_dead_strip	_bnx2_test_and_enable_2g5
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function bnx2_test_and_enable_2g5
_bnx2_test_and_enable_2g5:              ; @bnx2_test_and_enable_2g5
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _BNX2_PHY_FLAG_2_5G_CAPABLE@GOTPAGE
Lloh1:
	ldr	x9, [x9, _BNX2_PHY_FLAG_2_5G_CAPABLE@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_7
; %bb.1:
	mov	x19, x0
	ldr	w8, [x0, #4]
Lloh3:
	adrp	x9, _AUTONEG_SPEED@GOTPAGE
Lloh4:
	ldr	x9, [x9, _AUTONEG_SPEED@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_3
; %bb.2:
Lloh6:
	adrp	x8, _ADVERTISED_2500baseX_Full@GOTPAGE
Lloh7:
	ldr	x8, [x8, _ADVERTISED_2500baseX_Full@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	ldr	w9, [x19, #12]
	orr	w8, w9, w8
	str	w8, [x19, #12]
LBB0_3:
	mov	x0, x19
	bl	_BNX2_CHIP
Lloh9:
	adrp	x21, _BNX2_CHIP_5709@GOTPAGE
Lloh10:
	ldr	x21, [x21, _BNX2_CHIP_5709@GOTPAGEOFF]
	ldr	x8, [x21]
	cmp	x0, x8
	b.ne	LBB0_5
; %bb.4:
Lloh11:
	adrp	x8, _MII_BNX2_BLK_ADDR@GOTPAGE
Lloh12:
	ldr	x8, [x8, _MII_BNX2_BLK_ADDR@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
Lloh14:
	adrp	x8, _MII_BNX2_BLK_ADDR_OVER1G@GOTPAGE
Lloh15:
	ldr	x8, [x8, _MII_BNX2_BLK_ADDR_OVER1G@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_bnx2_write_phy
LBB0_5:
	ldr	w1, [x19, #8]
	add	x2, sp, #12
	mov	x0, x19
	bl	_bnx2_read_phy
	ldr	w8, [sp, #12]
Lloh17:
	adrp	x9, _BCM5708S_UP1_2G5@GOTPAGE
Lloh18:
	ldr	x9, [x9, _BCM5708S_UP1_2G5@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_8
; %bb.6:
	mov	w20, #1
	b	LBB0_9
LBB0_7:
	mov	w20, #0
	b	LBB0_11
LBB0_8:
	orr	w2, w9, w8
	str	w2, [sp, #12]
	ldr	w1, [x19, #8]
	mov	x0, x19
	bl	_bnx2_write_phy
	mov	w20, #0
LBB0_9:
	mov	x0, x19
	bl	_BNX2_CHIP
	ldr	x8, [x21]
	cmp	x0, x8
	b.ne	LBB0_11
; %bb.10:
Lloh20:
	adrp	x8, _MII_BNX2_BLK_ADDR@GOTPAGE
Lloh21:
	ldr	x8, [x8, _MII_BNX2_BLK_ADDR@GOTPAGEOFF]
Lloh22:
	ldr	w1, [x8]
Lloh23:
	adrp	x8, _MII_BNX2_BLK_ADDR_COMBO_IEEEB0@GOTPAGE
Lloh24:
	ldr	x8, [x8, _MII_BNX2_BLK_ADDR_COMBO_IEEEB0@GOTPAGEOFF]
Lloh25:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_bnx2_write_phy
LBB0_11:
	mov	x0, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.cfi_endproc
                                        ; -- End function
	.comm	_BNX2_PHY_FLAG_2_5G_CAPABLE,4,2 ; @BNX2_PHY_FLAG_2_5G_CAPABLE
	.comm	_AUTONEG_SPEED,4,2              ; @AUTONEG_SPEED
	.comm	_ADVERTISED_2500baseX_Full,4,2  ; @ADVERTISED_2500baseX_Full
	.comm	_BNX2_CHIP_5709,8,3             ; @BNX2_CHIP_5709
	.comm	_MII_BNX2_BLK_ADDR,4,2          ; @MII_BNX2_BLK_ADDR
	.comm	_MII_BNX2_BLK_ADDR_OVER1G,4,2   ; @MII_BNX2_BLK_ADDR_OVER1G
	.comm	_BCM5708S_UP1_2G5,4,2           ; @BCM5708S_UP1_2G5
	.comm	_MII_BNX2_BLK_ADDR_COMBO_IEEEB0,4,2 ; @MII_BNX2_BLK_ADDR_COMBO_IEEEB0
	.no_dead_strip	_bnx2_test_and_enable_2g5
.subsections_via_symbols
