	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function evergreen_pcie_gart_disable
_evergreen_pcie_gart_disable:           ## @evergreen_pcie_gart_disable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_VM_CONTEXT0_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_VM_CONTEXT1_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_VM_L2_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_ENABLE_L2_FRAGMENT_PROCESSING@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$7, %edi
	callq	_EFFECTIVE_L2_QUEUE_SIZE
	orl	%eax, %ebx
	movl	%r15d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_VM_L2_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_VM_L2_CNTL3@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	xorl	%edi, %edi
	callq	_BANK_SELECT
	movl	%eax, %ebx
	movl	$2, %edi
	callq	_CACHE_UPDATE_MODE
	orl	%eax, %ebx
	movl	%r15d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	$5, %edi
	callq	_EFFECTIVE_L1_TLB_SIZE
	movl	%eax, %ebx
	movl	$5, %edi
	callq	_EFFECTIVE_L1_QUEUE_SIZE
	orl	%eax, %ebx
	movq	_MC_VM_MD_L1_TLB0_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_MD_L1_TLB1_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_MD_L1_TLB2_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_MB_L1_TLB0_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_MB_L1_TLB1_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_MB_L1_TLB2_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_MB_L1_TLB3_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	%r14, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_gart_table_vram_unpin   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_VM_CONTEXT0_CNTL,4,2           ## @VM_CONTEXT0_CNTL
	.comm	_VM_CONTEXT1_CNTL,4,2           ## @VM_CONTEXT1_CNTL
	.comm	_VM_L2_CNTL,4,2                 ## @VM_L2_CNTL
	.comm	_ENABLE_L2_FRAGMENT_PROCESSING,4,2 ## @ENABLE_L2_FRAGMENT_PROCESSING
	.comm	_VM_L2_CNTL2,4,2                ## @VM_L2_CNTL2
	.comm	_VM_L2_CNTL3,4,2                ## @VM_L2_CNTL3
	.comm	_MC_VM_MD_L1_TLB0_CNTL,4,2      ## @MC_VM_MD_L1_TLB0_CNTL
	.comm	_MC_VM_MD_L1_TLB1_CNTL,4,2      ## @MC_VM_MD_L1_TLB1_CNTL
	.comm	_MC_VM_MD_L1_TLB2_CNTL,4,2      ## @MC_VM_MD_L1_TLB2_CNTL
	.comm	_MC_VM_MB_L1_TLB0_CNTL,4,2      ## @MC_VM_MB_L1_TLB0_CNTL
	.comm	_MC_VM_MB_L1_TLB1_CNTL,4,2      ## @MC_VM_MB_L1_TLB1_CNTL
	.comm	_MC_VM_MB_L1_TLB2_CNTL,4,2      ## @MC_VM_MB_L1_TLB2_CNTL
	.comm	_MC_VM_MB_L1_TLB3_CNTL,4,2      ## @MC_VM_MB_L1_TLB3_CNTL
	.no_dead_strip	_evergreen_pcie_gart_disable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function evergreen_pcie_gart_disable
_evergreen_pcie_gart_disable:           ; @evergreen_pcie_gart_disable
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, _VM_CONTEXT0_CNTL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _VM_CONTEXT0_CNTL@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh3:
	adrp	x8, _VM_CONTEXT1_CNTL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _VM_CONTEXT1_CNTL@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh6:
	adrp	x8, _VM_L2_CNTL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _VM_L2_CNTL@GOTPAGEOFF]
Lloh8:
	ldr	w20, [x8]
Lloh9:
	adrp	x8, _ENABLE_L2_FRAGMENT_PROCESSING@GOTPAGE
Lloh10:
	ldr	x8, [x8, _ENABLE_L2_FRAGMENT_PROCESSING@GOTPAGEOFF]
Lloh11:
	ldr	w21, [x8]
	mov	w0, #7
	bl	_EFFECTIVE_L2_QUEUE_SIZE
	orr	w1, w0, w21
	mov	x0, x20
	bl	_WREG32
Lloh12:
	adrp	x8, _VM_L2_CNTL2@GOTPAGE
Lloh13:
	ldr	x8, [x8, _VM_L2_CNTL2@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh15:
	adrp	x8, _VM_L2_CNTL3@GOTPAGE
Lloh16:
	ldr	x8, [x8, _VM_L2_CNTL3@GOTPAGEOFF]
Lloh17:
	ldr	w20, [x8]
	mov	w0, #0
	bl	_BANK_SELECT
	mov	x21, x0
	mov	w0, #2
	bl	_CACHE_UPDATE_MODE
	orr	w1, w0, w21
	mov	x0, x20
	bl	_WREG32
	mov	w0, #5
	bl	_EFFECTIVE_L1_TLB_SIZE
	mov	x20, x0
	mov	w0, #5
	bl	_EFFECTIVE_L1_QUEUE_SIZE
	orr	w20, w0, w20
Lloh18:
	adrp	x8, _MC_VM_MD_L1_TLB0_CNTL@GOTPAGE
Lloh19:
	ldr	x8, [x8, _MC_VM_MD_L1_TLB0_CNTL@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh21:
	adrp	x8, _MC_VM_MD_L1_TLB1_CNTL@GOTPAGE
Lloh22:
	ldr	x8, [x8, _MC_VM_MD_L1_TLB1_CNTL@GOTPAGEOFF]
Lloh23:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh24:
	adrp	x8, _MC_VM_MD_L1_TLB2_CNTL@GOTPAGE
Lloh25:
	ldr	x8, [x8, _MC_VM_MD_L1_TLB2_CNTL@GOTPAGEOFF]
Lloh26:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh27:
	adrp	x8, _MC_VM_MB_L1_TLB0_CNTL@GOTPAGE
Lloh28:
	ldr	x8, [x8, _MC_VM_MB_L1_TLB0_CNTL@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh30:
	adrp	x8, _MC_VM_MB_L1_TLB1_CNTL@GOTPAGE
Lloh31:
	ldr	x8, [x8, _MC_VM_MB_L1_TLB1_CNTL@GOTPAGEOFF]
Lloh32:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh33:
	adrp	x8, _MC_VM_MB_L1_TLB2_CNTL@GOTPAGE
Lloh34:
	ldr	x8, [x8, _MC_VM_MB_L1_TLB2_CNTL@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh36:
	adrp	x8, _MC_VM_MB_L1_TLB3_CNTL@GOTPAGE
Lloh37:
	ldr	x8, [x8, _MC_VM_MB_L1_TLB3_CNTL@GOTPAGEOFF]
Lloh38:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_radeon_gart_table_vram_unpin
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_VM_CONTEXT0_CNTL,4,2           ; @VM_CONTEXT0_CNTL
	.comm	_VM_CONTEXT1_CNTL,4,2           ; @VM_CONTEXT1_CNTL
	.comm	_VM_L2_CNTL,4,2                 ; @VM_L2_CNTL
	.comm	_ENABLE_L2_FRAGMENT_PROCESSING,4,2 ; @ENABLE_L2_FRAGMENT_PROCESSING
	.comm	_VM_L2_CNTL2,4,2                ; @VM_L2_CNTL2
	.comm	_VM_L2_CNTL3,4,2                ; @VM_L2_CNTL3
	.comm	_MC_VM_MD_L1_TLB0_CNTL,4,2      ; @MC_VM_MD_L1_TLB0_CNTL
	.comm	_MC_VM_MD_L1_TLB1_CNTL,4,2      ; @MC_VM_MD_L1_TLB1_CNTL
	.comm	_MC_VM_MD_L1_TLB2_CNTL,4,2      ; @MC_VM_MD_L1_TLB2_CNTL
	.comm	_MC_VM_MB_L1_TLB0_CNTL,4,2      ; @MC_VM_MB_L1_TLB0_CNTL
	.comm	_MC_VM_MB_L1_TLB1_CNTL,4,2      ; @MC_VM_MB_L1_TLB1_CNTL
	.comm	_MC_VM_MB_L1_TLB2_CNTL,4,2      ; @MC_VM_MB_L1_TLB2_CNTL
	.comm	_MC_VM_MB_L1_TLB3_CNTL,4,2      ; @MC_VM_MB_L1_TLB3_CNTL
	.no_dead_strip	_evergreen_pcie_gart_disable
.subsections_via_symbols
