	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function c4_detect
_c4_detect:                             ## @c4_detect
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	_PCI_OUT_INT_MASK@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	addq	(%r15), %rdi
	movl	$12, %esi
	callq	_c4outmeml
	movq	(%rbx), %rdi
	addq	(%r15), %rdi
	callq	_c4inmeml
	movl	$1, %r14d
	cmpl	$12, %eax
	jne	LBB0_50
## %bb.1:
	movq	_DOORBELL@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	addq	(%r15), %rdi
	movq	_DBELL_RESET_ARM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_c4outmeml
	movq	_jiffies@GOTPCREL(%rip), %r12
	movslq	(%r12), %r13
	movq	_HZ@GOTPCREL(%rip), %rax
	movslq	(%rax), %rbx
	movq	(%r14), %rdi
	addq	(%r15), %rdi
	callq	_c4inmeml
	cmpl	$-1, %eax
	je	LBB0_6
## %bb.2:
	leaq	(%rbx,%rbx,4), %rax
	leaq	(,%rax,2), %rbx
	addq	%r13, %rbx
	movq	_DBELL_ADDR@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r12), %edi
	movq	%rbx, %rsi
	callq	_time_before
	testl	%eax, %eax
	je	LBB0_4
## %bb.5:                               ##   in Loop: Header=BB0_3 Depth=1
	movq	(%r14), %rdi
	addq	(%r15), %rdi
	movl	(%r13), %esi
	callq	_c4outmeml
	xorl	%eax, %eax
	callq	_mb
	movq	(%r14), %rdi
	addq	(%r15), %rdi
	callq	_c4inmeml
	cmpl	$-1, %eax
	jne	LBB0_3
LBB0_6:
	movq	_DC21285_ARMCSR_BASE@GOTPCREL(%rip), %r13
	movq	_CHAN_1_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	(%r13), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_c4_poke
	movq	_CHAN_2_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	(%r13), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_c4_poke
	movq	_MAILBOX_0@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	addq	(%r15), %rdi
	movl	$1437226410, %esi               ## imm = 0x55AA55AA
	callq	_c4outmeml
	movq	(%rbx), %rdi
	addq	(%r15), %rdi
	callq	_c4inmeml
	movl	$3, %r14d
	cmpl	$1437226410, %eax               ## imm = 0x55AA55AA
	jne	LBB0_50
## %bb.7:
	movq	(%rbx), %rdi
	addq	(%r15), %rdi
	movl	$-1437226411, %esi              ## imm = 0xAA55AA55
	callq	_c4outmeml
	movq	(%rbx), %rdi
	addq	(%r15), %rdi
	callq	_c4inmeml
	movl	$4, %r14d
	cmpl	$-1437226411, %eax              ## imm = 0xAA55AA55
	jne	LBB0_50
## %bb.8:
	movq	_DBELL_SA_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	(%r13), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_c4_poke
	movl	$5, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.9:
	movq	_DBELL_PCI_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	(%r13), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_c4_poke
	movl	$6, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.10:
	movq	_SA_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	(%r13), %esi
	movq	_SA_CTL_ALLRIGHT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_c4_poke
	movl	$7, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.11:
	movq	_XBUS_CYCLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	(%r13), %esi
	movq	_INIT_XBUS_CYCLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_c4_poke
	movl	$8, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.12:
	movq	_XBUS_STROBE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	(%r13), %esi
	movq	_INIT_XBUS_STROBE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_c4_poke
	testq	%rax, %rax
	jne	LBB0_50
## %bb.13:
	movq	_DRAM_TIMING@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	addl	(%r13), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_c4_poke
	movl	$9, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.14:
	movl	$1, %edi
	callq	_mdelay
	movq	_DC21285_DRAM_A0MR@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	leaq	-48(%rbp), %rdx
	movq	%r15, %rdi
	callq	_c4_peek
	movl	$10, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.15:
	movq	_DC21285_DRAM_A1MR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-48(%rbp), %rdx
	movq	%r15, %rdi
	callq	_c4_peek
	movl	$11, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.16:
	movq	_DC21285_DRAM_A2MR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-48(%rbp), %rdx
	movq	%r15, %rdi
	callq	_c4_peek
	movl	$12, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.17:
	movq	_DC21285_DRAM_A3MR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-48(%rbp), %rdx
	movq	%r15, %rdi
	callq	_c4_peek
	movl	$13, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.18:
	movq	_CAS_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	(%rbx), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_c4_poke
	movl	$14, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.19:
	movq	_CAS_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DC21285_DRAM_A1MR@GOTPCREL(%rip), %rax
	addl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_c4_poke
	movl	$15, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.20:
	movq	_CAS_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DC21285_DRAM_A2MR@GOTPCREL(%rip), %rax
	addl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_c4_poke
	movl	$16, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.21:
	movq	_CAS_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DC21285_DRAM_A3MR@GOTPCREL(%rip), %rax
	addl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_c4_poke
	movl	$17, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.22:
	movl	$1, %edi
	callq	_mdelay
	movl	(%r12), %esi
	addl	(%r13), %esi
	movq	_DRAM_TIMING_DEF@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_c4_poke
	movl	$18, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.23:
	movq	_DRAM_ADDR_SIZE_0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	(%r13), %esi
	movq	_DRAM_AD_SZ_DEF0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_c4_poke
	movl	$19, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.24:
	movq	_DRAM_ADDR_SIZE_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	(%r13), %esi
	movq	_DRAM_AD_SZ_NULL@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movq	%r15, %rdi
	callq	_c4_poke
	movl	$20, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.25:
	movq	_DRAM_ADDR_SIZE_2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	(%r13), %esi
	movl	(%r12), %edx
	movq	%r15, %rdi
	callq	_c4_poke
	movl	$21, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.26:
	movq	_DRAM_ADDR_SIZE_3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	(%r13), %esi
	movl	(%r12), %edx
	movq	%r15, %rdi
	callq	_c4_poke
	movl	$22, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.27:
	movq	%r15, %rdi
	xorl	%esi, %esi
	movl	$286331153, %edx                ## imm = 0x11111111
	callq	_c4_poke
	movl	$23, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.28:
	movq	%r15, %rdi
	movl	$4194304, %esi                  ## imm = 0x400000
	movl	$572662306, %edx                ## imm = 0x22222222
	callq	_c4_poke
	testq	%rax, %rax
	jne	LBB0_50
## %bb.29:
	movq	%r15, %rdi
	movl	$8388608, %esi                  ## imm = 0x800000
	movl	$858993459, %edx                ## imm = 0x33333333
	callq	_c4_poke
	testq	%rax, %rax
	jne	LBB0_50
## %bb.30:
	movq	%r15, %rdi
	movl	$12582912, %esi                 ## imm = 0xC00000
	movl	$1145324612, %edx               ## imm = 0x44444444
	callq	_c4_poke
	testq	%rax, %rax
	jne	LBB0_50
## %bb.31:
	leaq	-48(%rbp), %rdx
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_c4_peek
	movl	$24, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.32:
	cmpq	$286331153, -48(%rbp)           ## imm = 0x11111111
	jne	LBB0_50
## %bb.33:
	leaq	-48(%rbp), %rdx
	movq	%r15, %rdi
	movl	$4194304, %esi                  ## imm = 0x400000
	callq	_c4_peek
	testq	%rax, %rax
	jne	LBB0_50
## %bb.34:
	cmpq	$572662306, -48(%rbp)           ## imm = 0x22222222
	jne	LBB0_50
## %bb.35:
	leaq	-48(%rbp), %rdx
	movq	%r15, %rdi
	movl	$8388608, %esi                  ## imm = 0x800000
	callq	_c4_peek
	testq	%rax, %rax
	jne	LBB0_50
## %bb.36:
	cmpq	$858993459, -48(%rbp)           ## imm = 0x33333333
	jne	LBB0_50
## %bb.37:
	leaq	-48(%rbp), %rdx
	movq	%r15, %rdi
	movl	$12582912, %esi                 ## imm = 0xC00000
	callq	_c4_peek
	testq	%rax, %rax
	jne	LBB0_50
## %bb.38:
	cmpq	$1145324612, -48(%rbp)          ## imm = 0x44444444
	jne	LBB0_50
## %bb.39:
	movq	%r15, %rdi
	xorl	%esi, %esi
	movl	$1431655765, %edx               ## imm = 0x55555555
	callq	_c4_poke
	movl	$25, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.40:
	movq	%r15, %rdi
	movl	$4194304, %esi                  ## imm = 0x400000
	movl	$1717986918, %edx               ## imm = 0x66666666
	callq	_c4_poke
	testq	%rax, %rax
	jne	LBB0_50
## %bb.41:
	movq	%r15, %rdi
	movl	$8388608, %esi                  ## imm = 0x800000
	movl	$2004318071, %edx               ## imm = 0x77777777
	callq	_c4_poke
	testq	%rax, %rax
	jne	LBB0_50
## %bb.42:
	movq	%r15, %rdi
	movl	$12582912, %esi                 ## imm = 0xC00000
	movl	$-2004318072, %edx              ## imm = 0x88888888
	callq	_c4_poke
	testq	%rax, %rax
	jne	LBB0_50
## %bb.43:
	leaq	-48(%rbp), %rdx
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_c4_peek
	movl	$26, %r14d
	testq	%rax, %rax
	jne	LBB0_50
## %bb.44:
	cmpq	$1431655765, -48(%rbp)          ## imm = 0x55555555
	jne	LBB0_50
## %bb.45:
	leaq	-48(%rbp), %rdx
	movq	%r15, %rdi
	movl	$4194304, %esi                  ## imm = 0x400000
	callq	_c4_peek
	testq	%rax, %rax
	jne	LBB0_50
## %bb.46:
	cmpq	$1717986918, -48(%rbp)          ## imm = 0x66666666
	jne	LBB0_50
## %bb.47:
	leaq	-48(%rbp), %rdx
	movq	%r15, %rdi
	movl	$8388608, %esi                  ## imm = 0x800000
	callq	_c4_peek
	testq	%rax, %rax
	jne	LBB0_50
## %bb.48:
	cmpq	$2004318071, -48(%rbp)          ## imm = 0x77777777
	jne	LBB0_50
## %bb.49:
	leaq	-48(%rbp), %rdx
	movq	%r15, %rdi
	movl	$12582912, %esi                 ## imm = 0xC00000
	callq	_c4_peek
	movl	$2290649224, %ecx               ## imm = 0x88888888
	xorq	-48(%rbp), %rcx
	xorl	%edx, %edx
	orq	%rax, %rcx
	movl	$26, %r14d
	cmovel	%edx, %r14d
	jmp	LBB0_50
LBB0_4:
	movl	$2, %r14d
LBB0_50:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PCI_OUT_INT_MASK,8,3           ## @PCI_OUT_INT_MASK
	.comm	_DOORBELL,8,3                   ## @DOORBELL
	.comm	_DBELL_RESET_ARM,4,2            ## @DBELL_RESET_ARM
	.comm	_jiffies,4,2                    ## @jiffies
	.comm	_HZ,4,2                         ## @HZ
	.comm	_DBELL_ADDR,4,2                 ## @DBELL_ADDR
	.comm	_DC21285_ARMCSR_BASE,4,2        ## @DC21285_ARMCSR_BASE
	.comm	_CHAN_1_CONTROL,4,2             ## @CHAN_1_CONTROL
	.comm	_CHAN_2_CONTROL,4,2             ## @CHAN_2_CONTROL
	.comm	_MAILBOX_0,8,3                  ## @MAILBOX_0
	.comm	_DBELL_SA_MASK,4,2              ## @DBELL_SA_MASK
	.comm	_DBELL_PCI_MASK,4,2             ## @DBELL_PCI_MASK
	.comm	_SA_CONTROL,4,2                 ## @SA_CONTROL
	.comm	_SA_CTL_ALLRIGHT,4,2            ## @SA_CTL_ALLRIGHT
	.comm	_XBUS_CYCLE,4,2                 ## @XBUS_CYCLE
	.comm	_INIT_XBUS_CYCLE,4,2            ## @INIT_XBUS_CYCLE
	.comm	_XBUS_STROBE,4,2                ## @XBUS_STROBE
	.comm	_INIT_XBUS_STROBE,4,2           ## @INIT_XBUS_STROBE
	.comm	_DRAM_TIMING,4,2                ## @DRAM_TIMING
	.comm	_DC21285_DRAM_A0MR,4,2          ## @DC21285_DRAM_A0MR
	.comm	_DC21285_DRAM_A1MR,4,2          ## @DC21285_DRAM_A1MR
	.comm	_DC21285_DRAM_A2MR,4,2          ## @DC21285_DRAM_A2MR
	.comm	_DC21285_DRAM_A3MR,4,2          ## @DC21285_DRAM_A3MR
	.comm	_CAS_OFFSET,4,2                 ## @CAS_OFFSET
	.comm	_DRAM_TIMING_DEF,4,2            ## @DRAM_TIMING_DEF
	.comm	_DRAM_ADDR_SIZE_0,4,2           ## @DRAM_ADDR_SIZE_0
	.comm	_DRAM_AD_SZ_DEF0,4,2            ## @DRAM_AD_SZ_DEF0
	.comm	_DRAM_ADDR_SIZE_1,4,2           ## @DRAM_ADDR_SIZE_1
	.comm	_DRAM_AD_SZ_NULL,4,2            ## @DRAM_AD_SZ_NULL
	.comm	_DRAM_ADDR_SIZE_2,4,2           ## @DRAM_ADDR_SIZE_2
	.comm	_DRAM_ADDR_SIZE_3,4,2           ## @DRAM_ADDR_SIZE_3
	.no_dead_strip	_c4_detect
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function c4_detect
_c4_detect:                             ; @c4_detect
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldr	x8, [x0]
Lloh0:
	adrp	x20, _PCI_OUT_INT_MASK@GOTPAGE
Lloh1:
	ldr	x20, [x20, _PCI_OUT_INT_MASK@GOTPAGEOFF]
	ldr	x9, [x20]
	add	x0, x9, x8
	mov	w1, #12
	bl	_c4outmeml
	ldr	x8, [x19]
	ldr	x9, [x20]
	add	x0, x9, x8
	bl	_c4inmeml
	cmp	w0, #12
	b.ne	LBB0_9
; %bb.1:
Lloh2:
	adrp	x21, _DOORBELL@GOTPAGE
Lloh3:
	ldr	x21, [x21, _DOORBELL@GOTPAGEOFF]
	ldr	x8, [x19]
	ldr	x9, [x21]
	add	x0, x9, x8
Lloh4:
	adrp	x8, _DBELL_RESET_ARM@GOTPAGE
Lloh5:
	ldr	x8, [x8, _DBELL_RESET_ARM@GOTPAGEOFF]
Lloh6:
	ldr	w1, [x8]
	bl	_c4outmeml
Lloh7:
	adrp	x22, _jiffies@GOTPAGE
Lloh8:
	ldr	x22, [x22, _jiffies@GOTPAGEOFF]
	ldrsw	x20, [x22]
Lloh9:
	adrp	x8, _HZ@GOTPAGE
Lloh10:
	ldr	x8, [x8, _HZ@GOTPAGEOFF]
Lloh11:
	ldrsw	x23, [x8]
	ldr	x8, [x19]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_c4inmeml
	cmn	w0, #1
	b.eq	LBB0_5
; %bb.2:
	mov	w8, #10
	madd	x20, x23, x8, x20
Lloh12:
	adrp	x23, _DBELL_ADDR@GOTPAGE
Lloh13:
	ldr	x23, [x23, _DBELL_ADDR@GOTPAGEOFF]
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x22]
	mov	x1, x20
	bl	_time_before
	cbz	w0, LBB0_11
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	ldr	x8, [x19]
	ldr	x9, [x21]
	add	x0, x9, x8
	ldr	w1, [x23]
	bl	_c4outmeml
	bl	_mb
	ldr	x8, [x19]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_c4inmeml
	cmn	w0, #1
	b.ne	LBB0_3
LBB0_5:
Lloh14:
	adrp	x20, _DC21285_ARMCSR_BASE@GOTPAGE
Lloh15:
	ldr	x20, [x20, _DC21285_ARMCSR_BASE@GOTPAGEOFF]
	ldr	w8, [x20]
Lloh16:
	adrp	x9, _CHAN_1_CONTROL@GOTPAGE
Lloh17:
	ldr	x9, [x9, _CHAN_1_CONTROL@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	add	w1, w9, w8
	mov	x0, x19
	mov	w2, #0
	bl	_c4_poke
	ldr	w8, [x20]
Lloh19:
	adrp	x9, _CHAN_2_CONTROL@GOTPAGE
Lloh20:
	ldr	x9, [x9, _CHAN_2_CONTROL@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	add	w1, w9, w8
	mov	x0, x19
	mov	w2, #0
	bl	_c4_poke
	ldr	x8, [x19]
Lloh22:
	adrp	x21, _MAILBOX_0@GOTPAGE
Lloh23:
	ldr	x21, [x21, _MAILBOX_0@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x0, x9, x8
	mov	w22, #21930
	movk	w22, #21930, lsl #16
	mov	w1, #21930
	movk	w1, #21930, lsl #16
	bl	_c4outmeml
	ldr	x8, [x19]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_c4inmeml
	cmp	w0, w22
	b.ne	LBB0_10
; %bb.6:
	ldr	x8, [x19]
	ldr	x9, [x21]
	add	x0, x9, x8
	mov	w22, #43605
	movk	w22, #43605, lsl #16
	mov	w1, #43605
	movk	w1, #43605, lsl #16
	bl	_c4outmeml
	ldr	x8, [x19]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_c4inmeml
	cmp	w0, w22
	b.ne	LBB0_12
; %bb.7:
	ldr	w8, [x20]
Lloh24:
	adrp	x9, _DBELL_SA_MASK@GOTPAGE
Lloh25:
	ldr	x9, [x9, _DBELL_SA_MASK@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	add	w1, w9, w8
	mov	x0, x19
	mov	w2, #0
	bl	_c4_poke
	cbz	x0, LBB0_14
; %bb.8:
	mov	w0, #5
	b	LBB0_13
LBB0_9:
	mov	w0, #1
	b	LBB0_13
LBB0_10:
	mov	w0, #3
	b	LBB0_13
LBB0_11:
	mov	w0, #2
	b	LBB0_13
LBB0_12:
	mov	w0, #4
LBB0_13:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_14:
	ldr	w8, [x20]
Lloh27:
	adrp	x9, _DBELL_PCI_MASK@GOTPAGE
Lloh28:
	ldr	x9, [x9, _DBELL_PCI_MASK@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	add	w1, w9, w8
	mov	x0, x19
	mov	w2, #0
	bl	_c4_poke
	cbz	x0, LBB0_16
; %bb.15:
	mov	w0, #6
	b	LBB0_13
LBB0_16:
Lloh30:
	adrp	x8, _SA_CONTROL@GOTPAGE
Lloh31:
	ldr	x8, [x8, _SA_CONTROL@GOTPAGEOFF]
	ldr	w9, [x20]
Lloh32:
	ldr	w8, [x8]
	add	w1, w8, w9
Lloh33:
	adrp	x8, _SA_CTL_ALLRIGHT@GOTPAGE
Lloh34:
	ldr	x8, [x8, _SA_CTL_ALLRIGHT@GOTPAGEOFF]
Lloh35:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_c4_poke
	cbz	x0, LBB0_18
; %bb.17:
	mov	w0, #7
	b	LBB0_13
LBB0_18:
Lloh36:
	adrp	x8, _XBUS_CYCLE@GOTPAGE
Lloh37:
	ldr	x8, [x8, _XBUS_CYCLE@GOTPAGEOFF]
	ldr	w9, [x20]
Lloh38:
	ldr	w8, [x8]
	add	w1, w8, w9
Lloh39:
	adrp	x8, _INIT_XBUS_CYCLE@GOTPAGE
Lloh40:
	ldr	x8, [x8, _INIT_XBUS_CYCLE@GOTPAGEOFF]
Lloh41:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_c4_poke
	cbnz	x0, LBB0_20
; %bb.19:
Lloh42:
	adrp	x8, _XBUS_STROBE@GOTPAGE
Lloh43:
	ldr	x8, [x8, _XBUS_STROBE@GOTPAGEOFF]
	ldr	w9, [x20]
Lloh44:
	ldr	w8, [x8]
	add	w1, w8, w9
Lloh45:
	adrp	x8, _INIT_XBUS_STROBE@GOTPAGE
Lloh46:
	ldr	x8, [x8, _INIT_XBUS_STROBE@GOTPAGEOFF]
Lloh47:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_c4_poke
	cbz	x0, LBB0_21
LBB0_20:
	mov	w0, #8
	b	LBB0_13
LBB0_21:
	ldr	w8, [x20]
Lloh48:
	adrp	x21, _DRAM_TIMING@GOTPAGE
Lloh49:
	ldr	x21, [x21, _DRAM_TIMING@GOTPAGEOFF]
	ldr	w9, [x21]
	add	w1, w9, w8
	mov	x0, x19
	mov	w2, #0
	bl	_c4_poke
	cbz	x0, LBB0_23
; %bb.22:
	mov	w0, #9
	b	LBB0_13
LBB0_23:
	mov	w0, #1
	bl	_mdelay
Lloh50:
	adrp	x25, _DC21285_DRAM_A0MR@GOTPAGE
Lloh51:
	ldr	x25, [x25, _DC21285_DRAM_A0MR@GOTPAGEOFF]
	ldr	w1, [x25]
	add	x2, sp, #8
	mov	x0, x19
	bl	_c4_peek
	cbz	x0, LBB0_25
; %bb.24:
	mov	w0, #10
	b	LBB0_13
LBB0_25:
Lloh52:
	adrp	x24, _DC21285_DRAM_A1MR@GOTPAGE
Lloh53:
	ldr	x24, [x24, _DC21285_DRAM_A1MR@GOTPAGEOFF]
	ldr	w1, [x24]
	add	x2, sp, #8
	mov	x0, x19
	bl	_c4_peek
	cbz	x0, LBB0_27
; %bb.26:
	mov	w0, #11
	b	LBB0_13
LBB0_27:
Lloh54:
	adrp	x23, _DC21285_DRAM_A2MR@GOTPAGE
Lloh55:
	ldr	x23, [x23, _DC21285_DRAM_A2MR@GOTPAGEOFF]
	ldr	w1, [x23]
	add	x2, sp, #8
	mov	x0, x19
	bl	_c4_peek
	cbz	x0, LBB0_29
; %bb.28:
	mov	w0, #12
	b	LBB0_13
LBB0_29:
Lloh56:
	adrp	x22, _DC21285_DRAM_A3MR@GOTPAGE
Lloh57:
	ldr	x22, [x22, _DC21285_DRAM_A3MR@GOTPAGEOFF]
	ldr	w1, [x22]
	add	x2, sp, #8
	mov	x0, x19
	bl	_c4_peek
	cbz	x0, LBB0_31
; %bb.30:
	mov	w0, #13
	b	LBB0_13
LBB0_31:
	ldr	w8, [x25]
Lloh58:
	adrp	x25, _CAS_OFFSET@GOTPAGE
Lloh59:
	ldr	x25, [x25, _CAS_OFFSET@GOTPAGEOFF]
	ldr	w9, [x25]
	add	w1, w9, w8
	mov	x0, x19
	mov	w2, #0
	bl	_c4_poke
	cbz	x0, LBB0_33
; %bb.32:
	mov	w0, #14
	b	LBB0_13
LBB0_33:
	ldr	w8, [x24]
	ldr	w9, [x25]
	add	w1, w9, w8
	mov	x0, x19
	mov	w2, #0
	bl	_c4_poke
	cbz	x0, LBB0_35
; %bb.34:
	mov	w0, #15
	b	LBB0_13
LBB0_35:
	ldr	w8, [x23]
	ldr	w9, [x25]
	add	w1, w9, w8
	mov	x0, x19
	mov	w2, #0
	bl	_c4_poke
	cbz	x0, LBB0_37
; %bb.36:
	mov	w0, #16
	b	LBB0_13
LBB0_37:
	ldr	w8, [x22]
	ldr	w9, [x25]
	add	w1, w9, w8
	mov	x0, x19
	mov	w2, #0
	bl	_c4_poke
	cbz	x0, LBB0_39
; %bb.38:
	mov	w0, #17
	b	LBB0_13
LBB0_39:
	mov	w0, #1
	bl	_mdelay
	ldr	w8, [x20]
	ldr	w9, [x21]
	add	w1, w9, w8
Lloh60:
	adrp	x8, _DRAM_TIMING_DEF@GOTPAGE
Lloh61:
	ldr	x8, [x8, _DRAM_TIMING_DEF@GOTPAGEOFF]
Lloh62:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_c4_poke
	cbz	x0, LBB0_41
; %bb.40:
	mov	w0, #18
	b	LBB0_13
LBB0_41:
Lloh63:
	adrp	x8, _DRAM_ADDR_SIZE_0@GOTPAGE
Lloh64:
	ldr	x8, [x8, _DRAM_ADDR_SIZE_0@GOTPAGEOFF]
	ldr	w9, [x20]
Lloh65:
	ldr	w8, [x8]
	add	w1, w8, w9
Lloh66:
	adrp	x8, _DRAM_AD_SZ_DEF0@GOTPAGE
Lloh67:
	ldr	x8, [x8, _DRAM_AD_SZ_DEF0@GOTPAGEOFF]
Lloh68:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_c4_poke
	cbz	x0, LBB0_43
; %bb.42:
	mov	w0, #19
	b	LBB0_13
LBB0_43:
Lloh69:
	adrp	x8, _DRAM_ADDR_SIZE_1@GOTPAGE
Lloh70:
	ldr	x8, [x8, _DRAM_ADDR_SIZE_1@GOTPAGEOFF]
	ldr	w9, [x20]
Lloh71:
	ldr	w8, [x8]
	add	w1, w8, w9
Lloh72:
	adrp	x21, _DRAM_AD_SZ_NULL@GOTPAGE
Lloh73:
	ldr	x21, [x21, _DRAM_AD_SZ_NULL@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	x0, x19
	bl	_c4_poke
	cbz	x0, LBB0_45
; %bb.44:
	mov	w0, #20
	b	LBB0_13
LBB0_45:
	ldr	w8, [x20]
Lloh74:
	adrp	x9, _DRAM_ADDR_SIZE_2@GOTPAGE
Lloh75:
	ldr	x9, [x9, _DRAM_ADDR_SIZE_2@GOTPAGEOFF]
Lloh76:
	ldr	w9, [x9]
	add	w1, w9, w8
	ldr	w2, [x21]
	mov	x0, x19
	bl	_c4_poke
	cbz	x0, LBB0_47
; %bb.46:
	mov	w0, #21
	b	LBB0_13
LBB0_47:
	ldr	w8, [x20]
Lloh77:
	adrp	x9, _DRAM_ADDR_SIZE_3@GOTPAGE
Lloh78:
	ldr	x9, [x9, _DRAM_ADDR_SIZE_3@GOTPAGEOFF]
Lloh79:
	ldr	w9, [x9]
	add	w1, w9, w8
	ldr	w2, [x21]
	mov	x0, x19
	bl	_c4_poke
	cbz	x0, LBB0_49
; %bb.48:
	mov	w0, #22
	b	LBB0_13
LBB0_49:
	mov	x0, x19
	mov	w1, #0
	mov	w2, #286331153
	bl	_c4_poke
	cbnz	x0, LBB0_53
; %bb.50:
	mov	x0, x19
	mov	w1, #4194304
	mov	w2, #572662306
	bl	_c4_poke
	cbnz	x0, LBB0_53
; %bb.51:
	mov	x0, x19
	mov	w1, #8388608
	mov	w2, #858993459
	bl	_c4_poke
	cbnz	x0, LBB0_53
; %bb.52:
	mov	x0, x19
	mov	w1, #12582912
	mov	w2, #1145324612
	bl	_c4_poke
	cbz	x0, LBB0_54
LBB0_53:
	mov	w0, #23
	b	LBB0_13
LBB0_54:
	add	x2, sp, #8
	mov	x0, x19
	mov	w1, #0
	bl	_c4_peek
	mov	x8, x0
	mov	w0, #24
	cbnz	x8, LBB0_13
; %bb.55:
	ldr	x8, [sp, #8]
	mov	w9, #286331153
	cmp	x8, x9
	b.ne	LBB0_13
; %bb.56:
	add	x2, sp, #8
	mov	x0, x19
	mov	w1, #4194304
	bl	_c4_peek
	mov	x8, x0
	mov	w0, #24
	cbnz	x8, LBB0_13
; %bb.57:
	ldr	x8, [sp, #8]
	mov	w9, #572662306
	cmp	x8, x9
	b.ne	LBB0_13
; %bb.58:
	add	x2, sp, #8
	mov	x0, x19
	mov	w1, #8388608
	bl	_c4_peek
	mov	x8, x0
	mov	w0, #24
	cbnz	x8, LBB0_13
; %bb.59:
	ldr	x8, [sp, #8]
	mov	w9, #858993459
	cmp	x8, x9
	b.ne	LBB0_13
; %bb.60:
	add	x2, sp, #8
	mov	x0, x19
	mov	w1, #12582912
	bl	_c4_peek
	mov	x8, x0
	mov	w0, #24
	cbnz	x8, LBB0_13
; %bb.61:
	ldr	x8, [sp, #8]
	mov	w9, #1145324612
	cmp	x8, x9
	b.ne	LBB0_13
; %bb.62:
	mov	x0, x19
	mov	w1, #0
	mov	w2, #1431655765
	bl	_c4_poke
	cbnz	x0, LBB0_66
; %bb.63:
	mov	x0, x19
	mov	w1, #4194304
	mov	w2, #1717986918
	bl	_c4_poke
	cbnz	x0, LBB0_66
; %bb.64:
	mov	x0, x19
	mov	w1, #8388608
	mov	w2, #2004318071
	bl	_c4_poke
	cbnz	x0, LBB0_66
; %bb.65:
	mov	x0, x19
	mov	w1, #12582912
	mov	w2, #-2004318072
	bl	_c4_poke
	cbz	x0, LBB0_67
LBB0_66:
	mov	w0, #25
	b	LBB0_13
LBB0_67:
	add	x2, sp, #8
	mov	x0, x19
	mov	w1, #0
	bl	_c4_peek
	mov	x8, x0
	mov	w0, #26
	cbnz	x8, LBB0_13
; %bb.68:
	ldr	x8, [sp, #8]
	mov	w9, #1431655765
	cmp	x8, x9
	b.ne	LBB0_13
; %bb.69:
	add	x2, sp, #8
	mov	x0, x19
	mov	w1, #4194304
	bl	_c4_peek
	mov	x8, x0
	mov	w0, #26
	cbnz	x8, LBB0_13
; %bb.70:
	ldr	x8, [sp, #8]
	mov	w9, #1717986918
	cmp	x8, x9
	b.ne	LBB0_13
; %bb.71:
	add	x2, sp, #8
	mov	x0, x19
	mov	w1, #8388608
	bl	_c4_peek
	mov	x8, x0
	mov	w0, #26
	cbnz	x8, LBB0_13
; %bb.72:
	ldr	x8, [sp, #8]
	mov	w9, #2004318071
	cmp	x8, x9
	b.ne	LBB0_13
; %bb.73:
	add	x2, sp, #8
	mov	x0, x19
	mov	w1, #12582912
	bl	_c4_peek
	ldr	x8, [sp, #8]
	mov	w9, #-2004318072
	cmp	x8, x9
	ccmp	x0, #0, #0, eq
	mov	w8, #26
	csel	w0, w8, wzr, ne
	b	LBB0_13
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh54, Lloh55
	.loh AdrpLdrGot	Lloh56, Lloh57
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGot	Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.cfi_endproc
                                        ; -- End function
	.comm	_PCI_OUT_INT_MASK,8,3           ; @PCI_OUT_INT_MASK
	.comm	_DOORBELL,8,3                   ; @DOORBELL
	.comm	_DBELL_RESET_ARM,4,2            ; @DBELL_RESET_ARM
	.comm	_jiffies,4,2                    ; @jiffies
	.comm	_HZ,4,2                         ; @HZ
	.comm	_DBELL_ADDR,4,2                 ; @DBELL_ADDR
	.comm	_DC21285_ARMCSR_BASE,4,2        ; @DC21285_ARMCSR_BASE
	.comm	_CHAN_1_CONTROL,4,2             ; @CHAN_1_CONTROL
	.comm	_CHAN_2_CONTROL,4,2             ; @CHAN_2_CONTROL
	.comm	_MAILBOX_0,8,3                  ; @MAILBOX_0
	.comm	_DBELL_SA_MASK,4,2              ; @DBELL_SA_MASK
	.comm	_DBELL_PCI_MASK,4,2             ; @DBELL_PCI_MASK
	.comm	_SA_CONTROL,4,2                 ; @SA_CONTROL
	.comm	_SA_CTL_ALLRIGHT,4,2            ; @SA_CTL_ALLRIGHT
	.comm	_XBUS_CYCLE,4,2                 ; @XBUS_CYCLE
	.comm	_INIT_XBUS_CYCLE,4,2            ; @INIT_XBUS_CYCLE
	.comm	_XBUS_STROBE,4,2                ; @XBUS_STROBE
	.comm	_INIT_XBUS_STROBE,4,2           ; @INIT_XBUS_STROBE
	.comm	_DRAM_TIMING,4,2                ; @DRAM_TIMING
	.comm	_DC21285_DRAM_A0MR,4,2          ; @DC21285_DRAM_A0MR
	.comm	_DC21285_DRAM_A1MR,4,2          ; @DC21285_DRAM_A1MR
	.comm	_DC21285_DRAM_A2MR,4,2          ; @DC21285_DRAM_A2MR
	.comm	_DC21285_DRAM_A3MR,4,2          ; @DC21285_DRAM_A3MR
	.comm	_CAS_OFFSET,4,2                 ; @CAS_OFFSET
	.comm	_DRAM_TIMING_DEF,4,2            ; @DRAM_TIMING_DEF
	.comm	_DRAM_ADDR_SIZE_0,4,2           ; @DRAM_ADDR_SIZE_0
	.comm	_DRAM_AD_SZ_DEF0,4,2            ; @DRAM_AD_SZ_DEF0
	.comm	_DRAM_ADDR_SIZE_1,4,2           ; @DRAM_ADDR_SIZE_1
	.comm	_DRAM_AD_SZ_NULL,4,2            ; @DRAM_AD_SZ_NULL
	.comm	_DRAM_ADDR_SIZE_2,4,2           ; @DRAM_ADDR_SIZE_2
	.comm	_DRAM_ADDR_SIZE_3,4,2           ; @DRAM_ADDR_SIZE_3
	.no_dead_strip	_c4_detect
.subsections_via_symbols
