	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r600_cp_resume                 ## -- Begin function r600_cp_resume
	.p2align	4, 0x90
_r600_cp_resume:                        ## @r600_cp_resume
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	16(%rdi), %r13
	movq	_RADEON_RING_TYPE_GFX_INDEX@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	leaq	(%rax,%rax,4), %r14
	leaq	(%r13,%r14,4), %rax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movq	_GRBM_SOFT_RESET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_SOFT_RESET_CP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_WREG32
	movl	(%rbx), %edi
	callq	_RREG32
	movl	$15, %edi
	callq	_mdelay
	movl	(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r13,%r14,4), %eax
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	callq	_drm_order
	movl	%eax, %r12d
	movq	_RADEON_GPU_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	callq	_drm_order
	movl	%eax, %ebx
	shll	$8, %ebx
	orl	%r12d, %ebx
	movq	_CP_RB_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_CP_SEM_WAIT_TIMER@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CP_RB_WPTR_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r12), %edi
	movq	_RB_RPTR_WR_ENA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	%ebx, %esi
	callq	_WREG32
	movq	_CP_RB_RPTR_WR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	%r13, -56(%rbp)                 ## 8-byte Spill
	movl	$0, 4(%r13,%r14,4)
	movq	_CP_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CP_RB_RPTR_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_WB_CP_RPTR_OFFSET@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	addl	(%r15), %esi
	andl	$-4, %esi
	callq	_WREG32
	movq	_CP_RB_RPTR_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	(%r13), %edi
	addl	(%r15), %edi
	callq	_upper_32_bits
	movzbl	%al, %esi
	movl	%r12d, %edi
	callq	_WREG32
	movq	_SCRATCH_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_WB_SCRATCH_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	(%r15), %esi
	sarl	$8, %esi
	callq	_WREG32
	cmpq	$0, 8(%r15)
	movl	$255, %esi
	jne	LBB0_1
## %bb.2:
	movq	_RB_NO_UPDATE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	xorl	%esi, %esi
	jmp	LBB0_3
LBB0_1:
	xorl	%eax, %eax
LBB0_3:
	orl	%eax, %ebx
	movq	_SCRATCH_UMSK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32
	movl	$1, %edi
	callq	_mdelay
	movq	_CP_RB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_CP_RB_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movl	8(%rbx,%r14,4), %esi
	sarl	$8, %esi
	callq	_WREG32
	movq	_CP_DEBUG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$402653184, %esi                ## imm = 0x18000000
	callq	_WREG32
	movq	_CP_RB_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, 16(%rbx,%r14,4)
	movq	%r15, %rdi
	callq	_r600_cp_start
	movl	$1, 12(%rbx,%r14,4)
	movq	_RADEON_RING_TYPE_GFX_INDEX@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	movq	-48(%rbp), %rdx                 ## 8-byte Reload
	callq	_radeon_ring_test
	testl	%eax, %eax
	je	LBB0_5
## %bb.4:
	leaq	(%rbx,%r14,4), %rcx
	addq	$12, %rcx
	movl	$0, (%rcx)
LBB0_5:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_RING_TYPE_GFX_INDEX,8,3 ## @RADEON_RING_TYPE_GFX_INDEX
	.comm	_GRBM_SOFT_RESET,4,2            ## @GRBM_SOFT_RESET
	.comm	_SOFT_RESET_CP,4,2              ## @SOFT_RESET_CP
	.comm	_RADEON_GPU_PAGE_SIZE,4,2       ## @RADEON_GPU_PAGE_SIZE
	.comm	_CP_RB_CNTL,4,2                 ## @CP_RB_CNTL
	.comm	_CP_SEM_WAIT_TIMER,4,2          ## @CP_SEM_WAIT_TIMER
	.comm	_CP_RB_WPTR_DELAY,4,2           ## @CP_RB_WPTR_DELAY
	.comm	_RB_RPTR_WR_ENA,4,2             ## @RB_RPTR_WR_ENA
	.comm	_CP_RB_RPTR_WR,4,2              ## @CP_RB_RPTR_WR
	.comm	_CP_RB_WPTR,4,2                 ## @CP_RB_WPTR
	.comm	_CP_RB_RPTR_ADDR,4,2            ## @CP_RB_RPTR_ADDR
	.comm	_RADEON_WB_CP_RPTR_OFFSET,4,2   ## @RADEON_WB_CP_RPTR_OFFSET
	.comm	_CP_RB_RPTR_ADDR_HI,4,2         ## @CP_RB_RPTR_ADDR_HI
	.comm	_SCRATCH_ADDR,4,2               ## @SCRATCH_ADDR
	.comm	_RADEON_WB_SCRATCH_OFFSET,4,2   ## @RADEON_WB_SCRATCH_OFFSET
	.comm	_SCRATCH_UMSK,4,2               ## @SCRATCH_UMSK
	.comm	_RB_NO_UPDATE,4,2               ## @RB_NO_UPDATE
	.comm	_CP_RB_BASE,4,2                 ## @CP_RB_BASE
	.comm	_CP_DEBUG,4,2                   ## @CP_DEBUG
	.comm	_CP_RB_RPTR,4,2                 ## @CP_RB_RPTR
	.comm	_BUF_SWAP_32BIT,4,2             ## @BUF_SWAP_32BIT
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r600_cp_resume                 ; -- Begin function r600_cp_resume
	.p2align	2
_r600_cp_resume:                        ; @r600_cp_resume
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldr	x8, [x0, #16]
Lloh0:
	adrp	x23, _RADEON_RING_TYPE_GFX_INDEX@GOTPAGE
Lloh1:
	ldr	x23, [x23, _RADEON_RING_TYPE_GFX_INDEX@GOTPAGEOFF]
	ldr	x9, [x23]
	mov	w10, #20
	madd	x20, x9, x10, x8
Lloh2:
	adrp	x21, _GRBM_SOFT_RESET@GOTPAGE
Lloh3:
	ldr	x21, [x21, _GRBM_SOFT_RESET@GOTPAGEOFF]
	ldr	w0, [x21]
Lloh4:
	adrp	x8, _SOFT_RESET_CP@GOTPAGE
Lloh5:
	ldr	x8, [x8, _SOFT_RESET_CP@GOTPAGEOFF]
Lloh6:
	ldr	w1, [x8]
	bl	_WREG32
	ldr	w0, [x21]
	bl	_RREG32
	mov	w0, #15
	bl	_mdelay
	ldr	w0, [x21]
	mov	w1, #0
	bl	_WREG32
	ldr	w8, [x20]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #3
	bl	_drm_order
	mov	x21, x0
Lloh7:
	adrp	x8, _RADEON_GPU_PAGE_SIZE@GOTPAGE
Lloh8:
	ldr	x8, [x8, _RADEON_GPU_PAGE_SIZE@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #3
	bl	_drm_order
	orr	w21, w21, w0, lsl #8
Lloh10:
	adrp	x24, _CP_RB_CNTL@GOTPAGE
Lloh11:
	ldr	x24, [x24, _CP_RB_CNTL@GOTPAGEOFF]
	ldr	w0, [x24]
	mov	x1, x21
	bl	_WREG32
Lloh12:
	adrp	x8, _CP_SEM_WAIT_TIMER@GOTPAGE
Lloh13:
	ldr	x8, [x8, _CP_SEM_WAIT_TIMER@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh15:
	adrp	x8, _CP_RB_WPTR_DELAY@GOTPAGE
Lloh16:
	ldr	x8, [x8, _CP_RB_WPTR_DELAY@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x24]
Lloh18:
	adrp	x8, _RB_RPTR_WR_ENA@GOTPAGE
Lloh19:
	ldr	x8, [x8, _RB_RPTR_WR_ENA@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	orr	w1, w8, w21
	bl	_WREG32
Lloh21:
	adrp	x8, _CP_RB_RPTR_WR@GOTPAGE
Lloh22:
	ldr	x8, [x8, _CP_RB_RPTR_WR@GOTPAGEOFF]
Lloh23:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	str	wzr, [x20, #4]
Lloh24:
	adrp	x8, _CP_RB_WPTR@GOTPAGE
Lloh25:
	ldr	x8, [x8, _CP_RB_WPTR@GOTPAGEOFF]
Lloh26:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh27:
	adrp	x8, _CP_RB_RPTR_ADDR@GOTPAGE
Lloh28:
	ldr	x8, [x8, _CP_RB_RPTR_ADDR@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	ldr	w8, [x19]
Lloh30:
	adrp	x25, _RADEON_WB_CP_RPTR_OFFSET@GOTPAGE
Lloh31:
	ldr	x25, [x25, _RADEON_WB_CP_RPTR_OFFSET@GOTPAGEOFF]
	ldr	w9, [x25]
	add	w8, w9, w8
	and	w1, w8, #0xfffffffc
	bl	_WREG32
Lloh32:
	adrp	x8, _CP_RB_RPTR_ADDR_HI@GOTPAGE
Lloh33:
	ldr	x8, [x8, _CP_RB_RPTR_ADDR_HI@GOTPAGEOFF]
Lloh34:
	ldr	w22, [x8]
	ldr	w8, [x19]
	ldr	w9, [x25]
	add	w0, w9, w8
	bl	_upper_32_bits
	and	w1, w0, #0xff
	mov	x0, x22
	bl	_WREG32
Lloh35:
	adrp	x8, _SCRATCH_ADDR@GOTPAGE
Lloh36:
	ldr	x8, [x8, _SCRATCH_ADDR@GOTPAGEOFF]
Lloh37:
	ldr	w0, [x8]
	ldr	w8, [x19]
Lloh38:
	adrp	x9, _RADEON_WB_SCRATCH_OFFSET@GOTPAGE
Lloh39:
	ldr	x9, [x9, _RADEON_WB_SCRATCH_OFFSET@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
	add	w8, w9, w8
	asr	w1, w8, #8
	bl	_WREG32
	ldr	x8, [x19, #8]
Lloh41:
	adrp	x9, _RB_NO_UPDATE@GOTPAGE
Lloh42:
	ldr	x9, [x9, _RB_NO_UPDATE@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
	cmp	x8, #0
	mov	w8, #255
	csel	w1, wzr, w8, eq
	csel	w8, w9, wzr, eq
	orr	w21, w21, w8
Lloh44:
	adrp	x8, _SCRATCH_UMSK@GOTPAGE
Lloh45:
	ldr	x8, [x8, _SCRATCH_UMSK@GOTPAGEOFF]
Lloh46:
	ldr	w0, [x8]
	bl	_WREG32
	mov	w22, #1
	mov	w0, #1
	bl	_mdelay
	ldr	w0, [x24]
	mov	x1, x21
	bl	_WREG32
Lloh47:
	adrp	x8, _CP_RB_BASE@GOTPAGE
Lloh48:
	ldr	x8, [x8, _CP_RB_BASE@GOTPAGEOFF]
Lloh49:
	ldr	w0, [x8]
	ldr	w8, [x20, #8]
	asr	w1, w8, #8
	bl	_WREG32
Lloh50:
	adrp	x8, _CP_DEBUG@GOTPAGE
Lloh51:
	ldr	x8, [x8, _CP_DEBUG@GOTPAGEOFF]
Lloh52:
	ldr	w0, [x8]
	mov	w1, #402653184
	bl	_WREG32
Lloh53:
	adrp	x8, _CP_RB_RPTR@GOTPAGE
Lloh54:
	ldr	x8, [x8, _CP_RB_RPTR@GOTPAGEOFF]
Lloh55:
	ldr	w0, [x8]
	bl	_RREG32
	str	w0, [x20, #16]
	mov	x0, x19
	bl	_r600_cp_start
	mov	x21, x20
	str	w22, [x21, #12]!
	ldr	x1, [x23]
	mov	x0, x19
	mov	x2, x20
	bl	_radeon_ring_test
	cbz	w0, LBB0_2
; %bb.1:
	str	wzr, [x21]
LBB0_2:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_RING_TYPE_GFX_INDEX,8,3 ; @RADEON_RING_TYPE_GFX_INDEX
	.comm	_GRBM_SOFT_RESET,4,2            ; @GRBM_SOFT_RESET
	.comm	_SOFT_RESET_CP,4,2              ; @SOFT_RESET_CP
	.comm	_RADEON_GPU_PAGE_SIZE,4,2       ; @RADEON_GPU_PAGE_SIZE
	.comm	_CP_RB_CNTL,4,2                 ; @CP_RB_CNTL
	.comm	_CP_SEM_WAIT_TIMER,4,2          ; @CP_SEM_WAIT_TIMER
	.comm	_CP_RB_WPTR_DELAY,4,2           ; @CP_RB_WPTR_DELAY
	.comm	_RB_RPTR_WR_ENA,4,2             ; @RB_RPTR_WR_ENA
	.comm	_CP_RB_RPTR_WR,4,2              ; @CP_RB_RPTR_WR
	.comm	_CP_RB_WPTR,4,2                 ; @CP_RB_WPTR
	.comm	_CP_RB_RPTR_ADDR,4,2            ; @CP_RB_RPTR_ADDR
	.comm	_RADEON_WB_CP_RPTR_OFFSET,4,2   ; @RADEON_WB_CP_RPTR_OFFSET
	.comm	_CP_RB_RPTR_ADDR_HI,4,2         ; @CP_RB_RPTR_ADDR_HI
	.comm	_SCRATCH_ADDR,4,2               ; @SCRATCH_ADDR
	.comm	_RADEON_WB_SCRATCH_OFFSET,4,2   ; @RADEON_WB_SCRATCH_OFFSET
	.comm	_SCRATCH_UMSK,4,2               ; @SCRATCH_UMSK
	.comm	_RB_NO_UPDATE,4,2               ; @RB_NO_UPDATE
	.comm	_CP_RB_BASE,4,2                 ; @CP_RB_BASE
	.comm	_CP_DEBUG,4,2                   ; @CP_DEBUG
	.comm	_CP_RB_RPTR,4,2                 ; @CP_RB_RPTR
	.comm	_BUF_SWAP_32BIT,4,2             ; @BUF_SWAP_32BIT
.subsections_via_symbols
