	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function nvidia_init_iorr
_nvidia_init_iorr:                      ## @nvidia_init_iorr
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movl	%edi, %r13d
	movq	_AMD_K7_NUM_IORR@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	testl	%ecx, %ecx
	jle	LBB0_1
## %bb.2:
	movl	%ecx, -48(%rbp)                 ## 4-byte Spill
	movl	%r14d, -44(%rbp)                ## 4-byte Spill
	xorl	%r15d, %r15d
	movq	_IORR_BASE0@GOTPCREL(%rip), %r14
	movq	_IORR_MASK0@GOTPCREL(%rip), %r12
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movq	(%r14), %rdi
	addq	%r15, %rdi
	xorl	%edx, %edx
	callq	_rdmsr
	movq	(%r12), %rdi
	addq	%r15, %rdi
	movl	$15, %edx
	callq	_rdmsr
	cmpl	$4095, %r13d                    ## imm = 0xFFF
	jbe	LBB0_4
## %bb.5:                               ##   in Loop: Header=BB0_3 Depth=1
	incq	%rbx
	movq	_AMD_K7_NUM_IORR@GOTPCREL(%rip), %rax
	movslq	(%rax), %rax
	addq	$2, %r15
	cmpq	%rax, %rbx
	jl	LBB0_3
## %bb.6:
	leal	-1(%rbx), %ecx
	movl	-44(%rbp), %r14d                ## 4-byte Reload
	cmpl	%eax, %ebx
	jge	LBB0_8
	jmp	LBB0_10
LBB0_1:
	xorl	%ebx, %ebx
	movl	%ecx, %eax
	cmpl	%eax, %ebx
	jge	LBB0_8
	jmp	LBB0_10
LBB0_4:
	movq	_AMD_K7_NUM_IORR@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	-44(%rbp), %r14d                ## 4-byte Reload
	movl	-48(%rbp), %ecx                 ## 4-byte Reload
	cmpl	%eax, %ebx
	jl	LBB0_10
LBB0_8:
	movl	%ecx, %ebx
	cmpl	%eax, %ecx
	jge	LBB0_9
LBB0_10:
	andl	$-4096, %r13d                   ## imm = 0xF000
	orl	$24, %r13d
	negl	%r14d
	andl	$-4096, %r14d                   ## imm = 0xF000
	orl	$2048, %r14d                    ## imm = 0x800
	movq	_IORR_BASE0@GOTPCREL(%rip), %rax
	addl	%ebx, %ebx
	movslq	%ebx, %r12
	movq	(%rax), %rdi
	addq	%r12, %rdi
	xorl	%r15d, %r15d
	movl	%r13d, %esi
	xorl	%edx, %edx
	callq	_wrmsr
	movq	_IORR_MASK0@GOTPCREL(%rip), %rax
	addq	(%rax), %r12
	movq	%r12, %rdi
	movl	%r14d, %esi
	movl	$15, %edx
	callq	_wrmsr
	movq	_SYSCFG@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	callq	_rdmsr
	movq	(%rbx), %rdi
	movl	$-1, %esi
	callq	_wrmsr
	jmp	LBB0_11
LBB0_9:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r15d, %r15d
	subl	(%rax), %r15d
LBB0_11:
	movl	%r15d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_K7_NUM_IORR,4,2            ## @AMD_K7_NUM_IORR
	.comm	_IORR_BASE0,8,3                 ## @IORR_BASE0
	.comm	_IORR_MASK0,8,3                 ## @IORR_MASK0
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_SYSCFG,8,3                     ## @SYSCFG
	.no_dead_strip	_nvidia_init_iorr
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function nvidia_init_iorr
_nvidia_init_iorr:                      ; @nvidia_init_iorr
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x1
	mov	x20, x0
Lloh0:
	adrp	x25, _AMD_K7_NUM_IORR@GOTPAGE
Lloh1:
	ldr	x25, [x25, _AMD_K7_NUM_IORR@GOTPAGEOFF]
	ldr	w24, [x25]
Lloh2:
	adrp	x22, _IORR_BASE0@GOTPAGE
Lloh3:
	ldr	x22, [x22, _IORR_BASE0@GOTPAGEOFF]
Lloh4:
	adrp	x21, _IORR_MASK0@GOTPAGE
Lloh5:
	ldr	x21, [x21, _IORR_MASK0@GOTPAGEOFF]
	cmp	w24, #1
	b.lt	LBB0_5
; %bb.1:
	mov	x26, #0
	mov	x23, #0
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x22]
	add	x0, x26, x8
	mov	w2, #0
	bl	_rdmsr
	ldr	x8, [x21]
	add	x0, x26, x8
	mov	w2, #15
	bl	_rdmsr
	cmp	w20, #4095
	b.ls	LBB0_6
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	add	x23, x23, #1
	ldrsw	x8, [x25]
	add	x26, x26, #2
	cmp	x23, x8
	b.lt	LBB0_2
; %bb.4:
	sub	w24, w23, #1
	cmp	w23, w8
	b.ge	LBB0_7
	b	LBB0_8
LBB0_5:
	mov	w23, #0
	mov	x8, x24
	cmp	w23, w8
	b.ge	LBB0_7
	b	LBB0_8
LBB0_6:
	ldr	w8, [x25]
	cmp	w23, w8
	b.lt	LBB0_8
LBB0_7:
	mov	x23, x24
	cmp	w24, w8
	b.ge	LBB0_9
LBB0_8:
	and	w8, w20, #0xfffff000
	orr	w1, w8, #0x18
	neg	w8, w19
	and	w8, w8, #0xfffff000
	orr	w19, w8, #0x800
	ldr	x8, [x22]
	lsl	w9, w23, #1
	sxtw	x20, w9
	add	x0, x8, x20
	mov	w2, #0
	bl	_wrmsr
	ldr	x8, [x21]
	add	x0, x8, x20
	mov	x1, x19
	mov	w2, #15
	bl	_wrmsr
Lloh6:
	adrp	x19, _SYSCFG@GOTPAGE
Lloh7:
	ldr	x19, [x19, _SYSCFG@GOTPAGEOFF]
	ldr	x0, [x19]
	bl	_rdmsr
	ldr	x0, [x19]
	mov	w1, #-1
	bl	_wrmsr
	mov	w0, #0
	b	LBB0_10
LBB0_9:
Lloh8:
	adrp	x8, _EINVAL@GOTPAGE
Lloh9:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_10:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_K7_NUM_IORR,4,2            ; @AMD_K7_NUM_IORR
	.comm	_IORR_BASE0,8,3                 ; @IORR_BASE0
	.comm	_IORR_MASK0,8,3                 ; @IORR_MASK0
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_SYSCFG,8,3                     ; @SYSCFG
	.no_dead_strip	_nvidia_init_iorr
.subsections_via_symbols
