	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_drm_cvt_mode                   ## -- Begin function drm_cvt_mode
	.p2align	4, 0x90
_drm_cvt_mode:                          ## @drm_cvt_mode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%r9d, %ebx
	movl	%r8d, -48(%rbp)                 ## 4-byte Spill
	movl	%ecx, %r14d
	movl	%edx, %r12d
	movl	%esi, %r15d
	callq	_drm_mode_create
	movq	%rax, %r13
	testq	%rax, %rax
	je	LBB0_25
## %bb.1:
	testl	%r14d, %r14d
	movl	$60, %r9d
	cmovnel	%r14d, %r9d
	testl	%ebx, %ebx
	setne	%cl
	shll	%cl, %r9d
	movq	%r15, %rax
	addl	$7, %r15d
	testl	%eax, %eax
	movq	%rax, %rdi
	cmovnsl	%eax, %r15d
	andl	$-8, %r15d
	cmpl	$0, 16(%rbp)
	movl	%ebx, -44(%rbp)                 ## 4-byte Spill
	je	LBB0_2
## %bb.5:
	leal	(%r15,%r15), %eax
	leal	(%rax,%rax,8), %eax
	cltq
	imulq	$274877907, %rax, %rdx          ## imm = 0x10624DD3
	movq	%rdx, %rsi
	shrq	$63, %rsi
	sarq	$38, %rdx
	leal	(%rdx,%rsi), %eax
	addl	$7, %eax
                                        ## kill: def $edx killed $edx killed $rdx
	addl	%esi, %edx
	cmovnsl	%edx, %eax
	andl	$-8, %eax
	movl	%r12d, %r14d
	testl	%ebx, %ebx
	je	LBB0_7
## %bb.6:
	movl	%r12d, %r14d
	shrl	$31, %r14d
	addl	%r12d, %r14d
	sarl	%r14d
LBB0_7:
	leal	(%r15,%rax,2), %r15d
	leal	(%r14,%r14), %eax
	leal	(%rax,%rax,8), %eax
	cltq
	imulq	$274877907, %rax, %rsi          ## imm = 0x10624DD3
	movq	%rsi, %rax
	shrq	$63, %rax
	sarq	$38, %rsi
	addl	%eax, %esi
	addl	%esi, %esi
	jmp	LBB0_8
LBB0_2:
	movl	%r12d, %r14d
	testl	%ebx, %ebx
	je	LBB0_4
## %bb.3:
	movl	%r12d, %r14d
	shrl	$31, %r14d
	addl	%r12d, %r14d
	sarl	%r14d
LBB0_4:
	xorl	%esi, %esi
LBB0_8:
	movl	%r15d, (%r13)
	leal	(%rsi,%r12), %r8d
	movl	%r8d, 4(%r13)
	imull	$-1431655765, %r12d, %eax       ## imm = 0xAAAAAAAB
	addl	$715827882, %eax                ## imm = 0x2AAAAAAA
	cmpl	$1431655764, %eax               ## imm = 0x55555554
	ja	LBB0_10
## %bb.9:
	leal	(,%r12,4), %eax
	cltq
	imulq	$1431655766, %rax, %rax         ## imm = 0x55555556
	movq	%rax, %rdx
	shrq	$63, %rdx
	shrq	$32, %rax
	addl	%edx, %eax
	movl	$4, %r11d
	cmpl	%edi, %eax
	je	LBB0_19
LBB0_10:
	movslq	%r12d, %rax
	imulq	$954437177, %rax, %rax          ## imm = 0x38E38E39
	movq	%rax, %rdx
	shrq	$63, %rdx
	sarq	$33, %rax
	addl	%edx, %eax
	leal	(%rax,%rax,8), %edx
	movl	%r12d, %r10d
	subl	%edx, %r10d
	jne	LBB0_12
## %bb.11:
	movl	%r12d, %edx
	shll	$4, %edx
	movslq	%edx, %rdx
	imulq	$954437177, %rdx, %rdx          ## imm = 0x38E38E39
	movq	%rdx, %rax
	shrq	$63, %rax
	sarq	$33, %rdx
	addl	%eax, %edx
	movl	$5, %r11d
	cmpl	%edi, %edx
	je	LBB0_19
LBB0_12:
	imull	$-858993459, %r12d, %eax        ## imm = 0xCCCCCCCD
	addl	$429496728, %eax                ## imm = 0x19999998
	rorl	%eax
	cmpl	$429496728, %eax                ## imm = 0x19999998
	ja	LBB0_14
## %bb.13:
	movl	%r12d, %eax
	shll	$4, %eax
	cltq
	imulq	$1717986919, %rax, %rax         ## imm = 0x66666667
	movq	%rax, %rdx
	shrq	$63, %rdx
	sarq	$34, %rax
	addl	%edx, %eax
	movl	$6, %r11d
	cmpl	%edi, %eax
	je	LBB0_19
LBB0_14:
	testb	$3, %r12b
	jne	LBB0_16
## %bb.15:
	leal	(%r12,%r12,4), %eax
	leal	(%r12,%r12,4), %edx
	addl	$3, %edx
	testl	%eax, %eax
	cmovnsl	%eax, %edx
	sarl	$2, %edx
	movl	$7, %r11d
	cmpl	%edi, %edx
	je	LBB0_19
LBB0_16:
	testl	%r10d, %r10d
	jne	LBB0_18
## %bb.17:
	leal	(%r12,%r12,4), %eax
	leal	(%rax,%rax,2), %eax
	cltq
	imulq	$954437177, %rax, %rax          ## imm = 0x38E38E39
	movq	%rax, %rdx
	shrq	$63, %rdx
	sarq	$33, %rax
	addl	%edx, %eax
	movl	$7, %r11d
	cmpl	%edi, %eax
	je	LBB0_19
LBB0_18:
	movl	$10, %r11d
LBB0_19:
	movq	_HV_FACTOR@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	imull	$1000000, %ebx, %eax            ## imm = 0xF4240
	movl	-48(%rbp), %r12d                ## 4-byte Reload
	testl	%r12d, %r12d
	je	LBB0_20
## %bb.21:
	imull	$460, %ebx, %ecx                ## imm = 0x1CC
	movl	%ecx, %edx
	imull	%r9d, %edx
	subl	%edx, %eax
	addl	%r14d, %esi
	imull	%esi, %r9d
	xorl	%edx, %edx
	divl	%r9d
	movl	%eax, %r9d
	movl	%ecx, %eax
	xorl	%edx, %edx
	divl	%r9d
	movl	%eax, %ecx
	incl	%ecx
	leal	9(%r11), %eax
	cmpl	%eax, %ecx
	cmovlel	%eax, %ecx
	addl	%esi, %ecx
	leal	160(%r15), %r10d
	leal	80(%r15), %esi
	addl	$48, %r15d
	jmp	LBB0_22
LBB0_20:
	xorl	%edi, %edi
	movb	%cl, %dil
	imull	$550, %ebx, %r10d               ## imm = 0x226
	movl	%r10d, %edx
	imull	%r9d, %edx
	subl	%edx, %eax
	addl	%r14d, %esi
	leal	(%rdi,%rsi,2), %ecx
	addl	$6, %ecx
	addl	%eax, %eax
	imull	%r9d, %ecx
	xorl	%edx, %edx
	divl	%ecx
	movl	%eax, %r9d
	movl	%r10d, %eax
	xorl	%edx, %edx
	divl	%r9d
                                        ## kill: def $eax killed $eax def $rax
	incl	%eax
	leal	3(%r11), %ecx
	cmpl	%ecx, %eax
	cmovlel	%ecx, %eax
	leal	(%rax,%rsi), %ecx
	addl	$3, %ecx
	movl	%ebx, %eax
	shll	$5, %eax
	subl	%ebx, %eax
	subl	%ebx, %eax
	imull	$300, %r9d, %edx                ## imm = 0x12C
	imulq	$274877907, %rdx, %rdx          ## imm = 0x10624DD3
	shrq	$38, %rdx
	subl	%edx, %eax
	leal	(,%rbx,4), %edx
	leal	(%rdx,%rdx,4), %edx
	cmpl	%edx, %eax
	cmovbel	%edx, %eax
	imull	$100, %ebx, %esi
	subl	%eax, %esi
	imull	%r15d, %eax
	xorl	%edx, %edx
	divl	%esi
                                        ## kill: def $eax killed $eax def $rax
	leal	15(%rax), %esi
	testl	%eax, %eax
	cmovnsl	%eax, %esi
	andl	$-16, %esi
	leal	(%rsi,%r15), %r10d
	sarl	%esi
	addl	%r15d, %esi
	leal	(,%r10,8), %eax
	cltq
	imulq	$-1374389535, %rax, %rax        ## imm = 0xAE147AE1
	movq	%rax, %rdx
	shrq	$63, %rdx
	sarq	$37, %rax
	addl	%edx, %eax
	leal	(%rax,%rsi), %r15d
	addl	$7, %r15d
                                        ## kill: def $eax killed $eax killed $rax
	addl	%esi, %eax
	cmovnsl	%eax, %r15d
	andl	$-8, %r15d
	addl	$8, %r15d
LBB0_22:
	leal	3(%r8), %edi
	imull	%r10d, %ebx
	imull	$1000, %ebx, %eax               ## imm = 0x3E8
	xorl	%edx, %edx
	divl	%r9d
	cltq
	imulq	$274877907, %rax, %rax          ## imm = 0x10624DD3
	movq	%rax, %rdx
	shrq	$63, %rdx
	sarq	$36, %rax
	addl	%edx, %eax
	imull	$250, %eax, %eax
	leal	(%r11,%r8), %edx
	addl	$3, %edx
	movl	%ecx, 8(%r13)
	movl	%r10d, 12(%r13)
	movl	%esi, 16(%r13)
	movl	%r15d, 20(%r13)
	movl	%edi, 24(%r13)
	movl	%edx, 28(%r13)
	movl	%eax, 32(%r13)
	cmpl	$0, -44(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_24
## %bb.23:
	addl	%ecx, %ecx
	movl	%ecx, 8(%r13)
	movq	_DRM_MODE_FLAG_INTERLACE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, 36(%r13)
LBB0_24:
	movq	%r13, %rdi
	callq	_drm_mode_set_name
	movq	_DRM_MODE_FLAG_PVSYNC@GOTPCREL(%rip), %rax
	movq	_DRM_MODE_FLAG_PHSYNC@GOTPCREL(%rip), %rcx
	movq	_DRM_MODE_FLAG_NHSYNC@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movq	_DRM_MODE_FLAG_NVSYNC@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	orl	(%rax), %edx
	orl	(%rcx), %esi
	testl	%r12d, %r12d
	cmovel	%edx, %esi
	orl	%esi, 36(%r13)
LBB0_25:
	movq	%r13, %rax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_HV_FACTOR,4,2                  ## @HV_FACTOR
	.comm	_DRM_MODE_FLAG_INTERLACE,4,2    ## @DRM_MODE_FLAG_INTERLACE
	.comm	_DRM_MODE_FLAG_PHSYNC,4,2       ## @DRM_MODE_FLAG_PHSYNC
	.comm	_DRM_MODE_FLAG_NVSYNC,4,2       ## @DRM_MODE_FLAG_NVSYNC
	.comm	_DRM_MODE_FLAG_PVSYNC,4,2       ## @DRM_MODE_FLAG_PVSYNC
	.comm	_DRM_MODE_FLAG_NHSYNC,4,2       ## @DRM_MODE_FLAG_NHSYNC
	.comm	_CVT_CLOCK_STEP,4,2             ## @CVT_CLOCK_STEP
	.comm	_CVT_C_PRIME,4,2                ## @CVT_C_PRIME
	.comm	_CVT_HSYNC_PERCENTAGE,4,2       ## @CVT_HSYNC_PERCENTAGE
	.comm	_CVT_H_GRANULARITY,4,2          ## @CVT_H_GRANULARITY
	.comm	_CVT_MARGIN_PERCENTAGE,4,2      ## @CVT_MARGIN_PERCENTAGE
	.comm	_CVT_MIN_VSYNC_BP,4,2           ## @CVT_MIN_VSYNC_BP
	.comm	_CVT_MIN_V_BPORCH,4,2           ## @CVT_MIN_V_BPORCH
	.comm	_CVT_MIN_V_PORCH,4,2            ## @CVT_MIN_V_PORCH
	.comm	_CVT_M_PRIME,4,2                ## @CVT_M_PRIME
	.comm	_CVT_RB_H_BLANK,4,2             ## @CVT_RB_H_BLANK
	.comm	_CVT_RB_H_SYNC,4,2              ## @CVT_RB_H_SYNC
	.comm	_CVT_RB_MIN_VBLANK,4,2          ## @CVT_RB_MIN_VBLANK
	.comm	_CVT_RB_VFPORCH,4,2             ## @CVT_RB_VFPORCH
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_drm_cvt_mode                   ; -- Begin function drm_cvt_mode
	.p2align	2
_drm_cvt_mode:                          ; @drm_cvt_mode
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x24, x6
	mov	x21, x5
	mov	x19, x4
	mov	x25, x3
	mov	x23, x2
	mov	x22, x1
	bl	_drm_mode_create
	mov	x20, x0
	cbz	x0, LBB0_25
; %bb.1:
	mov	w8, #60
	cmp	w25, #0
	csel	w11, w8, w25, eq
	cmp	w21, #0
	cset	w10, ne
	negs	w8, w22
	and	w8, w8, #0x7
	and	w9, w22, #0x7
	csneg	w8, w9, w8, mi
	sub	w8, w22, w8
	cbz	w24, LBB0_3
; %bb.2:
	add	w9, w8, w8, lsl #3
	lsl	w9, w9, #1
	mov	w13, #19923
	movk	w13, #4194, lsl #16
	smull	x9, w9, w13
	lsr	x12, x9, #63
	asr	x9, x9, #38
	add	w9, w9, w12
	negs	w12, w9
	and	w14, w9, #0x7
	and	w12, w12, #0x7
	csneg	w12, w14, w12, mi
	sub	w9, w9, w12
	add	w8, w8, w9, lsl #1
	cmp	w23, #0
	cinc	w9, w23, lt
	asr	w9, w9, #1
	cmp	w21, #0
	csel	w12, w23, w9, eq
	add	w9, w12, w12, lsl #3
	lsl	w9, w9, #1
	smull	x9, w9, w13
	lsr	x13, x9, #63
	asr	x9, x9, #38
	add	w9, w9, w13
	lsl	w13, w9, #1
	b	LBB0_4
LBB0_3:
	mov	w13, #0
	cmp	w23, #0
	cinc	w9, w23, lt
	asr	w9, w9, #1
	cmp	w21, #0
	csel	w12, w23, w9, eq
LBB0_4:
	add	w9, w13, w23
	stp	w8, w9, [x20]
	mov	w14, #43691
	movk	w14, #43690, lsl #16
	mov	w15, #43690
	movk	w15, #10922, lsl #16
	madd	w14, w23, w14, w15
	mov	w15, #21844
	movk	w15, #21845, lsl #16
	cmp	w14, w15
	b.hi	LBB0_7
; %bb.5:
	lsl	w14, w23, #2
	mov	w15, #21846
	movk	w15, #21845, lsl #16
	smull	x14, w14, w15
	lsr	x15, x14, #63
	lsr	x14, x14, #32
	add	w14, w14, w15
	cmp	w14, w22
	b.ne	LBB0_7
; %bb.6:
	mov	w14, #4
	b	LBB0_19
LBB0_7:
	mov	w15, #36409
	movk	w15, #14563, lsl #16
	smull	x14, w23, w15
	lsr	x16, x14, #63
	asr	x14, x14, #33
	add	w14, w14, w16
	add	w14, w14, w14, lsl #3
	subs	w14, w23, w14
	b.ne	LBB0_10
; %bb.8:
	lsl	w16, w23, #4
	smull	x15, w16, w15
	lsr	x16, x15, #63
	asr	x15, x15, #33
	add	w15, w15, w16
	cmp	w15, w22
	b.ne	LBB0_10
; %bb.9:
	mov	w14, #5
	b	LBB0_19
LBB0_10:
	mov	w15, #52429
	movk	w15, #52428, lsl #16
	mov	w16, #39320
	movk	w16, #6553, lsl #16
	madd	w15, w23, w15, w16
	ror	w15, w15, #1
	cmp	w15, w16
	b.hi	LBB0_13
; %bb.11:
	lsl	w15, w23, #4
	mov	w16, #26215
	movk	w16, #26214, lsl #16
	smull	x15, w15, w16
	lsr	x16, x15, #63
	asr	x15, x15, #34
	add	w15, w15, w16
	cmp	w15, w22
	b.ne	LBB0_13
; %bb.12:
	mov	w14, #6
	b	LBB0_19
LBB0_13:
	tst	w23, #0x3
	b.ne	LBB0_15
; %bb.14:
	add	w15, w23, w23, lsl #2
	add	w16, w15, #3
	cmp	w15, #0
	csel	w15, w16, w15, lt
	cmp	w22, w15, asr #2
	b.eq	LBB0_17
LBB0_15:
	cbnz	w14, LBB0_18
; %bb.16:
	lsl	w14, w23, #4
	sub	w14, w14, w23
	mov	w15, #36409
	movk	w15, #14563, lsl #16
	smull	x14, w14, w15
	lsr	x15, x14, #63
	asr	x14, x14, #33
	add	w14, w14, w15
	cmp	w14, w22
	b.ne	LBB0_18
LBB0_17:
	mov	w14, #7
	b	LBB0_19
LBB0_18:
	mov	w14, #10
LBB0_19:
	lsl	w15, w11, w10
Lloh0:
	adrp	x11, _HV_FACTOR@GOTPAGE
Lloh1:
	ldr	x11, [x11, _HV_FACTOR@GOTPAGEOFF]
Lloh2:
	ldr	w11, [x11]
	mov	w16, #16960
	movk	w16, #15, lsl #16
	mul	w16, w11, w16
	cbz	w19, LBB0_21
; %bb.20:
	mov	w10, #460
	mul	w17, w11, w10
	msub	w10, w17, w15, w16
	add	w12, w13, w12
	mul	w13, w12, w15
	udiv	w10, w10, w13
	udiv	w13, w17, w10
	add	w15, w13, #1
	add	w16, w14, #9
	cmp	w15, w16
	csinc	w13, w16, w13, le
	add	w12, w13, w12
	add	w13, w8, #160
	add	w15, w8, #80
	add	w8, w8, #48
	b	LBB0_22
LBB0_21:
	mov	w17, #550
	mul	w17, w11, w17
	msub	w16, w17, w15, w16
	add	w12, w13, w12
	bfi	w10, w12, #1, #31
	add	w10, w10, #6
	lsl	w13, w16, #1
	mul	w10, w10, w15
	udiv	w10, w13, w10
	udiv	w13, w17, w10
	add	w15, w13, #1
	add	w16, w14, #3
	cmp	w15, w16
	csinc	w13, w16, w13, le
	add	w12, w12, w13
	add	w12, w12, #3
	mov	w13, #30
	mul	w13, w11, w13
	mov	w15, #300
	mul	w15, w10, w15
	mov	w16, #19923
	movk	w16, #4194, lsl #16
	umull	x15, w15, w16
	lsr	x15, x15, #38
	add	w16, w11, w11, lsl #2
	lsl	w16, w16, #2
	sub	w13, w13, w15
	cmp	w13, w16
	csel	w13, w13, w16, hi
	mul	w15, w13, w8
	mov	w16, #100
	neg	w13, w13
	madd	w13, w11, w16, w13
	udiv	w13, w15, w13
	and	w15, w13, #0xf
	negs	w16, w13
	and	w16, w16, #0xf
	csneg	w15, w15, w16, mi
	sub	w15, w13, w15
	add	w13, w15, w8
	cmp	w15, #0
	cinc	w15, w15, lt
	add	w15, w8, w15, asr #1
	lsl	w8, w13, #3
	mov	w16, #31457
	movk	w16, #44564, lsl #16
	smull	x8, w8, w16
	lsr	x16, x8, #63
	asr	x8, x8, #37
	add	w8, w8, w16
	add	w8, w8, w15
	and	w16, w8, #0x7
	negs	w17, w8
	and	w17, w17, #0x7
	csneg	w16, w16, w17, mi
	sub	w8, w8, w16
	add	w8, w8, #8
LBB0_22:
	add	w9, w9, #3
	add	w14, w14, w9
	stp	w12, w13, [x20, #8]
	stp	w15, w8, [x20, #16]
	stp	w9, w14, [x20, #24]
	mul	w8, w13, w11
	mov	w9, #1000
	mul	w8, w8, w9
	udiv	w8, w8, w10
	mov	w9, #19923
	movk	w9, #4194, lsl #16
	smull	x8, w8, w9
	lsr	x9, x8, #32
	lsr	x8, x8, #63
	add	w8, w8, w9, asr #4
	mov	w9, #250
	mul	w8, w8, w9
	str	w8, [x20, #32]
	cbz	w21, LBB0_24
; %bb.23:
	lsl	w8, w12, #1
	str	w8, [x20, #8]
Lloh3:
	adrp	x8, _DRM_MODE_FLAG_INTERLACE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _DRM_MODE_FLAG_INTERLACE@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	ldr	w9, [x20, #36]
	orr	w8, w9, w8
	str	w8, [x20, #36]
LBB0_24:
	mov	x0, x20
	bl	_drm_mode_set_name
Lloh6:
	adrp	x8, _DRM_MODE_FLAG_PVSYNC@GOTPAGE
Lloh7:
	ldr	x8, [x8, _DRM_MODE_FLAG_PVSYNC@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
Lloh9:
	adrp	x9, _DRM_MODE_FLAG_PHSYNC@GOTPAGE
Lloh10:
	ldr	x9, [x9, _DRM_MODE_FLAG_PHSYNC@GOTPAGEOFF]
Lloh11:
	adrp	x10, _DRM_MODE_FLAG_NHSYNC@GOTPAGE
Lloh12:
	ldr	x10, [x10, _DRM_MODE_FLAG_NHSYNC@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
Lloh14:
	ldr	w10, [x10]
Lloh15:
	adrp	x11, _DRM_MODE_FLAG_NVSYNC@GOTPAGE
Lloh16:
	ldr	x11, [x11, _DRM_MODE_FLAG_NVSYNC@GOTPAGEOFF]
Lloh17:
	ldr	w11, [x11]
	orr	w8, w10, w8
	orr	w9, w11, w9
	cmp	w19, #0
	csel	w8, w8, w9, eq
	ldr	w9, [x20, #36]
	orr	w8, w8, w9
	str	w8, [x20, #36]
LBB0_25:
	mov	x0, x20
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh13
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_HV_FACTOR,4,2                  ; @HV_FACTOR
	.comm	_DRM_MODE_FLAG_INTERLACE,4,2    ; @DRM_MODE_FLAG_INTERLACE
	.comm	_DRM_MODE_FLAG_PHSYNC,4,2       ; @DRM_MODE_FLAG_PHSYNC
	.comm	_DRM_MODE_FLAG_NVSYNC,4,2       ; @DRM_MODE_FLAG_NVSYNC
	.comm	_DRM_MODE_FLAG_PVSYNC,4,2       ; @DRM_MODE_FLAG_PVSYNC
	.comm	_DRM_MODE_FLAG_NHSYNC,4,2       ; @DRM_MODE_FLAG_NHSYNC
	.comm	_CVT_CLOCK_STEP,4,2             ; @CVT_CLOCK_STEP
	.comm	_CVT_C_PRIME,4,2                ; @CVT_C_PRIME
	.comm	_CVT_HSYNC_PERCENTAGE,4,2       ; @CVT_HSYNC_PERCENTAGE
	.comm	_CVT_H_GRANULARITY,4,2          ; @CVT_H_GRANULARITY
	.comm	_CVT_MARGIN_PERCENTAGE,4,2      ; @CVT_MARGIN_PERCENTAGE
	.comm	_CVT_MIN_VSYNC_BP,4,2           ; @CVT_MIN_VSYNC_BP
	.comm	_CVT_MIN_V_BPORCH,4,2           ; @CVT_MIN_V_BPORCH
	.comm	_CVT_MIN_V_PORCH,4,2            ; @CVT_MIN_V_PORCH
	.comm	_CVT_M_PRIME,4,2                ; @CVT_M_PRIME
	.comm	_CVT_RB_H_BLANK,4,2             ; @CVT_RB_H_BLANK
	.comm	_CVT_RB_H_SYNC,4,2              ; @CVT_RB_H_SYNC
	.comm	_CVT_RB_MIN_VBLANK,4,2          ; @CVT_RB_MIN_VBLANK
	.comm	_CVT_RB_VFPORCH,4,2             ; @CVT_RB_VFPORCH
.subsections_via_symbols
