	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_asic_init               ## -- Begin function radeon_asic_init
	.p2align	4, 0x90
_radeon_asic_init:                      ## @radeon_asic_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	callq	_radeon_register_accessor_init
	movl	(%rbx), %ecx
	movq	_RADEON_SINGLE_CRTC@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	andl	%ecx, %edx
	xorl	%eax, %eax
	cmpl	$1, %edx
	movl	$0, %edx
	adcl	$1, %edx
	movl	8(%rbx), %esi
	movl	%edx, 4(%rbx)
	leal	-128(%rsi), %edx
	cmpl	$55, %edx
	ja	LBB0_26
## %bb.1:
	movl	$4, %eax
	leaq	LJTI0_0(%rip), %rdi
	movslq	(%rdi,%rdx,4), %rdx
	addq	%rdi, %rdx
	jmpq	*%rdx
LBB0_13:
	movq	_r600_asic@GOTPCREL(%rip), %rdx
	jmp	LBB0_28
LBB0_12:
	movq	_r520_asic@GOTPCREL(%rip), %rdx
	jmp	LBB0_28
LBB0_27:
	movq	_r100_asic@GOTPCREL(%rip), %rdx
	jmp	LBB0_28
LBB0_23:
	movq	_si_asic@GOTPCREL(%rip), %rdx
	movq	%rdx, 16(%rbx)
	cmpl	$175, %esi
	jne	LBB0_25
## %bb.24:
	movl	$2, 4(%rbx)
	jmp	LBB0_29
LBB0_15:
	movq	_rv770_asic@GOTPCREL(%rip), %rdx
	jmp	LBB0_28
LBB0_3:
	movq	_RADEON_IS_PCIE@GOTPCREL(%rip), %rax
	testl	%ecx, (%rax)
	je	LBB0_5
## %bb.4:
	movq	_r300_asic_pcie@GOTPCREL(%rip), %rdx
	jmp	LBB0_28
LBB0_2:
	movq	_r200_asic@GOTPCREL(%rip), %rdx
	jmp	LBB0_28
LBB0_16:
	movl	$6, %eax
LBB0_17:
	movl	%eax, 4(%rbx)
	movq	_evergreen_asic@GOTPCREL(%rip), %rdx
	jmp	LBB0_28
LBB0_18:
	movq	_sumo_asic@GOTPCREL(%rip), %rdx
	jmp	LBB0_28
LBB0_6:
	movq	_r420_asic@GOTPCREL(%rip), %rdx
	movq	%rdx, 16(%rbx)
	cmpq	$0, 24(%rbx)
	jne	LBB0_29
## %bb.7:
	movq	_radeon_legacy_get_engine_clock@GOTPCREL(%rip), %rax
	movq	_r420_asic@GOTPCREL(%rip), %rdx
	movq	%rax, 24(%rdx)
	movq	_radeon_legacy_set_engine_clock@GOTPCREL(%rip), %rax
	movq	%rax, 16(%rdx)
	movq	_radeon_legacy_get_memory_clock@GOTPCREL(%rip), %rax
	movq	%rax, 8(%rdx)
	movq	$0, (%rdx)
	movq	_radeon_legacy_set_backlight_level@GOTPCREL(%rip), %rax
	movq	%rax, 32(%rdx)
	jmp	LBB0_29
LBB0_19:
	movl	$6, %eax
LBB0_20:
	movl	%eax, 4(%rbx)
	movq	_btc_asic@GOTPCREL(%rip), %rdx
	jmp	LBB0_28
LBB0_14:
	movq	_rs780_asic@GOTPCREL(%rip), %rdx
	jmp	LBB0_28
LBB0_10:
	movq	_rs690_asic@GOTPCREL(%rip), %rdx
	jmp	LBB0_28
LBB0_8:
	movq	_rs400_asic@GOTPCREL(%rip), %rdx
	jmp	LBB0_28
LBB0_25:
	movl	$6, 4(%rbx)
	jmp	LBB0_29
LBB0_5:
	movq	_r300_asic@GOTPCREL(%rip), %rdx
	jmp	LBB0_28
LBB0_26:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	subl	(%rcx), %eax
	jmp	LBB0_31
LBB0_11:
	movq	_rv515_asic@GOTPCREL(%rip), %rdx
	jmp	LBB0_28
LBB0_9:
	movq	_rs600_asic@GOTPCREL(%rip), %rdx
LBB0_28:
	movq	%rdx, 16(%rbx)
LBB0_29:
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rsi
	xorl	%eax, %eax
	testl	%ecx, (%rsi)
	je	LBB0_31
## %bb.30:
	xorps	%xmm0, %xmm0
	movups	%xmm0, (%rdx)
LBB0_31:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
LBB0_21:
	movq	_cayman_asic@GOTPCREL(%rip), %rdx
	movq	%rdx, 16(%rbx)
	movl	$6, 4(%rbx)
	jmp	LBB0_29
LBB0_22:
	movq	_trinity_asic@GOTPCREL(%rip), %rdx
	movq	%rdx, 16(%rbx)
	movl	$4, 4(%rbx)
	jmp	LBB0_29
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_23, LBB0_23-LJTI0_0
.set L0_0_set_19, LBB0_19-LJTI0_0
.set L0_0_set_18, LBB0_18-LJTI0_0
.set L0_0_set_15, LBB0_15-LJTI0_0
.set L0_0_set_13, LBB0_13-LJTI0_0
.set L0_0_set_12, LBB0_12-LJTI0_0
.set L0_0_set_11, LBB0_11-LJTI0_0
.set L0_0_set_6, LBB0_6-LJTI0_0
.set L0_0_set_3, LBB0_3-LJTI0_0
.set L0_0_set_2, LBB0_2-LJTI0_0
.set L0_0_set_27, LBB0_27-LJTI0_0
.set L0_0_set_14, LBB0_14-LJTI0_0
.set L0_0_set_10, LBB0_10-LJTI0_0
.set L0_0_set_9, LBB0_9-LJTI0_0
.set L0_0_set_8, LBB0_8-LJTI0_0
.set L0_0_set_16, LBB0_16-LJTI0_0
.set L0_0_set_17, LBB0_17-LJTI0_0
.set L0_0_set_21, LBB0_21-LJTI0_0
.set L0_0_set_20, LBB0_20-LJTI0_0
.set L0_0_set_22, LBB0_22-LJTI0_0
LJTI0_0:
	.long	L0_0_set_23
	.long	L0_0_set_19
	.long	L0_0_set_23
	.long	L0_0_set_18
	.long	L0_0_set_18
	.long	L0_0_set_15
	.long	L0_0_set_15
	.long	L0_0_set_15
	.long	L0_0_set_15
	.long	L0_0_set_13
	.long	L0_0_set_13
	.long	L0_0_set_13
	.long	L0_0_set_13
	.long	L0_0_set_13
	.long	L0_0_set_12
	.long	L0_0_set_12
	.long	L0_0_set_12
	.long	L0_0_set_11
	.long	L0_0_set_6
	.long	L0_0_set_3
	.long	L0_0_set_3
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_10
	.long	L0_0_set_10
	.long	L0_0_set_9
	.long	L0_0_set_8
	.long	L0_0_set_8
	.long	L0_0_set_2
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_16
	.long	L0_0_set_13
	.long	L0_0_set_12
	.long	L0_0_set_12
	.long	L0_0_set_6
	.long	L0_0_set_6
	.long	L0_0_set_3
	.long	L0_0_set_3
	.long	L0_0_set_2
	.long	L0_0_set_27
	.long	L0_0_set_23
	.long	L0_0_set_18
	.long	L0_0_set_23
	.long	L0_0_set_16
	.long	L0_0_set_16
	.long	L0_0_set_16
	.long	L0_0_set_17
	.long	L0_0_set_21
	.long	L0_0_set_20
	.long	L0_0_set_19
	.long	L0_0_set_22
	.end_data_region
                                        ## -- End function
	.comm	_RADEON_SINGLE_CRTC,4,2         ## @RADEON_SINGLE_CRTC
	.comm	_r100_asic,40,3                 ## @r100_asic
	.comm	_r200_asic,40,3                 ## @r200_asic
	.comm	_RADEON_IS_PCIE,4,2             ## @RADEON_IS_PCIE
	.comm	_r300_asic_pcie,40,3            ## @r300_asic_pcie
	.comm	_r300_asic,40,3                 ## @r300_asic
	.comm	_r420_asic,40,3                 ## @r420_asic
	.comm	_radeon_legacy_get_engine_clock,4,2 ## @radeon_legacy_get_engine_clock
	.comm	_radeon_legacy_set_engine_clock,4,2 ## @radeon_legacy_set_engine_clock
	.comm	_radeon_legacy_get_memory_clock,4,2 ## @radeon_legacy_get_memory_clock
	.comm	_radeon_legacy_set_backlight_level,4,2 ## @radeon_legacy_set_backlight_level
	.comm	_rs400_asic,40,3                ## @rs400_asic
	.comm	_rs600_asic,40,3                ## @rs600_asic
	.comm	_rs690_asic,40,3                ## @rs690_asic
	.comm	_rv515_asic,40,3                ## @rv515_asic
	.comm	_r520_asic,40,3                 ## @r520_asic
	.comm	_r600_asic,40,3                 ## @r600_asic
	.comm	_rs780_asic,40,3                ## @rs780_asic
	.comm	_rv770_asic,40,3                ## @rv770_asic
	.comm	_evergreen_asic,40,3            ## @evergreen_asic
	.comm	_sumo_asic,40,3                 ## @sumo_asic
	.comm	_btc_asic,40,3                  ## @btc_asic
	.comm	_cayman_asic,40,3               ## @cayman_asic
	.comm	_trinity_asic,40,3              ## @trinity_asic
	.comm	_si_asic,40,3                   ## @si_asic
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_asic_init               ; -- Begin function radeon_asic_init
	.p2align	2
_radeon_asic_init:                      ; @radeon_asic_init
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_radeon_register_accessor_init
	ldr	w8, [x19]
Lloh0:
	adrp	x9, _RADEON_SINGLE_CRTC@GOTPAGE
Lloh1:
	ldr	x9, [x9, _RADEON_SINGLE_CRTC@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	mov	w9, #1
	cinc	w9, w9, eq
	str	w9, [x19, #4]
	ldr	w10, [x19, #8]
	sub	w11, w10, #128
	cmp	w11, #55
	b.hi	LBB0_24
; %bb.1:
	mov	w9, #4
Lloh3:
	adrp	x12, lJTI0_0@PAGE
Lloh4:
	add	x12, x12, lJTI0_0@PAGEOFF
	adr	x13, LBB0_2
	ldrb	w14, [x12, x11]
	add	x13, x13, x14, lsl #2
	br	x13
LBB0_2:
Lloh5:
	adrp	x9, _r600_asic@GOTPAGE
Lloh6:
	ldr	x9, [x9, _r600_asic@GOTPAGEOFF]
	b	LBB0_27
LBB0_3:
Lloh7:
	adrp	x9, _r520_asic@GOTPAGE
Lloh8:
	ldr	x9, [x9, _r520_asic@GOTPAGEOFF]
	b	LBB0_27
LBB0_4:
Lloh9:
	adrp	x9, _r100_asic@GOTPAGE
Lloh10:
	ldr	x9, [x9, _r100_asic@GOTPAGEOFF]
	b	LBB0_27
LBB0_5:
Lloh11:
	adrp	x9, _si_asic@GOTPAGE
Lloh12:
	ldr	x9, [x9, _si_asic@GOTPAGEOFF]
	str	x9, [x19, #16]
	cmp	w10, #175
	b.ne	LBB0_21
; %bb.6:
	mov	w9, #2
	b	LBB0_22
LBB0_7:
Lloh13:
	adrp	x9, _rv770_asic@GOTPAGE
Lloh14:
	ldr	x9, [x9, _rv770_asic@GOTPAGEOFF]
	b	LBB0_27
LBB0_8:
Lloh15:
	adrp	x9, _RADEON_IS_PCIE@GOTPAGE
Lloh16:
	ldr	x9, [x9, _RADEON_IS_PCIE@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_23
; %bb.9:
Lloh18:
	adrp	x9, _r300_asic_pcie@GOTPAGE
Lloh19:
	ldr	x9, [x9, _r300_asic_pcie@GOTPAGEOFF]
	b	LBB0_27
LBB0_10:
Lloh20:
	adrp	x9, _r200_asic@GOTPAGE
Lloh21:
	ldr	x9, [x9, _r200_asic@GOTPAGEOFF]
	b	LBB0_27
LBB0_11:
	mov	w9, #6
LBB0_12:
	str	w9, [x19, #4]
Lloh22:
	adrp	x9, _evergreen_asic@GOTPAGE
Lloh23:
	ldr	x9, [x9, _evergreen_asic@GOTPAGEOFF]
	b	LBB0_27
LBB0_13:
Lloh24:
	adrp	x9, _sumo_asic@GOTPAGE
Lloh25:
	ldr	x9, [x9, _sumo_asic@GOTPAGEOFF]
	b	LBB0_27
LBB0_14:
Lloh26:
	adrp	x9, _r420_asic@GOTPAGE
Lloh27:
	ldr	x9, [x9, _r420_asic@GOTPAGEOFF]
	str	x9, [x19, #16]
	ldr	x10, [x19, #24]
	cbnz	x10, LBB0_28
; %bb.15:
Lloh28:
	adrp	x10, _radeon_legacy_get_engine_clock@GOTPAGE
Lloh29:
	ldr	x10, [x10, _radeon_legacy_get_engine_clock@GOTPAGEOFF]
Lloh30:
	adrp	x11, _radeon_legacy_set_engine_clock@GOTPAGE
Lloh31:
	ldr	x11, [x11, _radeon_legacy_set_engine_clock@GOTPAGEOFF]
Lloh32:
	adrp	x12, _radeon_legacy_get_memory_clock@GOTPAGE
Lloh33:
	ldr	x12, [x12, _radeon_legacy_get_memory_clock@GOTPAGEOFF]
	stp	x11, x10, [x9, #16]
	stp	xzr, x12, [x9]
Lloh34:
	adrp	x10, _radeon_legacy_set_backlight_level@GOTPAGE
Lloh35:
	ldr	x10, [x10, _radeon_legacy_set_backlight_level@GOTPAGEOFF]
	str	x10, [x9, #32]
	b	LBB0_28
LBB0_16:
	mov	w9, #6
LBB0_17:
	str	w9, [x19, #4]
Lloh36:
	adrp	x9, _btc_asic@GOTPAGE
Lloh37:
	ldr	x9, [x9, _btc_asic@GOTPAGEOFF]
	b	LBB0_27
LBB0_18:
Lloh38:
	adrp	x9, _rs780_asic@GOTPAGE
Lloh39:
	ldr	x9, [x9, _rs780_asic@GOTPAGEOFF]
	b	LBB0_27
LBB0_19:
Lloh40:
	adrp	x9, _rs690_asic@GOTPAGE
Lloh41:
	ldr	x9, [x9, _rs690_asic@GOTPAGEOFF]
	b	LBB0_27
LBB0_20:
Lloh42:
	adrp	x9, _rs400_asic@GOTPAGE
Lloh43:
	ldr	x9, [x9, _rs400_asic@GOTPAGEOFF]
	b	LBB0_27
LBB0_21:
	mov	w9, #6
LBB0_22:
	str	w9, [x19, #4]
Lloh44:
	adrp	x9, _si_asic@GOTPAGE
Lloh45:
	ldr	x9, [x9, _si_asic@GOTPAGEOFF]
	b	LBB0_28
LBB0_23:
Lloh46:
	adrp	x9, _r300_asic@GOTPAGE
Lloh47:
	ldr	x9, [x9, _r300_asic@GOTPAGEOFF]
	b	LBB0_27
LBB0_24:
Lloh48:
	adrp	x8, _EINVAL@GOTPAGE
Lloh49:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh50:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_31
LBB0_25:
Lloh51:
	adrp	x9, _rv515_asic@GOTPAGE
Lloh52:
	ldr	x9, [x9, _rv515_asic@GOTPAGEOFF]
	b	LBB0_27
LBB0_26:
Lloh53:
	adrp	x9, _rs600_asic@GOTPAGE
Lloh54:
	ldr	x9, [x9, _rs600_asic@GOTPAGEOFF]
LBB0_27:
	str	x9, [x19, #16]
LBB0_28:
Lloh55:
	adrp	x10, _RADEON_IS_IGP@GOTPAGE
Lloh56:
	ldr	x10, [x10, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh57:
	ldr	w10, [x10]
	tst	w10, w8
	b.eq	LBB0_30
; %bb.29:
	mov	w0, #0
	stp	xzr, xzr, [x9]
	b	LBB0_31
LBB0_30:
	mov	w0, #0
LBB0_31:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_32:
Lloh58:
	adrp	x9, _cayman_asic@GOTPAGE
Lloh59:
	ldr	x9, [x9, _cayman_asic@GOTPAGEOFF]
	str	x9, [x19, #16]
	mov	w10, #6
	str	w10, [x19, #4]
	b	LBB0_28
LBB0_33:
Lloh60:
	adrp	x9, _trinity_asic@GOTPAGE
Lloh61:
	ldr	x9, [x9, _trinity_asic@GOTPAGEOFF]
	str	x9, [x19, #16]
	mov	w10, #4
	str	w10, [x19, #4]
	b	LBB0_28
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGot	Lloh60, Lloh61
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_16-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_13-LBB0_2)>>2
	.byte	(LBB0_13-LBB0_2)>>2
	.byte	(LBB0_7-LBB0_2)>>2
	.byte	(LBB0_7-LBB0_2)>>2
	.byte	(LBB0_7-LBB0_2)>>2
	.byte	(LBB0_7-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_3-LBB0_2)>>2
	.byte	(LBB0_3-LBB0_2)>>2
	.byte	(LBB0_3-LBB0_2)>>2
	.byte	(LBB0_25-LBB0_2)>>2
	.byte	(LBB0_14-LBB0_2)>>2
	.byte	(LBB0_8-LBB0_2)>>2
	.byte	(LBB0_8-LBB0_2)>>2
	.byte	(LBB0_10-LBB0_2)>>2
	.byte	(LBB0_10-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_18-LBB0_2)>>2
	.byte	(LBB0_18-LBB0_2)>>2
	.byte	(LBB0_19-LBB0_2)>>2
	.byte	(LBB0_19-LBB0_2)>>2
	.byte	(LBB0_26-LBB0_2)>>2
	.byte	(LBB0_20-LBB0_2)>>2
	.byte	(LBB0_20-LBB0_2)>>2
	.byte	(LBB0_10-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_11-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_3-LBB0_2)>>2
	.byte	(LBB0_3-LBB0_2)>>2
	.byte	(LBB0_14-LBB0_2)>>2
	.byte	(LBB0_14-LBB0_2)>>2
	.byte	(LBB0_8-LBB0_2)>>2
	.byte	(LBB0_8-LBB0_2)>>2
	.byte	(LBB0_10-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_13-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_11-LBB0_2)>>2
	.byte	(LBB0_11-LBB0_2)>>2
	.byte	(LBB0_11-LBB0_2)>>2
	.byte	(LBB0_12-LBB0_2)>>2
	.byte	(LBB0_32-LBB0_2)>>2
	.byte	(LBB0_17-LBB0_2)>>2
	.byte	(LBB0_16-LBB0_2)>>2
	.byte	(LBB0_33-LBB0_2)>>2
                                        ; -- End function
	.comm	_RADEON_SINGLE_CRTC,4,2         ; @RADEON_SINGLE_CRTC
	.comm	_r100_asic,40,3                 ; @r100_asic
	.comm	_r200_asic,40,3                 ; @r200_asic
	.comm	_RADEON_IS_PCIE,4,2             ; @RADEON_IS_PCIE
	.comm	_r300_asic_pcie,40,3            ; @r300_asic_pcie
	.comm	_r300_asic,40,3                 ; @r300_asic
	.comm	_r420_asic,40,3                 ; @r420_asic
	.comm	_radeon_legacy_get_engine_clock,4,2 ; @radeon_legacy_get_engine_clock
	.comm	_radeon_legacy_set_engine_clock,4,2 ; @radeon_legacy_set_engine_clock
	.comm	_radeon_legacy_get_memory_clock,4,2 ; @radeon_legacy_get_memory_clock
	.comm	_radeon_legacy_set_backlight_level,4,2 ; @radeon_legacy_set_backlight_level
	.comm	_rs400_asic,40,3                ; @rs400_asic
	.comm	_rs600_asic,40,3                ; @rs600_asic
	.comm	_rs690_asic,40,3                ; @rs690_asic
	.comm	_rv515_asic,40,3                ; @rv515_asic
	.comm	_r520_asic,40,3                 ; @r520_asic
	.comm	_r600_asic,40,3                 ; @r600_asic
	.comm	_rs780_asic,40,3                ; @rs780_asic
	.comm	_rv770_asic,40,3                ; @rv770_asic
	.comm	_evergreen_asic,40,3            ; @evergreen_asic
	.comm	_sumo_asic,40,3                 ; @sumo_asic
	.comm	_btc_asic,40,3                  ; @btc_asic
	.comm	_cayman_asic,40,3               ; @cayman_asic
	.comm	_trinity_asic,40,3              ; @trinity_asic
	.comm	_si_asic,40,3                   ; @si_asic
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
.subsections_via_symbols
