	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function evergreen_gpu_check_soft_reset
_evergreen_gpu_check_soft_reset:        ## @evergreen_gpu_check_soft_reset
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, -48(%rbp)                 ## 8-byte Spill
	movq	_GRBM_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_PA_BUSY@GOTPCREL(%rip), %rdx
	movq	_SC_BUSY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rdx), %ecx
	movq	_SH_BUSY@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_SX_BUSY@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_TA_BUSY@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_VGT_BUSY@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_DB_BUSY@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_CB_BUSY@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_SPI_BUSY@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_VGT_BUSY_NO_DMA@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	andl	%eax, %ecx
	movq	_RADEON_RESET_GFX@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	cmovnel	%edx, %ecx
	movq	_CF_RQ_PENDING@GOTPCREL(%rip), %rsi
	movq	_PF_RQ_PENDING@GOTPCREL(%rip), %rdi
	movl	(%rdi), %edi
	orl	(%rsi), %edi
	movq	_CP_BUSY@GOTPCREL(%rip), %rsi
	orl	(%rsi), %edi
	movq	_CP_COHERENCY_BUSY@GOTPCREL(%rip), %rsi
	orl	(%rsi), %edi
	andl	%eax, %edi
	movq	_RADEON_RESET_CP@GOTPCREL(%rip), %rsi
	movl	(%rsi), %ebx
	cmovnel	%ebx, %edi
	orl	%ecx, %edi
	movq	_GRBM_EE_BUSY@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_RADEON_RESET_GRBM@GOTPCREL(%rip), %rcx
	orl	%edx, %ebx
	orl	(%rcx), %ebx
	testl	%eax, %eax
	cmovel	%edi, %ebx
	movq	_DMA_STATUS_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_DMA_IDLE@GOTPCREL(%rip), %rcx
	xorl	%r12d, %r12d
	movq	_RADEON_RESET_DMA@GOTPCREL(%rip), %r14
	movl	$0, %r13d
	andl	(%rcx), %eax
	jne	LBB0_2
## %bb.1:
	movl	(%r14), %r13d
LBB0_2:
	movq	_SRBM_STATUS2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r15d
	movq	_DMA_BUSY@GOTPCREL(%rip), %rax
	andl	(%rax), %r15d
	je	LBB0_4
## %bb.3:
	movl	(%r14), %r15d
LBB0_4:
	movq	_SRBM_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_RLC_RQ_PENDING@GOTPCREL(%rip), %rdx
	movq	_RLC_BUSY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rdx), %ecx
	andl	%eax, %ecx
	je	LBB0_6
## %bb.5:
	movq	_RADEON_RESET_RLC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_6:
	movq	_IH_BUSY@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	andl	%eax, %esi
	je	LBB0_8
## %bb.7:
	movq	_RADEON_RESET_IH@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
LBB0_8:
	movq	_SEM_BUSY@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	andl	%eax, %edx
	je	LBB0_10
## %bb.9:
	movq	_RADEON_RESET_SEM@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
LBB0_10:
	movq	_GRBM_RQ_PENDING@GOTPCREL(%rip), %rdi
	movl	(%rdi), %r14d
	andl	%eax, %r14d
	je	LBB0_12
## %bb.11:
	movq	_RADEON_RESET_GRBM@GOTPCREL(%rip), %rdi
	movl	(%rdi), %r14d
LBB0_12:
	orl	%r15d, %r13d
	orl	%esi, %ecx
	movq	_VMC_BUSY@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	movq	_RADEON_RESET_VMC@GOTPCREL(%rip), %r15
	andl	%eax, %esi
	je	LBB0_14
## %bb.13:
	movl	(%r15), %esi
LBB0_14:
	orl	%esi, %r14d
	orl	%r13d, %ebx
	orl	%edx, %ecx
	movq	_MCB_BUSY@GOTPCREL(%rip), %rsi
	movq	_MCB_NON_DISPLAY_BUSY@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rsi), %edx
	movq	_MCC_BUSY@GOTPCREL(%rip), %rsi
	orl	(%rsi), %edx
	movq	_MCD_BUSY@GOTPCREL(%rip), %rsi
	orl	(%rsi), %edx
	movq	_RADEON_RESET_MC@GOTPCREL(%rip), %r13
	andl	%eax, %edx
	je	LBB0_16
## %bb.15:
	movl	(%r13), %edx
LBB0_16:
	orl	%edx, %r14d
	orl	%ecx, %ebx
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_evergreen_is_display_hung
	testq	%rax, %rax
	je	LBB0_18
## %bb.17:
	movq	_RADEON_RESET_DISPLAY@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
LBB0_18:
	orl	%r12d, %r14d
	orl	%r14d, %ebx
	movq	_VM_L2_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_L2_BUSY@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	je	LBB0_20
## %bb.19:
	movl	(%r15), %eax
LBB0_20:
	orl	%eax, %ebx
	testl	%ebx, (%r13)
	je	LBB0_22
## %bb.21:
	leaq	L_.str(%rip), %rdi
	movl	%ebx, %esi
	callq	_DRM_DEBUG
	movl	(%r13), %eax
	notl	%eax
	andl	%eax, %ebx
LBB0_22:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_GRBM_STATUS,4,2                ## @GRBM_STATUS
	.comm	_PA_BUSY,4,2                    ## @PA_BUSY
	.comm	_SC_BUSY,4,2                    ## @SC_BUSY
	.comm	_SH_BUSY,4,2                    ## @SH_BUSY
	.comm	_SX_BUSY,4,2                    ## @SX_BUSY
	.comm	_TA_BUSY,4,2                    ## @TA_BUSY
	.comm	_VGT_BUSY,4,2                   ## @VGT_BUSY
	.comm	_DB_BUSY,4,2                    ## @DB_BUSY
	.comm	_CB_BUSY,4,2                    ## @CB_BUSY
	.comm	_SPI_BUSY,4,2                   ## @SPI_BUSY
	.comm	_VGT_BUSY_NO_DMA,4,2            ## @VGT_BUSY_NO_DMA
	.comm	_RADEON_RESET_GFX,4,2           ## @RADEON_RESET_GFX
	.comm	_CF_RQ_PENDING,4,2              ## @CF_RQ_PENDING
	.comm	_PF_RQ_PENDING,4,2              ## @PF_RQ_PENDING
	.comm	_CP_BUSY,4,2                    ## @CP_BUSY
	.comm	_CP_COHERENCY_BUSY,4,2          ## @CP_COHERENCY_BUSY
	.comm	_RADEON_RESET_CP,4,2            ## @RADEON_RESET_CP
	.comm	_GRBM_EE_BUSY,4,2               ## @GRBM_EE_BUSY
	.comm	_RADEON_RESET_GRBM,4,2          ## @RADEON_RESET_GRBM
	.comm	_DMA_STATUS_REG,4,2             ## @DMA_STATUS_REG
	.comm	_DMA_IDLE,4,2                   ## @DMA_IDLE
	.comm	_RADEON_RESET_DMA,4,2           ## @RADEON_RESET_DMA
	.comm	_SRBM_STATUS2,4,2               ## @SRBM_STATUS2
	.comm	_DMA_BUSY,4,2                   ## @DMA_BUSY
	.comm	_SRBM_STATUS,4,2                ## @SRBM_STATUS
	.comm	_RLC_RQ_PENDING,4,2             ## @RLC_RQ_PENDING
	.comm	_RLC_BUSY,4,2                   ## @RLC_BUSY
	.comm	_RADEON_RESET_RLC,4,2           ## @RADEON_RESET_RLC
	.comm	_IH_BUSY,4,2                    ## @IH_BUSY
	.comm	_RADEON_RESET_IH,4,2            ## @RADEON_RESET_IH
	.comm	_SEM_BUSY,4,2                   ## @SEM_BUSY
	.comm	_RADEON_RESET_SEM,4,2           ## @RADEON_RESET_SEM
	.comm	_GRBM_RQ_PENDING,4,2            ## @GRBM_RQ_PENDING
	.comm	_VMC_BUSY,4,2                   ## @VMC_BUSY
	.comm	_RADEON_RESET_VMC,4,2           ## @RADEON_RESET_VMC
	.comm	_MCB_BUSY,4,2                   ## @MCB_BUSY
	.comm	_MCB_NON_DISPLAY_BUSY,4,2       ## @MCB_NON_DISPLAY_BUSY
	.comm	_MCC_BUSY,4,2                   ## @MCC_BUSY
	.comm	_MCD_BUSY,4,2                   ## @MCD_BUSY
	.comm	_RADEON_RESET_MC,4,2            ## @RADEON_RESET_MC
	.comm	_RADEON_RESET_DISPLAY,4,2       ## @RADEON_RESET_DISPLAY
	.comm	_VM_L2_STATUS,4,2               ## @VM_L2_STATUS
	.comm	_L2_BUSY,4,2                    ## @L2_BUSY
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"MC busy: 0x%08X, clearing.\n"

	.no_dead_strip	_evergreen_gpu_check_soft_reset
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function evergreen_gpu_check_soft_reset
_evergreen_gpu_check_soft_reset:        ; @evergreen_gpu_check_soft_reset
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, _GRBM_STATUS@GOTPAGE
Lloh1:
	ldr	x8, [x8, _GRBM_STATUS@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_RREG32
Lloh3:
	adrp	x8, _PA_BUSY@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PA_BUSY@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
Lloh6:
	adrp	x9, _SC_BUSY@GOTPAGE
Lloh7:
	ldr	x9, [x9, _SC_BUSY@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh9:
	adrp	x9, _SH_BUSY@GOTPAGE
Lloh10:
	ldr	x9, [x9, _SH_BUSY@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
Lloh12:
	adrp	x10, _SX_BUSY@GOTPAGE
Lloh13:
	ldr	x10, [x10, _SX_BUSY@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh14:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh15:
	adrp	x9, _TA_BUSY@GOTPAGE
Lloh16:
	ldr	x9, [x9, _TA_BUSY@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh18:
	adrp	x9, _VGT_BUSY@GOTPAGE
Lloh19:
	ldr	x9, [x9, _VGT_BUSY@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
Lloh21:
	adrp	x10, _DB_BUSY@GOTPAGE
Lloh22:
	ldr	x10, [x10, _DB_BUSY@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh23:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh24:
	adrp	x9, _CB_BUSY@GOTPAGE
Lloh25:
	ldr	x9, [x9, _CB_BUSY@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh27:
	adrp	x9, _SPI_BUSY@GOTPAGE
Lloh28:
	ldr	x9, [x9, _SPI_BUSY@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
Lloh30:
	adrp	x10, _VGT_BUSY_NO_DMA@GOTPAGE
Lloh31:
	ldr	x10, [x10, _VGT_BUSY_NO_DMA@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh32:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh33:
	adrp	x9, _RADEON_RESET_GFX@GOTPAGE
Lloh34:
	ldr	x9, [x9, _RADEON_RESET_GFX@GOTPAGEOFF]
Lloh35:
	ldr	w9, [x9]
	tst	w8, w0
	csel	w8, wzr, w9, eq
Lloh36:
	adrp	x10, _CF_RQ_PENDING@GOTPAGE
Lloh37:
	ldr	x10, [x10, _CF_RQ_PENDING@GOTPAGEOFF]
Lloh38:
	adrp	x11, _PF_RQ_PENDING@GOTPAGE
Lloh39:
	ldr	x11, [x11, _PF_RQ_PENDING@GOTPAGEOFF]
Lloh40:
	ldr	w10, [x10]
Lloh41:
	ldr	w11, [x11]
	orr	w10, w11, w10
Lloh42:
	adrp	x11, _CP_BUSY@GOTPAGE
Lloh43:
	ldr	x11, [x11, _CP_BUSY@GOTPAGEOFF]
Lloh44:
	ldr	w11, [x11]
	orr	w10, w10, w11
Lloh45:
	adrp	x11, _CP_COHERENCY_BUSY@GOTPAGE
Lloh46:
	ldr	x11, [x11, _CP_COHERENCY_BUSY@GOTPAGEOFF]
Lloh47:
	ldr	w11, [x11]
Lloh48:
	adrp	x12, _RADEON_RESET_CP@GOTPAGE
Lloh49:
	ldr	x12, [x12, _RADEON_RESET_CP@GOTPAGEOFF]
	orr	w10, w10, w11
Lloh50:
	ldr	w11, [x12]
	tst	w10, w0
	csel	w10, wzr, w11, eq
Lloh51:
	adrp	x12, _GRBM_EE_BUSY@GOTPAGE
Lloh52:
	ldr	x12, [x12, _GRBM_EE_BUSY@GOTPAGEOFF]
	orr	w8, w10, w8
Lloh53:
	ldr	w10, [x12]
Lloh54:
	adrp	x20, _RADEON_RESET_GRBM@GOTPAGE
Lloh55:
	ldr	x20, [x20, _RADEON_RESET_GRBM@GOTPAGEOFF]
	ldr	w12, [x20]
	orr	w9, w11, w9
	orr	w9, w9, w12
	tst	w10, w0
	csel	w21, w8, w9, eq
Lloh56:
	adrp	x8, _DMA_STATUS_REG@GOTPAGE
Lloh57:
	ldr	x8, [x8, _DMA_STATUS_REG@GOTPAGEOFF]
Lloh58:
	ldr	w0, [x8]
	bl	_RREG32
Lloh59:
	adrp	x8, _DMA_IDLE@GOTPAGE
Lloh60:
	ldr	x8, [x8, _DMA_IDLE@GOTPAGEOFF]
Lloh61:
	ldr	w8, [x8]
Lloh62:
	adrp	x22, _RADEON_RESET_DMA@GOTPAGE
Lloh63:
	ldr	x22, [x22, _RADEON_RESET_DMA@GOTPAGEOFF]
	ldr	w9, [x22]
	tst	w8, w0
	csel	w8, w9, wzr, eq
	orr	w21, w8, w21
Lloh64:
	adrp	x8, _SRBM_STATUS2@GOTPAGE
Lloh65:
	ldr	x8, [x8, _SRBM_STATUS2@GOTPAGEOFF]
Lloh66:
	ldr	w0, [x8]
	bl	_RREG32
Lloh67:
	adrp	x8, _DMA_BUSY@GOTPAGE
Lloh68:
	ldr	x8, [x8, _DMA_BUSY@GOTPAGEOFF]
Lloh69:
	ldr	w8, [x8]
	ldr	w9, [x22]
	tst	w8, w0
	csel	w8, wzr, w9, eq
	orr	w21, w21, w8
Lloh70:
	adrp	x8, _SRBM_STATUS@GOTPAGE
Lloh71:
	ldr	x8, [x8, _SRBM_STATUS@GOTPAGEOFF]
Lloh72:
	ldr	w0, [x8]
	bl	_RREG32
Lloh73:
	adrp	x8, _RLC_RQ_PENDING@GOTPAGE
Lloh74:
	ldr	x8, [x8, _RLC_RQ_PENDING@GOTPAGEOFF]
Lloh75:
	ldr	w8, [x8]
Lloh76:
	adrp	x9, _RLC_BUSY@GOTPAGE
Lloh77:
	ldr	x9, [x9, _RLC_BUSY@GOTPAGEOFF]
Lloh78:
	ldr	w9, [x9]
Lloh79:
	adrp	x10, _RADEON_RESET_RLC@GOTPAGE
Lloh80:
	ldr	x10, [x10, _RADEON_RESET_RLC@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh81:
	ldr	w9, [x10]
	tst	w8, w0
	csel	w8, wzr, w9, eq
Lloh82:
	adrp	x9, _IH_BUSY@GOTPAGE
Lloh83:
	ldr	x9, [x9, _IH_BUSY@GOTPAGEOFF]
	orr	w8, w21, w8
Lloh84:
	ldr	w9, [x9]
Lloh85:
	adrp	x10, _RADEON_RESET_IH@GOTPAGE
Lloh86:
	ldr	x10, [x10, _RADEON_RESET_IH@GOTPAGEOFF]
Lloh87:
	ldr	w10, [x10]
	tst	w9, w0
	csel	w9, wzr, w10, eq
	orr	w8, w8, w9
Lloh88:
	adrp	x9, _SEM_BUSY@GOTPAGE
Lloh89:
	ldr	x9, [x9, _SEM_BUSY@GOTPAGEOFF]
Lloh90:
	adrp	x10, _RADEON_RESET_SEM@GOTPAGE
Lloh91:
	ldr	x10, [x10, _RADEON_RESET_SEM@GOTPAGEOFF]
Lloh92:
	ldr	w9, [x9]
Lloh93:
	ldr	w10, [x10]
	tst	w9, w0
	csel	w9, wzr, w10, eq
Lloh94:
	adrp	x10, _GRBM_RQ_PENDING@GOTPAGE
Lloh95:
	ldr	x10, [x10, _GRBM_RQ_PENDING@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh96:
	ldr	w9, [x10]
	ldr	w10, [x20]
	tst	w9, w0
	csel	w9, wzr, w10, eq
	orr	w8, w8, w9
Lloh97:
	adrp	x9, _VMC_BUSY@GOTPAGE
Lloh98:
	ldr	x9, [x9, _VMC_BUSY@GOTPAGEOFF]
Lloh99:
	ldr	w9, [x9]
Lloh100:
	adrp	x21, _RADEON_RESET_VMC@GOTPAGE
Lloh101:
	ldr	x21, [x21, _RADEON_RESET_VMC@GOTPAGEOFF]
	ldr	w10, [x21]
	tst	w9, w0
	csel	w9, wzr, w10, eq
	orr	w8, w8, w9
Lloh102:
	adrp	x9, _MCB_BUSY@GOTPAGE
Lloh103:
	ldr	x9, [x9, _MCB_BUSY@GOTPAGEOFF]
Lloh104:
	ldr	w9, [x9]
Lloh105:
	adrp	x10, _MCB_NON_DISPLAY_BUSY@GOTPAGE
Lloh106:
	ldr	x10, [x10, _MCB_NON_DISPLAY_BUSY@GOTPAGEOFF]
Lloh107:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh108:
	adrp	x10, _MCC_BUSY@GOTPAGE
Lloh109:
	ldr	x10, [x10, _MCC_BUSY@GOTPAGEOFF]
Lloh110:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh111:
	adrp	x10, _MCD_BUSY@GOTPAGE
Lloh112:
	ldr	x10, [x10, _MCD_BUSY@GOTPAGEOFF]
Lloh113:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh114:
	adrp	x20, _RADEON_RESET_MC@GOTPAGE
Lloh115:
	ldr	x20, [x20, _RADEON_RESET_MC@GOTPAGEOFF]
	ldr	w10, [x20]
	tst	w9, w0
	csel	w9, wzr, w10, eq
	orr	w22, w8, w9
	mov	x0, x19
	bl	_evergreen_is_display_hung
Lloh116:
	adrp	x8, _RADEON_RESET_DISPLAY@GOTPAGE
Lloh117:
	ldr	x8, [x8, _RADEON_RESET_DISPLAY@GOTPAGEOFF]
Lloh118:
	ldr	w8, [x8]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w19, w22, w8
Lloh119:
	adrp	x8, _VM_L2_STATUS@GOTPAGE
Lloh120:
	ldr	x8, [x8, _VM_L2_STATUS@GOTPAGEOFF]
Lloh121:
	ldr	w0, [x8]
	bl	_RREG32
Lloh122:
	adrp	x8, _L2_BUSY@GOTPAGE
Lloh123:
	ldr	x8, [x8, _L2_BUSY@GOTPAGEOFF]
Lloh124:
	ldr	w8, [x8]
	ldr	w9, [x21]
	tst	w8, w0
	csel	w8, wzr, w9, eq
	orr	w19, w19, w8
	ldr	w8, [x20]
	tst	w19, w8
	b.eq	LBB0_2
; %bb.1:
Lloh125:
	adrp	x0, l_.str@PAGE
Lloh126:
	add	x0, x0, l_.str@PAGEOFF
	mov	x1, x19
	bl	_DRM_DEBUG
	ldr	w8, [x20]
	bic	w19, w19, w8
LBB0_2:
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGot	Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGot	Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh92
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGot	Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGot	Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh40
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh125, Lloh126
	.cfi_endproc
                                        ; -- End function
	.comm	_GRBM_STATUS,4,2                ; @GRBM_STATUS
	.comm	_PA_BUSY,4,2                    ; @PA_BUSY
	.comm	_SC_BUSY,4,2                    ; @SC_BUSY
	.comm	_SH_BUSY,4,2                    ; @SH_BUSY
	.comm	_SX_BUSY,4,2                    ; @SX_BUSY
	.comm	_TA_BUSY,4,2                    ; @TA_BUSY
	.comm	_VGT_BUSY,4,2                   ; @VGT_BUSY
	.comm	_DB_BUSY,4,2                    ; @DB_BUSY
	.comm	_CB_BUSY,4,2                    ; @CB_BUSY
	.comm	_SPI_BUSY,4,2                   ; @SPI_BUSY
	.comm	_VGT_BUSY_NO_DMA,4,2            ; @VGT_BUSY_NO_DMA
	.comm	_RADEON_RESET_GFX,4,2           ; @RADEON_RESET_GFX
	.comm	_CF_RQ_PENDING,4,2              ; @CF_RQ_PENDING
	.comm	_PF_RQ_PENDING,4,2              ; @PF_RQ_PENDING
	.comm	_CP_BUSY,4,2                    ; @CP_BUSY
	.comm	_CP_COHERENCY_BUSY,4,2          ; @CP_COHERENCY_BUSY
	.comm	_RADEON_RESET_CP,4,2            ; @RADEON_RESET_CP
	.comm	_GRBM_EE_BUSY,4,2               ; @GRBM_EE_BUSY
	.comm	_RADEON_RESET_GRBM,4,2          ; @RADEON_RESET_GRBM
	.comm	_DMA_STATUS_REG,4,2             ; @DMA_STATUS_REG
	.comm	_DMA_IDLE,4,2                   ; @DMA_IDLE
	.comm	_RADEON_RESET_DMA,4,2           ; @RADEON_RESET_DMA
	.comm	_SRBM_STATUS2,4,2               ; @SRBM_STATUS2
	.comm	_DMA_BUSY,4,2                   ; @DMA_BUSY
	.comm	_SRBM_STATUS,4,2                ; @SRBM_STATUS
	.comm	_RLC_RQ_PENDING,4,2             ; @RLC_RQ_PENDING
	.comm	_RLC_BUSY,4,2                   ; @RLC_BUSY
	.comm	_RADEON_RESET_RLC,4,2           ; @RADEON_RESET_RLC
	.comm	_IH_BUSY,4,2                    ; @IH_BUSY
	.comm	_RADEON_RESET_IH,4,2            ; @RADEON_RESET_IH
	.comm	_SEM_BUSY,4,2                   ; @SEM_BUSY
	.comm	_RADEON_RESET_SEM,4,2           ; @RADEON_RESET_SEM
	.comm	_GRBM_RQ_PENDING,4,2            ; @GRBM_RQ_PENDING
	.comm	_VMC_BUSY,4,2                   ; @VMC_BUSY
	.comm	_RADEON_RESET_VMC,4,2           ; @RADEON_RESET_VMC
	.comm	_MCB_BUSY,4,2                   ; @MCB_BUSY
	.comm	_MCB_NON_DISPLAY_BUSY,4,2       ; @MCB_NON_DISPLAY_BUSY
	.comm	_MCC_BUSY,4,2                   ; @MCC_BUSY
	.comm	_MCD_BUSY,4,2                   ; @MCD_BUSY
	.comm	_RADEON_RESET_MC,4,2            ; @RADEON_RESET_MC
	.comm	_RADEON_RESET_DISPLAY,4,2       ; @RADEON_RESET_DISPLAY
	.comm	_VM_L2_STATUS,4,2               ; @VM_L2_STATUS
	.comm	_L2_BUSY,4,2                    ; @L2_BUSY
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"MC busy: 0x%08X, clearing.\n"

	.no_dead_strip	_evergreen_gpu_check_soft_reset
.subsections_via_symbols
