	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r100_set_surface_reg           ## -- Begin function r100_set_surface_reg
	.p2align	4, 0x90
_r100_set_surface_reg:                  ## @r100_set_surface_reg
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
                                        ## kill: def $r9d killed $r9d def $r9
	movq	%r9, -88(%rbp)                  ## 8-byte Spill
	movl	%r8d, %r9d
	movl	%ecx, %eax
	movl	%edx, %r11d
	movq	(%rdi), %rcx
	movq	_CHIP_RS200@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jle	LBB0_1
## %bb.5:
	movq	_CHIP_RV280@GOTPCREL(%rip), %rdx
	movq	_RADEON_TILING_MACRO@GOTPCREL(%rip), %rbx
	movl	(%rbx), %r8d
	cmpq	(%rdx), %rcx
	jle	LBB0_6
## %bb.10:
	movl	%r8d, %r10d
	andl	%r11d, %r10d
	je	LBB0_12
## %bb.11:
	movq	_R300_SURF_TILE_MACRO@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r10d
LBB0_12:
	movq	_RADEON_TILING_MICRO@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%r11d, %ecx
	je	LBB0_15
## %bb.13:
	movq	_R300_SURF_TILE_MICRO@GOTPCREL(%rip), %rdx
	jmp	LBB0_14
LBB0_1:
	movq	_RADEON_TILING_MACRO@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r8d
	movq	_RADEON_TILING_MICRO@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, %edx
	orl	%r8d, %edx
	movl	%r11d, %ebx
	notl	%ebx
	xorl	%r10d, %r10d
	testl	%ebx, %edx
	jne	LBB0_3
## %bb.2:
	movq	_RADEON_SURF_TILE_COLOR_BOTH@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r10d
LBB0_3:
	testl	%r11d, %r8d
	je	LBB0_15
## %bb.4:
	movq	_RADEON_SURF_TILE_COLOR_MACRO@GOTPCREL(%rip), %rdx
	jmp	LBB0_14
LBB0_6:
	movl	%r8d, %r10d
	andl	%r11d, %r10d
	je	LBB0_8
## %bb.7:
	movq	_R200_SURF_TILE_COLOR_MACRO@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r10d
LBB0_8:
	movq	_RADEON_TILING_MICRO@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%r11d, %ecx
	je	LBB0_15
## %bb.9:
	movq	_R200_SURF_TILE_COLOR_MICRO@GOTPCREL(%rip), %rdx
LBB0_14:
	orl	(%rdx), %r10d
LBB0_15:
	movq	_RADEON_TILING_SWAP_16BIT@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r14d
	movq	_RADEON_SURF_AP0_SWP_16BPP@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movl	%edx, -44(%rbp)                 ## 4-byte Spill
	movq	_RADEON_SURF_AP1_SWP_16BPP@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r13d
	movq	_RADEON_TILING_SWAP_32BIT@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r15d
	movq	_RADEON_SURF_AP0_SWP_32BPP@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movl	%edx, -48(%rbp)                 ## 4-byte Spill
	movq	_RADEON_SURF_AP1_SWP_32BPP@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r12d
	movl	%r15d, %edx
	orl	%r14d, %edx
	testl	%r11d, %edx
	je	LBB0_21
## %bb.16:
	orl	%r8d, %ecx
	testl	%r11d, %ecx
	jne	LBB0_21
## %bb.17:
	movl	%r10d, -52(%rbp)                ## 4-byte Spill
	movl	%r11d, -56(%rbp)                ## 4-byte Spill
	movq	%rax, -72(%rbp)                 ## 8-byte Spill
	movl	%esi, -60(%rbp)                 ## 4-byte Spill
	movq	%r9, -80(%rbp)                  ## 8-byte Spill
	movq	%rdi, %rbx
	callq	_ASIC_IS_RN50
	testq	%rax, %rax
	je	LBB0_18
## %bb.19:
	movq	-72(%rbp), %rcx                 ## 8-byte Reload
	leal	15(%rcx), %eax
	testl	%ecx, %ecx
	cmovnsl	%ecx, %eax
	sarl	$4, %eax
                                        ## kill: def $eax killed $eax def $rax
	movq	-80(%rbp), %r9                  ## 8-byte Reload
	movl	-60(%rbp), %esi                 ## 4-byte Reload
	jmp	LBB0_20
LBB0_18:
	movq	-80(%rbp), %r9                  ## 8-byte Reload
	movl	-60(%rbp), %esi                 ## 4-byte Reload
	movq	-72(%rbp), %rax                 ## 8-byte Reload
LBB0_20:
	movq	%rbx, %rdi
	movl	-56(%rbp), %r11d                ## 4-byte Reload
	movl	-52(%rbp), %r10d                ## 4-byte Reload
LBB0_21:
	movl	-48(%rbp), %r8d                 ## 4-byte Reload
	movl	-44(%rbp), %ebx                 ## 4-byte Reload
	movq	(%rdi), %rdi
	movq	_CHIP_R300@GOTPCREL(%rip), %rcx
	xorl	%edx, %edx
	cmpq	(%rcx), %rdi
	setl	%dl
	andl	%r11d, %r15d
	andl	%r11d, %r14d
	leal	8(,%rdx,8), %ecx
	orl	%ebx, %r13d
                                        ## kill: def $eax killed $eax killed $rax
	cltd
	idivl	%ecx
	testl	%r14d, %r14d
	cmovel	%r14d, %r13d
	orl	%r10d, %r13d
	orl	%r8d, %r12d
	testl	%r15d, %r15d
	cmovel	%r15d, %r12d
	orl	%r13d, %r12d
	orl	%eax, %r12d
	movl	%esi, %ebx
	shll	$4, %ebx
	movq	-88(%rbp), %rax                 ## 8-byte Reload
	leal	(%r9,%rax), %r15d
	decl	%r15d
	leaq	L_.str(%rip), %rdi
	movl	%r12d, %edx
	movl	%r9d, %ecx
	movq	%r9, %r14
	movl	%r15d, %r8d
	callq	_DRM_DEBUG_KMS
	movq	_RADEON_SURFACE0_INFO@GOTPCREL(%rip), %rax
	movslq	%ebx, %rbx
	movq	(%rax), %rdi
	addq	%rbx, %rdi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_RADEON_SURFACE0_LOWER_BOUND@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_RADEON_SURFACE0_UPPER_BOUND@GOTPCREL(%rip), %rax
	addq	(%rax), %rbx
	movq	%rbx, %rdi
	movl	%r15d, %esi
	callq	_WREG32
	xorl	%eax, %eax
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CHIP_RS200,8,3                 ## @CHIP_RS200
	.comm	_RADEON_TILING_MACRO,4,2        ## @RADEON_TILING_MACRO
	.comm	_RADEON_TILING_MICRO,4,2        ## @RADEON_TILING_MICRO
	.comm	_RADEON_SURF_TILE_COLOR_BOTH,4,2 ## @RADEON_SURF_TILE_COLOR_BOTH
	.comm	_RADEON_SURF_TILE_COLOR_MACRO,4,2 ## @RADEON_SURF_TILE_COLOR_MACRO
	.comm	_CHIP_RV280,8,3                 ## @CHIP_RV280
	.comm	_R200_SURF_TILE_COLOR_MACRO,4,2 ## @R200_SURF_TILE_COLOR_MACRO
	.comm	_R200_SURF_TILE_COLOR_MICRO,4,2 ## @R200_SURF_TILE_COLOR_MICRO
	.comm	_R300_SURF_TILE_MACRO,4,2       ## @R300_SURF_TILE_MACRO
	.comm	_R300_SURF_TILE_MICRO,4,2       ## @R300_SURF_TILE_MICRO
	.comm	_RADEON_TILING_SWAP_16BIT,4,2   ## @RADEON_TILING_SWAP_16BIT
	.comm	_RADEON_SURF_AP0_SWP_16BPP,4,2  ## @RADEON_SURF_AP0_SWP_16BPP
	.comm	_RADEON_SURF_AP1_SWP_16BPP,4,2  ## @RADEON_SURF_AP1_SWP_16BPP
	.comm	_RADEON_TILING_SWAP_32BIT,4,2   ## @RADEON_TILING_SWAP_32BIT
	.comm	_RADEON_SURF_AP0_SWP_32BPP,4,2  ## @RADEON_SURF_AP0_SWP_32BPP
	.comm	_RADEON_SURF_AP1_SWP_32BPP,4,2  ## @RADEON_SURF_AP1_SWP_32BPP
	.comm	_CHIP_R300,8,3                  ## @CHIP_R300
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"writing surface %d %d %x %x\n"

	.comm	_RADEON_SURFACE0_INFO,8,3       ## @RADEON_SURFACE0_INFO
	.comm	_RADEON_SURFACE0_LOWER_BOUND,8,3 ## @RADEON_SURFACE0_LOWER_BOUND
	.comm	_RADEON_SURFACE0_UPPER_BOUND,8,3 ## @RADEON_SURFACE0_UPPER_BOUND
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r100_set_surface_reg           ; -- Begin function r100_set_surface_reg
	.p2align	2
_r100_set_surface_reg:                  ; @r100_set_surface_reg
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x4
	mov	x22, x2
	mov	x24, x0
	ldr	x9, [x0]
Lloh0:
	adrp	x8, _CHIP_RS200@GOTPAGE
Lloh1:
	ldr	x8, [x8, _CHIP_RS200@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	cmp	x9, x8
	b.le	LBB0_4
; %bb.1:
Lloh3:
	adrp	x8, _CHIP_RV280@GOTPAGE
Lloh4:
	ldr	x8, [x8, _CHIP_RV280@GOTPAGEOFF]
Lloh5:
	ldr	x11, [x8]
Lloh6:
	adrp	x8, _RADEON_TILING_MACRO@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_TILING_MACRO@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	and	w10, w8, w22
	cmp	x9, x11
	b.le	LBB0_6
; %bb.2:
Lloh9:
	adrp	x9, _R300_SURF_TILE_MACRO@GOTPAGE
Lloh10:
	ldr	x9, [x9, _R300_SURF_TILE_MACRO@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	cmp	w10, #0
	csel	w25, wzr, w9, eq
Lloh12:
	adrp	x9, _RADEON_TILING_MICRO@GOTPAGE
Lloh13:
	ldr	x9, [x9, _RADEON_TILING_MICRO@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	tst	w9, w22
	b.eq	LBB0_9
; %bb.3:
Lloh15:
	adrp	x10, _R300_SURF_TILE_MICRO@GOTPAGE
Lloh16:
	ldr	x10, [x10, _R300_SURF_TILE_MICRO@GOTPAGEOFF]
	b	LBB0_8
LBB0_4:
Lloh17:
	adrp	x8, _RADEON_TILING_MACRO@GOTPAGE
Lloh18:
	ldr	x8, [x8, _RADEON_TILING_MACRO@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
Lloh20:
	adrp	x9, _RADEON_TILING_MICRO@GOTPAGE
Lloh21:
	ldr	x9, [x9, _RADEON_TILING_MICRO@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	orr	w10, w9, w8
Lloh23:
	adrp	x11, _RADEON_SURF_TILE_COLOR_BOTH@GOTPAGE
Lloh24:
	ldr	x11, [x11, _RADEON_SURF_TILE_COLOR_BOTH@GOTPAGEOFF]
Lloh25:
	ldr	w11, [x11]
	bics	wzr, w10, w22
	csel	w25, w11, wzr, eq
	tst	w8, w22
	b.eq	LBB0_9
; %bb.5:
Lloh26:
	adrp	x10, _RADEON_SURF_TILE_COLOR_MACRO@GOTPAGE
Lloh27:
	ldr	x10, [x10, _RADEON_SURF_TILE_COLOR_MACRO@GOTPAGEOFF]
	b	LBB0_8
LBB0_6:
Lloh28:
	adrp	x9, _R200_SURF_TILE_COLOR_MACRO@GOTPAGE
Lloh29:
	ldr	x9, [x9, _R200_SURF_TILE_COLOR_MACRO@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
	cmp	w10, #0
	csel	w25, wzr, w9, eq
Lloh31:
	adrp	x9, _RADEON_TILING_MICRO@GOTPAGE
Lloh32:
	ldr	x9, [x9, _RADEON_TILING_MICRO@GOTPAGEOFF]
Lloh33:
	ldr	w9, [x9]
	tst	w9, w22
	b.eq	LBB0_9
; %bb.7:
Lloh34:
	adrp	x10, _R200_SURF_TILE_COLOR_MICRO@GOTPAGE
Lloh35:
	ldr	x10, [x10, _R200_SURF_TILE_COLOR_MICRO@GOTPAGEOFF]
LBB0_8:
	ldr	w10, [x10]
	orr	w25, w10, w25
LBB0_9:
Lloh36:
	adrp	x10, _RADEON_TILING_SWAP_16BIT@GOTPAGE
Lloh37:
	ldr	x10, [x10, _RADEON_TILING_SWAP_16BIT@GOTPAGEOFF]
Lloh38:
	ldr	w26, [x10]
Lloh39:
	adrp	x10, _RADEON_SURF_AP0_SWP_16BPP@GOTPAGE
Lloh40:
	ldr	x10, [x10, _RADEON_SURF_AP0_SWP_16BPP@GOTPAGEOFF]
Lloh41:
	ldr	w28, [x10]
Lloh42:
	adrp	x10, _RADEON_SURF_AP1_SWP_16BPP@GOTPAGE
Lloh43:
	ldr	x10, [x10, _RADEON_SURF_AP1_SWP_16BPP@GOTPAGEOFF]
Lloh44:
	ldr	w20, [x10]
Lloh45:
	adrp	x10, _RADEON_TILING_SWAP_32BIT@GOTPAGE
Lloh46:
	ldr	x10, [x10, _RADEON_TILING_SWAP_32BIT@GOTPAGEOFF]
Lloh47:
	ldr	w27, [x10]
Lloh48:
	adrp	x10, _RADEON_SURF_AP0_SWP_32BPP@GOTPAGE
Lloh49:
	ldr	x10, [x10, _RADEON_SURF_AP0_SWP_32BPP@GOTPAGEOFF]
Lloh50:
	ldr	w21, [x10]
Lloh51:
	adrp	x10, _RADEON_SURF_AP1_SWP_32BPP@GOTPAGE
Lloh52:
	ldr	x10, [x10, _RADEON_SURF_AP1_SWP_32BPP@GOTPAGEOFF]
Lloh53:
	ldr	w23, [x10]
	orr	w10, w27, w26
	and	w10, w10, w22
	cmp	w10, #0
	orr	w8, w9, w8
	and	w8, w8, w22
	ccmp	w8, #0, #0, ne
	b.ne	LBB0_11
; %bb.10:
	mov	x0, x24
	stp	w5, w1, [sp, #8]                ; 8-byte Folded Spill
	str	w3, [sp, #4]                    ; 4-byte Folded Spill
	bl	_ASIC_IS_RN50
	ldp	w3, w5, [sp, #4]                ; 8-byte Folded Reload
	ldr	w1, [sp, #12]                   ; 4-byte Folded Reload
	add	w8, w3, #15
	cmp	w3, #0
	csel	w8, w8, w3, lt
	asr	w8, w8, #4
	cmp	x0, #0
	csel	w3, w3, w8, eq
LBB0_11:
	ldr	x8, [x24]
Lloh54:
	adrp	x9, _CHIP_R300@GOTPAGE
Lloh55:
	ldr	x9, [x9, _CHIP_R300@GOTPAGEOFF]
Lloh56:
	ldr	x9, [x9]
	cmp	x8, x9
	mov	w8, #8
	mov	w9, #16
	csel	w8, w9, w8, lt
	sdiv	w8, w3, w8
	orr	w9, w20, w28
	tst	w26, w22
	csel	w9, wzr, w9, eq
	orr	w9, w9, w25
	orr	w10, w23, w21
	tst	w27, w22
	csel	w10, wzr, w10, eq
	orr	w9, w9, w10
	orr	w22, w9, w8
	lsl	w20, w1, #4
	add	w8, w19, w5
	sub	w21, w8, #1
Lloh57:
	adrp	x0, l_.str@PAGE
Lloh58:
	add	x0, x0, l_.str@PAGEOFF
	mov	x2, x22
	mov	x3, x19
	mov	x4, x21
	bl	_DRM_DEBUG_KMS
Lloh59:
	adrp	x8, _RADEON_SURFACE0_INFO@GOTPAGE
Lloh60:
	ldr	x8, [x8, _RADEON_SURFACE0_INFO@GOTPAGEOFF]
Lloh61:
	ldr	x8, [x8]
	sxtw	x20, w20
	add	x0, x8, x20
	mov	x1, x22
	bl	_WREG32
Lloh62:
	adrp	x8, _RADEON_SURFACE0_LOWER_BOUND@GOTPAGE
Lloh63:
	ldr	x8, [x8, _RADEON_SURFACE0_LOWER_BOUND@GOTPAGEOFF]
Lloh64:
	ldr	x8, [x8]
	add	x0, x8, x20
	mov	x1, x19
	bl	_WREG32
Lloh65:
	adrp	x8, _RADEON_SURFACE0_UPPER_BOUND@GOTPAGE
Lloh66:
	ldr	x8, [x8, _RADEON_SURFACE0_UPPER_BOUND@GOTPAGEOFF]
Lloh67:
	ldr	x8, [x8]
	add	x0, x8, x20
	mov	x1, x21
	bl	_WREG32
	mov	w0, #0
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpAdd	Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.cfi_endproc
                                        ; -- End function
	.comm	_CHIP_RS200,8,3                 ; @CHIP_RS200
	.comm	_RADEON_TILING_MACRO,4,2        ; @RADEON_TILING_MACRO
	.comm	_RADEON_TILING_MICRO,4,2        ; @RADEON_TILING_MICRO
	.comm	_RADEON_SURF_TILE_COLOR_BOTH,4,2 ; @RADEON_SURF_TILE_COLOR_BOTH
	.comm	_RADEON_SURF_TILE_COLOR_MACRO,4,2 ; @RADEON_SURF_TILE_COLOR_MACRO
	.comm	_CHIP_RV280,8,3                 ; @CHIP_RV280
	.comm	_R200_SURF_TILE_COLOR_MACRO,4,2 ; @R200_SURF_TILE_COLOR_MACRO
	.comm	_R200_SURF_TILE_COLOR_MICRO,4,2 ; @R200_SURF_TILE_COLOR_MICRO
	.comm	_R300_SURF_TILE_MACRO,4,2       ; @R300_SURF_TILE_MACRO
	.comm	_R300_SURF_TILE_MICRO,4,2       ; @R300_SURF_TILE_MICRO
	.comm	_RADEON_TILING_SWAP_16BIT,4,2   ; @RADEON_TILING_SWAP_16BIT
	.comm	_RADEON_SURF_AP0_SWP_16BPP,4,2  ; @RADEON_SURF_AP0_SWP_16BPP
	.comm	_RADEON_SURF_AP1_SWP_16BPP,4,2  ; @RADEON_SURF_AP1_SWP_16BPP
	.comm	_RADEON_TILING_SWAP_32BIT,4,2   ; @RADEON_TILING_SWAP_32BIT
	.comm	_RADEON_SURF_AP0_SWP_32BPP,4,2  ; @RADEON_SURF_AP0_SWP_32BPP
	.comm	_RADEON_SURF_AP1_SWP_32BPP,4,2  ; @RADEON_SURF_AP1_SWP_32BPP
	.comm	_CHIP_R300,8,3                  ; @CHIP_R300
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"writing surface %d %d %x %x\n"

	.comm	_RADEON_SURFACE0_INFO,8,3       ; @RADEON_SURFACE0_INFO
	.comm	_RADEON_SURFACE0_LOWER_BOUND,8,3 ; @RADEON_SURFACE0_LOWER_BOUND
	.comm	_RADEON_SURFACE0_UPPER_BOUND,8,3 ; @RADEON_SURFACE0_UPPER_BOUND
.subsections_via_symbols
