	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_acknowledge_irqs
_radeon_acknowledge_irqs:               ## @radeon_acknowledge_irqs
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r12
	movq	%rdi, %rbx
	movq	_RADEON_GEN_INT_STATUS@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RADEON_READ
	movq	_RADEON_SW_INT_TEST@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r13d
	movl	$0, (%r12)
	movq	_RADEON_FAMILY_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	(%rbx), %ecx
	movl	%eax, %r14d
	movq	_CHIP_RS600@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ecx
	jge	LBB0_1
## %bb.7:
	movq	_RADEON_CRTC_VBLANK_STAT@GOTPCREL(%rip), %rax
	movq	_RADEON_CRTC2_VBLANK_STAT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	jmp	LBB0_8
LBB0_1:
	movq	_R500_DISPLAY_INT_STATUS@GOTPCREL(%rip), %rbx
	testl	%r14d, (%rbx)
	je	LBB0_6
## %bb.2:
	movq	_R500_DISP_INTERRUPT_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RADEON_READ
	movl	%eax, %r15d
	movl	%eax, (%r12)
	movq	_R500_D1_VBLANK_INTERRUPT@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_4
## %bb.3:
	movq	_R500_D1MODE_VBLANK_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_R500_VBLANK_ACK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_RADEON_WRITE
LBB0_4:
	movq	_R500_D2_VBLANK_INTERRUPT@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	movq	_RADEON_GEN_INT_STATUS@GOTPCREL(%rip), %r15
	je	LBB0_6
## %bb.5:
	movq	_R500_D2MODE_VBLANK_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_R500_VBLANK_ACK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_RADEON_WRITE
LBB0_6:
	movl	(%rbx), %ebx
LBB0_8:
	orl	%r13d, %ebx
	andl	%r14d, %ebx
	je	LBB0_10
## %bb.9:
	movl	(%r15), %edi
	movl	%ebx, %esi
	callq	_RADEON_WRITE
LBB0_10:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_GEN_INT_STATUS,4,2      ## @RADEON_GEN_INT_STATUS
	.comm	_RADEON_SW_INT_TEST,4,2         ## @RADEON_SW_INT_TEST
	.comm	_RADEON_FAMILY_MASK,4,2         ## @RADEON_FAMILY_MASK
	.comm	_CHIP_RS600,4,2                 ## @CHIP_RS600
	.comm	_R500_DISPLAY_INT_STATUS,4,2    ## @R500_DISPLAY_INT_STATUS
	.comm	_R500_DISP_INTERRUPT_STATUS,4,2 ## @R500_DISP_INTERRUPT_STATUS
	.comm	_R500_D1_VBLANK_INTERRUPT,4,2   ## @R500_D1_VBLANK_INTERRUPT
	.comm	_R500_D1MODE_VBLANK_STATUS,4,2  ## @R500_D1MODE_VBLANK_STATUS
	.comm	_R500_VBLANK_ACK,4,2            ## @R500_VBLANK_ACK
	.comm	_R500_D2_VBLANK_INTERRUPT,4,2   ## @R500_D2_VBLANK_INTERRUPT
	.comm	_R500_D2MODE_VBLANK_STATUS,4,2  ## @R500_D2MODE_VBLANK_STATUS
	.comm	_RADEON_CRTC_VBLANK_STAT,4,2    ## @RADEON_CRTC_VBLANK_STAT
	.comm	_RADEON_CRTC2_VBLANK_STAT,4,2   ## @RADEON_CRTC2_VBLANK_STAT
	.no_dead_strip	_radeon_acknowledge_irqs
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_acknowledge_irqs
_radeon_acknowledge_irqs:               ; @radeon_acknowledge_irqs
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x1
	mov	x21, x0
Lloh0:
	adrp	x22, _RADEON_GEN_INT_STATUS@GOTPAGE
Lloh1:
	ldr	x22, [x22, _RADEON_GEN_INT_STATUS@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_RADEON_READ
	mov	x19, x0
Lloh2:
	adrp	x8, _RADEON_SW_INT_TEST@GOTPAGE
Lloh3:
	ldr	x8, [x8, _RADEON_SW_INT_TEST@GOTPAGEOFF]
Lloh4:
	ldr	w23, [x8]
	str	wzr, [x20]
	ldr	w8, [x21]
Lloh5:
	adrp	x9, _RADEON_FAMILY_MASK@GOTPAGE
Lloh6:
	ldr	x9, [x9, _RADEON_FAMILY_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	and	w8, w9, w8
Lloh8:
	adrp	x9, _CHIP_RS600@GOTPAGE
Lloh9:
	ldr	x9, [x9, _CHIP_RS600@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ge	LBB0_2
; %bb.1:
Lloh11:
	adrp	x8, _RADEON_CRTC_VBLANK_STAT@GOTPAGE
Lloh12:
	ldr	x8, [x8, _RADEON_CRTC_VBLANK_STAT@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
Lloh14:
	adrp	x9, _RADEON_CRTC2_VBLANK_STAT@GOTPAGE
Lloh15:
	ldr	x9, [x9, _RADEON_CRTC2_VBLANK_STAT@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
	orr	w8, w9, w8
	b	LBB0_8
LBB0_2:
Lloh17:
	adrp	x24, _R500_DISPLAY_INT_STATUS@GOTPAGE
Lloh18:
	ldr	x24, [x24, _R500_DISPLAY_INT_STATUS@GOTPAGEOFF]
	ldr	w8, [x24]
	tst	w8, w19
	b.eq	LBB0_7
; %bb.3:
Lloh19:
	adrp	x8, _R500_DISP_INTERRUPT_STATUS@GOTPAGE
Lloh20:
	ldr	x8, [x8, _R500_DISP_INTERRUPT_STATUS@GOTPAGEOFF]
Lloh21:
	ldr	w0, [x8]
	bl	_RADEON_READ
	mov	x21, x0
	str	w0, [x20]
Lloh22:
	adrp	x8, _R500_D1_VBLANK_INTERRUPT@GOTPAGE
Lloh23:
	ldr	x8, [x8, _R500_D1_VBLANK_INTERRUPT@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
Lloh25:
	adrp	x20, _R500_VBLANK_ACK@GOTPAGE
Lloh26:
	ldr	x20, [x20, _R500_VBLANK_ACK@GOTPAGEOFF]
	tst	w8, w0
	b.eq	LBB0_5
; %bb.4:
Lloh27:
	adrp	x8, _R500_D1MODE_VBLANK_STATUS@GOTPAGE
Lloh28:
	ldr	x8, [x8, _R500_D1MODE_VBLANK_STATUS@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	ldr	w1, [x20]
	bl	_RADEON_WRITE
LBB0_5:
Lloh30:
	adrp	x8, _R500_D2_VBLANK_INTERRUPT@GOTPAGE
Lloh31:
	ldr	x8, [x8, _R500_D2_VBLANK_INTERRUPT@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
	tst	w8, w21
	b.eq	LBB0_7
; %bb.6:
Lloh33:
	adrp	x8, _R500_D2MODE_VBLANK_STATUS@GOTPAGE
Lloh34:
	ldr	x8, [x8, _R500_D2MODE_VBLANK_STATUS@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	ldr	w1, [x20]
	bl	_RADEON_WRITE
LBB0_7:
	ldr	w8, [x24]
LBB0_8:
	orr	w8, w8, w23
	ands	w19, w8, w19
	b.eq	LBB0_10
; %bb.9:
	ldr	w0, [x22]
	mov	x1, x19
	bl	_RADEON_WRITE
LBB0_10:
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_GEN_INT_STATUS,4,2      ; @RADEON_GEN_INT_STATUS
	.comm	_RADEON_SW_INT_TEST,4,2         ; @RADEON_SW_INT_TEST
	.comm	_RADEON_FAMILY_MASK,4,2         ; @RADEON_FAMILY_MASK
	.comm	_CHIP_RS600,4,2                 ; @CHIP_RS600
	.comm	_R500_DISPLAY_INT_STATUS,4,2    ; @R500_DISPLAY_INT_STATUS
	.comm	_R500_DISP_INTERRUPT_STATUS,4,2 ; @R500_DISP_INTERRUPT_STATUS
	.comm	_R500_D1_VBLANK_INTERRUPT,4,2   ; @R500_D1_VBLANK_INTERRUPT
	.comm	_R500_D1MODE_VBLANK_STATUS,4,2  ; @R500_D1MODE_VBLANK_STATUS
	.comm	_R500_VBLANK_ACK,4,2            ; @R500_VBLANK_ACK
	.comm	_R500_D2_VBLANK_INTERRUPT,4,2   ; @R500_D2_VBLANK_INTERRUPT
	.comm	_R500_D2MODE_VBLANK_STATUS,4,2  ; @R500_D2MODE_VBLANK_STATUS
	.comm	_RADEON_CRTC_VBLANK_STAT,4,2    ; @RADEON_CRTC_VBLANK_STAT
	.comm	_RADEON_CRTC2_VBLANK_STAT,4,2   ; @RADEON_CRTC2_VBLANK_STAT
	.no_dead_strip	_radeon_acknowledge_irqs
.subsections_via_symbols
