	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r100_irq_set                   ## -- Begin function r100_irq_set
	.p2align	4, 0x90
_r100_irq_set:                          ## @r100_irq_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	cmpl	$0, 32(%rdi)
	je	LBB0_1
## %bb.2:
	movq	%rdi, %rbx
	movq	_RADEON_RING_TYPE_GFX_INDEX@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	shlq	$2, %rdi
	addq	24(%rbx), %rdi
	callq	_atomic_read
	xorl	%r14d, %r14d
	testq	%rax, %rax
	je	LBB0_4
## %bb.3:
	movq	_RADEON_SW_INT_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
LBB0_4:
	movq	16(%rbx), %rax
	cmpq	$0, (%rax)
	jne	LBB0_6
## %bb.5:
	movq	8(%rbx), %rdi
	callq	_atomic_read
	testq	%rax, %rax
	je	LBB0_7
LBB0_6:
	movq	_RADEON_CRTC_VBLANK_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
LBB0_7:
	movq	16(%rbx), %rax
	cmpq	$0, 8(%rax)
	jne	LBB0_9
## %bb.8:
	movq	8(%rbx), %rdi
	addq	$4, %rdi
	callq	_atomic_read
	testq	%rax, %rax
	je	LBB0_10
LBB0_9:
	movq	_RADEON_CRTC2_VBLANK_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
LBB0_10:
	movq	(%rbx), %rax
	xorl	%ebx, %ebx
	cmpq	$0, (%rax)
	movl	$0, %esi
	je	LBB0_12
## %bb.11:
	movq	_RADEON_FP_DETECT_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
LBB0_12:
	cmpq	$0, 8(%rax)
	movl	$0, %eax
	je	LBB0_14
## %bb.13:
	movq	_RADEON_FP2_DETECT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_14:
	orl	%eax, %r14d
	orl	%r14d, %esi
	movq	_RADEON_GEN_INT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32
	jmp	LBB0_15
LBB0_1:
	leaq	L_.str(%rip), %rsi
	movl	$1, %edi
	callq	_WARN
	movq	_R_000040_GEN_INT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%ebx, %ebx
	xorl	%esi, %esi
	callq	_WREG32
	movq	_EINVAL@GOTPCREL(%rip), %rax
	subl	(%rax), %ebx
LBB0_15:
	movl	%ebx, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Can't enable IRQ/MSI because no handler is installed\n"

	.comm	_R_000040_GEN_INT_CNTL,4,2      ## @R_000040_GEN_INT_CNTL
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_RADEON_RING_TYPE_GFX_INDEX,8,3 ## @RADEON_RING_TYPE_GFX_INDEX
	.comm	_RADEON_SW_INT_ENABLE,4,2       ## @RADEON_SW_INT_ENABLE
	.comm	_RADEON_CRTC_VBLANK_MASK,4,2    ## @RADEON_CRTC_VBLANK_MASK
	.comm	_RADEON_CRTC2_VBLANK_MASK,4,2   ## @RADEON_CRTC2_VBLANK_MASK
	.comm	_RADEON_FP_DETECT_MASK,4,2      ## @RADEON_FP_DETECT_MASK
	.comm	_RADEON_FP2_DETECT_MASK,4,2     ## @RADEON_FP2_DETECT_MASK
	.comm	_RADEON_GEN_INT_CNTL,4,2        ## @RADEON_GEN_INT_CNTL
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r100_irq_set                   ; -- Begin function r100_irq_set
	.p2align	2
_r100_irq_set:                          ; @r100_irq_set
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	w8, [x0, #32]
	cbz	w8, LBB0_8
; %bb.1:
	mov	x19, x0
	ldr	x8, [x0, #24]
Lloh0:
	adrp	x9, _RADEON_RING_TYPE_GFX_INDEX@GOTPAGE
Lloh1:
	ldr	x9, [x9, _RADEON_RING_TYPE_GFX_INDEX@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	add	x0, x8, x9, lsl #2
	bl	_atomic_read
Lloh3:
	adrp	x8, _RADEON_SW_INT_ENABLE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _RADEON_SW_INT_ENABLE@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	cmp	x0, #0
	csel	w20, wzr, w8, eq
	ldr	x8, [x19, #16]
	ldr	x8, [x8]
	cbnz	x8, LBB0_3
; %bb.2:
	ldr	x0, [x19, #8]
	bl	_atomic_read
	cbz	x0, LBB0_4
LBB0_3:
Lloh6:
	adrp	x8, _RADEON_CRTC_VBLANK_MASK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_CRTC_VBLANK_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	orr	w20, w8, w20
LBB0_4:
	ldr	x8, [x19, #16]
	ldr	x8, [x8, #8]
	cbnz	x8, LBB0_6
; %bb.5:
	ldr	x8, [x19, #8]
	add	x0, x8, #4
	bl	_atomic_read
	cbz	x0, LBB0_7
LBB0_6:
Lloh9:
	adrp	x8, _RADEON_CRTC2_VBLANK_MASK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _RADEON_CRTC2_VBLANK_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	orr	w20, w8, w20
LBB0_7:
	ldr	x8, [x19]
Lloh12:
	adrp	x9, _RADEON_FP_DETECT_MASK@GOTPAGE
Lloh13:
	ldr	x9, [x9, _RADEON_FP_DETECT_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	ldp	x10, x8, [x8]
	cmp	x10, #0
	csel	w9, wzr, w9, eq
	orr	w9, w9, w20
Lloh15:
	adrp	x10, _RADEON_FP2_DETECT_MASK@GOTPAGE
Lloh16:
	ldr	x10, [x10, _RADEON_FP2_DETECT_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w10, [x10]
	cmp	x8, #0
	csel	w8, wzr, w10, eq
	orr	w1, w9, w8
Lloh18:
	adrp	x8, _RADEON_GEN_INT_CNTL@GOTPAGE
Lloh19:
	ldr	x8, [x8, _RADEON_GEN_INT_CNTL@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
	bl	_WREG32
	mov	w0, #0
	b	LBB0_9
LBB0_8:
Lloh21:
	adrp	x1, l_.str@PAGE
Lloh22:
	add	x1, x1, l_.str@PAGEOFF
	mov	w0, #1
	bl	_WARN
Lloh23:
	adrp	x8, _R_000040_GEN_INT_CNTL@GOTPAGE
Lloh24:
	ldr	x8, [x8, _R_000040_GEN_INT_CNTL@GOTPAGEOFF]
Lloh25:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh26:
	adrp	x8, _EINVAL@GOTPAGE
Lloh27:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_9:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpAdd	Lloh21, Lloh22
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Can't enable IRQ/MSI because no handler is installed\n"

	.comm	_R_000040_GEN_INT_CNTL,4,2      ; @R_000040_GEN_INT_CNTL
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_RADEON_RING_TYPE_GFX_INDEX,8,3 ; @RADEON_RING_TYPE_GFX_INDEX
	.comm	_RADEON_SW_INT_ENABLE,4,2       ; @RADEON_SW_INT_ENABLE
	.comm	_RADEON_CRTC_VBLANK_MASK,4,2    ; @RADEON_CRTC_VBLANK_MASK
	.comm	_RADEON_CRTC2_VBLANK_MASK,4,2   ; @RADEON_CRTC2_VBLANK_MASK
	.comm	_RADEON_FP_DETECT_MASK,4,2      ; @RADEON_FP_DETECT_MASK
	.comm	_RADEON_FP2_DETECT_MASK,4,2     ; @RADEON_FP2_DETECT_MASK
	.comm	_RADEON_GEN_INT_CNTL,4,2        ; @RADEON_GEN_INT_CNTL
.subsections_via_symbols
