	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_md_show_usage                  ## -- Begin function md_show_usage
	.p2align	4, 0x90
_md_show_usage:                         ## @md_show_usage
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	leaq	L_.str(%rip), %rdi
	callq	__
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_fprintf
	leaq	L_.str.1(%rip), %rdi
	callq	__
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_fprintf
	leaq	L_.str.2(%rip), %rdi
	callq	__
	movq	%rbx, %rdi
	movq	%rax, %rsi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_fprintf                        ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"PowerPC options:\n-a32\t\t\tgenerate ELF32/XCOFF32\n-a64\t\t\tgenerate ELF64/XCOFF64\n-u\t\t\tignored\n-mpwrx, -mpwr2\t\tgenerate code for POWER/2 (RIOS2)\n-mpwr\t\t\tgenerate code for POWER (RIOS1)\n-m601\t\t\tgenerate code for PowerPC 601\n-mppc, -mppc32, -m603, -m604\n\t\t\tgenerate code for PowerPC 603/604\n-m403, -m405\t\tgenerate code for PowerPC 403/405\n-m440\t\t\tgenerate code for PowerPC 440\n-m7400, -m7410, -m7450, -m7455\n\t\t\tgenerate code For PowerPC 7400/7410/7450/7455\n"

L_.str.1:                               ## @.str.1
	.asciz	"-mppc64, -m620\t\tgenerate code for PowerPC 620/625/630\n-mppc64bridge\t\tgenerate code for PowerPC 64, including bridge insns\n-mbooke64\t\tgenerate code for 64-bit PowerPC BookE\n-mbooke, mbooke32\tgenerate code for 32-bit PowerPC BookE\n-mpower4\t\tgenerate code for Power4 architecture\n-mpower5\t\tgenerate code for Power5 architecture\n-mpower6\t\tgenerate code for Power6 architecture\n-mcell\t\t\tgenerate code for Cell Broadband Engine architecture\n-mcom\t\t\tgenerate code Power/PowerPC common instructions\n-many\t\t\tgenerate code for any architecture (PWR/PWRX/PPC)\n"

L_.str.2:                               ## @.str.2
	.asciz	"-maltivec\t\tgenerate code for AltiVec\n-me300\t\t\tgenerate code for PowerPC e300 family\n-me500, -me500x2\tgenerate code for Motorola e500 core complex\n-mspe\t\t\tgenerate code for Motorola SPE instructions\n-mregnames\t\tAllow symbolic names for registers\n-mno-regnames\t\tDo not allow symbolic names for registers\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_md_show_usage                  ; -- Begin function md_show_usage
	.p2align	2
_md_show_usage:                         ; @md_show_usage
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	__
	mov	x1, x0
	mov	x0, x19
	bl	_fprintf
Lloh2:
	adrp	x0, l_.str.1@PAGE
Lloh3:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	__
	mov	x1, x0
	mov	x0, x19
	bl	_fprintf
Lloh4:
	adrp	x0, l_.str.2@PAGE
Lloh5:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	__
	mov	x1, x0
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_fprintf
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpAdd	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"PowerPC options:\n-a32\t\t\tgenerate ELF32/XCOFF32\n-a64\t\t\tgenerate ELF64/XCOFF64\n-u\t\t\tignored\n-mpwrx, -mpwr2\t\tgenerate code for POWER/2 (RIOS2)\n-mpwr\t\t\tgenerate code for POWER (RIOS1)\n-m601\t\t\tgenerate code for PowerPC 601\n-mppc, -mppc32, -m603, -m604\n\t\t\tgenerate code for PowerPC 603/604\n-m403, -m405\t\tgenerate code for PowerPC 403/405\n-m440\t\t\tgenerate code for PowerPC 440\n-m7400, -m7410, -m7450, -m7455\n\t\t\tgenerate code For PowerPC 7400/7410/7450/7455\n"

l_.str.1:                               ; @.str.1
	.asciz	"-mppc64, -m620\t\tgenerate code for PowerPC 620/625/630\n-mppc64bridge\t\tgenerate code for PowerPC 64, including bridge insns\n-mbooke64\t\tgenerate code for 64-bit PowerPC BookE\n-mbooke, mbooke32\tgenerate code for 32-bit PowerPC BookE\n-mpower4\t\tgenerate code for Power4 architecture\n-mpower5\t\tgenerate code for Power5 architecture\n-mpower6\t\tgenerate code for Power6 architecture\n-mcell\t\t\tgenerate code for Cell Broadband Engine architecture\n-mcom\t\t\tgenerate code Power/PowerPC common instructions\n-many\t\t\tgenerate code for any architecture (PWR/PWRX/PPC)\n"

l_.str.2:                               ; @.str.2
	.asciz	"-maltivec\t\tgenerate code for AltiVec\n-me300\t\t\tgenerate code for PowerPC e300 family\n-me500, -me500x2\tgenerate code for Motorola e500 core complex\n-mspe\t\t\tgenerate code for Motorola SPE instructions\n-mregnames\t\tAllow symbolic names for registers\n-mno-regnames\t\tDo not allow symbolic names for registers\n"

.subsections_via_symbols
