	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function wm8900_set_fll
_wm8900_set_fll:                        ## @wm8900_set_fll
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %r14d
	movl	%edx, %ebx
	movq	%rdi, %r15
	movq	(%rdi), %r13
	cmpl	%edx, (%r13)
	jne	LBB0_2
## %bb.1:
	cmpl	%r14d, 4(%r13)
	je	LBB0_13
LBB0_2:
	movq	_WM8900_REG_POWER1@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_snd_soc_read
	movl	(%r12), %esi
	movq	_WM8900_REG_POWER1_FLL_ENA@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	%r15, %rdi
	callq	_snd_soc_write
	testl	%ebx, %ebx
	je	LBB0_4
## %bb.3:
	testl	%r14d, %r14d
	je	LBB0_4
## %bb.5:
	leaq	-64(%rbp), %rdi
	movl	%ebx, %esi
	movl	%r14d, %edx
	callq	_fll_factors
	testq	%rax, %rax
	jne	LBB0_12
## %bb.6:
	movl	%ebx, (%r13)
	movl	%r14d, 4(%r13)
	movq	_WM8900_REG_FLLCTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_WM8900_REG_FLLCTL1_OSC_ENA@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	orl	-64(%rbp), %edx
	movq	%r15, %rdi
	callq	_snd_soc_write
	movq	_WM8900_REG_FLLCTL4@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-60(%rbp), %edx
	sarl	$5, %edx
	movq	%r15, %rdi
	callq	_snd_soc_write
	movq	_WM8900_REG_FLLCTL5@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-60(%rbp), %edx
	movl	-56(%rbp), %eax
	shll	$6, %eax
	andl	$31, %edx
	orl	%eax, %edx
	movq	%r15, %rdi
	callq	_snd_soc_write
	movl	-52(%rbp), %edx
	movq	_WM8900_REG_FLLCTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	testl	%edx, %edx
	je	LBB0_8
## %bb.7:
	sarl	$8, %edx
	orl	$256, %edx                      ## imm = 0x100
	movq	%r15, %rdi
	callq	_snd_soc_write
	movq	_WM8900_REG_FLLCTL3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movzbl	-52(%rbp), %edx
	movq	%r15, %rdi
	jmp	LBB0_9
LBB0_4:
	movq	_WM8900_REG_CLOCKING1@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_snd_soc_read
	movl	(%r12), %esi
	movq	_WM8900_REG_CLOCKING1_MCLK_SRC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	%r15, %rdi
	callq	_snd_soc_write
	movq	_WM8900_REG_FLLCTL1@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_snd_soc_read
	movl	(%r12), %esi
	movq	_WM8900_REG_FLLCTL1_OSC_ENA@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	%r15, %rdi
	callq	_snd_soc_write
	movl	%ebx, (%r13)
	movl	%r14d, 4(%r13)
	jmp	LBB0_13
LBB0_8:
	movq	%r15, %rdi
	xorl	%edx, %edx
LBB0_9:
	callq	_snd_soc_write
	xorl	%edx, %edx
	cmpq	$0, -48(%rbp)
	movq	_WM8900_REG_FLLCTL6@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	je	LBB0_11
## %bb.10:
	movq	_WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
LBB0_11:
	movq	%r15, %rdi
	callq	_snd_soc_write
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_snd_soc_read
	movl	(%r12), %esi
	movq	_WM8900_REG_POWER1_FLL_ENA@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	%r15, %rdi
	movl	%eax, %edx
	callq	_snd_soc_write
LBB0_12:
	movq	_WM8900_REG_CLOCKING1@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_snd_soc_read
	movl	(%rbx), %esi
	movq	_WM8900_REG_CLOCKING1_MCLK_SRC@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	%r15, %rdi
	movl	%eax, %edx
	callq	_snd_soc_write
LBB0_13:
	xorl	%eax, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_WM8900_REG_POWER1,4,2          ## @WM8900_REG_POWER1
	.comm	_WM8900_REG_POWER1_FLL_ENA,4,2  ## @WM8900_REG_POWER1_FLL_ENA
	.comm	_WM8900_REG_CLOCKING1,4,2       ## @WM8900_REG_CLOCKING1
	.comm	_WM8900_REG_CLOCKING1_MCLK_SRC,4,2 ## @WM8900_REG_CLOCKING1_MCLK_SRC
	.comm	_WM8900_REG_FLLCTL1,4,2         ## @WM8900_REG_FLLCTL1
	.comm	_WM8900_REG_FLLCTL1_OSC_ENA,4,2 ## @WM8900_REG_FLLCTL1_OSC_ENA
	.comm	_WM8900_REG_FLLCTL4,4,2         ## @WM8900_REG_FLLCTL4
	.comm	_WM8900_REG_FLLCTL5,4,2         ## @WM8900_REG_FLLCTL5
	.comm	_WM8900_REG_FLLCTL2,4,2         ## @WM8900_REG_FLLCTL2
	.comm	_WM8900_REG_FLLCTL3,4,2         ## @WM8900_REG_FLLCTL3
	.comm	_WM8900_REG_FLLCTL6,4,2         ## @WM8900_REG_FLLCTL6
	.comm	_WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF,4,2 ## @WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF
	.no_dead_strip	_wm8900_set_fll
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function wm8900_set_fll
_wm8900_set_fll:                        ; @wm8900_set_fll
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x3
	mov	x21, x2
	mov	x19, x0
	ldr	x24, [x0]
	ldr	w8, [x24]
	cmp	w8, w2
	b.ne	LBB0_2
; %bb.1:
	ldr	w8, [x24, #4]
	cmp	w8, w20
	b.eq	LBB0_11
LBB0_2:
Lloh0:
	adrp	x22, _WM8900_REG_POWER1@GOTPAGE
Lloh1:
	ldr	x22, [x22, _WM8900_REG_POWER1@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x19
	bl	_snd_soc_read
	ldr	w1, [x22]
Lloh2:
	adrp	x23, _WM8900_REG_POWER1_FLL_ENA@GOTPAGE
Lloh3:
	ldr	x23, [x23, _WM8900_REG_POWER1_FLL_ENA@GOTPAGEOFF]
	ldr	w8, [x23]
	bic	w2, w0, w8
	mov	x0, x19
	bl	_snd_soc_write
	cbz	w21, LBB0_7
; %bb.3:
	cbz	w20, LBB0_7
; %bb.4:
	add	x0, sp, #8
	mov	x1, x21
	mov	x2, x20
	bl	_fll_factors
	cbnz	x0, LBB0_10
; %bb.5:
	stp	w21, w20, [x24]
Lloh4:
	adrp	x8, _WM8900_REG_FLLCTL1@GOTPAGE
Lloh5:
	ldr	x8, [x8, _WM8900_REG_FLLCTL1@GOTPAGEOFF]
Lloh6:
	ldr	w1, [x8]
	ldr	w8, [sp, #8]
Lloh7:
	adrp	x9, _WM8900_REG_FLLCTL1_OSC_ENA@GOTPAGE
Lloh8:
	ldr	x9, [x9, _WM8900_REG_FLLCTL1_OSC_ENA@GOTPAGEOFF]
Lloh9:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_snd_soc_write
Lloh10:
	adrp	x8, _WM8900_REG_FLLCTL4@GOTPAGE
Lloh11:
	ldr	x8, [x8, _WM8900_REG_FLLCTL4@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
	ldr	w8, [sp, #12]
	asr	w2, w8, #5
	mov	x0, x19
	bl	_snd_soc_write
Lloh13:
	adrp	x8, _WM8900_REG_FLLCTL5@GOTPAGE
Lloh14:
	ldr	x8, [x8, _WM8900_REG_FLLCTL5@GOTPAGEOFF]
Lloh15:
	ldr	w1, [x8]
	ldp	w9, w8, [sp, #12]
	and	w2, w9, #0x1f
	bfi	w2, w8, #6, #26
	mov	x0, x19
	bl	_snd_soc_write
	ldr	w8, [sp, #20]
Lloh16:
	adrp	x9, _WM8900_REG_FLLCTL2@GOTPAGE
Lloh17:
	ldr	x9, [x9, _WM8900_REG_FLLCTL2@GOTPAGEOFF]
Lloh18:
	ldr	w1, [x9]
	cbz	w8, LBB0_8
; %bb.6:
	asr	w8, w8, #8
	orr	w2, w8, #0x100
	mov	x0, x19
	bl	_snd_soc_write
Lloh19:
	adrp	x8, _WM8900_REG_FLLCTL3@GOTPAGE
Lloh20:
	ldr	x8, [x8, _WM8900_REG_FLLCTL3@GOTPAGEOFF]
Lloh21:
	ldr	w1, [x8]
	ldrb	w2, [sp, #20]
	mov	x0, x19
	b	LBB0_9
LBB0_7:
Lloh22:
	adrp	x22, _WM8900_REG_CLOCKING1@GOTPAGE
Lloh23:
	ldr	x22, [x22, _WM8900_REG_CLOCKING1@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x19
	bl	_snd_soc_read
	ldr	w1, [x22]
Lloh24:
	adrp	x8, _WM8900_REG_CLOCKING1_MCLK_SRC@GOTPAGE
Lloh25:
	ldr	x8, [x8, _WM8900_REG_CLOCKING1_MCLK_SRC@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	bic	w2, w0, w8
	mov	x0, x19
	bl	_snd_soc_write
Lloh27:
	adrp	x22, _WM8900_REG_FLLCTL1@GOTPAGE
Lloh28:
	ldr	x22, [x22, _WM8900_REG_FLLCTL1@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x19
	bl	_snd_soc_read
	ldr	w1, [x22]
Lloh29:
	adrp	x8, _WM8900_REG_FLLCTL1_OSC_ENA@GOTPAGE
Lloh30:
	ldr	x8, [x8, _WM8900_REG_FLLCTL1_OSC_ENA@GOTPAGEOFF]
Lloh31:
	ldr	w8, [x8]
	bic	w2, w0, w8
	mov	x0, x19
	bl	_snd_soc_write
	stp	w21, w20, [x24]
	b	LBB0_11
LBB0_8:
	mov	x0, x19
	mov	w2, #0
LBB0_9:
	bl	_snd_soc_write
	ldr	x8, [sp, #24]
Lloh32:
	adrp	x9, _WM8900_REG_FLLCTL6@GOTPAGE
Lloh33:
	ldr	x9, [x9, _WM8900_REG_FLLCTL6@GOTPAGEOFF]
Lloh34:
	ldr	w1, [x9]
Lloh35:
	adrp	x9, _WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF@GOTPAGE
Lloh36:
	ldr	x9, [x9, _WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF@GOTPAGEOFF]
Lloh37:
	ldr	w9, [x9]
	cmp	x8, #0
	csel	w2, wzr, w9, eq
	mov	x0, x19
	bl	_snd_soc_write
	ldr	w1, [x22]
	mov	x0, x19
	bl	_snd_soc_read
	ldr	w1, [x22]
	ldr	w8, [x23]
	orr	w2, w8, w0
	mov	x0, x19
	bl	_snd_soc_write
LBB0_10:
Lloh38:
	adrp	x20, _WM8900_REG_CLOCKING1@GOTPAGE
Lloh39:
	ldr	x20, [x20, _WM8900_REG_CLOCKING1@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_snd_soc_read
	ldr	w1, [x20]
Lloh40:
	adrp	x8, _WM8900_REG_CLOCKING1_MCLK_SRC@GOTPAGE
Lloh41:
	ldr	x8, [x8, _WM8900_REG_CLOCKING1_MCLK_SRC@GOTPAGEOFF]
Lloh42:
	ldr	w8, [x8]
	orr	w2, w8, w0
	mov	x0, x19
	bl	_snd_soc_write
LBB0_11:
	mov	w0, #0
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh38, Lloh39
	.cfi_endproc
                                        ; -- End function
	.comm	_WM8900_REG_POWER1,4,2          ; @WM8900_REG_POWER1
	.comm	_WM8900_REG_POWER1_FLL_ENA,4,2  ; @WM8900_REG_POWER1_FLL_ENA
	.comm	_WM8900_REG_CLOCKING1,4,2       ; @WM8900_REG_CLOCKING1
	.comm	_WM8900_REG_CLOCKING1_MCLK_SRC,4,2 ; @WM8900_REG_CLOCKING1_MCLK_SRC
	.comm	_WM8900_REG_FLLCTL1,4,2         ; @WM8900_REG_FLLCTL1
	.comm	_WM8900_REG_FLLCTL1_OSC_ENA,4,2 ; @WM8900_REG_FLLCTL1_OSC_ENA
	.comm	_WM8900_REG_FLLCTL4,4,2         ; @WM8900_REG_FLLCTL4
	.comm	_WM8900_REG_FLLCTL5,4,2         ; @WM8900_REG_FLLCTL5
	.comm	_WM8900_REG_FLLCTL2,4,2         ; @WM8900_REG_FLLCTL2
	.comm	_WM8900_REG_FLLCTL3,4,2         ; @WM8900_REG_FLLCTL3
	.comm	_WM8900_REG_FLLCTL6,4,2         ; @WM8900_REG_FLLCTL6
	.comm	_WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF,4,2 ; @WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF
	.no_dead_strip	_wm8900_set_fll
.subsections_via_symbols
