	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function opcode_select
_opcode_select:                         ## @opcode_select
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	cmpl	$32, %edi
	je	LBB0_8
## %bb.1:
	movl	%edi, %ebx
	cmpl	$16, %edi
	jne	LBB0_15
## %bb.2:
	movq	_thumb_mode@GOTPCREL(%rip), %rbx
	cmpl	$0, (%rbx)
	jne	LBB0_6
## %bb.3:
	movq	_cpu_variant@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_arm_ext_v4t@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_ARM_CPU_HAS_FEATURE
	testl	%eax, %eax
	jne	LBB0_5
## %bb.4:
	leaq	L_.str(%rip), %rdi
	callq	__
	movl	%eax, %edi
	xorl	%eax, %eax
	callq	_as_bad
LBB0_5:
	movl	$1, (%rbx)
	movq	_now_seg@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_record_alignment
LBB0_6:
	movq	_MAP_THUMB@GOTPCREL(%rip), %rax
	jmp	LBB0_7
LBB0_8:
	movq	_thumb_mode@GOTPCREL(%rip), %rbx
	cmpl	$0, (%rbx)
	je	LBB0_14
## %bb.9:
	movq	_cpu_variant@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_arm_ext_v1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_ARM_CPU_HAS_FEATURE
	testl	%eax, %eax
	jne	LBB0_11
## %bb.10:
	leaq	L_.str.1(%rip), %rdi
	callq	__
	movl	%eax, %edi
	xorl	%eax, %eax
	callq	_as_bad
LBB0_11:
	movl	$0, (%rbx)
	movq	_need_pass_2@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	jne	LBB0_13
## %bb.12:
	movl	$2, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_frag_align
LBB0_13:
	movq	_now_seg@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_record_alignment
LBB0_14:
	movq	_MAP_ARM@GOTPCREL(%rip), %rax
LBB0_7:
	movl	(%rax), %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_mapping_state                  ## TAILCALL
LBB0_15:
	leaq	L_.str.2(%rip), %rdi
	callq	__
	movl	%eax, %edi
	movl	%ebx, %esi
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_as_bad                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_thumb_mode,4,2                 ## @thumb_mode
	.comm	_cpu_variant,4,2                ## @cpu_variant
	.comm	_arm_ext_v4t,4,2                ## @arm_ext_v4t
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"selected processor does not support THUMB opcodes"

	.comm	_now_seg,4,2                    ## @now_seg
	.comm	_MAP_THUMB,4,2                  ## @MAP_THUMB
	.comm	_arm_ext_v1,4,2                 ## @arm_ext_v1
L_.str.1:                               ## @.str.1
	.asciz	"selected processor does not support ARM opcodes"

	.comm	_need_pass_2,4,2                ## @need_pass_2
	.comm	_MAP_ARM,4,2                    ## @MAP_ARM
L_.str.2:                               ## @.str.2
	.asciz	"invalid instruction size selected (%d)"

	.no_dead_strip	_opcode_select
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function opcode_select
_opcode_select:                         ; @opcode_select
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #48
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	cmp	w0, #32
	b.eq	LBB0_7
; %bb.1:
	mov	x19, x0
	cmp	w0, #16
	b.ne	LBB0_15
; %bb.2:
Lloh0:
	adrp	x19, _thumb_mode@GOTPAGE
Lloh1:
	ldr	x19, [x19, _thumb_mode@GOTPAGEOFF]
	ldr	w8, [x19]
	cbnz	w8, LBB0_6
; %bb.3:
Lloh2:
	adrp	x8, _cpu_variant@GOTPAGE
Lloh3:
	ldr	x8, [x8, _cpu_variant@GOTPAGEOFF]
Lloh4:
	ldr	w0, [x8]
Lloh5:
	adrp	x8, _arm_ext_v4t@GOTPAGE
Lloh6:
	ldr	x8, [x8, _arm_ext_v4t@GOTPAGEOFF]
Lloh7:
	ldr	w1, [x8]
	bl	_ARM_CPU_HAS_FEATURE
	cbnz	w0, LBB0_5
; %bb.4:
Lloh8:
	adrp	x0, l_.str@PAGE
Lloh9:
	add	x0, x0, l_.str@PAGEOFF
	bl	__
	bl	_as_bad
LBB0_5:
	mov	w8, #1
	str	w8, [x19]
Lloh10:
	adrp	x8, _now_seg@GOTPAGE
Lloh11:
	ldr	x8, [x8, _now_seg@GOTPAGEOFF]
Lloh12:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_record_alignment
LBB0_6:
Lloh13:
	adrp	x8, _MAP_THUMB@GOTPAGE
Lloh14:
	ldr	x8, [x8, _MAP_THUMB@GOTPAGEOFF]
	b	LBB0_14
LBB0_7:
Lloh15:
	adrp	x19, _thumb_mode@GOTPAGE
Lloh16:
	ldr	x19, [x19, _thumb_mode@GOTPAGEOFF]
	ldr	w8, [x19]
	cbz	w8, LBB0_13
; %bb.8:
Lloh17:
	adrp	x8, _cpu_variant@GOTPAGE
Lloh18:
	ldr	x8, [x8, _cpu_variant@GOTPAGEOFF]
Lloh19:
	ldr	w0, [x8]
Lloh20:
	adrp	x8, _arm_ext_v1@GOTPAGE
Lloh21:
	ldr	x8, [x8, _arm_ext_v1@GOTPAGEOFF]
Lloh22:
	ldr	w1, [x8]
	bl	_ARM_CPU_HAS_FEATURE
	cbnz	w0, LBB0_10
; %bb.9:
Lloh23:
	adrp	x0, l_.str.1@PAGE
Lloh24:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	__
	bl	_as_bad
LBB0_10:
	str	wzr, [x19]
Lloh25:
	adrp	x8, _need_pass_2@GOTPAGE
Lloh26:
	ldr	x8, [x8, _need_pass_2@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
	cbnz	w8, LBB0_12
; %bb.11:
	mov	w0, #2
	mov	w1, #0
	mov	w2, #0
	bl	_frag_align
LBB0_12:
Lloh28:
	adrp	x8, _now_seg@GOTPAGE
Lloh29:
	ldr	x8, [x8, _now_seg@GOTPAGEOFF]
Lloh30:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_record_alignment
LBB0_13:
Lloh31:
	adrp	x8, _MAP_ARM@GOTPAGE
Lloh32:
	ldr	x8, [x8, _MAP_ARM@GOTPAGEOFF]
LBB0_14:
	ldr	w0, [x8]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	b	_mapping_state
LBB0_15:
Lloh33:
	adrp	x0, l_.str.2@PAGE
Lloh34:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	__
	str	x19, [sp]
	bl	_as_bad
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpAdd	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpAdd	Lloh33, Lloh34
	.cfi_endproc
                                        ; -- End function
	.comm	_thumb_mode,4,2                 ; @thumb_mode
	.comm	_cpu_variant,4,2                ; @cpu_variant
	.comm	_arm_ext_v4t,4,2                ; @arm_ext_v4t
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"selected processor does not support THUMB opcodes"

	.comm	_now_seg,4,2                    ; @now_seg
	.comm	_MAP_THUMB,4,2                  ; @MAP_THUMB
	.comm	_arm_ext_v1,4,2                 ; @arm_ext_v1
l_.str.1:                               ; @.str.1
	.asciz	"selected processor does not support ARM opcodes"

	.comm	_need_pass_2,4,2                ; @need_pass_2
	.comm	_MAP_ARM,4,2                    ; @MAP_ARM
l_.str.2:                               ; @.str.2
	.asciz	"invalid instruction size selected (%d)"

	.no_dead_strip	_opcode_select
.subsections_via_symbols
