	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mep_check_parallel32_scheduling
_mep_check_parallel32_scheduling:       ## @mep_check_parallel32_scheduling
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	subq	$32, %rsp
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_num_insns_saved@GOTPCREL(%rip), %r15
	movl	(%r15), %eax
	cmpl	$3, %eax
	jl	LBB0_2
## %bb.1:
	leaq	L_.str(%rip), %rdi
	callq	_as_fatal
	movl	(%r15), %eax
LBB0_2:
	testl	%eax, %eax
	je	LBB0_25
## %bb.3:
	movq	_saved_insns@GOTPCREL(%rip), %r12
	movq	(%r12), %rax
	movq	(%rax), %rdi
	callq	_MEP_INSN_COP_P
	movl	%eax, %r14d
	movq	(%r12), %rdi
	addq	$12, %rdi
	callq	_CGEN_FIELDS_BITSIZE
	movl	%eax, %ebx
	cmpl	$2, (%r15)
	jne	LBB0_12
## %bb.4:
	movq	(%r12), %rax
	movq	16(%rax), %rdi
	callq	_MEP_INSN_COP_P
	movl	%eax, %r15d
	movq	(%r12), %rdi
	addq	$28, %rdi
	callq	_CGEN_FIELDS_BITSIZE
	testl	%r14d, %r14d
	je	LBB0_6
## %bb.5:
	testl	%r15d, %r15d
	je	LBB0_8
LBB0_6:
	testl	%r15d, %r15d
	je	LBB0_11
## %bb.7:
	testl	%r14d, %r14d
	jne	LBB0_11
LBB0_8:
	addl	%ebx, %eax
	cmpl	$32, %eax
	je	LBB0_25
## %bb.9:
	leaq	L_.str.1(%rip), %rdi
	jmp	LBB0_10
LBB0_12:
	cmpl	$33, %ebx
	jl	LBB0_14
## %bb.13:
	leaq	L_.str.3(%rip), %rdi
	callq	_as_fatal
	jmp	LBB0_15
LBB0_14:
	cmpl	$32, %ebx
	je	LBB0_25
LBB0_15:
	movq	(%r12), %rax
	movq	(%rax), %rdi
	movq	_CGEN_INSN_VLIW32_NO_MATCHING_NOP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_CGEN_INSN_ATTR_VALUE
	testq	%rax, %rax
	je	LBB0_17
## %bb.16:
	leaq	L_.str.4(%rip), %rdi
	callq	_as_fatal
LBB0_17:
	testl	%r14d, %r14d
	je	LBB0_20
## %bb.18:
	movq	_gas_cgen_cpu_desc@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	leaq	-44(%rbp), %rdx
	leaq	L_.str.5(%rip), %rsi
	leaq	-40(%rbp), %r8
	callq	_mep_cgen_assemble_insn
	movq	%rax, -56(%rbp)
	testq	%rax, %rax
	je	LBB0_24
## %bb.19:
	movq	(%r12), %rax
	movups	(%rax), %xmm0
	movups	%xmm0, 16(%rax)
	movups	-56(%rbp), %xmm0
	movups	%xmm0, (%rax)
	incl	(%r15)
	xorl	%edi, %edi
	callq	_gas_cgen_swap_fixups
	movl	$1, %edi
	callq	_gas_cgen_save_fixups
	jmp	LBB0_25
LBB0_20:
	movq	(%r12), %rax
	movq	(%rax), %rax
	movq	(%rax), %rax
	movl	(%rax), %eax
	movq	_MEP_INSN_BSR12@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_25
## %bb.21:
	movq	_MEP_INSN_BEQZ@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_25
## %bb.22:
	movq	_MEP_INSN_BNEZ@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_25
## %bb.23:
	movq	_gas_cgen_cpu_desc@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	leaq	-44(%rbp), %rdx
	leaq	L_.str.7(%rip), %rsi
	leaq	-40(%rbp), %r8
	callq	_mep_cgen_assemble_insn
	movq	%rax, -56(%rbp)
	testq	%rax, %rax
	je	LBB0_24
## %bb.26:
	movq	-48(%rbp), %rsi
	movq	%rax, %rdi
	callq	_mep_save_insn
	jmp	LBB0_25
LBB0_11:
	leaq	L_.str.2(%rip), %rdi
LBB0_10:
	xorl	%eax, %eax
	addq	$32, %rsp
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_as_bad                         ## TAILCALL
LBB0_24:
	movq	-40(%rbp), %rsi
	leaq	L_.str.6(%rip), %rdi
	xorl	%eax, %eax
	callq	_as_bad
LBB0_25:
	addq	$32, %rsp
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_num_insns_saved,4,2            ## @num_insns_saved
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Internally paralled cores and coprocessors not supported."

	.comm	_saved_insns,8,3                ## @saved_insns
L_.str.1:                               ## @.str.1
	.asciz	"core and copro insn lengths must total 32 bits."

L_.str.2:                               ## @.str.2
	.asciz	"vliw group must consist of 1 core and 1 copro insn."

L_.str.3:                               ## @.str.3
	.asciz	"Cannot use 48- or 64-bit insns with a 32 bit datapath."

	.comm	_CGEN_INSN_VLIW32_NO_MATCHING_NOP,4,2 ## @CGEN_INSN_VLIW32_NO_MATCHING_NOP
L_.str.4:                               ## @.str.4
	.asciz	"No valid nop."

	.comm	_gas_cgen_cpu_desc,4,2          ## @gas_cgen_cpu_desc
L_.str.5:                               ## @.str.5
	.asciz	"nop"

L_.str.6:                               ## @.str.6
	.asciz	"%s"

	.comm	_MEP_INSN_BSR12,4,2             ## @MEP_INSN_BSR12
	.comm	_MEP_INSN_BEQZ,4,2              ## @MEP_INSN_BEQZ
	.comm	_MEP_INSN_BNEZ,4,2              ## @MEP_INSN_BNEZ
L_.str.7:                               ## @.str.7
	.asciz	"cpnop16"

	.no_dead_strip	_mep_check_parallel32_scheduling
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mep_check_parallel32_scheduling
_mep_check_parallel32_scheduling:       ; @mep_check_parallel32_scheduling
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
Lloh0:
	adrp	x21, _num_insns_saved@GOTPAGE
Lloh1:
	ldr	x21, [x21, _num_insns_saved@GOTPAGEOFF]
	ldr	w8, [x21]
	cmp	w8, #3
	b.lt	LBB0_2
; %bb.1:
Lloh2:
	adrp	x0, l_.str@PAGE
Lloh3:
	add	x0, x0, l_.str@PAGEOFF
	bl	_as_fatal
	ldr	w8, [x21]
LBB0_2:
	cbz	w8, LBB0_22
; %bb.3:
Lloh4:
	adrp	x22, _saved_insns@GOTPAGE
Lloh5:
	ldr	x22, [x22, _saved_insns@GOTPAGEOFF]
	ldr	x8, [x22]
	ldr	x0, [x8]
	bl	_MEP_INSN_COP_P
	mov	x19, x0
	ldr	x8, [x22]
	add	x0, x8, #12
	bl	_CGEN_FIELDS_BITSIZE
	mov	x20, x0
	ldr	w8, [x21]
	cmp	w8, #2
	b.ne	LBB0_7
; %bb.4:
	ldr	x8, [x22]
	ldr	x0, [x8, #16]
	bl	_MEP_INSN_COP_P
	mov	x21, x0
	ldr	x8, [x22]
	add	x0, x8, #28
	bl	_CGEN_FIELDS_BITSIZE
	cmp	w19, #0
	ccmp	w21, #0, #0, ne
	b.eq	LBB0_9
; %bb.5:
	cmp	w21, #0
	ccmp	w19, #0, #0, ne
	b.eq	LBB0_9
; %bb.6:
Lloh6:
	adrp	x0, l_.str.2@PAGE
Lloh7:
	add	x0, x0, l_.str.2@PAGEOFF
	b	LBB0_11
LBB0_7:
	cmp	w20, #33
	b.lt	LBB0_12
; %bb.8:
Lloh8:
	adrp	x0, l_.str.3@PAGE
Lloh9:
	add	x0, x0, l_.str.3@PAGEOFF
	bl	_as_fatal
	b	LBB0_13
LBB0_9:
	add	w8, w0, w20
	cmp	w8, #32
	b.eq	LBB0_22
; %bb.10:
Lloh10:
	adrp	x0, l_.str.1@PAGE
Lloh11:
	add	x0, x0, l_.str.1@PAGEOFF
LBB0_11:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #80
	b	_as_bad
LBB0_12:
	cmp	w20, #32
	b.eq	LBB0_22
LBB0_13:
	ldr	x8, [x22]
	ldr	x0, [x8]
Lloh12:
	adrp	x8, _CGEN_INSN_VLIW32_NO_MATCHING_NOP@GOTPAGE
Lloh13:
	ldr	x8, [x8, _CGEN_INSN_VLIW32_NO_MATCHING_NOP@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	bl	_CGEN_INSN_ATTR_VALUE
	cbz	x0, LBB0_15
; %bb.14:
Lloh15:
	adrp	x0, l_.str.4@PAGE
Lloh16:
	add	x0, x0, l_.str.4@PAGEOFF
	bl	_as_fatal
LBB0_15:
	cbz	w19, LBB0_18
; %bb.16:
Lloh17:
	adrp	x8, _gas_cgen_cpu_desc@GOTPAGE
Lloh18:
	ldr	x8, [x8, _gas_cgen_cpu_desc@GOTPAGEOFF]
Lloh19:
	ldr	w0, [x8]
	add	x8, sp, #8
	add	x2, x8, #12
Lloh20:
	adrp	x1, l_.str.5@PAGE
Lloh21:
	add	x1, x1, l_.str.5@PAGEOFF
	add	x4, sp, #24
	bl	_mep_cgen_assemble_insn
	str	x0, [sp, #8]
	cbz	x0, LBB0_21
; %bb.17:
	ldr	x8, [x22]
	ldr	q0, [x8]
	ldur	q1, [sp, #8]
	stp	q1, q0, [x8]
	ldr	w8, [x21]
	add	w8, w8, #1
	str	w8, [x21]
	mov	w0, #0
	bl	_gas_cgen_swap_fixups
	mov	w0, #1
	bl	_gas_cgen_save_fixups
	b	LBB0_22
LBB0_18:
	ldr	x8, [x22]
	ldr	x8, [x8]
	ldr	x8, [x8]
	ldr	w8, [x8]
Lloh22:
	adrp	x9, _MEP_INSN_BSR12@GOTPAGE
Lloh23:
	ldr	x9, [x9, _MEP_INSN_BSR12@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
Lloh25:
	adrp	x10, _MEP_INSN_BEQZ@GOTPAGE
Lloh26:
	ldr	x10, [x10, _MEP_INSN_BEQZ@GOTPAGEOFF]
Lloh27:
	ldr	w10, [x10]
Lloh28:
	adrp	x11, _MEP_INSN_BNEZ@GOTPAGE
Lloh29:
	ldr	x11, [x11, _MEP_INSN_BNEZ@GOTPAGEOFF]
Lloh30:
	ldr	w11, [x11]
	cmp	w8, w9
	ccmp	w8, w10, #4, ne
	ccmp	w8, w11, #4, ne
	b.eq	LBB0_22
; %bb.19:
Lloh31:
	adrp	x8, _gas_cgen_cpu_desc@GOTPAGE
Lloh32:
	ldr	x8, [x8, _gas_cgen_cpu_desc@GOTPAGEOFF]
Lloh33:
	ldr	w0, [x8]
	add	x8, sp, #8
	add	x2, x8, #12
Lloh34:
	adrp	x1, l_.str.7@PAGE
Lloh35:
	add	x1, x1, l_.str.7@PAGEOFF
	add	x4, sp, #24
	bl	_mep_cgen_assemble_insn
	str	x0, [sp, #8]
	cbz	x0, LBB0_21
; %bb.20:
	ldr	x1, [sp, #16]
	bl	_mep_save_insn
	b	LBB0_22
LBB0_21:
	ldr	x8, [sp, #24]
	str	x8, [sp]
Lloh36:
	adrp	x0, l_.str.6@PAGE
Lloh37:
	add	x0, x0, l_.str.6@PAGEOFF
	bl	_as_bad
LBB0_22:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpAdd	Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpAdd	Lloh36, Lloh37
	.cfi_endproc
                                        ; -- End function
	.comm	_num_insns_saved,4,2            ; @num_insns_saved
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Internally paralled cores and coprocessors not supported."

	.comm	_saved_insns,8,3                ; @saved_insns
l_.str.1:                               ; @.str.1
	.asciz	"core and copro insn lengths must total 32 bits."

l_.str.2:                               ; @.str.2
	.asciz	"vliw group must consist of 1 core and 1 copro insn."

l_.str.3:                               ; @.str.3
	.asciz	"Cannot use 48- or 64-bit insns with a 32 bit datapath."

	.comm	_CGEN_INSN_VLIW32_NO_MATCHING_NOP,4,2 ; @CGEN_INSN_VLIW32_NO_MATCHING_NOP
l_.str.4:                               ; @.str.4
	.asciz	"No valid nop."

	.comm	_gas_cgen_cpu_desc,4,2          ; @gas_cgen_cpu_desc
l_.str.5:                               ; @.str.5
	.asciz	"nop"

l_.str.6:                               ; @.str.6
	.asciz	"%s"

	.comm	_MEP_INSN_BSR12,4,2             ; @MEP_INSN_BSR12
	.comm	_MEP_INSN_BEQZ,4,2              ; @MEP_INSN_BEQZ
	.comm	_MEP_INSN_BNEZ,4,2              ; @MEP_INSN_BNEZ
l_.str.7:                               ; @.str.7
	.asciz	"cpnop16"

	.no_dead_strip	_mep_check_parallel32_scheduling
.subsections_via_symbols
