	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mep_check_parallel64_scheduling
_mep_check_parallel64_scheduling:       ## @mep_check_parallel64_scheduling
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_num_insns_saved@GOTPCREL(%rip), %rbx
	movl	(%rbx), %eax
	cmpl	$3, %eax
	jl	LBB0_2
## %bb.1:
	leaq	L_.str(%rip), %rdi
	callq	_as_fatal
	movl	(%rbx), %eax
LBB0_2:
	testl	%eax, %eax
	je	LBB0_13
## %bb.3:
	movq	_saved_insns@GOTPCREL(%rip), %r13
	movq	(%r13), %rax
	movq	8(%rax), %rdi
	callq	_MEP_INSN_COP_P
	movl	%eax, %r14d
	movq	(%r13), %rdi
	addq	$16, %rdi
	callq	_CGEN_FIELDS_BITSIZE
	movl	%eax, %r12d
	cmpl	$2, (%rbx)
	jne	LBB0_11
## %bb.4:
	movq	(%r13), %rax
	movq	32(%rax), %rdi
	callq	_MEP_INSN_COP_P
	movl	%eax, %r15d
	movq	(%r13), %rdi
	addq	$40, %rdi
	callq	_CGEN_FIELDS_BITSIZE
	testl	%r14d, %r14d
	je	LBB0_6
## %bb.5:
	testl	%r15d, %r15d
	je	LBB0_8
LBB0_6:
	leaq	L_.str.2(%rip), %rdi
	testl	%r15d, %r15d
	je	LBB0_10
## %bb.7:
	testl	%r14d, %r14d
	jne	LBB0_10
LBB0_8:
	addl	%r12d, %eax
	cmpl	$64, %eax
	je	LBB0_13
## %bb.9:
	leaq	L_.str.1(%rip), %rdi
LBB0_10:
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_as_bad                         ## TAILCALL
LBB0_11:
	cmpl	$64, %r12d
	jne	LBB0_12
LBB0_13:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_12:
	callq	_mep_check_parallel64_scheduling.cold.1
	jmp	LBB0_13
	.cfi_endproc
                                        ## -- End function
	.p2align	4, 0x90                         ## -- Begin function mep_check_parallel64_scheduling.cold.1
_mep_check_parallel64_scheduling.cold.1: ## @mep_check_parallel64_scheduling.cold.1
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	_saved_insns@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	8(%rax), %rdi
	movq	_CGEN_INSN_VLIW64_NO_MATCHING_NOP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_CGEN_INSN_ATTR_VALUE
	leaq	L_.str.3(%rip), %rdi
	callq	_as_fatal
	ud2
	.cfi_endproc
                                        ## -- End function
	.comm	_num_insns_saved,4,2            ## @num_insns_saved
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Internally parallel cores of coprocessors not supported."

	.comm	_saved_insns,8,3                ## @saved_insns
L_.str.1:                               ## @.str.1
	.asciz	"core and copro insn lengths must total 64 bits."

L_.str.2:                               ## @.str.2
	.asciz	"vliw group must consist of 1 core and 1 copro insn."

	.comm	_CGEN_INSN_VLIW64_NO_MATCHING_NOP,4,2 ## @CGEN_INSN_VLIW64_NO_MATCHING_NOP
L_.str.3:                               ## @.str.3
	.asciz	"No valid nop."

	.comm	_gas_cgen_cpu_desc,4,2          ## @gas_cgen_cpu_desc
	.no_dead_strip	_mep_check_parallel64_scheduling
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mep_check_parallel64_scheduling
_mep_check_parallel64_scheduling:       ; @mep_check_parallel64_scheduling
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
Lloh0:
	adrp	x21, _num_insns_saved@GOTPAGE
Lloh1:
	ldr	x21, [x21, _num_insns_saved@GOTPAGEOFF]
	ldr	w8, [x21]
	cmp	w8, #3
	b.lt	LBB0_2
; %bb.1:
Lloh2:
	adrp	x0, l_.str@PAGE
Lloh3:
	add	x0, x0, l_.str@PAGEOFF
	bl	_as_fatal
	ldr	w8, [x21]
LBB0_2:
	cbz	w8, LBB0_10
; %bb.3:
Lloh4:
	adrp	x22, _saved_insns@GOTPAGE
Lloh5:
	ldr	x22, [x22, _saved_insns@GOTPAGEOFF]
	ldr	x8, [x22]
	ldr	x0, [x8, #8]
	bl	_MEP_INSN_COP_P
	mov	x19, x0
	ldr	x8, [x22]
	add	x0, x8, #16
	bl	_CGEN_FIELDS_BITSIZE
	mov	x20, x0
	ldr	w8, [x21]
	cmp	w8, #2
	b.ne	LBB0_7
; %bb.4:
	ldr	x8, [x22]
	ldr	x0, [x8, #32]
	bl	_MEP_INSN_COP_P
	mov	x21, x0
	ldr	x8, [x22]
	add	x0, x8, #40
	bl	_CGEN_FIELDS_BITSIZE
	cmp	w19, #0
	ccmp	w21, #0, #0, ne
	b.eq	LBB0_9
; %bb.5:
	cmp	w21, #0
	ccmp	w19, #0, #0, ne
	b.eq	LBB0_9
; %bb.6:
Lloh6:
	adrp	x0, l_.str.2@PAGE
Lloh7:
	add	x0, x0, l_.str.2@PAGEOFF
	b	LBB0_12
LBB0_7:
	cmp	w20, #64
	b.eq	LBB0_10
; %bb.8:
	bl	_mep_check_parallel64_scheduling.cold.1
LBB0_9:
	add	w8, w0, w20
	cmp	w8, #64
	b.ne	LBB0_11
LBB0_10:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_11:
Lloh8:
	adrp	x0, l_.str.1@PAGE
Lloh9:
	add	x0, x0, l_.str.1@PAGEOFF
LBB0_12:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_as_bad
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpAdd	Lloh8, Lloh9
	.cfi_endproc
                                        ; -- End function
	.p2align	2                               ; -- Begin function mep_check_parallel64_scheduling.cold.1
_mep_check_parallel64_scheduling.cold.1: ; @mep_check_parallel64_scheduling.cold.1
	.cfi_startproc
; %bb.0:
	stp	x29, x30, [sp, #-16]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 16
	mov	x29, sp
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
Lloh10:
	adrp	x8, _saved_insns@GOTPAGE
Lloh11:
	ldr	x8, [x8, _saved_insns@GOTPAGEOFF]
Lloh12:
	ldr	x8, [x8]
	ldr	x0, [x8, #8]
Lloh13:
	adrp	x8, _CGEN_INSN_VLIW64_NO_MATCHING_NOP@GOTPAGE
Lloh14:
	ldr	x8, [x8, _CGEN_INSN_VLIW64_NO_MATCHING_NOP@GOTPAGEOFF]
Lloh15:
	ldr	w1, [x8]
	bl	_CGEN_INSN_ATTR_VALUE
Lloh16:
	adrp	x0, l_.str.3@PAGE
Lloh17:
	add	x0, x0, l_.str.3@PAGEOFF
	bl	_as_fatal
	brk	#0x1
	.loh AdrpAdd	Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.cfi_endproc
                                        ; -- End function
	.comm	_num_insns_saved,4,2            ; @num_insns_saved
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Internally parallel cores of coprocessors not supported."

	.comm	_saved_insns,8,3                ; @saved_insns
l_.str.1:                               ; @.str.1
	.asciz	"core and copro insn lengths must total 64 bits."

l_.str.2:                               ; @.str.2
	.asciz	"vliw group must consist of 1 core and 1 copro insn."

	.comm	_CGEN_INSN_VLIW64_NO_MATCHING_NOP,4,2 ; @CGEN_INSN_VLIW64_NO_MATCHING_NOP
l_.str.3:                               ; @.str.3
	.asciz	"No valid nop."

	.comm	_gas_cgen_cpu_desc,4,2          ; @gas_cgen_cpu_desc
	.no_dead_strip	_mep_check_parallel64_scheduling
.subsections_via_symbols
