	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_mips_after_parse_args          ## -- Begin function mips_after_parse_args
	.p2align	4, 0x90
_mips_after_parse_args:                 ## @mips_after_parse_args
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_TARGET_OS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	leaq	L_.str(%rip), %rsi
	movl	$2, %edx
	callq	_strncmp
	testq	%rax, %rax
	jne	LBB0_5
## %bb.1:
	movq	_g_switch_seen@GOTPCREL(%rip), %rax
	cmpq	$0, (%rax)
	movq	_g_switch_value@GOTPCREL(%rip), %rbx
	je	LBB0_4
## %bb.2:
	cmpq	$0, (%rbx)
	je	LBB0_4
## %bb.3:
	leaq	L_.str.1(%rip), %rdi
	callq	__
	movslq	%eax, %rdi
	xorl	%eax, %eax
	callq	_as_bad
LBB0_4:
	movq	$0, (%rbx)
LBB0_5:
	movq	_mips_abi@GOTPCREL(%rip), %r12
	movq	(%r12), %rax
	movq	_NO_ABI@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_7
## %bb.6:
	movq	_MIPS_DEFAULT_ABI@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, (%r12)
LBB0_7:
	movq	_mips_arch_string@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	testq	%rsi, %rsi
	je	LBB0_12
## %bb.8:
	leaq	L_.str.2(%rip), %rdi
	callq	_mips_parse_cpu
	movq	%rax, %r14
	movq	_file_mips_isa@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	movq	_ISA_UNKNOWN@GOTPCREL(%rip), %rax
	cmpq	(%rax), %rdi
	je	LBB0_14
## %bb.9:
	testq	%r14, %r14
	je	LBB0_13
## %bb.10:
	cmpq	(%r14), %rdi
	je	LBB0_16
## %bb.11:
	leaq	L_.str.3(%rip), %rdi
	callq	__
	movslq	%eax, %r13
	movq	(%rbx), %rdi
	callq	_mips_cpu_info_from_isa
	movl	12(%rax), %r15d
	movq	(%r14), %rdi
	callq	_mips_cpu_info_from_isa
	movl	12(%rax), %edx
	movq	%r13, %rdi
	movl	%r15d, %esi
	xorl	%eax, %eax
	callq	_as_bad
	jmp	LBB0_16
LBB0_12:
	movq	_file_mips_isa@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movq	_ISA_UNKNOWN@GOTPCREL(%rip), %rax
	cmpq	(%rax), %rdi
	je	LBB0_15
LBB0_13:
	callq	_mips_cpu_info_from_isa
	movq	%rax, %r14
LBB0_14:
	testq	%r14, %r14
	jne	LBB0_16
LBB0_15:
	movq	_MIPS_CPU_STRING_DEFAULT@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	leaq	L_.str.4(%rip), %rdi
	callq	_mips_parse_cpu
	movq	%rax, %r14
LBB0_16:
	movq	(%r12), %rdi
	callq	_ABI_NEEDS_64BIT_REGS
	testq	%rax, %rax
	je	LBB0_19
## %bb.17:
	movq	(%r14), %rdi
	callq	_ISA_HAS_64BIT_REGS
	testq	%rax, %rax
	jne	LBB0_19
## %bb.18:
	movl	12(%r14), %esi
	leaq	L_.str.5(%rip), %rdi
	xorl	%eax, %eax
	callq	_as_bad
LBB0_19:
	movq	%r14, %rdi
	callq	_mips_set_architecture
	movq	_mips_tune_string@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	testq	%rsi, %rsi
	je	LBB0_22
## %bb.20:
	leaq	L_.str.6(%rip), %rdi
	callq	_mips_parse_cpu
	testq	%rax, %rax
	je	LBB0_22
## %bb.21:
	movq	%rax, %rdi
	jmp	LBB0_23
LBB0_22:
	movq	%r14, %rdi
LBB0_23:
	callq	_mips_set_tune
	movq	_file_mips_gp32@GOTPCREL(%rip), %rbx
	movl	(%rbx), %eax
	testl	%eax, %eax
	js	LBB0_27
## %bb.24:
	je	LBB0_30
## %bb.25:
	cmpl	$1, %eax
	jne	LBB0_26
LBB0_32:
	movq	(%r12), %rdi
	callq	_ABI_NEEDS_64BIT_REGS
	testq	%rax, %rax
	je	LBB0_34
## %bb.33:
	leaq	L_.str.8(%rip), %rdi
	jmp	LBB0_38
LBB0_27:
	movq	(%r12), %rdi
	callq	_ABI_NEEDS_32BIT_REGS
	movb	$1, %cl
	testq	%rax, %rax
	jne	LBB0_29
## %bb.28:
	movq	_mips_opts@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_ISA_HAS_64BIT_REGS
	testq	%rax, %rax
	sete	%cl
LBB0_29:
	movzbl	%cl, %eax
	movl	%eax, (%rbx)
	jmp	LBB0_39
LBB0_30:
	movq	_mips_opts@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_ISA_HAS_64BIT_REGS
	testq	%rax, %rax
	je	LBB0_37
## %bb.31:
	movl	(%rbx), %eax
	cmpl	$1, %eax
	je	LBB0_32
LBB0_26:
	testl	%eax, %eax
	jne	LBB0_39
	jmp	LBB0_35
LBB0_34:
	movl	(%rbx), %eax
	testl	%eax, %eax
	jne	LBB0_39
LBB0_35:
	movq	(%r12), %rdi
	callq	_ABI_NEEDS_32BIT_REGS
	testq	%rax, %rax
	je	LBB0_39
## %bb.36:
	leaq	L_.str.9(%rip), %rdi
	jmp	LBB0_38
LBB0_37:
	leaq	L_.str.7(%rip), %rdi
LBB0_38:
	callq	__
	movslq	%eax, %rdi
	xorl	%eax, %eax
	callq	_as_bad
LBB0_39:
	movq	_file_mips_fp32@GOTPCREL(%rip), %r15
	movl	(%r15), %eax
	testl	%eax, %eax
	je	LBB0_43
## %bb.40:
	cmpl	$1, %eax
	jne	LBB0_48
## %bb.41:
	movq	(%r12), %rdi
	callq	_ABI_NEEDS_64BIT_REGS
	testq	%rax, %rax
	je	LBB0_56
## %bb.42:
	leaq	L_.str.12(%rip), %rdi
	jmp	LBB0_47
LBB0_43:
	movq	_mips_opts@GOTPCREL(%rip), %r13
	movq	(%r13), %rdi
	callq	_ISA_HAS_64BIT_FPRS
	testl	%eax, %eax
	je	LBB0_54
## %bb.44:
	movq	(%r12), %rdi
	callq	_ABI_NEEDS_32BIT_REGS
	testq	%rax, %rax
	je	LBB0_56
## %bb.45:
	movq	(%r13), %rdi
	callq	_ISA_HAS_MXHC1
	testl	%eax, %eax
	jne	LBB0_56
## %bb.46:
	leaq	L_.str.11(%rip), %rdi
LBB0_47:
	callq	__
	movslq	%eax, %rdi
	xorl	%eax, %eax
	callq	_as_warn
	jmp	LBB0_56
LBB0_48:
	cmpl	$0, (%rbx)
	je	LBB0_55
## %bb.49:
	movq	_mips_opts@GOTPCREL(%rip), %rax
	cmpl	$0, 8(%rax)
	jg	LBB0_51
## %bb.50:
	cmpl	$0, 12(%rax)
	jle	LBB0_53
LBB0_51:
	movq	(%rax), %rdi
	callq	_ISA_HAS_64BIT_FPRS
	testl	%eax, %eax
	je	LBB0_53
LBB0_55:
	movl	$0, (%r15)
	jmp	LBB0_56
LBB0_53:
	movl	$1, (%r15)
	jmp	LBB0_56
LBB0_54:
	leaq	L_.str.10(%rip), %rdi
	callq	__
	movslq	%eax, %rdi
	xorl	%eax, %eax
	callq	_as_bad
LBB0_56:
	movq	_mips_opts@GOTPCREL(%rip), %r13
	movq	(%r13), %rdi
	callq	_ISA_HAS_64BIT_REGS
	testq	%rax, %rax
	je	LBB0_60
## %bb.57:
	movq	(%r12), %rax
	movq	_NO_ABI@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	sete	%cl
	cmpl	$1, (%rbx)
	sete	%dl
	testb	%dl, %cl
	jne	LBB0_59
## %bb.58:
	movq	_O32_ABI@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_60
LBB0_59:
	movq	_mips_32bitmode@GOTPCREL(%rip), %rax
	movl	$1, (%rax)
LBB0_60:
	movq	(%r13), %rax
	movq	_ISA_MIPS1@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_63
## %bb.61:
	movq	_mips_trap@GOTPCREL(%rip), %rax
	cmpq	$0, (%rax)
	je	LBB0_63
## %bb.62:
	leaq	L_.str.13(%rip), %rdi
	callq	__
	movslq	%eax, %rdi
	xorl	%eax, %eax
	callq	_as_bad
LBB0_63:
	cmpl	$-1, 16(%r13)
	jne	LBB0_65
## %bb.64:
	movq	_file_mips_arch@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_CPU_HAS_MIPS16
	xorl	%ecx, %ecx
	testq	%rax, %rax
	setne	%cl
	movl	%ecx, 16(%r13)
LBB0_65:
	movl	8(%r13), %ecx
	cmpl	$-1, %ecx
	je	LBB0_67
## %bb.66:
	movl	(%r15), %eax
	testl	%ecx, %ecx
	jne	LBB0_68
	jmp	LBB0_70
LBB0_67:
	movq	_MIPS_CPU_ASE_MIPS3D@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	8(%r14), %eax
	setne	%cl
	movl	(%r15), %eax
	testl	%eax, %eax
	sete	%dl
	andb	%cl, %dl
	movzbl	%dl, %ecx
	movl	%ecx, 8(%r13)
	testl	%ecx, %ecx
	je	LBB0_70
LBB0_68:
	cmpl	$1, %eax
	jne	LBB0_70
## %bb.69:
	leaq	L_.str.14(%rip), %rdi
	callq	__
	movslq	%eax, %rdi
	xorl	%eax, %eax
	callq	_as_bad
LBB0_70:
	movl	12(%r13), %ecx
	cmpl	$-1, %ecx
	je	LBB0_72
## %bb.71:
	movl	(%r15), %eax
	testl	%ecx, %ecx
	jne	LBB0_73
	jmp	LBB0_75
LBB0_72:
	movq	_MIPS_CPU_ASE_MDMX@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	8(%r14), %eax
	setne	%cl
	movl	(%r15), %eax
	testl	%eax, %eax
	sete	%dl
	andb	%cl, %dl
	movzbl	%dl, %ecx
	movl	%ecx, 12(%r13)
	testl	%ecx, %ecx
	je	LBB0_75
LBB0_73:
	cmpl	$1, %eax
	jne	LBB0_75
## %bb.74:
	leaq	L_.str.15(%rip), %rdi
	callq	__
	movslq	%eax, %rdi
	xorl	%eax, %eax
	callq	_as_bad
LBB0_75:
	movl	20(%r13), %eax
	cmpl	$-1, %eax
	jne	LBB0_77
## %bb.76:
	movq	_MIPS_CPU_ASE_SMARTMIPS@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%eax, %eax
	andl	8(%r14), %ecx
	setne	%al
	movl	%eax, 20(%r13)
LBB0_77:
	testl	%eax, %eax
	je	LBB0_80
## %bb.78:
	movq	_ISA_SUPPORTS_SMARTMIPS@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	jne	LBB0_80
## %bb.79:
	movq	(%r13), %rdi
	callq	_mips_cpu_info_from_isa
	movl	12(%rax), %esi
	leaq	L_.str.16(%rip), %rdi
	xorl	%eax, %eax
	callq	_as_warn
LBB0_80:
	movl	24(%r13), %eax
	cmpl	$-1, %eax
	jne	LBB0_82
## %bb.81:
	movq	_MIPS_CPU_ASE_DSP@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%eax, %eax
	andl	8(%r14), %ecx
	setne	%al
	movl	%eax, 24(%r13)
LBB0_82:
	testl	%eax, %eax
	je	LBB0_85
## %bb.83:
	movq	_ISA_SUPPORTS_DSP_ASE@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	jne	LBB0_85
## %bb.84:
	movq	(%r13), %rdi
	callq	_mips_cpu_info_from_isa
	movl	12(%rax), %esi
	leaq	L_.str.17(%rip), %rdi
	xorl	%eax, %eax
	callq	_as_warn
LBB0_85:
	movl	28(%r13), %eax
	cmpl	$-1, %eax
	jne	LBB0_87
## %bb.86:
	movl	8(%r14), %ecx
	movq	_MIPS_CPU_ASE_DSPR2@GOTPCREL(%rip), %rdx
	xorl	%eax, %eax
	movl	(%rdx), %edx
	andl	%ecx, %edx
	setne	%al
	movl	%eax, 28(%r13)
	movq	_MIPS_CPU_ASE_DSP@GOTPCREL(%rip), %rdx
	xorl	%esi, %esi
	andl	(%rdx), %ecx
	setne	%sil
	movl	%esi, 24(%r13)
LBB0_87:
	testl	%eax, %eax
	je	LBB0_90
## %bb.88:
	movq	_ISA_SUPPORTS_DSPR2_ASE@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	jne	LBB0_90
## %bb.89:
	movq	(%r13), %rdi
	callq	_mips_cpu_info_from_isa
	movl	12(%rax), %esi
	leaq	L_.str.18(%rip), %rdi
	xorl	%eax, %eax
	callq	_as_warn
LBB0_90:
	movl	32(%r13), %eax
	cmpl	$-1, %eax
	jne	LBB0_92
## %bb.91:
	movq	_MIPS_CPU_ASE_MT@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%eax, %eax
	andl	8(%r14), %ecx
	setne	%al
	movl	%eax, 32(%r13)
LBB0_92:
	testl	%eax, %eax
	je	LBB0_95
## %bb.93:
	movq	_ISA_SUPPORTS_MT_ASE@GOTPCREL(%rip), %rcx
	cmpl	$0, (%rcx)
	jne	LBB0_95
## %bb.94:
	movq	(%r13), %rdi
	callq	_mips_cpu_info_from_isa
	movl	12(%rax), %esi
	leaq	L_.str.19(%rip), %rdi
	xorl	%eax, %eax
	callq	_as_warn
	movl	32(%r13), %eax
LBB0_95:
	movq	(%r13), %rcx
	movq	_file_mips_isa@GOTPCREL(%rip), %rdx
	movq	%rcx, (%rdx)
	movl	16(%r13), %ecx
	movq	_file_ase_mips16@GOTPCREL(%rip), %rdx
	movl	%ecx, (%rdx)
	movl	8(%r13), %ecx
	movq	_file_ase_mips3d@GOTPCREL(%rip), %rdx
	movl	%ecx, (%rdx)
	movl	12(%r13), %ecx
	movq	_file_ase_mdmx@GOTPCREL(%rip), %rdx
	movl	%ecx, (%rdx)
	movl	20(%r13), %ecx
	movq	_file_ase_smartmips@GOTPCREL(%rip), %rdx
	movl	%ecx, (%rdx)
	movl	24(%r13), %ecx
	movq	_file_ase_dsp@GOTPCREL(%rip), %rdx
	movl	%ecx, (%rdx)
	movl	28(%r13), %ecx
	movq	_file_ase_dspr2@GOTPCREL(%rip), %rdx
	movl	%ecx, (%rdx)
	movq	_file_ase_mt@GOTPCREL(%rip), %rcx
	movl	%eax, (%rcx)
	movl	(%rbx), %eax
	movl	%eax, 36(%r13)
	movl	(%r15), %eax
	movl	%eax, 40(%r13)
	movq	_mips_flag_mdebug@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	jns	LBB0_97
## %bb.96:
	movl	$0, (%rax)
LBB0_97:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_TARGET_OS,4,2                  ## @TARGET_OS
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"pe"

	.comm	_g_switch_seen,8,3              ## @g_switch_seen
	.comm	_g_switch_value,8,3             ## @g_switch_value
L_.str.1:                               ## @.str.1
	.asciz	"-G not supported in this configuration."

	.comm	_mips_abi,8,3                   ## @mips_abi
	.comm	_NO_ABI,8,3                     ## @NO_ABI
	.comm	_MIPS_DEFAULT_ABI,8,3           ## @MIPS_DEFAULT_ABI
	.comm	_mips_arch_string,8,3           ## @mips_arch_string
L_.str.2:                               ## @.str.2
	.asciz	"-march"

	.comm	_file_mips_isa,8,3              ## @file_mips_isa
	.comm	_ISA_UNKNOWN,8,3                ## @ISA_UNKNOWN
L_.str.3:                               ## @.str.3
	.asciz	"-%s conflicts with the other architecture options, which imply -%s"

L_.str.4:                               ## @.str.4
	.asciz	"default CPU"

	.comm	_MIPS_CPU_STRING_DEFAULT,8,3    ## @MIPS_CPU_STRING_DEFAULT
L_.str.5:                               ## @.str.5
	.asciz	"-march=%s is not compatible with the selected ABI"

	.comm	_mips_tune_string,8,3           ## @mips_tune_string
L_.str.6:                               ## @.str.6
	.asciz	"-mtune"

	.comm	_file_mips_gp32,4,2             ## @file_mips_gp32
	.comm	_mips_opts,48,3                 ## @mips_opts
L_.str.7:                               ## @.str.7
	.asciz	"-mgp64 used with a 32-bit processor"

L_.str.8:                               ## @.str.8
	.asciz	"-mgp32 used with a 64-bit ABI"

L_.str.9:                               ## @.str.9
	.asciz	"-mgp64 used with a 32-bit ABI"

	.comm	_file_mips_fp32,4,2             ## @file_mips_fp32
L_.str.10:                              ## @.str.10
	.asciz	"-mfp64 used with a 32-bit fpu"

L_.str.11:                              ## @.str.11
	.asciz	"-mfp64 used with a 32-bit ABI"

L_.str.12:                              ## @.str.12
	.asciz	"-mfp32 used with a 64-bit ABI"

	.comm	_O32_ABI,8,3                    ## @O32_ABI
	.comm	_mips_32bitmode,4,2             ## @mips_32bitmode
	.comm	_ISA_MIPS1,8,3                  ## @ISA_MIPS1
	.comm	_mips_trap,8,3                  ## @mips_trap
L_.str.13:                              ## @.str.13
	.asciz	"trap exception not supported at ISA 1"

	.comm	_file_mips_arch,4,2             ## @file_mips_arch
	.comm	_MIPS_CPU_ASE_MIPS3D,4,2        ## @MIPS_CPU_ASE_MIPS3D
L_.str.14:                              ## @.str.14
	.asciz	"-mfp32 used with -mips3d"

	.comm	_MIPS_CPU_ASE_MDMX,4,2          ## @MIPS_CPU_ASE_MDMX
L_.str.15:                              ## @.str.15
	.asciz	"-mfp32 used with -mdmx"

	.comm	_MIPS_CPU_ASE_SMARTMIPS,4,2     ## @MIPS_CPU_ASE_SMARTMIPS
	.comm	_ISA_SUPPORTS_SMARTMIPS,4,2     ## @ISA_SUPPORTS_SMARTMIPS
L_.str.16:                              ## @.str.16
	.asciz	"%s ISA does not support SmartMIPS"

	.comm	_MIPS_CPU_ASE_DSP,4,2           ## @MIPS_CPU_ASE_DSP
	.comm	_ISA_SUPPORTS_DSP_ASE,4,2       ## @ISA_SUPPORTS_DSP_ASE
L_.str.17:                              ## @.str.17
	.asciz	"%s ISA does not support DSP ASE"

	.comm	_MIPS_CPU_ASE_DSPR2,4,2         ## @MIPS_CPU_ASE_DSPR2
	.comm	_ISA_SUPPORTS_DSPR2_ASE,4,2     ## @ISA_SUPPORTS_DSPR2_ASE
L_.str.18:                              ## @.str.18
	.asciz	"%s ISA does not support DSP R2 ASE"

	.comm	_MIPS_CPU_ASE_MT,4,2            ## @MIPS_CPU_ASE_MT
	.comm	_ISA_SUPPORTS_MT_ASE,4,2        ## @ISA_SUPPORTS_MT_ASE
L_.str.19:                              ## @.str.19
	.asciz	"%s ISA does not support MT ASE"

	.comm	_file_ase_mips16,4,2            ## @file_ase_mips16
	.comm	_file_ase_mips3d,4,2            ## @file_ase_mips3d
	.comm	_file_ase_mdmx,4,2              ## @file_ase_mdmx
	.comm	_file_ase_smartmips,4,2         ## @file_ase_smartmips
	.comm	_file_ase_dsp,4,2               ## @file_ase_dsp
	.comm	_file_ase_dspr2,4,2             ## @file_ase_dspr2
	.comm	_file_ase_mt,4,2                ## @file_ase_mt
	.comm	_mips_flag_mdebug,4,2           ## @mips_flag_mdebug
	.comm	_OUTPUT_FLAVOR,8,3              ## @OUTPUT_FLAVOR
	.comm	_bfd_target_ecoff_flavour,8,3   ## @bfd_target_ecoff_flavour
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_mips_after_parse_args          ; -- Begin function mips_after_parse_args
	.p2align	2
_mips_after_parse_args:                 ; @mips_after_parse_args
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
Lloh0:
	adrp	x8, _TARGET_OS@GOTPAGE
Lloh1:
	ldr	x8, [x8, _TARGET_OS@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
Lloh3:
	adrp	x1, l_.str@PAGE
Lloh4:
	add	x1, x1, l_.str@PAGEOFF
	mov	w2, #2
	bl	_strncmp
	cbnz	x0, LBB0_4
; %bb.1:
Lloh5:
	adrp	x8, _g_switch_seen@GOTPAGE
Lloh6:
	ldr	x8, [x8, _g_switch_seen@GOTPAGEOFF]
Lloh7:
	ldr	x8, [x8]
Lloh8:
	adrp	x19, _g_switch_value@GOTPAGE
Lloh9:
	ldr	x19, [x19, _g_switch_value@GOTPAGEOFF]
	ldr	x9, [x19]
	cmp	x8, #0
	ccmp	x9, #0, #4, ne
	b.eq	LBB0_3
; %bb.2:
Lloh10:
	adrp	x0, l_.str.1@PAGE
Lloh11:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	__
                                        ; kill: def $w0 killed $w0 def $x0
	sxtw	x0, w0
	bl	_as_bad
LBB0_3:
	str	xzr, [x19]
LBB0_4:
Lloh12:
	adrp	x24, _mips_abi@GOTPAGE
Lloh13:
	ldr	x24, [x24, _mips_abi@GOTPAGEOFF]
	ldr	x8, [x24]
Lloh14:
	adrp	x25, _NO_ABI@GOTPAGE
Lloh15:
	ldr	x25, [x25, _NO_ABI@GOTPAGEOFF]
	ldr	x9, [x25]
	cmp	x8, x9
	b.ne	LBB0_6
; %bb.5:
Lloh16:
	adrp	x8, _MIPS_DEFAULT_ABI@GOTPAGE
Lloh17:
	ldr	x8, [x8, _MIPS_DEFAULT_ABI@GOTPAGEOFF]
Lloh18:
	ldr	x8, [x8]
	str	x8, [x24]
LBB0_6:
Lloh19:
	adrp	x8, _mips_arch_string@GOTPAGE
Lloh20:
	ldr	x8, [x8, _mips_arch_string@GOTPAGEOFF]
Lloh21:
	ldr	x1, [x8]
Lloh22:
	adrp	x21, _file_mips_isa@GOTPAGE
Lloh23:
	ldr	x21, [x21, _file_mips_isa@GOTPAGEOFF]
Lloh24:
	adrp	x20, _ISA_UNKNOWN@GOTPAGE
Lloh25:
	ldr	x20, [x20, _ISA_UNKNOWN@GOTPAGEOFF]
	cbz	x1, LBB0_11
; %bb.7:
Lloh26:
	adrp	x0, l_.str.2@PAGE
Lloh27:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	_mips_parse_cpu
	mov	x19, x0
	ldr	x0, [x21]
	ldr	x8, [x20]
	cmp	x0, x8
	b.eq	LBB0_13
; %bb.8:
	cbz	x19, LBB0_12
; %bb.9:
	ldr	x8, [x19]
	cmp	x0, x8
	b.eq	LBB0_15
; %bb.10:
Lloh28:
	adrp	x0, l_.str.3@PAGE
Lloh29:
	add	x0, x0, l_.str.3@PAGEOFF
	bl	__
                                        ; kill: def $w0 killed $w0 def $x0
	sxtw	x20, w0
	ldr	x0, [x21]
	bl	_mips_cpu_info_from_isa
	ldr	x8, [x19]
	ldr	w22, [x0, #12]
	mov	x0, x8
	bl	_mips_cpu_info_from_isa
	ldr	w8, [x0, #12]
	stp	x22, x8, [sp]
	mov	x0, x20
	bl	_as_bad
	b	LBB0_15
LBB0_11:
	ldr	x0, [x21]
	ldr	x8, [x20]
	cmp	x0, x8
	b.eq	LBB0_14
LBB0_12:
	bl	_mips_cpu_info_from_isa
	mov	x19, x0
LBB0_13:
	cbnz	x19, LBB0_15
LBB0_14:
Lloh30:
	adrp	x8, _MIPS_CPU_STRING_DEFAULT@GOTPAGE
Lloh31:
	ldr	x8, [x8, _MIPS_CPU_STRING_DEFAULT@GOTPAGEOFF]
Lloh32:
	ldr	x1, [x8]
Lloh33:
	adrp	x0, l_.str.4@PAGE
Lloh34:
	add	x0, x0, l_.str.4@PAGEOFF
	bl	_mips_parse_cpu
	mov	x19, x0
LBB0_15:
	ldr	x0, [x24]
	bl	_ABI_NEEDS_64BIT_REGS
	cbz	x0, LBB0_18
; %bb.16:
	ldr	x0, [x19]
	bl	_ISA_HAS_64BIT_REGS
	cbnz	x0, LBB0_18
; %bb.17:
	ldr	w8, [x19, #12]
	str	x8, [sp]
Lloh35:
	adrp	x0, l_.str.5@PAGE
Lloh36:
	add	x0, x0, l_.str.5@PAGEOFF
	bl	_as_bad
LBB0_18:
	mov	x0, x19
	bl	_mips_set_architecture
Lloh37:
	adrp	x8, _mips_tune_string@GOTPAGE
Lloh38:
	ldr	x8, [x8, _mips_tune_string@GOTPAGEOFF]
Lloh39:
	ldr	x1, [x8]
	cbz	x1, LBB0_20
; %bb.19:
Lloh40:
	adrp	x0, l_.str.6@PAGE
Lloh41:
	add	x0, x0, l_.str.6@PAGEOFF
	bl	_mips_parse_cpu
	cbnz	x0, LBB0_21
LBB0_20:
	mov	x0, x19
LBB0_21:
	bl	_mips_set_tune
Lloh42:
	adrp	x22, _file_mips_gp32@GOTPAGE
Lloh43:
	ldr	x22, [x22, _file_mips_gp32@GOTPAGEOFF]
	ldr	w8, [x22]
Lloh44:
	adrp	x20, _mips_opts@GOTPAGE
Lloh45:
	ldr	x20, [x20, _mips_opts@GOTPAGEOFF]
	tbnz	w8, #31, LBB0_26
; %bb.22:
	cbz	w8, LBB0_28
; %bb.23:
	cmp	w8, #1
	b.ne	LBB0_30
LBB0_24:
	ldr	x0, [x24]
	bl	_ABI_NEEDS_64BIT_REGS
	cbz	x0, LBB0_33
; %bb.25:
Lloh46:
	adrp	x0, l_.str.8@PAGE
Lloh47:
	add	x0, x0, l_.str.8@PAGEOFF
	b	LBB0_37
LBB0_26:
	ldr	x0, [x24]
	bl	_ABI_NEEDS_32BIT_REGS
	cbz	x0, LBB0_31
; %bb.27:
	mov	w8, #1
	b	LBB0_32
LBB0_28:
	ldr	x0, [x20]
	bl	_ISA_HAS_64BIT_REGS
	cbz	x0, LBB0_36
; %bb.29:
	ldr	w8, [x22]
	cmp	w8, #1
	b.eq	LBB0_24
LBB0_30:
	cbnz	w8, LBB0_38
	b	LBB0_34
LBB0_31:
	ldr	x0, [x20]
	bl	_ISA_HAS_64BIT_REGS
	cmp	x0, #0
	cset	w8, eq
LBB0_32:
	str	w8, [x22]
	b	LBB0_38
LBB0_33:
	ldr	w8, [x22]
	cbnz	w8, LBB0_38
LBB0_34:
	ldr	x0, [x24]
	bl	_ABI_NEEDS_32BIT_REGS
	cbz	x0, LBB0_38
; %bb.35:
Lloh48:
	adrp	x0, l_.str.9@PAGE
Lloh49:
	add	x0, x0, l_.str.9@PAGEOFF
	b	LBB0_37
LBB0_36:
Lloh50:
	adrp	x0, l_.str.7@PAGE
Lloh51:
	add	x0, x0, l_.str.7@PAGEOFF
LBB0_37:
	bl	__
                                        ; kill: def $w0 killed $w0 def $x0
	sxtw	x0, w0
	bl	_as_bad
LBB0_38:
Lloh52:
	adrp	x23, _file_mips_fp32@GOTPAGE
Lloh53:
	ldr	x23, [x23, _file_mips_fp32@GOTPAGEOFF]
	ldr	w8, [x23]
	cbz	w8, LBB0_42
; %bb.39:
	cmp	w8, #1
	b.ne	LBB0_47
; %bb.40:
	ldr	x0, [x24]
	bl	_ABI_NEEDS_64BIT_REGS
	cbz	x0, LBB0_54
; %bb.41:
Lloh54:
	adrp	x0, l_.str.12@PAGE
Lloh55:
	add	x0, x0, l_.str.12@PAGEOFF
	b	LBB0_46
LBB0_42:
	ldr	x0, [x20]
	bl	_ISA_HAS_64BIT_FPRS
	cbz	w0, LBB0_53
; %bb.43:
	ldr	x0, [x24]
	bl	_ABI_NEEDS_32BIT_REGS
	cbz	x0, LBB0_54
; %bb.44:
	ldr	x0, [x20]
	bl	_ISA_HAS_MXHC1
	cbnz	w0, LBB0_54
; %bb.45:
Lloh56:
	adrp	x0, l_.str.11@PAGE
Lloh57:
	add	x0, x0, l_.str.11@PAGEOFF
LBB0_46:
	bl	__
                                        ; kill: def $w0 killed $w0 def $x0
	sxtw	x0, w0
	bl	_as_warn
	b	LBB0_54
LBB0_47:
	ldr	w8, [x22]
	cbz	w8, LBB0_51
; %bb.48:
	ldr	w8, [x20, #8]
	cmp	w8, #0
	b.gt	LBB0_50
; %bb.49:
	ldr	w8, [x20, #12]
	cmp	w8, #1
	b.lt	LBB0_52
LBB0_50:
	ldr	x0, [x20]
	bl	_ISA_HAS_64BIT_FPRS
	cbz	w0, LBB0_52
LBB0_51:
	str	wzr, [x23]
	b	LBB0_54
LBB0_52:
	mov	w8, #1
	str	w8, [x23]
	b	LBB0_54
LBB0_53:
Lloh58:
	adrp	x0, l_.str.10@PAGE
Lloh59:
	add	x0, x0, l_.str.10@PAGEOFF
	bl	__
                                        ; kill: def $w0 killed $w0 def $x0
	sxtw	x0, w0
	bl	_as_bad
LBB0_54:
	ldr	x0, [x20]
	bl	_ISA_HAS_64BIT_REGS
	cbz	x0, LBB0_58
; %bb.55:
	ldr	x8, [x24]
	ldr	x9, [x25]
	ldr	w10, [x22]
	cmp	w10, #1
	ccmp	x8, x9, #0, eq
	b.eq	LBB0_57
; %bb.56:
Lloh60:
	adrp	x9, _O32_ABI@GOTPAGE
Lloh61:
	ldr	x9, [x9, _O32_ABI@GOTPAGEOFF]
Lloh62:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_58
LBB0_57:
Lloh63:
	adrp	x8, _mips_32bitmode@GOTPAGE
Lloh64:
	ldr	x8, [x8, _mips_32bitmode@GOTPAGEOFF]
	mov	w9, #1
Lloh65:
	str	w9, [x8]
LBB0_58:
	ldr	x8, [x20]
Lloh66:
	adrp	x9, _ISA_MIPS1@GOTPAGE
Lloh67:
	ldr	x9, [x9, _ISA_MIPS1@GOTPAGEOFF]
Lloh68:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_61
; %bb.59:
Lloh69:
	adrp	x8, _mips_trap@GOTPAGE
Lloh70:
	ldr	x8, [x8, _mips_trap@GOTPAGEOFF]
Lloh71:
	ldr	x8, [x8]
	cbz	x8, LBB0_61
; %bb.60:
Lloh72:
	adrp	x0, l_.str.13@PAGE
Lloh73:
	add	x0, x0, l_.str.13@PAGEOFF
	bl	__
                                        ; kill: def $w0 killed $w0 def $x0
	sxtw	x0, w0
	bl	_as_bad
LBB0_61:
	ldr	w8, [x20, #16]
	cmn	w8, #1
	b.ne	LBB0_63
; %bb.62:
Lloh74:
	adrp	x8, _file_mips_arch@GOTPAGE
Lloh75:
	ldr	x8, [x8, _file_mips_arch@GOTPAGEOFF]
Lloh76:
	ldr	w0, [x8]
	bl	_CPU_HAS_MIPS16
	cmp	x0, #0
	cset	w8, ne
	str	w8, [x20, #16]
LBB0_63:
	ldr	w9, [x20, #8]
	cmn	w9, #1
	b.eq	LBB0_65
; %bb.64:
	ldr	w8, [x23]
	cbnz	w9, LBB0_66
	b	LBB0_68
LBB0_65:
	ldr	w8, [x19, #8]
Lloh77:
	adrp	x9, _MIPS_CPU_ASE_MIPS3D@GOTPAGE
Lloh78:
	ldr	x9, [x9, _MIPS_CPU_ASE_MIPS3D@GOTPAGEOFF]
Lloh79:
	ldr	w9, [x9]
	tst	w9, w8
	ldr	w8, [x23]
	ccmp	w8, #0, #0, ne
	cset	w9, eq
	str	w9, [x20, #8]
	cbz	w9, LBB0_68
LBB0_66:
	cmp	w8, #1
	b.ne	LBB0_68
; %bb.67:
Lloh80:
	adrp	x0, l_.str.14@PAGE
Lloh81:
	add	x0, x0, l_.str.14@PAGEOFF
	bl	__
                                        ; kill: def $w0 killed $w0 def $x0
	sxtw	x0, w0
	bl	_as_bad
LBB0_68:
	ldr	w9, [x20, #12]
	cmn	w9, #1
	b.eq	LBB0_70
; %bb.69:
	ldr	w8, [x23]
	cbnz	w9, LBB0_71
	b	LBB0_73
LBB0_70:
	ldr	w8, [x19, #8]
Lloh82:
	adrp	x9, _MIPS_CPU_ASE_MDMX@GOTPAGE
Lloh83:
	ldr	x9, [x9, _MIPS_CPU_ASE_MDMX@GOTPAGEOFF]
Lloh84:
	ldr	w9, [x9]
	tst	w9, w8
	ldr	w8, [x23]
	ccmp	w8, #0, #0, ne
	cset	w9, eq
	str	w9, [x20, #12]
	cbz	w9, LBB0_73
LBB0_71:
	cmp	w8, #1
	b.ne	LBB0_73
; %bb.72:
Lloh85:
	adrp	x0, l_.str.15@PAGE
Lloh86:
	add	x0, x0, l_.str.15@PAGEOFF
	bl	__
                                        ; kill: def $w0 killed $w0 def $x0
	sxtw	x0, w0
	bl	_as_bad
LBB0_73:
	ldr	w8, [x20, #20]
	cmn	w8, #1
	b.ne	LBB0_75
; %bb.74:
	ldr	w8, [x19, #8]
Lloh87:
	adrp	x9, _MIPS_CPU_ASE_SMARTMIPS@GOTPAGE
Lloh88:
	ldr	x9, [x9, _MIPS_CPU_ASE_SMARTMIPS@GOTPAGEOFF]
Lloh89:
	ldr	w9, [x9]
	tst	w9, w8
	cset	w8, ne
	str	w8, [x20, #20]
LBB0_75:
	cbz	w8, LBB0_78
; %bb.76:
Lloh90:
	adrp	x8, _ISA_SUPPORTS_SMARTMIPS@GOTPAGE
Lloh91:
	ldr	x8, [x8, _ISA_SUPPORTS_SMARTMIPS@GOTPAGEOFF]
Lloh92:
	ldr	w8, [x8]
	cbnz	w8, LBB0_78
; %bb.77:
	ldr	x0, [x20]
	bl	_mips_cpu_info_from_isa
	ldr	w8, [x0, #12]
	str	x8, [sp]
Lloh93:
	adrp	x0, l_.str.16@PAGE
Lloh94:
	add	x0, x0, l_.str.16@PAGEOFF
	bl	_as_warn
LBB0_78:
	ldr	w8, [x20, #24]
	cmn	w8, #1
	b.ne	LBB0_80
; %bb.79:
	ldr	w8, [x19, #8]
Lloh95:
	adrp	x9, _MIPS_CPU_ASE_DSP@GOTPAGE
Lloh96:
	ldr	x9, [x9, _MIPS_CPU_ASE_DSP@GOTPAGEOFF]
Lloh97:
	ldr	w9, [x9]
	tst	w9, w8
	cset	w8, ne
	str	w8, [x20, #24]
LBB0_80:
	cbz	w8, LBB0_83
; %bb.81:
Lloh98:
	adrp	x8, _ISA_SUPPORTS_DSP_ASE@GOTPAGE
Lloh99:
	ldr	x8, [x8, _ISA_SUPPORTS_DSP_ASE@GOTPAGEOFF]
Lloh100:
	ldr	w8, [x8]
	cbnz	w8, LBB0_83
; %bb.82:
	ldr	x0, [x20]
	bl	_mips_cpu_info_from_isa
	ldr	w8, [x0, #12]
	str	x8, [sp]
Lloh101:
	adrp	x0, l_.str.17@PAGE
Lloh102:
	add	x0, x0, l_.str.17@PAGEOFF
	bl	_as_warn
LBB0_83:
	ldr	w8, [x20, #28]
	cmn	w8, #1
	b.ne	LBB0_85
; %bb.84:
	ldr	w9, [x19, #8]
Lloh103:
	adrp	x8, _MIPS_CPU_ASE_DSPR2@GOTPAGE
Lloh104:
	ldr	x8, [x8, _MIPS_CPU_ASE_DSPR2@GOTPAGEOFF]
Lloh105:
	ldr	w8, [x8]
	tst	w8, w9
Lloh106:
	adrp	x10, _MIPS_CPU_ASE_DSP@GOTPAGE
Lloh107:
	ldr	x10, [x10, _MIPS_CPU_ASE_DSP@GOTPAGEOFF]
	cset	w8, ne
Lloh108:
	ldr	w10, [x10]
	tst	w10, w9
	cset	w9, ne
	stp	w9, w8, [x20, #24]
LBB0_85:
	cbz	w8, LBB0_88
; %bb.86:
Lloh109:
	adrp	x8, _ISA_SUPPORTS_DSPR2_ASE@GOTPAGE
Lloh110:
	ldr	x8, [x8, _ISA_SUPPORTS_DSPR2_ASE@GOTPAGEOFF]
Lloh111:
	ldr	w8, [x8]
	cbnz	w8, LBB0_88
; %bb.87:
	ldr	x0, [x20]
	bl	_mips_cpu_info_from_isa
	ldr	w8, [x0, #12]
	str	x8, [sp]
Lloh112:
	adrp	x0, l_.str.18@PAGE
Lloh113:
	add	x0, x0, l_.str.18@PAGEOFF
	bl	_as_warn
LBB0_88:
	ldr	w8, [x20, #32]
	cmn	w8, #1
	b.ne	LBB0_90
; %bb.89:
	ldr	w8, [x19, #8]
Lloh114:
	adrp	x9, _MIPS_CPU_ASE_MT@GOTPAGE
Lloh115:
	ldr	x9, [x9, _MIPS_CPU_ASE_MT@GOTPAGEOFF]
Lloh116:
	ldr	w9, [x9]
	tst	w9, w8
	cset	w8, ne
	str	w8, [x20, #32]
LBB0_90:
	cbz	w8, LBB0_93
; %bb.91:
Lloh117:
	adrp	x9, _ISA_SUPPORTS_MT_ASE@GOTPAGE
Lloh118:
	ldr	x9, [x9, _ISA_SUPPORTS_MT_ASE@GOTPAGEOFF]
Lloh119:
	ldr	w9, [x9]
	cbnz	w9, LBB0_93
; %bb.92:
	ldr	x0, [x20]
	bl	_mips_cpu_info_from_isa
	ldr	w8, [x0, #12]
	str	x8, [sp]
Lloh120:
	adrp	x0, l_.str.19@PAGE
Lloh121:
	add	x0, x0, l_.str.19@PAGEOFF
	bl	_as_warn
	ldr	w8, [x20, #32]
LBB0_93:
	ldr	x9, [x20]
	str	x9, [x21]
Lloh122:
	adrp	x9, _file_ase_mips16@GOTPAGE
Lloh123:
	ldr	x9, [x9, _file_ase_mips16@GOTPAGEOFF]
	ldp	w10, w11, [x20, #16]
Lloh124:
	str	w10, [x9]
Lloh125:
	adrp	x9, _file_ase_mips3d@GOTPAGE
Lloh126:
	ldr	x9, [x9, _file_ase_mips3d@GOTPAGEOFF]
	ldp	w10, w12, [x20, #8]
Lloh127:
	str	w10, [x9]
Lloh128:
	adrp	x9, _file_ase_mdmx@GOTPAGE
Lloh129:
	ldr	x9, [x9, _file_ase_mdmx@GOTPAGEOFF]
Lloh130:
	str	w12, [x9]
Lloh131:
	adrp	x9, _file_ase_smartmips@GOTPAGE
Lloh132:
	ldr	x9, [x9, _file_ase_smartmips@GOTPAGEOFF]
Lloh133:
	str	w11, [x9]
Lloh134:
	adrp	x9, _file_ase_dsp@GOTPAGE
Lloh135:
	ldr	x9, [x9, _file_ase_dsp@GOTPAGEOFF]
	ldp	w10, w11, [x20, #24]
Lloh136:
	adrp	x12, _file_ase_dspr2@GOTPAGE
Lloh137:
	ldr	x12, [x12, _file_ase_dspr2@GOTPAGEOFF]
Lloh138:
	str	w10, [x9]
Lloh139:
	str	w11, [x12]
Lloh140:
	adrp	x9, _file_ase_mt@GOTPAGE
Lloh141:
	ldr	x9, [x9, _file_ase_mt@GOTPAGEOFF]
Lloh142:
	str	w8, [x9]
	ldr	w8, [x22]
	ldr	w9, [x23]
	stp	w8, w9, [x20, #36]
Lloh143:
	adrp	x8, _mips_flag_mdebug@GOTPAGE
Lloh144:
	ldr	x8, [x8, _mips_flag_mdebug@GOTPAGEOFF]
	ldr	w9, [x8]
	tbz	w9, #31, LBB0_95
; %bb.94:
	str	wzr, [x8]
LBB0_95:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpAdd	Lloh26, Lloh27
	.loh AdrpAdd	Lloh28, Lloh29
	.loh AdrpAdd	Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpAdd	Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpAdd	Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpAdd	Lloh46, Lloh47
	.loh AdrpAdd	Lloh48, Lloh49
	.loh AdrpAdd	Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpAdd	Lloh54, Lloh55
	.loh AdrpAdd	Lloh56, Lloh57
	.loh AdrpAdd	Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotStr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpAdd	Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpAdd	Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpAdd	Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpAdd	Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpAdd	Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpAdd	Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpAdd	Lloh120, Lloh121
	.loh AdrpLdrGot	Lloh143, Lloh144
	.loh AdrpLdrGotStr	Lloh140, Lloh141, Lloh142
	.loh AdrpLdrGotStr	Lloh136, Lloh137, Lloh139
	.loh AdrpLdrGotStr	Lloh134, Lloh135, Lloh138
	.loh AdrpLdrGotStr	Lloh131, Lloh132, Lloh133
	.loh AdrpLdrGotStr	Lloh128, Lloh129, Lloh130
	.loh AdrpLdrGotStr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotStr	Lloh122, Lloh123, Lloh124
	.cfi_endproc
                                        ; -- End function
	.comm	_TARGET_OS,4,2                  ; @TARGET_OS
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"pe"

	.comm	_g_switch_seen,8,3              ; @g_switch_seen
	.comm	_g_switch_value,8,3             ; @g_switch_value
l_.str.1:                               ; @.str.1
	.asciz	"-G not supported in this configuration."

	.comm	_mips_abi,8,3                   ; @mips_abi
	.comm	_NO_ABI,8,3                     ; @NO_ABI
	.comm	_MIPS_DEFAULT_ABI,8,3           ; @MIPS_DEFAULT_ABI
	.comm	_mips_arch_string,8,3           ; @mips_arch_string
l_.str.2:                               ; @.str.2
	.asciz	"-march"

	.comm	_file_mips_isa,8,3              ; @file_mips_isa
	.comm	_ISA_UNKNOWN,8,3                ; @ISA_UNKNOWN
l_.str.3:                               ; @.str.3
	.asciz	"-%s conflicts with the other architecture options, which imply -%s"

l_.str.4:                               ; @.str.4
	.asciz	"default CPU"

	.comm	_MIPS_CPU_STRING_DEFAULT,8,3    ; @MIPS_CPU_STRING_DEFAULT
l_.str.5:                               ; @.str.5
	.asciz	"-march=%s is not compatible with the selected ABI"

	.comm	_mips_tune_string,8,3           ; @mips_tune_string
l_.str.6:                               ; @.str.6
	.asciz	"-mtune"

	.comm	_file_mips_gp32,4,2             ; @file_mips_gp32
	.comm	_mips_opts,48,3                 ; @mips_opts
l_.str.7:                               ; @.str.7
	.asciz	"-mgp64 used with a 32-bit processor"

l_.str.8:                               ; @.str.8
	.asciz	"-mgp32 used with a 64-bit ABI"

l_.str.9:                               ; @.str.9
	.asciz	"-mgp64 used with a 32-bit ABI"

	.comm	_file_mips_fp32,4,2             ; @file_mips_fp32
l_.str.10:                              ; @.str.10
	.asciz	"-mfp64 used with a 32-bit fpu"

l_.str.11:                              ; @.str.11
	.asciz	"-mfp64 used with a 32-bit ABI"

l_.str.12:                              ; @.str.12
	.asciz	"-mfp32 used with a 64-bit ABI"

	.comm	_O32_ABI,8,3                    ; @O32_ABI
	.comm	_mips_32bitmode,4,2             ; @mips_32bitmode
	.comm	_ISA_MIPS1,8,3                  ; @ISA_MIPS1
	.comm	_mips_trap,8,3                  ; @mips_trap
l_.str.13:                              ; @.str.13
	.asciz	"trap exception not supported at ISA 1"

	.comm	_file_mips_arch,4,2             ; @file_mips_arch
	.comm	_MIPS_CPU_ASE_MIPS3D,4,2        ; @MIPS_CPU_ASE_MIPS3D
l_.str.14:                              ; @.str.14
	.asciz	"-mfp32 used with -mips3d"

	.comm	_MIPS_CPU_ASE_MDMX,4,2          ; @MIPS_CPU_ASE_MDMX
l_.str.15:                              ; @.str.15
	.asciz	"-mfp32 used with -mdmx"

	.comm	_MIPS_CPU_ASE_SMARTMIPS,4,2     ; @MIPS_CPU_ASE_SMARTMIPS
	.comm	_ISA_SUPPORTS_SMARTMIPS,4,2     ; @ISA_SUPPORTS_SMARTMIPS
l_.str.16:                              ; @.str.16
	.asciz	"%s ISA does not support SmartMIPS"

	.comm	_MIPS_CPU_ASE_DSP,4,2           ; @MIPS_CPU_ASE_DSP
	.comm	_ISA_SUPPORTS_DSP_ASE,4,2       ; @ISA_SUPPORTS_DSP_ASE
l_.str.17:                              ; @.str.17
	.asciz	"%s ISA does not support DSP ASE"

	.comm	_MIPS_CPU_ASE_DSPR2,4,2         ; @MIPS_CPU_ASE_DSPR2
	.comm	_ISA_SUPPORTS_DSPR2_ASE,4,2     ; @ISA_SUPPORTS_DSPR2_ASE
l_.str.18:                              ; @.str.18
	.asciz	"%s ISA does not support DSP R2 ASE"

	.comm	_MIPS_CPU_ASE_MT,4,2            ; @MIPS_CPU_ASE_MT
	.comm	_ISA_SUPPORTS_MT_ASE,4,2        ; @ISA_SUPPORTS_MT_ASE
l_.str.19:                              ; @.str.19
	.asciz	"%s ISA does not support MT ASE"

	.comm	_file_ase_mips16,4,2            ; @file_ase_mips16
	.comm	_file_ase_mips3d,4,2            ; @file_ase_mips3d
	.comm	_file_ase_mdmx,4,2              ; @file_ase_mdmx
	.comm	_file_ase_smartmips,4,2         ; @file_ase_smartmips
	.comm	_file_ase_dsp,4,2               ; @file_ase_dsp
	.comm	_file_ase_dspr2,4,2             ; @file_ase_dspr2
	.comm	_file_ase_mt,4,2                ; @file_ase_mt
	.comm	_mips_flag_mdebug,4,2           ; @mips_flag_mdebug
	.comm	_OUTPUT_FLAVOR,8,3              ; @OUTPUT_FLAVOR
	.comm	_bfd_target_ecoff_flavour,8,3   ; @bfd_target_ecoff_flavour
.subsections_via_symbols
