	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ix86_expand_vector_init_one_nonzero
_ix86_expand_vector_init_one_nonzero:   ## @ix86_expand_vector_init_one_nonzero
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %ebx
	xorl	%eax, %eax
	leal	-128(%rbx), %esi
	cmpl	$9, %esi
	ja	LBB0_30
## %bb.1:
	movl	%r8d, %r13d
	movl	%ecx, %r12d
	movl	%edi, %r14d
	movl	$130, %r15d
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rsi,4), %rsi
	addq	%rcx, %rsi
	jmpq	*%rsi
LBB0_22:
	movl	$133, %r15d
	testl	%r14d, %r14d
	je	LBB0_30
LBB0_23:
	testl	%r13d, %r13d
	jne	LBB0_30
## %bb.24:
	movl	%edx, -44(%rbp)                 ## 4-byte Spill
	movq	_SImode@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	%ebx, %edi
	callq	_GET_MODE_INNER
	movl	%r13d, %edi
	movl	%eax, %esi
	movl	%r12d, %edx
	movl	$1, %ecx
	callq	_convert_modes
	movl	%eax, %r13d
	movl	%r15d, %edi
	callq	_gen_reg_rtx
	movl	%eax, %r12d
	movl	%r14d, %edi
	movl	%r15d, %esi
	movl	%eax, %edx
	movl	%r13d, %ecx
	xorl	%r8d, %r8d
	callq	_ix86_expand_vector_init_one_nonzero
	testl	%eax, %eax
	jne	LBB0_26
## %bb.25:
	xorl	%eax, %eax
	callq	_gcc_unreachable
LBB0_26:
	movl	%ebx, %edi
	movl	%r12d, %esi
	jmp	LBB0_27
LBB0_5:
	movl	%edx, -44(%rbp)                 ## 4-byte Spill
	movl	%edx, %edi
	callq	_REG_P
	testl	%eax, %eax
	je	LBB0_7
## %bb.6:
	movl	-44(%rbp), %r15d                ## 4-byte Reload
	movl	%r15d, %edi
	callq	_REGNO
	movq	_FIRST_PSEUDO_REGISTER@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jge	LBB0_8
LBB0_7:
	movl	%ebx, %edi
	callq	_gen_reg_rtx
	movl	%eax, %r15d
LBB0_8:
	movl	%ebx, %edi
	callq	_GET_MODE_INNER
	movl	%eax, %edi
	movl	%r12d, %esi
	callq	_force_reg
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_gen_rtx_VEC_DUPLICATE
	movl	%eax, %r14d
	movl	%ebx, %edi
	callq	_CONST0_RTX
	movq	_const1_rtx@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ebx, %edi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_gen_rtx_VEC_MERGE
	movq	_VOIDmode@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gen_rtx_SET
	movl	%eax, %edi
	callq	_emit_insn
	testl	%r13d, %r13d
	je	LBB0_20
## %bb.9:
	cmpl	$131, %ebx
	je	LBB0_13
## %bb.10:
	movq	_TARGET_SSE2@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	je	LBB0_13
## %bb.11:
	movl	$1, %edi
	callq	_GEN_INT
	movl	%eax, %r14d
	xorl	%edi, %edi
	cmpl	$1, %r13d
	setne	%dil
	callq	_GEN_INT
	movl	%r15d, %ebx
	movl	%eax, %r15d
	xorl	%edi, %edi
	cmpl	$2, %r13d
	setne	%dil
	callq	_GEN_INT
	movl	%eax, %r12d
	xorl	%edi, %edi
	cmpl	$3, %r13d
	setne	%dil
	callq	_GEN_INT
	movl	%ebx, %edi
	movl	%ebx, %esi
	movl	%r14d, %edx
	movl	%r15d, %ecx
	movl	%r12d, %r8d
	movl	%eax, %r9d
	callq	_gen_sse2_pshufd_1
	movl	%eax, %edi
	callq	_emit_insn
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	cmpl	%edi, %ebx
	je	LBB0_29
## %bb.12:
	movl	%ebx, %esi
	jmp	LBB0_28
LBB0_2:
	testl	%r14d, %r14d
	je	LBB0_30
LBB0_3:
	testl	%r13d, %r13d
	jne	LBB0_30
## %bb.4:
	movl	%ebx, %edi
	movl	%edx, %r15d
	callq	_GET_MODE_INNER
	movl	%eax, %edi
	movl	%r12d, %esi
	callq	_force_reg
	movl	%eax, %r14d
	movl	%ebx, %edi
	callq	_GET_MODE_INNER
	movl	%eax, %edi
	callq	_CONST0_RTX
	movl	%ebx, %edi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_gen_rtx_VEC_CONCAT
	movq	_VOIDmode@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gen_rtx_SET
	movl	%eax, %edi
	callq	_emit_insn
	jmp	LBB0_29
LBB0_20:
	movl	$1, %eax
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	cmpl	%edi, %r15d
	je	LBB0_30
## %bb.21:
	movl	%r15d, %esi
	jmp	LBB0_28
LBB0_13:
	cmpl	$131, %ebx
	je	LBB0_14
## %bb.15:
	movl	$131, %edi
	callq	_gen_reg_rtx
	movl	%eax, %r14d
	movl	$131, %edi
	movl	%r15d, %esi
	callq	_gen_lowpart
	movl	%r14d, %edi
	movl	%eax, %esi
	callq	_emit_move_insn
	jmp	LBB0_16
LBB0_14:
	movl	%r15d, %r14d
LBB0_16:
	movl	$1, %edi
	callq	_GEN_INT
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	xorl	%edi, %edi
	cmpl	$1, %r13d
	setne	%dil
	callq	_GEN_INT
	movl	%eax, %r15d
	xorl	%edi, %edi
	cmpl	$2, %r13d
	sete	%dil
	xorl	$5, %edi
	callq	_GEN_INT
	movl	%eax, %r12d
	xorl	%edi, %edi
	cmpl	$3, %r13d
	sete	%dil
	xorl	$5, %edi
	callq	_GEN_INT
	movl	%eax, (%rsp)
	movl	%r14d, %edi
	movl	%r14d, %esi
	movl	%r14d, %edx
	movl	-48(%rbp), %ecx                 ## 4-byte Reload
	movl	%r15d, %r8d
	movl	%r12d, %r9d
	callq	_gen_sse_shufps_1
	movl	%eax, %edi
	callq	_emit_insn
	cmpl	$131, %ebx
	je	LBB0_18
## %bb.17:
	movl	$130, %edi
	movl	%r14d, %esi
LBB0_27:
	callq	_gen_lowpart
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	movl	%eax, %esi
LBB0_28:
	callq	_emit_move_insn
LBB0_29:
	movl	$1, %eax
LBB0_30:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_18:
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	cmpl	%edi, %r14d
	je	LBB0_29
## %bb.19:
	movl	%r14d, %esi
	jmp	LBB0_28
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_22, LBB0_22-LJTI0_0
.set L0_0_set_23, LBB0_23-LJTI0_0
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_2, LBB0_2-LJTI0_0
.set L0_0_set_3, LBB0_3-LJTI0_0
LJTI0_0:
	.long	L0_0_set_22
	.long	L0_0_set_23
	.long	L0_0_set_5
	.long	L0_0_set_5
	.long	L0_0_set_22
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_3
	.long	L0_0_set_3
	.long	L0_0_set_23
	.end_data_region
                                        ## -- End function
	.comm	_VOIDmode,4,2                   ## @VOIDmode
	.comm	_FIRST_PSEUDO_REGISTER,4,2      ## @FIRST_PSEUDO_REGISTER
	.comm	_const1_rtx,4,2                 ## @const1_rtx
	.comm	_TARGET_SSE2,4,2                ## @TARGET_SSE2
	.comm	_SImode,4,2                     ## @SImode
	.no_dead_strip	_ix86_expand_vector_init_one_nonzero
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ix86_expand_vector_init_one_nonzero
_ix86_expand_vector_init_one_nonzero:   ; @ix86_expand_vector_init_one_nonzero
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	sub	w8, w1, #128
	cmp	w8, #9
	b.hi	LBB0_18
; %bb.1:
	mov	x22, x4
	mov	x24, x3
	mov	x19, x2
	mov	x20, x1
	mov	x21, x0
	mov	w23, #130
Lloh0:
	adrp	x9, lJTI0_0@PAGE
Lloh1:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_2
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_2:
	cbz	w21, LBB0_18
; %bb.3:
	mov	w23, #133
LBB0_4:
	cbnz	w22, LBB0_18
; %bb.5:
Lloh2:
	adrp	x8, _SImode@GOTPAGE
Lloh3:
	ldr	x8, [x8, _SImode@GOTPAGEOFF]
Lloh4:
	ldr	w22, [x8]
	mov	x0, x20
	bl	_GET_MODE_INNER
	mov	x1, x0
	mov	x0, x22
	mov	x2, x24
	mov	w3, #1
	bl	_convert_modes
	mov	x24, x0
	mov	x0, x23
	bl	_gen_reg_rtx
	mov	x22, x0
	mov	x0, x21
	mov	x1, x23
	mov	x2, x22
	mov	x3, x24
	mov	w4, #0
	bl	_ix86_expand_vector_init_one_nonzero
	cbnz	w0, LBB0_7
; %bb.6:
	bl	_gcc_unreachable
LBB0_7:
	mov	x0, x20
	mov	x1, x22
	b	LBB0_24
LBB0_8:
	mov	x0, x19
	bl	_REG_P
	cbz	w0, LBB0_10
; %bb.9:
	mov	x0, x19
	bl	_REGNO
Lloh5:
	adrp	x8, _FIRST_PSEUDO_REGISTER@GOTPAGE
Lloh6:
	ldr	x8, [x8, _FIRST_PSEUDO_REGISTER@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	mov	x21, x19
	cmp	w0, w8
	b.ge	LBB0_11
LBB0_10:
	mov	x0, x20
	bl	_gen_reg_rtx
	mov	x21, x0
LBB0_11:
	mov	x0, x20
	bl	_GET_MODE_INNER
	mov	x1, x24
	bl	_force_reg
	mov	x1, x0
	mov	x0, x20
	bl	_gen_rtx_VEC_DUPLICATE
	mov	x23, x0
	mov	x0, x20
	bl	_CONST0_RTX
	mov	x2, x0
Lloh8:
	adrp	x8, _const1_rtx@GOTPAGE
Lloh9:
	ldr	x8, [x8, _const1_rtx@GOTPAGEOFF]
Lloh10:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x23
	bl	_gen_rtx_VEC_MERGE
	mov	x2, x0
Lloh11:
	adrp	x8, _VOIDmode@GOTPAGE
Lloh12:
	ldr	x8, [x8, _VOIDmode@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
	mov	x1, x21
	bl	_gen_rtx_SET
	bl	_emit_insn
	cbz	w22, LBB0_25
; %bb.12:
	cmp	w20, #131
	b.eq	LBB0_20
; %bb.13:
Lloh14:
	adrp	x8, _TARGET_SSE2@GOTPAGE
Lloh15:
	ldr	x8, [x8, _TARGET_SSE2@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
	cbz	w8, LBB0_20
; %bb.14:
	mov	w23, #1
	mov	w0, #1
	bl	_GEN_INT
	mov	x20, x0
	cmp	w22, #1
	cset	w0, ne
	bl	_GEN_INT
	mov	x24, x0
	cmp	w22, #2
	cset	w0, ne
	bl	_GEN_INT
	mov	x25, x0
	cmp	w22, #3
	cset	w0, ne
	bl	_GEN_INT
	mov	x5, x0
	mov	x0, x21
	mov	x1, x21
	mov	x2, x20
	mov	x3, x24
	mov	x4, x25
	bl	_gen_sse2_pshufd_1
	bl	_emit_insn
	cmp	w21, w19
	b.ne	LBB0_26
	b	LBB0_29
LBB0_15:
	mov	w23, #0
	cbz	w21, LBB0_29
; %bb.16:
	cbz	w22, LBB0_19
	b	LBB0_29
LBB0_17:
	cbz	w22, LBB0_19
LBB0_18:
	mov	w23, #0
	b	LBB0_29
LBB0_19:
	mov	x0, x20
	bl	_GET_MODE_INNER
	mov	x1, x24
	bl	_force_reg
	mov	x21, x0
	mov	x0, x20
	bl	_GET_MODE_INNER
	bl	_CONST0_RTX
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gen_rtx_VEC_CONCAT
	mov	x2, x0
Lloh17:
	adrp	x8, _VOIDmode@GOTPAGE
Lloh18:
	ldr	x8, [x8, _VOIDmode@GOTPAGEOFF]
Lloh19:
	ldr	w0, [x8]
	mov	x1, x19
	bl	_gen_rtx_SET
	bl	_emit_insn
	b	LBB0_28
LBB0_20:
	cmp	w20, #131
	b.eq	LBB0_22
; %bb.21:
	mov	w0, #131
	bl	_gen_reg_rtx
	mov	x23, x0
	mov	w0, #131
	mov	x1, x21
	bl	_gen_lowpart
	mov	x1, x0
	mov	x0, x23
	bl	_emit_move_insn
	mov	x21, x23
LBB0_22:
	mov	w0, #1
	bl	_GEN_INT
	mov	x23, x0
	cmp	w22, #1
	cset	w0, ne
	bl	_GEN_INT
	mov	x24, x0
	cmp	w22, #2
	mov	w26, #4
	cinc	w0, w26, ne
	bl	_GEN_INT
	mov	x25, x0
	cmp	w22, #3
	cinc	w0, w26, ne
	bl	_GEN_INT
	mov	x6, x0
	mov	x0, x21
	mov	x1, x21
	mov	x2, x21
	mov	x3, x23
	mov	x4, x24
	mov	x5, x25
	bl	_gen_sse_shufps_1
	bl	_emit_insn
	cmp	w20, #131
	b.eq	LBB0_25
; %bb.23:
	mov	w0, #130
	mov	x1, x21
LBB0_24:
	bl	_gen_lowpart
	mov	x1, x0
	mov	x0, x19
	b	LBB0_27
LBB0_25:
	cmp	w21, w19
	b.eq	LBB0_28
LBB0_26:
	mov	x0, x19
	mov	x1, x21
LBB0_27:
	bl	_emit_move_insn
LBB0_28:
	mov	w23, #1
LBB0_29:
	mov	x0, x23
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_8-LBB0_2)>>2
	.byte	(LBB0_8-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_15-LBB0_2)>>2
	.byte	(LBB0_15-LBB0_2)>>2
	.byte	(LBB0_17-LBB0_2)>>2
	.byte	(LBB0_17-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
                                        ; -- End function
	.comm	_VOIDmode,4,2                   ; @VOIDmode
	.comm	_FIRST_PSEUDO_REGISTER,4,2      ; @FIRST_PSEUDO_REGISTER
	.comm	_const1_rtx,4,2                 ; @const1_rtx
	.comm	_TARGET_SSE2,4,2                ; @TARGET_SSE2
	.comm	_SImode,4,2                     ; @SImode
	.no_dead_strip	_ix86_expand_vector_init_one_nonzero
.subsections_via_symbols
