	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function davinci_hw_dit_param
_davinci_hw_dit_param:                  ## @davinci_hw_dit_param
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_DAVINCI_MCASP_PDIR_REG@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r14), %rdi
	movq	_AFSX@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_mcasp_set_bits
	movq	_DAVINCI_MCASP_TXMASK_REG@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r14), %rdi
	movl	$16777215, %esi                 ## imm = 0xFFFFFF
	callq	_mcasp_set_reg
	movq	_DAVINCI_MCASP_TXFMT_REG@GOTPCREL(%rip), %rax
	movq	(%rax), %r15
	addq	(%r14), %r15
	movl	$6, %edi
	callq	_TXROT
	movl	%eax, %ebx
	movl	$15, %edi
	callq	_TXSSZ
	orl	%eax, %ebx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_mcasp_set_bits
	movq	_DAVINCI_MCASP_TXFMCTL_REG@GOTPCREL(%rip), %rax
	movq	(%rax), %r15
	addq	(%r14), %r15
	movq	_AFSXE@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$384, %edi                      ## imm = 0x180
	callq	_FSXMOD
	orl	%eax, %ebx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_mcasp_set_reg
	movq	_DAVINCI_MCASP_TXTDM_REG@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r14), %rdi
	movl	$-1, %esi
	callq	_mcasp_set_reg
	movq	_DAVINCI_MCASP_ACLKXCTL_REG@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r14), %rdi
	movq	_ACLKXE@GOTPCREL(%rip), %rax
	movq	_TX_ASYNC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	callq	_mcasp_set_bits
	movq	_DAVINCI_MCASP_XEVTCTL_REG@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r14), %rdi
	movq	_TXDATADMADIS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_mcasp_clr_bits
	movq	_DAVINCI_MCASP_AHCLKXCTL_REG@GOTPCREL(%rip), %rax
	movq	(%rax), %rbx
	addq	(%r14), %rbx
	movl	$3, %edi
	callq	_AHCLKXDIV
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_mcasp_set_bits
	movq	_DAVINCI_MCASP_TXDITCTL_REG@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r14), %rdi
	movq	_DITEN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_mcasp_set_bits                 ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_DAVINCI_MCASP_PDIR_REG,8,3     ## @DAVINCI_MCASP_PDIR_REG
	.comm	_AFSX,4,2                       ## @AFSX
	.comm	_DAVINCI_MCASP_TXMASK_REG,8,3   ## @DAVINCI_MCASP_TXMASK_REG
	.comm	_DAVINCI_MCASP_TXFMT_REG,8,3    ## @DAVINCI_MCASP_TXFMT_REG
	.comm	_DAVINCI_MCASP_TXFMCTL_REG,8,3  ## @DAVINCI_MCASP_TXFMCTL_REG
	.comm	_AFSXE,4,2                      ## @AFSXE
	.comm	_DAVINCI_MCASP_TXTDM_REG,8,3    ## @DAVINCI_MCASP_TXTDM_REG
	.comm	_DAVINCI_MCASP_ACLKXCTL_REG,8,3 ## @DAVINCI_MCASP_ACLKXCTL_REG
	.comm	_ACLKXE,4,2                     ## @ACLKXE
	.comm	_TX_ASYNC,4,2                   ## @TX_ASYNC
	.comm	_DAVINCI_MCASP_XEVTCTL_REG,8,3  ## @DAVINCI_MCASP_XEVTCTL_REG
	.comm	_TXDATADMADIS,4,2               ## @TXDATADMADIS
	.comm	_DAVINCI_MCASP_AHCLKXCTL_REG,8,3 ## @DAVINCI_MCASP_AHCLKXCTL_REG
	.comm	_DAVINCI_MCASP_TXDITCTL_REG,8,3 ## @DAVINCI_MCASP_TXDITCTL_REG
	.comm	_DITEN,4,2                      ## @DITEN
	.no_dead_strip	_davinci_hw_dit_param
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function davinci_hw_dit_param
_davinci_hw_dit_param:                  ; @davinci_hw_dit_param
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, _DAVINCI_MCASP_PDIR_REG@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DAVINCI_MCASP_PDIR_REG@GOTPAGEOFF]
	ldr	x9, [x0]
Lloh2:
	ldr	x8, [x8]
	add	x0, x8, x9
Lloh3:
	adrp	x8, _AFSX@GOTPAGE
Lloh4:
	ldr	x8, [x8, _AFSX@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	bl	_mcasp_set_bits
	ldr	x8, [x19]
Lloh6:
	adrp	x9, _DAVINCI_MCASP_TXMASK_REG@GOTPAGE
Lloh7:
	ldr	x9, [x9, _DAVINCI_MCASP_TXMASK_REG@GOTPAGEOFF]
Lloh8:
	ldr	x9, [x9]
	add	x0, x9, x8
	mov	w1, #16777215
	bl	_mcasp_set_reg
	ldr	x8, [x19]
Lloh9:
	adrp	x9, _DAVINCI_MCASP_TXFMT_REG@GOTPAGE
Lloh10:
	ldr	x9, [x9, _DAVINCI_MCASP_TXFMT_REG@GOTPAGEOFF]
Lloh11:
	ldr	x9, [x9]
	add	x20, x9, x8
	mov	w0, #6
	bl	_TXROT
	mov	x21, x0
	mov	w0, #15
	bl	_TXSSZ
	orr	w1, w0, w21
	mov	x0, x20
	bl	_mcasp_set_bits
Lloh12:
	adrp	x8, _DAVINCI_MCASP_TXFMCTL_REG@GOTPAGE
Lloh13:
	ldr	x8, [x8, _DAVINCI_MCASP_TXFMCTL_REG@GOTPAGEOFF]
	ldr	x9, [x19]
Lloh14:
	ldr	x8, [x8]
	add	x20, x8, x9
Lloh15:
	adrp	x8, _AFSXE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _AFSXE@GOTPAGEOFF]
Lloh17:
	ldr	w21, [x8]
	mov	w0, #384
	bl	_FSXMOD
	orr	w1, w0, w21
	mov	x0, x20
	bl	_mcasp_set_reg
	ldr	x8, [x19]
Lloh18:
	adrp	x9, _DAVINCI_MCASP_TXTDM_REG@GOTPAGE
Lloh19:
	ldr	x9, [x9, _DAVINCI_MCASP_TXTDM_REG@GOTPAGEOFF]
Lloh20:
	ldr	x9, [x9]
	add	x0, x9, x8
	mov	w1, #-1
	bl	_mcasp_set_reg
	ldr	x8, [x19]
Lloh21:
	adrp	x9, _DAVINCI_MCASP_ACLKXCTL_REG@GOTPAGE
Lloh22:
	ldr	x9, [x9, _DAVINCI_MCASP_ACLKXCTL_REG@GOTPAGEOFF]
Lloh23:
	ldr	x9, [x9]
Lloh24:
	adrp	x10, _ACLKXE@GOTPAGE
Lloh25:
	ldr	x10, [x10, _ACLKXE@GOTPAGEOFF]
	add	x0, x9, x8
Lloh26:
	ldr	w8, [x10]
Lloh27:
	adrp	x9, _TX_ASYNC@GOTPAGE
Lloh28:
	ldr	x9, [x9, _TX_ASYNC@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	orr	w1, w9, w8
	bl	_mcasp_set_bits
Lloh30:
	adrp	x8, _DAVINCI_MCASP_XEVTCTL_REG@GOTPAGE
Lloh31:
	ldr	x8, [x8, _DAVINCI_MCASP_XEVTCTL_REG@GOTPAGEOFF]
	ldr	x9, [x19]
Lloh32:
	ldr	x8, [x8]
	add	x0, x8, x9
Lloh33:
	adrp	x8, _TXDATADMADIS@GOTPAGE
Lloh34:
	ldr	x8, [x8, _TXDATADMADIS@GOTPAGEOFF]
Lloh35:
	ldr	w1, [x8]
	bl	_mcasp_clr_bits
	ldr	x8, [x19]
Lloh36:
	adrp	x9, _DAVINCI_MCASP_AHCLKXCTL_REG@GOTPAGE
Lloh37:
	ldr	x9, [x9, _DAVINCI_MCASP_AHCLKXCTL_REG@GOTPAGEOFF]
Lloh38:
	ldr	x9, [x9]
	add	x20, x9, x8
	mov	w0, #3
	bl	_AHCLKXDIV
	mov	x1, x0
	mov	x0, x20
	bl	_mcasp_set_bits
	ldr	x8, [x19]
Lloh39:
	adrp	x9, _DAVINCI_MCASP_TXDITCTL_REG@GOTPAGE
Lloh40:
	ldr	x9, [x9, _DAVINCI_MCASP_TXDITCTL_REG@GOTPAGEOFF]
Lloh41:
	ldr	x9, [x9]
	add	x0, x9, x8
Lloh42:
	adrp	x8, _DITEN@GOTPAGE
Lloh43:
	ldr	x8, [x8, _DITEN@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x8]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_mcasp_set_bits
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_DAVINCI_MCASP_PDIR_REG,8,3     ; @DAVINCI_MCASP_PDIR_REG
	.comm	_AFSX,4,2                       ; @AFSX
	.comm	_DAVINCI_MCASP_TXMASK_REG,8,3   ; @DAVINCI_MCASP_TXMASK_REG
	.comm	_DAVINCI_MCASP_TXFMT_REG,8,3    ; @DAVINCI_MCASP_TXFMT_REG
	.comm	_DAVINCI_MCASP_TXFMCTL_REG,8,3  ; @DAVINCI_MCASP_TXFMCTL_REG
	.comm	_AFSXE,4,2                      ; @AFSXE
	.comm	_DAVINCI_MCASP_TXTDM_REG,8,3    ; @DAVINCI_MCASP_TXTDM_REG
	.comm	_DAVINCI_MCASP_ACLKXCTL_REG,8,3 ; @DAVINCI_MCASP_ACLKXCTL_REG
	.comm	_ACLKXE,4,2                     ; @ACLKXE
	.comm	_TX_ASYNC,4,2                   ; @TX_ASYNC
	.comm	_DAVINCI_MCASP_XEVTCTL_REG,8,3  ; @DAVINCI_MCASP_XEVTCTL_REG
	.comm	_TXDATADMADIS,4,2               ; @TXDATADMADIS
	.comm	_DAVINCI_MCASP_AHCLKXCTL_REG,8,3 ; @DAVINCI_MCASP_AHCLKXCTL_REG
	.comm	_DAVINCI_MCASP_TXDITCTL_REG,8,3 ; @DAVINCI_MCASP_TXDITCTL_REG
	.comm	_DITEN,4,2                      ; @DITEN
	.no_dead_strip	_davinci_hw_dit_param
.subsections_via_symbols
