	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_md_show_usage                  ## -- Begin function md_show_usage
	.p2align	4, 0x90
_md_show_usage:                         ## @md_show_usage
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	leaq	L_.str(%rip), %rdi
	callq	__
	movq	%r12, %rdi
	movq	%rax, %rsi
	callq	_fprintf
	leaq	L_.str.1(%rip), %rdi
	callq	__
	movq	%r12, %rdi
	movq	%rax, %rsi
	callq	_fprintf
	movl	$1, -44(%rbp)
	movq	_mips_cpu_info_table@GOTPCREL(%rip), %r15
	movq	(%r15), %rax
	movq	(%rax), %rsi
	testq	%rsi, %rsi
	je	LBB0_3
## %bb.1:
	movl	$8, %ebx
	leaq	-48(%rbp), %r14
	leaq	-44(%rbp), %r13
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r12, %rdi
	movq	%r14, %rdx
	movq	%r13, %rcx
	callq	_show
	movq	(%r15), %rax
	movq	(%rax,%rbx), %rsi
	addq	$8, %rbx
	testq	%rsi, %rsi
	jne	LBB0_2
LBB0_3:
	leaq	L_.str.2(%rip), %rsi
	leaq	-48(%rbp), %r14
	leaq	-44(%rbp), %r15
	movq	%r12, %rdi
	movq	%r14, %rdx
	movq	%r15, %rcx
	callq	_show
	movl	$10, %edi
	movq	%r12, %rsi
	callq	_fputc
	leaq	L_.str.3(%rip), %rdi
	callq	__
	movq	%r12, %rdi
	movq	%rax, %rsi
	callq	_fprintf
	movl	$1, -44(%rbp)
	leaq	L_.str.4(%rip), %rsi
	movq	%r12, %rdi
	movq	%r14, %rdx
	movq	%r15, %rcx
	callq	_show
	leaq	L_.str.5(%rip), %rsi
	movq	%r12, %rdi
	movq	%r14, %rdx
	movq	%r15, %rcx
	callq	_show
	leaq	L_.str.6(%rip), %rsi
	movq	%r12, %rdi
	movq	%r14, %rdx
	movq	%r15, %rcx
	callq	_show
	leaq	L_.str.7(%rip), %rsi
	movq	%r12, %rdi
	movq	%r14, %rdx
	movq	%r15, %rcx
	callq	_show
	movl	$10, %edi
	movq	%r12, %rsi
	callq	_fputc
	leaq	L_.str.8(%rip), %rdi
	callq	__
	movq	%r12, %rdi
	movq	%rax, %rsi
	callq	_fprintf
	leaq	L_.str.9(%rip), %rdi
	callq	__
	movq	%r12, %rdi
	movq	%rax, %rsi
	callq	_fprintf
	leaq	L_.str.10(%rip), %rdi
	callq	__
	movq	%r12, %rdi
	movq	%rax, %rsi
	callq	_fprintf
	leaq	L_.str.11(%rip), %rdi
	callq	__
	movq	%r12, %rdi
	movq	%rax, %rsi
	callq	_fprintf
	leaq	L_.str.12(%rip), %rdi
	callq	__
	movq	%r12, %rdi
	movq	%rax, %rsi
	callq	_fprintf
	leaq	L_.str.13(%rip), %rdi
	callq	__
	movq	%r12, %rdi
	movq	%rax, %rsi
	callq	_fprintf
	leaq	L_.str.14(%rip), %rdi
	callq	__
	movq	%r12, %rdi
	movq	%rax, %rsi
	callq	_fprintf
	leaq	L_.str.15(%rip), %rdi
	callq	__
	movq	%r12, %rdi
	movq	%rax, %rsi
	callq	_fprintf
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"MIPS options:\n-EB\t\t\tgenerate big endian output\n-EL\t\t\tgenerate little endian output\n-g, -g2\t\t\tdo not remove unneeded NOPs or swap branches\n-G NUM\t\t\tallow referencing objects up to NUM bytes\n\t\t\timplicitly with the gp register [default 8]\n"

L_.str.1:                               ## @.str.1
	.asciz	"-mips1\t\t\tgenerate MIPS ISA I instructions\n-mips2\t\t\tgenerate MIPS ISA II instructions\n-mips3\t\t\tgenerate MIPS ISA III instructions\n-mips4\t\t\tgenerate MIPS ISA IV instructions\n-mips5                  generate MIPS ISA V instructions\n-mips32                 generate MIPS32 ISA instructions\n-mips32r2               generate MIPS32 release 2 ISA instructions\n-mips64                 generate MIPS64 ISA instructions\n-mips64r2               generate MIPS64 release 2 ISA instructions\n-march=CPU/-mtune=CPU\tgenerate code/schedule for CPU, where CPU is one of:\n"

	.comm	_mips_cpu_info_table,8,3        ## @mips_cpu_info_table
L_.str.2:                               ## @.str.2
	.asciz	"from-abi"

L_.str.3:                               ## @.str.3
	.asciz	"-mCPU\t\t\tequivalent to -march=CPU -mtune=CPU. Deprecated.\n-no-mCPU\t\tdon't generate code specific to CPU.\n\t\t\tFor -mCPU and -no-mCPU, CPU must be one of:\n"

L_.str.4:                               ## @.str.4
	.asciz	"3900"

L_.str.5:                               ## @.str.5
	.asciz	"4010"

L_.str.6:                               ## @.str.6
	.asciz	"4100"

L_.str.7:                               ## @.str.7
	.asciz	"4650"

L_.str.8:                               ## @.str.8
	.asciz	"-mips16\t\t\tgenerate mips16 instructions\n-no-mips16\t\tdo not generate mips16 instructions\n"

L_.str.9:                               ## @.str.9
	.asciz	"-msmartmips\t\tgenerate smartmips instructions\n-mno-smartmips\t\tdo not generate smartmips instructions\n"

L_.str.10:                              ## @.str.10
	.asciz	"-mdsp\t\t\tgenerate DSP instructions\n-mno-dsp\t\tdo not generate DSP instructions\n"

L_.str.11:                              ## @.str.11
	.asciz	"-mdspr2\t\t\tgenerate DSP R2 instructions\n-mno-dspr2\t\tdo not generate DSP R2 instructions\n"

L_.str.12:                              ## @.str.12
	.asciz	"-mmt\t\t\tgenerate MT instructions\n-mno-mt\t\t\tdo not generate MT instructions\n"

L_.str.13:                              ## @.str.13
	.asciz	"-mfix-vr4120\t\twork around certain VR4120 errata\n-mfix-vr4130\t\twork around VR4130 mflo/mfhi errata\n-mgp32\t\t\tuse 32-bit GPRs, regardless of the chosen ISA\n-mfp32\t\t\tuse 32-bit FPRs, regardless of the chosen ISA\n-msym32\t\t\tassume all symbols have 32-bit values\n-O0\t\t\tremove unneeded NOPs, do not swap branches\n-O\t\t\tremove unneeded NOPs and swap branches\n--[no-]construct-floats [dis]allow floating point values to be constructed\n--trap, --no-break\ttrap exception on div by 0 and mult overflow\n--break, --no-trap\tbreak exception on div by 0 and mult overflow\n"

L_.str.14:                              ## @.str.14
	.asciz	"-mocteon-unsupported    error on unsupported Octeon instructions\n-mno-octeon-unsupported do not error on unsupported Octeon instructions\n"

L_.str.15:                              ## @.str.15
	.asciz	"-mocteon-useun    generate Octeon unaligned load/store instructions\n-mno-octeon-useun generate MIPS unaligned load/store instructions\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_md_show_usage                  ; -- Begin function md_show_usage
	.p2align	2
_md_show_usage:                         ; @md_show_usage
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	__
	mov	x1, x0
	mov	x0, x19
	bl	_fprintf
Lloh2:
	adrp	x0, l_.str.1@PAGE
Lloh3:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	__
	mov	x1, x0
	mov	x0, x19
	bl	_fprintf
	mov	w20, #1
	str	w20, [sp, #8]
Lloh4:
	adrp	x21, _mips_cpu_info_table@GOTPAGE
Lloh5:
	ldr	x21, [x21, _mips_cpu_info_table@GOTPAGEOFF]
	ldr	x8, [x21]
	ldr	x1, [x8]
	cbz	x1, LBB0_3
; %bb.1:
	mov	w22, #8
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	add	x2, sp, #12
	add	x3, sp, #8
	mov	x0, x19
	bl	_show
	ldr	x8, [x21]
	ldr	x1, [x8, x22]
	add	x22, x22, #8
	cbnz	x1, LBB0_2
LBB0_3:
Lloh6:
	adrp	x1, l_.str.2@PAGE
Lloh7:
	add	x1, x1, l_.str.2@PAGEOFF
	add	x2, sp, #12
	add	x3, sp, #8
	mov	x0, x19
	bl	_show
	mov	w0, #10
	mov	x1, x19
	bl	_fputc
Lloh8:
	adrp	x0, l_.str.3@PAGE
Lloh9:
	add	x0, x0, l_.str.3@PAGEOFF
	bl	__
	mov	x1, x0
	mov	x0, x19
	bl	_fprintf
	str	w20, [sp, #8]
Lloh10:
	adrp	x1, l_.str.4@PAGE
Lloh11:
	add	x1, x1, l_.str.4@PAGEOFF
	add	x2, sp, #12
	add	x3, sp, #8
	mov	x0, x19
	bl	_show
Lloh12:
	adrp	x1, l_.str.5@PAGE
Lloh13:
	add	x1, x1, l_.str.5@PAGEOFF
	add	x2, sp, #12
	add	x3, sp, #8
	mov	x0, x19
	bl	_show
Lloh14:
	adrp	x1, l_.str.6@PAGE
Lloh15:
	add	x1, x1, l_.str.6@PAGEOFF
	add	x2, sp, #12
	add	x3, sp, #8
	mov	x0, x19
	bl	_show
Lloh16:
	adrp	x1, l_.str.7@PAGE
Lloh17:
	add	x1, x1, l_.str.7@PAGEOFF
	add	x2, sp, #12
	add	x3, sp, #8
	mov	x0, x19
	bl	_show
	mov	w0, #10
	mov	x1, x19
	bl	_fputc
Lloh18:
	adrp	x0, l_.str.8@PAGE
Lloh19:
	add	x0, x0, l_.str.8@PAGEOFF
	bl	__
	mov	x1, x0
	mov	x0, x19
	bl	_fprintf
Lloh20:
	adrp	x0, l_.str.9@PAGE
Lloh21:
	add	x0, x0, l_.str.9@PAGEOFF
	bl	__
	mov	x1, x0
	mov	x0, x19
	bl	_fprintf
Lloh22:
	adrp	x0, l_.str.10@PAGE
Lloh23:
	add	x0, x0, l_.str.10@PAGEOFF
	bl	__
	mov	x1, x0
	mov	x0, x19
	bl	_fprintf
Lloh24:
	adrp	x0, l_.str.11@PAGE
Lloh25:
	add	x0, x0, l_.str.11@PAGEOFF
	bl	__
	mov	x1, x0
	mov	x0, x19
	bl	_fprintf
Lloh26:
	adrp	x0, l_.str.12@PAGE
Lloh27:
	add	x0, x0, l_.str.12@PAGEOFF
	bl	__
	mov	x1, x0
	mov	x0, x19
	bl	_fprintf
Lloh28:
	adrp	x0, l_.str.13@PAGE
Lloh29:
	add	x0, x0, l_.str.13@PAGEOFF
	bl	__
	mov	x1, x0
	mov	x0, x19
	bl	_fprintf
Lloh30:
	adrp	x0, l_.str.14@PAGE
Lloh31:
	add	x0, x0, l_.str.14@PAGEOFF
	bl	__
	mov	x1, x0
	mov	x0, x19
	bl	_fprintf
Lloh32:
	adrp	x0, l_.str.15@PAGE
Lloh33:
	add	x0, x0, l_.str.15@PAGEOFF
	bl	__
	mov	x1, x0
	mov	x0, x19
	bl	_fprintf
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh32, Lloh33
	.loh AdrpAdd	Lloh30, Lloh31
	.loh AdrpAdd	Lloh28, Lloh29
	.loh AdrpAdd	Lloh26, Lloh27
	.loh AdrpAdd	Lloh24, Lloh25
	.loh AdrpAdd	Lloh22, Lloh23
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpAdd	Lloh18, Lloh19
	.loh AdrpAdd	Lloh16, Lloh17
	.loh AdrpAdd	Lloh14, Lloh15
	.loh AdrpAdd	Lloh12, Lloh13
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh6, Lloh7
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"MIPS options:\n-EB\t\t\tgenerate big endian output\n-EL\t\t\tgenerate little endian output\n-g, -g2\t\t\tdo not remove unneeded NOPs or swap branches\n-G NUM\t\t\tallow referencing objects up to NUM bytes\n\t\t\timplicitly with the gp register [default 8]\n"

l_.str.1:                               ; @.str.1
	.asciz	"-mips1\t\t\tgenerate MIPS ISA I instructions\n-mips2\t\t\tgenerate MIPS ISA II instructions\n-mips3\t\t\tgenerate MIPS ISA III instructions\n-mips4\t\t\tgenerate MIPS ISA IV instructions\n-mips5                  generate MIPS ISA V instructions\n-mips32                 generate MIPS32 ISA instructions\n-mips32r2               generate MIPS32 release 2 ISA instructions\n-mips64                 generate MIPS64 ISA instructions\n-mips64r2               generate MIPS64 release 2 ISA instructions\n-march=CPU/-mtune=CPU\tgenerate code/schedule for CPU, where CPU is one of:\n"

	.comm	_mips_cpu_info_table,8,3        ; @mips_cpu_info_table
l_.str.2:                               ; @.str.2
	.asciz	"from-abi"

l_.str.3:                               ; @.str.3
	.asciz	"-mCPU\t\t\tequivalent to -march=CPU -mtune=CPU. Deprecated.\n-no-mCPU\t\tdon't generate code specific to CPU.\n\t\t\tFor -mCPU and -no-mCPU, CPU must be one of:\n"

l_.str.4:                               ; @.str.4
	.asciz	"3900"

l_.str.5:                               ; @.str.5
	.asciz	"4010"

l_.str.6:                               ; @.str.6
	.asciz	"4100"

l_.str.7:                               ; @.str.7
	.asciz	"4650"

l_.str.8:                               ; @.str.8
	.asciz	"-mips16\t\t\tgenerate mips16 instructions\n-no-mips16\t\tdo not generate mips16 instructions\n"

l_.str.9:                               ; @.str.9
	.asciz	"-msmartmips\t\tgenerate smartmips instructions\n-mno-smartmips\t\tdo not generate smartmips instructions\n"

l_.str.10:                              ; @.str.10
	.asciz	"-mdsp\t\t\tgenerate DSP instructions\n-mno-dsp\t\tdo not generate DSP instructions\n"

l_.str.11:                              ; @.str.11
	.asciz	"-mdspr2\t\t\tgenerate DSP R2 instructions\n-mno-dspr2\t\tdo not generate DSP R2 instructions\n"

l_.str.12:                              ; @.str.12
	.asciz	"-mmt\t\t\tgenerate MT instructions\n-mno-mt\t\t\tdo not generate MT instructions\n"

l_.str.13:                              ; @.str.13
	.asciz	"-mfix-vr4120\t\twork around certain VR4120 errata\n-mfix-vr4130\t\twork around VR4130 mflo/mfhi errata\n-mgp32\t\t\tuse 32-bit GPRs, regardless of the chosen ISA\n-mfp32\t\t\tuse 32-bit FPRs, regardless of the chosen ISA\n-msym32\t\t\tassume all symbols have 32-bit values\n-O0\t\t\tremove unneeded NOPs, do not swap branches\n-O\t\t\tremove unneeded NOPs and swap branches\n--[no-]construct-floats [dis]allow floating point values to be constructed\n--trap, --no-break\ttrap exception on div by 0 and mult overflow\n--break, --no-trap\tbreak exception on div by 0 and mult overflow\n"

l_.str.14:                              ; @.str.14
	.asciz	"-mocteon-unsupported    error on unsupported Octeon instructions\n-mno-octeon-unsupported do not error on unsupported Octeon instructions\n"

l_.str.15:                              ; @.str.15
	.asciz	"-mocteon-useun    generate Octeon unaligned load/store instructions\n-mno-octeon-useun generate MIPS unaligned load/store instructions\n"

.subsections_via_symbols
