	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ca0132_set_dsp_msr
_ca0132_set_dsp_msr:                    ## @ca0132_set_dsp_msr
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movl	%esi, %r14d
	movq	%rdi, %rbx
	movq	_CONTROL_FLAG_DSP_96KHZ@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r14d, %edx
	callq	_chipio_set_control_flag
	movq	_CONTROL_FLAG_DAC_96KHZ@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	%r14d, %edx
	callq	_chipio_set_control_flag
	movq	_CONTROL_FLAG_SRC_RATE_96KHZ@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	%r14d, %edx
	callq	_chipio_set_control_flag
	movq	_CONTROL_FLAG_SRC_CLOCK_196MHZ@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	%r14d, %edx
	callq	_chipio_set_control_flag
	movq	_CONTROL_FLAG_ADC_B_96KHZ@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	%r14d, %edx
	callq	_chipio_set_control_flag
	movq	_CONTROL_FLAG_ADC_C_96KHZ@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	%r14d, %edx
	callq	_chipio_set_control_flag
	movq	_MEM_CONNID_MICIN1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SR_96_000@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	movq	%rbx, %rdi
	callq	_chipio_set_conn_rate
	movq	_MEM_CONNID_MICOUT1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r14), %edx
	movq	%rbx, %rdi
	callq	_chipio_set_conn_rate
	movq	_MEM_CONNID_WUH@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SR_48_000@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_chipio_set_conn_rate           ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_CONTROL_FLAG_DSP_96KHZ,4,2     ## @CONTROL_FLAG_DSP_96KHZ
	.comm	_CONTROL_FLAG_DAC_96KHZ,4,2     ## @CONTROL_FLAG_DAC_96KHZ
	.comm	_CONTROL_FLAG_SRC_RATE_96KHZ,4,2 ## @CONTROL_FLAG_SRC_RATE_96KHZ
	.comm	_CONTROL_FLAG_SRC_CLOCK_196MHZ,4,2 ## @CONTROL_FLAG_SRC_CLOCK_196MHZ
	.comm	_CONTROL_FLAG_ADC_B_96KHZ,4,2   ## @CONTROL_FLAG_ADC_B_96KHZ
	.comm	_CONTROL_FLAG_ADC_C_96KHZ,4,2   ## @CONTROL_FLAG_ADC_C_96KHZ
	.comm	_MEM_CONNID_MICIN1,4,2          ## @MEM_CONNID_MICIN1
	.comm	_SR_96_000,4,2                  ## @SR_96_000
	.comm	_MEM_CONNID_MICOUT1,4,2         ## @MEM_CONNID_MICOUT1
	.comm	_MEM_CONNID_WUH,4,2             ## @MEM_CONNID_WUH
	.comm	_SR_48_000,4,2                  ## @SR_48_000
	.no_dead_strip	_ca0132_set_dsp_msr
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ca0132_set_dsp_msr
_ca0132_set_dsp_msr:                    ; @ca0132_set_dsp_msr
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x8, _CONTROL_FLAG_DSP_96KHZ@GOTPAGE
Lloh1:
	ldr	x8, [x8, _CONTROL_FLAG_DSP_96KHZ@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x2, x20
	bl	_chipio_set_control_flag
Lloh3:
	adrp	x8, _CONTROL_FLAG_DAC_96KHZ@GOTPAGE
Lloh4:
	ldr	x8, [x8, _CONTROL_FLAG_DAC_96KHZ@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_chipio_set_control_flag
Lloh6:
	adrp	x8, _CONTROL_FLAG_SRC_RATE_96KHZ@GOTPAGE
Lloh7:
	ldr	x8, [x8, _CONTROL_FLAG_SRC_RATE_96KHZ@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_chipio_set_control_flag
Lloh9:
	adrp	x8, _CONTROL_FLAG_SRC_CLOCK_196MHZ@GOTPAGE
Lloh10:
	ldr	x8, [x8, _CONTROL_FLAG_SRC_CLOCK_196MHZ@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_chipio_set_control_flag
Lloh12:
	adrp	x8, _CONTROL_FLAG_ADC_B_96KHZ@GOTPAGE
Lloh13:
	ldr	x8, [x8, _CONTROL_FLAG_ADC_B_96KHZ@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_chipio_set_control_flag
Lloh15:
	adrp	x8, _CONTROL_FLAG_ADC_C_96KHZ@GOTPAGE
Lloh16:
	ldr	x8, [x8, _CONTROL_FLAG_ADC_C_96KHZ@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_chipio_set_control_flag
Lloh18:
	adrp	x8, _MEM_CONNID_MICIN1@GOTPAGE
Lloh19:
	ldr	x8, [x8, _MEM_CONNID_MICIN1@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
Lloh21:
	adrp	x20, _SR_96_000@GOTPAGE
Lloh22:
	ldr	x20, [x20, _SR_96_000@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	x0, x19
	bl	_chipio_set_conn_rate
Lloh23:
	adrp	x8, _MEM_CONNID_MICOUT1@GOTPAGE
Lloh24:
	ldr	x8, [x8, _MEM_CONNID_MICOUT1@GOTPAGEOFF]
Lloh25:
	ldr	w1, [x8]
	ldr	w2, [x20]
	mov	x0, x19
	bl	_chipio_set_conn_rate
Lloh26:
	adrp	x8, _MEM_CONNID_WUH@GOTPAGE
Lloh27:
	ldr	x8, [x8, _MEM_CONNID_WUH@GOTPAGEOFF]
Lloh28:
	ldr	w1, [x8]
Lloh29:
	adrp	x8, _SR_48_000@GOTPAGE
Lloh30:
	ldr	x8, [x8, _SR_48_000@GOTPAGEOFF]
Lloh31:
	ldr	w2, [x8]
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_chipio_set_conn_rate
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_CONTROL_FLAG_DSP_96KHZ,4,2     ; @CONTROL_FLAG_DSP_96KHZ
	.comm	_CONTROL_FLAG_DAC_96KHZ,4,2     ; @CONTROL_FLAG_DAC_96KHZ
	.comm	_CONTROL_FLAG_SRC_RATE_96KHZ,4,2 ; @CONTROL_FLAG_SRC_RATE_96KHZ
	.comm	_CONTROL_FLAG_SRC_CLOCK_196MHZ,4,2 ; @CONTROL_FLAG_SRC_CLOCK_196MHZ
	.comm	_CONTROL_FLAG_ADC_B_96KHZ,4,2   ; @CONTROL_FLAG_ADC_B_96KHZ
	.comm	_CONTROL_FLAG_ADC_C_96KHZ,4,2   ; @CONTROL_FLAG_ADC_C_96KHZ
	.comm	_MEM_CONNID_MICIN1,4,2          ; @MEM_CONNID_MICIN1
	.comm	_SR_96_000,4,2                  ; @SR_96_000
	.comm	_MEM_CONNID_MICOUT1,4,2         ; @MEM_CONNID_MICOUT1
	.comm	_MEM_CONNID_WUH,4,2             ; @MEM_CONNID_WUH
	.comm	_SR_48_000,4,2                  ; @SR_48_000
	.no_dead_strip	_ca0132_set_dsp_msr
.subsections_via_symbols
