	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function configure_clock
_configure_clock:                       ## @configure_clock
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	8(%rdi), %r12
	movl	(%r12), %eax
	cmpl	$129, %eax
	je	LBB0_4
## %bb.1:
	cmpl	$128, %eax
	jne	LBB0_12
## %bb.2:
	movl	4(%r12), %r14d
	cmpl	$12225001, %r14d                ## imm = 0xBA89E9
	setge	%cl
	movl	%r14d, %eax
	shrl	%cl, %eax
	movl	%eax, 8(%r12)
	xorl	%r15d, %r15d
	movq	%rbx, %rdi
	movl	$129, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	callq	_wm9081_set_fll
	movq	_WM9081_CLOCK_CONTROL_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_snd_soc_read
	movb	$1, %r13b
	cmpl	$12225000, %r14d                ## imm = 0xBA89E8
	jle	LBB0_23
## %bb.3:
	movq	_WM9081_MCLKDIV2@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	xorl	%r15d, %r15d
	movb	$1, %r13b
	movl	%eax, %edx
	jmp	LBB0_24
LBB0_4:
	cmpl	$0, 20(%r12)
	movq	%rbx, -48(%rbp)                 ## 8-byte Spill
	je	LBB0_13
## %bb.5:
	cmpl	$0, 12(%r12)
	je	LBB0_13
## %bb.6:
	movq	_clk_sys_rates@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	callq	_ARRAY_SIZE
	xorl	%r13d, %r13d
	testl	%eax, %eax
	jg	LBB0_8
## %bb.7:
                                        ## implicit-def: $r14d
	jmp	LBB0_11
	.p2align	4, 0x90
LBB0_10:                                ##   in Loop: Header=BB0_8 Depth=1
	incq	%r13
	callq	_ARRAY_SIZE
	cltq
	cmpq	%rax, %r13
	jge	LBB0_11
LBB0_8:                                 ## =>This Inner Loop Header: Depth=1
	movq	(%r15), %rdi
	movl	(%rdi,%r13,4), %r14d
	imull	16(%r12), %r14d
	cmpl	12(%r12), %r14d
	jl	LBB0_10
## %bb.9:                               ##   in Loop: Header=BB0_8 Depth=1
	cmpl	$3000000, %r14d                 ## imm = 0x2DC6C0
	jle	LBB0_10
LBB0_11:
	movq	(%r15), %rdi
	callq	_ARRAY_SIZE
	cmpl	%eax, %r13d
	je	LBB0_12
	jmp	LBB0_20
LBB0_13:
	cmpl	$0, 16(%r12)
	je	LBB0_14
## %bb.15:
	movq	_clk_sys_rates@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	callq	_ARRAY_SIZE
	xorl	%ebx, %ebx
	testl	%eax, %eax
	jle	LBB0_16
	.p2align	4, 0x90
LBB0_17:                                ## =>This Inner Loop Header: Depth=1
	movq	(%r15), %rdi
	movl	16(%r12), %r14d
	imull	(%rdi,%rbx,4), %r14d
	cmpl	$3000000, %r14d                 ## imm = 0x2DC6C0
	jg	LBB0_19
## %bb.18:                              ##   in Loop: Header=BB0_17 Depth=1
	incq	%rbx
	callq	_ARRAY_SIZE
	cltq
	cmpq	%rax, %rbx
	jl	LBB0_17
	jmp	LBB0_19
LBB0_14:
	movl	$12288000, %r14d                ## imm = 0xBB8000
	jmp	LBB0_20
LBB0_16:
                                        ## implicit-def: $r14d
LBB0_19:
	movq	(%r15), %rdi
	callq	_ARRAY_SIZE
	cmpl	%eax, %ebx
	jne	LBB0_20
LBB0_12:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r15d, %r15d
	subl	(%rax), %r15d
	jmp	LBB0_25
LBB0_20:
	movl	4(%r12), %edx
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movl	$129, %esi
	movl	%r14d, %ecx
	callq	_wm9081_set_fll
	movl	%eax, %r15d
	testl	%eax, %eax
	je	LBB0_22
## %bb.21:
	movl	4(%r12), %r14d
LBB0_22:
	testl	%r15d, %r15d
	setne	%r13b
	movl	%r14d, 8(%r12)
	movq	_WM9081_CLOCK_CONTROL_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	callq	_snd_soc_read
LBB0_23:
	movq	_WM9081_MCLKDIV2@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
LBB0_24:
	movq	_WM9081_CLOCK_CONTROL_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_snd_soc_write
	movq	_WM9081_CLOCK_CONTROL_3@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_snd_soc_read
	movq	_WM9081_CLK_SRC_SEL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%edx, %ecx
	orl	%eax, %ecx
	notl	%edx
	andl	%eax, %edx
	testb	%r13b, %r13b
	cmovel	%ecx, %edx
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_snd_soc_write
	movl	(%rbx), %edi
	movl	8(%r12), %edx
	leaq	L_.str(%rip), %rsi
	callq	_dev_dbg
LBB0_25:
	movl	%r15d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_clk_sys_rates,8,3              ## @clk_sys_rates
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_WM9081_CLOCK_CONTROL_1,4,2     ## @WM9081_CLOCK_CONTROL_1
	.comm	_WM9081_MCLKDIV2,4,2            ## @WM9081_MCLKDIV2
	.comm	_WM9081_CLOCK_CONTROL_3,4,2     ## @WM9081_CLOCK_CONTROL_3
	.comm	_WM9081_CLK_SRC_SEL,4,2         ## @WM9081_CLK_SRC_SEL
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"CLK_SYS is %dHz\n"

	.no_dead_strip	_configure_clock
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function configure_clock
_configure_clock:                       ; @configure_clock
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	x22, [x0, #8]
	ldr	w8, [x22]
	cmp	w8, #129
	b.eq	LBB0_4
; %bb.1:
	cmp	w8, #128
	b.ne	LBB0_18
; %bb.2:
	ldr	w20, [x22, #4]
	mov	w21, #35304
	movk	w21, #186, lsl #16
	cmp	w20, w21
	cset	w8, gt
	lsr	w8, w20, w8
	str	w8, [x22, #8]
	mov	x0, x19
	mov	w1, #129
	mov	w2, #0
	mov	w3, #0
	bl	_wm9081_set_fll
Lloh0:
	adrp	x8, _WM9081_CLOCK_CONTROL_1@GOTPAGE
Lloh1:
	ldr	x8, [x8, _WM9081_CLOCK_CONTROL_1@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_snd_soc_read
	cmp	w20, w21
	b.le	LBB0_15
; %bb.3:
	mov	w20, #0
Lloh3:
	adrp	x8, _WM9081_MCLKDIV2@GOTPAGE
Lloh4:
	ldr	x8, [x8, _WM9081_MCLKDIV2@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	orr	w2, w8, w0
	mov	w23, #1
	b	LBB0_24
LBB0_4:
	ldr	w8, [x22, #20]
	cbz	w8, LBB0_10
; %bb.5:
	ldr	w8, [x22, #12]
	cbz	w8, LBB0_10
; %bb.6:
Lloh6:
	adrp	x20, _clk_sys_rates@GOTPAGE
Lloh7:
	ldr	x20, [x20, _clk_sys_rates@GOTPAGEOFF]
	ldr	x0, [x20]
	bl	_ARRAY_SIZE
	cmp	w0, #1
	b.lt	LBB0_16
; %bb.7:
	mov	x23, #0
	mov	w24, #50880
	movk	w24, #45, lsl #16
LBB0_8:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x0, [x20]
	ldr	w8, [x0, x23, lsl #2]
	ldp	w10, w9, [x22, #12]
	mul	w21, w8, w9
	cmp	w21, w10
	ccmp	w21, w24, #4, ge
	b.gt	LBB0_17
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=1
	add	x23, x23, #1
	bl	_ARRAY_SIZE
	cmp	x23, w0, sxtw
	b.lt	LBB0_8
	b	LBB0_17
LBB0_10:
	ldr	w8, [x22, #16]
	cbz	w8, LBB0_19
; %bb.11:
Lloh8:
	adrp	x20, _clk_sys_rates@GOTPAGE
Lloh9:
	ldr	x20, [x20, _clk_sys_rates@GOTPAGEOFF]
	ldr	x0, [x20]
	bl	_ARRAY_SIZE
	cmp	w0, #1
	b.lt	LBB0_16
; %bb.12:
	mov	x23, #0
	mov	w24, #50880
	movk	w24, #45, lsl #16
LBB0_13:                                ; =>This Inner Loop Header: Depth=1
	ldr	x0, [x20]
	ldr	w8, [x0, x23, lsl #2]
	ldr	w9, [x22, #16]
	mul	w21, w9, w8
	cmp	w21, w24
	b.gt	LBB0_17
; %bb.14:                               ;   in Loop: Header=BB0_13 Depth=1
	add	x23, x23, #1
	bl	_ARRAY_SIZE
	cmp	x23, w0, sxtw
	b.lt	LBB0_13
	b	LBB0_17
LBB0_15:
	mov	w20, #0
	mov	w23, #1
	b	LBB0_23
LBB0_16:
	mov	w23, #0
                                        ; implicit-def: $w21
LBB0_17:
	ldr	x0, [x20]
	bl	_ARRAY_SIZE
	cmp	w23, w0
	b.ne	LBB0_20
LBB0_18:
Lloh10:
	adrp	x8, _EINVAL@GOTPAGE
Lloh11:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	neg	w20, w8
	b	LBB0_25
LBB0_19:
	mov	w21, #32768
	movk	w21, #187, lsl #16
LBB0_20:
	ldr	w2, [x22, #4]
	mov	x0, x19
	mov	w1, #129
	mov	x3, x21
	bl	_wm9081_set_fll
	mov	x20, x0
	cbz	w0, LBB0_22
; %bb.21:
	ldr	w21, [x22, #4]
LBB0_22:
	cmp	w20, #0
	cset	w23, ne
	str	w21, [x22, #8]
Lloh13:
	adrp	x8, _WM9081_CLOCK_CONTROL_1@GOTPAGE
Lloh14:
	ldr	x8, [x8, _WM9081_CLOCK_CONTROL_1@GOTPAGEOFF]
Lloh15:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_snd_soc_read
LBB0_23:
Lloh16:
	adrp	x8, _WM9081_MCLKDIV2@GOTPAGE
Lloh17:
	ldr	x8, [x8, _WM9081_MCLKDIV2@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	bic	w2, w0, w8
LBB0_24:
Lloh19:
	adrp	x8, _WM9081_CLOCK_CONTROL_1@GOTPAGE
Lloh20:
	ldr	x8, [x8, _WM9081_CLOCK_CONTROL_1@GOTPAGEOFF]
Lloh21:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_snd_soc_write
Lloh22:
	adrp	x21, _WM9081_CLOCK_CONTROL_3@GOTPAGE
Lloh23:
	ldr	x21, [x21, _WM9081_CLOCK_CONTROL_3@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_snd_soc_read
Lloh24:
	adrp	x8, _WM9081_CLK_SRC_SEL@GOTPAGE
Lloh25:
	ldr	x8, [x8, _WM9081_CLK_SRC_SEL@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	orr	w9, w8, w0
	bic	w8, w0, w8
	cmp	w23, #0
	csel	w2, w8, w9, ne
	ldr	w1, [x21]
	mov	x0, x19
	bl	_snd_soc_write
	ldr	w0, [x19]
	ldr	w2, [x22, #8]
Lloh27:
	adrp	x1, l_.str@PAGE
Lloh28:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_dbg
LBB0_25:
	mov	x0, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpAdd	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.cfi_endproc
                                        ; -- End function
	.comm	_clk_sys_rates,8,3              ; @clk_sys_rates
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_WM9081_CLOCK_CONTROL_1,4,2     ; @WM9081_CLOCK_CONTROL_1
	.comm	_WM9081_MCLKDIV2,4,2            ; @WM9081_MCLKDIV2
	.comm	_WM9081_CLOCK_CONTROL_3,4,2     ; @WM9081_CLOCK_CONTROL_3
	.comm	_WM9081_CLK_SRC_SEL,4,2         ; @WM9081_CLK_SRC_SEL
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"CLK_SYS is %dHz\n"

	.no_dead_strip	_configure_clock
.subsections_via_symbols
