	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_init_set_costs                 ## -- Begin function init_set_costs
	.p2align	4, 0x90
_init_set_costs:                        ## @init_set_costs
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_SImode@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_FIRST_PSEUDO_REGISTER@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	callq	_gen_raw_REG
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movl	(%rbx), %edi
	movl	(%r13), %esi
	incl	%esi
	callq	_gen_raw_REG
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_Pmode@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r13), %esi
	addl	$2, %esi
	callq	_gen_raw_REG
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_gen_rtx_MEM
	movl	%eax, %edi
	callq	_validize_mem
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	cmpl	$0, (%r13)
	je	LBB0_6
## %bb.1:
	xorl	%ebx, %ebx
	movq	_reg_class_contents@GOTPCREL(%rip), %r14
	movq	_GENERAL_REGS@GOTPCREL(%rip), %r15
	movq	_fixed_regs@GOTPCREL(%rip), %r12
	jmp	LBB0_2
	.p2align	4, 0x90
LBB0_5:                                 ##   in Loop: Header=BB0_2 Depth=1
	incq	%rbx
	movl	(%r13), %eax
	cmpq	%rax, %rbx
	jae	LBB0_6
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	(%r14), %rax
	movq	(%r15), %rcx
	movl	(%rax,%rcx,4), %edi
	movl	%ebx, %esi
	callq	_TEST_HARD_REG_BIT
	testq	%rax, %rax
	je	LBB0_5
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	(%r12), %rax
	cmpl	$0, (%rax,%rbx,4)
	jne	LBB0_5
## %bb.4:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	_target_avail_regs@GOTPCREL(%rip), %rax
	incl	(%rax)
	jmp	LBB0_5
LBB0_6:
	movq	_target_res_regs@GOTPCREL(%rip), %rax
	movl	$3, (%rax)
	xorl	%eax, %eax
	callq	_start_sequence
	movl	-52(%rbp), %r14d                ## 4-byte Reload
	movl	%r14d, %edi
	movl	-48(%rbp), %r15d                ## 4-byte Reload
	movl	%r15d, %esi
	callq	_emit_move_insn
	xorl	%eax, %eax
	callq	_get_insns
	movl	%eax, %ebx
	xorl	%eax, %eax
	callq	_end_sequence
	movl	%ebx, %edi
	callq	_seq_cost
	movq	_target_small_cost@GOTPCREL(%rip), %rcx
	movl	%eax, (%rcx)
	addl	%eax, %eax
	movq	_target_pres_cost@GOTPCREL(%rip), %rcx
	movl	%eax, (%rcx)
	xorl	%eax, %eax
	callq	_start_sequence
	movl	-44(%rbp), %ebx                 ## 4-byte Reload
	movl	%ebx, %edi
	movl	%r14d, %esi
	callq	_emit_move_insn
	movl	%r15d, %edi
	movl	%ebx, %esi
	callq	_emit_move_insn
	xorl	%eax, %eax
	callq	_get_insns
	movl	%eax, %ebx
	xorl	%eax, %eax
	callq	_end_sequence
	movl	%ebx, %edi
	callq	_seq_cost
	movq	_target_spill_cost@GOTPCREL(%rip), %rcx
	movq	%rax, (%rcx)
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_SImode,4,2                     ## @SImode
	.comm	_FIRST_PSEUDO_REGISTER,4,2      ## @FIRST_PSEUDO_REGISTER
	.comm	_Pmode,4,2                      ## @Pmode
	.comm	_reg_class_contents,8,3         ## @reg_class_contents
	.comm	_GENERAL_REGS,8,3               ## @GENERAL_REGS
	.comm	_fixed_regs,8,3                 ## @fixed_regs
	.comm	_target_avail_regs,4,2          ## @target_avail_regs
	.comm	_target_res_regs,4,2            ## @target_res_regs
	.comm	_target_small_cost,4,2          ## @target_small_cost
	.comm	_target_pres_cost,4,2           ## @target_pres_cost
	.comm	_target_spill_cost,8,3          ## @target_spill_cost
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_init_set_costs                 ; -- Begin function init_set_costs
	.p2align	2
_init_set_costs:                        ; @init_set_costs
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
Lloh0:
	adrp	x21, _SImode@GOTPAGE
Lloh1:
	ldr	x21, [x21, _SImode@GOTPAGEOFF]
	ldr	w0, [x21]
Lloh2:
	adrp	x23, _FIRST_PSEUDO_REGISTER@GOTPAGE
Lloh3:
	ldr	x23, [x23, _FIRST_PSEUDO_REGISTER@GOTPAGEOFF]
	ldr	w1, [x23]
	bl	_gen_raw_REG
	mov	x19, x0
	ldr	w0, [x21]
	ldr	w8, [x23]
	add	w1, w8, #1
	bl	_gen_raw_REG
	mov	x20, x0
Lloh4:
	adrp	x8, _Pmode@GOTPAGE
Lloh5:
	ldr	x8, [x8, _Pmode@GOTPAGEOFF]
Lloh6:
	ldr	w0, [x8]
	ldr	w8, [x23]
	add	w1, w8, #2
	bl	_gen_raw_REG
	mov	x1, x0
	ldr	w0, [x21]
	bl	_gen_rtx_MEM
	bl	_validize_mem
	mov	x21, x0
	ldr	w8, [x23]
	cbz	w8, LBB0_6
; %bb.1:
	mov	x22, #0
Lloh7:
	adrp	x24, _reg_class_contents@GOTPAGE
Lloh8:
	ldr	x24, [x24, _reg_class_contents@GOTPAGEOFF]
Lloh9:
	adrp	x25, _GENERAL_REGS@GOTPAGE
Lloh10:
	ldr	x25, [x25, _GENERAL_REGS@GOTPAGEOFF]
Lloh11:
	adrp	x26, _fixed_regs@GOTPAGE
Lloh12:
	ldr	x26, [x26, _fixed_regs@GOTPAGEOFF]
Lloh13:
	adrp	x27, _target_avail_regs@GOTPAGE
Lloh14:
	ldr	x27, [x27, _target_avail_regs@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:                                 ;   in Loop: Header=BB0_3 Depth=1
	add	x22, x22, #1
	ldr	w8, [x23]
	cmp	x22, x8
	b.hs	LBB0_6
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x24]
	ldr	x9, [x25]
	ldr	w0, [x8, x9, lsl #2]
	mov	x1, x22
	bl	_TEST_HARD_REG_BIT
	cbz	x0, LBB0_2
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	ldr	x8, [x26]
	ldr	w8, [x8, x22, lsl #2]
	cbnz	w8, LBB0_2
; %bb.5:                                ;   in Loop: Header=BB0_3 Depth=1
	ldr	w8, [x27]
	add	w8, w8, #1
	str	w8, [x27]
	b	LBB0_2
LBB0_6:
Lloh15:
	adrp	x8, _target_res_regs@GOTPAGE
Lloh16:
	ldr	x8, [x8, _target_res_regs@GOTPAGEOFF]
	mov	w9, #3
Lloh17:
	str	w9, [x8]
	bl	_start_sequence
	mov	x0, x19
	mov	x1, x20
	bl	_emit_move_insn
	bl	_get_insns
	mov	x22, x0
	bl	_end_sequence
	mov	x0, x22
	bl	_seq_cost
Lloh18:
	adrp	x8, _target_small_cost@GOTPAGE
Lloh19:
	ldr	x8, [x8, _target_small_cost@GOTPAGEOFF]
Lloh20:
	str	w0, [x8]
	lsl	w8, w0, #1
Lloh21:
	adrp	x9, _target_pres_cost@GOTPAGE
Lloh22:
	ldr	x9, [x9, _target_pres_cost@GOTPAGEOFF]
Lloh23:
	str	w8, [x9]
	bl	_start_sequence
	mov	x0, x21
	mov	x1, x19
	bl	_emit_move_insn
	mov	x0, x20
	mov	x1, x21
	bl	_emit_move_insn
	bl	_get_insns
	mov	x19, x0
	bl	_end_sequence
	mov	x0, x19
	bl	_seq_cost
Lloh24:
	adrp	x8, _target_spill_cost@GOTPAGE
Lloh25:
	ldr	x8, [x8, _target_spill_cost@GOTPAGEOFF]
Lloh26:
	str	x0, [x8]
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGotStr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotStr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotStr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotStr	Lloh15, Lloh16, Lloh17
	.cfi_endproc
                                        ; -- End function
	.comm	_SImode,4,2                     ; @SImode
	.comm	_FIRST_PSEUDO_REGISTER,4,2      ; @FIRST_PSEUDO_REGISTER
	.comm	_Pmode,4,2                      ; @Pmode
	.comm	_reg_class_contents,8,3         ; @reg_class_contents
	.comm	_GENERAL_REGS,8,3               ; @GENERAL_REGS
	.comm	_fixed_regs,8,3                 ; @fixed_regs
	.comm	_target_avail_regs,4,2          ; @target_avail_regs
	.comm	_target_res_regs,4,2            ; @target_res_regs
	.comm	_target_small_cost,4,2          ; @target_small_cost
	.comm	_target_pres_cost,4,2           ; @target_pres_cost
	.comm	_target_spill_cost,8,3          ; @target_spill_cost
.subsections_via_symbols
