	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function aml8726_sdxc_intr
_aml8726_sdxc_intr:                     ## @aml8726_sdxc_intr
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	callq	_AML_SDXC_LOCK
	movq	_AML_SDXC_IRQ_STATUS_REG@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_CSR_READ_4
	movl	%eax, %r15d
	movq	_AML_SDXC_SEND_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_CSR_READ_4
	movl	%eax, %r12d
	movq	_AML_SDXC_STATUS_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_CSR_READ_4
	cmpq	$0, 8(%rbx)
	je	LBB0_29
## %bb.1:
	movq	_MMC_ERR_NONE@GOTPCREL(%rip), %rsi
	movq	_AML_SDXC_IRQ_STATUS_TX_FIFO_EMPTY@GOTPCREL(%rip), %rdx
	movq	_AML_SDXC_IRQ_STATUS_RX_FIFO_FULL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rdx), %ecx
	testl	%r15d, %ecx
	movl	%r15d, -48(%rbp)                ## 4-byte Spill
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	je	LBB0_4
## %bb.2:
	movq	_MMC_ERR_FIFO@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	jmp	LBB0_10
LBB0_4:
	movq	_AML_SDXC_IRQ_ENABLE_A_PKG_CRC_ERR@GOTPCREL(%rip), %rdx
	movq	_AML_SDXC_IRQ_ENABLE_RESP_CRC_ERR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rdx), %ecx
	testl	%r15d, %ecx
	je	LBB0_6
## %bb.5:
	movq	_MMC_ERR_BADCRC@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	jmp	LBB0_10
LBB0_6:
	movq	_AML_SDXC_IRQ_ENABLE_A_PKG_TIMEOUT_ERR@GOTPCREL(%rip), %rdx
	movq	_AML_SDXC_IRQ_ENABLE_RESP_TIMEOUT_ERR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rdx), %ecx
	testl	%r15d, %ecx
	je	LBB0_8
## %bb.7:
	movq	_MMC_ERR_TIMEOUT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	jmp	LBB0_10
LBB0_8:
	movq	_AML_SDXC_IRQ_STATUS_RESP_OK@GOTPCREL(%rip), %rdx
	movq	_AML_SDXC_IRQ_STATUS_DMA_DONE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rdx), %ecx
	movq	_AML_SDXC_IRQ_STATUS_TRANSFER_DONE_OK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	testl	%r15d, %ecx
	je	LBB0_29
## %bb.9:
	movl	(%rsi), %eax
LBB0_10:
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	%rbx, %rdi
	callq	_aml8726_sdxc_disengage_dma
	movq	_AML_SDXC_SEND_CMD_HAS_RESP@GOTPCREL(%rip), %rax
	movl	%r12d, -52(%rbp)                ## 4-byte Spill
	testl	%r12d, (%rax)
	je	LBB0_13
## %bb.11:
	movq	_AML_SDXC_SEND_RESP_136@GOTPCREL(%rip), %rax
	xorl	%r12d, %r12d
	movl	-52(%rbp), %ecx                 ## 4-byte Reload
	testl	%ecx, (%rax)
	setne	%r12b
	leal	1(,%r12,4), %r14d
	movl	%r12d, %eax
	notl	%eax
	leal	(%rax,%r12,4), %r15d
	incl	%r15d
	movq	_AML_SDXC_PDMA_REG@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_12:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r13), %esi
	movq	%rbx, %rdi
	callq	_CSR_READ_4
	movq	_AML_SDXC_PDMA_RESP_INDEX_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_AML_SDXC_PDMA_DMA_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_AML_SDXC_PDMA_RESP_INDEX_SHIFT@GOTPCREL(%rip), %rcx
	movzbl	(%rcx), %ecx
	movl	%r12d, %edx
	shll	%cl, %edx
	notl	%esi
	andl	%eax, %esi
	orl	%esi, %edx
	movl	(%r13), %esi
	movq	%rbx, %rdi
	callq	_CSR_WRITE_4
	movq	_AML_SDXC_CMD_ARGUMENT_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_CSR_READ_4
	movq	8(%rbx), %rcx
	movq	(%rcx), %rcx
	movslq	%r15d, %r15
	movl	%eax, (%rcx,%r15,4)
	incq	%r12
	decl	%r15d
	cmpq	%r14, %r12
	jb	LBB0_12
LBB0_13:
	movq	_AML_SDXC_STATUS_BUSY@GOTPCREL(%rip), %r14
	movl	-56(%rbp), %r13d                ## 4-byte Reload
	testl	%r13d, (%r14)
	je	LBB0_14
## %bb.15:
	movq	_AML_SDXC_IRQ_STATUS_DMA_DONE@GOTPCREL(%rip), %rax
	movq	_AML_SDXC_IRQ_STATUS_TRANSFER_DONE_OK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movl	-48(%rbp), %edx                 ## 4-byte Reload
	testl	%edx, %ecx
	movl	-52(%rbp), %r12d                ## 4-byte Reload
	movl	-44(%rbp), %r15d                ## 4-byte Reload
	je	LBB0_17
## %bb.16:
	movq	_AML_SDXC_IRQ_STATUS_REG@GOTPCREL(%rip), %r14
	jmp	LBB0_25
LBB0_14:
	movq	_AML_SDXC_IRQ_STATUS_REG@GOTPCREL(%rip), %r14
	movl	-48(%rbp), %edx                 ## 4-byte Reload
	movl	-52(%rbp), %r12d                ## 4-byte Reload
	movl	-44(%rbp), %r15d                ## 4-byte Reload
	jmp	LBB0_25
LBB0_17:
	movq	_MMC_ERR_NONE@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r15d
	jne	LBB0_19
## %bb.18:
	movq	_MMC_ERR_FAILED@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
LBB0_19:
	movq	%rbx, %rdi
	callq	_aml8726_sdxc_soft_reset
	movq	_AML_SDXC_STATUS_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_CSR_READ_4
	testl	%eax, (%r14)
	je	LBB0_20
## %bb.21:
	movl	%r15d, -44(%rbp)                ## 4-byte Spill
	movq	_AML_SDXC_STATUS_REG@GOTPCREL(%rip), %r15
	.p2align	4, 0x90
LBB0_22:                                ## =>This Inner Loop Header: Depth=1
	xorl	%eax, %eax
	callq	_cpu_spinwait
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_CSR_READ_4
	testl	%eax, (%r14)
	jne	LBB0_22
## %bb.23:
	movq	_AML_SDXC_IRQ_STATUS_REG@GOTPCREL(%rip), %r14
	movl	-44(%rbp), %r15d                ## 4-byte Reload
	jmp	LBB0_24
LBB0_20:
	movq	_AML_SDXC_IRQ_STATUS_REG@GOTPCREL(%rip), %r14
LBB0_24:
	movl	-48(%rbp), %edx                 ## 4-byte Reload
LBB0_25:
	movq	8(%rbx), %rax
	movq	_MMC_RSP_BUSY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, 8(%rax)
	jne	LBB0_27
## %bb.26:
	movq	_AML_SDXC_SEND_INDEX_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %r12d
	movq	_MMC_STOP_TRANSMISSION@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r12d
	jne	LBB0_30
LBB0_27:
	movq	_AML_SDXC_STATUS_DAT0@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_28
LBB0_30:
	movq	%rbx, %rdi
	movl	%r15d, %esi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_aml8726_sdxc_finish_command    ## TAILCALL
LBB0_28:
	movl	%r15d, 4(%rbx)
	movq	_AML_SDXC_BUSY_POLL_INTVL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%edx, %r15d
	callq	_msecs_to_ticks
	movq	_aml8726_sdxc_busy_check@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%rbx, %rdi
	movl	%eax, %esi
	movq	%rbx, %rcx
	callq	_callout_reset
LBB0_29:
	movl	(%r14), %esi
	movq	_AML_SDXC_IRQ_STATUS_CLEAR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	andl	%r15d, %edx
	movq	%rbx, %rdi
	callq	_CSR_WRITE_4
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_CSR_BARRIER
	movq	%rbx, %rdi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_AML_SDXC_UNLOCK                ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AML_SDXC_IRQ_STATUS_REG,4,2    ## @AML_SDXC_IRQ_STATUS_REG
	.comm	_AML_SDXC_SEND_REG,4,2          ## @AML_SDXC_SEND_REG
	.comm	_AML_SDXC_STATUS_REG,4,2        ## @AML_SDXC_STATUS_REG
	.comm	_MMC_ERR_NONE,4,2               ## @MMC_ERR_NONE
	.comm	_AML_SDXC_IRQ_STATUS_TX_FIFO_EMPTY,4,2 ## @AML_SDXC_IRQ_STATUS_TX_FIFO_EMPTY
	.comm	_AML_SDXC_IRQ_STATUS_RX_FIFO_FULL,4,2 ## @AML_SDXC_IRQ_STATUS_RX_FIFO_FULL
	.comm	_MMC_ERR_FIFO,4,2               ## @MMC_ERR_FIFO
	.comm	_AML_SDXC_IRQ_ENABLE_A_PKG_CRC_ERR,4,2 ## @AML_SDXC_IRQ_ENABLE_A_PKG_CRC_ERR
	.comm	_AML_SDXC_IRQ_ENABLE_RESP_CRC_ERR,4,2 ## @AML_SDXC_IRQ_ENABLE_RESP_CRC_ERR
	.comm	_MMC_ERR_BADCRC,4,2             ## @MMC_ERR_BADCRC
	.comm	_AML_SDXC_IRQ_ENABLE_A_PKG_TIMEOUT_ERR,4,2 ## @AML_SDXC_IRQ_ENABLE_A_PKG_TIMEOUT_ERR
	.comm	_AML_SDXC_IRQ_ENABLE_RESP_TIMEOUT_ERR,4,2 ## @AML_SDXC_IRQ_ENABLE_RESP_TIMEOUT_ERR
	.comm	_MMC_ERR_TIMEOUT,4,2            ## @MMC_ERR_TIMEOUT
	.comm	_AML_SDXC_IRQ_STATUS_RESP_OK,4,2 ## @AML_SDXC_IRQ_STATUS_RESP_OK
	.comm	_AML_SDXC_IRQ_STATUS_DMA_DONE,4,2 ## @AML_SDXC_IRQ_STATUS_DMA_DONE
	.comm	_AML_SDXC_IRQ_STATUS_TRANSFER_DONE_OK,4,2 ## @AML_SDXC_IRQ_STATUS_TRANSFER_DONE_OK
	.comm	_AML_SDXC_IRQ_STATUS_CLEAR,4,2  ## @AML_SDXC_IRQ_STATUS_CLEAR
	.comm	_AML_SDXC_SEND_CMD_HAS_RESP,4,2 ## @AML_SDXC_SEND_CMD_HAS_RESP
	.comm	_AML_SDXC_SEND_RESP_136,4,2     ## @AML_SDXC_SEND_RESP_136
	.comm	_AML_SDXC_PDMA_REG,4,2          ## @AML_SDXC_PDMA_REG
	.comm	_AML_SDXC_PDMA_DMA_EN,4,2       ## @AML_SDXC_PDMA_DMA_EN
	.comm	_AML_SDXC_PDMA_RESP_INDEX_MASK,4,2 ## @AML_SDXC_PDMA_RESP_INDEX_MASK
	.comm	_AML_SDXC_PDMA_RESP_INDEX_SHIFT,4,2 ## @AML_SDXC_PDMA_RESP_INDEX_SHIFT
	.comm	_AML_SDXC_CMD_ARGUMENT_REG,4,2  ## @AML_SDXC_CMD_ARGUMENT_REG
	.comm	_AML_SDXC_STATUS_BUSY,4,2       ## @AML_SDXC_STATUS_BUSY
	.comm	_MMC_ERR_FAILED,4,2             ## @MMC_ERR_FAILED
	.comm	_MMC_RSP_BUSY,4,2               ## @MMC_RSP_BUSY
	.comm	_AML_SDXC_SEND_INDEX_MASK,4,2   ## @AML_SDXC_SEND_INDEX_MASK
	.comm	_MMC_STOP_TRANSMISSION,4,2      ## @MMC_STOP_TRANSMISSION
	.comm	_AML_SDXC_STATUS_DAT0,4,2       ## @AML_SDXC_STATUS_DAT0
	.comm	_AML_SDXC_BUSY_POLL_INTVL,4,2   ## @AML_SDXC_BUSY_POLL_INTVL
	.comm	_aml8726_sdxc_busy_check,4,2    ## @aml8726_sdxc_busy_check
	.no_dead_strip	_aml8726_sdxc_intr
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function aml8726_sdxc_intr
_aml8726_sdxc_intr:                     ; @aml8726_sdxc_intr
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	bl	_AML_SDXC_LOCK
Lloh0:
	adrp	x23, _AML_SDXC_IRQ_STATUS_REG@GOTPAGE
Lloh1:
	ldr	x23, [x23, _AML_SDXC_IRQ_STATUS_REG@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x19
	bl	_CSR_READ_4
	mov	x20, x0
Lloh2:
	adrp	x8, _AML_SDXC_SEND_REG@GOTPAGE
Lloh3:
	ldr	x8, [x8, _AML_SDXC_SEND_REG@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_CSR_READ_4
	mov	x22, x0
Lloh5:
	adrp	x25, _AML_SDXC_STATUS_REG@GOTPAGE
Lloh6:
	ldr	x25, [x25, _AML_SDXC_STATUS_REG@GOTPAGEOFF]
	ldr	w1, [x25]
	mov	x0, x19
	bl	_CSR_READ_4
	ldr	x8, [x19, #8]
	cbz	x8, LBB0_26
; %bb.1:
	mov	x21, x0
Lloh7:
	adrp	x10, _MMC_ERR_NONE@GOTPAGE
Lloh8:
	ldr	x10, [x10, _MMC_ERR_NONE@GOTPAGEOFF]
Lloh9:
	adrp	x8, _AML_SDXC_IRQ_STATUS_TX_FIFO_EMPTY@GOTPAGE
Lloh10:
	ldr	x8, [x8, _AML_SDXC_IRQ_STATUS_TX_FIFO_EMPTY@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
Lloh12:
	adrp	x9, _AML_SDXC_IRQ_STATUS_RX_FIFO_FULL@GOTPAGE
Lloh13:
	ldr	x9, [x9, _AML_SDXC_IRQ_STATUS_RX_FIFO_FULL@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	orr	w8, w9, w8
	tst	w8, w20
	b.eq	LBB0_3
; %bb.2:
Lloh15:
	adrp	x8, _MMC_ERR_FIFO@GOTPAGE
Lloh16:
	ldr	x8, [x8, _MMC_ERR_FIFO@GOTPAGEOFF]
	b	LBB0_7
LBB0_3:
Lloh17:
	adrp	x8, _AML_SDXC_IRQ_ENABLE_A_PKG_CRC_ERR@GOTPAGE
Lloh18:
	ldr	x8, [x8, _AML_SDXC_IRQ_ENABLE_A_PKG_CRC_ERR@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
Lloh20:
	adrp	x9, _AML_SDXC_IRQ_ENABLE_RESP_CRC_ERR@GOTPAGE
Lloh21:
	ldr	x9, [x9, _AML_SDXC_IRQ_ENABLE_RESP_CRC_ERR@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	orr	w8, w9, w8
	tst	w8, w20
	b.eq	LBB0_5
; %bb.4:
Lloh23:
	adrp	x8, _MMC_ERR_BADCRC@GOTPAGE
Lloh24:
	ldr	x8, [x8, _MMC_ERR_BADCRC@GOTPAGEOFF]
	b	LBB0_7
LBB0_5:
Lloh25:
	adrp	x8, _AML_SDXC_IRQ_ENABLE_A_PKG_TIMEOUT_ERR@GOTPAGE
Lloh26:
	ldr	x8, [x8, _AML_SDXC_IRQ_ENABLE_A_PKG_TIMEOUT_ERR@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
Lloh28:
	adrp	x9, _AML_SDXC_IRQ_ENABLE_RESP_TIMEOUT_ERR@GOTPAGE
Lloh29:
	ldr	x9, [x9, _AML_SDXC_IRQ_ENABLE_RESP_TIMEOUT_ERR@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
	orr	w8, w9, w8
	tst	w8, w20
	b.eq	LBB0_24
; %bb.6:
Lloh31:
	adrp	x8, _MMC_ERR_TIMEOUT@GOTPAGE
Lloh32:
	ldr	x8, [x8, _MMC_ERR_TIMEOUT@GOTPAGEOFF]
LBB0_7:
	ldr	w23, [x8]
LBB0_8:
	mov	x0, x19
	bl	_aml8726_sdxc_disengage_dma
Lloh33:
	adrp	x8, _AML_SDXC_SEND_CMD_HAS_RESP@GOTPAGE
Lloh34:
	ldr	x8, [x8, _AML_SDXC_SEND_CMD_HAS_RESP@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_14
; %bb.9:
Lloh36:
	adrp	x8, _AML_SDXC_SEND_RESP_136@GOTPAGE
Lloh37:
	ldr	x8, [x8, _AML_SDXC_SEND_RESP_136@GOTPAGEOFF]
Lloh38:
	ldr	w24, [x8]
Lloh39:
	adrp	x28, _AML_SDXC_PDMA_REG@GOTPAGE
Lloh40:
	ldr	x28, [x28, _AML_SDXC_PDMA_REG@GOTPAGEOFF]
	ldr	w1, [x28]
	mov	x0, x19
	bl	_CSR_READ_4
	tst	w24, w22
	cset	w24, ne
	mov	w8, #5
	csinc	w27, w8, wzr, ne
Lloh41:
	adrp	x8, _AML_SDXC_PDMA_DMA_EN@GOTPAGE
Lloh42:
	ldr	x8, [x8, _AML_SDXC_PDMA_DMA_EN@GOTPAGEOFF]
Lloh43:
	ldr	w8, [x8]
Lloh44:
	adrp	x9, _AML_SDXC_PDMA_RESP_INDEX_MASK@GOTPAGE
Lloh45:
	ldr	x9, [x9, _AML_SDXC_PDMA_RESP_INDEX_MASK@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
Lloh47:
	adrp	x9, _AML_SDXC_PDMA_RESP_INDEX_SHIFT@GOTPAGE
Lloh48:
	ldr	x9, [x9, _AML_SDXC_PDMA_RESP_INDEX_SHIFT@GOTPAGEOFF]
Lloh49:
	ldr	w9, [x9]
	lsl	w9, w24, w9
	orr	w2, w8, w9
	ldr	w1, [x28]
	mov	w8, #1
	cinc	x26, x8, ne
	mov	x0, x19
	bl	_CSR_WRITE_4
Lloh50:
	adrp	x8, _AML_SDXC_CMD_ARGUMENT_REG@GOTPAGE
Lloh51:
	ldr	x8, [x8, _AML_SDXC_CMD_ARGUMENT_REG@GOTPAGEOFF]
Lloh52:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_CSR_READ_4
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	mvn	w9, w24
	add	w9, w27, w9
	str	w0, [x8, w9, sxtw #2]
	cmp	x26, x27
	b.hs	LBB0_14
; %bb.10:
	ldr	w1, [x28]
	mov	x0, x19
	bl	_CSR_READ_4
Lloh53:
	adrp	x8, _AML_SDXC_PDMA_DMA_EN@GOTPAGE
Lloh54:
	ldr	x8, [x8, _AML_SDXC_PDMA_DMA_EN@GOTPAGEOFF]
Lloh55:
	ldr	w8, [x8]
Lloh56:
	adrp	x9, _AML_SDXC_PDMA_RESP_INDEX_MASK@GOTPAGE
Lloh57:
	ldr	x9, [x9, _AML_SDXC_PDMA_RESP_INDEX_MASK@GOTPAGEOFF]
Lloh58:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
Lloh59:
	adrp	x9, _AML_SDXC_PDMA_RESP_INDEX_SHIFT@GOTPAGE
Lloh60:
	ldr	x9, [x9, _AML_SDXC_PDMA_RESP_INDEX_SHIFT@GOTPAGEOFF]
Lloh61:
	ldr	w9, [x9]
	lsl	w9, w26, w9
	orr	w2, w8, w9
	ldr	w1, [x28]
	mov	x0, x19
	bl	_CSR_WRITE_4
Lloh62:
	adrp	x8, _AML_SDXC_CMD_ARGUMENT_REG@GOTPAGE
Lloh63:
	ldr	x8, [x8, _AML_SDXC_CMD_ARGUMENT_REG@GOTPAGEOFF]
Lloh64:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_CSR_READ_4
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	mvn	w9, w26
	add	w9, w27, w9
	str	w0, [x8, w9, sxtw #2]
	add	x24, x26, #1
	cmp	x24, x27
	b.hs	LBB0_14
; %bb.11:
	ldr	w1, [x28]
	mov	x0, x19
	bl	_CSR_READ_4
Lloh65:
	adrp	x8, _AML_SDXC_PDMA_DMA_EN@GOTPAGE
Lloh66:
	ldr	x8, [x8, _AML_SDXC_PDMA_DMA_EN@GOTPAGEOFF]
Lloh67:
	ldr	w8, [x8]
Lloh68:
	adrp	x9, _AML_SDXC_PDMA_RESP_INDEX_MASK@GOTPAGE
Lloh69:
	ldr	x9, [x9, _AML_SDXC_PDMA_RESP_INDEX_MASK@GOTPAGEOFF]
Lloh70:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
Lloh71:
	adrp	x9, _AML_SDXC_PDMA_RESP_INDEX_SHIFT@GOTPAGE
Lloh72:
	ldr	x9, [x9, _AML_SDXC_PDMA_RESP_INDEX_SHIFT@GOTPAGEOFF]
Lloh73:
	ldr	w9, [x9]
	lsl	w9, w24, w9
	orr	w2, w8, w9
	ldr	w1, [x28]
	mov	x0, x19
	bl	_CSR_WRITE_4
Lloh74:
	adrp	x8, _AML_SDXC_CMD_ARGUMENT_REG@GOTPAGE
Lloh75:
	ldr	x8, [x8, _AML_SDXC_CMD_ARGUMENT_REG@GOTPAGEOFF]
Lloh76:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_CSR_READ_4
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	mvn	w9, w24
	add	w9, w27, w9
	str	w0, [x8, w9, sxtw #2]
	add	x24, x26, #2
	cmp	x24, x27
	b.hs	LBB0_14
; %bb.12:
	ldr	w1, [x28]
	mov	x0, x19
	bl	_CSR_READ_4
Lloh77:
	adrp	x8, _AML_SDXC_PDMA_DMA_EN@GOTPAGE
Lloh78:
	ldr	x8, [x8, _AML_SDXC_PDMA_DMA_EN@GOTPAGEOFF]
Lloh79:
	ldr	w8, [x8]
Lloh80:
	adrp	x9, _AML_SDXC_PDMA_RESP_INDEX_MASK@GOTPAGE
Lloh81:
	ldr	x9, [x9, _AML_SDXC_PDMA_RESP_INDEX_MASK@GOTPAGEOFF]
Lloh82:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
Lloh83:
	adrp	x9, _AML_SDXC_PDMA_RESP_INDEX_SHIFT@GOTPAGE
Lloh84:
	ldr	x9, [x9, _AML_SDXC_PDMA_RESP_INDEX_SHIFT@GOTPAGEOFF]
Lloh85:
	ldr	w9, [x9]
	lsl	w9, w24, w9
	orr	w2, w8, w9
	ldr	w1, [x28]
	mov	x0, x19
	bl	_CSR_WRITE_4
Lloh86:
	adrp	x8, _AML_SDXC_CMD_ARGUMENT_REG@GOTPAGE
Lloh87:
	ldr	x8, [x8, _AML_SDXC_CMD_ARGUMENT_REG@GOTPAGEOFF]
Lloh88:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_CSR_READ_4
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	mvn	w9, w24
	add	w9, w27, w9
	str	w0, [x8, w9, sxtw #2]
	add	x24, x26, #3
	cmp	x24, x27
	b.hs	LBB0_14
; %bb.13:
	ldr	w1, [x28]
	mov	x0, x19
	bl	_CSR_READ_4
Lloh89:
	adrp	x8, _AML_SDXC_PDMA_DMA_EN@GOTPAGE
Lloh90:
	ldr	x8, [x8, _AML_SDXC_PDMA_DMA_EN@GOTPAGEOFF]
Lloh91:
	ldr	w8, [x8]
Lloh92:
	adrp	x9, _AML_SDXC_PDMA_RESP_INDEX_MASK@GOTPAGE
Lloh93:
	ldr	x9, [x9, _AML_SDXC_PDMA_RESP_INDEX_MASK@GOTPAGEOFF]
Lloh94:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
Lloh95:
	adrp	x9, _AML_SDXC_PDMA_RESP_INDEX_SHIFT@GOTPAGE
Lloh96:
	ldr	x9, [x9, _AML_SDXC_PDMA_RESP_INDEX_SHIFT@GOTPAGEOFF]
Lloh97:
	ldr	w9, [x9]
	lsl	w9, w24, w9
	orr	w2, w8, w9
	ldr	w1, [x28]
	mov	x0, x19
	bl	_CSR_WRITE_4
Lloh98:
	adrp	x8, _AML_SDXC_CMD_ARGUMENT_REG@GOTPAGE
Lloh99:
	ldr	x8, [x8, _AML_SDXC_CMD_ARGUMENT_REG@GOTPAGEOFF]
Lloh100:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_CSR_READ_4
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	mvn	w9, w24
	add	w9, w27, w9
	str	w0, [x8, w9, sxtw #2]
LBB0_14:
Lloh101:
	adrp	x26, _AML_SDXC_STATUS_BUSY@GOTPAGE
Lloh102:
	ldr	x26, [x26, _AML_SDXC_STATUS_BUSY@GOTPAGEOFF]
	ldr	w8, [x26]
	tst	w8, w21
	b.eq	LBB0_16
; %bb.15:
Lloh103:
	adrp	x8, _AML_SDXC_IRQ_STATUS_DMA_DONE@GOTPAGE
Lloh104:
	ldr	x8, [x8, _AML_SDXC_IRQ_STATUS_DMA_DONE@GOTPAGEOFF]
Lloh105:
	ldr	w8, [x8]
Lloh106:
	adrp	x9, _AML_SDXC_IRQ_STATUS_TRANSFER_DONE_OK@GOTPAGE
Lloh107:
	ldr	x9, [x9, _AML_SDXC_IRQ_STATUS_TRANSFER_DONE_OK@GOTPAGEOFF]
Lloh108:
	ldr	w9, [x9]
	orr	w8, w9, w8
	tst	w8, w20
	b.eq	LBB0_21
LBB0_16:
	ldr	x8, [x19, #8]
	ldr	w8, [x8, #8]
Lloh109:
	adrp	x9, _MMC_RSP_BUSY@GOTPAGE
Lloh110:
	ldr	x9, [x9, _MMC_RSP_BUSY@GOTPAGEOFF]
Lloh111:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_18
; %bb.17:
Lloh112:
	adrp	x8, _AML_SDXC_SEND_INDEX_MASK@GOTPAGE
Lloh113:
	ldr	x8, [x8, _AML_SDXC_SEND_INDEX_MASK@GOTPAGEOFF]
Lloh114:
	ldr	w8, [x8]
	and	w8, w8, w22
Lloh115:
	adrp	x9, _MMC_STOP_TRANSMISSION@GOTPAGE
Lloh116:
	ldr	x9, [x9, _MMC_STOP_TRANSMISSION@GOTPAGEOFF]
Lloh117:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_19
LBB0_18:
Lloh118:
	adrp	x8, _AML_SDXC_STATUS_DAT0@GOTPAGE
Lloh119:
	ldr	x8, [x8, _AML_SDXC_STATUS_DAT0@GOTPAGEOFF]
Lloh120:
	ldr	w8, [x8]
	tst	w8, w21
	b.eq	LBB0_20
LBB0_19:
	mov	x0, x19
	mov	x1, x23
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_aml8726_sdxc_finish_command
LBB0_20:
	str	w23, [x19, #4]
Lloh121:
	adrp	x8, _AML_SDXC_BUSY_POLL_INTVL@GOTPAGE
Lloh122:
	ldr	x8, [x8, _AML_SDXC_BUSY_POLL_INTVL@GOTPAGEOFF]
Lloh123:
	ldr	w0, [x8]
	bl	_msecs_to_ticks
	mov	x1, x0
Lloh124:
	adrp	x8, _aml8726_sdxc_busy_check@GOTPAGE
Lloh125:
	ldr	x8, [x8, _aml8726_sdxc_busy_check@GOTPAGEOFF]
Lloh126:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x3, x19
	bl	_callout_reset
Lloh127:
	adrp	x21, _AML_SDXC_IRQ_STATUS_REG@GOTPAGE
Lloh128:
	ldr	x21, [x21, _AML_SDXC_IRQ_STATUS_REG@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh129:
	adrp	x8, _AML_SDXC_IRQ_STATUS_CLEAR@GOTPAGE
Lloh130:
	ldr	x8, [x8, _AML_SDXC_IRQ_STATUS_CLEAR@GOTPAGEOFF]
Lloh131:
	ldr	w8, [x8]
	and	w2, w8, w20
	mov	x0, x19
	bl	_CSR_WRITE_4
	ldr	w1, [x21]
	b	LBB0_27
LBB0_21:
Lloh132:
	adrp	x8, _MMC_ERR_NONE@GOTPAGE
Lloh133:
	ldr	x8, [x8, _MMC_ERR_NONE@GOTPAGEOFF]
Lloh134:
	ldr	w8, [x8]
Lloh135:
	adrp	x9, _MMC_ERR_FAILED@GOTPAGE
Lloh136:
	ldr	x9, [x9, _MMC_ERR_FAILED@GOTPAGEOFF]
Lloh137:
	ldr	w9, [x9]
	cmp	w23, w8
	csel	w23, w9, w23, eq
	mov	x0, x19
	bl	_aml8726_sdxc_soft_reset
LBB0_22:                                ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x25]
	mov	x0, x19
	bl	_CSR_READ_4
	ldr	w8, [x26]
	tst	w8, w0
	b.eq	LBB0_16
; %bb.23:                               ;   in Loop: Header=BB0_22 Depth=1
	bl	_cpu_spinwait
	b	LBB0_22
LBB0_24:
Lloh138:
	adrp	x8, _AML_SDXC_IRQ_STATUS_RESP_OK@GOTPAGE
Lloh139:
	ldr	x8, [x8, _AML_SDXC_IRQ_STATUS_RESP_OK@GOTPAGEOFF]
Lloh140:
	ldr	w8, [x8]
Lloh141:
	adrp	x9, _AML_SDXC_IRQ_STATUS_DMA_DONE@GOTPAGE
Lloh142:
	ldr	x9, [x9, _AML_SDXC_IRQ_STATUS_DMA_DONE@GOTPAGEOFF]
Lloh143:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh144:
	adrp	x9, _AML_SDXC_IRQ_STATUS_TRANSFER_DONE_OK@GOTPAGE
Lloh145:
	ldr	x9, [x9, _AML_SDXC_IRQ_STATUS_TRANSFER_DONE_OK@GOTPAGEOFF]
Lloh146:
	ldr	w9, [x9]
	orr	w8, w8, w9
	tst	w8, w20
	b.eq	LBB0_26
; %bb.25:
	ldr	w23, [x10]
	b	LBB0_8
LBB0_26:
	ldr	w1, [x23]
Lloh147:
	adrp	x8, _AML_SDXC_IRQ_STATUS_CLEAR@GOTPAGE
Lloh148:
	ldr	x8, [x8, _AML_SDXC_IRQ_STATUS_CLEAR@GOTPAGEOFF]
Lloh149:
	ldr	w8, [x8]
	and	w2, w8, w20
	mov	x0, x19
	bl	_CSR_WRITE_4
	ldr	w1, [x23]
LBB0_27:
	mov	x0, x19
	bl	_CSR_BARRIER
	mov	x0, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_AML_SDXC_UNLOCK
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGot	Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.loh AdrpLdrGotLdr	Lloh112, Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGotLdr	Lloh129, Lloh130, Lloh131
	.loh AdrpLdrGot	Lloh127, Lloh128
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh135, Lloh136, Lloh137
	.loh AdrpLdrGotLdr	Lloh132, Lloh133, Lloh134
	.loh AdrpLdrGotLdr	Lloh144, Lloh145, Lloh146
	.loh AdrpLdrGotLdr	Lloh141, Lloh142, Lloh143
	.loh AdrpLdrGotLdr	Lloh138, Lloh139, Lloh140
	.loh AdrpLdrGotLdr	Lloh147, Lloh148, Lloh149
	.cfi_endproc
                                        ; -- End function
	.comm	_AML_SDXC_IRQ_STATUS_REG,4,2    ; @AML_SDXC_IRQ_STATUS_REG
	.comm	_AML_SDXC_SEND_REG,4,2          ; @AML_SDXC_SEND_REG
	.comm	_AML_SDXC_STATUS_REG,4,2        ; @AML_SDXC_STATUS_REG
	.comm	_MMC_ERR_NONE,4,2               ; @MMC_ERR_NONE
	.comm	_AML_SDXC_IRQ_STATUS_TX_FIFO_EMPTY,4,2 ; @AML_SDXC_IRQ_STATUS_TX_FIFO_EMPTY
	.comm	_AML_SDXC_IRQ_STATUS_RX_FIFO_FULL,4,2 ; @AML_SDXC_IRQ_STATUS_RX_FIFO_FULL
	.comm	_MMC_ERR_FIFO,4,2               ; @MMC_ERR_FIFO
	.comm	_AML_SDXC_IRQ_ENABLE_A_PKG_CRC_ERR,4,2 ; @AML_SDXC_IRQ_ENABLE_A_PKG_CRC_ERR
	.comm	_AML_SDXC_IRQ_ENABLE_RESP_CRC_ERR,4,2 ; @AML_SDXC_IRQ_ENABLE_RESP_CRC_ERR
	.comm	_MMC_ERR_BADCRC,4,2             ; @MMC_ERR_BADCRC
	.comm	_AML_SDXC_IRQ_ENABLE_A_PKG_TIMEOUT_ERR,4,2 ; @AML_SDXC_IRQ_ENABLE_A_PKG_TIMEOUT_ERR
	.comm	_AML_SDXC_IRQ_ENABLE_RESP_TIMEOUT_ERR,4,2 ; @AML_SDXC_IRQ_ENABLE_RESP_TIMEOUT_ERR
	.comm	_MMC_ERR_TIMEOUT,4,2            ; @MMC_ERR_TIMEOUT
	.comm	_AML_SDXC_IRQ_STATUS_RESP_OK,4,2 ; @AML_SDXC_IRQ_STATUS_RESP_OK
	.comm	_AML_SDXC_IRQ_STATUS_DMA_DONE,4,2 ; @AML_SDXC_IRQ_STATUS_DMA_DONE
	.comm	_AML_SDXC_IRQ_STATUS_TRANSFER_DONE_OK,4,2 ; @AML_SDXC_IRQ_STATUS_TRANSFER_DONE_OK
	.comm	_AML_SDXC_IRQ_STATUS_CLEAR,4,2  ; @AML_SDXC_IRQ_STATUS_CLEAR
	.comm	_AML_SDXC_SEND_CMD_HAS_RESP,4,2 ; @AML_SDXC_SEND_CMD_HAS_RESP
	.comm	_AML_SDXC_SEND_RESP_136,4,2     ; @AML_SDXC_SEND_RESP_136
	.comm	_AML_SDXC_PDMA_REG,4,2          ; @AML_SDXC_PDMA_REG
	.comm	_AML_SDXC_PDMA_DMA_EN,4,2       ; @AML_SDXC_PDMA_DMA_EN
	.comm	_AML_SDXC_PDMA_RESP_INDEX_MASK,4,2 ; @AML_SDXC_PDMA_RESP_INDEX_MASK
	.comm	_AML_SDXC_PDMA_RESP_INDEX_SHIFT,4,2 ; @AML_SDXC_PDMA_RESP_INDEX_SHIFT
	.comm	_AML_SDXC_CMD_ARGUMENT_REG,4,2  ; @AML_SDXC_CMD_ARGUMENT_REG
	.comm	_AML_SDXC_STATUS_BUSY,4,2       ; @AML_SDXC_STATUS_BUSY
	.comm	_MMC_ERR_FAILED,4,2             ; @MMC_ERR_FAILED
	.comm	_MMC_RSP_BUSY,4,2               ; @MMC_RSP_BUSY
	.comm	_AML_SDXC_SEND_INDEX_MASK,4,2   ; @AML_SDXC_SEND_INDEX_MASK
	.comm	_MMC_STOP_TRANSMISSION,4,2      ; @MMC_STOP_TRANSMISSION
	.comm	_AML_SDXC_STATUS_DAT0,4,2       ; @AML_SDXC_STATUS_DAT0
	.comm	_AML_SDXC_BUSY_POLL_INTVL,4,2   ; @AML_SDXC_BUSY_POLL_INTVL
	.comm	_aml8726_sdxc_busy_check,4,2    ; @aml8726_sdxc_busy_check
	.no_dead_strip	_aml8726_sdxc_intr
.subsections_via_symbols
