	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_ahci_ctrl_init
_tegra_ahci_ctrl_init:                  ## @tegra_ahci_ctrl_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_SATA_CONFIGURATION@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rsi
	callq	_SATA_RD4
	movq	_SATA_CONFIGURATION_EN_FPCI@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	(%rbx), %rsi
	movq	%r14, %rdi
	movl	%eax, %edx
	callq	_SATA_WR4
	movq	_FUSE_SATA_CALIB@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_tegra_fuse_read_4
	movq	_tegra124_pad_calibration@GOTPCREL(%rip), %rcx
	movq	(%rcx), %r13
	movq	_FUSE_SATA_CALIB_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movslq	%eax, %r12
	movq	_SCFG_OFFSET@GOTPCREL(%rip), %r15
	movq	_T_SATA0_INDEX@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%r15), %rsi
	movq	%r14, %rdi
	movl	$1, %edx
	callq	_SATA_WR4
	movq	_T_SATA0_CHX_PHY_CTRL1_GEN1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%r15), %rsi
	movq	%r14, %rdi
	callq	_SATA_RD4
	movq	_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %sil
	movl	%esi, %ecx
	shll	%cl, %edx
	movq	_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movq	_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %bl
	movl	%ebx, %ecx
	shll	%cl, %edi
	orl	%edx, %edi
	notl	%edi
	andl	%eax, %edi
	shlq	$4, %r12
	movl	(%r13,%r12), %eax
	movl	4(%r13,%r12), %edx
	movl	%esi, %ecx
	shll	%cl, %eax
	orl	%edi, %eax
	movl	%ebx, %ecx
	shll	%cl, %edx
	orl	%eax, %edx
	movq	_T_SATA0_CHX_PHY_CTRL1_GEN1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%r15), %rsi
	movq	%r14, %rdi
	callq	_SATA_WR4
	movq	_T_SATA0_CHX_PHY_CTRL1_GEN2@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%r15), %rsi
	movq	%r14, %rdi
	callq	_SATA_RD4
	movq	_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %sil
	movl	%esi, %ecx
	shll	%cl, %edx
	movq	_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movq	_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %bl
	movl	%ebx, %ecx
	shll	%cl, %edi
	orl	%edx, %edi
	notl	%edi
	andl	%eax, %edi
	movl	8(%r13,%r12), %eax
	movl	12(%r13,%r12), %edx
	movl	%esi, %ecx
	shll	%cl, %eax
	orl	%edi, %eax
	movl	%ebx, %ecx
	shll	%cl, %edx
	orl	%eax, %edx
	movq	_T_SATA0_CHX_PHY_CTRL1_GEN2@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%r15), %rsi
	movq	%r14, %rdi
	callq	_SATA_WR4
	movq	_T_SATA0_CHX_PHY_CTRL11@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%r15), %rsi
	movq	_T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_SATA_WR4
	movq	_T_SATA0_CHX_PHY_CTRL2@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%r15), %rsi
	movq	_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_SATA_WR4
	movq	_T_SATA0_INDEX@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%r15), %rsi
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	_SATA_WR4
	movq	_T_SATA0_CFG_SATA@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rsi
	addq	(%r15), %rsi
	movq	%r14, %rdi
	callq	_SATA_RD4
	movq	_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN@GOTPCREL(%rip), %r12
	orl	(%r12), %eax
	movq	(%rbx), %rsi
	addq	(%r15), %rsi
	movq	%r14, %rdi
	movl	%eax, %edx
	callq	_SATA_WR4
	movq	_T_SATA0_BKDOOR_CC@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%r15), %rsi
	movq	%r14, %rdi
	movl	$17170688, %edx                 ## imm = 0x1060100
	callq	_SATA_WR4
	movq	(%rbx), %rsi
	addq	(%r15), %rsi
	movq	%r14, %rdi
	callq	_SATA_RD4
	movl	(%r12), %edx
	notl	%edx
	andl	%eax, %edx
	movq	(%rbx), %rsi
	addq	(%r15), %rsi
	movq	%r14, %rdi
	callq	_SATA_WR4
	movq	_T_SATA0_CFG_1@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rsi
	addq	(%r15), %rsi
	movq	%r14, %rdi
	callq	_SATA_RD4
	movq	_T_SATA0_CFG_1_IO_SPACE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_T_SATA0_CFG_1_MEMORY_SPACE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_T_SATA0_CFG_1_BUS_MASTER@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_T_SATA0_CFG_1_SERR@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	(%rbx), %rsi
	addq	(%r15), %rsi
	movq	%r14, %rdi
	movl	%eax, %edx
	callq	_SATA_WR4
	movq	_SATA_FPCI_BAR5@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_SATA_FPCI_BAR5_START_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$65536, %edx                    ## imm = 0x10000
	shll	%cl, %edx
	movq	%r14, %rdi
	callq	_SATA_WR4
	movq	_T_SATA0_CFG_9@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%r15), %rsi
	movq	_T_SATA0_CFG_9_BASE_ADDRESS_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$32768, %edx                    ## imm = 0x8000
	shll	%cl, %edx
	movq	%r14, %rdi
	callq	_SATA_WR4
	movq	_SATA_INTR_MASK@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rsi
	movq	%r14, %rdi
	callq	_SATA_RD4
	movq	_SATA_INTR_MASK_IP_INT_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	(%rbx), %rsi
	movq	%r14, %rdi
	movl	%eax, %edx
	callq	_SATA_WR4
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_SATA_CONFIGURATION,8,3         ## @SATA_CONFIGURATION
	.comm	_SATA_CONFIGURATION_EN_FPCI,4,2 ## @SATA_CONFIGURATION_EN_FPCI
	.comm	_FUSE_SATA_CALIB,4,2            ## @FUSE_SATA_CALIB
	.comm	_tegra124_pad_calibration,8,3   ## @tegra124_pad_calibration
	.comm	_FUSE_SATA_CALIB_MASK,4,2       ## @FUSE_SATA_CALIB_MASK
	.comm	_SCFG_OFFSET,8,3                ## @SCFG_OFFSET
	.comm	_T_SATA0_INDEX,8,3              ## @T_SATA0_INDEX
	.comm	_T_SATA0_CHX_PHY_CTRL1_GEN1,8,3 ## @T_SATA0_CHX_PHY_CTRL1_GEN1
	.comm	_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK,4,2 ## @T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK
	.comm	_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT,4,2 ## @T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT
	.comm	_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK,4,2 ## @T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK
	.comm	_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT,4,2 ## @T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT
	.comm	_T_SATA0_CHX_PHY_CTRL1_GEN2,8,3 ## @T_SATA0_CHX_PHY_CTRL1_GEN2
	.comm	_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK,4,2 ## @T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK
	.comm	_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT,4,2 ## @T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT
	.comm	_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK,4,2 ## @T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK
	.comm	_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT,4,2 ## @T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT
	.comm	_T_SATA0_CHX_PHY_CTRL11,8,3     ## @T_SATA0_CHX_PHY_CTRL11
	.comm	_T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,4,2 ## @T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ
	.comm	_T_SATA0_CHX_PHY_CTRL2,8,3      ## @T_SATA0_CHX_PHY_CTRL2
	.comm	_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,4,2 ## @T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1
	.comm	_T_SATA0_CFG_SATA,8,3           ## @T_SATA0_CFG_SATA
	.comm	_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN,4,2 ## @T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN
	.comm	_T_SATA0_BKDOOR_CC,8,3          ## @T_SATA0_BKDOOR_CC
	.comm	_T_SATA0_CFG_1,8,3              ## @T_SATA0_CFG_1
	.comm	_T_SATA0_CFG_1_IO_SPACE,4,2     ## @T_SATA0_CFG_1_IO_SPACE
	.comm	_T_SATA0_CFG_1_MEMORY_SPACE,4,2 ## @T_SATA0_CFG_1_MEMORY_SPACE
	.comm	_T_SATA0_CFG_1_BUS_MASTER,4,2   ## @T_SATA0_CFG_1_BUS_MASTER
	.comm	_T_SATA0_CFG_1_SERR,4,2         ## @T_SATA0_CFG_1_SERR
	.comm	_SATA_FPCI_BAR5,8,3             ## @SATA_FPCI_BAR5
	.comm	_SATA_FPCI_BAR5_START_SHIFT,4,2 ## @SATA_FPCI_BAR5_START_SHIFT
	.comm	_T_SATA0_CFG_9,8,3              ## @T_SATA0_CFG_9
	.comm	_T_SATA0_CFG_9_BASE_ADDRESS_SHIFT,4,2 ## @T_SATA0_CFG_9_BASE_ADDRESS_SHIFT
	.comm	_SATA_INTR_MASK,8,3             ## @SATA_INTR_MASK
	.comm	_SATA_INTR_MASK_IP_INT_MASK,4,2 ## @SATA_INTR_MASK_IP_INT_MASK
	.no_dead_strip	_tegra_ahci_ctrl_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_ahci_ctrl_init
_tegra_ahci_ctrl_init:                  ; @tegra_ahci_ctrl_init
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x20, _SATA_CONFIGURATION@GOTPAGE
Lloh1:
	ldr	x20, [x20, _SATA_CONFIGURATION@GOTPAGEOFF]
	ldr	x1, [x20]
	bl	_SATA_RD4
Lloh2:
	adrp	x8, _SATA_CONFIGURATION_EN_FPCI@GOTPAGE
Lloh3:
	ldr	x8, [x8, _SATA_CONFIGURATION_EN_FPCI@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	orr	w2, w8, w0
	ldr	x1, [x20]
	mov	x0, x19
	bl	_SATA_WR4
Lloh5:
	adrp	x8, _FUSE_SATA_CALIB@GOTPAGE
Lloh6:
	ldr	x8, [x8, _FUSE_SATA_CALIB@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
	bl	_tegra_fuse_read_4
Lloh8:
	adrp	x8, _tegra124_pad_calibration@GOTPAGE
Lloh9:
	ldr	x8, [x8, _tegra124_pad_calibration@GOTPAGEOFF]
Lloh10:
	ldr	x22, [x8]
Lloh11:
	adrp	x8, _FUSE_SATA_CALIB_MASK@GOTPAGE
Lloh12:
	ldr	x8, [x8, _FUSE_SATA_CALIB_MASK@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
Lloh14:
	adrp	x20, _SCFG_OFFSET@GOTPAGE
Lloh15:
	ldr	x20, [x20, _SCFG_OFFSET@GOTPAGEOFF]
	and	w23, w8, w0
	ldr	x8, [x20]
Lloh16:
	adrp	x21, _T_SATA0_INDEX@GOTPAGE
Lloh17:
	ldr	x21, [x21, _T_SATA0_INDEX@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x1, x9, x8
	mov	x0, x19
	mov	w2, #1
	bl	_SATA_WR4
	ldr	x8, [x20]
Lloh18:
	adrp	x24, _T_SATA0_CHX_PHY_CTRL1_GEN1@GOTPAGE
Lloh19:
	ldr	x24, [x24, _T_SATA0_CHX_PHY_CTRL1_GEN1@GOTPAGEOFF]
	ldr	x9, [x24]
	add	x1, x9, x8
	mov	x0, x19
	bl	_SATA_RD4
Lloh20:
	adrp	x8, _T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK@GOTPAGE
Lloh21:
	ldr	x8, [x8, _T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
Lloh23:
	adrp	x9, _T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT@GOTPAGE
Lloh24:
	ldr	x9, [x9, _T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT@GOTPAGEOFF]
Lloh25:
	ldr	w9, [x9]
Lloh26:
	adrp	x10, _T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK@GOTPAGE
Lloh27:
	ldr	x10, [x10, _T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK@GOTPAGEOFF]
	lsl	w8, w8, w9
Lloh28:
	ldr	w10, [x10]
Lloh29:
	adrp	x11, _T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT@GOTPAGE
Lloh30:
	ldr	x11, [x11, _T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT@GOTPAGEOFF]
Lloh31:
	ldr	w11, [x11]
	lsl	w10, w10, w11
	orr	w8, w10, w8
	bic	w8, w0, w8
	add	x22, x22, w23, sxtw #4
	ldp	w10, w12, [x22]
	lsl	w9, w10, w9
	orr	w8, w8, w9
	lsl	w9, w12, w11
	orr	w2, w8, w9
	ldr	x8, [x20]
	ldr	x9, [x24]
	add	x1, x9, x8
	mov	x0, x19
	bl	_SATA_WR4
	ldr	x8, [x20]
Lloh32:
	adrp	x23, _T_SATA0_CHX_PHY_CTRL1_GEN2@GOTPAGE
Lloh33:
	ldr	x23, [x23, _T_SATA0_CHX_PHY_CTRL1_GEN2@GOTPAGEOFF]
	ldr	x9, [x23]
	add	x1, x9, x8
	mov	x0, x19
	bl	_SATA_RD4
Lloh34:
	adrp	x8, _T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK@GOTPAGE
Lloh35:
	ldr	x8, [x8, _T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK@GOTPAGEOFF]
Lloh36:
	ldr	w8, [x8]
Lloh37:
	adrp	x9, _T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT@GOTPAGE
Lloh38:
	ldr	x9, [x9, _T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT@GOTPAGEOFF]
Lloh39:
	ldr	w9, [x9]
	lsl	w8, w8, w9
Lloh40:
	adrp	x10, _T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK@GOTPAGE
Lloh41:
	ldr	x10, [x10, _T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK@GOTPAGEOFF]
Lloh42:
	ldr	w10, [x10]
Lloh43:
	adrp	x11, _T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT@GOTPAGE
Lloh44:
	ldr	x11, [x11, _T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT@GOTPAGEOFF]
Lloh45:
	ldr	w11, [x11]
	lsl	w10, w10, w11
	orr	w8, w10, w8
	bic	w8, w0, w8
	ldp	w10, w12, [x22, #8]
	lsl	w9, w10, w9
	orr	w8, w8, w9
	lsl	w9, w12, w11
	orr	w2, w8, w9
	ldr	x8, [x20]
	ldr	x9, [x23]
	add	x1, x9, x8
	mov	x0, x19
	bl	_SATA_WR4
Lloh46:
	adrp	x8, _T_SATA0_CHX_PHY_CTRL11@GOTPAGE
Lloh47:
	ldr	x8, [x8, _T_SATA0_CHX_PHY_CTRL11@GOTPAGEOFF]
	ldr	x9, [x20]
Lloh48:
	ldr	x8, [x8]
	add	x1, x8, x9
Lloh49:
	adrp	x8, _T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ@GOTPAGE
Lloh50:
	ldr	x8, [x8, _T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ@GOTPAGEOFF]
Lloh51:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_SATA_WR4
Lloh52:
	adrp	x8, _T_SATA0_CHX_PHY_CTRL2@GOTPAGE
Lloh53:
	ldr	x8, [x8, _T_SATA0_CHX_PHY_CTRL2@GOTPAGEOFF]
	ldr	x9, [x20]
Lloh54:
	ldr	x8, [x8]
	add	x1, x8, x9
Lloh55:
	adrp	x8, _T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1@GOTPAGE
Lloh56:
	ldr	x8, [x8, _T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1@GOTPAGEOFF]
Lloh57:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_SATA_WR4
	ldr	x8, [x20]
	ldr	x9, [x21]
	add	x1, x9, x8
	mov	x0, x19
	mov	w2, #0
	bl	_SATA_WR4
	ldr	x8, [x20]
Lloh58:
	adrp	x21, _T_SATA0_CFG_SATA@GOTPAGE
Lloh59:
	ldr	x21, [x21, _T_SATA0_CFG_SATA@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x1, x9, x8
	mov	x0, x19
	bl	_SATA_RD4
Lloh60:
	adrp	x22, _T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN@GOTPAGE
Lloh61:
	ldr	x22, [x22, _T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN@GOTPAGEOFF]
	ldr	w8, [x22]
	orr	w2, w8, w0
	ldr	x8, [x20]
	ldr	x9, [x21]
	add	x1, x9, x8
	mov	x0, x19
	bl	_SATA_WR4
	ldr	x8, [x20]
Lloh62:
	adrp	x9, _T_SATA0_BKDOOR_CC@GOTPAGE
Lloh63:
	ldr	x9, [x9, _T_SATA0_BKDOOR_CC@GOTPAGEOFF]
Lloh64:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	x0, x19
	mov	w2, #256
	movk	w2, #262, lsl #16
	bl	_SATA_WR4
	ldr	x8, [x20]
	ldr	x9, [x21]
	add	x1, x9, x8
	mov	x0, x19
	bl	_SATA_RD4
	ldr	w8, [x22]
	bic	w2, w0, w8
	ldr	x8, [x20]
	ldr	x9, [x21]
	add	x1, x9, x8
	mov	x0, x19
	bl	_SATA_WR4
	ldr	x8, [x20]
Lloh65:
	adrp	x21, _T_SATA0_CFG_1@GOTPAGE
Lloh66:
	ldr	x21, [x21, _T_SATA0_CFG_1@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x1, x9, x8
	mov	x0, x19
	bl	_SATA_RD4
Lloh67:
	adrp	x8, _T_SATA0_CFG_1_IO_SPACE@GOTPAGE
Lloh68:
	ldr	x8, [x8, _T_SATA0_CFG_1_IO_SPACE@GOTPAGEOFF]
Lloh69:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh70:
	adrp	x9, _T_SATA0_CFG_1_MEMORY_SPACE@GOTPAGE
Lloh71:
	ldr	x9, [x9, _T_SATA0_CFG_1_MEMORY_SPACE@GOTPAGEOFF]
Lloh72:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh73:
	adrp	x9, _T_SATA0_CFG_1_BUS_MASTER@GOTPAGE
Lloh74:
	ldr	x9, [x9, _T_SATA0_CFG_1_BUS_MASTER@GOTPAGEOFF]
Lloh75:
	ldr	w9, [x9]
Lloh76:
	adrp	x10, _T_SATA0_CFG_1_SERR@GOTPAGE
Lloh77:
	ldr	x10, [x10, _T_SATA0_CFG_1_SERR@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh78:
	ldr	w9, [x10]
	orr	w2, w8, w9
	ldr	x8, [x20]
	ldr	x9, [x21]
	add	x1, x9, x8
	mov	x0, x19
	bl	_SATA_WR4
Lloh79:
	adrp	x8, _SATA_FPCI_BAR5@GOTPAGE
Lloh80:
	ldr	x8, [x8, _SATA_FPCI_BAR5@GOTPAGEOFF]
Lloh81:
	ldr	x1, [x8]
Lloh82:
	adrp	x8, _SATA_FPCI_BAR5_START_SHIFT@GOTPAGE
Lloh83:
	ldr	x8, [x8, _SATA_FPCI_BAR5_START_SHIFT@GOTPAGEOFF]
Lloh84:
	ldr	w8, [x8]
	mov	w9, #65536
	lsl	w2, w9, w8
	mov	x0, x19
	bl	_SATA_WR4
	ldr	x8, [x20]
Lloh85:
	adrp	x9, _T_SATA0_CFG_9@GOTPAGE
Lloh86:
	ldr	x9, [x9, _T_SATA0_CFG_9@GOTPAGEOFF]
Lloh87:
	ldr	x9, [x9]
	add	x1, x9, x8
Lloh88:
	adrp	x8, _T_SATA0_CFG_9_BASE_ADDRESS_SHIFT@GOTPAGE
Lloh89:
	ldr	x8, [x8, _T_SATA0_CFG_9_BASE_ADDRESS_SHIFT@GOTPAGEOFF]
Lloh90:
	ldr	w8, [x8]
	mov	w9, #32768
	lsl	w2, w9, w8
	mov	x0, x19
	bl	_SATA_WR4
Lloh91:
	adrp	x20, _SATA_INTR_MASK@GOTPAGE
Lloh92:
	ldr	x20, [x20, _SATA_INTR_MASK@GOTPAGEOFF]
	ldr	x1, [x20]
	mov	x0, x19
	bl	_SATA_RD4
Lloh93:
	adrp	x8, _SATA_INTR_MASK_IP_INT_MASK@GOTPAGE
Lloh94:
	ldr	x8, [x8, _SATA_INTR_MASK_IP_INT_MASK@GOTPAGEOFF]
Lloh95:
	ldr	w8, [x8]
	orr	w2, w8, w0
	ldr	x1, [x20]
	mov	x0, x19
	bl	_SATA_WR4
	mov	w0, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGot	Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_SATA_CONFIGURATION,8,3         ; @SATA_CONFIGURATION
	.comm	_SATA_CONFIGURATION_EN_FPCI,4,2 ; @SATA_CONFIGURATION_EN_FPCI
	.comm	_FUSE_SATA_CALIB,4,2            ; @FUSE_SATA_CALIB
	.comm	_tegra124_pad_calibration,8,3   ; @tegra124_pad_calibration
	.comm	_FUSE_SATA_CALIB_MASK,4,2       ; @FUSE_SATA_CALIB_MASK
	.comm	_SCFG_OFFSET,8,3                ; @SCFG_OFFSET
	.comm	_T_SATA0_INDEX,8,3              ; @T_SATA0_INDEX
	.comm	_T_SATA0_CHX_PHY_CTRL1_GEN1,8,3 ; @T_SATA0_CHX_PHY_CTRL1_GEN1
	.comm	_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK,4,2 ; @T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK
	.comm	_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT,4,2 ; @T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT
	.comm	_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK,4,2 ; @T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK
	.comm	_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT,4,2 ; @T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT
	.comm	_T_SATA0_CHX_PHY_CTRL1_GEN2,8,3 ; @T_SATA0_CHX_PHY_CTRL1_GEN2
	.comm	_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK,4,2 ; @T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK
	.comm	_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT,4,2 ; @T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT
	.comm	_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK,4,2 ; @T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK
	.comm	_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT,4,2 ; @T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT
	.comm	_T_SATA0_CHX_PHY_CTRL11,8,3     ; @T_SATA0_CHX_PHY_CTRL11
	.comm	_T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,4,2 ; @T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ
	.comm	_T_SATA0_CHX_PHY_CTRL2,8,3      ; @T_SATA0_CHX_PHY_CTRL2
	.comm	_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,4,2 ; @T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1
	.comm	_T_SATA0_CFG_SATA,8,3           ; @T_SATA0_CFG_SATA
	.comm	_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN,4,2 ; @T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN
	.comm	_T_SATA0_BKDOOR_CC,8,3          ; @T_SATA0_BKDOOR_CC
	.comm	_T_SATA0_CFG_1,8,3              ; @T_SATA0_CFG_1
	.comm	_T_SATA0_CFG_1_IO_SPACE,4,2     ; @T_SATA0_CFG_1_IO_SPACE
	.comm	_T_SATA0_CFG_1_MEMORY_SPACE,4,2 ; @T_SATA0_CFG_1_MEMORY_SPACE
	.comm	_T_SATA0_CFG_1_BUS_MASTER,4,2   ; @T_SATA0_CFG_1_BUS_MASTER
	.comm	_T_SATA0_CFG_1_SERR,4,2         ; @T_SATA0_CFG_1_SERR
	.comm	_SATA_FPCI_BAR5,8,3             ; @SATA_FPCI_BAR5
	.comm	_SATA_FPCI_BAR5_START_SHIFT,4,2 ; @SATA_FPCI_BAR5_START_SHIFT
	.comm	_T_SATA0_CFG_9,8,3              ; @T_SATA0_CFG_9
	.comm	_T_SATA0_CFG_9_BASE_ADDRESS_SHIFT,4,2 ; @T_SATA0_CFG_9_BASE_ADDRESS_SHIFT
	.comm	_SATA_INTR_MASK,8,3             ; @SATA_INTR_MASK
	.comm	_SATA_INTR_MASK_IP_INT_MASK,4,2 ; @SATA_INTR_MASK_IP_INT_MASK
	.no_dead_strip	_tegra_ahci_ctrl_init
.subsections_via_symbols
