	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ipu_init_buffer
_ipu_init_buffer:                       ## @ipu_init_buffer
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	8(%rdi), %rax
	movq	_MODE_BPP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	imull	(%rax), %ecx
	leal	7(%rcx), %ebx
	testl	%ecx, %ecx
	cmovnsl	%ecx, %ebx
	sarl	$3, %ebx
	leaq	-48(%rbp), %r15
	movq	%r15, %rdi
	callq	_CH_PARAM_RESET
	movq	8(%r14), %rax
	movl	(%rax), %esi
	decl	%esi
	movq	%r15, %rdi
	callq	_CH_PARAM_SET_FW
	movq	8(%r14), %rax
	movq	8(%rax), %rsi
	decq	%rsi
	movq	%r15, %rdi
	callq	_CH_PARAM_SET_FH
	decl	%ebx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_CH_PARAM_SET_SLY
	movl	(%r14), %esi
	sarl	$3, %esi
	movq	%r15, %rdi
	callq	_CH_PARAM_SET_EBA0
	movl	(%r14), %esi
	sarl	$3, %esi
	movq	%r15, %rdi
	callq	_CH_PARAM_SET_EBA1
	movq	_IPU_PIX_FORMAT_BPP_16@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_CH_PARAM_SET_BPP
	movq	_IPU_PIX_FORMAT_RGB@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_CH_PARAM_SET_PFS
	movq	%r15, %rdi
	movl	$15, %esi
	callq	_CH_PARAM_SET_NPB
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_CH_PARAM_SET_RED_OFFSET
	movq	%r15, %rdi
	movl	$4, %esi
	callq	_CH_PARAM_SET_RED_WIDTH
	movq	%r15, %rdi
	movl	$5, %esi
	callq	_CH_PARAM_SET_GREEN_OFFSET
	movq	%r15, %rdi
	movl	$5, %esi
	callq	_CH_PARAM_SET_GREEN_WIDTH
	movq	%r15, %rdi
	movl	$11, %esi
	callq	_CH_PARAM_SET_BLUE_OFFSET
	movq	%r15, %rdi
	movl	$4, %esi
	callq	_CH_PARAM_SET_BLUE_WIDTH
	movq	%r15, %rdi
	movl	$16, %esi
	callq	_CH_PARAM_SET_ALPHA_OFFSET
	movq	%r15, %rdi
	movl	$7, %esi
	callq	_CH_PARAM_SET_ALPHA_WIDTH
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_CH_PARAM_SET_UBO
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_CH_PARAM_SET_VBO
	movq	_DMA_CHANNEL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movq	%r15, %rdx
	callq	_IPU_WRITE_CH_PARAM
	movq	_DMFC_IC_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DMFC_IC_CTRL_DISABLED@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r14, %rdi
	callq	_IPU_WRITE4
	movq	_DMFC_WR_CHAN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DMFC_WR_CHAN_BURST_SIZE_8@GOTPCREL(%rip), %rax
	movq	_DMFC_WR_CHAN_FIFO_SIZE_128@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rdx
	orq	(%rax), %rdx
	movq	%r14, %rdi
	callq	_IPU_WRITE4
	movq	_DMFC_WR_CHAN_DEF@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	$1, %edi
	callq	_DMFC_WR_CHAN_DEF_WM_CLR_2C
	movq	%rax, %r12
	movl	$1, %edi
	callq	_DMFC_WR_CHAN_DEF_WM_CLR_1C
	orq	%rax, %r12
	movl	$1, %edi
	callq	_DMFC_WR_CHAN_DEF_WM_CLR_2
	movq	%rax, %rbx
	movl	$7, %edi
	callq	_DMFC_WR_CHAN_DEF_WM_CLR_1
	orq	%rax, %rbx
	orq	%r12, %rbx
	movl	$5, %edi
	callq	_DMFC_WR_CHAN_DEF_WM_SET_1
	orq	%rax, %rbx
	movq	_DMFC_WR_CHAN_DEF_WM_EN_1@GOTPCREL(%rip), %rax
	orq	(%rax), %rbx
	movq	%r14, %rdi
	movl	%r15d, %esi
	movq	%rbx, %rdx
	callq	_IPU_WRITE4
	movq	_DMFC_DP_CHAN@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_DMFC_DP_CHAN_BURST_SIZE_8@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_DMFC_DP_CHAN_BURST_SIZE_5F
	movq	%rax, %r12
	movq	_DMFC_DP_CHAN_FIFO_SIZE_128@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_DMFC_DP_CHAN_FIFO_SIZE_5F
	orq	%rax, %r12
	movl	$6, %edi
	callq	_DMFC_DP_CHAN_ST_ADDR_SIZE_5F
	movq	%rax, %r13
	movl	(%rbx), %edi
	callq	_DMFC_DP_CHAN_BURST_SIZE_5B
	orq	%rax, %r13
	orq	%r12, %r13
	movq	_DMFC_DP_CHAN_FIFO_SIZE_256@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_DMFC_DP_CHAN_FIFO_SIZE_5B
	movq	%rax, %rbx
	movl	$2, %edi
	callq	_DMFC_DP_CHAN_ST_ADDR_SIZE_5B
	orq	%rax, %rbx
	orq	%r13, %rbx
	movq	%r14, %rdi
	movl	%r15d, %esi
	movq	%rbx, %rdx
	callq	_IPU_WRITE4
	movq	_DMFC_DP_CHAN_DEF@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	$1, %edi
	callq	_DMFC_DP_CHAN_DEF_WM_CLR_6F
	movq	%rax, %r12
	movl	$1, %edi
	callq	_DMFC_DP_CHAN_DEF_WM_CLR_6B
	orq	%rax, %r12
	movl	$7, %edi
	callq	_DMFC_DP_CHAN_DEF_WM_CLR_5F
	movq	%rax, %r13
	movl	$5, %edi
	callq	_DMFC_DP_CHAN_DEF_WM_SET_5F
	orq	%rax, %r13
	orq	%r12, %r13
	movq	_DMFC_DP_CHAN_DEF_WM_EN_5F@GOTPCREL(%rip), %rax
	orq	(%rax), %r13
	movl	$7, %edi
	callq	_DMFC_DP_CHAN_DEF_WM_CLR_5B
	movq	%rax, %rbx
	movl	$5, %edi
	callq	_DMFC_DP_CHAN_DEF_WM_SET_5B
	orq	%rax, %rbx
	orq	%r13, %rbx
	movq	_DMFC_DP_CHAN_DEF_WM_EN_5B@GOTPCREL(%rip), %rax
	orq	(%rax), %rbx
	movq	%r14, %rdi
	movl	%r15d, %esi
	movq	%rbx, %rdx
	callq	_IPU_WRITE4
	movq	_DMFC_GENERAL_1@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_IPU_READ4
	movq	_DMFC_GENERAL_1_WAIT4EOT_5B@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movl	(%rbx), %esi
	movslq	%ecx, %rdx
	movq	%r14, %rdi
	callq	_IPU_WRITE4
	movq	_DMA_CHANNEL@GOTPCREL(%rip), %r12
	cmpl	$32, (%r12)
	movq	_IPU_CUR_BUF_1@GOTPCREL(%rip), %rax
	cmovlq	_IPU_CUR_BUF_0@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_IPU_CH_DB_MODE_SEL_1@GOTPCREL(%rip), %rax
	cmovlq	_IPU_CH_DB_MODE_SEL_0@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_IPU_READ4
	movb	(%r12), %cl
	btsl	%ecx, %eax
	movslq	%eax, %rdx
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_IPU_WRITE4
	movb	(%r12), %cl
	andb	$31, %cl
	movl	$1, %edx
	shlq	%cl, %rdx
	movq	%r14, %rdi
	movl	%r15d, %esi
	callq	_IPU_WRITE4
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MODE_BPP,4,2                   ## @MODE_BPP
	.comm	_IPU_PIX_FORMAT_BPP_16,4,2      ## @IPU_PIX_FORMAT_BPP_16
	.comm	_IPU_PIX_FORMAT_RGB,4,2         ## @IPU_PIX_FORMAT_RGB
	.comm	_DMA_CHANNEL,4,2                ## @DMA_CHANNEL
	.comm	_DMFC_IC_CTRL,4,2               ## @DMFC_IC_CTRL
	.comm	_DMFC_IC_CTRL_DISABLED,8,3      ## @DMFC_IC_CTRL_DISABLED
	.comm	_DMFC_WR_CHAN,4,2               ## @DMFC_WR_CHAN
	.comm	_DMFC_WR_CHAN_BURST_SIZE_8,8,3  ## @DMFC_WR_CHAN_BURST_SIZE_8
	.comm	_DMFC_WR_CHAN_FIFO_SIZE_128,8,3 ## @DMFC_WR_CHAN_FIFO_SIZE_128
	.comm	_DMFC_WR_CHAN_DEF,4,2           ## @DMFC_WR_CHAN_DEF
	.comm	_DMFC_WR_CHAN_DEF_WM_EN_1,8,3   ## @DMFC_WR_CHAN_DEF_WM_EN_1
	.comm	_DMFC_DP_CHAN,4,2               ## @DMFC_DP_CHAN
	.comm	_DMFC_DP_CHAN_BURST_SIZE_8,4,2  ## @DMFC_DP_CHAN_BURST_SIZE_8
	.comm	_DMFC_DP_CHAN_FIFO_SIZE_128,4,2 ## @DMFC_DP_CHAN_FIFO_SIZE_128
	.comm	_DMFC_DP_CHAN_FIFO_SIZE_256,4,2 ## @DMFC_DP_CHAN_FIFO_SIZE_256
	.comm	_DMFC_DP_CHAN_DEF,4,2           ## @DMFC_DP_CHAN_DEF
	.comm	_DMFC_DP_CHAN_DEF_WM_EN_5F,8,3  ## @DMFC_DP_CHAN_DEF_WM_EN_5F
	.comm	_DMFC_DP_CHAN_DEF_WM_EN_5B,8,3  ## @DMFC_DP_CHAN_DEF_WM_EN_5B
	.comm	_DMFC_GENERAL_1,4,2             ## @DMFC_GENERAL_1
	.comm	_DMFC_GENERAL_1_WAIT4EOT_5B,4,2 ## @DMFC_GENERAL_1_WAIT4EOT_5B
	.comm	_IPU_CH_DB_MODE_SEL_0,4,2       ## @IPU_CH_DB_MODE_SEL_0
	.comm	_IPU_CUR_BUF_0,4,2              ## @IPU_CUR_BUF_0
	.comm	_IPU_CH_DB_MODE_SEL_1,4,2       ## @IPU_CH_DB_MODE_SEL_1
	.comm	_IPU_CUR_BUF_1,4,2              ## @IPU_CUR_BUF_1
	.no_dead_strip	_ipu_init_buffer
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ipu_init_buffer
_ipu_init_buffer:                       ; @ipu_init_buffer
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	x8, [x0, #8]
	ldr	w8, [x8]
Lloh0:
	adrp	x9, _MODE_BPP@GOTPAGE
Lloh1:
	ldr	x9, [x9, _MODE_BPP@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	mul	w8, w9, w8
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w20, w8, #3
	add	x0, sp, #8
	bl	_CH_PARAM_RESET
	ldr	x8, [x19, #8]
	ldr	w8, [x8]
	sub	w1, w8, #1
	add	x0, sp, #8
	bl	_CH_PARAM_SET_FW
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	sub	x1, x8, #1
	add	x0, sp, #8
	bl	_CH_PARAM_SET_FH
	sub	w1, w20, #1
	add	x0, sp, #8
	bl	_CH_PARAM_SET_SLY
	ldr	w8, [x19]
	asr	w1, w8, #3
	add	x0, sp, #8
	bl	_CH_PARAM_SET_EBA0
	ldr	w8, [x19]
	asr	w1, w8, #3
	add	x0, sp, #8
	bl	_CH_PARAM_SET_EBA1
Lloh3:
	adrp	x8, _IPU_PIX_FORMAT_BPP_16@GOTPAGE
Lloh4:
	ldr	x8, [x8, _IPU_PIX_FORMAT_BPP_16@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	add	x0, sp, #8
	bl	_CH_PARAM_SET_BPP
Lloh6:
	adrp	x8, _IPU_PIX_FORMAT_RGB@GOTPAGE
Lloh7:
	ldr	x8, [x8, _IPU_PIX_FORMAT_RGB@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	add	x0, sp, #8
	bl	_CH_PARAM_SET_PFS
	add	x0, sp, #8
	mov	w1, #15
	bl	_CH_PARAM_SET_NPB
	add	x0, sp, #8
	mov	w1, #0
	bl	_CH_PARAM_SET_RED_OFFSET
	add	x0, sp, #8
	mov	w1, #4
	bl	_CH_PARAM_SET_RED_WIDTH
	add	x0, sp, #8
	mov	w1, #5
	bl	_CH_PARAM_SET_GREEN_OFFSET
	add	x0, sp, #8
	mov	w1, #5
	bl	_CH_PARAM_SET_GREEN_WIDTH
	add	x0, sp, #8
	mov	w1, #11
	bl	_CH_PARAM_SET_BLUE_OFFSET
	add	x0, sp, #8
	mov	w1, #4
	bl	_CH_PARAM_SET_BLUE_WIDTH
	add	x0, sp, #8
	mov	w1, #16
	bl	_CH_PARAM_SET_ALPHA_OFFSET
	add	x0, sp, #8
	mov	w1, #7
	bl	_CH_PARAM_SET_ALPHA_WIDTH
	add	x0, sp, #8
	mov	w1, #0
	bl	_CH_PARAM_SET_UBO
	add	x0, sp, #8
	mov	w1, #0
	bl	_CH_PARAM_SET_VBO
Lloh9:
	adrp	x22, _DMA_CHANNEL@GOTPAGE
Lloh10:
	ldr	x22, [x22, _DMA_CHANNEL@GOTPAGEOFF]
	ldr	w1, [x22]
	add	x2, sp, #8
	mov	x0, x19
	bl	_IPU_WRITE_CH_PARAM
Lloh11:
	adrp	x8, _DMFC_IC_CTRL@GOTPAGE
Lloh12:
	ldr	x8, [x8, _DMFC_IC_CTRL@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
Lloh14:
	adrp	x8, _DMFC_IC_CTRL_DISABLED@GOTPAGE
Lloh15:
	ldr	x8, [x8, _DMFC_IC_CTRL_DISABLED@GOTPAGEOFF]
Lloh16:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_IPU_WRITE4
Lloh17:
	adrp	x8, _DMFC_WR_CHAN@GOTPAGE
Lloh18:
	ldr	x8, [x8, _DMFC_WR_CHAN@GOTPAGEOFF]
Lloh19:
	adrp	x9, _DMFC_WR_CHAN_BURST_SIZE_8@GOTPAGE
Lloh20:
	ldr	x9, [x9, _DMFC_WR_CHAN_BURST_SIZE_8@GOTPAGEOFF]
Lloh21:
	ldr	w1, [x8]
Lloh22:
	ldr	x8, [x9]
Lloh23:
	adrp	x9, _DMFC_WR_CHAN_FIFO_SIZE_128@GOTPAGE
Lloh24:
	ldr	x9, [x9, _DMFC_WR_CHAN_FIFO_SIZE_128@GOTPAGEOFF]
Lloh25:
	ldr	x9, [x9]
	orr	x2, x9, x8
	mov	x0, x19
	bl	_IPU_WRITE4
Lloh26:
	adrp	x8, _DMFC_WR_CHAN_DEF@GOTPAGE
Lloh27:
	ldr	x8, [x8, _DMFC_WR_CHAN_DEF@GOTPAGEOFF]
Lloh28:
	ldr	w20, [x8]
	mov	w23, #1
	mov	w0, #1
	bl	_DMFC_WR_CHAN_DEF_WM_CLR_2C
	mov	x21, x0
	mov	w0, #1
	bl	_DMFC_WR_CHAN_DEF_WM_CLR_1C
	orr	x21, x0, x21
	mov	w0, #1
	bl	_DMFC_WR_CHAN_DEF_WM_CLR_2
	orr	x21, x21, x0
	mov	w0, #7
	bl	_DMFC_WR_CHAN_DEF_WM_CLR_1
	orr	x21, x21, x0
	mov	w0, #5
	bl	_DMFC_WR_CHAN_DEF_WM_SET_1
	orr	x8, x21, x0
Lloh29:
	adrp	x9, _DMFC_WR_CHAN_DEF_WM_EN_1@GOTPAGE
Lloh30:
	ldr	x9, [x9, _DMFC_WR_CHAN_DEF_WM_EN_1@GOTPAGEOFF]
Lloh31:
	ldr	x9, [x9]
	orr	x2, x8, x9
	mov	x0, x19
	mov	x1, x20
	bl	_IPU_WRITE4
Lloh32:
	adrp	x8, _DMFC_DP_CHAN@GOTPAGE
Lloh33:
	ldr	x8, [x8, _DMFC_DP_CHAN@GOTPAGEOFF]
Lloh34:
	ldr	w20, [x8]
Lloh35:
	adrp	x24, _DMFC_DP_CHAN_BURST_SIZE_8@GOTPAGE
Lloh36:
	ldr	x24, [x24, _DMFC_DP_CHAN_BURST_SIZE_8@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_DMFC_DP_CHAN_BURST_SIZE_5F
	mov	x21, x0
Lloh37:
	adrp	x8, _DMFC_DP_CHAN_FIFO_SIZE_128@GOTPAGE
Lloh38:
	ldr	x8, [x8, _DMFC_DP_CHAN_FIFO_SIZE_128@GOTPAGEOFF]
Lloh39:
	ldr	w0, [x8]
	bl	_DMFC_DP_CHAN_FIFO_SIZE_5F
	orr	x21, x0, x21
	mov	w0, #6
	bl	_DMFC_DP_CHAN_ST_ADDR_SIZE_5F
	orr	x21, x21, x0
	ldr	w0, [x24]
	bl	_DMFC_DP_CHAN_BURST_SIZE_5B
	orr	x21, x21, x0
Lloh40:
	adrp	x8, _DMFC_DP_CHAN_FIFO_SIZE_256@GOTPAGE
Lloh41:
	ldr	x8, [x8, _DMFC_DP_CHAN_FIFO_SIZE_256@GOTPAGEOFF]
Lloh42:
	ldr	w0, [x8]
	bl	_DMFC_DP_CHAN_FIFO_SIZE_5B
	orr	x21, x21, x0
	mov	w0, #2
	bl	_DMFC_DP_CHAN_ST_ADDR_SIZE_5B
	orr	x2, x21, x0
	mov	x0, x19
	mov	x1, x20
	bl	_IPU_WRITE4
Lloh43:
	adrp	x8, _DMFC_DP_CHAN_DEF@GOTPAGE
Lloh44:
	ldr	x8, [x8, _DMFC_DP_CHAN_DEF@GOTPAGEOFF]
Lloh45:
	ldr	w20, [x8]
	mov	w0, #1
	bl	_DMFC_DP_CHAN_DEF_WM_CLR_6F
	mov	x21, x0
	mov	w0, #1
	bl	_DMFC_DP_CHAN_DEF_WM_CLR_6B
	orr	x21, x0, x21
	mov	w0, #7
	bl	_DMFC_DP_CHAN_DEF_WM_CLR_5F
	orr	x21, x21, x0
	mov	w0, #5
	bl	_DMFC_DP_CHAN_DEF_WM_SET_5F
	orr	x8, x21, x0
Lloh46:
	adrp	x9, _DMFC_DP_CHAN_DEF_WM_EN_5F@GOTPAGE
Lloh47:
	ldr	x9, [x9, _DMFC_DP_CHAN_DEF_WM_EN_5F@GOTPAGEOFF]
Lloh48:
	ldr	x9, [x9]
	orr	x21, x8, x9
	mov	w0, #7
	bl	_DMFC_DP_CHAN_DEF_WM_CLR_5B
	orr	x21, x21, x0
	mov	w0, #5
	bl	_DMFC_DP_CHAN_DEF_WM_SET_5B
	orr	x8, x21, x0
Lloh49:
	adrp	x9, _DMFC_DP_CHAN_DEF_WM_EN_5B@GOTPAGE
Lloh50:
	ldr	x9, [x9, _DMFC_DP_CHAN_DEF_WM_EN_5B@GOTPAGEOFF]
Lloh51:
	ldr	x9, [x9]
	orr	x2, x8, x9
	mov	x0, x19
	mov	x1, x20
	bl	_IPU_WRITE4
Lloh52:
	adrp	x20, _DMFC_GENERAL_1@GOTPAGE
Lloh53:
	ldr	x20, [x20, _DMFC_GENERAL_1@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_IPU_READ4
Lloh54:
	adrp	x8, _DMFC_GENERAL_1_WAIT4EOT_5B@GOTPAGE
Lloh55:
	ldr	x8, [x8, _DMFC_GENERAL_1_WAIT4EOT_5B@GOTPAGEOFF]
Lloh56:
	ldr	w8, [x8]
	bic	w8, w0, w8
	ldr	w1, [x20]
	sxtw	x2, w8
	mov	x0, x19
	bl	_IPU_WRITE4
Lloh57:
	adrp	x8, _IPU_CUR_BUF_0@GOTPAGE
Lloh58:
	ldr	x8, [x8, _IPU_CUR_BUF_0@GOTPAGEOFF]
	ldr	w9, [x22]
Lloh59:
	adrp	x10, _IPU_CUR_BUF_1@GOTPAGE
Lloh60:
	ldr	x10, [x10, _IPU_CUR_BUF_1@GOTPAGEOFF]
	cmp	w9, #32
	csel	x8, x8, x10, lt
	ldr	w20, [x8]
Lloh61:
	adrp	x8, _IPU_CH_DB_MODE_SEL_0@GOTPAGE
Lloh62:
	ldr	x8, [x8, _IPU_CH_DB_MODE_SEL_0@GOTPAGEOFF]
Lloh63:
	adrp	x9, _IPU_CH_DB_MODE_SEL_1@GOTPAGE
Lloh64:
	ldr	x9, [x9, _IPU_CH_DB_MODE_SEL_1@GOTPAGEOFF]
	csel	x8, x8, x9, lt
	ldr	w21, [x8]
	mov	x0, x19
	mov	x1, x21
	bl	_IPU_READ4
	ldr	w8, [x22]
	lsl	w8, w23, w8
	orr	w8, w8, w0
	sxtw	x2, w8
	mov	x0, x19
	mov	x1, x21
	bl	_IPU_WRITE4
	ldr	w8, [x22]
	and	x8, x8, #0x1f
	lsl	x2, x23, x8
	mov	x0, x19
	mov	x1, x20
	bl	_IPU_WRITE4
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGot	Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpLdrGot	Lloh59, Lloh60
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh21
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_MODE_BPP,4,2                   ; @MODE_BPP
	.comm	_IPU_PIX_FORMAT_BPP_16,4,2      ; @IPU_PIX_FORMAT_BPP_16
	.comm	_IPU_PIX_FORMAT_RGB,4,2         ; @IPU_PIX_FORMAT_RGB
	.comm	_DMA_CHANNEL,4,2                ; @DMA_CHANNEL
	.comm	_DMFC_IC_CTRL,4,2               ; @DMFC_IC_CTRL
	.comm	_DMFC_IC_CTRL_DISABLED,8,3      ; @DMFC_IC_CTRL_DISABLED
	.comm	_DMFC_WR_CHAN,4,2               ; @DMFC_WR_CHAN
	.comm	_DMFC_WR_CHAN_BURST_SIZE_8,8,3  ; @DMFC_WR_CHAN_BURST_SIZE_8
	.comm	_DMFC_WR_CHAN_FIFO_SIZE_128,8,3 ; @DMFC_WR_CHAN_FIFO_SIZE_128
	.comm	_DMFC_WR_CHAN_DEF,4,2           ; @DMFC_WR_CHAN_DEF
	.comm	_DMFC_WR_CHAN_DEF_WM_EN_1,8,3   ; @DMFC_WR_CHAN_DEF_WM_EN_1
	.comm	_DMFC_DP_CHAN,4,2               ; @DMFC_DP_CHAN
	.comm	_DMFC_DP_CHAN_BURST_SIZE_8,4,2  ; @DMFC_DP_CHAN_BURST_SIZE_8
	.comm	_DMFC_DP_CHAN_FIFO_SIZE_128,4,2 ; @DMFC_DP_CHAN_FIFO_SIZE_128
	.comm	_DMFC_DP_CHAN_FIFO_SIZE_256,4,2 ; @DMFC_DP_CHAN_FIFO_SIZE_256
	.comm	_DMFC_DP_CHAN_DEF,4,2           ; @DMFC_DP_CHAN_DEF
	.comm	_DMFC_DP_CHAN_DEF_WM_EN_5F,8,3  ; @DMFC_DP_CHAN_DEF_WM_EN_5F
	.comm	_DMFC_DP_CHAN_DEF_WM_EN_5B,8,3  ; @DMFC_DP_CHAN_DEF_WM_EN_5B
	.comm	_DMFC_GENERAL_1,4,2             ; @DMFC_GENERAL_1
	.comm	_DMFC_GENERAL_1_WAIT4EOT_5B,4,2 ; @DMFC_GENERAL_1_WAIT4EOT_5B
	.comm	_IPU_CH_DB_MODE_SEL_0,4,2       ; @IPU_CH_DB_MODE_SEL_0
	.comm	_IPU_CUR_BUF_0,4,2              ; @IPU_CUR_BUF_0
	.comm	_IPU_CH_DB_MODE_SEL_1,4,2       ; @IPU_CH_DB_MODE_SEL_1
	.comm	_IPU_CUR_BUF_1,4,2              ; @IPU_CUR_BUF_1
	.no_dead_strip	_ipu_init_buffer
.subsections_via_symbols
