	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_pcib_enable_fdt_resources
_tegra_pcib_enable_fdt_resources:       ## @tegra_pcib_enable_fdt_resources
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movl	56(%rdi), %edi
	callq	_hwreset_assert
	testl	%eax, %eax
	je	LBB0_2
## %bb.1:
	movl	%eax, %ebx
	leaq	L_.str(%rip), %rsi
	jmp	LBB0_30
LBB0_2:
	movl	16(%r14), %edi
	callq	_hwreset_assert
	testl	%eax, %eax
	je	LBB0_4
## %bb.3:
	movl	%eax, %ebx
	leaq	L_.str.1(%rip), %rsi
	jmp	LBB0_30
LBB0_4:
	movl	20(%r14), %edi
	callq	_hwreset_assert
	testl	%eax, %eax
	je	LBB0_6
## %bb.5:
	movl	%eax, %ebx
	leaq	L_.str.2(%rip), %rsi
	jmp	LBB0_30
LBB0_6:
	movq	_TEGRA_POWERGATE_PCX@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_tegra_powergate_power_off
	movl	52(%r14), %edi
	callq	_regulator_enable
	testl	%eax, %eax
	je	LBB0_8
## %bb.7:
	movl	%eax, %ebx
	leaq	L_.str.3(%rip), %rsi
	jmp	LBB0_30
LBB0_8:
	movl	48(%r14), %edi
	callq	_regulator_enable
	testl	%eax, %eax
	je	LBB0_10
## %bb.9:
	movl	%eax, %ebx
	leaq	L_.str.4(%rip), %rsi
	jmp	LBB0_30
LBB0_10:
	movl	44(%r14), %edi
	callq	_regulator_enable
	testl	%eax, %eax
	je	LBB0_12
## %bb.11:
	movl	%eax, %ebx
	leaq	L_.str.5(%rip), %rsi
	jmp	LBB0_30
LBB0_12:
	movl	40(%r14), %edi
	callq	_regulator_enable
	testl	%eax, %eax
	je	LBB0_14
## %bb.13:
	movl	%eax, %ebx
	leaq	L_.str.6(%rip), %rsi
	jmp	LBB0_30
LBB0_14:
	movl	36(%r14), %edi
	callq	_regulator_enable
	testl	%eax, %eax
	je	LBB0_16
## %bb.15:
	movl	%eax, %ebx
	leaq	L_.str.7(%rip), %rsi
	jmp	LBB0_30
LBB0_16:
	movl	32(%r14), %edi
	callq	_regulator_enable
	testl	%eax, %eax
	je	LBB0_18
## %bb.17:
	movl	%eax, %ebx
	leaq	L_.str.8(%rip), %rsi
	jmp	LBB0_30
LBB0_18:
	movl	28(%r14), %edi
	callq	_regulator_enable
	testl	%eax, %eax
	je	LBB0_20
## %bb.19:
	movl	%eax, %ebx
	leaq	L_.str.9(%rip), %rsi
	jmp	LBB0_30
LBB0_20:
	movl	(%r15), %edi
	movl	20(%r14), %edx
	movl	24(%r14), %esi
	callq	_tegra_powergate_sequence_power_up
	testl	%eax, %eax
	je	LBB0_22
## %bb.21:
	movl	%eax, %ebx
	leaq	L_.str.10(%rip), %rsi
	jmp	LBB0_30
LBB0_22:
	movl	16(%r14), %edi
	callq	_hwreset_deassert
	testl	%eax, %eax
	je	LBB0_24
## %bb.23:
	movl	%eax, %ebx
	leaq	L_.str.11(%rip), %rsi
	jmp	LBB0_30
LBB0_24:
	movl	12(%r14), %edi
	callq	_clk_enable
	testl	%eax, %eax
	je	LBB0_26
## %bb.25:
	movl	%eax, %ebx
	leaq	L_.str.12(%rip), %rsi
	jmp	LBB0_30
LBB0_26:
	movl	8(%r14), %edi
	callq	_clk_enable
	testl	%eax, %eax
	je	LBB0_28
## %bb.27:
	movl	%eax, %ebx
	leaq	L_.str.13(%rip), %rsi
	jmp	LBB0_30
LBB0_28:
	movl	4(%r14), %edi
	callq	_clk_enable
	testl	%eax, %eax
	je	LBB0_32
## %bb.29:
	movl	%eax, %ebx
	leaq	L_.str.14(%rip), %rsi
LBB0_30:
	movl	(%r14), %edi
	callq	_device_printf
LBB0_31:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_32:
	xorl	%ebx, %ebx
	jmp	LBB0_31
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Cannot assert 'pcie_x' reset\n"

L_.str.1:                               ## @.str.1
	.asciz	"Cannot assert  'afi' reset\n"

L_.str.2:                               ## @.str.2
	.asciz	"Cannot assert  'pex' reset\n"

	.comm	_TEGRA_POWERGATE_PCX,4,2        ## @TEGRA_POWERGATE_PCX
L_.str.3:                               ## @.str.3
	.asciz	"Cannot enable 'avddio_pex' regulator\n"

L_.str.4:                               ## @.str.4
	.asciz	"Cannot enable 'dvddio_pex' regulator\n"

L_.str.5:                               ## @.str.5
	.asciz	"Cannot enable 'avdd-pex-pll' regulator\n"

L_.str.6:                               ## @.str.6
	.asciz	"Cannot enable 'hvdd-pex-supply' regulator\n"

L_.str.7:                               ## @.str.7
	.asciz	"Cannot enable 'hvdd-pex-pll-e-supply' regulator\n"

L_.str.8:                               ## @.str.8
	.asciz	"Cannot enable 'vddio-pex-ctl' regulator\n"

L_.str.9:                               ## @.str.9
	.asciz	"Cannot enable 'avdd-pll-erefe-supply' regulator\n"

L_.str.10:                              ## @.str.10
	.asciz	"Cannot enable 'PCX' powergate\n"

L_.str.11:                              ## @.str.11
	.asciz	"Cannot unreset 'afi' reset\n"

L_.str.12:                              ## @.str.12
	.asciz	"Cannot enable 'afi' clock\n"

L_.str.13:                              ## @.str.13
	.asciz	"Cannot enable 'cml' clock\n"

L_.str.14:                              ## @.str.14
	.asciz	"Cannot enable 'pll_e' clock\n"

	.no_dead_strip	_tegra_pcib_enable_fdt_resources
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_pcib_enable_fdt_resources
_tegra_pcib_enable_fdt_resources:       ; @tegra_pcib_enable_fdt_resources
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	w0, [x0, #56]
	bl	_hwreset_assert
	cbz	w0, LBB0_2
; %bb.1:
	mov	x20, x0
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	b	LBB0_30
LBB0_2:
	ldr	w0, [x19, #16]
	bl	_hwreset_assert
	cbz	w0, LBB0_4
; %bb.3:
	mov	x20, x0
Lloh2:
	adrp	x1, l_.str.1@PAGE
Lloh3:
	add	x1, x1, l_.str.1@PAGEOFF
	b	LBB0_30
LBB0_4:
	ldr	w0, [x19, #20]
	bl	_hwreset_assert
	cbz	w0, LBB0_6
; %bb.5:
	mov	x20, x0
Lloh4:
	adrp	x1, l_.str.2@PAGE
Lloh5:
	add	x1, x1, l_.str.2@PAGEOFF
	b	LBB0_30
LBB0_6:
Lloh6:
	adrp	x21, _TEGRA_POWERGATE_PCX@GOTPAGE
Lloh7:
	ldr	x21, [x21, _TEGRA_POWERGATE_PCX@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_tegra_powergate_power_off
	ldr	w0, [x19, #52]
	bl	_regulator_enable
	cbz	w0, LBB0_8
; %bb.7:
	mov	x20, x0
Lloh8:
	adrp	x1, l_.str.3@PAGE
Lloh9:
	add	x1, x1, l_.str.3@PAGEOFF
	b	LBB0_30
LBB0_8:
	ldr	w0, [x19, #48]
	bl	_regulator_enable
	cbz	w0, LBB0_10
; %bb.9:
	mov	x20, x0
Lloh10:
	adrp	x1, l_.str.4@PAGE
Lloh11:
	add	x1, x1, l_.str.4@PAGEOFF
	b	LBB0_30
LBB0_10:
	ldr	w0, [x19, #44]
	bl	_regulator_enable
	cbz	w0, LBB0_12
; %bb.11:
	mov	x20, x0
Lloh12:
	adrp	x1, l_.str.5@PAGE
Lloh13:
	add	x1, x1, l_.str.5@PAGEOFF
	b	LBB0_30
LBB0_12:
	ldr	w0, [x19, #40]
	bl	_regulator_enable
	cbz	w0, LBB0_14
; %bb.13:
	mov	x20, x0
Lloh14:
	adrp	x1, l_.str.6@PAGE
Lloh15:
	add	x1, x1, l_.str.6@PAGEOFF
	b	LBB0_30
LBB0_14:
	ldr	w0, [x19, #36]
	bl	_regulator_enable
	cbz	w0, LBB0_16
; %bb.15:
	mov	x20, x0
Lloh16:
	adrp	x1, l_.str.7@PAGE
Lloh17:
	add	x1, x1, l_.str.7@PAGEOFF
	b	LBB0_30
LBB0_16:
	ldr	w0, [x19, #32]
	bl	_regulator_enable
	cbz	w0, LBB0_18
; %bb.17:
	mov	x20, x0
Lloh18:
	adrp	x1, l_.str.8@PAGE
Lloh19:
	add	x1, x1, l_.str.8@PAGEOFF
	b	LBB0_30
LBB0_18:
	ldr	w0, [x19, #28]
	bl	_regulator_enable
	cbz	w0, LBB0_20
; %bb.19:
	mov	x20, x0
Lloh20:
	adrp	x1, l_.str.9@PAGE
Lloh21:
	add	x1, x1, l_.str.9@PAGEOFF
	b	LBB0_30
LBB0_20:
	ldr	w0, [x21]
	ldp	w2, w1, [x19, #20]
	bl	_tegra_powergate_sequence_power_up
	cbz	w0, LBB0_22
; %bb.21:
	mov	x20, x0
Lloh22:
	adrp	x1, l_.str.10@PAGE
Lloh23:
	add	x1, x1, l_.str.10@PAGEOFF
	b	LBB0_30
LBB0_22:
	ldr	w0, [x19, #16]
	bl	_hwreset_deassert
	cbz	w0, LBB0_24
; %bb.23:
	mov	x20, x0
Lloh24:
	adrp	x1, l_.str.11@PAGE
Lloh25:
	add	x1, x1, l_.str.11@PAGEOFF
	b	LBB0_30
LBB0_24:
	ldr	w0, [x19, #12]
	bl	_clk_enable
	cbz	w0, LBB0_26
; %bb.25:
	mov	x20, x0
Lloh26:
	adrp	x1, l_.str.12@PAGE
Lloh27:
	add	x1, x1, l_.str.12@PAGEOFF
	b	LBB0_30
LBB0_26:
	ldr	w0, [x19, #8]
	bl	_clk_enable
	cbz	w0, LBB0_28
; %bb.27:
	mov	x20, x0
Lloh28:
	adrp	x1, l_.str.13@PAGE
Lloh29:
	add	x1, x1, l_.str.13@PAGEOFF
	b	LBB0_30
LBB0_28:
	ldr	w0, [x19, #4]
	bl	_clk_enable
	mov	x20, x0
	cbz	w0, LBB0_31
; %bb.29:
Lloh30:
	adrp	x1, l_.str.14@PAGE
Lloh31:
	add	x1, x1, l_.str.14@PAGEOFF
LBB0_30:
	ldr	w0, [x19]
	bl	_device_printf
LBB0_31:
	mov	x0, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpAdd	Lloh12, Lloh13
	.loh AdrpAdd	Lloh14, Lloh15
	.loh AdrpAdd	Lloh16, Lloh17
	.loh AdrpAdd	Lloh18, Lloh19
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpAdd	Lloh22, Lloh23
	.loh AdrpAdd	Lloh24, Lloh25
	.loh AdrpAdd	Lloh26, Lloh27
	.loh AdrpAdd	Lloh28, Lloh29
	.loh AdrpAdd	Lloh30, Lloh31
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Cannot assert 'pcie_x' reset\n"

l_.str.1:                               ; @.str.1
	.asciz	"Cannot assert  'afi' reset\n"

l_.str.2:                               ; @.str.2
	.asciz	"Cannot assert  'pex' reset\n"

	.comm	_TEGRA_POWERGATE_PCX,4,2        ; @TEGRA_POWERGATE_PCX
l_.str.3:                               ; @.str.3
	.asciz	"Cannot enable 'avddio_pex' regulator\n"

l_.str.4:                               ; @.str.4
	.asciz	"Cannot enable 'dvddio_pex' regulator\n"

l_.str.5:                               ; @.str.5
	.asciz	"Cannot enable 'avdd-pex-pll' regulator\n"

l_.str.6:                               ; @.str.6
	.asciz	"Cannot enable 'hvdd-pex-supply' regulator\n"

l_.str.7:                               ; @.str.7
	.asciz	"Cannot enable 'hvdd-pex-pll-e-supply' regulator\n"

l_.str.8:                               ; @.str.8
	.asciz	"Cannot enable 'vddio-pex-ctl' regulator\n"

l_.str.9:                               ; @.str.9
	.asciz	"Cannot enable 'avdd-pll-erefe-supply' regulator\n"

l_.str.10:                              ; @.str.10
	.asciz	"Cannot enable 'PCX' powergate\n"

l_.str.11:                              ; @.str.11
	.asciz	"Cannot unreset 'afi' reset\n"

l_.str.12:                              ; @.str.12
	.asciz	"Cannot enable 'afi' clock\n"

l_.str.13:                              ; @.str.13
	.asciz	"Cannot enable 'cml' clock\n"

l_.str.14:                              ; @.str.14
	.asciz	"Cannot enable 'pll_e' clock\n"

	.no_dead_strip	_tegra_pcib_enable_fdt_resources
.subsections_via_symbols
