	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mv_pcib_attach
_mv_pcib_attach:                        ## @mv_pcib_attach
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edi, %r12d
	callq	_device_get_softc
	movq	%rax, %r14
	movl	%r12d, 52(%rax)
	movl	%r12d, %edi
	callq	_ofw_bus_get_node
	movl	%eax, %r15d
	movl	%eax, %edi
	callq	_OF_parent
	movl	%eax, %ebx
	leaq	L_.str(%rip), %rsi
	leaq	-44(%rbp), %rdx
	movl	%r15d, %edi
	movl	$4, %ecx
	callq	_OF_getencprop
	testq	%rax, %rax
	jle	LBB0_2
## %bb.1:
	movl	-44(%rbp), %eax
LBB0_4:
	movl	%eax, (%r14)
	leaq	L_.str.1(%rip), %rsi
	movl	%r15d, %edi
	callq	_ofw_bus_node_is_compatible
	testq	%rax, %rax
	je	LBB0_6
## %bb.5:
	movq	_MV_TYPE_PCIE@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 96(%r14)
	movl	-44(%rbp), %edi
	callq	_MV_WIN_PCIE_TARGET
	movl	%eax, 88(%r14)
	movl	-44(%rbp), %edi
	callq	_MV_WIN_PCIE_MEM_ATTR
	movl	%eax, 84(%r14)
	movl	-44(%rbp), %edi
	callq	_MV_WIN_PCIE_IO_ATTR
LBB0_10:
	movl	%eax, 80(%r14)
	jmp	LBB0_11
LBB0_2:
	leaq	L_.str(%rip), %rsi
	movl	%r15d, %edi
	callq	_OF_hasprop
	testl	%eax, %eax
	jne	LBB0_18
## %bb.3:
	movl	$0, -44(%rbp)
	xorl	%eax, %eax
	jmp	LBB0_4
LBB0_6:
	leaq	L_.str.2(%rip), %rsi
	movl	%ebx, %edi
	callq	_ofw_bus_node_is_compatible
	testq	%rax, %rax
	je	LBB0_8
## %bb.7:
	movq	_MV_TYPE_PCIE@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 96(%r14)
	movl	-44(%rbp), %edi
	callq	_MV_WIN_PCIE_TARGET_ARMADA38X
	movl	%eax, 88(%r14)
	movl	-44(%rbp), %edi
	callq	_MV_WIN_PCIE_MEM_ATTR_ARMADA38X
	movl	%eax, 84(%r14)
	movl	-44(%rbp), %edi
	callq	_MV_WIN_PCIE_IO_ATTR_ARMADA38X
	movl	%eax, 80(%r14)
	movl	$1, 8(%r14)
LBB0_11:
	leaq	72(%r14), %rdx
	movq	$0, 72(%r14)
	movq	_SYS_RES_MEMORY@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_RF_ACTIVE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%r12d, %edi
	callq	_bus_alloc_resource_any
	movq	%rax, 64(%r14)
	testq	%rax, %rax
	je	LBB0_12
## %bb.13:
	movq	%rax, %rdi
	callq	_rman_get_bustag
	movl	%eax, 48(%r14)
	movq	64(%r14), %rdi
	callq	_rman_get_bushandle
	movl	%eax, 44(%r14)
	movl	48(%r14), %edi
	movq	_PCIE_REG_CONTROL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %esi
	callq	_bus_space_read_4
	movq	_PCIE_CONTROL_ROOT_CMPLX@GOTPCREL(%rip), %rsi
	movq	_MV_MODE_ROOT@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	andl	(%rsi), %eax
	jne	LBB0_15
## %bb.14:
	movq	_MV_MODE_ENDPOINT@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
LBB0_15:
	movq	%rdx, 16(%r14)
	cmpq	%rcx, %rdx
	jne	LBB0_17
## %bb.16:
	leaq	56(%r14), %rsi
	movl	%r15d, %edi
	movl	$4, %edx
	callq	_ofw_bus_setup_iinfo
LBB0_17:
	movl	%r15d, %edi
	movq	%r14, %rsi
	callq	_mv_pcib_decode_win
	testq	%rax, %rax
	jne	LBB0_18
## %bb.19:
	xorl	%eax, %eax
	callq	_mv_pcib_hw_cfginit
	movl	-44(%rbp), %esi
	movq	%r14, %rdi
	callq	_mv_pcib_enable
	movq	%r14, %rdi
	callq	_mv_pcib_mem_init
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_34
## %bb.20:
	movq	_PCI_BUSMAX@GOTPCREL(%rip), %r13
	cmpl	$0, (%r13)
	jle	LBB0_28
## %bb.21:
	xorl	%r15d, %r15d
	jmp	LBB0_22
	.p2align	4, 0x90
LBB0_26:                                ##   in Loop: Header=BB0_22 Depth=1
	movl	%r15d, 24(%r14)
LBB0_27:                                ##   in Loop: Header=BB0_22 Depth=1
	incl	%r15d
	cmpl	(%r13), %r15d
	jge	LBB0_28
LBB0_22:                                ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_25 Depth 2
	movl	%r12d, %edi
	callq	_mv_pcib_maxslots
	testl	%eax, %eax
	jle	LBB0_27
## %bb.23:                              ##   in Loop: Header=BB0_22 Depth=1
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_25:                                ##   Parent Loop BB0_22 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movl	%ebx, %ecx
	andl	$7, %ecx
	movl	%r12d, %edi
	movl	%r15d, %esi
	movl	%ebx, %edx
	xorl	%r8d, %r8d
	movl	$4, %r9d
	callq	_mv_pcib_read_config
	cmpl	$-1, %eax
	jne	LBB0_26
## %bb.24:                              ##   in Loop: Header=BB0_25 Depth=2
	incl	%ebx
	movl	%r12d, %edi
	callq	_mv_pcib_maxslots
	cmpl	%eax, %ebx
	jl	LBB0_25
	jmp	LBB0_27
LBB0_12:
	leaq	L_.str.4(%rip), %rsi
	movl	%r12d, %edi
	callq	_device_printf
LBB0_18:
	movq	_ENXIO@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
LBB0_34:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_8:
	leaq	L_.str.3(%rip), %rsi
	movl	%r15d, %edi
	callq	_ofw_bus_node_is_compatible
	testq	%rax, %rax
	je	LBB0_18
## %bb.9:
	movq	_MV_TYPE_PCI@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 96(%r14)
	movq	_MV_WIN_PCI_TARGET@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 88(%r14)
	movq	_MV_WIN_PCI_MEM_ATTR@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 84(%r14)
	movq	_MV_WIN_PCI_IO_ATTR@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	jmp	LBB0_10
LBB0_28:
	movq	16(%r14), %rax
	movq	_MV_MODE_ROOT@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_31
## %bb.29:
	movl	24(%r14), %ebx
	movl	52(%r14), %edi
	callq	_mv_pcib_maxslots
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_mv_pcib_init
	testl	%eax, %eax
	je	LBB0_30
## %bb.33:
	movl	%eax, %ebx
	leaq	36(%r14), %rdi
	callq	_rman_fini
	addq	$32, %r14
	movq	%r14, %rdi
	callq	_rman_fini
	jmp	LBB0_34
LBB0_31:
	movl	$1, 28(%r14)
	movl	44(%r14), %esi
	movl	48(%r14), %edi
	movq	_PCIE_REG_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_PCIE_STATUS_DEV_OFFS@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$1, %eax
	shll	%cl, %eax
	movl	%eax, %ecx
	callq	_bus_space_write_4
	leaq	L_.str.6(%rip), %rsi
	jmp	LBB0_32
LBB0_30:
	leaq	L_.str.5(%rip), %rsi
LBB0_32:
	movl	%r12d, %edi
	movl	$-1, %edx
	callq	_device_add_child
	addq	$40, %r14
	movq	_MTX_DEF@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	leaq	L_.str.7(%rip), %rsi
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	_mtx_init
	movl	%r12d, %edi
	callq	_bus_generic_attach
	movl	%eax, %ebx
	jmp	LBB0_34
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"marvell,pcie-port"

	.comm	_ENXIO,4,2                      ## @ENXIO
L_.str.1:                               ## @.str.1
	.asciz	"mrvl,pcie"

	.comm	_MV_TYPE_PCIE,8,3               ## @MV_TYPE_PCIE
L_.str.2:                               ## @.str.2
	.asciz	"marvell,armada-370-pcie"

L_.str.3:                               ## @.str.3
	.asciz	"mrvl,pci"

	.comm	_MV_TYPE_PCI,8,3                ## @MV_TYPE_PCI
	.comm	_MV_WIN_PCI_TARGET,4,2          ## @MV_WIN_PCI_TARGET
	.comm	_MV_WIN_PCI_MEM_ATTR,4,2        ## @MV_WIN_PCI_MEM_ATTR
	.comm	_MV_WIN_PCI_IO_ATTR,4,2         ## @MV_WIN_PCI_IO_ATTR
	.comm	_SYS_RES_MEMORY,4,2             ## @SYS_RES_MEMORY
	.comm	_RF_ACTIVE,4,2                  ## @RF_ACTIVE
L_.str.4:                               ## @.str.4
	.asciz	"could not map memory\n"

	.comm	_PCIE_REG_CONTROL,4,2           ## @PCIE_REG_CONTROL
	.comm	_PCIE_CONTROL_ROOT_CMPLX,4,2    ## @PCIE_CONTROL_ROOT_CMPLX
	.comm	_MV_MODE_ROOT,8,3               ## @MV_MODE_ROOT
	.comm	_MV_MODE_ENDPOINT,8,3           ## @MV_MODE_ENDPOINT
	.comm	_PCI_BUSMAX,4,2                 ## @PCI_BUSMAX
L_.str.5:                               ## @.str.5
	.asciz	"pci"

	.comm	_PCIE_REG_STATUS,4,2            ## @PCIE_REG_STATUS
	.comm	_PCIE_STATUS_DEV_OFFS,4,2       ## @PCIE_STATUS_DEV_OFFS
L_.str.6:                               ## @.str.6
	.asciz	"pci_ep"

L_.str.7:                               ## @.str.7
	.asciz	"msi_mtx"

	.comm	_MTX_DEF,4,2                    ## @MTX_DEF
	.no_dead_strip	_mv_pcib_attach
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mv_pcib_attach
_mv_pcib_attach:                        ; @mv_pcib_attach
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	bl	_device_get_softc
	mov	x20, x0
	str	w19, [x0, #52]
	mov	x0, x19
	bl	_ofw_bus_get_node
	mov	x21, x0
	bl	_OF_parent
	mov	x22, x0
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	add	x2, sp, #12
	mov	x0, x21
	mov	w3, #4
	bl	_OF_getencprop
	cmp	x0, #1
	b.lt	LBB0_4
; %bb.1:
	ldr	w8, [sp, #12]
LBB0_2:
	str	w8, [x20]
Lloh2:
	adrp	x1, l_.str.1@PAGE
Lloh3:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x21
	bl	_ofw_bus_node_is_compatible
	cbz	x0, LBB0_6
; %bb.3:
Lloh4:
	adrp	x8, _MV_TYPE_PCIE@GOTPAGE
Lloh5:
	ldr	x8, [x8, _MV_TYPE_PCIE@GOTPAGEOFF]
Lloh6:
	ldr	x8, [x8]
	str	x8, [x20, #96]
	ldr	w0, [sp, #12]
	bl	_MV_WIN_PCIE_TARGET
	str	w0, [x20, #88]
	ldr	w0, [sp, #12]
	bl	_MV_WIN_PCIE_MEM_ATTR
	str	w0, [x20, #84]
	ldr	w0, [sp, #12]
	bl	_MV_WIN_PCIE_IO_ATTR
	str	w0, [x20, #80]
	mov	w8, #1
	str	w8, [x20, #4]
	b	LBB0_10
LBB0_4:
Lloh7:
	adrp	x1, l_.str@PAGE
Lloh8:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x21
	bl	_OF_hasprop
	cbnz	w0, LBB0_24
; %bb.5:
	mov	w8, #0
	str	wzr, [sp, #12]
	b	LBB0_2
LBB0_6:
Lloh9:
	adrp	x1, l_.str.2@PAGE
Lloh10:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x0, x22
	bl	_ofw_bus_node_is_compatible
	cbz	x0, LBB0_8
; %bb.7:
Lloh11:
	adrp	x8, _MV_TYPE_PCIE@GOTPAGE
Lloh12:
	ldr	x8, [x8, _MV_TYPE_PCIE@GOTPAGEOFF]
Lloh13:
	ldr	x8, [x8]
	str	x8, [x20, #96]
	ldr	w0, [sp, #12]
	bl	_MV_WIN_PCIE_TARGET_ARMADA38X
	str	w0, [x20, #88]
	ldr	w0, [sp, #12]
	bl	_MV_WIN_PCIE_MEM_ATTR_ARMADA38X
	str	w0, [x20, #84]
	ldr	w0, [sp, #12]
	bl	_MV_WIN_PCIE_IO_ATTR_ARMADA38X
	str	w0, [x20, #80]
	mov	w8, #1
	str	w8, [x20, #8]
	b	LBB0_10
LBB0_8:
Lloh14:
	adrp	x1, l_.str.3@PAGE
Lloh15:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x0, x21
	bl	_ofw_bus_node_is_compatible
	cbz	x0, LBB0_24
; %bb.9:
Lloh16:
	adrp	x8, _MV_TYPE_PCI@GOTPAGE
Lloh17:
	ldr	x8, [x8, _MV_TYPE_PCI@GOTPAGEOFF]
Lloh18:
	ldr	x8, [x8]
	str	x8, [x20, #96]
Lloh19:
	adrp	x8, _MV_WIN_PCI_TARGET@GOTPAGE
Lloh20:
	ldr	x8, [x8, _MV_WIN_PCI_TARGET@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
	str	w8, [x20, #88]
Lloh22:
	adrp	x8, _MV_WIN_PCI_MEM_ATTR@GOTPAGE
Lloh23:
	ldr	x8, [x8, _MV_WIN_PCI_MEM_ATTR@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
Lloh25:
	adrp	x9, _MV_WIN_PCI_IO_ATTR@GOTPAGE
Lloh26:
	ldr	x9, [x9, _MV_WIN_PCI_IO_ATTR@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
	stp	w9, w8, [x20, #80]
LBB0_10:
	mov	x22, x20
	str	xzr, [x22, #72]!
Lloh28:
	adrp	x8, _SYS_RES_MEMORY@GOTPAGE
Lloh29:
	ldr	x8, [x8, _SYS_RES_MEMORY@GOTPAGEOFF]
Lloh30:
	ldr	w1, [x8]
Lloh31:
	adrp	x8, _RF_ACTIVE@GOTPAGE
Lloh32:
	ldr	x8, [x8, _RF_ACTIVE@GOTPAGEOFF]
Lloh33:
	ldr	w3, [x8]
	mov	x0, x19
	mov	x2, x22
	bl	_bus_alloc_resource_any
	stur	x0, [x22, #-8]
	cbz	x0, LBB0_23
; %bb.11:
	bl	_rman_get_bustag
	str	w0, [x20, #48]
	ldr	x0, [x20, #64]
	bl	_rman_get_bushandle
	mov	x1, x0
	str	w0, [x20, #44]
	ldr	w0, [x20, #48]
Lloh34:
	adrp	x8, _PCIE_REG_CONTROL@GOTPAGE
Lloh35:
	ldr	x8, [x8, _PCIE_REG_CONTROL@GOTPAGEOFF]
Lloh36:
	ldr	w2, [x8]
	bl	_bus_space_read_4
Lloh37:
	adrp	x8, _PCIE_CONTROL_ROOT_CMPLX@GOTPAGE
Lloh38:
	ldr	x8, [x8, _PCIE_CONTROL_ROOT_CMPLX@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
Lloh40:
	adrp	x23, _MV_MODE_ROOT@GOTPAGE
Lloh41:
	ldr	x23, [x23, _MV_MODE_ROOT@GOTPAGEOFF]
Lloh42:
	adrp	x9, _MV_MODE_ENDPOINT@GOTPAGE
Lloh43:
	ldr	x9, [x9, _MV_MODE_ENDPOINT@GOTPAGEOFF]
	ldr	x10, [x23]
Lloh44:
	ldr	x9, [x9]
	tst	w8, w0
	csel	x8, x9, x10, eq
	str	x8, [x20, #16]
	cmp	x8, x10
	b.ne	LBB0_13
; %bb.12:
	add	x1, x20, #56
	mov	x0, x21
	mov	w2, #4
	bl	_ofw_bus_setup_iinfo
LBB0_13:
	mov	x0, x21
	mov	x1, x20
	bl	_mv_pcib_decode_win
	cbnz	x0, LBB0_24
; %bb.14:
	bl	_mv_pcib_hw_cfginit
	ldr	w1, [sp, #12]
	mov	x0, x20
	bl	_mv_pcib_enable
	mov	x0, x20
	bl	_mv_pcib_mem_init
	mov	x21, x0
	cbnz	w0, LBB0_25
; %bb.15:
Lloh45:
	adrp	x24, _PCI_BUSMAX@GOTPAGE
Lloh46:
	ldr	x24, [x24, _PCI_BUSMAX@GOTPAGEOFF]
	ldr	w8, [x24]
	cmp	w8, #1
	b.lt	LBB0_26
; %bb.16:
	mov	w21, #0
	b	LBB0_19
LBB0_17:                                ;   in Loop: Header=BB0_19 Depth=1
	str	w21, [x20, #24]
LBB0_18:                                ;   in Loop: Header=BB0_19 Depth=1
	add	w21, w21, #1
	ldr	w8, [x24]
	cmp	w21, w8
	b.ge	LBB0_26
LBB0_19:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_21 Depth 2
	mov	x0, x19
	bl	_mv_pcib_maxslots
	cmp	w0, #1
	b.lt	LBB0_18
; %bb.20:                               ;   in Loop: Header=BB0_19 Depth=1
	mov	w22, #0
LBB0_21:                                ;   Parent Loop BB0_19 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	and	w3, w22, #0x7
	mov	x0, x19
	mov	x1, x21
	mov	x2, x22
	mov	w4, #0
	mov	w5, #4
	bl	_mv_pcib_read_config
	cmn	w0, #1
	b.ne	LBB0_17
; %bb.22:                               ;   in Loop: Header=BB0_21 Depth=2
	add	w22, w22, #1
	mov	x0, x19
	bl	_mv_pcib_maxslots
	cmp	w22, w0
	b.lt	LBB0_21
	b	LBB0_18
LBB0_23:
Lloh47:
	adrp	x1, l_.str.4@PAGE
Lloh48:
	add	x1, x1, l_.str.4@PAGEOFF
	mov	x0, x19
	bl	_device_printf
LBB0_24:
Lloh49:
	adrp	x8, _ENXIO@GOTPAGE
Lloh50:
	ldr	x8, [x8, _ENXIO@GOTPAGEOFF]
Lloh51:
	ldr	w21, [x8]
LBB0_25:
	mov	x0, x21
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
LBB0_26:
	ldr	x8, [x20, #16]
	ldr	x9, [x23]
	cmp	x8, x9
	b.ne	LBB0_29
; %bb.27:
	ldr	w21, [x20, #24]
	ldr	w0, [x20, #52]
	bl	_mv_pcib_maxslots
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_mv_pcib_init
	cbz	w0, LBB0_30
; %bb.28:
	mov	x21, x0
	add	x0, x20, #36
	bl	_rman_fini
	add	x0, x20, #32
	bl	_rman_fini
	b	LBB0_25
LBB0_29:
	mov	w8, #1
	str	w8, [x20, #28]
Lloh52:
	adrp	x9, _PCIE_REG_STATUS@GOTPAGE
Lloh53:
	ldr	x9, [x9, _PCIE_REG_STATUS@GOTPAGEOFF]
	ldp	w1, w0, [x20, #44]
Lloh54:
	ldr	w2, [x9]
Lloh55:
	adrp	x9, _PCIE_STATUS_DEV_OFFS@GOTPAGE
Lloh56:
	ldr	x9, [x9, _PCIE_STATUS_DEV_OFFS@GOTPAGEOFF]
Lloh57:
	ldr	w9, [x9]
	lsl	w3, w8, w9
	bl	_bus_space_write_4
Lloh58:
	adrp	x1, l_.str.6@PAGE
Lloh59:
	add	x1, x1, l_.str.6@PAGEOFF
	b	LBB0_31
LBB0_30:
Lloh60:
	adrp	x1, l_.str.5@PAGE
Lloh61:
	add	x1, x1, l_.str.5@PAGEOFF
LBB0_31:
	mov	x0, x19
	mov	w2, #-1
	bl	_device_add_child
	add	x0, x20, #40
Lloh62:
	adrp	x8, _MTX_DEF@GOTPAGE
Lloh63:
	ldr	x8, [x8, _MTX_DEF@GOTPAGEOFF]
Lloh64:
	ldr	w3, [x8]
Lloh65:
	adrp	x1, l_.str.7@PAGE
Lloh66:
	add	x1, x1, l_.str.7@PAGEOFF
	mov	x2, #0
	bl	_mtx_init
	mov	x0, x19
	bl	_bus_generic_attach
	mov	x21, x0
	b	LBB0_25
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpAdd	Lloh7, Lloh8
	.loh AdrpAdd	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpAdd	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpAdd	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpAdd	Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpAdd	Lloh60, Lloh61
	.loh AdrpAdd	Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"marvell,pcie-port"

	.comm	_ENXIO,4,2                      ; @ENXIO
l_.str.1:                               ; @.str.1
	.asciz	"mrvl,pcie"

	.comm	_MV_TYPE_PCIE,8,3               ; @MV_TYPE_PCIE
l_.str.2:                               ; @.str.2
	.asciz	"marvell,armada-370-pcie"

l_.str.3:                               ; @.str.3
	.asciz	"mrvl,pci"

	.comm	_MV_TYPE_PCI,8,3                ; @MV_TYPE_PCI
	.comm	_MV_WIN_PCI_TARGET,4,2          ; @MV_WIN_PCI_TARGET
	.comm	_MV_WIN_PCI_MEM_ATTR,4,2        ; @MV_WIN_PCI_MEM_ATTR
	.comm	_MV_WIN_PCI_IO_ATTR,4,2         ; @MV_WIN_PCI_IO_ATTR
	.comm	_SYS_RES_MEMORY,4,2             ; @SYS_RES_MEMORY
	.comm	_RF_ACTIVE,4,2                  ; @RF_ACTIVE
l_.str.4:                               ; @.str.4
	.asciz	"could not map memory\n"

	.comm	_PCIE_REG_CONTROL,4,2           ; @PCIE_REG_CONTROL
	.comm	_PCIE_CONTROL_ROOT_CMPLX,4,2    ; @PCIE_CONTROL_ROOT_CMPLX
	.comm	_MV_MODE_ROOT,8,3               ; @MV_MODE_ROOT
	.comm	_MV_MODE_ENDPOINT,8,3           ; @MV_MODE_ENDPOINT
	.comm	_PCI_BUSMAX,4,2                 ; @PCI_BUSMAX
l_.str.5:                               ; @.str.5
	.asciz	"pci"

	.comm	_PCIE_REG_STATUS,4,2            ; @PCIE_REG_STATUS
	.comm	_PCIE_STATUS_DEV_OFFS,4,2       ; @PCIE_STATUS_DEV_OFFS
l_.str.6:                               ; @.str.6
	.asciz	"pci_ep"

l_.str.7:                               ; @.str.7
	.asciz	"msi_mtx"

	.comm	_MTX_DEF,4,2                    ; @MTX_DEF
	.no_dead_strip	_mv_pcib_attach
.subsections_via_symbols
