	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function power_on_cpu
_power_on_cpu:                          ## @power_on_cpu
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	testl	%edi, %edi
	jle	LBB0_11
## %bb.1:
	movq	_aml8726_soc_hw_rev@GOTPCREL(%rip), %r12
	movl	(%r12), %eax
	andl	$-2, %eax
	cmpl	$128, %eax
	jne	LBB0_11
## %bb.2:
	movl	%edi, %ebx
	movq	_AML_SCU_CPU_PWR_STATUS_REG@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_SCU_READ_4
	movq	_AML_SCU_CPU_PWR_STATUS_CPU1_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r14d
	movl	%ebx, %ecx
	leal	-8(,%rcx,8), %ecx
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %r14d
	decl	%ebx
	notl	%r14d
	andl	%eax, %r14d
	movl	(%r15), %edi
	movl	%r14d, %esi
	callq	_SCU_WRITE_4
	movl	(%r15), %edi
	callq	_SCU_BARRIER
	cmpl	$128, (%r12)
	jne	LBB0_4
## %bb.3:
	movq	_AML_M8_CPU_PWR_CNTL0_REG@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_AOBUS_READ_4
	movq	_AML_M8B_CPU_PWR_CNTL0_MODE_CPU1_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	leal	(%rbx,%rbx), %ecx
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r15), %edi
	callq	_AOBUS_WRITE_4
	movl	(%r15), %edi
	callq	_AOBUS_BARRIER
LBB0_4:
	movl	$5, %edi
	callq	_DELAY
	movq	_AML_SOC_CPU_CLK_CNTL_REG@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_CBUS_READ_4
	movq	_AML_M8_CPU_CLK_CNTL_RESET_CPU1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%ebx, %ecx
	shll	%cl, %esi
	orl	%eax, %esi
	movl	(%r13), %edi
	callq	_CBUS_WRITE_4
	movl	(%r13), %edi
	callq	_CBUS_BARRIER
	cmpl	$128, (%r12)
	jne	LBB0_6
## %bb.5:
	movq	_AML_M8B_CPU_PWR_MEM_PD0_REG@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_AOBUS_READ_4
	movq	_AML_M8B_CPU_PWR_MEM_PD0_CPU1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	leal	(,%rbx,4), %ecx
                                        ## kill: def $cl killed $cl killed $ecx
	sarl	%cl, %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r15), %edi
	callq	_AOBUS_WRITE_4
	movl	(%r15), %edi
	callq	_AOBUS_BARRIER
LBB0_6:
	movq	_AML_M8_CPU_PWR_CNTL1_REG@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_AOBUS_READ_4
	movq	_AML_M8_CPU_PWR_CNTL1_MODE_CPU1_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	leal	(%rbx,%rbx), %ecx
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r15), %edi
	callq	_AOBUS_WRITE_4
	movl	(%r15), %edi
	callq	_AOBUS_BARRIER
	movl	$10, %edi
	callq	_DELAY
	cmpl	$128, (%r12)
	jne	LBB0_10
## %bb.7:
	movl	(%r15), %edi
	callq	_AOBUS_READ_4
	movq	_AML_M8B_CPU_PWR_CNTL1_PWR_CPU1@GOTPCREL(%rip), %r12
	.p2align	4, 0x90
LBB0_9:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r12), %edx
	movl	%ebx, %ecx
	shll	%cl, %edx
	testl	%eax, %edx
	jne	LBB0_10
## %bb.8:                               ##   in Loop: Header=BB0_9 Depth=1
	movl	$10, %edi
	callq	_DELAY
	movl	(%r15), %edi
	callq	_AOBUS_READ_4
	jmp	LBB0_9
LBB0_10:
	movq	_AML_M8_CPU_PWR_CNTL0_REG@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_AOBUS_READ_4
	movq	_AML_M8_CPU_PWR_CNTL0_ISO_CPU1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%ebx, %ecx
	shll	%cl, %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r15), %edi
	callq	_AOBUS_WRITE_4
	movl	(%r15), %edi
	callq	_AOBUS_BARRIER
	movl	(%r13), %edi
	callq	_CBUS_READ_4
	movq	_AML_M8_CPU_CLK_CNTL_RESET_CPU1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%ebx, %ecx
	shll	%cl, %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r13), %edi
	callq	_CBUS_WRITE_4
	movl	(%r13), %edi
	callq	_CBUS_BARRIER
	movq	_aml8726_soc_hw_rev@GOTPCREL(%rip), %rax
	cmpl	$128, (%rax)
	jne	LBB0_11
## %bb.12:
	movq	_AML_SCU_CPU_PWR_STATUS_REG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movl	%r14d, %esi
	callq	_SCU_WRITE_4
	movl	(%rbx), %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_SCU_BARRIER                    ## TAILCALL
LBB0_11:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_aml8726_soc_hw_rev,4,2         ## @aml8726_soc_hw_rev
	.comm	_AML_SCU_CPU_PWR_STATUS_REG,4,2 ## @AML_SCU_CPU_PWR_STATUS_REG
	.comm	_AML_SCU_CPU_PWR_STATUS_CPU1_MASK,4,2 ## @AML_SCU_CPU_PWR_STATUS_CPU1_MASK
	.comm	_AML_M8_CPU_PWR_CNTL0_REG,4,2   ## @AML_M8_CPU_PWR_CNTL0_REG
	.comm	_AML_M8B_CPU_PWR_CNTL0_MODE_CPU1_MASK,4,2 ## @AML_M8B_CPU_PWR_CNTL0_MODE_CPU1_MASK
	.comm	_AML_SOC_CPU_CLK_CNTL_REG,4,2   ## @AML_SOC_CPU_CLK_CNTL_REG
	.comm	_AML_M8_CPU_CLK_CNTL_RESET_CPU1,4,2 ## @AML_M8_CPU_CLK_CNTL_RESET_CPU1
	.comm	_AML_M8B_CPU_PWR_MEM_PD0_REG,4,2 ## @AML_M8B_CPU_PWR_MEM_PD0_REG
	.comm	_AML_M8B_CPU_PWR_MEM_PD0_CPU1,4,2 ## @AML_M8B_CPU_PWR_MEM_PD0_CPU1
	.comm	_AML_M8_CPU_PWR_CNTL1_REG,4,2   ## @AML_M8_CPU_PWR_CNTL1_REG
	.comm	_AML_M8_CPU_PWR_CNTL1_MODE_CPU1_MASK,4,2 ## @AML_M8_CPU_PWR_CNTL1_MODE_CPU1_MASK
	.comm	_AML_M8B_CPU_PWR_CNTL1_PWR_CPU1,4,2 ## @AML_M8B_CPU_PWR_CNTL1_PWR_CPU1
	.comm	_AML_M8_CPU_PWR_CNTL0_ISO_CPU1,4,2 ## @AML_M8_CPU_PWR_CNTL0_ISO_CPU1
	.no_dead_strip	_power_on_cpu
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function power_on_cpu
_power_on_cpu:                          ; @power_on_cpu
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	subs	w22, w0, #1
	b.lt	LBB0_12
; %bb.1:
Lloh0:
	adrp	x21, _aml8726_soc_hw_rev@GOTPAGE
Lloh1:
	ldr	x21, [x21, _aml8726_soc_hw_rev@GOTPAGEOFF]
	ldr	w8, [x21]
	and	w8, w8, #0xfffffffe
	cmp	w8, #128
	b.ne	LBB0_12
; %bb.2:
Lloh2:
	adrp	x20, _AML_SCU_CPU_PWR_STATUS_REG@GOTPAGE
Lloh3:
	ldr	x20, [x20, _AML_SCU_CPU_PWR_STATUS_REG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_SCU_READ_4
Lloh4:
	adrp	x8, _AML_SCU_CPU_PWR_STATUS_CPU1_MASK@GOTPAGE
Lloh5:
	ldr	x8, [x8, _AML_SCU_CPU_PWR_STATUS_CPU1_MASK@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
	lsl	w9, w22, #3
	lsl	w8, w8, w9
	bic	w19, w0, w8
	ldr	w0, [x20]
	mov	x1, x19
	bl	_SCU_WRITE_4
	ldr	w0, [x20]
	bl	_SCU_BARRIER
	ldr	w8, [x21]
Lloh7:
	adrp	x23, _AML_M8_CPU_PWR_CNTL0_REG@GOTPAGE
Lloh8:
	ldr	x23, [x23, _AML_M8_CPU_PWR_CNTL0_REG@GOTPAGEOFF]
	lsl	w26, w22, #1
	cmp	w8, #128
	b.ne	LBB0_4
; %bb.3:
	ldr	w0, [x23]
	bl	_AOBUS_READ_4
Lloh9:
	adrp	x8, _AML_M8B_CPU_PWR_CNTL0_MODE_CPU1_MASK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _AML_M8B_CPU_PWR_CNTL0_MODE_CPU1_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	lsl	w8, w8, w26
	bic	w1, w0, w8
	ldr	w0, [x23]
	bl	_AOBUS_WRITE_4
	ldr	w0, [x23]
	bl	_AOBUS_BARRIER
LBB0_4:
	mov	w0, #5
	bl	_DELAY
Lloh12:
	adrp	x24, _AML_SOC_CPU_CLK_CNTL_REG@GOTPAGE
Lloh13:
	ldr	x24, [x24, _AML_SOC_CPU_CLK_CNTL_REG@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_CBUS_READ_4
Lloh14:
	adrp	x25, _AML_M8_CPU_CLK_CNTL_RESET_CPU1@GOTPAGE
Lloh15:
	ldr	x25, [x25, _AML_M8_CPU_CLK_CNTL_RESET_CPU1@GOTPAGEOFF]
	ldr	w8, [x25]
	lsl	w8, w8, w22
	orr	w1, w8, w0
	ldr	w0, [x24]
	bl	_CBUS_WRITE_4
	ldr	w0, [x24]
	bl	_CBUS_BARRIER
	ldr	w8, [x21]
	cmp	w8, #128
	b.ne	LBB0_6
; %bb.5:
Lloh16:
	adrp	x27, _AML_M8B_CPU_PWR_MEM_PD0_REG@GOTPAGE
Lloh17:
	ldr	x27, [x27, _AML_M8B_CPU_PWR_MEM_PD0_REG@GOTPAGEOFF]
	ldr	w0, [x27]
	bl	_AOBUS_READ_4
Lloh18:
	adrp	x8, _AML_M8B_CPU_PWR_MEM_PD0_CPU1@GOTPAGE
Lloh19:
	ldr	x8, [x8, _AML_M8B_CPU_PWR_MEM_PD0_CPU1@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	lsl	w9, w22, #2
	asr	w8, w8, w9
	bic	w1, w0, w8
	ldr	w0, [x27]
	bl	_AOBUS_WRITE_4
	ldr	w0, [x27]
	bl	_AOBUS_BARRIER
LBB0_6:
Lloh21:
	adrp	x27, _AML_M8_CPU_PWR_CNTL1_REG@GOTPAGE
Lloh22:
	ldr	x27, [x27, _AML_M8_CPU_PWR_CNTL1_REG@GOTPAGEOFF]
	ldr	w0, [x27]
	bl	_AOBUS_READ_4
Lloh23:
	adrp	x8, _AML_M8_CPU_PWR_CNTL1_MODE_CPU1_MASK@GOTPAGE
Lloh24:
	ldr	x8, [x8, _AML_M8_CPU_PWR_CNTL1_MODE_CPU1_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
	lsl	w8, w8, w26
	bic	w1, w0, w8
	ldr	w0, [x27]
	bl	_AOBUS_WRITE_4
	ldr	w0, [x27]
	bl	_AOBUS_BARRIER
	mov	w0, #10
	bl	_DELAY
	ldr	w8, [x21]
	cmp	w8, #128
	b.ne	LBB0_10
; %bb.7:
	ldr	w0, [x27]
	bl	_AOBUS_READ_4
Lloh26:
	adrp	x26, _AML_M8B_CPU_PWR_CNTL1_PWR_CPU1@GOTPAGE
Lloh27:
	ldr	x26, [x26, _AML_M8B_CPU_PWR_CNTL1_PWR_CPU1@GOTPAGEOFF]
LBB0_8:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w8, [x26]
	lsl	w8, w8, w22
	tst	w8, w0
	b.ne	LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=1
	mov	w0, #10
	bl	_DELAY
	ldr	w0, [x27]
	bl	_AOBUS_READ_4
	b	LBB0_8
LBB0_10:
	ldr	w0, [x23]
	bl	_AOBUS_READ_4
Lloh28:
	adrp	x8, _AML_M8_CPU_PWR_CNTL0_ISO_CPU1@GOTPAGE
Lloh29:
	ldr	x8, [x8, _AML_M8_CPU_PWR_CNTL0_ISO_CPU1@GOTPAGEOFF]
Lloh30:
	ldr	w8, [x8]
	lsl	w8, w8, w22
	bic	w1, w0, w8
	ldr	w0, [x23]
	bl	_AOBUS_WRITE_4
	ldr	w0, [x23]
	bl	_AOBUS_BARRIER
	ldr	w0, [x24]
	bl	_CBUS_READ_4
	ldr	w8, [x25]
	lsl	w8, w8, w22
	bic	w1, w0, w8
	ldr	w0, [x24]
	bl	_CBUS_WRITE_4
	ldr	w0, [x24]
	bl	_CBUS_BARRIER
	ldr	w8, [x21]
	cmp	w8, #128
	b.ne	LBB0_12
; %bb.11:
	ldr	w0, [x20]
	mov	x1, x19
	bl	_SCU_WRITE_4
	ldr	w0, [x20]
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_SCU_BARRIER
LBB0_12:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.cfi_endproc
                                        ; -- End function
	.comm	_aml8726_soc_hw_rev,4,2         ; @aml8726_soc_hw_rev
	.comm	_AML_SCU_CPU_PWR_STATUS_REG,4,2 ; @AML_SCU_CPU_PWR_STATUS_REG
	.comm	_AML_SCU_CPU_PWR_STATUS_CPU1_MASK,4,2 ; @AML_SCU_CPU_PWR_STATUS_CPU1_MASK
	.comm	_AML_M8_CPU_PWR_CNTL0_REG,4,2   ; @AML_M8_CPU_PWR_CNTL0_REG
	.comm	_AML_M8B_CPU_PWR_CNTL0_MODE_CPU1_MASK,4,2 ; @AML_M8B_CPU_PWR_CNTL0_MODE_CPU1_MASK
	.comm	_AML_SOC_CPU_CLK_CNTL_REG,4,2   ; @AML_SOC_CPU_CLK_CNTL_REG
	.comm	_AML_M8_CPU_CLK_CNTL_RESET_CPU1,4,2 ; @AML_M8_CPU_CLK_CNTL_RESET_CPU1
	.comm	_AML_M8B_CPU_PWR_MEM_PD0_REG,4,2 ; @AML_M8B_CPU_PWR_MEM_PD0_REG
	.comm	_AML_M8B_CPU_PWR_MEM_PD0_CPU1,4,2 ; @AML_M8B_CPU_PWR_MEM_PD0_CPU1
	.comm	_AML_M8_CPU_PWR_CNTL1_REG,4,2   ; @AML_M8_CPU_PWR_CNTL1_REG
	.comm	_AML_M8_CPU_PWR_CNTL1_MODE_CPU1_MASK,4,2 ; @AML_M8_CPU_PWR_CNTL1_MODE_CPU1_MASK
	.comm	_AML_M8B_CPU_PWR_CNTL1_PWR_CPU1,4,2 ; @AML_M8B_CPU_PWR_CNTL1_PWR_CPU1
	.comm	_AML_M8_CPU_PWR_CNTL0_ISO_CPU1,4,2 ; @AML_M8_CPU_PWR_CNTL0_ISO_CPU1
	.no_dead_strip	_power_on_cpu
.subsections_via_symbols
