	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function __fpu_cmpck
___fpu_cmpck:                           ## @__fpu_cmpck
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %r14
	movl	(%rdi), %eax
	movq	_FSR_CEXC_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	%eax, %ebx
	shll	%cl, %ebx
	orl	4(%rdi), %ebx
	testl	%eax, %eax
	je	LBB0_4
## %bb.1:
	movq	_FSR_NV@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_FSR_TEM_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	%eax, %edx
	shll	%cl, %edx
	testl	%ebx, %edx
	je	LBB0_3
## %bb.2:
	movq	_FSR_FTT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %ebx
	movq	_FSR_FTT_IEEE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_FSR_FTT
	orl	%ebx, %eax
	movl	%eax, 4(%r14)
	movq	_SIGFPE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	jmp	LBB0_5
LBB0_3:
	movq	_FSR_AEXC_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	orl	%eax, %ebx
LBB0_4:
	movl	%ebx, 4(%r14)
	xorl	%eax, %eax
LBB0_5:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_FSR_CEXC_SHIFT,4,2             ## @FSR_CEXC_SHIFT
	.comm	_FSR_NV,4,2                     ## @FSR_NV
	.comm	_FSR_TEM_SHIFT,4,2              ## @FSR_TEM_SHIFT
	.comm	_FSR_FTT_MASK,4,2               ## @FSR_FTT_MASK
	.comm	_FSR_FTT_IEEE,4,2               ## @FSR_FTT_IEEE
	.comm	_SIGFPE,4,2                     ## @SIGFPE
	.comm	_FSR_AEXC_SHIFT,4,2             ## @FSR_AEXC_SHIFT
	.no_dead_strip	___fpu_cmpck
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function __fpu_cmpck
___fpu_cmpck:                           ; @__fpu_cmpck
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldp	w9, w8, [x0]
Lloh0:
	adrp	x10, _FSR_CEXC_SHIFT@GOTPAGE
Lloh1:
	ldr	x10, [x10, _FSR_CEXC_SHIFT@GOTPAGEOFF]
Lloh2:
	ldr	w10, [x10]
	lsl	w10, w9, w10
	orr	w8, w10, w8
	cbz	w9, LBB0_4
; %bb.1:
Lloh3:
	adrp	x9, _FSR_NV@GOTPAGE
Lloh4:
	ldr	x9, [x9, _FSR_NV@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
Lloh6:
	adrp	x10, _FSR_TEM_SHIFT@GOTPAGE
Lloh7:
	ldr	x10, [x10, _FSR_TEM_SHIFT@GOTPAGEOFF]
Lloh8:
	ldr	w10, [x10]
	lsl	w10, w9, w10
	tst	w10, w8
	b.eq	LBB0_3
; %bb.2:
Lloh9:
	adrp	x9, _FSR_FTT_MASK@GOTPAGE
Lloh10:
	ldr	x9, [x9, _FSR_FTT_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	bic	w20, w8, w9
Lloh12:
	adrp	x8, _FSR_FTT_IEEE@GOTPAGE
Lloh13:
	ldr	x8, [x8, _FSR_FTT_IEEE@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	bl	_FSR_FTT
	orr	w8, w0, w20
	str	w8, [x19, #4]
Lloh15:
	adrp	x8, _SIGFPE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _SIGFPE@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	b	LBB0_5
LBB0_3:
Lloh18:
	adrp	x10, _FSR_AEXC_SHIFT@GOTPAGE
Lloh19:
	ldr	x10, [x10, _FSR_AEXC_SHIFT@GOTPAGEOFF]
Lloh20:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w8, w9, w8
LBB0_4:
	mov	w0, #0
	str	w8, [x19, #4]
LBB0_5:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.cfi_endproc
                                        ; -- End function
	.comm	_FSR_CEXC_SHIFT,4,2             ; @FSR_CEXC_SHIFT
	.comm	_FSR_NV,4,2                     ; @FSR_NV
	.comm	_FSR_TEM_SHIFT,4,2              ; @FSR_TEM_SHIFT
	.comm	_FSR_FTT_MASK,4,2               ; @FSR_FTT_MASK
	.comm	_FSR_FTT_IEEE,4,2               ; @FSR_FTT_IEEE
	.comm	_SIGFPE,4,2                     ; @SIGFPE
	.comm	_FSR_AEXC_SHIFT,4,2             ; @FSR_AEXC_SHIFT
	.no_dead_strip	___fpu_cmpck
.subsections_via_symbols
