	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function soc_identify
_soc_identify:                          ## @soc_identify
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %ebx
	movl	%edi, %r14d
	leaq	L_.str(%rip), %rdi
	xorl	%eax, %eax
	callq	_printf
	movq	_bootverbose@GOTPCREL(%rip), %rax
	cmpq	$0, (%rax)
	je	LBB0_2
## %bb.1:
	leaq	L_.str.1(%rip), %rdi
	movl	%r14d, %esi
	movl	%ebx, %edx
	xorl	%eax, %eax
	callq	_printf
LBB0_2:
	leaq	L_.str.2(%rip), %r15
	leal	-128(%r14), %eax
	cmpl	$16, %eax
	ja	LBB0_26
## %bb.3:
	leaq	L_.str.15(%rip), %rsi
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_25:
	leaq	L_.str.28(%rip), %rsi
	jmp	LBB0_27
LBB0_13:
	cmpl	$2, %ebx
	leaq	L_.str.19(%rip), %rax
	leaq	L_.str.2(%rip), %r15
	cmoveq	%rax, %r15
	leaq	L_.str.18(%rip), %rsi
	jmp	LBB0_27
LBB0_6:
	addl	$-4, %ebx
	leaq	L_.str.7(%rip), %rsi
	cmpl	$3, %ebx
	jae	LBB0_27
## %bb.7:
	movslq	%ebx, %rax
	leaq	l_reltable.soc_identify(%rip), %rcx
	jmp	LBB0_10
LBB0_4:
	cmpl	$3, %ebx
	leaq	L_.str.4(%rip), %rax
	leaq	L_.str.2(%rip), %r15
	cmoveq	%rax, %r15
	leaq	L_.str.3(%rip), %rsi
	jmp	LBB0_27
LBB0_26:
	leaq	L_.str.29(%rip), %rsi
	jmp	LBB0_27
LBB0_24:
	leaq	L_.str.27(%rip), %rsi
	jmp	LBB0_27
LBB0_23:
	leaq	L_.str.26(%rip), %rsi
	jmp	LBB0_27
LBB0_21:
	leaq	L_.str.24(%rip), %rsi
	jmp	LBB0_27
LBB0_22:
	leaq	L_.str.25(%rip), %rsi
	jmp	LBB0_27
LBB0_12:
	leaq	L_.str.17(%rip), %rsi
	jmp	LBB0_27
LBB0_11:
	leaq	L_.str.16(%rip), %rsi
	jmp	LBB0_27
LBB0_18:
	leaq	L_.str.21(%rip), %rsi
	jmp	LBB0_27
LBB0_19:
	leaq	L_.str.22(%rip), %rsi
	jmp	LBB0_27
LBB0_20:
	leaq	L_.str.23(%rip), %rsi
	jmp	LBB0_27
LBB0_14:
	leaq	L_.str.20(%rip), %rsi
	testl	%ebx, %ebx
	je	LBB0_15
## %bb.16:
	cmpl	$1, %ebx
	jne	LBB0_27
## %bb.17:
	leaq	L_.str.14(%rip), %r15
	jmp	LBB0_27
LBB0_8:
	leaq	L_.str.11(%rip), %rsi
	cmpl	$4, %ebx
	jae	LBB0_27
## %bb.9:
	movslq	%ebx, %rax
	leaq	l_reltable.soc_identify.45(%rip), %rcx
LBB0_10:
	movslq	(%rcx,%rax,4), %r15
	addq	%rcx, %r15
	jmp	LBB0_27
LBB0_5:
	cmpl	$2, %ebx
	leaq	L_.str.6(%rip), %rax
	leaq	L_.str.2(%rip), %r15
	cmoveq	%rax, %r15
	leaq	L_.str.5(%rip), %rsi
	jmp	LBB0_27
LBB0_15:
	leaq	L_.str.13(%rip), %r15
LBB0_27:
	leaq	L_.str.30(%rip), %rdi
	xorl	%eax, %eax
	callq	_printf
	cmpb	$0, (%r15)
	je	LBB0_29
## %bb.28:
	leaq	L_.str.31(%rip), %rdi
	movq	%r15, %rsi
	xorl	%eax, %eax
	callq	_printf
LBB0_29:
	xorl	%eax, %eax
	callq	_get_tclk
	cltq
	imulq	$1125899907, %rax, %rsi         ## imm = 0x431BDE83
	movq	%rsi, %rax
	shrq	$63, %rax
	sarq	$50, %rsi
	addl	%eax, %esi
	leaq	L_.str.32(%rip), %rdi
                                        ## kill: def $esi killed $esi killed $rsi
	xorl	%eax, %eax
	callq	_printf
	xorl	%eax, %eax
	callq	_get_cpu_freq
	testl	%eax, %eax
	je	LBB0_31
## %bb.30:
	cltq
	imulq	$1125899907, %rax, %rsi         ## imm = 0x431BDE83
	movq	%rsi, %rax
	shrq	$63, %rax
	sarq	$50, %rsi
	addl	%eax, %esi
	leaq	L_.str.33(%rip), %rdi
                                        ## kill: def $esi killed $esi killed $rsi
	xorl	%eax, %eax
	callq	_printf
LBB0_31:
	movl	$10, %edi
	callq	_putchar
	movq	_CPU_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_read_cpu_ctrl
	movq	_CPU_CONFIG_IC_PREF@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%eax, %ecx
	leaq	L_.str.37(%rip), %rcx
	leaq	L_.str.36(%rip), %rdx
	movq	%rdx, %rsi
	cmoveq	%rcx, %rsi
	movq	_CPU_CONFIG_DC_PREF@GOTPCREL(%rip), %rdi
	andl	(%rdi), %eax
	cmoveq	%rcx, %rdx
	leaq	L_.str.35(%rip), %rdi
	xorl	%eax, %eax
	callq	_printf
	leal	-140(%r14), %eax
	cmpl	$2, %eax
	jae	LBB0_32
## %bb.34:
	movq	_CPU_L2_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_read_cpu_ctrl
	movq	_CPU_L2_CONFIG_MODE@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	leaq	L_.str.40(%rip), %rax
	leaq	L_.str.39(%rip), %rsi
	cmoveq	%rax, %rsi
	leaq	L_.str.38(%rip), %rdi
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_printf                         ## TAILCALL
LBB0_32:
	cmpl	$132, %r14d
	jne	LBB0_33
## %bb.35:
	movq	_CPU_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_read_cpu_ctrl
	movq	_CPU_CONTROL_L2_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%eax, %ecx
	movq	_CPU_CONTROL_L2_MODE@GOTPCREL(%rip), %rdx
	andl	(%rdx), %eax
	testl	%ecx, %ecx
	leaq	L_.str.43(%rip), %rcx
	leaq	L_.str.42(%rip), %rsi
	cmoveq	%rcx, %rsi
	testl	%eax, %eax
	leaq	L_.str.40(%rip), %rax
	leaq	L_.str.39(%rip), %rdx
	cmoveq	%rax, %rdx
	leaq	L_.str.41(%rip), %rdi
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_printf                         ## TAILCALL
LBB0_33:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_25, LBB0_25-LJTI0_0
.set L0_0_set_24, LBB0_24-LJTI0_0
.set L0_0_set_23, LBB0_23-LJTI0_0
.set L0_0_set_21, LBB0_21-LJTI0_0
.set L0_0_set_22, LBB0_22-LJTI0_0
.set L0_0_set_12, LBB0_12-LJTI0_0
.set L0_0_set_11, LBB0_11-LJTI0_0
.set L0_0_set_27, LBB0_27-LJTI0_0
.set L0_0_set_18, LBB0_18-LJTI0_0
.set L0_0_set_19, LBB0_19-LJTI0_0
.set L0_0_set_20, LBB0_20-LJTI0_0
.set L0_0_set_13, LBB0_13-LJTI0_0
.set L0_0_set_14, LBB0_14-LJTI0_0
.set L0_0_set_8, LBB0_8-LJTI0_0
.set L0_0_set_6, LBB0_6-LJTI0_0
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_4, LBB0_4-LJTI0_0
LJTI0_0:
	.long	L0_0_set_25
	.long	L0_0_set_24
	.long	L0_0_set_23
	.long	L0_0_set_21
	.long	L0_0_set_22
	.long	L0_0_set_12
	.long	L0_0_set_11
	.long	L0_0_set_27
	.long	L0_0_set_18
	.long	L0_0_set_19
	.long	L0_0_set_20
	.long	L0_0_set_13
	.long	L0_0_set_14
	.long	L0_0_set_8
	.long	L0_0_set_6
	.long	L0_0_set_5
	.long	L0_0_set_4
	.end_data_region
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"SOC: "

	.comm	_bootverbose,8,3                ## @bootverbose
L_.str.1:                               ## @.str.1
	.asciz	"(0x%4x:0x%02x) "

L_.str.2:                               ## @.str.2
	.space	1

L_.str.3:                               ## @.str.3
	.asciz	"Marvell 88F5181"

L_.str.4:                               ## @.str.4
	.asciz	"B1"

L_.str.5:                               ## @.str.5
	.asciz	"Marvell 88F5182"

L_.str.6:                               ## @.str.6
	.asciz	"A2"

L_.str.7:                               ## @.str.7
	.asciz	"Marvell 88F5281"

L_.str.8:                               ## @.str.8
	.asciz	"D0"

L_.str.9:                               ## @.str.9
	.asciz	"D1"

L_.str.10:                              ## @.str.10
	.asciz	"D2"

L_.str.11:                              ## @.str.11
	.asciz	"Marvell 88F6281"

L_.str.12:                              ## @.str.12
	.asciz	"Z0"

L_.str.13:                              ## @.str.13
	.asciz	"A0"

L_.str.14:                              ## @.str.14
	.asciz	"A1"

L_.str.15:                              ## @.str.15
	.asciz	"Marvell 88RC8180"

L_.str.16:                              ## @.str.16
	.asciz	"Marvell 88RC9480"

L_.str.17:                              ## @.str.17
	.asciz	"Marvell 88RC9580"

L_.str.18:                              ## @.str.18
	.asciz	"Marvell 88F6781"

L_.str.19:                              ## @.str.19
	.asciz	"Y0"

L_.str.20:                              ## @.str.20
	.asciz	"Marvell 88F6282"

L_.str.21:                              ## @.str.21
	.asciz	"Marvell 88F6828"

L_.str.22:                              ## @.str.22
	.asciz	"Marvell 88F6820"

L_.str.23:                              ## @.str.23
	.asciz	"Marvell 88F6810"

L_.str.24:                              ## @.str.24
	.asciz	"Marvell MV78100 Z0"

L_.str.25:                              ## @.str.25
	.asciz	"Marvell MV78100"

L_.str.26:                              ## @.str.26
	.asciz	"Marvell MV78160"

L_.str.27:                              ## @.str.27
	.asciz	"Marvell MV78260"

L_.str.28:                              ## @.str.28
	.asciz	"Marvell MV78460"

L_.str.29:                              ## @.str.29
	.asciz	"UNKNOWN"

L_.str.30:                              ## @.str.30
	.asciz	"%s"

L_.str.31:                              ## @.str.31
	.asciz	" rev %s"

L_.str.32:                              ## @.str.32
	.asciz	", TClock %dMHz"

L_.str.33:                              ## @.str.33
	.asciz	", Frequency %dMHz"

	.comm	_CPU_CONFIG,4,2                 ## @CPU_CONFIG
L_.str.35:                              ## @.str.35
	.asciz	"  Instruction cache prefetch %s, data cache prefetch %s\n"

	.comm	_CPU_CONFIG_IC_PREF,4,2         ## @CPU_CONFIG_IC_PREF
L_.str.36:                              ## @.str.36
	.asciz	"enabled"

L_.str.37:                              ## @.str.37
	.asciz	"disabled"

	.comm	_CPU_CONFIG_DC_PREF,4,2         ## @CPU_CONFIG_DC_PREF
	.comm	_CPU_L2_CONFIG,4,2              ## @CPU_L2_CONFIG
	.comm	_CPU_L2_CONFIG_MODE,4,2         ## @CPU_L2_CONFIG_MODE
L_.str.38:                              ## @.str.38
	.asciz	"  256KB 4-way set-associative %s unified L2 cache\n"

L_.str.39:                              ## @.str.39
	.asciz	"write-through"

L_.str.40:                              ## @.str.40
	.asciz	"write-back"

	.comm	_CPU_CONTROL,4,2                ## @CPU_CONTROL
	.comm	_CPU_CONTROL_L2_SIZE,4,2        ## @CPU_CONTROL_L2_SIZE
	.comm	_CPU_CONTROL_L2_MODE,4,2        ## @CPU_CONTROL_L2_MODE
L_.str.41:                              ## @.str.41
	.asciz	"  %s set-associative %s unified L2 cache\n"

L_.str.42:                              ## @.str.42
	.asciz	"256KB 4-way"

L_.str.43:                              ## @.str.43
	.asciz	"512KB 8-way"

	.no_dead_strip	_soc_identify
	.section	__TEXT,__const
	.p2align	2                               ## @reltable.soc_identify
l_reltable.soc_identify:
	.long	L_.str.8-l_reltable.soc_identify
	.long	L_.str.9-l_reltable.soc_identify
	.long	L_.str.10-l_reltable.soc_identify

	.p2align	2                               ## @reltable.soc_identify.45
l_reltable.soc_identify.45:
	.long	L_.str.12-l_reltable.soc_identify.45
	.long	L_.str.2-l_reltable.soc_identify.45
	.long	L_.str.13-l_reltable.soc_identify.45
	.long	L_.str.14-l_reltable.soc_identify.45

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function soc_identify
_soc_identify:                          ; @soc_identify
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_printf
Lloh2:
	adrp	x8, _bootverbose@GOTPAGE
Lloh3:
	ldr	x8, [x8, _bootverbose@GOTPAGEOFF]
Lloh4:
	ldr	x8, [x8]
	cbz	x8, LBB0_2
; %bb.1:
	stp	x19, x20, [sp]
Lloh5:
	adrp	x0, l_.str.1@PAGE
Lloh6:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_printf
LBB0_2:
	sub	w9, w19, #128
Lloh7:
	adrp	x21, l_.str.2@PAGE
Lloh8:
	add	x21, x21, l_.str.2@PAGEOFF
	cmp	w9, #16
	b.hi	LBB0_18
; %bb.3:
Lloh9:
	adrp	x8, l_.str.15@PAGE
Lloh10:
	add	x8, x8, l_.str.15@PAGEOFF
Lloh11:
	adrp	x10, lJTI0_0@PAGE
Lloh12:
	add	x10, x10, lJTI0_0@PAGEOFF
	adr	x11, LBB0_4
	ldrb	w12, [x10, x9]
	add	x11, x11, x12, lsl #2
	br	x11
LBB0_4:
Lloh13:
	adrp	x21, l_.str.2@PAGE
Lloh14:
	add	x21, x21, l_.str.2@PAGEOFF
Lloh15:
	adrp	x8, l_.str.28@PAGE
Lloh16:
	add	x8, x8, l_.str.28@PAGEOFF
	b	LBB0_32
LBB0_5:
Lloh17:
	adrp	x21, l_.str.2@PAGE
Lloh18:
	add	x21, x21, l_.str.2@PAGEOFF
Lloh19:
	adrp	x8, l_.str.27@PAGE
Lloh20:
	add	x8, x8, l_.str.27@PAGEOFF
	b	LBB0_32
LBB0_6:
Lloh21:
	adrp	x21, l_.str.2@PAGE
Lloh22:
	add	x21, x21, l_.str.2@PAGEOFF
Lloh23:
	adrp	x8, l_.str.26@PAGE
Lloh24:
	add	x8, x8, l_.str.26@PAGEOFF
	b	LBB0_32
LBB0_7:
Lloh25:
	adrp	x21, l_.str.2@PAGE
Lloh26:
	add	x21, x21, l_.str.2@PAGEOFF
Lloh27:
	adrp	x8, l_.str.24@PAGE
Lloh28:
	add	x8, x8, l_.str.24@PAGEOFF
	b	LBB0_32
LBB0_8:
Lloh29:
	adrp	x21, l_.str.2@PAGE
Lloh30:
	add	x21, x21, l_.str.2@PAGEOFF
Lloh31:
	adrp	x8, l_.str.16@PAGE
Lloh32:
	add	x8, x8, l_.str.16@PAGEOFF
	b	LBB0_32
LBB0_9:
Lloh33:
	adrp	x21, l_.str.2@PAGE
Lloh34:
	add	x21, x21, l_.str.2@PAGEOFF
Lloh35:
	adrp	x8, l_.str.22@PAGE
Lloh36:
	add	x8, x8, l_.str.22@PAGEOFF
	b	LBB0_32
LBB0_10:
Lloh37:
	adrp	x8, l_.str.19@PAGE
Lloh38:
	add	x8, x8, l_.str.19@PAGEOFF
	cmp	w20, #2
	csel	x21, x8, x21, eq
Lloh39:
	adrp	x8, l_.str.18@PAGE
Lloh40:
	add	x8, x8, l_.str.18@PAGEOFF
	b	LBB0_32
LBB0_11:
	cbz	w20, LBB0_29
; %bb.12:
	cmp	w20, #1
	b.ne	LBB0_30
; %bb.13:
Lloh41:
	adrp	x21, l_.str.14@PAGE
Lloh42:
	add	x21, x21, l_.str.14@PAGEOFF
	b	LBB0_31
LBB0_14:
	sub	w8, w20, #4
	cmp	w8, #3
	b.hs	LBB0_25
; %bb.15:
Lloh43:
	adrp	x9, l_switch.table.soc_identify@PAGE
Lloh44:
	add	x9, x9, l_switch.table.soc_identify@PAGEOFF
	ldr	x21, [x9, w8, sxtw #3]
	b	LBB0_26
LBB0_16:
Lloh45:
	adrp	x8, l_.str.6@PAGE
Lloh46:
	add	x8, x8, l_.str.6@PAGEOFF
	cmp	w20, #2
	csel	x21, x8, x21, eq
Lloh47:
	adrp	x8, l_.str.5@PAGE
Lloh48:
	add	x8, x8, l_.str.5@PAGEOFF
	b	LBB0_32
LBB0_17:
Lloh49:
	adrp	x8, l_.str.4@PAGE
Lloh50:
	add	x8, x8, l_.str.4@PAGEOFF
	cmp	w20, #3
	csel	x21, x8, x21, eq
Lloh51:
	adrp	x8, l_.str.3@PAGE
Lloh52:
	add	x8, x8, l_.str.3@PAGEOFF
	b	LBB0_32
LBB0_18:
Lloh53:
	adrp	x8, l_.str.29@PAGE
Lloh54:
	add	x8, x8, l_.str.29@PAGEOFF
	b	LBB0_32
LBB0_19:
Lloh55:
	adrp	x21, l_.str.2@PAGE
Lloh56:
	add	x21, x21, l_.str.2@PAGEOFF
Lloh57:
	adrp	x8, l_.str.25@PAGE
Lloh58:
	add	x8, x8, l_.str.25@PAGEOFF
	b	LBB0_32
LBB0_20:
Lloh59:
	adrp	x21, l_.str.2@PAGE
Lloh60:
	add	x21, x21, l_.str.2@PAGEOFF
Lloh61:
	adrp	x8, l_.str.17@PAGE
Lloh62:
	add	x8, x8, l_.str.17@PAGEOFF
	b	LBB0_32
LBB0_21:
Lloh63:
	adrp	x21, l_.str.2@PAGE
Lloh64:
	add	x21, x21, l_.str.2@PAGEOFF
Lloh65:
	adrp	x8, l_.str.21@PAGE
Lloh66:
	add	x8, x8, l_.str.21@PAGEOFF
	b	LBB0_32
LBB0_22:
Lloh67:
	adrp	x21, l_.str.2@PAGE
Lloh68:
	add	x21, x21, l_.str.2@PAGEOFF
Lloh69:
	adrp	x8, l_.str.23@PAGE
Lloh70:
	add	x8, x8, l_.str.23@PAGEOFF
	b	LBB0_32
LBB0_23:
	cmp	w20, #4
	b.hs	LBB0_27
; %bb.24:
Lloh71:
	adrp	x8, l_switch.table.soc_identify.44@PAGE
Lloh72:
	add	x8, x8, l_switch.table.soc_identify.44@PAGEOFF
	ldr	x21, [x8, w20, sxtw #3]
	b	LBB0_28
LBB0_25:
Lloh73:
	adrp	x21, l_.str.2@PAGE
Lloh74:
	add	x21, x21, l_.str.2@PAGEOFF
LBB0_26:
Lloh75:
	adrp	x8, l_.str.7@PAGE
Lloh76:
	add	x8, x8, l_.str.7@PAGEOFF
	b	LBB0_32
LBB0_27:
Lloh77:
	adrp	x21, l_.str.2@PAGE
Lloh78:
	add	x21, x21, l_.str.2@PAGEOFF
LBB0_28:
Lloh79:
	adrp	x8, l_.str.11@PAGE
Lloh80:
	add	x8, x8, l_.str.11@PAGEOFF
	b	LBB0_32
LBB0_29:
Lloh81:
	adrp	x21, l_.str.13@PAGE
Lloh82:
	add	x21, x21, l_.str.13@PAGEOFF
	b	LBB0_31
LBB0_30:
Lloh83:
	adrp	x21, l_.str.2@PAGE
Lloh84:
	add	x21, x21, l_.str.2@PAGEOFF
LBB0_31:
Lloh85:
	adrp	x8, l_.str.20@PAGE
Lloh86:
	add	x8, x8, l_.str.20@PAGEOFF
LBB0_32:
	str	x8, [sp]
Lloh87:
	adrp	x0, l_.str.30@PAGE
Lloh88:
	add	x0, x0, l_.str.30@PAGEOFF
	bl	_printf
	ldrb	w8, [x21]
	cbz	w8, LBB0_34
; %bb.33:
	str	x21, [sp]
Lloh89:
	adrp	x0, l_.str.31@PAGE
Lloh90:
	add	x0, x0, l_.str.31@PAGEOFF
	bl	_printf
LBB0_34:
	bl	_get_tclk
	mov	w8, #56963
	movk	w8, #17179, lsl #16
	smull	x8, w0, w8
	lsr	x9, x8, #63
	asr	x8, x8, #50
	add	w8, w8, w9
	str	x8, [sp]
Lloh91:
	adrp	x0, l_.str.32@PAGE
Lloh92:
	add	x0, x0, l_.str.32@PAGEOFF
	bl	_printf
	bl	_get_cpu_freq
	cbz	w0, LBB0_36
; %bb.35:
	mov	w8, #16960
	movk	w8, #15, lsl #16
	sdiv	w8, w0, w8
	str	x8, [sp]
Lloh93:
	adrp	x0, l_.str.33@PAGE
Lloh94:
	add	x0, x0, l_.str.33@PAGEOFF
	bl	_printf
LBB0_36:
	mov	w0, #10
	bl	_putchar
Lloh95:
	adrp	x8, _CPU_CONFIG@GOTPAGE
Lloh96:
	ldr	x8, [x8, _CPU_CONFIG@GOTPAGEOFF]
Lloh97:
	ldr	w0, [x8]
	bl	_read_cpu_ctrl
Lloh98:
	adrp	x8, _CPU_CONFIG_IC_PREF@GOTPAGE
Lloh99:
	ldr	x8, [x8, _CPU_CONFIG_IC_PREF@GOTPAGEOFF]
Lloh100:
	ldr	w8, [x8]
Lloh101:
	adrp	x9, l_.str.36@PAGE
Lloh102:
	add	x9, x9, l_.str.36@PAGEOFF
Lloh103:
	adrp	x10, l_.str.37@PAGE
Lloh104:
	add	x10, x10, l_.str.37@PAGEOFF
	tst	w8, w0
	csel	x8, x10, x9, eq
Lloh105:
	adrp	x11, _CPU_CONFIG_DC_PREF@GOTPAGE
Lloh106:
	ldr	x11, [x11, _CPU_CONFIG_DC_PREF@GOTPAGEOFF]
Lloh107:
	ldr	w11, [x11]
	tst	w11, w0
	csel	x9, x10, x9, eq
	stp	x8, x9, [sp]
Lloh108:
	adrp	x0, l_.str.35@PAGE
Lloh109:
	add	x0, x0, l_.str.35@PAGEOFF
	bl	_printf
	sub	w8, w19, #140
	cmp	w8, #2
	b.hs	LBB0_38
; %bb.37:
Lloh110:
	adrp	x8, _CPU_L2_CONFIG@GOTPAGE
Lloh111:
	ldr	x8, [x8, _CPU_L2_CONFIG@GOTPAGEOFF]
Lloh112:
	ldr	w0, [x8]
	bl	_read_cpu_ctrl
Lloh113:
	adrp	x8, _CPU_L2_CONFIG_MODE@GOTPAGE
Lloh114:
	ldr	x8, [x8, _CPU_L2_CONFIG_MODE@GOTPAGEOFF]
Lloh115:
	ldr	w8, [x8]
Lloh116:
	adrp	x9, l_.str.39@PAGE
Lloh117:
	add	x9, x9, l_.str.39@PAGEOFF
Lloh118:
	adrp	x10, l_.str.40@PAGE
Lloh119:
	add	x10, x10, l_.str.40@PAGEOFF
	tst	w8, w0
	csel	x8, x10, x9, eq
	str	x8, [sp]
Lloh120:
	adrp	x0, l_.str.38@PAGE
Lloh121:
	add	x0, x0, l_.str.38@PAGEOFF
	b	LBB0_40
LBB0_38:
	cmp	w19, #132
	b.ne	LBB0_41
; %bb.39:
Lloh122:
	adrp	x8, _CPU_CONTROL@GOTPAGE
Lloh123:
	ldr	x8, [x8, _CPU_CONTROL@GOTPAGEOFF]
Lloh124:
	ldr	w0, [x8]
	bl	_read_cpu_ctrl
Lloh125:
	adrp	x8, _CPU_CONTROL_L2_SIZE@GOTPAGE
Lloh126:
	ldr	x8, [x8, _CPU_CONTROL_L2_SIZE@GOTPAGEOFF]
Lloh127:
	ldr	w8, [x8]
Lloh128:
	adrp	x9, _CPU_CONTROL_L2_MODE@GOTPAGE
Lloh129:
	ldr	x9, [x9, _CPU_CONTROL_L2_MODE@GOTPAGEOFF]
Lloh130:
	ldr	w9, [x9]
Lloh131:
	adrp	x10, l_.str.42@PAGE
Lloh132:
	add	x10, x10, l_.str.42@PAGEOFF
Lloh133:
	adrp	x11, l_.str.43@PAGE
Lloh134:
	add	x11, x11, l_.str.43@PAGEOFF
	tst	w8, w0
	csel	x8, x11, x10, eq
Lloh135:
	adrp	x10, l_.str.39@PAGE
Lloh136:
	add	x10, x10, l_.str.39@PAGEOFF
Lloh137:
	adrp	x11, l_.str.40@PAGE
Lloh138:
	add	x11, x11, l_.str.40@PAGEOFF
	tst	w9, w0
	csel	x9, x11, x10, eq
	stp	x8, x9, [sp]
Lloh139:
	adrp	x0, l_.str.41@PAGE
Lloh140:
	add	x0, x0, l_.str.41@PAGEOFF
LBB0_40:
	bl	_printf
LBB0_41:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpAdd	Lloh7, Lloh8
	.loh AdrpAdd	Lloh11, Lloh12
	.loh AdrpAdd	Lloh9, Lloh10
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpAdd	Lloh13, Lloh14
	.loh AdrpAdd	Lloh19, Lloh20
	.loh AdrpAdd	Lloh17, Lloh18
	.loh AdrpAdd	Lloh23, Lloh24
	.loh AdrpAdd	Lloh21, Lloh22
	.loh AdrpAdd	Lloh27, Lloh28
	.loh AdrpAdd	Lloh25, Lloh26
	.loh AdrpAdd	Lloh31, Lloh32
	.loh AdrpAdd	Lloh29, Lloh30
	.loh AdrpAdd	Lloh35, Lloh36
	.loh AdrpAdd	Lloh33, Lloh34
	.loh AdrpAdd	Lloh39, Lloh40
	.loh AdrpAdd	Lloh37, Lloh38
	.loh AdrpAdd	Lloh41, Lloh42
	.loh AdrpAdd	Lloh43, Lloh44
	.loh AdrpAdd	Lloh47, Lloh48
	.loh AdrpAdd	Lloh45, Lloh46
	.loh AdrpAdd	Lloh51, Lloh52
	.loh AdrpAdd	Lloh49, Lloh50
	.loh AdrpAdd	Lloh53, Lloh54
	.loh AdrpAdd	Lloh57, Lloh58
	.loh AdrpAdd	Lloh55, Lloh56
	.loh AdrpAdd	Lloh61, Lloh62
	.loh AdrpAdd	Lloh59, Lloh60
	.loh AdrpAdd	Lloh65, Lloh66
	.loh AdrpAdd	Lloh63, Lloh64
	.loh AdrpAdd	Lloh69, Lloh70
	.loh AdrpAdd	Lloh67, Lloh68
	.loh AdrpAdd	Lloh71, Lloh72
	.loh AdrpAdd	Lloh73, Lloh74
	.loh AdrpAdd	Lloh75, Lloh76
	.loh AdrpAdd	Lloh77, Lloh78
	.loh AdrpAdd	Lloh79, Lloh80
	.loh AdrpAdd	Lloh81, Lloh82
	.loh AdrpAdd	Lloh83, Lloh84
	.loh AdrpAdd	Lloh85, Lloh86
	.loh AdrpAdd	Lloh87, Lloh88
	.loh AdrpAdd	Lloh89, Lloh90
	.loh AdrpAdd	Lloh91, Lloh92
	.loh AdrpAdd	Lloh93, Lloh94
	.loh AdrpAdd	Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpAdd	Lloh103, Lloh104
	.loh AdrpAdd	Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpAdd	Lloh120, Lloh121
	.loh AdrpAdd	Lloh118, Lloh119
	.loh AdrpAdd	Lloh116, Lloh117
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpAdd	Lloh139, Lloh140
	.loh AdrpAdd	Lloh137, Lloh138
	.loh AdrpAdd	Lloh135, Lloh136
	.loh AdrpAdd	Lloh133, Lloh134
	.loh AdrpAdd	Lloh131, Lloh132
	.loh AdrpLdrGotLdr	Lloh128, Lloh129, Lloh130
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_4-LBB0_4)>>2
	.byte	(LBB0_5-LBB0_4)>>2
	.byte	(LBB0_6-LBB0_4)>>2
	.byte	(LBB0_7-LBB0_4)>>2
	.byte	(LBB0_19-LBB0_4)>>2
	.byte	(LBB0_20-LBB0_4)>>2
	.byte	(LBB0_8-LBB0_4)>>2
	.byte	(LBB0_32-LBB0_4)>>2
	.byte	(LBB0_21-LBB0_4)>>2
	.byte	(LBB0_9-LBB0_4)>>2
	.byte	(LBB0_22-LBB0_4)>>2
	.byte	(LBB0_10-LBB0_4)>>2
	.byte	(LBB0_11-LBB0_4)>>2
	.byte	(LBB0_23-LBB0_4)>>2
	.byte	(LBB0_14-LBB0_4)>>2
	.byte	(LBB0_16-LBB0_4)>>2
	.byte	(LBB0_17-LBB0_4)>>2
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"SOC: "

	.comm	_bootverbose,8,3                ; @bootverbose
l_.str.1:                               ; @.str.1
	.asciz	"(0x%4x:0x%02x) "

l_.str.2:                               ; @.str.2
	.space	1

l_.str.3:                               ; @.str.3
	.asciz	"Marvell 88F5181"

l_.str.4:                               ; @.str.4
	.asciz	"B1"

l_.str.5:                               ; @.str.5
	.asciz	"Marvell 88F5182"

l_.str.6:                               ; @.str.6
	.asciz	"A2"

l_.str.7:                               ; @.str.7
	.asciz	"Marvell 88F5281"

l_.str.8:                               ; @.str.8
	.asciz	"D0"

l_.str.9:                               ; @.str.9
	.asciz	"D1"

l_.str.10:                              ; @.str.10
	.asciz	"D2"

l_.str.11:                              ; @.str.11
	.asciz	"Marvell 88F6281"

l_.str.12:                              ; @.str.12
	.asciz	"Z0"

l_.str.13:                              ; @.str.13
	.asciz	"A0"

l_.str.14:                              ; @.str.14
	.asciz	"A1"

l_.str.15:                              ; @.str.15
	.asciz	"Marvell 88RC8180"

l_.str.16:                              ; @.str.16
	.asciz	"Marvell 88RC9480"

l_.str.17:                              ; @.str.17
	.asciz	"Marvell 88RC9580"

l_.str.18:                              ; @.str.18
	.asciz	"Marvell 88F6781"

l_.str.19:                              ; @.str.19
	.asciz	"Y0"

l_.str.20:                              ; @.str.20
	.asciz	"Marvell 88F6282"

l_.str.21:                              ; @.str.21
	.asciz	"Marvell 88F6828"

l_.str.22:                              ; @.str.22
	.asciz	"Marvell 88F6820"

l_.str.23:                              ; @.str.23
	.asciz	"Marvell 88F6810"

l_.str.24:                              ; @.str.24
	.asciz	"Marvell MV78100 Z0"

l_.str.25:                              ; @.str.25
	.asciz	"Marvell MV78100"

l_.str.26:                              ; @.str.26
	.asciz	"Marvell MV78160"

l_.str.27:                              ; @.str.27
	.asciz	"Marvell MV78260"

l_.str.28:                              ; @.str.28
	.asciz	"Marvell MV78460"

l_.str.29:                              ; @.str.29
	.asciz	"UNKNOWN"

l_.str.30:                              ; @.str.30
	.asciz	"%s"

l_.str.31:                              ; @.str.31
	.asciz	" rev %s"

l_.str.32:                              ; @.str.32
	.asciz	", TClock %dMHz"

l_.str.33:                              ; @.str.33
	.asciz	", Frequency %dMHz"

	.comm	_CPU_CONFIG,4,2                 ; @CPU_CONFIG
l_.str.35:                              ; @.str.35
	.asciz	"  Instruction cache prefetch %s, data cache prefetch %s\n"

	.comm	_CPU_CONFIG_IC_PREF,4,2         ; @CPU_CONFIG_IC_PREF
l_.str.36:                              ; @.str.36
	.asciz	"enabled"

l_.str.37:                              ; @.str.37
	.asciz	"disabled"

	.comm	_CPU_CONFIG_DC_PREF,4,2         ; @CPU_CONFIG_DC_PREF
	.comm	_CPU_L2_CONFIG,4,2              ; @CPU_L2_CONFIG
	.comm	_CPU_L2_CONFIG_MODE,4,2         ; @CPU_L2_CONFIG_MODE
l_.str.38:                              ; @.str.38
	.asciz	"  256KB 4-way set-associative %s unified L2 cache\n"

l_.str.39:                              ; @.str.39
	.asciz	"write-through"

l_.str.40:                              ; @.str.40
	.asciz	"write-back"

	.comm	_CPU_CONTROL,4,2                ; @CPU_CONTROL
	.comm	_CPU_CONTROL_L2_SIZE,4,2        ; @CPU_CONTROL_L2_SIZE
	.comm	_CPU_CONTROL_L2_MODE,4,2        ; @CPU_CONTROL_L2_MODE
l_.str.41:                              ; @.str.41
	.asciz	"  %s set-associative %s unified L2 cache\n"

l_.str.42:                              ; @.str.42
	.asciz	"256KB 4-way"

l_.str.43:                              ; @.str.43
	.asciz	"512KB 8-way"

	.no_dead_strip	_soc_identify
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.soc_identify
l_switch.table.soc_identify:
	.quad	l_.str.8
	.quad	l_.str.9
	.quad	l_.str.10

	.p2align	3                               ; @switch.table.soc_identify.44
l_switch.table.soc_identify.44:
	.quad	l_.str.12
	.quad	l_.str.2
	.quad	l_.str.13
	.quad	l_.str.14

.subsections_via_symbols
