	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function aml8726_sdxc_update_ios
_aml8726_sdxc_update_ios:               ## @aml8726_sdxc_update_ios
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	callq	_device_get_softc
	movq	%rax, %r15
	movl	$-131, %eax
	addl	56(%r15), %eax
	cmpl	$3, %eax
	jae	LBB0_27
## %bb.1:
	movq	_AML_SDXC_CNTRL_RX_ENDIAN_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$7, %esi
	movl	$7, %edx
	shll	%cl, %edx
	movq	_AML_SDXC_CNTRL_TX_ENDIAN_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %esi
	movq	_AML_SDXC_CNTRL_RX_PERIOD_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$15, %edi
	shll	%cl, %edi
	orl	%edx, %esi
	movq	_AML_SDXC_CNTRL_RX_TIMEOUT_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$127, %edx
	shll	%cl, %edx
	orl	%edi, %edx
	orl	%esi, %edx
	cltq
	leaq	l_switch.table.aml8726_sdxc_update_ios(%rip), %rcx
	movq	(%rcx,%rax,8), %rax
	orl	(%rax), %edx
	movq	_AML_SDXC_CNTRL_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_CSR_WRITE_4
	movq	_AML_SDXC_CLK_CNTRL_REG@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_CSR_READ_4
	movq	_AML_SDXC_CLK_CNTRL_TX_CLK_EN@GOTPCREL(%rip), %rdx
	movq	_AML_SDXC_CLK_CNTRL_RX_CLK_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rdx), %ebx
	movq	_AML_SDXC_CLK_CNTRL_SD_CLK_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	(%r12), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_CSR_WRITE_4
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_CSR_BARRIER
	movq	_AML_SDXC_CLK_CNTRL_CLK_MODULE_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	notl	%r14d
	andl	%ebx, %r14d
	movl	(%r12), %esi
	movq	%r15, %rdi
	movl	%r14d, %edx
	callq	_CSR_WRITE_4
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_CSR_BARRIER
	movq	_AML_SDXC_CLK_CNTRL_CLK_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	%r14d, %esi
	movq	_AML_SDXC_CLK_CNTRL_CLK_SEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	btsl	%eax, %esi
	movl	(%r15), %ecx
	movl	60(%r15), %r8d
	movl	%ecx, %eax
	cltd
	idivl	%r8d
                                        ## kill: def $eax killed $eax def $rax
	leal	-1(%rax), %ebx
	cmpl	$2, %eax
	movl	$1, %r14d
	cmovbl	%r14d, %ebx
	leal	1(%rbx), %edi
	movl	%ecx, %eax
	xorl	%edx, %edx
	divl	%edi
	cmpl	%r8d, %eax
	cmoval	%edi, %ebx
	movq	_AML_SDXC_CLK_CNTRL_CLK_DIV_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_AML_SDXC_CLK_CNTRL_CLK_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	%eax, %r13d
	shrl	%cl, %r13d
	cmpl	%r13d, %ebx
	cmovbl	%ebx, %r13d
	notl	%eax
	andl	%esi, %eax
	movl	%r13d, %edx
	shll	%cl, %edx
	orl	%eax, %edx
	movq	_AML_SDXC_CLK_CNTRL_MEM_PWR_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	notl	%ebx
	andl	%edx, %ebx
	movq	_AML_SDXC_CLK_CNTRL_MEM_PWR_ON@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	(%r12), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_CSR_WRITE_4
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_CSR_BARRIER
	movq	_AML_SDXC_CLK_CNTRL_CLK_MODULE_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	(%r12), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_CSR_WRITE_4
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_CSR_BARRIER
	movq	_AML_SDXC_CLK_CNTRL_TX_CLK_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_AML_SDXC_CLK_CNTRL_RX_CLK_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_AML_SDXC_CLK_CNTRL_SD_CLK_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	(%r12), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_CSR_WRITE_4
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_CSR_BARRIER
	movl	(%r15), %eax
	xorl	%edx, %edx
	divl	%r13d
	movq	_aml8726_sdxc_clk_phases@GOTPCREL(%rip), %rcx
	movq	(%rcx), %r8
	movl	(%r8), %edi
	testl	%edi, %edi
	je	LBB0_2
## %bb.3:
	movb	64(%r15), %cl
	shll	%cl, %r14d
	leaq	12(%r8), %rsi
	xorl	%ecx, %ecx
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	testl	%edi, %r14d
	setne	%bl
	movl	-8(%rsi), %edi
	cmpl	%edi, %eax
	setg	%dl
	testb	%dl, %bl
	jne	LBB0_7
## %bb.5:                               ##   in Loop: Header=BB0_4 Depth=1
	testl	%edi, %edi
	je	LBB0_7
## %bb.6:                               ##   in Loop: Header=BB0_4 Depth=1
	incq	%rcx
	movl	(%rsi), %edi
	addq	$12, %rsi
	testl	%edi, %edi
	jne	LBB0_4
LBB0_7:
	movl	%ecx, %ecx
	jmp	LBB0_8
LBB0_2:
	xorl	%ecx, %ecx
LBB0_8:
	movq	_AML_SDXC_CLK2_SD_PHASE_SHIFT@GOTPCREL(%rip), %rax
	leaq	(%rcx,%rcx,2), %rcx
	movl	8(%r8,%rcx,4), %edx
	movq	_AML_SDXC_CLK2_RX_PHASE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	movb	(%rax), %al
	btsl	%eax, %edx
	movq	_AML_SDXC_CLK2_REG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_CSR_WRITE_4
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_CSR_BARRIER
	movl	68(%r15), %eax
	cmpl	$130, %eax
	je	LBB0_26
## %bb.9:
	cmpl	$129, %eax
	je	LBB0_16
## %bb.10:
	cmpl	$128, %eax
	jne	LBB0_27
## %bb.11:
	movq	48(%r15), %rdi
	testq	%rdi, %rdi
	je	LBB0_12
## %bb.13:
	movl	64(%r15), %ecx
	movl	$1, %eax
	shll	%cl, %eax
	movq	8(%r15), %rsi
	movl	(%rsi), %ebx
	xorl	%edx, %edx
	btl	%ecx, %ebx
	jb	LBB0_15
## %bb.14:
	movl	$1, %edx
	testl	%eax, 4(%rsi)
	je	LBB0_27
LBB0_15:
	movl	40(%r15), %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_GPIO_PIN_SET                   ## TAILCALL
LBB0_27:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
LBB0_28:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_26:
	movq	%r15, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_aml8726_sdxc_power_off         ## TAILCALL
LBB0_16:
	movq	%r15, %rdi
	callq	_aml8726_sdxc_power_on
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	LBB0_28
## %bb.17:
	movq	32(%r15), %rbx
	xorl	%r14d, %r14d
	testq	%rbx, %rbx
	je	LBB0_28
## %bb.18:
	movl	24(%r15), %edi
	movl	28(%r15), %r12d
	callq	_PIN_ON_FLAG
	movq	%rbx, %rdi
	movl	%r12d, %esi
	movl	%eax, %edx
	callq	_GPIO_PIN_SET
	testl	%eax, %eax
	jne	LBB0_21
## %bb.19:
	movq	32(%r15), %rdi
	movl	28(%r15), %esi
	movq	_GPIO_PIN_OUTPUT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_GPIO_PIN_SETFLAGS
	testl	%eax, %eax
	je	LBB0_20
LBB0_21:
	movq	_ENXIO@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
LBB0_22:
	movl	$5, %edi
	callq	_DELAY
	movq	32(%r15), %r12
	movl	24(%r15), %edi
	movl	28(%r15), %ebx
	callq	_PIN_OFF_FLAG
	movq	%r12, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_GPIO_PIN_SET
	testl	%eax, %eax
	je	LBB0_24
## %bb.23:
	movq	_ENXIO@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
LBB0_24:
	movl	$5, %edi
	callq	_DELAY
	testl	%r13d, %r13d
	je	LBB0_28
## %bb.25:
	movl	16(%r15), %edi
	leaq	L_.str(%rip), %rsi
	callq	_device_printf
	movl	%r13d, %r14d
	jmp	LBB0_28
LBB0_12:
	xorl	%r14d, %r14d
	jmp	LBB0_28
LBB0_20:
	xorl	%r13d, %r13d
	jmp	LBB0_22
	.cfi_endproc
                                        ## -- End function
	.comm	_AML_SDXC_CNTRL_TX_ENDIAN_SHIFT,4,2 ## @AML_SDXC_CNTRL_TX_ENDIAN_SHIFT
	.comm	_AML_SDXC_CNTRL_RX_ENDIAN_SHIFT,4,2 ## @AML_SDXC_CNTRL_RX_ENDIAN_SHIFT
	.comm	_AML_SDXC_CNTRL_RX_PERIOD_SHIFT,4,2 ## @AML_SDXC_CNTRL_RX_PERIOD_SHIFT
	.comm	_AML_SDXC_CNTRL_RX_TIMEOUT_SHIFT,4,2 ## @AML_SDXC_CNTRL_RX_TIMEOUT_SHIFT
	.comm	_AML_SDXC_CNTRL_BUS_WIDTH_8,4,2 ## @AML_SDXC_CNTRL_BUS_WIDTH_8
	.comm	_AML_SDXC_CNTRL_BUS_WIDTH_4,4,2 ## @AML_SDXC_CNTRL_BUS_WIDTH_4
	.comm	_AML_SDXC_CNTRL_BUS_WIDTH_1,4,2 ## @AML_SDXC_CNTRL_BUS_WIDTH_1
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_AML_SDXC_CNTRL_REG,4,2         ## @AML_SDXC_CNTRL_REG
	.comm	_AML_SDXC_CLK_CNTRL_REG,4,2     ## @AML_SDXC_CLK_CNTRL_REG
	.comm	_AML_SDXC_CLK_CNTRL_TX_CLK_EN,4,2 ## @AML_SDXC_CLK_CNTRL_TX_CLK_EN
	.comm	_AML_SDXC_CLK_CNTRL_RX_CLK_EN,4,2 ## @AML_SDXC_CLK_CNTRL_RX_CLK_EN
	.comm	_AML_SDXC_CLK_CNTRL_SD_CLK_EN,4,2 ## @AML_SDXC_CLK_CNTRL_SD_CLK_EN
	.comm	_AML_SDXC_CLK_CNTRL_CLK_MODULE_EN,4,2 ## @AML_SDXC_CLK_CNTRL_CLK_MODULE_EN
	.comm	_AML_SDXC_CLK_CNTRL_CLK_SEL_MASK,4,2 ## @AML_SDXC_CLK_CNTRL_CLK_SEL_MASK
	.comm	_AML_SDXC_CLK_CNTRL_CLK_SEL_SHIFT,4,2 ## @AML_SDXC_CLK_CNTRL_CLK_SEL_SHIFT
	.comm	_AML_SDXC_CLK_CNTRL_CLK_DIV_MASK,4,2 ## @AML_SDXC_CLK_CNTRL_CLK_DIV_MASK
	.comm	_AML_SDXC_CLK_CNTRL_CLK_DIV_SHIFT,4,2 ## @AML_SDXC_CLK_CNTRL_CLK_DIV_SHIFT
	.comm	_AML_SDXC_CLK_CNTRL_MEM_PWR_MASK,4,2 ## @AML_SDXC_CLK_CNTRL_MEM_PWR_MASK
	.comm	_AML_SDXC_CLK_CNTRL_MEM_PWR_ON,4,2 ## @AML_SDXC_CLK_CNTRL_MEM_PWR_ON
	.comm	_aml8726_sdxc_clk_phases,8,3    ## @aml8726_sdxc_clk_phases
	.comm	_AML_SDXC_CLK2_SD_PHASE_SHIFT,4,2 ## @AML_SDXC_CLK2_SD_PHASE_SHIFT
	.comm	_AML_SDXC_CLK2_RX_PHASE_SHIFT,4,2 ## @AML_SDXC_CLK2_RX_PHASE_SHIFT
	.comm	_AML_SDXC_CLK2_REG,4,2          ## @AML_SDXC_CLK2_REG
	.comm	_GPIO_PIN_OUTPUT,4,2            ## @GPIO_PIN_OUTPUT
	.comm	_ENXIO,4,2                      ## @ENXIO
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"could not use gpio to reset card\n"

	.no_dead_strip	_aml8726_sdxc_update_ios
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.aml8726_sdxc_update_ios
l_switch.table.aml8726_sdxc_update_ios:
	.quad	_AML_SDXC_CNTRL_BUS_WIDTH_8
	.quad	_AML_SDXC_CNTRL_BUS_WIDTH_4
	.quad	_AML_SDXC_CNTRL_BUS_WIDTH_1

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function aml8726_sdxc_update_ios
_aml8726_sdxc_update_ios:               ; @aml8726_sdxc_update_ios
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	bl	_device_get_softc
	ldr	w8, [x0, #56]
	sub	w8, w8, #131
	cmp	w8, #3
	b.hs	LBB0_25
; %bb.1:
	mov	x19, x0
Lloh0:
	adrp	x9, _AML_SDXC_CNTRL_RX_ENDIAN_SHIFT@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AML_SDXC_CNTRL_RX_ENDIAN_SHIFT@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	mov	w10, #7
	lsl	w9, w10, w9
Lloh3:
	adrp	x11, _AML_SDXC_CNTRL_TX_ENDIAN_SHIFT@GOTPAGE
Lloh4:
	ldr	x11, [x11, _AML_SDXC_CNTRL_TX_ENDIAN_SHIFT@GOTPAGEOFF]
Lloh5:
	ldr	w11, [x11]
	lsl	w10, w10, w11
	orr	w9, w9, w10
Lloh6:
	adrp	x10, _AML_SDXC_CNTRL_RX_PERIOD_SHIFT@GOTPAGE
Lloh7:
	ldr	x10, [x10, _AML_SDXC_CNTRL_RX_PERIOD_SHIFT@GOTPAGEOFF]
Lloh8:
	ldr	w10, [x10]
	mov	w11, #15
	lsl	w10, w11, w10
	orr	w9, w9, w10
Lloh9:
	adrp	x10, _AML_SDXC_CNTRL_RX_TIMEOUT_SHIFT@GOTPAGE
Lloh10:
	ldr	x10, [x10, _AML_SDXC_CNTRL_RX_TIMEOUT_SHIFT@GOTPAGEOFF]
Lloh11:
	ldr	w10, [x10]
	mov	w11, #127
	lsl	w10, w11, w10
Lloh12:
	adrp	x11, l_switch.table.aml8726_sdxc_update_ios@PAGE
Lloh13:
	add	x11, x11, l_switch.table.aml8726_sdxc_update_ios@PAGEOFF
	ldr	x8, [x11, w8, sxtw #3]
	orr	w9, w9, w10
	ldr	w8, [x8]
	orr	w2, w9, w8
Lloh14:
	adrp	x8, _AML_SDXC_CNTRL_REG@GOTPAGE
Lloh15:
	ldr	x8, [x8, _AML_SDXC_CNTRL_REG@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
	bl	_CSR_WRITE_4
Lloh17:
	adrp	x22, _AML_SDXC_CLK_CNTRL_REG@GOTPAGE
Lloh18:
	ldr	x22, [x22, _AML_SDXC_CLK_CNTRL_REG@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x19
	bl	_CSR_READ_4
Lloh19:
	adrp	x23, _AML_SDXC_CLK_CNTRL_TX_CLK_EN@GOTPAGE
Lloh20:
	ldr	x23, [x23, _AML_SDXC_CLK_CNTRL_TX_CLK_EN@GOTPAGEOFF]
	ldr	w8, [x23]
Lloh21:
	adrp	x24, _AML_SDXC_CLK_CNTRL_RX_CLK_EN@GOTPAGE
Lloh22:
	ldr	x24, [x24, _AML_SDXC_CLK_CNTRL_RX_CLK_EN@GOTPAGEOFF]
	ldr	w9, [x24]
	orr	w8, w9, w8
Lloh23:
	adrp	x25, _AML_SDXC_CLK_CNTRL_SD_CLK_EN@GOTPAGE
Lloh24:
	ldr	x25, [x25, _AML_SDXC_CLK_CNTRL_SD_CLK_EN@GOTPAGEOFF]
	ldr	w9, [x25]
	orr	w8, w8, w9
	bic	w20, w0, w8
	ldr	w1, [x22]
	mov	x0, x19
	mov	x2, x20
	bl	_CSR_WRITE_4
	ldr	w1, [x22]
	mov	x0, x19
	bl	_CSR_BARRIER
Lloh25:
	adrp	x27, _AML_SDXC_CLK_CNTRL_CLK_MODULE_EN@GOTPAGE
Lloh26:
	ldr	x27, [x27, _AML_SDXC_CLK_CNTRL_CLK_MODULE_EN@GOTPAGEOFF]
	ldr	w8, [x27]
	bic	w20, w20, w8
	ldr	w1, [x22]
	mov	x0, x19
	mov	x2, x20
	bl	_CSR_WRITE_4
	ldr	w1, [x22]
	mov	x0, x19
	bl	_CSR_BARRIER
Lloh27:
	adrp	x8, _AML_SDXC_CLK_CNTRL_CLK_SEL_MASK@GOTPAGE
Lloh28:
	ldr	x8, [x8, _AML_SDXC_CLK_CNTRL_CLK_SEL_MASK@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	bic	w8, w20, w8
Lloh30:
	adrp	x9, _AML_SDXC_CLK_CNTRL_CLK_SEL_SHIFT@GOTPAGE
Lloh31:
	ldr	x9, [x9, _AML_SDXC_CLK_CNTRL_CLK_SEL_SHIFT@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	mov	w21, #1
	lsl	w9, w21, w9
	orr	w8, w9, w8
	ldr	w9, [x19]
	ldr	w10, [x19, #60]
	sdiv	w11, w9, w10
	subs	w11, w11, #1
	csinc	w11, w11, wzr, hi
	add	w12, w11, #1
	udiv	w9, w9, w12
	cmp	w9, w10
	cinc	w9, w11, hi
Lloh33:
	adrp	x10, _AML_SDXC_CLK_CNTRL_CLK_DIV_MASK@GOTPAGE
Lloh34:
	ldr	x10, [x10, _AML_SDXC_CLK_CNTRL_CLK_DIV_MASK@GOTPAGEOFF]
Lloh35:
	ldr	w10, [x10]
Lloh36:
	adrp	x11, _AML_SDXC_CLK_CNTRL_CLK_DIV_SHIFT@GOTPAGE
Lloh37:
	ldr	x11, [x11, _AML_SDXC_CLK_CNTRL_CLK_DIV_SHIFT@GOTPAGEOFF]
Lloh38:
	ldr	w11, [x11]
	lsr	w12, w10, w11
	cmp	w9, w12
	csel	w26, w9, w12, lo
	bic	w8, w8, w10
	lsl	w9, w26, w11
	orr	w8, w9, w8
Lloh39:
	adrp	x9, _AML_SDXC_CLK_CNTRL_MEM_PWR_MASK@GOTPAGE
Lloh40:
	ldr	x9, [x9, _AML_SDXC_CLK_CNTRL_MEM_PWR_MASK@GOTPAGEOFF]
Lloh41:
	ldr	w9, [x9]
	bic	w8, w8, w9
Lloh42:
	adrp	x9, _AML_SDXC_CLK_CNTRL_MEM_PWR_ON@GOTPAGE
Lloh43:
	ldr	x9, [x9, _AML_SDXC_CLK_CNTRL_MEM_PWR_ON@GOTPAGEOFF]
Lloh44:
	ldr	w9, [x9]
	orr	w20, w8, w9
	ldr	w1, [x22]
	mov	x0, x19
	mov	x2, x20
	bl	_CSR_WRITE_4
	ldr	w1, [x22]
	mov	x0, x19
	bl	_CSR_BARRIER
	ldr	w8, [x27]
	orr	w20, w8, w20
	ldr	w1, [x22]
	mov	x0, x19
	mov	x2, x20
	bl	_CSR_WRITE_4
	ldr	w1, [x22]
	mov	x0, x19
	bl	_CSR_BARRIER
	ldr	w8, [x23]
	ldr	w9, [x24]
	ldr	w10, [x25]
	orr	w8, w8, w20
	orr	w8, w8, w9
	orr	w2, w8, w10
	ldr	w1, [x22]
	mov	x0, x19
	bl	_CSR_WRITE_4
	ldr	w1, [x22]
	mov	x0, x19
	bl	_CSR_BARRIER
Lloh45:
	adrp	x8, _aml8726_sdxc_clk_phases@GOTPAGE
Lloh46:
	ldr	x8, [x8, _aml8726_sdxc_clk_phases@GOTPAGEOFF]
Lloh47:
	ldr	x8, [x8]
	ldr	w12, [x8]
	cbz	w12, LBB0_6
; %bb.2:
	mov	x9, #0
	ldr	w13, [x19]
	ldr	w10, [x19, #64]
	lsl	w10, w21, w10
	add	x11, x8, #12
	udiv	w13, w13, w26
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	and	w12, w10, w12
	ldur	w14, [x11, #-8]
	cmp	w13, w14
	ccmp	w12, #0, #4, gt
	ccmp	w14, #0, #4, eq
	b.eq	LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	add	x9, x9, #1
	ldr	w12, [x11], #12
	cbnz	w12, LBB0_3
LBB0_5:
	and	x9, x9, #0xffffffff
	b	LBB0_7
LBB0_6:
	mov	x9, #0
LBB0_7:
Lloh48:
	adrp	x10, _AML_SDXC_CLK2_SD_PHASE_SHIFT@GOTPAGE
Lloh49:
	ldr	x10, [x10, _AML_SDXC_CLK2_SD_PHASE_SHIFT@GOTPAGEOFF]
Lloh50:
	ldr	w10, [x10]
	lsl	w10, w21, w10
	mov	w11, #12
	madd	x8, x9, x11, x8
	ldr	w8, [x8, #8]
Lloh51:
	adrp	x9, _AML_SDXC_CLK2_RX_PHASE_SHIFT@GOTPAGE
Lloh52:
	ldr	x9, [x9, _AML_SDXC_CLK2_RX_PHASE_SHIFT@GOTPAGEOFF]
Lloh53:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	orr	w2, w8, w10
Lloh54:
	adrp	x20, _AML_SDXC_CLK2_REG@GOTPAGE
Lloh55:
	ldr	x20, [x20, _AML_SDXC_CLK2_REG@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_CSR_WRITE_4
	ldr	w1, [x20]
	mov	x0, x19
	bl	_CSR_BARRIER
	ldr	w8, [x19, #68]
	cmp	w8, #130
	b.eq	LBB0_13
; %bb.8:
	cmp	w8, #129
	b.eq	LBB0_14
; %bb.9:
	cmp	w8, #128
	b.ne	LBB0_25
; %bb.10:
	ldr	x0, [x19, #48]
	cbz	x0, LBB0_21
; %bb.11:
	ldr	x8, [x19, #8]
	ldr	w9, [x19, #64]
	mov	w10, #1
	lsl	w9, w10, w9
	ldr	w10, [x8]
	tst	w9, w10
	b.eq	LBB0_22
; %bb.12:
	mov	w2, #0
	b	LBB0_24
LBB0_13:
	mov	x0, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_aml8726_sdxc_power_off
LBB0_14:
	mov	x0, x19
	bl	_aml8726_sdxc_power_on
	mov	x20, x0
	cbnz	w0, LBB0_26
; %bb.15:
	ldr	x20, [x19, #32]
	cbz	x20, LBB0_26
; %bb.16:
	ldp	w0, w21, [x19, #24]
	bl	_PIN_ON_FLAG
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_GPIO_PIN_SET
Lloh56:
	adrp	x22, _ENXIO@GOTPAGE
Lloh57:
	ldr	x22, [x22, _ENXIO@GOTPAGEOFF]
	cbnz	w0, LBB0_18
; %bb.17:
	ldr	x0, [x19, #32]
	ldr	w1, [x19, #28]
Lloh58:
	adrp	x8, _GPIO_PIN_OUTPUT@GOTPAGE
Lloh59:
	ldr	x8, [x8, _GPIO_PIN_OUTPUT@GOTPAGEOFF]
Lloh60:
	ldr	w2, [x8]
	bl	_GPIO_PIN_SETFLAGS
	cbz	w0, LBB0_27
LBB0_18:
	ldr	w23, [x22]
LBB0_19:
	mov	w0, #5
	bl	_DELAY
	ldr	x20, [x19, #32]
	ldp	w0, w21, [x19, #24]
	bl	_PIN_OFF_FLAG
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_GPIO_PIN_SET
	ldr	w8, [x22]
	cmp	w0, #0
	csel	w20, w23, w8, eq
	mov	w0, #5
	bl	_DELAY
	cbz	w20, LBB0_26
; %bb.20:
	ldr	w0, [x19, #16]
Lloh61:
	adrp	x1, l_.str@PAGE
Lloh62:
	add	x1, x1, l_.str@PAGEOFF
	bl	_device_printf
	b	LBB0_26
LBB0_21:
	mov	w20, #0
	b	LBB0_26
LBB0_22:
	ldr	w8, [x8, #4]
	tst	w9, w8
	b.eq	LBB0_25
; %bb.23:
	mov	w2, #1
LBB0_24:
	ldr	w1, [x19, #40]
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_GPIO_PIN_SET
LBB0_25:
Lloh63:
	adrp	x8, _EINVAL@GOTPAGE
Lloh64:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh65:
	ldr	w20, [x8]
LBB0_26:
	mov	x0, x20
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
LBB0_27:
	mov	w23, #0
	b	LBB0_19
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpAdd	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpAdd	Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.cfi_endproc
                                        ; -- End function
	.comm	_AML_SDXC_CNTRL_TX_ENDIAN_SHIFT,4,2 ; @AML_SDXC_CNTRL_TX_ENDIAN_SHIFT
	.comm	_AML_SDXC_CNTRL_RX_ENDIAN_SHIFT,4,2 ; @AML_SDXC_CNTRL_RX_ENDIAN_SHIFT
	.comm	_AML_SDXC_CNTRL_RX_PERIOD_SHIFT,4,2 ; @AML_SDXC_CNTRL_RX_PERIOD_SHIFT
	.comm	_AML_SDXC_CNTRL_RX_TIMEOUT_SHIFT,4,2 ; @AML_SDXC_CNTRL_RX_TIMEOUT_SHIFT
	.comm	_AML_SDXC_CNTRL_BUS_WIDTH_8,4,2 ; @AML_SDXC_CNTRL_BUS_WIDTH_8
	.comm	_AML_SDXC_CNTRL_BUS_WIDTH_4,4,2 ; @AML_SDXC_CNTRL_BUS_WIDTH_4
	.comm	_AML_SDXC_CNTRL_BUS_WIDTH_1,4,2 ; @AML_SDXC_CNTRL_BUS_WIDTH_1
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_AML_SDXC_CNTRL_REG,4,2         ; @AML_SDXC_CNTRL_REG
	.comm	_AML_SDXC_CLK_CNTRL_REG,4,2     ; @AML_SDXC_CLK_CNTRL_REG
	.comm	_AML_SDXC_CLK_CNTRL_TX_CLK_EN,4,2 ; @AML_SDXC_CLK_CNTRL_TX_CLK_EN
	.comm	_AML_SDXC_CLK_CNTRL_RX_CLK_EN,4,2 ; @AML_SDXC_CLK_CNTRL_RX_CLK_EN
	.comm	_AML_SDXC_CLK_CNTRL_SD_CLK_EN,4,2 ; @AML_SDXC_CLK_CNTRL_SD_CLK_EN
	.comm	_AML_SDXC_CLK_CNTRL_CLK_MODULE_EN,4,2 ; @AML_SDXC_CLK_CNTRL_CLK_MODULE_EN
	.comm	_AML_SDXC_CLK_CNTRL_CLK_SEL_MASK,4,2 ; @AML_SDXC_CLK_CNTRL_CLK_SEL_MASK
	.comm	_AML_SDXC_CLK_CNTRL_CLK_SEL_SHIFT,4,2 ; @AML_SDXC_CLK_CNTRL_CLK_SEL_SHIFT
	.comm	_AML_SDXC_CLK_CNTRL_CLK_DIV_MASK,4,2 ; @AML_SDXC_CLK_CNTRL_CLK_DIV_MASK
	.comm	_AML_SDXC_CLK_CNTRL_CLK_DIV_SHIFT,4,2 ; @AML_SDXC_CLK_CNTRL_CLK_DIV_SHIFT
	.comm	_AML_SDXC_CLK_CNTRL_MEM_PWR_MASK,4,2 ; @AML_SDXC_CLK_CNTRL_MEM_PWR_MASK
	.comm	_AML_SDXC_CLK_CNTRL_MEM_PWR_ON,4,2 ; @AML_SDXC_CLK_CNTRL_MEM_PWR_ON
	.comm	_aml8726_sdxc_clk_phases,8,3    ; @aml8726_sdxc_clk_phases
	.comm	_AML_SDXC_CLK2_SD_PHASE_SHIFT,4,2 ; @AML_SDXC_CLK2_SD_PHASE_SHIFT
	.comm	_AML_SDXC_CLK2_RX_PHASE_SHIFT,4,2 ; @AML_SDXC_CLK2_RX_PHASE_SHIFT
	.comm	_AML_SDXC_CLK2_REG,4,2          ; @AML_SDXC_CLK2_REG
	.comm	_GPIO_PIN_OUTPUT,4,2            ; @GPIO_PIN_OUTPUT
	.comm	_ENXIO,4,2                      ; @ENXIO
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"could not use gpio to reset card\n"

	.no_dead_strip	_aml8726_sdxc_update_ios
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.aml8726_sdxc_update_ios
l_switch.table.aml8726_sdxc_update_ios:
	.quad	_AML_SDXC_CNTRL_BUS_WIDTH_8
	.quad	_AML_SDXC_CNTRL_BUS_WIDTH_4
	.quad	_AML_SDXC_CNTRL_BUS_WIDTH_1

.subsections_via_symbols
