	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function spi_calc_clockdiv
_spi_calc_clockdiv:                     ## @spi_calc_clockdiv
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	subq	$16, %rsp
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movl	(%rdi), %r9d
	xorl	%r14d, %r14d
	cmpl	%esi, %r9d
	jle	LBB0_36
## %bb.1:
	movl	%esi, %r8d
	movl	%r9d, %eax
	cltd
	idivl	%esi
	cmpl	$17, %eax
	jge	LBB0_3
## %bb.2:
	xorl	%r14d, %r14d
	jmp	LBB0_32
LBB0_3:
	movl	%r9d, %eax
	sarl	%eax
	cltd
	idivl	%r8d
	cmpl	$17, %eax
	jge	LBB0_5
## %bb.4:
	movl	$1, %r14d
	jmp	LBB0_32
LBB0_5:
	movl	%r9d, %eax
	sarl	$2, %eax
	cltd
	idivl	%r8d
	cmpl	$17, %eax
	jge	LBB0_7
## %bb.6:
	movl	$2, %r14d
	jmp	LBB0_32
LBB0_7:
	movl	%r9d, %eax
	sarl	$3, %eax
	cltd
	idivl	%r8d
	cmpl	$17, %eax
	jge	LBB0_9
## %bb.8:
	movl	$3, %r14d
	jmp	LBB0_32
LBB0_9:
	movl	%r9d, %eax
	sarl	$4, %eax
	cltd
	idivl	%r8d
	cmpl	$17, %eax
	jge	LBB0_11
## %bb.10:
	movl	$4, %r14d
	jmp	LBB0_32
LBB0_11:
	movl	%r9d, %eax
	sarl	$5, %eax
	cltd
	idivl	%r8d
	cmpl	$17, %eax
	jge	LBB0_13
## %bb.12:
	movl	$5, %r14d
	jmp	LBB0_32
LBB0_13:
	movl	%r9d, %eax
	sarl	$6, %eax
	cltd
	idivl	%r8d
	cmpl	$17, %eax
	jge	LBB0_15
## %bb.14:
	movl	$6, %r14d
	jmp	LBB0_32
LBB0_15:
	movl	%r9d, %eax
	sarl	$7, %eax
	cltd
	idivl	%r8d
	cmpl	$17, %eax
	jge	LBB0_17
## %bb.16:
	movl	$7, %r14d
	jmp	LBB0_32
LBB0_17:
	movl	%r9d, %eax
	sarl	$8, %eax
	cltd
	idivl	%r8d
	cmpl	$17, %eax
	jge	LBB0_19
## %bb.18:
	movl	$8, %r14d
	jmp	LBB0_32
LBB0_19:
	movl	%r9d, %eax
	sarl	$9, %eax
	cltd
	idivl	%r8d
	cmpl	$17, %eax
	jge	LBB0_21
## %bb.20:
	movl	$9, %r14d
	jmp	LBB0_32
LBB0_21:
	movl	%r9d, %eax
	sarl	$10, %eax
	cltd
	idivl	%r8d
	cmpl	$17, %eax
	jge	LBB0_23
## %bb.22:
	movl	$10, %r14d
	jmp	LBB0_32
LBB0_23:
	movl	%r9d, %eax
	sarl	$11, %eax
	cltd
	idivl	%r8d
	cmpl	$17, %eax
	jge	LBB0_25
## %bb.24:
	movl	$11, %r14d
	jmp	LBB0_32
LBB0_25:
	movl	%r9d, %eax
	sarl	$12, %eax
	cltd
	idivl	%r8d
	cmpl	$17, %eax
	jge	LBB0_27
## %bb.26:
	movl	$12, %r14d
	jmp	LBB0_32
LBB0_27:
	movl	%r9d, %eax
	sarl	$13, %eax
	cltd
	idivl	%r8d
	cmpl	$17, %eax
	jge	LBB0_29
## %bb.28:
	movl	$13, %r14d
	jmp	LBB0_32
LBB0_29:
	movl	%r9d, %eax
	sarl	$14, %eax
	cltd
	idivl	%r8d
	cmpl	$17, %eax
	jge	LBB0_31
## %bb.30:
	movl	$14, %r14d
	jmp	LBB0_32
LBB0_31:
	movl	%r9d, %eax
	sarl	$15, %eax
	cltd
	idivl	%r8d
	movl	$15, %r14d
	movl	$15, %ebx
	cmpl	$16, %eax
	jg	LBB0_33
LBB0_32:
	decl	%eax
	movl	%eax, %ebx
LBB0_33:
	cmpl	$2, 4(%rdi)
	jl	LBB0_35
## %bb.34:
	movl	8(%rdi), %edi
	leal	1(%rbx), %r10d
	movl	$1, %esi
	movl	%r14d, %ecx
	shll	%cl, %esi
	movl	%r9d, %eax
	cltd
	idivl	%r10d
	cltd
	idivl	%esi
	movl	%eax, (%rsp)
	leaq	L_.str(%rip), %rsi
	movl	%r9d, %edx
	movl	%r8d, %ecx
	movl	%ebx, %r8d
	movl	%r14d, %r9d
	callq	_device_printf
LBB0_35:
	movq	_CTLREG_PREDIV_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %ebx
	movq	_CTLREG_POSTDIV_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r14d
	orl	%ebx, %r14d
LBB0_36:
	movl	%r14d, %eax
	addq	$16, %rsp
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"base %u bus %u; pre %u, post %u; actual busfreq %u\n"

	.comm	_CTLREG_PREDIV_SHIFT,4,2        ## @CTLREG_PREDIV_SHIFT
	.comm	_CTLREG_POSTDIV_SHIFT,4,2       ## @CTLREG_POSTDIV_SHIFT
	.no_dead_strip	_spi_calc_clockdiv
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function spi_calc_clockdiv
_spi_calc_clockdiv:                     ; @spi_calc_clockdiv
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	w2, [x0]
	cmp	w2, w1
	b.le	LBB0_3
; %bb.1:
	mov	x3, x1
	sdiv	w8, w2, w1
	cmp	w8, #17
	b.ge	LBB0_4
; %bb.2:
	mov	w19, #0
	b	LBB0_33
LBB0_3:
	mov	w0, #0
	b	LBB0_37
LBB0_4:
	asr	w8, w2, #1
	sdiv	w8, w8, w3
	cmp	w8, #17
	b.ge	LBB0_6
; %bb.5:
	mov	w19, #1
	b	LBB0_33
LBB0_6:
	asr	w8, w2, #2
	sdiv	w8, w8, w3
	cmp	w8, #17
	b.ge	LBB0_8
; %bb.7:
	mov	w19, #2
	b	LBB0_33
LBB0_8:
	asr	w8, w2, #3
	sdiv	w8, w8, w3
	cmp	w8, #17
	b.ge	LBB0_10
; %bb.9:
	mov	w19, #3
	b	LBB0_33
LBB0_10:
	asr	w8, w2, #4
	sdiv	w8, w8, w3
	cmp	w8, #17
	b.ge	LBB0_12
; %bb.11:
	mov	w19, #4
	b	LBB0_33
LBB0_12:
	asr	w8, w2, #5
	sdiv	w8, w8, w3
	cmp	w8, #17
	b.ge	LBB0_14
; %bb.13:
	mov	w19, #5
	b	LBB0_33
LBB0_14:
	asr	w8, w2, #6
	sdiv	w8, w8, w3
	cmp	w8, #17
	b.ge	LBB0_16
; %bb.15:
	mov	w19, #6
	b	LBB0_33
LBB0_16:
	asr	w8, w2, #7
	sdiv	w8, w8, w3
	cmp	w8, #17
	b.ge	LBB0_18
; %bb.17:
	mov	w19, #7
	b	LBB0_33
LBB0_18:
	asr	w8, w2, #8
	sdiv	w8, w8, w3
	cmp	w8, #17
	b.ge	LBB0_20
; %bb.19:
	mov	w19, #8
	b	LBB0_33
LBB0_20:
	asr	w8, w2, #9
	sdiv	w8, w8, w3
	cmp	w8, #17
	b.ge	LBB0_22
; %bb.21:
	mov	w19, #9
	b	LBB0_33
LBB0_22:
	asr	w8, w2, #10
	sdiv	w8, w8, w3
	cmp	w8, #17
	b.ge	LBB0_24
; %bb.23:
	mov	w19, #10
	b	LBB0_33
LBB0_24:
	asr	w8, w2, #11
	sdiv	w8, w8, w3
	cmp	w8, #17
	b.ge	LBB0_26
; %bb.25:
	mov	w19, #11
	b	LBB0_33
LBB0_26:
	asr	w8, w2, #12
	sdiv	w8, w8, w3
	cmp	w8, #17
	b.ge	LBB0_28
; %bb.27:
	mov	w19, #12
	b	LBB0_33
LBB0_28:
	asr	w8, w2, #13
	sdiv	w8, w8, w3
	cmp	w8, #17
	b.ge	LBB0_30
; %bb.29:
	mov	w19, #13
	b	LBB0_33
LBB0_30:
	asr	w8, w2, #14
	sdiv	w8, w8, w3
	cmp	w8, #17
	b.ge	LBB0_32
; %bb.31:
	mov	w19, #14
	b	LBB0_33
LBB0_32:
	asr	w8, w2, #15
	sdiv	w8, w8, w3
	mov	w19, #15
	mov	w20, #15
	cmp	w8, #16
	b.gt	LBB0_34
LBB0_33:
	sub	w20, w8, #1
LBB0_34:
	ldr	w8, [x0, #4]
	cmp	w8, #2
	b.lt	LBB0_36
; %bb.35:
	ldr	w0, [x0, #8]
	add	w8, w20, #1
	sdiv	w8, w2, w8
	mov	w9, #1
	lsl	w9, w9, w19
	sdiv	w6, w8, w9
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	mov	x4, x20
	mov	x5, x19
	bl	_device_printf
LBB0_36:
Lloh2:
	adrp	x8, _CTLREG_PREDIV_SHIFT@GOTPAGE
Lloh3:
	ldr	x8, [x8, _CTLREG_PREDIV_SHIFT@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	lsl	w8, w20, w8
Lloh5:
	adrp	x9, _CTLREG_POSTDIV_SHIFT@GOTPAGE
Lloh6:
	ldr	x9, [x9, _CTLREG_POSTDIV_SHIFT@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	lsl	w9, w19, w9
	orr	w0, w9, w8
LBB0_37:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"base %u bus %u; pre %u, post %u; actual busfreq %u\n"

	.comm	_CTLREG_PREDIV_SHIFT,4,2        ; @CTLREG_PREDIV_SHIFT
	.comm	_CTLREG_POSTDIV_SHIFT,4,2       ; @CTLREG_POSTDIV_SHIFT
	.no_dead_strip	_spi_calc_clockdiv
.subsections_via_symbols
