	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mv_watchdog_enable_armv5
_mv_watchdog_enable_armv5:              ## @mv_watchdog_enable_armv5
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	_timer_softc@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rax
	movq	(%rax), %rax
	movl	4(%rax), %edi
	callq	_read_cpu_ctrl
	movq	(%rbx), %rcx
	movq	(%rcx), %rcx
	andl	(%rcx), %eax
	movl	4(%rcx), %edi
	movl	%eax, %esi
	callq	_write_cpu_ctrl
	movq	_BRIDGE_IRQ_MASK@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_read_cpu_ctrl
	movq	_IRQ_TIMER_WD_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_write_cpu_ctrl
	movq	_RSTOUTn_MASK@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_read_cpu_ctrl
	movq	_WD_RST_OUT_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_write_cpu_ctrl
	xorl	%eax, %eax
	callq	_mv_get_timer_control
	movq	_CPU_TIMER2_EN@GOTPCREL(%rip), %rcx
	movq	_CPU_TIMER2_AUTO@GOTPCREL(%rip), %rdx
	orl	(%rcx), %eax
	orl	(%rdx), %eax
	movl	%eax, %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_mv_set_timer_control           ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_timer_softc,8,3                ## @timer_softc
	.comm	_BRIDGE_IRQ_MASK,4,2            ## @BRIDGE_IRQ_MASK
	.comm	_IRQ_TIMER_WD_MASK,4,2          ## @IRQ_TIMER_WD_MASK
	.comm	_RSTOUTn_MASK,4,2               ## @RSTOUTn_MASK
	.comm	_WD_RST_OUT_EN,4,2              ## @WD_RST_OUT_EN
	.comm	_CPU_TIMER2_EN,4,2              ## @CPU_TIMER2_EN
	.comm	_CPU_TIMER2_AUTO,4,2            ## @CPU_TIMER2_AUTO
	.no_dead_strip	_mv_watchdog_enable_armv5
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mv_watchdog_enable_armv5
_mv_watchdog_enable_armv5:              ; @mv_watchdog_enable_armv5
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
Lloh0:
	adrp	x19, _timer_softc@GOTPAGE
Lloh1:
	ldr	x19, [x19, _timer_softc@GOTPAGEOFF]
	ldr	x8, [x19]
	ldr	x8, [x8]
	ldr	w0, [x8, #4]
	bl	_read_cpu_ctrl
	ldr	x8, [x19]
	ldr	x8, [x8]
	ldp	w9, w8, [x8]
	and	w1, w9, w0
	mov	x0, x8
	bl	_write_cpu_ctrl
Lloh2:
	adrp	x19, _BRIDGE_IRQ_MASK@GOTPAGE
Lloh3:
	ldr	x19, [x19, _BRIDGE_IRQ_MASK@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_read_cpu_ctrl
Lloh4:
	adrp	x8, _IRQ_TIMER_WD_MASK@GOTPAGE
Lloh5:
	ldr	x8, [x8, _IRQ_TIMER_WD_MASK@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x19]
	bl	_write_cpu_ctrl
Lloh7:
	adrp	x19, _RSTOUTn_MASK@GOTPAGE
Lloh8:
	ldr	x19, [x19, _RSTOUTn_MASK@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_read_cpu_ctrl
Lloh9:
	adrp	x8, _WD_RST_OUT_EN@GOTPAGE
Lloh10:
	ldr	x8, [x8, _WD_RST_OUT_EN@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x19]
	bl	_write_cpu_ctrl
	bl	_mv_get_timer_control
Lloh12:
	adrp	x8, _CPU_TIMER2_EN@GOTPAGE
Lloh13:
	ldr	x8, [x8, _CPU_TIMER2_EN@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
Lloh15:
	adrp	x9, _CPU_TIMER2_AUTO@GOTPAGE
Lloh16:
	ldr	x9, [x9, _CPU_TIMER2_AUTO@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w0, w8, w9
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_mv_set_timer_control
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_timer_softc,8,3                ; @timer_softc
	.comm	_BRIDGE_IRQ_MASK,4,2            ; @BRIDGE_IRQ_MASK
	.comm	_IRQ_TIMER_WD_MASK,4,2          ; @IRQ_TIMER_WD_MASK
	.comm	_RSTOUTn_MASK,4,2               ; @RSTOUTn_MASK
	.comm	_WD_RST_OUT_EN,4,2              ; @WD_RST_OUT_EN
	.comm	_CPU_TIMER2_EN,4,2              ; @CPU_TIMER2_EN
	.comm	_CPU_TIMER2_AUTO,4,2            ; @CPU_TIMER2_AUTO
	.no_dead_strip	_mv_watchdog_enable_armv5
.subsections_via_symbols
