	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_imx_ccm_hdmi_enable            ## -- Begin function imx_ccm_hdmi_enable
	.p2align	4, 0x90
_imx_ccm_hdmi_enable:                   ## @imx_ccm_hdmi_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_ccm_sc@GOTPCREL(%rip), %rax
	movq	(%rax), %r14
	movq	_CCM_CCGR2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_RD4
	movq	_CCGR2_HDMI_TX@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_CCGR2_HDMI_TX_ISFR@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %esi
	movq	%r14, %rdi
	movl	%eax, %edx
	callq	_WR4
	movq	_CCM_CHSCCDR@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_RD4
	movq	_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK@GOTPCREL(%rip), %rcx
	movq	_CHSCCDR_IPU1_DI0_PODF_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	movq	_CHSCCDR_IPU1_DI0_CLK_SEL_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	_CHSCCDR_PODF_DIVIDE_BY_3@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_CHSCCDR_IPU1_DI0_PODF_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %esi
	notl	%edx
	movq	_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movq	_CHSCCDR_IPU_PRE_CLK_540M_PFD@GOTPCREL(%rip), %rdi
	movl	(%rdi), %ebx
	shll	%cl, %ebx
	andl	%eax, %edx
	orl	%esi, %ebx
	orl	%edx, %ebx
	movl	(%r15), %esi
	movq	%r14, %rdi
	movl	%ebx, %edx
	callq	_WR4
	movq	_CHSCCDR_CLK_SEL_LDB_DI0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %edx
	orl	%ebx, %edx
	movl	(%r15), %esi
	movq	%r14, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WR4                            ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_ccm_sc,8,3                     ## @ccm_sc
	.comm	_CCM_CCGR2,4,2                  ## @CCM_CCGR2
	.comm	_CCGR2_HDMI_TX,4,2              ## @CCGR2_HDMI_TX
	.comm	_CCGR2_HDMI_TX_ISFR,4,2         ## @CCGR2_HDMI_TX_ISFR
	.comm	_CCM_CHSCCDR,4,2                ## @CCM_CHSCCDR
	.comm	_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK,4,2 ## @CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
	.comm	_CHSCCDR_IPU1_DI0_PODF_MASK,4,2 ## @CHSCCDR_IPU1_DI0_PODF_MASK
	.comm	_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,4,2 ## @CHSCCDR_IPU1_DI0_CLK_SEL_MASK
	.comm	_CHSCCDR_PODF_DIVIDE_BY_3,4,2   ## @CHSCCDR_PODF_DIVIDE_BY_3
	.comm	_CHSCCDR_IPU1_DI0_PODF_SHIFT,4,2 ## @CHSCCDR_IPU1_DI0_PODF_SHIFT
	.comm	_CHSCCDR_IPU_PRE_CLK_540M_PFD,4,2 ## @CHSCCDR_IPU_PRE_CLK_540M_PFD
	.comm	_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT,4,2 ## @CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT
	.comm	_CHSCCDR_CLK_SEL_LDB_DI0,4,2    ## @CHSCCDR_CLK_SEL_LDB_DI0
	.comm	_CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT,4,2 ## @CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_imx_ccm_hdmi_enable            ; -- Begin function imx_ccm_hdmi_enable
	.p2align	2
_imx_ccm_hdmi_enable:                   ; @imx_ccm_hdmi_enable
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
Lloh0:
	adrp	x8, _ccm_sc@GOTPAGE
Lloh1:
	ldr	x8, [x8, _ccm_sc@GOTPAGEOFF]
Lloh2:
	ldr	x19, [x8]
Lloh3:
	adrp	x20, _CCM_CCGR2@GOTPAGE
Lloh4:
	ldr	x20, [x20, _CCM_CCGR2@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_RD4
Lloh5:
	adrp	x8, _CCGR2_HDMI_TX@GOTPAGE
Lloh6:
	ldr	x8, [x8, _CCGR2_HDMI_TX@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
Lloh8:
	adrp	x9, _CCGR2_HDMI_TX_ISFR@GOTPAGE
Lloh9:
	ldr	x9, [x9, _CCGR2_HDMI_TX_ISFR@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w2, w8, w9
	ldr	w1, [x20]
	mov	x0, x19
	bl	_WR4
Lloh11:
	adrp	x21, _CCM_CHSCCDR@GOTPAGE
Lloh12:
	ldr	x21, [x21, _CCM_CHSCCDR@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_RD4
Lloh13:
	adrp	x8, _CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK@GOTPAGE
Lloh14:
	ldr	x8, [x8, _CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
Lloh16:
	adrp	x9, _CHSCCDR_IPU1_DI0_PODF_MASK@GOTPAGE
Lloh17:
	ldr	x9, [x9, _CHSCCDR_IPU1_DI0_PODF_MASK@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh19:
	adrp	x9, _CHSCCDR_IPU1_DI0_CLK_SEL_MASK@GOTPAGE
Lloh20:
	ldr	x9, [x9, _CHSCCDR_IPU1_DI0_CLK_SEL_MASK@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w8, w0, w8
Lloh22:
	adrp	x9, _CHSCCDR_PODF_DIVIDE_BY_3@GOTPAGE
Lloh23:
	ldr	x9, [x9, _CHSCCDR_PODF_DIVIDE_BY_3@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
Lloh25:
	adrp	x10, _CHSCCDR_IPU1_DI0_PODF_SHIFT@GOTPAGE
Lloh26:
	ldr	x10, [x10, _CHSCCDR_IPU1_DI0_PODF_SHIFT@GOTPAGEOFF]
Lloh27:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w8, w9, w8
Lloh28:
	adrp	x9, _CHSCCDR_IPU_PRE_CLK_540M_PFD@GOTPAGE
Lloh29:
	ldr	x9, [x9, _CHSCCDR_IPU_PRE_CLK_540M_PFD@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
Lloh31:
	adrp	x10, _CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT@GOTPAGE
Lloh32:
	ldr	x10, [x10, _CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT@GOTPAGEOFF]
Lloh33:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w20, w8, w9
	ldr	w1, [x21]
	mov	x0, x19
	mov	x2, x20
	bl	_WR4
Lloh34:
	adrp	x8, _CHSCCDR_CLK_SEL_LDB_DI0@GOTPAGE
Lloh35:
	ldr	x8, [x8, _CHSCCDR_CLK_SEL_LDB_DI0@GOTPAGEOFF]
Lloh36:
	ldr	w8, [x8]
Lloh37:
	adrp	x9, _CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT@GOTPAGE
Lloh38:
	ldr	x9, [x9, _CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT@GOTPAGEOFF]
Lloh39:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	orr	w2, w8, w20
	ldr	w1, [x21]
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WR4
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_ccm_sc,8,3                     ; @ccm_sc
	.comm	_CCM_CCGR2,4,2                  ; @CCM_CCGR2
	.comm	_CCGR2_HDMI_TX,4,2              ; @CCGR2_HDMI_TX
	.comm	_CCGR2_HDMI_TX_ISFR,4,2         ; @CCGR2_HDMI_TX_ISFR
	.comm	_CCM_CHSCCDR,4,2                ; @CCM_CHSCCDR
	.comm	_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK,4,2 ; @CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
	.comm	_CHSCCDR_IPU1_DI0_PODF_MASK,4,2 ; @CHSCCDR_IPU1_DI0_PODF_MASK
	.comm	_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,4,2 ; @CHSCCDR_IPU1_DI0_CLK_SEL_MASK
	.comm	_CHSCCDR_PODF_DIVIDE_BY_3,4,2   ; @CHSCCDR_PODF_DIVIDE_BY_3
	.comm	_CHSCCDR_IPU1_DI0_PODF_SHIFT,4,2 ; @CHSCCDR_IPU1_DI0_PODF_SHIFT
	.comm	_CHSCCDR_IPU_PRE_CLK_540M_PFD,4,2 ; @CHSCCDR_IPU_PRE_CLK_540M_PFD
	.comm	_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT,4,2 ; @CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT
	.comm	_CHSCCDR_CLK_SEL_LDB_DI0,4,2    ; @CHSCCDR_CLK_SEL_LDB_DI0
	.comm	_CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT,4,2 ; @CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT
.subsections_via_symbols
