	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mlx4_cq_read_wc_flags
_mlx4_cq_read_wc_flags:                 ## @mlx4_cq_read_wc_flags
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	callq	_ibv_cq_ex_to_cq
	movl	%eax, %edi
	callq	_to_mcq
	movq	%rax, %rbx
	movq	8(%rax), %rax
	movl	(%rax), %ecx
	movq	_MLX4_CQE_IS_SEND_MASK@GOTPCREL(%rip), %rdx
	testl	%ecx, (%rdx)
	je	LBB0_3
## %bb.1:
	movq	_MLX4_CQE_OPCODE_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %ecx
	addl	$-131, %ecx
	xorl	%eax, %eax
	cmpl	$2, %ecx
	jae	LBB0_11
## %bb.2:
	movq	_IBV_WC_WITH_IMM@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	jmp	LBB0_11
LBB0_3:
	movq	_MLX4_CQ_FLAGS_RX_CSUM_VALID@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	testl	%edx, (%rbx)
	je	LBB0_4
## %bb.5:
	movl	4(%rax), %r15d
	movq	_MLX4_CQE_STATUS_IPV4_CSUM_OK@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_htobe32
	movl	%eax, %r14d
	andl	%r15d, %r14d
	movl	(%r12), %edi
	callq	_htobe32
	xorl	%r15d, %r15d
	cmpl	%eax, %r14d
	sete	%r15b
	movq	_IBV_WC_IP_CSUM_OK_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r15d
	movq	8(%rbx), %rax
	movl	(%rax), %ecx
	jmp	LBB0_6
LBB0_4:
	xorl	%r15d, %r15d
LBB0_6:
	movq	_MLX4_CQE_OPCODE_MASK@GOTPCREL(%rip), %rdx
	andl	(%rdx), %ecx
	leal	-129(%rcx), %edx
	cmpl	$2, %edx
	jae	LBB0_7
## %bb.12:
	movq	_IBV_WC_WITH_IMM@GOTPCREL(%rip), %rcx
	jmp	LBB0_9
LBB0_7:
	cmpl	$128, %ecx
	jne	LBB0_10
## %bb.8:
	movq	_IBV_WC_WITH_INV@GOTPCREL(%rip), %rcx
LBB0_9:
	orl	(%rcx), %r15d
LBB0_10:
	movl	8(%rax), %edi
	callq	_be32toh
	movq	_IBV_WC_GRH@GOTPCREL(%rip), %rcx
	sarl	$31, %eax
	andl	(%rcx), %eax
	orl	%r15d, %eax
LBB0_11:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MLX4_CQE_IS_SEND_MASK,4,2      ## @MLX4_CQE_IS_SEND_MASK
	.comm	_MLX4_CQE_OPCODE_MASK,4,2       ## @MLX4_CQE_OPCODE_MASK
	.comm	_IBV_WC_WITH_IMM,4,2            ## @IBV_WC_WITH_IMM
	.comm	_MLX4_CQ_FLAGS_RX_CSUM_VALID,4,2 ## @MLX4_CQ_FLAGS_RX_CSUM_VALID
	.comm	_MLX4_CQE_STATUS_IPV4_CSUM_OK,4,2 ## @MLX4_CQE_STATUS_IPV4_CSUM_OK
	.comm	_IBV_WC_IP_CSUM_OK_SHIFT,4,2    ## @IBV_WC_IP_CSUM_OK_SHIFT
	.comm	_IBV_WC_WITH_INV,4,2            ## @IBV_WC_WITH_INV
	.comm	_IBV_WC_GRH,4,2                 ## @IBV_WC_GRH
	.no_dead_strip	_mlx4_cq_read_wc_flags
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mlx4_cq_read_wc_flags
_mlx4_cq_read_wc_flags:                 ; @mlx4_cq_read_wc_flags
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	bl	_ibv_cq_ex_to_cq
	bl	_to_mcq
	ldr	x8, [x0, #8]
	ldr	w9, [x8]
Lloh0:
	adrp	x10, _MLX4_CQE_IS_SEND_MASK@GOTPAGE
Lloh1:
	ldr	x10, [x10, _MLX4_CQE_IS_SEND_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w10, [x10]
	tst	w10, w9
	b.eq	LBB0_2
; %bb.1:
Lloh3:
	adrp	x8, _MLX4_CQE_OPCODE_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _MLX4_CQE_OPCODE_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	and	w8, w8, w9
	sub	w8, w8, #131
Lloh6:
	adrp	x9, _IBV_WC_WITH_IMM@GOTPAGE
Lloh7:
	ldr	x9, [x9, _IBV_WC_WITH_IMM@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	cmp	w8, #2
	csel	w0, w9, wzr, lo
	b	LBB0_11
LBB0_2:
	mov	x19, x0
	ldr	w10, [x0]
Lloh9:
	adrp	x11, _MLX4_CQ_FLAGS_RX_CSUM_VALID@GOTPAGE
Lloh10:
	ldr	x11, [x11, _MLX4_CQ_FLAGS_RX_CSUM_VALID@GOTPAGEOFF]
Lloh11:
	ldr	w11, [x11]
	tst	w11, w10
	b.eq	LBB0_4
; %bb.3:
	ldr	w20, [x8, #4]
Lloh12:
	adrp	x21, _MLX4_CQE_STATUS_IPV4_CSUM_OK@GOTPAGE
Lloh13:
	ldr	x21, [x21, _MLX4_CQE_STATUS_IPV4_CSUM_OK@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_htobe32
	and	w20, w0, w20
	ldr	w0, [x21]
	bl	_htobe32
	cmp	w20, w0
	cset	w8, eq
Lloh14:
	adrp	x9, _IBV_WC_IP_CSUM_OK_SHIFT@GOTPAGE
Lloh15:
	ldr	x9, [x9, _IBV_WC_IP_CSUM_OK_SHIFT@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
	lsl	w20, w8, w9
	ldr	x8, [x19, #8]
	ldr	w9, [x8]
	b	LBB0_5
LBB0_4:
	mov	w20, #0
LBB0_5:
Lloh17:
	adrp	x10, _MLX4_CQE_OPCODE_MASK@GOTPAGE
Lloh18:
	ldr	x10, [x10, _MLX4_CQE_OPCODE_MASK@GOTPAGEOFF]
Lloh19:
	ldr	w10, [x10]
	and	w9, w10, w9
	sub	w10, w9, #129
	cmp	w10, #2
	b.hs	LBB0_7
; %bb.6:
Lloh20:
	adrp	x9, _IBV_WC_WITH_IMM@GOTPAGE
Lloh21:
	ldr	x9, [x9, _IBV_WC_WITH_IMM@GOTPAGEOFF]
	b	LBB0_9
LBB0_7:
	cmp	w9, #128
	b.ne	LBB0_10
; %bb.8:
Lloh22:
	adrp	x9, _IBV_WC_WITH_INV@GOTPAGE
Lloh23:
	ldr	x9, [x9, _IBV_WC_WITH_INV@GOTPAGEOFF]
LBB0_9:
	ldr	w9, [x9]
	orr	w20, w9, w20
LBB0_10:
	ldr	w0, [x8, #8]
	bl	_be32toh
Lloh24:
	adrp	x8, _IBV_WC_GRH@GOTPAGE
Lloh25:
	ldr	x8, [x8, _IBV_WC_GRH@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	and	w8, w8, w0, asr #31
	orr	w0, w8, w20
LBB0_11:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.cfi_endproc
                                        ; -- End function
	.comm	_MLX4_CQE_IS_SEND_MASK,4,2      ; @MLX4_CQE_IS_SEND_MASK
	.comm	_MLX4_CQE_OPCODE_MASK,4,2       ; @MLX4_CQE_OPCODE_MASK
	.comm	_IBV_WC_WITH_IMM,4,2            ; @IBV_WC_WITH_IMM
	.comm	_MLX4_CQ_FLAGS_RX_CSUM_VALID,4,2 ; @MLX4_CQ_FLAGS_RX_CSUM_VALID
	.comm	_MLX4_CQE_STATUS_IPV4_CSUM_OK,4,2 ; @MLX4_CQE_STATUS_IPV4_CSUM_OK
	.comm	_IBV_WC_IP_CSUM_OK_SHIFT,4,2    ; @IBV_WC_IP_CSUM_OK_SHIFT
	.comm	_IBV_WC_WITH_INV,4,2            ; @IBV_WC_WITH_INV
	.comm	_IBV_WC_GRH,4,2                 ; @IBV_WC_GRH
	.no_dead_strip	_mlx4_cq_read_wc_flags
.subsections_via_symbols
