	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_identify_arm_cpu               ## -- Begin function identify_arm_cpu
	.p2align	4, 0x90
_identify_arm_cpu:                      ## @identify_arm_cpu
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	xorl	%eax, %eax
	callq	_cp15_sctlr_get
	movq	%rax, %r12
	xorl	%eax, %eax
	callq	_cp15_midr_get
	testq	%rax, %rax
	je	LBB0_3
## %bb.1:
	movq	%rax, %r14
	movq	_cpuids@GOTPCREL(%rip), %r15
	movq	(%r15), %rax
	movq	(%rax), %rsi
	testq	%rsi, %rsi
	je	LBB0_2
## %bb.4:
	movq	_CPU_ID_CPU_MASK@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rdx
	andq	%r14, %rdx
	leaq	32(%rax), %rdi
	xorl	%ecx, %ecx
	.p2align	4, 0x90
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	cmpq	%rdx, %rsi
	je	LBB0_6
## %bb.7:                               ##   in Loop: Header=BB0_5 Depth=1
	incq	%rcx
	movq	(%rdi), %rsi
	addq	$32, %rdi
	testq	%rsi, %rsi
	jne	LBB0_5
## %bb.8:
	movl	%ecx, %ebx
	jmp	LBB0_9
LBB0_3:
	leaq	L_str(%rip), %rdi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_puts                           ## TAILCALL
LBB0_2:
	xorl	%ebx, %ebx
	jmp	LBB0_9
LBB0_6:
	movl	%ecx, %ebx
	movq	%rbx, %rcx
	shlq	$5, %rcx
	movq	8(%rax,%rcx), %rdi
	movq	_cpu_class@GOTPCREL(%rip), %rdx
	movq	%rdi, (%rdx)
	movq	16(%rax,%rcx), %rsi
	movq	24(%rax,%rcx), %rax
	movq	_CPU_ID_REVISION_MASK@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	andq	%r14, %rcx
	movq	(%rax,%rcx,8), %rdx
	movq	_cpu_classes@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	(%rax,%rdi,8), %rcx
	leaq	L_.str.1(%rip), %rdi
	xorl	%eax, %eax
	callq	_printf
	movq	(%r15), %rax
LBB0_9:
	shlq	$5, %rbx
	cmpq	$0, (%rax,%rbx)
	jne	LBB0_11
## %bb.10:
	leaq	L_.str.2(%rip), %rdi
	movq	%r14, %rsi
	xorl	%eax, %eax
	callq	_printf
LBB0_11:
	movl	$32, %edi
	callq	_putchar
	movq	_CPU_CONTROL_BEND_ENABLE@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	andq	%r12, %rax
	leaq	L_.str.5(%rip), %rax
	leaq	L_.str.4(%rip), %rdi
	cmoveq	%rax, %rdi
	xorl	%eax, %eax
	callq	_printf
	movq	_cpu_class@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	addq	$-128, %rax
	cmpq	$6, %rax
	ja	LBB0_13
## %bb.12:
	movq	_CPU_CONTROL_DC_ENABLE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	andq	%r12, %rdi
	leaq	L_.str.6(%rip), %rsi
	callq	_print_enadis
	movq	_CPU_CONTROL_IC_ENABLE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	andq	%r12, %rdi
	leaq	L_.str.7(%rip), %rsi
	callq	_print_enadis
LBB0_13:
	movq	_CPU_CONTROL_WBUF_ENABLE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	andq	%r12, %rdi
	leaq	L_.str.8(%rip), %rsi
	callq	_print_enadis
	movq	_CPU_CONTROL_LABT_ENABLE@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	andq	%r12, %rax
	leaq	L_.str.10(%rip), %rax
	leaq	L_.str.9(%rip), %rdi
	cmoveq	%rax, %rdi
	xorl	%eax, %eax
	callq	_printf
	movq	_CPU_CONTROL_BPRD_ENABLE@GOTPCREL(%rip), %rax
	andq	(%rax), %r12
	leaq	L_.str.11(%rip), %rsi
	movq	%r12, %rdi
	callq	_print_enadis
	movl	$10, %edi
	callq	_putchar
	movq	_arm_picache_line_size@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_arm_pdcache_line_size@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdx
	movq	%rax, %rcx
	orq	%rdx, %rcx
	jne	LBB0_14
## %bb.18:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_14:
	movq	_arm_pcache_unified@GOTPCREL(%rip), %rcx
	cmpq	$0, (%rcx)
	je	LBB0_17
## %bb.15:
	movq	_arm_pdcache_size@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	leal	1023(%rax), %esi
	testl	%eax, %eax
	cmovnsl	%eax, %esi
	sarl	$10, %esi
	movq	_arm_pdcache_ways@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	_wtnames@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_arm_pcache_type@GOTPCREL(%rip), %rdi
	movq	(%rdi), %rdi
	movq	(%rax,%rdi,8), %r8
	leaq	L_.str.13(%rip), %rdi
	jmp	LBB0_16
LBB0_17:
	movq	_arm_picache_size@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	leal	1023(%rcx), %esi
	testl	%ecx, %ecx
	cmovnsl	%ecx, %esi
	sarl	$10, %esi
	movq	_arm_picache_ways@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	leaq	L_.str.14(%rip), %rdi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	_printf
	movq	_arm_pdcache_size@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	leal	1023(%rax), %esi
	testl	%eax, %eax
	cmovnsl	%eax, %esi
	sarl	$10, %esi
	movq	(%rbx), %rdx
	movq	_arm_pdcache_ways@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	_wtnames@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_arm_pcache_type@GOTPCREL(%rip), %rdi
	movq	(%rdi), %rdi
	movq	(%rax,%rdi,8), %r8
	leaq	L_.str.15(%rip), %rdi
LBB0_16:
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_printf                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_cpuids,8,3                     ## @cpuids
	.comm	_CPU_ID_CPU_MASK,8,3            ## @CPU_ID_CPU_MASK
	.comm	_cpu_class,8,3                  ## @cpu_class
	.section	__TEXT,__cstring,cstring_literals
L_.str.1:                               ## @.str.1
	.asciz	"CPU: %s %s (%s core)\n"

	.comm	_CPU_ID_REVISION_MASK,8,3       ## @CPU_ID_REVISION_MASK
	.comm	_cpu_classes,8,3                ## @cpu_classes
L_.str.2:                               ## @.str.2
	.asciz	"unknown CPU (ID = 0x%x)\n"

	.comm	_CPU_CONTROL_BEND_ENABLE,8,3    ## @CPU_CONTROL_BEND_ENABLE
L_.str.4:                               ## @.str.4
	.asciz	" Big-endian"

L_.str.5:                               ## @.str.5
	.asciz	" Little-endian"

	.comm	_CPU_CONTROL_DC_ENABLE,8,3      ## @CPU_CONTROL_DC_ENABLE
L_.str.6:                               ## @.str.6
	.asciz	"DC"

	.comm	_CPU_CONTROL_IC_ENABLE,8,3      ## @CPU_CONTROL_IC_ENABLE
L_.str.7:                               ## @.str.7
	.asciz	"IC"

	.comm	_CPU_CONTROL_WBUF_ENABLE,8,3    ## @CPU_CONTROL_WBUF_ENABLE
L_.str.8:                               ## @.str.8
	.asciz	"WB"

	.comm	_CPU_CONTROL_LABT_ENABLE,8,3    ## @CPU_CONTROL_LABT_ENABLE
L_.str.9:                               ## @.str.9
	.asciz	" LABT"

L_.str.10:                              ## @.str.10
	.asciz	" EABT"

	.comm	_CPU_CONTROL_BPRD_ENABLE,8,3    ## @CPU_CONTROL_BPRD_ENABLE
L_.str.11:                              ## @.str.11
	.asciz	"branch prediction"

	.comm	_arm_picache_line_size,8,3      ## @arm_picache_line_size
	.comm	_arm_pdcache_line_size,8,3      ## @arm_pdcache_line_size
	.comm	_arm_pcache_unified,8,3         ## @arm_pcache_unified
L_.str.13:                              ## @.str.13
	.asciz	"  %dKB/%dB %d-way %s unified cache\n"

	.comm	_arm_pdcache_size,4,2           ## @arm_pdcache_size
	.comm	_arm_pdcache_ways,4,2           ## @arm_pdcache_ways
	.comm	_wtnames,8,3                    ## @wtnames
	.comm	_arm_pcache_type,8,3            ## @arm_pcache_type
L_.str.14:                              ## @.str.14
	.asciz	"  %dKB/%dB %d-way instruction cache\n"

	.comm	_arm_picache_size,4,2           ## @arm_picache_size
	.comm	_arm_picache_ways,4,2           ## @arm_picache_ways
L_.str.15:                              ## @.str.15
	.asciz	"  %dKB/%dB %d-way %s data cache\n"

	.comm	_MV_BTB_DISABLE,4,2             ## @MV_BTB_DISABLE
	.comm	_MV_DC_STREAM_ENABLE,4,2        ## @MV_DC_STREAM_ENABLE
	.comm	_MV_L2_ENABLE,4,2               ## @MV_L2_ENABLE
	.comm	_MV_L2_PREFETCH_DISABLE,4,2     ## @MV_L2_PREFETCH_DISABLE
	.comm	_MV_WA_ENABLE,4,2               ## @MV_WA_ENABLE
L_str:                                  ## @str
	.asciz	"Processor failed probe - no CPU ID"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_identify_arm_cpu               ; -- Begin function identify_arm_cpu
	.p2align	2
_identify_arm_cpu:                      ; @identify_arm_cpu
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	bl	_cp15_sctlr_get
	mov	x19, x0
	bl	_cp15_midr_get
	cbz	x0, LBB0_6
; %bb.1:
	mov	x20, x0
Lloh0:
	adrp	x22, _cpuids@GOTPAGE
Lloh1:
	ldr	x22, [x22, _cpuids@GOTPAGEOFF]
	ldr	x8, [x22]
	ldr	x10, [x8]
Lloh2:
	adrp	x21, _cpu_class@GOTPAGE
Lloh3:
	ldr	x21, [x21, _cpu_class@GOTPAGEOFF]
	cbz	x10, LBB0_7
; %bb.2:
	mov	x9, #0
Lloh4:
	adrp	x11, _CPU_ID_CPU_MASK@GOTPAGE
Lloh5:
	ldr	x11, [x11, _CPU_ID_CPU_MASK@GOTPAGEOFF]
Lloh6:
	ldr	x11, [x11]
	and	x11, x11, x20
	mov	w12, #32
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	cmp	x10, x11
	b.eq	LBB0_8
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	add	x9, x9, #1
	ldr	x10, [x8, x12]
	add	x12, x12, #32
	cbnz	x10, LBB0_3
; %bb.5:
	and	x23, x9, #0xffffffff
	b	LBB0_9
LBB0_6:
Lloh7:
	adrp	x0, l_str@PAGE
Lloh8:
	add	x0, x0, l_str@PAGEOFF
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #96
	b	_puts
LBB0_7:
	mov	x23, #0
	b	LBB0_9
LBB0_8:
	and	x23, x9, #0xffffffff
	add	x8, x8, x23, lsl #5
	ldp	x9, x10, [x8, #8]
	ldr	x8, [x8, #24]
Lloh9:
	adrp	x11, _CPU_ID_REVISION_MASK@GOTPAGE
Lloh10:
	ldr	x11, [x11, _CPU_ID_REVISION_MASK@GOTPAGEOFF]
Lloh11:
	ldr	x11, [x11]
	and	x11, x11, x20
	ldr	x8, [x8, x11, lsl #3]
	str	x9, [x21]
Lloh12:
	adrp	x11, _cpu_classes@GOTPAGE
Lloh13:
	ldr	x11, [x11, _cpu_classes@GOTPAGEOFF]
Lloh14:
	ldr	x11, [x11]
	ldr	x9, [x11, x9, lsl #3]
	stp	x8, x9, [sp, #8]
	str	x10, [sp]
Lloh15:
	adrp	x0, l_.str.1@PAGE
Lloh16:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_printf
	ldr	x8, [x22]
LBB0_9:
	lsl	x9, x23, #5
	ldr	x8, [x8, x9]
	cbnz	x8, LBB0_11
; %bb.10:
	str	x20, [sp]
Lloh17:
	adrp	x0, l_.str.2@PAGE
Lloh18:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	_printf
LBB0_11:
	mov	w0, #32
	bl	_putchar
Lloh19:
	adrp	x8, _CPU_CONTROL_BEND_ENABLE@GOTPAGE
Lloh20:
	ldr	x8, [x8, _CPU_CONTROL_BEND_ENABLE@GOTPAGEOFF]
Lloh21:
	ldr	x8, [x8]
Lloh22:
	adrp	x9, l_.str.4@PAGE
Lloh23:
	add	x9, x9, l_.str.4@PAGEOFF
Lloh24:
	adrp	x10, l_.str.5@PAGE
Lloh25:
	add	x10, x10, l_.str.5@PAGEOFF
	tst	x8, x19
	csel	x0, x10, x9, eq
	bl	_printf
	ldr	x8, [x21]
	sub	x8, x8, #128
	cmp	x8, #6
	b.hi	LBB0_13
; %bb.12:
Lloh26:
	adrp	x8, _CPU_CONTROL_DC_ENABLE@GOTPAGE
Lloh27:
	ldr	x8, [x8, _CPU_CONTROL_DC_ENABLE@GOTPAGEOFF]
Lloh28:
	ldr	x8, [x8]
	and	x0, x8, x19
Lloh29:
	adrp	x1, l_.str.6@PAGE
Lloh30:
	add	x1, x1, l_.str.6@PAGEOFF
	bl	_print_enadis
Lloh31:
	adrp	x8, _CPU_CONTROL_IC_ENABLE@GOTPAGE
Lloh32:
	ldr	x8, [x8, _CPU_CONTROL_IC_ENABLE@GOTPAGEOFF]
Lloh33:
	ldr	x8, [x8]
	and	x0, x8, x19
Lloh34:
	adrp	x1, l_.str.7@PAGE
Lloh35:
	add	x1, x1, l_.str.7@PAGEOFF
	bl	_print_enadis
LBB0_13:
Lloh36:
	adrp	x8, _CPU_CONTROL_WBUF_ENABLE@GOTPAGE
Lloh37:
	ldr	x8, [x8, _CPU_CONTROL_WBUF_ENABLE@GOTPAGEOFF]
Lloh38:
	ldr	x8, [x8]
	and	x0, x8, x19
Lloh39:
	adrp	x1, l_.str.8@PAGE
Lloh40:
	add	x1, x1, l_.str.8@PAGEOFF
	bl	_print_enadis
Lloh41:
	adrp	x8, _CPU_CONTROL_LABT_ENABLE@GOTPAGE
Lloh42:
	ldr	x8, [x8, _CPU_CONTROL_LABT_ENABLE@GOTPAGEOFF]
Lloh43:
	ldr	x8, [x8]
Lloh44:
	adrp	x9, l_.str.9@PAGE
Lloh45:
	add	x9, x9, l_.str.9@PAGEOFF
Lloh46:
	adrp	x10, l_.str.10@PAGE
Lloh47:
	add	x10, x10, l_.str.10@PAGEOFF
	tst	x8, x19
	csel	x0, x10, x9, eq
	bl	_printf
Lloh48:
	adrp	x8, _CPU_CONTROL_BPRD_ENABLE@GOTPAGE
Lloh49:
	ldr	x8, [x8, _CPU_CONTROL_BPRD_ENABLE@GOTPAGEOFF]
Lloh50:
	ldr	x8, [x8]
	and	x0, x8, x19
Lloh51:
	adrp	x1, l_.str.11@PAGE
Lloh52:
	add	x1, x1, l_.str.11@PAGEOFF
	bl	_print_enadis
	mov	w0, #10
	bl	_putchar
Lloh53:
	adrp	x8, _arm_picache_line_size@GOTPAGE
Lloh54:
	ldr	x8, [x8, _arm_picache_line_size@GOTPAGEOFF]
Lloh55:
	ldr	x9, [x8]
Lloh56:
	adrp	x19, _arm_pdcache_line_size@GOTPAGE
Lloh57:
	ldr	x19, [x19, _arm_pdcache_line_size@GOTPAGEOFF]
	ldr	x8, [x19]
	orr	x10, x9, x8
	cbz	x10, LBB0_18
; %bb.14:
Lloh58:
	adrp	x10, _arm_pcache_unified@GOTPAGE
Lloh59:
	ldr	x10, [x10, _arm_pcache_unified@GOTPAGEOFF]
Lloh60:
	ldr	x10, [x10]
	cbz	x10, LBB0_16
; %bb.15:
Lloh61:
	adrp	x9, _arm_pdcache_size@GOTPAGE
Lloh62:
	ldr	x9, [x9, _arm_pdcache_size@GOTPAGEOFF]
Lloh63:
	ldr	w9, [x9]
	add	w10, w9, #1023
	cmp	w9, #0
	csel	w9, w10, w9, lt
	asr	w9, w9, #10
Lloh64:
	adrp	x10, _arm_pdcache_ways@GOTPAGE
Lloh65:
	ldr	x10, [x10, _arm_pdcache_ways@GOTPAGEOFF]
Lloh66:
	adrp	x11, _wtnames@GOTPAGE
Lloh67:
	ldr	x11, [x11, _wtnames@GOTPAGEOFF]
Lloh68:
	ldr	x11, [x11]
Lloh69:
	adrp	x12, _arm_pcache_type@GOTPAGE
Lloh70:
	ldr	x12, [x12, _arm_pcache_type@GOTPAGEOFF]
Lloh71:
	ldr	x12, [x12]
	ldr	x11, [x11, x12, lsl #3]
Lloh72:
	ldr	w10, [x10]
	stp	x10, x11, [sp, #16]
	stp	x9, x8, [sp]
Lloh73:
	adrp	x0, l_.str.13@PAGE
Lloh74:
	add	x0, x0, l_.str.13@PAGEOFF
	b	LBB0_17
LBB0_16:
Lloh75:
	adrp	x8, _arm_picache_size@GOTPAGE
Lloh76:
	ldr	x8, [x8, _arm_picache_size@GOTPAGEOFF]
Lloh77:
	ldr	w8, [x8]
	add	w10, w8, #1023
	cmp	w8, #0
	csel	w8, w10, w8, lt
	asr	w8, w8, #10
Lloh78:
	adrp	x10, _arm_picache_ways@GOTPAGE
Lloh79:
	ldr	x10, [x10, _arm_picache_ways@GOTPAGEOFF]
Lloh80:
	ldr	w10, [x10]
	stp	x9, x10, [sp, #8]
	str	x8, [sp]
Lloh81:
	adrp	x0, l_.str.14@PAGE
Lloh82:
	add	x0, x0, l_.str.14@PAGEOFF
	bl	_printf
Lloh83:
	adrp	x8, _arm_pdcache_size@GOTPAGE
Lloh84:
	ldr	x8, [x8, _arm_pdcache_size@GOTPAGEOFF]
Lloh85:
	ldr	w8, [x8]
	add	w9, w8, #1023
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w8, w8, #10
	ldr	x9, [x19]
Lloh86:
	adrp	x10, _arm_pdcache_ways@GOTPAGE
Lloh87:
	ldr	x10, [x10, _arm_pdcache_ways@GOTPAGEOFF]
Lloh88:
	adrp	x11, _wtnames@GOTPAGE
Lloh89:
	ldr	x11, [x11, _wtnames@GOTPAGEOFF]
Lloh90:
	ldr	x11, [x11]
Lloh91:
	adrp	x12, _arm_pcache_type@GOTPAGE
Lloh92:
	ldr	x12, [x12, _arm_pcache_type@GOTPAGEOFF]
Lloh93:
	ldr	x12, [x12]
	ldr	x11, [x11, x12, lsl #3]
Lloh94:
	ldr	w10, [x10]
	stp	x10, x11, [sp, #16]
	stp	x8, x9, [sp]
Lloh95:
	adrp	x0, l_.str.15@PAGE
Lloh96:
	add	x0, x0, l_.str.15@PAGEOFF
LBB0_17:
	bl	_printf
LBB0_18:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpAdd	Lloh7, Lloh8
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpAdd	Lloh17, Lloh18
	.loh AdrpAdd	Lloh24, Lloh25
	.loh AdrpAdd	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpAdd	Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpAdd	Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpAdd	Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpAdd	Lloh46, Lloh47
	.loh AdrpAdd	Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpAdd	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpAdd	Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh72
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpAdd	Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh94
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpAdd	Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.cfi_endproc
                                        ; -- End function
	.comm	_cpuids,8,3                     ; @cpuids
	.comm	_CPU_ID_CPU_MASK,8,3            ; @CPU_ID_CPU_MASK
	.comm	_cpu_class,8,3                  ; @cpu_class
	.section	__TEXT,__cstring,cstring_literals
l_.str.1:                               ; @.str.1
	.asciz	"CPU: %s %s (%s core)\n"

	.comm	_CPU_ID_REVISION_MASK,8,3       ; @CPU_ID_REVISION_MASK
	.comm	_cpu_classes,8,3                ; @cpu_classes
l_.str.2:                               ; @.str.2
	.asciz	"unknown CPU (ID = 0x%x)\n"

	.comm	_CPU_CONTROL_BEND_ENABLE,8,3    ; @CPU_CONTROL_BEND_ENABLE
l_.str.4:                               ; @.str.4
	.asciz	" Big-endian"

l_.str.5:                               ; @.str.5
	.asciz	" Little-endian"

	.comm	_CPU_CONTROL_DC_ENABLE,8,3      ; @CPU_CONTROL_DC_ENABLE
l_.str.6:                               ; @.str.6
	.asciz	"DC"

	.comm	_CPU_CONTROL_IC_ENABLE,8,3      ; @CPU_CONTROL_IC_ENABLE
l_.str.7:                               ; @.str.7
	.asciz	"IC"

	.comm	_CPU_CONTROL_WBUF_ENABLE,8,3    ; @CPU_CONTROL_WBUF_ENABLE
l_.str.8:                               ; @.str.8
	.asciz	"WB"

	.comm	_CPU_CONTROL_LABT_ENABLE,8,3    ; @CPU_CONTROL_LABT_ENABLE
l_.str.9:                               ; @.str.9
	.asciz	" LABT"

l_.str.10:                              ; @.str.10
	.asciz	" EABT"

	.comm	_CPU_CONTROL_BPRD_ENABLE,8,3    ; @CPU_CONTROL_BPRD_ENABLE
l_.str.11:                              ; @.str.11
	.asciz	"branch prediction"

	.comm	_arm_picache_line_size,8,3      ; @arm_picache_line_size
	.comm	_arm_pdcache_line_size,8,3      ; @arm_pdcache_line_size
	.comm	_arm_pcache_unified,8,3         ; @arm_pcache_unified
l_.str.13:                              ; @.str.13
	.asciz	"  %dKB/%dB %d-way %s unified cache\n"

	.comm	_arm_pdcache_size,4,2           ; @arm_pdcache_size
	.comm	_arm_pdcache_ways,4,2           ; @arm_pdcache_ways
	.comm	_wtnames,8,3                    ; @wtnames
	.comm	_arm_pcache_type,8,3            ; @arm_pcache_type
l_.str.14:                              ; @.str.14
	.asciz	"  %dKB/%dB %d-way instruction cache\n"

	.comm	_arm_picache_size,4,2           ; @arm_picache_size
	.comm	_arm_picache_ways,4,2           ; @arm_picache_ways
l_.str.15:                              ; @.str.15
	.asciz	"  %dKB/%dB %d-way %s data cache\n"

	.comm	_MV_BTB_DISABLE,4,2             ; @MV_BTB_DISABLE
	.comm	_MV_DC_STREAM_ENABLE,4,2        ; @MV_DC_STREAM_ENABLE
	.comm	_MV_L2_ENABLE,4,2               ; @MV_L2_ENABLE
	.comm	_MV_L2_PREFETCH_DISABLE,4,2     ; @MV_L2_PREFETCH_DISABLE
	.comm	_MV_WA_ENABLE,4,2               ; @MV_WA_ENABLE
l_str:                                  ; @str
	.asciz	"Processor failed probe - no CPU ID"

.subsections_via_symbols
