	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function spi_hw_setup
_spi_hw_setup:                          ## @spi_hw_setup
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r14d
	movl	%esi, %r15d
	movq	%rdi, %rbx
	movq	_CTLREG_EN@GOTPCREL(%rip), %rax
	movq	_CTLREG_CMODES_MASTER@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rax), %edx
	movq	_CTLREG_SMC@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	%edx, (%rdi)
	movl	%ecx, %esi
	callq	_spi_calc_clockdiv
	orl	(%rbx), %eax
	movl	%eax, (%rbx)
	movq	_CTLREG_BLEN_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$7, %edx
	shll	%cl, %edx
	orl	%eax, %edx
	movl	%edx, (%rbx)
	movq	_ECSPI_CTLREG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_WR4
	movq	_SPIBUS_CS_HIGH@GOTPCREL(%rip), %rax
	andl	(%rax), %r15d
	movq	_CFGREG_SSPOL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$1, %eax
	shll	%cl, %eax
	testl	%r15d, %r15d
	cmovel	%r15d, %eax
	movl	$1, %edx
	movq	_SPIBUS_MODE_CPHA@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_CFGREG_SCLKPHA_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	andl	%r14d, %esi
	testl	%esi, %esi
	cmovel	%esi, %edx
	orl	%eax, %edx
	movq	_SPIBUS_MODE_CPOL@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_2
## %bb.1:
	movq	_CFGREG_SCLKPOL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	btsl	%eax, %edx
	movq	_CFGREG_SCLKCTL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	btsl	%eax, %edx
LBB0_2:
	movq	_ECSPI_CFGREG@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_WR4
	movq	_FIFO_RXTHRESH@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_DMA_RX_THRESH_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	movq	_FIFO_TXTHRESH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_DMA_TX_THRESH_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	orl	%eax, %edx
	movq	_ECSPI_DMAREG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_WR4
	movl	(%r14), %esi
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_RD4                            ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_CTLREG_EN,4,2                  ## @CTLREG_EN
	.comm	_CTLREG_CMODES_MASTER,4,2       ## @CTLREG_CMODES_MASTER
	.comm	_CTLREG_SMC,4,2                 ## @CTLREG_SMC
	.comm	_CTLREG_BLEN_SHIFT,4,2          ## @CTLREG_BLEN_SHIFT
	.comm	_ECSPI_CTLREG,4,2               ## @ECSPI_CTLREG
	.comm	_SPIBUS_CS_HIGH,4,2             ## @SPIBUS_CS_HIGH
	.comm	_CFGREG_SSPOL_SHIFT,4,2         ## @CFGREG_SSPOL_SHIFT
	.comm	_SPIBUS_MODE_CPHA,4,2           ## @SPIBUS_MODE_CPHA
	.comm	_CFGREG_SCLKPHA_SHIFT,4,2       ## @CFGREG_SCLKPHA_SHIFT
	.comm	_SPIBUS_MODE_CPOL,4,2           ## @SPIBUS_MODE_CPOL
	.comm	_CFGREG_SCLKPOL_SHIFT,4,2       ## @CFGREG_SCLKPOL_SHIFT
	.comm	_CFGREG_SCLKCTL_SHIFT,4,2       ## @CFGREG_SCLKCTL_SHIFT
	.comm	_ECSPI_CFGREG,4,2               ## @ECSPI_CFGREG
	.comm	_FIFO_RXTHRESH,4,2              ## @FIFO_RXTHRESH
	.comm	_DMA_RX_THRESH_SHIFT,4,2        ## @DMA_RX_THRESH_SHIFT
	.comm	_FIFO_TXTHRESH,4,2              ## @FIFO_TXTHRESH
	.comm	_DMA_TX_THRESH_SHIFT,4,2        ## @DMA_TX_THRESH_SHIFT
	.comm	_ECSPI_DMAREG,4,2               ## @ECSPI_DMAREG
	.no_dead_strip	_spi_hw_setup
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function spi_hw_setup
_spi_hw_setup:                          ; @spi_hw_setup
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x2
	mov	x21, x1
	mov	x19, x0
Lloh0:
	adrp	x8, _CTLREG_EN@GOTPAGE
Lloh1:
	ldr	x8, [x8, _CTLREG_EN@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _CTLREG_CMODES_MASTER@GOTPAGE
Lloh4:
	ldr	x9, [x9, _CTLREG_CMODES_MASTER@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh6:
	adrp	x9, _CTLREG_SMC@GOTPAGE
Lloh7:
	ldr	x9, [x9, _CTLREG_SMC@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x0]
	mov	x1, x3
	bl	_spi_calc_clockdiv
	ldr	w8, [x19]
	orr	w8, w8, w0
	str	w8, [x19]
Lloh9:
	adrp	x9, _CTLREG_BLEN_SHIFT@GOTPAGE
Lloh10:
	ldr	x9, [x9, _CTLREG_BLEN_SHIFT@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	mov	w10, #7
	lsl	w9, w10, w9
	orr	w2, w9, w8
	str	w2, [x19]
Lloh12:
	adrp	x8, _ECSPI_CTLREG@GOTPAGE
Lloh13:
	ldr	x8, [x8, _ECSPI_CTLREG@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_WR4
Lloh15:
	adrp	x8, _SPIBUS_CS_HIGH@GOTPAGE
Lloh16:
	ldr	x8, [x8, _SPIBUS_CS_HIGH@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x8]
Lloh18:
	adrp	x8, _CFGREG_SSPOL_SHIFT@GOTPAGE
Lloh19:
	ldr	x8, [x8, _CFGREG_SSPOL_SHIFT@GOTPAGEOFF]
Lloh20:
	ldr	w10, [x8]
	mov	w8, #1
	lsl	w10, w8, w10
	tst	w9, w21
	csel	w9, wzr, w10, eq
Lloh21:
	adrp	x10, _SPIBUS_MODE_CPHA@GOTPAGE
Lloh22:
	ldr	x10, [x10, _SPIBUS_MODE_CPHA@GOTPAGEOFF]
Lloh23:
	ldr	w10, [x10]
Lloh24:
	adrp	x11, _CFGREG_SCLKPHA_SHIFT@GOTPAGE
Lloh25:
	ldr	x11, [x11, _CFGREG_SCLKPHA_SHIFT@GOTPAGEOFF]
Lloh26:
	ldr	w11, [x11]
	lsl	w11, w8, w11
	tst	w10, w20
	csel	w10, wzr, w11, eq
	orr	w2, w10, w9
Lloh27:
	adrp	x9, _SPIBUS_MODE_CPOL@GOTPAGE
Lloh28:
	ldr	x9, [x9, _SPIBUS_MODE_CPOL@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	tst	w9, w20
	b.eq	LBB0_2
; %bb.1:
Lloh30:
	adrp	x9, _CFGREG_SCLKPOL_SHIFT@GOTPAGE
Lloh31:
	ldr	x9, [x9, _CFGREG_SCLKPOL_SHIFT@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	lsl	w9, w8, w9
	orr	w9, w9, w2
Lloh33:
	adrp	x10, _CFGREG_SCLKCTL_SHIFT@GOTPAGE
Lloh34:
	ldr	x10, [x10, _CFGREG_SCLKCTL_SHIFT@GOTPAGEOFF]
Lloh35:
	ldr	w10, [x10]
	lsl	w8, w8, w10
	orr	w2, w9, w8
LBB0_2:
Lloh36:
	adrp	x20, _ECSPI_CFGREG@GOTPAGE
Lloh37:
	ldr	x20, [x20, _ECSPI_CFGREG@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_WR4
Lloh38:
	adrp	x8, _FIFO_RXTHRESH@GOTPAGE
Lloh39:
	ldr	x8, [x8, _FIFO_RXTHRESH@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
Lloh41:
	adrp	x9, _DMA_RX_THRESH_SHIFT@GOTPAGE
Lloh42:
	ldr	x9, [x9, _DMA_RX_THRESH_SHIFT@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
	lsl	w8, w8, w9
Lloh44:
	adrp	x9, _FIFO_TXTHRESH@GOTPAGE
Lloh45:
	ldr	x9, [x9, _FIFO_TXTHRESH@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
Lloh47:
	adrp	x10, _DMA_TX_THRESH_SHIFT@GOTPAGE
Lloh48:
	ldr	x10, [x10, _DMA_TX_THRESH_SHIFT@GOTPAGEOFF]
Lloh49:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w2, w9, w8
Lloh50:
	adrp	x8, _ECSPI_DMAREG@GOTPAGE
Lloh51:
	ldr	x8, [x8, _ECSPI_DMAREG@GOTPAGEOFF]
Lloh52:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_WR4
	ldr	w1, [x20]
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_RD4
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh36, Lloh37
	.cfi_endproc
                                        ; -- End function
	.comm	_CTLREG_EN,4,2                  ; @CTLREG_EN
	.comm	_CTLREG_CMODES_MASTER,4,2       ; @CTLREG_CMODES_MASTER
	.comm	_CTLREG_SMC,4,2                 ; @CTLREG_SMC
	.comm	_CTLREG_BLEN_SHIFT,4,2          ; @CTLREG_BLEN_SHIFT
	.comm	_ECSPI_CTLREG,4,2               ; @ECSPI_CTLREG
	.comm	_SPIBUS_CS_HIGH,4,2             ; @SPIBUS_CS_HIGH
	.comm	_CFGREG_SSPOL_SHIFT,4,2         ; @CFGREG_SSPOL_SHIFT
	.comm	_SPIBUS_MODE_CPHA,4,2           ; @SPIBUS_MODE_CPHA
	.comm	_CFGREG_SCLKPHA_SHIFT,4,2       ; @CFGREG_SCLKPHA_SHIFT
	.comm	_SPIBUS_MODE_CPOL,4,2           ; @SPIBUS_MODE_CPOL
	.comm	_CFGREG_SCLKPOL_SHIFT,4,2       ; @CFGREG_SCLKPOL_SHIFT
	.comm	_CFGREG_SCLKCTL_SHIFT,4,2       ; @CFGREG_SCLKCTL_SHIFT
	.comm	_ECSPI_CFGREG,4,2               ; @ECSPI_CFGREG
	.comm	_FIFO_RXTHRESH,4,2              ; @FIFO_RXTHRESH
	.comm	_DMA_RX_THRESH_SHIFT,4,2        ; @DMA_RX_THRESH_SHIFT
	.comm	_FIFO_TXTHRESH,4,2              ; @FIFO_TXTHRESH
	.comm	_DMA_TX_THRESH_SHIFT,4,2        ; @DMA_TX_THRESH_SHIFT
	.comm	_ECSPI_DMAREG,4,2               ; @ECSPI_DMAREG
	.no_dead_strip	_spi_hw_setup
.subsections_via_symbols
