	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function a10dmac_set_config
_a10dmac_set_config:                    ## @a10dmac_set_config
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r15
	movq	%rsi, %r14
	movl	(%rdx), %eax
	cmpl	$8, %eax
	je	LBB0_1
## %bb.2:
	cmpl	$32, %eax
	je	LBB0_5
## %bb.3:
	cmpl	$16, %eax
	jne	LBB0_23
## %bb.4:
	movq	_AWIN_DMA_CTL_DATA_WIDTH_16@GOTPCREL(%rip), %rax
	jmp	LBB0_6
LBB0_1:
	movq	_AWIN_DMA_CTL_DATA_WIDTH_8@GOTPCREL(%rip), %rax
	jmp	LBB0_6
LBB0_5:
	movq	_AWIN_DMA_CTL_DATA_WIDTH_32@GOTPCREL(%rip), %rax
LBB0_6:
	movl	(%rax), %edx
	movl	4(%r15), %eax
	cmpl	$1, %eax
	je	LBB0_7
## %bb.8:
	cmpl	$8, %eax
	je	LBB0_11
## %bb.9:
	cmpl	$4, %eax
	jne	LBB0_23
## %bb.10:
	movq	_AWIN_DMA_CTL_BURST_LEN_4@GOTPCREL(%rip), %rax
	jmp	LBB0_12
LBB0_7:
	movq	_AWIN_DMA_CTL_BURST_LEN_1@GOTPCREL(%rip), %rax
	jmp	LBB0_12
LBB0_11:
	movq	_AWIN_DMA_CTL_BURST_LEN_8@GOTPCREL(%rip), %rax
LBB0_12:
	movl	(%rax), %eax
	movl	8(%r15), %ecx
	cmpl	$8, %ecx
	je	LBB0_13
## %bb.14:
	cmpl	$32, %ecx
	je	LBB0_17
## %bb.15:
	cmpl	$16, %ecx
	jne	LBB0_23
## %bb.16:
	movq	_AWIN_DMA_CTL_DATA_WIDTH_16@GOTPCREL(%rip), %rcx
	jmp	LBB0_18
LBB0_13:
	movq	_AWIN_DMA_CTL_DATA_WIDTH_8@GOTPCREL(%rip), %rcx
	jmp	LBB0_18
LBB0_17:
	movq	_AWIN_DMA_CTL_DATA_WIDTH_32@GOTPCREL(%rip), %rcx
LBB0_18:
	movl	(%rcx), %esi
	movl	12(%r15), %ecx
	cmpl	$1, %ecx
	je	LBB0_19
## %bb.20:
	cmpl	$8, %ecx
	je	LBB0_24
## %bb.21:
	cmpl	$4, %ecx
	jne	LBB0_23
## %bb.22:
	movq	_AWIN_DMA_CTL_BURST_LEN_4@GOTPCREL(%rip), %rcx
	jmp	LBB0_25
LBB0_23:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
LBB0_32:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_19:
	movq	_AWIN_DMA_CTL_BURST_LEN_1@GOTPCREL(%rip), %rcx
	jmp	LBB0_25
LBB0_24:
	movq	_AWIN_DMA_CTL_BURST_LEN_8@GOTPCREL(%rip), %rcx
LBB0_25:
	movl	(%rcx), %ebx
	movq	_AWIN_DMA_CTL_DST_DATA_WIDTH_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	movq	_AWIN_DMA_CTL_DST_BURST_LEN_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	orl	%edx, %eax
	movq	_AWIN_DMA_CTL_DST_DRQ_TYPE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	16(%r15), %edx
	shll	%cl, %edx
	movq	_AWIN_DMA_CTL_SRC_DATA_WIDTH_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %esi
	movl	20(%r15), %edi
	orl	%edx, %esi
	movq	_AWIN_DMA_CTL_SRC_BURST_LEN_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %ebx
	movq	_AWIN_DMA_CTL_SRC_DRQ_TYPE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edi
	orl	%eax, %esi
	orl	%ebx, %edi
	orl	%esi, %edi
	movq	(%r14), %rcx
	movq	_CH_NDMA@GOTPCREL(%rip), %rdx
	movq	48(%r15), %rax
	cmpq	(%rdx), %rcx
	jne	LBB0_31
## %bb.26:
	xorl	%ebx, %ebx
	movl	$0, %edx
	testq	%rax, %rax
	je	LBB0_28
## %bb.27:
	movq	_AWIN_NDMA_CTL_DST_ADDR_NOINCR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
LBB0_28:
	orl	%edi, %edx
	cmpq	$0, 40(%r15)
	movl	$0, %eax
	je	LBB0_30
## %bb.29:
	movq	_AWIN_NDMA_CTL_SRC_ADDR_NOINCR@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_30:
	orl	%eax, %edx
	movq	_AWIN_NDMA_CTL_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_DMACH_WRITE
	jmp	LBB0_32
LBB0_31:
	testq	%rax, %rax
	movq	_AWIN_DDMA_CTL_DMA_ADDR_IO@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_AWIN_DDMA_CTL_DMA_ADDR_LINEAR@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%edx, %esi
	cmovel	%eax, %esi
	cmpq	$0, 40(%r15)
	cmovel	%eax, %edx
	movq	_AWIN_DDMA_CTL_DST_ADDR_MODE_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %esi
	movq	_AWIN_DDMA_CTL_SRC_ADDR_MODE_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %edx
	orl	%edi, %esi
	orl	%esi, %edx
	movq	_AWIN_DDMA_CTL_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_DMACH_WRITE
	movl	24(%r15), %edi
	movl	28(%r15), %eax
	decl	%edi
	decl	%eax
	movl	32(%r15), %ebx
	decl	%ebx
	movl	36(%r15), %edx
	movq	_AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edi
	movq	_AWIN_DDMA_PARA_DST_WAIT_CYC_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	decl	%edx
	movq	_AWIN_DDMA_PARA_REG@GOTPCREL(%rip), %rsi
	movq	_AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %ebx
	movq	_AWIN_DDMA_PARA_SRC_WAIT_CYC_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	movl	(%rsi), %esi
	orl	%edi, %eax
	orl	%ebx, %edx
	orl	%eax, %edx
	movq	%r14, %rdi
	callq	_DMACH_WRITE
	xorl	%ebx, %ebx
	jmp	LBB0_32
	.cfi_endproc
                                        ## -- End function
	.comm	_AWIN_DMA_CTL_DATA_WIDTH_8,4,2  ## @AWIN_DMA_CTL_DATA_WIDTH_8
	.comm	_AWIN_DMA_CTL_DATA_WIDTH_16,4,2 ## @AWIN_DMA_CTL_DATA_WIDTH_16
	.comm	_AWIN_DMA_CTL_DATA_WIDTH_32,4,2 ## @AWIN_DMA_CTL_DATA_WIDTH_32
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_AWIN_DMA_CTL_BURST_LEN_1,4,2   ## @AWIN_DMA_CTL_BURST_LEN_1
	.comm	_AWIN_DMA_CTL_BURST_LEN_4,4,2   ## @AWIN_DMA_CTL_BURST_LEN_4
	.comm	_AWIN_DMA_CTL_BURST_LEN_8,4,2   ## @AWIN_DMA_CTL_BURST_LEN_8
	.comm	_AWIN_DMA_CTL_DST_DATA_WIDTH_SHIFT,4,2 ## @AWIN_DMA_CTL_DST_DATA_WIDTH_SHIFT
	.comm	_AWIN_DMA_CTL_DST_BURST_LEN_SHIFT,4,2 ## @AWIN_DMA_CTL_DST_BURST_LEN_SHIFT
	.comm	_AWIN_DMA_CTL_DST_DRQ_TYPE_SHIFT,4,2 ## @AWIN_DMA_CTL_DST_DRQ_TYPE_SHIFT
	.comm	_AWIN_DMA_CTL_SRC_DATA_WIDTH_SHIFT,4,2 ## @AWIN_DMA_CTL_SRC_DATA_WIDTH_SHIFT
	.comm	_AWIN_DMA_CTL_SRC_BURST_LEN_SHIFT,4,2 ## @AWIN_DMA_CTL_SRC_BURST_LEN_SHIFT
	.comm	_AWIN_DMA_CTL_SRC_DRQ_TYPE_SHIFT,4,2 ## @AWIN_DMA_CTL_SRC_DRQ_TYPE_SHIFT
	.comm	_CH_NDMA,8,3                    ## @CH_NDMA
	.comm	_AWIN_NDMA_CTL_DST_ADDR_NOINCR,4,2 ## @AWIN_NDMA_CTL_DST_ADDR_NOINCR
	.comm	_AWIN_NDMA_CTL_SRC_ADDR_NOINCR,4,2 ## @AWIN_NDMA_CTL_SRC_ADDR_NOINCR
	.comm	_AWIN_NDMA_CTL_REG,4,2          ## @AWIN_NDMA_CTL_REG
	.comm	_AWIN_DDMA_CTL_DMA_ADDR_IO,4,2  ## @AWIN_DDMA_CTL_DMA_ADDR_IO
	.comm	_AWIN_DDMA_CTL_DMA_ADDR_LINEAR,4,2 ## @AWIN_DDMA_CTL_DMA_ADDR_LINEAR
	.comm	_AWIN_DDMA_CTL_DST_ADDR_MODE_SHIFT,4,2 ## @AWIN_DDMA_CTL_DST_ADDR_MODE_SHIFT
	.comm	_AWIN_DDMA_CTL_SRC_ADDR_MODE_SHIFT,4,2 ## @AWIN_DDMA_CTL_SRC_ADDR_MODE_SHIFT
	.comm	_AWIN_DDMA_CTL_REG,4,2          ## @AWIN_DDMA_CTL_REG
	.comm	_AWIN_DDMA_PARA_REG,4,2         ## @AWIN_DDMA_PARA_REG
	.comm	_AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_SHIFT,4,2 ## @AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_SHIFT
	.comm	_AWIN_DDMA_PARA_DST_WAIT_CYC_SHIFT,4,2 ## @AWIN_DDMA_PARA_DST_WAIT_CYC_SHIFT
	.comm	_AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_SHIFT,4,2 ## @AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_SHIFT
	.comm	_AWIN_DDMA_PARA_SRC_WAIT_CYC_SHIFT,4,2 ## @AWIN_DDMA_PARA_SRC_WAIT_CYC_SHIFT
	.no_dead_strip	_a10dmac_set_config
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function a10dmac_set_config
_a10dmac_set_config:                    ; @a10dmac_set_config
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x20, x2
	mov	x19, x1
	ldr	w8, [x2]
	cmp	w8, #8
	b.eq	LBB0_4
; %bb.1:
	cmp	w8, #32
	b.eq	LBB0_5
; %bb.2:
	cmp	w8, #16
	b.ne	LBB0_22
; %bb.3:
Lloh0:
	adrp	x8, _AWIN_DMA_CTL_DATA_WIDTH_16@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AWIN_DMA_CTL_DATA_WIDTH_16@GOTPAGEOFF]
	b	LBB0_6
LBB0_4:
Lloh2:
	adrp	x8, _AWIN_DMA_CTL_DATA_WIDTH_8@GOTPAGE
Lloh3:
	ldr	x8, [x8, _AWIN_DMA_CTL_DATA_WIDTH_8@GOTPAGEOFF]
	b	LBB0_6
LBB0_5:
Lloh4:
	adrp	x8, _AWIN_DMA_CTL_DATA_WIDTH_32@GOTPAGE
Lloh5:
	ldr	x8, [x8, _AWIN_DMA_CTL_DATA_WIDTH_32@GOTPAGEOFF]
LBB0_6:
	ldr	w8, [x8]
	ldr	w9, [x20, #4]
	cmp	w9, #1
	b.eq	LBB0_10
; %bb.7:
	cmp	w9, #8
	b.eq	LBB0_11
; %bb.8:
	cmp	w9, #4
	b.ne	LBB0_22
; %bb.9:
Lloh6:
	adrp	x9, _AWIN_DMA_CTL_BURST_LEN_4@GOTPAGE
Lloh7:
	ldr	x9, [x9, _AWIN_DMA_CTL_BURST_LEN_4@GOTPAGEOFF]
	b	LBB0_12
LBB0_10:
Lloh8:
	adrp	x9, _AWIN_DMA_CTL_BURST_LEN_1@GOTPAGE
Lloh9:
	ldr	x9, [x9, _AWIN_DMA_CTL_BURST_LEN_1@GOTPAGEOFF]
	b	LBB0_12
LBB0_11:
Lloh10:
	adrp	x9, _AWIN_DMA_CTL_BURST_LEN_8@GOTPAGE
Lloh11:
	ldr	x9, [x9, _AWIN_DMA_CTL_BURST_LEN_8@GOTPAGEOFF]
LBB0_12:
	ldr	w9, [x9]
	ldr	w10, [x20, #8]
	cmp	w10, #8
	b.eq	LBB0_16
; %bb.13:
	cmp	w10, #32
	b.eq	LBB0_17
; %bb.14:
	cmp	w10, #16
	b.ne	LBB0_22
; %bb.15:
Lloh12:
	adrp	x10, _AWIN_DMA_CTL_DATA_WIDTH_16@GOTPAGE
Lloh13:
	ldr	x10, [x10, _AWIN_DMA_CTL_DATA_WIDTH_16@GOTPAGEOFF]
	b	LBB0_18
LBB0_16:
Lloh14:
	adrp	x10, _AWIN_DMA_CTL_DATA_WIDTH_8@GOTPAGE
Lloh15:
	ldr	x10, [x10, _AWIN_DMA_CTL_DATA_WIDTH_8@GOTPAGEOFF]
	b	LBB0_18
LBB0_17:
Lloh16:
	adrp	x10, _AWIN_DMA_CTL_DATA_WIDTH_32@GOTPAGE
Lloh17:
	ldr	x10, [x10, _AWIN_DMA_CTL_DATA_WIDTH_32@GOTPAGEOFF]
LBB0_18:
	ldr	w10, [x10]
	ldr	w11, [x20, #12]
	cmp	w11, #1
	b.eq	LBB0_23
; %bb.19:
	cmp	w11, #8
	b.eq	LBB0_24
; %bb.20:
	cmp	w11, #4
	b.ne	LBB0_22
; %bb.21:
Lloh18:
	adrp	x11, _AWIN_DMA_CTL_BURST_LEN_4@GOTPAGE
Lloh19:
	ldr	x11, [x11, _AWIN_DMA_CTL_BURST_LEN_4@GOTPAGEOFF]
	b	LBB0_25
LBB0_22:
Lloh20:
	adrp	x8, _EINVAL@GOTPAGE
Lloh21:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh22:
	ldr	w0, [x8]
	b	LBB0_29
LBB0_23:
Lloh23:
	adrp	x11, _AWIN_DMA_CTL_BURST_LEN_1@GOTPAGE
Lloh24:
	ldr	x11, [x11, _AWIN_DMA_CTL_BURST_LEN_1@GOTPAGEOFF]
	b	LBB0_25
LBB0_24:
Lloh25:
	adrp	x11, _AWIN_DMA_CTL_BURST_LEN_8@GOTPAGE
Lloh26:
	ldr	x11, [x11, _AWIN_DMA_CTL_BURST_LEN_8@GOTPAGEOFF]
LBB0_25:
Lloh27:
	adrp	x12, _AWIN_DMA_CTL_DST_DATA_WIDTH_SHIFT@GOTPAGE
Lloh28:
	ldr	x12, [x12, _AWIN_DMA_CTL_DST_DATA_WIDTH_SHIFT@GOTPAGEOFF]
Lloh29:
	ldr	w12, [x12]
	lsl	w8, w8, w12
Lloh30:
	adrp	x12, _AWIN_DMA_CTL_DST_BURST_LEN_SHIFT@GOTPAGE
Lloh31:
	ldr	x12, [x12, _AWIN_DMA_CTL_DST_BURST_LEN_SHIFT@GOTPAGEOFF]
Lloh32:
	ldr	w12, [x12]
	lsl	w9, w9, w12
	orr	w8, w9, w8
Lloh33:
	adrp	x9, _AWIN_DMA_CTL_DST_DRQ_TYPE_SHIFT@GOTPAGE
Lloh34:
	ldr	x9, [x9, _AWIN_DMA_CTL_DST_DRQ_TYPE_SHIFT@GOTPAGEOFF]
Lloh35:
	ldr	w9, [x9]
	ldp	w12, w13, [x20, #16]
	lsl	w9, w12, w9
	ldr	w11, [x11]
	orr	w8, w8, w9
Lloh36:
	adrp	x9, _AWIN_DMA_CTL_SRC_DATA_WIDTH_SHIFT@GOTPAGE
Lloh37:
	ldr	x9, [x9, _AWIN_DMA_CTL_SRC_DATA_WIDTH_SHIFT@GOTPAGEOFF]
Lloh38:
	ldr	w9, [x9]
	lsl	w9, w10, w9
	orr	w8, w8, w9
Lloh39:
	adrp	x9, _AWIN_DMA_CTL_SRC_BURST_LEN_SHIFT@GOTPAGE
Lloh40:
	ldr	x9, [x9, _AWIN_DMA_CTL_SRC_BURST_LEN_SHIFT@GOTPAGEOFF]
Lloh41:
	ldr	w9, [x9]
	lsl	w9, w11, w9
	orr	w8, w8, w9
Lloh42:
	adrp	x9, _AWIN_DMA_CTL_SRC_DRQ_TYPE_SHIFT@GOTPAGE
Lloh43:
	ldr	x9, [x9, _AWIN_DMA_CTL_SRC_DRQ_TYPE_SHIFT@GOTPAGEOFF]
Lloh44:
	ldr	w9, [x9]
	lsl	w9, w13, w9
	orr	w8, w8, w9
	ldr	x10, [x19]
Lloh45:
	adrp	x9, _CH_NDMA@GOTPAGE
Lloh46:
	ldr	x9, [x9, _CH_NDMA@GOTPAGEOFF]
Lloh47:
	ldr	x11, [x9]
	ldr	x9, [x20, #48]
	cmp	x10, x11
	b.ne	LBB0_27
; %bb.26:
Lloh48:
	adrp	x10, _AWIN_NDMA_CTL_DST_ADDR_NOINCR@GOTPAGE
Lloh49:
	ldr	x10, [x10, _AWIN_NDMA_CTL_DST_ADDR_NOINCR@GOTPAGEOFF]
Lloh50:
	ldr	w10, [x10]
	cmp	x9, #0
	csel	w9, wzr, w10, eq
	orr	w8, w9, w8
	ldr	x9, [x20, #40]
Lloh51:
	adrp	x10, _AWIN_NDMA_CTL_SRC_ADDR_NOINCR@GOTPAGE
Lloh52:
	ldr	x10, [x10, _AWIN_NDMA_CTL_SRC_ADDR_NOINCR@GOTPAGEOFF]
Lloh53:
	ldr	w10, [x10]
	cmp	x9, #0
	csel	w9, wzr, w10, eq
	orr	w2, w8, w9
Lloh54:
	adrp	x8, _AWIN_NDMA_CTL_REG@GOTPAGE
Lloh55:
	ldr	x8, [x8, _AWIN_NDMA_CTL_REG@GOTPAGEOFF]
Lloh56:
	ldr	w1, [x8]
	b	LBB0_28
LBB0_27:
Lloh57:
	adrp	x10, _AWIN_DDMA_CTL_DMA_ADDR_IO@GOTPAGE
Lloh58:
	ldr	x10, [x10, _AWIN_DDMA_CTL_DMA_ADDR_IO@GOTPAGEOFF]
Lloh59:
	ldr	w10, [x10]
Lloh60:
	adrp	x11, _AWIN_DDMA_CTL_DMA_ADDR_LINEAR@GOTPAGE
Lloh61:
	ldr	x11, [x11, _AWIN_DDMA_CTL_DMA_ADDR_LINEAR@GOTPAGEOFF]
Lloh62:
	ldr	w11, [x11]
	cmp	x9, #0
	csel	w9, w11, w10, eq
	ldr	x12, [x20, #40]
	cmp	x12, #0
Lloh63:
	adrp	x12, _AWIN_DDMA_CTL_DST_ADDR_MODE_SHIFT@GOTPAGE
Lloh64:
	ldr	x12, [x12, _AWIN_DDMA_CTL_DST_ADDR_MODE_SHIFT@GOTPAGEOFF]
	csel	w10, w11, w10, eq
Lloh65:
	ldr	w11, [x12]
	lsl	w9, w9, w11
	orr	w8, w9, w8
Lloh66:
	adrp	x9, _AWIN_DDMA_CTL_SRC_ADDR_MODE_SHIFT@GOTPAGE
Lloh67:
	ldr	x9, [x9, _AWIN_DDMA_CTL_SRC_ADDR_MODE_SHIFT@GOTPAGEOFF]
Lloh68:
	ldr	w9, [x9]
	lsl	w9, w10, w9
	orr	w2, w8, w9
Lloh69:
	adrp	x8, _AWIN_DDMA_CTL_REG@GOTPAGE
Lloh70:
	ldr	x8, [x8, _AWIN_DDMA_CTL_REG@GOTPAGEOFF]
Lloh71:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_DMACH_WRITE
	ldp	w8, w9, [x20, #24]
	sub	w8, w8, #1
	sub	w9, w9, #1
	ldp	w10, w11, [x20, #32]
	sub	w10, w10, #1
	sub	w11, w11, #1
Lloh72:
	adrp	x12, _AWIN_DDMA_PARA_REG@GOTPAGE
Lloh73:
	ldr	x12, [x12, _AWIN_DDMA_PARA_REG@GOTPAGEOFF]
Lloh74:
	adrp	x13, _AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_SHIFT@GOTPAGE
Lloh75:
	ldr	x13, [x13, _AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_SHIFT@GOTPAGEOFF]
Lloh76:
	ldr	w1, [x12]
Lloh77:
	ldr	w12, [x13]
	lsl	w8, w8, w12
Lloh78:
	adrp	x12, _AWIN_DDMA_PARA_DST_WAIT_CYC_SHIFT@GOTPAGE
Lloh79:
	ldr	x12, [x12, _AWIN_DDMA_PARA_DST_WAIT_CYC_SHIFT@GOTPAGEOFF]
Lloh80:
	ldr	w12, [x12]
	lsl	w9, w9, w12
	orr	w8, w9, w8
Lloh81:
	adrp	x9, _AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_SHIFT@GOTPAGE
Lloh82:
	ldr	x9, [x9, _AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_SHIFT@GOTPAGEOFF]
Lloh83:
	ldr	w9, [x9]
	lsl	w9, w10, w9
	orr	w8, w8, w9
Lloh84:
	adrp	x9, _AWIN_DDMA_PARA_SRC_WAIT_CYC_SHIFT@GOTPAGE
Lloh85:
	ldr	x9, [x9, _AWIN_DDMA_PARA_SRC_WAIT_CYC_SHIFT@GOTPAGEOFF]
Lloh86:
	ldr	w9, [x9]
	lsl	w9, w11, w9
	orr	w2, w8, w9
LBB0_28:
	mov	x0, x19
	bl	_DMACH_WRITE
	mov	w0, #0
LBB0_29:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh76
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.cfi_endproc
                                        ; -- End function
	.comm	_AWIN_DMA_CTL_DATA_WIDTH_8,4,2  ; @AWIN_DMA_CTL_DATA_WIDTH_8
	.comm	_AWIN_DMA_CTL_DATA_WIDTH_16,4,2 ; @AWIN_DMA_CTL_DATA_WIDTH_16
	.comm	_AWIN_DMA_CTL_DATA_WIDTH_32,4,2 ; @AWIN_DMA_CTL_DATA_WIDTH_32
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_AWIN_DMA_CTL_BURST_LEN_1,4,2   ; @AWIN_DMA_CTL_BURST_LEN_1
	.comm	_AWIN_DMA_CTL_BURST_LEN_4,4,2   ; @AWIN_DMA_CTL_BURST_LEN_4
	.comm	_AWIN_DMA_CTL_BURST_LEN_8,4,2   ; @AWIN_DMA_CTL_BURST_LEN_8
	.comm	_AWIN_DMA_CTL_DST_DATA_WIDTH_SHIFT,4,2 ; @AWIN_DMA_CTL_DST_DATA_WIDTH_SHIFT
	.comm	_AWIN_DMA_CTL_DST_BURST_LEN_SHIFT,4,2 ; @AWIN_DMA_CTL_DST_BURST_LEN_SHIFT
	.comm	_AWIN_DMA_CTL_DST_DRQ_TYPE_SHIFT,4,2 ; @AWIN_DMA_CTL_DST_DRQ_TYPE_SHIFT
	.comm	_AWIN_DMA_CTL_SRC_DATA_WIDTH_SHIFT,4,2 ; @AWIN_DMA_CTL_SRC_DATA_WIDTH_SHIFT
	.comm	_AWIN_DMA_CTL_SRC_BURST_LEN_SHIFT,4,2 ; @AWIN_DMA_CTL_SRC_BURST_LEN_SHIFT
	.comm	_AWIN_DMA_CTL_SRC_DRQ_TYPE_SHIFT,4,2 ; @AWIN_DMA_CTL_SRC_DRQ_TYPE_SHIFT
	.comm	_CH_NDMA,8,3                    ; @CH_NDMA
	.comm	_AWIN_NDMA_CTL_DST_ADDR_NOINCR,4,2 ; @AWIN_NDMA_CTL_DST_ADDR_NOINCR
	.comm	_AWIN_NDMA_CTL_SRC_ADDR_NOINCR,4,2 ; @AWIN_NDMA_CTL_SRC_ADDR_NOINCR
	.comm	_AWIN_NDMA_CTL_REG,4,2          ; @AWIN_NDMA_CTL_REG
	.comm	_AWIN_DDMA_CTL_DMA_ADDR_IO,4,2  ; @AWIN_DDMA_CTL_DMA_ADDR_IO
	.comm	_AWIN_DDMA_CTL_DMA_ADDR_LINEAR,4,2 ; @AWIN_DDMA_CTL_DMA_ADDR_LINEAR
	.comm	_AWIN_DDMA_CTL_DST_ADDR_MODE_SHIFT,4,2 ; @AWIN_DDMA_CTL_DST_ADDR_MODE_SHIFT
	.comm	_AWIN_DDMA_CTL_SRC_ADDR_MODE_SHIFT,4,2 ; @AWIN_DDMA_CTL_SRC_ADDR_MODE_SHIFT
	.comm	_AWIN_DDMA_CTL_REG,4,2          ; @AWIN_DDMA_CTL_REG
	.comm	_AWIN_DDMA_PARA_REG,4,2         ; @AWIN_DDMA_PARA_REG
	.comm	_AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_SHIFT,4,2 ; @AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_SHIFT
	.comm	_AWIN_DDMA_PARA_DST_WAIT_CYC_SHIFT,4,2 ; @AWIN_DDMA_PARA_DST_WAIT_CYC_SHIFT
	.comm	_AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_SHIFT,4,2 ; @AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_SHIFT
	.comm	_AWIN_DDMA_PARA_SRC_WAIT_CYC_SHIFT,4,2 ; @AWIN_DDMA_PARA_SRC_WAIT_CYC_SHIFT
	.no_dead_strip	_a10dmac_set_config
.subsections_via_symbols
