	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_pcie_cfgregopen                ## -- Begin function pcie_cfgregopen
	.p2align	4, 0x90
_pcie_cfgregopen:                       ## @pcie_cfgregopen
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	xorl	%eax, %eax
	testq	%rsi, %rsi
	jne	LBB0_12
## %bb.1:
	movq	_mcfg_enable@GOTPCREL(%rip), %rcx
	cmpl	$0, (%rcx)
	je	LBB0_12
## %bb.2:
	movq	%rdx, %r14
	movl	%edi, %ebx
	movq	_bootverbose@GOTPCREL(%rip), %rax
	cmpq	$0, (%rax)
	je	LBB0_4
## %bb.3:
	leaq	L_.str(%rip), %rdi
	movl	%ebx, %esi
	callq	_printf
LBB0_4:
	movq	%r14, %rsi
	shlq	$20, %rsi
	addq	$1048576, %rsi                  ## imm = 0x100000
	movl	%ebx, %edi
	callq	_pmap_mapdev_pciecfg
	movq	_pcie_base@GOTPCREL(%rip), %rcx
	movq	%rax, (%rcx)
	movq	_pcie_minbus@GOTPCREL(%rip), %rax
	movq	$0, (%rax)
	movq	_pcie_maxbus@GOTPCREL(%rip), %rax
	movq	%r14, (%rax)
	movq	_CFGMECH_PCIE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_cfgmech@GOTPCREL(%rip), %rcx
	movl	%eax, (%rcx)
	xorl	%eax, %eax
	callq	_pci_cfgregopen
	movq	%rax, %rcx
	movl	$1, %eax
	testq	%rcx, %rcx
	je	LBB0_12
## %bb.5:
	movq	_PCI_SLOTMAX@GOTPCREL(%rip), %r15
	cmpl	$0, (%r15)
	js	LBB0_12
## %bb.6:
	movl	$-1, %ebx
	movq	_pcie_badslots@GOTPCREL(%rip), %r12
	jmp	LBB0_7
	.p2align	4, 0x90
LBB0_10:                                ##   in Loop: Header=BB0_7 Depth=1
	cmpl	(%r15), %ebx
	jge	LBB0_11
LBB0_7:                                 ## =>This Inner Loop Header: Depth=1
	incl	%ebx
	xorl	%edi, %edi
	movl	%ebx, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	movl	$4, %r8d
	callq	_pcireg_cfgread
	cmpl	$-1, %eax
	je	LBB0_10
## %bb.8:                               ##   in Loop: Header=BB0_7 Depth=1
	movl	%eax, %r14d
	xorl	%edi, %edi
	movl	%ebx, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	movl	$4, %r8d
	callq	_pciereg_cfgread
	cmpl	%r14d, %eax
	je	LBB0_10
## %bb.9:                               ##   in Loop: Header=BB0_7 Depth=1
	movl	$1, %eax
	movl	%ebx, %ecx
	shll	%cl, %eax
	orl	%eax, (%r12)
	jmp	LBB0_10
LBB0_11:
	movl	$1, %eax
LBB0_12:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_mcfg_enable,4,2                ## @mcfg_enable
	.comm	_bootverbose,8,3                ## @bootverbose
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"PCIe: Memory Mapped configuration base @ 0x%lx\n"

	.comm	_pcie_base,8,3                  ## @pcie_base
	.comm	_pcie_minbus,8,3                ## @pcie_minbus
	.comm	_pcie_maxbus,8,3                ## @pcie_maxbus
	.comm	_CFGMECH_PCIE,4,2               ## @CFGMECH_PCIE
	.comm	_cfgmech,4,2                    ## @cfgmech
	.comm	_PCI_SLOTMAX,4,2                ## @PCI_SLOTMAX
	.comm	_pcie_badslots,4,2              ## @pcie_badslots
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_pcie_cfgregopen                ; -- Begin function pcie_cfgregopen
	.p2align	2
_pcie_cfgregopen:                       ; @pcie_cfgregopen
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x0
	mov	w0, #0
	cbnz	x1, LBB0_12
; %bb.1:
Lloh0:
	adrp	x8, _mcfg_enable@GOTPAGE
Lloh1:
	ldr	x8, [x8, _mcfg_enable@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cbz	w8, LBB0_12
; %bb.2:
	mov	x19, x2
Lloh3:
	adrp	x8, _bootverbose@GOTPAGE
Lloh4:
	ldr	x8, [x8, _bootverbose@GOTPAGEOFF]
Lloh5:
	ldr	x8, [x8]
	cbz	x8, LBB0_4
; %bb.3:
Lloh6:
	adrp	x0, l_.str@PAGE
Lloh7:
	add	x0, x0, l_.str@PAGEOFF
	mov	x1, x20
	bl	_printf
LBB0_4:
	lsl	x8, x19, #20
	add	x1, x8, #256, lsl #12           ; =1048576
	mov	x0, x20
	bl	_pmap_mapdev_pciecfg
Lloh8:
	adrp	x8, _pcie_base@GOTPAGE
Lloh9:
	ldr	x8, [x8, _pcie_base@GOTPAGEOFF]
Lloh10:
	str	x0, [x8]
Lloh11:
	adrp	x8, _pcie_minbus@GOTPAGE
Lloh12:
	ldr	x8, [x8, _pcie_minbus@GOTPAGEOFF]
Lloh13:
	str	xzr, [x8]
Lloh14:
	adrp	x8, _pcie_maxbus@GOTPAGE
Lloh15:
	ldr	x8, [x8, _pcie_maxbus@GOTPAGEOFF]
Lloh16:
	str	x19, [x8]
Lloh17:
	adrp	x8, _CFGMECH_PCIE@GOTPAGE
Lloh18:
	ldr	x8, [x8, _CFGMECH_PCIE@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
Lloh20:
	adrp	x9, _cfgmech@GOTPAGE
Lloh21:
	ldr	x9, [x9, _cfgmech@GOTPAGEOFF]
Lloh22:
	str	w8, [x9]
	bl	_pci_cfgregopen
	mov	x8, x0
	mov	w0, #1
	cbz	x8, LBB0_12
; %bb.5:
Lloh23:
	adrp	x21, _PCI_SLOTMAX@GOTPAGE
Lloh24:
	ldr	x21, [x21, _PCI_SLOTMAX@GOTPAGEOFF]
	ldr	w8, [x21]
	tbnz	w8, #31, LBB0_12
; %bb.6:
	mov	w19, #-1
	mov	w22, #1
Lloh25:
	adrp	x23, _pcie_badslots@GOTPAGE
Lloh26:
	ldr	x23, [x23, _pcie_badslots@GOTPAGEOFF]
	b	LBB0_8
LBB0_7:                                 ;   in Loop: Header=BB0_8 Depth=1
	ldr	w8, [x21]
	cmp	w19, w8
	b.ge	LBB0_11
LBB0_8:                                 ; =>This Inner Loop Header: Depth=1
	add	w19, w19, #1
	mov	w0, #0
	mov	x1, x19
	mov	w2, #0
	mov	w3, #0
	mov	w4, #4
	bl	_pcireg_cfgread
	cmn	w0, #1
	b.eq	LBB0_7
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=1
	mov	x20, x0
	mov	w0, #0
	mov	x1, x19
	mov	w2, #0
	mov	w3, #0
	mov	w4, #4
	bl	_pciereg_cfgread
	cmp	w0, w20
	b.eq	LBB0_7
; %bb.10:                               ;   in Loop: Header=BB0_8 Depth=1
	lsl	w8, w22, w19
	ldr	w9, [x23]
	orr	w8, w9, w8
	str	w8, [x23]
	b	LBB0_7
LBB0_11:
	mov	w0, #1
LBB0_12:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpLdrGotStr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotStr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotStr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotStr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh25, Lloh26
	.cfi_endproc
                                        ; -- End function
	.comm	_mcfg_enable,4,2                ; @mcfg_enable
	.comm	_bootverbose,8,3                ; @bootverbose
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"PCIe: Memory Mapped configuration base @ 0x%lx\n"

	.comm	_pcie_base,8,3                  ; @pcie_base
	.comm	_pcie_minbus,8,3                ; @pcie_minbus
	.comm	_pcie_maxbus,8,3                ; @pcie_maxbus
	.comm	_CFGMECH_PCIE,4,2               ; @CFGMECH_PCIE
	.comm	_cfgmech,4,2                    ; @cfgmech
	.comm	_PCI_SLOTMAX,4,2                ; @PCI_SLOTMAX
	.comm	_pcie_badslots,4,2              ; @pcie_badslots
.subsections_via_symbols
