	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_pcib_wait_for_link
_tegra_pcib_wait_for_link:              ## @tegra_pcib_wait_for_link
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %r15
	movl	(%rdi), %edi
	movl	(%rsi), %edx
	movq	_RP_PRIV_MISC@GOTPCREL(%rip), %rbx
	movl	(%rbx), %r8d
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	movl	$4, %r9d
	callq	_tegra_pcib_read_config
	movq	_RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r9d
	notl	%r9d
	andl	%eax, %r9d
	movq	_RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT@GOTPCREL(%rip), %rax
	orl	(%rax), %r9d
	movl	(%r15), %edi
	movl	(%r14), %edx
	movl	(%rbx), %r8d
	movl	$4, (%rsp)
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_tegra_pcib_write_config
	movq	_TEGRA_PCIE_LINKUP_TIMEOUT@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	testl	%ebx, %ebx
	jle	LBB0_8
## %bb.1:
	incl	%ebx
	movq	_RP_VEND_XP@GOTPCREL(%rip), %r13
	movq	_RP_VEND_XP_DL_UP@GOTPCREL(%rip), %r12
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r15), %edi
	movl	(%r14), %edx
	movl	(%r13), %r8d
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	movl	$4, %r9d
	callq	_tegra_pcib_read_config
	testl	%eax, (%r12)
	jne	LBB0_4
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movl	$1, %edi
	callq	_DELAY
	decl	%ebx
	cmpl	$1, %ebx
	jg	LBB0_2
	jmp	LBB0_8
LBB0_4:
	movq	_TEGRA_PCIE_LINKUP_TIMEOUT@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	testl	%ebx, %ebx
	jle	LBB0_8
## %bb.5:
	incl	%ebx
	movq	_RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE@GOTPCREL(%rip), %r13
	xorl	%r12d, %r12d
	.p2align	4, 0x90
LBB0_6:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r15), %edi
	movl	(%r14), %edx
	movq	_RP_LINK_CONTROL_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	movl	$4, %r9d
	callq	_tegra_pcib_read_config
	testl	%eax, (%r13)
	jne	LBB0_9
## %bb.7:                               ##   in Loop: Header=BB0_6 Depth=1
	movl	$1, %edi
	callq	_DELAY
	decl	%ebx
	cmpl	$1, %ebx
	jg	LBB0_6
LBB0_8:
	movq	_ETIMEDOUT@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
LBB0_9:
	movl	%r12d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RP_PRIV_MISC,4,2               ## @RP_PRIV_MISC
	.comm	_RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT,4,2 ## @RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT
	.comm	_RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT,4,2 ## @RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT
	.comm	_TEGRA_PCIE_LINKUP_TIMEOUT,4,2  ## @TEGRA_PCIE_LINKUP_TIMEOUT
	.comm	_RP_VEND_XP,4,2                 ## @RP_VEND_XP
	.comm	_RP_VEND_XP_DL_UP,4,2           ## @RP_VEND_XP_DL_UP
	.comm	_ETIMEDOUT,4,2                  ## @ETIMEDOUT
	.comm	_RP_LINK_CONTROL_STATUS,4,2     ## @RP_LINK_CONTROL_STATUS
	.comm	_RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE,4,2 ## @RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE
	.no_dead_strip	_tegra_pcib_wait_for_link
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_pcib_wait_for_link
_tegra_pcib_wait_for_link:              ; @tegra_pcib_wait_for_link
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x1
	mov	x20, x0
	ldr	w0, [x0]
	ldr	w2, [x1]
Lloh0:
	adrp	x21, _RP_PRIV_MISC@GOTPAGE
Lloh1:
	ldr	x21, [x21, _RP_PRIV_MISC@GOTPAGEOFF]
	ldr	w4, [x21]
	mov	w1, #0
	mov	w3, #0
	mov	w5, #4
	bl	_tegra_pcib_read_config
Lloh2:
	adrp	x8, _RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT@GOTPAGE
Lloh3:
	ldr	x8, [x8, _RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
Lloh5:
	adrp	x9, _RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT@GOTPAGE
Lloh6:
	ldr	x9, [x9, _RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT@GOTPAGEOFF]
	bic	w8, w0, w8
Lloh7:
	ldr	w9, [x9]
	orr	w5, w8, w9
	ldr	w0, [x20]
	ldr	w2, [x19]
	ldr	w4, [x21]
	mov	w1, #0
	mov	w3, #0
	mov	w6, #4
	bl	_tegra_pcib_write_config
Lloh8:
	adrp	x21, _TEGRA_PCIE_LINKUP_TIMEOUT@GOTPAGE
Lloh9:
	ldr	x21, [x21, _TEGRA_PCIE_LINKUP_TIMEOUT@GOTPAGEOFF]
	ldr	w8, [x21]
	cmp	w8, #1
	b.lt	LBB0_8
; %bb.1:
	add	w22, w8, #1
Lloh10:
	adrp	x23, _RP_VEND_XP@GOTPAGE
Lloh11:
	ldr	x23, [x23, _RP_VEND_XP@GOTPAGEOFF]
Lloh12:
	adrp	x24, _RP_VEND_XP_DL_UP@GOTPAGE
Lloh13:
	ldr	x24, [x24, _RP_VEND_XP_DL_UP@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x20]
	ldr	w2, [x19]
	ldr	w4, [x23]
	mov	w1, #0
	mov	w3, #0
	mov	w5, #4
	bl	_tegra_pcib_read_config
	ldr	w8, [x24]
	tst	w8, w0
	b.ne	LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	mov	w0, #1
	bl	_DELAY
	sub	w22, w22, #1
	cmp	w22, #1
	b.gt	LBB0_2
	b	LBB0_8
LBB0_4:
	ldr	w8, [x21]
	cmp	w8, #1
	b.lt	LBB0_8
; %bb.5:
	add	w21, w8, #1
Lloh14:
	adrp	x22, _RP_LINK_CONTROL_STATUS@GOTPAGE
Lloh15:
	ldr	x22, [x22, _RP_LINK_CONTROL_STATUS@GOTPAGEOFF]
Lloh16:
	adrp	x23, _RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE@GOTPAGE
Lloh17:
	ldr	x23, [x23, _RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE@GOTPAGEOFF]
LBB0_6:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x20]
	ldr	w2, [x19]
	ldr	w4, [x22]
	mov	w1, #0
	mov	w3, #0
	mov	w5, #4
	bl	_tegra_pcib_read_config
	ldr	w8, [x23]
	tst	w8, w0
	b.ne	LBB0_10
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=1
	mov	w0, #1
	bl	_DELAY
	sub	w21, w21, #1
	cmp	w21, #1
	b.gt	LBB0_6
LBB0_8:
Lloh18:
	adrp	x8, _ETIMEDOUT@GOTPAGE
Lloh19:
	ldr	x8, [x8, _ETIMEDOUT@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
LBB0_9:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_10:
	mov	w0, #0
	b	LBB0_9
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.cfi_endproc
                                        ; -- End function
	.comm	_RP_PRIV_MISC,4,2               ; @RP_PRIV_MISC
	.comm	_RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT,4,2 ; @RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT
	.comm	_RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT,4,2 ; @RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT
	.comm	_TEGRA_PCIE_LINKUP_TIMEOUT,4,2  ; @TEGRA_PCIE_LINKUP_TIMEOUT
	.comm	_RP_VEND_XP,4,2                 ; @RP_VEND_XP
	.comm	_RP_VEND_XP_DL_UP,4,2           ; @RP_VEND_XP_DL_UP
	.comm	_ETIMEDOUT,4,2                  ; @ETIMEDOUT
	.comm	_RP_LINK_CONTROL_STATUS,4,2     ; @RP_LINK_CONTROL_STATUS
	.comm	_RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE,4,2 ; @RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE
	.no_dead_strip	_tegra_pcib_wait_for_link
.subsections_via_symbols
