	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function plle_enable
_plle_enable:                           ## @plle_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movl	4(%rdi), %esi
	leaq	-44(%rbp), %r14
	movq	%r14, %rdx
	callq	_RD4
	movq	_PLLE_BASE_LOCK_OVERRIDE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	andl	-44(%rbp), %edx
	movl	%edx, -44(%rbp)
	movl	4(%r12), %esi
	movq	%r12, %rdi
	callq	_WR4
	movq	_PLLE_AUX@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%r12, %rdi
	movq	%r14, %rdx
	callq	_RD4
	movq	_PLLE_AUX_ENABLE_SWCTL@GOTPCREL(%rip), %rcx
	movl	-44(%rbp), %eax
	orl	(%rcx), %eax
	movq	_PLLE_AUX_SEQ_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movl	%edx, -44(%rbp)
	movl	(%r13), %esi
	movq	%r12, %rdi
	callq	_WR4
	movl	$10, %edi
	callq	_DELAY
	movl	(%r12), %esi
	movq	%r12, %rdi
	movq	%r14, %rdx
	callq	_RD4
	movq	_PLLE_MISC_LOCK_ENABLE@GOTPCREL(%rip), %rax
	movl	-44(%rbp), %ecx
	orl	(%rax), %ecx
	movq	_PLLE_MISC_IDDQ_SWCTL@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_PLLE_MISC_IDDQ_OVERRIDE_VALUE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	andl	%ecx, %edx
	movq	_PLLE_MISC_PTS@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_PLLE_MISC_VREG_BG_CTRL_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_PLLE_MISC_VREG_CTRL_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	%edx, -44(%rbp)
	movl	(%r12), %esi
	movq	%r12, %rdi
	callq	_WR4
	movl	$10, %edi
	callq	_DELAY
	movq	_PLLE_SS_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r12, %rdi
	movq	%r14, %rdx
	callq	_RD4
	movq	_PLLE_SS_CNTL_DISABLE@GOTPCREL(%rip), %rax
	movl	-44(%rbp), %edx
	orl	(%rax), %edx
	movl	%edx, -44(%rbp)
	movl	(%r15), %esi
	movq	%r12, %rdi
	callq	_WR4
	movl	4(%r12), %esi
	movq	%r12, %rdi
	movq	%r14, %rdx
	callq	_RD4
	movl	-44(%rbp), %esi
	movl	$13, %ebx
	movq	%r12, %rdi
	movl	$1, %edx
	movl	$200, %ecx
	movl	$13, %r8d
	callq	_set_divisors
	movq	_PLLE_BASE_DIVCML_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_PLLE_BASE_DIVCML_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	notl	%edx
	shll	%cl, %ebx
	andl	%eax, %edx
	orl	%edx, %ebx
	movl	%ebx, -44(%rbp)
	movl	4(%r12), %esi
	movq	%r12, %rdi
	movl	%ebx, %edx
	callq	_WR4
	movl	$10, %edi
	callq	_DELAY
	movq	%r12, %rdi
	callq	_pll_enable
	movq	%r12, %rdi
	callq	_wait_for_lock
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	LBB0_2
## %bb.1:
	movl	(%r15), %esi
	leaq	-44(%rbp), %rdx
	movq	%r12, %rdi
	movq	%rdx, %rbx
	callq	_RD4
	movq	_PLLE_SS_CNTL_SSCCENTER@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_PLLE_SS_CNTL_SSCINVERT@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_PLLE_SS_CNTL_COEFFICIENTS_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	notl	%edx
	andl	-44(%rbp), %edx
	movq	_PLLE_SS_CNTL_COEFFICIENTS_VAL@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	%edx, -44(%rbp)
	movl	(%r15), %esi
	movq	%r12, %rdi
	callq	_WR4
	movq	_PLLE_SS_CNTL_SSCBYP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_PLLE_SS_CNTL_BYPASS_SS@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	notl	%edx
	andl	-44(%rbp), %edx
	movl	%edx, -44(%rbp)
	movl	(%r15), %esi
	movq	%r12, %rdi
	callq	_WR4
	movl	$10, %edi
	callq	_DELAY
	movq	_PLLE_SS_CNTL_INTERP_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	andl	-44(%rbp), %edx
	movl	%edx, -44(%rbp)
	movl	(%r15), %esi
	movq	%r12, %rdi
	callq	_WR4
	movl	$10, %edi
	callq	_DELAY
	movl	(%r12), %esi
	movq	%r12, %rdi
	movq	%rbx, %r15
	movq	%rbx, %rdx
	callq	_RD4
	movq	_PLLE_MISC_IDDQ_SWCTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	andl	-44(%rbp), %edx
	movl	%edx, -44(%rbp)
	movl	(%r12), %esi
	movq	%r12, %rdi
	callq	_WR4
	movl	(%r13), %esi
	movq	%r12, %rdi
	movq	%rbx, %rdx
	callq	_RD4
	movq	_PLLE_AUX_USE_LOCKDET@GOTPCREL(%rip), %rax
	movl	-44(%rbp), %ecx
	orl	(%rax), %ecx
	movq	_PLLE_AUX_SEQ_START_STATE@GOTPCREL(%rip), %rbx
	orl	(%rbx), %ecx
	movq	_PLLE_AUX_ENABLE_SWCTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_PLLE_AUX_SS_SWCTL@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	notl	%edx
	andl	%ecx, %edx
	movl	%edx, -44(%rbp)
	movl	(%r13), %esi
	movq	%r12, %rdi
	callq	_WR4
	movl	(%rbx), %eax
	orl	%eax, -44(%rbp)
	movl	$10, %edi
	callq	_DELAY
	movl	-44(%rbp), %edx
	movq	_PLLE_AUX_SEQ_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	%edx, -44(%rbp)
	movl	(%r13), %esi
	movq	%r12, %rdi
	callq	_WR4
	movq	_XUSBIO_PLL_CFG0@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	movq	%r15, %rdx
	movq	%r15, %r13
	callq	_RD4
	movq	_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET@GOTPCREL(%rip), %rax
	movl	-44(%rbp), %ecx
	orl	(%rax), %ecx
	movq	_XUSBIO_PLL_CFG0_SEQ_START_STATE@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	notl	%edx
	andl	%ecx, %edx
	movl	%edx, -44(%rbp)
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_WR4
	movl	$10, %edi
	callq	_DELAY
	movq	_XUSBIO_PLL_CFG0_SEQ_ENABLE@GOTPCREL(%rip), %rax
	movl	-44(%rbp), %edx
	orl	(%rax), %edx
	movl	%edx, -44(%rbp)
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_WR4
	movq	_SATA_PLL_CFG0@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r12, %rdi
	movq	%r13, %rdx
	callq	_RD4
	movq	_SATA_PLL_CFG0_PADPLL_RESET_SWCTL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	notl	%eax
	andl	-44(%rbp), %eax
	movq	_SATA_PLL_CFG0_PADPLL_USE_LOCKDET@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_SATA_PLL_CFG0_SEQ_IN_SWCTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	_SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	_SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	_SATA_PLL_CFG0_SEQ_ENABLE@GOTPCREL(%rip), %rbx
	orl	(%rbx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	_SATA_PLL_CFG0_SEQ_START_STATE@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	%edx, -44(%rbp)
	movl	(%r15), %esi
	movq	%r12, %rdi
	callq	_WR4
	movl	$10, %edi
	callq	_DELAY
	movl	-44(%rbp), %edx
	orl	(%rbx), %edx
	movl	%edx, -44(%rbp)
	movl	(%r15), %esi
	movq	%r12, %rdi
	callq	_WR4
	movq	_PCIE_PLL_CFG0@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	movq	%r13, %rdx
	callq	_RD4
	movq	_PCIE_PLL_CFG0_SEQ_ENABLE@GOTPCREL(%rip), %rax
	movl	-44(%rbp), %edx
	orl	(%rax), %edx
	movl	%edx, -44(%rbp)
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_WR4
LBB0_2:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PLLE_BASE_LOCK_OVERRIDE,4,2    ## @PLLE_BASE_LOCK_OVERRIDE
	.comm	_PLLE_AUX,4,2                   ## @PLLE_AUX
	.comm	_PLLE_AUX_ENABLE_SWCTL,4,2      ## @PLLE_AUX_ENABLE_SWCTL
	.comm	_PLLE_AUX_SEQ_ENABLE,4,2        ## @PLLE_AUX_SEQ_ENABLE
	.comm	_PLLE_MISC_LOCK_ENABLE,4,2      ## @PLLE_MISC_LOCK_ENABLE
	.comm	_PLLE_MISC_IDDQ_SWCTL,4,2       ## @PLLE_MISC_IDDQ_SWCTL
	.comm	_PLLE_MISC_IDDQ_OVERRIDE_VALUE,4,2 ## @PLLE_MISC_IDDQ_OVERRIDE_VALUE
	.comm	_PLLE_MISC_PTS,4,2              ## @PLLE_MISC_PTS
	.comm	_PLLE_MISC_VREG_BG_CTRL_MASK,4,2 ## @PLLE_MISC_VREG_BG_CTRL_MASK
	.comm	_PLLE_MISC_VREG_CTRL_MASK,4,2   ## @PLLE_MISC_VREG_CTRL_MASK
	.comm	_PLLE_SS_CNTL,4,2               ## @PLLE_SS_CNTL
	.comm	_PLLE_SS_CNTL_DISABLE,4,2       ## @PLLE_SS_CNTL_DISABLE
	.comm	_PLLE_BASE_DIVCML_MASK,4,2      ## @PLLE_BASE_DIVCML_MASK
	.comm	_PLLE_BASE_DIVCML_SHIFT,4,2     ## @PLLE_BASE_DIVCML_SHIFT
	.comm	_PLLE_SS_CNTL_SSCCENTER,4,2     ## @PLLE_SS_CNTL_SSCCENTER
	.comm	_PLLE_SS_CNTL_SSCINVERT,4,2     ## @PLLE_SS_CNTL_SSCINVERT
	.comm	_PLLE_SS_CNTL_COEFFICIENTS_MASK,4,2 ## @PLLE_SS_CNTL_COEFFICIENTS_MASK
	.comm	_PLLE_SS_CNTL_COEFFICIENTS_VAL,4,2 ## @PLLE_SS_CNTL_COEFFICIENTS_VAL
	.comm	_PLLE_SS_CNTL_SSCBYP,4,2        ## @PLLE_SS_CNTL_SSCBYP
	.comm	_PLLE_SS_CNTL_BYPASS_SS,4,2     ## @PLLE_SS_CNTL_BYPASS_SS
	.comm	_PLLE_SS_CNTL_INTERP_RESET,4,2  ## @PLLE_SS_CNTL_INTERP_RESET
	.comm	_PLLE_AUX_USE_LOCKDET,4,2       ## @PLLE_AUX_USE_LOCKDET
	.comm	_PLLE_AUX_SEQ_START_STATE,4,2   ## @PLLE_AUX_SEQ_START_STATE
	.comm	_PLLE_AUX_SS_SWCTL,4,2          ## @PLLE_AUX_SS_SWCTL
	.comm	_XUSBIO_PLL_CFG0,4,2            ## @XUSBIO_PLL_CFG0
	.comm	_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET,4,2 ## @XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET
	.comm	_XUSBIO_PLL_CFG0_SEQ_START_STATE,4,2 ## @XUSBIO_PLL_CFG0_SEQ_START_STATE
	.comm	_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL,4,2 ## @XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL
	.comm	_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL,4,2 ## @XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL
	.comm	_XUSBIO_PLL_CFG0_SEQ_ENABLE,4,2 ## @XUSBIO_PLL_CFG0_SEQ_ENABLE
	.comm	_SATA_PLL_CFG0,4,2              ## @SATA_PLL_CFG0
	.comm	_SATA_PLL_CFG0_PADPLL_RESET_SWCTL,4,2 ## @SATA_PLL_CFG0_PADPLL_RESET_SWCTL
	.comm	_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE,4,2 ## @SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE
	.comm	_SATA_PLL_CFG0_PADPLL_USE_LOCKDET,4,2 ## @SATA_PLL_CFG0_PADPLL_USE_LOCKDET
	.comm	_SATA_PLL_CFG0_SEQ_IN_SWCTL,4,2 ## @SATA_PLL_CFG0_SEQ_IN_SWCTL
	.comm	_SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE,4,2 ## @SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE
	.comm	_SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE,4,2 ## @SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE
	.comm	_SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE,4,2 ## @SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE
	.comm	_SATA_PLL_CFG0_SEQ_ENABLE,4,2   ## @SATA_PLL_CFG0_SEQ_ENABLE
	.comm	_SATA_PLL_CFG0_SEQ_START_STATE,4,2 ## @SATA_PLL_CFG0_SEQ_START_STATE
	.comm	_PCIE_PLL_CFG0,4,2              ## @PCIE_PLL_CFG0
	.comm	_PCIE_PLL_CFG0_SEQ_ENABLE,4,2   ## @PCIE_PLL_CFG0_SEQ_ENABLE
	.no_dead_strip	_plle_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function plle_enable
_plle_enable:                           ; @plle_enable
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldr	w1, [x0, #4]
	add	x2, sp, #12
	bl	_RD4
Lloh0:
	adrp	x8, _PLLE_BASE_LOCK_OVERRIDE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PLLE_BASE_LOCK_OVERRIDE@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	bic	w2, w9, w8
	str	w2, [sp, #12]
	ldr	w1, [x19, #4]
	mov	x0, x19
	bl	_WR4
Lloh3:
	adrp	x21, _PLLE_AUX@GOTPAGE
Lloh4:
	ldr	x21, [x21, _PLLE_AUX@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x2, sp, #12
	mov	x0, x19
	bl	_RD4
Lloh5:
	adrp	x23, _PLLE_AUX_ENABLE_SWCTL@GOTPAGE
Lloh6:
	ldr	x23, [x23, _PLLE_AUX_ENABLE_SWCTL@GOTPAGEOFF]
	ldr	w8, [x23]
	ldr	w9, [sp, #12]
	orr	w8, w9, w8
Lloh7:
	adrp	x22, _PLLE_AUX_SEQ_ENABLE@GOTPAGE
Lloh8:
	ldr	x22, [x22, _PLLE_AUX_SEQ_ENABLE@GOTPAGEOFF]
	ldr	w9, [x22]
	bic	w2, w8, w9
	str	w2, [sp, #12]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_WR4
	mov	w0, #10
	bl	_DELAY
	ldr	w1, [x19]
	add	x2, sp, #12
	mov	x0, x19
	bl	_RD4
Lloh9:
	adrp	x8, _PLLE_MISC_LOCK_ENABLE@GOTPAGE
Lloh10:
	ldr	x8, [x8, _PLLE_MISC_LOCK_ENABLE@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	orr	w8, w9, w8
Lloh12:
	adrp	x24, _PLLE_MISC_IDDQ_SWCTL@GOTPAGE
Lloh13:
	ldr	x24, [x24, _PLLE_MISC_IDDQ_SWCTL@GOTPAGEOFF]
	ldr	w9, [x24]
	orr	w8, w9, w8
Lloh14:
	adrp	x9, _PLLE_MISC_IDDQ_OVERRIDE_VALUE@GOTPAGE
Lloh15:
	ldr	x9, [x9, _PLLE_MISC_IDDQ_OVERRIDE_VALUE@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
	bic	w8, w8, w9
Lloh17:
	adrp	x9, _PLLE_MISC_PTS@GOTPAGE
Lloh18:
	ldr	x9, [x9, _PLLE_MISC_PTS@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh20:
	adrp	x9, _PLLE_MISC_VREG_BG_CTRL_MASK@GOTPAGE
Lloh21:
	ldr	x9, [x9, _PLLE_MISC_VREG_BG_CTRL_MASK@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh23:
	adrp	x9, _PLLE_MISC_VREG_CTRL_MASK@GOTPAGE
Lloh24:
	ldr	x9, [x9, _PLLE_MISC_VREG_CTRL_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w9, [x9]
	orr	w2, w9, w8
	str	w2, [sp, #12]
	ldr	w1, [x19]
	mov	x0, x19
	bl	_WR4
	mov	w0, #10
	bl	_DELAY
Lloh26:
	adrp	x25, _PLLE_SS_CNTL@GOTPAGE
Lloh27:
	ldr	x25, [x25, _PLLE_SS_CNTL@GOTPAGEOFF]
	ldr	w1, [x25]
	add	x2, sp, #12
	mov	x0, x19
	bl	_RD4
Lloh28:
	adrp	x8, _PLLE_SS_CNTL_DISABLE@GOTPAGE
Lloh29:
	ldr	x8, [x8, _PLLE_SS_CNTL_DISABLE@GOTPAGEOFF]
Lloh30:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	orr	w2, w9, w8
	str	w2, [sp, #12]
	ldr	w1, [x25]
	mov	x0, x19
	bl	_WR4
	ldr	w1, [x19, #4]
	add	x2, sp, #12
	mov	x0, x19
	bl	_RD4
	ldr	w1, [sp, #12]
	mov	w20, #13
	mov	x0, x19
	mov	w2, #1
	mov	w3, #200
	mov	w4, #13
	bl	_set_divisors
Lloh31:
	adrp	x8, _PLLE_BASE_DIVCML_MASK@GOTPAGE
Lloh32:
	ldr	x8, [x8, _PLLE_BASE_DIVCML_MASK@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
Lloh34:
	adrp	x9, _PLLE_BASE_DIVCML_SHIFT@GOTPAGE
Lloh35:
	ldr	x9, [x9, _PLLE_BASE_DIVCML_SHIFT@GOTPAGEOFF]
Lloh36:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	bic	w8, w0, w8
	lsl	w9, w20, w9
	orr	w2, w8, w9
	str	w2, [sp, #12]
	ldr	w1, [x19, #4]
	mov	x0, x19
	bl	_WR4
	mov	w0, #10
	bl	_DELAY
	mov	x0, x19
	bl	_pll_enable
	mov	x0, x19
	bl	_wait_for_lock
	mov	x20, x0
	cbnz	w0, LBB0_2
; %bb.1:
	ldr	w1, [x25]
	add	x2, sp, #12
	mov	x0, x19
	bl	_RD4
Lloh37:
	adrp	x8, _PLLE_SS_CNTL_SSCCENTER@GOTPAGE
Lloh38:
	ldr	x8, [x8, _PLLE_SS_CNTL_SSCCENTER@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
Lloh40:
	adrp	x10, _PLLE_SS_CNTL_SSCINVERT@GOTPAGE
Lloh41:
	ldr	x10, [x10, _PLLE_SS_CNTL_SSCINVERT@GOTPAGEOFF]
Lloh42:
	ldr	w10, [x10]
	orr	w8, w8, w10
Lloh43:
	adrp	x10, _PLLE_SS_CNTL_COEFFICIENTS_MASK@GOTPAGE
Lloh44:
	ldr	x10, [x10, _PLLE_SS_CNTL_COEFFICIENTS_MASK@GOTPAGEOFF]
Lloh45:
	ldr	w10, [x10]
	orr	w8, w8, w10
	bic	w8, w9, w8
Lloh46:
	adrp	x9, _PLLE_SS_CNTL_COEFFICIENTS_VAL@GOTPAGE
Lloh47:
	ldr	x9, [x9, _PLLE_SS_CNTL_COEFFICIENTS_VAL@GOTPAGEOFF]
Lloh48:
	ldr	w9, [x9]
	orr	w2, w9, w8
	str	w2, [sp, #12]
	ldr	w1, [x25]
	mov	x0, x19
	bl	_WR4
Lloh49:
	adrp	x8, _PLLE_SS_CNTL_SSCBYP@GOTPAGE
Lloh50:
	ldr	x8, [x8, _PLLE_SS_CNTL_SSCBYP@GOTPAGEOFF]
Lloh51:
	ldr	w8, [x8]
Lloh52:
	adrp	x9, _PLLE_SS_CNTL_BYPASS_SS@GOTPAGE
Lloh53:
	ldr	x9, [x9, _PLLE_SS_CNTL_BYPASS_SS@GOTPAGEOFF]
	ldr	w10, [sp, #12]
Lloh54:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w2, w10, w8
	str	w2, [sp, #12]
	ldr	w1, [x25]
	mov	x0, x19
	bl	_WR4
	mov	w0, #10
	bl	_DELAY
Lloh55:
	adrp	x8, _PLLE_SS_CNTL_INTERP_RESET@GOTPAGE
Lloh56:
	ldr	x8, [x8, _PLLE_SS_CNTL_INTERP_RESET@GOTPAGEOFF]
Lloh57:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	bic	w2, w9, w8
	str	w2, [sp, #12]
	ldr	w1, [x25]
	mov	x0, x19
	bl	_WR4
	mov	w0, #10
	bl	_DELAY
	ldr	w1, [x19]
	add	x2, sp, #12
	mov	x0, x19
	bl	_RD4
	ldr	w8, [x24]
	ldr	w9, [sp, #12]
	bic	w2, w9, w8
	str	w2, [sp, #12]
	ldr	w1, [x19]
	mov	x0, x19
	bl	_WR4
	ldr	w1, [x21]
	add	x2, sp, #12
	mov	x0, x19
	bl	_RD4
Lloh58:
	adrp	x8, _PLLE_AUX_USE_LOCKDET@GOTPAGE
Lloh59:
	ldr	x8, [x8, _PLLE_AUX_USE_LOCKDET@GOTPAGEOFF]
Lloh60:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	orr	w8, w9, w8
Lloh61:
	adrp	x24, _PLLE_AUX_SEQ_START_STATE@GOTPAGE
Lloh62:
	ldr	x24, [x24, _PLLE_AUX_SEQ_START_STATE@GOTPAGEOFF]
	ldr	w9, [x24]
	orr	w8, w9, w8
Lloh63:
	adrp	x9, _PLLE_AUX_SS_SWCTL@GOTPAGE
Lloh64:
	ldr	x9, [x9, _PLLE_AUX_SS_SWCTL@GOTPAGEOFF]
	ldr	w10, [x23]
Lloh65:
	ldr	w9, [x9]
	orr	w9, w10, w9
	bic	w2, w8, w9
	str	w2, [sp, #12]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_WR4
	ldr	w8, [x24]
	ldr	w9, [sp, #12]
	orr	w8, w9, w8
	str	w8, [sp, #12]
	mov	w0, #10
	bl	_DELAY
	ldr	w8, [x22]
	ldr	w9, [sp, #12]
	orr	w2, w9, w8
	str	w2, [sp, #12]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_WR4
Lloh66:
	adrp	x21, _XUSBIO_PLL_CFG0@GOTPAGE
Lloh67:
	ldr	x21, [x21, _XUSBIO_PLL_CFG0@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x2, sp, #12
	mov	x0, x19
	bl	_RD4
Lloh68:
	adrp	x8, _XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET@GOTPAGE
Lloh69:
	ldr	x8, [x8, _XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET@GOTPAGEOFF]
Lloh70:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	orr	w8, w9, w8
Lloh71:
	adrp	x9, _XUSBIO_PLL_CFG0_SEQ_START_STATE@GOTPAGE
Lloh72:
	ldr	x9, [x9, _XUSBIO_PLL_CFG0_SEQ_START_STATE@GOTPAGEOFF]
Lloh73:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh74:
	adrp	x9, _XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL@GOTPAGE
Lloh75:
	ldr	x9, [x9, _XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL@GOTPAGEOFF]
Lloh76:
	adrp	x10, _XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL@GOTPAGE
Lloh77:
	ldr	x10, [x10, _XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL@GOTPAGEOFF]
Lloh78:
	ldr	w9, [x9]
Lloh79:
	ldr	w10, [x10]
	orr	w9, w9, w10
	bic	w2, w8, w9
	str	w2, [sp, #12]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_WR4
	mov	w0, #10
	bl	_DELAY
Lloh80:
	adrp	x8, _XUSBIO_PLL_CFG0_SEQ_ENABLE@GOTPAGE
Lloh81:
	ldr	x8, [x8, _XUSBIO_PLL_CFG0_SEQ_ENABLE@GOTPAGEOFF]
Lloh82:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	orr	w2, w9, w8
	str	w2, [sp, #12]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_WR4
Lloh83:
	adrp	x21, _SATA_PLL_CFG0@GOTPAGE
Lloh84:
	ldr	x21, [x21, _SATA_PLL_CFG0@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x2, sp, #12
	mov	x0, x19
	bl	_RD4
Lloh85:
	adrp	x8, _SATA_PLL_CFG0_PADPLL_RESET_SWCTL@GOTPAGE
Lloh86:
	ldr	x8, [x8, _SATA_PLL_CFG0_PADPLL_RESET_SWCTL@GOTPAGEOFF]
Lloh87:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
Lloh88:
	adrp	x10, _SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE@GOTPAGE
Lloh89:
	ldr	x10, [x10, _SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE@GOTPAGEOFF]
Lloh90:
	ldr	w10, [x10]
	orr	w8, w8, w10
	bic	w8, w9, w8
Lloh91:
	adrp	x9, _SATA_PLL_CFG0_PADPLL_USE_LOCKDET@GOTPAGE
Lloh92:
	ldr	x9, [x9, _SATA_PLL_CFG0_PADPLL_USE_LOCKDET@GOTPAGEOFF]
Lloh93:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh94:
	adrp	x9, _SATA_PLL_CFG0_SEQ_IN_SWCTL@GOTPAGE
Lloh95:
	ldr	x9, [x9, _SATA_PLL_CFG0_SEQ_IN_SWCTL@GOTPAGEOFF]
Lloh96:
	ldr	w9, [x9]
Lloh97:
	adrp	x10, _SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE@GOTPAGE
Lloh98:
	ldr	x10, [x10, _SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE@GOTPAGEOFF]
Lloh99:
	ldr	w10, [x10]
Lloh100:
	adrp	x11, _SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE@GOTPAGE
Lloh101:
	ldr	x11, [x11, _SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE@GOTPAGEOFF]
	orr	w9, w9, w10
Lloh102:
	ldr	w10, [x11]
	orr	w9, w9, w10
Lloh103:
	adrp	x10, _SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE@GOTPAGE
Lloh104:
	ldr	x10, [x10, _SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE@GOTPAGEOFF]
Lloh105:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh106:
	adrp	x22, _SATA_PLL_CFG0_SEQ_ENABLE@GOTPAGE
Lloh107:
	ldr	x22, [x22, _SATA_PLL_CFG0_SEQ_ENABLE@GOTPAGEOFF]
	ldr	w10, [x22]
	orr	w9, w9, w10
	bic	w8, w8, w9
Lloh108:
	adrp	x9, _SATA_PLL_CFG0_SEQ_START_STATE@GOTPAGE
Lloh109:
	ldr	x9, [x9, _SATA_PLL_CFG0_SEQ_START_STATE@GOTPAGEOFF]
Lloh110:
	ldr	w9, [x9]
	orr	w2, w9, w8
	str	w2, [sp, #12]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_WR4
	mov	w0, #10
	bl	_DELAY
	ldr	w8, [x22]
	ldr	w9, [sp, #12]
	orr	w2, w9, w8
	str	w2, [sp, #12]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_WR4
Lloh111:
	adrp	x21, _PCIE_PLL_CFG0@GOTPAGE
Lloh112:
	ldr	x21, [x21, _PCIE_PLL_CFG0@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x2, sp, #12
	mov	x0, x19
	bl	_RD4
Lloh113:
	adrp	x8, _PCIE_PLL_CFG0_SEQ_ENABLE@GOTPAGE
Lloh114:
	ldr	x8, [x8, _PCIE_PLL_CFG0_SEQ_ENABLE@GOTPAGEOFF]
Lloh115:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	orr	w2, w9, w8
	str	w2, [sp, #12]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_WR4
LBB0_2:
	mov	x0, x20
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGot	Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGot	Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGot	Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh78
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGot	Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.cfi_endproc
                                        ; -- End function
	.comm	_PLLE_BASE_LOCK_OVERRIDE,4,2    ; @PLLE_BASE_LOCK_OVERRIDE
	.comm	_PLLE_AUX,4,2                   ; @PLLE_AUX
	.comm	_PLLE_AUX_ENABLE_SWCTL,4,2      ; @PLLE_AUX_ENABLE_SWCTL
	.comm	_PLLE_AUX_SEQ_ENABLE,4,2        ; @PLLE_AUX_SEQ_ENABLE
	.comm	_PLLE_MISC_LOCK_ENABLE,4,2      ; @PLLE_MISC_LOCK_ENABLE
	.comm	_PLLE_MISC_IDDQ_SWCTL,4,2       ; @PLLE_MISC_IDDQ_SWCTL
	.comm	_PLLE_MISC_IDDQ_OVERRIDE_VALUE,4,2 ; @PLLE_MISC_IDDQ_OVERRIDE_VALUE
	.comm	_PLLE_MISC_PTS,4,2              ; @PLLE_MISC_PTS
	.comm	_PLLE_MISC_VREG_BG_CTRL_MASK,4,2 ; @PLLE_MISC_VREG_BG_CTRL_MASK
	.comm	_PLLE_MISC_VREG_CTRL_MASK,4,2   ; @PLLE_MISC_VREG_CTRL_MASK
	.comm	_PLLE_SS_CNTL,4,2               ; @PLLE_SS_CNTL
	.comm	_PLLE_SS_CNTL_DISABLE,4,2       ; @PLLE_SS_CNTL_DISABLE
	.comm	_PLLE_BASE_DIVCML_MASK,4,2      ; @PLLE_BASE_DIVCML_MASK
	.comm	_PLLE_BASE_DIVCML_SHIFT,4,2     ; @PLLE_BASE_DIVCML_SHIFT
	.comm	_PLLE_SS_CNTL_SSCCENTER,4,2     ; @PLLE_SS_CNTL_SSCCENTER
	.comm	_PLLE_SS_CNTL_SSCINVERT,4,2     ; @PLLE_SS_CNTL_SSCINVERT
	.comm	_PLLE_SS_CNTL_COEFFICIENTS_MASK,4,2 ; @PLLE_SS_CNTL_COEFFICIENTS_MASK
	.comm	_PLLE_SS_CNTL_COEFFICIENTS_VAL,4,2 ; @PLLE_SS_CNTL_COEFFICIENTS_VAL
	.comm	_PLLE_SS_CNTL_SSCBYP,4,2        ; @PLLE_SS_CNTL_SSCBYP
	.comm	_PLLE_SS_CNTL_BYPASS_SS,4,2     ; @PLLE_SS_CNTL_BYPASS_SS
	.comm	_PLLE_SS_CNTL_INTERP_RESET,4,2  ; @PLLE_SS_CNTL_INTERP_RESET
	.comm	_PLLE_AUX_USE_LOCKDET,4,2       ; @PLLE_AUX_USE_LOCKDET
	.comm	_PLLE_AUX_SEQ_START_STATE,4,2   ; @PLLE_AUX_SEQ_START_STATE
	.comm	_PLLE_AUX_SS_SWCTL,4,2          ; @PLLE_AUX_SS_SWCTL
	.comm	_XUSBIO_PLL_CFG0,4,2            ; @XUSBIO_PLL_CFG0
	.comm	_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET,4,2 ; @XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET
	.comm	_XUSBIO_PLL_CFG0_SEQ_START_STATE,4,2 ; @XUSBIO_PLL_CFG0_SEQ_START_STATE
	.comm	_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL,4,2 ; @XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL
	.comm	_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL,4,2 ; @XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL
	.comm	_XUSBIO_PLL_CFG0_SEQ_ENABLE,4,2 ; @XUSBIO_PLL_CFG0_SEQ_ENABLE
	.comm	_SATA_PLL_CFG0,4,2              ; @SATA_PLL_CFG0
	.comm	_SATA_PLL_CFG0_PADPLL_RESET_SWCTL,4,2 ; @SATA_PLL_CFG0_PADPLL_RESET_SWCTL
	.comm	_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE,4,2 ; @SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE
	.comm	_SATA_PLL_CFG0_PADPLL_USE_LOCKDET,4,2 ; @SATA_PLL_CFG0_PADPLL_USE_LOCKDET
	.comm	_SATA_PLL_CFG0_SEQ_IN_SWCTL,4,2 ; @SATA_PLL_CFG0_SEQ_IN_SWCTL
	.comm	_SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE,4,2 ; @SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE
	.comm	_SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE,4,2 ; @SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE
	.comm	_SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE,4,2 ; @SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE
	.comm	_SATA_PLL_CFG0_SEQ_ENABLE,4,2   ; @SATA_PLL_CFG0_SEQ_ENABLE
	.comm	_SATA_PLL_CFG0_SEQ_START_STATE,4,2 ; @SATA_PLL_CFG0_SEQ_START_STATE
	.comm	_PCIE_PLL_CFG0,4,2              ; @PCIE_PLL_CFG0
	.comm	_PCIE_PLL_CFG0_SEQ_ENABLE,4,2   ; @PCIE_PLL_CFG0_SEQ_ENABLE
	.no_dead_strip	_plle_enable
.subsections_via_symbols
