	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function atibl_pll_wreg
_atibl_pll_wreg:                        ## @atibl_pll_wreg
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r14d
	movl	%esi, %edx
	movq	%rdi, %rbx
	movl	(%rdi), %edi
	movq	_RADEON_CLOCK_CNTL_INDEX@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	andl	$63, %edx
	movq	_RADEON_PLL_WR_EN@GOTPCREL(%rip), %r13
	orl	(%r13), %edx
	callq	_bus_write_1
	movl	(%rbx), %edi
	movq	_RADEON_CLOCK_CNTL_DATA@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	callq	_bus_read_4
	movl	(%rbx), %edi
	movq	_RADEON_CRTC_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_bus_read_4
	movl	(%rbx), %edi
	movl	(%r12), %esi
	movl	%r14d, %edx
	callq	_bus_write_4
	movl	$5000, %edi                     ## imm = 0x1388
	callq	_DELAY
	movl	(%rbx), %edi
	movl	(%r15), %esi
	callq	_bus_read_4
	movl	%eax, %r14d
	movl	(%r13), %edx
	orl	$-64, %edx
	andl	%eax, %edx
	movl	(%rbx), %edi
	movl	(%r15), %esi
	callq	_bus_write_4
	movl	(%rbx), %edi
	movl	(%r12), %esi
	callq	_bus_read_4
	movl	(%rbx), %edi
	movl	(%r15), %esi
	movl	%r14d, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_bus_write_4                    ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_CLOCK_CNTL_INDEX,4,2    ## @RADEON_CLOCK_CNTL_INDEX
	.comm	_RADEON_PLL_WR_EN,4,2           ## @RADEON_PLL_WR_EN
	.comm	_RADEON_CLOCK_CNTL_DATA,4,2     ## @RADEON_CLOCK_CNTL_DATA
	.comm	_RADEON_CRTC_GEN_CNTL,4,2       ## @RADEON_CRTC_GEN_CNTL
	.no_dead_strip	_atibl_pll_wreg
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function atibl_pll_wreg
_atibl_pll_wreg:                        ; @atibl_pll_wreg
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x2
	mov	x19, x0
	ldr	w0, [x0]
Lloh0:
	adrp	x21, _RADEON_CLOCK_CNTL_INDEX@GOTPAGE
Lloh1:
	ldr	x21, [x21, _RADEON_CLOCK_CNTL_INDEX@GOTPAGEOFF]
	ldr	w8, [x21]
	and	w9, w1, #0x3f
Lloh2:
	adrp	x22, _RADEON_PLL_WR_EN@GOTPAGE
Lloh3:
	ldr	x22, [x22, _RADEON_PLL_WR_EN@GOTPAGEOFF]
	ldr	w10, [x22]
	orr	w2, w10, w9
	mov	x1, x8
	bl	_bus_write_1
	ldr	w0, [x19]
Lloh4:
	adrp	x23, _RADEON_CLOCK_CNTL_DATA@GOTPAGE
Lloh5:
	ldr	x23, [x23, _RADEON_CLOCK_CNTL_DATA@GOTPAGEOFF]
	ldr	w1, [x23]
	bl	_bus_read_4
	ldr	w0, [x19]
Lloh6:
	adrp	x8, _RADEON_CRTC_GEN_CNTL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_CRTC_GEN_CNTL@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	bl	_bus_read_4
	ldr	w0, [x19]
	ldr	w1, [x23]
	mov	x2, x20
	bl	_bus_write_4
	mov	w0, #5000
	bl	_DELAY
	ldr	w0, [x19]
	ldr	w1, [x21]
	bl	_bus_read_4
	mov	x20, x0
	ldr	w8, [x22]
	orr	w8, w8, #0xffffffc0
	and	w2, w8, w0
	ldr	w0, [x19]
	ldr	w1, [x21]
	bl	_bus_write_4
	ldr	w0, [x19]
	ldr	w1, [x23]
	bl	_bus_read_4
	ldr	w0, [x19]
	ldr	w1, [x21]
	mov	x2, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_bus_write_4
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_CLOCK_CNTL_INDEX,4,2    ; @RADEON_CLOCK_CNTL_INDEX
	.comm	_RADEON_PLL_WR_EN,4,2           ; @RADEON_PLL_WR_EN
	.comm	_RADEON_CLOCK_CNTL_DATA,4,2     ; @RADEON_CLOCK_CNTL_DATA
	.comm	_RADEON_CRTC_GEN_CNTL,4,2       ; @RADEON_CRTC_GEN_CNTL
	.no_dead_strip	_atibl_pll_wreg
.subsections_via_symbols
