	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function fsl_pcib_probe
_fsl_pcib_probe:                        ## @fsl_pcib_probe
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movl	%edi, %ebx
	callq	_ofw_bus_get_type
	movq	_ENXIO@GOTPCREL(%rip), %r14
	testq	%rax, %rax
	je	LBB0_9
## %bb.1:
	movl	%ebx, %edi
	callq	_ofw_bus_get_type
	leaq	L_.str(%rip), %rsi
	movq	%rax, %rdi
	callq	_strcmp
	testq	%rax, %rax
	jne	LBB0_9
## %bb.2:
	leaq	L_.str.1(%rip), %rsi
	movl	%ebx, %edi
	callq	_ofw_bus_is_compatible
	testq	%rax, %rax
	jne	LBB0_8
## %bb.3:
	leaq	L_.str.2(%rip), %rsi
	movl	%ebx, %edi
	callq	_ofw_bus_is_compatible
	testq	%rax, %rax
	jne	LBB0_8
## %bb.4:
	leaq	L_.str.3(%rip), %rsi
	movl	%ebx, %edi
	callq	_ofw_bus_is_compatible
	testq	%rax, %rax
	jne	LBB0_8
## %bb.5:
	leaq	L_.str.4(%rip), %rsi
	movl	%ebx, %edi
	callq	_ofw_bus_is_compatible
	testq	%rax, %rax
	jne	LBB0_8
## %bb.6:
	leaq	L_.str.5(%rip), %rsi
	movl	%ebx, %edi
	callq	_ofw_bus_is_compatible
	testq	%rax, %rax
	jne	LBB0_8
## %bb.7:
	leaq	L_.str.6(%rip), %rsi
	movl	%ebx, %edi
	callq	_ofw_bus_is_compatible
	testq	%rax, %rax
	je	LBB0_9
LBB0_8:
	leaq	L_.str.7(%rip), %rsi
	movl	%ebx, %edi
	callq	_device_set_desc
	movq	_BUS_PROBE_DEFAULT@GOTPCREL(%rip), %r14
LBB0_9:
	movl	(%r14), %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"pci"

	.comm	_ENXIO,4,2                      ## @ENXIO
L_.str.1:                               ## @.str.1
	.asciz	"fsl,mpc8540-pci"

L_.str.2:                               ## @.str.2
	.asciz	"fsl,mpc8540-pcie"

L_.str.3:                               ## @.str.3
	.asciz	"fsl,mpc8548-pcie"

L_.str.4:                               ## @.str.4
	.asciz	"fsl,p5020-pcie"

L_.str.5:                               ## @.str.5
	.asciz	"fsl,qoriq-pcie-v2.2"

L_.str.6:                               ## @.str.6
	.asciz	"fsl,qoriq-pcie"

L_.str.7:                               ## @.str.7
	.asciz	"Freescale Integrated PCI/PCI-E Controller"

	.comm	_BUS_PROBE_DEFAULT,4,2          ## @BUS_PROBE_DEFAULT
	.no_dead_strip	_fsl_pcib_probe
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function fsl_pcib_probe
_fsl_pcib_probe:                        ; @fsl_pcib_probe
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_ofw_bus_get_type
	cbz	x0, LBB0_2
; %bb.1:
	mov	x0, x19
	bl	_ofw_bus_get_type
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	bl	_strcmp
	cbz	x0, LBB0_3
LBB0_2:
Lloh2:
	adrp	x8, _ENXIO@GOTPAGE
Lloh3:
	ldr	x8, [x8, _ENXIO@GOTPAGEOFF]
	b	LBB0_10
LBB0_3:
Lloh4:
	adrp	x1, l_.str.1@PAGE
Lloh5:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x19
	bl	_ofw_bus_is_compatible
	cbnz	x0, LBB0_9
; %bb.4:
Lloh6:
	adrp	x1, l_.str.2@PAGE
Lloh7:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x0, x19
	bl	_ofw_bus_is_compatible
	cbnz	x0, LBB0_9
; %bb.5:
Lloh8:
	adrp	x1, l_.str.3@PAGE
Lloh9:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x0, x19
	bl	_ofw_bus_is_compatible
	cbnz	x0, LBB0_9
; %bb.6:
Lloh10:
	adrp	x1, l_.str.4@PAGE
Lloh11:
	add	x1, x1, l_.str.4@PAGEOFF
	mov	x0, x19
	bl	_ofw_bus_is_compatible
	cbnz	x0, LBB0_9
; %bb.7:
Lloh12:
	adrp	x1, l_.str.5@PAGE
Lloh13:
	add	x1, x1, l_.str.5@PAGEOFF
	mov	x0, x19
	bl	_ofw_bus_is_compatible
	cbnz	x0, LBB0_9
; %bb.8:
Lloh14:
	adrp	x1, l_.str.6@PAGE
Lloh15:
	add	x1, x1, l_.str.6@PAGEOFF
	mov	x0, x19
	bl	_ofw_bus_is_compatible
	cbz	x0, LBB0_2
LBB0_9:
Lloh16:
	adrp	x1, l_.str.7@PAGE
Lloh17:
	add	x1, x1, l_.str.7@PAGEOFF
	mov	x0, x19
	bl	_device_set_desc
Lloh18:
	adrp	x8, _BUS_PROBE_DEFAULT@GOTPAGE
Lloh19:
	ldr	x8, [x8, _BUS_PROBE_DEFAULT@GOTPAGEOFF]
LBB0_10:
	ldr	w0, [x8]
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpAdd	Lloh12, Lloh13
	.loh AdrpAdd	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpAdd	Lloh16, Lloh17
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"pci"

	.comm	_ENXIO,4,2                      ; @ENXIO
l_.str.1:                               ; @.str.1
	.asciz	"fsl,mpc8540-pci"

l_.str.2:                               ; @.str.2
	.asciz	"fsl,mpc8540-pcie"

l_.str.3:                               ; @.str.3
	.asciz	"fsl,mpc8548-pcie"

l_.str.4:                               ; @.str.4
	.asciz	"fsl,p5020-pcie"

l_.str.5:                               ; @.str.5
	.asciz	"fsl,qoriq-pcie-v2.2"

l_.str.6:                               ; @.str.6
	.asciz	"fsl,qoriq-pcie"

l_.str.7:                               ; @.str.7
	.asciz	"Freescale Integrated PCI/PCI-E Controller"

	.comm	_BUS_PROBE_DEFAULT,4,2          ; @BUS_PROBE_DEFAULT
	.no_dead_strip	_fsl_pcib_probe
.subsections_via_symbols
