	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function _mca_init
__mca_init:                             ## @_mca_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edi, %ebx
	movq	_cpu_id@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_CPUID_TO_FAMILY
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	_mca_enabled@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	je	LBB0_32
## %bb.1:
	movq	_cpu_feature@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_CPUID_MCE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_32
## %bb.2:
	movq	_CPUID_MCA@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_31
## %bb.3:
	testl	%ebx, %ebx
	je	LBB0_5
## %bb.4:
	movq	_cmci_mask@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PCPU_SET
LBB0_5:
	movq	_MSR_MCG_CAP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_rdmsr
	movl	%eax, %r12d
	movq	_MCG_CAP_CTL_P@GOTPCREL(%rip), %rax
	testl	%r12d, (%rax)
	je	LBB0_7
## %bb.6:
	movq	_MSR_MCG_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_MCG_CTL_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_wrmsr
LBB0_7:
	xorl	%eax, %eax
	callq	_IS_BSP
	testl	%ebx, %ebx
	je	LBB0_10
## %bb.8:
	testq	%rax, %rax
	je	LBB0_10
## %bb.9:
	movl	%r12d, %edi
	callq	_mca_setup
LBB0_10:
	movq	_cpu_vendor_id@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_CPU_VENDOR_AMD@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_15
## %bb.11:
	cmpl	$16, -44(%rbp)                  ## 4-byte Folded Reload
	jne	LBB0_15
## %bb.12:
	movq	_amd10h_L1TP@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	jne	LBB0_15
## %bb.13:
	movq	_MSR_MC0_CTL_MASK@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_rdmsr
	testb	$32, %al
	jne	LBB0_15
## %bb.14:
	movl	(%r14), %edi
	orl	$32, %eax
	movl	%eax, %esi
	callq	_wrmsr
LBB0_15:
	movq	_amd_rascap@GOTPCREL(%rip), %rax
	movq	_AMDRAS_SCALABLE_MCA@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, (%rax)
	je	LBB0_17
## %bb.16:
	movq	_mca_smca_ctl_reg@GOTPCREL(%rip), %rax
	movq	_mca_msr_ops@GOTPCREL(%rip), %rcx
	movq	%rax, 8(%rcx)
	movq	_mca_smca_status_reg@GOTPCREL(%rip), %rax
	movq	%rax, (%rcx)
	movq	_mca_smca_addr_reg@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 20(%rcx)
	movq	_mca_smca_misc_reg@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 16(%rcx)
LBB0_17:
	movl	%ebx, -48(%rbp)                 ## 4-byte Spill
	testl	%ebx, %ebx
	je	LBB0_19
## %bb.18:
	movq	_mca_lock@GOTPCREL(%rip), %rdi
	callq	_mtx_lock_spin
LBB0_19:
	movq	_MCG_CAP_COUNT@GOTPCREL(%rip), %r14
	testl	%r12d, (%r14)
	jle	LBB0_29
## %bb.20:
	xorl	%ebx, %ebx
	movq	_mca_msr_ops@GOTPCREL(%rip), %r15
	jmp	LBB0_21
	.p2align	4, 0x90
LBB0_27:                                ##   in Loop: Header=BB0_21 Depth=1
	movl	%ebx, %edi
	callq	*8(%r15)
	movl	%eax, %edi
	movl	%r13d, %esi
	callq	_wrmsr
LBB0_28:                                ##   in Loop: Header=BB0_21 Depth=1
	movl	%ebx, %edi
	callq	*(%r15)
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_wrmsr
	incl	%ebx
	movl	(%r14), %eax
	andl	%r12d, %eax
	cmpl	%eax, %ebx
	jge	LBB0_29
LBB0_21:                                ## =>This Inner Loop Header: Depth=1
	movq	_cpu_vendor_id@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_CPU_VENDOR_INTEL@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_25
## %bb.22:                              ##   in Loop: Header=BB0_21 Depth=1
	movl	$-1, %r13d
	testl	%ebx, %ebx
	jne	LBB0_27
## %bb.23:                              ##   in Loop: Header=BB0_21 Depth=1
	cmpl	$6, -44(%rbp)                   ## 4-byte Folded Reload
	jne	LBB0_27
## %bb.24:                              ##   in Loop: Header=BB0_21 Depth=1
	movq	_cpu_id@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_CPUID_TO_MODEL
	cmpl	$26, %eax
	jge	LBB0_27
	jmp	LBB0_28
	.p2align	4, 0x90
LBB0_25:                                ##   in Loop: Header=BB0_21 Depth=1
	movl	$-1, %r13d
	movq	_CPU_VENDOR_AMD@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_27
## %bb.26:                              ##   in Loop: Header=BB0_21 Depth=1
	movl	-44(%rbp), %ecx                 ## 4-byte Reload
	cmpl	$23, %ecx
	setge	%al
	cmpl	$15, %ecx
	setl	%cl
	movq	_MC_AMDNB_BANK@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %ebx
	setne	%dl
	orb	%al, %cl
	orb	%dl, %cl
	movzbl	%cl, %r13d
	shll	$10, %r13d
	orl	$-1025, %r13d                   ## imm = 0xFBFF
	jmp	LBB0_27
LBB0_32:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_29:
	cmpl	$0, -48(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_31
## %bb.30:
	movq	_mca_lock@GOTPCREL(%rip), %rdi
	callq	_mtx_unlock_spin
LBB0_31:
	xorl	%eax, %eax
	callq	_rcr4
	movq	_CR4_MCE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_load_cr4                       ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_cpu_id,4,2                     ## @cpu_id
	.comm	_mca_enabled,4,2                ## @mca_enabled
	.comm	_cpu_feature,4,2                ## @cpu_feature
	.comm	_CPUID_MCE,4,2                  ## @CPUID_MCE
	.comm	_CPUID_MCA,4,2                  ## @CPUID_MCA
	.comm	_cmci_mask,4,2                  ## @cmci_mask
	.comm	_MSR_MCG_CAP,4,2                ## @MSR_MCG_CAP
	.comm	_MCG_CAP_CTL_P,4,2              ## @MCG_CAP_CTL_P
	.comm	_MSR_MCG_CTL,4,2                ## @MSR_MCG_CTL
	.comm	_MCG_CTL_ENABLE,4,2             ## @MCG_CTL_ENABLE
	.comm	_cpu_vendor_id,8,3              ## @cpu_vendor_id
	.comm	_CPU_VENDOR_AMD,8,3             ## @CPU_VENDOR_AMD
	.comm	_amd10h_L1TP,4,2                ## @amd10h_L1TP
	.comm	_MSR_MC0_CTL_MASK,4,2           ## @MSR_MC0_CTL_MASK
	.comm	_amd_rascap,4,2                 ## @amd_rascap
	.comm	_AMDRAS_SCALABLE_MCA,4,2        ## @AMDRAS_SCALABLE_MCA
	.comm	_mca_msr_ops,24,3               ## @mca_msr_ops
	.comm	_mca_smca_addr_reg,4,2          ## @mca_smca_addr_reg
	.comm	_mca_smca_misc_reg,4,2          ## @mca_smca_misc_reg
	.comm	_mca_lock,4,2                   ## @mca_lock
	.comm	_MCG_CAP_COUNT,4,2              ## @MCG_CAP_COUNT
	.comm	_CPU_VENDOR_INTEL,8,3           ## @CPU_VENDOR_INTEL
	.comm	_MC_AMDNB_BANK,4,2              ## @MC_AMDNB_BANK
	.comm	_CR4_MCE,4,2                    ## @CR4_MCE
	.no_dead_strip	__mca_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function _mca_init
__mca_init:                             ; @_mca_init
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
Lloh0:
	adrp	x8, _cpu_id@GOTPAGE
Lloh1:
	ldr	x8, [x8, _cpu_id@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_CPUID_TO_FAMILY
Lloh3:
	adrp	x8, _mca_enabled@GOTPAGE
Lloh4:
	ldr	x8, [x8, _mca_enabled@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	cbz	w8, LBB0_28
; %bb.1:
Lloh6:
	adrp	x8, _cpu_feature@GOTPAGE
Lloh7:
	ldr	x8, [x8, _cpu_feature@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
Lloh9:
	adrp	x9, _CPUID_MCE@GOTPAGE
Lloh10:
	ldr	x9, [x9, _CPUID_MCE@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_28
; %bb.2:
Lloh12:
	adrp	x9, _CPUID_MCA@GOTPAGE
Lloh13:
	ldr	x9, [x9, _CPUID_MCA@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_31
; %bb.3:
	mov	x20, x0
	cbz	w19, LBB0_5
; %bb.4:
Lloh15:
	adrp	x8, _cmci_mask@GOTPAGE
Lloh16:
	ldr	x8, [x8, _cmci_mask@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PCPU_SET
LBB0_5:
Lloh18:
	adrp	x8, _MSR_MCG_CAP@GOTPAGE
Lloh19:
	ldr	x8, [x8, _MSR_MCG_CAP@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
	bl	_rdmsr
	mov	x21, x0
Lloh21:
	adrp	x8, _MCG_CAP_CTL_P@GOTPAGE
Lloh22:
	ldr	x8, [x8, _MCG_CAP_CTL_P@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_7
; %bb.6:
Lloh24:
	adrp	x8, _MSR_MCG_CTL@GOTPAGE
Lloh25:
	ldr	x8, [x8, _MSR_MCG_CTL@GOTPAGEOFF]
Lloh26:
	ldr	w0, [x8]
Lloh27:
	adrp	x8, _MCG_CTL_ENABLE@GOTPAGE
Lloh28:
	ldr	x8, [x8, _MCG_CTL_ENABLE@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	bl	_wrmsr
LBB0_7:
	bl	_IS_BSP
	cbz	w19, LBB0_10
; %bb.8:
	cbz	x0, LBB0_10
; %bb.9:
	mov	x0, x21
	bl	_mca_setup
LBB0_10:
Lloh30:
	adrp	x25, _cpu_vendor_id@GOTPAGE
Lloh31:
	ldr	x25, [x25, _cpu_vendor_id@GOTPAGEOFF]
	ldr	x8, [x25]
Lloh32:
	adrp	x26, _CPU_VENDOR_AMD@GOTPAGE
Lloh33:
	ldr	x26, [x26, _CPU_VENDOR_AMD@GOTPAGEOFF]
	ldr	x9, [x26]
Lloh34:
	adrp	x10, _amd10h_L1TP@GOTPAGE
Lloh35:
	ldr	x10, [x10, _amd10h_L1TP@GOTPAGEOFF]
Lloh36:
	ldr	w10, [x10]
	cmp	x8, x9
	ccmp	w20, #16, #0, eq
	ccmp	w10, #0, #0, eq
	b.ne	LBB0_13
; %bb.11:
Lloh37:
	adrp	x22, _MSR_MC0_CTL_MASK@GOTPAGE
Lloh38:
	ldr	x22, [x22, _MSR_MC0_CTL_MASK@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_rdmsr
	tbnz	w0, #5, LBB0_13
; %bb.12:
	ldr	w8, [x22]
	orr	w1, w0, #0x20
	mov	x0, x8
	bl	_wrmsr
LBB0_13:
Lloh39:
	adrp	x8, _amd_rascap@GOTPAGE
Lloh40:
	ldr	x8, [x8, _amd_rascap@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
Lloh42:
	adrp	x9, _AMDRAS_SCALABLE_MCA@GOTPAGE
Lloh43:
	ldr	x9, [x9, _AMDRAS_SCALABLE_MCA@GOTPAGEOFF]
Lloh44:
	ldr	w9, [x9]
Lloh45:
	adrp	x27, _mca_msr_ops@GOTPAGE
Lloh46:
	ldr	x27, [x27, _mca_msr_ops@GOTPAGEOFF]
	tst	w9, w8
	b.eq	LBB0_15
; %bb.14:
Lloh47:
	adrp	x8, _mca_smca_ctl_reg@GOTPAGE
Lloh48:
	ldr	x8, [x8, _mca_smca_ctl_reg@GOTPAGEOFF]
Lloh49:
	adrp	x9, _mca_smca_status_reg@GOTPAGE
Lloh50:
	ldr	x9, [x9, _mca_smca_status_reg@GOTPAGEOFF]
	stp	x9, x8, [x27]
Lloh51:
	adrp	x8, _mca_smca_addr_reg@GOTPAGE
Lloh52:
	ldr	x8, [x8, _mca_smca_addr_reg@GOTPAGEOFF]
Lloh53:
	ldr	w8, [x8]
Lloh54:
	adrp	x9, _mca_smca_misc_reg@GOTPAGE
Lloh55:
	ldr	x9, [x9, _mca_smca_misc_reg@GOTPAGEOFF]
Lloh56:
	ldr	w9, [x9]
	stp	w9, w8, [x27, #16]
LBB0_15:
	cbz	w19, LBB0_17
; %bb.16:
Lloh57:
	adrp	x0, _mca_lock@GOTPAGE
Lloh58:
	ldr	x0, [x0, _mca_lock@GOTPAGEOFF]
	bl	_mtx_lock_spin
LBB0_17:
Lloh59:
	adrp	x28, _MCG_CAP_COUNT@GOTPAGE
Lloh60:
	ldr	x28, [x28, _MCG_CAP_COUNT@GOTPAGEOFF]
	ldr	w8, [x28]
	and	w8, w8, w21
	cmp	w8, #1
	b.lt	LBB0_29
; %bb.18:
	mov	w22, #0
Lloh61:
	adrp	x24, _CPU_VENDOR_INTEL@GOTPAGE
Lloh62:
	ldr	x24, [x24, _CPU_VENDOR_INTEL@GOTPAGEOFF]
	b	LBB0_22
LBB0_19:                                ;   in Loop: Header=BB0_22 Depth=1
	mov	w23, #-1
LBB0_20:                                ;   in Loop: Header=BB0_22 Depth=1
	ldr	x8, [x27, #8]
	mov	x0, x22
	blr	x8
	mov	x1, x23
	bl	_wrmsr
LBB0_21:                                ;   in Loop: Header=BB0_22 Depth=1
	ldr	x8, [x27]
	mov	x0, x22
	blr	x8
	mov	w1, #0
	bl	_wrmsr
	add	w22, w22, #1
	ldr	w8, [x28]
	and	w8, w8, w21
	cmp	w22, w8
	b.ge	LBB0_29
LBB0_22:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x25]
	ldr	x9, [x24]
	cmp	x8, x9
	b.ne	LBB0_26
; %bb.23:                               ;   in Loop: Header=BB0_22 Depth=1
	mov	w23, #-1
	cbnz	w22, LBB0_20
; %bb.24:                               ;   in Loop: Header=BB0_22 Depth=1
	cmp	w20, #6
	b.ne	LBB0_20
; %bb.25:                               ;   in Loop: Header=BB0_22 Depth=1
Lloh63:
	adrp	x8, _cpu_id@GOTPAGE
Lloh64:
	ldr	x8, [x8, _cpu_id@GOTPAGEOFF]
Lloh65:
	ldr	w0, [x8]
	bl	_CPUID_TO_MODEL
	cmp	w0, #26
	b.ge	LBB0_19
	b	LBB0_21
LBB0_26:                                ;   in Loop: Header=BB0_22 Depth=1
	ldr	x9, [x26]
	cmp	x8, x9
	b.ne	LBB0_19
; %bb.27:                               ;   in Loop: Header=BB0_22 Depth=1
	cmp	w20, #23
	ccmp	w20, #14, #4, lt
Lloh66:
	adrp	x8, _MC_AMDNB_BANK@GOTPAGE
Lloh67:
	ldr	x8, [x8, _MC_AMDNB_BANK@GOTPAGEOFF]
Lloh68:
	ldr	w8, [x8]
	ccmp	w22, w8, #0, gt
	mov	w8, #-1025
	csinv	w23, w8, wzr, eq
	b	LBB0_20
LBB0_28:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
LBB0_29:
	cbz	w19, LBB0_31
; %bb.30:
Lloh69:
	adrp	x0, _mca_lock@GOTPAGE
Lloh70:
	ldr	x0, [x0, _mca_lock@GOTPAGEOFF]
	bl	_mtx_unlock_spin
LBB0_31:
	bl	_rcr4
Lloh71:
	adrp	x8, _CR4_MCE@GOTPAGE
Lloh72:
	ldr	x8, [x8, _CR4_MCE@GOTPAGEOFF]
Lloh73:
	ldr	w8, [x8]
	orr	w0, w8, w0
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_load_cr4
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpLdrGot	Lloh59, Lloh60
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGot	Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.cfi_endproc
                                        ; -- End function
	.comm	_cpu_id,4,2                     ; @cpu_id
	.comm	_mca_enabled,4,2                ; @mca_enabled
	.comm	_cpu_feature,4,2                ; @cpu_feature
	.comm	_CPUID_MCE,4,2                  ; @CPUID_MCE
	.comm	_CPUID_MCA,4,2                  ; @CPUID_MCA
	.comm	_cmci_mask,4,2                  ; @cmci_mask
	.comm	_MSR_MCG_CAP,4,2                ; @MSR_MCG_CAP
	.comm	_MCG_CAP_CTL_P,4,2              ; @MCG_CAP_CTL_P
	.comm	_MSR_MCG_CTL,4,2                ; @MSR_MCG_CTL
	.comm	_MCG_CTL_ENABLE,4,2             ; @MCG_CTL_ENABLE
	.comm	_cpu_vendor_id,8,3              ; @cpu_vendor_id
	.comm	_CPU_VENDOR_AMD,8,3             ; @CPU_VENDOR_AMD
	.comm	_amd10h_L1TP,4,2                ; @amd10h_L1TP
	.comm	_MSR_MC0_CTL_MASK,4,2           ; @MSR_MC0_CTL_MASK
	.comm	_amd_rascap,4,2                 ; @amd_rascap
	.comm	_AMDRAS_SCALABLE_MCA,4,2        ; @AMDRAS_SCALABLE_MCA
	.comm	_mca_msr_ops,24,3               ; @mca_msr_ops
	.comm	_mca_smca_addr_reg,4,2          ; @mca_smca_addr_reg
	.comm	_mca_smca_misc_reg,4,2          ; @mca_smca_misc_reg
	.comm	_mca_lock,4,2                   ; @mca_lock
	.comm	_MCG_CAP_COUNT,4,2              ; @MCG_CAP_COUNT
	.comm	_CPU_VENDOR_INTEL,8,3           ; @CPU_VENDOR_INTEL
	.comm	_MC_AMDNB_BANK,4,2              ; @MC_AMDNB_BANK
	.comm	_CR4_MCE,4,2                    ; @CR4_MCE
	.no_dead_strip	__mca_init
.subsections_via_symbols
