	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function xlp_pcib_hardware_swap_enable
_xlp_pcib_hardware_swap_enable:         ## @xlp_pcib_hardware_swap_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r12d
	movl	%edi, %r14d
	callq	_XLP_IO_PCIE_OFFSET
	movl	%eax, %ebx
	movl	%eax, %edi
	callq	_nlm_dev_exists
	testl	%eax, %eax
	je	LBB0_1
## %bb.2:
	movl	%r14d, %edi
	callq	_nlm_get_bridge_regbase
	movl	%eax, %r15d
	movl	%ebx, %edi
	callq	_nlm_pcicfg_base
	movl	%eax, %r14d
	movq	_BRIDGE_PCIEMEM_BASE0@GOTPCREL(%rip), %rax
	movslq	%r12d, %rbx
	movq	(%rax), %rsi
	addq	%rbx, %rsi
	movl	%r15d, %edi
	callq	_nlm_read_bridge_reg
	movq	_PCIE_BYTE_SWAP_MEM_BASE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%r14d, %edi
	movl	%eax, %edx
	callq	_nlm_write_pci_reg
	movq	_BRIDGE_PCIEMEM_LIMIT0@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	%rbx, %rsi
	movl	%r15d, %edi
	callq	_nlm_read_bridge_reg
	movq	_PCIE_BYTE_SWAP_MEM_LIM@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	$4095, %eax                     ## imm = 0xFFF
	movl	%r14d, %edi
	movl	%eax, %edx
	callq	_nlm_write_pci_reg
	movq	_BRIDGE_PCIEIO_BASE0@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	%rbx, %rsi
	movl	%r15d, %edi
	callq	_nlm_read_bridge_reg
	movq	_PCIE_BYTE_SWAP_IO_BASE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%r14d, %edi
	movl	%eax, %edx
	callq	_nlm_write_pci_reg
	movq	_BRIDGE_PCIEIO_LIMIT0@GOTPCREL(%rip), %rax
	addq	(%rax), %rbx
	movl	%r15d, %edi
	movq	%rbx, %rsi
	callq	_nlm_read_bridge_reg
	movq	_PCIE_BYTE_SWAP_IO_LIM@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	$4095, %eax                     ## imm = 0xFFF
	movl	%r14d, %edi
	movl	%eax, %edx
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_nlm_write_pci_reg              ## TAILCALL
LBB0_1:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_BRIDGE_PCIEMEM_BASE0,8,3       ## @BRIDGE_PCIEMEM_BASE0
	.comm	_PCIE_BYTE_SWAP_MEM_BASE,4,2    ## @PCIE_BYTE_SWAP_MEM_BASE
	.comm	_BRIDGE_PCIEMEM_LIMIT0,8,3      ## @BRIDGE_PCIEMEM_LIMIT0
	.comm	_PCIE_BYTE_SWAP_MEM_LIM,4,2     ## @PCIE_BYTE_SWAP_MEM_LIM
	.comm	_BRIDGE_PCIEIO_BASE0,8,3        ## @BRIDGE_PCIEIO_BASE0
	.comm	_PCIE_BYTE_SWAP_IO_BASE,4,2     ## @PCIE_BYTE_SWAP_IO_BASE
	.comm	_BRIDGE_PCIEIO_LIMIT0,8,3       ## @BRIDGE_PCIEIO_LIMIT0
	.comm	_PCIE_BYTE_SWAP_IO_LIM,4,2      ## @PCIE_BYTE_SWAP_IO_LIM
	.no_dead_strip	_xlp_pcib_hardware_swap_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function xlp_pcib_hardware_swap_enable
_xlp_pcib_hardware_swap_enable:         ; @xlp_pcib_hardware_swap_enable
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x21, x1
	mov	x19, x0
	bl	_XLP_IO_PCIE_OFFSET
	mov	x22, x0
	bl	_nlm_dev_exists
	cbz	w0, LBB0_2
; %bb.1:
	mov	x0, x19
	bl	_nlm_get_bridge_regbase
	mov	x20, x0
	mov	x0, x22
	bl	_nlm_pcicfg_base
	mov	x19, x0
Lloh0:
	adrp	x8, _BRIDGE_PCIEMEM_BASE0@GOTPAGE
Lloh1:
	ldr	x8, [x8, _BRIDGE_PCIEMEM_BASE0@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	sxtw	x21, w21
	add	x1, x8, x21
	mov	x0, x20
	bl	_nlm_read_bridge_reg
	mov	x2, x0
Lloh3:
	adrp	x8, _PCIE_BYTE_SWAP_MEM_BASE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCIE_BYTE_SWAP_MEM_BASE@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_nlm_write_pci_reg
Lloh6:
	adrp	x8, _BRIDGE_PCIEMEM_LIMIT0@GOTPAGE
Lloh7:
	ldr	x8, [x8, _BRIDGE_PCIEMEM_LIMIT0@GOTPAGEOFF]
Lloh8:
	ldr	x8, [x8]
	add	x1, x8, x21
	mov	x0, x20
	bl	_nlm_read_bridge_reg
Lloh9:
	adrp	x8, _PCIE_BYTE_SWAP_MEM_LIM@GOTPAGE
Lloh10:
	ldr	x8, [x8, _PCIE_BYTE_SWAP_MEM_LIM@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	orr	w2, w0, #0xfff
	mov	x0, x19
	bl	_nlm_write_pci_reg
Lloh12:
	adrp	x8, _BRIDGE_PCIEIO_BASE0@GOTPAGE
Lloh13:
	ldr	x8, [x8, _BRIDGE_PCIEIO_BASE0@GOTPAGEOFF]
Lloh14:
	ldr	x8, [x8]
	add	x1, x8, x21
	mov	x0, x20
	bl	_nlm_read_bridge_reg
	mov	x2, x0
Lloh15:
	adrp	x8, _PCIE_BYTE_SWAP_IO_BASE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _PCIE_BYTE_SWAP_IO_BASE@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_nlm_write_pci_reg
Lloh18:
	adrp	x8, _BRIDGE_PCIEIO_LIMIT0@GOTPAGE
Lloh19:
	ldr	x8, [x8, _BRIDGE_PCIEIO_LIMIT0@GOTPAGEOFF]
Lloh20:
	ldr	x8, [x8]
	add	x1, x8, x21
	mov	x0, x20
	bl	_nlm_read_bridge_reg
Lloh21:
	adrp	x8, _PCIE_BYTE_SWAP_IO_LIM@GOTPAGE
Lloh22:
	ldr	x8, [x8, _PCIE_BYTE_SWAP_IO_LIM@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	orr	w2, w0, #0xfff
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_nlm_write_pci_reg
LBB0_2:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_BRIDGE_PCIEMEM_BASE0,8,3       ; @BRIDGE_PCIEMEM_BASE0
	.comm	_PCIE_BYTE_SWAP_MEM_BASE,4,2    ; @PCIE_BYTE_SWAP_MEM_BASE
	.comm	_BRIDGE_PCIEMEM_LIMIT0,8,3      ; @BRIDGE_PCIEMEM_LIMIT0
	.comm	_PCIE_BYTE_SWAP_MEM_LIM,4,2     ; @PCIE_BYTE_SWAP_MEM_LIM
	.comm	_BRIDGE_PCIEIO_BASE0,8,3        ; @BRIDGE_PCIEIO_BASE0
	.comm	_PCIE_BYTE_SWAP_IO_BASE,4,2     ; @PCIE_BYTE_SWAP_IO_BASE
	.comm	_BRIDGE_PCIEIO_LIMIT0,8,3       ; @BRIDGE_PCIEIO_LIMIT0
	.comm	_PCIE_BYTE_SWAP_IO_LIM,4,2      ; @PCIE_BYTE_SWAP_IO_LIM
	.no_dead_strip	_xlp_pcib_hardware_swap_enable
.subsections_via_symbols
