	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function print_AMD_info
_print_AMD_info:                        ## @print_AMD_info
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -32(%rbp)
	movq	_cpu_exthigh@GOTPCREL(%rip), %r15
	cmpl	$-2147483643, (%r15)            ## imm = 0x80000005
	jb	LBB0_9
## %bb.1:
	leaq	-48(%rbp), %rsi
	movl	$-2147483643, %edi              ## imm = 0x80000005
	callq	_do_cpuid
	movzbl	-46(%rbp), %esi
	leaq	L_.str(%rip), %rdi
	xorl	%eax, %eax
	callq	_printf
	movsbl	-45(%rbp), %edi
	callq	_print_AMD_assoc
	movzbl	-48(%rbp), %esi
	leaq	L_.str.1(%rip), %rdi
	xorl	%eax, %eax
	callq	_printf
	movzbl	-47(%rbp), %edi
	callq	_print_AMD_assoc
	movzbl	-42(%rbp), %esi
	leaq	L_.str.2(%rip), %rdi
	xorl	%eax, %eax
	callq	_printf
	movsbl	-41(%rbp), %edi
	callq	_print_AMD_assoc
	movzbl	-44(%rbp), %esi
	leaq	L_.str.3(%rip), %rdi
	xorl	%eax, %eax
	callq	_printf
	movzbl	-43(%rbp), %edi
	callq	_print_AMD_assoc
	movsbl	-37(%rbp), %esi
	leaq	L_.str.4(%rip), %rdi
	xorl	%eax, %eax
	callq	_printf
	movzbl	-40(%rbp), %esi
	leaq	L_.str.5(%rip), %r14
	movq	%r14, %rdi
	xorl	%eax, %eax
	callq	_printf
	movzbl	-39(%rbp), %esi
	leaq	L_.str.6(%rip), %rbx
	movq	%rbx, %rdi
	xorl	%eax, %eax
	callq	_printf
	movzbl	-38(%rbp), %edi
	callq	_print_AMD_assoc
	movsbl	-33(%rbp), %esi
	leaq	L_.str.7(%rip), %rdi
	xorl	%eax, %eax
	callq	_printf
	movzbl	-36(%rbp), %esi
	movq	%r14, %rdi
	xorl	%eax, %eax
	callq	_printf
	movzbl	-35(%rbp), %esi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	callq	_printf
	movzbl	-34(%rbp), %edi
	callq	_print_AMD_assoc
	cmpl	$-2147483642, (%r15)            ## imm = 0x80000006
	jb	LBB0_9
## %bb.2:
	leaq	-48(%rbp), %rsi
	movl	$-2147483642, %edi              ## imm = 0x80000006
	callq	_do_cpuid
	movl	-48(%rbp), %esi
	cmpl	$65536, %esi                    ## imm = 0x10000
	jae	LBB0_3
## %bb.4:
	andl	$4095, %esi                     ## imm = 0xFFF
	leaq	L_.str.10(%rip), %rdi
	jmp	LBB0_5
LBB0_3:
	shrl	$16, %esi
	andl	$4095, %esi                     ## imm = 0xFFF
	leaq	L_.str.8(%rip), %rdi
	xorl	%eax, %eax
	callq	_printf
	movl	-48(%rbp), %edi
	sarl	$28, %edi
	callq	_print_AMD_l2_assoc
	movl	$4095, %esi                     ## imm = 0xFFF
	andl	-48(%rbp), %esi
	leaq	L_.str.9(%rip), %rdi
LBB0_5:
	xorl	%eax, %eax
	callq	_printf
	movl	-48(%rbp), %edi
	shrl	$28, %edi
	callq	_print_AMD_l2_assoc
	movl	-44(%rbp), %esi
	cmpl	$65536, %esi                    ## imm = 0x10000
	jae	LBB0_6
## %bb.7:
	leaq	L_.str.13(%rip), %rdi
	xorl	%esi, %esi
	jmp	LBB0_8
LBB0_6:
	shrl	$16, %esi
	andl	$4095, %esi                     ## imm = 0xFFF
	leaq	L_.str.11(%rip), %rdi
	xorl	%eax, %eax
	callq	_printf
	movl	-44(%rbp), %edi
	sarl	$28, %edi
	callq	_print_AMD_l2_assoc
	movzwl	-42(%rbp), %esi
	andl	$4095, %esi                     ## imm = 0xFFF
	leaq	L_.str.12(%rip), %rdi
LBB0_8:
	xorl	%eax, %eax
	callq	_printf
	movl	-44(%rbp), %edi
	shrl	$28, %edi
	callq	_print_AMD_l2_assoc
	movswl	-38(%rbp), %esi
	leaq	L_.str.14(%rip), %rdi
	xorl	%eax, %eax
	callq	_printf
	movzbl	-40(%rbp), %esi
	leaq	L_.str.5(%rip), %rdi
	xorl	%eax, %eax
	callq	_printf
	movl	-40(%rbp), %esi
	shrl	$8, %esi
	andl	$15, %esi
	leaq	L_.str.6(%rip), %rdi
	xorl	%eax, %eax
	callq	_printf
	movl	-40(%rbp), %edi
	shrl	$12, %edi
	andl	$15, %edi
	callq	_print_AMD_l2_assoc
LBB0_9:
	movq	_cpu_id@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_CPUID_TO_FAMILY
	cmpl	$15, %eax
	jne	LBB0_13
## %bb.10:
	movl	(%rbx), %edi
	callq	_CPUID_TO_MODEL
	cmpl	$32, %eax
	jl	LBB0_13
## %bb.11:
	movl	(%rbx), %edi
	callq	_CPUID_TO_MODEL
	cmpl	$63, %eax
	jg	LBB0_13
## %bb.12:
	leaq	L_str(%rip), %rdi
	callq	_puts
LBB0_13:
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	cmpq	-32(%rbp), %rax
	jne	LBB0_15
## %bb.14:
	addq	$24, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_15:
	callq	___stack_chk_fail
	.cfi_endproc
                                        ## -- End function
	.comm	_cpu_exthigh,4,2                ## @cpu_exthigh
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"L1 2MB data TLB: %d entries"

L_.str.1:                               ## @.str.1
	.asciz	"L1 2MB instruction TLB: %d entries"

L_.str.2:                               ## @.str.2
	.asciz	"L1 4KB data TLB: %d entries"

L_.str.3:                               ## @.str.3
	.asciz	"L1 4KB instruction TLB: %d entries"

L_.str.4:                               ## @.str.4
	.asciz	"L1 data cache: %d kbytes"

L_.str.5:                               ## @.str.5
	.asciz	", %d bytes/line"

L_.str.6:                               ## @.str.6
	.asciz	", %d lines/tag"

L_.str.7:                               ## @.str.7
	.asciz	"L1 instruction cache: %d kbytes"

L_.str.8:                               ## @.str.8
	.asciz	"L2 2MB data TLB: %d entries"

L_.str.9:                               ## @.str.9
	.asciz	"L2 2MB instruction TLB: %d entries"

L_.str.10:                              ## @.str.10
	.asciz	"L2 2MB unified TLB: %d entries"

L_.str.11:                              ## @.str.11
	.asciz	"L2 4KB data TLB: %d entries"

L_.str.12:                              ## @.str.12
	.asciz	"L2 4KB instruction TLB: %d entries"

L_.str.13:                              ## @.str.13
	.asciz	"L2 4KB unified TLB: %d entries"

L_.str.14:                              ## @.str.14
	.asciz	"L2 unified cache: %d kbytes"

	.comm	_cpu_id,4,2                     ## @cpu_id
L_str:                                  ## @str
	.asciz	"WARNING: This architecture revision has known SMP hardware bugs which may cause random instability"

	.no_dead_strip	_print_AMD_info
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function print_AMD_info
_print_AMD_info:                        ; @print_AMD_info
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
Lloh0:
	adrp	x8, ___stack_chk_guard@GOTPAGE
Lloh1:
	ldr	x8, [x8, ___stack_chk_guard@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	str	x8, [sp, #24]
	mov	w21, #5
	movk	w21, #32768, lsl #16
Lloh3:
	adrp	x22, _cpu_exthigh@GOTPAGE
Lloh4:
	ldr	x22, [x22, _cpu_exthigh@GOTPAGEOFF]
	ldr	w8, [x22]
	sub	w9, w21, #1
	cmp	w8, w9
	b.ls	LBB0_9
; %bb.1:
	add	x1, sp, #8
	mov	w0, #5
	movk	w0, #32768, lsl #16
	bl	_do_cpuid
	ldrb	w8, [sp, #10]
	str	x8, [sp]
Lloh5:
	adrp	x0, l_.str@PAGE
Lloh6:
	add	x0, x0, l_.str@PAGEOFF
	bl	_printf
	ldrsb	w0, [sp, #11]
	bl	_print_AMD_assoc
	ldrb	w8, [sp, #8]
	str	x8, [sp]
Lloh7:
	adrp	x0, l_.str.1@PAGE
Lloh8:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_printf
	ldrb	w0, [sp, #9]
	bl	_print_AMD_assoc
	ldrb	w8, [sp, #14]
	str	x8, [sp]
Lloh9:
	adrp	x0, l_.str.2@PAGE
Lloh10:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	_printf
	ldrsb	w0, [sp, #15]
	bl	_print_AMD_assoc
	ldrb	w8, [sp, #12]
	str	x8, [sp]
Lloh11:
	adrp	x0, l_.str.3@PAGE
Lloh12:
	add	x0, x0, l_.str.3@PAGEOFF
	bl	_printf
	ldrb	w0, [sp, #13]
	bl	_print_AMD_assoc
	ldrsb	x8, [sp, #19]
	str	x8, [sp]
Lloh13:
	adrp	x0, l_.str.4@PAGE
Lloh14:
	add	x0, x0, l_.str.4@PAGEOFF
	bl	_printf
	ldrb	w8, [sp, #16]
	str	x8, [sp]
Lloh15:
	adrp	x19, l_.str.5@PAGE
Lloh16:
	add	x19, x19, l_.str.5@PAGEOFF
	mov	x0, x19
	bl	_printf
	ldrb	w8, [sp, #17]
	str	x8, [sp]
Lloh17:
	adrp	x20, l_.str.6@PAGE
Lloh18:
	add	x20, x20, l_.str.6@PAGEOFF
	mov	x0, x20
	bl	_printf
	ldrb	w0, [sp, #18]
	bl	_print_AMD_assoc
	ldrsb	x8, [sp, #23]
	str	x8, [sp]
Lloh19:
	adrp	x0, l_.str.7@PAGE
Lloh20:
	add	x0, x0, l_.str.7@PAGEOFF
	bl	_printf
	ldrb	w8, [sp, #20]
	str	x8, [sp]
	mov	x0, x19
	bl	_printf
	ldrb	w8, [sp, #21]
	str	x8, [sp]
	mov	x0, x20
	bl	_printf
	ldrb	w0, [sp, #22]
	bl	_print_AMD_assoc
	ldr	w8, [x22]
	cmp	w8, w21
	b.ls	LBB0_9
; %bb.2:
	add	w0, w21, #1
	add	x1, sp, #8
	bl	_do_cpuid
	ldr	w8, [sp, #8]
	cmp	w8, #16, lsl #12                ; =65536
	b.hs	LBB0_4
; %bb.3:
	and	w8, w8, #0xfff
	str	x8, [sp]
Lloh21:
	adrp	x0, l_.str.10@PAGE
Lloh22:
	add	x0, x0, l_.str.10@PAGEOFF
	b	LBB0_5
LBB0_4:
	ubfx	w8, w8, #16, #12
	str	x8, [sp]
Lloh23:
	adrp	x0, l_.str.8@PAGE
Lloh24:
	add	x0, x0, l_.str.8@PAGEOFF
	bl	_printf
	ldr	w8, [sp, #8]
	asr	w0, w8, #28
	bl	_print_AMD_l2_assoc
	ldr	w8, [sp, #8]
	and	w8, w8, #0xfff
	str	x8, [sp]
Lloh25:
	adrp	x0, l_.str.9@PAGE
Lloh26:
	add	x0, x0, l_.str.9@PAGEOFF
LBB0_5:
	bl	_printf
	ldr	w8, [sp, #8]
	lsr	w0, w8, #28
	bl	_print_AMD_l2_assoc
	ldr	w8, [sp, #12]
	cmp	w8, #16, lsl #12                ; =65536
	b.hs	LBB0_7
; %bb.6:
	str	xzr, [sp]
Lloh27:
	adrp	x0, l_.str.13@PAGE
Lloh28:
	add	x0, x0, l_.str.13@PAGEOFF
	b	LBB0_8
LBB0_7:
	ubfx	w8, w8, #16, #12
	str	x8, [sp]
Lloh29:
	adrp	x0, l_.str.11@PAGE
Lloh30:
	add	x0, x0, l_.str.11@PAGEOFF
	bl	_printf
	ldr	w8, [sp, #12]
	asr	w0, w8, #28
	bl	_print_AMD_l2_assoc
	ldrh	w8, [sp, #14]
	and	w8, w8, #0xfff
	str	x8, [sp]
Lloh31:
	adrp	x0, l_.str.12@PAGE
Lloh32:
	add	x0, x0, l_.str.12@PAGEOFF
LBB0_8:
	bl	_printf
	ldr	w8, [sp, #12]
	lsr	w0, w8, #28
	bl	_print_AMD_l2_assoc
	ldrsh	x8, [sp, #18]
	str	x8, [sp]
Lloh33:
	adrp	x0, l_.str.14@PAGE
Lloh34:
	add	x0, x0, l_.str.14@PAGEOFF
	bl	_printf
	ldrb	w8, [sp, #16]
	str	x8, [sp]
Lloh35:
	adrp	x0, l_.str.5@PAGE
Lloh36:
	add	x0, x0, l_.str.5@PAGEOFF
	bl	_printf
	ldr	w8, [sp, #16]
	ubfx	w8, w8, #8, #4
	str	x8, [sp]
Lloh37:
	adrp	x0, l_.str.6@PAGE
Lloh38:
	add	x0, x0, l_.str.6@PAGEOFF
	bl	_printf
	ldr	w8, [sp, #16]
	ubfx	w0, w8, #12, #4
	bl	_print_AMD_l2_assoc
LBB0_9:
Lloh39:
	adrp	x19, _cpu_id@GOTPAGE
Lloh40:
	ldr	x19, [x19, _cpu_id@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_CPUID_TO_FAMILY
	cmp	w0, #15
	b.ne	LBB0_13
; %bb.10:
	ldr	w0, [x19]
	bl	_CPUID_TO_MODEL
	cmp	w0, #32
	b.lt	LBB0_13
; %bb.11:
	ldr	w0, [x19]
	bl	_CPUID_TO_MODEL
	cmp	w0, #63
	b.gt	LBB0_13
; %bb.12:
Lloh41:
	adrp	x0, l_str@PAGE
Lloh42:
	add	x0, x0, l_str@PAGEOFF
	bl	_puts
LBB0_13:
	ldr	x8, [sp, #24]
Lloh43:
	adrp	x9, ___stack_chk_guard@GOTPAGE
Lloh44:
	ldr	x9, [x9, ___stack_chk_guard@GOTPAGEOFF]
Lloh45:
	ldr	x9, [x9]
	cmp	x9, x8
	b.ne	LBB0_15
; %bb.14:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
LBB0_15:
	bl	___stack_chk_fail
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh19, Lloh20
	.loh AdrpAdd	Lloh17, Lloh18
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpAdd	Lloh13, Lloh14
	.loh AdrpAdd	Lloh11, Lloh12
	.loh AdrpAdd	Lloh9, Lloh10
	.loh AdrpAdd	Lloh7, Lloh8
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpAdd	Lloh21, Lloh22
	.loh AdrpAdd	Lloh25, Lloh26
	.loh AdrpAdd	Lloh23, Lloh24
	.loh AdrpAdd	Lloh27, Lloh28
	.loh AdrpAdd	Lloh31, Lloh32
	.loh AdrpAdd	Lloh29, Lloh30
	.loh AdrpAdd	Lloh37, Lloh38
	.loh AdrpAdd	Lloh35, Lloh36
	.loh AdrpAdd	Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpAdd	Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.cfi_endproc
                                        ; -- End function
	.comm	_cpu_exthigh,4,2                ; @cpu_exthigh
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"L1 2MB data TLB: %d entries"

l_.str.1:                               ; @.str.1
	.asciz	"L1 2MB instruction TLB: %d entries"

l_.str.2:                               ; @.str.2
	.asciz	"L1 4KB data TLB: %d entries"

l_.str.3:                               ; @.str.3
	.asciz	"L1 4KB instruction TLB: %d entries"

l_.str.4:                               ; @.str.4
	.asciz	"L1 data cache: %d kbytes"

l_.str.5:                               ; @.str.5
	.asciz	", %d bytes/line"

l_.str.6:                               ; @.str.6
	.asciz	", %d lines/tag"

l_.str.7:                               ; @.str.7
	.asciz	"L1 instruction cache: %d kbytes"

l_.str.8:                               ; @.str.8
	.asciz	"L2 2MB data TLB: %d entries"

l_.str.9:                               ; @.str.9
	.asciz	"L2 2MB instruction TLB: %d entries"

l_.str.10:                              ; @.str.10
	.asciz	"L2 2MB unified TLB: %d entries"

l_.str.11:                              ; @.str.11
	.asciz	"L2 4KB data TLB: %d entries"

l_.str.12:                              ; @.str.12
	.asciz	"L2 4KB instruction TLB: %d entries"

l_.str.13:                              ; @.str.13
	.asciz	"L2 4KB unified TLB: %d entries"

l_.str.14:                              ; @.str.14
	.asciz	"L2 unified cache: %d kbytes"

	.comm	_cpu_id,4,2                     ; @cpu_id
l_str:                                  ; @str
	.asciz	"WARNING: This architecture revision has known SMP hardware bugs which may cause random instability"

	.no_dead_strip	_print_AMD_info
.subsections_via_symbols
