	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_fpu_sqrt                       ## -- Begin function fpu_sqrt
	.p2align	4, 0x90
_fpu_sqrt:                              ## @fpu_sqrt
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	leaq	8(%rdi), %rbx
	movq	_FPE_REG@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	leaq	L_.str(%rip), %rsi
	callq	_DPRINTF
	movl	(%r15), %edi
	movq	%rbx, %rsi
	callq	_DUMPFPN
	movl	(%r15), %edi
	leaq	L_.str.1(%rip), %rsi
	callq	_DPRINTF
	movq	%rbx, %rdi
	callq	_ISNAN
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	_FPSCR_VXSNAN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r14)
	jmp	LBB0_4
LBB0_2:
	movq	%rbx, %rdi
	callq	_ISZERO
	testq	%rax, %rax
	je	LBB0_5
## %bb.3:
	movq	_FPSCR_ZX@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r14)
	movq	_FPC_INF@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 32(%r14)
LBB0_4:
	movl	(%r15), %edi
	movq	%rbx, %rsi
	callq	_DUMPFPN
	movq	%rbx, %rax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_5:
	cmpq	$0, 24(%r14)
	je	LBB0_6
## %bb.15:
	movq	_FPSCR_VXSQRT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r14)
	movq	%r14, %rdi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_fpu_newnan                     ## TAILCALL
LBB0_6:
	movq	%rbx, %rdi
	callq	_ISINF
	testq	%rax, %rax
	jne	LBB0_4
## %bb.7:
	movq	8(%r14), %r8
	movl	(%r8), %edx
	movl	4(%r8), %ecx
	movl	8(%r8), %eax
	movl	12(%r8), %r13d
	movl	16(%r14), %esi
	testb	$1, %sil
	je	LBB0_9
## %bb.8:
	addl	%edx, %edx
	movl	%ecx, %edi
	sarl	$31, %edi
	orl	%edi, %edx
	addl	%ecx, %ecx
	movl	%eax, %edi
	sarl	$31, %edi
	orl	%edi, %ecx
	addl	%eax, %eax
	movl	%r13d, %edi
	sarl	$31, %edi
	orl	%edi, %eax
	addl	%r13d, %r13d
LBB0_9:
	sarl	%esi
	movl	%esi, 16(%r14)
	movq	_FP_1@GOTPCREL(%rip), %rsi
	movl	(%rsi), %r10d
	addl	%edx, %edx
	movl	%ecx, %esi
	sarl	$31, %esi
	orl	%edx, %esi
	addl	%ecx, %ecx
	movl	%eax, %edx
	sarl	$31, %edx
	orl	%ecx, %edx
	addl	%eax, %eax
	movl	%r13d, %r14d
	sarl	$31, %r14d
	orl	%eax, %r14d
	subl	%r10d, %esi
	leal	(%r10,%r10), %r15d
	leal	(%r13,%r13), %r12d
	cmpl	$2, %r10d
	jae	LBB0_11
## %bb.10:
	movl	%esi, %edi
	jmp	LBB0_13
LBB0_11:
	xorl	%r9d, %r9d
	movl	%r10d, %r11d
	movl	%r10d, %ecx
	.p2align	4, 0x90
LBB0_12:                                ## =>This Inner Loop Header: Depth=1
	movl	%r12d, %r13d
	sarl	%ecx
	addl	%esi, %esi
	movl	%edx, %edi
	sarl	$31, %edi
	orl	%esi, %edi
	addl	%edx, %edx
	movl	%r14d, %esi
	sarl	$31, %esi
	orl	%esi, %edx
	addl	%r14d, %r14d
	movl	%r12d, %esi
	sarl	$31, %esi
	orl	%esi, %r14d
	movl	%r15d, %esi
	orl	%ecx, %esi
	movl	%r11d, %ebx
	andl	$-2, %ebx
	cmpl	%esi, %edi
	movl	%ecx, %eax
	cmovll	%r9d, %eax
	cmovll	%r9d, %esi
	cmovll	%r9d, %ebx
	orl	%eax, %r10d
	subl	%esi, %edi
	orl	%ebx, %r15d
	leal	(%r13,%r13), %r12d
	movl	%edi, %esi
	cmpl	$3, %r11d
	movl	%ecx, %r11d
	ja	LBB0_12
LBB0_13:
	movl	%r10d, (%r8)
	addl	%edi, %edi
	movl	%r15d, %ebx
	movl	%edx, %r15d
	sarl	$31, %r15d
	orl	%edi, %r15d
	addl	%edx, %edx
	movl	%r14d, %esi
	sarl	$31, %esi
	orl	%edx, %esi
	addl	%r14d, %r14d
	sarl	$31, %r12d
	orl	%r14d, %r12d
	shll	$2, %r13d
	movq	%r13, %r14
	movl	$-2147483648, %r13d             ## imm = 0x80000000
	movl	%esi, -44(%rbp)                 ## 4-byte Spill
	movl	$-2147483648, %edx              ## imm = 0x80000000
	callq	_FPU_SUBS
	movl	%r15d, -48(%rbp)                ## 4-byte Spill
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_FPU_SUBC
	orl	$1, %ebx
	movl	%ebx, -52(%rbp)                 ## 4-byte Spill
	movq	%r14, %r15
	xorl	%edx, %edx
	movl	$-2147483648, %ebx              ## imm = 0x80000000
	.p2align	4, 0x90
LBB0_14:                                ## =>This Inner Loop Header: Depth=1
	sarl	%ebx
	movl	-48(%rbp), %r14d                ## 4-byte Reload
	addl	%r14d, %r14d
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	movl	%esi, %eax
	sarl	$31, %eax
	orl	%eax, %r14d
	addl	%esi, %esi
	movl	%r12d, %eax
	sarl	$31, %eax
	orl	%eax, %esi
	addl	%r12d, %r12d
	movl	%r15d, %eax
	sarl	$31, %eax
	orl	%eax, %r12d
	movl	%r12d, -56(%rbp)                ## 4-byte Spill
	addl	%r15d, %r15d
	movl	%edx, %r12d
	orl	%ebx, %edx
	movl	%esi, -44(%rbp)                 ## 4-byte Spill
	callq	_FPU_SUBS
	movl	%r14d, -48(%rbp)                ## 4-byte Spill
	movl	%r14d, %esi
	movl	-52(%rbp), %edx                 ## 4-byte Reload
	callq	_FPU_SUBC
	movl	%r12d, %edx
	movl	-56(%rbp), %r12d                ## 4-byte Reload
	andl	$-2, %r13d
	orl	%r13d, %edx
	movl	%ebx, %r13d
	jmp	LBB0_14
	.cfi_endproc
                                        ## -- End function
	.comm	_FPU_DECL_CARRY,4,2             ## @FPU_DECL_CARRY
	.comm	_FPE_REG,4,2                    ## @FPE_REG
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"fpu_sqer:\n"

L_.str.1:                               ## @.str.1
	.asciz	"=>\n"

	.comm	_FPSCR_VXSNAN,4,2               ## @FPSCR_VXSNAN
	.comm	_FPSCR_ZX,4,2                   ## @FPSCR_ZX
	.comm	_FPC_INF,4,2                    ## @FPC_INF
	.comm	_FPSCR_VXSQRT,4,2               ## @FPSCR_VXSQRT
	.comm	_FP_1,4,2                       ## @FP_1
	.comm	_DOUBLE_X,4,2                   ## @DOUBLE_X
	.comm	_EVEN_DOUBLE,4,2                ## @EVEN_DOUBLE
	.comm	_ODD_DOUBLE,4,2                 ## @ODD_DOUBLE
	.comm	_t0,4,2                         ## @t0
	.comm	_t1,4,2                         ## @t1
	.comm	_t2,4,2                         ## @t2
	.comm	_t3,4,2                         ## @t3
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_fpu_sqrt                       ; -- Begin function fpu_sqrt
	.p2align	2
_fpu_sqrt:                              ; @fpu_sqrt
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	add	x20, x0, #8
Lloh0:
	adrp	x21, _FPE_REG@GOTPAGE
Lloh1:
	ldr	x21, [x21, _FPE_REG@GOTPAGEOFF]
	ldr	w0, [x21]
Lloh2:
	adrp	x1, l_.str@PAGE
Lloh3:
	add	x1, x1, l_.str@PAGEOFF
	bl	_DPRINTF
	ldr	w0, [x21]
	mov	x1, x20
	bl	_DUMPFPN
	ldr	w0, [x21]
Lloh4:
	adrp	x1, l_.str.1@PAGE
Lloh5:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_DPRINTF
	mov	x0, x20
	bl	_ISNAN
	cbz	x0, LBB0_2
; %bb.1:
Lloh6:
	adrp	x8, _FPSCR_VXSNAN@GOTPAGE
Lloh7:
	ldr	x8, [x8, _FPSCR_VXSNAN@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
	b	LBB0_4
LBB0_2:
	mov	x0, x20
	bl	_ISZERO
	cbz	x0, LBB0_5
; %bb.3:
Lloh9:
	adrp	x8, _FPSCR_ZX@GOTPAGE
Lloh10:
	ldr	x8, [x8, _FPSCR_ZX@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
Lloh12:
	adrp	x8, _FPC_INF@GOTPAGE
Lloh13:
	ldr	x8, [x8, _FPC_INF@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	str	w8, [x19, #32]
LBB0_4:
	ldr	w0, [x21]
	mov	x1, x20
	bl	_DUMPFPN
	mov	x0, x20
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_5:
	ldr	x8, [x19, #24]
	cbz	x8, LBB0_7
; %bb.6:
Lloh15:
	adrp	x8, _FPSCR_VXSQRT@GOTPAGE
Lloh16:
	ldr	x8, [x8, _FPSCR_VXSQRT@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
	mov	x0, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_fpu_newnan
LBB0_7:
	mov	x0, x20
	bl	_ISINF
	cbnz	x0, LBB0_4
; %bb.8:
	ldr	x8, [x19, #8]
	ldp	w9, w10, [x8]
	asr	w11, w10, #31
	ldp	w12, w13, [x8, #8]
	ldr	w14, [x19, #16]
	orr	w11, w11, w9, lsl #1
	asr	w15, w12, #31
	orr	w15, w15, w10, lsl #1
	asr	w16, w13, #31
	orr	w16, w16, w12, lsl #1
	lsl	w17, w13, #1
	tst	w14, #0x1
	csel	w9, w9, w11, eq
	csel	w11, w10, w15, eq
	csel	w15, w12, w16, eq
	csel	w12, w13, w17, eq
	asr	w10, w14, #1
Lloh18:
	adrp	x13, _FP_1@GOTPAGE
Lloh19:
	ldr	x13, [x13, _FP_1@GOTPAGEOFF]
	str	w10, [x19, #16]
Lloh20:
	ldr	w10, [x13]
	asr	w13, w11, #31
	orr	w13, w13, w9, lsl #1
	asr	w9, w15, #31
	orr	w11, w9, w11, lsl #1
	asr	w9, w12, #31
	orr	w9, w9, w15, lsl #1
	sub	w13, w13, w10
	lsl	w19, w10, #1
	lsl	w14, w12, #1
	cmp	w10, #2
	b.lo	LBB0_11
; %bb.9:
	mov	x15, x10
LBB0_10:                                ; =>This Inner Loop Header: Depth=1
	mov	x12, x14
	asr	w14, w11, #31
	orr	w13, w14, w13, lsl #1
	asr	w16, w15, #1
	asr	w14, w9, #31
	orr	w11, w14, w11, lsl #1
	asr	w14, w12, #31
	orr	w9, w14, w9, lsl #1
	orr	w14, w19, w16
	and	w17, w15, #0xfffffffe
	cmp	w13, w14
	csel	w0, wzr, w16, lt
	orr	w10, w0, w10
	csel	w14, wzr, w14, lt
	csel	w17, wzr, w17, lt
	sub	w13, w13, w14
	orr	w19, w17, w19
	lsl	w14, w12, #1
	cmp	w15, #3
	mov	x15, x16
	b.hi	LBB0_10
LBB0_11:
	str	w10, [x8]
	asr	w8, w11, #31
	orr	w20, w8, w13, lsl #1
	asr	w8, w9, #31
	orr	w21, w8, w11, lsl #1
	asr	w8, w14, #31
	lsl	w22, w12, #2
	orr	w23, w8, w9, lsl #1
	mov	w24, #-2147483648
	mov	x1, x21
	mov	w2, #-2147483648
	bl	_FPU_SUBS
	mov	x1, x20
	mov	x2, x19
	bl	_FPU_SUBC
	mov	w25, #0
	orr	w19, w19, #0x1
LBB0_12:                                ; =>This Inner Loop Header: Depth=1
	asr	w26, w24, #1
	asr	w8, w21, #31
	orr	w20, w8, w20, lsl #1
	asr	w8, w23, #31
	orr	w21, w8, w21, lsl #1
	asr	w8, w22, #31
	lsl	w22, w22, #1
	orr	w2, w25, w26
	orr	w23, w8, w23, lsl #1
	mov	x1, x21
	bl	_FPU_SUBS
	mov	x1, x20
	mov	x2, x19
	bl	_FPU_SUBC
	and	w8, w24, #0xfffffffe
	orr	w25, w25, w8
	mov	x24, x26
	b	LBB0_12
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.cfi_endproc
                                        ; -- End function
	.comm	_FPU_DECL_CARRY,4,2             ; @FPU_DECL_CARRY
	.comm	_FPE_REG,4,2                    ; @FPE_REG
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"fpu_sqer:\n"

l_.str.1:                               ; @.str.1
	.asciz	"=>\n"

	.comm	_FPSCR_VXSNAN,4,2               ; @FPSCR_VXSNAN
	.comm	_FPSCR_ZX,4,2                   ; @FPSCR_ZX
	.comm	_FPC_INF,4,2                    ; @FPC_INF
	.comm	_FPSCR_VXSQRT,4,2               ; @FPSCR_VXSQRT
	.comm	_FP_1,4,2                       ; @FP_1
	.comm	_DOUBLE_X,4,2                   ; @DOUBLE_X
	.comm	_EVEN_DOUBLE,4,2                ; @EVEN_DOUBLE
	.comm	_ODD_DOUBLE,4,2                 ; @ODD_DOUBLE
	.comm	_t0,4,2                         ; @t0
	.comm	_t1,4,2                         ; @t1
	.comm	_t2,4,2                         ; @t2
	.comm	_t3,4,2                         ; @t3
.subsections_via_symbols
