	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function amd_thresholding_start
_amd_thresholding_start:                ## @amd_thresholding_start
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r15d
	movq	%rdi, %r14
	movq	_amd_elvt@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	shrq	$63, %rdi
	xorl	$1, %edi
	leaq	L_.str(%rip), %rsi
                                        ## kill: def $edi killed $edi killed $rdi
	callq	_KASSERT
	movq	_mca_msr_ops@GOTPCREL(%rip), %r12
	movl	%r15d, %edi
	callq	*(%r12)
	movl	%eax, %edi
	callq	_rdmsr
	movq	_MC_MISC_AMD_INT_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	_MC_MISC_AMD_INT_LVT@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_MC_MISC_AMD_LVT_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movq	_MC_MISC_AMD_LVT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	(%rbx), %esi
	shll	%cl, %esi
	notl	%eax
	andl	%edx, %eax
	orl	%eax, %esi
	movq	_MC_MISC_AMD_CNT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%esi, %eax
	movq	_MC_MISC_AMD_CNT_MAX@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	subl	(%r14), %edx
	movq	_MC_MISC_AMD_CNT_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	orl	%eax, %edx
	movq	_MC_MISC_AMD_OVERFLOW@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	notl	%ebx
	andl	%edx, %ebx
	movq	_MC_MISC_AMD_CNTEN@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	%r15d, %edi
	callq	*(%r12)
	movl	%eax, %edi
	movl	%ebx, %esi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_wrmsr                          ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_amd_elvt,8,3                   ## @amd_elvt
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"ELVT offset is not set"

	.comm	_mca_msr_ops,8,3                ## @mca_msr_ops
	.comm	_MC_MISC_AMD_INT_MASK,4,2       ## @MC_MISC_AMD_INT_MASK
	.comm	_MC_MISC_AMD_INT_LVT,4,2        ## @MC_MISC_AMD_INT_LVT
	.comm	_MC_MISC_AMD_LVT_MASK,4,2       ## @MC_MISC_AMD_LVT_MASK
	.comm	_MC_MISC_AMD_LVT_SHIFT,4,2      ## @MC_MISC_AMD_LVT_SHIFT
	.comm	_MC_MISC_AMD_CNT_MASK,4,2       ## @MC_MISC_AMD_CNT_MASK
	.comm	_MC_MISC_AMD_CNT_MAX,8,3        ## @MC_MISC_AMD_CNT_MAX
	.comm	_MC_MISC_AMD_CNT_SHIFT,4,2      ## @MC_MISC_AMD_CNT_SHIFT
	.comm	_MC_MISC_AMD_OVERFLOW,4,2       ## @MC_MISC_AMD_OVERFLOW
	.comm	_MC_MISC_AMD_CNTEN,4,2          ## @MC_MISC_AMD_CNTEN
	.no_dead_strip	_amd_thresholding_start
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function amd_thresholding_start
_amd_thresholding_start:                ; @amd_thresholding_start
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x1
	mov	x20, x0
Lloh0:
	adrp	x21, _amd_elvt@GOTPAGE
Lloh1:
	ldr	x21, [x21, _amd_elvt@GOTPAGEOFF]
	ldr	x8, [x21]
	lsr	x8, x8, #63
	eor	w0, w8, #0x1
Lloh2:
	adrp	x1, l_.str@PAGE
Lloh3:
	add	x1, x1, l_.str@PAGEOFF
	bl	_KASSERT
Lloh4:
	adrp	x22, _mca_msr_ops@GOTPAGE
Lloh5:
	ldr	x22, [x22, _mca_msr_ops@GOTPAGEOFF]
	ldr	x8, [x22]
	mov	x0, x19
	blr	x8
	bl	_rdmsr
Lloh6:
	adrp	x8, _MC_MISC_AMD_INT_MASK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _MC_MISC_AMD_INT_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
Lloh9:
	adrp	x9, _MC_MISC_AMD_INT_LVT@GOTPAGE
Lloh10:
	ldr	x9, [x9, _MC_MISC_AMD_INT_LVT@GOTPAGEOFF]
	bic	w8, w0, w8
Lloh11:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh12:
	adrp	x9, _MC_MISC_AMD_LVT_MASK@GOTPAGE
Lloh13:
	ldr	x9, [x9, _MC_MISC_AMD_LVT_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	bic	w8, w8, w9
	ldr	w9, [x21]
Lloh15:
	adrp	x10, _MC_MISC_AMD_LVT_SHIFT@GOTPAGE
Lloh16:
	ldr	x10, [x10, _MC_MISC_AMD_LVT_SHIFT@GOTPAGEOFF]
Lloh17:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w8, w9, w8
Lloh18:
	adrp	x9, _MC_MISC_AMD_CNT_MASK@GOTPAGE
Lloh19:
	ldr	x9, [x9, _MC_MISC_AMD_CNT_MASK@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
Lloh21:
	adrp	x10, _MC_MISC_AMD_CNT_MAX@GOTPAGE
Lloh22:
	ldr	x10, [x10, _MC_MISC_AMD_CNT_MAX@GOTPAGEOFF]
	bic	w8, w8, w9
Lloh23:
	ldr	w9, [x10]
	ldr	w10, [x20]
	sub	w9, w9, w10
Lloh24:
	adrp	x10, _MC_MISC_AMD_CNT_SHIFT@GOTPAGE
Lloh25:
	ldr	x10, [x10, _MC_MISC_AMD_CNT_SHIFT@GOTPAGEOFF]
Lloh26:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w8, w9, w8
Lloh27:
	adrp	x9, _MC_MISC_AMD_OVERFLOW@GOTPAGE
Lloh28:
	ldr	x9, [x9, _MC_MISC_AMD_OVERFLOW@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	bic	w8, w8, w9
Lloh30:
	adrp	x9, _MC_MISC_AMD_CNTEN@GOTPAGE
Lloh31:
	ldr	x9, [x9, _MC_MISC_AMD_CNTEN@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	orr	w20, w8, w9
	ldr	x8, [x22]
	mov	x0, x19
	blr	x8
	mov	x1, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_wrmsr
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_amd_elvt,8,3                   ; @amd_elvt
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"ELVT offset is not set"

	.comm	_mca_msr_ops,8,3                ; @mca_msr_ops
	.comm	_MC_MISC_AMD_INT_MASK,4,2       ; @MC_MISC_AMD_INT_MASK
	.comm	_MC_MISC_AMD_INT_LVT,4,2        ; @MC_MISC_AMD_INT_LVT
	.comm	_MC_MISC_AMD_LVT_MASK,4,2       ; @MC_MISC_AMD_LVT_MASK
	.comm	_MC_MISC_AMD_LVT_SHIFT,4,2      ; @MC_MISC_AMD_LVT_SHIFT
	.comm	_MC_MISC_AMD_CNT_MASK,4,2       ; @MC_MISC_AMD_CNT_MASK
	.comm	_MC_MISC_AMD_CNT_MAX,8,3        ; @MC_MISC_AMD_CNT_MAX
	.comm	_MC_MISC_AMD_CNT_SHIFT,4,2      ; @MC_MISC_AMD_CNT_SHIFT
	.comm	_MC_MISC_AMD_OVERFLOW,4,2       ; @MC_MISC_AMD_OVERFLOW
	.comm	_MC_MISC_AMD_CNTEN,4,2          ; @MC_MISC_AMD_CNTEN
	.no_dead_strip	_amd_thresholding_start
.subsections_via_symbols
