	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mips_platform_pcib_setup_intr
_mips_platform_pcib_setup_intr:         ## @mips_platform_pcib_setup_intr
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%r9, -64(%rbp)                  ## 8-byte Spill
	movq	%r8, %r15
	movl	%ecx, %ebx
	movq	%rdx, %r13
	movl	%esi, %r14d
	movl	%edi, %r12d
	movq	%rdx, %rdi
	callq	_rman_activate_resource
	movl	%eax, %ecx
	testl	%eax, %eax
	jne	LBB0_14
## %bb.1:
	movl	%r12d, -44(%rbp)                ## 4-byte Spill
	movl	%r14d, -48(%rbp)                ## 4-byte Spill
	movq	-64(%rbp), %r12                 ## 8-byte Reload
	movl	%ebx, -52(%rbp)                 ## 4-byte Spill
	movq	%r13, %rdi
	callq	_rman_get_start
	movl	%eax, %r14d
	movq	%r13, %rdi
	callq	_rman_get_end
	movl	%eax, %ebx
	movq	%r13, %rdi
	callq	_rman_get_start
	cmpl	%ebx, %r14d
	jne	LBB0_2
## %bb.3:
	xorl	%ecx, %ecx
	testl	%eax, %eax
	je	LBB0_14
## %bb.4:
	movl	%eax, %ebx
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	callq	_device_get_name
	leaq	L_.str.1(%rip), %rsi
	movl	%eax, %edi
	callq	_strcmp
	testq	%rax, %rax
	jne	LBB0_13
## %bb.5:
	cmpl	$64, %ebx
	jl	LBB0_6
## %bb.7:
	movl	%ebx, %eax
	testb	$31, %al
	movl	$0, %ecx
	jne	LBB0_14
## %bb.8:
	movq	%r12, %r13
	movq	%r15, %r12
	addl	$-64, %eax
	movl	%eax, %r15d
	xorl	%eax, %eax
	callq	_nlm_nodeid
	shrl	$5, %r15d
	movl	%eax, %edi
	movl	%r15d, %esi
	callq	_XLP_IO_PCIE_OFFSET
	movl	%eax, %edi
	callq	_nlm_pcicfg_base
	movl	%eax, %r14d
	movq	_PCIE_MSI_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PCIE_MSI_VECTOR_INT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r14d, %edi
	callq	_nlm_write_pci_reg
	movq	_PCIE_INT_EN0@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movl	%r14d, %edi
	callq	_nlm_read_pci_reg
	movl	(%rbx), %esi
	movq	_PCIE_MSI_INT_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%r14d, %edi
	movl	%eax, %edx
	callq	_nlm_write_pci_reg
	movq	_PCIE_BRIDGE_CMD@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movl	%r14d, %edi
	callq	_nlm_read_pci_reg
	movl	(%rbx), %esi
	movq	_PCIM_CMD_INTxDIS@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%r14d, %edi
	movl	%eax, %edx
	callq	_nlm_write_pci_reg
	movq	_PCIE_BRIDGE_MSI_ADDRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MSI_MIPS_ADDR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r14d, %edi
	callq	_nlm_write_pci_reg
	movq	_PCIE_BRIDGE_MSI_ADDRH@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r14d, %edi
	xorl	%edx, %edx
	callq	_nlm_write_pci_reg
	movq	_PCIE_BRIDGE_MSI_CAP@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movl	%r14d, %edi
	callq	_nlm_read_pci_reg
	movl	(%rbx), %esi
	movq	_PCIM_MSICTRL_MSI_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_PCIM_MSICTRL_MMC_32@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	shll	$16, %edx
	orl	%eax, %edx
	movl	%r14d, %edi
	callq	_nlm_write_pci_reg
	movl	%r15d, %edi
	callq	_PIC_PCIE_IRQ
	movl	%eax, %ebx
	movq	%r12, %r14
	jmp	LBB0_9
LBB0_2:
	movq	%r13, %rdi
	movl	%eax, %ebx
	callq	_rman_get_end
	leaq	L_.str(%rip), %rsi
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	movl	%ebx, %edx
	movl	%eax, %ecx
	callq	_device_printf
	movq	_EINVAL@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	jmp	LBB0_14
LBB0_6:
	movq	%r12, %r13
	movq	%r15, %r14
LBB0_9:
	movq	24(%rbp), %r12
	movq	16(%rbp), %r15
	xorl	%edi, %edi
	callq	_PIC_PCIE_IRQ
	cmpl	%eax, %ebx
	jl	LBB0_12
## %bb.10:
	movl	$3, %edi
	callq	_PIC_PCIE_IRQ
	cmpl	%eax, %ebx
	jg	LBB0_12
## %bb.11:
	movq	_bridge_pcie_ack@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%ebx, %edi
	xorl	%edx, %edx
	callq	_xlp_set_bus_ack
LBB0_12:
	movl	-48(%rbp), %edi                 ## 4-byte Reload
	callq	_device_get_name
	movq	%r12, (%rsp)
	movl	%eax, %edi
	movq	%r14, %rsi
	movq	%r13, %rdx
	movq	%r15, %rcx
	movl	%ebx, %r8d
	movl	-52(%rbp), %r9d                 ## 4-byte Reload
	callq	_cpu_establish_hardintr
LBB0_13:
	xorl	%ecx, %ecx
LBB0_14:
	movl	%ecx, %eax
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Interrupt allocation %ju != %ju\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
L_.str.1:                               ## @.str.1
	.asciz	"pcib"

	.comm	_PCIE_MSI_EN,4,2                ## @PCIE_MSI_EN
	.comm	_PCIE_MSI_VECTOR_INT_EN,4,2     ## @PCIE_MSI_VECTOR_INT_EN
	.comm	_PCIE_INT_EN0,4,2               ## @PCIE_INT_EN0
	.comm	_PCIE_MSI_INT_EN,4,2            ## @PCIE_MSI_INT_EN
	.comm	_PCIE_BRIDGE_CMD,4,2            ## @PCIE_BRIDGE_CMD
	.comm	_PCIM_CMD_INTxDIS,4,2           ## @PCIM_CMD_INTxDIS
	.comm	_PCIE_BRIDGE_MSI_ADDRL,4,2      ## @PCIE_BRIDGE_MSI_ADDRL
	.comm	_MSI_MIPS_ADDR_BASE,4,2         ## @MSI_MIPS_ADDR_BASE
	.comm	_PCIE_BRIDGE_MSI_ADDRH,4,2      ## @PCIE_BRIDGE_MSI_ADDRH
	.comm	_PCIE_BRIDGE_MSI_CAP,4,2        ## @PCIE_BRIDGE_MSI_CAP
	.comm	_PCIM_MSICTRL_MSI_ENABLE,4,2    ## @PCIM_MSICTRL_MSI_ENABLE
	.comm	_PCIM_MSICTRL_MMC_32,4,2        ## @PCIM_MSICTRL_MMC_32
	.comm	_bridge_pcie_ack,4,2            ## @bridge_pcie_ack
	.no_dead_strip	_mips_platform_pcib_setup_intr
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mips_platform_pcib_setup_intr
_mips_platform_pcib_setup_intr:         ; @mips_platform_pcib_setup_intr
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x7
	mov	x20, x6
	mov	x22, x5
	mov	x23, x4
	mov	x21, x3
	mov	x27, x2
	mov	x24, x1
	mov	x26, x0
	mov	x0, x2
	bl	_rman_activate_resource
	cbnz	w0, LBB0_13
; %bb.1:
	str	x19, [sp, #8]                   ; 8-byte Folded Spill
	mov	x0, x27
	bl	_rman_get_start
	mov	x28, x0
	mov	x0, x27
	bl	_rman_get_end
	mov	x19, x0
	mov	x0, x27
	bl	_rman_get_start
	mov	x25, x0
	cmp	w28, w19
	b.ne	LBB0_12
; %bb.2:
	cbz	w25, LBB0_11
; %bb.3:
	mov	x0, x26
	bl	_device_get_name
Lloh0:
	adrp	x1, l_.str.1@PAGE
Lloh1:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_strcmp
	cbnz	x0, LBB0_11
; %bb.4:
	subs	w19, w25, #64
	b.lt	LBB0_7
; %bb.5:
	tst	w25, #0x1f
	b.ne	LBB0_11
; %bb.6:
	bl	_nlm_nodeid
	lsr	w25, w19, #5
	mov	x1, x25
	bl	_XLP_IO_PCIE_OFFSET
	bl	_nlm_pcicfg_base
	mov	x26, x0
Lloh2:
	adrp	x8, _PCIE_MSI_EN@GOTPAGE
Lloh3:
	ldr	x8, [x8, _PCIE_MSI_EN@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
Lloh5:
	adrp	x8, _PCIE_MSI_VECTOR_INT_EN@GOTPAGE
Lloh6:
	ldr	x8, [x8, _PCIE_MSI_VECTOR_INT_EN@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	bl	_nlm_write_pci_reg
Lloh8:
	adrp	x19, _PCIE_INT_EN0@GOTPAGE
Lloh9:
	ldr	x19, [x19, _PCIE_INT_EN0@GOTPAGEOFF]
	ldr	w1, [x19]
	mov	x0, x26
	bl	_nlm_read_pci_reg
	ldr	w1, [x19]
Lloh10:
	adrp	x8, _PCIE_MSI_INT_EN@GOTPAGE
Lloh11:
	ldr	x8, [x8, _PCIE_MSI_INT_EN@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	orr	w2, w8, w0
	mov	x0, x26
	bl	_nlm_write_pci_reg
Lloh13:
	adrp	x19, _PCIE_BRIDGE_CMD@GOTPAGE
Lloh14:
	ldr	x19, [x19, _PCIE_BRIDGE_CMD@GOTPAGEOFF]
	ldr	w1, [x19]
	mov	x0, x26
	bl	_nlm_read_pci_reg
	ldr	w1, [x19]
Lloh15:
	adrp	x8, _PCIM_CMD_INTxDIS@GOTPAGE
Lloh16:
	ldr	x8, [x8, _PCIM_CMD_INTxDIS@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	orr	w2, w8, w0
	mov	x0, x26
	bl	_nlm_write_pci_reg
Lloh18:
	adrp	x8, _PCIE_BRIDGE_MSI_ADDRL@GOTPAGE
Lloh19:
	ldr	x8, [x8, _PCIE_BRIDGE_MSI_ADDRL@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
Lloh21:
	adrp	x8, _MSI_MIPS_ADDR_BASE@GOTPAGE
Lloh22:
	ldr	x8, [x8, _MSI_MIPS_ADDR_BASE@GOTPAGEOFF]
Lloh23:
	ldr	w2, [x8]
	mov	x0, x26
	bl	_nlm_write_pci_reg
Lloh24:
	adrp	x8, _PCIE_BRIDGE_MSI_ADDRH@GOTPAGE
Lloh25:
	ldr	x8, [x8, _PCIE_BRIDGE_MSI_ADDRH@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	x0, x26
	mov	w2, #0
	bl	_nlm_write_pci_reg
Lloh27:
	adrp	x19, _PCIE_BRIDGE_MSI_CAP@GOTPAGE
Lloh28:
	ldr	x19, [x19, _PCIE_BRIDGE_MSI_CAP@GOTPAGEOFF]
	ldr	w1, [x19]
	mov	x0, x26
	bl	_nlm_read_pci_reg
	ldr	w1, [x19]
Lloh29:
	adrp	x8, _PCIM_MSICTRL_MSI_ENABLE@GOTPAGE
Lloh30:
	ldr	x8, [x8, _PCIM_MSICTRL_MSI_ENABLE@GOTPAGEOFF]
Lloh31:
	ldr	w8, [x8]
Lloh32:
	adrp	x9, _PCIM_MSICTRL_MMC_32@GOTPAGE
Lloh33:
	ldr	x9, [x9, _PCIM_MSICTRL_MMC_32@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	orr	w8, w8, w9
	orr	w2, w0, w8, lsl #16
	mov	x0, x26
	bl	_nlm_write_pci_reg
	mov	x0, x25
	bl	_PIC_PCIE_IRQ
	mov	x25, x0
LBB0_7:
	mov	w0, #0
	bl	_PIC_PCIE_IRQ
	cmp	w25, w0
	b.lt	LBB0_10
; %bb.8:
	mov	w0, #3
	bl	_PIC_PCIE_IRQ
	cmp	w25, w0
	b.gt	LBB0_10
; %bb.9:
Lloh35:
	adrp	x8, _bridge_pcie_ack@GOTPAGE
Lloh36:
	ldr	x8, [x8, _bridge_pcie_ack@GOTPAGEOFF]
Lloh37:
	ldr	w1, [x8]
	mov	x0, x25
	mov	x2, #0
	bl	_xlp_set_bus_ack
LBB0_10:
	mov	x0, x24
	bl	_device_get_name
	mov	x1, x23
	mov	x2, x22
	mov	x3, x20
	mov	x4, x25
	mov	x5, x21
	ldr	x6, [sp, #8]                    ; 8-byte Folded Reload
	bl	_cpu_establish_hardintr
LBB0_11:
	mov	w0, #0
	b	LBB0_13
LBB0_12:
	mov	x0, x27
	bl	_rman_get_end
	mov	x3, x0
Lloh38:
	adrp	x1, l_.str@PAGE
Lloh39:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x26
	mov	x2, x25
	bl	_device_printf
Lloh40:
	adrp	x8, _EINVAL@GOTPAGE
Lloh41:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh42:
	ldr	w0, [x8]
LBB0_13:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpAdd	Lloh38, Lloh39
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Interrupt allocation %ju != %ju\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
l_.str.1:                               ; @.str.1
	.asciz	"pcib"

	.comm	_PCIE_MSI_EN,4,2                ; @PCIE_MSI_EN
	.comm	_PCIE_MSI_VECTOR_INT_EN,4,2     ; @PCIE_MSI_VECTOR_INT_EN
	.comm	_PCIE_INT_EN0,4,2               ; @PCIE_INT_EN0
	.comm	_PCIE_MSI_INT_EN,4,2            ; @PCIE_MSI_INT_EN
	.comm	_PCIE_BRIDGE_CMD,4,2            ; @PCIE_BRIDGE_CMD
	.comm	_PCIM_CMD_INTxDIS,4,2           ; @PCIM_CMD_INTxDIS
	.comm	_PCIE_BRIDGE_MSI_ADDRL,4,2      ; @PCIE_BRIDGE_MSI_ADDRL
	.comm	_MSI_MIPS_ADDR_BASE,4,2         ; @MSI_MIPS_ADDR_BASE
	.comm	_PCIE_BRIDGE_MSI_ADDRH,4,2      ; @PCIE_BRIDGE_MSI_ADDRH
	.comm	_PCIE_BRIDGE_MSI_CAP,4,2        ; @PCIE_BRIDGE_MSI_CAP
	.comm	_PCIM_MSICTRL_MSI_ENABLE,4,2    ; @PCIM_MSICTRL_MSI_ENABLE
	.comm	_PCIM_MSICTRL_MMC_32,4,2        ; @PCIM_MSICTRL_MMC_32
	.comm	_bridge_pcie_ack,4,2            ; @bridge_pcie_ack
	.no_dead_strip	_mips_platform_pcib_setup_intr
.subsections_via_symbols
