	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function atibl_setlevel
_atibl_setlevel:                        ## @atibl_setlevel
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	cmpl	$100, %esi
	movl	$100, %ebx
	cmovll	%esi, %ebx
	movq	%rdi, %r12
	movl	(%rdi), %edi
	movq	_RADEON_LVDS_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_bus_read_4
	movl	%eax, %r14d
	testl	%ebx, %ebx
	jle	LBB0_2
## %bb.1:
	leal	(%rbx,%rbx,4), %r15d
	shrl	%r15d
	addl	$5, %r15d
	movl	(%r12), %edi
	movq	_RADEON_DISP_PWR_MAN@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	callq	_bus_read_4
	movq	_RADEON_AUTO_PWRUP_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r12), %edi
	movl	(%rbx), %esi
	movl	%eax, %edx
	callq	_bus_write_4
	movl	(%r12), %edi
	movq	_RADEON_LVDS_PLL_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	callq	_bus_read_4
	movl	%eax, %ebx
	movq	_RADEON_LVDS_PLL_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	(%r12), %edi
	movl	(%r13), %esi
	movl	%ebx, %edx
	callq	_bus_write_4
	movq	_RADEON_LVDS_PLL_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	andl	%ebx, %edx
	movl	(%r12), %edi
	movl	(%r13), %esi
	callq	_bus_write_4
	movl	$1000, %edi                     ## imm = 0x3E8
	callq	_DELAY
	movq	_RADEON_LVDS_DISPLAY_DIS@GOTPCREL(%rip), %rax
	movq	_RADEON_LVDS_BL_MOD_LEVEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	(%rax), %eax
	orl	%edx, %eax
	notl	%eax
	andl	%eax, %r14d
	movq	_RADEON_LVDS_ON@GOTPCREL(%rip), %rax
	movq	_RADEON_LVDS_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	orl	%r14d, %ebx
	movq	_RADEON_LVDS_DIGON@GOTPCREL(%rip), %rax
	movq	_RADEON_LVDS_BLON@GOTPCREL(%rip), %rsi
	movq	_RADEON_LVDS_BL_MOD_LEVEL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r15d
	andl	%edx, %r15d
	orl	(%rax), %ebx
	orl	(%rsi), %ebx
	movq	_RADEON_LVDS_BL_MOD_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	orl	%r15d, %ebx
	movl	$200000, %edi                   ## imm = 0x30D40
	callq	_DELAY
	movl	(%r12), %edi
	movq	_RADEON_LVDS_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%ebx, %edx
	callq	_bus_write_4
	jmp	LBB0_3
LBB0_2:
	movq	_RADEON_PIXCLKS_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_atibl_pll_rreg
	movl	%eax, %r15d
	movl	(%rbx), %esi
	movq	_RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	andl	%r15d, %edx
	movq	%r12, %rdi
	callq	_atibl_pll_wreg
	movq	_RADEON_LVDS_DISPLAY_DIS@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
	movq	_RADEON_LVDS_BL_MOD_EN@GOTPCREL(%rip), %rax
	movq	_RADEON_LVDS_BL_MOD_LEVEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r13d
	orl	(%rax), %r13d
	notl	%r13d
	andl	%r14d, %r13d
	movl	(%r12), %edi
	movq	_RADEON_LVDS_GEN_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movl	%r13d, %edx
	callq	_bus_write_4
	movq	_RADEON_LVDS_ON@GOTPCREL(%rip), %rax
	movq	_RADEON_LVDS_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	notl	%ebx
	andl	%r13d, %ebx
	movl	$200000, %edi                   ## imm = 0x30D40
	callq	_DELAY
	movl	(%r12), %edi
	movl	(%r14), %esi
	movl	%ebx, %edx
	callq	_bus_write_4
	movq	_RADEON_PIXCLKS_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	%r15d, %edx
	callq	_atibl_pll_wreg
	movl	$200000, %edi                   ## imm = 0x30D40
	callq	_DELAY
LBB0_3:
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_LVDS_GEN_CNTL,4,2       ## @RADEON_LVDS_GEN_CNTL
	.comm	_RADEON_DISP_PWR_MAN,4,2        ## @RADEON_DISP_PWR_MAN
	.comm	_RADEON_AUTO_PWRUP_EN,4,2       ## @RADEON_AUTO_PWRUP_EN
	.comm	_RADEON_LVDS_PLL_CNTL,4,2       ## @RADEON_LVDS_PLL_CNTL
	.comm	_RADEON_LVDS_PLL_EN,4,2         ## @RADEON_LVDS_PLL_EN
	.comm	_RADEON_LVDS_PLL_RESET,4,2      ## @RADEON_LVDS_PLL_RESET
	.comm	_RADEON_LVDS_DISPLAY_DIS,4,2    ## @RADEON_LVDS_DISPLAY_DIS
	.comm	_RADEON_LVDS_BL_MOD_LEVEL_MASK,4,2 ## @RADEON_LVDS_BL_MOD_LEVEL_MASK
	.comm	_RADEON_LVDS_ON,4,2             ## @RADEON_LVDS_ON
	.comm	_RADEON_LVDS_EN,4,2             ## @RADEON_LVDS_EN
	.comm	_RADEON_LVDS_DIGON,4,2          ## @RADEON_LVDS_DIGON
	.comm	_RADEON_LVDS_BLON,4,2           ## @RADEON_LVDS_BLON
	.comm	_RADEON_LVDS_BL_MOD_LEVEL_SHIFT,4,2 ## @RADEON_LVDS_BL_MOD_LEVEL_SHIFT
	.comm	_RADEON_LVDS_BL_MOD_EN,4,2      ## @RADEON_LVDS_BL_MOD_EN
	.comm	_RADEON_PIXCLKS_CNTL,4,2        ## @RADEON_PIXCLKS_CNTL
	.comm	_RADEON_PIXCLK_LVDS_ALWAYS_ONb,4,2 ## @RADEON_PIXCLK_LVDS_ALWAYS_ONb
	.no_dead_strip	_atibl_setlevel
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function atibl_setlevel
_atibl_setlevel:                        ; @atibl_setlevel
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	mov	w8, #100
	cmp	w1, #100
	csel	w21, w1, w8, lt
	ldr	w0, [x0]
Lloh0:
	adrp	x22, _RADEON_LVDS_GEN_CNTL@GOTPAGE
Lloh1:
	ldr	x22, [x22, _RADEON_LVDS_GEN_CNTL@GOTPAGEOFF]
	ldr	w1, [x22]
	bl	_bus_read_4
	mov	x20, x0
	cmp	w21, #1
	b.lt	LBB0_2
; %bb.1:
	add	w8, w21, w21, lsl #2
	lsr	w8, w8, #1
	add	w23, w8, #5
	ldr	w0, [x19]
Lloh2:
	adrp	x21, _RADEON_DISP_PWR_MAN@GOTPAGE
Lloh3:
	ldr	x21, [x21, _RADEON_DISP_PWR_MAN@GOTPAGEOFF]
	ldr	w1, [x21]
	bl	_bus_read_4
Lloh4:
	adrp	x8, _RADEON_AUTO_PWRUP_EN@GOTPAGE
Lloh5:
	ldr	x8, [x8, _RADEON_AUTO_PWRUP_EN@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
	orr	w2, w8, w0
	ldr	w0, [x19]
	ldr	w1, [x21]
	bl	_bus_write_4
	ldr	w0, [x19]
Lloh7:
	adrp	x24, _RADEON_LVDS_PLL_CNTL@GOTPAGE
Lloh8:
	ldr	x24, [x24, _RADEON_LVDS_PLL_CNTL@GOTPAGEOFF]
	ldr	w1, [x24]
	bl	_bus_read_4
Lloh9:
	adrp	x8, _RADEON_LVDS_PLL_EN@GOTPAGE
Lloh10:
	ldr	x8, [x8, _RADEON_LVDS_PLL_EN@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	orr	w21, w8, w0
	ldr	w0, [x19]
	ldr	w1, [x24]
	mov	x2, x21
	bl	_bus_write_4
Lloh12:
	adrp	x8, _RADEON_LVDS_PLL_RESET@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RADEON_LVDS_PLL_RESET@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	bic	w2, w21, w8
	ldr	w0, [x19]
	ldr	w1, [x24]
	bl	_bus_write_4
	mov	w0, #1000
	bl	_DELAY
Lloh15:
	adrp	x8, _RADEON_LVDS_DISPLAY_DIS@GOTPAGE
Lloh16:
	ldr	x8, [x8, _RADEON_LVDS_DISPLAY_DIS@GOTPAGEOFF]
Lloh17:
	adrp	x9, _RADEON_LVDS_BL_MOD_LEVEL_MASK@GOTPAGE
Lloh18:
	ldr	x9, [x9, _RADEON_LVDS_BL_MOD_LEVEL_MASK@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
Lloh20:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w20, w8
Lloh21:
	adrp	x10, _RADEON_LVDS_ON@GOTPAGE
Lloh22:
	ldr	x10, [x10, _RADEON_LVDS_ON@GOTPAGEOFF]
Lloh23:
	ldr	w10, [x10]
Lloh24:
	adrp	x11, _RADEON_LVDS_EN@GOTPAGE
Lloh25:
	ldr	x11, [x11, _RADEON_LVDS_EN@GOTPAGEOFF]
Lloh26:
	ldr	w11, [x11]
Lloh27:
	adrp	x12, _RADEON_LVDS_DIGON@GOTPAGE
Lloh28:
	ldr	x12, [x12, _RADEON_LVDS_DIGON@GOTPAGEOFF]
	orr	w10, w11, w10
Lloh29:
	ldr	w11, [x12]
Lloh30:
	adrp	x12, _RADEON_LVDS_BLON@GOTPAGE
Lloh31:
	ldr	x12, [x12, _RADEON_LVDS_BLON@GOTPAGEOFF]
Lloh32:
	adrp	x13, _RADEON_LVDS_BL_MOD_LEVEL_SHIFT@GOTPAGE
Lloh33:
	ldr	x13, [x13, _RADEON_LVDS_BL_MOD_LEVEL_SHIFT@GOTPAGEOFF]
Lloh34:
	ldr	w12, [x12]
Lloh35:
	ldr	w13, [x13]
	lsl	w13, w23, w13
	and	w9, w13, w9
Lloh36:
	adrp	x13, _RADEON_LVDS_BL_MOD_EN@GOTPAGE
Lloh37:
	ldr	x13, [x13, _RADEON_LVDS_BL_MOD_EN@GOTPAGEOFF]
Lloh38:
	ldr	w13, [x13]
	orr	w8, w10, w8
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w8, w8, w13
	orr	w20, w8, w9
	mov	w0, #3392
	movk	w0, #3, lsl #16
	bl	_DELAY
	ldr	w0, [x19]
	ldr	w1, [x22]
	mov	x2, x20
	bl	_bus_write_4
	b	LBB0_3
LBB0_2:
Lloh39:
	adrp	x23, _RADEON_PIXCLKS_CNTL@GOTPAGE
Lloh40:
	ldr	x23, [x23, _RADEON_PIXCLKS_CNTL@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x19
	bl	_atibl_pll_rreg
	mov	x21, x0
	ldr	w1, [x23]
Lloh41:
	adrp	x8, _RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPAGE
Lloh42:
	ldr	x8, [x8, _RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPAGEOFF]
Lloh43:
	ldr	w8, [x8]
	bic	w2, w0, w8
	mov	x0, x19
	bl	_atibl_pll_wreg
Lloh44:
	adrp	x8, _RADEON_LVDS_DISPLAY_DIS@GOTPAGE
Lloh45:
	ldr	x8, [x8, _RADEON_LVDS_DISPLAY_DIS@GOTPAGEOFF]
Lloh46:
	ldr	w8, [x8]
	orr	w8, w8, w20
Lloh47:
	adrp	x9, _RADEON_LVDS_BL_MOD_EN@GOTPAGE
Lloh48:
	ldr	x9, [x9, _RADEON_LVDS_BL_MOD_EN@GOTPAGEOFF]
Lloh49:
	adrp	x10, _RADEON_LVDS_BL_MOD_LEVEL_MASK@GOTPAGE
Lloh50:
	ldr	x10, [x10, _RADEON_LVDS_BL_MOD_LEVEL_MASK@GOTPAGEOFF]
Lloh51:
	ldr	w9, [x9]
Lloh52:
	ldr	w10, [x10]
	orr	w9, w10, w9
	bic	w20, w8, w9
	ldr	w0, [x19]
	ldr	w1, [x22]
	mov	x2, x20
	bl	_bus_write_4
Lloh53:
	adrp	x8, _RADEON_LVDS_ON@GOTPAGE
Lloh54:
	ldr	x8, [x8, _RADEON_LVDS_ON@GOTPAGEOFF]
Lloh55:
	ldr	w8, [x8]
Lloh56:
	adrp	x9, _RADEON_LVDS_EN@GOTPAGE
Lloh57:
	ldr	x9, [x9, _RADEON_LVDS_EN@GOTPAGEOFF]
Lloh58:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w20, w20, w8
	mov	w0, #3392
	movk	w0, #3, lsl #16
	bl	_DELAY
	ldr	w0, [x19]
	ldr	w1, [x22]
	mov	x2, x20
	bl	_bus_write_4
	ldr	w1, [x23]
	mov	x0, x19
	mov	x2, x21
	bl	_atibl_pll_wreg
	mov	w0, #3392
	movk	w0, #3, lsl #16
	bl	_DELAY
LBB0_3:
	mov	w0, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh34
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh19
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh51
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh39, Lloh40
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_LVDS_GEN_CNTL,4,2       ; @RADEON_LVDS_GEN_CNTL
	.comm	_RADEON_DISP_PWR_MAN,4,2        ; @RADEON_DISP_PWR_MAN
	.comm	_RADEON_AUTO_PWRUP_EN,4,2       ; @RADEON_AUTO_PWRUP_EN
	.comm	_RADEON_LVDS_PLL_CNTL,4,2       ; @RADEON_LVDS_PLL_CNTL
	.comm	_RADEON_LVDS_PLL_EN,4,2         ; @RADEON_LVDS_PLL_EN
	.comm	_RADEON_LVDS_PLL_RESET,4,2      ; @RADEON_LVDS_PLL_RESET
	.comm	_RADEON_LVDS_DISPLAY_DIS,4,2    ; @RADEON_LVDS_DISPLAY_DIS
	.comm	_RADEON_LVDS_BL_MOD_LEVEL_MASK,4,2 ; @RADEON_LVDS_BL_MOD_LEVEL_MASK
	.comm	_RADEON_LVDS_ON,4,2             ; @RADEON_LVDS_ON
	.comm	_RADEON_LVDS_EN,4,2             ; @RADEON_LVDS_EN
	.comm	_RADEON_LVDS_DIGON,4,2          ; @RADEON_LVDS_DIGON
	.comm	_RADEON_LVDS_BLON,4,2           ; @RADEON_LVDS_BLON
	.comm	_RADEON_LVDS_BL_MOD_LEVEL_SHIFT,4,2 ; @RADEON_LVDS_BL_MOD_LEVEL_SHIFT
	.comm	_RADEON_LVDS_BL_MOD_EN,4,2      ; @RADEON_LVDS_BL_MOD_EN
	.comm	_RADEON_PIXCLKS_CNTL,4,2        ; @RADEON_PIXCLKS_CNTL
	.comm	_RADEON_PIXCLK_LVDS_ALWAYS_ONb,4,2 ; @RADEON_PIXCLK_LVDS_ALWAYS_ONb
	.no_dead_strip	_atibl_setlevel
.subsections_via_symbols
