	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gmc_v6_0_gart_disable
_gmc_v6_0_gart_disable:                 ## @gmc_v6_0_gart_disable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	movq	_mmVM_CONTEXT0_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT1_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmMC_VM_MX_L1_TLB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	callq	_WREG32
	movq	_mmVM_L2_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK@GOTPCREL(%rip), %rax
	movq	_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rdx
	orq	(%rax), %rdx
	movq	_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$7, %esi
	shlq	%cl, %rsi
	orq	%rdx, %rsi
	movq	_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	btsq	%rax, %rsi
	callq	_WREG32
	movq	_mmVM_L2_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmVM_L2_CNTL3@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	callq	_WREG32
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_amdgpu_gart_table_vram_unpin   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_mmVM_CONTEXT0_CNTL,4,2         ## @mmVM_CONTEXT0_CNTL
	.comm	_mmVM_CONTEXT1_CNTL,4,2         ## @mmVM_CONTEXT1_CNTL
	.comm	_mmMC_VM_MX_L1_TLB_CNTL,4,2     ## @mmMC_VM_MX_L1_TLB_CNTL
	.comm	_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK,8,3 ## @MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK
	.comm	_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT,8,3 ## @MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT
	.comm	_mmVM_L2_CNTL,4,2               ## @mmVM_L2_CNTL
	.comm	_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK,8,3 ## @VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK
	.comm	_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK,8,3 ## @VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK
	.comm	_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT,8,3 ## @VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT
	.comm	_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT,8,3 ## @VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT
	.comm	_mmVM_L2_CNTL2,4,2              ## @mmVM_L2_CNTL2
	.comm	_mmVM_L2_CNTL3,4,2              ## @mmVM_L2_CNTL3
	.comm	_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK,8,3 ## @VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK
	.comm	_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT,8,3 ## @VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT
	.no_dead_strip	_gmc_v6_0_gart_disable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gmc_v6_0_gart_disable
_gmc_v6_0_gart_disable:                 ; @gmc_v6_0_gart_disable
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
Lloh0:
	adrp	x8, _mmVM_CONTEXT0_CNTL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _mmVM_CONTEXT0_CNTL@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	mov	x1, #0
	bl	_WREG32
Lloh3:
	adrp	x8, _mmVM_CONTEXT1_CNTL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _mmVM_CONTEXT1_CNTL@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	mov	x1, #0
	bl	_WREG32
Lloh6:
	adrp	x8, _mmMC_VM_MX_L1_TLB_CNTL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _mmMC_VM_MX_L1_TLB_CNTL@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
Lloh9:
	adrp	x8, _MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK@GOTPAGEOFF]
Lloh11:
	ldr	x1, [x8]
	bl	_WREG32
Lloh12:
	adrp	x8, _mmVM_L2_CNTL@GOTPAGE
Lloh13:
	ldr	x8, [x8, _mmVM_L2_CNTL@GOTPAGEOFF]
Lloh14:
	adrp	x9, _VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK@GOTPAGE
Lloh15:
	ldr	x9, [x9, _VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
Lloh17:
	ldr	x8, [x9]
Lloh18:
	adrp	x9, _VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK@GOTPAGE
Lloh19:
	ldr	x9, [x9, _VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK@GOTPAGEOFF]
Lloh20:
	ldr	x9, [x9]
	orr	x8, x9, x8
Lloh21:
	adrp	x9, _VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT@GOTPAGE
Lloh22:
	ldr	x9, [x9, _VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT@GOTPAGEOFF]
Lloh23:
	ldr	x9, [x9]
	mov	w10, #7
	lsl	x9, x10, x9
	orr	x8, x8, x9
Lloh24:
	adrp	x9, _VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT@GOTPAGE
Lloh25:
	ldr	x9, [x9, _VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT@GOTPAGEOFF]
Lloh26:
	ldr	x9, [x9]
	mov	w10, #1
	lsl	x9, x10, x9
	orr	x1, x8, x9
	bl	_WREG32
Lloh27:
	adrp	x8, _mmVM_L2_CNTL2@GOTPAGE
Lloh28:
	ldr	x8, [x8, _mmVM_L2_CNTL2@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	mov	x1, #0
	bl	_WREG32
Lloh30:
	adrp	x8, _mmVM_L2_CNTL3@GOTPAGE
Lloh31:
	ldr	x8, [x8, _mmVM_L2_CNTL3@GOTPAGEOFF]
Lloh32:
	ldr	w0, [x8]
Lloh33:
	adrp	x8, _VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK@GOTPAGE
Lloh34:
	ldr	x8, [x8, _VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK@GOTPAGEOFF]
Lloh35:
	ldr	x1, [x8]
	bl	_WREG32
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_amdgpu_gart_table_vram_unpin
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh16
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_mmVM_CONTEXT0_CNTL,4,2         ; @mmVM_CONTEXT0_CNTL
	.comm	_mmVM_CONTEXT1_CNTL,4,2         ; @mmVM_CONTEXT1_CNTL
	.comm	_mmMC_VM_MX_L1_TLB_CNTL,4,2     ; @mmMC_VM_MX_L1_TLB_CNTL
	.comm	_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK,8,3 ; @MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK
	.comm	_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT,8,3 ; @MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT
	.comm	_mmVM_L2_CNTL,4,2               ; @mmVM_L2_CNTL
	.comm	_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK,8,3 ; @VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK
	.comm	_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK,8,3 ; @VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK
	.comm	_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT,8,3 ; @VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT
	.comm	_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT,8,3 ; @VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT
	.comm	_mmVM_L2_CNTL2,4,2              ; @mmVM_L2_CNTL2
	.comm	_mmVM_L2_CNTL3,4,2              ; @mmVM_L2_CNTL3
	.comm	_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK,8,3 ; @VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK
	.comm	_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT,8,3 ; @VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT
	.no_dead_strip	_gmc_v6_0_gart_disable
.subsections_via_symbols
