	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function amdgpu_vm_update_ptes
_amdgpu_vm_update_ptes:                 ## @amdgpu_vm_update_ptes
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$88, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%r8d, %eax
	movl	%ecx, %ebx
	movl	%edx, %r14d
	movl	%esi, %r13d
	movq	%rdi, %r12
	movq	8(%rdi), %r15
	leaq	-48(%rbp), %r8
	leaq	-64(%rbp), %r9
	movl	%eax, -60(%rbp)                 ## 4-byte Spill
	movl	%eax, %ecx
	callq	_amdgpu_vm_fragment
	movl	(%r12), %esi
	leaq	-88(%rbp), %rcx
	movq	%r15, %rdi
	movl	%r13d, -44(%rbp)                ## 4-byte Spill
	movl	%r13d, %edx
	callq	_amdgpu_vm_pt_start
	xorl	%eax, %eax
	movl	%r14d, -52(%rbp)                ## 4-byte Spill
	cmpl	%r14d, -88(%rbp)
	jae	LBB0_27
## %bb.1:
	leaq	-88(%rbp), %r13
	movq	%rbx, %r14
	movq	%r12, -72(%rbp)                 ## 8-byte Spill
	movq	%r15, -112(%rbp)                ## 8-byte Spill
	jmp	LBB0_2
	.p2align	4, 0x90
LBB0_4:                                 ##   in Loop: Header=BB0_2 Depth=1
	movq	%r15, %rdi
	movq	%r13, %rsi
	callq	_amdgpu_vm_pt_descendant
	testq	%rax, %rax
	je	LBB0_5
LBB0_25:                                ##   in Loop: Header=BB0_2 Depth=1
	movl	-52(%rbp), %eax                 ## 4-byte Reload
	cmpl	%eax, -88(%rbp)
	jae	LBB0_26
LBB0_2:                                 ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_10 Depth 2
                                        ##     Child Loop BB0_21 Depth 2
	movq	8(%r12), %rdi
	movl	(%r12), %esi
	movq	%r13, %rdx
	callq	_amdgpu_vm_alloc_pts
	testl	%eax, %eax
	jne	LBB0_27
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movl	-84(%rbp), %esi
	cmpl	8(%r15), %esi
	je	LBB0_4
## %bb.6:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	-80(%rbp), %rax
	movq	(%rax), %rax
	movq	%rax, -128(%rbp)                ## 8-byte Spill
	movq	%r15, %rdi
	callq	_amdgpu_vm_level_shift
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	movl	-84(%rbp), %esi
	decl	%esi
	movq	%r15, %rdi
	callq	_amdgpu_vm_level_shift
	movq	(%r15), %rcx
	movq	_CHIP_VEGA10@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jge	LBB0_13
## %bb.7:                               ##   in Loop: Header=BB0_2 Depth=1
	movl	-60(%rbp), %ecx                 ## 4-byte Reload
	movq	_AMDGPU_PTE_VALID@GOTPCREL(%rip), %rdx
	testl	%ecx, (%rdx)
	je	LBB0_13
## %bb.8:                               ##   in Loop: Header=BB0_2 Depth=1
	movl	-84(%rbp), %esi
	movq	_AMDGPU_VM_PTB@GOTPCREL(%rip), %rax
	cmpl	(%rax), %esi
	jne	LBB0_4
	jmp	LBB0_9
	.p2align	4, 0x90
LBB0_13:                                ##   in Loop: Header=BB0_2 Depth=1
	movl	-48(%rbp), %ecx
	cmpl	-56(%rbp), %ecx                 ## 4-byte Folded Reload
	jb	LBB0_4
## %bb.14:                              ##   in Loop: Header=BB0_2 Depth=1
	movl	-84(%rbp), %esi
	cmpl	%eax, %ecx
	jb	LBB0_9
## %bb.15:                              ##   in Loop: Header=BB0_2 Depth=1
	leal	-1(%rsi), %eax
	cmpl	8(%r15), %eax
	jne	LBB0_16
	.p2align	4, 0x90
LBB0_9:                                 ##   in Loop: Header=BB0_2 Depth=1
	movq	_AMDGPU_GPU_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	-56(%rbp), %r12d                ## 4-byte Reload
	movl	%r12d, %ecx
	shll	%cl, %eax
	movq	%rax, -120(%rbp)                ## 8-byte Spill
	movq	%r15, %rdi
                                        ## kill: def $esi killed $esi killed $rsi
	callq	_amdgpu_vm_entries_mask
                                        ## kill: def $eax killed $eax def $rax
	movl	-88(%rbp), %edx
	movl	%edx, %esi
	movl	%r12d, %ecx
	shrl	%cl, %esi
	andl	%eax, %esi
	incl	%eax
	shll	%cl, %eax
	shll	$3, %esi
	movq	%rsi, -104(%rbp)                ## 8-byte Spill
	movl	%eax, %edi
	negl	%edi
	andl	%edx, %edi
	addl	%eax, %edi
	movl	-52(%rbp), %esi                 ## 4-byte Reload
	callq	_min
	movl	-44(%rbp), %r13d                ## 4-byte Reload
	movl	%eax, -92(%rbp)                 ## 4-byte Spill
	jmp	LBB0_10
	.p2align	4, 0x90
LBB0_17:                                ##   in Loop: Header=BB0_10 Depth=2
	movl	-92(%rbp), %eax                 ## 4-byte Reload
	cmpl	%eax, %r13d
	movl	%r15d, %r12d
	jae	LBB0_18
LBB0_10:                                ##   Parent Loop BB0_2 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movl	%r14d, -44(%rbp)                ## 4-byte Spill
	movl	%r13d, %ebx
	movl	-64(%rbp), %esi
	movl	%eax, %edi
	callq	_min
	movl	%eax, %r13d
	movl	%eax, %r14d
	subl	%ebx, %r14d
	movl	-60(%rbp), %ebx                 ## 4-byte Reload
	movl	%r12d, %ecx
	shrl	%cl, %r14d
	movl	-84(%rbp), %r12d
	movl	-48(%rbp), %edi
	callq	_AMDGPU_PTE_FRAG
                                        ## kill: def $eax killed $eax def $rax
	orl	%ebx, %eax
	movq	-72(%rbp), %rdi                 ## 8-byte Reload
	movq	-128(%rbp), %rsi                ## 8-byte Reload
	movl	%r12d, %edx
	movl	-56(%rbp), %r15d                ## 4-byte Reload
	movq	-104(%rbp), %rbx                ## 8-byte Reload
	movl	%ebx, %ecx
	movl	-44(%rbp), %r12d                ## 4-byte Reload
	movl	%r12d, %r8d
	movl	%r14d, %r9d
	pushq	%rax
	pushq	-120(%rbp)                      ## 8-byte Folded Reload
	callq	_amdgpu_vm_update_flags
	addq	$16, %rsp
	leal	(%rbx,%r14,8), %ebx
	movq	%rbx, -104(%rbp)                ## 8-byte Spill
	movq	_AMDGPU_GPU_PAGE_SIZE@GOTPCREL(%rip), %rax
	imull	(%rax), %r14d
	movl	%r15d, %ecx
	shll	%cl, %r14d
	addl	%r12d, %r14d
	cmpl	-64(%rbp), %r13d
	jb	LBB0_17
## %bb.11:                              ##   in Loop: Header=BB0_10 Depth=2
	movq	-72(%rbp), %rdi                 ## 8-byte Reload
	movl	%r13d, %esi
	movl	-52(%rbp), %edx                 ## 4-byte Reload
	movl	-60(%rbp), %ecx                 ## 4-byte Reload
	leaq	-48(%rbp), %r8
	leaq	-64(%rbp), %r9
	callq	_amdgpu_vm_fragment
	cmpl	%r15d, -48(%rbp)
	movl	-92(%rbp), %eax                 ## 4-byte Reload
	movl	%r15d, %r12d
	jb	LBB0_18
## %bb.12:                              ##   in Loop: Header=BB0_10 Depth=2
	cmpl	%eax, %r13d
	jb	LBB0_10
LBB0_18:                                ##   in Loop: Header=BB0_2 Depth=1
	movl	%r13d, -44(%rbp)                ## 4-byte Spill
	movq	-112(%rbp), %r15                ## 8-byte Reload
	movq	%r15, %rdi
	leaq	-88(%rbp), %r13
	movq	%r13, %rsi
	callq	_amdgpu_vm_pt_descendant
	testq	%rax, %rax
	je	LBB0_22
## %bb.19:                              ##   in Loop: Header=BB0_2 Depth=1
	movl	-44(%rbp), %eax                 ## 4-byte Reload
	cmpl	%eax, -88(%rbp)
	jae	LBB0_24
## %bb.20:                              ##   in Loop: Header=BB0_2 Depth=1
	movq	-72(%rbp), %r12                 ## 8-byte Reload
	movl	-44(%rbp), %ebx                 ## 4-byte Reload
	.p2align	4, 0x90
LBB0_21:                                ##   Parent Loop BB0_2 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movl	(%r12), %esi
	movq	%r15, %rdi
	movq	%r13, %rdx
	callq	_amdgpu_vm_free_pts
	movq	%r15, %rdi
	movq	%r13, %rsi
	callq	_amdgpu_vm_pt_next
	cmpl	%ebx, -88(%rbp)
	jb	LBB0_21
	jmp	LBB0_25
LBB0_22:                                ##   in Loop: Header=BB0_2 Depth=1
	cmpl	%r12d, -48(%rbp)
	jb	LBB0_24
## %bb.23:                              ##   in Loop: Header=BB0_2 Depth=1
	movq	%r15, %rdi
	movq	%r13, %rsi
	callq	_amdgpu_vm_pt_next
LBB0_24:                                ##   in Loop: Header=BB0_2 Depth=1
	movq	-72(%rbp), %r12                 ## 8-byte Reload
	jmp	LBB0_25
LBB0_16:                                ##   in Loop: Header=BB0_2 Depth=1
	movq	%r13, %rdi
	callq	_amdgpu_vm_pt_ancestor
	testl	%eax, %eax
	jne	LBB0_25
LBB0_5:
	movq	_ENOENT@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_27
LBB0_26:
	xorl	%eax, %eax
LBB0_27:
	addq	$88, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_ENOENT,4,2                     ## @ENOENT
	.comm	_CHIP_VEGA10,8,3                ## @CHIP_VEGA10
	.comm	_AMDGPU_PTE_VALID,4,2           ## @AMDGPU_PTE_VALID
	.comm	_AMDGPU_VM_PTB,4,2              ## @AMDGPU_VM_PTB
	.comm	_AMDGPU_GPU_PAGE_SIZE,4,2       ## @AMDGPU_GPU_PAGE_SIZE
	.no_dead_strip	_amdgpu_vm_update_ptes
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function amdgpu_vm_update_ptes
_amdgpu_vm_update_ptes:                 ; @amdgpu_vm_update_ptes
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #160
	.cfi_def_cfa_offset 160
	stp	x28, x27, [sp, #64]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #80]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #96]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #112]            ; 16-byte Folded Spill
	stp	x20, x19, [sp, #128]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #144]            ; 16-byte Folded Spill
	add	x29, sp, #144
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x4
	mov	x20, x3
	mov	x21, x2
	mov	x24, x1
	mov	x22, x0
	ldr	x23, [x0, #8]
	add	x4, sp, #40
	add	x5, sp, #44
	mov	x3, x19
	bl	_amdgpu_vm_fragment
	ldr	w1, [x22]
	add	x3, sp, #48
	mov	x0, x23
	mov	x2, x24
	bl	_amdgpu_vm_pt_start
	ldr	w8, [sp, #48]
	str	w21, [sp, #12]                  ; 4-byte Folded Spill
	cmp	w8, w21
	b.hs	LBB0_25
; %bb.1:
Lloh0:
	adrp	x21, _CHIP_VEGA10@GOTPAGE
Lloh1:
	ldr	x21, [x21, _CHIP_VEGA10@GOTPAGEOFF]
	str	w19, [sp, #28]                  ; 4-byte Folded Spill
	str	x22, [sp, #16]                  ; 8-byte Folded Spill
	str	x23, [sp]                       ; 8-byte Folded Spill
	mov	w26, w19
	b	LBB0_4
LBB0_2:                                 ;   in Loop: Header=BB0_4 Depth=1
	add	x1, sp, #48
	mov	x0, x23
	bl	_amdgpu_vm_pt_descendant
	cbz	x0, LBB0_24
LBB0_3:                                 ;   in Loop: Header=BB0_4 Depth=1
	ldr	w8, [sp, #48]
	ldr	w9, [sp, #12]                   ; 4-byte Folded Reload
	cmp	w8, w9
	b.hs	LBB0_25
LBB0_4:                                 ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_14 Depth 2
                                        ;     Child Loop BB0_19 Depth 2
	ldr	x0, [x22, #8]
	ldr	w1, [x22]
	add	x2, sp, #48
	bl	_amdgpu_vm_alloc_pts
	cbnz	w0, LBB0_26
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	ldr	w1, [sp, #52]
	ldr	w8, [x23, #8]
	cmp	w1, w8
	b.eq	LBB0_2
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=1
	ldr	x8, [sp, #56]
	ldr	x8, [x8]
	str	x8, [sp, #32]                   ; 8-byte Folded Spill
	mov	x0, x23
	bl	_amdgpu_vm_level_shift
	mov	x25, x0
	ldr	w8, [sp, #52]
	sub	w1, w8, #1
	mov	x0, x23
	bl	_amdgpu_vm_level_shift
	ldr	x8, [x23]
	ldr	x9, [x21]
	cmp	x8, x9
	b.ge	LBB0_9
; %bb.7:                                ;   in Loop: Header=BB0_4 Depth=1
Lloh2:
	adrp	x8, _AMDGPU_PTE_VALID@GOTPAGE
Lloh3:
	ldr	x8, [x8, _AMDGPU_PTE_VALID@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	tst	w8, w19
	b.eq	LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_4 Depth=1
	ldr	w1, [sp, #52]
Lloh5:
	adrp	x8, _AMDGPU_VM_PTB@GOTPAGE
Lloh6:
	ldr	x8, [x8, _AMDGPU_VM_PTB@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	cmp	w1, w8
	b.ne	LBB0_2
	b	LBB0_12
LBB0_9:                                 ;   in Loop: Header=BB0_4 Depth=1
	ldr	w8, [sp, #40]
	cmp	w8, w25
	b.lo	LBB0_2
; %bb.10:                               ;   in Loop: Header=BB0_4 Depth=1
	ldr	w1, [sp, #52]
	cmp	w8, w0
	b.lo	LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_4 Depth=1
	sub	w8, w1, #1
	ldr	w9, [x23, #8]
	cmp	w8, w9
	b.ne	LBB0_23
LBB0_12:                                ;   in Loop: Header=BB0_4 Depth=1
Lloh8:
	adrp	x8, _AMDGPU_GPU_PAGE_SIZE@GOTPAGE
Lloh9:
	ldr	x8, [x8, _AMDGPU_GPU_PAGE_SIZE@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	lsl	w27, w8, w25
	mov	x0, x23
	bl	_amdgpu_vm_entries_mask
	ldr	w8, [sp, #48]
	lsr	w9, w8, w25
	and	w9, w9, w0
	lsl	w28, w9, #3
	add	w9, w0, #1
	lsl	w9, w9, w25
	neg	w10, w9
	and	w8, w8, w10
	add	w0, w8, w9
	ldr	w1, [sp, #12]                   ; 4-byte Folded Reload
	bl	_min
	mov	x21, x0
	b	LBB0_14
LBB0_13:                                ;   in Loop: Header=BB0_14 Depth=2
	cmp	w24, w21
	b.hs	LBB0_16
LBB0_14:                                ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	mov	x19, x24
	ldr	w1, [sp, #44]
	mov	x0, x21
	bl	_min
	mov	x24, x0
	sub	w8, w0, w19
	lsr	w23, w8, w25
	ldr	w19, [sp, #52]
	ldr	w0, [sp, #40]
	bl	_AMDGPU_PTE_FRAG
	orr	w7, w0, w26
	ldr	x22, [sp, #16]                  ; 8-byte Folded Reload
	mov	x0, x22
	ldr	x1, [sp, #32]                   ; 8-byte Folded Reload
	mov	x2, x19
	mov	x3, x28
	mov	x4, x20
	mov	x5, x23
	mov	x6, x27
	bl	_amdgpu_vm_update_flags
	add	w28, w28, w23, lsl #3
Lloh11:
	adrp	x8, _AMDGPU_GPU_PAGE_SIZE@GOTPAGE
Lloh12:
	ldr	x8, [x8, _AMDGPU_GPU_PAGE_SIZE@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
	mul	w8, w8, w23
	lsl	w8, w8, w25
	add	w20, w8, w20
	ldr	w8, [sp, #44]
	cmp	w24, w8
	b.lo	LBB0_13
; %bb.15:                               ;   in Loop: Header=BB0_14 Depth=2
	add	x4, sp, #40
	add	x5, sp, #44
	mov	x0, x22
	mov	x1, x24
	ldr	w2, [sp, #12]                   ; 4-byte Folded Reload
	mov	x3, x26
	bl	_amdgpu_vm_fragment
	ldr	w8, [sp, #40]
	cmp	w8, w25
	b.hs	LBB0_13
LBB0_16:                                ;   in Loop: Header=BB0_4 Depth=1
	add	x1, sp, #48
	ldr	x23, [sp]                       ; 8-byte Folded Reload
	mov	x0, x23
	bl	_amdgpu_vm_pt_descendant
	cbz	x0, LBB0_20
; %bb.17:                               ;   in Loop: Header=BB0_4 Depth=1
	ldr	w8, [sp, #48]
	cmp	w8, w24
	b.hs	LBB0_22
; %bb.18:                               ;   in Loop: Header=BB0_4 Depth=1
	ldr	w19, [sp, #28]                  ; 4-byte Folded Reload
	ldr	x22, [sp, #16]                  ; 8-byte Folded Reload
Lloh14:
	adrp	x21, _CHIP_VEGA10@GOTPAGE
Lloh15:
	ldr	x21, [x21, _CHIP_VEGA10@GOTPAGEOFF]
LBB0_19:                                ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ldr	w1, [x22]
	add	x2, sp, #48
	mov	x0, x23
	bl	_amdgpu_vm_free_pts
	add	x1, sp, #48
	mov	x0, x23
	bl	_amdgpu_vm_pt_next
	ldr	w8, [sp, #48]
	cmp	w8, w24
	b.lo	LBB0_19
	b	LBB0_3
LBB0_20:                                ;   in Loop: Header=BB0_4 Depth=1
	ldr	w8, [sp, #40]
	cmp	w8, w25
	b.lo	LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_4 Depth=1
	add	x1, sp, #48
	mov	x0, x23
	bl	_amdgpu_vm_pt_next
LBB0_22:                                ;   in Loop: Header=BB0_4 Depth=1
	ldr	w19, [sp, #28]                  ; 4-byte Folded Reload
	ldr	x22, [sp, #16]                  ; 8-byte Folded Reload
Lloh16:
	adrp	x21, _CHIP_VEGA10@GOTPAGE
Lloh17:
	ldr	x21, [x21, _CHIP_VEGA10@GOTPAGEOFF]
	b	LBB0_3
LBB0_23:                                ;   in Loop: Header=BB0_4 Depth=1
	add	x0, sp, #48
	bl	_amdgpu_vm_pt_ancestor
	cbnz	w0, LBB0_3
LBB0_24:
Lloh18:
	adrp	x8, _ENOENT@GOTPAGE
Lloh19:
	ldr	x8, [x8, _ENOENT@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_26
LBB0_25:
	mov	w0, #0
LBB0_26:
	ldp	x29, x30, [sp, #144]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #128]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #112]            ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #96]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #80]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #64]             ; 16-byte Folded Reload
	add	sp, sp, #160
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.cfi_endproc
                                        ; -- End function
	.comm	_ENOENT,4,2                     ; @ENOENT
	.comm	_CHIP_VEGA10,8,3                ; @CHIP_VEGA10
	.comm	_AMDGPU_PTE_VALID,4,2           ; @AMDGPU_PTE_VALID
	.comm	_AMDGPU_VM_PTB,4,2              ; @AMDGPU_VM_PTB
	.comm	_AMDGPU_GPU_PAGE_SIZE,4,2       ; @AMDGPU_GPU_PAGE_SIZE
	.no_dead_strip	_amdgpu_vm_update_ptes
.subsections_via_symbols
