	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function a5xx_hw_init
_a5xx_hw_init:                          ## @a5xx_hw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	callq	_to_adreno_gpu
	movq	%rax, %r14
	movq	_REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$3, %edx
	callq	_gpu_write
	movq	%r14, %rdi
	callq	_adreno_is_a540
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	_REG_A5XX_VBIF_GATE_OFF_WRREQ_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$9, %edx
	callq	_gpu_write
LBB0_2:
	movq	_REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$-1, %edx
	callq	_gpu_write
	movq	_REG_A5XX_RBBM_AHB_CNTL0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	8(%r14), %rax
	movq	_ADRENO_QUIRK_FAULT_DETECT_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, (%rax)
	je	LBB0_4
## %bb.3:
	movq	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$-268435456, %edx               ## imm = 0xF0000000
	callq	_gpu_write
	movq	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$-1, %edx
	callq	_gpu_write
	movq	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$-1, %edx
	callq	_gpu_write
	movq	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$-1, %edx
	callq	_gpu_write
	movq	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$-1, %edx
	callq	_gpu_write
	movq	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$-1, %edx
	callq	_gpu_write
	movq	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$-1, %edx
	callq	_gpu_write
	movq	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$-1, %edx
	callq	_gpu_write
LBB0_4:
	movq	_REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1073807359, %edx               ## imm = 0x4000FFFF
	callq	_gpu_write
	movq	_REG_A5XX_RBBM_PERFCTR_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A5XX_CP_PERFCTR_CP_SEL_0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PERF_CP_ALWAYS_COUNT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_gpu_write
	movq	_REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$6, %edx
	callq	_gpu_write
	movq	_REG_A5XX_UCHE_CACHE_WAYS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$2, %edx
	callq	_gpu_write
	movq	_REG_A5XX_UCHE_TRAP_BASE_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$-65536, %edx                   ## imm = 0xFFFF0000
	callq	_gpu_write
	movq	_REG_A5XX_UCHE_TRAP_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$131071, %edx                   ## imm = 0x1FFFF
	callq	_gpu_write
	movq	_REG_A5XX_UCHE_WRITE_THRU_BASE_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$-65536, %edx                   ## imm = 0xFFFF0000
	callq	_gpu_write
	movq	_REG_A5XX_UCHE_WRITE_THRU_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$131071, %edx                   ## imm = 0x1FFFF
	callq	_gpu_write
	movq	_REG_A5XX_UCHE_GMEM_RANGE_MIN_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1048576, %edx                  ## imm = 0x100000
	callq	_gpu_write
	movq	_REG_A5XX_UCHE_GMEM_RANGE_MIN_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movq	_REG_A5XX_UCHE_GMEM_RANGE_MAX_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1048575, %edx                  ## imm = 0xFFFFF
	addl	(%r14), %edx
	movq	%rbx, %rdi
	callq	_gpu_write
	movq	_REG_A5XX_UCHE_GMEM_RANGE_MAX_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movq	_REG_A5XX_CP_MEQ_THRESHOLDS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$64, %edx
	callq	_gpu_write
	movq	%r14, %rdi
	callq	_adreno_is_a530
	testq	%rax, %rax
	je	LBB0_6
## %bb.5:
	movq	_REG_A5XX_CP_MERCIU_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$64, %edx
	callq	_gpu_write
LBB0_6:
	movq	%r14, %rdi
	callq	_adreno_is_a540
	testq	%rax, %rax
	je	LBB0_8
## %bb.7:
	movq	_REG_A5XX_CP_MERCIU_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1024, %edx                     ## imm = 0x400
	callq	_gpu_write
LBB0_8:
	movq	_REG_A5XX_CP_ROQ_THRESHOLDS_2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$-2147483552, %edx              ## imm = 0x80000060
	callq	_gpu_write
	movq	_REG_A5XX_CP_ROQ_THRESHOLDS_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1075845910, %edx               ## imm = 0x40201B16
	callq	_gpu_write
	movq	_REG_A5XX_PC_DBG_ECO_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	movl	$-1071644672, %edx              ## imm = 0xC0200000
	callq	_gpu_write
	movq	8(%r14), %rax
	movq	_ADRENO_QUIRK_TWO_PASS_USE_WFI@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, (%rax)
	je	LBB0_10
## %bb.9:
	movl	(%r15), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	movl	$256, %ecx                      ## imm = 0x100
	callq	_gpu_rmw
LBB0_10:
	movl	(%r15), %esi
	movq	%rbx, %rdi
	movl	$-1071644416, %edx              ## imm = 0xC0200100
	callq	_gpu_write
	movq	_REG_A5XX_CP_CHICKEN_DBG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$33554432, %edx                 ## imm = 0x2000000
	callq	_gpu_write
	movq	_REG_A5XX_RBBM_AHB_CNTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$-1493172225, %edx              ## imm = 0xA6FFFFFF
	callq	_gpu_write
	movq	%rbx, %rdi
	movl	$1, %esi
	callq	_a5xx_set_hwcg
	movq	_REG_A5XX_RBBM_AHB_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$63, %edx
	callq	_gpu_write
	movq	_REG_A5XX_TPL1_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$256, %edx                      ## imm = 0x100
	callq	_gpu_write
	movq	_REG_A5XX_RB_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$4, %edx
	callq	_gpu_write
	movq	%r14, %rdi
	callq	_adreno_is_a540
	testq	%rax, %rax
	je	LBB0_12
## %bb.11:
	movq	_REG_A5XX_UCHE_DBG_ECO_CNTL_2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$2, %edx
	callq	_gpu_write
LBB0_12:
	movq	_REG_A5XX_CP_PROTECT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$7, %edx
	callq	_gpu_write
	xorl	%edi, %edi
	callq	_REG_A5XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$4, %edi
	movl	$4, %esi
	callq	_ADRENO_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$1, %edi
	callq	_REG_A5XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$8, %edi
	movl	$8, %esi
	callq	_ADRENO_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$2, %edi
	callq	_REG_A5XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$16, %edi
	movl	$16, %esi
	callq	_ADRENO_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$3, %edi
	callq	_REG_A5XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$32, %edi
	movl	$32, %esi
	callq	_ADRENO_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$4, %edi
	callq	_REG_A5XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$64, %edi
	movl	$64, %esi
	callq	_ADRENO_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$5, %edi
	callq	_REG_A5XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$128, %edi
	movl	$64, %esi
	callq	_ADRENO_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$6, %edi
	callq	_REG_A5XX_CP_PROTECT
	movl	%eax, %r15d
	movq	_REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movl	$16, %esi
	callq	_ADRENO_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$7, %edi
	callq	_REG_A5XX_CP_PROTECT
	movl	%eax, %r15d
	movq	_REG_A5XX_RBBM_SECVID_TRUST_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	movl	$2, %esi
	callq	_ADRENO_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$8, %edi
	callq	_REG_A5XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$2048, %edi                     ## imm = 0x800
	movl	$64, %esi
	callq	_ADRENO_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$9, %edi
	callq	_REG_A5XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$2112, %edi                     ## imm = 0x840
	movl	$8, %esi
	callq	_ADRENO_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$10, %edi
	callq	_REG_A5XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$2176, %edi                     ## imm = 0x880
	movl	$32, %esi
	callq	_ADRENO_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$11, %edi
	callq	_REG_A5XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$2720, %edi                     ## imm = 0xAA0
	movl	$1, %esi
	callq	_ADRENO_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$12, %edi
	callq	_REG_A5XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$3264, %edi                     ## imm = 0xCC0
	movl	$1, %esi
	callq	_ADRENO_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$13, %edi
	callq	_REG_A5XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$3312, %edi                     ## imm = 0xCF0
	movl	$2, %esi
	callq	_ADRENO_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$14, %edi
	callq	_REG_A5XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$3688, %edi                     ## imm = 0xE68
	movl	$8, %esi
	callq	_ADRENO_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$15, %edi
	callq	_REG_A5XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$3696, %edi                     ## imm = 0xE70
	movl	$4, %esi
	callq	_ADRENO_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$16, %edi
	callq	_REG_A5XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$3712, %edi                     ## imm = 0xE80
	movl	$16, %esi
	callq	_ADRENO_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movq	%r14, %rdi
	callq	_adreno_is_a530
	testq	%rax, %rax
	je	LBB0_14
## %bb.13:
	movl	$17, %edi
	callq	_REG_A5XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$65536, %edi                    ## imm = 0x10000
	movl	$32768, %esi                    ## imm = 0x8000
	callq	_ADRENO_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
LBB0_14:
	movq	_REG_A5XX_RBBM_SECVID_TSB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movl	(%r13), %esi
	movq	_REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	xorl	%ecx, %ecx
	callq	_gpu_write64
	movq	_REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movq	_REG_A5XX_CP_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A5XX_VSC_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A5XX_GRAS_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A5XX_RB_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A5XX_PC_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A5XX_HLSQ_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A5XX_VFD_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A5XX_VPC_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A5XX_UCHE_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A5XX_SP_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A5XX_TPL1_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	8(%r14), %rax
	movq	_ADRENO_QUIRK_LMLOADKILL_DISABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, (%rax)
	je	LBB0_16
## %bb.15:
	movq	_REG_A5XX_VPC_DBG_ECO_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	$23, %edi
	callq	_BIT
	movq	%rbx, %rdi
	movl	%r15d, %esi
	xorl	%edx, %edx
	movl	%eax, %ecx
	callq	_gpu_rmw
	movq	_REG_A5XX_HLSQ_DBG_ECO_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	$18, %edi
	callq	_BIT
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	xorl	%ecx, %ecx
	callq	_gpu_rmw
LBB0_16:
	movq	%rbx, %rdi
	callq	_adreno_hw_init
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	LBB0_29
## %bb.17:
	movq	%rbx, %rdi
	callq	_a5xx_preempt_hw_init
	movq	%rbx, %rdi
	callq	_a5xx_gpmu_ucode_init
	movq	%rbx, %rdi
	callq	_a5xx_ucode_init
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	LBB0_29
## %bb.18:
	movq	_REG_A5XX_RBBM_INT_0_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_A5XX_INT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_gpu_write
	movq	_REG_A5XX_CP_PFP_ME_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movq	%rbx, %rdi
	callq	_a5xx_me_init
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	LBB0_29
## %bb.19:
	movq	%rbx, %rdi
	callq	_a5xx_power_init
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	LBB0_29
## %bb.20:
	movq	%r14, %rdi
	callq	_adreno_is_a530
	testq	%rax, %rax
	je	LBB0_22
## %bb.21:
	movq	8(%rbx), %rax
	movl	(%rax), %edi
	movq	_CP_EVENT_WRITE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %edx
	callq	_OUT_PKT7
	movq	8(%rbx), %rax
	movl	(%rax), %edi
	movl	$15, %esi
	callq	_OUT_RING
	movq	8(%rbx), %rax
	movq	16(%rbx), %rcx
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	*(%rcx)
	movq	8(%rbx), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_a5xx_idle
	testl	%eax, %eax
	je	LBB0_26
LBB0_22:
	movq	%rbx, %rdi
	callq	_a5xx_zap_shader_init
	testl	%eax, %eax
	je	LBB0_24
## %bb.23:
	movq	(%rbx), %rax
	movl	(%rax), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_warn_once
	movl	(%r12), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	jmp	LBB0_25
LBB0_24:
	movq	8(%rbx), %rax
	movl	(%rax), %edi
	movq	_CP_SET_SECURE_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %edx
	callq	_OUT_PKT7
	movq	8(%rbx), %rax
	movl	(%rax), %edi
	xorl	%r15d, %r15d
	xorl	%esi, %esi
	callq	_OUT_RING
	movq	8(%rbx), %rax
	movq	16(%rbx), %rcx
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	*(%rcx)
	movq	8(%rbx), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_a5xx_idle
	testl	%eax, %eax
	je	LBB0_27
LBB0_25:
	movq	%rbx, %rdi
	callq	_a5xx_preempt_start
	xorl	%r15d, %r15d
	jmp	LBB0_29
LBB0_26:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r15d, %r15d
	jmp	LBB0_28
LBB0_27:
	movq	_EINVAL@GOTPCREL(%rip), %rax
LBB0_28:
	subl	(%rax), %r15d
LBB0_29:
	movl	%r15d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB,4,2 ## @REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB
	.comm	_REG_A5XX_VBIF_GATE_OFF_WRREQ_EN,4,2 ## @REG_A5XX_VBIF_GATE_OFF_WRREQ_EN
	.comm	_REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED,4,2 ## @REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED
	.comm	_REG_A5XX_RBBM_AHB_CNTL0,4,2    ## @REG_A5XX_RBBM_AHB_CNTL0
	.comm	_ADRENO_QUIRK_FAULT_DETECT_MASK,4,2 ## @ADRENO_QUIRK_FAULT_DETECT_MASK
	.comm	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11,4,2 ## @REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11
	.comm	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12,4,2 ## @REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12
	.comm	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13,4,2 ## @REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13
	.comm	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14,4,2 ## @REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14
	.comm	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15,4,2 ## @REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15
	.comm	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16,4,2 ## @REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16
	.comm	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17,4,2 ## @REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17
	.comm	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18,4,2 ## @REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18
	.comm	_REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL,4,2 ## @REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL
	.comm	_REG_A5XX_RBBM_PERFCTR_CNTL,4,2 ## @REG_A5XX_RBBM_PERFCTR_CNTL
	.comm	_REG_A5XX_CP_PERFCTR_CP_SEL_0,4,2 ## @REG_A5XX_CP_PERFCTR_CP_SEL_0
	.comm	_PERF_CP_ALWAYS_COUNT,4,2       ## @PERF_CP_ALWAYS_COUNT
	.comm	_REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0,4,2 ## @REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0
	.comm	_REG_A5XX_UCHE_CACHE_WAYS,4,2   ## @REG_A5XX_UCHE_CACHE_WAYS
	.comm	_REG_A5XX_UCHE_TRAP_BASE_LO,4,2 ## @REG_A5XX_UCHE_TRAP_BASE_LO
	.comm	_REG_A5XX_UCHE_TRAP_BASE_HI,4,2 ## @REG_A5XX_UCHE_TRAP_BASE_HI
	.comm	_REG_A5XX_UCHE_WRITE_THRU_BASE_LO,4,2 ## @REG_A5XX_UCHE_WRITE_THRU_BASE_LO
	.comm	_REG_A5XX_UCHE_WRITE_THRU_BASE_HI,4,2 ## @REG_A5XX_UCHE_WRITE_THRU_BASE_HI
	.comm	_REG_A5XX_UCHE_GMEM_RANGE_MIN_LO,4,2 ## @REG_A5XX_UCHE_GMEM_RANGE_MIN_LO
	.comm	_REG_A5XX_UCHE_GMEM_RANGE_MIN_HI,4,2 ## @REG_A5XX_UCHE_GMEM_RANGE_MIN_HI
	.comm	_REG_A5XX_UCHE_GMEM_RANGE_MAX_LO,4,2 ## @REG_A5XX_UCHE_GMEM_RANGE_MAX_LO
	.comm	_REG_A5XX_UCHE_GMEM_RANGE_MAX_HI,4,2 ## @REG_A5XX_UCHE_GMEM_RANGE_MAX_HI
	.comm	_REG_A5XX_CP_MEQ_THRESHOLDS,4,2 ## @REG_A5XX_CP_MEQ_THRESHOLDS
	.comm	_REG_A5XX_CP_MERCIU_SIZE,4,2    ## @REG_A5XX_CP_MERCIU_SIZE
	.comm	_REG_A5XX_CP_ROQ_THRESHOLDS_2,4,2 ## @REG_A5XX_CP_ROQ_THRESHOLDS_2
	.comm	_REG_A5XX_CP_ROQ_THRESHOLDS_1,4,2 ## @REG_A5XX_CP_ROQ_THRESHOLDS_1
	.comm	_REG_A5XX_PC_DBG_ECO_CNTL,4,2   ## @REG_A5XX_PC_DBG_ECO_CNTL
	.comm	_ADRENO_QUIRK_TWO_PASS_USE_WFI,4,2 ## @ADRENO_QUIRK_TWO_PASS_USE_WFI
	.comm	_REG_A5XX_CP_CHICKEN_DBG,4,2    ## @REG_A5XX_CP_CHICKEN_DBG
	.comm	_REG_A5XX_RBBM_AHB_CNTL1,4,2    ## @REG_A5XX_RBBM_AHB_CNTL1
	.comm	_REG_A5XX_RBBM_AHB_CNTL2,4,2    ## @REG_A5XX_RBBM_AHB_CNTL2
	.comm	_REG_A5XX_TPL1_MODE_CNTL,4,2    ## @REG_A5XX_TPL1_MODE_CNTL
	.comm	_REG_A5XX_RB_MODE_CNTL,4,2      ## @REG_A5XX_RB_MODE_CNTL
	.comm	_REG_A5XX_UCHE_DBG_ECO_CNTL_2,4,2 ## @REG_A5XX_UCHE_DBG_ECO_CNTL_2
	.comm	_REG_A5XX_CP_PROTECT_CNTL,4,2   ## @REG_A5XX_CP_PROTECT_CNTL
	.comm	_REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO,4,2 ## @REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO
	.comm	_REG_A5XX_RBBM_SECVID_TRUST_CNTL,4,2 ## @REG_A5XX_RBBM_SECVID_TRUST_CNTL
	.comm	_REG_A5XX_RBBM_SECVID_TSB_CNTL,4,2 ## @REG_A5XX_RBBM_SECVID_TSB_CNTL
	.comm	_REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI,4,2 ## @REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI
	.comm	_REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE,4,2 ## @REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE
	.comm	_REG_A5XX_CP_ADDR_MODE_CNTL,4,2 ## @REG_A5XX_CP_ADDR_MODE_CNTL
	.comm	_REG_A5XX_VSC_ADDR_MODE_CNTL,4,2 ## @REG_A5XX_VSC_ADDR_MODE_CNTL
	.comm	_REG_A5XX_GRAS_ADDR_MODE_CNTL,4,2 ## @REG_A5XX_GRAS_ADDR_MODE_CNTL
	.comm	_REG_A5XX_RB_ADDR_MODE_CNTL,4,2 ## @REG_A5XX_RB_ADDR_MODE_CNTL
	.comm	_REG_A5XX_PC_ADDR_MODE_CNTL,4,2 ## @REG_A5XX_PC_ADDR_MODE_CNTL
	.comm	_REG_A5XX_HLSQ_ADDR_MODE_CNTL,4,2 ## @REG_A5XX_HLSQ_ADDR_MODE_CNTL
	.comm	_REG_A5XX_VFD_ADDR_MODE_CNTL,4,2 ## @REG_A5XX_VFD_ADDR_MODE_CNTL
	.comm	_REG_A5XX_VPC_ADDR_MODE_CNTL,4,2 ## @REG_A5XX_VPC_ADDR_MODE_CNTL
	.comm	_REG_A5XX_UCHE_ADDR_MODE_CNTL,4,2 ## @REG_A5XX_UCHE_ADDR_MODE_CNTL
	.comm	_REG_A5XX_SP_ADDR_MODE_CNTL,4,2 ## @REG_A5XX_SP_ADDR_MODE_CNTL
	.comm	_REG_A5XX_TPL1_ADDR_MODE_CNTL,4,2 ## @REG_A5XX_TPL1_ADDR_MODE_CNTL
	.comm	_REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL,4,2 ## @REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL
	.comm	_ADRENO_QUIRK_LMLOADKILL_DISABLE,4,2 ## @ADRENO_QUIRK_LMLOADKILL_DISABLE
	.comm	_REG_A5XX_VPC_DBG_ECO_CNTL,4,2  ## @REG_A5XX_VPC_DBG_ECO_CNTL
	.comm	_REG_A5XX_HLSQ_DBG_ECO_CNTL,4,2 ## @REG_A5XX_HLSQ_DBG_ECO_CNTL
	.comm	_REG_A5XX_RBBM_INT_0_MASK,4,2   ## @REG_A5XX_RBBM_INT_0_MASK
	.comm	_A5XX_INT_MASK,4,2              ## @A5XX_INT_MASK
	.comm	_REG_A5XX_CP_PFP_ME_CNTL,4,2    ## @REG_A5XX_CP_PFP_ME_CNTL
	.comm	_CP_EVENT_WRITE,4,2             ## @CP_EVENT_WRITE
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_CP_SET_SECURE_MODE,4,2         ## @CP_SET_SECURE_MODE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"

	.no_dead_strip	_a5xx_hw_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function a5xx_hw_init
_a5xx_hw_init:                          ; @a5xx_hw_init
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	bl	_to_adreno_gpu
	mov	x20, x0
Lloh0:
	adrp	x8, _REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB@GOTPAGE
Lloh1:
	ldr	x8, [x8, _REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #3
	bl	_gpu_write
	mov	x0, x20
	bl	_adreno_is_a540
	cbz	x0, LBB0_2
; %bb.1:
Lloh3:
	adrp	x8, _REG_A5XX_VBIF_GATE_OFF_WRREQ_EN@GOTPAGE
Lloh4:
	ldr	x8, [x8, _REG_A5XX_VBIF_GATE_OFF_WRREQ_EN@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #9
	bl	_gpu_write
LBB0_2:
Lloh6:
	adrp	x8, _REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED@GOTPAGE
Lloh7:
	ldr	x8, [x8, _REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1
	bl	_gpu_write
Lloh9:
	adrp	x8, _REG_A5XX_RBBM_AHB_CNTL0@GOTPAGE
Lloh10:
	ldr	x8, [x8, _REG_A5XX_RBBM_AHB_CNTL0@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
	ldr	x8, [x20, #8]
	ldr	w8, [x8]
Lloh12:
	adrp	x9, _ADRENO_QUIRK_FAULT_DETECT_MASK@GOTPAGE
Lloh13:
	ldr	x9, [x9, _ADRENO_QUIRK_FAULT_DETECT_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_4
; %bb.3:
Lloh15:
	adrp	x8, _REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11@GOTPAGE
Lloh16:
	ldr	x8, [x8, _REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-268435456
	bl	_gpu_write
Lloh18:
	adrp	x8, _REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12@GOTPAGE
Lloh19:
	ldr	x8, [x8, _REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1
	bl	_gpu_write
Lloh21:
	adrp	x8, _REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13@GOTPAGE
Lloh22:
	ldr	x8, [x8, _REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1
	bl	_gpu_write
Lloh24:
	adrp	x8, _REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14@GOTPAGE
Lloh25:
	ldr	x8, [x8, _REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1
	bl	_gpu_write
Lloh27:
	adrp	x8, _REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15@GOTPAGE
Lloh28:
	ldr	x8, [x8, _REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1
	bl	_gpu_write
Lloh30:
	adrp	x8, _REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16@GOTPAGE
Lloh31:
	ldr	x8, [x8, _REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1
	bl	_gpu_write
Lloh33:
	adrp	x8, _REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17@GOTPAGE
Lloh34:
	ldr	x8, [x8, _REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17@GOTPAGEOFF]
Lloh35:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1
	bl	_gpu_write
Lloh36:
	adrp	x8, _REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18@GOTPAGE
Lloh37:
	ldr	x8, [x8, _REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1
	bl	_gpu_write
LBB0_4:
Lloh39:
	adrp	x8, _REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL@GOTPAGE
Lloh40:
	ldr	x8, [x8, _REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1073807359
	bl	_gpu_write
Lloh42:
	adrp	x8, _REG_A5XX_RBBM_PERFCTR_CNTL@GOTPAGE
Lloh43:
	ldr	x8, [x8, _REG_A5XX_RBBM_PERFCTR_CNTL@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
Lloh45:
	adrp	x8, _REG_A5XX_CP_PERFCTR_CP_SEL_0@GOTPAGE
Lloh46:
	ldr	x8, [x8, _REG_A5XX_CP_PERFCTR_CP_SEL_0@GOTPAGEOFF]
Lloh47:
	ldr	w1, [x8]
Lloh48:
	adrp	x8, _PERF_CP_ALWAYS_COUNT@GOTPAGE
Lloh49:
	ldr	x8, [x8, _PERF_CP_ALWAYS_COUNT@GOTPAGEOFF]
Lloh50:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_gpu_write
Lloh51:
	adrp	x8, _REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0@GOTPAGE
Lloh52:
	ldr	x8, [x8, _REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0@GOTPAGEOFF]
Lloh53:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #6
	bl	_gpu_write
Lloh54:
	adrp	x8, _REG_A5XX_UCHE_CACHE_WAYS@GOTPAGE
Lloh55:
	ldr	x8, [x8, _REG_A5XX_UCHE_CACHE_WAYS@GOTPAGEOFF]
Lloh56:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #2
	bl	_gpu_write
Lloh57:
	adrp	x8, _REG_A5XX_UCHE_TRAP_BASE_LO@GOTPAGE
Lloh58:
	ldr	x8, [x8, _REG_A5XX_UCHE_TRAP_BASE_LO@GOTPAGEOFF]
Lloh59:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-65536
	bl	_gpu_write
Lloh60:
	adrp	x8, _REG_A5XX_UCHE_TRAP_BASE_HI@GOTPAGE
Lloh61:
	ldr	x8, [x8, _REG_A5XX_UCHE_TRAP_BASE_HI@GOTPAGEOFF]
Lloh62:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #131071
	bl	_gpu_write
Lloh63:
	adrp	x8, _REG_A5XX_UCHE_WRITE_THRU_BASE_LO@GOTPAGE
Lloh64:
	ldr	x8, [x8, _REG_A5XX_UCHE_WRITE_THRU_BASE_LO@GOTPAGEOFF]
Lloh65:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-65536
	bl	_gpu_write
Lloh66:
	adrp	x8, _REG_A5XX_UCHE_WRITE_THRU_BASE_HI@GOTPAGE
Lloh67:
	ldr	x8, [x8, _REG_A5XX_UCHE_WRITE_THRU_BASE_HI@GOTPAGEOFF]
Lloh68:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #131071
	bl	_gpu_write
Lloh69:
	adrp	x8, _REG_A5XX_UCHE_GMEM_RANGE_MIN_LO@GOTPAGE
Lloh70:
	ldr	x8, [x8, _REG_A5XX_UCHE_GMEM_RANGE_MIN_LO@GOTPAGEOFF]
Lloh71:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1048576
	bl	_gpu_write
Lloh72:
	adrp	x8, _REG_A5XX_UCHE_GMEM_RANGE_MIN_HI@GOTPAGE
Lloh73:
	ldr	x8, [x8, _REG_A5XX_UCHE_GMEM_RANGE_MIN_HI@GOTPAGEOFF]
Lloh74:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
Lloh75:
	adrp	x8, _REG_A5XX_UCHE_GMEM_RANGE_MAX_LO@GOTPAGE
Lloh76:
	ldr	x8, [x8, _REG_A5XX_UCHE_GMEM_RANGE_MAX_LO@GOTPAGEOFF]
Lloh77:
	ldr	w1, [x8]
	ldr	w8, [x20]
	mov	w9, #1048575
	add	w2, w8, w9
	mov	x0, x19
	bl	_gpu_write
Lloh78:
	adrp	x8, _REG_A5XX_UCHE_GMEM_RANGE_MAX_HI@GOTPAGE
Lloh79:
	ldr	x8, [x8, _REG_A5XX_UCHE_GMEM_RANGE_MAX_HI@GOTPAGEOFF]
Lloh80:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
Lloh81:
	adrp	x8, _REG_A5XX_CP_MEQ_THRESHOLDS@GOTPAGE
Lloh82:
	ldr	x8, [x8, _REG_A5XX_CP_MEQ_THRESHOLDS@GOTPAGEOFF]
Lloh83:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #64
	bl	_gpu_write
	mov	x0, x20
	bl	_adreno_is_a530
Lloh84:
	adrp	x21, _REG_A5XX_CP_MERCIU_SIZE@GOTPAGE
Lloh85:
	ldr	x21, [x21, _REG_A5XX_CP_MERCIU_SIZE@GOTPAGEOFF]
	cbz	x0, LBB0_6
; %bb.5:
	ldr	w1, [x21]
	mov	x0, x19
	mov	w2, #64
	bl	_gpu_write
LBB0_6:
	mov	x0, x20
	bl	_adreno_is_a540
	cbz	x0, LBB0_8
; %bb.7:
	ldr	w1, [x21]
	mov	x0, x19
	mov	w2, #1024
	bl	_gpu_write
LBB0_8:
	mov	w21, #-1071644672
Lloh86:
	adrp	x8, _REG_A5XX_CP_ROQ_THRESHOLDS_2@GOTPAGE
Lloh87:
	ldr	x8, [x8, _REG_A5XX_CP_ROQ_THRESHOLDS_2@GOTPAGEOFF]
Lloh88:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #96
	movk	w2, #32768, lsl #16
	bl	_gpu_write
Lloh89:
	adrp	x8, _REG_A5XX_CP_ROQ_THRESHOLDS_1@GOTPAGE
Lloh90:
	ldr	x8, [x8, _REG_A5XX_CP_ROQ_THRESHOLDS_1@GOTPAGEOFF]
Lloh91:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #6934
	movk	w2, #16416, lsl #16
	bl	_gpu_write
Lloh92:
	adrp	x22, _REG_A5XX_PC_DBG_ECO_CNTL@GOTPAGE
Lloh93:
	ldr	x22, [x22, _REG_A5XX_PC_DBG_ECO_CNTL@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x19
	mov	w2, #-1071644672
	bl	_gpu_write
	ldr	x8, [x20, #8]
	ldr	w8, [x8]
Lloh94:
	adrp	x9, _ADRENO_QUIRK_TWO_PASS_USE_WFI@GOTPAGE
Lloh95:
	ldr	x9, [x9, _ADRENO_QUIRK_TWO_PASS_USE_WFI@GOTPAGEOFF]
Lloh96:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_10
; %bb.9:
	ldr	w1, [x22]
	mov	x0, x19
	mov	w2, #0
	mov	w3, #256
	bl	_gpu_rmw
LBB0_10:
	ldr	w1, [x22]
	add	w2, w21, #256
	mov	x0, x19
	bl	_gpu_write
Lloh97:
	adrp	x8, _REG_A5XX_CP_CHICKEN_DBG@GOTPAGE
Lloh98:
	ldr	x8, [x8, _REG_A5XX_CP_CHICKEN_DBG@GOTPAGEOFF]
Lloh99:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #33554432
	bl	_gpu_write
Lloh100:
	adrp	x8, _REG_A5XX_RBBM_AHB_CNTL1@GOTPAGE
Lloh101:
	ldr	x8, [x8, _REG_A5XX_RBBM_AHB_CNTL1@GOTPAGEOFF]
Lloh102:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1493172225
	bl	_gpu_write
	mov	x0, x19
	mov	w1, #1
	bl	_a5xx_set_hwcg
Lloh103:
	adrp	x8, _REG_A5XX_RBBM_AHB_CNTL2@GOTPAGE
Lloh104:
	ldr	x8, [x8, _REG_A5XX_RBBM_AHB_CNTL2@GOTPAGEOFF]
Lloh105:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #63
	bl	_gpu_write
Lloh106:
	adrp	x8, _REG_A5XX_TPL1_MODE_CNTL@GOTPAGE
Lloh107:
	ldr	x8, [x8, _REG_A5XX_TPL1_MODE_CNTL@GOTPAGEOFF]
Lloh108:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #256
	bl	_gpu_write
Lloh109:
	adrp	x8, _REG_A5XX_RB_MODE_CNTL@GOTPAGE
Lloh110:
	ldr	x8, [x8, _REG_A5XX_RB_MODE_CNTL@GOTPAGEOFF]
Lloh111:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #4
	bl	_gpu_write
	mov	x0, x20
	bl	_adreno_is_a540
	cbz	x0, LBB0_12
; %bb.11:
Lloh112:
	adrp	x8, _REG_A5XX_UCHE_DBG_ECO_CNTL_2@GOTPAGE
Lloh113:
	ldr	x8, [x8, _REG_A5XX_UCHE_DBG_ECO_CNTL_2@GOTPAGEOFF]
Lloh114:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #2
	bl	_gpu_write
LBB0_12:
Lloh115:
	adrp	x8, _REG_A5XX_CP_PROTECT_CNTL@GOTPAGE
Lloh116:
	ldr	x8, [x8, _REG_A5XX_CP_PROTECT_CNTL@GOTPAGEOFF]
Lloh117:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #7
	bl	_gpu_write
	mov	w0, #0
	bl	_REG_A5XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #4
	mov	w1, #4
	bl	_ADRENO_PROTECT_RW
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #1
	bl	_REG_A5XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #8
	mov	w1, #8
	bl	_ADRENO_PROTECT_RW
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #2
	bl	_REG_A5XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #16
	mov	w1, #16
	bl	_ADRENO_PROTECT_RW
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #3
	bl	_REG_A5XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #32
	mov	w1, #32
	bl	_ADRENO_PROTECT_RW
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #4
	bl	_REG_A5XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #64
	mov	w1, #64
	bl	_ADRENO_PROTECT_RW
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #5
	bl	_REG_A5XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #128
	mov	w1, #64
	bl	_ADRENO_PROTECT_RW
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #6
	bl	_REG_A5XX_CP_PROTECT
	mov	x21, x0
Lloh118:
	adrp	x23, _REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO@GOTPAGE
Lloh119:
	ldr	x23, [x23, _REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO@GOTPAGEOFF]
	ldr	w0, [x23]
	mov	w1, #16
	bl	_ADRENO_PROTECT_RW
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #7
	bl	_REG_A5XX_CP_PROTECT
	mov	x21, x0
Lloh120:
	adrp	x22, _REG_A5XX_RBBM_SECVID_TRUST_CNTL@GOTPAGE
Lloh121:
	ldr	x22, [x22, _REG_A5XX_RBBM_SECVID_TRUST_CNTL@GOTPAGEOFF]
	ldr	w0, [x22]
	mov	w1, #2
	bl	_ADRENO_PROTECT_RW
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #8
	bl	_REG_A5XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #2048
	mov	w1, #64
	bl	_ADRENO_PROTECT_RW
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #9
	bl	_REG_A5XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #2112
	mov	w1, #8
	bl	_ADRENO_PROTECT_RW
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #10
	bl	_REG_A5XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #2176
	mov	w1, #32
	bl	_ADRENO_PROTECT_RW
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #11
	bl	_REG_A5XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #2720
	mov	w1, #1
	bl	_ADRENO_PROTECT_RW
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #12
	bl	_REG_A5XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #3264
	mov	w1, #1
	bl	_ADRENO_PROTECT_RW
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #13
	bl	_REG_A5XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #3312
	mov	w1, #2
	bl	_ADRENO_PROTECT_RW
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #14
	bl	_REG_A5XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #3688
	mov	w1, #8
	bl	_ADRENO_PROTECT_RW
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #15
	bl	_REG_A5XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #3696
	mov	w1, #4
	bl	_ADRENO_PROTECT_RW
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #16
	bl	_REG_A5XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #3712
	mov	w1, #16
	bl	_ADRENO_PROTECT_RW
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
	mov	x0, x20
	bl	_adreno_is_a530
	cbz	x0, LBB0_14
; %bb.13:
	mov	w0, #17
	bl	_REG_A5XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #65536
	mov	w1, #32768
	bl	_ADRENO_PROTECT_RW
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
LBB0_14:
Lloh122:
	adrp	x8, _REG_A5XX_RBBM_SECVID_TSB_CNTL@GOTPAGE
Lloh123:
	ldr	x8, [x8, _REG_A5XX_RBBM_SECVID_TSB_CNTL@GOTPAGEOFF]
Lloh124:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
	ldr	w1, [x23]
Lloh125:
	adrp	x8, _REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI@GOTPAGE
Lloh126:
	ldr	x8, [x8, _REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI@GOTPAGEOFF]
Lloh127:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #0
	bl	_gpu_write64
Lloh128:
	adrp	x8, _REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE@GOTPAGE
Lloh129:
	ldr	x8, [x8, _REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE@GOTPAGEOFF]
Lloh130:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
Lloh131:
	adrp	x8, _REG_A5XX_CP_ADDR_MODE_CNTL@GOTPAGE
Lloh132:
	ldr	x8, [x8, _REG_A5XX_CP_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh133:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
Lloh134:
	adrp	x8, _REG_A5XX_VSC_ADDR_MODE_CNTL@GOTPAGE
Lloh135:
	ldr	x8, [x8, _REG_A5XX_VSC_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh136:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
Lloh137:
	adrp	x8, _REG_A5XX_GRAS_ADDR_MODE_CNTL@GOTPAGE
Lloh138:
	ldr	x8, [x8, _REG_A5XX_GRAS_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh139:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
Lloh140:
	adrp	x8, _REG_A5XX_RB_ADDR_MODE_CNTL@GOTPAGE
Lloh141:
	ldr	x8, [x8, _REG_A5XX_RB_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh142:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
Lloh143:
	adrp	x8, _REG_A5XX_PC_ADDR_MODE_CNTL@GOTPAGE
Lloh144:
	ldr	x8, [x8, _REG_A5XX_PC_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh145:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
Lloh146:
	adrp	x8, _REG_A5XX_HLSQ_ADDR_MODE_CNTL@GOTPAGE
Lloh147:
	ldr	x8, [x8, _REG_A5XX_HLSQ_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh148:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
Lloh149:
	adrp	x8, _REG_A5XX_VFD_ADDR_MODE_CNTL@GOTPAGE
Lloh150:
	ldr	x8, [x8, _REG_A5XX_VFD_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh151:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
Lloh152:
	adrp	x8, _REG_A5XX_VPC_ADDR_MODE_CNTL@GOTPAGE
Lloh153:
	ldr	x8, [x8, _REG_A5XX_VPC_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh154:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
Lloh155:
	adrp	x8, _REG_A5XX_UCHE_ADDR_MODE_CNTL@GOTPAGE
Lloh156:
	ldr	x8, [x8, _REG_A5XX_UCHE_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh157:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
Lloh158:
	adrp	x8, _REG_A5XX_SP_ADDR_MODE_CNTL@GOTPAGE
Lloh159:
	ldr	x8, [x8, _REG_A5XX_SP_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh160:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
Lloh161:
	adrp	x8, _REG_A5XX_TPL1_ADDR_MODE_CNTL@GOTPAGE
Lloh162:
	ldr	x8, [x8, _REG_A5XX_TPL1_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh163:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
Lloh164:
	adrp	x8, _REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL@GOTPAGE
Lloh165:
	ldr	x8, [x8, _REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh166:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
	ldr	x8, [x20, #8]
	ldr	w8, [x8]
Lloh167:
	adrp	x9, _ADRENO_QUIRK_LMLOADKILL_DISABLE@GOTPAGE
Lloh168:
	ldr	x9, [x9, _ADRENO_QUIRK_LMLOADKILL_DISABLE@GOTPAGEOFF]
Lloh169:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_16
; %bb.15:
Lloh170:
	adrp	x8, _REG_A5XX_VPC_DBG_ECO_CNTL@GOTPAGE
Lloh171:
	ldr	x8, [x8, _REG_A5XX_VPC_DBG_ECO_CNTL@GOTPAGEOFF]
Lloh172:
	ldr	w21, [x8]
	mov	w0, #23
	bl	_BIT
	mov	x3, x0
	mov	x0, x19
	mov	x1, x21
	mov	w2, #0
	bl	_gpu_rmw
Lloh173:
	adrp	x8, _REG_A5XX_HLSQ_DBG_ECO_CNTL@GOTPAGE
Lloh174:
	ldr	x8, [x8, _REG_A5XX_HLSQ_DBG_ECO_CNTL@GOTPAGEOFF]
Lloh175:
	ldr	w21, [x8]
	mov	w0, #18
	bl	_BIT
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	mov	w3, #0
	bl	_gpu_rmw
LBB0_16:
	mov	x0, x19
	bl	_adreno_hw_init
	cbnz	w0, LBB0_27
; %bb.17:
	mov	x0, x19
	bl	_a5xx_preempt_hw_init
	mov	x0, x19
	bl	_a5xx_gpmu_ucode_init
	mov	x0, x19
	bl	_a5xx_ucode_init
	cbnz	w0, LBB0_27
; %bb.18:
Lloh176:
	adrp	x8, _REG_A5XX_RBBM_INT_0_MASK@GOTPAGE
Lloh177:
	ldr	x8, [x8, _REG_A5XX_RBBM_INT_0_MASK@GOTPAGEOFF]
Lloh178:
	ldr	w1, [x8]
Lloh179:
	adrp	x8, _A5XX_INT_MASK@GOTPAGE
Lloh180:
	ldr	x8, [x8, _A5XX_INT_MASK@GOTPAGEOFF]
Lloh181:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_gpu_write
Lloh182:
	adrp	x8, _REG_A5XX_CP_PFP_ME_CNTL@GOTPAGE
Lloh183:
	ldr	x8, [x8, _REG_A5XX_CP_PFP_ME_CNTL@GOTPAGEOFF]
Lloh184:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
	mov	x0, x19
	bl	_a5xx_me_init
	cbnz	w0, LBB0_27
; %bb.19:
	mov	x0, x19
	bl	_a5xx_power_init
	cbnz	w0, LBB0_27
; %bb.20:
	mov	x0, x20
	bl	_adreno_is_a530
	cbz	x0, LBB0_22
; %bb.21:
	ldr	x8, [x19, #8]
	ldr	w0, [x8]
Lloh185:
	adrp	x8, _CP_EVENT_WRITE@GOTPAGE
Lloh186:
	ldr	x8, [x8, _CP_EVENT_WRITE@GOTPAGEOFF]
Lloh187:
	ldr	w1, [x8]
	mov	w2, #1
	bl	_OUT_PKT7
	ldr	x8, [x19, #8]
	ldr	w0, [x8]
	mov	w1, #15
	bl	_OUT_RING
	ldp	x9, x8, [x19, #8]
	ldr	x8, [x8]
	ldr	w1, [x9]
	mov	x0, x19
	blr	x8
	ldr	x8, [x19, #8]
	ldr	w1, [x8]
	mov	x0, x19
	bl	_a5xx_idle
	cbz	w0, LBB0_26
LBB0_22:
	mov	x0, x19
	bl	_a5xx_zap_shader_init
	cbz	w0, LBB0_24
; %bb.23:
	ldr	x8, [x19]
	ldr	w0, [x8]
Lloh188:
	adrp	x1, l_.str@PAGE
Lloh189:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_warn_once
	ldr	w1, [x22]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
	b	LBB0_25
LBB0_24:
	ldr	x8, [x19, #8]
	ldr	w0, [x8]
Lloh190:
	adrp	x8, _CP_SET_SECURE_MODE@GOTPAGE
Lloh191:
	ldr	x8, [x8, _CP_SET_SECURE_MODE@GOTPAGEOFF]
Lloh192:
	ldr	w1, [x8]
	mov	w2, #1
	bl	_OUT_PKT7
	ldr	x8, [x19, #8]
	ldr	w0, [x8]
	mov	w1, #0
	bl	_OUT_RING
	ldp	x9, x8, [x19, #8]
	ldr	x8, [x8]
	ldr	w1, [x9]
	mov	x0, x19
	blr	x8
	ldr	x8, [x19, #8]
	ldr	w1, [x8]
	mov	x0, x19
	bl	_a5xx_idle
	cbz	w0, LBB0_26
LBB0_25:
	mov	x0, x19
	bl	_a5xx_preempt_start
	mov	w0, #0
	b	LBB0_27
LBB0_26:
Lloh193:
	adrp	x8, _EINVAL@GOTPAGE
Lloh194:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh195:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_27:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGot	Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh112, Lloh113, Lloh114
	.loh AdrpLdrGot	Lloh120, Lloh121
	.loh AdrpLdrGot	Lloh118, Lloh119
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.loh AdrpLdrGotLdr	Lloh167, Lloh168, Lloh169
	.loh AdrpLdrGotLdr	Lloh164, Lloh165, Lloh166
	.loh AdrpLdrGotLdr	Lloh161, Lloh162, Lloh163
	.loh AdrpLdrGotLdr	Lloh158, Lloh159, Lloh160
	.loh AdrpLdrGotLdr	Lloh155, Lloh156, Lloh157
	.loh AdrpLdrGotLdr	Lloh152, Lloh153, Lloh154
	.loh AdrpLdrGotLdr	Lloh149, Lloh150, Lloh151
	.loh AdrpLdrGotLdr	Lloh146, Lloh147, Lloh148
	.loh AdrpLdrGotLdr	Lloh143, Lloh144, Lloh145
	.loh AdrpLdrGotLdr	Lloh140, Lloh141, Lloh142
	.loh AdrpLdrGotLdr	Lloh137, Lloh138, Lloh139
	.loh AdrpLdrGotLdr	Lloh134, Lloh135, Lloh136
	.loh AdrpLdrGotLdr	Lloh131, Lloh132, Lloh133
	.loh AdrpLdrGotLdr	Lloh128, Lloh129, Lloh130
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh173, Lloh174, Lloh175
	.loh AdrpLdrGotLdr	Lloh170, Lloh171, Lloh172
	.loh AdrpLdrGotLdr	Lloh182, Lloh183, Lloh184
	.loh AdrpLdrGotLdr	Lloh179, Lloh180, Lloh181
	.loh AdrpLdrGotLdr	Lloh176, Lloh177, Lloh178
	.loh AdrpLdrGotLdr	Lloh185, Lloh186, Lloh187
	.loh AdrpAdd	Lloh188, Lloh189
	.loh AdrpLdrGotLdr	Lloh190, Lloh191, Lloh192
	.loh AdrpLdrGotLdr	Lloh193, Lloh194, Lloh195
	.cfi_endproc
                                        ; -- End function
	.comm	_REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB,4,2 ; @REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB
	.comm	_REG_A5XX_VBIF_GATE_OFF_WRREQ_EN,4,2 ; @REG_A5XX_VBIF_GATE_OFF_WRREQ_EN
	.comm	_REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED,4,2 ; @REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED
	.comm	_REG_A5XX_RBBM_AHB_CNTL0,4,2    ; @REG_A5XX_RBBM_AHB_CNTL0
	.comm	_ADRENO_QUIRK_FAULT_DETECT_MASK,4,2 ; @ADRENO_QUIRK_FAULT_DETECT_MASK
	.comm	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11,4,2 ; @REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11
	.comm	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12,4,2 ; @REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12
	.comm	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13,4,2 ; @REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13
	.comm	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14,4,2 ; @REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14
	.comm	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15,4,2 ; @REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15
	.comm	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16,4,2 ; @REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16
	.comm	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17,4,2 ; @REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17
	.comm	_REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18,4,2 ; @REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18
	.comm	_REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL,4,2 ; @REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL
	.comm	_REG_A5XX_RBBM_PERFCTR_CNTL,4,2 ; @REG_A5XX_RBBM_PERFCTR_CNTL
	.comm	_REG_A5XX_CP_PERFCTR_CP_SEL_0,4,2 ; @REG_A5XX_CP_PERFCTR_CP_SEL_0
	.comm	_PERF_CP_ALWAYS_COUNT,4,2       ; @PERF_CP_ALWAYS_COUNT
	.comm	_REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0,4,2 ; @REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0
	.comm	_REG_A5XX_UCHE_CACHE_WAYS,4,2   ; @REG_A5XX_UCHE_CACHE_WAYS
	.comm	_REG_A5XX_UCHE_TRAP_BASE_LO,4,2 ; @REG_A5XX_UCHE_TRAP_BASE_LO
	.comm	_REG_A5XX_UCHE_TRAP_BASE_HI,4,2 ; @REG_A5XX_UCHE_TRAP_BASE_HI
	.comm	_REG_A5XX_UCHE_WRITE_THRU_BASE_LO,4,2 ; @REG_A5XX_UCHE_WRITE_THRU_BASE_LO
	.comm	_REG_A5XX_UCHE_WRITE_THRU_BASE_HI,4,2 ; @REG_A5XX_UCHE_WRITE_THRU_BASE_HI
	.comm	_REG_A5XX_UCHE_GMEM_RANGE_MIN_LO,4,2 ; @REG_A5XX_UCHE_GMEM_RANGE_MIN_LO
	.comm	_REG_A5XX_UCHE_GMEM_RANGE_MIN_HI,4,2 ; @REG_A5XX_UCHE_GMEM_RANGE_MIN_HI
	.comm	_REG_A5XX_UCHE_GMEM_RANGE_MAX_LO,4,2 ; @REG_A5XX_UCHE_GMEM_RANGE_MAX_LO
	.comm	_REG_A5XX_UCHE_GMEM_RANGE_MAX_HI,4,2 ; @REG_A5XX_UCHE_GMEM_RANGE_MAX_HI
	.comm	_REG_A5XX_CP_MEQ_THRESHOLDS,4,2 ; @REG_A5XX_CP_MEQ_THRESHOLDS
	.comm	_REG_A5XX_CP_MERCIU_SIZE,4,2    ; @REG_A5XX_CP_MERCIU_SIZE
	.comm	_REG_A5XX_CP_ROQ_THRESHOLDS_2,4,2 ; @REG_A5XX_CP_ROQ_THRESHOLDS_2
	.comm	_REG_A5XX_CP_ROQ_THRESHOLDS_1,4,2 ; @REG_A5XX_CP_ROQ_THRESHOLDS_1
	.comm	_REG_A5XX_PC_DBG_ECO_CNTL,4,2   ; @REG_A5XX_PC_DBG_ECO_CNTL
	.comm	_ADRENO_QUIRK_TWO_PASS_USE_WFI,4,2 ; @ADRENO_QUIRK_TWO_PASS_USE_WFI
	.comm	_REG_A5XX_CP_CHICKEN_DBG,4,2    ; @REG_A5XX_CP_CHICKEN_DBG
	.comm	_REG_A5XX_RBBM_AHB_CNTL1,4,2    ; @REG_A5XX_RBBM_AHB_CNTL1
	.comm	_REG_A5XX_RBBM_AHB_CNTL2,4,2    ; @REG_A5XX_RBBM_AHB_CNTL2
	.comm	_REG_A5XX_TPL1_MODE_CNTL,4,2    ; @REG_A5XX_TPL1_MODE_CNTL
	.comm	_REG_A5XX_RB_MODE_CNTL,4,2      ; @REG_A5XX_RB_MODE_CNTL
	.comm	_REG_A5XX_UCHE_DBG_ECO_CNTL_2,4,2 ; @REG_A5XX_UCHE_DBG_ECO_CNTL_2
	.comm	_REG_A5XX_CP_PROTECT_CNTL,4,2   ; @REG_A5XX_CP_PROTECT_CNTL
	.comm	_REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO,4,2 ; @REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO
	.comm	_REG_A5XX_RBBM_SECVID_TRUST_CNTL,4,2 ; @REG_A5XX_RBBM_SECVID_TRUST_CNTL
	.comm	_REG_A5XX_RBBM_SECVID_TSB_CNTL,4,2 ; @REG_A5XX_RBBM_SECVID_TSB_CNTL
	.comm	_REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI,4,2 ; @REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI
	.comm	_REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE,4,2 ; @REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE
	.comm	_REG_A5XX_CP_ADDR_MODE_CNTL,4,2 ; @REG_A5XX_CP_ADDR_MODE_CNTL
	.comm	_REG_A5XX_VSC_ADDR_MODE_CNTL,4,2 ; @REG_A5XX_VSC_ADDR_MODE_CNTL
	.comm	_REG_A5XX_GRAS_ADDR_MODE_CNTL,4,2 ; @REG_A5XX_GRAS_ADDR_MODE_CNTL
	.comm	_REG_A5XX_RB_ADDR_MODE_CNTL,4,2 ; @REG_A5XX_RB_ADDR_MODE_CNTL
	.comm	_REG_A5XX_PC_ADDR_MODE_CNTL,4,2 ; @REG_A5XX_PC_ADDR_MODE_CNTL
	.comm	_REG_A5XX_HLSQ_ADDR_MODE_CNTL,4,2 ; @REG_A5XX_HLSQ_ADDR_MODE_CNTL
	.comm	_REG_A5XX_VFD_ADDR_MODE_CNTL,4,2 ; @REG_A5XX_VFD_ADDR_MODE_CNTL
	.comm	_REG_A5XX_VPC_ADDR_MODE_CNTL,4,2 ; @REG_A5XX_VPC_ADDR_MODE_CNTL
	.comm	_REG_A5XX_UCHE_ADDR_MODE_CNTL,4,2 ; @REG_A5XX_UCHE_ADDR_MODE_CNTL
	.comm	_REG_A5XX_SP_ADDR_MODE_CNTL,4,2 ; @REG_A5XX_SP_ADDR_MODE_CNTL
	.comm	_REG_A5XX_TPL1_ADDR_MODE_CNTL,4,2 ; @REG_A5XX_TPL1_ADDR_MODE_CNTL
	.comm	_REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL,4,2 ; @REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL
	.comm	_ADRENO_QUIRK_LMLOADKILL_DISABLE,4,2 ; @ADRENO_QUIRK_LMLOADKILL_DISABLE
	.comm	_REG_A5XX_VPC_DBG_ECO_CNTL,4,2  ; @REG_A5XX_VPC_DBG_ECO_CNTL
	.comm	_REG_A5XX_HLSQ_DBG_ECO_CNTL,4,2 ; @REG_A5XX_HLSQ_DBG_ECO_CNTL
	.comm	_REG_A5XX_RBBM_INT_0_MASK,4,2   ; @REG_A5XX_RBBM_INT_0_MASK
	.comm	_A5XX_INT_MASK,4,2              ; @A5XX_INT_MASK
	.comm	_REG_A5XX_CP_PFP_ME_CNTL,4,2    ; @REG_A5XX_CP_PFP_ME_CNTL
	.comm	_CP_EVENT_WRITE,4,2             ; @CP_EVENT_WRITE
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_CP_SET_SECURE_MODE,4,2         ; @CP_SET_SECURE_MODE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"

	.no_dead_strip	_a5xx_hw_init
.subsections_via_symbols
