	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function si_gpu_init
_si_gpu_init:                           ## @si_gpu_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movl	$-129, %eax
	addl	(%rdi), %eax
	cmpl	$3, %eax
	ja	LBB0_1
## %bb.2:
	movslq	%eax, %rsi
	leaq	L_switch.table.si_gpu_init.3(%rip), %rax
	movl	(%rax,%rsi,4), %edx
	leaq	L_switch.table.si_gpu_init.1(%rip), %rax
	movl	(%rax,%rsi,4), %r11d
	leaq	L_switch.table.si_gpu_init.2(%rip), %rax
	movl	(%rax,%rsi,4), %ebx
	leaq	L_switch.table.si_gpu_init.4(%rip), %rax
	movl	(%rax,%rsi,4), %eax
	leaq	L_switch.table.si_gpu_init.5(%rip), %rcx
	movl	(%rcx,%rsi,4), %ecx
	leaq	L_switch.table.si_gpu_init.6(%rip), %rdi
	movl	(%rdi,%rsi,4), %r10d
	leaq	L_switch.table.si_gpu_init.7(%rip), %rdi
	movl	(%rdi,%rsi,4), %r9d
	leaq	l_switch.table.si_gpu_init.8(%rip), %rdi
	movq	(%rdi,%rsi,8), %r8
	movl	%edx, %esi
	jmp	LBB0_3
LBB0_1:
	movq	_VERDE_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %r8
	movl	$64, %r9d
	movl	$32, %r10d
	movl	$2, %esi
	movl	$5, %ebx
	movl	$4, %r11d
	movl	$1, %edx
	movl	$4, %eax
	movl	$4, %ecx
LBB0_3:
	movl	%edx, 8(%r12)
	movl	%r11d, 12(%r12)
	movl	%ebx, 16(%r12)
	movl	%esi, 20(%r12)
	movl	%eax, 24(%r12)
	movl	%ecx, 28(%r12)
	movl	$256, 32(%r12)                  ## imm = 0x100
	movl	%r10d, 36(%r12)
	movabsq	$137438953480, %rax             ## imm = 0x2000000008
	movq	%rax, 40(%r12)
	movl	%r9d, 48(%r12)
	movabsq	$1305670058032, %rax            ## imm = 0x13000000030
	movq	%rax, 52(%r12)
	movl	(%r8), %r13d
	movl	$11284, %ebx                    ## imm = 0x2C14
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movl	%ebx, %edi
	xorl	%esi, %esi
	callq	_WREG32
	leal	4(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	leal	8(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	leal	12(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	leal	16(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	addl	$24, %ebx
	cmpl	$12052, %ebx                    ## imm = 0x2F14
	jne	LBB0_4
## %bb.5:
	movq	_GRBM_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$255, %edi
	callq	_GRBM_READ_TIMEOUT
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_SRBM_INT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_WREG32
	movq	_SRBM_INT_ACK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_WREG32
	movq	%r12, %rdi
	callq	_evergreen_fix_pci_max_read_req_size
	movq	_BIF_FB_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_FB_READ_EN@GOTPCREL(%rip), %rax
	movq	_FB_WRITE_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	callq	_WREG32
	movq	_MC_SHARED_CHMAP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_MC_ARB_RAMCFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r15d
	movl	12(%r12), %eax
	movl	%eax, 60(%r12)
	movl	$256, 64(%r12)                  ## imm = 0x100
	movq	_NOOFCOLS_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r15d, %eax
	movq	_NOOFCOLS_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	addb	$8, %al
	movl	$4, %edx
	movl	$4, %esi
	movl	%eax, %ecx
	shll	%cl, %esi
	cmpl	$5119, %esi                     ## imm = 0x13FF
	jg	LBB0_7
## %bb.6:
	leal	1023(%rsi), %edx
	testl	%esi, %esi
	cmovnsl	%esi, %edx
	sarl	$10, %edx
LBB0_7:
	movl	%edx, 68(%r12)
	movabsq	$4294967328, %rax               ## imm = 0x100000020
	movq	%rax, 72(%r12)
	movl	$64, 80(%r12)
	movq	_ROW_SIZE_MASK@GOTPCREL(%rip), %rbx
	movl	(%rbx), %eax
	notl	%eax
	andl	%eax, %r13d
	xorl	%eax, %eax
	cmpl	$2, %edx
	sete	%al
	cmpl	$4, %edx
	movl	$2, %edi
	cmovnel	%eax, %edi
	callq	_ROW_SIZE
	movl	%eax, %r14d
	movl	60(%r12), %ecx
	decl	%ecx
	movl	$3, %eax
	cmpl	$3, %ecx
	ja	LBB0_9
## %bb.8:
	movslq	%ecx, %rax
	leaq	L_switch.table.si_gpu_init.9(%rip), %rcx
	movl	(%rcx,%rax,4), %eax
LBB0_9:
	orl	%r13d, %r14d
	movq	_NOOFBANK_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %r15d
	movq	_NOOFBANK_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %r15d
	testl	%r15d, %r15d
	je	LBB0_13
## %bb.10:
	cmpl	$1, %r15d
	jne	LBB0_12
## %bb.11:
	orl	$16, %eax
	jmp	LBB0_13
LBB0_12:
	orl	$32, %eax
LBB0_13:
	movq	_PIPE_INTERLEAVE_SIZE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	andl	%r14d, %edx
	movq	_PIPE_INTERLEAVE_SIZE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %edx
	shll	$8, %edx
	orl	%eax, %edx
	movl	(%rbx), %eax
	andl	%r14d, %eax
	movq	_ROW_SIZE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	shll	$12, %eax
	orl	%edx, %eax
	movl	%eax, 84(%r12)
	movq	_GB_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_DMIF_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_DMIF_ADDR_CALC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_HDP_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_DMA_TILING_CONFIG@GOTPCREL(%rip), %rbx
	movq	_DMA0_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	addl	(%rbx), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_DMA1_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	addl	(%rbx), %edi
	movl	%r14d, %esi
	callq	_WREG32
	cmpq	$0, 96(%r12)
	je	LBB0_15
## %bb.14:
	movq	_UVD_UDEC_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_UVD_UDEC_DB_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_UVD_UDEC_DBW_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
LBB0_15:
	movq	%r12, %rdi
	callq	_si_tiling_mode_table_init
	movl	8(%r12), %esi
	movl	20(%r12), %edx
	movl	24(%r12), %ecx
	movq	%r12, %rdi
	callq	_si_setup_rb
	movl	20(%r12), %edx
	movl	8(%r12), %esi
	movl	16(%r12), %ecx
	movq	%r12, %rdi
	callq	_si_setup_spi
	movq	$0, 88(%r12)
	movl	8(%r12), %ecx
	testl	%ecx, %ecx
	jle	LBB0_22
## %bb.16:
	movl	20(%r12), %eax
	xorl	%r14d, %r14d
	jmp	LBB0_17
	.p2align	4, 0x90
LBB0_21:                                ##   in Loop: Header=BB0_17 Depth=1
	incl	%r14d
	cmpl	%ecx, %r14d
	jge	LBB0_22
LBB0_17:                                ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_19 Depth 2
	testl	%eax, %eax
	jle	LBB0_21
## %bb.18:                              ##   in Loop: Header=BB0_17 Depth=1
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_19:                                ##   Parent Loop BB0_17 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movq	%r12, %rdi
	movl	%r14d, %esi
	movl	%ebx, %edx
	callq	_si_get_cu_active_bitmap
	movl	%eax, %edi
	callq	_hweight32
	addq	%rax, 88(%r12)
	incl	%ebx
	movl	20(%r12), %eax
	cmpl	%eax, %ebx
	jl	LBB0_19
## %bb.20:                              ##   in Loop: Header=BB0_17 Depth=1
	movl	8(%r12), %ecx
	jmp	LBB0_21
LBB0_22:
	movq	_CP_QUEUE_THRESHOLDS@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	$22, %edi
	callq	_ROQ_IB1_START
	movl	%eax, %ebx
	movl	$43, %edi
	callq	_ROQ_IB2_START
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_CP_MEQ_THRESHOLDS@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	$48, %edi
	callq	_MEQ1_START
	movl	%eax, %ebx
	movl	$96, %edi
	callq	_MEQ2_START
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_SX_DEBUG_1@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_SPI_CONFIG_CNTL_1@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$4, %edi
	callq	_VTX_DONE_DELAY
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_PA_SC_FIFO_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	44(%r12), %edi
	callq	_SC_FRONTEND_PRIM_FIFO_SIZE
	movl	%eax, %r15d
	movl	48(%r12), %edi
	callq	_SC_BACKEND_PRIM_FIFO_SIZE
	orl	%eax, %r15d
	movl	52(%r12), %edi
	callq	_SC_HIZ_TILE_FIFO_SIZE
	movl	%eax, %ebx
	movl	56(%r12), %edi
	callq	_SC_EARLYZ_TILE_FIFO_SIZE
	orl	%eax, %ebx
	orl	%r15d, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_VGT_NUM_INSTANCES@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_WREG32
	movq	_CP_PERFMON_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_SQ_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_PA_SC_FORCE_EOV_MAX_CNTS@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	$4095, %edi                     ## imm = 0xFFF
	callq	_FORCE_EOV_MAX_CLK_CNT
	movl	%eax, %ebx
	movl	$255, %edi
	callq	_FORCE_EOV_MAX_REZ_CNT
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_VGT_CACHE_INVALIDATION@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_VC_AND_TC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_CACHE_INVALIDATION
	movl	%eax, %ebx
	movq	_ES_AND_GS_AUTO@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_AUTO_INVLD_EN
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_VGT_GS_VERTEX_REUSE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$16, %esi
	callq	_WREG32
	movq	_PA_SC_LINE_STIPPLE_STATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CB_PERFCOUNTER0_SELECT0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CB_PERFCOUNTER0_SELECT1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CB_PERFCOUNTER1_SELECT0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CB_PERFCOUNTER1_SELECT1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CB_PERFCOUNTER2_SELECT0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CB_PERFCOUNTER2_SELECT1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CB_PERFCOUNTER3_SELECT0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CB_PERFCOUNTER3_SELECT1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_HDP_MISC_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_HDP_FLUSH_INVALIDATE_CACHE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_HDP_HOST_PATH_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_PA_CL_ENHANCE@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_CLIP_VTX_REORDER_ENA@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$3, %edi
	callq	_NUM_CLIP_SEQ
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	$50, %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_udelay                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_TAHITI_GB_ADDR_CONFIG_GOLDEN,4,2 ## @TAHITI_GB_ADDR_CONFIG_GOLDEN
	.comm	_VERDE_GB_ADDR_CONFIG_GOLDEN,4,2 ## @VERDE_GB_ADDR_CONFIG_GOLDEN
	.comm	_HAINAN_GB_ADDR_CONFIG_GOLDEN,4,2 ## @HAINAN_GB_ADDR_CONFIG_GOLDEN
	.comm	_GRBM_CNTL,4,2                  ## @GRBM_CNTL
	.comm	_SRBM_INT_CNTL,4,2              ## @SRBM_INT_CNTL
	.comm	_SRBM_INT_ACK,4,2               ## @SRBM_INT_ACK
	.comm	_BIF_FB_EN,4,2                  ## @BIF_FB_EN
	.comm	_FB_READ_EN,4,2                 ## @FB_READ_EN
	.comm	_FB_WRITE_EN,4,2                ## @FB_WRITE_EN
	.comm	_MC_SHARED_CHMAP,4,2            ## @MC_SHARED_CHMAP
	.comm	_MC_ARB_RAMCFG,4,2              ## @MC_ARB_RAMCFG
	.comm	_NOOFCOLS_MASK,4,2              ## @NOOFCOLS_MASK
	.comm	_NOOFCOLS_SHIFT,4,2             ## @NOOFCOLS_SHIFT
	.comm	_ROW_SIZE_MASK,4,2              ## @ROW_SIZE_MASK
	.comm	_NOOFBANK_MASK,4,2              ## @NOOFBANK_MASK
	.comm	_NOOFBANK_SHIFT,4,2             ## @NOOFBANK_SHIFT
	.comm	_PIPE_INTERLEAVE_SIZE_MASK,4,2  ## @PIPE_INTERLEAVE_SIZE_MASK
	.comm	_PIPE_INTERLEAVE_SIZE_SHIFT,4,2 ## @PIPE_INTERLEAVE_SIZE_SHIFT
	.comm	_ROW_SIZE_SHIFT,4,2             ## @ROW_SIZE_SHIFT
	.comm	_GB_ADDR_CONFIG,4,2             ## @GB_ADDR_CONFIG
	.comm	_DMIF_ADDR_CONFIG,4,2           ## @DMIF_ADDR_CONFIG
	.comm	_DMIF_ADDR_CALC,4,2             ## @DMIF_ADDR_CALC
	.comm	_HDP_ADDR_CONFIG,4,2            ## @HDP_ADDR_CONFIG
	.comm	_DMA_TILING_CONFIG,4,2          ## @DMA_TILING_CONFIG
	.comm	_DMA0_REGISTER_OFFSET,4,2       ## @DMA0_REGISTER_OFFSET
	.comm	_DMA1_REGISTER_OFFSET,4,2       ## @DMA1_REGISTER_OFFSET
	.comm	_UVD_UDEC_ADDR_CONFIG,4,2       ## @UVD_UDEC_ADDR_CONFIG
	.comm	_UVD_UDEC_DB_ADDR_CONFIG,4,2    ## @UVD_UDEC_DB_ADDR_CONFIG
	.comm	_UVD_UDEC_DBW_ADDR_CONFIG,4,2   ## @UVD_UDEC_DBW_ADDR_CONFIG
	.comm	_CP_QUEUE_THRESHOLDS,4,2        ## @CP_QUEUE_THRESHOLDS
	.comm	_CP_MEQ_THRESHOLDS,4,2          ## @CP_MEQ_THRESHOLDS
	.comm	_SX_DEBUG_1,4,2                 ## @SX_DEBUG_1
	.comm	_SPI_CONFIG_CNTL_1,4,2          ## @SPI_CONFIG_CNTL_1
	.comm	_PA_SC_FIFO_SIZE,4,2            ## @PA_SC_FIFO_SIZE
	.comm	_VGT_NUM_INSTANCES,4,2          ## @VGT_NUM_INSTANCES
	.comm	_CP_PERFMON_CNTL,4,2            ## @CP_PERFMON_CNTL
	.comm	_SQ_CONFIG,4,2                  ## @SQ_CONFIG
	.comm	_PA_SC_FORCE_EOV_MAX_CNTS,4,2   ## @PA_SC_FORCE_EOV_MAX_CNTS
	.comm	_VGT_CACHE_INVALIDATION,4,2     ## @VGT_CACHE_INVALIDATION
	.comm	_VC_AND_TC,4,2                  ## @VC_AND_TC
	.comm	_ES_AND_GS_AUTO,4,2             ## @ES_AND_GS_AUTO
	.comm	_VGT_GS_VERTEX_REUSE,4,2        ## @VGT_GS_VERTEX_REUSE
	.comm	_PA_SC_LINE_STIPPLE_STATE,4,2   ## @PA_SC_LINE_STIPPLE_STATE
	.comm	_CB_PERFCOUNTER0_SELECT0,4,2    ## @CB_PERFCOUNTER0_SELECT0
	.comm	_CB_PERFCOUNTER0_SELECT1,4,2    ## @CB_PERFCOUNTER0_SELECT1
	.comm	_CB_PERFCOUNTER1_SELECT0,4,2    ## @CB_PERFCOUNTER1_SELECT0
	.comm	_CB_PERFCOUNTER1_SELECT1,4,2    ## @CB_PERFCOUNTER1_SELECT1
	.comm	_CB_PERFCOUNTER2_SELECT0,4,2    ## @CB_PERFCOUNTER2_SELECT0
	.comm	_CB_PERFCOUNTER2_SELECT1,4,2    ## @CB_PERFCOUNTER2_SELECT1
	.comm	_CB_PERFCOUNTER3_SELECT0,4,2    ## @CB_PERFCOUNTER3_SELECT0
	.comm	_CB_PERFCOUNTER3_SELECT1,4,2    ## @CB_PERFCOUNTER3_SELECT1
	.comm	_HDP_MISC_CNTL,4,2              ## @HDP_MISC_CNTL
	.comm	_HDP_FLUSH_INVALIDATE_CACHE,4,2 ## @HDP_FLUSH_INVALIDATE_CACHE
	.comm	_HDP_HOST_PATH_CNTL,4,2         ## @HDP_HOST_PATH_CNTL
	.comm	_PA_CL_ENHANCE,4,2              ## @PA_CL_ENHANCE
	.comm	_CLIP_VTX_REORDER_ENA,4,2       ## @CLIP_VTX_REORDER_ENA
	.no_dead_strip	_si_gpu_init
	.section	__TEXT,__literal16,16byte_literals
	.p2align	2                               ## @switch.table.si_gpu_init.1
L_switch.table.si_gpu_init.1:
	.long	12                              ## 0xc
	.long	8                               ## 0x8
	.long	4                               ## 0x4
	.long	4                               ## 0x4

	.p2align	2                               ## @switch.table.si_gpu_init.2
L_switch.table.si_gpu_init.2:
	.long	8                               ## 0x8
	.long	5                               ## 0x5
	.long	6                               ## 0x6
	.long	5                               ## 0x5

	.p2align	2                               ## @switch.table.si_gpu_init.3
L_switch.table.si_gpu_init.3:
	.long	2                               ## 0x2
	.long	2                               ## 0x2
	.long	1                               ## 0x1
	.long	1                               ## 0x1

	.p2align	2                               ## @switch.table.si_gpu_init.4
L_switch.table.si_gpu_init.4:
	.long	4                               ## 0x4
	.long	4                               ## 0x4
	.long	2                               ## 0x2
	.long	1                               ## 0x1

	.p2align	2                               ## @switch.table.si_gpu_init.5
L_switch.table.si_gpu_init.5:
	.long	12                              ## 0xc
	.long	8                               ## 0x8
	.long	4                               ## 0x4
	.long	2                               ## 0x2

	.p2align	2                               ## @switch.table.si_gpu_init.6
L_switch.table.si_gpu_init.6:
	.long	32                              ## 0x20
	.long	32                              ## 0x20
	.long	16                              ## 0x10
	.long	16                              ## 0x10

	.p2align	2                               ## @switch.table.si_gpu_init.7
L_switch.table.si_gpu_init.7:
	.long	256                             ## 0x100
	.long	256                             ## 0x100
	.long	64                              ## 0x40
	.long	64                              ## 0x40

	.section	__DATA,__const
	.p2align	3                               ## @switch.table.si_gpu_init.8
l_switch.table.si_gpu_init.8:
	.quad	_TAHITI_GB_ADDR_CONFIG_GOLDEN
	.quad	_TAHITI_GB_ADDR_CONFIG_GOLDEN
	.quad	_VERDE_GB_ADDR_CONFIG_GOLDEN
	.quad	_HAINAN_GB_ADDR_CONFIG_GOLDEN

	.section	__TEXT,__literal16,16byte_literals
	.p2align	2                               ## @switch.table.si_gpu_init.9
L_switch.table.si_gpu_init.9:
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	3                               ## 0x3
	.long	2                               ## 0x2

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3                               ; -- Begin function si_gpu_init
lCPI0_0:
	.long	8                               ; 0x8
	.long	32                              ; 0x20
lCPI0_1:
	.long	48                              ; 0x30
	.long	304                             ; 0x130
lCPI0_2:
	.long	32                              ; 0x20
	.long	1                               ; 0x1
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	2
_si_gpu_init:                           ; @si_gpu_init
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	w8, [x0]
	sub	w8, w8, #129
	cmp	w8, #3
	b.hi	LBB0_2
; %bb.1:
	sbfiz	x9, x8, #2, #32
Lloh0:
	adrp	x10, l_switch.table.si_gpu_init.3@PAGE
Lloh1:
	add	x10, x10, l_switch.table.si_gpu_init.3@PAGEOFF
	ldr	w11, [x10, x9]
Lloh2:
	adrp	x10, l_switch.table.si_gpu_init.1@PAGE
Lloh3:
	add	x10, x10, l_switch.table.si_gpu_init.1@PAGEOFF
	ldr	w12, [x10, x9]
Lloh4:
	adrp	x10, l_switch.table.si_gpu_init.2@PAGE
Lloh5:
	add	x10, x10, l_switch.table.si_gpu_init.2@PAGEOFF
	ldr	w13, [x10, x9]
Lloh6:
	adrp	x10, l_switch.table.si_gpu_init.4@PAGE
Lloh7:
	add	x10, x10, l_switch.table.si_gpu_init.4@PAGEOFF
	ldr	w14, [x10, x9]
Lloh8:
	adrp	x10, l_switch.table.si_gpu_init.5@PAGE
Lloh9:
	add	x10, x10, l_switch.table.si_gpu_init.5@PAGEOFF
	ldr	w15, [x10, x9]
Lloh10:
	adrp	x10, l_switch.table.si_gpu_init.6@PAGE
Lloh11:
	add	x10, x10, l_switch.table.si_gpu_init.6@PAGEOFF
	ldr	w10, [x10, x9]
Lloh12:
	adrp	x16, l_switch.table.si_gpu_init.7@PAGE
Lloh13:
	add	x16, x16, l_switch.table.si_gpu_init.7@PAGEOFF
	ldr	w9, [x16, x9]
Lloh14:
	adrp	x16, l_switch.table.si_gpu_init.8@PAGE
Lloh15:
	add	x16, x16, l_switch.table.si_gpu_init.8@PAGEOFF
	ldr	x8, [x16, w8, sxtw #3]
	mov	x16, x11
	b	LBB0_3
LBB0_2:
Lloh16:
	adrp	x8, _VERDE_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh17:
	ldr	x8, [x8, _VERDE_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
	mov	w9, #64
	mov	w10, #32
	mov	w16, #2
	mov	w13, #5
	mov	w12, #4
	mov	w11, #1
	mov	w14, #4
	mov	w15, #4
LBB0_3:
	mov	w21, #0
	stp	w11, w12, [x19, #8]
	stp	w13, w16, [x19, #16]
	stp	w14, w15, [x19, #24]
	mov	w11, #256
	stp	w11, w10, [x19, #32]
Lloh18:
	adrp	x10, lCPI0_0@PAGE
Lloh19:
	ldr	d0, [x10, lCPI0_0@PAGEOFF]
	str	d0, [x19, #40]
	str	w9, [x19, #48]
Lloh20:
	adrp	x9, lCPI0_1@PAGE
Lloh21:
	ldr	d0, [x9, lCPI0_1@PAGEOFF]
	mov	w23, #11292
	mov	w24, #11284
	stur	d0, [x19, #52]
	mov	w25, #11288
	mov	w26, #11296
	mov	w27, #11300
	ldr	w22, [x8]
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
	add	w20, w21, w23
	add	w0, w21, w24
	mov	w1, #0
	bl	_WREG32
	add	w0, w21, w25
	mov	w1, #0
	bl	_WREG32
	mov	x0, x20
	mov	w1, #0
	bl	_WREG32
	add	w0, w21, w26
	mov	w1, #0
	bl	_WREG32
	add	w0, w21, w27
	mov	w1, #0
	bl	_WREG32
	add	w21, w21, #24
	cmp	w21, #768
	b.ne	LBB0_4
; %bb.5:
Lloh22:
	adrp	x8, _GRBM_CNTL@GOTPAGE
Lloh23:
	ldr	x8, [x8, _GRBM_CNTL@GOTPAGEOFF]
Lloh24:
	ldr	w20, [x8]
	mov	w0, #255
	bl	_GRBM_READ_TIMEOUT
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
Lloh25:
	adrp	x8, _SRBM_INT_CNTL@GOTPAGE
Lloh26:
	ldr	x8, [x8, _SRBM_INT_CNTL@GOTPAGEOFF]
Lloh27:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_WREG32
Lloh28:
	adrp	x8, _SRBM_INT_ACK@GOTPAGE
Lloh29:
	ldr	x8, [x8, _SRBM_INT_ACK@GOTPAGEOFF]
Lloh30:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_WREG32
	mov	x0, x19
	bl	_evergreen_fix_pci_max_read_req_size
Lloh31:
	adrp	x8, _BIF_FB_EN@GOTPAGE
Lloh32:
	ldr	x8, [x8, _BIF_FB_EN@GOTPAGEOFF]
Lloh33:
	adrp	x9, _FB_READ_EN@GOTPAGE
Lloh34:
	ldr	x9, [x9, _FB_READ_EN@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
Lloh36:
	ldr	w8, [x9]
Lloh37:
	adrp	x9, _FB_WRITE_EN@GOTPAGE
Lloh38:
	ldr	x9, [x9, _FB_WRITE_EN@GOTPAGEOFF]
Lloh39:
	ldr	w9, [x9]
	orr	w1, w9, w8
	bl	_WREG32
Lloh40:
	adrp	x8, _MC_SHARED_CHMAP@GOTPAGE
Lloh41:
	ldr	x8, [x8, _MC_SHARED_CHMAP@GOTPAGEOFF]
Lloh42:
	ldr	w0, [x8]
	bl	_RREG32
Lloh43:
	adrp	x8, _MC_ARB_RAMCFG@GOTPAGE
Lloh44:
	ldr	x8, [x8, _MC_ARB_RAMCFG@GOTPAGEOFF]
Lloh45:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x21, x0
	ldr	w8, [x19, #12]
	mov	w9, #256
	stp	w8, w9, [x19, #60]
Lloh46:
	adrp	x8, _NOOFCOLS_MASK@GOTPAGE
Lloh47:
	ldr	x8, [x8, _NOOFCOLS_MASK@GOTPAGEOFF]
Lloh48:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh49:
	adrp	x9, _NOOFCOLS_SHIFT@GOTPAGE
Lloh50:
	ldr	x9, [x9, _NOOFCOLS_SHIFT@GOTPAGEOFF]
Lloh51:
	ldr	w9, [x9]
	asr	w8, w8, w9
	add	w8, w8, #8
	mov	w9, #4
	lsl	w8, w9, w8
	add	w10, w8, #1023
	cmp	w8, #0
	csel	w10, w10, w8, lt
	asr	w10, w10, #10
	mov	w11, #5119
	cmp	w8, w11
	csel	w8, w9, w10, gt
	str	w8, [x19, #68]
Lloh52:
	adrp	x9, lCPI0_2@PAGE
Lloh53:
	ldr	d0, [x9, lCPI0_2@PAGEOFF]
	str	d0, [x19, #72]
	mov	w9, #64
	str	w9, [x19, #80]
Lloh54:
	adrp	x23, _ROW_SIZE_MASK@GOTPAGE
Lloh55:
	ldr	x23, [x23, _ROW_SIZE_MASK@GOTPAGEOFF]
	ldr	w9, [x23]
	bic	w20, w22, w9
	cmp	w8, #2
	cset	w9, eq
	mov	w10, #2
	cmp	w8, #4
	csel	w0, w10, w9, eq
	bl	_ROW_SIZE
	orr	w20, w0, w20
	ldr	w8, [x19, #60]
	sub	w8, w8, #1
	cmp	w8, #3
	b.hi	LBB0_7
; %bb.6:
Lloh56:
	adrp	x9, l_switch.table.si_gpu_init.9@PAGE
Lloh57:
	add	x9, x9, l_switch.table.si_gpu_init.9@PAGEOFF
	ldr	w8, [x9, w8, sxtw #2]
	b	LBB0_8
LBB0_7:
	mov	w8, #3
LBB0_8:
Lloh58:
	adrp	x9, _NOOFBANK_MASK@GOTPAGE
Lloh59:
	ldr	x9, [x9, _NOOFBANK_MASK@GOTPAGEOFF]
Lloh60:
	ldr	w9, [x9]
	and	w9, w9, w21
Lloh61:
	adrp	x10, _NOOFBANK_SHIFT@GOTPAGE
Lloh62:
	ldr	x10, [x10, _NOOFBANK_SHIFT@GOTPAGEOFF]
Lloh63:
	ldr	w10, [x10]
	asr	w9, w9, w10
	cbz	w9, LBB0_12
; %bb.9:
	cmp	w9, #1
	b.ne	LBB0_11
; %bb.10:
	orr	w8, w8, #0x10
	b	LBB0_12
LBB0_11:
	orr	w8, w8, #0x20
LBB0_12:
Lloh64:
	adrp	x9, _PIPE_INTERLEAVE_SIZE_MASK@GOTPAGE
Lloh65:
	ldr	x9, [x9, _PIPE_INTERLEAVE_SIZE_MASK@GOTPAGEOFF]
Lloh66:
	ldr	w9, [x9]
	and	w9, w9, w20
Lloh67:
	adrp	x10, _PIPE_INTERLEAVE_SIZE_SHIFT@GOTPAGE
Lloh68:
	ldr	x10, [x10, _PIPE_INTERLEAVE_SIZE_SHIFT@GOTPAGEOFF]
Lloh69:
	ldr	w10, [x10]
	asr	w9, w9, w10
	orr	w8, w8, w9, lsl #8
	ldr	w9, [x23]
	and	w9, w9, w20
Lloh70:
	adrp	x10, _ROW_SIZE_SHIFT@GOTPAGE
Lloh71:
	ldr	x10, [x10, _ROW_SIZE_SHIFT@GOTPAGEOFF]
Lloh72:
	ldr	w10, [x10]
	asr	w9, w9, w10
	orr	w8, w8, w9, lsl #12
	str	w8, [x19, #84]
Lloh73:
	adrp	x8, _GB_ADDR_CONFIG@GOTPAGE
Lloh74:
	ldr	x8, [x8, _GB_ADDR_CONFIG@GOTPAGEOFF]
Lloh75:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh76:
	adrp	x8, _DMIF_ADDR_CONFIG@GOTPAGE
Lloh77:
	ldr	x8, [x8, _DMIF_ADDR_CONFIG@GOTPAGEOFF]
Lloh78:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh79:
	adrp	x8, _DMIF_ADDR_CALC@GOTPAGE
Lloh80:
	ldr	x8, [x8, _DMIF_ADDR_CALC@GOTPAGEOFF]
Lloh81:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh82:
	adrp	x8, _HDP_ADDR_CONFIG@GOTPAGE
Lloh83:
	ldr	x8, [x8, _HDP_ADDR_CONFIG@GOTPAGEOFF]
Lloh84:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh85:
	adrp	x21, _DMA_TILING_CONFIG@GOTPAGE
Lloh86:
	ldr	x21, [x21, _DMA_TILING_CONFIG@GOTPAGEOFF]
	ldr	w8, [x21]
Lloh87:
	adrp	x9, _DMA0_REGISTER_OFFSET@GOTPAGE
Lloh88:
	ldr	x9, [x9, _DMA0_REGISTER_OFFSET@GOTPAGEOFF]
Lloh89:
	ldr	w9, [x9]
	add	w0, w9, w8
	mov	x1, x20
	bl	_WREG32
	ldr	w8, [x21]
Lloh90:
	adrp	x9, _DMA1_REGISTER_OFFSET@GOTPAGE
Lloh91:
	ldr	x9, [x9, _DMA1_REGISTER_OFFSET@GOTPAGEOFF]
Lloh92:
	ldr	w9, [x9]
	add	w0, w9, w8
	mov	x1, x20
	bl	_WREG32
	ldr	x8, [x19, #96]
	cbz	x8, LBB0_14
; %bb.13:
Lloh93:
	adrp	x8, _UVD_UDEC_ADDR_CONFIG@GOTPAGE
Lloh94:
	ldr	x8, [x8, _UVD_UDEC_ADDR_CONFIG@GOTPAGEOFF]
Lloh95:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh96:
	adrp	x8, _UVD_UDEC_DB_ADDR_CONFIG@GOTPAGE
Lloh97:
	ldr	x8, [x8, _UVD_UDEC_DB_ADDR_CONFIG@GOTPAGEOFF]
Lloh98:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh99:
	adrp	x8, _UVD_UDEC_DBW_ADDR_CONFIG@GOTPAGE
Lloh100:
	ldr	x8, [x8, _UVD_UDEC_DBW_ADDR_CONFIG@GOTPAGEOFF]
Lloh101:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
LBB0_14:
	mov	x0, x19
	bl	_si_tiling_mode_table_init
	ldr	w1, [x19, #8]
	ldp	w2, w3, [x19, #20]
	mov	x0, x19
	bl	_si_setup_rb
	ldr	w1, [x19, #8]
	ldp	w3, w2, [x19, #16]
	mov	x0, x19
	bl	_si_setup_spi
	str	xzr, [x19, #88]
	ldr	w9, [x19, #8]
	cmp	w9, #1
	b.lt	LBB0_21
; %bb.15:
	mov	w20, #0
	ldr	w8, [x19, #20]
	b	LBB0_17
LBB0_16:                                ;   in Loop: Header=BB0_17 Depth=1
	add	w20, w20, #1
	cmp	w20, w9
	b.ge	LBB0_21
LBB0_17:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_19 Depth 2
	cmp	w8, #1
	b.lt	LBB0_16
; %bb.18:                               ;   in Loop: Header=BB0_17 Depth=1
	mov	w21, #0
LBB0_19:                                ;   Parent Loop BB0_17 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	mov	x0, x19
	mov	x1, x20
	mov	x2, x21
	bl	_si_get_cu_active_bitmap
	bl	_hweight32
	ldr	x8, [x19, #88]
	add	x8, x8, x0
	str	x8, [x19, #88]
	add	w21, w21, #1
	ldr	w8, [x19, #20]
	cmp	w21, w8
	b.lt	LBB0_19
; %bb.20:                               ;   in Loop: Header=BB0_17 Depth=1
	ldr	w9, [x19, #8]
	b	LBB0_16
LBB0_21:
Lloh102:
	adrp	x8, _CP_QUEUE_THRESHOLDS@GOTPAGE
Lloh103:
	ldr	x8, [x8, _CP_QUEUE_THRESHOLDS@GOTPAGEOFF]
Lloh104:
	ldr	w20, [x8]
	mov	w0, #22
	bl	_ROQ_IB1_START
	mov	x21, x0
	mov	w0, #43
	bl	_ROQ_IB2_START
	orr	w1, w0, w21
	mov	x0, x20
	bl	_WREG32
Lloh105:
	adrp	x8, _CP_MEQ_THRESHOLDS@GOTPAGE
Lloh106:
	ldr	x8, [x8, _CP_MEQ_THRESHOLDS@GOTPAGEOFF]
Lloh107:
	ldr	w20, [x8]
	mov	w0, #48
	bl	_MEQ1_START
	mov	x21, x0
	mov	w0, #96
	bl	_MEQ2_START
	orr	w1, w0, w21
	mov	x0, x20
	bl	_WREG32
Lloh108:
	adrp	x20, _SX_DEBUG_1@GOTPAGE
Lloh109:
	ldr	x20, [x20, _SX_DEBUG_1@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	mov	x1, x0
	ldr	w0, [x20]
	bl	_WREG32
Lloh110:
	adrp	x8, _SPI_CONFIG_CNTL_1@GOTPAGE
Lloh111:
	ldr	x8, [x8, _SPI_CONFIG_CNTL_1@GOTPAGEOFF]
Lloh112:
	ldr	w20, [x8]
	mov	w0, #4
	bl	_VTX_DONE_DELAY
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
Lloh113:
	adrp	x8, _PA_SC_FIFO_SIZE@GOTPAGE
Lloh114:
	ldr	x8, [x8, _PA_SC_FIFO_SIZE@GOTPAGEOFF]
Lloh115:
	ldr	w20, [x8]
	ldr	w0, [x19, #44]
	bl	_SC_FRONTEND_PRIM_FIFO_SIZE
	mov	x21, x0
	ldr	w0, [x19, #48]
	bl	_SC_BACKEND_PRIM_FIFO_SIZE
	orr	w21, w0, w21
	ldr	w0, [x19, #52]
	bl	_SC_HIZ_TILE_FIFO_SIZE
	orr	w21, w21, w0
	ldr	w0, [x19, #56]
	bl	_SC_EARLYZ_TILE_FIFO_SIZE
	orr	w1, w21, w0
	mov	x0, x20
	bl	_WREG32
Lloh116:
	adrp	x8, _VGT_NUM_INSTANCES@GOTPAGE
Lloh117:
	ldr	x8, [x8, _VGT_NUM_INSTANCES@GOTPAGEOFF]
Lloh118:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_WREG32
Lloh119:
	adrp	x8, _CP_PERFMON_CNTL@GOTPAGE
Lloh120:
	ldr	x8, [x8, _CP_PERFMON_CNTL@GOTPAGEOFF]
Lloh121:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh122:
	adrp	x8, _SQ_CONFIG@GOTPAGE
Lloh123:
	ldr	x8, [x8, _SQ_CONFIG@GOTPAGEOFF]
Lloh124:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh125:
	adrp	x8, _PA_SC_FORCE_EOV_MAX_CNTS@GOTPAGE
Lloh126:
	ldr	x8, [x8, _PA_SC_FORCE_EOV_MAX_CNTS@GOTPAGEOFF]
Lloh127:
	ldr	w19, [x8]
	mov	w0, #4095
	bl	_FORCE_EOV_MAX_CLK_CNT
	mov	x20, x0
	mov	w0, #255
	bl	_FORCE_EOV_MAX_REZ_CNT
	orr	w1, w0, w20
	mov	x0, x19
	bl	_WREG32
Lloh128:
	adrp	x8, _VGT_CACHE_INVALIDATION@GOTPAGE
Lloh129:
	ldr	x8, [x8, _VGT_CACHE_INVALIDATION@GOTPAGEOFF]
Lloh130:
	ldr	w19, [x8]
Lloh131:
	adrp	x8, _VC_AND_TC@GOTPAGE
Lloh132:
	ldr	x8, [x8, _VC_AND_TC@GOTPAGEOFF]
Lloh133:
	ldr	w0, [x8]
	bl	_CACHE_INVALIDATION
	mov	x20, x0
Lloh134:
	adrp	x8, _ES_AND_GS_AUTO@GOTPAGE
Lloh135:
	ldr	x8, [x8, _ES_AND_GS_AUTO@GOTPAGEOFF]
Lloh136:
	ldr	w0, [x8]
	bl	_AUTO_INVLD_EN
	orr	w1, w0, w20
	mov	x0, x19
	bl	_WREG32
Lloh137:
	adrp	x8, _VGT_GS_VERTEX_REUSE@GOTPAGE
Lloh138:
	ldr	x8, [x8, _VGT_GS_VERTEX_REUSE@GOTPAGEOFF]
Lloh139:
	ldr	w0, [x8]
	mov	w1, #16
	bl	_WREG32
Lloh140:
	adrp	x8, _PA_SC_LINE_STIPPLE_STATE@GOTPAGE
Lloh141:
	ldr	x8, [x8, _PA_SC_LINE_STIPPLE_STATE@GOTPAGEOFF]
Lloh142:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh143:
	adrp	x8, _CB_PERFCOUNTER0_SELECT0@GOTPAGE
Lloh144:
	ldr	x8, [x8, _CB_PERFCOUNTER0_SELECT0@GOTPAGEOFF]
Lloh145:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh146:
	adrp	x8, _CB_PERFCOUNTER0_SELECT1@GOTPAGE
Lloh147:
	ldr	x8, [x8, _CB_PERFCOUNTER0_SELECT1@GOTPAGEOFF]
Lloh148:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh149:
	adrp	x8, _CB_PERFCOUNTER1_SELECT0@GOTPAGE
Lloh150:
	ldr	x8, [x8, _CB_PERFCOUNTER1_SELECT0@GOTPAGEOFF]
Lloh151:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh152:
	adrp	x8, _CB_PERFCOUNTER1_SELECT1@GOTPAGE
Lloh153:
	ldr	x8, [x8, _CB_PERFCOUNTER1_SELECT1@GOTPAGEOFF]
Lloh154:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh155:
	adrp	x8, _CB_PERFCOUNTER2_SELECT0@GOTPAGE
Lloh156:
	ldr	x8, [x8, _CB_PERFCOUNTER2_SELECT0@GOTPAGEOFF]
Lloh157:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh158:
	adrp	x8, _CB_PERFCOUNTER2_SELECT1@GOTPAGE
Lloh159:
	ldr	x8, [x8, _CB_PERFCOUNTER2_SELECT1@GOTPAGEOFF]
Lloh160:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh161:
	adrp	x8, _CB_PERFCOUNTER3_SELECT0@GOTPAGE
Lloh162:
	ldr	x8, [x8, _CB_PERFCOUNTER3_SELECT0@GOTPAGEOFF]
Lloh163:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh164:
	adrp	x8, _CB_PERFCOUNTER3_SELECT1@GOTPAGE
Lloh165:
	ldr	x8, [x8, _CB_PERFCOUNTER3_SELECT1@GOTPAGEOFF]
Lloh166:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh167:
	adrp	x19, _HDP_MISC_CNTL@GOTPAGE
Lloh168:
	ldr	x19, [x19, _HDP_MISC_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32
Lloh169:
	adrp	x8, _HDP_FLUSH_INVALIDATE_CACHE@GOTPAGE
Lloh170:
	ldr	x8, [x8, _HDP_FLUSH_INVALIDATE_CACHE@GOTPAGEOFF]
Lloh171:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x19]
	bl	_WREG32
Lloh172:
	adrp	x19, _HDP_HOST_PATH_CNTL@GOTPAGE
Lloh173:
	ldr	x19, [x19, _HDP_HOST_PATH_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32
	mov	x1, x0
	ldr	w0, [x19]
	bl	_WREG32
Lloh174:
	adrp	x8, _PA_CL_ENHANCE@GOTPAGE
Lloh175:
	ldr	x8, [x8, _PA_CL_ENHANCE@GOTPAGEOFF]
Lloh176:
	ldr	w19, [x8]
Lloh177:
	adrp	x8, _CLIP_VTX_REORDER_ENA@GOTPAGE
Lloh178:
	ldr	x8, [x8, _CLIP_VTX_REORDER_ENA@GOTPAGEOFF]
Lloh179:
	ldr	w20, [x8]
	mov	w0, #3
	bl	_NUM_CLIP_SEQ
	orr	w1, w0, w20
	mov	x0, x19
	bl	_WREG32
	mov	w0, #50
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_udelay
	.loh AdrpAdd	Lloh14, Lloh15
	.loh AdrpAdd	Lloh12, Lloh13
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdr	Lloh20, Lloh21
	.loh AdrpLdr	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh54, Lloh55
	.loh AdrpLdr	Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh35
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpAdd	Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGot	Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh177, Lloh178, Lloh179
	.loh AdrpLdrGotLdr	Lloh174, Lloh175, Lloh176
	.loh AdrpLdrGot	Lloh172, Lloh173
	.loh AdrpLdrGotLdr	Lloh169, Lloh170, Lloh171
	.loh AdrpLdrGot	Lloh167, Lloh168
	.loh AdrpLdrGotLdr	Lloh164, Lloh165, Lloh166
	.loh AdrpLdrGotLdr	Lloh161, Lloh162, Lloh163
	.loh AdrpLdrGotLdr	Lloh158, Lloh159, Lloh160
	.loh AdrpLdrGotLdr	Lloh155, Lloh156, Lloh157
	.loh AdrpLdrGotLdr	Lloh152, Lloh153, Lloh154
	.loh AdrpLdrGotLdr	Lloh149, Lloh150, Lloh151
	.loh AdrpLdrGotLdr	Lloh146, Lloh147, Lloh148
	.loh AdrpLdrGotLdr	Lloh143, Lloh144, Lloh145
	.loh AdrpLdrGotLdr	Lloh140, Lloh141, Lloh142
	.loh AdrpLdrGotLdr	Lloh137, Lloh138, Lloh139
	.loh AdrpLdrGotLdr	Lloh134, Lloh135, Lloh136
	.loh AdrpLdrGotLdr	Lloh131, Lloh132, Lloh133
	.loh AdrpLdrGotLdr	Lloh128, Lloh129, Lloh130
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGot	Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.cfi_endproc
                                        ; -- End function
	.comm	_TAHITI_GB_ADDR_CONFIG_GOLDEN,4,2 ; @TAHITI_GB_ADDR_CONFIG_GOLDEN
	.comm	_VERDE_GB_ADDR_CONFIG_GOLDEN,4,2 ; @VERDE_GB_ADDR_CONFIG_GOLDEN
	.comm	_HAINAN_GB_ADDR_CONFIG_GOLDEN,4,2 ; @HAINAN_GB_ADDR_CONFIG_GOLDEN
	.comm	_GRBM_CNTL,4,2                  ; @GRBM_CNTL
	.comm	_SRBM_INT_CNTL,4,2              ; @SRBM_INT_CNTL
	.comm	_SRBM_INT_ACK,4,2               ; @SRBM_INT_ACK
	.comm	_BIF_FB_EN,4,2                  ; @BIF_FB_EN
	.comm	_FB_READ_EN,4,2                 ; @FB_READ_EN
	.comm	_FB_WRITE_EN,4,2                ; @FB_WRITE_EN
	.comm	_MC_SHARED_CHMAP,4,2            ; @MC_SHARED_CHMAP
	.comm	_MC_ARB_RAMCFG,4,2              ; @MC_ARB_RAMCFG
	.comm	_NOOFCOLS_MASK,4,2              ; @NOOFCOLS_MASK
	.comm	_NOOFCOLS_SHIFT,4,2             ; @NOOFCOLS_SHIFT
	.comm	_ROW_SIZE_MASK,4,2              ; @ROW_SIZE_MASK
	.comm	_NOOFBANK_MASK,4,2              ; @NOOFBANK_MASK
	.comm	_NOOFBANK_SHIFT,4,2             ; @NOOFBANK_SHIFT
	.comm	_PIPE_INTERLEAVE_SIZE_MASK,4,2  ; @PIPE_INTERLEAVE_SIZE_MASK
	.comm	_PIPE_INTERLEAVE_SIZE_SHIFT,4,2 ; @PIPE_INTERLEAVE_SIZE_SHIFT
	.comm	_ROW_SIZE_SHIFT,4,2             ; @ROW_SIZE_SHIFT
	.comm	_GB_ADDR_CONFIG,4,2             ; @GB_ADDR_CONFIG
	.comm	_DMIF_ADDR_CONFIG,4,2           ; @DMIF_ADDR_CONFIG
	.comm	_DMIF_ADDR_CALC,4,2             ; @DMIF_ADDR_CALC
	.comm	_HDP_ADDR_CONFIG,4,2            ; @HDP_ADDR_CONFIG
	.comm	_DMA_TILING_CONFIG,4,2          ; @DMA_TILING_CONFIG
	.comm	_DMA0_REGISTER_OFFSET,4,2       ; @DMA0_REGISTER_OFFSET
	.comm	_DMA1_REGISTER_OFFSET,4,2       ; @DMA1_REGISTER_OFFSET
	.comm	_UVD_UDEC_ADDR_CONFIG,4,2       ; @UVD_UDEC_ADDR_CONFIG
	.comm	_UVD_UDEC_DB_ADDR_CONFIG,4,2    ; @UVD_UDEC_DB_ADDR_CONFIG
	.comm	_UVD_UDEC_DBW_ADDR_CONFIG,4,2   ; @UVD_UDEC_DBW_ADDR_CONFIG
	.comm	_CP_QUEUE_THRESHOLDS,4,2        ; @CP_QUEUE_THRESHOLDS
	.comm	_CP_MEQ_THRESHOLDS,4,2          ; @CP_MEQ_THRESHOLDS
	.comm	_SX_DEBUG_1,4,2                 ; @SX_DEBUG_1
	.comm	_SPI_CONFIG_CNTL_1,4,2          ; @SPI_CONFIG_CNTL_1
	.comm	_PA_SC_FIFO_SIZE,4,2            ; @PA_SC_FIFO_SIZE
	.comm	_VGT_NUM_INSTANCES,4,2          ; @VGT_NUM_INSTANCES
	.comm	_CP_PERFMON_CNTL,4,2            ; @CP_PERFMON_CNTL
	.comm	_SQ_CONFIG,4,2                  ; @SQ_CONFIG
	.comm	_PA_SC_FORCE_EOV_MAX_CNTS,4,2   ; @PA_SC_FORCE_EOV_MAX_CNTS
	.comm	_VGT_CACHE_INVALIDATION,4,2     ; @VGT_CACHE_INVALIDATION
	.comm	_VC_AND_TC,4,2                  ; @VC_AND_TC
	.comm	_ES_AND_GS_AUTO,4,2             ; @ES_AND_GS_AUTO
	.comm	_VGT_GS_VERTEX_REUSE,4,2        ; @VGT_GS_VERTEX_REUSE
	.comm	_PA_SC_LINE_STIPPLE_STATE,4,2   ; @PA_SC_LINE_STIPPLE_STATE
	.comm	_CB_PERFCOUNTER0_SELECT0,4,2    ; @CB_PERFCOUNTER0_SELECT0
	.comm	_CB_PERFCOUNTER0_SELECT1,4,2    ; @CB_PERFCOUNTER0_SELECT1
	.comm	_CB_PERFCOUNTER1_SELECT0,4,2    ; @CB_PERFCOUNTER1_SELECT0
	.comm	_CB_PERFCOUNTER1_SELECT1,4,2    ; @CB_PERFCOUNTER1_SELECT1
	.comm	_CB_PERFCOUNTER2_SELECT0,4,2    ; @CB_PERFCOUNTER2_SELECT0
	.comm	_CB_PERFCOUNTER2_SELECT1,4,2    ; @CB_PERFCOUNTER2_SELECT1
	.comm	_CB_PERFCOUNTER3_SELECT0,4,2    ; @CB_PERFCOUNTER3_SELECT0
	.comm	_CB_PERFCOUNTER3_SELECT1,4,2    ; @CB_PERFCOUNTER3_SELECT1
	.comm	_HDP_MISC_CNTL,4,2              ; @HDP_MISC_CNTL
	.comm	_HDP_FLUSH_INVALIDATE_CACHE,4,2 ; @HDP_FLUSH_INVALIDATE_CACHE
	.comm	_HDP_HOST_PATH_CNTL,4,2         ; @HDP_HOST_PATH_CNTL
	.comm	_PA_CL_ENHANCE,4,2              ; @PA_CL_ENHANCE
	.comm	_CLIP_VTX_REORDER_ENA,4,2       ; @CLIP_VTX_REORDER_ENA
	.no_dead_strip	_si_gpu_init
	.section	__TEXT,__literal16,16byte_literals
	.p2align	2                               ; @switch.table.si_gpu_init.1
l_switch.table.si_gpu_init.1:
	.long	12                              ; 0xc
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	4                               ; 0x4

	.p2align	2                               ; @switch.table.si_gpu_init.2
l_switch.table.si_gpu_init.2:
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	6                               ; 0x6
	.long	5                               ; 0x5

	.p2align	2                               ; @switch.table.si_gpu_init.3
l_switch.table.si_gpu_init.3:
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	1                               ; 0x1

	.p2align	2                               ; @switch.table.si_gpu_init.4
l_switch.table.si_gpu_init.4:
	.long	4                               ; 0x4
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	1                               ; 0x1

	.p2align	2                               ; @switch.table.si_gpu_init.5
l_switch.table.si_gpu_init.5:
	.long	12                              ; 0xc
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	2                               ; 0x2

	.p2align	2                               ; @switch.table.si_gpu_init.6
l_switch.table.si_gpu_init.6:
	.long	32                              ; 0x20
	.long	32                              ; 0x20
	.long	16                              ; 0x10
	.long	16                              ; 0x10

	.p2align	2                               ; @switch.table.si_gpu_init.7
l_switch.table.si_gpu_init.7:
	.long	256                             ; 0x100
	.long	256                             ; 0x100
	.long	64                              ; 0x40
	.long	64                              ; 0x40

	.section	__DATA,__const
	.p2align	3                               ; @switch.table.si_gpu_init.8
l_switch.table.si_gpu_init.8:
	.quad	_TAHITI_GB_ADDR_CONFIG_GOLDEN
	.quad	_TAHITI_GB_ADDR_CONFIG_GOLDEN
	.quad	_VERDE_GB_ADDR_CONFIG_GOLDEN
	.quad	_HAINAN_GB_ADDR_CONFIG_GOLDEN

	.section	__TEXT,__literal16,16byte_literals
	.p2align	2                               ; @switch.table.si_gpu_init.9
l_switch.table.si_gpu_init.9:
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	3                               ; 0x3
	.long	2                               ; 0x2

.subsections_via_symbols
