	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v1_0_dec_ring_emit_reg_wait
_vcn_v1_0_dec_ring_emit_reg_wait:       ## @vcn_v1_0_dec_ring_emit_reg_wait
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %r14d
	movl	%edx, %r15d
	movl	%esi, %ebx
	movq	%rdi, %r12
	movq	_UVD@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movq	_mmUVD_GPCOM_VCPU_DATA0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	shll	$2, %ebx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_GPCOM_VCPU_DATA1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r12, %rdi
	movl	%r15d, %esi
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_GP_SCRATCH8@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_GPCOM_VCPU_CMD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_VCN_DEC_CMD_REG_READ_COND_WAIT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%esi, %esi
	movq	%r12, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_write              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_GPCOM_VCPU_DATA0,4,2     ## @mmUVD_GPCOM_VCPU_DATA0
	.comm	_mmUVD_GPCOM_VCPU_DATA1,4,2     ## @mmUVD_GPCOM_VCPU_DATA1
	.comm	_mmUVD_GP_SCRATCH8,4,2          ## @mmUVD_GP_SCRATCH8
	.comm	_mmUVD_GPCOM_VCPU_CMD,4,2       ## @mmUVD_GPCOM_VCPU_CMD
	.comm	_VCN_DEC_CMD_REG_READ_COND_WAIT,4,2 ## @VCN_DEC_CMD_REG_READ_COND_WAIT
	.no_dead_strip	_vcn_v1_0_dec_ring_emit_reg_wait
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v1_0_dec_ring_emit_reg_wait
_vcn_v1_0_dec_ring_emit_reg_wait:       ; @vcn_v1_0_dec_ring_emit_reg_wait
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x3
	mov	x21, x2
	mov	x22, x1
	mov	x19, x0
Lloh0:
	adrp	x23, _UVD@GOTPAGE
Lloh1:
	ldr	x23, [x23, _UVD@GOTPAGEOFF]
	ldr	w0, [x23]
Lloh2:
	adrp	x8, _mmUVD_GPCOM_VCPU_DATA0@GOTPAGE
Lloh3:
	ldr	x8, [x8, _mmUVD_GPCOM_VCPU_DATA0@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	lsl	w1, w22, #2
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x23]
Lloh5:
	adrp	x8, _mmUVD_GPCOM_VCPU_DATA1@GOTPAGE
Lloh6:
	ldr	x8, [x8, _mmUVD_GPCOM_VCPU_DATA1@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	x1, x21
	bl	_amdgpu_ring_write
	ldr	w0, [x23]
Lloh8:
	adrp	x8, _mmUVD_GP_SCRATCH8@GOTPAGE
Lloh9:
	ldr	x8, [x8, _mmUVD_GP_SCRATCH8@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_ring_write
	ldr	w0, [x23]
Lloh11:
	adrp	x8, _mmUVD_GPCOM_VCPU_CMD@GOTPAGE
Lloh12:
	ldr	x8, [x8, _mmUVD_GPCOM_VCPU_CMD@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh14:
	adrp	x8, _VCN_DEC_CMD_REG_READ_COND_WAIT@GOTPAGE
Lloh15:
	ldr	x8, [x8, _VCN_DEC_CMD_REG_READ_COND_WAIT@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
	lsl	w1, w8, #1
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_amdgpu_ring_write
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_GPCOM_VCPU_DATA0,4,2     ; @mmUVD_GPCOM_VCPU_DATA0
	.comm	_mmUVD_GPCOM_VCPU_DATA1,4,2     ; @mmUVD_GPCOM_VCPU_DATA1
	.comm	_mmUVD_GP_SCRATCH8,4,2          ; @mmUVD_GP_SCRATCH8
	.comm	_mmUVD_GPCOM_VCPU_CMD,4,2       ; @mmUVD_GPCOM_VCPU_CMD
	.comm	_VCN_DEC_CMD_REG_READ_COND_WAIT,4,2 ; @VCN_DEC_CMD_REG_READ_COND_WAIT
	.no_dead_strip	_vcn_v1_0_dec_ring_emit_reg_wait
.subsections_via_symbols
