	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_card_posted             ## -- Begin function radeon_card_posted
	.p2align	4, 0x90
_radeon_card_posted:                    ## @radeon_card_posted
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	(%rdi), %rax
	movq	_CHIP_BONAIRE@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_2
## %bb.1:
	xorl	%ebx, %ebx
	xorl	%eax, %eax
	callq	_radeon_device_is_virtual
	testq	%rax, %rax
	jne	LBB0_19
LBB0_2:
	movq	_EFI_BOOT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_efi_enabled
	testq	%rax, %rax
	je	LBB0_5
## %bb.3:
	movq	16(%r15), %rax
	movq	(%rax), %rax
	movq	_PCI_VENDOR_ID_APPLE@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_5
## %bb.4:
	movq	(%r15), %rax
	movq	_CHIP_R600@GOTPCREL(%rip), %rcx
	xorl	%ebx, %ebx
	cmpq	(%rcx), %rax
	jl	LBB0_19
LBB0_5:
	movq	%r15, %rdi
	callq	_ASIC_IS_NODCE
	testq	%rax, %rax
	je	LBB0_6
LBB0_15:
	movq	(%r15), %rax
	movq	_CHIP_R600@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_16
## %bb.17:
	movq	_RADEON_CONFIG_MEMSIZE@GOTPCREL(%rip), %rax
	jmp	LBB0_18
LBB0_16:
	movq	_R600_CONFIG_MEMSIZE@GOTPCREL(%rip), %rax
LBB0_18:
	movq	(%rax), %rdi
	callq	_RREG32
	xorl	%ebx, %ebx
	testl	%eax, %eax
	setne	%bl
LBB0_19:
	movl	%ebx, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_6:
	movq	%r15, %rdi
	callq	_ASIC_IS_DCE4
	testq	%rax, %rax
	je	LBB0_11
## %bb.7:
	movq	_EVERGREEN_CRTC_CONTROL@GOTPCREL(%rip), %r12
	movq	_EVERGREEN_CRTC0_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r12), %rdi
	callq	_RREG32
	movl	%eax, %ebx
	movq	_EVERGREEN_CRTC1_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r12), %rdi
	callq	_RREG32
	movl	%eax, %r14d
	orl	%ebx, %r14d
	cmpl	$4, 8(%r15)
	jl	LBB0_10
## %bb.8:
	movq	_EVERGREEN_CRTC2_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r12), %rdi
	callq	_RREG32
	movl	%eax, %ebx
	movq	_EVERGREEN_CRTC3_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r12), %rdi
	callq	_RREG32
	orl	%ebx, %r14d
	orl	%eax, %r14d
	cmpl	$6, 8(%r15)
	jl	LBB0_10
## %bb.9:
	movq	_EVERGREEN_CRTC4_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r12), %rdi
	callq	_RREG32
	movl	%eax, %ebx
	movq	_EVERGREEN_CRTC5_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r12), %rdi
	callq	_RREG32
	orl	%r14d, %ebx
	orl	%eax, %ebx
	movl	%ebx, %r14d
LBB0_10:
	movq	_EVERGREEN_CRTC_MASTER_EN@GOTPCREL(%rip), %rax
	movl	$1, %ebx
	testl	%r14d, (%rax)
	jne	LBB0_19
	jmp	LBB0_15
LBB0_11:
	movq	%r15, %rdi
	callq	_ASIC_IS_AVIVO
	testq	%rax, %rax
	je	LBB0_13
## %bb.12:
	movq	_AVIVO_D1CRTC_CONTROL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %ebx
	movq	_AVIVO_D2CRTC_CONTROL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	orl	%ebx, %eax
	movq	_AVIVO_CRTC_EN@GOTPCREL(%rip), %rcx
	jmp	LBB0_14
LBB0_13:
	movq	_RADEON_CRTC_GEN_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %ebx
	movq	_RADEON_CRTC2_GEN_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	orl	%ebx, %eax
	movq	_RADEON_CRTC_EN@GOTPCREL(%rip), %rcx
LBB0_14:
	movl	$1, %ebx
	testl	%eax, (%rcx)
	jne	LBB0_19
	jmp	LBB0_15
	.cfi_endproc
                                        ## -- End function
	.comm	_CHIP_BONAIRE,8,3               ## @CHIP_BONAIRE
	.comm	_EFI_BOOT,4,2                   ## @EFI_BOOT
	.comm	_PCI_VENDOR_ID_APPLE,8,3        ## @PCI_VENDOR_ID_APPLE
	.comm	_CHIP_R600,8,3                  ## @CHIP_R600
	.comm	_EVERGREEN_CRTC_CONTROL,8,3     ## @EVERGREEN_CRTC_CONTROL
	.comm	_EVERGREEN_CRTC0_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC0_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC1_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC1_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC2_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC2_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC3_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC3_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC4_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC4_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC5_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC5_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC_MASTER_EN,4,2   ## @EVERGREEN_CRTC_MASTER_EN
	.comm	_AVIVO_D1CRTC_CONTROL,8,3       ## @AVIVO_D1CRTC_CONTROL
	.comm	_AVIVO_D2CRTC_CONTROL,8,3       ## @AVIVO_D2CRTC_CONTROL
	.comm	_AVIVO_CRTC_EN,4,2              ## @AVIVO_CRTC_EN
	.comm	_RADEON_CRTC_GEN_CNTL,8,3       ## @RADEON_CRTC_GEN_CNTL
	.comm	_RADEON_CRTC2_GEN_CNTL,8,3      ## @RADEON_CRTC2_GEN_CNTL
	.comm	_RADEON_CRTC_EN,4,2             ## @RADEON_CRTC_EN
	.comm	_R600_CONFIG_MEMSIZE,8,3        ## @R600_CONFIG_MEMSIZE
	.comm	_RADEON_CONFIG_MEMSIZE,8,3      ## @RADEON_CONFIG_MEMSIZE
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_card_posted             ; -- Begin function radeon_card_posted
	.p2align	2
_radeon_card_posted:                    ; @radeon_card_posted
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x8, [x0]
Lloh0:
	adrp	x9, _CHIP_BONAIRE@GOTPAGE
Lloh1:
	ldr	x9, [x9, _CHIP_BONAIRE@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	b.lt	LBB0_2
; %bb.1:
	bl	_radeon_device_is_virtual
	cbnz	x0, LBB0_5
LBB0_2:
Lloh3:
	adrp	x8, _EFI_BOOT@GOTPAGE
Lloh4:
	ldr	x8, [x8, _EFI_BOOT@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	bl	_efi_enabled
	cbz	x0, LBB0_6
; %bb.3:
	ldr	x8, [x19, #16]
	ldr	x8, [x8]
Lloh6:
	adrp	x9, _PCI_VENDOR_ID_APPLE@GOTPAGE
Lloh7:
	ldr	x9, [x9, _PCI_VENDOR_ID_APPLE@GOTPAGEOFF]
Lloh8:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_6
; %bb.4:
	ldr	x8, [x19]
Lloh9:
	adrp	x9, _CHIP_R600@GOTPAGE
Lloh10:
	ldr	x9, [x9, _CHIP_R600@GOTPAGEOFF]
Lloh11:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_6
LBB0_5:
	mov	w0, #0
	b	LBB0_18
LBB0_6:
	mov	x0, x19
	bl	_ASIC_IS_NODCE
	cbz	x0, LBB0_8
LBB0_7:
	ldr	x8, [x19]
Lloh12:
	adrp	x9, _CHIP_R600@GOTPAGE
Lloh13:
	ldr	x9, [x9, _CHIP_R600@GOTPAGEOFF]
Lloh14:
	adrp	x10, _RADEON_CONFIG_MEMSIZE@GOTPAGE
Lloh15:
	ldr	x10, [x10, _RADEON_CONFIG_MEMSIZE@GOTPAGEOFF]
Lloh16:
	ldr	x9, [x9]
Lloh17:
	adrp	x11, _R600_CONFIG_MEMSIZE@GOTPAGE
Lloh18:
	ldr	x11, [x11, _R600_CONFIG_MEMSIZE@GOTPAGEOFF]
	cmp	x8, x9
	csel	x8, x10, x11, lt
	ldr	x0, [x8]
	bl	_RREG32
	cmp	w0, #0
	cset	w0, ne
	b	LBB0_18
LBB0_8:
	mov	x0, x19
	bl	_ASIC_IS_DCE4
	cbz	x0, LBB0_13
; %bb.9:
Lloh19:
	adrp	x21, _EVERGREEN_CRTC_CONTROL@GOTPAGE
Lloh20:
	ldr	x21, [x21, _EVERGREEN_CRTC_CONTROL@GOTPAGEOFF]
	ldr	x8, [x21]
Lloh21:
	adrp	x9, _EVERGREEN_CRTC0_REGISTER_OFFSET@GOTPAGE
Lloh22:
	ldr	x9, [x9, _EVERGREEN_CRTC0_REGISTER_OFFSET@GOTPAGEOFF]
Lloh23:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_RREG32
	mov	x20, x0
	ldr	x8, [x21]
Lloh24:
	adrp	x9, _EVERGREEN_CRTC1_REGISTER_OFFSET@GOTPAGE
Lloh25:
	ldr	x9, [x9, _EVERGREEN_CRTC1_REGISTER_OFFSET@GOTPAGEOFF]
Lloh26:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_RREG32
	orr	w22, w0, w20
	ldr	w8, [x19, #8]
	cmp	w8, #4
	b.lt	LBB0_12
; %bb.10:
	ldr	x8, [x21]
Lloh27:
	adrp	x9, _EVERGREEN_CRTC2_REGISTER_OFFSET@GOTPAGE
Lloh28:
	ldr	x9, [x9, _EVERGREEN_CRTC2_REGISTER_OFFSET@GOTPAGEOFF]
Lloh29:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_RREG32
	mov	x20, x0
	ldr	x8, [x21]
Lloh30:
	adrp	x9, _EVERGREEN_CRTC3_REGISTER_OFFSET@GOTPAGE
Lloh31:
	ldr	x9, [x9, _EVERGREEN_CRTC3_REGISTER_OFFSET@GOTPAGEOFF]
Lloh32:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_RREG32
	orr	w8, w20, w22
	orr	w22, w8, w0
	ldr	w8, [x19, #8]
	cmp	w8, #6
	b.lt	LBB0_12
; %bb.11:
	ldr	x8, [x21]
Lloh33:
	adrp	x9, _EVERGREEN_CRTC4_REGISTER_OFFSET@GOTPAGE
Lloh34:
	ldr	x9, [x9, _EVERGREEN_CRTC4_REGISTER_OFFSET@GOTPAGEOFF]
Lloh35:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_RREG32
	mov	x20, x0
	ldr	x8, [x21]
Lloh36:
	adrp	x9, _EVERGREEN_CRTC5_REGISTER_OFFSET@GOTPAGE
Lloh37:
	ldr	x9, [x9, _EVERGREEN_CRTC5_REGISTER_OFFSET@GOTPAGEOFF]
Lloh38:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_RREG32
	orr	w8, w20, w22
	orr	w22, w8, w0
LBB0_12:
Lloh39:
	adrp	x8, _EVERGREEN_CRTC_MASTER_EN@GOTPAGE
Lloh40:
	ldr	x8, [x8, _EVERGREEN_CRTC_MASTER_EN@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
	tst	w8, w22
	b.ne	LBB0_17
	b	LBB0_7
LBB0_13:
	mov	x0, x19
	bl	_ASIC_IS_AVIVO
	cbz	x0, LBB0_15
; %bb.14:
Lloh42:
	adrp	x8, _AVIVO_D1CRTC_CONTROL@GOTPAGE
Lloh43:
	ldr	x8, [x8, _AVIVO_D1CRTC_CONTROL@GOTPAGEOFF]
Lloh44:
	ldr	x0, [x8]
	bl	_RREG32
	mov	x20, x0
Lloh45:
	adrp	x8, _AVIVO_D2CRTC_CONTROL@GOTPAGE
Lloh46:
	ldr	x8, [x8, _AVIVO_D2CRTC_CONTROL@GOTPAGEOFF]
Lloh47:
	ldr	x0, [x8]
	bl	_RREG32
	orr	w8, w0, w20
Lloh48:
	adrp	x9, _AVIVO_CRTC_EN@GOTPAGE
Lloh49:
	ldr	x9, [x9, _AVIVO_CRTC_EN@GOTPAGEOFF]
	b	LBB0_16
LBB0_15:
Lloh50:
	adrp	x8, _RADEON_CRTC_GEN_CNTL@GOTPAGE
Lloh51:
	ldr	x8, [x8, _RADEON_CRTC_GEN_CNTL@GOTPAGEOFF]
Lloh52:
	ldr	x0, [x8]
	bl	_RREG32
	mov	x20, x0
Lloh53:
	adrp	x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGE
Lloh54:
	ldr	x8, [x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGEOFF]
Lloh55:
	ldr	x0, [x8]
	bl	_RREG32
	orr	w8, w0, w20
Lloh56:
	adrp	x9, _RADEON_CRTC_EN@GOTPAGE
Lloh57:
	ldr	x9, [x9, _RADEON_CRTC_EN@GOTPAGEOFF]
LBB0_16:
	ldr	w9, [x9]
	tst	w8, w9
	b.eq	LBB0_7
LBB0_17:
	mov	w0, #1
LBB0_18:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh16
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.cfi_endproc
                                        ; -- End function
	.comm	_CHIP_BONAIRE,8,3               ; @CHIP_BONAIRE
	.comm	_EFI_BOOT,4,2                   ; @EFI_BOOT
	.comm	_PCI_VENDOR_ID_APPLE,8,3        ; @PCI_VENDOR_ID_APPLE
	.comm	_CHIP_R600,8,3                  ; @CHIP_R600
	.comm	_EVERGREEN_CRTC_CONTROL,8,3     ; @EVERGREEN_CRTC_CONTROL
	.comm	_EVERGREEN_CRTC0_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC0_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC1_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC1_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC2_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC2_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC3_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC3_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC4_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC4_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC5_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC5_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC_MASTER_EN,4,2   ; @EVERGREEN_CRTC_MASTER_EN
	.comm	_AVIVO_D1CRTC_CONTROL,8,3       ; @AVIVO_D1CRTC_CONTROL
	.comm	_AVIVO_D2CRTC_CONTROL,8,3       ; @AVIVO_D2CRTC_CONTROL
	.comm	_AVIVO_CRTC_EN,4,2              ; @AVIVO_CRTC_EN
	.comm	_RADEON_CRTC_GEN_CNTL,8,3       ; @RADEON_CRTC_GEN_CNTL
	.comm	_RADEON_CRTC2_GEN_CNTL,8,3      ; @RADEON_CRTC2_GEN_CNTL
	.comm	_RADEON_CRTC_EN,4,2             ; @RADEON_CRTC_EN
	.comm	_R600_CONFIG_MEMSIZE,8,3        ; @R600_CONFIG_MEMSIZE
	.comm	_RADEON_CONFIG_MEMSIZE,8,3      ; @RADEON_CONFIG_MEMSIZE
.subsections_via_symbols
