	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function etnaviv_iommuv2_restore_sec
_etnaviv_iommuv2_restore_sec:           ## @etnaviv_iommuv2_restore_sec
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %r13
	movq	%rsi, %rdi
	callq	_to_v2_context
	movq	%rax, %r15
	movq	_VIVS_MMUv2_SEC_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_gpu_read
	movq	_VIVS_MMUv2_SEC_CONTROL_ENABLE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_2
## %bb.1:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	movq	_VIVS_MMUv2_PTA_ADDRESS_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	(%r14), %rax
	movl	8(%rax), %edi
	callq	_lower_32_bits
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movq	_VIVS_MMUv2_PTA_ADDRESS_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	(%r14), %rax
	movl	8(%rax), %edi
	callq	_upper_32_bits
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movq	_VIVS_MMUv2_PTA_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_VIVS_MMUv2_PTA_CONTROL_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	callq	_gpu_write
	movq	_VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	(%r14), %rax
	movl	16(%rax), %edi
	callq	_lower_32_bits
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movq	_VIVS_MMUv2_SEC_SAFE_ADDR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	(%r14), %rax
	movl	16(%rax), %edi
	callq	_lower_32_bits
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movq	_VIVS_MMUv2_SAFE_ADDRESS_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	(%r14), %rax
	movl	16(%rax), %edi
	callq	_upper_32_bits
	movl	%eax, %edi
	callq	_VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH
	movl	%eax, %ebx
	movq	(%r14), %rax
	movl	16(%rax), %edi
	callq	_upper_32_bits
	movl	%eax, %edi
	callq	_VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH
	orl	%eax, %ebx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%ebx, %edx
	callq	_gpu_write
	movq	_VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	8(%r15), %eax
	movq	(%r14), %rcx
	movq	(%rcx), %rcx
	movq	(%r15), %rsi
	movl	%eax, (%rcx,%rsi,4)
	movq	%r13, %rdi
	callq	_etnaviv_buffer_config_pta
	movl	%eax, %ebx
	movq	%r13, %rdi
	callq	_etnaviv_cmdbuf_get_pa
	movq	%r13, %rdi
	movl	%eax, %esi
	movl	%ebx, %edx
	callq	_etnaviv_gpu_start_fe
	movq	%r13, %rdi
	movl	$100, %esi
	callq	_etnaviv_gpu_wait_idle
	movq	_VIVS_MMUv2_SEC_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_VIVS_MMUv2_SEC_CONTROL_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_gpu_write                      ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_VIVS_MMUv2_SEC_CONTROL,4,2     ## @VIVS_MMUv2_SEC_CONTROL
	.comm	_VIVS_MMUv2_SEC_CONTROL_ENABLE,4,2 ## @VIVS_MMUv2_SEC_CONTROL_ENABLE
	.comm	_VIVS_MMUv2_PTA_ADDRESS_LOW,4,2 ## @VIVS_MMUv2_PTA_ADDRESS_LOW
	.comm	_VIVS_MMUv2_PTA_ADDRESS_HIGH,4,2 ## @VIVS_MMUv2_PTA_ADDRESS_HIGH
	.comm	_VIVS_MMUv2_PTA_CONTROL,4,2     ## @VIVS_MMUv2_PTA_CONTROL
	.comm	_VIVS_MMUv2_PTA_CONTROL_ENABLE,4,2 ## @VIVS_MMUv2_PTA_CONTROL_ENABLE
	.comm	_VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW,4,2 ## @VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW
	.comm	_VIVS_MMUv2_SEC_SAFE_ADDR_LOW,4,2 ## @VIVS_MMUv2_SEC_SAFE_ADDR_LOW
	.comm	_VIVS_MMUv2_SAFE_ADDRESS_CONFIG,4,2 ## @VIVS_MMUv2_SAFE_ADDRESS_CONFIG
	.comm	_VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K,4,2 ## @VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K
	.no_dead_strip	_etnaviv_iommuv2_restore_sec
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function etnaviv_iommuv2_restore_sec
_etnaviv_iommuv2_restore_sec:           ; @etnaviv_iommuv2_restore_sec
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x1
	mov	x19, x0
	mov	x0, x1
	bl	_to_v2_context
	mov	x21, x0
Lloh0:
	adrp	x24, _VIVS_MMUv2_SEC_CONTROL@GOTPAGE
Lloh1:
	ldr	x24, [x24, _VIVS_MMUv2_SEC_CONTROL@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	x0, x19
	bl	_gpu_read
Lloh2:
	adrp	x25, _VIVS_MMUv2_SEC_CONTROL_ENABLE@GOTPAGE
Lloh3:
	ldr	x25, [x25, _VIVS_MMUv2_SEC_CONTROL_ENABLE@GOTPAGEOFF]
	ldr	w8, [x25]
	tst	w8, w0
	b.eq	LBB0_2
; %bb.1:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_2:
Lloh4:
	adrp	x8, _VIVS_MMUv2_PTA_ADDRESS_LOW@GOTPAGE
Lloh5:
	ldr	x8, [x8, _VIVS_MMUv2_PTA_ADDRESS_LOW@GOTPAGEOFF]
Lloh6:
	ldr	w22, [x8]
	ldr	x8, [x20]
	ldr	w0, [x8, #8]
	bl	_lower_32_bits
	mov	x2, x0
	mov	x0, x19
	mov	x1, x22
	bl	_gpu_write
Lloh7:
	adrp	x8, _VIVS_MMUv2_PTA_ADDRESS_HIGH@GOTPAGE
Lloh8:
	ldr	x8, [x8, _VIVS_MMUv2_PTA_ADDRESS_HIGH@GOTPAGEOFF]
Lloh9:
	ldr	w22, [x8]
	ldr	x8, [x20]
	ldr	w0, [x8, #8]
	bl	_upper_32_bits
	mov	x2, x0
	mov	x0, x19
	mov	x1, x22
	bl	_gpu_write
Lloh10:
	adrp	x8, _VIVS_MMUv2_PTA_CONTROL@GOTPAGE
Lloh11:
	ldr	x8, [x8, _VIVS_MMUv2_PTA_CONTROL@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
Lloh13:
	adrp	x8, _VIVS_MMUv2_PTA_CONTROL_ENABLE@GOTPAGE
Lloh14:
	ldr	x8, [x8, _VIVS_MMUv2_PTA_CONTROL_ENABLE@GOTPAGEOFF]
Lloh15:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_gpu_write
Lloh16:
	adrp	x8, _VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW@GOTPAGE
Lloh17:
	ldr	x8, [x8, _VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW@GOTPAGEOFF]
Lloh18:
	ldr	w22, [x8]
	ldr	x8, [x20]
	ldr	w0, [x8, #16]
	bl	_lower_32_bits
	mov	x2, x0
	mov	x0, x19
	mov	x1, x22
	bl	_gpu_write
Lloh19:
	adrp	x8, _VIVS_MMUv2_SEC_SAFE_ADDR_LOW@GOTPAGE
Lloh20:
	ldr	x8, [x8, _VIVS_MMUv2_SEC_SAFE_ADDR_LOW@GOTPAGEOFF]
Lloh21:
	ldr	w22, [x8]
	ldr	x8, [x20]
	ldr	w0, [x8, #16]
	bl	_lower_32_bits
	mov	x2, x0
	mov	x0, x19
	mov	x1, x22
	bl	_gpu_write
Lloh22:
	adrp	x8, _VIVS_MMUv2_SAFE_ADDRESS_CONFIG@GOTPAGE
Lloh23:
	ldr	x8, [x8, _VIVS_MMUv2_SAFE_ADDRESS_CONFIG@GOTPAGEOFF]
Lloh24:
	ldr	w22, [x8]
	ldr	x8, [x20]
	ldr	w0, [x8, #16]
	bl	_upper_32_bits
	bl	_VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH
	mov	x23, x0
	ldr	x8, [x20]
	ldr	w0, [x8, #16]
	bl	_upper_32_bits
	bl	_VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH
	orr	w2, w0, w23
	mov	x0, x19
	mov	x1, x22
	bl	_gpu_write
	ldr	w8, [x21, #8]
Lloh25:
	adrp	x9, _VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K@GOTPAGE
Lloh26:
	ldr	x9, [x9, _VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
	orr	w8, w9, w8
	ldr	x9, [x20]
	ldr	x9, [x9]
	ldr	x1, [x21]
	str	w8, [x9, x1, lsl #2]
	mov	x0, x19
	bl	_etnaviv_buffer_config_pta
	mov	x20, x0
	mov	x0, x19
	bl	_etnaviv_cmdbuf_get_pa
	mov	x1, x0
	mov	x0, x19
                                        ; kill: def $w1 killed $w1 killed $x1
	mov	x2, x20
	bl	_etnaviv_gpu_start_fe
	mov	x0, x19
	mov	w1, #100
	bl	_etnaviv_gpu_wait_idle
	ldr	w1, [x24]
	ldr	w2, [x25]
	mov	x0, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_gpu_write
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.cfi_endproc
                                        ; -- End function
	.comm	_VIVS_MMUv2_SEC_CONTROL,4,2     ; @VIVS_MMUv2_SEC_CONTROL
	.comm	_VIVS_MMUv2_SEC_CONTROL_ENABLE,4,2 ; @VIVS_MMUv2_SEC_CONTROL_ENABLE
	.comm	_VIVS_MMUv2_PTA_ADDRESS_LOW,4,2 ; @VIVS_MMUv2_PTA_ADDRESS_LOW
	.comm	_VIVS_MMUv2_PTA_ADDRESS_HIGH,4,2 ; @VIVS_MMUv2_PTA_ADDRESS_HIGH
	.comm	_VIVS_MMUv2_PTA_CONTROL,4,2     ; @VIVS_MMUv2_PTA_CONTROL
	.comm	_VIVS_MMUv2_PTA_CONTROL_ENABLE,4,2 ; @VIVS_MMUv2_PTA_CONTROL_ENABLE
	.comm	_VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW,4,2 ; @VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW
	.comm	_VIVS_MMUv2_SEC_SAFE_ADDR_LOW,4,2 ; @VIVS_MMUv2_SEC_SAFE_ADDR_LOW
	.comm	_VIVS_MMUv2_SAFE_ADDRESS_CONFIG,4,2 ; @VIVS_MMUv2_SAFE_ADDRESS_CONFIG
	.comm	_VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K,4,2 ; @VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K
	.no_dead_strip	_etnaviv_iommuv2_restore_sec
.subsections_via_symbols
