	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gmc_v6_0_gart_enable
_gmc_v6_0_gart_enable:                  ## @gmc_v6_0_gart_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	cmpq	$0, 16(%rdi)
	je	LBB0_1
## %bb.2:
	movq	%r12, %rdi
	callq	_amdgpu_gart_table_vram_pin
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	LBB0_4
## %bb.3:
	movq	16(%r12), %rdi
	callq	_amdgpu_bo_gpu_offset
	movl	%eax, %r14d
	movq	_mmMC_VM_MX_L1_TLB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK@GOTPCREL(%rip), %rcx
	movq	_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK@GOTPCREL(%rip), %rdx
	movq	_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK@GOTPCREL(%rip), %rsi
	orl	(%rcx), %eax
	orl	(%rdx), %eax
	orl	(%rsi), %eax
	movslq	%eax, %rsi
	orq	$1280, %rsi                     ## imm = 0x500
	callq	_WREG32
	movq	_mmVM_L2_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_VM_L2_CNTL__ENABLE_L2_CACHE_MASK@GOTPCREL(%rip), %rax
	movq	_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rdx
	orq	(%rax), %rdx
	movq	_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK@GOTPCREL(%rip), %rax
	orq	(%rax), %rdx
	movq	_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK@GOTPCREL(%rip), %rax
	orq	(%rax), %rdx
	movq	_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$7, %esi
	shlq	%cl, %rsi
	orq	%rdx, %rsi
	movq	_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	btsq	%rax, %rsi
	callq	_WREG32
	movq	_mmVM_L2_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK@GOTPCREL(%rip), %rax
	movq	_VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rsi
	orq	(%rax), %rsi
	callq	_WREG32
	movq	40(%r12), %rsi
	movq	_mmVM_L2_CNTL3@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK@GOTPCREL(%rip), %rax
	movq	_VM_L2_CNTL3__BANK_SELECT__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movq	%rsi, %rdx
	shlq	%cl, %rdx
	orq	(%rax), %rdx
	movq	_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shlq	%cl, %rsi
	orq	%rdx, %rsi
	callq	_WREG32
	movq	_mmVM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	24(%r12), %eax
	sarl	$12, %eax
	movslq	%eax, %rsi
	callq	_WREG32
	movq	_mmVM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	28(%r12), %eax
	sarl	$12, %eax
	movslq	%eax, %rsi
	callq	_WREG32
	movq	_mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movl	%r14d, %eax
	sarl	$12, %eax
	movslq	%eax, %rbx
	movq	%rbx, %rsi
	callq	_WREG32
	movq	_mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r12), %eax
	sarl	$12, %eax
	movslq	%eax, %rsi
	callq	_WREG32
	movq	_mmVM_CONTEXT0_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%r15d, %r15d
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT0_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK@GOTPCREL(%rip), %rax
	movq	_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rsi
	orq	(%rax), %rsi
	callq	_WREG32
	movl	$1397, %edi                     ## imm = 0x575
	xorl	%esi, %esi
	callq	_WREG32
	movl	$1398, %edi                     ## imm = 0x576
	xorl	%esi, %esi
	callq	_WREG32
	movl	$1399, %edi                     ## imm = 0x577
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT1_PAGE_TABLE_START_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT1_PAGE_TABLE_END_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movslq	48(%r12), %rsi
	decq	%rsi
	callq	_WREG32
	movl	(%r13), %edi
	incl	%edi
	movq	%rbx, %rsi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$2, %edi
	movq	%rbx, %rsi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$3, %edi
	movq	%rbx, %rsi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$4, %edi
	movq	%rbx, %rsi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$5, %edi
	movq	%rbx, %rsi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$6, %edi
	movq	%rbx, %rsi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$7, %edi
	movq	%rbx, %rsi
	callq	_WREG32
	movq	_mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movq	%rbx, %rsi
	callq	_WREG32
	movl	(%r13), %edi
	incl	%edi
	movq	%rbx, %rsi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$2, %edi
	movq	%rbx, %rsi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$3, %edi
	movq	%rbx, %rsi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$4, %edi
	movq	%rbx, %rsi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$5, %edi
	movq	%rbx, %rsi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$6, %edi
	movq	%rbx, %rsi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$7, %edi
	movq	%rbx, %rsi
	callq	_WREG32
	movq	_mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r12), %eax
	sarl	$12, %eax
	movslq	%eax, %rsi
	callq	_WREG32
	movq	_mmVM_CONTEXT1_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$4, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT1_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT@GOTPCREL(%rip), %rdx
	movq	_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	52(%r12), %esi
	addl	$-9, %esi
	shll	%cl, %esi
	movb	(%rdx), %cl
	btsq	%rcx, %rax
	movslq	%esi, %rsi
	orq	%rax, %rsi
	callq	_WREG32
	movq	_amdgpu_vm_fault_stop@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_AMDGPU_VM_FAULT_STOP_ALWAYS@GOTPCREL(%rip), %rcx
	xorl	%esi, %esi
	cmpq	(%rcx), %rax
	setne	%sil
	movq	%r12, %rdi
	callq	_gmc_v6_0_set_fault_enable_default
	movq	%r12, %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	callq	_gmc_v6_0_flush_gpu_tlb
	movl	32(%r12), %edx
	movl	36(%r12), %edi
	sarl	$20, %edx
	movslq	%r14d, %rcx
	leaq	L_.str.1(%rip), %rsi
	callq	_dev_info
	movl	$1, 8(%r12)
	jmp	LBB0_4
LBB0_1:
	movl	36(%r12), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r15d, %r15d
	subl	(%rax), %r15d
LBB0_4:
	movl	%r15d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"No VRAM object for PCIE GART.\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_mmMC_VM_MX_L1_TLB_CNTL,4,2     ## @mmMC_VM_MX_L1_TLB_CNTL
	.comm	_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK,4,2 ## @MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK
	.comm	_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK,4,2 ## @MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK
	.comm	_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK,4,2 ## @MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK
	.comm	_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK,4,2 ## @MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK
	.comm	_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT,8,3 ## @MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT
	.comm	_mmVM_L2_CNTL,4,2               ## @mmVM_L2_CNTL
	.comm	_VM_L2_CNTL__ENABLE_L2_CACHE_MASK,8,3 ## @VM_L2_CNTL__ENABLE_L2_CACHE_MASK
	.comm	_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK,8,3 ## @VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK
	.comm	_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK,8,3 ## @VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK
	.comm	_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK,8,3 ## @VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK
	.comm	_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT,8,3 ## @VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT
	.comm	_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT,8,3 ## @VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT
	.comm	_mmVM_L2_CNTL2,4,2              ## @mmVM_L2_CNTL2
	.comm	_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK,8,3 ## @VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK
	.comm	_VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK,8,3 ## @VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK
	.comm	_mmVM_L2_CNTL3,4,2              ## @mmVM_L2_CNTL3
	.comm	_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK,8,3 ## @VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK
	.comm	_VM_L2_CNTL3__BANK_SELECT__SHIFT,8,3 ## @VM_L2_CNTL3__BANK_SELECT__SHIFT
	.comm	_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT,8,3 ## @VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT
	.comm	_mmVM_CONTEXT0_PAGE_TABLE_START_ADDR,4,2 ## @mmVM_CONTEXT0_PAGE_TABLE_START_ADDR
	.comm	_mmVM_CONTEXT0_PAGE_TABLE_END_ADDR,4,2 ## @mmVM_CONTEXT0_PAGE_TABLE_END_ADDR
	.comm	_mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR,4,2 ## @mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
	.comm	_mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,4,2 ## @mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
	.comm	_mmVM_CONTEXT0_CNTL2,4,2        ## @mmVM_CONTEXT0_CNTL2
	.comm	_mmVM_CONTEXT0_CNTL,4,2         ## @mmVM_CONTEXT0_CNTL
	.comm	_VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK,8,3 ## @VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK
	.comm	_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT,8,3 ## @VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT
	.comm	_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK,8,3 ## @VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
	.comm	_mmVM_CONTEXT1_PAGE_TABLE_START_ADDR,4,2 ## @mmVM_CONTEXT1_PAGE_TABLE_START_ADDR
	.comm	_mmVM_CONTEXT1_PAGE_TABLE_END_ADDR,4,2 ## @mmVM_CONTEXT1_PAGE_TABLE_END_ADDR
	.comm	_mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR,4,2 ## @mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
	.comm	_mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,4,2 ## @mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR
	.comm	_mmVM_CONTEXT1_CNTL2,4,2        ## @mmVM_CONTEXT1_CNTL2
	.comm	_mmVM_CONTEXT1_CNTL,4,2         ## @mmVM_CONTEXT1_CNTL
	.comm	_VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK,8,3 ## @VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK
	.comm	_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT,8,3 ## @VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT
	.comm	_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT,4,2 ## @VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
	.comm	_amdgpu_vm_fault_stop,8,3       ## @amdgpu_vm_fault_stop
	.comm	_AMDGPU_VM_FAULT_STOP_ALWAYS,8,3 ## @AMDGPU_VM_FAULT_STOP_ALWAYS
L_.str.1:                               ## @.str.1
	.asciz	"PCIE GART of %uM enabled (table at 0x%016llX).\n"

	.no_dead_strip	_gmc_v6_0_gart_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gmc_v6_0_gart_enable
_gmc_v6_0_gart_enable:                  ; @gmc_v6_0_gart_enable
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	x8, [x0, #16]
	cbz	x8, LBB0_3
; %bb.1:
	mov	x0, x19
	bl	_amdgpu_gart_table_vram_pin
	cbnz	w0, LBB0_4
; %bb.2:
	ldr	x0, [x19, #16]
	bl	_amdgpu_bo_gpu_offset
	mov	x20, x0
Lloh0:
	adrp	x8, _mmMC_VM_MX_L1_TLB_CNTL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _mmMC_VM_MX_L1_TLB_CNTL@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
Lloh3:
	adrp	x8, _MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
Lloh6:
	adrp	x9, _MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK@GOTPAGE
Lloh7:
	ldr	x9, [x9, _MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
Lloh9:
	adrp	x10, _MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK@GOTPAGE
Lloh10:
	ldr	x10, [x10, _MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w10, [x10]
Lloh12:
	adrp	x11, _MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK@GOTPAGE
Lloh13:
	ldr	x11, [x11, _MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w11, [x11]
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	sxtw	x8, w8
	mov	w9, #1280
	orr	x1, x8, x9
	bl	_WREG32
Lloh15:
	adrp	x8, _mmVM_L2_CNTL@GOTPAGE
Lloh16:
	ldr	x8, [x8, _mmVM_L2_CNTL@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
Lloh18:
	adrp	x8, _VM_L2_CNTL__ENABLE_L2_CACHE_MASK@GOTPAGE
Lloh19:
	ldr	x8, [x8, _VM_L2_CNTL__ENABLE_L2_CACHE_MASK@GOTPAGEOFF]
Lloh20:
	ldr	x8, [x8]
Lloh21:
	adrp	x9, _VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK@GOTPAGE
Lloh22:
	ldr	x9, [x9, _VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK@GOTPAGEOFF]
Lloh23:
	ldr	x9, [x9]
	orr	x8, x9, x8
Lloh24:
	adrp	x9, _VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK@GOTPAGE
Lloh25:
	ldr	x9, [x9, _VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK@GOTPAGEOFF]
Lloh26:
	ldr	x9, [x9]
	orr	x8, x8, x9
Lloh27:
	adrp	x9, _VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK@GOTPAGE
Lloh28:
	ldr	x9, [x9, _VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK@GOTPAGEOFF]
Lloh29:
	ldr	x9, [x9]
	orr	x8, x8, x9
Lloh30:
	adrp	x9, _VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT@GOTPAGE
Lloh31:
	ldr	x9, [x9, _VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT@GOTPAGEOFF]
Lloh32:
	ldr	x9, [x9]
	mov	w10, #7
	lsl	x9, x10, x9
	orr	x8, x8, x9
Lloh33:
	adrp	x9, _VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT@GOTPAGE
Lloh34:
	ldr	x9, [x9, _VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT@GOTPAGEOFF]
Lloh35:
	ldr	x9, [x9]
	mov	w22, #1
	lsl	x9, x22, x9
	orr	x1, x8, x9
	bl	_WREG32
Lloh36:
	adrp	x8, _mmVM_L2_CNTL2@GOTPAGE
Lloh37:
	ldr	x8, [x8, _mmVM_L2_CNTL2@GOTPAGEOFF]
Lloh38:
	adrp	x9, _VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK@GOTPAGE
Lloh39:
	ldr	x9, [x9, _VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK@GOTPAGEOFF]
Lloh40:
	ldr	w0, [x8]
Lloh41:
	ldr	x8, [x9]
Lloh42:
	adrp	x9, _VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK@GOTPAGE
Lloh43:
	ldr	x9, [x9, _VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK@GOTPAGEOFF]
Lloh44:
	ldr	x9, [x9]
	orr	x1, x9, x8
	bl	_WREG32
	ldr	x8, [x19, #40]
Lloh45:
	adrp	x9, _mmVM_L2_CNTL3@GOTPAGE
Lloh46:
	ldr	x9, [x9, _mmVM_L2_CNTL3@GOTPAGEOFF]
Lloh47:
	adrp	x10, _VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK@GOTPAGE
Lloh48:
	ldr	x10, [x10, _VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK@GOTPAGEOFF]
Lloh49:
	ldr	w0, [x9]
Lloh50:
	ldr	x9, [x10]
Lloh51:
	adrp	x10, _VM_L2_CNTL3__BANK_SELECT__SHIFT@GOTPAGE
Lloh52:
	ldr	x10, [x10, _VM_L2_CNTL3__BANK_SELECT__SHIFT@GOTPAGEOFF]
Lloh53:
	ldr	x10, [x10]
	lsl	x10, x8, x10
	orr	x9, x10, x9
Lloh54:
	adrp	x10, _VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT@GOTPAGE
Lloh55:
	ldr	x10, [x10, _VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT@GOTPAGEOFF]
Lloh56:
	ldr	x10, [x10]
	lsl	x8, x8, x10
	orr	x1, x9, x8
	bl	_WREG32
Lloh57:
	adrp	x8, _mmVM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPAGE
Lloh58:
	ldr	x8, [x8, _mmVM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPAGEOFF]
Lloh59:
	ldr	w0, [x8]
	ldr	w8, [x19, #24]
	sbfx	x1, x8, #12, #20
	bl	_WREG32
Lloh60:
	adrp	x8, _mmVM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPAGE
Lloh61:
	ldr	x8, [x8, _mmVM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPAGEOFF]
Lloh62:
	ldr	w0, [x8]
	ldr	w8, [x19, #28]
	sbfx	x1, x8, #12, #20
	bl	_WREG32
Lloh63:
	adrp	x23, _mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPAGE
Lloh64:
	ldr	x23, [x23, _mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPAGEOFF]
	ldr	w0, [x23]
	sbfx	x21, x20, #12, #20
	mov	x1, x21
	bl	_WREG32
Lloh65:
	adrp	x8, _mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR@GOTPAGE
Lloh66:
	ldr	x8, [x8, _mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR@GOTPAGEOFF]
Lloh67:
	ldr	w0, [x8]
	ldr	w8, [x19]
	sbfx	x1, x8, #12, #20
	bl	_WREG32
Lloh68:
	adrp	x8, _mmVM_CONTEXT0_CNTL2@GOTPAGE
Lloh69:
	ldr	x8, [x8, _mmVM_CONTEXT0_CNTL2@GOTPAGEOFF]
Lloh70:
	ldr	w0, [x8]
	mov	x1, #0
	bl	_WREG32
Lloh71:
	adrp	x8, _mmVM_CONTEXT0_CNTL@GOTPAGE
Lloh72:
	ldr	x8, [x8, _mmVM_CONTEXT0_CNTL@GOTPAGEOFF]
Lloh73:
	adrp	x9, _VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK@GOTPAGE
Lloh74:
	ldr	x9, [x9, _VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK@GOTPAGEOFF]
Lloh75:
	ldr	w0, [x8]
Lloh76:
	ldr	x8, [x9]
Lloh77:
	adrp	x9, _VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK@GOTPAGE
Lloh78:
	ldr	x9, [x9, _VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK@GOTPAGEOFF]
Lloh79:
	ldr	x9, [x9]
	orr	x1, x9, x8
	bl	_WREG32
	mov	w0, #1397
	mov	x1, #0
	bl	_WREG32
	mov	w0, #1398
	mov	x1, #0
	bl	_WREG32
	mov	w0, #1399
	mov	x1, #0
	bl	_WREG32
Lloh80:
	adrp	x8, _mmVM_CONTEXT1_PAGE_TABLE_START_ADDR@GOTPAGE
Lloh81:
	ldr	x8, [x8, _mmVM_CONTEXT1_PAGE_TABLE_START_ADDR@GOTPAGEOFF]
Lloh82:
	ldr	w0, [x8]
	mov	x1, #0
	bl	_WREG32
Lloh83:
	adrp	x8, _mmVM_CONTEXT1_PAGE_TABLE_END_ADDR@GOTPAGE
Lloh84:
	ldr	x8, [x8, _mmVM_CONTEXT1_PAGE_TABLE_END_ADDR@GOTPAGEOFF]
Lloh85:
	ldr	w0, [x8]
	ldrsw	x8, [x19, #48]
	sub	x1, x8, #1
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #1
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #2
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #3
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #4
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #5
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #6
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #7
	mov	x1, x21
	bl	_WREG32
Lloh86:
	adrp	x23, _mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR@GOTPAGE
Lloh87:
	ldr	x23, [x23, _mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR@GOTPAGEOFF]
	ldr	w0, [x23]
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #1
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #2
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #3
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #4
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #5
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #6
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #7
	mov	x1, x21
	bl	_WREG32
Lloh88:
	adrp	x8, _mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR@GOTPAGE
Lloh89:
	ldr	x8, [x8, _mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR@GOTPAGEOFF]
Lloh90:
	ldr	w0, [x8]
	ldr	w8, [x19]
	sbfx	x1, x8, #12, #20
	bl	_WREG32
Lloh91:
	adrp	x8, _mmVM_CONTEXT1_CNTL2@GOTPAGE
Lloh92:
	ldr	x8, [x8, _mmVM_CONTEXT1_CNTL2@GOTPAGEOFF]
Lloh93:
	ldr	w0, [x8]
	mov	w1, #4
	bl	_WREG32
Lloh94:
	adrp	x8, _mmVM_CONTEXT1_CNTL@GOTPAGE
Lloh95:
	ldr	x8, [x8, _mmVM_CONTEXT1_CNTL@GOTPAGEOFF]
Lloh96:
	ldr	w0, [x8]
Lloh97:
	adrp	x8, _VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK@GOTPAGE
Lloh98:
	ldr	x8, [x8, _VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK@GOTPAGEOFF]
Lloh99:
	adrp	x9, _VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT@GOTPAGE
Lloh100:
	ldr	x9, [x9, _VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT@GOTPAGEOFF]
Lloh101:
	ldr	x8, [x8]
Lloh102:
	ldr	x9, [x9]
	lsl	x9, x22, x9
	orr	x8, x9, x8
	ldr	w9, [x19, #52]
	sub	w9, w9, #9
Lloh103:
	adrp	x10, _VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT@GOTPAGE
Lloh104:
	ldr	x10, [x10, _VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT@GOTPAGEOFF]
Lloh105:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	sxtw	x9, w9
	orr	x1, x8, x9
	bl	_WREG32
Lloh106:
	adrp	x8, _amdgpu_vm_fault_stop@GOTPAGE
Lloh107:
	ldr	x8, [x8, _amdgpu_vm_fault_stop@GOTPAGEOFF]
Lloh108:
	ldr	x8, [x8]
Lloh109:
	adrp	x9, _AMDGPU_VM_FAULT_STOP_ALWAYS@GOTPAGE
Lloh110:
	ldr	x9, [x9, _AMDGPU_VM_FAULT_STOP_ALWAYS@GOTPAGEOFF]
Lloh111:
	ldr	x9, [x9]
	cmp	x8, x9
	cset	w1, ne
	mov	x0, x19
	bl	_gmc_v6_0_set_fault_enable_default
	mov	x0, x19
	mov	w1, #0
	mov	w2, #0
	mov	w3, #0
	bl	_gmc_v6_0_flush_gpu_tlb
	ldp	w8, w0, [x19, #32]
	asr	w2, w8, #20
	sxtw	x3, w20
Lloh112:
	adrp	x1, l_.str.1@PAGE
Lloh113:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_info
	mov	w0, #0
	str	w22, [x19, #8]
	b	LBB0_4
LBB0_3:
	ldr	w0, [x19, #36]
Lloh114:
	adrp	x1, l_.str@PAGE
Lloh115:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
Lloh116:
	adrp	x8, _EINVAL@GOTPAGE
Lloh117:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh118:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_4:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh101
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGot	Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh75
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGot	Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh49
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh40
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpAdd	Lloh114, Lloh115
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"No VRAM object for PCIE GART.\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_mmMC_VM_MX_L1_TLB_CNTL,4,2     ; @mmMC_VM_MX_L1_TLB_CNTL
	.comm	_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK,4,2 ; @MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK
	.comm	_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK,4,2 ; @MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK
	.comm	_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK,4,2 ; @MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK
	.comm	_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK,4,2 ; @MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK
	.comm	_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT,8,3 ; @MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT
	.comm	_mmVM_L2_CNTL,4,2               ; @mmVM_L2_CNTL
	.comm	_VM_L2_CNTL__ENABLE_L2_CACHE_MASK,8,3 ; @VM_L2_CNTL__ENABLE_L2_CACHE_MASK
	.comm	_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK,8,3 ; @VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK
	.comm	_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK,8,3 ; @VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK
	.comm	_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK,8,3 ; @VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK
	.comm	_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT,8,3 ; @VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT
	.comm	_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT,8,3 ; @VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT
	.comm	_mmVM_L2_CNTL2,4,2              ; @mmVM_L2_CNTL2
	.comm	_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK,8,3 ; @VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK
	.comm	_VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK,8,3 ; @VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK
	.comm	_mmVM_L2_CNTL3,4,2              ; @mmVM_L2_CNTL3
	.comm	_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK,8,3 ; @VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK
	.comm	_VM_L2_CNTL3__BANK_SELECT__SHIFT,8,3 ; @VM_L2_CNTL3__BANK_SELECT__SHIFT
	.comm	_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT,8,3 ; @VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT
	.comm	_mmVM_CONTEXT0_PAGE_TABLE_START_ADDR,4,2 ; @mmVM_CONTEXT0_PAGE_TABLE_START_ADDR
	.comm	_mmVM_CONTEXT0_PAGE_TABLE_END_ADDR,4,2 ; @mmVM_CONTEXT0_PAGE_TABLE_END_ADDR
	.comm	_mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR,4,2 ; @mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
	.comm	_mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,4,2 ; @mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
	.comm	_mmVM_CONTEXT0_CNTL2,4,2        ; @mmVM_CONTEXT0_CNTL2
	.comm	_mmVM_CONTEXT0_CNTL,4,2         ; @mmVM_CONTEXT0_CNTL
	.comm	_VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK,8,3 ; @VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK
	.comm	_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT,8,3 ; @VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT
	.comm	_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK,8,3 ; @VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
	.comm	_mmVM_CONTEXT1_PAGE_TABLE_START_ADDR,4,2 ; @mmVM_CONTEXT1_PAGE_TABLE_START_ADDR
	.comm	_mmVM_CONTEXT1_PAGE_TABLE_END_ADDR,4,2 ; @mmVM_CONTEXT1_PAGE_TABLE_END_ADDR
	.comm	_mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR,4,2 ; @mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
	.comm	_mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,4,2 ; @mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR
	.comm	_mmVM_CONTEXT1_CNTL2,4,2        ; @mmVM_CONTEXT1_CNTL2
	.comm	_mmVM_CONTEXT1_CNTL,4,2         ; @mmVM_CONTEXT1_CNTL
	.comm	_VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK,8,3 ; @VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK
	.comm	_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT,8,3 ; @VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT
	.comm	_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT,4,2 ; @VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
	.comm	_amdgpu_vm_fault_stop,8,3       ; @amdgpu_vm_fault_stop
	.comm	_AMDGPU_VM_FAULT_STOP_ALWAYS,8,3 ; @AMDGPU_VM_FAULT_STOP_ALWAYS
l_.str.1:                               ; @.str.1
	.asciz	"PCIE GART of %uM enabled (table at 0x%016llX).\n"

	.no_dead_strip	_gmc_v6_0_gart_enable
.subsections_via_symbols
