	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function i9xx_compute_dpll
_i9xx_compute_dpll:                     ## @i9xx_compute_dpll
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r15
	movq	%rsi, %r12
	movq	%rdi, %rbx
	movl	(%rdi), %edi
	callq	_to_i915
	movq	%rax, %r14
	movq	%rbx, %rdi
	movq	%r12, %rsi
	movq	%r15, %rdx
	callq	_i9xx_update_pll_dividers
	movq	_DPLL_VGA_MODE_DIS@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_INTEL_OUTPUT_LVDS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_intel_crtc_has_type
	testq	%rax, %rax
	jne	LBB0_1
## %bb.2:
	movq	_DPLLB_MODE_DAC_SERIAL@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_1:
	movq	_DPLLB_MODE_LVDS@GOTPCREL(%rip), %rax
LBB0_3:
	orl	(%rax), %ebx
	movq	%r14, %rdi
	callq	_IS_I945G
	testq	%rax, %rax
	jne	LBB0_7
## %bb.4:
	movq	%r14, %rdi
	callq	_IS_I945GM
	testq	%rax, %rax
	jne	LBB0_7
## %bb.5:
	movq	%r14, %rdi
	callq	_IS_G33
	testq	%rax, %rax
	jne	LBB0_7
## %bb.6:
	movq	%r14, %rdi
	callq	_IS_PINEVIEW
	testq	%rax, %rax
	je	LBB0_8
LBB0_7:
	movl	(%r12), %eax
	decl	%eax
	movq	_SDVO_MULTIPLIER_SHIFT_HIRES@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	orl	%eax, %ebx
LBB0_8:
	movq	_INTEL_OUTPUT_SDVO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_intel_crtc_has_type
	testq	%rax, %rax
	movq	%r15, -48(%rbp)                 ## 8-byte Spill
	jne	LBB0_10
## %bb.9:
	movq	_INTEL_OUTPUT_HDMI@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_intel_crtc_has_type
	testq	%rax, %rax
	je	LBB0_11
LBB0_10:
	movq	_DPLL_SDVO_HIGH_SPEED@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
LBB0_11:
	movq	%r12, %rdi
	callq	_intel_crtc_has_dp_encoder
	xorl	%r15d, %r15d
	testq	%rax, %rax
	je	LBB0_13
## %bb.12:
	movq	_DPLL_SDVO_HIGH_SPEED@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
LBB0_13:
	orl	%ebx, %r15d
	movq	%r14, %rdi
	callq	_IS_PINEVIEW
	movb	24(%r12), %cl
	decb	%cl
	movl	$1, %r13d
	shll	%cl, %r13d
	testq	%rax, %rax
	je	LBB0_15
## %bb.14:
	movq	_DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r13d
	orl	%r15d, %r13d
	jmp	LBB0_18
LBB0_15:
	movq	_DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r13d
	orl	%r15d, %r13d
	movq	%r14, %rdi
	callq	_IS_G4X
	movq	-48(%rbp), %rcx                 ## 8-byte Reload
	testq	%rcx, %rcx
	je	LBB0_18
## %bb.16:
	testq	%rax, %rax
	je	LBB0_18
## %bb.17:
	movb	(%rcx), %cl
	decb	%cl
	movl	$1, %eax
	shll	%cl, %eax
	movq	_DPLL_FPA1_P1_POST_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	orl	%eax, %r13d
LBB0_18:
	movl	28(%r12), %eax
	addl	$-5, %eax
	cmpl	$9, %eax
	ja	LBB0_25
## %bb.19:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_20:
	movq	_DPLL_DAC_SERIAL_P2_CLOCK_DIV_5@GOTPCREL(%rip), %rax
	jmp	LBB0_24
LBB0_21:
	movq	_DPLLB_LVDS_P2_CLOCK_DIV_7@GOTPCREL(%rip), %rax
	jmp	LBB0_24
LBB0_22:
	movq	_DPLL_DAC_SERIAL_P2_CLOCK_DIV_10@GOTPCREL(%rip), %rax
	jmp	LBB0_24
LBB0_23:
	movq	_DPLLB_LVDS_P2_CLOCK_DIV_14@GOTPCREL(%rip), %rax
LBB0_24:
	orl	(%rax), %r13d
LBB0_25:
	movq	%r14, %rdi
	callq	_INTEL_GEN
	movq	_PLL_LOAD_PULSE_PHASE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$6, %edx
	shll	%cl, %edx
	xorl	%ebx, %ebx
	cmpl	$4, %eax
	cmovgel	%edx, %ebx
	orl	%r13d, %ebx
	cmpq	$0, 16(%r12)
	je	LBB0_27
## %bb.26:
	movq	_PLL_REF_INPUT_TVCLKINBC@GOTPCREL(%rip), %rax
	jmp	LBB0_31
LBB0_27:
	movq	_INTEL_OUTPUT_LVDS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_intel_crtc_has_type
	testq	%rax, %rax
	je	LBB0_30
## %bb.28:
	movq	%r14, %rdi
	callq	_intel_panel_use_ssc
	testq	%rax, %rax
	je	LBB0_30
## %bb.29:
	movq	_PLLB_REF_INPUT_SPREADSPECTRUMIN@GOTPCREL(%rip), %rax
	jmp	LBB0_31
LBB0_30:
	movq	_PLL_REF_INPUT_DREFCLK@GOTPCREL(%rip), %rax
LBB0_31:
	orl	(%rax), %ebx
	movq	_DPLL_VCO_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	%ebx, 4(%r12)
	movq	%r14, %rdi
	callq	_INTEL_GEN
	cmpl	$4, %eax
	jl	LBB0_33
## %bb.32:
	movl	(%r12), %eax
	decl	%eax
	movq	_DPLL_MD_UDI_MULTIPLIER_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	movl	%eax, 8(%r12)
LBB0_33:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_20, LBB0_20-LJTI0_0
.set L0_0_set_25, LBB0_25-LJTI0_0
.set L0_0_set_21, LBB0_21-LJTI0_0
.set L0_0_set_22, LBB0_22-LJTI0_0
.set L0_0_set_23, LBB0_23-LJTI0_0
LJTI0_0:
	.long	L0_0_set_20
	.long	L0_0_set_25
	.long	L0_0_set_21
	.long	L0_0_set_25
	.long	L0_0_set_25
	.long	L0_0_set_22
	.long	L0_0_set_25
	.long	L0_0_set_25
	.long	L0_0_set_25
	.long	L0_0_set_23
	.end_data_region
                                        ## -- End function
	.comm	_DPLL_VGA_MODE_DIS,4,2          ## @DPLL_VGA_MODE_DIS
	.comm	_INTEL_OUTPUT_LVDS,4,2          ## @INTEL_OUTPUT_LVDS
	.comm	_DPLLB_MODE_LVDS,4,2            ## @DPLLB_MODE_LVDS
	.comm	_DPLLB_MODE_DAC_SERIAL,4,2      ## @DPLLB_MODE_DAC_SERIAL
	.comm	_SDVO_MULTIPLIER_SHIFT_HIRES,4,2 ## @SDVO_MULTIPLIER_SHIFT_HIRES
	.comm	_INTEL_OUTPUT_SDVO,4,2          ## @INTEL_OUTPUT_SDVO
	.comm	_INTEL_OUTPUT_HDMI,4,2          ## @INTEL_OUTPUT_HDMI
	.comm	_DPLL_SDVO_HIGH_SPEED,4,2       ## @DPLL_SDVO_HIGH_SPEED
	.comm	_DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW,4,2 ## @DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
	.comm	_DPLL_FPA01_P1_POST_DIV_SHIFT,4,2 ## @DPLL_FPA01_P1_POST_DIV_SHIFT
	.comm	_DPLL_FPA1_P1_POST_DIV_SHIFT,4,2 ## @DPLL_FPA1_P1_POST_DIV_SHIFT
	.comm	_DPLL_DAC_SERIAL_P2_CLOCK_DIV_5,4,2 ## @DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
	.comm	_DPLLB_LVDS_P2_CLOCK_DIV_7,4,2  ## @DPLLB_LVDS_P2_CLOCK_DIV_7
	.comm	_DPLL_DAC_SERIAL_P2_CLOCK_DIV_10,4,2 ## @DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
	.comm	_DPLLB_LVDS_P2_CLOCK_DIV_14,4,2 ## @DPLLB_LVDS_P2_CLOCK_DIV_14
	.comm	_PLL_LOAD_PULSE_PHASE_SHIFT,4,2 ## @PLL_LOAD_PULSE_PHASE_SHIFT
	.comm	_PLL_REF_INPUT_TVCLKINBC,4,2    ## @PLL_REF_INPUT_TVCLKINBC
	.comm	_PLLB_REF_INPUT_SPREADSPECTRUMIN,4,2 ## @PLLB_REF_INPUT_SPREADSPECTRUMIN
	.comm	_PLL_REF_INPUT_DREFCLK,4,2      ## @PLL_REF_INPUT_DREFCLK
	.comm	_DPLL_VCO_ENABLE,4,2            ## @DPLL_VCO_ENABLE
	.comm	_DPLL_MD_UDI_MULTIPLIER_SHIFT,4,2 ## @DPLL_MD_UDI_MULTIPLIER_SHIFT
	.no_dead_strip	_i9xx_compute_dpll
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function i9xx_compute_dpll
_i9xx_compute_dpll:                     ; @i9xx_compute_dpll
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x21, x2
	mov	x19, x1
	mov	x22, x0
	ldr	w0, [x0]
	bl	_to_i915
	mov	x20, x0
	mov	x0, x22
	mov	x1, x19
	mov	x2, x21
	bl	_i9xx_update_pll_dividers
Lloh0:
	adrp	x8, _DPLL_VGA_MODE_DIS@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DPLL_VGA_MODE_DIS@GOTPAGEOFF]
Lloh2:
	ldr	w23, [x8]
Lloh3:
	adrp	x22, _INTEL_OUTPUT_LVDS@GOTPAGE
Lloh4:
	ldr	x22, [x22, _INTEL_OUTPUT_LVDS@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x19
	bl	_intel_crtc_has_type
Lloh5:
	adrp	x8, _DPLLB_MODE_DAC_SERIAL@GOTPAGE
Lloh6:
	ldr	x8, [x8, _DPLLB_MODE_DAC_SERIAL@GOTPAGEOFF]
Lloh7:
	adrp	x9, _DPLLB_MODE_LVDS@GOTPAGE
Lloh8:
	ldr	x9, [x9, _DPLLB_MODE_LVDS@GOTPAGEOFF]
	cmp	x0, #0
	csel	x8, x8, x9, eq
	ldr	w8, [x8]
	orr	w23, w8, w23
	mov	x0, x20
	bl	_IS_I945G
	cbnz	x0, LBB0_4
; %bb.1:
	mov	x0, x20
	bl	_IS_I945GM
	cbnz	x0, LBB0_4
; %bb.2:
	mov	x0, x20
	bl	_IS_G33
	cbnz	x0, LBB0_4
; %bb.3:
	mov	x0, x20
	bl	_IS_PINEVIEW
	cbz	x0, LBB0_5
LBB0_4:
	ldr	w8, [x19]
	sub	w8, w8, #1
Lloh9:
	adrp	x9, _SDVO_MULTIPLIER_SHIFT_HIRES@GOTPAGE
Lloh10:
	ldr	x9, [x9, _SDVO_MULTIPLIER_SHIFT_HIRES@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	orr	w23, w8, w23
LBB0_5:
Lloh12:
	adrp	x8, _INTEL_OUTPUT_SDVO@GOTPAGE
Lloh13:
	ldr	x8, [x8, _INTEL_OUTPUT_SDVO@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_intel_crtc_has_type
Lloh15:
	adrp	x24, _DPLL_SDVO_HIGH_SPEED@GOTPAGE
Lloh16:
	ldr	x24, [x24, _DPLL_SDVO_HIGH_SPEED@GOTPAGEOFF]
	cbnz	x0, LBB0_7
; %bb.6:
Lloh17:
	adrp	x8, _INTEL_OUTPUT_HDMI@GOTPAGE
Lloh18:
	ldr	x8, [x8, _INTEL_OUTPUT_HDMI@GOTPAGEOFF]
Lloh19:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_intel_crtc_has_type
	cbz	x0, LBB0_8
LBB0_7:
	ldr	w8, [x24]
	orr	w23, w8, w23
LBB0_8:
	mov	x0, x19
	bl	_intel_crtc_has_dp_encoder
	ldr	w8, [x24]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w23, w8, w23
	mov	x0, x20
	bl	_IS_PINEVIEW
	ldr	w8, [x19, #24]
	sub	w8, w8, #1
	mov	w9, #1
	lsl	w8, w9, w8
	cbz	x0, LBB0_10
; %bb.9:
Lloh20:
	adrp	x9, _DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW@GOTPAGE
Lloh21:
	ldr	x9, [x9, _DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW@GOTPAGEOFF]
	b	LBB0_13
LBB0_10:
Lloh22:
	adrp	x9, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGE
Lloh23:
	ldr	x9, [x9, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	orr	w23, w8, w23
	mov	x0, x20
	bl	_IS_G4X
	cbz	x21, LBB0_14
; %bb.11:
	cbz	x0, LBB0_14
; %bb.12:
	ldr	w8, [x21]
	sub	w8, w8, #1
	mov	w9, #1
	lsl	w8, w9, w8
Lloh25:
	adrp	x9, _DPLL_FPA1_P1_POST_DIV_SHIFT@GOTPAGE
Lloh26:
	ldr	x9, [x9, _DPLL_FPA1_P1_POST_DIV_SHIFT@GOTPAGEOFF]
LBB0_13:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	orr	w23, w8, w23
LBB0_14:
	ldr	w8, [x19, #28]
	sub	w8, w8, #5
	cmp	w8, #9
	b.hi	LBB0_21
; %bb.15:
Lloh27:
	adrp	x9, lJTI0_0@PAGE
Lloh28:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_16
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_16:
Lloh29:
	adrp	x8, _DPLL_DAC_SERIAL_P2_CLOCK_DIV_5@GOTPAGE
Lloh30:
	ldr	x8, [x8, _DPLL_DAC_SERIAL_P2_CLOCK_DIV_5@GOTPAGEOFF]
	b	LBB0_20
LBB0_17:
Lloh31:
	adrp	x8, _DPLLB_LVDS_P2_CLOCK_DIV_7@GOTPAGE
Lloh32:
	ldr	x8, [x8, _DPLLB_LVDS_P2_CLOCK_DIV_7@GOTPAGEOFF]
	b	LBB0_20
LBB0_18:
Lloh33:
	adrp	x8, _DPLL_DAC_SERIAL_P2_CLOCK_DIV_10@GOTPAGE
Lloh34:
	ldr	x8, [x8, _DPLL_DAC_SERIAL_P2_CLOCK_DIV_10@GOTPAGEOFF]
	b	LBB0_20
LBB0_19:
Lloh35:
	adrp	x8, _DPLLB_LVDS_P2_CLOCK_DIV_14@GOTPAGE
Lloh36:
	ldr	x8, [x8, _DPLLB_LVDS_P2_CLOCK_DIV_14@GOTPAGEOFF]
LBB0_20:
	ldr	w8, [x8]
	orr	w23, w8, w23
LBB0_21:
	mov	x0, x20
	bl	_INTEL_GEN
Lloh37:
	adrp	x8, _PLL_LOAD_PULSE_PHASE_SHIFT@GOTPAGE
Lloh38:
	ldr	x8, [x8, _PLL_LOAD_PULSE_PHASE_SHIFT@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
	mov	w9, #6
	lsl	w8, w9, w8
	cmp	w0, #3
	csel	w8, w8, wzr, gt
	orr	w21, w8, w23
	ldr	x8, [x19, #16]
	cbz	x8, LBB0_23
; %bb.22:
Lloh40:
	adrp	x8, _PLL_REF_INPUT_TVCLKINBC@GOTPAGE
Lloh41:
	ldr	x8, [x8, _PLL_REF_INPUT_TVCLKINBC@GOTPAGEOFF]
	b	LBB0_27
LBB0_23:
	ldr	w1, [x22]
	mov	x0, x19
	bl	_intel_crtc_has_type
	cbz	x0, LBB0_26
; %bb.24:
	mov	x0, x20
	bl	_intel_panel_use_ssc
	cbz	x0, LBB0_26
; %bb.25:
Lloh42:
	adrp	x8, _PLLB_REF_INPUT_SPREADSPECTRUMIN@GOTPAGE
Lloh43:
	ldr	x8, [x8, _PLLB_REF_INPUT_SPREADSPECTRUMIN@GOTPAGEOFF]
	b	LBB0_27
LBB0_26:
Lloh44:
	adrp	x8, _PLL_REF_INPUT_DREFCLK@GOTPAGE
Lloh45:
	ldr	x8, [x8, _PLL_REF_INPUT_DREFCLK@GOTPAGEOFF]
LBB0_27:
	ldr	w8, [x8]
	orr	w8, w21, w8
Lloh46:
	adrp	x9, _DPLL_VCO_ENABLE@GOTPAGE
Lloh47:
	ldr	x9, [x9, _DPLL_VCO_ENABLE@GOTPAGEOFF]
Lloh48:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x19, #4]
	mov	x0, x20
	bl	_INTEL_GEN
	cmp	w0, #4
	b.lt	LBB0_29
; %bb.28:
	ldr	w8, [x19]
	sub	w8, w8, #1
Lloh49:
	adrp	x9, _DPLL_MD_UDI_MULTIPLIER_SHIFT@GOTPAGE
Lloh50:
	ldr	x9, [x9, _DPLL_MD_UDI_MULTIPLIER_SHIFT@GOTPAGEOFF]
Lloh51:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	str	w8, [x19, #8]
LBB0_29:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpAdd	Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_16-LBB0_16)>>2
	.byte	(LBB0_21-LBB0_16)>>2
	.byte	(LBB0_17-LBB0_16)>>2
	.byte	(LBB0_21-LBB0_16)>>2
	.byte	(LBB0_21-LBB0_16)>>2
	.byte	(LBB0_18-LBB0_16)>>2
	.byte	(LBB0_21-LBB0_16)>>2
	.byte	(LBB0_21-LBB0_16)>>2
	.byte	(LBB0_21-LBB0_16)>>2
	.byte	(LBB0_19-LBB0_16)>>2
                                        ; -- End function
	.comm	_DPLL_VGA_MODE_DIS,4,2          ; @DPLL_VGA_MODE_DIS
	.comm	_INTEL_OUTPUT_LVDS,4,2          ; @INTEL_OUTPUT_LVDS
	.comm	_DPLLB_MODE_LVDS,4,2            ; @DPLLB_MODE_LVDS
	.comm	_DPLLB_MODE_DAC_SERIAL,4,2      ; @DPLLB_MODE_DAC_SERIAL
	.comm	_SDVO_MULTIPLIER_SHIFT_HIRES,4,2 ; @SDVO_MULTIPLIER_SHIFT_HIRES
	.comm	_INTEL_OUTPUT_SDVO,4,2          ; @INTEL_OUTPUT_SDVO
	.comm	_INTEL_OUTPUT_HDMI,4,2          ; @INTEL_OUTPUT_HDMI
	.comm	_DPLL_SDVO_HIGH_SPEED,4,2       ; @DPLL_SDVO_HIGH_SPEED
	.comm	_DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW,4,2 ; @DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
	.comm	_DPLL_FPA01_P1_POST_DIV_SHIFT,4,2 ; @DPLL_FPA01_P1_POST_DIV_SHIFT
	.comm	_DPLL_FPA1_P1_POST_DIV_SHIFT,4,2 ; @DPLL_FPA1_P1_POST_DIV_SHIFT
	.comm	_DPLL_DAC_SERIAL_P2_CLOCK_DIV_5,4,2 ; @DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
	.comm	_DPLLB_LVDS_P2_CLOCK_DIV_7,4,2  ; @DPLLB_LVDS_P2_CLOCK_DIV_7
	.comm	_DPLL_DAC_SERIAL_P2_CLOCK_DIV_10,4,2 ; @DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
	.comm	_DPLLB_LVDS_P2_CLOCK_DIV_14,4,2 ; @DPLLB_LVDS_P2_CLOCK_DIV_14
	.comm	_PLL_LOAD_PULSE_PHASE_SHIFT,4,2 ; @PLL_LOAD_PULSE_PHASE_SHIFT
	.comm	_PLL_REF_INPUT_TVCLKINBC,4,2    ; @PLL_REF_INPUT_TVCLKINBC
	.comm	_PLLB_REF_INPUT_SPREADSPECTRUMIN,4,2 ; @PLLB_REF_INPUT_SPREADSPECTRUMIN
	.comm	_PLL_REF_INPUT_DREFCLK,4,2      ; @PLL_REF_INPUT_DREFCLK
	.comm	_DPLL_VCO_ENABLE,4,2            ; @DPLL_VCO_ENABLE
	.comm	_DPLL_MD_UDI_MULTIPLIER_SHIFT,4,2 ; @DPLL_MD_UDI_MULTIPLIER_SHIFT
	.no_dead_strip	_i9xx_compute_dpll
.subsections_via_symbols
