	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gmc_v8_0_gart_enable
_gmc_v8_0_gart_enable:                  ## @gmc_v8_0_gart_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	cmpq	$0, 16(%rdi)
	je	LBB0_1
## %bb.2:
	movq	%r12, %rdi
	callq	_amdgpu_gart_table_vram_pin
	testl	%eax, %eax
	jne	LBB0_4
## %bb.3:
	movq	16(%r12), %rdi
	callq	_amdgpu_bo_gpu_offset
	movl	%eax, %r15d
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	_mmMC_VM_MX_L1_TLB_CNTL@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	callq	_RREG32
	movq	_MC_VM_MX_L1_TLB_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_ENABLE_L1_TLB@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_ENABLE_L1_FRAGMENT_PROCESSING@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_SYSTEM_ACCESS_MODE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$3, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_ENABLE_ADVANCED_DRIVER_MODEL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_SYSTEM_APERTURE_UNMAPPED_ACCESS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movq	(%r14), %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmVM_L2_CNTL@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	callq	_RREG32
	movq	_VM_L2_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_ENABLE_L2_CACHE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_ENABLE_L2_FRAGMENT_PROCESSING@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_EFFECTIVE_L2_QUEUE_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$7, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_CONTEXT1_IDENTITY_ACCESS_MODE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movq	(%r14), %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmVM_L2_CNTL2@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	callq	_RREG32
	movq	_VM_L2_CNTL2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_INVALIDATE_ALL_L1_TLBS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_INVALIDATE_L2_CACHE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movq	(%r14), %rdi
	movl	%eax, %esi
	callq	_WREG32
	movl	36(%r12), %ebx
	movq	_mmVM_L2_CNTL3@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	callq	_RREG32
	movq	_VM_L2_CNTL3@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	_L2_CACHE_BIGK_ASSOCIATIVITY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r13), %esi
	movq	_BANK_SELECT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	%ebx, %ecx
	callq	_REG_SET_FIELD
	movl	(%r13), %esi
	movq	_L2_CACHE_BIGK_FRAGMENT_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	%ebx, %ecx
	callq	_REG_SET_FIELD
	movq	(%r14), %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmVM_L2_CNTL4@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	callq	_RREG32
	movq	_VM_L2_CNTL4@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movq	(%r14), %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	24(%r12), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	28(%r12), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	movl	%r15d, %ebx
	sarl	$12, %ebx
	movl	%ebx, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	(%r12), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT0_CNTL2@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT0_CNTL@GOTPCREL(%rip), %r13
	movq	(%r13), %rdi
	callq	_RREG32
	movq	_VM_CONTEXT0_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_ENABLE_CONTEXT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r15), %esi
	movq	_PAGE_TABLE_DEPTH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%r15), %esi
	movq	_RANGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movq	(%r13), %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT1_PAGE_TABLE_START_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT1_PAGE_TABLE_END_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	40(%r12), %esi
	decl	%esi
	callq	_WREG32
	movq	(%r14), %rdi
	incq	%rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	(%r14), %rdi
	addq	$2, %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	(%r14), %rdi
	addq	$3, %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	(%r14), %rdi
	addq	$4, %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	(%r14), %rdi
	addq	$5, %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	(%r14), %rdi
	addq	$6, %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	(%r14), %rdi
	addq	$7, %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	(%r14), %rdi
	incq	%rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	(%r14), %rdi
	addq	$2, %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	(%r14), %rdi
	addq	$3, %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	(%r14), %rdi
	addq	$4, %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	(%r14), %rdi
	addq	$5, %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	(%r14), %rdi
	addq	$6, %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	(%r14), %rdi
	addq	$7, %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	(%r12), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT1_CNTL2@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	$4, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT1_CNTL@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	callq	_RREG32
	movq	_VM_CONTEXT1_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_ENABLE_CONTEXT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_PAGE_TABLE_DEPTH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movl	(%r15), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_PDE0_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_VALID_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_READ_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_WRITE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_PAGE_TABLE_BLOCK_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	44(%r12), %ecx
	addl	$-9, %ecx
	movl	%eax, %edi
	callq	_REG_SET_FIELD
	movq	(%r14), %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	_amdgpu_vm_fault_stop@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_AMDGPU_VM_FAULT_STOP_ALWAYS@GOTPCREL(%rip), %rcx
	xorl	%esi, %esi
	cmpq	(%rcx), %rax
	setne	%sil
	movq	%r12, %rdi
	callq	_gmc_v8_0_set_fault_enable_default
	movq	%r12, %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	callq	_gmc_v8_0_flush_gpu_tlb
	movl	32(%r12), %esi
	sarl	$20, %esi
	movslq	-44(%rbp), %rdx                 ## 4-byte Folded Reload
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_INFO
	xorl	%eax, %eax
	movl	$1, 8(%r12)
	jmp	LBB0_4
LBB0_1:
	movl	48(%r12), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_4:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"No VRAM object for PCIE GART.\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_mmMC_VM_MX_L1_TLB_CNTL,8,3     ## @mmMC_VM_MX_L1_TLB_CNTL
	.comm	_MC_VM_MX_L1_TLB_CNTL,4,2       ## @MC_VM_MX_L1_TLB_CNTL
	.comm	_ENABLE_L1_TLB,4,2              ## @ENABLE_L1_TLB
	.comm	_ENABLE_L1_FRAGMENT_PROCESSING,4,2 ## @ENABLE_L1_FRAGMENT_PROCESSING
	.comm	_SYSTEM_ACCESS_MODE,4,2         ## @SYSTEM_ACCESS_MODE
	.comm	_ENABLE_ADVANCED_DRIVER_MODEL,4,2 ## @ENABLE_ADVANCED_DRIVER_MODEL
	.comm	_SYSTEM_APERTURE_UNMAPPED_ACCESS,4,2 ## @SYSTEM_APERTURE_UNMAPPED_ACCESS
	.comm	_mmVM_L2_CNTL,8,3               ## @mmVM_L2_CNTL
	.comm	_VM_L2_CNTL,4,2                 ## @VM_L2_CNTL
	.comm	_ENABLE_L2_CACHE,4,2            ## @ENABLE_L2_CACHE
	.comm	_ENABLE_L2_FRAGMENT_PROCESSING,4,2 ## @ENABLE_L2_FRAGMENT_PROCESSING
	.comm	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE,4,2 ## @ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE,4,2 ## @ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_EFFECTIVE_L2_QUEUE_SIZE,4,2    ## @EFFECTIVE_L2_QUEUE_SIZE
	.comm	_CONTEXT1_IDENTITY_ACCESS_MODE,4,2 ## @CONTEXT1_IDENTITY_ACCESS_MODE
	.comm	_ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY,4,2 ## @ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY
	.comm	_mmVM_L2_CNTL2,8,3              ## @mmVM_L2_CNTL2
	.comm	_VM_L2_CNTL2,4,2                ## @VM_L2_CNTL2
	.comm	_INVALIDATE_ALL_L1_TLBS,4,2     ## @INVALIDATE_ALL_L1_TLBS
	.comm	_INVALIDATE_L2_CACHE,4,2        ## @INVALIDATE_L2_CACHE
	.comm	_mmVM_L2_CNTL3,8,3              ## @mmVM_L2_CNTL3
	.comm	_VM_L2_CNTL3,4,2                ## @VM_L2_CNTL3
	.comm	_L2_CACHE_BIGK_ASSOCIATIVITY,4,2 ## @L2_CACHE_BIGK_ASSOCIATIVITY
	.comm	_BANK_SELECT,4,2                ## @BANK_SELECT
	.comm	_L2_CACHE_BIGK_FRAGMENT_SIZE,4,2 ## @L2_CACHE_BIGK_FRAGMENT_SIZE
	.comm	_mmVM_L2_CNTL4,8,3              ## @mmVM_L2_CNTL4
	.comm	_VM_L2_CNTL4,4,2                ## @VM_L2_CNTL4
	.comm	_VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL,4,2 ## @VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL
	.comm	_VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED,4,2 ## @VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED
	.comm	_VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP,4,2 ## @VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP
	.comm	_VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL,4,2 ## @VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL
	.comm	_VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED,4,2 ## @VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED
	.comm	_VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP,4,2 ## @VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP
	.comm	_VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL,4,2 ## @VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL
	.comm	_VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED,4,2 ## @VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED
	.comm	_VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP,4,2 ## @VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP
	.comm	_VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL,4,2 ## @VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL
	.comm	_VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED,4,2 ## @VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED
	.comm	_VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP,4,2 ## @VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP
	.comm	_mmVM_CONTEXT0_PAGE_TABLE_START_ADDR,8,3 ## @mmVM_CONTEXT0_PAGE_TABLE_START_ADDR
	.comm	_mmVM_CONTEXT0_PAGE_TABLE_END_ADDR,8,3 ## @mmVM_CONTEXT0_PAGE_TABLE_END_ADDR
	.comm	_mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR,8,3 ## @mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
	.comm	_mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,8,3 ## @mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
	.comm	_mmVM_CONTEXT0_CNTL2,8,3        ## @mmVM_CONTEXT0_CNTL2
	.comm	_mmVM_CONTEXT0_CNTL,8,3         ## @mmVM_CONTEXT0_CNTL
	.comm	_VM_CONTEXT0_CNTL,4,2           ## @VM_CONTEXT0_CNTL
	.comm	_ENABLE_CONTEXT,4,2             ## @ENABLE_CONTEXT
	.comm	_PAGE_TABLE_DEPTH,4,2           ## @PAGE_TABLE_DEPTH
	.comm	_RANGE_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ## @RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR,8,3 ## @mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR
	.comm	_mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR,8,3 ## @mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR
	.comm	_mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET,8,3 ## @mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET
	.comm	_mmVM_CONTEXT1_PAGE_TABLE_START_ADDR,8,3 ## @mmVM_CONTEXT1_PAGE_TABLE_START_ADDR
	.comm	_mmVM_CONTEXT1_PAGE_TABLE_END_ADDR,8,3 ## @mmVM_CONTEXT1_PAGE_TABLE_END_ADDR
	.comm	_mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR,8,3 ## @mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
	.comm	_mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,8,3 ## @mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR
	.comm	_mmVM_CONTEXT1_CNTL2,8,3        ## @mmVM_CONTEXT1_CNTL2
	.comm	_mmVM_CONTEXT1_CNTL,8,3         ## @mmVM_CONTEXT1_CNTL
	.comm	_VM_CONTEXT1_CNTL,4,2           ## @VM_CONTEXT1_CNTL
	.comm	_DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ## @DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_PDE0_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ## @PDE0_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_VALID_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ## @VALID_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_READ_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ## @READ_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_WRITE_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ## @WRITE_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ## @EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_PAGE_TABLE_BLOCK_SIZE,4,2      ## @PAGE_TABLE_BLOCK_SIZE
	.comm	_amdgpu_vm_fault_stop,8,3       ## @amdgpu_vm_fault_stop
	.comm	_AMDGPU_VM_FAULT_STOP_ALWAYS,8,3 ## @AMDGPU_VM_FAULT_STOP_ALWAYS
L_.str.1:                               ## @.str.1
	.asciz	"PCIE GART of %uM enabled (table at 0x%016llX).\n"

	.no_dead_strip	_gmc_v8_0_gart_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gmc_v8_0_gart_enable
_gmc_v8_0_gart_enable:                  ; @gmc_v8_0_gart_enable
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	x8, [x0, #16]
	cbz	x8, LBB0_3
; %bb.1:
	mov	x0, x19
	bl	_amdgpu_gart_table_vram_pin
	cbnz	w0, LBB0_4
; %bb.2:
	ldr	x0, [x19, #16]
	bl	_amdgpu_bo_gpu_offset
	mov	x20, x0
Lloh0:
	adrp	x21, _mmMC_VM_MX_L1_TLB_CNTL@GOTPAGE
Lloh1:
	ldr	x21, [x21, _mmMC_VM_MX_L1_TLB_CNTL@GOTPAGEOFF]
	ldr	x0, [x21]
	bl	_RREG32
Lloh2:
	adrp	x23, _MC_VM_MX_L1_TLB_CNTL@GOTPAGE
Lloh3:
	ldr	x23, [x23, _MC_VM_MX_L1_TLB_CNTL@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh4:
	adrp	x8, _ENABLE_L1_TLB@GOTPAGE
Lloh5:
	ldr	x8, [x8, _ENABLE_L1_TLB@GOTPAGEOFF]
Lloh6:
	ldr	w2, [x8]
	mov	w22, #1
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh7:
	adrp	x8, _ENABLE_L1_FRAGMENT_PROCESSING@GOTPAGE
Lloh8:
	ldr	x8, [x8, _ENABLE_L1_FRAGMENT_PROCESSING@GOTPAGEOFF]
Lloh9:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh10:
	adrp	x8, _SYSTEM_ACCESS_MODE@GOTPAGE
Lloh11:
	ldr	x8, [x8, _SYSTEM_ACCESS_MODE@GOTPAGEOFF]
Lloh12:
	ldr	w2, [x8]
	mov	w3, #3
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh13:
	adrp	x8, _ENABLE_ADVANCED_DRIVER_MODEL@GOTPAGE
Lloh14:
	ldr	x8, [x8, _ENABLE_ADVANCED_DRIVER_MODEL@GOTPAGEOFF]
Lloh15:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh16:
	adrp	x8, _SYSTEM_APERTURE_UNMAPPED_ACCESS@GOTPAGE
Lloh17:
	ldr	x8, [x8, _SYSTEM_APERTURE_UNMAPPED_ACCESS@GOTPAGEOFF]
Lloh18:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	mov	x1, x0
	ldr	x0, [x21]
	bl	_WREG32
Lloh19:
	adrp	x21, _mmVM_L2_CNTL@GOTPAGE
Lloh20:
	ldr	x21, [x21, _mmVM_L2_CNTL@GOTPAGEOFF]
	ldr	x0, [x21]
	bl	_RREG32
Lloh21:
	adrp	x23, _VM_L2_CNTL@GOTPAGE
Lloh22:
	ldr	x23, [x23, _VM_L2_CNTL@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh23:
	adrp	x8, _ENABLE_L2_CACHE@GOTPAGE
Lloh24:
	ldr	x8, [x8, _ENABLE_L2_CACHE@GOTPAGEOFF]
Lloh25:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh26:
	adrp	x8, _ENABLE_L2_FRAGMENT_PROCESSING@GOTPAGE
Lloh27:
	ldr	x8, [x8, _ENABLE_L2_FRAGMENT_PROCESSING@GOTPAGEOFF]
Lloh28:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh29:
	adrp	x8, _ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGE
Lloh30:
	ldr	x8, [x8, _ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGEOFF]
Lloh31:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh32:
	adrp	x8, _ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGE
Lloh33:
	ldr	x8, [x8, _ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGEOFF]
Lloh34:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh35:
	adrp	x8, _EFFECTIVE_L2_QUEUE_SIZE@GOTPAGE
Lloh36:
	ldr	x8, [x8, _EFFECTIVE_L2_QUEUE_SIZE@GOTPAGEOFF]
Lloh37:
	ldr	w2, [x8]
	mov	w3, #7
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh38:
	adrp	x8, _CONTEXT1_IDENTITY_ACCESS_MODE@GOTPAGE
Lloh39:
	ldr	x8, [x8, _CONTEXT1_IDENTITY_ACCESS_MODE@GOTPAGEOFF]
Lloh40:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh41:
	adrp	x8, _ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY@GOTPAGE
Lloh42:
	ldr	x8, [x8, _ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY@GOTPAGEOFF]
Lloh43:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x1, x0
	ldr	x0, [x21]
	bl	_WREG32
Lloh44:
	adrp	x21, _mmVM_L2_CNTL2@GOTPAGE
Lloh45:
	ldr	x21, [x21, _mmVM_L2_CNTL2@GOTPAGEOFF]
	ldr	x0, [x21]
	bl	_RREG32
Lloh46:
	adrp	x23, _VM_L2_CNTL2@GOTPAGE
Lloh47:
	ldr	x23, [x23, _VM_L2_CNTL2@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh48:
	adrp	x8, _INVALIDATE_ALL_L1_TLBS@GOTPAGE
Lloh49:
	ldr	x8, [x8, _INVALIDATE_ALL_L1_TLBS@GOTPAGEOFF]
Lloh50:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh51:
	adrp	x8, _INVALIDATE_L2_CACHE@GOTPAGE
Lloh52:
	ldr	x8, [x8, _INVALIDATE_L2_CACHE@GOTPAGEOFF]
Lloh53:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x1, x0
	ldr	x0, [x21]
	bl	_WREG32
	ldr	w21, [x19, #36]
Lloh54:
	adrp	x23, _mmVM_L2_CNTL3@GOTPAGE
Lloh55:
	ldr	x23, [x23, _mmVM_L2_CNTL3@GOTPAGEOFF]
	ldr	x0, [x23]
	bl	_RREG32
Lloh56:
	adrp	x24, _VM_L2_CNTL3@GOTPAGE
Lloh57:
	ldr	x24, [x24, _VM_L2_CNTL3@GOTPAGEOFF]
	ldr	w1, [x24]
Lloh58:
	adrp	x8, _L2_CACHE_BIGK_ASSOCIATIVITY@GOTPAGE
Lloh59:
	ldr	x8, [x8, _L2_CACHE_BIGK_ASSOCIATIVITY@GOTPAGEOFF]
Lloh60:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x24]
Lloh61:
	adrp	x8, _BANK_SELECT@GOTPAGE
Lloh62:
	ldr	x8, [x8, _BANK_SELECT@GOTPAGEOFF]
Lloh63:
	ldr	w2, [x8]
	mov	x3, x21
	bl	_REG_SET_FIELD
	ldr	w1, [x24]
Lloh64:
	adrp	x8, _L2_CACHE_BIGK_FRAGMENT_SIZE@GOTPAGE
Lloh65:
	ldr	x8, [x8, _L2_CACHE_BIGK_FRAGMENT_SIZE@GOTPAGEOFF]
Lloh66:
	ldr	w2, [x8]
	mov	x3, x21
	bl	_REG_SET_FIELD
	mov	x1, x0
	ldr	x0, [x23]
	bl	_WREG32
Lloh67:
	adrp	x21, _mmVM_L2_CNTL4@GOTPAGE
Lloh68:
	ldr	x21, [x21, _mmVM_L2_CNTL4@GOTPAGEOFF]
	ldr	x0, [x21]
	bl	_RREG32
Lloh69:
	adrp	x23, _VM_L2_CNTL4@GOTPAGE
Lloh70:
	ldr	x23, [x23, _VM_L2_CNTL4@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh71:
	adrp	x8, _VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL@GOTPAGE
Lloh72:
	ldr	x8, [x8, _VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL@GOTPAGEOFF]
Lloh73:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh74:
	adrp	x8, _VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED@GOTPAGE
Lloh75:
	ldr	x8, [x8, _VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED@GOTPAGEOFF]
Lloh76:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh77:
	adrp	x8, _VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP@GOTPAGE
Lloh78:
	ldr	x8, [x8, _VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP@GOTPAGEOFF]
Lloh79:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh80:
	adrp	x8, _VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL@GOTPAGE
Lloh81:
	ldr	x8, [x8, _VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL@GOTPAGEOFF]
Lloh82:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh83:
	adrp	x8, _VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED@GOTPAGE
Lloh84:
	ldr	x8, [x8, _VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED@GOTPAGEOFF]
Lloh85:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh86:
	adrp	x8, _VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP@GOTPAGE
Lloh87:
	ldr	x8, [x8, _VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP@GOTPAGEOFF]
Lloh88:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh89:
	adrp	x8, _VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL@GOTPAGE
Lloh90:
	ldr	x8, [x8, _VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL@GOTPAGEOFF]
Lloh91:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh92:
	adrp	x8, _VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED@GOTPAGE
Lloh93:
	ldr	x8, [x8, _VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED@GOTPAGEOFF]
Lloh94:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh95:
	adrp	x8, _VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP@GOTPAGE
Lloh96:
	ldr	x8, [x8, _VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP@GOTPAGEOFF]
Lloh97:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh98:
	adrp	x8, _VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL@GOTPAGE
Lloh99:
	ldr	x8, [x8, _VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL@GOTPAGEOFF]
Lloh100:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh101:
	adrp	x8, _VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED@GOTPAGE
Lloh102:
	ldr	x8, [x8, _VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED@GOTPAGEOFF]
Lloh103:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh104:
	adrp	x8, _VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP@GOTPAGE
Lloh105:
	ldr	x8, [x8, _VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP@GOTPAGEOFF]
Lloh106:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	mov	x1, x0
	ldr	x0, [x21]
	bl	_WREG32
Lloh107:
	adrp	x8, _mmVM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPAGE
Lloh108:
	ldr	x8, [x8, _mmVM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPAGEOFF]
Lloh109:
	ldr	x0, [x8]
	ldr	w8, [x19, #24]
	asr	w1, w8, #12
	bl	_WREG32
Lloh110:
	adrp	x8, _mmVM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPAGE
Lloh111:
	ldr	x8, [x8, _mmVM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPAGEOFF]
Lloh112:
	ldr	x0, [x8]
	ldr	w8, [x19, #28]
	asr	w1, w8, #12
	bl	_WREG32
Lloh113:
	adrp	x26, _mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPAGE
Lloh114:
	ldr	x26, [x26, _mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPAGEOFF]
	ldr	x0, [x26]
	asr	w21, w20, #12
	mov	x1, x21
	bl	_WREG32
Lloh115:
	adrp	x8, _mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR@GOTPAGE
Lloh116:
	ldr	x8, [x8, _mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR@GOTPAGEOFF]
Lloh117:
	ldr	x0, [x8]
	ldr	w8, [x19]
	asr	w1, w8, #12
	bl	_WREG32
Lloh118:
	adrp	x8, _mmVM_CONTEXT0_CNTL2@GOTPAGE
Lloh119:
	ldr	x8, [x8, _mmVM_CONTEXT0_CNTL2@GOTPAGEOFF]
Lloh120:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh121:
	adrp	x27, _mmVM_CONTEXT0_CNTL@GOTPAGE
Lloh122:
	ldr	x27, [x27, _mmVM_CONTEXT0_CNTL@GOTPAGEOFF]
	ldr	x0, [x27]
	bl	_RREG32
Lloh123:
	adrp	x25, _VM_CONTEXT0_CNTL@GOTPAGE
Lloh124:
	ldr	x25, [x25, _VM_CONTEXT0_CNTL@GOTPAGEOFF]
	ldr	w1, [x25]
Lloh125:
	adrp	x23, _ENABLE_CONTEXT@GOTPAGE
Lloh126:
	ldr	x23, [x23, _ENABLE_CONTEXT@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x25]
Lloh127:
	adrp	x24, _PAGE_TABLE_DEPTH@GOTPAGE
Lloh128:
	ldr	x24, [x24, _PAGE_TABLE_DEPTH@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x25]
Lloh129:
	adrp	x25, _RANGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGE
Lloh130:
	ldr	x25, [x25, _RANGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGEOFF]
	ldr	w2, [x25]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x1, x0
	ldr	x0, [x27]
	bl	_WREG32
Lloh131:
	adrp	x8, _mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR@GOTPAGE
Lloh132:
	ldr	x8, [x8, _mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR@GOTPAGEOFF]
Lloh133:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh134:
	adrp	x8, _mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR@GOTPAGE
Lloh135:
	ldr	x8, [x8, _mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR@GOTPAGEOFF]
Lloh136:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh137:
	adrp	x8, _mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET@GOTPAGE
Lloh138:
	ldr	x8, [x8, _mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET@GOTPAGEOFF]
Lloh139:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh140:
	adrp	x8, _mmVM_CONTEXT1_PAGE_TABLE_START_ADDR@GOTPAGE
Lloh141:
	ldr	x8, [x8, _mmVM_CONTEXT1_PAGE_TABLE_START_ADDR@GOTPAGEOFF]
Lloh142:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh143:
	adrp	x8, _mmVM_CONTEXT1_PAGE_TABLE_END_ADDR@GOTPAGE
Lloh144:
	ldr	x8, [x8, _mmVM_CONTEXT1_PAGE_TABLE_END_ADDR@GOTPAGEOFF]
Lloh145:
	ldr	x0, [x8]
	ldr	w8, [x19, #40]
	sub	w1, w8, #1
	bl	_WREG32
	ldr	x8, [x26]
	add	x0, x8, #1
	mov	x1, x21
	bl	_WREG32
	ldr	x8, [x26]
	add	x0, x8, #2
	mov	x1, x21
	bl	_WREG32
	ldr	x8, [x26]
	add	x0, x8, #3
	mov	x1, x21
	bl	_WREG32
	ldr	x8, [x26]
	add	x0, x8, #4
	mov	x1, x21
	bl	_WREG32
	ldr	x8, [x26]
	add	x0, x8, #5
	mov	x1, x21
	bl	_WREG32
	ldr	x8, [x26]
	add	x0, x8, #6
	mov	x1, x21
	bl	_WREG32
	ldr	x8, [x26]
	add	x0, x8, #7
	mov	x1, x21
	bl	_WREG32
Lloh146:
	adrp	x26, _mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR@GOTPAGE
Lloh147:
	ldr	x26, [x26, _mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR@GOTPAGEOFF]
	ldr	x0, [x26]
	mov	x1, x21
	bl	_WREG32
	ldr	x8, [x26]
	add	x0, x8, #1
	mov	x1, x21
	bl	_WREG32
	ldr	x8, [x26]
	add	x0, x8, #2
	mov	x1, x21
	bl	_WREG32
	ldr	x8, [x26]
	add	x0, x8, #3
	mov	x1, x21
	bl	_WREG32
	ldr	x8, [x26]
	add	x0, x8, #4
	mov	x1, x21
	bl	_WREG32
	ldr	x8, [x26]
	add	x0, x8, #5
	mov	x1, x21
	bl	_WREG32
	ldr	x8, [x26]
	add	x0, x8, #6
	mov	x1, x21
	bl	_WREG32
	ldr	x8, [x26]
	add	x0, x8, #7
	mov	x1, x21
	bl	_WREG32
Lloh148:
	adrp	x8, _mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR@GOTPAGE
Lloh149:
	ldr	x8, [x8, _mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR@GOTPAGEOFF]
Lloh150:
	ldr	x0, [x8]
	ldr	w8, [x19]
	asr	w1, w8, #12
	bl	_WREG32
Lloh151:
	adrp	x8, _mmVM_CONTEXT1_CNTL2@GOTPAGE
Lloh152:
	ldr	x8, [x8, _mmVM_CONTEXT1_CNTL2@GOTPAGEOFF]
Lloh153:
	ldr	x0, [x8]
	mov	w1, #4
	bl	_WREG32
Lloh154:
	adrp	x21, _mmVM_CONTEXT1_CNTL@GOTPAGE
Lloh155:
	ldr	x21, [x21, _mmVM_CONTEXT1_CNTL@GOTPAGEOFF]
	ldr	x0, [x21]
	bl	_RREG32
Lloh156:
	adrp	x26, _VM_CONTEXT1_CNTL@GOTPAGE
Lloh157:
	ldr	x26, [x26, _VM_CONTEXT1_CNTL@GOTPAGEOFF]
	ldr	w1, [x26]
	ldr	w2, [x23]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x26]
	ldr	w2, [x24]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x26]
	ldr	w2, [x25]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x26]
Lloh158:
	adrp	x8, _DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGE
Lloh159:
	ldr	x8, [x8, _DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGEOFF]
Lloh160:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x26]
Lloh161:
	adrp	x8, _PDE0_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGE
Lloh162:
	ldr	x8, [x8, _PDE0_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGEOFF]
Lloh163:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x26]
Lloh164:
	adrp	x8, _VALID_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGE
Lloh165:
	ldr	x8, [x8, _VALID_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGEOFF]
Lloh166:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x26]
Lloh167:
	adrp	x8, _READ_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGE
Lloh168:
	ldr	x8, [x8, _READ_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGEOFF]
Lloh169:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x26]
Lloh170:
	adrp	x8, _WRITE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGE
Lloh171:
	ldr	x8, [x8, _WRITE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGEOFF]
Lloh172:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x26]
Lloh173:
	adrp	x8, _EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGE
Lloh174:
	ldr	x8, [x8, _EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGEOFF]
Lloh175:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x26]
Lloh176:
	adrp	x8, _PAGE_TABLE_BLOCK_SIZE@GOTPAGE
Lloh177:
	ldr	x8, [x8, _PAGE_TABLE_BLOCK_SIZE@GOTPAGEOFF]
Lloh178:
	ldr	w2, [x8]
	ldr	w8, [x19, #44]
	sub	w3, w8, #9
	bl	_REG_SET_FIELD
	mov	x1, x0
	ldr	x0, [x21]
	bl	_WREG32
Lloh179:
	adrp	x8, _amdgpu_vm_fault_stop@GOTPAGE
Lloh180:
	ldr	x8, [x8, _amdgpu_vm_fault_stop@GOTPAGEOFF]
Lloh181:
	ldr	x8, [x8]
Lloh182:
	adrp	x9, _AMDGPU_VM_FAULT_STOP_ALWAYS@GOTPAGE
Lloh183:
	ldr	x9, [x9, _AMDGPU_VM_FAULT_STOP_ALWAYS@GOTPAGEOFF]
Lloh184:
	ldr	x9, [x9]
	cmp	x8, x9
	cset	w1, ne
	mov	x0, x19
	bl	_gmc_v8_0_set_fault_enable_default
	mov	x0, x19
	mov	w1, #0
	mov	w2, #0
	mov	w3, #0
	bl	_gmc_v8_0_flush_gpu_tlb
	ldr	w8, [x19, #32]
	asr	w1, w8, #20
	sxtw	x2, w20
Lloh185:
	adrp	x0, l_.str.1@PAGE
Lloh186:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_INFO
	mov	w0, #0
	str	w22, [x19, #8]
	b	LBB0_4
LBB0_3:
	ldr	w0, [x19, #48]
Lloh187:
	adrp	x1, l_.str@PAGE
Lloh188:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
Lloh189:
	adrp	x8, _EINVAL@GOTPAGE
Lloh190:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh191:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_4:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh185, Lloh186
	.loh AdrpLdrGotLdr	Lloh182, Lloh183, Lloh184
	.loh AdrpLdrGotLdr	Lloh179, Lloh180, Lloh181
	.loh AdrpLdrGotLdr	Lloh176, Lloh177, Lloh178
	.loh AdrpLdrGotLdr	Lloh173, Lloh174, Lloh175
	.loh AdrpLdrGotLdr	Lloh170, Lloh171, Lloh172
	.loh AdrpLdrGotLdr	Lloh167, Lloh168, Lloh169
	.loh AdrpLdrGotLdr	Lloh164, Lloh165, Lloh166
	.loh AdrpLdrGotLdr	Lloh161, Lloh162, Lloh163
	.loh AdrpLdrGotLdr	Lloh158, Lloh159, Lloh160
	.loh AdrpLdrGot	Lloh156, Lloh157
	.loh AdrpLdrGot	Lloh154, Lloh155
	.loh AdrpLdrGotLdr	Lloh151, Lloh152, Lloh153
	.loh AdrpLdrGotLdr	Lloh148, Lloh149, Lloh150
	.loh AdrpLdrGot	Lloh146, Lloh147
	.loh AdrpLdrGotLdr	Lloh143, Lloh144, Lloh145
	.loh AdrpLdrGotLdr	Lloh140, Lloh141, Lloh142
	.loh AdrpLdrGotLdr	Lloh137, Lloh138, Lloh139
	.loh AdrpLdrGotLdr	Lloh134, Lloh135, Lloh136
	.loh AdrpLdrGotLdr	Lloh131, Lloh132, Lloh133
	.loh AdrpLdrGot	Lloh129, Lloh130
	.loh AdrpLdrGot	Lloh127, Lloh128
	.loh AdrpLdrGot	Lloh125, Lloh126
	.loh AdrpLdrGot	Lloh123, Lloh124
	.loh AdrpLdrGot	Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.loh AdrpLdrGot	Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGot	Lloh69, Lloh70
	.loh AdrpLdrGot	Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGot	Lloh56, Lloh57
	.loh AdrpLdrGot	Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh189, Lloh190, Lloh191
	.loh AdrpAdd	Lloh187, Lloh188
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"No VRAM object for PCIE GART.\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_mmMC_VM_MX_L1_TLB_CNTL,8,3     ; @mmMC_VM_MX_L1_TLB_CNTL
	.comm	_MC_VM_MX_L1_TLB_CNTL,4,2       ; @MC_VM_MX_L1_TLB_CNTL
	.comm	_ENABLE_L1_TLB,4,2              ; @ENABLE_L1_TLB
	.comm	_ENABLE_L1_FRAGMENT_PROCESSING,4,2 ; @ENABLE_L1_FRAGMENT_PROCESSING
	.comm	_SYSTEM_ACCESS_MODE,4,2         ; @SYSTEM_ACCESS_MODE
	.comm	_ENABLE_ADVANCED_DRIVER_MODEL,4,2 ; @ENABLE_ADVANCED_DRIVER_MODEL
	.comm	_SYSTEM_APERTURE_UNMAPPED_ACCESS,4,2 ; @SYSTEM_APERTURE_UNMAPPED_ACCESS
	.comm	_mmVM_L2_CNTL,8,3               ; @mmVM_L2_CNTL
	.comm	_VM_L2_CNTL,4,2                 ; @VM_L2_CNTL
	.comm	_ENABLE_L2_CACHE,4,2            ; @ENABLE_L2_CACHE
	.comm	_ENABLE_L2_FRAGMENT_PROCESSING,4,2 ; @ENABLE_L2_FRAGMENT_PROCESSING
	.comm	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE,4,2 ; @ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE,4,2 ; @ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_EFFECTIVE_L2_QUEUE_SIZE,4,2    ; @EFFECTIVE_L2_QUEUE_SIZE
	.comm	_CONTEXT1_IDENTITY_ACCESS_MODE,4,2 ; @CONTEXT1_IDENTITY_ACCESS_MODE
	.comm	_ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY,4,2 ; @ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY
	.comm	_mmVM_L2_CNTL2,8,3              ; @mmVM_L2_CNTL2
	.comm	_VM_L2_CNTL2,4,2                ; @VM_L2_CNTL2
	.comm	_INVALIDATE_ALL_L1_TLBS,4,2     ; @INVALIDATE_ALL_L1_TLBS
	.comm	_INVALIDATE_L2_CACHE,4,2        ; @INVALIDATE_L2_CACHE
	.comm	_mmVM_L2_CNTL3,8,3              ; @mmVM_L2_CNTL3
	.comm	_VM_L2_CNTL3,4,2                ; @VM_L2_CNTL3
	.comm	_L2_CACHE_BIGK_ASSOCIATIVITY,4,2 ; @L2_CACHE_BIGK_ASSOCIATIVITY
	.comm	_BANK_SELECT,4,2                ; @BANK_SELECT
	.comm	_L2_CACHE_BIGK_FRAGMENT_SIZE,4,2 ; @L2_CACHE_BIGK_FRAGMENT_SIZE
	.comm	_mmVM_L2_CNTL4,8,3              ; @mmVM_L2_CNTL4
	.comm	_VM_L2_CNTL4,4,2                ; @VM_L2_CNTL4
	.comm	_VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL,4,2 ; @VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL
	.comm	_VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED,4,2 ; @VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED
	.comm	_VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP,4,2 ; @VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP
	.comm	_VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL,4,2 ; @VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL
	.comm	_VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED,4,2 ; @VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED
	.comm	_VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP,4,2 ; @VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP
	.comm	_VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL,4,2 ; @VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL
	.comm	_VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED,4,2 ; @VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED
	.comm	_VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP,4,2 ; @VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP
	.comm	_VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL,4,2 ; @VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL
	.comm	_VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED,4,2 ; @VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED
	.comm	_VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP,4,2 ; @VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP
	.comm	_mmVM_CONTEXT0_PAGE_TABLE_START_ADDR,8,3 ; @mmVM_CONTEXT0_PAGE_TABLE_START_ADDR
	.comm	_mmVM_CONTEXT0_PAGE_TABLE_END_ADDR,8,3 ; @mmVM_CONTEXT0_PAGE_TABLE_END_ADDR
	.comm	_mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR,8,3 ; @mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
	.comm	_mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,8,3 ; @mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
	.comm	_mmVM_CONTEXT0_CNTL2,8,3        ; @mmVM_CONTEXT0_CNTL2
	.comm	_mmVM_CONTEXT0_CNTL,8,3         ; @mmVM_CONTEXT0_CNTL
	.comm	_VM_CONTEXT0_CNTL,4,2           ; @VM_CONTEXT0_CNTL
	.comm	_ENABLE_CONTEXT,4,2             ; @ENABLE_CONTEXT
	.comm	_PAGE_TABLE_DEPTH,4,2           ; @PAGE_TABLE_DEPTH
	.comm	_RANGE_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ; @RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR,8,3 ; @mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR
	.comm	_mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR,8,3 ; @mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR
	.comm	_mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET,8,3 ; @mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET
	.comm	_mmVM_CONTEXT1_PAGE_TABLE_START_ADDR,8,3 ; @mmVM_CONTEXT1_PAGE_TABLE_START_ADDR
	.comm	_mmVM_CONTEXT1_PAGE_TABLE_END_ADDR,8,3 ; @mmVM_CONTEXT1_PAGE_TABLE_END_ADDR
	.comm	_mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR,8,3 ; @mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
	.comm	_mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,8,3 ; @mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR
	.comm	_mmVM_CONTEXT1_CNTL2,8,3        ; @mmVM_CONTEXT1_CNTL2
	.comm	_mmVM_CONTEXT1_CNTL,8,3         ; @mmVM_CONTEXT1_CNTL
	.comm	_VM_CONTEXT1_CNTL,4,2           ; @VM_CONTEXT1_CNTL
	.comm	_DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ; @DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_PDE0_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ; @PDE0_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_VALID_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ; @VALID_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_READ_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ; @READ_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_WRITE_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ; @WRITE_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ; @EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_PAGE_TABLE_BLOCK_SIZE,4,2      ; @PAGE_TABLE_BLOCK_SIZE
	.comm	_amdgpu_vm_fault_stop,8,3       ; @amdgpu_vm_fault_stop
	.comm	_AMDGPU_VM_FAULT_STOP_ALWAYS,8,3 ; @AMDGPU_VM_FAULT_STOP_ALWAYS
l_.str.1:                               ; @.str.1
	.asciz	"PCIE GART of %uM enabled (table at 0x%016llX).\n"

	.no_dead_strip	_gmc_v8_0_gart_enable
.subsections_via_symbols
