	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function uvd_v7_0_sw_init
_uvd_v7_0_sw_init:                      ## @uvd_v7_0_sw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	cmpl	$0, (%rdi)
	jle	LBB0_9
## %bb.1:
	xorl	%ebx, %ebx
	movq	_amdgpu_ih_clientid_uvds@GOTPCREL(%rip), %r14
	jmp	LBB0_2
	.p2align	4, 0x90
LBB0_8:                                 ##   in Loop: Header=BB0_2 Depth=1
	incq	%rbx
	movslq	(%r12), %rax
	cmpq	%rax, %rbx
	jge	LBB0_9
LBB0_2:                                 ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_7 Depth 2
	movl	4(%r12), %eax
	btl	%ebx, %eax
	jb	LBB0_8
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	(%r14), %rax
	movl	(%rax,%rbx,4), %esi
	movq	_UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%rbx, %r15
	shlq	$5, %r15
	movq	16(%r12), %rcx
	addq	%r15, %rcx
	movq	%r12, %rdi
	callq	_amdgpu_irq_add_id
	testl	%eax, %eax
	jne	LBB0_31
## %bb.4:                               ##   in Loop: Header=BB0_2 Depth=1
	cmpl	$0, 8(%r12)
	jle	LBB0_8
## %bb.5:                               ##   in Loop: Header=BB0_2 Depth=1
	xorl	%r13d, %r13d
	.p2align	4, 0x90
LBB0_7:                                 ##   Parent Loop BB0_2 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movq	(%r14), %rax
	movl	(%rax,%rbx,4), %esi
	movq	_UVD_7_0__SRCID__UVD_ENC_GEN_PURP@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	addq	%r13, %rdx
	movq	16(%r12), %rcx
	addq	%r15, %rcx
	movq	%r12, %rdi
	callq	_amdgpu_irq_add_id
	testl	%eax, %eax
	jne	LBB0_31
## %bb.6:                               ##   in Loop: Header=BB0_7 Depth=2
	incq	%r13
	movslq	8(%r12), %rax
	cmpq	%rax, %r13
	jl	LBB0_7
	jmp	LBB0_8
LBB0_9:
	movq	%r12, %rdi
	callq	_amdgpu_uvd_sw_init
	testl	%eax, %eax
	je	LBB0_10
LBB0_31:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_10:
	movq	40(%r12), %rax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_14
## %bb.11:
	movq	24(%r12), %rax
	movq	56(%r12), %rcx
	movq	(%rax), %rbx
	movq	_AMDGPU_UCODE_ID_UVD@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rsi
	movq	%rsi, %rdi
	shlq	$4, %rdi
	movq	%rsi, (%rcx,%rdi)
	movq	(%rdx), %rdx
	shlq	$4, %rdx
	movq	%rax, 8(%rcx,%rdx)
	movl	(%rbx), %edi
	callq	_le32_to_cpu
	movq	_PAGE_SIZE@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movl	%eax, %edi
	callq	_ALIGN
	addl	%eax, 48(%r12)
	movl	(%r12), %eax
	movq	_UVD7_MAX_HW_INSTANCES_VEGA20@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_13
## %bb.12:
	movq	_AMDGPU_UCODE_ID_UVD1@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	56(%r12), %rdx
	movq	%rcx, %rsi
	shlq	$4, %rsi
	movq	%rcx, (%rdx,%rsi)
	movq	24(%r12), %rcx
	movq	(%rax), %rax
	shlq	$4, %rax
	movq	%rcx, 8(%rdx,%rax)
	movl	(%rbx), %edi
	callq	_le32_to_cpu
	movl	(%r14), %esi
	movl	%eax, %edi
	callq	_ALIGN
	addl	%eax, 48(%r12)
LBB0_13:
	leaq	L_.str(%rip), %rdi
	callq	_DRM_INFO
LBB0_14:
	cmpl	$0, (%r12)
	jle	LBB0_29
## %bb.15:
	xorl	%ebx, %ebx
	jmp	LBB0_16
	.p2align	4, 0x90
LBB0_28:                                ##   in Loop: Header=BB0_16 Depth=1
	incq	%rbx
	movslq	(%r12), %rax
	cmpq	%rax, %rbx
	jge	LBB0_29
LBB0_16:                                ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_22 Depth 2
	movl	4(%r12), %eax
	btl	%ebx, %eax
	jb	LBB0_28
## %bb.17:                              ##   in Loop: Header=BB0_16 Depth=1
	movq	%r12, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	movq	%rbx, -48(%rbp)                 ## 8-byte Spill
	jne	LBB0_19
## %bb.18:                              ##   in Loop: Header=BB0_16 Depth=1
	movq	16(%r12), %rax
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	shlq	$5, %rbx
	leaq	(%rax,%rbx), %r14
	addq	$16, %r14
	movl	16(%rax,%rbx), %edx
	movl	28(%rax,%rbx), %edi
	leaq	L_.str.1(%rip), %rsi
	xorl	%eax, %eax
	callq	_sprintf
	addq	16(%r12), %rbx
	movq	%r12, %rdi
	movq	%r14, %rsi
	movl	$512, %edx                      ## imm = 0x200
	movq	%rbx, %rcx
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	xorl	%r8d, %r8d
	callq	_amdgpu_ring_init
	testl	%eax, %eax
	jne	LBB0_31
LBB0_19:                                ##   in Loop: Header=BB0_16 Depth=1
	cmpl	$0, 8(%r12)
	jle	LBB0_28
## %bb.20:                              ##   in Loop: Header=BB0_16 Depth=1
	xorl	%r15d, %r15d
	xorl	%r13d, %r13d
	.p2align	4, 0x90
LBB0_22:                                ##   Parent Loop BB0_16 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movq	16(%r12), %rax
	shlq	$5, %rbx
	movq	8(%rax,%rbx), %r14
	leaq	(%r14,%r15), %rax
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
	movl	(%r14,%r15), %edx
	movl	12(%r14,%r15), %edi
	leaq	L_.str.2(%rip), %rsi
	movl	%r13d, %ecx
	xorl	%eax, %eax
	callq	_sprintf
	movq	%r12, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_27
## %bb.23:                              ##   in Loop: Header=BB0_22 Depth=2
	movl	$1, 4(%r14,%r15)
	testq	%r15, %r15
	je	LBB0_24
## %bb.25:                              ##   in Loop: Header=BB0_22 Depth=2
	movl	36(%r12), %eax
	addl	%eax, %eax
	incl	%eax
	jmp	LBB0_26
	.p2align	4, 0x90
LBB0_24:                                ##   in Loop: Header=BB0_22 Depth=2
	movl	32(%r12), %eax
	addl	%eax, %eax
LBB0_26:                                ##   in Loop: Header=BB0_22 Depth=2
	movl	%eax, 8(%r14,%r15)
LBB0_27:                                ##   in Loop: Header=BB0_22 Depth=2
	addq	16(%r12), %rbx
	movq	%r12, %rdi
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
	movl	$512, %edx                      ## imm = 0x200
	movq	%rbx, %rcx
	xorl	%r8d, %r8d
	callq	_amdgpu_ring_init
	testl	%eax, %eax
	jne	LBB0_31
## %bb.21:                              ##   in Loop: Header=BB0_22 Depth=2
	incq	%r13
	movslq	8(%r12), %rax
	addq	$16, %r15
	cmpq	%rax, %r13
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	jl	LBB0_22
	jmp	LBB0_28
LBB0_29:
	movq	%r12, %rdi
	callq	_amdgpu_uvd_resume
	testl	%eax, %eax
	jne	LBB0_31
## %bb.30:
	movq	%r12, %rdi
	callq	_amdgpu_uvd_entity_init
	testl	%eax, %eax
	jne	LBB0_31
## %bb.32:
	movq	%r12, %rdi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_virt_alloc_mm_table     ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_amdgpu_ih_clientid_uvds,8,3    ## @amdgpu_ih_clientid_uvds
	.comm	_UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,8,3 ## @UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT
	.comm	_UVD_7_0__SRCID__UVD_ENC_GEN_PURP,8,3 ## @UVD_7_0__SRCID__UVD_ENC_GEN_PURP
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_UVD,8,3        ## @AMDGPU_UCODE_ID_UVD
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
	.comm	_UVD7_MAX_HW_INSTANCES_VEGA20,4,2 ## @UVD7_MAX_HW_INSTANCES_VEGA20
	.comm	_AMDGPU_UCODE_ID_UVD1,8,3       ## @AMDGPU_UCODE_ID_UVD1
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"PSP loading UVD firmware\n"

L_.str.1:                               ## @.str.1
	.asciz	"uvd_%d"

L_.str.2:                               ## @.str.2
	.asciz	"uvd_enc_%d.%d"

	.no_dead_strip	_uvd_v7_0_sw_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function uvd_v7_0_sw_init
_uvd_v7_0_sw_init:                      ; @uvd_v7_0_sw_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	w8, [x0]
	cmp	w8, #1
	b.lt	LBB0_9
; %bb.1:
	mov	x20, #0
Lloh0:
	adrp	x21, _amdgpu_ih_clientid_uvds@GOTPAGE
Lloh1:
	ldr	x21, [x21, _amdgpu_ih_clientid_uvds@GOTPAGEOFF]
Lloh2:
	adrp	x22, _UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT@GOTPAGE
Lloh3:
	ldr	x22, [x22, _UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT@GOTPAGEOFF]
Lloh4:
	adrp	x23, _UVD_7_0__SRCID__UVD_ENC_GEN_PURP@GOTPAGE
Lloh5:
	ldr	x23, [x23, _UVD_7_0__SRCID__UVD_ENC_GEN_PURP@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:                                 ;   in Loop: Header=BB0_3 Depth=1
	add	x20, x20, #1
	ldrsw	x8, [x19]
	cmp	x20, x8
	b.ge	LBB0_9
LBB0_3:                                 ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
	ldr	w8, [x19, #4]
	lsr	w8, w8, w20
	tbnz	w8, #0, LBB0_2
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	ldr	x8, [x21]
	ldr	w1, [x8, x20, lsl #2]
	ldr	x2, [x22]
	ldr	x8, [x19, #16]
	add	x3, x8, x20, lsl #5
	mov	x0, x19
	bl	_amdgpu_irq_add_id
	cbnz	w0, LBB0_10
; %bb.5:                                ;   in Loop: Header=BB0_3 Depth=1
	ldr	w8, [x19, #8]
	cmp	w8, #1
	b.lt	LBB0_2
; %bb.6:                                ;   in Loop: Header=BB0_3 Depth=1
	mov	x24, #0
LBB0_7:                                 ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ldr	x8, [x21]
	ldr	w1, [x8, x20, lsl #2]
	ldr	x8, [x23]
	add	x2, x24, x8
	ldr	x8, [x19, #16]
	add	x3, x8, x20, lsl #5
	mov	x0, x19
	bl	_amdgpu_irq_add_id
	cbnz	w0, LBB0_10
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=2
	add	x24, x24, #1
	ldrsw	x8, [x19, #8]
	cmp	x24, x8
	b.lt	LBB0_7
	b	LBB0_2
LBB0_9:
	mov	x0, x19
	bl	_amdgpu_uvd_sw_init
	cbz	w0, LBB0_11
LBB0_10:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
LBB0_11:
	ldr	x8, [x19, #40]
Lloh6:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh7:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh8:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_15
; %bb.12:
	ldr	x8, [x19, #24]
	ldr	x20, [x8]
Lloh9:
	adrp	x9, _AMDGPU_UCODE_ID_UVD@GOTPAGE
Lloh10:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_UVD@GOTPAGEOFF]
	ldr	x10, [x9]
	ldr	x11, [x19, #56]
	lsl	x12, x10, #4
	str	x10, [x11, x12]
	ldr	x9, [x9]
	add	x9, x11, x9, lsl #4
	str	x8, [x9, #8]
	ldr	w0, [x20]
	bl	_le32_to_cpu
Lloh11:
	adrp	x21, _PAGE_SIZE@GOTPAGE
Lloh12:
	ldr	x21, [x21, _PAGE_SIZE@GOTPAGEOFF]
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #48]
	add	w8, w8, w0
	str	w8, [x19, #48]
	ldr	w8, [x19]
Lloh13:
	adrp	x9, _UVD7_MAX_HW_INSTANCES_VEGA20@GOTPAGE
Lloh14:
	ldr	x9, [x9, _UVD7_MAX_HW_INSTANCES_VEGA20@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_14
; %bb.13:
Lloh16:
	adrp	x8, _AMDGPU_UCODE_ID_UVD1@GOTPAGE
Lloh17:
	ldr	x8, [x8, _AMDGPU_UCODE_ID_UVD1@GOTPAGEOFF]
	ldr	x9, [x8]
	ldr	x10, [x19, #56]
	lsl	x11, x9, #4
	str	x9, [x10, x11]
	ldr	x9, [x19, #24]
	ldr	x8, [x8]
	add	x8, x10, x8, lsl #4
	str	x9, [x8, #8]
	ldr	w0, [x20]
	bl	_le32_to_cpu
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #48]
	add	w8, w8, w0
	str	w8, [x19, #48]
LBB0_14:
Lloh18:
	adrp	x0, l_.str@PAGE
Lloh19:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_INFO
LBB0_15:
	ldr	w8, [x19]
	cmp	w8, #1
	b.lt	LBB0_30
; %bb.16:
	mov	x23, #0
Lloh20:
	adrp	x20, l_.str.1@PAGE
Lloh21:
	add	x20, x20, l_.str.1@PAGEOFF
	mov	w24, #1
Lloh22:
	adrp	x21, l_.str.2@PAGE
Lloh23:
	add	x21, x21, l_.str.2@PAGEOFF
	b	LBB0_18
LBB0_17:                                ;   in Loop: Header=BB0_18 Depth=1
	add	x23, x23, #1
	ldrsw	x8, [x19]
	cmp	x23, x8
	b.ge	LBB0_30
LBB0_18:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_23 Depth 2
	ldr	w8, [x19, #4]
	lsr	w8, w8, w23
	tbnz	w8, #0, LBB0_17
; %bb.19:                               ;   in Loop: Header=BB0_18 Depth=1
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbnz	x0, LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_18 Depth=1
	ldr	x8, [x19, #16]
	lsl	x25, x23, #5
	add	x22, x8, x25
	ldr	w2, [x22, #16]!
	ldr	w0, [x22, #12]
	mov	x1, x20
	bl	_sprintf
	ldr	x8, [x19, #16]
	add	x3, x8, x25
	mov	x0, x19
	mov	x1, x22
	mov	w2, #512
	mov	w4, #0
	bl	_amdgpu_ring_init
	cbnz	w0, LBB0_10
LBB0_21:                                ;   in Loop: Header=BB0_18 Depth=1
	ldr	w8, [x19, #8]
	cmp	w8, #1
	b.lt	LBB0_17
; %bb.22:                               ;   in Loop: Header=BB0_18 Depth=1
	mov	x25, #0
	mov	x26, #0
LBB0_23:                                ;   Parent Loop BB0_18 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ldr	x8, [x19, #16]
	add	x8, x8, x23, lsl #5
	ldr	x27, [x8, #8]
	add	x22, x27, x25
	ldr	w0, [x22, #12]
	ldr	w2, [x22]
	str	x26, [sp]
	mov	x1, x21
	bl	_sprintf
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_28
; %bb.24:                               ;   in Loop: Header=BB0_23 Depth=2
	str	w24, [x22, #4]
	cbz	x25, LBB0_26
; %bb.25:                               ;   in Loop: Header=BB0_23 Depth=2
	ldr	w9, [x19, #36]
	mov	w8, #1
	bfi	w8, w9, #1, #31
	b	LBB0_27
LBB0_26:                                ;   in Loop: Header=BB0_23 Depth=2
	ldr	w8, [x19, #32]
	lsl	w8, w8, #1
LBB0_27:                                ;   in Loop: Header=BB0_23 Depth=2
	add	x9, x27, x25
	str	w8, [x9, #8]
LBB0_28:                                ;   in Loop: Header=BB0_23 Depth=2
	ldr	x8, [x19, #16]
	add	x3, x8, x23, lsl #5
	mov	x0, x19
	mov	x1, x22
	mov	w2, #512
	mov	w4, #0
	bl	_amdgpu_ring_init
	cbnz	w0, LBB0_10
; %bb.29:                               ;   in Loop: Header=BB0_23 Depth=2
	add	x26, x26, #1
	ldrsw	x8, [x19, #8]
	add	x25, x25, #16
	cmp	x26, x8
	b.lt	LBB0_23
	b	LBB0_17
LBB0_30:
	mov	x0, x19
	bl	_amdgpu_uvd_resume
	cbnz	w0, LBB0_10
; %bb.31:
	mov	x0, x19
	bl	_amdgpu_uvd_entity_init
	cbnz	w0, LBB0_10
; %bb.32:
	mov	x0, x19
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	b	_amdgpu_virt_alloc_mm_table
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpAdd	Lloh18, Lloh19
	.loh AdrpAdd	Lloh22, Lloh23
	.loh AdrpAdd	Lloh20, Lloh21
	.cfi_endproc
                                        ; -- End function
	.comm	_amdgpu_ih_clientid_uvds,8,3    ; @amdgpu_ih_clientid_uvds
	.comm	_UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,8,3 ; @UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT
	.comm	_UVD_7_0__SRCID__UVD_ENC_GEN_PURP,8,3 ; @UVD_7_0__SRCID__UVD_ENC_GEN_PURP
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_UVD,8,3        ; @AMDGPU_UCODE_ID_UVD
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
	.comm	_UVD7_MAX_HW_INSTANCES_VEGA20,4,2 ; @UVD7_MAX_HW_INSTANCES_VEGA20
	.comm	_AMDGPU_UCODE_ID_UVD1,8,3       ; @AMDGPU_UCODE_ID_UVD1
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"PSP loading UVD firmware\n"

l_.str.1:                               ; @.str.1
	.asciz	"uvd_%d"

l_.str.2:                               ; @.str.2
	.asciz	"uvd_enc_%d.%d"

	.no_dead_strip	_uvd_v7_0_sw_init
.subsections_via_symbols
