	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v1_0_jpeg_ring_emit_reg_wait
_vcn_v1_0_jpeg_ring_emit_reg_wait:      ## @vcn_v1_0_jpeg_ring_emit_reg_wait
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, -48(%rbp)                 ## 4-byte Spill
	movl	%edx, -44(%rbp)                 ## 4-byte Spill
	movl	%esi, %r12d
	movq	%rdi, %rbx
	leal	(,%r12,4), %r15d
	movq	_UVD@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movq	_mmUVD_JRBC_RB_COND_RD_TIMER@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_PACKETJ_TYPE0@GOTPCREL(%rip), %r13
	movl	(%r13), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$20972032, %esi                 ## imm = 0x1400200
	callq	_amdgpu_ring_write
	movl	(%r14), %edi
	movq	_mmUVD_JRBC_RB_REF_DATA@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r13), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_amdgpu_ring_write
	movl	(%r14), %edi
	movq	_mmUVD_JRBC_EXTERNAL_REG_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r13), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	%r12d, %eax
	andl	$1073741696, %eax               ## imm = 0x3FFFFF80
	cmpl	$30720, %eax                    ## imm = 0x7800
	je	LBB0_2
## %bb.1:
	leal	-129024(,%r12,4), %eax
	cmpl	$10239, %eax                    ## imm = 0x27FF
	jbe	LBB0_2
## %bb.3:
	movq	%rbx, %rdi
	movl	%r15d, %esi
	callq	_amdgpu_ring_write
	xorl	%r15d, %r15d
	jmp	LBB0_4
LBB0_2:
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
	sarl	$2, %r15d
LBB0_4:
	movq	_PACKETJ_TYPE3@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%r15d, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	-48(%rbp), %esi                 ## 4-byte Reload
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_write              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_JRBC_RB_COND_RD_TIMER,4,2 ## @mmUVD_JRBC_RB_COND_RD_TIMER
	.comm	_PACKETJ_TYPE0,4,2              ## @PACKETJ_TYPE0
	.comm	_mmUVD_JRBC_RB_REF_DATA,4,2     ## @mmUVD_JRBC_RB_REF_DATA
	.comm	_mmUVD_JRBC_EXTERNAL_REG_BASE,4,2 ## @mmUVD_JRBC_EXTERNAL_REG_BASE
	.comm	_PACKETJ_TYPE3,4,2              ## @PACKETJ_TYPE3
	.no_dead_strip	_vcn_v1_0_jpeg_ring_emit_reg_wait
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v1_0_jpeg_ring_emit_reg_wait
_vcn_v1_0_jpeg_ring_emit_reg_wait:      ; @vcn_v1_0_jpeg_ring_emit_reg_wait
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x3
	mov	x23, x2
	mov	x22, x1
	mov	x20, x0
	lsl	w21, w1, #2
Lloh0:
	adrp	x24, _UVD@GOTPAGE
Lloh1:
	ldr	x24, [x24, _UVD@GOTPAGEOFF]
	ldr	w0, [x24]
Lloh2:
	adrp	x8, _mmUVD_JRBC_RB_COND_RD_TIMER@GOTPAGE
Lloh3:
	ldr	x8, [x8, _mmUVD_JRBC_RB_COND_RD_TIMER@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh5:
	adrp	x25, _PACKETJ_TYPE0@GOTPAGE
Lloh6:
	ldr	x25, [x25, _PACKETJ_TYPE0@GOTPAGEOFF]
	ldr	w3, [x25]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
	mov	x0, x20
	mov	w1, #512
	movk	w1, #320, lsl #16
	bl	_amdgpu_ring_write
	ldr	w0, [x24]
Lloh7:
	adrp	x8, _mmUVD_JRBC_RB_REF_DATA@GOTPAGE
Lloh8:
	ldr	x8, [x8, _mmUVD_JRBC_RB_REF_DATA@GOTPAGEOFF]
Lloh9:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w3, [x25]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
	mov	x0, x20
	mov	x1, x23
	bl	_amdgpu_ring_write
	ldr	w0, [x24]
Lloh10:
	adrp	x8, _mmUVD_JRBC_EXTERNAL_REG_BASE@GOTPAGE
Lloh11:
	ldr	x8, [x8, _mmUVD_JRBC_EXTERNAL_REG_BASE@GOTPAGEOFF]
Lloh12:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w3, [x25]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
	and	w8, w22, #0x3fffff80
	mov	w9, #30720
	cmp	w8, w9
	b.eq	LBB0_3
; %bb.1:
	mov	w8, #2048
	movk	w8, #65534, lsl #16
	add	w8, w21, w8
	lsr	w8, w8, #11
	cmp	w8, #4
	b.ls	LBB0_3
; %bb.2:
	mov	x0, x20
	mov	x1, x21
	bl	_amdgpu_ring_write
	mov	w0, #0
	b	LBB0_4
LBB0_3:
	mov	x0, x20
	mov	w1, #0
	bl	_amdgpu_ring_write
	asr	w0, w21, #2
LBB0_4:
Lloh13:
	adrp	x8, _PACKETJ_TYPE3@GOTPAGE
Lloh14:
	ldr	x8, [x8, _PACKETJ_TYPE3@GOTPAGEOFF]
Lloh15:
	ldr	w3, [x8]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
	mov	x0, x20
	mov	x1, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_amdgpu_ring_write
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.cfi_endproc
                                        ; -- End function
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_JRBC_RB_COND_RD_TIMER,4,2 ; @mmUVD_JRBC_RB_COND_RD_TIMER
	.comm	_PACKETJ_TYPE0,4,2              ; @PACKETJ_TYPE0
	.comm	_mmUVD_JRBC_RB_REF_DATA,4,2     ; @mmUVD_JRBC_RB_REF_DATA
	.comm	_mmUVD_JRBC_EXTERNAL_REG_BASE,4,2 ; @mmUVD_JRBC_EXTERNAL_REG_BASE
	.comm	_PACKETJ_TYPE3,4,2              ; @PACKETJ_TYPE3
	.no_dead_strip	_vcn_v1_0_jpeg_ring_emit_reg_wait
.subsections_via_symbols
