	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function sdma_v5_0_ctx_switch_enable
_sdma_v5_0_ctx_switch_enable:           ## @sdma_v5_0_ctx_switch_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, -44(%rbp)                 ## 4-byte Spill
	movq	%rdi, %r15
	movq	_amdgpu_sdma_phase_quantum@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	testl	%esi, %esi
	je	LBB0_1
## %bb.2:
	movq	_SDMA0_PHASE0_QUANTUM__VALUE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_SDMA0_PHASE0_QUANTUM__VALUE__SHIFT@GOTPCREL(%rip), %r12
	movl	(%r12), %eax
	movl	%eax, %ecx
	shrl	%cl, %ebx
	cmpl	%ebx, %esi
	jbe	LBB0_15
## %bb.3:
	xorl	%r13d, %r13d
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	incl	%esi
	shrl	%esi
	incl	%r13d
	cmpl	%ebx, %esi
	ja	LBB0_4
## %bb.5:
	movq	_SDMA0_PHASE0_QUANTUM__UNIT_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r14d
	movq	_SDMA0_PHASE0_QUANTUM__UNIT__SHIFT@GOTPCREL(%rip), %rdi
	movl	(%rdi), %edx
	movl	%edx, %ecx
	shrl	%cl, %r14d
	cmpl	%r14d, %r13d
	jbe	LBB0_7
## %bb.6:
	movl	%ebx, %edx
	movl	%r14d, %ecx
	shll	%cl, %edx
	leaq	L_.str(%rip), %rsi
	movq	%rdi, %r13
	movl	$1, %edi
	callq	_WARN_ONCE
	movl	(%r12), %eax
	movl	(%r13), %edx
	movl	%ebx, %esi
	movl	%r14d, %r13d
	jmp	LBB0_7
LBB0_1:
	xorl	%r13d, %r13d
	cmpl	$0, (%r15)
	jg	LBB0_9
	jmp	LBB0_14
LBB0_15:
	movq	_SDMA0_PHASE0_QUANTUM__UNIT__SHIFT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%r13d, %r13d
LBB0_7:
	movl	%eax, %ecx
	shll	%cl, %esi
	movl	%edx, %ecx
	shll	%cl, %r13d
	orl	%esi, %r13d
	cmpl	$0, (%r15)
	jle	LBB0_14
LBB0_9:
	xorl	%eax, %eax
	cmpl	$0, -44(%rbp)                   ## 4-byte Folded Reload
	setne	%al
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	xorl	%ebx, %ebx
	movq	_mmSDMA0_CNTL@GOTPCREL(%rip), %rax
	jmp	LBB0_10
	.p2align	4, 0x90
LBB0_13:                                ##   in Loop: Header=BB0_10 Depth=1
	movl	(%r12), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	%r12, %rax
	incl	%ebx
	cmpl	(%r15), %ebx
	jge	LBB0_14
LBB0_10:                                ## =>This Inner Loop Header: Depth=1
	movq	%rax, %r12
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	callq	_RREG32
	movq	_SDMA0_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_AUTO_CTXSW_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	-48(%rbp), %ecx                 ## 4-byte Reload
	callq	_REG_SET_FIELD
	movl	%eax, %r14d
	cmpl	$0, -44(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_13
## %bb.11:                              ##   in Loop: Header=BB0_10 Depth=1
	movq	_amdgpu_sdma_phase_quantum@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	je	LBB0_13
## %bb.12:                              ##   in Loop: Header=BB0_10 Depth=1
	movq	_mmSDMA0_PHASE0_QUANTUM@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	movl	%r13d, %esi
	callq	_WREG32
	movq	_mmSDMA0_PHASE1_QUANTUM@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	movl	%r13d, %esi
	callq	_WREG32
	movq	_mmSDMA0_PHASE2_QUANTUM@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	movl	%r13d, %esi
	callq	_WREG32
	jmp	LBB0_13
LBB0_14:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_amdgpu_sdma_phase_quantum,4,2  ## @amdgpu_sdma_phase_quantum
	.comm	_SDMA0_PHASE0_QUANTUM__VALUE_MASK,4,2 ## @SDMA0_PHASE0_QUANTUM__VALUE_MASK
	.comm	_SDMA0_PHASE0_QUANTUM__VALUE__SHIFT,4,2 ## @SDMA0_PHASE0_QUANTUM__VALUE__SHIFT
	.comm	_SDMA0_PHASE0_QUANTUM__UNIT_MASK,4,2 ## @SDMA0_PHASE0_QUANTUM__UNIT_MASK
	.comm	_SDMA0_PHASE0_QUANTUM__UNIT__SHIFT,4,2 ## @SDMA0_PHASE0_QUANTUM__UNIT__SHIFT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"clamping sdma_phase_quantum to %uK clock cycles\n"

	.comm	_mmSDMA0_CNTL,4,2               ## @mmSDMA0_CNTL
	.comm	_SDMA0_CNTL,4,2                 ## @SDMA0_CNTL
	.comm	_AUTO_CTXSW_ENABLE,4,2          ## @AUTO_CTXSW_ENABLE
	.comm	_mmSDMA0_PHASE0_QUANTUM,4,2     ## @mmSDMA0_PHASE0_QUANTUM
	.comm	_mmSDMA0_PHASE1_QUANTUM,4,2     ## @mmSDMA0_PHASE1_QUANTUM
	.comm	_mmSDMA0_PHASE2_QUANTUM,4,2     ## @mmSDMA0_PHASE2_QUANTUM
	.no_dead_strip	_sdma_v5_0_ctx_switch_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function sdma_v5_0_ctx_switch_enable
_sdma_v5_0_ctx_switch_enable:           ; @sdma_v5_0_ctx_switch_enable
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x1
	mov	x20, x0
Lloh0:
	adrp	x8, _amdgpu_sdma_phase_quantum@GOTPAGE
Lloh1:
	ldr	x8, [x8, _amdgpu_sdma_phase_quantum@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x8]
	cbz	w9, LBB0_6
; %bb.1:
Lloh3:
	adrp	x8, _SDMA0_PHASE0_QUANTUM__VALUE_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _SDMA0_PHASE0_QUANTUM__VALUE_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w10, [x8]
Lloh6:
	adrp	x22, _SDMA0_PHASE0_QUANTUM__VALUE__SHIFT@GOTPAGE
Lloh7:
	ldr	x22, [x22, _SDMA0_PHASE0_QUANTUM__VALUE__SHIFT@GOTPAGEOFF]
	ldr	w8, [x22]
	lsr	w21, w10, w8
	cmp	w9, w21
	b.ls	LBB0_7
; %bb.2:
	mov	w10, #0
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	add	w9, w9, #1
	lsr	w9, w9, #1
	add	w10, w10, #1
	cmp	w9, w21
	b.hi	LBB0_3
; %bb.4:
Lloh8:
	adrp	x11, _SDMA0_PHASE0_QUANTUM__UNIT_MASK@GOTPAGE
Lloh9:
	ldr	x11, [x11, _SDMA0_PHASE0_QUANTUM__UNIT_MASK@GOTPAGEOFF]
Lloh10:
	ldr	w12, [x11]
Lloh11:
	adrp	x24, _SDMA0_PHASE0_QUANTUM__UNIT__SHIFT@GOTPAGE
Lloh12:
	ldr	x24, [x24, _SDMA0_PHASE0_QUANTUM__UNIT__SHIFT@GOTPAGEOFF]
	ldr	w11, [x24]
	lsr	w23, w12, w11
	cmp	w10, w23
	b.ls	LBB0_8
; %bb.5:
	lsl	w2, w21, w23
Lloh13:
	adrp	x1, l_.str@PAGE
Lloh14:
	add	x1, x1, l_.str@PAGEOFF
	mov	w0, #1
	bl	_WARN_ONCE
	ldr	w8, [x22]
	ldr	w11, [x24]
	mov	x9, x21
	mov	x10, x23
	b	LBB0_8
LBB0_6:
	mov	w21, #0
	b	LBB0_9
LBB0_7:
	mov	w10, #0
Lloh15:
	adrp	x11, _SDMA0_PHASE0_QUANTUM__UNIT__SHIFT@GOTPAGE
Lloh16:
	ldr	x11, [x11, _SDMA0_PHASE0_QUANTUM__UNIT__SHIFT@GOTPAGEOFF]
Lloh17:
	ldr	w11, [x11]
LBB0_8:
	lsl	w8, w9, w8
	lsl	w9, w10, w11
	orr	w21, w9, w8
LBB0_9:
	ldr	w8, [x20]
	cmp	w8, #1
	b.lt	LBB0_15
; %bb.10:
	mov	w22, #0
	cmp	w19, #0
	cset	w23, ne
Lloh18:
	adrp	x26, _mmSDMA0_CNTL@GOTPAGE
Lloh19:
	ldr	x26, [x26, _mmSDMA0_CNTL@GOTPAGEOFF]
Lloh20:
	adrp	x27, _SDMA0_CNTL@GOTPAGE
Lloh21:
	ldr	x27, [x27, _SDMA0_CNTL@GOTPAGEOFF]
Lloh22:
	adrp	x28, _AUTO_CTXSW_ENABLE@GOTPAGE
Lloh23:
	ldr	x28, [x28, _AUTO_CTXSW_ENABLE@GOTPAGEOFF]
Lloh24:
	adrp	x25, _mmSDMA0_PHASE2_QUANTUM@GOTPAGE
Lloh25:
	ldr	x25, [x25, _mmSDMA0_PHASE2_QUANTUM@GOTPAGEOFF]
	b	LBB0_12
LBB0_11:                                ;   in Loop: Header=BB0_12 Depth=1
	ldr	w2, [x26]
	mov	x0, x20
	mov	x1, x22
	bl	_sdma_v5_0_get_reg_offset
	mov	x1, x24
	bl	_WREG32
	add	w22, w22, #1
	ldr	w8, [x20]
	cmp	w22, w8
	b.ge	LBB0_15
LBB0_12:                                ; =>This Inner Loop Header: Depth=1
	ldr	w2, [x26]
	mov	x0, x20
	mov	x1, x22
	bl	_sdma_v5_0_get_reg_offset
	bl	_RREG32
	ldr	w1, [x27]
	ldr	w2, [x28]
	mov	x3, x23
	bl	_REG_SET_FIELD
	mov	x24, x0
	cbz	w19, LBB0_11
; %bb.13:                               ;   in Loop: Header=BB0_12 Depth=1
Lloh26:
	adrp	x8, _amdgpu_sdma_phase_quantum@GOTPAGE
Lloh27:
	ldr	x8, [x8, _amdgpu_sdma_phase_quantum@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
	cbz	w8, LBB0_11
; %bb.14:                               ;   in Loop: Header=BB0_12 Depth=1
Lloh29:
	adrp	x8, _mmSDMA0_PHASE0_QUANTUM@GOTPAGE
Lloh30:
	ldr	x8, [x8, _mmSDMA0_PHASE0_QUANTUM@GOTPAGEOFF]
Lloh31:
	ldr	w2, [x8]
	mov	x0, x20
	mov	x1, x22
	bl	_sdma_v5_0_get_reg_offset
	mov	x1, x21
	bl	_WREG32
Lloh32:
	adrp	x8, _mmSDMA0_PHASE1_QUANTUM@GOTPAGE
Lloh33:
	ldr	x8, [x8, _mmSDMA0_PHASE1_QUANTUM@GOTPAGEOFF]
Lloh34:
	ldr	w2, [x8]
	mov	x0, x20
	mov	x1, x22
	bl	_sdma_v5_0_get_reg_offset
	mov	x1, x21
	bl	_WREG32
	ldr	w2, [x25]
	mov	x0, x20
	mov	x1, x22
	bl	_sdma_v5_0_get_reg_offset
	mov	x1, x21
	bl	_WREG32
	b	LBB0_11
LBB0_15:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpAdd	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.cfi_endproc
                                        ; -- End function
	.comm	_amdgpu_sdma_phase_quantum,4,2  ; @amdgpu_sdma_phase_quantum
	.comm	_SDMA0_PHASE0_QUANTUM__VALUE_MASK,4,2 ; @SDMA0_PHASE0_QUANTUM__VALUE_MASK
	.comm	_SDMA0_PHASE0_QUANTUM__VALUE__SHIFT,4,2 ; @SDMA0_PHASE0_QUANTUM__VALUE__SHIFT
	.comm	_SDMA0_PHASE0_QUANTUM__UNIT_MASK,4,2 ; @SDMA0_PHASE0_QUANTUM__UNIT_MASK
	.comm	_SDMA0_PHASE0_QUANTUM__UNIT__SHIFT,4,2 ; @SDMA0_PHASE0_QUANTUM__UNIT__SHIFT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"clamping sdma_phase_quantum to %uK clock cycles\n"

	.comm	_mmSDMA0_CNTL,4,2               ; @mmSDMA0_CNTL
	.comm	_SDMA0_CNTL,4,2                 ; @SDMA0_CNTL
	.comm	_AUTO_CTXSW_ENABLE,4,2          ; @AUTO_CTXSW_ENABLE
	.comm	_mmSDMA0_PHASE0_QUANTUM,4,2     ; @mmSDMA0_PHASE0_QUANTUM
	.comm	_mmSDMA0_PHASE1_QUANTUM,4,2     ; @mmSDMA0_PHASE1_QUANTUM
	.comm	_mmSDMA0_PHASE2_QUANTUM,4,2     ; @mmSDMA0_PHASE2_QUANTUM
	.no_dead_strip	_sdma_v5_0_ctx_switch_enable
.subsections_via_symbols
