	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function socfpga_fpga_dclk_set_and_wait_clear
_socfpga_fpga_dclk_set_and_wait_clear:  ## @socfpga_fpga_dclk_set_and_wait_clear
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %rbx
	movq	_SOCFPGA_FPGMGR_DCLKSTAT_OFST@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	callq	_socfpga_fpga_readl
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	%rbx, %rdi
	callq	_socfpga_fpga_clear_done_status
LBB0_2:
	movq	_SOCFPGA_FPGMGR_DCLKCNT_OFST@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	callq	_socfpga_fpga_writel
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_socfpga_fpga_readl
	movq	_SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE@GOTPCREL(%rip), %r14
	cmpq	(%r14), %rax
	je	LBB0_3
## %bb.4:
	movl	$1, %edi
	callq	_udelay
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_socfpga_fpga_readl
	cmpq	(%r14), %rax
	je	LBB0_3
## %bb.5:
	movl	$1, %edi
	callq	_udelay
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_socfpga_fpga_readl
	cmpq	(%r14), %rax
	jne	LBB0_6
LBB0_3:
	movq	%rbx, %rdi
	callq	_socfpga_fpga_clear_done_status
	xorl	%eax, %eax
LBB0_7:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_6:
	movl	$1, %edi
	callq	_udelay
	movq	_ETIMEDOUT@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_7
	.cfi_endproc
                                        ## -- End function
	.comm	_SOCFPGA_FPGMGR_DCLKSTAT_OFST,4,2 ## @SOCFPGA_FPGMGR_DCLKSTAT_OFST
	.comm	_SOCFPGA_FPGMGR_DCLKCNT_OFST,4,2 ## @SOCFPGA_FPGMGR_DCLKCNT_OFST
	.comm	_SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE,8,3 ## @SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE
	.comm	_ETIMEDOUT,4,2                  ## @ETIMEDOUT
	.no_dead_strip	_socfpga_fpga_dclk_set_and_wait_clear
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function socfpga_fpga_dclk_set_and_wait_clear
_socfpga_fpga_dclk_set_and_wait_clear:  ; @socfpga_fpga_dclk_set_and_wait_clear
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x21, _SOCFPGA_FPGMGR_DCLKSTAT_OFST@GOTPAGE
Lloh1:
	ldr	x21, [x21, _SOCFPGA_FPGMGR_DCLKSTAT_OFST@GOTPAGEOFF]
	ldr	w1, [x21]
	bl	_socfpga_fpga_readl
	cbz	x0, LBB0_2
; %bb.1:
	mov	x0, x19
	bl	_socfpga_fpga_clear_done_status
LBB0_2:
Lloh2:
	adrp	x8, _SOCFPGA_FPGMGR_DCLKCNT_OFST@GOTPAGE
Lloh3:
	ldr	x8, [x8, _SOCFPGA_FPGMGR_DCLKCNT_OFST@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_socfpga_fpga_writel
	ldr	w1, [x21]
	mov	x0, x19
	bl	_socfpga_fpga_readl
Lloh5:
	adrp	x20, _SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE@GOTPAGE
Lloh6:
	ldr	x20, [x20, _SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE@GOTPAGEOFF]
	ldr	x8, [x20]
	cmp	x0, x8
	b.eq	LBB0_5
; %bb.3:
	mov	w0, #1
	bl	_udelay
	ldr	w1, [x21]
	mov	x0, x19
	bl	_socfpga_fpga_readl
	ldr	x8, [x20]
	cmp	x0, x8
	b.eq	LBB0_5
; %bb.4:
	mov	w0, #1
	bl	_udelay
	ldr	w1, [x21]
	mov	x0, x19
	bl	_socfpga_fpga_readl
	ldr	x8, [x20]
	cmp	x0, x8
	b.ne	LBB0_7
LBB0_5:
	mov	x0, x19
	bl	_socfpga_fpga_clear_done_status
	mov	w0, #0
LBB0_6:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_7:
	mov	w0, #1
	bl	_udelay
Lloh7:
	adrp	x8, _ETIMEDOUT@GOTPAGE
Lloh8:
	ldr	x8, [x8, _ETIMEDOUT@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_6
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.cfi_endproc
                                        ; -- End function
	.comm	_SOCFPGA_FPGMGR_DCLKSTAT_OFST,4,2 ; @SOCFPGA_FPGMGR_DCLKSTAT_OFST
	.comm	_SOCFPGA_FPGMGR_DCLKCNT_OFST,4,2 ; @SOCFPGA_FPGMGR_DCLKCNT_OFST
	.comm	_SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE,8,3 ; @SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE
	.comm	_ETIMEDOUT,4,2                  ; @ETIMEDOUT
	.no_dead_strip	_socfpga_fpga_dclk_set_and_wait_clear
.subsections_via_symbols
