	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v9_0_ring_emit_fence
_gfx_v9_0_ring_emit_fence:              ## @gfx_v9_0_ring_emit_fence
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %r12d
	movl	%edx, -52(%rbp)                 ## 4-byte Spill
	movl	%esi, -48(%rbp)                 ## 4-byte Spill
	movq	%rdi, %r13
	movq	_AMDGPU_FENCE_FLAG_64BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	_AMDGPU_FENCE_FLAG_INT@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_AMDGPU_FENCE_FLAG_TC_WB_ONLY@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	andl	%ecx, %ebx
	movq	_PACKET3_RELEASE_MEM@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$6, %esi
	callq	_PACKET3
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	testl	%ebx, %ebx
	je	LBB0_2
## %bb.1:
	movq	_EOP_TC_NC_ACTION_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_EOP_TC_WB_ACTION_EN@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_2:
	movq	_EOP_TCL1_ACTION_EN@GOTPCREL(%rip), %rax
	movq	_EOP_TC_ACTION_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	_EOP_TC_WB_ACTION_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_EOP_TC_MD_ACTION_EN@GOTPCREL(%rip), %rax
LBB0_3:
	xorl	%r15d, %r15d
	testl	%r12d, %r14d
	setne	%r15b
	orl	(%rax), %ebx
	movq	_CACHE_FLUSH_AND_INV_TS_EVENT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_EVENT_TYPE
	movl	%eax, %r14d
	movl	$5, %edi
	callq	_EVENT_INDEX
	orl	%eax, %r14d
	orl	%ebx, %r14d
	movq	%r13, %rdi
	movl	%r14d, %esi
	callq	_amdgpu_ring_write
	xorl	%r14d, %r14d
	xorl	%eax, %eax
	testl	%r12d, -44(%rbp)                ## 4-byte Folded Reload
	setne	%r14b
	sete	%al
	movl	$2, %edi
	subl	%eax, %edi
	callq	_DATA_SEL
	movl	%eax, %ebx
	addl	%r15d, %r15d
	movl	%r15d, %edi
	callq	_INT_SEL
	orl	%eax, %ebx
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_amdgpu_ring_write
	leal	3(,%r14,4), %edi
	movl	-48(%rbp), %ebx                 ## 4-byte Reload
	andl	%ebx, %edi
	callq	_BUG_ON
	movl	%ebx, %edi
	callq	_lower_32_bits
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	%ebx, %edi
	callq	_upper_32_bits
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	-52(%rbp), %ebx                 ## 4-byte Reload
	movl	%ebx, %edi
	callq	_lower_32_bits
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	%ebx, %edi
	callq	_upper_32_bits
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r13, %rdi
	xorl	%esi, %esi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_write              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_FENCE_FLAG_64BIT,4,2    ## @AMDGPU_FENCE_FLAG_64BIT
	.comm	_AMDGPU_FENCE_FLAG_INT,4,2      ## @AMDGPU_FENCE_FLAG_INT
	.comm	_AMDGPU_FENCE_FLAG_TC_WB_ONLY,4,2 ## @AMDGPU_FENCE_FLAG_TC_WB_ONLY
	.comm	_PACKET3_RELEASE_MEM,4,2        ## @PACKET3_RELEASE_MEM
	.comm	_EOP_TC_WB_ACTION_EN,4,2        ## @EOP_TC_WB_ACTION_EN
	.comm	_EOP_TC_NC_ACTION_EN,4,2        ## @EOP_TC_NC_ACTION_EN
	.comm	_EOP_TCL1_ACTION_EN,4,2         ## @EOP_TCL1_ACTION_EN
	.comm	_EOP_TC_ACTION_EN,4,2           ## @EOP_TC_ACTION_EN
	.comm	_EOP_TC_MD_ACTION_EN,4,2        ## @EOP_TC_MD_ACTION_EN
	.comm	_CACHE_FLUSH_AND_INV_TS_EVENT,4,2 ## @CACHE_FLUSH_AND_INV_TS_EVENT
	.no_dead_strip	_gfx_v9_0_ring_emit_fence
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v9_0_ring_emit_fence
_gfx_v9_0_ring_emit_fence:              ; @gfx_v9_0_ring_emit_fence
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x22, x3
	mov	x20, x2
	mov	x21, x1
	mov	x19, x0
Lloh0:
	adrp	x8, _AMDGPU_FENCE_FLAG_64BIT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPU_FENCE_FLAG_64BIT@GOTPAGEOFF]
Lloh2:
	ldr	w23, [x8]
Lloh3:
	adrp	x8, _AMDGPU_FENCE_FLAG_INT@GOTPAGE
Lloh4:
	ldr	x8, [x8, _AMDGPU_FENCE_FLAG_INT@GOTPAGEOFF]
Lloh5:
	adrp	x9, _AMDGPU_FENCE_FLAG_TC_WB_ONLY@GOTPAGE
Lloh6:
	ldr	x9, [x9, _AMDGPU_FENCE_FLAG_TC_WB_ONLY@GOTPAGEOFF]
Lloh7:
	ldr	w24, [x8]
Lloh8:
	ldr	w8, [x9]
	and	w25, w8, w3
Lloh9:
	adrp	x8, _PACKET3_RELEASE_MEM@GOTPAGE
Lloh10:
	ldr	x8, [x8, _PACKET3_RELEASE_MEM@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	mov	w1, #6
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	cbz	w25, LBB0_2
; %bb.1:
Lloh12:
	adrp	x8, _EOP_TC_NC_ACTION_EN@GOTPAGE
Lloh13:
	ldr	x8, [x8, _EOP_TC_NC_ACTION_EN@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
Lloh15:
	adrp	x9, _EOP_TC_WB_ACTION_EN@GOTPAGE
Lloh16:
	ldr	x9, [x9, _EOP_TC_WB_ACTION_EN@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:
Lloh17:
	adrp	x8, _EOP_TCL1_ACTION_EN@GOTPAGE
Lloh18:
	ldr	x8, [x8, _EOP_TCL1_ACTION_EN@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
Lloh20:
	adrp	x9, _EOP_TC_ACTION_EN@GOTPAGE
Lloh21:
	ldr	x9, [x9, _EOP_TC_ACTION_EN@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh23:
	adrp	x9, _EOP_TC_WB_ACTION_EN@GOTPAGE
Lloh24:
	ldr	x9, [x9, _EOP_TC_WB_ACTION_EN@GOTPAGEOFF]
Lloh25:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh26:
	adrp	x9, _EOP_TC_MD_ACTION_EN@GOTPAGE
Lloh27:
	ldr	x9, [x9, _EOP_TC_MD_ACTION_EN@GOTPAGEOFF]
LBB0_3:
	ldr	w9, [x9]
	tst	w24, w22
	cset	w24, ne
	orr	w25, w8, w9
Lloh28:
	adrp	x8, _CACHE_FLUSH_AND_INV_TS_EVENT@GOTPAGE
Lloh29:
	ldr	x8, [x8, _CACHE_FLUSH_AND_INV_TS_EVENT@GOTPAGEOFF]
Lloh30:
	ldr	w0, [x8]
	bl	_EVENT_TYPE
	orr	w25, w0, w25
	mov	w0, #5
	bl	_EVENT_INDEX
	orr	w1, w25, w0
	mov	x0, x19
	bl	_amdgpu_ring_write
	tst	w23, w22
	mov	w8, #1
	cinc	w0, w8, ne
	mov	w8, #7
	mov	w9, #3
	csel	w23, w9, w8, eq
	bl	_DATA_SEL
	mov	x22, x0
	lsl	w0, w24, #1
	bl	_INT_SEL
	orr	w1, w0, w22
	mov	x0, x19
	bl	_amdgpu_ring_write
	and	w0, w23, w21
	bl	_BUG_ON
	mov	x0, x21
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x21
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x20
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x20
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_amdgpu_ring_write
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh7
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_FENCE_FLAG_64BIT,4,2    ; @AMDGPU_FENCE_FLAG_64BIT
	.comm	_AMDGPU_FENCE_FLAG_INT,4,2      ; @AMDGPU_FENCE_FLAG_INT
	.comm	_AMDGPU_FENCE_FLAG_TC_WB_ONLY,4,2 ; @AMDGPU_FENCE_FLAG_TC_WB_ONLY
	.comm	_PACKET3_RELEASE_MEM,4,2        ; @PACKET3_RELEASE_MEM
	.comm	_EOP_TC_WB_ACTION_EN,4,2        ; @EOP_TC_WB_ACTION_EN
	.comm	_EOP_TC_NC_ACTION_EN,4,2        ; @EOP_TC_NC_ACTION_EN
	.comm	_EOP_TCL1_ACTION_EN,4,2         ; @EOP_TCL1_ACTION_EN
	.comm	_EOP_TC_ACTION_EN,4,2           ; @EOP_TC_ACTION_EN
	.comm	_EOP_TC_MD_ACTION_EN,4,2        ; @EOP_TC_MD_ACTION_EN
	.comm	_CACHE_FLUSH_AND_INV_TS_EVENT,4,2 ; @CACHE_FLUSH_AND_INV_TS_EVENT
	.no_dead_strip	_gfx_v9_0_ring_emit_fence
.subsections_via_symbols
