	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function cdv_intel_dp_mode_set
_cdv_intel_dp_mode_set:                 ## @cdv_intel_dp_mode_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r12
	movq	%rsi, %r15
	movq	%rdi, %rbx
	callq	_to_gma_encoder
	movq	%rax, %r13
	movq	8(%rbx), %rdi
	callq	_to_gma_crtc
	movq	%rax, %r14
	movq	_DP_VOLTAGE_0_4@GOTPCREL(%rip), %rcx
	movq	_DP_PRE_EMPHASIS_0@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	(%rcx), %eax
	movq	(%r13), %rbx
	orl	4(%rbx), %eax
	movl	%eax, (%rbx)
	movl	(%r12), %ecx
	movq	_DRM_MODE_FLAG_PHSYNC@GOTPCREL(%rip), %rdx
	testl	%ecx, (%rdx)
	je	LBB0_2
## %bb.1:
	movq	_DP_SYNC_HS_HIGH@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movl	%eax, (%rbx)
LBB0_2:
	movq	_DRM_MODE_FLAG_PVSYNC@GOTPCREL(%rip), %rdx
	testl	%ecx, (%rdx)
	je	LBB0_4
## %bb.3:
	movq	_DP_SYNC_VS_HIGH@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%rbx)
LBB0_4:
	movq	_DP_LINK_TRAIN_OFF@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%rbx)
	movl	8(%rbx), %ecx
	cmpl	$1, %ecx
	je	LBB0_5
## %bb.6:
	cmpl	$4, %ecx
	je	LBB0_9
## %bb.7:
	cmpl	$2, %ecx
	jne	LBB0_11
## %bb.8:
	movq	_DP_PORT_WIDTH_2@GOTPCREL(%rip), %rcx
	jmp	LBB0_10
LBB0_5:
	movq	_DP_PORT_WIDTH_1@GOTPCREL(%rip), %rcx
	jmp	LBB0_10
LBB0_9:
	movq	_DP_PORT_WIDTH_4@GOTPCREL(%rip), %rcx
LBB0_10:
	orl	(%rcx), %eax
	movl	%eax, (%rbx)
LBB0_11:
	cmpq	$0, 48(%rbx)
	je	LBB0_13
## %bb.12:
	movq	_DP_AUDIO_OUTPUT_ENABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%rbx)
LBB0_13:
	movq	16(%rbx), %rdi
	movq	_DP_LINK_CONFIGURATION_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_memset
	movl	24(%rbx), %ecx
	movq	16(%rbx), %rax
	movl	%ecx, (%rax)
	movl	8(%rbx), %ecx
	movl	%ecx, 4(%rax)
	movq	32(%rbx), %rdx
	movq	_DP_DPCD_REV@GOTPCREL(%rip), %rsi
	movq	(%rsi), %rsi
	cmpl	$17, (%rdx,%rsi,4)
	jl	LBB0_16
## %bb.14:
	movq	_DP_MAX_LANE_COUNT@GOTPCREL(%rip), %rsi
	movq	(%rsi), %rsi
	movq	_DP_ENHANCED_FRAME_CAP@GOTPCREL(%rip), %rdi
	movl	(%rdi), %edi
	testl	%edi, (%rdx,%rsi,4)
	je	LBB0_16
## %bb.15:
	movq	_DP_LANE_COUNT_ENHANCED_FRAME_EN@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movl	%ecx, 4(%rax)
	movq	_DP_ENHANCED_FRAMING@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%rbx)
LBB0_16:
	cmpl	$1, (%r14)
	jne	LBB0_17
## %bb.18:
	movq	_DP_PIPEB_SELECT@GOTPCREL(%rip), %rax
	movl	(%rbx), %esi
	orl	(%rax), %esi
	movl	%esi, (%rbx)
	jmp	LBB0_19
LBB0_17:
	movl	(%rbx), %esi
LBB0_19:
	movl	40(%rbx), %edi
	movq	_DP_PORT_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	callq	_REG_WRITE
	movl	(%rbx), %esi
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	movq	%r13, %rdi
	callq	_is_edp
	testq	%rax, %rax
	je	LBB0_24
## %bb.20:
	movq	%r13, %rdi
	callq	_cdv_intel_edp_panel_on
	movq	8(%r15), %rax
	cmpq	8(%r12), %rax
	jne	LBB0_22
## %bb.21:
	movq	16(%r15), %rcx
	xorl	%eax, %eax
	cmpq	16(%r12), %rcx
	je	LBB0_23
LBB0_22:
	movq	_PFIT_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_23:
	movl	(%r14), %esi
	movq	_PFIT_PIPE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %esi
	orl	%eax, %esi
	movq	_PFIT_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_REG_WRITE                      ## TAILCALL
LBB0_24:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DP_VOLTAGE_0_4,4,2             ## @DP_VOLTAGE_0_4
	.comm	_DP_PRE_EMPHASIS_0,4,2          ## @DP_PRE_EMPHASIS_0
	.comm	_DRM_MODE_FLAG_PHSYNC,4,2       ## @DRM_MODE_FLAG_PHSYNC
	.comm	_DP_SYNC_HS_HIGH,4,2            ## @DP_SYNC_HS_HIGH
	.comm	_DRM_MODE_FLAG_PVSYNC,4,2       ## @DRM_MODE_FLAG_PVSYNC
	.comm	_DP_SYNC_VS_HIGH,4,2            ## @DP_SYNC_VS_HIGH
	.comm	_DP_LINK_TRAIN_OFF,4,2          ## @DP_LINK_TRAIN_OFF
	.comm	_DP_PORT_WIDTH_1,4,2            ## @DP_PORT_WIDTH_1
	.comm	_DP_PORT_WIDTH_2,4,2            ## @DP_PORT_WIDTH_2
	.comm	_DP_PORT_WIDTH_4,4,2            ## @DP_PORT_WIDTH_4
	.comm	_DP_AUDIO_OUTPUT_ENABLE,4,2     ## @DP_AUDIO_OUTPUT_ENABLE
	.comm	_DP_LINK_CONFIGURATION_SIZE,4,2 ## @DP_LINK_CONFIGURATION_SIZE
	.comm	_DP_DPCD_REV,8,3                ## @DP_DPCD_REV
	.comm	_DP_MAX_LANE_COUNT,8,3          ## @DP_MAX_LANE_COUNT
	.comm	_DP_ENHANCED_FRAME_CAP,4,2      ## @DP_ENHANCED_FRAME_CAP
	.comm	_DP_LANE_COUNT_ENHANCED_FRAME_EN,4,2 ## @DP_LANE_COUNT_ENHANCED_FRAME_EN
	.comm	_DP_ENHANCED_FRAMING,4,2        ## @DP_ENHANCED_FRAMING
	.comm	_DP_PIPEB_SELECT,4,2            ## @DP_PIPEB_SELECT
	.comm	_DP_PORT_EN,4,2                 ## @DP_PORT_EN
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"DP expected reg is %x\n"

	.comm	_PFIT_ENABLE,4,2                ## @PFIT_ENABLE
	.comm	_PFIT_PIPE_SHIFT,4,2            ## @PFIT_PIPE_SHIFT
	.comm	_PFIT_CONTROL,4,2               ## @PFIT_CONTROL
	.no_dead_strip	_cdv_intel_dp_mode_set
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cdv_intel_dp_mode_set
_cdv_intel_dp_mode_set:                 ; @cdv_intel_dp_mode_set
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x2
	mov	x21, x1
	mov	x19, x0
	bl	_to_gma_encoder
	mov	x22, x0
	ldr	x0, [x19, #8]
	bl	_to_gma_crtc
	mov	x19, x0
	ldr	x23, [x22]
Lloh0:
	adrp	x8, _DP_VOLTAGE_0_4@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DP_VOLTAGE_0_4@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _DP_PRE_EMPHASIS_0@GOTPAGE
Lloh4:
	ldr	x9, [x9, _DP_PRE_EMPHASIS_0@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	orr	w8, w9, w8
	ldr	w9, [x23, #4]
	orr	w8, w9, w8
	str	w8, [x23]
	ldr	w9, [x20]
Lloh6:
	adrp	x10, _DRM_MODE_FLAG_PHSYNC@GOTPAGE
Lloh7:
	ldr	x10, [x10, _DRM_MODE_FLAG_PHSYNC@GOTPAGEOFF]
Lloh8:
	ldr	w10, [x10]
	tst	w10, w9
	b.eq	LBB0_2
; %bb.1:
Lloh9:
	adrp	x10, _DP_SYNC_HS_HIGH@GOTPAGE
Lloh10:
	ldr	x10, [x10, _DP_SYNC_HS_HIGH@GOTPAGEOFF]
Lloh11:
	ldr	w10, [x10]
	orr	w8, w10, w8
	str	w8, [x23]
LBB0_2:
Lloh12:
	adrp	x10, _DRM_MODE_FLAG_PVSYNC@GOTPAGE
Lloh13:
	ldr	x10, [x10, _DRM_MODE_FLAG_PVSYNC@GOTPAGEOFF]
Lloh14:
	ldr	w10, [x10]
	tst	w10, w9
	b.eq	LBB0_4
; %bb.3:
Lloh15:
	adrp	x9, _DP_SYNC_VS_HIGH@GOTPAGE
Lloh16:
	ldr	x9, [x9, _DP_SYNC_VS_HIGH@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x23]
LBB0_4:
Lloh18:
	adrp	x9, _DP_LINK_TRAIN_OFF@GOTPAGE
Lloh19:
	ldr	x9, [x9, _DP_LINK_TRAIN_OFF@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x23]
	ldr	w9, [x23, #8]
	cmp	w9, #1
	b.eq	LBB0_8
; %bb.5:
	cmp	w9, #4
	b.eq	LBB0_9
; %bb.6:
	cmp	w9, #2
	b.ne	LBB0_11
; %bb.7:
Lloh21:
	adrp	x9, _DP_PORT_WIDTH_2@GOTPAGE
Lloh22:
	ldr	x9, [x9, _DP_PORT_WIDTH_2@GOTPAGEOFF]
	b	LBB0_10
LBB0_8:
Lloh23:
	adrp	x9, _DP_PORT_WIDTH_1@GOTPAGE
Lloh24:
	ldr	x9, [x9, _DP_PORT_WIDTH_1@GOTPAGEOFF]
	b	LBB0_10
LBB0_9:
Lloh25:
	adrp	x9, _DP_PORT_WIDTH_4@GOTPAGE
Lloh26:
	ldr	x9, [x9, _DP_PORT_WIDTH_4@GOTPAGEOFF]
LBB0_10:
	ldr	w9, [x9]
	orr	w8, w9, w8
	str	w8, [x23]
LBB0_11:
	ldr	x9, [x23, #48]
	cbz	x9, LBB0_13
; %bb.12:
Lloh27:
	adrp	x9, _DP_AUDIO_OUTPUT_ENABLE@GOTPAGE
Lloh28:
	ldr	x9, [x9, _DP_AUDIO_OUTPUT_ENABLE@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x23]
LBB0_13:
	ldr	x0, [x23, #16]
Lloh30:
	adrp	x8, _DP_LINK_CONFIGURATION_SIZE@GOTPAGE
Lloh31:
	ldr	x8, [x8, _DP_LINK_CONFIGURATION_SIZE@GOTPAGEOFF]
Lloh32:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_memset
	ldr	w9, [x23, #24]
	ldr	x8, [x23, #16]
	str	w9, [x8]
	ldr	w9, [x23, #8]
	str	w9, [x8, #4]
	ldr	x10, [x23, #32]
Lloh33:
	adrp	x11, _DP_DPCD_REV@GOTPAGE
Lloh34:
	ldr	x11, [x11, _DP_DPCD_REV@GOTPAGEOFF]
Lloh35:
	ldr	x11, [x11]
	ldr	w11, [x10, x11, lsl #2]
	cmp	w11, #17
	b.lt	LBB0_16
; %bb.14:
Lloh36:
	adrp	x11, _DP_MAX_LANE_COUNT@GOTPAGE
Lloh37:
	ldr	x11, [x11, _DP_MAX_LANE_COUNT@GOTPAGEOFF]
Lloh38:
	ldr	x11, [x11]
	ldr	w10, [x10, x11, lsl #2]
Lloh39:
	adrp	x11, _DP_ENHANCED_FRAME_CAP@GOTPAGE
Lloh40:
	ldr	x11, [x11, _DP_ENHANCED_FRAME_CAP@GOTPAGEOFF]
Lloh41:
	ldr	w11, [x11]
	tst	w11, w10
	b.eq	LBB0_16
; %bb.15:
Lloh42:
	adrp	x10, _DP_LANE_COUNT_ENHANCED_FRAME_EN@GOTPAGE
Lloh43:
	ldr	x10, [x10, _DP_LANE_COUNT_ENHANCED_FRAME_EN@GOTPAGEOFF]
Lloh44:
	ldr	w10, [x10]
	orr	w9, w10, w9
	str	w9, [x8, #4]
Lloh45:
	adrp	x8, _DP_ENHANCED_FRAMING@GOTPAGE
Lloh46:
	ldr	x8, [x8, _DP_ENHANCED_FRAMING@GOTPAGEOFF]
Lloh47:
	ldr	w8, [x8]
	ldr	w9, [x23]
	orr	w8, w9, w8
	str	w8, [x23]
LBB0_16:
	ldr	w8, [x19]
	cmp	w8, #1
	b.ne	LBB0_18
; %bb.17:
Lloh48:
	adrp	x8, _DP_PIPEB_SELECT@GOTPAGE
Lloh49:
	ldr	x8, [x8, _DP_PIPEB_SELECT@GOTPAGEOFF]
Lloh50:
	ldr	w8, [x8]
	ldr	w9, [x23]
	orr	w8, w9, w8
	str	w8, [x23]
	b	LBB0_19
LBB0_18:
	ldr	w8, [x23]
LBB0_19:
	ldr	w0, [x23, #40]
Lloh51:
	adrp	x9, _DP_PORT_EN@GOTPAGE
Lloh52:
	ldr	x9, [x9, _DP_PORT_EN@GOTPAGEOFF]
Lloh53:
	ldr	w9, [x9]
	orr	w1, w9, w8
	bl	_REG_WRITE
	ldr	w1, [x23]
Lloh54:
	adrp	x0, l_.str@PAGE
Lloh55:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_KMS
	mov	x0, x22
	bl	_is_edp
	cbz	x0, LBB0_25
; %bb.20:
	mov	x0, x22
	bl	_cdv_intel_edp_panel_on
	ldr	x8, [x21, #8]
	ldr	x9, [x20, #8]
	cmp	x8, x9
	b.ne	LBB0_23
; %bb.21:
	ldr	x8, [x21, #16]
	ldr	x9, [x20, #16]
	cmp	x8, x9
	b.ne	LBB0_23
; %bb.22:
	mov	w8, #0
	b	LBB0_24
LBB0_23:
Lloh56:
	adrp	x8, _PFIT_ENABLE@GOTPAGE
Lloh57:
	ldr	x8, [x8, _PFIT_ENABLE@GOTPAGEOFF]
Lloh58:
	ldr	w8, [x8]
LBB0_24:
	ldr	w9, [x19]
Lloh59:
	adrp	x10, _PFIT_PIPE_SHIFT@GOTPAGE
Lloh60:
	ldr	x10, [x10, _PFIT_PIPE_SHIFT@GOTPAGEOFF]
Lloh61:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w1, w9, w8
Lloh62:
	adrp	x8, _PFIT_CONTROL@GOTPAGE
Lloh63:
	ldr	x8, [x8, _PFIT_CONTROL@GOTPAGEOFF]
Lloh64:
	ldr	w0, [x8]
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_REG_WRITE
LBB0_25:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpAdd	Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.cfi_endproc
                                        ; -- End function
	.comm	_DP_VOLTAGE_0_4,4,2             ; @DP_VOLTAGE_0_4
	.comm	_DP_PRE_EMPHASIS_0,4,2          ; @DP_PRE_EMPHASIS_0
	.comm	_DRM_MODE_FLAG_PHSYNC,4,2       ; @DRM_MODE_FLAG_PHSYNC
	.comm	_DP_SYNC_HS_HIGH,4,2            ; @DP_SYNC_HS_HIGH
	.comm	_DRM_MODE_FLAG_PVSYNC,4,2       ; @DRM_MODE_FLAG_PVSYNC
	.comm	_DP_SYNC_VS_HIGH,4,2            ; @DP_SYNC_VS_HIGH
	.comm	_DP_LINK_TRAIN_OFF,4,2          ; @DP_LINK_TRAIN_OFF
	.comm	_DP_PORT_WIDTH_1,4,2            ; @DP_PORT_WIDTH_1
	.comm	_DP_PORT_WIDTH_2,4,2            ; @DP_PORT_WIDTH_2
	.comm	_DP_PORT_WIDTH_4,4,2            ; @DP_PORT_WIDTH_4
	.comm	_DP_AUDIO_OUTPUT_ENABLE,4,2     ; @DP_AUDIO_OUTPUT_ENABLE
	.comm	_DP_LINK_CONFIGURATION_SIZE,4,2 ; @DP_LINK_CONFIGURATION_SIZE
	.comm	_DP_DPCD_REV,8,3                ; @DP_DPCD_REV
	.comm	_DP_MAX_LANE_COUNT,8,3          ; @DP_MAX_LANE_COUNT
	.comm	_DP_ENHANCED_FRAME_CAP,4,2      ; @DP_ENHANCED_FRAME_CAP
	.comm	_DP_LANE_COUNT_ENHANCED_FRAME_EN,4,2 ; @DP_LANE_COUNT_ENHANCED_FRAME_EN
	.comm	_DP_ENHANCED_FRAMING,4,2        ; @DP_ENHANCED_FRAMING
	.comm	_DP_PIPEB_SELECT,4,2            ; @DP_PIPEB_SELECT
	.comm	_DP_PORT_EN,4,2                 ; @DP_PORT_EN
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"DP expected reg is %x\n"

	.comm	_PFIT_ENABLE,4,2                ; @PFIT_ENABLE
	.comm	_PFIT_PIPE_SHIFT,4,2            ; @PFIT_PIPE_SHIFT
	.comm	_PFIT_CONTROL,4,2               ; @PFIT_CONTROL
	.no_dead_strip	_cdv_intel_dp_mode_set
.subsections_via_symbols
