	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_vm_flush                ## -- Begin function amdgpu_vm_flush
	.p2align	4, 0x90
_amdgpu_vm_flush:                       ## @amdgpu_vm_flush
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$104, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, -44(%rbp)                 ## 4-byte Spill
	movq	(%rdi), %rax
	movq	8(%rdi), %rcx
	movl	(%rax), %edx
	movq	%rcx, -104(%rbp)                ## 8-byte Spill
	movq	16(%rcx), %r8
	shlq	$4, %rdx
	movq	8(%r8,%rdx), %r13
	movq	(%rsi), %rcx
	leaq	(%rcx,%rcx,4), %rbx
	shlq	$4, %rbx
	leaq	(%rbx,%r13), %rcx
	cmpq	$0, 24(%rax)
	movq	%r8, -128(%rbp)                 ## 8-byte Spill
	movq	%rdx, -120(%rbp)                ## 8-byte Spill
	je	LBB0_1
## %bb.2:
	movq	(%rcx), %rax
	movl	$1, %r14d
	cmpq	8(%rsi), %rax
	jne	LBB0_8
## %bb.3:
	movq	8(%r13,%rbx), %rax
	cmpq	16(%rsi), %rax
	jne	LBB0_8
## %bb.4:
	movq	16(%r13,%rbx), %rax
	cmpq	24(%rsi), %rax
	jne	LBB0_8
## %bb.5:
	movq	24(%r13,%rbx), %rax
	cmpq	32(%rsi), %rax
	jne	LBB0_8
## %bb.6:
	movq	32(%r13,%rbx), %rax
	cmpq	40(%rsi), %rax
	jne	LBB0_8
## %bb.7:
	movq	40(%r13,%rbx), %rax
	xorl	%r14d, %r14d
	cmpq	48(%rsi), %rax
	setne	%r14b
	jmp	LBB0_8
LBB0_1:
	xorl	%r14d, %r14d
LBB0_8:
	movq	%rdi, -56(%rbp)                 ## 8-byte Spill
	movl	56(%rsi), %r15d
	movq	48(%r13,%rbx), %rax
	movl	$1, %r12d
	movq	%rsi, -64(%rbp)                 ## 8-byte Spill
	cmpq	64(%rsi), %rax
	jne	LBB0_11
## %bb.9:
	movq	56(%r13,%rbx), %rdi
	movl	$1, %r12d
	testq	%rdi, %rdi
	je	LBB0_11
## %bb.10:
	movq	%rcx, %r12
	callq	_dma_fence_is_signaled
	movq	%r12, %rcx
	xorl	%r12d, %r12d
	testl	%eax, %eax
	sete	%r12b
LBB0_11:
	movq	%rbx, -88(%rbp)                 ## 8-byte Spill
	movq	%r13, -96(%rbp)                 ## 8-byte Spill
	movq	$0, -72(%rbp)
	movq	-104(%rbp), %rdi                ## 8-byte Reload
	movq	%rcx, -136(%rbp)                ## 8-byte Spill
	movq	%rcx, %rsi
	callq	_amdgpu_vmid_had_gpu_reset
	testq	%rax, %rax
	movl	%r14d, %ebx
	movl	$1, %eax
	cmovnel	%eax, %ebx
	cmovnel	%eax, %r15d
	cmovnel	%eax, %r12d
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rax
	xorl	%ecx, %ecx
	cmpq	$0, 24(%rax)
	setne	%dl
	xorl	%r13d, %r13d
	cmpl	$0, 48(%rax)
	movl	$0, %r14d
	je	LBB0_13
## %bb.12:
	movq	-64(%rbp), %rsi                 ## 8-byte Reload
	movq	72(%rsi), %rsi
	movq	_AMDGPU_BO_INVALID_OFFSET@GOTPCREL(%rip), %rdi
	xorl	%r14d, %r14d
	cmpq	(%rdi), %rsi
	setne	%r14b
LBB0_13:
	movb	%dl, %cl
	movq	-104(%rbp), %rdx                ## 8-byte Reload
	movq	8(%rdx), %rdx
	cmpq	$0, (%rdx)
	je	LBB0_15
## %bb.14:
	xorl	%r13d, %r13d
	cmpq	$0, 40(%rax)
	setne	%r13b
LBB0_15:
	andl	%ecx, %ebx
	andl	%r15d, %r14d
	cmpl	$0, -44(%rbp)                   ## 4-byte Folded Reload
	jne	LBB0_18
## %bb.16:
	testl	%r14d, %r14d
	jne	LBB0_18
## %bb.17:
	xorl	%r15d, %r15d
	testl	%ebx, %ebx
	je	LBB0_40
LBB0_18:
	cmpq	$0, 32(%rax)
	movl	%ebx, -108(%rbp)                ## 4-byte Spill
	je	LBB0_19
## %bb.20:
	movq	-56(%rbp), %r15                 ## 8-byte Reload
	movq	%r15, %rdi
	callq	_amdgpu_ring_init_cond_exec
	movl	%eax, -76(%rbp)                 ## 4-byte Spill
	cmpl	$0, -44(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_23
LBB0_22:
	movq	%r15, %rdi
	callq	_amdgpu_ring_emit_pipeline_sync
LBB0_23:
	andl	%r12d, %r13d
	testl	%r14d, %r14d
	je	LBB0_27
## %bb.24:
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	movq	(%rbx), %rsi
	movq	72(%rbx), %rdx
	movq	%r15, %rdi
	callq	_trace_amdgpu_vm_flush
	movq	(%rbx), %rsi
	movq	72(%rbx), %rdx
	movq	%r15, %rdi
	callq	_amdgpu_ring_emit_vm_flush
	testl	%r13d, %r13d
	jne	LBB0_28
## %bb.25:
	leaq	-72(%rbp), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_amdgpu_fence_emit
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	LBB0_40
## %bb.26:
	movb	$1, %al
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	-56(%rbp), %r15                 ## 8-byte Reload
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	jmp	LBB0_31
LBB0_19:
	movl	$0, -76(%rbp)                   ## 4-byte Folded Spill
	movq	-56(%rbp), %r15                 ## 8-byte Reload
	cmpl	$0, -44(%rbp)                   ## 4-byte Folded Reload
	jne	LBB0_22
	jmp	LBB0_23
LBB0_27:
	testl	%r13d, %r13d
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	je	LBB0_33
LBB0_28:
	movq	(%rbx), %rsi
	movq	64(%rbx), %rdx
	movq	%r15, %rdi
	callq	_amdgpu_gmc_emit_pasid_mapping
	leaq	-72(%rbp), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_amdgpu_fence_emit
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	LBB0_40
## %bb.29:
	testl	%r14d, %r14d
	movq	-56(%rbp), %r15                 ## 8-byte Reload
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	je	LBB0_32
## %bb.30:
	movl	$0, -44(%rbp)                   ## 4-byte Folded Spill
LBB0_31:
	movq	-96(%rbp), %r12                 ## 8-byte Reload
	movq	-88(%rbp), %r13                 ## 8-byte Reload
	movq	-128(%rbp), %r14                ## 8-byte Reload
	addq	-120(%rbp), %r14                ## 8-byte Folded Reload
	movq	%r14, %rdi
	callq	_mutex_lock
	movq	72(%r12,%r13), %rdi
	callq	_dma_fence_put
	movq	-72(%rbp), %rdi
	callq	_dma_fence_get
	movq	%rax, 72(%r12,%r13)
	movq	-104(%rbp), %rdi                ## 8-byte Reload
	callq	_atomic_read
	movl	%eax, 64(%r12,%r13)
	movq	%r14, %rdi
	callq	_mutex_unlock
	cmpb	$0, -44(%rbp)                   ## 1-byte Folded Reload
	jne	LBB0_33
LBB0_32:
	movq	-96(%rbp), %r14                 ## 8-byte Reload
	movq	-88(%rbp), %r12                 ## 8-byte Reload
	leaq	(%r14,%r12), %rax
	addq	$48, %rax
	movq	64(%rbx), %rcx
	movq	%rcx, (%rax)
	movq	56(%r14,%r12), %rdi
	callq	_dma_fence_put
	movq	-72(%rbp), %rdi
	callq	_dma_fence_get
	movq	%rax, 56(%r14,%r12)
LBB0_33:
	movq	-72(%rbp), %rdi
	callq	_dma_fence_put
	movq	(%r15), %rax
	cmpq	$0, 24(%rax)
	je	LBB0_36
## %bb.34:
	cmpl	$0, -108(%rbp)                  ## 4-byte Folded Reload
	je	LBB0_36
## %bb.35:
	movq	8(%rbx), %rdx
	movq	-136(%rbp), %rax                ## 8-byte Reload
	movq	%rdx, (%rax)
	movq	16(%rbx), %rcx
	movq	-96(%rbp), %rsi                 ## 8-byte Reload
	movq	-88(%rbp), %rdi                 ## 8-byte Reload
	movq	%rcx, 8(%rsi,%rdi)
	movq	24(%rbx), %r8
	movq	%r8, 16(%rsi,%rdi)
	movq	32(%rbx), %r9
	movq	%r9, 24(%rsi,%rdi)
	movq	40(%rbx), %r10
	movq	%r10, 32(%rsi,%rdi)
	movq	48(%rbx), %rax
	movq	%rax, 40(%rsi,%rdi)
	movq	(%rbx), %rsi
	movq	%r15, %rdi
	pushq	%rax
	pushq	%r10
	callq	_amdgpu_ring_emit_gds_switch
	addq	$16, %rsp
	movq	(%r15), %rax
LBB0_36:
	cmpq	$0, 16(%rax)
	je	LBB0_38
## %bb.37:
	movq	%r15, %rdi
	movl	-76(%rbp), %esi                 ## 4-byte Reload
	callq	_amdgpu_ring_patch_cond_exec
	movq	(%r15), %rax
LBB0_38:
	xorl	%r15d, %r15d
	cmpq	$0, 8(%rax)
	je	LBB0_40
## %bb.39:
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	callq	_amdgpu_ring_emit_switch_buffer
	movq	%rbx, %rdi
	callq	_amdgpu_ring_emit_switch_buffer
LBB0_40:
	movl	%r15d, %eax
	addq	$104, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_BO_INVALID_OFFSET,8,3   ## @AMDGPU_BO_INVALID_OFFSET
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_vm_flush                ; -- Begin function amdgpu_vm_flush
	.p2align	2
_amdgpu_vm_flush:                       ; @amdgpu_vm_flush
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #144
	.cfi_def_cfa_offset 144
	stp	x28, x27, [sp, #48]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #64]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #80]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #96]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #112]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #128]            ; 16-byte Folded Spill
	add	x29, sp, #128
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x23, x2
	mov	x20, x1
	mov	x19, x0
	ldp	x8, x22, [x0]
	ldr	w10, [x8]
	ldr	x11, [x22, #16]
	add	x9, x11, x10, lsl #4
	ldr	x25, [x9, #8]
	ldr	x26, [x1]
	mov	w9, #80
	madd	x1, x26, x9, x25
	ldr	x8, [x8, #24]
	stp	x11, x10, [sp, #16]             ; 16-byte Folded Spill
	cbz	x8, LBB0_8
; %bb.1:
	ldr	x8, [x1]
	ldr	x9, [x20, #8]
	cmp	x8, x9
	b.ne	LBB0_7
; %bb.2:
	mov	w8, #80
	madd	x8, x26, x8, x25
	ldr	x8, [x8, #8]
	ldr	x9, [x20, #16]
	cmp	x8, x9
	b.ne	LBB0_7
; %bb.3:
	mov	w8, #80
	madd	x8, x26, x8, x25
	ldr	x8, [x8, #16]
	ldr	x9, [x20, #24]
	cmp	x8, x9
	b.ne	LBB0_7
; %bb.4:
	mov	w8, #80
	madd	x8, x26, x8, x25
	ldr	x8, [x8, #24]
	ldr	x9, [x20, #32]
	cmp	x8, x9
	b.ne	LBB0_7
; %bb.5:
	mov	w8, #80
	madd	x8, x26, x8, x25
	ldr	x8, [x8, #32]
	ldr	x9, [x20, #40]
	cmp	x8, x9
	b.ne	LBB0_7
; %bb.6:
	mov	w8, #80
	madd	x8, x26, x8, x25
	ldr	x8, [x8, #40]
	ldr	x9, [x20, #48]
	cmp	x8, x9
	cset	w27, ne
	b	LBB0_9
LBB0_7:
	mov	w27, #1
	b	LBB0_9
LBB0_8:
	mov	w27, #0
LBB0_9:
	ldr	w21, [x20, #56]
	mov	w8, #80
	madd	x24, x26, x8, x25
	ldr	x8, [x24, #48]!
	ldr	x9, [x20, #64]
	cmp	x8, x9
	b.ne	LBB0_12
; %bb.10:
	mov	w8, #80
	madd	x8, x26, x8, x25
	ldr	x0, [x8, #56]
	cbz	x0, LBB0_12
; %bb.11:
	mov	x28, x1
	bl	_dma_fence_is_signaled
	mov	x1, x28
	cmp	w0, #0
	cset	w28, eq
	b	LBB0_13
LBB0_12:
	mov	w28, #1
LBB0_13:
	stp	x1, xzr, [sp, #32]              ; 8-byte Folded Spill
	mov	x0, x22
	bl	_amdgpu_vmid_had_gpu_reset
	cmp	x0, #0
	csinc	w9, w27, wzr, eq
	csinc	w10, w21, wzr, eq
	csinc	w21, w28, wzr, eq
	ldr	x8, [x19]
	ldr	x11, [x8, #24]
	cmp	x11, #0
	cset	w11, ne
	ldr	w12, [x8, #48]
	cbz	w12, LBB0_15
; %bb.14:
	ldr	x12, [x20, #72]
Lloh0:
	adrp	x13, _AMDGPU_BO_INVALID_OFFSET@GOTPAGE
Lloh1:
	ldr	x13, [x13, _AMDGPU_BO_INVALID_OFFSET@GOTPAGEOFF]
Lloh2:
	ldr	x13, [x13]
	cmp	x12, x13
	cset	w12, ne
LBB0_15:
	ldr	x13, [x22, #8]
	ldr	x13, [x13]
	cbz	x13, LBB0_17
; %bb.16:
	ldr	x13, [x8, #40]
	cmp	x13, #0
	cset	w27, ne
	b	LBB0_18
LBB0_17:
	mov	w27, #0
LBB0_18:
	and	w9, w9, w11
	and	w28, w12, w10
	cbnz	w23, LBB0_20
; %bb.19:
	cmp	w28, #0
	ccmp	w9, #0, #0, eq
	b.eq	LBB0_41
LBB0_20:
	ldr	x8, [x8, #32]
	str	w9, [sp, #12]                   ; 4-byte Folded Spill
	cbz	x8, LBB0_27
; %bb.21:
	mov	x0, x19
	bl	_amdgpu_ring_init_cond_exec
	str	w0, [sp, #8]                    ; 4-byte Folded Spill
	cbz	w23, LBB0_23
LBB0_22:
	mov	x0, x19
	bl	_amdgpu_ring_emit_pipeline_sync
LBB0_23:
	and	w21, w27, w21
	cbz	w28, LBB0_28
; %bb.24:
	ldr	x1, [x20]
	ldr	x2, [x20, #72]
	mov	x0, x19
	bl	_trace_amdgpu_vm_flush
	ldr	x1, [x20]
	ldr	x2, [x20, #72]
	mov	x0, x19
	bl	_amdgpu_ring_emit_vm_flush
	cbnz	w21, LBB0_29
; %bb.25:
	add	x1, sp, #40
	mov	x0, x19
	mov	w2, #0
	bl	_amdgpu_fence_emit
	cbnz	w0, LBB0_42
; %bb.26:
	mov	w21, #1
	b	LBB0_32
LBB0_27:
	str	wzr, [sp, #8]                   ; 4-byte Folded Spill
	cbnz	w23, LBB0_22
	b	LBB0_23
LBB0_28:
	cbz	w21, LBB0_34
LBB0_29:
	ldr	x1, [x20]
	ldr	x2, [x20, #64]
	mov	x0, x19
	bl	_amdgpu_gmc_emit_pasid_mapping
	add	x1, sp, #40
	mov	x0, x19
	mov	w2, #0
	bl	_amdgpu_fence_emit
	cbnz	w0, LBB0_42
; %bb.30:
	cbz	w28, LBB0_33
; %bb.31:
	mov	w21, #0
LBB0_32:
	ldp	x9, x8, [sp, #16]               ; 16-byte Folded Reload
	add	x23, x9, x8, lsl #4
	mov	x0, x23
	bl	_mutex_lock
	mov	w8, #80
	madd	x27, x26, x8, x25
	ldr	x0, [x27, #72]
	bl	_dma_fence_put
	ldr	x0, [sp, #40]
	bl	_dma_fence_get
	str	x0, [x27, #72]
	mov	x0, x22
	bl	_atomic_read
	str	w0, [x27, #64]
	mov	x0, x23
	bl	_mutex_unlock
	tbnz	w21, #0, LBB0_34
LBB0_33:
	ldr	x8, [x20, #64]
	str	x8, [x24]
	mov	w8, #80
	madd	x21, x26, x8, x25
	ldr	x0, [x21, #56]
	bl	_dma_fence_put
	ldr	x0, [sp, #40]
	bl	_dma_fence_get
	str	x0, [x21, #56]
LBB0_34:
	ldr	x0, [sp, #40]
	bl	_dma_fence_put
	ldr	x8, [x19]
	ldr	x9, [x8, #24]
	cbz	x9, LBB0_37
; %bb.35:
	ldr	w9, [sp, #12]                   ; 4-byte Folded Reload
	cbz	w9, LBB0_37
; %bb.36:
	ldp	x1, x2, [x20]
	ldr	x8, [sp, #32]                   ; 8-byte Folded Reload
	str	x2, [x8]
	mov	w8, #80
	madd	x8, x26, x8, x25
	ldp	x3, x4, [x20, #16]
	stp	x3, x4, [x8, #8]
	ldp	x5, x6, [x20, #32]
	stp	x5, x6, [x8, #24]
	ldr	x7, [x20, #48]
	str	x7, [x8, #40]
	mov	x0, x19
	bl	_amdgpu_ring_emit_gds_switch
	ldr	x8, [x19]
LBB0_37:
	ldr	x9, [x8, #16]
	cbz	x9, LBB0_39
; %bb.38:
	mov	x0, x19
	ldr	w1, [sp, #8]                    ; 4-byte Folded Reload
	bl	_amdgpu_ring_patch_cond_exec
	ldr	x8, [x19]
LBB0_39:
	ldr	x8, [x8, #8]
	cbz	x8, LBB0_41
; %bb.40:
	mov	x0, x19
	bl	_amdgpu_ring_emit_switch_buffer
	mov	x0, x19
	bl	_amdgpu_ring_emit_switch_buffer
LBB0_41:
	mov	w0, #0
LBB0_42:
	ldp	x29, x30, [sp, #128]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #112]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #96]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #80]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #64]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #144
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_BO_INVALID_OFFSET,8,3   ; @AMDGPU_BO_INVALID_OFFSET
.subsections_via_symbols
