	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function soc15_update_hdp_light_sleep
_soc15_update_hdp_light_sleep:          ## @soc15_update_hdp_light_sleep
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %rbx
	movq	(%rdi), %rax
	movq	_CHIP_VEGA20@GOTPCREL(%rip), %rcx
	movq	_HDP@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	cmpq	(%rcx), %rax
	je	LBB0_2
## %bb.1:
	movq	_CHIP_ARCTURUS@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_2
## %bb.6:
	movq	_mmHDP_MEM_POWER_LS@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	callq	_RREG32
	testl	%r14d, %r14d
	je	LBB0_9
## %bb.7:
	movq	_AMD_CG_SUPPORT_HDP_LS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, 8(%rbx)
	je	LBB0_9
## %bb.8:
	movq	_HDP_MEM_POWER_LS__LS_ENABLE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	%eax, %ebx
	cmpl	%ebx, %eax
	jne	LBB0_13
	jmp	LBB0_12
LBB0_2:
	movq	_mmHDP_MEM_POWER_CTRL@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	callq	_RREG32
	testl	%r14d, %r14d
	je	LBB0_5
## %bb.3:
	movq	_AMD_CG_SUPPORT_HDP_LS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, 8(%rbx)
	je	LBB0_5
## %bb.4:
	movq	_HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK@GOTPCREL(%rip), %rcx
	movq	_HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK@GOTPCREL(%rip), %rdx
	movq	_HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK@GOTPCREL(%rip), %rsi
	movq	_HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK@GOTPCREL(%rip), %rdi
	movl	(%rcx), %ebx
	orl	%eax, %ebx
	orl	(%rdx), %ebx
	orl	(%rsi), %ebx
	orl	(%rdi), %ebx
	cmpl	%ebx, %eax
	je	LBB0_12
LBB0_13:
	movl	(%r15), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	%ebx, %esi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
LBB0_9:
	movq	_HDP_MEM_POWER_LS__LS_ENABLE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	jmp	LBB0_10
LBB0_5:
	movq	_HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK@GOTPCREL(%rip), %rcx
	movq	_HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	movq	_HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
LBB0_10:
	notl	%ebx
	andl	%eax, %ebx
	cmpl	%ebx, %eax
	jne	LBB0_13
LBB0_12:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CHIP_VEGA20,8,3                ## @CHIP_VEGA20
	.comm	_CHIP_ARCTURUS,8,3              ## @CHIP_ARCTURUS
	.comm	_HDP,4,2                        ## @HDP
	.comm	_mmHDP_MEM_POWER_CTRL,4,2       ## @mmHDP_MEM_POWER_CTRL
	.comm	_AMD_CG_SUPPORT_HDP_LS,4,2      ## @AMD_CG_SUPPORT_HDP_LS
	.comm	_HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK,4,2 ## @HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK
	.comm	_HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK,4,2 ## @HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK
	.comm	_HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK,4,2 ## @HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK
	.comm	_HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK,4,2 ## @HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK
	.comm	_mmHDP_MEM_POWER_LS,4,2         ## @mmHDP_MEM_POWER_LS
	.comm	_HDP_MEM_POWER_LS__LS_ENABLE_MASK,4,2 ## @HDP_MEM_POWER_LS__LS_ENABLE_MASK
	.no_dead_strip	_soc15_update_hdp_light_sleep
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function soc15_update_hdp_light_sleep
_soc15_update_hdp_light_sleep:          ; @soc15_update_hdp_light_sleep
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	mov	x19, x0
	ldr	x8, [x0]
Lloh0:
	adrp	x9, _CHIP_VEGA20@GOTPAGE
Lloh1:
	ldr	x9, [x9, _CHIP_VEGA20@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
Lloh3:
	adrp	x10, _CHIP_ARCTURUS@GOTPAGE
Lloh4:
	ldr	x10, [x10, _CHIP_ARCTURUS@GOTPAGEOFF]
Lloh5:
	ldr	x10, [x10]
Lloh6:
	adrp	x21, _HDP@GOTPAGE
Lloh7:
	ldr	x21, [x21, _HDP@GOTPAGEOFF]
	ldr	w0, [x21]
	cmp	x8, x9
	ccmp	x8, x10, #4, ne
	b.ne	LBB0_4
; %bb.1:
Lloh8:
	adrp	x8, _mmHDP_MEM_POWER_CTRL@GOTPAGE
Lloh9:
	ldr	x8, [x8, _mmHDP_MEM_POWER_CTRL@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	bl	_RREG32
	cbz	w20, LBB0_7
; %bb.2:
	ldr	w8, [x19, #8]
Lloh11:
	adrp	x9, _AMD_CG_SUPPORT_HDP_LS@GOTPAGE
Lloh12:
	ldr	x9, [x9, _AMD_CG_SUPPORT_HDP_LS@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_7
; %bb.3:
Lloh14:
	adrp	x8, _HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK@GOTPAGE
Lloh15:
	ldr	x8, [x8, _HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK@GOTPAGEOFF]
Lloh16:
	adrp	x9, _HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK@GOTPAGE
Lloh17:
	ldr	x9, [x9, _HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
Lloh19:
	ldr	w9, [x9]
Lloh20:
	adrp	x10, _HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK@GOTPAGE
Lloh21:
	ldr	x10, [x10, _HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK@GOTPAGEOFF]
Lloh22:
	adrp	x11, _HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK@GOTPAGE
Lloh23:
	ldr	x11, [x11, _HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK@GOTPAGEOFF]
Lloh24:
	ldr	w10, [x10]
Lloh25:
	ldr	w11, [x11]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w19, w8, w11
	cmp	w0, w19
	b.ne	LBB0_8
	b	LBB0_10
LBB0_4:
Lloh26:
	adrp	x8, _mmHDP_MEM_POWER_LS@GOTPAGE
Lloh27:
	ldr	x8, [x8, _mmHDP_MEM_POWER_LS@GOTPAGEOFF]
Lloh28:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	bl	_RREG32
	cbz	w20, LBB0_9
; %bb.5:
	ldr	w8, [x19, #8]
Lloh29:
	adrp	x9, _AMD_CG_SUPPORT_HDP_LS@GOTPAGE
Lloh30:
	ldr	x9, [x9, _AMD_CG_SUPPORT_HDP_LS@GOTPAGEOFF]
Lloh31:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_9
; %bb.6:
Lloh32:
	adrp	x8, _HDP_MEM_POWER_LS__LS_ENABLE_MASK@GOTPAGE
Lloh33:
	ldr	x8, [x8, _HDP_MEM_POWER_LS__LS_ENABLE_MASK@GOTPAGEOFF]
Lloh34:
	ldr	w8, [x8]
	orr	w19, w8, w0
	cmp	w0, w19
	b.eq	LBB0_10
	b	LBB0_11
LBB0_7:
Lloh35:
	adrp	x8, _HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK@GOTPAGE
Lloh36:
	ldr	x8, [x8, _HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK@GOTPAGEOFF]
Lloh37:
	adrp	x9, _HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK@GOTPAGE
Lloh38:
	ldr	x9, [x9, _HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
Lloh40:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh41:
	adrp	x9, _HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK@GOTPAGE
Lloh42:
	ldr	x9, [x9, _HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh44:
	adrp	x9, _HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK@GOTPAGE
Lloh45:
	ldr	x9, [x9, _HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w19, w0, w8
	cmp	w0, w19
	b.eq	LBB0_10
LBB0_8:
Lloh47:
	adrp	x8, _mmHDP_MEM_POWER_CTRL@GOTPAGE
Lloh48:
	ldr	x8, [x8, _mmHDP_MEM_POWER_CTRL@GOTPAGEOFF]
	b	LBB0_12
LBB0_9:
Lloh49:
	adrp	x8, _HDP_MEM_POWER_LS__LS_ENABLE_MASK@GOTPAGE
Lloh50:
	ldr	x8, [x8, _HDP_MEM_POWER_LS__LS_ENABLE_MASK@GOTPAGEOFF]
Lloh51:
	ldr	w8, [x8]
	bic	w19, w0, w8
	cmp	w0, w19
	b.ne	LBB0_11
LBB0_10:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_11:
Lloh52:
	adrp	x8, _mmHDP_MEM_POWER_LS@GOTPAGE
Lloh53:
	ldr	x8, [x8, _mmHDP_MEM_POWER_LS@GOTPAGEOFF]
LBB0_12:
	ldr	w0, [x21]
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x1, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh24
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh18
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh39
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh52, Lloh53
	.cfi_endproc
                                        ; -- End function
	.comm	_CHIP_VEGA20,8,3                ; @CHIP_VEGA20
	.comm	_CHIP_ARCTURUS,8,3              ; @CHIP_ARCTURUS
	.comm	_HDP,4,2                        ; @HDP
	.comm	_mmHDP_MEM_POWER_CTRL,4,2       ; @mmHDP_MEM_POWER_CTRL
	.comm	_AMD_CG_SUPPORT_HDP_LS,4,2      ; @AMD_CG_SUPPORT_HDP_LS
	.comm	_HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK,4,2 ; @HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK
	.comm	_HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK,4,2 ; @HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK
	.comm	_HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK,4,2 ; @HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK
	.comm	_HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK,4,2 ; @HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK
	.comm	_mmHDP_MEM_POWER_LS,4,2         ; @mmHDP_MEM_POWER_LS
	.comm	_HDP_MEM_POWER_LS__LS_ENABLE_MASK,4,2 ; @HDP_MEM_POWER_LS__LS_ENABLE_MASK
	.no_dead_strip	_soc15_update_hdp_light_sleep
.subsections_via_symbols
