	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ci_update_vce_dpm
_ci_update_vce_dpm:                     ## @ci_update_vce_dpm
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r12
	movq	%rsi, %rbx
	movq	%rdi, %r15
	callq	_ci_get_pi
	movq	%rax, %r14
	movq	(%rbx), %rax
	cmpq	%rax, (%r12)
	jne	LBB0_1
## %bb.5:
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_1:
	movq	_RADEON_CG_BLOCK_VCE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	%r15, %rdi
	testq	%rax, %rax
	je	LBB0_3
## %bb.2:
	xorl	%edx, %edx
	callq	_cik_update_cg
	movq	%r15, %rdi
	callq	_ci_get_vce_boot_level
	movl	%eax, (%r14)
	movq	_DPM_TABLE_475@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_RREG32_SMC
	movq	_VceBootLevel_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	(%r14), %edi
	callq	_VceBootLevel
	orl	%eax, %ebx
	movl	(%r12), %edi
	movl	%ebx, %esi
	callq	_WREG32_SMC
	movl	$1, %esi
	jmp	LBB0_4
LBB0_3:
	movl	$1, %edx
	callq	_cik_update_cg
	xorl	%esi, %esi
LBB0_4:
	movq	%r15, %rdi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_ci_enable_vce_dpm              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_CG_BLOCK_VCE,4,2        ## @RADEON_CG_BLOCK_VCE
	.comm	_DPM_TABLE_475,4,2              ## @DPM_TABLE_475
	.comm	_VceBootLevel_MASK,4,2          ## @VceBootLevel_MASK
	.no_dead_strip	_ci_update_vce_dpm
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ci_update_vce_dpm
_ci_update_vce_dpm:                     ; @ci_update_vce_dpm
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x21, x2
	mov	x22, x1
	mov	x19, x0
	bl	_ci_get_pi
	ldr	x9, [x21]
	ldr	x8, [x22]
	cmp	x9, x8
	b.ne	LBB0_2
; %bb.1:
	mov	w0, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_2:
Lloh0:
	adrp	x9, _RADEON_CG_BLOCK_VCE@GOTPAGE
Lloh1:
	ldr	x9, [x9, _RADEON_CG_BLOCK_VCE@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x9]
	cbz	x8, LBB0_4
; %bb.3:
	mov	x20, x0
	mov	x0, x19
	mov	w2, #0
	bl	_cik_update_cg
	mov	x0, x19
	bl	_ci_get_vce_boot_level
	str	w0, [x20]
Lloh3:
	adrp	x21, _DPM_TABLE_475@GOTPAGE
Lloh4:
	ldr	x21, [x21, _DPM_TABLE_475@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32_SMC
Lloh5:
	adrp	x8, _VceBootLevel_MASK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _VceBootLevel_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	bic	w22, w0, w8
	ldr	w0, [x20]
	bl	_VceBootLevel
	orr	w1, w0, w22
	ldr	w0, [x21]
	bl	_WREG32_SMC
	mov	w1, #1
	b	LBB0_5
LBB0_4:
	mov	x0, x19
	mov	w2, #1
	bl	_cik_update_cg
	mov	w1, #0
LBB0_5:
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_ci_enable_vce_dpm
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_CG_BLOCK_VCE,4,2        ; @RADEON_CG_BLOCK_VCE
	.comm	_DPM_TABLE_475,4,2              ; @DPM_TABLE_475
	.comm	_VceBootLevel_MASK,4,2          ; @VceBootLevel_MASK
	.no_dead_strip	_ci_update_vce_dpm
.subsections_via_symbols
