	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v10_0_init_microcode
_gfx_v10_0_init_microcode:              ## @gfx_v10_0_init_microcode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$72, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -48(%rbp)
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG
	leaq	-106(%rbp), %rdi
	xorl	%esi, %esi
	movl	$10, %edx
	callq	_memset
	movl	(%r15), %eax
	cmpl	$130, %eax
	je	LBB0_6
## %bb.1:
	cmpl	$129, %eax
	je	LBB0_7
## %bb.2:
	cmpl	$128, %eax
	jne	LBB0_8
## %bb.3:
	movq	208(%r15), %rax
	cmpl	$29504, (%rax)                  ## imm = 0x7340
	leaq	L_.str.2(%rip), %r14
	jne	LBB0_5
## %bb.4:
	cmpl	$0, 4(%rax)
	jne	LBB0_9
LBB0_5:
	leaq	L_.str.3(%rip), %rdx
	leaq	-106(%rbp), %rdi
	movl	$10, %esi
	xorl	%eax, %eax
	callq	_snprintf
	jmp	LBB0_9
LBB0_6:
	leaq	L_.str.1(%rip), %r14
	jmp	LBB0_9
LBB0_7:
	leaq	L_.str.4(%rip), %r14
	jmp	LBB0_9
LBB0_8:
	xorl	%eax, %eax
	callq	_BUG
                                        ## implicit-def: $r14
LBB0_9:
	leaq	L_.str.5(%rip), %rdx
	leaq	-96(%rbp), %r12
	leaq	-106(%rbp), %r8
	movq	%r12, %rdi
	movl	$40, %esi
	movq	%r14, %rcx
	xorl	%eax, %eax
	callq	_snprintf
	leaq	96(%r15), %rbx
	movl	176(%r15), %edx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	_request_firmware
	movl	%eax, %r13d
	testl	%eax, %eax
	jne	LBB0_16
## %bb.10:
	movq	(%rbx), %rdi
	callq	_amdgpu_ucode_validate
	movl	%eax, %r13d
	testl	%eax, %eax
	jne	LBB0_16
## %bb.11:
	movq	96(%r15), %rax
	movq	(%rax), %rbx
	movl	8(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 8(%r15)
	movl	(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 12(%r15)
	leaq	L_.str.6(%rip), %rdx
	leaq	-96(%rbp), %r12
	leaq	-106(%rbp), %r8
	movq	%r12, %rdi
	movl	$40, %esi
	movq	%r14, %rcx
	xorl	%eax, %eax
	callq	_snprintf
	leaq	88(%r15), %rbx
	movl	176(%r15), %edx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	_request_firmware
	movl	%eax, %r13d
	testl	%eax, %eax
	jne	LBB0_16
## %bb.12:
	movq	(%rbx), %rdi
	callq	_amdgpu_ucode_validate
	movl	%eax, %r13d
	testl	%eax, %eax
	jne	LBB0_16
## %bb.13:
	movq	88(%r15), %rax
	movq	(%rax), %rbx
	movl	8(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 16(%r15)
	movl	(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 20(%r15)
	leaq	L_.str.7(%rip), %rdx
	leaq	-96(%rbp), %r12
	leaq	-106(%rbp), %r8
	movq	%r12, %rdi
	movl	$40, %esi
	movq	%r14, %rcx
	xorl	%eax, %eax
	callq	_snprintf
	leaq	80(%r15), %rbx
	movl	176(%r15), %edx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	_request_firmware
	movl	%eax, %r13d
	testl	%eax, %eax
	jne	LBB0_16
## %bb.14:
	movq	(%rbx), %rdi
	callq	_amdgpu_ucode_validate
	movl	%eax, %r13d
	testl	%eax, %eax
	jne	LBB0_16
## %bb.15:
	movq	80(%r15), %rax
	movq	(%rax), %rbx
	movl	8(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 24(%r15)
	movl	(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 28(%r15)
	leaq	L_.str.8(%rip), %rdx
	leaq	-96(%rbp), %rbx
	movq	%rbx, %rdi
	movl	$40, %esi
	movq	%r14, %rcx
	xorl	%eax, %eax
	callq	_snprintf
	leaq	72(%r15), %r12
	movl	176(%r15), %edx
	movq	%r12, %rdi
	movq	%rbx, %rsi
	callq	_request_firmware
	movl	%eax, %r13d
	testl	%eax, %eax
	je	LBB0_19
LBB0_16:
	movl	176(%r15), %edi
	leaq	L_.str.11(%rip), %rsi
	leaq	-96(%rbp), %rdx
	callq	_dev_err
	movq	96(%r15), %rdi
	callq	_release_firmware
	movq	$0, 96(%r15)
	movq	88(%r15), %rdi
	callq	_release_firmware
	movq	$0, 88(%r15)
	movq	80(%r15), %rdi
	callq	_release_firmware
	movq	$0, 80(%r15)
	movq	72(%r15), %rdi
	callq	_release_firmware
	movq	$0, 72(%r15)
	movq	64(%r15), %rdi
	callq	_release_firmware
	movq	$0, 64(%r15)
	movq	56(%r15), %rdi
	callq	_release_firmware
	movq	$0, 56(%r15)
LBB0_17:
	movq	%r15, %rdi
	callq	_gfx_v10_0_check_gfxoff_flag
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	cmpq	-48(%rbp), %rax
	jne	LBB0_50
## %bb.18:
	movl	%r13d, %eax
	addq	$72, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_19:
	movq	(%r12), %rdi
	callq	_amdgpu_ucode_validate
	movq	(%r12), %rax
	movq	(%rax), %r13
	movl	56(%r13), %edi
	callq	_le16_to_cpu
	movl	%eax, %r12d
	movl	52(%r13), %edi
	callq	_le16_to_cpu
	cmpl	$2, %r12d
	jne	LBB0_22
## %bb.20:
	cmpl	$1, %eax
	jne	LBB0_22
## %bb.21:
	movl	$1, 104(%r15)
LBB0_22:
	movl	48(%r13), %edi
	callq	_le32_to_cpu
	movl	%eax, 32(%r15)
	movl	(%r13), %edi
	callq	_le32_to_cpu
	movl	%eax, 36(%r15)
	movl	4(%r13), %edi
	callq	_le32_to_cpu
	movl	%eax, 108(%r15)
	movl	8(%r13), %edi
	callq	_le32_to_cpu
	movl	%eax, 112(%r15)
	movl	12(%r13), %edi
	callq	_le32_to_cpu
	movl	%eax, 116(%r15)
	movl	16(%r13), %edi
	callq	_le32_to_cpu
	movl	%eax, 120(%r15)
	movl	20(%r13), %edi
	callq	_le32_to_cpu
	movl	%eax, 124(%r15)
	movl	24(%r13), %edi
	callq	_le32_to_cpu
	movl	%eax, 128(%r15)
	movl	28(%r13), %edi
	callq	_le32_to_cpu
	movl	%eax, 132(%r15)
	movl	32(%r13), %edi
	callq	_le32_to_cpu
	movl	%eax, 136(%r15)
	movl	36(%r13), %edi
	callq	_le32_to_cpu
	movl	%eax, 140(%r15)
	addl	136(%r15), %eax
	movq	_GFP_KERNEL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_kmalloc
	movq	%rax, 144(%r15)
	testq	%rax, %rax
	je	LBB0_25
## %bb.23:
	movl	40(%r13), %edi
	callq	_le32_to_cpu
	cmpl	$4, 32(%r13)
	jae	LBB0_27
## %bb.24:
	movq	144(%r15), %rcx
	xorl	%ebx, %ebx
	jmp	LBB0_29
LBB0_25:
	movq	_ENOMEM@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	testl	%r13d, %r13d
	je	LBB0_47
## %bb.26:
	negl	%r13d
	jmp	LBB0_16
LBB0_27:
	movslq	%eax, %r12
	addq	%r13, %r12
	xorl	%ebx, %ebx
LBB0_28:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r12,%rbx,4), %edi
	callq	_le32_to_cpu
	movq	144(%r15), %rcx
	movl	%eax, (%rcx,%rbx,4)
	incq	%rbx
	movl	32(%r13), %eax
	shrq	$2, %rax
	cmpq	%rax, %rbx
	jb	LBB0_28
LBB0_29:
	leaq	(%rcx,%rbx,4), %rax
	movq	%rax, 152(%r15)
	movl	44(%r13), %edi
	callq	_le32_to_cpu
	cmpl	$4, 36(%r13)
	jb	LBB0_32
## %bb.30:
	movslq	%eax, %r12
	addq	%r13, %r12
	xorl	%ebx, %ebx
LBB0_31:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r12,%rbx,4), %edi
	callq	_le32_to_cpu
	movq	152(%r15), %rcx
	movl	%eax, (%rcx,%rbx,4)
	incq	%rbx
	movl	36(%r13), %eax
	shrq	$2, %rax
	cmpq	%rax, %rbx
	jb	LBB0_31
LBB0_32:
	cmpl	$0, 104(%r15)
	je	LBB0_34
## %bb.33:
	movq	%r15, %rdi
	callq	_gfx_v10_0_init_rlc_ext_microcode
LBB0_34:
	leaq	L_.str.9(%rip), %rdx
	leaq	-96(%rbp), %r12
	leaq	-106(%rbp), %r8
	movq	%r12, %rdi
	movl	$40, %esi
	movq	%r14, %rcx
	xorl	%eax, %eax
	callq	_snprintf
	leaq	64(%r15), %rbx
	movl	176(%r15), %edx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	_request_firmware
	movl	%eax, %r13d
	testl	%eax, %eax
	jne	LBB0_16
## %bb.35:
	movq	(%rbx), %rdi
	callq	_amdgpu_ucode_validate
	movl	%eax, %r13d
	testl	%eax, %eax
	jne	LBB0_16
## %bb.36:
	movq	64(%r15), %rax
	movq	(%rax), %rbx
	movl	8(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 40(%r15)
	movl	(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 44(%r15)
	leaq	L_.str.10(%rip), %rdx
	leaq	-96(%rbp), %r12
	leaq	-106(%rbp), %r8
	movq	%r12, %rdi
	movl	$40, %esi
	movq	%r14, %rcx
	xorl	%eax, %eax
	callq	_snprintf
	leaq	56(%r15), %rbx
	movl	176(%r15), %edx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	_request_firmware
	testl	%eax, %eax
	je	LBB0_48
## %bb.37:
	movq	$0, (%rbx)
LBB0_38:
	movq	184(%r15), %rax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_46
## %bb.39:
	movq	200(%r15), %rax
	movq	_AMDGPU_UCODE_ID_CP_PFP@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	96(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movq	(%rcx), %rax
	movl	(%rax), %edi
	callq	_le32_to_cpu
	movq	_PAGE_SIZE@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movl	%eax, %edi
	callq	_ALIGN
	addl	%eax, 192(%r15)
	movq	200(%r15), %rax
	movq	_AMDGPU_UCODE_ID_CP_ME@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	88(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movq	(%rcx), %rax
	movl	(%rax), %edi
	callq	_le32_to_cpu
	movl	(%r14), %esi
	movl	%eax, %edi
	callq	_ALIGN
	addl	%eax, 192(%r15)
	movq	200(%r15), %rax
	movq	_AMDGPU_UCODE_ID_CP_CE@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	80(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movq	(%rcx), %rax
	movl	(%rax), %edi
	callq	_le32_to_cpu
	movl	(%r14), %esi
	movl	%eax, %edi
	callq	_ALIGN
	addl	%eax, 192(%r15)
	movq	200(%r15), %rax
	movq	_AMDGPU_UCODE_ID_RLC_G@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	72(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movq	(%rcx), %rax
	movl	(%rax), %edi
	callq	_le32_to_cpu
	movl	(%r14), %esi
	movl	%eax, %edi
	callq	_ALIGN
	addl	%eax, 192(%r15)
	cmpl	$0, 104(%r15)
	je	LBB0_44
## %bb.40:
	movl	160(%r15), %edi
	testl	%edi, %edi
	je	LBB0_44
## %bb.41:
	cmpl	$0, 164(%r15)
	je	LBB0_44
## %bb.42:
	cmpl	$0, 168(%r15)
	je	LBB0_44
## %bb.43:
	movq	200(%r15), %rax
	movq	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	72(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movl	(%r14), %esi
	callq	_ALIGN
	addl	%eax, 192(%r15)
	movq	200(%r15), %rax
	movq	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	72(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movl	164(%r15), %edi
	movl	(%r14), %esi
	callq	_ALIGN
	addl	%eax, 192(%r15)
	movq	200(%r15), %rax
	movq	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	72(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movl	168(%r15), %edi
	movl	(%r14), %esi
	callq	_ALIGN
	addl	%eax, 192(%r15)
LBB0_44:
	movq	200(%r15), %rax
	movq	_AMDGPU_UCODE_ID_CP_MEC1@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	64(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movq	(%rcx), %r12
	movl	(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, %ebx
	movl	4(%r12), %edi
	callq	_le32_to_cpu
	shll	$2, %eax
	subl	%eax, %ebx
	movl	(%r14), %esi
	movl	%ebx, %edi
	callq	_ALIGN
	addl	%eax, 192(%r15)
	movq	200(%r15), %rax
	movq	_AMDGPU_UCODE_ID_CP_MEC1_JT@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	64(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movl	4(%r12), %edi
	callq	_le32_to_cpu
                                        ## kill: def $eax killed $eax def $rax
	leal	(,%rax,4), %edi
	movl	(%r14), %esi
	callq	_ALIGN
	addl	%eax, 192(%r15)
	movq	56(%r15), %rax
	testq	%rax, %rax
	je	LBB0_46
## %bb.45:
	movq	200(%r15), %rcx
	movq	_AMDGPU_UCODE_ID_CP_MEC2@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdx
	movq	%rdx, %rsi
	shlq	$4, %rsi
	movq	%rdx, (%rcx,%rsi)
	movq	%rax, 8(%rcx,%rsi)
	movq	(%rax), %r12
	movl	(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, %ebx
	movl	4(%r12), %edi
	callq	_le32_to_cpu
	shll	$2, %eax
	subl	%eax, %ebx
	movl	(%r14), %esi
	movl	%ebx, %edi
	callq	_ALIGN
	addl	%eax, 192(%r15)
	movq	200(%r15), %rax
	movq	_AMDGPU_UCODE_ID_CP_MEC2_JT@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	56(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movl	4(%r12), %edi
	callq	_le32_to_cpu
                                        ## kill: def $eax killed $eax def $rax
	leal	(,%rax,4), %edi
	movl	(%r14), %esi
	callq	_ALIGN
	addl	%eax, 192(%r15)
LBB0_46:
	movq	%r15, %rdi
	callq	_gfx_v10_0_check_fw_write_wait
LBB0_47:
	xorl	%r13d, %r13d
	jmp	LBB0_17
LBB0_48:
	movq	(%rbx), %rdi
	callq	_amdgpu_ucode_validate
	movl	%eax, %r13d
	testl	%eax, %eax
	jne	LBB0_16
## %bb.49:
	movq	56(%r15), %rax
	movq	(%rax), %rbx
	movl	8(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 48(%r15)
	movl	(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 52(%r15)
	jmp	LBB0_38
LBB0_50:
	callq	___stack_chk_fail
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"\n"

L_.str.1:                               ## @.str.1
	.asciz	"navi10"

L_.str.2:                               ## @.str.2
	.asciz	"navi14"

L_.str.3:                               ## @.str.3
	.asciz	"_wks"

L_.str.4:                               ## @.str.4
	.asciz	"navi12"

L_.str.5:                               ## @.str.5
	.asciz	"amdgpu/%s_pfp%s.bin"

L_.str.6:                               ## @.str.6
	.asciz	"amdgpu/%s_me%s.bin"

L_.str.7:                               ## @.str.7
	.asciz	"amdgpu/%s_ce%s.bin"

L_.str.8:                               ## @.str.8
	.asciz	"amdgpu/%s_rlc.bin"

	.comm	_GFP_KERNEL,4,2                 ## @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ## @ENOMEM
L_.str.9:                               ## @.str.9
	.asciz	"amdgpu/%s_mec%s.bin"

L_.str.10:                              ## @.str.10
	.asciz	"amdgpu/%s_mec2%s.bin"

	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_CP_PFP,8,3     ## @AMDGPU_UCODE_ID_CP_PFP
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
	.comm	_AMDGPU_UCODE_ID_CP_ME,8,3      ## @AMDGPU_UCODE_ID_CP_ME
	.comm	_AMDGPU_UCODE_ID_CP_CE,8,3      ## @AMDGPU_UCODE_ID_CP_CE
	.comm	_AMDGPU_UCODE_ID_RLC_G,8,3      ## @AMDGPU_UCODE_ID_RLC_G
	.comm	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,8,3 ## @AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
	.comm	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,8,3 ## @AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
	.comm	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,8,3 ## @AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
	.comm	_AMDGPU_UCODE_ID_CP_MEC1,8,3    ## @AMDGPU_UCODE_ID_CP_MEC1
	.comm	_AMDGPU_UCODE_ID_CP_MEC1_JT,8,3 ## @AMDGPU_UCODE_ID_CP_MEC1_JT
	.comm	_AMDGPU_UCODE_ID_CP_MEC2,8,3    ## @AMDGPU_UCODE_ID_CP_MEC2
	.comm	_AMDGPU_UCODE_ID_CP_MEC2_JT,8,3 ## @AMDGPU_UCODE_ID_CP_MEC2_JT
L_.str.11:                              ## @.str.11
	.asciz	"gfx10: Failed to load firmware \"%s\"\n"

	.no_dead_strip	_gfx_v10_0_init_microcode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v10_0_init_microcode
_gfx_v10_0_init_microcode:              ; @gfx_v10_0_init_microcode
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #144
	.cfi_def_cfa_offset 144
	stp	x24, x23, [sp, #80]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #96]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #112]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #128]            ; 16-byte Folded Spill
	add	x29, sp, #128
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x8, ___stack_chk_guard@GOTPAGE
Lloh1:
	ldr	x8, [x8, ___stack_chk_guard@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	stur	x8, [x29, #-56]
Lloh3:
	adrp	x0, l_.str@PAGE
Lloh4:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG
	add	x20, sp, #22
	add	x0, sp, #22
	mov	w1, #0
	mov	w2, #10
	bl	_memset
	ldr	w8, [x19]
	cmp	w8, #130
	b.eq	LBB0_7
; %bb.1:
	cmp	w8, #129
	b.eq	LBB0_8
; %bb.2:
	cmp	w8, #128
	b.ne	LBB0_9
; %bb.3:
	ldr	x8, [x19, #208]
	ldr	w9, [x8]
	mov	w10, #29504
	cmp	w9, w10
	b.ne	LBB0_5
; %bb.4:
	ldr	w8, [x8, #4]
	cbnz	w8, LBB0_6
LBB0_5:
Lloh5:
	adrp	x2, l_.str.3@PAGE
Lloh6:
	add	x2, x2, l_.str.3@PAGEOFF
	add	x0, sp, #22
	mov	w1, #10
	bl	_snprintf
LBB0_6:
Lloh7:
	adrp	x22, l_.str.2@PAGE
Lloh8:
	add	x22, x22, l_.str.2@PAGEOFF
	b	LBB0_10
LBB0_7:
Lloh9:
	adrp	x22, l_.str.1@PAGE
Lloh10:
	add	x22, x22, l_.str.1@PAGEOFF
	b	LBB0_10
LBB0_8:
Lloh11:
	adrp	x22, l_.str.4@PAGE
Lloh12:
	add	x22, x22, l_.str.4@PAGEOFF
	b	LBB0_10
LBB0_9:
	bl	_BUG
                                        ; implicit-def: $x22
LBB0_10:
	stp	x22, x20, [sp]
Lloh13:
	adrp	x2, l_.str.5@PAGE
Lloh14:
	add	x2, x2, l_.str.5@PAGEOFF
	add	x0, sp, #32
	mov	w1, #40
	bl	_snprintf
	add	x21, x19, #96
	ldr	w2, [x19, #176]
	add	x1, sp, #32
	mov	x0, x21
	bl	_request_firmware
	mov	x20, x0
	cbnz	w0, LBB0_17
; %bb.11:
	ldr	x0, [x21]
	bl	_amdgpu_ucode_validate
	mov	x20, x0
	cbnz	w0, LBB0_17
; %bb.12:
	ldr	x8, [x19, #96]
	ldr	x20, [x8]
	ldr	w0, [x20, #8]
	bl	_le32_to_cpu
	str	w0, [x19, #8]
	ldr	w0, [x20]
	bl	_le32_to_cpu
	str	w0, [x19, #12]
	add	x8, sp, #22
	stp	x22, x8, [sp]
Lloh15:
	adrp	x2, l_.str.6@PAGE
Lloh16:
	add	x2, x2, l_.str.6@PAGEOFF
	add	x0, sp, #32
	mov	w1, #40
	bl	_snprintf
	add	x21, x19, #88
	ldr	w2, [x19, #176]
	add	x1, sp, #32
	mov	x0, x21
	bl	_request_firmware
	mov	x20, x0
	cbnz	w0, LBB0_17
; %bb.13:
	ldr	x0, [x21]
	bl	_amdgpu_ucode_validate
	mov	x20, x0
	cbnz	w0, LBB0_17
; %bb.14:
	ldr	x8, [x19, #88]
	ldr	x20, [x8]
	ldr	w0, [x20, #8]
	bl	_le32_to_cpu
	str	w0, [x19, #16]
	ldr	w0, [x20]
	bl	_le32_to_cpu
	str	w0, [x19, #20]
	add	x8, sp, #22
	stp	x22, x8, [sp]
Lloh17:
	adrp	x2, l_.str.7@PAGE
Lloh18:
	add	x2, x2, l_.str.7@PAGEOFF
	add	x0, sp, #32
	mov	w1, #40
	bl	_snprintf
	add	x21, x19, #80
	ldr	w2, [x19, #176]
	add	x1, sp, #32
	mov	x0, x21
	bl	_request_firmware
	mov	x20, x0
	cbnz	w0, LBB0_17
; %bb.15:
	ldr	x0, [x21]
	bl	_amdgpu_ucode_validate
	mov	x20, x0
	cbnz	w0, LBB0_17
; %bb.16:
	ldr	x8, [x19, #80]
	ldr	x20, [x8]
	ldr	w0, [x20, #8]
	bl	_le32_to_cpu
	str	w0, [x19, #24]
	ldr	w0, [x20]
	bl	_le32_to_cpu
	str	w0, [x19, #28]
	str	x22, [sp]
Lloh19:
	adrp	x2, l_.str.8@PAGE
Lloh20:
	add	x2, x2, l_.str.8@PAGEOFF
	add	x0, sp, #32
	mov	w1, #40
	bl	_snprintf
	add	x21, x19, #72
	ldr	w2, [x19, #176]
	add	x1, sp, #32
	mov	x0, x21
	bl	_request_firmware
	mov	x20, x0
	cbz	w0, LBB0_20
LBB0_17:
	ldr	w0, [x19, #176]
Lloh21:
	adrp	x1, l_.str.11@PAGE
Lloh22:
	add	x1, x1, l_.str.11@PAGEOFF
	add	x2, sp, #32
	bl	_dev_err
	ldr	x0, [x19, #96]
	bl	_release_firmware
	str	xzr, [x19, #96]
	ldr	x0, [x19, #88]
	bl	_release_firmware
	str	xzr, [x19, #88]
	ldr	x0, [x19, #80]
	bl	_release_firmware
	str	xzr, [x19, #80]
	ldr	x0, [x19, #72]
	bl	_release_firmware
	str	xzr, [x19, #72]
	ldr	x0, [x19, #64]
	bl	_release_firmware
	str	xzr, [x19, #64]
	ldr	x0, [x19, #56]
	bl	_release_firmware
	str	xzr, [x19, #56]
LBB0_18:
	mov	x0, x19
	bl	_gfx_v10_0_check_gfxoff_flag
	ldur	x8, [x29, #-56]
Lloh23:
	adrp	x9, ___stack_chk_guard@GOTPAGE
Lloh24:
	ldr	x9, [x9, ___stack_chk_guard@GOTPAGEOFF]
Lloh25:
	ldr	x9, [x9]
	cmp	x9, x8
	b.ne	LBB0_51
; %bb.19:
	mov	x0, x20
	ldp	x29, x30, [sp, #128]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #112]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #96]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #80]             ; 16-byte Folded Reload
	add	sp, sp, #144
	ret
LBB0_20:
	ldr	x0, [x21]
	bl	_amdgpu_ucode_validate
	ldr	x8, [x21]
	ldr	x21, [x8]
	ldr	w0, [x21, #56]
	bl	_le16_to_cpu
	mov	x20, x0
	ldr	w0, [x21, #52]
	bl	_le16_to_cpu
	cmp	w20, #2
	b.ne	LBB0_23
; %bb.21:
	cmp	w0, #1
	b.ne	LBB0_23
; %bb.22:
	mov	w8, #1
	str	w8, [x19, #104]
LBB0_23:
	ldr	w0, [x21, #48]
	bl	_le32_to_cpu
	str	w0, [x19, #32]
	ldr	w0, [x21]
	bl	_le32_to_cpu
	str	w0, [x19, #36]
	ldr	w0, [x21, #4]
	bl	_le32_to_cpu
	str	w0, [x19, #108]
	ldr	w0, [x21, #8]
	bl	_le32_to_cpu
	str	w0, [x19, #112]
	ldr	w0, [x21, #12]
	bl	_le32_to_cpu
	str	w0, [x19, #116]
	ldr	w0, [x21, #16]
	bl	_le32_to_cpu
	str	w0, [x19, #120]
	ldr	w0, [x21, #20]
	bl	_le32_to_cpu
	str	w0, [x19, #124]
	ldr	w0, [x21, #24]
	bl	_le32_to_cpu
	str	w0, [x19, #128]
	ldr	w0, [x21, #28]
	bl	_le32_to_cpu
	str	w0, [x19, #132]
	ldr	w0, [x21, #32]
	bl	_le32_to_cpu
	str	w0, [x19, #136]
	ldr	w0, [x21, #36]
	bl	_le32_to_cpu
	str	w0, [x19, #140]
	ldr	w8, [x19, #136]
	add	w0, w8, w0
Lloh26:
	adrp	x8, _GFP_KERNEL@GOTPAGE
Lloh27:
	ldr	x8, [x8, _GFP_KERNEL@GOTPAGEOFF]
Lloh28:
	ldr	w1, [x8]
	bl	_kmalloc
	str	x0, [x19, #144]
	cbz	x0, LBB0_26
; %bb.24:
	ldr	w0, [x21, #40]
	bl	_le32_to_cpu
	ldr	w8, [x21, #32]
	cmp	w8, #4
	b.hs	LBB0_28
; %bb.25:
	mov	x20, #0
	ldr	x8, [x19, #144]
	b	LBB0_30
LBB0_26:
Lloh29:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh30:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
Lloh31:
	ldr	w8, [x8]
	cbz	w8, LBB0_48
; %bb.27:
	neg	w20, w8
	b	LBB0_17
LBB0_28:
	mov	x20, #0
	add	x23, x21, w0, sxtw
LBB0_29:                                ; =>This Inner Loop Header: Depth=1
	lsl	x24, x20, #2
	ldr	w0, [x23, x24]
	bl	_le32_to_cpu
	ldr	x8, [x19, #144]
	str	w0, [x8, x24]
	add	x20, x20, #1
	ldr	w9, [x21, #32]
	cmp	x20, x9, lsr #2
	b.lo	LBB0_29
LBB0_30:
	add	x8, x8, x20, lsl #2
	str	x8, [x19, #152]
	ldr	w0, [x21, #44]
	bl	_le32_to_cpu
	ldr	w8, [x21, #36]
	cmp	w8, #4
	b.lo	LBB0_33
; %bb.31:
	mov	x20, #0
	add	x23, x21, w0, sxtw
LBB0_32:                                ; =>This Inner Loop Header: Depth=1
	lsl	x24, x20, #2
	ldr	w0, [x23, x24]
	bl	_le32_to_cpu
	ldr	x8, [x19, #152]
	str	w0, [x8, x24]
	add	x20, x20, #1
	ldr	w8, [x21, #36]
	cmp	x20, x8, lsr #2
	b.lo	LBB0_32
LBB0_33:
	ldr	w8, [x19, #104]
	cbz	w8, LBB0_35
; %bb.34:
	mov	x0, x19
	bl	_gfx_v10_0_init_rlc_ext_microcode
LBB0_35:
	add	x8, sp, #22
	stp	x22, x8, [sp]
Lloh32:
	adrp	x2, l_.str.9@PAGE
Lloh33:
	add	x2, x2, l_.str.9@PAGEOFF
	add	x0, sp, #32
	mov	w1, #40
	bl	_snprintf
	add	x21, x19, #64
	ldr	w2, [x19, #176]
	add	x1, sp, #32
	mov	x0, x21
	bl	_request_firmware
	mov	x20, x0
	cbnz	w0, LBB0_17
; %bb.36:
	ldr	x0, [x21]
	bl	_amdgpu_ucode_validate
	mov	x20, x0
	cbnz	w0, LBB0_17
; %bb.37:
	ldr	x8, [x19, #64]
	ldr	x20, [x8]
	ldr	w0, [x20, #8]
	bl	_le32_to_cpu
	str	w0, [x19, #40]
	ldr	w0, [x20]
	bl	_le32_to_cpu
	str	w0, [x19, #44]
	add	x8, sp, #22
	stp	x22, x8, [sp]
Lloh34:
	adrp	x2, l_.str.10@PAGE
Lloh35:
	add	x2, x2, l_.str.10@PAGEOFF
	add	x0, sp, #32
	mov	w1, #40
	bl	_snprintf
	add	x20, x19, #56
	ldr	w2, [x19, #176]
	add	x1, sp, #32
	mov	x0, x20
	bl	_request_firmware
	cbz	w0, LBB0_49
; %bb.38:
	str	xzr, [x20]
LBB0_39:
	ldr	x8, [x19, #184]
Lloh36:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh37:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh38:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_47
; %bb.40:
	ldr	x8, [x19, #200]
Lloh39:
	adrp	x9, _AMDGPU_UCODE_ID_CP_PFP@GOTPAGE
Lloh40:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_CP_PFP@GOTPAGEOFF]
Lloh41:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19, #96]
	str	x9, [x8, #8]
	ldr	x8, [x9]
	ldr	w0, [x8]
	bl	_le32_to_cpu
Lloh42:
	adrp	x21, _PAGE_SIZE@GOTPAGE
Lloh43:
	ldr	x21, [x21, _PAGE_SIZE@GOTPAGEOFF]
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #192]
	add	w8, w8, w0
	str	w8, [x19, #192]
	ldr	x8, [x19, #200]
Lloh44:
	adrp	x9, _AMDGPU_UCODE_ID_CP_ME@GOTPAGE
Lloh45:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_CP_ME@GOTPAGEOFF]
Lloh46:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19, #88]
	str	x9, [x8, #8]
	ldr	x8, [x9]
	ldr	w0, [x8]
	bl	_le32_to_cpu
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #192]
	add	w8, w8, w0
	str	w8, [x19, #192]
	ldr	x8, [x19, #200]
Lloh47:
	adrp	x9, _AMDGPU_UCODE_ID_CP_CE@GOTPAGE
Lloh48:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_CP_CE@GOTPAGEOFF]
Lloh49:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19, #80]
	str	x9, [x8, #8]
	ldr	x8, [x9]
	ldr	w0, [x8]
	bl	_le32_to_cpu
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #192]
	add	w8, w8, w0
	str	w8, [x19, #192]
	ldr	x8, [x19, #200]
Lloh50:
	adrp	x9, _AMDGPU_UCODE_ID_RLC_G@GOTPAGE
Lloh51:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_RLC_G@GOTPAGEOFF]
Lloh52:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19, #72]
	str	x9, [x8, #8]
	ldr	x8, [x9]
	ldr	w0, [x8]
	bl	_le32_to_cpu
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #192]
	add	w8, w8, w0
	str	w8, [x19, #192]
	ldr	w8, [x19, #104]
	cbz	w8, LBB0_45
; %bb.41:
	ldr	w0, [x19, #160]
	cbz	w0, LBB0_45
; %bb.42:
	ldr	w8, [x19, #164]
	cbz	w8, LBB0_45
; %bb.43:
	ldr	w8, [x19, #168]
	cbz	w8, LBB0_45
; %bb.44:
	ldr	x8, [x19, #200]
Lloh53:
	adrp	x9, _AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL@GOTPAGE
Lloh54:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL@GOTPAGEOFF]
Lloh55:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19, #72]
	str	x9, [x8, #8]
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #192]
	add	w8, w8, w0
	str	w8, [x19, #192]
	ldr	x8, [x19, #200]
Lloh56:
	adrp	x9, _AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM@GOTPAGE
Lloh57:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM@GOTPAGEOFF]
Lloh58:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19, #72]
	str	x9, [x8, #8]
	ldr	w0, [x19, #164]
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #192]
	add	w8, w8, w0
	str	w8, [x19, #192]
	ldr	x8, [x19, #200]
Lloh59:
	adrp	x9, _AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM@GOTPAGE
Lloh60:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM@GOTPAGEOFF]
Lloh61:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19, #72]
	str	x9, [x8, #8]
	ldr	w0, [x19, #168]
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #192]
	add	w8, w8, w0
	str	w8, [x19, #192]
LBB0_45:
	ldr	x8, [x19, #200]
Lloh62:
	adrp	x9, _AMDGPU_UCODE_ID_CP_MEC1@GOTPAGE
Lloh63:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_CP_MEC1@GOTPAGEOFF]
Lloh64:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19, #64]
	str	x9, [x8, #8]
	ldr	x22, [x9]
	ldr	w0, [x22]
	bl	_le32_to_cpu
	mov	x20, x0
	ldr	w0, [x22, #4]
	bl	_le32_to_cpu
	sub	w0, w20, w0, lsl #2
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #192]
	add	w8, w8, w0
	str	w8, [x19, #192]
	ldr	x8, [x19, #200]
Lloh65:
	adrp	x9, _AMDGPU_UCODE_ID_CP_MEC1_JT@GOTPAGE
Lloh66:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_CP_MEC1_JT@GOTPAGEOFF]
Lloh67:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19, #64]
	str	x9, [x8, #8]
	ldr	w0, [x22, #4]
	bl	_le32_to_cpu
	lsl	w0, w0, #2
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #192]
	add	w8, w8, w0
	str	w8, [x19, #192]
	ldr	x8, [x19, #56]
	cbz	x8, LBB0_47
; %bb.46:
	ldr	x9, [x19, #200]
Lloh68:
	adrp	x10, _AMDGPU_UCODE_ID_CP_MEC2@GOTPAGE
Lloh69:
	ldr	x10, [x10, _AMDGPU_UCODE_ID_CP_MEC2@GOTPAGEOFF]
Lloh70:
	ldr	x10, [x10]
	add	x9, x9, x10, lsl #4
	stp	x10, x8, [x9]
	ldr	x22, [x8]
	ldr	w0, [x22]
	bl	_le32_to_cpu
	mov	x20, x0
	ldr	w0, [x22, #4]
	bl	_le32_to_cpu
	sub	w0, w20, w0, lsl #2
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #192]
	add	w8, w8, w0
	str	w8, [x19, #192]
	ldr	x8, [x19, #200]
Lloh71:
	adrp	x9, _AMDGPU_UCODE_ID_CP_MEC2_JT@GOTPAGE
Lloh72:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_CP_MEC2_JT@GOTPAGEOFF]
Lloh73:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19, #56]
	str	x9, [x8, #8]
	ldr	w0, [x22, #4]
	bl	_le32_to_cpu
	lsl	w0, w0, #2
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #192]
	add	w8, w8, w0
	str	w8, [x19, #192]
LBB0_47:
	mov	x0, x19
	bl	_gfx_v10_0_check_fw_write_wait
LBB0_48:
	mov	w20, #0
	b	LBB0_18
LBB0_49:
	ldr	x0, [x20]
	bl	_amdgpu_ucode_validate
	mov	x20, x0
	cbnz	w0, LBB0_17
; %bb.50:
	ldr	x8, [x19, #56]
	ldr	x20, [x8]
	ldr	w0, [x20, #8]
	bl	_le32_to_cpu
	str	w0, [x19, #48]
	ldr	w0, [x20]
	bl	_le32_to_cpu
	str	w0, [x19, #52]
	b	LBB0_39
LBB0_51:
	bl	___stack_chk_fail
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpAdd	Lloh7, Lloh8
	.loh AdrpAdd	Lloh9, Lloh10
	.loh AdrpAdd	Lloh11, Lloh12
	.loh AdrpAdd	Lloh13, Lloh14
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpAdd	Lloh17, Lloh18
	.loh AdrpAdd	Lloh19, Lloh20
	.loh AdrpAdd	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpAdd	Lloh32, Lloh33
	.loh AdrpAdd	Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"\n"

l_.str.1:                               ; @.str.1
	.asciz	"navi10"

l_.str.2:                               ; @.str.2
	.asciz	"navi14"

l_.str.3:                               ; @.str.3
	.asciz	"_wks"

l_.str.4:                               ; @.str.4
	.asciz	"navi12"

l_.str.5:                               ; @.str.5
	.asciz	"amdgpu/%s_pfp%s.bin"

l_.str.6:                               ; @.str.6
	.asciz	"amdgpu/%s_me%s.bin"

l_.str.7:                               ; @.str.7
	.asciz	"amdgpu/%s_ce%s.bin"

l_.str.8:                               ; @.str.8
	.asciz	"amdgpu/%s_rlc.bin"

	.comm	_GFP_KERNEL,4,2                 ; @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ; @ENOMEM
l_.str.9:                               ; @.str.9
	.asciz	"amdgpu/%s_mec%s.bin"

l_.str.10:                              ; @.str.10
	.asciz	"amdgpu/%s_mec2%s.bin"

	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_CP_PFP,8,3     ; @AMDGPU_UCODE_ID_CP_PFP
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
	.comm	_AMDGPU_UCODE_ID_CP_ME,8,3      ; @AMDGPU_UCODE_ID_CP_ME
	.comm	_AMDGPU_UCODE_ID_CP_CE,8,3      ; @AMDGPU_UCODE_ID_CP_CE
	.comm	_AMDGPU_UCODE_ID_RLC_G,8,3      ; @AMDGPU_UCODE_ID_RLC_G
	.comm	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,8,3 ; @AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
	.comm	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,8,3 ; @AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
	.comm	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,8,3 ; @AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
	.comm	_AMDGPU_UCODE_ID_CP_MEC1,8,3    ; @AMDGPU_UCODE_ID_CP_MEC1
	.comm	_AMDGPU_UCODE_ID_CP_MEC1_JT,8,3 ; @AMDGPU_UCODE_ID_CP_MEC1_JT
	.comm	_AMDGPU_UCODE_ID_CP_MEC2,8,3    ; @AMDGPU_UCODE_ID_CP_MEC2
	.comm	_AMDGPU_UCODE_ID_CP_MEC2_JT,8,3 ; @AMDGPU_UCODE_ID_CP_MEC2_JT
l_.str.11:                              ; @.str.11
	.asciz	"gfx10: Failed to load firmware \"%s\"\n"

	.no_dead_strip	_gfx_v10_0_init_microcode
.subsections_via_symbols
