	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r100_vram_init_sizes           ## -- Begin function r100_vram_init_sizes
	.p2align	4, 0x90
_r100_vram_init_sizes:                  ## @r100_vram_init_sizes
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movl	48(%rdi), %edi
	xorl	%esi, %esi
	callq	_pci_resource_start
	movl	%eax, 40(%rbx)
	movl	48(%rbx), %edi
	xorl	%esi, %esi
	callq	_pci_resource_len
	movq	%rax, 8(%rbx)
	movq	%rbx, %rdi
	callq	_r100_get_accessible_vram
	movq	8(%rbx), %rcx
	cmpq	%rcx, %rax
	cmovlq	%rax, %rcx
	movq	%rcx, 16(%rbx)
	movq	_RADEON_CONFIG_APER_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	%rax, %r14
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rbx)
	je	LBB0_3
## %bb.1:
	movq	_RADEON_NB_TOM@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %ecx
	shll	$16, %ecx
	negl	%ecx
	leal	(%rax,%rcx), %esi
	addl	$65536, %esi                    ## imm = 0x10000
	andl	$-65536, %esi                   ## imm = 0xFFFF0000
	movl	%esi, 24(%rbx)
	movq	_RADEON_CONFIG_MEMSIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32
	movslq	24(%rbx), %rax
	jmp	LBB0_2
LBB0_3:
	movq	_RADEON_CONFIG_MEMSIZE@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32
	movl	%eax, 24(%rbx)
	testl	%eax, %eax
	jne	LBB0_5
## %bb.4:
	movl	$8388608, 24(%rbx)              ## imm = 0x800000
	movl	(%r15), %edi
	movl	$8388608, %esi                  ## imm = 0x800000
	callq	_WREG32
	movl	24(%rbx), %eax
LBB0_5:
	movq	8(%rbx), %rcx
	cmpq	%r14, %rcx
	cmovgq	%rcx, %r14
	cltq
	cmpq	%rax, %r14
	jle	LBB0_2
## %bb.6:
	movq	%r14, 32(%rbx)
	jmp	LBB0_7
LBB0_2:
	movq	%rax, 32(%rbx)
LBB0_7:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_CONFIG_APER_SIZE,4,2    ## @RADEON_CONFIG_APER_SIZE
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
	.comm	_RADEON_NB_TOM,4,2              ## @RADEON_NB_TOM
	.comm	_RADEON_CONFIG_MEMSIZE,4,2      ## @RADEON_CONFIG_MEMSIZE
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r100_vram_init_sizes           ; -- Begin function r100_vram_init_sizes
	.p2align	2
_r100_vram_init_sizes:                  ; @r100_vram_init_sizes
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	w0, [x0, #48]
	mov	w1, #0
	bl	_pci_resource_start
	str	w0, [x19, #40]
	ldr	w0, [x19, #48]
	mov	w1, #0
	bl	_pci_resource_len
	str	x0, [x19, #8]
	mov	x0, x19
	bl	_r100_get_accessible_vram
	ldr	x8, [x19, #8]
	cmp	x0, x8
	csel	x8, x0, x8, lt
	str	x8, [x19, #16]
Lloh0:
	adrp	x8, _RADEON_CONFIG_APER_SIZE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_CONFIG_APER_SIZE@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_RREG32
	ldr	w8, [x19]
Lloh3:
	adrp	x9, _RADEON_IS_IGP@GOTPAGE
Lloh4:
	ldr	x9, [x9, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
Lloh6:
	adrp	x8, _RADEON_NB_TOM@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_NB_TOM@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	bl	_RREG32
	sub	w8, w0, w0, lsl #16
	add	w8, w8, #16, lsl #12            ; =65536
	and	w1, w8, #0xffff0000
	str	w1, [x19, #24]
Lloh9:
	adrp	x8, _RADEON_CONFIG_MEMSIZE@GOTPAGE
Lloh10:
	ldr	x8, [x8, _RADEON_CONFIG_MEMSIZE@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	bl	_WREG32
	ldrsw	x8, [x19, #24]
	b	LBB0_6
LBB0_2:
	mov	x20, x0
Lloh12:
	adrp	x21, _RADEON_CONFIG_MEMSIZE@GOTPAGE
Lloh13:
	ldr	x21, [x21, _RADEON_CONFIG_MEMSIZE@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
	str	w0, [x19, #24]
	mov	x8, x0
	cbnz	w0, LBB0_4
; %bb.3:
	mov	w8, #8388608
	str	w8, [x19, #24]
	ldr	w0, [x21]
	mov	w1, #8388608
	bl	_WREG32
	ldr	w8, [x19, #24]
LBB0_4:
	ldr	x9, [x19, #8]
	cmp	x9, x20
	csel	x9, x9, x20, gt
	sxtw	x8, w8
	cmp	x9, x8
	b.le	LBB0_6
; %bb.5:
	str	x9, [x19, #32]
	b	LBB0_7
LBB0_6:
	str	x8, [x19, #32]
LBB0_7:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh12, Lloh13
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_CONFIG_APER_SIZE,4,2    ; @RADEON_CONFIG_APER_SIZE
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
	.comm	_RADEON_NB_TOM,4,2              ; @RADEON_NB_TOM
	.comm	_RADEON_CONFIG_MEMSIZE,4,2      ; @RADEON_CONFIG_MEMSIZE
.subsections_via_symbols
