	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function cik_pcie_gart_disable
_cik_pcie_gart_disable:                 ## @cik_pcie_gart_disable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movl	$1, %ebx
	movl	$4294967268, %r14d              ## imm = 0xFFFFFFE4
	movl	$4, %r15d
	movq	_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR@GOTPCREL(%rip), %r13
	jmp	LBB0_1
	.p2align	4, 0x90
LBB0_3:                                 ##   in Loop: Header=BB0_1 Depth=1
	movl	%r14d, %edi
	andl	$-4, %edi
	addq	(%r13), %rdi
LBB0_4:                                 ##   in Loop: Header=BB0_1 Depth=1
	callq	_RREG32
	movq	(%r12), %rcx
	movl	%eax, (%rcx,%rbx,4)
	incq	%rbx
	addq	$4, %r14
	addq	$4, %r15
	cmpq	$16, %rbx
	je	LBB0_5
LBB0_1:                                 ## =>This Inner Loop Header: Depth=1
	cmpq	$7, %rbx
	ja	LBB0_3
## %bb.2:                               ##   in Loop: Header=BB0_1 Depth=1
	movq	_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	%r15, %rdi
	jmp	LBB0_4
LBB0_5:
	movq	_VM_CONTEXT0_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_VM_CONTEXT1_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_MC_VM_MX_L1_TLB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_SYSTEM_ACCESS_MODE_NOT_IN_SYS@GOTPCREL(%rip), %rax
	movq	_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	callq	_WREG32
	movq	_VM_L2_CNTL@GOTPCREL(%rip), %rax
	movq	_ENABLE_L2_FRAGMENT_PROCESSING@GOTPCREL(%rip), %rcx
	movq	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	movl	(%rax), %r14d
	movq	_ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	$7, %edi
	callq	_EFFECTIVE_L2_QUEUE_SIZE
	movl	%eax, %r15d
	movl	$1, %edi
	callq	_CONTEXT1_IDENTITY_ACCESS_MODE
	orl	%eax, %r15d
	orl	%ebx, %r15d
	movl	%r14d, %edi
	movl	%r15d, %esi
	callq	_WREG32
	movq	_VM_L2_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_VM_L2_CNTL3@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_L2_CACHE_BIGK_ASSOCIATIVITY@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	$6, %edi
	callq	_L2_CACHE_BIGK_FRAGMENT_SIZE
	orl	%eax, %r15d
	movl	%r14d, %edi
	movl	%r15d, %esi
	callq	_WREG32
	movq	%r12, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_gart_table_vram_unpin   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR,8,3 ## @VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
	.comm	_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR,8,3 ## @VM_CONTEXT8_PAGE_TABLE_BASE_ADDR
	.comm	_VM_CONTEXT0_CNTL,4,2           ## @VM_CONTEXT0_CNTL
	.comm	_VM_CONTEXT1_CNTL,4,2           ## @VM_CONTEXT1_CNTL
	.comm	_MC_VM_MX_L1_TLB_CNTL,4,2       ## @MC_VM_MX_L1_TLB_CNTL
	.comm	_SYSTEM_ACCESS_MODE_NOT_IN_SYS,4,2 ## @SYSTEM_ACCESS_MODE_NOT_IN_SYS
	.comm	_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU,4,2 ## @SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
	.comm	_VM_L2_CNTL,4,2                 ## @VM_L2_CNTL
	.comm	_ENABLE_L2_FRAGMENT_PROCESSING,4,2 ## @ENABLE_L2_FRAGMENT_PROCESSING
	.comm	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE,4,2 ## @ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE,4,2 ## @ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_VM_L2_CNTL2,4,2                ## @VM_L2_CNTL2
	.comm	_VM_L2_CNTL3,4,2                ## @VM_L2_CNTL3
	.comm	_L2_CACHE_BIGK_ASSOCIATIVITY,4,2 ## @L2_CACHE_BIGK_ASSOCIATIVITY
	.no_dead_strip	_cik_pcie_gart_disable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cik_pcie_gart_disable
_cik_pcie_gart_disable:                 ; @cik_pcie_gart_disable
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x20, _VM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPAGE
Lloh1:
	ldr	x20, [x20, _VM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPAGEOFF]
	ldr	x8, [x20]
	add	x0, x8, #4
	bl	_RREG32
	ldr	x8, [x19]
	str	w0, [x8, #4]
	ldr	x8, [x20]
	add	x0, x8, #8
	bl	_RREG32
	ldr	x8, [x19]
	str	w0, [x8, #8]
	ldr	x8, [x20]
	add	x0, x8, #12
	bl	_RREG32
	ldr	x8, [x19]
	str	w0, [x8, #12]
	ldr	x8, [x20]
	add	x0, x8, #16
	bl	_RREG32
	ldr	x8, [x19]
	str	w0, [x8, #16]
	ldr	x8, [x20]
	add	x0, x8, #20
	bl	_RREG32
	ldr	x8, [x19]
	str	w0, [x8, #20]
	ldr	x8, [x20]
	add	x0, x8, #24
	bl	_RREG32
	ldr	x8, [x19]
	str	w0, [x8, #24]
	ldr	x8, [x20]
	add	x0, x8, #28
	bl	_RREG32
	ldr	x8, [x19]
	str	w0, [x8, #28]
Lloh2:
	adrp	x20, _VM_CONTEXT8_PAGE_TABLE_BASE_ADDR@GOTPAGE
Lloh3:
	ldr	x20, [x20, _VM_CONTEXT8_PAGE_TABLE_BASE_ADDR@GOTPAGEOFF]
	ldr	x0, [x20]
	bl	_RREG32
	ldr	x8, [x19]
	str	w0, [x8, #32]
	ldr	x8, [x20]
	add	x0, x8, #4
	bl	_RREG32
	ldr	x8, [x19]
	str	w0, [x8, #36]
	ldr	x8, [x20]
	add	x0, x8, #8
	bl	_RREG32
	ldr	x8, [x19]
	str	w0, [x8, #40]
	ldr	x8, [x20]
	add	x0, x8, #12
	bl	_RREG32
	ldr	x8, [x19]
	str	w0, [x8, #44]
	ldr	x8, [x20]
	add	x0, x8, #16
	bl	_RREG32
	ldr	x8, [x19]
	str	w0, [x8, #48]
	ldr	x8, [x20]
	add	x0, x8, #20
	bl	_RREG32
	ldr	x8, [x19]
	str	w0, [x8, #52]
	ldr	x8, [x20]
	add	x0, x8, #24
	bl	_RREG32
	ldr	x8, [x19]
	str	w0, [x8, #56]
	ldr	x8, [x20]
	add	x0, x8, #28
	bl	_RREG32
	ldr	x8, [x19]
	str	w0, [x8, #60]
Lloh4:
	adrp	x8, _VM_CONTEXT0_CNTL@GOTPAGE
Lloh5:
	ldr	x8, [x8, _VM_CONTEXT0_CNTL@GOTPAGEOFF]
Lloh6:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh7:
	adrp	x8, _VM_CONTEXT1_CNTL@GOTPAGE
Lloh8:
	ldr	x8, [x8, _VM_CONTEXT1_CNTL@GOTPAGEOFF]
Lloh9:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh10:
	adrp	x8, _MC_VM_MX_L1_TLB_CNTL@GOTPAGE
Lloh11:
	ldr	x8, [x8, _MC_VM_MX_L1_TLB_CNTL@GOTPAGEOFF]
Lloh12:
	adrp	x9, _SYSTEM_ACCESS_MODE_NOT_IN_SYS@GOTPAGE
Lloh13:
	ldr	x9, [x9, _SYSTEM_ACCESS_MODE_NOT_IN_SYS@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
Lloh15:
	ldr	w8, [x9]
Lloh16:
	adrp	x9, _SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU@GOTPAGE
Lloh17:
	ldr	x9, [x9, _SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	orr	w1, w9, w8
	bl	_WREG32
Lloh19:
	adrp	x8, _VM_L2_CNTL@GOTPAGE
Lloh20:
	ldr	x8, [x8, _VM_L2_CNTL@GOTPAGEOFF]
Lloh21:
	ldr	w20, [x8]
Lloh22:
	adrp	x8, _ENABLE_L2_FRAGMENT_PROCESSING@GOTPAGE
Lloh23:
	ldr	x8, [x8, _ENABLE_L2_FRAGMENT_PROCESSING@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
Lloh25:
	adrp	x9, _ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGE
Lloh26:
	ldr	x9, [x9, _ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh28:
	adrp	x9, _ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGE
Lloh29:
	ldr	x9, [x9, _ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
	orr	w21, w8, w9
	mov	w0, #7
	bl	_EFFECTIVE_L2_QUEUE_SIZE
	orr	w21, w21, w0
	mov	w0, #1
	bl	_CONTEXT1_IDENTITY_ACCESS_MODE
	orr	w1, w21, w0
	mov	x0, x20
	bl	_WREG32
Lloh31:
	adrp	x8, _VM_L2_CNTL2@GOTPAGE
Lloh32:
	ldr	x8, [x8, _VM_L2_CNTL2@GOTPAGEOFF]
Lloh33:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh34:
	adrp	x8, _VM_L2_CNTL3@GOTPAGE
Lloh35:
	ldr	x8, [x8, _VM_L2_CNTL3@GOTPAGEOFF]
Lloh36:
	ldr	w20, [x8]
Lloh37:
	adrp	x8, _L2_CACHE_BIGK_ASSOCIATIVITY@GOTPAGE
Lloh38:
	ldr	x8, [x8, _L2_CACHE_BIGK_ASSOCIATIVITY@GOTPAGEOFF]
Lloh39:
	ldr	w21, [x8]
	mov	w0, #6
	bl	_L2_CACHE_BIGK_FRAGMENT_SIZE
	orr	w1, w0, w21
	mov	x0, x20
	bl	_WREG32
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_radeon_gart_table_vram_unpin
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh14
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR,8,3 ; @VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
	.comm	_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR,8,3 ; @VM_CONTEXT8_PAGE_TABLE_BASE_ADDR
	.comm	_VM_CONTEXT0_CNTL,4,2           ; @VM_CONTEXT0_CNTL
	.comm	_VM_CONTEXT1_CNTL,4,2           ; @VM_CONTEXT1_CNTL
	.comm	_MC_VM_MX_L1_TLB_CNTL,4,2       ; @MC_VM_MX_L1_TLB_CNTL
	.comm	_SYSTEM_ACCESS_MODE_NOT_IN_SYS,4,2 ; @SYSTEM_ACCESS_MODE_NOT_IN_SYS
	.comm	_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU,4,2 ; @SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
	.comm	_VM_L2_CNTL,4,2                 ; @VM_L2_CNTL
	.comm	_ENABLE_L2_FRAGMENT_PROCESSING,4,2 ; @ENABLE_L2_FRAGMENT_PROCESSING
	.comm	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE,4,2 ; @ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE,4,2 ; @ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_VM_L2_CNTL2,4,2                ; @VM_L2_CNTL2
	.comm	_VM_L2_CNTL3,4,2                ; @VM_L2_CNTL3
	.comm	_L2_CACHE_BIGK_ASSOCIATIVITY,4,2 ; @L2_CACHE_BIGK_ASSOCIATIVITY
	.no_dead_strip	_cik_pcie_gart_disable
.subsections_via_symbols
