	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ingenic_drm_crtc_update_timings
_ingenic_drm_crtc_update_timings:       ## @ingenic_drm_crtc_update_timings
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movl	(%rsi), %edx
	movl	4(%rsi), %eax
	subl	%eax, %edx
	movl	8(%rsi), %r15d
	movl	%r15d, %ecx
	subl	%eax, %ecx
	movl	%ecx, -52(%rbp)                 ## 4-byte Spill
	movl	12(%rsi), %eax
	addl	%ecx, %eax
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	movl	16(%rsi), %r13d
	movl	20(%rsi), %eax
	subl	%eax, %r13d
	movl	24(%rsi), %r14d
	movl	%r14d, %r12d
	subl	%eax, %r12d
	movq	%rsi, -64(%rbp)                 ## 8-byte Spill
	movl	28(%rsi), %eax
	addl	%r12d, %eax
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movl	(%rdi), %edi
	movq	_JZ_REG_LCD_VSYNC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_JZ_LCD_VSYNC_VPE_OFFSET@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %edx
	callq	_regmap_write
	movl	(%rbx), %edi
	movq	_JZ_REG_LCD_HSYNC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_JZ_LCD_HSYNC_HPE_OFFSET@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	%r13d, -44(%rbp)                ## 4-byte Spill
	shll	%cl, %r13d
	movl	%r13d, %edx
	callq	_regmap_write
	movl	(%rbx), %edi
	movq	_JZ_LCD_VAT_HT_OFFSET@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r14d
	movq	_JZ_REG_LCD_VAT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_JZ_LCD_VAT_VT_OFFSET@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r15d
	orl	%r14d, %r15d
	movl	-48(%rbp), %r14d                ## 4-byte Reload
	movl	%r15d, %edx
	callq	_regmap_write
	movl	(%rbx), %edi
	movq	%rbx, %r13
	movq	_JZ_LCD_DAH_HDS_OFFSET@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r12d
	movq	_JZ_REG_LCD_DAH@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_JZ_LCD_DAH_HDE_OFFSET@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	%r14d, %edx
	shll	%cl, %edx
	orl	%r12d, %edx
	callq	_regmap_write
	movl	(%rbx), %edi
	movq	_JZ_LCD_DAV_VDS_OFFSET@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	-52(%rbp), %ebx                 ## 4-byte Reload
	shll	%cl, %ebx
	movq	_JZ_REG_LCD_DAV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_JZ_LCD_DAV_VDE_OFFSET@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	-56(%rbp), %edx                 ## 4-byte Reload
	shll	%cl, %edx
	orl	%ebx, %edx
	movq	%r13, %rbx
	callq	_regmap_write
	cmpq	$0, 8(%r13)
	je	LBB0_1
## %bb.2:
	movl	(%rbx), %edi
	movq	_JZ_REG_LCD_PS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r14d, %eax
	shll	$16, %eax
	incl	%r14d
	orl	%eax, %r14d
	movl	%r14d, %edx
	callq	_regmap_write
	movl	(%rbx), %edi
	movq	_JZ_REG_LCD_CLS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r14d, %edx
	callq	_regmap_write
	movl	(%rbx), %edi
	movq	_JZ_REG_LCD_SPL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	movl	%edx, %eax
	shll	$16, %eax
	incl	%edx
	orl	%eax, %edx
	callq	_regmap_write
	movl	(%rbx), %edi
	movq	_JZ_REG_LCD_REV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	-64(%rbp), %rax                 ## 8-byte Reload
	movl	24(%rax), %edx
	shll	$16, %edx
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_regmap_write                   ## TAILCALL
LBB0_1:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_JZ_REG_LCD_VSYNC,4,2           ## @JZ_REG_LCD_VSYNC
	.comm	_JZ_LCD_VSYNC_VPS_OFFSET,4,2    ## @JZ_LCD_VSYNC_VPS_OFFSET
	.comm	_JZ_LCD_VSYNC_VPE_OFFSET,4,2    ## @JZ_LCD_VSYNC_VPE_OFFSET
	.comm	_JZ_REG_LCD_HSYNC,4,2           ## @JZ_REG_LCD_HSYNC
	.comm	_JZ_LCD_HSYNC_HPS_OFFSET,4,2    ## @JZ_LCD_HSYNC_HPS_OFFSET
	.comm	_JZ_LCD_HSYNC_HPE_OFFSET,4,2    ## @JZ_LCD_HSYNC_HPE_OFFSET
	.comm	_JZ_REG_LCD_VAT,4,2             ## @JZ_REG_LCD_VAT
	.comm	_JZ_LCD_VAT_HT_OFFSET,4,2       ## @JZ_LCD_VAT_HT_OFFSET
	.comm	_JZ_LCD_VAT_VT_OFFSET,4,2       ## @JZ_LCD_VAT_VT_OFFSET
	.comm	_JZ_REG_LCD_DAH,4,2             ## @JZ_REG_LCD_DAH
	.comm	_JZ_LCD_DAH_HDS_OFFSET,4,2      ## @JZ_LCD_DAH_HDS_OFFSET
	.comm	_JZ_LCD_DAH_HDE_OFFSET,4,2      ## @JZ_LCD_DAH_HDE_OFFSET
	.comm	_JZ_REG_LCD_DAV,4,2             ## @JZ_REG_LCD_DAV
	.comm	_JZ_LCD_DAV_VDS_OFFSET,4,2      ## @JZ_LCD_DAV_VDS_OFFSET
	.comm	_JZ_LCD_DAV_VDE_OFFSET,4,2      ## @JZ_LCD_DAV_VDE_OFFSET
	.comm	_JZ_REG_LCD_PS,4,2              ## @JZ_REG_LCD_PS
	.comm	_JZ_REG_LCD_CLS,4,2             ## @JZ_REG_LCD_CLS
	.comm	_JZ_REG_LCD_SPL,4,2             ## @JZ_REG_LCD_SPL
	.comm	_JZ_REG_LCD_REV,4,2             ## @JZ_REG_LCD_REV
	.no_dead_strip	_ingenic_drm_crtc_update_timings
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ingenic_drm_crtc_update_timings
_ingenic_drm_crtc_update_timings:       ; @ingenic_drm_crtc_update_timings
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x1
	mov	x20, x0
	ldp	w8, w9, [x1]
	sub	w8, w8, w9
	ldp	w25, w10, [x1, #8]
	sub	w24, w25, w9
	add	w23, w24, w10
	ldp	w9, w10, [x1, #16]
	sub	w22, w9, w10
	ldp	w26, w9, [x1, #24]
	sub	w27, w26, w10
	add	w21, w27, w9
Lloh0:
	adrp	x9, _JZ_REG_LCD_VSYNC@GOTPAGE
Lloh1:
	ldr	x9, [x9, _JZ_REG_LCD_VSYNC@GOTPAGEOFF]
	ldr	w0, [x0]
Lloh2:
	ldr	w1, [x9]
Lloh3:
	adrp	x9, _JZ_LCD_VSYNC_VPE_OFFSET@GOTPAGE
Lloh4:
	ldr	x9, [x9, _JZ_LCD_VSYNC_VPE_OFFSET@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	lsl	w2, w8, w9
	bl	_regmap_write
Lloh6:
	adrp	x8, _JZ_REG_LCD_HSYNC@GOTPAGE
Lloh7:
	ldr	x8, [x8, _JZ_REG_LCD_HSYNC@GOTPAGEOFF]
	ldr	w0, [x20]
Lloh8:
	ldr	w1, [x8]
Lloh9:
	adrp	x8, _JZ_LCD_HSYNC_HPE_OFFSET@GOTPAGE
Lloh10:
	ldr	x8, [x8, _JZ_LCD_HSYNC_HPE_OFFSET@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	lsl	w2, w22, w8
	bl	_regmap_write
	ldr	w0, [x20]
Lloh12:
	adrp	x8, _JZ_REG_LCD_VAT@GOTPAGE
Lloh13:
	ldr	x8, [x8, _JZ_REG_LCD_VAT@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
Lloh15:
	adrp	x8, _JZ_LCD_VAT_HT_OFFSET@GOTPAGE
Lloh16:
	ldr	x8, [x8, _JZ_LCD_VAT_HT_OFFSET@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	lsl	w8, w26, w8
Lloh18:
	adrp	x9, _JZ_LCD_VAT_VT_OFFSET@GOTPAGE
Lloh19:
	ldr	x9, [x9, _JZ_LCD_VAT_VT_OFFSET@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	lsl	w9, w25, w9
	orr	w2, w9, w8
	bl	_regmap_write
	ldr	w0, [x20]
Lloh21:
	adrp	x8, _JZ_REG_LCD_DAH@GOTPAGE
Lloh22:
	ldr	x8, [x8, _JZ_REG_LCD_DAH@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
Lloh24:
	adrp	x8, _JZ_LCD_DAH_HDS_OFFSET@GOTPAGE
Lloh25:
	ldr	x8, [x8, _JZ_LCD_DAH_HDS_OFFSET@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	lsl	w8, w27, w8
Lloh27:
	adrp	x9, _JZ_LCD_DAH_HDE_OFFSET@GOTPAGE
Lloh28:
	ldr	x9, [x9, _JZ_LCD_DAH_HDE_OFFSET@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	lsl	w9, w21, w9
	orr	w2, w9, w8
	bl	_regmap_write
	ldr	w0, [x20]
Lloh30:
	adrp	x8, _JZ_REG_LCD_DAV@GOTPAGE
Lloh31:
	ldr	x8, [x8, _JZ_REG_LCD_DAV@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
Lloh33:
	adrp	x8, _JZ_LCD_DAV_VDS_OFFSET@GOTPAGE
Lloh34:
	ldr	x8, [x8, _JZ_LCD_DAV_VDS_OFFSET@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
	lsl	w8, w24, w8
Lloh36:
	adrp	x9, _JZ_LCD_DAV_VDE_OFFSET@GOTPAGE
Lloh37:
	ldr	x9, [x9, _JZ_LCD_DAV_VDE_OFFSET@GOTPAGEOFF]
Lloh38:
	ldr	w9, [x9]
	lsl	w9, w23, w9
	orr	w2, w9, w8
	bl	_regmap_write
	ldr	x8, [x20, #8]
	cbz	x8, LBB0_2
; %bb.1:
	ldr	w0, [x20]
Lloh39:
	adrp	x8, _JZ_REG_LCD_PS@GOTPAGE
Lloh40:
	ldr	x8, [x8, _JZ_REG_LCD_PS@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	add	w8, w21, #1
	orr	w21, w8, w21, lsl #16
	mov	x2, x21
	bl	_regmap_write
	ldr	w0, [x20]
Lloh42:
	adrp	x8, _JZ_REG_LCD_CLS@GOTPAGE
Lloh43:
	ldr	x8, [x8, _JZ_REG_LCD_CLS@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x8]
	mov	x2, x21
	bl	_regmap_write
	ldr	w0, [x20]
Lloh45:
	adrp	x8, _JZ_REG_LCD_SPL@GOTPAGE
Lloh46:
	ldr	x8, [x8, _JZ_REG_LCD_SPL@GOTPAGEOFF]
Lloh47:
	ldr	w1, [x8]
	add	w8, w22, #1
	orr	w2, w8, w22, lsl #16
	bl	_regmap_write
	ldr	w0, [x20]
Lloh48:
	adrp	x8, _JZ_REG_LCD_REV@GOTPAGE
Lloh49:
	ldr	x8, [x8, _JZ_REG_LCD_REV@GOTPAGEOFF]
Lloh50:
	ldr	w1, [x8]
	ldr	w8, [x19, #24]
	lsl	w2, w8, #16
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_regmap_write
LBB0_2:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.cfi_endproc
                                        ; -- End function
	.comm	_JZ_REG_LCD_VSYNC,4,2           ; @JZ_REG_LCD_VSYNC
	.comm	_JZ_LCD_VSYNC_VPS_OFFSET,4,2    ; @JZ_LCD_VSYNC_VPS_OFFSET
	.comm	_JZ_LCD_VSYNC_VPE_OFFSET,4,2    ; @JZ_LCD_VSYNC_VPE_OFFSET
	.comm	_JZ_REG_LCD_HSYNC,4,2           ; @JZ_REG_LCD_HSYNC
	.comm	_JZ_LCD_HSYNC_HPS_OFFSET,4,2    ; @JZ_LCD_HSYNC_HPS_OFFSET
	.comm	_JZ_LCD_HSYNC_HPE_OFFSET,4,2    ; @JZ_LCD_HSYNC_HPE_OFFSET
	.comm	_JZ_REG_LCD_VAT,4,2             ; @JZ_REG_LCD_VAT
	.comm	_JZ_LCD_VAT_HT_OFFSET,4,2       ; @JZ_LCD_VAT_HT_OFFSET
	.comm	_JZ_LCD_VAT_VT_OFFSET,4,2       ; @JZ_LCD_VAT_VT_OFFSET
	.comm	_JZ_REG_LCD_DAH,4,2             ; @JZ_REG_LCD_DAH
	.comm	_JZ_LCD_DAH_HDS_OFFSET,4,2      ; @JZ_LCD_DAH_HDS_OFFSET
	.comm	_JZ_LCD_DAH_HDE_OFFSET,4,2      ; @JZ_LCD_DAH_HDE_OFFSET
	.comm	_JZ_REG_LCD_DAV,4,2             ; @JZ_REG_LCD_DAV
	.comm	_JZ_LCD_DAV_VDS_OFFSET,4,2      ; @JZ_LCD_DAV_VDS_OFFSET
	.comm	_JZ_LCD_DAV_VDE_OFFSET,4,2      ; @JZ_LCD_DAV_VDE_OFFSET
	.comm	_JZ_REG_LCD_PS,4,2              ; @JZ_REG_LCD_PS
	.comm	_JZ_REG_LCD_CLS,4,2             ; @JZ_REG_LCD_CLS
	.comm	_JZ_REG_LCD_SPL,4,2             ; @JZ_REG_LCD_SPL
	.comm	_JZ_REG_LCD_REV,4,2             ; @JZ_REG_LCD_REV
	.no_dead_strip	_ingenic_drm_crtc_update_timings
.subsections_via_symbols
