	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function nbio_v2_3_update_medium_grain_clock_gating
_nbio_v2_3_update_medium_grain_clock_gating: ## @nbio_v2_3_update_medium_grain_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %ebx
	movq	%rdi, %r14
	movq	_smnCPM_CONTROL@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32_PCIE
	testl	%ebx, %ebx
	je	LBB0_3
## %bb.1:
	movq	_AMD_CG_SUPPORT_BIF_MGCG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, (%r14)
	je	LBB0_3
## %bb.2:
	movq	_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK@GOTPCREL(%rip), %rcx
	movq	_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK@GOTPCREL(%rip), %rdx
	movq	_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK@GOTPCREL(%rip), %rdi
	movq	_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK@GOTPCREL(%rip), %rbx
	movq	_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK@GOTPCREL(%rip), %r8
	movq	_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK@GOTPCREL(%rip), %r9
	movl	(%rcx), %esi
	orl	%eax, %esi
	orl	(%rdx), %esi
	orl	(%rdi), %esi
	orl	(%rbx), %esi
	orl	(%r8), %esi
	orl	(%r9), %esi
	cmpl	%esi, %eax
	je	LBB0_5
LBB0_6:
	movl	(%r15), %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_PCIE                    ## TAILCALL
LBB0_3:
	movq	_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK@GOTPCREL(%rip), %rcx
	movq	_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	movq	_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	cmpl	%esi, %eax
	jne	LBB0_6
LBB0_5:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_smnCPM_CONTROL,4,2             ## @smnCPM_CONTROL
	.comm	_AMD_CG_SUPPORT_BIF_MGCG,4,2    ## @AMD_CG_SUPPORT_BIF_MGCG
	.comm	_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK,4,2 ## @CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK
	.comm	_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK,4,2 ## @CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK
	.comm	_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK,4,2 ## @CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK
	.comm	_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK,4,2 ## @CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK
	.comm	_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK,4,2 ## @CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK
	.comm	_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK,4,2 ## @CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK
	.no_dead_strip	_nbio_v2_3_update_medium_grain_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function nbio_v2_3_update_medium_grain_clock_gating
_nbio_v2_3_update_medium_grain_clock_gating: ; @nbio_v2_3_update_medium_grain_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x21, _smnCPM_CONTROL@GOTPAGE
Lloh1:
	ldr	x21, [x21, _smnCPM_CONTROL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32_PCIE
	cbz	w20, LBB0_4
; %bb.1:
	ldr	w8, [x19]
Lloh2:
	adrp	x9, _AMD_CG_SUPPORT_BIF_MGCG@GOTPAGE
Lloh3:
	ldr	x9, [x9, _AMD_CG_SUPPORT_BIF_MGCG@GOTPAGEOFF]
Lloh4:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_4
; %bb.2:
Lloh5:
	adrp	x8, _CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
Lloh8:
	adrp	x9, _CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK@GOTPAGE
Lloh9:
	ldr	x9, [x9, _CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
Lloh11:
	adrp	x10, _CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK@GOTPAGE
Lloh12:
	ldr	x10, [x10, _CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK@GOTPAGEOFF]
Lloh13:
	ldr	w10, [x10]
Lloh14:
	adrp	x11, _CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK@GOTPAGE
Lloh15:
	ldr	x11, [x11, _CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w11, [x11]
Lloh17:
	adrp	x12, _CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK@GOTPAGE
Lloh18:
	ldr	x12, [x12, _CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK@GOTPAGEOFF]
Lloh19:
	ldr	w12, [x12]
Lloh20:
	adrp	x13, _CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK@GOTPAGE
Lloh21:
	ldr	x13, [x13, _CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK@GOTPAGEOFF]
Lloh22:
	ldr	w13, [x13]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w1, w8, w13
	cmp	w0, w1
	b.eq	LBB0_5
LBB0_3:
	ldr	w0, [x21]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32_PCIE
LBB0_4:
Lloh23:
	adrp	x8, _CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK@GOTPAGE
Lloh24:
	ldr	x8, [x8, _CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
Lloh26:
	adrp	x9, _CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK@GOTPAGE
Lloh27:
	ldr	x9, [x9, _CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK@GOTPAGEOFF]
Lloh28:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh29:
	adrp	x9, _CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK@GOTPAGE
Lloh30:
	ldr	x9, [x9, _CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK@GOTPAGEOFF]
Lloh31:
	ldr	w9, [x9]
Lloh32:
	adrp	x10, _CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK@GOTPAGE
Lloh33:
	ldr	x10, [x10, _CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh34:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh35:
	adrp	x9, _CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK@GOTPAGE
Lloh36:
	ldr	x9, [x9, _CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK@GOTPAGEOFF]
Lloh37:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh38:
	adrp	x9, _CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK@GOTPAGE
Lloh39:
	ldr	x9, [x9, _CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w1, w0, w8
	cmp	w0, w1
	b.ne	LBB0_3
LBB0_5:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.cfi_endproc
                                        ; -- End function
	.comm	_smnCPM_CONTROL,4,2             ; @smnCPM_CONTROL
	.comm	_AMD_CG_SUPPORT_BIF_MGCG,4,2    ; @AMD_CG_SUPPORT_BIF_MGCG
	.comm	_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK,4,2 ; @CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK
	.comm	_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK,4,2 ; @CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK
	.comm	_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK,4,2 ; @CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK
	.comm	_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK,4,2 ; @CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK
	.comm	_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK,4,2 ; @CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK
	.comm	_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK,4,2 ; @CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK
	.no_dead_strip	_nbio_v2_3_update_medium_grain_clock_gating
.subsections_via_symbols
