	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function uvd_v6_0_sw_init
_uvd_v6_0_sw_init:                      ## @uvd_v6_0_sw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r13
	movq	_AMDGPU_IRQ_CLIENTID_LEGACY@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	_VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	8(%rdi), %rcx
	callq	_amdgpu_irq_add_id
	testl	%eax, %eax
	jne	LBB0_24
## %bb.1:
	movq	%r13, %rdi
	callq	_uvd_v6_0_enc_support
	testq	%rax, %rax
	je	LBB0_6
## %bb.2:
	cmpl	$0, (%r13)
	jle	LBB0_6
## %bb.3:
	xorl	%ebx, %ebx
	movq	_VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP@GOTPCREL(%rip), %r15
	.p2align	4, 0x90
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %esi
	movq	(%r15), %rdx
	addq	%rbx, %rdx
	movq	8(%r13), %rcx
	movq	%r13, %rdi
	callq	_amdgpu_irq_add_id
	testl	%eax, %eax
	jne	LBB0_24
## %bb.4:                               ##   in Loop: Header=BB0_5 Depth=1
	incq	%rbx
	movslq	(%r13), %rax
	cmpq	%rax, %rbx
	jl	LBB0_5
LBB0_6:
	movq	%r13, %rdi
	callq	_amdgpu_uvd_sw_init
	testl	%eax, %eax
	jne	LBB0_24
## %bb.7:
	movq	%r13, %rdi
	callq	_uvd_v6_0_enc_support
	testq	%rax, %rax
	jne	LBB0_17
## %bb.8:
	movl	(%r13), %esi
	movq	8(%r13), %rax
	testl	%esi, %esi
	jle	LBB0_16
## %bb.9:
	movq	8(%rax), %rdx
	leaq	-1(%rsi), %rdi
	movl	%esi, %ecx
	andl	$3, %ecx
	cmpq	$3, %rdi
	jae	LBB0_11
## %bb.10:
	xorl	%edi, %edi
	jmp	LBB0_13
LBB0_11:
	andl	$-4, %esi
	leaq	56(%rdx), %rbx
	xorl	%edi, %edi
	.p2align	4, 0x90
LBB0_12:                                ## =>This Inner Loop Header: Depth=1
	movq	$0, -48(%rbx)
	movq	$0, -32(%rbx)
	movq	$0, -16(%rbx)
	movq	$0, (%rbx)
	addq	$4, %rdi
	addq	$64, %rbx
	cmpq	%rdi, %rsi
	jne	LBB0_12
LBB0_13:
	testq	%rcx, %rcx
	je	LBB0_16
## %bb.14:
	shlq	$4, %rdi
	addq	%rdi, %rdx
	addq	$8, %rdx
	shlq	$4, %rcx
	xorl	%esi, %esi
	.p2align	4, 0x90
LBB0_15:                                ## =>This Inner Loop Header: Depth=1
	movq	$0, (%rdx,%rsi)
	addq	$16, %rsi
	cmpq	%rsi, %rcx
	jne	LBB0_15
LBB0_16:
	movl	$1, (%rax)
	movl	$0, (%r13)
	leaq	L_.str(%rip), %rdi
	callq	_DRM_INFO
LBB0_17:
	movq	8(%r13), %r14
	movl	16(%r14), %edi
	addq	$16, %r14
	leaq	L_.str.1(%rip), %rsi
	xorl	%eax, %eax
	callq	_sprintf
	movq	8(%r13), %rcx
	movq	%r13, %rdi
	movq	%r14, %rsi
	movl	$512, %edx                      ## imm = 0x200
	xorl	%r8d, %r8d
	callq	_amdgpu_ring_init
	testl	%eax, %eax
	jne	LBB0_24
## %bb.18:
	movq	%r13, %rdi
	callq	_amdgpu_uvd_resume
	testl	%eax, %eax
	je	LBB0_19
LBB0_24:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_19:
	movq	%r13, %rdi
	callq	_uvd_v6_0_enc_support
	testq	%rax, %rax
	je	LBB0_25
## %bb.20:
	cmpl	$0, (%r13)
	jle	LBB0_25
## %bb.21:
	leaq	L_.str.2(%rip), %r14
	xorl	%ebx, %ebx
	xorl	%r15d, %r15d
LBB0_23:                                ## =>This Inner Loop Header: Depth=1
	movq	8(%r13), %rax
	movq	8(%rax), %r12
	movl	(%r12,%rbx), %edi
	addq	%rbx, %r12
	movq	%r14, %rsi
	movl	%r15d, %edx
	xorl	%eax, %eax
	callq	_sprintf
	movq	8(%r13), %rcx
	movq	%r13, %rdi
	movq	%r12, %rsi
	movl	$512, %edx                      ## imm = 0x200
	xorl	%r8d, %r8d
	callq	_amdgpu_ring_init
	testl	%eax, %eax
	jne	LBB0_24
## %bb.22:                              ##   in Loop: Header=BB0_23 Depth=1
	incq	%r15
	movslq	(%r13), %rax
	addq	$16, %rbx
	cmpq	%rax, %r15
	jl	LBB0_23
LBB0_25:
	movq	%r13, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_uvd_entity_init         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_IRQ_CLIENTID_LEGACY,4,2 ## @AMDGPU_IRQ_CLIENTID_LEGACY
	.comm	_VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE,8,3 ## @VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE
	.comm	_VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP,8,3 ## @VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"UVD ENC is disabled\n"

L_.str.1:                               ## @.str.1
	.asciz	"uvd"

L_.str.2:                               ## @.str.2
	.asciz	"uvd_enc%d"

	.no_dead_strip	_uvd_v6_0_sw_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function uvd_v6_0_sw_init
_uvd_v6_0_sw_init:                      ; @uvd_v6_0_sw_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x20, _AMDGPU_IRQ_CLIENTID_LEGACY@GOTPAGE
Lloh1:
	ldr	x20, [x20, _AMDGPU_IRQ_CLIENTID_LEGACY@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh2:
	adrp	x8, _VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE@GOTPAGE
Lloh3:
	ldr	x8, [x8, _VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE@GOTPAGEOFF]
Lloh4:
	ldr	x2, [x8]
	ldr	x3, [x0, #8]
	bl	_amdgpu_irq_add_id
	cbnz	w0, LBB0_19
; %bb.1:
	mov	x0, x19
	bl	_uvd_v6_0_enc_support
	cbz	x0, LBB0_6
; %bb.2:
	ldr	w8, [x19]
	cmp	w8, #1
	b.lt	LBB0_6
; %bb.3:
	mov	x21, #0
Lloh5:
	adrp	x22, _VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP@GOTPAGE
Lloh6:
	ldr	x22, [x22, _VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP@GOTPAGEOFF]
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x20]
	ldr	x8, [x22]
	add	x2, x21, x8
	ldr	x3, [x19, #8]
	mov	x0, x19
	bl	_amdgpu_irq_add_id
	cbnz	w0, LBB0_19
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	add	x21, x21, #1
	ldrsw	x8, [x19]
	cmp	x21, x8
	b.lt	LBB0_4
LBB0_6:
	mov	x0, x19
	bl	_amdgpu_uvd_sw_init
	cbnz	w0, LBB0_19
; %bb.7:
	mov	x0, x19
	bl	_uvd_v6_0_enc_support
	cbnz	x0, LBB0_17
; %bb.8:
	ldr	w9, [x19]
	ldr	x8, [x19, #8]
	cmp	w9, #1
	b.lt	LBB0_16
; %bb.9:
	ldr	x10, [x8, #8]
	cmp	w9, #4
	b.hs	LBB0_11
; %bb.10:
	mov	x11, #0
	b	LBB0_14
LBB0_11:
	and	x11, x9, #0xfffffffc
	add	x12, x10, #40
	mov	x13, x11
LBB0_12:                                ; =>This Inner Loop Header: Depth=1
	stur	xzr, [x12, #-32]
	stur	xzr, [x12, #-16]
	str	xzr, [x12]
	str	xzr, [x12, #16]
	add	x12, x12, #64
	subs	x13, x13, #4
	b.ne	LBB0_12
; %bb.13:
	cmp	x11, x9
	b.eq	LBB0_16
LBB0_14:
	add	x10, x10, x11, lsl #4
	add	x10, x10, #8
	sub	x9, x9, x11
LBB0_15:                                ; =>This Inner Loop Header: Depth=1
	str	xzr, [x10], #16
	subs	x9, x9, #1
	b.ne	LBB0_15
LBB0_16:
	mov	w9, #1
	str	w9, [x8]
	str	wzr, [x19]
Lloh7:
	adrp	x0, l_.str@PAGE
Lloh8:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_INFO
LBB0_17:
	ldr	x20, [x19, #8]
	ldr	w0, [x20, #16]!
Lloh9:
	adrp	x1, l_.str.1@PAGE
Lloh10:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_sprintf
	ldr	x3, [x19, #8]
	mov	x0, x19
	mov	x1, x20
	mov	w2, #512
	mov	w4, #0
	bl	_amdgpu_ring_init
	cbnz	w0, LBB0_19
; %bb.18:
	mov	x0, x19
	bl	_amdgpu_uvd_resume
	cbz	w0, LBB0_20
LBB0_19:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
LBB0_20:
	mov	x0, x19
	bl	_uvd_v6_0_enc_support
	cbz	x0, LBB0_25
; %bb.21:
	ldr	w8, [x19]
	cmp	w8, #1
	b.lt	LBB0_25
; %bb.22:
	mov	x22, #0
	mov	x23, #0
Lloh11:
	adrp	x20, l_.str.2@PAGE
Lloh12:
	add	x20, x20, l_.str.2@PAGEOFF
LBB0_23:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	add	x21, x8, x22
	ldr	w0, [x21]
	str	x23, [sp]
	mov	x1, x20
	bl	_sprintf
	ldr	x3, [x19, #8]
	mov	x0, x19
	mov	x1, x21
	mov	w2, #512
	mov	w4, #0
	bl	_amdgpu_ring_init
	cbnz	w0, LBB0_19
; %bb.24:                               ;   in Loop: Header=BB0_23 Depth=1
	add	x23, x23, #1
	ldrsw	x8, [x19]
	add	x22, x22, #16
	cmp	x23, x8
	b.lt	LBB0_23
LBB0_25:
	mov	x0, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	b	_amdgpu_uvd_entity_init
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpAdd	Lloh7, Lloh8
	.loh AdrpAdd	Lloh9, Lloh10
	.loh AdrpAdd	Lloh11, Lloh12
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_IRQ_CLIENTID_LEGACY,4,2 ; @AMDGPU_IRQ_CLIENTID_LEGACY
	.comm	_VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE,8,3 ; @VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE
	.comm	_VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP,8,3 ; @VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"UVD ENC is disabled\n"

l_.str.1:                               ; @.str.1
	.asciz	"uvd"

l_.str.2:                               ; @.str.2
	.asciz	"uvd_enc%d"

	.no_dead_strip	_uvd_v6_0_sw_init
.subsections_via_symbols
