	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v8_0_update_medium_grain_clock_gating
_gfx_v8_0_update_medium_grain_clock_gating: ## @gfx_v8_0_update_medium_grain_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %ebx
	movq	%rdi, %r14
	callq	_amdgpu_gfx_rlc_enter_safe_mode
	testl	%ebx, %ebx
	je	LBB0_17
## %bb.1:
	movl	(%r14), %eax
	movq	_AMD_CG_SUPPORT_GFX_MGCG@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_17
## %bb.2:
	movq	_AMD_CG_SUPPORT_GFX_MGLS@GOTPCREL(%rip), %r15
	testl	%eax, (%r15)
	je	LBB0_7
## %bb.3:
	movq	_AMD_CG_SUPPORT_GFX_RLC_LS@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_5
## %bb.4:
	movq	_RLC_MEM_SLP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RLC_MEM_LS_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %edx
	callq	_WREG32_FIELD
	movl	(%r14), %eax
LBB0_5:
	movq	_AMD_CG_SUPPORT_GFX_CP_LS@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_7
## %bb.6:
	movq	_CP_MEM_SLP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_CP_MEM_LS_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %edx
	callq	_WREG32_FIELD
LBB0_7:
	movq	_mmRLC_CGTT_MGCG_OVERRIDE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_RLC_CGTT_MGCG_OVERRIDE__CPF_MASK@GOTPCREL(%rip), %rcx
	movq	_RLC_CGTT_MGCG_OVERRIDE__RLC_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rcx
	movq	_RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %esi
	movl	(%rcx), %edx
	xorl	%ecx, %ecx
	testl	%edx, 4(%r14)
	jne	LBB0_9
## %bb.8:
	movq	_RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_9:
	orl	%ecx, %esi
	notl	%esi
	andl	%eax, %esi
	cmpl	%esi, %eax
	je	LBB0_11
## %bb.10:
	movl	(%rbx), %edi
	callq	_WREG32
LBB0_11:
	movq	%r14, %rdi
	callq	_gfx_v8_0_wait_for_rlc_serdes
	movq	_BPM_REG_MGCG_OVERRIDE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_CLE_BPM_SERDES_CMD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_gfx_v8_0_send_serdes_cmd
	movq	_AMD_CG_SUPPORT_GFX_CGTS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r14)
	je	LBB0_26
## %bb.12:
	movq	_mmCGTS_SM_CTRL_REG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_CGTS_SM_CTRL_REG__SM_MODE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	_CGTS_SM_CTRL_REG__SM_MODE__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %esi
	shll	%cl, %esi
	orl	%edx, %esi
	movq	_CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_CGTS_SM_CTRL_REG__OVERRIDE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%esi, %edx
	movl	(%r14), %ecx
	testl	%ecx, (%r15)
	je	LBB0_15
## %bb.13:
	movq	_AMD_CG_SUPPORT_GFX_CGTS_LS@GOTPCREL(%rip), %rsi
	testl	%ecx, (%rsi)
	je	LBB0_15
## %bb.14:
	movq	_CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%ecx, %edx
LBB0_15:
	movq	_CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK@GOTPCREL(%rip), %rdi
	movq	_CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$150, %esi
	shll	%cl, %esi
	orl	(%rdi), %edx
	orl	%edx, %esi
	cmpl	%esi, %eax
	je	LBB0_26
## %bb.16:
	movl	(%rbx), %edi
	callq	_WREG32
	jmp	LBB0_26
LBB0_17:
	movq	_mmRLC_CGTT_MGCG_OVERRIDE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_RLC_CGTT_MGCG_OVERRIDE__CPF_MASK@GOTPCREL(%rip), %rcx
	movq	_RLC_CGTT_MGCG_OVERRIDE__RLC_MASK@GOTPCREL(%rip), %rdx
	movq	_RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK@GOTPCREL(%rip), %rdi
	movl	(%rcx), %esi
	orl	%eax, %esi
	orl	(%rdx), %esi
	orl	(%rdi), %esi
	movq	_RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	cmpl	%esi, %eax
	je	LBB0_19
## %bb.18:
	movl	(%rbx), %edi
	callq	_WREG32
LBB0_19:
	movq	_mmRLC_MEM_SLP_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%eax, %ecx
	je	LBB0_21
## %bb.20:
	notl	%ecx
	andl	%ecx, %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
LBB0_21:
	movq	_mmCP_MEM_SLP_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%eax, %ecx
	je	LBB0_23
## %bb.22:
	notl	%ecx
	andl	%ecx, %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
LBB0_23:
	movq	_mmCGTS_SM_CTRL_REG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_CGTS_SM_CTRL_REG__OVERRIDE_MASK@GOTPCREL(%rip), %rcx
	movq	_CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK@GOTPCREL(%rip), %rdx
	movl	(%rcx), %esi
	orl	%eax, %esi
	orl	(%rdx), %esi
	cmpl	%esi, %eax
	je	LBB0_25
## %bb.24:
	movl	(%rbx), %edi
	callq	_WREG32
LBB0_25:
	movq	%r14, %rdi
	callq	_gfx_v8_0_wait_for_rlc_serdes
	movq	_BPM_REG_MGCG_OVERRIDE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SET_BPM_SERDES_CMD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_gfx_v8_0_send_serdes_cmd
LBB0_26:
	movl	$50, %edi
	callq	_udelay
	movq	%r14, %rdi
	callq	_gfx_v8_0_wait_for_rlc_serdes
	movq	%r14, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_gfx_rlc_exit_safe_mode  ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_CG_SUPPORT_GFX_MGCG,4,2    ## @AMD_CG_SUPPORT_GFX_MGCG
	.comm	_AMD_CG_SUPPORT_GFX_MGLS,4,2    ## @AMD_CG_SUPPORT_GFX_MGLS
	.comm	_AMD_CG_SUPPORT_GFX_RLC_LS,4,2  ## @AMD_CG_SUPPORT_GFX_RLC_LS
	.comm	_RLC_MEM_SLP_CNTL,4,2           ## @RLC_MEM_SLP_CNTL
	.comm	_RLC_MEM_LS_EN,4,2              ## @RLC_MEM_LS_EN
	.comm	_AMD_CG_SUPPORT_GFX_CP_LS,4,2   ## @AMD_CG_SUPPORT_GFX_CP_LS
	.comm	_CP_MEM_SLP_CNTL,4,2            ## @CP_MEM_SLP_CNTL
	.comm	_CP_MEM_LS_EN,4,2               ## @CP_MEM_LS_EN
	.comm	_mmRLC_CGTT_MGCG_OVERRIDE,4,2   ## @mmRLC_CGTT_MGCG_OVERRIDE
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_RLC_CGTT_MGCG_OVERRIDE__CPF_MASK,4,2 ## @RLC_CGTT_MGCG_OVERRIDE__CPF_MASK
	.comm	_RLC_CGTT_MGCG_OVERRIDE__RLC_MASK,4,2 ## @RLC_CGTT_MGCG_OVERRIDE__RLC_MASK
	.comm	_RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK,4,2 ## @RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK
	.comm	_RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK,4,2 ## @RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK
	.comm	_BPM_REG_MGCG_OVERRIDE,4,2      ## @BPM_REG_MGCG_OVERRIDE
	.comm	_CLE_BPM_SERDES_CMD,4,2         ## @CLE_BPM_SERDES_CMD
	.comm	_AMD_CG_SUPPORT_GFX_CGTS,4,2    ## @AMD_CG_SUPPORT_GFX_CGTS
	.comm	_mmCGTS_SM_CTRL_REG,4,2         ## @mmCGTS_SM_CTRL_REG
	.comm	_CGTS_SM_CTRL_REG__SM_MODE_MASK,4,2 ## @CGTS_SM_CTRL_REG__SM_MODE_MASK
	.comm	_CGTS_SM_CTRL_REG__SM_MODE__SHIFT,4,2 ## @CGTS_SM_CTRL_REG__SM_MODE__SHIFT
	.comm	_CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK,4,2 ## @CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK
	.comm	_CGTS_SM_CTRL_REG__OVERRIDE_MASK,4,2 ## @CGTS_SM_CTRL_REG__OVERRIDE_MASK
	.comm	_AMD_CG_SUPPORT_GFX_CGTS_LS,4,2 ## @AMD_CG_SUPPORT_GFX_CGTS_LS
	.comm	_CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK,4,2 ## @CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK
	.comm	_CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK,4,2 ## @CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK
	.comm	_CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT,4,2 ## @CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT
	.comm	_mmRLC_MEM_SLP_CNTL,4,2         ## @mmRLC_MEM_SLP_CNTL
	.comm	_RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK,4,2 ## @RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK
	.comm	_mmCP_MEM_SLP_CNTL,4,2          ## @mmCP_MEM_SLP_CNTL
	.comm	_CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK,4,2 ## @CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK
	.comm	_SET_BPM_SERDES_CMD,4,2         ## @SET_BPM_SERDES_CMD
	.no_dead_strip	_gfx_v8_0_update_medium_grain_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v8_0_update_medium_grain_clock_gating
_gfx_v8_0_update_medium_grain_clock_gating: ; @gfx_v8_0_update_medium_grain_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	mov	x19, x0
	bl	_amdgpu_gfx_rlc_enter_safe_mode
	cbz	w20, LBB0_15
; %bb.1:
	ldr	w8, [x19]
Lloh0:
	adrp	x9, _AMD_CG_SUPPORT_GFX_MGCG@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_CG_SUPPORT_GFX_MGCG@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_15
; %bb.2:
Lloh3:
	adrp	x20, _AMD_CG_SUPPORT_GFX_MGLS@GOTPAGE
Lloh4:
	ldr	x20, [x20, _AMD_CG_SUPPORT_GFX_MGLS@GOTPAGEOFF]
	ldr	w9, [x20]
	tst	w9, w8
	b.eq	LBB0_7
; %bb.3:
Lloh5:
	adrp	x9, _AMD_CG_SUPPORT_GFX_RLC_LS@GOTPAGE
Lloh6:
	ldr	x9, [x9, _AMD_CG_SUPPORT_GFX_RLC_LS@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_5
; %bb.4:
Lloh8:
	adrp	x8, _RLC_MEM_SLP_CNTL@GOTPAGE
Lloh9:
	ldr	x8, [x8, _RLC_MEM_SLP_CNTL@GOTPAGEOFF]
Lloh10:
	ldr	w0, [x8]
Lloh11:
	adrp	x8, _RLC_MEM_LS_EN@GOTPAGE
Lloh12:
	ldr	x8, [x8, _RLC_MEM_LS_EN@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
	mov	w2, #1
	bl	_WREG32_FIELD
	ldr	w8, [x19]
LBB0_5:
Lloh14:
	adrp	x9, _AMD_CG_SUPPORT_GFX_CP_LS@GOTPAGE
Lloh15:
	ldr	x9, [x9, _AMD_CG_SUPPORT_GFX_CP_LS@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_7
; %bb.6:
Lloh17:
	adrp	x8, _CP_MEM_SLP_CNTL@GOTPAGE
Lloh18:
	ldr	x8, [x8, _CP_MEM_SLP_CNTL@GOTPAGEOFF]
Lloh19:
	ldr	w0, [x8]
Lloh20:
	adrp	x8, _CP_MEM_LS_EN@GOTPAGE
Lloh21:
	ldr	x8, [x8, _CP_MEM_LS_EN@GOTPAGEOFF]
Lloh22:
	ldr	w1, [x8]
	mov	w2, #1
	bl	_WREG32_FIELD
LBB0_7:
Lloh23:
	adrp	x21, _mmRLC_CGTT_MGCG_OVERRIDE@GOTPAGE
Lloh24:
	ldr	x21, [x21, _mmRLC_CGTT_MGCG_OVERRIDE@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
	ldr	w8, [x19, #4]
Lloh25:
	adrp	x9, _AMD_IS_APU@GOTPAGE
Lloh26:
	ldr	x9, [x9, _AMD_IS_APU@GOTPAGEOFF]
Lloh27:
	adrp	x10, _RLC_CGTT_MGCG_OVERRIDE__CPF_MASK@GOTPAGE
Lloh28:
	ldr	x10, [x10, _RLC_CGTT_MGCG_OVERRIDE__CPF_MASK@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
Lloh30:
	ldr	w10, [x10]
Lloh31:
	adrp	x11, _RLC_CGTT_MGCG_OVERRIDE__RLC_MASK@GOTPAGE
Lloh32:
	ldr	x11, [x11, _RLC_CGTT_MGCG_OVERRIDE__RLC_MASK@GOTPAGEOFF]
Lloh33:
	ldr	w11, [x11]
	orr	w10, w11, w10
Lloh34:
	adrp	x11, _RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK@GOTPAGE
Lloh35:
	ldr	x11, [x11, _RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK@GOTPAGEOFF]
Lloh36:
	ldr	w11, [x11]
	orr	w10, w10, w11
Lloh37:
	adrp	x11, _RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK@GOTPAGE
Lloh38:
	ldr	x11, [x11, _RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK@GOTPAGEOFF]
Lloh39:
	ldr	w11, [x11]
	tst	w9, w8
	csel	w8, w11, wzr, eq
	orr	w8, w10, w8
	bic	w1, w0, w8
	cmp	w0, w1
	b.eq	LBB0_9
; %bb.8:
	ldr	w0, [x21]
	bl	_WREG32
LBB0_9:
	mov	x0, x19
	bl	_gfx_v8_0_wait_for_rlc_serdes
Lloh40:
	adrp	x8, _BPM_REG_MGCG_OVERRIDE@GOTPAGE
Lloh41:
	ldr	x8, [x8, _BPM_REG_MGCG_OVERRIDE@GOTPAGEOFF]
Lloh42:
	ldr	w1, [x8]
Lloh43:
	adrp	x8, _CLE_BPM_SERDES_CMD@GOTPAGE
Lloh44:
	ldr	x8, [x8, _CLE_BPM_SERDES_CMD@GOTPAGEOFF]
Lloh45:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_gfx_v8_0_send_serdes_cmd
	ldr	w8, [x19]
Lloh46:
	adrp	x9, _AMD_CG_SUPPORT_GFX_CGTS@GOTPAGE
Lloh47:
	ldr	x9, [x9, _AMD_CG_SUPPORT_GFX_CGTS@GOTPAGEOFF]
Lloh48:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_24
; %bb.10:
Lloh49:
	adrp	x21, _mmCGTS_SM_CTRL_REG@GOTPAGE
Lloh50:
	ldr	x21, [x21, _mmCGTS_SM_CTRL_REG@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
Lloh51:
	adrp	x8, _CGTS_SM_CTRL_REG__SM_MODE_MASK@GOTPAGE
Lloh52:
	ldr	x8, [x8, _CGTS_SM_CTRL_REG__SM_MODE_MASK@GOTPAGEOFF]
Lloh53:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh54:
	adrp	x9, _CGTS_SM_CTRL_REG__SM_MODE__SHIFT@GOTPAGE
Lloh55:
	ldr	x9, [x9, _CGTS_SM_CTRL_REG__SM_MODE__SHIFT@GOTPAGEOFF]
Lloh56:
	ldr	w9, [x9]
	mov	w10, #2
	lsl	w9, w10, w9
	orr	w8, w9, w8
Lloh57:
	adrp	x9, _CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK@GOTPAGE
Lloh58:
	ldr	x9, [x9, _CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK@GOTPAGEOFF]
Lloh59:
	ldr	w9, [x9]
Lloh60:
	adrp	x10, _CGTS_SM_CTRL_REG__OVERRIDE_MASK@GOTPAGE
Lloh61:
	ldr	x10, [x10, _CGTS_SM_CTRL_REG__OVERRIDE_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh62:
	ldr	w9, [x10]
	bic	w8, w8, w9
	ldr	w9, [x19]
	ldr	w10, [x20]
	tst	w10, w9
	b.eq	LBB0_13
; %bb.11:
Lloh63:
	adrp	x10, _AMD_CG_SUPPORT_GFX_CGTS_LS@GOTPAGE
Lloh64:
	ldr	x10, [x10, _AMD_CG_SUPPORT_GFX_CGTS_LS@GOTPAGEOFF]
Lloh65:
	ldr	w10, [x10]
	tst	w10, w9
	b.eq	LBB0_13
; %bb.12:
Lloh66:
	adrp	x9, _CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK@GOTPAGE
Lloh67:
	ldr	x9, [x9, _CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK@GOTPAGEOFF]
Lloh68:
	ldr	w9, [x9]
	bic	w8, w8, w9
LBB0_13:
Lloh69:
	adrp	x9, _CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK@GOTPAGE
Lloh70:
	ldr	x9, [x9, _CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK@GOTPAGEOFF]
Lloh71:
	ldr	w9, [x9]
Lloh72:
	adrp	x10, _CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT@GOTPAGE
Lloh73:
	ldr	x10, [x10, _CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh74:
	ldr	w9, [x10]
	mov	w10, #150
	lsl	w9, w10, w9
	orr	w1, w8, w9
	cmp	w0, w1
	b.eq	LBB0_24
; %bb.14:
	ldr	w0, [x21]
	bl	_WREG32
	b	LBB0_24
LBB0_15:
Lloh75:
	adrp	x20, _mmRLC_CGTT_MGCG_OVERRIDE@GOTPAGE
Lloh76:
	ldr	x20, [x20, _mmRLC_CGTT_MGCG_OVERRIDE@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh77:
	adrp	x8, _RLC_CGTT_MGCG_OVERRIDE__CPF_MASK@GOTPAGE
Lloh78:
	ldr	x8, [x8, _RLC_CGTT_MGCG_OVERRIDE__CPF_MASK@GOTPAGEOFF]
Lloh79:
	ldr	w8, [x8]
Lloh80:
	adrp	x9, _RLC_CGTT_MGCG_OVERRIDE__RLC_MASK@GOTPAGE
Lloh81:
	ldr	x9, [x9, _RLC_CGTT_MGCG_OVERRIDE__RLC_MASK@GOTPAGEOFF]
Lloh82:
	ldr	w9, [x9]
Lloh83:
	adrp	x10, _RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK@GOTPAGE
Lloh84:
	ldr	x10, [x10, _RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK@GOTPAGEOFF]
Lloh85:
	ldr	w10, [x10]
Lloh86:
	adrp	x11, _RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK@GOTPAGE
Lloh87:
	ldr	x11, [x11, _RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK@GOTPAGEOFF]
Lloh88:
	ldr	w11, [x11]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w1, w8, w11
	cmp	w0, w1
	b.eq	LBB0_17
; %bb.16:
	ldr	w0, [x20]
	bl	_WREG32
LBB0_17:
Lloh89:
	adrp	x20, _mmRLC_MEM_SLP_CNTL@GOTPAGE
Lloh90:
	ldr	x20, [x20, _mmRLC_MEM_SLP_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh91:
	adrp	x8, _RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK@GOTPAGE
Lloh92:
	ldr	x8, [x8, _RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh93:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_19
; %bb.18:
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32
LBB0_19:
Lloh94:
	adrp	x20, _mmCP_MEM_SLP_CNTL@GOTPAGE
Lloh95:
	ldr	x20, [x20, _mmCP_MEM_SLP_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh96:
	adrp	x8, _CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPAGE
Lloh97:
	ldr	x8, [x8, _CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh98:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_21
; %bb.20:
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32
LBB0_21:
Lloh99:
	adrp	x20, _mmCGTS_SM_CTRL_REG@GOTPAGE
Lloh100:
	ldr	x20, [x20, _mmCGTS_SM_CTRL_REG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh101:
	adrp	x8, _CGTS_SM_CTRL_REG__OVERRIDE_MASK@GOTPAGE
Lloh102:
	ldr	x8, [x8, _CGTS_SM_CTRL_REG__OVERRIDE_MASK@GOTPAGEOFF]
Lloh103:
	ldr	w8, [x8]
Lloh104:
	adrp	x9, _CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK@GOTPAGE
Lloh105:
	ldr	x9, [x9, _CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK@GOTPAGEOFF]
Lloh106:
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w1, w8, w9
	cmp	w0, w1
	b.eq	LBB0_23
; %bb.22:
	ldr	w0, [x20]
	bl	_WREG32
LBB0_23:
	mov	x0, x19
	bl	_gfx_v8_0_wait_for_rlc_serdes
Lloh107:
	adrp	x8, _BPM_REG_MGCG_OVERRIDE@GOTPAGE
Lloh108:
	ldr	x8, [x8, _BPM_REG_MGCG_OVERRIDE@GOTPAGEOFF]
Lloh109:
	ldr	w1, [x8]
Lloh110:
	adrp	x8, _SET_BPM_SERDES_CMD@GOTPAGE
Lloh111:
	ldr	x8, [x8, _SET_BPM_SERDES_CMD@GOTPAGEOFF]
Lloh112:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_gfx_v8_0_send_serdes_cmd
LBB0_24:
	mov	w0, #50
	bl	_udelay
	mov	x0, x19
	bl	_gfx_v8_0_wait_for_rlc_serdes
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_amdgpu_gfx_rlc_exit_safe_mode
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh29
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGot	Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGot	Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGot	Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGot	Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_CG_SUPPORT_GFX_MGCG,4,2    ; @AMD_CG_SUPPORT_GFX_MGCG
	.comm	_AMD_CG_SUPPORT_GFX_MGLS,4,2    ; @AMD_CG_SUPPORT_GFX_MGLS
	.comm	_AMD_CG_SUPPORT_GFX_RLC_LS,4,2  ; @AMD_CG_SUPPORT_GFX_RLC_LS
	.comm	_RLC_MEM_SLP_CNTL,4,2           ; @RLC_MEM_SLP_CNTL
	.comm	_RLC_MEM_LS_EN,4,2              ; @RLC_MEM_LS_EN
	.comm	_AMD_CG_SUPPORT_GFX_CP_LS,4,2   ; @AMD_CG_SUPPORT_GFX_CP_LS
	.comm	_CP_MEM_SLP_CNTL,4,2            ; @CP_MEM_SLP_CNTL
	.comm	_CP_MEM_LS_EN,4,2               ; @CP_MEM_LS_EN
	.comm	_mmRLC_CGTT_MGCG_OVERRIDE,4,2   ; @mmRLC_CGTT_MGCG_OVERRIDE
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_RLC_CGTT_MGCG_OVERRIDE__CPF_MASK,4,2 ; @RLC_CGTT_MGCG_OVERRIDE__CPF_MASK
	.comm	_RLC_CGTT_MGCG_OVERRIDE__RLC_MASK,4,2 ; @RLC_CGTT_MGCG_OVERRIDE__RLC_MASK
	.comm	_RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK,4,2 ; @RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK
	.comm	_RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK,4,2 ; @RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK
	.comm	_BPM_REG_MGCG_OVERRIDE,4,2      ; @BPM_REG_MGCG_OVERRIDE
	.comm	_CLE_BPM_SERDES_CMD,4,2         ; @CLE_BPM_SERDES_CMD
	.comm	_AMD_CG_SUPPORT_GFX_CGTS,4,2    ; @AMD_CG_SUPPORT_GFX_CGTS
	.comm	_mmCGTS_SM_CTRL_REG,4,2         ; @mmCGTS_SM_CTRL_REG
	.comm	_CGTS_SM_CTRL_REG__SM_MODE_MASK,4,2 ; @CGTS_SM_CTRL_REG__SM_MODE_MASK
	.comm	_CGTS_SM_CTRL_REG__SM_MODE__SHIFT,4,2 ; @CGTS_SM_CTRL_REG__SM_MODE__SHIFT
	.comm	_CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK,4,2 ; @CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK
	.comm	_CGTS_SM_CTRL_REG__OVERRIDE_MASK,4,2 ; @CGTS_SM_CTRL_REG__OVERRIDE_MASK
	.comm	_AMD_CG_SUPPORT_GFX_CGTS_LS,4,2 ; @AMD_CG_SUPPORT_GFX_CGTS_LS
	.comm	_CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK,4,2 ; @CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK
	.comm	_CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK,4,2 ; @CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK
	.comm	_CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT,4,2 ; @CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT
	.comm	_mmRLC_MEM_SLP_CNTL,4,2         ; @mmRLC_MEM_SLP_CNTL
	.comm	_RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK,4,2 ; @RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK
	.comm	_mmCP_MEM_SLP_CNTL,4,2          ; @mmCP_MEM_SLP_CNTL
	.comm	_CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK,4,2 ; @CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK
	.comm	_SET_BPM_SERDES_CMD,4,2         ; @SET_BPM_SERDES_CMD
	.no_dead_strip	_gfx_v8_0_update_medium_grain_clock_gating
.subsections_via_symbols
