	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function a3xx_hw_init
_a3xx_hw_init:                          ## @a3xx_hw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r13
	callq	_to_adreno_gpu
	movq	%rax, %r14
	movq	%rax, %rdi
	callq	_to_a3xx_gpu
	movq	%rax, %r15
	movl	(%r13), %esi
	leaq	L_.str(%rip), %rdi
	callq	_DBG
	movq	%r14, %rdi
	callq	_adreno_is_a305
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	_REG_A3XX_VBIF_IN_RD_LIM_CONF0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$269488144, %edx                ## imm = 0x10101010
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_IN_RD_LIM_CONF1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$269488144, %edx                ## imm = 0x10101010
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_OUT_RD_LIM_CONF0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$269488144, %edx                ## imm = 0x10101010
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_OUT_WR_LIM_CONF0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$269488144, %edx                ## imm = 0x10101010
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_DDR_OUT_MAX_BURST@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$771, %edx                      ## imm = 0x303
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_IN_WR_LIM_CONF0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$269488144, %edx                ## imm = 0x10101010
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_IN_WR_LIM_CONF1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$269488144, %edx                ## imm = 0x10101010
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_GATE_OFF_WRREQ_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$255, %edx
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_ARB_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$48, %edx
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_OUT_AXI_AOOO_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$60, %edx
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_OUT_AXI_AOOO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$3932220, %edx                  ## imm = 0x3C003C
	callq	_gpu_write
	jmp	LBB0_11
LBB0_2:
	movq	%r14, %rdi
	callq	_adreno_is_a306
	testq	%rax, %rax
	je	LBB0_4
## %bb.3:
	movq	_REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$3, %edx
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_OUT_RD_LIM_CONF0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$10, %edx
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_OUT_WR_LIM_CONF0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$10, %edx
	callq	_gpu_write
	jmp	LBB0_11
LBB0_4:
	movq	%r14, %rdi
	callq	_adreno_is_a320
	testq	%rax, %rax
	je	LBB0_6
## %bb.5:
	movq	_REG_A3XX_VBIF_IN_RD_LIM_CONF0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$269488144, %edx                ## imm = 0x10101010
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_IN_RD_LIM_CONF1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$269488144, %edx                ## imm = 0x10101010
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_OUT_RD_LIM_CONF0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$269488144, %edx                ## imm = 0x10101010
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_OUT_WR_LIM_CONF0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$269488144, %edx                ## imm = 0x10101010
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_DDR_OUT_MAX_BURST@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$771, %edx                      ## imm = 0x303
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_IN_WR_LIM_CONF0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$269488144, %edx                ## imm = 0x10101010
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_IN_WR_LIM_CONF1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$269488144, %edx                ## imm = 0x10101010
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_GATE_OFF_WRREQ_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$255, %edx
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_ARB_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$48, %edx
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_OUT_AXI_AOOO_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$60, %edx
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_OUT_AXI_AOOO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$3932220, %edx                  ## imm = 0x3C003C
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_ABIT_SORT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$255, %edx
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_ABIT_SORT_CONF@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$164, %edx
	callq	_gpu_write
	jmp	LBB0_11
LBB0_6:
	movq	%r14, %rdi
	callq	_adreno_is_a330v2
	testq	%rax, %rax
	je	LBB0_8
## %bb.7:
	movq	_REG_A3XX_VBIF_ABIT_SORT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$65599, %edx                    ## imm = 0x1003F
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_ABIT_SORT_CONF@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$164, %edx
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_GATE_OFF_WRREQ_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$63, %edx
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_DDR_OUT_MAX_BURST@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$771, %edx                      ## imm = 0x303
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$3, %edx
	callq	_gpu_write
	jmp	LBB0_11
LBB0_8:
	movq	%r14, %rdi
	callq	_adreno_is_a330
	testq	%rax, %rax
	je	LBB0_10
## %bb.9:
	movq	_REG_A3XX_VBIF_IN_RD_LIM_CONF0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$404232216, %edx                ## imm = 0x18181818
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_IN_RD_LIM_CONF1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$404232216, %edx                ## imm = 0x18181818
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_OUT_RD_LIM_CONF0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$404232216, %edx                ## imm = 0x18181818
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_OUT_WR_LIM_CONF0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$404232216, %edx                ## imm = 0x18181818
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_DDR_OUT_MAX_BURST@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$771, %edx                      ## imm = 0x303
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_IN_WR_LIM_CONF0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$404232216, %edx                ## imm = 0x18181818
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_IN_WR_LIM_CONF1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$404232216, %edx                ## imm = 0x18181818
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_GATE_OFF_WRREQ_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$63, %edx
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_ARB_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$48, %edx
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_OUT_AXI_AOOO_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$63, %edx
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_OUT_AXI_AOOO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$4128831, %edx                  ## imm = 0x3F003F
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_ABIT_SORT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$65599, %edx                    ## imm = 0x1003F
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_ABIT_SORT_CONF@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$164, %edx
	callq	_gpu_write
	movq	_REG_A3XX_VBIF_CLKON@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$1, %edx
	callq	_gpu_write
	jmp	LBB0_11
LBB0_10:
	xorl	%eax, %eax
	callq	_BUG
LBB0_11:
	movq	_REG_A3XX_RBBM_GPU_BUSY_MASKED@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$-1, %edx
	callq	_gpu_write
	movq	_REG_A3XX_RBBM_SP_HYST_CNT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$16, %edx
	callq	_gpu_write
	movq	_REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$16, %edx
	callq	_gpu_write
	movq	_REG_A3XX_RBBM_AHB_CTL0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A3XX_RBBM_AHB_CTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$-1493172225, %edx              ## imm = 0xA6FFFFFF
	callq	_gpu_write
	movq	_REG_A3XX_RBBM_RBBM_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$196608, %edx                   ## imm = 0x30000
	callq	_gpu_write
	movq	_REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$69631, %edx                    ## imm = 0x10FFF
	callq	_gpu_write
	movq	_REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	%r14, %rdi
	callq	_adreno_is_a306
	movl	$-1431655766, %edx              ## imm = 0xAAAAAAAA
	testq	%rax, %rax
	jne	LBB0_15
## %bb.12:
	movq	%r14, %rdi
	callq	_adreno_is_a320
	movl	$-1073741825, %edx              ## imm = 0xBFFFFFFF
	testq	%rax, %rax
	jne	LBB0_15
## %bb.13:
	movq	%r14, %rdi
	callq	_adreno_is_a330v2
	movl	$-1431655766, %edx              ## imm = 0xAAAAAAAA
	testq	%rax, %rax
	jne	LBB0_15
## %bb.14:
	movq	%r14, %rdi
	callq	_adreno_is_a330
	movl	$-1073938433, %edx              ## imm = 0xBFFCFFFF
	testq	%rax, %rax
	je	LBB0_16
LBB0_15:
	movq	_REG_A3XX_RBBM_CLOCK_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_gpu_write
LBB0_16:
	movq	%r14, %rdi
	callq	_adreno_is_a330v2
	movl	$89216085, %edx                 ## imm = 0x5515455
	testq	%rax, %rax
	jne	LBB0_18
## %bb.17:
	movq	%r14, %rdi
	callq	_adreno_is_a330
	xorl	%edx, %edx
	testq	%rax, %rax
	je	LBB0_19
LBB0_18:
	movq	_REG_A3XX_RBBM_GPR0_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_gpu_write
LBB0_19:
	cmpq	$0, 8(%r15)
	je	LBB0_21
## %bb.20:
	movq	_REG_A3XX_RB_GMEM_BASE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r15), %edx
	sarl	$14, %edx
	movq	%r13, %rdi
	callq	_gpu_write
LBB0_21:
	movq	_REG_A3XX_RBBM_PERFCTR_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$1, %edx
	callq	_gpu_write
	cmpl	$0, 4(%r13)
	jle	LBB0_24
## %bb.22:
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_23:                                ## =>This Inner Loop Header: Depth=1
	movq	8(%r13), %rax
	movl	(%rax,%rbx,8), %edx
	movl	4(%rax,%rbx,8), %esi
	movq	%r13, %rdi
	callq	_gpu_write
	incq	%rbx
	movslq	4(%r13), %rax
	cmpq	%rax, %rbx
	jl	LBB0_23
LBB0_24:
	movq	_REG_A3XX_RBBM_INT_0_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_A3XX_INT0_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	callq	_gpu_write
	movq	%r13, %rdi
	callq	_adreno_hw_init
	movl	%eax, %ecx
	testl	%eax, %eax
	jne	LBB0_39
## %bb.25:
	movq	_REG_A3XX_CP_PROTECT_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$7, %edx
	callq	_gpu_write
	xorl	%edi, %edi
	callq	_REG_A3XX_CP_PROTECT
	movq	%r13, %rdi
	movl	%eax, %esi
	movl	$1660944448, %edx               ## imm = 0x63000040
	callq	_gpu_write
	movl	$1, %edi
	callq	_REG_A3XX_CP_PROTECT
	movq	%r13, %rdi
	movl	%eax, %esi
	movl	$1644167296, %edx               ## imm = 0x62000080
	callq	_gpu_write
	movl	$2, %edi
	callq	_REG_A3XX_CP_PROTECT
	movq	%r13, %rdi
	movl	%eax, %esi
	movl	$1610612940, %edx               ## imm = 0x600000CC
	callq	_gpu_write
	movl	$3, %edi
	callq	_REG_A3XX_CP_PROTECT
	movq	%r13, %rdi
	movl	%eax, %esi
	movl	$1610613000, %edx               ## imm = 0x60000108
	callq	_gpu_write
	movl	$4, %edi
	callq	_REG_A3XX_CP_PROTECT
	movq	%r13, %rdi
	movl	%eax, %esi
	movl	$1677721920, %edx               ## imm = 0x64000140
	callq	_gpu_write
	movl	$5, %edi
	callq	_REG_A3XX_CP_PROTECT
	movq	%r13, %rdi
	movl	%eax, %esi
	movl	$1711277056, %edx               ## imm = 0x66000400
	callq	_gpu_write
	movl	$6, %edi
	callq	_REG_A3XX_CP_PROTECT
	movq	%r13, %rdi
	movl	%eax, %esi
	movl	$1694500608, %edx               ## imm = 0x65000700
	callq	_gpu_write
	movl	$7, %edi
	callq	_REG_A3XX_CP_PROTECT
	movq	%r13, %rdi
	movl	%eax, %esi
	movl	$1627391960, %edx               ## imm = 0x610007D8
	callq	_gpu_write
	movl	$8, %edi
	callq	_REG_A3XX_CP_PROTECT
	movq	%r13, %rdi
	movl	%eax, %esi
	movl	$1644169184, %edx               ## imm = 0x620007E0
	callq	_gpu_write
	movl	$9, %edi
	callq	_REG_A3XX_CP_PROTECT
	movq	%r13, %rdi
	movl	%eax, %esi
	movl	$1627394424, %edx               ## imm = 0x61001178
	callq	_gpu_write
	movl	$10, %edi
	callq	_REG_A3XX_CP_PROTECT
	movq	%r13, %rdi
	movl	%eax, %esi
	movl	$1677726080, %edx               ## imm = 0x64001180
	callq	_gpu_write
	movl	$11, %edi
	callq	_REG_A3XX_CP_PROTECT
	movq	%r13, %rdi
	movl	%eax, %esi
	movl	$1610625792, %edx               ## imm = 0x60003300
	callq	_gpu_write
	movl	$12, %edi
	callq	_REG_A3XX_CP_PROTECT
	movq	%r13, %rdi
	movl	%eax, %esi
	movl	$1795211264, %edx               ## imm = 0x6B00C000
	callq	_gpu_write
	movq	%r14, -48(%rbp)                 ## 8-byte Spill
	movq	(%r14), %rax
	movq	_ADRENO_FW_PM4@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	(%rax,%rcx,8), %rax
	movq	8(%rax), %r15
	movl	(%rax), %r12d
	movl	4(%r15), %esi
	leaq	L_.str.1(%rip), %rdi
	callq	_DBG
	movq	_REG_AXXX_CP_DEBUG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE@GOTPCREL(%rip), %rax
	movq	_AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	%r13, %rdi
	callq	_gpu_write
	movq	_REG_AXXX_CP_ME_RAM_WADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	cmpl	$8, %r12d
	jl	LBB0_28
## %bb.26:
	shrq	$2, %r12
	movl	$1, %ebx
	movq	_REG_AXXX_CP_ME_RAM_DATA@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_27:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %esi
	movl	(%r15,%rbx,4), %edx
	movq	%r13, %rdi
	callq	_gpu_write
	incq	%rbx
	cmpq	%rbx, %r12
	jne	LBB0_27
LBB0_28:
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rax
	movq	_ADRENO_FW_PFP@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	(%rax,%rcx,8), %rax
	movq	8(%rax), %r15
	movl	(%rax), %r12d
	movl	20(%r15), %esi
	leaq	L_.str.2(%rip), %rdi
	callq	_DBG
	movq	_REG_A3XX_CP_PFP_UCODE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	cmpl	$8, %r12d
	jl	LBB0_31
## %bb.29:
	shrq	$2, %r12
	movl	$1, %ebx
	movq	_REG_A3XX_CP_PFP_UCODE_DATA@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_30:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %esi
	movl	(%r15,%rbx,4), %edx
	movq	%r13, %rdi
	callq	_gpu_write
	incq	%rbx
	cmpq	%rbx, %r12
	jne	LBB0_30
LBB0_31:
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	callq	_adreno_is_a305
	testq	%rax, %rax
	jne	LBB0_34
## %bb.32:
	movq	%rbx, %rdi
	callq	_adreno_is_a306
	testq	%rax, %rax
	jne	LBB0_34
## %bb.33:
	movq	%rbx, %rdi
	callq	_adreno_is_a320
	testq	%rax, %rax
	je	LBB0_35
LBB0_34:
	movq	_REG_AXXX_CP_QUEUE_THRESHOLDS@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	$2, %edi
	callq	_AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START
	movl	%eax, %r15d
	movl	$6, %edi
	callq	_AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START
	orl	%eax, %r15d
	movl	$14, %edi
	callq	_AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START
	orl	%eax, %r15d
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	%r15d, %edx
LBB0_37:
	callq	_gpu_write
LBB0_38:
	movq	_REG_AXXX_CP_ME_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%ebx, %ebx
	movq	%r13, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movq	%r13, %rdi
	callq	_a3xx_me_init
	movq	_EINVAL@GOTPCREL(%rip), %rdx
	xorl	%ecx, %ecx
	subl	(%rdx), %ecx
	testq	%rax, %rax
	cmovnel	%ebx, %ecx
LBB0_39:
	movl	%ecx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_35:
	movq	%rbx, %rdi
	callq	_adreno_is_a330
	testq	%rax, %rax
	je	LBB0_38
## %bb.36:
	movq	_REG_AXXX_CP_QUEUE_THRESHOLDS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$4071432, %edx                  ## imm = 0x3E2008
	jmp	LBB0_37
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"%s"

	.comm	_REG_A3XX_VBIF_IN_RD_LIM_CONF0,4,2 ## @REG_A3XX_VBIF_IN_RD_LIM_CONF0
	.comm	_REG_A3XX_VBIF_IN_RD_LIM_CONF1,4,2 ## @REG_A3XX_VBIF_IN_RD_LIM_CONF1
	.comm	_REG_A3XX_VBIF_OUT_RD_LIM_CONF0,4,2 ## @REG_A3XX_VBIF_OUT_RD_LIM_CONF0
	.comm	_REG_A3XX_VBIF_OUT_WR_LIM_CONF0,4,2 ## @REG_A3XX_VBIF_OUT_WR_LIM_CONF0
	.comm	_REG_A3XX_VBIF_DDR_OUT_MAX_BURST,4,2 ## @REG_A3XX_VBIF_DDR_OUT_MAX_BURST
	.comm	_REG_A3XX_VBIF_IN_WR_LIM_CONF0,4,2 ## @REG_A3XX_VBIF_IN_WR_LIM_CONF0
	.comm	_REG_A3XX_VBIF_IN_WR_LIM_CONF1,4,2 ## @REG_A3XX_VBIF_IN_WR_LIM_CONF1
	.comm	_REG_A3XX_VBIF_GATE_OFF_WRREQ_EN,4,2 ## @REG_A3XX_VBIF_GATE_OFF_WRREQ_EN
	.comm	_REG_A3XX_VBIF_ARB_CTL,4,2      ## @REG_A3XX_VBIF_ARB_CTL
	.comm	_REG_A3XX_VBIF_OUT_AXI_AOOO_EN,4,2 ## @REG_A3XX_VBIF_OUT_AXI_AOOO_EN
	.comm	_REG_A3XX_VBIF_OUT_AXI_AOOO,4,2 ## @REG_A3XX_VBIF_OUT_AXI_AOOO
	.comm	_REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB,4,2 ## @REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB
	.comm	_REG_A3XX_VBIF_ABIT_SORT,4,2    ## @REG_A3XX_VBIF_ABIT_SORT
	.comm	_REG_A3XX_VBIF_ABIT_SORT_CONF,4,2 ## @REG_A3XX_VBIF_ABIT_SORT_CONF
	.comm	_REG_A3XX_VBIF_CLKON,4,2        ## @REG_A3XX_VBIF_CLKON
	.comm	_REG_A3XX_RBBM_GPU_BUSY_MASKED,4,2 ## @REG_A3XX_RBBM_GPU_BUSY_MASKED
	.comm	_REG_A3XX_RBBM_SP_HYST_CNT,4,2  ## @REG_A3XX_RBBM_SP_HYST_CNT
	.comm	_REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL,4,2 ## @REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL
	.comm	_REG_A3XX_RBBM_AHB_CTL0,4,2     ## @REG_A3XX_RBBM_AHB_CTL0
	.comm	_REG_A3XX_RBBM_AHB_CTL1,4,2     ## @REG_A3XX_RBBM_AHB_CTL1
	.comm	_REG_A3XX_RBBM_RBBM_CTL,4,2     ## @REG_A3XX_RBBM_RBBM_CTL
	.comm	_REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL,4,2 ## @REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL
	.comm	_REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG,4,2 ## @REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG
	.comm	_REG_A3XX_RBBM_CLOCK_CTL,4,2    ## @REG_A3XX_RBBM_CLOCK_CTL
	.comm	_REG_A3XX_RBBM_GPR0_CTL,4,2     ## @REG_A3XX_RBBM_GPR0_CTL
	.comm	_REG_A3XX_RB_GMEM_BASE_ADDR,4,2 ## @REG_A3XX_RB_GMEM_BASE_ADDR
	.comm	_REG_A3XX_RBBM_PERFCTR_CTL,4,2  ## @REG_A3XX_RBBM_PERFCTR_CTL
	.comm	_REG_A3XX_RBBM_INT_0_MASK,4,2   ## @REG_A3XX_RBBM_INT_0_MASK
	.comm	_A3XX_INT0_MASK,4,2             ## @A3XX_INT0_MASK
	.comm	_REG_A3XX_CP_PROTECT_CTRL,4,2   ## @REG_A3XX_CP_PROTECT_CTRL
	.comm	_ADRENO_FW_PM4,8,3              ## @ADRENO_FW_PM4
L_.str.1:                               ## @.str.1
	.asciz	"loading PM4 ucode version: %x"

	.comm	_REG_AXXX_CP_DEBUG,4,2          ## @REG_AXXX_CP_DEBUG
	.comm	_AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE,4,2 ## @AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE
	.comm	_AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE,4,2 ## @AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE
	.comm	_REG_AXXX_CP_ME_RAM_WADDR,4,2   ## @REG_AXXX_CP_ME_RAM_WADDR
	.comm	_REG_AXXX_CP_ME_RAM_DATA,4,2    ## @REG_AXXX_CP_ME_RAM_DATA
	.comm	_ADRENO_FW_PFP,8,3              ## @ADRENO_FW_PFP
L_.str.2:                               ## @.str.2
	.asciz	"loading PFP ucode version: %x"

	.comm	_REG_A3XX_CP_PFP_UCODE_ADDR,4,2 ## @REG_A3XX_CP_PFP_UCODE_ADDR
	.comm	_REG_A3XX_CP_PFP_UCODE_DATA,4,2 ## @REG_A3XX_CP_PFP_UCODE_DATA
	.comm	_REG_AXXX_CP_QUEUE_THRESHOLDS,4,2 ## @REG_AXXX_CP_QUEUE_THRESHOLDS
	.comm	_REG_AXXX_CP_ME_CNTL,4,2        ## @REG_AXXX_CP_ME_CNTL
	.comm	_EINVAL,4,2                     ## @EINVAL
	.no_dead_strip	_a3xx_hw_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function a3xx_hw_init
_a3xx_hw_init:                          ; @a3xx_hw_init
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	mov	w23, #63
	movk	w23, #1, lsl #16
	bl	_to_adreno_gpu
	mov	x20, x0
	bl	_to_a3xx_gpu
	mov	x21, x0
	ldr	w1, [x19]
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DBG
	mov	x0, x20
	bl	_adreno_is_a305
	cbz	x0, LBB0_2
; %bb.1:
Lloh2:
	adrp	x8, _REG_A3XX_VBIF_IN_RD_LIM_CONF0@GOTPAGE
Lloh3:
	ldr	x8, [x8, _REG_A3XX_VBIF_IN_RD_LIM_CONF0@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #269488144
	bl	_gpu_write
Lloh5:
	adrp	x8, _REG_A3XX_VBIF_IN_RD_LIM_CONF1@GOTPAGE
Lloh6:
	ldr	x8, [x8, _REG_A3XX_VBIF_IN_RD_LIM_CONF1@GOTPAGEOFF]
Lloh7:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #269488144
	bl	_gpu_write
Lloh8:
	adrp	x8, _REG_A3XX_VBIF_OUT_RD_LIM_CONF0@GOTPAGE
Lloh9:
	ldr	x8, [x8, _REG_A3XX_VBIF_OUT_RD_LIM_CONF0@GOTPAGEOFF]
Lloh10:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #269488144
	bl	_gpu_write
Lloh11:
	adrp	x8, _REG_A3XX_VBIF_OUT_WR_LIM_CONF0@GOTPAGE
Lloh12:
	ldr	x8, [x8, _REG_A3XX_VBIF_OUT_WR_LIM_CONF0@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #269488144
	bl	_gpu_write
Lloh14:
	adrp	x8, _REG_A3XX_VBIF_DDR_OUT_MAX_BURST@GOTPAGE
Lloh15:
	ldr	x8, [x8, _REG_A3XX_VBIF_DDR_OUT_MAX_BURST@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #771
	bl	_gpu_write
Lloh17:
	adrp	x8, _REG_A3XX_VBIF_IN_WR_LIM_CONF0@GOTPAGE
Lloh18:
	ldr	x8, [x8, _REG_A3XX_VBIF_IN_WR_LIM_CONF0@GOTPAGEOFF]
Lloh19:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #269488144
	bl	_gpu_write
Lloh20:
	adrp	x8, _REG_A3XX_VBIF_IN_WR_LIM_CONF1@GOTPAGE
Lloh21:
	ldr	x8, [x8, _REG_A3XX_VBIF_IN_WR_LIM_CONF1@GOTPAGEOFF]
Lloh22:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #269488144
	bl	_gpu_write
Lloh23:
	adrp	x8, _REG_A3XX_VBIF_GATE_OFF_WRREQ_EN@GOTPAGE
Lloh24:
	ldr	x8, [x8, _REG_A3XX_VBIF_GATE_OFF_WRREQ_EN@GOTPAGEOFF]
Lloh25:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #255
	bl	_gpu_write
Lloh26:
	adrp	x8, _REG_A3XX_VBIF_ARB_CTL@GOTPAGE
Lloh27:
	ldr	x8, [x8, _REG_A3XX_VBIF_ARB_CTL@GOTPAGEOFF]
Lloh28:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #48
	bl	_gpu_write
Lloh29:
	adrp	x8, _REG_A3XX_VBIF_OUT_AXI_AOOO_EN@GOTPAGE
Lloh30:
	ldr	x8, [x8, _REG_A3XX_VBIF_OUT_AXI_AOOO_EN@GOTPAGEOFF]
Lloh31:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #60
	bl	_gpu_write
Lloh32:
	adrp	x8, _REG_A3XX_VBIF_OUT_AXI_AOOO@GOTPAGE
Lloh33:
	ldr	x8, [x8, _REG_A3XX_VBIF_OUT_AXI_AOOO@GOTPAGEOFF]
Lloh34:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #3932220
	bl	_gpu_write
	b	LBB0_11
LBB0_2:
	mov	x0, x20
	bl	_adreno_is_a306
	cbz	x0, LBB0_4
; %bb.3:
Lloh35:
	adrp	x8, _REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB@GOTPAGE
Lloh36:
	ldr	x8, [x8, _REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB@GOTPAGEOFF]
Lloh37:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #3
	bl	_gpu_write
Lloh38:
	adrp	x8, _REG_A3XX_VBIF_OUT_RD_LIM_CONF0@GOTPAGE
Lloh39:
	ldr	x8, [x8, _REG_A3XX_VBIF_OUT_RD_LIM_CONF0@GOTPAGEOFF]
Lloh40:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #10
	bl	_gpu_write
Lloh41:
	adrp	x8, _REG_A3XX_VBIF_OUT_WR_LIM_CONF0@GOTPAGE
Lloh42:
	ldr	x8, [x8, _REG_A3XX_VBIF_OUT_WR_LIM_CONF0@GOTPAGEOFF]
Lloh43:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #10
	bl	_gpu_write
	b	LBB0_11
LBB0_4:
	mov	x0, x20
	bl	_adreno_is_a320
	cbz	x0, LBB0_6
; %bb.5:
Lloh44:
	adrp	x8, _REG_A3XX_VBIF_IN_RD_LIM_CONF0@GOTPAGE
Lloh45:
	ldr	x8, [x8, _REG_A3XX_VBIF_IN_RD_LIM_CONF0@GOTPAGEOFF]
Lloh46:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #269488144
	bl	_gpu_write
Lloh47:
	adrp	x8, _REG_A3XX_VBIF_IN_RD_LIM_CONF1@GOTPAGE
Lloh48:
	ldr	x8, [x8, _REG_A3XX_VBIF_IN_RD_LIM_CONF1@GOTPAGEOFF]
Lloh49:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #269488144
	bl	_gpu_write
Lloh50:
	adrp	x8, _REG_A3XX_VBIF_OUT_RD_LIM_CONF0@GOTPAGE
Lloh51:
	ldr	x8, [x8, _REG_A3XX_VBIF_OUT_RD_LIM_CONF0@GOTPAGEOFF]
Lloh52:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #269488144
	bl	_gpu_write
Lloh53:
	adrp	x8, _REG_A3XX_VBIF_OUT_WR_LIM_CONF0@GOTPAGE
Lloh54:
	ldr	x8, [x8, _REG_A3XX_VBIF_OUT_WR_LIM_CONF0@GOTPAGEOFF]
Lloh55:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #269488144
	bl	_gpu_write
Lloh56:
	adrp	x8, _REG_A3XX_VBIF_DDR_OUT_MAX_BURST@GOTPAGE
Lloh57:
	ldr	x8, [x8, _REG_A3XX_VBIF_DDR_OUT_MAX_BURST@GOTPAGEOFF]
Lloh58:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #771
	bl	_gpu_write
Lloh59:
	adrp	x8, _REG_A3XX_VBIF_IN_WR_LIM_CONF0@GOTPAGE
Lloh60:
	ldr	x8, [x8, _REG_A3XX_VBIF_IN_WR_LIM_CONF0@GOTPAGEOFF]
Lloh61:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #269488144
	bl	_gpu_write
Lloh62:
	adrp	x8, _REG_A3XX_VBIF_IN_WR_LIM_CONF1@GOTPAGE
Lloh63:
	ldr	x8, [x8, _REG_A3XX_VBIF_IN_WR_LIM_CONF1@GOTPAGEOFF]
Lloh64:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #269488144
	bl	_gpu_write
Lloh65:
	adrp	x8, _REG_A3XX_VBIF_GATE_OFF_WRREQ_EN@GOTPAGE
Lloh66:
	ldr	x8, [x8, _REG_A3XX_VBIF_GATE_OFF_WRREQ_EN@GOTPAGEOFF]
Lloh67:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #255
	bl	_gpu_write
Lloh68:
	adrp	x8, _REG_A3XX_VBIF_ARB_CTL@GOTPAGE
Lloh69:
	ldr	x8, [x8, _REG_A3XX_VBIF_ARB_CTL@GOTPAGEOFF]
Lloh70:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #48
	bl	_gpu_write
Lloh71:
	adrp	x8, _REG_A3XX_VBIF_OUT_AXI_AOOO_EN@GOTPAGE
Lloh72:
	ldr	x8, [x8, _REG_A3XX_VBIF_OUT_AXI_AOOO_EN@GOTPAGEOFF]
Lloh73:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #60
	bl	_gpu_write
Lloh74:
	adrp	x8, _REG_A3XX_VBIF_OUT_AXI_AOOO@GOTPAGE
Lloh75:
	ldr	x8, [x8, _REG_A3XX_VBIF_OUT_AXI_AOOO@GOTPAGEOFF]
Lloh76:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #3932220
	bl	_gpu_write
Lloh77:
	adrp	x8, _REG_A3XX_VBIF_ABIT_SORT@GOTPAGE
Lloh78:
	ldr	x8, [x8, _REG_A3XX_VBIF_ABIT_SORT@GOTPAGEOFF]
Lloh79:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #255
	bl	_gpu_write
Lloh80:
	adrp	x8, _REG_A3XX_VBIF_ABIT_SORT_CONF@GOTPAGE
Lloh81:
	ldr	x8, [x8, _REG_A3XX_VBIF_ABIT_SORT_CONF@GOTPAGEOFF]
Lloh82:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #164
	bl	_gpu_write
	b	LBB0_11
LBB0_6:
	mov	x0, x20
	bl	_adreno_is_a330v2
	cbz	x0, LBB0_8
; %bb.7:
Lloh83:
	adrp	x8, _REG_A3XX_VBIF_ABIT_SORT@GOTPAGE
Lloh84:
	ldr	x8, [x8, _REG_A3XX_VBIF_ABIT_SORT@GOTPAGEOFF]
Lloh85:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #63
	movk	w2, #1, lsl #16
	bl	_gpu_write
Lloh86:
	adrp	x8, _REG_A3XX_VBIF_ABIT_SORT_CONF@GOTPAGE
Lloh87:
	ldr	x8, [x8, _REG_A3XX_VBIF_ABIT_SORT_CONF@GOTPAGEOFF]
Lloh88:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #164
	bl	_gpu_write
Lloh89:
	adrp	x8, _REG_A3XX_VBIF_GATE_OFF_WRREQ_EN@GOTPAGE
Lloh90:
	ldr	x8, [x8, _REG_A3XX_VBIF_GATE_OFF_WRREQ_EN@GOTPAGEOFF]
Lloh91:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #63
	bl	_gpu_write
Lloh92:
	adrp	x8, _REG_A3XX_VBIF_DDR_OUT_MAX_BURST@GOTPAGE
Lloh93:
	ldr	x8, [x8, _REG_A3XX_VBIF_DDR_OUT_MAX_BURST@GOTPAGEOFF]
Lloh94:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #771
	bl	_gpu_write
Lloh95:
	adrp	x8, _REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB@GOTPAGE
Lloh96:
	ldr	x8, [x8, _REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB@GOTPAGEOFF]
Lloh97:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #3
	bl	_gpu_write
	b	LBB0_11
LBB0_8:
	mov	x0, x20
	bl	_adreno_is_a330
	cbz	x0, LBB0_10
; %bb.9:
Lloh98:
	adrp	x8, _REG_A3XX_VBIF_IN_RD_LIM_CONF0@GOTPAGE
Lloh99:
	ldr	x8, [x8, _REG_A3XX_VBIF_IN_RD_LIM_CONF0@GOTPAGEOFF]
Lloh100:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #404232216
	bl	_gpu_write
Lloh101:
	adrp	x8, _REG_A3XX_VBIF_IN_RD_LIM_CONF1@GOTPAGE
Lloh102:
	ldr	x8, [x8, _REG_A3XX_VBIF_IN_RD_LIM_CONF1@GOTPAGEOFF]
Lloh103:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #404232216
	bl	_gpu_write
Lloh104:
	adrp	x8, _REG_A3XX_VBIF_OUT_RD_LIM_CONF0@GOTPAGE
Lloh105:
	ldr	x8, [x8, _REG_A3XX_VBIF_OUT_RD_LIM_CONF0@GOTPAGEOFF]
Lloh106:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #404232216
	bl	_gpu_write
Lloh107:
	adrp	x8, _REG_A3XX_VBIF_OUT_WR_LIM_CONF0@GOTPAGE
Lloh108:
	ldr	x8, [x8, _REG_A3XX_VBIF_OUT_WR_LIM_CONF0@GOTPAGEOFF]
Lloh109:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #404232216
	bl	_gpu_write
Lloh110:
	adrp	x8, _REG_A3XX_VBIF_DDR_OUT_MAX_BURST@GOTPAGE
Lloh111:
	ldr	x8, [x8, _REG_A3XX_VBIF_DDR_OUT_MAX_BURST@GOTPAGEOFF]
Lloh112:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #771
	bl	_gpu_write
Lloh113:
	adrp	x8, _REG_A3XX_VBIF_IN_WR_LIM_CONF0@GOTPAGE
Lloh114:
	ldr	x8, [x8, _REG_A3XX_VBIF_IN_WR_LIM_CONF0@GOTPAGEOFF]
Lloh115:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #404232216
	bl	_gpu_write
Lloh116:
	adrp	x8, _REG_A3XX_VBIF_IN_WR_LIM_CONF1@GOTPAGE
Lloh117:
	ldr	x8, [x8, _REG_A3XX_VBIF_IN_WR_LIM_CONF1@GOTPAGEOFF]
Lloh118:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #404232216
	bl	_gpu_write
Lloh119:
	adrp	x8, _REG_A3XX_VBIF_GATE_OFF_WRREQ_EN@GOTPAGE
Lloh120:
	ldr	x8, [x8, _REG_A3XX_VBIF_GATE_OFF_WRREQ_EN@GOTPAGEOFF]
Lloh121:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #63
	bl	_gpu_write
Lloh122:
	adrp	x8, _REG_A3XX_VBIF_ARB_CTL@GOTPAGE
Lloh123:
	ldr	x8, [x8, _REG_A3XX_VBIF_ARB_CTL@GOTPAGEOFF]
Lloh124:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #48
	bl	_gpu_write
Lloh125:
	adrp	x8, _REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB@GOTPAGE
Lloh126:
	ldr	x8, [x8, _REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB@GOTPAGEOFF]
Lloh127:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
Lloh128:
	adrp	x8, _REG_A3XX_VBIF_OUT_AXI_AOOO_EN@GOTPAGE
Lloh129:
	ldr	x8, [x8, _REG_A3XX_VBIF_OUT_AXI_AOOO_EN@GOTPAGEOFF]
Lloh130:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #63
	bl	_gpu_write
Lloh131:
	adrp	x8, _REG_A3XX_VBIF_OUT_AXI_AOOO@GOTPAGE
Lloh132:
	ldr	x8, [x8, _REG_A3XX_VBIF_OUT_AXI_AOOO@GOTPAGEOFF]
Lloh133:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #4128831
	bl	_gpu_write
Lloh134:
	adrp	x8, _REG_A3XX_VBIF_ABIT_SORT@GOTPAGE
Lloh135:
	ldr	x8, [x8, _REG_A3XX_VBIF_ABIT_SORT@GOTPAGEOFF]
Lloh136:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #63
	movk	w2, #1, lsl #16
	bl	_gpu_write
Lloh137:
	adrp	x8, _REG_A3XX_VBIF_ABIT_SORT_CONF@GOTPAGE
Lloh138:
	ldr	x8, [x8, _REG_A3XX_VBIF_ABIT_SORT_CONF@GOTPAGEOFF]
Lloh139:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #164
	bl	_gpu_write
Lloh140:
	adrp	x8, _REG_A3XX_VBIF_CLKON@GOTPAGE
Lloh141:
	ldr	x8, [x8, _REG_A3XX_VBIF_CLKON@GOTPAGEOFF]
Lloh142:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
	b	LBB0_11
LBB0_10:
	bl	_BUG
LBB0_11:
	mov	w22, #-1431655766
Lloh143:
	adrp	x8, _REG_A3XX_RBBM_GPU_BUSY_MASKED@GOTPAGE
Lloh144:
	ldr	x8, [x8, _REG_A3XX_RBBM_GPU_BUSY_MASKED@GOTPAGEOFF]
Lloh145:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1
	bl	_gpu_write
Lloh146:
	adrp	x8, _REG_A3XX_RBBM_SP_HYST_CNT@GOTPAGE
Lloh147:
	ldr	x8, [x8, _REG_A3XX_RBBM_SP_HYST_CNT@GOTPAGEOFF]
Lloh148:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #16
	bl	_gpu_write
Lloh149:
	adrp	x8, _REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL@GOTPAGE
Lloh150:
	ldr	x8, [x8, _REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL@GOTPAGEOFF]
Lloh151:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #16
	bl	_gpu_write
Lloh152:
	adrp	x8, _REG_A3XX_RBBM_AHB_CTL0@GOTPAGE
Lloh153:
	ldr	x8, [x8, _REG_A3XX_RBBM_AHB_CTL0@GOTPAGEOFF]
Lloh154:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
Lloh155:
	adrp	x8, _REG_A3XX_RBBM_AHB_CTL1@GOTPAGE
Lloh156:
	ldr	x8, [x8, _REG_A3XX_RBBM_AHB_CTL1@GOTPAGEOFF]
Lloh157:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1493172225
	bl	_gpu_write
Lloh158:
	adrp	x8, _REG_A3XX_RBBM_RBBM_CTL@GOTPAGE
Lloh159:
	ldr	x8, [x8, _REG_A3XX_RBBM_RBBM_CTL@GOTPAGEOFF]
Lloh160:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #196608
	bl	_gpu_write
Lloh161:
	adrp	x8, _REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL@GOTPAGE
Lloh162:
	ldr	x8, [x8, _REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL@GOTPAGEOFF]
Lloh163:
	ldr	w1, [x8]
	add	w2, w23, #4032
	mov	x0, x19
	bl	_gpu_write
Lloh164:
	adrp	x8, _REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG@GOTPAGE
Lloh165:
	ldr	x8, [x8, _REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG@GOTPAGEOFF]
Lloh166:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
	mov	x0, x20
	bl	_adreno_is_a306
	cbnz	x0, LBB0_17
; %bb.12:
	mov	x0, x20
	bl	_adreno_is_a320
	cbz	x0, LBB0_14
; %bb.13:
	mov	w22, #-1073741825
	b	LBB0_17
LBB0_14:
	mov	x0, x20
	bl	_adreno_is_a330v2
	cbnz	x0, LBB0_17
; %bb.15:
	mov	x0, x20
	bl	_adreno_is_a330
	cbz	x0, LBB0_18
; %bb.16:
	mov	w22, #-1073938433
LBB0_17:
Lloh167:
	adrp	x8, _REG_A3XX_RBBM_CLOCK_CTL@GOTPAGE
Lloh168:
	ldr	x8, [x8, _REG_A3XX_RBBM_CLOCK_CTL@GOTPAGEOFF]
Lloh169:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x22
	bl	_gpu_write
LBB0_18:
	mov	x0, x20
	bl	_adreno_is_a330v2
	cbz	x0, LBB0_20
; %bb.19:
	mov	w2, #21589
	movk	w2, #1361, lsl #16
	b	LBB0_22
LBB0_20:
	mov	x0, x20
	bl	_adreno_is_a330
	cbz	x0, LBB0_23
; %bb.21:
	mov	w2, #0
LBB0_22:
Lloh170:
	adrp	x8, _REG_A3XX_RBBM_GPR0_CTL@GOTPAGE
Lloh171:
	ldr	x8, [x8, _REG_A3XX_RBBM_GPR0_CTL@GOTPAGEOFF]
Lloh172:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_gpu_write
LBB0_23:
	ldr	x8, [x21, #8]
	cbz	x8, LBB0_25
; %bb.24:
Lloh173:
	adrp	x8, _REG_A3XX_RB_GMEM_BASE_ADDR@GOTPAGE
Lloh174:
	ldr	x8, [x8, _REG_A3XX_RB_GMEM_BASE_ADDR@GOTPAGEOFF]
Lloh175:
	ldr	w1, [x8]
	ldr	w8, [x21]
	asr	w2, w8, #14
	mov	x0, x19
	bl	_gpu_write
LBB0_25:
Lloh176:
	adrp	x8, _REG_A3XX_RBBM_PERFCTR_CTL@GOTPAGE
Lloh177:
	ldr	x8, [x8, _REG_A3XX_RBBM_PERFCTR_CTL@GOTPAGEOFF]
Lloh178:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
	ldr	w8, [x19, #4]
	cmp	w8, #1
	b.lt	LBB0_28
; %bb.26:
	mov	x21, #0
	mov	x22, #0
LBB0_27:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #8]
	add	x8, x8, x21
	ldp	w2, w1, [x8]
	mov	x0, x19
	bl	_gpu_write
	add	x22, x22, #1
	ldrsw	x8, [x19, #4]
	add	x21, x21, #8
	cmp	x22, x8
	b.lt	LBB0_27
LBB0_28:
Lloh179:
	adrp	x8, _REG_A3XX_RBBM_INT_0_MASK@GOTPAGE
Lloh180:
	ldr	x8, [x8, _REG_A3XX_RBBM_INT_0_MASK@GOTPAGEOFF]
Lloh181:
	ldr	w1, [x8]
Lloh182:
	adrp	x8, _A3XX_INT0_MASK@GOTPAGE
Lloh183:
	ldr	x8, [x8, _A3XX_INT0_MASK@GOTPAGEOFF]
Lloh184:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_gpu_write
	mov	x0, x19
	bl	_adreno_hw_init
	cbnz	w0, LBB0_41
; %bb.29:
Lloh185:
	adrp	x8, _REG_A3XX_CP_PROTECT_CTRL@GOTPAGE
Lloh186:
	ldr	x8, [x8, _REG_A3XX_CP_PROTECT_CTRL@GOTPAGEOFF]
Lloh187:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #7
	bl	_gpu_write
	mov	w0, #0
	bl	_REG_A3XX_CP_PROTECT
	mov	x1, x0
	mov	x0, x19
	mov	w2, #64
	movk	w2, #25344, lsl #16
	bl	_gpu_write
	mov	w0, #1
	bl	_REG_A3XX_CP_PROTECT
	mov	x1, x0
	mov	w21, #128
	movk	w21, #25088, lsl #16
	mov	x0, x19
	mov	w2, #128
	movk	w2, #25088, lsl #16
	bl	_gpu_write
	mov	w0, #2
	bl	_REG_A3XX_CP_PROTECT
	mov	x1, x0
	mov	w22, #204
	movk	w22, #24576, lsl #16
	mov	x0, x19
	mov	w2, #204
	movk	w2, #24576, lsl #16
	bl	_gpu_write
	mov	w0, #3
	bl	_REG_A3XX_CP_PROTECT
	mov	x1, x0
	add	w2, w22, #60
	mov	x0, x19
	bl	_gpu_write
	mov	w0, #4
	bl	_REG_A3XX_CP_PROTECT
	mov	x1, x0
	mov	x0, x19
	mov	w2, #320
	movk	w2, #25600, lsl #16
	bl	_gpu_write
	mov	w0, #5
	bl	_REG_A3XX_CP_PROTECT
	mov	x1, x0
	mov	x0, x19
	mov	w2, #1024
	movk	w2, #26112, lsl #16
	bl	_gpu_write
	mov	w0, #6
	bl	_REG_A3XX_CP_PROTECT
	mov	x1, x0
	mov	x0, x19
	mov	w2, #1792
	movk	w2, #25856, lsl #16
	bl	_gpu_write
	mov	w0, #7
	bl	_REG_A3XX_CP_PROTECT
	mov	x1, x0
	mov	w22, #2008
	movk	w22, #24832, lsl #16
	mov	x0, x19
	mov	w2, #2008
	movk	w2, #24832, lsl #16
	bl	_gpu_write
	mov	w0, #8
	bl	_REG_A3XX_CP_PROTECT
	mov	x1, x0
	mov	w8, #1888
	orr	w2, w21, w8
	mov	x0, x19
	bl	_gpu_write
	mov	w0, #9
	bl	_REG_A3XX_CP_PROTECT
	mov	x1, x0
	add	w2, w22, #2464
	mov	x0, x19
	bl	_gpu_write
	mov	w0, #10
	bl	_REG_A3XX_CP_PROTECT
	mov	x1, x0
	mov	x0, x19
	mov	w2, #4480
	movk	w2, #25600, lsl #16
	bl	_gpu_write
	mov	w0, #11
	bl	_REG_A3XX_CP_PROTECT
	mov	x1, x0
	mov	x0, x19
	mov	w2, #13056
	movk	w2, #24576, lsl #16
	bl	_gpu_write
	mov	w0, #12
	bl	_REG_A3XX_CP_PROTECT
	mov	x1, x0
	mov	x0, x19
	mov	w2, #49152
	movk	w2, #27392, lsl #16
	bl	_gpu_write
	ldr	x8, [x20]
Lloh188:
	adrp	x9, _ADRENO_FW_PM4@GOTPAGE
Lloh189:
	ldr	x9, [x9, _ADRENO_FW_PM4@GOTPAGEOFF]
Lloh190:
	ldr	x9, [x9]
	ldr	x8, [x8, x9, lsl #3]
	ldr	x21, [x8, #8]
	ldr	w22, [x8]
	ldr	w1, [x21, #4]
Lloh191:
	adrp	x0, l_.str.1@PAGE
Lloh192:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DBG
Lloh193:
	adrp	x8, _REG_AXXX_CP_DEBUG@GOTPAGE
Lloh194:
	ldr	x8, [x8, _REG_AXXX_CP_DEBUG@GOTPAGEOFF]
Lloh195:
	adrp	x9, _AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE@GOTPAGE
Lloh196:
	ldr	x9, [x9, _AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE@GOTPAGEOFF]
Lloh197:
	ldr	w1, [x8]
Lloh198:
	ldr	w8, [x9]
Lloh199:
	adrp	x9, _AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE@GOTPAGE
Lloh200:
	ldr	x9, [x9, _AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE@GOTPAGEOFF]
Lloh201:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_gpu_write
Lloh202:
	adrp	x8, _REG_AXXX_CP_ME_RAM_WADDR@GOTPAGE
Lloh203:
	ldr	x8, [x8, _REG_AXXX_CP_ME_RAM_WADDR@GOTPAGEOFF]
Lloh204:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
	cmp	w22, #8
	b.lt	LBB0_32
; %bb.30:
	lsr	x8, x22, #2
	add	x21, x21, #4
	sub	x22, x8, #1
Lloh205:
	adrp	x23, _REG_AXXX_CP_ME_RAM_DATA@GOTPAGE
Lloh206:
	ldr	x23, [x23, _REG_AXXX_CP_ME_RAM_DATA@GOTPAGEOFF]
LBB0_31:                                ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x23]
	ldr	w2, [x21], #4
	mov	x0, x19
	bl	_gpu_write
	subs	x22, x22, #1
	b.ne	LBB0_31
LBB0_32:
	ldr	x8, [x20]
Lloh207:
	adrp	x9, _ADRENO_FW_PFP@GOTPAGE
Lloh208:
	ldr	x9, [x9, _ADRENO_FW_PFP@GOTPAGEOFF]
Lloh209:
	ldr	x9, [x9]
	ldr	x8, [x8, x9, lsl #3]
	ldr	x21, [x8, #8]
	ldr	w22, [x8]
	ldr	w1, [x21, #20]
Lloh210:
	adrp	x0, l_.str.2@PAGE
Lloh211:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	_DBG
Lloh212:
	adrp	x8, _REG_A3XX_CP_PFP_UCODE_ADDR@GOTPAGE
Lloh213:
	ldr	x8, [x8, _REG_A3XX_CP_PFP_UCODE_ADDR@GOTPAGEOFF]
Lloh214:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
	cmp	w22, #8
	b.lt	LBB0_35
; %bb.33:
	lsr	x8, x22, #2
	add	x21, x21, #4
	sub	x22, x8, #1
Lloh215:
	adrp	x23, _REG_A3XX_CP_PFP_UCODE_DATA@GOTPAGE
Lloh216:
	ldr	x23, [x23, _REG_A3XX_CP_PFP_UCODE_DATA@GOTPAGEOFF]
LBB0_34:                                ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x23]
	ldr	w2, [x21], #4
	mov	x0, x19
	bl	_gpu_write
	subs	x22, x22, #1
	b.ne	LBB0_34
LBB0_35:
	mov	x0, x20
	bl	_adreno_is_a305
	cbnz	x0, LBB0_38
; %bb.36:
	mov	x0, x20
	bl	_adreno_is_a306
	cbnz	x0, LBB0_38
; %bb.37:
	mov	x0, x20
	bl	_adreno_is_a320
	cbz	x0, LBB0_42
LBB0_38:
Lloh217:
	adrp	x8, _REG_AXXX_CP_QUEUE_THRESHOLDS@GOTPAGE
Lloh218:
	ldr	x8, [x8, _REG_AXXX_CP_QUEUE_THRESHOLDS@GOTPAGEOFF]
Lloh219:
	ldr	w20, [x8]
	mov	w0, #2
	bl	_AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START
	mov	x21, x0
	mov	w0, #6
	bl	_AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START
	orr	w21, w0, w21
	mov	w0, #14
	bl	_AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START
	orr	w2, w21, w0
	mov	x0, x19
	mov	x1, x20
LBB0_39:
	bl	_gpu_write
LBB0_40:
Lloh220:
	adrp	x8, _REG_AXXX_CP_ME_CNTL@GOTPAGE
Lloh221:
	ldr	x8, [x8, _REG_AXXX_CP_ME_CNTL@GOTPAGEOFF]
Lloh222:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
	mov	x0, x19
	bl	_a3xx_me_init
Lloh223:
	adrp	x8, _EINVAL@GOTPAGE
Lloh224:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh225:
	ldr	w8, [x8]
	cmp	x0, #0
	csneg	w0, wzr, w8, ne
LBB0_41:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_42:
	mov	x0, x20
	bl	_adreno_is_a330
	cbz	x0, LBB0_40
; %bb.43:
Lloh226:
	adrp	x8, _REG_AXXX_CP_QUEUE_THRESHOLDS@GOTPAGE
Lloh227:
	ldr	x8, [x8, _REG_AXXX_CP_QUEUE_THRESHOLDS@GOTPAGEOFF]
Lloh228:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #8200
	movk	w2, #62, lsl #16
	b	LBB0_39
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh140, Lloh141, Lloh142
	.loh AdrpLdrGotLdr	Lloh137, Lloh138, Lloh139
	.loh AdrpLdrGotLdr	Lloh134, Lloh135, Lloh136
	.loh AdrpLdrGotLdr	Lloh131, Lloh132, Lloh133
	.loh AdrpLdrGotLdr	Lloh128, Lloh129, Lloh130
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh164, Lloh165, Lloh166
	.loh AdrpLdrGotLdr	Lloh161, Lloh162, Lloh163
	.loh AdrpLdrGotLdr	Lloh158, Lloh159, Lloh160
	.loh AdrpLdrGotLdr	Lloh155, Lloh156, Lloh157
	.loh AdrpLdrGotLdr	Lloh152, Lloh153, Lloh154
	.loh AdrpLdrGotLdr	Lloh149, Lloh150, Lloh151
	.loh AdrpLdrGotLdr	Lloh146, Lloh147, Lloh148
	.loh AdrpLdrGotLdr	Lloh143, Lloh144, Lloh145
	.loh AdrpLdrGotLdr	Lloh167, Lloh168, Lloh169
	.loh AdrpLdrGotLdr	Lloh170, Lloh171, Lloh172
	.loh AdrpLdrGotLdr	Lloh173, Lloh174, Lloh175
	.loh AdrpLdrGotLdr	Lloh176, Lloh177, Lloh178
	.loh AdrpLdrGotLdr	Lloh182, Lloh183, Lloh184
	.loh AdrpLdrGotLdr	Lloh179, Lloh180, Lloh181
	.loh AdrpLdrGotLdr	Lloh202, Lloh203, Lloh204
	.loh AdrpLdrGotLdr	Lloh199, Lloh200, Lloh201
	.loh AdrpLdrGotLdr	Lloh195, Lloh196, Lloh198
	.loh AdrpLdrGotLdr	Lloh193, Lloh194, Lloh197
	.loh AdrpAdd	Lloh191, Lloh192
	.loh AdrpLdrGotLdr	Lloh188, Lloh189, Lloh190
	.loh AdrpLdrGotLdr	Lloh185, Lloh186, Lloh187
	.loh AdrpLdrGot	Lloh205, Lloh206
	.loh AdrpLdrGotLdr	Lloh212, Lloh213, Lloh214
	.loh AdrpAdd	Lloh210, Lloh211
	.loh AdrpLdrGotLdr	Lloh207, Lloh208, Lloh209
	.loh AdrpLdrGot	Lloh215, Lloh216
	.loh AdrpLdrGotLdr	Lloh217, Lloh218, Lloh219
	.loh AdrpLdrGotLdr	Lloh223, Lloh224, Lloh225
	.loh AdrpLdrGotLdr	Lloh220, Lloh221, Lloh222
	.loh AdrpLdrGotLdr	Lloh226, Lloh227, Lloh228
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"%s"

	.comm	_REG_A3XX_VBIF_IN_RD_LIM_CONF0,4,2 ; @REG_A3XX_VBIF_IN_RD_LIM_CONF0
	.comm	_REG_A3XX_VBIF_IN_RD_LIM_CONF1,4,2 ; @REG_A3XX_VBIF_IN_RD_LIM_CONF1
	.comm	_REG_A3XX_VBIF_OUT_RD_LIM_CONF0,4,2 ; @REG_A3XX_VBIF_OUT_RD_LIM_CONF0
	.comm	_REG_A3XX_VBIF_OUT_WR_LIM_CONF0,4,2 ; @REG_A3XX_VBIF_OUT_WR_LIM_CONF0
	.comm	_REG_A3XX_VBIF_DDR_OUT_MAX_BURST,4,2 ; @REG_A3XX_VBIF_DDR_OUT_MAX_BURST
	.comm	_REG_A3XX_VBIF_IN_WR_LIM_CONF0,4,2 ; @REG_A3XX_VBIF_IN_WR_LIM_CONF0
	.comm	_REG_A3XX_VBIF_IN_WR_LIM_CONF1,4,2 ; @REG_A3XX_VBIF_IN_WR_LIM_CONF1
	.comm	_REG_A3XX_VBIF_GATE_OFF_WRREQ_EN,4,2 ; @REG_A3XX_VBIF_GATE_OFF_WRREQ_EN
	.comm	_REG_A3XX_VBIF_ARB_CTL,4,2      ; @REG_A3XX_VBIF_ARB_CTL
	.comm	_REG_A3XX_VBIF_OUT_AXI_AOOO_EN,4,2 ; @REG_A3XX_VBIF_OUT_AXI_AOOO_EN
	.comm	_REG_A3XX_VBIF_OUT_AXI_AOOO,4,2 ; @REG_A3XX_VBIF_OUT_AXI_AOOO
	.comm	_REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB,4,2 ; @REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB
	.comm	_REG_A3XX_VBIF_ABIT_SORT,4,2    ; @REG_A3XX_VBIF_ABIT_SORT
	.comm	_REG_A3XX_VBIF_ABIT_SORT_CONF,4,2 ; @REG_A3XX_VBIF_ABIT_SORT_CONF
	.comm	_REG_A3XX_VBIF_CLKON,4,2        ; @REG_A3XX_VBIF_CLKON
	.comm	_REG_A3XX_RBBM_GPU_BUSY_MASKED,4,2 ; @REG_A3XX_RBBM_GPU_BUSY_MASKED
	.comm	_REG_A3XX_RBBM_SP_HYST_CNT,4,2  ; @REG_A3XX_RBBM_SP_HYST_CNT
	.comm	_REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL,4,2 ; @REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL
	.comm	_REG_A3XX_RBBM_AHB_CTL0,4,2     ; @REG_A3XX_RBBM_AHB_CTL0
	.comm	_REG_A3XX_RBBM_AHB_CTL1,4,2     ; @REG_A3XX_RBBM_AHB_CTL1
	.comm	_REG_A3XX_RBBM_RBBM_CTL,4,2     ; @REG_A3XX_RBBM_RBBM_CTL
	.comm	_REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL,4,2 ; @REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL
	.comm	_REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG,4,2 ; @REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG
	.comm	_REG_A3XX_RBBM_CLOCK_CTL,4,2    ; @REG_A3XX_RBBM_CLOCK_CTL
	.comm	_REG_A3XX_RBBM_GPR0_CTL,4,2     ; @REG_A3XX_RBBM_GPR0_CTL
	.comm	_REG_A3XX_RB_GMEM_BASE_ADDR,4,2 ; @REG_A3XX_RB_GMEM_BASE_ADDR
	.comm	_REG_A3XX_RBBM_PERFCTR_CTL,4,2  ; @REG_A3XX_RBBM_PERFCTR_CTL
	.comm	_REG_A3XX_RBBM_INT_0_MASK,4,2   ; @REG_A3XX_RBBM_INT_0_MASK
	.comm	_A3XX_INT0_MASK,4,2             ; @A3XX_INT0_MASK
	.comm	_REG_A3XX_CP_PROTECT_CTRL,4,2   ; @REG_A3XX_CP_PROTECT_CTRL
	.comm	_ADRENO_FW_PM4,8,3              ; @ADRENO_FW_PM4
l_.str.1:                               ; @.str.1
	.asciz	"loading PM4 ucode version: %x"

	.comm	_REG_AXXX_CP_DEBUG,4,2          ; @REG_AXXX_CP_DEBUG
	.comm	_AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE,4,2 ; @AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE
	.comm	_AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE,4,2 ; @AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE
	.comm	_REG_AXXX_CP_ME_RAM_WADDR,4,2   ; @REG_AXXX_CP_ME_RAM_WADDR
	.comm	_REG_AXXX_CP_ME_RAM_DATA,4,2    ; @REG_AXXX_CP_ME_RAM_DATA
	.comm	_ADRENO_FW_PFP,8,3              ; @ADRENO_FW_PFP
l_.str.2:                               ; @.str.2
	.asciz	"loading PFP ucode version: %x"

	.comm	_REG_A3XX_CP_PFP_UCODE_ADDR,4,2 ; @REG_A3XX_CP_PFP_UCODE_ADDR
	.comm	_REG_A3XX_CP_PFP_UCODE_DATA,4,2 ; @REG_A3XX_CP_PFP_UCODE_DATA
	.comm	_REG_AXXX_CP_QUEUE_THRESHOLDS,4,2 ; @REG_AXXX_CP_QUEUE_THRESHOLDS
	.comm	_REG_AXXX_CP_ME_CNTL,4,2        ; @REG_AXXX_CP_ME_CNTL
	.comm	_EINVAL,4,2                     ; @EINVAL
	.no_dead_strip	_a3xx_hw_init
.subsections_via_symbols
