	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_dpu_hw_setup_scaler3           ## -- Begin function dpu_hw_setup_scaler3
	.p2align	4, 0x90
_dpu_hw_setup_scaler3:                  ## @dpu_hw_setup_scaler3
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%r8, %rbx
	movl	%ecx, %r14d
	movl	%edx, %r13d
	movq	%rsi, %r12
	movq	%rdi, %r15
	cmpl	$0, 120(%rsi)
	je	LBB0_12
## %bb.1:
	movl	%r13d, -68(%rbp)                ## 4-byte Spill
	xorl	%r13d, %r13d
	xorl	%edi, %edi
	callq	_BIT
	movq	%rbx, %rdi
	movl	(%r12), %ebx
	andl	$3, %ebx
	shll	$16, %ebx
	orl	%eax, %ebx
	testq	%rdi, %rdi
	movq	%rdi, -96(%rbp)                 ## 8-byte Spill
	je	LBB0_4
## %bb.2:
	callq	_DPU_FORMAT_IS_YUV
	testq	%rax, %rax
	je	LBB0_4
## %bb.3:
	movl	$12, %edi
	callq	_BIT
	orl	%ebx, %eax
	movl	4(%r12), %ebx
	andl	$3, %ebx
	shll	$24, %ebx
	orl	%eax, %ebx
LBB0_4:
	movl	%r14d, -64(%rbp)                ## 4-byte Spill
	movq	%r15, -80(%rbp)                 ## 8-byte Spill
	movl	8(%r12), %eax
	shll	$31, %eax
	orl	%ebx, %eax
	movl	%eax, %ebx
	cmpq	$0, 112(%r12)
	je	LBB0_6
## %bb.5:
	movl	$4, %edi
	callq	_BIT
	movl	%eax, %r13d
LBB0_6:
	orl	%r13d, %ebx
	movq	16(%r12), %rax
	movq	24(%r12), %rcx
	movl	(%rax), %edx
	movl	4(%rax), %r13d
	andl	$127, %edx
	movl	(%rcx), %esi
	movl	4(%rcx), %r14d
	andl	$127, %esi
	shll	$8, %esi
	orl	%edx, %esi
	andl	$127, %r13d
	shll	$16, %r13d
	andl	$127, %r14d
	movq	32(%r12), %rax
	movl	$131071, %r15d                  ## imm = 0x1FFFF
	movl	(%rax), %ecx
	andl	%r15d, %ecx
	movl	%ecx, -88(%rbp)                 ## 4-byte Spill
	movq	40(%r12), %rcx
	movl	(%rcx), %edx
	movl	4(%rcx), %ecx
	movl	4(%rax), %eax
	andl	%r15d, %eax
	movl	%eax, -84(%rbp)                 ## 4-byte Spill
	movl	52(%r12), %eax
	movl	%eax, -60(%rbp)                 ## 4-byte Spill
	andl	48(%r12), %r15d
	cmpq	$0, 104(%r12)
	je	LBB0_8
## %bb.7:
	movl	%esi, -56(%rbp)                 ## 4-byte Spill
	leaq	104(%r12), %rsi
	movq	-80(%rbp), %rdi                 ## 8-byte Reload
	movl	%ecx, -52(%rbp)                 ## 4-byte Spill
	movl	%edx, -48(%rbp)                 ## 4-byte Spill
	movl	-68(%rbp), %edx                 ## 4-byte Reload
	callq	__dpu_hw_setup_scaler3_de
	movl	$8, %edi
	callq	_BIT
	movl	-48(%rbp), %edx                 ## 4-byte Reload
	movl	-52(%rbp), %ecx                 ## 4-byte Reload
	movl	-56(%rbp), %esi                 ## 4-byte Reload
	orl	%eax, %ebx
LBB0_8:
	movl	%ebx, -44(%rbp)                 ## 4-byte Spill
	movl	-60(%rbp), %ebx                 ## 4-byte Reload
	orl	%r13d, %esi
	shll	$24, %r14d
	shll	$16, %edx
	shll	$16, %ecx
	shll	$16, %ebx
	cmpq	$0, 96(%r12)
	movl	-68(%rbp), %r13d                ## 4-byte Reload
	je	LBB0_10
## %bb.9:
	movq	-80(%rbp), %rdi                 ## 8-byte Reload
	movl	%esi, -56(%rbp)                 ## 4-byte Spill
	movq	%r12, %rsi
	movl	%ecx, -52(%rbp)                 ## 4-byte Spill
	movl	%edx, -48(%rbp)                 ## 4-byte Spill
	movl	%r13d, %edx
	callq	__dpu_hw_setup_scaler3_lut
	movl	-48(%rbp), %edx                 ## 4-byte Reload
	movl	-52(%rbp), %ecx                 ## 4-byte Reload
	movl	-56(%rbp), %esi                 ## 4-byte Reload
LBB0_10:
	orl	%r14d, %esi
	movl	%esi, -56(%rbp)                 ## 4-byte Spill
	orl	-88(%rbp), %edx                 ## 4-byte Folded Reload
	movl	%edx, -48(%rbp)                 ## 4-byte Spill
	orl	-84(%rbp), %ecx                 ## 4-byte Folded Reload
	movl	%ecx, -52(%rbp)                 ## 4-byte Spill
	orl	%r15d, %ebx
	movl	%ebx, -60(%rbp)                 ## 4-byte Spill
	movl	-64(%rbp), %r14d                ## 4-byte Reload
	cmpl	$4098, %r14d                    ## imm = 0x1002
	jne	LBB0_14
## %bb.11:
	movq	56(%r12), %rax
	movq	64(%r12), %rcx
	movl	(%rax), %esi
	movl	4(%rax), %eax
	andl	$63, %esi
	movl	(%rcx), %edi
	movl	4(%rcx), %edx
	andl	$63, %edi
	shll	$8, %edi
	orl	%esi, %edi
	andl	$63, %eax
	shll	$16, %eax
	orl	%edi, %eax
	andl	$63, %edx
	shll	$24, %edx
	orl	%eax, %edx
	movq	_QSEED3_PHASE_INIT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	-80(%rbp), %r15                 ## 8-byte Reload
	movq	%r15, %rdi
	jmp	LBB0_15
LBB0_12:
	movl	$0, -44(%rbp)                   ## 4-byte Folded Spill
	testq	%rbx, %rbx
	jne	LBB0_16
	jmp	LBB0_13
LBB0_14:
	movq	_QSEED3_PHASE_INIT_Y_H@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	56(%r12), %rax
	movl	$2097151, %r14d                 ## imm = 0x1FFFFF
	movl	(%rax), %edx
	andl	%r14d, %edx
	movq	-80(%rbp), %r15                 ## 8-byte Reload
	movq	%r15, %rdi
	callq	_DPU_REG_WRITE
	movq	_QSEED3_PHASE_INIT_Y_V@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	64(%r12), %rax
	movl	(%rax), %edx
	andl	%r14d, %edx
	movq	%r15, %rdi
	callq	_DPU_REG_WRITE
	movq	_QSEED3_PHASE_INIT_UV_H@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	56(%r12), %rax
	movl	4(%rax), %edx
	andl	%r14d, %edx
	movq	%r15, %rdi
	callq	_DPU_REG_WRITE
	movq	_QSEED3_PHASE_INIT_UV_V@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	64(%r12), %rax
	andl	4(%rax), %r14d
	movq	%r15, %rdi
	movl	%r14d, %edx
	movl	-64(%rbp), %r14d                ## 4-byte Reload
LBB0_15:
	callq	_DPU_REG_WRITE
	movq	_QSEED3_PHASE_STEP_Y_H@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	72(%r12), %rax
	movl	$16777215, %ebx                 ## imm = 0xFFFFFF
	movl	(%rax), %edx
	andl	%ebx, %edx
	movq	%r15, %rdi
	callq	_DPU_REG_WRITE
	movq	_QSEED3_PHASE_STEP_Y_V@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	80(%r12), %rax
	movl	(%rax), %edx
	andl	%ebx, %edx
	movq	%r15, %rdi
	callq	_DPU_REG_WRITE
	movq	_QSEED3_PHASE_STEP_UV_H@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	72(%r12), %rax
	movl	4(%rax), %edx
	andl	%ebx, %edx
	movq	%r15, %rdi
	callq	_DPU_REG_WRITE
	movq	_QSEED3_PHASE_STEP_UV_V@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	80(%r12), %rax
	andl	4(%rax), %ebx
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_DPU_REG_WRITE
	movq	_QSEED3_PRELOAD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	%r15, %rdi
	movl	-56(%rbp), %edx                 ## 4-byte Reload
	callq	_DPU_REG_WRITE
	movq	_QSEED3_SRC_SIZE_Y_RGB_A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	%r15, %rdi
	movl	-48(%rbp), %edx                 ## 4-byte Reload
	callq	_DPU_REG_WRITE
	movq	_QSEED3_SRC_SIZE_UV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	%r15, %rdi
	movl	-52(%rbp), %edx                 ## 4-byte Reload
	callq	_DPU_REG_WRITE
	movq	_QSEED3_DST_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	%r15, %rdi
	movl	-60(%rbp), %edx                 ## 4-byte Reload
	callq	_DPU_REG_WRITE
	movq	-96(%rbp), %rbx                 ## 8-byte Reload
	testq	%rbx, %rbx
	je	LBB0_13
LBB0_16:
	movq	%rbx, %rdi
	callq	_DPU_FORMAT_IS_DX
	testl	%eax, %eax
	je	LBB0_20
## %bb.17:
	cmpq	$0, (%rbx)
	je	LBB0_13
LBB0_18:
	movl	$10, %edi
	callq	_BIT
	orl	-44(%rbp), %eax                 ## 4-byte Folded Reload
	movl	88(%r12), %edx
	cmpl	$4098, %r14d                    ## imm = 0x1002
	jne	LBB0_22
## %bb.19:
	andl	$1, %edx
	shll	$30, %edx
	jmp	LBB0_23
LBB0_20:
	movl	$14, %edi
	callq	_BIT
	orl	%eax, -44(%rbp)                 ## 4-byte Folded Spill
	cmpq	$0, (%rbx)
	jne	LBB0_18
LBB0_13:
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	jmp	LBB0_24
LBB0_22:
	andl	$3, %edx
	shll	$29, %edx
LBB0_23:
	orl	%eax, %edx
LBB0_24:
	movq	_QSEED3_OP_MODE@GOTPCREL(%rip), %rax
	addl	(%rax), %r13d
	movq	%r15, %rdi
	movl	%r13d, %esi
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_DPU_REG_WRITE                  ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_QSEED3_PHASE_INIT,4,2          ## @QSEED3_PHASE_INIT
	.comm	_QSEED3_PHASE_INIT_Y_H,4,2      ## @QSEED3_PHASE_INIT_Y_H
	.comm	_QSEED3_PHASE_INIT_Y_V,4,2      ## @QSEED3_PHASE_INIT_Y_V
	.comm	_QSEED3_PHASE_INIT_UV_H,4,2     ## @QSEED3_PHASE_INIT_UV_H
	.comm	_QSEED3_PHASE_INIT_UV_V,4,2     ## @QSEED3_PHASE_INIT_UV_V
	.comm	_QSEED3_PHASE_STEP_Y_H,4,2      ## @QSEED3_PHASE_STEP_Y_H
	.comm	_QSEED3_PHASE_STEP_Y_V,4,2      ## @QSEED3_PHASE_STEP_Y_V
	.comm	_QSEED3_PHASE_STEP_UV_H,4,2     ## @QSEED3_PHASE_STEP_UV_H
	.comm	_QSEED3_PHASE_STEP_UV_V,4,2     ## @QSEED3_PHASE_STEP_UV_V
	.comm	_QSEED3_PRELOAD,4,2             ## @QSEED3_PRELOAD
	.comm	_QSEED3_SRC_SIZE_Y_RGB_A,4,2    ## @QSEED3_SRC_SIZE_Y_RGB_A
	.comm	_QSEED3_SRC_SIZE_UV,4,2         ## @QSEED3_SRC_SIZE_UV
	.comm	_QSEED3_DST_SIZE,4,2            ## @QSEED3_DST_SIZE
	.comm	_QSEED3_OP_MODE,4,2             ## @QSEED3_OP_MODE
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_dpu_hw_setup_scaler3           ; -- Begin function dpu_hw_setup_scaler3
	.p2align	2
_dpu_hw_setup_scaler3:                  ; @dpu_hw_setup_scaler3
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #128
	.cfi_def_cfa_offset 128
	stp	x28, x27, [sp, #32]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #48]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #64]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #80]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #96]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #112]            ; 16-byte Folded Spill
	add	x29, sp, #112
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x23, x4
	mov	x21, x3
	mov	x19, x2
	mov	x22, x1
	mov	x20, x0
	ldr	w8, [x1, #120]
	cbz	w8, LBB0_6
; %bb.1:
	str	w21, [sp, #28]                  ; 4-byte Folded Spill
	mov	w0, #0
	bl	_BIT
	ldr	w8, [x22]
	ubfiz	w8, w8, #16, #2
	orr	w21, w8, w0
	cbz	x23, LBB0_4
; %bb.2:
	mov	x0, x23
	bl	_DPU_FORMAT_IS_YUV
	cbz	x0, LBB0_4
; %bb.3:
	mov	w0, #12
	bl	_BIT
	orr	w8, w0, w21
	ldr	w9, [x22, #4]
	ubfiz	w9, w9, #24, #2
	orr	w21, w8, w9
LBB0_4:
	ldr	w8, [x22, #8]
	orr	w21, w21, w8, lsl #31
	ldr	x8, [x22, #112]
	str	x23, [sp, #16]                  ; 8-byte Folded Spill
	cbz	x8, LBB0_7
; %bb.5:
	mov	w0, #4
	bl	_BIT
	b	LBB0_8
LBB0_6:
	mov	w24, #0
	cbnz	x23, LBB0_17
	b	LBB0_20
LBB0_7:
	mov	w0, #0
LBB0_8:
	orr	w27, w21, w0
	mov	x1, x22
	ldr	x8, [x1, #104]!
	ldp	x9, x10, [x1, #-88]
	ldp	w11, w9, [x9]
	and	w25, w11, #0x7f
	ldp	w11, w12, [x10]
	bfi	w25, w11, #8, #7
	bfi	w25, w9, #16, #7
	ldp	x9, x10, [x1, #-72]
	ldp	w11, w9, [x9]
	and	w23, w11, #0x1ffff
	and	w21, w9, #0x1ffff
	ldp	w26, w28, [x10]
	ldp	w9, w15, [x1, #-56]
	and	w9, w9, #0x1ffff
	cbz	x8, LBB0_10
; %bb.9:
	mov	x0, x20
	mov	x2, x19
	str	w12, [sp, #4]                   ; 4-byte Folded Spill
	str	x20, [sp, #8]                   ; 8-byte Folded Spill
	mov	x20, x19
	mov	x19, x25
	mov	x25, x15
	mov	x24, x9
	bl	__dpu_hw_setup_scaler3_de
	mov	w0, #8
	bl	_BIT
	mov	x9, x24
	mov	x15, x25
	mov	x25, x19
	mov	x19, x20
	ldr	x20, [sp, #8]                   ; 8-byte Folded Reload
	ldr	w12, [sp, #4]                   ; 4-byte Folded Reload
	orr	w24, w0, w27
	b	LBB0_11
LBB0_10:
	mov	x24, x27
LBB0_11:
	bfi	w25, w12, #24, #7
	orr	w8, w23, w26, lsl #16
	str	w8, [sp, #8]                    ; 4-byte Folded Spill
	orr	w28, w21, w28, lsl #16
	ldr	x8, [x22, #96]
	orr	w26, w9, w15, lsl #16
	cbz	x8, LBB0_13
; %bb.12:
	mov	x0, x20
	mov	x1, x22
	mov	x2, x19
	bl	__dpu_hw_setup_scaler3_lut
LBB0_13:
	mov	w8, #4098
	ldr	w21, [sp, #28]                  ; 4-byte Folded Reload
	cmp	w21, w8
	ldr	x23, [sp, #16]                  ; 8-byte Folded Reload
	b.ne	LBB0_15
; %bb.14:
	ldp	x8, x9, [x22, #56]
	ldp	w10, w8, [x8]
	and	w2, w10, #0x3f
	ldp	w10, w9, [x9]
	bfi	w2, w10, #8, #6
	bfi	w2, w8, #16, #6
	bfi	w2, w9, #24, #6
Lloh0:
	adrp	x8, _QSEED3_PHASE_INIT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _QSEED3_PHASE_INIT@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	add	w1, w8, w19
	b	LBB0_16
LBB0_15:
Lloh3:
	adrp	x8, _QSEED3_PHASE_INIT_Y_H@GOTPAGE
Lloh4:
	ldr	x8, [x8, _QSEED3_PHASE_INIT_Y_H@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	add	w1, w8, w19
	ldr	x8, [x22, #56]
	ldr	w8, [x8]
	and	w2, w8, #0x1fffff
	mov	x0, x20
	bl	_DPU_REG_WRITE
Lloh6:
	adrp	x8, _QSEED3_PHASE_INIT_Y_V@GOTPAGE
Lloh7:
	ldr	x8, [x8, _QSEED3_PHASE_INIT_Y_V@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	add	w1, w8, w19
	ldr	x8, [x22, #64]
	ldr	w8, [x8]
	and	w2, w8, #0x1fffff
	mov	x0, x20
	bl	_DPU_REG_WRITE
Lloh9:
	adrp	x8, _QSEED3_PHASE_INIT_UV_H@GOTPAGE
Lloh10:
	ldr	x8, [x8, _QSEED3_PHASE_INIT_UV_H@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	add	w1, w8, w19
	ldr	x8, [x22, #56]
	ldr	w8, [x8, #4]
	and	w2, w8, #0x1fffff
	mov	x0, x20
	bl	_DPU_REG_WRITE
Lloh12:
	adrp	x8, _QSEED3_PHASE_INIT_UV_V@GOTPAGE
Lloh13:
	ldr	x8, [x8, _QSEED3_PHASE_INIT_UV_V@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	add	w1, w8, w19
	ldr	x8, [x22, #64]
	ldr	w8, [x8, #4]
	and	w2, w8, #0x1fffff
LBB0_16:
	mov	x0, x20
	bl	_DPU_REG_WRITE
	ldr	w27, [sp, #8]                   ; 4-byte Folded Reload
Lloh15:
	adrp	x8, _QSEED3_PHASE_STEP_Y_H@GOTPAGE
Lloh16:
	ldr	x8, [x8, _QSEED3_PHASE_STEP_Y_H@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	add	w1, w8, w19
	ldr	x8, [x22, #72]
	ldr	w8, [x8]
	and	w2, w8, #0xffffff
	mov	x0, x20
	bl	_DPU_REG_WRITE
Lloh18:
	adrp	x8, _QSEED3_PHASE_STEP_Y_V@GOTPAGE
Lloh19:
	ldr	x8, [x8, _QSEED3_PHASE_STEP_Y_V@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	add	w1, w8, w19
	ldr	x8, [x22, #80]
	ldr	w8, [x8]
	and	w2, w8, #0xffffff
	mov	x0, x20
	bl	_DPU_REG_WRITE
Lloh21:
	adrp	x8, _QSEED3_PHASE_STEP_UV_H@GOTPAGE
Lloh22:
	ldr	x8, [x8, _QSEED3_PHASE_STEP_UV_H@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	add	w1, w8, w19
	ldr	x8, [x22, #72]
	ldr	w8, [x8, #4]
	and	w2, w8, #0xffffff
	mov	x0, x20
	bl	_DPU_REG_WRITE
Lloh24:
	adrp	x8, _QSEED3_PHASE_STEP_UV_V@GOTPAGE
Lloh25:
	ldr	x8, [x8, _QSEED3_PHASE_STEP_UV_V@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	add	w1, w8, w19
	ldr	x8, [x22, #80]
	ldr	w8, [x8, #4]
	and	w2, w8, #0xffffff
	mov	x0, x20
	bl	_DPU_REG_WRITE
Lloh27:
	adrp	x8, _QSEED3_PRELOAD@GOTPAGE
Lloh28:
	ldr	x8, [x8, _QSEED3_PRELOAD@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	add	w1, w8, w19
	mov	x0, x20
	mov	x2, x25
	bl	_DPU_REG_WRITE
Lloh30:
	adrp	x8, _QSEED3_SRC_SIZE_Y_RGB_A@GOTPAGE
Lloh31:
	ldr	x8, [x8, _QSEED3_SRC_SIZE_Y_RGB_A@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
	add	w1, w8, w19
	mov	x0, x20
	mov	x2, x27
	bl	_DPU_REG_WRITE
Lloh33:
	adrp	x8, _QSEED3_SRC_SIZE_UV@GOTPAGE
Lloh34:
	ldr	x8, [x8, _QSEED3_SRC_SIZE_UV@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
	add	w1, w8, w19
	mov	x0, x20
	mov	x2, x28
	bl	_DPU_REG_WRITE
Lloh36:
	adrp	x8, _QSEED3_DST_SIZE@GOTPAGE
Lloh37:
	ldr	x8, [x8, _QSEED3_DST_SIZE@GOTPAGEOFF]
Lloh38:
	ldr	w8, [x8]
	add	w1, w8, w19
	mov	x0, x20
	mov	x2, x26
	bl	_DPU_REG_WRITE
	cbz	x23, LBB0_20
LBB0_17:
	mov	x0, x23
	bl	_DPU_FORMAT_IS_DX
	cbz	w0, LBB0_21
; %bb.18:
	ldr	x8, [x23]
	cbz	x8, LBB0_20
LBB0_19:
	mov	w0, #10
	bl	_BIT
	orr	w8, w0, w24
	ldr	w9, [x22, #88]
	mov	w10, #4098
	ubfiz	w11, w9, #29, #2
	orr	w11, w11, w8
	ubfiz	w9, w9, #30, #1
	orr	w8, w9, w8
	cmp	w21, w10
	csel	w24, w11, w8, ne
LBB0_20:
Lloh39:
	adrp	x8, _QSEED3_OP_MODE@GOTPAGE
Lloh40:
	ldr	x8, [x8, _QSEED3_OP_MODE@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
	add	w1, w8, w19
	mov	x0, x20
	mov	x2, x24
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	b	_DPU_REG_WRITE
LBB0_21:
	mov	w0, #14
	bl	_BIT
	orr	w24, w0, w24
	ldr	x8, [x23]
	cbnz	x8, LBB0_19
	b	LBB0_20
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.cfi_endproc
                                        ; -- End function
	.comm	_QSEED3_PHASE_INIT,4,2          ; @QSEED3_PHASE_INIT
	.comm	_QSEED3_PHASE_INIT_Y_H,4,2      ; @QSEED3_PHASE_INIT_Y_H
	.comm	_QSEED3_PHASE_INIT_Y_V,4,2      ; @QSEED3_PHASE_INIT_Y_V
	.comm	_QSEED3_PHASE_INIT_UV_H,4,2     ; @QSEED3_PHASE_INIT_UV_H
	.comm	_QSEED3_PHASE_INIT_UV_V,4,2     ; @QSEED3_PHASE_INIT_UV_V
	.comm	_QSEED3_PHASE_STEP_Y_H,4,2      ; @QSEED3_PHASE_STEP_Y_H
	.comm	_QSEED3_PHASE_STEP_Y_V,4,2      ; @QSEED3_PHASE_STEP_Y_V
	.comm	_QSEED3_PHASE_STEP_UV_H,4,2     ; @QSEED3_PHASE_STEP_UV_H
	.comm	_QSEED3_PHASE_STEP_UV_V,4,2     ; @QSEED3_PHASE_STEP_UV_V
	.comm	_QSEED3_PRELOAD,4,2             ; @QSEED3_PRELOAD
	.comm	_QSEED3_SRC_SIZE_Y_RGB_A,4,2    ; @QSEED3_SRC_SIZE_Y_RGB_A
	.comm	_QSEED3_SRC_SIZE_UV,4,2         ; @QSEED3_SRC_SIZE_UV
	.comm	_QSEED3_DST_SIZE,4,2            ; @QSEED3_DST_SIZE
	.comm	_QSEED3_OP_MODE,4,2             ; @QSEED3_OP_MODE
.subsections_via_symbols
