	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_gmc_pd_addr             ## -- Begin function amdgpu_gmc_pd_addr
	.p2align	4, 0x90
_amdgpu_gmc_pd_addr:                    ## @amdgpu_gmc_pd_addr
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	movl	(%rdi), %edi
	callq	_amdgpu_ttm_adev
	movq	(%rax), %rax
	movq	_CHIP_VEGA10@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_1
## %bb.2:
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_amdgpu_bo_gpu_offset           ## TAILCALL
LBB0_1:
	movq	_AMDGPU_PTE_VALID@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -12(%rbp)
	leaq	-16(%rbp), %rdx
	leaq	-12(%rbp), %rcx
	movq	%rbx, %rdi
	movl	$-1, %esi
	callq	_amdgpu_gmc_get_pde_for_bo
	movl	-16(%rbp), %eax
	orl	-12(%rbp), %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CHIP_VEGA10,8,3                ## @CHIP_VEGA10
	.comm	_AMDGPU_PTE_VALID,4,2           ## @AMDGPU_PTE_VALID
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_gmc_pd_addr             ; -- Begin function amdgpu_gmc_pd_addr
	.p2align	2
_amdgpu_gmc_pd_addr:                    ; @amdgpu_gmc_pd_addr
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #48
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	w0, [x0]
	bl	_amdgpu_ttm_adev
	ldr	x8, [x0]
Lloh0:
	adrp	x9, _CHIP_VEGA10@GOTPAGE
Lloh1:
	ldr	x9, [x9, _CHIP_VEGA10@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_2
; %bb.1:
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	b	_amdgpu_bo_gpu_offset
LBB0_2:
Lloh3:
	adrp	x8, _AMDGPU_PTE_VALID@GOTPAGE
Lloh4:
	ldr	x8, [x8, _AMDGPU_PTE_VALID@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	str	w8, [sp, #8]
	add	x2, sp, #12
	add	x3, sp, #8
	mov	x0, x19
	mov	w1, #-1
	bl	_amdgpu_gmc_get_pde_for_bo
	ldp	w8, w9, [sp, #8]
	orr	w0, w9, w8
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_CHIP_VEGA10,8,3                ; @CHIP_VEGA10
	.comm	_AMDGPU_PTE_VALID,4,2           ; @AMDGPU_PTE_VALID
.subsections_via_symbols
