	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function zynq_fpga_ops_write_init
_zynq_fpga_ops_write_init:              ## @zynq_fpga_ops_write_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rcx, %r15
	movq	%rdx, -64(%rbp)                 ## 8-byte Spill
	movq	%rsi, %r14
	movq	%rdi, %r12
	movq	8(%rdi), %r13
	movl	(%r13), %edi
	callq	_clk_enable
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_24
## %bb.1:
	movq	%r15, -56(%rbp)                 ## 8-byte Spill
	movq	%r12, -48(%rbp)                 ## 8-byte Spill
	movl	(%r14), %eax
	movq	_FPGA_MGR_ENCRYPTED_BITSTREAM@GOTPCREL(%rip), %rbx
	testl	%eax, (%rbx)
	movq	%r13, %r12
	movq	-64(%rbp), %r15                 ## 8-byte Reload
	je	LBB0_4
## %bb.2:
	movq	_CTRL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_zynq_fpga_read
	movq	_CTRL_SEC_EN_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_7
## %bb.3:
	movl	(%r14), %eax
LBB0_4:
	movq	%rbx, %r13
	movq	_FPGA_MGR_PARTIAL_RECONFIG@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_5
LBB0_16:
	movq	_CTRL_OFFSET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_zynq_fpga_read
	movl	(%r13), %edi
	movl	(%rbx), %esi
	movq	_CTRL_PCAP_PR_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_CTRL_PCAP_MODE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%edi, (%r14)
	je	LBB0_18
## %bb.17:
	movq	_CTRL_PCAP_RATE_EN_MASK@GOTPCREL(%rip), %rdi
	orl	%eax, %edx
	orl	%ecx, %edx
	orl	(%rdi), %edx
	jmp	LBB0_19
LBB0_5:
	movq	%r15, %rdi
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
	callq	_zynq_fpga_has_sync
	testl	%eax, %eax
	je	LBB0_6
## %bb.10:
	movl	4(%r12), %edi
	movq	_SLCR_FPGA_RST_CTRL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_FPGA_RST_ALL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_regmap_write
	movl	4(%r12), %edi
	movq	_SLCR_LVL_SHFTR_EN_OFFSET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_LVL_SHFTR_DISABLE_ALL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_regmap_write
	movl	4(%r12), %edi
	movl	(%rbx), %esi
	movq	_LVL_SHFTR_ENABLE_PS_TO_PL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_regmap_write
	movq	_CTRL_OFFSET@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r12, %rdi
	callq	_zynq_fpga_read
	movq	_CTRL_PCFG_PROG_B_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r15), %esi
	movq	%r12, %rdi
	movl	%eax, %edx
	callq	_zynq_fpga_write
	movq	_STATUS_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_INIT_POLL_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	movq	_INIT_POLL_TIMEOUT@GOTPCREL(%rip), %rax
	movl	(%rax), %r9d
	movq	%r12, %rdi
	xorl	%ecx, %ecx
	callq	_zynq_fpga_poll_timeout
	testl	%eax, %eax
	je	LBB0_13
LBB0_11:
	movl	%eax, %ebx
	leaq	L_.str.2(%rip), %rsi
	jmp	LBB0_12
LBB0_7:
	leaq	L_.str(%rip), %rsi
	jmp	LBB0_8
LBB0_18:
	orl	%eax, %edx
	orl	%ecx, %edx
LBB0_19:
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	movq	%r12, %rdi
	callq	_zynq_fpga_write
	movq	_STATUS_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_zynq_fpga_read
	movq	_STATUS_DMA_Q_F@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	jne	LBB0_21
## %bb.20:
	movq	_STATUS_DMA_Q_E@GOTPCREL(%rip), %rcx
	notl	%eax
	testl	%eax, (%rcx)
	jne	LBB0_21
## %bb.22:
	movq	_MCTRL_OFFSET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_zynq_fpga_read
	movl	(%rbx), %esi
	movq	_MCTRL_PCAP_LPBK_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	%r12, %rdi
	callq	_zynq_fpga_write
	xorl	%ebx, %ebx
	jmp	LBB0_23
LBB0_21:
	leaq	L_.str.4(%rip), %rsi
	movq	%rbx, %rdi
	callq	_dev_err
	movq	_EBUSY@GOTPCREL(%rip), %rax
	jmp	LBB0_9
LBB0_6:
	leaq	L_.str.1(%rip), %rsi
LBB0_8:
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_dev_err
	movq	_EINVAL@GOTPCREL(%rip), %rax
LBB0_9:
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
LBB0_23:
	movl	(%r12), %edi
	callq	_clk_disable
LBB0_24:
	movl	%ebx, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_13:
	movl	(%r15), %esi
	movq	%r12, %rdi
	callq	_zynq_fpga_read
	movq	_CTRL_PCFG_PROG_B_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movl	(%r15), %esi
	movq	%r12, %rdi
	callq	_zynq_fpga_write
	movq	_STATUS_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_INIT_POLL_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	movq	_INIT_POLL_TIMEOUT@GOTPCREL(%rip), %rax
	movl	(%rax), %r9d
	movq	%r12, %rdi
	movl	$1, %ecx
	callq	_zynq_fpga_poll_timeout
	testl	%eax, %eax
	je	LBB0_15
## %bb.14:
	movl	%eax, %ebx
	leaq	L_.str.3(%rip), %rsi
LBB0_12:
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_dev_err
	jmp	LBB0_23
LBB0_15:
	movl	(%r15), %esi
	movq	%r12, %rdi
	callq	_zynq_fpga_read
	movq	_CTRL_PCFG_PROG_B_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r15), %esi
	movq	%r12, %rdi
	movl	%eax, %edx
	callq	_zynq_fpga_write
	movq	_STATUS_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_INIT_POLL_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	movq	_INIT_POLL_TIMEOUT@GOTPCREL(%rip), %rax
	movl	(%rax), %r9d
	movq	%r12, %rdi
	xorl	%ecx, %ecx
	callq	_zynq_fpga_poll_timeout
	testl	%eax, %eax
	jne	LBB0_11
	jmp	LBB0_16
	.cfi_endproc
                                        ## -- End function
	.comm	_FPGA_MGR_ENCRYPTED_BITSTREAM,4,2 ## @FPGA_MGR_ENCRYPTED_BITSTREAM
	.comm	_CTRL_OFFSET,4,2                ## @CTRL_OFFSET
	.comm	_CTRL_SEC_EN_MASK,4,2           ## @CTRL_SEC_EN_MASK
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"System not secure, can't use crypted bitstreams\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_FPGA_MGR_PARTIAL_RECONFIG,4,2  ## @FPGA_MGR_PARTIAL_RECONFIG
L_.str.1:                               ## @.str.1
	.asciz	"Invalid bitstream, could not find a sync word. Bitstream must be a byte swapped .bin file\n"

	.comm	_SLCR_FPGA_RST_CTRL_OFFSET,4,2  ## @SLCR_FPGA_RST_CTRL_OFFSET
	.comm	_FPGA_RST_ALL_MASK,4,2          ## @FPGA_RST_ALL_MASK
	.comm	_SLCR_LVL_SHFTR_EN_OFFSET,4,2   ## @SLCR_LVL_SHFTR_EN_OFFSET
	.comm	_LVL_SHFTR_DISABLE_ALL_MASK,4,2 ## @LVL_SHFTR_DISABLE_ALL_MASK
	.comm	_LVL_SHFTR_ENABLE_PS_TO_PL,4,2  ## @LVL_SHFTR_ENABLE_PS_TO_PL
	.comm	_CTRL_PCFG_PROG_B_MASK,4,2      ## @CTRL_PCFG_PROG_B_MASK
	.comm	_STATUS_OFFSET,4,2              ## @STATUS_OFFSET
	.comm	_STATUS_PCFG_INIT_MASK,4,2      ## @STATUS_PCFG_INIT_MASK
	.comm	_INIT_POLL_DELAY,4,2            ## @INIT_POLL_DELAY
	.comm	_INIT_POLL_TIMEOUT,4,2          ## @INIT_POLL_TIMEOUT
L_.str.2:                               ## @.str.2
	.asciz	"Timeout waiting for PCFG_INIT\n"

L_.str.3:                               ## @.str.3
	.asciz	"Timeout waiting for !PCFG_INIT\n"

	.comm	_CTRL_PCAP_PR_MASK,4,2          ## @CTRL_PCAP_PR_MASK
	.comm	_CTRL_PCAP_MODE_MASK,4,2        ## @CTRL_PCAP_MODE_MASK
	.comm	_CTRL_PCAP_RATE_EN_MASK,4,2     ## @CTRL_PCAP_RATE_EN_MASK
	.comm	_STATUS_DMA_Q_F,4,2             ## @STATUS_DMA_Q_F
	.comm	_STATUS_DMA_Q_E,4,2             ## @STATUS_DMA_Q_E
L_.str.4:                               ## @.str.4
	.asciz	"DMA command queue not right\n"

	.comm	_EBUSY,4,2                      ## @EBUSY
	.comm	_MCTRL_OFFSET,4,2               ## @MCTRL_OFFSET
	.comm	_MCTRL_PCAP_LPBK_MASK,4,2       ## @MCTRL_PCAP_LPBK_MASK
	.no_dead_strip	_zynq_fpga_ops_write_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function zynq_fpga_ops_write_init
_zynq_fpga_ops_write_init:              ; @zynq_fpga_ops_write_init
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x23, x3
	mov	x24, x2
	mov	x21, x1
	mov	x20, x0
	ldr	x19, [x0, #8]
	ldr	w0, [x19]
	bl	_clk_enable
	mov	x22, x0
	cbnz	w0, LBB0_20
; %bb.1:
	ldr	w8, [x21]
Lloh0:
	adrp	x26, _FPGA_MGR_ENCRYPTED_BITSTREAM@GOTPAGE
Lloh1:
	ldr	x26, [x26, _FPGA_MGR_ENCRYPTED_BITSTREAM@GOTPAGEOFF]
	ldr	w9, [x26]
Lloh2:
	adrp	x25, _CTRL_OFFSET@GOTPAGE
Lloh3:
	ldr	x25, [x25, _CTRL_OFFSET@GOTPAGEOFF]
	tst	w9, w8
	b.eq	LBB0_4
; %bb.2:
	ldr	w1, [x25]
	mov	x0, x19
	bl	_zynq_fpga_read
Lloh4:
	adrp	x8, _CTRL_SEC_EN_MASK@GOTPAGE
Lloh5:
	ldr	x8, [x8, _CTRL_SEC_EN_MASK@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_10
; %bb.3:
	ldr	w8, [x21]
LBB0_4:
Lloh7:
	adrp	x9, _FPGA_MGR_PARTIAL_RECONFIG@GOTPAGE
Lloh8:
	ldr	x9, [x9, _FPGA_MGR_PARTIAL_RECONFIG@GOTPAGEOFF]
Lloh9:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_7
LBB0_5:
	ldr	w1, [x25]
	mov	x0, x19
	bl	_zynq_fpga_read
	ldr	w10, [x21]
	ldr	w11, [x26]
Lloh10:
	adrp	x8, _CTRL_PCAP_PR_MASK@GOTPAGE
Lloh11:
	ldr	x8, [x8, _CTRL_PCAP_PR_MASK@GOTPAGEOFF]
	ldr	w1, [x25]
Lloh12:
	ldr	w8, [x8]
Lloh13:
	adrp	x9, _CTRL_PCAP_MODE_MASK@GOTPAGE
Lloh14:
	ldr	x9, [x9, _CTRL_PCAP_MODE_MASK@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	tst	w11, w10
	b.eq	LBB0_11
; %bb.6:
Lloh16:
	adrp	x10, _CTRL_PCAP_RATE_EN_MASK@GOTPAGE
Lloh17:
	ldr	x10, [x10, _CTRL_PCAP_RATE_EN_MASK@GOTPAGEOFF]
Lloh18:
	ldr	w10, [x10]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w2, w8, w10
	b	LBB0_12
LBB0_7:
	mov	x0, x24
	mov	x1, x23
	bl	_zynq_fpga_has_sync
	cbz	w0, LBB0_16
; %bb.8:
	ldr	w0, [x19, #4]
Lloh19:
	adrp	x8, _SLCR_FPGA_RST_CTRL_OFFSET@GOTPAGE
Lloh20:
	ldr	x8, [x8, _SLCR_FPGA_RST_CTRL_OFFSET@GOTPAGEOFF]
Lloh21:
	ldr	w1, [x8]
Lloh22:
	adrp	x8, _FPGA_RST_ALL_MASK@GOTPAGE
Lloh23:
	ldr	x8, [x8, _FPGA_RST_ALL_MASK@GOTPAGEOFF]
Lloh24:
	ldr	w2, [x8]
	bl	_regmap_write
	ldr	w0, [x19, #4]
Lloh25:
	adrp	x22, _SLCR_LVL_SHFTR_EN_OFFSET@GOTPAGE
Lloh26:
	ldr	x22, [x22, _SLCR_LVL_SHFTR_EN_OFFSET@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh27:
	adrp	x8, _LVL_SHFTR_DISABLE_ALL_MASK@GOTPAGE
Lloh28:
	ldr	x8, [x8, _LVL_SHFTR_DISABLE_ALL_MASK@GOTPAGEOFF]
Lloh29:
	ldr	w2, [x8]
	bl	_regmap_write
	ldr	w0, [x19, #4]
	ldr	w1, [x22]
Lloh30:
	adrp	x8, _LVL_SHFTR_ENABLE_PS_TO_PL@GOTPAGE
Lloh31:
	ldr	x8, [x8, _LVL_SHFTR_ENABLE_PS_TO_PL@GOTPAGEOFF]
Lloh32:
	ldr	w2, [x8]
	bl	_regmap_write
	ldr	w1, [x25]
	mov	x0, x19
	bl	_zynq_fpga_read
Lloh33:
	adrp	x23, _CTRL_PCFG_PROG_B_MASK@GOTPAGE
Lloh34:
	ldr	x23, [x23, _CTRL_PCFG_PROG_B_MASK@GOTPAGEOFF]
	ldr	w8, [x23]
	orr	w2, w8, w0
	ldr	w1, [x25]
	mov	x0, x19
	bl	_zynq_fpga_write
Lloh35:
	adrp	x24, _STATUS_OFFSET@GOTPAGE
Lloh36:
	ldr	x24, [x24, _STATUS_OFFSET@GOTPAGEOFF]
	ldr	w1, [x24]
Lloh37:
	adrp	x27, _INIT_POLL_DELAY@GOTPAGE
Lloh38:
	ldr	x27, [x27, _INIT_POLL_DELAY@GOTPAGEOFF]
	ldr	w4, [x27]
Lloh39:
	adrp	x28, _INIT_POLL_TIMEOUT@GOTPAGE
Lloh40:
	ldr	x28, [x28, _INIT_POLL_TIMEOUT@GOTPAGEOFF]
	ldr	w5, [x28]
	mov	x0, x19
	mov	w3, #0
	bl	_zynq_fpga_poll_timeout
	cbz	w0, LBB0_21
LBB0_9:
	mov	x22, x0
Lloh41:
	adrp	x1, l_.str.2@PAGE
Lloh42:
	add	x1, x1, l_.str.2@PAGEOFF
	b	LBB0_23
LBB0_10:
Lloh43:
	adrp	x1, l_.str@PAGE
Lloh44:
	add	x1, x1, l_.str@PAGEOFF
	b	LBB0_17
LBB0_11:
	orr	w8, w8, w0
	orr	w2, w8, w9
LBB0_12:
	mov	x0, x19
	bl	_zynq_fpga_write
Lloh45:
	adrp	x8, _STATUS_OFFSET@GOTPAGE
Lloh46:
	ldr	x8, [x8, _STATUS_OFFSET@GOTPAGEOFF]
Lloh47:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_zynq_fpga_read
Lloh48:
	adrp	x8, _STATUS_DMA_Q_F@GOTPAGE
Lloh49:
	ldr	x8, [x8, _STATUS_DMA_Q_F@GOTPAGEOFF]
Lloh50:
	ldr	w8, [x8]
	tst	w8, w0
	b.ne	LBB0_15
; %bb.13:
Lloh51:
	adrp	x8, _STATUS_DMA_Q_E@GOTPAGE
Lloh52:
	ldr	x8, [x8, _STATUS_DMA_Q_E@GOTPAGEOFF]
Lloh53:
	ldr	w8, [x8]
	bics	wzr, w8, w0
	b.ne	LBB0_15
; %bb.14:
Lloh54:
	adrp	x20, _MCTRL_OFFSET@GOTPAGE
Lloh55:
	ldr	x20, [x20, _MCTRL_OFFSET@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_zynq_fpga_read
	ldr	w1, [x20]
Lloh56:
	adrp	x8, _MCTRL_PCAP_LPBK_MASK@GOTPAGE
Lloh57:
	ldr	x8, [x8, _MCTRL_PCAP_LPBK_MASK@GOTPAGEOFF]
Lloh58:
	ldr	w8, [x8]
	bic	w2, w0, w8
	mov	x0, x19
	bl	_zynq_fpga_write
	mov	w22, #0
	b	LBB0_19
LBB0_15:
Lloh59:
	adrp	x1, l_.str.4@PAGE
Lloh60:
	add	x1, x1, l_.str.4@PAGEOFF
	mov	x0, x20
	bl	_dev_err
Lloh61:
	adrp	x8, _EBUSY@GOTPAGE
Lloh62:
	ldr	x8, [x8, _EBUSY@GOTPAGEOFF]
	b	LBB0_18
LBB0_16:
Lloh63:
	adrp	x1, l_.str.1@PAGE
Lloh64:
	add	x1, x1, l_.str.1@PAGEOFF
LBB0_17:
	mov	x0, x20
	bl	_dev_err
Lloh65:
	adrp	x8, _EINVAL@GOTPAGE
Lloh66:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
LBB0_18:
	ldr	w8, [x8]
	neg	w22, w8
LBB0_19:
	ldr	w0, [x19]
	bl	_clk_disable
LBB0_20:
	mov	x0, x22
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
LBB0_21:
	ldr	w1, [x25]
	mov	x0, x19
	bl	_zynq_fpga_read
	ldr	w8, [x23]
	bic	w2, w0, w8
	ldr	w1, [x25]
	mov	x0, x19
	bl	_zynq_fpga_write
	ldr	w1, [x24]
	ldr	w4, [x27]
	ldr	w5, [x28]
	mov	x0, x19
	mov	w3, #1
	bl	_zynq_fpga_poll_timeout
	cbz	w0, LBB0_24
; %bb.22:
	mov	x22, x0
Lloh67:
	adrp	x1, l_.str.3@PAGE
Lloh68:
	add	x1, x1, l_.str.3@PAGEOFF
LBB0_23:
	mov	x0, x20
	bl	_dev_err
	b	LBB0_19
LBB0_24:
	ldr	w1, [x25]
	mov	x0, x19
	bl	_zynq_fpga_read
	ldr	w8, [x23]
	orr	w2, w8, w0
	ldr	w1, [x25]
	mov	x0, x19
	bl	_zynq_fpga_write
	ldr	w1, [x24]
	ldr	w4, [x27]
	ldr	w5, [x28]
	mov	x0, x19
	mov	w3, #0
	bl	_zynq_fpga_poll_timeout
	cbnz	w0, LBB0_9
	b	LBB0_5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpAdd	Lloh41, Lloh42
	.loh AdrpAdd	Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGot	Lloh54, Lloh55
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpAdd	Lloh59, Lloh60
	.loh AdrpAdd	Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpAdd	Lloh67, Lloh68
	.cfi_endproc
                                        ; -- End function
	.comm	_FPGA_MGR_ENCRYPTED_BITSTREAM,4,2 ; @FPGA_MGR_ENCRYPTED_BITSTREAM
	.comm	_CTRL_OFFSET,4,2                ; @CTRL_OFFSET
	.comm	_CTRL_SEC_EN_MASK,4,2           ; @CTRL_SEC_EN_MASK
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"System not secure, can't use crypted bitstreams\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_FPGA_MGR_PARTIAL_RECONFIG,4,2  ; @FPGA_MGR_PARTIAL_RECONFIG
l_.str.1:                               ; @.str.1
	.asciz	"Invalid bitstream, could not find a sync word. Bitstream must be a byte swapped .bin file\n"

	.comm	_SLCR_FPGA_RST_CTRL_OFFSET,4,2  ; @SLCR_FPGA_RST_CTRL_OFFSET
	.comm	_FPGA_RST_ALL_MASK,4,2          ; @FPGA_RST_ALL_MASK
	.comm	_SLCR_LVL_SHFTR_EN_OFFSET,4,2   ; @SLCR_LVL_SHFTR_EN_OFFSET
	.comm	_LVL_SHFTR_DISABLE_ALL_MASK,4,2 ; @LVL_SHFTR_DISABLE_ALL_MASK
	.comm	_LVL_SHFTR_ENABLE_PS_TO_PL,4,2  ; @LVL_SHFTR_ENABLE_PS_TO_PL
	.comm	_CTRL_PCFG_PROG_B_MASK,4,2      ; @CTRL_PCFG_PROG_B_MASK
	.comm	_STATUS_OFFSET,4,2              ; @STATUS_OFFSET
	.comm	_STATUS_PCFG_INIT_MASK,4,2      ; @STATUS_PCFG_INIT_MASK
	.comm	_INIT_POLL_DELAY,4,2            ; @INIT_POLL_DELAY
	.comm	_INIT_POLL_TIMEOUT,4,2          ; @INIT_POLL_TIMEOUT
l_.str.2:                               ; @.str.2
	.asciz	"Timeout waiting for PCFG_INIT\n"

l_.str.3:                               ; @.str.3
	.asciz	"Timeout waiting for !PCFG_INIT\n"

	.comm	_CTRL_PCAP_PR_MASK,4,2          ; @CTRL_PCAP_PR_MASK
	.comm	_CTRL_PCAP_MODE_MASK,4,2        ; @CTRL_PCAP_MODE_MASK
	.comm	_CTRL_PCAP_RATE_EN_MASK,4,2     ; @CTRL_PCAP_RATE_EN_MASK
	.comm	_STATUS_DMA_Q_F,4,2             ; @STATUS_DMA_Q_F
	.comm	_STATUS_DMA_Q_E,4,2             ; @STATUS_DMA_Q_E
l_.str.4:                               ; @.str.4
	.asciz	"DMA command queue not right\n"

	.comm	_EBUSY,4,2                      ; @EBUSY
	.comm	_MCTRL_OFFSET,4,2               ; @MCTRL_OFFSET
	.comm	_MCTRL_PCAP_LPBK_MASK,4,2       ; @MCTRL_PCAP_LPBK_MASK
	.no_dead_strip	_zynq_fpga_ops_write_init
.subsections_via_symbols
