	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function df_v3_6_update_medium_grain_clock_gating
_df_v3_6_update_medium_grain_clock_gating: ## @df_v3_6_update_medium_grain_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %rbx
	movq	8(%rdi), %rax
	movl	$1, %esi
	callq	*(%rax)
	testl	%r14d, %r14d
	je	LBB0_3
## %bb.1:
	movq	_AMD_CG_SUPPORT_DF_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rbx)
	je	LBB0_3
## %bb.2:
	movq	_DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY@GOTPCREL(%rip), %r14
	jmp	LBB0_4
LBB0_3:
	movq	_DF_V3_6_MGCG_DISABLE@GOTPCREL(%rip), %r14
LBB0_4:
	movq	_DF@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	movq	_mmDF_PIE_AON0_DfGlobalClkGater@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	orl	(%r14), %ecx
	movl	(%r15), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movq	8(%rbx), %rax
	movq	(%rax), %rax
	movq	%rbx, %rdi
	xorl	%esi, %esi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmpq	*%rax                           ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_CG_SUPPORT_DF_MGCG,4,2     ## @AMD_CG_SUPPORT_DF_MGCG
	.comm	_DF,4,2                         ## @DF
	.comm	_mmDF_PIE_AON0_DfGlobalClkGater,4,2 ## @mmDF_PIE_AON0_DfGlobalClkGater
	.comm	_DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK,4,2 ## @DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK
	.comm	_DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY,4,2 ## @DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY
	.comm	_DF_V3_6_MGCG_DISABLE,4,2       ## @DF_V3_6_MGCG_DISABLE
	.no_dead_strip	_df_v3_6_update_medium_grain_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function df_v3_6_update_medium_grain_clock_gating
_df_v3_6_update_medium_grain_clock_gating: ; @df_v3_6_update_medium_grain_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	mov	x19, x0
	ldr	x8, [x0, #8]
	ldr	x8, [x8]
	mov	w1, #1
	blr	x8
	cbz	w20, LBB0_3
; %bb.1:
	ldr	w8, [x19]
Lloh0:
	adrp	x9, _AMD_CG_SUPPORT_DF_MGCG@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_CG_SUPPORT_DF_MGCG@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_3
; %bb.2:
Lloh3:
	adrp	x20, _DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY@GOTPAGE
Lloh4:
	ldr	x20, [x20, _DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY@GOTPAGEOFF]
	b	LBB0_4
LBB0_3:
Lloh5:
	adrp	x20, _DF_V3_6_MGCG_DISABLE@GOTPAGE
Lloh6:
	ldr	x20, [x20, _DF_V3_6_MGCG_DISABLE@GOTPAGEOFF]
LBB0_4:
Lloh7:
	adrp	x21, _DF@GOTPAGE
Lloh8:
	ldr	x21, [x21, _DF@GOTPAGEOFF]
	ldr	w0, [x21]
Lloh9:
	adrp	x22, _mmDF_PIE_AON0_DfGlobalClkGater@GOTPAGE
Lloh10:
	ldr	x22, [x22, _mmDF_PIE_AON0_DfGlobalClkGater@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh11:
	adrp	x8, _DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK@GOTPAGE
Lloh12:
	ldr	x8, [x8, _DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
	bic	w8, w0, w8
	ldr	w9, [x20]
	orr	w3, w8, w9
	ldr	w0, [x21]
	ldr	w2, [x22]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	x8, [x19, #8]
	ldr	x2, [x8]
	mov	x0, x19
	mov	w1, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	br	x2
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_CG_SUPPORT_DF_MGCG,4,2     ; @AMD_CG_SUPPORT_DF_MGCG
	.comm	_DF,4,2                         ; @DF
	.comm	_mmDF_PIE_AON0_DfGlobalClkGater,4,2 ; @mmDF_PIE_AON0_DfGlobalClkGater
	.comm	_DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK,4,2 ; @DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK
	.comm	_DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY,4,2 ; @DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY
	.comm	_DF_V3_6_MGCG_DISABLE,4,2       ; @DF_V3_6_MGCG_DISABLE
	.no_dead_strip	_df_v3_6_update_medium_grain_clock_gating
.subsections_via_symbols
