	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v2_0_start_dpg_mode
_vcn_v2_0_start_dpg_mode:               ## @vcn_v2_0_start_dpg_mode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r12d
	movq	%rdi, %r14
	movq	24(%rdi), %rax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	callq	_vcn_v2_0_enable_static_power_gating
	movq	_UVD@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movq	_mmUVD_POWER_STATUS@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_UVD_POWER_STATUS__UVD_PG_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_POWER_STATUS__UVD_PG_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r13), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	testl	%r12d, %r12d
	je	LBB0_2
## %bb.1:
	movq	8(%r14), %rax
	movq	%rax, (%r14)
LBB0_2:
	movq	%r14, %rdi
	xorl	%esi, %esi
	movl	%r12d, %edx
	callq	_vcn_v2_0_clock_gating_dpg_mode
	movq	_UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$255, %ebx
	shll	%cl, %ebx
	movq	_UVD_VCPU_CNTL__CLK_EN_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	(%r13), %edi
	movq	_mmUVD_VCPU_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	movl	%ebx, %esi
	xorl	%edx, %edx
	movl	%r12d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%r13), %edi
	movq	_mmUVD_MASTINT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	movl	%r12d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movq	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_UVD_LMI_CTRL__REQ_MODE_MASK@GOTPCREL(%rip), %rax
	movq	_UVD_LMI_CTRL__CRC_RESET_MASK@GOTPCREL(%rip), %rdx
	movq	_UVD_LMI_CTRL__MASK_MC_URGENT_MASK@GOTPCREL(%rip), %rsi
	movq	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPCREL(%rip), %r8
	movq	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$8, %edi
	shll	%cl, %edi
	orl	(%rax), %ebx
	orl	(%rdx), %ebx
	orl	(%rsi), %ebx
	orl	(%r8), %ebx
	movq	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	orl	%edi, %ebx
	orl	$1048576, %ebx                  ## imm = 0x100000
	movl	(%r13), %edi
	movq	_mmUVD_LMI_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	movl	%ebx, %esi
	xorl	%edx, %edx
	movl	%r12d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%r13), %edi
	movq	_mmUVD_MPC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movq	_UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %r15d
	movl	$2, %esi
	shll	%cl, %esi
	movl	%eax, %edi
	xorl	%edx, %edx
	movl	%r12d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%r13), %edi
	movq	_mmUVD_MPC_SET_MUXA0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movq	_UVD_MPC_SET_MUXA0__VARA_2__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %edx
	shll	%cl, %edx
	movq	_UVD_MPC_SET_MUXA0__VARA_1__SHIFT@GOTPCREL(%rip), %rsi
	movq	_UVD_MPC_SET_MUXA0__VARA_3__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$3, %edi
	shll	%cl, %edi
	movb	(%rsi), %cl
	btsl	%ecx, %edx
	movq	_UVD_MPC_SET_MUXA0__VARA_4__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$4, %esi
	shll	%cl, %esi
	movl	$3, %r13d
	movl	$4, %ebx
	orl	%edi, %esi
	orl	%edx, %esi
	movl	%eax, %edi
	xorl	%edx, %edx
	movl	%r12d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movq	_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmUVD_MPC_SET_MUXB0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movq	_UVD_MPC_SET_MUXB0__VARB_2__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %edx
	shll	%cl, %edx
	movq	_UVD_MPC_SET_MUXB0__VARB_3__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r13d
	movq	_UVD_MPC_SET_MUXB0__VARB_4__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movq	_UVD_MPC_SET_MUXB0__VARB_1__SHIFT@GOTPCREL(%rip), %rsi
	shll	%cl, %ebx
	movb	(%rsi), %cl
	btsl	%ecx, %edx
	orl	%r13d, %ebx
	movq	_UVD@GOTPCREL(%rip), %r13
	orl	%edx, %ebx
	movl	%eax, %edi
	movl	%ebx, %esi
	xorl	%edx, %edx
	movl	%r12d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%r13), %edi
	movq	_mmUVD_MPC_SET_MUX@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movq	_UVD_MPC_SET_MUX__SET_1__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %dl
	movq	_UVD_MPC_SET_MUX__SET_2__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r15d
	btsl	%edx, %r15d
	movl	%eax, %edi
	movl	%r15d, %esi
	xorl	%edx, %edx
	movl	%r12d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movq	%r14, %rdi
	movl	%r12d, %esi
	callq	_vcn_v2_0_mc_resume_dpg_mode
	movl	(%r13), %edi
	movq	_mmUVD_REG_XX_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	movl	$16, %esi
	xorl	%edx, %edx
	movl	%r12d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%r13), %edi
	movq	_mmUVD_RBC_XX_IB_REG_CHECK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	movl	$3, %esi
	xorl	%edx, %edx
	movl	%r12d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%r13), %edi
	movq	_mmUVD_SOFT_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	movl	%r12d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%r13), %edi
	movq	_mmUVD_LMI_CTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movq	_UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$31, %esi
	shll	%cl, %esi
	movl	%eax, %edi
	xorl	%edx, %edx
	movl	%r12d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%r13), %edi
	movq	_mmUVD_MASTINT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movq	_UVD_MASTINT_EN__VCPU_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	xorl	%edx, %edx
	movl	%r12d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	testl	%r12d, %r12d
	je	LBB0_4
## %bb.3:
	movl	(%r14), %ecx
	movl	16(%r14), %edx
	subl	8(%r14), %ecx
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_psp_update_vcn_sram
LBB0_4:
	movq	-48(%rbp), %r15                 ## 8-byte Reload
	movl	16(%r15), %edi
	callq	_order_base_2
	movq	_UVD_RBC_RB_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_RB_BUFSZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%edi, %edi
	movl	%eax, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_BLKSZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_NO_FETCH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_NO_UPDATE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_RPTR_WR_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r13), %edi
	movq	_mmUVD_RBC_RB_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmUVD_RBC_RB_WPTR_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %ebx
	movq	_mmUVD_RBC_RB_RPTR_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	8(%r15), %rdi
	callq	_upper_32_bits
	sarl	$2, %eax
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r14d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %ebx
	movq	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	8(%r15), %rdi
	callq	_lower_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r14d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %ebx
	movq	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	8(%r15), %rdi
	callq	_upper_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r14d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmUVD_RBC_RB_RPTR@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmUVD_SCRATCH2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	%rax, (%r15)
	movl	(%r13), %ebx
	movq	_mmUVD_RBC_RB_WPTR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r14d
	movq	%rax, %rdi
	callq	_lower_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r14d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_POWER_STATUS,4,2         ## @mmUVD_POWER_STATUS
	.comm	_UVD_POWER_STATUS__UVD_PG_MODE_MASK,4,2 ## @UVD_POWER_STATUS__UVD_PG_MODE_MASK
	.comm	_UVD_POWER_STATUS__UVD_PG_EN_MASK,4,2 ## @UVD_POWER_STATUS__UVD_PG_EN_MASK
	.comm	_UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT,4,2 ## @UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT
	.comm	_UVD_VCPU_CNTL__CLK_EN_MASK,4,2 ## @UVD_VCPU_CNTL__CLK_EN_MASK
	.comm	_UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK,4,2 ## @UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK
	.comm	_mmUVD_VCPU_CNTL,4,2            ## @mmUVD_VCPU_CNTL
	.comm	_mmUVD_MASTINT_EN,4,2           ## @mmUVD_MASTINT_EN
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK,4,2 ## @UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK
	.comm	_UVD_LMI_CTRL__REQ_MODE_MASK,4,2 ## @UVD_LMI_CTRL__REQ_MODE_MASK
	.comm	_UVD_LMI_CTRL__CRC_RESET_MASK,4,2 ## @UVD_LMI_CTRL__CRC_RESET_MASK
	.comm	_UVD_LMI_CTRL__MASK_MC_URGENT_MASK,4,2 ## @UVD_LMI_CTRL__MASK_MC_URGENT_MASK
	.comm	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK,4,2 ## @UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK,4,2 ## @UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT,4,2 ## @UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT
	.comm	_mmUVD_LMI_CTRL,4,2             ## @mmUVD_LMI_CTRL
	.comm	_mmUVD_MPC_CNTL,4,2             ## @mmUVD_MPC_CNTL
	.comm	_UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT,4,2 ## @UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT
	.comm	_mmUVD_MPC_SET_MUXA0,4,2        ## @mmUVD_MPC_SET_MUXA0
	.comm	_UVD_MPC_SET_MUXA0__VARA_1__SHIFT,4,2 ## @UVD_MPC_SET_MUXA0__VARA_1__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_2__SHIFT,4,2 ## @UVD_MPC_SET_MUXA0__VARA_2__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_3__SHIFT,4,2 ## @UVD_MPC_SET_MUXA0__VARA_3__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_4__SHIFT,4,2 ## @UVD_MPC_SET_MUXA0__VARA_4__SHIFT
	.comm	_mmUVD_MPC_SET_MUXB0,4,2        ## @mmUVD_MPC_SET_MUXB0
	.comm	_UVD_MPC_SET_MUXB0__VARB_1__SHIFT,4,2 ## @UVD_MPC_SET_MUXB0__VARB_1__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_2__SHIFT,4,2 ## @UVD_MPC_SET_MUXB0__VARB_2__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_3__SHIFT,4,2 ## @UVD_MPC_SET_MUXB0__VARB_3__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_4__SHIFT,4,2 ## @UVD_MPC_SET_MUXB0__VARB_4__SHIFT
	.comm	_mmUVD_MPC_SET_MUX,4,2          ## @mmUVD_MPC_SET_MUX
	.comm	_UVD_MPC_SET_MUX__SET_0__SHIFT,4,2 ## @UVD_MPC_SET_MUX__SET_0__SHIFT
	.comm	_UVD_MPC_SET_MUX__SET_1__SHIFT,4,2 ## @UVD_MPC_SET_MUX__SET_1__SHIFT
	.comm	_UVD_MPC_SET_MUX__SET_2__SHIFT,4,2 ## @UVD_MPC_SET_MUX__SET_2__SHIFT
	.comm	_mmUVD_REG_XX_MASK,4,2          ## @mmUVD_REG_XX_MASK
	.comm	_mmUVD_RBC_XX_IB_REG_CHECK,4,2  ## @mmUVD_RBC_XX_IB_REG_CHECK
	.comm	_mmUVD_SOFT_RESET,4,2           ## @mmUVD_SOFT_RESET
	.comm	_mmUVD_LMI_CTRL2,4,2            ## @mmUVD_LMI_CTRL2
	.comm	_UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,4,2 ## @UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT
	.comm	_UVD_MASTINT_EN__VCPU_EN_MASK,4,2 ## @UVD_MASTINT_EN__VCPU_EN_MASK
	.comm	_UVD_RBC_RB_CNTL,4,2            ## @UVD_RBC_RB_CNTL
	.comm	_RB_BUFSZ,4,2                   ## @RB_BUFSZ
	.comm	_RB_BLKSZ,4,2                   ## @RB_BLKSZ
	.comm	_RB_NO_FETCH,4,2                ## @RB_NO_FETCH
	.comm	_RB_NO_UPDATE,4,2               ## @RB_NO_UPDATE
	.comm	_RB_RPTR_WR_EN,4,2              ## @RB_RPTR_WR_EN
	.comm	_mmUVD_RBC_RB_CNTL,4,2          ## @mmUVD_RBC_RB_CNTL
	.comm	_mmUVD_RBC_RB_WPTR_CNTL,4,2     ## @mmUVD_RBC_RB_WPTR_CNTL
	.comm	_mmUVD_RBC_RB_RPTR_ADDR,4,2     ## @mmUVD_RBC_RB_RPTR_ADDR
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
	.comm	_mmUVD_RBC_RB_RPTR,4,2          ## @mmUVD_RBC_RB_RPTR
	.comm	_mmUVD_SCRATCH2,4,2             ## @mmUVD_SCRATCH2
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ## @mmUVD_RBC_RB_WPTR
	.no_dead_strip	_vcn_v2_0_start_dpg_mode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v2_0_start_dpg_mode
_vcn_v2_0_start_dpg_mode:               ; @vcn_v2_0_start_dpg_mode
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x20, x1
	mov	x19, x0
	ldr	x22, [x0, #24]
	bl	_vcn_v2_0_enable_static_power_gating
Lloh0:
	adrp	x23, _UVD@GOTPAGE
Lloh1:
	ldr	x23, [x23, _UVD@GOTPAGEOFF]
	ldr	w0, [x23]
Lloh2:
	adrp	x21, _mmUVD_POWER_STATUS@GOTPAGE
Lloh3:
	ldr	x21, [x21, _mmUVD_POWER_STATUS@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh4:
	adrp	x8, _UVD_POWER_STATUS__UVD_PG_MODE_MASK@GOTPAGE
Lloh5:
	ldr	x8, [x8, _UVD_POWER_STATUS__UVD_PG_MODE_MASK@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh7:
	adrp	x9, _UVD_POWER_STATUS__UVD_PG_EN_MASK@GOTPAGE
Lloh8:
	ldr	x9, [x9, _UVD_POWER_STATUS__UVD_PG_EN_MASK@GOTPAGEOFF]
Lloh9:
	ldr	w9, [x9]
	orr	w3, w8, w9
	ldr	w0, [x23]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_WREG32_SOC15
	cbz	w20, LBB0_2
; %bb.1:
	ldr	x8, [x19, #8]
	str	x8, [x19]
LBB0_2:
	mov	x0, x19
	mov	w1, #0
	mov	x2, x20
	bl	_vcn_v2_0_clock_gating_dpg_mode
Lloh10:
	adrp	x8, _UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT@GOTPAGE
Lloh11:
	ldr	x8, [x8, _UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	mov	w9, #255
	lsl	w8, w9, w8
Lloh13:
	adrp	x9, _UVD_VCPU_CNTL__CLK_EN_MASK@GOTPAGE
Lloh14:
	ldr	x9, [x9, _UVD_VCPU_CNTL__CLK_EN_MASK@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh16:
	adrp	x9, _UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK@GOTPAGE
Lloh17:
	ldr	x9, [x9, _UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	orr	w21, w8, w9
	ldr	w0, [x23]
Lloh19:
	adrp	x8, _mmUVD_VCPU_CNTL@GOTPAGE
Lloh20:
	ldr	x8, [x8, _mmUVD_VCPU_CNTL@GOTPAGEOFF]
Lloh21:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	x1, x21
	mov	w2, #0
	mov	x3, x20
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh22:
	adrp	x24, _mmUVD_MASTINT_EN@GOTPAGE
Lloh23:
	ldr	x24, [x24, _mmUVD_MASTINT_EN@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	w1, #0
	mov	w2, #0
	mov	x3, x20
	bl	_WREG32_SOC15_DPG_MODE_2_0
Lloh24:
	adrp	x8, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPAGE
Lloh25:
	ldr	x8, [x8, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPAGEOFF]
Lloh26:
	adrp	x9, _UVD_LMI_CTRL__REQ_MODE_MASK@GOTPAGE
Lloh27:
	ldr	x9, [x9, _UVD_LMI_CTRL__REQ_MODE_MASK@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
Lloh29:
	ldr	w9, [x9]
Lloh30:
	adrp	x10, _UVD_LMI_CTRL__CRC_RESET_MASK@GOTPAGE
Lloh31:
	ldr	x10, [x10, _UVD_LMI_CTRL__CRC_RESET_MASK@GOTPAGEOFF]
Lloh32:
	adrp	x11, _UVD_LMI_CTRL__MASK_MC_URGENT_MASK@GOTPAGE
Lloh33:
	ldr	x11, [x11, _UVD_LMI_CTRL__MASK_MC_URGENT_MASK@GOTPAGEOFF]
Lloh34:
	ldr	w10, [x10]
Lloh35:
	ldr	w11, [x11]
Lloh36:
	adrp	x12, _UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPAGE
Lloh37:
	ldr	x12, [x12, _UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPAGEOFF]
Lloh38:
	adrp	x13, _UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPAGE
Lloh39:
	ldr	x13, [x13, _UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPAGEOFF]
Lloh40:
	ldr	w12, [x12]
Lloh41:
	ldr	w13, [x13]
Lloh42:
	adrp	x14, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT@GOTPAGE
Lloh43:
	ldr	x14, [x14, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT@GOTPAGEOFF]
Lloh44:
	ldr	w14, [x14]
	mov	w15, #8
	lsl	w14, w15, w14
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w8, w8, w13
	orr	w8, w8, w14
	orr	w21, w8, #0x100000
	ldr	w0, [x23]
Lloh45:
	adrp	x8, _mmUVD_LMI_CTRL@GOTPAGE
Lloh46:
	ldr	x8, [x8, _mmUVD_LMI_CTRL@GOTPAGEOFF]
Lloh47:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	x1, x21
	mov	w2, #0
	mov	x3, x20
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh48:
	adrp	x8, _mmUVD_MPC_CNTL@GOTPAGE
Lloh49:
	ldr	x8, [x8, _mmUVD_MPC_CNTL@GOTPAGEOFF]
Lloh50:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
Lloh51:
	adrp	x8, _UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT@GOTPAGE
Lloh52:
	ldr	x8, [x8, _UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT@GOTPAGEOFF]
Lloh53:
	ldr	w8, [x8]
	mov	w21, #2
	lsl	w1, w21, w8
	mov	w2, #0
	mov	x3, x20
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh54:
	adrp	x8, _mmUVD_MPC_SET_MUXA0@GOTPAGE
Lloh55:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXA0@GOTPAGEOFF]
Lloh56:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
Lloh57:
	adrp	x8, _UVD_MPC_SET_MUXA0__VARA_1__SHIFT@GOTPAGE
Lloh58:
	ldr	x8, [x8, _UVD_MPC_SET_MUXA0__VARA_1__SHIFT@GOTPAGEOFF]
Lloh59:
	ldr	w8, [x8]
	mov	w25, #1
	lsl	w8, w25, w8
Lloh60:
	adrp	x9, _UVD_MPC_SET_MUXA0__VARA_2__SHIFT@GOTPAGE
Lloh61:
	ldr	x9, [x9, _UVD_MPC_SET_MUXA0__VARA_2__SHIFT@GOTPAGEOFF]
Lloh62:
	ldr	w9, [x9]
	lsl	w9, w21, w9
	orr	w8, w9, w8
Lloh63:
	adrp	x9, _UVD_MPC_SET_MUXA0__VARA_3__SHIFT@GOTPAGE
Lloh64:
	ldr	x9, [x9, _UVD_MPC_SET_MUXA0__VARA_3__SHIFT@GOTPAGEOFF]
Lloh65:
	ldr	w9, [x9]
	mov	w26, #3
	lsl	w9, w26, w9
	orr	w8, w8, w9
Lloh66:
	adrp	x9, _UVD_MPC_SET_MUXA0__VARA_4__SHIFT@GOTPAGE
Lloh67:
	ldr	x9, [x9, _UVD_MPC_SET_MUXA0__VARA_4__SHIFT@GOTPAGEOFF]
Lloh68:
	ldr	w9, [x9]
	mov	w27, #4
	lsl	w9, w27, w9
	orr	w1, w8, w9
	mov	w2, #0
	mov	x3, x20
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh69:
	adrp	x8, _mmUVD_MPC_SET_MUXB0@GOTPAGE
Lloh70:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXB0@GOTPAGEOFF]
Lloh71:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
Lloh72:
	adrp	x8, _UVD_MPC_SET_MUXB0__VARB_1__SHIFT@GOTPAGE
Lloh73:
	ldr	x8, [x8, _UVD_MPC_SET_MUXB0__VARB_1__SHIFT@GOTPAGEOFF]
Lloh74:
	ldr	w8, [x8]
	lsl	w8, w25, w8
Lloh75:
	adrp	x9, _UVD_MPC_SET_MUXB0__VARB_2__SHIFT@GOTPAGE
Lloh76:
	ldr	x9, [x9, _UVD_MPC_SET_MUXB0__VARB_2__SHIFT@GOTPAGEOFF]
Lloh77:
	ldr	w9, [x9]
	lsl	w9, w21, w9
	orr	w8, w9, w8
Lloh78:
	adrp	x9, _UVD_MPC_SET_MUXB0__VARB_3__SHIFT@GOTPAGE
Lloh79:
	ldr	x9, [x9, _UVD_MPC_SET_MUXB0__VARB_3__SHIFT@GOTPAGEOFF]
Lloh80:
	ldr	w9, [x9]
	lsl	w9, w26, w9
	orr	w8, w8, w9
Lloh81:
	adrp	x9, _UVD_MPC_SET_MUXB0__VARB_4__SHIFT@GOTPAGE
Lloh82:
	ldr	x9, [x9, _UVD_MPC_SET_MUXB0__VARB_4__SHIFT@GOTPAGEOFF]
Lloh83:
	ldr	w9, [x9]
	lsl	w9, w27, w9
	orr	w1, w8, w9
	mov	w2, #0
	mov	x3, x20
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh84:
	adrp	x8, _mmUVD_MPC_SET_MUX@GOTPAGE
Lloh85:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUX@GOTPAGEOFF]
Lloh86:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
Lloh87:
	adrp	x8, _UVD_MPC_SET_MUX__SET_1__SHIFT@GOTPAGE
Lloh88:
	ldr	x8, [x8, _UVD_MPC_SET_MUX__SET_1__SHIFT@GOTPAGEOFF]
Lloh89:
	ldr	w8, [x8]
	lsl	w8, w25, w8
Lloh90:
	adrp	x9, _UVD_MPC_SET_MUX__SET_2__SHIFT@GOTPAGE
Lloh91:
	ldr	x9, [x9, _UVD_MPC_SET_MUX__SET_2__SHIFT@GOTPAGEOFF]
Lloh92:
	ldr	w9, [x9]
	lsl	w9, w21, w9
	orr	w1, w9, w8
	mov	w2, #0
	mov	x3, x20
	bl	_WREG32_SOC15_DPG_MODE_2_0
	mov	x0, x19
	mov	x1, x20
	bl	_vcn_v2_0_mc_resume_dpg_mode
	ldr	w0, [x23]
Lloh93:
	adrp	x8, _mmUVD_REG_XX_MASK@GOTPAGE
Lloh94:
	ldr	x8, [x8, _mmUVD_REG_XX_MASK@GOTPAGEOFF]
Lloh95:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	w1, #16
	mov	w2, #0
	mov	x3, x20
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh96:
	adrp	x8, _mmUVD_RBC_XX_IB_REG_CHECK@GOTPAGE
Lloh97:
	ldr	x8, [x8, _mmUVD_RBC_XX_IB_REG_CHECK@GOTPAGEOFF]
Lloh98:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	w1, #3
	mov	w2, #0
	mov	x3, x20
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh99:
	adrp	x8, _mmUVD_SOFT_RESET@GOTPAGE
Lloh100:
	ldr	x8, [x8, _mmUVD_SOFT_RESET@GOTPAGEOFF]
Lloh101:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	w1, #0
	mov	w2, #0
	mov	x3, x20
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh102:
	adrp	x8, _mmUVD_LMI_CTRL2@GOTPAGE
Lloh103:
	ldr	x8, [x8, _mmUVD_LMI_CTRL2@GOTPAGEOFF]
Lloh104:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
Lloh105:
	adrp	x8, _UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT@GOTPAGE
Lloh106:
	ldr	x8, [x8, _UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT@GOTPAGEOFF]
Lloh107:
	ldr	w8, [x8]
	mov	w9, #31
	lsl	w1, w9, w8
	mov	w2, #0
	mov	x3, x20
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
	ldr	w2, [x24]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
Lloh108:
	adrp	x8, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGE
Lloh109:
	ldr	x8, [x8, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGEOFF]
Lloh110:
	ldr	w1, [x8]
	mov	w2, #0
	mov	x3, x20
	bl	_WREG32_SOC15_DPG_MODE_2_0
	cbz	w20, LBB0_4
; %bb.3:
	ldr	w2, [x19, #16]
	ldr	w8, [x19]
	ldr	w9, [x19, #8]
	sub	w3, w8, w9
	mov	x0, x19
	mov	w1, #0
	bl	_psp_update_vcn_sram
LBB0_4:
	ldr	w0, [x22, #16]
	bl	_order_base_2
	mov	x3, x0
Lloh111:
	adrp	x19, _UVD_RBC_RB_CNTL@GOTPAGE
Lloh112:
	ldr	x19, [x19, _UVD_RBC_RB_CNTL@GOTPAGEOFF]
	ldr	w1, [x19]
Lloh113:
	adrp	x8, _RB_BUFSZ@GOTPAGE
Lloh114:
	ldr	x8, [x8, _RB_BUFSZ@GOTPAGEOFF]
Lloh115:
	ldr	w2, [x8]
	mov	w0, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh116:
	adrp	x8, _RB_BLKSZ@GOTPAGE
Lloh117:
	ldr	x8, [x8, _RB_BLKSZ@GOTPAGEOFF]
Lloh118:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh119:
	adrp	x8, _RB_NO_FETCH@GOTPAGE
Lloh120:
	ldr	x8, [x8, _RB_NO_FETCH@GOTPAGEOFF]
Lloh121:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh122:
	adrp	x8, _RB_NO_UPDATE@GOTPAGE
Lloh123:
	ldr	x8, [x8, _RB_NO_UPDATE@GOTPAGEOFF]
Lloh124:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh125:
	adrp	x8, _RB_RPTR_WR_EN@GOTPAGE
Lloh126:
	ldr	x8, [x8, _RB_RPTR_WR_EN@GOTPAGEOFF]
Lloh127:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x23]
Lloh128:
	adrp	x8, _mmUVD_RBC_RB_CNTL@GOTPAGE
Lloh129:
	ldr	x8, [x8, _mmUVD_RBC_RB_CNTL@GOTPAGEOFF]
Lloh130:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x23]
Lloh131:
	adrp	x8, _mmUVD_RBC_RB_WPTR_CNTL@GOTPAGE
Lloh132:
	ldr	x8, [x8, _mmUVD_RBC_RB_WPTR_CNTL@GOTPAGEOFF]
Lloh133:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w19, [x23]
Lloh134:
	adrp	x8, _mmUVD_RBC_RB_RPTR_ADDR@GOTPAGE
Lloh135:
	ldr	x8, [x8, _mmUVD_RBC_RB_RPTR_ADDR@GOTPAGEOFF]
Lloh136:
	ldr	w20, [x8]
	ldr	x0, [x22, #8]
	bl	_upper_32_bits
	asr	w3, w0, #2
	mov	x0, x19
	mov	w1, #0
	mov	x2, x20
	bl	_WREG32_SOC15
	ldr	w19, [x23]
Lloh137:
	adrp	x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPAGE
Lloh138:
	ldr	x8, [x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh139:
	ldr	w20, [x8]
	ldr	x0, [x22, #8]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x19
	mov	w1, #0
	mov	x2, x20
	bl	_WREG32_SOC15
	ldr	w19, [x23]
Lloh140:
	adrp	x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPAGE
Lloh141:
	ldr	x8, [x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh142:
	ldr	w20, [x8]
	ldr	x0, [x22, #8]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x19
	mov	w1, #0
	mov	x2, x20
	bl	_WREG32_SOC15
	ldr	w0, [x23]
Lloh143:
	adrp	x19, _mmUVD_RBC_RB_RPTR@GOTPAGE
Lloh144:
	ldr	x19, [x19, _mmUVD_RBC_RB_RPTR@GOTPAGEOFF]
	ldr	w2, [x19]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x23]
Lloh145:
	adrp	x8, _mmUVD_SCRATCH2@GOTPAGE
Lloh146:
	ldr	x8, [x8, _mmUVD_SCRATCH2@GOTPAGEOFF]
Lloh147:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x23]
	ldr	w2, [x19]
	mov	w1, #0
	bl	_RREG32_SOC15
	str	x0, [x22]
	ldr	w19, [x23]
Lloh148:
	adrp	x8, _mmUVD_RBC_RB_WPTR@GOTPAGE
Lloh149:
	ldr	x8, [x8, _mmUVD_RBC_RB_WPTR@GOTPAGEOFF]
Lloh150:
	ldr	w20, [x8]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x19
	mov	w1, #0
	mov	x2, x20
	bl	_WREG32_SOC15
	mov	w0, #0
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh40
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh34
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh28
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh148, Lloh149, Lloh150
	.loh AdrpLdrGotLdr	Lloh145, Lloh146, Lloh147
	.loh AdrpLdrGot	Lloh143, Lloh144
	.loh AdrpLdrGotLdr	Lloh140, Lloh141, Lloh142
	.loh AdrpLdrGotLdr	Lloh137, Lloh138, Lloh139
	.loh AdrpLdrGotLdr	Lloh134, Lloh135, Lloh136
	.loh AdrpLdrGotLdr	Lloh131, Lloh132, Lloh133
	.loh AdrpLdrGotLdr	Lloh128, Lloh129, Lloh130
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGot	Lloh111, Lloh112
	.cfi_endproc
                                        ; -- End function
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_POWER_STATUS,4,2         ; @mmUVD_POWER_STATUS
	.comm	_UVD_POWER_STATUS__UVD_PG_MODE_MASK,4,2 ; @UVD_POWER_STATUS__UVD_PG_MODE_MASK
	.comm	_UVD_POWER_STATUS__UVD_PG_EN_MASK,4,2 ; @UVD_POWER_STATUS__UVD_PG_EN_MASK
	.comm	_UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT,4,2 ; @UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT
	.comm	_UVD_VCPU_CNTL__CLK_EN_MASK,4,2 ; @UVD_VCPU_CNTL__CLK_EN_MASK
	.comm	_UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK,4,2 ; @UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK
	.comm	_mmUVD_VCPU_CNTL,4,2            ; @mmUVD_VCPU_CNTL
	.comm	_mmUVD_MASTINT_EN,4,2           ; @mmUVD_MASTINT_EN
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK,4,2 ; @UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK
	.comm	_UVD_LMI_CTRL__REQ_MODE_MASK,4,2 ; @UVD_LMI_CTRL__REQ_MODE_MASK
	.comm	_UVD_LMI_CTRL__CRC_RESET_MASK,4,2 ; @UVD_LMI_CTRL__CRC_RESET_MASK
	.comm	_UVD_LMI_CTRL__MASK_MC_URGENT_MASK,4,2 ; @UVD_LMI_CTRL__MASK_MC_URGENT_MASK
	.comm	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK,4,2 ; @UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK,4,2 ; @UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT,4,2 ; @UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT
	.comm	_mmUVD_LMI_CTRL,4,2             ; @mmUVD_LMI_CTRL
	.comm	_mmUVD_MPC_CNTL,4,2             ; @mmUVD_MPC_CNTL
	.comm	_UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT,4,2 ; @UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT
	.comm	_mmUVD_MPC_SET_MUXA0,4,2        ; @mmUVD_MPC_SET_MUXA0
	.comm	_UVD_MPC_SET_MUXA0__VARA_1__SHIFT,4,2 ; @UVD_MPC_SET_MUXA0__VARA_1__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_2__SHIFT,4,2 ; @UVD_MPC_SET_MUXA0__VARA_2__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_3__SHIFT,4,2 ; @UVD_MPC_SET_MUXA0__VARA_3__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_4__SHIFT,4,2 ; @UVD_MPC_SET_MUXA0__VARA_4__SHIFT
	.comm	_mmUVD_MPC_SET_MUXB0,4,2        ; @mmUVD_MPC_SET_MUXB0
	.comm	_UVD_MPC_SET_MUXB0__VARB_1__SHIFT,4,2 ; @UVD_MPC_SET_MUXB0__VARB_1__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_2__SHIFT,4,2 ; @UVD_MPC_SET_MUXB0__VARB_2__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_3__SHIFT,4,2 ; @UVD_MPC_SET_MUXB0__VARB_3__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_4__SHIFT,4,2 ; @UVD_MPC_SET_MUXB0__VARB_4__SHIFT
	.comm	_mmUVD_MPC_SET_MUX,4,2          ; @mmUVD_MPC_SET_MUX
	.comm	_UVD_MPC_SET_MUX__SET_0__SHIFT,4,2 ; @UVD_MPC_SET_MUX__SET_0__SHIFT
	.comm	_UVD_MPC_SET_MUX__SET_1__SHIFT,4,2 ; @UVD_MPC_SET_MUX__SET_1__SHIFT
	.comm	_UVD_MPC_SET_MUX__SET_2__SHIFT,4,2 ; @UVD_MPC_SET_MUX__SET_2__SHIFT
	.comm	_mmUVD_REG_XX_MASK,4,2          ; @mmUVD_REG_XX_MASK
	.comm	_mmUVD_RBC_XX_IB_REG_CHECK,4,2  ; @mmUVD_RBC_XX_IB_REG_CHECK
	.comm	_mmUVD_SOFT_RESET,4,2           ; @mmUVD_SOFT_RESET
	.comm	_mmUVD_LMI_CTRL2,4,2            ; @mmUVD_LMI_CTRL2
	.comm	_UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,4,2 ; @UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT
	.comm	_UVD_MASTINT_EN__VCPU_EN_MASK,4,2 ; @UVD_MASTINT_EN__VCPU_EN_MASK
	.comm	_UVD_RBC_RB_CNTL,4,2            ; @UVD_RBC_RB_CNTL
	.comm	_RB_BUFSZ,4,2                   ; @RB_BUFSZ
	.comm	_RB_BLKSZ,4,2                   ; @RB_BLKSZ
	.comm	_RB_NO_FETCH,4,2                ; @RB_NO_FETCH
	.comm	_RB_NO_UPDATE,4,2               ; @RB_NO_UPDATE
	.comm	_RB_RPTR_WR_EN,4,2              ; @RB_RPTR_WR_EN
	.comm	_mmUVD_RBC_RB_CNTL,4,2          ; @mmUVD_RBC_RB_CNTL
	.comm	_mmUVD_RBC_RB_WPTR_CNTL,4,2     ; @mmUVD_RBC_RB_WPTR_CNTL
	.comm	_mmUVD_RBC_RB_RPTR_ADDR,4,2     ; @mmUVD_RBC_RB_RPTR_ADDR
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
	.comm	_mmUVD_RBC_RB_RPTR,4,2          ; @mmUVD_RBC_RB_RPTR
	.comm	_mmUVD_SCRATCH2,4,2             ; @mmUVD_SCRATCH2
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ; @mmUVD_RBC_RB_WPTR
	.no_dead_strip	_vcn_v2_0_start_dpg_mode
.subsections_via_symbols
