	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_rn_clk_mgr_construct           ## -- Begin function rn_clk_mgr_construct
	.p2align	4, 0x90
_rn_clk_mgr_construct:                  ## @rn_clk_mgr_construct
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r14
	movq	%rsi, %rbx
	movq	%rdi, %r15
	movq	8(%rdi), %r13
	movl	$0, -56(%rbp)
	movq	$0, -64(%rbp)
	movq	%rdi, 40(%rsi)
	movq	_dcn21_funcs@GOTPCREL(%rip), %r12
	movq	%r12, 32(%rsi)
	movq	%rdx, 80(%rsi)
	movq	%rcx, 72(%rsi)
	xorps	%xmm0, %xmm0
	movups	%xmm0, 56(%rsi)
	movq	$1000, (%rsi)                   ## imm = 0x3E8
	movl	$48000, 8(%rsi)                 ## imm = 0xBB80
	movq	%rsi, %rdi
	callq	_rn_vbios_smu_get_smu_version
	movl	%eax, 48(%rbx)
	movl	4(%r15), %edi
	callq	_IS_FPGA_MAXIMUS_DC
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	_dcn2_update_clocks_fpga@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, (%r12)
	movabsq	$2576980381200000, %rax         ## imm = 0x927C00036EE80
	movq	%rax, 12(%rbx)
	jmp	LBB0_5
LBB0_2:
	leaq	16(%rbx), %r12
	movl	$0, -48(%rbp)
	movq	%rbx, %rdi
	callq	_get_vco_frequency_from_reg
	testl	%eax, %eax
	movl	$3600000, %ecx                  ## imm = 0x36EE80
	cmovnel	%eax, %ecx
	movl	%ecx, 12(%rbx)
	leaq	-64(%rbp), %rdi
	leaq	-48(%rbp), %rdx
	movq	%r12, %rsi
	callq	_rn_dump_clk_registers
	movl	-64(%rbp), %eax
	movl	%eax, 16(%rbx)
	cmpl	$600000, %eax                   ## imm = 0x927C0
	je	LBB0_5
## %bb.3:
	movl	$600000, (%r12)                 ## imm = 0x927C0
	movl	$1, %edi
	callq	_ASSERT
	cmpl	$0, (%r12)
	jne	LBB0_5
## %bb.4:
	movl	$600000, (%r12)                 ## imm = 0x927C0
LBB0_5:
	movq	%rbx, %rdi
	callq	_dce_clock_read_ss_info
	movq	_rn_bw_params@GOTPCREL(%rip), %rax
	movq	%rax, 24(%rbx)
	testq	%r14, %r14
	je	LBB0_7
## %bb.6:
	leaq	-56(%rbp), %r12
	movq	%r14, %rdi
	movq	%r12, %rsi
	callq	*16(%r14)
	movq	24(%rbx), %rdi
	movq	%r12, %rsi
	movq	%r15, %rdx
	callq	_clk_mgr_helper_populate_bw_params
LBB0_7:
	cmpl	$0, 4(%r13)
	je	LBB0_8
LBB0_11:
	cmpl	$0, (%r13)
	jne	LBB0_13
## %bb.12:
	movq	%rbx, %rdi
	callq	_rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn
LBB0_13:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_8:
	movl	$0, -48(%rbp)
	movq	24(%rbx), %rdi
	leaq	-48(%rbp), %rsi
	callq	_build_watermark_ranges
	testq	%r14, %r14
	je	LBB0_11
## %bb.9:
	movq	8(%r14), %rax
	testq	%rax, %rax
	je	LBB0_11
## %bb.10:
	leaq	-48(%rbp), %rsi
	movq	%r14, %rdi
	callq	*%rax
	jmp	LBB0_11
	.cfi_endproc
                                        ## -- End function
	.comm	_dcn21_funcs,4,2                ## @dcn21_funcs
	.comm	_dcn2_update_clocks_fpga,4,2    ## @dcn2_update_clocks_fpga
	.comm	_rn_bw_params,4,2               ## @rn_bw_params
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3                               ; -- Begin function rn_clk_mgr_construct
lCPI0_0:
	.long	1000                            ; 0x3e8
	.long	0                               ; 0x0
lCPI0_1:
	.long	3600000                         ; 0x36ee80
	.long	600000                          ; 0x927c0
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_rn_clk_mgr_construct
	.p2align	2
_rn_clk_mgr_construct:                  ; @rn_clk_mgr_construct
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x2
	mov	x19, x1
	mov	x21, x0
	ldr	x23, [x0, #8]
	str	wzr, [sp, #24]
Lloh0:
	adrp	x22, _dcn21_funcs@GOTPAGE
Lloh1:
	ldr	x22, [x22, _dcn21_funcs@GOTPAGEOFF]
	str	xzr, [sp, #16]
	stp	x22, x0, [x1, #32]
	stp	x3, x2, [x1, #72]
	stp	xzr, xzr, [x1, #56]
Lloh2:
	adrp	x8, lCPI0_0@PAGE
Lloh3:
	ldr	d0, [x8, lCPI0_0@PAGEOFF]
	str	d0, [x1]
	mov	w8, #48000
	str	w8, [x1, #8]
	mov	x0, x1
	bl	_rn_vbios_smu_get_smu_version
	str	w0, [x19, #48]
	ldr	w0, [x21, #4]
	bl	_IS_FPGA_MAXIMUS_DC
	cbz	x0, LBB0_2
; %bb.1:
Lloh4:
	adrp	x8, _dcn2_update_clocks_fpga@GOTPAGE
Lloh5:
	ldr	x8, [x8, _dcn2_update_clocks_fpga@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
	str	w8, [x22]
Lloh7:
	adrp	x8, lCPI0_1@PAGE
Lloh8:
	ldr	d0, [x8, lCPI0_1@PAGEOFF]
	stur	d0, [x19, #12]
	b	LBB0_5
LBB0_2:
	mov	w24, #10176
	movk	w24, #9, lsl #16
	add	x22, x19, #16
	str	wzr, [sp, #8]
	mov	x0, x19
	bl	_get_vco_frequency_from_reg
	mov	w8, #61056
	movk	w8, #54, lsl #16
	cmp	w0, #0
	csel	w8, w8, w0, eq
	str	w8, [x19, #12]
	add	x0, sp, #16
	add	x2, sp, #8
	mov	x1, x22
	bl	_rn_dump_clk_registers
	ldr	w8, [sp, #16]
	str	w8, [x19, #16]
	cmp	w8, w24
	b.eq	LBB0_5
; %bb.3:
	str	w24, [x22]
	mov	w0, #1
	bl	_ASSERT
	ldr	w8, [x22]
	cbnz	w8, LBB0_5
; %bb.4:
	str	w24, [x22]
LBB0_5:
	mov	x0, x19
	bl	_dce_clock_read_ss_info
Lloh9:
	adrp	x8, _rn_bw_params@GOTPAGE
Lloh10:
	ldr	x8, [x8, _rn_bw_params@GOTPAGEOFF]
	str	x8, [x19, #24]
	cbz	x20, LBB0_7
; %bb.6:
	ldr	x8, [x20, #16]
	add	x1, sp, #24
	mov	x0, x20
	blr	x8
	ldr	x0, [x19, #24]
	add	x1, sp, #24
	mov	x2, x21
	bl	_clk_mgr_helper_populate_bw_params
LBB0_7:
	ldr	w8, [x23, #4]
	cbz	w8, LBB0_11
LBB0_8:
	ldr	w8, [x23]
	cbnz	w8, LBB0_10
; %bb.9:
	mov	x0, x19
	bl	_rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn
LBB0_10:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_11:
	str	wzr, [sp, #8]
	ldr	x0, [x19, #24]
	add	x1, sp, #8
	bl	_build_watermark_ranges
	cbz	x20, LBB0_8
; %bb.12:
	ldr	x8, [x20, #8]
	cbz	x8, LBB0_8
; %bb.13:
	add	x1, sp, #8
	mov	x0, x20
	blr	x8
	b	LBB0_8
	.loh AdrpLdr	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdr	Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh9, Lloh10
	.cfi_endproc
                                        ; -- End function
	.comm	_dcn21_funcs,4,2                ; @dcn21_funcs
	.comm	_dcn2_update_clocks_fpga,4,2    ; @dcn2_update_clocks_fpga
	.comm	_rn_bw_params,4,2               ; @rn_bw_params
.subsections_via_symbols
