	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gmc_v7_0_gart_enable
_gmc_v7_0_gart_enable:                  ## @gmc_v7_0_gart_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	cmpq	$0, 24(%rdi)
	je	LBB0_1
## %bb.2:
	movq	%r12, %rdi
	callq	_amdgpu_gart_table_vram_pin
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	LBB0_6
## %bb.3:
	movq	24(%r12), %rdi
	callq	_amdgpu_bo_gpu_offset
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	_mmMC_VM_MX_L1_TLB_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32
	movq	_MC_VM_MX_L1_TLB_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_ENABLE_L1_TLB@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_ENABLE_L1_FRAGMENT_PROCESSING@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_SYSTEM_ACCESS_MODE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$3, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_ENABLE_ADVANCED_DRIVER_MODEL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_SYSTEM_APERTURE_UNMAPPED_ACCESS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%r15d, %r15d
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%r14), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmVM_L2_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32
	movq	_VM_L2_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_ENABLE_L2_CACHE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_ENABLE_L2_FRAGMENT_PROCESSING@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_EFFECTIVE_L2_QUEUE_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$7, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_CONTEXT1_IDENTITY_ACCESS_MODE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r14), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_VM_L2_CNTL2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_INVALIDATE_ALL_L1_TLBS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%edi, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_INVALIDATE_L2_CACHE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movq	_mmVM_L2_CNTL2@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movl	44(%r12), %ebx
	movq	_mmVM_L2_CNTL3@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32
	movq	_VM_L2_CNTL3@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	_L2_CACHE_BIGK_ASSOCIATIVITY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r13), %esi
	movq	_BANK_SELECT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	%ebx, %ecx
	callq	_REG_SET_FIELD
	movl	(%r13), %esi
	movq	_L2_CACHE_BIGK_FRAGMENT_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	%ebx, %ecx
	callq	_REG_SET_FIELD
	movl	(%r14), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	32(%r12), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	36(%r12), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movl	-44(%rbp), %ebx                 ## 4-byte Reload
	sarl	$12, %ebx
	movl	%ebx, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r12), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT0_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT0_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_VM_CONTEXT0_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	_ENABLE_CONTEXT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r14), %esi
	movq	_PAGE_TABLE_DEPTH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%r14), %esi
	movq	_RANGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movq	_mmVM_CONTEXT0_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movl	$1397, %edi                     ## imm = 0x575
	xorl	%esi, %esi
	callq	_WREG32
	movl	$1398, %edi                     ## imm = 0x576
	xorl	%esi, %esi
	callq	_WREG32
	movl	$1399, %edi                     ## imm = 0x577
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT1_PAGE_TABLE_START_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT1_PAGE_TABLE_END_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	48(%r12), %esi
	decl	%esi
	callq	_WREG32
	movl	(%r13), %edi
	incl	%edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$2, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$3, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$4, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$5, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$6, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$7, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r13), %edi
	incl	%edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$2, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$3, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$4, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$5, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$6, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$7, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r12), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT1_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$4, %esi
	callq	_WREG32
	movq	_mmVM_CONTEXT1_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32
	movq	_VM_CONTEXT1_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_ENABLE_CONTEXT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_PAGE_TABLE_DEPTH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_PAGE_TABLE_BLOCK_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	52(%r12), %ecx
	addl	$-9, %ecx
	movl	%eax, %edi
	callq	_REG_SET_FIELD
	movl	(%r14), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_amdgpu_vm_fault_stop@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_AMDGPU_VM_FAULT_STOP_ALWAYS@GOTPCREL(%rip), %rcx
	xorl	%esi, %esi
	cmpq	(%rcx), %rax
	setne	%sil
	movq	%r12, %rdi
	callq	_gmc_v7_0_set_fault_enable_default
	movq	8(%r12), %rax
	movq	_CHIP_KAVERI@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_5
## %bb.4:
	movq	_mmCHUB_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_BYPASS_VM@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32
LBB0_5:
	movq	%r12, %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	callq	_gmc_v7_0_flush_gpu_tlb
	movl	40(%r12), %esi
	sarl	$20, %esi
	movslq	-44(%rbp), %rdx                 ## 4-byte Folded Reload
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_INFO
	movl	$1, 16(%r12)
	jmp	LBB0_6
LBB0_1:
	movl	56(%r12), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r15d, %r15d
	subl	(%rax), %r15d
LBB0_6:
	movl	%r15d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"No VRAM object for PCIE GART.\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_mmMC_VM_MX_L1_TLB_CNTL,4,2     ## @mmMC_VM_MX_L1_TLB_CNTL
	.comm	_MC_VM_MX_L1_TLB_CNTL,4,2       ## @MC_VM_MX_L1_TLB_CNTL
	.comm	_ENABLE_L1_TLB,4,2              ## @ENABLE_L1_TLB
	.comm	_ENABLE_L1_FRAGMENT_PROCESSING,4,2 ## @ENABLE_L1_FRAGMENT_PROCESSING
	.comm	_SYSTEM_ACCESS_MODE,4,2         ## @SYSTEM_ACCESS_MODE
	.comm	_ENABLE_ADVANCED_DRIVER_MODEL,4,2 ## @ENABLE_ADVANCED_DRIVER_MODEL
	.comm	_SYSTEM_APERTURE_UNMAPPED_ACCESS,4,2 ## @SYSTEM_APERTURE_UNMAPPED_ACCESS
	.comm	_mmVM_L2_CNTL,4,2               ## @mmVM_L2_CNTL
	.comm	_VM_L2_CNTL,4,2                 ## @VM_L2_CNTL
	.comm	_ENABLE_L2_CACHE,4,2            ## @ENABLE_L2_CACHE
	.comm	_ENABLE_L2_FRAGMENT_PROCESSING,4,2 ## @ENABLE_L2_FRAGMENT_PROCESSING
	.comm	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE,4,2 ## @ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE,4,2 ## @ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_EFFECTIVE_L2_QUEUE_SIZE,4,2    ## @EFFECTIVE_L2_QUEUE_SIZE
	.comm	_CONTEXT1_IDENTITY_ACCESS_MODE,4,2 ## @CONTEXT1_IDENTITY_ACCESS_MODE
	.comm	_ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY,4,2 ## @ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY
	.comm	_VM_L2_CNTL2,4,2                ## @VM_L2_CNTL2
	.comm	_INVALIDATE_ALL_L1_TLBS,4,2     ## @INVALIDATE_ALL_L1_TLBS
	.comm	_INVALIDATE_L2_CACHE,4,2        ## @INVALIDATE_L2_CACHE
	.comm	_mmVM_L2_CNTL2,4,2              ## @mmVM_L2_CNTL2
	.comm	_mmVM_L2_CNTL3,4,2              ## @mmVM_L2_CNTL3
	.comm	_VM_L2_CNTL3,4,2                ## @VM_L2_CNTL3
	.comm	_L2_CACHE_BIGK_ASSOCIATIVITY,4,2 ## @L2_CACHE_BIGK_ASSOCIATIVITY
	.comm	_BANK_SELECT,4,2                ## @BANK_SELECT
	.comm	_L2_CACHE_BIGK_FRAGMENT_SIZE,4,2 ## @L2_CACHE_BIGK_FRAGMENT_SIZE
	.comm	_mmVM_CONTEXT0_PAGE_TABLE_START_ADDR,4,2 ## @mmVM_CONTEXT0_PAGE_TABLE_START_ADDR
	.comm	_mmVM_CONTEXT0_PAGE_TABLE_END_ADDR,4,2 ## @mmVM_CONTEXT0_PAGE_TABLE_END_ADDR
	.comm	_mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR,4,2 ## @mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
	.comm	_mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,4,2 ## @mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
	.comm	_mmVM_CONTEXT0_CNTL2,4,2        ## @mmVM_CONTEXT0_CNTL2
	.comm	_mmVM_CONTEXT0_CNTL,4,2         ## @mmVM_CONTEXT0_CNTL
	.comm	_VM_CONTEXT0_CNTL,4,2           ## @VM_CONTEXT0_CNTL
	.comm	_ENABLE_CONTEXT,4,2             ## @ENABLE_CONTEXT
	.comm	_PAGE_TABLE_DEPTH,4,2           ## @PAGE_TABLE_DEPTH
	.comm	_RANGE_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ## @RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_mmVM_CONTEXT1_PAGE_TABLE_START_ADDR,4,2 ## @mmVM_CONTEXT1_PAGE_TABLE_START_ADDR
	.comm	_mmVM_CONTEXT1_PAGE_TABLE_END_ADDR,4,2 ## @mmVM_CONTEXT1_PAGE_TABLE_END_ADDR
	.comm	_mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR,4,2 ## @mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
	.comm	_mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,4,2 ## @mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR
	.comm	_mmVM_CONTEXT1_CNTL2,4,2        ## @mmVM_CONTEXT1_CNTL2
	.comm	_mmVM_CONTEXT1_CNTL,4,2         ## @mmVM_CONTEXT1_CNTL
	.comm	_VM_CONTEXT1_CNTL,4,2           ## @VM_CONTEXT1_CNTL
	.comm	_PAGE_TABLE_BLOCK_SIZE,4,2      ## @PAGE_TABLE_BLOCK_SIZE
	.comm	_amdgpu_vm_fault_stop,8,3       ## @amdgpu_vm_fault_stop
	.comm	_AMDGPU_VM_FAULT_STOP_ALWAYS,8,3 ## @AMDGPU_VM_FAULT_STOP_ALWAYS
	.comm	_CHIP_KAVERI,8,3                ## @CHIP_KAVERI
	.comm	_mmCHUB_CONTROL,4,2             ## @mmCHUB_CONTROL
	.comm	_BYPASS_VM,4,2                  ## @BYPASS_VM
L_.str.1:                               ## @.str.1
	.asciz	"PCIE GART of %uM enabled (table at 0x%016llX).\n"

	.no_dead_strip	_gmc_v7_0_gart_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gmc_v7_0_gart_enable
_gmc_v7_0_gart_enable:                  ; @gmc_v7_0_gart_enable
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	x8, [x0, #24]
	cbz	x8, LBB0_5
; %bb.1:
	mov	x0, x19
	bl	_amdgpu_gart_table_vram_pin
	cbnz	w0, LBB0_6
; %bb.2:
	ldr	x0, [x19, #24]
	bl	_amdgpu_bo_gpu_offset
	mov	x20, x0
Lloh0:
	adrp	x21, _mmMC_VM_MX_L1_TLB_CNTL@GOTPAGE
Lloh1:
	ldr	x21, [x21, _mmMC_VM_MX_L1_TLB_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
Lloh2:
	adrp	x23, _MC_VM_MX_L1_TLB_CNTL@GOTPAGE
Lloh3:
	ldr	x23, [x23, _MC_VM_MX_L1_TLB_CNTL@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh4:
	adrp	x8, _ENABLE_L1_TLB@GOTPAGE
Lloh5:
	ldr	x8, [x8, _ENABLE_L1_TLB@GOTPAGEOFF]
Lloh6:
	ldr	w2, [x8]
	mov	w22, #1
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh7:
	adrp	x8, _ENABLE_L1_FRAGMENT_PROCESSING@GOTPAGE
Lloh8:
	ldr	x8, [x8, _ENABLE_L1_FRAGMENT_PROCESSING@GOTPAGEOFF]
Lloh9:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh10:
	adrp	x8, _SYSTEM_ACCESS_MODE@GOTPAGE
Lloh11:
	ldr	x8, [x8, _SYSTEM_ACCESS_MODE@GOTPAGEOFF]
Lloh12:
	ldr	w2, [x8]
	mov	w3, #3
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh13:
	adrp	x8, _ENABLE_ADVANCED_DRIVER_MODEL@GOTPAGE
Lloh14:
	ldr	x8, [x8, _ENABLE_ADVANCED_DRIVER_MODEL@GOTPAGEOFF]
Lloh15:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh16:
	adrp	x8, _SYSTEM_APERTURE_UNMAPPED_ACCESS@GOTPAGE
Lloh17:
	ldr	x8, [x8, _SYSTEM_APERTURE_UNMAPPED_ACCESS@GOTPAGEOFF]
Lloh18:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	mov	x1, x0
	ldr	w0, [x21]
	bl	_WREG32
Lloh19:
	adrp	x21, _mmVM_L2_CNTL@GOTPAGE
Lloh20:
	ldr	x21, [x21, _mmVM_L2_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
Lloh21:
	adrp	x23, _VM_L2_CNTL@GOTPAGE
Lloh22:
	ldr	x23, [x23, _VM_L2_CNTL@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh23:
	adrp	x8, _ENABLE_L2_CACHE@GOTPAGE
Lloh24:
	ldr	x8, [x8, _ENABLE_L2_CACHE@GOTPAGEOFF]
Lloh25:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh26:
	adrp	x8, _ENABLE_L2_FRAGMENT_PROCESSING@GOTPAGE
Lloh27:
	ldr	x8, [x8, _ENABLE_L2_FRAGMENT_PROCESSING@GOTPAGEOFF]
Lloh28:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh29:
	adrp	x8, _ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGE
Lloh30:
	ldr	x8, [x8, _ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGEOFF]
Lloh31:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh32:
	adrp	x8, _ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGE
Lloh33:
	ldr	x8, [x8, _ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGEOFF]
Lloh34:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh35:
	adrp	x8, _EFFECTIVE_L2_QUEUE_SIZE@GOTPAGE
Lloh36:
	ldr	x8, [x8, _EFFECTIVE_L2_QUEUE_SIZE@GOTPAGEOFF]
Lloh37:
	ldr	w2, [x8]
	mov	w3, #7
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh38:
	adrp	x8, _CONTEXT1_IDENTITY_ACCESS_MODE@GOTPAGE
Lloh39:
	ldr	x8, [x8, _CONTEXT1_IDENTITY_ACCESS_MODE@GOTPAGEOFF]
Lloh40:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh41:
	adrp	x8, _ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY@GOTPAGE
Lloh42:
	ldr	x8, [x8, _ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY@GOTPAGEOFF]
Lloh43:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x1, x0
	ldr	w0, [x21]
	bl	_WREG32
Lloh44:
	adrp	x21, _VM_L2_CNTL2@GOTPAGE
Lloh45:
	ldr	x21, [x21, _VM_L2_CNTL2@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh46:
	adrp	x8, _INVALIDATE_ALL_L1_TLBS@GOTPAGE
Lloh47:
	ldr	x8, [x8, _INVALIDATE_ALL_L1_TLBS@GOTPAGEOFF]
Lloh48:
	ldr	w2, [x8]
	mov	w0, #0
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x21]
Lloh49:
	adrp	x8, _INVALIDATE_L2_CACHE@GOTPAGE
Lloh50:
	ldr	x8, [x8, _INVALIDATE_L2_CACHE@GOTPAGEOFF]
Lloh51:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x1, x0
Lloh52:
	adrp	x8, _mmVM_L2_CNTL2@GOTPAGE
Lloh53:
	ldr	x8, [x8, _mmVM_L2_CNTL2@GOTPAGEOFF]
Lloh54:
	ldr	w0, [x8]
	bl	_WREG32
	ldr	w21, [x19, #44]
Lloh55:
	adrp	x23, _mmVM_L2_CNTL3@GOTPAGE
Lloh56:
	ldr	x23, [x23, _mmVM_L2_CNTL3@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32
Lloh57:
	adrp	x24, _VM_L2_CNTL3@GOTPAGE
Lloh58:
	ldr	x24, [x24, _VM_L2_CNTL3@GOTPAGEOFF]
	ldr	w1, [x24]
Lloh59:
	adrp	x8, _L2_CACHE_BIGK_ASSOCIATIVITY@GOTPAGE
Lloh60:
	ldr	x8, [x8, _L2_CACHE_BIGK_ASSOCIATIVITY@GOTPAGEOFF]
Lloh61:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x24]
Lloh62:
	adrp	x8, _BANK_SELECT@GOTPAGE
Lloh63:
	ldr	x8, [x8, _BANK_SELECT@GOTPAGEOFF]
Lloh64:
	ldr	w2, [x8]
	mov	x3, x21
	bl	_REG_SET_FIELD
	ldr	w1, [x24]
Lloh65:
	adrp	x8, _L2_CACHE_BIGK_FRAGMENT_SIZE@GOTPAGE
Lloh66:
	ldr	x8, [x8, _L2_CACHE_BIGK_FRAGMENT_SIZE@GOTPAGEOFF]
Lloh67:
	ldr	w2, [x8]
	mov	x3, x21
	bl	_REG_SET_FIELD
	mov	x1, x0
	ldr	w0, [x23]
	bl	_WREG32
Lloh68:
	adrp	x8, _mmVM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPAGE
Lloh69:
	ldr	x8, [x8, _mmVM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPAGEOFF]
Lloh70:
	ldr	w0, [x8]
	ldr	w8, [x19, #32]
	asr	w1, w8, #12
	bl	_WREG32
Lloh71:
	adrp	x8, _mmVM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPAGE
Lloh72:
	ldr	x8, [x8, _mmVM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPAGEOFF]
Lloh73:
	ldr	w0, [x8]
	ldr	w8, [x19, #36]
	asr	w1, w8, #12
	bl	_WREG32
Lloh74:
	adrp	x25, _mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPAGE
Lloh75:
	ldr	x25, [x25, _mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPAGEOFF]
	ldr	w0, [x25]
	asr	w21, w20, #12
	mov	x1, x21
	bl	_WREG32
Lloh76:
	adrp	x8, _mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR@GOTPAGE
Lloh77:
	ldr	x8, [x8, _mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR@GOTPAGEOFF]
Lloh78:
	ldr	w0, [x8]
	ldr	w8, [x19]
	asr	w1, w8, #12
	bl	_WREG32
Lloh79:
	adrp	x8, _mmVM_CONTEXT0_CNTL2@GOTPAGE
Lloh80:
	ldr	x8, [x8, _mmVM_CONTEXT0_CNTL2@GOTPAGEOFF]
Lloh81:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh82:
	adrp	x26, _mmVM_CONTEXT0_CNTL@GOTPAGE
Lloh83:
	ldr	x26, [x26, _mmVM_CONTEXT0_CNTL@GOTPAGEOFF]
	ldr	w0, [x26]
	bl	_RREG32
Lloh84:
	adrp	x27, _VM_CONTEXT0_CNTL@GOTPAGE
Lloh85:
	ldr	x27, [x27, _VM_CONTEXT0_CNTL@GOTPAGEOFF]
	ldr	w1, [x27]
Lloh86:
	adrp	x23, _ENABLE_CONTEXT@GOTPAGE
Lloh87:
	ldr	x23, [x23, _ENABLE_CONTEXT@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x27]
Lloh88:
	adrp	x24, _PAGE_TABLE_DEPTH@GOTPAGE
Lloh89:
	ldr	x24, [x24, _PAGE_TABLE_DEPTH@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x27]
Lloh90:
	adrp	x8, _RANGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGE
Lloh91:
	ldr	x8, [x8, _RANGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGEOFF]
Lloh92:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x1, x0
	ldr	w0, [x26]
	bl	_WREG32
	mov	w0, #1397
	mov	w1, #0
	bl	_WREG32
	mov	w0, #1398
	mov	w1, #0
	bl	_WREG32
	mov	w0, #1399
	mov	w1, #0
	bl	_WREG32
Lloh93:
	adrp	x8, _mmVM_CONTEXT1_PAGE_TABLE_START_ADDR@GOTPAGE
Lloh94:
	ldr	x8, [x8, _mmVM_CONTEXT1_PAGE_TABLE_START_ADDR@GOTPAGEOFF]
Lloh95:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh96:
	adrp	x8, _mmVM_CONTEXT1_PAGE_TABLE_END_ADDR@GOTPAGE
Lloh97:
	ldr	x8, [x8, _mmVM_CONTEXT1_PAGE_TABLE_END_ADDR@GOTPAGEOFF]
Lloh98:
	ldr	w0, [x8]
	ldr	w8, [x19, #48]
	sub	w1, w8, #1
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #1
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #2
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #3
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #4
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #5
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #6
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #7
	mov	x1, x21
	bl	_WREG32
Lloh99:
	adrp	x25, _mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR@GOTPAGE
Lloh100:
	ldr	x25, [x25, _mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR@GOTPAGEOFF]
	ldr	w0, [x25]
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #1
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #2
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #3
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #4
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #5
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #6
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #7
	mov	x1, x21
	bl	_WREG32
Lloh101:
	adrp	x8, _mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR@GOTPAGE
Lloh102:
	ldr	x8, [x8, _mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR@GOTPAGEOFF]
Lloh103:
	ldr	w0, [x8]
	ldr	w8, [x19]
	asr	w1, w8, #12
	bl	_WREG32
Lloh104:
	adrp	x8, _mmVM_CONTEXT1_CNTL2@GOTPAGE
Lloh105:
	ldr	x8, [x8, _mmVM_CONTEXT1_CNTL2@GOTPAGEOFF]
Lloh106:
	ldr	w0, [x8]
	mov	w1, #4
	bl	_WREG32
Lloh107:
	adrp	x21, _mmVM_CONTEXT1_CNTL@GOTPAGE
Lloh108:
	ldr	x21, [x21, _mmVM_CONTEXT1_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
Lloh109:
	adrp	x25, _VM_CONTEXT1_CNTL@GOTPAGE
Lloh110:
	ldr	x25, [x25, _VM_CONTEXT1_CNTL@GOTPAGEOFF]
	ldr	w1, [x25]
	ldr	w2, [x23]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x25]
	ldr	w2, [x24]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x25]
Lloh111:
	adrp	x8, _PAGE_TABLE_BLOCK_SIZE@GOTPAGE
Lloh112:
	ldr	x8, [x8, _PAGE_TABLE_BLOCK_SIZE@GOTPAGEOFF]
Lloh113:
	ldr	w2, [x8]
	ldr	w8, [x19, #52]
	sub	w3, w8, #9
	bl	_REG_SET_FIELD
	mov	x1, x0
	ldr	w0, [x21]
	bl	_WREG32
Lloh114:
	adrp	x8, _amdgpu_vm_fault_stop@GOTPAGE
Lloh115:
	ldr	x8, [x8, _amdgpu_vm_fault_stop@GOTPAGEOFF]
Lloh116:
	ldr	x8, [x8]
Lloh117:
	adrp	x9, _AMDGPU_VM_FAULT_STOP_ALWAYS@GOTPAGE
Lloh118:
	ldr	x9, [x9, _AMDGPU_VM_FAULT_STOP_ALWAYS@GOTPAGEOFF]
Lloh119:
	ldr	x9, [x9]
	cmp	x8, x9
	cset	w1, ne
	mov	x0, x19
	bl	_gmc_v7_0_set_fault_enable_default
	ldr	x8, [x19, #8]
Lloh120:
	adrp	x9, _CHIP_KAVERI@GOTPAGE
Lloh121:
	ldr	x9, [x9, _CHIP_KAVERI@GOTPAGEOFF]
Lloh122:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_4
; %bb.3:
Lloh123:
	adrp	x21, _mmCHUB_CONTROL@GOTPAGE
Lloh124:
	ldr	x21, [x21, _mmCHUB_CONTROL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
Lloh125:
	adrp	x8, _BYPASS_VM@GOTPAGE
Lloh126:
	ldr	x8, [x8, _BYPASS_VM@GOTPAGEOFF]
Lloh127:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w0, [x21]
	bl	_WREG32
LBB0_4:
	mov	x0, x19
	mov	w1, #0
	mov	w2, #0
	mov	w3, #0
	bl	_gmc_v7_0_flush_gpu_tlb
	ldr	w8, [x19, #40]
	asr	w1, w8, #20
	sxtw	x2, w20
Lloh128:
	adrp	x0, l_.str.1@PAGE
Lloh129:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_INFO
	mov	w0, #0
	str	w22, [x19, #16]
	b	LBB0_6
LBB0_5:
	ldr	w0, [x19, #56]
Lloh130:
	adrp	x1, l_.str@PAGE
Lloh131:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
Lloh132:
	adrp	x8, _EINVAL@GOTPAGE
Lloh133:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh134:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_6:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh120, Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGot	Lloh109, Lloh110
	.loh AdrpLdrGot	Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGot	Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGot	Lloh88, Lloh89
	.loh AdrpLdrGot	Lloh86, Lloh87
	.loh AdrpLdrGot	Lloh84, Lloh85
	.loh AdrpLdrGot	Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGot	Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGot	Lloh123, Lloh124
	.loh AdrpAdd	Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh132, Lloh133, Lloh134
	.loh AdrpAdd	Lloh130, Lloh131
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"No VRAM object for PCIE GART.\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_mmMC_VM_MX_L1_TLB_CNTL,4,2     ; @mmMC_VM_MX_L1_TLB_CNTL
	.comm	_MC_VM_MX_L1_TLB_CNTL,4,2       ; @MC_VM_MX_L1_TLB_CNTL
	.comm	_ENABLE_L1_TLB,4,2              ; @ENABLE_L1_TLB
	.comm	_ENABLE_L1_FRAGMENT_PROCESSING,4,2 ; @ENABLE_L1_FRAGMENT_PROCESSING
	.comm	_SYSTEM_ACCESS_MODE,4,2         ; @SYSTEM_ACCESS_MODE
	.comm	_ENABLE_ADVANCED_DRIVER_MODEL,4,2 ; @ENABLE_ADVANCED_DRIVER_MODEL
	.comm	_SYSTEM_APERTURE_UNMAPPED_ACCESS,4,2 ; @SYSTEM_APERTURE_UNMAPPED_ACCESS
	.comm	_mmVM_L2_CNTL,4,2               ; @mmVM_L2_CNTL
	.comm	_VM_L2_CNTL,4,2                 ; @VM_L2_CNTL
	.comm	_ENABLE_L2_CACHE,4,2            ; @ENABLE_L2_CACHE
	.comm	_ENABLE_L2_FRAGMENT_PROCESSING,4,2 ; @ENABLE_L2_FRAGMENT_PROCESSING
	.comm	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE,4,2 ; @ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE,4,2 ; @ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_EFFECTIVE_L2_QUEUE_SIZE,4,2    ; @EFFECTIVE_L2_QUEUE_SIZE
	.comm	_CONTEXT1_IDENTITY_ACCESS_MODE,4,2 ; @CONTEXT1_IDENTITY_ACCESS_MODE
	.comm	_ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY,4,2 ; @ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY
	.comm	_VM_L2_CNTL2,4,2                ; @VM_L2_CNTL2
	.comm	_INVALIDATE_ALL_L1_TLBS,4,2     ; @INVALIDATE_ALL_L1_TLBS
	.comm	_INVALIDATE_L2_CACHE,4,2        ; @INVALIDATE_L2_CACHE
	.comm	_mmVM_L2_CNTL2,4,2              ; @mmVM_L2_CNTL2
	.comm	_mmVM_L2_CNTL3,4,2              ; @mmVM_L2_CNTL3
	.comm	_VM_L2_CNTL3,4,2                ; @VM_L2_CNTL3
	.comm	_L2_CACHE_BIGK_ASSOCIATIVITY,4,2 ; @L2_CACHE_BIGK_ASSOCIATIVITY
	.comm	_BANK_SELECT,4,2                ; @BANK_SELECT
	.comm	_L2_CACHE_BIGK_FRAGMENT_SIZE,4,2 ; @L2_CACHE_BIGK_FRAGMENT_SIZE
	.comm	_mmVM_CONTEXT0_PAGE_TABLE_START_ADDR,4,2 ; @mmVM_CONTEXT0_PAGE_TABLE_START_ADDR
	.comm	_mmVM_CONTEXT0_PAGE_TABLE_END_ADDR,4,2 ; @mmVM_CONTEXT0_PAGE_TABLE_END_ADDR
	.comm	_mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR,4,2 ; @mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
	.comm	_mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,4,2 ; @mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
	.comm	_mmVM_CONTEXT0_CNTL2,4,2        ; @mmVM_CONTEXT0_CNTL2
	.comm	_mmVM_CONTEXT0_CNTL,4,2         ; @mmVM_CONTEXT0_CNTL
	.comm	_VM_CONTEXT0_CNTL,4,2           ; @VM_CONTEXT0_CNTL
	.comm	_ENABLE_CONTEXT,4,2             ; @ENABLE_CONTEXT
	.comm	_PAGE_TABLE_DEPTH,4,2           ; @PAGE_TABLE_DEPTH
	.comm	_RANGE_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ; @RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_mmVM_CONTEXT1_PAGE_TABLE_START_ADDR,4,2 ; @mmVM_CONTEXT1_PAGE_TABLE_START_ADDR
	.comm	_mmVM_CONTEXT1_PAGE_TABLE_END_ADDR,4,2 ; @mmVM_CONTEXT1_PAGE_TABLE_END_ADDR
	.comm	_mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR,4,2 ; @mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
	.comm	_mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,4,2 ; @mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR
	.comm	_mmVM_CONTEXT1_CNTL2,4,2        ; @mmVM_CONTEXT1_CNTL2
	.comm	_mmVM_CONTEXT1_CNTL,4,2         ; @mmVM_CONTEXT1_CNTL
	.comm	_VM_CONTEXT1_CNTL,4,2           ; @VM_CONTEXT1_CNTL
	.comm	_PAGE_TABLE_BLOCK_SIZE,4,2      ; @PAGE_TABLE_BLOCK_SIZE
	.comm	_amdgpu_vm_fault_stop,8,3       ; @amdgpu_vm_fault_stop
	.comm	_AMDGPU_VM_FAULT_STOP_ALWAYS,8,3 ; @AMDGPU_VM_FAULT_STOP_ALWAYS
	.comm	_CHIP_KAVERI,8,3                ; @CHIP_KAVERI
	.comm	_mmCHUB_CONTROL,4,2             ; @mmCHUB_CONTROL
	.comm	_BYPASS_VM,4,2                  ; @BYPASS_VM
l_.str.1:                               ; @.str.1
	.asciz	"PCIE GART of %uM enabled (table at 0x%016llX).\n"

	.no_dead_strip	_gmc_v7_0_gart_enable
.subsections_via_symbols
