	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function nbio_v7_0_update_medium_grain_light_sleep
_nbio_v7_0_update_medium_grain_light_sleep: ## @nbio_v7_0_update_medium_grain_light_sleep
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %ebx
	movq	%rdi, %r14
	movq	_smnPCIE_CNTL2@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32_PCIE
	testl	%ebx, %ebx
	je	LBB0_3
## %bb.1:
	movq	_AMD_CG_SUPPORT_BIF_LS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, (%r14)
	je	LBB0_3
## %bb.2:
	movq	_PCIE_CNTL2__SLV_MEM_LS_EN_MASK@GOTPCREL(%rip), %rcx
	movq	_PCIE_CNTL2__MST_MEM_LS_EN_MASK@GOTPCREL(%rip), %rdx
	movq	_PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK@GOTPCREL(%rip), %rdi
	movl	(%rcx), %esi
	orl	%eax, %esi
	orl	(%rdx), %esi
	orl	(%rdi), %esi
	cmpl	%esi, %eax
	je	LBB0_5
LBB0_6:
	movl	(%r15), %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_PCIE                    ## TAILCALL
LBB0_3:
	movq	_PCIE_CNTL2__SLV_MEM_LS_EN_MASK@GOTPCREL(%rip), %rcx
	movq	_PCIE_CNTL2__MST_MEM_LS_EN_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	movq	_PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	cmpl	%esi, %eax
	jne	LBB0_6
LBB0_5:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_smnPCIE_CNTL2,4,2              ## @smnPCIE_CNTL2
	.comm	_AMD_CG_SUPPORT_BIF_LS,4,2      ## @AMD_CG_SUPPORT_BIF_LS
	.comm	_PCIE_CNTL2__SLV_MEM_LS_EN_MASK,4,2 ## @PCIE_CNTL2__SLV_MEM_LS_EN_MASK
	.comm	_PCIE_CNTL2__MST_MEM_LS_EN_MASK,4,2 ## @PCIE_CNTL2__MST_MEM_LS_EN_MASK
	.comm	_PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK,4,2 ## @PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK
	.no_dead_strip	_nbio_v7_0_update_medium_grain_light_sleep
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function nbio_v7_0_update_medium_grain_light_sleep
_nbio_v7_0_update_medium_grain_light_sleep: ; @nbio_v7_0_update_medium_grain_light_sleep
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x21, _smnPCIE_CNTL2@GOTPAGE
Lloh1:
	ldr	x21, [x21, _smnPCIE_CNTL2@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32_PCIE
	cbz	w20, LBB0_4
; %bb.1:
	ldr	w8, [x19]
Lloh2:
	adrp	x9, _AMD_CG_SUPPORT_BIF_LS@GOTPAGE
Lloh3:
	ldr	x9, [x9, _AMD_CG_SUPPORT_BIF_LS@GOTPAGEOFF]
Lloh4:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_4
; %bb.2:
Lloh5:
	adrp	x8, _PCIE_CNTL2__SLV_MEM_LS_EN_MASK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _PCIE_CNTL2__SLV_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
Lloh8:
	adrp	x9, _PCIE_CNTL2__MST_MEM_LS_EN_MASK@GOTPAGE
Lloh9:
	ldr	x9, [x9, _PCIE_CNTL2__MST_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
Lloh11:
	adrp	x10, _PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK@GOTPAGE
Lloh12:
	ldr	x10, [x10, _PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh13:
	ldr	w10, [x10]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w1, w8, w10
	cmp	w0, w1
	b.eq	LBB0_5
LBB0_3:
	ldr	w0, [x21]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32_PCIE
LBB0_4:
Lloh14:
	adrp	x8, _PCIE_CNTL2__SLV_MEM_LS_EN_MASK@GOTPAGE
Lloh15:
	ldr	x8, [x8, _PCIE_CNTL2__SLV_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
Lloh17:
	adrp	x9, _PCIE_CNTL2__MST_MEM_LS_EN_MASK@GOTPAGE
Lloh18:
	ldr	x9, [x9, _PCIE_CNTL2__MST_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh20:
	adrp	x9, _PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK@GOTPAGE
Lloh21:
	ldr	x9, [x9, _PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w1, w0, w8
	cmp	w0, w1
	b.ne	LBB0_3
LBB0_5:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.cfi_endproc
                                        ; -- End function
	.comm	_smnPCIE_CNTL2,4,2              ; @smnPCIE_CNTL2
	.comm	_AMD_CG_SUPPORT_BIF_LS,4,2      ; @AMD_CG_SUPPORT_BIF_LS
	.comm	_PCIE_CNTL2__SLV_MEM_LS_EN_MASK,4,2 ; @PCIE_CNTL2__SLV_MEM_LS_EN_MASK
	.comm	_PCIE_CNTL2__MST_MEM_LS_EN_MASK,4,2 ; @PCIE_CNTL2__MST_MEM_LS_EN_MASK
	.comm	_PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK,4,2 ; @PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK
	.no_dead_strip	_nbio_v7_0_update_medium_grain_light_sleep
.subsections_via_symbols
