	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v2_5_enable_clock_gating
_vcn_v2_5_enable_clock_gating:          ## @vcn_v2_5_enable_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	4(%rdi), %eax
	testl	%eax, %eax
	jle	LBB0_5
## %bb.1:
	movq	%rdi, %r14
	xorl	%ebx, %ebx
	movq	_VCN@GOTPCREL(%rip), %r15
	movq	_mmUVD_CGC_CTRL@GOTPCREL(%rip), %r12
	movq	_mmUVD_SUVD_CGC_CTRL@GOTPCREL(%rip), %r13
	jmp	LBB0_2
	.p2align	4, 0x90
LBB0_4:                                 ##   in Loop: Header=BB0_2 Depth=1
	incl	%ebx
	cmpl	%eax, %ebx
	jge	LBB0_5
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movl	8(%r14), %ecx
	btl	%ebx, %ecx
	jb	LBB0_4
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movl	(%r15), %edi
	movl	(%r12), %edx
	movl	%ebx, %esi
	callq	_RREG32_SOC15
	movq	_UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPCREL(%rip), %rcx
	movzbl	(%rcx), %ecx
	movl	$1, %edx
	shll	%cl, %edx
	movq	_AMD_CG_SUPPORT_VCN_MGCG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	(%r14), %ecx
	testl	%ecx, %ecx
	cmovel	%ecx, %edx
	orl	%eax, %edx
	movq	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPCREL(%rip), %rax
	movzbl	(%rax), %esi
	movq	_UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPCREL(%rip), %rax
	movzbl	(%rax), %ecx
	movl	$4, %eax
	shll	%cl, %eax
	btsl	%esi, %edx
	orl	%edx, %eax
	movl	(%r15), %edi
	movl	(%r12), %edx
	movl	%ebx, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r15), %edi
	movl	(%r12), %edx
	movl	%ebx, %esi
	callq	_RREG32_SOC15
	movq	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__SYS_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__REGS_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__RBC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__MPC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__WCB_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r15), %edi
	movl	(%r12), %edx
	movl	%ebx, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r15), %edi
	movl	(%r13), %edx
	movl	%ebx, %esi
	callq	_RREG32_SOC15
	movq	_UVD_SUVD_CGC_CTRL__SRE_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_CTRL__SIT_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_CTRL__SMP_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_CTRL__SCM_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_CTRL__SDB_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_CTRL__ENT_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_CTRL__IME_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_CTRL__SITE_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r15), %edi
	movl	(%r13), %edx
	movl	%ebx, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	4(%r14), %eax
	jmp	LBB0_4
LBB0_5:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_VCN,4,2                        ## @VCN
	.comm	_mmUVD_CGC_CTRL,4,2             ## @mmUVD_CGC_CTRL
	.comm	_AMD_CG_SUPPORT_VCN_MGCG,4,2    ## @AMD_CG_SUPPORT_VCN_MGCG
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT,4,2 ## @UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT
	.comm	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT,4,2 ## @UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
	.comm	_UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT,4,2 ## @UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT
	.comm	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_RE_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_CM_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_IT_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_DB_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_MP_MODE_MASK
	.comm	_UVD_CGC_CTRL__SYS_MODE_MASK,4,2 ## @UVD_CGC_CTRL__SYS_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPEG2_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPEG2_MODE_MASK
	.comm	_UVD_CGC_CTRL__REGS_MODE_MASK,4,2 ## @UVD_CGC_CTRL__REGS_MODE_MASK
	.comm	_UVD_CGC_CTRL__RBC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__RBC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_MC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LMI_MC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LMI_UMC_MODE_MASK
	.comm	_UVD_CGC_CTRL__IDCT_MODE_MASK,4,2 ## @UVD_CGC_CTRL__IDCT_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPRD_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPRD_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LBSI_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LBSI_MODE_MASK
	.comm	_UVD_CGC_CTRL__LRBBM_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LRBBM_MODE_MASK
	.comm	_UVD_CGC_CTRL__WCB_MODE_MASK,4,2 ## @UVD_CGC_CTRL__WCB_MODE_MASK
	.comm	_UVD_CGC_CTRL__VCPU_MODE_MASK,4,2 ## @UVD_CGC_CTRL__VCPU_MODE_MASK
	.comm	_mmUVD_SUVD_CGC_CTRL,4,2        ## @mmUVD_SUVD_CGC_CTRL
	.comm	_UVD_SUVD_CGC_CTRL__SRE_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SIT_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SMP_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SCM_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SDB_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__ENT_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__IME_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__IME_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SITE_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
	.no_dead_strip	_vcn_v2_5_enable_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v2_5_enable_clock_gating
_vcn_v2_5_enable_clock_gating:          ; @vcn_v2_5_enable_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	ldr	w8, [x0, #4]
	cmp	w8, #1
	b.lt	LBB0_5
; %bb.1:
	mov	x19, x0
	mov	w20, #0
Lloh0:
	adrp	x21, _VCN@GOTPAGE
Lloh1:
	ldr	x21, [x21, _VCN@GOTPAGEOFF]
Lloh2:
	adrp	x22, _mmUVD_CGC_CTRL@GOTPAGE
Lloh3:
	ldr	x22, [x22, _mmUVD_CGC_CTRL@GOTPAGEOFF]
	mov	w25, #1
Lloh4:
	adrp	x28, _mmUVD_SUVD_CGC_CTRL@GOTPAGE
Lloh5:
	ldr	x28, [x28, _mmUVD_SUVD_CGC_CTRL@GOTPAGEOFF]
Lloh6:
	adrp	x26, _UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK@GOTPAGE
Lloh7:
	ldr	x26, [x26, _UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK@GOTPAGEOFF]
Lloh8:
	adrp	x27, _UVD_SUVD_CGC_CTRL__ENT_MODE_MASK@GOTPAGE
Lloh9:
	ldr	x27, [x27, _UVD_SUVD_CGC_CTRL__ENT_MODE_MASK@GOTPAGEOFF]
Lloh10:
	adrp	x23, _UVD_SUVD_CGC_CTRL__IME_MODE_MASK@GOTPAGE
Lloh11:
	ldr	x23, [x23, _UVD_SUVD_CGC_CTRL__IME_MODE_MASK@GOTPAGEOFF]
Lloh12:
	adrp	x24, _UVD_SUVD_CGC_CTRL__SITE_MODE_MASK@GOTPAGE
Lloh13:
	ldr	x24, [x24, _UVD_SUVD_CGC_CTRL__SITE_MODE_MASK@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:                                 ;   in Loop: Header=BB0_3 Depth=1
	add	w20, w20, #1
	cmp	w20, w8
	b.ge	LBB0_5
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w9, [x19, #8]
	lsr	w9, w9, w20
	tbnz	w9, #0, LBB0_2
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	ldr	w0, [x21]
	ldr	w2, [x22]
	mov	x1, x20
	bl	_RREG32_SOC15
	ldr	w8, [x19]
Lloh14:
	adrp	x9, _AMD_CG_SUPPORT_VCN_MGCG@GOTPAGE
Lloh15:
	ldr	x9, [x9, _AMD_CG_SUPPORT_VCN_MGCG@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
Lloh17:
	adrp	x10, _UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPAGE
Lloh18:
	ldr	x10, [x10, _UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPAGEOFF]
Lloh19:
	ldr	w10, [x10]
	lsl	w10, w25, w10
	tst	w9, w8
	csel	w8, wzr, w10, eq
	orr	w8, w8, w0
Lloh20:
	adrp	x9, _UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPAGE
Lloh21:
	ldr	x9, [x9, _UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	lsl	w9, w25, w9
	orr	w8, w8, w9
Lloh23:
	adrp	x9, _UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPAGE
Lloh24:
	ldr	x9, [x9, _UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPAGEOFF]
Lloh25:
	ldr	w9, [x9]
	mov	w10, #4
	lsl	w9, w10, w9
	orr	w3, w8, w9
	ldr	w0, [x21]
	ldr	w2, [x22]
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w0, [x21]
	ldr	w2, [x22]
	mov	x1, x20
	bl	_RREG32_SOC15
Lloh26:
	adrp	x8, _UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPAGE
Lloh27:
	ldr	x8, [x8, _UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
Lloh29:
	adrp	x9, _UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPAGE
Lloh30:
	ldr	x9, [x9, _UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPAGEOFF]
Lloh31:
	ldr	w9, [x9]
	orr	w8, w8, w0
Lloh32:
	adrp	x10, _UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPAGE
Lloh33:
	ldr	x10, [x10, _UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPAGEOFF]
Lloh34:
	ldr	w10, [x10]
	orr	w8, w8, w9
Lloh35:
	adrp	x9, _UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPAGE
Lloh36:
	ldr	x9, [x9, _UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPAGEOFF]
Lloh37:
	ldr	w9, [x9]
	orr	w8, w8, w10
Lloh38:
	adrp	x10, _UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPAGE
Lloh39:
	ldr	x10, [x10, _UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPAGEOFF]
Lloh40:
	ldr	w10, [x10]
	orr	w8, w8, w9
Lloh41:
	adrp	x9, _UVD_CGC_CTRL__SYS_MODE_MASK@GOTPAGE
Lloh42:
	ldr	x9, [x9, _UVD_CGC_CTRL__SYS_MODE_MASK@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
	orr	w8, w8, w10
Lloh44:
	adrp	x10, _UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPAGE
Lloh45:
	ldr	x10, [x10, _UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPAGEOFF]
Lloh46:
	ldr	w10, [x10]
	orr	w8, w8, w9
Lloh47:
	adrp	x9, _UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPAGE
Lloh48:
	ldr	x9, [x9, _UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPAGEOFF]
Lloh49:
	ldr	w9, [x9]
	orr	w8, w8, w10
Lloh50:
	adrp	x10, _UVD_CGC_CTRL__REGS_MODE_MASK@GOTPAGE
Lloh51:
	ldr	x10, [x10, _UVD_CGC_CTRL__REGS_MODE_MASK@GOTPAGEOFF]
Lloh52:
	ldr	w10, [x10]
	orr	w8, w8, w9
Lloh53:
	adrp	x9, _UVD_CGC_CTRL__RBC_MODE_MASK@GOTPAGE
Lloh54:
	ldr	x9, [x9, _UVD_CGC_CTRL__RBC_MODE_MASK@GOTPAGEOFF]
Lloh55:
	ldr	w9, [x9]
	orr	w8, w8, w10
Lloh56:
	adrp	x10, _UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPAGE
Lloh57:
	ldr	x10, [x10, _UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPAGEOFF]
Lloh58:
	ldr	w10, [x10]
	orr	w8, w8, w9
Lloh59:
	adrp	x9, _UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPAGE
Lloh60:
	ldr	x9, [x9, _UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPAGEOFF]
Lloh61:
	ldr	w9, [x9]
	orr	w8, w8, w10
Lloh62:
	adrp	x10, _UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPAGE
Lloh63:
	ldr	x10, [x10, _UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPAGEOFF]
Lloh64:
	ldr	w10, [x10]
	orr	w8, w8, w9
Lloh65:
	adrp	x9, _UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPAGE
Lloh66:
	ldr	x9, [x9, _UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPAGEOFF]
Lloh67:
	ldr	w9, [x9]
	orr	w8, w8, w10
Lloh68:
	adrp	x10, _UVD_CGC_CTRL__MPC_MODE_MASK@GOTPAGE
Lloh69:
	ldr	x10, [x10, _UVD_CGC_CTRL__MPC_MODE_MASK@GOTPAGEOFF]
Lloh70:
	ldr	w10, [x10]
	orr	w8, w8, w9
Lloh71:
	adrp	x9, _UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPAGE
Lloh72:
	ldr	x9, [x9, _UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPAGEOFF]
Lloh73:
	ldr	w9, [x9]
	orr	w8, w8, w10
Lloh74:
	adrp	x10, _UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPAGE
Lloh75:
	ldr	x10, [x10, _UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPAGEOFF]
Lloh76:
	ldr	w10, [x10]
	orr	w8, w8, w9
Lloh77:
	adrp	x9, _UVD_CGC_CTRL__WCB_MODE_MASK@GOTPAGE
Lloh78:
	ldr	x9, [x9, _UVD_CGC_CTRL__WCB_MODE_MASK@GOTPAGEOFF]
Lloh79:
	ldr	w9, [x9]
	orr	w8, w8, w10
Lloh80:
	adrp	x10, _UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPAGE
Lloh81:
	ldr	x10, [x10, _UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPAGEOFF]
Lloh82:
	ldr	w10, [x10]
	orr	w8, w8, w9
	orr	w3, w8, w10
	ldr	w0, [x21]
	ldr	w2, [x22]
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w0, [x21]
	ldr	w2, [x28]
	mov	x1, x20
	bl	_RREG32_SOC15
Lloh83:
	adrp	x8, _UVD_SUVD_CGC_CTRL__SRE_MODE_MASK@GOTPAGE
Lloh84:
	ldr	x8, [x8, _UVD_SUVD_CGC_CTRL__SRE_MODE_MASK@GOTPAGEOFF]
Lloh85:
	ldr	w8, [x8]
Lloh86:
	adrp	x9, _UVD_SUVD_CGC_CTRL__SIT_MODE_MASK@GOTPAGE
Lloh87:
	ldr	x9, [x9, _UVD_SUVD_CGC_CTRL__SIT_MODE_MASK@GOTPAGEOFF]
Lloh88:
	ldr	w9, [x9]
Lloh89:
	adrp	x10, _UVD_SUVD_CGC_CTRL__SMP_MODE_MASK@GOTPAGE
Lloh90:
	ldr	x10, [x10, _UVD_SUVD_CGC_CTRL__SMP_MODE_MASK@GOTPAGEOFF]
Lloh91:
	ldr	w10, [x10]
Lloh92:
	adrp	x11, _UVD_SUVD_CGC_CTRL__SCM_MODE_MASK@GOTPAGE
Lloh93:
	ldr	x11, [x11, _UVD_SUVD_CGC_CTRL__SCM_MODE_MASK@GOTPAGEOFF]
Lloh94:
	ldr	w11, [x11]
Lloh95:
	adrp	x12, _UVD_SUVD_CGC_CTRL__SDB_MODE_MASK@GOTPAGE
Lloh96:
	ldr	x12, [x12, _UVD_SUVD_CGC_CTRL__SDB_MODE_MASK@GOTPAGEOFF]
Lloh97:
	ldr	w12, [x12]
Lloh98:
	adrp	x13, _UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK@GOTPAGE
Lloh99:
	ldr	x13, [x13, _UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK@GOTPAGEOFF]
Lloh100:
	ldr	w13, [x13]
	ldr	w14, [x26]
	ldr	w15, [x27]
	ldr	w16, [x23]
	ldr	w17, [x24]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w8, w8, w13
	orr	w8, w8, w14
	orr	w8, w8, w15
	orr	w8, w8, w16
	orr	w3, w8, w17
	ldr	w0, [x21]
	ldr	w2, [x28]
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w8, [x19, #4]
	b	LBB0_2
LBB0_5:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.cfi_endproc
                                        ; -- End function
	.comm	_VCN,4,2                        ; @VCN
	.comm	_mmUVD_CGC_CTRL,4,2             ; @mmUVD_CGC_CTRL
	.comm	_AMD_CG_SUPPORT_VCN_MGCG,4,2    ; @AMD_CG_SUPPORT_VCN_MGCG
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT,4,2 ; @UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT
	.comm	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT,4,2 ; @UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
	.comm	_UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT,4,2 ; @UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT
	.comm	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_RE_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_CM_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_IT_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_DB_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_MP_MODE_MASK
	.comm	_UVD_CGC_CTRL__SYS_MODE_MASK,4,2 ; @UVD_CGC_CTRL__SYS_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPEG2_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPEG2_MODE_MASK
	.comm	_UVD_CGC_CTRL__REGS_MODE_MASK,4,2 ; @UVD_CGC_CTRL__REGS_MODE_MASK
	.comm	_UVD_CGC_CTRL__RBC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__RBC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_MC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LMI_MC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LMI_UMC_MODE_MASK
	.comm	_UVD_CGC_CTRL__IDCT_MODE_MASK,4,2 ; @UVD_CGC_CTRL__IDCT_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPRD_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPRD_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LBSI_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LBSI_MODE_MASK
	.comm	_UVD_CGC_CTRL__LRBBM_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LRBBM_MODE_MASK
	.comm	_UVD_CGC_CTRL__WCB_MODE_MASK,4,2 ; @UVD_CGC_CTRL__WCB_MODE_MASK
	.comm	_UVD_CGC_CTRL__VCPU_MODE_MASK,4,2 ; @UVD_CGC_CTRL__VCPU_MODE_MASK
	.comm	_mmUVD_SUVD_CGC_CTRL,4,2        ; @mmUVD_SUVD_CGC_CTRL
	.comm	_UVD_SUVD_CGC_CTRL__SRE_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SIT_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SMP_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SCM_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SDB_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__ENT_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__IME_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__IME_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SITE_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
	.no_dead_strip	_vcn_v2_5_enable_clock_gating
.subsections_via_symbols
