	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function cik_program_aspm
_cik_program_aspm:                      ## @cik_program_aspm
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_amdgpu_aspm@GOTPCREL(%rip), %rax
	cmpq	$0, (%rax)
	je	LBB0_41
## %bb.1:
	movq	%rdi, %r14
	movq	8(%rdi), %rax
	movq	(%rax), %rdi
	callq	_pci_is_root_bus
	testq	%rax, %rax
	jne	LBB0_41
## %bb.2:
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r14)
	jne	LBB0_41
## %bb.3:
	movq	_ixPCIE_LC_N_FTS_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32_PCIE
	movq	_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$36, %edx
	shll	%cl, %edx
	movq	_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	orl	%edx, %esi
	cmpl	%esi, %eax
	je	LBB0_5
## %bb.4:
	movl	(%r15), %edi
	callq	_WREG32_PCIE
LBB0_5:
	movq	_ixPCIE_LC_CNTL3@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE
	movq	_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	%eax, %esi
	cmpl	%esi, %eax
	je	LBB0_7
## %bb.6:
	movl	(%rbx), %edi
	callq	_WREG32_PCIE
LBB0_7:
	movq	_ixPCIE_P_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE
	movq	_PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	%eax, %esi
	cmpl	%esi, %eax
	je	LBB0_9
## %bb.8:
	movl	(%rbx), %edi
	callq	_WREG32_PCIE
LBB0_9:
	movq	_ixPCIE_LC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PCIE
	movq	_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK@GOTPCREL(%rip), %rsi
	movq	_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rsi), %edx
	notl	%edx
	andl	%eax, %edx
	movq	_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	%esi, %edx
	movq	_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$7, %edi
	shll	%cl, %edi
	movl	$7, %r12d
	movq	_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$7, %ebx
	shll	%cl, %ebx
	orl	%edi, %ebx
	orl	%edx, %ebx
	notl	%esi
	andl	%ebx, %esi
	cmpl	%esi, %eax
	je	LBB0_11
## %bb.10:
	movq	_ixPCIE_LC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32_PCIE
LBB0_11:
	movq	_ixPB0_PIF_PWRDOWN_0@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_RREG32_PCIE
	movq	_PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK@GOTPCREL(%rip), %rcx
	movq	_PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	movq	_PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movq	_PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT@GOTPCREL(%rip), %rdx
	movb	(%rdx), %dl
	movl	$7, %edi
	shll	%cl, %edi
	notl	%esi
	movl	%edx, %ecx
	shll	%cl, %r12d
	andl	%eax, %esi
	orl	%esi, %edi
	orl	%edi, %r12d
	cmpl	%r12d, %eax
	je	LBB0_13
## %bb.12:
	movl	(%r13), %edi
	movl	%r12d, %esi
	callq	_WREG32_PCIE
LBB0_13:
	movq	_ixPB0_PIF_PWRDOWN_1@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_RREG32_PCIE
	movq	_PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK@GOTPCREL(%rip), %rcx
	movq	_PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	movq	_PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$7, %edi
	shll	%cl, %edi
	notl	%edx
	andl	%eax, %edx
	movq	_PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$7, %esi
	shll	%cl, %esi
	orl	%edx, %edi
	movl	$7, %ebx
	orl	%edi, %esi
	cmpl	%esi, %eax
	je	LBB0_15
## %bb.14:
	movl	(%r13), %edi
	callq	_WREG32_PCIE
LBB0_15:
	movq	_ixPB1_PIF_PWRDOWN_0@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_RREG32_PCIE
	movq	_PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK@GOTPCREL(%rip), %rcx
	movq	_PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	movq	_PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movq	_PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT@GOTPCREL(%rip), %rdx
	movb	(%rdx), %dl
	movl	$7, %edi
	shll	%cl, %edi
	notl	%esi
	movl	%edx, %ecx
	shll	%cl, %ebx
	andl	%eax, %esi
	orl	%esi, %edi
	orl	%edi, %ebx
	cmpl	%ebx, %eax
	je	LBB0_17
## %bb.16:
	movl	(%r13), %edi
	movl	%ebx, %esi
	callq	_WREG32_PCIE
LBB0_17:
	movq	_ixPB1_PIF_PWRDOWN_1@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE
	movq	_PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$7, %edx
	shll	%cl, %edx
	movq	_PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK@GOTPCREL(%rip), %rcx
	movq	_PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK@GOTPCREL(%rip), %rsi
	movl	(%rsi), %edi
	orl	(%rcx), %edi
	notl	%edi
	movq	_PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$7, %esi
	shll	%cl, %esi
	andl	%eax, %edi
	orl	%edi, %edx
	orl	%edx, %esi
	cmpl	%esi, %eax
	je	LBB0_19
## %bb.18:
	movl	(%rbx), %edi
	callq	_WREG32_PCIE
LBB0_19:
	movq	_ixPCIE_LC_LINK_WIDTH_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE
	movq	_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movq	_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$3, %esi
	shll	%cl, %esi
	andl	%eax, %edx
	notl	%esi
	orl	%edx, %esi
	cmpl	%esi, %eax
	je	LBB0_21
## %bb.20:
	movl	(%rbx), %edi
	callq	_WREG32_PCIE
LBB0_21:
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movq	(%rax), %rdi
	movq	_PCI_EXP_LNKCAP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-44(%rbp), %rdx
	callq	_pcie_capability_read_dword
	movq	_PCI_EXP_LNKCAP_CLKPM@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	-44(%rbp), %eax
	je	LBB0_34
## %bb.22:
	movq	_ixPCIE_LC_CNTL2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE
	movq	_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK@GOTPCREL(%rip), %rcx
	movq	_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK@GOTPCREL(%rip), %rdx
	movl	(%rcx), %esi
	orl	%eax, %esi
	orl	(%rdx), %esi
	cmpl	%esi, %eax
	je	LBB0_24
## %bb.23:
	movl	(%rbx), %edi
	callq	_WREG32_PCIE
LBB0_24:
	movq	_ixTHM_CLK_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_SMC
	movq	_THM_CLK_CNTL__CMON_CLK_SEL_MASK@GOTPCREL(%rip), %rcx
	movq	_THM_CLK_CNTL__TMON_CLK_SEL_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_THM_CLK_CNTL__CMON_CLK_SEL__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movq	_THM_CLK_CNTL__TMON_CLK_SEL__SHIFT@GOTPCREL(%rip), %rdx
	movb	(%rdx), %dl
	btsl	%ecx, %esi
	btsl	%edx, %esi
	cmpl	%esi, %eax
	je	LBB0_26
## %bb.25:
	movl	(%rbx), %edi
	callq	_WREG32_SMC
LBB0_26:
	movq	_ixMISC_CLK_CTRL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_SMC
	movq	_MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK@GOTPCREL(%rip), %rcx
	movq	_MISC_CLK_CTRL__ZCLK_SEL_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movq	_MISC_CLK_CTRL__ZCLK_SEL__SHIFT@GOTPCREL(%rip), %rdx
	movb	(%rdx), %dl
	btsl	%ecx, %esi
	btsl	%edx, %esi
	cmpl	%esi, %eax
	je	LBB0_28
## %bb.27:
	movl	(%rbx), %edi
	callq	_WREG32_SMC
LBB0_28:
	movq	_ixCG_CLKPIN_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_SMC
	movq	_CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	cmpl	%esi, %eax
	je	LBB0_30
## %bb.29:
	movl	(%rbx), %edi
	callq	_WREG32_SMC
LBB0_30:
	movq	_ixCG_CLKPIN_CNTL_2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_SMC
	movq	_CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	cmpl	%esi, %eax
	je	LBB0_32
## %bb.31:
	movl	(%rbx), %edi
	callq	_WREG32_SMC
LBB0_32:
	movq	_ixMPLL_BYPASSCLK_SEL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_SMC
	movq	_MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$4, %esi
	shll	%cl, %esi
	notl	%edx
	andl	%eax, %edx
	orl	%edx, %esi
	cmpl	%esi, %eax
	je	LBB0_34
## %bb.33:
	movl	(%rbx), %edi
	callq	_WREG32_SMC
LBB0_34:
	movq	_ixPCIE_CNTL2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE
	movq	_PCIE_CNTL2__SLV_MEM_LS_EN_MASK@GOTPCREL(%rip), %rcx
	movq	_PCIE_CNTL2__MST_MEM_LS_EN_MASK@GOTPCREL(%rip), %rdx
	movl	(%rcx), %esi
	orl	%eax, %esi
	orl	(%rdx), %esi
	movq	_PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	cmpl	%esi, %eax
	je	LBB0_36
## %bb.35:
	movl	(%rbx), %edi
	callq	_WREG32_PCIE
LBB0_36:
	movl	(%r15), %edi
	callq	_RREG32_PCIE
	movq	_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK@GOTPCREL(%rip), %rcx
	notl	%eax
	testl	%eax, (%rcx)
	jne	LBB0_41
## %bb.37:
	movq	_ixPCIE_LC_STATUS1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PCIE
	movq	_PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_41
## %bb.38:
	movq	_PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_41
## %bb.39:
	movq	_ixPCIE_LC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PCIE
	movq	_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	cmpl	%esi, %eax
	je	LBB0_41
## %bb.40:
	movq	_ixPCIE_LC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32_PCIE
LBB0_41:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_amdgpu_aspm,8,3                ## @amdgpu_aspm
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_ixPCIE_LC_N_FTS_CNTL,4,2       ## @ixPCIE_LC_N_FTS_CNTL
	.comm	_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK,4,2 ## @PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK
	.comm	_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT,4,2 ## @PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT
	.comm	_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK,4,2 ## @PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK
	.comm	_ixPCIE_LC_CNTL3,4,2            ## @ixPCIE_LC_CNTL3
	.comm	_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK,4,2 ## @PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK
	.comm	_ixPCIE_P_CNTL,4,2              ## @ixPCIE_P_CNTL
	.comm	_PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK,4,2 ## @PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK
	.comm	_ixPCIE_LC_CNTL,4,2             ## @ixPCIE_LC_CNTL
	.comm	_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK,4,2 ## @PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK
	.comm	_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK,4,2 ## @PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK
	.comm	_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK,4,2 ## @PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK
	.comm	_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT,4,2 ## @PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT
	.comm	_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT,4,2 ## @PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT
	.comm	_ixPB0_PIF_PWRDOWN_0,4,2        ## @ixPB0_PIF_PWRDOWN_0
	.comm	_PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK,4,2 ## @PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK
	.comm	_PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK,4,2 ## @PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK
	.comm	_PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT,4,2 ## @PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT
	.comm	_PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT,4,2 ## @PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT
	.comm	_ixPB0_PIF_PWRDOWN_1,4,2        ## @ixPB0_PIF_PWRDOWN_1
	.comm	_PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK,4,2 ## @PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK
	.comm	_PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK,4,2 ## @PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK
	.comm	_PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT,4,2 ## @PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT
	.comm	_PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT,4,2 ## @PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT
	.comm	_ixPB1_PIF_PWRDOWN_0,4,2        ## @ixPB1_PIF_PWRDOWN_0
	.comm	_PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK,4,2 ## @PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK
	.comm	_PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK,4,2 ## @PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK
	.comm	_PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT,4,2 ## @PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT
	.comm	_PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT,4,2 ## @PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT
	.comm	_ixPB1_PIF_PWRDOWN_1,4,2        ## @ixPB1_PIF_PWRDOWN_1
	.comm	_PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK,4,2 ## @PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK
	.comm	_PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK,4,2 ## @PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK
	.comm	_PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT,4,2 ## @PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT
	.comm	_PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT,4,2 ## @PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT
	.comm	_ixPCIE_LC_LINK_WIDTH_CNTL,4,2  ## @ixPCIE_LC_LINK_WIDTH_CNTL
	.comm	_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK,4,2 ## @PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK
	.comm	_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT,4,2 ## @PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT
	.comm	_PCI_EXP_LNKCAP,4,2             ## @PCI_EXP_LNKCAP
	.comm	_PCI_EXP_LNKCAP_CLKPM,4,2       ## @PCI_EXP_LNKCAP_CLKPM
	.comm	_ixPCIE_LC_CNTL2,4,2            ## @ixPCIE_LC_CNTL2
	.comm	_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK,4,2 ## @PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
	.comm	_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK,4,2 ## @PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
	.comm	_ixTHM_CLK_CNTL,4,2             ## @ixTHM_CLK_CNTL
	.comm	_THM_CLK_CNTL__CMON_CLK_SEL_MASK,4,2 ## @THM_CLK_CNTL__CMON_CLK_SEL_MASK
	.comm	_THM_CLK_CNTL__TMON_CLK_SEL_MASK,4,2 ## @THM_CLK_CNTL__TMON_CLK_SEL_MASK
	.comm	_THM_CLK_CNTL__CMON_CLK_SEL__SHIFT,4,2 ## @THM_CLK_CNTL__CMON_CLK_SEL__SHIFT
	.comm	_THM_CLK_CNTL__TMON_CLK_SEL__SHIFT,4,2 ## @THM_CLK_CNTL__TMON_CLK_SEL__SHIFT
	.comm	_ixMISC_CLK_CTRL,4,2            ## @ixMISC_CLK_CTRL
	.comm	_MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK,4,2 ## @MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK
	.comm	_MISC_CLK_CTRL__ZCLK_SEL_MASK,4,2 ## @MISC_CLK_CTRL__ZCLK_SEL_MASK
	.comm	_MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT,4,2 ## @MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT
	.comm	_MISC_CLK_CTRL__ZCLK_SEL__SHIFT,4,2 ## @MISC_CLK_CTRL__ZCLK_SEL__SHIFT
	.comm	_ixCG_CLKPIN_CNTL,4,2           ## @ixCG_CLKPIN_CNTL
	.comm	_CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK,4,2 ## @CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK
	.comm	_ixCG_CLKPIN_CNTL_2,4,2         ## @ixCG_CLKPIN_CNTL_2
	.comm	_CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK,4,2 ## @CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK
	.comm	_ixMPLL_BYPASSCLK_SEL,4,2       ## @ixMPLL_BYPASSCLK_SEL
	.comm	_MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK,4,2 ## @MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK
	.comm	_MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT,4,2 ## @MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT
	.comm	_ixPCIE_CNTL2,4,2               ## @ixPCIE_CNTL2
	.comm	_PCIE_CNTL2__SLV_MEM_LS_EN_MASK,4,2 ## @PCIE_CNTL2__SLV_MEM_LS_EN_MASK
	.comm	_PCIE_CNTL2__MST_MEM_LS_EN_MASK,4,2 ## @PCIE_CNTL2__MST_MEM_LS_EN_MASK
	.comm	_PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK,4,2 ## @PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK
	.comm	_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK,4,2 ## @PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK
	.comm	_ixPCIE_LC_STATUS1,4,2          ## @ixPCIE_LC_STATUS1
	.comm	_PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK,4,2 ## @PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK
	.comm	_PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK,4,2 ## @PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK
	.no_dead_strip	_cik_program_aspm
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cik_program_aspm
_cik_program_aspm:                      ; @cik_program_aspm
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
Lloh0:
	adrp	x8, _amdgpu_aspm@GOTPAGE
Lloh1:
	ldr	x8, [x8, _amdgpu_aspm@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	cbz	x8, LBB0_41
; %bb.1:
	mov	x19, x0
	ldr	x8, [x0, #8]
	ldr	x0, [x8]
	bl	_pci_is_root_bus
	cbnz	x0, LBB0_41
; %bb.2:
	ldr	w8, [x19]
Lloh3:
	adrp	x9, _AMD_IS_APU@GOTPAGE
Lloh4:
	ldr	x9, [x9, _AMD_IS_APU@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_41
; %bb.3:
Lloh6:
	adrp	x20, _ixPCIE_LC_N_FTS_CNTL@GOTPAGE
Lloh7:
	ldr	x20, [x20, _ixPCIE_LC_N_FTS_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PCIE
Lloh8:
	adrp	x8, _PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK@GOTPAGE
Lloh9:
	ldr	x8, [x8, _PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh11:
	adrp	x9, _PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT@GOTPAGE
Lloh12:
	ldr	x9, [x9, _PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	mov	w10, #36
	lsl	w9, w10, w9
Lloh14:
	adrp	x10, _PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK@GOTPAGE
Lloh15:
	ldr	x10, [x10, _PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w10, [x10]
	orr	w8, w10, w8
	orr	w1, w8, w9
	cmp	w0, w1
	b.eq	LBB0_5
; %bb.4:
	ldr	w0, [x20]
	bl	_WREG32_PCIE
LBB0_5:
Lloh17:
	adrp	x21, _ixPCIE_LC_CNTL3@GOTPAGE
Lloh18:
	ldr	x21, [x21, _ixPCIE_LC_CNTL3@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32_PCIE
Lloh19:
	adrp	x8, _PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK@GOTPAGE
Lloh20:
	ldr	x8, [x8, _PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
	orr	w1, w8, w0
	cmp	w0, w1
	b.eq	LBB0_7
; %bb.6:
	ldr	w0, [x21]
	bl	_WREG32_PCIE
LBB0_7:
Lloh22:
	adrp	x21, _ixPCIE_P_CNTL@GOTPAGE
Lloh23:
	ldr	x21, [x21, _ixPCIE_P_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32_PCIE
Lloh24:
	adrp	x8, _PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK@GOTPAGE
Lloh25:
	ldr	x8, [x8, _PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	orr	w1, w8, w0
	cmp	w0, w1
	b.eq	LBB0_9
; %bb.8:
	ldr	w0, [x21]
	bl	_WREG32_PCIE
LBB0_9:
Lloh27:
	adrp	x21, _ixPCIE_LC_CNTL@GOTPAGE
Lloh28:
	ldr	x21, [x21, _ixPCIE_LC_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32_PCIE
Lloh29:
	adrp	x22, _PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK@GOTPAGE
Lloh30:
	ldr	x22, [x22, _PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK@GOTPAGEOFF]
	ldr	w8, [x22]
Lloh31:
	adrp	x9, _PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK@GOTPAGE
Lloh32:
	ldr	x9, [x9, _PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK@GOTPAGEOFF]
Lloh33:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
Lloh34:
	adrp	x9, _PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK@GOTPAGE
Lloh35:
	ldr	x9, [x9, _PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK@GOTPAGEOFF]
Lloh36:
	ldr	w9, [x9]
Lloh37:
	adrp	x10, _PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT@GOTPAGE
Lloh38:
	ldr	x10, [x10, _PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh39:
	ldr	w10, [x10]
	mov	w23, #7
	lsl	w10, w23, w10
Lloh40:
	adrp	x11, _PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT@GOTPAGE
Lloh41:
	ldr	x11, [x11, _PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT@GOTPAGEOFF]
	orr	w8, w8, w10
Lloh42:
	ldr	w10, [x11]
	lsl	w10, w23, w10
	orr	w8, w8, w10
	bic	w1, w8, w9
	cmp	w0, w1
	b.eq	LBB0_11
; %bb.10:
	ldr	w0, [x21]
	bl	_WREG32_PCIE
LBB0_11:
Lloh43:
	adrp	x24, _ixPB0_PIF_PWRDOWN_0@GOTPAGE
Lloh44:
	ldr	x24, [x24, _ixPB0_PIF_PWRDOWN_0@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_RREG32_PCIE
Lloh45:
	adrp	x8, _PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK@GOTPAGE
Lloh46:
	ldr	x8, [x8, _PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK@GOTPAGEOFF]
Lloh47:
	ldr	w8, [x8]
Lloh48:
	adrp	x9, _PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK@GOTPAGE
Lloh49:
	ldr	x9, [x9, _PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK@GOTPAGEOFF]
Lloh50:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
Lloh51:
	adrp	x9, _PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT@GOTPAGE
Lloh52:
	ldr	x9, [x9, _PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT@GOTPAGEOFF]
Lloh53:
	ldr	w9, [x9]
Lloh54:
	adrp	x10, _PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT@GOTPAGE
Lloh55:
	ldr	x10, [x10, _PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT@GOTPAGEOFF]
	lsl	w9, w23, w9
Lloh56:
	ldr	w10, [x10]
	lsl	w10, w23, w10
	orr	w8, w8, w9
	orr	w1, w8, w10
	cmp	w0, w1
	b.eq	LBB0_13
; %bb.12:
	ldr	w0, [x24]
	bl	_WREG32_PCIE
LBB0_13:
Lloh57:
	adrp	x24, _ixPB0_PIF_PWRDOWN_1@GOTPAGE
Lloh58:
	ldr	x24, [x24, _ixPB0_PIF_PWRDOWN_1@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_RREG32_PCIE
Lloh59:
	adrp	x8, _PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK@GOTPAGE
Lloh60:
	ldr	x8, [x8, _PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK@GOTPAGEOFF]
Lloh61:
	ldr	w8, [x8]
Lloh62:
	adrp	x9, _PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK@GOTPAGE
Lloh63:
	ldr	x9, [x9, _PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK@GOTPAGEOFF]
Lloh64:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
Lloh65:
	adrp	x9, _PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT@GOTPAGE
Lloh66:
	ldr	x9, [x9, _PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT@GOTPAGEOFF]
Lloh67:
	ldr	w9, [x9]
	mov	w23, #7
Lloh68:
	adrp	x10, _PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT@GOTPAGE
Lloh69:
	ldr	x10, [x10, _PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT@GOTPAGEOFF]
	lsl	w9, w23, w9
Lloh70:
	ldr	w10, [x10]
	lsl	w10, w23, w10
	orr	w8, w8, w9
	orr	w1, w8, w10
	cmp	w0, w1
	b.eq	LBB0_15
; %bb.14:
	ldr	w0, [x24]
	bl	_WREG32_PCIE
LBB0_15:
Lloh71:
	adrp	x24, _ixPB1_PIF_PWRDOWN_0@GOTPAGE
Lloh72:
	ldr	x24, [x24, _ixPB1_PIF_PWRDOWN_0@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_RREG32_PCIE
Lloh73:
	adrp	x8, _PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK@GOTPAGE
Lloh74:
	ldr	x8, [x8, _PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK@GOTPAGEOFF]
Lloh75:
	ldr	w8, [x8]
Lloh76:
	adrp	x9, _PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK@GOTPAGE
Lloh77:
	ldr	x9, [x9, _PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK@GOTPAGEOFF]
Lloh78:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
Lloh79:
	adrp	x9, _PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT@GOTPAGE
Lloh80:
	ldr	x9, [x9, _PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT@GOTPAGEOFF]
Lloh81:
	ldr	w9, [x9]
Lloh82:
	adrp	x10, _PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT@GOTPAGE
Lloh83:
	ldr	x10, [x10, _PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT@GOTPAGEOFF]
	lsl	w9, w23, w9
Lloh84:
	ldr	w10, [x10]
	lsl	w10, w23, w10
	orr	w8, w8, w9
	orr	w1, w8, w10
	cmp	w0, w1
	b.eq	LBB0_17
; %bb.16:
	ldr	w0, [x24]
	bl	_WREG32_PCIE
LBB0_17:
Lloh85:
	adrp	x23, _ixPB1_PIF_PWRDOWN_1@GOTPAGE
Lloh86:
	ldr	x23, [x23, _ixPB1_PIF_PWRDOWN_1@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32_PCIE
Lloh87:
	adrp	x8, _PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK@GOTPAGE
Lloh88:
	ldr	x8, [x8, _PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK@GOTPAGEOFF]
Lloh89:
	ldr	w8, [x8]
Lloh90:
	adrp	x9, _PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK@GOTPAGE
Lloh91:
	ldr	x9, [x9, _PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK@GOTPAGEOFF]
Lloh92:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
Lloh93:
	adrp	x9, _PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT@GOTPAGE
Lloh94:
	ldr	x9, [x9, _PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT@GOTPAGEOFF]
Lloh95:
	ldr	w9, [x9]
	mov	w10, #7
Lloh96:
	adrp	x11, _PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT@GOTPAGE
Lloh97:
	ldr	x11, [x11, _PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT@GOTPAGEOFF]
	lsl	w9, w10, w9
Lloh98:
	ldr	w11, [x11]
	lsl	w10, w10, w11
	orr	w8, w8, w9
	orr	w1, w8, w10
	cmp	w0, w1
	b.eq	LBB0_19
; %bb.18:
	ldr	w0, [x23]
	bl	_WREG32_PCIE
LBB0_19:
Lloh99:
	adrp	x23, _ixPCIE_LC_LINK_WIDTH_CNTL@GOTPAGE
Lloh100:
	ldr	x23, [x23, _ixPCIE_LC_LINK_WIDTH_CNTL@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32_PCIE
Lloh101:
	adrp	x8, _PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK@GOTPAGE
Lloh102:
	ldr	x8, [x8, _PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK@GOTPAGEOFF]
Lloh103:
	ldr	w8, [x8]
Lloh104:
	adrp	x9, _PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT@GOTPAGE
Lloh105:
	ldr	x9, [x9, _PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT@GOTPAGEOFF]
	bic	w8, w0, w8
Lloh106:
	ldr	w9, [x9]
	mov	w10, #3
	lsl	w9, w10, w9
	orn	w1, w8, w9
	cmp	w0, w1
	b.eq	LBB0_21
; %bb.20:
	ldr	w0, [x23]
	bl	_WREG32_PCIE
LBB0_21:
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	ldr	x0, [x8]
Lloh107:
	adrp	x8, _PCI_EXP_LNKCAP@GOTPAGE
Lloh108:
	ldr	x8, [x8, _PCI_EXP_LNKCAP@GOTPAGEOFF]
Lloh109:
	ldr	w1, [x8]
	add	x2, sp, #12
	bl	_pcie_capability_read_dword
	ldr	w8, [sp, #12]
Lloh110:
	adrp	x9, _PCI_EXP_LNKCAP_CLKPM@GOTPAGE
Lloh111:
	ldr	x9, [x9, _PCI_EXP_LNKCAP_CLKPM@GOTPAGEOFF]
Lloh112:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_34
; %bb.22:
Lloh113:
	adrp	x19, _ixPCIE_LC_CNTL2@GOTPAGE
Lloh114:
	ldr	x19, [x19, _ixPCIE_LC_CNTL2@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PCIE
Lloh115:
	adrp	x8, _PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK@GOTPAGE
Lloh116:
	ldr	x8, [x8, _PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK@GOTPAGEOFF]
Lloh117:
	ldr	w8, [x8]
Lloh118:
	adrp	x9, _PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK@GOTPAGE
Lloh119:
	ldr	x9, [x9, _PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK@GOTPAGEOFF]
Lloh120:
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w1, w8, w9
	cmp	w0, w1
	b.eq	LBB0_24
; %bb.23:
	ldr	w0, [x19]
	bl	_WREG32_PCIE
LBB0_24:
Lloh121:
	adrp	x23, _ixTHM_CLK_CNTL@GOTPAGE
Lloh122:
	ldr	x23, [x23, _ixTHM_CLK_CNTL@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32_SMC
Lloh123:
	adrp	x8, _THM_CLK_CNTL__CMON_CLK_SEL_MASK@GOTPAGE
Lloh124:
	ldr	x8, [x8, _THM_CLK_CNTL__CMON_CLK_SEL_MASK@GOTPAGEOFF]
Lloh125:
	ldr	w8, [x8]
Lloh126:
	adrp	x9, _THM_CLK_CNTL__TMON_CLK_SEL_MASK@GOTPAGE
Lloh127:
	ldr	x9, [x9, _THM_CLK_CNTL__TMON_CLK_SEL_MASK@GOTPAGEOFF]
Lloh128:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
Lloh129:
	adrp	x9, _THM_CLK_CNTL__CMON_CLK_SEL__SHIFT@GOTPAGE
Lloh130:
	ldr	x9, [x9, _THM_CLK_CNTL__CMON_CLK_SEL__SHIFT@GOTPAGEOFF]
Lloh131:
	ldr	w9, [x9]
	mov	w19, #1
Lloh132:
	adrp	x10, _THM_CLK_CNTL__TMON_CLK_SEL__SHIFT@GOTPAGE
Lloh133:
	ldr	x10, [x10, _THM_CLK_CNTL__TMON_CLK_SEL__SHIFT@GOTPAGEOFF]
	lsl	w9, w19, w9
Lloh134:
	ldr	w10, [x10]
	lsl	w10, w19, w10
	orr	w8, w8, w9
	orr	w1, w8, w10
	cmp	w0, w1
	b.eq	LBB0_26
; %bb.25:
	ldr	w0, [x23]
	bl	_WREG32_SMC
LBB0_26:
Lloh135:
	adrp	x23, _ixMISC_CLK_CTRL@GOTPAGE
Lloh136:
	ldr	x23, [x23, _ixMISC_CLK_CTRL@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32_SMC
Lloh137:
	adrp	x8, _MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK@GOTPAGE
Lloh138:
	ldr	x8, [x8, _MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK@GOTPAGEOFF]
Lloh139:
	ldr	w8, [x8]
Lloh140:
	adrp	x9, _MISC_CLK_CTRL__ZCLK_SEL_MASK@GOTPAGE
Lloh141:
	ldr	x9, [x9, _MISC_CLK_CTRL__ZCLK_SEL_MASK@GOTPAGEOFF]
Lloh142:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
Lloh143:
	adrp	x9, _MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT@GOTPAGE
Lloh144:
	ldr	x9, [x9, _MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT@GOTPAGEOFF]
Lloh145:
	ldr	w9, [x9]
Lloh146:
	adrp	x10, _MISC_CLK_CTRL__ZCLK_SEL__SHIFT@GOTPAGE
Lloh147:
	ldr	x10, [x10, _MISC_CLK_CTRL__ZCLK_SEL__SHIFT@GOTPAGEOFF]
	lsl	w9, w19, w9
Lloh148:
	ldr	w10, [x10]
	lsl	w10, w19, w10
	orr	w8, w8, w9
	orr	w1, w8, w10
	cmp	w0, w1
	b.eq	LBB0_28
; %bb.27:
	ldr	w0, [x23]
	bl	_WREG32_SMC
LBB0_28:
Lloh149:
	adrp	x19, _ixCG_CLKPIN_CNTL@GOTPAGE
Lloh150:
	ldr	x19, [x19, _ixCG_CLKPIN_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_SMC
Lloh151:
	adrp	x8, _CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK@GOTPAGE
Lloh152:
	ldr	x8, [x8, _CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK@GOTPAGEOFF]
Lloh153:
	ldr	w8, [x8]
	bic	w1, w0, w8
	cmp	w0, w1
	b.eq	LBB0_30
; %bb.29:
	ldr	w0, [x19]
	bl	_WREG32_SMC
LBB0_30:
Lloh154:
	adrp	x19, _ixCG_CLKPIN_CNTL_2@GOTPAGE
Lloh155:
	ldr	x19, [x19, _ixCG_CLKPIN_CNTL_2@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_SMC
Lloh156:
	adrp	x8, _CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK@GOTPAGE
Lloh157:
	ldr	x8, [x8, _CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK@GOTPAGEOFF]
Lloh158:
	ldr	w8, [x8]
	bic	w1, w0, w8
	cmp	w0, w1
	b.eq	LBB0_32
; %bb.31:
	ldr	w0, [x19]
	bl	_WREG32_SMC
LBB0_32:
Lloh159:
	adrp	x19, _ixMPLL_BYPASSCLK_SEL@GOTPAGE
Lloh160:
	ldr	x19, [x19, _ixMPLL_BYPASSCLK_SEL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_SMC
Lloh161:
	adrp	x8, _MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK@GOTPAGE
Lloh162:
	ldr	x8, [x8, _MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK@GOTPAGEOFF]
Lloh163:
	ldr	w8, [x8]
Lloh164:
	adrp	x9, _MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT@GOTPAGE
Lloh165:
	ldr	x9, [x9, _MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT@GOTPAGEOFF]
	bic	w8, w0, w8
Lloh166:
	ldr	w9, [x9]
	mov	w10, #4
	lsl	w9, w10, w9
	orr	w1, w9, w8
	cmp	w0, w1
	b.eq	LBB0_34
; %bb.33:
	ldr	w0, [x19]
	bl	_WREG32_SMC
LBB0_34:
Lloh167:
	adrp	x19, _ixPCIE_CNTL2@GOTPAGE
Lloh168:
	ldr	x19, [x19, _ixPCIE_CNTL2@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PCIE
Lloh169:
	adrp	x8, _PCIE_CNTL2__SLV_MEM_LS_EN_MASK@GOTPAGE
Lloh170:
	ldr	x8, [x8, _PCIE_CNTL2__SLV_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh171:
	ldr	w8, [x8]
Lloh172:
	adrp	x9, _PCIE_CNTL2__MST_MEM_LS_EN_MASK@GOTPAGE
Lloh173:
	ldr	x9, [x9, _PCIE_CNTL2__MST_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh174:
	adrp	x10, _PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK@GOTPAGE
Lloh175:
	ldr	x10, [x10, _PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh176:
	ldr	w9, [x9]
Lloh177:
	ldr	w10, [x10]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w1, w8, w10
	cmp	w0, w1
	b.eq	LBB0_36
; %bb.35:
	ldr	w0, [x19]
	bl	_WREG32_PCIE
LBB0_36:
	ldr	w0, [x20]
	bl	_RREG32_PCIE
Lloh178:
	adrp	x8, _PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK@GOTPAGE
Lloh179:
	ldr	x8, [x8, _PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK@GOTPAGEOFF]
Lloh180:
	ldr	w8, [x8]
	bics	wzr, w8, w0
	b.ne	LBB0_41
; %bb.37:
Lloh181:
	adrp	x8, _ixPCIE_LC_STATUS1@GOTPAGE
Lloh182:
	ldr	x8, [x8, _ixPCIE_LC_STATUS1@GOTPAGEOFF]
Lloh183:
	ldr	w0, [x8]
	bl	_RREG32_PCIE
Lloh184:
	adrp	x8, _PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK@GOTPAGE
Lloh185:
	ldr	x8, [x8, _PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK@GOTPAGEOFF]
Lloh186:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_41
; %bb.38:
Lloh187:
	adrp	x8, _PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK@GOTPAGE
Lloh188:
	ldr	x8, [x8, _PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK@GOTPAGEOFF]
Lloh189:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_41
; %bb.39:
	ldr	w0, [x21]
	bl	_RREG32_PCIE
	ldr	w8, [x22]
	bic	w1, w0, w8
	cmp	w0, w1
	b.eq	LBB0_41
; %bb.40:
	ldr	w0, [x21]
	bl	_WREG32_PCIE
LBB0_41:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGot	Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGot	Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGot	Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.loh AdrpLdrGot	Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh132, Lloh133, Lloh134
	.loh AdrpLdrGotLdr	Lloh129, Lloh130, Lloh131
	.loh AdrpLdrGotLdr	Lloh126, Lloh127, Lloh128
	.loh AdrpLdrGotLdr	Lloh123, Lloh124, Lloh125
	.loh AdrpLdrGot	Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh146, Lloh147, Lloh148
	.loh AdrpLdrGotLdr	Lloh143, Lloh144, Lloh145
	.loh AdrpLdrGotLdr	Lloh140, Lloh141, Lloh142
	.loh AdrpLdrGotLdr	Lloh137, Lloh138, Lloh139
	.loh AdrpLdrGot	Lloh135, Lloh136
	.loh AdrpLdrGotLdr	Lloh151, Lloh152, Lloh153
	.loh AdrpLdrGot	Lloh149, Lloh150
	.loh AdrpLdrGotLdr	Lloh156, Lloh157, Lloh158
	.loh AdrpLdrGot	Lloh154, Lloh155
	.loh AdrpLdrGotLdr	Lloh164, Lloh165, Lloh166
	.loh AdrpLdrGotLdr	Lloh161, Lloh162, Lloh163
	.loh AdrpLdrGot	Lloh159, Lloh160
	.loh AdrpLdrGotLdr	Lloh174, Lloh175, Lloh177
	.loh AdrpLdrGotLdr	Lloh172, Lloh173, Lloh176
	.loh AdrpLdrGotLdr	Lloh169, Lloh170, Lloh171
	.loh AdrpLdrGot	Lloh167, Lloh168
	.loh AdrpLdrGotLdr	Lloh178, Lloh179, Lloh180
	.loh AdrpLdrGotLdr	Lloh184, Lloh185, Lloh186
	.loh AdrpLdrGotLdr	Lloh181, Lloh182, Lloh183
	.loh AdrpLdrGotLdr	Lloh187, Lloh188, Lloh189
	.cfi_endproc
                                        ; -- End function
	.comm	_amdgpu_aspm,8,3                ; @amdgpu_aspm
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_ixPCIE_LC_N_FTS_CNTL,4,2       ; @ixPCIE_LC_N_FTS_CNTL
	.comm	_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK,4,2 ; @PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK
	.comm	_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT,4,2 ; @PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT
	.comm	_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK,4,2 ; @PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK
	.comm	_ixPCIE_LC_CNTL3,4,2            ; @ixPCIE_LC_CNTL3
	.comm	_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK,4,2 ; @PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK
	.comm	_ixPCIE_P_CNTL,4,2              ; @ixPCIE_P_CNTL
	.comm	_PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK,4,2 ; @PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK
	.comm	_ixPCIE_LC_CNTL,4,2             ; @ixPCIE_LC_CNTL
	.comm	_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK,4,2 ; @PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK
	.comm	_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK,4,2 ; @PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK
	.comm	_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK,4,2 ; @PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK
	.comm	_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT,4,2 ; @PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT
	.comm	_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT,4,2 ; @PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT
	.comm	_ixPB0_PIF_PWRDOWN_0,4,2        ; @ixPB0_PIF_PWRDOWN_0
	.comm	_PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK,4,2 ; @PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK
	.comm	_PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK,4,2 ; @PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK
	.comm	_PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT,4,2 ; @PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT
	.comm	_PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT,4,2 ; @PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT
	.comm	_ixPB0_PIF_PWRDOWN_1,4,2        ; @ixPB0_PIF_PWRDOWN_1
	.comm	_PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK,4,2 ; @PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK
	.comm	_PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK,4,2 ; @PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK
	.comm	_PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT,4,2 ; @PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT
	.comm	_PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT,4,2 ; @PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT
	.comm	_ixPB1_PIF_PWRDOWN_0,4,2        ; @ixPB1_PIF_PWRDOWN_0
	.comm	_PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK,4,2 ; @PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK
	.comm	_PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK,4,2 ; @PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK
	.comm	_PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT,4,2 ; @PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT
	.comm	_PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT,4,2 ; @PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT
	.comm	_ixPB1_PIF_PWRDOWN_1,4,2        ; @ixPB1_PIF_PWRDOWN_1
	.comm	_PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK,4,2 ; @PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK
	.comm	_PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK,4,2 ; @PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK
	.comm	_PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT,4,2 ; @PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT
	.comm	_PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT,4,2 ; @PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT
	.comm	_ixPCIE_LC_LINK_WIDTH_CNTL,4,2  ; @ixPCIE_LC_LINK_WIDTH_CNTL
	.comm	_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK,4,2 ; @PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK
	.comm	_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT,4,2 ; @PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT
	.comm	_PCI_EXP_LNKCAP,4,2             ; @PCI_EXP_LNKCAP
	.comm	_PCI_EXP_LNKCAP_CLKPM,4,2       ; @PCI_EXP_LNKCAP_CLKPM
	.comm	_ixPCIE_LC_CNTL2,4,2            ; @ixPCIE_LC_CNTL2
	.comm	_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK,4,2 ; @PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
	.comm	_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK,4,2 ; @PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
	.comm	_ixTHM_CLK_CNTL,4,2             ; @ixTHM_CLK_CNTL
	.comm	_THM_CLK_CNTL__CMON_CLK_SEL_MASK,4,2 ; @THM_CLK_CNTL__CMON_CLK_SEL_MASK
	.comm	_THM_CLK_CNTL__TMON_CLK_SEL_MASK,4,2 ; @THM_CLK_CNTL__TMON_CLK_SEL_MASK
	.comm	_THM_CLK_CNTL__CMON_CLK_SEL__SHIFT,4,2 ; @THM_CLK_CNTL__CMON_CLK_SEL__SHIFT
	.comm	_THM_CLK_CNTL__TMON_CLK_SEL__SHIFT,4,2 ; @THM_CLK_CNTL__TMON_CLK_SEL__SHIFT
	.comm	_ixMISC_CLK_CTRL,4,2            ; @ixMISC_CLK_CTRL
	.comm	_MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK,4,2 ; @MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK
	.comm	_MISC_CLK_CTRL__ZCLK_SEL_MASK,4,2 ; @MISC_CLK_CTRL__ZCLK_SEL_MASK
	.comm	_MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT,4,2 ; @MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT
	.comm	_MISC_CLK_CTRL__ZCLK_SEL__SHIFT,4,2 ; @MISC_CLK_CTRL__ZCLK_SEL__SHIFT
	.comm	_ixCG_CLKPIN_CNTL,4,2           ; @ixCG_CLKPIN_CNTL
	.comm	_CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK,4,2 ; @CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK
	.comm	_ixCG_CLKPIN_CNTL_2,4,2         ; @ixCG_CLKPIN_CNTL_2
	.comm	_CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK,4,2 ; @CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK
	.comm	_ixMPLL_BYPASSCLK_SEL,4,2       ; @ixMPLL_BYPASSCLK_SEL
	.comm	_MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK,4,2 ; @MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK
	.comm	_MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT,4,2 ; @MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT
	.comm	_ixPCIE_CNTL2,4,2               ; @ixPCIE_CNTL2
	.comm	_PCIE_CNTL2__SLV_MEM_LS_EN_MASK,4,2 ; @PCIE_CNTL2__SLV_MEM_LS_EN_MASK
	.comm	_PCIE_CNTL2__MST_MEM_LS_EN_MASK,4,2 ; @PCIE_CNTL2__MST_MEM_LS_EN_MASK
	.comm	_PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK,4,2 ; @PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK
	.comm	_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK,4,2 ; @PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK
	.comm	_ixPCIE_LC_STATUS1,4,2          ; @ixPCIE_LC_STATUS1
	.comm	_PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK,4,2 ; @PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK
	.comm	_PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK,4,2 ; @PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK
	.no_dead_strip	_cik_program_aspm
.subsections_via_symbols
