	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v10_0_kiq_set_interrupt_state
_gfx_v10_0_kiq_set_interrupt_state:     ## @gfx_v10_0_kiq_set_interrupt_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %r14d
	movl	%edx, %r12d
	movq	%rdi, %rbx
	cmpl	$1, (%rdi)
	movq	_GC@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	jne	LBB0_1
## %bb.2:
	movq	_mmCP_ME1_PIPE0_INT_CNTL@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_1:
	movq	_mmCP_ME2_PIPE0_INT_CNTL@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	cmpl	$128, %r12d
	jne	LBB0_8
## %bb.4:
	movl	%eax, %r15d
	addl	8(%rbx), %r15d
	movq	_AMDGPU_IRQ_STATE_DISABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	(%r13), %edi
	movq	_mmCPC_INT_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	%eax, %edi
	movq	_CPC_INT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_GENERIC2_INT_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	cmpl	%r14d, %r12d
	movq	%rax, %r14
	jne	LBB0_7
## %bb.5:
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%r13), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	%r15d, %edi
	callq	_RREG32
	movq	_CP_ME2_PIPE0_INT_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	(%r14), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	jmp	LBB0_6
LBB0_8:
	xorl	%eax, %eax
	callq	_BUG
	jmp	LBB0_9
LBB0_7:
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r13), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	%r15d, %edi
	callq	_RREG32
	movq	_CP_ME2_PIPE0_INT_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	(%r14), %edx
	movl	%eax, %edi
	movl	$1, %ecx
LBB0_6:
	callq	_REG_SET_FIELD
	movl	%r15d, %edi
	movl	%eax, %esi
	callq	_WREG32
LBB0_9:
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_GC,4,2                         ## @GC
	.comm	_mmCP_ME1_PIPE0_INT_CNTL,4,2    ## @mmCP_ME1_PIPE0_INT_CNTL
	.comm	_mmCP_ME2_PIPE0_INT_CNTL,4,2    ## @mmCP_ME2_PIPE0_INT_CNTL
	.comm	_AMDGPU_IRQ_STATE_DISABLE,4,2   ## @AMDGPU_IRQ_STATE_DISABLE
	.comm	_mmCPC_INT_CNTL,4,2             ## @mmCPC_INT_CNTL
	.comm	_CPC_INT_CNTL,4,2               ## @CPC_INT_CNTL
	.comm	_GENERIC2_INT_ENABLE,4,2        ## @GENERIC2_INT_ENABLE
	.comm	_CP_ME2_PIPE0_INT_CNTL,4,2      ## @CP_ME2_PIPE0_INT_CNTL
	.no_dead_strip	_gfx_v10_0_kiq_set_interrupt_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v10_0_kiq_set_interrupt_state
_gfx_v10_0_kiq_set_interrupt_state:     ; @gfx_v10_0_kiq_set_interrupt_state
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x3
	mov	x21, x2
	mov	x19, x0
	ldr	w8, [x0]
Lloh0:
	adrp	x22, _GC@GOTPAGE
Lloh1:
	ldr	x22, [x22, _GC@GOTPAGEOFF]
Lloh2:
	adrp	x9, _mmCP_ME1_PIPE0_INT_CNTL@GOTPAGE
Lloh3:
	ldr	x9, [x9, _mmCP_ME1_PIPE0_INT_CNTL@GOTPAGEOFF]
	ldr	w0, [x22]
Lloh4:
	adrp	x10, _mmCP_ME2_PIPE0_INT_CNTL@GOTPAGE
Lloh5:
	ldr	x10, [x10, _mmCP_ME2_PIPE0_INT_CNTL@GOTPAGEOFF]
	cmp	w8, #1
	csel	x8, x9, x10, eq
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	cmp	w21, #128
	b.ne	LBB0_3
; %bb.1:
	ldr	w8, [x19, #8]
Lloh6:
	adrp	x9, _AMDGPU_IRQ_STATE_DISABLE@GOTPAGE
Lloh7:
	ldr	x9, [x9, _AMDGPU_IRQ_STATE_DISABLE@GOTPAGEOFF]
	add	w19, w0, w8
Lloh8:
	ldr	w24, [x9]
	ldr	w0, [x22]
Lloh9:
	adrp	x23, _mmCPC_INT_CNTL@GOTPAGE
Lloh10:
	ldr	x23, [x23, _mmCPC_INT_CNTL@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh11:
	adrp	x8, _CPC_INT_CNTL@GOTPAGE
Lloh12:
	ldr	x8, [x8, _CPC_INT_CNTL@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
Lloh14:
	adrp	x21, _GENERIC2_INT_ENABLE@GOTPAGE
Lloh15:
	ldr	x21, [x21, _GENERIC2_INT_ENABLE@GOTPAGEOFF]
	ldr	w2, [x21]
	cmp	w24, w20
	b.ne	LBB0_4
; %bb.2:
	mov	w3, #0
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x22]
	ldr	w2, [x23]
	mov	w1, #0
	bl	_WREG32_SOC15
	mov	x0, x19
	bl	_RREG32
Lloh16:
	adrp	x8, _CP_ME2_PIPE0_INT_CNTL@GOTPAGE
Lloh17:
	ldr	x8, [x8, _CP_ME2_PIPE0_INT_CNTL@GOTPAGEOFF]
Lloh18:
	ldr	w1, [x8]
	ldr	w2, [x21]
	mov	w3, #0
	b	LBB0_5
LBB0_3:
	bl	_BUG
	b	LBB0_6
LBB0_4:
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x22]
	ldr	w2, [x23]
	mov	w1, #0
	bl	_WREG32_SOC15
	mov	x0, x19
	bl	_RREG32
Lloh19:
	adrp	x8, _CP_ME2_PIPE0_INT_CNTL@GOTPAGE
Lloh20:
	ldr	x8, [x8, _CP_ME2_PIPE0_INT_CNTL@GOTPAGEOFF]
Lloh21:
	ldr	w1, [x8]
	ldr	w2, [x21]
	mov	w3, #1
LBB0_5:
	bl	_REG_SET_FIELD
	mov	x1, x0
	mov	x0, x19
	bl	_WREG32
LBB0_6:
	mov	w0, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.cfi_endproc
                                        ; -- End function
	.comm	_GC,4,2                         ; @GC
	.comm	_mmCP_ME1_PIPE0_INT_CNTL,4,2    ; @mmCP_ME1_PIPE0_INT_CNTL
	.comm	_mmCP_ME2_PIPE0_INT_CNTL,4,2    ; @mmCP_ME2_PIPE0_INT_CNTL
	.comm	_AMDGPU_IRQ_STATE_DISABLE,4,2   ; @AMDGPU_IRQ_STATE_DISABLE
	.comm	_mmCPC_INT_CNTL,4,2             ; @mmCPC_INT_CNTL
	.comm	_CPC_INT_CNTL,4,2               ; @CPC_INT_CNTL
	.comm	_GENERIC2_INT_ENABLE,4,2        ; @GENERIC2_INT_ENABLE
	.comm	_CP_ME2_PIPE0_INT_CNTL,4,2      ; @CP_ME2_PIPE0_INT_CNTL
	.no_dead_strip	_gfx_v10_0_kiq_set_interrupt_state
.subsections_via_symbols
