	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_sor_power_down
_tegra_sor_power_down:                  ## @tegra_sor_power_down
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_SOR_PWR@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	callq	_tegra_sor_readl
	movq	_SOR_PWR_NORMAL_STATE_PU@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rbx
	notq	%rbx
	andq	%rax, %rbx
	movq	_SOR_PWR_TRIGGER@GOTPCREL(%rip), %r12
	orq	(%r12), %rbx
	movl	(%r13), %edx
	movq	%r14, -48(%rbp)                 ## 8-byte Spill
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	_tegra_sor_writel
	movq	_jiffies@GOTPCREL(%rip), %rax
	movq	(%rax), %r14
	movl	$250, %edi
	callq	_msecs_to_jiffies
	movq	%rax, %r15
	addq	%r14, %r15
	movq	_jiffies@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movq	%r15, %rsi
	callq	_time_before
	testq	%rax, %rax
	je	LBB0_4
## %bb.1:
	movq	-48(%rbp), %r14                 ## 8-byte Reload
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r13), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	testq	%rax, (%r12)
	je	LBB0_14
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	%rax, %rbx
	movl	$25, %edi
	movl	$100, %esi
	callq	_usleep_range
	movq	_jiffies@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movq	%r15, %rsi
	callq	_time_before
	testq	%rax, %rax
	jne	LBB0_2
LBB0_4:
	testq	%rbx, (%r12)
	je	LBB0_6
LBB0_5:
	movq	_ETIMEDOUT@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
	jmp	LBB0_15
LBB0_6:
	movq	-48(%rbp), %r14                 ## 8-byte Reload
	movl	12(%r14), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_set_parent_clock
	testl	%eax, %eax
	js	LBB0_7
## %bb.8:
	movq	(%r14), %rax
	movq	(%rax), %rax
	movl	8(%rax), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_DP_PADCTL_PD_TXD_3@GOTPCREL(%rip), %rcx
	movq	_SOR_DP_PADCTL_PD_TXD_0@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rsi
	orq	(%rcx), %rsi
	movq	_SOR_DP_PADCTL_PD_TXD_1@GOTPCREL(%rip), %rcx
	orq	(%rcx), %rsi
	movq	_SOR_DP_PADCTL_PD_TXD_2@GOTPCREL(%rip), %rcx
	orq	(%rcx), %rsi
	notq	%rsi
	andq	%rax, %rsi
	movq	(%r14), %rax
	movq	(%rax), %rax
	movl	8(%rax), %edx
	movq	%r14, %rdi
	callq	_tegra_sor_writel
	movq	_SOR_LANE_SEQ_CTL_TRIGGER@GOTPCREL(%rip), %r13
	movq	_SOR_LANE_SEQ_CTL_SEQUENCE_UP@GOTPCREL(%rip), %rax
	movq	(%rax), %rbx
	orq	(%r13), %rbx
	movq	_SOR_LANE_SEQ_CTL_POWER_STATE_DOWN@GOTPCREL(%rip), %rax
	orq	(%rax), %rbx
	movq	_SOR_LANE_SEQ_CTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	_tegra_sor_writel
	movq	_jiffies@GOTPCREL(%rip), %rax
	movq	(%rax), %r14
	movl	$250, %edi
	callq	_msecs_to_jiffies
	movq	%rax, %r15
	addq	%r14, %r15
	movq	-48(%rbp), %r14                 ## 8-byte Reload
	.p2align	4, 0x90
LBB0_9:                                 ## =>This Inner Loop Header: Depth=1
	movq	_jiffies@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movq	%r15, %rsi
	callq	_time_before
	testq	%rax, %rax
	je	LBB0_12
## %bb.10:                              ##   in Loop: Header=BB0_9 Depth=1
	movl	(%r12), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	%rax, %rbx
	testq	%rax, (%r13)
	je	LBB0_12
## %bb.11:                              ##   in Loop: Header=BB0_9 Depth=1
	movl	$25, %edi
	movl	$100, %esi
	callq	_usleep_range
	jmp	LBB0_9
LBB0_12:
	testq	%rbx, (%r13)
	jne	LBB0_5
## %bb.13:
	movq	(%r14), %rax
	movq	(%rax), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_PLL2_PORT_POWERDOWN@GOTPCREL(%rip), %rcx
	orq	(%rcx), %rax
	movq	(%r14), %rcx
	movq	(%rcx), %rcx
	movl	(%rcx), %edx
	movq	%r14, %rdi
	movq	%rax, %rsi
	callq	_tegra_sor_writel
	movl	$20, %edi
	movl	$100, %esi
	callq	_usleep_range
	movq	(%r14), %rax
	movq	(%rax), %rax
	movl	4(%rax), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_PLL0_VCOPD@GOTPCREL(%rip), %rcx
	movq	_SOR_PLL0_PWR@GOTPCREL(%rip), %rdx
	orq	(%rcx), %rax
	orq	(%rdx), %rax
	movq	(%r14), %rcx
	movq	(%rcx), %rcx
	movl	4(%rcx), %edx
	movq	%r14, %rdi
	movq	%rax, %rsi
	callq	_tegra_sor_writel
	movq	(%r14), %rax
	movq	(%rax), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_PLL2_SEQ_PLLCAPPD@GOTPCREL(%rip), %rcx
	orq	(%rcx), %rax
	movq	_SOR_PLL2_SEQ_PLLCAPPD_ENFORCE@GOTPCREL(%rip), %rcx
	orq	(%rcx), %rax
	movq	(%r14), %rcx
	movq	(%rcx), %rcx
	movl	(%rcx), %edx
	movq	%r14, %rdi
	movq	%rax, %rsi
	callq	_tegra_sor_writel
	movl	$20, %edi
	movl	$100, %esi
	callq	_usleep_range
LBB0_14:
	xorl	%ebx, %ebx
LBB0_15:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_7:
	movl	%eax, %ebx
	movl	8(%r14), %edi
	leaq	L_.str(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
	jmp	LBB0_15
	.cfi_endproc
                                        ## -- End function
	.comm	_SOR_PWR,4,2                    ## @SOR_PWR
	.comm	_SOR_PWR_NORMAL_STATE_PU,8,3    ## @SOR_PWR_NORMAL_STATE_PU
	.comm	_SOR_PWR_TRIGGER,8,3            ## @SOR_PWR_TRIGGER
	.comm	_jiffies,8,3                    ## @jiffies
	.comm	_ETIMEDOUT,4,2                  ## @ETIMEDOUT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"failed to set safe parent clock: %d\n"

	.comm	_SOR_DP_PADCTL_PD_TXD_3,8,3     ## @SOR_DP_PADCTL_PD_TXD_3
	.comm	_SOR_DP_PADCTL_PD_TXD_0,8,3     ## @SOR_DP_PADCTL_PD_TXD_0
	.comm	_SOR_DP_PADCTL_PD_TXD_1,8,3     ## @SOR_DP_PADCTL_PD_TXD_1
	.comm	_SOR_DP_PADCTL_PD_TXD_2,8,3     ## @SOR_DP_PADCTL_PD_TXD_2
	.comm	_SOR_LANE_SEQ_CTL_TRIGGER,8,3   ## @SOR_LANE_SEQ_CTL_TRIGGER
	.comm	_SOR_LANE_SEQ_CTL_SEQUENCE_UP,8,3 ## @SOR_LANE_SEQ_CTL_SEQUENCE_UP
	.comm	_SOR_LANE_SEQ_CTL_POWER_STATE_DOWN,8,3 ## @SOR_LANE_SEQ_CTL_POWER_STATE_DOWN
	.comm	_SOR_LANE_SEQ_CTL,4,2           ## @SOR_LANE_SEQ_CTL
	.comm	_SOR_PLL2_PORT_POWERDOWN,8,3    ## @SOR_PLL2_PORT_POWERDOWN
	.comm	_SOR_PLL0_VCOPD,8,3             ## @SOR_PLL0_VCOPD
	.comm	_SOR_PLL0_PWR,8,3               ## @SOR_PLL0_PWR
	.comm	_SOR_PLL2_SEQ_PLLCAPPD,8,3      ## @SOR_PLL2_SEQ_PLLCAPPD
	.comm	_SOR_PLL2_SEQ_PLLCAPPD_ENFORCE,8,3 ## @SOR_PLL2_SEQ_PLLCAPPD_ENFORCE
	.no_dead_strip	_tegra_sor_power_down
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_sor_power_down
_tegra_sor_power_down:                  ; @tegra_sor_power_down
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x23, _SOR_PWR@GOTPAGE
Lloh1:
	ldr	x23, [x23, _SOR_PWR@GOTPAGEOFF]
	ldr	w1, [x23]
	bl	_tegra_sor_readl
Lloh2:
	adrp	x8, _SOR_PWR_NORMAL_STATE_PU@GOTPAGE
Lloh3:
	ldr	x8, [x8, _SOR_PWR_NORMAL_STATE_PU@GOTPAGEOFF]
Lloh4:
	ldr	x8, [x8]
	bic	x8, x0, x8
Lloh5:
	adrp	x24, _SOR_PWR_TRIGGER@GOTPAGE
Lloh6:
	ldr	x24, [x24, _SOR_PWR_TRIGGER@GOTPAGEOFF]
	ldr	x9, [x24]
	orr	x20, x8, x9
	ldr	w2, [x23]
	mov	x0, x19
	mov	x1, x20
	bl	_tegra_sor_writel
Lloh7:
	adrp	x22, _jiffies@GOTPAGE
Lloh8:
	ldr	x22, [x22, _jiffies@GOTPAGEOFF]
	ldr	x21, [x22]
	mov	w0, #250
	bl	_msecs_to_jiffies
	add	x21, x0, x21
LBB0_1:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x0, [x22]
	mov	x1, x21
	bl	_time_before
	cbz	x0, LBB0_4
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	ldr	w1, [x23]
	mov	x0, x19
	bl	_tegra_sor_readl
	ldr	x8, [x24]
	tst	x8, x0
	b.eq	LBB0_13
; %bb.3:                                ;   in Loop: Header=BB0_1 Depth=1
	mov	x20, x0
	mov	w0, #25
	mov	w1, #100
	bl	_usleep_range
	b	LBB0_1
LBB0_4:
	ldr	x8, [x24]
	tst	x8, x20
	b.eq	LBB0_6
LBB0_5:
Lloh9:
	adrp	x8, _ETIMEDOUT@GOTPAGE
Lloh10:
	ldr	x8, [x8, _ETIMEDOUT@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	neg	w20, w8
	b	LBB0_14
LBB0_6:
	ldr	w1, [x19, #12]
	mov	x0, x19
	bl	_tegra_sor_set_parent_clock
	tbnz	w0, #31, LBB0_15
; %bb.7:
	ldr	x8, [x19]
	ldr	x8, [x8]
	ldr	w1, [x8, #8]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh12:
	adrp	x8, _SOR_DP_PADCTL_PD_TXD_3@GOTPAGE
Lloh13:
	ldr	x8, [x8, _SOR_DP_PADCTL_PD_TXD_3@GOTPAGEOFF]
Lloh14:
	ldr	x8, [x8]
Lloh15:
	adrp	x9, _SOR_DP_PADCTL_PD_TXD_0@GOTPAGE
Lloh16:
	ldr	x9, [x9, _SOR_DP_PADCTL_PD_TXD_0@GOTPAGEOFF]
Lloh17:
	ldr	x9, [x9]
	orr	x8, x9, x8
Lloh18:
	adrp	x9, _SOR_DP_PADCTL_PD_TXD_1@GOTPAGE
Lloh19:
	ldr	x9, [x9, _SOR_DP_PADCTL_PD_TXD_1@GOTPAGEOFF]
Lloh20:
	ldr	x9, [x9]
	orr	x8, x8, x9
Lloh21:
	adrp	x9, _SOR_DP_PADCTL_PD_TXD_2@GOTPAGE
Lloh22:
	ldr	x9, [x9, _SOR_DP_PADCTL_PD_TXD_2@GOTPAGEOFF]
Lloh23:
	ldr	x9, [x9]
	orr	x8, x8, x9
	bic	x1, x0, x8
	ldr	x8, [x19]
	ldr	x8, [x8]
	ldr	w2, [x8, #8]
	mov	x0, x19
	bl	_tegra_sor_writel
Lloh24:
	adrp	x23, _SOR_LANE_SEQ_CTL_TRIGGER@GOTPAGE
Lloh25:
	ldr	x23, [x23, _SOR_LANE_SEQ_CTL_TRIGGER@GOTPAGEOFF]
	ldr	x8, [x23]
Lloh26:
	adrp	x9, _SOR_LANE_SEQ_CTL_SEQUENCE_UP@GOTPAGE
Lloh27:
	ldr	x9, [x9, _SOR_LANE_SEQ_CTL_SEQUENCE_UP@GOTPAGEOFF]
Lloh28:
	ldr	x9, [x9]
Lloh29:
	adrp	x10, _SOR_LANE_SEQ_CTL_POWER_STATE_DOWN@GOTPAGE
Lloh30:
	ldr	x10, [x10, _SOR_LANE_SEQ_CTL_POWER_STATE_DOWN@GOTPAGEOFF]
	orr	x8, x9, x8
Lloh31:
	ldr	x9, [x10]
	orr	x20, x8, x9
Lloh32:
	adrp	x24, _SOR_LANE_SEQ_CTL@GOTPAGE
Lloh33:
	ldr	x24, [x24, _SOR_LANE_SEQ_CTL@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	x0, x19
	mov	x1, x20
	bl	_tegra_sor_writel
	ldr	x21, [x22]
	mov	w0, #250
	bl	_msecs_to_jiffies
	add	x21, x0, x21
LBB0_8:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x0, [x22]
	mov	x1, x21
	bl	_time_before
	cbz	x0, LBB0_11
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=1
	ldr	w1, [x24]
	mov	x0, x19
	bl	_tegra_sor_readl
	mov	x20, x0
	ldr	x8, [x23]
	tst	x8, x0
	b.eq	LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_8 Depth=1
	mov	w0, #25
	mov	w1, #100
	bl	_usleep_range
	b	LBB0_8
LBB0_11:
	ldr	x8, [x23]
	tst	x8, x20
	b.ne	LBB0_5
; %bb.12:
	ldr	x8, [x19]
	ldr	x8, [x8]
	ldr	w1, [x8]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh34:
	adrp	x8, _SOR_PLL2_PORT_POWERDOWN@GOTPAGE
Lloh35:
	ldr	x8, [x8, _SOR_PLL2_PORT_POWERDOWN@GOTPAGEOFF]
Lloh36:
	ldr	x8, [x8]
	orr	x1, x8, x0
	ldr	x8, [x19]
	ldr	x8, [x8]
	ldr	w2, [x8]
	mov	x0, x19
	bl	_tegra_sor_writel
	mov	w0, #20
	mov	w1, #100
	bl	_usleep_range
	ldr	x8, [x19]
	ldr	x8, [x8]
	ldr	w1, [x8, #4]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh37:
	adrp	x8, _SOR_PLL0_VCOPD@GOTPAGE
Lloh38:
	ldr	x8, [x8, _SOR_PLL0_VCOPD@GOTPAGEOFF]
Lloh39:
	ldr	x8, [x8]
Lloh40:
	adrp	x9, _SOR_PLL0_PWR@GOTPAGE
Lloh41:
	ldr	x9, [x9, _SOR_PLL0_PWR@GOTPAGEOFF]
Lloh42:
	ldr	x9, [x9]
	orr	x8, x8, x0
	orr	x1, x8, x9
	ldr	x8, [x19]
	ldr	x8, [x8]
	ldr	w2, [x8, #4]
	mov	x0, x19
	bl	_tegra_sor_writel
	ldr	x8, [x19]
	ldr	x8, [x8]
	ldr	w1, [x8]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh43:
	adrp	x8, _SOR_PLL2_SEQ_PLLCAPPD@GOTPAGE
Lloh44:
	ldr	x8, [x8, _SOR_PLL2_SEQ_PLLCAPPD@GOTPAGEOFF]
Lloh45:
	ldr	x8, [x8]
Lloh46:
	adrp	x9, _SOR_PLL2_SEQ_PLLCAPPD_ENFORCE@GOTPAGE
Lloh47:
	ldr	x9, [x9, _SOR_PLL2_SEQ_PLLCAPPD_ENFORCE@GOTPAGEOFF]
	orr	x8, x8, x0
Lloh48:
	ldr	x9, [x9]
	orr	x1, x8, x9
	ldr	x8, [x19]
	ldr	x8, [x8]
	ldr	w2, [x8]
	mov	x0, x19
	bl	_tegra_sor_writel
	mov	w0, #20
	mov	w1, #100
	bl	_usleep_range
LBB0_13:
	mov	w20, #0
LBB0_14:
	mov	x0, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_15:
	mov	x20, x0
	ldr	w0, [x19, #8]
Lloh49:
	adrp	x1, l_.str@PAGE
Lloh50:
	add	x1, x1, l_.str@PAGEOFF
	mov	x2, x20
	bl	_dev_err
	b	LBB0_14
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpAdd	Lloh49, Lloh50
	.cfi_endproc
                                        ; -- End function
	.comm	_SOR_PWR,4,2                    ; @SOR_PWR
	.comm	_SOR_PWR_NORMAL_STATE_PU,8,3    ; @SOR_PWR_NORMAL_STATE_PU
	.comm	_SOR_PWR_TRIGGER,8,3            ; @SOR_PWR_TRIGGER
	.comm	_jiffies,8,3                    ; @jiffies
	.comm	_ETIMEDOUT,4,2                  ; @ETIMEDOUT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"failed to set safe parent clock: %d\n"

	.comm	_SOR_DP_PADCTL_PD_TXD_3,8,3     ; @SOR_DP_PADCTL_PD_TXD_3
	.comm	_SOR_DP_PADCTL_PD_TXD_0,8,3     ; @SOR_DP_PADCTL_PD_TXD_0
	.comm	_SOR_DP_PADCTL_PD_TXD_1,8,3     ; @SOR_DP_PADCTL_PD_TXD_1
	.comm	_SOR_DP_PADCTL_PD_TXD_2,8,3     ; @SOR_DP_PADCTL_PD_TXD_2
	.comm	_SOR_LANE_SEQ_CTL_TRIGGER,8,3   ; @SOR_LANE_SEQ_CTL_TRIGGER
	.comm	_SOR_LANE_SEQ_CTL_SEQUENCE_UP,8,3 ; @SOR_LANE_SEQ_CTL_SEQUENCE_UP
	.comm	_SOR_LANE_SEQ_CTL_POWER_STATE_DOWN,8,3 ; @SOR_LANE_SEQ_CTL_POWER_STATE_DOWN
	.comm	_SOR_LANE_SEQ_CTL,4,2           ; @SOR_LANE_SEQ_CTL
	.comm	_SOR_PLL2_PORT_POWERDOWN,8,3    ; @SOR_PLL2_PORT_POWERDOWN
	.comm	_SOR_PLL0_VCOPD,8,3             ; @SOR_PLL0_VCOPD
	.comm	_SOR_PLL0_PWR,8,3               ; @SOR_PLL0_PWR
	.comm	_SOR_PLL2_SEQ_PLLCAPPD,8,3      ; @SOR_PLL2_SEQ_PLLCAPPD
	.comm	_SOR_PLL2_SEQ_PLLCAPPD_ENFORCE,8,3 ; @SOR_PLL2_SEQ_PLLCAPPD_ENFORCE
	.no_dead_strip	_tegra_sor_power_down
.subsections_via_symbols
