	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function sync_point_perfmon_sample_post
_sync_point_perfmon_sample_post:        ## @sync_point_perfmon_sample_post
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %r14
	movq	(%rsi), %rbx
	movq	_ETNA_PM_PROCESS_POST@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_sync_point_perfmon_sample
	cmpl	$0, (%rbx)
	je	LBB0_3
## %bb.1:
	movq	8(%rbx), %rax
	addq	$8, %rax
	xorl	%ecx, %ecx
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movl	-8(%rax), %edx
	movq	(%rax), %rsi
	movl	%edx, (%rsi)
	incq	%rcx
	movl	(%rbx), %edx
	addq	$16, %rax
	cmpq	%rdx, %rcx
	jb	LBB0_2
LBB0_3:
	movq	_VIVS_HI_CLOCK_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_gpu_read
	movq	_VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %esi
	movq	%r14, %rdi
	movl	%eax, %edx
	callq	_gpu_write
	movq	_VIVS_PM_POWER_CONTROLS@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_gpu_read
	movq	_VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %esi
	movq	%r14, %rdi
	movl	%eax, %edx
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_gpu_write                      ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_ETNA_PM_PROCESS_POST,4,2       ## @ETNA_PM_PROCESS_POST
	.comm	_VIVS_HI_CLOCK_CONTROL,4,2      ## @VIVS_HI_CLOCK_CONTROL
	.comm	_VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS,4,2 ## @VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS
	.comm	_VIVS_PM_POWER_CONTROLS,4,2     ## @VIVS_PM_POWER_CONTROLS
	.comm	_VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING,4,2 ## @VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING
	.no_dead_strip	_sync_point_perfmon_sample_post
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function sync_point_perfmon_sample_post
_sync_point_perfmon_sample_post:        ; @sync_point_perfmon_sample_post
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	x20, [x1]
Lloh0:
	adrp	x8, _ETNA_PM_PROCESS_POST@GOTPAGE
Lloh1:
	ldr	x8, [x8, _ETNA_PM_PROCESS_POST@GOTPAGEOFF]
Lloh2:
	ldr	w2, [x8]
	bl	_sync_point_perfmon_sample
	ldr	w8, [x20]
	cbz	w8, LBB0_3
; %bb.1:
	mov	x8, #0
	ldr	x9, [x20, #8]
	add	x9, x9, #8
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldur	w10, [x9, #-8]
	ldr	x11, [x9], #16
	str	w10, [x11]
	add	x8, x8, #1
	ldr	w10, [x20]
	cmp	x8, x10
	b.lo	LBB0_2
LBB0_3:
Lloh3:
	adrp	x20, _VIVS_HI_CLOCK_CONTROL@GOTPAGE
Lloh4:
	ldr	x20, [x20, _VIVS_HI_CLOCK_CONTROL@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_gpu_read
Lloh5:
	adrp	x8, _VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS@GOTPAGE
Lloh6:
	ldr	x8, [x8, _VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	orr	w2, w8, w0
	ldr	w1, [x20]
	mov	x0, x19
	bl	_gpu_write
Lloh8:
	adrp	x20, _VIVS_PM_POWER_CONTROLS@GOTPAGE
Lloh9:
	ldr	x20, [x20, _VIVS_PM_POWER_CONTROLS@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_gpu_read
Lloh10:
	adrp	x8, _VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING@GOTPAGE
Lloh11:
	ldr	x8, [x8, _VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	orr	w2, w8, w0
	ldr	w1, [x20]
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_gpu_write
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_ETNA_PM_PROCESS_POST,4,2       ; @ETNA_PM_PROCESS_POST
	.comm	_VIVS_HI_CLOCK_CONTROL,4,2      ; @VIVS_HI_CLOCK_CONTROL
	.comm	_VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS,4,2 ; @VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS
	.comm	_VIVS_PM_POWER_CONTROLS,4,2     ; @VIVS_PM_POWER_CONTROLS
	.comm	_VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING,4,2 ; @VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING
	.no_dead_strip	_sync_point_perfmon_sample_post
.subsections_via_symbols
