	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_gem_va_ioctl            ## -- Begin function amdgpu_gem_va_ioctl
	.p2align	4, 0x90
_amdgpu_gem_va_ioctl:                   ## @amdgpu_gem_va_ioctl
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$72, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r15
	movl	16(%rsi), %edx
	movq	_AMDGPU_VA_RESERVED_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	cmpl	%ecx, %edx
	jge	LBB0_2
## %bb.1:
	movq	(%rdi), %rdi
	leaq	L_.str(%rip), %rsi
	xorl	%r13d, %r13d
	xorl	%eax, %eax
	callq	_dev_dbg
	jmp	LBB0_19
LBB0_2:
	movq	%rsi, %r12
	movq	_AMDGPU_VM_DELAY_UPDATE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_AMDGPU_VM_PAGE_READABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	%eax, %esi
	movq	_AMDGPU_VM_PAGE_WRITEABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_AMDGPU_VM_PAGE_EXECUTABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_AMDGPU_VM_MTYPE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_AMDGPU_VM_PAGE_PRT@GOTPCREL(%rip), %r13
	orl	(%r13), %eax
	movq	8(%rdi), %r9
	movq	(%r15), %r10
	movq	_AMDGPU_GMC_HOLE_START@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	cmpl	%ecx, %edx
	jl	LBB0_5
## %bb.3:
	movq	_AMDGPU_GMC_HOLE_END@GOTPCREL(%rip), %rbx
	movl	(%rbx), %r8d
	cmpl	%r8d, %edx
	jge	LBB0_5
## %bb.4:
	movq	(%rdi), %rdi
	leaq	L_.str.1(%rip), %rsi
	xorl	%r13d, %r13d
	xorl	%eax, %eax
	callq	_dev_dbg
	jmp	LBB0_19
LBB0_5:
	movq	_AMDGPU_GMC_HOLE_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %edx
	movl	%edx, 16(%r12)
	movl	(%r12), %edx
	notl	%esi
	testl	%esi, %edx
	je	LBB0_8
## %bb.6:
	notl	%eax
	testl	%eax, %edx
	je	LBB0_8
## %bb.7:
	movq	(%rdi), %rdi
	leaq	L_.str.2(%rip), %rsi
	jmp	LBB0_18
LBB0_8:
	movl	4(%r12), %edx
	movl	%edx, %eax
	andl	$-4, %eax
	cmpl	$128, %eax
	jne	LBB0_17
## %bb.9:
	movq	%r10, -56(%rbp)                 ## 8-byte Spill
	movq	%r9, -64(%rbp)                  ## 8-byte Spill
	leaq	-48(%rbp), %rdi
	callq	_INIT_LIST_HEAD
	leaq	-72(%rbp), %rdi
	callq	_INIT_LIST_HEAD
	xorl	%ebx, %ebx
	cmpl	$131, 4(%r12)
	movl	$0, %r14d
	je	LBB0_13
## %bb.10:
	movl	(%r13), %eax
	xorl	%ebx, %ebx
	movl	$0, %r14d
	testl	%eax, (%r12)
	jne	LBB0_13
## %bb.11:
	movl	20(%r12), %esi
	movq	%r15, %rdi
	callq	_drm_gem_object_lookup
	testq	%rax, %rax
	je	LBB0_25
## %bb.12:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	_gem_to_amdgpu_bo
	movq	%rax, %r14
	addq	$4, %rax
	movq	%rax, -96(%rbp)
	movq	_AMDGPU_GEM_CREATE_VM_ALWAYS_VALID@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	xorl	%ecx, %ecx
	andl	(%r14), %eax
	setne	%cl
	movl	%ecx, -104(%rbp)
	leaq	-100(%rbp), %rdi
	leaq	-48(%rbp), %rsi
	callq	_list_add
LBB0_13:
	movq	%rbx, %r15
	leaq	-48(%rbp), %rbx
	leaq	-88(%rbp), %rdx
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	movq	%rbx, %rsi
	callq	_amdgpu_vm_get_pd_bo
	leaq	-80(%rbp), %rdi
	leaq	-72(%rbp), %rcx
	movq	%rbx, %rsi
	movl	$1, %edx
	xorl	%r8d, %r8d
	callq	_ttm_eu_reserve_buffers
	movl	%eax, %r13d
	testl	%eax, %eax
	jne	LBB0_38
## %bb.14:
	testq	%r14, %r14
	je	LBB0_22
## %bb.15:
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	movq	%r14, %rsi
	callq	_amdgpu_vm_bo_find
	testq	%rax, %rax
	je	LBB0_24
## %bb.16:
	movq	%rax, %r13
	movl	4(%r12), %eax
	jmp	LBB0_27
LBB0_17:
	movq	(%rdi), %rdi
	leaq	L_.str.3(%rip), %rsi
LBB0_18:
	xorl	%r13d, %r13d
	xorl	%eax, %eax
	callq	_dev_dbg
LBB0_19:
	movq	_EINVAL@GOTPCREL(%rip), %rax
LBB0_20:
	subl	(%rax), %r13d
LBB0_21:
	movl	%r13d, %eax
	addq	$72, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_22:
	movl	4(%r12), %eax
	cmpl	$131, %eax
	jne	LBB0_26
## %bb.23:
	xorl	%r13d, %r13d
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	jmp	LBB0_30
LBB0_24:
	movq	_ENOENT@GOTPCREL(%rip), %rax
	xorl	%r13d, %r13d
	subl	(%rax), %r13d
	jmp	LBB0_37
LBB0_25:
	movq	_ENOENT@GOTPCREL(%rip), %rax
	xorl	%r13d, %r13d
	jmp	LBB0_20
LBB0_26:
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	movq	8(%rcx), %r13
LBB0_27:
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	addl	$-128, %eax
	cmpl	$3, %eax
	ja	LBB0_31
## %bb.28:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_29:
	movl	16(%r12), %edx
	movq	%rbx, %rdi
	movq	%r13, %r14
	movq	%r13, %rsi
	callq	_amdgpu_vm_bo_unmap
	jmp	LBB0_34
LBB0_30:
	movq	%r13, %r14
	movl	8(%r12), %ecx
	movl	16(%r12), %edx
	movq	%rbx, %rdi
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
	callq	_amdgpu_vm_bo_clear_mappings
	jmp	LBB0_34
LBB0_31:
	movq	%r13, %r14
	jmp	LBB0_35
LBB0_32:
	movl	(%r12), %esi
	movq	%rbx, %rdi
	callq	_amdgpu_gmc_get_pte_flags
	movl	16(%r12), %edx
	movl	8(%r12), %r8d
	movl	12(%r12), %ecx
	movq	%rbx, %rdi
	movq	%r13, %r14
	movq	%r13, %rsi
	movl	%eax, %r9d
	callq	_amdgpu_vm_bo_replace_map
	jmp	LBB0_34
LBB0_33:
	movl	(%r12), %esi
	movq	%rbx, %rdi
	callq	_amdgpu_gmc_get_pte_flags
	movl	16(%r12), %edx
	movl	8(%r12), %r8d
	movl	12(%r12), %ecx
	movq	%rbx, %rdi
	movq	%r13, %r14
	movq	%r13, %rsi
	movl	%eax, %r9d
	callq	_amdgpu_vm_bo_map
LBB0_34:
	movl	%eax, %r13d
	testl	%eax, %eax
	jne	LBB0_37
LBB0_35:
	movq	_AMDGPU_VM_DELAY_UPDATE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%r12), %eax
	movq	_amdgpu_vm_debug@GOTPCREL(%rip), %rcx
	xorl	%r13d, %r13d
	orl	(%rcx), %eax
	jne	LBB0_37
## %bb.36:
	movl	4(%r12), %ecx
	movq	%rbx, %rdi
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
	movq	%r14, %rdx
	callq	_amdgpu_gem_va_update_vm
LBB0_37:
	leaq	-80(%rbp), %rdi
	leaq	-48(%rbp), %rsi
	callq	_ttm_eu_backoff_reservation
LBB0_38:
	movq	%r15, %rdi
	callq	_drm_gem_object_put_unlocked
	jmp	LBB0_21
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_29, LBB0_29-LJTI0_0
.set L0_0_set_32, LBB0_32-LJTI0_0
.set L0_0_set_33, LBB0_33-LJTI0_0
.set L0_0_set_30, LBB0_30-LJTI0_0
LJTI0_0:
	.long	L0_0_set_29
	.long	L0_0_set_32
	.long	L0_0_set_33
	.long	L0_0_set_30
	.end_data_region
                                        ## -- End function
	.comm	_AMDGPU_VM_DELAY_UPDATE,4,2     ## @AMDGPU_VM_DELAY_UPDATE
	.comm	_AMDGPU_VM_PAGE_READABLE,4,2    ## @AMDGPU_VM_PAGE_READABLE
	.comm	_AMDGPU_VM_PAGE_WRITEABLE,4,2   ## @AMDGPU_VM_PAGE_WRITEABLE
	.comm	_AMDGPU_VM_PAGE_EXECUTABLE,4,2  ## @AMDGPU_VM_PAGE_EXECUTABLE
	.comm	_AMDGPU_VM_MTYPE_MASK,4,2       ## @AMDGPU_VM_MTYPE_MASK
	.comm	_AMDGPU_VM_PAGE_PRT,4,2         ## @AMDGPU_VM_PAGE_PRT
	.comm	_AMDGPU_VA_RESERVED_SIZE,4,2    ## @AMDGPU_VA_RESERVED_SIZE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"va_address 0x%LX is in reserved area 0x%LX\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_AMDGPU_GMC_HOLE_START,4,2      ## @AMDGPU_GMC_HOLE_START
	.comm	_AMDGPU_GMC_HOLE_END,4,2        ## @AMDGPU_GMC_HOLE_END
L_.str.1:                               ## @.str.1
	.asciz	"va_address 0x%LX is in VA hole 0x%LX-0x%LX\n"

	.comm	_AMDGPU_GMC_HOLE_MASK,4,2       ## @AMDGPU_GMC_HOLE_MASK
L_.str.2:                               ## @.str.2
	.asciz	"invalid flags combination 0x%08X\n"

L_.str.3:                               ## @.str.3
	.asciz	"unsupported operation %d\n"

	.comm	_ENOENT,4,2                     ## @ENOENT
	.comm	_AMDGPU_GEM_CREATE_VM_ALWAYS_VALID,4,2 ## @AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
	.comm	_amdgpu_vm_debug,4,2            ## @amdgpu_vm_debug
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_gem_va_ioctl            ; -- Begin function amdgpu_gem_va_ioctl
	.p2align	2
_amdgpu_gem_va_ioctl:                   ; @amdgpu_gem_va_ioctl
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #144
	.cfi_def_cfa_offset 144
	stp	x26, x25, [sp, #64]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #80]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #96]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #112]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #128]            ; 16-byte Folded Spill
	add	x29, sp, #128
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x22, x2
	ldr	w2, [x1, #16]
Lloh0:
	adrp	x8, _AMDGPU_VA_RESERVED_SIZE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPU_VA_RESERVED_SIZE@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cmp	w2, w8
	b.ge	LBB0_2
; %bb.1:
	ldr	x0, [x0]
	str	x8, [sp]
Lloh3:
	adrp	x1, l_.str@PAGE
Lloh4:
	add	x1, x1, l_.str@PAGEOFF
	b	LBB0_16
LBB0_2:
	mov	x19, x1
Lloh5:
	adrp	x25, _AMDGPU_VM_DELAY_UPDATE@GOTPAGE
Lloh6:
	ldr	x25, [x25, _AMDGPU_VM_DELAY_UPDATE@GOTPAGEOFF]
	ldr	w8, [x25]
Lloh7:
	adrp	x9, _AMDGPU_VM_PAGE_READABLE@GOTPAGE
Lloh8:
	ldr	x9, [x9, _AMDGPU_VM_PAGE_READABLE@GOTPAGEOFF]
Lloh9:
	ldr	w9, [x9]
Lloh10:
	adrp	x10, _AMDGPU_VM_PAGE_WRITEABLE@GOTPAGE
Lloh11:
	ldr	x10, [x10, _AMDGPU_VM_PAGE_WRITEABLE@GOTPAGEOFF]
Lloh12:
	ldr	w10, [x10]
Lloh13:
	adrp	x11, _AMDGPU_VM_PAGE_EXECUTABLE@GOTPAGE
Lloh14:
	ldr	x11, [x11, _AMDGPU_VM_PAGE_EXECUTABLE@GOTPAGEOFF]
Lloh15:
	ldr	w11, [x11]
Lloh16:
	adrp	x12, _AMDGPU_VM_MTYPE_MASK@GOTPAGE
Lloh17:
	ldr	x12, [x12, _AMDGPU_VM_MTYPE_MASK@GOTPAGEOFF]
Lloh18:
	ldr	w12, [x12]
Lloh19:
	adrp	x23, _AMDGPU_VM_PAGE_PRT@GOTPAGE
Lloh20:
	ldr	x23, [x23, _AMDGPU_VM_PAGE_PRT@GOTPAGEOFF]
	ldr	w13, [x23]
	ldr	x20, [x0, #8]
	ldr	x21, [x22]
Lloh21:
	adrp	x14, _AMDGPU_GMC_HOLE_START@GOTPAGE
Lloh22:
	ldr	x14, [x14, _AMDGPU_GMC_HOLE_START@GOTPAGEOFF]
Lloh23:
	ldr	w14, [x14]
	cmp	w2, w14
	b.lt	LBB0_5
; %bb.3:
Lloh24:
	adrp	x15, _AMDGPU_GMC_HOLE_END@GOTPAGE
Lloh25:
	ldr	x15, [x15, _AMDGPU_GMC_HOLE_END@GOTPAGEOFF]
Lloh26:
	ldr	w15, [x15]
	cmp	w2, w15
	b.ge	LBB0_5
; %bb.4:
	ldr	x0, [x0]
	stp	x14, x15, [sp]
Lloh27:
	adrp	x1, l_.str.1@PAGE
Lloh28:
	add	x1, x1, l_.str.1@PAGEOFF
	b	LBB0_16
LBB0_5:
	orr	w9, w9, w8
	orr	w9, w9, w10
	orr	w9, w9, w11
	orr	w9, w9, w12
	orr	w8, w13, w8
Lloh29:
	adrp	x10, _AMDGPU_GMC_HOLE_MASK@GOTPAGE
Lloh30:
	ldr	x10, [x10, _AMDGPU_GMC_HOLE_MASK@GOTPAGEOFF]
Lloh31:
	ldr	w10, [x10]
	and	w10, w10, w2
	str	w10, [x19, #16]
	ldr	w2, [x19]
	bic	w9, w2, w9
	cmp	w9, #0
	bic	w8, w2, w8
	ccmp	w8, #0, #4, ne
	b.ne	LBB0_14
; %bb.6:
	ldr	w2, [x19, #4]
	and	w8, w2, #0xfffffffc
	cmp	w8, #128
	b.ne	LBB0_15
; %bb.7:
	add	x0, sp, #24
	bl	_INIT_LIST_HEAD
	add	x0, sp, #16
	bl	_INIT_LIST_HEAD
	ldr	w8, [x19, #4]
	cmp	w8, #131
	b.eq	LBB0_9
; %bb.8:
	ldr	w8, [x19]
	ldr	w9, [x23]
	tst	w9, w8
	b.eq	LBB0_19
LBB0_9:
	mov	x22, #0
	mov	x23, #0
LBB0_10:
	add	x1, sp, #24
	add	x2, sp, #56
	mov	x0, x21
	bl	_amdgpu_vm_get_pd_bo
	add	x0, sp, #32
	add	x1, sp, #24
	add	x3, sp, #16
	mov	w2, #1
	mov	w4, #0
	bl	_ttm_eu_reserve_buffers
	mov	x24, x0
	cbnz	w0, LBB0_37
; %bb.11:
	cbz	x23, LBB0_21
; %bb.12:
	mov	x0, x21
	mov	x1, x23
	bl	_amdgpu_vm_bo_find
	cbz	x0, LBB0_23
; %bb.13:
	mov	x23, x0
	ldr	w8, [x19, #4]
	b	LBB0_26
LBB0_14:
	ldr	x0, [x0]
Lloh32:
	adrp	x1, l_.str.2@PAGE
Lloh33:
	add	x1, x1, l_.str.2@PAGEOFF
	b	LBB0_16
LBB0_15:
	ldr	x0, [x0]
Lloh34:
	adrp	x1, l_.str.3@PAGE
Lloh35:
	add	x1, x1, l_.str.3@PAGEOFF
LBB0_16:
	bl	_dev_dbg
Lloh36:
	adrp	x8, _EINVAL@GOTPAGE
Lloh37:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
LBB0_17:
	ldr	w8, [x8]
	neg	w24, w8
LBB0_18:
	mov	x0, x24
	ldp	x29, x30, [sp, #128]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #112]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #96]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #80]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #64]             ; 16-byte Folded Reload
	add	sp, sp, #144
	ret
LBB0_19:
	ldr	w1, [x19, #20]
	mov	x0, x22
	bl	_drm_gem_object_lookup
	cbz	x0, LBB0_24
; %bb.20:
	mov	x22, x0
	bl	_gem_to_amdgpu_bo
	mov	x23, x0
	mov	x8, x0
	ldr	w9, [x8], #4
	str	x8, [sp, #48]
Lloh38:
	adrp	x8, _AMDGPU_GEM_CREATE_VM_ALWAYS_VALID@GOTPAGE
Lloh39:
	ldr	x8, [x8, _AMDGPU_GEM_CREATE_VM_ALWAYS_VALID@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
	tst	w8, w9
	cset	w8, ne
	str	w8, [sp, #40]
	add	x8, sp, #40
	orr	x0, x8, #0x4
	add	x1, sp, #24
	bl	_list_add
	b	LBB0_10
LBB0_21:
	ldr	w8, [x19, #4]
	cmp	w8, #131
	b.ne	LBB0_25
; %bb.22:
	mov	x23, #0
	b	LBB0_29
LBB0_23:
Lloh41:
	adrp	x8, _ENOENT@GOTPAGE
Lloh42:
	ldr	x8, [x8, _ENOENT@GOTPAGEOFF]
Lloh43:
	ldr	w8, [x8]
	neg	w24, w8
	b	LBB0_36
LBB0_24:
Lloh44:
	adrp	x8, _ENOENT@GOTPAGE
Lloh45:
	ldr	x8, [x8, _ENOENT@GOTPAGEOFF]
	b	LBB0_17
LBB0_25:
	ldr	x23, [x21, #8]
LBB0_26:
	sub	w8, w8, #128
	cmp	w8, #3
	b.hi	LBB0_33
; %bb.27:
Lloh46:
	adrp	x9, lJTI0_0@PAGE
Lloh47:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_28
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_28:
	ldr	w2, [x19, #16]
	mov	x0, x20
	mov	x1, x23
	bl	_amdgpu_vm_bo_unmap
	b	LBB0_32
LBB0_29:
	ldr	w2, [x19, #16]
	ldr	w3, [x19, #8]
	mov	x0, x20
	mov	x1, x21
	bl	_amdgpu_vm_bo_clear_mappings
	b	LBB0_32
LBB0_30:
	ldr	w1, [x19]
	mov	x0, x20
	bl	_amdgpu_gmc_get_pte_flags
	mov	x5, x0
	ldp	w3, w2, [x19, #12]
	ldr	w4, [x19, #8]
	mov	x0, x20
	mov	x1, x23
	bl	_amdgpu_vm_bo_replace_map
	b	LBB0_32
LBB0_31:
	ldr	w1, [x19]
	mov	x0, x20
	bl	_amdgpu_gmc_get_pte_flags
	mov	x5, x0
	ldp	w3, w2, [x19, #12]
	ldr	w4, [x19, #8]
	mov	x0, x20
	mov	x1, x23
	bl	_amdgpu_vm_bo_map
LBB0_32:
	mov	x24, x0
	cbnz	w0, LBB0_36
LBB0_33:
	ldr	w8, [x19]
	ldr	w9, [x25]
	and	w8, w9, w8
Lloh48:
	adrp	x9, _amdgpu_vm_debug@GOTPAGE
Lloh49:
	ldr	x9, [x9, _amdgpu_vm_debug@GOTPAGEOFF]
Lloh50:
	ldr	w9, [x9]
	orr	w8, w8, w9
	cbnz	w8, LBB0_35
; %bb.34:
	ldr	w3, [x19, #4]
	mov	x0, x20
	mov	x1, x21
	mov	x2, x23
	bl	_amdgpu_gem_va_update_vm
LBB0_35:
	mov	w24, #0
LBB0_36:
	add	x0, sp, #32
	add	x1, sp, #24
	bl	_ttm_eu_backoff_reservation
LBB0_37:
	mov	x0, x22
	bl	_drm_gem_object_put_unlocked
	b	LBB0_18
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpAdd	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpAdd	Lloh32, Lloh33
	.loh AdrpAdd	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpAdd	Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_28-LBB0_28)>>2
	.byte	(LBB0_30-LBB0_28)>>2
	.byte	(LBB0_31-LBB0_28)>>2
	.byte	(LBB0_29-LBB0_28)>>2
                                        ; -- End function
	.comm	_AMDGPU_VM_DELAY_UPDATE,4,2     ; @AMDGPU_VM_DELAY_UPDATE
	.comm	_AMDGPU_VM_PAGE_READABLE,4,2    ; @AMDGPU_VM_PAGE_READABLE
	.comm	_AMDGPU_VM_PAGE_WRITEABLE,4,2   ; @AMDGPU_VM_PAGE_WRITEABLE
	.comm	_AMDGPU_VM_PAGE_EXECUTABLE,4,2  ; @AMDGPU_VM_PAGE_EXECUTABLE
	.comm	_AMDGPU_VM_MTYPE_MASK,4,2       ; @AMDGPU_VM_MTYPE_MASK
	.comm	_AMDGPU_VM_PAGE_PRT,4,2         ; @AMDGPU_VM_PAGE_PRT
	.comm	_AMDGPU_VA_RESERVED_SIZE,4,2    ; @AMDGPU_VA_RESERVED_SIZE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"va_address 0x%LX is in reserved area 0x%LX\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_AMDGPU_GMC_HOLE_START,4,2      ; @AMDGPU_GMC_HOLE_START
	.comm	_AMDGPU_GMC_HOLE_END,4,2        ; @AMDGPU_GMC_HOLE_END
l_.str.1:                               ; @.str.1
	.asciz	"va_address 0x%LX is in VA hole 0x%LX-0x%LX\n"

	.comm	_AMDGPU_GMC_HOLE_MASK,4,2       ; @AMDGPU_GMC_HOLE_MASK
l_.str.2:                               ; @.str.2
	.asciz	"invalid flags combination 0x%08X\n"

l_.str.3:                               ; @.str.3
	.asciz	"unsupported operation %d\n"

	.comm	_ENOENT,4,2                     ; @ENOENT
	.comm	_AMDGPU_GEM_CREATE_VM_ALWAYS_VALID,4,2 ; @AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
	.comm	_amdgpu_vm_debug,4,2            ; @amdgpu_vm_debug
.subsections_via_symbols
