	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v8_0_init_microcode
_gfx_v8_0_init_microcode:               ## @gfx_v8_0_init_microcode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -48(%rbp)
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG
	movl	(%r15), %eax
	addl	$-128, %eax
	cmpl	$9, %eax
	jae	LBB0_35
## %bb.1:
	cltq
	leaq	l_switch.table.gfx_v8_0_init_microcode(%rip), %rcx
	movq	(%rcx,%rax,8), %r14
	leaq	L_.str.11(%rip), %rdx
	leaq	-80(%rbp), %r12
	movq	%r12, %rdi
	movl	$30, %esi
	movq	%r14, %rcx
	callq	_snprintf
	leaq	96(%r15), %rbx
	movl	160(%r15), %edx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	_request_firmware
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	LBB0_32
## %bb.2:
	movq	(%rbx), %rdi
	callq	_amdgpu_ucode_validate
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	LBB0_32
## %bb.3:
	movq	96(%r15), %rax
	movq	(%rax), %rbx
	movl	8(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 8(%r15)
	movl	(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 12(%r15)
	leaq	L_.str.13(%rip), %rdx
	leaq	-80(%rbp), %r12
	movq	%r12, %rdi
	movl	$30, %esi
	movq	%r14, %rcx
	callq	_snprintf
	leaq	88(%r15), %rbx
	movl	160(%r15), %edx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	_request_firmware
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	LBB0_32
## %bb.4:
	movq	(%rbx), %rdi
	callq	_amdgpu_ucode_validate
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	LBB0_32
## %bb.5:
	movq	88(%r15), %rax
	movq	(%rax), %rbx
	movl	8(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 16(%r15)
	movl	(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 20(%r15)
	leaq	L_.str.15(%rip), %rdx
	leaq	-80(%rbp), %r12
	movq	%r12, %rdi
	movl	$30, %esi
	movq	%r14, %rcx
	callq	_snprintf
	leaq	80(%r15), %rbx
	movl	160(%r15), %edx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	_request_firmware
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	LBB0_32
## %bb.6:
	movq	(%rbx), %rdi
	callq	_amdgpu_ucode_validate
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	LBB0_32
## %bb.7:
	movq	80(%r15), %rax
	movq	(%rax), %rbx
	movl	8(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 24(%r15)
	movl	(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 28(%r15)
	cmpl	$46, %eax
	jl	LBB0_10
## %bb.8:
	cmpl	$46, 12(%r15)
	jl	LBB0_10
## %bb.9:
	movl	$1, 184(%r15)
	leaq	L_.str.16(%rip), %rdi
	callq	_DRM_INFO
	jmp	LBB0_11
LBB0_10:
	movl	$0, 184(%r15)
LBB0_11:
	leaq	L_.str.17(%rip), %rdx
	leaq	-80(%rbp), %rbx
	movq	%rbx, %rdi
	movl	$30, %esi
	movq	%r14, %rcx
	callq	_snprintf
	leaq	72(%r15), %rdi
	movl	160(%r15), %edx
	movq	%rbx, %rsi
	callq	_request_firmware
	movl	%eax, %r12d
	testl	%eax, %eax
	je	LBB0_12
LBB0_32:
	movl	160(%r15), %edi
	leaq	L_.str.22(%rip), %rsi
	leaq	-80(%rbp), %rdx
	callq	_dev_err
	movq	96(%r15), %rdi
	callq	_release_firmware
	movq	$0, 96(%r15)
	movq	88(%r15), %rdi
	callq	_release_firmware
	movq	$0, 88(%r15)
	movq	80(%r15), %rdi
	callq	_release_firmware
	movq	$0, 80(%r15)
	movq	72(%r15), %rdi
	callq	_release_firmware
	movq	$0, 72(%r15)
	movq	64(%r15), %rdi
	callq	_release_firmware
	movq	$0, 64(%r15)
	movq	56(%r15), %rdi
	callq	_release_firmware
	movq	$0, 56(%r15)
LBB0_33:
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	cmpq	-48(%rbp), %rax
	jne	LBB0_38
## %bb.34:
	movl	%r12d, %eax
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_12:
	movq	72(%r15), %rdi
	callq	_amdgpu_ucode_validate
	movq	72(%r15), %rax
	movq	(%rax), %r12
	movl	48(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, 32(%r15)
	movl	(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, 36(%r15)
	movl	4(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, 104(%r15)
	movl	8(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, 108(%r15)
	movl	12(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, 112(%r15)
	movl	16(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, 116(%r15)
	movl	20(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, 120(%r15)
	movl	24(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, 124(%r15)
	movl	28(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, 128(%r15)
	movl	32(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, 132(%r15)
	movl	36(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, 136(%r15)
	addl	132(%r15), %eax
	movq	_GFP_KERNEL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_kmalloc
	movq	%rax, 144(%r15)
	testq	%rax, %rax
	je	LBB0_30
## %bb.13:
	movl	40(%r12), %edi
	callq	_le32_to_cpu
	cmpl	$4, 132(%r15)
	jae	LBB0_14
## %bb.36:
	movq	144(%r15), %rcx
	xorl	%ebx, %ebx
	jmp	LBB0_16
LBB0_30:
	movq	_ENOMEM@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	testl	%r12d, %r12d
	je	LBB0_37
## %bb.31:
	negl	%r12d
	jmp	LBB0_32
LBB0_14:
	movslq	%eax, %r13
	addq	%r12, %r13
	xorl	%ebx, %ebx
LBB0_15:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r13,%rbx,4), %edi
	callq	_le32_to_cpu
	movq	144(%r15), %rcx
	movl	%eax, (%rcx,%rbx,4)
	incq	%rbx
	movl	132(%r15), %eax
	sarl	$2, %eax
	cmpq	%rax, %rbx
	jb	LBB0_15
LBB0_16:
	leaq	(%rcx,%rbx,4), %rax
	movq	%rax, 152(%r15)
	movl	44(%r12), %edi
	callq	_le32_to_cpu
	cmpl	$4, 136(%r15)
	jb	LBB0_19
## %bb.17:
	cltq
	addq	%rax, %r12
	xorl	%ebx, %ebx
LBB0_18:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r12,%rbx,4), %edi
	callq	_le32_to_cpu
	movq	152(%r15), %rcx
	movl	%eax, (%rcx,%rbx,4)
	incq	%rbx
	movl	136(%r15), %eax
	sarl	$2, %eax
	cmpq	%rax, %rbx
	jb	LBB0_18
LBB0_19:
	leaq	L_.str.19(%rip), %rdx
	leaq	-80(%rbp), %r12
	movq	%r12, %rdi
	movl	$30, %esi
	movq	%r14, %rcx
	callq	_snprintf
	leaq	64(%r15), %rbx
	movl	160(%r15), %edx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	_request_firmware
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	LBB0_32
## %bb.20:
	movq	(%rbx), %rdi
	callq	_amdgpu_ucode_validate
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	LBB0_32
## %bb.21:
	movq	64(%r15), %rax
	movq	(%rax), %rbx
	movl	8(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 40(%r15)
	movl	(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 44(%r15)
	movl	(%r15), %eax
	orl	$2, %eax
	cmpl	$131, %eax
	je	LBB0_26
## %bb.22:
	leaq	L_.str.21(%rip), %rdx
	leaq	-80(%rbp), %r12
	movq	%r12, %rdi
	movl	$30, %esi
	movq	%r14, %rcx
	callq	_snprintf
	leaq	56(%r15), %rbx
	movl	160(%r15), %edx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	_request_firmware
	testl	%eax, %eax
	je	LBB0_23
## %bb.25:
	movq	$0, (%rbx)
LBB0_26:
	movq	176(%r15), %rax
	movq	_AMDGPU_UCODE_ID_CP_PFP@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	96(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movq	(%rcx), %rax
	movl	(%rax), %edi
	callq	_le32_to_cpu
	movq	_PAGE_SIZE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movl	%eax, %edi
	callq	_ALIGN
	addl	%eax, 168(%r15)
	movq	176(%r15), %rax
	movq	_AMDGPU_UCODE_ID_CP_ME@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	88(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movq	(%rcx), %rax
	movl	(%rax), %edi
	callq	_le32_to_cpu
	movl	(%rbx), %esi
	movl	%eax, %edi
	callq	_ALIGN
	addl	%eax, 168(%r15)
	movq	176(%r15), %rax
	movq	_AMDGPU_UCODE_ID_CP_CE@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	80(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movq	(%rcx), %rax
	movl	(%rax), %edi
	callq	_le32_to_cpu
	movl	(%rbx), %esi
	movl	%eax, %edi
	callq	_ALIGN
	addl	%eax, 168(%r15)
	movq	176(%r15), %rax
	movq	_AMDGPU_UCODE_ID_RLC_G@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	72(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movq	(%rcx), %rax
	movl	(%rax), %edi
	callq	_le32_to_cpu
	movl	(%rbx), %esi
	movl	%eax, %edi
	callq	_ALIGN
	addl	%eax, 168(%r15)
	movq	176(%r15), %rax
	movq	_AMDGPU_UCODE_ID_CP_MEC1@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	64(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movq	(%rcx), %rax
	movl	(%rax), %edi
	callq	_le32_to_cpu
	movl	(%rbx), %esi
	movl	%eax, %edi
	callq	_ALIGN
	addl	%eax, 168(%r15)
	movq	64(%r15), %rax
	movq	(%rax), %rax
	movl	4(%rax), %edi
	callq	_le32_to_cpu
                                        ## kill: def $eax killed $eax def $rax
	leal	(,%rax,4), %edi
	movl	(%rbx), %esi
	callq	_ALIGN
	addl	%eax, 168(%r15)
	movq	%r15, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_28
## %bb.27:
	movq	176(%r15), %rax
	movq	_AMDGPU_UCODE_ID_STORAGE@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	64(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movl	(%rbx), %edi
	shll	$6, %edi
	callq	_le32_to_cpu
	movl	(%rbx), %esi
	movl	%eax, %edi
	callq	_ALIGN
	addl	%eax, 168(%r15)
LBB0_28:
	movq	56(%r15), %rax
	xorl	%r12d, %r12d
	testq	%rax, %rax
	je	LBB0_33
## %bb.29:
	movq	176(%r15), %rcx
	movq	_AMDGPU_UCODE_ID_CP_MEC2@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdx
	movq	%rdx, %rsi
	shlq	$4, %rsi
	movq	%rdx, (%rcx,%rsi)
	movq	%rax, 8(%rcx,%rsi)
	movq	(%rax), %rax
	movl	(%rax), %edi
	callq	_le32_to_cpu
	movl	(%rbx), %esi
	movl	%eax, %edi
	callq	_ALIGN
	addl	%eax, 168(%r15)
	jmp	LBB0_33
LBB0_37:
	xorl	%r12d, %r12d
	jmp	LBB0_33
LBB0_23:
	movq	(%rbx), %rdi
	callq	_amdgpu_ucode_validate
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	LBB0_32
## %bb.24:
	movq	56(%r15), %rax
	movq	(%rax), %rbx
	movl	8(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 48(%r15)
	movl	(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 52(%r15)
	jmp	LBB0_26
LBB0_38:
	callq	___stack_chk_fail
LBB0_35:
	xorl	%eax, %eax
	callq	_BUG
	ud2
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"\n"

L_.str.1:                               ## @.str.1
	.asciz	"topaz"

L_.str.2:                               ## @.str.2
	.asciz	"tonga"

L_.str.3:                               ## @.str.3
	.asciz	"carrizo"

L_.str.4:                               ## @.str.4
	.asciz	"fiji"

L_.str.5:                               ## @.str.5
	.asciz	"stoney"

L_.str.6:                               ## @.str.6
	.asciz	"polaris10"

L_.str.7:                               ## @.str.7
	.asciz	"polaris11"

L_.str.8:                               ## @.str.8
	.asciz	"polaris12"

L_.str.9:                               ## @.str.9
	.asciz	"vegam"

	.comm	_ENOENT,4,2                     ## @ENOENT
L_.str.11:                              ## @.str.11
	.asciz	"amdgpu/%s_pfp.bin"

L_.str.13:                              ## @.str.13
	.asciz	"amdgpu/%s_me.bin"

L_.str.15:                              ## @.str.15
	.asciz	"amdgpu/%s_ce.bin"

L_.str.16:                              ## @.str.16
	.asciz	"Chained IB support enabled!\n"

L_.str.17:                              ## @.str.17
	.asciz	"amdgpu/%s_rlc.bin"

	.comm	_GFP_KERNEL,4,2                 ## @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ## @ENOMEM
L_.str.19:                              ## @.str.19
	.asciz	"amdgpu/%s_mec.bin"

L_.str.21:                              ## @.str.21
	.asciz	"amdgpu/%s_mec2.bin"

	.comm	_AMDGPU_UCODE_ID_CP_PFP,8,3     ## @AMDGPU_UCODE_ID_CP_PFP
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
	.comm	_AMDGPU_UCODE_ID_CP_ME,8,3      ## @AMDGPU_UCODE_ID_CP_ME
	.comm	_AMDGPU_UCODE_ID_CP_CE,8,3      ## @AMDGPU_UCODE_ID_CP_CE
	.comm	_AMDGPU_UCODE_ID_RLC_G,8,3      ## @AMDGPU_UCODE_ID_RLC_G
	.comm	_AMDGPU_UCODE_ID_CP_MEC1,8,3    ## @AMDGPU_UCODE_ID_CP_MEC1
	.comm	_AMDGPU_UCODE_ID_STORAGE,8,3    ## @AMDGPU_UCODE_ID_STORAGE
	.comm	_AMDGPU_UCODE_ID_CP_MEC2,8,3    ## @AMDGPU_UCODE_ID_CP_MEC2
L_.str.22:                              ## @.str.22
	.asciz	"gfx8: Failed to load firmware \"%s\"\n"

	.no_dead_strip	_gfx_v8_0_init_microcode
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.gfx_v8_0_init_microcode
l_switch.table.gfx_v8_0_init_microcode:
	.quad	L_.str.9
	.quad	L_.str.1
	.quad	L_.str.2
	.quad	L_.str.5
	.quad	L_.str.8
	.quad	L_.str.7
	.quad	L_.str.6
	.quad	L_.str.4
	.quad	L_.str.3

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v8_0_init_microcode
_gfx_v8_0_init_microcode:               ; @gfx_v8_0_init_microcode
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x8, ___stack_chk_guard@GOTPAGE
Lloh1:
	ldr	x8, [x8, ___stack_chk_guard@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	str	x8, [sp, #40]
Lloh3:
	adrp	x0, l_.str@PAGE
Lloh4:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG
	ldr	w8, [x19]
	sub	w8, w8, #128
	cmp	w8, #9
	b.hs	LBB0_38
; %bb.1:
Lloh5:
	adrp	x9, l_switch.table.gfx_v8_0_init_microcode@PAGE
Lloh6:
	add	x9, x9, l_switch.table.gfx_v8_0_init_microcode@PAGEOFF
	ldr	x20, [x9, w8, sxtw #3]
Lloh7:
	adrp	x2, l_.str.11@PAGE
Lloh8:
	add	x2, x2, l_.str.11@PAGEOFF
	add	x0, sp, #10
	mov	w1, #30
	mov	x3, x20
	bl	_snprintf
	add	x22, x19, #96
	ldr	w2, [x19, #160]
	add	x1, sp, #10
	mov	x0, x22
	bl	_request_firmware
	mov	x21, x0
	cbnz	w0, LBB0_12
; %bb.2:
	ldr	x0, [x22]
	bl	_amdgpu_ucode_validate
	mov	x21, x0
	cbnz	w0, LBB0_12
; %bb.3:
	ldr	x8, [x19, #96]
	ldr	x21, [x8]
	ldr	w0, [x21, #8]
	bl	_le32_to_cpu
	str	w0, [x19, #8]
	ldr	w0, [x21]
	bl	_le32_to_cpu
	str	w0, [x19, #12]
Lloh9:
	adrp	x2, l_.str.13@PAGE
Lloh10:
	add	x2, x2, l_.str.13@PAGEOFF
	add	x0, sp, #10
	mov	w1, #30
	mov	x3, x20
	bl	_snprintf
	add	x22, x19, #88
	ldr	w2, [x19, #160]
	add	x1, sp, #10
	mov	x0, x22
	bl	_request_firmware
	mov	x21, x0
	cbnz	w0, LBB0_12
; %bb.4:
	ldr	x0, [x22]
	bl	_amdgpu_ucode_validate
	mov	x21, x0
	cbnz	w0, LBB0_12
; %bb.5:
	ldr	x8, [x19, #88]
	ldr	x21, [x8]
	ldr	w0, [x21, #8]
	bl	_le32_to_cpu
	str	w0, [x19, #16]
	ldr	w0, [x21]
	bl	_le32_to_cpu
	str	w0, [x19, #20]
Lloh11:
	adrp	x2, l_.str.15@PAGE
Lloh12:
	add	x2, x2, l_.str.15@PAGEOFF
	add	x0, sp, #10
	mov	w1, #30
	mov	x3, x20
	bl	_snprintf
	add	x22, x19, #80
	ldr	w2, [x19, #160]
	add	x1, sp, #10
	mov	x0, x22
	bl	_request_firmware
	mov	x21, x0
	cbnz	w0, LBB0_12
; %bb.6:
	ldr	x0, [x22]
	bl	_amdgpu_ucode_validate
	mov	x21, x0
	cbnz	w0, LBB0_12
; %bb.7:
	ldr	x8, [x19, #80]
	ldr	x21, [x8]
	ldr	w0, [x21, #8]
	bl	_le32_to_cpu
	str	w0, [x19, #24]
	ldr	w0, [x21]
	bl	_le32_to_cpu
	str	w0, [x19, #28]
	cmp	w0, #46
	b.lt	LBB0_10
; %bb.8:
	ldr	w8, [x19, #12]
	cmp	w8, #46
	b.lt	LBB0_10
; %bb.9:
	mov	w8, #1
	str	w8, [x19, #184]
Lloh13:
	adrp	x0, l_.str.16@PAGE
Lloh14:
	add	x0, x0, l_.str.16@PAGEOFF
	bl	_DRM_INFO
	b	LBB0_11
LBB0_10:
	str	wzr, [x19, #184]
LBB0_11:
Lloh15:
	adrp	x2, l_.str.17@PAGE
Lloh16:
	add	x2, x2, l_.str.17@PAGEOFF
	add	x0, sp, #10
	mov	w1, #30
	mov	x3, x20
	bl	_snprintf
	add	x0, x19, #72
	ldr	w2, [x19, #160]
	add	x1, sp, #10
	bl	_request_firmware
	mov	x21, x0
	cbz	w0, LBB0_15
LBB0_12:
	ldr	w0, [x19, #160]
Lloh17:
	adrp	x1, l_.str.22@PAGE
Lloh18:
	add	x1, x1, l_.str.22@PAGEOFF
	add	x2, sp, #10
	bl	_dev_err
	ldr	x0, [x19, #96]
	bl	_release_firmware
	str	xzr, [x19, #96]
	ldr	x0, [x19, #88]
	bl	_release_firmware
	str	xzr, [x19, #88]
	ldr	x0, [x19, #80]
	bl	_release_firmware
	str	xzr, [x19, #80]
	ldr	x0, [x19, #72]
	bl	_release_firmware
	str	xzr, [x19, #72]
	ldr	x0, [x19, #64]
	bl	_release_firmware
	str	xzr, [x19, #64]
	ldr	x0, [x19, #56]
	bl	_release_firmware
	str	xzr, [x19, #56]
LBB0_13:
	ldr	x8, [sp, #40]
Lloh19:
	adrp	x9, ___stack_chk_guard@GOTPAGE
Lloh20:
	ldr	x9, [x9, ___stack_chk_guard@GOTPAGEOFF]
Lloh21:
	ldr	x9, [x9]
	cmp	x9, x8
	b.ne	LBB0_37
; %bb.14:
	mov	x0, x21
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
LBB0_15:
	ldr	x0, [x19, #72]
	bl	_amdgpu_ucode_validate
	ldr	x8, [x19, #72]
	ldr	x21, [x8]
	ldr	w0, [x21, #48]
	bl	_le32_to_cpu
	str	w0, [x19, #32]
	ldr	w0, [x21]
	bl	_le32_to_cpu
	str	w0, [x19, #36]
	ldr	w0, [x21, #4]
	bl	_le32_to_cpu
	str	w0, [x19, #104]
	ldr	w0, [x21, #8]
	bl	_le32_to_cpu
	str	w0, [x19, #108]
	ldr	w0, [x21, #12]
	bl	_le32_to_cpu
	str	w0, [x19, #112]
	ldr	w0, [x21, #16]
	bl	_le32_to_cpu
	str	w0, [x19, #116]
	ldr	w0, [x21, #20]
	bl	_le32_to_cpu
	str	w0, [x19, #120]
	ldr	w0, [x21, #24]
	bl	_le32_to_cpu
	str	w0, [x19, #124]
	ldr	w0, [x21, #28]
	bl	_le32_to_cpu
	str	w0, [x19, #128]
	ldr	w0, [x21, #32]
	bl	_le32_to_cpu
	str	w0, [x19, #132]
	ldr	w0, [x21, #36]
	bl	_le32_to_cpu
	str	w0, [x19, #136]
	ldr	w8, [x19, #132]
	add	w0, w8, w0
Lloh22:
	adrp	x8, _GFP_KERNEL@GOTPAGE
Lloh23:
	ldr	x8, [x8, _GFP_KERNEL@GOTPAGEOFF]
Lloh24:
	ldr	w1, [x8]
	bl	_kmalloc
	str	x0, [x19, #144]
	cbz	x0, LBB0_18
; %bb.16:
	ldr	w0, [x21, #40]
	bl	_le32_to_cpu
	ldr	w8, [x19, #132]
	cmp	w8, #4
	b.hs	LBB0_20
; %bb.17:
	mov	x22, #0
	ldr	x8, [x19, #144]
	b	LBB0_22
LBB0_18:
Lloh25:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh26:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
	cbz	w8, LBB0_34
; %bb.19:
	neg	w21, w8
	b	LBB0_12
LBB0_20:
	mov	x22, #0
	add	x23, x21, w0, sxtw
LBB0_21:                                ; =>This Inner Loop Header: Depth=1
	lsl	x24, x22, #2
	ldr	w0, [x23, x24]
	bl	_le32_to_cpu
	ldr	x8, [x19, #144]
	str	w0, [x8, x24]
	add	x22, x22, #1
	ldr	w9, [x19, #132]
	asr	w9, w9, #2
	cmp	x22, x9
	b.lo	LBB0_21
LBB0_22:
	add	x8, x8, x22, lsl #2
	str	x8, [x19, #152]
	ldr	w0, [x21, #44]
	bl	_le32_to_cpu
	ldr	w8, [x19, #136]
	cmp	w8, #4
	b.lo	LBB0_25
; %bb.23:
	mov	x22, #0
	add	x21, x21, w0, sxtw
LBB0_24:                                ; =>This Inner Loop Header: Depth=1
	lsl	x23, x22, #2
	ldr	w0, [x21, x23]
	bl	_le32_to_cpu
	ldr	x8, [x19, #152]
	str	w0, [x8, x23]
	add	x22, x22, #1
	ldr	w8, [x19, #136]
	asr	w8, w8, #2
	cmp	x22, x8
	b.lo	LBB0_24
LBB0_25:
Lloh28:
	adrp	x2, l_.str.19@PAGE
Lloh29:
	add	x2, x2, l_.str.19@PAGEOFF
	add	x0, sp, #10
	mov	w1, #30
	mov	x3, x20
	bl	_snprintf
	add	x22, x19, #64
	ldr	w2, [x19, #160]
	add	x1, sp, #10
	mov	x0, x22
	bl	_request_firmware
	mov	x21, x0
	cbnz	w0, LBB0_12
; %bb.26:
	ldr	x0, [x22]
	bl	_amdgpu_ucode_validate
	mov	x21, x0
	cbnz	w0, LBB0_12
; %bb.27:
	ldr	x8, [x19, #64]
	ldr	x21, [x8]
	ldr	w0, [x21, #8]
	bl	_le32_to_cpu
	str	w0, [x19, #40]
	ldr	w0, [x21]
	bl	_le32_to_cpu
	str	w0, [x19, #44]
	ldr	w8, [x19]
	orr	w8, w8, #0x2
	cmp	w8, #131
	b.eq	LBB0_30
; %bb.28:
Lloh30:
	adrp	x2, l_.str.21@PAGE
Lloh31:
	add	x2, x2, l_.str.21@PAGEOFF
	add	x0, sp, #10
	mov	w1, #30
	mov	x3, x20
	bl	_snprintf
	add	x20, x19, #56
	ldr	w2, [x19, #160]
	add	x1, sp, #10
	mov	x0, x20
	bl	_request_firmware
	cbz	w0, LBB0_35
; %bb.29:
	str	xzr, [x20]
LBB0_30:
	ldr	x8, [x19, #176]
Lloh32:
	adrp	x9, _AMDGPU_UCODE_ID_CP_PFP@GOTPAGE
Lloh33:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_CP_PFP@GOTPAGEOFF]
Lloh34:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19, #96]
	str	x9, [x8, #8]
	ldr	x8, [x9]
	ldr	w0, [x8]
	bl	_le32_to_cpu
Lloh35:
	adrp	x20, _PAGE_SIZE@GOTPAGE
Lloh36:
	ldr	x20, [x20, _PAGE_SIZE@GOTPAGEOFF]
	ldr	w1, [x20]
	bl	_ALIGN
	ldr	w8, [x19, #168]
	add	w8, w8, w0
	str	w8, [x19, #168]
	ldr	x8, [x19, #176]
Lloh37:
	adrp	x9, _AMDGPU_UCODE_ID_CP_ME@GOTPAGE
Lloh38:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_CP_ME@GOTPAGEOFF]
Lloh39:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19, #88]
	str	x9, [x8, #8]
	ldr	x8, [x9]
	ldr	w0, [x8]
	bl	_le32_to_cpu
	ldr	w1, [x20]
	bl	_ALIGN
	ldr	w8, [x19, #168]
	add	w8, w8, w0
	str	w8, [x19, #168]
	ldr	x8, [x19, #176]
Lloh40:
	adrp	x9, _AMDGPU_UCODE_ID_CP_CE@GOTPAGE
Lloh41:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_CP_CE@GOTPAGEOFF]
Lloh42:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19, #80]
	str	x9, [x8, #8]
	ldr	x8, [x9]
	ldr	w0, [x8]
	bl	_le32_to_cpu
	ldr	w1, [x20]
	bl	_ALIGN
	ldr	w8, [x19, #168]
	add	w8, w8, w0
	str	w8, [x19, #168]
	ldr	x8, [x19, #176]
Lloh43:
	adrp	x9, _AMDGPU_UCODE_ID_RLC_G@GOTPAGE
Lloh44:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_RLC_G@GOTPAGEOFF]
Lloh45:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19, #72]
	str	x9, [x8, #8]
	ldr	x8, [x9]
	ldr	w0, [x8]
	bl	_le32_to_cpu
	ldr	w1, [x20]
	bl	_ALIGN
	ldr	w8, [x19, #168]
	add	w8, w8, w0
	str	w8, [x19, #168]
	ldr	x8, [x19, #176]
Lloh46:
	adrp	x9, _AMDGPU_UCODE_ID_CP_MEC1@GOTPAGE
Lloh47:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_CP_MEC1@GOTPAGEOFF]
Lloh48:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19, #64]
	str	x9, [x8, #8]
	ldr	x8, [x9]
	ldr	w0, [x8]
	bl	_le32_to_cpu
	ldr	w1, [x20]
	bl	_ALIGN
	ldr	w8, [x19, #168]
	add	w8, w8, w0
	str	w8, [x19, #168]
	ldr	x8, [x19, #64]
	ldr	x8, [x8]
	ldr	w0, [x8, #4]
	bl	_le32_to_cpu
	lsl	w0, w0, #2
	ldr	w1, [x20]
	bl	_ALIGN
	ldr	w8, [x19, #168]
	add	w8, w8, w0
	str	w8, [x19, #168]
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_32
; %bb.31:
	ldr	x8, [x19, #176]
Lloh49:
	adrp	x9, _AMDGPU_UCODE_ID_STORAGE@GOTPAGE
Lloh50:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_STORAGE@GOTPAGEOFF]
Lloh51:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19, #64]
	str	x9, [x8, #8]
	ldr	w8, [x20]
	lsl	w0, w8, #6
	bl	_le32_to_cpu
	ldr	w1, [x20]
	bl	_ALIGN
	ldr	w8, [x19, #168]
	add	w8, w8, w0
	str	w8, [x19, #168]
LBB0_32:
	ldr	x8, [x19, #56]
	cbz	x8, LBB0_34
; %bb.33:
	ldr	x9, [x19, #176]
Lloh52:
	adrp	x10, _AMDGPU_UCODE_ID_CP_MEC2@GOTPAGE
Lloh53:
	ldr	x10, [x10, _AMDGPU_UCODE_ID_CP_MEC2@GOTPAGEOFF]
Lloh54:
	ldr	x10, [x10]
	add	x9, x9, x10, lsl #4
	stp	x10, x8, [x9]
	ldr	x8, [x8]
	ldr	w0, [x8]
	bl	_le32_to_cpu
	ldr	w1, [x20]
	bl	_ALIGN
	mov	w21, #0
	ldr	w8, [x19, #168]
	add	w8, w8, w0
	str	w8, [x19, #168]
	b	LBB0_13
LBB0_34:
	mov	w21, #0
	b	LBB0_13
LBB0_35:
	ldr	x0, [x20]
	bl	_amdgpu_ucode_validate
	mov	x21, x0
	cbnz	w0, LBB0_12
; %bb.36:
	ldr	x8, [x19, #56]
	ldr	x20, [x8]
	ldr	w0, [x20, #8]
	bl	_le32_to_cpu
	str	w0, [x19, #48]
	ldr	w0, [x20]
	bl	_le32_to_cpu
	str	w0, [x19, #52]
	b	LBB0_30
LBB0_37:
	bl	___stack_chk_fail
LBB0_38:
	bl	_BUG
	brk	#0x1
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh7, Lloh8
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpAdd	Lloh9, Lloh10
	.loh AdrpAdd	Lloh11, Lloh12
	.loh AdrpAdd	Lloh13, Lloh14
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpAdd	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpAdd	Lloh28, Lloh29
	.loh AdrpAdd	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"\n"

l_.str.1:                               ; @.str.1
	.asciz	"topaz"

l_.str.2:                               ; @.str.2
	.asciz	"tonga"

l_.str.3:                               ; @.str.3
	.asciz	"carrizo"

l_.str.4:                               ; @.str.4
	.asciz	"fiji"

l_.str.5:                               ; @.str.5
	.asciz	"stoney"

l_.str.6:                               ; @.str.6
	.asciz	"polaris10"

l_.str.7:                               ; @.str.7
	.asciz	"polaris11"

l_.str.8:                               ; @.str.8
	.asciz	"polaris12"

l_.str.9:                               ; @.str.9
	.asciz	"vegam"

	.comm	_ENOENT,4,2                     ; @ENOENT
l_.str.11:                              ; @.str.11
	.asciz	"amdgpu/%s_pfp.bin"

l_.str.13:                              ; @.str.13
	.asciz	"amdgpu/%s_me.bin"

l_.str.15:                              ; @.str.15
	.asciz	"amdgpu/%s_ce.bin"

l_.str.16:                              ; @.str.16
	.asciz	"Chained IB support enabled!\n"

l_.str.17:                              ; @.str.17
	.asciz	"amdgpu/%s_rlc.bin"

	.comm	_GFP_KERNEL,4,2                 ; @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ; @ENOMEM
l_.str.19:                              ; @.str.19
	.asciz	"amdgpu/%s_mec.bin"

l_.str.21:                              ; @.str.21
	.asciz	"amdgpu/%s_mec2.bin"

	.comm	_AMDGPU_UCODE_ID_CP_PFP,8,3     ; @AMDGPU_UCODE_ID_CP_PFP
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
	.comm	_AMDGPU_UCODE_ID_CP_ME,8,3      ; @AMDGPU_UCODE_ID_CP_ME
	.comm	_AMDGPU_UCODE_ID_CP_CE,8,3      ; @AMDGPU_UCODE_ID_CP_CE
	.comm	_AMDGPU_UCODE_ID_RLC_G,8,3      ; @AMDGPU_UCODE_ID_RLC_G
	.comm	_AMDGPU_UCODE_ID_CP_MEC1,8,3    ; @AMDGPU_UCODE_ID_CP_MEC1
	.comm	_AMDGPU_UCODE_ID_STORAGE,8,3    ; @AMDGPU_UCODE_ID_STORAGE
	.comm	_AMDGPU_UCODE_ID_CP_MEC2,8,3    ; @AMDGPU_UCODE_ID_CP_MEC2
l_.str.22:                              ; @.str.22
	.asciz	"gfx8: Failed to load firmware \"%s\"\n"

	.no_dead_strip	_gfx_v8_0_init_microcode
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.gfx_v8_0_init_microcode
l_switch.table.gfx_v8_0_init_microcode:
	.quad	l_.str.9
	.quad	l_.str.1
	.quad	l_.str.2
	.quad	l_.str.5
	.quad	l_.str.8
	.quad	l_.str.7
	.quad	l_.str.6
	.quad	l_.str.4
	.quad	l_.str.3

.subsections_via_symbols
