	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mixer_cfg_layer
_mixer_cfg_layer:                       ## @mixer_cfg_layer
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r14d
	movq	%rdi, %r15
	xorl	%ebx, %ebx
	negl	%ecx
	sbbl	%ebx, %ebx
	cmpl	$128, %esi
	je	LBB0_6
## %bb.1:
	cmpl	$1, %esi
	je	LBB0_5
## %bb.2:
	testl	%esi, %esi
	jne	LBB0_8
## %bb.3:
	movq	_MXR_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MXR_CFG_GRP0_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_mixer_reg_writemask
	movq	_MXR_LAYER_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%r14d, %edi
	callq	_MXR_LAYER_CFG_GRP0_VAL
	movq	_MXR_LAYER_CFG_GRP0_MASK@GOTPCREL(%rip), %rcx
	jmp	LBB0_4
LBB0_6:
	movq	_MXR_BIT_VP_ENABLED@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	%r15, %rsi
	callq	_test_bit
	testl	%eax, %eax
	je	LBB0_8
## %bb.7:
	movq	_VP_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_VP_ENABLE_ON@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_vp_reg_writemask
	movq	_MXR_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MXR_CFG_VP_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_mixer_reg_writemask
	movq	_MXR_LAYER_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%r14d, %edi
	callq	_MXR_LAYER_CFG_VP_VAL
	movq	_MXR_LAYER_CFG_VP_MASK@GOTPCREL(%rip), %rcx
	jmp	LBB0_4
LBB0_8:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_5:
	movq	_MXR_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MXR_CFG_GRP1_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_mixer_reg_writemask
	movq	_MXR_LAYER_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%r14d, %edi
	callq	_MXR_LAYER_CFG_GRP1_VAL
	movq	_MXR_LAYER_CFG_GRP1_MASK@GOTPCREL(%rip), %rcx
LBB0_4:
	movl	(%rcx), %ecx
	movq	%r15, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_mixer_reg_writemask            ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_MXR_CFG,4,2                    ## @MXR_CFG
	.comm	_MXR_CFG_GRP0_ENABLE,4,2        ## @MXR_CFG_GRP0_ENABLE
	.comm	_MXR_LAYER_CFG,4,2              ## @MXR_LAYER_CFG
	.comm	_MXR_LAYER_CFG_GRP0_MASK,4,2    ## @MXR_LAYER_CFG_GRP0_MASK
	.comm	_MXR_CFG_GRP1_ENABLE,4,2        ## @MXR_CFG_GRP1_ENABLE
	.comm	_MXR_LAYER_CFG_GRP1_MASK,4,2    ## @MXR_LAYER_CFG_GRP1_MASK
	.comm	_MXR_BIT_VP_ENABLED,4,2         ## @MXR_BIT_VP_ENABLED
	.comm	_VP_ENABLE,4,2                  ## @VP_ENABLE
	.comm	_VP_ENABLE_ON,4,2               ## @VP_ENABLE_ON
	.comm	_MXR_CFG_VP_ENABLE,4,2          ## @MXR_CFG_VP_ENABLE
	.comm	_MXR_LAYER_CFG_VP_MASK,4,2      ## @MXR_LAYER_CFG_VP_MASK
	.no_dead_strip	_mixer_cfg_layer
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mixer_cfg_layer
_mixer_cfg_layer:                       ; @mixer_cfg_layer
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x2
	mov	x19, x0
	cmp	w3, #0
	csetm	w21, ne
	cmp	w1, #128
	b.eq	LBB0_4
; %bb.1:
	cmp	w1, #1
	b.eq	LBB0_7
; %bb.2:
	cbnz	w1, LBB0_6
; %bb.3:
Lloh0:
	adrp	x8, _MXR_CFG@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MXR_CFG@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
Lloh3:
	adrp	x8, _MXR_CFG_GRP0_ENABLE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _MXR_CFG_GRP0_ENABLE@GOTPAGEOFF]
Lloh5:
	ldr	w3, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_mixer_reg_writemask
Lloh6:
	adrp	x8, _MXR_LAYER_CFG@GOTPAGE
Lloh7:
	ldr	x8, [x8, _MXR_LAYER_CFG@GOTPAGEOFF]
Lloh8:
	ldr	w21, [x8]
	mov	x0, x20
	bl	_MXR_LAYER_CFG_GRP0_VAL
	mov	x2, x0
Lloh9:
	adrp	x8, _MXR_LAYER_CFG_GRP0_MASK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _MXR_LAYER_CFG_GRP0_MASK@GOTPAGEOFF]
	b	LBB0_8
LBB0_4:
Lloh11:
	adrp	x8, _MXR_BIT_VP_ENABLED@GOTPAGE
Lloh12:
	ldr	x8, [x8, _MXR_BIT_VP_ENABLED@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
	mov	x1, x19
	bl	_test_bit
	cbz	w0, LBB0_6
; %bb.5:
Lloh14:
	adrp	x8, _VP_ENABLE@GOTPAGE
Lloh15:
	ldr	x8, [x8, _VP_ENABLE@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
Lloh17:
	adrp	x8, _VP_ENABLE_ON@GOTPAGE
Lloh18:
	ldr	x8, [x8, _VP_ENABLE_ON@GOTPAGEOFF]
Lloh19:
	ldr	w3, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_vp_reg_writemask
Lloh20:
	adrp	x8, _MXR_CFG@GOTPAGE
Lloh21:
	ldr	x8, [x8, _MXR_CFG@GOTPAGEOFF]
Lloh22:
	ldr	w1, [x8]
Lloh23:
	adrp	x8, _MXR_CFG_VP_ENABLE@GOTPAGE
Lloh24:
	ldr	x8, [x8, _MXR_CFG_VP_ENABLE@GOTPAGEOFF]
Lloh25:
	ldr	w3, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_mixer_reg_writemask
Lloh26:
	adrp	x8, _MXR_LAYER_CFG@GOTPAGE
Lloh27:
	ldr	x8, [x8, _MXR_LAYER_CFG@GOTPAGEOFF]
Lloh28:
	ldr	w21, [x8]
	mov	x0, x20
	bl	_MXR_LAYER_CFG_VP_VAL
	mov	x2, x0
Lloh29:
	adrp	x8, _MXR_LAYER_CFG_VP_MASK@GOTPAGE
Lloh30:
	ldr	x8, [x8, _MXR_LAYER_CFG_VP_MASK@GOTPAGEOFF]
	b	LBB0_8
LBB0_6:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_7:
Lloh31:
	adrp	x8, _MXR_CFG@GOTPAGE
Lloh32:
	ldr	x8, [x8, _MXR_CFG@GOTPAGEOFF]
Lloh33:
	ldr	w1, [x8]
Lloh34:
	adrp	x8, _MXR_CFG_GRP1_ENABLE@GOTPAGE
Lloh35:
	ldr	x8, [x8, _MXR_CFG_GRP1_ENABLE@GOTPAGEOFF]
Lloh36:
	ldr	w3, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_mixer_reg_writemask
Lloh37:
	adrp	x8, _MXR_LAYER_CFG@GOTPAGE
Lloh38:
	ldr	x8, [x8, _MXR_LAYER_CFG@GOTPAGEOFF]
Lloh39:
	ldr	w21, [x8]
	mov	x0, x20
	bl	_MXR_LAYER_CFG_GRP1_VAL
	mov	x2, x0
Lloh40:
	adrp	x8, _MXR_LAYER_CFG_GRP1_MASK@GOTPAGE
Lloh41:
	ldr	x8, [x8, _MXR_LAYER_CFG_GRP1_MASK@GOTPAGEOFF]
LBB0_8:
	ldr	w3, [x8]
	mov	x0, x19
	mov	x1, x21
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_mixer_reg_writemask
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.cfi_endproc
                                        ; -- End function
	.comm	_MXR_CFG,4,2                    ; @MXR_CFG
	.comm	_MXR_CFG_GRP0_ENABLE,4,2        ; @MXR_CFG_GRP0_ENABLE
	.comm	_MXR_LAYER_CFG,4,2              ; @MXR_LAYER_CFG
	.comm	_MXR_LAYER_CFG_GRP0_MASK,4,2    ; @MXR_LAYER_CFG_GRP0_MASK
	.comm	_MXR_CFG_GRP1_ENABLE,4,2        ; @MXR_CFG_GRP1_ENABLE
	.comm	_MXR_LAYER_CFG_GRP1_MASK,4,2    ; @MXR_LAYER_CFG_GRP1_MASK
	.comm	_MXR_BIT_VP_ENABLED,4,2         ; @MXR_BIT_VP_ENABLED
	.comm	_VP_ENABLE,4,2                  ; @VP_ENABLE
	.comm	_VP_ENABLE_ON,4,2               ; @VP_ENABLE_ON
	.comm	_MXR_CFG_VP_ENABLE,4,2          ; @MXR_CFG_VP_ENABLE
	.comm	_MXR_LAYER_CFG_VP_MASK,4,2      ; @MXR_LAYER_CFG_VP_MASK
	.no_dead_strip	_mixer_cfg_layer
.subsections_via_symbols
