	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function soc15_asic_reset_method
_soc15_asic_reset_method:               ## @soc15_asic_reset_method
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	subq	$16, %rsp
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	movl	(%rdi), %eax
	leal	-129(%rax), %ecx
	cmpl	$2, %ecx
	jb	LBB0_4
## %bb.1:
	cmpl	$128, %eax
	je	LBB0_5
## %bb.2:
	cmpl	$131, %eax
	jne	LBB0_10
## %bb.3:
	movq	_AMD_RESET_METHOD_MODE2@GOTPCREL(%rip), %rax
	jmp	LBB0_14
LBB0_4:
	leaq	-20(%rbp), %rsi
	movq	%rbx, %rdi
	callq	_soc15_asic_get_baco_capability
	jmp	LBB0_11
LBB0_5:
	cmpl	$524390, 4(%rbx)                ## imm = 0x80066
	jle	LBB0_10
## %bb.6:
	leaq	-20(%rbp), %rsi
	movq	%rbx, %rdi
	callq	_soc15_asic_get_baco_capability
	cmpl	$0, -20(%rbp)
	je	LBB0_11
## %bb.7:
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_get_xgmi_hive
	movq	%rax, %r14
	movq	%rbx, %rdi
	callq	_amdgpu_ras_get_context
	testq	%r14, %r14
	je	LBB0_8
LBB0_10:
	movl	$0, -20(%rbp)
LBB0_11:
	cmpl	$0, -20(%rbp)
	jne	LBB0_12
## %bb.13:
	movq	_AMD_RESET_METHOD_MODE1@GOTPCREL(%rip), %rax
	jmp	LBB0_14
LBB0_12:
	movq	_AMD_RESET_METHOD_BACO@GOTPCREL(%rip), %rax
LBB0_14:
	movl	(%rax), %eax
	addq	$16, %rsp
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
LBB0_8:
	testq	%rax, %rax
	je	LBB0_11
## %bb.9:
	cmpl	$0, (%rax)
	jne	LBB0_10
	jmp	LBB0_11
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_RESET_METHOD_MODE2,4,2     ## @AMD_RESET_METHOD_MODE2
	.comm	_AMD_RESET_METHOD_BACO,4,2      ## @AMD_RESET_METHOD_BACO
	.comm	_AMD_RESET_METHOD_MODE1,4,2     ## @AMD_RESET_METHOD_MODE1
	.no_dead_strip	_soc15_asic_reset_method
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function soc15_asic_reset_method
_soc15_asic_reset_method:               ; @soc15_asic_reset_method
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #48
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	w8, [x0]
	sub	w9, w8, #129
	cmp	w9, #2
	b.lo	LBB0_4
; %bb.1:
	cmp	w8, #128
	b.eq	LBB0_5
; %bb.2:
	cmp	w8, #131
	b.ne	LBB0_8
; %bb.3:
Lloh0:
	adrp	x8, _AMD_RESET_METHOD_MODE2@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMD_RESET_METHOD_MODE2@GOTPAGEOFF]
	b	LBB0_10
LBB0_4:
	add	x1, sp, #12
	mov	x0, x19
	bl	_soc15_asic_get_baco_capability
	b	LBB0_9
LBB0_5:
	ldr	w8, [x19, #4]
	mov	w9, #102
	movk	w9, #8, lsl #16
	cmp	w8, w9
	b.le	LBB0_8
; %bb.6:
	add	x1, sp, #12
	mov	x0, x19
	bl	_soc15_asic_get_baco_capability
	ldr	w8, [sp, #12]
	cbz	w8, LBB0_9
; %bb.7:
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_get_xgmi_hive
	mov	x20, x0
	mov	x0, x19
	bl	_amdgpu_ras_get_context
	cbz	x20, LBB0_11
LBB0_8:
	str	wzr, [sp, #12]
LBB0_9:
	ldr	w8, [sp, #12]
Lloh2:
	adrp	x9, _AMD_RESET_METHOD_BACO@GOTPAGE
Lloh3:
	ldr	x9, [x9, _AMD_RESET_METHOD_BACO@GOTPAGEOFF]
Lloh4:
	adrp	x10, _AMD_RESET_METHOD_MODE1@GOTPAGE
Lloh5:
	ldr	x10, [x10, _AMD_RESET_METHOD_MODE1@GOTPAGEOFF]
	cmp	w8, #0
	csel	x8, x10, x9, eq
LBB0_10:
	ldr	w0, [x8]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	ret
LBB0_11:
	cbz	x0, LBB0_9
; %bb.12:
	ldr	w8, [x0]
	cbnz	w8, LBB0_8
	b	LBB0_9
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_RESET_METHOD_MODE2,4,2     ; @AMD_RESET_METHOD_MODE2
	.comm	_AMD_RESET_METHOD_BACO,4,2      ; @AMD_RESET_METHOD_BACO
	.comm	_AMD_RESET_METHOD_MODE1,4,2     ; @AMD_RESET_METHOD_MODE1
	.no_dead_strip	_soc15_asic_reset_method
.subsections_via_symbols
