	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gmc_v9_0_vm_fault_interrupt_state
_gmc_v9_0_vm_fault_interrupt_state:     ## @gmc_v9_0_vm_fault_interrupt_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rax
	movq	_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rdx
	movq	(%rdx), %r15
	orq	(%rax), %r15
	movq	_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rax
	orq	(%rax), %r15
	movq	_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rax
	orq	(%rax), %r15
	movq	_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rax
	orq	(%rax), %r15
	movq	%rdi, %r14
	movq	_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rax
	orq	(%rax), %r15
	movq	_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rax
	orq	(%rax), %r15
	cmpl	$129, %ecx
	je	LBB0_5
## %bb.1:
	cmpl	$128, %ecx
	jne	LBB0_8
## %bb.2:
	cmpq	$0, (%r14)
	je	LBB0_8
## %bb.3:
	xorl	%r12d, %r12d
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movq	8(%r14), %r13
	movq	(%r13,%r12,8), %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	orq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	incq	%rbx
	movq	%rbx, %rdi
	callq	_RREG32
	orq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$2, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	orq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$3, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	orq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$4, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	orq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$5, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	orq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$6, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	orq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$7, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	orq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$8, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	orq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$9, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	orq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$10, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	orq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$11, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	orq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$12, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	orq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$13, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	orq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$14, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	orq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$15, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	orq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	incq	%r12
	cmpq	(%r14), %r12
	jb	LBB0_4
	jmp	LBB0_8
LBB0_5:
	cmpq	$0, (%r14)
	je	LBB0_8
## %bb.6:
	notq	%r15
	xorl	%r12d, %r12d
	.p2align	4, 0x90
LBB0_7:                                 ## =>This Inner Loop Header: Depth=1
	movq	8(%r14), %r13
	movq	(%r13,%r12,8), %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	andq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	incq	%rbx
	movq	%rbx, %rdi
	callq	_RREG32
	andq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$2, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	andq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$3, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	andq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$4, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	andq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$5, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	andq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$6, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	andq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$7, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	andq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$8, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	andq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$9, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	andq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$10, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	andq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$11, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	andq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$12, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	andq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$13, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	andq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$14, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	andq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	movq	(%r13,%r12,8), %rbx
	addq	$15, %rbx
	movq	%rbx, %rdi
	callq	_RREG32
	andq	%r15, %rax
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_WREG32
	incq	%r12
	cmpq	(%r14), %r12
	jb	LBB0_7
LBB0_8:
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,8,3 ## @VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,8,3 ## @VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,8,3 ## @VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,8,3 ## @VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,8,3 ## @VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,8,3 ## @VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,8,3 ## @VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.no_dead_strip	_gmc_v9_0_vm_fault_interrupt_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gmc_v9_0_vm_fault_interrupt_state
_gmc_v9_0_vm_fault_interrupt_state:     ; @gmc_v9_0_vm_fault_interrupt_state
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x8, _VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
Lloh2:
	adrp	x9, _VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh3:
	ldr	x9, [x9, _VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
Lloh4:
	ldr	x8, [x8]
Lloh5:
	ldr	x9, [x9]
	orr	x8, x9, x8
Lloh6:
	adrp	x9, _VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh7:
	ldr	x9, [x9, _VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
Lloh8:
	ldr	x9, [x9]
	orr	x8, x8, x9
Lloh9:
	adrp	x9, _VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh10:
	ldr	x9, [x9, _VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
Lloh11:
	ldr	x9, [x9]
Lloh12:
	adrp	x10, _VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh13:
	ldr	x10, [x10, _VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
	orr	x8, x8, x9
Lloh14:
	ldr	x9, [x10]
	orr	x8, x8, x9
Lloh15:
	adrp	x9, _VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh16:
	ldr	x9, [x9, _VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
Lloh17:
	ldr	x9, [x9]
	orr	x8, x8, x9
Lloh18:
	adrp	x9, _VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh19:
	ldr	x9, [x9, _VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
Lloh20:
	ldr	x9, [x9]
	orr	x21, x8, x9
	cmp	w3, #129
	b.eq	LBB0_5
; %bb.1:
	cmp	w3, #128
	b.ne	LBB0_8
; %bb.2:
	ldr	x8, [x19]
	cbz	x8, LBB0_8
; %bb.3:
	mov	x22, #0
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x23, [x19, #8]
	lsl	x24, x22, #3
	ldr	x20, [x23, x24]
	mov	x0, x20
	bl	_RREG32
	orr	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #1
	mov	x0, x20
	bl	_RREG32
	orr	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #2
	mov	x0, x20
	bl	_RREG32
	orr	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #3
	mov	x0, x20
	bl	_RREG32
	orr	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #4
	mov	x0, x20
	bl	_RREG32
	orr	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #5
	mov	x0, x20
	bl	_RREG32
	orr	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #6
	mov	x0, x20
	bl	_RREG32
	orr	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #7
	mov	x0, x20
	bl	_RREG32
	orr	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #8
	mov	x0, x20
	bl	_RREG32
	orr	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #9
	mov	x0, x20
	bl	_RREG32
	orr	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #10
	mov	x0, x20
	bl	_RREG32
	orr	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #11
	mov	x0, x20
	bl	_RREG32
	orr	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #12
	mov	x0, x20
	bl	_RREG32
	orr	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #13
	mov	x0, x20
	bl	_RREG32
	orr	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #14
	mov	x0, x20
	bl	_RREG32
	orr	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #15
	mov	x0, x20
	bl	_RREG32
	orr	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	add	x22, x22, #1
	ldr	x8, [x19]
	cmp	x22, x8
	b.lo	LBB0_4
	b	LBB0_8
LBB0_5:
	ldr	x8, [x19]
	cbz	x8, LBB0_8
; %bb.6:
	mov	x22, #0
	mvn	x21, x21
LBB0_7:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x23, [x19, #8]
	lsl	x24, x22, #3
	ldr	x20, [x23, x24]
	mov	x0, x20
	bl	_RREG32
	and	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #1
	mov	x0, x20
	bl	_RREG32
	and	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #2
	mov	x0, x20
	bl	_RREG32
	and	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #3
	mov	x0, x20
	bl	_RREG32
	and	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #4
	mov	x0, x20
	bl	_RREG32
	and	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #5
	mov	x0, x20
	bl	_RREG32
	and	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #6
	mov	x0, x20
	bl	_RREG32
	and	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #7
	mov	x0, x20
	bl	_RREG32
	and	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #8
	mov	x0, x20
	bl	_RREG32
	and	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #9
	mov	x0, x20
	bl	_RREG32
	and	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #10
	mov	x0, x20
	bl	_RREG32
	and	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #11
	mov	x0, x20
	bl	_RREG32
	and	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #12
	mov	x0, x20
	bl	_RREG32
	and	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #13
	mov	x0, x20
	bl	_RREG32
	and	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #14
	mov	x0, x20
	bl	_RREG32
	and	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	ldr	x8, [x23, x24]
	add	x20, x8, #15
	mov	x0, x20
	bl	_RREG32
	and	x1, x0, x21
	mov	x0, x20
	bl	_WREG32
	add	x22, x22, #1
	ldr	x8, [x19]
	cmp	x22, x8
	b.lo	LBB0_7
LBB0_8:
	mov	w0, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,8,3 ; @VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,8,3 ; @VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,8,3 ; @VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,8,3 ; @VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,8,3 ; @VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,8,3 ; @VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,8,3 ; @VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.no_dead_strip	_gmc_v9_0_vm_fault_interrupt_state
.subsections_via_symbols
