	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v9_0_update_gfx_cg_power_gating
_gfx_v9_0_update_gfx_cg_power_gating:   ## @gfx_v9_0_update_gfx_cg_power_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movl	%esi, %r14d
	movq	%rdi, %rbx
	callq	_amdgpu_gfx_rlc_enter_safe_mode
	movq	%rbx, %rdi
	callq	_is_support_sw_smu
	testl	%r14d, %r14d
	jne	LBB0_3
## %bb.1:
	testq	%rax, %rax
	je	LBB0_3
## %bb.2:
	leaq	4(%rbx), %rdi
	xorl	%esi, %esi
	callq	_smu_set_gfx_cgpg
LBB0_3:
	testl	%r14d, %r14d
	je	LBB0_6
## %bb.4:
	movq	_AMD_PG_SUPPORT_GFX_PG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%rbx), %eax
	je	LBB0_6
## %bb.5:
	movl	$1, %r14d
	movq	%rbx, %rdi
	movl	$1, %esi
	callq	_gfx_v9_0_enable_gfx_cg_power_gating
	movq	_AMD_PG_SUPPORT_GFX_PIPELINE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rbx)
	jne	LBB0_7
	jmp	LBB0_8
LBB0_6:
	xorl	%r14d, %r14d
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_gfx_v9_0_enable_gfx_cg_power_gating
LBB0_7:
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_gfx_v9_0_enable_gfx_pipeline_powergating
LBB0_8:
	movq	%rbx, %rdi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_amdgpu_gfx_rlc_exit_safe_mode  ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_PG_SUPPORT_GFX_PG,4,2      ## @AMD_PG_SUPPORT_GFX_PG
	.comm	_AMD_PG_SUPPORT_GFX_PIPELINE,4,2 ## @AMD_PG_SUPPORT_GFX_PIPELINE
	.no_dead_strip	_gfx_v9_0_update_gfx_cg_power_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v9_0_update_gfx_cg_power_gating
_gfx_v9_0_update_gfx_cg_power_gating:   ; @gfx_v9_0_update_gfx_cg_power_gating
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x20, x1
	mov	x19, x0
	bl	_amdgpu_gfx_rlc_enter_safe_mode
	mov	x0, x19
	bl	_is_support_sw_smu
	cbnz	w20, LBB0_3
; %bb.1:
	cbz	x0, LBB0_3
; %bb.2:
	add	x0, x19, #4
	mov	w1, #0
	bl	_smu_set_gfx_cgpg
LBB0_3:
	cbz	w20, LBB0_6
; %bb.4:
	ldr	w8, [x19]
Lloh0:
	adrp	x9, _AMD_PG_SUPPORT_GFX_PG@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_PG_SUPPORT_GFX_PG@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	and	w8, w9, w8
	cbz	w8, LBB0_6
; %bb.5:
	mov	w20, #1
	mov	x0, x19
	mov	w1, #1
	bl	_gfx_v9_0_enable_gfx_cg_power_gating
	ldr	w8, [x19]
Lloh3:
	adrp	x9, _AMD_PG_SUPPORT_GFX_PIPELINE@GOTPAGE
Lloh4:
	ldr	x9, [x9, _AMD_PG_SUPPORT_GFX_PIPELINE@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_7
	b	LBB0_8
LBB0_6:
	mov	x0, x19
	mov	w1, #0
	bl	_gfx_v9_0_enable_gfx_cg_power_gating
	mov	w20, #0
LBB0_7:
	mov	x0, x19
	mov	x1, x20
	bl	_gfx_v9_0_enable_gfx_pipeline_powergating
LBB0_8:
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_amdgpu_gfx_rlc_exit_safe_mode
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_PG_SUPPORT_GFX_PG,4,2      ; @AMD_PG_SUPPORT_GFX_PG
	.comm	_AMD_PG_SUPPORT_GFX_PIPELINE,4,2 ; @AMD_PG_SUPPORT_GFX_PIPELINE
	.no_dead_strip	_gfx_v9_0_update_gfx_cg_power_gating
.subsections_via_symbols
