	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v7_0_rlc_init
_gfx_v7_0_rlc_init:                     ## @gfx_v7_0_rlc_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rdi)
	je	LBB0_5
## %bb.1:
	movq	8(%rbx), %rax
	movq	_CHIP_KAVERI@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_2
## %bb.3:
	movq	_spectre_rlc_save_restore_register_list@GOTPCREL(%rip), %rax
	jmp	LBB0_4
LBB0_2:
	movq	_kalindi_rlc_save_restore_register_list@GOTPCREL(%rip), %rax
LBB0_4:
	movq	(%rax), %rdi
	movq	%rdi, 16(%rbx)
	callq	_ARRAY_SIZE
	movq	%rax, 40(%rbx)
LBB0_5:
	movq	_ci_cs_data@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 32(%rbx)
	movq	_CP_ME_TABLE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	shll	$2, %eax
	leal	(%rax,%rax,4), %edi
	movl	$2048, %esi                     ## imm = 0x800
	callq	_ALIGN
	addq	$65536, %rax                    ## imm = 0x10000
	movq	%rax, 24(%rbx)
	movq	32(%rbx), %r14
	cmpq	$0, 16(%rbx)
	je	LBB0_7
## %bb.6:
	movl	$240, %esi
	addq	40(%rbx), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_gfx_rlc_init_sr
	testl	%eax, %eax
	jne	LBB0_12
LBB0_7:
	testq	%r14, %r14
	je	LBB0_9
## %bb.8:
	movq	%rbx, %rdi
	callq	_amdgpu_gfx_rlc_init_csb
	testl	%eax, %eax
	jne	LBB0_12
LBB0_9:
	cmpq	$0, 24(%rbx)
	je	LBB0_11
## %bb.10:
	movq	%rbx, %rdi
	callq	_amdgpu_gfx_rlc_init_cpt
	testl	%eax, %eax
	jne	LBB0_12
LBB0_11:
	xorl	%eax, %eax
LBB0_12:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_CHIP_KAVERI,8,3                ## @CHIP_KAVERI
	.comm	_spectre_rlc_save_restore_register_list,8,3 ## @spectre_rlc_save_restore_register_list
	.comm	_kalindi_rlc_save_restore_register_list,8,3 ## @kalindi_rlc_save_restore_register_list
	.comm	_ci_cs_data,8,3                 ## @ci_cs_data
	.comm	_CP_ME_TABLE_SIZE,4,2           ## @CP_ME_TABLE_SIZE
	.no_dead_strip	_gfx_v7_0_rlc_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v7_0_rlc_init
_gfx_v7_0_rlc_init:                     ; @gfx_v7_0_rlc_init
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _AMD_IS_APU@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_IS_APU@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
	ldr	x8, [x19, #8]
Lloh3:
	adrp	x9, _CHIP_KAVERI@GOTPAGE
Lloh4:
	ldr	x9, [x9, _CHIP_KAVERI@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
Lloh6:
	adrp	x10, _spectre_rlc_save_restore_register_list@GOTPAGE
Lloh7:
	ldr	x10, [x10, _spectre_rlc_save_restore_register_list@GOTPAGEOFF]
Lloh8:
	adrp	x11, _kalindi_rlc_save_restore_register_list@GOTPAGE
Lloh9:
	ldr	x11, [x11, _kalindi_rlc_save_restore_register_list@GOTPAGEOFF]
	cmp	x8, x9
	csel	x8, x10, x11, eq
	ldr	x0, [x8]
	str	x0, [x19, #16]
	bl	_ARRAY_SIZE
	str	x0, [x19, #40]
LBB0_2:
Lloh10:
	adrp	x8, _ci_cs_data@GOTPAGE
Lloh11:
	ldr	x8, [x8, _ci_cs_data@GOTPAGEOFF]
Lloh12:
	ldr	x8, [x8]
	str	x8, [x19, #32]
Lloh13:
	adrp	x8, _CP_ME_TABLE_SIZE@GOTPAGE
Lloh14:
	ldr	x8, [x8, _CP_ME_TABLE_SIZE@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
	add	w8, w8, w8, lsl #2
	lsl	w0, w8, #2
	mov	w1, #2048
	bl	_ALIGN
	add	x8, x0, #16, lsl #12            ; =65536
	str	x8, [x19, #24]
	ldr	x8, [x19, #16]
	ldr	x20, [x19, #32]
	cbz	x8, LBB0_4
; %bb.3:
	ldr	x8, [x19, #40]
	add	x1, x8, #240
	mov	x0, x19
	bl	_amdgpu_gfx_rlc_init_sr
	cbnz	w0, LBB0_9
LBB0_4:
	cbz	x20, LBB0_6
; %bb.5:
	mov	x0, x19
	bl	_amdgpu_gfx_rlc_init_csb
	cbnz	w0, LBB0_9
LBB0_6:
	ldr	x8, [x19, #24]
	cbz	x8, LBB0_8
; %bb.7:
	mov	x0, x19
	bl	_amdgpu_gfx_rlc_init_cpt
	cbnz	w0, LBB0_9
LBB0_8:
	mov	w0, #0
LBB0_9:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_CHIP_KAVERI,8,3                ; @CHIP_KAVERI
	.comm	_spectre_rlc_save_restore_register_list,8,3 ; @spectre_rlc_save_restore_register_list
	.comm	_kalindi_rlc_save_restore_register_list,8,3 ; @kalindi_rlc_save_restore_register_list
	.comm	_ci_cs_data,8,3                 ; @ci_cs_data
	.comm	_CP_ME_TABLE_SIZE,4,2           ; @CP_ME_TABLE_SIZE
	.no_dead_strip	_gfx_v7_0_rlc_init
.subsections_via_symbols
