	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v9_0_rlc_resume
_gfx_v9_0_rlc_resume:                   ## @gfx_v9_0_rlc_resume
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	%rbx, %rdi
	callq	_gfx_v9_0_init_csb
	jmp	LBB0_10
LBB0_2:
	movq	8(%rbx), %rax
	movq	%rbx, %rdi
	callq	*8(%rax)
	movq	_GC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmRLC_CGCG_CGLS_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movq	%rbx, %rdi
	callq	_gfx_v9_0_init_pg
	movq	16(%rbx), %rax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_4
## %bb.3:
	movq	%rbx, %rdi
	callq	_gfx_v9_0_rlc_load_microcode
	testl	%eax, %eax
	jne	LBB0_11
LBB0_4:
	movl	(%rbx), %eax
	cmpl	$128, %eax
	je	LBB0_7
## %bb.5:
	cmpl	$129, %eax
	jne	LBB0_9
## %bb.6:
	movq	_amdgpu_lbpw@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	setne	%al
	jmp	LBB0_8
LBB0_7:
	movq	_amdgpu_lbpw@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	setg	%al
LBB0_8:
	movzbl	%al, %esi
	movq	%rbx, %rdi
	callq	_gfx_v9_0_enable_lbpw
LBB0_9:
	movq	8(%rbx), %rax
	movq	%rbx, %rdi
	callq	*(%rax)
LBB0_10:
	xorl	%eax, %eax
LBB0_11:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_GC,4,2                         ## @GC
	.comm	_mmRLC_CGCG_CGLS_CTRL,4,2       ## @mmRLC_CGCG_CGLS_CTRL
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_amdgpu_lbpw,4,2                ## @amdgpu_lbpw
	.no_dead_strip	_gfx_v9_0_rlc_resume
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v9_0_rlc_resume
_gfx_v9_0_rlc_resume:                   ; @gfx_v9_0_rlc_resume
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_2
; %bb.1:
	mov	x0, x19
	bl	_gfx_v9_0_init_csb
	b	LBB0_10
LBB0_2:
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	mov	x0, x19
	blr	x8
Lloh0:
	adrp	x8, _GC@GOTPAGE
Lloh1:
	ldr	x8, [x8, _GC@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
Lloh3:
	adrp	x8, _mmRLC_CGCG_CGLS_CTRL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _mmRLC_CGCG_CGLS_CTRL@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	mov	x0, x19
	bl	_gfx_v9_0_init_pg
	ldr	x8, [x19, #16]
Lloh6:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh7:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh8:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_4
; %bb.3:
	mov	x0, x19
	bl	_gfx_v9_0_rlc_load_microcode
	cbnz	w0, LBB0_11
LBB0_4:
	ldr	w8, [x19]
	cmp	w8, #128
	b.eq	LBB0_7
; %bb.5:
	cmp	w8, #129
	b.ne	LBB0_9
; %bb.6:
Lloh9:
	adrp	x8, _amdgpu_lbpw@GOTPAGE
Lloh10:
	ldr	x8, [x8, _amdgpu_lbpw@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	cmp	w8, #0
	cset	w1, ne
	b	LBB0_8
LBB0_7:
Lloh12:
	adrp	x8, _amdgpu_lbpw@GOTPAGE
Lloh13:
	ldr	x8, [x8, _amdgpu_lbpw@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	cmp	w8, #0
	cset	w1, gt
LBB0_8:
	mov	x0, x19
	bl	_gfx_v9_0_enable_lbpw
LBB0_9:
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	mov	x0, x19
	blr	x8
LBB0_10:
	mov	w0, #0
LBB0_11:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.cfi_endproc
                                        ; -- End function
	.comm	_GC,4,2                         ; @GC
	.comm	_mmRLC_CGCG_CGLS_CTRL,4,2       ; @mmRLC_CGCG_CGLS_CTRL
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_amdgpu_lbpw,4,2                ; @amdgpu_lbpw
	.no_dead_strip	_gfx_v9_0_rlc_resume
.subsections_via_symbols
