	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vce_v4_0_set_interrupt_state
_vce_v4_0_set_interrupt_state:          ## @vce_v4_0_set_interrupt_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %ebx
	callq	_amdgpu_sriov_vf
	testl	%eax, %eax
	jne	LBB0_4
## %bb.1:
	movq	_AMDGPU_IRQ_STATE_ENABLE@GOTPCREL(%rip), %rax
	movq	_VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK@GOTPCREL(%rip), %r15
	movl	$0, %r14d
	cmpl	%ebx, (%rax)
	jne	LBB0_3
## %bb.2:
	movl	(%r15), %r14d
LBB0_3:
	movq	_VCE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmVCE_SYS_INT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r15), %edx
	notl	%edx
	movl	%eax, %edi
	movl	%r14d, %esi
	callq	_WREG32_P
LBB0_4:
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_IRQ_STATE_ENABLE,4,2    ## @AMDGPU_IRQ_STATE_ENABLE
	.comm	_VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK,4,2 ## @VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK
	.comm	_VCE,4,2                        ## @VCE
	.comm	_mmVCE_SYS_INT_EN,4,2           ## @mmVCE_SYS_INT_EN
	.no_dead_strip	_vce_v4_0_set_interrupt_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vce_v4_0_set_interrupt_state
_vce_v4_0_set_interrupt_state:          ; @vce_v4_0_set_interrupt_state
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x3
	bl	_amdgpu_sriov_vf
	cbnz	w0, LBB0_2
; %bb.1:
Lloh0:
	adrp	x8, _AMDGPU_IRQ_STATE_ENABLE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPU_IRQ_STATE_ENABLE@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x20, _VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK@GOTPAGE
Lloh4:
	ldr	x20, [x20, _VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK@GOTPAGEOFF]
	ldr	w9, [x20]
	cmp	w8, w19
	csel	w19, w9, wzr, eq
Lloh5:
	adrp	x8, _VCE@GOTPAGE
Lloh6:
	ldr	x8, [x8, _VCE@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
Lloh8:
	adrp	x8, _mmVCE_SYS_INT_EN@GOTPAGE
Lloh9:
	ldr	x8, [x8, _mmVCE_SYS_INT_EN@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x20]
	mvn	w2, w8
	mov	x1, x19
	bl	_WREG32_P
LBB0_2:
	mov	w0, #0
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_IRQ_STATE_ENABLE,4,2    ; @AMDGPU_IRQ_STATE_ENABLE
	.comm	_VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK,4,2 ; @VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK
	.comm	_VCE,4,2                        ; @VCE
	.comm	_mmVCE_SYS_INT_EN,4,2           ; @mmVCE_SYS_INT_EN
	.no_dead_strip	_vce_v4_0_set_interrupt_state
.subsections_via_symbols
