	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vi_need_reset_on_init
_vi_need_reset_on_init:                 ## @vi_need_reset_on_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%eax, %eax
	testl	%ecx, (%rdi)
	jne	LBB0_2
## %bb.1:
	movq	_ixSMC_SYSCON_CLOCK_CNTL_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_SMC
	movl	%eax, %ebx
	movq	_ixSMC_PC_C@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_SMC
	movl	%eax, %r14d
	movq	_SMC_SYSCON_CLOCK_CNTL_0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_ck_disable@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%ebx, %edi
	callq	_REG_GET_FIELD
	testq	%rax, %rax
	sete	%al
	cmpl	$131328, %r14d                  ## imm = 0x20100
	setge	%cl
	andb	%al, %cl
	movzbl	%cl, %eax
LBB0_2:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_ixSMC_SYSCON_CLOCK_CNTL_0,4,2  ## @ixSMC_SYSCON_CLOCK_CNTL_0
	.comm	_ixSMC_PC_C,4,2                 ## @ixSMC_PC_C
	.comm	_SMC_SYSCON_CLOCK_CNTL_0,4,2    ## @SMC_SYSCON_CLOCK_CNTL_0
	.comm	_ck_disable,4,2                 ## @ck_disable
	.no_dead_strip	_vi_need_reset_on_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vi_need_reset_on_init
_vi_need_reset_on_init:                 ; @vi_need_reset_on_init
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _AMD_IS_APU@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_IS_APU@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
	mov	w0, #0
	b	LBB0_3
LBB0_2:
Lloh3:
	adrp	x8, _ixSMC_SYSCON_CLOCK_CNTL_0@GOTPAGE
Lloh4:
	ldr	x8, [x8, _ixSMC_SYSCON_CLOCK_CNTL_0@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	bl	_RREG32_SMC
	mov	x19, x0
Lloh6:
	adrp	x8, _ixSMC_PC_C@GOTPAGE
Lloh7:
	ldr	x8, [x8, _ixSMC_PC_C@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	bl	_RREG32_SMC
	mov	x20, x0
Lloh9:
	adrp	x8, _SMC_SYSCON_CLOCK_CNTL_0@GOTPAGE
Lloh10:
	ldr	x8, [x8, _SMC_SYSCON_CLOCK_CNTL_0@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
Lloh12:
	adrp	x8, _ck_disable@GOTPAGE
Lloh13:
	ldr	x8, [x8, _ck_disable@GOTPAGEOFF]
Lloh14:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_REG_GET_FIELD
	cmp	x0, #0
	mov	w8, #255
	movk	w8, #2, lsl #16
	ccmp	w20, w8, #4, eq
	cset	w0, gt
LBB0_3:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_ixSMC_SYSCON_CLOCK_CNTL_0,4,2  ; @ixSMC_SYSCON_CLOCK_CNTL_0
	.comm	_ixSMC_PC_C,4,2                 ; @ixSMC_PC_C
	.comm	_SMC_SYSCON_CLOCK_CNTL_0,4,2    ; @SMC_SYSCON_CLOCK_CNTL_0
	.comm	_ck_disable,4,2                 ; @ck_disable
	.no_dead_strip	_vi_need_reset_on_init
.subsections_via_symbols
