	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mtk_hdmi_pll_set_rate
_mtk_hdmi_pll_set_rate:                 ## @mtk_hdmi_pll_set_rate
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %rbx
	callq	_to_mtk_hdmi_phy
	movq	%rax, %r12
	xorl	%r13d, %r13d
	cmpq	$128000001, %rbx                ## imm = 0x7A12001
	adcl	$1, %r13d
	cmpq	$64000001, %rbx                 ## imm = 0x3D09001
	movl	$3, %eax
	cmovbl	%eax, %r13d
	movq	_HDMI_CON6@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	_RG_HTPLL_PREDIV_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_mtk_hdmi_phy_set_bits
	movl	(%r14), %esi
	movq	_RG_HTPLL_POSDIV_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_mtk_hdmi_phy_set_bits
	movq	_HDMI_CON2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_RG_HDMITX_EN_TX_POSDIV@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_mtk_hdmi_phy_set_bits
	movq	_RG_HTPLL_IC@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$1, %edx
	shll	%cl, %edx
	movl	(%r14), %esi
	movl	$1, %r15d
	movq	_RG_HTPLL_IC_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r12, %rdi
	callq	_mtk_hdmi_phy_mask
	movq	_RG_HTPLL_IR@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$1, %edx
	shll	%cl, %edx
	movl	(%r14), %esi
	movq	_RG_HTPLL_IR_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r12, %rdi
	callq	_mtk_hdmi_phy_mask
	movq	_RG_HDMITX_TX_POSDIV@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r13d
	movl	(%rbx), %esi
	movq	_RG_HDMITX_TX_POSDIV_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r12, %rdi
	movl	%r13d, %edx
	callq	_mtk_hdmi_phy_mask
	movq	_RG_HTPLL_FBKSEL@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$1, %edx
	shll	%cl, %edx
	movl	(%r14), %esi
	movq	_RG_HTPLL_FBKSEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r12, %rdi
	callq	_mtk_hdmi_phy_mask
	movq	_RG_HTPLL_FBKDIV@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$19, %edx
	shll	%cl, %edx
	movl	(%r14), %esi
	movq	_RG_HTPLL_FBKDIV_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r12, %rdi
	callq	_mtk_hdmi_phy_mask
	movq	_HDMI_CON7@GOTPCREL(%rip), %rax
	movq	_RG_HTPLL_DIVEN@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %edx
	shll	%cl, %edx
	movl	(%rax), %esi
	movl	$2, %ebx
	movq	_RG_HTPLL_DIVEN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r12, %rdi
	callq	_mtk_hdmi_phy_mask
	movq	_RG_HTPLL_BP@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$12, %edx
	shll	%cl, %edx
	movl	(%r14), %esi
	movq	_RG_HTPLL_BP_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r12, %rdi
	callq	_mtk_hdmi_phy_mask
	movq	_RG_HTPLL_BC@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %ebx
	movl	(%r14), %esi
	movq	_RG_HTPLL_BC_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r12, %rdi
	movl	%ebx, %edx
	callq	_mtk_hdmi_phy_mask
	movq	_RG_HTPLL_BR@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r15d
	movl	(%r14), %esi
	movq	_RG_HTPLL_BR_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r12, %rdi
	movl	%r15d, %edx
	callq	_mtk_hdmi_phy_mask
	movq	_HDMI_CON1@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_RG_HDMITX_PRED_IMP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_mtk_hdmi_phy_clear_bits
	movq	_RG_HDMITX_PRED_IBIAS@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$3, %edx
	shll	%cl, %edx
	movl	(%rbx), %esi
	movq	_RG_HDMITX_PRED_IBIAS_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r12, %rdi
	callq	_mtk_hdmi_phy_mask
	movq	_HDMI_CON0@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	_RG_HDMITX_EN_IMP_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_mtk_hdmi_phy_clear_bits
	movq	_RG_HDMITX_DRV_IMP@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$40, %edx
	shll	%cl, %edx
	movl	(%rbx), %esi
	movq	_RG_HDMITX_DRV_IMP_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r12, %rdi
	callq	_mtk_hdmi_phy_mask
	movq	_HDMI_CON4@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_RG_HDMITX_RESERVE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r12, %rdi
	movl	$40, %edx
	callq	_mtk_hdmi_phy_mask
	movq	_RG_HDMITX_DRV_IBIAS@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$10, %edx
	shll	%cl, %edx
	movl	(%r14), %esi
	movq	_RG_HDMITX_DRV_IBIAS_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r12, %rdi
	callq	_mtk_hdmi_phy_mask
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_HDMI_CON6,4,2                  ## @HDMI_CON6
	.comm	_RG_HTPLL_PREDIV_MASK,4,2       ## @RG_HTPLL_PREDIV_MASK
	.comm	_RG_HTPLL_POSDIV_MASK,4,2       ## @RG_HTPLL_POSDIV_MASK
	.comm	_HDMI_CON2,4,2                  ## @HDMI_CON2
	.comm	_RG_HDMITX_EN_TX_POSDIV,4,2     ## @RG_HDMITX_EN_TX_POSDIV
	.comm	_RG_HTPLL_IC,4,2                ## @RG_HTPLL_IC
	.comm	_RG_HTPLL_IC_MASK,4,2           ## @RG_HTPLL_IC_MASK
	.comm	_RG_HTPLL_IR,4,2                ## @RG_HTPLL_IR
	.comm	_RG_HTPLL_IR_MASK,4,2           ## @RG_HTPLL_IR_MASK
	.comm	_RG_HDMITX_TX_POSDIV,4,2        ## @RG_HDMITX_TX_POSDIV
	.comm	_RG_HDMITX_TX_POSDIV_MASK,4,2   ## @RG_HDMITX_TX_POSDIV_MASK
	.comm	_RG_HTPLL_FBKSEL,4,2            ## @RG_HTPLL_FBKSEL
	.comm	_RG_HTPLL_FBKSEL_MASK,4,2       ## @RG_HTPLL_FBKSEL_MASK
	.comm	_RG_HTPLL_FBKDIV,4,2            ## @RG_HTPLL_FBKDIV
	.comm	_RG_HTPLL_FBKDIV_MASK,4,2       ## @RG_HTPLL_FBKDIV_MASK
	.comm	_HDMI_CON7,4,2                  ## @HDMI_CON7
	.comm	_RG_HTPLL_DIVEN,4,2             ## @RG_HTPLL_DIVEN
	.comm	_RG_HTPLL_DIVEN_MASK,4,2        ## @RG_HTPLL_DIVEN_MASK
	.comm	_RG_HTPLL_BP,4,2                ## @RG_HTPLL_BP
	.comm	_RG_HTPLL_BP_MASK,4,2           ## @RG_HTPLL_BP_MASK
	.comm	_RG_HTPLL_BC,4,2                ## @RG_HTPLL_BC
	.comm	_RG_HTPLL_BC_MASK,4,2           ## @RG_HTPLL_BC_MASK
	.comm	_RG_HTPLL_BR,4,2                ## @RG_HTPLL_BR
	.comm	_RG_HTPLL_BR_MASK,4,2           ## @RG_HTPLL_BR_MASK
	.comm	_HDMI_CON1,4,2                  ## @HDMI_CON1
	.comm	_RG_HDMITX_PRED_IMP,4,2         ## @RG_HDMITX_PRED_IMP
	.comm	_RG_HDMITX_PRED_IBIAS,4,2       ## @RG_HDMITX_PRED_IBIAS
	.comm	_RG_HDMITX_PRED_IBIAS_MASK,4,2  ## @RG_HDMITX_PRED_IBIAS_MASK
	.comm	_HDMI_CON0,4,2                  ## @HDMI_CON0
	.comm	_RG_HDMITX_EN_IMP_MASK,4,2      ## @RG_HDMITX_EN_IMP_MASK
	.comm	_RG_HDMITX_DRV_IMP,4,2          ## @RG_HDMITX_DRV_IMP
	.comm	_RG_HDMITX_DRV_IMP_MASK,4,2     ## @RG_HDMITX_DRV_IMP_MASK
	.comm	_HDMI_CON4,4,2                  ## @HDMI_CON4
	.comm	_RG_HDMITX_RESERVE_MASK,4,2     ## @RG_HDMITX_RESERVE_MASK
	.comm	_RG_HDMITX_DRV_IBIAS,4,2        ## @RG_HDMITX_DRV_IBIAS
	.comm	_RG_HDMITX_DRV_IBIAS_MASK,4,2   ## @RG_HDMITX_DRV_IBIAS_MASK
	.no_dead_strip	_mtk_hdmi_pll_set_rate
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mtk_hdmi_pll_set_rate
_mtk_hdmi_pll_set_rate:                 ; @mtk_hdmi_pll_set_rate
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x1
	bl	_to_mtk_hdmi_phy
	mov	x19, x0
	mov	w8, #8193
	movk	w8, #1953, lsl #16
	cmp	x20, x8
	mov	w21, #1
	cinc	w8, w21, lo
	mov	w9, #36865
	movk	w9, #976, lsl #16
	cmp	x20, x9
	mov	w20, #3
	csel	w23, w20, w8, lo
Lloh0:
	adrp	x22, _HDMI_CON6@GOTPAGE
Lloh1:
	ldr	x22, [x22, _HDMI_CON6@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh2:
	adrp	x8, _RG_HTPLL_PREDIV_MASK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _RG_HTPLL_PREDIV_MASK@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	bl	_mtk_hdmi_phy_set_bits
	ldr	w1, [x22]
Lloh5:
	adrp	x8, _RG_HTPLL_POSDIV_MASK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _RG_HTPLL_POSDIV_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mtk_hdmi_phy_set_bits
Lloh8:
	adrp	x24, _HDMI_CON2@GOTPAGE
Lloh9:
	ldr	x24, [x24, _HDMI_CON2@GOTPAGEOFF]
	ldr	w1, [x24]
Lloh10:
	adrp	x8, _RG_HDMITX_EN_TX_POSDIV@GOTPAGE
Lloh11:
	ldr	x8, [x8, _RG_HDMITX_EN_TX_POSDIV@GOTPAGEOFF]
Lloh12:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mtk_hdmi_phy_set_bits
Lloh13:
	adrp	x8, _RG_HTPLL_IC@GOTPAGE
Lloh14:
	ldr	x8, [x8, _RG_HTPLL_IC@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh15:
	ldr	w8, [x8]
	lsl	w2, w21, w8
Lloh16:
	adrp	x8, _RG_HTPLL_IC_MASK@GOTPAGE
Lloh17:
	ldr	x8, [x8, _RG_HTPLL_IC_MASK@GOTPAGEOFF]
Lloh18:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_mtk_hdmi_phy_mask
Lloh19:
	adrp	x8, _RG_HTPLL_IR@GOTPAGE
Lloh20:
	ldr	x8, [x8, _RG_HTPLL_IR@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh21:
	ldr	w8, [x8]
	lsl	w2, w21, w8
Lloh22:
	adrp	x8, _RG_HTPLL_IR_MASK@GOTPAGE
Lloh23:
	ldr	x8, [x8, _RG_HTPLL_IR_MASK@GOTPAGEOFF]
Lloh24:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_mtk_hdmi_phy_mask
Lloh25:
	adrp	x8, _RG_HDMITX_TX_POSDIV@GOTPAGE
Lloh26:
	ldr	x8, [x8, _RG_HDMITX_TX_POSDIV@GOTPAGEOFF]
	ldr	w1, [x24]
Lloh27:
	ldr	w8, [x8]
	lsl	w2, w23, w8
Lloh28:
	adrp	x8, _RG_HDMITX_TX_POSDIV_MASK@GOTPAGE
Lloh29:
	ldr	x8, [x8, _RG_HDMITX_TX_POSDIV_MASK@GOTPAGEOFF]
Lloh30:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_mtk_hdmi_phy_mask
Lloh31:
	adrp	x8, _RG_HTPLL_FBKSEL@GOTPAGE
Lloh32:
	ldr	x8, [x8, _RG_HTPLL_FBKSEL@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh33:
	ldr	w8, [x8]
	lsl	w2, w21, w8
Lloh34:
	adrp	x8, _RG_HTPLL_FBKSEL_MASK@GOTPAGE
Lloh35:
	ldr	x8, [x8, _RG_HTPLL_FBKSEL_MASK@GOTPAGEOFF]
Lloh36:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_mtk_hdmi_phy_mask
	ldr	w1, [x22]
Lloh37:
	adrp	x8, _RG_HTPLL_FBKDIV@GOTPAGE
Lloh38:
	ldr	x8, [x8, _RG_HTPLL_FBKDIV@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
	mov	w9, #19
	lsl	w2, w9, w8
Lloh40:
	adrp	x8, _RG_HTPLL_FBKDIV_MASK@GOTPAGE
Lloh41:
	ldr	x8, [x8, _RG_HTPLL_FBKDIV_MASK@GOTPAGEOFF]
Lloh42:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_mtk_hdmi_phy_mask
Lloh43:
	adrp	x8, _HDMI_CON7@GOTPAGE
Lloh44:
	ldr	x8, [x8, _HDMI_CON7@GOTPAGEOFF]
Lloh45:
	ldr	w1, [x8]
Lloh46:
	adrp	x8, _RG_HTPLL_DIVEN@GOTPAGE
Lloh47:
	ldr	x8, [x8, _RG_HTPLL_DIVEN@GOTPAGEOFF]
Lloh48:
	ldr	w8, [x8]
	mov	w23, #2
	lsl	w2, w23, w8
Lloh49:
	adrp	x8, _RG_HTPLL_DIVEN_MASK@GOTPAGE
Lloh50:
	ldr	x8, [x8, _RG_HTPLL_DIVEN_MASK@GOTPAGEOFF]
Lloh51:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_mtk_hdmi_phy_mask
	ldr	w1, [x22]
Lloh52:
	adrp	x8, _RG_HTPLL_BP@GOTPAGE
Lloh53:
	ldr	x8, [x8, _RG_HTPLL_BP@GOTPAGEOFF]
Lloh54:
	ldr	w8, [x8]
	mov	w9, #12
	lsl	w2, w9, w8
Lloh55:
	adrp	x8, _RG_HTPLL_BP_MASK@GOTPAGE
Lloh56:
	ldr	x8, [x8, _RG_HTPLL_BP_MASK@GOTPAGEOFF]
Lloh57:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_mtk_hdmi_phy_mask
Lloh58:
	adrp	x8, _RG_HTPLL_BC@GOTPAGE
Lloh59:
	ldr	x8, [x8, _RG_HTPLL_BC@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh60:
	ldr	w8, [x8]
	lsl	w2, w23, w8
Lloh61:
	adrp	x8, _RG_HTPLL_BC_MASK@GOTPAGE
Lloh62:
	ldr	x8, [x8, _RG_HTPLL_BC_MASK@GOTPAGEOFF]
Lloh63:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_mtk_hdmi_phy_mask
Lloh64:
	adrp	x8, _RG_HTPLL_BR@GOTPAGE
Lloh65:
	ldr	x8, [x8, _RG_HTPLL_BR@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh66:
	ldr	w8, [x8]
	lsl	w2, w21, w8
Lloh67:
	adrp	x8, _RG_HTPLL_BR_MASK@GOTPAGE
Lloh68:
	ldr	x8, [x8, _RG_HTPLL_BR_MASK@GOTPAGEOFF]
Lloh69:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_mtk_hdmi_phy_mask
Lloh70:
	adrp	x21, _HDMI_CON1@GOTPAGE
Lloh71:
	ldr	x21, [x21, _HDMI_CON1@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh72:
	adrp	x8, _RG_HDMITX_PRED_IMP@GOTPAGE
Lloh73:
	ldr	x8, [x8, _RG_HDMITX_PRED_IMP@GOTPAGEOFF]
Lloh74:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mtk_hdmi_phy_clear_bits
Lloh75:
	adrp	x8, _RG_HDMITX_PRED_IBIAS@GOTPAGE
Lloh76:
	ldr	x8, [x8, _RG_HDMITX_PRED_IBIAS@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh77:
	ldr	w8, [x8]
	lsl	w2, w20, w8
Lloh78:
	adrp	x8, _RG_HDMITX_PRED_IBIAS_MASK@GOTPAGE
Lloh79:
	ldr	x8, [x8, _RG_HDMITX_PRED_IBIAS_MASK@GOTPAGEOFF]
Lloh80:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_mtk_hdmi_phy_mask
Lloh81:
	adrp	x20, _HDMI_CON0@GOTPAGE
Lloh82:
	ldr	x20, [x20, _HDMI_CON0@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh83:
	adrp	x8, _RG_HDMITX_EN_IMP_MASK@GOTPAGE
Lloh84:
	ldr	x8, [x8, _RG_HDMITX_EN_IMP_MASK@GOTPAGEOFF]
Lloh85:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mtk_hdmi_phy_clear_bits
	ldr	w1, [x21]
Lloh86:
	adrp	x8, _RG_HDMITX_DRV_IMP@GOTPAGE
Lloh87:
	ldr	x8, [x8, _RG_HDMITX_DRV_IMP@GOTPAGEOFF]
Lloh88:
	ldr	w8, [x8]
	mov	w9, #40
	lsl	w2, w9, w8
Lloh89:
	adrp	x8, _RG_HDMITX_DRV_IMP_MASK@GOTPAGE
Lloh90:
	ldr	x8, [x8, _RG_HDMITX_DRV_IMP_MASK@GOTPAGEOFF]
Lloh91:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_mtk_hdmi_phy_mask
Lloh92:
	adrp	x8, _HDMI_CON4@GOTPAGE
Lloh93:
	ldr	x8, [x8, _HDMI_CON4@GOTPAGEOFF]
Lloh94:
	ldr	w1, [x8]
Lloh95:
	adrp	x8, _RG_HDMITX_RESERVE_MASK@GOTPAGE
Lloh96:
	ldr	x8, [x8, _RG_HDMITX_RESERVE_MASK@GOTPAGEOFF]
Lloh97:
	ldr	w3, [x8]
	mov	x0, x19
	mov	w2, #40
	bl	_mtk_hdmi_phy_mask
	ldr	w1, [x20]
Lloh98:
	adrp	x8, _RG_HDMITX_DRV_IBIAS@GOTPAGE
Lloh99:
	ldr	x8, [x8, _RG_HDMITX_DRV_IBIAS@GOTPAGEOFF]
Lloh100:
	ldr	w8, [x8]
	mov	w9, #10
	lsl	w2, w9, w8
Lloh101:
	adrp	x8, _RG_HDMITX_DRV_IBIAS_MASK@GOTPAGE
Lloh102:
	ldr	x8, [x8, _RG_HDMITX_DRV_IBIAS_MASK@GOTPAGEOFF]
Lloh103:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_mtk_hdmi_phy_mask
	mov	w0, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGot	Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGot	Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_HDMI_CON6,4,2                  ; @HDMI_CON6
	.comm	_RG_HTPLL_PREDIV_MASK,4,2       ; @RG_HTPLL_PREDIV_MASK
	.comm	_RG_HTPLL_POSDIV_MASK,4,2       ; @RG_HTPLL_POSDIV_MASK
	.comm	_HDMI_CON2,4,2                  ; @HDMI_CON2
	.comm	_RG_HDMITX_EN_TX_POSDIV,4,2     ; @RG_HDMITX_EN_TX_POSDIV
	.comm	_RG_HTPLL_IC,4,2                ; @RG_HTPLL_IC
	.comm	_RG_HTPLL_IC_MASK,4,2           ; @RG_HTPLL_IC_MASK
	.comm	_RG_HTPLL_IR,4,2                ; @RG_HTPLL_IR
	.comm	_RG_HTPLL_IR_MASK,4,2           ; @RG_HTPLL_IR_MASK
	.comm	_RG_HDMITX_TX_POSDIV,4,2        ; @RG_HDMITX_TX_POSDIV
	.comm	_RG_HDMITX_TX_POSDIV_MASK,4,2   ; @RG_HDMITX_TX_POSDIV_MASK
	.comm	_RG_HTPLL_FBKSEL,4,2            ; @RG_HTPLL_FBKSEL
	.comm	_RG_HTPLL_FBKSEL_MASK,4,2       ; @RG_HTPLL_FBKSEL_MASK
	.comm	_RG_HTPLL_FBKDIV,4,2            ; @RG_HTPLL_FBKDIV
	.comm	_RG_HTPLL_FBKDIV_MASK,4,2       ; @RG_HTPLL_FBKDIV_MASK
	.comm	_HDMI_CON7,4,2                  ; @HDMI_CON7
	.comm	_RG_HTPLL_DIVEN,4,2             ; @RG_HTPLL_DIVEN
	.comm	_RG_HTPLL_DIVEN_MASK,4,2        ; @RG_HTPLL_DIVEN_MASK
	.comm	_RG_HTPLL_BP,4,2                ; @RG_HTPLL_BP
	.comm	_RG_HTPLL_BP_MASK,4,2           ; @RG_HTPLL_BP_MASK
	.comm	_RG_HTPLL_BC,4,2                ; @RG_HTPLL_BC
	.comm	_RG_HTPLL_BC_MASK,4,2           ; @RG_HTPLL_BC_MASK
	.comm	_RG_HTPLL_BR,4,2                ; @RG_HTPLL_BR
	.comm	_RG_HTPLL_BR_MASK,4,2           ; @RG_HTPLL_BR_MASK
	.comm	_HDMI_CON1,4,2                  ; @HDMI_CON1
	.comm	_RG_HDMITX_PRED_IMP,4,2         ; @RG_HDMITX_PRED_IMP
	.comm	_RG_HDMITX_PRED_IBIAS,4,2       ; @RG_HDMITX_PRED_IBIAS
	.comm	_RG_HDMITX_PRED_IBIAS_MASK,4,2  ; @RG_HDMITX_PRED_IBIAS_MASK
	.comm	_HDMI_CON0,4,2                  ; @HDMI_CON0
	.comm	_RG_HDMITX_EN_IMP_MASK,4,2      ; @RG_HDMITX_EN_IMP_MASK
	.comm	_RG_HDMITX_DRV_IMP,4,2          ; @RG_HDMITX_DRV_IMP
	.comm	_RG_HDMITX_DRV_IMP_MASK,4,2     ; @RG_HDMITX_DRV_IMP_MASK
	.comm	_HDMI_CON4,4,2                  ; @HDMI_CON4
	.comm	_RG_HDMITX_RESERVE_MASK,4,2     ; @RG_HDMITX_RESERVE_MASK
	.comm	_RG_HDMITX_DRV_IBIAS,4,2        ; @RG_HDMITX_DRV_IBIAS
	.comm	_RG_HDMITX_DRV_IBIAS_MASK,4,2   ; @RG_HDMITX_DRV_IBIAS_MASK
	.no_dead_strip	_mtk_hdmi_pll_set_rate
.subsections_via_symbols
