	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r100_set_common_regs           ## -- Begin function r100_set_common_regs
	.p2align	4, 0x90
_r100_set_common_regs:                  ## @r100_set_common_regs
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	(%rdi), %rbx
	movq	_RADEON_OV0_SCALE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_RADEON_SUBPIC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_RADEON_VIPH_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_RADEON_I2C_CNTL_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_RADEON_DVI_I2C_CNTL_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_RADEON_CAP0_TRIG_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_RADEON_CAP1_TRIG_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%rbx), %rax
	movl	(%rax), %ecx
	leal	-20825(%rcx), %edx
	cmpl	$2, %edx
	jb	LBB0_3
## %bb.1:
	cmpl	$20830, %ecx                    ## imm = 0x515E
	je	LBB0_6
## %bb.2:
	cmpl	$22889, %ecx                    ## imm = 0x5969
	je	LBB0_6
	jmp	LBB0_7
LBB0_3:
	cmpl	$4136, 4(%rax)                  ## imm = 0x1028
	jne	LBB0_7
## %bb.4:
	movl	$-364, %ecx                     ## imm = 0xFE94
	addl	8(%rax), %ecx
	cmpl	$46, %ecx
	ja	LBB0_7
## %bb.5:
	movabsq	$70369826701343, %rax           ## imm = 0x40004086001F
	btq	%rcx, %rax
	jae	LBB0_7
LBB0_6:
	movq	_RADEON_DISP_HW_DEBUG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r14d
	movq	_RADEON_TV_DAC_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_RREG32
	movl	%eax, %r15d
	movq	_RADEON_DAC_CNTL2@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_RREG32
	movq	_RADEON_DAC2_DAC_CLK_SEL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movq	_RADEON_DAC2_DAC2_CLK_SEL@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_RADEON_CRT2_DISP1_SEL@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
	movq	_RADEON_TV_DAC_PEDESTAL@GOTPCREL(%rip), %rcx
	movq	_RADEON_TV_DAC_STD_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	(%rcx), %eax
	movq	_RADEON_TV_DAC_RDACPD@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_TV_DAC_GDACPD@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_TV_DAC_BDACPD@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_TV_DAC_BGADJ_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_TV_DAC_DACADJ_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	notl	%eax
	andl	%r15d, %eax
	movq	_RADEON_TV_DAC_NBLANK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_RADEON_TV_DAC_NHOLD@GOTPCREL(%rip), %rcx
	movq	_RADEON_TV_DAC_STD_PS2@GOTPCREL(%rip), %rdx
	orl	(%rcx), %esi
	orl	%eax, %esi
	orl	(%rdx), %esi
	orl	$5767168, %esi                  ## imm = 0x580000
	movl	(%r12), %edi
	callq	_WREG32
	movq	_RADEON_DISP_HW_DEBUG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movl	(%r13), %edi
	movl	%ebx, %esi
	callq	_WREG32
LBB0_7:
	movq	_RADEON_PLL_PWRMGT_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_PM_MODE_SEL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_PLL                     ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_OV0_SCALE_CNTL,4,2      ## @RADEON_OV0_SCALE_CNTL
	.comm	_RADEON_SUBPIC_CNTL,4,2         ## @RADEON_SUBPIC_CNTL
	.comm	_RADEON_VIPH_CONTROL,4,2        ## @RADEON_VIPH_CONTROL
	.comm	_RADEON_I2C_CNTL_1,4,2          ## @RADEON_I2C_CNTL_1
	.comm	_RADEON_DVI_I2C_CNTL_1,4,2      ## @RADEON_DVI_I2C_CNTL_1
	.comm	_RADEON_CAP0_TRIG_CNTL,4,2      ## @RADEON_CAP0_TRIG_CNTL
	.comm	_RADEON_CAP1_TRIG_CNTL,4,2      ## @RADEON_CAP1_TRIG_CNTL
	.comm	_RADEON_DISP_HW_DEBUG,4,2       ## @RADEON_DISP_HW_DEBUG
	.comm	_RADEON_TV_DAC_CNTL,4,2         ## @RADEON_TV_DAC_CNTL
	.comm	_RADEON_DAC_CNTL2,4,2           ## @RADEON_DAC_CNTL2
	.comm	_RADEON_DAC2_DAC_CLK_SEL,4,2    ## @RADEON_DAC2_DAC_CLK_SEL
	.comm	_RADEON_DAC2_DAC2_CLK_SEL,4,2   ## @RADEON_DAC2_DAC2_CLK_SEL
	.comm	_RADEON_CRT2_DISP1_SEL,4,2      ## @RADEON_CRT2_DISP1_SEL
	.comm	_RADEON_TV_DAC_PEDESTAL,4,2     ## @RADEON_TV_DAC_PEDESTAL
	.comm	_RADEON_TV_DAC_STD_MASK,4,2     ## @RADEON_TV_DAC_STD_MASK
	.comm	_RADEON_TV_DAC_RDACPD,4,2       ## @RADEON_TV_DAC_RDACPD
	.comm	_RADEON_TV_DAC_GDACPD,4,2       ## @RADEON_TV_DAC_GDACPD
	.comm	_RADEON_TV_DAC_BDACPD,4,2       ## @RADEON_TV_DAC_BDACPD
	.comm	_RADEON_TV_DAC_BGADJ_MASK,4,2   ## @RADEON_TV_DAC_BGADJ_MASK
	.comm	_RADEON_TV_DAC_DACADJ_MASK,4,2  ## @RADEON_TV_DAC_DACADJ_MASK
	.comm	_RADEON_TV_DAC_NBLANK,4,2       ## @RADEON_TV_DAC_NBLANK
	.comm	_RADEON_TV_DAC_NHOLD,4,2        ## @RADEON_TV_DAC_NHOLD
	.comm	_RADEON_TV_DAC_STD_PS2,4,2      ## @RADEON_TV_DAC_STD_PS2
	.comm	_RADEON_PLL_PWRMGT_CNTL,4,2     ## @RADEON_PLL_PWRMGT_CNTL
	.comm	_RADEON_PM_MODE_SEL,4,2         ## @RADEON_PM_MODE_SEL
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r100_set_common_regs           ; -- Begin function r100_set_common_regs
	.p2align	2
_r100_set_common_regs:                  ; @r100_set_common_regs
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	ldr	x19, [x0]
Lloh0:
	adrp	x8, _RADEON_OV0_SCALE_CNTL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_OV0_SCALE_CNTL@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh3:
	adrp	x8, _RADEON_SUBPIC_CNTL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _RADEON_SUBPIC_CNTL@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh6:
	adrp	x8, _RADEON_VIPH_CONTROL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_VIPH_CONTROL@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh9:
	adrp	x8, _RADEON_I2C_CNTL_1@GOTPAGE
Lloh10:
	ldr	x8, [x8, _RADEON_I2C_CNTL_1@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh12:
	adrp	x8, _RADEON_DVI_I2C_CNTL_1@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RADEON_DVI_I2C_CNTL_1@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh15:
	adrp	x8, _RADEON_CAP0_TRIG_CNTL@GOTPAGE
Lloh16:
	ldr	x8, [x8, _RADEON_CAP0_TRIG_CNTL@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh18:
	adrp	x8, _RADEON_CAP1_TRIG_CNTL@GOTPAGE
Lloh19:
	ldr	x8, [x8, _RADEON_CAP1_TRIG_CNTL@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x19]
	ldr	w9, [x8]
	mov	w10, #-20825
	add	w10, w9, w10
	cmp	w10, #2
	b.lo	LBB0_2
; %bb.1:
	mov	w8, #20830
	cmp	w9, w8
	mov	w8, #22889
	ccmp	w9, w8, #4, ne
	b.eq	LBB0_4
	b	LBB0_5
LBB0_2:
	ldr	w9, [x8, #4]
	mov	w10, #4136
	cmp	w9, w10
	b.ne	LBB0_5
; %bb.3:
	ldr	w8, [x8, #8]
	sub	w8, w8, #364
	cmp	w8, #46
	mov	w9, #1
	lsl	x8, x9, x8
	mov	x9, #31
	movk	x9, #16518, lsl #16
	movk	x9, #16384, lsl #32
	and	x8, x8, x9
	ccmp	x8, #0, #4, ls
	b.eq	LBB0_5
LBB0_4:
Lloh21:
	adrp	x22, _RADEON_DISP_HW_DEBUG@GOTPAGE
Lloh22:
	ldr	x22, [x22, _RADEON_DISP_HW_DEBUG@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_RREG32
	mov	x19, x0
Lloh23:
	adrp	x24, _RADEON_TV_DAC_CNTL@GOTPAGE
Lloh24:
	ldr	x24, [x24, _RADEON_TV_DAC_CNTL@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_RREG32
	mov	x20, x0
Lloh25:
	adrp	x23, _RADEON_DAC_CNTL2@GOTPAGE
Lloh26:
	ldr	x23, [x23, _RADEON_DAC_CNTL2@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32
Lloh27:
	adrp	x8, _RADEON_DAC2_DAC_CLK_SEL@GOTPAGE
Lloh28:
	ldr	x8, [x8, _RADEON_DAC2_DAC_CLK_SEL@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh30:
	adrp	x9, _RADEON_DAC2_DAC2_CLK_SEL@GOTPAGE
Lloh31:
	ldr	x9, [x9, _RADEON_DAC2_DAC2_CLK_SEL@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	orr	w21, w8, w9
Lloh33:
	adrp	x8, _RADEON_CRT2_DISP1_SEL@GOTPAGE
Lloh34:
	ldr	x8, [x8, _RADEON_CRT2_DISP1_SEL@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
Lloh36:
	adrp	x9, _RADEON_TV_DAC_PEDESTAL@GOTPAGE
Lloh37:
	ldr	x9, [x9, _RADEON_TV_DAC_PEDESTAL@GOTPAGEOFF]
	orr	w19, w8, w19
Lloh38:
	ldr	w8, [x9]
Lloh39:
	adrp	x9, _RADEON_TV_DAC_STD_MASK@GOTPAGE
Lloh40:
	ldr	x9, [x9, _RADEON_TV_DAC_STD_MASK@GOTPAGEOFF]
Lloh41:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh42:
	adrp	x9, _RADEON_TV_DAC_RDACPD@GOTPAGE
Lloh43:
	ldr	x9, [x9, _RADEON_TV_DAC_RDACPD@GOTPAGEOFF]
Lloh44:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh45:
	adrp	x9, _RADEON_TV_DAC_GDACPD@GOTPAGE
Lloh46:
	ldr	x9, [x9, _RADEON_TV_DAC_GDACPD@GOTPAGEOFF]
Lloh47:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh48:
	adrp	x9, _RADEON_TV_DAC_BDACPD@GOTPAGE
Lloh49:
	ldr	x9, [x9, _RADEON_TV_DAC_BDACPD@GOTPAGEOFF]
Lloh50:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh51:
	adrp	x9, _RADEON_TV_DAC_BGADJ_MASK@GOTPAGE
Lloh52:
	ldr	x9, [x9, _RADEON_TV_DAC_BGADJ_MASK@GOTPAGEOFF]
Lloh53:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh54:
	adrp	x9, _RADEON_TV_DAC_DACADJ_MASK@GOTPAGE
Lloh55:
	ldr	x9, [x9, _RADEON_TV_DAC_DACADJ_MASK@GOTPAGEOFF]
Lloh56:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w8, w20, w8
Lloh57:
	adrp	x9, _RADEON_TV_DAC_NBLANK@GOTPAGE
Lloh58:
	ldr	x9, [x9, _RADEON_TV_DAC_NBLANK@GOTPAGEOFF]
Lloh59:
	ldr	w9, [x9]
Lloh60:
	adrp	x10, _RADEON_TV_DAC_NHOLD@GOTPAGE
Lloh61:
	ldr	x10, [x10, _RADEON_TV_DAC_NHOLD@GOTPAGEOFF]
Lloh62:
	ldr	w10, [x10]
Lloh63:
	adrp	x11, _RADEON_TV_DAC_STD_PS2@GOTPAGE
Lloh64:
	ldr	x11, [x11, _RADEON_TV_DAC_STD_PS2@GOTPAGEOFF]
Lloh65:
	ldr	w11, [x11]
	orr	w9, w9, w10
	orr	w8, w9, w8
	orr	w8, w8, w11
	mov	w9, #5767168
	orr	w1, w8, w9
	ldr	w0, [x24]
	bl	_WREG32
	ldr	w0, [x22]
	mov	x1, x19
	bl	_WREG32
	ldr	w0, [x23]
	mov	x1, x21
	bl	_WREG32
LBB0_5:
Lloh66:
	adrp	x19, _RADEON_PLL_PWRMGT_CNTL@GOTPAGE
Lloh67:
	ldr	x19, [x19, _RADEON_PLL_PWRMGT_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh68:
	adrp	x8, _RADEON_PM_MODE_SEL@GOTPAGE
Lloh69:
	ldr	x8, [x8, _RADEON_PM_MODE_SEL@GOTPAGEOFF]
Lloh70:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w0, [x19]
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_WREG32_PLL
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGot	Lloh66, Lloh67
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_OV0_SCALE_CNTL,4,2      ; @RADEON_OV0_SCALE_CNTL
	.comm	_RADEON_SUBPIC_CNTL,4,2         ; @RADEON_SUBPIC_CNTL
	.comm	_RADEON_VIPH_CONTROL,4,2        ; @RADEON_VIPH_CONTROL
	.comm	_RADEON_I2C_CNTL_1,4,2          ; @RADEON_I2C_CNTL_1
	.comm	_RADEON_DVI_I2C_CNTL_1,4,2      ; @RADEON_DVI_I2C_CNTL_1
	.comm	_RADEON_CAP0_TRIG_CNTL,4,2      ; @RADEON_CAP0_TRIG_CNTL
	.comm	_RADEON_CAP1_TRIG_CNTL,4,2      ; @RADEON_CAP1_TRIG_CNTL
	.comm	_RADEON_DISP_HW_DEBUG,4,2       ; @RADEON_DISP_HW_DEBUG
	.comm	_RADEON_TV_DAC_CNTL,4,2         ; @RADEON_TV_DAC_CNTL
	.comm	_RADEON_DAC_CNTL2,4,2           ; @RADEON_DAC_CNTL2
	.comm	_RADEON_DAC2_DAC_CLK_SEL,4,2    ; @RADEON_DAC2_DAC_CLK_SEL
	.comm	_RADEON_DAC2_DAC2_CLK_SEL,4,2   ; @RADEON_DAC2_DAC2_CLK_SEL
	.comm	_RADEON_CRT2_DISP1_SEL,4,2      ; @RADEON_CRT2_DISP1_SEL
	.comm	_RADEON_TV_DAC_PEDESTAL,4,2     ; @RADEON_TV_DAC_PEDESTAL
	.comm	_RADEON_TV_DAC_STD_MASK,4,2     ; @RADEON_TV_DAC_STD_MASK
	.comm	_RADEON_TV_DAC_RDACPD,4,2       ; @RADEON_TV_DAC_RDACPD
	.comm	_RADEON_TV_DAC_GDACPD,4,2       ; @RADEON_TV_DAC_GDACPD
	.comm	_RADEON_TV_DAC_BDACPD,4,2       ; @RADEON_TV_DAC_BDACPD
	.comm	_RADEON_TV_DAC_BGADJ_MASK,4,2   ; @RADEON_TV_DAC_BGADJ_MASK
	.comm	_RADEON_TV_DAC_DACADJ_MASK,4,2  ; @RADEON_TV_DAC_DACADJ_MASK
	.comm	_RADEON_TV_DAC_NBLANK,4,2       ; @RADEON_TV_DAC_NBLANK
	.comm	_RADEON_TV_DAC_NHOLD,4,2        ; @RADEON_TV_DAC_NHOLD
	.comm	_RADEON_TV_DAC_STD_PS2,4,2      ; @RADEON_TV_DAC_STD_PS2
	.comm	_RADEON_PLL_PWRMGT_CNTL,4,2     ; @RADEON_PLL_PWRMGT_CNTL
	.comm	_RADEON_PM_MODE_SEL,4,2         ; @RADEON_PM_MODE_SEL
.subsections_via_symbols
