	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function icl_update_active_dpll
_icl_update_active_dpll:                ## @icl_update_active_dpll
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %rbx
	callq	_intel_atomic_get_new_crtc_state
	movq	%rax, %r14
	movq	_ICL_PORT_DPLL_DEFAULT@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	(%rbx), %rax
	movq	_INTEL_OUTPUT_DP_MST@GOTPCREL(%rip), %rcx
	addq	$8, %rbx
	cmpq	(%rcx), %rax
	jne	LBB0_2
## %bb.1:
	movq	%rbx, %rdi
	callq	_enc_to_mst
	movq	(%rax), %rax
	testq	%rax, %rax
	jne	LBB0_4
	jmp	LBB0_5
LBB0_2:
	movq	%rbx, %rdi
	callq	_enc_to_dig_port
	testq	%rax, %rax
	je	LBB0_5
LBB0_4:
	movq	(%rax), %rax
	movq	_TC_PORT_DP_ALT@GOTPCREL(%rip), %rcx
	movq	_TC_PORT_LEGACY@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rax
	movq	_ICL_PORT_DPLL_MG_PHY@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	cmovel	%edx, %r15d
	cmpq	(%rcx), %rax
	cmovel	%edx, %r15d
LBB0_5:
	movq	%r14, %rdi
	movl	%r15d, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_icl_set_active_port_dpll       ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_ICL_PORT_DPLL_DEFAULT,4,2      ## @ICL_PORT_DPLL_DEFAULT
	.comm	_INTEL_OUTPUT_DP_MST,8,3        ## @INTEL_OUTPUT_DP_MST
	.comm	_TC_PORT_DP_ALT,8,3             ## @TC_PORT_DP_ALT
	.comm	_TC_PORT_LEGACY,8,3             ## @TC_PORT_LEGACY
	.comm	_ICL_PORT_DPLL_MG_PHY,4,2       ## @ICL_PORT_DPLL_MG_PHY
	.no_dead_strip	_icl_update_active_dpll
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function icl_update_active_dpll
_icl_update_active_dpll:                ; @icl_update_active_dpll
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x21, x2
	bl	_intel_atomic_get_new_crtc_state
	mov	x19, x0
Lloh0:
	adrp	x8, _ICL_PORT_DPLL_DEFAULT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _ICL_PORT_DPLL_DEFAULT@GOTPAGEOFF]
Lloh2:
	ldr	w20, [x8]
	ldr	x8, [x21], #8
Lloh3:
	adrp	x9, _INTEL_OUTPUT_DP_MST@GOTPAGE
Lloh4:
	ldr	x9, [x9, _INTEL_OUTPUT_DP_MST@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
	mov	x0, x21
	cmp	x8, x9
	b.ne	LBB0_2
; %bb.1:
	bl	_enc_to_mst
	ldr	x0, [x0]
	cbnz	x0, LBB0_3
	b	LBB0_4
LBB0_2:
	bl	_enc_to_dig_port
	cbz	x0, LBB0_4
LBB0_3:
	ldr	x8, [x0]
Lloh6:
	adrp	x9, _TC_PORT_DP_ALT@GOTPAGE
Lloh7:
	ldr	x9, [x9, _TC_PORT_DP_ALT@GOTPAGEOFF]
Lloh8:
	ldr	x9, [x9]
Lloh9:
	adrp	x10, _TC_PORT_LEGACY@GOTPAGE
Lloh10:
	ldr	x10, [x10, _TC_PORT_LEGACY@GOTPAGEOFF]
Lloh11:
	ldr	x10, [x10]
	cmp	x8, x10
	ccmp	x8, x9, #4, ne
Lloh12:
	adrp	x8, _ICL_PORT_DPLL_MG_PHY@GOTPAGE
Lloh13:
	ldr	x8, [x8, _ICL_PORT_DPLL_MG_PHY@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	csel	w20, w8, w20, eq
LBB0_4:
	mov	x0, x19
	mov	x1, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_icl_set_active_port_dpll
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_ICL_PORT_DPLL_DEFAULT,4,2      ; @ICL_PORT_DPLL_DEFAULT
	.comm	_INTEL_OUTPUT_DP_MST,8,3        ; @INTEL_OUTPUT_DP_MST
	.comm	_TC_PORT_DP_ALT,8,3             ; @TC_PORT_DP_ALT
	.comm	_TC_PORT_LEGACY,8,3             ; @TC_PORT_LEGACY
	.comm	_ICL_PORT_DPLL_MG_PHY,4,2       ; @ICL_PORT_DPLL_MG_PHY
	.no_dead_strip	_icl_update_active_dpll
.subsections_via_symbols
