	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_legacy_get_engine_clock ## -- Begin function radeon_legacy_get_engine_clock
	.p2align	4, 0x90
_radeon_legacy_get_engine_clock:        ## @radeon_legacy_get_engine_clock
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	_RADEON_M_SPLL_REF_FB_DIV@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_RREG32_PLL
	movl	%eax, %ebx
	movq	_RADEON_SPLL_FB_DIV_SHIFT@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_RADEON_SPLL_FB_DIV_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	(%r15), %r15d
	movl	(%r13), %edi
	callq	_RREG32_PLL
	movl	%eax, %esi
	movq	_RADEON_M_SPLL_REF_DIV_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %esi
	je	LBB0_1
## %bb.2:
	movl	%r14d, %ecx
	sarl	%cl, %ebx
	andl	%r12d, %ebx
	imull	%r15d, %ebx
	addl	%ebx, %ebx
	movl	%ebx, %eax
	cltd
	idivl	%esi
	movl	%eax, %ebx
	movq	_RADEON_SCLK_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PLL
	movq	_RADEON_SCLK_SRC_SEL_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	cmpl	$4, %eax
	je	LBB0_7
## %bb.3:
	cmpl	$3, %eax
	je	LBB0_6
## %bb.4:
	cmpl	$2, %eax
	jne	LBB0_8
## %bb.5:
	sarl	%ebx
	jmp	LBB0_8
LBB0_1:
	xorl	%ebx, %ebx
	jmp	LBB0_8
LBB0_7:
	sarl	$3, %ebx
	jmp	LBB0_8
LBB0_6:
	sarl	$2, %ebx
LBB0_8:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_M_SPLL_REF_FB_DIV,4,2   ## @RADEON_M_SPLL_REF_FB_DIV
	.comm	_RADEON_SPLL_FB_DIV_SHIFT,4,2   ## @RADEON_SPLL_FB_DIV_SHIFT
	.comm	_RADEON_SPLL_FB_DIV_MASK,4,2    ## @RADEON_SPLL_FB_DIV_MASK
	.comm	_RADEON_M_SPLL_REF_DIV_MASK,4,2 ## @RADEON_M_SPLL_REF_DIV_MASK
	.comm	_RADEON_SCLK_CNTL,4,2           ## @RADEON_SCLK_CNTL
	.comm	_RADEON_SCLK_SRC_SEL_MASK,4,2   ## @RADEON_SCLK_SRC_SEL_MASK
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_legacy_get_engine_clock ; -- Begin function radeon_legacy_get_engine_clock
	.p2align	2
_radeon_legacy_get_engine_clock:        ; @radeon_legacy_get_engine_clock
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x0
Lloh0:
	adrp	x23, _RADEON_M_SPLL_REF_FB_DIV@GOTPAGE
Lloh1:
	ldr	x23, [x23, _RADEON_M_SPLL_REF_FB_DIV@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32_PLL
	mov	x19, x0
Lloh2:
	adrp	x8, _RADEON_SPLL_FB_DIV_SHIFT@GOTPAGE
Lloh3:
	ldr	x8, [x8, _RADEON_SPLL_FB_DIV_SHIFT@GOTPAGEOFF]
Lloh4:
	ldr	w21, [x8]
Lloh5:
	adrp	x8, _RADEON_SPLL_FB_DIV_MASK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _RADEON_SPLL_FB_DIV_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w22, [x8]
	ldr	w20, [x20]
	ldr	w0, [x23]
	bl	_RREG32_PLL
Lloh8:
	adrp	x8, _RADEON_M_SPLL_REF_DIV_MASK@GOTPAGE
Lloh9:
	ldr	x8, [x8, _RADEON_M_SPLL_REF_DIV_MASK@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	ands	w8, w8, w0
	b.eq	LBB0_5
; %bb.1:
	asr	w9, w19, w21
	and	w9, w9, w22
	mul	w9, w9, w20
	lsl	w9, w9, #1
Lloh11:
	adrp	x10, _RADEON_SCLK_CNTL@GOTPAGE
Lloh12:
	ldr	x10, [x10, _RADEON_SCLK_CNTL@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x10]
	sdiv	w19, w9, w8
	bl	_RREG32_PLL
Lloh14:
	adrp	x8, _RADEON_SCLK_SRC_SEL_MASK@GOTPAGE
Lloh15:
	ldr	x8, [x8, _RADEON_SCLK_SRC_SEL_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
	and	w8, w8, w0
	cmp	w8, #4
	b.eq	LBB0_6
; %bb.2:
	cmp	w8, #3
	b.eq	LBB0_7
; %bb.3:
	cmp	w8, #2
	b.ne	LBB0_8
; %bb.4:
	asr	w19, w19, #1
	b	LBB0_8
LBB0_5:
	mov	w19, #0
	b	LBB0_8
LBB0_6:
	asr	w19, w19, #3
	b	LBB0_8
LBB0_7:
	asr	w19, w19, #2
LBB0_8:
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_M_SPLL_REF_FB_DIV,4,2   ; @RADEON_M_SPLL_REF_FB_DIV
	.comm	_RADEON_SPLL_FB_DIV_SHIFT,4,2   ; @RADEON_SPLL_FB_DIV_SHIFT
	.comm	_RADEON_SPLL_FB_DIV_MASK,4,2    ; @RADEON_SPLL_FB_DIV_MASK
	.comm	_RADEON_M_SPLL_REF_DIV_MASK,4,2 ; @RADEON_M_SPLL_REF_DIV_MASK
	.comm	_RADEON_SCLK_CNTL,4,2           ; @RADEON_SCLK_CNTL
	.comm	_RADEON_SCLK_SRC_SEL_MASK,4,2   ; @RADEON_SCLK_SRC_SEL_MASK
.subsections_via_symbols
