	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function panfrost_gpu_init_quirks
_panfrost_gpu_init_quirks:              ## @panfrost_gpu_init_quirks
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	_HW_ISSUE_8443@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_panfrost_has_hw_issue
	testq	%rax, %rax
	jne	LBB0_3
## %bb.1:
	movq	_HW_ISSUE_11035@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_panfrost_has_hw_issue
	testq	%rax, %rax
	je	LBB0_2
LBB0_3:
	movq	_SC_LS_PAUSEBUFFER_DISABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
LBB0_4:
	movq	_HW_ISSUE_10327@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_panfrost_has_hw_issue
	xorl	%r14d, %r14d
	movl	$0, %ebx
	testq	%rax, %rax
	je	LBB0_6
## %bb.5:
	movq	_SC_SDC_DISABLE_OQ_DISCARD@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
LBB0_6:
	orl	%r12d, %ebx
	movq	_HW_ISSUE_10797@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_panfrost_has_hw_issue
	testq	%rax, %rax
	je	LBB0_8
## %bb.7:
	movq	_SC_ENABLE_TEXGRD_FLAGS@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
LBB0_8:
	orl	%r14d, %ebx
	movq	_GPUCORE_1619@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_panfrost_has_hw_issue
	testq	%rax, %rax
	jne	LBB0_14
## %bb.9:
	movq	%r15, %rdi
	movl	$1872, %esi                     ## imm = 0x750
	callq	_panfrost_model_cmp
	testq	%rax, %rax
	js	LBB0_10
## %bb.11:
	movq	%r15, %rdi
	movl	$2176, %esi                     ## imm = 0x880
	callq	_panfrost_model_cmp
	testq	%rax, %rax
	jg	LBB0_14
## %bb.12:
	movq	_SC_LS_ALLOW_ATTR_TYPES@GOTPCREL(%rip), %rax
	jmp	LBB0_13
LBB0_2:
	xorl	%r12d, %r12d
	jmp	LBB0_4
LBB0_10:
	movq	_SC_LS_ATTR_CHECK_DISABLE@GOTPCREL(%rip), %rax
LBB0_13:
	orl	(%rax), %ebx
LBB0_14:
	movq	_HW_FEATURE_TLS_HASHING@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_panfrost_has_hw_feature
	xorl	%edx, %edx
	testq	%rax, %rax
	je	LBB0_16
## %bb.15:
	movq	_SC_TLS_HASH_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
LBB0_16:
	orl	%ebx, %edx
	je	LBB0_18
## %bb.17:
	movq	_GPU_SHADER_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_gpu_write
LBB0_18:
	movq	_GPU_TILER_CONFIG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_gpu_read
	movl	%eax, %r14d
	movq	_HW_ISSUE_T76X_3953@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_panfrost_has_hw_issue
	xorl	%edx, %edx
	testq	%rax, %rax
	je	LBB0_20
## %bb.19:
	movq	_TC_CLOCK_GATE_OVERRIDE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
LBB0_20:
	orl	%r14d, %edx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_gpu_write
	movq	_GPU_L2_MMU_CONFIG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_gpu_read
	movl	%eax, %r14d
	movq	_HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_panfrost_has_hw_feature
	movq	_L2_MMU_CONFIG_LIMIT_EXTERNAL_READS@GOTPCREL(%rip), %rcx
	movq	_L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS@GOTPCREL(%rip), %rsi
	movq	_L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edi
	movq	_L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edi
	orl	(%rsi), %edx
	testq	%rax, %rax
	cmovel	%edi, %edx
	notl	%edx
	andl	%r14d, %edx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_gpu_write
	movq	%r15, %rdi
	movl	$2144, %esi                     ## imm = 0x860
	callq	_panfrost_model_eq
	testq	%rax, %rax
	jne	LBB0_22
## %bb.21:
	movq	%r15, %rdi
	movl	$2176, %esi                     ## imm = 0x880
	callq	_panfrost_model_eq
	testq	%rax, %rax
	je	LBB0_24
LBB0_22:
	cmpl	$8192, (%r15)                   ## imm = 0x2000
	jl	LBB0_24
## %bb.23:
	movq	_JM_MAX_JOB_THROTTLE_LIMIT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_JM_JOB_THROTTLE_LIMIT_SHIFT@GOTPCREL(%rip), %rax
	jmp	LBB0_27
LBB0_24:
	movq	%r15, %rdi
	movl	$24576, %esi                    ## imm = 0x6000
	callq	_panfrost_model_eq
	testq	%rax, %rax
	je	LBB0_28
## %bb.25:
	movl	4(%r15), %edx
	movq	_COHERENCY_ACE@GOTPCREL(%rip), %rax
	cmpl	(%rax), %edx
	jne	LBB0_28
## %bb.26:
	movq	_COHERENCY_ACE_LITE@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_JM_FORCE_COHERENCY_FEATURES_SHIFT@GOTPCREL(%rip), %rax
LBB0_27:
	movb	(%rax), %cl
	shll	%cl, %edx
	testl	%edx, %edx
	je	LBB0_28
## %bb.29:
	movq	_GPU_JM_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_gpu_write                      ## TAILCALL
LBB0_28:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_HW_ISSUE_8443,4,2              ## @HW_ISSUE_8443
	.comm	_HW_ISSUE_11035,4,2             ## @HW_ISSUE_11035
	.comm	_SC_LS_PAUSEBUFFER_DISABLE,4,2  ## @SC_LS_PAUSEBUFFER_DISABLE
	.comm	_HW_ISSUE_10327,4,2             ## @HW_ISSUE_10327
	.comm	_SC_SDC_DISABLE_OQ_DISCARD,4,2  ## @SC_SDC_DISABLE_OQ_DISCARD
	.comm	_HW_ISSUE_10797,4,2             ## @HW_ISSUE_10797
	.comm	_SC_ENABLE_TEXGRD_FLAGS,4,2     ## @SC_ENABLE_TEXGRD_FLAGS
	.comm	_GPUCORE_1619,4,2               ## @GPUCORE_1619
	.comm	_SC_LS_ATTR_CHECK_DISABLE,4,2   ## @SC_LS_ATTR_CHECK_DISABLE
	.comm	_SC_LS_ALLOW_ATTR_TYPES,4,2     ## @SC_LS_ALLOW_ATTR_TYPES
	.comm	_HW_FEATURE_TLS_HASHING,4,2     ## @HW_FEATURE_TLS_HASHING
	.comm	_SC_TLS_HASH_ENABLE,4,2         ## @SC_TLS_HASH_ENABLE
	.comm	_GPU_SHADER_CONFIG,4,2          ## @GPU_SHADER_CONFIG
	.comm	_GPU_TILER_CONFIG,4,2           ## @GPU_TILER_CONFIG
	.comm	_HW_ISSUE_T76X_3953,4,2         ## @HW_ISSUE_T76X_3953
	.comm	_TC_CLOCK_GATE_OVERRIDE,4,2     ## @TC_CLOCK_GATE_OVERRIDE
	.comm	_GPU_L2_MMU_CONFIG,4,2          ## @GPU_L2_MMU_CONFIG
	.comm	_HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG,4,2 ## @HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG
	.comm	_L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS,4,2 ## @L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS
	.comm	_L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES,4,2 ## @L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES
	.comm	_L2_MMU_CONFIG_LIMIT_EXTERNAL_READS,4,2 ## @L2_MMU_CONFIG_LIMIT_EXTERNAL_READS
	.comm	_L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES,4,2 ## @L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES
	.comm	_JM_MAX_JOB_THROTTLE_LIMIT,4,2  ## @JM_MAX_JOB_THROTTLE_LIMIT
	.comm	_JM_JOB_THROTTLE_LIMIT_SHIFT,4,2 ## @JM_JOB_THROTTLE_LIMIT_SHIFT
	.comm	_COHERENCY_ACE,4,2              ## @COHERENCY_ACE
	.comm	_COHERENCY_ACE_LITE,4,2         ## @COHERENCY_ACE_LITE
	.comm	_JM_FORCE_COHERENCY_FEATURES_SHIFT,4,2 ## @JM_FORCE_COHERENCY_FEATURES_SHIFT
	.comm	_GPU_JM_CONFIG,4,2              ## @GPU_JM_CONFIG
	.no_dead_strip	_panfrost_gpu_init_quirks
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function panfrost_gpu_init_quirks
_panfrost_gpu_init_quirks:              ; @panfrost_gpu_init_quirks
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, _HW_ISSUE_8443@GOTPAGE
Lloh1:
	ldr	x8, [x8, _HW_ISSUE_8443@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	bl	_panfrost_has_hw_issue
	cbnz	x0, LBB0_2
; %bb.1:
Lloh3:
	adrp	x8, _HW_ISSUE_11035@GOTPAGE
Lloh4:
	ldr	x8, [x8, _HW_ISSUE_11035@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_panfrost_has_hw_issue
	cbz	x0, LBB0_7
LBB0_2:
Lloh6:
	adrp	x8, _SC_LS_PAUSEBUFFER_DISABLE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _SC_LS_PAUSEBUFFER_DISABLE@GOTPAGEOFF]
Lloh8:
	ldr	w20, [x8]
LBB0_3:
Lloh9:
	adrp	x8, _HW_ISSUE_10327@GOTPAGE
Lloh10:
	ldr	x8, [x8, _HW_ISSUE_10327@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_panfrost_has_hw_issue
Lloh12:
	adrp	x8, _SC_SDC_DISABLE_OQ_DISCARD@GOTPAGE
Lloh13:
	ldr	x8, [x8, _SC_SDC_DISABLE_OQ_DISCARD@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w20, w8, w20
Lloh15:
	adrp	x8, _HW_ISSUE_10797@GOTPAGE
Lloh16:
	ldr	x8, [x8, _HW_ISSUE_10797@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_panfrost_has_hw_issue
Lloh18:
	adrp	x8, _SC_ENABLE_TEXGRD_FLAGS@GOTPAGE
Lloh19:
	ldr	x8, [x8, _SC_ENABLE_TEXGRD_FLAGS@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w20, w20, w8
Lloh21:
	adrp	x8, _GPUCORE_1619@GOTPAGE
Lloh22:
	ldr	x8, [x8, _GPUCORE_1619@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_panfrost_has_hw_issue
	cbnz	x0, LBB0_10
; %bb.4:
	mov	x0, x19
	mov	w1, #1872
	bl	_panfrost_model_cmp
	tbnz	x0, #63, LBB0_8
; %bb.5:
	mov	x0, x19
	mov	w1, #2176
	bl	_panfrost_model_cmp
	cmp	x0, #0
	b.gt	LBB0_10
; %bb.6:
Lloh24:
	adrp	x8, _SC_LS_ALLOW_ATTR_TYPES@GOTPAGE
Lloh25:
	ldr	x8, [x8, _SC_LS_ALLOW_ATTR_TYPES@GOTPAGEOFF]
	b	LBB0_9
LBB0_7:
	mov	w20, #0
	b	LBB0_3
LBB0_8:
Lloh26:
	adrp	x8, _SC_LS_ATTR_CHECK_DISABLE@GOTPAGE
Lloh27:
	ldr	x8, [x8, _SC_LS_ATTR_CHECK_DISABLE@GOTPAGEOFF]
LBB0_9:
	ldr	w8, [x8]
	orr	w20, w8, w20
LBB0_10:
Lloh28:
	adrp	x8, _HW_FEATURE_TLS_HASHING@GOTPAGE
Lloh29:
	ldr	x8, [x8, _HW_FEATURE_TLS_HASHING@GOTPAGEOFF]
Lloh30:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_panfrost_has_hw_feature
Lloh31:
	adrp	x8, _SC_TLS_HASH_ENABLE@GOTPAGE
Lloh32:
	ldr	x8, [x8, _SC_TLS_HASH_ENABLE@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w2, w8, w20
	cbz	w2, LBB0_12
; %bb.11:
Lloh34:
	adrp	x8, _GPU_SHADER_CONFIG@GOTPAGE
Lloh35:
	ldr	x8, [x8, _GPU_SHADER_CONFIG@GOTPAGEOFF]
Lloh36:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_gpu_write
LBB0_12:
Lloh37:
	adrp	x21, _GPU_TILER_CONFIG@GOTPAGE
Lloh38:
	ldr	x21, [x21, _GPU_TILER_CONFIG@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_gpu_read
	mov	x20, x0
Lloh39:
	adrp	x8, _HW_ISSUE_T76X_3953@GOTPAGE
Lloh40:
	ldr	x8, [x8, _HW_ISSUE_T76X_3953@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_panfrost_has_hw_issue
Lloh42:
	adrp	x8, _TC_CLOCK_GATE_OVERRIDE@GOTPAGE
Lloh43:
	ldr	x8, [x8, _TC_CLOCK_GATE_OVERRIDE@GOTPAGEOFF]
Lloh44:
	ldr	w8, [x8]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w2, w8, w20
	ldr	w1, [x21]
	mov	x0, x19
	bl	_gpu_write
Lloh45:
	adrp	x21, _GPU_L2_MMU_CONFIG@GOTPAGE
Lloh46:
	ldr	x21, [x21, _GPU_L2_MMU_CONFIG@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_gpu_read
	mov	x20, x0
Lloh47:
	adrp	x8, _HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG@GOTPAGE
Lloh48:
	ldr	x8, [x8, _HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG@GOTPAGEOFF]
Lloh49:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_panfrost_has_hw_feature
Lloh50:
	adrp	x8, _L2_MMU_CONFIG_LIMIT_EXTERNAL_READS@GOTPAGE
Lloh51:
	ldr	x8, [x8, _L2_MMU_CONFIG_LIMIT_EXTERNAL_READS@GOTPAGEOFF]
Lloh52:
	ldr	w8, [x8]
Lloh53:
	adrp	x9, _L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS@GOTPAGE
Lloh54:
	ldr	x9, [x9, _L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS@GOTPAGEOFF]
Lloh55:
	ldr	w9, [x9]
Lloh56:
	adrp	x10, _L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES@GOTPAGE
Lloh57:
	ldr	x10, [x10, _L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES@GOTPAGEOFF]
Lloh58:
	ldr	w10, [x10]
Lloh59:
	adrp	x11, _L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES@GOTPAGE
Lloh60:
	ldr	x11, [x11, _L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES@GOTPAGEOFF]
Lloh61:
	ldr	w11, [x11]
	orr	w8, w10, w8
	orr	w9, w11, w9
	cmp	x0, #0
	csel	w8, w8, w9, eq
	bic	w2, w20, w8
	ldr	w1, [x21]
	mov	x0, x19
	bl	_gpu_write
	mov	x0, x19
	mov	w1, #2144
	bl	_panfrost_model_eq
	cbnz	x0, LBB0_14
; %bb.13:
	mov	x0, x19
	mov	w1, #2176
	bl	_panfrost_model_eq
	cbz	x0, LBB0_16
LBB0_14:
	ldr	w8, [x19]
	cmp	w8, #2, lsl #12                 ; =8192
	b.lt	LBB0_16
; %bb.15:
Lloh62:
	adrp	x8, _JM_MAX_JOB_THROTTLE_LIMIT@GOTPAGE
Lloh63:
	ldr	x8, [x8, _JM_MAX_JOB_THROTTLE_LIMIT@GOTPAGEOFF]
Lloh64:
	ldr	w8, [x8]
Lloh65:
	adrp	x9, _JM_JOB_THROTTLE_LIMIT_SHIFT@GOTPAGE
Lloh66:
	ldr	x9, [x9, _JM_JOB_THROTTLE_LIMIT_SHIFT@GOTPAGEOFF]
	b	LBB0_19
LBB0_16:
	mov	x0, x19
	mov	w1, #24576
	bl	_panfrost_model_eq
	cbz	x0, LBB0_21
; %bb.17:
	ldr	w8, [x19, #4]
Lloh67:
	adrp	x9, _COHERENCY_ACE@GOTPAGE
Lloh68:
	ldr	x9, [x9, _COHERENCY_ACE@GOTPAGEOFF]
Lloh69:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_21
; %bb.18:
Lloh70:
	adrp	x9, _COHERENCY_ACE_LITE@GOTPAGE
Lloh71:
	ldr	x9, [x9, _COHERENCY_ACE_LITE@GOTPAGEOFF]
Lloh72:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh73:
	adrp	x9, _JM_FORCE_COHERENCY_FEATURES_SHIFT@GOTPAGE
Lloh74:
	ldr	x9, [x9, _JM_FORCE_COHERENCY_FEATURES_SHIFT@GOTPAGEOFF]
LBB0_19:
	ldr	w9, [x9]
	lsl	w2, w8, w9
	cbz	w2, LBB0_21
; %bb.20:
Lloh75:
	adrp	x8, _GPU_JM_CONFIG@GOTPAGE
Lloh76:
	ldr	x8, [x8, _GPU_JM_CONFIG@GOTPAGEOFF]
Lloh77:
	ldr	w1, [x8]
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_gpu_write
LBB0_21:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGot	Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.cfi_endproc
                                        ; -- End function
	.comm	_HW_ISSUE_8443,4,2              ; @HW_ISSUE_8443
	.comm	_HW_ISSUE_11035,4,2             ; @HW_ISSUE_11035
	.comm	_SC_LS_PAUSEBUFFER_DISABLE,4,2  ; @SC_LS_PAUSEBUFFER_DISABLE
	.comm	_HW_ISSUE_10327,4,2             ; @HW_ISSUE_10327
	.comm	_SC_SDC_DISABLE_OQ_DISCARD,4,2  ; @SC_SDC_DISABLE_OQ_DISCARD
	.comm	_HW_ISSUE_10797,4,2             ; @HW_ISSUE_10797
	.comm	_SC_ENABLE_TEXGRD_FLAGS,4,2     ; @SC_ENABLE_TEXGRD_FLAGS
	.comm	_GPUCORE_1619,4,2               ; @GPUCORE_1619
	.comm	_SC_LS_ATTR_CHECK_DISABLE,4,2   ; @SC_LS_ATTR_CHECK_DISABLE
	.comm	_SC_LS_ALLOW_ATTR_TYPES,4,2     ; @SC_LS_ALLOW_ATTR_TYPES
	.comm	_HW_FEATURE_TLS_HASHING,4,2     ; @HW_FEATURE_TLS_HASHING
	.comm	_SC_TLS_HASH_ENABLE,4,2         ; @SC_TLS_HASH_ENABLE
	.comm	_GPU_SHADER_CONFIG,4,2          ; @GPU_SHADER_CONFIG
	.comm	_GPU_TILER_CONFIG,4,2           ; @GPU_TILER_CONFIG
	.comm	_HW_ISSUE_T76X_3953,4,2         ; @HW_ISSUE_T76X_3953
	.comm	_TC_CLOCK_GATE_OVERRIDE,4,2     ; @TC_CLOCK_GATE_OVERRIDE
	.comm	_GPU_L2_MMU_CONFIG,4,2          ; @GPU_L2_MMU_CONFIG
	.comm	_HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG,4,2 ; @HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG
	.comm	_L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS,4,2 ; @L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS
	.comm	_L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES,4,2 ; @L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES
	.comm	_L2_MMU_CONFIG_LIMIT_EXTERNAL_READS,4,2 ; @L2_MMU_CONFIG_LIMIT_EXTERNAL_READS
	.comm	_L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES,4,2 ; @L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES
	.comm	_JM_MAX_JOB_THROTTLE_LIMIT,4,2  ; @JM_MAX_JOB_THROTTLE_LIMIT
	.comm	_JM_JOB_THROTTLE_LIMIT_SHIFT,4,2 ; @JM_JOB_THROTTLE_LIMIT_SHIFT
	.comm	_COHERENCY_ACE,4,2              ; @COHERENCY_ACE
	.comm	_COHERENCY_ACE_LITE,4,2         ; @COHERENCY_ACE_LITE
	.comm	_JM_FORCE_COHERENCY_FEATURES_SHIFT,4,2 ; @JM_FORCE_COHERENCY_FEATURES_SHIFT
	.comm	_GPU_JM_CONFIG,4,2              ; @GPU_JM_CONFIG
	.no_dead_strip	_panfrost_gpu_init_quirks
.subsections_via_symbols
