	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function a4xx_hw_init
_a4xx_hw_init:                          ## @a4xx_hw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	callq	_to_adreno_gpu
	movq	%rax, %r14
	movq	%rax, %rdi
	callq	_to_a4xx_gpu
	movq	%rax, %r15
	movq	%r14, %rdi
	callq	_adreno_is_a420
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	_REG_A4XX_VBIF_ABIT_SORT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$65567, %edx                    ## imm = 0x1001F
	callq	_gpu_write
	movq	_REG_A4XX_VBIF_ABIT_SORT_CONF@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$164, %edx
	callq	_gpu_write
	jmp	LBB0_3
LBB0_2:
	movq	%r14, %rdi
	callq	_adreno_is_a430
	testq	%rax, %rax
	je	LBB0_4
LBB0_3:
	movq	_REG_A4XX_VBIF_GATE_OFF_WRREQ_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A4XX_VBIF_IN_RD_LIM_CONF0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$404232216, %edx                ## imm = 0x18181818
	callq	_gpu_write
	movq	_REG_A4XX_VBIF_IN_RD_LIM_CONF1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$24, %edx
	callq	_gpu_write
	movq	_REG_A4XX_VBIF_IN_WR_LIM_CONF0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$404232216, %edx                ## imm = 0x18181818
	callq	_gpu_write
	movq	_REG_A4XX_VBIF_IN_WR_LIM_CONF1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$24, %edx
	callq	_gpu_write
	movq	_REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$3, %edx
	callq	_gpu_write
LBB0_5:
	movq	_REG_A4XX_RBBM_GPU_BUSY_MASKED@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$-1, %edx
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_SP_HYST_CNT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$16, %edx
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$16, %edx
	callq	_gpu_write
	movq	%r14, %rdi
	callq	_adreno_is_a430
	testq	%rax, %rax
	je	LBB0_7
## %bb.6:
	movq	_REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$48, %edx
	callq	_gpu_write
LBB0_7:
	movq	_REG_A4XX_RBBM_AHB_CTL0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_AHB_CTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$-1493172225, %edx              ## imm = 0xA6FFFFFF
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_RBBM_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$48, %edx
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$1073807359, %edx               ## imm = 0x4000FFFF
	callq	_gpu_write
	movq	_REG_A4XX_RB_GMEM_BASE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r15), %edx
	sarl	$14, %edx
	movq	%r12, %rdi
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_PERFCTR_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A4XX_CP_PERFCTR_CP_SEL_0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_CP_ALWAYS_COUNT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_gpu_write
	movq	%r14, %rdi
	callq	_adreno_is_a430
	testq	%rax, %rax
	je	LBB0_9
## %bb.8:
	movq	_REG_A4XX_UCHE_CACHE_WAYS_VFD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$7, %edx
	callq	_gpu_write
LBB0_9:
	movq	_REG_A4XX_UCHE_TRAP_BASE_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$-65536, %edx                   ## imm = 0xFFFF0000
	callq	_gpu_write
	movq	_REG_A4XX_UCHE_TRAP_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$-65536, %edx                   ## imm = 0xFFFF0000
	callq	_gpu_write
	movq	_REG_A4XX_CP_DEBUG@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	%r14, %rdi
	callq	_adreno_is_a420
	xorl	%edx, %edx
	testq	%rax, %rax
	setne	%dl
	shll	$29, %edx
	orl	$33554432, %edx                 ## imm = 0x2000000
	movq	%r12, %rdi
	movl	%r15d, %esi
	callq	_gpu_write
	movq	%r14, %rdi
	callq	_adreno_is_a420
	testq	%rax, %rax
	jne	LBB0_11
## %bb.10:
	movq	_REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$1089, %edx                     ## imm = 0x441
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$1089, %edx                     ## imm = 0x441
	callq	_gpu_write
LBB0_11:
	movq	%r12, %rdi
	callq	_a4xx_enable_hwcg
	movq	%r14, %rdi
	callq	_adreno_is_a420
	testq	%rax, %rax
	je	LBB0_13
## %bb.12:
	movq	_REG_A4XX_RBBM_CLOCK_DELAY_HLSQ@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_gpu_read
	movq	_A4XX_CGC_HLSQ_EARLY_CYC__MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_A4XX_CGC_HLSQ_EARLY_CYC__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %edx
	shll	%cl, %edx
	notl	%esi
	andl	%eax, %esi
	orl	%esi, %edx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_gpu_write
LBB0_13:
	movq	_REG_A4XX_CP_PROTECT_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$7, %edx
	callq	_gpu_write
	xorl	%edi, %edi
	callq	_REG_A4XX_CP_PROTECT
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$1644167184, %edx               ## imm = 0x62000010
	callq	_gpu_write
	movl	$1, %edi
	callq	_REG_A4XX_CP_PROTECT
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$1660944416, %edx               ## imm = 0x63000020
	callq	_gpu_write
	movl	$2, %edi
	callq	_REG_A4XX_CP_PROTECT
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$1677721664, %edx               ## imm = 0x64000040
	callq	_gpu_write
	movl	$3, %edi
	callq	_REG_A4XX_CP_PROTECT
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$1694498944, %edx               ## imm = 0x65000080
	callq	_gpu_write
	movl	$4, %edi
	callq	_REG_A4XX_CP_PROTECT
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$1711276288, %edx               ## imm = 0x66000100
	callq	_gpu_write
	movl	$5, %edi
	callq	_REG_A4XX_CP_PROTECT
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$1677722112, %edx               ## imm = 0x64000200
	callq	_gpu_write
	movl	$6, %edi
	callq	_REG_A4XX_CP_PROTECT
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$1728055296, %edx               ## imm = 0x67000800
	callq	_gpu_write
	movl	$7, %edi
	callq	_REG_A4XX_CP_PROTECT
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$1677727232, %edx               ## imm = 0x64001600
	callq	_gpu_write
	movl	$8, %edi
	callq	_REG_A4XX_CP_PROTECT
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$1610625792, %edx               ## imm = 0x60003300
	callq	_gpu_write
	movl	$9, %edi
	callq	_REG_A4XX_CP_PROTECT
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$1610627072, %edx               ## imm = 0x60003800
	callq	_gpu_write
	movl	$10, %edi
	callq	_REG_A4XX_CP_PROTECT
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$1627404672, %edx               ## imm = 0x61003980
	callq	_gpu_write
	movl	$11, %edi
	callq	_REG_A4XX_CP_PROTECT
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$1845559296, %edx               ## imm = 0x6E010000
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_INT_0_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_A4XX_INT0_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_gpu_write
	movq	%r12, %rdi
	callq	_adreno_hw_init
	movl	%eax, %ecx
	testl	%eax, %eax
	jne	LBB0_21
## %bb.14:
	movq	%r14, -48(%rbp)                 ## 8-byte Spill
	movq	(%r14), %rax
	movq	_ADRENO_FW_PM4@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	(%rax,%rcx,8), %rax
	movq	8(%rax), %r15
	movl	(%rax), %r13d
	movl	(%r15), %esi
	leaq	L_.str(%rip), %rdi
	callq	_DBG
	movq	_REG_A4XX_CP_ME_RAM_WADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	cmpl	$8, %r13d
	jl	LBB0_17
## %bb.15:
	shrq	$2, %r13
	movl	$1, %ebx
	movq	_REG_A4XX_CP_ME_RAM_DATA@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_16:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %esi
	movl	(%r15,%rbx,4), %edx
	movq	%r12, %rdi
	callq	_gpu_write
	incq	%rbx
	cmpq	%rbx, %r13
	jne	LBB0_16
LBB0_17:
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rax
	movq	_ADRENO_FW_PFP@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	(%rax,%rcx,8), %rax
	movq	8(%rax), %r15
	movl	(%rax), %r13d
	movl	(%r15), %esi
	leaq	L_.str.1(%rip), %rdi
	callq	_DBG
	movq	_REG_A4XX_CP_PFP_UCODE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	cmpl	$8, %r13d
	jl	LBB0_20
## %bb.18:
	shrq	$2, %r13
	movl	$1, %ebx
	movq	_REG_A4XX_CP_PFP_UCODE_DATA@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_19:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %esi
	movl	(%r15,%rbx,4), %edx
	movq	%r12, %rdi
	callq	_gpu_write
	incq	%rbx
	cmpq	%rbx, %r13
	jne	LBB0_19
LBB0_20:
	movq	_REG_A4XX_CP_ME_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movq	%r12, %rdi
	callq	_a4xx_me_init
	movq	_EINVAL@GOTPCREL(%rip), %rdx
	xorl	%ecx, %ecx
	subl	(%rdx), %ecx
	testq	%rax, %rax
	movl	$0, %eax
	cmovnel	%eax, %ecx
LBB0_21:
	movl	%ecx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_4:
	xorl	%eax, %eax
	callq	_BUG
	jmp	LBB0_5
	.cfi_endproc
                                        ## -- End function
	.comm	_REG_A4XX_VBIF_ABIT_SORT,4,2    ## @REG_A4XX_VBIF_ABIT_SORT
	.comm	_REG_A4XX_VBIF_ABIT_SORT_CONF,4,2 ## @REG_A4XX_VBIF_ABIT_SORT_CONF
	.comm	_REG_A4XX_VBIF_GATE_OFF_WRREQ_EN,4,2 ## @REG_A4XX_VBIF_GATE_OFF_WRREQ_EN
	.comm	_REG_A4XX_VBIF_IN_RD_LIM_CONF0,4,2 ## @REG_A4XX_VBIF_IN_RD_LIM_CONF0
	.comm	_REG_A4XX_VBIF_IN_RD_LIM_CONF1,4,2 ## @REG_A4XX_VBIF_IN_RD_LIM_CONF1
	.comm	_REG_A4XX_VBIF_IN_WR_LIM_CONF0,4,2 ## @REG_A4XX_VBIF_IN_WR_LIM_CONF0
	.comm	_REG_A4XX_VBIF_IN_WR_LIM_CONF1,4,2 ## @REG_A4XX_VBIF_IN_WR_LIM_CONF1
	.comm	_REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB,4,2 ## @REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB
	.comm	_REG_A4XX_RBBM_GPU_BUSY_MASKED,4,2 ## @REG_A4XX_RBBM_GPU_BUSY_MASKED
	.comm	_REG_A4XX_RBBM_SP_HYST_CNT,4,2  ## @REG_A4XX_RBBM_SP_HYST_CNT
	.comm	_REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL,4,2 ## @REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL
	.comm	_REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2,4,2 ## @REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2
	.comm	_REG_A4XX_RBBM_AHB_CTL0,4,2     ## @REG_A4XX_RBBM_AHB_CTL0
	.comm	_REG_A4XX_RBBM_AHB_CTL1,4,2     ## @REG_A4XX_RBBM_AHB_CTL1
	.comm	_REG_A4XX_RBBM_RBBM_CTL,4,2     ## @REG_A4XX_RBBM_RBBM_CTL
	.comm	_REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL,4,2 ## @REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL
	.comm	_REG_A4XX_RB_GMEM_BASE_ADDR,4,2 ## @REG_A4XX_RB_GMEM_BASE_ADDR
	.comm	_REG_A4XX_RBBM_PERFCTR_CTL,4,2  ## @REG_A4XX_RBBM_PERFCTR_CTL
	.comm	_REG_A4XX_CP_PERFCTR_CP_SEL_0,4,2 ## @REG_A4XX_CP_PERFCTR_CP_SEL_0
	.comm	_CP_ALWAYS_COUNT,4,2            ## @CP_ALWAYS_COUNT
	.comm	_REG_A4XX_UCHE_CACHE_WAYS_VFD,4,2 ## @REG_A4XX_UCHE_CACHE_WAYS_VFD
	.comm	_REG_A4XX_UCHE_TRAP_BASE_LO,4,2 ## @REG_A4XX_UCHE_TRAP_BASE_LO
	.comm	_REG_A4XX_UCHE_TRAP_BASE_HI,4,2 ## @REG_A4XX_UCHE_TRAP_BASE_HI
	.comm	_REG_A4XX_CP_DEBUG,4,2          ## @REG_A4XX_CP_DEBUG
	.comm	_REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0,4,2 ## @REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0
	.comm	_REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1,4,2 ## @REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1
	.comm	_REG_A4XX_RBBM_CLOCK_DELAY_HLSQ,4,2 ## @REG_A4XX_RBBM_CLOCK_DELAY_HLSQ
	.comm	_A4XX_CGC_HLSQ_EARLY_CYC__MASK,4,2 ## @A4XX_CGC_HLSQ_EARLY_CYC__MASK
	.comm	_A4XX_CGC_HLSQ_EARLY_CYC__SHIFT,4,2 ## @A4XX_CGC_HLSQ_EARLY_CYC__SHIFT
	.comm	_REG_A4XX_CP_PROTECT_CTRL,4,2   ## @REG_A4XX_CP_PROTECT_CTRL
	.comm	_REG_A4XX_RBBM_INT_0_MASK,4,2   ## @REG_A4XX_RBBM_INT_0_MASK
	.comm	_A4XX_INT0_MASK,4,2             ## @A4XX_INT0_MASK
	.comm	_ADRENO_FW_PM4,8,3              ## @ADRENO_FW_PM4
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"loading PM4 ucode version: %u"

	.comm	_REG_A4XX_CP_ME_RAM_WADDR,4,2   ## @REG_A4XX_CP_ME_RAM_WADDR
	.comm	_REG_A4XX_CP_ME_RAM_DATA,4,2    ## @REG_A4XX_CP_ME_RAM_DATA
	.comm	_ADRENO_FW_PFP,8,3              ## @ADRENO_FW_PFP
L_.str.1:                               ## @.str.1
	.asciz	"loading PFP ucode version: %u"

	.comm	_REG_A4XX_CP_PFP_UCODE_ADDR,4,2 ## @REG_A4XX_CP_PFP_UCODE_ADDR
	.comm	_REG_A4XX_CP_PFP_UCODE_DATA,4,2 ## @REG_A4XX_CP_PFP_UCODE_DATA
	.comm	_REG_A4XX_CP_ME_CNTL,4,2        ## @REG_A4XX_CP_ME_CNTL
	.comm	_EINVAL,4,2                     ## @EINVAL
	.no_dead_strip	_a4xx_hw_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function a4xx_hw_init
_a4xx_hw_init:                          ; @a4xx_hw_init
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	bl	_to_adreno_gpu
	mov	x20, x0
	bl	_to_a4xx_gpu
	mov	x21, x0
	mov	x0, x20
	bl	_adreno_is_a420
	cbz	x0, LBB0_2
; %bb.1:
Lloh0:
	adrp	x8, _REG_A4XX_VBIF_ABIT_SORT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _REG_A4XX_VBIF_ABIT_SORT@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #31
	movk	w2, #1, lsl #16
	bl	_gpu_write
Lloh3:
	adrp	x8, _REG_A4XX_VBIF_ABIT_SORT_CONF@GOTPAGE
Lloh4:
	ldr	x8, [x8, _REG_A4XX_VBIF_ABIT_SORT_CONF@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #164
	bl	_gpu_write
	b	LBB0_3
LBB0_2:
	mov	x0, x20
	bl	_adreno_is_a430
	cbz	x0, LBB0_21
LBB0_3:
Lloh6:
	adrp	x8, _REG_A4XX_VBIF_GATE_OFF_WRREQ_EN@GOTPAGE
Lloh7:
	ldr	x8, [x8, _REG_A4XX_VBIF_GATE_OFF_WRREQ_EN@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
Lloh9:
	adrp	x8, _REG_A4XX_VBIF_IN_RD_LIM_CONF0@GOTPAGE
Lloh10:
	ldr	x8, [x8, _REG_A4XX_VBIF_IN_RD_LIM_CONF0@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #404232216
	bl	_gpu_write
Lloh12:
	adrp	x8, _REG_A4XX_VBIF_IN_RD_LIM_CONF1@GOTPAGE
Lloh13:
	ldr	x8, [x8, _REG_A4XX_VBIF_IN_RD_LIM_CONF1@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #24
	bl	_gpu_write
Lloh15:
	adrp	x8, _REG_A4XX_VBIF_IN_WR_LIM_CONF0@GOTPAGE
Lloh16:
	ldr	x8, [x8, _REG_A4XX_VBIF_IN_WR_LIM_CONF0@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #404232216
	bl	_gpu_write
Lloh18:
	adrp	x8, _REG_A4XX_VBIF_IN_WR_LIM_CONF1@GOTPAGE
Lloh19:
	ldr	x8, [x8, _REG_A4XX_VBIF_IN_WR_LIM_CONF1@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #24
	bl	_gpu_write
Lloh21:
	adrp	x8, _REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB@GOTPAGE
Lloh22:
	ldr	x8, [x8, _REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #3
	bl	_gpu_write
LBB0_4:
Lloh24:
	adrp	x8, _REG_A4XX_RBBM_GPU_BUSY_MASKED@GOTPAGE
Lloh25:
	ldr	x8, [x8, _REG_A4XX_RBBM_GPU_BUSY_MASKED@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1
	bl	_gpu_write
Lloh27:
	adrp	x8, _REG_A4XX_RBBM_SP_HYST_CNT@GOTPAGE
Lloh28:
	ldr	x8, [x8, _REG_A4XX_RBBM_SP_HYST_CNT@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #16
	bl	_gpu_write
Lloh30:
	adrp	x8, _REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL@GOTPAGE
Lloh31:
	ldr	x8, [x8, _REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #16
	bl	_gpu_write
	mov	x0, x20
	bl	_adreno_is_a430
	cbz	x0, LBB0_6
; %bb.5:
Lloh33:
	adrp	x8, _REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2@GOTPAGE
Lloh34:
	ldr	x8, [x8, _REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2@GOTPAGEOFF]
Lloh35:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #48
	bl	_gpu_write
LBB0_6:
Lloh36:
	adrp	x8, _REG_A4XX_RBBM_AHB_CTL0@GOTPAGE
Lloh37:
	ldr	x8, [x8, _REG_A4XX_RBBM_AHB_CTL0@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
Lloh39:
	adrp	x8, _REG_A4XX_RBBM_AHB_CTL1@GOTPAGE
Lloh40:
	ldr	x8, [x8, _REG_A4XX_RBBM_AHB_CTL1@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1493172225
	bl	_gpu_write
Lloh42:
	adrp	x8, _REG_A4XX_RBBM_RBBM_CTL@GOTPAGE
Lloh43:
	ldr	x8, [x8, _REG_A4XX_RBBM_RBBM_CTL@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #48
	bl	_gpu_write
Lloh45:
	adrp	x8, _REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL@GOTPAGE
Lloh46:
	ldr	x8, [x8, _REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL@GOTPAGEOFF]
Lloh47:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1073807359
	bl	_gpu_write
Lloh48:
	adrp	x8, _REG_A4XX_RB_GMEM_BASE_ADDR@GOTPAGE
Lloh49:
	ldr	x8, [x8, _REG_A4XX_RB_GMEM_BASE_ADDR@GOTPAGEOFF]
Lloh50:
	ldr	w1, [x8]
	ldr	w8, [x21]
	asr	w2, w8, #14
	mov	x0, x19
	bl	_gpu_write
Lloh51:
	adrp	x8, _REG_A4XX_RBBM_PERFCTR_CTL@GOTPAGE
Lloh52:
	ldr	x8, [x8, _REG_A4XX_RBBM_PERFCTR_CTL@GOTPAGEOFF]
Lloh53:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
Lloh54:
	adrp	x8, _REG_A4XX_CP_PERFCTR_CP_SEL_0@GOTPAGE
Lloh55:
	ldr	x8, [x8, _REG_A4XX_CP_PERFCTR_CP_SEL_0@GOTPAGEOFF]
Lloh56:
	ldr	w1, [x8]
Lloh57:
	adrp	x8, _CP_ALWAYS_COUNT@GOTPAGE
Lloh58:
	ldr	x8, [x8, _CP_ALWAYS_COUNT@GOTPAGEOFF]
Lloh59:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_gpu_write
	mov	x0, x20
	bl	_adreno_is_a430
	cbz	x0, LBB0_8
; %bb.7:
Lloh60:
	adrp	x8, _REG_A4XX_UCHE_CACHE_WAYS_VFD@GOTPAGE
Lloh61:
	ldr	x8, [x8, _REG_A4XX_UCHE_CACHE_WAYS_VFD@GOTPAGEOFF]
Lloh62:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #7
	bl	_gpu_write
LBB0_8:
Lloh63:
	adrp	x8, _REG_A4XX_UCHE_TRAP_BASE_LO@GOTPAGE
Lloh64:
	ldr	x8, [x8, _REG_A4XX_UCHE_TRAP_BASE_LO@GOTPAGEOFF]
Lloh65:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-65536
	bl	_gpu_write
Lloh66:
	adrp	x8, _REG_A4XX_UCHE_TRAP_BASE_HI@GOTPAGE
Lloh67:
	ldr	x8, [x8, _REG_A4XX_UCHE_TRAP_BASE_HI@GOTPAGEOFF]
Lloh68:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-65536
	bl	_gpu_write
Lloh69:
	adrp	x8, _REG_A4XX_CP_DEBUG@GOTPAGE
Lloh70:
	ldr	x8, [x8, _REG_A4XX_CP_DEBUG@GOTPAGEOFF]
Lloh71:
	ldr	w21, [x8]
	mov	x0, x20
	bl	_adreno_is_a420
	cmp	x0, #0
	mov	w8, #570425344
	mov	w9, #33554432
	csel	w2, w9, w8, eq
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
	mov	x0, x20
	bl	_adreno_is_a420
	cbnz	x0, LBB0_10
; %bb.9:
Lloh72:
	adrp	x8, _REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0@GOTPAGE
Lloh73:
	ldr	x8, [x8, _REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0@GOTPAGEOFF]
Lloh74:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1089
	bl	_gpu_write
Lloh75:
	adrp	x8, _REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1@GOTPAGE
Lloh76:
	ldr	x8, [x8, _REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1@GOTPAGEOFF]
Lloh77:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1089
	bl	_gpu_write
LBB0_10:
	mov	x0, x19
	bl	_a4xx_enable_hwcg
	mov	x0, x20
	bl	_adreno_is_a420
	cbz	x0, LBB0_12
; %bb.11:
Lloh78:
	adrp	x21, _REG_A4XX_RBBM_CLOCK_DELAY_HLSQ@GOTPAGE
Lloh79:
	ldr	x21, [x21, _REG_A4XX_RBBM_CLOCK_DELAY_HLSQ@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_gpu_read
Lloh80:
	adrp	x8, _A4XX_CGC_HLSQ_EARLY_CYC__MASK@GOTPAGE
Lloh81:
	ldr	x8, [x8, _A4XX_CGC_HLSQ_EARLY_CYC__MASK@GOTPAGEOFF]
Lloh82:
	ldr	w8, [x8]
Lloh83:
	adrp	x9, _A4XX_CGC_HLSQ_EARLY_CYC__SHIFT@GOTPAGE
Lloh84:
	ldr	x9, [x9, _A4XX_CGC_HLSQ_EARLY_CYC__SHIFT@GOTPAGEOFF]
	bic	w8, w0, w8
Lloh85:
	ldr	w9, [x9]
	mov	w10, #2
	lsl	w9, w10, w9
	orr	w2, w9, w8
	ldr	w1, [x21]
	mov	x0, x19
	bl	_gpu_write
LBB0_12:
Lloh86:
	adrp	x8, _REG_A4XX_CP_PROTECT_CTRL@GOTPAGE
Lloh87:
	ldr	x8, [x8, _REG_A4XX_CP_PROTECT_CTRL@GOTPAGEOFF]
Lloh88:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #7
	bl	_gpu_write
	mov	w0, #0
	bl	_REG_A4XX_CP_PROTECT
	mov	x1, x0
	mov	x0, x19
	mov	w2, #16
	movk	w2, #25088, lsl #16
	bl	_gpu_write
	mov	w0, #1
	bl	_REG_A4XX_CP_PROTECT
	mov	x1, x0
	mov	x0, x19
	mov	w2, #32
	movk	w2, #25344, lsl #16
	bl	_gpu_write
	mov	w0, #2
	bl	_REG_A4XX_CP_PROTECT
	mov	x1, x0
	mov	w21, #64
	movk	w21, #25600, lsl #16
	mov	x0, x19
	mov	w2, #64
	movk	w2, #25600, lsl #16
	bl	_gpu_write
	mov	w0, #3
	bl	_REG_A4XX_CP_PROTECT
	mov	x1, x0
	mov	x0, x19
	mov	w2, #128
	movk	w2, #25856, lsl #16
	bl	_gpu_write
	mov	w0, #4
	bl	_REG_A4XX_CP_PROTECT
	mov	x1, x0
	mov	x0, x19
	mov	w2, #256
	movk	w2, #26112, lsl #16
	bl	_gpu_write
	mov	w0, #5
	bl	_REG_A4XX_CP_PROTECT
	mov	x1, x0
	add	w2, w21, #448
	mov	x0, x19
	bl	_gpu_write
	mov	w0, #6
	bl	_REG_A4XX_CP_PROTECT
	mov	x1, x0
	mov	x0, x19
	mov	w2, #2048
	movk	w2, #26368, lsl #16
	bl	_gpu_write
	mov	w0, #7
	bl	_REG_A4XX_CP_PROTECT
	mov	x1, x0
	mov	x0, x19
	mov	w2, #5632
	movk	w2, #25600, lsl #16
	bl	_gpu_write
	mov	w0, #8
	bl	_REG_A4XX_CP_PROTECT
	mov	x1, x0
	mov	w21, #13056
	movk	w21, #24576, lsl #16
	mov	x0, x19
	mov	w2, #13056
	movk	w2, #24576, lsl #16
	bl	_gpu_write
	mov	w0, #9
	bl	_REG_A4XX_CP_PROTECT
	mov	x1, x0
	add	w2, w21, #1280
	mov	x0, x19
	bl	_gpu_write
	mov	w0, #10
	bl	_REG_A4XX_CP_PROTECT
	mov	x1, x0
	mov	x0, x19
	mov	w2, #14720
	movk	w2, #24832, lsl #16
	bl	_gpu_write
	mov	w0, #11
	bl	_REG_A4XX_CP_PROTECT
	mov	x1, x0
	mov	x0, x19
	mov	w2, #1845559296
	bl	_gpu_write
Lloh89:
	adrp	x8, _REG_A4XX_RBBM_INT_0_MASK@GOTPAGE
Lloh90:
	ldr	x8, [x8, _REG_A4XX_RBBM_INT_0_MASK@GOTPAGEOFF]
Lloh91:
	ldr	w1, [x8]
Lloh92:
	adrp	x8, _A4XX_INT0_MASK@GOTPAGE
Lloh93:
	ldr	x8, [x8, _A4XX_INT0_MASK@GOTPAGEOFF]
Lloh94:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_gpu_write
	mov	x0, x19
	bl	_adreno_hw_init
	cbnz	w0, LBB0_20
; %bb.13:
	ldr	x8, [x20]
Lloh95:
	adrp	x9, _ADRENO_FW_PM4@GOTPAGE
Lloh96:
	ldr	x9, [x9, _ADRENO_FW_PM4@GOTPAGEOFF]
Lloh97:
	ldr	x9, [x9]
	ldr	x8, [x8, x9, lsl #3]
	ldr	x21, [x8, #8]
	ldr	w22, [x8]
	ldr	w1, [x21]
Lloh98:
	adrp	x0, l_.str@PAGE
Lloh99:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DBG
Lloh100:
	adrp	x8, _REG_A4XX_CP_ME_RAM_WADDR@GOTPAGE
Lloh101:
	ldr	x8, [x8, _REG_A4XX_CP_ME_RAM_WADDR@GOTPAGEOFF]
Lloh102:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
	cmp	w22, #8
	b.lt	LBB0_16
; %bb.14:
	lsr	x8, x22, #2
	add	x21, x21, #4
	sub	x22, x8, #1
Lloh103:
	adrp	x23, _REG_A4XX_CP_ME_RAM_DATA@GOTPAGE
Lloh104:
	ldr	x23, [x23, _REG_A4XX_CP_ME_RAM_DATA@GOTPAGEOFF]
LBB0_15:                                ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x23]
	ldr	w2, [x21], #4
	mov	x0, x19
	bl	_gpu_write
	subs	x22, x22, #1
	b.ne	LBB0_15
LBB0_16:
	ldr	x8, [x20]
Lloh105:
	adrp	x9, _ADRENO_FW_PFP@GOTPAGE
Lloh106:
	ldr	x9, [x9, _ADRENO_FW_PFP@GOTPAGEOFF]
Lloh107:
	ldr	x9, [x9]
	ldr	x8, [x8, x9, lsl #3]
	ldr	x20, [x8, #8]
	ldr	w21, [x8]
	ldr	w1, [x20]
Lloh108:
	adrp	x0, l_.str.1@PAGE
Lloh109:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DBG
Lloh110:
	adrp	x8, _REG_A4XX_CP_PFP_UCODE_ADDR@GOTPAGE
Lloh111:
	ldr	x8, [x8, _REG_A4XX_CP_PFP_UCODE_ADDR@GOTPAGEOFF]
Lloh112:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
	cmp	w21, #8
	b.lt	LBB0_19
; %bb.17:
	lsr	x8, x21, #2
	add	x20, x20, #4
	sub	x21, x8, #1
Lloh113:
	adrp	x22, _REG_A4XX_CP_PFP_UCODE_DATA@GOTPAGE
Lloh114:
	ldr	x22, [x22, _REG_A4XX_CP_PFP_UCODE_DATA@GOTPAGEOFF]
LBB0_18:                                ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x22]
	ldr	w2, [x20], #4
	mov	x0, x19
	bl	_gpu_write
	subs	x21, x21, #1
	b.ne	LBB0_18
LBB0_19:
Lloh115:
	adrp	x8, _REG_A4XX_CP_ME_CNTL@GOTPAGE
Lloh116:
	ldr	x8, [x8, _REG_A4XX_CP_ME_CNTL@GOTPAGEOFF]
Lloh117:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
	mov	x0, x19
	bl	_a4xx_me_init
Lloh118:
	adrp	x8, _EINVAL@GOTPAGE
Lloh119:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh120:
	ldr	w8, [x8]
	cmp	x0, #0
	csneg	w0, wzr, w8, ne
LBB0_20:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_21:
	bl	_BUG
	b	LBB0_4
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGot	Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpAdd	Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGot	Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpAdd	Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGot	Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.cfi_endproc
                                        ; -- End function
	.comm	_REG_A4XX_VBIF_ABIT_SORT,4,2    ; @REG_A4XX_VBIF_ABIT_SORT
	.comm	_REG_A4XX_VBIF_ABIT_SORT_CONF,4,2 ; @REG_A4XX_VBIF_ABIT_SORT_CONF
	.comm	_REG_A4XX_VBIF_GATE_OFF_WRREQ_EN,4,2 ; @REG_A4XX_VBIF_GATE_OFF_WRREQ_EN
	.comm	_REG_A4XX_VBIF_IN_RD_LIM_CONF0,4,2 ; @REG_A4XX_VBIF_IN_RD_LIM_CONF0
	.comm	_REG_A4XX_VBIF_IN_RD_LIM_CONF1,4,2 ; @REG_A4XX_VBIF_IN_RD_LIM_CONF1
	.comm	_REG_A4XX_VBIF_IN_WR_LIM_CONF0,4,2 ; @REG_A4XX_VBIF_IN_WR_LIM_CONF0
	.comm	_REG_A4XX_VBIF_IN_WR_LIM_CONF1,4,2 ; @REG_A4XX_VBIF_IN_WR_LIM_CONF1
	.comm	_REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB,4,2 ; @REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB
	.comm	_REG_A4XX_RBBM_GPU_BUSY_MASKED,4,2 ; @REG_A4XX_RBBM_GPU_BUSY_MASKED
	.comm	_REG_A4XX_RBBM_SP_HYST_CNT,4,2  ; @REG_A4XX_RBBM_SP_HYST_CNT
	.comm	_REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL,4,2 ; @REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL
	.comm	_REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2,4,2 ; @REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2
	.comm	_REG_A4XX_RBBM_AHB_CTL0,4,2     ; @REG_A4XX_RBBM_AHB_CTL0
	.comm	_REG_A4XX_RBBM_AHB_CTL1,4,2     ; @REG_A4XX_RBBM_AHB_CTL1
	.comm	_REG_A4XX_RBBM_RBBM_CTL,4,2     ; @REG_A4XX_RBBM_RBBM_CTL
	.comm	_REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL,4,2 ; @REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL
	.comm	_REG_A4XX_RB_GMEM_BASE_ADDR,4,2 ; @REG_A4XX_RB_GMEM_BASE_ADDR
	.comm	_REG_A4XX_RBBM_PERFCTR_CTL,4,2  ; @REG_A4XX_RBBM_PERFCTR_CTL
	.comm	_REG_A4XX_CP_PERFCTR_CP_SEL_0,4,2 ; @REG_A4XX_CP_PERFCTR_CP_SEL_0
	.comm	_CP_ALWAYS_COUNT,4,2            ; @CP_ALWAYS_COUNT
	.comm	_REG_A4XX_UCHE_CACHE_WAYS_VFD,4,2 ; @REG_A4XX_UCHE_CACHE_WAYS_VFD
	.comm	_REG_A4XX_UCHE_TRAP_BASE_LO,4,2 ; @REG_A4XX_UCHE_TRAP_BASE_LO
	.comm	_REG_A4XX_UCHE_TRAP_BASE_HI,4,2 ; @REG_A4XX_UCHE_TRAP_BASE_HI
	.comm	_REG_A4XX_CP_DEBUG,4,2          ; @REG_A4XX_CP_DEBUG
	.comm	_REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0,4,2 ; @REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0
	.comm	_REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1,4,2 ; @REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1
	.comm	_REG_A4XX_RBBM_CLOCK_DELAY_HLSQ,4,2 ; @REG_A4XX_RBBM_CLOCK_DELAY_HLSQ
	.comm	_A4XX_CGC_HLSQ_EARLY_CYC__MASK,4,2 ; @A4XX_CGC_HLSQ_EARLY_CYC__MASK
	.comm	_A4XX_CGC_HLSQ_EARLY_CYC__SHIFT,4,2 ; @A4XX_CGC_HLSQ_EARLY_CYC__SHIFT
	.comm	_REG_A4XX_CP_PROTECT_CTRL,4,2   ; @REG_A4XX_CP_PROTECT_CTRL
	.comm	_REG_A4XX_RBBM_INT_0_MASK,4,2   ; @REG_A4XX_RBBM_INT_0_MASK
	.comm	_A4XX_INT0_MASK,4,2             ; @A4XX_INT0_MASK
	.comm	_ADRENO_FW_PM4,8,3              ; @ADRENO_FW_PM4
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"loading PM4 ucode version: %u"

	.comm	_REG_A4XX_CP_ME_RAM_WADDR,4,2   ; @REG_A4XX_CP_ME_RAM_WADDR
	.comm	_REG_A4XX_CP_ME_RAM_DATA,4,2    ; @REG_A4XX_CP_ME_RAM_DATA
	.comm	_ADRENO_FW_PFP,8,3              ; @ADRENO_FW_PFP
l_.str.1:                               ; @.str.1
	.asciz	"loading PFP ucode version: %u"

	.comm	_REG_A4XX_CP_PFP_UCODE_ADDR,4,2 ; @REG_A4XX_CP_PFP_UCODE_ADDR
	.comm	_REG_A4XX_CP_PFP_UCODE_DATA,4,2 ; @REG_A4XX_CP_PFP_UCODE_DATA
	.comm	_REG_A4XX_CP_ME_CNTL,4,2        ; @REG_A4XX_CP_ME_CNTL
	.comm	_EINVAL,4,2                     ; @EINVAL
	.no_dead_strip	_a4xx_hw_init
.subsections_via_symbols
