	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v10_0_sw_init
_gfx_v10_0_sw_init:                     ## @gfx_v10_0_sw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r13
	movl	(%rdi), %eax
	addl	$-128, %eax
	xorl	%ecx, %ecx
	cmpl	$3, %eax
	movl	$1, 28(%rdi)
	adcl	$1, %ecx
	movl	%ecx, 32(%rdi)
	movl	$1, 36(%rdi)
	movl	%ecx, 16(%rdi)
	movabsq	$34359738372, %rax              ## imm = 0x800000004
	movq	%rax, 20(%rdi)
	movq	_SOC15_IH_CLIENTID_GRBM_CP@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	leaq	8(%rdi), %r14
	movq	%r14, %rcx
	callq	_amdgpu_irq_add_id
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_41
## %bb.1:
	movl	(%r15), %esi
	movq	_GFX_10_1__SRCID__CP_EOP_INTERRUPT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	leaq	52(%r13), %rcx
	movq	%r13, %rdi
	callq	_amdgpu_irq_add_id
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_41
## %bb.2:
	movl	(%r15), %esi
	movq	_GFX_10_1__SRCID__CP_PRIV_REG_FAULT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	leaq	48(%r13), %rcx
	movq	%r13, %rdi
	callq	_amdgpu_irq_add_id
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_41
## %bb.3:
	movl	(%r15), %esi
	movq	_GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	leaq	44(%r13), %rcx
	movq	%r13, %rdi
	callq	_amdgpu_irq_add_id
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_41
## %bb.4:
	movq	_AMDGPU_GFX_NORMAL_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 40(%r13)
	movq	%r13, %rdi
	callq	_gfx_v10_0_scratch_init
	movq	%r13, %rdi
	callq	_gfx_v10_0_me_init
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_41
## %bb.5:
	movq	%r13, %rdi
	callq	_gfx_v10_0_rlc_init
	testl	%eax, %eax
	je	LBB0_7
## %bb.6:
	movl	%eax, %ebx
	leaq	L_.str(%rip), %rdi
	jmp	LBB0_40
LBB0_7:
	movq	%r13, %rdi
	callq	_gfx_v10_0_mec_init
	testl	%eax, %eax
	je	LBB0_9
## %bb.8:
	movl	%eax, %ebx
	leaq	L_.str.1(%rip), %rdi
LBB0_40:
	callq	_DRM_ERROR
LBB0_41:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_9:
	movl	28(%r13), %ecx
	testl	%ecx, %ecx
	jle	LBB0_24
## %bb.10:
	movl	36(%r13), %eax
	movl	$0, -44(%rbp)                   ## 4-byte Folded Spill
	xorl	%r15d, %r15d
LBB0_11:                                ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_15 Depth 2
                                        ##       Child Loop BB0_19 Depth 3
	testl	%eax, %eax
	jle	LBB0_23
## %bb.12:                              ##   in Loop: Header=BB0_11 Depth=1
	movl	32(%r13), %edx
	xorl	%ebx, %ebx
	jmp	LBB0_15
LBB0_13:                                ##   in Loop: Header=BB0_15 Depth=2
	movl	36(%r13), %eax
LBB0_14:                                ##   in Loop: Header=BB0_15 Depth=2
	incl	%ebx
	cmpl	%eax, %ebx
	jge	LBB0_22
LBB0_15:                                ##   Parent Loop BB0_11 Depth=1
                                        ## =>  This Loop Header: Depth=2
                                        ##       Child Loop BB0_19 Depth 3
	testl	%edx, %edx
	jle	LBB0_14
## %bb.16:                              ##   in Loop: Header=BB0_15 Depth=2
	xorl	%r12d, %r12d
	movl	%ebx, -48(%rbp)                 ## 4-byte Spill
	jmp	LBB0_19
LBB0_17:                                ##   in Loop: Header=BB0_19 Depth=3
	incl	%r15d
	movl	-48(%rbp), %ebx                 ## 4-byte Reload
LBB0_18:                                ##   in Loop: Header=BB0_19 Depth=3
	incl	%r12d
	movl	32(%r13), %edx
	cmpl	%edx, %r12d
	jge	LBB0_13
LBB0_19:                                ##   Parent Loop BB0_11 Depth=1
                                        ##     Parent Loop BB0_15 Depth=2
                                        ## =>    This Inner Loop Header: Depth=3
	movq	%r13, %rdi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	movl	%r12d, %edx
	movl	%ebx, %ecx
	callq	_amdgpu_gfx_is_me_queue_enabled
	testl	%eax, %eax
	je	LBB0_18
## %bb.20:                              ##   in Loop: Header=BB0_19 Depth=3
	movq	%r13, %rdi
	movl	%r15d, %esi
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	movl	%r12d, %ecx
	movl	%ebx, %r8d
	callq	_gfx_v10_0_gfx_ring_init
	testl	%eax, %eax
	je	LBB0_17
	jmp	LBB0_21
LBB0_22:                                ##   in Loop: Header=BB0_11 Depth=1
	movl	28(%r13), %ecx
LBB0_23:                                ##   in Loop: Header=BB0_11 Depth=1
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	incl	%edx
	movl	%edx, -44(%rbp)                 ## 4-byte Spill
	cmpl	%ecx, %edx
	jl	LBB0_11
LBB0_24:
	movl	16(%r13), %ecx
	testl	%ecx, %ecx
	jle	LBB0_38
## %bb.25:
	movl	24(%r13), %eax
	movl	$0, -44(%rbp)                   ## 4-byte Folded Spill
	xorl	%r15d, %r15d
LBB0_26:                                ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_30 Depth 2
                                        ##       Child Loop BB0_33 Depth 3
	testl	%eax, %eax
	jle	LBB0_37
## %bb.27:                              ##   in Loop: Header=BB0_26 Depth=1
	movl	20(%r13), %edx
	xorl	%ebx, %ebx
	jmp	LBB0_30
LBB0_28:                                ##   in Loop: Header=BB0_30 Depth=2
	movl	24(%r13), %eax
LBB0_29:                                ##   in Loop: Header=BB0_30 Depth=2
	incl	%ebx
	cmpl	%eax, %ebx
	jge	LBB0_36
LBB0_30:                                ##   Parent Loop BB0_26 Depth=1
                                        ## =>  This Loop Header: Depth=2
                                        ##       Child Loop BB0_33 Depth 3
	testl	%edx, %edx
	jle	LBB0_29
## %bb.31:                              ##   in Loop: Header=BB0_30 Depth=2
	xorl	%r12d, %r12d
	movl	%ebx, -48(%rbp)                 ## 4-byte Spill
	jmp	LBB0_33
LBB0_32:                                ##   in Loop: Header=BB0_33 Depth=3
	incl	%r12d
	movl	20(%r13), %edx
	cmpl	%edx, %r12d
	jge	LBB0_28
LBB0_33:                                ##   Parent Loop BB0_26 Depth=1
                                        ##     Parent Loop BB0_30 Depth=2
                                        ## =>    This Inner Loop Header: Depth=3
	movq	%r13, %rdi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	movl	%r12d, %edx
	movl	%ebx, %ecx
	callq	_amdgpu_gfx_is_mec_queue_enabled
	testl	%eax, %eax
	je	LBB0_32
## %bb.34:                              ##   in Loop: Header=BB0_33 Depth=3
	movq	%r13, %rdi
	movl	%r15d, %esi
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	movl	%r12d, %ecx
	movl	%ebx, %r8d
	callq	_gfx_v10_0_compute_ring_init
	testl	%eax, %eax
	jne	LBB0_21
## %bb.35:                              ##   in Loop: Header=BB0_33 Depth=3
	incl	%r15d
	movl	-48(%rbp), %ebx                 ## 4-byte Reload
	jmp	LBB0_32
LBB0_36:                                ##   in Loop: Header=BB0_26 Depth=1
	movl	16(%r13), %ecx
LBB0_37:                                ##   in Loop: Header=BB0_26 Depth=1
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	incl	%edx
	movl	%edx, -44(%rbp)                 ## 4-byte Spill
	cmpl	%ecx, %edx
	jl	LBB0_26
LBB0_38:
	movq	_GFX10_MEC_HPD_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_amdgpu_gfx_kiq_init
	testl	%eax, %eax
	je	LBB0_42
## %bb.39:
	movl	%eax, %ebx
	leaq	L_.str.2(%rip), %rdi
	jmp	LBB0_40
LBB0_21:
	movl	%eax, %ebx
	jmp	LBB0_41
LBB0_42:
	leaq	12(%r13), %rsi
	movq	%r13, %rdi
	movq	%r14, %rdx
	callq	_amdgpu_gfx_kiq_init_ring
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_41
## %bb.43:
	movq	%r13, %rdi
	movl	$4, %esi
	callq	_amdgpu_gfx_mqd_sw_init
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_41
## %bb.44:
	movq	56(%r13), %rax
	movq	_AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_46
## %bb.45:
	movq	%r13, %rdi
	callq	_gfx_v10_0_rlc_backdoor_autoload_buffer_init
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_41
LBB0_46:
	movq	_F32_CE_PROGRAM_RAM_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 4(%r13)
	movq	%r13, %rdi
	callq	_gfx_v10_0_gpu_early_init
	xorl	%ebx, %ebx
	jmp	LBB0_41
	.cfi_endproc
                                        ## -- End function
	.comm	_SOC15_IH_CLIENTID_GRBM_CP,4,2  ## @SOC15_IH_CLIENTID_GRBM_CP
	.comm	_GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,4,2 ## @GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT
	.comm	_GFX_10_1__SRCID__CP_EOP_INTERRUPT,4,2 ## @GFX_10_1__SRCID__CP_EOP_INTERRUPT
	.comm	_GFX_10_1__SRCID__CP_PRIV_REG_FAULT,4,2 ## @GFX_10_1__SRCID__CP_PRIV_REG_FAULT
	.comm	_GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,4,2 ## @GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT
	.comm	_AMDGPU_GFX_NORMAL_MODE,4,2     ## @AMDGPU_GFX_NORMAL_MODE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Failed to init rlc BOs!\n"

L_.str.1:                               ## @.str.1
	.asciz	"Failed to init MEC BOs!\n"

	.comm	_GFX10_MEC_HPD_SIZE,4,2         ## @GFX10_MEC_HPD_SIZE
L_.str.2:                               ## @.str.2
	.asciz	"Failed to init KIQ BOs!\n"

	.comm	_AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,8,3 ## @AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO
	.comm	_F32_CE_PROGRAM_RAM_SIZE,4,2    ## @F32_CE_PROGRAM_RAM_SIZE
	.no_dead_strip	_gfx_v10_0_sw_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3                               ; -- Begin function gfx_v10_0_sw_init
lCPI0_0:
	.long	4                               ; 0x4
	.long	8                               ; 0x8
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	2
_gfx_v10_0_sw_init:                     ; @gfx_v10_0_sw_init
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldr	w8, [x0]
	sub	w8, w8, #128
	mov	w9, #1
	cmp	w8, #3
	cinc	w8, w9, lo
	stp	w9, w8, [x0, #28]
	str	w9, [x0, #36]
	str	w8, [x0, #16]
Lloh0:
	adrp	x8, lCPI0_0@PAGE
Lloh1:
	ldr	d0, [x8, lCPI0_0@PAGEOFF]
Lloh2:
	adrp	x21, _SOC15_IH_CLIENTID_GRBM_CP@GOTPAGE
Lloh3:
	ldr	x21, [x21, _SOC15_IH_CLIENTID_GRBM_CP@GOTPAGEOFF]
	stur	d0, [x0, #20]
	ldr	w1, [x21]
Lloh4:
	adrp	x8, _GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT@GOTPAGE
Lloh5:
	ldr	x8, [x8, _GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT@GOTPAGEOFF]
Lloh6:
	ldr	w2, [x8]
	add	x20, x0, #8
	mov	x3, x20
	bl	_amdgpu_irq_add_id
	mov	x23, x0
	cbnz	w0, LBB0_10
; %bb.1:
	ldr	w1, [x21]
Lloh7:
	adrp	x8, _GFX_10_1__SRCID__CP_EOP_INTERRUPT@GOTPAGE
Lloh8:
	ldr	x8, [x8, _GFX_10_1__SRCID__CP_EOP_INTERRUPT@GOTPAGEOFF]
Lloh9:
	ldr	w2, [x8]
	add	x3, x19, #52
	mov	x0, x19
	bl	_amdgpu_irq_add_id
	mov	x23, x0
	cbnz	w0, LBB0_10
; %bb.2:
	ldr	w1, [x21]
Lloh10:
	adrp	x8, _GFX_10_1__SRCID__CP_PRIV_REG_FAULT@GOTPAGE
Lloh11:
	ldr	x8, [x8, _GFX_10_1__SRCID__CP_PRIV_REG_FAULT@GOTPAGEOFF]
Lloh12:
	ldr	w2, [x8]
	add	x3, x19, #48
	mov	x0, x19
	bl	_amdgpu_irq_add_id
	mov	x23, x0
	cbnz	w0, LBB0_10
; %bb.3:
	ldr	w1, [x21]
Lloh13:
	adrp	x8, _GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT@GOTPAGE
Lloh14:
	ldr	x8, [x8, _GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT@GOTPAGEOFF]
Lloh15:
	ldr	w2, [x8]
	add	x3, x19, #44
	mov	x0, x19
	bl	_amdgpu_irq_add_id
	mov	x23, x0
	cbnz	w0, LBB0_10
; %bb.4:
Lloh16:
	adrp	x8, _AMDGPU_GFX_NORMAL_MODE@GOTPAGE
Lloh17:
	ldr	x8, [x8, _AMDGPU_GFX_NORMAL_MODE@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	str	w8, [x19, #40]
	mov	x0, x19
	bl	_gfx_v10_0_scratch_init
	mov	x0, x19
	bl	_gfx_v10_0_me_init
	mov	x23, x0
	cbnz	w0, LBB0_10
; %bb.5:
	mov	x0, x19
	bl	_gfx_v10_0_rlc_init
	cbz	w0, LBB0_7
; %bb.6:
	mov	x23, x0
Lloh19:
	adrp	x0, l_.str@PAGE
Lloh20:
	add	x0, x0, l_.str@PAGEOFF
	b	LBB0_9
LBB0_7:
	mov	x0, x19
	bl	_gfx_v10_0_mec_init
	cbz	w0, LBB0_11
; %bb.8:
	mov	x23, x0
Lloh21:
	adrp	x0, l_.str.1@PAGE
Lloh22:
	add	x0, x0, l_.str.1@PAGEOFF
LBB0_9:
	bl	_DRM_ERROR
LBB0_10:
	mov	x0, x23
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_11:
	ldr	w9, [x19, #28]
	cmp	w9, #1
	b.lt	LBB0_25
; %bb.12:
	mov	w21, #0
	mov	w22, #0
	ldr	w8, [x19, #36]
LBB0_13:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_17 Depth 2
                                        ;       Child Loop BB0_21 Depth 3
	cmp	w8, #1
	b.lt	LBB0_24
; %bb.14:                               ;   in Loop: Header=BB0_13 Depth=1
	mov	w24, #0
	ldr	w9, [x19, #32]
	b	LBB0_17
LBB0_15:                                ;   in Loop: Header=BB0_17 Depth=2
	ldr	w8, [x19, #36]
LBB0_16:                                ;   in Loop: Header=BB0_17 Depth=2
	add	w24, w24, #1
	cmp	w24, w8
	b.ge	LBB0_23
LBB0_17:                                ;   Parent Loop BB0_13 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_21 Depth 3
	cmp	w9, #1
	b.lt	LBB0_16
; %bb.18:                               ;   in Loop: Header=BB0_17 Depth=2
	mov	w25, #0
	b	LBB0_21
LBB0_19:                                ;   in Loop: Header=BB0_21 Depth=3
	add	w22, w22, #1
LBB0_20:                                ;   in Loop: Header=BB0_21 Depth=3
	add	w25, w25, #1
	ldr	w9, [x19, #32]
	cmp	w25, w9
	b.ge	LBB0_15
LBB0_21:                                ;   Parent Loop BB0_13 Depth=1
                                        ;     Parent Loop BB0_17 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	mov	x0, x19
	mov	x1, x21
	mov	x2, x25
	mov	x3, x24
	bl	_amdgpu_gfx_is_me_queue_enabled
	cbz	w0, LBB0_20
; %bb.22:                               ;   in Loop: Header=BB0_21 Depth=3
	mov	x0, x19
	mov	x1, x22
	mov	x2, x21
	mov	x3, x25
	mov	x4, x24
	bl	_gfx_v10_0_gfx_ring_init
	cbz	w0, LBB0_19
	b	LBB0_41
LBB0_23:                                ;   in Loop: Header=BB0_13 Depth=1
	ldr	w9, [x19, #28]
LBB0_24:                                ;   in Loop: Header=BB0_13 Depth=1
	add	w21, w21, #1
	cmp	w21, w9
	b.lt	LBB0_13
LBB0_25:
	ldr	w9, [x19, #16]
	cmp	w9, #1
	b.lt	LBB0_39
; %bb.26:
	mov	w21, #0
	mov	w22, #0
	ldr	w8, [x19, #24]
LBB0_27:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_31 Depth 2
                                        ;       Child Loop BB0_34 Depth 3
	cmp	w8, #1
	b.lt	LBB0_38
; %bb.28:                               ;   in Loop: Header=BB0_27 Depth=1
	mov	w24, #0
	ldr	w9, [x19, #20]
	b	LBB0_31
LBB0_29:                                ;   in Loop: Header=BB0_31 Depth=2
	ldr	w8, [x19, #24]
LBB0_30:                                ;   in Loop: Header=BB0_31 Depth=2
	add	w24, w24, #1
	cmp	w24, w8
	b.ge	LBB0_37
LBB0_31:                                ;   Parent Loop BB0_27 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_34 Depth 3
	cmp	w9, #1
	b.lt	LBB0_30
; %bb.32:                               ;   in Loop: Header=BB0_31 Depth=2
	mov	w25, #0
	b	LBB0_34
LBB0_33:                                ;   in Loop: Header=BB0_34 Depth=3
	add	w25, w25, #1
	ldr	w9, [x19, #20]
	cmp	w25, w9
	b.ge	LBB0_29
LBB0_34:                                ;   Parent Loop BB0_27 Depth=1
                                        ;     Parent Loop BB0_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	mov	x0, x19
	mov	x1, x21
	mov	x2, x25
	mov	x3, x24
	bl	_amdgpu_gfx_is_mec_queue_enabled
	cbz	w0, LBB0_33
; %bb.35:                               ;   in Loop: Header=BB0_34 Depth=3
	mov	x0, x19
	mov	x1, x22
	mov	x2, x21
	mov	x3, x25
	mov	x4, x24
	bl	_gfx_v10_0_compute_ring_init
	cbnz	w0, LBB0_41
; %bb.36:                               ;   in Loop: Header=BB0_34 Depth=3
	add	w22, w22, #1
	b	LBB0_33
LBB0_37:                                ;   in Loop: Header=BB0_27 Depth=1
	ldr	w9, [x19, #16]
LBB0_38:                                ;   in Loop: Header=BB0_27 Depth=1
	add	w21, w21, #1
	cmp	w21, w9
	b.lt	LBB0_27
LBB0_39:
Lloh23:
	adrp	x8, _GFX10_MEC_HPD_SIZE@GOTPAGE
Lloh24:
	ldr	x8, [x8, _GFX10_MEC_HPD_SIZE@GOTPAGEOFF]
Lloh25:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_amdgpu_gfx_kiq_init
	cbz	w0, LBB0_42
; %bb.40:
	mov	x23, x0
Lloh26:
	adrp	x0, l_.str.2@PAGE
Lloh27:
	add	x0, x0, l_.str.2@PAGEOFF
	b	LBB0_9
LBB0_41:
	mov	x23, x0
	b	LBB0_10
LBB0_42:
	add	x1, x19, #12
	mov	x0, x19
	mov	x2, x20
	bl	_amdgpu_gfx_kiq_init_ring
	mov	x23, x0
	cbnz	w0, LBB0_10
; %bb.43:
	mov	x0, x19
	mov	w1, #4
	bl	_amdgpu_gfx_mqd_sw_init
	mov	x23, x0
	cbnz	w0, LBB0_10
; %bb.44:
	ldr	x8, [x19, #56]
Lloh28:
	adrp	x9, _AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO@GOTPAGE
Lloh29:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO@GOTPAGEOFF]
Lloh30:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_46
; %bb.45:
	mov	x0, x19
	bl	_gfx_v10_0_rlc_backdoor_autoload_buffer_init
	mov	x23, x0
	cbnz	w0, LBB0_10
LBB0_46:
Lloh31:
	adrp	x8, _F32_CE_PROGRAM_RAM_SIZE@GOTPAGE
Lloh32:
	ldr	x8, [x8, _F32_CE_PROGRAM_RAM_SIZE@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
	str	w8, [x19, #4]
	mov	x0, x19
	bl	_gfx_v10_0_gpu_early_init
	mov	w23, #0
	b	LBB0_10
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpAdrp	Lloh0, Lloh4
	.loh AdrpLdr	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpAdd	Lloh19, Lloh20
	.loh AdrpAdd	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpAdd	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.cfi_endproc
                                        ; -- End function
	.comm	_SOC15_IH_CLIENTID_GRBM_CP,4,2  ; @SOC15_IH_CLIENTID_GRBM_CP
	.comm	_GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,4,2 ; @GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT
	.comm	_GFX_10_1__SRCID__CP_EOP_INTERRUPT,4,2 ; @GFX_10_1__SRCID__CP_EOP_INTERRUPT
	.comm	_GFX_10_1__SRCID__CP_PRIV_REG_FAULT,4,2 ; @GFX_10_1__SRCID__CP_PRIV_REG_FAULT
	.comm	_GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,4,2 ; @GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT
	.comm	_AMDGPU_GFX_NORMAL_MODE,4,2     ; @AMDGPU_GFX_NORMAL_MODE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Failed to init rlc BOs!\n"

l_.str.1:                               ; @.str.1
	.asciz	"Failed to init MEC BOs!\n"

	.comm	_GFX10_MEC_HPD_SIZE,4,2         ; @GFX10_MEC_HPD_SIZE
l_.str.2:                               ; @.str.2
	.asciz	"Failed to init KIQ BOs!\n"

	.comm	_AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,8,3 ; @AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO
	.comm	_F32_CE_PROGRAM_RAM_SIZE,4,2    ; @F32_CE_PROGRAM_RAM_SIZE
	.no_dead_strip	_gfx_v10_0_sw_init
.subsections_via_symbols
