	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function cik_disable_interrupt_state
_cik_disable_interrupt_state:           ## @cik_disable_interrupt_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	_CP_INT_CNTL_RING0@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	callq	_RREG32
	movq	_CNTX_BUSY_INT_ENABLE@GOTPCREL(%rip), %rcx
	movq	_CNTX_EMPTY_INT_ENABLE@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	andl	%eax, %esi
	movq	(%rbx), %rdi
	callq	_WREG32
	movq	_SDMA0_CNTL@GOTPCREL(%rip), %rbx
	movq	_SDMA0_REGISTER_OFFSET@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	addq	(%rbx), %rdi
	callq	_RREG32
	movq	_TRAP_ENABLE@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	notl	%esi
	andl	%eax, %esi
	movq	(%r14), %rdi
	addq	(%rbx), %rdi
	callq	_WREG32
	movq	_SDMA1_REGISTER_OFFSET@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	addq	(%rbx), %rdi
	callq	_RREG32
	movl	(%r15), %esi
	notl	%esi
	andl	%eax, %esi
	movq	(%r14), %rdi
	addq	(%rbx), %rdi
	callq	_WREG32
	movq	_CP_ME1_PIPE0_INT_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CP_ME1_PIPE1_INT_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CP_ME1_PIPE2_INT_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CP_ME1_PIPE3_INT_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CP_ME2_PIPE0_INT_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CP_ME2_PIPE1_INT_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CP_ME2_PIPE2_INT_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CP_ME2_PIPE3_INT_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_GRBM_INT_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_SRBM_INT_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_LB_INTERRUPT_MASK@GOTPCREL(%rip), %rbx
	movq	_EVERGREEN_CRTC0_REGISTER_OFFSET@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	addq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_EVERGREEN_CRTC1_REGISTER_OFFSET@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	addq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r12), %eax
	cmpl	$4, %eax
	jl	LBB0_3
## %bb.1:
	movq	_EVERGREEN_CRTC2_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_EVERGREEN_CRTC3_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r12), %eax
	cmpl	$6, %eax
	jl	LBB0_3
## %bb.2:
	movq	_EVERGREEN_CRTC4_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_EVERGREEN_CRTC5_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r12), %eax
LBB0_3:
	cmpl	$2, %eax
	jl	LBB0_7
## %bb.4:
	movq	_GRPH_INT_CONTROL@GOTPCREL(%rip), %rbx
	movq	(%r14), %rdi
	addq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%r15), %rdi
	addq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	cmpl	$4, (%r12)
	jl	LBB0_7
## %bb.5:
	movq	_EVERGREEN_CRTC2_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_EVERGREEN_CRTC3_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	cmpl	$6, (%r12)
	jl	LBB0_7
## %bb.6:
	movq	_EVERGREEN_CRTC4_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_EVERGREEN_CRTC5_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	_WREG32
LBB0_7:
	movq	_DAC_AUTODETECT_INT_CONTROL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_DC_HPD1_INT_CONTROL@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	callq	_RREG32
	movq	_DC_HPDx_INT_POLARITY@GOTPCREL(%rip), %r14
	andl	(%r14), %eax
	movq	(%rbx), %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	_DC_HPD2_INT_CONTROL@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	callq	_RREG32
	andl	(%r14), %eax
	movq	(%rbx), %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	_DC_HPD3_INT_CONTROL@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	callq	_RREG32
	andl	(%r14), %eax
	movq	(%rbx), %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	_DC_HPD4_INT_CONTROL@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	callq	_RREG32
	andl	(%r14), %eax
	movq	(%rbx), %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	_DC_HPD5_INT_CONTROL@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	callq	_RREG32
	andl	(%r14), %eax
	movq	(%rbx), %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	_DC_HPD6_INT_CONTROL@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	callq	_RREG32
	andl	(%r14), %eax
	movq	(%rbx), %rdi
	movl	%eax, %esi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_CP_INT_CNTL_RING0,8,3          ## @CP_INT_CNTL_RING0
	.comm	_CNTX_BUSY_INT_ENABLE,4,2       ## @CNTX_BUSY_INT_ENABLE
	.comm	_CNTX_EMPTY_INT_ENABLE,4,2      ## @CNTX_EMPTY_INT_ENABLE
	.comm	_SDMA0_CNTL,8,3                 ## @SDMA0_CNTL
	.comm	_SDMA0_REGISTER_OFFSET,8,3      ## @SDMA0_REGISTER_OFFSET
	.comm	_TRAP_ENABLE,4,2                ## @TRAP_ENABLE
	.comm	_SDMA1_REGISTER_OFFSET,8,3      ## @SDMA1_REGISTER_OFFSET
	.comm	_CP_ME1_PIPE0_INT_CNTL,8,3      ## @CP_ME1_PIPE0_INT_CNTL
	.comm	_CP_ME1_PIPE1_INT_CNTL,8,3      ## @CP_ME1_PIPE1_INT_CNTL
	.comm	_CP_ME1_PIPE2_INT_CNTL,8,3      ## @CP_ME1_PIPE2_INT_CNTL
	.comm	_CP_ME1_PIPE3_INT_CNTL,8,3      ## @CP_ME1_PIPE3_INT_CNTL
	.comm	_CP_ME2_PIPE0_INT_CNTL,8,3      ## @CP_ME2_PIPE0_INT_CNTL
	.comm	_CP_ME2_PIPE1_INT_CNTL,8,3      ## @CP_ME2_PIPE1_INT_CNTL
	.comm	_CP_ME2_PIPE2_INT_CNTL,8,3      ## @CP_ME2_PIPE2_INT_CNTL
	.comm	_CP_ME2_PIPE3_INT_CNTL,8,3      ## @CP_ME2_PIPE3_INT_CNTL
	.comm	_GRBM_INT_CNTL,8,3              ## @GRBM_INT_CNTL
	.comm	_SRBM_INT_CNTL,8,3              ## @SRBM_INT_CNTL
	.comm	_LB_INTERRUPT_MASK,8,3          ## @LB_INTERRUPT_MASK
	.comm	_EVERGREEN_CRTC0_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC0_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC1_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC1_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC2_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC2_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC3_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC3_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC4_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC4_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC5_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC5_REGISTER_OFFSET
	.comm	_GRPH_INT_CONTROL,8,3           ## @GRPH_INT_CONTROL
	.comm	_DAC_AUTODETECT_INT_CONTROL,8,3 ## @DAC_AUTODETECT_INT_CONTROL
	.comm	_DC_HPD1_INT_CONTROL,8,3        ## @DC_HPD1_INT_CONTROL
	.comm	_DC_HPDx_INT_POLARITY,4,2       ## @DC_HPDx_INT_POLARITY
	.comm	_DC_HPD2_INT_CONTROL,8,3        ## @DC_HPD2_INT_CONTROL
	.comm	_DC_HPD3_INT_CONTROL,8,3        ## @DC_HPD3_INT_CONTROL
	.comm	_DC_HPD4_INT_CONTROL,8,3        ## @DC_HPD4_INT_CONTROL
	.comm	_DC_HPD5_INT_CONTROL,8,3        ## @DC_HPD5_INT_CONTROL
	.comm	_DC_HPD6_INT_CONTROL,8,3        ## @DC_HPD6_INT_CONTROL
	.no_dead_strip	_cik_disable_interrupt_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cik_disable_interrupt_state
_cik_disable_interrupt_state:           ; @cik_disable_interrupt_state
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x20, _CP_INT_CNTL_RING0@GOTPAGE
Lloh1:
	ldr	x20, [x20, _CP_INT_CNTL_RING0@GOTPAGEOFF]
	ldr	x0, [x20]
	bl	_RREG32
Lloh2:
	adrp	x8, _CNTX_BUSY_INT_ENABLE@GOTPAGE
Lloh3:
	ldr	x8, [x8, _CNTX_BUSY_INT_ENABLE@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
Lloh5:
	adrp	x9, _CNTX_EMPTY_INT_ENABLE@GOTPAGE
Lloh6:
	ldr	x9, [x9, _CNTX_EMPTY_INT_ENABLE@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	orr	w8, w9, w8
	and	w1, w8, w0
	ldr	x0, [x20]
	bl	_WREG32
Lloh8:
	adrp	x20, _SDMA0_CNTL@GOTPAGE
Lloh9:
	ldr	x20, [x20, _SDMA0_CNTL@GOTPAGEOFF]
	ldr	x8, [x20]
Lloh10:
	adrp	x21, _SDMA0_REGISTER_OFFSET@GOTPAGE
Lloh11:
	ldr	x21, [x21, _SDMA0_REGISTER_OFFSET@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_RREG32
Lloh12:
	adrp	x22, _TRAP_ENABLE@GOTPAGE
Lloh13:
	ldr	x22, [x22, _TRAP_ENABLE@GOTPAGEOFF]
	ldr	w8, [x22]
	bic	w1, w0, w8
	ldr	x8, [x20]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_WREG32
	ldr	x8, [x20]
Lloh14:
	adrp	x21, _SDMA1_REGISTER_OFFSET@GOTPAGE
Lloh15:
	ldr	x21, [x21, _SDMA1_REGISTER_OFFSET@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_RREG32
	ldr	w8, [x22]
	bic	w1, w0, w8
	ldr	x8, [x20]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_WREG32
Lloh16:
	adrp	x8, _CP_ME1_PIPE0_INT_CNTL@GOTPAGE
Lloh17:
	ldr	x8, [x8, _CP_ME1_PIPE0_INT_CNTL@GOTPAGEOFF]
Lloh18:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh19:
	adrp	x8, _CP_ME1_PIPE1_INT_CNTL@GOTPAGE
Lloh20:
	ldr	x8, [x8, _CP_ME1_PIPE1_INT_CNTL@GOTPAGEOFF]
Lloh21:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh22:
	adrp	x8, _CP_ME1_PIPE2_INT_CNTL@GOTPAGE
Lloh23:
	ldr	x8, [x8, _CP_ME1_PIPE2_INT_CNTL@GOTPAGEOFF]
Lloh24:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh25:
	adrp	x8, _CP_ME1_PIPE3_INT_CNTL@GOTPAGE
Lloh26:
	ldr	x8, [x8, _CP_ME1_PIPE3_INT_CNTL@GOTPAGEOFF]
Lloh27:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh28:
	adrp	x8, _CP_ME2_PIPE0_INT_CNTL@GOTPAGE
Lloh29:
	ldr	x8, [x8, _CP_ME2_PIPE0_INT_CNTL@GOTPAGEOFF]
Lloh30:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh31:
	adrp	x8, _CP_ME2_PIPE1_INT_CNTL@GOTPAGE
Lloh32:
	ldr	x8, [x8, _CP_ME2_PIPE1_INT_CNTL@GOTPAGEOFF]
Lloh33:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh34:
	adrp	x8, _CP_ME2_PIPE2_INT_CNTL@GOTPAGE
Lloh35:
	ldr	x8, [x8, _CP_ME2_PIPE2_INT_CNTL@GOTPAGEOFF]
Lloh36:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh37:
	adrp	x8, _CP_ME2_PIPE3_INT_CNTL@GOTPAGE
Lloh38:
	ldr	x8, [x8, _CP_ME2_PIPE3_INT_CNTL@GOTPAGEOFF]
Lloh39:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh40:
	adrp	x8, _GRBM_INT_CNTL@GOTPAGE
Lloh41:
	ldr	x8, [x8, _GRBM_INT_CNTL@GOTPAGEOFF]
Lloh42:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh43:
	adrp	x8, _SRBM_INT_CNTL@GOTPAGE
Lloh44:
	ldr	x8, [x8, _SRBM_INT_CNTL@GOTPAGEOFF]
Lloh45:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh46:
	adrp	x22, _LB_INTERRUPT_MASK@GOTPAGE
Lloh47:
	ldr	x22, [x22, _LB_INTERRUPT_MASK@GOTPAGEOFF]
	ldr	x8, [x22]
Lloh48:
	adrp	x20, _EVERGREEN_CRTC0_REGISTER_OFFSET@GOTPAGE
Lloh49:
	ldr	x20, [x20, _EVERGREEN_CRTC0_REGISTER_OFFSET@GOTPAGEOFF]
	ldr	x9, [x20]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x22]
Lloh50:
	adrp	x21, _EVERGREEN_CRTC1_REGISTER_OFFSET@GOTPAGE
Lloh51:
	ldr	x21, [x21, _EVERGREEN_CRTC1_REGISTER_OFFSET@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
	ldr	w8, [x19]
	cmp	w8, #4
	b.lt	LBB0_3
; %bb.1:
	ldr	x8, [x22]
Lloh52:
	adrp	x9, _EVERGREEN_CRTC2_REGISTER_OFFSET@GOTPAGE
Lloh53:
	ldr	x9, [x9, _EVERGREEN_CRTC2_REGISTER_OFFSET@GOTPAGEOFF]
Lloh54:
	ldr	x9, [x9]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x22]
Lloh55:
	adrp	x9, _EVERGREEN_CRTC3_REGISTER_OFFSET@GOTPAGE
Lloh56:
	ldr	x9, [x9, _EVERGREEN_CRTC3_REGISTER_OFFSET@GOTPAGEOFF]
Lloh57:
	ldr	x9, [x9]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
	ldr	w8, [x19]
	cmp	w8, #6
	b.lt	LBB0_3
; %bb.2:
	ldr	x8, [x22]
Lloh58:
	adrp	x9, _EVERGREEN_CRTC4_REGISTER_OFFSET@GOTPAGE
Lloh59:
	ldr	x9, [x9, _EVERGREEN_CRTC4_REGISTER_OFFSET@GOTPAGEOFF]
Lloh60:
	ldr	x9, [x9]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x22]
Lloh61:
	adrp	x9, _EVERGREEN_CRTC5_REGISTER_OFFSET@GOTPAGE
Lloh62:
	ldr	x9, [x9, _EVERGREEN_CRTC5_REGISTER_OFFSET@GOTPAGEOFF]
Lloh63:
	ldr	x9, [x9]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
	ldr	w8, [x19]
LBB0_3:
	cmp	w8, #2
	b.lt	LBB0_7
; %bb.4:
Lloh64:
	adrp	x22, _GRPH_INT_CONTROL@GOTPAGE
Lloh65:
	ldr	x22, [x22, _GRPH_INT_CONTROL@GOTPAGEOFF]
	ldr	x8, [x22]
	ldr	x9, [x20]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x22]
	ldr	x9, [x21]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
	ldr	w8, [x19]
	cmp	w8, #4
	b.lt	LBB0_7
; %bb.5:
	ldr	x8, [x22]
Lloh66:
	adrp	x9, _EVERGREEN_CRTC2_REGISTER_OFFSET@GOTPAGE
Lloh67:
	ldr	x9, [x9, _EVERGREEN_CRTC2_REGISTER_OFFSET@GOTPAGEOFF]
Lloh68:
	ldr	x9, [x9]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x22]
Lloh69:
	adrp	x9, _EVERGREEN_CRTC3_REGISTER_OFFSET@GOTPAGE
Lloh70:
	ldr	x9, [x9, _EVERGREEN_CRTC3_REGISTER_OFFSET@GOTPAGEOFF]
Lloh71:
	ldr	x9, [x9]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
	ldr	w8, [x19]
	cmp	w8, #6
	b.lt	LBB0_7
; %bb.6:
	ldr	x8, [x22]
Lloh72:
	adrp	x9, _EVERGREEN_CRTC4_REGISTER_OFFSET@GOTPAGE
Lloh73:
	ldr	x9, [x9, _EVERGREEN_CRTC4_REGISTER_OFFSET@GOTPAGEOFF]
Lloh74:
	ldr	x9, [x9]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x22]
Lloh75:
	adrp	x9, _EVERGREEN_CRTC5_REGISTER_OFFSET@GOTPAGE
Lloh76:
	ldr	x9, [x9, _EVERGREEN_CRTC5_REGISTER_OFFSET@GOTPAGEOFF]
Lloh77:
	ldr	x9, [x9]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
LBB0_7:
Lloh78:
	adrp	x8, _DAC_AUTODETECT_INT_CONTROL@GOTPAGE
Lloh79:
	ldr	x8, [x8, _DAC_AUTODETECT_INT_CONTROL@GOTPAGEOFF]
Lloh80:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh81:
	adrp	x20, _DC_HPD1_INT_CONTROL@GOTPAGE
Lloh82:
	ldr	x20, [x20, _DC_HPD1_INT_CONTROL@GOTPAGEOFF]
	ldr	x0, [x20]
	bl	_RREG32
Lloh83:
	adrp	x19, _DC_HPDx_INT_POLARITY@GOTPAGE
Lloh84:
	ldr	x19, [x19, _DC_HPDx_INT_POLARITY@GOTPAGEOFF]
	ldr	w8, [x19]
	and	w1, w8, w0
	ldr	x0, [x20]
	bl	_WREG32
Lloh85:
	adrp	x20, _DC_HPD2_INT_CONTROL@GOTPAGE
Lloh86:
	ldr	x20, [x20, _DC_HPD2_INT_CONTROL@GOTPAGEOFF]
	ldr	x0, [x20]
	bl	_RREG32
	ldr	w8, [x19]
	and	w1, w8, w0
	ldr	x0, [x20]
	bl	_WREG32
Lloh87:
	adrp	x20, _DC_HPD3_INT_CONTROL@GOTPAGE
Lloh88:
	ldr	x20, [x20, _DC_HPD3_INT_CONTROL@GOTPAGEOFF]
	ldr	x0, [x20]
	bl	_RREG32
	ldr	w8, [x19]
	and	w1, w8, w0
	ldr	x0, [x20]
	bl	_WREG32
Lloh89:
	adrp	x20, _DC_HPD4_INT_CONTROL@GOTPAGE
Lloh90:
	ldr	x20, [x20, _DC_HPD4_INT_CONTROL@GOTPAGEOFF]
	ldr	x0, [x20]
	bl	_RREG32
	ldr	w8, [x19]
	and	w1, w8, w0
	ldr	x0, [x20]
	bl	_WREG32
Lloh91:
	adrp	x20, _DC_HPD5_INT_CONTROL@GOTPAGE
Lloh92:
	ldr	x20, [x20, _DC_HPD5_INT_CONTROL@GOTPAGEOFF]
	ldr	x0, [x20]
	bl	_RREG32
	ldr	w8, [x19]
	and	w1, w8, w0
	ldr	x0, [x20]
	bl	_WREG32
Lloh93:
	adrp	x20, _DC_HPD6_INT_CONTROL@GOTPAGE
Lloh94:
	ldr	x20, [x20, _DC_HPD6_INT_CONTROL@GOTPAGEOFF]
	ldr	x0, [x20]
	bl	_RREG32
	ldr	w8, [x19]
	and	w1, w8, w0
	ldr	x0, [x20]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGot	Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGot	Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGot	Lloh93, Lloh94
	.loh AdrpLdrGot	Lloh91, Lloh92
	.loh AdrpLdrGot	Lloh89, Lloh90
	.loh AdrpLdrGot	Lloh87, Lloh88
	.loh AdrpLdrGot	Lloh85, Lloh86
	.loh AdrpLdrGot	Lloh83, Lloh84
	.loh AdrpLdrGot	Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.cfi_endproc
                                        ; -- End function
	.comm	_CP_INT_CNTL_RING0,8,3          ; @CP_INT_CNTL_RING0
	.comm	_CNTX_BUSY_INT_ENABLE,4,2       ; @CNTX_BUSY_INT_ENABLE
	.comm	_CNTX_EMPTY_INT_ENABLE,4,2      ; @CNTX_EMPTY_INT_ENABLE
	.comm	_SDMA0_CNTL,8,3                 ; @SDMA0_CNTL
	.comm	_SDMA0_REGISTER_OFFSET,8,3      ; @SDMA0_REGISTER_OFFSET
	.comm	_TRAP_ENABLE,4,2                ; @TRAP_ENABLE
	.comm	_SDMA1_REGISTER_OFFSET,8,3      ; @SDMA1_REGISTER_OFFSET
	.comm	_CP_ME1_PIPE0_INT_CNTL,8,3      ; @CP_ME1_PIPE0_INT_CNTL
	.comm	_CP_ME1_PIPE1_INT_CNTL,8,3      ; @CP_ME1_PIPE1_INT_CNTL
	.comm	_CP_ME1_PIPE2_INT_CNTL,8,3      ; @CP_ME1_PIPE2_INT_CNTL
	.comm	_CP_ME1_PIPE3_INT_CNTL,8,3      ; @CP_ME1_PIPE3_INT_CNTL
	.comm	_CP_ME2_PIPE0_INT_CNTL,8,3      ; @CP_ME2_PIPE0_INT_CNTL
	.comm	_CP_ME2_PIPE1_INT_CNTL,8,3      ; @CP_ME2_PIPE1_INT_CNTL
	.comm	_CP_ME2_PIPE2_INT_CNTL,8,3      ; @CP_ME2_PIPE2_INT_CNTL
	.comm	_CP_ME2_PIPE3_INT_CNTL,8,3      ; @CP_ME2_PIPE3_INT_CNTL
	.comm	_GRBM_INT_CNTL,8,3              ; @GRBM_INT_CNTL
	.comm	_SRBM_INT_CNTL,8,3              ; @SRBM_INT_CNTL
	.comm	_LB_INTERRUPT_MASK,8,3          ; @LB_INTERRUPT_MASK
	.comm	_EVERGREEN_CRTC0_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC0_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC1_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC1_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC2_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC2_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC3_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC3_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC4_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC4_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC5_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC5_REGISTER_OFFSET
	.comm	_GRPH_INT_CONTROL,8,3           ; @GRPH_INT_CONTROL
	.comm	_DAC_AUTODETECT_INT_CONTROL,8,3 ; @DAC_AUTODETECT_INT_CONTROL
	.comm	_DC_HPD1_INT_CONTROL,8,3        ; @DC_HPD1_INT_CONTROL
	.comm	_DC_HPDx_INT_POLARITY,4,2       ; @DC_HPDx_INT_POLARITY
	.comm	_DC_HPD2_INT_CONTROL,8,3        ; @DC_HPD2_INT_CONTROL
	.comm	_DC_HPD3_INT_CONTROL,8,3        ; @DC_HPD3_INT_CONTROL
	.comm	_DC_HPD4_INT_CONTROL,8,3        ; @DC_HPD4_INT_CONTROL
	.comm	_DC_HPD5_INT_CONTROL,8,3        ; @DC_HPD5_INT_CONTROL
	.comm	_DC_HPD6_INT_CONTROL,8,3        ; @DC_HPD6_INT_CONTROL
	.no_dead_strip	_cik_disable_interrupt_state
.subsections_via_symbols
