	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dpu_hw_lm_setup_blend_config
_dpu_hw_lm_setup_blend_config:          ## @dpu_hw_lm_setup_blend_config
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_DPU_STAGE_BASE@GOTPCREL(%rip), %rax
	cmpq	%rsi, (%rax)
	je	LBB0_2
## %bb.1:
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, %r12
	movq	%rdi, %r13
	callq	__stage_offset
	movl	%eax, %ebx
	movl	%eax, %edi
	shrl	$31, %edi
	callq	_WARN_ON
	testq	%rax, %rax
	je	LBB0_3
LBB0_2:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_3:
	movq	_LM_BLEND0_FG_ALPHA@GOTPCREL(%rip), %rax
	movslq	%ebx, %rbx
	movq	(%rax), %rsi
	addq	%rbx, %rsi
	movq	%r13, %rdi
	movq	%r12, %rdx
	callq	_DPU_REG_WRITE
	movq	_LM_BLEND0_BG_ALPHA@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	%rbx, %rsi
	movq	%r13, %rdi
	movq	%r15, %rdx
	callq	_DPU_REG_WRITE
	movq	_LM_BLEND0_OP@GOTPCREL(%rip), %rax
	addq	(%rax), %rbx
	movq	%r13, %rdi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_DPU_REG_WRITE                  ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_DPU_STAGE_BASE,8,3             ## @DPU_STAGE_BASE
	.comm	_LM_BLEND0_FG_ALPHA,8,3         ## @LM_BLEND0_FG_ALPHA
	.comm	_LM_BLEND0_BG_ALPHA,8,3         ## @LM_BLEND0_BG_ALPHA
	.comm	_LM_BLEND0_OP,8,3               ## @LM_BLEND0_OP
	.no_dead_strip	_dpu_hw_lm_setup_blend_config
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dpu_hw_lm_setup_blend_config
_dpu_hw_lm_setup_blend_config:          ; @dpu_hw_lm_setup_blend_config
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
Lloh0:
	adrp	x8, _DPU_STAGE_BASE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DPU_STAGE_BASE@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	cmp	x8, x1
	b.eq	LBB0_2
; %bb.1:
	mov	x19, x4
	mov	x21, x3
	mov	x22, x2
	mov	x20, x0
	bl	__stage_offset
	mov	x23, x0
	lsr	w0, w0, #31
	bl	_WARN_ON
	cbz	x0, LBB0_3
LBB0_2:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_3:
Lloh3:
	adrp	x8, _LM_BLEND0_FG_ALPHA@GOTPAGE
Lloh4:
	ldr	x8, [x8, _LM_BLEND0_FG_ALPHA@GOTPAGEOFF]
Lloh5:
	ldr	x8, [x8]
	sxtw	x23, w23
	add	x1, x8, x23
	mov	x0, x20
	mov	x2, x22
	bl	_DPU_REG_WRITE
Lloh6:
	adrp	x8, _LM_BLEND0_BG_ALPHA@GOTPAGE
Lloh7:
	ldr	x8, [x8, _LM_BLEND0_BG_ALPHA@GOTPAGEOFF]
Lloh8:
	ldr	x8, [x8]
	add	x1, x8, x23
	mov	x0, x20
	mov	x2, x21
	bl	_DPU_REG_WRITE
Lloh9:
	adrp	x8, _LM_BLEND0_OP@GOTPAGE
Lloh10:
	ldr	x8, [x8, _LM_BLEND0_OP@GOTPAGEOFF]
Lloh11:
	ldr	x8, [x8]
	add	x1, x8, x23
	mov	x0, x20
	mov	x2, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_DPU_REG_WRITE
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_DPU_STAGE_BASE,8,3             ; @DPU_STAGE_BASE
	.comm	_LM_BLEND0_FG_ALPHA,8,3         ; @LM_BLEND0_FG_ALPHA
	.comm	_LM_BLEND0_BG_ALPHA,8,3         ; @LM_BLEND0_BG_ALPHA
	.comm	_LM_BLEND0_OP,8,3               ; @LM_BLEND0_OP
	.no_dead_strip	_dpu_hw_lm_setup_blend_config
.subsections_via_symbols
