	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_vm_need_pipeline_sync   ## -- Begin function amdgpu_vm_need_pipeline_sync
	.p2align	4, 0x90
_amdgpu_vm_need_pipeline_sync:          ## @amdgpu_vm_need_pipeline_sync
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movb	$1, %r15b
	cmpq	$0, 56(%rsi)
	jne	LBB0_2
## %bb.1:
	cmpq	$0, 8(%rdi)
	setne	%r15b
LBB0_2:
	movq	(%rsi), %rax
	testq	%rax, %rax
	je	LBB0_3
## %bb.4:
	movq	(%rdi), %rbx
	movq	16(%rdi), %rdi
	movl	(%rbx), %ecx
	movq	(%rdi), %rdx
	movq	(%rdx,%rcx,8), %rcx
	leaq	(%rax,%rax,2), %rdx
	shlq	$4, %rdx
	leaq	(%rcx,%rdx), %rax
	cmpq	$0, 8(%rbx)
	je	LBB0_5
## %bb.6:
	movq	(%rax), %rbx
	movb	$1, %r14b
	cmpq	8(%rsi), %rbx
	jne	LBB0_12
## %bb.7:
	movq	8(%rcx,%rdx), %rbx
	cmpq	16(%rsi), %rbx
	jne	LBB0_12
## %bb.8:
	movq	16(%rcx,%rdx), %rbx
	cmpq	24(%rsi), %rbx
	jne	LBB0_12
## %bb.9:
	movq	24(%rcx,%rdx), %rbx
	cmpq	32(%rsi), %rbx
	jne	LBB0_12
## %bb.10:
	movq	32(%rcx,%rdx), %rbx
	cmpq	40(%rsi), %rbx
	jne	LBB0_12
## %bb.11:
	movq	40(%rcx,%rdx), %rcx
	cmpq	48(%rsi), %rcx
	setne	%r14b
	jmp	LBB0_12
LBB0_3:
	xorl	%eax, %eax
	jmp	LBB0_14
LBB0_5:
	xorl	%r14d, %r14d
LBB0_12:
	movq	%rax, %rsi
	callq	_amdgpu_vmid_had_gpu_reset
	movq	%rax, %rcx
	movl	$1, %eax
	testq	%rcx, %rcx
	jne	LBB0_14
## %bb.13:
	orb	%r14b, %r15b
	movzbl	%r15b, %eax
LBB0_14:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_vm_need_pipeline_sync   ; -- Begin function amdgpu_vm_need_pipeline_sync
	.p2align	2
_amdgpu_vm_need_pipeline_sync:          ; @amdgpu_vm_need_pipeline_sync
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x8, x1
	mov	x9, x0
	ldr	x10, [x1, #56]
	cbz	x10, LBB0_9
; %bb.1:
	mov	w19, #1
	ldr	x10, [x8]
	cbz	x10, LBB0_10
LBB0_2:
	ldr	x0, [x9, #16]
	ldr	x11, [x9]
	ldr	w9, [x11]
	ldr	x12, [x0]
	ldr	x9, [x12, x9, lsl #3]
	mov	w12, #48
	madd	x1, x10, x12, x9
	ldr	x11, [x11, #8]
	cbz	x11, LBB0_13
; %bb.3:
	ldr	x11, [x1]
	ldr	x12, [x8, #8]
	cmp	x11, x12
	b.ne	LBB0_11
; %bb.4:
	mov	w11, #48
	madd	x11, x10, x11, x9
	ldr	x11, [x11, #8]
	ldr	x12, [x8, #16]
	cmp	x11, x12
	b.ne	LBB0_11
; %bb.5:
	mov	w11, #48
	madd	x11, x10, x11, x9
	ldr	x11, [x11, #16]
	ldr	x12, [x8, #24]
	cmp	x11, x12
	b.ne	LBB0_11
; %bb.6:
	mov	w11, #48
	madd	x11, x10, x11, x9
	ldr	x11, [x11, #24]
	ldr	x12, [x8, #32]
	cmp	x11, x12
	b.ne	LBB0_11
; %bb.7:
	mov	w11, #48
	madd	x11, x10, x11, x9
	ldr	x11, [x11, #32]
	ldr	x12, [x8, #40]
	cmp	x11, x12
	b.ne	LBB0_11
; %bb.8:
	mov	w11, #48
	madd	x9, x10, x11, x9
	ldr	x9, [x9, #40]
	ldr	x8, [x8, #48]
	cmp	x9, x8
	cset	w20, ne
	bl	_amdgpu_vmid_had_gpu_reset
	cbnz	x0, LBB0_12
	b	LBB0_14
LBB0_9:
	ldr	x10, [x9, #8]
	cmp	x10, #0
	cset	w19, ne
	ldr	x10, [x8]
	cbnz	x10, LBB0_2
LBB0_10:
	mov	w0, #0
	b	LBB0_15
LBB0_11:
	mov	w20, #1
	bl	_amdgpu_vmid_had_gpu_reset
	cbz	x0, LBB0_14
LBB0_12:
	mov	w0, #1
	b	LBB0_15
LBB0_13:
	mov	w20, #0
	bl	_amdgpu_vmid_had_gpu_reset
	cbnz	x0, LBB0_12
LBB0_14:
	orr	w0, w19, w20
LBB0_15:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.cfi_endproc
                                        ; -- End function
.subsections_via_symbols
