	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function socfpga_fpga_cfg_mode_set
_socfpga_fpga_cfg_mode_set:             ## @socfpga_fpga_cfg_mode_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	callq	_socfpga_fpga_cfg_mode_get
	movl	%eax, %ebx
	testl	%eax, %eax
	js	LBB0_2
## %bb.1:
	movq	_SOCFPGA_FPGMGR_CTL_OFST@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_socfpga_fpga_readl
	movq	_SOCFPGA_FPGMGR_CTL_CDRATIO_MASK@GOTPCREL(%rip), %rcx
	movq	_SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_cfgmgr_modes@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movl	%ebx, %ecx
	orl	(%rax,%rcx,4), %esi
	movq	_SOCFPGA_FPGMGR_CTL_NCE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	andl	%esi, %edx
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_socfpga_fpga_writel
	xorl	%ebx, %ebx
LBB0_2:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_SOCFPGA_FPGMGR_CTL_OFST,4,2    ## @SOCFPGA_FPGMGR_CTL_OFST
	.comm	_SOCFPGA_FPGMGR_CTL_CDRATIO_MASK,4,2 ## @SOCFPGA_FPGMGR_CTL_CDRATIO_MASK
	.comm	_SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK,4,2 ## @SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK
	.comm	_cfgmgr_modes,8,3               ## @cfgmgr_modes
	.comm	_SOCFPGA_FPGMGR_CTL_NCE,4,2     ## @SOCFPGA_FPGMGR_CTL_NCE
	.no_dead_strip	_socfpga_fpga_cfg_mode_set
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function socfpga_fpga_cfg_mode_set
_socfpga_fpga_cfg_mode_set:             ; @socfpga_fpga_cfg_mode_set
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	bl	_socfpga_fpga_cfg_mode_get
	mov	x20, x0
	tbnz	w0, #31, LBB0_2
; %bb.1:
Lloh0:
	adrp	x21, _SOCFPGA_FPGMGR_CTL_OFST@GOTPAGE
Lloh1:
	ldr	x21, [x21, _SOCFPGA_FPGMGR_CTL_OFST@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_socfpga_fpga_readl
Lloh2:
	adrp	x8, _SOCFPGA_FPGMGR_CTL_CDRATIO_MASK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _SOCFPGA_FPGMGR_CTL_CDRATIO_MASK@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
Lloh5:
	adrp	x9, _SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK@GOTPAGE
Lloh6:
	ldr	x9, [x9, _SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
Lloh8:
	adrp	x9, _cfgmgr_modes@GOTPAGE
Lloh9:
	ldr	x9, [x9, _cfgmgr_modes@GOTPAGEOFF]
Lloh10:
	ldr	x9, [x9]
	ldr	w9, [x9, w20, uxtw #2]
	orr	w8, w8, w9
Lloh11:
	adrp	x9, _SOCFPGA_FPGMGR_CTL_NCE@GOTPAGE
Lloh12:
	ldr	x9, [x9, _SOCFPGA_FPGMGR_CTL_NCE@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	bic	w2, w8, w9
	ldr	w1, [x21]
	mov	x0, x19
	bl	_socfpga_fpga_writel
	mov	w20, #0
LBB0_2:
	mov	x0, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_SOCFPGA_FPGMGR_CTL_OFST,4,2    ; @SOCFPGA_FPGMGR_CTL_OFST
	.comm	_SOCFPGA_FPGMGR_CTL_CDRATIO_MASK,4,2 ; @SOCFPGA_FPGMGR_CTL_CDRATIO_MASK
	.comm	_SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK,4,2 ; @SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK
	.comm	_cfgmgr_modes,8,3               ; @cfgmgr_modes
	.comm	_SOCFPGA_FPGMGR_CTL_NCE,4,2     ; @SOCFPGA_FPGMGR_CTL_NCE
	.no_dead_strip	_socfpga_fpga_cfg_mode_set
.subsections_via_symbols
