	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rv6xx_force_pcie_gen1
_rv6xx_force_pcie_gen1:                 ## @rv6xx_force_pcie_gen1
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	_PCIE_LC_SPEED_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_GEN2_EN@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movl	(%r14), %edi
	movl	%eax, %esi
	callq	_WREG32_PCIE_PORT
	movl	(%r14), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_INITIATE_LINK_SPEED_CHANGE@GOTPCREL(%rip), %r15
	orl	(%r15), %eax
	movl	(%r14), %edi
	movl	%eax, %esi
	callq	_WREG32_PCIE_PORT
	cmpl	$0, (%r12)
	jle	LBB0_4
## %bb.1:
	xorl	%ebx, %ebx
	movq	_LC_CURRENT_DATA_RATE@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %edi
	callq	_RREG32_PCIE_PORT
	testl	%eax, (%r13)
	je	LBB0_4
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movl	$1, %edi
	callq	_udelay
	incl	%ebx
	cmpl	(%r12), %ebx
	jl	LBB0_2
LBB0_4:
	movl	(%r14), %edi
	callq	_RREG32_PCIE_PORT
	movl	(%r15), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r14), %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_PCIE_PORT               ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PCIE_LC_SPEED_CNTL,4,2         ## @PCIE_LC_SPEED_CNTL
	.comm	_LC_GEN2_EN,4,2                 ## @LC_GEN2_EN
	.comm	_LC_INITIATE_LINK_SPEED_CHANGE,4,2 ## @LC_INITIATE_LINK_SPEED_CHANGE
	.comm	_LC_CURRENT_DATA_RATE,4,2       ## @LC_CURRENT_DATA_RATE
	.no_dead_strip	_rv6xx_force_pcie_gen1
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rv6xx_force_pcie_gen1
_rv6xx_force_pcie_gen1:                 ; @rv6xx_force_pcie_gen1
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x20, _PCIE_LC_SPEED_CNTL@GOTPAGE
Lloh1:
	ldr	x20, [x20, _PCIE_LC_SPEED_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PCIE_PORT
Lloh2:
	adrp	x8, _LC_GEN2_EN@GOTPAGE
Lloh3:
	ldr	x8, [x8, _LC_GEN2_EN@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	and	w1, w8, w0
	ldr	w0, [x20]
	bl	_WREG32_PCIE_PORT
	ldr	w0, [x20]
	bl	_RREG32_PCIE_PORT
Lloh5:
	adrp	x21, _LC_INITIATE_LINK_SPEED_CHANGE@GOTPAGE
Lloh6:
	ldr	x21, [x21, _LC_INITIATE_LINK_SPEED_CHANGE@GOTPAGEOFF]
	ldr	w8, [x21]
	orr	w1, w8, w0
	ldr	w0, [x20]
	bl	_WREG32_PCIE_PORT
	ldr	w8, [x19]
	cmp	w8, #1
	b.lt	LBB0_4
; %bb.1:
	mov	w22, #0
Lloh7:
	adrp	x23, _LC_CURRENT_DATA_RATE@GOTPAGE
Lloh8:
	ldr	x23, [x23, _LC_CURRENT_DATA_RATE@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x20]
	bl	_RREG32_PCIE_PORT
	ldr	w8, [x23]
	tst	w8, w0
	b.eq	LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	mov	w0, #1
	bl	_udelay
	add	w22, w22, #1
	ldr	w8, [x19]
	cmp	w22, w8
	b.lt	LBB0_2
LBB0_4:
	ldr	w0, [x20]
	bl	_RREG32_PCIE_PORT
	ldr	w8, [x21]
	bic	w1, w0, w8
	ldr	w0, [x20]
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_WREG32_PCIE_PORT
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_PCIE_LC_SPEED_CNTL,4,2         ; @PCIE_LC_SPEED_CNTL
	.comm	_LC_GEN2_EN,4,2                 ; @LC_GEN2_EN
	.comm	_LC_INITIATE_LINK_SPEED_CHANGE,4,2 ; @LC_INITIATE_LINK_SPEED_CHANGE
	.comm	_LC_CURRENT_DATA_RATE,4,2       ; @LC_CURRENT_DATA_RATE
	.no_dead_strip	_rv6xx_force_pcie_gen1
.subsections_via_symbols
