	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function sdma_v5_0_gfx_resume
_sdma_v5_0_gfx_resume:                  ## @sdma_v5_0_gfx_resume
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	cmpl	$0, 24(%rdi)
	jle	LBB0_18
## %bb.1:
	movq	%rdi, %r12
	xorl	%r15d, %r15d
	movq	_mmSDMA0_GFX_RB_CNTL@GOTPCREL(%rip), %r13
	xorl	%r14d, %r14d
	jmp	LBB0_2
	.p2align	4, 0x90
LBB0_17:                                ##   in Loop: Header=BB0_2 Depth=1
	incq	%r14
	movslq	24(%r12), %rax
	addq	$40, %r15
	cmpq	%rax, %r14
	movq	_mmSDMA0_GFX_RB_CNTL@GOTPCREL(%rip), %r13
	jge	LBB0_18
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r15, -64(%rbp)                 ## 8-byte Spill
	movq	32(%r12), %r15
	movq	-64(%rbp), %rax                 ## 8-byte Reload
	movslq	(%r15,%rax), %rax
	shlq	$2, %rax
	movq	%rax, -72(%rbp)                 ## 8-byte Spill
	movq	_mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	-64(%rbp), %rax                 ## 8-byte Reload
	movl	4(%r15,%rax), %eax
	leal	3(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$2, %edi
	callq	_order_base_2
	movl	%eax, %ebx
	movl	(%r13), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	callq	_RREG32
	movq	_SDMA0_GFX_RB_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_RB_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	%ebx, %ecx
	callq	_REG_SET_FIELD
	movl	%eax, %ebx
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movl	(%r13), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_mmSDMA0_GFX_RB_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmSDMA0_GFX_RB_RPTR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmSDMA0_GFX_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmSDMA0_GFX_RB_WPTR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	-64(%rbp), %rax                 ## 8-byte Reload
	movslq	8(%r15,%rax), %rbx
	shlq	$2, %rbx
	addq	16(%r12), %rbx
	movq	_mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %r13d
	movq	%rbx, %rdi
	callq	_lower_32_bits
	movl	%r13d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %r13d
	movq	%rbx, %rdi
	callq	_upper_32_bits
	movl	%r13d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmSDMA0_GFX_RB_WPTR_POLL_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	callq	_RREG32
	movq	_SDMA0_GFX_RB_WPTR_POLL_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_F32_POLL_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	%eax, %ebx
	movl	(%r13), %edx
	movq	%r15, %r13
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_mmSDMA0_GFX_RB_RPTR_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %r15d
	movq	16(%r12), %rdi
	movq	-72(%rbp), %rbx                 ## 8-byte Reload
	addq	%rbx, %rdi
	callq	_upper_32_bits
	movl	%r15d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmSDMA0_GFX_RB_RPTR_ADDR_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %r15d
	movq	%rbx, %rdi
	addq	16(%r12), %rdi
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	callq	_lower_32_bits
	andl	$-4, %eax
	movl	%r15d, %edi
	movq	%rbx, %r15
	movl	%eax, %esi
	callq	_WREG32
	movq	_SDMA0_GFX_RB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_RPTR_WRITEBACK_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	-48(%rbp), %edi                 ## 4-byte Reload
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	%eax, -72(%rbp)                 ## 4-byte Spill
	movq	_mmSDMA0_GFX_RB_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	12(%r13,%rbx), %esi
	sarl	$8, %esi
	movl	%eax, %edi
	callq	_WREG32
	movq	_mmSDMA0_GFX_RB_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	callq	_WREG32
	movq	$0, 32(%r13,%rbx)
	movq	_mmSDMA0_GFX_MINOR_PTR_UPDATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	movl	$1, %esi
	callq	_WREG32
	movq	%r12, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	jne	LBB0_4
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	_mmSDMA0_GFX_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %ebx
	movq	32(%r13,%r15), %rdi
	callq	_lower_32_bits
                                        ## kill: def $eax killed $eax def $rax
	leal	(,%rax,4), %esi
	movl	%ebx, %edi
	callq	_WREG32
	movq	_mmSDMA0_GFX_RB_WPTR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %ebx
	movq	32(%r13,%r15), %rdi
	callq	_upper_32_bits
                                        ## kill: def $eax killed $eax def $rax
	leal	(,%rax,4), %esi
	movl	%ebx, %edi
	callq	_WREG32
LBB0_4:                                 ##   in Loop: Header=BB0_2 Depth=1
	movq	_mmSDMA0_GFX_DOORBELL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	callq	_RREG32
	movl	%eax, %ebx
	movq	_mmSDMA0_GFX_DOORBELL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	callq	_RREG32
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	cmpq	$0, 24(%r13,%r15)
	movq	_SDMA0_GFX_DOORBELL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%ebx, %edi
	je	LBB0_6
## %bb.5:                               ##   in Loop: Header=BB0_2 Depth=1
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	movq	_SDMA0_GFX_DOORBELL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	16(%r13,%r15), %ecx
	movl	-48(%rbp), %edi                 ## 4-byte Reload
	callq	_REG_SET_FIELD
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	jmp	LBB0_7
	.p2align	4, 0x90
LBB0_6:                                 ##   in Loop: Header=BB0_2 Depth=1
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
LBB0_7:                                 ##   in Loop: Header=BB0_2 Depth=1
	leaq	(%r15,%r13), %rbx
	movq	_mmSDMA0_GFX_DOORBELL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	movl	-56(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_mmSDMA0_GFX_DOORBELL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	movl	-48(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	8(%r12), %rax
	movq	24(%r13,%r15), %rdx
	movq	%r13, -48(%rbp)                 ## 8-byte Spill
	movl	16(%r13,%r15), %ecx
	movq	%r12, %rdi
	movl	%r14d, %esi
	movl	$20, %r8d
	callq	*(%rax)
	movq	%r12, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_9
## %bb.8:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	%rbx, %rdi
	callq	_sdma_v5_0_ring_set_wptr
LBB0_9:                                 ##   in Loop: Header=BB0_2 Depth=1
	movq	%rbx, -56(%rbp)                 ## 8-byte Spill
	movq	_mmSDMA0_GFX_MINOR_PTR_UPDATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmSDMA0_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	callq	_RREG32
	movq	_SDMA0_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_UTC_L1_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_MIDCMD_PREEMPT_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	%eax, %ebx
	movl	(%r13), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_mmSDMA0_UTCL1_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	callq	_RREG32
	movq	_SDMA0_UTCL1_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_RESP_MODE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$3, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_REDO_DELAY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$9, %ecx
	callq	_REG_SET_FIELD
	movl	%eax, %ebx
	movl	(%r13), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_mmSDMA0_UTCL1_PAGE@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	callq	_RREG32
	andl	$16715775, %eax                 ## imm = 0xFF0FFF
	movq	_CACHE_READ_POLICY_L2__DEFAULT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	shll	$12, %ecx
	movq	_CACHE_WRITE_POLICY_L2__DEFAULT@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	shll	$14, %ebx
	orl	%ecx, %ebx
	orl	%eax, %ebx
	movl	(%r13), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	%r12, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	movq	_mmSDMA0_GFX_RB_CNTL@GOTPCREL(%rip), %r13
	jne	LBB0_11
## %bb.10:                              ##   in Loop: Header=BB0_2 Depth=1
	movq	_mmSDMA0_F32_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	callq	_RREG32
	movq	_SDMA0_F32_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_HALT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	%eax, %ebx
	movq	_mmSDMA0_F32_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_WREG32
LBB0_11:                                ##   in Loop: Header=BB0_2 Depth=1
	movq	_SDMA0_GFX_RB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_RB_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	-72(%rbp), %edi                 ## 4-byte Reload
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	%eax, %ebx
	movl	(%r13), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_mmSDMA0_GFX_IB_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	callq	_RREG32
	movq	_SDMA0_GFX_IB_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_IB_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	%eax, %ebx
	movl	(%r13), %edx
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	-48(%rbp), %r13                 ## 8-byte Reload
	movl	$1, 20(%r13,%r15)
	movq	%r12, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_13
## %bb.12:                              ##   in Loop: Header=BB0_2 Depth=1
	movq	%r12, %rdi
	movl	$1, %esi
	callq	_sdma_v5_0_ctx_switch_enable
	movq	%r12, %rdi
	movl	$1, %esi
	callq	_sdma_v5_0_enable
LBB0_13:                                ##   in Loop: Header=BB0_2 Depth=1
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	callq	_amdgpu_ring_test_ring
	testl	%eax, %eax
	jne	LBB0_14
## %bb.15:                              ##   in Loop: Header=BB0_2 Depth=1
	cmpq	(%r12), %rbx
	jne	LBB0_17
## %bb.16:                              ##   in Loop: Header=BB0_2 Depth=1
	movq	%r12, %rdi
	movl	$1, %esi
	callq	_amdgpu_ttm_set_buffer_funcs_status
	jmp	LBB0_17
LBB0_18:
	xorl	%eax, %eax
	jmp	LBB0_19
LBB0_14:
	movl	$0, 20(%r13,%r15)
LBB0_19:
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL,4,2 ## @mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
	.comm	_mmSDMA0_GFX_RB_CNTL,4,2        ## @mmSDMA0_GFX_RB_CNTL
	.comm	_SDMA0_GFX_RB_CNTL,4,2          ## @SDMA0_GFX_RB_CNTL
	.comm	_RB_SIZE,4,2                    ## @RB_SIZE
	.comm	_mmSDMA0_GFX_RB_RPTR,4,2        ## @mmSDMA0_GFX_RB_RPTR
	.comm	_mmSDMA0_GFX_RB_RPTR_HI,4,2     ## @mmSDMA0_GFX_RB_RPTR_HI
	.comm	_mmSDMA0_GFX_RB_WPTR,4,2        ## @mmSDMA0_GFX_RB_WPTR
	.comm	_mmSDMA0_GFX_RB_WPTR_HI,4,2     ## @mmSDMA0_GFX_RB_WPTR_HI
	.comm	_mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,4,2 ## @mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO
	.comm	_mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,4,2 ## @mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI
	.comm	_mmSDMA0_GFX_RB_WPTR_POLL_CNTL,4,2 ## @mmSDMA0_GFX_RB_WPTR_POLL_CNTL
	.comm	_SDMA0_GFX_RB_WPTR_POLL_CNTL,4,2 ## @SDMA0_GFX_RB_WPTR_POLL_CNTL
	.comm	_F32_POLL_ENABLE,4,2            ## @F32_POLL_ENABLE
	.comm	_mmSDMA0_GFX_RB_RPTR_ADDR_HI,4,2 ## @mmSDMA0_GFX_RB_RPTR_ADDR_HI
	.comm	_mmSDMA0_GFX_RB_RPTR_ADDR_LO,4,2 ## @mmSDMA0_GFX_RB_RPTR_ADDR_LO
	.comm	_RPTR_WRITEBACK_ENABLE,4,2      ## @RPTR_WRITEBACK_ENABLE
	.comm	_mmSDMA0_GFX_RB_BASE,4,2        ## @mmSDMA0_GFX_RB_BASE
	.comm	_mmSDMA0_GFX_RB_BASE_HI,4,2     ## @mmSDMA0_GFX_RB_BASE_HI
	.comm	_mmSDMA0_GFX_MINOR_PTR_UPDATE,4,2 ## @mmSDMA0_GFX_MINOR_PTR_UPDATE
	.comm	_mmSDMA0_GFX_DOORBELL,4,2       ## @mmSDMA0_GFX_DOORBELL
	.comm	_mmSDMA0_GFX_DOORBELL_OFFSET,4,2 ## @mmSDMA0_GFX_DOORBELL_OFFSET
	.comm	_SDMA0_GFX_DOORBELL,4,2         ## @SDMA0_GFX_DOORBELL
	.comm	_ENABLE,4,2                     ## @ENABLE
	.comm	_SDMA0_GFX_DOORBELL_OFFSET,4,2  ## @SDMA0_GFX_DOORBELL_OFFSET
	.comm	_OFFSET,4,2                     ## @OFFSET
	.comm	_mmSDMA0_CNTL,4,2               ## @mmSDMA0_CNTL
	.comm	_SDMA0_CNTL,4,2                 ## @SDMA0_CNTL
	.comm	_UTC_L1_ENABLE,4,2              ## @UTC_L1_ENABLE
	.comm	_MIDCMD_PREEMPT_ENABLE,4,2      ## @MIDCMD_PREEMPT_ENABLE
	.comm	_mmSDMA0_UTCL1_CNTL,4,2         ## @mmSDMA0_UTCL1_CNTL
	.comm	_SDMA0_UTCL1_CNTL,4,2           ## @SDMA0_UTCL1_CNTL
	.comm	_RESP_MODE,4,2                  ## @RESP_MODE
	.comm	_REDO_DELAY,4,2                 ## @REDO_DELAY
	.comm	_mmSDMA0_UTCL1_PAGE,4,2         ## @mmSDMA0_UTCL1_PAGE
	.comm	_CACHE_READ_POLICY_L2__DEFAULT,4,2 ## @CACHE_READ_POLICY_L2__DEFAULT
	.comm	_CACHE_WRITE_POLICY_L2__DEFAULT,4,2 ## @CACHE_WRITE_POLICY_L2__DEFAULT
	.comm	_mmSDMA0_F32_CNTL,4,2           ## @mmSDMA0_F32_CNTL
	.comm	_SDMA0_F32_CNTL,4,2             ## @SDMA0_F32_CNTL
	.comm	_HALT,4,2                       ## @HALT
	.comm	_RB_ENABLE,4,2                  ## @RB_ENABLE
	.comm	_mmSDMA0_GFX_IB_CNTL,4,2        ## @mmSDMA0_GFX_IB_CNTL
	.comm	_SDMA0_GFX_IB_CNTL,4,2          ## @SDMA0_GFX_IB_CNTL
	.comm	_IB_ENABLE,4,2                  ## @IB_ENABLE
	.comm	_IB_SWAP_ENABLE,4,2             ## @IB_SWAP_ENABLE
	.comm	_RB_SWAP_ENABLE,4,2             ## @RB_SWAP_ENABLE
	.comm	_RPTR_WRITEBACK_SWAP_ENABLE,4,2 ## @RPTR_WRITEBACK_SWAP_ENABLE
	.no_dead_strip	_sdma_v5_0_gfx_resume
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function sdma_v5_0_gfx_resume
_sdma_v5_0_gfx_resume:                  ; @sdma_v5_0_gfx_resume
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	ldr	w8, [x0, #24]
	cmp	w8, #1
	b.lt	LBB0_17
; %bb.1:
	mov	x19, x0
	mov	x25, #0
	mov	x20, #0
Lloh0:
	adrp	x23, _mmSDMA0_GFX_RB_CNTL@GOTPAGE
Lloh1:
	ldr	x23, [x23, _mmSDMA0_GFX_RB_CNTL@GOTPAGEOFF]
Lloh2:
	adrp	x27, _mmSDMA0_GFX_MINOR_PTR_UPDATE@GOTPAGE
Lloh3:
	ldr	x27, [x27, _mmSDMA0_GFX_MINOR_PTR_UPDATE@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:                                 ;   in Loop: Header=BB0_3 Depth=1
	add	x20, x20, #1
	ldrsw	x8, [x19, #24]
	add	x25, x25, #40
	cmp	x20, x8
	b.ge	LBB0_17
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #32]
	str	x8, [sp, #8]                    ; 8-byte Folded Spill
	add	x21, x8, x25
	ldrsw	x8, [x21]
	mov	x26, x27
	lsl	x27, x8, #2
Lloh4:
	adrp	x8, _mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL@GOTPAGE
Lloh5:
	ldr	x8, [x8, _mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL@GOTPAGEOFF]
Lloh6:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	w1, #0
	bl	_WREG32
	ldr	w8, [x21, #4]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #2
	bl	_order_base_2
	mov	x22, x0
	ldr	w2, [x23]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	bl	_RREG32
Lloh7:
	adrp	x28, _SDMA0_GFX_RB_CNTL@GOTPAGE
Lloh8:
	ldr	x28, [x28, _SDMA0_GFX_RB_CNTL@GOTPAGEOFF]
	ldr	w1, [x28]
Lloh9:
	adrp	x8, _RB_SIZE@GOTPAGE
Lloh10:
	ldr	x8, [x8, _RB_SIZE@GOTPAGEOFF]
Lloh11:
	ldr	w2, [x8]
	mov	x3, x22
	bl	_REG_SET_FIELD
	mov	x22, x0
	ldr	w2, [x23]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	x1, x22
	bl	_WREG32
Lloh12:
	adrp	x8, _mmSDMA0_GFX_RB_RPTR@GOTPAGE
Lloh13:
	ldr	x8, [x8, _mmSDMA0_GFX_RB_RPTR@GOTPAGEOFF]
Lloh14:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	w1, #0
	bl	_WREG32
Lloh15:
	adrp	x8, _mmSDMA0_GFX_RB_RPTR_HI@GOTPAGE
Lloh16:
	ldr	x8, [x8, _mmSDMA0_GFX_RB_RPTR_HI@GOTPAGEOFF]
Lloh17:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	w1, #0
	bl	_WREG32
Lloh18:
	adrp	x8, _mmSDMA0_GFX_RB_WPTR@GOTPAGE
Lloh19:
	ldr	x8, [x8, _mmSDMA0_GFX_RB_WPTR@GOTPAGEOFF]
Lloh20:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	w1, #0
	bl	_WREG32
Lloh21:
	adrp	x8, _mmSDMA0_GFX_RB_WPTR_HI@GOTPAGE
Lloh22:
	ldr	x8, [x8, _mmSDMA0_GFX_RB_WPTR_HI@GOTPAGEOFF]
Lloh23:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x19, #16]
	ldrsw	x9, [x21, #8]
	add	x23, x8, x9, lsl #2
Lloh24:
	adrp	x8, _mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO@GOTPAGE
Lloh25:
	ldr	x8, [x8, _mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO@GOTPAGEOFF]
Lloh26:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	x24, x0
	mov	x0, x23
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x24
	bl	_WREG32
Lloh27:
	adrp	x8, _mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI@GOTPAGE
Lloh28:
	ldr	x8, [x8, _mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI@GOTPAGEOFF]
Lloh29:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	x24, x0
	mov	x0, x23
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x24
	bl	_WREG32
Lloh30:
	adrp	x24, _mmSDMA0_GFX_RB_WPTR_POLL_CNTL@GOTPAGE
Lloh31:
	ldr	x24, [x24, _mmSDMA0_GFX_RB_WPTR_POLL_CNTL@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	bl	_RREG32
Lloh32:
	adrp	x8, _SDMA0_GFX_RB_WPTR_POLL_CNTL@GOTPAGE
Lloh33:
	ldr	x8, [x8, _SDMA0_GFX_RB_WPTR_POLL_CNTL@GOTPAGEOFF]
Lloh34:
	ldr	w1, [x8]
Lloh35:
	adrp	x8, _F32_POLL_ENABLE@GOTPAGE
Lloh36:
	ldr	x8, [x8, _F32_POLL_ENABLE@GOTPAGEOFF]
Lloh37:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x23, x0
	ldr	w2, [x24]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	x1, x23
	bl	_WREG32
Lloh38:
	adrp	x8, _mmSDMA0_GFX_RB_RPTR_ADDR_HI@GOTPAGE
Lloh39:
	ldr	x8, [x8, _mmSDMA0_GFX_RB_RPTR_ADDR_HI@GOTPAGEOFF]
Lloh40:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	x23, x0
	ldr	x8, [x19, #16]
	add	x0, x8, x27
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x23
	bl	_WREG32
Lloh41:
	adrp	x8, _mmSDMA0_GFX_RB_RPTR_ADDR_LO@GOTPAGE
Lloh42:
	ldr	x8, [x8, _mmSDMA0_GFX_RB_RPTR_ADDR_LO@GOTPAGEOFF]
Lloh43:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	x23, x0
	ldr	x8, [x19, #16]
	add	x0, x8, x27
	mov	x27, x26
	bl	_lower_32_bits
	and	w1, w0, #0xfffffffc
	mov	x0, x23
	bl	_WREG32
	ldr	w1, [x28]
Lloh44:
	adrp	x8, _RPTR_WRITEBACK_ENABLE@GOTPAGE
Lloh45:
	ldr	x8, [x8, _RPTR_WRITEBACK_ENABLE@GOTPAGEOFF]
Lloh46:
	ldr	w2, [x8]
	mov	x0, x22
	mov	w3, #1
	bl	_REG_SET_FIELD
	str	w0, [sp, #4]                    ; 4-byte Folded Spill
Lloh47:
	adrp	x8, _mmSDMA0_GFX_RB_BASE@GOTPAGE
Lloh48:
	ldr	x8, [x8, _mmSDMA0_GFX_RB_BASE@GOTPAGEOFF]
Lloh49:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	ldr	w8, [x21, #12]
	asr	w1, w8, #8
	bl	_WREG32
Lloh50:
	adrp	x8, _mmSDMA0_GFX_RB_BASE_HI@GOTPAGE
Lloh51:
	ldr	x8, [x8, _mmSDMA0_GFX_RB_BASE_HI@GOTPAGEOFF]
Lloh52:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	bl	_WREG32
	str	xzr, [x21, #32]
	ldr	w2, [x26]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	w1, #1
	bl	_WREG32
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbnz	x0, LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
Lloh53:
	adrp	x8, _mmSDMA0_GFX_RB_WPTR@GOTPAGE
Lloh54:
	ldr	x8, [x8, _mmSDMA0_GFX_RB_WPTR@GOTPAGEOFF]
Lloh55:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	x23, x0
	ldr	x0, [x21, #32]
	bl	_lower_32_bits
	lsl	w1, w0, #2
	mov	x0, x23
	bl	_WREG32
Lloh56:
	adrp	x8, _mmSDMA0_GFX_RB_WPTR_HI@GOTPAGE
Lloh57:
	ldr	x8, [x8, _mmSDMA0_GFX_RB_WPTR_HI@GOTPAGEOFF]
Lloh58:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	x23, x0
	ldr	x0, [x21, #32]
	bl	_upper_32_bits
	lsl	w1, w0, #2
	mov	x0, x23
	bl	_WREG32
LBB0_5:                                 ;   in Loop: Header=BB0_3 Depth=1
Lloh59:
	adrp	x22, _mmSDMA0_GFX_DOORBELL@GOTPAGE
Lloh60:
	ldr	x22, [x22, _mmSDMA0_GFX_DOORBELL@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	bl	_RREG32
	mov	x24, x0
Lloh61:
	adrp	x28, _mmSDMA0_GFX_DOORBELL_OFFSET@GOTPAGE
Lloh62:
	ldr	x28, [x28, _mmSDMA0_GFX_DOORBELL_OFFSET@GOTPAGEOFF]
	ldr	w2, [x28]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	bl	_RREG32
	mov	x23, x0
	ldr	x8, [x21, #24]
Lloh63:
	adrp	x9, _SDMA0_GFX_DOORBELL@GOTPAGE
Lloh64:
	ldr	x9, [x9, _SDMA0_GFX_DOORBELL@GOTPAGEOFF]
Lloh65:
	ldr	w1, [x9]
Lloh66:
	adrp	x9, _ENABLE@GOTPAGE
Lloh67:
	ldr	x9, [x9, _ENABLE@GOTPAGEOFF]
Lloh68:
	ldr	w2, [x9]
	mov	x0, x24
	cbz	x8, LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_3 Depth=1
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x24, x0
Lloh69:
	adrp	x8, _SDMA0_GFX_DOORBELL_OFFSET@GOTPAGE
Lloh70:
	ldr	x8, [x8, _SDMA0_GFX_DOORBELL_OFFSET@GOTPAGEOFF]
Lloh71:
	ldr	w1, [x8]
Lloh72:
	adrp	x8, _OFFSET@GOTPAGE
Lloh73:
	ldr	x8, [x8, _OFFSET@GOTPAGEOFF]
Lloh74:
	ldr	w2, [x8]
	ldr	x26, [sp, #8]                   ; 8-byte Folded Reload
	add	x8, x26, x25
	ldr	w3, [x8, #16]
	mov	x0, x23
	bl	_REG_SET_FIELD
	mov	x23, x0
	b	LBB0_8
LBB0_7:                                 ;   in Loop: Header=BB0_3 Depth=1
	mov	w3, #0
	bl	_REG_SET_FIELD
	mov	x24, x0
	ldr	x26, [sp, #8]                   ; 8-byte Folded Reload
LBB0_8:                                 ;   in Loop: Header=BB0_3 Depth=1
	ldr	w2, [x22]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	x1, x24
	bl	_WREG32
	ldr	w2, [x28]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	x1, x23
	bl	_WREG32
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	ldr	x2, [x21, #24]
	add	x9, x26, x25
	ldr	w3, [x9, #16]
	mov	x0, x19
	mov	x1, x20
	mov	w4, #20
	blr	x8
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_3 Depth=1
	mov	x0, x21
	bl	_sdma_v5_0_ring_set_wptr
LBB0_10:                                ;   in Loop: Header=BB0_3 Depth=1
	ldr	w2, [x27]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	w1, #0
	bl	_WREG32
Lloh75:
	adrp	x24, _mmSDMA0_CNTL@GOTPAGE
Lloh76:
	ldr	x24, [x24, _mmSDMA0_CNTL@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	bl	_RREG32
Lloh77:
	adrp	x23, _SDMA0_CNTL@GOTPAGE
Lloh78:
	ldr	x23, [x23, _SDMA0_CNTL@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh79:
	adrp	x8, _UTC_L1_ENABLE@GOTPAGE
Lloh80:
	ldr	x8, [x8, _UTC_L1_ENABLE@GOTPAGEOFF]
Lloh81:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh82:
	adrp	x8, _MIDCMD_PREEMPT_ENABLE@GOTPAGE
Lloh83:
	ldr	x8, [x8, _MIDCMD_PREEMPT_ENABLE@GOTPAGEOFF]
Lloh84:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x23, x0
	ldr	w2, [x24]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	x1, x23
	bl	_WREG32
Lloh85:
	adrp	x24, _mmSDMA0_UTCL1_CNTL@GOTPAGE
Lloh86:
	ldr	x24, [x24, _mmSDMA0_UTCL1_CNTL@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	bl	_RREG32
Lloh87:
	adrp	x23, _SDMA0_UTCL1_CNTL@GOTPAGE
Lloh88:
	ldr	x23, [x23, _SDMA0_UTCL1_CNTL@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh89:
	adrp	x8, _RESP_MODE@GOTPAGE
Lloh90:
	ldr	x8, [x8, _RESP_MODE@GOTPAGEOFF]
Lloh91:
	ldr	w2, [x8]
	mov	w3, #3
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh92:
	adrp	x8, _REDO_DELAY@GOTPAGE
Lloh93:
	ldr	x8, [x8, _REDO_DELAY@GOTPAGEOFF]
Lloh94:
	ldr	w2, [x8]
	mov	w3, #9
	bl	_REG_SET_FIELD
	mov	x23, x0
	ldr	w2, [x24]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	x1, x23
	bl	_WREG32
Lloh95:
	adrp	x24, _mmSDMA0_UTCL1_PAGE@GOTPAGE
Lloh96:
	ldr	x24, [x24, _mmSDMA0_UTCL1_PAGE@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	bl	_RREG32
	mov	w8, #4095
	movk	w8, #255, lsl #16
	and	w8, w0, w8
Lloh97:
	adrp	x9, _CACHE_READ_POLICY_L2__DEFAULT@GOTPAGE
Lloh98:
	ldr	x9, [x9, _CACHE_READ_POLICY_L2__DEFAULT@GOTPAGEOFF]
Lloh99:
	ldr	w9, [x9]
Lloh100:
	adrp	x10, _CACHE_WRITE_POLICY_L2__DEFAULT@GOTPAGE
Lloh101:
	ldr	x10, [x10, _CACHE_WRITE_POLICY_L2__DEFAULT@GOTPAGEOFF]
Lloh102:
	ldr	w10, [x10]
	orr	w8, w8, w9, lsl #12
	orr	w23, w8, w10, lsl #14
	ldr	w2, [x24]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	x1, x23
	bl	_WREG32
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbnz	x0, LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_3 Depth=1
Lloh103:
	adrp	x24, _mmSDMA0_F32_CNTL@GOTPAGE
Lloh104:
	ldr	x24, [x24, _mmSDMA0_F32_CNTL@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	bl	_RREG32
Lloh105:
	adrp	x8, _SDMA0_F32_CNTL@GOTPAGE
Lloh106:
	ldr	x8, [x8, _SDMA0_F32_CNTL@GOTPAGEOFF]
Lloh107:
	ldr	w1, [x8]
Lloh108:
	adrp	x8, _HALT@GOTPAGE
Lloh109:
	ldr	x8, [x8, _HALT@GOTPAGEOFF]
Lloh110:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	mov	x23, x0
	ldr	w2, [x24]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	x1, x23
	bl	_WREG32
LBB0_12:                                ;   in Loop: Header=BB0_3 Depth=1
Lloh111:
	adrp	x8, _SDMA0_GFX_RB_CNTL@GOTPAGE
Lloh112:
	ldr	x8, [x8, _SDMA0_GFX_RB_CNTL@GOTPAGEOFF]
Lloh113:
	ldr	w1, [x8]
Lloh114:
	adrp	x8, _RB_ENABLE@GOTPAGE
Lloh115:
	ldr	x8, [x8, _RB_ENABLE@GOTPAGEOFF]
Lloh116:
	ldr	w2, [x8]
	ldr	w0, [sp, #4]                    ; 4-byte Folded Reload
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x22, x0
Lloh117:
	adrp	x23, _mmSDMA0_GFX_RB_CNTL@GOTPAGE
Lloh118:
	ldr	x23, [x23, _mmSDMA0_GFX_RB_CNTL@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	x1, x22
	bl	_WREG32
Lloh119:
	adrp	x24, _mmSDMA0_GFX_IB_CNTL@GOTPAGE
Lloh120:
	ldr	x24, [x24, _mmSDMA0_GFX_IB_CNTL@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	bl	_RREG32
Lloh121:
	adrp	x8, _SDMA0_GFX_IB_CNTL@GOTPAGE
Lloh122:
	ldr	x8, [x8, _SDMA0_GFX_IB_CNTL@GOTPAGEOFF]
Lloh123:
	ldr	w1, [x8]
Lloh124:
	adrp	x8, _IB_ENABLE@GOTPAGE
Lloh125:
	ldr	x8, [x8, _IB_ENABLE@GOTPAGEOFF]
Lloh126:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x22, x0
	ldr	w2, [x24]
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v5_0_get_reg_offset
	mov	x1, x22
	bl	_WREG32
	add	x8, x26, x25
	mov	w9, #1
	str	w9, [x8, #20]
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_3 Depth=1
	mov	x0, x19
	mov	w1, #1
	bl	_sdma_v5_0_ctx_switch_enable
	mov	x0, x19
	mov	w1, #1
	bl	_sdma_v5_0_enable
LBB0_14:                                ;   in Loop: Header=BB0_3 Depth=1
	mov	x0, x21
	bl	_amdgpu_ring_test_ring
	cbnz	w0, LBB0_18
; %bb.15:                               ;   in Loop: Header=BB0_3 Depth=1
	ldr	x8, [x19]
	cmp	x21, x8
	b.ne	LBB0_2
; %bb.16:                               ;   in Loop: Header=BB0_3 Depth=1
	mov	x0, x19
	mov	w1, #1
	bl	_amdgpu_ttm_set_buffer_funcs_status
	b	LBB0_2
LBB0_17:
	mov	w0, #0
	b	LBB0_19
LBB0_18:
	add	x8, x26, x25
	str	wzr, [x8, #20]
LBB0_19:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpLdrGot	Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGot	Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGot	Lloh87, Lloh88
	.loh AdrpLdrGot	Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGot	Lloh77, Lloh78
	.loh AdrpLdrGot	Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGot	Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGot	Lloh119, Lloh120
	.loh AdrpLdrGot	Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.cfi_endproc
                                        ; -- End function
	.comm	_mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL,4,2 ; @mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
	.comm	_mmSDMA0_GFX_RB_CNTL,4,2        ; @mmSDMA0_GFX_RB_CNTL
	.comm	_SDMA0_GFX_RB_CNTL,4,2          ; @SDMA0_GFX_RB_CNTL
	.comm	_RB_SIZE,4,2                    ; @RB_SIZE
	.comm	_mmSDMA0_GFX_RB_RPTR,4,2        ; @mmSDMA0_GFX_RB_RPTR
	.comm	_mmSDMA0_GFX_RB_RPTR_HI,4,2     ; @mmSDMA0_GFX_RB_RPTR_HI
	.comm	_mmSDMA0_GFX_RB_WPTR,4,2        ; @mmSDMA0_GFX_RB_WPTR
	.comm	_mmSDMA0_GFX_RB_WPTR_HI,4,2     ; @mmSDMA0_GFX_RB_WPTR_HI
	.comm	_mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,4,2 ; @mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO
	.comm	_mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,4,2 ; @mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI
	.comm	_mmSDMA0_GFX_RB_WPTR_POLL_CNTL,4,2 ; @mmSDMA0_GFX_RB_WPTR_POLL_CNTL
	.comm	_SDMA0_GFX_RB_WPTR_POLL_CNTL,4,2 ; @SDMA0_GFX_RB_WPTR_POLL_CNTL
	.comm	_F32_POLL_ENABLE,4,2            ; @F32_POLL_ENABLE
	.comm	_mmSDMA0_GFX_RB_RPTR_ADDR_HI,4,2 ; @mmSDMA0_GFX_RB_RPTR_ADDR_HI
	.comm	_mmSDMA0_GFX_RB_RPTR_ADDR_LO,4,2 ; @mmSDMA0_GFX_RB_RPTR_ADDR_LO
	.comm	_RPTR_WRITEBACK_ENABLE,4,2      ; @RPTR_WRITEBACK_ENABLE
	.comm	_mmSDMA0_GFX_RB_BASE,4,2        ; @mmSDMA0_GFX_RB_BASE
	.comm	_mmSDMA0_GFX_RB_BASE_HI,4,2     ; @mmSDMA0_GFX_RB_BASE_HI
	.comm	_mmSDMA0_GFX_MINOR_PTR_UPDATE,4,2 ; @mmSDMA0_GFX_MINOR_PTR_UPDATE
	.comm	_mmSDMA0_GFX_DOORBELL,4,2       ; @mmSDMA0_GFX_DOORBELL
	.comm	_mmSDMA0_GFX_DOORBELL_OFFSET,4,2 ; @mmSDMA0_GFX_DOORBELL_OFFSET
	.comm	_SDMA0_GFX_DOORBELL,4,2         ; @SDMA0_GFX_DOORBELL
	.comm	_ENABLE,4,2                     ; @ENABLE
	.comm	_SDMA0_GFX_DOORBELL_OFFSET,4,2  ; @SDMA0_GFX_DOORBELL_OFFSET
	.comm	_OFFSET,4,2                     ; @OFFSET
	.comm	_mmSDMA0_CNTL,4,2               ; @mmSDMA0_CNTL
	.comm	_SDMA0_CNTL,4,2                 ; @SDMA0_CNTL
	.comm	_UTC_L1_ENABLE,4,2              ; @UTC_L1_ENABLE
	.comm	_MIDCMD_PREEMPT_ENABLE,4,2      ; @MIDCMD_PREEMPT_ENABLE
	.comm	_mmSDMA0_UTCL1_CNTL,4,2         ; @mmSDMA0_UTCL1_CNTL
	.comm	_SDMA0_UTCL1_CNTL,4,2           ; @SDMA0_UTCL1_CNTL
	.comm	_RESP_MODE,4,2                  ; @RESP_MODE
	.comm	_REDO_DELAY,4,2                 ; @REDO_DELAY
	.comm	_mmSDMA0_UTCL1_PAGE,4,2         ; @mmSDMA0_UTCL1_PAGE
	.comm	_CACHE_READ_POLICY_L2__DEFAULT,4,2 ; @CACHE_READ_POLICY_L2__DEFAULT
	.comm	_CACHE_WRITE_POLICY_L2__DEFAULT,4,2 ; @CACHE_WRITE_POLICY_L2__DEFAULT
	.comm	_mmSDMA0_F32_CNTL,4,2           ; @mmSDMA0_F32_CNTL
	.comm	_SDMA0_F32_CNTL,4,2             ; @SDMA0_F32_CNTL
	.comm	_HALT,4,2                       ; @HALT
	.comm	_RB_ENABLE,4,2                  ; @RB_ENABLE
	.comm	_mmSDMA0_GFX_IB_CNTL,4,2        ; @mmSDMA0_GFX_IB_CNTL
	.comm	_SDMA0_GFX_IB_CNTL,4,2          ; @SDMA0_GFX_IB_CNTL
	.comm	_IB_ENABLE,4,2                  ; @IB_ENABLE
	.comm	_IB_SWAP_ENABLE,4,2             ; @IB_SWAP_ENABLE
	.comm	_RB_SWAP_ENABLE,4,2             ; @RB_SWAP_ENABLE
	.comm	_RPTR_WRITEBACK_SWAP_ENABLE,4,2 ; @RPTR_WRITEBACK_SWAP_ENABLE
	.no_dead_strip	_sdma_v5_0_gfx_resume
.subsections_via_symbols
