	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v1_0_stop_spg_mode
_vcn_v1_0_stop_spg_mode:                ## @vcn_v1_0_stop_spg_mode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_UVD@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_mmUVD_STATUS@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	movq	_UVD_STATUS__IDLE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%esi, %esi
	movl	$7, %r8d
	callq	_SOC15_WAIT_ON_RREG
	movq	_UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK@GOTPCREL(%rip), %rax
	movq	_UVD_LMI_STATUS__READ_CLEAN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	_UVD_LMI_STATUS__WRITE_CLEAN_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movl	(%rbx), %edi
	movq	_mmUVD_LMI_STATUS@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	xorl	%esi, %esi
	movl	%ecx, %r8d
	callq	_SOC15_WAIT_ON_RREG
	movl	(%rbx), %edi
	movq	_mmUVD_SOFT_RESET@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	callq	_WREG32_P
	movq	_UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK@GOTPCREL(%rip), %rax
	movq	_UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movl	(%rbx), %edi
	movl	(%r13), %edx
	xorl	%esi, %esi
	movl	%ecx, %r8d
	callq	_SOC15_WAIT_ON_RREG
	movl	(%rbx), %edi
	movq	_mmUVD_VCPU_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_VCPU_CNTL__CLK_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	(%rbx), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	callq	_WREG32_P
	movl	(%rbx), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	callq	_WREG32_P
	movl	(%rbx), %edi
	movl	(%r15), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movq	%r14, %rdi
	callq	_vcn_v1_0_enable_clock_gating
	movq	%r14, %rdi
	callq	_vcn_1_0_enable_static_power_gating
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_STATUS,4,2               ## @mmUVD_STATUS
	.comm	_UVD_STATUS__IDLE,4,2           ## @UVD_STATUS__IDLE
	.comm	_UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK,4,2 ## @UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK
	.comm	_UVD_LMI_STATUS__READ_CLEAN_MASK,4,2 ## @UVD_LMI_STATUS__READ_CLEAN_MASK
	.comm	_UVD_LMI_STATUS__WRITE_CLEAN_MASK,4,2 ## @UVD_LMI_STATUS__WRITE_CLEAN_MASK
	.comm	_UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK,4,2 ## @UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK
	.comm	_mmUVD_LMI_STATUS,4,2           ## @mmUVD_LMI_STATUS
	.comm	_mmUVD_SOFT_RESET,4,2           ## @mmUVD_SOFT_RESET
	.comm	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
	.comm	_UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK,4,2 ## @UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK
	.comm	_UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK,4,2 ## @UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK
	.comm	_mmUVD_VCPU_CNTL,4,2            ## @mmUVD_VCPU_CNTL
	.comm	_UVD_VCPU_CNTL__CLK_EN_MASK,4,2 ## @UVD_VCPU_CNTL__CLK_EN_MASK
	.comm	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
	.no_dead_strip	_vcn_v1_0_stop_spg_mode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v1_0_stop_spg_mode
_vcn_v1_0_stop_spg_mode:                ; @vcn_v1_0_stop_spg_mode
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x20, _UVD@GOTPAGE
Lloh1:
	ldr	x20, [x20, _UVD@GOTPAGEOFF]
	ldr	w0, [x20]
Lloh2:
	adrp	x21, _mmUVD_STATUS@GOTPAGE
Lloh3:
	ldr	x21, [x21, _mmUVD_STATUS@GOTPAGEOFF]
	ldr	w2, [x21]
Lloh4:
	adrp	x8, _UVD_STATUS__IDLE@GOTPAGE
Lloh5:
	ldr	x8, [x8, _UVD_STATUS__IDLE@GOTPAGEOFF]
Lloh6:
	ldr	w3, [x8]
	mov	w1, #0
	mov	w4, #7
	bl	_SOC15_WAIT_ON_RREG
Lloh7:
	adrp	x8, _UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK@GOTPAGE
Lloh8:
	ldr	x8, [x8, _UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
Lloh10:
	adrp	x9, _UVD_LMI_STATUS__READ_CLEAN_MASK@GOTPAGE
Lloh11:
	ldr	x9, [x9, _UVD_LMI_STATUS__READ_CLEAN_MASK@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh13:
	adrp	x9, _UVD_LMI_STATUS__WRITE_CLEAN_MASK@GOTPAGE
Lloh14:
	ldr	x9, [x9, _UVD_LMI_STATUS__WRITE_CLEAN_MASK@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh16:
	adrp	x9, _UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK@GOTPAGE
Lloh17:
	ldr	x9, [x9, _UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	orr	w3, w8, w9
	ldr	w0, [x20]
Lloh19:
	adrp	x23, _mmUVD_LMI_STATUS@GOTPAGE
Lloh20:
	ldr	x23, [x23, _mmUVD_LMI_STATUS@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	w1, #0
	mov	x4, x3
	bl	_SOC15_WAIT_ON_RREG
	ldr	w0, [x20]
Lloh21:
	adrp	x22, _mmUVD_SOFT_RESET@GOTPAGE
Lloh22:
	ldr	x22, [x22, _mmUVD_SOFT_RESET@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh23:
	adrp	x8, _UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPAGE
Lloh24:
	ldr	x8, [x8, _UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w1, [x8]
	mvn	w2, w1
	bl	_WREG32_P
Lloh26:
	adrp	x8, _UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK@GOTPAGE
Lloh27:
	ldr	x8, [x8, _UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
Lloh29:
	adrp	x9, _UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK@GOTPAGE
Lloh30:
	ldr	x9, [x9, _UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK@GOTPAGEOFF]
Lloh31:
	ldr	w9, [x9]
	orr	w3, w9, w8
	ldr	w0, [x20]
	ldr	w2, [x23]
	mov	w1, #0
	mov	x4, x3
	bl	_SOC15_WAIT_ON_RREG
	ldr	w0, [x20]
Lloh32:
	adrp	x8, _mmUVD_VCPU_CNTL@GOTPAGE
Lloh33:
	ldr	x8, [x8, _mmUVD_VCPU_CNTL@GOTPAGEOFF]
Lloh34:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh35:
	adrp	x8, _UVD_VCPU_CNTL__CLK_EN_MASK@GOTPAGE
Lloh36:
	ldr	x8, [x8, _UVD_VCPU_CNTL__CLK_EN_MASK@GOTPAGEOFF]
Lloh37:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w0, [x20]
	ldr	w2, [x22]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh38:
	adrp	x8, _UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPAGE
Lloh39:
	ldr	x8, [x8, _UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh40:
	ldr	w1, [x8]
	mvn	w2, w1
	bl	_WREG32_P
	ldr	w0, [x20]
	ldr	w2, [x22]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh41:
	adrp	x8, _UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPAGE
Lloh42:
	ldr	x8, [x8, _UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh43:
	ldr	w1, [x8]
	mvn	w2, w1
	bl	_WREG32_P
	ldr	w0, [x20]
	ldr	w2, [x21]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	mov	x0, x19
	bl	_vcn_v1_0_enable_clock_gating
	mov	x0, x19
	bl	_vcn_1_0_enable_static_power_gating
	mov	w0, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_STATUS,4,2               ; @mmUVD_STATUS
	.comm	_UVD_STATUS__IDLE,4,2           ; @UVD_STATUS__IDLE
	.comm	_UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK,4,2 ; @UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK
	.comm	_UVD_LMI_STATUS__READ_CLEAN_MASK,4,2 ; @UVD_LMI_STATUS__READ_CLEAN_MASK
	.comm	_UVD_LMI_STATUS__WRITE_CLEAN_MASK,4,2 ; @UVD_LMI_STATUS__WRITE_CLEAN_MASK
	.comm	_UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK,4,2 ; @UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK
	.comm	_mmUVD_LMI_STATUS,4,2           ; @mmUVD_LMI_STATUS
	.comm	_mmUVD_SOFT_RESET,4,2           ; @mmUVD_SOFT_RESET
	.comm	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
	.comm	_UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK,4,2 ; @UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK
	.comm	_UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK,4,2 ; @UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK
	.comm	_mmUVD_VCPU_CNTL,4,2            ; @mmUVD_VCPU_CNTL
	.comm	_UVD_VCPU_CNTL__CLK_EN_MASK,4,2 ; @UVD_VCPU_CNTL__CLK_EN_MASK
	.comm	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
	.no_dead_strip	_vcn_v1_0_stop_spg_mode
.subsections_via_symbols
