	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v2_0_hw_init
_vcn_v2_0_hw_init:                      ## @vcn_v2_0_hw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	16(%rdi), %rbx
	movq	24(%rdi), %rax
	leaq	24(%rbx), %r14
	movl	28(%rbx), %edx
	movl	32(%rbx), %esi
	xorl	%ecx, %ecx
	callq	*(%rax)
	movl	$1, 24(%rbx)
	movq	%r14, %rdi
	callq	_amdgpu_ring_test_ring
	testl	%eax, %eax
	jne	LBB0_1
## %bb.2:
	cmpl	$0, 8(%r15)
	jle	LBB0_6
## %bb.3:
	xorl	%ebx, %ebx
	xorl	%r14d, %r14d
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movq	16(%r15), %rax
	movq	16(%rax), %r12
	leaq	(%r12,%rbx), %rdi
	movl	$1, (%r12,%rbx)
	callq	_amdgpu_ring_test_ring
	testl	%eax, %eax
	jne	LBB0_8
## %bb.5:                               ##   in Loop: Header=BB0_4 Depth=1
	incq	%r14
	movslq	8(%r15), %rax
	addq	$12, %rbx
	cmpq	%rax, %r14
	jl	LBB0_4
LBB0_6:
	movq	16(%r15), %r14
	movl	$1, (%r14)
	movq	%r14, %rdi
	callq	_amdgpu_ring_test_ring
	testl	%eax, %eax
	je	LBB0_9
LBB0_1:
	movl	$0, (%r14)
LBB0_10:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_8:
	movl	$0, (%r12,%rbx)
	jmp	LBB0_10
LBB0_9:
	movq	_AMD_PG_SUPPORT_VCN_DPG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%r15), %eax
	leaq	L_.str.2(%rip), %rax
	leaq	L_.str.1(%rip), %rsi
	cmoveq	%rax, %rsi
	leaq	L_.str(%rip), %rdi
	callq	_DRM_INFO
	xorl	%eax, %eax
	jmp	LBB0_10
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"VCN decode and encode initialized successfully(under %s).\n"

	.comm	_AMD_PG_SUPPORT_VCN_DPG,4,2     ## @AMD_PG_SUPPORT_VCN_DPG
L_.str.1:                               ## @.str.1
	.asciz	"DPG Mode"

L_.str.2:                               ## @.str.2
	.asciz	"SPG Mode"

	.no_dead_strip	_vcn_v2_0_hw_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v2_0_hw_init
_vcn_v2_0_hw_init:                      ; @vcn_v2_0_hw_init
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldp	x20, x8, [x0, #16]
	ldr	x8, [x8]
	ldp	w2, w1, [x20, #28]
	mov	w3, #0
	blr	x8
	mov	w8, #1
	str	w8, [x20, #24]!
	mov	x0, x20
	bl	_amdgpu_ring_test_ring
	cbnz	w0, LBB0_6
; %bb.1:
	ldr	w8, [x19, #8]
	cmp	w8, #1
	b.lt	LBB0_5
; %bb.2:
	mov	x20, #0
	mov	x21, #0
	mov	w22, #1
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #16]
	ldr	x23, [x8, #16]
	add	x0, x23, x20
	str	w22, [x0]
	bl	_amdgpu_ring_test_ring
	cbnz	w0, LBB0_8
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	add	x21, x21, #1
	ldrsw	x8, [x19, #8]
	add	x20, x20, #12
	cmp	x21, x8
	b.lt	LBB0_3
LBB0_5:
	ldr	x20, [x19, #16]
	mov	w8, #1
	str	w8, [x20]
	mov	x0, x20
	bl	_amdgpu_ring_test_ring
	cbz	w0, LBB0_9
LBB0_6:
	str	wzr, [x20]
LBB0_7:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_8:
	str	wzr, [x23, x20]
	b	LBB0_7
LBB0_9:
	ldr	w8, [x19]
Lloh0:
	adrp	x9, _AMD_PG_SUPPORT_VCN_DPG@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_PG_SUPPORT_VCN_DPG@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
Lloh3:
	adrp	x10, l_.str.1@PAGE
Lloh4:
	add	x10, x10, l_.str.1@PAGEOFF
Lloh5:
	adrp	x11, l_.str.2@PAGE
Lloh6:
	add	x11, x11, l_.str.2@PAGEOFF
	tst	w9, w8
	csel	x1, x11, x10, eq
Lloh7:
	adrp	x0, l_.str@PAGE
Lloh8:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_INFO
	mov	w0, #0
	b	LBB0_7
	.loh AdrpAdd	Lloh7, Lloh8
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"VCN decode and encode initialized successfully(under %s).\n"

	.comm	_AMD_PG_SUPPORT_VCN_DPG,4,2     ; @AMD_PG_SUPPORT_VCN_DPG
l_.str.1:                               ; @.str.1
	.asciz	"DPG Mode"

l_.str.2:                               ; @.str.2
	.asciz	"SPG Mode"

	.no_dead_strip	_vcn_v2_0_hw_init
.subsections_via_symbols
