	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function exynos_ppmu_v2_disable
_exynos_ppmu_v2_disable:                ## @exynos_ppmu_v2_disable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	subq	$16, %rsp
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	callq	_devfreq_event_get_drvdata
	movq	_PPMU_CCNT_MASK@GOTPCREL(%rip), %rcx
	movq	_PPMU_PMCNT0_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	movq	_PPMU_PMCNT1_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_PPMU_PMCNT2_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_PPMU_PMCNT3_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	%rax, %r14
	movl	(%rax), %edi
	movq	_PPMU_V2_FLAG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%ebx, %edx
	callq	_regmap_write
	testl	%eax, %eax
	js	LBB0_20
## %bb.1:
	movl	(%r14), %edi
	movq	_PPMU_V2_INTENC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%ebx, %edx
	callq	_regmap_write
	testl	%eax, %eax
	js	LBB0_20
## %bb.2:
	movl	(%r14), %edi
	movq	_PPMU_V2_CNTENC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%ebx, %edx
	callq	_regmap_write
	testl	%eax, %eax
	js	LBB0_20
## %bb.3:
	movl	(%r14), %edi
	movq	_PPMU_V2_CNT_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%ebx, %edx
	callq	_regmap_write
	testl	%eax, %eax
	js	LBB0_20
## %bb.4:
	movl	(%r14), %edi
	movq	_PPMU_V2_CIG_CFG0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	testl	%eax, %eax
	js	LBB0_20
## %bb.5:
	movl	(%r14), %edi
	movq	_PPMU_V2_CIG_CFG1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	testl	%eax, %eax
	js	LBB0_20
## %bb.6:
	movl	(%r14), %edi
	movq	_PPMU_V2_CIG_CFG2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	testl	%eax, %eax
	js	LBB0_20
## %bb.7:
	movl	(%r14), %edi
	movq	_PPMU_V2_CIG_RESULT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	testl	%eax, %eax
	js	LBB0_20
## %bb.8:
	movl	(%r14), %edi
	movq	_PPMU_V2_CNT_AUTO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	testl	%eax, %eax
	js	LBB0_20
## %bb.9:
	movl	(%r14), %edi
	movq	_PPMU_V2_CH_EV0_TYPE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	testl	%eax, %eax
	js	LBB0_20
## %bb.10:
	movl	(%r14), %edi
	movq	_PPMU_V2_CH_EV1_TYPE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	testl	%eax, %eax
	js	LBB0_20
## %bb.11:
	movl	(%r14), %edi
	movq	_PPMU_V2_CH_EV2_TYPE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	testl	%eax, %eax
	js	LBB0_20
## %bb.12:
	movl	(%r14), %edi
	movq	_PPMU_V2_CH_EV3_TYPE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	testl	%eax, %eax
	js	LBB0_20
## %bb.13:
	movl	(%r14), %edi
	movq	_PPMU_V2_SM_ID_V@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	testl	%eax, %eax
	js	LBB0_20
## %bb.14:
	movl	(%r14), %edi
	movq	_PPMU_V2_SM_ID_A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	testl	%eax, %eax
	js	LBB0_20
## %bb.15:
	movl	(%r14), %edi
	movq	_PPMU_V2_SM_OTHERS_V@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	testl	%eax, %eax
	js	LBB0_20
## %bb.16:
	movl	(%r14), %edi
	movq	_PPMU_V2_SM_OTHERS_A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	testl	%eax, %eax
	js	LBB0_20
## %bb.17:
	movl	(%r14), %edi
	movq	_PPMU_V2_INTERRUPT_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	testl	%eax, %eax
	js	LBB0_20
## %bb.18:
	movl	(%r14), %edi
	movq	_PPMU_V2_PMNC@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	leaq	-20(%rbp), %rdx
	callq	_regmap_read
	testl	%eax, %eax
	js	LBB0_20
## %bb.19:
	movq	_PPMU_PMNC_ENABLE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	andl	-20(%rbp), %edx
	movl	%edx, -20(%rbp)
	movl	(%r14), %edi
	movl	(%rbx), %esi
	callq	_regmap_write
	movl	%eax, %ecx
	sarl	$31, %eax
	andl	%ecx, %eax
LBB0_20:
	addq	$16, %rsp
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PPMU_CCNT_MASK,4,2             ## @PPMU_CCNT_MASK
	.comm	_PPMU_PMCNT0_MASK,4,2           ## @PPMU_PMCNT0_MASK
	.comm	_PPMU_PMCNT1_MASK,4,2           ## @PPMU_PMCNT1_MASK
	.comm	_PPMU_PMCNT2_MASK,4,2           ## @PPMU_PMCNT2_MASK
	.comm	_PPMU_PMCNT3_MASK,4,2           ## @PPMU_PMCNT3_MASK
	.comm	_PPMU_V2_FLAG,4,2               ## @PPMU_V2_FLAG
	.comm	_PPMU_V2_INTENC,4,2             ## @PPMU_V2_INTENC
	.comm	_PPMU_V2_CNTENC,4,2             ## @PPMU_V2_CNTENC
	.comm	_PPMU_V2_CNT_RESET,4,2          ## @PPMU_V2_CNT_RESET
	.comm	_PPMU_V2_CIG_CFG0,4,2           ## @PPMU_V2_CIG_CFG0
	.comm	_PPMU_V2_CIG_CFG1,4,2           ## @PPMU_V2_CIG_CFG1
	.comm	_PPMU_V2_CIG_CFG2,4,2           ## @PPMU_V2_CIG_CFG2
	.comm	_PPMU_V2_CIG_RESULT,4,2         ## @PPMU_V2_CIG_RESULT
	.comm	_PPMU_V2_CNT_AUTO,4,2           ## @PPMU_V2_CNT_AUTO
	.comm	_PPMU_V2_CH_EV0_TYPE,4,2        ## @PPMU_V2_CH_EV0_TYPE
	.comm	_PPMU_V2_CH_EV1_TYPE,4,2        ## @PPMU_V2_CH_EV1_TYPE
	.comm	_PPMU_V2_CH_EV2_TYPE,4,2        ## @PPMU_V2_CH_EV2_TYPE
	.comm	_PPMU_V2_CH_EV3_TYPE,4,2        ## @PPMU_V2_CH_EV3_TYPE
	.comm	_PPMU_V2_SM_ID_V,4,2            ## @PPMU_V2_SM_ID_V
	.comm	_PPMU_V2_SM_ID_A,4,2            ## @PPMU_V2_SM_ID_A
	.comm	_PPMU_V2_SM_OTHERS_V,4,2        ## @PPMU_V2_SM_OTHERS_V
	.comm	_PPMU_V2_SM_OTHERS_A,4,2        ## @PPMU_V2_SM_OTHERS_A
	.comm	_PPMU_V2_INTERRUPT_RESET,4,2    ## @PPMU_V2_INTERRUPT_RESET
	.comm	_PPMU_V2_PMNC,4,2               ## @PPMU_V2_PMNC
	.comm	_PPMU_PMNC_ENABLE_MASK,4,2      ## @PPMU_PMNC_ENABLE_MASK
	.no_dead_strip	_exynos_ppmu_v2_disable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function exynos_ppmu_v2_disable
_exynos_ppmu_v2_disable:                ; @exynos_ppmu_v2_disable
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #48
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	bl	_devfreq_event_get_drvdata
	mov	x19, x0
Lloh0:
	adrp	x8, _PPMU_CCNT_MASK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PPMU_CCNT_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _PPMU_PMCNT0_MASK@GOTPAGE
Lloh4:
	ldr	x9, [x9, _PPMU_PMCNT0_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh6:
	adrp	x9, _PPMU_PMCNT1_MASK@GOTPAGE
Lloh7:
	ldr	x9, [x9, _PPMU_PMCNT1_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh9:
	adrp	x9, _PPMU_PMCNT2_MASK@GOTPAGE
Lloh10:
	ldr	x9, [x9, _PPMU_PMCNT2_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh12:
	adrp	x9, _PPMU_PMCNT3_MASK@GOTPAGE
Lloh13:
	ldr	x9, [x9, _PPMU_PMCNT3_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	orr	w20, w8, w9
	ldr	w0, [x0]
Lloh15:
	adrp	x8, _PPMU_V2_FLAG@GOTPAGE
Lloh16:
	ldr	x8, [x8, _PPMU_V2_FLAG@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	x2, x20
	bl	_regmap_write
	tbnz	w0, #31, LBB0_20
; %bb.1:
	ldr	w0, [x19]
Lloh18:
	adrp	x8, _PPMU_V2_INTENC@GOTPAGE
Lloh19:
	ldr	x8, [x8, _PPMU_V2_INTENC@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	mov	x2, x20
	bl	_regmap_write
	tbnz	w0, #31, LBB0_20
; %bb.2:
	ldr	w0, [x19]
Lloh21:
	adrp	x8, _PPMU_V2_CNTENC@GOTPAGE
Lloh22:
	ldr	x8, [x8, _PPMU_V2_CNTENC@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	mov	x2, x20
	bl	_regmap_write
	tbnz	w0, #31, LBB0_20
; %bb.3:
	ldr	w0, [x19]
Lloh24:
	adrp	x8, _PPMU_V2_CNT_RESET@GOTPAGE
Lloh25:
	ldr	x8, [x8, _PPMU_V2_CNT_RESET@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	x2, x20
	bl	_regmap_write
	tbnz	w0, #31, LBB0_20
; %bb.4:
	ldr	w0, [x19]
Lloh27:
	adrp	x8, _PPMU_V2_CIG_CFG0@GOTPAGE
Lloh28:
	ldr	x8, [x8, _PPMU_V2_CIG_CFG0@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_regmap_write
	tbnz	w0, #31, LBB0_20
; %bb.5:
	ldr	w0, [x19]
Lloh30:
	adrp	x8, _PPMU_V2_CIG_CFG1@GOTPAGE
Lloh31:
	ldr	x8, [x8, _PPMU_V2_CIG_CFG1@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_regmap_write
	tbnz	w0, #31, LBB0_20
; %bb.6:
	ldr	w0, [x19]
Lloh33:
	adrp	x8, _PPMU_V2_CIG_CFG2@GOTPAGE
Lloh34:
	ldr	x8, [x8, _PPMU_V2_CIG_CFG2@GOTPAGEOFF]
Lloh35:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_regmap_write
	tbnz	w0, #31, LBB0_20
; %bb.7:
	ldr	w0, [x19]
Lloh36:
	adrp	x8, _PPMU_V2_CIG_RESULT@GOTPAGE
Lloh37:
	ldr	x8, [x8, _PPMU_V2_CIG_RESULT@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_regmap_write
	tbnz	w0, #31, LBB0_20
; %bb.8:
	ldr	w0, [x19]
Lloh39:
	adrp	x8, _PPMU_V2_CNT_AUTO@GOTPAGE
Lloh40:
	ldr	x8, [x8, _PPMU_V2_CNT_AUTO@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_regmap_write
	tbnz	w0, #31, LBB0_20
; %bb.9:
	ldr	w0, [x19]
Lloh42:
	adrp	x8, _PPMU_V2_CH_EV0_TYPE@GOTPAGE
Lloh43:
	ldr	x8, [x8, _PPMU_V2_CH_EV0_TYPE@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_regmap_write
	tbnz	w0, #31, LBB0_20
; %bb.10:
	ldr	w0, [x19]
Lloh45:
	adrp	x8, _PPMU_V2_CH_EV1_TYPE@GOTPAGE
Lloh46:
	ldr	x8, [x8, _PPMU_V2_CH_EV1_TYPE@GOTPAGEOFF]
Lloh47:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_regmap_write
	tbnz	w0, #31, LBB0_20
; %bb.11:
	ldr	w0, [x19]
Lloh48:
	adrp	x8, _PPMU_V2_CH_EV2_TYPE@GOTPAGE
Lloh49:
	ldr	x8, [x8, _PPMU_V2_CH_EV2_TYPE@GOTPAGEOFF]
Lloh50:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_regmap_write
	tbnz	w0, #31, LBB0_20
; %bb.12:
	ldr	w0, [x19]
Lloh51:
	adrp	x8, _PPMU_V2_CH_EV3_TYPE@GOTPAGE
Lloh52:
	ldr	x8, [x8, _PPMU_V2_CH_EV3_TYPE@GOTPAGEOFF]
Lloh53:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_regmap_write
	tbnz	w0, #31, LBB0_20
; %bb.13:
	ldr	w0, [x19]
Lloh54:
	adrp	x8, _PPMU_V2_SM_ID_V@GOTPAGE
Lloh55:
	ldr	x8, [x8, _PPMU_V2_SM_ID_V@GOTPAGEOFF]
Lloh56:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_regmap_write
	tbnz	w0, #31, LBB0_20
; %bb.14:
	ldr	w0, [x19]
Lloh57:
	adrp	x8, _PPMU_V2_SM_ID_A@GOTPAGE
Lloh58:
	ldr	x8, [x8, _PPMU_V2_SM_ID_A@GOTPAGEOFF]
Lloh59:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_regmap_write
	tbnz	w0, #31, LBB0_20
; %bb.15:
	ldr	w0, [x19]
Lloh60:
	adrp	x8, _PPMU_V2_SM_OTHERS_V@GOTPAGE
Lloh61:
	ldr	x8, [x8, _PPMU_V2_SM_OTHERS_V@GOTPAGEOFF]
Lloh62:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_regmap_write
	tbnz	w0, #31, LBB0_20
; %bb.16:
	ldr	w0, [x19]
Lloh63:
	adrp	x8, _PPMU_V2_SM_OTHERS_A@GOTPAGE
Lloh64:
	ldr	x8, [x8, _PPMU_V2_SM_OTHERS_A@GOTPAGEOFF]
Lloh65:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_regmap_write
	tbnz	w0, #31, LBB0_20
; %bb.17:
	ldr	w0, [x19]
Lloh66:
	adrp	x8, _PPMU_V2_INTERRUPT_RESET@GOTPAGE
Lloh67:
	ldr	x8, [x8, _PPMU_V2_INTERRUPT_RESET@GOTPAGEOFF]
Lloh68:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_regmap_write
	tbnz	w0, #31, LBB0_20
; %bb.18:
	ldr	w0, [x19]
Lloh69:
	adrp	x20, _PPMU_V2_PMNC@GOTPAGE
Lloh70:
	ldr	x20, [x20, _PPMU_V2_PMNC@GOTPAGEOFF]
	ldr	w1, [x20]
	add	x2, sp, #12
	bl	_regmap_read
	tbnz	w0, #31, LBB0_20
; %bb.19:
Lloh71:
	adrp	x8, _PPMU_PMNC_ENABLE_MASK@GOTPAGE
Lloh72:
	ldr	x8, [x8, _PPMU_PMNC_ENABLE_MASK@GOTPAGEOFF]
Lloh73:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	bic	w2, w9, w8
	str	w2, [sp, #12]
	ldr	w0, [x19]
	ldr	w1, [x20]
	bl	_regmap_write
	cmp	w0, #0
	csel	w0, w0, wzr, lt
LBB0_20:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	ret
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGot	Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.cfi_endproc
                                        ; -- End function
	.comm	_PPMU_CCNT_MASK,4,2             ; @PPMU_CCNT_MASK
	.comm	_PPMU_PMCNT0_MASK,4,2           ; @PPMU_PMCNT0_MASK
	.comm	_PPMU_PMCNT1_MASK,4,2           ; @PPMU_PMCNT1_MASK
	.comm	_PPMU_PMCNT2_MASK,4,2           ; @PPMU_PMCNT2_MASK
	.comm	_PPMU_PMCNT3_MASK,4,2           ; @PPMU_PMCNT3_MASK
	.comm	_PPMU_V2_FLAG,4,2               ; @PPMU_V2_FLAG
	.comm	_PPMU_V2_INTENC,4,2             ; @PPMU_V2_INTENC
	.comm	_PPMU_V2_CNTENC,4,2             ; @PPMU_V2_CNTENC
	.comm	_PPMU_V2_CNT_RESET,4,2          ; @PPMU_V2_CNT_RESET
	.comm	_PPMU_V2_CIG_CFG0,4,2           ; @PPMU_V2_CIG_CFG0
	.comm	_PPMU_V2_CIG_CFG1,4,2           ; @PPMU_V2_CIG_CFG1
	.comm	_PPMU_V2_CIG_CFG2,4,2           ; @PPMU_V2_CIG_CFG2
	.comm	_PPMU_V2_CIG_RESULT,4,2         ; @PPMU_V2_CIG_RESULT
	.comm	_PPMU_V2_CNT_AUTO,4,2           ; @PPMU_V2_CNT_AUTO
	.comm	_PPMU_V2_CH_EV0_TYPE,4,2        ; @PPMU_V2_CH_EV0_TYPE
	.comm	_PPMU_V2_CH_EV1_TYPE,4,2        ; @PPMU_V2_CH_EV1_TYPE
	.comm	_PPMU_V2_CH_EV2_TYPE,4,2        ; @PPMU_V2_CH_EV2_TYPE
	.comm	_PPMU_V2_CH_EV3_TYPE,4,2        ; @PPMU_V2_CH_EV3_TYPE
	.comm	_PPMU_V2_SM_ID_V,4,2            ; @PPMU_V2_SM_ID_V
	.comm	_PPMU_V2_SM_ID_A,4,2            ; @PPMU_V2_SM_ID_A
	.comm	_PPMU_V2_SM_OTHERS_V,4,2        ; @PPMU_V2_SM_OTHERS_V
	.comm	_PPMU_V2_SM_OTHERS_A,4,2        ; @PPMU_V2_SM_OTHERS_A
	.comm	_PPMU_V2_INTERRUPT_RESET,4,2    ; @PPMU_V2_INTERRUPT_RESET
	.comm	_PPMU_V2_PMNC,4,2               ; @PPMU_V2_PMNC
	.comm	_PPMU_PMNC_ENABLE_MASK,4,2      ; @PPMU_PMNC_ENABLE_MASK
	.no_dead_strip	_exynos_ppmu_v2_disable
.subsections_via_symbols
