	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function si_enable_dma_mgcg
_si_enable_dma_mgcg:                    ## @si_enable_dma_mgcg
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	testl	%esi, %esi
	je	LBB0_7
## %bb.1:
	movq	_RADEON_CG_SUPPORT_SDMA_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rdi)
	je	LBB0_7
## %bb.2:
	movq	_DMA0_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_DMA_POWER_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	addl	%ebx, %edi
	callq	_RREG32
	movq	_MEM_POWER_OVERRIDE@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	notl	%esi
	andl	%eax, %esi
	cmpl	%eax, %esi
	je	LBB0_4
## %bb.3:
	movl	(%r15), %edi
	addl	%ebx, %edi
	callq	_WREG32
LBB0_4:
	movq	_DMA_CLK_CTRL@GOTPCREL(%rip), %rax
	addl	(%rax), %ebx
	movl	$256, %r14d                     ## imm = 0x100
	movl	%ebx, %edi
	movl	$256, %esi                      ## imm = 0x100
	callq	_WREG32
	movq	_DMA1_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	(%r15), %edi
	addl	%ebx, %edi
	callq	_RREG32
	movl	(%r12), %esi
	notl	%esi
	andl	%eax, %esi
	cmpl	%eax, %esi
	je	LBB0_6
## %bb.5:
	movl	(%r15), %edi
	addl	%ebx, %edi
	callq	_WREG32
	jmp	LBB0_6
LBB0_7:
	movq	_DMA0_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_DMA_POWER_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	addl	%ebx, %edi
	callq	_RREG32
	movq	_MEM_POWER_OVERRIDE@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	orl	%eax, %esi
	cmpl	%eax, %esi
	je	LBB0_9
## %bb.8:
	movl	(%r14), %edi
	addl	%ebx, %edi
	callq	_WREG32
LBB0_9:
	movq	_DMA_CLK_CTRL@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	addl	%ebx, %edi
	callq	_RREG32
	cmpl	$-16777216, %eax                ## imm = 0xFF000000
	je	LBB0_11
## %bb.10:
	addl	(%r12), %ebx
	movl	%ebx, %edi
	movl	$-16777216, %esi                ## imm = 0xFF000000
	callq	_WREG32
LBB0_11:
	movq	_DMA1_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	(%r14), %edi
	addl	%ebx, %edi
	callq	_RREG32
	movl	(%r15), %esi
	orl	%eax, %esi
	cmpl	%eax, %esi
	je	LBB0_13
## %bb.12:
	movl	(%r14), %edi
	addl	%ebx, %edi
	callq	_WREG32
LBB0_13:
	movl	(%r12), %edi
	addl	%ebx, %edi
	callq	_RREG32
	movl	$-16777216, %r14d               ## imm = 0xFF000000
	cmpl	$-16777216, %eax                ## imm = 0xFF000000
	jne	LBB0_6
## %bb.14:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_6:
	movq	_DMA_CLK_CTRL@GOTPCREL(%rip), %rax
	addl	(%rax), %ebx
	movl	%ebx, %edi
	movl	%r14d, %esi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_CG_SUPPORT_SDMA_MGCG,4,2 ## @RADEON_CG_SUPPORT_SDMA_MGCG
	.comm	_DMA0_REGISTER_OFFSET,4,2       ## @DMA0_REGISTER_OFFSET
	.comm	_DMA1_REGISTER_OFFSET,4,2       ## @DMA1_REGISTER_OFFSET
	.comm	_DMA_POWER_CNTL,4,2             ## @DMA_POWER_CNTL
	.comm	_MEM_POWER_OVERRIDE,4,2         ## @MEM_POWER_OVERRIDE
	.comm	_DMA_CLK_CTRL,4,2               ## @DMA_CLK_CTRL
	.no_dead_strip	_si_enable_dma_mgcg
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function si_enable_dma_mgcg
_si_enable_dma_mgcg:                    ; @si_enable_dma_mgcg
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
Lloh0:
	adrp	x20, _DMA_CLK_CTRL@GOTPAGE
Lloh1:
	ldr	x20, [x20, _DMA_CLK_CTRL@GOTPAGEOFF]
	cbz	w1, LBB0_6
; %bb.1:
	ldr	w8, [x0]
Lloh2:
	adrp	x9, _RADEON_CG_SUPPORT_SDMA_MGCG@GOTPAGE
Lloh3:
	ldr	x9, [x9, _RADEON_CG_SUPPORT_SDMA_MGCG@GOTPAGEOFF]
Lloh4:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_6
; %bb.2:
Lloh5:
	adrp	x8, _DMA0_REGISTER_OFFSET@GOTPAGE
Lloh6:
	ldr	x8, [x8, _DMA0_REGISTER_OFFSET@GOTPAGEOFF]
Lloh7:
	ldr	w19, [x8]
Lloh8:
	adrp	x22, _DMA_POWER_CNTL@GOTPAGE
Lloh9:
	ldr	x22, [x22, _DMA_POWER_CNTL@GOTPAGEOFF]
	ldr	w8, [x22]
	add	w0, w8, w19
	bl	_RREG32
Lloh10:
	adrp	x23, _MEM_POWER_OVERRIDE@GOTPAGE
Lloh11:
	ldr	x23, [x23, _MEM_POWER_OVERRIDE@GOTPAGEOFF]
	ldr	w8, [x23]
	bic	w1, w0, w8
	cmp	w1, w0
	b.eq	LBB0_4
; %bb.3:
	ldr	w8, [x22]
	add	w0, w8, w19
	bl	_WREG32
LBB0_4:
	ldr	w8, [x20]
	add	w0, w8, w19
	mov	w19, #256
	mov	w1, #256
	bl	_WREG32
Lloh12:
	adrp	x8, _DMA1_REGISTER_OFFSET@GOTPAGE
Lloh13:
	ldr	x8, [x8, _DMA1_REGISTER_OFFSET@GOTPAGEOFF]
Lloh14:
	ldr	w21, [x8]
	ldr	w8, [x22]
	add	w0, w8, w21
	bl	_RREG32
	ldr	w8, [x23]
	bic	w1, w0, w8
	cmp	w1, w0
	b.eq	LBB0_14
; %bb.5:
	ldr	w8, [x22]
	add	w0, w8, w21
	bl	_WREG32
	mov	w19, #256
	b	LBB0_14
LBB0_6:
Lloh15:
	adrp	x8, _DMA0_REGISTER_OFFSET@GOTPAGE
Lloh16:
	ldr	x8, [x8, _DMA0_REGISTER_OFFSET@GOTPAGEOFF]
Lloh17:
	ldr	w21, [x8]
Lloh18:
	adrp	x19, _DMA_POWER_CNTL@GOTPAGE
Lloh19:
	ldr	x19, [x19, _DMA_POWER_CNTL@GOTPAGEOFF]
	ldr	w8, [x19]
	add	w0, w8, w21
	bl	_RREG32
Lloh20:
	adrp	x22, _MEM_POWER_OVERRIDE@GOTPAGE
Lloh21:
	ldr	x22, [x22, _MEM_POWER_OVERRIDE@GOTPAGEOFF]
	ldr	w8, [x22]
	orr	w1, w8, w0
	cmp	w1, w0
	b.eq	LBB0_8
; %bb.7:
	ldr	w8, [x19]
	add	w0, w8, w21
	bl	_WREG32
LBB0_8:
	ldr	w8, [x20]
	add	w0, w8, w21
	bl	_RREG32
	mov	w8, #-16777216
	cmp	w0, w8
	b.eq	LBB0_10
; %bb.9:
	ldr	w8, [x20]
	add	w0, w8, w21
	mov	w1, #-16777216
	bl	_WREG32
LBB0_10:
Lloh22:
	adrp	x8, _DMA1_REGISTER_OFFSET@GOTPAGE
Lloh23:
	ldr	x8, [x8, _DMA1_REGISTER_OFFSET@GOTPAGEOFF]
Lloh24:
	ldr	w21, [x8]
	ldr	w8, [x19]
	add	w0, w8, w21
	bl	_RREG32
	ldr	w8, [x22]
	orr	w1, w8, w0
	cmp	w1, w0
	b.eq	LBB0_12
; %bb.11:
	ldr	w8, [x19]
	add	w0, w8, w21
	bl	_WREG32
LBB0_12:
	ldr	w8, [x20]
	add	w0, w8, w21
	bl	_RREG32
	mov	w19, #-16777216
	cmp	w0, w19
	b.ne	LBB0_14
; %bb.13:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_14:
	ldr	w8, [x20]
	add	w0, w8, w21
	mov	x1, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_WREG32
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_CG_SUPPORT_SDMA_MGCG,4,2 ; @RADEON_CG_SUPPORT_SDMA_MGCG
	.comm	_DMA0_REGISTER_OFFSET,4,2       ; @DMA0_REGISTER_OFFSET
	.comm	_DMA1_REGISTER_OFFSET,4,2       ; @DMA1_REGISTER_OFFSET
	.comm	_DMA_POWER_CNTL,4,2             ; @DMA_POWER_CNTL
	.comm	_MEM_POWER_OVERRIDE,4,2         ; @MEM_POWER_OVERRIDE
	.comm	_DMA_CLK_CTRL,4,2               ; @DMA_CLK_CTRL
	.no_dead_strip	_si_enable_dma_mgcg
.subsections_via_symbols
