	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rv7xx_parse_pplib_clock_info
_rv7xx_parse_pplib_clock_info:          ## @rv7xx_parse_pplib_clock_info
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$72, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rcx, %r12
	movl	%edx, %r13d
	movq	%rsi, %r14
	movq	%rdi, %rbx
	callq	_rv770_get_pi
	movq	%rax, -72(%rbp)                 ## 8-byte Spill
	movq	%rbx, -48(%rbp)                 ## 8-byte Spill
	movq	%rbx, %rdi
	callq	_evergreen_get_pi
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
	movq	%r14, -80(%rbp)                 ## 8-byte Spill
	movq	%r14, %rdi
	callq	_rv770_get_ps
	movq	%rax, %r14
	cmpl	$1, %r13d
	movq	%rax, -64(%rbp)                 ## 8-byte Spill
	je	LBB0_26
## %bb.1:
	testl	%r13d, %r13d
	je	LBB0_3
## %bb.2:
	addq	$24, %r14
	jmp	LBB0_3
LBB0_26:
	addq	$48, %r14
LBB0_3:
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	movq	(%rbx), %rax
	movq	_CHIP_CEDAR@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_4
## %bb.5:
	movl	20(%r12), %edi
	callq	_le16_to_cpu
	movl	(%r12), %r13d
	movl	16(%r12), %edi
	shll	$16, %r13d
	orl	%eax, %r13d
	callq	_le16_to_cpu
	movl	4(%r12), %r15d
	movl	12(%r12), %edi
	shll	$16, %r15d
	orl	%eax, %r15d
	callq	_le16_to_cpu
	movl	%eax, (%r14)
	jmp	LBB0_6
LBB0_4:
	movl	24(%r12), %edi
	callq	_le16_to_cpu
	movl	(%r12), %r13d
	movl	20(%r12), %edi
	shll	$16, %r13d
	orl	%eax, %r13d
	callq	_le16_to_cpu
	movl	4(%r12), %r15d
	movl	16(%r12), %edi
	shll	$16, %r15d
	orl	%eax, %r15d
	callq	_le16_to_cpu
	movl	%eax, (%r14)
	movl	12(%r12), %edi
	callq	_le16_to_cpu
	movq	%rax, 16(%r14)
LBB0_6:
	movl	8(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, 4(%r14)
	movl	%r15d, 8(%r14)
	movl	%r13d, 12(%r14)
	movl	(%r14), %ecx
	cmpl	$65281, %ecx                    ## imm = 0xFF01
	movq	-80(%rbp), %r12                 ## 8-byte Reload
	movq	-72(%rbp), %rdi                 ## 8-byte Reload
	jne	LBB0_10
## %bb.7:
	movl	(%rdi), %ecx
	testl	%ecx, %ecx
	je	LBB0_8
## %bb.9:
	movl	%ecx, (%r14)
	jmp	LBB0_10
LBB0_8:
	movl	$65281, %ecx                    ## imm = 0xFF01
LBB0_10:
	movl	(%r12), %eax
	movq	_ATOM_PPLIB_CLASSIFICATION_ACPI@GOTPCREL(%rip), %rdx
	testl	%eax, (%rdx)
	je	LBB0_14
## %bb.11:
	movl	%ecx, 4(%rdi)
	movq	(%rbx), %rdx
	movq	_CHIP_CEDAR@GOTPCREL(%rip), %rsi
	cmpq	(%rsi), %rdx
	jl	LBB0_13
## %bb.12:
	movq	16(%r14), %rdx
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
	movq	%rdx, 16(%rsi)
LBB0_13:
	movq	_ATOM_PPLIB_R600_FLAGS_PCIEGEN2@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	xorl	%esi, %esi
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	andl	4(%rbx), %edx
	setne	%sil
	movl	%esi, 8(%rdi)
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
LBB0_14:
	movq	_ATOM_PPLIB_CLASSIFICATION2_ULV@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	testl	%edx, 4(%r12)
	je	LBB0_17
## %bb.15:
	movq	(%rbx), %rdx
	movq	_CHIP_BARTS@GOTPCREL(%rip), %rsi
	cmpq	(%rsi), %rdx
	jl	LBB0_17
## %bb.16:
	movq	-56(%rbp), %rdx                 ## 8-byte Reload
	movl	$1, (%rdx)
	movq	%r14, 8(%rdx)
LBB0_17:
	cmpl	%ecx, 12(%rdi)
	jle	LBB0_19
## %bb.18:
	movl	%ecx, 12(%rdi)
LBB0_19:
	cmpl	%ecx, 16(%rdi)
	jge	LBB0_21
## %bb.20:
	movl	%ecx, 16(%rdi)
LBB0_21:
	movq	_ATOM_PPLIB_CLASSIFICATION_BOOT@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_23
## %bb.22:
	leaq	-96(%rbp), %rsi
	leaq	-88(%rbp), %rdx
	leaq	-104(%rbp), %rcx
	movq	%rbx, %rdi
	callq	_radeon_atombios_get_default_voltages
	movl	32(%rbx), %r15d
	movl	%r15d, 8(%r14)
	movl	36(%rbx), %r13d
	movl	%r13d, 12(%r14)
	movl	-96(%rbp), %eax
	movl	%eax, (%r14)
	movq	-88(%rbp), %rax
	movq	%rax, 16(%r14)
	movl	(%r12), %eax
LBB0_23:
	movq	_ATOM_PPLIB_CLASSIFICATION_UI_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_25
## %bb.24:
	movl	%r13d, 8(%rbx)
	movl	%r15d, 12(%rbx)
	movl	(%r14), %eax
	movl	%eax, 16(%rbx)
	movq	16(%r14), %rax
	movq	%rax, 24(%rbx)
LBB0_25:
	addq	$72, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CHIP_CEDAR,8,3                 ## @CHIP_CEDAR
	.comm	_ATOM_PPLIB_CLASSIFICATION_ACPI,4,2 ## @ATOM_PPLIB_CLASSIFICATION_ACPI
	.comm	_ATOM_PPLIB_R600_FLAGS_PCIEGEN2,4,2 ## @ATOM_PPLIB_R600_FLAGS_PCIEGEN2
	.comm	_ATOM_PPLIB_CLASSIFICATION2_ULV,4,2 ## @ATOM_PPLIB_CLASSIFICATION2_ULV
	.comm	_CHIP_BARTS,8,3                 ## @CHIP_BARTS
	.comm	_ATOM_PPLIB_CLASSIFICATION_BOOT,4,2 ## @ATOM_PPLIB_CLASSIFICATION_BOOT
	.comm	_ATOM_PPLIB_CLASSIFICATION_UI_MASK,4,2 ## @ATOM_PPLIB_CLASSIFICATION_UI_MASK
	.comm	_ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE,4,2 ## @ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
	.no_dead_strip	_rv7xx_parse_pplib_clock_info
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rv7xx_parse_pplib_clock_info
_rv7xx_parse_pplib_clock_info:          ; @rv7xx_parse_pplib_clock_info
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #128
	.cfi_def_cfa_offset 128
	stp	x28, x27, [sp, #32]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #48]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #64]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #80]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #96]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #112]            ; 16-byte Folded Spill
	add	x29, sp, #112
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x24, x3
	mov	x25, x2
	mov	x20, x1
	mov	x19, x0
	bl	_rv770_get_pi
	mov	x21, x0
	mov	x0, x19
	bl	_evergreen_get_pi
	mov	x22, x0
	mov	x0, x20
	bl	_rv770_get_ps
	mov	x23, x0
	cmp	w25, #1
	b.eq	LBB0_3
; %bb.1:
	cbnz	w25, LBB0_4
; %bb.2:
	mov	x25, x23
	b	LBB0_5
LBB0_3:
	add	x25, x23, #48
	b	LBB0_5
LBB0_4:
	add	x25, x23, #24
LBB0_5:
	ldr	x8, [x19]
Lloh0:
	adrp	x28, _CHIP_CEDAR@GOTPAGE
Lloh1:
	ldr	x28, [x28, _CHIP_CEDAR@GOTPAGEOFF]
	ldr	x9, [x28]
	cmp	x8, x9
	b.ge	LBB0_7
; %bb.6:
	ldr	w0, [x24, #20]
	bl	_le16_to_cpu
	ldr	w8, [x24]
	orr	w26, w0, w8, lsl #16
	ldr	w0, [x24, #16]
	bl	_le16_to_cpu
	ldr	w8, [x24, #4]
	orr	w27, w0, w8, lsl #16
	ldr	w0, [x24, #12]
	bl	_le16_to_cpu
	str	w0, [x25]
	b	LBB0_8
LBB0_7:
	ldr	w0, [x24, #24]
	bl	_le16_to_cpu
	ldr	w8, [x24]
	orr	w26, w0, w8, lsl #16
	ldr	w0, [x24, #20]
	bl	_le16_to_cpu
	ldr	w8, [x24, #4]
	orr	w27, w0, w8, lsl #16
	ldr	w0, [x24, #16]
	bl	_le16_to_cpu
	str	w0, [x25]
	ldr	w0, [x24, #12]
	bl	_le16_to_cpu
	str	x0, [x25, #16]
LBB0_8:
	ldr	w0, [x24, #8]
	bl	_le32_to_cpu
	stp	w0, w27, [x25, #4]
	str	w26, [x25, #12]
	ldr	w9, [x25]
	mov	w8, #65281
	cmp	w9, w8
	b.ne	LBB0_12
; %bb.9:
	ldr	w9, [x21]
	cbz	w9, LBB0_11
; %bb.10:
	str	w9, [x25]
	b	LBB0_12
LBB0_11:
	mov	w9, #65281
LBB0_12:
	ldr	w8, [x20]
Lloh2:
	adrp	x10, _ATOM_PPLIB_CLASSIFICATION_ACPI@GOTPAGE
Lloh3:
	ldr	x10, [x10, _ATOM_PPLIB_CLASSIFICATION_ACPI@GOTPAGEOFF]
Lloh4:
	ldr	w10, [x10]
	tst	w10, w8
	b.eq	LBB0_16
; %bb.13:
	str	w9, [x21, #4]
	ldr	x10, [x19]
	ldr	x11, [x28]
	cmp	x10, x11
	b.lt	LBB0_15
; %bb.14:
	ldr	x10, [x25, #16]
	str	x10, [x22, #16]
LBB0_15:
	ldr	w10, [x23, #4]
Lloh5:
	adrp	x11, _ATOM_PPLIB_R600_FLAGS_PCIEGEN2@GOTPAGE
Lloh6:
	ldr	x11, [x11, _ATOM_PPLIB_R600_FLAGS_PCIEGEN2@GOTPAGEOFF]
Lloh7:
	ldr	w11, [x11]
	tst	w11, w10
	cset	w10, ne
	str	w10, [x21, #8]
LBB0_16:
	ldr	w10, [x20, #4]
Lloh8:
	adrp	x11, _ATOM_PPLIB_CLASSIFICATION2_ULV@GOTPAGE
Lloh9:
	ldr	x11, [x11, _ATOM_PPLIB_CLASSIFICATION2_ULV@GOTPAGEOFF]
Lloh10:
	ldr	w11, [x11]
	tst	w11, w10
	b.eq	LBB0_19
; %bb.17:
	ldr	x10, [x19]
Lloh11:
	adrp	x11, _CHIP_BARTS@GOTPAGE
Lloh12:
	ldr	x11, [x11, _CHIP_BARTS@GOTPAGEOFF]
Lloh13:
	ldr	x11, [x11]
	cmp	x10, x11
	b.lt	LBB0_19
; %bb.18:
	mov	w10, #1
	str	w10, [x22]
	str	x25, [x22, #8]
LBB0_19:
	ldr	w10, [x21, #12]
	cmp	w10, w9
	b.le	LBB0_21
; %bb.20:
	str	w9, [x21, #12]
LBB0_21:
	ldr	w10, [x21, #16]
	cmp	w10, w9
	b.ge	LBB0_23
; %bb.22:
	str	w9, [x21, #16]
LBB0_23:
Lloh14:
	adrp	x9, _ATOM_PPLIB_CLASSIFICATION_BOOT@GOTPAGE
Lloh15:
	ldr	x9, [x9, _ATOM_PPLIB_CLASSIFICATION_BOOT@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_25
; %bb.24:
	add	x1, sp, #24
	add	x2, sp, #16
	add	x3, sp, #8
	mov	x0, x19
	bl	_radeon_atombios_get_default_voltages
	ldr	w27, [x19, #32]
	str	w27, [x25, #8]
	ldr	w26, [x19, #36]
	str	w26, [x25, #12]
	ldr	x8, [sp, #24]
	str	w8, [x25]
	ldr	x8, [sp, #16]
	str	x8, [x25, #16]
	ldr	w8, [x20]
LBB0_25:
Lloh17:
	adrp	x9, _ATOM_PPLIB_CLASSIFICATION_UI_MASK@GOTPAGE
Lloh18:
	ldr	x9, [x9, _ATOM_PPLIB_CLASSIFICATION_UI_MASK@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	and	w8, w9, w8
Lloh20:
	adrp	x9, _ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE@GOTPAGE
Lloh21:
	ldr	x9, [x9, _ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_27
; %bb.26:
	stp	w26, w27, [x19, #8]
	ldr	w8, [x25]
	str	w8, [x19, #16]
	ldr	x8, [x25, #16]
	str	x8, [x19, #24]
LBB0_27:
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.cfi_endproc
                                        ; -- End function
	.comm	_CHIP_CEDAR,8,3                 ; @CHIP_CEDAR
	.comm	_ATOM_PPLIB_CLASSIFICATION_ACPI,4,2 ; @ATOM_PPLIB_CLASSIFICATION_ACPI
	.comm	_ATOM_PPLIB_R600_FLAGS_PCIEGEN2,4,2 ; @ATOM_PPLIB_R600_FLAGS_PCIEGEN2
	.comm	_ATOM_PPLIB_CLASSIFICATION2_ULV,4,2 ; @ATOM_PPLIB_CLASSIFICATION2_ULV
	.comm	_CHIP_BARTS,8,3                 ; @CHIP_BARTS
	.comm	_ATOM_PPLIB_CLASSIFICATION_BOOT,4,2 ; @ATOM_PPLIB_CLASSIFICATION_BOOT
	.comm	_ATOM_PPLIB_CLASSIFICATION_UI_MASK,4,2 ; @ATOM_PPLIB_CLASSIFICATION_UI_MASK
	.comm	_ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE,4,2 ; @ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
	.no_dead_strip	_rv7xx_parse_pplib_clock_info
.subsections_via_symbols
