	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_vm_bo_map               ## -- Begin function amdgpu_vm_bo_map
	.p2align	4, 0x90
_amdgpu_vm_bo_map:                      ## @amdgpu_vm_bo_map
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_AMDGPU_GPU_PAGE_MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	testq	%rdx, %rax
	je	LBB0_1
LBB0_4:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
LBB0_5:
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_20:
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_1:
	movq	%r8, %r14
	testq	%r8, %r8
	je	LBB0_4
## %bb.2:
	movq	%rcx, %rbx
	movq	%rax, %rcx
	andq	%rbx, %rcx
	jne	LBB0_4
## %bb.3:
	andq	%r14, %rax
	jne	LBB0_4
## %bb.6:
	movq	%rdx, %r13
	leaq	(%rdx,%r14), %rcx
	decq	%rcx
	cmpq	%rdx, %rcx
	jle	LBB0_4
## %bb.7:
	movq	%rsi, %r12
	movq	%rdi, %r15
	movq	(%rsi), %rdi
	movq	8(%rsi), %rsi
	testq	%rsi, %rsi
	movq	%r9, -56(%rbp)                  ## 8-byte Spill
	movq	%rsi, -48(%rbp)                 ## 8-byte Spill
	je	LBB0_9
## %bb.8:
	addq	%rbx, %r14
	movq	%rdi, -72(%rbp)                 ## 8-byte Spill
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movq	%rcx, -64(%rbp)                 ## 8-byte Spill
	callq	_amdgpu_bo_size
	movq	-64(%rbp), %rcx                 ## 8-byte Reload
	movq	-72(%rbp), %rdi                 ## 8-byte Reload
	cmpq	%rax, %r14
	jg	LBB0_4
LBB0_9:
	movq	_AMDGPU_GPU_PAGE_SIZE@GOTPCREL(%rip), %rax
	movq	(%rax), %r10
	movq	%r13, %rax
	orq	%r10, %rax
	shrq	$32, %rax
	je	LBB0_10
## %bb.11:
	movq	%r13, %rax
	cqto
	idivq	%r10
	movq	%rax, %r14
	jmp	LBB0_12
LBB0_10:
	movl	%r13d, %eax
	xorl	%edx, %edx
	divl	%r10d
	movl	%eax, %r14d
LBB0_12:
	movq	%rcx, %rax
	orq	%r10, %rax
	shrq	$32, %rax
	je	LBB0_13
## %bb.14:
	movq	%rcx, %rax
	cqto
	idivq	%r10
	movq	%rax, %r13
	jmp	LBB0_15
LBB0_13:
	movl	%ecx, %eax
	xorl	%edx, %edx
	divl	%r10d
	movl	%eax, %r13d
LBB0_15:
	movq	%r14, %rsi
	movq	%r13, %rdx
	callq	_amdgpu_vm_it_iter_first
	testq	%rax, %rax
	je	LBB0_17
## %bb.16:
	movl	(%r15), %edi
	movq	16(%rax), %rcx
	movq	24(%rax), %r9
	incq	%rcx
	movq	%rcx, (%rsp)
	leaq	L_.str(%rip), %rsi
	movq	-48(%rbp), %rdx                 ## 8-byte Reload
	movq	%r14, %rcx
	movq	%r13, %r8
	callq	_dev_err
	jmp	LBB0_4
LBB0_17:
	movq	_GFP_KERNEL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$32, %edi
	callq	_kmalloc
	testq	%rax, %rax
	je	LBB0_18
## %bb.19:
	movq	%r14, 24(%rax)
	movq	%r13, 16(%rax)
	movq	%rbx, 8(%rax)
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	movq	%rcx, (%rax)
	movq	%r15, %rdi
	movq	%r12, %rsi
	movq	%rax, %rdx
	callq	_amdgpu_vm_bo_insert_map
	xorl	%eax, %eax
	jmp	LBB0_20
LBB0_18:
	movq	_ENOMEM@GOTPCREL(%rip), %rcx
	jmp	LBB0_5
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_GPU_PAGE_MASK,8,3       ## @AMDGPU_GPU_PAGE_MASK
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_AMDGPU_GPU_PAGE_SIZE,8,3       ## @AMDGPU_GPU_PAGE_SIZE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"bo %p va 0x%010Lx-0x%010Lx conflict with 0x%010Lx-0x%010Lx\n"

	.comm	_GFP_KERNEL,4,2                 ## @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ## @ENOMEM
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_vm_bo_map               ; -- Begin function amdgpu_vm_bo_map
	.p2align	2
_amdgpu_vm_bo_map:                      ; @amdgpu_vm_bo_map
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
Lloh0:
	adrp	x8, _AMDGPU_GPU_PAGE_MASK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPU_GPU_PAGE_MASK@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	and	x9, x8, x2
	cmp	x9, #0
	and	x9, x8, x3
	and	x8, x8, x4
	ccmp	x4, #0, #4, eq
	ccmp	x9, #0, #0, ne
	ccmp	x8, #0, #0, eq
	b.eq	LBB0_4
LBB0_1:
Lloh3:
	adrp	x8, _EINVAL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
LBB0_2:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_3:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
LBB0_4:
	mov	x24, x2
	add	x8, x2, x4
	sub	x25, x8, #1
	cmp	x25, x2
	b.le	LBB0_1
; %bb.5:
	mov	x19, x5
	mov	x22, x3
	mov	x21, x1
	mov	x20, x0
	ldp	x26, x23, [x1]
	cbz	x23, LBB0_7
; %bb.6:
	add	x27, x4, x22
	mov	x0, x23
	bl	_amdgpu_bo_size
	cmp	x27, x0
	b.gt	LBB0_1
LBB0_7:
Lloh5:
	adrp	x8, _AMDGPU_GPU_PAGE_SIZE@GOTPAGE
Lloh6:
	ldr	x8, [x8, _AMDGPU_GPU_PAGE_SIZE@GOTPAGEOFF]
Lloh7:
	ldr	x8, [x8]
	sdiv	x24, x24, x8
	sdiv	x25, x25, x8
	mov	x0, x26
	mov	x1, x24
	mov	x2, x25
	bl	_amdgpu_vm_it_iter_first
	cbz	x0, LBB0_9
; %bb.8:
	ldr	w8, [x20]
	ldp	x9, x5, [x0, #16]
	add	x6, x9, #1
Lloh8:
	adrp	x1, l_.str@PAGE
Lloh9:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x8
	mov	x2, x23
	mov	x3, x24
	mov	x4, x25
	bl	_dev_err
	b	LBB0_1
LBB0_9:
Lloh10:
	adrp	x8, _GFP_KERNEL@GOTPAGE
Lloh11:
	ldr	x8, [x8, _GFP_KERNEL@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
	mov	w0, #32
	bl	_kmalloc
	cbz	x0, LBB0_11
; %bb.10:
	mov	x2, x0
	stp	x25, x24, [x0, #16]
	stp	x19, x22, [x0]
	mov	x0, x20
	mov	x1, x21
	bl	_amdgpu_vm_bo_insert_map
	mov	w0, #0
	b	LBB0_3
LBB0_11:
Lloh13:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh14:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
	b	LBB0_2
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh13, Lloh14
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_GPU_PAGE_MASK,8,3       ; @AMDGPU_GPU_PAGE_MASK
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_AMDGPU_GPU_PAGE_SIZE,8,3       ; @AMDGPU_GPU_PAGE_SIZE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"bo %p va 0x%010Lx-0x%010Lx conflict with 0x%010Lx-0x%010Lx\n"

	.comm	_GFP_KERNEL,4,2                 ; @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ; @ENOMEM
.subsections_via_symbols
