	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_vcn_v2_0_jpeg_ring_emit_ib     ## -- Begin function vcn_v2_0_jpeg_ring_emit_ib
	.p2align	4, 0x90
_vcn_v2_0_jpeg_ring_emit_ib:            ## @vcn_v2_0_jpeg_ring_emit_ib
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r14
	movq	%rdi, %r12
	movq	%rsi, %rdi
	callq	_AMDGPU_JOB_GET_VMID
	movl	%eax, %r15d
	movq	_mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_PACKETJ_TYPE0@GOTPCREL(%rip), %r13
	movl	(%r13), %ecx
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	%r15d, %ebx
	shll	$4, %ebx
	orl	%r15d, %ebx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_amdgpu_ring_write
	movq	_mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r13), %ecx
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_amdgpu_ring_write
	movq	_mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r13), %ecx
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	4(%r14), %edi
	callq	_lower_32_bits
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r13), %ecx
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	4(%r14), %edi
	callq	_upper_32_bits
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r13), %ecx
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	(%r14), %esi
	movq	%r12, %rdi
	callq	_amdgpu_ring_write
	movq	_mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r13), %ecx
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	(%r12), %edi
	callq	_lower_32_bits
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r13), %ecx
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	(%r12), %edi
	callq	_upper_32_bits
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_PACKETJ_CONDITION_CHECK0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_PACKETJ_TYPE2@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%edi, %edi
	xorl	%esi, %esi
	callq	_PACKETJ
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
	movq	_mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r13), %ecx
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r12, %rdi
	movl	$20972032, %esi                 ## imm = 0x1400200
	callq	_amdgpu_ring_write
	movq	_mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r13), %ecx
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r12, %rdi
	movl	$2, %esi
	callq	_amdgpu_ring_write
	movq	_mmUVD_JRBC_STATUS_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_PACKETJ_CONDITION_CHECK3@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_PACKETJ_TYPE3@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%esi, %esi
	callq	_PACKETJ
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r12, %rdi
	movl	$2, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_write              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,4,2 ## @mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET
	.comm	_PACKETJ_TYPE0,4,2              ## @PACKETJ_TYPE0
	.comm	_mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,4,2 ## @mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET
	.comm	_mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,4,2 ## @mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET
	.comm	_mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,4,2 ## @mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET
	.comm	_mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,4,2 ## @mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET
	.comm	_mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,4,2 ## @mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET
	.comm	_mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,4,2 ## @mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET
	.comm	_PACKETJ_CONDITION_CHECK0,4,2   ## @PACKETJ_CONDITION_CHECK0
	.comm	_PACKETJ_TYPE2,4,2              ## @PACKETJ_TYPE2
	.comm	_mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,4,2 ## @mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET
	.comm	_mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,4,2 ## @mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET
	.comm	_mmUVD_JRBC_STATUS_INTERNAL_OFFSET,4,2 ## @mmUVD_JRBC_STATUS_INTERNAL_OFFSET
	.comm	_PACKETJ_CONDITION_CHECK3,4,2   ## @PACKETJ_CONDITION_CHECK3
	.comm	_PACKETJ_TYPE3,4,2              ## @PACKETJ_TYPE3
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_vcn_v2_0_jpeg_ring_emit_ib     ; -- Begin function vcn_v2_0_jpeg_ring_emit_ib
	.p2align	2
_vcn_v2_0_jpeg_ring_emit_ib:            ; @vcn_v2_0_jpeg_ring_emit_ib
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x2
	mov	x19, x0
	mov	x0, x1
	bl	_AMDGPU_JOB_GET_VMID
	mov	x21, x0
Lloh0:
	adrp	x8, _mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET@GOTPAGE
Lloh1:
	ldr	x8, [x8, _mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
Lloh3:
	adrp	x22, _PACKETJ_TYPE0@GOTPAGE
Lloh4:
	ldr	x22, [x22, _PACKETJ_TYPE0@GOTPAGEOFF]
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	orr	w21, w21, w21, lsl #4
	mov	x0, x19
	mov	x1, x21
	bl	_amdgpu_ring_write
Lloh5:
	adrp	x8, _mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET@GOTPAGE
Lloh6:
	ldr	x8, [x8, _mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	x1, x21
	bl	_amdgpu_ring_write
Lloh8:
	adrp	x8, _mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET@GOTPAGE
Lloh9:
	ldr	x8, [x8, _mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh10:
	ldr	w0, [x8]
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x20, #4]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh11:
	adrp	x8, _mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET@GOTPAGE
Lloh12:
	ldr	x8, [x8, _mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x20, #4]
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh14:
	adrp	x8, _mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET@GOTPAGE
Lloh15:
	ldr	x8, [x8, _mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w1, [x20]
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh17:
	adrp	x8, _mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET@GOTPAGE
Lloh18:
	ldr	x8, [x8, _mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh19:
	ldr	w0, [x8]
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x19]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh20:
	adrp	x8, _mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET@GOTPAGE
Lloh21:
	ldr	x8, [x8, _mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh22:
	ldr	w0, [x8]
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x19]
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh23:
	adrp	x8, _PACKETJ_CONDITION_CHECK0@GOTPAGE
Lloh24:
	ldr	x8, [x8, _PACKETJ_CONDITION_CHECK0@GOTPAGEOFF]
Lloh25:
	ldr	w2, [x8]
Lloh26:
	adrp	x8, _PACKETJ_TYPE2@GOTPAGE
Lloh27:
	ldr	x8, [x8, _PACKETJ_TYPE2@GOTPAGEOFF]
Lloh28:
	ldr	w3, [x8]
	mov	w0, #0
	mov	w1, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_ring_write
Lloh29:
	adrp	x8, _mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET@GOTPAGE
Lloh30:
	ldr	x8, [x8, _mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh31:
	ldr	w0, [x8]
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #512
	movk	w1, #320, lsl #16
	bl	_amdgpu_ring_write
Lloh32:
	adrp	x8, _mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET@GOTPAGE
Lloh33:
	ldr	x8, [x8, _mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh34:
	ldr	w0, [x8]
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #2
	bl	_amdgpu_ring_write
Lloh35:
	adrp	x8, _mmUVD_JRBC_STATUS_INTERNAL_OFFSET@GOTPAGE
Lloh36:
	ldr	x8, [x8, _mmUVD_JRBC_STATUS_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh37:
	ldr	w0, [x8]
Lloh38:
	adrp	x8, _PACKETJ_CONDITION_CHECK3@GOTPAGE
Lloh39:
	ldr	x8, [x8, _PACKETJ_CONDITION_CHECK3@GOTPAGEOFF]
Lloh40:
	ldr	w2, [x8]
Lloh41:
	adrp	x8, _PACKETJ_TYPE3@GOTPAGE
Lloh42:
	ldr	x8, [x8, _PACKETJ_TYPE3@GOTPAGEOFF]
Lloh43:
	ldr	w3, [x8]
	mov	w1, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #2
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_amdgpu_ring_write
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,4,2 ; @mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET
	.comm	_PACKETJ_TYPE0,4,2              ; @PACKETJ_TYPE0
	.comm	_mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,4,2 ; @mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET
	.comm	_mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,4,2 ; @mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET
	.comm	_mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,4,2 ; @mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET
	.comm	_mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,4,2 ; @mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET
	.comm	_mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,4,2 ; @mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET
	.comm	_mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,4,2 ; @mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET
	.comm	_PACKETJ_CONDITION_CHECK0,4,2   ; @PACKETJ_CONDITION_CHECK0
	.comm	_PACKETJ_TYPE2,4,2              ; @PACKETJ_TYPE2
	.comm	_mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,4,2 ; @mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET
	.comm	_mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,4,2 ; @mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET
	.comm	_mmUVD_JRBC_STATUS_INTERNAL_OFFSET,4,2 ; @mmUVD_JRBC_STATUS_INTERNAL_OFFSET
	.comm	_PACKETJ_CONDITION_CHECK3,4,2   ; @PACKETJ_CONDITION_CHECK3
	.comm	_PACKETJ_TYPE3,4,2              ; @PACKETJ_TYPE3
.subsections_via_symbols
