	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_meson_crtc_irq                 ## -- Begin function meson_crtc_irq
	.p2align	4, 0x90
_meson_crtc_irq:                        ## @meson_crtc_irq
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movl	8(%rdi), %edi
	callq	_to_meson_crtc
	movq	%rax, %r14
	cmpq	$0, 280(%r15)
	je	LBB0_5
## %bb.1:
	cmpl	$0, 16(%r15)
	je	LBB0_5
## %bb.2:
	movl	20(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VIU_OSD1_CTRL_STAT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	24(%r15), %rax
	movq	288(%r15), %rbx
	movl	(%rax), %r12d
	movq	_VIU_OSD1_BLK0_CFG_W0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	24(%r15), %rax
	movq	288(%r15), %rbx
	movl	4(%rax), %r12d
	movq	_VIU_OSD1_BLK0_CFG_W1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	24(%r15), %rax
	movq	288(%r15), %rbx
	movl	8(%rax), %r12d
	movq	_VIU_OSD1_BLK0_CFG_W2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	24(%r15), %rax
	movq	288(%r15), %rbx
	movl	12(%rax), %r12d
	movq	_VIU_OSD1_BLK0_CFG_W3@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	24(%r15), %rax
	movq	288(%r15), %rbx
	movl	16(%rax), %r12d
	movq	_VIU_OSD1_BLK0_CFG_W4@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	32(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_OSD_SC_CTRL0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	36(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_OSD_SCI_WH_M1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	40(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_OSD_SCO_H_START_END@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	44(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_OSD_SCO_V_START_END@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	48(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_OSD_VSC_INI_PHASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	52(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_OSD_VSC_PHASE_STEP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	56(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_OSD_HSC_INI_PHASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	60(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_OSD_HSC_PHASE_STEP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	64(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_OSD_HSC_CTRL0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	68(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_OSD_VSC_CTRL0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	300(%r15), %edi
	movl	312(%r15), %esi
	movl	272(%r15), %edx
	movl	264(%r15), %r8d
	movl	268(%r15), %ecx
	movq	_MESON_CANVAS_WRAP_NONE@GOTPCREL(%rip), %rax
	movl	(%rax), %r9d
	movq	_MESON_CANVAS_BLKMODE_LINEAR@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	pushq	$0
	pushq	%rax
	callq	_meson_canvas_config
	addq	$16, %rsp
	movq	24(%r14), %rax
	testq	%rax, %rax
	je	LBB0_4
## %bb.3:
	movq	%r15, %rdi
	callq	*%rax
LBB0_4:
	movl	$0, 16(%r15)
LBB0_5:
	cmpq	$0, 256(%r15)
	je	LBB0_16
## %bb.6:
	cmpl	$0, 72(%r15)
	je	LBB0_16
## %bb.7:
	movl	76(%r15), %eax
	cmpl	$1, %eax
	je	LBB0_12
## %bb.8:
	cmpl	$2, %eax
	je	LBB0_11
## %bb.9:
	cmpl	$3, %eax
	jne	LBB0_13
## %bb.10:
	movl	300(%r15), %edi
	movl	308(%r15), %esi
	movl	252(%r15), %edx
	movl	244(%r15), %r8d
	movl	248(%r15), %ecx
	movq	_MESON_CANVAS_WRAP_NONE@GOTPCREL(%rip), %rax
	movl	(%rax), %r9d
	movq	_MESON_CANVAS_BLKMODE_LINEAR@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_MESON_CANVAS_ENDIAN_SWAP64@GOTPCREL(%rip), %rbx
	movl	(%rbx), %ebx
	pushq	%rbx
	pushq	%rax
	callq	_meson_canvas_config
	addq	$16, %rsp
LBB0_11:
	movl	300(%r15), %edi
	movl	304(%r15), %esi
	movl	240(%r15), %edx
	movl	232(%r15), %r8d
	movl	236(%r15), %ecx
	movq	_MESON_CANVAS_WRAP_NONE@GOTPCREL(%rip), %rax
	movl	(%rax), %r9d
	movq	_MESON_CANVAS_BLKMODE_LINEAR@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_MESON_CANVAS_ENDIAN_SWAP64@GOTPCREL(%rip), %rbx
	movl	(%rbx), %ebx
	pushq	%rbx
	pushq	%rax
	callq	_meson_canvas_config
	addq	$16, %rsp
LBB0_12:
	movl	300(%r15), %edi
	movl	296(%r15), %esi
	movl	228(%r15), %edx
	movl	220(%r15), %r8d
	movl	224(%r15), %ecx
	movq	_MESON_CANVAS_WRAP_NONE@GOTPCREL(%rip), %rax
	movl	(%rax), %r9d
	movq	_MESON_CANVAS_BLKMODE_LINEAR@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_MESON_CANVAS_ENDIAN_SWAP64@GOTPCREL(%rip), %rbx
	movl	(%rbx), %ebx
	pushq	%rbx
	pushq	%rax
	callq	_meson_canvas_config
	addq	$16, %rsp
LBB0_13:
	movl	80(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_GEN_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	80(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD2_IF0_GEN_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	84(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_GEN_REG2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	88(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VIU_VD1_FMT_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	88(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VIU_VD2_FMT_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	92(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VIU_VD1_FMT_W@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	92(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VIU_VD2_FMT_W@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	96(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_CANVAS0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	96(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_CANVAS1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	96(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD2_IF0_CANVAS0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	96(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD2_IF0_CANVAS1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	100(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_LUMA_X0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	100(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_LUMA_X1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	100(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD2_IF0_LUMA_X0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	100(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD2_IF0_LUMA_X1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	104(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_LUMA_Y0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	104(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_LUMA_Y1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	104(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD2_IF0_LUMA_Y0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	104(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD2_IF0_LUMA_Y1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	108(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_CHROMA_X0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	108(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_CHROMA_X1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	108(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD2_IF0_CHROMA_X0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	108(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD2_IF0_CHROMA_X1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	112(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_CHROMA_Y0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	112(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_CHROMA_Y1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	112(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD2_IF0_CHROMA_Y0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	112(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD2_IF0_CHROMA_Y1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	116(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_RPT_LOOP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	116(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD2_IF0_RPT_LOOP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	120(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_LUMA0_RPT_PAT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	120(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD2_IF0_LUMA0_RPT_PAT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	120(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_LUMA1_RPT_PAT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	120(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD2_IF0_LUMA1_RPT_PAT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	124(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_CHROMA0_RPT_PAT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	124(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD2_IF0_CHROMA0_RPT_PAT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	124(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_CHROMA1_RPT_PAT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	124(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD2_IF0_CHROMA1_RPT_PAT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_LUMA_PSEL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	xorl	%edi, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_CHROMA_PSEL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	xorl	%edi, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD2_IF0_LUMA_PSEL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	xorl	%edi, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD2_IF0_CHROMA_PSEL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	xorl	%edi, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	128(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_RANGE_MAP_Y@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	132(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_RANGE_MAP_CB@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	136(%r15), %r12d
	movq	16(%r14), %rbx
	addq	288(%r15), %rbx
	movq	_VD1_IF0_RANGE_MAP_CR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	$4, %edi
	callq	_VPP_VSC_BANK_LENGTH
	movl	%eax, %ebx
	movl	$4, %edi
	callq	_VPP_HSC_BANK_LENGTH
	orl	%eax, %ebx
	movq	_VPP_SC_VD_EN_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_VPP_SC_TOP_EN_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_VPP_SC_HSC_EN_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_VPP_SC_VSC_EN_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	288(%r15), %r12
	movq	_VPP_SC_MISC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %r12
	movl	%ebx, %edi
	movq	%r12, %rsi
	callq	_writel_relaxed
	movl	140(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_PIC_IN_HEIGHT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	144(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_POSTBLEND_VD1_H_START_END@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	148(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_BLEND_VD2_H_START_END@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	152(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_POSTBLEND_VD1_V_START_END@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	156(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_BLEND_VD2_V_START_END@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	160(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_HSC_REGION12_STARTP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	164(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_HSC_REGION34_STARTP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	168(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_HSC_REGION4_ENDP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	172(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_HSC_START_PHASE_STEP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	176(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_HSC_REGION1_PHASE_SLOPE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	180(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_HSC_REGION3_PHASE_SLOPE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	184(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_LINE_IN_LENGTH@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	188(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_PREBLEND_H_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	192(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_VSC_REGION12_STARTP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	196(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_VSC_REGION34_STARTP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	200(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_VSC_REGION4_ENDP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	204(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_VSC_START_PHASE_STEP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	208(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_VSC_INI_PHASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	212(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_VSC_PHASE_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	216(%r15), %r12d
	movq	288(%r15), %rbx
	movq	_VPP_HSC_PHASE_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	288(%r15), %rbx
	movq	_VPP_SCALE_COEF_IDX@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	$66, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	8(%r14), %rax
	testq	%rax, %rax
	je	LBB0_15
## %bb.14:
	movq	%r15, %rdi
	callq	*%rax
LBB0_15:
	movl	$0, 72(%r15)
LBB0_16:
	movl	8(%r15), %edi
	callq	_drm_crtc_handle_vblank
	movq	(%r15), %rdi
	callq	_spin_lock_irqsave
	movq	(%r14), %rsi
	testq	%rsi, %rsi
	je	LBB0_18
## %bb.17:
	movl	8(%r15), %edi
	callq	_drm_crtc_send_vblank_event
	movl	8(%r15), %edi
	callq	_drm_crtc_vblank_put
	movq	$0, (%r14)
LBB0_18:
	movq	(%r15), %rdi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_spin_unlock_irqrestore         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_VIU_OSD1_CTRL_STAT,4,2         ## @VIU_OSD1_CTRL_STAT
	.comm	_VIU_OSD1_BLK0_CFG_W0,4,2       ## @VIU_OSD1_BLK0_CFG_W0
	.comm	_VIU_OSD1_BLK0_CFG_W1,4,2       ## @VIU_OSD1_BLK0_CFG_W1
	.comm	_VIU_OSD1_BLK0_CFG_W2,4,2       ## @VIU_OSD1_BLK0_CFG_W2
	.comm	_VIU_OSD1_BLK0_CFG_W3,4,2       ## @VIU_OSD1_BLK0_CFG_W3
	.comm	_VIU_OSD1_BLK0_CFG_W4,4,2       ## @VIU_OSD1_BLK0_CFG_W4
	.comm	_VPP_OSD_SC_CTRL0,4,2           ## @VPP_OSD_SC_CTRL0
	.comm	_VPP_OSD_SCI_WH_M1,4,2          ## @VPP_OSD_SCI_WH_M1
	.comm	_VPP_OSD_SCO_H_START_END,4,2    ## @VPP_OSD_SCO_H_START_END
	.comm	_VPP_OSD_SCO_V_START_END,4,2    ## @VPP_OSD_SCO_V_START_END
	.comm	_VPP_OSD_VSC_INI_PHASE,4,2      ## @VPP_OSD_VSC_INI_PHASE
	.comm	_VPP_OSD_VSC_PHASE_STEP,4,2     ## @VPP_OSD_VSC_PHASE_STEP
	.comm	_VPP_OSD_HSC_INI_PHASE,4,2      ## @VPP_OSD_HSC_INI_PHASE
	.comm	_VPP_OSD_HSC_PHASE_STEP,4,2     ## @VPP_OSD_HSC_PHASE_STEP
	.comm	_VPP_OSD_HSC_CTRL0,4,2          ## @VPP_OSD_HSC_CTRL0
	.comm	_VPP_OSD_VSC_CTRL0,4,2          ## @VPP_OSD_VSC_CTRL0
	.comm	_MESON_CANVAS_WRAP_NONE,4,2     ## @MESON_CANVAS_WRAP_NONE
	.comm	_MESON_CANVAS_BLKMODE_LINEAR,4,2 ## @MESON_CANVAS_BLKMODE_LINEAR
	.comm	_MESON_CANVAS_ENDIAN_SWAP64,4,2 ## @MESON_CANVAS_ENDIAN_SWAP64
	.comm	_VD1_IF0_GEN_REG,4,2            ## @VD1_IF0_GEN_REG
	.comm	_VD2_IF0_GEN_REG,4,2            ## @VD2_IF0_GEN_REG
	.comm	_VD1_IF0_GEN_REG2,4,2           ## @VD1_IF0_GEN_REG2
	.comm	_VIU_VD1_FMT_CTRL,4,2           ## @VIU_VD1_FMT_CTRL
	.comm	_VIU_VD2_FMT_CTRL,4,2           ## @VIU_VD2_FMT_CTRL
	.comm	_VIU_VD1_FMT_W,4,2              ## @VIU_VD1_FMT_W
	.comm	_VIU_VD2_FMT_W,4,2              ## @VIU_VD2_FMT_W
	.comm	_VD1_IF0_CANVAS0,4,2            ## @VD1_IF0_CANVAS0
	.comm	_VD1_IF0_CANVAS1,4,2            ## @VD1_IF0_CANVAS1
	.comm	_VD2_IF0_CANVAS0,4,2            ## @VD2_IF0_CANVAS0
	.comm	_VD2_IF0_CANVAS1,4,2            ## @VD2_IF0_CANVAS1
	.comm	_VD1_IF0_LUMA_X0,4,2            ## @VD1_IF0_LUMA_X0
	.comm	_VD1_IF0_LUMA_X1,4,2            ## @VD1_IF0_LUMA_X1
	.comm	_VD2_IF0_LUMA_X0,4,2            ## @VD2_IF0_LUMA_X0
	.comm	_VD2_IF0_LUMA_X1,4,2            ## @VD2_IF0_LUMA_X1
	.comm	_VD1_IF0_LUMA_Y0,4,2            ## @VD1_IF0_LUMA_Y0
	.comm	_VD1_IF0_LUMA_Y1,4,2            ## @VD1_IF0_LUMA_Y1
	.comm	_VD2_IF0_LUMA_Y0,4,2            ## @VD2_IF0_LUMA_Y0
	.comm	_VD2_IF0_LUMA_Y1,4,2            ## @VD2_IF0_LUMA_Y1
	.comm	_VD1_IF0_CHROMA_X0,4,2          ## @VD1_IF0_CHROMA_X0
	.comm	_VD1_IF0_CHROMA_X1,4,2          ## @VD1_IF0_CHROMA_X1
	.comm	_VD2_IF0_CHROMA_X0,4,2          ## @VD2_IF0_CHROMA_X0
	.comm	_VD2_IF0_CHROMA_X1,4,2          ## @VD2_IF0_CHROMA_X1
	.comm	_VD1_IF0_CHROMA_Y0,4,2          ## @VD1_IF0_CHROMA_Y0
	.comm	_VD1_IF0_CHROMA_Y1,4,2          ## @VD1_IF0_CHROMA_Y1
	.comm	_VD2_IF0_CHROMA_Y0,4,2          ## @VD2_IF0_CHROMA_Y0
	.comm	_VD2_IF0_CHROMA_Y1,4,2          ## @VD2_IF0_CHROMA_Y1
	.comm	_VD1_IF0_RPT_LOOP,4,2           ## @VD1_IF0_RPT_LOOP
	.comm	_VD2_IF0_RPT_LOOP,4,2           ## @VD2_IF0_RPT_LOOP
	.comm	_VD1_IF0_LUMA0_RPT_PAT,4,2      ## @VD1_IF0_LUMA0_RPT_PAT
	.comm	_VD2_IF0_LUMA0_RPT_PAT,4,2      ## @VD2_IF0_LUMA0_RPT_PAT
	.comm	_VD1_IF0_LUMA1_RPT_PAT,4,2      ## @VD1_IF0_LUMA1_RPT_PAT
	.comm	_VD2_IF0_LUMA1_RPT_PAT,4,2      ## @VD2_IF0_LUMA1_RPT_PAT
	.comm	_VD1_IF0_CHROMA0_RPT_PAT,4,2    ## @VD1_IF0_CHROMA0_RPT_PAT
	.comm	_VD2_IF0_CHROMA0_RPT_PAT,4,2    ## @VD2_IF0_CHROMA0_RPT_PAT
	.comm	_VD1_IF0_CHROMA1_RPT_PAT,4,2    ## @VD1_IF0_CHROMA1_RPT_PAT
	.comm	_VD2_IF0_CHROMA1_RPT_PAT,4,2    ## @VD2_IF0_CHROMA1_RPT_PAT
	.comm	_VD1_IF0_LUMA_PSEL,4,2          ## @VD1_IF0_LUMA_PSEL
	.comm	_VD1_IF0_CHROMA_PSEL,4,2        ## @VD1_IF0_CHROMA_PSEL
	.comm	_VD2_IF0_LUMA_PSEL,4,2          ## @VD2_IF0_LUMA_PSEL
	.comm	_VD2_IF0_CHROMA_PSEL,4,2        ## @VD2_IF0_CHROMA_PSEL
	.comm	_VD1_IF0_RANGE_MAP_Y,4,2        ## @VD1_IF0_RANGE_MAP_Y
	.comm	_VD1_IF0_RANGE_MAP_CB,4,2       ## @VD1_IF0_RANGE_MAP_CB
	.comm	_VD1_IF0_RANGE_MAP_CR,4,2       ## @VD1_IF0_RANGE_MAP_CR
	.comm	_VPP_SC_VD_EN_ENABLE,4,2        ## @VPP_SC_VD_EN_ENABLE
	.comm	_VPP_SC_TOP_EN_ENABLE,4,2       ## @VPP_SC_TOP_EN_ENABLE
	.comm	_VPP_SC_HSC_EN_ENABLE,4,2       ## @VPP_SC_HSC_EN_ENABLE
	.comm	_VPP_SC_VSC_EN_ENABLE,4,2       ## @VPP_SC_VSC_EN_ENABLE
	.comm	_VPP_SC_MISC,4,2                ## @VPP_SC_MISC
	.comm	_VPP_PIC_IN_HEIGHT,4,2          ## @VPP_PIC_IN_HEIGHT
	.comm	_VPP_POSTBLEND_VD1_H_START_END,4,2 ## @VPP_POSTBLEND_VD1_H_START_END
	.comm	_VPP_BLEND_VD2_H_START_END,4,2  ## @VPP_BLEND_VD2_H_START_END
	.comm	_VPP_POSTBLEND_VD1_V_START_END,4,2 ## @VPP_POSTBLEND_VD1_V_START_END
	.comm	_VPP_BLEND_VD2_V_START_END,4,2  ## @VPP_BLEND_VD2_V_START_END
	.comm	_VPP_HSC_REGION12_STARTP,4,2    ## @VPP_HSC_REGION12_STARTP
	.comm	_VPP_HSC_REGION34_STARTP,4,2    ## @VPP_HSC_REGION34_STARTP
	.comm	_VPP_HSC_REGION4_ENDP,4,2       ## @VPP_HSC_REGION4_ENDP
	.comm	_VPP_HSC_START_PHASE_STEP,4,2   ## @VPP_HSC_START_PHASE_STEP
	.comm	_VPP_HSC_REGION1_PHASE_SLOPE,4,2 ## @VPP_HSC_REGION1_PHASE_SLOPE
	.comm	_VPP_HSC_REGION3_PHASE_SLOPE,4,2 ## @VPP_HSC_REGION3_PHASE_SLOPE
	.comm	_VPP_LINE_IN_LENGTH,4,2         ## @VPP_LINE_IN_LENGTH
	.comm	_VPP_PREBLEND_H_SIZE,4,2        ## @VPP_PREBLEND_H_SIZE
	.comm	_VPP_VSC_REGION12_STARTP,4,2    ## @VPP_VSC_REGION12_STARTP
	.comm	_VPP_VSC_REGION34_STARTP,4,2    ## @VPP_VSC_REGION34_STARTP
	.comm	_VPP_VSC_REGION4_ENDP,4,2       ## @VPP_VSC_REGION4_ENDP
	.comm	_VPP_VSC_START_PHASE_STEP,4,2   ## @VPP_VSC_START_PHASE_STEP
	.comm	_VPP_VSC_INI_PHASE,4,2          ## @VPP_VSC_INI_PHASE
	.comm	_VPP_VSC_PHASE_CTRL,4,2         ## @VPP_VSC_PHASE_CTRL
	.comm	_VPP_HSC_PHASE_CTRL,4,2         ## @VPP_HSC_PHASE_CTRL
	.comm	_VPP_SCALE_COEF_IDX,4,2         ## @VPP_SCALE_COEF_IDX
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_meson_crtc_irq                 ; -- Begin function meson_crtc_irq
	.p2align	2
_meson_crtc_irq:                        ; @meson_crtc_irq
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	w0, [x0, #8]
	bl	_to_meson_crtc
	mov	x20, x0
	ldr	x8, [x19, #280]
	cbz	x8, LBB0_5
; %bb.1:
	ldr	w8, [x19, #16]
	cbz	w8, LBB0_5
; %bb.2:
	ldr	w21, [x19, #20]
	ldr	x22, [x19, #288]
Lloh0:
	adrp	x8, _VIU_OSD1_CTRL_STAT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _VIU_OSD1_CTRL_STAT@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	x8, [x19, #24]
	ldr	w21, [x8]
	ldr	x22, [x19, #288]
Lloh3:
	adrp	x8, _VIU_OSD1_BLK0_CFG_W0@GOTPAGE
Lloh4:
	ldr	x8, [x8, _VIU_OSD1_BLK0_CFG_W0@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	x8, [x19, #24]
	ldr	w21, [x8, #4]
	ldr	x22, [x19, #288]
Lloh6:
	adrp	x8, _VIU_OSD1_BLK0_CFG_W1@GOTPAGE
Lloh7:
	ldr	x8, [x8, _VIU_OSD1_BLK0_CFG_W1@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	x8, [x19, #24]
	ldr	w21, [x8, #8]
	ldr	x22, [x19, #288]
Lloh9:
	adrp	x8, _VIU_OSD1_BLK0_CFG_W2@GOTPAGE
Lloh10:
	ldr	x8, [x8, _VIU_OSD1_BLK0_CFG_W2@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	x8, [x19, #24]
	ldr	w21, [x8, #12]
	ldr	x22, [x19, #288]
Lloh12:
	adrp	x8, _VIU_OSD1_BLK0_CFG_W3@GOTPAGE
Lloh13:
	ldr	x8, [x8, _VIU_OSD1_BLK0_CFG_W3@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	x8, [x19, #24]
	ldr	w21, [x8, #16]
	ldr	x22, [x19, #288]
Lloh15:
	adrp	x8, _VIU_OSD1_BLK0_CFG_W4@GOTPAGE
Lloh16:
	ldr	x8, [x8, _VIU_OSD1_BLK0_CFG_W4@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #32]
	ldr	x22, [x19, #288]
Lloh18:
	adrp	x8, _VPP_OSD_SC_CTRL0@GOTPAGE
Lloh19:
	ldr	x8, [x8, _VPP_OSD_SC_CTRL0@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #36]
	ldr	x22, [x19, #288]
Lloh21:
	adrp	x8, _VPP_OSD_SCI_WH_M1@GOTPAGE
Lloh22:
	ldr	x8, [x8, _VPP_OSD_SCI_WH_M1@GOTPAGEOFF]
Lloh23:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #40]
	ldr	x22, [x19, #288]
Lloh24:
	adrp	x8, _VPP_OSD_SCO_H_START_END@GOTPAGE
Lloh25:
	ldr	x8, [x8, _VPP_OSD_SCO_H_START_END@GOTPAGEOFF]
Lloh26:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #44]
	ldr	x22, [x19, #288]
Lloh27:
	adrp	x8, _VPP_OSD_SCO_V_START_END@GOTPAGE
Lloh28:
	ldr	x8, [x8, _VPP_OSD_SCO_V_START_END@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #48]
	ldr	x22, [x19, #288]
Lloh30:
	adrp	x8, _VPP_OSD_VSC_INI_PHASE@GOTPAGE
Lloh31:
	ldr	x8, [x8, _VPP_OSD_VSC_INI_PHASE@GOTPAGEOFF]
Lloh32:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #52]
	ldr	x22, [x19, #288]
Lloh33:
	adrp	x8, _VPP_OSD_VSC_PHASE_STEP@GOTPAGE
Lloh34:
	ldr	x8, [x8, _VPP_OSD_VSC_PHASE_STEP@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #56]
	ldr	x22, [x19, #288]
Lloh36:
	adrp	x8, _VPP_OSD_HSC_INI_PHASE@GOTPAGE
Lloh37:
	ldr	x8, [x8, _VPP_OSD_HSC_INI_PHASE@GOTPAGEOFF]
Lloh38:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #60]
	ldr	x22, [x19, #288]
Lloh39:
	adrp	x8, _VPP_OSD_HSC_PHASE_STEP@GOTPAGE
Lloh40:
	ldr	x8, [x8, _VPP_OSD_HSC_PHASE_STEP@GOTPAGEOFF]
Lloh41:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #64]
	ldr	x22, [x19, #288]
Lloh42:
	adrp	x8, _VPP_OSD_HSC_CTRL0@GOTPAGE
Lloh43:
	ldr	x8, [x8, _VPP_OSD_HSC_CTRL0@GOTPAGEOFF]
Lloh44:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #68]
	ldr	x22, [x19, #288]
Lloh45:
	adrp	x8, _VPP_OSD_VSC_CTRL0@GOTPAGE
Lloh46:
	ldr	x8, [x8, _VPP_OSD_VSC_CTRL0@GOTPAGEOFF]
Lloh47:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w0, [x19, #300]
	ldr	w1, [x19, #312]
	ldr	w2, [x19, #272]
	ldr	w3, [x19, #268]
	ldr	w4, [x19, #264]
Lloh48:
	adrp	x8, _MESON_CANVAS_WRAP_NONE@GOTPAGE
Lloh49:
	ldr	x8, [x8, _MESON_CANVAS_WRAP_NONE@GOTPAGEOFF]
Lloh50:
	ldr	w5, [x8]
Lloh51:
	adrp	x8, _MESON_CANVAS_BLKMODE_LINEAR@GOTPAGE
Lloh52:
	ldr	x8, [x8, _MESON_CANVAS_BLKMODE_LINEAR@GOTPAGEOFF]
Lloh53:
	ldr	w6, [x8]
	mov	w7, #0
	bl	_meson_canvas_config
	ldr	x8, [x20, #24]
	cbz	x8, LBB0_4
; %bb.3:
	mov	x0, x19
	blr	x8
LBB0_4:
	str	wzr, [x19, #16]
LBB0_5:
	ldr	x8, [x19, #256]
	cbz	x8, LBB0_16
; %bb.6:
	ldr	w8, [x19, #72]
	cbz	w8, LBB0_16
; %bb.7:
	ldr	w8, [x19, #76]
	cmp	w8, #1
	b.eq	LBB0_12
; %bb.8:
	cmp	w8, #2
	b.eq	LBB0_11
; %bb.9:
	cmp	w8, #3
	b.ne	LBB0_13
; %bb.10:
	ldr	w0, [x19, #300]
	ldr	w1, [x19, #308]
	ldp	w3, w2, [x19, #248]
	ldr	w4, [x19, #244]
Lloh54:
	adrp	x8, _MESON_CANVAS_WRAP_NONE@GOTPAGE
Lloh55:
	ldr	x8, [x8, _MESON_CANVAS_WRAP_NONE@GOTPAGEOFF]
Lloh56:
	ldr	w5, [x8]
Lloh57:
	adrp	x8, _MESON_CANVAS_BLKMODE_LINEAR@GOTPAGE
Lloh58:
	ldr	x8, [x8, _MESON_CANVAS_BLKMODE_LINEAR@GOTPAGEOFF]
Lloh59:
	ldr	w6, [x8]
Lloh60:
	adrp	x8, _MESON_CANVAS_ENDIAN_SWAP64@GOTPAGE
Lloh61:
	ldr	x8, [x8, _MESON_CANVAS_ENDIAN_SWAP64@GOTPAGEOFF]
Lloh62:
	ldr	w7, [x8]
	bl	_meson_canvas_config
LBB0_11:
	ldr	w0, [x19, #300]
	ldr	w1, [x19, #304]
	ldp	w3, w2, [x19, #236]
	ldr	w4, [x19, #232]
Lloh63:
	adrp	x8, _MESON_CANVAS_WRAP_NONE@GOTPAGE
Lloh64:
	ldr	x8, [x8, _MESON_CANVAS_WRAP_NONE@GOTPAGEOFF]
Lloh65:
	ldr	w5, [x8]
Lloh66:
	adrp	x8, _MESON_CANVAS_BLKMODE_LINEAR@GOTPAGE
Lloh67:
	ldr	x8, [x8, _MESON_CANVAS_BLKMODE_LINEAR@GOTPAGEOFF]
Lloh68:
	ldr	w6, [x8]
Lloh69:
	adrp	x8, _MESON_CANVAS_ENDIAN_SWAP64@GOTPAGE
Lloh70:
	ldr	x8, [x8, _MESON_CANVAS_ENDIAN_SWAP64@GOTPAGEOFF]
Lloh71:
	ldr	w7, [x8]
	bl	_meson_canvas_config
LBB0_12:
	ldr	w0, [x19, #300]
	ldr	w1, [x19, #296]
	ldp	w3, w2, [x19, #224]
	ldr	w4, [x19, #220]
Lloh72:
	adrp	x8, _MESON_CANVAS_WRAP_NONE@GOTPAGE
Lloh73:
	ldr	x8, [x8, _MESON_CANVAS_WRAP_NONE@GOTPAGEOFF]
Lloh74:
	ldr	w5, [x8]
Lloh75:
	adrp	x8, _MESON_CANVAS_BLKMODE_LINEAR@GOTPAGE
Lloh76:
	ldr	x8, [x8, _MESON_CANVAS_BLKMODE_LINEAR@GOTPAGEOFF]
Lloh77:
	ldr	w6, [x8]
Lloh78:
	adrp	x8, _MESON_CANVAS_ENDIAN_SWAP64@GOTPAGE
Lloh79:
	ldr	x8, [x8, _MESON_CANVAS_ENDIAN_SWAP64@GOTPAGEOFF]
Lloh80:
	ldr	w7, [x8]
	bl	_meson_canvas_config
LBB0_13:
	ldr	w21, [x19, #80]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh81:
	adrp	x8, _VD1_IF0_GEN_REG@GOTPAGE
Lloh82:
	ldr	x8, [x8, _VD1_IF0_GEN_REG@GOTPAGEOFF]
Lloh83:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #80]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh84:
	adrp	x8, _VD2_IF0_GEN_REG@GOTPAGE
Lloh85:
	ldr	x8, [x8, _VD2_IF0_GEN_REG@GOTPAGEOFF]
Lloh86:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #84]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh87:
	adrp	x8, _VD1_IF0_GEN_REG2@GOTPAGE
Lloh88:
	ldr	x8, [x8, _VD1_IF0_GEN_REG2@GOTPAGEOFF]
Lloh89:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #88]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh90:
	adrp	x8, _VIU_VD1_FMT_CTRL@GOTPAGE
Lloh91:
	ldr	x8, [x8, _VIU_VD1_FMT_CTRL@GOTPAGEOFF]
Lloh92:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #88]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh93:
	adrp	x8, _VIU_VD2_FMT_CTRL@GOTPAGE
Lloh94:
	ldr	x8, [x8, _VIU_VD2_FMT_CTRL@GOTPAGEOFF]
Lloh95:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #92]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh96:
	adrp	x8, _VIU_VD1_FMT_W@GOTPAGE
Lloh97:
	ldr	x8, [x8, _VIU_VD1_FMT_W@GOTPAGEOFF]
Lloh98:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #92]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh99:
	adrp	x8, _VIU_VD2_FMT_W@GOTPAGE
Lloh100:
	ldr	x8, [x8, _VIU_VD2_FMT_W@GOTPAGEOFF]
Lloh101:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #96]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh102:
	adrp	x8, _VD1_IF0_CANVAS0@GOTPAGE
Lloh103:
	ldr	x8, [x8, _VD1_IF0_CANVAS0@GOTPAGEOFF]
Lloh104:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #96]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh105:
	adrp	x8, _VD1_IF0_CANVAS1@GOTPAGE
Lloh106:
	ldr	x8, [x8, _VD1_IF0_CANVAS1@GOTPAGEOFF]
Lloh107:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #96]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh108:
	adrp	x8, _VD2_IF0_CANVAS0@GOTPAGE
Lloh109:
	ldr	x8, [x8, _VD2_IF0_CANVAS0@GOTPAGEOFF]
Lloh110:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #96]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh111:
	adrp	x8, _VD2_IF0_CANVAS1@GOTPAGE
Lloh112:
	ldr	x8, [x8, _VD2_IF0_CANVAS1@GOTPAGEOFF]
Lloh113:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #100]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh114:
	adrp	x8, _VD1_IF0_LUMA_X0@GOTPAGE
Lloh115:
	ldr	x8, [x8, _VD1_IF0_LUMA_X0@GOTPAGEOFF]
Lloh116:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #100]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh117:
	adrp	x8, _VD1_IF0_LUMA_X1@GOTPAGE
Lloh118:
	ldr	x8, [x8, _VD1_IF0_LUMA_X1@GOTPAGEOFF]
Lloh119:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #100]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh120:
	adrp	x8, _VD2_IF0_LUMA_X0@GOTPAGE
Lloh121:
	ldr	x8, [x8, _VD2_IF0_LUMA_X0@GOTPAGEOFF]
Lloh122:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #100]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh123:
	adrp	x8, _VD2_IF0_LUMA_X1@GOTPAGE
Lloh124:
	ldr	x8, [x8, _VD2_IF0_LUMA_X1@GOTPAGEOFF]
Lloh125:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #104]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh126:
	adrp	x8, _VD1_IF0_LUMA_Y0@GOTPAGE
Lloh127:
	ldr	x8, [x8, _VD1_IF0_LUMA_Y0@GOTPAGEOFF]
Lloh128:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #104]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh129:
	adrp	x8, _VD1_IF0_LUMA_Y1@GOTPAGE
Lloh130:
	ldr	x8, [x8, _VD1_IF0_LUMA_Y1@GOTPAGEOFF]
Lloh131:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #104]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh132:
	adrp	x8, _VD2_IF0_LUMA_Y0@GOTPAGE
Lloh133:
	ldr	x8, [x8, _VD2_IF0_LUMA_Y0@GOTPAGEOFF]
Lloh134:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #104]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh135:
	adrp	x8, _VD2_IF0_LUMA_Y1@GOTPAGE
Lloh136:
	ldr	x8, [x8, _VD2_IF0_LUMA_Y1@GOTPAGEOFF]
Lloh137:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #108]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh138:
	adrp	x8, _VD1_IF0_CHROMA_X0@GOTPAGE
Lloh139:
	ldr	x8, [x8, _VD1_IF0_CHROMA_X0@GOTPAGEOFF]
Lloh140:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #108]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh141:
	adrp	x8, _VD1_IF0_CHROMA_X1@GOTPAGE
Lloh142:
	ldr	x8, [x8, _VD1_IF0_CHROMA_X1@GOTPAGEOFF]
Lloh143:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #108]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh144:
	adrp	x8, _VD2_IF0_CHROMA_X0@GOTPAGE
Lloh145:
	ldr	x8, [x8, _VD2_IF0_CHROMA_X0@GOTPAGEOFF]
Lloh146:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #108]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh147:
	adrp	x8, _VD2_IF0_CHROMA_X1@GOTPAGE
Lloh148:
	ldr	x8, [x8, _VD2_IF0_CHROMA_X1@GOTPAGEOFF]
Lloh149:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #112]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh150:
	adrp	x8, _VD1_IF0_CHROMA_Y0@GOTPAGE
Lloh151:
	ldr	x8, [x8, _VD1_IF0_CHROMA_Y0@GOTPAGEOFF]
Lloh152:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #112]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh153:
	adrp	x8, _VD1_IF0_CHROMA_Y1@GOTPAGE
Lloh154:
	ldr	x8, [x8, _VD1_IF0_CHROMA_Y1@GOTPAGEOFF]
Lloh155:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #112]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh156:
	adrp	x8, _VD2_IF0_CHROMA_Y0@GOTPAGE
Lloh157:
	ldr	x8, [x8, _VD2_IF0_CHROMA_Y0@GOTPAGEOFF]
Lloh158:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #112]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh159:
	adrp	x8, _VD2_IF0_CHROMA_Y1@GOTPAGE
Lloh160:
	ldr	x8, [x8, _VD2_IF0_CHROMA_Y1@GOTPAGEOFF]
Lloh161:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #116]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh162:
	adrp	x8, _VD1_IF0_RPT_LOOP@GOTPAGE
Lloh163:
	ldr	x8, [x8, _VD1_IF0_RPT_LOOP@GOTPAGEOFF]
Lloh164:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #116]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh165:
	adrp	x8, _VD2_IF0_RPT_LOOP@GOTPAGE
Lloh166:
	ldr	x8, [x8, _VD2_IF0_RPT_LOOP@GOTPAGEOFF]
Lloh167:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #120]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh168:
	adrp	x8, _VD1_IF0_LUMA0_RPT_PAT@GOTPAGE
Lloh169:
	ldr	x8, [x8, _VD1_IF0_LUMA0_RPT_PAT@GOTPAGEOFF]
Lloh170:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #120]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh171:
	adrp	x8, _VD2_IF0_LUMA0_RPT_PAT@GOTPAGE
Lloh172:
	ldr	x8, [x8, _VD2_IF0_LUMA0_RPT_PAT@GOTPAGEOFF]
Lloh173:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #120]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh174:
	adrp	x8, _VD1_IF0_LUMA1_RPT_PAT@GOTPAGE
Lloh175:
	ldr	x8, [x8, _VD1_IF0_LUMA1_RPT_PAT@GOTPAGEOFF]
Lloh176:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #120]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh177:
	adrp	x8, _VD2_IF0_LUMA1_RPT_PAT@GOTPAGE
Lloh178:
	ldr	x8, [x8, _VD2_IF0_LUMA1_RPT_PAT@GOTPAGEOFF]
Lloh179:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #124]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh180:
	adrp	x8, _VD1_IF0_CHROMA0_RPT_PAT@GOTPAGE
Lloh181:
	ldr	x8, [x8, _VD1_IF0_CHROMA0_RPT_PAT@GOTPAGEOFF]
Lloh182:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #124]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh183:
	adrp	x8, _VD2_IF0_CHROMA0_RPT_PAT@GOTPAGE
Lloh184:
	ldr	x8, [x8, _VD2_IF0_CHROMA0_RPT_PAT@GOTPAGEOFF]
Lloh185:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #124]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh186:
	adrp	x8, _VD1_IF0_CHROMA1_RPT_PAT@GOTPAGE
Lloh187:
	ldr	x8, [x8, _VD1_IF0_CHROMA1_RPT_PAT@GOTPAGEOFF]
Lloh188:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #124]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh189:
	adrp	x8, _VD2_IF0_CHROMA1_RPT_PAT@GOTPAGE
Lloh190:
	ldr	x8, [x8, _VD2_IF0_CHROMA1_RPT_PAT@GOTPAGEOFF]
Lloh191:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x21, x9, x8
Lloh192:
	adrp	x8, _VD1_IF0_LUMA_PSEL@GOTPAGE
Lloh193:
	ldr	x8, [x8, _VD1_IF0_LUMA_PSEL@GOTPAGEOFF]
Lloh194:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x21, x0
	mov	w0, #0
	bl	_writel_relaxed
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x21, x9, x8
Lloh195:
	adrp	x8, _VD1_IF0_CHROMA_PSEL@GOTPAGE
Lloh196:
	ldr	x8, [x8, _VD1_IF0_CHROMA_PSEL@GOTPAGEOFF]
Lloh197:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x21, x0
	mov	w0, #0
	bl	_writel_relaxed
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x21, x9, x8
Lloh198:
	adrp	x8, _VD2_IF0_LUMA_PSEL@GOTPAGE
Lloh199:
	ldr	x8, [x8, _VD2_IF0_LUMA_PSEL@GOTPAGEOFF]
Lloh200:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x21, x0
	mov	w0, #0
	bl	_writel_relaxed
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x21, x9, x8
Lloh201:
	adrp	x8, _VD2_IF0_CHROMA_PSEL@GOTPAGE
Lloh202:
	ldr	x8, [x8, _VD2_IF0_CHROMA_PSEL@GOTPAGEOFF]
Lloh203:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x21, x0
	mov	w0, #0
	bl	_writel_relaxed
	ldr	w21, [x19, #128]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh204:
	adrp	x8, _VD1_IF0_RANGE_MAP_Y@GOTPAGE
Lloh205:
	ldr	x8, [x8, _VD1_IF0_RANGE_MAP_Y@GOTPAGEOFF]
Lloh206:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #132]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh207:
	adrp	x8, _VD1_IF0_RANGE_MAP_CB@GOTPAGE
Lloh208:
	ldr	x8, [x8, _VD1_IF0_RANGE_MAP_CB@GOTPAGEOFF]
Lloh209:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #136]
	ldr	x8, [x19, #288]
	ldr	x9, [x20, #16]
	add	x22, x9, x8
Lloh210:
	adrp	x8, _VD1_IF0_RANGE_MAP_CR@GOTPAGE
Lloh211:
	ldr	x8, [x8, _VD1_IF0_RANGE_MAP_CR@GOTPAGEOFF]
Lloh212:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x22, x0
	mov	x0, x21
	bl	_writel_relaxed
	mov	w0, #4
	bl	_VPP_VSC_BANK_LENGTH
	mov	x21, x0
	mov	w0, #4
	bl	_VPP_HSC_BANK_LENGTH
	orr	w8, w0, w21
Lloh213:
	adrp	x9, _VPP_SC_VD_EN_ENABLE@GOTPAGE
Lloh214:
	ldr	x9, [x9, _VPP_SC_VD_EN_ENABLE@GOTPAGEOFF]
Lloh215:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh216:
	adrp	x9, _VPP_SC_TOP_EN_ENABLE@GOTPAGE
Lloh217:
	ldr	x9, [x9, _VPP_SC_TOP_EN_ENABLE@GOTPAGEOFF]
Lloh218:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh219:
	adrp	x9, _VPP_SC_HSC_EN_ENABLE@GOTPAGE
Lloh220:
	ldr	x9, [x9, _VPP_SC_HSC_EN_ENABLE@GOTPAGEOFF]
Lloh221:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh222:
	adrp	x9, _VPP_SC_VSC_EN_ENABLE@GOTPAGE
Lloh223:
	ldr	x9, [x9, _VPP_SC_VSC_EN_ENABLE@GOTPAGEOFF]
Lloh224:
	ldr	w9, [x9]
	orr	w21, w8, w9
	ldr	x22, [x19, #288]
Lloh225:
	adrp	x8, _VPP_SC_MISC@GOTPAGE
Lloh226:
	ldr	x8, [x8, _VPP_SC_MISC@GOTPAGEOFF]
Lloh227:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #140]
	ldr	x22, [x19, #288]
Lloh228:
	adrp	x8, _VPP_PIC_IN_HEIGHT@GOTPAGE
Lloh229:
	ldr	x8, [x8, _VPP_PIC_IN_HEIGHT@GOTPAGEOFF]
Lloh230:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #144]
	ldr	x22, [x19, #288]
Lloh231:
	adrp	x8, _VPP_POSTBLEND_VD1_H_START_END@GOTPAGE
Lloh232:
	ldr	x8, [x8, _VPP_POSTBLEND_VD1_H_START_END@GOTPAGEOFF]
Lloh233:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #148]
	ldr	x22, [x19, #288]
Lloh234:
	adrp	x8, _VPP_BLEND_VD2_H_START_END@GOTPAGE
Lloh235:
	ldr	x8, [x8, _VPP_BLEND_VD2_H_START_END@GOTPAGEOFF]
Lloh236:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #152]
	ldr	x22, [x19, #288]
Lloh237:
	adrp	x8, _VPP_POSTBLEND_VD1_V_START_END@GOTPAGE
Lloh238:
	ldr	x8, [x8, _VPP_POSTBLEND_VD1_V_START_END@GOTPAGEOFF]
Lloh239:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #156]
	ldr	x22, [x19, #288]
Lloh240:
	adrp	x8, _VPP_BLEND_VD2_V_START_END@GOTPAGE
Lloh241:
	ldr	x8, [x8, _VPP_BLEND_VD2_V_START_END@GOTPAGEOFF]
Lloh242:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #160]
	ldr	x22, [x19, #288]
Lloh243:
	adrp	x8, _VPP_HSC_REGION12_STARTP@GOTPAGE
Lloh244:
	ldr	x8, [x8, _VPP_HSC_REGION12_STARTP@GOTPAGEOFF]
Lloh245:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #164]
	ldr	x22, [x19, #288]
Lloh246:
	adrp	x8, _VPP_HSC_REGION34_STARTP@GOTPAGE
Lloh247:
	ldr	x8, [x8, _VPP_HSC_REGION34_STARTP@GOTPAGEOFF]
Lloh248:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #168]
	ldr	x22, [x19, #288]
Lloh249:
	adrp	x8, _VPP_HSC_REGION4_ENDP@GOTPAGE
Lloh250:
	ldr	x8, [x8, _VPP_HSC_REGION4_ENDP@GOTPAGEOFF]
Lloh251:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #172]
	ldr	x22, [x19, #288]
Lloh252:
	adrp	x8, _VPP_HSC_START_PHASE_STEP@GOTPAGE
Lloh253:
	ldr	x8, [x8, _VPP_HSC_START_PHASE_STEP@GOTPAGEOFF]
Lloh254:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #176]
	ldr	x22, [x19, #288]
Lloh255:
	adrp	x8, _VPP_HSC_REGION1_PHASE_SLOPE@GOTPAGE
Lloh256:
	ldr	x8, [x8, _VPP_HSC_REGION1_PHASE_SLOPE@GOTPAGEOFF]
Lloh257:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #180]
	ldr	x22, [x19, #288]
Lloh258:
	adrp	x8, _VPP_HSC_REGION3_PHASE_SLOPE@GOTPAGE
Lloh259:
	ldr	x8, [x8, _VPP_HSC_REGION3_PHASE_SLOPE@GOTPAGEOFF]
Lloh260:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #184]
	ldr	x22, [x19, #288]
Lloh261:
	adrp	x8, _VPP_LINE_IN_LENGTH@GOTPAGE
Lloh262:
	ldr	x8, [x8, _VPP_LINE_IN_LENGTH@GOTPAGEOFF]
Lloh263:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #188]
	ldr	x22, [x19, #288]
Lloh264:
	adrp	x8, _VPP_PREBLEND_H_SIZE@GOTPAGE
Lloh265:
	ldr	x8, [x8, _VPP_PREBLEND_H_SIZE@GOTPAGEOFF]
Lloh266:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #192]
	ldr	x22, [x19, #288]
Lloh267:
	adrp	x8, _VPP_VSC_REGION12_STARTP@GOTPAGE
Lloh268:
	ldr	x8, [x8, _VPP_VSC_REGION12_STARTP@GOTPAGEOFF]
Lloh269:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #196]
	ldr	x22, [x19, #288]
Lloh270:
	adrp	x8, _VPP_VSC_REGION34_STARTP@GOTPAGE
Lloh271:
	ldr	x8, [x8, _VPP_VSC_REGION34_STARTP@GOTPAGEOFF]
Lloh272:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #200]
	ldr	x22, [x19, #288]
Lloh273:
	adrp	x8, _VPP_VSC_REGION4_ENDP@GOTPAGE
Lloh274:
	ldr	x8, [x8, _VPP_VSC_REGION4_ENDP@GOTPAGEOFF]
Lloh275:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #204]
	ldr	x22, [x19, #288]
Lloh276:
	adrp	x8, _VPP_VSC_START_PHASE_STEP@GOTPAGE
Lloh277:
	ldr	x8, [x8, _VPP_VSC_START_PHASE_STEP@GOTPAGEOFF]
Lloh278:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #208]
	ldr	x22, [x19, #288]
Lloh279:
	adrp	x8, _VPP_VSC_INI_PHASE@GOTPAGE
Lloh280:
	ldr	x8, [x8, _VPP_VSC_INI_PHASE@GOTPAGEOFF]
Lloh281:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #212]
	ldr	x22, [x19, #288]
Lloh282:
	adrp	x8, _VPP_VSC_PHASE_CTRL@GOTPAGE
Lloh283:
	ldr	x8, [x8, _VPP_VSC_PHASE_CTRL@GOTPAGEOFF]
Lloh284:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x19, #216]
	ldr	x22, [x19, #288]
Lloh285:
	adrp	x8, _VPP_HSC_PHASE_CTRL@GOTPAGE
Lloh286:
	ldr	x8, [x8, _VPP_HSC_PHASE_CTRL@GOTPAGEOFF]
Lloh287:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
	ldr	x21, [x19, #288]
Lloh288:
	adrp	x8, _VPP_SCALE_COEF_IDX@GOTPAGE
Lloh289:
	ldr	x8, [x8, _VPP_SCALE_COEF_IDX@GOTPAGEOFF]
Lloh290:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x21
	mov	w0, #66
	bl	_writel_relaxed
	ldr	x8, [x20, #8]
	cbz	x8, LBB0_15
; %bb.14:
	mov	x0, x19
	blr	x8
LBB0_15:
	str	wzr, [x19, #72]
LBB0_16:
	ldr	w0, [x19, #8]
	bl	_drm_crtc_handle_vblank
	ldr	x0, [x19]
	bl	_spin_lock_irqsave
	ldr	x1, [x20]
	cbz	x1, LBB0_18
; %bb.17:
	ldr	w0, [x19, #8]
	bl	_drm_crtc_send_vblank_event
	ldr	w0, [x19, #8]
	bl	_drm_crtc_vblank_put
	str	xzr, [x20]
LBB0_18:
	ldr	x0, [x19]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_spin_unlock_irqrestore
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh288, Lloh289, Lloh290
	.loh AdrpLdrGotLdr	Lloh285, Lloh286, Lloh287
	.loh AdrpLdrGotLdr	Lloh282, Lloh283, Lloh284
	.loh AdrpLdrGotLdr	Lloh279, Lloh280, Lloh281
	.loh AdrpLdrGotLdr	Lloh276, Lloh277, Lloh278
	.loh AdrpLdrGotLdr	Lloh273, Lloh274, Lloh275
	.loh AdrpLdrGotLdr	Lloh270, Lloh271, Lloh272
	.loh AdrpLdrGotLdr	Lloh267, Lloh268, Lloh269
	.loh AdrpLdrGotLdr	Lloh264, Lloh265, Lloh266
	.loh AdrpLdrGotLdr	Lloh261, Lloh262, Lloh263
	.loh AdrpLdrGotLdr	Lloh258, Lloh259, Lloh260
	.loh AdrpLdrGotLdr	Lloh255, Lloh256, Lloh257
	.loh AdrpLdrGotLdr	Lloh252, Lloh253, Lloh254
	.loh AdrpLdrGotLdr	Lloh249, Lloh250, Lloh251
	.loh AdrpLdrGotLdr	Lloh246, Lloh247, Lloh248
	.loh AdrpLdrGotLdr	Lloh243, Lloh244, Lloh245
	.loh AdrpLdrGotLdr	Lloh240, Lloh241, Lloh242
	.loh AdrpLdrGotLdr	Lloh237, Lloh238, Lloh239
	.loh AdrpLdrGotLdr	Lloh234, Lloh235, Lloh236
	.loh AdrpLdrGotLdr	Lloh231, Lloh232, Lloh233
	.loh AdrpLdrGotLdr	Lloh228, Lloh229, Lloh230
	.loh AdrpLdrGotLdr	Lloh225, Lloh226, Lloh227
	.loh AdrpLdrGotLdr	Lloh222, Lloh223, Lloh224
	.loh AdrpLdrGotLdr	Lloh219, Lloh220, Lloh221
	.loh AdrpLdrGotLdr	Lloh216, Lloh217, Lloh218
	.loh AdrpLdrGotLdr	Lloh213, Lloh214, Lloh215
	.loh AdrpLdrGotLdr	Lloh210, Lloh211, Lloh212
	.loh AdrpLdrGotLdr	Lloh207, Lloh208, Lloh209
	.loh AdrpLdrGotLdr	Lloh204, Lloh205, Lloh206
	.loh AdrpLdrGotLdr	Lloh201, Lloh202, Lloh203
	.loh AdrpLdrGotLdr	Lloh198, Lloh199, Lloh200
	.loh AdrpLdrGotLdr	Lloh195, Lloh196, Lloh197
	.loh AdrpLdrGotLdr	Lloh192, Lloh193, Lloh194
	.loh AdrpLdrGotLdr	Lloh189, Lloh190, Lloh191
	.loh AdrpLdrGotLdr	Lloh186, Lloh187, Lloh188
	.loh AdrpLdrGotLdr	Lloh183, Lloh184, Lloh185
	.loh AdrpLdrGotLdr	Lloh180, Lloh181, Lloh182
	.loh AdrpLdrGotLdr	Lloh177, Lloh178, Lloh179
	.loh AdrpLdrGotLdr	Lloh174, Lloh175, Lloh176
	.loh AdrpLdrGotLdr	Lloh171, Lloh172, Lloh173
	.loh AdrpLdrGotLdr	Lloh168, Lloh169, Lloh170
	.loh AdrpLdrGotLdr	Lloh165, Lloh166, Lloh167
	.loh AdrpLdrGotLdr	Lloh162, Lloh163, Lloh164
	.loh AdrpLdrGotLdr	Lloh159, Lloh160, Lloh161
	.loh AdrpLdrGotLdr	Lloh156, Lloh157, Lloh158
	.loh AdrpLdrGotLdr	Lloh153, Lloh154, Lloh155
	.loh AdrpLdrGotLdr	Lloh150, Lloh151, Lloh152
	.loh AdrpLdrGotLdr	Lloh147, Lloh148, Lloh149
	.loh AdrpLdrGotLdr	Lloh144, Lloh145, Lloh146
	.loh AdrpLdrGotLdr	Lloh141, Lloh142, Lloh143
	.loh AdrpLdrGotLdr	Lloh138, Lloh139, Lloh140
	.loh AdrpLdrGotLdr	Lloh135, Lloh136, Lloh137
	.loh AdrpLdrGotLdr	Lloh132, Lloh133, Lloh134
	.loh AdrpLdrGotLdr	Lloh129, Lloh130, Lloh131
	.loh AdrpLdrGotLdr	Lloh126, Lloh127, Lloh128
	.loh AdrpLdrGotLdr	Lloh123, Lloh124, Lloh125
	.loh AdrpLdrGotLdr	Lloh120, Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.cfi_endproc
                                        ; -- End function
	.comm	_VIU_OSD1_CTRL_STAT,4,2         ; @VIU_OSD1_CTRL_STAT
	.comm	_VIU_OSD1_BLK0_CFG_W0,4,2       ; @VIU_OSD1_BLK0_CFG_W0
	.comm	_VIU_OSD1_BLK0_CFG_W1,4,2       ; @VIU_OSD1_BLK0_CFG_W1
	.comm	_VIU_OSD1_BLK0_CFG_W2,4,2       ; @VIU_OSD1_BLK0_CFG_W2
	.comm	_VIU_OSD1_BLK0_CFG_W3,4,2       ; @VIU_OSD1_BLK0_CFG_W3
	.comm	_VIU_OSD1_BLK0_CFG_W4,4,2       ; @VIU_OSD1_BLK0_CFG_W4
	.comm	_VPP_OSD_SC_CTRL0,4,2           ; @VPP_OSD_SC_CTRL0
	.comm	_VPP_OSD_SCI_WH_M1,4,2          ; @VPP_OSD_SCI_WH_M1
	.comm	_VPP_OSD_SCO_H_START_END,4,2    ; @VPP_OSD_SCO_H_START_END
	.comm	_VPP_OSD_SCO_V_START_END,4,2    ; @VPP_OSD_SCO_V_START_END
	.comm	_VPP_OSD_VSC_INI_PHASE,4,2      ; @VPP_OSD_VSC_INI_PHASE
	.comm	_VPP_OSD_VSC_PHASE_STEP,4,2     ; @VPP_OSD_VSC_PHASE_STEP
	.comm	_VPP_OSD_HSC_INI_PHASE,4,2      ; @VPP_OSD_HSC_INI_PHASE
	.comm	_VPP_OSD_HSC_PHASE_STEP,4,2     ; @VPP_OSD_HSC_PHASE_STEP
	.comm	_VPP_OSD_HSC_CTRL0,4,2          ; @VPP_OSD_HSC_CTRL0
	.comm	_VPP_OSD_VSC_CTRL0,4,2          ; @VPP_OSD_VSC_CTRL0
	.comm	_MESON_CANVAS_WRAP_NONE,4,2     ; @MESON_CANVAS_WRAP_NONE
	.comm	_MESON_CANVAS_BLKMODE_LINEAR,4,2 ; @MESON_CANVAS_BLKMODE_LINEAR
	.comm	_MESON_CANVAS_ENDIAN_SWAP64,4,2 ; @MESON_CANVAS_ENDIAN_SWAP64
	.comm	_VD1_IF0_GEN_REG,4,2            ; @VD1_IF0_GEN_REG
	.comm	_VD2_IF0_GEN_REG,4,2            ; @VD2_IF0_GEN_REG
	.comm	_VD1_IF0_GEN_REG2,4,2           ; @VD1_IF0_GEN_REG2
	.comm	_VIU_VD1_FMT_CTRL,4,2           ; @VIU_VD1_FMT_CTRL
	.comm	_VIU_VD2_FMT_CTRL,4,2           ; @VIU_VD2_FMT_CTRL
	.comm	_VIU_VD1_FMT_W,4,2              ; @VIU_VD1_FMT_W
	.comm	_VIU_VD2_FMT_W,4,2              ; @VIU_VD2_FMT_W
	.comm	_VD1_IF0_CANVAS0,4,2            ; @VD1_IF0_CANVAS0
	.comm	_VD1_IF0_CANVAS1,4,2            ; @VD1_IF0_CANVAS1
	.comm	_VD2_IF0_CANVAS0,4,2            ; @VD2_IF0_CANVAS0
	.comm	_VD2_IF0_CANVAS1,4,2            ; @VD2_IF0_CANVAS1
	.comm	_VD1_IF0_LUMA_X0,4,2            ; @VD1_IF0_LUMA_X0
	.comm	_VD1_IF0_LUMA_X1,4,2            ; @VD1_IF0_LUMA_X1
	.comm	_VD2_IF0_LUMA_X0,4,2            ; @VD2_IF0_LUMA_X0
	.comm	_VD2_IF0_LUMA_X1,4,2            ; @VD2_IF0_LUMA_X1
	.comm	_VD1_IF0_LUMA_Y0,4,2            ; @VD1_IF0_LUMA_Y0
	.comm	_VD1_IF0_LUMA_Y1,4,2            ; @VD1_IF0_LUMA_Y1
	.comm	_VD2_IF0_LUMA_Y0,4,2            ; @VD2_IF0_LUMA_Y0
	.comm	_VD2_IF0_LUMA_Y1,4,2            ; @VD2_IF0_LUMA_Y1
	.comm	_VD1_IF0_CHROMA_X0,4,2          ; @VD1_IF0_CHROMA_X0
	.comm	_VD1_IF0_CHROMA_X1,4,2          ; @VD1_IF0_CHROMA_X1
	.comm	_VD2_IF0_CHROMA_X0,4,2          ; @VD2_IF0_CHROMA_X0
	.comm	_VD2_IF0_CHROMA_X1,4,2          ; @VD2_IF0_CHROMA_X1
	.comm	_VD1_IF0_CHROMA_Y0,4,2          ; @VD1_IF0_CHROMA_Y0
	.comm	_VD1_IF0_CHROMA_Y1,4,2          ; @VD1_IF0_CHROMA_Y1
	.comm	_VD2_IF0_CHROMA_Y0,4,2          ; @VD2_IF0_CHROMA_Y0
	.comm	_VD2_IF0_CHROMA_Y1,4,2          ; @VD2_IF0_CHROMA_Y1
	.comm	_VD1_IF0_RPT_LOOP,4,2           ; @VD1_IF0_RPT_LOOP
	.comm	_VD2_IF0_RPT_LOOP,4,2           ; @VD2_IF0_RPT_LOOP
	.comm	_VD1_IF0_LUMA0_RPT_PAT,4,2      ; @VD1_IF0_LUMA0_RPT_PAT
	.comm	_VD2_IF0_LUMA0_RPT_PAT,4,2      ; @VD2_IF0_LUMA0_RPT_PAT
	.comm	_VD1_IF0_LUMA1_RPT_PAT,4,2      ; @VD1_IF0_LUMA1_RPT_PAT
	.comm	_VD2_IF0_LUMA1_RPT_PAT,4,2      ; @VD2_IF0_LUMA1_RPT_PAT
	.comm	_VD1_IF0_CHROMA0_RPT_PAT,4,2    ; @VD1_IF0_CHROMA0_RPT_PAT
	.comm	_VD2_IF0_CHROMA0_RPT_PAT,4,2    ; @VD2_IF0_CHROMA0_RPT_PAT
	.comm	_VD1_IF0_CHROMA1_RPT_PAT,4,2    ; @VD1_IF0_CHROMA1_RPT_PAT
	.comm	_VD2_IF0_CHROMA1_RPT_PAT,4,2    ; @VD2_IF0_CHROMA1_RPT_PAT
	.comm	_VD1_IF0_LUMA_PSEL,4,2          ; @VD1_IF0_LUMA_PSEL
	.comm	_VD1_IF0_CHROMA_PSEL,4,2        ; @VD1_IF0_CHROMA_PSEL
	.comm	_VD2_IF0_LUMA_PSEL,4,2          ; @VD2_IF0_LUMA_PSEL
	.comm	_VD2_IF0_CHROMA_PSEL,4,2        ; @VD2_IF0_CHROMA_PSEL
	.comm	_VD1_IF0_RANGE_MAP_Y,4,2        ; @VD1_IF0_RANGE_MAP_Y
	.comm	_VD1_IF0_RANGE_MAP_CB,4,2       ; @VD1_IF0_RANGE_MAP_CB
	.comm	_VD1_IF0_RANGE_MAP_CR,4,2       ; @VD1_IF0_RANGE_MAP_CR
	.comm	_VPP_SC_VD_EN_ENABLE,4,2        ; @VPP_SC_VD_EN_ENABLE
	.comm	_VPP_SC_TOP_EN_ENABLE,4,2       ; @VPP_SC_TOP_EN_ENABLE
	.comm	_VPP_SC_HSC_EN_ENABLE,4,2       ; @VPP_SC_HSC_EN_ENABLE
	.comm	_VPP_SC_VSC_EN_ENABLE,4,2       ; @VPP_SC_VSC_EN_ENABLE
	.comm	_VPP_SC_MISC,4,2                ; @VPP_SC_MISC
	.comm	_VPP_PIC_IN_HEIGHT,4,2          ; @VPP_PIC_IN_HEIGHT
	.comm	_VPP_POSTBLEND_VD1_H_START_END,4,2 ; @VPP_POSTBLEND_VD1_H_START_END
	.comm	_VPP_BLEND_VD2_H_START_END,4,2  ; @VPP_BLEND_VD2_H_START_END
	.comm	_VPP_POSTBLEND_VD1_V_START_END,4,2 ; @VPP_POSTBLEND_VD1_V_START_END
	.comm	_VPP_BLEND_VD2_V_START_END,4,2  ; @VPP_BLEND_VD2_V_START_END
	.comm	_VPP_HSC_REGION12_STARTP,4,2    ; @VPP_HSC_REGION12_STARTP
	.comm	_VPP_HSC_REGION34_STARTP,4,2    ; @VPP_HSC_REGION34_STARTP
	.comm	_VPP_HSC_REGION4_ENDP,4,2       ; @VPP_HSC_REGION4_ENDP
	.comm	_VPP_HSC_START_PHASE_STEP,4,2   ; @VPP_HSC_START_PHASE_STEP
	.comm	_VPP_HSC_REGION1_PHASE_SLOPE,4,2 ; @VPP_HSC_REGION1_PHASE_SLOPE
	.comm	_VPP_HSC_REGION3_PHASE_SLOPE,4,2 ; @VPP_HSC_REGION3_PHASE_SLOPE
	.comm	_VPP_LINE_IN_LENGTH,4,2         ; @VPP_LINE_IN_LENGTH
	.comm	_VPP_PREBLEND_H_SIZE,4,2        ; @VPP_PREBLEND_H_SIZE
	.comm	_VPP_VSC_REGION12_STARTP,4,2    ; @VPP_VSC_REGION12_STARTP
	.comm	_VPP_VSC_REGION34_STARTP,4,2    ; @VPP_VSC_REGION34_STARTP
	.comm	_VPP_VSC_REGION4_ENDP,4,2       ; @VPP_VSC_REGION4_ENDP
	.comm	_VPP_VSC_START_PHASE_STEP,4,2   ; @VPP_VSC_START_PHASE_STEP
	.comm	_VPP_VSC_INI_PHASE,4,2          ; @VPP_VSC_INI_PHASE
	.comm	_VPP_VSC_PHASE_CTRL,4,2         ; @VPP_VSC_PHASE_CTRL
	.comm	_VPP_HSC_PHASE_CTRL,4,2         ; @VPP_HSC_PHASE_CTRL
	.comm	_VPP_SCALE_COEF_IDX,4,2         ; @VPP_SCALE_COEF_IDX
.subsections_via_symbols
