	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ts73xx_fpga_write_init
_ts73xx_fpga_write_init:                ## @ts73xx_fpga_write_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	(%rdi), %rbx
	movq	_TS73XX_FPGA_CONFIG_REG@GOTPCREL(%rip), %r14
	movq	(%r14), %rsi
	addq	(%rbx), %rsi
	xorl	%edi, %edi
	callq	_writeb
	movq	_TS73XX_FPGA_RESET_LOW_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_udelay
	movq	_TS73XX_FPGA_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	(%r14), %rsi
	addq	(%rbx), %rsi
	callq	_writeb
	movq	_TS73XX_FPGA_RESET_HIGH_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_udelay
	xorl	%eax, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_TS73XX_FPGA_CONFIG_REG,8,3     ## @TS73XX_FPGA_CONFIG_REG
	.comm	_TS73XX_FPGA_RESET_LOW_DELAY,4,2 ## @TS73XX_FPGA_RESET_LOW_DELAY
	.comm	_TS73XX_FPGA_RESET,4,2          ## @TS73XX_FPGA_RESET
	.comm	_TS73XX_FPGA_RESET_HIGH_DELAY,4,2 ## @TS73XX_FPGA_RESET_HIGH_DELAY
	.no_dead_strip	_ts73xx_fpga_write_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ts73xx_fpga_write_init
_ts73xx_fpga_write_init:                ; @ts73xx_fpga_write_init
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	x19, [x0]
	ldr	x8, [x19]
Lloh0:
	adrp	x20, _TS73XX_FPGA_CONFIG_REG@GOTPAGE
Lloh1:
	ldr	x20, [x20, _TS73XX_FPGA_CONFIG_REG@GOTPAGEOFF]
	ldr	x9, [x20]
	add	x1, x9, x8
	mov	w0, #0
	bl	_writeb
Lloh2:
	adrp	x8, _TS73XX_FPGA_RESET_LOW_DELAY@GOTPAGE
Lloh3:
	ldr	x8, [x8, _TS73XX_FPGA_RESET_LOW_DELAY@GOTPAGEOFF]
Lloh4:
	ldr	w0, [x8]
	bl	_udelay
Lloh5:
	adrp	x8, _TS73XX_FPGA_RESET@GOTPAGE
Lloh6:
	ldr	x8, [x8, _TS73XX_FPGA_RESET@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
	ldr	x8, [x19]
	ldr	x9, [x20]
	add	x1, x9, x8
	bl	_writeb
Lloh8:
	adrp	x8, _TS73XX_FPGA_RESET_HIGH_DELAY@GOTPAGE
Lloh9:
	ldr	x8, [x8, _TS73XX_FPGA_RESET_HIGH_DELAY@GOTPAGEOFF]
Lloh10:
	ldr	w0, [x8]
	bl	_udelay
	mov	w0, #0
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_TS73XX_FPGA_CONFIG_REG,8,3     ; @TS73XX_FPGA_CONFIG_REG
	.comm	_TS73XX_FPGA_RESET_LOW_DELAY,4,2 ; @TS73XX_FPGA_RESET_LOW_DELAY
	.comm	_TS73XX_FPGA_RESET,4,2          ; @TS73XX_FPGA_RESET
	.comm	_TS73XX_FPGA_RESET_HIGH_DELAY,4,2 ; @TS73XX_FPGA_RESET_HIGH_DELAY
	.no_dead_strip	_ts73xx_fpga_write_init
.subsections_via_symbols
