	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dw_hdmi_phy_init
_dw_hdmi_phy_init:                      ## @dw_hdmi_phy_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r14
	movq	%rsi, %r15
	movq	%rdi, -64(%rbp)                 ## 8-byte Spill
	movq	8(%rsi), %r12
	movq	(%r12), %rbx
	movq	_VPU_HDMI_SETTING@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movq	%rbx, %rdi
	callq	_readl_relaxed
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movq	%r14, -48(%rbp)                 ## 8-byte Spill
	movl	4(%r14), %esi
	cmpl	$340001, (%r14)                 ## imm = 0x53021
	movl	$40, %eax
	movl	$10, %edx
	cmovgel	%eax, %edx
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG_DRIVER
	movl	16(%r12), %edi
	movq	_HHI_HDMI_CLK_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$65535, %edx                    ## imm = 0xFFFF
	movl	$256, %ecx                      ## imm = 0x100
	callq	_regmap_update_bits
	movl	16(%r12), %edi
	movq	_HHI_MEM_PD_REG0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%r13d, %r13d
	movl	$65280, %edx                    ## imm = 0xFF00
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movq	(%r15), %rax
	movq	_HDMITX_TOP_SW_RESET@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	*(%rax)
	movq	_HDMITX_TOP_CLK_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	$3, %edx
	movl	$3, %ecx
	callq	_dw_hdmi_top_write_bits
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	$48, %edx
	movl	$48, %ecx
	callq	_dw_hdmi_top_write_bits
	movq	(%r15), %rax
	movq	(%rax), %r14
	movq	_HDMITX_TOP_BIST_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$12, %edi
	callq	_BIT
	movq	%r15, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	*%r14
	movq	%r12, %r14
	movq	-48(%rbp), %r12                 ## 8-byte Reload
	cmpl	$340001, (%r12)                 ## imm = 0x53021
	movq	(%r15), %rax
	movq	_HDMITX_TOP_TMDS_CLK_PTTN_01@GOTPCREL(%rip), %rcx
	movl	$2031647, %edx                  ## imm = 0x1F001F
	cmovll	%edx, %r13d
	movl	(%rcx), %esi
	movl	$67044351, %ebx                 ## imm = 0x3FF03FF
	cmovll	%edx, %ebx
	movq	%r15, %rdi
	movl	%r13d, %edx
	callq	*(%rax)
	movq	(%r15), %rax
	movq	_HDMITX_TOP_TMDS_CLK_PTTN_23@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	*(%rax)
	movq	(%r15), %rax
	movq	_HDMITX_TOP_TMDS_CLK_PTTN_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	$1, %edx
	callq	*(%rax)
	movl	$20, %edi
	callq	_msleep
	movq	(%r15), %rax
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	$2, %edx
	callq	*(%rax)
	movq	%r15, %rdi
	movq	%r12, %rsi
	callq	_meson_hdmi_phy_setup_mode
	movl	16(%r14), %edi
	movq	_HHI_HDMI_PHY_CNTL1@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movl	$-65536, %edx                   ## imm = 0xFFFF0000
	movl	$59768832, %ecx                 ## imm = 0x3900000
	callq	_regmap_update_bits
	leaq	L_.str.1(%rip), %rsi
	movq	%r15, %rdi
	callq	_dw_hdmi_is_compatible
	testq	%rax, %rax
	jne	LBB0_3
## %bb.1:
	leaq	L_.str.2(%rip), %rsi
	movq	%r15, %rdi
	callq	_dw_hdmi_is_compatible
	testq	%rax, %rax
	jne	LBB0_3
## %bb.2:
	leaq	L_.str.3(%rip), %rsi
	movq	%r15, %rdi
	callq	_dw_hdmi_is_compatible
	testq	%rax, %rax
	je	LBB0_4
LBB0_3:
	movl	16(%r14), %ebx
	movl	(%r13), %r12d
	movl	$17, %edi
	callq	_BIT
	movl	%ebx, %edi
	movl	%r12d, %esi
	movl	%eax, %edx
	xorl	%ecx, %ecx
LBB0_5:
	callq	_regmap_update_bits
	movl	16(%r14), %edi
	movl	(%r13), %esi
	movl	$15, %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	callq	_dw_hdmi_set_high_tmds_clock_ratio
	movl	$100, %edi
	callq	_msleep
	movq	%r15, %rdi
	callq	_meson_dw_hdmi_phy_reset
	movq	%r15, %rdi
	callq	_meson_dw_hdmi_phy_reset
	movq	%r15, %rdi
	callq	_meson_dw_hdmi_phy_reset
	cmpq	$0, 8(%r14)
	movq	(%r14), %rbx
	movq	_ENCP_VIDEO_EN@GOTPCREL(%rip), %r15
	movq	_ENCI_VIDEO_EN@GOTPCREL(%rip), %r12
	movq	%r12, %rax
	cmoveq	%r15, %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	xorl	%edi, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	(%r14), %rbx
	movq	_VPU_HDMI_SETTING@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	$3, %edi
	xorl	%esi, %esi
	movq	%rbx, %rdx
	callq	_writel_bits_relaxed
	movq	(%r14), %rbx
	movl	(%r13), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	$3840, %edi                     ## imm = 0xF00
	xorl	%esi, %esi
	movq	%rbx, %rdx
	callq	_writel_bits_relaxed
	cmpq	$0, 8(%r14)
	movq	(%r14), %rbx
	cmoveq	%r15, %r12
	movl	(%r12), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	$1, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	-52(%rbp), %r15d                ## 4-byte Reload
	andl	$3840, %r15d                    ## imm = 0xF00
	movq	(%r14), %rbx
	movl	(%r13), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	$3840, %edi                     ## imm = 0xF00
	movl	%r15d, %esi
	movq	%rbx, %rdx
	callq	_writel_bits_relaxed
	cmpq	$0, 8(%r14)
	jne	LBB0_6
## %bb.7:
	movq	%r14, %rcx
	movq	_MESON_VENC_SOURCE_ENCP@GOTPCREL(%rip), %rax
	jmp	LBB0_8
LBB0_6:
	movq	%r14, %rcx
	movq	_MESON_VENC_SOURCE_ENCI@GOTPCREL(%rip), %rax
LBB0_8:
	movl	(%rax), %r14d
	movq	(%rcx), %rbx
	movl	(%r13), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	$3, %edi
	movl	%r14d, %esi
	movq	%rbx, %rdx
	callq	_writel_bits_relaxed
	xorl	%eax, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_4:
	movl	16(%r14), %eax
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movl	(%r13), %r12d
	movl	$17, %edi
	callq	_BIT
	movl	%eax, %ebx
	movl	$17, %edi
	callq	_BIT
	movl	-48(%rbp), %edi                 ## 4-byte Reload
	movl	%r12d, %esi
	movl	%ebx, %edx
	movl	%eax, %ecx
	jmp	LBB0_5
	.cfi_endproc
                                        ## -- End function
	.comm	_VPU_HDMI_SETTING,4,2           ## @VPU_HDMI_SETTING
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"\"%s\" div%d\n"

	.comm	_HHI_HDMI_CLK_CNTL,4,2          ## @HHI_HDMI_CLK_CNTL
	.comm	_HHI_MEM_PD_REG0,4,2            ## @HHI_MEM_PD_REG0
	.comm	_HDMITX_TOP_SW_RESET,4,2        ## @HDMITX_TOP_SW_RESET
	.comm	_HDMITX_TOP_CLK_CNTL,4,2        ## @HDMITX_TOP_CLK_CNTL
	.comm	_HDMITX_TOP_BIST_CNTL,4,2       ## @HDMITX_TOP_BIST_CNTL
	.comm	_HDMITX_TOP_TMDS_CLK_PTTN_01,4,2 ## @HDMITX_TOP_TMDS_CLK_PTTN_01
	.comm	_HDMITX_TOP_TMDS_CLK_PTTN_23,4,2 ## @HDMITX_TOP_TMDS_CLK_PTTN_23
	.comm	_HDMITX_TOP_TMDS_CLK_PTTN_CNTL,4,2 ## @HDMITX_TOP_TMDS_CLK_PTTN_CNTL
	.comm	_HHI_HDMI_PHY_CNTL1,4,2         ## @HHI_HDMI_PHY_CNTL1
L_.str.1:                               ## @.str.1
	.asciz	"amlogic,meson-gxl-dw-hdmi"

L_.str.2:                               ## @.str.2
	.asciz	"amlogic,meson-gxm-dw-hdmi"

L_.str.3:                               ## @.str.3
	.asciz	"amlogic,meson-g12a-dw-hdmi"

	.comm	_ENCI_VIDEO_EN,4,2              ## @ENCI_VIDEO_EN
	.comm	_ENCP_VIDEO_EN,4,2              ## @ENCP_VIDEO_EN
	.comm	_MESON_VENC_SOURCE_ENCI,4,2     ## @MESON_VENC_SOURCE_ENCI
	.comm	_MESON_VENC_SOURCE_ENCP,4,2     ## @MESON_VENC_SOURCE_ENCP
	.no_dead_strip	_dw_hdmi_phy_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dw_hdmi_phy_init
_dw_hdmi_phy_init:                      ; @dw_hdmi_phy_init
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x22, x2
	mov	x20, x1
	mov	x21, x0
	ldr	x25, [x1, #8]
	ldr	x19, [x25]
Lloh0:
	adrp	x26, _VPU_HDMI_SETTING@GOTPAGE
Lloh1:
	ldr	x26, [x26, _VPU_HDMI_SETTING@GOTPAGEOFF]
	ldr	w0, [x26]
	bl	__REG
	add	x0, x0, x19
	bl	_readl_relaxed
	mov	x19, x0
	ldp	w8, w1, [x22]
	mov	w24, #12320
	movk	w24, #5, lsl #16
	mov	w9, #10
	mov	w10, #40
	cmp	w8, w24
	csel	w2, w10, w9, gt
Lloh2:
	adrp	x0, l_.str@PAGE
Lloh3:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_DRIVER
	ldr	w0, [x25, #16]
Lloh4:
	adrp	x8, _HHI_HDMI_CLK_CNTL@GOTPAGE
Lloh5:
	ldr	x8, [x8, _HHI_HDMI_CLK_CNTL@GOTPAGEOFF]
Lloh6:
	ldr	w1, [x8]
	mov	w2, #65535
	mov	w3, #256
	bl	_regmap_update_bits
	ldr	w0, [x25, #16]
Lloh7:
	adrp	x8, _HHI_MEM_PD_REG0@GOTPAGE
Lloh8:
	ldr	x8, [x8, _HHI_MEM_PD_REG0@GOTPAGEOFF]
Lloh9:
	ldr	w1, [x8]
	mov	w2, #65280
	mov	w3, #0
	bl	_regmap_update_bits
	ldr	x8, [x20]
	ldr	x8, [x8]
Lloh10:
	adrp	x9, _HDMITX_TOP_SW_RESET@GOTPAGE
Lloh11:
	ldr	x9, [x9, _HDMITX_TOP_SW_RESET@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x9]
	mov	x0, x20
	mov	w2, #0
	blr	x8
Lloh13:
	adrp	x23, _HDMITX_TOP_CLK_CNTL@GOTPAGE
Lloh14:
	ldr	x23, [x23, _HDMITX_TOP_CLK_CNTL@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x20
	mov	w2, #3
	mov	w3, #3
	bl	_dw_hdmi_top_write_bits
	ldr	w1, [x23]
	mov	x0, x20
	mov	w2, #48
	mov	w3, #48
	bl	_dw_hdmi_top_write_bits
	ldr	x8, [x20]
	ldr	x27, [x8]
Lloh15:
	adrp	x8, _HDMITX_TOP_BIST_CNTL@GOTPAGE
Lloh16:
	ldr	x8, [x8, _HDMITX_TOP_BIST_CNTL@GOTPAGEOFF]
Lloh17:
	ldr	w23, [x8]
	mov	w0, #12
	bl	_BIT
	mov	x2, x0
	mov	x0, x20
	mov	x1, x23
	blr	x27
	ldr	w8, [x22]
	ldr	x9, [x20]
	ldr	x9, [x9]
Lloh18:
	adrp	x10, _HDMITX_TOP_TMDS_CLK_PTTN_01@GOTPAGE
Lloh19:
	ldr	x10, [x10, _HDMITX_TOP_TMDS_CLK_PTTN_01@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x10]
	mov	w10, #2031647
	cmp	w8, w24
	csel	w2, wzr, w10, gt
	mov	w8, #67044351
	csel	w23, w8, w10, gt
	mov	x0, x20
	blr	x9
	ldr	x8, [x20]
	ldr	x8, [x8]
Lloh21:
	adrp	x9, _HDMITX_TOP_TMDS_CLK_PTTN_23@GOTPAGE
Lloh22:
	ldr	x9, [x9, _HDMITX_TOP_TMDS_CLK_PTTN_23@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x9]
	mov	x0, x20
	mov	x2, x23
	blr	x8
	ldr	x8, [x20]
	ldr	x8, [x8]
Lloh24:
	adrp	x23, _HDMITX_TOP_TMDS_CLK_PTTN_CNTL@GOTPAGE
Lloh25:
	ldr	x23, [x23, _HDMITX_TOP_TMDS_CLK_PTTN_CNTL@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x20
	mov	w2, #1
	blr	x8
	mov	w0, #20
	bl	_msleep
	ldr	x8, [x20]
	ldr	x8, [x8]
	ldr	w1, [x23]
	mov	x0, x20
	mov	w2, #2
	blr	x8
	mov	x0, x20
	mov	x1, x22
	bl	_meson_hdmi_phy_setup_mode
	ldr	w0, [x25, #16]
Lloh26:
	adrp	x27, _HHI_HDMI_PHY_CNTL1@GOTPAGE
Lloh27:
	ldr	x27, [x27, _HHI_HDMI_PHY_CNTL1@GOTPAGEOFF]
	ldr	w1, [x27]
	mov	w2, #-65536
	mov	w3, #59768832
	bl	_regmap_update_bits
Lloh28:
	adrp	x1, l_.str.1@PAGE
Lloh29:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x20
	bl	_dw_hdmi_is_compatible
	cbnz	x0, LBB0_3
; %bb.1:
Lloh30:
	adrp	x1, l_.str.2@PAGE
Lloh31:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x0, x20
	bl	_dw_hdmi_is_compatible
	cbnz	x0, LBB0_3
; %bb.2:
Lloh32:
	adrp	x1, l_.str.3@PAGE
Lloh33:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x0, x20
	bl	_dw_hdmi_is_compatible
	cbz	x0, LBB0_5
LBB0_3:
	ldr	w22, [x25, #16]
	ldr	w23, [x27]
	mov	w0, #17
	bl	_BIT
	mov	x2, x0
	mov	x0, x22
	mov	x1, x23
	mov	w3, #0
LBB0_4:
	bl	_regmap_update_bits
	ldr	w0, [x25, #16]
	ldr	w1, [x27]
	mov	w2, #15
	mov	w3, #0
	bl	_regmap_update_bits
	mov	x0, x21
	bl	_dw_hdmi_set_high_tmds_clock_ratio
	mov	w0, #100
	bl	_msleep
	mov	x0, x20
	bl	_meson_dw_hdmi_phy_reset
	mov	x0, x20
	bl	_meson_dw_hdmi_phy_reset
	mov	x0, x20
	bl	_meson_dw_hdmi_phy_reset
Lloh34:
	adrp	x20, _ENCP_VIDEO_EN@GOTPAGE
Lloh35:
	ldr	x20, [x20, _ENCP_VIDEO_EN@GOTPAGEOFF]
	ldp	x21, x8, [x25]
Lloh36:
	adrp	x22, _ENCI_VIDEO_EN@GOTPAGE
Lloh37:
	ldr	x22, [x22, _ENCI_VIDEO_EN@GOTPAGEOFF]
	cmp	x8, #0
	csel	x8, x20, x22, eq
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x21
	mov	w0, #0
	bl	_writel_relaxed
	ldr	x21, [x25]
	ldr	w0, [x26]
	bl	__REG
	add	x2, x0, x21
	mov	w0, #3
	mov	w1, #0
	bl	_writel_bits_relaxed
	ldr	x21, [x25]
	ldr	w0, [x26]
	bl	__REG
	add	x2, x0, x21
	mov	w0, #3840
	mov	w1, #0
	bl	_writel_bits_relaxed
	ldp	x21, x8, [x25]
	cmp	x8, #0
	csel	x8, x20, x22, eq
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x21
	mov	w0, #1
	bl	_writel_relaxed
	and	w19, w19, #0xf00
	ldr	x20, [x25]
	ldr	w0, [x26]
	bl	__REG
	add	x2, x0, x20
	mov	w0, #3840
	mov	x1, x19
	bl	_writel_bits_relaxed
Lloh38:
	adrp	x8, _MESON_VENC_SOURCE_ENCP@GOTPAGE
Lloh39:
	ldr	x8, [x8, _MESON_VENC_SOURCE_ENCP@GOTPAGEOFF]
Lloh40:
	adrp	x9, _MESON_VENC_SOURCE_ENCI@GOTPAGE
Lloh41:
	ldr	x9, [x9, _MESON_VENC_SOURCE_ENCI@GOTPAGEOFF]
	ldp	x20, x10, [x25]
	cmp	x10, #0
	csel	x8, x8, x9, eq
	ldr	w19, [x8]
	ldr	w0, [x26]
	bl	__REG
	add	x2, x0, x20
	mov	w0, #3
	mov	x1, x19
	bl	_writel_bits_relaxed
	mov	w0, #0
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
LBB0_5:
	ldr	w22, [x25, #16]
	ldr	w23, [x27]
	mov	w0, #17
	bl	_BIT
	mov	x24, x0
	mov	w0, #17
	bl	_BIT
	mov	x3, x0
	mov	x0, x22
	mov	x1, x23
	mov	x2, x24
	b	LBB0_4
	.loh AdrpAdd	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh30, Lloh31
	.loh AdrpAdd	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh34, Lloh35
	.cfi_endproc
                                        ; -- End function
	.comm	_VPU_HDMI_SETTING,4,2           ; @VPU_HDMI_SETTING
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"\"%s\" div%d\n"

	.comm	_HHI_HDMI_CLK_CNTL,4,2          ; @HHI_HDMI_CLK_CNTL
	.comm	_HHI_MEM_PD_REG0,4,2            ; @HHI_MEM_PD_REG0
	.comm	_HDMITX_TOP_SW_RESET,4,2        ; @HDMITX_TOP_SW_RESET
	.comm	_HDMITX_TOP_CLK_CNTL,4,2        ; @HDMITX_TOP_CLK_CNTL
	.comm	_HDMITX_TOP_BIST_CNTL,4,2       ; @HDMITX_TOP_BIST_CNTL
	.comm	_HDMITX_TOP_TMDS_CLK_PTTN_01,4,2 ; @HDMITX_TOP_TMDS_CLK_PTTN_01
	.comm	_HDMITX_TOP_TMDS_CLK_PTTN_23,4,2 ; @HDMITX_TOP_TMDS_CLK_PTTN_23
	.comm	_HDMITX_TOP_TMDS_CLK_PTTN_CNTL,4,2 ; @HDMITX_TOP_TMDS_CLK_PTTN_CNTL
	.comm	_HHI_HDMI_PHY_CNTL1,4,2         ; @HHI_HDMI_PHY_CNTL1
l_.str.1:                               ; @.str.1
	.asciz	"amlogic,meson-gxl-dw-hdmi"

l_.str.2:                               ; @.str.2
	.asciz	"amlogic,meson-gxm-dw-hdmi"

l_.str.3:                               ; @.str.3
	.asciz	"amlogic,meson-g12a-dw-hdmi"

	.comm	_ENCI_VIDEO_EN,4,2              ; @ENCI_VIDEO_EN
	.comm	_ENCP_VIDEO_EN,4,2              ; @ENCP_VIDEO_EN
	.comm	_MESON_VENC_SOURCE_ENCI,4,2     ; @MESON_VENC_SOURCE_ENCI
	.comm	_MESON_VENC_SOURCE_ENCP,4,2     ; @MESON_VENC_SOURCE_ENCP
	.no_dead_strip	_dw_hdmi_phy_init
.subsections_via_symbols
