	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gtt_write_workarounds
_gtt_write_workarounds:                 ## @gtt_write_workarounds
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	(%rdi), %r14
	movq	8(%rdi), %rbx
	movq	%rbx, %rdi
	callq	_IS_BROADWELL
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	_GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW@GOTPCREL(%rip), %rax
	jmp	LBB0_8
LBB0_2:
	movq	%rbx, %rdi
	callq	_IS_CHERRYVIEW
	testq	%rax, %rax
	je	LBB0_4
## %bb.3:
	movq	_GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV@GOTPCREL(%rip), %rax
	jmp	LBB0_8
LBB0_4:
	movq	%rbx, %rdi
	callq	_IS_GEN9_LP
	testq	%rax, %rax
	je	LBB0_6
## %bb.5:
	movq	_GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT@GOTPCREL(%rip), %rax
	jmp	LBB0_8
LBB0_6:
	movq	%rbx, %rdi
	callq	_INTEL_GEN
	cmpl	$9, %eax
	jl	LBB0_9
## %bb.7:
	movq	_GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL@GOTPCREL(%rip), %rax
LBB0_8:
	movq	_GEN8_L3_LRA_1_GPGPU@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_intel_uncore_write
LBB0_9:
	movq	_I915_GTT_PAGE_SIZE_64K@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_HAS_PAGE_SIZES
	testq	%rax, %rax
	je	LBB0_12
## %bb.10:
	movq	%rbx, %rdi
	callq	_INTEL_GEN
	cmpl	$10, %eax
	jg	LBB0_12
## %bb.11:
	movq	_GEN8_GAMW_ECO_DEV_RW_IA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_GAMW_ECO_ENABLE_64K_IPS_FIELD@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	_intel_uncore_rmw
LBB0_12:
	movq	%rbx, %rdi
	movl	$8, %esi
	movl	$11, %edx
	callq	_IS_GEN_RANGE
	testq	%rax, %rax
	je	LBB0_18
## %bb.13:
	movq	_I915_GTT_PAGE_SIZE_2M@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_HAS_PAGE_SIZES
	movq	%rax, %rbx
	xorl	%r15d, %r15d
	movq	_HSW_GTT_CACHE_EN@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movl	$0, %edx
	testq	%rax, %rax
	jne	LBB0_15
## %bb.14:
	movq	_GTT_CACHE_EN_ALL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
LBB0_15:
	movq	%r14, %rdi
	callq	_intel_uncore_write
	testq	%rbx, %rbx
	jne	LBB0_17
## %bb.16:
	movl	(%r12), %esi
	movq	%r14, %rdi
	callq	_intel_uncore_read
	xorl	%r15d, %r15d
	testq	%rax, %rax
	sete	%r15b
LBB0_17:
	movl	%r15d, %edi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WARN_ON_ONCE                   ## TAILCALL
LBB0_18:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_GEN8_L3_LRA_1_GPGPU,4,2        ## @GEN8_L3_LRA_1_GPGPU
	.comm	_GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW,4,2 ## @GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW
	.comm	_GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV,4,2 ## @GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV
	.comm	_GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT,4,2 ## @GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT
	.comm	_GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL,4,2 ## @GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL
	.comm	_I915_GTT_PAGE_SIZE_64K,4,2     ## @I915_GTT_PAGE_SIZE_64K
	.comm	_GEN8_GAMW_ECO_DEV_RW_IA,4,2    ## @GEN8_GAMW_ECO_DEV_RW_IA
	.comm	_GAMW_ECO_ENABLE_64K_IPS_FIELD,4,2 ## @GAMW_ECO_ENABLE_64K_IPS_FIELD
	.comm	_I915_GTT_PAGE_SIZE_2M,4,2      ## @I915_GTT_PAGE_SIZE_2M
	.comm	_HSW_GTT_CACHE_EN,4,2           ## @HSW_GTT_CACHE_EN
	.comm	_GTT_CACHE_EN_ALL,4,2           ## @GTT_CACHE_EN_ALL
	.no_dead_strip	_gtt_write_workarounds
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gtt_write_workarounds
_gtt_write_workarounds:                 ; @gtt_write_workarounds
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	ldp	x19, x20, [x0]
	mov	x0, x20
	bl	_IS_BROADWELL
	cbz	x0, LBB0_2
; %bb.1:
Lloh0:
	adrp	x8, _GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW@GOTPAGE
Lloh1:
	ldr	x8, [x8, _GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW@GOTPAGEOFF]
	b	LBB0_8
LBB0_2:
	mov	x0, x20
	bl	_IS_CHERRYVIEW
	cbz	x0, LBB0_4
; %bb.3:
Lloh2:
	adrp	x8, _GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV@GOTPAGE
Lloh3:
	ldr	x8, [x8, _GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV@GOTPAGEOFF]
	b	LBB0_8
LBB0_4:
	mov	x0, x20
	bl	_IS_GEN9_LP
	cbz	x0, LBB0_6
; %bb.5:
Lloh4:
	adrp	x8, _GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT@GOTPAGE
Lloh5:
	ldr	x8, [x8, _GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT@GOTPAGEOFF]
	b	LBB0_8
LBB0_6:
	mov	x0, x20
	bl	_INTEL_GEN
	cmp	w0, #9
	b.lt	LBB0_9
; %bb.7:
Lloh6:
	adrp	x8, _GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL@GOTPAGEOFF]
LBB0_8:
Lloh8:
	adrp	x9, _GEN8_L3_LRA_1_GPGPU@GOTPAGE
Lloh9:
	ldr	x9, [x9, _GEN8_L3_LRA_1_GPGPU@GOTPAGEOFF]
Lloh10:
	ldr	w1, [x9]
	ldr	w2, [x8]
	mov	x0, x19
	bl	_intel_uncore_write
LBB0_9:
Lloh11:
	adrp	x8, _I915_GTT_PAGE_SIZE_64K@GOTPAGE
Lloh12:
	ldr	x8, [x8, _I915_GTT_PAGE_SIZE_64K@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_HAS_PAGE_SIZES
	cbz	x0, LBB0_12
; %bb.10:
	mov	x0, x20
	bl	_INTEL_GEN
	cmp	w0, #10
	b.gt	LBB0_12
; %bb.11:
Lloh14:
	adrp	x8, _GEN8_GAMW_ECO_DEV_RW_IA@GOTPAGE
Lloh15:
	ldr	x8, [x8, _GEN8_GAMW_ECO_DEV_RW_IA@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
Lloh17:
	adrp	x8, _GAMW_ECO_ENABLE_64K_IPS_FIELD@GOTPAGE
Lloh18:
	ldr	x8, [x8, _GAMW_ECO_ENABLE_64K_IPS_FIELD@GOTPAGEOFF]
Lloh19:
	ldr	w3, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_intel_uncore_rmw
LBB0_12:
	mov	x0, x20
	mov	w1, #8
	mov	w2, #11
	bl	_IS_GEN_RANGE
	cbz	x0, LBB0_16
; %bb.13:
Lloh20:
	adrp	x8, _I915_GTT_PAGE_SIZE_2M@GOTPAGE
Lloh21:
	ldr	x8, [x8, _I915_GTT_PAGE_SIZE_2M@GOTPAGEOFF]
Lloh22:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_HAS_PAGE_SIZES
	mov	x20, x0
Lloh23:
	adrp	x21, _HSW_GTT_CACHE_EN@GOTPAGE
Lloh24:
	ldr	x21, [x21, _HSW_GTT_CACHE_EN@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh25:
	adrp	x8, _GTT_CACHE_EN_ALL@GOTPAGE
Lloh26:
	ldr	x8, [x8, _GTT_CACHE_EN_ALL@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
	cmp	x0, #0
	csel	w2, w8, wzr, eq
	mov	x0, x19
	bl	_intel_uncore_write
	mov	w0, #0
	cbnz	x20, LBB0_15
; %bb.14:
	ldr	w1, [x21]
	mov	x0, x19
	bl	_intel_uncore_read
	cmp	x0, #0
	cset	w0, eq
LBB0_15:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WARN_ON_ONCE
LBB0_16:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.cfi_endproc
                                        ; -- End function
	.comm	_GEN8_L3_LRA_1_GPGPU,4,2        ; @GEN8_L3_LRA_1_GPGPU
	.comm	_GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW,4,2 ; @GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW
	.comm	_GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV,4,2 ; @GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV
	.comm	_GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT,4,2 ; @GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT
	.comm	_GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL,4,2 ; @GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL
	.comm	_I915_GTT_PAGE_SIZE_64K,4,2     ; @I915_GTT_PAGE_SIZE_64K
	.comm	_GEN8_GAMW_ECO_DEV_RW_IA,4,2    ; @GEN8_GAMW_ECO_DEV_RW_IA
	.comm	_GAMW_ECO_ENABLE_64K_IPS_FIELD,4,2 ; @GAMW_ECO_ENABLE_64K_IPS_FIELD
	.comm	_I915_GTT_PAGE_SIZE_2M,4,2      ; @I915_GTT_PAGE_SIZE_2M
	.comm	_HSW_GTT_CACHE_EN,4,2           ; @HSW_GTT_CACHE_EN
	.comm	_GTT_CACHE_EN_ALL,4,2           ; @GTT_CACHE_EN_ALL
	.no_dead_strip	_gtt_write_workarounds
.subsections_via_symbols
