	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function zynq_fpga_ops_state
_zynq_fpga_ops_state:                   ## @zynq_fpga_ops_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	(%rdi), %rbx
	movl	(%rbx), %edi
	callq	_clk_enable
	testl	%eax, %eax
	jne	LBB0_3
## %bb.1:
	movq	_INT_STS_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_zynq_fpga_read
	movl	%eax, %r14d
	movl	(%rbx), %edi
	callq	_clk_disable
	movq	_IXR_PCFG_DONE_MASK@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	jne	LBB0_2
LBB0_3:
	movq	_FPGA_MGR_STATE_UNKNOWN@GOTPCREL(%rip), %rax
	jmp	LBB0_4
LBB0_2:
	movq	_FPGA_MGR_STATE_OPERATING@GOTPCREL(%rip), %rax
LBB0_4:
	movl	(%rax), %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_FPGA_MGR_STATE_UNKNOWN,4,2     ## @FPGA_MGR_STATE_UNKNOWN
	.comm	_INT_STS_OFFSET,4,2             ## @INT_STS_OFFSET
	.comm	_IXR_PCFG_DONE_MASK,4,2         ## @IXR_PCFG_DONE_MASK
	.comm	_FPGA_MGR_STATE_OPERATING,4,2   ## @FPGA_MGR_STATE_OPERATING
	.no_dead_strip	_zynq_fpga_ops_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function zynq_fpga_ops_state
_zynq_fpga_ops_state:                   ; @zynq_fpga_ops_state
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	ldr	x19, [x0]
	ldr	w0, [x19]
	bl	_clk_enable
Lloh0:
	adrp	x21, _FPGA_MGR_STATE_UNKNOWN@GOTPAGE
Lloh1:
	ldr	x21, [x21, _FPGA_MGR_STATE_UNKNOWN@GOTPAGEOFF]
	cbnz	w0, LBB0_2
; %bb.1:
Lloh2:
	adrp	x8, _INT_STS_OFFSET@GOTPAGE
Lloh3:
	ldr	x8, [x8, _INT_STS_OFFSET@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_zynq_fpga_read
	mov	x20, x0
	ldr	w0, [x19]
	bl	_clk_disable
Lloh5:
	adrp	x8, _IXR_PCFG_DONE_MASK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _IXR_PCFG_DONE_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
Lloh8:
	adrp	x9, _FPGA_MGR_STATE_OPERATING@GOTPAGE
Lloh9:
	ldr	x9, [x9, _FPGA_MGR_STATE_OPERATING@GOTPAGEOFF]
	tst	w8, w20
	csel	x21, x21, x9, eq
LBB0_2:
	ldr	w0, [x21]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_FPGA_MGR_STATE_UNKNOWN,4,2     ; @FPGA_MGR_STATE_UNKNOWN
	.comm	_INT_STS_OFFSET,4,2             ; @INT_STS_OFFSET
	.comm	_IXR_PCFG_DONE_MASK,4,2         ; @IXR_PCFG_DONE_MASK
	.comm	_FPGA_MGR_STATE_OPERATING,4,2   ; @FPGA_MGR_STATE_OPERATING
	.no_dead_strip	_zynq_fpga_ops_state
.subsections_via_symbols
