	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vi_set_uvd_clocks
_vi_set_uvd_clocks:                     ## @vi_set_uvd_clocks
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movl	%edx, %r14d
	movq	%rdi, %rbx
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rdi)
	je	LBB0_3
## %bb.1:
	movq	_ixGNB_CLK2_DFS_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_ixGNB_CLK2_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	callq	_vi_set_uvd_clock
	testl	%eax, %eax
	jne	LBB0_7
## %bb.2:
	movq	_ixGNB_CLK1_DFS_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_ixGNB_CLK1_STATUS@GOTPCREL(%rip), %rax
	jmp	LBB0_5
LBB0_3:
	movq	_ixCG_VCLK_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_ixCG_VCLK_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	callq	_vi_set_uvd_clock
	testl	%eax, %eax
	jne	LBB0_7
## %bb.4:
	movq	_ixCG_DCLK_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_ixCG_DCLK_STATUS@GOTPCREL(%rip), %rax
LBB0_5:
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_vi_set_uvd_clock
	testl	%eax, %eax
	jne	LBB0_7
## %bb.6:
	xorl	%eax, %eax
LBB0_7:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_ixGNB_CLK2_DFS_CNTL,4,2        ## @ixGNB_CLK2_DFS_CNTL
	.comm	_ixGNB_CLK2_STATUS,4,2          ## @ixGNB_CLK2_STATUS
	.comm	_ixGNB_CLK1_DFS_CNTL,4,2        ## @ixGNB_CLK1_DFS_CNTL
	.comm	_ixGNB_CLK1_STATUS,4,2          ## @ixGNB_CLK1_STATUS
	.comm	_ixCG_VCLK_CNTL,4,2             ## @ixCG_VCLK_CNTL
	.comm	_ixCG_VCLK_STATUS,4,2           ## @ixCG_VCLK_STATUS
	.comm	_ixCG_DCLK_CNTL,4,2             ## @ixCG_DCLK_CNTL
	.comm	_ixCG_DCLK_STATUS,4,2           ## @ixCG_DCLK_STATUS
	.no_dead_strip	_vi_set_uvd_clocks
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vi_set_uvd_clocks
_vi_set_uvd_clocks:                     ; @vi_set_uvd_clocks
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x2
	mov	x20, x0
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _AMD_IS_APU@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_IS_APU@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_3
; %bb.1:
Lloh3:
	adrp	x8, _ixGNB_CLK2_DFS_CNTL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _ixGNB_CLK2_DFS_CNTL@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
Lloh6:
	adrp	x8, _ixGNB_CLK2_STATUS@GOTPAGE
Lloh7:
	ldr	x8, [x8, _ixGNB_CLK2_STATUS@GOTPAGEOFF]
Lloh8:
	ldr	w3, [x8]
	mov	x0, x20
	bl	_vi_set_uvd_clock
	cbnz	w0, LBB0_7
; %bb.2:
Lloh9:
	adrp	x8, _ixGNB_CLK1_DFS_CNTL@GOTPAGE
Lloh10:
	ldr	x8, [x8, _ixGNB_CLK1_DFS_CNTL@GOTPAGEOFF]
Lloh11:
	ldr	w2, [x8]
Lloh12:
	adrp	x8, _ixGNB_CLK1_STATUS@GOTPAGE
Lloh13:
	ldr	x8, [x8, _ixGNB_CLK1_STATUS@GOTPAGEOFF]
	b	LBB0_5
LBB0_3:
Lloh14:
	adrp	x8, _ixCG_VCLK_CNTL@GOTPAGE
Lloh15:
	ldr	x8, [x8, _ixCG_VCLK_CNTL@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
Lloh17:
	adrp	x8, _ixCG_VCLK_STATUS@GOTPAGE
Lloh18:
	ldr	x8, [x8, _ixCG_VCLK_STATUS@GOTPAGEOFF]
Lloh19:
	ldr	w3, [x8]
	mov	x0, x20
	bl	_vi_set_uvd_clock
	cbnz	w0, LBB0_7
; %bb.4:
Lloh20:
	adrp	x8, _ixCG_DCLK_CNTL@GOTPAGE
Lloh21:
	ldr	x8, [x8, _ixCG_DCLK_CNTL@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
Lloh23:
	adrp	x8, _ixCG_DCLK_STATUS@GOTPAGE
Lloh24:
	ldr	x8, [x8, _ixCG_DCLK_STATUS@GOTPAGEOFF]
LBB0_5:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	bl	_vi_set_uvd_clock
	cbnz	w0, LBB0_7
; %bb.6:
	mov	w0, #0
LBB0_7:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_ixGNB_CLK2_DFS_CNTL,4,2        ; @ixGNB_CLK2_DFS_CNTL
	.comm	_ixGNB_CLK2_STATUS,4,2          ; @ixGNB_CLK2_STATUS
	.comm	_ixGNB_CLK1_DFS_CNTL,4,2        ; @ixGNB_CLK1_DFS_CNTL
	.comm	_ixGNB_CLK1_STATUS,4,2          ; @ixGNB_CLK1_STATUS
	.comm	_ixCG_VCLK_CNTL,4,2             ; @ixCG_VCLK_CNTL
	.comm	_ixCG_VCLK_STATUS,4,2           ; @ixCG_VCLK_STATUS
	.comm	_ixCG_DCLK_CNTL,4,2             ; @ixCG_DCLK_CNTL
	.comm	_ixCG_DCLK_STATUS,4,2           ; @ixCG_DCLK_STATUS
	.no_dead_strip	_vi_set_uvd_clocks
.subsections_via_symbols
