	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function uvd_v7_0_sriov_start
_uvd_v7_0_sriov_start:                  ## @uvd_v7_0_sriov_start
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	$0, -72(%rbp)
	movq	%rdi, -56(%rbp)                 ## 8-byte Spill
	movq	(%rdi), %rsi
	movq	_MMSCH_COMMAND__END@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -72(%rbp)
	cmpl	$0, (%rsi)
	jne	LBB0_11
## %bb.1:
	cmpq	$0, 8(%rsi)
	jne	LBB0_11
## %bb.2:
	movq	_MMSCH_VERSION@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 28(%rsi)
	movl	$8, 16(%rsi)
	movl	20(%rsi), %eax
	movl	24(%rsi), %ecx
	leal	(%rcx,%rax), %edx
	orl	%ecx, %eax
	movl	$8, %eax
	cmovnel	%edx, %eax
	movl	%eax, (%rsi)
	cltq
	movq	%rsi, -88(%rbp)                 ## 8-byte Spill
	leaq	(%rsi,%rax,4), %rax
	movq	%rax, -80(%rbp)                 ## 8-byte Spill
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	8(%rax), %eax
	testl	%eax, %eax
	jle	LBB0_10
## %bb.3:
	xorl	%ebx, %ebx
	movq	_UVD@GOTPCREL(%rip), %r14
	xorl	%r15d, %r15d
	jmp	LBB0_4
LBB0_7:                                 ##   in Loop: Header=BB0_4 Depth=1
	movq	-56(%rbp), %r14                 ## 8-byte Reload
	movq	24(%r14), %rax
	movl	(%rax,%rcx), %edi
	movq	%rcx, %r13
	movq	%rdx, %r12
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r12), %edi
	movq	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %ebx
	movq	24(%r14), %rax
	movl	(%rax,%r13), %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movq	%r12, %r14
	movl	(%r12), %edi
	movq	_mmUVD_VCPU_CACHE_OFFSET0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_AMDGPU_UVD_FIRMWARE_OFFSET@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	sarl	$3, %esi
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	-44(%rbp), %r12d                ## 4-byte Reload
	movl	%r12d, %r13d
LBB0_8:                                 ##   in Loop: Header=BB0_4 Depth=1
	movq	%r14, %rbx
	movl	(%r14), %edi
	movq	_mmUVD_VCPU_CACHE_SIZE0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	%r12d, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r14), %edi
	movq	%r14, %r12
	movq	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	-56(%rbp), %r14                 ## 8-byte Reload
	movq	24(%r14), %rax
	movq	-64(%rbp), %rcx                 ## 8-byte Reload
	movl	(%rax,%rcx), %edi
	movq	%rcx, %rbx
	addl	%r13d, %edi
	callq	_lower_32_bits
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	movl	%eax, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r12), %edi
	movq	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %r12d
	movq	24(%r14), %rax
	movl	(%rax,%rbx), %edi
	addl	%r13d, %edi
	callq	_upper_32_bits
	movl	%r12d, %edi
	movl	%eax, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movq	_UVD@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movq	_mmUVD_VCPU_CACHE_OFFSET1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	$2097152, %esi                  ## imm = 0x200000
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r14), %edi
	movq	_mmUVD_VCPU_CACHE_SIZE1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_AMDGPU_UVD_HEAP_SIZE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r14), %edi
	movq	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movq	24(%rbx), %rax
	movq	-64(%rbp), %r12                 ## 8-byte Reload
	movl	(%rax,%r12), %edi
	addl	%r13d, %edi
	movq	_AMDGPU_UVD_HEAP_SIZE@GOTPCREL(%rip), %rax
	addl	(%rax), %edi
	callq	_lower_32_bits
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	movl	%eax, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r14), %edi
	movq	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %r14d
	movq	24(%rbx), %rax
	addl	(%rax,%r12), %r13d
	movq	_AMDGPU_UVD_HEAP_SIZE@GOTPCREL(%rip), %rax
	addl	(%rax), %r13d
	movl	%r13d, %edi
	callq	_upper_32_bits
	movl	%r14d, %edi
	movl	%eax, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movq	_UVD@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movq	_mmUVD_VCPU_CACHE_OFFSET2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	$4194304, %esi                  ## imm = 0x400000
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r14), %edi
	movq	_mmUVD_VCPU_CACHE_SIZE2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_AMDGPU_UVD_SESSION_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	leal	(%rcx,%rcx,4), %esi
	shll	$3, %esi
	movq	_AMDGPU_UVD_STACK_SIZE@GOTPCREL(%rip), %rcx
	addl	(%rcx), %esi
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r14), %edi
	movq	_mmUVD_GP_SCRATCH4@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movl	16(%rbx), %esi
	movq	%rbx, %r13
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r14), %edi
	movq	_mmUVD_CGC_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	movl	%eax, %edi
	xorl	%edx, %edx
	callq	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	movl	(%r14), %edi
	movq	_mmUVD_MASTINT_EN@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_MASTINT_EN__VCPU_EN_MASK@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	notl	%esi
	movl	%eax, %edi
	xorl	%edx, %edx
	callq	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	movl	(%r14), %edi
	movq	_mmUVD_LMI_CTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%edx, %esi
	notl	%esi
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	movl	(%r14), %edi
	movq	_mmUVD_SOFT_RESET@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_SOFT_RESET__RBC_SOFT_RESET_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_SOFT_RESET__CSM_SOFT_RESET_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_SOFT_RESET__CXW_SOFT_RESET_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_SOFT_RESET__TAP_SOFT_RESET_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r14), %edi
	movq	_mmUVD_LMI_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT@GOTPCREL(%rip), %rcx
	movzbl	(%rcx), %ecx
	movl	$64, %esi
	shll	%cl, %esi
	movq	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_LMI_CTRL__REQ_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	orl	$1048576, %esi                  ## imm = 0x100000
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r14), %edi
	movl	(%r12), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%rbx), %esi
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r14), %edi
	movq	_mmUVD_VCPU_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_VCPU_CNTL__CLK_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r14), %edi
	movq	_mmUVD_MASTINT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_MASTINT_EN__SYS_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_UVD_MASTINT_EN__VCPU_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movl	%edx, %esi
	notl	%esi
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	movl	(%r14), %edi
	movq	_mmUVD_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_STATUS__VCPU_REPORT__SHIFT@GOTPCREL(%rip), %rcx
	movzbl	(%rcx), %ecx
	movl	$2, %esi
	shll	%cl, %esi
	notl	%esi
	movl	%eax, %edi
	xorl	%edx, %edx
	callq	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	movq	-96(%rbp), %rax                 ## 8-byte Reload
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	movl	16(%rax,%rbx), %edi
	callq	_order_base_2
	movq	_UVD_RBC_RB_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	_RB_BUFSZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%edi, %edi
	movl	%eax, %ecx
	callq	_REG_SET_FIELD
	movl	(%r12), %esi
	movq	_RB_NO_FETCH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	%eax, %r12d
	movl	(%r14), %edi
	movq	_mmUVD_RBC_RB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	%r12d, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movq	24(%r13), %rax
	movq	8(%rax,%rbx), %r13
	movq	$0, 8(%r13)
	movl	(%r14), %edi
	movq	_mmUVD_RB_BASE_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movl	4(%r13), %esi
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r14), %edi
	movq	_mmUVD_RB_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %r12d
	movl	4(%r13), %edi
	callq	_upper_32_bits
	movl	%r12d, %edi
	movl	%eax, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r14), %edi
	movq	_mmUVD_RB_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r13), %ecx
	leal	3(%rcx), %esi
	testl	%ecx, %ecx
	cmovnsl	%ecx, %esi
	sarl	$2, %esi
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r14), %edi
	movq	_mmUVD_SOFT_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r14), %edi
	movq	_mmUVD_LMI_CTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	movl	%eax, %edi
	xorl	%edx, %edx
	callq	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	movl	(%r14), %edi
	movq	_mmUVD_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	$2, %esi
	movl	$2, %edx
	callq	_MMSCH_V1_0_INSERT_DIRECT_POLL
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	8(%rax), %eax
LBB0_9:                                 ##   in Loop: Header=BB0_4 Depth=1
	incq	%r15
	movslq	%eax, %rcx
	addq	$32, %rbx
	cmpq	%rcx, %r15
	jge	LBB0_10
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	movl	12(%rcx), %ecx
	btl	%r15d, %ecx
	jb	LBB0_9
## %bb.5:                               ##   in Loop: Header=BB0_4 Depth=1
	movq	-56(%rbp), %r12                 ## 8-byte Reload
	movq	24(%r12), %rax
	movq	%rax, -96(%rbp)                 ## 8-byte Spill
	movq	$0, 24(%rax,%rbx)
	movq	32(%r12), %rax
	movq	(%rax), %rdi
	addq	$4, %rdi
	callq	_AMDGPU_GPU_PAGE_ALIGN
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movl	(%r14), %edi
	movq	_mmUVD_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	$-1, %esi
	movl	$4, %edx
	callq	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	movq	40(%r12), %r13
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rax
	movq	(%rax), %r12
	movl	(%r14), %edi
	movq	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	%r14, %rdx
	movq	%rbx, %rcx
	movl	%eax, %ebx
	cmpq	%r12, %r13
	movq	%rcx, -64(%rbp)                 ## 8-byte Spill
	jne	LBB0_7
## %bb.6:                               ##   in Loop: Header=BB0_4 Depth=1
	movq	-56(%rbp), %r14                 ## 8-byte Reload
	movq	48(%r14), %rax
	movq	_AMDGPU_UCODE_ID_UVD@GOTPCREL(%rip), %r12
	movq	(%r12), %rcx
	movl	(%rax,%rcx,8), %esi
	movl	%ebx, %edi
	movq	%rdx, %rbx
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%rbx), %edi
	movq	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	48(%r14), %rcx
	movq	(%r12), %rdx
	movl	4(%rcx,%rdx,8), %esi
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movq	%rbx, %r14
	movl	(%rbx), %edi
	movq	_mmUVD_VCPU_CACHE_OFFSET0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%r13d, %r13d
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	-44(%rbp), %r12d                ## 4-byte Reload
	jmp	LBB0_8
LBB0_10:
	leaq	-72(%rbp), %rsi
	movq	-80(%rbp), %rdi                 ## 8-byte Reload
	movl	$8, %edx
	callq	_memcpy
	movq	-88(%rbp), %rax                 ## 8-byte Reload
	movq	$2, 8(%rax)
LBB0_11:
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	movq	%rdi, %rsi
	callq	_uvd_v7_0_mmsch_start
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MMSCH_COMMAND__DIRECT_REG_WRITE,4,2 ## @MMSCH_COMMAND__DIRECT_REG_WRITE
	.comm	_MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE,4,2 ## @MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE
	.comm	_MMSCH_COMMAND__DIRECT_REG_POLLING,4,2 ## @MMSCH_COMMAND__DIRECT_REG_POLLING
	.comm	_MMSCH_COMMAND__END,4,2         ## @MMSCH_COMMAND__END
	.comm	_MMSCH_VERSION,4,2              ## @MMSCH_VERSION
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_STATUS,4,2               ## @mmUVD_STATUS
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
	.comm	_AMDGPU_UCODE_ID_UVD,8,3        ## @AMDGPU_UCODE_ID_UVD
	.comm	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET0,4,2   ## @mmUVD_VCPU_CACHE_OFFSET0
	.comm	_AMDGPU_UVD_FIRMWARE_OFFSET,4,2 ## @AMDGPU_UVD_FIRMWARE_OFFSET
	.comm	_mmUVD_VCPU_CACHE_SIZE0,4,2     ## @mmUVD_VCPU_CACHE_SIZE0
	.comm	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET1,4,2   ## @mmUVD_VCPU_CACHE_OFFSET1
	.comm	_mmUVD_VCPU_CACHE_SIZE1,4,2     ## @mmUVD_VCPU_CACHE_SIZE1
	.comm	_AMDGPU_UVD_HEAP_SIZE,4,2       ## @AMDGPU_UVD_HEAP_SIZE
	.comm	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET2,4,2   ## @mmUVD_VCPU_CACHE_OFFSET2
	.comm	_mmUVD_VCPU_CACHE_SIZE2,4,2     ## @mmUVD_VCPU_CACHE_SIZE2
	.comm	_AMDGPU_UVD_STACK_SIZE,4,2      ## @AMDGPU_UVD_STACK_SIZE
	.comm	_AMDGPU_UVD_SESSION_SIZE,4,2    ## @AMDGPU_UVD_SESSION_SIZE
	.comm	_mmUVD_GP_SCRATCH4,4,2          ## @mmUVD_GP_SCRATCH4
	.comm	_mmUVD_CGC_CTRL,4,2             ## @mmUVD_CGC_CTRL
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK,4,2 ## @UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK
	.comm	_mmUVD_MASTINT_EN,4,2           ## @mmUVD_MASTINT_EN
	.comm	_UVD_MASTINT_EN__VCPU_EN_MASK,4,2 ## @UVD_MASTINT_EN__VCPU_EN_MASK
	.comm	_mmUVD_LMI_CTRL2,4,2            ## @mmUVD_LMI_CTRL2
	.comm	_UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,4,2 ## @UVD_LMI_CTRL2__STALL_ARB_UMC_MASK
	.comm	_mmUVD_SOFT_RESET,4,2           ## @mmUVD_SOFT_RESET
	.comm	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__RBC_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__RBC_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__CSM_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__CSM_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__CXW_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__CXW_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__TAP_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__TAP_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
	.comm	_mmUVD_LMI_CTRL,4,2             ## @mmUVD_LMI_CTRL
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT,4,2 ## @UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK,4,2 ## @UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK
	.comm	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK,4,2 ## @UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK,4,2 ## @UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__REQ_MODE_MASK,4,2 ## @UVD_LMI_CTRL__REQ_MODE_MASK
	.comm	_mmUVD_VCPU_CNTL,4,2            ## @mmUVD_VCPU_CNTL
	.comm	_UVD_VCPU_CNTL__CLK_EN_MASK,4,2 ## @UVD_VCPU_CNTL__CLK_EN_MASK
	.comm	_UVD_MASTINT_EN__SYS_EN_MASK,4,2 ## @UVD_MASTINT_EN__SYS_EN_MASK
	.comm	_UVD_STATUS__VCPU_REPORT__SHIFT,4,2 ## @UVD_STATUS__VCPU_REPORT__SHIFT
	.comm	_UVD_RBC_RB_CNTL,4,2            ## @UVD_RBC_RB_CNTL
	.comm	_RB_BUFSZ,4,2                   ## @RB_BUFSZ
	.comm	_RB_NO_FETCH,4,2                ## @RB_NO_FETCH
	.comm	_mmUVD_RBC_RB_CNTL,4,2          ## @mmUVD_RBC_RB_CNTL
	.comm	_mmUVD_RB_BASE_LO,4,2           ## @mmUVD_RB_BASE_LO
	.comm	_mmUVD_RB_BASE_HI,4,2           ## @mmUVD_RB_BASE_HI
	.comm	_mmUVD_RB_SIZE,4,2              ## @mmUVD_RB_SIZE
	.no_dead_strip	_uvd_v7_0_sriov_start
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function uvd_v7_0_sriov_start
_uvd_v7_0_sriov_start:                  ; @uvd_v7_0_sriov_start
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #128
	.cfi_def_cfa_offset 128
	stp	x28, x27, [sp, #32]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #48]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #64]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #80]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #96]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #112]            ; 16-byte Folded Spill
	add	x29, sp, #112
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	str	xzr, [sp, #24]
	ldr	x12, [x0]
Lloh0:
	adrp	x8, _MMSCH_COMMAND__END@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MMSCH_COMMAND__END@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	str	w8, [sp, #24]
	ldr	w8, [x12]
	cbnz	w8, LBB0_11
; %bb.1:
	ldr	x8, [x12, #8]
	cbnz	x8, LBB0_11
; %bb.2:
Lloh3:
	adrp	x8, _MMSCH_VERSION@GOTPAGE
Lloh4:
	ldr	x8, [x8, _MMSCH_VERSION@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	str	w8, [x12, #28]
	mov	w8, #8
	str	w8, [x12, #16]
	ldp	w9, w10, [x12, #20]
	orr	w11, w9, w10
	add	w9, w10, w9
	cmp	w11, #0
	csel	w8, w8, w9, eq
	str	w8, [x12]
	add	x8, x12, w8, sxtw #2
	stp	x12, x8, [sp, #8]               ; 16-byte Folded Spill
	ldr	w8, [x19, #8]
	cmp	w8, #1
	b.lt	LBB0_10
; %bb.3:
	mov	x25, #0
	mov	x21, #0
Lloh6:
	adrp	x26, _UVD@GOTPAGE
Lloh7:
	ldr	x26, [x26, _UVD@GOTPAGEOFF]
Lloh8:
	adrp	x28, _mmUVD_STATUS@GOTPAGE
Lloh9:
	ldr	x28, [x28, _mmUVD_STATUS@GOTPAGEOFF]
	b	LBB0_7
LBB0_4:                                 ;   in Loop: Header=BB0_7 Depth=1
	ldr	x8, [x19, #24]
	ldr	w0, [x8, x25]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x23
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
Lloh10:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPAGE
Lloh11:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh12:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
	mov	x23, x0
	ldr	x8, [x19, #24]
	ldr	w0, [x8, x25]
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x23
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
Lloh13:
	adrp	x8, _mmUVD_VCPU_CACHE_OFFSET0@GOTPAGE
Lloh14:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_OFFSET0@GOTPAGEOFF]
Lloh15:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh16:
	adrp	x8, _AMDGPU_UVD_FIRMWARE_OFFSET@GOTPAGE
Lloh17:
	ldr	x8, [x8, _AMDGPU_UVD_FIRMWARE_OFFSET@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	asr	w1, w8, #3
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	mov	x23, x22
LBB0_5:                                 ;   in Loop: Header=BB0_7 Depth=1
	mov	x28, x24
	ldr	w0, [x26]
Lloh19:
	adrp	x8, _mmUVD_VCPU_CACHE_SIZE0@GOTPAGE
Lloh20:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_SIZE0@GOTPAGEOFF]
Lloh21:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
	mov	x1, x22
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
Lloh22:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW@GOTPAGE
Lloh23:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh24:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
	mov	x22, x0
	ldr	x8, [x19, #24]
	ldr	w8, [x8, x25]
	add	w0, w8, w23
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x22
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
Lloh25:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH@GOTPAGE
Lloh26:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh27:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
	mov	x22, x0
	ldr	x8, [x19, #24]
	ldr	w8, [x8, x25]
	add	w0, w8, w23
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x22
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
Lloh28:
	adrp	x8, _mmUVD_VCPU_CACHE_OFFSET1@GOTPAGE
Lloh29:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_OFFSET1@GOTPAGEOFF]
Lloh30:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
	mov	w1, #2097152
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
Lloh31:
	adrp	x8, _mmUVD_VCPU_CACHE_SIZE1@GOTPAGE
Lloh32:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_SIZE1@GOTPAGEOFF]
Lloh33:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
Lloh34:
	adrp	x20, _AMDGPU_UVD_HEAP_SIZE@GOTPAGE
Lloh35:
	ldr	x20, [x20, _AMDGPU_UVD_HEAP_SIZE@GOTPAGEOFF]
	ldr	w1, [x20]
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
Lloh36:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW@GOTPAGE
Lloh37:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh38:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
	mov	x22, x0
	ldr	x8, [x19, #24]
	ldr	w8, [x8, x25]
	ldr	w9, [x20]
	add	w8, w8, w23
	add	w0, w8, w9
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x22
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
Lloh39:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH@GOTPAGE
Lloh40:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh41:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
	mov	x22, x0
	ldr	x8, [x19, #24]
	ldr	w8, [x8, x25]
	ldr	w9, [x20]
	add	w8, w8, w23
	add	w0, w8, w9
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x22
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
Lloh42:
	adrp	x8, _mmUVD_VCPU_CACHE_OFFSET2@GOTPAGE
Lloh43:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_OFFSET2@GOTPAGEOFF]
Lloh44:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
	mov	w1, #4194304
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
Lloh45:
	adrp	x8, _mmUVD_VCPU_CACHE_SIZE2@GOTPAGE
Lloh46:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_SIZE2@GOTPAGEOFF]
Lloh47:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
Lloh48:
	adrp	x8, _AMDGPU_UVD_STACK_SIZE@GOTPAGE
Lloh49:
	ldr	x8, [x8, _AMDGPU_UVD_STACK_SIZE@GOTPAGEOFF]
Lloh50:
	ldr	w8, [x8]
Lloh51:
	adrp	x9, _AMDGPU_UVD_SESSION_SIZE@GOTPAGE
Lloh52:
	ldr	x9, [x9, _AMDGPU_UVD_SESSION_SIZE@GOTPAGEOFF]
Lloh53:
	ldr	w9, [x9]
	mov	w10, #40
	madd	w1, w9, w10, w8
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
Lloh54:
	adrp	x8, _mmUVD_GP_SCRATCH4@GOTPAGE
Lloh55:
	ldr	x8, [x8, _mmUVD_GP_SCRATCH4@GOTPAGEOFF]
Lloh56:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
	ldr	w1, [x19, #16]
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
Lloh57:
	adrp	x8, _mmUVD_CGC_CTRL@GOTPAGE
Lloh58:
	ldr	x8, [x8, _mmUVD_CGC_CTRL@GOTPAGEOFF]
Lloh59:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
Lloh60:
	adrp	x8, _UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPAGE
Lloh61:
	ldr	x8, [x8, _UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPAGEOFF]
Lloh62:
	ldr	w8, [x8]
	mvn	w1, w8
	mov	w2, #0
	bl	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	ldr	w0, [x26]
Lloh63:
	adrp	x20, _mmUVD_MASTINT_EN@GOTPAGE
Lloh64:
	ldr	x20, [x20, _mmUVD_MASTINT_EN@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
Lloh65:
	adrp	x22, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGE
Lloh66:
	ldr	x22, [x22, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGEOFF]
	ldr	w8, [x22]
	mvn	w1, w8
	mov	w2, #0
	bl	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	ldr	w0, [x26]
Lloh67:
	adrp	x23, _mmUVD_LMI_CTRL2@GOTPAGE
Lloh68:
	ldr	x23, [x23, _mmUVD_LMI_CTRL2@GOTPAGEOFF]
Lloh69:
	ldr	w2, [x23]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
Lloh70:
	adrp	x24, _UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPAGE
Lloh71:
	ldr	x24, [x24, _UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPAGEOFF]
Lloh72:
	ldr	w2, [x24]
	mvn	w1, w2
	bl	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	ldr	w0, [x26]
Lloh73:
	adrp	x23, _mmUVD_SOFT_RESET@GOTPAGE
Lloh74:
	ldr	x23, [x23, _mmUVD_SOFT_RESET@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
Lloh75:
	adrp	x8, _UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPAGE
Lloh76:
	ldr	x8, [x8, _UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh77:
	ldr	w8, [x8]
Lloh78:
	adrp	x24, _UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPAGE
Lloh79:
	ldr	x24, [x24, _UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPAGEOFF]
	ldr	w9, [x24]
	orr	w8, w9, w8
Lloh80:
	adrp	x9, _UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK@GOTPAGE
Lloh81:
	ldr	x9, [x9, _UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh82:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh83:
	adrp	x9, _UVD_SOFT_RESET__RBC_SOFT_RESET_MASK@GOTPAGE
Lloh84:
	ldr	x9, [x9, _UVD_SOFT_RESET__RBC_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh85:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh86:
	adrp	x9, _UVD_SOFT_RESET__CSM_SOFT_RESET_MASK@GOTPAGE
Lloh87:
	ldr	x9, [x9, _UVD_SOFT_RESET__CSM_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh88:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh89:
	adrp	x9, _UVD_SOFT_RESET__CXW_SOFT_RESET_MASK@GOTPAGE
Lloh90:
	ldr	x9, [x9, _UVD_SOFT_RESET__CXW_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh91:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh92:
	adrp	x9, _UVD_SOFT_RESET__TAP_SOFT_RESET_MASK@GOTPAGE
Lloh93:
	ldr	x9, [x9, _UVD_SOFT_RESET__TAP_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh94:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh95:
	adrp	x9, _UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPAGE
Lloh96:
	ldr	x9, [x9, _UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh97:
	ldr	w9, [x9]
	orr	w1, w8, w9
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
Lloh98:
	adrp	x8, _mmUVD_LMI_CTRL@GOTPAGE
Lloh99:
	ldr	x8, [x8, _mmUVD_LMI_CTRL@GOTPAGEOFF]
Lloh100:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
Lloh101:
	adrp	x8, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT@GOTPAGE
Lloh102:
	ldr	x8, [x8, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT@GOTPAGEOFF]
Lloh103:
	ldr	w8, [x8]
	mov	w9, #64
	lsl	w8, w9, w8
Lloh104:
	adrp	x9, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPAGE
Lloh105:
	ldr	x9, [x9, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPAGEOFF]
Lloh106:
	ldr	w9, [x9]
Lloh107:
	adrp	x10, _UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPAGE
Lloh108:
	ldr	x10, [x10, _UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPAGEOFF]
Lloh109:
	ldr	w10, [x10]
Lloh110:
	adrp	x11, _UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPAGE
Lloh111:
	ldr	x11, [x11, _UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPAGEOFF]
Lloh112:
	ldr	w11, [x11]
Lloh113:
	adrp	x12, _UVD_LMI_CTRL__REQ_MODE_MASK@GOTPAGE
Lloh114:
	ldr	x12, [x12, _UVD_LMI_CTRL__REQ_MODE_MASK@GOTPAGEOFF]
Lloh115:
	ldr	w12, [x12]
	orr	w8, w9, w8
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w1, w8, #0x100000
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
	ldr	w2, [x23]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
	ldr	w1, [x24]
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
Lloh116:
	adrp	x8, _mmUVD_VCPU_CNTL@GOTPAGE
Lloh117:
	ldr	x8, [x8, _mmUVD_VCPU_CNTL@GOTPAGEOFF]
Lloh118:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
Lloh119:
	adrp	x8, _UVD_VCPU_CNTL__CLK_EN_MASK@GOTPAGE
Lloh120:
	ldr	x8, [x8, _UVD_VCPU_CNTL__CLK_EN_MASK@GOTPAGEOFF]
Lloh121:
	ldr	w1, [x8]
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
	ldr	w2, [x20]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x22]
Lloh122:
	adrp	x9, _UVD_MASTINT_EN__SYS_EN_MASK@GOTPAGE
Lloh123:
	ldr	x9, [x9, _UVD_MASTINT_EN__SYS_EN_MASK@GOTPAGEOFF]
Lloh124:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mvn	w1, w2
	bl	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	ldr	w0, [x26]
	ldr	w2, [x28]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
Lloh125:
	adrp	x8, _UVD_STATUS__VCPU_REPORT__SHIFT@GOTPAGE
Lloh126:
	ldr	x8, [x8, _UVD_STATUS__VCPU_REPORT__SHIFT@GOTPAGEOFF]
Lloh127:
	ldr	w8, [x8]
	mov	w9, #2
	lsl	w8, w9, w8
	mvn	w1, w8
	mov	w2, #0
	bl	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	add	x8, x27, x25
	ldr	w0, [x8, #16]
	bl	_order_base_2
	mov	x3, x0
Lloh128:
	adrp	x20, _UVD_RBC_RB_CNTL@GOTPAGE
Lloh129:
	ldr	x20, [x20, _UVD_RBC_RB_CNTL@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh130:
	adrp	x8, _RB_BUFSZ@GOTPAGE
Lloh131:
	ldr	x8, [x8, _RB_BUFSZ@GOTPAGEOFF]
Lloh132:
	ldr	w2, [x8]
	mov	w0, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x20]
Lloh133:
	adrp	x8, _RB_NO_FETCH@GOTPAGE
Lloh134:
	ldr	x8, [x8, _RB_NO_FETCH@GOTPAGEOFF]
Lloh135:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x22, x0
	ldr	w0, [x26]
Lloh136:
	adrp	x8, _mmUVD_RBC_RB_CNTL@GOTPAGE
Lloh137:
	ldr	x8, [x8, _mmUVD_RBC_RB_CNTL@GOTPAGEOFF]
Lloh138:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
	mov	x1, x22
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	x8, [x19, #24]
	add	x8, x8, x25
	ldr	x20, [x8, #8]
	str	xzr, [x20, #8]
	ldr	w0, [x26]
Lloh139:
	adrp	x8, _mmUVD_RB_BASE_LO@GOTPAGE
Lloh140:
	ldr	x8, [x8, _mmUVD_RB_BASE_LO@GOTPAGEOFF]
Lloh141:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
	ldr	w1, [x20, #4]
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
Lloh142:
	adrp	x8, _mmUVD_RB_BASE_HI@GOTPAGE
Lloh143:
	ldr	x8, [x8, _mmUVD_RB_BASE_HI@GOTPAGEOFF]
Lloh144:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
	mov	x22, x0
	ldr	w0, [x20, #4]
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x22
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
Lloh145:
	adrp	x8, _mmUVD_RB_SIZE@GOTPAGE
Lloh146:
	ldr	x8, [x8, _mmUVD_RB_SIZE@GOTPAGEOFF]
Lloh147:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x20]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w1, w8, #2
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
	ldr	w2, [x23]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
Lloh148:
	adrp	x8, _mmUVD_LMI_CTRL2@GOTPAGE
Lloh149:
	ldr	x8, [x8, _mmUVD_LMI_CTRL2@GOTPAGEOFF]
Lloh150:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
Lloh151:
	adrp	x8, _UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPAGE
Lloh152:
	ldr	x8, [x8, _UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPAGEOFF]
Lloh153:
	ldr	w8, [x8]
	mvn	w1, w8
	mov	w2, #0
	bl	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	ldr	w0, [x26]
	ldr	w2, [x28]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
	mov	w1, #2
	mov	w2, #2
	bl	_MMSCH_V1_0_INSERT_DIRECT_POLL
	ldr	w8, [x19, #8]
LBB0_6:                                 ;   in Loop: Header=BB0_7 Depth=1
	add	x21, x21, #1
	add	x25, x25, #32
	cmp	x21, w8, sxtw
	b.ge	LBB0_10
LBB0_7:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w9, [x19, #12]
	lsr	w9, w9, w21
	tbnz	w9, #0, LBB0_6
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=1
	ldp	x27, x8, [x19, #24]
	add	x9, x27, x25
	str	xzr, [x9, #24]
	ldr	x8, [x8]
	add	x0, x8, #4
	bl	_AMDGPU_GPU_PAGE_ALIGN
	mov	x22, x0
	ldr	w0, [x26]
	mov	x24, x28
	ldr	w2, [x28]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
	mov	w1, #-1
	mov	w2, #4
	bl	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	ldr	x20, [x19, #40]
Lloh154:
	adrp	x8, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh155:
	ldr	x8, [x8, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh156:
	ldr	x28, [x8]
	ldr	w0, [x26]
Lloh157:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW@GOTPAGE
Lloh158:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh159:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
	mov	x23, x0
	cmp	x20, x28
	b.ne	LBB0_4
; %bb.9:                                ;   in Loop: Header=BB0_7 Depth=1
	ldr	x8, [x19, #48]
Lloh160:
	adrp	x20, _AMDGPU_UCODE_ID_UVD@GOTPAGE
Lloh161:
	ldr	x20, [x20, _AMDGPU_UCODE_ID_UVD@GOTPAGEOFF]
	ldr	x9, [x20]
	lsl	x9, x9, #3
	ldr	w1, [x8, x9]
	mov	x0, x23
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
Lloh162:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPAGE
Lloh163:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh164:
	ldr	w2, [x8]
	mov	x1, x21
	bl	_SOC15_REG_OFFSET
	ldr	x8, [x19, #48]
	ldr	x9, [x20]
	add	x8, x8, x9, lsl #3
	ldr	w1, [x8, #4]
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x26]
Lloh165:
	adrp	x8, _mmUVD_VCPU_CACHE_OFFSET0@GOTPAGE
Lloh166:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_OFFSET0@GOTPAGEOFF]
Lloh167:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	mov	w23, #0
	b	LBB0_5
LBB0_10:
	add	x1, sp, #24
	ldr	x0, [sp, #16]                   ; 8-byte Folded Reload
	mov	w2, #8
	bl	_memcpy
	mov	w8, #2
	ldr	x9, [sp, #8]                    ; 8-byte Folded Reload
	str	x8, [x9, #8]
LBB0_11:
	mov	x0, x19
	mov	x1, x19
	bl	_uvd_v7_0_mmsch_start
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh151, Lloh152, Lloh153
	.loh AdrpLdrGotLdr	Lloh148, Lloh149, Lloh150
	.loh AdrpLdrGotLdr	Lloh145, Lloh146, Lloh147
	.loh AdrpLdrGotLdr	Lloh142, Lloh143, Lloh144
	.loh AdrpLdrGotLdr	Lloh139, Lloh140, Lloh141
	.loh AdrpLdrGotLdr	Lloh136, Lloh137, Lloh138
	.loh AdrpLdrGotLdr	Lloh133, Lloh134, Lloh135
	.loh AdrpLdrGotLdr	Lloh130, Lloh131, Lloh132
	.loh AdrpLdrGot	Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGot	Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGot	Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGot	Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh157, Lloh158, Lloh159
	.loh AdrpLdrGotLdr	Lloh154, Lloh155, Lloh156
	.loh AdrpLdrGotLdr	Lloh165, Lloh166, Lloh167
	.loh AdrpLdrGotLdr	Lloh162, Lloh163, Lloh164
	.loh AdrpLdrGot	Lloh160, Lloh161
	.cfi_endproc
                                        ; -- End function
	.comm	_MMSCH_COMMAND__DIRECT_REG_WRITE,4,2 ; @MMSCH_COMMAND__DIRECT_REG_WRITE
	.comm	_MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE,4,2 ; @MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE
	.comm	_MMSCH_COMMAND__DIRECT_REG_POLLING,4,2 ; @MMSCH_COMMAND__DIRECT_REG_POLLING
	.comm	_MMSCH_COMMAND__END,4,2         ; @MMSCH_COMMAND__END
	.comm	_MMSCH_VERSION,4,2              ; @MMSCH_VERSION
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_STATUS,4,2               ; @mmUVD_STATUS
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
	.comm	_AMDGPU_UCODE_ID_UVD,8,3        ; @AMDGPU_UCODE_ID_UVD
	.comm	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET0,4,2   ; @mmUVD_VCPU_CACHE_OFFSET0
	.comm	_AMDGPU_UVD_FIRMWARE_OFFSET,4,2 ; @AMDGPU_UVD_FIRMWARE_OFFSET
	.comm	_mmUVD_VCPU_CACHE_SIZE0,4,2     ; @mmUVD_VCPU_CACHE_SIZE0
	.comm	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET1,4,2   ; @mmUVD_VCPU_CACHE_OFFSET1
	.comm	_mmUVD_VCPU_CACHE_SIZE1,4,2     ; @mmUVD_VCPU_CACHE_SIZE1
	.comm	_AMDGPU_UVD_HEAP_SIZE,4,2       ; @AMDGPU_UVD_HEAP_SIZE
	.comm	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET2,4,2   ; @mmUVD_VCPU_CACHE_OFFSET2
	.comm	_mmUVD_VCPU_CACHE_SIZE2,4,2     ; @mmUVD_VCPU_CACHE_SIZE2
	.comm	_AMDGPU_UVD_STACK_SIZE,4,2      ; @AMDGPU_UVD_STACK_SIZE
	.comm	_AMDGPU_UVD_SESSION_SIZE,4,2    ; @AMDGPU_UVD_SESSION_SIZE
	.comm	_mmUVD_GP_SCRATCH4,4,2          ; @mmUVD_GP_SCRATCH4
	.comm	_mmUVD_CGC_CTRL,4,2             ; @mmUVD_CGC_CTRL
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK,4,2 ; @UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK
	.comm	_mmUVD_MASTINT_EN,4,2           ; @mmUVD_MASTINT_EN
	.comm	_UVD_MASTINT_EN__VCPU_EN_MASK,4,2 ; @UVD_MASTINT_EN__VCPU_EN_MASK
	.comm	_mmUVD_LMI_CTRL2,4,2            ; @mmUVD_LMI_CTRL2
	.comm	_UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,4,2 ; @UVD_LMI_CTRL2__STALL_ARB_UMC_MASK
	.comm	_mmUVD_SOFT_RESET,4,2           ; @mmUVD_SOFT_RESET
	.comm	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__RBC_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__RBC_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__CSM_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__CSM_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__CXW_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__CXW_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__TAP_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__TAP_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
	.comm	_mmUVD_LMI_CTRL,4,2             ; @mmUVD_LMI_CTRL
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT,4,2 ; @UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK,4,2 ; @UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK
	.comm	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK,4,2 ; @UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK,4,2 ; @UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__REQ_MODE_MASK,4,2 ; @UVD_LMI_CTRL__REQ_MODE_MASK
	.comm	_mmUVD_VCPU_CNTL,4,2            ; @mmUVD_VCPU_CNTL
	.comm	_UVD_VCPU_CNTL__CLK_EN_MASK,4,2 ; @UVD_VCPU_CNTL__CLK_EN_MASK
	.comm	_UVD_MASTINT_EN__SYS_EN_MASK,4,2 ; @UVD_MASTINT_EN__SYS_EN_MASK
	.comm	_UVD_STATUS__VCPU_REPORT__SHIFT,4,2 ; @UVD_STATUS__VCPU_REPORT__SHIFT
	.comm	_UVD_RBC_RB_CNTL,4,2            ; @UVD_RBC_RB_CNTL
	.comm	_RB_BUFSZ,4,2                   ; @RB_BUFSZ
	.comm	_RB_NO_FETCH,4,2                ; @RB_NO_FETCH
	.comm	_mmUVD_RBC_RB_CNTL,4,2          ; @mmUVD_RBC_RB_CNTL
	.comm	_mmUVD_RB_BASE_LO,4,2           ; @mmUVD_RB_BASE_LO
	.comm	_mmUVD_RB_BASE_HI,4,2           ; @mmUVD_RB_BASE_HI
	.comm	_mmUVD_RB_SIZE,4,2              ; @mmUVD_RB_SIZE
	.no_dead_strip	_uvd_v7_0_sriov_start
.subsections_via_symbols
