	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function si_populate_smc_acpi_state
_si_populate_smc_acpi_state:            ## @si_populate_smc_acpi_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$88, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r12
	movq	%rdi, %r15
	callq	_rv770_get_pi
	movq	%rax, %r14
	movq	%r15, %rdi
	callq	_evergreen_get_pi
	movq	%rax, %rbx
	movq	%r15, %rdi
	callq	_si_get_pi
	movq	%rax, %r13
	movl	(%rax), %r8d
	movl	4(%rax), %eax
	movl	%eax, -96(%rbp)                 ## 4-byte Spill
	movl	8(%r13), %r9d
	movl	12(%r13), %r10d
	movl	16(%r13), %eax
	movl	%eax, -68(%rbp)                 ## 4-byte Spill
	movl	20(%r13), %eax
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movl	24(%r13), %eax
	movl	%eax, -72(%rbp)                 ## 4-byte Spill
	movl	28(%r13), %eax
	movl	%eax, -76(%rbp)                 ## 4-byte Spill
	movl	32(%r13), %r11d
	movl	36(%r13), %ecx
	movl	40(%r13), %edi
	movups	16(%r12), %xmm0
	movups	%xmm0, (%r12)
	movq	_PPSMC_SWSTATE_FLAG_DC@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, 8(%r12)
	movq	(%r14), %rdx
	leaq	20(%rbx), %rsi
	testq	%rdx, %rdx
	movq	%r15, -48(%rbp)                 ## 8-byte Spill
	movq	%rbx, -64(%rbp)                 ## 8-byte Spill
	movl	%r10d, -104(%rbp)               ## 4-byte Spill
	movl	%r9d, -100(%rbp)                ## 4-byte Spill
	movl	%r8d, -92(%rbp)                 ## 4-byte Spill
	movl	%edi, -88(%rbp)                 ## 4-byte Spill
	movl	%ecx, -84(%rbp)                 ## 4-byte Spill
	movl	%r11d, -80(%rbp)                ## 4-byte Spill
	je	LBB0_5
## %bb.1:
	movl	$196, %ebx
	movq	(%r12), %rcx
	addq	%rbx, %rcx
	movq	%r15, %rdi
	callq	_si_populate_voltage_value
	testl	%eax, %eax
	movq	%r14, %r15
	movl	-52(%rbp), %r14d                ## 4-byte Reload
	jne	LBB0_4
## %bb.2:
	addq	(%r12), %rbx
	leaq	-112(%rbp), %rdx
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movq	%rbx, %rsi
	callq	_si_get_std_voltage_value
	testl	%eax, %eax
	jne	LBB0_4
## %bb.3:
	movl	-112(%rbp), %esi
	movq	(%r12), %rcx
	movl	196(%rcx), %edx
	addq	$204, %rcx
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_si_populate_std_voltage_value
LBB0_4:
	movl	72(%r13), %eax
	movq	(%r12), %r9
	movl	%eax, 200(%r9)
	cmpq	$0, 56(%r13)
	movq	%r15, %rax
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	jne	LBB0_11
	jmp	LBB0_12
LBB0_5:
	movq	%r14, -120(%rbp)                ## 8-byte Spill
	movq	8(%r14), %rdx
	movl	$196, %ebx
	movq	(%r12), %rcx
	addq	%rbx, %rcx
	movq	%r15, %rdi
	callq	_si_populate_voltage_value
	testl	%eax, %eax
	movq	%r15, %rdi
	movl	-52(%rbp), %r14d                ## 4-byte Reload
	jne	LBB0_9
## %bb.6:
	addq	(%r12), %rbx
	leaq	-108(%rbp), %rdx
	movq	%rbx, %rsi
	callq	_si_get_std_voltage_value
	testl	%eax, %eax
	jne	LBB0_8
## %bb.7:
	movl	-108(%rbp), %esi
	movq	(%r12), %rcx
	movl	196(%rcx), %edx
	addq	$204, %rcx
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_si_populate_std_voltage_value
LBB0_8:
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
LBB0_9:
	movl	64(%r13), %edx
	movl	68(%r13), %esi
	movq	_RADEON_PCIE_GEN1@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	callq	_r600_get_pcie_gen_support
	movq	(%r12), %r9
	movl	%eax, 200(%r9)
	cmpq	$0, 56(%r13)
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	movq	-120(%rbp), %r15                ## 8-byte Reload
	je	LBB0_12
## %bb.10:
	movq	%r15, %rax
	addq	$8, %rax
LBB0_11:
	movq	(%rax), %rdx
	addq	$196, %r9
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movq	%rdi, %rsi
	xorl	%ecx, %ecx
	xorl	%r8d, %r8d
	callq	_si_populate_phase_shedding_value
LBB0_12:
	cmpq	$0, (%r15)
	je	LBB0_15
## %bb.13:
	movq	8(%rbx), %rdx
	testq	%rdx, %rdx
	je	LBB0_15
## %bb.14:
	movq	%rbx, %rsi
	addq	$16, %rsi
	movl	$192, %ecx
	addq	(%r12), %rcx
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_si_populate_voltage_value
LBB0_15:
	movq	_MRDCK0_RESET@GOTPCREL(%rip), %rax
	movq	_MRDCK1_RESET@GOTPCREL(%rip), %rcx
	orl	(%rax), %r14d
	orl	(%rcx), %r14d
	movq	_MRDCK0_PDNB@GOTPCREL(%rip), %rax
	movq	_MRDCK1_PDNB@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	notl	%ebx
	andl	%r14d, %ebx
	movq	_MRDCK0_BYPASS@GOTPCREL(%rip), %rax
	movq	_MRDCK1_BYPASS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	notl	%ecx
	movl	-68(%rbp), %r14d                ## 4-byte Reload
	andl	%ecx, %r14d
	movq	_SCLK_MUX_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	movl	-96(%rbp), %r15d                ## 4-byte Reload
	andl	%eax, %r15d
	movl	$4, %edi
	callq	_SCLK_MUX_SEL
	orl	%eax, %r15d
	movl	%r14d, %edi
	callq	_cpu_to_be32
	movq	(%r12), %rcx
	movq	%rax, 184(%rcx)
	movl	%ebx, %edi
	callq	_cpu_to_be32
	movq	(%r12), %rcx
	movq	%rax, 176(%rcx)
	movl	-72(%rbp), %edi                 ## 4-byte Reload
	callq	_cpu_to_be32
	movq	(%r12), %rcx
	movq	%rax, 168(%rcx)
	movl	-76(%rbp), %edi                 ## 4-byte Reload
	callq	_cpu_to_be32
	movq	(%r12), %rcx
	movq	%rax, 160(%rcx)
	movl	-80(%rbp), %edi                 ## 4-byte Reload
	callq	_cpu_to_be32
	movq	(%r12), %rcx
	movq	%rax, 152(%rcx)
	movl	-84(%rbp), %edi                 ## 4-byte Reload
	callq	_cpu_to_be32
	movq	(%r12), %rcx
	movq	%rax, 144(%rcx)
	movl	-88(%rbp), %edi                 ## 4-byte Reload
	callq	_cpu_to_be32
	movq	(%r12), %rcx
	movq	%rax, 136(%rcx)
	movl	44(%r13), %edi
	callq	_cpu_to_be32
	movq	(%r12), %rcx
	movq	%rax, 128(%rcx)
	movl	48(%r13), %edi
	callq	_cpu_to_be32
	movq	(%r12), %rcx
	movq	%rax, 120(%rcx)
	movl	-92(%rbp), %edi                 ## 4-byte Reload
	callq	_cpu_to_be32
	movq	(%r12), %rcx
	movq	%rax, 104(%rcx)
	movl	%r15d, %edi
	callq	_cpu_to_be32
	movq	(%r12), %rcx
	movq	%rax, 96(%rcx)
	movl	-100(%rbp), %edi                ## 4-byte Reload
	callq	_cpu_to_be32
	movq	(%r12), %rcx
	movq	%rax, 88(%rcx)
	movl	-104(%rbp), %edi                ## 4-byte Reload
	callq	_cpu_to_be32
	movq	(%r12), %rdx
	movq	%rax, 80(%rdx)
	movq	$0, 112(%rdx)
	movq	$0, 72(%rdx)
	addq	$64, %rdx
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	xorl	%esi, %esi
	callq	_si_populate_mvdd_value
	movq	-64(%rbp), %rax                 ## 8-byte Reload
	cmpq	$0, (%rax)
	movq	(%r12), %rax
	je	LBB0_17
## %bb.16:
	movq	$0, 56(%rax)
LBB0_17:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 32(%rax)
	movups	%xmm0, 16(%rax)
	movq	$0, 48(%rax)
	movq	_MIN_POWER_MASK@GOTPCREL(%rip), %rax
	movq	_MAX_POWER_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	orl	(%rax), %edi
	callq	_cpu_to_be32
	movq	(%r12), %rcx
	movq	%rax, 8(%rcx)
	movq	_MAX_POWER_DELTA_MASK@GOTPCREL(%rip), %rax
	movq	_STI_SIZE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	orl	(%rax), %edi
	movq	_LTI_RATIO_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	callq	_cpu_to_be32
	movq	(%r12), %rcx
	movq	%rax, (%rcx)
	xorl	%eax, %eax
	addq	$88, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PPSMC_SWSTATE_FLAG_DC,4,2      ## @PPSMC_SWSTATE_FLAG_DC
	.comm	_RADEON_PCIE_GEN1,4,2           ## @RADEON_PCIE_GEN1
	.comm	_MRDCK0_RESET,4,2               ## @MRDCK0_RESET
	.comm	_MRDCK1_RESET,4,2               ## @MRDCK1_RESET
	.comm	_MRDCK0_PDNB,4,2                ## @MRDCK0_PDNB
	.comm	_MRDCK1_PDNB,4,2                ## @MRDCK1_PDNB
	.comm	_MRDCK0_BYPASS,4,2              ## @MRDCK0_BYPASS
	.comm	_MRDCK1_BYPASS,4,2              ## @MRDCK1_BYPASS
	.comm	_SCLK_MUX_SEL_MASK,4,2          ## @SCLK_MUX_SEL_MASK
	.comm	_MIN_POWER_MASK,4,2             ## @MIN_POWER_MASK
	.comm	_MAX_POWER_MASK,4,2             ## @MAX_POWER_MASK
	.comm	_MAX_POWER_DELTA_MASK,4,2       ## @MAX_POWER_DELTA_MASK
	.comm	_STI_SIZE_MASK,4,2              ## @STI_SIZE_MASK
	.comm	_LTI_RATIO_MASK,4,2             ## @LTI_RATIO_MASK
	.no_dead_strip	_si_populate_smc_acpi_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function si_populate_smc_acpi_state
_si_populate_smc_acpi_state:            ; @si_populate_smc_acpi_state
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #144
	.cfi_def_cfa_offset 144
	stp	x28, x27, [sp, #48]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #64]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #80]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #96]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #112]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #128]            ; 16-byte Folded Spill
	add	x29, sp, #128
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x1
	mov	x20, x0
	bl	_rv770_get_pi
	mov	x22, x0
	mov	x0, x20
	bl	_evergreen_get_pi
	mov	x21, x0
	mov	x0, x20
	bl	_si_get_pi
	mov	x25, x0
	ldp	w12, w16, [x0]
	ldp	w11, w10, [x0, #8]
	ldp	w27, w26, [x0, #16]
	ldp	w28, w15, [x0, #24]
	ldp	w23, w14, [x0, #32]
	ldr	w13, [x0, #40]
	ldr	q0, [x19, #16]
	str	q0, [x19]
Lloh0:
	adrp	x8, _PPSMC_SWSTATE_FLAG_DC@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PPSMC_SWSTATE_FLAG_DC@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	ldr	w9, [x19, #8]
	bic	w8, w9, w8
	str	w8, [x19, #8]
	ldr	x2, [x22]
	add	x1, x21, #20
	stp	w11, w10, [sp, #32]             ; 8-byte Folded Spill
	stp	w13, w12, [sp, #24]             ; 8-byte Folded Spill
	stp	w15, w14, [sp, #16]             ; 8-byte Folded Spill
	str	w16, [sp, #12]                  ; 4-byte Folded Spill
	cbz	x2, LBB0_6
; %bb.1:
	ldr	x8, [x19]
	add	x3, x8, #196
	mov	x0, x20
	bl	_si_populate_voltage_value
	cbnz	w0, LBB0_4
; %bb.2:
	ldr	x8, [x19]
	add	x1, x8, #196
	add	x2, sp, #44
	mov	x0, x20
	bl	_si_get_std_voltage_value
	cbnz	w0, LBB0_4
; %bb.3:
	ldr	w1, [sp, #44]
	ldr	x8, [x19]
	ldr	w2, [x8, #196]
	add	x3, x8, #204
	mov	x0, x20
	bl	_si_populate_std_voltage_value
LBB0_4:
	ldr	w9, [x25, #72]
	ldr	x8, [x19]
	str	w9, [x8, #200]
	ldr	x9, [x25, #56]
	cbz	x9, LBB0_11
; %bb.5:
	mov	x24, x22
	b	LBB0_10
LBB0_6:
	mov	x24, x22
	ldr	x2, [x24, #8]!
	ldr	x8, [x19]
	add	x3, x8, #196
	mov	x0, x20
	bl	_si_populate_voltage_value
	cbnz	w0, LBB0_9
; %bb.7:
	ldr	x8, [x19]
	add	x1, x8, #196
	add	x2, sp, #40
	mov	x0, x20
	bl	_si_get_std_voltage_value
	cbnz	w0, LBB0_9
; %bb.8:
	ldr	w1, [sp, #40]
	ldr	x8, [x19]
	ldr	w2, [x8, #196]
	add	x3, x8, #204
	mov	x0, x20
	bl	_si_populate_std_voltage_value
LBB0_9:
	ldp	w2, w1, [x25, #64]
Lloh3:
	adrp	x8, _RADEON_PCIE_GEN1@GOTPAGE
Lloh4:
	ldr	x8, [x8, _RADEON_PCIE_GEN1@GOTPAGEOFF]
Lloh5:
	ldr	w3, [x8]
	mov	x0, x20
	bl	_r600_get_pcie_gen_support
	ldr	x8, [x19]
	str	w0, [x8, #200]
	ldr	x9, [x25, #56]
	cbz	x9, LBB0_11
LBB0_10:
	ldr	x2, [x24]
	add	x5, x8, #196
	mov	x0, x20
	mov	x1, x20
	mov	w3, #0
	mov	w4, #0
	bl	_si_populate_phase_shedding_value
LBB0_11:
	ldr	x8, [x22]
	cbz	x8, LBB0_14
; %bb.12:
	ldr	x2, [x21, #8]
	cbz	x2, LBB0_14
; %bb.13:
	add	x1, x21, #16
	ldr	x8, [x19]
	add	x3, x8, #192
	mov	x0, x20
	bl	_si_populate_voltage_value
LBB0_14:
Lloh6:
	adrp	x8, _MRDCK0_RESET@GOTPAGE
Lloh7:
	ldr	x8, [x8, _MRDCK0_RESET@GOTPAGEOFF]
Lloh8:
	adrp	x9, _MRDCK1_RESET@GOTPAGE
Lloh9:
	ldr	x9, [x9, _MRDCK1_RESET@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
Lloh11:
	ldr	w9, [x9]
	orr	w8, w8, w26
	orr	w8, w8, w9
Lloh12:
	adrp	x9, _MRDCK0_PDNB@GOTPAGE
Lloh13:
	ldr	x9, [x9, _MRDCK0_PDNB@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
Lloh15:
	adrp	x10, _MRDCK1_PDNB@GOTPAGE
Lloh16:
	ldr	x10, [x10, _MRDCK1_PDNB@GOTPAGEOFF]
Lloh17:
	ldr	w10, [x10]
	orr	w9, w10, w9
	bic	w26, w8, w9
Lloh18:
	adrp	x8, _MRDCK0_BYPASS@GOTPAGE
Lloh19:
	ldr	x8, [x8, _MRDCK0_BYPASS@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
Lloh21:
	adrp	x9, _MRDCK1_BYPASS@GOTPAGE
Lloh22:
	ldr	x9, [x9, _MRDCK1_BYPASS@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w27, w27, w8
Lloh24:
	adrp	x8, _SCLK_MUX_SEL_MASK@GOTPAGE
Lloh25:
	ldr	x8, [x8, _SCLK_MUX_SEL_MASK@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]                   ; 4-byte Folded Reload
	bic	w22, w9, w8
	mov	w0, #4
	bl	_SCLK_MUX_SEL
	orr	w24, w22, w0
	mov	x0, x27
	bl	_cpu_to_be32
	ldr	x8, [x19]
	str	x0, [x8, #184]
	mov	x0, x26
	bl	_cpu_to_be32
	ldr	x8, [x19]
	str	x0, [x8, #176]
	mov	x0, x28
	bl	_cpu_to_be32
	ldr	x8, [x19]
	str	x0, [x8, #168]
	ldr	w0, [sp, #16]                   ; 4-byte Folded Reload
	bl	_cpu_to_be32
	ldr	x8, [x19]
	str	x0, [x8, #160]
	mov	x0, x23
	bl	_cpu_to_be32
	ldr	x8, [x19]
	str	x0, [x8, #152]
	ldr	w0, [sp, #20]                   ; 4-byte Folded Reload
	bl	_cpu_to_be32
	ldr	x8, [x19]
	str	x0, [x8, #144]
	ldr	w0, [sp, #24]                   ; 4-byte Folded Reload
	bl	_cpu_to_be32
	ldr	x8, [x19]
	str	x0, [x8, #136]
	ldr	w0, [x25, #44]
	bl	_cpu_to_be32
	ldr	x8, [x19]
	str	x0, [x8, #128]
	ldr	w0, [x25, #48]
	bl	_cpu_to_be32
	ldr	x8, [x19]
	str	x0, [x8, #120]
	ldr	w0, [sp, #28]                   ; 4-byte Folded Reload
	bl	_cpu_to_be32
	ldr	x8, [x19]
	str	x0, [x8, #104]
	mov	x0, x24
	bl	_cpu_to_be32
	ldr	x8, [x19]
	str	x0, [x8, #96]
	ldr	w0, [sp, #32]                   ; 4-byte Folded Reload
	bl	_cpu_to_be32
	ldr	x8, [x19]
	str	x0, [x8, #88]
	ldr	w0, [sp, #36]                   ; 4-byte Folded Reload
	bl	_cpu_to_be32
	ldr	x8, [x19]
	str	xzr, [x8, #112]
	stp	xzr, x0, [x8, #72]
	add	x2, x8, #64
	mov	x0, x20
	mov	w1, #0
	bl	_si_populate_mvdd_value
	ldr	x9, [x21]
	ldr	x8, [x19]
	cbz	x9, LBB0_16
; %bb.15:
	str	xzr, [x8, #56]
LBB0_16:
	str	xzr, [x8, #48]
	movi.2d	v0, #0000000000000000
Lloh27:
	adrp	x9, _MIN_POWER_MASK@GOTPAGE
Lloh28:
	ldr	x9, [x9, _MIN_POWER_MASK@GOTPAGEOFF]
	stp	q0, q0, [x8, #16]
Lloh29:
	ldr	w8, [x9]
Lloh30:
	adrp	x9, _MAX_POWER_MASK@GOTPAGE
Lloh31:
	ldr	x9, [x9, _MAX_POWER_MASK@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	orr	w0, w9, w8
	bl	_cpu_to_be32
	ldr	x8, [x19]
	str	x0, [x8, #8]
Lloh33:
	adrp	x8, _MAX_POWER_DELTA_MASK@GOTPAGE
Lloh34:
	ldr	x8, [x8, _MAX_POWER_DELTA_MASK@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
Lloh36:
	adrp	x9, _STI_SIZE_MASK@GOTPAGE
Lloh37:
	ldr	x9, [x9, _STI_SIZE_MASK@GOTPAGEOFF]
Lloh38:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh39:
	adrp	x9, _LTI_RATIO_MASK@GOTPAGE
Lloh40:
	ldr	x9, [x9, _LTI_RATIO_MASK@GOTPAGEOFF]
Lloh41:
	ldr	w9, [x9]
	orr	w0, w8, w9
	bl	_cpu_to_be32
	ldr	x8, [x19]
	str	x0, [x8]
	mov	w0, #0
	ldp	x29, x30, [sp, #128]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #112]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #96]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #80]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #64]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #144
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh10
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.cfi_endproc
                                        ; -- End function
	.comm	_PPSMC_SWSTATE_FLAG_DC,4,2      ; @PPSMC_SWSTATE_FLAG_DC
	.comm	_RADEON_PCIE_GEN1,4,2           ; @RADEON_PCIE_GEN1
	.comm	_MRDCK0_RESET,4,2               ; @MRDCK0_RESET
	.comm	_MRDCK1_RESET,4,2               ; @MRDCK1_RESET
	.comm	_MRDCK0_PDNB,4,2                ; @MRDCK0_PDNB
	.comm	_MRDCK1_PDNB,4,2                ; @MRDCK1_PDNB
	.comm	_MRDCK0_BYPASS,4,2              ; @MRDCK0_BYPASS
	.comm	_MRDCK1_BYPASS,4,2              ; @MRDCK1_BYPASS
	.comm	_SCLK_MUX_SEL_MASK,4,2          ; @SCLK_MUX_SEL_MASK
	.comm	_MIN_POWER_MASK,4,2             ; @MIN_POWER_MASK
	.comm	_MAX_POWER_MASK,4,2             ; @MAX_POWER_MASK
	.comm	_MAX_POWER_DELTA_MASK,4,2       ; @MAX_POWER_DELTA_MASK
	.comm	_STI_SIZE_MASK,4,2              ; @STI_SIZE_MASK
	.comm	_LTI_RATIO_MASK,4,2             ; @LTI_RATIO_MASK
	.no_dead_strip	_si_populate_smc_acpi_state
.subsections_via_symbols
