	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_soc15_set_ip_blocks            ## -- Begin function soc15_set_ip_blocks
	.p2align	4, 0x90
_soc15_set_ip_blocks:                   ## @soc15_set_ip_blocks
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	movl	(%rdi), %eax
	leal	-129(%rax), %ecx
	cmpl	$4, %ecx
	jae	LBB0_1
## %bb.4:
	movq	%rbx, %rdi
	callq	_vega10_reg_base_init
LBB0_5:
	movl	(%rbx), %eax
	cmpl	$133, %eax
	je	LBB0_7
## %bb.6:
	cmpl	$128, %eax
	jne	LBB0_8
LBB0_7:
	movl	$1, 48(%rbx)
LBB0_8:
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	andl	4(%rbx), %edx
	cmpl	$128, %eax
	sete	%cl
	cmpl	$133, %eax
	sete	%al
	orb	%cl, %al
	movq	_nbio_v6_1_funcs@GOTPCREL(%rip), %rax
	cmovneq	_nbio_v7_4_funcs@GOTPCREL(%rip), %rax
	movq	_df_v1_7_funcs@GOTPCREL(%rip), %rcx
	cmovneq	_df_v3_6_funcs@GOTPCREL(%rip), %rcx
	testl	%edx, %edx
	je	LBB0_10
## %bb.9:
	movq	_nbio_v7_0_funcs@GOTPCREL(%rip), %rax
LBB0_10:
	movq	%rax, 24(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%rbx, %rdi
	callq	_soc15_get_rev_id
	movl	%eax, 32(%rbx)
	movq	24(%rbx), %rax
	movq	%rbx, %rdi
	callq	*(%rax)
	movq	%rbx, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_12
## %bb.11:
	movq	_xgpu_ai_virt_ops@GOTPCREL(%rip), %rax
	movq	%rax, 16(%rbx)
LBB0_12:
	movl	(%rbx), %eax
	addl	$-128, %eax
	cmpl	$5, %eax
	ja	LBB0_55
## %bb.13:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_14:
	movq	_vega10_common_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_gmc_v9_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	%rbx, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_20
## %bb.15:
	movl	12(%rbx), %eax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	xorl	%edi, %edi
	cmpl	(%rcx), %eax
	sete	%dil
	callq	_likely
	movq	_vega10_ih_ip_block@GOTPCREL(%rip), %r14
	testl	%eax, %eax
	je	LBB0_24
## %bb.16:
	cmpl	$128, (%rbx)
	jne	LBB0_17
## %bb.18:
	movq	_psp_v11_0_ip_block@GOTPCREL(%rip), %rsi
	jmp	LBB0_19
LBB0_1:
	cmpl	$128, %eax
	je	LBB0_57
## %bb.2:
	cmpl	$133, %eax
	jne	LBB0_55
## %bb.3:
	movq	%rbx, %rdi
	callq	_arct_reg_base_init
	jmp	LBB0_5
LBB0_55:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_56
LBB0_57:
	movq	%rbx, %rdi
	callq	_vega20_reg_base_init
	jmp	LBB0_5
LBB0_20:
	movq	_vega10_ih_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	movl	12(%rbx), %eax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	xorl	%edi, %edi
	cmpl	(%rcx), %eax
	sete	%dil
	callq	_likely
	testl	%eax, %eax
	je	LBB0_25
## %bb.21:
	cmpl	$128, (%rbx)
	jne	LBB0_22
## %bb.23:
	movq	_psp_v11_0_ip_block@GOTPCREL(%rip), %r14
	jmp	LBB0_24
LBB0_47:
	movq	_vega10_common_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_gmc_v9_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_vega10_ih_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	movl	12(%rbx), %eax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	xorl	%edi, %edi
	cmpl	(%rcx), %eax
	sete	%dil
	callq	_likely
	testl	%eax, %eax
	je	LBB0_49
## %bb.48:
	movq	_psp_v12_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
LBB0_49:
	movq	%rbx, %rdi
	callq	_is_support_sw_smu
	testl	%eax, %eax
	je	LBB0_51
## %bb.50:
	movq	_smu_v12_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
LBB0_51:
	movq	_gfx_v9_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_sdma_v4_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	cmpl	$0, 8(%rbx)
	jne	LBB0_53
## %bb.52:
	movq	%rbx, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_54
LBB0_53:
	movq	_dce_virtual_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
LBB0_54:
	movq	_vcn_v2_0_ip_block@GOTPCREL(%rip), %rsi
	jmp	LBB0_42
LBB0_36:
	movq	_vega10_common_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_gmc_v9_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_vega10_ih_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	movl	12(%rbx), %eax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	xorl	%edi, %edi
	cmpl	(%rcx), %eax
	sete	%dil
	callq	_likely
	testl	%eax, %eax
	je	LBB0_38
## %bb.37:
	movq	_psp_v10_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
LBB0_38:
	movq	_gfx_v9_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_sdma_v4_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_pp_smu_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	cmpl	$0, 8(%rbx)
	jne	LBB0_40
## %bb.39:
	movq	%rbx, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_41
LBB0_40:
	movq	_dce_virtual_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
LBB0_41:
	movq	_vcn_v1_0_ip_block@GOTPCREL(%rip), %rsi
	jmp	LBB0_42
LBB0_43:
	movq	_vega10_common_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_gmc_v9_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_vega10_ih_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	cmpl	$0, 8(%rbx)
	jne	LBB0_45
## %bb.44:
	movq	%rbx, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_46
LBB0_45:
	movq	_dce_virtual_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
LBB0_46:
	movq	_gfx_v9_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_sdma_v4_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_smu_v11_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_vcn_v2_5_ip_block@GOTPCREL(%rip), %rsi
	jmp	LBB0_42
LBB0_17:
	movq	_psp_v3_1_ip_block@GOTPCREL(%rip), %rsi
LBB0_19:
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	jmp	LBB0_24
LBB0_22:
	movq	_psp_v3_1_ip_block@GOTPCREL(%rip), %r14
LBB0_24:
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	_amdgpu_device_ip_block_add
LBB0_25:
	movq	_gfx_v9_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_sdma_v4_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	%rbx, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_26
## %bb.30:
	cmpl	$0, 8(%rbx)
	jne	LBB0_32
	jmp	LBB0_31
LBB0_26:
	movq	%rbx, %rdi
	callq	_is_support_sw_smu
	testl	%eax, %eax
	jne	LBB0_27
## %bb.28:
	movq	_pp_smu_ip_block@GOTPCREL(%rip), %rsi
	jmp	LBB0_29
LBB0_27:
	movq	_smu_v11_0_ip_block@GOTPCREL(%rip), %rsi
LBB0_29:
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	cmpl	$0, 8(%rbx)
	jne	LBB0_32
LBB0_31:
	movq	%rbx, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_33
LBB0_32:
	movq	_dce_virtual_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
LBB0_33:
	cmpl	$128, (%rbx)
	jne	LBB0_35
## %bb.34:
	movq	%rbx, %rdi
	callq	_amdgpu_sriov_vf
	movq	%rax, %rcx
	xorl	%eax, %eax
	testq	%rcx, %rcx
	jne	LBB0_56
LBB0_35:
	movq	_uvd_v7_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_vce_v4_0_ip_block@GOTPCREL(%rip), %rsi
LBB0_42:
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_block_add
	xorl	%eax, %eax
LBB0_56:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_14, LBB0_14-LJTI0_0
.set L0_0_set_47, LBB0_47-LJTI0_0
.set L0_0_set_36, LBB0_36-LJTI0_0
.set L0_0_set_43, LBB0_43-LJTI0_0
LJTI0_0:
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_47
	.long	L0_0_set_36
	.long	L0_0_set_43
	.end_data_region
                                        ## -- End function
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_nbio_v7_0_funcs,8,3            ## @nbio_v7_0_funcs
	.comm	_nbio_v7_4_funcs,8,3            ## @nbio_v7_4_funcs
	.comm	_nbio_v6_1_funcs,8,3            ## @nbio_v6_1_funcs
	.comm	_df_v3_6_funcs,4,2              ## @df_v3_6_funcs
	.comm	_df_v1_7_funcs,4,2              ## @df_v1_7_funcs
	.comm	_xgpu_ai_virt_ops,4,2           ## @xgpu_ai_virt_ops
	.comm	_vega10_common_ip_block,4,2     ## @vega10_common_ip_block
	.comm	_gmc_v9_0_ip_block,4,2          ## @gmc_v9_0_ip_block
	.comm	_AMDGPU_FW_LOAD_PSP,4,2         ## @AMDGPU_FW_LOAD_PSP
	.comm	_psp_v11_0_ip_block,4,2         ## @psp_v11_0_ip_block
	.comm	_psp_v3_1_ip_block,4,2          ## @psp_v3_1_ip_block
	.comm	_vega10_ih_ip_block,4,2         ## @vega10_ih_ip_block
	.comm	_gfx_v9_0_ip_block,4,2          ## @gfx_v9_0_ip_block
	.comm	_sdma_v4_0_ip_block,4,2         ## @sdma_v4_0_ip_block
	.comm	_smu_v11_0_ip_block,4,2         ## @smu_v11_0_ip_block
	.comm	_pp_smu_ip_block,4,2            ## @pp_smu_ip_block
	.comm	_dce_virtual_ip_block,4,2       ## @dce_virtual_ip_block
	.comm	_uvd_v7_0_ip_block,4,2          ## @uvd_v7_0_ip_block
	.comm	_vce_v4_0_ip_block,4,2          ## @vce_v4_0_ip_block
	.comm	_psp_v10_0_ip_block,4,2         ## @psp_v10_0_ip_block
	.comm	_vcn_v1_0_ip_block,4,2          ## @vcn_v1_0_ip_block
	.comm	_vcn_v2_5_ip_block,4,2          ## @vcn_v2_5_ip_block
	.comm	_psp_v12_0_ip_block,4,2         ## @psp_v12_0_ip_block
	.comm	_smu_v12_0_ip_block,4,2         ## @smu_v12_0_ip_block
	.comm	_vcn_v2_0_ip_block,4,2          ## @vcn_v2_0_ip_block
	.comm	_dm_ip_block,4,2                ## @dm_ip_block
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_soc15_set_ip_blocks            ; -- Begin function soc15_set_ip_blocks
	.p2align	2
_soc15_set_ip_blocks:                   ; @soc15_set_ip_blocks
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	w8, [x0]
	sub	w9, w8, #129
	cmp	w9, #4
	b.hs	LBB0_2
; %bb.1:
	mov	x0, x19
	bl	_vega10_reg_base_init
	b	LBB0_6
LBB0_2:
	cmp	w8, #128
	b.eq	LBB0_5
; %bb.3:
	cmp	w8, #133
	b.ne	LBB0_17
; %bb.4:
	mov	x0, x19
	bl	_arct_reg_base_init
	b	LBB0_6
LBB0_5:
	mov	x0, x19
	bl	_vega20_reg_base_init
LBB0_6:
	ldr	w8, [x19]
	cmp	w8, #133
	b.eq	LBB0_8
; %bb.7:
	cmp	w8, #128
	b.ne	LBB0_9
LBB0_8:
	mov	w9, #1
	str	w9, [x19, #48]
LBB0_9:
	ldr	w9, [x19, #4]
Lloh0:
	adrp	x10, _AMD_IS_APU@GOTPAGE
Lloh1:
	ldr	x10, [x10, _AMD_IS_APU@GOTPAGEOFF]
	cmp	w8, #128
	mov	w11, #133
	ccmp	w8, w11, #4, ne
Lloh2:
	adrp	x8, _nbio_v6_1_funcs@GOTPAGE
Lloh3:
	ldr	x8, [x8, _nbio_v6_1_funcs@GOTPAGEOFF]
Lloh4:
	adrp	x11, _nbio_v7_4_funcs@GOTPAGE
Lloh5:
	ldr	x11, [x11, _nbio_v7_4_funcs@GOTPAGEOFF]
	csel	x8, x11, x8, eq
Lloh6:
	adrp	x11, _nbio_v7_0_funcs@GOTPAGE
Lloh7:
	ldr	x11, [x11, _nbio_v7_0_funcs@GOTPAGEOFF]
Lloh8:
	adrp	x12, _df_v1_7_funcs@GOTPAGE
Lloh9:
	ldr	x12, [x12, _df_v1_7_funcs@GOTPAGEOFF]
Lloh10:
	adrp	x13, _df_v3_6_funcs@GOTPAGE
Lloh11:
	ldr	x13, [x13, _df_v3_6_funcs@GOTPAGEOFF]
Lloh12:
	ldr	w10, [x10]
	csel	x12, x13, x12, eq
	tst	w10, w9
	csel	x8, x8, x11, eq
	str	x8, [x19, #24]
	str	x12, [x19, #40]
	mov	x0, x19
	bl	_soc15_get_rev_id
	str	w0, [x19, #32]
	ldr	x8, [x19, #24]
	ldr	x8, [x8]
	mov	x0, x19
	blr	x8
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_11
; %bb.10:
Lloh13:
	adrp	x8, _xgpu_ai_virt_ops@GOTPAGE
Lloh14:
	ldr	x8, [x8, _xgpu_ai_virt_ops@GOTPAGEOFF]
	str	x8, [x19, #16]
LBB0_11:
	ldr	w8, [x19]
	sub	w8, w8, #128
	cmp	w8, #5
	b.hi	LBB0_17
; %bb.12:
Lloh15:
	adrp	x9, lJTI0_0@PAGE
Lloh16:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_13
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_13:
Lloh17:
	adrp	x1, _vega10_common_ip_block@GOTPAGE
Lloh18:
	ldr	x1, [x1, _vega10_common_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh19:
	adrp	x1, _gmc_v9_0_ip_block@GOTPAGE
Lloh20:
	ldr	x1, [x1, _gmc_v9_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_18
; %bb.14:
	ldr	w8, [x19, #12]
Lloh21:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh22:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	cmp	w8, w9
	cset	w0, eq
	bl	_likely
	cbz	w0, LBB0_16
; %bb.15:
	ldr	w8, [x19]
Lloh24:
	adrp	x9, _psp_v3_1_ip_block@GOTPAGE
Lloh25:
	ldr	x9, [x9, _psp_v3_1_ip_block@GOTPAGEOFF]
Lloh26:
	adrp	x10, _psp_v11_0_ip_block@GOTPAGE
Lloh27:
	ldr	x10, [x10, _psp_v11_0_ip_block@GOTPAGEOFF]
	cmp	w8, #128
	csel	x1, x10, x9, eq
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
LBB0_16:
Lloh28:
	adrp	x1, _vega10_ih_ip_block@GOTPAGE
Lloh29:
	ldr	x1, [x1, _vega10_ih_ip_block@GOTPAGEOFF]
	b	LBB0_20
LBB0_17:
Lloh30:
	adrp	x8, _EINVAL@GOTPAGE
Lloh31:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_49
LBB0_18:
Lloh33:
	adrp	x1, _vega10_ih_ip_block@GOTPAGE
Lloh34:
	ldr	x1, [x1, _vega10_ih_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
	ldr	w8, [x19, #12]
Lloh35:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh36:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh37:
	ldr	w9, [x9]
	cmp	w8, w9
	cset	w0, eq
	bl	_likely
	cbz	w0, LBB0_21
; %bb.19:
	ldr	w8, [x19]
Lloh38:
	adrp	x9, _psp_v3_1_ip_block@GOTPAGE
Lloh39:
	ldr	x9, [x9, _psp_v3_1_ip_block@GOTPAGEOFF]
Lloh40:
	adrp	x10, _psp_v11_0_ip_block@GOTPAGE
Lloh41:
	ldr	x10, [x10, _psp_v11_0_ip_block@GOTPAGEOFF]
	cmp	w8, #128
	csel	x1, x10, x9, eq
LBB0_20:
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
LBB0_21:
Lloh42:
	adrp	x1, _gfx_v9_0_ip_block@GOTPAGE
Lloh43:
	ldr	x1, [x1, _gfx_v9_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh44:
	adrp	x1, _sdma_v4_0_ip_block@GOTPAGE
Lloh45:
	ldr	x1, [x1, _sdma_v4_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_23
; %bb.22:
	ldr	w8, [x19, #8]
	cbnz	w8, LBB0_25
	b	LBB0_24
LBB0_23:
	mov	x0, x19
	bl	_is_support_sw_smu
Lloh46:
	adrp	x8, _smu_v11_0_ip_block@GOTPAGE
Lloh47:
	ldr	x8, [x8, _smu_v11_0_ip_block@GOTPAGEOFF]
Lloh48:
	adrp	x9, _pp_smu_ip_block@GOTPAGE
Lloh49:
	ldr	x9, [x9, _pp_smu_ip_block@GOTPAGEOFF]
	cmp	w0, #0
	csel	x1, x9, x8, eq
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
	ldr	w8, [x19, #8]
	cbnz	w8, LBB0_25
LBB0_24:
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_26
LBB0_25:
Lloh50:
	adrp	x1, _dce_virtual_ip_block@GOTPAGE
Lloh51:
	ldr	x1, [x1, _dce_virtual_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
LBB0_26:
	ldr	w8, [x19]
	cmp	w8, #128
	b.ne	LBB0_28
; %bb.27:
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbnz	x0, LBB0_48
LBB0_28:
Lloh52:
	adrp	x1, _uvd_v7_0_ip_block@GOTPAGE
Lloh53:
	ldr	x1, [x1, _uvd_v7_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh54:
	adrp	x1, _vce_v4_0_ip_block@GOTPAGE
Lloh55:
	ldr	x1, [x1, _vce_v4_0_ip_block@GOTPAGEOFF]
	b	LBB0_47
LBB0_29:
Lloh56:
	adrp	x1, _vega10_common_ip_block@GOTPAGE
Lloh57:
	ldr	x1, [x1, _vega10_common_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh58:
	adrp	x1, _gmc_v9_0_ip_block@GOTPAGE
Lloh59:
	ldr	x1, [x1, _gmc_v9_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh60:
	adrp	x1, _vega10_ih_ip_block@GOTPAGE
Lloh61:
	ldr	x1, [x1, _vega10_ih_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
	ldr	w8, [x19, #12]
Lloh62:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh63:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh64:
	ldr	w9, [x9]
	cmp	w8, w9
	cset	w0, eq
	bl	_likely
	cbz	w0, LBB0_31
; %bb.30:
Lloh65:
	adrp	x1, _psp_v12_0_ip_block@GOTPAGE
Lloh66:
	ldr	x1, [x1, _psp_v12_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
LBB0_31:
	mov	x0, x19
	bl	_is_support_sw_smu
	cbz	w0, LBB0_33
; %bb.32:
Lloh67:
	adrp	x1, _smu_v12_0_ip_block@GOTPAGE
Lloh68:
	ldr	x1, [x1, _smu_v12_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
LBB0_33:
Lloh69:
	adrp	x1, _gfx_v9_0_ip_block@GOTPAGE
Lloh70:
	ldr	x1, [x1, _gfx_v9_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh71:
	adrp	x1, _sdma_v4_0_ip_block@GOTPAGE
Lloh72:
	ldr	x1, [x1, _sdma_v4_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
	ldr	w8, [x19, #8]
	cbnz	w8, LBB0_35
; %bb.34:
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_36
LBB0_35:
Lloh73:
	adrp	x1, _dce_virtual_ip_block@GOTPAGE
Lloh74:
	ldr	x1, [x1, _dce_virtual_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
LBB0_36:
Lloh75:
	adrp	x1, _vcn_v2_0_ip_block@GOTPAGE
Lloh76:
	ldr	x1, [x1, _vcn_v2_0_ip_block@GOTPAGEOFF]
	b	LBB0_47
LBB0_37:
Lloh77:
	adrp	x1, _vega10_common_ip_block@GOTPAGE
Lloh78:
	ldr	x1, [x1, _vega10_common_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh79:
	adrp	x1, _gmc_v9_0_ip_block@GOTPAGE
Lloh80:
	ldr	x1, [x1, _gmc_v9_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh81:
	adrp	x1, _vega10_ih_ip_block@GOTPAGE
Lloh82:
	ldr	x1, [x1, _vega10_ih_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
	ldr	w8, [x19, #12]
Lloh83:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh84:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh85:
	ldr	w9, [x9]
	cmp	w8, w9
	cset	w0, eq
	bl	_likely
	cbz	w0, LBB0_39
; %bb.38:
Lloh86:
	adrp	x1, _psp_v10_0_ip_block@GOTPAGE
Lloh87:
	ldr	x1, [x1, _psp_v10_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
LBB0_39:
Lloh88:
	adrp	x1, _gfx_v9_0_ip_block@GOTPAGE
Lloh89:
	ldr	x1, [x1, _gfx_v9_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh90:
	adrp	x1, _sdma_v4_0_ip_block@GOTPAGE
Lloh91:
	ldr	x1, [x1, _sdma_v4_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh92:
	adrp	x1, _pp_smu_ip_block@GOTPAGE
Lloh93:
	ldr	x1, [x1, _pp_smu_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
	ldr	w8, [x19, #8]
	cbnz	w8, LBB0_41
; %bb.40:
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_42
LBB0_41:
Lloh94:
	adrp	x1, _dce_virtual_ip_block@GOTPAGE
Lloh95:
	ldr	x1, [x1, _dce_virtual_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
LBB0_42:
Lloh96:
	adrp	x1, _vcn_v1_0_ip_block@GOTPAGE
Lloh97:
	ldr	x1, [x1, _vcn_v1_0_ip_block@GOTPAGEOFF]
	b	LBB0_47
LBB0_43:
Lloh98:
	adrp	x1, _vega10_common_ip_block@GOTPAGE
Lloh99:
	ldr	x1, [x1, _vega10_common_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh100:
	adrp	x1, _gmc_v9_0_ip_block@GOTPAGE
Lloh101:
	ldr	x1, [x1, _gmc_v9_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh102:
	adrp	x1, _vega10_ih_ip_block@GOTPAGE
Lloh103:
	ldr	x1, [x1, _vega10_ih_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
	ldr	w8, [x19, #8]
	cbnz	w8, LBB0_45
; %bb.44:
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_46
LBB0_45:
Lloh104:
	adrp	x1, _dce_virtual_ip_block@GOTPAGE
Lloh105:
	ldr	x1, [x1, _dce_virtual_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
LBB0_46:
Lloh106:
	adrp	x1, _gfx_v9_0_ip_block@GOTPAGE
Lloh107:
	ldr	x1, [x1, _gfx_v9_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh108:
	adrp	x1, _sdma_v4_0_ip_block@GOTPAGE
Lloh109:
	ldr	x1, [x1, _sdma_v4_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh110:
	adrp	x1, _smu_v11_0_ip_block@GOTPAGE
Lloh111:
	ldr	x1, [x1, _smu_v11_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh112:
	adrp	x1, _vcn_v2_5_ip_block@GOTPAGE
Lloh113:
	ldr	x1, [x1, _vcn_v2_5_ip_block@GOTPAGEOFF]
LBB0_47:
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
LBB0_48:
	mov	w0, #0
LBB0_49:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh12
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGot	Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh54, Lloh55
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGot	Lloh56, Lloh57
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGot	Lloh67, Lloh68
	.loh AdrpLdrGot	Lloh71, Lloh72
	.loh AdrpLdrGot	Lloh69, Lloh70
	.loh AdrpLdrGot	Lloh73, Lloh74
	.loh AdrpLdrGot	Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGot	Lloh81, Lloh82
	.loh AdrpLdrGot	Lloh79, Lloh80
	.loh AdrpLdrGot	Lloh77, Lloh78
	.loh AdrpLdrGot	Lloh86, Lloh87
	.loh AdrpLdrGot	Lloh92, Lloh93
	.loh AdrpLdrGot	Lloh90, Lloh91
	.loh AdrpLdrGot	Lloh88, Lloh89
	.loh AdrpLdrGot	Lloh94, Lloh95
	.loh AdrpLdrGot	Lloh96, Lloh97
	.loh AdrpLdrGot	Lloh102, Lloh103
	.loh AdrpLdrGot	Lloh100, Lloh101
	.loh AdrpLdrGot	Lloh98, Lloh99
	.loh AdrpLdrGot	Lloh104, Lloh105
	.loh AdrpLdrGot	Lloh112, Lloh113
	.loh AdrpLdrGot	Lloh110, Lloh111
	.loh AdrpLdrGot	Lloh108, Lloh109
	.loh AdrpLdrGot	Lloh106, Lloh107
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_13-LBB0_13)>>2
	.byte	(LBB0_13-LBB0_13)>>2
	.byte	(LBB0_13-LBB0_13)>>2
	.byte	(LBB0_29-LBB0_13)>>2
	.byte	(LBB0_37-LBB0_13)>>2
	.byte	(LBB0_43-LBB0_13)>>2
                                        ; -- End function
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_nbio_v7_0_funcs,8,3            ; @nbio_v7_0_funcs
	.comm	_nbio_v7_4_funcs,8,3            ; @nbio_v7_4_funcs
	.comm	_nbio_v6_1_funcs,8,3            ; @nbio_v6_1_funcs
	.comm	_df_v3_6_funcs,4,2              ; @df_v3_6_funcs
	.comm	_df_v1_7_funcs,4,2              ; @df_v1_7_funcs
	.comm	_xgpu_ai_virt_ops,4,2           ; @xgpu_ai_virt_ops
	.comm	_vega10_common_ip_block,4,2     ; @vega10_common_ip_block
	.comm	_gmc_v9_0_ip_block,4,2          ; @gmc_v9_0_ip_block
	.comm	_AMDGPU_FW_LOAD_PSP,4,2         ; @AMDGPU_FW_LOAD_PSP
	.comm	_psp_v11_0_ip_block,4,2         ; @psp_v11_0_ip_block
	.comm	_psp_v3_1_ip_block,4,2          ; @psp_v3_1_ip_block
	.comm	_vega10_ih_ip_block,4,2         ; @vega10_ih_ip_block
	.comm	_gfx_v9_0_ip_block,4,2          ; @gfx_v9_0_ip_block
	.comm	_sdma_v4_0_ip_block,4,2         ; @sdma_v4_0_ip_block
	.comm	_smu_v11_0_ip_block,4,2         ; @smu_v11_0_ip_block
	.comm	_pp_smu_ip_block,4,2            ; @pp_smu_ip_block
	.comm	_dce_virtual_ip_block,4,2       ; @dce_virtual_ip_block
	.comm	_uvd_v7_0_ip_block,4,2          ; @uvd_v7_0_ip_block
	.comm	_vce_v4_0_ip_block,4,2          ; @vce_v4_0_ip_block
	.comm	_psp_v10_0_ip_block,4,2         ; @psp_v10_0_ip_block
	.comm	_vcn_v1_0_ip_block,4,2          ; @vcn_v1_0_ip_block
	.comm	_vcn_v2_5_ip_block,4,2          ; @vcn_v2_5_ip_block
	.comm	_psp_v12_0_ip_block,4,2         ; @psp_v12_0_ip_block
	.comm	_smu_v12_0_ip_block,4,2         ; @smu_v12_0_ip_block
	.comm	_vcn_v2_0_ip_block,4,2          ; @vcn_v2_0_ip_block
	.comm	_dm_ip_block,4,2                ; @dm_ip_block
.subsections_via_symbols
