	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function i9xx_crtc_clock_get
_i9xx_crtc_clock_get:                   ## @i9xx_crtc_clock_get
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r15
	movq	(%rdi), %rbx
	movq	%rbx, %rdi
	callq	_to_i915
	movq	%rax, %r13
	movl	(%r15), %r14d
	movl	8(%r15), %r12d
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	_i9xx_pll_refclk
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	_DISPLAY_RATE_SELECT_FPA1@GOTPCREL(%rip), %rax
	xorl	%ecx, %ecx
	movl	(%rax), %eax
	andl	%r12d, %eax
	setne	%cl
	movl	12(%r15,%rcx,4), %ebx
	movq	_FP_M1_DIV_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%ebx, %eax
	movq	_FP_M1_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	movl	%eax, -64(%rbp)
	movq	%r13, %rdi
	callq	_IS_PINEVIEW
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	_FP_N_PINEVIEW_DIV_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	andl	%ebx, %edi
	movq	_FP_N_DIV_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarl	%cl, %edi
	callq	_ffs
	decl	%eax
	movq	_FP_M2_PINEVIEW_DIV_MASK@GOTPCREL(%rip), %rcx
	jmp	LBB0_3
LBB0_2:
	movq	_FP_N_DIV_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%ebx, %eax
	movq	_FP_N_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	movq	_FP_M2_DIV_MASK@GOTPCREL(%rip), %rcx
LBB0_3:
	andl	(%rcx), %ebx
	movq	_FP_M2_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %ebx
	movl	%eax, -60(%rbp)
	movl	%ebx, -56(%rbp)
	movq	%r13, %rdi
	movl	$2, %esi
	callq	_IS_GEN
	testl	%eax, %eax
	je	LBB0_4
## %bb.11:
	movq	%r13, %rdi
	callq	_IS_I830
	xorl	%ebx, %ebx
	testq	%rax, %rax
	je	LBB0_12
## %bb.13:
	cmpl	$1, %r14d
	je	LBB0_14
	jmp	LBB0_18
LBB0_4:
	movq	%r13, %rdi
	callq	_IS_PINEVIEW
	testq	%rax, %rax
	movq	_DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW@GOTPCREL(%rip), %rax
	cmoveq	_DPLL_FPA01_P1_POST_DIV_MASK@GOTPCREL(%rip), %rax
	movq	_DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW@GOTPCREL(%rip), %rcx
	cmoveq	_DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movl	(%rax), %edi
	andl	%r12d, %edi
	movb	(%rcx), %cl
	sarl	%cl, %edi
	callq	_ffs
	movl	%eax, -52(%rbp)
	movq	_DPLL_MODE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	andl	%r12d, %esi
	cmpl	$128, %esi
	je	LBB0_8
## %bb.5:
	cmpl	$129, %esi
	jne	LBB0_7
## %bb.6:
	movq	_DPLL_DAC_SERIAL_P2_CLOCK_DIV_5@GOTPCREL(%rip), %rax
	xorl	%ecx, %ecx
	testl	%r12d, (%rax)
	sete	%cl
	leal	(%rcx,%rcx,4), %eax
	addl	$5, %eax
	jmp	LBB0_9
LBB0_12:
	movq	_LVDS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movl	%eax, %ebx
	cmpl	$1, %r14d
	jne	LBB0_18
LBB0_14:
	movq	_LVDS_PORT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%ebx, %eax
	je	LBB0_18
## %bb.15:
	movq	_DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS@GOTPCREL(%rip), %rax
	andl	(%rax), %r12d
	movq	_DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarl	%cl, %r12d
	movl	%r12d, %edi
	callq	_ffs
	movl	%eax, -52(%rbp)
	movq	_LVDS_CLKB_POWER_UP@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_17
## %bb.16:
	movl	$7, -48(%rbp)
	jmp	LBB0_23
LBB0_18:
	movq	_PLL_P1_DIVIDE_BY_TWO@GOTPCREL(%rip), %rcx
	movl	$2, %eax
	testl	%r12d, (%rcx)
	jne	LBB0_20
## %bb.19:
	movq	_DPLL_FPA01_P1_POST_DIV_MASK_I830@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r12d, %eax
	movq	_DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	addl	$2, %eax
LBB0_20:
	movl	%eax, -52(%rbp)
	movq	_PLL_P2_DIVIDE_BY_4@GOTPCREL(%rip), %rax
	testl	%r12d, (%rax)
	je	LBB0_22
## %bb.21:
	movl	$4, -48(%rbp)
	jmp	LBB0_23
LBB0_8:
	movq	_DPLLB_LVDS_P2_CLOCK_DIV_7@GOTPCREL(%rip), %rax
	testl	%r12d, (%rax)
	movl	$14, %ecx
	movl	$7, %eax
	cmovel	%ecx, %eax
LBB0_9:
	movl	-44(%rbp), %ebx                 ## 4-byte Reload
	movl	%eax, -48(%rbp)
	movq	%r13, %rdi
	callq	_IS_PINEVIEW
	leaq	-64(%rbp), %rsi
	movl	%ebx, %edi
	testq	%rax, %rax
	je	LBB0_24
## %bb.10:
	callq	_pnv_calc_dpll_params
	jmp	LBB0_25
LBB0_7:
	leaq	L_.str(%rip), %rdi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_DRM_DEBUG_KMS                  ## TAILCALL
LBB0_17:
	movl	$14, -48(%rbp)
	jmp	LBB0_23
LBB0_22:
	movl	$2, -48(%rbp)
LBB0_23:
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	leaq	-64(%rbp), %rsi
LBB0_24:
	callq	_i9xx_calc_dpll_params
LBB0_25:
	movl	%eax, 4(%r15)
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DISPLAY_RATE_SELECT_FPA1,4,2   ## @DISPLAY_RATE_SELECT_FPA1
	.comm	_FP_M1_DIV_MASK,4,2             ## @FP_M1_DIV_MASK
	.comm	_FP_M1_DIV_SHIFT,4,2            ## @FP_M1_DIV_SHIFT
	.comm	_FP_N_PINEVIEW_DIV_MASK,4,2     ## @FP_N_PINEVIEW_DIV_MASK
	.comm	_FP_N_DIV_SHIFT,4,2             ## @FP_N_DIV_SHIFT
	.comm	_FP_M2_PINEVIEW_DIV_MASK,4,2    ## @FP_M2_PINEVIEW_DIV_MASK
	.comm	_FP_M2_DIV_SHIFT,4,2            ## @FP_M2_DIV_SHIFT
	.comm	_FP_N_DIV_MASK,4,2              ## @FP_N_DIV_MASK
	.comm	_FP_M2_DIV_MASK,4,2             ## @FP_M2_DIV_MASK
	.comm	_DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW,4,2 ## @DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
	.comm	_DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW,4,2 ## @DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
	.comm	_DPLL_FPA01_P1_POST_DIV_MASK,4,2 ## @DPLL_FPA01_P1_POST_DIV_MASK
	.comm	_DPLL_FPA01_P1_POST_DIV_SHIFT,4,2 ## @DPLL_FPA01_P1_POST_DIV_SHIFT
	.comm	_DPLL_MODE_MASK,4,2             ## @DPLL_MODE_MASK
	.comm	_DPLL_DAC_SERIAL_P2_CLOCK_DIV_5,4,2 ## @DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
	.comm	_DPLLB_LVDS_P2_CLOCK_DIV_7,4,2  ## @DPLLB_LVDS_P2_CLOCK_DIV_7
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Unknown DPLL mode %08x in programmed mode\n"

	.comm	_LVDS,4,2                       ## @LVDS
	.comm	_LVDS_PORT_EN,4,2               ## @LVDS_PORT_EN
	.comm	_DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS,4,2 ## @DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
	.comm	_LVDS_CLKB_POWER_UP,4,2         ## @LVDS_CLKB_POWER_UP
	.comm	_PLL_P1_DIVIDE_BY_TWO,4,2       ## @PLL_P1_DIVIDE_BY_TWO
	.comm	_DPLL_FPA01_P1_POST_DIV_MASK_I830,4,2 ## @DPLL_FPA01_P1_POST_DIV_MASK_I830
	.comm	_PLL_P2_DIVIDE_BY_4,4,2         ## @PLL_P2_DIVIDE_BY_4
	.no_dead_strip	_i9xx_crtc_clock_get
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function i9xx_crtc_clock_get
_i9xx_crtc_clock_get:                   ; @i9xx_crtc_clock_get
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x1
	ldr	x20, [x0]
	mov	x0, x20
	bl	_to_i915
	mov	x21, x0
	ldr	w23, [x19]
	ldr	w22, [x19, #8]
	mov	x0, x20
	mov	x1, x19
	bl	_i9xx_pll_refclk
	mov	x20, x0
Lloh0:
	adrp	x8, _DISPLAY_RATE_SELECT_FPA1@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DISPLAY_RATE_SELECT_FPA1@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	tst	w8, w22
	mov	w8, #16
	mov	w9, #12
	csel	x8, x9, x8, eq
	ldr	w24, [x19, x8]
Lloh3:
	adrp	x8, _FP_M1_DIV_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _FP_M1_DIV_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	and	w8, w8, w24
Lloh6:
	adrp	x9, _FP_M1_DIV_SHIFT@GOTPAGE
Lloh7:
	ldr	x9, [x9, _FP_M1_DIV_SHIFT@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	asr	w8, w8, w9
	str	w8, [sp, #8]
	mov	x0, x21
	bl	_IS_PINEVIEW
	cbz	x0, LBB0_2
; %bb.1:
Lloh9:
	adrp	x8, _FP_N_PINEVIEW_DIV_MASK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _FP_N_PINEVIEW_DIV_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	and	w8, w8, w24
Lloh12:
	adrp	x9, _FP_N_DIV_SHIFT@GOTPAGE
Lloh13:
	ldr	x9, [x9, _FP_N_DIV_SHIFT@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	asr	w0, w8, w9
	bl	_ffs
	sub	w8, w0, #1
Lloh15:
	adrp	x9, _FP_M2_PINEVIEW_DIV_MASK@GOTPAGE
Lloh16:
	ldr	x9, [x9, _FP_M2_PINEVIEW_DIV_MASK@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:
Lloh17:
	adrp	x8, _FP_N_DIV_MASK@GOTPAGE
Lloh18:
	ldr	x8, [x8, _FP_N_DIV_MASK@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
	and	w8, w8, w24
Lloh20:
	adrp	x9, _FP_N_DIV_SHIFT@GOTPAGE
Lloh21:
	ldr	x9, [x9, _FP_N_DIV_SHIFT@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	asr	w8, w8, w9
Lloh23:
	adrp	x9, _FP_M2_DIV_MASK@GOTPAGE
Lloh24:
	ldr	x9, [x9, _FP_M2_DIV_MASK@GOTPAGEOFF]
LBB0_3:
	ldr	w9, [x9]
	and	w9, w9, w24
Lloh25:
	adrp	x10, _FP_M2_DIV_SHIFT@GOTPAGE
Lloh26:
	ldr	x10, [x10, _FP_M2_DIV_SHIFT@GOTPAGEOFF]
Lloh27:
	ldr	w10, [x10]
	asr	w9, w9, w10
	stp	w8, w9, [sp, #12]
	mov	x0, x21
	mov	w1, #2
	bl	_IS_GEN
	cbz	w0, LBB0_6
; %bb.4:
	mov	x0, x21
	bl	_IS_I830
	cbz	x0, LBB0_9
; %bb.5:
	mov	w21, #0
	cmp	w23, #1
	b.eq	LBB0_10
	b	LBB0_13
LBB0_6:
	mov	x0, x21
	bl	_IS_PINEVIEW
Lloh28:
	adrp	x8, _DPLL_FPA01_P1_POST_DIV_MASK@GOTPAGE
Lloh29:
	ldr	x8, [x8, _DPLL_FPA01_P1_POST_DIV_MASK@GOTPAGEOFF]
Lloh30:
	adrp	x9, _DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW@GOTPAGE
Lloh31:
	ldr	x9, [x9, _DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW@GOTPAGEOFF]
	cmp	x0, #0
	csel	x8, x8, x9, eq
	ldr	w8, [x8]
Lloh32:
	adrp	x9, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGE
Lloh33:
	ldr	x9, [x9, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGEOFF]
	and	w8, w8, w22
Lloh34:
	adrp	x10, _DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW@GOTPAGE
Lloh35:
	ldr	x10, [x10, _DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW@GOTPAGEOFF]
	csel	x9, x9, x10, eq
	ldr	w9, [x9]
	asr	w0, w8, w9
	bl	_ffs
	str	w0, [sp, #20]
Lloh36:
	adrp	x8, _DPLL_MODE_MASK@GOTPAGE
Lloh37:
	ldr	x8, [x8, _DPLL_MODE_MASK@GOTPAGEOFF]
Lloh38:
	ldr	w8, [x8]
	and	w1, w8, w22
	cmp	w1, #128
	b.eq	LBB0_15
; %bb.7:
	cmp	w1, #129
	b.ne	LBB0_18
; %bb.8:
Lloh39:
	adrp	x8, _DPLL_DAC_SERIAL_P2_CLOCK_DIV_5@GOTPAGE
Lloh40:
	ldr	x8, [x8, _DPLL_DAC_SERIAL_P2_CLOCK_DIV_5@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
	tst	w8, w22
	mov	w8, #5
	mov	w9, #10
	b	LBB0_16
LBB0_9:
Lloh42:
	adrp	x8, _LVDS@GOTPAGE
Lloh43:
	ldr	x8, [x8, _LVDS@GOTPAGEOFF]
Lloh44:
	ldr	w0, [x8]
	bl	_I915_READ
	mov	x21, x0
	cmp	w23, #1
	b.ne	LBB0_13
LBB0_10:
Lloh45:
	adrp	x8, _LVDS_PORT_EN@GOTPAGE
Lloh46:
	ldr	x8, [x8, _LVDS_PORT_EN@GOTPAGEOFF]
Lloh47:
	ldr	w8, [x8]
	and	w8, w8, w21
	cbz	w8, LBB0_13
; %bb.11:
Lloh48:
	adrp	x8, _DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS@GOTPAGE
Lloh49:
	ldr	x8, [x8, _DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS@GOTPAGEOFF]
Lloh50:
	ldr	w8, [x8]
	and	w8, w8, w22
Lloh51:
	adrp	x9, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGE
Lloh52:
	ldr	x9, [x9, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGEOFF]
Lloh53:
	ldr	w9, [x9]
	asr	w0, w8, w9
	bl	_ffs
	str	w0, [sp, #20]
Lloh54:
	adrp	x8, _LVDS_CLKB_POWER_UP@GOTPAGE
Lloh55:
	ldr	x8, [x8, _LVDS_CLKB_POWER_UP@GOTPAGEOFF]
Lloh56:
	ldr	w8, [x8]
	tst	w8, w21
	b.eq	LBB0_19
; %bb.12:
	mov	w8, #7
	b	LBB0_24
LBB0_13:
Lloh57:
	adrp	x8, _PLL_P1_DIVIDE_BY_TWO@GOTPAGE
Lloh58:
	ldr	x8, [x8, _PLL_P1_DIVIDE_BY_TWO@GOTPAGEOFF]
Lloh59:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_20
; %bb.14:
	mov	w8, #2
	b	LBB0_21
LBB0_15:
Lloh60:
	adrp	x8, _DPLLB_LVDS_P2_CLOCK_DIV_7@GOTPAGE
Lloh61:
	ldr	x8, [x8, _DPLLB_LVDS_P2_CLOCK_DIV_7@GOTPAGEOFF]
Lloh62:
	ldr	w8, [x8]
	tst	w8, w22
	mov	w8, #7
	mov	w9, #14
LBB0_16:
	csel	w8, w9, w8, eq
	str	w8, [sp, #24]
	mov	x0, x21
	bl	_IS_PINEVIEW
	cbz	x0, LBB0_25
; %bb.17:
	add	x1, sp, #8
	mov	x0, x20
	bl	_pnv_calc_dpll_params
	b	LBB0_26
LBB0_18:
Lloh63:
	adrp	x0, l_.str@PAGE
Lloh64:
	add	x0, x0, l_.str@PAGEOFF
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #96
	b	_DRM_DEBUG_KMS
LBB0_19:
	mov	w8, #14
	b	LBB0_24
LBB0_20:
Lloh65:
	adrp	x8, _DPLL_FPA01_P1_POST_DIV_MASK_I830@GOTPAGE
Lloh66:
	ldr	x8, [x8, _DPLL_FPA01_P1_POST_DIV_MASK_I830@GOTPAGEOFF]
Lloh67:
	ldr	w8, [x8]
	and	w8, w8, w22
Lloh68:
	adrp	x9, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGE
Lloh69:
	ldr	x9, [x9, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGEOFF]
Lloh70:
	ldr	w9, [x9]
	asr	w8, w8, w9
	add	w8, w8, #2
LBB0_21:
	str	w8, [sp, #20]
Lloh71:
	adrp	x8, _PLL_P2_DIVIDE_BY_4@GOTPAGE
Lloh72:
	ldr	x8, [x8, _PLL_P2_DIVIDE_BY_4@GOTPAGEOFF]
Lloh73:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_23
; %bb.22:
	mov	w8, #4
	b	LBB0_24
LBB0_23:
	mov	w8, #2
LBB0_24:
	str	w8, [sp, #24]
LBB0_25:
	add	x1, sp, #8
	mov	x0, x20
	bl	_i9xx_calc_dpll_params
LBB0_26:
	str	w0, [x19, #4]
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpAdd	Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.cfi_endproc
                                        ; -- End function
	.comm	_DISPLAY_RATE_SELECT_FPA1,4,2   ; @DISPLAY_RATE_SELECT_FPA1
	.comm	_FP_M1_DIV_MASK,4,2             ; @FP_M1_DIV_MASK
	.comm	_FP_M1_DIV_SHIFT,4,2            ; @FP_M1_DIV_SHIFT
	.comm	_FP_N_PINEVIEW_DIV_MASK,4,2     ; @FP_N_PINEVIEW_DIV_MASK
	.comm	_FP_N_DIV_SHIFT,4,2             ; @FP_N_DIV_SHIFT
	.comm	_FP_M2_PINEVIEW_DIV_MASK,4,2    ; @FP_M2_PINEVIEW_DIV_MASK
	.comm	_FP_M2_DIV_SHIFT,4,2            ; @FP_M2_DIV_SHIFT
	.comm	_FP_N_DIV_MASK,4,2              ; @FP_N_DIV_MASK
	.comm	_FP_M2_DIV_MASK,4,2             ; @FP_M2_DIV_MASK
	.comm	_DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW,4,2 ; @DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
	.comm	_DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW,4,2 ; @DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
	.comm	_DPLL_FPA01_P1_POST_DIV_MASK,4,2 ; @DPLL_FPA01_P1_POST_DIV_MASK
	.comm	_DPLL_FPA01_P1_POST_DIV_SHIFT,4,2 ; @DPLL_FPA01_P1_POST_DIV_SHIFT
	.comm	_DPLL_MODE_MASK,4,2             ; @DPLL_MODE_MASK
	.comm	_DPLL_DAC_SERIAL_P2_CLOCK_DIV_5,4,2 ; @DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
	.comm	_DPLLB_LVDS_P2_CLOCK_DIV_7,4,2  ; @DPLLB_LVDS_P2_CLOCK_DIV_7
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Unknown DPLL mode %08x in programmed mode\n"

	.comm	_LVDS,4,2                       ; @LVDS
	.comm	_LVDS_PORT_EN,4,2               ; @LVDS_PORT_EN
	.comm	_DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS,4,2 ; @DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
	.comm	_LVDS_CLKB_POWER_UP,4,2         ; @LVDS_CLKB_POWER_UP
	.comm	_PLL_P1_DIVIDE_BY_TWO,4,2       ; @PLL_P1_DIVIDE_BY_TWO
	.comm	_DPLL_FPA01_P1_POST_DIV_MASK_I830,4,2 ; @DPLL_FPA01_P1_POST_DIV_MASK_I830
	.comm	_PLL_P2_DIVIDE_BY_4,4,2         ; @PLL_P2_DIVIDE_BY_4
	.no_dead_strip	_i9xx_crtc_clock_get
.subsections_via_symbols
