	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_evergreen_program_aspm         ## -- Begin function evergreen_program_aspm
	.p2align	4, 0x90
_evergreen_program_aspm:                ## @evergreen_program_aspm
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_radeon_aspm@GOTPCREL(%rip), %rax
	cmpq	$0, (%rax)
	je	LBB0_36
## %bb.1:
	movl	(%rdi), %ebx
	movq	_RADEON_IS_PCIE@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_36
## %bb.2:
	movl	$-137, %r15d
	movq	%rdi, -48(%rbp)                 ## 8-byte Spill
	addl	4(%rdi), %r15d
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_PB0_PIF_PAIRING@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_RREG32_PIF_PHY0
	movq	_MULTI_PIF@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movl	%esi, %ecx
	notl	%ecx
	andl	%eax, %ecx
	orl	%eax, %esi
	testl	%ebx, %r14d
	cmovnel	%ecx, %esi
	cmpl	%eax, %esi
	je	LBB0_4
## %bb.3:
	movl	(%r12), %edi
	callq	_WREG32_PIF_PHY0
LBB0_4:
	movq	_PB1_PIF_PAIRING@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_RREG32_PIF_PHY1
	movl	(%r13), %esi
	movl	%esi, %ecx
	notl	%ecx
	andl	%eax, %ecx
	orl	%eax, %esi
	testl	%ebx, %r14d
	cmovnel	%ecx, %esi
	cmpl	%eax, %esi
	je	LBB0_6
## %bb.5:
	movl	(%r12), %edi
	callq	_WREG32_PIF_PHY1
LBB0_6:
	movq	_PCIE_LC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_L0S_INACTIVITY_MASK@GOTPCREL(%rip), %rcx
	movq	_LC_L1_INACTIVITY_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r14d
	orl	(%rcx), %r14d
	notl	%r14d
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	andl	%eax, %r14d
	cmpl	$-10, %r15d
	ja	LBB0_7
## %bb.8:
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	movl	4(%rbx), %eax
	movq	_CHIP_BARTS@GOTPCREL(%rip), %rcx
	xorl	%edx, %edx
	cmpl	(%rcx), %eax
	setge	%dl
	leal	3(,%rdx,4), %edi
	callq	_LC_L0S_INACTIVITY
	orl	%eax, %r14d
	jmp	LBB0_9
LBB0_7:
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
LBB0_9:
	movl	4(%rbx), %eax
	movq	_CHIP_BARTS@GOTPCREL(%rip), %rcx
	xorl	%edi, %edi
	cmpl	(%rcx), %eax
	setl	%dil
	addl	$7, %edi
	callq	_LC_L1_INACTIVITY
	movl	%eax, %r15d
	movq	_PB0_PIF_PWRDOWN_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PIF_PHY0
	movl	%eax, %r13d
	movq	_PLL_POWER_STATE_IN_OFF_0_MASK@GOTPCREL(%rip), %rax
	movq	_PLL_POWER_STATE_IN_TXS2_0_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	notl	%ebx
	andl	%r13d, %ebx
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_OFF_0
	movl	%eax, %r12d
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_TXS2_0
	orl	%r12d, %eax
	orl	%ebx, %eax
	cmpl	%r13d, %eax
	je	LBB0_11
## %bb.10:
	movq	_PB0_PIF_PWRDOWN_0@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%eax, %esi
	callq	_WREG32_PIF_PHY0
LBB0_11:
	movq	_PB0_PIF_PWRDOWN_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PIF_PHY0
	movl	%eax, %r13d
	movq	_PLL_POWER_STATE_IN_OFF_1_MASK@GOTPCREL(%rip), %rax
	movq	_PLL_POWER_STATE_IN_TXS2_1_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	notl	%ebx
	andl	%r13d, %ebx
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_OFF_1
	movl	%eax, %r12d
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_TXS2_1
	orl	%r12d, %eax
	orl	%ebx, %eax
	cmpl	%r13d, %eax
	je	LBB0_13
## %bb.12:
	movq	_PB0_PIF_PWRDOWN_1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%eax, %esi
	callq	_WREG32_PIF_PHY0
LBB0_13:
	movq	_PB1_PIF_PWRDOWN_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PIF_PHY1
	movl	%eax, %r13d
	movq	_PLL_POWER_STATE_IN_TXS2_0_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_PLL_POWER_STATE_IN_OFF_0_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	notl	%ebx
	andl	%r13d, %ebx
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_OFF_0
	movl	%eax, %r12d
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_TXS2_0
	orl	%r12d, %eax
	orl	%ebx, %eax
	cmpl	%r13d, %eax
	je	LBB0_15
## %bb.14:
	movq	_PB1_PIF_PWRDOWN_0@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%eax, %esi
	callq	_WREG32_PIF_PHY1
LBB0_15:
	movq	_PB1_PIF_PWRDOWN_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PIF_PHY1
	movl	%eax, %r13d
	movq	_PLL_POWER_STATE_IN_TXS2_1_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_PLL_POWER_STATE_IN_OFF_1_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	notl	%ebx
	andl	%r13d, %ebx
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_OFF_1
	movl	%eax, %r12d
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_TXS2_1
	orl	%r12d, %eax
	orl	%ebx, %eax
	cmpl	%r13d, %eax
	je	LBB0_17
## %bb.16:
	movq	_PB1_PIF_PWRDOWN_1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%eax, %esi
	callq	_WREG32_PIF_PHY1
LBB0_17:
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movl	4(%rax), %eax
	movq	_CHIP_BARTS@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	movq	_PB0_PIF_PWRDOWN_0@GOTPCREL(%rip), %r13
	jl	LBB0_26
## %bb.18:
	movl	(%r13), %edi
	callq	_RREG32_PIF_PHY0
	movl	%eax, %r12d
	movq	_PLL_RAMP_UP_TIME_0_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	notl	%ebx
	andl	%r12d, %ebx
	movl	$4, %edi
	callq	_PLL_RAMP_UP_TIME_0
	orl	%ebx, %eax
	cmpl	%r12d, %eax
	je	LBB0_20
## %bb.19:
	movl	(%r13), %edi
	movl	%eax, %esi
	callq	_WREG32_PIF_PHY0
LBB0_20:
	movq	_PB0_PIF_PWRDOWN_1@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_RREG32_PIF_PHY0
	movl	%eax, %r12d
	movq	_PLL_RAMP_UP_TIME_1_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	notl	%ebx
	andl	%r12d, %ebx
	movl	$4, %edi
	callq	_PLL_RAMP_UP_TIME_1
	orl	%ebx, %eax
	cmpl	%r12d, %eax
	je	LBB0_22
## %bb.21:
	movl	(%r13), %edi
	movl	%eax, %esi
	callq	_WREG32_PIF_PHY0
LBB0_22:
	movq	_PB1_PIF_PWRDOWN_0@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_RREG32_PIF_PHY1
	movl	%eax, %r12d
	movq	_PLL_RAMP_UP_TIME_0_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	notl	%ebx
	andl	%r12d, %ebx
	movl	$4, %edi
	callq	_PLL_RAMP_UP_TIME_0
	orl	%ebx, %eax
	cmpl	%r12d, %eax
	je	LBB0_24
## %bb.23:
	movl	(%r13), %edi
	movl	%eax, %esi
	callq	_WREG32_PIF_PHY1
LBB0_24:
	movq	_PB1_PIF_PWRDOWN_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PIF_PHY1
	movl	%eax, %r12d
	movq	_PLL_RAMP_UP_TIME_1_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	notl	%ebx
	andl	%r12d, %ebx
	movl	$4, %edi
	callq	_PLL_RAMP_UP_TIME_1
	orl	%ebx, %eax
	cmpl	%r12d, %eax
	je	LBB0_26
## %bb.25:
	movq	_PB1_PIF_PWRDOWN_1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%eax, %esi
	callq	_WREG32_PIF_PHY1
LBB0_26:
	movq	_PCIE_LC_LINK_WIDTH_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_RREG32_PCIE_PORT
	movl	%eax, %r12d
	movq	_LC_DYN_LANES_PWR_STATE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	notl	%ebx
	andl	%r12d, %ebx
	movl	$3, %edi
	callq	_LC_DYN_LANES_PWR_STATE
	orl	%ebx, %eax
	cmpl	%r12d, %eax
	je	LBB0_28
## %bb.27:
	movl	(%r13), %edi
	movl	%eax, %esi
	callq	_WREG32_PCIE_PORT
LBB0_28:
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	movl	4(%rbx), %eax
	movq	_CHIP_BARTS@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jl	LBB0_33
## %bb.29:
	movq	_PB0_PIF_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PIF_PHY0
	movl	%eax, %r12d
	movq	_LS2_EXIT_TIME_MASK@GOTPCREL(%rip), %r13
	movl	(%r13), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	$1, %edi
	callq	_LS2_EXIT_TIME
	orl	%ebx, %eax
	cmpl	%r12d, %eax
	je	LBB0_31
## %bb.30:
	movq	_PB0_PIF_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%eax, %esi
	callq	_WREG32_PIF_PHY0
LBB0_31:
	movq	_PB1_PIF_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PIF_PHY1
	movl	%eax, %r12d
	movl	(%r13), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	$1, %edi
	callq	_LS2_EXIT_TIME
	orl	%ebx, %eax
	cmpl	%r12d, %eax
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	je	LBB0_33
## %bb.32:
	movq	_PB1_PIF_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%eax, %esi
	callq	_WREG32_PIF_PHY1
LBB0_33:
	orl	%r14d, %r15d
	movl	4(%rbx), %ecx
	xorl	%eax, %eax
	movq	_CHIP_BARTS@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %ecx
	jge	LBB0_35
## %bb.34:
	movq	_LC_PMI_TO_L1_DIS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_35:
	orl	%eax, %r15d
	cmpl	-52(%rbp), %r15d                ## 4-byte Folded Reload
	jne	LBB0_37
LBB0_36:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_37:
	movq	_PCIE_LC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r15d, %esi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_PCIE_PORT               ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_radeon_aspm,8,3                ## @radeon_aspm
	.comm	_RADEON_IS_PCIE,4,2             ## @RADEON_IS_PCIE
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
	.comm	_PB0_PIF_PAIRING,4,2            ## @PB0_PIF_PAIRING
	.comm	_MULTI_PIF,4,2                  ## @MULTI_PIF
	.comm	_PB1_PIF_PAIRING,4,2            ## @PB1_PIF_PAIRING
	.comm	_PCIE_LC_CNTL,4,2               ## @PCIE_LC_CNTL
	.comm	_LC_L0S_INACTIVITY_MASK,4,2     ## @LC_L0S_INACTIVITY_MASK
	.comm	_LC_L1_INACTIVITY_MASK,4,2      ## @LC_L1_INACTIVITY_MASK
	.comm	_CHIP_BARTS,4,2                 ## @CHIP_BARTS
	.comm	_PB0_PIF_PWRDOWN_0,4,2          ## @PB0_PIF_PWRDOWN_0
	.comm	_PLL_POWER_STATE_IN_OFF_0_MASK,4,2 ## @PLL_POWER_STATE_IN_OFF_0_MASK
	.comm	_PLL_POWER_STATE_IN_TXS2_0_MASK,4,2 ## @PLL_POWER_STATE_IN_TXS2_0_MASK
	.comm	_PB0_PIF_PWRDOWN_1,4,2          ## @PB0_PIF_PWRDOWN_1
	.comm	_PLL_POWER_STATE_IN_OFF_1_MASK,4,2 ## @PLL_POWER_STATE_IN_OFF_1_MASK
	.comm	_PLL_POWER_STATE_IN_TXS2_1_MASK,4,2 ## @PLL_POWER_STATE_IN_TXS2_1_MASK
	.comm	_PB1_PIF_PWRDOWN_0,4,2          ## @PB1_PIF_PWRDOWN_0
	.comm	_PB1_PIF_PWRDOWN_1,4,2          ## @PB1_PIF_PWRDOWN_1
	.comm	_PLL_RAMP_UP_TIME_0_MASK,4,2    ## @PLL_RAMP_UP_TIME_0_MASK
	.comm	_PLL_RAMP_UP_TIME_1_MASK,4,2    ## @PLL_RAMP_UP_TIME_1_MASK
	.comm	_PCIE_LC_LINK_WIDTH_CNTL,4,2    ## @PCIE_LC_LINK_WIDTH_CNTL
	.comm	_LC_DYN_LANES_PWR_STATE_MASK,4,2 ## @LC_DYN_LANES_PWR_STATE_MASK
	.comm	_PB0_PIF_CNTL,4,2               ## @PB0_PIF_CNTL
	.comm	_LS2_EXIT_TIME_MASK,4,2         ## @LS2_EXIT_TIME_MASK
	.comm	_PB1_PIF_CNTL,4,2               ## @PB1_PIF_CNTL
	.comm	_LC_PMI_TO_L1_DIS,4,2           ## @LC_PMI_TO_L1_DIS
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_evergreen_program_aspm         ; -- Begin function evergreen_program_aspm
	.p2align	2
_evergreen_program_aspm:                ; @evergreen_program_aspm
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
Lloh0:
	adrp	x8, _radeon_aspm@GOTPAGE
Lloh1:
	ldr	x8, [x8, _radeon_aspm@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	cbz	x8, LBB0_33
; %bb.1:
	mov	x19, x0
	ldr	w21, [x0]
Lloh3:
	adrp	x8, _RADEON_IS_PCIE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _RADEON_IS_PCIE@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	tst	w8, w21
	b.eq	LBB0_33
; %bb.2:
	ldr	w20, [x19, #4]
Lloh6:
	adrp	x8, _RADEON_IS_IGP@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh8:
	ldr	w24, [x8]
Lloh9:
	adrp	x23, _PB0_PIF_PAIRING@GOTPAGE
Lloh10:
	ldr	x23, [x23, _PB0_PIF_PAIRING@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32_PIF_PHY0
Lloh11:
	adrp	x22, _MULTI_PIF@GOTPAGE
Lloh12:
	ldr	x22, [x22, _MULTI_PIF@GOTPAGEOFF]
	ands	w21, w24, w21
	ldr	w8, [x22]
	bic	w9, w0, w8
	orr	w8, w8, w0
	csel	w1, w8, w9, eq
	cmp	w1, w0
	b.eq	LBB0_4
; %bb.3:
	ldr	w0, [x23]
	bl	_WREG32_PIF_PHY0
LBB0_4:
	sub	w20, w20, #137
Lloh13:
	adrp	x23, _PB1_PIF_PAIRING@GOTPAGE
Lloh14:
	ldr	x23, [x23, _PB1_PIF_PAIRING@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32_PIF_PHY1
	ldr	w8, [x22]
	bic	w9, w0, w8
	orr	w8, w8, w0
	cmp	w21, #0
	csel	w1, w8, w9, eq
	cmp	w1, w0
	b.eq	LBB0_6
; %bb.5:
	ldr	w0, [x23]
	bl	_WREG32_PIF_PHY1
LBB0_6:
Lloh15:
	adrp	x8, _PCIE_LC_CNTL@GOTPAGE
Lloh16:
	ldr	x8, [x8, _PCIE_LC_CNTL@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	bl	_RREG32_PCIE_PORT
Lloh18:
	adrp	x8, _LC_L0S_INACTIVITY_MASK@GOTPAGE
Lloh19:
	ldr	x8, [x8, _LC_L0S_INACTIVITY_MASK@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
Lloh21:
	adrp	x9, _LC_L1_INACTIVITY_MASK@GOTPAGE
Lloh22:
	ldr	x9, [x9, _LC_L1_INACTIVITY_MASK@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	orr	w8, w9, w8
	str	w0, [sp, #12]                   ; 4-byte Folded Spill
	bic	w26, w0, w8
Lloh24:
	adrp	x21, _CHIP_BARTS@GOTPAGE
Lloh25:
	ldr	x21, [x21, _CHIP_BARTS@GOTPAGEOFF]
	cmn	w20, #10
	b.hi	LBB0_8
; %bb.7:
	ldr	w8, [x19, #4]
	ldr	w9, [x21]
	mov	w10, #7
	mov	w11, #3
	cmp	w8, w9
	csel	w0, w11, w10, lt
	bl	_LC_L0S_INACTIVITY
	orr	w26, w0, w26
LBB0_8:
	ldr	w8, [x19, #4]
	ldr	w9, [x21]
	cmp	w8, w9
	mov	w8, #7
	cinc	w0, w8, lt
	bl	_LC_L1_INACTIVITY
	str	w0, [sp, #8]                    ; 4-byte Folded Spill
Lloh26:
	adrp	x24, _PB0_PIF_PWRDOWN_0@GOTPAGE
Lloh27:
	ldr	x24, [x24, _PB0_PIF_PWRDOWN_0@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_RREG32_PIF_PHY0
	mov	x22, x0
Lloh28:
	adrp	x21, _PLL_POWER_STATE_IN_OFF_0_MASK@GOTPAGE
Lloh29:
	ldr	x21, [x21, _PLL_POWER_STATE_IN_OFF_0_MASK@GOTPAGEOFF]
	ldr	w8, [x21]
Lloh30:
	adrp	x25, _PLL_POWER_STATE_IN_TXS2_0_MASK@GOTPAGE
Lloh31:
	ldr	x25, [x25, _PLL_POWER_STATE_IN_TXS2_0_MASK@GOTPAGEOFF]
	ldr	w9, [x25]
	orr	w8, w9, w8
	bic	w20, w0, w8
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_OFF_0
	mov	x23, x0
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_TXS2_0
	orr	w8, w0, w23
	orr	w1, w8, w20
	cmp	w1, w22
	b.eq	LBB0_10
; %bb.9:
	ldr	w0, [x24]
	bl	_WREG32_PIF_PHY0
LBB0_10:
Lloh32:
	adrp	x28, _PB0_PIF_PWRDOWN_1@GOTPAGE
Lloh33:
	ldr	x28, [x28, _PB0_PIF_PWRDOWN_1@GOTPAGEOFF]
	ldr	w0, [x28]
	bl	_RREG32_PIF_PHY0
	mov	x22, x0
Lloh34:
	adrp	x20, _PLL_POWER_STATE_IN_OFF_1_MASK@GOTPAGE
Lloh35:
	ldr	x20, [x20, _PLL_POWER_STATE_IN_OFF_1_MASK@GOTPAGEOFF]
	ldr	w8, [x20]
Lloh36:
	adrp	x27, _PLL_POWER_STATE_IN_TXS2_1_MASK@GOTPAGE
Lloh37:
	ldr	x27, [x27, _PLL_POWER_STATE_IN_TXS2_1_MASK@GOTPAGEOFF]
	ldr	w9, [x27]
	orr	w8, w9, w8
	bic	w24, w0, w8
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_OFF_1
	mov	x23, x0
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_TXS2_1
	orr	w8, w0, w23
	orr	w1, w8, w24
	cmp	w1, w22
	b.eq	LBB0_12
; %bb.11:
	ldr	w0, [x28]
	bl	_WREG32_PIF_PHY0
LBB0_12:
Lloh38:
	adrp	x24, _PB1_PIF_PWRDOWN_0@GOTPAGE
Lloh39:
	ldr	x24, [x24, _PB1_PIF_PWRDOWN_0@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_RREG32_PIF_PHY1
	mov	x22, x0
	ldr	w8, [x21]
	ldr	w9, [x25]
	orr	w8, w9, w8
	bic	w21, w0, w8
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_OFF_0
	mov	x23, x0
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_TXS2_0
	orr	w8, w0, w23
	orr	w1, w8, w21
	cmp	w1, w22
	b.eq	LBB0_14
; %bb.13:
	ldr	w0, [x24]
	bl	_WREG32_PIF_PHY1
LBB0_14:
Lloh40:
	adrp	x21, _PB1_PIF_PWRDOWN_1@GOTPAGE
Lloh41:
	ldr	x21, [x21, _PB1_PIF_PWRDOWN_1@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32_PIF_PHY1
	mov	x22, x0
	ldr	w8, [x20]
	ldr	w9, [x27]
	orr	w8, w9, w8
	bic	w20, w0, w8
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_OFF_1
	mov	x23, x0
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_TXS2_1
	orr	w8, w0, w23
	orr	w1, w8, w20
	cmp	w1, w22
	b.eq	LBB0_16
; %bb.15:
	ldr	w0, [x21]
	bl	_WREG32_PIF_PHY1
LBB0_16:
	ldr	w8, [x19, #4]
Lloh42:
	adrp	x27, _CHIP_BARTS@GOTPAGE
Lloh43:
	ldr	x27, [x27, _CHIP_BARTS@GOTPAGEOFF]
	ldr	w9, [x27]
	cmp	w8, w9
	b.lt	LBB0_25
; %bb.17:
Lloh44:
	adrp	x25, _PB0_PIF_PWRDOWN_0@GOTPAGE
Lloh45:
	ldr	x25, [x25, _PB0_PIF_PWRDOWN_0@GOTPAGEOFF]
	ldr	w0, [x25]
	bl	_RREG32_PIF_PHY0
	mov	x22, x0
Lloh46:
	adrp	x20, _PLL_RAMP_UP_TIME_0_MASK@GOTPAGE
Lloh47:
	ldr	x20, [x20, _PLL_RAMP_UP_TIME_0_MASK@GOTPAGEOFF]
	ldr	w8, [x20]
	bic	w23, w0, w8
	mov	w0, #4
	bl	_PLL_RAMP_UP_TIME_0
	orr	w1, w23, w0
	cmp	w1, w22
	b.eq	LBB0_19
; %bb.18:
	ldr	w0, [x25]
	bl	_WREG32_PIF_PHY0
LBB0_19:
	ldr	w0, [x28]
	bl	_RREG32_PIF_PHY0
	mov	x22, x0
Lloh48:
	adrp	x23, _PLL_RAMP_UP_TIME_1_MASK@GOTPAGE
Lloh49:
	ldr	x23, [x23, _PLL_RAMP_UP_TIME_1_MASK@GOTPAGEOFF]
	ldr	w8, [x23]
	bic	w25, w0, w8
	mov	w0, #4
	bl	_PLL_RAMP_UP_TIME_1
	orr	w1, w25, w0
	cmp	w1, w22
	b.eq	LBB0_21
; %bb.20:
	ldr	w0, [x28]
	bl	_WREG32_PIF_PHY0
LBB0_21:
	ldr	w0, [x24]
	bl	_RREG32_PIF_PHY1
	mov	x22, x0
	ldr	w8, [x20]
	bic	w20, w0, w8
	mov	w0, #4
	bl	_PLL_RAMP_UP_TIME_0
	orr	w1, w20, w0
	cmp	w1, w22
	b.eq	LBB0_23
; %bb.22:
	ldr	w0, [x24]
	bl	_WREG32_PIF_PHY1
LBB0_23:
	ldr	w0, [x21]
	bl	_RREG32_PIF_PHY1
	mov	x22, x0
	ldr	w8, [x23]
	bic	w20, w0, w8
	mov	w0, #4
	bl	_PLL_RAMP_UP_TIME_1
	orr	w1, w20, w0
	cmp	w1, w22
	b.eq	LBB0_25
; %bb.24:
	ldr	w0, [x21]
	bl	_WREG32_PIF_PHY1
LBB0_25:
Lloh50:
	adrp	x20, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGE
Lloh51:
	ldr	x20, [x20, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PCIE_PORT
	mov	x22, x0
Lloh52:
	adrp	x8, _LC_DYN_LANES_PWR_STATE_MASK@GOTPAGE
Lloh53:
	ldr	x8, [x8, _LC_DYN_LANES_PWR_STATE_MASK@GOTPAGEOFF]
Lloh54:
	ldr	w8, [x8]
	bic	w21, w0, w8
	mov	w0, #3
	bl	_LC_DYN_LANES_PWR_STATE
	orr	w1, w21, w0
	cmp	w1, w22
	b.eq	LBB0_27
; %bb.26:
	ldr	w0, [x20]
	bl	_WREG32_PCIE_PORT
LBB0_27:
	ldr	w8, [sp, #8]                    ; 4-byte Folded Reload
	orr	w20, w8, w26
	ldr	w8, [x19, #4]
	ldr	w9, [x27]
	cmp	w8, w9
	b.lt	LBB0_32
; %bb.28:
Lloh55:
	adrp	x23, _PB0_PIF_CNTL@GOTPAGE
Lloh56:
	ldr	x23, [x23, _PB0_PIF_CNTL@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32_PIF_PHY0
	mov	x21, x0
Lloh57:
	adrp	x22, _LS2_EXIT_TIME_MASK@GOTPAGE
Lloh58:
	ldr	x22, [x22, _LS2_EXIT_TIME_MASK@GOTPAGEOFF]
	ldr	w8, [x22]
	bic	w24, w0, w8
	mov	w0, #1
	bl	_LS2_EXIT_TIME
	orr	w1, w24, w0
	cmp	w1, w21
	b.eq	LBB0_30
; %bb.29:
	ldr	w0, [x23]
	bl	_WREG32_PIF_PHY0
LBB0_30:
Lloh59:
	adrp	x23, _PB1_PIF_CNTL@GOTPAGE
Lloh60:
	ldr	x23, [x23, _PB1_PIF_CNTL@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32_PIF_PHY1
	mov	x21, x0
	ldr	w8, [x22]
	bic	w22, w0, w8
	mov	w0, #1
	bl	_LS2_EXIT_TIME
	orr	w1, w22, w0
	cmp	w1, w21
	b.eq	LBB0_32
; %bb.31:
	ldr	w0, [x23]
	bl	_WREG32_PIF_PHY1
LBB0_32:
	ldr	w8, [x19, #4]
Lloh61:
	adrp	x9, _LC_PMI_TO_L1_DIS@GOTPAGE
Lloh62:
	ldr	x9, [x9, _LC_PMI_TO_L1_DIS@GOTPAGEOFF]
	ldr	w10, [x27]
Lloh63:
	ldr	w9, [x9]
	cmp	w8, w10
	csel	w8, w9, wzr, lt
	orr	w1, w20, w8
	ldr	w8, [sp, #12]                   ; 4-byte Folded Reload
	cmp	w1, w8
	b.ne	LBB0_34
LBB0_33:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
LBB0_34:
Lloh64:
	adrp	x8, _PCIE_LC_CNTL@GOTPAGE
Lloh65:
	ldr	x8, [x8, _PCIE_LC_CNTL@GOTPAGEOFF]
Lloh66:
	ldr	w0, [x8]
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	b	_WREG32_PCIE_PORT
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.cfi_endproc
                                        ; -- End function
	.comm	_radeon_aspm,8,3                ; @radeon_aspm
	.comm	_RADEON_IS_PCIE,4,2             ; @RADEON_IS_PCIE
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
	.comm	_PB0_PIF_PAIRING,4,2            ; @PB0_PIF_PAIRING
	.comm	_MULTI_PIF,4,2                  ; @MULTI_PIF
	.comm	_PB1_PIF_PAIRING,4,2            ; @PB1_PIF_PAIRING
	.comm	_PCIE_LC_CNTL,4,2               ; @PCIE_LC_CNTL
	.comm	_LC_L0S_INACTIVITY_MASK,4,2     ; @LC_L0S_INACTIVITY_MASK
	.comm	_LC_L1_INACTIVITY_MASK,4,2      ; @LC_L1_INACTIVITY_MASK
	.comm	_CHIP_BARTS,4,2                 ; @CHIP_BARTS
	.comm	_PB0_PIF_PWRDOWN_0,4,2          ; @PB0_PIF_PWRDOWN_0
	.comm	_PLL_POWER_STATE_IN_OFF_0_MASK,4,2 ; @PLL_POWER_STATE_IN_OFF_0_MASK
	.comm	_PLL_POWER_STATE_IN_TXS2_0_MASK,4,2 ; @PLL_POWER_STATE_IN_TXS2_0_MASK
	.comm	_PB0_PIF_PWRDOWN_1,4,2          ; @PB0_PIF_PWRDOWN_1
	.comm	_PLL_POWER_STATE_IN_OFF_1_MASK,4,2 ; @PLL_POWER_STATE_IN_OFF_1_MASK
	.comm	_PLL_POWER_STATE_IN_TXS2_1_MASK,4,2 ; @PLL_POWER_STATE_IN_TXS2_1_MASK
	.comm	_PB1_PIF_PWRDOWN_0,4,2          ; @PB1_PIF_PWRDOWN_0
	.comm	_PB1_PIF_PWRDOWN_1,4,2          ; @PB1_PIF_PWRDOWN_1
	.comm	_PLL_RAMP_UP_TIME_0_MASK,4,2    ; @PLL_RAMP_UP_TIME_0_MASK
	.comm	_PLL_RAMP_UP_TIME_1_MASK,4,2    ; @PLL_RAMP_UP_TIME_1_MASK
	.comm	_PCIE_LC_LINK_WIDTH_CNTL,4,2    ; @PCIE_LC_LINK_WIDTH_CNTL
	.comm	_LC_DYN_LANES_PWR_STATE_MASK,4,2 ; @LC_DYN_LANES_PWR_STATE_MASK
	.comm	_PB0_PIF_CNTL,4,2               ; @PB0_PIF_CNTL
	.comm	_LS2_EXIT_TIME_MASK,4,2         ; @LS2_EXIT_TIME_MASK
	.comm	_PB1_PIF_CNTL,4,2               ; @PB1_PIF_CNTL
	.comm	_LC_PMI_TO_L1_DIS,4,2           ; @LC_PMI_TO_L1_DIS
.subsections_via_symbols
