	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v10_0_cp_compute_load_microcode
_gfx_v10_0_cp_compute_load_microcode:   ## @gfx_v10_0_cp_compute_load_microcode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	cmpq	$0, 8(%rdi)
	je	LBB0_1
## %bb.2:
	movq	%rdi, %rbx
	xorl	%esi, %esi
	callq	_gfx_v10_0_cp_compute_enable
	movq	8(%rbx), %rax
	movq	(%rax), %r14
	leaq	8(%r14), %rdi
	callq	_amdgpu_ucode_print_gfx_hdr
	movq	%rbx, -48(%rbp)                 ## 8-byte Spill
	movq	8(%rbx), %rax
	movq	(%rax), %rbx
	movq	%r14, -56(%rbp)                 ## 8-byte Spill
	movl	8(%r14), %edi
	callq	_le32_to_cpu
	movq	%rax, %r12
	addq	%rbx, %r12
	movq	_GC@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movq	_mmCP_CPC_IC_OP_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_CP_CPC_IC_OP_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_INVALIDATE_CACHE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r14), %edi
	movl	(%r13), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	$50000, %r14d                   ## imm = 0xC350
	movq	_INVALIDATE_CACHE_COMPLETE@GOTPCREL(%rip), %r15
	.p2align	4, 0x90
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movq	_GC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r13), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	(%rbx), %esi
	movl	(%r15), %edx
	movl	%eax, %edi
	callq	_REG_GET_FIELD
	cmpl	$1, %eax
	je	LBB0_6
## %bb.4:                               ##   in Loop: Header=BB0_3 Depth=1
	movl	$1, %edi
	callq	_udelay
	decl	%r14d
	jne	LBB0_3
## %bb.5:
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movl	24(%rax), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
LBB0_1:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_12
LBB0_6:
	movq	_amdgpu_emu_mode@GOTPCREL(%rip), %rax
	cmpl	$1, (%rax)
	movq	-48(%rbp), %r15                 ## 8-byte Reload
	jne	LBB0_8
## %bb.7:
	movq	16(%r15), %rax
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	*(%rax)
LBB0_8:
	movq	_GC@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movq	_mmCP_CPC_IC_BASE_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_CP_CPC_IC_BASE_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_CACHE_POLICY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_EXE_DISABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_ADDRESS_CLAMP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r13), %edi
	movl	(%r14), %edx
	movq	%r13, %r14
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmCP_CPC_IC_BASE_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	$-4096, %ecx                    ## imm = 0xF000
	andl	4(%r15), %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r13), %ebx
	movq	_mmCP_CPC_IC_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	4(%r15), %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r13d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmCP_MEC_ME1_UCODE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	cmpl	$0, (%rcx)
	je	LBB0_11
## %bb.9:
	xorl	%ebx, %ebx
	movq	_mmCP_MEC_ME1_UCODE_DATA@GOTPCREL(%rip), %r15
	.p2align	4, 0x90
LBB0_10:                                ## =>This Inner Loop Header: Depth=1
	movq	_GC@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	(%r15), %r13d
	movslq	4(%rcx), %rax
	leaq	(%r12,%rax,4), %rdi
	callq	_le32_to_cpup
	movl	%r14d, %edi
	movq	_GC@GOTPCREL(%rip), %r14
	xorl	%esi, %esi
	movl	%r13d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	incq	%rbx
	movl	(%rcx), %eax
	addq	$4, %r12
	cmpq	%rax, %rbx
	jb	LBB0_10
LBB0_11:
	movl	(%r14), %edi
	movq	_mmCP_MEC_ME1_UCODE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	xorl	%eax, %eax
LBB0_12:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_GC,4,2                         ## @GC
	.comm	_mmCP_CPC_IC_OP_CNTL,4,2        ## @mmCP_CPC_IC_OP_CNTL
	.comm	_CP_CPC_IC_OP_CNTL,4,2          ## @CP_CPC_IC_OP_CNTL
	.comm	_INVALIDATE_CACHE,4,2           ## @INVALIDATE_CACHE
	.comm	_INVALIDATE_CACHE_COMPLETE,4,2  ## @INVALIDATE_CACHE_COMPLETE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"failed to invalidate instruction cache\n"

	.comm	_amdgpu_emu_mode,4,2            ## @amdgpu_emu_mode
	.comm	_mmCP_CPC_IC_BASE_CNTL,4,2      ## @mmCP_CPC_IC_BASE_CNTL
	.comm	_CP_CPC_IC_BASE_CNTL,4,2        ## @CP_CPC_IC_BASE_CNTL
	.comm	_CACHE_POLICY,4,2               ## @CACHE_POLICY
	.comm	_EXE_DISABLE,4,2                ## @EXE_DISABLE
	.comm	_ADDRESS_CLAMP,4,2              ## @ADDRESS_CLAMP
	.comm	_mmCP_CPC_IC_BASE_LO,4,2        ## @mmCP_CPC_IC_BASE_LO
	.comm	_mmCP_CPC_IC_BASE_HI,4,2        ## @mmCP_CPC_IC_BASE_HI
	.comm	_mmCP_MEC_ME1_UCODE_ADDR,4,2    ## @mmCP_MEC_ME1_UCODE_ADDR
	.comm	_mmCP_MEC_ME1_UCODE_DATA,4,2    ## @mmCP_MEC_ME1_UCODE_DATA
	.no_dead_strip	_gfx_v10_0_cp_compute_load_microcode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v10_0_cp_compute_load_microcode
_gfx_v10_0_cp_compute_load_microcode:   ; @gfx_v10_0_cp_compute_load_microcode
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	ldr	x8, [x0, #8]
	cbz	x8, LBB0_5
; %bb.1:
	mov	x19, x0
	mov	w1, #0
	bl	_gfx_v10_0_cp_compute_enable
	ldr	x8, [x19, #8]
	ldr	x22, [x8]
	add	x0, x22, #8
	bl	_amdgpu_ucode_print_gfx_hdr
	ldr	x8, [x19, #8]
	ldr	x20, [x8]
	ldr	w0, [x22, #8]
	bl	_le32_to_cpu
	add	x23, x0, x20
Lloh0:
	adrp	x24, _GC@GOTPAGE
Lloh1:
	ldr	x24, [x24, _GC@GOTPAGEOFF]
	ldr	w0, [x24]
Lloh2:
	adrp	x20, _mmCP_CPC_IC_OP_CNTL@GOTPAGE
Lloh3:
	ldr	x20, [x20, _mmCP_CPC_IC_OP_CNTL@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh4:
	adrp	x21, _CP_CPC_IC_OP_CNTL@GOTPAGE
Lloh5:
	ldr	x21, [x21, _CP_CPC_IC_OP_CNTL@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh6:
	adrp	x8, _INVALIDATE_CACHE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _INVALIDATE_CACHE@GOTPAGEOFF]
Lloh8:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x24]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_WREG32_SOC15
	mov	w25, #50000
Lloh9:
	adrp	x26, _INVALIDATE_CACHE_COMPLETE@GOTPAGE
Lloh10:
	ldr	x26, [x26, _INVALIDATE_CACHE_COMPLETE@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x24]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_RREG32_SOC15
	ldr	w1, [x21]
	ldr	w2, [x26]
	bl	_REG_GET_FIELD
	cmp	w0, #1
	b.eq	LBB0_6
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	mov	w0, #1
	bl	_udelay
	subs	w25, w25, #1
	b.ne	LBB0_2
; %bb.4:
	ldr	w0, [x19, #24]
Lloh11:
	adrp	x1, l_.str@PAGE
Lloh12:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
LBB0_5:
Lloh13:
	adrp	x8, _EINVAL@GOTPAGE
Lloh14:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_12
LBB0_6:
Lloh16:
	adrp	x8, _amdgpu_emu_mode@GOTPAGE
Lloh17:
	ldr	x8, [x8, _amdgpu_emu_mode@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	cmp	w8, #1
	b.ne	LBB0_8
; %bb.7:
	ldr	x8, [x19, #16]
	ldr	x8, [x8]
	mov	x0, x19
	mov	x1, #0
	blr	x8
LBB0_8:
	ldr	w0, [x24]
Lloh19:
	adrp	x20, _mmCP_CPC_IC_BASE_CNTL@GOTPAGE
Lloh20:
	ldr	x20, [x20, _mmCP_CPC_IC_BASE_CNTL@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh21:
	adrp	x21, _CP_CPC_IC_BASE_CNTL@GOTPAGE
Lloh22:
	ldr	x21, [x21, _CP_CPC_IC_BASE_CNTL@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh23:
	adrp	x8, _CACHE_POLICY@GOTPAGE
Lloh24:
	ldr	x8, [x8, _CACHE_POLICY@GOTPAGEOFF]
Lloh25:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x21]
Lloh26:
	adrp	x8, _EXE_DISABLE@GOTPAGE
Lloh27:
	ldr	x8, [x8, _EXE_DISABLE@GOTPAGEOFF]
Lloh28:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x21]
Lloh29:
	adrp	x8, _ADDRESS_CLAMP@GOTPAGE
Lloh30:
	ldr	x8, [x8, _ADDRESS_CLAMP@GOTPAGEOFF]
Lloh31:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x24]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh32:
	adrp	x8, _mmCP_CPC_IC_BASE_LO@GOTPAGE
Lloh33:
	ldr	x8, [x8, _mmCP_CPC_IC_BASE_LO@GOTPAGEOFF]
Lloh34:
	ldr	w2, [x8]
	ldr	w8, [x19, #4]
	and	w3, w8, #0xfffff000
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w20, [x24]
Lloh35:
	adrp	x8, _mmCP_CPC_IC_BASE_HI@GOTPAGE
Lloh36:
	ldr	x8, [x8, _mmCP_CPC_IC_BASE_HI@GOTPAGEOFF]
Lloh37:
	ldr	w21, [x8]
	ldr	w0, [x19, #4]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh38:
	adrp	x25, _mmCP_MEC_ME1_UCODE_ADDR@GOTPAGE
Lloh39:
	ldr	x25, [x25, _mmCP_MEC_ME1_UCODE_ADDR@GOTPAGEOFF]
	ldr	w2, [x25]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w8, [x22]
	cbz	w8, LBB0_11
; %bb.9:
	mov	x26, #0
Lloh40:
	adrp	x27, _mmCP_MEC_ME1_UCODE_DATA@GOTPAGE
Lloh41:
	ldr	x27, [x27, _mmCP_MEC_ME1_UCODE_DATA@GOTPAGEOFF]
LBB0_10:                                ; =>This Inner Loop Header: Depth=1
	ldr	w20, [x24]
	ldr	w21, [x27]
	ldrsw	x8, [x22, #4]
	add	x0, x23, x8, lsl #2
	bl	_le32_to_cpup
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	add	x26, x26, #1
	ldr	w8, [x22]
	add	x23, x23, #4
	cmp	x26, x8
	b.lo	LBB0_10
LBB0_11:
	ldr	w0, [x24]
	ldr	w2, [x25]
	ldr	w3, [x19]
	mov	w1, #0
	bl	_WREG32_SOC15
	mov	w0, #0
LBB0_12:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh40, Lloh41
	.cfi_endproc
                                        ; -- End function
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_GC,4,2                         ; @GC
	.comm	_mmCP_CPC_IC_OP_CNTL,4,2        ; @mmCP_CPC_IC_OP_CNTL
	.comm	_CP_CPC_IC_OP_CNTL,4,2          ; @CP_CPC_IC_OP_CNTL
	.comm	_INVALIDATE_CACHE,4,2           ; @INVALIDATE_CACHE
	.comm	_INVALIDATE_CACHE_COMPLETE,4,2  ; @INVALIDATE_CACHE_COMPLETE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"failed to invalidate instruction cache\n"

	.comm	_amdgpu_emu_mode,4,2            ; @amdgpu_emu_mode
	.comm	_mmCP_CPC_IC_BASE_CNTL,4,2      ; @mmCP_CPC_IC_BASE_CNTL
	.comm	_CP_CPC_IC_BASE_CNTL,4,2        ; @CP_CPC_IC_BASE_CNTL
	.comm	_CACHE_POLICY,4,2               ; @CACHE_POLICY
	.comm	_EXE_DISABLE,4,2                ; @EXE_DISABLE
	.comm	_ADDRESS_CLAMP,4,2              ; @ADDRESS_CLAMP
	.comm	_mmCP_CPC_IC_BASE_LO,4,2        ; @mmCP_CPC_IC_BASE_LO
	.comm	_mmCP_CPC_IC_BASE_HI,4,2        ; @mmCP_CPC_IC_BASE_HI
	.comm	_mmCP_MEC_ME1_UCODE_ADDR,4,2    ; @mmCP_MEC_ME1_UCODE_ADDR
	.comm	_mmCP_MEC_ME1_UCODE_DATA,4,2    ; @mmCP_MEC_ME1_UCODE_DATA
	.no_dead_strip	_gfx_v10_0_cp_compute_load_microcode
.subsections_via_symbols
