	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function exynos_dsi_set_phy_ctrl
_exynos_dsi_set_phy_ctrl:               ## @exynos_dsi_set_phy_ctrl
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	(%rdi), %rax
	cmpq	$0, 8(%rax)
	je	LBB0_2
## %bb.1:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
LBB0_2:
	movq	%rdi, %r14
	movq	(%rax), %rbx
	movq	_PHYCTRL_ULPS_EXIT@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_PHYCTRL_VREG_LP@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	(%rbx,%rcx,4), %edx
	orl	(%rbx,%rax,4), %edx
	movq	_PHYCTRL_SLEW_UP@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	orl	(%rbx,%rax,4), %edx
	movq	_DSIM_PHYCTRL_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_exynos_dsi_write
	movq	_PHYTIMING_LPX@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_PHYTIMING_HS_EXIT@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	(%rbx,%rcx,4), %edx
	orl	(%rbx,%rax,4), %edx
	movq	_DSIM_PHYTIMING_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_exynos_dsi_write
	movq	_PHYTIMING_CLK_PREPARE@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_PHYTIMING_CLK_ZERO@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	(%rbx,%rcx,4), %edx
	orl	(%rbx,%rax,4), %edx
	movq	_PHYTIMING_CLK_POST@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	orl	(%rbx,%rax,4), %edx
	movq	_PHYTIMING_CLK_TRAIL@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	orl	(%rbx,%rax,4), %edx
	movq	_DSIM_PHYTIMING1_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_exynos_dsi_write
	movq	_PHYTIMING_HS_PREPARE@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_PHYTIMING_HS_ZERO@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	(%rbx,%rcx,4), %edx
	orl	(%rbx,%rax,4), %edx
	movq	_PHYTIMING_HS_TRAIL@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	orl	(%rbx,%rax,4), %edx
	movq	_DSIM_PHYTIMING2_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_exynos_dsi_write               ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PHYCTRL_ULPS_EXIT,8,3          ## @PHYCTRL_ULPS_EXIT
	.comm	_PHYCTRL_VREG_LP,8,3            ## @PHYCTRL_VREG_LP
	.comm	_PHYCTRL_SLEW_UP,8,3            ## @PHYCTRL_SLEW_UP
	.comm	_DSIM_PHYCTRL_REG,4,2           ## @DSIM_PHYCTRL_REG
	.comm	_PHYTIMING_LPX,8,3              ## @PHYTIMING_LPX
	.comm	_PHYTIMING_HS_EXIT,8,3          ## @PHYTIMING_HS_EXIT
	.comm	_DSIM_PHYTIMING_REG,4,2         ## @DSIM_PHYTIMING_REG
	.comm	_PHYTIMING_CLK_PREPARE,8,3      ## @PHYTIMING_CLK_PREPARE
	.comm	_PHYTIMING_CLK_ZERO,8,3         ## @PHYTIMING_CLK_ZERO
	.comm	_PHYTIMING_CLK_POST,8,3         ## @PHYTIMING_CLK_POST
	.comm	_PHYTIMING_CLK_TRAIL,8,3        ## @PHYTIMING_CLK_TRAIL
	.comm	_DSIM_PHYTIMING1_REG,4,2        ## @DSIM_PHYTIMING1_REG
	.comm	_PHYTIMING_HS_PREPARE,8,3       ## @PHYTIMING_HS_PREPARE
	.comm	_PHYTIMING_HS_ZERO,8,3          ## @PHYTIMING_HS_ZERO
	.comm	_PHYTIMING_HS_TRAIL,8,3         ## @PHYTIMING_HS_TRAIL
	.comm	_DSIM_PHYTIMING2_REG,4,2        ## @DSIM_PHYTIMING2_REG
	.no_dead_strip	_exynos_dsi_set_phy_ctrl
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function exynos_dsi_set_phy_ctrl
_exynos_dsi_set_phy_ctrl:               ; @exynos_dsi_set_phy_ctrl
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	x8, [x0]
	ldr	x9, [x8, #8]
	cbz	x9, LBB0_2
; %bb.1:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_2:
	mov	x19, x0
	ldr	x20, [x8]
Lloh0:
	adrp	x8, _PHYCTRL_ULPS_EXIT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PHYCTRL_ULPS_EXIT@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	ldr	w8, [x20, x8, lsl #2]
Lloh3:
	adrp	x9, _PHYCTRL_VREG_LP@GOTPAGE
Lloh4:
	ldr	x9, [x9, _PHYCTRL_VREG_LP@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
	ldr	w9, [x20, x9, lsl #2]
	orr	w8, w9, w8
Lloh6:
	adrp	x9, _PHYCTRL_SLEW_UP@GOTPAGE
Lloh7:
	ldr	x9, [x9, _PHYCTRL_SLEW_UP@GOTPAGEOFF]
Lloh8:
	ldr	x9, [x9]
	ldr	w9, [x20, x9, lsl #2]
	orr	w2, w8, w9
Lloh9:
	adrp	x8, _DSIM_PHYCTRL_REG@GOTPAGE
Lloh10:
	ldr	x8, [x8, _DSIM_PHYCTRL_REG@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	bl	_exynos_dsi_write
Lloh12:
	adrp	x8, _PHYTIMING_LPX@GOTPAGE
Lloh13:
	ldr	x8, [x8, _PHYTIMING_LPX@GOTPAGEOFF]
Lloh14:
	ldr	x8, [x8]
	ldr	w8, [x20, x8, lsl #2]
Lloh15:
	adrp	x9, _PHYTIMING_HS_EXIT@GOTPAGE
Lloh16:
	ldr	x9, [x9, _PHYTIMING_HS_EXIT@GOTPAGEOFF]
Lloh17:
	ldr	x9, [x9]
	ldr	w9, [x20, x9, lsl #2]
	orr	w2, w9, w8
Lloh18:
	adrp	x8, _DSIM_PHYTIMING_REG@GOTPAGE
Lloh19:
	ldr	x8, [x8, _DSIM_PHYTIMING_REG@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_exynos_dsi_write
Lloh21:
	adrp	x8, _PHYTIMING_CLK_PREPARE@GOTPAGE
Lloh22:
	ldr	x8, [x8, _PHYTIMING_CLK_PREPARE@GOTPAGEOFF]
Lloh23:
	ldr	x8, [x8]
	ldr	w8, [x20, x8, lsl #2]
Lloh24:
	adrp	x9, _PHYTIMING_CLK_ZERO@GOTPAGE
Lloh25:
	ldr	x9, [x9, _PHYTIMING_CLK_ZERO@GOTPAGEOFF]
Lloh26:
	ldr	x9, [x9]
	ldr	w9, [x20, x9, lsl #2]
	orr	w8, w9, w8
Lloh27:
	adrp	x9, _PHYTIMING_CLK_POST@GOTPAGE
Lloh28:
	ldr	x9, [x9, _PHYTIMING_CLK_POST@GOTPAGEOFF]
Lloh29:
	ldr	x9, [x9]
	ldr	w9, [x20, x9, lsl #2]
	orr	w8, w8, w9
Lloh30:
	adrp	x9, _PHYTIMING_CLK_TRAIL@GOTPAGE
Lloh31:
	ldr	x9, [x9, _PHYTIMING_CLK_TRAIL@GOTPAGEOFF]
Lloh32:
	ldr	x9, [x9]
	ldr	w9, [x20, x9, lsl #2]
	orr	w2, w8, w9
Lloh33:
	adrp	x8, _DSIM_PHYTIMING1_REG@GOTPAGE
Lloh34:
	ldr	x8, [x8, _DSIM_PHYTIMING1_REG@GOTPAGEOFF]
Lloh35:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_exynos_dsi_write
Lloh36:
	adrp	x8, _PHYTIMING_HS_PREPARE@GOTPAGE
Lloh37:
	ldr	x8, [x8, _PHYTIMING_HS_PREPARE@GOTPAGEOFF]
Lloh38:
	ldr	x8, [x8]
	ldr	w8, [x20, x8, lsl #2]
Lloh39:
	adrp	x9, _PHYTIMING_HS_ZERO@GOTPAGE
Lloh40:
	ldr	x9, [x9, _PHYTIMING_HS_ZERO@GOTPAGEOFF]
Lloh41:
	ldr	x9, [x9]
	ldr	w9, [x20, x9, lsl #2]
	orr	w8, w9, w8
Lloh42:
	adrp	x9, _PHYTIMING_HS_TRAIL@GOTPAGE
Lloh43:
	ldr	x9, [x9, _PHYTIMING_HS_TRAIL@GOTPAGEOFF]
Lloh44:
	ldr	x9, [x9]
	ldr	w9, [x20, x9, lsl #2]
	orr	w2, w8, w9
Lloh45:
	adrp	x8, _DSIM_PHYTIMING2_REG@GOTPAGE
Lloh46:
	ldr	x8, [x8, _DSIM_PHYTIMING2_REG@GOTPAGEOFF]
Lloh47:
	ldr	w1, [x8]
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_exynos_dsi_write
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_PHYCTRL_ULPS_EXIT,8,3          ; @PHYCTRL_ULPS_EXIT
	.comm	_PHYCTRL_VREG_LP,8,3            ; @PHYCTRL_VREG_LP
	.comm	_PHYCTRL_SLEW_UP,8,3            ; @PHYCTRL_SLEW_UP
	.comm	_DSIM_PHYCTRL_REG,4,2           ; @DSIM_PHYCTRL_REG
	.comm	_PHYTIMING_LPX,8,3              ; @PHYTIMING_LPX
	.comm	_PHYTIMING_HS_EXIT,8,3          ; @PHYTIMING_HS_EXIT
	.comm	_DSIM_PHYTIMING_REG,4,2         ; @DSIM_PHYTIMING_REG
	.comm	_PHYTIMING_CLK_PREPARE,8,3      ; @PHYTIMING_CLK_PREPARE
	.comm	_PHYTIMING_CLK_ZERO,8,3         ; @PHYTIMING_CLK_ZERO
	.comm	_PHYTIMING_CLK_POST,8,3         ; @PHYTIMING_CLK_POST
	.comm	_PHYTIMING_CLK_TRAIL,8,3        ; @PHYTIMING_CLK_TRAIL
	.comm	_DSIM_PHYTIMING1_REG,4,2        ; @DSIM_PHYTIMING1_REG
	.comm	_PHYTIMING_HS_PREPARE,8,3       ; @PHYTIMING_HS_PREPARE
	.comm	_PHYTIMING_HS_ZERO,8,3          ; @PHYTIMING_HS_ZERO
	.comm	_PHYTIMING_HS_TRAIL,8,3         ; @PHYTIMING_HS_TRAIL
	.comm	_DSIM_PHYTIMING2_REG,4,2        ; @DSIM_PHYTIMING2_REG
	.no_dead_strip	_exynos_dsi_set_phy_ctrl
.subsections_via_symbols
