	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gmc_v10_0_get_vm_pte_flags
_gmc_v10_0_get_vm_pte_flags:            ## @gmc_v10_0_get_vm_pte_flags
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	_AMDGPU_VM_PAGE_EXECUTABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	_AMDGPU_PTE_EXECUTABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_AMDGPU_VM_PAGE_READABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	_AMDGPU_PTE_READABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_AMDGPU_VM_PAGE_WRITEABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	_AMDGPU_PTE_WRITEABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_AMDGPU_VM_MTYPE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%esi, %eax
	addl	$-128, %eax
	cmpl	$4, %eax
	ja	LBB0_1
## %bb.2:
	cltq
	leaq	l_switch.table.gmc_v10_0_get_vm_pte_flags(%rip), %rcx
	movq	(%rcx,%rax,8), %rax
	jmp	LBB0_3
LBB0_1:
	movq	_MTYPE_NC@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %edi
	callq	_AMDGPU_PTE_MTYPE_NV10
	andl	%r14d, %r13d
	andl	%r14d, %r12d
	movl	-48(%rbp), %ecx                 ## 4-byte Reload
	cmovel	%r12d, %ecx
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	andl	%r14d, %edx
	cmovel	%edx, %r15d
	orl	%ecx, %r15d
	testl	%r13d, %r13d
	cmovel	%r13d, %ebx
	orl	%eax, %ebx
	orl	%r15d, %ebx
	movq	_AMDGPU_VM_PAGE_PRT@GOTPCREL(%rip), %rax
	andl	(%rax), %r14d
	je	LBB0_5
## %bb.4:
	movq	_AMDGPU_PTE_PRT@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
LBB0_5:
	orl	%r14d, %ebx
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_VM_PAGE_EXECUTABLE,4,2  ## @AMDGPU_VM_PAGE_EXECUTABLE
	.comm	_AMDGPU_PTE_EXECUTABLE,4,2      ## @AMDGPU_PTE_EXECUTABLE
	.comm	_AMDGPU_VM_PAGE_READABLE,4,2    ## @AMDGPU_VM_PAGE_READABLE
	.comm	_AMDGPU_PTE_READABLE,4,2        ## @AMDGPU_PTE_READABLE
	.comm	_AMDGPU_VM_PAGE_WRITEABLE,4,2   ## @AMDGPU_VM_PAGE_WRITEABLE
	.comm	_AMDGPU_PTE_WRITEABLE,4,2       ## @AMDGPU_PTE_WRITEABLE
	.comm	_AMDGPU_VM_MTYPE_MASK,4,2       ## @AMDGPU_VM_MTYPE_MASK
	.comm	_MTYPE_NC,4,2                   ## @MTYPE_NC
	.comm	_MTYPE_WC,4,2                   ## @MTYPE_WC
	.comm	_MTYPE_CC,4,2                   ## @MTYPE_CC
	.comm	_MTYPE_UC,4,2                   ## @MTYPE_UC
	.comm	_AMDGPU_VM_PAGE_PRT,4,2         ## @AMDGPU_VM_PAGE_PRT
	.comm	_AMDGPU_PTE_PRT,4,2             ## @AMDGPU_PTE_PRT
	.no_dead_strip	_gmc_v10_0_get_vm_pte_flags
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.gmc_v10_0_get_vm_pte_flags
l_switch.table.gmc_v10_0_get_vm_pte_flags:
	.quad	_MTYPE_WC
	.quad	_MTYPE_UC
	.quad	_MTYPE_NC
	.quad	_MTYPE_NC
	.quad	_MTYPE_CC

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gmc_v10_0_get_vm_pte_flags
_gmc_v10_0_get_vm_pte_flags:            ; @gmc_v10_0_get_vm_pte_flags
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x1
Lloh0:
	adrp	x8, _AMDGPU_VM_PAGE_EXECUTABLE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPU_VM_PAGE_EXECUTABLE@GOTPAGEOFF]
Lloh2:
	ldr	w20, [x8]
Lloh3:
	adrp	x8, _AMDGPU_PTE_EXECUTABLE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _AMDGPU_PTE_EXECUTABLE@GOTPAGEOFF]
Lloh5:
	ldr	w21, [x8]
Lloh6:
	adrp	x8, _AMDGPU_VM_PAGE_READABLE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _AMDGPU_VM_PAGE_READABLE@GOTPAGEOFF]
Lloh8:
	ldr	w22, [x8]
Lloh9:
	adrp	x8, _AMDGPU_PTE_READABLE@GOTPAGE
Lloh10:
	ldr	x8, [x8, _AMDGPU_PTE_READABLE@GOTPAGEOFF]
Lloh11:
	ldr	w23, [x8]
Lloh12:
	adrp	x8, _AMDGPU_VM_PAGE_WRITEABLE@GOTPAGE
Lloh13:
	ldr	x8, [x8, _AMDGPU_VM_PAGE_WRITEABLE@GOTPAGEOFF]
Lloh14:
	ldr	w24, [x8]
Lloh15:
	adrp	x8, _AMDGPU_PTE_WRITEABLE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _AMDGPU_PTE_WRITEABLE@GOTPAGEOFF]
Lloh17:
	ldr	w25, [x8]
Lloh18:
	adrp	x8, _AMDGPU_VM_MTYPE_MASK@GOTPAGE
Lloh19:
	ldr	x8, [x8, _AMDGPU_VM_MTYPE_MASK@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	and	w8, w8, w1
	sub	w8, w8, #128
	cmp	w8, #4
	b.hi	LBB0_2
; %bb.1:
Lloh21:
	adrp	x9, l_switch.table.gmc_v10_0_get_vm_pte_flags@PAGE
Lloh22:
	add	x9, x9, l_switch.table.gmc_v10_0_get_vm_pte_flags@PAGEOFF
	ldr	x8, [x9, w8, sxtw #3]
	b	LBB0_3
LBB0_2:
Lloh23:
	adrp	x8, _MTYPE_NC@GOTPAGE
Lloh24:
	ldr	x8, [x8, _MTYPE_NC@GOTPAGEOFF]
LBB0_3:
	ldr	w0, [x8]
	bl	_AMDGPU_PTE_MTYPE_NV10
	tst	w20, w19
	csel	w8, wzr, w21, eq
	tst	w22, w19
	csel	w9, wzr, w23, eq
	orr	w8, w9, w8
	tst	w24, w19
	csel	w9, wzr, w25, eq
	orr	w8, w8, w9
	orr	w8, w8, w0
Lloh25:
	adrp	x9, _AMDGPU_VM_PAGE_PRT@GOTPAGE
Lloh26:
	ldr	x9, [x9, _AMDGPU_VM_PAGE_PRT@GOTPAGEOFF]
Lloh27:
	adrp	x10, _AMDGPU_PTE_PRT@GOTPAGE
Lloh28:
	ldr	x10, [x10, _AMDGPU_PTE_PRT@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
Lloh30:
	ldr	w10, [x10]
	tst	w9, w19
	csel	w9, wzr, w10, eq
	orr	w0, w8, w9
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh29
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_VM_PAGE_EXECUTABLE,4,2  ; @AMDGPU_VM_PAGE_EXECUTABLE
	.comm	_AMDGPU_PTE_EXECUTABLE,4,2      ; @AMDGPU_PTE_EXECUTABLE
	.comm	_AMDGPU_VM_PAGE_READABLE,4,2    ; @AMDGPU_VM_PAGE_READABLE
	.comm	_AMDGPU_PTE_READABLE,4,2        ; @AMDGPU_PTE_READABLE
	.comm	_AMDGPU_VM_PAGE_WRITEABLE,4,2   ; @AMDGPU_VM_PAGE_WRITEABLE
	.comm	_AMDGPU_PTE_WRITEABLE,4,2       ; @AMDGPU_PTE_WRITEABLE
	.comm	_AMDGPU_VM_MTYPE_MASK,4,2       ; @AMDGPU_VM_MTYPE_MASK
	.comm	_MTYPE_NC,4,2                   ; @MTYPE_NC
	.comm	_MTYPE_WC,4,2                   ; @MTYPE_WC
	.comm	_MTYPE_CC,4,2                   ; @MTYPE_CC
	.comm	_MTYPE_UC,4,2                   ; @MTYPE_UC
	.comm	_AMDGPU_VM_PAGE_PRT,4,2         ; @AMDGPU_VM_PAGE_PRT
	.comm	_AMDGPU_PTE_PRT,4,2             ; @AMDGPU_PTE_PRT
	.no_dead_strip	_gmc_v10_0_get_vm_pte_flags
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.gmc_v10_0_get_vm_pte_flags
l_switch.table.gmc_v10_0_get_vm_pte_flags:
	.quad	_MTYPE_WC
	.quad	_MTYPE_UC
	.quad	_MTYPE_NC
	.quad	_MTYPE_NC
	.quad	_MTYPE_CC

.subsections_via_symbols
