	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_dce120_timing_generator_setup_global_swap_lock ## -- Begin function dce120_timing_generator_setup_global_swap_lock
	.p2align	4, 0x90
_dce120_timing_generator_setup_global_swap_lock: ## @dce120_timing_generator_setup_global_swap_lock
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r15
	movq	%rdi, %rbx
	callq	_DCE110TG_FROM_TG
	movq	%rax, %r12
	movl	8(%rbx), %edi
	movq	_mmCRTC0_CRTC_V_TOTAL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r12), %edx
	callq	_dm_read_reg_soc15
	movq	_CRTC0_CRTC_V_TOTAL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_CRTC_V_TOTAL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%rax, %rdi
	callq	_get_reg_field_value
	movq	%rax, %r14
	movl	8(%rbx), %edi
	movq	_mmCRTC0_CRTC_GSL_WINDOW@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r12), %edx
	xorl	%ecx, %ecx
	callq	_dm_write_reg_soc15
	movq	_DCP0_DCP_GSL_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movq	_DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_FD
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_FD
	movq	(%r15), %rcx
	xorl	%r15d, %r15d
	cmpq	(%rbx), %rcx
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	sete	%r15b
	movq	_DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_FD
                                        ## kill: def $eax killed $eax def $rax
	movq	%rax, -72(%rbp)                 ## 8-byte Spill
	movq	_HFLIP_READY_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	%rax, -64(%rbp)                 ## 8-byte Spill
	movq	_DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_FD
	movl	%eax, %r13d
	movq	_HFLIP_CHECK_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	_DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_FD
	movl	%eax, %ebx
	movq	_DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_FD
                                        ## kill: def $eax killed $eax def $rax
	movl	-52(%rbp), %edi                 ## 4-byte Reload
	movl	$6, %esi
	movl	-48(%rbp), %edx                 ## 4-byte Reload
	movl	$1, %ecx
	movl	-44(%rbp), %r8d                 ## 4-byte Reload
	movl	%r15d, %r9d
	pushq	$1
	pushq	%rax
	pushq	$0
	pushq	%rbx
	pushq	%r12
	pushq	%r13
	pushq	-64(%rbp)                       ## 8-byte Folded Reload
	pushq	-72(%rbp)                       ## 8-byte Folded Reload
	callq	_CRTC_REG_UPDATE_N
	addq	$64, %rsp
	movq	_CRTC0_CRTC_GSL_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_CRTC_GSL_CHECK_LINE_NUM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_FLIP_READY_BACK_LOOKUP@GOTPCREL(%rip), %rax
	subq	(%rax), %r14
	movq	_CRTC_GSL_FORCE_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	_VFLIP_READY_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	movq	%r14, %rdx
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_CRTC_REG_SET_2                 ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_mmCRTC0_CRTC_V_TOTAL,4,2       ## @mmCRTC0_CRTC_V_TOTAL
	.comm	_CRTC0_CRTC_V_TOTAL,4,2         ## @CRTC0_CRTC_V_TOTAL
	.comm	_CRTC_V_TOTAL,4,2               ## @CRTC_V_TOTAL
	.comm	_mmCRTC0_CRTC_GSL_WINDOW,4,2    ## @mmCRTC0_CRTC_GSL_WINDOW
	.comm	_DCP0_DCP_GSL_CONTROL,4,2       ## @DCP0_DCP_GSL_CONTROL
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN,4,2 ## @DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN,4,2 ## @DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY,4,2 ## @DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY
	.comm	_HFLIP_READY_DELAY,4,2          ## @HFLIP_READY_DELAY
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY,4,2 ## @DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY
	.comm	_HFLIP_CHECK_DELAY,4,2          ## @HFLIP_CHECK_DELAY
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE,4,2 ## @DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING,4,2 ## @DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING
	.comm	_CRTC0_CRTC_GSL_CONTROL,4,2     ## @CRTC0_CRTC_GSL_CONTROL
	.comm	_CRTC_GSL_CHECK_LINE_NUM,4,2    ## @CRTC_GSL_CHECK_LINE_NUM
	.comm	_FLIP_READY_BACK_LOOKUP,8,3     ## @FLIP_READY_BACK_LOOKUP
	.comm	_CRTC_GSL_FORCE_DELAY,4,2       ## @CRTC_GSL_FORCE_DELAY
	.comm	_VFLIP_READY_DELAY,4,2          ## @VFLIP_READY_DELAY
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_dce120_timing_generator_setup_global_swap_lock ; -- Begin function dce120_timing_generator_setup_global_swap_lock
	.p2align	2
_dce120_timing_generator_setup_global_swap_lock: ; @dce120_timing_generator_setup_global_swap_lock
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #128
	.cfi_def_cfa_offset 128
	stp	x28, x27, [sp, #32]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #48]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #64]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #80]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #96]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #112]            ; 16-byte Folded Spill
	add	x29, sp, #112
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x1
	mov	x22, x0
	bl	_DCE110TG_FROM_TG
	mov	x20, x0
	ldr	w0, [x22, #8]
Lloh0:
	adrp	x8, _mmCRTC0_CRTC_V_TOTAL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _mmCRTC0_CRTC_V_TOTAL@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	ldr	w2, [x20]
	bl	_dm_read_reg_soc15
Lloh3:
	adrp	x8, _CRTC0_CRTC_V_TOTAL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _CRTC0_CRTC_V_TOTAL@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
Lloh6:
	adrp	x8, _CRTC_V_TOTAL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _CRTC_V_TOTAL@GOTPAGEOFF]
Lloh8:
	ldr	w2, [x8]
	bl	_get_reg_field_value
	mov	x19, x0
	ldr	w0, [x22, #8]
Lloh9:
	adrp	x8, _mmCRTC0_CRTC_GSL_WINDOW@GOTPAGE
Lloh10:
	ldr	x8, [x8, _mmCRTC0_CRTC_GSL_WINDOW@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	ldr	w2, [x20]
	mov	w3, #0
	bl	_dm_write_reg_soc15
Lloh12:
	adrp	x8, _DCP0_DCP_GSL_CONTROL@GOTPAGE
Lloh13:
	ldr	x8, [x8, _DCP0_DCP_GSL_CONTROL@GOTPAGEOFF]
Lloh14:
	ldr	w20, [x8]
Lloh15:
	adrp	x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN@GOTPAGE
Lloh16:
	ldr	x8, [x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	bl	_FD
	mov	x23, x0
Lloh18:
	adrp	x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN@GOTPAGE
Lloh19:
	ldr	x8, [x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
	bl	_FD
	mov	x24, x0
	ldr	x8, [x21]
	ldr	x9, [x22]
	cmp	x8, x9
	cset	w21, eq
Lloh21:
	adrp	x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY@GOTPAGE
Lloh22:
	ldr	x8, [x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY@GOTPAGEOFF]
Lloh23:
	ldr	w0, [x8]
	bl	_FD
	mov	x22, x0
Lloh24:
	adrp	x8, _HFLIP_READY_DELAY@GOTPAGE
Lloh25:
	ldr	x8, [x8, _HFLIP_READY_DELAY@GOTPAGEOFF]
Lloh26:
	ldr	w25, [x8]
Lloh27:
	adrp	x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY@GOTPAGE
Lloh28:
	ldr	x8, [x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	bl	_FD
	mov	x26, x0
Lloh30:
	adrp	x8, _HFLIP_CHECK_DELAY@GOTPAGE
Lloh31:
	ldr	x8, [x8, _HFLIP_CHECK_DELAY@GOTPAGEOFF]
Lloh32:
	ldr	w28, [x8]
Lloh33:
	adrp	x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE@GOTPAGE
Lloh34:
	ldr	x8, [x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	bl	_FD
	mov	x27, x0
Lloh36:
	adrp	x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING@GOTPAGE
Lloh37:
	ldr	x8, [x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING@GOTPAGEOFF]
Lloh38:
	ldr	w0, [x8]
	bl	_FD
	mov	w8, #1
	stp	w0, w8, [sp, #16]
	stp	w27, wzr, [sp, #8]
	stp	w26, w28, [sp]
	mov	x0, x20
	mov	w1, #6
	mov	x2, x23
	mov	w3, #1
	mov	x4, x24
	mov	x5, x21
	mov	x6, x22
	mov	x7, x25
	bl	_CRTC_REG_UPDATE_N
Lloh39:
	adrp	x8, _CRTC0_CRTC_GSL_CONTROL@GOTPAGE
Lloh40:
	ldr	x8, [x8, _CRTC0_CRTC_GSL_CONTROL@GOTPAGEOFF]
Lloh41:
	ldr	w0, [x8]
Lloh42:
	adrp	x8, _CRTC_GSL_CHECK_LINE_NUM@GOTPAGE
Lloh43:
	ldr	x8, [x8, _CRTC_GSL_CHECK_LINE_NUM@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x8]
Lloh45:
	adrp	x8, _FLIP_READY_BACK_LOOKUP@GOTPAGE
Lloh46:
	ldr	x8, [x8, _FLIP_READY_BACK_LOOKUP@GOTPAGEOFF]
Lloh47:
	ldr	x8, [x8]
	sub	x2, x19, x8
Lloh48:
	adrp	x8, _CRTC_GSL_FORCE_DELAY@GOTPAGE
Lloh49:
	ldr	x8, [x8, _CRTC_GSL_FORCE_DELAY@GOTPAGEOFF]
Lloh50:
	ldr	w3, [x8]
Lloh51:
	adrp	x8, _VFLIP_READY_DELAY@GOTPAGE
Lloh52:
	ldr	x8, [x8, _VFLIP_READY_DELAY@GOTPAGEOFF]
Lloh53:
	ldr	w4, [x8]
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	b	_CRTC_REG_SET_2
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_mmCRTC0_CRTC_V_TOTAL,4,2       ; @mmCRTC0_CRTC_V_TOTAL
	.comm	_CRTC0_CRTC_V_TOTAL,4,2         ; @CRTC0_CRTC_V_TOTAL
	.comm	_CRTC_V_TOTAL,4,2               ; @CRTC_V_TOTAL
	.comm	_mmCRTC0_CRTC_GSL_WINDOW,4,2    ; @mmCRTC0_CRTC_GSL_WINDOW
	.comm	_DCP0_DCP_GSL_CONTROL,4,2       ; @DCP0_DCP_GSL_CONTROL
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN,4,2 ; @DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN,4,2 ; @DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY,4,2 ; @DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY
	.comm	_HFLIP_READY_DELAY,4,2          ; @HFLIP_READY_DELAY
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY,4,2 ; @DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY
	.comm	_HFLIP_CHECK_DELAY,4,2          ; @HFLIP_CHECK_DELAY
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE,4,2 ; @DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING,4,2 ; @DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING
	.comm	_CRTC0_CRTC_GSL_CONTROL,4,2     ; @CRTC0_CRTC_GSL_CONTROL
	.comm	_CRTC_GSL_CHECK_LINE_NUM,4,2    ; @CRTC_GSL_CHECK_LINE_NUM
	.comm	_FLIP_READY_BACK_LOOKUP,8,3     ; @FLIP_READY_BACK_LOOKUP
	.comm	_CRTC_GSL_FORCE_DELAY,4,2       ; @CRTC_GSL_FORCE_DELAY
	.comm	_VFLIP_READY_DELAY,4,2          ; @VFLIP_READY_DELAY
.subsections_via_symbols
