	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function r600_pcie_gen2_enable
_r600_pcie_gen2_enable:                 ## @r600_pcie_gen2_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_radeon_pcie_gen2@GOTPCREL(%rip), %rax
	cmpq	$0, (%rax)
	je	LBB0_24
## %bb.1:
	movq	%rdi, %rbx
	movl	(%rdi), %eax
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_2
LBB0_24:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	movq	_RADEON_IS_PCIE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_24
## %bb.3:
	movq	%rbx, %rdi
	callq	_ASIC_IS_X2
	testq	%rax, %rax
	jne	LBB0_24
## %bb.4:
	movq	8(%rbx), %rax
	movq	_CHIP_R600@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jle	LBB0_24
## %bb.5:
	movq	16(%rbx), %rax
	movq	(%rax), %rax
	movq	(%rax), %rax
	movq	_PCIE_SPEED_5_0GT@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_7
## %bb.6:
	movq	_PCIE_SPEED_8_0GT@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_24
LBB0_7:
	movq	_PCIE_LC_SPEED_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_CURRENT_DATA_RATE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_8
## %bb.25:
	leaq	L_.str(%rip), %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_DRM_INFO                       ## TAILCALL
LBB0_8:
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_INFO
	movq	8(%rbx), %rax
	movq	_CHIP_RV670@GOTPCREL(%rip), %r15
	movq	_CHIP_RV635@GOTPCREL(%rip), %r13
	cmpq	(%r15), %rax
	je	LBB0_11
## %bb.9:
	movq	_CHIP_RV620@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_11
## %bb.10:
	cmpq	(%r13), %rax
	jne	LBB0_15
LBB0_11:
	movq	_PCIE_LC_LINK_WIDTH_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_UPCONFIGURE_DIS@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r14), %edi
	callq	_WREG32_PCIE_PORT
	movl	(%r14), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_RENEGOTIATION_SUPPORT@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_13
## %bb.12:
	movq	_LC_LINK_WIDTH_RD_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	andl	%eax, %esi
	movq	_LC_LINK_WIDTH_RD_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %esi
	movq	_LC_LINK_WIDTH_MASK@GOTPCREL(%rip), %rcx
	movq	_LC_RECONFIG_ARC_MISSING_ESCAPE@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	notl	%edx
	andl	%edx, %eax
	movq	_LC_RECONFIG_NOW@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_LC_RENEGOTIATE_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	jmp	LBB0_14
LBB0_13:
	movl	(%r15), %esi
LBB0_14:
	orl	%eax, %esi
	movl	(%r14), %edi
	callq	_WREG32_PCIE_PORT
	movq	_CHIP_RV670@GOTPCREL(%rip), %r15
LBB0_15:
	movl	(%r12), %edi
	callq	_RREG32_PCIE_PORT
	movl	%eax, %r14d
	movq	_LC_OTHER_SIDE_EVER_SENT_GEN2@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_22
## %bb.16:
	movq	_LC_OTHER_SIDE_SUPPORTS_GEN2@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_22
## %bb.17:
	movq	8(%rbx), %rax
	cmpq	(%r15), %rax
	je	LBB0_20
## %bb.18:
	movq	_CHIP_RV620@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_20
## %bb.19:
	cmpq	(%r13), %rax
	jne	LBB0_21
LBB0_20:
	movq	_MM_CFGREGS_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movl	$8, %esi
	callq	_WREG32
	movl	$16520, %edi                    ## imm = 0x4088
	callq	_RREG32
	movl	%eax, %r15d
	movl	(%r13), %edi
	movq	_CHIP_RV635@GOTPCREL(%rip), %r13
	xorl	%esi, %esi
	callq	_WREG32
	movq	_SELECTABLE_DEEMPHASIS@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	movq	_CHIP_RV670@GOTPCREL(%rip), %r15
	jne	LBB0_24
LBB0_21:
	movq	_LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r14d
	movq	_LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$3, %eax
	shll	%cl, %eax
	orl	%r14d, %eax
	movq	_LC_VOLTAGE_TIMER_SEL_MASK@GOTPCREL(%rip), %rcx
	movq	_LC_FORCE_DIS_HW_SPEED_CHANGE@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_LC_FORCE_EN_HW_SPEED_CHANGE@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	(%r12), %edi
	callq	_WREG32_PCIE_PORT
	movl	$21532, %edi                    ## imm = 0x541C
	callq	_RREG32
	orl	$8, %eax
	movl	$21532, %edi                    ## imm = 0x541C
	movl	%eax, %esi
	callq	_WREG32
	movq	_MM_CFGREGS_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movq	_MM_WR_TO_CFG_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_WREG32
	movl	$16520, %edi                    ## imm = 0x4088
	callq	_RREG16
	movq	_TARGET_LINK_SPEED_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	orl	$2, %esi
	movl	$16520, %edi                    ## imm = 0x4088
	callq	_WREG16
	movl	(%r14), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	8(%rbx), %rax
	cmpq	(%r15), %rax
	sete	%cl
	movq	_CHIP_RV620@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rax
	sete	%dl
	orb	%cl, %dl
	cmpq	(%r13), %rax
	sete	%al
	orb	%dl, %al
	movq	_PCIE_LC_TRAINING_CNTL@GOTPCREL(%rip), %r14
	cmoveq	%r12, %r14
	movl	(%r14), %edi
	movq	_LC_TARGET_LINK_SPEED_OVERRIDE_EN@GOTPCREL(%rip), %rbx
	cmovneq	_LC_POINT_7_PLUS_EN@GOTPCREL(%rip), %rbx
	callq	_RREG32_PCIE_PORT
	movl	(%rbx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r14), %edi
	callq	_WREG32_PCIE_PORT
	movl	(%r12), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_GEN2_EN_STRAP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r12), %edi
	jmp	LBB0_23
LBB0_22:
	movq	_PCIE_LC_LINK_WIDTH_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_UPCONFIGURE_DIS@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
LBB0_23:
	movl	%eax, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_PCIE_PORT               ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_radeon_pcie_gen2,8,3           ## @radeon_pcie_gen2
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
	.comm	_RADEON_IS_PCIE,4,2             ## @RADEON_IS_PCIE
	.comm	_CHIP_R600,8,3                  ## @CHIP_R600
	.comm	_PCIE_SPEED_5_0GT,8,3           ## @PCIE_SPEED_5_0GT
	.comm	_PCIE_SPEED_8_0GT,8,3           ## @PCIE_SPEED_8_0GT
	.comm	_PCIE_LC_SPEED_CNTL,4,2         ## @PCIE_LC_SPEED_CNTL
	.comm	_LC_CURRENT_DATA_RATE,4,2       ## @LC_CURRENT_DATA_RATE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"PCIE gen 2 link speeds already enabled\n"

L_.str.1:                               ## @.str.1
	.asciz	"enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"

	.comm	_CHIP_RV670,8,3                 ## @CHIP_RV670
	.comm	_CHIP_RV620,8,3                 ## @CHIP_RV620
	.comm	_CHIP_RV635,8,3                 ## @CHIP_RV635
	.comm	_PCIE_LC_LINK_WIDTH_CNTL,4,2    ## @PCIE_LC_LINK_WIDTH_CNTL
	.comm	_LC_UPCONFIGURE_DIS,4,2         ## @LC_UPCONFIGURE_DIS
	.comm	_LC_RENEGOTIATION_SUPPORT,4,2   ## @LC_RENEGOTIATION_SUPPORT
	.comm	_LC_LINK_WIDTH_RD_MASK,4,2      ## @LC_LINK_WIDTH_RD_MASK
	.comm	_LC_LINK_WIDTH_RD_SHIFT,4,2     ## @LC_LINK_WIDTH_RD_SHIFT
	.comm	_LC_LINK_WIDTH_MASK,4,2         ## @LC_LINK_WIDTH_MASK
	.comm	_LC_RECONFIG_ARC_MISSING_ESCAPE,4,2 ## @LC_RECONFIG_ARC_MISSING_ESCAPE
	.comm	_LC_RECONFIG_NOW,4,2            ## @LC_RECONFIG_NOW
	.comm	_LC_RENEGOTIATE_EN,4,2          ## @LC_RENEGOTIATE_EN
	.comm	_LC_OTHER_SIDE_EVER_SENT_GEN2,4,2 ## @LC_OTHER_SIDE_EVER_SENT_GEN2
	.comm	_LC_OTHER_SIDE_SUPPORTS_GEN2,4,2 ## @LC_OTHER_SIDE_SUPPORTS_GEN2
	.comm	_MM_CFGREGS_CNTL,4,2            ## @MM_CFGREGS_CNTL
	.comm	_SELECTABLE_DEEMPHASIS,4,2      ## @SELECTABLE_DEEMPHASIS
	.comm	_LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK,4,2 ## @LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
	.comm	_LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT,4,2 ## @LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT
	.comm	_LC_VOLTAGE_TIMER_SEL_MASK,4,2  ## @LC_VOLTAGE_TIMER_SEL_MASK
	.comm	_LC_FORCE_DIS_HW_SPEED_CHANGE,4,2 ## @LC_FORCE_DIS_HW_SPEED_CHANGE
	.comm	_LC_FORCE_EN_HW_SPEED_CHANGE,4,2 ## @LC_FORCE_EN_HW_SPEED_CHANGE
	.comm	_MM_WR_TO_CFG_EN,4,2            ## @MM_WR_TO_CFG_EN
	.comm	_TARGET_LINK_SPEED_MASK,4,2     ## @TARGET_LINK_SPEED_MASK
	.comm	_PCIE_LC_TRAINING_CNTL,4,2      ## @PCIE_LC_TRAINING_CNTL
	.comm	_LC_POINT_7_PLUS_EN,4,2         ## @LC_POINT_7_PLUS_EN
	.comm	_LC_TARGET_LINK_SPEED_OVERRIDE_EN,4,2 ## @LC_TARGET_LINK_SPEED_OVERRIDE_EN
	.comm	_LC_GEN2_EN_STRAP,4,2           ## @LC_GEN2_EN_STRAP
	.no_dead_strip	_r600_pcie_gen2_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function r600_pcie_gen2_enable
_r600_pcie_gen2_enable:                 ; @r600_pcie_gen2_enable
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
Lloh0:
	adrp	x8, _radeon_pcie_gen2@GOTPAGE
Lloh1:
	ldr	x8, [x8, _radeon_pcie_gen2@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	cbz	x8, LBB0_2
; %bb.1:
	mov	x19, x0
	ldr	w8, [x0]
Lloh3:
	adrp	x9, _RADEON_IS_IGP@GOTPAGE
Lloh4:
	ldr	x9, [x9, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_3
LBB0_2:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_3:
Lloh6:
	adrp	x9, _RADEON_IS_PCIE@GOTPAGE
Lloh7:
	ldr	x9, [x9, _RADEON_IS_PCIE@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.4:
	mov	x0, x19
	bl	_ASIC_IS_X2
	cbnz	x0, LBB0_2
; %bb.5:
	ldr	x8, [x19, #8]
Lloh9:
	adrp	x9, _CHIP_R600@GOTPAGE
Lloh10:
	ldr	x9, [x9, _CHIP_R600@GOTPAGEOFF]
Lloh11:
	ldr	x9, [x9]
	cmp	x8, x9
	b.le	LBB0_2
; %bb.6:
	ldr	x8, [x19, #16]
	ldr	x8, [x8]
	ldr	x8, [x8]
Lloh12:
	adrp	x9, _PCIE_SPEED_5_0GT@GOTPAGE
Lloh13:
	ldr	x9, [x9, _PCIE_SPEED_5_0GT@GOTPAGEOFF]
Lloh14:
	ldr	x9, [x9]
Lloh15:
	adrp	x10, _PCIE_SPEED_8_0GT@GOTPAGE
Lloh16:
	ldr	x10, [x10, _PCIE_SPEED_8_0GT@GOTPAGEOFF]
Lloh17:
	ldr	x10, [x10]
	cmp	x8, x9
	ccmp	x8, x10, #4, ne
	b.ne	LBB0_2
; %bb.7:
Lloh18:
	adrp	x22, _PCIE_LC_SPEED_CNTL@GOTPAGE
Lloh19:
	ldr	x22, [x22, _PCIE_LC_SPEED_CNTL@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_RREG32_PCIE_PORT
Lloh20:
	adrp	x8, _LC_CURRENT_DATA_RATE@GOTPAGE
Lloh21:
	ldr	x8, [x8, _LC_CURRENT_DATA_RATE@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_9
; %bb.8:
Lloh23:
	adrp	x0, l_.str@PAGE
Lloh24:
	add	x0, x0, l_.str@PAGEOFF
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_DRM_INFO
LBB0_9:
Lloh25:
	adrp	x0, l_.str.1@PAGE
Lloh26:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_INFO
	ldr	x8, [x19, #8]
Lloh27:
	adrp	x24, _CHIP_RV670@GOTPAGE
Lloh28:
	ldr	x24, [x24, _CHIP_RV670@GOTPAGEOFF]
Lloh29:
	adrp	x25, _CHIP_RV620@GOTPAGE
Lloh30:
	ldr	x25, [x25, _CHIP_RV620@GOTPAGEOFF]
Lloh31:
	adrp	x23, _CHIP_RV635@GOTPAGE
Lloh32:
	ldr	x23, [x23, _CHIP_RV635@GOTPAGEOFF]
	ldr	x9, [x24]
Lloh33:
	adrp	x21, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGE
Lloh34:
	ldr	x21, [x21, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGEOFF]
Lloh35:
	adrp	x26, _LC_UPCONFIGURE_DIS@GOTPAGE
Lloh36:
	ldr	x26, [x26, _LC_UPCONFIGURE_DIS@GOTPAGEOFF]
	cmp	x8, x9
	b.eq	LBB0_12
; %bb.10:
	ldr	x9, [x25]
	cmp	x8, x9
	b.eq	LBB0_12
; %bb.11:
	ldr	x9, [x23]
	cmp	x8, x9
	b.ne	LBB0_16
LBB0_12:
	ldr	w0, [x21]
	bl	_RREG32_PCIE_PORT
	ldr	w8, [x26]
	bic	w1, w0, w8
	ldr	w0, [x21]
	bl	_WREG32_PCIE_PORT
	ldr	w0, [x21]
	bl	_RREG32_PCIE_PORT
Lloh37:
	adrp	x8, _LC_RENEGOTIATION_SUPPORT@GOTPAGE
Lloh38:
	ldr	x8, [x8, _LC_RENEGOTIATION_SUPPORT@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_14
; %bb.13:
Lloh40:
	adrp	x8, _LC_LINK_WIDTH_RD_MASK@GOTPAGE
Lloh41:
	ldr	x8, [x8, _LC_LINK_WIDTH_RD_MASK@GOTPAGEOFF]
Lloh42:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh43:
	adrp	x9, _LC_LINK_WIDTH_RD_SHIFT@GOTPAGE
Lloh44:
	ldr	x9, [x9, _LC_LINK_WIDTH_RD_SHIFT@GOTPAGEOFF]
Lloh45:
	ldr	w9, [x9]
	asr	w8, w8, w9
Lloh46:
	adrp	x9, _LC_LINK_WIDTH_MASK@GOTPAGE
Lloh47:
	ldr	x9, [x9, _LC_LINK_WIDTH_MASK@GOTPAGEOFF]
Lloh48:
	ldr	w9, [x9]
Lloh49:
	adrp	x10, _LC_RECONFIG_ARC_MISSING_ESCAPE@GOTPAGE
Lloh50:
	ldr	x10, [x10, _LC_RECONFIG_ARC_MISSING_ESCAPE@GOTPAGEOFF]
Lloh51:
	ldr	w10, [x10]
	orr	w9, w10, w9
	bic	w9, w0, w9
Lloh52:
	adrp	x10, _LC_RECONFIG_NOW@GOTPAGE
Lloh53:
	ldr	x10, [x10, _LC_RECONFIG_NOW@GOTPAGEOFF]
Lloh54:
	ldr	w10, [x10]
	orr	w8, w10, w8
Lloh55:
	adrp	x10, _LC_RENEGOTIATE_EN@GOTPAGE
Lloh56:
	ldr	x10, [x10, _LC_RENEGOTIATE_EN@GOTPAGEOFF]
Lloh57:
	ldr	w10, [x10]
	orr	w8, w8, w10
	orr	w1, w8, w9
	b	LBB0_15
LBB0_14:
	ldr	w8, [x26]
	orr	w1, w8, w0
LBB0_15:
	ldr	w0, [x21]
	bl	_WREG32_PCIE_PORT
LBB0_16:
	ldr	w0, [x22]
	bl	_RREG32_PCIE_PORT
Lloh58:
	adrp	x8, _LC_OTHER_SIDE_EVER_SENT_GEN2@GOTPAGE
Lloh59:
	ldr	x8, [x8, _LC_OTHER_SIDE_EVER_SENT_GEN2@GOTPAGEOFF]
Lloh60:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_23
; %bb.17:
	mov	x20, x0
Lloh61:
	adrp	x8, _LC_OTHER_SIDE_SUPPORTS_GEN2@GOTPAGE
Lloh62:
	ldr	x8, [x8, _LC_OTHER_SIDE_SUPPORTS_GEN2@GOTPAGEOFF]
Lloh63:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_23
; %bb.18:
	ldr	x8, [x19, #8]
	ldr	x9, [x24]
Lloh64:
	adrp	x26, _MM_CFGREGS_CNTL@GOTPAGE
Lloh65:
	ldr	x26, [x26, _MM_CFGREGS_CNTL@GOTPAGEOFF]
	cmp	x8, x9
	b.eq	LBB0_21
; %bb.19:
	ldr	x9, [x25]
	cmp	x8, x9
	b.eq	LBB0_21
; %bb.20:
	ldr	x9, [x23]
	cmp	x8, x9
	b.ne	LBB0_22
LBB0_21:
	ldr	w0, [x26]
	mov	w1, #8
	bl	_WREG32
	mov	w0, #16520
	bl	_RREG32
	mov	x21, x0
	ldr	w0, [x26]
	mov	w1, #0
	bl	_WREG32
Lloh66:
	adrp	x8, _SELECTABLE_DEEMPHASIS@GOTPAGE
Lloh67:
	ldr	x8, [x8, _SELECTABLE_DEEMPHASIS@GOTPAGEOFF]
Lloh68:
	ldr	w8, [x8]
	tst	w8, w21
	b.ne	LBB0_2
LBB0_22:
Lloh69:
	adrp	x8, _LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK@GOTPAGE
Lloh70:
	ldr	x8, [x8, _LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK@GOTPAGEOFF]
Lloh71:
	ldr	w8, [x8]
Lloh72:
	adrp	x9, _LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT@GOTPAGE
Lloh73:
	ldr	x9, [x9, _LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT@GOTPAGEOFF]
	bic	w8, w20, w8
Lloh74:
	ldr	w9, [x9]
	mov	w10, #3
	lsl	w9, w10, w9
Lloh75:
	adrp	x10, _LC_VOLTAGE_TIMER_SEL_MASK@GOTPAGE
Lloh76:
	ldr	x10, [x10, _LC_VOLTAGE_TIMER_SEL_MASK@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh77:
	ldr	w9, [x10]
Lloh78:
	adrp	x10, _LC_FORCE_DIS_HW_SPEED_CHANGE@GOTPAGE
Lloh79:
	ldr	x10, [x10, _LC_FORCE_DIS_HW_SPEED_CHANGE@GOTPAGEOFF]
Lloh80:
	ldr	w10, [x10]
	orr	w9, w10, w9
	bic	w8, w8, w9
Lloh81:
	adrp	x9, _LC_FORCE_EN_HW_SPEED_CHANGE@GOTPAGE
Lloh82:
	ldr	x9, [x9, _LC_FORCE_EN_HW_SPEED_CHANGE@GOTPAGEOFF]
Lloh83:
	ldr	w9, [x9]
	orr	w1, w8, w9
	ldr	w0, [x22]
	bl	_WREG32_PCIE_PORT
	mov	w0, #21532
	bl	_RREG32
	orr	w1, w0, #0x8
	mov	w0, #21532
	bl	_WREG32
	ldr	w0, [x26]
Lloh84:
	adrp	x8, _MM_WR_TO_CFG_EN@GOTPAGE
Lloh85:
	ldr	x8, [x8, _MM_WR_TO_CFG_EN@GOTPAGEOFF]
Lloh86:
	ldr	w1, [x8]
	bl	_WREG32
	mov	w0, #16520
	bl	_RREG16
Lloh87:
	adrp	x8, _TARGET_LINK_SPEED_MASK@GOTPAGE
Lloh88:
	ldr	x8, [x8, _TARGET_LINK_SPEED_MASK@GOTPAGEOFF]
Lloh89:
	ldr	w8, [x8]
	bic	w8, w0, w8
	orr	w1, w8, #0x2
	mov	w0, #16520
	bl	_WREG16
	ldr	w0, [x26]
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x19, #8]
	ldr	x9, [x24]
	cmp	x8, x9
	ldr	x9, [x25]
	ccmp	x8, x9, #4, ne
	ldr	x9, [x23]
	ccmp	x8, x9, #4, ne
Lloh90:
	adrp	x8, _PCIE_LC_TRAINING_CNTL@GOTPAGE
Lloh91:
	ldr	x8, [x8, _PCIE_LC_TRAINING_CNTL@GOTPAGEOFF]
	csel	x19, x8, x22, eq
	ldr	w0, [x19]
Lloh92:
	adrp	x8, _LC_POINT_7_PLUS_EN@GOTPAGE
Lloh93:
	ldr	x8, [x8, _LC_POINT_7_PLUS_EN@GOTPAGEOFF]
Lloh94:
	adrp	x9, _LC_TARGET_LINK_SPEED_OVERRIDE_EN@GOTPAGE
Lloh95:
	ldr	x9, [x9, _LC_TARGET_LINK_SPEED_OVERRIDE_EN@GOTPAGEOFF]
	csel	x20, x8, x9, eq
	bl	_RREG32_PCIE_PORT
	ldr	w8, [x20]
	bic	w1, w0, w8
	ldr	w0, [x19]
	bl	_WREG32_PCIE_PORT
	ldr	w0, [x22]
	bl	_RREG32_PCIE_PORT
Lloh96:
	adrp	x8, _LC_GEN2_EN_STRAP@GOTPAGE
Lloh97:
	ldr	x8, [x8, _LC_GEN2_EN_STRAP@GOTPAGEOFF]
Lloh98:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x22]
	b	LBB0_24
LBB0_23:
	ldr	w0, [x21]
	bl	_RREG32_PCIE_PORT
	ldr	w8, [x26]
	orr	w1, w8, w0
	ldr	w0, [x21]
LBB0_24:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_WREG32_PCIE_PORT
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpAdd	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpAdd	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGot	Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGot	Lloh94, Lloh95
	.loh AdrpLdrGot	Lloh92, Lloh93
	.loh AdrpLdrGot	Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.cfi_endproc
                                        ; -- End function
	.comm	_radeon_pcie_gen2,8,3           ; @radeon_pcie_gen2
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
	.comm	_RADEON_IS_PCIE,4,2             ; @RADEON_IS_PCIE
	.comm	_CHIP_R600,8,3                  ; @CHIP_R600
	.comm	_PCIE_SPEED_5_0GT,8,3           ; @PCIE_SPEED_5_0GT
	.comm	_PCIE_SPEED_8_0GT,8,3           ; @PCIE_SPEED_8_0GT
	.comm	_PCIE_LC_SPEED_CNTL,4,2         ; @PCIE_LC_SPEED_CNTL
	.comm	_LC_CURRENT_DATA_RATE,4,2       ; @LC_CURRENT_DATA_RATE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"PCIE gen 2 link speeds already enabled\n"

l_.str.1:                               ; @.str.1
	.asciz	"enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"

	.comm	_CHIP_RV670,8,3                 ; @CHIP_RV670
	.comm	_CHIP_RV620,8,3                 ; @CHIP_RV620
	.comm	_CHIP_RV635,8,3                 ; @CHIP_RV635
	.comm	_PCIE_LC_LINK_WIDTH_CNTL,4,2    ; @PCIE_LC_LINK_WIDTH_CNTL
	.comm	_LC_UPCONFIGURE_DIS,4,2         ; @LC_UPCONFIGURE_DIS
	.comm	_LC_RENEGOTIATION_SUPPORT,4,2   ; @LC_RENEGOTIATION_SUPPORT
	.comm	_LC_LINK_WIDTH_RD_MASK,4,2      ; @LC_LINK_WIDTH_RD_MASK
	.comm	_LC_LINK_WIDTH_RD_SHIFT,4,2     ; @LC_LINK_WIDTH_RD_SHIFT
	.comm	_LC_LINK_WIDTH_MASK,4,2         ; @LC_LINK_WIDTH_MASK
	.comm	_LC_RECONFIG_ARC_MISSING_ESCAPE,4,2 ; @LC_RECONFIG_ARC_MISSING_ESCAPE
	.comm	_LC_RECONFIG_NOW,4,2            ; @LC_RECONFIG_NOW
	.comm	_LC_RENEGOTIATE_EN,4,2          ; @LC_RENEGOTIATE_EN
	.comm	_LC_OTHER_SIDE_EVER_SENT_GEN2,4,2 ; @LC_OTHER_SIDE_EVER_SENT_GEN2
	.comm	_LC_OTHER_SIDE_SUPPORTS_GEN2,4,2 ; @LC_OTHER_SIDE_SUPPORTS_GEN2
	.comm	_MM_CFGREGS_CNTL,4,2            ; @MM_CFGREGS_CNTL
	.comm	_SELECTABLE_DEEMPHASIS,4,2      ; @SELECTABLE_DEEMPHASIS
	.comm	_LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK,4,2 ; @LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
	.comm	_LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT,4,2 ; @LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT
	.comm	_LC_VOLTAGE_TIMER_SEL_MASK,4,2  ; @LC_VOLTAGE_TIMER_SEL_MASK
	.comm	_LC_FORCE_DIS_HW_SPEED_CHANGE,4,2 ; @LC_FORCE_DIS_HW_SPEED_CHANGE
	.comm	_LC_FORCE_EN_HW_SPEED_CHANGE,4,2 ; @LC_FORCE_EN_HW_SPEED_CHANGE
	.comm	_MM_WR_TO_CFG_EN,4,2            ; @MM_WR_TO_CFG_EN
	.comm	_TARGET_LINK_SPEED_MASK,4,2     ; @TARGET_LINK_SPEED_MASK
	.comm	_PCIE_LC_TRAINING_CNTL,4,2      ; @PCIE_LC_TRAINING_CNTL
	.comm	_LC_POINT_7_PLUS_EN,4,2         ; @LC_POINT_7_PLUS_EN
	.comm	_LC_TARGET_LINK_SPEED_OVERRIDE_EN,4,2 ; @LC_TARGET_LINK_SPEED_OVERRIDE_EN
	.comm	_LC_GEN2_EN_STRAP,4,2           ; @LC_GEN2_EN_STRAP
	.no_dead_strip	_r600_pcie_gen2_enable
.subsections_via_symbols
