	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function sun8i_hdmi_phy_config_h3
_sun8i_hdmi_phy_config_h3:              ## @sun8i_hdmi_phy_config_h3
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$104, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r12d
	movq	%rsi, %r14
	movq	_SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -132(%rbp)                ## 4-byte Spill
	movq	_SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	$7, %edi
	callq	_SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET
	movl	%eax, -128(%rbp)                ## 4-byte Spill
	movl	$1, %edi
	callq	_SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN
	movl	%eax, -116(%rbp)                ## 4-byte Spill
	movq	_SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -124(%rbp)                ## 4-byte Spill
	movq	_SUN8I_HDMI_PHY_PLL_CFG1_CS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -120(%rbp)                ## 4-byte Spill
	movl	$2, %edi
	callq	_SUN8I_HDMI_PHY_PLL_CFG1_CP_S
	movl	%eax, -112(%rbp)                ## 4-byte Spill
	movl	$63, %edi
	callq	_SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT
	movl	%eax, -104(%rbp)                ## 4-byte Spill
	movq	_SUN8I_HDMI_PHY_PLL_CFG1_BWS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -108(%rbp)                ## 4-byte Spill
	movq	_SUN8I_HDMI_PHY_PLL_CFG2_SV_H@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -100(%rbp)                ## 4-byte Spill
	movq	_SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -136(%rbp)                ## 4-byte Spill
	movq	_SUN8I_HDMI_PHY_PLL_CFG2_SDIV2@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -96(%rbp)                 ## 4-byte Spill
	movl	$1, %edi
	callq	_SUN8I_HDMI_PHY_ANA_CFG1_REG_SVBH
	movl	%eax, %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_CKEN@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_LDOEN@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_ENVBS@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_ENBI@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SUN8I_HDMI_PHY_ANA_CFG2_M_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -92(%rbp)                 ## 4-byte Spill
	movq	_SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -140(%rbp)                ## 4-byte Spill
	movq	_SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -88(%rbp)                 ## 4-byte Spill
	movl	$1, %edi
	callq	_SUN8I_HDMI_PHY_ANA_CFG2_REG_CKSS
	movl	%eax, -84(%rbp)                 ## 4-byte Spill
	movl	$1, %edi
	callq	_SUN8I_HDMI_PHY_ANA_CFG2_REG_CSMPS
	movl	%eax, -80(%rbp)                 ## 4-byte Spill
	movl	$992, %edi                      ## imm = 0x3E0
	callq	_SUN8I_HDMI_PHY_ANA_CFG3_REG_WIRE
	movl	%eax, %r15d
	movq	_SUN8I_HDMI_PHY_ANA_CFG3_SDAEN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -60(%rbp)                 ## 4-byte Spill
	movq	_SUN8I_HDMI_PHY_ANA_CFG3_SCLEN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -76(%rbp)                 ## 4-byte Spill
	cmpl	$27000000, %r12d                ## imm = 0x19BFCC0
	ja	LBB0_3
## %bb.1:
	movq	_SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33@GOTPCREL(%rip), %rax
	movl	%r15d, -72(%rbp)                ## 4-byte Spill
	movl	(%rax), %r15d
	movl	$32, %edi
	callq	_SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT
	orl	%r15d, %eax
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movl	$4, %edi
	callq	_SUN8I_HDMI_PHY_PLL_CFG2_VCO_S
	movl	%eax, %r12d
	movl	$4, %edi
	callq	_SUN8I_HDMI_PHY_PLL_CFG2_S
	orl	%r12d, %eax
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	$4, %edi
	callq	_SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV
	movl	%eax, %r15d
	movl	4(%r14), %edi
	callq	_SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI
	movl	%eax, %r12d
	orl	%r15d, %r12d
	movl	$3, %edi
	callq	_SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK
	movl	%eax, %r15d
	movl	$5, %edi
	jmp	LBB0_2
LBB0_3:
	cmpl	$74250000, %r12d                ## imm = 0x46CF710
	ja	LBB0_5
## %bb.4:
	movq	_SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33@GOTPCREL(%rip), %rax
	movl	%r15d, -72(%rbp)                ## 4-byte Spill
	movl	(%rax), %r15d
	movl	$32, %edi
	callq	_SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT
	orl	%r15d, %eax
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movl	$4, %edi
	callq	_SUN8I_HDMI_PHY_PLL_CFG2_VCO_S
	movl	%eax, %r15d
	movl	$5, %edi
	callq	_SUN8I_HDMI_PHY_PLL_CFG2_S
	orl	%r15d, %eax
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	$4, %edi
	callq	_SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV
	movl	%eax, %r15d
	movl	4(%r14), %edi
	callq	_SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI
	movl	%eax, %r12d
	orl	%r15d, %r12d
	movl	$5, %edi
	callq	_SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK
	movl	%eax, %r15d
	movl	$7, %edi
LBB0_2:
	callq	_SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP
	orl	%r15d, %eax
	movl	-72(%rbp), %r15d                ## 4-byte Reload
	movl	$0, -44(%rbp)                   ## 4-byte Folded Spill
	jmp	LBB0_9
LBB0_5:
	movq	%r14, -72(%rbp)                 ## 8-byte Spill
	cmpl	$148500000, %r12d               ## imm = 0x8D9EE20
	ja	LBB0_7
## %bb.6:
	movq	_SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	$32, %edi
	callq	_SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT
	orl	%r14d, %eax
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movl	$4, %edi
	callq	_SUN8I_HDMI_PHY_PLL_CFG2_VCO_S
	movl	%eax, %r14d
	movl	$6, %edi
	callq	_SUN8I_HDMI_PHY_PLL_CFG2_S
	orl	%r14d, %eax
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK@GOTPCREL(%rip), %rax
	movq	_SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r14d
	orl	(%rax), %r14d
	movl	$2, %edi
	callq	_SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV
	movl	%eax, %r12d
	orl	%r14d, %r12d
	movl	$7, %edi
	callq	_SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK
	movl	%eax, %r14d
	movl	$9, %edi
	callq	_SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP
	orl	%r14d, %eax
	movl	$0, -44(%rbp)                   ## 4-byte Folded Spill
	jmp	LBB0_8
LBB0_7:
	movl	$63, %edi
	callq	_SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movl	$6, %edi
	callq	_SUN8I_HDMI_PHY_PLL_CFG2_VCO_S
	movl	%eax, %r14d
	movl	$7, %edi
	callq	_SUN8I_HDMI_PHY_PLL_CFG2_S
	orl	%r14d, %eax
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK@GOTPCREL(%rip), %rax
	movq	_SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r14d
	orl	(%rax), %r14d
	movl	$4, %edi
	callq	_SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV
	movl	%eax, %r12d
	orl	%r14d, %r12d
	movl	$9, %edi
	callq	_SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movl	$13, %edi
	callq	_SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP
	movl	%eax, %r14d
	orl	-44(%rbp), %r14d                ## 4-byte Folded Reload
	movl	$3, %edi
	callq	_SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP
	orl	%r14d, %eax
	movl	$2, -44(%rbp)                   ## 4-byte Folded Spill
LBB0_8:
	movq	-72(%rbp), %r14                 ## 8-byte Reload
LBB0_9:
	movl	-60(%rbp), %ecx                 ## 4-byte Reload
	orl	%r15d, %ecx
	orl	-76(%rbp), %ecx                 ## 4-byte Folded Reload
	orl	%eax, %ecx
	movl	%ecx, -60(%rbp)                 ## 4-byte Spill
	movl	-140(%rbp), %r15d               ## 4-byte Reload
	orl	-92(%rbp), %r15d                ## 4-byte Folded Reload
	orl	-88(%rbp), %r15d                ## 4-byte Folded Reload
	orl	-84(%rbp), %r15d                ## 4-byte Folded Reload
	orl	-80(%rbp), %r15d                ## 4-byte Folded Reload
	orl	%r12d, %r15d
	movl	-136(%rbp), %r12d               ## 4-byte Reload
	orl	-100(%rbp), %r12d               ## 4-byte Folded Reload
	orl	-96(%rbp), %r12d                ## 4-byte Folded Reload
	orl	-48(%rbp), %r12d                ## 4-byte Folded Reload
	orl	-132(%rbp), %r13d               ## 4-byte Folded Reload
	orl	-128(%rbp), %r13d               ## 4-byte Folded Reload
	orl	-116(%rbp), %r13d               ## 4-byte Folded Reload
	orl	-124(%rbp), %r13d               ## 4-byte Folded Reload
	orl	-120(%rbp), %r13d               ## 4-byte Folded Reload
	orl	-112(%rbp), %r13d               ## 4-byte Folded Reload
	orl	-104(%rbp), %r13d               ## 4-byte Folded Reload
	orl	-108(%rbp), %r13d               ## 4-byte Folded Reload
	orl	-52(%rbp), %r13d                ## 4-byte Folded Reload
	movl	(%r14), %edi
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	(%r14), %edi
	movq	_SUN8I_HDMI_PHY_PLL_CFG1_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	movl	%r13d, %ecx
	callq	_regmap_update_bits
	movl	(%r14), %edi
	movq	_SUN8I_HDMI_PHY_PLL_CFG2_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	movl	%r12d, %ecx
	callq	_regmap_update_bits
	movl	$10000, %edi                    ## imm = 0x2710
	movl	$15000, %esi                    ## imm = 0x3A98
	callq	_usleep_range
	movl	(%r14), %edi
	movq	_SUN8I_HDMI_PHY_PLL_CFG3_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_SUN8I_HDMI_PHY_PLL_CFG1_REG@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	_SUN8I_HDMI_PHY_PLL_CFG1_PLLEN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	$100, %edi
	callq	_msleep
	movl	(%r14), %edi
	movq	_SUN8I_HDMI_PHY_ANA_STS_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-56(%rbp), %rdx
	callq	_regmap_read
	movq	_SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	andl	-56(%rbp), %edi
	movq	_SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarl	%cl, %edi
	movl	%edi, -56(%rbp)
	addl	-44(%rbp), %edi                 ## 4-byte Folded Reload
	movl	$63, %esi
	callq	_min
	movl	%eax, -56(%rbp)
	movl	(%r14), %edi
	movl	(%r12), %esi
	movq	_SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1@GOTPCREL(%rip), %rax
	movq	_SUN8I_HDMI_PHY_PLL_CFG1_REG_OD@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r14), %edi
	movl	(%r12), %esi
	movq	_SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	-56(%rbp), %eax
	movq	_SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	movl	%eax, %ecx
	callq	_regmap_update_bits
	movl	$100, %edi
	callq	_msleep
	movl	(%r14), %edi
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%ebx, %edx
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_SUN8I_HDMI_PHY_ANA_CFG2_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r15d, %edx
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_SUN8I_HDMI_PHY_ANA_CFG3_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-60(%rbp), %edx                 ## 4-byte Reload
	callq	_regmap_write
	xorl	%eax, %eax
	addq	$104, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN,4,2 ## @SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN,4,2 ## @SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN,4,2 ## @SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_CS,4,2 ## @SUN8I_HDMI_PHY_PLL_CFG1_CS
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_BWS,4,2 ## @SUN8I_HDMI_PHY_PLL_CFG1_BWS
	.comm	_SUN8I_HDMI_PHY_PLL_CFG2_SV_H,4,2 ## @SUN8I_HDMI_PHY_PLL_CFG2_SV_H
	.comm	_SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN,4,2 ## @SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN
	.comm	_SUN8I_HDMI_PHY_PLL_CFG2_SDIV2,4,2 ## @SUN8I_HDMI_PHY_PLL_CFG2_SDIV2
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_CKEN,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_CKEN
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_LDOEN,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_LDOEN
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENVBS,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_ENVBS
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENBI,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_ENBI
	.comm	_SUN8I_HDMI_PHY_ANA_CFG2_M_EN,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG2_M_EN
	.comm	_SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK
	.comm	_SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN
	.comm	_SUN8I_HDMI_PHY_ANA_CFG3_SDAEN,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG3_SDAEN
	.comm	_SUN8I_HDMI_PHY_ANA_CFG3_SCLEN,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG3_SCLEN
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33,4,2 ## @SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW
	.comm	_SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK
	.comm	_SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_REG,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_REG
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_REG,4,2 ## @SUN8I_HDMI_PHY_PLL_CFG1_REG
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,8,3 ## @SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK
	.comm	_SUN8I_HDMI_PHY_PLL_CFG2_REG,4,2 ## @SUN8I_HDMI_PHY_PLL_CFG2_REG
	.comm	_SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK,8,3 ## @SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK
	.comm	_SUN8I_HDMI_PHY_PLL_CFG3_REG,4,2 ## @SUN8I_HDMI_PHY_PLL_CFG3_REG
	.comm	_SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2,4,2 ## @SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_PLLEN,4,2 ## @SUN8I_HDMI_PHY_PLL_CFG1_PLLEN
	.comm	_SUN8I_HDMI_PHY_ANA_STS_REG,4,2 ## @SUN8I_HDMI_PHY_ANA_STS_REG
	.comm	_SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK,4,2 ## @SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK
	.comm	_SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT,4,2 ## @SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1,4,2 ## @SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_REG_OD,4,2 ## @SUN8I_HDMI_PHY_PLL_CFG1_REG_OD
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK,4,2 ## @SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT,4,2 ## @SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT
	.comm	_SUN8I_HDMI_PHY_ANA_CFG2_REG,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG2_REG
	.comm	_SUN8I_HDMI_PHY_ANA_CFG3_REG,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG3_REG
	.no_dead_strip	_sun8i_hdmi_phy_config_h3
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function sun8i_hdmi_phy_config_h3
_sun8i_hdmi_phy_config_h3:              ; @sun8i_hdmi_phy_config_h3
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #176
	.cfi_def_cfa_offset 176
	stp	x28, x27, [sp, #80]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #96]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #112]            ; 16-byte Folded Spill
	stp	x22, x21, [sp, #128]            ; 16-byte Folded Spill
	stp	x20, x19, [sp, #144]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #160]            ; 16-byte Folded Spill
	add	x29, sp, #160
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x28, x2
	mov	x19, x1
Lloh0:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN@GOTPAGE
Lloh1:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	str	w8, [sp, #72]                   ; 4-byte Folded Spill
Lloh3:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN@GOTPAGE
Lloh4:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	str	w8, [sp, #68]                   ; 4-byte Folded Spill
	mov	w0, #7
	bl	_SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET
	str	w0, [sp, #64]                   ; 4-byte Folded Spill
	mov	w0, #1
	bl	_SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN
	str	w0, [sp, #60]                   ; 4-byte Folded Spill
Lloh6:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN@GOTPAGE
Lloh7:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	str	w8, [sp, #56]                   ; 4-byte Folded Spill
Lloh9:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG1_CS@GOTPAGE
Lloh10:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG1_CS@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	str	w8, [sp, #52]                   ; 4-byte Folded Spill
	mov	w0, #2
	bl	_SUN8I_HDMI_PHY_PLL_CFG1_CP_S
	str	w0, [sp, #48]                   ; 4-byte Folded Spill
	mov	w0, #63
	bl	_SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT
	str	w0, [sp, #44]                   ; 4-byte Folded Spill
Lloh12:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG1_BWS@GOTPAGE
Lloh13:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG1_BWS@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	str	w8, [sp, #40]                   ; 4-byte Folded Spill
Lloh15:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG2_SV_H@GOTPAGE
Lloh16:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG2_SV_H@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	str	w8, [sp, #36]                   ; 4-byte Folded Spill
Lloh18:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN@GOTPAGE
Lloh19:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	str	w8, [sp, #32]                   ; 4-byte Folded Spill
Lloh21:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG2_SDIV2@GOTPAGE
Lloh22:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG2_SDIV2@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	str	w8, [sp, #28]                   ; 4-byte Folded Spill
	mov	w0, #1
	bl	_SUN8I_HDMI_PHY_ANA_CFG1_REG_SVBH
Lloh24:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT@GOTPAGE
Lloh25:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh27:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT@GOTPAGE
Lloh28:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
Lloh30:
	adrp	x10, _SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT@GOTPAGE
Lloh31:
	ldr	x10, [x10, _SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh32:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh33:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT@GOTPAGE
Lloh34:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT@GOTPAGEOFF]
Lloh35:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh36:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL@GOTPAGE
Lloh37:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL@GOTPAGEOFF]
Lloh38:
	ldr	w9, [x9]
Lloh39:
	adrp	x10, _SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG@GOTPAGE
Lloh40:
	ldr	x10, [x10, _SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh41:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh42:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS@GOTPAGE
Lloh43:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS@GOTPAGEOFF]
Lloh44:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh45:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN@GOTPAGE
Lloh46:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN@GOTPAGEOFF]
Lloh47:
	ldr	w9, [x9]
Lloh48:
	adrp	x10, _SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK@GOTPAGE
Lloh49:
	ldr	x10, [x10, _SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh50:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh51:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL@GOTPAGE
Lloh52:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL@GOTPAGEOFF]
Lloh53:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh54:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK@GOTPAGE
Lloh55:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK@GOTPAGEOFF]
Lloh56:
	ldr	w9, [x9]
Lloh57:
	adrp	x10, _SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2@GOTPAGE
Lloh58:
	ldr	x10, [x10, _SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh59:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh60:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1@GOTPAGE
Lloh61:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1@GOTPAGEOFF]
Lloh62:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh63:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0@GOTPAGE
Lloh64:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0@GOTPAGEOFF]
Lloh65:
	ldr	w9, [x9]
Lloh66:
	adrp	x10, _SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2@GOTPAGE
Lloh67:
	ldr	x10, [x10, _SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh68:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh69:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1@GOTPAGE
Lloh70:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1@GOTPAGEOFF]
Lloh71:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh72:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0@GOTPAGE
Lloh73:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0@GOTPAGEOFF]
Lloh74:
	ldr	w9, [x9]
Lloh75:
	adrp	x10, _SUN8I_HDMI_PHY_ANA_CFG1_CKEN@GOTPAGE
Lloh76:
	ldr	x10, [x10, _SUN8I_HDMI_PHY_ANA_CFG1_CKEN@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh77:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh78:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG1_LDOEN@GOTPAGE
Lloh79:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG1_LDOEN@GOTPAGEOFF]
Lloh80:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh81:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG1_ENVBS@GOTPAGE
Lloh82:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG1_ENVBS@GOTPAGEOFF]
Lloh83:
	ldr	w9, [x9]
Lloh84:
	adrp	x10, _SUN8I_HDMI_PHY_ANA_CFG1_ENBI@GOTPAGE
Lloh85:
	ldr	x10, [x10, _SUN8I_HDMI_PHY_ANA_CFG1_ENBI@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh86:
	ldr	w9, [x10]
	orr	w20, w8, w9
Lloh87:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG2_M_EN@GOTPAGE
Lloh88:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG2_M_EN@GOTPAGEOFF]
Lloh89:
	ldr	w8, [x8]
	str	w8, [sp, #24]                   ; 4-byte Folded Spill
Lloh90:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK@GOTPAGE
Lloh91:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK@GOTPAGEOFF]
Lloh92:
	ldr	w8, [x8]
	str	w8, [sp, #20]                   ; 4-byte Folded Spill
Lloh93:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN@GOTPAGE
Lloh94:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN@GOTPAGEOFF]
Lloh95:
	ldr	w8, [x8]
	str	w8, [sp, #16]                   ; 4-byte Folded Spill
	mov	w0, #1
	bl	_SUN8I_HDMI_PHY_ANA_CFG2_REG_CKSS
	str	w0, [sp, #12]                   ; 4-byte Folded Spill
	mov	w0, #1
	bl	_SUN8I_HDMI_PHY_ANA_CFG2_REG_CSMPS
	str	w0, [sp, #8]                    ; 4-byte Folded Spill
	mov	w0, #992
	bl	_SUN8I_HDMI_PHY_ANA_CFG3_REG_WIRE
	mov	x27, x0
Lloh96:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG3_SDAEN@GOTPAGE
Lloh97:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG3_SDAEN@GOTPAGEOFF]
Lloh98:
	ldr	w23, [x8]
Lloh99:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG3_SCLEN@GOTPAGE
Lloh100:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG3_SCLEN@GOTPAGEOFF]
Lloh101:
	ldr	w22, [x8]
	mov	w8, #64704
	movk	w8, #411, lsl #16
	cmp	w28, w8
	b.hi	LBB0_2
; %bb.1:
Lloh102:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33@GOTPAGE
Lloh103:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33@GOTPAGEOFF]
Lloh104:
	ldr	w21, [x8]
	mov	w0, #32
	bl	_SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT
	orr	w28, w0, w21
	mov	w0, #4
	bl	_SUN8I_HDMI_PHY_PLL_CFG2_VCO_S
	mov	x21, x0
	mov	w0, #4
	bl	_SUN8I_HDMI_PHY_PLL_CFG2_S
	orr	w24, w0, w21
Lloh105:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW@GOTPAGE
Lloh106:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW@GOTPAGEOFF]
Lloh107:
	ldr	w8, [x8]
	orr	w20, w8, w20
	mov	w0, #4
	bl	_SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV
	mov	x21, x0
	ldr	w0, [x19, #4]
	bl	_SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI
	orr	w25, w0, w21
	mov	w0, #3
	bl	_SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK
	mov	x21, x0
	mov	w0, #5
	b	LBB0_6
LBB0_2:
	mov	w8, #63248
	movk	w8, #1132, lsl #16
	cmp	w28, w8
	b.hi	LBB0_4
; %bb.3:
Lloh108:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33@GOTPAGE
Lloh109:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33@GOTPAGEOFF]
Lloh110:
	ldr	w21, [x8]
	mov	w0, #32
	bl	_SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT
	orr	w28, w0, w21
	mov	w0, #4
	bl	_SUN8I_HDMI_PHY_PLL_CFG2_VCO_S
	mov	x21, x0
	mov	w0, #5
	bl	_SUN8I_HDMI_PHY_PLL_CFG2_S
	orr	w24, w0, w21
Lloh111:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW@GOTPAGE
Lloh112:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW@GOTPAGEOFF]
Lloh113:
	ldr	w8, [x8]
	orr	w20, w8, w20
	mov	w0, #4
	bl	_SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV
	mov	x21, x0
	ldr	w0, [x19, #4]
	bl	_SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI
	orr	w25, w0, w21
	mov	w0, #5
	bl	_SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK
	mov	x21, x0
	mov	w0, #7
	b	LBB0_6
LBB0_4:
	mov	w8, #60960
	movk	w8, #2265, lsl #16
	cmp	w28, w8
	b.hi	LBB0_8
; %bb.5:
Lloh114:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33@GOTPAGE
Lloh115:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33@GOTPAGEOFF]
Lloh116:
	ldr	w21, [x8]
	mov	w0, #32
	bl	_SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT
	orr	w28, w0, w21
	mov	w0, #4
	bl	_SUN8I_HDMI_PHY_PLL_CFG2_VCO_S
	mov	x21, x0
	mov	w0, #6
	bl	_SUN8I_HDMI_PHY_PLL_CFG2_S
Lloh117:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK@GOTPAGE
Lloh118:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK@GOTPAGEOFF]
	orr	w24, w0, w21
Lloh119:
	ldr	w8, [x8]
Lloh120:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW@GOTPAGE
Lloh121:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW@GOTPAGEOFF]
Lloh122:
	ldr	w9, [x9]
	orr	w21, w9, w8
	mov	w0, #2
	bl	_SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV
	orr	w25, w21, w0
	mov	w0, #7
	bl	_SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK
	mov	x21, x0
	mov	w0, #9
LBB0_6:
	bl	_SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP
	mov	w26, #0
	orr	w8, w0, w21
LBB0_7:
	orr	w9, w23, w27
	orr	w9, w9, w22
	orr	w27, w9, w8
	ldp	w9, w8, [sp, #20]               ; 8-byte Folded Reload
	orr	w8, w9, w8
	ldr	w9, [sp, #16]                   ; 4-byte Folded Reload
	orr	w8, w8, w9
	ldr	w9, [sp, #12]                   ; 4-byte Folded Reload
	orr	w8, w8, w9
	ldr	w9, [sp, #8]                    ; 4-byte Folded Reload
	orr	w8, w8, w9
	orr	w25, w8, w25
	ldp	w9, w8, [sp, #32]               ; 8-byte Folded Reload
	orr	w8, w9, w8
	ldr	w9, [sp, #28]                   ; 4-byte Folded Reload
	orr	w8, w8, w9
	orr	w21, w8, w24
	ldp	w9, w8, [sp, #68]               ; 8-byte Folded Reload
	orr	w8, w9, w8
	ldr	w9, [sp, #64]                   ; 4-byte Folded Reload
	orr	w8, w8, w9
	ldr	w9, [sp, #60]                   ; 4-byte Folded Reload
	orr	w8, w8, w9
	ldr	w9, [sp, #56]                   ; 4-byte Folded Reload
	orr	w8, w8, w9
	ldr	w9, [sp, #52]                   ; 4-byte Folded Reload
	orr	w8, w8, w9
	ldr	w9, [sp, #48]                   ; 4-byte Folded Reload
	orr	w8, w8, w9
	ldr	w9, [sp, #44]                   ; 4-byte Folded Reload
	orr	w8, w8, w9
	ldr	w9, [sp, #40]                   ; 4-byte Folded Reload
	orr	w8, w8, w9
	orr	w22, w8, w28
	ldr	w0, [x19]
Lloh123:
	adrp	x23, _SUN8I_HDMI_PHY_ANA_CFG1_REG@GOTPAGE
Lloh124:
	ldr	x23, [x23, _SUN8I_HDMI_PHY_ANA_CFG1_REG@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh125:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK@GOTPAGE
Lloh126:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK@GOTPAGEOFF]
Lloh127:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_regmap_update_bits
Lloh128:
	adrp	x24, _SUN8I_HDMI_PHY_PLL_CFG1_REG@GOTPAGE
Lloh129:
	ldr	x24, [x24, _SUN8I_HDMI_PHY_PLL_CFG1_REG@GOTPAGEOFF]
	ldr	w0, [x19]
	ldr	w1, [x24]
Lloh130:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK@GOTPAGE
Lloh131:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK@GOTPAGEOFF]
Lloh132:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	x3, x22
	bl	_regmap_update_bits
Lloh133:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG2_REG@GOTPAGE
Lloh134:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG2_REG@GOTPAGEOFF]
	ldr	w0, [x19]
Lloh135:
	ldr	w1, [x8]
Lloh136:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK@GOTPAGE
Lloh137:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK@GOTPAGEOFF]
Lloh138:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	x3, x21
	bl	_regmap_update_bits
	mov	w0, #10000
	mov	w1, #15000
	bl	_usleep_range
	ldr	w0, [x19]
Lloh139:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG3_REG@GOTPAGE
Lloh140:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG3_REG@GOTPAGEOFF]
Lloh141:
	ldr	w1, [x8]
Lloh142:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2@GOTPAGE
Lloh143:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2@GOTPAGEOFF]
Lloh144:
	ldr	w2, [x8]
	bl	_regmap_write
	ldr	w0, [x19]
	ldr	w1, [x24]
Lloh145:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG1_PLLEN@GOTPAGE
Lloh146:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG1_PLLEN@GOTPAGEOFF]
Lloh147:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	mov	w0, #100
	bl	_msleep
	ldr	w0, [x19]
Lloh148:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_STS_REG@GOTPAGE
Lloh149:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_STS_REG@GOTPAGEOFF]
Lloh150:
	ldr	w1, [x8]
	add	x2, sp, #76
	bl	_regmap_read
	ldr	w8, [sp, #76]
Lloh151:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK@GOTPAGE
Lloh152:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK@GOTPAGEOFF]
Lloh153:
	ldr	w9, [x9]
	and	w8, w9, w8
Lloh154:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT@GOTPAGE
Lloh155:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT@GOTPAGEOFF]
Lloh156:
	ldr	w9, [x9]
	asr	w8, w8, w9
	str	w8, [sp, #76]
	add	w0, w8, w26
	mov	w1, #63
	bl	_min
	str	w0, [sp, #76]
	ldr	w0, [x19]
Lloh157:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1@GOTPAGE
Lloh158:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1@GOTPAGEOFF]
	ldr	w1, [x24]
Lloh159:
	ldr	w8, [x8]
Lloh160:
	adrp	x9, _SUN8I_HDMI_PHY_PLL_CFG1_REG_OD@GOTPAGE
Lloh161:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_PLL_CFG1_REG_OD@GOTPAGEOFF]
Lloh162:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x24]
Lloh163:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK@GOTPAGE
Lloh164:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK@GOTPAGEOFF]
Lloh165:
	ldr	w2, [x8]
	ldr	w8, [sp, #76]
Lloh166:
	adrp	x9, _SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT@GOTPAGE
Lloh167:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT@GOTPAGEOFF]
Lloh168:
	ldr	w9, [x9]
	lsl	w3, w8, w9
	bl	_regmap_update_bits
	mov	w0, #100
	bl	_msleep
	ldr	w0, [x19]
	ldr	w1, [x23]
	mov	x2, x20
	bl	_regmap_write
	ldr	w0, [x19]
Lloh169:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG2_REG@GOTPAGE
Lloh170:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG2_REG@GOTPAGEOFF]
Lloh171:
	ldr	w1, [x8]
	mov	x2, x25
	bl	_regmap_write
	ldr	w0, [x19]
Lloh172:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG3_REG@GOTPAGE
Lloh173:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG3_REG@GOTPAGEOFF]
Lloh174:
	ldr	w1, [x8]
	mov	x2, x27
	bl	_regmap_write
	mov	w0, #0
	ldp	x29, x30, [sp, #160]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #144]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #128]            ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #112]            ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #96]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #80]             ; 16-byte Folded Reload
	add	sp, sp, #176
	ret
LBB0_8:
	mov	w0, #63
	bl	_SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT
	mov	x28, x0
	mov	w0, #6
	bl	_SUN8I_HDMI_PHY_PLL_CFG2_VCO_S
	mov	x21, x0
	mov	w0, #7
	bl	_SUN8I_HDMI_PHY_PLL_CFG2_S
Lloh175:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK@GOTPAGE
Lloh176:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK@GOTPAGEOFF]
	orr	w24, w0, w21
Lloh177:
	ldr	w8, [x8]
Lloh178:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW@GOTPAGE
Lloh179:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW@GOTPAGEOFF]
Lloh180:
	ldr	w9, [x9]
	orr	w21, w9, w8
	mov	w0, #4
	bl	_SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV
	orr	w25, w21, w0
	mov	w0, #9
	bl	_SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK
	mov	x21, x0
	mov	w0, #13
	bl	_SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP
	orr	w21, w0, w21
	mov	w0, #3
	bl	_SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP
	orr	w8, w21, w0
	mov	w26, #2
	b	LBB0_7
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh120, Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh172, Lloh173, Lloh174
	.loh AdrpLdrGotLdr	Lloh169, Lloh170, Lloh171
	.loh AdrpLdrGotLdr	Lloh166, Lloh167, Lloh168
	.loh AdrpLdrGotLdr	Lloh163, Lloh164, Lloh165
	.loh AdrpLdrGotLdr	Lloh160, Lloh161, Lloh162
	.loh AdrpLdrGotLdr	Lloh157, Lloh158, Lloh159
	.loh AdrpLdrGotLdr	Lloh154, Lloh155, Lloh156
	.loh AdrpLdrGotLdr	Lloh151, Lloh152, Lloh153
	.loh AdrpLdrGotLdr	Lloh148, Lloh149, Lloh150
	.loh AdrpLdrGotLdr	Lloh145, Lloh146, Lloh147
	.loh AdrpLdrGotLdr	Lloh142, Lloh143, Lloh144
	.loh AdrpLdrGotLdr	Lloh139, Lloh140, Lloh141
	.loh AdrpLdrGotLdr	Lloh136, Lloh137, Lloh138
	.loh AdrpLdrGotLdr	Lloh133, Lloh134, Lloh135
	.loh AdrpLdrGotLdr	Lloh130, Lloh131, Lloh132
	.loh AdrpLdrGot	Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGot	Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh178, Lloh179, Lloh180
	.loh AdrpLdrGotLdr	Lloh175, Lloh176, Lloh177
	.cfi_endproc
                                        ; -- End function
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN,4,2 ; @SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN,4,2 ; @SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN,4,2 ; @SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_CS,4,2 ; @SUN8I_HDMI_PHY_PLL_CFG1_CS
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_BWS,4,2 ; @SUN8I_HDMI_PHY_PLL_CFG1_BWS
	.comm	_SUN8I_HDMI_PHY_PLL_CFG2_SV_H,4,2 ; @SUN8I_HDMI_PHY_PLL_CFG2_SV_H
	.comm	_SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN,4,2 ; @SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN
	.comm	_SUN8I_HDMI_PHY_PLL_CFG2_SDIV2,4,2 ; @SUN8I_HDMI_PHY_PLL_CFG2_SDIV2
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_CKEN,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_CKEN
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_LDOEN,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_LDOEN
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENVBS,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_ENVBS
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENBI,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_ENBI
	.comm	_SUN8I_HDMI_PHY_ANA_CFG2_M_EN,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG2_M_EN
	.comm	_SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK
	.comm	_SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN
	.comm	_SUN8I_HDMI_PHY_ANA_CFG3_SDAEN,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG3_SDAEN
	.comm	_SUN8I_HDMI_PHY_ANA_CFG3_SCLEN,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG3_SCLEN
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33,4,2 ; @SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW
	.comm	_SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK
	.comm	_SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_REG,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_REG
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_REG,4,2 ; @SUN8I_HDMI_PHY_PLL_CFG1_REG
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,8,3 ; @SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK
	.comm	_SUN8I_HDMI_PHY_PLL_CFG2_REG,4,2 ; @SUN8I_HDMI_PHY_PLL_CFG2_REG
	.comm	_SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK,8,3 ; @SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK
	.comm	_SUN8I_HDMI_PHY_PLL_CFG3_REG,4,2 ; @SUN8I_HDMI_PHY_PLL_CFG3_REG
	.comm	_SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2,4,2 ; @SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_PLLEN,4,2 ; @SUN8I_HDMI_PHY_PLL_CFG1_PLLEN
	.comm	_SUN8I_HDMI_PHY_ANA_STS_REG,4,2 ; @SUN8I_HDMI_PHY_ANA_STS_REG
	.comm	_SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK,4,2 ; @SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK
	.comm	_SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT,4,2 ; @SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1,4,2 ; @SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_REG_OD,4,2 ; @SUN8I_HDMI_PHY_PLL_CFG1_REG_OD
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK,4,2 ; @SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT,4,2 ; @SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT
	.comm	_SUN8I_HDMI_PHY_ANA_CFG2_REG,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG2_REG
	.comm	_SUN8I_HDMI_PHY_ANA_CFG3_REG,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG3_REG
	.no_dead_strip	_sun8i_hdmi_phy_config_h3
.subsections_via_symbols
