	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_gen11_gt_irq_postinstall       ## -- Begin function gen11_gt_irq_postinstall
	.p2align	4, 0x90
_gen11_gt_irq_postinstall:              ## @gen11_gt_irq_postinstall
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_GT_RENDER_USER_INTERRUPT@GOTPCREL(%rip), %rax
	movq	_GT_CONTEXT_SWITCH_INTERRUPT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	orl	(%rax), %edi
	movq	8(%r14), %r15
	movl	%edi, %ebx
	shll	$16, %ebx
	movl	%ebx, %r12d
	orl	%edi, %r12d
	andl	$-65536, %edi                   ## imm = 0xFFFF0000
	callq	_BUILD_BUG_ON
	movq	_GEN11_RENDER_COPY_INTR_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%r12d, %edx
	callq	_intel_uncore_write
	movq	_GEN11_VCS_VECS_INTR_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%r12d, %edx
	callq	_intel_uncore_write
	movq	_GEN11_RCS0_RSVD_INTR_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%ebx
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_intel_uncore_write
	movq	_GEN11_BCS_RSVD_INTR_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_intel_uncore_write
	movq	_GEN11_VCS0_VCS1_INTR_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%r12d
	movq	%r15, %rdi
	movl	%r12d, %edx
	callq	_intel_uncore_write
	movq	_GEN11_VCS2_VCS3_INTR_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%r12d, %edx
	callq	_intel_uncore_write
	movq	_GEN11_VECS0_VECS1_INTR_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%r12d, %edx
	callq	_intel_uncore_write
	movabsq	$-4294967296, %rax              ## imm = 0xFFFFFFFF00000000
	movq	%rax, (%r14)
	movq	_GEN11_GPM_WGBOXPERF_INTR_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_intel_uncore_write
	movq	_GEN11_GPM_WGBOXPERF_INTR_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$-1, %edx
	callq	_intel_uncore_write
	movq	_GEN11_GUC_SG_INTR_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_intel_uncore_write
	movq	_GEN11_GUC_SG_INTR_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$-1, %edx
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_intel_uncore_write             ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_GT_RENDER_USER_INTERRUPT,4,2   ## @GT_RENDER_USER_INTERRUPT
	.comm	_GT_CONTEXT_SWITCH_INTERRUPT,4,2 ## @GT_CONTEXT_SWITCH_INTERRUPT
	.comm	_GEN11_RENDER_COPY_INTR_ENABLE,4,2 ## @GEN11_RENDER_COPY_INTR_ENABLE
	.comm	_GEN11_VCS_VECS_INTR_ENABLE,4,2 ## @GEN11_VCS_VECS_INTR_ENABLE
	.comm	_GEN11_RCS0_RSVD_INTR_MASK,4,2  ## @GEN11_RCS0_RSVD_INTR_MASK
	.comm	_GEN11_BCS_RSVD_INTR_MASK,4,2   ## @GEN11_BCS_RSVD_INTR_MASK
	.comm	_GEN11_VCS0_VCS1_INTR_MASK,4,2  ## @GEN11_VCS0_VCS1_INTR_MASK
	.comm	_GEN11_VCS2_VCS3_INTR_MASK,4,2  ## @GEN11_VCS2_VCS3_INTR_MASK
	.comm	_GEN11_VECS0_VECS1_INTR_MASK,4,2 ## @GEN11_VECS0_VECS1_INTR_MASK
	.comm	_GEN11_GPM_WGBOXPERF_INTR_ENABLE,4,2 ## @GEN11_GPM_WGBOXPERF_INTR_ENABLE
	.comm	_GEN11_GPM_WGBOXPERF_INTR_MASK,4,2 ## @GEN11_GPM_WGBOXPERF_INTR_MASK
	.comm	_GEN11_GUC_SG_INTR_ENABLE,4,2   ## @GEN11_GUC_SG_INTR_ENABLE
	.comm	_GEN11_GUC_SG_INTR_MASK,4,2     ## @GEN11_GUC_SG_INTR_MASK
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_gen11_gt_irq_postinstall       ; -- Begin function gen11_gt_irq_postinstall
	.p2align	2
_gen11_gt_irq_postinstall:              ; @gen11_gt_irq_postinstall
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x0
Lloh0:
	adrp	x8, _GT_RENDER_USER_INTERRUPT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _GT_RENDER_USER_INTERRUPT@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _GT_CONTEXT_SWITCH_INTERRUPT@GOTPAGE
Lloh4:
	ldr	x9, [x9, _GT_CONTEXT_SWITCH_INTERRUPT@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	orr	w8, w9, w8
	ldr	x19, [x0, #8]
	lsl	w22, w8, #16
	orr	w21, w22, w8
	and	w0, w8, #0xffff0000
	bl	_BUILD_BUG_ON
Lloh6:
	adrp	x8, _GEN11_RENDER_COPY_INTR_ENABLE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _GEN11_RENDER_COPY_INTR_ENABLE@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_intel_uncore_write
Lloh9:
	adrp	x8, _GEN11_VCS_VECS_INTR_ENABLE@GOTPAGE
Lloh10:
	ldr	x8, [x8, _GEN11_VCS_VECS_INTR_ENABLE@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_intel_uncore_write
Lloh12:
	adrp	x8, _GEN11_RCS0_RSVD_INTR_MASK@GOTPAGE
Lloh13:
	ldr	x8, [x8, _GEN11_RCS0_RSVD_INTR_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mvn	w22, w22
	mov	x0, x19
	mov	x2, x22
	bl	_intel_uncore_write
Lloh15:
	adrp	x8, _GEN11_BCS_RSVD_INTR_MASK@GOTPAGE
Lloh16:
	ldr	x8, [x8, _GEN11_BCS_RSVD_INTR_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x22
	bl	_intel_uncore_write
Lloh18:
	adrp	x8, _GEN11_VCS0_VCS1_INTR_MASK@GOTPAGE
Lloh19:
	ldr	x8, [x8, _GEN11_VCS0_VCS1_INTR_MASK@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	mvn	w21, w21
	mov	x0, x19
	mov	x2, x21
	bl	_intel_uncore_write
Lloh21:
	adrp	x8, _GEN11_VCS2_VCS3_INTR_MASK@GOTPAGE
Lloh22:
	ldr	x8, [x8, _GEN11_VCS2_VCS3_INTR_MASK@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_intel_uncore_write
Lloh24:
	adrp	x8, _GEN11_VECS0_VECS1_INTR_MASK@GOTPAGE
Lloh25:
	ldr	x8, [x8, _GEN11_VECS0_VECS1_INTR_MASK@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_intel_uncore_write
	movi	d0, #0xffffffff00000000
	str	d0, [x20]
Lloh27:
	adrp	x8, _GEN11_GPM_WGBOXPERF_INTR_ENABLE@GOTPAGE
Lloh28:
	ldr	x8, [x8, _GEN11_GPM_WGBOXPERF_INTR_ENABLE@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_intel_uncore_write
Lloh30:
	adrp	x8, _GEN11_GPM_WGBOXPERF_INTR_MASK@GOTPAGE
Lloh31:
	ldr	x8, [x8, _GEN11_GPM_WGBOXPERF_INTR_MASK@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1
	bl	_intel_uncore_write
Lloh33:
	adrp	x8, _GEN11_GUC_SG_INTR_ENABLE@GOTPAGE
Lloh34:
	ldr	x8, [x8, _GEN11_GUC_SG_INTR_ENABLE@GOTPAGEOFF]
Lloh35:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_intel_uncore_write
Lloh36:
	adrp	x8, _GEN11_GUC_SG_INTR_MASK@GOTPAGE
Lloh37:
	ldr	x8, [x8, _GEN11_GUC_SG_INTR_MASK@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_intel_uncore_write
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_GT_RENDER_USER_INTERRUPT,4,2   ; @GT_RENDER_USER_INTERRUPT
	.comm	_GT_CONTEXT_SWITCH_INTERRUPT,4,2 ; @GT_CONTEXT_SWITCH_INTERRUPT
	.comm	_GEN11_RENDER_COPY_INTR_ENABLE,4,2 ; @GEN11_RENDER_COPY_INTR_ENABLE
	.comm	_GEN11_VCS_VECS_INTR_ENABLE,4,2 ; @GEN11_VCS_VECS_INTR_ENABLE
	.comm	_GEN11_RCS0_RSVD_INTR_MASK,4,2  ; @GEN11_RCS0_RSVD_INTR_MASK
	.comm	_GEN11_BCS_RSVD_INTR_MASK,4,2   ; @GEN11_BCS_RSVD_INTR_MASK
	.comm	_GEN11_VCS0_VCS1_INTR_MASK,4,2  ; @GEN11_VCS0_VCS1_INTR_MASK
	.comm	_GEN11_VCS2_VCS3_INTR_MASK,4,2  ; @GEN11_VCS2_VCS3_INTR_MASK
	.comm	_GEN11_VECS0_VECS1_INTR_MASK,4,2 ; @GEN11_VECS0_VECS1_INTR_MASK
	.comm	_GEN11_GPM_WGBOXPERF_INTR_ENABLE,4,2 ; @GEN11_GPM_WGBOXPERF_INTR_ENABLE
	.comm	_GEN11_GPM_WGBOXPERF_INTR_MASK,4,2 ; @GEN11_GPM_WGBOXPERF_INTR_MASK
	.comm	_GEN11_GUC_SG_INTR_ENABLE,4,2   ; @GEN11_GUC_SG_INTR_ENABLE
	.comm	_GEN11_GUC_SG_INTR_MASK,4,2     ; @GEN11_GUC_SG_INTR_MASK
.subsections_via_symbols
