	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ironlake_pch_enable
_ironlake_pch_enable:                   ## @ironlake_pch_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %rbx
	movq	%rdi, -72(%rbp)                 ## 8-byte Spill
	movl	12(%rsi), %edi
	callq	_to_intel_crtc
	movq	%rax, %r12
	movq	8(%rax), %rdi
	callq	_to_i915
	movq	%rax, %r15
	movl	(%r12), %r13d
	movq	%rax, %rdi
	movl	%r13d, %esi
	callq	_assert_pch_transcoder_disabled
	movq	%r15, %rdi
	callq	_IS_IVYBRIDGE
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	%rbx, %rdi
	callq	_ivybridge_update_fdi_bc_bifurcation
LBB0_2:
	movl	%r13d, %edi
	callq	_FDI_RX_TUSIZE1
	movl	%eax, %r14d
	movl	%r13d, %edi
	callq	_PIPE_DATA_M1
	movl	%eax, %edi
	callq	_I915_READ
	movq	_TU_SIZE_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movl	%r14d, %edi
	movl	%eax, %esi
	callq	_I915_WRITE
	movq	%r12, %rdi
	movq	%rbx, %rsi
	callq	*(%r15)
	movq	%r15, %rdi
	callq	_HAS_PCH_CPT
	testq	%rax, %rax
	je	LBB0_4
## %bb.3:
	movq	_PCH_DPLL_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movl	%eax, %r14d
	movl	%r13d, %edi
	callq	_TRANS_DPLL_ENABLE
	orl	%eax, %r14d
	movl	%r13d, %edi
	callq	_TRANS_DPLLB_SEL
	movq	%r12, -48(%rbp)                 ## 8-byte Spill
	movq	%rbx, %r12
	movl	%eax, %ebx
	movq	(%r12), %rax
	movq	%rax, -64(%rbp)                 ## 8-byte Spill
	movq	_DPLL_ID_PCH_PLL_B@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_intel_get_shared_dpll_by_id
	movl	%r14d, %ecx
	orl	%ebx, %ecx
	notl	%ebx
	andl	%r14d, %ebx
	cmpq	%rax, -64(%rbp)                 ## 8-byte Folded Reload
	cmovel	%ecx, %ebx
	movq	_PCH_DPLL_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	movq	%r12, %rbx
	movq	-48(%rbp), %r12                 ## 8-byte Reload
	callq	_I915_WRITE
LBB0_4:
	movq	%rbx, %rdi
	callq	_intel_enable_shared_dpll
	movq	%r15, %rdi
	movl	%r13d, %esi
	callq	_assert_panel_unlocked
	movq	%rbx, %rdi
	movl	%r13d, %esi
	callq	_ironlake_pch_transcoder_set_timings
	movq	%r12, %rdi
	callq	_intel_fdi_normal_train
	movq	%r15, %rdi
	callq	_HAS_PCH_CPT
	testq	%rax, %rax
	je	LBB0_11
## %bb.5:
	movq	%rbx, %rdi
	callq	_intel_crtc_has_dp_encoder
	testq	%rax, %rax
	je	LBB0_11
## %bb.6:
	movl	%r13d, %edi
	callq	_PIPECONF
	movl	%eax, %edi
	callq	_I915_READ
	movl	%eax, %r14d
	movq	_PIPECONF_BPC_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %r14d
	movl	%r13d, %edi
	callq	_TRANS_DP_CTL
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movl	%eax, %edi
	callq	_I915_READ
	movq	%rbx, %rsi
	movl	%eax, %ebx
	movq	_TRANS_DP_PORT_SEL_MASK@GOTPCREL(%rip), %rcx
	movq	_TRANS_DP_SYNC_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	(%rcx), %eax
	movq	_TRANS_DP_BPC_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	notl	%eax
	andl	$-32, %r14d
	movq	%rsi, %rdx
	movl	8(%rsi), %r13d
	movq	_DRM_MODE_FLAG_PHSYNC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r12d
	andl	%r13d, %r12d
	je	LBB0_8
## %bb.7:
	movq	_TRANS_DP_HSYNC_ACTIVE_HIGH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r12d
LBB0_8:
	andl	%eax, %ebx
	movq	_TRANS_DP_OUTPUT_ENABLE@GOTPCREL(%rip), %rax
	shll	$4, %r14d
	movq	_DRM_MODE_FLAG_PVSYNC@GOTPCREL(%rip), %rcx
	andl	(%rcx), %r13d
	je	LBB0_10
## %bb.9:
	movq	_TRANS_DP_VSYNC_ACTIVE_HIGH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r13d
LBB0_10:
	orl	(%rax), %r14d
	movq	-72(%rbp), %rdi                 ## 8-byte Reload
	movq	%rdx, %rsi
	movq	%rdx, -56(%rbp)                 ## 8-byte Spill
	callq	_intel_get_crtc_new_encoder
	movl	(%rax), %r15d
	movq	_PORT_B@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r15d
	setb	%al
	movq	_PORT_D@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %r15d
	seta	%cl
	orb	%al, %cl
	movzbl	%cl, %edi
	callq	_WARN_ON
	movl	%r15d, %edi
	callq	_TRANS_DP_PORT_SEL
	orl	%r12d, %ebx
	orl	%r13d, %ebx
	orl	%eax, %ebx
	orl	%r14d, %ebx
	movl	-48(%rbp), %edi                 ## 4-byte Reload
	movl	%ebx, %esi
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	callq	_I915_WRITE
LBB0_11:
	movq	%rbx, %rdi
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_ironlake_enable_pch_transcoder ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_TU_SIZE_MASK,4,2               ## @TU_SIZE_MASK
	.comm	_PCH_DPLL_SEL,4,2               ## @PCH_DPLL_SEL
	.comm	_DPLL_ID_PCH_PLL_B,4,2          ## @DPLL_ID_PCH_PLL_B
	.comm	_PIPECONF_BPC_MASK,4,2          ## @PIPECONF_BPC_MASK
	.comm	_TRANS_DP_PORT_SEL_MASK,4,2     ## @TRANS_DP_PORT_SEL_MASK
	.comm	_TRANS_DP_SYNC_MASK,4,2         ## @TRANS_DP_SYNC_MASK
	.comm	_TRANS_DP_BPC_MASK,4,2          ## @TRANS_DP_BPC_MASK
	.comm	_TRANS_DP_OUTPUT_ENABLE,4,2     ## @TRANS_DP_OUTPUT_ENABLE
	.comm	_DRM_MODE_FLAG_PHSYNC,4,2       ## @DRM_MODE_FLAG_PHSYNC
	.comm	_TRANS_DP_HSYNC_ACTIVE_HIGH,4,2 ## @TRANS_DP_HSYNC_ACTIVE_HIGH
	.comm	_DRM_MODE_FLAG_PVSYNC,4,2       ## @DRM_MODE_FLAG_PVSYNC
	.comm	_TRANS_DP_VSYNC_ACTIVE_HIGH,4,2 ## @TRANS_DP_VSYNC_ACTIVE_HIGH
	.comm	_PORT_B,4,2                     ## @PORT_B
	.comm	_PORT_D,4,2                     ## @PORT_D
	.no_dead_strip	_ironlake_pch_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ironlake_pch_enable
_ironlake_pch_enable:                   ; @ironlake_pch_enable
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x1
	mov	x20, x0
	ldr	w0, [x1, #12]
	bl	_to_intel_crtc
	mov	x22, x0
	ldr	x0, [x0, #8]
	bl	_to_i915
	mov	x23, x0
	ldr	w21, [x22]
	mov	x1, x21
	bl	_assert_pch_transcoder_disabled
	mov	x0, x23
	bl	_IS_IVYBRIDGE
	cbz	x0, LBB0_2
; %bb.1:
	mov	x0, x19
	bl	_ivybridge_update_fdi_bc_bifurcation
LBB0_2:
	mov	x0, x21
	bl	_FDI_RX_TUSIZE1
	mov	x24, x0
	mov	x0, x21
	bl	_PIPE_DATA_M1
	bl	_I915_READ
Lloh0:
	adrp	x8, _TU_SIZE_MASK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _TU_SIZE_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	and	w1, w8, w0
	mov	x0, x24
	bl	_I915_WRITE
	ldr	x8, [x23]
	mov	x0, x22
	mov	x1, x19
	blr	x8
	mov	x0, x23
	bl	_HAS_PCH_CPT
	cbz	x0, LBB0_4
; %bb.3:
Lloh3:
	adrp	x25, _PCH_DPLL_SEL@GOTPAGE
Lloh4:
	ldr	x25, [x25, _PCH_DPLL_SEL@GOTPAGEOFF]
	ldr	w0, [x25]
	bl	_I915_READ
	mov	x24, x0
	mov	x0, x21
	bl	_TRANS_DPLL_ENABLE
	orr	w26, w0, w24
	mov	x0, x21
	bl	_TRANS_DPLLB_SEL
	mov	x24, x0
	ldr	x27, [x19]
Lloh5:
	adrp	x8, _DPLL_ID_PCH_PLL_B@GOTPAGE
Lloh6:
	ldr	x8, [x8, _DPLL_ID_PCH_PLL_B@GOTPAGEOFF]
Lloh7:
	ldr	w1, [x8]
	mov	x0, x23
	bl	_intel_get_shared_dpll_by_id
	orr	w8, w26, w24
	bic	w9, w26, w24
	cmp	x27, x0
	csel	w1, w8, w9, eq
	ldr	w0, [x25]
	bl	_I915_WRITE
LBB0_4:
	mov	x0, x19
	bl	_intel_enable_shared_dpll
	mov	x0, x23
	mov	x1, x21
	bl	_assert_panel_unlocked
	mov	x0, x19
	mov	x1, x21
	bl	_ironlake_pch_transcoder_set_timings
	mov	x0, x22
	bl	_intel_fdi_normal_train
	mov	x0, x23
	bl	_HAS_PCH_CPT
	cbz	x0, LBB0_7
; %bb.5:
	mov	x0, x19
	bl	_intel_crtc_has_dp_encoder
	cbz	x0, LBB0_7
; %bb.6:
	mov	x0, x21
	bl	_PIPECONF
	bl	_I915_READ
Lloh8:
	adrp	x8, _PIPECONF_BPC_MASK@GOTPAGE
Lloh9:
	ldr	x8, [x8, _PIPECONF_BPC_MASK@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	and	w22, w8, w0
	mov	x0, x21
	bl	_TRANS_DP_CTL
	mov	x21, x0
	bl	_I915_READ
Lloh11:
	adrp	x8, _TRANS_DP_PORT_SEL_MASK@GOTPAGE
Lloh12:
	ldr	x8, [x8, _TRANS_DP_PORT_SEL_MASK@GOTPAGEOFF]
Lloh13:
	adrp	x9, _TRANS_DP_SYNC_MASK@GOTPAGE
Lloh14:
	ldr	x9, [x9, _TRANS_DP_SYNC_MASK@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
Lloh16:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh17:
	adrp	x9, _TRANS_DP_BPC_MASK@GOTPAGE
Lloh18:
	ldr	x9, [x9, _TRANS_DP_BPC_MASK@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w23, w0, w8
Lloh20:
	adrp	x8, _TRANS_DP_OUTPUT_ENABLE@GOTPAGE
Lloh21:
	ldr	x8, [x8, _TRANS_DP_OUTPUT_ENABLE@GOTPAGEOFF]
Lloh22:
	ldr	w24, [x8]
	lsl	w8, w22, #4
	and	w22, w8, #0xfffffe00
	ldr	w8, [x19, #8]
Lloh23:
	adrp	x9, _DRM_MODE_FLAG_PHSYNC@GOTPAGE
Lloh24:
	ldr	x9, [x9, _DRM_MODE_FLAG_PHSYNC@GOTPAGEOFF]
Lloh25:
	adrp	x10, _TRANS_DP_HSYNC_ACTIVE_HIGH@GOTPAGE
Lloh26:
	ldr	x10, [x10, _TRANS_DP_HSYNC_ACTIVE_HIGH@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
Lloh28:
	ldr	w10, [x10]
	tst	w9, w8
	csel	w25, wzr, w10, eq
Lloh29:
	adrp	x9, _DRM_MODE_FLAG_PVSYNC@GOTPAGE
Lloh30:
	ldr	x9, [x9, _DRM_MODE_FLAG_PVSYNC@GOTPAGEOFF]
Lloh31:
	ldr	w9, [x9]
Lloh32:
	adrp	x10, _TRANS_DP_VSYNC_ACTIVE_HIGH@GOTPAGE
Lloh33:
	ldr	x10, [x10, _TRANS_DP_VSYNC_ACTIVE_HIGH@GOTPAGEOFF]
Lloh34:
	ldr	w10, [x10]
	tst	w9, w8
	csel	w26, wzr, w10, eq
	mov	x0, x20
	mov	x1, x19
	bl	_intel_get_crtc_new_encoder
	ldr	w20, [x0]
Lloh35:
	adrp	x8, _PORT_B@GOTPAGE
Lloh36:
	ldr	x8, [x8, _PORT_B@GOTPAGEOFF]
Lloh37:
	ldr	w8, [x8]
	cmp	w20, w8
Lloh38:
	adrp	x8, _PORT_D@GOTPAGE
Lloh39:
	ldr	x8, [x8, _PORT_D@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
	ccmp	w20, w8, #2, hs
	cset	w0, hi
	bl	_WARN_ON
	mov	x0, x20
	bl	_TRANS_DP_PORT_SEL
	orr	w8, w24, w22
	orr	w8, w8, w23
	orr	w8, w8, w25
	orr	w8, w8, w26
	orr	w1, w8, w0
	mov	x0, x21
	bl	_I915_WRITE
LBB0_7:
	mov	x0, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_ironlake_enable_pch_transcoder
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh27
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh15
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.cfi_endproc
                                        ; -- End function
	.comm	_TU_SIZE_MASK,4,2               ; @TU_SIZE_MASK
	.comm	_PCH_DPLL_SEL,4,2               ; @PCH_DPLL_SEL
	.comm	_DPLL_ID_PCH_PLL_B,4,2          ; @DPLL_ID_PCH_PLL_B
	.comm	_PIPECONF_BPC_MASK,4,2          ; @PIPECONF_BPC_MASK
	.comm	_TRANS_DP_PORT_SEL_MASK,4,2     ; @TRANS_DP_PORT_SEL_MASK
	.comm	_TRANS_DP_SYNC_MASK,4,2         ; @TRANS_DP_SYNC_MASK
	.comm	_TRANS_DP_BPC_MASK,4,2          ; @TRANS_DP_BPC_MASK
	.comm	_TRANS_DP_OUTPUT_ENABLE,4,2     ; @TRANS_DP_OUTPUT_ENABLE
	.comm	_DRM_MODE_FLAG_PHSYNC,4,2       ; @DRM_MODE_FLAG_PHSYNC
	.comm	_TRANS_DP_HSYNC_ACTIVE_HIGH,4,2 ; @TRANS_DP_HSYNC_ACTIVE_HIGH
	.comm	_DRM_MODE_FLAG_PVSYNC,4,2       ; @DRM_MODE_FLAG_PVSYNC
	.comm	_TRANS_DP_VSYNC_ACTIVE_HIGH,4,2 ; @TRANS_DP_VSYNC_ACTIVE_HIGH
	.comm	_PORT_B,4,2                     ; @PORT_B
	.comm	_PORT_D,4,2                     ; @PORT_D
	.no_dead_strip	_ironlake_pch_enable
.subsections_via_symbols
