	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_vcn_v2_0_jpeg_ring_emit_fence  ## -- Begin function vcn_v2_0_jpeg_ring_emit_fence
	.p2align	4, 0x90
_vcn_v2_0_jpeg_ring_emit_fence:         ## @vcn_v2_0_jpeg_ring_emit_fence
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r15d
	movl	%esi, %r14d
	movq	%rdi, %rbx
	movq	_AMDGPU_FENCE_FLAG_64BIT@GOTPCREL(%rip), %rax
	andl	(%rax), %ecx
	movl	%ecx, %edi
	callq	_WARN_ON
	movq	_mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_PACKETJ_TYPE0@GOTPCREL(%rip), %r12
	movl	(%r12), %ecx
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	%r15d, %esi
	callq	_amdgpu_ring_write
	movq	_mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r12), %ecx
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	%r15d, %esi
	callq	_amdgpu_ring_write
	movq	_mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r12), %ecx
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	%r14d, %edi
	callq	_lower_32_bits
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r12), %ecx
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	%r14d, %edi
	callq	_upper_32_bits
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movl	(%r12), %ecx
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$8, %esi
	callq	_amdgpu_ring_write
	movl	(%r14), %edi
	movq	_PACKETJ_CONDITION_CHECK0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_PACKETJ_TYPE4@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%esi, %esi
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
	movq	_mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r12), %ecx
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$16316, %esi                    ## imm = 0x3FBC
	callq	_amdgpu_ring_write
	movq	_JRBC_DEC_EXTERNAL_REG_WRITE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r12), %ecx
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$1, %esi
	callq	_amdgpu_ring_write
	movq	_PACKETJ_TYPE7@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%edi, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	xorl	%esi, %esi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_write              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_FENCE_FLAG_64BIT,4,2    ## @AMDGPU_FENCE_FLAG_64BIT
	.comm	_mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,4,2 ## @mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET
	.comm	_PACKETJ_TYPE0,4,2              ## @PACKETJ_TYPE0
	.comm	_mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,4,2 ## @mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET
	.comm	_mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,4,2 ## @mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET
	.comm	_mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,4,2 ## @mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET
	.comm	_mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,4,2 ## @mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET
	.comm	_PACKETJ_CONDITION_CHECK0,4,2   ## @PACKETJ_CONDITION_CHECK0
	.comm	_PACKETJ_TYPE4,4,2              ## @PACKETJ_TYPE4
	.comm	_mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,4,2 ## @mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET
	.comm	_JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,4,2 ## @JRBC_DEC_EXTERNAL_REG_WRITE_ADDR
	.comm	_PACKETJ_TYPE7,4,2              ## @PACKETJ_TYPE7
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_vcn_v2_0_jpeg_ring_emit_fence  ; -- Begin function vcn_v2_0_jpeg_ring_emit_fence
	.p2align	2
_vcn_v2_0_jpeg_ring_emit_fence:         ; @vcn_v2_0_jpeg_ring_emit_fence
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x21, x2
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x8, _AMDGPU_FENCE_FLAG_64BIT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPU_FENCE_FLAG_64BIT@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	and	w0, w8, w3
	bl	_WARN_ON
Lloh3:
	adrp	x8, _mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET@GOTPAGE
Lloh4:
	ldr	x8, [x8, _mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
Lloh6:
	adrp	x22, _PACKETJ_TYPE0@GOTPAGE
Lloh7:
	ldr	x22, [x22, _PACKETJ_TYPE0@GOTPAGEOFF]
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	x1, x21
	bl	_amdgpu_ring_write
Lloh8:
	adrp	x8, _mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET@GOTPAGE
Lloh9:
	ldr	x8, [x8, _mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh10:
	ldr	w0, [x8]
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	x1, x21
	bl	_amdgpu_ring_write
Lloh11:
	adrp	x8, _mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET@GOTPAGE
Lloh12:
	ldr	x8, [x8, _mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x20
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh14:
	adrp	x8, _mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET@GOTPAGE
Lloh15:
	ldr	x8, [x8, _mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x20
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh17:
	adrp	x20, _mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET@GOTPAGE
Lloh18:
	ldr	x20, [x20, _mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET@GOTPAGEOFF]
	ldr	w0, [x20]
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #8
	bl	_amdgpu_ring_write
	ldr	w0, [x20]
Lloh19:
	adrp	x8, _PACKETJ_CONDITION_CHECK0@GOTPAGE
Lloh20:
	ldr	x8, [x8, _PACKETJ_CONDITION_CHECK0@GOTPAGEOFF]
Lloh21:
	ldr	w2, [x8]
Lloh22:
	adrp	x8, _PACKETJ_TYPE4@GOTPAGE
Lloh23:
	ldr	x8, [x8, _PACKETJ_TYPE4@GOTPAGEOFF]
Lloh24:
	ldr	w3, [x8]
	mov	w1, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_ring_write
Lloh25:
	adrp	x8, _mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET@GOTPAGE
Lloh26:
	ldr	x8, [x8, _mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh27:
	ldr	w0, [x8]
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #16316
	bl	_amdgpu_ring_write
Lloh28:
	adrp	x8, _JRBC_DEC_EXTERNAL_REG_WRITE_ADDR@GOTPAGE
Lloh29:
	ldr	x8, [x8, _JRBC_DEC_EXTERNAL_REG_WRITE_ADDR@GOTPAGEOFF]
Lloh30:
	ldr	w0, [x8]
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #1
	bl	_amdgpu_ring_write
Lloh31:
	adrp	x8, _PACKETJ_TYPE7@GOTPAGE
Lloh32:
	ldr	x8, [x8, _PACKETJ_TYPE7@GOTPAGEOFF]
Lloh33:
	ldr	w3, [x8]
	mov	w0, #0
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_amdgpu_ring_write
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_FENCE_FLAG_64BIT,4,2    ; @AMDGPU_FENCE_FLAG_64BIT
	.comm	_mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,4,2 ; @mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET
	.comm	_PACKETJ_TYPE0,4,2              ; @PACKETJ_TYPE0
	.comm	_mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,4,2 ; @mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET
	.comm	_mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,4,2 ; @mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET
	.comm	_mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,4,2 ; @mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET
	.comm	_mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,4,2 ; @mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET
	.comm	_PACKETJ_CONDITION_CHECK0,4,2   ; @PACKETJ_CONDITION_CHECK0
	.comm	_PACKETJ_TYPE4,4,2              ; @PACKETJ_TYPE4
	.comm	_mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,4,2 ; @mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET
	.comm	_JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,4,2 ; @JRBC_DEC_EXTERNAL_REG_WRITE_ADDR
	.comm	_PACKETJ_TYPE7,4,2              ; @PACKETJ_TYPE7
.subsections_via_symbols
