	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function cdv_dpll_set_clock_cdv
_cdv_dpll_set_clock_cdv:                ## @cdv_dpll_set_clock_cdv
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%r8d, -64(%rbp)                 ## 4-byte Spill
	movl	%ecx, %r12d
	movq	%rdx, -72(%rbp)                 ## 8-byte Spill
	movq	%rdi, %r13
	movq	%rsi, %rdi
	callq	_to_gma_crtc
	movl	(%rax), %r14d
	testl	%r14d, %r14d
	movq	_DPLL_B@GOTPCREL(%rip), %rax
	cmoveq	_DPLL_A@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_SB_REF_DPLLB@GOTPCREL(%rip), %rax
	cmoveq	_SB_REF_DPLLA@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	%r13, %rdi
	callq	_cdv_sb_reset
	movq	_DPLL_SYNCLOCK_ENABLE@GOTPCREL(%rip), %rax
	movq	_DPLL_VGA_MODE_DIS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movl	%ebx, %edi
	callq	_REG_WRITE
	movl	$100, %edi
	callq	_udelay
	movl	$6858497, -56(%rbp)             ## imm = 0x68A701
	movl	%r14d, %edi
	callq	_SB_REF_SFR
	movq	%r13, %rdi
	movl	%eax, %esi
	movl	$6858497, %edx                  ## imm = 0x68A701
	callq	_cdv_sb_write
	leaq	-56(%rbp), %rdx
	movq	%r13, %rdi
	movl	%r15d, %esi
	callq	_cdv_sb_read
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_34
## %bb.1:
	movq	_REF_CLK_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, -56(%rbp)
	testl	%r12d, %r12d
	jne	LBB0_5
## %bb.2:
	cmpl	$1, %r14d
	jne	LBB0_5
## %bb.3:
	movq	_DP_MASK@GOTPCREL(%rip), %rax
	movl	-64(%rbp), %ecx                 ## 4-byte Reload
	testl	%ecx, (%rax)
	je	LBB0_4
LBB0_5:
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	movq	_REF_CLK_DPLL@GOTPCREL(%rip), %rax
LBB0_6:
	movl	-56(%rbp), %edx
	orl	(%rax), %edx
	movl	%edx, -56(%rbp)
	movq	%r13, %rdi
	movl	%r15d, %esi
	callq	_cdv_sb_write
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_34
## %bb.7:
	movl	%r14d, %edi
	callq	_SB_M
	leaq	-60(%rbp), %rdx
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_cdv_sb_read
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_34
## %bb.8:
	movq	_SB_M_DIVIDER_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	movq	-72(%rbp), %rcx                 ## 8-byte Reload
	movl	(%rcx), %edx
	movq	_SB_M_DIVIDER_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	andl	-60(%rbp), %eax
	orl	%eax, %edx
	movl	%edx, -60(%rbp)
	movl	%r14d, %edi
	callq	_SB_M
	movl	-60(%rbp), %edx
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_cdv_sb_write
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_34
## %bb.9:
	movl	%r14d, %edi
	callq	_SB_N_VCO
	leaq	-52(%rbp), %rdx
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_cdv_sb_read
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_34
## %bb.10:
	movq	_SB_N_VCO_SEL_MASK@GOTPCREL(%rip), %rax
	movq	_SB_N_DIVIDER_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movzwl	-52(%rbp), %edx
	movq	_SB_N_CB_TUNE_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	orl	$263, %edx                      ## imm = 0x107
	notl	%esi
	movq	_SB_N_DIVIDER_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movq	-72(%rbp), %rdi                 ## 8-byte Reload
	movl	4(%rdi), %eax
	shll	%cl, %eax
	andl	%edx, %esi
	movl	8(%rdi), %edx
	orl	%esi, %eax
	cmpl	$2249999, %edx                  ## imm = 0x22550F
	jg	LBB0_12
## %bb.11:
	movq	_SB_N_CB_TUNE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %edx
	jmp	LBB0_18
LBB0_4:
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	movq	_REF_CLK_DPLLA@GOTPCREL(%rip), %rax
	jmp	LBB0_6
LBB0_12:
	cmpl	$2749999, %edx                  ## imm = 0x29F62F
	ja	LBB0_14
## %bb.13:
	movq	_SB_N_CB_TUNE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	btsl	%ecx, %eax
	movq	_SB_N_VCO_SEL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	btsl	%ecx, %eax
	movl	%eax, -52(%rbp)
	jmp	LBB0_19
LBB0_14:
	movq	_SB_N_VCO_SEL_SHIFT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	cmpl	$3299999, %edx                  ## imm = 0x325A9F
	ja	LBB0_16
## %bb.15:
	movl	$2, %edx
	jmp	LBB0_17
LBB0_16:
	movl	$3, %edx
LBB0_17:
                                        ## kill: def $cl killed $cl killed $ecx
LBB0_18:
	shll	%cl, %edx
	orl	%eax, %edx
	movl	%edx, -52(%rbp)
LBB0_19:
	movl	%r14d, %edi
	callq	_SB_N_VCO
	movl	-52(%rbp), %edx
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_cdv_sb_write
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_34
## %bb.20:
	movl	%r14d, %edi
	callq	_SB_P
	leaq	-48(%rbp), %rdx
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_cdv_sb_read
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_34
## %bb.21:
	movq	_SB_P2_DIVIDER_MASK@GOTPCREL(%rip), %rax
	movq	_SB_P1_DIVIDER_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	notl	%ecx
	andl	%ecx, -48(%rbp)
	movq	-72(%rbp), %rbx                 ## 8-byte Reload
	movl	16(%rbx), %edi
	movq	_SB_P1_DIVIDER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_SET_FIELD
	orl	%eax, -48(%rbp)
	movl	12(%rbx), %esi
	leal	-5(%rsi), %eax
	cmpl	$9, %eax
	ja	LBB0_31
## %bb.22:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_23:
	movq	_SB_P2_5@GOTPCREL(%rip), %rax
	jmp	LBB0_24
LBB0_31:
	leaq	L_.str.2(%rip), %rdi
                                        ## kill: def $esi killed $esi killed $rsi
	callq	_DRM_ERROR
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
	jmp	LBB0_34
LBB0_30:
	movq	_SB_P2_7@GOTPCREL(%rip), %rax
	jmp	LBB0_24
LBB0_28:
	movq	_SB_P2_10@GOTPCREL(%rip), %rax
	jmp	LBB0_24
LBB0_29:
	movq	_SB_P2_14@GOTPCREL(%rip), %rax
LBB0_24:
	movl	(%rax), %edi
	movq	_SB_P2_DIVIDER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_SET_FIELD
	orl	%eax, -48(%rbp)
	movl	%r14d, %edi
	callq	_SB_P
	movl	-48(%rbp), %edx
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_cdv_sb_write
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_34
## %bb.25:
	xorl	%ebx, %ebx
	movl	-64(%rbp), %ecx                 ## 4-byte Reload
	testl	%ecx, %ecx
	je	LBB0_34
## %bb.26:
	movq	_DDI_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %ecx
	movq	_DDI0_SELECT@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ecx
	jne	LBB0_32
## %bb.27:
	movq	_PSB_LANE0@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	leaq	-44(%rbp), %rdx
	movq	%r13, %rdi
	movl	%r12d, %esi
	callq	_cdv_sb_read
	movq	_LANE_PLL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, -44(%rbp)
	movq	_LANE_PLL_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	%r14d, %edi
	callq	_LANE_PLL_PIPE
	orl	%eax, %r15d
	orl	-44(%rbp), %r15d
	movl	%r15d, -44(%rbp)
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%r15d, %edx
	callq	_cdv_sb_write
	movq	_PSB_LANE1@GOTPCREL(%rip), %rax
	jmp	LBB0_33
LBB0_32:
	movq	_PSB_LANE2@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	leaq	-44(%rbp), %rdx
	movq	%r13, %rdi
	movl	%r12d, %esi
	callq	_cdv_sb_read
	movq	_LANE_PLL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, -44(%rbp)
	movq	_LANE_PLL_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	%r14d, %edi
	callq	_LANE_PLL_PIPE
	orl	%eax, %r15d
	orl	-44(%rbp), %r15d
	movl	%r15d, -44(%rbp)
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%r15d, %edx
	callq	_cdv_sb_write
	movq	_PSB_LANE3@GOTPCREL(%rip), %rax
LBB0_33:
	movl	(%rax), %r15d
	movq	%r13, %rdi
	movl	%r15d, %esi
	leaq	-44(%rbp), %rdx
	callq	_cdv_sb_read
	movq	_LANE_PLL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, -44(%rbp)
	movq	_LANE_PLL_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	%r14d, %edi
	callq	_LANE_PLL_PIPE
	orl	%eax, %r12d
	orl	-44(%rbp), %r12d
	movl	%r12d, -44(%rbp)
	movq	%r13, %rdi
	movl	%r15d, %esi
	movl	%r12d, %edx
	callq	_cdv_sb_write
LBB0_34:
	movl	%ebx, %eax
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_23, LBB0_23-LJTI0_0
.set L0_0_set_31, LBB0_31-LJTI0_0
.set L0_0_set_30, LBB0_30-LJTI0_0
.set L0_0_set_28, LBB0_28-LJTI0_0
.set L0_0_set_29, LBB0_29-LJTI0_0
LJTI0_0:
	.long	L0_0_set_23
	.long	L0_0_set_31
	.long	L0_0_set_30
	.long	L0_0_set_31
	.long	L0_0_set_31
	.long	L0_0_set_28
	.long	L0_0_set_31
	.long	L0_0_set_31
	.long	L0_0_set_31
	.long	L0_0_set_29
	.end_data_region
                                        ## -- End function
	.comm	_DPLL_A,4,2                     ## @DPLL_A
	.comm	_DPLL_B,4,2                     ## @DPLL_B
	.comm	_SB_REF_DPLLA,4,2               ## @SB_REF_DPLLA
	.comm	_SB_REF_DPLLB,4,2               ## @SB_REF_DPLLB
	.comm	_DPLL_SYNCLOCK_ENABLE,4,2       ## @DPLL_SYNCLOCK_ENABLE
	.comm	_DPLL_VGA_MODE_DIS,4,2          ## @DPLL_VGA_MODE_DIS
	.comm	_REF_CLK_MASK,4,2               ## @REF_CLK_MASK
	.comm	_DP_MASK,4,2                    ## @DP_MASK
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"use DPLLA for pipe B\n"

	.comm	_REF_CLK_DPLLA,4,2              ## @REF_CLK_DPLLA
L_.str.1:                               ## @.str.1
	.asciz	"use their DPLL for pipe A/B\n"

	.comm	_REF_CLK_DPLL,4,2               ## @REF_CLK_DPLL
	.comm	_SB_M_DIVIDER_MASK,4,2          ## @SB_M_DIVIDER_MASK
	.comm	_SB_M_DIVIDER_SHIFT,4,2         ## @SB_M_DIVIDER_SHIFT
	.comm	_SB_N_VCO_SEL_MASK,4,2          ## @SB_N_VCO_SEL_MASK
	.comm	_SB_N_DIVIDER_MASK,4,2          ## @SB_N_DIVIDER_MASK
	.comm	_SB_N_CB_TUNE_MASK,4,2          ## @SB_N_CB_TUNE_MASK
	.comm	_SB_N_DIVIDER_SHIFT,4,2         ## @SB_N_DIVIDER_SHIFT
	.comm	_SB_N_CB_TUNE_SHIFT,4,2         ## @SB_N_CB_TUNE_SHIFT
	.comm	_SB_N_VCO_SEL_SHIFT,4,2         ## @SB_N_VCO_SEL_SHIFT
	.comm	_SB_P2_DIVIDER_MASK,4,2         ## @SB_P2_DIVIDER_MASK
	.comm	_SB_P1_DIVIDER_MASK,4,2         ## @SB_P1_DIVIDER_MASK
	.comm	_SB_P1_DIVIDER,4,2              ## @SB_P1_DIVIDER
	.comm	_SB_P2_5,4,2                    ## @SB_P2_5
	.comm	_SB_P2_DIVIDER,4,2              ## @SB_P2_DIVIDER
	.comm	_SB_P2_10,4,2                   ## @SB_P2_10
	.comm	_SB_P2_14,4,2                   ## @SB_P2_14
	.comm	_SB_P2_7,4,2                    ## @SB_P2_7
L_.str.2:                               ## @.str.2
	.asciz	"Bad P2 clock: %d\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_DDI_MASK,4,2                   ## @DDI_MASK
	.comm	_DDI0_SELECT,4,2                ## @DDI0_SELECT
	.comm	_PSB_LANE0,4,2                  ## @PSB_LANE0
	.comm	_LANE_PLL_MASK,4,2              ## @LANE_PLL_MASK
	.comm	_LANE_PLL_ENABLE,4,2            ## @LANE_PLL_ENABLE
	.comm	_PSB_LANE1,4,2                  ## @PSB_LANE1
	.comm	_PSB_LANE2,4,2                  ## @PSB_LANE2
	.comm	_PSB_LANE3,4,2                  ## @PSB_LANE3
	.no_dead_strip	_cdv_dpll_set_clock_cdv
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cdv_dpll_set_clock_cdv
_cdv_dpll_set_clock_cdv:                ; @cdv_dpll_set_clock_cdv
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x21, x4
	mov	x24, x3
	mov	x22, x2
	mov	x19, x0
	mov	x0, x1
	bl	_to_gma_crtc
Lloh0:
	adrp	x8, _DPLL_A@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DPLL_A@GOTPAGEOFF]
	ldr	w20, [x0]
Lloh2:
	adrp	x9, _DPLL_B@GOTPAGE
Lloh3:
	ldr	x9, [x9, _DPLL_B@GOTPAGEOFF]
	cmp	w20, #0
	csel	x8, x8, x9, eq
	ldr	w25, [x8]
Lloh4:
	adrp	x8, _SB_REF_DPLLA@GOTPAGE
Lloh5:
	ldr	x8, [x8, _SB_REF_DPLLA@GOTPAGEOFF]
Lloh6:
	adrp	x9, _SB_REF_DPLLB@GOTPAGE
Lloh7:
	ldr	x9, [x9, _SB_REF_DPLLB@GOTPAGEOFF]
	csel	x8, x8, x9, eq
	ldr	w23, [x8]
	mov	x0, x19
	bl	_cdv_sb_reset
Lloh8:
	adrp	x8, _DPLL_SYNCLOCK_ENABLE@GOTPAGE
Lloh9:
	ldr	x8, [x8, _DPLL_SYNCLOCK_ENABLE@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
Lloh11:
	adrp	x9, _DPLL_VGA_MODE_DIS@GOTPAGE
Lloh12:
	ldr	x9, [x9, _DPLL_VGA_MODE_DIS@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	orr	w1, w9, w8
	mov	x0, x25
	bl	_REG_WRITE
	mov	w0, #100
	bl	_udelay
	mov	w8, #42753
	movk	w8, #104, lsl #16
	str	w8, [sp, #16]
	mov	x0, x20
	bl	_SB_REF_SFR
	mov	x1, x0
	mov	x0, x19
	mov	w2, #42753
	movk	w2, #104, lsl #16
	bl	_cdv_sb_write
	add	x2, sp, #16
	mov	x0, x19
	mov	x1, x23
	bl	_cdv_sb_read
	cbnz	w0, LBB0_34
; %bb.1:
Lloh14:
	adrp	x8, _REF_CLK_MASK@GOTPAGE
Lloh15:
	ldr	x8, [x8, _REF_CLK_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
	ldr	w9, [sp, #16]
	bic	w8, w9, w8
	str	w8, [sp, #16]
	cbnz	w24, LBB0_4
; %bb.2:
	cmp	w20, #1
	b.ne	LBB0_4
; %bb.3:
Lloh17:
	adrp	x8, _DP_MASK@GOTPAGE
Lloh18:
	ldr	x8, [x8, _DP_MASK@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
	tst	w8, w21
	b.eq	LBB0_11
LBB0_4:
Lloh20:
	adrp	x0, l_.str.1@PAGE
Lloh21:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_DEBUG_KMS
Lloh22:
	adrp	x8, _REF_CLK_DPLL@GOTPAGE
Lloh23:
	ldr	x8, [x8, _REF_CLK_DPLL@GOTPAGEOFF]
LBB0_5:
	ldr	w8, [x8]
	ldr	w9, [sp, #16]
	orr	w2, w9, w8
	str	w2, [sp, #16]
	mov	x0, x19
	mov	x1, x23
	bl	_cdv_sb_write
	cbnz	w0, LBB0_34
; %bb.6:
	mov	x0, x20
	bl	_SB_M
	mov	x1, x0
	add	x2, sp, #28
	mov	x0, x19
	bl	_cdv_sb_read
	cbnz	w0, LBB0_34
; %bb.7:
Lloh24:
	adrp	x8, _SB_M_DIVIDER_MASK@GOTPAGE
Lloh25:
	ldr	x8, [x8, _SB_M_DIVIDER_MASK@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	ldr	w9, [sp, #28]
	bic	w8, w9, w8
	ldr	w9, [x22]
Lloh27:
	adrp	x10, _SB_M_DIVIDER_SHIFT@GOTPAGE
Lloh28:
	ldr	x10, [x10, _SB_M_DIVIDER_SHIFT@GOTPAGEOFF]
Lloh29:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w8, w9, w8
	str	w8, [sp, #28]
	mov	x0, x20
	bl	_SB_M
	mov	x1, x0
	ldr	w2, [sp, #28]
	mov	x0, x19
	bl	_cdv_sb_write
	cbnz	w0, LBB0_34
; %bb.8:
	mov	x0, x20
	bl	_SB_N_VCO
	mov	x1, x0
	add	x2, sp, #24
	mov	x0, x19
	bl	_cdv_sb_read
	cbnz	w0, LBB0_34
; %bb.9:
	ldr	w8, [sp, #24]
	and	w8, w8, #0xfff8
	mov	w9, #263
	orr	w8, w8, w9
Lloh30:
	adrp	x9, _SB_N_VCO_SEL_MASK@GOTPAGE
Lloh31:
	ldr	x9, [x9, _SB_N_VCO_SEL_MASK@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
Lloh33:
	adrp	x10, _SB_N_DIVIDER_MASK@GOTPAGE
Lloh34:
	ldr	x10, [x10, _SB_N_DIVIDER_MASK@GOTPAGEOFF]
Lloh35:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh36:
	adrp	x10, _SB_N_CB_TUNE_MASK@GOTPAGE
Lloh37:
	ldr	x10, [x10, _SB_N_CB_TUNE_MASK@GOTPAGEOFF]
Lloh38:
	ldr	w10, [x10]
	orr	w9, w9, w10
	bic	w8, w8, w9
Lloh39:
	adrp	x9, _SB_N_DIVIDER_SHIFT@GOTPAGE
Lloh40:
	ldr	x9, [x9, _SB_N_DIVIDER_SHIFT@GOTPAGEOFF]
Lloh41:
	ldr	w10, [x9]
	ldp	w11, w9, [x22, #4]
	lsl	w10, w11, w10
	orr	w8, w10, w8
	mov	w10, #21775
	movk	w10, #34, lsl #16
	cmp	w9, w10
	b.gt	LBB0_12
; %bb.10:
Lloh42:
	adrp	x9, _SB_N_CB_TUNE_SHIFT@GOTPAGE
Lloh43:
	ldr	x9, [x9, _SB_N_CB_TUNE_SHIFT@GOTPAGEOFF]
Lloh44:
	ldr	w9, [x9]
	mov	w10, #2
	lsl	w9, w10, w9
	b	LBB0_18
LBB0_11:
Lloh45:
	adrp	x0, l_.str@PAGE
Lloh46:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_KMS
Lloh47:
	adrp	x8, _REF_CLK_DPLLA@GOTPAGE
Lloh48:
	ldr	x8, [x8, _REF_CLK_DPLLA@GOTPAGEOFF]
	b	LBB0_5
LBB0_12:
	mov	w10, #63023
	movk	w10, #41, lsl #16
	cmp	w9, w10
	b.hi	LBB0_14
; %bb.13:
Lloh49:
	adrp	x9, _SB_N_CB_TUNE_SHIFT@GOTPAGE
Lloh50:
	ldr	x9, [x9, _SB_N_CB_TUNE_SHIFT@GOTPAGEOFF]
Lloh51:
	ldr	w9, [x9]
	mov	w10, #1
	lsl	w9, w10, w9
	orr	w8, w9, w8
Lloh52:
	adrp	x9, _SB_N_VCO_SEL_SHIFT@GOTPAGE
Lloh53:
	ldr	x9, [x9, _SB_N_VCO_SEL_SHIFT@GOTPAGEOFF]
Lloh54:
	ldr	w9, [x9]
	lsl	w9, w10, w9
	b	LBB0_18
LBB0_14:
Lloh55:
	adrp	x10, _SB_N_VCO_SEL_SHIFT@GOTPAGE
Lloh56:
	ldr	x10, [x10, _SB_N_VCO_SEL_SHIFT@GOTPAGEOFF]
Lloh57:
	ldr	w10, [x10]
	mov	w11, #23199
	movk	w11, #50, lsl #16
	cmp	w9, w11
	b.hi	LBB0_16
; %bb.15:
	mov	w9, #2
	b	LBB0_17
LBB0_16:
	mov	w9, #3
LBB0_17:
	lsl	w9, w9, w10
LBB0_18:
	orr	w8, w9, w8
	str	w8, [sp, #24]
	mov	x0, x20
	bl	_SB_N_VCO
	mov	x1, x0
	ldr	w2, [sp, #24]
	mov	x0, x19
	bl	_cdv_sb_write
	cbnz	w0, LBB0_34
; %bb.19:
	mov	x0, x20
	bl	_SB_P
	mov	x1, x0
	add	x2, sp, #20
	mov	x0, x19
	bl	_cdv_sb_read
	cbnz	w0, LBB0_34
; %bb.20:
Lloh58:
	adrp	x8, _SB_P2_DIVIDER_MASK@GOTPAGE
Lloh59:
	ldr	x8, [x8, _SB_P2_DIVIDER_MASK@GOTPAGEOFF]
Lloh60:
	ldr	w8, [x8]
Lloh61:
	adrp	x9, _SB_P1_DIVIDER_MASK@GOTPAGE
Lloh62:
	ldr	x9, [x9, _SB_P1_DIVIDER_MASK@GOTPAGEOFF]
Lloh63:
	ldr	w9, [x9]
	orr	w8, w9, w8
	ldr	w9, [sp, #20]
	bic	w8, w9, w8
	str	w8, [sp, #20]
	ldr	w0, [x22, #16]
Lloh64:
	adrp	x8, _SB_P1_DIVIDER@GOTPAGE
Lloh65:
	ldr	x8, [x8, _SB_P1_DIVIDER@GOTPAGEOFF]
Lloh66:
	ldr	w1, [x8]
	bl	_SET_FIELD
	ldr	w8, [sp, #20]
	orr	w8, w8, w0
	str	w8, [sp, #20]
	ldr	w1, [x22, #12]
	sub	w8, w1, #5
	cmp	w8, #9
	b.hi	LBB0_23
; %bb.21:
Lloh67:
	adrp	x9, lJTI0_0@PAGE
Lloh68:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_22
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_22:
Lloh69:
	adrp	x8, _SB_P2_5@GOTPAGE
Lloh70:
	ldr	x8, [x8, _SB_P2_5@GOTPAGEOFF]
	b	LBB0_27
LBB0_23:
Lloh71:
	adrp	x0, l_.str.2@PAGE
Lloh72:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	_DRM_ERROR
Lloh73:
	adrp	x8, _EINVAL@GOTPAGE
Lloh74:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh75:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_34
LBB0_24:
Lloh76:
	adrp	x8, _SB_P2_7@GOTPAGE
Lloh77:
	ldr	x8, [x8, _SB_P2_7@GOTPAGEOFF]
	b	LBB0_27
LBB0_25:
Lloh78:
	adrp	x8, _SB_P2_10@GOTPAGE
Lloh79:
	ldr	x8, [x8, _SB_P2_10@GOTPAGEOFF]
	b	LBB0_27
LBB0_26:
Lloh80:
	adrp	x8, _SB_P2_14@GOTPAGE
Lloh81:
	ldr	x8, [x8, _SB_P2_14@GOTPAGEOFF]
LBB0_27:
	ldr	w0, [x8]
Lloh82:
	adrp	x8, _SB_P2_DIVIDER@GOTPAGE
Lloh83:
	ldr	x8, [x8, _SB_P2_DIVIDER@GOTPAGEOFF]
Lloh84:
	ldr	w1, [x8]
	bl	_SET_FIELD
	ldr	w8, [sp, #20]
	orr	w8, w8, w0
	str	w8, [sp, #20]
	mov	x0, x20
	bl	_SB_P
	mov	x1, x0
	ldr	w2, [sp, #20]
	mov	x0, x19
	bl	_cdv_sb_write
	cbnz	w0, LBB0_34
; %bb.28:
	cbz	w21, LBB0_33
; %bb.29:
Lloh85:
	adrp	x8, _DDI_MASK@GOTPAGE
Lloh86:
	ldr	x8, [x8, _DDI_MASK@GOTPAGEOFF]
Lloh87:
	ldr	w8, [x8]
	and	w8, w8, w21
Lloh88:
	adrp	x9, _DDI0_SELECT@GOTPAGE
Lloh89:
	ldr	x9, [x9, _DDI0_SELECT@GOTPAGEOFF]
Lloh90:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_31
; %bb.30:
Lloh91:
	adrp	x8, _PSB_LANE0@GOTPAGE
Lloh92:
	ldr	x8, [x8, _PSB_LANE0@GOTPAGEOFF]
Lloh93:
	ldr	w21, [x8]
	add	x2, sp, #12
	mov	x0, x19
	mov	x1, x21
	bl	_cdv_sb_read
Lloh94:
	adrp	x22, _LANE_PLL_MASK@GOTPAGE
Lloh95:
	ldr	x22, [x22, _LANE_PLL_MASK@GOTPAGEOFF]
	ldr	w8, [x22]
	ldr	w9, [sp, #12]
	bic	w8, w9, w8
	str	w8, [sp, #12]
Lloh96:
	adrp	x23, _LANE_PLL_ENABLE@GOTPAGE
Lloh97:
	ldr	x23, [x23, _LANE_PLL_ENABLE@GOTPAGEOFF]
	ldr	w24, [x23]
	mov	x0, x20
	bl	_LANE_PLL_PIPE
	orr	w8, w0, w24
	ldr	w9, [sp, #12]
	orr	w2, w8, w9
	str	w2, [sp, #12]
	mov	x0, x19
	mov	x1, x21
	bl	_cdv_sb_write
Lloh98:
	adrp	x8, _PSB_LANE1@GOTPAGE
Lloh99:
	ldr	x8, [x8, _PSB_LANE1@GOTPAGEOFF]
	b	LBB0_32
LBB0_31:
Lloh100:
	adrp	x8, _PSB_LANE2@GOTPAGE
Lloh101:
	ldr	x8, [x8, _PSB_LANE2@GOTPAGEOFF]
Lloh102:
	ldr	w21, [x8]
	add	x2, sp, #12
	mov	x0, x19
	mov	x1, x21
	bl	_cdv_sb_read
Lloh103:
	adrp	x22, _LANE_PLL_MASK@GOTPAGE
Lloh104:
	ldr	x22, [x22, _LANE_PLL_MASK@GOTPAGEOFF]
	ldr	w8, [x22]
	ldr	w9, [sp, #12]
	bic	w8, w9, w8
	str	w8, [sp, #12]
Lloh105:
	adrp	x23, _LANE_PLL_ENABLE@GOTPAGE
Lloh106:
	ldr	x23, [x23, _LANE_PLL_ENABLE@GOTPAGEOFF]
	ldr	w24, [x23]
	mov	x0, x20
	bl	_LANE_PLL_PIPE
	orr	w8, w0, w24
	ldr	w9, [sp, #12]
	orr	w2, w8, w9
	str	w2, [sp, #12]
	mov	x0, x19
	mov	x1, x21
	bl	_cdv_sb_write
Lloh107:
	adrp	x8, _PSB_LANE3@GOTPAGE
Lloh108:
	ldr	x8, [x8, _PSB_LANE3@GOTPAGEOFF]
LBB0_32:
	ldr	w21, [x8]
	add	x2, sp, #12
	mov	x0, x19
	mov	x1, x21
	bl	_cdv_sb_read
	ldr	w8, [x22]
	ldr	w9, [sp, #12]
	bic	w8, w9, w8
	str	w8, [sp, #12]
	ldr	w22, [x23]
	mov	x0, x20
	bl	_LANE_PLL_PIPE
	orr	w8, w0, w22
	ldr	w9, [sp, #12]
	orr	w2, w8, w9
	str	w2, [sp, #12]
	mov	x0, x19
	mov	x1, x21
	bl	_cdv_sb_write
LBB0_33:
	mov	w0, #0
LBB0_34:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpAdd	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpAdd	Lloh67, Lloh68
	.loh AdrpLdrGot	Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpAdd	Lloh71, Lloh72
	.loh AdrpLdrGot	Lloh76, Lloh77
	.loh AdrpLdrGot	Lloh78, Lloh79
	.loh AdrpLdrGot	Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGot	Lloh98, Lloh99
	.loh AdrpLdrGot	Lloh96, Lloh97
	.loh AdrpLdrGot	Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGot	Lloh107, Lloh108
	.loh AdrpLdrGot	Lloh105, Lloh106
	.loh AdrpLdrGot	Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_22-LBB0_22)>>2
	.byte	(LBB0_23-LBB0_22)>>2
	.byte	(LBB0_24-LBB0_22)>>2
	.byte	(LBB0_23-LBB0_22)>>2
	.byte	(LBB0_23-LBB0_22)>>2
	.byte	(LBB0_25-LBB0_22)>>2
	.byte	(LBB0_23-LBB0_22)>>2
	.byte	(LBB0_23-LBB0_22)>>2
	.byte	(LBB0_23-LBB0_22)>>2
	.byte	(LBB0_26-LBB0_22)>>2
                                        ; -- End function
	.comm	_DPLL_A,4,2                     ; @DPLL_A
	.comm	_DPLL_B,4,2                     ; @DPLL_B
	.comm	_SB_REF_DPLLA,4,2               ; @SB_REF_DPLLA
	.comm	_SB_REF_DPLLB,4,2               ; @SB_REF_DPLLB
	.comm	_DPLL_SYNCLOCK_ENABLE,4,2       ; @DPLL_SYNCLOCK_ENABLE
	.comm	_DPLL_VGA_MODE_DIS,4,2          ; @DPLL_VGA_MODE_DIS
	.comm	_REF_CLK_MASK,4,2               ; @REF_CLK_MASK
	.comm	_DP_MASK,4,2                    ; @DP_MASK
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"use DPLLA for pipe B\n"

	.comm	_REF_CLK_DPLLA,4,2              ; @REF_CLK_DPLLA
l_.str.1:                               ; @.str.1
	.asciz	"use their DPLL for pipe A/B\n"

	.comm	_REF_CLK_DPLL,4,2               ; @REF_CLK_DPLL
	.comm	_SB_M_DIVIDER_MASK,4,2          ; @SB_M_DIVIDER_MASK
	.comm	_SB_M_DIVIDER_SHIFT,4,2         ; @SB_M_DIVIDER_SHIFT
	.comm	_SB_N_VCO_SEL_MASK,4,2          ; @SB_N_VCO_SEL_MASK
	.comm	_SB_N_DIVIDER_MASK,4,2          ; @SB_N_DIVIDER_MASK
	.comm	_SB_N_CB_TUNE_MASK,4,2          ; @SB_N_CB_TUNE_MASK
	.comm	_SB_N_DIVIDER_SHIFT,4,2         ; @SB_N_DIVIDER_SHIFT
	.comm	_SB_N_CB_TUNE_SHIFT,4,2         ; @SB_N_CB_TUNE_SHIFT
	.comm	_SB_N_VCO_SEL_SHIFT,4,2         ; @SB_N_VCO_SEL_SHIFT
	.comm	_SB_P2_DIVIDER_MASK,4,2         ; @SB_P2_DIVIDER_MASK
	.comm	_SB_P1_DIVIDER_MASK,4,2         ; @SB_P1_DIVIDER_MASK
	.comm	_SB_P1_DIVIDER,4,2              ; @SB_P1_DIVIDER
	.comm	_SB_P2_5,4,2                    ; @SB_P2_5
	.comm	_SB_P2_DIVIDER,4,2              ; @SB_P2_DIVIDER
	.comm	_SB_P2_10,4,2                   ; @SB_P2_10
	.comm	_SB_P2_14,4,2                   ; @SB_P2_14
	.comm	_SB_P2_7,4,2                    ; @SB_P2_7
l_.str.2:                               ; @.str.2
	.asciz	"Bad P2 clock: %d\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_DDI_MASK,4,2                   ; @DDI_MASK
	.comm	_DDI0_SELECT,4,2                ; @DDI0_SELECT
	.comm	_PSB_LANE0,4,2                  ; @PSB_LANE0
	.comm	_LANE_PLL_MASK,4,2              ; @LANE_PLL_MASK
	.comm	_LANE_PLL_ENABLE,4,2            ; @LANE_PLL_ENABLE
	.comm	_PSB_LANE1,4,2                  ; @PSB_LANE1
	.comm	_PSB_LANE2,4,2                  ; @PSB_LANE2
	.comm	_PSB_LANE3,4,2                  ; @PSB_LANE3
	.no_dead_strip	_cdv_dpll_set_clock_cdv
.subsections_via_symbols
