	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v2_5_stop
_vcn_v2_5_stop:                         ## @vcn_v2_5_stop
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	callq	_jpeg_v2_5_stop
	testl	%eax, %eax
	jne	LBB0_7
## %bb.1:
	movl	(%r14), %eax
	testl	%eax, %eax
	jle	LBB0_6
## %bb.2:
	xorl	%ebx, %ebx
	movq	_VCN@GOTPCREL(%rip), %r15
	jmp	LBB0_3
	.p2align	4, 0x90
LBB0_5:                                 ##   in Loop: Header=BB0_3 Depth=1
	incl	%ebx
	cmpl	%eax, %ebx
	jge	LBB0_6
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movl	4(%r14), %ecx
	btl	%ebx, %ecx
	jb	LBB0_5
## %bb.4:                               ##   in Loop: Header=BB0_3 Depth=1
	movl	(%r15), %edi
	movq	_mmUVD_STATUS@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movq	_UVD_STATUS__IDLE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ebx, %esi
	movl	$7, %r8d
	xorl	%r9d, %r9d
	callq	_SOC15_WAIT_ON_RREG
	movq	_UVD_LMI_STATUS__READ_CLEAN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	_UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_UVD_LMI_STATUS__WRITE_CLEAN_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movl	(%r15), %edi
	movq	_mmUVD_LMI_STATUS@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	movl	%ebx, %esi
	movl	%ecx, %r8d
	xorl	%r9d, %r9d
	callq	_SOC15_WAIT_ON_RREG
	movl	(%r15), %edi
	movq	_mmUVD_LMI_CTRL2@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movl	%ebx, %esi
	callq	_RREG32_SOC15
	movq	_UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r15), %edi
	movl	(%r12), %edx
	movl	%ebx, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	_UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	_UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movl	(%r15), %edi
	movl	(%r13), %edx
	movl	%ebx, %esi
	movl	%ecx, %r8d
	xorl	%r9d, %r9d
	callq	_SOC15_WAIT_ON_RREG
	movq	_UVD@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	movq	_mmUVD_RB_ARB_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%ebx, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_RB_ARB_CTRL__VCPU_DIS_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	callq	_WREG32_P
	movl	(%r12), %edi
	movq	_mmUVD_VCPU_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	movl	%ebx, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_VCPU_CNTL__BLK_RST_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	callq	_WREG32_P
	movl	(%r12), %edi
	movl	(%r13), %edx
	movl	%ebx, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_VCPU_CNTL__CLK_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	(%r15), %edi
	movq	_mmUVD_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%ebx, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movq	%r14, %rdi
	callq	_vcn_v2_5_enable_clock_gating
	movl	(%r12), %edi
	movq	_mmUVD_POWER_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%ebx, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_POWER_STATUS__UVD_POWER_STATUS_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	callq	_WREG32_P
	movl	(%r14), %eax
	jmp	LBB0_5
LBB0_6:
	xorl	%eax, %eax
LBB0_7:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_VCN,4,2                        ## @VCN
	.comm	_mmUVD_STATUS,4,2               ## @mmUVD_STATUS
	.comm	_UVD_STATUS__IDLE,4,2           ## @UVD_STATUS__IDLE
	.comm	_UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK,4,2 ## @UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK
	.comm	_UVD_LMI_STATUS__READ_CLEAN_MASK,4,2 ## @UVD_LMI_STATUS__READ_CLEAN_MASK
	.comm	_UVD_LMI_STATUS__WRITE_CLEAN_MASK,4,2 ## @UVD_LMI_STATUS__WRITE_CLEAN_MASK
	.comm	_UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK,4,2 ## @UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK
	.comm	_mmUVD_LMI_STATUS,4,2           ## @mmUVD_LMI_STATUS
	.comm	_mmUVD_LMI_CTRL2,4,2            ## @mmUVD_LMI_CTRL2
	.comm	_UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,4,2 ## @UVD_LMI_CTRL2__STALL_ARB_UMC_MASK
	.comm	_UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK,4,2 ## @UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK
	.comm	_UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK,4,2 ## @UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_RB_ARB_CTRL,4,2          ## @mmUVD_RB_ARB_CTRL
	.comm	_UVD_RB_ARB_CTRL__VCPU_DIS_MASK,4,2 ## @UVD_RB_ARB_CTRL__VCPU_DIS_MASK
	.comm	_mmUVD_VCPU_CNTL,4,2            ## @mmUVD_VCPU_CNTL
	.comm	_UVD_VCPU_CNTL__BLK_RST_MASK,4,2 ## @UVD_VCPU_CNTL__BLK_RST_MASK
	.comm	_UVD_VCPU_CNTL__CLK_EN_MASK,4,2 ## @UVD_VCPU_CNTL__CLK_EN_MASK
	.comm	_mmUVD_POWER_STATUS,4,2         ## @mmUVD_POWER_STATUS
	.comm	_UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,4,2 ## @UVD_POWER_STATUS__UVD_POWER_STATUS_MASK
	.no_dead_strip	_vcn_v2_5_stop
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v2_5_stop
_vcn_v2_5_stop:                         ; @vcn_v2_5_stop
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	bl	_jpeg_v2_5_stop
	cbnz	w0, LBB0_7
; %bb.1:
	ldr	w8, [x19]
	cmp	w8, #1
	b.lt	LBB0_6
; %bb.2:
	mov	w20, #0
Lloh0:
	adrp	x21, _VCN@GOTPAGE
Lloh1:
	ldr	x21, [x21, _VCN@GOTPAGEOFF]
Lloh2:
	adrp	x22, _mmUVD_STATUS@GOTPAGE
Lloh3:
	ldr	x22, [x22, _mmUVD_STATUS@GOTPAGEOFF]
Lloh4:
	adrp	x28, _mmUVD_LMI_STATUS@GOTPAGE
Lloh5:
	ldr	x28, [x28, _mmUVD_LMI_STATUS@GOTPAGEOFF]
Lloh6:
	adrp	x23, _mmUVD_LMI_CTRL2@GOTPAGE
Lloh7:
	ldr	x23, [x23, _mmUVD_LMI_CTRL2@GOTPAGEOFF]
Lloh8:
	adrp	x27, _UVD@GOTPAGE
Lloh9:
	ldr	x27, [x27, _UVD@GOTPAGEOFF]
Lloh10:
	adrp	x26, _mmUVD_VCPU_CNTL@GOTPAGE
Lloh11:
	ldr	x26, [x26, _mmUVD_VCPU_CNTL@GOTPAGEOFF]
Lloh12:
	adrp	x24, _mmUVD_POWER_STATUS@GOTPAGE
Lloh13:
	ldr	x24, [x24, _mmUVD_POWER_STATUS@GOTPAGEOFF]
Lloh14:
	adrp	x25, _UVD_POWER_STATUS__UVD_POWER_STATUS_MASK@GOTPAGE
Lloh15:
	ldr	x25, [x25, _UVD_POWER_STATUS__UVD_POWER_STATUS_MASK@GOTPAGEOFF]
	b	LBB0_4
LBB0_3:                                 ;   in Loop: Header=BB0_4 Depth=1
	add	w20, w20, #1
	cmp	w20, w8
	b.ge	LBB0_6
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w9, [x19, #4]
	lsr	w9, w9, w20
	tbnz	w9, #0, LBB0_3
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	ldr	w0, [x21]
	ldr	w2, [x22]
Lloh16:
	adrp	x8, _UVD_STATUS__IDLE@GOTPAGE
Lloh17:
	ldr	x8, [x8, _UVD_STATUS__IDLE@GOTPAGEOFF]
Lloh18:
	ldr	w3, [x8]
	mov	x1, x20
	mov	w4, #7
	mov	w5, #0
	bl	_SOC15_WAIT_ON_RREG
Lloh19:
	adrp	x8, _UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK@GOTPAGE
Lloh20:
	ldr	x8, [x8, _UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
Lloh22:
	adrp	x9, _UVD_LMI_STATUS__READ_CLEAN_MASK@GOTPAGE
Lloh23:
	ldr	x9, [x9, _UVD_LMI_STATUS__READ_CLEAN_MASK@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh25:
	adrp	x9, _UVD_LMI_STATUS__WRITE_CLEAN_MASK@GOTPAGE
Lloh26:
	ldr	x9, [x9, _UVD_LMI_STATUS__WRITE_CLEAN_MASK@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh28:
	adrp	x9, _UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK@GOTPAGE
Lloh29:
	ldr	x9, [x9, _UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
	orr	w3, w8, w9
	ldr	w0, [x21]
	ldr	w2, [x28]
	mov	x1, x20
	mov	x4, x3
	mov	w5, #0
	bl	_SOC15_WAIT_ON_RREG
	ldr	w0, [x21]
	ldr	w2, [x23]
	mov	x1, x20
	bl	_RREG32_SOC15
Lloh31:
	adrp	x8, _UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPAGE
Lloh32:
	ldr	x8, [x8, _UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
	orr	w3, w8, w0
	ldr	w0, [x21]
	ldr	w2, [x23]
	mov	x1, x20
	bl	_WREG32_SOC15
Lloh34:
	adrp	x8, _UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK@GOTPAGE
Lloh35:
	ldr	x8, [x8, _UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK@GOTPAGEOFF]
Lloh36:
	ldr	w8, [x8]
Lloh37:
	adrp	x9, _UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK@GOTPAGE
Lloh38:
	ldr	x9, [x9, _UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK@GOTPAGEOFF]
Lloh39:
	ldr	w9, [x9]
	orr	w3, w9, w8
	ldr	w0, [x21]
	ldr	w2, [x28]
	mov	x1, x20
	mov	x4, x3
	mov	w5, #0
	bl	_SOC15_WAIT_ON_RREG
	ldr	w0, [x27]
Lloh40:
	adrp	x8, _mmUVD_RB_ARB_CTRL@GOTPAGE
Lloh41:
	ldr	x8, [x8, _mmUVD_RB_ARB_CTRL@GOTPAGEOFF]
Lloh42:
	ldr	w2, [x8]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
Lloh43:
	adrp	x8, _UVD_RB_ARB_CTRL__VCPU_DIS_MASK@GOTPAGE
Lloh44:
	ldr	x8, [x8, _UVD_RB_ARB_CTRL__VCPU_DIS_MASK@GOTPAGEOFF]
Lloh45:
	ldr	w1, [x8]
	mvn	w2, w1
	bl	_WREG32_P
	ldr	w0, [x27]
	ldr	w2, [x26]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
Lloh46:
	adrp	x8, _UVD_VCPU_CNTL__BLK_RST_MASK@GOTPAGE
Lloh47:
	ldr	x8, [x8, _UVD_VCPU_CNTL__BLK_RST_MASK@GOTPAGEOFF]
Lloh48:
	ldr	w1, [x8]
	mvn	w2, w1
	bl	_WREG32_P
	ldr	w0, [x27]
	ldr	w2, [x26]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
Lloh49:
	adrp	x8, _UVD_VCPU_CNTL__CLK_EN_MASK@GOTPAGE
Lloh50:
	ldr	x8, [x8, _UVD_VCPU_CNTL__CLK_EN_MASK@GOTPAGEOFF]
Lloh51:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w0, [x21]
	ldr	w2, [x22]
	mov	x1, x20
	mov	w3, #0
	bl	_WREG32_SOC15
	mov	x0, x19
	bl	_vcn_v2_5_enable_clock_gating
	ldr	w0, [x27]
	ldr	w2, [x24]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	ldr	w1, [x25]
	mvn	w2, w1
	bl	_WREG32_P
	ldr	w8, [x19]
	b	LBB0_3
LBB0_6:
	mov	w0, #0
LBB0_7:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.cfi_endproc
                                        ; -- End function
	.comm	_VCN,4,2                        ; @VCN
	.comm	_mmUVD_STATUS,4,2               ; @mmUVD_STATUS
	.comm	_UVD_STATUS__IDLE,4,2           ; @UVD_STATUS__IDLE
	.comm	_UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK,4,2 ; @UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK
	.comm	_UVD_LMI_STATUS__READ_CLEAN_MASK,4,2 ; @UVD_LMI_STATUS__READ_CLEAN_MASK
	.comm	_UVD_LMI_STATUS__WRITE_CLEAN_MASK,4,2 ; @UVD_LMI_STATUS__WRITE_CLEAN_MASK
	.comm	_UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK,4,2 ; @UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK
	.comm	_mmUVD_LMI_STATUS,4,2           ; @mmUVD_LMI_STATUS
	.comm	_mmUVD_LMI_CTRL2,4,2            ; @mmUVD_LMI_CTRL2
	.comm	_UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,4,2 ; @UVD_LMI_CTRL2__STALL_ARB_UMC_MASK
	.comm	_UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK,4,2 ; @UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK
	.comm	_UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK,4,2 ; @UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_RB_ARB_CTRL,4,2          ; @mmUVD_RB_ARB_CTRL
	.comm	_UVD_RB_ARB_CTRL__VCPU_DIS_MASK,4,2 ; @UVD_RB_ARB_CTRL__VCPU_DIS_MASK
	.comm	_mmUVD_VCPU_CNTL,4,2            ; @mmUVD_VCPU_CNTL
	.comm	_UVD_VCPU_CNTL__BLK_RST_MASK,4,2 ; @UVD_VCPU_CNTL__BLK_RST_MASK
	.comm	_UVD_VCPU_CNTL__CLK_EN_MASK,4,2 ; @UVD_VCPU_CNTL__CLK_EN_MASK
	.comm	_mmUVD_POWER_STATUS,4,2         ; @mmUVD_POWER_STATUS
	.comm	_UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,4,2 ; @UVD_POWER_STATUS__UVD_POWER_STATUS_MASK
	.no_dead_strip	_vcn_v2_5_stop
.subsections_via_symbols
