	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function uvd_v5_0_mc_resume
_uvd_v5_0_mc_resume:                    ## @uvd_v5_0_mc_resume
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	16(%rdi), %rax
	movl	(%rax), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	16(%r14), %rax
	movl	(%rax), %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_AMDGPU_UVD_FIRMWARE_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	%r14, %rdi
	callq	_AMDGPU_UVD_FIRMWARE_SIZE
	movl	%eax, %r12d
	movq	_mmUVD_VCPU_CACHE_OFFSET0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	sarl	$3, %esi
	callq	_WREG32
	movq	_mmUVD_VCPU_CACHE_SIZE0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	addl	%ebx, %r12d
	movq	_AMDGPU_UVD_HEAP_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_mmUVD_VCPU_CACHE_OFFSET1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	sarl	$3, %esi
	callq	_WREG32
	movq	_mmUVD_VCPU_CACHE_SIZE1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movq	_AMDGPU_UVD_SESSION_SIZE@GOTPCREL(%rip), %rax
	movl	8(%r14), %ebx
	imull	(%rax), %ebx
	movq	_AMDGPU_UVD_STACK_SIZE@GOTPCREL(%rip), %rax
	addl	(%rax), %ebx
	addl	%r15d, %r12d
	movq	_mmUVD_VCPU_CACHE_OFFSET2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	sarl	$3, %r12d
	movl	%r12d, %esi
	callq	_WREG32
	movq	_mmUVD_VCPU_CACHE_SIZE2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_mmUVD_UDEC_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r14), %esi
	callq	_WREG32
	movq	_mmUVD_UDEC_DB_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r14), %esi
	callq	_WREG32
	movq	_mmUVD_UDEC_DBW_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r14), %esi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
	.comm	_AMDGPU_UVD_FIRMWARE_OFFSET,4,2 ## @AMDGPU_UVD_FIRMWARE_OFFSET
	.comm	_mmUVD_VCPU_CACHE_OFFSET0,4,2   ## @mmUVD_VCPU_CACHE_OFFSET0
	.comm	_mmUVD_VCPU_CACHE_SIZE0,4,2     ## @mmUVD_VCPU_CACHE_SIZE0
	.comm	_AMDGPU_UVD_HEAP_SIZE,4,2       ## @AMDGPU_UVD_HEAP_SIZE
	.comm	_mmUVD_VCPU_CACHE_OFFSET1,4,2   ## @mmUVD_VCPU_CACHE_OFFSET1
	.comm	_mmUVD_VCPU_CACHE_SIZE1,4,2     ## @mmUVD_VCPU_CACHE_SIZE1
	.comm	_AMDGPU_UVD_STACK_SIZE,4,2      ## @AMDGPU_UVD_STACK_SIZE
	.comm	_AMDGPU_UVD_SESSION_SIZE,4,2    ## @AMDGPU_UVD_SESSION_SIZE
	.comm	_mmUVD_VCPU_CACHE_OFFSET2,4,2   ## @mmUVD_VCPU_CACHE_OFFSET2
	.comm	_mmUVD_VCPU_CACHE_SIZE2,4,2     ## @mmUVD_VCPU_CACHE_SIZE2
	.comm	_mmUVD_UDEC_ADDR_CONFIG,4,2     ## @mmUVD_UDEC_ADDR_CONFIG
	.comm	_mmUVD_UDEC_DB_ADDR_CONFIG,4,2  ## @mmUVD_UDEC_DB_ADDR_CONFIG
	.comm	_mmUVD_UDEC_DBW_ADDR_CONFIG,4,2 ## @mmUVD_UDEC_DBW_ADDR_CONFIG
	.no_dead_strip	_uvd_v5_0_mc_resume
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function uvd_v5_0_mc_resume
_uvd_v5_0_mc_resume:                    ; @uvd_v5_0_mc_resume
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW@GOTPAGE
Lloh1:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh2:
	ldr	w20, [x8]
	ldr	x8, [x0, #16]
	ldr	w0, [x8]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
Lloh3:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPAGE
Lloh4:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh5:
	ldr	w20, [x8]
	ldr	x8, [x19, #16]
	ldr	w0, [x8]
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
Lloh6:
	adrp	x8, _AMDGPU_UVD_FIRMWARE_OFFSET@GOTPAGE
Lloh7:
	ldr	x8, [x8, _AMDGPU_UVD_FIRMWARE_OFFSET@GOTPAGEOFF]
Lloh8:
	ldr	w21, [x8]
	mov	x0, x19
	bl	_AMDGPU_UVD_FIRMWARE_SIZE
	mov	x20, x0
Lloh9:
	adrp	x8, _mmUVD_VCPU_CACHE_OFFSET0@GOTPAGE
Lloh10:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_OFFSET0@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	asr	w1, w21, #3
	bl	_WREG32
Lloh12:
	adrp	x8, _mmUVD_VCPU_CACHE_SIZE0@GOTPAGE
Lloh13:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_SIZE0@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh15:
	adrp	x8, _AMDGPU_UVD_HEAP_SIZE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _AMDGPU_UVD_HEAP_SIZE@GOTPAGEOFF]
	add	w21, w20, w21
Lloh17:
	ldr	w20, [x8]
Lloh18:
	adrp	x8, _mmUVD_VCPU_CACHE_OFFSET1@GOTPAGE
Lloh19:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_OFFSET1@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
	asr	w1, w21, #3
	bl	_WREG32
Lloh21:
	adrp	x8, _mmUVD_VCPU_CACHE_SIZE1@GOTPAGE
Lloh22:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_SIZE1@GOTPAGEOFF]
Lloh23:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
	add	w8, w20, w21
Lloh24:
	adrp	x9, _AMDGPU_UVD_STACK_SIZE@GOTPAGE
Lloh25:
	ldr	x9, [x9, _AMDGPU_UVD_STACK_SIZE@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
Lloh27:
	adrp	x10, _AMDGPU_UVD_SESSION_SIZE@GOTPAGE
Lloh28:
	ldr	x10, [x10, _AMDGPU_UVD_SESSION_SIZE@GOTPAGEOFF]
Lloh29:
	ldr	w10, [x10]
	ldr	w11, [x19, #8]
	madd	w20, w11, w10, w9
Lloh30:
	adrp	x9, _mmUVD_VCPU_CACHE_OFFSET2@GOTPAGE
Lloh31:
	ldr	x9, [x9, _mmUVD_VCPU_CACHE_OFFSET2@GOTPAGEOFF]
Lloh32:
	ldr	w0, [x9]
	asr	w1, w8, #3
	bl	_WREG32
Lloh33:
	adrp	x8, _mmUVD_VCPU_CACHE_SIZE2@GOTPAGE
Lloh34:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_SIZE2@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh36:
	adrp	x8, _mmUVD_UDEC_ADDR_CONFIG@GOTPAGE
Lloh37:
	ldr	x8, [x8, _mmUVD_UDEC_ADDR_CONFIG@GOTPAGEOFF]
Lloh38:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_WREG32
Lloh39:
	adrp	x8, _mmUVD_UDEC_DB_ADDR_CONFIG@GOTPAGE
Lloh40:
	ldr	x8, [x8, _mmUVD_UDEC_DB_ADDR_CONFIG@GOTPAGEOFF]
Lloh41:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_WREG32
Lloh42:
	adrp	x8, _mmUVD_UDEC_DBW_ADDR_CONFIG@GOTPAGE
Lloh43:
	ldr	x8, [x8, _mmUVD_UDEC_DBW_ADDR_CONFIG@GOTPAGEOFF]
Lloh44:
	ldr	w0, [x8]
	ldr	w1, [x19]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
	.comm	_AMDGPU_UVD_FIRMWARE_OFFSET,4,2 ; @AMDGPU_UVD_FIRMWARE_OFFSET
	.comm	_mmUVD_VCPU_CACHE_OFFSET0,4,2   ; @mmUVD_VCPU_CACHE_OFFSET0
	.comm	_mmUVD_VCPU_CACHE_SIZE0,4,2     ; @mmUVD_VCPU_CACHE_SIZE0
	.comm	_AMDGPU_UVD_HEAP_SIZE,4,2       ; @AMDGPU_UVD_HEAP_SIZE
	.comm	_mmUVD_VCPU_CACHE_OFFSET1,4,2   ; @mmUVD_VCPU_CACHE_OFFSET1
	.comm	_mmUVD_VCPU_CACHE_SIZE1,4,2     ; @mmUVD_VCPU_CACHE_SIZE1
	.comm	_AMDGPU_UVD_STACK_SIZE,4,2      ; @AMDGPU_UVD_STACK_SIZE
	.comm	_AMDGPU_UVD_SESSION_SIZE,4,2    ; @AMDGPU_UVD_SESSION_SIZE
	.comm	_mmUVD_VCPU_CACHE_OFFSET2,4,2   ; @mmUVD_VCPU_CACHE_OFFSET2
	.comm	_mmUVD_VCPU_CACHE_SIZE2,4,2     ; @mmUVD_VCPU_CACHE_SIZE2
	.comm	_mmUVD_UDEC_ADDR_CONFIG,4,2     ; @mmUVD_UDEC_ADDR_CONFIG
	.comm	_mmUVD_UDEC_DB_ADDR_CONFIG,4,2  ; @mmUVD_UDEC_DB_ADDR_CONFIG
	.comm	_mmUVD_UDEC_DBW_ADDR_CONFIG,4,2 ; @mmUVD_UDEC_DBW_ADDR_CONFIG
	.no_dead_strip	_uvd_v5_0_mc_resume
.subsections_via_symbols
