	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_get_crtc_scanoutpos     ## -- Begin function radeon_get_crtc_scanoutpos
	.p2align	4, 0x90
_radeon_get_crtc_scanoutpos:            ## @radeon_get_crtc_scanoutpos
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%r8, -72(%rbp)                  ## 8-byte Spill
	movq	%rcx, %r15
	movl	%edx, %r14d
	movl	%esi, %r12d
	movq	(%rdi), %r13
	testq	%r9, %r9
	je	LBB0_2
## %bb.1:
	movq	%r9, %rbx
	xorl	%eax, %eax
	callq	_ktime_get
	movl	%eax, (%rbx)
LBB0_2:
	movq	%r13, %rdi
	callq	_ASIC_IS_DCE4
	testq	%rax, %rax
	movl	%r12d, -52(%rbp)                ## 4-byte Spill
	movq	%r13, -64(%rbp)                 ## 8-byte Spill
	movl	%r14d, -48(%rbp)                ## 4-byte Spill
	je	LBB0_13
## %bb.3:
	cmpl	$5, %r12d
	ja	LBB0_4
## %bb.5:
	movl	%r12d, %eax
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_6:
	movl	$1, -44(%rbp)                   ## 4-byte Folded Spill
	movq	_EVERGREEN_CRTC_V_BLANK_START_END@GOTPCREL(%rip), %rax
	movq	_EVERGREEN_CRTC0_REGISTER_OFFSET@GOTPCREL(%rip), %r14
	jmp	LBB0_7
LBB0_13:
	movq	%r13, %rdi
	callq	_ASIC_IS_AVIVO
	testq	%rax, %rax
	je	LBB0_21
## %bb.14:
	cmpl	$1, %r12d
	je	LBB0_20
## %bb.15:
	movl	$1, -44(%rbp)                   ## 4-byte Folded Spill
	xorl	%r13d, %r13d
	testl	%r12d, %r12d
	jne	LBB0_16
## %bb.17:
	movq	_AVIVO_D1CRTC_V_BLANK_START_END@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %r13d
	movq	_AVIVO_D1CRTC_STATUS_POSITION@GOTPCREL(%rip), %rax
	jmp	LBB0_18
LBB0_21:
	cmpl	$1, %r12d
	je	LBB0_24
## %bb.22:
	testl	%r12d, %r12d
	jne	LBB0_4
## %bb.23:
	movq	_RADEON_CRTC_V_TOTAL_DISP@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %r13d
	movq	_RADEON_CRTC_V_DISP@GOTPCREL(%rip), %rax
	andl	(%rax), %r13d
	movq	_RADEON_CRTC_V_DISP_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarl	%cl, %r13d
	movq	_RADEON_CRTC_VLINE_CRNT_VLINE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %r12d
	sarl	$16, %r12d
	movq	_RADEON_CRTC_V_TOTAL@GOTPCREL(%rip), %rax
	andl	(%rax), %r12d
	movq	_RADEON_CRTC_STATUS@GOTPCREL(%rip), %rax
	jmp	LBB0_25
LBB0_4:
	movl	$1, -44(%rbp)                   ## 4-byte Folded Spill
	xorl	%r13d, %r13d
LBB0_16:
	xorl	%r12d, %r12d
	xorl	%r14d, %r14d
	jmp	LBB0_27
LBB0_8:
	movl	$1, -44(%rbp)                   ## 4-byte Folded Spill
	movq	_EVERGREEN_CRTC_V_BLANK_START_END@GOTPCREL(%rip), %rax
	movq	_EVERGREEN_CRTC1_REGISTER_OFFSET@GOTPCREL(%rip), %r14
	jmp	LBB0_7
LBB0_9:
	movl	$1, -44(%rbp)                   ## 4-byte Folded Spill
	movq	_EVERGREEN_CRTC_V_BLANK_START_END@GOTPCREL(%rip), %rax
	movq	_EVERGREEN_CRTC2_REGISTER_OFFSET@GOTPCREL(%rip), %r14
	jmp	LBB0_7
LBB0_10:
	movl	$1, -44(%rbp)                   ## 4-byte Folded Spill
	movq	_EVERGREEN_CRTC_V_BLANK_START_END@GOTPCREL(%rip), %rax
	movq	_EVERGREEN_CRTC3_REGISTER_OFFSET@GOTPCREL(%rip), %r14
	jmp	LBB0_7
LBB0_11:
	movl	$1, -44(%rbp)                   ## 4-byte Folded Spill
	movq	_EVERGREEN_CRTC_V_BLANK_START_END@GOTPCREL(%rip), %rax
	movq	_EVERGREEN_CRTC4_REGISTER_OFFSET@GOTPCREL(%rip), %r14
	jmp	LBB0_7
LBB0_12:
	movl	$1, -44(%rbp)                   ## 4-byte Folded Spill
	movq	_EVERGREEN_CRTC_V_BLANK_START_END@GOTPCREL(%rip), %rax
	movq	_EVERGREEN_CRTC5_REGISTER_OFFSET@GOTPCREL(%rip), %r14
LBB0_7:
	movq	(%r14), %rdi
	addq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %r13d
	movq	_EVERGREEN_CRTC_STATUS_POSITION@GOTPCREL(%rip), %rax
	movq	(%r14), %rdi
	addq	(%rax), %rdi
	jmp	LBB0_19
LBB0_20:
	movl	$1, -44(%rbp)                   ## 4-byte Folded Spill
	movq	_AVIVO_D2CRTC_V_BLANK_START_END@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %r13d
	movq	_AVIVO_D2CRTC_STATUS_POSITION@GOTPCREL(%rip), %rax
LBB0_18:
	movq	(%rax), %rdi
LBB0_19:
	callq	_RREG32
	movl	%eax, %r12d
LBB0_26:
	movq	_DRM_SCANOUTPOS_VALID@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
LBB0_27:
	movq	16(%rbp), %rax
	testq	%rax, %rax
	je	LBB0_29
## %bb.28:
	movq	%rax, %rbx
	xorl	%eax, %eax
	callq	_ktime_get
	movl	%eax, (%rbx)
LBB0_29:
	movq	24(%rbp), %r8
	movl	%r12d, %eax
	andl	$8191, %eax                     ## imm = 0x1FFF
	movl	%eax, (%r15)
	shrl	$16, %r12d
	andl	$8191, %r12d                    ## imm = 0x1FFF
	movq	-72(%rbp), %rcx                 ## 8-byte Reload
	movl	%r12d, (%rcx)
	testl	%r13d, %r13d
	jle	LBB0_31
## %bb.30:
	movq	_DRM_SCANOUTPOS_ACCURATE@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
	movl	%r13d, %esi
	andl	$8191, %esi                     ## imm = 0x1FFF
	shrl	$16, %r13d
	andl	$8191, %r13d                    ## imm = 0x1FFF
	jmp	LBB0_32
LBB0_31:
	movl	(%r8), %esi
	xorl	%r13d, %r13d
LBB0_32:
	movl	-48(%rbp), %r10d                ## 4-byte Reload
	movq	_GET_DISTANCE_TO_VBLANKSTART@GOTPCREL(%rip), %r9
	testl	%r10d, (%r9)
	je	LBB0_34
## %bb.33:
	movl	(%r15), %eax
	subl	%esi, %eax
	movl	%eax, (%rcx)
LBB0_34:
	movq	_USE_REAL_VBLANKSTART@GOTPCREL(%rip), %rax
	testl	%r10d, (%rax)
	jne	LBB0_36
## %bb.35:
	movq	-64(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rax
	movl	-52(%rbp), %ecx                 ## 4-byte Reload
	movq	(%rax,%rcx,8), %rax
	subl	(%rax), %esi
LBB0_36:
	movl	(%r15), %ebx
	movl	%ebx, %edi
	subl	%esi, %edi
	setl	%al
	cmpl	%r13d, %ebx
	setge	%dl
	andb	%al, %dl
	cmpl	$0, -44(%rbp)                   ## 4-byte Folded Reload
	sete	%cl
	orb	%dl, %cl
	movq	_DRM_SCANOUTPOS_IN_VBLANK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%r10d, (%r9)
	jne	LBB0_40
## %bb.37:
	cmpl	%esi, %ebx
	setl	%dl
	orb	%cl, %dl
	jne	LBB0_39
## %bb.38:
	subl	4(%r8), %ebx
LBB0_39:
	subl	%r13d, %ebx
	movl	%ebx, %edi
LBB0_40:
	xorl	%edx, %edx
	testb	%cl, %cl
	cmovnel	%edx, %eax
	orl	%r14d, %eax
	movl	%edi, (%r15)
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_24:
	movq	_RADEON_CRTC2_V_TOTAL_DISP@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %r13d
	movq	_RADEON_CRTC_V_DISP@GOTPCREL(%rip), %rax
	andl	(%rax), %r13d
	movq	_RADEON_CRTC_V_DISP_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarl	%cl, %r13d
	movq	_RADEON_CRTC2_VLINE_CRNT_VLINE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %r12d
	sarl	$16, %r12d
	movq	_RADEON_CRTC_V_TOTAL@GOTPCREL(%rip), %rax
	andl	(%rax), %r12d
	movq	_RADEON_CRTC2_STATUS@GOTPCREL(%rip), %rax
LBB0_25:
	movq	(%rax), %rdi
	callq	_RREG32
	andl	$1, %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	jmp	LBB0_26
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_6, LBB0_6-LJTI0_0
.set L0_0_set_8, LBB0_8-LJTI0_0
.set L0_0_set_9, LBB0_9-LJTI0_0
.set L0_0_set_10, LBB0_10-LJTI0_0
.set L0_0_set_11, LBB0_11-LJTI0_0
.set L0_0_set_12, LBB0_12-LJTI0_0
LJTI0_0:
	.long	L0_0_set_6
	.long	L0_0_set_8
	.long	L0_0_set_9
	.long	L0_0_set_10
	.long	L0_0_set_11
	.long	L0_0_set_12
	.end_data_region
                                        ## -- End function
	.comm	_EVERGREEN_CRTC_V_BLANK_START_END,8,3 ## @EVERGREEN_CRTC_V_BLANK_START_END
	.comm	_EVERGREEN_CRTC0_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC0_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC_STATUS_POSITION,8,3 ## @EVERGREEN_CRTC_STATUS_POSITION
	.comm	_DRM_SCANOUTPOS_VALID,4,2       ## @DRM_SCANOUTPOS_VALID
	.comm	_EVERGREEN_CRTC1_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC1_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC2_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC2_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC3_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC3_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC4_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC4_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC5_REGISTER_OFFSET,8,3 ## @EVERGREEN_CRTC5_REGISTER_OFFSET
	.comm	_AVIVO_D1CRTC_V_BLANK_START_END,8,3 ## @AVIVO_D1CRTC_V_BLANK_START_END
	.comm	_AVIVO_D1CRTC_STATUS_POSITION,8,3 ## @AVIVO_D1CRTC_STATUS_POSITION
	.comm	_AVIVO_D2CRTC_V_BLANK_START_END,8,3 ## @AVIVO_D2CRTC_V_BLANK_START_END
	.comm	_AVIVO_D2CRTC_STATUS_POSITION,8,3 ## @AVIVO_D2CRTC_STATUS_POSITION
	.comm	_RADEON_CRTC_V_TOTAL_DISP,8,3   ## @RADEON_CRTC_V_TOTAL_DISP
	.comm	_RADEON_CRTC_V_DISP,4,2         ## @RADEON_CRTC_V_DISP
	.comm	_RADEON_CRTC_V_DISP_SHIFT,4,2   ## @RADEON_CRTC_V_DISP_SHIFT
	.comm	_RADEON_CRTC_VLINE_CRNT_VLINE,8,3 ## @RADEON_CRTC_VLINE_CRNT_VLINE
	.comm	_RADEON_CRTC_V_TOTAL,4,2        ## @RADEON_CRTC_V_TOTAL
	.comm	_RADEON_CRTC_STATUS,8,3         ## @RADEON_CRTC_STATUS
	.comm	_RADEON_CRTC2_V_TOTAL_DISP,8,3  ## @RADEON_CRTC2_V_TOTAL_DISP
	.comm	_RADEON_CRTC2_VLINE_CRNT_VLINE,8,3 ## @RADEON_CRTC2_VLINE_CRNT_VLINE
	.comm	_RADEON_CRTC2_STATUS,8,3        ## @RADEON_CRTC2_STATUS
	.comm	_DRM_SCANOUTPOS_ACCURATE,4,2    ## @DRM_SCANOUTPOS_ACCURATE
	.comm	_GET_DISTANCE_TO_VBLANKSTART,4,2 ## @GET_DISTANCE_TO_VBLANKSTART
	.comm	_USE_REAL_VBLANKSTART,4,2       ## @USE_REAL_VBLANKSTART
	.comm	_DRM_SCANOUTPOS_IN_VBLANK,4,2   ## @DRM_SCANOUTPOS_IN_VBLANK
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_get_crtc_scanoutpos     ; -- Begin function radeon_get_crtc_scanoutpos
	.p2align	2
_radeon_get_crtc_scanoutpos:            ; @radeon_get_crtc_scanoutpos
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	str	x7, [sp, #8]                    ; 8-byte Folded Spill
	mov	x25, x6
	mov	x24, x4
	mov	x19, x3
	mov	x21, x2
	mov	x22, x1
	ldr	x23, [x0]
	cbz	x5, LBB0_2
; %bb.1:
	mov	x26, x5
	bl	_ktime_get
	str	w0, [x26]
LBB0_2:
	mov	x0, x23
	bl	_ASIC_IS_DCE4
	cbz	x0, LBB0_6
; %bb.3:
	cmp	w22, #5
	b.hi	LBB0_13
; %bb.4:
	mov	w8, w22
Lloh0:
	adrp	x9, lJTI0_0@PAGE
Lloh1:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_5
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_5:
Lloh2:
	adrp	x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGE
Lloh3:
	ldr	x8, [x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGEOFF]
Lloh4:
	ldr	x8, [x8]
Lloh5:
	adrp	x20, _EVERGREEN_CRTC0_REGISTER_OFFSET@GOTPAGE
Lloh6:
	ldr	x20, [x20, _EVERGREEN_CRTC0_REGISTER_OFFSET@GOTPAGEOFF]
	b	LBB0_19
LBB0_6:
	mov	x0, x23
	bl	_ASIC_IS_AVIVO
	cmp	w22, #1
	cbz	x0, LBB0_10
; %bb.7:
	b.eq	LBB0_20
; %bb.8:
	cbnz	w22, LBB0_13
; %bb.9:
Lloh7:
	adrp	x8, _AVIVO_D1CRTC_V_BLANK_START_END@GOTPAGE
Lloh8:
	ldr	x8, [x8, _AVIVO_D1CRTC_V_BLANK_START_END@GOTPAGEOFF]
Lloh9:
	ldr	x0, [x8]
	bl	_RREG32
	mov	x26, x0
Lloh10:
	adrp	x8, _AVIVO_D1CRTC_STATUS_POSITION@GOTPAGE
Lloh11:
	ldr	x8, [x8, _AVIVO_D1CRTC_STATUS_POSITION@GOTPAGEOFF]
	b	LBB0_21
LBB0_10:
	b.eq	LBB0_36
; %bb.11:
	cbnz	w22, LBB0_13
; %bb.12:
Lloh12:
	adrp	x8, _RADEON_CRTC_V_TOTAL_DISP@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RADEON_CRTC_V_TOTAL_DISP@GOTPAGEOFF]
Lloh14:
	ldr	x0, [x8]
	bl	_RREG32
Lloh15:
	adrp	x8, _RADEON_CRTC_V_DISP@GOTPAGE
Lloh16:
	ldr	x8, [x8, _RADEON_CRTC_V_DISP@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
Lloh18:
	adrp	x9, _RADEON_CRTC_V_DISP_SHIFT@GOTPAGE
Lloh19:
	ldr	x9, [x9, _RADEON_CRTC_V_DISP_SHIFT@GOTPAGEOFF]
	and	w8, w8, w0
Lloh20:
	ldr	w9, [x9]
	asr	w26, w8, w9
Lloh21:
	adrp	x8, _RADEON_CRTC_VLINE_CRNT_VLINE@GOTPAGE
Lloh22:
	ldr	x8, [x8, _RADEON_CRTC_VLINE_CRNT_VLINE@GOTPAGEOFF]
Lloh23:
	ldr	x0, [x8]
	bl	_RREG32
Lloh24:
	adrp	x8, _RADEON_CRTC_V_TOTAL@GOTPAGE
Lloh25:
	ldr	x8, [x8, _RADEON_CRTC_V_TOTAL@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	and	w27, w8, w0, asr #16
Lloh27:
	adrp	x8, _RADEON_CRTC_STATUS@GOTPAGE
Lloh28:
	ldr	x8, [x8, _RADEON_CRTC_STATUS@GOTPAGEOFF]
	b	LBB0_37
LBB0_13:
	mov	w26, #0
	mov	w27, #0
	mov	w28, #0
	mov	w20, #1
	cbnz	x25, LBB0_23
	b	LBB0_24
LBB0_14:
Lloh29:
	adrp	x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGE
Lloh30:
	ldr	x8, [x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGEOFF]
Lloh31:
	ldr	x8, [x8]
Lloh32:
	adrp	x20, _EVERGREEN_CRTC1_REGISTER_OFFSET@GOTPAGE
Lloh33:
	ldr	x20, [x20, _EVERGREEN_CRTC1_REGISTER_OFFSET@GOTPAGEOFF]
	b	LBB0_19
LBB0_15:
Lloh34:
	adrp	x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGE
Lloh35:
	ldr	x8, [x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGEOFF]
Lloh36:
	ldr	x8, [x8]
Lloh37:
	adrp	x20, _EVERGREEN_CRTC2_REGISTER_OFFSET@GOTPAGE
Lloh38:
	ldr	x20, [x20, _EVERGREEN_CRTC2_REGISTER_OFFSET@GOTPAGEOFF]
	b	LBB0_19
LBB0_16:
Lloh39:
	adrp	x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGE
Lloh40:
	ldr	x8, [x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGEOFF]
Lloh41:
	ldr	x8, [x8]
Lloh42:
	adrp	x20, _EVERGREEN_CRTC3_REGISTER_OFFSET@GOTPAGE
Lloh43:
	ldr	x20, [x20, _EVERGREEN_CRTC3_REGISTER_OFFSET@GOTPAGEOFF]
	b	LBB0_19
LBB0_17:
Lloh44:
	adrp	x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGE
Lloh45:
	ldr	x8, [x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGEOFF]
Lloh46:
	ldr	x8, [x8]
Lloh47:
	adrp	x20, _EVERGREEN_CRTC4_REGISTER_OFFSET@GOTPAGE
Lloh48:
	ldr	x20, [x20, _EVERGREEN_CRTC4_REGISTER_OFFSET@GOTPAGEOFF]
	b	LBB0_19
LBB0_18:
Lloh49:
	adrp	x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGE
Lloh50:
	ldr	x8, [x8, _EVERGREEN_CRTC_V_BLANK_START_END@GOTPAGEOFF]
Lloh51:
	ldr	x8, [x8]
Lloh52:
	adrp	x20, _EVERGREEN_CRTC5_REGISTER_OFFSET@GOTPAGE
Lloh53:
	ldr	x20, [x20, _EVERGREEN_CRTC5_REGISTER_OFFSET@GOTPAGEOFF]
LBB0_19:
	ldr	x9, [x20]
	add	x0, x9, x8
	bl	_RREG32
	mov	x26, x0
Lloh54:
	adrp	x8, _EVERGREEN_CRTC_STATUS_POSITION@GOTPAGE
Lloh55:
	ldr	x8, [x8, _EVERGREEN_CRTC_STATUS_POSITION@GOTPAGEOFF]
Lloh56:
	ldr	x8, [x8]
	ldr	x9, [x20]
	add	x0, x9, x8
	b	LBB0_22
LBB0_20:
Lloh57:
	adrp	x8, _AVIVO_D2CRTC_V_BLANK_START_END@GOTPAGE
Lloh58:
	ldr	x8, [x8, _AVIVO_D2CRTC_V_BLANK_START_END@GOTPAGEOFF]
Lloh59:
	ldr	x0, [x8]
	bl	_RREG32
	mov	x26, x0
Lloh60:
	adrp	x8, _AVIVO_D2CRTC_STATUS_POSITION@GOTPAGE
Lloh61:
	ldr	x8, [x8, _AVIVO_D2CRTC_STATUS_POSITION@GOTPAGEOFF]
LBB0_21:
	ldr	x0, [x8]
LBB0_22:
	bl	_RREG32
	mov	x27, x0
Lloh62:
	adrp	x8, _DRM_SCANOUTPOS_VALID@GOTPAGE
Lloh63:
	ldr	x8, [x8, _DRM_SCANOUTPOS_VALID@GOTPAGEOFF]
Lloh64:
	ldr	w28, [x8]
	mov	w20, #1
	cbz	x25, LBB0_24
LBB0_23:
	bl	_ktime_get
	str	w0, [x25]
LBB0_24:
	and	w8, w27, #0x1fff
	str	w8, [x19]
	ubfx	w8, w27, #16, #13
	str	w8, [x24]
	cmp	w26, #1
	b.lt	LBB0_26
; %bb.25:
Lloh65:
	adrp	x8, _DRM_SCANOUTPOS_ACCURATE@GOTPAGE
Lloh66:
	ldr	x8, [x8, _DRM_SCANOUTPOS_ACCURATE@GOTPAGEOFF]
Lloh67:
	ldr	w8, [x8]
	orr	w28, w8, w28
	and	w9, w26, #0x1fff
	ubfx	w8, w26, #16, #13
	b	LBB0_27
LBB0_26:
	mov	w8, #0
	ldr	x9, [sp, #8]                    ; 8-byte Folded Reload
	ldr	w9, [x9]
LBB0_27:
Lloh68:
	adrp	x10, _GET_DISTANCE_TO_VBLANKSTART@GOTPAGE
Lloh69:
	ldr	x10, [x10, _GET_DISTANCE_TO_VBLANKSTART@GOTPAGEOFF]
	ldr	w11, [x10]
	tst	w11, w21
	b.eq	LBB0_29
; %bb.28:
	ldr	w11, [x19]
	sub	w11, w11, w9
	str	w11, [x24]
LBB0_29:
Lloh70:
	adrp	x11, _USE_REAL_VBLANKSTART@GOTPAGE
Lloh71:
	ldr	x11, [x11, _USE_REAL_VBLANKSTART@GOTPAGEOFF]
Lloh72:
	ldr	w11, [x11]
	tst	w11, w21
	b.ne	LBB0_31
; %bb.30:
	ldr	x11, [x23]
	ldr	x11, [x11, w22, uxtw #3]
	ldr	w11, [x11]
	sub	w9, w9, w11
LBB0_31:
	ldr	w13, [x19]
	subs	w14, w13, w9
	ccmp	w13, w8, #8, lt
	ccmp	w20, #0, #4, lt
	cset	w11, eq
Lloh73:
	adrp	x12, _DRM_SCANOUTPOS_IN_VBLANK@GOTPAGE
Lloh74:
	ldr	x12, [x12, _DRM_SCANOUTPOS_IN_VBLANK@GOTPAGEOFF]
Lloh75:
	ldr	w12, [x12]
	ldr	w10, [x10]
	tst	w10, w21
	b.ne	LBB0_35
; %bb.32:
	cmp	w13, w9
	cset	w9, lt
	orr	w9, w11, w9
	tbnz	w9, #0, LBB0_34
; %bb.33:
	ldr	x9, [sp, #8]                    ; 8-byte Folded Reload
	ldr	w9, [x9, #4]
	sub	w13, w13, w9
LBB0_34:
	sub	w14, w13, w8
LBB0_35:
	cmp	w11, #0
	csel	w8, wzr, w12, ne
	orr	w0, w8, w28
	str	w14, [x19]
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
LBB0_36:
Lloh76:
	adrp	x8, _RADEON_CRTC2_V_TOTAL_DISP@GOTPAGE
Lloh77:
	ldr	x8, [x8, _RADEON_CRTC2_V_TOTAL_DISP@GOTPAGEOFF]
Lloh78:
	ldr	x0, [x8]
	bl	_RREG32
Lloh79:
	adrp	x8, _RADEON_CRTC_V_DISP@GOTPAGE
Lloh80:
	ldr	x8, [x8, _RADEON_CRTC_V_DISP@GOTPAGEOFF]
Lloh81:
	ldr	w8, [x8]
Lloh82:
	adrp	x9, _RADEON_CRTC_V_DISP_SHIFT@GOTPAGE
Lloh83:
	ldr	x9, [x9, _RADEON_CRTC_V_DISP_SHIFT@GOTPAGEOFF]
	and	w8, w8, w0
Lloh84:
	ldr	w9, [x9]
	asr	w26, w8, w9
Lloh85:
	adrp	x8, _RADEON_CRTC2_VLINE_CRNT_VLINE@GOTPAGE
Lloh86:
	ldr	x8, [x8, _RADEON_CRTC2_VLINE_CRNT_VLINE@GOTPAGEOFF]
Lloh87:
	ldr	x0, [x8]
	bl	_RREG32
Lloh88:
	adrp	x8, _RADEON_CRTC_V_TOTAL@GOTPAGE
Lloh89:
	ldr	x8, [x8, _RADEON_CRTC_V_TOTAL@GOTPAGEOFF]
Lloh90:
	ldr	w8, [x8]
	and	w27, w8, w0, asr #16
Lloh91:
	adrp	x8, _RADEON_CRTC2_STATUS@GOTPAGE
Lloh92:
	ldr	x8, [x8, _RADEON_CRTC2_STATUS@GOTPAGEOFF]
LBB0_37:
	ldr	x0, [x8]
	bl	_RREG32
	and	w20, w0, #0x1
Lloh93:
	adrp	x8, _DRM_SCANOUTPOS_VALID@GOTPAGE
Lloh94:
	ldr	x8, [x8, _DRM_SCANOUTPOS_VALID@GOTPAGEOFF]
Lloh95:
	ldr	w28, [x8]
	cbnz	x25, LBB0_23
	b	LBB0_24
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGot	Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGot	Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_5-LBB0_5)>>2
	.byte	(LBB0_14-LBB0_5)>>2
	.byte	(LBB0_15-LBB0_5)>>2
	.byte	(LBB0_16-LBB0_5)>>2
	.byte	(LBB0_17-LBB0_5)>>2
	.byte	(LBB0_18-LBB0_5)>>2
                                        ; -- End function
	.comm	_EVERGREEN_CRTC_V_BLANK_START_END,8,3 ; @EVERGREEN_CRTC_V_BLANK_START_END
	.comm	_EVERGREEN_CRTC0_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC0_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC_STATUS_POSITION,8,3 ; @EVERGREEN_CRTC_STATUS_POSITION
	.comm	_DRM_SCANOUTPOS_VALID,4,2       ; @DRM_SCANOUTPOS_VALID
	.comm	_EVERGREEN_CRTC1_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC1_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC2_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC2_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC3_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC3_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC4_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC4_REGISTER_OFFSET
	.comm	_EVERGREEN_CRTC5_REGISTER_OFFSET,8,3 ; @EVERGREEN_CRTC5_REGISTER_OFFSET
	.comm	_AVIVO_D1CRTC_V_BLANK_START_END,8,3 ; @AVIVO_D1CRTC_V_BLANK_START_END
	.comm	_AVIVO_D1CRTC_STATUS_POSITION,8,3 ; @AVIVO_D1CRTC_STATUS_POSITION
	.comm	_AVIVO_D2CRTC_V_BLANK_START_END,8,3 ; @AVIVO_D2CRTC_V_BLANK_START_END
	.comm	_AVIVO_D2CRTC_STATUS_POSITION,8,3 ; @AVIVO_D2CRTC_STATUS_POSITION
	.comm	_RADEON_CRTC_V_TOTAL_DISP,8,3   ; @RADEON_CRTC_V_TOTAL_DISP
	.comm	_RADEON_CRTC_V_DISP,4,2         ; @RADEON_CRTC_V_DISP
	.comm	_RADEON_CRTC_V_DISP_SHIFT,4,2   ; @RADEON_CRTC_V_DISP_SHIFT
	.comm	_RADEON_CRTC_VLINE_CRNT_VLINE,8,3 ; @RADEON_CRTC_VLINE_CRNT_VLINE
	.comm	_RADEON_CRTC_V_TOTAL,4,2        ; @RADEON_CRTC_V_TOTAL
	.comm	_RADEON_CRTC_STATUS,8,3         ; @RADEON_CRTC_STATUS
	.comm	_RADEON_CRTC2_V_TOTAL_DISP,8,3  ; @RADEON_CRTC2_V_TOTAL_DISP
	.comm	_RADEON_CRTC2_VLINE_CRNT_VLINE,8,3 ; @RADEON_CRTC2_VLINE_CRNT_VLINE
	.comm	_RADEON_CRTC2_STATUS,8,3        ; @RADEON_CRTC2_STATUS
	.comm	_DRM_SCANOUTPOS_ACCURATE,4,2    ; @DRM_SCANOUTPOS_ACCURATE
	.comm	_GET_DISTANCE_TO_VBLANKSTART,4,2 ; @GET_DISTANCE_TO_VBLANKSTART
	.comm	_USE_REAL_VBLANKSTART,4,2       ; @USE_REAL_VBLANKSTART
	.comm	_DRM_SCANOUTPOS_IN_VBLANK,4,2   ; @DRM_SCANOUTPOS_IN_VBLANK
.subsections_via_symbols
