	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4                               ## -- Begin function vega10_set_default_registry_data
LCPI0_0:
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
LCPI0_1:
	.long	1                               ## 0x1
	.long	6                               ## 0x6
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	4, 0x90
_vega10_set_default_registry_data:      ## @vega10_set_default_registry_data
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	8(%rdi), %rax
	movl	(%rdi), %ecx
	movq	_PP_SCLK_DPM_MASK@GOTPCREL(%rip), %rdx
	movq	_PP_SOCCLK_DPM_MASK@GOTPCREL(%rip), %rsi
	movq	_PP_MCLK_DPM_MASK@GOTPCREL(%rip), %rdi
	movd	(%rdx), %xmm0                   ## xmm0 = mem[0],zero,zero,zero
	pinsrd	$1, (%rsi), %xmm0
	pinsrd	$2, (%rdi), %xmm0
	movq	_PP_PCIE_DPM_MASK@GOTPCREL(%rip), %rdx
	pinsrd	$3, (%rdx), %xmm0
	movd	%ecx, %xmm1
	pshufd	$0, %xmm1, %xmm1                ## xmm1 = xmm1[0,0,0,0]
	pand	%xmm0, %xmm1
	pxor	%xmm0, %xmm0
	pcmpeqd	%xmm0, %xmm1
	psrld	$31, %xmm1
	movdqu	%xmm1, 120(%rax)
	movq	_PP_DCEFCLK_DPM_MASK@GOTPCREL(%rip), %rdx
	xorl	%esi, %esi
	movl	(%rdx), %edx
	andl	%ecx, %edx
	sete	%sil
	movl	%esi, 136(%rax)
	movq	_PP_POWER_CONTAINMENT_MASK@GOTPCREL(%rip), %rsi
	movabsq	$4294967297, %rdx               ## imm = 0x100000001
	testl	%ecx, (%rsi)
	je	LBB0_2
## %bb.1:
	movq	%rdx, 140(%rax)
	movl	$1, 148(%rax)
LBB0_2:
	movq	_PP_CLOCK_STRETCH_MASK@GOTPCREL(%rip), %rsi
	xorl	%edi, %edi
	movl	(%rsi), %esi
	andl	%ecx, %esi
	setne	%dil
	movl	%edi, 152(%rax)
	movq	_PP_ULV_MASK@GOTPCREL(%rip), %rsi
	xorl	%edi, %edi
	movl	(%rsi), %esi
	andl	%ecx, %esi
	setne	%dil
	movl	%edi, 156(%rax)
	movq	_PP_SCLK_DEEP_SLEEP_MASK@GOTPCREL(%rip), %rsi
	xorl	%edi, %edi
	movl	(%rsi), %esi
	andl	%ecx, %esi
	setne	%dil
	movl	%edi, 160(%rax)
	movq	$0, 264(%rax)
	movq	%rdx, 164(%rax)
	movl	$1, 172(%rax)
	movq	_PP_AVFS_MASK@GOTPCREL(%rip), %rdx
	xorl	%esi, %esi
	andl	(%rdx), %ecx
	setne	%sil
	movl	%esi, 176(%rax)
	movaps	LCPI0_0(%rip), %xmm1            ## xmm1 = [1,1,1,1]
	movups	%xmm1, 180(%rax)
	movdqu	%xmm0, 248(%rax)
	movdqu	%xmm0, 232(%rax)
	movaps	LCPI0_1(%rip), %xmm1            ## xmm1 = [1,6,1,1]
	movups	%xmm1, 196(%rax)
	movdqu	%xmm0, 216(%rax)
	movq	_PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, 112(%rax)
	movq	_PPREGKEY_VEGA10QUADRATICEQUATION_DFLT@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, 104(%rax)
	movq	%rcx, 96(%rax)
	movq	%rcx, 88(%rax)
	movq	%rcx, 80(%rax)
	movq	%rcx, 72(%rax)
	movq	%rcx, 64(%rax)
	movq	%rcx, 56(%rax)
	movq	%rcx, 48(%rax)
	movq	%rcx, 40(%rax)
	movq	%rcx, 32(%rax)
	movq	%rcx, 24(%rax)
	movq	%rcx, 16(%rax)
	movq	_PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, 12(%rax)
	movq	_PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, 8(%rax)
	movq	_PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, 4(%rax)
	movq	_PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, (%rax)
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PP_SCLK_DPM_MASK,4,2           ## @PP_SCLK_DPM_MASK
	.comm	_PP_SOCCLK_DPM_MASK,4,2         ## @PP_SOCCLK_DPM_MASK
	.comm	_PP_MCLK_DPM_MASK,4,2           ## @PP_MCLK_DPM_MASK
	.comm	_PP_PCIE_DPM_MASK,4,2           ## @PP_PCIE_DPM_MASK
	.comm	_PP_DCEFCLK_DPM_MASK,4,2        ## @PP_DCEFCLK_DPM_MASK
	.comm	_PP_POWER_CONTAINMENT_MASK,4,2  ## @PP_POWER_CONTAINMENT_MASK
	.comm	_PP_CLOCK_STRETCH_MASK,4,2      ## @PP_CLOCK_STRETCH_MASK
	.comm	_PP_ULV_MASK,4,2                ## @PP_ULV_MASK
	.comm	_PP_SCLK_DEEP_SLEEP_MASK,4,2    ## @PP_SCLK_DEEP_SLEEP_MASK
	.comm	_PP_AVFS_MASK,4,2               ## @PP_AVFS_MASK
	.comm	_PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT,4,2 ## @PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT
	.comm	_PPREGKEY_VEGA10QUADRATICEQUATION_DFLT,8,3 ## @PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
	.comm	_PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT,4,2 ## @PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT
	.comm	_PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT,4,2 ## @PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT
	.comm	_PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT,4,2 ## @PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT
	.comm	_PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT,4,2 ## @PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT
	.no_dead_strip	_vega10_set_default_registry_data
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4                               ; -- Begin function vega10_set_default_registry_data
lCPI0_0:
	.long	1                               ; 0x1
	.long	6                               ; 0x6
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	2
_vega10_set_default_registry_data:      ; @vega10_set_default_registry_data
	.cfi_startproc
; %bb.0:
Lloh0:
	adrp	x9, _PP_SCLK_DPM_MASK@GOTPAGE
Lloh1:
	ldr	x9, [x9, _PP_SCLK_DPM_MASK@GOTPAGEOFF]
Lloh2:
	adrp	x10, _PP_SOCCLK_DPM_MASK@GOTPAGE
Lloh3:
	ldr	x10, [x10, _PP_SOCCLK_DPM_MASK@GOTPAGEOFF]
	ldr	x8, [x0, #8]
Lloh4:
	adrp	x11, _PP_MCLK_DPM_MASK@GOTPAGE
Lloh5:
	ldr	x11, [x11, _PP_MCLK_DPM_MASK@GOTPAGEOFF]
Lloh6:
	adrp	x12, _PP_PCIE_DPM_MASK@GOTPAGE
Lloh7:
	ldr	x12, [x12, _PP_PCIE_DPM_MASK@GOTPAGEOFF]
Lloh8:
	ldr	s0, [x9]
	ld1.s	{ v0 }[1], [x10]
	ld1.s	{ v0 }[2], [x11]
	ld1.s	{ v0 }[3], [x12]
	ldr	w9, [x0]
	dup.4s	v1, w9
	and.16b	v0, v0, v1
	cmeq.4s	v1, v0, #0
	movi.4s	v0, #1
	and.16b	v1, v1, v0
	stur	q1, [x8, #120]
Lloh9:
	adrp	x10, _PP_DCEFCLK_DPM_MASK@GOTPAGE
Lloh10:
	ldr	x10, [x10, _PP_DCEFCLK_DPM_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w10, [x10]
	tst	w10, w9
	cset	w10, eq
	str	w10, [x8, #136]
Lloh12:
	adrp	x10, _PP_POWER_CONTAINMENT_MASK@GOTPAGE
Lloh13:
	ldr	x10, [x10, _PP_POWER_CONTAINMENT_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w10, [x10]
	tst	w10, w9
	b.eq	LBB0_2
; %bb.1:
	movi.2s	v1, #1
	stur	d1, [x8, #140]
	mov	w10, #1
	str	w10, [x8, #148]
LBB0_2:
Lloh15:
	adrp	x10, _PP_CLOCK_STRETCH_MASK@GOTPAGE
Lloh16:
	ldr	x10, [x10, _PP_CLOCK_STRETCH_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w10, [x10]
	tst	w10, w9
	cset	w10, ne
Lloh18:
	adrp	x11, _PP_ULV_MASK@GOTPAGE
Lloh19:
	ldr	x11, [x11, _PP_ULV_MASK@GOTPAGEOFF]
Lloh20:
	ldr	w11, [x11]
	tst	w11, w9
	cset	w11, ne
Lloh21:
	adrp	x12, _PP_SCLK_DEEP_SLEEP_MASK@GOTPAGE
Lloh22:
	ldr	x12, [x12, _PP_SCLK_DEEP_SLEEP_MASK@GOTPAGEOFF]
	stp	w10, w11, [x8, #152]
Lloh23:
	ldr	w10, [x12]
	tst	w10, w9
	cset	w10, ne
	str	w10, [x8, #160]
	str	xzr, [x8, #264]
	movi.2s	v1, #1
	stur	d1, [x8, #164]
Lloh24:
	adrp	x10, _PP_AVFS_MASK@GOTPAGE
Lloh25:
	ldr	x10, [x10, _PP_AVFS_MASK@GOTPAGEOFF]
Lloh26:
	ldr	w10, [x10]
	tst	w10, w9
	mov	w9, #1
	cset	w10, ne
	stp	w9, w10, [x8, #172]
	stur	q0, [x8, #180]
	movi.2d	v0, #0000000000000000
	stur	q0, [x8, #232]
	stur	q0, [x8, #248]
Lloh27:
	adrp	x9, lCPI0_0@PAGE
Lloh28:
	ldr	q0, [x9, lCPI0_0@PAGEOFF]
	stur	q0, [x8, #196]
	stp	xzr, xzr, [x8, #216]
Lloh29:
	adrp	x9, _PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT@GOTPAGE
Lloh30:
	ldr	x9, [x9, _PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT@GOTPAGEOFF]
Lloh31:
	ldr	w9, [x9]
Lloh32:
	adrp	x10, _PPREGKEY_VEGA10QUADRATICEQUATION_DFLT@GOTPAGE
Lloh33:
	ldr	x10, [x10, _PPREGKEY_VEGA10QUADRATICEQUATION_DFLT@GOTPAGEOFF]
	str	w9, [x8, #112]
Lloh34:
	ldr	x9, [x10]
	stp	x9, x9, [x8, #96]
	stp	x9, x9, [x8, #80]
	stp	x9, x9, [x8, #64]
	stp	x9, x9, [x8, #48]
	stp	x9, x9, [x8, #32]
	stp	x9, x9, [x8, #16]
Lloh35:
	adrp	x9, _PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT@GOTPAGE
Lloh36:
	ldr	x9, [x9, _PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT@GOTPAGEOFF]
Lloh37:
	adrp	x10, _PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT@GOTPAGE
Lloh38:
	ldr	x10, [x10, _PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT@GOTPAGEOFF]
Lloh39:
	ldr	w9, [x9]
Lloh40:
	ldr	w10, [x10]
	stp	w10, w9, [x8, #8]
Lloh41:
	adrp	x9, _PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT@GOTPAGE
Lloh42:
	ldr	x9, [x9, _PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
Lloh44:
	adrp	x10, _PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT@GOTPAGE
Lloh45:
	ldr	x10, [x10, _PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT@GOTPAGEOFF]
Lloh46:
	ldr	w10, [x10]
	stp	w10, w9, [x8]
	ret
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh8
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh39
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpAdrp	Lloh27, Lloh29
	.loh AdrpLdr	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.cfi_endproc
                                        ; -- End function
	.comm	_PP_SCLK_DPM_MASK,4,2           ; @PP_SCLK_DPM_MASK
	.comm	_PP_SOCCLK_DPM_MASK,4,2         ; @PP_SOCCLK_DPM_MASK
	.comm	_PP_MCLK_DPM_MASK,4,2           ; @PP_MCLK_DPM_MASK
	.comm	_PP_PCIE_DPM_MASK,4,2           ; @PP_PCIE_DPM_MASK
	.comm	_PP_DCEFCLK_DPM_MASK,4,2        ; @PP_DCEFCLK_DPM_MASK
	.comm	_PP_POWER_CONTAINMENT_MASK,4,2  ; @PP_POWER_CONTAINMENT_MASK
	.comm	_PP_CLOCK_STRETCH_MASK,4,2      ; @PP_CLOCK_STRETCH_MASK
	.comm	_PP_ULV_MASK,4,2                ; @PP_ULV_MASK
	.comm	_PP_SCLK_DEEP_SLEEP_MASK,4,2    ; @PP_SCLK_DEEP_SLEEP_MASK
	.comm	_PP_AVFS_MASK,4,2               ; @PP_AVFS_MASK
	.comm	_PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT,4,2 ; @PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT
	.comm	_PPREGKEY_VEGA10QUADRATICEQUATION_DFLT,8,3 ; @PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
	.comm	_PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT,4,2 ; @PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT
	.comm	_PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT,4,2 ; @PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT
	.comm	_PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT,4,2 ; @PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT
	.comm	_PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT,4,2 ; @PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT
	.no_dead_strip	_vega10_set_default_registry_data
.subsections_via_symbols
