	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_optc1_lock                     ## -- Begin function optc1_lock
	.p2align	4, 0x90
_optc1_lock:                            ## @optc1_lock
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	callq	_DCN10TG_FROM_TG
	movq	_OTG_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_REG_READ
	testb	$1, %al
	je	LBB0_2
## %bb.1:
	movq	_OTG_GLOBAL_CONTROL0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_OTG_MASTER_UPDATE_LOCK_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%rbx), %ecx
	xorl	%esi, %esi
	callq	_REG_SET
	movq	_OTG_MASTER_UPDATE_LOCK@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	xorl	%esi, %esi
	movl	%edi, %edx
	movl	$1, %ecx
	callq	_REG_SET
	movq	8(%rbx), %rax
	movq	(%rax), %rax
	movq	_DCE_ENV_FPGA_MAXIMUS@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_3
LBB0_2:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
LBB0_3:
	movl	(%r14), %edi
	movq	_UPDATE_LOCK_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %edx
	movl	$1, %ecx
	movl	$10, %r8d
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_REG_WAIT                       ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_OTG_CONTROL,4,2                ## @OTG_CONTROL
	.comm	_OTG_GLOBAL_CONTROL0,4,2        ## @OTG_GLOBAL_CONTROL0
	.comm	_OTG_MASTER_UPDATE_LOCK_SEL,4,2 ## @OTG_MASTER_UPDATE_LOCK_SEL
	.comm	_OTG_MASTER_UPDATE_LOCK,4,2     ## @OTG_MASTER_UPDATE_LOCK
	.comm	_DCE_ENV_FPGA_MAXIMUS,8,3       ## @DCE_ENV_FPGA_MAXIMUS
	.comm	_UPDATE_LOCK_STATUS,4,2         ## @UPDATE_LOCK_STATUS
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_optc1_lock                     ; -- Begin function optc1_lock
	.p2align	2
_optc1_lock:                            ; @optc1_lock
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_DCN10TG_FROM_TG
Lloh0:
	adrp	x8, _OTG_CONTROL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _OTG_CONTROL@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_REG_READ
	tbz	w0, #0, LBB0_2
; %bb.1:
Lloh3:
	adrp	x8, _OTG_GLOBAL_CONTROL0@GOTPAGE
Lloh4:
	ldr	x8, [x8, _OTG_GLOBAL_CONTROL0@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
Lloh6:
	adrp	x8, _OTG_MASTER_UPDATE_LOCK_SEL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _OTG_MASTER_UPDATE_LOCK_SEL@GOTPAGEOFF]
Lloh8:
	ldr	w2, [x8]
	ldr	w3, [x19]
	mov	w1, #0
	bl	_REG_SET
Lloh9:
	adrp	x20, _OTG_MASTER_UPDATE_LOCK@GOTPAGE
Lloh10:
	ldr	x20, [x20, _OTG_MASTER_UPDATE_LOCK@GOTPAGEOFF]
	ldr	w0, [x20]
	mov	w1, #0
	mov	x2, x0
	mov	w3, #1
	bl	_REG_SET
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
Lloh11:
	adrp	x9, _DCE_ENV_FPGA_MAXIMUS@GOTPAGE
Lloh12:
	ldr	x9, [x9, _DCE_ENV_FPGA_MAXIMUS@GOTPAGEOFF]
Lloh13:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_3
LBB0_2:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_3:
	ldr	w0, [x20]
Lloh14:
	adrp	x8, _UPDATE_LOCK_STATUS@GOTPAGE
Lloh15:
	ldr	x8, [x8, _UPDATE_LOCK_STATUS@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
	mov	w2, #1
	mov	w3, #1
	mov	w4, #10
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_REG_WAIT
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.cfi_endproc
                                        ; -- End function
	.comm	_OTG_CONTROL,4,2                ; @OTG_CONTROL
	.comm	_OTG_GLOBAL_CONTROL0,4,2        ; @OTG_GLOBAL_CONTROL0
	.comm	_OTG_MASTER_UPDATE_LOCK_SEL,4,2 ; @OTG_MASTER_UPDATE_LOCK_SEL
	.comm	_OTG_MASTER_UPDATE_LOCK,4,2     ; @OTG_MASTER_UPDATE_LOCK
	.comm	_DCE_ENV_FPGA_MAXIMUS,8,3       ; @DCE_ENV_FPGA_MAXIMUS
	.comm	_UPDATE_LOCK_STATUS,4,2         ; @UPDATE_LOCK_STATUS
.subsections_via_symbols
