	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function intel_enable_rps
_intel_enable_rps:                      ## @intel_enable_rps
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	addq	$40, %rdi
	callq	_lockdep_assert_held
	cmpl	$0, (%rbx)
	jne	LBB0_14
## %bb.1:
	movq	%rbx, %rdi
	callq	_IS_CHERRYVIEW
	movq	%rbx, %rdi
	testq	%rax, %rax
	je	LBB0_3
## %bb.2:
	callq	_cherryview_enable_rps
	jmp	LBB0_13
LBB0_3:
	callq	_IS_VALLEYVIEW
	movq	%rbx, %rdi
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	callq	_valleyview_enable_rps
	jmp	LBB0_13
LBB0_5:
	callq	_INTEL_GEN
	movq	%rbx, %rdi
	cmpl	$9, %eax
	jl	LBB0_7
## %bb.6:
	callq	_gen9_enable_rps
	jmp	LBB0_13
LBB0_7:
	callq	_IS_BROADWELL
	movq	%rbx, %rdi
	testq	%rax, %rax
	je	LBB0_9
## %bb.8:
	callq	_gen8_enable_rps
	jmp	LBB0_13
LBB0_9:
	callq	_INTEL_GEN
	movq	%rbx, %rdi
	cmpl	$6, %eax
	jl	LBB0_11
## %bb.10:
	callq	_gen6_enable_rps
	jmp	LBB0_13
LBB0_11:
	callq	_IS_IRONLAKE_M
	testq	%rax, %rax
	je	LBB0_13
## %bb.12:
	movq	%rbx, %rdi
	callq	_ironlake_enable_drps
	movq	%rbx, %rdi
	callq	_intel_init_emon
LBB0_13:
	movq	8(%rbx), %rax
	xorl	%edi, %edi
	cmpq	16(%rbx), %rax
	setl	%dil
	callq	_WARN_ON
	movq	24(%rbx), %rax
	xorl	%edi, %edi
	cmpq	8(%rbx), %rax
	setg	%dil
	callq	_WARN_ON
	movq	32(%rbx), %rax
	xorl	%edi, %edi
	cmpq	16(%rbx), %rax
	setl	%dil
	callq	_WARN_ON
	movq	32(%rbx), %rax
	xorl	%edi, %edi
	cmpq	8(%rbx), %rax
	setg	%dil
	callq	_WARN_ON
	movl	$1, (%rbx)
LBB0_14:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.no_dead_strip	_intel_enable_rps
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function intel_enable_rps
_intel_enable_rps:                      ; @intel_enable_rps
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	add	x0, x0, #40
	bl	_lockdep_assert_held
	ldr	w8, [x19]
	cbnz	w8, LBB0_14
; %bb.1:
	mov	x0, x19
	bl	_IS_CHERRYVIEW
	cbz	x0, LBB0_3
; %bb.2:
	mov	x0, x19
	bl	_cherryview_enable_rps
	b	LBB0_13
LBB0_3:
	mov	x0, x19
	bl	_IS_VALLEYVIEW
	cbz	x0, LBB0_5
; %bb.4:
	mov	x0, x19
	bl	_valleyview_enable_rps
	b	LBB0_13
LBB0_5:
	mov	x0, x19
	bl	_INTEL_GEN
	cmp	w0, #9
	b.lt	LBB0_7
; %bb.6:
	mov	x0, x19
	bl	_gen9_enable_rps
	b	LBB0_13
LBB0_7:
	mov	x0, x19
	bl	_IS_BROADWELL
	cbz	x0, LBB0_9
; %bb.8:
	mov	x0, x19
	bl	_gen8_enable_rps
	b	LBB0_13
LBB0_9:
	mov	x0, x19
	bl	_INTEL_GEN
	cmp	w0, #6
	b.lt	LBB0_11
; %bb.10:
	mov	x0, x19
	bl	_gen6_enable_rps
	b	LBB0_13
LBB0_11:
	mov	x0, x19
	bl	_IS_IRONLAKE_M
	cbz	x0, LBB0_13
; %bb.12:
	mov	x0, x19
	bl	_ironlake_enable_drps
	mov	x0, x19
	bl	_intel_init_emon
LBB0_13:
	ldp	x8, x9, [x19, #8]
	cmp	x8, x9
	cset	w0, lt
	bl	_WARN_ON
	ldr	x8, [x19, #24]
	ldr	x9, [x19, #8]
	cmp	x8, x9
	cset	w0, gt
	bl	_WARN_ON
	ldr	x8, [x19, #32]
	ldr	x9, [x19, #16]
	cmp	x8, x9
	cset	w0, lt
	bl	_WARN_ON
	ldr	x8, [x19, #32]
	ldr	x9, [x19, #8]
	cmp	x8, x9
	cset	w0, gt
	bl	_WARN_ON
	mov	w8, #1
	str	w8, [x19]
LBB0_14:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.cfi_endproc
                                        ; -- End function
	.no_dead_strip	_intel_enable_rps
.subsections_via_symbols
