	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v10_0_update_medium_grain_clock_gating
_gfx_v10_0_update_medium_grain_clock_gating: ## @gfx_v10_0_update_medium_grain_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	testl	%esi, %esi
	je	LBB0_11
## %bb.1:
	movq	%rdi, %rbx
	movq	_AMD_CG_SUPPORT_GFX_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rdi)
	je	LBB0_11
## %bb.2:
	movq	_GC@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movq	_mmRLC_CGTT_MGCG_OVERRIDE@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK@GOTPCREL(%rip), %rdx
	movq	_RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rdx), %ecx
	movq	_RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movq	_RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	cmpl	%ecx, %eax
	je	LBB0_4
## %bb.3:
	movl	(%r14), %edi
	movl	(%r15), %edx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
LBB0_4:
	movl	(%rbx), %eax
	movq	_AMD_CG_SUPPORT_GFX_MGLS@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_10
## %bb.5:
	movq	_AMD_CG_SUPPORT_GFX_RLC_LS@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_8
## %bb.6:
	movl	(%r14), %edi
	movq	_mmRLC_MEM_SLP_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	%eax, %ecx
	cmpl	%ecx, %eax
	je	LBB0_8
## %bb.7:
	movl	(%r14), %edi
	movl	(%r15), %edx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
LBB0_8:
	movq	_AMD_CG_SUPPORT_GFX_CP_LS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rbx)
	je	LBB0_10
## %bb.9:
	movl	(%r14), %edi
	movq	_mmCP_MEM_SLP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	%eax, %ecx
	movq	_CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%ecx, %eax
	cmpl	%eax, %ecx
	jne	LBB0_17
	jmp	LBB0_10
LBB0_11:
	movq	_GC@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	movq	_mmRLC_CGTT_MGCG_OVERRIDE@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK@GOTPCREL(%rip), %rcx
	movq	_RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK@GOTPCREL(%rip), %rdx
	movq	_RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK@GOTPCREL(%rip), %rsi
	movl	(%rcx), %ecx
	orl	%eax, %ecx
	orl	(%rdx), %ecx
	orl	(%rsi), %ecx
	movq	_RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	cmpl	%ecx, %eax
	je	LBB0_13
## %bb.12:
	movl	(%r15), %edi
	movl	(%r14), %edx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
LBB0_13:
	movl	(%r15), %edi
	movq	_mmRLC_MEM_SLP_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%eax, %ecx
	je	LBB0_15
## %bb.14:
	notl	%ecx
	andl	%ecx, %eax
	movl	(%r15), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
LBB0_15:
	movl	(%r15), %edi
	movq	_mmCP_MEM_SLP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%eax, %ecx
	je	LBB0_10
## %bb.16:
	notl	%ecx
	andl	%ecx, %eax
LBB0_17:
	movq	_GC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movq	_mmCP_MEM_SLP_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_SOC15                   ## TAILCALL
LBB0_10:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_CG_SUPPORT_GFX_MGCG,4,2    ## @AMD_CG_SUPPORT_GFX_MGCG
	.comm	_GC,4,2                         ## @GC
	.comm	_mmRLC_CGTT_MGCG_OVERRIDE,4,2   ## @mmRLC_CGTT_MGCG_OVERRIDE
	.comm	_RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK,4,2 ## @RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK
	.comm	_RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK,4,2 ## @RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK
	.comm	_RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK,4,2 ## @RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK
	.comm	_RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK,4,2 ## @RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK
	.comm	_AMD_CG_SUPPORT_GFX_MGLS,4,2    ## @AMD_CG_SUPPORT_GFX_MGLS
	.comm	_AMD_CG_SUPPORT_GFX_RLC_LS,4,2  ## @AMD_CG_SUPPORT_GFX_RLC_LS
	.comm	_mmRLC_MEM_SLP_CNTL,4,2         ## @mmRLC_MEM_SLP_CNTL
	.comm	_RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK,4,2 ## @RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK
	.comm	_AMD_CG_SUPPORT_GFX_CP_LS,4,2   ## @AMD_CG_SUPPORT_GFX_CP_LS
	.comm	_mmCP_MEM_SLP_CNTL,4,2          ## @mmCP_MEM_SLP_CNTL
	.comm	_CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK,4,2 ## @CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK
	.no_dead_strip	_gfx_v10_0_update_medium_grain_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v10_0_update_medium_grain_clock_gating
_gfx_v10_0_update_medium_grain_clock_gating: ; @gfx_v10_0_update_medium_grain_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	cbz	w1, LBB0_10
; %bb.1:
	mov	x19, x0
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _AMD_CG_SUPPORT_GFX_MGCG@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_CG_SUPPORT_GFX_MGCG@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_10
; %bb.2:
Lloh3:
	adrp	x20, _GC@GOTPAGE
Lloh4:
	ldr	x20, [x20, _GC@GOTPAGEOFF]
	ldr	w0, [x20]
Lloh5:
	adrp	x21, _mmRLC_CGTT_MGCG_OVERRIDE@GOTPAGE
Lloh6:
	ldr	x21, [x21, _mmRLC_CGTT_MGCG_OVERRIDE@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh7:
	adrp	x8, _RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK@GOTPAGE
Lloh8:
	ldr	x8, [x8, _RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
Lloh10:
	adrp	x9, _RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK@GOTPAGE
Lloh11:
	ldr	x9, [x9, _RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh13:
	adrp	x9, _RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK@GOTPAGE
Lloh14:
	ldr	x9, [x9, _RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w8, w0, w8
Lloh16:
	adrp	x9, _RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK@GOTPAGE
Lloh17:
	ldr	x9, [x9, _RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	orr	w3, w8, w9
	cmp	w0, w3
	b.eq	LBB0_4
; %bb.3:
	ldr	w0, [x20]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_WREG32_SOC15
LBB0_4:
	ldr	w8, [x19]
Lloh19:
	adrp	x9, _AMD_CG_SUPPORT_GFX_MGLS@GOTPAGE
Lloh20:
	ldr	x9, [x9, _AMD_CG_SUPPORT_GFX_MGLS@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_17
; %bb.5:
Lloh22:
	adrp	x9, _AMD_CG_SUPPORT_GFX_RLC_LS@GOTPAGE
Lloh23:
	ldr	x9, [x9, _AMD_CG_SUPPORT_GFX_RLC_LS@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_8
; %bb.6:
	ldr	w0, [x20]
Lloh25:
	adrp	x21, _mmRLC_MEM_SLP_CNTL@GOTPAGE
Lloh26:
	ldr	x21, [x21, _mmRLC_MEM_SLP_CNTL@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh27:
	adrp	x8, _RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK@GOTPAGE
Lloh28:
	ldr	x8, [x8, _RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	orr	w3, w8, w0
	cmp	w0, w3
	b.eq	LBB0_8
; %bb.7:
	ldr	w0, [x20]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_WREG32_SOC15
LBB0_8:
	ldr	w8, [x19]
Lloh30:
	adrp	x9, _AMD_CG_SUPPORT_GFX_CP_LS@GOTPAGE
Lloh31:
	ldr	x9, [x9, _AMD_CG_SUPPORT_GFX_CP_LS@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_17
; %bb.9:
	ldr	w0, [x20]
Lloh33:
	adrp	x8, _mmCP_MEM_SLP_CNTL@GOTPAGE
Lloh34:
	ldr	x8, [x8, _mmCP_MEM_SLP_CNTL@GOTPAGEOFF]
Lloh35:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh36:
	adrp	x8, _CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPAGE
Lloh37:
	ldr	x8, [x8, _CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh38:
	ldr	w8, [x8]
	orr	w3, w8, w0
	cmp	w0, w3
	b.ne	LBB0_16
	b	LBB0_17
LBB0_10:
Lloh39:
	adrp	x19, _GC@GOTPAGE
Lloh40:
	ldr	x19, [x19, _GC@GOTPAGEOFF]
	ldr	w0, [x19]
Lloh41:
	adrp	x20, _mmRLC_CGTT_MGCG_OVERRIDE@GOTPAGE
Lloh42:
	ldr	x20, [x20, _mmRLC_CGTT_MGCG_OVERRIDE@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh43:
	adrp	x8, _RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK@GOTPAGE
Lloh44:
	ldr	x8, [x8, _RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK@GOTPAGEOFF]
Lloh45:
	ldr	w8, [x8]
Lloh46:
	adrp	x9, _RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK@GOTPAGE
Lloh47:
	ldr	x9, [x9, _RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK@GOTPAGEOFF]
Lloh48:
	ldr	w9, [x9]
Lloh49:
	adrp	x10, _RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK@GOTPAGE
Lloh50:
	ldr	x10, [x10, _RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK@GOTPAGEOFF]
Lloh51:
	ldr	w10, [x10]
Lloh52:
	adrp	x11, _RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK@GOTPAGE
Lloh53:
	ldr	x11, [x11, _RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK@GOTPAGEOFF]
Lloh54:
	ldr	w11, [x11]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w3, w8, w11
	cmp	w0, w3
	b.eq	LBB0_12
; %bb.11:
	ldr	w0, [x19]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_WREG32_SOC15
LBB0_12:
	ldr	w0, [x19]
Lloh55:
	adrp	x20, _mmRLC_MEM_SLP_CNTL@GOTPAGE
Lloh56:
	ldr	x20, [x20, _mmRLC_MEM_SLP_CNTL@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh57:
	adrp	x8, _RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK@GOTPAGE
Lloh58:
	ldr	x8, [x8, _RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh59:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_14
; %bb.13:
	bic	w3, w0, w8
	ldr	w0, [x19]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_WREG32_SOC15
LBB0_14:
	ldr	w0, [x19]
Lloh60:
	adrp	x8, _mmCP_MEM_SLP_CNTL@GOTPAGE
Lloh61:
	ldr	x8, [x8, _mmCP_MEM_SLP_CNTL@GOTPAGEOFF]
Lloh62:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh63:
	adrp	x8, _CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPAGE
Lloh64:
	ldr	x8, [x8, _CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh65:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_17
; %bb.15:
	bic	w3, w0, w8
LBB0_16:
Lloh66:
	adrp	x8, _GC@GOTPAGE
Lloh67:
	ldr	x8, [x8, _GC@GOTPAGEOFF]
Lloh68:
	adrp	x9, _mmCP_MEM_SLP_CNTL@GOTPAGE
Lloh69:
	ldr	x9, [x9, _mmCP_MEM_SLP_CNTL@GOTPAGEOFF]
Lloh70:
	ldr	w0, [x8]
Lloh71:
	ldr	w2, [x9]
	mov	w1, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32_SOC15
LBB0_17:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh70
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_CG_SUPPORT_GFX_MGCG,4,2    ; @AMD_CG_SUPPORT_GFX_MGCG
	.comm	_GC,4,2                         ; @GC
	.comm	_mmRLC_CGTT_MGCG_OVERRIDE,4,2   ; @mmRLC_CGTT_MGCG_OVERRIDE
	.comm	_RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK,4,2 ; @RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK
	.comm	_RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK,4,2 ; @RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK
	.comm	_RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK,4,2 ; @RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK
	.comm	_RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK,4,2 ; @RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK
	.comm	_AMD_CG_SUPPORT_GFX_MGLS,4,2    ; @AMD_CG_SUPPORT_GFX_MGLS
	.comm	_AMD_CG_SUPPORT_GFX_RLC_LS,4,2  ; @AMD_CG_SUPPORT_GFX_RLC_LS
	.comm	_mmRLC_MEM_SLP_CNTL,4,2         ; @mmRLC_MEM_SLP_CNTL
	.comm	_RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK,4,2 ; @RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK
	.comm	_AMD_CG_SUPPORT_GFX_CP_LS,4,2   ; @AMD_CG_SUPPORT_GFX_CP_LS
	.comm	_mmCP_MEM_SLP_CNTL,4,2          ; @mmCP_MEM_SLP_CNTL
	.comm	_CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK,4,2 ; @CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK
	.no_dead_strip	_gfx_v10_0_update_medium_grain_clock_gating
.subsections_via_symbols
