	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function cik_program_aspm
_cik_program_aspm:                      ## @cik_program_aspm
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_radeon_aspm@GOTPCREL(%rip), %rax
	cmpq	$0, (%rax)
	je	LBB0_42
## %bb.1:
	movq	%rdi, %r14
	movl	(%rdi), %eax
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_2
LBB0_42:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	movq	_RADEON_IS_PCIE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_42
## %bb.3:
	movq	_PCIE_LC_N_FTS_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_RREG32_PCIE_PORT
	movl	%eax, %r15d
	movq	_LC_XMIT_N_FTS_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	notl	%ebx
	andl	%r15d, %ebx
	movl	$36, %edi
	callq	_LC_XMIT_N_FTS
	movq	_LC_XMIT_N_FTS_OVERRIDE_EN@GOTPCREL(%rip), %rcx
	orl	%ebx, %eax
	orl	(%rcx), %eax
	cmpl	%eax, %r15d
	je	LBB0_5
## %bb.4:
	movl	(%r12), %edi
	movl	%eax, %esi
	callq	_WREG32_PCIE_PORT
LBB0_5:
	movq	_PCIE_LC_CNTL3@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_GO_TO_RECOVERY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	%eax, %esi
	cmpl	%esi, %eax
	je	LBB0_7
## %bb.6:
	movl	(%rbx), %edi
	callq	_WREG32_PCIE_PORT
LBB0_7:
	movq	_PCIE_P_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE_PORT
	movq	_P_IGNORE_EDB_ERR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	%eax, %esi
	cmpl	%esi, %eax
	je	LBB0_9
## %bb.8:
	movl	(%rbx), %edi
	callq	_WREG32_PCIE_PORT
LBB0_9:
	movq	_PCIE_LC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PCIE_PORT
	movl	%eax, %r15d
	movq	_LC_L0S_INACTIVITY_MASK@GOTPCREL(%rip), %rcx
	movq	_LC_L1_INACTIVITY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	orl	(%rcx), %ebx
	notl	%ebx
	andl	%r15d, %ebx
	movq	_LC_PMI_TO_L1_DIS@GOTPCREL(%rip), %r13
	orl	(%r13), %ebx
	movl	$7, %edi
	callq	_LC_L0S_INACTIVITY
	movl	%eax, %r12d
	movl	$7, %edi
	callq	_LC_L1_INACTIVITY
	orl	%r12d, %eax
	orl	%ebx, %eax
	movl	(%r13), %esi
	notl	%esi
	andl	%eax, %esi
	cmpl	%esi, %r15d
	je	LBB0_11
## %bb.10:
	movq	_PCIE_LC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32_PCIE_PORT
LBB0_11:
	movq	_PB0_PIF_PWRDOWN_0@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_RREG32_PCIE_PORT
	movl	%eax, %r15d
	movq	_PLL_POWER_STATE_IN_OFF_0_MASK@GOTPCREL(%rip), %rax
	movq	_PLL_POWER_STATE_IN_TXS2_0_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	notl	%ebx
	andl	%r15d, %ebx
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_OFF_0
	movl	%eax, %r13d
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_TXS2_0
	orl	%r13d, %eax
	orl	%ebx, %eax
	cmpl	%eax, %r15d
	je	LBB0_13
## %bb.12:
	movl	(%r12), %edi
	movl	%eax, %esi
	callq	_WREG32_PCIE_PORT
LBB0_13:
	movq	_PB0_PIF_PWRDOWN_1@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_RREG32_PCIE_PORT
	movl	%eax, %r15d
	movq	_PLL_POWER_STATE_IN_OFF_1_MASK@GOTPCREL(%rip), %rax
	movq	_PLL_POWER_STATE_IN_TXS2_1_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r12d
	orl	(%rax), %r12d
	notl	%r12d
	andl	%r15d, %r12d
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_OFF_1
	movl	%eax, %ebx
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_TXS2_1
	orl	%ebx, %eax
	orl	%r12d, %eax
	cmpl	%eax, %r15d
	je	LBB0_15
## %bb.14:
	movl	(%r13), %edi
	movl	%eax, %esi
	callq	_WREG32_PCIE_PORT
LBB0_15:
	movq	_PB1_PIF_PWRDOWN_0@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_RREG32_PCIE_PORT
	movl	%eax, %r12d
	movq	_PLL_POWER_STATE_IN_TXS2_0_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_PLL_POWER_STATE_IN_OFF_0_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	notl	%ebx
	andl	%r12d, %ebx
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_OFF_0
	movl	%eax, %r15d
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_TXS2_0
	orl	%r15d, %eax
	orl	%ebx, %eax
	cmpl	%eax, %r12d
	je	LBB0_17
## %bb.16:
	movl	(%r13), %edi
	movl	%eax, %esi
	callq	_WREG32_PCIE_PORT
LBB0_17:
	movq	_PB1_PIF_PWRDOWN_1@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_RREG32_PCIE_PORT
	movl	%eax, %r12d
	movq	_PLL_POWER_STATE_IN_TXS2_1_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_PLL_POWER_STATE_IN_OFF_1_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	notl	%ebx
	andl	%r12d, %ebx
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_OFF_1
	movl	%eax, %r15d
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_TXS2_1
	orl	%r15d, %eax
	orl	%ebx, %eax
	cmpl	%eax, %r12d
	je	LBB0_19
## %bb.18:
	movl	(%r13), %edi
	movl	%eax, %esi
	callq	_WREG32_PCIE_PORT
LBB0_19:
	movq	_PCIE_LC_LINK_WIDTH_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32_PCIE_PORT
	movl	%eax, %r12d
	movq	_LC_DYN_LANES_PWR_STATE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	notl	%ebx
	andl	%r12d, %ebx
	movl	$3, %edi
	callq	_LC_DYN_LANES_PWR_STATE
	orl	%ebx, %eax
	cmpl	%eax, %r12d
	je	LBB0_21
## %bb.20:
	movl	(%r15), %edi
	movl	%eax, %esi
	callq	_WREG32_PCIE_PORT
LBB0_21:
	movq	8(%r14), %rax
	movq	(%rax), %rdi
	callq	_pci_is_root_bus
	testl	%eax, %eax
	movq	_PCIE_LC_N_FTS_CNTL@GOTPCREL(%rip), %r13
	je	LBB0_22
LBB0_35:
	movq	_PCIE_CNTL2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE_PORT
	movq	_SLV_MEM_LS_EN@GOTPCREL(%rip), %rcx
	movq	_MST_MEM_LS_EN@GOTPCREL(%rip), %rdx
	movl	(%rcx), %esi
	orl	%eax, %esi
	orl	(%rdx), %esi
	movq	_REPLAY_MEM_LS_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	cmpl	%esi, %eax
	je	LBB0_37
## %bb.36:
	movl	(%rbx), %edi
	callq	_WREG32_PCIE_PORT
LBB0_37:
	movl	(%r13), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_N_FTS_MASK@GOTPCREL(%rip), %rcx
	notl	%eax
	testl	%eax, (%rcx)
	jne	LBB0_42
## %bb.38:
	movq	_PCIE_LC_STATUS1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_REVERSE_XMIT@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_42
## %bb.39:
	movq	_LC_REVERSE_RCVR@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_42
## %bb.40:
	movq	_PCIE_LC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_L0S_INACTIVITY_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	cmpl	%esi, %eax
	je	LBB0_42
## %bb.41:
	movq	_PCIE_LC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32_PCIE_PORT
	jmp	LBB0_42
LBB0_22:
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movq	(%rax), %rdi
	movq	_PCI_EXP_LNKCAP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-44(%rbp), %rdx
	callq	_pcie_capability_read_dword
	movq	_PCI_EXP_LNKCAP_CLKPM@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	-44(%rbp), %eax
	je	LBB0_35
## %bb.23:
	movq	_PCIE_LC_CNTL2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_ALLOW_PDWN_IN_L1@GOTPCREL(%rip), %rcx
	movq	_LC_ALLOW_PDWN_IN_L23@GOTPCREL(%rip), %rdx
	movl	(%rcx), %esi
	orl	%eax, %esi
	orl	(%rdx), %esi
	cmpl	%esi, %eax
	je	LBB0_25
## %bb.24:
	movl	(%rbx), %edi
	callq	_WREG32_PCIE_PORT
LBB0_25:
	movq	_THM_CLK_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32_SMC
	movl	%eax, %r14d
	movq	_CMON_CLK_SEL_MASK@GOTPCREL(%rip), %rax
	movq	_TMON_CLK_SEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	notl	%ebx
	andl	%r14d, %ebx
	movl	$1, %edi
	callq	_CMON_CLK_SEL
	movl	%eax, %r12d
	movl	$1, %edi
	callq	_TMON_CLK_SEL
	orl	%r12d, %eax
	orl	%ebx, %eax
	cmpl	%eax, %r14d
	je	LBB0_27
## %bb.26:
	movl	(%r15), %edi
	movl	%eax, %esi
	callq	_WREG32_SMC
LBB0_27:
	movq	_MISC_CLK_CTRL@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32_SMC
	movl	%eax, %r14d
	movq	_DEEP_SLEEP_CLK_SEL_MASK@GOTPCREL(%rip), %rax
	movq	_ZCLK_SEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	notl	%ebx
	andl	%r14d, %ebx
	movl	$1, %edi
	callq	_DEEP_SLEEP_CLK_SEL
	movl	%eax, %r12d
	movl	$1, %edi
	callq	_ZCLK_SEL
	orl	%r12d, %eax
	orl	%ebx, %eax
	cmpl	%eax, %r14d
	je	LBB0_29
## %bb.28:
	movl	(%r15), %edi
	movl	%eax, %esi
	callq	_WREG32_SMC
LBB0_29:
	movq	_CG_CLKPIN_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_SMC
	movq	_BCLK_AS_XCLK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	cmpl	%esi, %eax
	je	LBB0_31
## %bb.30:
	movl	(%rbx), %edi
	callq	_WREG32_SMC
LBB0_31:
	movq	_CG_CLKPIN_CNTL_2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_SMC
	movq	_FORCE_BIF_REFCLK_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	cmpl	%esi, %eax
	je	LBB0_33
## %bb.32:
	movl	(%rbx), %edi
	callq	_WREG32_SMC
LBB0_33:
	movq	_MPLL_BYPASSCLK_SEL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32_SMC
	movl	%eax, %r15d
	movq	_MPLL_CLKOUT_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	notl	%ebx
	andl	%r15d, %ebx
	movl	$4, %edi
	callq	_MPLL_CLKOUT_SEL
	orl	%ebx, %eax
	cmpl	%eax, %r15d
	je	LBB0_35
## %bb.34:
	movl	(%r14), %edi
	movl	%eax, %esi
	callq	_WREG32_SMC
	jmp	LBB0_35
	.cfi_endproc
                                        ## -- End function
	.comm	_radeon_aspm,8,3                ## @radeon_aspm
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
	.comm	_RADEON_IS_PCIE,4,2             ## @RADEON_IS_PCIE
	.comm	_PCIE_LC_N_FTS_CNTL,4,2         ## @PCIE_LC_N_FTS_CNTL
	.comm	_LC_XMIT_N_FTS_MASK,4,2         ## @LC_XMIT_N_FTS_MASK
	.comm	_LC_XMIT_N_FTS_OVERRIDE_EN,4,2  ## @LC_XMIT_N_FTS_OVERRIDE_EN
	.comm	_PCIE_LC_CNTL3,4,2              ## @PCIE_LC_CNTL3
	.comm	_LC_GO_TO_RECOVERY,4,2          ## @LC_GO_TO_RECOVERY
	.comm	_PCIE_P_CNTL,4,2                ## @PCIE_P_CNTL
	.comm	_P_IGNORE_EDB_ERR,4,2           ## @P_IGNORE_EDB_ERR
	.comm	_PCIE_LC_CNTL,4,2               ## @PCIE_LC_CNTL
	.comm	_LC_L0S_INACTIVITY_MASK,4,2     ## @LC_L0S_INACTIVITY_MASK
	.comm	_LC_L1_INACTIVITY_MASK,4,2      ## @LC_L1_INACTIVITY_MASK
	.comm	_LC_PMI_TO_L1_DIS,4,2           ## @LC_PMI_TO_L1_DIS
	.comm	_PB0_PIF_PWRDOWN_0,4,2          ## @PB0_PIF_PWRDOWN_0
	.comm	_PLL_POWER_STATE_IN_OFF_0_MASK,4,2 ## @PLL_POWER_STATE_IN_OFF_0_MASK
	.comm	_PLL_POWER_STATE_IN_TXS2_0_MASK,4,2 ## @PLL_POWER_STATE_IN_TXS2_0_MASK
	.comm	_PB0_PIF_PWRDOWN_1,4,2          ## @PB0_PIF_PWRDOWN_1
	.comm	_PLL_POWER_STATE_IN_OFF_1_MASK,4,2 ## @PLL_POWER_STATE_IN_OFF_1_MASK
	.comm	_PLL_POWER_STATE_IN_TXS2_1_MASK,4,2 ## @PLL_POWER_STATE_IN_TXS2_1_MASK
	.comm	_PB1_PIF_PWRDOWN_0,4,2          ## @PB1_PIF_PWRDOWN_0
	.comm	_PB1_PIF_PWRDOWN_1,4,2          ## @PB1_PIF_PWRDOWN_1
	.comm	_PCIE_LC_LINK_WIDTH_CNTL,4,2    ## @PCIE_LC_LINK_WIDTH_CNTL
	.comm	_LC_DYN_LANES_PWR_STATE_MASK,4,2 ## @LC_DYN_LANES_PWR_STATE_MASK
	.comm	_PCI_EXP_LNKCAP,4,2             ## @PCI_EXP_LNKCAP
	.comm	_PCI_EXP_LNKCAP_CLKPM,4,2       ## @PCI_EXP_LNKCAP_CLKPM
	.comm	_PCIE_LC_CNTL2,4,2              ## @PCIE_LC_CNTL2
	.comm	_LC_ALLOW_PDWN_IN_L1,4,2        ## @LC_ALLOW_PDWN_IN_L1
	.comm	_LC_ALLOW_PDWN_IN_L23,4,2       ## @LC_ALLOW_PDWN_IN_L23
	.comm	_THM_CLK_CNTL,4,2               ## @THM_CLK_CNTL
	.comm	_CMON_CLK_SEL_MASK,4,2          ## @CMON_CLK_SEL_MASK
	.comm	_TMON_CLK_SEL_MASK,4,2          ## @TMON_CLK_SEL_MASK
	.comm	_MISC_CLK_CTRL,4,2              ## @MISC_CLK_CTRL
	.comm	_DEEP_SLEEP_CLK_SEL_MASK,4,2    ## @DEEP_SLEEP_CLK_SEL_MASK
	.comm	_ZCLK_SEL_MASK,4,2              ## @ZCLK_SEL_MASK
	.comm	_CG_CLKPIN_CNTL,4,2             ## @CG_CLKPIN_CNTL
	.comm	_BCLK_AS_XCLK,4,2               ## @BCLK_AS_XCLK
	.comm	_CG_CLKPIN_CNTL_2,4,2           ## @CG_CLKPIN_CNTL_2
	.comm	_FORCE_BIF_REFCLK_EN,4,2        ## @FORCE_BIF_REFCLK_EN
	.comm	_MPLL_BYPASSCLK_SEL,4,2         ## @MPLL_BYPASSCLK_SEL
	.comm	_MPLL_CLKOUT_SEL_MASK,4,2       ## @MPLL_CLKOUT_SEL_MASK
	.comm	_PCIE_CNTL2,4,2                 ## @PCIE_CNTL2
	.comm	_SLV_MEM_LS_EN,4,2              ## @SLV_MEM_LS_EN
	.comm	_MST_MEM_LS_EN,4,2              ## @MST_MEM_LS_EN
	.comm	_REPLAY_MEM_LS_EN,4,2           ## @REPLAY_MEM_LS_EN
	.comm	_LC_N_FTS_MASK,4,2              ## @LC_N_FTS_MASK
	.comm	_PCIE_LC_STATUS1,4,2            ## @PCIE_LC_STATUS1
	.comm	_LC_REVERSE_XMIT,4,2            ## @LC_REVERSE_XMIT
	.comm	_LC_REVERSE_RCVR,4,2            ## @LC_REVERSE_RCVR
	.no_dead_strip	_cik_program_aspm
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cik_program_aspm
_cik_program_aspm:                      ; @cik_program_aspm
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
Lloh0:
	adrp	x8, _radeon_aspm@GOTPAGE
Lloh1:
	ldr	x8, [x8, _radeon_aspm@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	cbz	x8, LBB0_2
; %bb.1:
	mov	x19, x0
	ldr	w8, [x0]
Lloh3:
	adrp	x9, _RADEON_IS_IGP@GOTPAGE
Lloh4:
	ldr	x9, [x9, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_3
LBB0_2:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
LBB0_3:
Lloh6:
	adrp	x9, _RADEON_IS_PCIE@GOTPAGE
Lloh7:
	ldr	x9, [x9, _RADEON_IS_PCIE@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.4:
Lloh9:
	adrp	x22, _PCIE_LC_N_FTS_CNTL@GOTPAGE
Lloh10:
	ldr	x22, [x22, _PCIE_LC_N_FTS_CNTL@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_RREG32_PCIE_PORT
	mov	x20, x0
Lloh11:
	adrp	x8, _LC_XMIT_N_FTS_MASK@GOTPAGE
Lloh12:
	ldr	x8, [x8, _LC_XMIT_N_FTS_MASK@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
	bic	w21, w0, w8
	mov	w0, #36
	bl	_LC_XMIT_N_FTS
Lloh14:
	adrp	x8, _LC_XMIT_N_FTS_OVERRIDE_EN@GOTPAGE
Lloh15:
	ldr	x8, [x8, _LC_XMIT_N_FTS_OVERRIDE_EN@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
	orr	w9, w21, w0
	orr	w1, w9, w8
	cmp	w20, w1
	b.eq	LBB0_6
; %bb.5:
	ldr	w0, [x22]
	bl	_WREG32_PCIE_PORT
LBB0_6:
Lloh17:
	adrp	x20, _PCIE_LC_CNTL3@GOTPAGE
Lloh18:
	ldr	x20, [x20, _PCIE_LC_CNTL3@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PCIE_PORT
Lloh19:
	adrp	x8, _LC_GO_TO_RECOVERY@GOTPAGE
Lloh20:
	ldr	x8, [x8, _LC_GO_TO_RECOVERY@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
	orr	w1, w8, w0
	cmp	w0, w1
	b.eq	LBB0_8
; %bb.7:
	ldr	w0, [x20]
	bl	_WREG32_PCIE_PORT
LBB0_8:
Lloh22:
	adrp	x20, _PCIE_P_CNTL@GOTPAGE
Lloh23:
	ldr	x20, [x20, _PCIE_P_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PCIE_PORT
Lloh24:
	adrp	x8, _P_IGNORE_EDB_ERR@GOTPAGE
Lloh25:
	ldr	x8, [x8, _P_IGNORE_EDB_ERR@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	orr	w1, w8, w0
	cmp	w0, w1
	b.eq	LBB0_10
; %bb.9:
	ldr	w0, [x20]
	bl	_WREG32_PCIE_PORT
LBB0_10:
Lloh27:
	adrp	x8, _PCIE_LC_CNTL@GOTPAGE
Lloh28:
	ldr	x8, [x8, _PCIE_LC_CNTL@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	bl	_RREG32_PCIE_PORT
	mov	x20, x0
Lloh30:
	adrp	x8, _LC_L0S_INACTIVITY_MASK@GOTPAGE
Lloh31:
	ldr	x8, [x8, _LC_L0S_INACTIVITY_MASK@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
Lloh33:
	adrp	x9, _LC_L1_INACTIVITY_MASK@GOTPAGE
Lloh34:
	ldr	x9, [x9, _LC_L1_INACTIVITY_MASK@GOTPAGEOFF]
Lloh35:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
Lloh36:
	adrp	x21, _LC_PMI_TO_L1_DIS@GOTPAGE
Lloh37:
	ldr	x21, [x21, _LC_PMI_TO_L1_DIS@GOTPAGEOFF]
	ldr	w9, [x21]
	orr	w24, w8, w9
	mov	w0, #7
	bl	_LC_L0S_INACTIVITY
	orr	w24, w24, w0
	mov	w0, #7
	bl	_LC_L1_INACTIVITY
	orr	w8, w24, w0
	ldr	w9, [x21]
	bic	w1, w8, w9
	cmp	w20, w1
	b.eq	LBB0_12
; %bb.11:
Lloh38:
	adrp	x8, _PCIE_LC_CNTL@GOTPAGE
Lloh39:
	ldr	x8, [x8, _PCIE_LC_CNTL@GOTPAGEOFF]
Lloh40:
	ldr	w0, [x8]
	bl	_WREG32_PCIE_PORT
LBB0_12:
Lloh41:
	adrp	x27, _PB0_PIF_PWRDOWN_0@GOTPAGE
Lloh42:
	ldr	x27, [x27, _PB0_PIF_PWRDOWN_0@GOTPAGEOFF]
	ldr	w0, [x27]
	bl	_RREG32_PCIE_PORT
	mov	x20, x0
Lloh43:
	adrp	x25, _PLL_POWER_STATE_IN_OFF_0_MASK@GOTPAGE
Lloh44:
	ldr	x25, [x25, _PLL_POWER_STATE_IN_OFF_0_MASK@GOTPAGEOFF]
	ldr	w8, [x25]
Lloh45:
	adrp	x26, _PLL_POWER_STATE_IN_TXS2_0_MASK@GOTPAGE
Lloh46:
	ldr	x26, [x26, _PLL_POWER_STATE_IN_TXS2_0_MASK@GOTPAGEOFF]
	ldr	w9, [x26]
	orr	w8, w9, w8
	bic	w24, w0, w8
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_OFF_0
	mov	x21, x0
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_TXS2_0
	orr	w8, w0, w21
	orr	w1, w8, w24
	cmp	w20, w1
	b.eq	LBB0_14
; %bb.13:
	ldr	w0, [x27]
	bl	_WREG32_PCIE_PORT
LBB0_14:
Lloh47:
	adrp	x24, _PB0_PIF_PWRDOWN_1@GOTPAGE
Lloh48:
	ldr	x24, [x24, _PB0_PIF_PWRDOWN_1@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_RREG32_PCIE_PORT
	mov	x20, x0
Lloh49:
	adrp	x27, _PLL_POWER_STATE_IN_OFF_1_MASK@GOTPAGE
Lloh50:
	ldr	x27, [x27, _PLL_POWER_STATE_IN_OFF_1_MASK@GOTPAGEOFF]
	ldr	w8, [x27]
Lloh51:
	adrp	x28, _PLL_POWER_STATE_IN_TXS2_1_MASK@GOTPAGE
Lloh52:
	ldr	x28, [x28, _PLL_POWER_STATE_IN_TXS2_1_MASK@GOTPAGEOFF]
	ldr	w9, [x28]
	orr	w8, w9, w8
	bic	w23, w0, w8
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_OFF_1
	mov	x21, x0
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_TXS2_1
	orr	w8, w0, w21
	orr	w1, w8, w23
	cmp	w20, w1
	b.eq	LBB0_16
; %bb.15:
	ldr	w0, [x24]
	bl	_WREG32_PCIE_PORT
LBB0_16:
Lloh53:
	adrp	x24, _PB1_PIF_PWRDOWN_0@GOTPAGE
Lloh54:
	ldr	x24, [x24, _PB1_PIF_PWRDOWN_0@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_RREG32_PCIE_PORT
	mov	x20, x0
	ldr	w8, [x25]
	ldr	w9, [x26]
	orr	w8, w9, w8
	bic	w23, w0, w8
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_OFF_0
	mov	x21, x0
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_TXS2_0
	orr	w8, w0, w21
	orr	w1, w8, w23
	cmp	w20, w1
	b.eq	LBB0_18
; %bb.17:
	ldr	w0, [x24]
	bl	_WREG32_PCIE_PORT
LBB0_18:
Lloh55:
	adrp	x24, _PB1_PIF_PWRDOWN_1@GOTPAGE
Lloh56:
	ldr	x24, [x24, _PB1_PIF_PWRDOWN_1@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_RREG32_PCIE_PORT
	mov	x20, x0
	ldr	w8, [x27]
	ldr	w9, [x28]
	orr	w8, w9, w8
	bic	w23, w0, w8
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_OFF_1
	mov	x21, x0
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_TXS2_1
	orr	w8, w0, w21
	orr	w1, w8, w23
	cmp	w20, w1
	b.eq	LBB0_20
; %bb.19:
	ldr	w0, [x24]
	bl	_WREG32_PCIE_PORT
LBB0_20:
Lloh57:
	adrp	x21, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGE
Lloh58:
	ldr	x21, [x21, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32_PCIE_PORT
	mov	x20, x0
Lloh59:
	adrp	x8, _LC_DYN_LANES_PWR_STATE_MASK@GOTPAGE
Lloh60:
	ldr	x8, [x8, _LC_DYN_LANES_PWR_STATE_MASK@GOTPAGEOFF]
Lloh61:
	ldr	w8, [x8]
	bic	w23, w0, w8
	mov	w0, #3
	bl	_LC_DYN_LANES_PWR_STATE
	orr	w1, w23, w0
	cmp	w20, w1
	b.eq	LBB0_22
; %bb.21:
	ldr	w0, [x21]
	bl	_WREG32_PCIE_PORT
LBB0_22:
	ldr	x8, [x19, #8]
	ldr	x0, [x8]
	bl	_pci_is_root_bus
	cbz	w0, LBB0_30
LBB0_23:
Lloh62:
	adrp	x19, _PCIE_CNTL2@GOTPAGE
Lloh63:
	ldr	x19, [x19, _PCIE_CNTL2@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PCIE_PORT
Lloh64:
	adrp	x8, _SLV_MEM_LS_EN@GOTPAGE
Lloh65:
	ldr	x8, [x8, _SLV_MEM_LS_EN@GOTPAGEOFF]
Lloh66:
	ldr	w8, [x8]
Lloh67:
	adrp	x9, _MST_MEM_LS_EN@GOTPAGE
Lloh68:
	ldr	x9, [x9, _MST_MEM_LS_EN@GOTPAGEOFF]
Lloh69:
	adrp	x10, _REPLAY_MEM_LS_EN@GOTPAGE
Lloh70:
	ldr	x10, [x10, _REPLAY_MEM_LS_EN@GOTPAGEOFF]
Lloh71:
	ldr	w9, [x9]
Lloh72:
	ldr	w10, [x10]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w1, w8, w10
	cmp	w0, w1
	b.eq	LBB0_25
; %bb.24:
	ldr	w0, [x19]
	bl	_WREG32_PCIE_PORT
LBB0_25:
	ldr	w0, [x22]
	bl	_RREG32_PCIE_PORT
Lloh73:
	adrp	x8, _LC_N_FTS_MASK@GOTPAGE
Lloh74:
	ldr	x8, [x8, _LC_N_FTS_MASK@GOTPAGEOFF]
Lloh75:
	ldr	w8, [x8]
	bics	wzr, w8, w0
	b.ne	LBB0_2
; %bb.26:
Lloh76:
	adrp	x8, _PCIE_LC_STATUS1@GOTPAGE
Lloh77:
	ldr	x8, [x8, _PCIE_LC_STATUS1@GOTPAGEOFF]
Lloh78:
	ldr	w0, [x8]
	bl	_RREG32_PCIE_PORT
Lloh79:
	adrp	x8, _LC_REVERSE_XMIT@GOTPAGE
Lloh80:
	ldr	x8, [x8, _LC_REVERSE_XMIT@GOTPAGEOFF]
Lloh81:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_2
; %bb.27:
Lloh82:
	adrp	x8, _LC_REVERSE_RCVR@GOTPAGE
Lloh83:
	ldr	x8, [x8, _LC_REVERSE_RCVR@GOTPAGEOFF]
Lloh84:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_2
; %bb.28:
Lloh85:
	adrp	x8, _PCIE_LC_CNTL@GOTPAGE
Lloh86:
	ldr	x8, [x8, _PCIE_LC_CNTL@GOTPAGEOFF]
Lloh87:
	ldr	w0, [x8]
	bl	_RREG32_PCIE_PORT
Lloh88:
	adrp	x8, _LC_L0S_INACTIVITY_MASK@GOTPAGE
Lloh89:
	ldr	x8, [x8, _LC_L0S_INACTIVITY_MASK@GOTPAGEOFF]
Lloh90:
	ldr	w8, [x8]
	bic	w1, w0, w8
	cmp	w0, w1
	b.eq	LBB0_2
; %bb.29:
Lloh91:
	adrp	x8, _PCIE_LC_CNTL@GOTPAGE
Lloh92:
	ldr	x8, [x8, _PCIE_LC_CNTL@GOTPAGEOFF]
Lloh93:
	ldr	w0, [x8]
	bl	_WREG32_PCIE_PORT
	b	LBB0_2
LBB0_30:
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	ldr	x0, [x8]
Lloh94:
	adrp	x8, _PCI_EXP_LNKCAP@GOTPAGE
Lloh95:
	ldr	x8, [x8, _PCI_EXP_LNKCAP@GOTPAGEOFF]
Lloh96:
	ldr	w1, [x8]
	add	x2, sp, #12
	bl	_pcie_capability_read_dword
	ldr	w8, [sp, #12]
Lloh97:
	adrp	x9, _PCI_EXP_LNKCAP_CLKPM@GOTPAGE
Lloh98:
	ldr	x9, [x9, _PCI_EXP_LNKCAP_CLKPM@GOTPAGEOFF]
Lloh99:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_23
; %bb.31:
Lloh100:
	adrp	x19, _PCIE_LC_CNTL2@GOTPAGE
Lloh101:
	ldr	x19, [x19, _PCIE_LC_CNTL2@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PCIE_PORT
Lloh102:
	adrp	x8, _LC_ALLOW_PDWN_IN_L1@GOTPAGE
Lloh103:
	ldr	x8, [x8, _LC_ALLOW_PDWN_IN_L1@GOTPAGEOFF]
Lloh104:
	ldr	w8, [x8]
Lloh105:
	adrp	x9, _LC_ALLOW_PDWN_IN_L23@GOTPAGE
Lloh106:
	ldr	x9, [x9, _LC_ALLOW_PDWN_IN_L23@GOTPAGEOFF]
Lloh107:
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w1, w8, w9
	cmp	w0, w1
	b.eq	LBB0_33
; %bb.32:
	ldr	w0, [x19]
	bl	_WREG32_PCIE_PORT
LBB0_33:
Lloh108:
	adrp	x21, _THM_CLK_CNTL@GOTPAGE
Lloh109:
	ldr	x21, [x21, _THM_CLK_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32_SMC
	mov	x19, x0
Lloh110:
	adrp	x8, _CMON_CLK_SEL_MASK@GOTPAGE
Lloh111:
	ldr	x8, [x8, _CMON_CLK_SEL_MASK@GOTPAGEOFF]
Lloh112:
	ldr	w8, [x8]
Lloh113:
	adrp	x9, _TMON_CLK_SEL_MASK@GOTPAGE
Lloh114:
	ldr	x9, [x9, _TMON_CLK_SEL_MASK@GOTPAGEOFF]
Lloh115:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w23, w0, w8
	mov	w0, #1
	bl	_CMON_CLK_SEL
	mov	x20, x0
	mov	w0, #1
	bl	_TMON_CLK_SEL
	orr	w8, w0, w20
	orr	w1, w8, w23
	cmp	w19, w1
	b.eq	LBB0_35
; %bb.34:
	ldr	w0, [x21]
	bl	_WREG32_SMC
LBB0_35:
Lloh116:
	adrp	x21, _MISC_CLK_CTRL@GOTPAGE
Lloh117:
	ldr	x21, [x21, _MISC_CLK_CTRL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32_SMC
	mov	x19, x0
Lloh118:
	adrp	x8, _DEEP_SLEEP_CLK_SEL_MASK@GOTPAGE
Lloh119:
	ldr	x8, [x8, _DEEP_SLEEP_CLK_SEL_MASK@GOTPAGEOFF]
Lloh120:
	ldr	w8, [x8]
Lloh121:
	adrp	x9, _ZCLK_SEL_MASK@GOTPAGE
Lloh122:
	ldr	x9, [x9, _ZCLK_SEL_MASK@GOTPAGEOFF]
Lloh123:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w23, w0, w8
	mov	w0, #1
	bl	_DEEP_SLEEP_CLK_SEL
	mov	x20, x0
	mov	w0, #1
	bl	_ZCLK_SEL
	orr	w8, w0, w20
	orr	w1, w8, w23
	cmp	w19, w1
	b.eq	LBB0_37
; %bb.36:
	ldr	w0, [x21]
	bl	_WREG32_SMC
LBB0_37:
Lloh124:
	adrp	x19, _CG_CLKPIN_CNTL@GOTPAGE
Lloh125:
	ldr	x19, [x19, _CG_CLKPIN_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_SMC
Lloh126:
	adrp	x8, _BCLK_AS_XCLK@GOTPAGE
Lloh127:
	ldr	x8, [x8, _BCLK_AS_XCLK@GOTPAGEOFF]
Lloh128:
	ldr	w8, [x8]
	bic	w1, w0, w8
	cmp	w0, w1
	b.eq	LBB0_39
; %bb.38:
	ldr	w0, [x19]
	bl	_WREG32_SMC
LBB0_39:
Lloh129:
	adrp	x19, _CG_CLKPIN_CNTL_2@GOTPAGE
Lloh130:
	ldr	x19, [x19, _CG_CLKPIN_CNTL_2@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_SMC
Lloh131:
	adrp	x8, _FORCE_BIF_REFCLK_EN@GOTPAGE
Lloh132:
	ldr	x8, [x8, _FORCE_BIF_REFCLK_EN@GOTPAGEOFF]
Lloh133:
	ldr	w8, [x8]
	bic	w1, w0, w8
	cmp	w0, w1
	b.eq	LBB0_41
; %bb.40:
	ldr	w0, [x19]
	bl	_WREG32_SMC
LBB0_41:
Lloh134:
	adrp	x20, _MPLL_BYPASSCLK_SEL@GOTPAGE
Lloh135:
	ldr	x20, [x20, _MPLL_BYPASSCLK_SEL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_SMC
	mov	x19, x0
Lloh136:
	adrp	x8, _MPLL_CLKOUT_SEL_MASK@GOTPAGE
Lloh137:
	ldr	x8, [x8, _MPLL_CLKOUT_SEL_MASK@GOTPAGEOFF]
Lloh138:
	ldr	w8, [x8]
	bic	w21, w0, w8
	mov	w0, #4
	bl	_MPLL_CLKOUT_SEL
	orr	w1, w21, w0
	cmp	w19, w1
	b.eq	LBB0_23
; %bb.42:
	ldr	w0, [x20]
	bl	_WREG32_SMC
	b	LBB0_23
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh71
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGot	Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGot	Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGot	Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGot	Lloh116, Lloh117
	.loh AdrpLdrGotLdr	Lloh126, Lloh127, Lloh128
	.loh AdrpLdrGot	Lloh124, Lloh125
	.loh AdrpLdrGotLdr	Lloh131, Lloh132, Lloh133
	.loh AdrpLdrGot	Lloh129, Lloh130
	.loh AdrpLdrGotLdr	Lloh136, Lloh137, Lloh138
	.loh AdrpLdrGot	Lloh134, Lloh135
	.cfi_endproc
                                        ; -- End function
	.comm	_radeon_aspm,8,3                ; @radeon_aspm
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
	.comm	_RADEON_IS_PCIE,4,2             ; @RADEON_IS_PCIE
	.comm	_PCIE_LC_N_FTS_CNTL,4,2         ; @PCIE_LC_N_FTS_CNTL
	.comm	_LC_XMIT_N_FTS_MASK,4,2         ; @LC_XMIT_N_FTS_MASK
	.comm	_LC_XMIT_N_FTS_OVERRIDE_EN,4,2  ; @LC_XMIT_N_FTS_OVERRIDE_EN
	.comm	_PCIE_LC_CNTL3,4,2              ; @PCIE_LC_CNTL3
	.comm	_LC_GO_TO_RECOVERY,4,2          ; @LC_GO_TO_RECOVERY
	.comm	_PCIE_P_CNTL,4,2                ; @PCIE_P_CNTL
	.comm	_P_IGNORE_EDB_ERR,4,2           ; @P_IGNORE_EDB_ERR
	.comm	_PCIE_LC_CNTL,4,2               ; @PCIE_LC_CNTL
	.comm	_LC_L0S_INACTIVITY_MASK,4,2     ; @LC_L0S_INACTIVITY_MASK
	.comm	_LC_L1_INACTIVITY_MASK,4,2      ; @LC_L1_INACTIVITY_MASK
	.comm	_LC_PMI_TO_L1_DIS,4,2           ; @LC_PMI_TO_L1_DIS
	.comm	_PB0_PIF_PWRDOWN_0,4,2          ; @PB0_PIF_PWRDOWN_0
	.comm	_PLL_POWER_STATE_IN_OFF_0_MASK,4,2 ; @PLL_POWER_STATE_IN_OFF_0_MASK
	.comm	_PLL_POWER_STATE_IN_TXS2_0_MASK,4,2 ; @PLL_POWER_STATE_IN_TXS2_0_MASK
	.comm	_PB0_PIF_PWRDOWN_1,4,2          ; @PB0_PIF_PWRDOWN_1
	.comm	_PLL_POWER_STATE_IN_OFF_1_MASK,4,2 ; @PLL_POWER_STATE_IN_OFF_1_MASK
	.comm	_PLL_POWER_STATE_IN_TXS2_1_MASK,4,2 ; @PLL_POWER_STATE_IN_TXS2_1_MASK
	.comm	_PB1_PIF_PWRDOWN_0,4,2          ; @PB1_PIF_PWRDOWN_0
	.comm	_PB1_PIF_PWRDOWN_1,4,2          ; @PB1_PIF_PWRDOWN_1
	.comm	_PCIE_LC_LINK_WIDTH_CNTL,4,2    ; @PCIE_LC_LINK_WIDTH_CNTL
	.comm	_LC_DYN_LANES_PWR_STATE_MASK,4,2 ; @LC_DYN_LANES_PWR_STATE_MASK
	.comm	_PCI_EXP_LNKCAP,4,2             ; @PCI_EXP_LNKCAP
	.comm	_PCI_EXP_LNKCAP_CLKPM,4,2       ; @PCI_EXP_LNKCAP_CLKPM
	.comm	_PCIE_LC_CNTL2,4,2              ; @PCIE_LC_CNTL2
	.comm	_LC_ALLOW_PDWN_IN_L1,4,2        ; @LC_ALLOW_PDWN_IN_L1
	.comm	_LC_ALLOW_PDWN_IN_L23,4,2       ; @LC_ALLOW_PDWN_IN_L23
	.comm	_THM_CLK_CNTL,4,2               ; @THM_CLK_CNTL
	.comm	_CMON_CLK_SEL_MASK,4,2          ; @CMON_CLK_SEL_MASK
	.comm	_TMON_CLK_SEL_MASK,4,2          ; @TMON_CLK_SEL_MASK
	.comm	_MISC_CLK_CTRL,4,2              ; @MISC_CLK_CTRL
	.comm	_DEEP_SLEEP_CLK_SEL_MASK,4,2    ; @DEEP_SLEEP_CLK_SEL_MASK
	.comm	_ZCLK_SEL_MASK,4,2              ; @ZCLK_SEL_MASK
	.comm	_CG_CLKPIN_CNTL,4,2             ; @CG_CLKPIN_CNTL
	.comm	_BCLK_AS_XCLK,4,2               ; @BCLK_AS_XCLK
	.comm	_CG_CLKPIN_CNTL_2,4,2           ; @CG_CLKPIN_CNTL_2
	.comm	_FORCE_BIF_REFCLK_EN,4,2        ; @FORCE_BIF_REFCLK_EN
	.comm	_MPLL_BYPASSCLK_SEL,4,2         ; @MPLL_BYPASSCLK_SEL
	.comm	_MPLL_CLKOUT_SEL_MASK,4,2       ; @MPLL_CLKOUT_SEL_MASK
	.comm	_PCIE_CNTL2,4,2                 ; @PCIE_CNTL2
	.comm	_SLV_MEM_LS_EN,4,2              ; @SLV_MEM_LS_EN
	.comm	_MST_MEM_LS_EN,4,2              ; @MST_MEM_LS_EN
	.comm	_REPLAY_MEM_LS_EN,4,2           ; @REPLAY_MEM_LS_EN
	.comm	_LC_N_FTS_MASK,4,2              ; @LC_N_FTS_MASK
	.comm	_PCIE_LC_STATUS1,4,2            ; @PCIE_LC_STATUS1
	.comm	_LC_REVERSE_XMIT,4,2            ; @LC_REVERSE_XMIT
	.comm	_LC_REVERSE_RCVR,4,2            ; @LC_REVERSE_RCVR
	.no_dead_strip	_cik_program_aspm
.subsections_via_symbols
