	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function si_get_pcie_lanes
_si_get_pcie_lanes:                     ## @si_get_pcie_lanes
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	xorl	%ecx, %ecx
	testl	%eax, (%rdi)
	jne	LBB0_3
## %bb.1:
	movq	_PCIE_LC_LINK_WIDTH_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_LINK_WIDTH_RD_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_LC_LINK_WIDTH_RD_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	addl	$-128, %eax
	movl	$16, %ecx
	cmpl	$4, %eax
	ja	LBB0_3
## %bb.2:
	cltq
	leaq	l_switch.table.si_get_pcie_lanes(%rip), %rcx
	movl	(%rcx,%rax,4), %ecx
LBB0_3:
	movl	%ecx, %eax
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_PCIE_LC_LINK_WIDTH_CNTL,4,2    ## @PCIE_LC_LINK_WIDTH_CNTL
	.comm	_LC_LINK_WIDTH_RD_MASK,4,2      ## @LC_LINK_WIDTH_RD_MASK
	.comm	_LC_LINK_WIDTH_RD_SHIFT,4,2     ## @LC_LINK_WIDTH_RD_SHIFT
	.no_dead_strip	_si_get_pcie_lanes
	.section	__TEXT,__const
	.p2align	2                               ## @switch.table.si_get_pcie_lanes
l_switch.table.si_get_pcie_lanes:
	.long	8                               ## 0x8
	.long	4                               ## 0x4
	.long	2                               ## 0x2
	.long	16                              ## 0x10
	.long	1                               ## 0x1

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function si_get_pcie_lanes
_si_get_pcie_lanes:                     ; @si_get_pcie_lanes
	.cfi_startproc
; %bb.0:
	stp	x29, x30, [sp, #-16]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 16
	mov	x29, sp
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _AMD_IS_APU@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_IS_APU@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
	mov	w0, #0
	ldp	x29, x30, [sp], #16             ; 16-byte Folded Reload
	ret
LBB0_2:
Lloh3:
	adrp	x8, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	bl	_RREG32_PCIE_PORT
Lloh6:
	adrp	x8, _LC_LINK_WIDTH_RD_MASK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _LC_LINK_WIDTH_RD_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh9:
	adrp	x9, _LC_LINK_WIDTH_RD_SHIFT@GOTPAGE
Lloh10:
	ldr	x9, [x9, _LC_LINK_WIDTH_RD_SHIFT@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	asr	w8, w8, w9
	sub	w8, w8, #128
	cmp	w8, #4
	b.hi	LBB0_4
; %bb.3:
Lloh12:
	adrp	x9, l_switch.table.si_get_pcie_lanes@PAGE
Lloh13:
	add	x9, x9, l_switch.table.si_get_pcie_lanes@PAGEOFF
	ldr	w0, [x9, w8, sxtw #2]
	ldp	x29, x30, [sp], #16             ; 16-byte Folded Reload
	ret
LBB0_4:
	mov	w0, #16
	ldp	x29, x30, [sp], #16             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpAdd	Lloh12, Lloh13
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_PCIE_LC_LINK_WIDTH_CNTL,4,2    ; @PCIE_LC_LINK_WIDTH_CNTL
	.comm	_LC_LINK_WIDTH_RD_MASK,4,2      ; @LC_LINK_WIDTH_RD_MASK
	.comm	_LC_LINK_WIDTH_RD_SHIFT,4,2     ; @LC_LINK_WIDTH_RD_SHIFT
	.no_dead_strip	_si_get_pcie_lanes
	.section	__TEXT,__const
	.p2align	2                               ; @switch.table.si_get_pcie_lanes
l_switch.table.si_get_pcie_lanes:
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	16                              ; 0x10
	.long	1                               ; 0x1

.subsections_via_symbols
