	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_evergreen_pcie_gen2_enable     ## -- Begin function evergreen_pcie_gen2_enable
	.p2align	4, 0x90
_evergreen_pcie_gen2_enable:            ## @evergreen_pcie_gen2_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	_radeon_pcie_gen2@GOTPCREL(%rip), %rax
	cmpq	$0, (%rax)
	je	LBB0_12
## %bb.1:
	movq	%rdi, %rbx
	movl	(%rdi), %eax
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_2
LBB0_12:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
LBB0_2:
	movq	_RADEON_IS_PCIE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_12
## %bb.3:
	movq	%rbx, %rdi
	callq	_ASIC_IS_X2
	testq	%rax, %rax
	jne	LBB0_12
## %bb.4:
	movq	8(%rbx), %rax
	movq	(%rax), %rax
	movq	(%rax), %rax
	movq	_PCIE_SPEED_5_0GT@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_6
## %bb.5:
	movq	_PCIE_SPEED_8_0GT@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_12
LBB0_6:
	movq	_PCIE_LC_SPEED_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32_PCIE_PORT
	movl	%eax, %ebx
	movq	_LC_CURRENT_DATA_RATE@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_7
## %bb.13:
	leaq	L_.str(%rip), %rdi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_DRM_INFO                       ## TAILCALL
LBB0_7:
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_INFO
	movq	_LC_OTHER_SIDE_EVER_SENT_GEN2@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	jne	LBB0_9
## %bb.8:
	movq	_LC_OTHER_SIDE_SUPPORTS_GEN2@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_10
LBB0_9:
	movq	_PCIE_LC_LINK_WIDTH_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_UPCONFIGURE_DIS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32_PCIE_PORT
	movl	(%r14), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_TARGET_LINK_SPEED_OVERRIDE_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r14), %edi
	callq	_WREG32_PCIE_PORT
	movl	(%r14), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_CLR_FAILED_SPD_CHANGE_CNT@GOTPCREL(%rip), %rbx
	orl	(%rbx), %eax
	movl	(%r14), %edi
	movl	%eax, %esi
	callq	_WREG32_PCIE_PORT
	movl	(%r14), %edi
	callq	_RREG32_PCIE_PORT
	movl	(%rbx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r14), %edi
	callq	_WREG32_PCIE_PORT
	movl	(%r14), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_GEN2_EN_STRAP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r14), %edi
LBB0_11:
	movl	%eax, %esi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_WREG32_PCIE_PORT               ## TAILCALL
LBB0_10:
	movq	_PCIE_LC_LINK_WIDTH_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_UPCONFIGURE_DIS@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	jmp	LBB0_11
	.cfi_endproc
                                        ## -- End function
	.comm	_radeon_pcie_gen2,8,3           ## @radeon_pcie_gen2
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
	.comm	_RADEON_IS_PCIE,4,2             ## @RADEON_IS_PCIE
	.comm	_PCIE_SPEED_5_0GT,8,3           ## @PCIE_SPEED_5_0GT
	.comm	_PCIE_SPEED_8_0GT,8,3           ## @PCIE_SPEED_8_0GT
	.comm	_PCIE_LC_SPEED_CNTL,4,2         ## @PCIE_LC_SPEED_CNTL
	.comm	_LC_CURRENT_DATA_RATE,4,2       ## @LC_CURRENT_DATA_RATE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"PCIE gen 2 link speeds already enabled\n"

L_.str.1:                               ## @.str.1
	.asciz	"enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"

	.comm	_LC_OTHER_SIDE_EVER_SENT_GEN2,4,2 ## @LC_OTHER_SIDE_EVER_SENT_GEN2
	.comm	_LC_OTHER_SIDE_SUPPORTS_GEN2,4,2 ## @LC_OTHER_SIDE_SUPPORTS_GEN2
	.comm	_PCIE_LC_LINK_WIDTH_CNTL,4,2    ## @PCIE_LC_LINK_WIDTH_CNTL
	.comm	_LC_UPCONFIGURE_DIS,4,2         ## @LC_UPCONFIGURE_DIS
	.comm	_LC_TARGET_LINK_SPEED_OVERRIDE_EN,4,2 ## @LC_TARGET_LINK_SPEED_OVERRIDE_EN
	.comm	_LC_CLR_FAILED_SPD_CHANGE_CNT,4,2 ## @LC_CLR_FAILED_SPD_CHANGE_CNT
	.comm	_LC_GEN2_EN_STRAP,4,2           ## @LC_GEN2_EN_STRAP
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_evergreen_pcie_gen2_enable     ; -- Begin function evergreen_pcie_gen2_enable
	.p2align	2
_evergreen_pcie_gen2_enable:            ; @evergreen_pcie_gen2_enable
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
Lloh0:
	adrp	x8, _radeon_pcie_gen2@GOTPAGE
Lloh1:
	ldr	x8, [x8, _radeon_pcie_gen2@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	cbz	x8, LBB0_2
; %bb.1:
	mov	x19, x0
	ldr	w8, [x0]
Lloh3:
	adrp	x9, _RADEON_IS_IGP@GOTPAGE
Lloh4:
	ldr	x9, [x9, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_3
LBB0_2:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_3:
Lloh6:
	adrp	x9, _RADEON_IS_PCIE@GOTPAGE
Lloh7:
	ldr	x9, [x9, _RADEON_IS_PCIE@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.4:
	mov	x0, x19
	bl	_ASIC_IS_X2
	cbnz	x0, LBB0_2
; %bb.5:
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	ldr	x8, [x8]
Lloh9:
	adrp	x9, _PCIE_SPEED_5_0GT@GOTPAGE
Lloh10:
	ldr	x9, [x9, _PCIE_SPEED_5_0GT@GOTPAGEOFF]
Lloh11:
	ldr	x9, [x9]
Lloh12:
	adrp	x10, _PCIE_SPEED_8_0GT@GOTPAGE
Lloh13:
	ldr	x10, [x10, _PCIE_SPEED_8_0GT@GOTPAGEOFF]
Lloh14:
	ldr	x10, [x10]
	cmp	x8, x9
	ccmp	x8, x10, #4, ne
	b.ne	LBB0_2
; %bb.6:
Lloh15:
	adrp	x20, _PCIE_LC_SPEED_CNTL@GOTPAGE
Lloh16:
	ldr	x20, [x20, _PCIE_LC_SPEED_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PCIE_PORT
Lloh17:
	adrp	x8, _LC_CURRENT_DATA_RATE@GOTPAGE
Lloh18:
	ldr	x8, [x8, _LC_CURRENT_DATA_RATE@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_8
; %bb.7:
Lloh20:
	adrp	x0, l_.str@PAGE
Lloh21:
	add	x0, x0, l_.str@PAGEOFF
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_DRM_INFO
LBB0_8:
	mov	x19, x0
Lloh22:
	adrp	x0, l_.str.1@PAGE
Lloh23:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_INFO
Lloh24:
	adrp	x8, _LC_OTHER_SIDE_EVER_SENT_GEN2@GOTPAGE
Lloh25:
	ldr	x8, [x8, _LC_OTHER_SIDE_EVER_SENT_GEN2@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	tst	w8, w19
	b.ne	LBB0_10
; %bb.9:
Lloh27:
	adrp	x8, _LC_OTHER_SIDE_SUPPORTS_GEN2@GOTPAGE
Lloh28:
	ldr	x8, [x8, _LC_OTHER_SIDE_SUPPORTS_GEN2@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	tst	w8, w19
	b.eq	LBB0_12
LBB0_10:
Lloh30:
	adrp	x19, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGE
Lloh31:
	ldr	x19, [x19, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PCIE_PORT
Lloh32:
	adrp	x8, _LC_UPCONFIGURE_DIS@GOTPAGE
Lloh33:
	ldr	x8, [x8, _LC_UPCONFIGURE_DIS@GOTPAGEOFF]
Lloh34:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w0, [x19]
	bl	_WREG32_PCIE_PORT
	ldr	w0, [x20]
	bl	_RREG32_PCIE_PORT
Lloh35:
	adrp	x8, _LC_TARGET_LINK_SPEED_OVERRIDE_EN@GOTPAGE
Lloh36:
	ldr	x8, [x8, _LC_TARGET_LINK_SPEED_OVERRIDE_EN@GOTPAGEOFF]
Lloh37:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32_PCIE_PORT
	ldr	w0, [x20]
	bl	_RREG32_PCIE_PORT
Lloh38:
	adrp	x19, _LC_CLR_FAILED_SPD_CHANGE_CNT@GOTPAGE
Lloh39:
	ldr	x19, [x19, _LC_CLR_FAILED_SPD_CHANGE_CNT@GOTPAGEOFF]
	ldr	w8, [x19]
	orr	w1, w8, w0
	ldr	w0, [x20]
	bl	_WREG32_PCIE_PORT
	ldr	w0, [x20]
	bl	_RREG32_PCIE_PORT
	ldr	w8, [x19]
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32_PCIE_PORT
	ldr	w0, [x20]
	bl	_RREG32_PCIE_PORT
Lloh40:
	adrp	x8, _LC_GEN2_EN_STRAP@GOTPAGE
Lloh41:
	ldr	x8, [x8, _LC_GEN2_EN_STRAP@GOTPAGEOFF]
Lloh42:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x20]
LBB0_11:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_WREG32_PCIE_PORT
LBB0_12:
Lloh43:
	adrp	x19, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGE
Lloh44:
	ldr	x19, [x19, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PCIE_PORT
Lloh45:
	adrp	x8, _LC_UPCONFIGURE_DIS@GOTPAGE
Lloh46:
	ldr	x8, [x8, _LC_UPCONFIGURE_DIS@GOTPAGEOFF]
Lloh47:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x19]
	b	LBB0_11
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpAdd	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh43, Lloh44
	.cfi_endproc
                                        ; -- End function
	.comm	_radeon_pcie_gen2,8,3           ; @radeon_pcie_gen2
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
	.comm	_RADEON_IS_PCIE,4,2             ; @RADEON_IS_PCIE
	.comm	_PCIE_SPEED_5_0GT,8,3           ; @PCIE_SPEED_5_0GT
	.comm	_PCIE_SPEED_8_0GT,8,3           ; @PCIE_SPEED_8_0GT
	.comm	_PCIE_LC_SPEED_CNTL,4,2         ; @PCIE_LC_SPEED_CNTL
	.comm	_LC_CURRENT_DATA_RATE,4,2       ; @LC_CURRENT_DATA_RATE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"PCIE gen 2 link speeds already enabled\n"

l_.str.1:                               ; @.str.1
	.asciz	"enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"

	.comm	_LC_OTHER_SIDE_EVER_SENT_GEN2,4,2 ; @LC_OTHER_SIDE_EVER_SENT_GEN2
	.comm	_LC_OTHER_SIDE_SUPPORTS_GEN2,4,2 ; @LC_OTHER_SIDE_SUPPORTS_GEN2
	.comm	_PCIE_LC_LINK_WIDTH_CNTL,4,2    ; @PCIE_LC_LINK_WIDTH_CNTL
	.comm	_LC_UPCONFIGURE_DIS,4,2         ; @LC_UPCONFIGURE_DIS
	.comm	_LC_TARGET_LINK_SPEED_OVERRIDE_EN,4,2 ; @LC_TARGET_LINK_SPEED_OVERRIDE_EN
	.comm	_LC_CLR_FAILED_SPD_CHANGE_CNT,4,2 ; @LC_CLR_FAILED_SPD_CHANGE_CNT
	.comm	_LC_GEN2_EN_STRAP,4,2           ; @LC_GEN2_EN_STRAP
.subsections_via_symbols
