	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v9_0_constants_init
_gfx_v9_0_constants_init:               ## @gfx_v9_0_constants_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_GC@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	movq	_GRBM_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_READ_TIMEOUT@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%esi, %esi
	movl	$255, %r8d
	callq	_WREG32_FIELD15_RLC
	movq	%r14, %rdi
	callq	_gfx_v9_0_tiling_mode_table_init
	movq	%r14, %rdi
	callq	_gfx_v9_0_setup_rb
	leaq	28(%r14), %rsi
	movq	%r14, %rdi
	callq	_gfx_v9_0_get_cu_info
	movl	(%r15), %edi
	movq	_mmDB_DEBUG2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	%eax, 24(%r14)
	movq	%r14, %rdi
	callq	_mutex_lock
	movq	16(%r14), %rax
	movq	_AMDGPU_GFXHUB_0@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	cmpl	$0, (%rax,%rcx,4)
	jle	LBB0_4
## %bb.1:
	movq	%r14, %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	xorl	%r8d, %r8d
	callq	_soc15_grbm_select
	movq	_SH_MEM_CONFIG@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	_ALIGNMENT_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_SH_MEM_ALIGNMENT_MODE_UNALIGNED@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%edi, %edi
	callq	_REG_SET_FIELD
	movl	(%r13), %esi
	movq	_RETRY_DISABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_amdgpu_noretry@GOTPCREL(%rip), %rdi
	xorl	%ecx, %ecx
	cmpl	$0, (%rdi)
	setne	%cl
	movq	%rax, %rdi
	callq	_REG_SET_FIELD
	movl	(%r15), %edi
	movq	_mmSH_MEM_CONFIG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movq	%rax, %rcx
	callq	_WREG32_SOC15_RLC
	movl	(%r15), %edi
	movq	_mmSH_MEM_BASES@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15_RLC
	movq	16(%r14), %rax
	movq	_AMDGPU_GFXHUB_0@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	cmpl	$2, (%rax,%rcx,4)
	jl	LBB0_4
## %bb.2:
	movl	$1, %ebx
	movq	_SH_MEM_BASES@GOTPCREL(%rip), %r12
	.p2align	4, 0x90
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	movl	%ebx, %r8d
	callq	_soc15_grbm_select
	movl	(%r13), %esi
	movq	_ALIGNMENT_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_SH_MEM_ALIGNMENT_MODE_UNALIGNED@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%edi, %edi
	callq	_REG_SET_FIELD
	movl	(%r13), %esi
	movq	_RETRY_DISABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%ecx, %ecx
	movq	_amdgpu_noretry@GOTPCREL(%rip), %rdi
	cmpl	$0, (%rdi)
	setne	%cl
	movq	%rax, %rdi
	callq	_REG_SET_FIELD
	movl	(%r15), %edi
	movq	_mmSH_MEM_CONFIG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movq	%rax, %rcx
	callq	_WREG32_SOC15_RLC
	movl	(%r12), %esi
	movq	_PRIVATE_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%edi, %edi
	callq	_REG_SET_FIELD
	movl	(%r12), %esi
	movq	_SHARED_BASE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%rax, %rdi
	callq	_REG_SET_FIELD
	movl	(%r15), %edi
	movq	_mmSH_MEM_BASES@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movq	%rax, %rcx
	callq	_WREG32_SOC15_RLC
	incl	%ebx
	movq	16(%r14), %rax
	movq	_AMDGPU_GFXHUB_0@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	cmpl	(%rax,%rcx,4), %ebx
	jl	LBB0_3
LBB0_4:
	movq	%r14, %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	xorl	%r8d, %r8d
	callq	_soc15_grbm_select
	movq	%r14, %rdi
	callq	_mutex_unlock
	movq	%r14, %rdi
	callq	_gfx_v9_0_init_compute_vmid
	movq	%r14, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_gfx_v9_0_init_gds_vmid         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_GC,4,2                         ## @GC
	.comm	_GRBM_CNTL,4,2                  ## @GRBM_CNTL
	.comm	_READ_TIMEOUT,4,2               ## @READ_TIMEOUT
	.comm	_mmDB_DEBUG2,4,2                ## @mmDB_DEBUG2
	.comm	_AMDGPU_GFXHUB_0,8,3            ## @AMDGPU_GFXHUB_0
	.comm	_SH_MEM_CONFIG,4,2              ## @SH_MEM_CONFIG
	.comm	_ALIGNMENT_MODE,4,2             ## @ALIGNMENT_MODE
	.comm	_SH_MEM_ALIGNMENT_MODE_UNALIGNED,4,2 ## @SH_MEM_ALIGNMENT_MODE_UNALIGNED
	.comm	_RETRY_DISABLE,4,2              ## @RETRY_DISABLE
	.comm	_amdgpu_noretry,4,2             ## @amdgpu_noretry
	.comm	_mmSH_MEM_CONFIG,4,2            ## @mmSH_MEM_CONFIG
	.comm	_mmSH_MEM_BASES,4,2             ## @mmSH_MEM_BASES
	.comm	_SH_MEM_BASES,4,2               ## @SH_MEM_BASES
	.comm	_PRIVATE_BASE,4,2               ## @PRIVATE_BASE
	.comm	_SHARED_BASE,4,2                ## @SHARED_BASE
	.no_dead_strip	_gfx_v9_0_constants_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v9_0_constants_init
_gfx_v9_0_constants_init:               ; @gfx_v9_0_constants_init
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
Lloh0:
	adrp	x21, _GC@GOTPAGE
Lloh1:
	ldr	x21, [x21, _GC@GOTPAGEOFF]
	ldr	w0, [x21]
Lloh2:
	adrp	x8, _GRBM_CNTL@GOTPAGE
Lloh3:
	ldr	x8, [x8, _GRBM_CNTL@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
Lloh5:
	adrp	x8, _READ_TIMEOUT@GOTPAGE
Lloh6:
	ldr	x8, [x8, _READ_TIMEOUT@GOTPAGEOFF]
Lloh7:
	ldr	w3, [x8]
	mov	w1, #0
	mov	w4, #255
	bl	_WREG32_FIELD15_RLC
	mov	x0, x19
	bl	_gfx_v9_0_tiling_mode_table_init
	mov	x0, x19
	bl	_gfx_v9_0_setup_rb
	add	x1, x19, #28
	mov	x0, x19
	bl	_gfx_v9_0_get_cu_info
	ldr	w0, [x21]
Lloh8:
	adrp	x8, _mmDB_DEBUG2@GOTPAGE
Lloh9:
	ldr	x8, [x8, _mmDB_DEBUG2@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_RREG32_SOC15
	str	w0, [x19, #24]
	mov	x0, x19
	bl	_mutex_lock
	ldr	x8, [x19, #16]
Lloh11:
	adrp	x9, _AMDGPU_GFXHUB_0@GOTPAGE
Lloh12:
	ldr	x9, [x9, _AMDGPU_GFXHUB_0@GOTPAGEOFF]
Lloh13:
	ldr	x9, [x9]
	ldr	w8, [x8, x9, lsl #2]
	cmp	w8, #1
	b.lt	LBB0_4
; %bb.1:
	mov	x0, x19
	mov	w1, #0
	mov	w2, #0
	mov	w3, #0
	mov	w4, #0
	bl	_soc15_grbm_select
Lloh14:
	adrp	x23, _SH_MEM_CONFIG@GOTPAGE
Lloh15:
	ldr	x23, [x23, _SH_MEM_CONFIG@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh16:
	adrp	x8, _ALIGNMENT_MODE@GOTPAGE
Lloh17:
	ldr	x8, [x8, _ALIGNMENT_MODE@GOTPAGEOFF]
Lloh18:
	ldr	w2, [x8]
Lloh19:
	adrp	x8, _SH_MEM_ALIGNMENT_MODE_UNALIGNED@GOTPAGE
Lloh20:
	ldr	x8, [x8, _SH_MEM_ALIGNMENT_MODE_UNALIGNED@GOTPAGEOFF]
Lloh21:
	ldr	w3, [x8]
	mov	x0, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh22:
	adrp	x8, _RETRY_DISABLE@GOTPAGE
Lloh23:
	ldr	x8, [x8, _RETRY_DISABLE@GOTPAGEOFF]
Lloh24:
	ldr	w2, [x8]
Lloh25:
	adrp	x27, _amdgpu_noretry@GOTPAGE
Lloh26:
	ldr	x27, [x27, _amdgpu_noretry@GOTPAGEOFF]
	ldr	w8, [x27]
	cmp	w8, #0
	cset	w3, ne
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x21]
Lloh27:
	adrp	x28, _mmSH_MEM_CONFIG@GOTPAGE
Lloh28:
	ldr	x28, [x28, _mmSH_MEM_CONFIG@GOTPAGEOFF]
	ldr	w2, [x28]
	mov	w1, #0
	bl	_WREG32_SOC15_RLC
	ldr	w0, [x21]
Lloh29:
	adrp	x24, _mmSH_MEM_BASES@GOTPAGE
Lloh30:
	ldr	x24, [x24, _mmSH_MEM_BASES@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	w1, #0
	mov	x3, #0
	bl	_WREG32_SOC15_RLC
	ldr	x8, [x19, #16]
Lloh31:
	adrp	x9, _AMDGPU_GFXHUB_0@GOTPAGE
Lloh32:
	ldr	x9, [x9, _AMDGPU_GFXHUB_0@GOTPAGEOFF]
Lloh33:
	ldr	x9, [x9]
	ldr	w8, [x8, x9, lsl #2]
	cmp	w8, #2
	b.lt	LBB0_4
; %bb.2:
	mov	w20, #1
Lloh34:
	adrp	x22, _SH_MEM_BASES@GOTPAGE
Lloh35:
	ldr	x22, [x22, _SH_MEM_BASES@GOTPAGEOFF]
Lloh36:
	adrp	x25, _PRIVATE_BASE@GOTPAGE
Lloh37:
	ldr	x25, [x25, _PRIVATE_BASE@GOTPAGEOFF]
Lloh38:
	adrp	x26, _SHARED_BASE@GOTPAGE
Lloh39:
	ldr	x26, [x26, _SHARED_BASE@GOTPAGEOFF]
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x19
	mov	w1, #0
	mov	w2, #0
	mov	w3, #0
	mov	x4, x20
	bl	_soc15_grbm_select
	ldr	w1, [x23]
Lloh40:
	adrp	x8, _ALIGNMENT_MODE@GOTPAGE
Lloh41:
	ldr	x8, [x8, _ALIGNMENT_MODE@GOTPAGEOFF]
Lloh42:
	ldr	w2, [x8]
Lloh43:
	adrp	x8, _SH_MEM_ALIGNMENT_MODE_UNALIGNED@GOTPAGE
Lloh44:
	ldr	x8, [x8, _SH_MEM_ALIGNMENT_MODE_UNALIGNED@GOTPAGEOFF]
Lloh45:
	ldr	w3, [x8]
	mov	x0, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x23]
Lloh46:
	adrp	x8, _RETRY_DISABLE@GOTPAGE
Lloh47:
	ldr	x8, [x8, _RETRY_DISABLE@GOTPAGEOFF]
Lloh48:
	ldr	w2, [x8]
	ldr	w8, [x27]
	cmp	w8, #0
	cset	w3, ne
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x21]
	ldr	w2, [x28]
	mov	w1, #0
	bl	_WREG32_SOC15_RLC
	ldr	w1, [x22]
	ldr	w2, [x25]
	mov	x0, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x22]
	ldr	w2, [x26]
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x21]
	ldr	w2, [x24]
	mov	w1, #0
	bl	_WREG32_SOC15_RLC
	add	w20, w20, #1
	ldr	x8, [x19, #16]
Lloh49:
	adrp	x9, _AMDGPU_GFXHUB_0@GOTPAGE
Lloh50:
	ldr	x9, [x9, _AMDGPU_GFXHUB_0@GOTPAGEOFF]
Lloh51:
	ldr	x9, [x9]
	ldr	w8, [x8, x9, lsl #2]
	cmp	w20, w8
	b.lt	LBB0_3
LBB0_4:
	mov	x0, x19
	mov	w1, #0
	mov	w2, #0
	mov	w3, #0
	mov	w4, #0
	bl	_soc15_grbm_select
	mov	x0, x19
	bl	_mutex_unlock
	mov	x0, x19
	bl	_gfx_v9_0_init_compute_vmid
	mov	x0, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_gfx_v9_0_init_gds_vmid
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.cfi_endproc
                                        ; -- End function
	.comm	_GC,4,2                         ; @GC
	.comm	_GRBM_CNTL,4,2                  ; @GRBM_CNTL
	.comm	_READ_TIMEOUT,4,2               ; @READ_TIMEOUT
	.comm	_mmDB_DEBUG2,4,2                ; @mmDB_DEBUG2
	.comm	_AMDGPU_GFXHUB_0,8,3            ; @AMDGPU_GFXHUB_0
	.comm	_SH_MEM_CONFIG,4,2              ; @SH_MEM_CONFIG
	.comm	_ALIGNMENT_MODE,4,2             ; @ALIGNMENT_MODE
	.comm	_SH_MEM_ALIGNMENT_MODE_UNALIGNED,4,2 ; @SH_MEM_ALIGNMENT_MODE_UNALIGNED
	.comm	_RETRY_DISABLE,4,2              ; @RETRY_DISABLE
	.comm	_amdgpu_noretry,4,2             ; @amdgpu_noretry
	.comm	_mmSH_MEM_CONFIG,4,2            ; @mmSH_MEM_CONFIG
	.comm	_mmSH_MEM_BASES,4,2             ; @mmSH_MEM_BASES
	.comm	_SH_MEM_BASES,4,2               ; @SH_MEM_BASES
	.comm	_PRIVATE_BASE,4,2               ; @PRIVATE_BASE
	.comm	_SHARED_BASE,4,2                ; @SHARED_BASE
	.no_dead_strip	_gfx_v9_0_constants_init
.subsections_via_symbols
