	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v6_0_ring_emit_fence
_gfx_v6_0_ring_emit_fence:              ## @gfx_v6_0_ring_emit_fence
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_AMDGPU_FENCE_FLAG_64BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	andl	%ecx, %r14d
	movq	_AMDGPU_FENCE_FLAG_INT@GOTPCREL(%rip), %rax
	xorl	%r15d, %r15d
	andl	(%rax), %ecx
	movl	%edx, -44(%rbp)                 ## 4-byte Spill
	movl	%esi, %r12d
	movq	%rdi, %r13
	setne	%r15b
	movq	_PACKET3_SET_CONFIG_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_PACKET3
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_mmCP_COHER_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PACKET3_SET_CONFIG_REG_START@GOTPCREL(%rip), %rax
	subl	(%rax), %esi
	movq	%r13, %rdi
	callq	_amdgpu_ring_write
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
	movq	_PACKET3_SURFACE_SYNC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$3, %esi
	callq	_PACKET3
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_PACKET3_TCL1_ACTION_ENA@GOTPCREL(%rip), %rax
	movq	_PACKET3_TC_ACTION_ENA@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movq	_PACKET3_SH_KCACHE_ACTION_ENA@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_PACKET3_SH_ICACHE_ACTION_ENA@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	%r13, %rdi
	callq	_amdgpu_ring_write
	movq	%r13, %rdi
	movl	$-1, %esi
	callq	_amdgpu_ring_write
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
	movq	%r13, %rdi
	movl	$10, %esi
	callq	_amdgpu_ring_write
	movq	_PACKET3_EVENT_WRITE_EOP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$4, %esi
	callq	_PACKET3
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_CACHE_FLUSH_AND_INV_TS_EVENT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_EVENT_TYPE
	movl	%eax, %ebx
	movl	$5, %edi
	callq	_EVENT_INDEX
	orl	%eax, %ebx
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_amdgpu_ring_write
	movl	%r12d, %esi
	andl	$-4, %esi
	movq	%r13, %rdi
	callq	_amdgpu_ring_write
	movl	%r12d, %edi
	callq	_upper_32_bits
	movzwl	%ax, %eax
	cmpl	$1, %r14d
	movl	$2, %edx
	sbbl	$0, %edx
	movq	_CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	orl	%eax, %edx
	addl	%r15d, %r15d
	movq	_CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r15d
	orl	%edx, %r15d
	movq	%r13, %rdi
	movl	%r15d, %esi
	callq	_amdgpu_ring_write
	movl	-44(%rbp), %ebx                 ## 4-byte Reload
	movl	%ebx, %edi
	callq	_lower_32_bits
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	%ebx, %edi
	callq	_upper_32_bits
	movq	%r13, %rdi
	movl	%eax, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_write              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_FENCE_FLAG_64BIT,4,2    ## @AMDGPU_FENCE_FLAG_64BIT
	.comm	_AMDGPU_FENCE_FLAG_INT,4,2      ## @AMDGPU_FENCE_FLAG_INT
	.comm	_PACKET3_SET_CONFIG_REG,4,2     ## @PACKET3_SET_CONFIG_REG
	.comm	_mmCP_COHER_CNTL2,4,2           ## @mmCP_COHER_CNTL2
	.comm	_PACKET3_SET_CONFIG_REG_START,4,2 ## @PACKET3_SET_CONFIG_REG_START
	.comm	_PACKET3_SURFACE_SYNC,4,2       ## @PACKET3_SURFACE_SYNC
	.comm	_PACKET3_TCL1_ACTION_ENA,4,2    ## @PACKET3_TCL1_ACTION_ENA
	.comm	_PACKET3_TC_ACTION_ENA,4,2      ## @PACKET3_TC_ACTION_ENA
	.comm	_PACKET3_SH_KCACHE_ACTION_ENA,4,2 ## @PACKET3_SH_KCACHE_ACTION_ENA
	.comm	_PACKET3_SH_ICACHE_ACTION_ENA,4,2 ## @PACKET3_SH_ICACHE_ACTION_ENA
	.comm	_PACKET3_EVENT_WRITE_EOP,4,2    ## @PACKET3_EVENT_WRITE_EOP
	.comm	_CACHE_FLUSH_AND_INV_TS_EVENT,4,2 ## @CACHE_FLUSH_AND_INV_TS_EVENT
	.comm	_CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT,4,2 ## @CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT
	.comm	_CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT,4,2 ## @CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT
	.no_dead_strip	_gfx_v6_0_ring_emit_fence
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v6_0_ring_emit_fence
_gfx_v6_0_ring_emit_fence:              ; @gfx_v6_0_ring_emit_fence
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x21, x3
	mov	x20, x2
	mov	x22, x1
	mov	x19, x0
Lloh0:
	adrp	x8, _AMDGPU_FENCE_FLAG_64BIT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPU_FENCE_FLAG_64BIT@GOTPAGEOFF]
Lloh2:
	ldr	w25, [x8]
Lloh3:
	adrp	x8, _AMDGPU_FENCE_FLAG_INT@GOTPAGE
Lloh4:
	ldr	x8, [x8, _AMDGPU_FENCE_FLAG_INT@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	tst	w8, w3
	cset	w24, ne
Lloh6:
	adrp	x8, _PACKET3_SET_CONFIG_REG@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PACKET3_SET_CONFIG_REG@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	mov	w26, #1
	mov	w1, #1
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh9:
	adrp	x8, _mmCP_COHER_CNTL2@GOTPAGE
Lloh10:
	ldr	x8, [x8, _mmCP_COHER_CNTL2@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
Lloh12:
	adrp	x9, _PACKET3_SET_CONFIG_REG_START@GOTPAGE
Lloh13:
	ldr	x9, [x9, _PACKET3_SET_CONFIG_REG_START@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	sub	w1, w8, w9
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_ring_write
Lloh15:
	adrp	x8, _PACKET3_SURFACE_SYNC@GOTPAGE
Lloh16:
	ldr	x8, [x8, _PACKET3_SURFACE_SYNC@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	mov	w1, #3
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh18:
	adrp	x8, _PACKET3_TCL1_ACTION_ENA@GOTPAGE
Lloh19:
	ldr	x8, [x8, _PACKET3_TCL1_ACTION_ENA@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
Lloh21:
	adrp	x9, _PACKET3_TC_ACTION_ENA@GOTPAGE
Lloh22:
	ldr	x9, [x9, _PACKET3_TC_ACTION_ENA@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh24:
	adrp	x9, _PACKET3_SH_KCACHE_ACTION_ENA@GOTPAGE
Lloh25:
	ldr	x9, [x9, _PACKET3_SH_KCACHE_ACTION_ENA@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh27:
	adrp	x9, _PACKET3_SH_ICACHE_ACTION_ENA@GOTPAGE
Lloh28:
	ldr	x9, [x9, _PACKET3_SH_ICACHE_ACTION_ENA@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	orr	w1, w8, w9
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #-1
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #10
	bl	_amdgpu_ring_write
Lloh30:
	adrp	x8, _PACKET3_EVENT_WRITE_EOP@GOTPAGE
Lloh31:
	ldr	x8, [x8, _PACKET3_EVENT_WRITE_EOP@GOTPAGEOFF]
Lloh32:
	ldr	w0, [x8]
	mov	w1, #4
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh33:
	adrp	x8, _CACHE_FLUSH_AND_INV_TS_EVENT@GOTPAGE
Lloh34:
	ldr	x8, [x8, _CACHE_FLUSH_AND_INV_TS_EVENT@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	bl	_EVENT_TYPE
	mov	x23, x0
	mov	w0, #5
	bl	_EVENT_INDEX
	orr	w1, w0, w23
	mov	x0, x19
	bl	_amdgpu_ring_write
	and	w1, w22, #0xfffffffc
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x22
	bl	_upper_32_bits
	and	w8, w0, #0xffff
	tst	w25, w21
	cinc	w9, w26, ne
Lloh36:
	adrp	x10, _CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT@GOTPAGE
Lloh37:
	ldr	x10, [x10, _CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT@GOTPAGEOFF]
Lloh38:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w8, w9, w8
	lsl	w9, w24, #1
Lloh39:
	adrp	x10, _CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT@GOTPAGE
Lloh40:
	ldr	x10, [x10, _CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT@GOTPAGEOFF]
Lloh41:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w1, w8, w9
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x20
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x20
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_amdgpu_ring_write
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_FENCE_FLAG_64BIT,4,2    ; @AMDGPU_FENCE_FLAG_64BIT
	.comm	_AMDGPU_FENCE_FLAG_INT,4,2      ; @AMDGPU_FENCE_FLAG_INT
	.comm	_PACKET3_SET_CONFIG_REG,4,2     ; @PACKET3_SET_CONFIG_REG
	.comm	_mmCP_COHER_CNTL2,4,2           ; @mmCP_COHER_CNTL2
	.comm	_PACKET3_SET_CONFIG_REG_START,4,2 ; @PACKET3_SET_CONFIG_REG_START
	.comm	_PACKET3_SURFACE_SYNC,4,2       ; @PACKET3_SURFACE_SYNC
	.comm	_PACKET3_TCL1_ACTION_ENA,4,2    ; @PACKET3_TCL1_ACTION_ENA
	.comm	_PACKET3_TC_ACTION_ENA,4,2      ; @PACKET3_TC_ACTION_ENA
	.comm	_PACKET3_SH_KCACHE_ACTION_ENA,4,2 ; @PACKET3_SH_KCACHE_ACTION_ENA
	.comm	_PACKET3_SH_ICACHE_ACTION_ENA,4,2 ; @PACKET3_SH_ICACHE_ACTION_ENA
	.comm	_PACKET3_EVENT_WRITE_EOP,4,2    ; @PACKET3_EVENT_WRITE_EOP
	.comm	_CACHE_FLUSH_AND_INV_TS_EVENT,4,2 ; @CACHE_FLUSH_AND_INV_TS_EVENT
	.comm	_CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT,4,2 ; @CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT
	.comm	_CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT,4,2 ; @CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT
	.no_dead_strip	_gfx_v6_0_ring_emit_fence
.subsections_via_symbols
