	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gmc_v7_0_enable_mc_mgcg
_gmc_v7_0_enable_mc_mgcg:               ## @gmc_v7_0_enable_mc_mgcg
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r15d
	movq	%rdi, %r14
	movq	_mc_cg_registers@GOTPCREL(%rip), %r12
	movq	(%r12), %rdi
	callq	_ARRAY_SIZE
	testl	%eax, %eax
	jle	LBB0_9
## %bb.1:
	xorl	%ebx, %ebx
	movq	_mc_cg_en@GOTPCREL(%rip), %r13
	jmp	LBB0_2
	.p2align	4, 0x90
LBB0_8:                                 ##   in Loop: Header=BB0_2 Depth=1
	incq	%rbx
	movq	(%r12), %rdi
	callq	_ARRAY_SIZE
	cltq
	cmpq	%rax, %rbx
	jge	LBB0_9
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	(%r12), %rax
	movl	(%rax,%rbx,4), %edi
	callq	_RREG32
	testl	%r15d, %r15d
	je	LBB0_5
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	_AMD_CG_SUPPORT_MC_MGCG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, (%r14)
	je	LBB0_5
## %bb.4:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	(%r13), %rcx
	movl	(%rcx,%rbx,4), %esi
	orl	%eax, %esi
	cmpl	%eax, %esi
	je	LBB0_8
	jmp	LBB0_7
	.p2align	4, 0x90
LBB0_5:                                 ##   in Loop: Header=BB0_2 Depth=1
	movq	(%r13), %rcx
	movl	(%rcx,%rbx,4), %esi
	notl	%esi
	andl	%eax, %esi
	cmpl	%eax, %esi
	je	LBB0_8
LBB0_7:                                 ##   in Loop: Header=BB0_2 Depth=1
	movq	(%r12), %rax
	movl	(%rax,%rbx,4), %edi
	callq	_WREG32
	jmp	LBB0_8
LBB0_9:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_mc_cg_registers,8,3            ## @mc_cg_registers
	.comm	_AMD_CG_SUPPORT_MC_MGCG,4,2     ## @AMD_CG_SUPPORT_MC_MGCG
	.comm	_mc_cg_en,8,3                   ## @mc_cg_en
	.no_dead_strip	_gmc_v7_0_enable_mc_mgcg
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gmc_v7_0_enable_mc_mgcg
_gmc_v7_0_enable_mc_mgcg:               ; @gmc_v7_0_enable_mc_mgcg
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x1
	mov	x20, x0
Lloh0:
	adrp	x21, _mc_cg_registers@GOTPAGE
Lloh1:
	ldr	x21, [x21, _mc_cg_registers@GOTPAGEOFF]
	ldr	x0, [x21]
	bl	_ARRAY_SIZE
	cmp	w0, #1
	b.lt	LBB0_8
; %bb.1:
	mov	x22, #0
Lloh2:
	adrp	x23, _mc_cg_en@GOTPAGE
Lloh3:
	ldr	x23, [x23, _mc_cg_en@GOTPAGEOFF]
Lloh4:
	adrp	x24, _AMD_CG_SUPPORT_MC_MGCG@GOTPAGE
Lloh5:
	ldr	x24, [x24, _AMD_CG_SUPPORT_MC_MGCG@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:                                 ;   in Loop: Header=BB0_3 Depth=1
	add	x22, x22, #1
	ldr	x0, [x21]
	bl	_ARRAY_SIZE
	cmp	x22, w0, sxtw
	b.ge	LBB0_8
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x21]
	ldr	w0, [x8, x22, lsl #2]
	bl	_RREG32
	cbz	w19, LBB0_6
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	ldr	w8, [x20]
	ldr	w9, [x24]
	tst	w9, w8
	b.eq	LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_3 Depth=1
	ldr	x8, [x23]
	ldr	w8, [x8, x22, lsl #2]
	orr	w1, w8, w0
	cmp	w1, w0
	b.eq	LBB0_2
	b	LBB0_7
LBB0_6:                                 ;   in Loop: Header=BB0_3 Depth=1
	ldr	x8, [x23]
	ldr	w8, [x8, x22, lsl #2]
	bic	w1, w0, w8
	cmp	w1, w0
	b.eq	LBB0_2
LBB0_7:                                 ;   in Loop: Header=BB0_3 Depth=1
	ldr	x8, [x21]
	ldr	w0, [x8, x22, lsl #2]
	bl	_WREG32
	b	LBB0_2
LBB0_8:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.cfi_endproc
                                        ; -- End function
	.comm	_mc_cg_registers,8,3            ; @mc_cg_registers
	.comm	_AMD_CG_SUPPORT_MC_MGCG,4,2     ; @AMD_CG_SUPPORT_MC_MGCG
	.comm	_mc_cg_en,8,3                   ; @mc_cg_en
	.no_dead_strip	_gmc_v7_0_enable_mc_mgcg
.subsections_via_symbols
