	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v2_5_disable_clock_gating
_vcn_v2_5_disable_clock_gating:         ## @vcn_v2_5_disable_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	4(%rdi), %eax
	testl	%eax, %eax
	jle	LBB0_8
## %bb.1:
	movq	%rdi, %r14
	xorl	%r15d, %r15d
	movq	_VCN@GOTPCREL(%rip), %r12
	movq	_mmUVD_CGC_CTRL@GOTPCREL(%rip), %r13
	jmp	LBB0_2
LBB0_5:                                 ##   in Loop: Header=BB0_2 Depth=1
	movq	_UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%ecx, %eax
LBB0_6:                                 ##   in Loop: Header=BB0_2 Depth=1
	movq	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPCREL(%rip), %rcx
	movzbl	(%rcx), %edx
	movq	_UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPCREL(%rip), %rcx
	movzbl	(%rcx), %ecx
	movl	$4, %ebx
	shll	%cl, %ebx
	btsl	%edx, %eax
	orl	%eax, %ebx
	movl	(%r12), %edi
	movl	(%r13), %edx
	movl	%r15d, %esi
	movl	%ebx, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmUVD_CGC_GATE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movl	%r15d, %esi
	callq	_RREG32_SOC15
	movq	_UVD_CGC_GATE__UDEC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	_UVD_CGC_GATE__SYS_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__MPEG2_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__REGS_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__RBC_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__LMI_MC_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__LMI_UMC_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__IDCT_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__MPRD_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__MPC_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__LBSI_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__LRBBM_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__UDEC_RE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__UDEC_CM_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__UDEC_IT_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__UDEC_DB_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__UDEC_MP_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__WCB_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__VCPU_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__MMSCH_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movl	(%r12), %edi
	movl	(%rbx), %edx
	movl	%r15d, %esi
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movl	(%rbx), %edx
	movl	%r15d, %esi
	xorl	%ecx, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_SOC15_WAIT_ON_RREG
	movl	(%r12), %edi
	movl	(%r13), %edx
	movl	%r15d, %esi
	callq	_RREG32_SOC15
	movq	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__SYS_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__REGS_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__RBC_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__MPC_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__WCB_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__MMSCH_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movl	(%r12), %edi
	movl	(%r13), %edx
	movl	%r15d, %esi
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmUVD_SUVD_CGC_GATE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movl	%r15d, %esi
	callq	_RREG32_SOC15
	movq	_UVD_SUVD_CGC_GATE__SRE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SIT_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SMP_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SCM_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SDB_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SRE_H264_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SRE_HEVC_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SIT_H264_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SIT_HEVC_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SCM_H264_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SCM_HEVC_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SDB_H264_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SDB_HEVC_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SCLR_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__UVD_SC_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__ENT_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SITE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SRE_VP9_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SCM_VP9_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SDB_VP9_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__IME_HEVC_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r12), %edi
	movl	(%rbx), %edx
	movl	%r15d, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmUVD_SUVD_CGC_CTRL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movl	%r15d, %esi
	callq	_RREG32_SOC15
	movq	_UVD_SUVD_CGC_CTRL__SIT_MODE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	_UVD_SUVD_CGC_CTRL__SRE_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_SUVD_CGC_CTRL__SMP_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_SUVD_CGC_CTRL__SCM_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_SUVD_CGC_CTRL__SDB_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_SUVD_CGC_CTRL__ENT_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_SUVD_CGC_CTRL__IME_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_SUVD_CGC_CTRL__SITE_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movl	(%r12), %edi
	movl	(%rbx), %edx
	movl	%r15d, %esi
	callq	_WREG32_SOC15
	movl	4(%r14), %eax
LBB0_7:                                 ##   in Loop: Header=BB0_2 Depth=1
	incl	%r15d
	cmpl	%eax, %r15d
	jge	LBB0_8
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movl	8(%r14), %ecx
	btl	%r15d, %ecx
	jb	LBB0_7
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movl	(%r12), %edi
	movl	(%r13), %edx
	movl	%r15d, %esi
	callq	_RREG32_SOC15
	movq	_AMD_CG_SUPPORT_VCN_MGCG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, (%r14)
	je	LBB0_5
## %bb.4:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	_UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPCREL(%rip), %rcx
	movzbl	(%rcx), %ecx
	btsl	%ecx, %eax
	jmp	LBB0_6
LBB0_8:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_VCN,4,2                        ## @VCN
	.comm	_mmUVD_CGC_CTRL,4,2             ## @mmUVD_CGC_CTRL
	.comm	_AMD_CG_SUPPORT_VCN_MGCG,4,2    ## @AMD_CG_SUPPORT_VCN_MGCG
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT,4,2 ## @UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK,4,2 ## @UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK
	.comm	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT,4,2 ## @UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
	.comm	_UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT,4,2 ## @UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT
	.comm	_mmUVD_CGC_GATE,4,2             ## @mmUVD_CGC_GATE
	.comm	_UVD_CGC_GATE__SYS_MASK,4,2     ## @UVD_CGC_GATE__SYS_MASK
	.comm	_UVD_CGC_GATE__UDEC_MASK,4,2    ## @UVD_CGC_GATE__UDEC_MASK
	.comm	_UVD_CGC_GATE__MPEG2_MASK,4,2   ## @UVD_CGC_GATE__MPEG2_MASK
	.comm	_UVD_CGC_GATE__REGS_MASK,4,2    ## @UVD_CGC_GATE__REGS_MASK
	.comm	_UVD_CGC_GATE__RBC_MASK,4,2     ## @UVD_CGC_GATE__RBC_MASK
	.comm	_UVD_CGC_GATE__LMI_MC_MASK,4,2  ## @UVD_CGC_GATE__LMI_MC_MASK
	.comm	_UVD_CGC_GATE__LMI_UMC_MASK,4,2 ## @UVD_CGC_GATE__LMI_UMC_MASK
	.comm	_UVD_CGC_GATE__IDCT_MASK,4,2    ## @UVD_CGC_GATE__IDCT_MASK
	.comm	_UVD_CGC_GATE__MPRD_MASK,4,2    ## @UVD_CGC_GATE__MPRD_MASK
	.comm	_UVD_CGC_GATE__MPC_MASK,4,2     ## @UVD_CGC_GATE__MPC_MASK
	.comm	_UVD_CGC_GATE__LBSI_MASK,4,2    ## @UVD_CGC_GATE__LBSI_MASK
	.comm	_UVD_CGC_GATE__LRBBM_MASK,4,2   ## @UVD_CGC_GATE__LRBBM_MASK
	.comm	_UVD_CGC_GATE__UDEC_RE_MASK,4,2 ## @UVD_CGC_GATE__UDEC_RE_MASK
	.comm	_UVD_CGC_GATE__UDEC_CM_MASK,4,2 ## @UVD_CGC_GATE__UDEC_CM_MASK
	.comm	_UVD_CGC_GATE__UDEC_IT_MASK,4,2 ## @UVD_CGC_GATE__UDEC_IT_MASK
	.comm	_UVD_CGC_GATE__UDEC_DB_MASK,4,2 ## @UVD_CGC_GATE__UDEC_DB_MASK
	.comm	_UVD_CGC_GATE__UDEC_MP_MASK,4,2 ## @UVD_CGC_GATE__UDEC_MP_MASK
	.comm	_UVD_CGC_GATE__WCB_MASK,4,2     ## @UVD_CGC_GATE__WCB_MASK
	.comm	_UVD_CGC_GATE__VCPU_MASK,4,2    ## @UVD_CGC_GATE__VCPU_MASK
	.comm	_UVD_CGC_GATE__MMSCH_MASK,4,2   ## @UVD_CGC_GATE__MMSCH_MASK
	.comm	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_RE_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_CM_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_IT_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_DB_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_MP_MODE_MASK
	.comm	_UVD_CGC_CTRL__SYS_MODE_MASK,4,2 ## @UVD_CGC_CTRL__SYS_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPEG2_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPEG2_MODE_MASK
	.comm	_UVD_CGC_CTRL__REGS_MODE_MASK,4,2 ## @UVD_CGC_CTRL__REGS_MODE_MASK
	.comm	_UVD_CGC_CTRL__RBC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__RBC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_MC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LMI_MC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LMI_UMC_MODE_MASK
	.comm	_UVD_CGC_CTRL__IDCT_MODE_MASK,4,2 ## @UVD_CGC_CTRL__IDCT_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPRD_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPRD_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LBSI_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LBSI_MODE_MASK
	.comm	_UVD_CGC_CTRL__LRBBM_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LRBBM_MODE_MASK
	.comm	_UVD_CGC_CTRL__WCB_MODE_MASK,4,2 ## @UVD_CGC_CTRL__WCB_MODE_MASK
	.comm	_UVD_CGC_CTRL__VCPU_MODE_MASK,4,2 ## @UVD_CGC_CTRL__VCPU_MODE_MASK
	.comm	_UVD_CGC_CTRL__MMSCH_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MMSCH_MODE_MASK
	.comm	_mmUVD_SUVD_CGC_GATE,4,2        ## @mmUVD_SUVD_CGC_GATE
	.comm	_UVD_SUVD_CGC_GATE__SRE_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SRE_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SIT_MASK
	.comm	_UVD_SUVD_CGC_GATE__SMP_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SMP_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SCM_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SDB_MASK
	.comm	_UVD_SUVD_CGC_GATE__SRE_H264_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SRE_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SRE_HEVC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_H264_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SIT_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_HEVC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_H264_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SCM_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_HEVC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_H264_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SDB_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_HEVC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCLR_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SCLR_MASK
	.comm	_UVD_SUVD_CGC_GATE__UVD_SC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__UVD_SC_MASK
	.comm	_UVD_SUVD_CGC_GATE__ENT_MASK,4,2 ## @UVD_SUVD_CGC_GATE__ENT_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SITE_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SITE_MASK
	.comm	_UVD_SUVD_CGC_GATE__SRE_VP9_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SRE_VP9_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_VP9_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SCM_VP9_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_VP9_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SDB_VP9_MASK
	.comm	_UVD_SUVD_CGC_GATE__IME_HEVC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__IME_HEVC_MASK
	.comm	_mmUVD_SUVD_CGC_CTRL,4,2        ## @mmUVD_SUVD_CGC_CTRL
	.comm	_UVD_SUVD_CGC_CTRL__SRE_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SIT_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SMP_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SCM_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SDB_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__ENT_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__IME_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__IME_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SITE_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
	.no_dead_strip	_vcn_v2_5_disable_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v2_5_disable_clock_gating
_vcn_v2_5_disable_clock_gating:         ; @vcn_v2_5_disable_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	ldr	w8, [x0, #4]
	cmp	w8, #1
	b.lt	LBB0_8
; %bb.1:
	mov	x19, x0
	mov	w20, #0
Lloh0:
	adrp	x21, _VCN@GOTPAGE
Lloh1:
	ldr	x21, [x21, _VCN@GOTPAGEOFF]
Lloh2:
	adrp	x22, _mmUVD_CGC_CTRL@GOTPAGE
Lloh3:
	ldr	x22, [x22, _mmUVD_CGC_CTRL@GOTPAGEOFF]
	mov	w26, #1
Lloh4:
	adrp	x24, _mmUVD_CGC_GATE@GOTPAGE
Lloh5:
	ldr	x24, [x24, _mmUVD_CGC_GATE@GOTPAGEOFF]
Lloh6:
	adrp	x23, _mmUVD_SUVD_CGC_GATE@GOTPAGE
Lloh7:
	ldr	x23, [x23, _mmUVD_SUVD_CGC_GATE@GOTPAGEOFF]
Lloh8:
	adrp	x25, _mmUVD_SUVD_CGC_CTRL@GOTPAGE
Lloh9:
	ldr	x25, [x25, _mmUVD_SUVD_CGC_CTRL@GOTPAGEOFF]
Lloh10:
	adrp	x27, _UVD_SUVD_CGC_CTRL__IME_MODE_MASK@GOTPAGE
Lloh11:
	ldr	x27, [x27, _UVD_SUVD_CGC_CTRL__IME_MODE_MASK@GOTPAGEOFF]
Lloh12:
	adrp	x28, _UVD_SUVD_CGC_CTRL__SITE_MODE_MASK@GOTPAGE
Lloh13:
	ldr	x28, [x28, _UVD_SUVD_CGC_CTRL__SITE_MODE_MASK@GOTPAGEOFF]
	b	LBB0_5
LBB0_2:                                 ;   in Loop: Header=BB0_5 Depth=1
Lloh14:
	adrp	x8, _UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPAGE
Lloh15:
	ldr	x8, [x8, _UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
	bic	w8, w0, w8
LBB0_3:                                 ;   in Loop: Header=BB0_5 Depth=1
Lloh17:
	adrp	x9, _UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPAGE
Lloh18:
	ldr	x9, [x9, _UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	lsl	w9, w26, w9
	orr	w8, w9, w8
Lloh20:
	adrp	x9, _UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPAGE
Lloh21:
	ldr	x9, [x9, _UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	mov	w10, #4
	lsl	w9, w10, w9
	orr	w3, w8, w9
	ldr	w0, [x21]
	ldr	w2, [x22]
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w0, [x21]
	ldr	w2, [x24]
	mov	x1, x20
	bl	_RREG32_SOC15
Lloh23:
	adrp	x8, _UVD_CGC_GATE__SYS_MASK@GOTPAGE
Lloh24:
	ldr	x8, [x8, _UVD_CGC_GATE__SYS_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
Lloh26:
	adrp	x9, _UVD_CGC_GATE__UDEC_MASK@GOTPAGE
Lloh27:
	ldr	x9, [x9, _UVD_CGC_GATE__UDEC_MASK@GOTPAGEOFF]
Lloh28:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh29:
	adrp	x9, _UVD_CGC_GATE__MPEG2_MASK@GOTPAGE
Lloh30:
	ldr	x9, [x9, _UVD_CGC_GATE__MPEG2_MASK@GOTPAGEOFF]
Lloh31:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh32:
	adrp	x9, _UVD_CGC_GATE__REGS_MASK@GOTPAGE
Lloh33:
	ldr	x9, [x9, _UVD_CGC_GATE__REGS_MASK@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh35:
	adrp	x9, _UVD_CGC_GATE__RBC_MASK@GOTPAGE
Lloh36:
	ldr	x9, [x9, _UVD_CGC_GATE__RBC_MASK@GOTPAGEOFF]
Lloh37:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh38:
	adrp	x9, _UVD_CGC_GATE__LMI_MC_MASK@GOTPAGE
Lloh39:
	ldr	x9, [x9, _UVD_CGC_GATE__LMI_MC_MASK@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh41:
	adrp	x9, _UVD_CGC_GATE__LMI_UMC_MASK@GOTPAGE
Lloh42:
	ldr	x9, [x9, _UVD_CGC_GATE__LMI_UMC_MASK@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh44:
	adrp	x9, _UVD_CGC_GATE__IDCT_MASK@GOTPAGE
Lloh45:
	ldr	x9, [x9, _UVD_CGC_GATE__IDCT_MASK@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh47:
	adrp	x9, _UVD_CGC_GATE__MPRD_MASK@GOTPAGE
Lloh48:
	ldr	x9, [x9, _UVD_CGC_GATE__MPRD_MASK@GOTPAGEOFF]
Lloh49:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh50:
	adrp	x9, _UVD_CGC_GATE__MPC_MASK@GOTPAGE
Lloh51:
	ldr	x9, [x9, _UVD_CGC_GATE__MPC_MASK@GOTPAGEOFF]
Lloh52:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh53:
	adrp	x9, _UVD_CGC_GATE__LBSI_MASK@GOTPAGE
Lloh54:
	ldr	x9, [x9, _UVD_CGC_GATE__LBSI_MASK@GOTPAGEOFF]
Lloh55:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh56:
	adrp	x9, _UVD_CGC_GATE__LRBBM_MASK@GOTPAGE
Lloh57:
	ldr	x9, [x9, _UVD_CGC_GATE__LRBBM_MASK@GOTPAGEOFF]
Lloh58:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh59:
	adrp	x9, _UVD_CGC_GATE__UDEC_RE_MASK@GOTPAGE
Lloh60:
	ldr	x9, [x9, _UVD_CGC_GATE__UDEC_RE_MASK@GOTPAGEOFF]
Lloh61:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh62:
	adrp	x9, _UVD_CGC_GATE__UDEC_CM_MASK@GOTPAGE
Lloh63:
	ldr	x9, [x9, _UVD_CGC_GATE__UDEC_CM_MASK@GOTPAGEOFF]
Lloh64:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh65:
	adrp	x9, _UVD_CGC_GATE__UDEC_IT_MASK@GOTPAGE
Lloh66:
	ldr	x9, [x9, _UVD_CGC_GATE__UDEC_IT_MASK@GOTPAGEOFF]
Lloh67:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh68:
	adrp	x9, _UVD_CGC_GATE__UDEC_DB_MASK@GOTPAGE
Lloh69:
	ldr	x9, [x9, _UVD_CGC_GATE__UDEC_DB_MASK@GOTPAGEOFF]
Lloh70:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh71:
	adrp	x9, _UVD_CGC_GATE__UDEC_MP_MASK@GOTPAGE
Lloh72:
	ldr	x9, [x9, _UVD_CGC_GATE__UDEC_MP_MASK@GOTPAGEOFF]
Lloh73:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh74:
	adrp	x9, _UVD_CGC_GATE__WCB_MASK@GOTPAGE
Lloh75:
	ldr	x9, [x9, _UVD_CGC_GATE__WCB_MASK@GOTPAGEOFF]
Lloh76:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh77:
	adrp	x9, _UVD_CGC_GATE__VCPU_MASK@GOTPAGE
Lloh78:
	ldr	x9, [x9, _UVD_CGC_GATE__VCPU_MASK@GOTPAGEOFF]
Lloh79:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh80:
	adrp	x9, _UVD_CGC_GATE__MMSCH_MASK@GOTPAGE
Lloh81:
	ldr	x9, [x9, _UVD_CGC_GATE__MMSCH_MASK@GOTPAGEOFF]
Lloh82:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w3, w0, w8
	ldr	w0, [x21]
	ldr	w2, [x24]
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w0, [x21]
	ldr	w2, [x24]
	mov	x1, x20
	mov	w3, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_SOC15_WAIT_ON_RREG
	ldr	w0, [x21]
	ldr	w2, [x22]
	mov	x1, x20
	bl	_RREG32_SOC15
Lloh83:
	adrp	x8, _UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPAGE
Lloh84:
	ldr	x8, [x8, _UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPAGEOFF]
Lloh85:
	ldr	w8, [x8]
Lloh86:
	adrp	x9, _UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPAGE
Lloh87:
	ldr	x9, [x9, _UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPAGEOFF]
Lloh88:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh89:
	adrp	x9, _UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPAGE
Lloh90:
	ldr	x9, [x9, _UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPAGEOFF]
Lloh91:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh92:
	adrp	x9, _UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPAGE
Lloh93:
	ldr	x9, [x9, _UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPAGEOFF]
Lloh94:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh95:
	adrp	x9, _UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPAGE
Lloh96:
	ldr	x9, [x9, _UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPAGEOFF]
Lloh97:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh98:
	adrp	x9, _UVD_CGC_CTRL__SYS_MODE_MASK@GOTPAGE
Lloh99:
	ldr	x9, [x9, _UVD_CGC_CTRL__SYS_MODE_MASK@GOTPAGEOFF]
Lloh100:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh101:
	adrp	x9, _UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPAGE
Lloh102:
	ldr	x9, [x9, _UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPAGEOFF]
Lloh103:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh104:
	adrp	x9, _UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPAGE
Lloh105:
	ldr	x9, [x9, _UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPAGEOFF]
Lloh106:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh107:
	adrp	x9, _UVD_CGC_CTRL__REGS_MODE_MASK@GOTPAGE
Lloh108:
	ldr	x9, [x9, _UVD_CGC_CTRL__REGS_MODE_MASK@GOTPAGEOFF]
Lloh109:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh110:
	adrp	x9, _UVD_CGC_CTRL__RBC_MODE_MASK@GOTPAGE
Lloh111:
	ldr	x9, [x9, _UVD_CGC_CTRL__RBC_MODE_MASK@GOTPAGEOFF]
Lloh112:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh113:
	adrp	x9, _UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPAGE
Lloh114:
	ldr	x9, [x9, _UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPAGEOFF]
Lloh115:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh116:
	adrp	x9, _UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPAGE
Lloh117:
	ldr	x9, [x9, _UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPAGEOFF]
Lloh118:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh119:
	adrp	x9, _UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPAGE
Lloh120:
	ldr	x9, [x9, _UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPAGEOFF]
Lloh121:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh122:
	adrp	x9, _UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPAGE
Lloh123:
	ldr	x9, [x9, _UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPAGEOFF]
Lloh124:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh125:
	adrp	x9, _UVD_CGC_CTRL__MPC_MODE_MASK@GOTPAGE
Lloh126:
	ldr	x9, [x9, _UVD_CGC_CTRL__MPC_MODE_MASK@GOTPAGEOFF]
Lloh127:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh128:
	adrp	x9, _UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPAGE
Lloh129:
	ldr	x9, [x9, _UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPAGEOFF]
Lloh130:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh131:
	adrp	x9, _UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPAGE
Lloh132:
	ldr	x9, [x9, _UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPAGEOFF]
Lloh133:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh134:
	adrp	x9, _UVD_CGC_CTRL__WCB_MODE_MASK@GOTPAGE
Lloh135:
	ldr	x9, [x9, _UVD_CGC_CTRL__WCB_MODE_MASK@GOTPAGEOFF]
Lloh136:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh137:
	adrp	x9, _UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPAGE
Lloh138:
	ldr	x9, [x9, _UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPAGEOFF]
Lloh139:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh140:
	adrp	x9, _UVD_CGC_CTRL__MMSCH_MODE_MASK@GOTPAGE
Lloh141:
	ldr	x9, [x9, _UVD_CGC_CTRL__MMSCH_MODE_MASK@GOTPAGEOFF]
Lloh142:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w3, w0, w8
	ldr	w0, [x21]
	ldr	w2, [x22]
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w0, [x21]
	ldr	w2, [x23]
	mov	x1, x20
	bl	_RREG32_SOC15
Lloh143:
	adrp	x8, _UVD_SUVD_CGC_GATE__SRE_MASK@GOTPAGE
Lloh144:
	ldr	x8, [x8, _UVD_SUVD_CGC_GATE__SRE_MASK@GOTPAGEOFF]
Lloh145:
	ldr	w8, [x8]
Lloh146:
	adrp	x9, _UVD_SUVD_CGC_GATE__SIT_MASK@GOTPAGE
Lloh147:
	ldr	x9, [x9, _UVD_SUVD_CGC_GATE__SIT_MASK@GOTPAGEOFF]
Lloh148:
	ldr	w9, [x9]
	orr	w8, w8, w0
Lloh149:
	adrp	x10, _UVD_SUVD_CGC_GATE__SMP_MASK@GOTPAGE
Lloh150:
	ldr	x10, [x10, _UVD_SUVD_CGC_GATE__SMP_MASK@GOTPAGEOFF]
Lloh151:
	ldr	w10, [x10]
	orr	w8, w8, w9
Lloh152:
	adrp	x9, _UVD_SUVD_CGC_GATE__SCM_MASK@GOTPAGE
Lloh153:
	ldr	x9, [x9, _UVD_SUVD_CGC_GATE__SCM_MASK@GOTPAGEOFF]
Lloh154:
	ldr	w9, [x9]
	orr	w8, w8, w10
Lloh155:
	adrp	x10, _UVD_SUVD_CGC_GATE__SDB_MASK@GOTPAGE
Lloh156:
	ldr	x10, [x10, _UVD_SUVD_CGC_GATE__SDB_MASK@GOTPAGEOFF]
Lloh157:
	ldr	w10, [x10]
	orr	w8, w8, w9
Lloh158:
	adrp	x9, _UVD_SUVD_CGC_GATE__SRE_H264_MASK@GOTPAGE
Lloh159:
	ldr	x9, [x9, _UVD_SUVD_CGC_GATE__SRE_H264_MASK@GOTPAGEOFF]
Lloh160:
	ldr	w9, [x9]
	orr	w8, w8, w10
Lloh161:
	adrp	x10, _UVD_SUVD_CGC_GATE__SRE_HEVC_MASK@GOTPAGE
Lloh162:
	ldr	x10, [x10, _UVD_SUVD_CGC_GATE__SRE_HEVC_MASK@GOTPAGEOFF]
Lloh163:
	ldr	w10, [x10]
	orr	w8, w8, w9
Lloh164:
	adrp	x9, _UVD_SUVD_CGC_GATE__SIT_H264_MASK@GOTPAGE
Lloh165:
	ldr	x9, [x9, _UVD_SUVD_CGC_GATE__SIT_H264_MASK@GOTPAGEOFF]
Lloh166:
	ldr	w9, [x9]
	orr	w8, w8, w10
Lloh167:
	adrp	x10, _UVD_SUVD_CGC_GATE__SIT_HEVC_MASK@GOTPAGE
Lloh168:
	ldr	x10, [x10, _UVD_SUVD_CGC_GATE__SIT_HEVC_MASK@GOTPAGEOFF]
Lloh169:
	ldr	w10, [x10]
	orr	w8, w8, w9
Lloh170:
	adrp	x9, _UVD_SUVD_CGC_GATE__SCM_H264_MASK@GOTPAGE
Lloh171:
	ldr	x9, [x9, _UVD_SUVD_CGC_GATE__SCM_H264_MASK@GOTPAGEOFF]
Lloh172:
	ldr	w9, [x9]
	orr	w8, w8, w10
Lloh173:
	adrp	x10, _UVD_SUVD_CGC_GATE__SCM_HEVC_MASK@GOTPAGE
Lloh174:
	ldr	x10, [x10, _UVD_SUVD_CGC_GATE__SCM_HEVC_MASK@GOTPAGEOFF]
Lloh175:
	ldr	w10, [x10]
	orr	w8, w8, w9
Lloh176:
	adrp	x9, _UVD_SUVD_CGC_GATE__SDB_H264_MASK@GOTPAGE
Lloh177:
	ldr	x9, [x9, _UVD_SUVD_CGC_GATE__SDB_H264_MASK@GOTPAGEOFF]
Lloh178:
	ldr	w9, [x9]
	orr	w8, w8, w10
Lloh179:
	adrp	x10, _UVD_SUVD_CGC_GATE__SDB_HEVC_MASK@GOTPAGE
Lloh180:
	ldr	x10, [x10, _UVD_SUVD_CGC_GATE__SDB_HEVC_MASK@GOTPAGEOFF]
Lloh181:
	ldr	w10, [x10]
	orr	w8, w8, w9
Lloh182:
	adrp	x9, _UVD_SUVD_CGC_GATE__SCLR_MASK@GOTPAGE
Lloh183:
	ldr	x9, [x9, _UVD_SUVD_CGC_GATE__SCLR_MASK@GOTPAGEOFF]
Lloh184:
	ldr	w9, [x9]
	orr	w8, w8, w10
Lloh185:
	adrp	x10, _UVD_SUVD_CGC_GATE__UVD_SC_MASK@GOTPAGE
Lloh186:
	ldr	x10, [x10, _UVD_SUVD_CGC_GATE__UVD_SC_MASK@GOTPAGEOFF]
Lloh187:
	ldr	w10, [x10]
	orr	w8, w8, w9
Lloh188:
	adrp	x9, _UVD_SUVD_CGC_GATE__ENT_MASK@GOTPAGE
Lloh189:
	ldr	x9, [x9, _UVD_SUVD_CGC_GATE__ENT_MASK@GOTPAGEOFF]
Lloh190:
	ldr	w9, [x9]
	orr	w8, w8, w10
Lloh191:
	adrp	x10, _UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK@GOTPAGE
Lloh192:
	ldr	x10, [x10, _UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK@GOTPAGEOFF]
Lloh193:
	ldr	w10, [x10]
	orr	w8, w8, w9
Lloh194:
	adrp	x9, _UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK@GOTPAGE
Lloh195:
	ldr	x9, [x9, _UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK@GOTPAGEOFF]
Lloh196:
	ldr	w9, [x9]
	orr	w8, w8, w10
Lloh197:
	adrp	x10, _UVD_SUVD_CGC_GATE__SITE_MASK@GOTPAGE
Lloh198:
	ldr	x10, [x10, _UVD_SUVD_CGC_GATE__SITE_MASK@GOTPAGEOFF]
Lloh199:
	ldr	w10, [x10]
	orr	w8, w8, w9
Lloh200:
	adrp	x9, _UVD_SUVD_CGC_GATE__SRE_VP9_MASK@GOTPAGE
Lloh201:
	ldr	x9, [x9, _UVD_SUVD_CGC_GATE__SRE_VP9_MASK@GOTPAGEOFF]
Lloh202:
	ldr	w9, [x9]
	orr	w8, w8, w10
Lloh203:
	adrp	x10, _UVD_SUVD_CGC_GATE__SCM_VP9_MASK@GOTPAGE
Lloh204:
	ldr	x10, [x10, _UVD_SUVD_CGC_GATE__SCM_VP9_MASK@GOTPAGEOFF]
Lloh205:
	ldr	w10, [x10]
	orr	w8, w8, w9
Lloh206:
	adrp	x9, _UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK@GOTPAGE
Lloh207:
	ldr	x9, [x9, _UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK@GOTPAGEOFF]
Lloh208:
	ldr	w9, [x9]
	orr	w8, w8, w10
Lloh209:
	adrp	x10, _UVD_SUVD_CGC_GATE__SDB_VP9_MASK@GOTPAGE
Lloh210:
	ldr	x10, [x10, _UVD_SUVD_CGC_GATE__SDB_VP9_MASK@GOTPAGEOFF]
Lloh211:
	ldr	w10, [x10]
	orr	w8, w8, w9
Lloh212:
	adrp	x9, _UVD_SUVD_CGC_GATE__IME_HEVC_MASK@GOTPAGE
Lloh213:
	ldr	x9, [x9, _UVD_SUVD_CGC_GATE__IME_HEVC_MASK@GOTPAGEOFF]
Lloh214:
	ldr	w9, [x9]
	orr	w8, w8, w10
	orr	w3, w8, w9
	ldr	w0, [x21]
	ldr	w2, [x23]
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w0, [x21]
	ldr	w2, [x25]
	mov	x1, x20
	bl	_RREG32_SOC15
Lloh215:
	adrp	x8, _UVD_SUVD_CGC_CTRL__SRE_MODE_MASK@GOTPAGE
Lloh216:
	ldr	x8, [x8, _UVD_SUVD_CGC_CTRL__SRE_MODE_MASK@GOTPAGEOFF]
Lloh217:
	ldr	w8, [x8]
Lloh218:
	adrp	x9, _UVD_SUVD_CGC_CTRL__SIT_MODE_MASK@GOTPAGE
Lloh219:
	ldr	x9, [x9, _UVD_SUVD_CGC_CTRL__SIT_MODE_MASK@GOTPAGEOFF]
Lloh220:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh221:
	adrp	x9, _UVD_SUVD_CGC_CTRL__SMP_MODE_MASK@GOTPAGE
Lloh222:
	ldr	x9, [x9, _UVD_SUVD_CGC_CTRL__SMP_MODE_MASK@GOTPAGEOFF]
Lloh223:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh224:
	adrp	x9, _UVD_SUVD_CGC_CTRL__SCM_MODE_MASK@GOTPAGE
Lloh225:
	ldr	x9, [x9, _UVD_SUVD_CGC_CTRL__SCM_MODE_MASK@GOTPAGEOFF]
Lloh226:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh227:
	adrp	x9, _UVD_SUVD_CGC_CTRL__SDB_MODE_MASK@GOTPAGE
Lloh228:
	ldr	x9, [x9, _UVD_SUVD_CGC_CTRL__SDB_MODE_MASK@GOTPAGEOFF]
Lloh229:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh230:
	adrp	x9, _UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK@GOTPAGE
Lloh231:
	ldr	x9, [x9, _UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK@GOTPAGEOFF]
Lloh232:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh233:
	adrp	x9, _UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK@GOTPAGE
Lloh234:
	ldr	x9, [x9, _UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK@GOTPAGEOFF]
Lloh235:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh236:
	adrp	x9, _UVD_SUVD_CGC_CTRL__ENT_MODE_MASK@GOTPAGE
Lloh237:
	ldr	x9, [x9, _UVD_SUVD_CGC_CTRL__ENT_MODE_MASK@GOTPAGEOFF]
Lloh238:
	ldr	w9, [x9]
	orr	w8, w8, w9
	ldr	w9, [x27]
	orr	w8, w8, w9
	ldr	w9, [x28]
	orr	w8, w8, w9
	bic	w3, w0, w8
	ldr	w0, [x21]
	ldr	w2, [x25]
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w8, [x19, #4]
LBB0_4:                                 ;   in Loop: Header=BB0_5 Depth=1
	add	w20, w20, #1
	cmp	w20, w8
	b.ge	LBB0_8
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w9, [x19, #8]
	lsr	w9, w9, w20
	tbnz	w9, #0, LBB0_4
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	ldr	w0, [x21]
	ldr	w2, [x22]
	mov	x1, x20
	bl	_RREG32_SOC15
	ldr	w8, [x19]
Lloh239:
	adrp	x9, _AMD_CG_SUPPORT_VCN_MGCG@GOTPAGE
Lloh240:
	ldr	x9, [x9, _AMD_CG_SUPPORT_VCN_MGCG@GOTPAGEOFF]
Lloh241:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.7:                                ;   in Loop: Header=BB0_5 Depth=1
Lloh242:
	adrp	x8, _UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPAGE
Lloh243:
	ldr	x8, [x8, _UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPAGEOFF]
Lloh244:
	ldr	w8, [x8]
	lsl	w8, w26, w8
	orr	w8, w8, w0
	b	LBB0_3
LBB0_8:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh236, Lloh237, Lloh238
	.loh AdrpLdrGotLdr	Lloh233, Lloh234, Lloh235
	.loh AdrpLdrGotLdr	Lloh230, Lloh231, Lloh232
	.loh AdrpLdrGotLdr	Lloh227, Lloh228, Lloh229
	.loh AdrpLdrGotLdr	Lloh224, Lloh225, Lloh226
	.loh AdrpLdrGotLdr	Lloh221, Lloh222, Lloh223
	.loh AdrpLdrGotLdr	Lloh218, Lloh219, Lloh220
	.loh AdrpLdrGotLdr	Lloh215, Lloh216, Lloh217
	.loh AdrpLdrGotLdr	Lloh212, Lloh213, Lloh214
	.loh AdrpLdrGotLdr	Lloh209, Lloh210, Lloh211
	.loh AdrpLdrGotLdr	Lloh206, Lloh207, Lloh208
	.loh AdrpLdrGotLdr	Lloh203, Lloh204, Lloh205
	.loh AdrpLdrGotLdr	Lloh200, Lloh201, Lloh202
	.loh AdrpLdrGotLdr	Lloh197, Lloh198, Lloh199
	.loh AdrpLdrGotLdr	Lloh194, Lloh195, Lloh196
	.loh AdrpLdrGotLdr	Lloh191, Lloh192, Lloh193
	.loh AdrpLdrGotLdr	Lloh188, Lloh189, Lloh190
	.loh AdrpLdrGotLdr	Lloh185, Lloh186, Lloh187
	.loh AdrpLdrGotLdr	Lloh182, Lloh183, Lloh184
	.loh AdrpLdrGotLdr	Lloh179, Lloh180, Lloh181
	.loh AdrpLdrGotLdr	Lloh176, Lloh177, Lloh178
	.loh AdrpLdrGotLdr	Lloh173, Lloh174, Lloh175
	.loh AdrpLdrGotLdr	Lloh170, Lloh171, Lloh172
	.loh AdrpLdrGotLdr	Lloh167, Lloh168, Lloh169
	.loh AdrpLdrGotLdr	Lloh164, Lloh165, Lloh166
	.loh AdrpLdrGotLdr	Lloh161, Lloh162, Lloh163
	.loh AdrpLdrGotLdr	Lloh158, Lloh159, Lloh160
	.loh AdrpLdrGotLdr	Lloh155, Lloh156, Lloh157
	.loh AdrpLdrGotLdr	Lloh152, Lloh153, Lloh154
	.loh AdrpLdrGotLdr	Lloh149, Lloh150, Lloh151
	.loh AdrpLdrGotLdr	Lloh146, Lloh147, Lloh148
	.loh AdrpLdrGotLdr	Lloh143, Lloh144, Lloh145
	.loh AdrpLdrGotLdr	Lloh140, Lloh141, Lloh142
	.loh AdrpLdrGotLdr	Lloh137, Lloh138, Lloh139
	.loh AdrpLdrGotLdr	Lloh134, Lloh135, Lloh136
	.loh AdrpLdrGotLdr	Lloh131, Lloh132, Lloh133
	.loh AdrpLdrGotLdr	Lloh128, Lloh129, Lloh130
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh239, Lloh240, Lloh241
	.loh AdrpLdrGotLdr	Lloh242, Lloh243, Lloh244
	.cfi_endproc
                                        ; -- End function
	.comm	_VCN,4,2                        ; @VCN
	.comm	_mmUVD_CGC_CTRL,4,2             ; @mmUVD_CGC_CTRL
	.comm	_AMD_CG_SUPPORT_VCN_MGCG,4,2    ; @AMD_CG_SUPPORT_VCN_MGCG
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT,4,2 ; @UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK,4,2 ; @UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK
	.comm	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT,4,2 ; @UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
	.comm	_UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT,4,2 ; @UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT
	.comm	_mmUVD_CGC_GATE,4,2             ; @mmUVD_CGC_GATE
	.comm	_UVD_CGC_GATE__SYS_MASK,4,2     ; @UVD_CGC_GATE__SYS_MASK
	.comm	_UVD_CGC_GATE__UDEC_MASK,4,2    ; @UVD_CGC_GATE__UDEC_MASK
	.comm	_UVD_CGC_GATE__MPEG2_MASK,4,2   ; @UVD_CGC_GATE__MPEG2_MASK
	.comm	_UVD_CGC_GATE__REGS_MASK,4,2    ; @UVD_CGC_GATE__REGS_MASK
	.comm	_UVD_CGC_GATE__RBC_MASK,4,2     ; @UVD_CGC_GATE__RBC_MASK
	.comm	_UVD_CGC_GATE__LMI_MC_MASK,4,2  ; @UVD_CGC_GATE__LMI_MC_MASK
	.comm	_UVD_CGC_GATE__LMI_UMC_MASK,4,2 ; @UVD_CGC_GATE__LMI_UMC_MASK
	.comm	_UVD_CGC_GATE__IDCT_MASK,4,2    ; @UVD_CGC_GATE__IDCT_MASK
	.comm	_UVD_CGC_GATE__MPRD_MASK,4,2    ; @UVD_CGC_GATE__MPRD_MASK
	.comm	_UVD_CGC_GATE__MPC_MASK,4,2     ; @UVD_CGC_GATE__MPC_MASK
	.comm	_UVD_CGC_GATE__LBSI_MASK,4,2    ; @UVD_CGC_GATE__LBSI_MASK
	.comm	_UVD_CGC_GATE__LRBBM_MASK,4,2   ; @UVD_CGC_GATE__LRBBM_MASK
	.comm	_UVD_CGC_GATE__UDEC_RE_MASK,4,2 ; @UVD_CGC_GATE__UDEC_RE_MASK
	.comm	_UVD_CGC_GATE__UDEC_CM_MASK,4,2 ; @UVD_CGC_GATE__UDEC_CM_MASK
	.comm	_UVD_CGC_GATE__UDEC_IT_MASK,4,2 ; @UVD_CGC_GATE__UDEC_IT_MASK
	.comm	_UVD_CGC_GATE__UDEC_DB_MASK,4,2 ; @UVD_CGC_GATE__UDEC_DB_MASK
	.comm	_UVD_CGC_GATE__UDEC_MP_MASK,4,2 ; @UVD_CGC_GATE__UDEC_MP_MASK
	.comm	_UVD_CGC_GATE__WCB_MASK,4,2     ; @UVD_CGC_GATE__WCB_MASK
	.comm	_UVD_CGC_GATE__VCPU_MASK,4,2    ; @UVD_CGC_GATE__VCPU_MASK
	.comm	_UVD_CGC_GATE__MMSCH_MASK,4,2   ; @UVD_CGC_GATE__MMSCH_MASK
	.comm	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_RE_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_CM_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_IT_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_DB_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_MP_MODE_MASK
	.comm	_UVD_CGC_CTRL__SYS_MODE_MASK,4,2 ; @UVD_CGC_CTRL__SYS_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPEG2_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPEG2_MODE_MASK
	.comm	_UVD_CGC_CTRL__REGS_MODE_MASK,4,2 ; @UVD_CGC_CTRL__REGS_MODE_MASK
	.comm	_UVD_CGC_CTRL__RBC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__RBC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_MC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LMI_MC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LMI_UMC_MODE_MASK
	.comm	_UVD_CGC_CTRL__IDCT_MODE_MASK,4,2 ; @UVD_CGC_CTRL__IDCT_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPRD_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPRD_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LBSI_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LBSI_MODE_MASK
	.comm	_UVD_CGC_CTRL__LRBBM_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LRBBM_MODE_MASK
	.comm	_UVD_CGC_CTRL__WCB_MODE_MASK,4,2 ; @UVD_CGC_CTRL__WCB_MODE_MASK
	.comm	_UVD_CGC_CTRL__VCPU_MODE_MASK,4,2 ; @UVD_CGC_CTRL__VCPU_MODE_MASK
	.comm	_UVD_CGC_CTRL__MMSCH_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MMSCH_MODE_MASK
	.comm	_mmUVD_SUVD_CGC_GATE,4,2        ; @mmUVD_SUVD_CGC_GATE
	.comm	_UVD_SUVD_CGC_GATE__SRE_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SRE_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SIT_MASK
	.comm	_UVD_SUVD_CGC_GATE__SMP_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SMP_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SCM_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SDB_MASK
	.comm	_UVD_SUVD_CGC_GATE__SRE_H264_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SRE_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SRE_HEVC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_H264_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SIT_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_HEVC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_H264_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SCM_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_HEVC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_H264_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SDB_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_HEVC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCLR_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SCLR_MASK
	.comm	_UVD_SUVD_CGC_GATE__UVD_SC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__UVD_SC_MASK
	.comm	_UVD_SUVD_CGC_GATE__ENT_MASK,4,2 ; @UVD_SUVD_CGC_GATE__ENT_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SITE_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SITE_MASK
	.comm	_UVD_SUVD_CGC_GATE__SRE_VP9_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SRE_VP9_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_VP9_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SCM_VP9_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_VP9_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SDB_VP9_MASK
	.comm	_UVD_SUVD_CGC_GATE__IME_HEVC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__IME_HEVC_MASK
	.comm	_mmUVD_SUVD_CGC_CTRL,4,2        ; @mmUVD_SUVD_CGC_CTRL
	.comm	_UVD_SUVD_CGC_CTRL__SRE_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SIT_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SMP_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SCM_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SDB_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__ENT_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__IME_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__IME_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SITE_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
	.no_dead_strip	_vcn_v2_5_disable_clock_gating
.subsections_via_symbols
