	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function uvd_v5_0_enable_mgcg
_uvd_v5_0_enable_mgcg:                  ## @uvd_v5_0_enable_mgcg
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	testl	%esi, %esi
	je	LBB0_3
## %bb.1:
	movq	_AMD_CG_SUPPORT_UVD_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rdi)
	je	LBB0_3
## %bb.2:
	movq	_ixUVD_CGC_MEM_CTRL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_UVD_CTX
	orl	$4095, %eax                     ## imm = 0xFFF
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_UVD_CTX
	movq	_mmUVD_CGC_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	%eax, %esi
	cmpl	%esi, %eax
	je	LBB0_5
LBB0_6:
	movq	_mmUVD_CGC_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
LBB0_3:
	movq	_ixUVD_CGC_MEM_CTRL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_UVD_CTX
	andl	$-4096, %eax                    ## imm = 0xF000
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_UVD_CTX
	movq	_mmUVD_CGC_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	cmpl	%esi, %eax
	jne	LBB0_6
LBB0_5:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_CG_SUPPORT_UVD_MGCG,4,2    ## @AMD_CG_SUPPORT_UVD_MGCG
	.comm	_ixUVD_CGC_MEM_CTRL,4,2         ## @ixUVD_CGC_MEM_CTRL
	.comm	_mmUVD_CGC_CTRL,4,2             ## @mmUVD_CGC_CTRL
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK,4,2 ## @UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK
	.no_dead_strip	_uvd_v5_0_enable_mgcg
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function uvd_v5_0_enable_mgcg
_uvd_v5_0_enable_mgcg:                  ; @uvd_v5_0_enable_mgcg
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	cbz	w1, LBB0_4
; %bb.1:
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _AMD_CG_SUPPORT_UVD_MGCG@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_CG_SUPPORT_UVD_MGCG@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_4
; %bb.2:
Lloh3:
	adrp	x19, _ixUVD_CGC_MEM_CTRL@GOTPAGE
Lloh4:
	ldr	x19, [x19, _ixUVD_CGC_MEM_CTRL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_UVD_CTX
	orr	w1, w0, #0xfff
	ldr	w0, [x19]
	bl	_WREG32_UVD_CTX
Lloh5:
	adrp	x8, _mmUVD_CGC_CTRL@GOTPAGE
Lloh6:
	ldr	x8, [x8, _mmUVD_CGC_CTRL@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
	bl	_RREG32
Lloh8:
	adrp	x8, _UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPAGE
Lloh9:
	ldr	x8, [x8, _UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	orr	w1, w8, w0
	cmp	w0, w1
	b.eq	LBB0_5
LBB0_3:
Lloh11:
	adrp	x8, _mmUVD_CGC_CTRL@GOTPAGE
Lloh12:
	ldr	x8, [x8, _mmUVD_CGC_CTRL@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_WREG32
LBB0_4:
Lloh14:
	adrp	x19, _ixUVD_CGC_MEM_CTRL@GOTPAGE
Lloh15:
	ldr	x19, [x19, _ixUVD_CGC_MEM_CTRL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_UVD_CTX
	and	w1, w0, #0xfffff000
	ldr	w0, [x19]
	bl	_WREG32_UVD_CTX
Lloh16:
	adrp	x8, _mmUVD_CGC_CTRL@GOTPAGE
Lloh17:
	ldr	x8, [x8, _mmUVD_CGC_CTRL@GOTPAGEOFF]
Lloh18:
	ldr	w0, [x8]
	bl	_RREG32
Lloh19:
	adrp	x8, _UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPAGE
Lloh20:
	ldr	x8, [x8, _UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
	bic	w1, w0, w8
	cmp	w0, w1
	b.ne	LBB0_3
LBB0_5:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_CG_SUPPORT_UVD_MGCG,4,2    ; @AMD_CG_SUPPORT_UVD_MGCG
	.comm	_ixUVD_CGC_MEM_CTRL,4,2         ; @ixUVD_CGC_MEM_CTRL
	.comm	_mmUVD_CGC_CTRL,4,2             ; @mmUVD_CGC_CTRL
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK,4,2 ; @UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK
	.no_dead_strip	_uvd_v5_0_enable_mgcg
.subsections_via_symbols
