	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_sor_dp_train_fast
_tegra_sor_dp_train_fast:               ## @tegra_sor_dp_train_fast
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, -48(%rbp)                 ## 8-byte Spill
	movq	%rdi, %r15
	movl	$64, %edi
	callq	_SOR_LANE_DRIVE_CURRENT_LANE3
	movl	%eax, %r12d
	movl	$64, %edi
	callq	_SOR_LANE_DRIVE_CURRENT_LANE2
	orl	%eax, %r12d
	movl	$64, %edi
	callq	_SOR_LANE_DRIVE_CURRENT_LANE1
	movl	%eax, %ebx
	movl	$64, %edi
	callq	_SOR_LANE_DRIVE_CURRENT_LANE0
	orl	%eax, %ebx
	orl	%r12d, %ebx
	movq	_SOR_LANE_DRIVE_CURRENT0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_tegra_sor_writel
	movl	$15, %edi
	callq	_SOR_LANE_PREEMPHASIS_LANE3
	movl	%eax, %r12d
	movl	$15, %edi
	callq	_SOR_LANE_PREEMPHASIS_LANE2
	orl	%eax, %r12d
	movl	$15, %edi
	callq	_SOR_LANE_PREEMPHASIS_LANE1
	movl	%eax, %ebx
	movl	$15, %edi
	callq	_SOR_LANE_PREEMPHASIS_LANE0
	orl	%eax, %ebx
	orl	%r12d, %ebx
	movq	_SOR_LANE_PREEMPHASIS0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_tegra_sor_writel
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	_SOR_LANE_POSTCURSOR_LANE3
	movl	%eax, %r12d
	xorl	%edi, %edi
	callq	_SOR_LANE_POSTCURSOR_LANE2
	orl	%eax, %r12d
	xorl	%edi, %edi
	callq	_SOR_LANE_POSTCURSOR_LANE1
	movl	%eax, %r13d
	xorl	%edi, %edi
	callq	_SOR_LANE_POSTCURSOR_LANE0
	orl	%eax, %r13d
	orl	%r12d, %r13d
	movq	_SOR_LANE_POSTCURSOR0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%r13d, %esi
	callq	_tegra_sor_writel
	movq	_SOR_LVDS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_tegra_sor_writel
	movq	8(%r15), %rax
	movq	(%rax), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_DP_PADCTL_TX_PU_ENABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_SOR_DP_PADCTL_TX_PU_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r12d
	notl	%r12d
	andl	%eax, %r12d
	movl	$2, %edi
	callq	_SOR_DP_PADCTL_TX_PU
	orl	%eax, %r12d
	movq	8(%r15), %rax
	movq	(%rax), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%r12d, %esi
	callq	_tegra_sor_writel
	movq	8(%r15), %rax
	movq	(%rax), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_DP_PADCTL_CM_TXD_3@GOTPCREL(%rip), %r13
	movq	_SOR_DP_PADCTL_CM_TXD_2@GOTPCREL(%rip), %r12
	movq	_SOR_DP_PADCTL_CM_TXD_1@GOTPCREL(%rip), %r14
	movq	_SOR_DP_PADCTL_CM_TXD_0@GOTPCREL(%rip), %rcx
	orl	(%r13), %eax
	orl	(%r12), %eax
	orl	(%r14), %eax
	orl	(%rcx), %eax
	movq	8(%r15), %rcx
	movq	(%rcx), %rcx
	movl	(%rcx), %edx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_tegra_sor_writel
	movl	$10, %edi
	movl	$100, %esi
	callq	_usleep_range
	movq	8(%r15), %rax
	movq	(%rax), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movl	(%r12), %esi
	orl	(%r13), %esi
	orl	(%r14), %esi
	movq	_SOR_DP_PADCTL_CM_TXD_0@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	8(%r15), %rax
	movq	(%rax), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_tegra_sor_writel
	movl	(%r15), %edi
	movq	_DP_SET_ANSI_8B10B@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_drm_dp_aux_prepare
	testl	%eax, %eax
	js	LBB0_30
## %bb.1:
	movq	-48(%rbp), %r14                 ## 8-byte Reload
	movl	(%r14), %edx
	testl	%edx, %edx
	je	LBB0_9
## %bb.2:
	movq	_SOR_DP_TPG_CHANNEL_CODING@GOTPCREL(%rip), %rcx
	movq	_SOR_DP_TPG_SCRAMBLER_NONE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	(%rcx), %eax
	movq	_SOR_DP_TPG_PATTERN_TRAIN1@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	leal	-1(%rdx), %esi
	movl	%edx, %ecx
	andl	$7, %ecx
	cmpl	$7, %esi
	jae	LBB0_4
## %bb.3:
	xorl	%ebx, %ebx
	testl	%ecx, %ecx
	jne	LBB0_8
	jmp	LBB0_9
LBB0_4:
	andl	$-8, %edx
	.p2align	4, 0x90
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	addl	$-8, %edx
	jne	LBB0_5
## %bb.6:
	movl	%eax, %edx
	shll	$16, %edx
	movl	%eax, %ebx
	shll	$8, %ebx
	orl	%edx, %ebx
	orl	%eax, %ebx
	shll	$8, %ebx
	orl	%eax, %ebx
	testl	%ecx, %ecx
	je	LBB0_9
	.p2align	4, 0x90
LBB0_8:                                 ## =>This Inner Loop Header: Depth=1
	shll	$8, %ebx
	orl	%eax, %ebx
	decl	%ecx
	jne	LBB0_8
LBB0_9:
	movq	_SOR_DP_TPG@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_tegra_sor_writel
	movq	_DP_TRAINING_PATTERN_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r15), %edi
	movq	%r14, %rsi
	callq	_drm_dp_aux_train
	testl	%eax, %eax
	js	LBB0_30
## %bb.10:
	movq	_SOR_DP_SPARE0@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_DP_SPARE_SEQ_ENABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_SOR_DP_SPARE_PANEL_INTERNAL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_SOR_DP_SPARE_MACRO_SOR_CLK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	(%rbx), %edx
	movq	%r15, %rdi
	callq	_tegra_sor_writel
	movl	(%r14), %edx
	testl	%edx, %edx
	je	LBB0_11
## %bb.12:
	movq	_SOR_DP_TPG_CHANNEL_CODING@GOTPCREL(%rip), %rcx
	movq	_SOR_DP_TPG_SCRAMBLER_NONE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	(%rcx), %eax
	movq	_SOR_DP_TPG_PATTERN_TRAIN2@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	leal	-1(%rdx), %esi
	movl	%edx, %ecx
	andl	$7, %ecx
	cmpl	$7, %esi
	jae	LBB0_14
## %bb.13:
	xorl	%esi, %esi
	testl	%ecx, %ecx
	jne	LBB0_18
	jmp	LBB0_19
LBB0_11:
	xorl	%esi, %esi
	jmp	LBB0_19
LBB0_14:
	andl	$-8, %edx
	.p2align	4, 0x90
LBB0_15:                                ## =>This Inner Loop Header: Depth=1
	addl	$-8, %edx
	jne	LBB0_15
## %bb.16:
	movl	%eax, %edx
	shll	$16, %edx
	movl	%eax, %esi
	shll	$8, %esi
	orl	%edx, %esi
	orl	%eax, %esi
	shll	$8, %esi
	orl	%eax, %esi
	testl	%ecx, %ecx
	je	LBB0_19
	.p2align	4, 0x90
LBB0_18:                                ## =>This Inner Loop Header: Depth=1
	shll	$8, %esi
	orl	%eax, %esi
	decl	%ecx
	jne	LBB0_18
LBB0_19:
	movl	(%r12), %edx
	movq	%r15, %rdi
	callq	_tegra_sor_writel
	movq	_DP_LINK_SCRAMBLING_DISABLE@GOTPCREL(%rip), %rax
	movq	_DP_TRAINING_PATTERN_2@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movl	(%r15), %edi
	movq	%r14, %rsi
	callq	_drm_dp_aux_train
	testl	%eax, %eax
	js	LBB0_30
## %bb.20:
	movl	(%r14), %edx
	testl	%edx, %edx
	je	LBB0_21
## %bb.22:
	movq	_SOR_DP_TPG_CHANNEL_CODING@GOTPCREL(%rip), %rcx
	movq	_SOR_DP_TPG_SCRAMBLER_GALIOS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	(%rcx), %eax
	movq	_SOR_DP_TPG_PATTERN_NONE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	leal	-1(%rdx), %esi
	movl	%edx, %ecx
	andl	$7, %ecx
	cmpl	$7, %esi
	jae	LBB0_24
## %bb.23:
	xorl	%esi, %esi
	testl	%ecx, %ecx
	jne	LBB0_28
	jmp	LBB0_29
LBB0_21:
	xorl	%esi, %esi
	jmp	LBB0_29
LBB0_24:
	andl	$-8, %edx
	.p2align	4, 0x90
LBB0_25:                                ## =>This Inner Loop Header: Depth=1
	addl	$-8, %edx
	jne	LBB0_25
## %bb.26:
	movl	%eax, %edx
	shll	$16, %edx
	movl	%eax, %esi
	shll	$8, %esi
	orl	%edx, %esi
	orl	%eax, %esi
	shll	$8, %esi
	orl	%eax, %esi
	testl	%ecx, %ecx
	je	LBB0_29
	.p2align	4, 0x90
LBB0_28:                                ## =>This Inner Loop Header: Depth=1
	shll	$8, %esi
	orl	%eax, %esi
	decl	%ecx
	jne	LBB0_28
LBB0_29:
	movl	(%r12), %edx
	movq	%r15, %rdi
	callq	_tegra_sor_writel
	movq	_DP_TRAINING_PATTERN_DISABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r15), %edi
	movq	%r14, %rsi
	callq	_drm_dp_aux_train
	movl	%eax, %ecx
	sarl	$31, %ecx
	andl	%ecx, %eax
LBB0_30:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_SOR_LANE_DRIVE_CURRENT0,4,2    ## @SOR_LANE_DRIVE_CURRENT0
	.comm	_SOR_LANE_PREEMPHASIS0,4,2      ## @SOR_LANE_PREEMPHASIS0
	.comm	_SOR_LANE_POSTCURSOR0,4,2       ## @SOR_LANE_POSTCURSOR0
	.comm	_SOR_LVDS,4,2                   ## @SOR_LVDS
	.comm	_SOR_DP_PADCTL_TX_PU_ENABLE,4,2 ## @SOR_DP_PADCTL_TX_PU_ENABLE
	.comm	_SOR_DP_PADCTL_TX_PU_MASK,4,2   ## @SOR_DP_PADCTL_TX_PU_MASK
	.comm	_SOR_DP_PADCTL_CM_TXD_3,4,2     ## @SOR_DP_PADCTL_CM_TXD_3
	.comm	_SOR_DP_PADCTL_CM_TXD_2,4,2     ## @SOR_DP_PADCTL_CM_TXD_2
	.comm	_SOR_DP_PADCTL_CM_TXD_1,4,2     ## @SOR_DP_PADCTL_CM_TXD_1
	.comm	_SOR_DP_PADCTL_CM_TXD_0,4,2     ## @SOR_DP_PADCTL_CM_TXD_0
	.comm	_DP_SET_ANSI_8B10B,4,2          ## @DP_SET_ANSI_8B10B
	.comm	_SOR_DP_TPG_CHANNEL_CODING,8,3  ## @SOR_DP_TPG_CHANNEL_CODING
	.comm	_SOR_DP_TPG_SCRAMBLER_NONE,8,3  ## @SOR_DP_TPG_SCRAMBLER_NONE
	.comm	_SOR_DP_TPG_PATTERN_TRAIN1,8,3  ## @SOR_DP_TPG_PATTERN_TRAIN1
	.comm	_SOR_DP_TPG,4,2                 ## @SOR_DP_TPG
	.comm	_DP_TRAINING_PATTERN_1,4,2      ## @DP_TRAINING_PATTERN_1
	.comm	_SOR_DP_SPARE0,4,2              ## @SOR_DP_SPARE0
	.comm	_SOR_DP_SPARE_SEQ_ENABLE,4,2    ## @SOR_DP_SPARE_SEQ_ENABLE
	.comm	_SOR_DP_SPARE_PANEL_INTERNAL,4,2 ## @SOR_DP_SPARE_PANEL_INTERNAL
	.comm	_SOR_DP_SPARE_MACRO_SOR_CLK,4,2 ## @SOR_DP_SPARE_MACRO_SOR_CLK
	.comm	_SOR_DP_TPG_PATTERN_TRAIN2,8,3  ## @SOR_DP_TPG_PATTERN_TRAIN2
	.comm	_DP_LINK_SCRAMBLING_DISABLE,4,2 ## @DP_LINK_SCRAMBLING_DISABLE
	.comm	_DP_TRAINING_PATTERN_2,4,2      ## @DP_TRAINING_PATTERN_2
	.comm	_SOR_DP_TPG_SCRAMBLER_GALIOS,8,3 ## @SOR_DP_TPG_SCRAMBLER_GALIOS
	.comm	_SOR_DP_TPG_PATTERN_NONE,8,3    ## @SOR_DP_TPG_PATTERN_NONE
	.comm	_DP_TRAINING_PATTERN_DISABLE,4,2 ## @DP_TRAINING_PATTERN_DISABLE
	.no_dead_strip	_tegra_sor_dp_train_fast
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_sor_dp_train_fast
_tegra_sor_dp_train_fast:               ; @tegra_sor_dp_train_fast
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x1
	mov	x20, x0
	mov	w0, #64
	bl	_SOR_LANE_DRIVE_CURRENT_LANE3
	mov	x21, x0
	mov	w0, #64
	bl	_SOR_LANE_DRIVE_CURRENT_LANE2
	orr	w21, w0, w21
	mov	w0, #64
	bl	_SOR_LANE_DRIVE_CURRENT_LANE1
	orr	w21, w21, w0
	mov	w0, #64
	bl	_SOR_LANE_DRIVE_CURRENT_LANE0
	orr	w1, w21, w0
Lloh0:
	adrp	x8, _SOR_LANE_DRIVE_CURRENT0@GOTPAGE
Lloh1:
	ldr	x8, [x8, _SOR_LANE_DRIVE_CURRENT0@GOTPAGEOFF]
Lloh2:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_tegra_sor_writel
	mov	w0, #15
	bl	_SOR_LANE_PREEMPHASIS_LANE3
	mov	x21, x0
	mov	w0, #15
	bl	_SOR_LANE_PREEMPHASIS_LANE2
	orr	w21, w0, w21
	mov	w0, #15
	bl	_SOR_LANE_PREEMPHASIS_LANE1
	orr	w21, w21, w0
	mov	w0, #15
	bl	_SOR_LANE_PREEMPHASIS_LANE0
	orr	w1, w21, w0
Lloh3:
	adrp	x8, _SOR_LANE_PREEMPHASIS0@GOTPAGE
Lloh4:
	ldr	x8, [x8, _SOR_LANE_PREEMPHASIS0@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_tegra_sor_writel
	mov	w0, #0
	bl	_SOR_LANE_POSTCURSOR_LANE3
	mov	x21, x0
	mov	w0, #0
	bl	_SOR_LANE_POSTCURSOR_LANE2
	orr	w21, w0, w21
	mov	w0, #0
	bl	_SOR_LANE_POSTCURSOR_LANE1
	orr	w21, w21, w0
	mov	w0, #0
	bl	_SOR_LANE_POSTCURSOR_LANE0
	orr	w1, w21, w0
Lloh6:
	adrp	x8, _SOR_LANE_POSTCURSOR0@GOTPAGE
Lloh7:
	ldr	x8, [x8, _SOR_LANE_POSTCURSOR0@GOTPAGEOFF]
Lloh8:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_tegra_sor_writel
Lloh9:
	adrp	x8, _SOR_LVDS@GOTPAGE
Lloh10:
	ldr	x8, [x8, _SOR_LVDS@GOTPAGEOFF]
Lloh11:
	ldr	w2, [x8]
	mov	x0, x20
	mov	w1, #0
	bl	_tegra_sor_writel
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w1, [x8]
	mov	x0, x20
	bl	_tegra_sor_readl
Lloh12:
	adrp	x8, _SOR_DP_PADCTL_TX_PU_ENABLE@GOTPAGE
Lloh13:
	ldr	x8, [x8, _SOR_DP_PADCTL_TX_PU_ENABLE@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh15:
	adrp	x9, _SOR_DP_PADCTL_TX_PU_MASK@GOTPAGE
Lloh16:
	ldr	x9, [x9, _SOR_DP_PADCTL_TX_PU_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	bic	w21, w8, w9
	mov	w0, #2
	bl	_SOR_DP_PADCTL_TX_PU
	orr	w1, w21, w0
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w2, [x8]
	mov	x0, x20
	bl	_tegra_sor_writel
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w1, [x8]
	mov	x0, x20
	bl	_tegra_sor_readl
Lloh18:
	adrp	x21, _SOR_DP_PADCTL_CM_TXD_3@GOTPAGE
Lloh19:
	ldr	x21, [x21, _SOR_DP_PADCTL_CM_TXD_3@GOTPAGEOFF]
	ldr	w8, [x21]
Lloh20:
	adrp	x22, _SOR_DP_PADCTL_CM_TXD_2@GOTPAGE
Lloh21:
	ldr	x22, [x22, _SOR_DP_PADCTL_CM_TXD_2@GOTPAGEOFF]
Lloh22:
	adrp	x23, _SOR_DP_PADCTL_CM_TXD_1@GOTPAGE
Lloh23:
	ldr	x23, [x23, _SOR_DP_PADCTL_CM_TXD_1@GOTPAGEOFF]
	ldr	w9, [x22]
	ldr	w10, [x23]
Lloh24:
	adrp	x24, _SOR_DP_PADCTL_CM_TXD_0@GOTPAGE
Lloh25:
	ldr	x24, [x24, _SOR_DP_PADCTL_CM_TXD_0@GOTPAGEOFF]
	ldr	w11, [x24]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w1, w8, w11
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w2, [x8]
	mov	x0, x20
	bl	_tegra_sor_writel
	mov	w0, #10
	mov	w1, #100
	bl	_usleep_range
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w1, [x8]
	mov	x0, x20
	bl	_tegra_sor_readl
	ldr	w8, [x21]
	ldr	w9, [x22]
	orr	w8, w9, w8
	ldr	w9, [x23]
	orr	w8, w8, w9
	ldr	w9, [x24]
	orr	w8, w8, w9
	bic	w1, w0, w8
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w2, [x8]
	mov	x0, x20
	bl	_tegra_sor_writel
	ldr	w0, [x20]
Lloh26:
	adrp	x8, _DP_SET_ANSI_8B10B@GOTPAGE
Lloh27:
	ldr	x8, [x8, _DP_SET_ANSI_8B10B@GOTPAGEOFF]
Lloh28:
	ldr	w1, [x8]
	bl	_drm_dp_aux_prepare
	tbnz	w0, #31, LBB0_15
; %bb.1:
	ldr	w8, [x19]
Lloh29:
	adrp	x21, _SOR_DP_TPG_CHANNEL_CODING@GOTPAGE
Lloh30:
	ldr	x21, [x21, _SOR_DP_TPG_CHANNEL_CODING@GOTPAGEOFF]
Lloh31:
	adrp	x23, _SOR_DP_TPG_SCRAMBLER_NONE@GOTPAGE
Lloh32:
	ldr	x23, [x23, _SOR_DP_TPG_SCRAMBLER_NONE@GOTPAGEOFF]
	mov	w1, #0
	cbz	w8, LBB0_4
; %bb.2:
	ldr	w9, [x21]
	ldr	w10, [x23]
	orr	w9, w10, w9
Lloh33:
	adrp	x10, _SOR_DP_TPG_PATTERN_TRAIN1@GOTPAGE
Lloh34:
	ldr	x10, [x10, _SOR_DP_TPG_PATTERN_TRAIN1@GOTPAGEOFF]
Lloh35:
	ldr	w10, [x10]
	orr	w9, w9, w10
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	orr	w1, w9, w1, lsl #8
	subs	w8, w8, #1
	b.ne	LBB0_3
LBB0_4:
Lloh36:
	adrp	x22, _SOR_DP_TPG@GOTPAGE
Lloh37:
	ldr	x22, [x22, _SOR_DP_TPG@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	x0, x20
	bl	_tegra_sor_writel
Lloh38:
	adrp	x8, _DP_TRAINING_PATTERN_1@GOTPAGE
Lloh39:
	ldr	x8, [x8, _DP_TRAINING_PATTERN_1@GOTPAGEOFF]
Lloh40:
	ldr	w2, [x8]
	ldr	w0, [x20]
	mov	x1, x19
	bl	_drm_dp_aux_train
	tbnz	w0, #31, LBB0_15
; %bb.5:
Lloh41:
	adrp	x24, _SOR_DP_SPARE0@GOTPAGE
Lloh42:
	ldr	x24, [x24, _SOR_DP_SPARE0@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	x0, x20
	bl	_tegra_sor_readl
Lloh43:
	adrp	x8, _SOR_DP_SPARE_SEQ_ENABLE@GOTPAGE
Lloh44:
	ldr	x8, [x8, _SOR_DP_SPARE_SEQ_ENABLE@GOTPAGEOFF]
Lloh45:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh46:
	adrp	x9, _SOR_DP_SPARE_PANEL_INTERNAL@GOTPAGE
Lloh47:
	ldr	x9, [x9, _SOR_DP_SPARE_PANEL_INTERNAL@GOTPAGEOFF]
Lloh48:
	ldr	w9, [x9]
	bic	w8, w8, w9
Lloh49:
	adrp	x9, _SOR_DP_SPARE_MACRO_SOR_CLK@GOTPAGE
Lloh50:
	ldr	x9, [x9, _SOR_DP_SPARE_MACRO_SOR_CLK@GOTPAGEOFF]
Lloh51:
	ldr	w9, [x9]
	orr	w1, w8, w9
	ldr	w2, [x24]
	mov	x0, x20
	bl	_tegra_sor_writel
	ldr	w8, [x19]
	cbz	w8, LBB0_8
; %bb.6:
	mov	w1, #0
	ldr	w9, [x21]
	ldr	w10, [x23]
	orr	w9, w10, w9
Lloh52:
	adrp	x10, _SOR_DP_TPG_PATTERN_TRAIN2@GOTPAGE
Lloh53:
	ldr	x10, [x10, _SOR_DP_TPG_PATTERN_TRAIN2@GOTPAGEOFF]
Lloh54:
	ldr	w10, [x10]
	orr	w9, w9, w10
LBB0_7:                                 ; =>This Inner Loop Header: Depth=1
	orr	w1, w9, w1, lsl #8
	subs	w8, w8, #1
	b.ne	LBB0_7
	b	LBB0_9
LBB0_8:
	mov	w1, #0
LBB0_9:
	ldr	w2, [x22]
	mov	x0, x20
	bl	_tegra_sor_writel
Lloh55:
	adrp	x8, _DP_LINK_SCRAMBLING_DISABLE@GOTPAGE
Lloh56:
	ldr	x8, [x8, _DP_LINK_SCRAMBLING_DISABLE@GOTPAGEOFF]
Lloh57:
	ldr	w8, [x8]
Lloh58:
	adrp	x9, _DP_TRAINING_PATTERN_2@GOTPAGE
Lloh59:
	ldr	x9, [x9, _DP_TRAINING_PATTERN_2@GOTPAGEOFF]
Lloh60:
	ldr	w9, [x9]
	orr	w2, w9, w8
	ldr	w0, [x20]
	mov	x1, x19
	bl	_drm_dp_aux_train
	tbnz	w0, #31, LBB0_15
; %bb.10:
	ldr	w8, [x19]
	cbz	w8, LBB0_13
; %bb.11:
	mov	w1, #0
	ldr	w9, [x21]
Lloh61:
	adrp	x10, _SOR_DP_TPG_SCRAMBLER_GALIOS@GOTPAGE
Lloh62:
	ldr	x10, [x10, _SOR_DP_TPG_SCRAMBLER_GALIOS@GOTPAGEOFF]
Lloh63:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh64:
	adrp	x10, _SOR_DP_TPG_PATTERN_NONE@GOTPAGE
Lloh65:
	ldr	x10, [x10, _SOR_DP_TPG_PATTERN_NONE@GOTPAGEOFF]
Lloh66:
	ldr	w10, [x10]
	orr	w9, w9, w10
LBB0_12:                                ; =>This Inner Loop Header: Depth=1
	orr	w1, w9, w1, lsl #8
	subs	w8, w8, #1
	b.ne	LBB0_12
	b	LBB0_14
LBB0_13:
	mov	w1, #0
LBB0_14:
	ldr	w2, [x22]
	mov	x0, x20
	bl	_tegra_sor_writel
Lloh67:
	adrp	x8, _DP_TRAINING_PATTERN_DISABLE@GOTPAGE
Lloh68:
	ldr	x8, [x8, _DP_TRAINING_PATTERN_DISABLE@GOTPAGEOFF]
Lloh69:
	ldr	w2, [x8]
	ldr	w0, [x20]
	mov	x1, x19
	bl	_drm_dp_aux_train
	cmp	w0, #0
	csel	w0, w0, wzr, lt
LBB0_15:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.cfi_endproc
                                        ; -- End function
	.comm	_SOR_LANE_DRIVE_CURRENT0,4,2    ; @SOR_LANE_DRIVE_CURRENT0
	.comm	_SOR_LANE_PREEMPHASIS0,4,2      ; @SOR_LANE_PREEMPHASIS0
	.comm	_SOR_LANE_POSTCURSOR0,4,2       ; @SOR_LANE_POSTCURSOR0
	.comm	_SOR_LVDS,4,2                   ; @SOR_LVDS
	.comm	_SOR_DP_PADCTL_TX_PU_ENABLE,4,2 ; @SOR_DP_PADCTL_TX_PU_ENABLE
	.comm	_SOR_DP_PADCTL_TX_PU_MASK,4,2   ; @SOR_DP_PADCTL_TX_PU_MASK
	.comm	_SOR_DP_PADCTL_CM_TXD_3,4,2     ; @SOR_DP_PADCTL_CM_TXD_3
	.comm	_SOR_DP_PADCTL_CM_TXD_2,4,2     ; @SOR_DP_PADCTL_CM_TXD_2
	.comm	_SOR_DP_PADCTL_CM_TXD_1,4,2     ; @SOR_DP_PADCTL_CM_TXD_1
	.comm	_SOR_DP_PADCTL_CM_TXD_0,4,2     ; @SOR_DP_PADCTL_CM_TXD_0
	.comm	_DP_SET_ANSI_8B10B,4,2          ; @DP_SET_ANSI_8B10B
	.comm	_SOR_DP_TPG_CHANNEL_CODING,8,3  ; @SOR_DP_TPG_CHANNEL_CODING
	.comm	_SOR_DP_TPG_SCRAMBLER_NONE,8,3  ; @SOR_DP_TPG_SCRAMBLER_NONE
	.comm	_SOR_DP_TPG_PATTERN_TRAIN1,8,3  ; @SOR_DP_TPG_PATTERN_TRAIN1
	.comm	_SOR_DP_TPG,4,2                 ; @SOR_DP_TPG
	.comm	_DP_TRAINING_PATTERN_1,4,2      ; @DP_TRAINING_PATTERN_1
	.comm	_SOR_DP_SPARE0,4,2              ; @SOR_DP_SPARE0
	.comm	_SOR_DP_SPARE_SEQ_ENABLE,4,2    ; @SOR_DP_SPARE_SEQ_ENABLE
	.comm	_SOR_DP_SPARE_PANEL_INTERNAL,4,2 ; @SOR_DP_SPARE_PANEL_INTERNAL
	.comm	_SOR_DP_SPARE_MACRO_SOR_CLK,4,2 ; @SOR_DP_SPARE_MACRO_SOR_CLK
	.comm	_SOR_DP_TPG_PATTERN_TRAIN2,8,3  ; @SOR_DP_TPG_PATTERN_TRAIN2
	.comm	_DP_LINK_SCRAMBLING_DISABLE,4,2 ; @DP_LINK_SCRAMBLING_DISABLE
	.comm	_DP_TRAINING_PATTERN_2,4,2      ; @DP_TRAINING_PATTERN_2
	.comm	_SOR_DP_TPG_SCRAMBLER_GALIOS,8,3 ; @SOR_DP_TPG_SCRAMBLER_GALIOS
	.comm	_SOR_DP_TPG_PATTERN_NONE,8,3    ; @SOR_DP_TPG_PATTERN_NONE
	.comm	_DP_TRAINING_PATTERN_DISABLE,4,2 ; @DP_TRAINING_PATTERN_DISABLE
	.no_dead_strip	_tegra_sor_dp_train_fast
.subsections_via_symbols
