	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tc_main_link_enable
_tc_main_link_enable:                   ## @tc_main_link_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	%rsp, %r14
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -48(%rbp)
	movq	8(%rdi), %rax
	movq	%rax, -72(%rbp)                 ## 8-byte Spill
	movq	_DP_LINK_STATUS_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	shlq	$2, %rax
	callq	____chkstk_darwin
	addq	$15, %rax
	andq	$-16, %rax
	subq	%rax, %rsp
	movq	%rsp, -56(%rbp)                 ## 8-byte Spill
	movq	8(%r12), %rdi
	leaq	L_.str(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_dbg
	movl	48(%r12), %edi
	movq	_DP0CTL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	leaq	-60(%rbp), %rdx
	callq	_regmap_read
	movl	%eax, %ebx
	testl	%eax, %eax
	je	LBB0_3
LBB0_1:
	movq	%r14, %rsp
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	cmpq	-48(%rbp), %rax
	jne	LBB0_40
## %bb.2:
	movl	%ebx, %eax
	leaq	-40(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_3:
	movq	_DP_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	andl	-60(%rbp), %edi
	callq	_WARN_ON
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	movl	48(%r12), %edi
	movl	(%r15), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_1
LBB0_5:
	movl	48(%r12), %r13d
	movq	_DP0_SRCCTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	%r12, %rdi
	callq	_tc_srcctrl
	movl	%r13d, %edi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_regmap_write
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_1
## %bb.6:
	movl	24(%r12), %ecx
	movq	_DP1_SRCCTRL@GOTPCREL(%rip), %rsi
	xorl	%edx, %edx
	cmpq	$0, 40(%r12)
	movl	$0, %eax
	je	LBB0_8
## %bb.7:
	movq	_DP0_SRCCTRL_SSCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_8:
	movl	48(%r12), %edi
	movl	(%rsi), %esi
	cmpl	$162000, %ecx                   ## imm = 0x278D0
	je	LBB0_10
## %bb.9:
	movq	_DP0_SRCCTRL_BW27@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
LBB0_10:
	orl	%eax, %edx
	callq	_regmap_write
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_1
## %bb.11:
	movq	%r12, %rdi
	callq	_tc_set_syspllparam
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_1
## %bb.12:
	movq	_BGREN@GOTPCREL(%rip), %rax
	movq	_PWR_SW_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r13d
	orl	(%rax), %r13d
	movq	_PHY_A0_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	movq	_PHY_M0_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	movl	48(%r12), %edi
	xorl	%eax, %eax
	cmpl	$2, 28(%r12)
	jne	LBB0_14
## %bb.13:
	movq	_PHY_2LANE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_14:
	orl	%eax, %r13d
	movq	_DP_PHY_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r13d, %edx
	callq	_regmap_write
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_1
## %bb.15:
	movq	_DP0_PLLCTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_tc_pllupdate
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_1
## %bb.16:
	movq	_DP1_PLLCTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_tc_pllupdate
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_1
## %bb.17:
	movq	_DP_PHY_RST@GOTPCREL(%rip), %rax
	movq	_PHY_M1_RST@GOTPCREL(%rip), %rdx
	movq	_PHY_M0_RST@GOTPCREL(%rip), %rcx
	orl	(%rax), %r13d
	orl	(%rdx), %r13d
	orl	(%rcx), %r13d
	movl	48(%r12), %edi
	movq	_DP_PHY_CTRL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movl	%r13d, %edx
	callq	_regmap_write
	movl	$100, %edi
	movl	$200, %esi
	callq	_usleep_range
	movq	_PHY_M1_RST@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_DP_PHY_RST@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_PHY_M0_RST@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	notl	%edx
	andl	%r13d, %edx
	movl	48(%r12), %edi
	movl	(%rbx), %esi
	callq	_regmap_write
	movl	(%rbx), %esi
	movq	_PHY_RDY@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r12, %rdi
	movl	%ecx, %edx
	movl	$1, %r8d
	movl	$1000, %r9d                     ## imm = 0x3E8
	callq	_tc_poll_timeout
	testl	%eax, %eax
	je	LBB0_19
## %bb.18:
	movl	%eax, %ebx
	leaq	L_.str.1(%rip), %rsi
	movq	-72(%rbp), %rdi                 ## 8-byte Reload
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_1
LBB0_19:
	movl	48(%r12), %edi
	movq	_DP0_MISC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_BPC_8@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_1
## %bb.20:
	leaq	52(%r12), %rbx
	movl	(%r12), %edx
	cmpl	16(%r12), %edx
	jne	LBB0_36
LBB0_21:
	leaq	24(%r12), %rsi
	movq	%rbx, %r13
	movq	%rbx, %rdi
	callq	_drm_dp_link_configure
	testl	%eax, %eax
	js	LBB0_60
## %bb.22:
	xorl	%eax, %eax
	cmpq	$0, 40(%r12)
	je	LBB0_24
## %bb.23:
	movq	_DP_SPREAD_AMP_0_5@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_24:
	movq	-56(%rbp), %rdx                 ## 8-byte Reload
	movl	%eax, (%rdx)
	movq	_DP_SET_ANSI_8B10B@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 4(%rdx)
	movq	_DP_DOWNSPREAD_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	_drm_dp_dpcd_write
	testl	%eax, %eax
	js	LBB0_60
## %bb.25:
	movq	_DP_TRAIN_VOLTAGE_SWING_LEVEL_0@GOTPCREL(%rip), %rax
	movq	_DP_TRAIN_PRE_EMPH_LEVEL_0@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	-56(%rbp), %rdx                 ## 8-byte Reload
	movl	%ecx, 4(%rdx)
	movl	%ecx, (%rdx)
	movq	_DP_TRAINING_LANE0_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	_drm_dp_dpcd_write
	testl	%eax, %eax
	js	LBB0_60
## %bb.26:
	movl	48(%r12), %edi
	movq	_DP0_SNKLTCTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DP_LINK_SCRAMBLING_DISABLE@GOTPCREL(%rip), %rcx
	movq	_DP_TRAINING_PATTERN_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	orl	(%rcx), %edx
	callq	_regmap_write
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_1
## %bb.27:
	movl	48(%r12), %edi
	movq	_DP0_LTLOOPCTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$-16777203, %edx                ## imm = 0xFF00000D
	callq	_regmap_write
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_1
## %bb.28:
	movl	48(%r12), %ebx
	movq	_DP0_SRCCTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -76(%rbp)                 ## 4-byte Spill
	movq	%r12, %rdi
	callq	_tc_srcctrl
	movq	_DP0_SRCCTRL_SCRMBLDIS@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_DP0_SRCCTRL_AUTOCORRECT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_DP0_SRCCTRL_TP1@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%ebx, %edi
	movl	-76(%rbp), %esi                 ## 4-byte Reload
	movl	%eax, %edx
	callq	_regmap_write
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_1
## %bb.29:
	movl	48(%r12), %edi
	movl	(%r15), %esi
	movq	_DP_LINK_CAP_ENHANCED_FRAMING@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	andl	32(%r12), %edx
	je	LBB0_31
## %bb.30:
	movq	_EF_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
LBB0_31:
	movq	_DP_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	callq	_regmap_write
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_1
## %bb.32:
	movq	%r12, %rdi
	callq	_tc_wait_link_training
	movl	%eax, %ebx
	testl	%eax, %eax
	js	LBB0_1
## %bb.33:
	je	LBB0_41
## %bb.34:
	movq	8(%r12), %rdi
	movq	_training_pattern1_errors@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movl	%ebx, %ecx
	movl	(%rax,%rcx,4), %edx
	leaq	L_.str.4(%rip), %rsi
LBB0_35:
	xorl	%ebx, %ebx
	xorl	%eax, %eax
	callq	_dev_err
	movq	_ENODEV@GOTPCREL(%rip), %rax
	subl	(%rax), %ebx
	jmp	LBB0_1
LBB0_36:
	leaq	L_.str.2(%rip), %rsi
	movq	-72(%rbp), %rdi                 ## 8-byte Reload
	xorl	%eax, %eax
	callq	_dev_dbg
	movl	(%r12), %edx
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	%edx, (%rax)
	movq	_DP_EDP_CONFIGURATION_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %r13
	movq	%rbx, %rdi
	callq	_drm_dp_dpcd_writeb
	testl	%eax, %eax
	js	LBB0_61
## %bb.37:
	movq	_DP_EDP_CONFIGURATION_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movq	-56(%rbp), %rdx                 ## 8-byte Reload
	callq	_drm_dp_dpcd_readb
	testl	%eax, %eax
	js	LBB0_61
## %bb.38:
	movl	(%r12), %edx
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	cmpl	%edx, (%rax)
	movq	%r13, %rbx
	je	LBB0_21
## %bb.39:
	leaq	L_.str.3(%rip), %rsi
	movq	-72(%rbp), %rdi                 ## 8-byte Reload
	xorl	%eax, %eax
	callq	_dev_dbg
	movl	$1, 20(%r12)
	jmp	LBB0_21
LBB0_40:
	callq	___stack_chk_fail
LBB0_41:
	movl	48(%r12), %edi
	movq	_DP0_SNKLTCTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DP_TRAINING_PATTERN_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_DP_LINK_SCRAMBLING_DISABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	callq	_regmap_write
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_1
## %bb.42:
	movl	48(%r12), %ebx
	movq	_DP0_SRCCTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	%r12, %rdi
	callq	_tc_srcctrl
	movq	_DP0_SRCCTRL_SCRMBLDIS@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_DP0_SRCCTRL_AUTOCORRECT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_DP0_SRCCTRL_TP2@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%ebx, %edi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_regmap_write
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_1
## %bb.43:
	movq	%r12, %rdi
	callq	_tc_wait_link_training
	movl	%eax, %ebx
	testl	%eax, %eax
	js	LBB0_1
## %bb.44:
	je	LBB0_46
## %bb.45:
	movq	8(%r12), %rdi
	movq	_training_pattern2_errors@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movl	%ebx, %ecx
	movl	(%rax,%rcx,4), %edx
	leaq	L_.str.5(%rip), %rsi
	jmp	LBB0_35
LBB0_46:
	movl	48(%r12), %ebx
	movq	_DP0_SRCCTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	%r12, %rdi
	callq	_tc_srcctrl
	movq	_DP0_SRCCTRL_AUTOCORRECT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%ebx, %edi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_regmap_write
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_1
## %bb.47:
	movl	20(%r12), %edx
	testl	%edx, %edx
	je	LBB0_49
## %bb.48:
	movq	_DP_LINK_SCRAMBLING_DISABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
LBB0_49:
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	%edx, (%rax)
	movq	_DP_TRAINING_PATTERN_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_drm_dp_dpcd_writeb
	testl	%eax, %eax
	js	LBB0_60
## %bb.50:
	movq	%r13, %rdi
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
	callq	_drm_dp_dpcd_read_link_status
	testl	%eax, %eax
	js	LBB0_61
## %bb.51:
	movq	_DP_CHANNEL_EQ_BITS@GOTPCREL(%rip), %r15
	movl	(%r15), %eax
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	movl	(%rcx), %edx
	andl	%eax, %edx
	movl	%edx, -60(%rbp)
	xorl	%ebx, %ebx
	cmpl	%eax, %edx
	je	LBB0_53
## %bb.52:
	movq	8(%r12), %rdi
	leaq	L_.str.6(%rip), %rsi
	xorl	%ebx, %ebx
	xorl	%eax, %eax
	callq	_dev_err
	movq	_ENODEV@GOTPCREL(%rip), %rax
	subl	(%rax), %ebx
LBB0_53:
	cmpl	$2, 28(%r12)
	jne	LBB0_58
## %bb.54:
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %edx
	sarl	$4, %edx
	movl	(%r15), %eax
	andl	%eax, %edx
	movl	%edx, -60(%rbp)
	cmpl	%eax, %edx
	je	LBB0_56
## %bb.55:
	movq	8(%r12), %rdi
	leaq	L_.str.7(%rip), %rsi
	xorl	%ebx, %ebx
	xorl	%eax, %eax
	callq	_dev_err
	movq	_ENODEV@GOTPCREL(%rip), %rax
	subl	(%rax), %ebx
LBB0_56:
	movq	_DP_INTERLANE_ALIGN_DONE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	testl	%eax, 8(%rcx)
	jne	LBB0_58
## %bb.57:
	movq	8(%r12), %rdi
	leaq	L_.str.8(%rip), %rsi
	xorl	%ebx, %ebx
	xorl	%eax, %eax
	callq	_dev_err
	movq	_ENODEV@GOTPCREL(%rip), %rax
	subl	(%rax), %ebx
LBB0_58:
	testl	%ebx, %ebx
	je	LBB0_64
## %bb.59:
	movq	-56(%rbp), %r12                 ## 8-byte Reload
	movl	(%r12), %edx
	leaq	L_.str.9(%rip), %rsi
	movq	-72(%rbp), %r15                 ## 8-byte Reload
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	_dev_err
	movl	4(%r12), %edx
	leaq	L_.str.10(%rip), %rsi
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	_dev_err
	movl	8(%r12), %edx
	leaq	L_.str.11(%rip), %rsi
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	_dev_err
	movl	12(%r12), %edx
	leaq	L_.str.12(%rip), %rsi
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	_dev_err
	movl	16(%r12), %edx
	leaq	L_.str.13(%rip), %rsi
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	_dev_err
	movl	20(%r12), %edx
	leaq	L_.str.14(%rip), %rsi
	movq	%r15, %rdi
	jmp	LBB0_63
LBB0_60:
	movl	%eax, %ebx
	movq	8(%r12), %rdi
	leaq	L_.str.16(%rip), %rsi
	jmp	LBB0_62
LBB0_61:
	movl	%eax, %ebx
	movq	8(%r12), %rdi
	leaq	L_.str.15(%rip), %rsi
LBB0_62:
	movl	%eax, %edx
LBB0_63:
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_1
LBB0_64:
	xorl	%ebx, %ebx
	jmp	LBB0_1
	.cfi_endproc
                                        ## -- End function
	.comm	_DP_LINK_STATUS_SIZE,4,2        ## @DP_LINK_STATUS_SIZE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"link enable\n"

	.comm	_DP0CTL,4,2                     ## @DP0CTL
	.comm	_DP_EN,4,2                      ## @DP_EN
	.comm	_DP0_SRCCTRL,4,2                ## @DP0_SRCCTRL
	.comm	_DP1_SRCCTRL,4,2                ## @DP1_SRCCTRL
	.comm	_DP0_SRCCTRL_SSCG,4,2           ## @DP0_SRCCTRL_SSCG
	.comm	_DP0_SRCCTRL_BW27,4,2           ## @DP0_SRCCTRL_BW27
	.comm	_BGREN,4,2                      ## @BGREN
	.comm	_PWR_SW_EN,4,2                  ## @PWR_SW_EN
	.comm	_PHY_A0_EN,4,2                  ## @PHY_A0_EN
	.comm	_PHY_M0_EN,4,2                  ## @PHY_M0_EN
	.comm	_PHY_2LANE,4,2                  ## @PHY_2LANE
	.comm	_DP_PHY_CTRL,4,2                ## @DP_PHY_CTRL
	.comm	_DP0_PLLCTRL,4,2                ## @DP0_PLLCTRL
	.comm	_DP1_PLLCTRL,4,2                ## @DP1_PLLCTRL
	.comm	_DP_PHY_RST,4,2                 ## @DP_PHY_RST
	.comm	_PHY_M1_RST,4,2                 ## @PHY_M1_RST
	.comm	_PHY_M0_RST,4,2                 ## @PHY_M0_RST
	.comm	_PHY_RDY,4,2                    ## @PHY_RDY
L_.str.1:                               ## @.str.1
	.asciz	"timeout waiting for phy become ready"

	.comm	_DP0_MISC,4,2                   ## @DP0_MISC
	.comm	_BPC_8,4,2                      ## @BPC_8
L_.str.2:                               ## @.str.2
	.asciz	"Trying to set display to ASSR: %d\n"

	.comm	_DP_EDP_CONFIGURATION_SET,4,2   ## @DP_EDP_CONFIGURATION_SET
L_.str.3:                               ## @.str.3
	.asciz	"Failed to switch display ASSR to %d, falling back to unscrambled mode\n"

	.comm	_DP_SPREAD_AMP_0_5,4,2          ## @DP_SPREAD_AMP_0_5
	.comm	_DP_SET_ANSI_8B10B,4,2          ## @DP_SET_ANSI_8B10B
	.comm	_DP_DOWNSPREAD_CTRL,4,2         ## @DP_DOWNSPREAD_CTRL
	.comm	_DP_TRAIN_VOLTAGE_SWING_LEVEL_0,4,2 ## @DP_TRAIN_VOLTAGE_SWING_LEVEL_0
	.comm	_DP_TRAIN_PRE_EMPH_LEVEL_0,4,2  ## @DP_TRAIN_PRE_EMPH_LEVEL_0
	.comm	_DP_TRAINING_LANE0_SET,4,2      ## @DP_TRAINING_LANE0_SET
	.comm	_DP0_SNKLTCTRL,4,2              ## @DP0_SNKLTCTRL
	.comm	_DP_LINK_SCRAMBLING_DISABLE,4,2 ## @DP_LINK_SCRAMBLING_DISABLE
	.comm	_DP_TRAINING_PATTERN_1,4,2      ## @DP_TRAINING_PATTERN_1
	.comm	_DP0_LTLOOPCTRL,4,2             ## @DP0_LTLOOPCTRL
	.comm	_DP0_SRCCTRL_SCRMBLDIS,4,2      ## @DP0_SRCCTRL_SCRMBLDIS
	.comm	_DP0_SRCCTRL_AUTOCORRECT,4,2    ## @DP0_SRCCTRL_AUTOCORRECT
	.comm	_DP0_SRCCTRL_TP1,4,2            ## @DP0_SRCCTRL_TP1
	.comm	_DP_LINK_CAP_ENHANCED_FRAMING,4,2 ## @DP_LINK_CAP_ENHANCED_FRAMING
	.comm	_EF_EN,4,2                      ## @EF_EN
L_.str.4:                               ## @.str.4
	.asciz	"Link training phase 1 failed: %s\n"

	.comm	_training_pattern1_errors,8,3   ## @training_pattern1_errors
	.comm	_ENODEV,4,2                     ## @ENODEV
	.comm	_DP_TRAINING_PATTERN_2,4,2      ## @DP_TRAINING_PATTERN_2
	.comm	_DP0_SRCCTRL_TP2,4,2            ## @DP0_SRCCTRL_TP2
L_.str.5:                               ## @.str.5
	.asciz	"Link training phase 2 failed: %s\n"

	.comm	_training_pattern2_errors,8,3   ## @training_pattern2_errors
	.comm	_DP_TRAINING_PATTERN_SET,4,2    ## @DP_TRAINING_PATTERN_SET
	.comm	_DP_CHANNEL_EQ_BITS,4,2         ## @DP_CHANNEL_EQ_BITS
L_.str.6:                               ## @.str.6
	.asciz	"Lane 0 failed: %x\n"

L_.str.7:                               ## @.str.7
	.asciz	"Lane 1 failed: %x\n"

	.comm	_DP_INTERLANE_ALIGN_DONE,4,2    ## @DP_INTERLANE_ALIGN_DONE
L_.str.8:                               ## @.str.8
	.asciz	"Interlane align failed\n"

L_.str.9:                               ## @.str.9
	.asciz	"0x0202 LANE0_1_STATUS:            0x%02x\n"

L_.str.10:                              ## @.str.10
	.asciz	"0x0203 LANE2_3_STATUS             0x%02x\n"

L_.str.11:                              ## @.str.11
	.asciz	"0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n"

L_.str.12:                              ## @.str.12
	.asciz	"0x0205 SINK_STATUS:               0x%02x\n"

L_.str.13:                              ## @.str.13
	.asciz	"0x0206 ADJUST_REQUEST_LANE0_1:    0x%02x\n"

L_.str.14:                              ## @.str.14
	.asciz	"0x0207 ADJUST_REQUEST_LANE2_3:    0x%02x\n"

L_.str.15:                              ## @.str.15
	.asciz	"Failed to read DPCD: %d\n"

L_.str.16:                              ## @.str.16
	.asciz	"Failed to write DPCD: %d\n"

	.no_dead_strip	_tc_main_link_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tc_main_link_enable
_tc_main_link_enable:                   ; @tc_main_link_enable
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	sub	sp, sp, #16
	mov	x21, x0
	mov	x25, sp
Lloh0:
	adrp	x8, ___stack_chk_guard@GOTPAGE
Lloh1:
	ldr	x8, [x8, ___stack_chk_guard@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	stur	x8, [x29, #-88]
	ldr	x19, [x0, #8]
Lloh3:
	adrp	x8, _DP_LINK_STATUS_SIZE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _DP_LINK_STATUS_SIZE@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	lsl	x8, x8, #2
	mov	x9, x8
Lloh6:
	adrp	x16, ___chkstk_darwin@GOTPAGE
Lloh7:
	ldr	x16, [x16, ___chkstk_darwin@GOTPAGEOFF]
	blr	x16
	mov	x9, sp
	add	x8, x8, #15
	and	x8, x8, #0x7fffffff0
	sub	x20, x9, x8
	mov	sp, x20
	ldr	x0, [x0, #8]
Lloh8:
	adrp	x1, l_.str@PAGE
Lloh9:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_dbg
	ldr	w0, [x21, #48]
Lloh10:
	adrp	x27, _DP0CTL@GOTPAGE
Lloh11:
	ldr	x27, [x27, _DP0CTL@GOTPAGEOFF]
	ldr	w1, [x27]
	sub	x2, x29, #92
	bl	_regmap_read
	mov	x23, x0
	cbz	w0, LBB0_3
LBB0_1:
	mov	sp, x25
	ldur	x8, [x29, #-88]
Lloh12:
	adrp	x9, ___stack_chk_guard@GOTPAGE
Lloh13:
	ldr	x9, [x9, ___stack_chk_guard@GOTPAGEOFF]
Lloh14:
	ldr	x9, [x9]
	cmp	x9, x8
	b.ne	LBB0_30
; %bb.2:
	mov	x0, x23
	sub	sp, x29, #80
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
LBB0_3:
	ldur	w8, [x29, #-92]
Lloh15:
	adrp	x28, _DP_EN@GOTPAGE
Lloh16:
	ldr	x28, [x28, _DP_EN@GOTPAGEOFF]
	ldr	w9, [x28]
	and	w0, w9, w8
	bl	_WARN_ON
	cbz	x0, LBB0_5
; %bb.4:
	ldr	w0, [x21, #48]
	ldr	w1, [x27]
	mov	w2, #0
	bl	_regmap_write
	mov	x23, x0
	cbnz	w0, LBB0_1
LBB0_5:
	ldr	w22, [x21, #48]
Lloh17:
	adrp	x26, _DP0_SRCCTRL@GOTPAGE
Lloh18:
	ldr	x26, [x26, _DP0_SRCCTRL@GOTPAGEOFF]
	ldr	w23, [x26]
	mov	x0, x21
	bl	_tc_srcctrl
	mov	x2, x0
	mov	x0, x22
	mov	x1, x23
	bl	_regmap_write
	mov	x23, x0
	cbnz	w0, LBB0_1
; %bb.6:
	mov	x22, x21
	ldr	w8, [x22, #24]!
	ldr	w0, [x22, #24]
Lloh19:
	adrp	x9, _DP1_SRCCTRL@GOTPAGE
Lloh20:
	ldr	x9, [x9, _DP1_SRCCTRL@GOTPAGEOFF]
Lloh21:
	ldr	w1, [x9]
	ldr	x9, [x22, #16]
Lloh22:
	adrp	x10, _DP0_SRCCTRL_SSCG@GOTPAGE
Lloh23:
	ldr	x10, [x10, _DP0_SRCCTRL_SSCG@GOTPAGEOFF]
Lloh24:
	ldr	w10, [x10]
	cmp	x9, #0
Lloh25:
	adrp	x9, _DP0_SRCCTRL_BW27@GOTPAGE
Lloh26:
	ldr	x9, [x9, _DP0_SRCCTRL_BW27@GOTPAGEOFF]
	csel	w10, wzr, w10, eq
Lloh27:
	ldr	w9, [x9]
	sub	w8, w8, #39, lsl #12            ; =159744
	cmp	w8, #2256
	csel	w8, wzr, w9, eq
	orr	w2, w8, w10
	bl	_regmap_write
	mov	x23, x0
	cbnz	w0, LBB0_1
; %bb.7:
	mov	x0, x21
	bl	_tc_set_syspllparam
	mov	x23, x0
	cbnz	w0, LBB0_1
; %bb.8:
Lloh28:
	adrp	x8, _BGREN@GOTPAGE
Lloh29:
	ldr	x8, [x8, _BGREN@GOTPAGEOFF]
Lloh30:
	ldr	w8, [x8]
Lloh31:
	adrp	x9, _PWR_SW_EN@GOTPAGE
Lloh32:
	ldr	x9, [x9, _PWR_SW_EN@GOTPAGEOFF]
Lloh33:
	ldr	w9, [x9]
Lloh34:
	adrp	x10, _PHY_A0_EN@GOTPAGE
Lloh35:
	ldr	x10, [x10, _PHY_A0_EN@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh36:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh37:
	adrp	x9, _PHY_M0_EN@GOTPAGE
Lloh38:
	ldr	x9, [x9, _PHY_M0_EN@GOTPAGEOFF]
Lloh39:
	ldr	w9, [x9]
	orr	w8, w8, w9
	ldr	w9, [x21, #28]
Lloh40:
	adrp	x10, _PHY_2LANE@GOTPAGE
Lloh41:
	ldr	x10, [x10, _PHY_2LANE@GOTPAGEOFF]
Lloh42:
	ldr	w10, [x10]
	cmp	w9, #2
	csel	w9, w10, wzr, eq
	orr	w24, w8, w9
	ldr	w0, [x21, #48]
Lloh43:
	adrp	x8, _DP_PHY_CTRL@GOTPAGE
Lloh44:
	ldr	x8, [x8, _DP_PHY_CTRL@GOTPAGEOFF]
Lloh45:
	ldr	w1, [x8]
	mov	x2, x24
	bl	_regmap_write
	mov	x23, x0
	cbnz	w0, LBB0_1
; %bb.9:
Lloh46:
	adrp	x8, _DP0_PLLCTRL@GOTPAGE
Lloh47:
	ldr	x8, [x8, _DP0_PLLCTRL@GOTPAGEOFF]
Lloh48:
	ldr	w1, [x8]
	mov	x0, x21
	bl	_tc_pllupdate
	mov	x23, x0
	cbnz	w0, LBB0_1
; %bb.10:
Lloh49:
	adrp	x8, _DP1_PLLCTRL@GOTPAGE
Lloh50:
	ldr	x8, [x8, _DP1_PLLCTRL@GOTPAGEOFF]
Lloh51:
	ldr	w1, [x8]
	mov	x0, x21
	bl	_tc_pllupdate
	mov	x23, x0
	cbnz	w0, LBB0_1
; %bb.11:
Lloh52:
	adrp	x8, _DP_PHY_RST@GOTPAGE
Lloh53:
	ldr	x8, [x8, _DP_PHY_RST@GOTPAGEOFF]
Lloh54:
	ldr	w8, [x8]
Lloh55:
	adrp	x9, _PHY_M1_RST@GOTPAGE
Lloh56:
	ldr	x9, [x9, _PHY_M1_RST@GOTPAGEOFF]
Lloh57:
	ldr	w9, [x9]
Lloh58:
	adrp	x10, _PHY_M0_RST@GOTPAGE
Lloh59:
	ldr	x10, [x10, _PHY_M0_RST@GOTPAGEOFF]
Lloh60:
	ldr	w10, [x10]
	orr	w8, w8, w24
	orr	w8, w8, w9
	orr	w23, w8, w10
	ldr	w0, [x21, #48]
Lloh61:
	adrp	x24, _DP_PHY_CTRL@GOTPAGE
Lloh62:
	ldr	x24, [x24, _DP_PHY_CTRL@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	x2, x23
	bl	_regmap_write
	mov	w0, #100
	mov	w1, #200
	bl	_usleep_range
Lloh63:
	adrp	x8, _DP_PHY_RST@GOTPAGE
Lloh64:
	ldr	x8, [x8, _DP_PHY_RST@GOTPAGEOFF]
Lloh65:
	ldr	w8, [x8]
Lloh66:
	adrp	x9, _PHY_M1_RST@GOTPAGE
Lloh67:
	ldr	x9, [x9, _PHY_M1_RST@GOTPAGEOFF]
Lloh68:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh69:
	adrp	x9, _PHY_M0_RST@GOTPAGE
Lloh70:
	ldr	x9, [x9, _PHY_M0_RST@GOTPAGEOFF]
Lloh71:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w2, w23, w8
	ldr	w0, [x21, #48]
	ldr	w1, [x24]
	bl	_regmap_write
	ldr	w1, [x24]
Lloh72:
	adrp	x8, _PHY_RDY@GOTPAGE
Lloh73:
	ldr	x8, [x8, _PHY_RDY@GOTPAGEOFF]
Lloh74:
	ldr	w2, [x8]
	mov	x0, x21
	mov	x3, x2
	mov	w4, #1
	mov	w5, #1000
	bl	_tc_poll_timeout
	cbz	w0, LBB0_13
; %bb.12:
	mov	x23, x0
Lloh75:
	adrp	x1, l_.str.1@PAGE
Lloh76:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x19
	bl	_dev_err
	b	LBB0_1
LBB0_13:
	ldr	w0, [x21, #48]
Lloh77:
	adrp	x8, _DP0_MISC@GOTPAGE
Lloh78:
	ldr	x8, [x8, _DP0_MISC@GOTPAGEOFF]
Lloh79:
	ldr	w1, [x8]
Lloh80:
	adrp	x8, _BPC_8@GOTPAGE
Lloh81:
	ldr	x8, [x8, _BPC_8@GOTPAGEOFF]
Lloh82:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	mov	x23, x0
	cbnz	w0, LBB0_1
; %bb.14:
	mov	x23, x22
	add	x24, x21, #52
	ldr	w8, [x21]
	ldr	w9, [x21, #16]
	cmp	w8, w9
	b.ne	LBB0_26
LBB0_15:
	mov	x22, x24
	mov	x0, x24
	mov	x1, x23
	bl	_drm_dp_link_configure
	tbnz	w0, #31, LBB0_41
; %bb.16:
Lloh83:
	adrp	x8, _DP_SPREAD_AMP_0_5@GOTPAGE
Lloh84:
	ldr	x8, [x8, _DP_SPREAD_AMP_0_5@GOTPAGEOFF]
	ldr	x9, [x21, #40]
Lloh85:
	ldr	w8, [x8]
	cmp	x9, #0
	csel	w8, wzr, w8, eq
Lloh86:
	adrp	x9, _DP_SET_ANSI_8B10B@GOTPAGE
Lloh87:
	ldr	x9, [x9, _DP_SET_ANSI_8B10B@GOTPAGEOFF]
Lloh88:
	ldr	w9, [x9]
	stp	w8, w9, [x20]
Lloh89:
	adrp	x8, _DP_DOWNSPREAD_CTRL@GOTPAGE
Lloh90:
	ldr	x8, [x8, _DP_DOWNSPREAD_CTRL@GOTPAGEOFF]
Lloh91:
	ldr	w1, [x8]
	mov	x0, x22
	mov	x2, x20
	mov	w3, #2
	bl	_drm_dp_dpcd_write
	tbnz	w0, #31, LBB0_41
; %bb.17:
Lloh92:
	adrp	x8, _DP_TRAIN_VOLTAGE_SWING_LEVEL_0@GOTPAGE
Lloh93:
	ldr	x8, [x8, _DP_TRAIN_VOLTAGE_SWING_LEVEL_0@GOTPAGEOFF]
Lloh94:
	ldr	w8, [x8]
Lloh95:
	adrp	x9, _DP_TRAIN_PRE_EMPH_LEVEL_0@GOTPAGE
Lloh96:
	ldr	x9, [x9, _DP_TRAIN_PRE_EMPH_LEVEL_0@GOTPAGEOFF]
Lloh97:
	ldr	w9, [x9]
	orr	w8, w9, w8
	stp	w8, w8, [x20]
Lloh98:
	adrp	x8, _DP_TRAINING_LANE0_SET@GOTPAGE
Lloh99:
	ldr	x8, [x8, _DP_TRAINING_LANE0_SET@GOTPAGEOFF]
Lloh100:
	ldr	w1, [x8]
	mov	x0, x22
	mov	x2, x20
	mov	w3, #2
	bl	_drm_dp_dpcd_write
	tbnz	w0, #31, LBB0_41
; %bb.18:
	ldr	w0, [x21, #48]
Lloh101:
	adrp	x24, _DP0_SNKLTCTRL@GOTPAGE
Lloh102:
	ldr	x24, [x24, _DP0_SNKLTCTRL@GOTPAGEOFF]
Lloh103:
	adrp	x8, _DP_LINK_SCRAMBLING_DISABLE@GOTPAGE
Lloh104:
	ldr	x8, [x8, _DP_LINK_SCRAMBLING_DISABLE@GOTPAGEOFF]
	ldr	w1, [x24]
Lloh105:
	ldr	w8, [x8]
Lloh106:
	adrp	x9, _DP_TRAINING_PATTERN_1@GOTPAGE
Lloh107:
	ldr	x9, [x9, _DP_TRAINING_PATTERN_1@GOTPAGEOFF]
Lloh108:
	ldr	w9, [x9]
	orr	w2, w9, w8
	bl	_regmap_write
	mov	x23, x0
	cbnz	w0, LBB0_1
; %bb.19:
	ldr	w0, [x21, #48]
Lloh109:
	adrp	x8, _DP0_LTLOOPCTRL@GOTPAGE
Lloh110:
	ldr	x8, [x8, _DP0_LTLOOPCTRL@GOTPAGEOFF]
Lloh111:
	ldr	w1, [x8]
	mov	w2, #13
	movk	w2, #65280, lsl #16
	bl	_regmap_write
	mov	x23, x0
	cbnz	w0, LBB0_1
; %bb.20:
	ldr	w23, [x21, #48]
	ldr	w8, [x26]
	stur	w8, [x29, #-96]                 ; 4-byte Folded Spill
	mov	x0, x21
	bl	_tc_srcctrl
Lloh112:
	adrp	x8, _DP0_SRCCTRL_SCRMBLDIS@GOTPAGE
Lloh113:
	ldr	x8, [x8, _DP0_SRCCTRL_SCRMBLDIS@GOTPAGEOFF]
Lloh114:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh115:
	adrp	x9, _DP0_SRCCTRL_AUTOCORRECT@GOTPAGE
Lloh116:
	ldr	x9, [x9, _DP0_SRCCTRL_AUTOCORRECT@GOTPAGEOFF]
Lloh117:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh118:
	adrp	x9, _DP0_SRCCTRL_TP1@GOTPAGE
Lloh119:
	ldr	x9, [x9, _DP0_SRCCTRL_TP1@GOTPAGEOFF]
Lloh120:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x23
	ldur	w1, [x29, #-96]                 ; 4-byte Folded Reload
	bl	_regmap_write
	mov	x23, x0
	cbnz	w0, LBB0_1
; %bb.21:
	ldr	w0, [x21, #48]
	ldr	w1, [x27]
	ldr	w8, [x21, #32]
Lloh121:
	adrp	x9, _DP_LINK_CAP_ENHANCED_FRAMING@GOTPAGE
Lloh122:
	ldr	x9, [x9, _DP_LINK_CAP_ENHANCED_FRAMING@GOTPAGEOFF]
Lloh123:
	adrp	x10, _EF_EN@GOTPAGE
Lloh124:
	ldr	x10, [x10, _EF_EN@GOTPAGEOFF]
Lloh125:
	ldr	w9, [x9]
Lloh126:
	ldr	w10, [x10]
	tst	w9, w8
	csel	w8, wzr, w10, eq
	ldr	w9, [x28]
	orr	w2, w8, w9
	bl	_regmap_write
	mov	x23, x0
	cbnz	w0, LBB0_1
; %bb.22:
	mov	x0, x21
	bl	_tc_wait_link_training
	mov	x23, x0
	tbnz	w0, #31, LBB0_1
; %bb.23:
	cbz	w23, LBB0_31
; %bb.24:
	ldr	x0, [x21, #8]
Lloh127:
	adrp	x8, _training_pattern1_errors@GOTPAGE
Lloh128:
	ldr	x8, [x8, _training_pattern1_errors@GOTPAGEOFF]
Lloh129:
	ldr	x8, [x8]
	ldr	w8, [x8, w23, uxtw #2]
	str	x8, [sp, #-16]!
Lloh130:
	adrp	x1, l_.str.4@PAGE
Lloh131:
	add	x1, x1, l_.str.4@PAGEOFF
LBB0_25:
	bl	_dev_err
	add	sp, sp, #16
Lloh132:
	adrp	x8, _ENODEV@GOTPAGE
Lloh133:
	ldr	x8, [x8, _ENODEV@GOTPAGEOFF]
Lloh134:
	ldr	w8, [x8]
	neg	w23, w8
	b	LBB0_1
LBB0_26:
	str	x8, [sp, #-16]!
Lloh135:
	adrp	x1, l_.str.2@PAGE
Lloh136:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x0, x19
	bl	_dev_dbg
	add	sp, sp, #16
	ldr	w2, [x21]
	str	w2, [x20]
Lloh137:
	adrp	x8, _DP_EDP_CONFIGURATION_SET@GOTPAGE
Lloh138:
	ldr	x8, [x8, _DP_EDP_CONFIGURATION_SET@GOTPAGEOFF]
Lloh139:
	ldr	w1, [x8]
	mov	x22, x24
	mov	x0, x24
	bl	_drm_dp_dpcd_writeb
	tbnz	w0, #31, LBB0_43
; %bb.27:
Lloh140:
	adrp	x8, _DP_EDP_CONFIGURATION_SET@GOTPAGE
Lloh141:
	ldr	x8, [x8, _DP_EDP_CONFIGURATION_SET@GOTPAGEOFF]
Lloh142:
	ldr	w1, [x8]
	mov	x0, x22
	mov	x2, x20
	bl	_drm_dp_dpcd_readb
	tbnz	w0, #31, LBB0_43
; %bb.28:
	ldr	w9, [x20]
	ldr	w8, [x21]
	cmp	w9, w8
	mov	x24, x22
	b.eq	LBB0_15
; %bb.29:
	str	x8, [sp, #-16]!
Lloh143:
	adrp	x1, l_.str.3@PAGE
Lloh144:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x0, x19
	bl	_dev_dbg
	add	sp, sp, #16
	mov	w8, #1
	str	w8, [x21, #20]
	b	LBB0_15
LBB0_30:
	bl	___stack_chk_fail
LBB0_31:
	ldr	w0, [x21, #48]
	ldr	w1, [x24]
Lloh145:
	adrp	x8, _DP_LINK_SCRAMBLING_DISABLE@GOTPAGE
Lloh146:
	ldr	x8, [x8, _DP_LINK_SCRAMBLING_DISABLE@GOTPAGEOFF]
Lloh147:
	ldr	w8, [x8]
Lloh148:
	adrp	x9, _DP_TRAINING_PATTERN_2@GOTPAGE
Lloh149:
	ldr	x9, [x9, _DP_TRAINING_PATTERN_2@GOTPAGEOFF]
Lloh150:
	ldr	w9, [x9]
	orr	w2, w9, w8
	bl	_regmap_write
	mov	x23, x0
	cbnz	w0, LBB0_1
; %bb.32:
	ldr	w23, [x21, #48]
	ldr	w24, [x26]
	mov	x0, x21
	bl	_tc_srcctrl
Lloh151:
	adrp	x8, _DP0_SRCCTRL_SCRMBLDIS@GOTPAGE
Lloh152:
	ldr	x8, [x8, _DP0_SRCCTRL_SCRMBLDIS@GOTPAGEOFF]
Lloh153:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh154:
	adrp	x9, _DP0_SRCCTRL_AUTOCORRECT@GOTPAGE
Lloh155:
	ldr	x9, [x9, _DP0_SRCCTRL_AUTOCORRECT@GOTPAGEOFF]
Lloh156:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh157:
	adrp	x9, _DP0_SRCCTRL_TP2@GOTPAGE
Lloh158:
	ldr	x9, [x9, _DP0_SRCCTRL_TP2@GOTPAGEOFF]
Lloh159:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x23
	mov	x1, x24
	bl	_regmap_write
	mov	x23, x0
	cbnz	w0, LBB0_1
; %bb.33:
	mov	x0, x21
	bl	_tc_wait_link_training
	mov	x23, x0
	tbnz	w0, #31, LBB0_1
; %bb.34:
	cbz	w23, LBB0_36
; %bb.35:
	ldr	x0, [x21, #8]
Lloh160:
	adrp	x8, _training_pattern2_errors@GOTPAGE
Lloh161:
	ldr	x8, [x8, _training_pattern2_errors@GOTPAGEOFF]
Lloh162:
	ldr	x8, [x8]
	ldr	w8, [x8, w23, uxtw #2]
	str	x8, [sp, #-16]!
Lloh163:
	adrp	x1, l_.str.5@PAGE
Lloh164:
	add	x1, x1, l_.str.5@PAGEOFF
	b	LBB0_25
LBB0_36:
	ldr	w23, [x21, #48]
	ldr	w24, [x26]
	mov	x0, x21
	bl	_tc_srcctrl
Lloh165:
	adrp	x8, _DP0_SRCCTRL_AUTOCORRECT@GOTPAGE
Lloh166:
	ldr	x8, [x8, _DP0_SRCCTRL_AUTOCORRECT@GOTPAGEOFF]
Lloh167:
	ldr	w8, [x8]
	orr	w2, w8, w0
	mov	x0, x23
	mov	x1, x24
	bl	_regmap_write
	mov	x23, x0
	cbnz	w0, LBB0_1
; %bb.37:
	ldr	w8, [x21, #20]
Lloh168:
	adrp	x9, _DP_LINK_SCRAMBLING_DISABLE@GOTPAGE
Lloh169:
	ldr	x9, [x9, _DP_LINK_SCRAMBLING_DISABLE@GOTPAGEOFF]
Lloh170:
	ldr	w9, [x9]
	cmp	w8, #0
	csel	w2, wzr, w9, eq
	str	w2, [x20]
Lloh171:
	adrp	x8, _DP_TRAINING_PATTERN_SET@GOTPAGE
Lloh172:
	ldr	x8, [x8, _DP_TRAINING_PATTERN_SET@GOTPAGEOFF]
Lloh173:
	ldr	w1, [x8]
	mov	x0, x22
	bl	_drm_dp_dpcd_writeb
	tbnz	w0, #31, LBB0_41
; %bb.38:
	mov	x0, x22
	mov	x1, x20
	bl	_drm_dp_dpcd_read_link_status
	tbnz	w0, #31, LBB0_43
; %bb.39:
	ldr	w8, [x20]
Lloh174:
	adrp	x22, _DP_CHANNEL_EQ_BITS@GOTPAGE
Lloh175:
	ldr	x22, [x22, _DP_CHANNEL_EQ_BITS@GOTPAGEOFF]
	ldr	w9, [x22]
	and	w8, w9, w8
	stur	w8, [x29, #-92]
	cmp	w8, w9
	b.ne	LBB0_44
; %bb.40:
	mov	w23, #0
	b	LBB0_45
LBB0_41:
	mov	x23, x0
	ldr	x0, [x21, #8]
	str	x23, [sp, #-16]!
Lloh176:
	adrp	x1, l_.str.16@PAGE
Lloh177:
	add	x1, x1, l_.str.16@PAGEOFF
LBB0_42:
	bl	_dev_err
	add	sp, sp, #16
	b	LBB0_1
LBB0_43:
	mov	x24, x0
	ldr	x0, [x21, #8]
	str	x24, [sp, #-16]!
Lloh178:
	adrp	x1, l_.str.15@PAGE
Lloh179:
	add	x1, x1, l_.str.15@PAGEOFF
	bl	_dev_err
	add	sp, sp, #16
	mov	x23, x24
	b	LBB0_1
LBB0_44:
	ldr	x0, [x21, #8]
	str	x8, [sp, #-16]!
Lloh180:
	adrp	x1, l_.str.6@PAGE
Lloh181:
	add	x1, x1, l_.str.6@PAGEOFF
	bl	_dev_err
	add	sp, sp, #16
Lloh182:
	adrp	x8, _ENODEV@GOTPAGE
Lloh183:
	ldr	x8, [x8, _ENODEV@GOTPAGEOFF]
Lloh184:
	ldr	w8, [x8]
	neg	w23, w8
LBB0_45:
	ldr	w8, [x21, #28]
	cmp	w8, #2
	b.ne	LBB0_50
; %bb.46:
	ldr	w8, [x20]
	ldr	w9, [x22]
	and	w8, w9, w8, asr #4
	stur	w8, [x29, #-92]
	cmp	w8, w9
	b.eq	LBB0_48
; %bb.47:
	ldr	x0, [x21, #8]
	str	x8, [sp, #-16]!
Lloh185:
	adrp	x1, l_.str.7@PAGE
Lloh186:
	add	x1, x1, l_.str.7@PAGEOFF
	bl	_dev_err
	add	sp, sp, #16
Lloh187:
	adrp	x8, _ENODEV@GOTPAGE
Lloh188:
	ldr	x8, [x8, _ENODEV@GOTPAGEOFF]
Lloh189:
	ldr	w8, [x8]
	neg	w23, w8
LBB0_48:
	ldr	w8, [x20, #8]
Lloh190:
	adrp	x9, _DP_INTERLANE_ALIGN_DONE@GOTPAGE
Lloh191:
	ldr	x9, [x9, _DP_INTERLANE_ALIGN_DONE@GOTPAGEOFF]
Lloh192:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_50
; %bb.49:
	ldr	x0, [x21, #8]
Lloh193:
	adrp	x1, l_.str.8@PAGE
Lloh194:
	add	x1, x1, l_.str.8@PAGEOFF
	bl	_dev_err
Lloh195:
	adrp	x8, _ENODEV@GOTPAGE
Lloh196:
	ldr	x8, [x8, _ENODEV@GOTPAGEOFF]
Lloh197:
	ldr	w8, [x8]
	neg	w23, w8
LBB0_50:
	cbz	w23, LBB0_1
; %bb.51:
	ldr	w8, [x20]
	str	x8, [sp, #-16]!
Lloh198:
	adrp	x1, l_.str.9@PAGE
Lloh199:
	add	x1, x1, l_.str.9@PAGEOFF
	mov	x0, x19
	bl	_dev_err
	add	sp, sp, #16
	ldr	w8, [x20, #4]
	str	x8, [sp, #-16]!
Lloh200:
	adrp	x1, l_.str.10@PAGE
Lloh201:
	add	x1, x1, l_.str.10@PAGEOFF
	mov	x0, x19
	bl	_dev_err
	add	sp, sp, #16
	ldr	w8, [x20, #8]
	str	x8, [sp, #-16]!
Lloh202:
	adrp	x1, l_.str.11@PAGE
Lloh203:
	add	x1, x1, l_.str.11@PAGEOFF
	mov	x0, x19
	bl	_dev_err
	add	sp, sp, #16
	ldr	w8, [x20, #12]
	str	x8, [sp, #-16]!
Lloh204:
	adrp	x1, l_.str.12@PAGE
Lloh205:
	add	x1, x1, l_.str.12@PAGEOFF
	mov	x0, x19
	bl	_dev_err
	add	sp, sp, #16
	ldr	w8, [x20, #16]
	str	x8, [sp, #-16]!
Lloh206:
	adrp	x1, l_.str.13@PAGE
Lloh207:
	add	x1, x1, l_.str.13@PAGEOFF
	mov	x0, x19
	bl	_dev_err
	add	sp, sp, #16
	ldr	w8, [x20, #20]
	str	x8, [sp, #-16]!
Lloh208:
	adrp	x1, l_.str.14@PAGE
Lloh209:
	add	x1, x1, l_.str.14@PAGEOFF
	mov	x0, x19
	b	LBB0_42
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpAdd	Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGot	Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.loh AdrpLdrGotLdr	Lloh112, Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh123, Lloh124, Lloh126
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh125
	.loh AdrpAdd	Lloh130, Lloh131
	.loh AdrpLdrGotLdr	Lloh127, Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh132, Lloh133, Lloh134
	.loh AdrpLdrGotLdr	Lloh137, Lloh138, Lloh139
	.loh AdrpAdd	Lloh135, Lloh136
	.loh AdrpLdrGotLdr	Lloh140, Lloh141, Lloh142
	.loh AdrpAdd	Lloh143, Lloh144
	.loh AdrpLdrGotLdr	Lloh148, Lloh149, Lloh150
	.loh AdrpLdrGotLdr	Lloh145, Lloh146, Lloh147
	.loh AdrpLdrGotLdr	Lloh157, Lloh158, Lloh159
	.loh AdrpLdrGotLdr	Lloh154, Lloh155, Lloh156
	.loh AdrpLdrGotLdr	Lloh151, Lloh152, Lloh153
	.loh AdrpAdd	Lloh163, Lloh164
	.loh AdrpLdrGotLdr	Lloh160, Lloh161, Lloh162
	.loh AdrpLdrGotLdr	Lloh165, Lloh166, Lloh167
	.loh AdrpLdrGotLdr	Lloh171, Lloh172, Lloh173
	.loh AdrpLdrGotLdr	Lloh168, Lloh169, Lloh170
	.loh AdrpLdrGot	Lloh174, Lloh175
	.loh AdrpAdd	Lloh176, Lloh177
	.loh AdrpAdd	Lloh178, Lloh179
	.loh AdrpLdrGotLdr	Lloh182, Lloh183, Lloh184
	.loh AdrpAdd	Lloh180, Lloh181
	.loh AdrpLdrGotLdr	Lloh187, Lloh188, Lloh189
	.loh AdrpAdd	Lloh185, Lloh186
	.loh AdrpLdrGotLdr	Lloh190, Lloh191, Lloh192
	.loh AdrpLdrGotLdr	Lloh195, Lloh196, Lloh197
	.loh AdrpAdd	Lloh193, Lloh194
	.loh AdrpAdd	Lloh208, Lloh209
	.loh AdrpAdd	Lloh206, Lloh207
	.loh AdrpAdd	Lloh204, Lloh205
	.loh AdrpAdd	Lloh202, Lloh203
	.loh AdrpAdd	Lloh200, Lloh201
	.loh AdrpAdd	Lloh198, Lloh199
	.cfi_endproc
                                        ; -- End function
	.comm	_DP_LINK_STATUS_SIZE,4,2        ; @DP_LINK_STATUS_SIZE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"link enable\n"

	.comm	_DP0CTL,4,2                     ; @DP0CTL
	.comm	_DP_EN,4,2                      ; @DP_EN
	.comm	_DP0_SRCCTRL,4,2                ; @DP0_SRCCTRL
	.comm	_DP1_SRCCTRL,4,2                ; @DP1_SRCCTRL
	.comm	_DP0_SRCCTRL_SSCG,4,2           ; @DP0_SRCCTRL_SSCG
	.comm	_DP0_SRCCTRL_BW27,4,2           ; @DP0_SRCCTRL_BW27
	.comm	_BGREN,4,2                      ; @BGREN
	.comm	_PWR_SW_EN,4,2                  ; @PWR_SW_EN
	.comm	_PHY_A0_EN,4,2                  ; @PHY_A0_EN
	.comm	_PHY_M0_EN,4,2                  ; @PHY_M0_EN
	.comm	_PHY_2LANE,4,2                  ; @PHY_2LANE
	.comm	_DP_PHY_CTRL,4,2                ; @DP_PHY_CTRL
	.comm	_DP0_PLLCTRL,4,2                ; @DP0_PLLCTRL
	.comm	_DP1_PLLCTRL,4,2                ; @DP1_PLLCTRL
	.comm	_DP_PHY_RST,4,2                 ; @DP_PHY_RST
	.comm	_PHY_M1_RST,4,2                 ; @PHY_M1_RST
	.comm	_PHY_M0_RST,4,2                 ; @PHY_M0_RST
	.comm	_PHY_RDY,4,2                    ; @PHY_RDY
l_.str.1:                               ; @.str.1
	.asciz	"timeout waiting for phy become ready"

	.comm	_DP0_MISC,4,2                   ; @DP0_MISC
	.comm	_BPC_8,4,2                      ; @BPC_8
l_.str.2:                               ; @.str.2
	.asciz	"Trying to set display to ASSR: %d\n"

	.comm	_DP_EDP_CONFIGURATION_SET,4,2   ; @DP_EDP_CONFIGURATION_SET
l_.str.3:                               ; @.str.3
	.asciz	"Failed to switch display ASSR to %d, falling back to unscrambled mode\n"

	.comm	_DP_SPREAD_AMP_0_5,4,2          ; @DP_SPREAD_AMP_0_5
	.comm	_DP_SET_ANSI_8B10B,4,2          ; @DP_SET_ANSI_8B10B
	.comm	_DP_DOWNSPREAD_CTRL,4,2         ; @DP_DOWNSPREAD_CTRL
	.comm	_DP_TRAIN_VOLTAGE_SWING_LEVEL_0,4,2 ; @DP_TRAIN_VOLTAGE_SWING_LEVEL_0
	.comm	_DP_TRAIN_PRE_EMPH_LEVEL_0,4,2  ; @DP_TRAIN_PRE_EMPH_LEVEL_0
	.comm	_DP_TRAINING_LANE0_SET,4,2      ; @DP_TRAINING_LANE0_SET
	.comm	_DP0_SNKLTCTRL,4,2              ; @DP0_SNKLTCTRL
	.comm	_DP_LINK_SCRAMBLING_DISABLE,4,2 ; @DP_LINK_SCRAMBLING_DISABLE
	.comm	_DP_TRAINING_PATTERN_1,4,2      ; @DP_TRAINING_PATTERN_1
	.comm	_DP0_LTLOOPCTRL,4,2             ; @DP0_LTLOOPCTRL
	.comm	_DP0_SRCCTRL_SCRMBLDIS,4,2      ; @DP0_SRCCTRL_SCRMBLDIS
	.comm	_DP0_SRCCTRL_AUTOCORRECT,4,2    ; @DP0_SRCCTRL_AUTOCORRECT
	.comm	_DP0_SRCCTRL_TP1,4,2            ; @DP0_SRCCTRL_TP1
	.comm	_DP_LINK_CAP_ENHANCED_FRAMING,4,2 ; @DP_LINK_CAP_ENHANCED_FRAMING
	.comm	_EF_EN,4,2                      ; @EF_EN
l_.str.4:                               ; @.str.4
	.asciz	"Link training phase 1 failed: %s\n"

	.comm	_training_pattern1_errors,8,3   ; @training_pattern1_errors
	.comm	_ENODEV,4,2                     ; @ENODEV
	.comm	_DP_TRAINING_PATTERN_2,4,2      ; @DP_TRAINING_PATTERN_2
	.comm	_DP0_SRCCTRL_TP2,4,2            ; @DP0_SRCCTRL_TP2
l_.str.5:                               ; @.str.5
	.asciz	"Link training phase 2 failed: %s\n"

	.comm	_training_pattern2_errors,8,3   ; @training_pattern2_errors
	.comm	_DP_TRAINING_PATTERN_SET,4,2    ; @DP_TRAINING_PATTERN_SET
	.comm	_DP_CHANNEL_EQ_BITS,4,2         ; @DP_CHANNEL_EQ_BITS
l_.str.6:                               ; @.str.6
	.asciz	"Lane 0 failed: %x\n"

l_.str.7:                               ; @.str.7
	.asciz	"Lane 1 failed: %x\n"

	.comm	_DP_INTERLANE_ALIGN_DONE,4,2    ; @DP_INTERLANE_ALIGN_DONE
l_.str.8:                               ; @.str.8
	.asciz	"Interlane align failed\n"

l_.str.9:                               ; @.str.9
	.asciz	"0x0202 LANE0_1_STATUS:            0x%02x\n"

l_.str.10:                              ; @.str.10
	.asciz	"0x0203 LANE2_3_STATUS             0x%02x\n"

l_.str.11:                              ; @.str.11
	.asciz	"0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n"

l_.str.12:                              ; @.str.12
	.asciz	"0x0205 SINK_STATUS:               0x%02x\n"

l_.str.13:                              ; @.str.13
	.asciz	"0x0206 ADJUST_REQUEST_LANE0_1:    0x%02x\n"

l_.str.14:                              ; @.str.14
	.asciz	"0x0207 ADJUST_REQUEST_LANE2_3:    0x%02x\n"

l_.str.15:                              ; @.str.15
	.asciz	"Failed to read DPCD: %d\n"

l_.str.16:                              ; @.str.16
	.asciz	"Failed to write DPCD: %d\n"

	.no_dead_strip	_tc_main_link_enable
.subsections_via_symbols
