	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_uvd_sw_init             ## -- Begin function amdgpu_uvd_sw_init
	.p2align	4, 0x90
_amdgpu_uvd_sw_init:                    ## @amdgpu_uvd_sw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	addq	$72, %rdi
	movq	_amdgpu_uvd_idle_work_handler@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_DELAYED_WORK
	movl	(%r15), %eax
	addl	$-128, %eax
	cmpl	$15, %eax
	jae	LBB0_1
## %bb.2:
	movl	$25087, %ecx                    ## imm = 0x61FF
	btl	%eax, %ecx
	jb	LBB0_3
LBB0_1:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r13d, %r13d
	subl	(%rax), %r13d
LBB0_39:
	movl	%r13d, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_3:
	cltq
	leaq	l_switch.table.amdgpu_uvd_sw_init(%rip), %rcx
	movq	(%rcx,%rax,8), %rax
	movq	(%rax), %r14
	leaq	64(%r15), %r12
	movl	80(%r15), %edx
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	_request_firmware
	testl	%eax, %eax
	je	LBB0_5
## %bb.4:
	movl	%eax, %r13d
	movl	80(%r15), %edi
	leaq	L_.str(%rip), %rsi
	movq	%r14, %rdx
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_39
LBB0_5:
	movq	(%r12), %rdi
	callq	_amdgpu_ucode_validate
	testl	%eax, %eax
	je	LBB0_7
## %bb.6:
	movl	%eax, %r13d
	movl	80(%r15), %edi
	leaq	L_.str.1(%rip), %rsi
	movq	%r14, %rdx
	xorl	%eax, %eax
	callq	_dev_err
	movq	64(%r15), %rdi
	callq	_release_firmware
	movq	$0, 64(%r15)
	jmp	LBB0_39
LBB0_7:
	movq	_AMDGPU_DEFAULT_UVD_HANDLES@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 8(%r15)
	movq	64(%r15), %rax
	movq	(%rax), %r12
	movl	4(%r12), %edi
	callq	_le32_to_cpu
	movzbl	%al, %r14d
	movl	(%r15), %ebx
	movl	4(%r12), %edi
	callq	_le32_to_cpu
	cmpl	$128, %ebx
	jg	LBB0_15
## %bb.8:
	movl	%eax, %r13d
	shrl	$24, %r13d
	movl	4(%r12), %edi
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	callq	_le32_to_cpu
	movzbl	%ah, %ebx
	leaq	L_.str.2(%rip), %rdi
	movl	%r13d, -44(%rbp)                ## 4-byte Spill
	movl	%r13d, %esi
	movl	%ebx, %edx
	movl	%r14d, %ecx
	xorl	%eax, %eax
	callq	_DRM_INFO
	movl	-48(%rbp), %ecx                 ## 4-byte Reload
	cmpl	$33554431, %ecx                 ## imm = 0x1FFFFFF
	ja	LBB0_11
## %bb.9:
	cmpl	$1, -44(%rbp)                   ## 4-byte Folded Reload
	jne	LBB0_12
## %bb.10:
	cmpl	$80, %ebx
	jb	LBB0_12
LBB0_11:
	movq	_AMDGPU_MAX_UVD_HANDLES@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 8(%r15)
LBB0_12:
	andl	$-16777216, %ecx                ## imm = 0xFF000000
	movl	%ebx, %eax
	shll	$16, %eax
	orl	%ecx, %eax
	shll	$8, %r14d
	orl	%eax, %r14d
	movl	%r14d, 16(%r15)
	movl	$-135, %eax
	addl	(%r15), %eax
	cmpl	$1, %eax
	ja	LBB0_16
## %bb.13:
	movq	_FW_1_66_16@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r14d
	jae	LBB0_16
## %bb.14:
	leaq	L_.str.3(%rip), %rdi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	movl	%ebx, %edx
	callq	_DRM_ERROR
	jmp	LBB0_16
LBB0_15:
	movzbl	%ah, %eax
	movl	%eax, %r13d
	movl	4(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, %ebx
	shrl	$24, %ebx
	andl	$63, %ebx
	movl	4(%r12), %edi
	callq	_le32_to_cpu
	shrl	$30, %eax
	leaq	L_.str.4(%rip), %rdi
	movl	%eax, %esi
	movl	%ebx, %edx
	movl	%r13d, %ecx
	movl	%r14d, %r8d
	xorl	%eax, %eax
	callq	_DRM_INFO
	movq	_AMDGPU_MAX_UVD_HANDLES@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 8(%r15)
	movl	4(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, 16(%r15)
LBB0_16:
	movq	_AMDGPU_UVD_STACK_SIZE@GOTPCREL(%rip), %rax
	movq	_AMDGPU_UVD_HEAP_SIZE@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	addq	(%rax), %rcx
	movq	_AMDGPU_UVD_SESSION_SIZE@GOTPCREL(%rip), %rax
	movq	8(%r15), %r14
	imulq	(%rax), %r14
	addq	%rcx, %r14
	movq	88(%r15), %rax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_18
## %bb.17:
	movl	(%r12), %edi
	callq	_le32_to_cpu
                                        ## kill: def $eax killed $eax def $rax
	leal	8(%rax), %edi
	callq	_AMDGPU_GPU_PAGE_ALIGN
	addq	%rax, %r14
LBB0_18:
	movl	20(%r15), %eax
	testl	%eax, %eax
	jle	LBB0_24
## %bb.19:
	movl	$8, %r12d
	xorl	%ebx, %ebx
	jmp	LBB0_20
LBB0_22:                                ##   in Loop: Header=BB0_20 Depth=1
	movl	20(%r15), %eax
LBB0_23:                                ##   in Loop: Header=BB0_20 Depth=1
	incq	%rbx
	movslq	%eax, %rcx
	addq	$12, %r12
	cmpq	%rcx, %rbx
	jge	LBB0_24
LBB0_20:                                ## =>This Inner Loop Header: Depth=1
	movl	24(%r15), %ecx
	btl	%ebx, %ecx
	jb	LBB0_23
## %bb.21:                              ##   in Loop: Header=BB0_20 Depth=1
	movq	_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_AMDGPU_GEM_DOMAIN_VRAM@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	56(%r15), %rax
	leaq	(%rax,%r12), %r8
	leaq	-4(%rax,%r12), %r9
	leaq	-8(%rax,%r12), %rax
	movq	%rax, (%rsp)
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_amdgpu_bo_create_kernel
	testl	%eax, %eax
	je	LBB0_22
## %bb.31:
	movl	%eax, %r13d
	movl	80(%r15), %edi
	leaq	L_.str.5(%rip), %rsi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_39
LBB0_24:
	cmpq	$0, 8(%r15)
	je	LBB0_27
## %bb.25:
	xorl	%ebx, %ebx
	xorl	%r14d, %r14d
	.p2align	4, 0x90
LBB0_26:                                ## =>This Inner Loop Header: Depth=1
	movq	48(%r15), %rdi
	addq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_atomic_set
	movq	40(%r15), %rax
	movq	$0, (%rax,%rbx,2)
	incq	%r14
	addq	$4, %rbx
	cmpq	%r14, 8(%r15)
	ja	LBB0_26
LBB0_27:
	movq	_AMD_IP_BLOCK_TYPE_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$5, %edx
	xorl	%ecx, %ecx
	callq	_amdgpu_device_ip_block_version_cmp
	testl	%eax, %eax
	jne	LBB0_29
## %bb.28:
	movl	$1, 28(%r15)
LBB0_29:
	movl	(%r15), %eax
	leal	-132(%rax), %ecx
	cmpl	$10, %ecx
	ja	LBB0_37
## %bb.30:
	leaq	LJTI0_0(%rip), %rdx
	movslq	(%rdx,%rcx,4), %rcx
	addq	%rdx, %rcx
	jmpq	*%rcx
LBB0_32:
	movl	16(%r15), %eax
	movq	_FW_1_65_10@GOTPCREL(%rip), %rcx
	jmp	LBB0_33
LBB0_36:
	movl	16(%r15), %eax
	movq	_FW_1_37_15@GOTPCREL(%rip), %rcx
	jmp	LBB0_33
LBB0_37:
	xorl	%ecx, %ecx
	cmpl	$136, %eax
	setge	%cl
	movl	%ecx, 32(%r15)
	jmp	LBB0_38
LBB0_35:
	movl	16(%r15), %eax
	movq	_FW_1_87_12@GOTPCREL(%rip), %rcx
	jmp	LBB0_33
LBB0_34:
	movl	16(%r15), %eax
	movq	_FW_1_87_11@GOTPCREL(%rip), %rcx
LBB0_33:
	xorl	%edx, %edx
	cmpl	(%rcx), %eax
	setae	%dl
	movl	%edx, 32(%r15)
LBB0_38:
	xorl	%r13d, %r13d
	jmp	LBB0_39
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_32, LBB0_32-LJTI0_0
.set L0_0_set_36, LBB0_36-LJTI0_0
.set L0_0_set_37, LBB0_37-LJTI0_0
.set L0_0_set_35, LBB0_35-LJTI0_0
.set L0_0_set_34, LBB0_34-LJTI0_0
LJTI0_0:
	.long	L0_0_set_32
	.long	L0_0_set_36
	.long	L0_0_set_37
	.long	L0_0_set_37
	.long	L0_0_set_37
	.long	L0_0_set_37
	.long	L0_0_set_37
	.long	L0_0_set_37
	.long	L0_0_set_37
	.long	L0_0_set_35
	.long	L0_0_set_34
	.end_data_region
                                        ## -- End function
	.comm	_amdgpu_uvd_idle_work_handler,4,2 ## @amdgpu_uvd_idle_work_handler
	.comm	_FIRMWARE_TONGA,8,3             ## @FIRMWARE_TONGA
	.comm	_FIRMWARE_FIJI,8,3              ## @FIRMWARE_FIJI
	.comm	_FIRMWARE_CARRIZO,8,3           ## @FIRMWARE_CARRIZO
	.comm	_FIRMWARE_STONEY,8,3            ## @FIRMWARE_STONEY
	.comm	_FIRMWARE_POLARIS10,8,3         ## @FIRMWARE_POLARIS10
	.comm	_FIRMWARE_POLARIS11,8,3         ## @FIRMWARE_POLARIS11
	.comm	_FIRMWARE_POLARIS12,8,3         ## @FIRMWARE_POLARIS12
	.comm	_FIRMWARE_VEGA10,8,3            ## @FIRMWARE_VEGA10
	.comm	_FIRMWARE_VEGA12,8,3            ## @FIRMWARE_VEGA12
	.comm	_FIRMWARE_VEGAM,8,3             ## @FIRMWARE_VEGAM
	.comm	_FIRMWARE_VEGA20,8,3            ## @FIRMWARE_VEGA20
	.comm	_EINVAL,4,2                     ## @EINVAL
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"amdgpu_uvd: Can't load firmware \"%s\"\n"

L_.str.1:                               ## @.str.1
	.asciz	"amdgpu_uvd: Can't validate firmware \"%s\"\n"

	.comm	_AMDGPU_DEFAULT_UVD_HANDLES,8,3 ## @AMDGPU_DEFAULT_UVD_HANDLES
L_.str.2:                               ## @.str.2
	.asciz	"Found UVD firmware Version: %hu.%hu Family ID: %hu\n"

	.comm	_AMDGPU_MAX_UVD_HANDLES,8,3     ## @AMDGPU_MAX_UVD_HANDLES
	.comm	_FW_1_66_16,4,2                 ## @FW_1_66_16
L_.str.3:                               ## @.str.3
	.asciz	"POLARIS10/11 UVD firmware version %hu.%hu is too old.\n"

L_.str.4:                               ## @.str.4
	.asciz	"Found UVD firmware ENC: %hu.%hu DEC: .%hu Family ID: %hu\n"

	.comm	_AMDGPU_UVD_STACK_SIZE,8,3      ## @AMDGPU_UVD_STACK_SIZE
	.comm	_AMDGPU_UVD_HEAP_SIZE,8,3       ## @AMDGPU_UVD_HEAP_SIZE
	.comm	_AMDGPU_UVD_SESSION_SIZE,8,3    ## @AMDGPU_UVD_SESSION_SIZE
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
	.comm	_AMDGPU_GEM_DOMAIN_VRAM,4,2     ## @AMDGPU_GEM_DOMAIN_VRAM
L_.str.5:                               ## @.str.5
	.asciz	"(%d) failed to allocate UVD bo\n"

	.comm	_AMD_IP_BLOCK_TYPE_UVD,4,2      ## @AMD_IP_BLOCK_TYPE_UVD
	.comm	_FW_1_65_10,4,2                 ## @FW_1_65_10
	.comm	_FW_1_87_11,4,2                 ## @FW_1_87_11
	.comm	_FW_1_87_12,4,2                 ## @FW_1_87_12
	.comm	_FW_1_37_15,4,2                 ## @FW_1_37_15
	.comm	_FIRMWARE_BONAIRE,8,3           ## @FIRMWARE_BONAIRE
	.comm	_FIRMWARE_HAWAII,8,3            ## @FIRMWARE_HAWAII
	.comm	_FIRMWARE_KABINI,8,3            ## @FIRMWARE_KABINI
	.comm	_FIRMWARE_KAVERI,8,3            ## @FIRMWARE_KAVERI
	.comm	_FIRMWARE_MULLINS,8,3           ## @FIRMWARE_MULLINS
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.amdgpu_uvd_sw_init
l_switch.table.amdgpu_uvd_sw_init:
	.quad	_FIRMWARE_VEGAM
	.quad	_FIRMWARE_VEGA20
	.quad	_FIRMWARE_VEGA12
	.quad	_FIRMWARE_VEGA10
	.quad	_FIRMWARE_TONGA
	.quad	_FIRMWARE_STONEY
	.quad	_FIRMWARE_POLARIS12
	.quad	_FIRMWARE_POLARIS11
	.quad	_FIRMWARE_POLARIS10
	.quad	_FIRMWARE_TONGA
	.quad	_FIRMWARE_TONGA
	.quad	_FIRMWARE_TONGA
	.quad	_FIRMWARE_TONGA
	.quad	_FIRMWARE_FIJI
	.quad	_FIRMWARE_CARRIZO

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_uvd_sw_init             ; -- Begin function amdgpu_uvd_sw_init
	.p2align	2
_amdgpu_uvd_sw_init:                    ; @amdgpu_uvd_sw_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	add	x0, x0, #72
Lloh0:
	adrp	x8, _amdgpu_uvd_idle_work_handler@GOTPAGE
Lloh1:
	ldr	x8, [x8, _amdgpu_uvd_idle_work_handler@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	bl	_INIT_DELAYED_WORK
	ldr	w8, [x19]
	sub	w8, w8, #128
	cmp	w8, #15
	b.hs	LBB0_2
; %bb.1:
	mov	w9, #25087
	lsr	w9, w9, w8
	tbnz	w9, #0, LBB0_4
LBB0_2:
Lloh3:
	adrp	x8, _EINVAL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	neg	w20, w8
LBB0_3:
	mov	x0, x20
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_4:
Lloh6:
	adrp	x9, l_switch.table.amdgpu_uvd_sw_init@PAGE
Lloh7:
	add	x9, x9, l_switch.table.amdgpu_uvd_sw_init@PAGEOFF
	ldr	x8, [x9, w8, sxtw #3]
	ldr	x21, [x8]
	add	x22, x19, #64
	ldr	w2, [x19, #80]
	mov	x0, x22
	mov	x1, x21
	bl	_request_firmware
	cbz	w0, LBB0_6
; %bb.5:
	mov	x20, x0
	ldr	w0, [x19, #80]
	str	x21, [sp]
Lloh8:
	adrp	x1, l_.str@PAGE
Lloh9:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
	b	LBB0_3
LBB0_6:
	ldr	x0, [x22]
	bl	_amdgpu_ucode_validate
	cbz	w0, LBB0_8
; %bb.7:
	mov	x20, x0
	ldr	w0, [x19, #80]
	str	x21, [sp]
Lloh10:
	adrp	x1, l_.str.1@PAGE
Lloh11:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_err
	ldr	x0, [x19, #64]
	bl	_release_firmware
	str	xzr, [x19, #64]
	b	LBB0_3
LBB0_8:
Lloh12:
	adrp	x8, _AMDGPU_DEFAULT_UVD_HANDLES@GOTPAGE
Lloh13:
	ldr	x8, [x8, _AMDGPU_DEFAULT_UVD_HANDLES@GOTPAGEOFF]
Lloh14:
	ldr	x8, [x8]
	str	x8, [x19, #8]
	ldr	x8, [x19, #64]
	ldr	x24, [x8]
	ldr	w0, [x24, #4]
	bl	_le32_to_cpu
	and	w20, w0, #0xff
	ldr	w21, [x19]
	ldr	w0, [x24, #4]
	bl	_le32_to_cpu
	mov	x23, x0
	cmp	w21, #128
	b.gt	LBB0_16
; %bb.9:
	lsr	w21, w23, #24
	ldr	w0, [x24, #4]
	bl	_le32_to_cpu
	ubfx	w22, w0, #8, #8
Lloh15:
	adrp	x0, l_.str.2@PAGE
Lloh16:
	add	x0, x0, l_.str.2@PAGEOFF
	mov	x1, x21
	mov	x2, x22
	mov	x3, x20
	bl	_DRM_INFO
	lsr	w8, w23, #25
	cbnz	w8, LBB0_12
; %bb.10:
	cmp	w21, #1
	b.ne	LBB0_13
; %bb.11:
	cmp	w22, #80
	b.lo	LBB0_13
LBB0_12:
Lloh17:
	adrp	x8, _AMDGPU_MAX_UVD_HANDLES@GOTPAGE
Lloh18:
	ldr	x8, [x8, _AMDGPU_MAX_UVD_HANDLES@GOTPAGEOFF]
Lloh19:
	ldr	x8, [x8]
	str	x8, [x19, #8]
LBB0_13:
	and	w8, w23, #0xff000000
	bfi	w8, w22, #16, #8
	bfi	w8, w20, #8, #8
	str	w8, [x19, #16]
	ldr	w9, [x19]
	sub	w9, w9, #135
	cmp	w9, #1
	b.hi	LBB0_17
; %bb.14:
Lloh20:
	adrp	x9, _FW_1_66_16@GOTPAGE
Lloh21:
	ldr	x9, [x9, _FW_1_66_16@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	cmp	w8, w9
	b.hs	LBB0_17
; %bb.15:
Lloh23:
	adrp	x0, l_.str.3@PAGE
Lloh24:
	add	x0, x0, l_.str.3@PAGEOFF
	mov	x1, x21
	mov	x2, x22
	bl	_DRM_ERROR
	b	LBB0_17
LBB0_16:
	ubfx	w21, w23, #8, #8
	ldr	w0, [x24, #4]
	bl	_le32_to_cpu
	ubfx	w22, w0, #24, #6
	ldr	w0, [x24, #4]
	bl	_le32_to_cpu
	lsr	w1, w0, #30
	str	x20, [sp]
Lloh25:
	adrp	x0, l_.str.4@PAGE
Lloh26:
	add	x0, x0, l_.str.4@PAGEOFF
	mov	x2, x22
	mov	x3, x21
	bl	_DRM_INFO
Lloh27:
	adrp	x8, _AMDGPU_MAX_UVD_HANDLES@GOTPAGE
Lloh28:
	ldr	x8, [x8, _AMDGPU_MAX_UVD_HANDLES@GOTPAGEOFF]
Lloh29:
	ldr	x8, [x8]
	str	x8, [x19, #8]
	ldr	w0, [x24, #4]
	bl	_le32_to_cpu
	str	w0, [x19, #16]
LBB0_17:
Lloh30:
	adrp	x8, _AMDGPU_UVD_STACK_SIZE@GOTPAGE
Lloh31:
	ldr	x8, [x8, _AMDGPU_UVD_STACK_SIZE@GOTPAGEOFF]
Lloh32:
	ldr	x8, [x8]
Lloh33:
	adrp	x9, _AMDGPU_UVD_HEAP_SIZE@GOTPAGE
Lloh34:
	ldr	x9, [x9, _AMDGPU_UVD_HEAP_SIZE@GOTPAGEOFF]
Lloh35:
	ldr	x9, [x9]
	add	x8, x9, x8
Lloh36:
	adrp	x9, _AMDGPU_UVD_SESSION_SIZE@GOTPAGE
Lloh37:
	ldr	x9, [x9, _AMDGPU_UVD_SESSION_SIZE@GOTPAGEOFF]
Lloh38:
	ldr	x9, [x9]
	ldr	x10, [x19, #8]
	madd	x21, x10, x9, x8
	ldr	x8, [x19, #88]
Lloh39:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh40:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh41:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_19
; %bb.18:
	ldr	w0, [x24]
	bl	_le32_to_cpu
	add	w0, w0, #8
	bl	_AMDGPU_GPU_PAGE_ALIGN
	add	x21, x0, x21
LBB0_19:
	ldr	w8, [x19, #20]
	cmp	w8, #1
	b.lt	LBB0_26
; %bb.20:
	mov	x22, #0
	mov	w23, #8
Lloh42:
	adrp	x24, _PAGE_SIZE@GOTPAGE
Lloh43:
	ldr	x24, [x24, _PAGE_SIZE@GOTPAGEOFF]
Lloh44:
	adrp	x25, _AMDGPU_GEM_DOMAIN_VRAM@GOTPAGE
Lloh45:
	ldr	x25, [x25, _AMDGPU_GEM_DOMAIN_VRAM@GOTPAGEOFF]
	b	LBB0_23
LBB0_21:                                ;   in Loop: Header=BB0_23 Depth=1
	ldr	w8, [x19, #20]
LBB0_22:                                ;   in Loop: Header=BB0_23 Depth=1
	add	x22, x22, #1
	add	x23, x23, #12
	cmp	x22, w8, sxtw
	b.ge	LBB0_26
LBB0_23:                                ; =>This Inner Loop Header: Depth=1
	ldr	w9, [x19, #24]
	lsr	w9, w9, w22
	tbnz	w9, #0, LBB0_22
; %bb.24:                               ;   in Loop: Header=BB0_23 Depth=1
	ldr	w2, [x24]
	ldr	w3, [x25]
	ldr	x8, [x19, #56]
	add	x4, x8, x23
	sub	x5, x4, #4
	sub	x6, x4, #8
	mov	x0, x19
	mov	x1, x21
	bl	_amdgpu_bo_create_kernel
	cbz	w0, LBB0_21
; %bb.25:
	mov	x20, x0
	ldr	w0, [x19, #80]
	str	x20, [sp]
Lloh46:
	adrp	x1, l_.str.5@PAGE
Lloh47:
	add	x1, x1, l_.str.5@PAGEOFF
	bl	_dev_err
	b	LBB0_3
LBB0_26:
	ldr	x8, [x19, #8]
	cbz	x8, LBB0_29
; %bb.27:
	mov	x20, #0
	mov	x21, #0
LBB0_28:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #48]
	add	x0, x8, x20
	mov	w1, #0
	bl	_atomic_set
	ldr	x8, [x19, #40]
	str	xzr, [x8, x21, lsl #3]
	add	x21, x21, #1
	ldr	x8, [x19, #8]
	add	x20, x20, #4
	cmp	x8, x21
	b.hi	LBB0_28
LBB0_29:
Lloh48:
	adrp	x8, _AMD_IP_BLOCK_TYPE_UVD@GOTPAGE
Lloh49:
	ldr	x8, [x8, _AMD_IP_BLOCK_TYPE_UVD@GOTPAGEOFF]
Lloh50:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #5
	mov	w3, #0
	bl	_amdgpu_device_ip_block_version_cmp
	cbnz	w0, LBB0_31
; %bb.30:
	mov	w8, #1
	str	w8, [x19, #28]
LBB0_31:
	ldr	w8, [x19]
	sub	w9, w8, #132
	cmp	w9, #10
	b.hi	LBB0_35
; %bb.32:
Lloh51:
	adrp	x10, lJTI0_0@PAGE
Lloh52:
	add	x10, x10, lJTI0_0@PAGEOFF
	adr	x11, LBB0_33
	ldrb	w12, [x10, x9]
	add	x11, x11, x12, lsl #2
	br	x11
LBB0_33:
	mov	w20, #0
	ldr	w8, [x19, #16]
Lloh53:
	adrp	x9, _FW_1_65_10@GOTPAGE
Lloh54:
	ldr	x9, [x9, _FW_1_65_10@GOTPAGEOFF]
	b	LBB0_38
LBB0_34:
	mov	w20, #0
	ldr	w8, [x19, #16]
Lloh55:
	adrp	x9, _FW_1_37_15@GOTPAGE
Lloh56:
	ldr	x9, [x9, _FW_1_37_15@GOTPAGEOFF]
	b	LBB0_38
LBB0_35:
	mov	w20, #0
	cmp	w8, #135
	cset	w8, gt
	b	LBB0_39
LBB0_36:
	mov	w20, #0
	ldr	w8, [x19, #16]
Lloh57:
	adrp	x9, _FW_1_87_12@GOTPAGE
Lloh58:
	ldr	x9, [x9, _FW_1_87_12@GOTPAGEOFF]
	b	LBB0_38
LBB0_37:
	mov	w20, #0
	ldr	w8, [x19, #16]
Lloh59:
	adrp	x9, _FW_1_87_11@GOTPAGE
Lloh60:
	ldr	x9, [x9, _FW_1_87_11@GOTPAGEOFF]
LBB0_38:
	ldr	w9, [x9]
	cmp	w8, w9
	cset	w8, hs
LBB0_39:
	str	w8, [x19, #32]
	b	LBB0_3
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpAdd	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpAdd	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpAdd	Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpAdd	Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpLdrGot	Lloh59, Lloh60
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_33-LBB0_33)>>2
	.byte	(LBB0_34-LBB0_33)>>2
	.byte	(LBB0_35-LBB0_33)>>2
	.byte	(LBB0_35-LBB0_33)>>2
	.byte	(LBB0_35-LBB0_33)>>2
	.byte	(LBB0_35-LBB0_33)>>2
	.byte	(LBB0_35-LBB0_33)>>2
	.byte	(LBB0_35-LBB0_33)>>2
	.byte	(LBB0_35-LBB0_33)>>2
	.byte	(LBB0_36-LBB0_33)>>2
	.byte	(LBB0_37-LBB0_33)>>2
                                        ; -- End function
	.comm	_amdgpu_uvd_idle_work_handler,4,2 ; @amdgpu_uvd_idle_work_handler
	.comm	_FIRMWARE_TONGA,8,3             ; @FIRMWARE_TONGA
	.comm	_FIRMWARE_FIJI,8,3              ; @FIRMWARE_FIJI
	.comm	_FIRMWARE_CARRIZO,8,3           ; @FIRMWARE_CARRIZO
	.comm	_FIRMWARE_STONEY,8,3            ; @FIRMWARE_STONEY
	.comm	_FIRMWARE_POLARIS10,8,3         ; @FIRMWARE_POLARIS10
	.comm	_FIRMWARE_POLARIS11,8,3         ; @FIRMWARE_POLARIS11
	.comm	_FIRMWARE_POLARIS12,8,3         ; @FIRMWARE_POLARIS12
	.comm	_FIRMWARE_VEGA10,8,3            ; @FIRMWARE_VEGA10
	.comm	_FIRMWARE_VEGA12,8,3            ; @FIRMWARE_VEGA12
	.comm	_FIRMWARE_VEGAM,8,3             ; @FIRMWARE_VEGAM
	.comm	_FIRMWARE_VEGA20,8,3            ; @FIRMWARE_VEGA20
	.comm	_EINVAL,4,2                     ; @EINVAL
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"amdgpu_uvd: Can't load firmware \"%s\"\n"

l_.str.1:                               ; @.str.1
	.asciz	"amdgpu_uvd: Can't validate firmware \"%s\"\n"

	.comm	_AMDGPU_DEFAULT_UVD_HANDLES,8,3 ; @AMDGPU_DEFAULT_UVD_HANDLES
l_.str.2:                               ; @.str.2
	.asciz	"Found UVD firmware Version: %hu.%hu Family ID: %hu\n"

	.comm	_AMDGPU_MAX_UVD_HANDLES,8,3     ; @AMDGPU_MAX_UVD_HANDLES
	.comm	_FW_1_66_16,4,2                 ; @FW_1_66_16
l_.str.3:                               ; @.str.3
	.asciz	"POLARIS10/11 UVD firmware version %hu.%hu is too old.\n"

l_.str.4:                               ; @.str.4
	.asciz	"Found UVD firmware ENC: %hu.%hu DEC: .%hu Family ID: %hu\n"

	.comm	_AMDGPU_UVD_STACK_SIZE,8,3      ; @AMDGPU_UVD_STACK_SIZE
	.comm	_AMDGPU_UVD_HEAP_SIZE,8,3       ; @AMDGPU_UVD_HEAP_SIZE
	.comm	_AMDGPU_UVD_SESSION_SIZE,8,3    ; @AMDGPU_UVD_SESSION_SIZE
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
	.comm	_AMDGPU_GEM_DOMAIN_VRAM,4,2     ; @AMDGPU_GEM_DOMAIN_VRAM
l_.str.5:                               ; @.str.5
	.asciz	"(%d) failed to allocate UVD bo\n"

	.comm	_AMD_IP_BLOCK_TYPE_UVD,4,2      ; @AMD_IP_BLOCK_TYPE_UVD
	.comm	_FW_1_65_10,4,2                 ; @FW_1_65_10
	.comm	_FW_1_87_11,4,2                 ; @FW_1_87_11
	.comm	_FW_1_87_12,4,2                 ; @FW_1_87_12
	.comm	_FW_1_37_15,4,2                 ; @FW_1_37_15
	.comm	_FIRMWARE_BONAIRE,8,3           ; @FIRMWARE_BONAIRE
	.comm	_FIRMWARE_HAWAII,8,3            ; @FIRMWARE_HAWAII
	.comm	_FIRMWARE_KABINI,8,3            ; @FIRMWARE_KABINI
	.comm	_FIRMWARE_KAVERI,8,3            ; @FIRMWARE_KAVERI
	.comm	_FIRMWARE_MULLINS,8,3           ; @FIRMWARE_MULLINS
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.amdgpu_uvd_sw_init
l_switch.table.amdgpu_uvd_sw_init:
	.quad	_FIRMWARE_VEGAM
	.quad	_FIRMWARE_VEGA20
	.quad	_FIRMWARE_VEGA12
	.quad	_FIRMWARE_VEGA10
	.quad	_FIRMWARE_TONGA
	.quad	_FIRMWARE_STONEY
	.quad	_FIRMWARE_POLARIS12
	.quad	_FIRMWARE_POLARIS11
	.quad	_FIRMWARE_POLARIS10
	.quad	_FIRMWARE_TONGA
	.quad	_FIRMWARE_TONGA
	.quad	_FIRMWARE_TONGA
	.quad	_FIRMWARE_TONGA
	.quad	_FIRMWARE_FIJI
	.quad	_FIRMWARE_CARRIZO

.subsections_via_symbols
