	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function sync_point_perfmon_sample_pre
_sync_point_perfmon_sample_pre:         ## @sync_point_perfmon_sample_pre
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %rbx
	movq	_VIVS_PM_POWER_CONTROLS@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	callq	_gpu_read
	movq	_VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_gpu_write
	movq	_VIVS_HI_CLOCK_CONTROL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_gpu_read
	movq	_VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_gpu_write
	movq	_ETNA_PM_PROCESS_PRE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_sync_point_perfmon_sample      ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_VIVS_PM_POWER_CONTROLS,4,2     ## @VIVS_PM_POWER_CONTROLS
	.comm	_VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING,4,2 ## @VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING
	.comm	_VIVS_HI_CLOCK_CONTROL,4,2      ## @VIVS_HI_CLOCK_CONTROL
	.comm	_VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS,4,2 ## @VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS
	.comm	_ETNA_PM_PROCESS_PRE,4,2        ## @ETNA_PM_PROCESS_PRE
	.no_dead_strip	_sync_point_perfmon_sample_pre
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function sync_point_perfmon_sample_pre
_sync_point_perfmon_sample_pre:         ; @sync_point_perfmon_sample_pre
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x1
	mov	x20, x0
Lloh0:
	adrp	x21, _VIVS_PM_POWER_CONTROLS@GOTPAGE
Lloh1:
	ldr	x21, [x21, _VIVS_PM_POWER_CONTROLS@GOTPAGEOFF]
	ldr	w1, [x21]
	bl	_gpu_read
Lloh2:
	adrp	x8, _VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING@GOTPAGE
Lloh3:
	ldr	x8, [x8, _VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	bic	w2, w0, w8
	ldr	w1, [x21]
	mov	x0, x20
	bl	_gpu_write
Lloh5:
	adrp	x21, _VIVS_HI_CLOCK_CONTROL@GOTPAGE
Lloh6:
	ldr	x21, [x21, _VIVS_HI_CLOCK_CONTROL@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x20
	bl	_gpu_read
Lloh7:
	adrp	x8, _VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS@GOTPAGE
Lloh8:
	ldr	x8, [x8, _VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	bic	w2, w0, w8
	ldr	w1, [x21]
	mov	x0, x20
	bl	_gpu_write
Lloh10:
	adrp	x8, _ETNA_PM_PROCESS_PRE@GOTPAGE
Lloh11:
	ldr	x8, [x8, _ETNA_PM_PROCESS_PRE@GOTPAGEOFF]
Lloh12:
	ldr	w2, [x8]
	mov	x0, x20
	mov	x1, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_sync_point_perfmon_sample
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_VIVS_PM_POWER_CONTROLS,4,2     ; @VIVS_PM_POWER_CONTROLS
	.comm	_VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING,4,2 ; @VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING
	.comm	_VIVS_HI_CLOCK_CONTROL,4,2      ; @VIVS_HI_CLOCK_CONTROL
	.comm	_VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS,4,2 ; @VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS
	.comm	_ETNA_PM_PROCESS_PRE,4,2        ; @ETNA_PM_PROCESS_PRE
	.no_dead_strip	_sync_point_perfmon_sample_pre
.subsections_via_symbols
