	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function amdgpu_bo_do_create
_amdgpu_bo_do_create:                   ## @amdgpu_bo_do_create
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$72, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r12
	movq	%rsi, %r13
	movq	%rdi, %r15
	movl	36(%rsi), %ecx
	movq	_ttm_bo_type_kernel@GOTPCREL(%rip), %rsi
	xorl	%eax, %eax
	xorl	%edx, %edx
	cmpl	(%rsi), %ecx
	setne	%dl
	movl	%edx, -72(%rbp)
	movq	$0, -68(%rbp)
	je	LBB0_2
## %bb.1:
	movq	_TTM_OPT_FLAG_ALLOW_RES_EVICT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_2:
	movl	%eax, -60(%rbp)
	movl	32(%r13), %eax
	movl	%eax, -56(%rbp)
	movq	(%r13), %rbx
	movl	8(%r13), %eax
	movq	_AMDGPU_GEM_DOMAIN_GWS@GOTPCREL(%rip), %rdx
	movq	_AMDGPU_GEM_DOMAIN_OA@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rdx), %ecx
	testl	%eax, %ecx
	je	LBB0_5
## %bb.3:
	movq	16(%r13), %r14
	jmp	LBB0_4
LBB0_5:
	movq	_AMDGPU_GEM_DOMAIN_GDS@GOTPCREL(%rip), %rcx
	movq	16(%r13), %rdi
	testl	%eax, (%rcx)
	je	LBB0_7
## %bb.6:
	movl	$4, %esi
	callq	_ALIGN
	movq	%rax, %r14
	movq	%rbx, %rdi
	movl	$4, %esi
	callq	_ALIGN
	movq	%rax, %rbx
LBB0_4:
	movq	_PAGE_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shlq	%cl, %rbx
LBB0_8:
	movl	8(%r13), %edx
	movq	%r15, %rdi
	movq	%rbx, %rsi
	callq	_amdgpu_bo_validate_size
	testl	%eax, %eax
	je	LBB0_9
## %bb.10:
	movq	%r14, -96(%rbp)                 ## 8-byte Spill
	movq	%r12, -80(%rbp)                 ## 8-byte Spill
	movq	$0, (%r12)
	leaq	8(%r15), %r14
	movq	%r14, %rdi
	movq	%rbx, %rsi
	movl	$88, %edx
	callq	_ttm_bo_dma_acc_size
	movq	%rax, -88(%rbp)                 ## 8-byte Spill
	movq	_GFP_KERNEL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$88, %edi
	callq	_kzalloc
	movq	%rax, -104(%rbp)
	testq	%rax, %rax
	je	LBB0_9
## %bb.11:
	movq	%rax, %r12
	movl	12(%r15), %edi
	leaq	20(%rax), %rsi
	movq	%rbx, %rdx
	callq	_drm_gem_private_object_init
	leaq	80(%r12), %rdi
	callq	_INIT_LIST_HEAD
	movq	$0, 72(%r12)
	movl	24(%r13), %eax
	testl	%eax, %eax
	jne	LBB0_13
## %bb.12:
	movl	8(%r13), %eax
LBB0_13:
	movl	%eax, (%r12)
	movl	%eax, 4(%r12)
	movl	36(%r13), %ecx
	movq	_ttm_bo_type_kernel@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %ecx
	je	LBB0_16
## %bb.14:
	movq	_AMDGPU_GEM_DOMAIN_VRAM@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_16
## %bb.15:
	movq	_AMDGPU_GEM_DOMAIN_GTT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, 4(%r12)
LBB0_16:
	movl	28(%r13), %edi
	movl	%edi, 8(%r12)
	callq	_amdgpu_bo_support_uswc
	testl	%eax, %eax
	jne	LBB0_18
## %bb.17:
	movq	_AMDGPU_GEM_CREATE_CPU_GTT_USWC@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, 8(%r12)
LBB0_18:
	movq	%r14, 56(%r12)
	movl	8(%r13), %esi
	movq	_AMDGPU_GEM_DOMAIN_OA@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_AMDGPU_GEM_DOMAIN_GWS@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_AMDGPU_GEM_DOMAIN_GDS@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	testl	%esi, %eax
	je	LBB0_20
## %bb.19:
	movq	_AMDGPU_GEM_DOMAIN_CPU@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
LBB0_20:
	movq	%r12, %rdi
	callq	_amdgpu_bo_placement_from_domain
	movl	36(%r13), %ecx
	movq	_ttm_bo_type_kernel@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ecx
	jne	LBB0_22
## %bb.21:
	movl	$1, 16(%r12)
LBB0_22:
	leaq	16(%r12), %rsi
	movq	%r12, %r8
	addq	$64, %r8
	movl	32(%r13), %eax
	subq	$8, %rsp
	movq	_amdgpu_bo_destroy@GOTPCREL(%rip), %r10
	leaq	-72(%rbp), %r11
	movq	%r14, %rdi
	movq	%rbx, %rdx
	movq	-96(%rbp), %r9                  ## 8-byte Reload
	pushq	%r10
	pushq	%rax
	pushq	$0
	pushq	-88(%rbp)                       ## 8-byte Folded Reload
	pushq	%r11
	callq	_ttm_bo_init_reserved
	addq	$48, %rsp
	movl	%eax, %ebx
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	callq	_unlikely
	testq	%rax, %rax
	jne	LBB0_39
## %bb.23:
	movq	%r15, %rdi
	callq	_amdgpu_gmc_vram_full_visible
	testl	%eax, %eax
	jne	LBB0_27
## %bb.24:
	movq	32(%r12), %rax
	movq	_TTM_PL_VRAM@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_27
## %bb.25:
	movq	(%r15), %rax
	movq	_PAGE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarq	%cl, %rax
	cmpq	%rax, 40(%r12)
	jge	LBB0_27
## %bb.26:
	movl	-64(%rbp), %edx
	movq	%r15, %rdi
	movl	%edx, %esi
	jmp	LBB0_28
LBB0_9:
	movq	_ENOMEM@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
LBB0_39:
	movl	%ebx, %eax
	addq	$72, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_7:
	movq	_PAGE_SIZE@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	callq	_ALIGN
	movq	_PAGE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shrq	%cl, %rax
	movl	(%r14), %esi
	movq	%rax, %r14
	movq	%rbx, %rdi
	callq	_ALIGN
	movq	%rax, %rbx
	jmp	LBB0_8
LBB0_27:
	movl	-64(%rbp), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
LBB0_28:
	callq	_amdgpu_cs_report_moved_bytes
	movq	_AMDGPU_GEM_CREATE_VRAM_CLEARED@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 28(%r13)
	je	LBB0_32
## %bb.29:
	movq	_TTM_PL_FLAG_VRAM@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 48(%r12)
	je	LBB0_32
## %bb.30:
	movl	20(%r12), %edx
	leaq	-48(%rbp), %rcx
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_fill_buffer
	movl	%eax, %ebx
	movl	%eax, %edi
	callq	_unlikely
	testq	%rax, %rax
	je	LBB0_31
## %bb.36:
	cmpl	$0, 32(%r13)
	jne	LBB0_38
## %bb.37:
	movl	20(%r12), %edi
	callq	_dma_resv_unlock
LBB0_38:
	leaq	-104(%rbp), %rdi
	callq	_amdgpu_bo_unref
	jmp	LBB0_39
LBB0_31:
	movq	-48(%rbp), %rsi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_amdgpu_bo_fence
	movq	24(%r12), %rdi
	callq	_dma_fence_put
	movq	-48(%rbp), %rdi
	callq	_dma_fence_get
	movq	%rax, 24(%r12)
	movq	-48(%rbp), %rdi
	callq	_dma_fence_put
LBB0_32:
	cmpl	$0, 32(%r13)
	jne	LBB0_34
## %bb.33:
	movq	%r12, %rdi
	callq	_amdgpu_bo_unreserve
LBB0_34:
	movq	-80(%rbp), %rax                 ## 8-byte Reload
	movq	%r12, (%rax)
	movq	%r12, %rdi
	callq	_trace_amdgpu_bo_create
	movl	36(%r13), %eax
	movq	_ttm_bo_type_device@GOTPCREL(%rip), %rcx
	xorl	%ebx, %ebx
	cmpl	(%rcx), %eax
	jne	LBB0_39
## %bb.35:
	movq	_AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, 8(%r12)
	jmp	LBB0_39
	.cfi_endproc
                                        ## -- End function
	.comm	_ttm_bo_type_kernel,4,2         ## @ttm_bo_type_kernel
	.comm	_TTM_OPT_FLAG_ALLOW_RES_EVICT,4,2 ## @TTM_OPT_FLAG_ALLOW_RES_EVICT
	.comm	_AMDGPU_GEM_DOMAIN_GWS,4,2      ## @AMDGPU_GEM_DOMAIN_GWS
	.comm	_AMDGPU_GEM_DOMAIN_OA,4,2       ## @AMDGPU_GEM_DOMAIN_OA
	.comm	_PAGE_SHIFT,8,3                 ## @PAGE_SHIFT
	.comm	_AMDGPU_GEM_DOMAIN_GDS,4,2      ## @AMDGPU_GEM_DOMAIN_GDS
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
	.comm	_ENOMEM,4,2                     ## @ENOMEM
	.comm	_GFP_KERNEL,4,2                 ## @GFP_KERNEL
	.comm	_AMDGPU_GEM_DOMAIN_VRAM,4,2     ## @AMDGPU_GEM_DOMAIN_VRAM
	.comm	_AMDGPU_GEM_DOMAIN_GTT,4,2      ## @AMDGPU_GEM_DOMAIN_GTT
	.comm	_AMDGPU_GEM_CREATE_CPU_GTT_USWC,4,2 ## @AMDGPU_GEM_CREATE_CPU_GTT_USWC
	.comm	_AMDGPU_GEM_DOMAIN_CPU,4,2      ## @AMDGPU_GEM_DOMAIN_CPU
	.comm	_amdgpu_bo_destroy,4,2          ## @amdgpu_bo_destroy
	.comm	_TTM_PL_VRAM,8,3                ## @TTM_PL_VRAM
	.comm	_AMDGPU_GEM_CREATE_VRAM_CLEARED,4,2 ## @AMDGPU_GEM_CREATE_VRAM_CLEARED
	.comm	_TTM_PL_FLAG_VRAM,4,2           ## @TTM_PL_FLAG_VRAM
	.comm	_ttm_bo_type_device,4,2         ## @ttm_bo_type_device
	.comm	_AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,4,2 ## @AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
	.no_dead_strip	_amdgpu_bo_do_create
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function amdgpu_bo_do_create
_amdgpu_bo_do_create:                   ; @amdgpu_bo_do_create
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #176
	.cfi_def_cfa_offset 176
	stp	x28, x27, [sp, #80]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #96]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #112]            ; 16-byte Folded Spill
	stp	x22, x21, [sp, #128]            ; 16-byte Folded Spill
	stp	x20, x19, [sp, #144]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #160]            ; 16-byte Folded Spill
	add	x29, sp, #160
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x25, x2
	mov	x19, x1
	mov	x21, x0
Lloh0:
	adrp	x27, _ttm_bo_type_kernel@GOTPAGE
Lloh1:
	ldr	x27, [x27, _ttm_bo_type_kernel@GOTPAGEOFF]
	ldr	w8, [x27]
Lloh2:
	adrp	x9, _TTM_OPT_FLAG_ALLOW_RES_EVICT@GOTPAGE
Lloh3:
	ldr	x9, [x9, _TTM_OPT_FLAG_ALLOW_RES_EVICT@GOTPAGEOFF]
Lloh4:
	ldr	w9, [x9]
	ldp	w11, w10, [x1, #32]
	cmp	w10, w8
	csel	w8, wzr, w9, eq
	cset	w9, ne
	stp	w9, wzr, [sp, #56]
	stp	wzr, w8, [sp, #64]
	str	w11, [sp, #72]
	ldr	x22, [x1]
	ldr	w8, [x1, #8]
Lloh5:
	adrp	x28, _AMDGPU_GEM_DOMAIN_GWS@GOTPAGE
Lloh6:
	ldr	x28, [x28, _AMDGPU_GEM_DOMAIN_GWS@GOTPAGEOFF]
	ldr	w9, [x28]
Lloh7:
	adrp	x20, _AMDGPU_GEM_DOMAIN_OA@GOTPAGE
Lloh8:
	ldr	x20, [x20, _AMDGPU_GEM_DOMAIN_OA@GOTPAGEOFF]
	ldr	w10, [x20]
	orr	w9, w10, w9
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
	ldr	x23, [x19, #16]
Lloh9:
	adrp	x8, _PAGE_SHIFT@GOTPAGE
Lloh10:
	ldr	x8, [x8, _PAGE_SHIFT@GOTPAGEOFF]
Lloh11:
	ldr	x8, [x8]
	lsl	x24, x22, x8
	b	LBB0_5
LBB0_2:
Lloh12:
	adrp	x9, _AMDGPU_GEM_DOMAIN_GDS@GOTPAGE
Lloh13:
	ldr	x9, [x9, _AMDGPU_GEM_DOMAIN_GDS@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	ldr	x0, [x19, #16]
	tst	w9, w8
	b.eq	LBB0_4
; %bb.3:
	mov	w1, #4
	bl	_ALIGN
	mov	x23, x0
	mov	x0, x22
	mov	w1, #4
	bl	_ALIGN
Lloh15:
	adrp	x8, _PAGE_SHIFT@GOTPAGE
Lloh16:
	ldr	x8, [x8, _PAGE_SHIFT@GOTPAGEOFF]
Lloh17:
	ldr	x8, [x8]
	lsl	x24, x0, x8
	b	LBB0_5
LBB0_4:
Lloh18:
	adrp	x24, _PAGE_SIZE@GOTPAGE
Lloh19:
	ldr	x24, [x24, _PAGE_SIZE@GOTPAGEOFF]
	ldr	w1, [x24]
	bl	_ALIGN
Lloh20:
	adrp	x8, _PAGE_SHIFT@GOTPAGE
Lloh21:
	ldr	x8, [x8, _PAGE_SHIFT@GOTPAGEOFF]
Lloh22:
	ldr	x8, [x8]
	lsr	x23, x0, x8
	ldr	w1, [x24]
	mov	x0, x22
	bl	_ALIGN
	mov	x24, x0
LBB0_5:
	ldr	w2, [x19, #8]
	mov	x0, x21
	mov	x1, x24
	bl	_amdgpu_bo_validate_size
	cbz	w0, LBB0_21
; %bb.6:
	str	x25, [sp, #32]                  ; 8-byte Folded Spill
	str	xzr, [x25]
	add	x25, x21, #8
	mov	x0, x25
	mov	x1, x24
	mov	w2, #88
	bl	_ttm_bo_dma_acc_size
	mov	x26, x0
Lloh23:
	adrp	x8, _GFP_KERNEL@GOTPAGE
Lloh24:
	ldr	x8, [x8, _GFP_KERNEL@GOTPAGEOFF]
Lloh25:
	ldr	w1, [x8]
	mov	w0, #88
	bl	_kzalloc
	str	x0, [sp, #48]
	cbz	x0, LBB0_21
; %bb.7:
	mov	x22, x0
	ldr	w0, [x21, #12]
	add	x1, x22, #20
	mov	x2, x24
	bl	_drm_gem_private_object_init
	add	x0, x22, #80
	bl	_INIT_LIST_HEAD
	str	xzr, [x22, #72]
	ldr	w8, [x19, #24]
	cbnz	w8, LBB0_9
; %bb.8:
	ldr	w8, [x19, #8]
LBB0_9:
	stp	w8, w8, [x22]
	ldr	w9, [x19, #36]
	ldr	w10, [x27]
	cmp	w9, w10
	b.eq	LBB0_12
; %bb.10:
Lloh26:
	adrp	x9, _AMDGPU_GEM_DOMAIN_VRAM@GOTPAGE
Lloh27:
	ldr	x9, [x9, _AMDGPU_GEM_DOMAIN_VRAM@GOTPAGEOFF]
Lloh28:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_12
; %bb.11:
Lloh29:
	adrp	x9, _AMDGPU_GEM_DOMAIN_GTT@GOTPAGE
Lloh30:
	ldr	x9, [x9, _AMDGPU_GEM_DOMAIN_GTT@GOTPAGEOFF]
Lloh31:
	ldr	w9, [x9]
	orr	w8, w9, w8
	str	w8, [x22, #4]
LBB0_12:
	ldr	w0, [x19, #28]
	str	w0, [x22, #8]
	bl	_amdgpu_bo_support_uswc
	cbnz	w0, LBB0_14
; %bb.13:
Lloh32:
	adrp	x8, _AMDGPU_GEM_CREATE_CPU_GTT_USWC@GOTPAGE
Lloh33:
	ldr	x8, [x8, _AMDGPU_GEM_CREATE_CPU_GTT_USWC@GOTPAGEOFF]
Lloh34:
	ldr	w8, [x8]
	ldr	w9, [x22, #8]
	bic	w8, w9, w8
	str	w8, [x22, #8]
LBB0_14:
	str	x25, [x22, #56]
	ldr	w8, [x19, #8]
	ldr	w9, [x28]
	ldr	w10, [x20]
	orr	w9, w10, w9
Lloh35:
	adrp	x10, _AMDGPU_GEM_DOMAIN_GDS@GOTPAGE
Lloh36:
	ldr	x10, [x10, _AMDGPU_GEM_DOMAIN_GDS@GOTPAGEOFF]
Lloh37:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh38:
	adrp	x10, _AMDGPU_GEM_DOMAIN_CPU@GOTPAGE
Lloh39:
	ldr	x10, [x10, _AMDGPU_GEM_DOMAIN_CPU@GOTPAGEOFF]
Lloh40:
	ldr	w10, [x10]
	tst	w9, w8
	csel	w1, w8, w10, eq
	mov	x0, x22
	bl	_amdgpu_bo_placement_from_domain
	ldr	w3, [x19, #36]
	ldr	w8, [x27]
	cmp	w3, w8
	b.ne	LBB0_16
; %bb.15:
	mov	w8, #1
	str	w8, [x22, #16]
LBB0_16:
	add	x1, x22, #16
	add	x4, x22, #64
	ldr	w8, [x19, #32]
Lloh41:
	adrp	x9, _amdgpu_bo_destroy@GOTPAGE
Lloh42:
	ldr	x9, [x9, _amdgpu_bo_destroy@GOTPAGEOFF]
	str	x9, [sp, #16]
	str	w8, [sp, #8]
	str	xzr, [sp]
	add	x6, sp, #56
	mov	x0, x25
	mov	x2, x24
	mov	x5, x23
	mov	x7, x26
	bl	_ttm_bo_init_reserved
	mov	x23, x0
	cmp	w0, #0
	cset	w0, ne
	bl	_unlikely
	cbnz	x0, LBB0_22
; %bb.17:
	mov	x0, x21
	bl	_amdgpu_gmc_vram_full_visible
	cbnz	w0, LBB0_23
; %bb.18:
	ldr	x8, [x22, #32]
Lloh43:
	adrp	x9, _TTM_PL_VRAM@GOTPAGE
Lloh44:
	ldr	x9, [x9, _TTM_PL_VRAM@GOTPAGEOFF]
Lloh45:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_23
; %bb.19:
	ldr	x8, [x22, #40]
	ldr	x9, [x21]
Lloh46:
	adrp	x10, _PAGE_SHIFT@GOTPAGE
Lloh47:
	ldr	x10, [x10, _PAGE_SHIFT@GOTPAGEOFF]
Lloh48:
	ldr	x10, [x10]
	asr	x9, x9, x10
	cmp	x8, x9
	b.ge	LBB0_23
; %bb.20:
	ldr	w1, [sp, #64]
	mov	x0, x21
	mov	x2, x1
	b	LBB0_24
LBB0_21:
Lloh49:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh50:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
Lloh51:
	ldr	w8, [x8]
	neg	w23, w8
LBB0_22:
	mov	x0, x23
	ldp	x29, x30, [sp, #160]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #144]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #128]            ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #112]            ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #96]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #80]             ; 16-byte Folded Reload
	add	sp, sp, #176
	ret
LBB0_23:
	ldr	w1, [sp, #64]
	mov	x0, x21
	mov	w2, #0
LBB0_24:
	bl	_amdgpu_cs_report_moved_bytes
	ldr	x20, [sp, #32]                  ; 8-byte Folded Reload
	ldr	w8, [x19, #28]
Lloh52:
	adrp	x9, _AMDGPU_GEM_CREATE_VRAM_CLEARED@GOTPAGE
Lloh53:
	ldr	x9, [x9, _AMDGPU_GEM_CREATE_VRAM_CLEARED@GOTPAGEOFF]
Lloh54:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_31
; %bb.25:
	ldr	w8, [x22, #48]
Lloh55:
	adrp	x9, _TTM_PL_FLAG_VRAM@GOTPAGE
Lloh56:
	ldr	x9, [x9, _TTM_PL_FLAG_VRAM@GOTPAGEOFF]
Lloh57:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_31
; %bb.26:
	ldr	w2, [x22, #20]
	add	x3, sp, #40
	mov	x0, x22
	mov	w1, #0
	bl	_amdgpu_fill_buffer
	mov	x23, x0
	bl	_unlikely
	cbz	x0, LBB0_30
; %bb.27:
	ldr	w8, [x19, #32]
	cbnz	w8, LBB0_29
; %bb.28:
	ldr	w0, [x22, #20]
	bl	_dma_resv_unlock
LBB0_29:
	add	x0, sp, #48
	bl	_amdgpu_bo_unref
	b	LBB0_22
LBB0_30:
	ldr	x1, [sp, #40]
	mov	x0, x22
	mov	w2, #0
	bl	_amdgpu_bo_fence
	ldr	x0, [x22, #24]
	bl	_dma_fence_put
	ldr	x0, [sp, #40]
	bl	_dma_fence_get
	str	x0, [x22, #24]
	ldr	x0, [sp, #40]
	bl	_dma_fence_put
LBB0_31:
	ldr	w8, [x19, #32]
	cbnz	w8, LBB0_33
; %bb.32:
	mov	x0, x22
	bl	_amdgpu_bo_unreserve
LBB0_33:
	str	x22, [x20]
	mov	x0, x22
	bl	_trace_amdgpu_bo_create
	ldr	w8, [x19, #36]
Lloh58:
	adrp	x9, _ttm_bo_type_device@GOTPAGE
Lloh59:
	ldr	x9, [x9, _ttm_bo_type_device@GOTPAGEOFF]
Lloh60:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_35
; %bb.34:
	mov	w23, #0
Lloh61:
	adrp	x8, _AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED@GOTPAGE
Lloh62:
	ldr	x8, [x8, _AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED@GOTPAGEOFF]
Lloh63:
	ldr	w8, [x8]
	ldr	w9, [x22, #8]
	bic	w8, w9, w8
	str	w8, [x22, #8]
	b	LBB0_22
LBB0_35:
	mov	w23, #0
	b	LBB0_22
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.cfi_endproc
                                        ; -- End function
	.comm	_ttm_bo_type_kernel,4,2         ; @ttm_bo_type_kernel
	.comm	_TTM_OPT_FLAG_ALLOW_RES_EVICT,4,2 ; @TTM_OPT_FLAG_ALLOW_RES_EVICT
	.comm	_AMDGPU_GEM_DOMAIN_GWS,4,2      ; @AMDGPU_GEM_DOMAIN_GWS
	.comm	_AMDGPU_GEM_DOMAIN_OA,4,2       ; @AMDGPU_GEM_DOMAIN_OA
	.comm	_PAGE_SHIFT,8,3                 ; @PAGE_SHIFT
	.comm	_AMDGPU_GEM_DOMAIN_GDS,4,2      ; @AMDGPU_GEM_DOMAIN_GDS
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
	.comm	_ENOMEM,4,2                     ; @ENOMEM
	.comm	_GFP_KERNEL,4,2                 ; @GFP_KERNEL
	.comm	_AMDGPU_GEM_DOMAIN_VRAM,4,2     ; @AMDGPU_GEM_DOMAIN_VRAM
	.comm	_AMDGPU_GEM_DOMAIN_GTT,4,2      ; @AMDGPU_GEM_DOMAIN_GTT
	.comm	_AMDGPU_GEM_CREATE_CPU_GTT_USWC,4,2 ; @AMDGPU_GEM_CREATE_CPU_GTT_USWC
	.comm	_AMDGPU_GEM_DOMAIN_CPU,4,2      ; @AMDGPU_GEM_DOMAIN_CPU
	.comm	_amdgpu_bo_destroy,4,2          ; @amdgpu_bo_destroy
	.comm	_TTM_PL_VRAM,8,3                ; @TTM_PL_VRAM
	.comm	_AMDGPU_GEM_CREATE_VRAM_CLEARED,4,2 ; @AMDGPU_GEM_CREATE_VRAM_CLEARED
	.comm	_TTM_PL_FLAG_VRAM,4,2           ; @TTM_PL_FLAG_VRAM
	.comm	_ttm_bo_type_device,4,2         ; @ttm_bo_type_device
	.comm	_AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,4,2 ; @AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
	.no_dead_strip	_amdgpu_bo_do_create
.subsections_via_symbols
