	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function a6xx_hw_init
_a6xx_hw_init:                          ## @a6xx_hw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	callq	_to_adreno_gpu
	movq	%rax, %r15
	movq	%rax, %rdi
	callq	_to_a6xx_gpu
	movq	%rax, %r14
	movq	_GMU_OOB_GPU_SET@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%rax, %rdi
	callq	_a6xx_gmu_set_oob
	movq	_REG_A6XX_RBBM_SECVID_TSB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movq	_REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	xorl	%ecx, %ecx
	callq	_gpu_write64
	movq	_REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movq	_REG_A6XX_CP_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A6XX_VSC_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A6XX_GRAS_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A6XX_RB_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A6XX_PC_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A6XX_HLSQ_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A6XX_VFD_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A6XX_VPC_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A6XX_UCHE_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A6XX_SP_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A6XX_TPL1_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	%rbx, %rdi
	movl	$1, %esi
	callq	_a6xx_set_hwcg
	movq	_REG_A6XX_VBIF_GATE_OFF_WRREQ_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$9, %edx
	callq	_gpu_write
	movq	_REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$3, %edx
	callq	_gpu_write
	movq	_REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$-1, %edx
	callq	_gpu_write
	movq	_REG_A6XX_UCHE_WRITE_RANGE_MAX_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$-64, %edx
	callq	_gpu_write
	movq	_REG_A6XX_UCHE_WRITE_RANGE_MAX_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$131071, %edx                   ## imm = 0x1FFFF
	callq	_gpu_write
	movq	_REG_A6XX_UCHE_TRAP_BASE_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$-4096, %edx                    ## imm = 0xF000
	callq	_gpu_write
	movq	_REG_A6XX_UCHE_TRAP_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$131071, %edx                   ## imm = 0x1FFFF
	callq	_gpu_write
	movq	_REG_A6XX_UCHE_WRITE_THRU_BASE_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$-4096, %edx                    ## imm = 0xF000
	callq	_gpu_write
	movq	_REG_A6XX_UCHE_WRITE_THRU_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$131071, %edx                   ## imm = 0x1FFFF
	callq	_gpu_write
	movq	_REG_A6XX_UCHE_GMEM_RANGE_MIN_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_REG_A6XX_UCHE_GMEM_RANGE_MIN_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	movl	$1048576, %ecx                  ## imm = 0x100000
	callq	_gpu_write64
	movq	_REG_A6XX_UCHE_GMEM_RANGE_MAX_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_REG_A6XX_UCHE_GMEM_RANGE_MAX_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	$1048575, %ecx                  ## imm = 0xFFFFF
	addl	(%r15), %ecx
	movq	%rbx, %rdi
	callq	_gpu_write64
	movq	_REG_A6XX_UCHE_FILTER_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$2052, %edx                     ## imm = 0x804
	callq	_gpu_write
	movq	_REG_A6XX_UCHE_CACHE_WAYS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$4, %edx
	callq	_gpu_write
	movq	_REG_A6XX_CP_ROQ_THRESHOLDS_2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$16777408, %edx                 ## imm = 0x10000C0
	callq	_gpu_write
	movq	_REG_A6XX_CP_ROQ_THRESHOLDS_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$-2143275476, %edx              ## imm = 0x8040362C
	callq	_gpu_write
	movq	_REG_A6XX_CP_MEM_POOL_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$128, %edx
	callq	_gpu_write
	movq	_REG_A6XX_PC_DBG_ECO_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1572864, %edx                  ## imm = 0x180000
	callq	_gpu_write
	movq	_REG_A6XX_CP_AHB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A6XX_RBBM_PERFCTR_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A6XX_CP_PERFCTR_CP_SEL_0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PERF_CP_ALWAYS_COUNT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_gpu_write
	movq	_REG_A6XX_RB_NC_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$4, %edx
	callq	_gpu_write
	movq	_REG_A6XX_TPL1_NC_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$4, %edx
	callq	_gpu_write
	movq	_REG_A6XX_SP_NC_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$4, %edx
	callq	_gpu_write
	movq	_REG_A6XX_UCHE_MODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$4194304, %edx                  ## imm = 0x400000
	callq	_gpu_write
	movq	_REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1075838975, %edx               ## imm = 0x401FFFFF
	callq	_gpu_write
	movq	_REG_A6XX_UCHE_CLIENT_PF@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A6XX_CP_PROTECT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$3, %edx
	callq	_gpu_write
	xorl	%edi, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$1536, %edi                     ## imm = 0x600
	movl	$81, %esi
	callq	_A6XX_PROTECT_RDONLY
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$1, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$44624, %edi                    ## imm = 0xAE50
	movl	$2, %esi
	callq	_A6XX_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$2, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$38436, %edi                    ## imm = 0x9624
	movl	$19, %esi
	callq	_A6XX_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$3, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$34352, %edi                    ## imm = 0x8630
	movl	$8, %esi
	callq	_A6XX_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$4, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$40560, %edi                    ## imm = 0x9E70
	movl	$1, %esi
	callq	_A6XX_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$5, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$40568, %edi                    ## imm = 0x9E78
	movl	$391, %esi                      ## imm = 0x187
	callq	_A6XX_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$6, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$61440, %edi                    ## imm = 0xF000
	movl	$2064, %esi                     ## imm = 0x810
	callq	_A6XX_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$7, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$64512, %edi                    ## imm = 0xFC00
	movl	$3, %esi
	callq	_A6XX_PROTECT_RDONLY
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$8, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$1294, %edi                     ## imm = 0x50E
	xorl	%esi, %esi
	callq	_A6XX_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$9, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$1295, %edi                     ## imm = 0x50F
	xorl	%esi, %esi
	callq	_A6XX_PROTECT_RDONLY
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$10, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$1296, %edi                     ## imm = 0x510
	xorl	%esi, %esi
	callq	_A6XX_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$11, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	xorl	%edi, %edi
	movl	$1273, %esi                     ## imm = 0x4F9
	callq	_A6XX_PROTECT_RDONLY
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$12, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$1281, %edi                     ## imm = 0x501
	movl	$10, %esi
	callq	_A6XX_PROTECT_RDONLY
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$13, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$1297, %edi                     ## imm = 0x511
	movl	$68, %esi
	callq	_A6XX_PROTECT_RDONLY
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$14, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$3584, %edi                     ## imm = 0xE00
	movl	$14, %esi
	callq	_A6XX_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$15, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$36352, %edi                    ## imm = 0x8E00
	xorl	%esi, %esi
	callq	_A6XX_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$16, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$36432, %edi                    ## imm = 0x8E50
	movl	$15, %esi
	callq	_A6XX_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$17, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$48642, %edi                    ## imm = 0xBE02
	xorl	%esi, %esi
	callq	_A6XX_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$18, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$48672, %edi                    ## imm = 0xBE20
	movl	$4595, %esi                     ## imm = 0x11F3
	callq	_A6XX_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$19, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$2048, %edi                     ## imm = 0x800
	movl	$130, %esi
	callq	_A6XX_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$20, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$2208, %edi                     ## imm = 0x8A0
	movl	$8, %esi
	callq	_A6XX_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$21, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$2219, %edi                     ## imm = 0x8AB
	movl	$25, %esi
	callq	_A6XX_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$22, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$2304, %edi                     ## imm = 0x900
	movl	$77, %esi
	callq	_A6XX_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$23, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$2445, %edi                     ## imm = 0x98D
	movl	$118, %esi
	callq	_A6XX_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$24, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$2432, %edi                     ## imm = 0x980
	movl	$4, %esi
	callq	_A6XX_PROTECT_RDONLY
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movl	$25, %edi
	callq	_REG_A6XX_CP_PROTECT
	movl	%eax, %r15d
	movl	$42544, %edi                    ## imm = 0xA630
	xorl	%esi, %esi
	callq	_A6XX_PROTECT_RW
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_gpu_write
	movq	_REG_A6XX_RBBM_INT_0_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_A6XX_INT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_gpu_write
	movq	%rbx, %rdi
	callq	_adreno_hw_init
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	LBB0_7
## %bb.1:
	movq	%rbx, %rdi
	callq	_a6xx_ucode_init
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	LBB0_7
## %bb.2:
	movq	8(%rbx), %rax
	movl	(%rax), %eax
	movl	%eax, 4(%r14)
	movq	_REG_A6XX_CP_SQE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_gpu_write
	movq	%rbx, %rdi
	callq	_a6xx_cp_init
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	LBB0_7
## %bb.3:
	movq	%rbx, %rdi
	callq	_a6xx_zap_shader_init
	testl	%eax, %eax
	je	LBB0_4
## %bb.6:
	movq	(%rbx), %rax
	movl	(%rax), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_warn_once
	movq	_REG_A6XX_RBBM_SECVID_TRUST_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%r15d, %r15d
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	jmp	LBB0_7
LBB0_4:
	movq	8(%rbx), %rax
	movl	(%rax), %edi
	movq	_CP_SET_SECURE_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %edx
	callq	_OUT_PKT7
	movq	8(%rbx), %rax
	movl	(%rax), %edi
	xorl	%r15d, %r15d
	xorl	%esi, %esi
	callq	_OUT_RING
	movq	8(%rbx), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_a6xx_flush
	movq	8(%rbx), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_a6xx_idle
	testl	%eax, %eax
	je	LBB0_5
LBB0_7:
	movl	(%r12), %esi
	movq	%r14, %rdi
	callq	_a6xx_gmu_clear_oob
	movq	_GMU_OOB_BOOT_SLUMBER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_a6xx_gmu_clear_oob
LBB0_8:
	movl	%r15d, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_5:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r15d, %r15d
	subl	(%rax), %r15d
	jmp	LBB0_8
	.cfi_endproc
                                        ## -- End function
	.comm	_GMU_OOB_GPU_SET,4,2            ## @GMU_OOB_GPU_SET
	.comm	_REG_A6XX_RBBM_SECVID_TSB_CNTL,4,2 ## @REG_A6XX_RBBM_SECVID_TSB_CNTL
	.comm	_REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO,4,2 ## @REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO
	.comm	_REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI,4,2 ## @REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI
	.comm	_REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE,4,2 ## @REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE
	.comm	_REG_A6XX_CP_ADDR_MODE_CNTL,4,2 ## @REG_A6XX_CP_ADDR_MODE_CNTL
	.comm	_REG_A6XX_VSC_ADDR_MODE_CNTL,4,2 ## @REG_A6XX_VSC_ADDR_MODE_CNTL
	.comm	_REG_A6XX_GRAS_ADDR_MODE_CNTL,4,2 ## @REG_A6XX_GRAS_ADDR_MODE_CNTL
	.comm	_REG_A6XX_RB_ADDR_MODE_CNTL,4,2 ## @REG_A6XX_RB_ADDR_MODE_CNTL
	.comm	_REG_A6XX_PC_ADDR_MODE_CNTL,4,2 ## @REG_A6XX_PC_ADDR_MODE_CNTL
	.comm	_REG_A6XX_HLSQ_ADDR_MODE_CNTL,4,2 ## @REG_A6XX_HLSQ_ADDR_MODE_CNTL
	.comm	_REG_A6XX_VFD_ADDR_MODE_CNTL,4,2 ## @REG_A6XX_VFD_ADDR_MODE_CNTL
	.comm	_REG_A6XX_VPC_ADDR_MODE_CNTL,4,2 ## @REG_A6XX_VPC_ADDR_MODE_CNTL
	.comm	_REG_A6XX_UCHE_ADDR_MODE_CNTL,4,2 ## @REG_A6XX_UCHE_ADDR_MODE_CNTL
	.comm	_REG_A6XX_SP_ADDR_MODE_CNTL,4,2 ## @REG_A6XX_SP_ADDR_MODE_CNTL
	.comm	_REG_A6XX_TPL1_ADDR_MODE_CNTL,4,2 ## @REG_A6XX_TPL1_ADDR_MODE_CNTL
	.comm	_REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL,4,2 ## @REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL
	.comm	_REG_A6XX_VBIF_GATE_OFF_WRREQ_EN,4,2 ## @REG_A6XX_VBIF_GATE_OFF_WRREQ_EN
	.comm	_REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL,4,2 ## @REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL
	.comm	_REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED,4,2 ## @REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED
	.comm	_REG_A6XX_UCHE_WRITE_RANGE_MAX_LO,4,2 ## @REG_A6XX_UCHE_WRITE_RANGE_MAX_LO
	.comm	_REG_A6XX_UCHE_WRITE_RANGE_MAX_HI,4,2 ## @REG_A6XX_UCHE_WRITE_RANGE_MAX_HI
	.comm	_REG_A6XX_UCHE_TRAP_BASE_LO,4,2 ## @REG_A6XX_UCHE_TRAP_BASE_LO
	.comm	_REG_A6XX_UCHE_TRAP_BASE_HI,4,2 ## @REG_A6XX_UCHE_TRAP_BASE_HI
	.comm	_REG_A6XX_UCHE_WRITE_THRU_BASE_LO,4,2 ## @REG_A6XX_UCHE_WRITE_THRU_BASE_LO
	.comm	_REG_A6XX_UCHE_WRITE_THRU_BASE_HI,4,2 ## @REG_A6XX_UCHE_WRITE_THRU_BASE_HI
	.comm	_REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,4,2 ## @REG_A6XX_UCHE_GMEM_RANGE_MIN_LO
	.comm	_REG_A6XX_UCHE_GMEM_RANGE_MIN_HI,4,2 ## @REG_A6XX_UCHE_GMEM_RANGE_MIN_HI
	.comm	_REG_A6XX_UCHE_GMEM_RANGE_MAX_LO,4,2 ## @REG_A6XX_UCHE_GMEM_RANGE_MAX_LO
	.comm	_REG_A6XX_UCHE_GMEM_RANGE_MAX_HI,4,2 ## @REG_A6XX_UCHE_GMEM_RANGE_MAX_HI
	.comm	_REG_A6XX_UCHE_FILTER_CNTL,4,2  ## @REG_A6XX_UCHE_FILTER_CNTL
	.comm	_REG_A6XX_UCHE_CACHE_WAYS,4,2   ## @REG_A6XX_UCHE_CACHE_WAYS
	.comm	_REG_A6XX_CP_ROQ_THRESHOLDS_2,4,2 ## @REG_A6XX_CP_ROQ_THRESHOLDS_2
	.comm	_REG_A6XX_CP_ROQ_THRESHOLDS_1,4,2 ## @REG_A6XX_CP_ROQ_THRESHOLDS_1
	.comm	_REG_A6XX_CP_MEM_POOL_SIZE,4,2  ## @REG_A6XX_CP_MEM_POOL_SIZE
	.comm	_REG_A6XX_PC_DBG_ECO_CNTL,4,2   ## @REG_A6XX_PC_DBG_ECO_CNTL
	.comm	_REG_A6XX_CP_AHB_CNTL,4,2       ## @REG_A6XX_CP_AHB_CNTL
	.comm	_REG_A6XX_RBBM_PERFCTR_CNTL,4,2 ## @REG_A6XX_RBBM_PERFCTR_CNTL
	.comm	_REG_A6XX_CP_PERFCTR_CP_SEL_0,4,2 ## @REG_A6XX_CP_PERFCTR_CP_SEL_0
	.comm	_PERF_CP_ALWAYS_COUNT,4,2       ## @PERF_CP_ALWAYS_COUNT
	.comm	_REG_A6XX_RB_NC_MODE_CNTL,4,2   ## @REG_A6XX_RB_NC_MODE_CNTL
	.comm	_REG_A6XX_TPL1_NC_MODE_CNTL,4,2 ## @REG_A6XX_TPL1_NC_MODE_CNTL
	.comm	_REG_A6XX_SP_NC_MODE_CNTL,4,2   ## @REG_A6XX_SP_NC_MODE_CNTL
	.comm	_REG_A6XX_UCHE_MODE_CNTL,4,2    ## @REG_A6XX_UCHE_MODE_CNTL
	.comm	_REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL,4,2 ## @REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL
	.comm	_REG_A6XX_UCHE_CLIENT_PF,4,2    ## @REG_A6XX_UCHE_CLIENT_PF
	.comm	_REG_A6XX_CP_PROTECT_CNTL,4,2   ## @REG_A6XX_CP_PROTECT_CNTL
	.comm	_REG_A6XX_RBBM_INT_0_MASK,4,2   ## @REG_A6XX_RBBM_INT_0_MASK
	.comm	_A6XX_INT_MASK,4,2              ## @A6XX_INT_MASK
	.comm	_REG_A6XX_CP_SQE_CNTL,4,2       ## @REG_A6XX_CP_SQE_CNTL
	.comm	_CP_SET_SECURE_MODE,4,2         ## @CP_SET_SECURE_MODE
	.comm	_EINVAL,4,2                     ## @EINVAL
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"

	.comm	_REG_A6XX_RBBM_SECVID_TRUST_CNTL,4,2 ## @REG_A6XX_RBBM_SECVID_TRUST_CNTL
	.comm	_GMU_OOB_BOOT_SLUMBER,4,2       ## @GMU_OOB_BOOT_SLUMBER
	.no_dead_strip	_a6xx_hw_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function a6xx_hw_init
_a6xx_hw_init:                          ; @a6xx_hw_init
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x0
	bl	_to_adreno_gpu
	mov	x21, x0
	bl	_to_a6xx_gpu
	mov	x19, x0
Lloh0:
	adrp	x22, _GMU_OOB_GPU_SET@GOTPAGE
Lloh1:
	ldr	x22, [x22, _GMU_OOB_GPU_SET@GOTPAGEOFF]
	ldr	w1, [x22]
	bl	_a6xx_gmu_set_oob
Lloh2:
	adrp	x8, _REG_A6XX_RBBM_SECVID_TSB_CNTL@GOTPAGE
Lloh3:
	ldr	x8, [x8, _REG_A6XX_RBBM_SECVID_TSB_CNTL@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #0
	bl	_gpu_write
Lloh5:
	adrp	x8, _REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO@GOTPAGE
Lloh6:
	ldr	x8, [x8, _REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO@GOTPAGEOFF]
Lloh7:
	ldr	w1, [x8]
Lloh8:
	adrp	x8, _REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI@GOTPAGE
Lloh9:
	ldr	x8, [x8, _REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	x0, x20
	mov	w3, #0
	bl	_gpu_write64
Lloh11:
	adrp	x8, _REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE@GOTPAGE
Lloh12:
	ldr	x8, [x8, _REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #0
	bl	_gpu_write
Lloh14:
	adrp	x8, _REG_A6XX_CP_ADDR_MODE_CNTL@GOTPAGE
Lloh15:
	ldr	x8, [x8, _REG_A6XX_CP_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #1
	bl	_gpu_write
Lloh17:
	adrp	x8, _REG_A6XX_VSC_ADDR_MODE_CNTL@GOTPAGE
Lloh18:
	ldr	x8, [x8, _REG_A6XX_VSC_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh19:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #1
	bl	_gpu_write
Lloh20:
	adrp	x8, _REG_A6XX_GRAS_ADDR_MODE_CNTL@GOTPAGE
Lloh21:
	ldr	x8, [x8, _REG_A6XX_GRAS_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh22:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #1
	bl	_gpu_write
Lloh23:
	adrp	x8, _REG_A6XX_RB_ADDR_MODE_CNTL@GOTPAGE
Lloh24:
	ldr	x8, [x8, _REG_A6XX_RB_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh25:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #1
	bl	_gpu_write
Lloh26:
	adrp	x8, _REG_A6XX_PC_ADDR_MODE_CNTL@GOTPAGE
Lloh27:
	ldr	x8, [x8, _REG_A6XX_PC_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh28:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #1
	bl	_gpu_write
Lloh29:
	adrp	x8, _REG_A6XX_HLSQ_ADDR_MODE_CNTL@GOTPAGE
Lloh30:
	ldr	x8, [x8, _REG_A6XX_HLSQ_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh31:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #1
	bl	_gpu_write
Lloh32:
	adrp	x8, _REG_A6XX_VFD_ADDR_MODE_CNTL@GOTPAGE
Lloh33:
	ldr	x8, [x8, _REG_A6XX_VFD_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh34:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #1
	bl	_gpu_write
Lloh35:
	adrp	x8, _REG_A6XX_VPC_ADDR_MODE_CNTL@GOTPAGE
Lloh36:
	ldr	x8, [x8, _REG_A6XX_VPC_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh37:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #1
	bl	_gpu_write
Lloh38:
	adrp	x8, _REG_A6XX_UCHE_ADDR_MODE_CNTL@GOTPAGE
Lloh39:
	ldr	x8, [x8, _REG_A6XX_UCHE_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh40:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #1
	bl	_gpu_write
Lloh41:
	adrp	x8, _REG_A6XX_SP_ADDR_MODE_CNTL@GOTPAGE
Lloh42:
	ldr	x8, [x8, _REG_A6XX_SP_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh43:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #1
	bl	_gpu_write
Lloh44:
	adrp	x8, _REG_A6XX_TPL1_ADDR_MODE_CNTL@GOTPAGE
Lloh45:
	ldr	x8, [x8, _REG_A6XX_TPL1_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh46:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #1
	bl	_gpu_write
Lloh47:
	adrp	x8, _REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL@GOTPAGE
Lloh48:
	ldr	x8, [x8, _REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL@GOTPAGEOFF]
Lloh49:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #1
	bl	_gpu_write
	mov	x0, x20
	mov	w1, #1
	bl	_a6xx_set_hwcg
Lloh50:
	adrp	x8, _REG_A6XX_VBIF_GATE_OFF_WRREQ_EN@GOTPAGE
Lloh51:
	ldr	x8, [x8, _REG_A6XX_VBIF_GATE_OFF_WRREQ_EN@GOTPAGEOFF]
Lloh52:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #9
	bl	_gpu_write
Lloh53:
	adrp	x8, _REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL@GOTPAGE
Lloh54:
	ldr	x8, [x8, _REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL@GOTPAGEOFF]
Lloh55:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #3
	bl	_gpu_write
Lloh56:
	adrp	x8, _REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED@GOTPAGE
Lloh57:
	ldr	x8, [x8, _REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED@GOTPAGEOFF]
Lloh58:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #-1
	bl	_gpu_write
Lloh59:
	adrp	x8, _REG_A6XX_UCHE_WRITE_RANGE_MAX_LO@GOTPAGE
Lloh60:
	ldr	x8, [x8, _REG_A6XX_UCHE_WRITE_RANGE_MAX_LO@GOTPAGEOFF]
Lloh61:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #-64
	bl	_gpu_write
Lloh62:
	adrp	x8, _REG_A6XX_UCHE_WRITE_RANGE_MAX_HI@GOTPAGE
Lloh63:
	ldr	x8, [x8, _REG_A6XX_UCHE_WRITE_RANGE_MAX_HI@GOTPAGEOFF]
Lloh64:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #131071
	bl	_gpu_write
Lloh65:
	adrp	x8, _REG_A6XX_UCHE_TRAP_BASE_LO@GOTPAGE
Lloh66:
	ldr	x8, [x8, _REG_A6XX_UCHE_TRAP_BASE_LO@GOTPAGEOFF]
Lloh67:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #-4096
	bl	_gpu_write
Lloh68:
	adrp	x8, _REG_A6XX_UCHE_TRAP_BASE_HI@GOTPAGE
Lloh69:
	ldr	x8, [x8, _REG_A6XX_UCHE_TRAP_BASE_HI@GOTPAGEOFF]
Lloh70:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #131071
	bl	_gpu_write
Lloh71:
	adrp	x8, _REG_A6XX_UCHE_WRITE_THRU_BASE_LO@GOTPAGE
Lloh72:
	ldr	x8, [x8, _REG_A6XX_UCHE_WRITE_THRU_BASE_LO@GOTPAGEOFF]
Lloh73:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #-4096
	bl	_gpu_write
Lloh74:
	adrp	x8, _REG_A6XX_UCHE_WRITE_THRU_BASE_HI@GOTPAGE
Lloh75:
	ldr	x8, [x8, _REG_A6XX_UCHE_WRITE_THRU_BASE_HI@GOTPAGEOFF]
Lloh76:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #131071
	bl	_gpu_write
Lloh77:
	adrp	x8, _REG_A6XX_UCHE_GMEM_RANGE_MIN_LO@GOTPAGE
Lloh78:
	ldr	x8, [x8, _REG_A6XX_UCHE_GMEM_RANGE_MIN_LO@GOTPAGEOFF]
Lloh79:
	ldr	w1, [x8]
Lloh80:
	adrp	x8, _REG_A6XX_UCHE_GMEM_RANGE_MIN_HI@GOTPAGE
Lloh81:
	ldr	x8, [x8, _REG_A6XX_UCHE_GMEM_RANGE_MIN_HI@GOTPAGEOFF]
Lloh82:
	ldr	w2, [x8]
	mov	x0, x20
	mov	w3, #1048576
	bl	_gpu_write64
Lloh83:
	adrp	x8, _REG_A6XX_UCHE_GMEM_RANGE_MAX_LO@GOTPAGE
Lloh84:
	ldr	x8, [x8, _REG_A6XX_UCHE_GMEM_RANGE_MAX_LO@GOTPAGEOFF]
Lloh85:
	ldr	w1, [x8]
Lloh86:
	adrp	x8, _REG_A6XX_UCHE_GMEM_RANGE_MAX_HI@GOTPAGE
Lloh87:
	ldr	x8, [x8, _REG_A6XX_UCHE_GMEM_RANGE_MAX_HI@GOTPAGEOFF]
Lloh88:
	ldr	w2, [x8]
	ldr	w8, [x21]
	mov	w9, #1048575
	add	w3, w8, w9
	mov	x0, x20
	bl	_gpu_write64
Lloh89:
	adrp	x8, _REG_A6XX_UCHE_FILTER_CNTL@GOTPAGE
Lloh90:
	ldr	x8, [x8, _REG_A6XX_UCHE_FILTER_CNTL@GOTPAGEOFF]
Lloh91:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #2052
	bl	_gpu_write
Lloh92:
	adrp	x8, _REG_A6XX_UCHE_CACHE_WAYS@GOTPAGE
Lloh93:
	ldr	x8, [x8, _REG_A6XX_UCHE_CACHE_WAYS@GOTPAGEOFF]
Lloh94:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #4
	bl	_gpu_write
Lloh95:
	adrp	x8, _REG_A6XX_CP_ROQ_THRESHOLDS_2@GOTPAGE
Lloh96:
	ldr	x8, [x8, _REG_A6XX_CP_ROQ_THRESHOLDS_2@GOTPAGEOFF]
Lloh97:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #192
	movk	w2, #256, lsl #16
	bl	_gpu_write
Lloh98:
	adrp	x8, _REG_A6XX_CP_ROQ_THRESHOLDS_1@GOTPAGE
Lloh99:
	ldr	x8, [x8, _REG_A6XX_CP_ROQ_THRESHOLDS_1@GOTPAGEOFF]
Lloh100:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #13868
	movk	w2, #32832, lsl #16
	bl	_gpu_write
Lloh101:
	adrp	x8, _REG_A6XX_CP_MEM_POOL_SIZE@GOTPAGE
Lloh102:
	ldr	x8, [x8, _REG_A6XX_CP_MEM_POOL_SIZE@GOTPAGEOFF]
Lloh103:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #128
	bl	_gpu_write
Lloh104:
	adrp	x8, _REG_A6XX_PC_DBG_ECO_CNTL@GOTPAGE
Lloh105:
	ldr	x8, [x8, _REG_A6XX_PC_DBG_ECO_CNTL@GOTPAGEOFF]
Lloh106:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #1572864
	bl	_gpu_write
Lloh107:
	adrp	x8, _REG_A6XX_CP_AHB_CNTL@GOTPAGE
Lloh108:
	ldr	x8, [x8, _REG_A6XX_CP_AHB_CNTL@GOTPAGEOFF]
Lloh109:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #1
	bl	_gpu_write
Lloh110:
	adrp	x8, _REG_A6XX_RBBM_PERFCTR_CNTL@GOTPAGE
Lloh111:
	ldr	x8, [x8, _REG_A6XX_RBBM_PERFCTR_CNTL@GOTPAGEOFF]
Lloh112:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #1
	bl	_gpu_write
Lloh113:
	adrp	x8, _REG_A6XX_CP_PERFCTR_CP_SEL_0@GOTPAGE
Lloh114:
	ldr	x8, [x8, _REG_A6XX_CP_PERFCTR_CP_SEL_0@GOTPAGEOFF]
Lloh115:
	ldr	w1, [x8]
Lloh116:
	adrp	x8, _PERF_CP_ALWAYS_COUNT@GOTPAGE
Lloh117:
	ldr	x8, [x8, _PERF_CP_ALWAYS_COUNT@GOTPAGEOFF]
Lloh118:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_gpu_write
Lloh119:
	adrp	x8, _REG_A6XX_RB_NC_MODE_CNTL@GOTPAGE
Lloh120:
	ldr	x8, [x8, _REG_A6XX_RB_NC_MODE_CNTL@GOTPAGEOFF]
Lloh121:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #4
	bl	_gpu_write
Lloh122:
	adrp	x8, _REG_A6XX_TPL1_NC_MODE_CNTL@GOTPAGE
Lloh123:
	ldr	x8, [x8, _REG_A6XX_TPL1_NC_MODE_CNTL@GOTPAGEOFF]
Lloh124:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #4
	bl	_gpu_write
Lloh125:
	adrp	x8, _REG_A6XX_SP_NC_MODE_CNTL@GOTPAGE
Lloh126:
	ldr	x8, [x8, _REG_A6XX_SP_NC_MODE_CNTL@GOTPAGEOFF]
Lloh127:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #4
	bl	_gpu_write
Lloh128:
	adrp	x8, _REG_A6XX_UCHE_MODE_CNTL@GOTPAGE
Lloh129:
	ldr	x8, [x8, _REG_A6XX_UCHE_MODE_CNTL@GOTPAGEOFF]
Lloh130:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #4194304
	bl	_gpu_write
Lloh131:
	adrp	x8, _REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL@GOTPAGE
Lloh132:
	ldr	x8, [x8, _REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL@GOTPAGEOFF]
Lloh133:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #1075838975
	bl	_gpu_write
Lloh134:
	adrp	x8, _REG_A6XX_UCHE_CLIENT_PF@GOTPAGE
Lloh135:
	ldr	x8, [x8, _REG_A6XX_UCHE_CLIENT_PF@GOTPAGEOFF]
Lloh136:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #1
	bl	_gpu_write
Lloh137:
	adrp	x8, _REG_A6XX_CP_PROTECT_CNTL@GOTPAGE
Lloh138:
	ldr	x8, [x8, _REG_A6XX_CP_PROTECT_CNTL@GOTPAGEOFF]
Lloh139:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #3
	bl	_gpu_write
	mov	w0, #0
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #1536
	mov	w1, #81
	bl	_A6XX_PROTECT_RDONLY
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #1
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #44624
	mov	w1, #2
	bl	_A6XX_PROTECT_RW
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #2
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #38436
	mov	w1, #19
	bl	_A6XX_PROTECT_RW
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #3
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #34352
	mov	w1, #8
	bl	_A6XX_PROTECT_RW
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #4
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #40560
	mov	w1, #1
	bl	_A6XX_PROTECT_RW
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #5
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #40568
	mov	w1, #391
	bl	_A6XX_PROTECT_RW
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #6
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #61440
	mov	w1, #2064
	bl	_A6XX_PROTECT_RW
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #7
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #64512
	mov	w1, #3
	bl	_A6XX_PROTECT_RDONLY
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #8
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #1294
	mov	w1, #0
	bl	_A6XX_PROTECT_RW
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #9
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #1295
	mov	w1, #0
	bl	_A6XX_PROTECT_RDONLY
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #10
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #1296
	mov	w1, #0
	bl	_A6XX_PROTECT_RW
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #11
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #0
	mov	w1, #1273
	bl	_A6XX_PROTECT_RDONLY
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #12
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #1281
	mov	w1, #10
	bl	_A6XX_PROTECT_RDONLY
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #13
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #1297
	mov	w1, #68
	bl	_A6XX_PROTECT_RDONLY
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #14
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #3584
	mov	w1, #14
	bl	_A6XX_PROTECT_RW
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #15
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #36352
	mov	w1, #0
	bl	_A6XX_PROTECT_RW
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #16
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #36432
	mov	w1, #15
	bl	_A6XX_PROTECT_RW
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #17
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #48642
	mov	w1, #0
	bl	_A6XX_PROTECT_RW
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #18
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #48672
	mov	w1, #4595
	bl	_A6XX_PROTECT_RW
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #19
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #2048
	mov	w1, #130
	bl	_A6XX_PROTECT_RW
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #20
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #2208
	mov	w1, #8
	bl	_A6XX_PROTECT_RW
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #21
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #2219
	mov	w1, #25
	bl	_A6XX_PROTECT_RW
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #22
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #2304
	mov	w1, #77
	bl	_A6XX_PROTECT_RW
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #23
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #2445
	mov	w1, #118
	bl	_A6XX_PROTECT_RW
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #24
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #2432
	mov	w1, #4
	bl	_A6XX_PROTECT_RDONLY
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
	mov	w0, #25
	bl	_REG_A6XX_CP_PROTECT
	mov	x21, x0
	mov	w0, #42544
	mov	w1, #0
	bl	_A6XX_PROTECT_RW
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_gpu_write
Lloh140:
	adrp	x8, _REG_A6XX_RBBM_INT_0_MASK@GOTPAGE
Lloh141:
	ldr	x8, [x8, _REG_A6XX_RBBM_INT_0_MASK@GOTPAGEOFF]
Lloh142:
	ldr	w1, [x8]
Lloh143:
	adrp	x8, _A6XX_INT_MASK@GOTPAGE
Lloh144:
	ldr	x8, [x8, _A6XX_INT_MASK@GOTPAGEOFF]
Lloh145:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_gpu_write
	mov	x0, x20
	bl	_adreno_hw_init
	mov	x21, x0
	cbnz	w0, LBB0_6
; %bb.1:
	mov	x0, x20
	bl	_a6xx_ucode_init
	mov	x21, x0
	cbnz	w0, LBB0_6
; %bb.2:
	ldr	x8, [x20, #8]
	ldr	w8, [x8]
	str	w8, [x19, #4]
Lloh146:
	adrp	x8, _REG_A6XX_CP_SQE_CNTL@GOTPAGE
Lloh147:
	ldr	x8, [x8, _REG_A6XX_CP_SQE_CNTL@GOTPAGEOFF]
Lloh148:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #1
	bl	_gpu_write
	mov	x0, x20
	bl	_a6xx_cp_init
	mov	x21, x0
	cbnz	w0, LBB0_6
; %bb.3:
	mov	x0, x20
	bl	_a6xx_zap_shader_init
	cbz	w0, LBB0_5
; %bb.4:
	ldr	x8, [x20]
	ldr	w0, [x8]
Lloh149:
	adrp	x1, l_.str@PAGE
Lloh150:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_warn_once
Lloh151:
	adrp	x8, _REG_A6XX_RBBM_SECVID_TRUST_CNTL@GOTPAGE
Lloh152:
	ldr	x8, [x8, _REG_A6XX_RBBM_SECVID_TRUST_CNTL@GOTPAGEOFF]
Lloh153:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #0
	bl	_gpu_write
	mov	w21, #0
	b	LBB0_6
LBB0_5:
	ldr	x8, [x20, #8]
	ldr	w0, [x8]
Lloh154:
	adrp	x8, _CP_SET_SECURE_MODE@GOTPAGE
Lloh155:
	ldr	x8, [x8, _CP_SET_SECURE_MODE@GOTPAGEOFF]
Lloh156:
	ldr	w1, [x8]
	mov	w2, #1
	bl	_OUT_PKT7
	ldr	x8, [x20, #8]
	ldr	w0, [x8]
	mov	w1, #0
	bl	_OUT_RING
	ldr	x8, [x20, #8]
	ldr	w1, [x8]
	mov	x0, x20
	bl	_a6xx_flush
	ldr	x8, [x20, #8]
	ldr	w1, [x8]
	mov	x0, x20
	bl	_a6xx_idle
	mov	w21, #0
	cbz	w0, LBB0_8
LBB0_6:
	ldr	w1, [x22]
	mov	x0, x19
	bl	_a6xx_gmu_clear_oob
Lloh157:
	adrp	x8, _GMU_OOB_BOOT_SLUMBER@GOTPAGE
Lloh158:
	ldr	x8, [x8, _GMU_OOB_BOOT_SLUMBER@GOTPAGEOFF]
Lloh159:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_a6xx_gmu_clear_oob
LBB0_7:
	mov	x0, x21
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_8:
Lloh160:
	adrp	x8, _EINVAL@GOTPAGE
Lloh161:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh162:
	ldr	w8, [x8]
	neg	w21, w8
	b	LBB0_7
	.loh AdrpLdrGotLdr	Lloh143, Lloh144, Lloh145
	.loh AdrpLdrGotLdr	Lloh140, Lloh141, Lloh142
	.loh AdrpLdrGotLdr	Lloh137, Lloh138, Lloh139
	.loh AdrpLdrGotLdr	Lloh134, Lloh135, Lloh136
	.loh AdrpLdrGotLdr	Lloh131, Lloh132, Lloh133
	.loh AdrpLdrGotLdr	Lloh128, Lloh129, Lloh130
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh146, Lloh147, Lloh148
	.loh AdrpLdrGotLdr	Lloh151, Lloh152, Lloh153
	.loh AdrpAdd	Lloh149, Lloh150
	.loh AdrpLdrGotLdr	Lloh154, Lloh155, Lloh156
	.loh AdrpLdrGotLdr	Lloh157, Lloh158, Lloh159
	.loh AdrpLdrGotLdr	Lloh160, Lloh161, Lloh162
	.cfi_endproc
                                        ; -- End function
	.comm	_GMU_OOB_GPU_SET,4,2            ; @GMU_OOB_GPU_SET
	.comm	_REG_A6XX_RBBM_SECVID_TSB_CNTL,4,2 ; @REG_A6XX_RBBM_SECVID_TSB_CNTL
	.comm	_REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO,4,2 ; @REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO
	.comm	_REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI,4,2 ; @REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI
	.comm	_REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE,4,2 ; @REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE
	.comm	_REG_A6XX_CP_ADDR_MODE_CNTL,4,2 ; @REG_A6XX_CP_ADDR_MODE_CNTL
	.comm	_REG_A6XX_VSC_ADDR_MODE_CNTL,4,2 ; @REG_A6XX_VSC_ADDR_MODE_CNTL
	.comm	_REG_A6XX_GRAS_ADDR_MODE_CNTL,4,2 ; @REG_A6XX_GRAS_ADDR_MODE_CNTL
	.comm	_REG_A6XX_RB_ADDR_MODE_CNTL,4,2 ; @REG_A6XX_RB_ADDR_MODE_CNTL
	.comm	_REG_A6XX_PC_ADDR_MODE_CNTL,4,2 ; @REG_A6XX_PC_ADDR_MODE_CNTL
	.comm	_REG_A6XX_HLSQ_ADDR_MODE_CNTL,4,2 ; @REG_A6XX_HLSQ_ADDR_MODE_CNTL
	.comm	_REG_A6XX_VFD_ADDR_MODE_CNTL,4,2 ; @REG_A6XX_VFD_ADDR_MODE_CNTL
	.comm	_REG_A6XX_VPC_ADDR_MODE_CNTL,4,2 ; @REG_A6XX_VPC_ADDR_MODE_CNTL
	.comm	_REG_A6XX_UCHE_ADDR_MODE_CNTL,4,2 ; @REG_A6XX_UCHE_ADDR_MODE_CNTL
	.comm	_REG_A6XX_SP_ADDR_MODE_CNTL,4,2 ; @REG_A6XX_SP_ADDR_MODE_CNTL
	.comm	_REG_A6XX_TPL1_ADDR_MODE_CNTL,4,2 ; @REG_A6XX_TPL1_ADDR_MODE_CNTL
	.comm	_REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL,4,2 ; @REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL
	.comm	_REG_A6XX_VBIF_GATE_OFF_WRREQ_EN,4,2 ; @REG_A6XX_VBIF_GATE_OFF_WRREQ_EN
	.comm	_REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL,4,2 ; @REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL
	.comm	_REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED,4,2 ; @REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED
	.comm	_REG_A6XX_UCHE_WRITE_RANGE_MAX_LO,4,2 ; @REG_A6XX_UCHE_WRITE_RANGE_MAX_LO
	.comm	_REG_A6XX_UCHE_WRITE_RANGE_MAX_HI,4,2 ; @REG_A6XX_UCHE_WRITE_RANGE_MAX_HI
	.comm	_REG_A6XX_UCHE_TRAP_BASE_LO,4,2 ; @REG_A6XX_UCHE_TRAP_BASE_LO
	.comm	_REG_A6XX_UCHE_TRAP_BASE_HI,4,2 ; @REG_A6XX_UCHE_TRAP_BASE_HI
	.comm	_REG_A6XX_UCHE_WRITE_THRU_BASE_LO,4,2 ; @REG_A6XX_UCHE_WRITE_THRU_BASE_LO
	.comm	_REG_A6XX_UCHE_WRITE_THRU_BASE_HI,4,2 ; @REG_A6XX_UCHE_WRITE_THRU_BASE_HI
	.comm	_REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,4,2 ; @REG_A6XX_UCHE_GMEM_RANGE_MIN_LO
	.comm	_REG_A6XX_UCHE_GMEM_RANGE_MIN_HI,4,2 ; @REG_A6XX_UCHE_GMEM_RANGE_MIN_HI
	.comm	_REG_A6XX_UCHE_GMEM_RANGE_MAX_LO,4,2 ; @REG_A6XX_UCHE_GMEM_RANGE_MAX_LO
	.comm	_REG_A6XX_UCHE_GMEM_RANGE_MAX_HI,4,2 ; @REG_A6XX_UCHE_GMEM_RANGE_MAX_HI
	.comm	_REG_A6XX_UCHE_FILTER_CNTL,4,2  ; @REG_A6XX_UCHE_FILTER_CNTL
	.comm	_REG_A6XX_UCHE_CACHE_WAYS,4,2   ; @REG_A6XX_UCHE_CACHE_WAYS
	.comm	_REG_A6XX_CP_ROQ_THRESHOLDS_2,4,2 ; @REG_A6XX_CP_ROQ_THRESHOLDS_2
	.comm	_REG_A6XX_CP_ROQ_THRESHOLDS_1,4,2 ; @REG_A6XX_CP_ROQ_THRESHOLDS_1
	.comm	_REG_A6XX_CP_MEM_POOL_SIZE,4,2  ; @REG_A6XX_CP_MEM_POOL_SIZE
	.comm	_REG_A6XX_PC_DBG_ECO_CNTL,4,2   ; @REG_A6XX_PC_DBG_ECO_CNTL
	.comm	_REG_A6XX_CP_AHB_CNTL,4,2       ; @REG_A6XX_CP_AHB_CNTL
	.comm	_REG_A6XX_RBBM_PERFCTR_CNTL,4,2 ; @REG_A6XX_RBBM_PERFCTR_CNTL
	.comm	_REG_A6XX_CP_PERFCTR_CP_SEL_0,4,2 ; @REG_A6XX_CP_PERFCTR_CP_SEL_0
	.comm	_PERF_CP_ALWAYS_COUNT,4,2       ; @PERF_CP_ALWAYS_COUNT
	.comm	_REG_A6XX_RB_NC_MODE_CNTL,4,2   ; @REG_A6XX_RB_NC_MODE_CNTL
	.comm	_REG_A6XX_TPL1_NC_MODE_CNTL,4,2 ; @REG_A6XX_TPL1_NC_MODE_CNTL
	.comm	_REG_A6XX_SP_NC_MODE_CNTL,4,2   ; @REG_A6XX_SP_NC_MODE_CNTL
	.comm	_REG_A6XX_UCHE_MODE_CNTL,4,2    ; @REG_A6XX_UCHE_MODE_CNTL
	.comm	_REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL,4,2 ; @REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL
	.comm	_REG_A6XX_UCHE_CLIENT_PF,4,2    ; @REG_A6XX_UCHE_CLIENT_PF
	.comm	_REG_A6XX_CP_PROTECT_CNTL,4,2   ; @REG_A6XX_CP_PROTECT_CNTL
	.comm	_REG_A6XX_RBBM_INT_0_MASK,4,2   ; @REG_A6XX_RBBM_INT_0_MASK
	.comm	_A6XX_INT_MASK,4,2              ; @A6XX_INT_MASK
	.comm	_REG_A6XX_CP_SQE_CNTL,4,2       ; @REG_A6XX_CP_SQE_CNTL
	.comm	_CP_SET_SECURE_MODE,4,2         ; @CP_SET_SECURE_MODE
	.comm	_EINVAL,4,2                     ; @EINVAL
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"

	.comm	_REG_A6XX_RBBM_SECVID_TRUST_CNTL,4,2 ; @REG_A6XX_RBBM_SECVID_TRUST_CNTL
	.comm	_GMU_OOB_BOOT_SLUMBER,4,2       ; @GMU_OOB_BOOT_SLUMBER
	.no_dead_strip	_a6xx_hw_init
.subsections_via_symbols
