	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v10_0_cp_gfx_start
_gfx_v10_0_cp_gfx_start:                ## @gfx_v10_0_cp_gfx_start
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_GC@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_mmCP_MAX_CONTEXT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	8(%r14), %ecx
	decl	%ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%rbx), %edi
	movq	_mmCP_DEVICE_ID@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	movl	$1, %ecx
	callq	_WREG32_SOC15
	movq	%r14, %rdi
	movl	$1, %esi
	callq	_gfx_v10_0_cp_gfx_enable
	movq	(%r14), %rbx
	movq	%r14, %rdi
	callq	_gfx_v10_0_get_csb_size
                                        ## kill: def $eax killed $eax def $rax
	leal	4(%rax), %esi
	movq	%rbx, %rdi
	callq	_amdgpu_ring_alloc
	testl	%eax, %eax
	je	LBB0_2
## %bb.1:
	movl	%eax, %r15d
	leaq	L_.str(%rip), %rdi
	movl	%eax, %esi
	callq	_DRM_ERROR
	jmp	LBB0_14
LBB0_2:
	movq	%r14, -48(%rbp)                 ## 8-byte Spill
	movq	_PACKET3_PREAMBLE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET3
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_PACKET3_PREAMBLE_BEGIN_CLEAR_STATE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_amdgpu_ring_write
	movq	_PACKET3_CONTEXT_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_PACKET3
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$-2147483648, %esi              ## imm = 0x80000000
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$-2147483648, %esi              ## imm = 0x80000000
	callq	_amdgpu_ring_write
	movq	_gfx10_cs_data@GOTPCREL(%rip), %rax
	movq	(%rax), %r15
	movq	8(%r15), %r13
	testq	%r13, %r13
	je	LBB0_11
## %bb.3:
	movq	_SECT_CONTEXT@GOTPCREL(%rip), %r12
	jmp	LBB0_4
	.p2align	4, 0x90
LBB0_10:                                ##   in Loop: Header=BB0_4 Depth=1
	movq	24(%r15), %r13
	addq	$16, %r15
	testq	%r13, %r13
	je	LBB0_11
LBB0_4:                                 ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_5 Depth 2
                                        ##       Child Loop BB0_8 Depth 3
	cmpq	$0, (%r13)
	jne	LBB0_5
	jmp	LBB0_10
	.p2align	4, 0x90
LBB0_9:                                 ##   in Loop: Header=BB0_5 Depth=2
	cmpq	$0, 16(%r13)
	leaq	16(%r13), %r13
	je	LBB0_10
LBB0_5:                                 ##   Parent Loop BB0_4 Depth=1
                                        ## =>  This Loop Header: Depth=2
                                        ##       Child Loop BB0_8 Depth 3
	movq	(%r15), %rax
	cmpq	(%r12), %rax
	jne	LBB0_9
## %bb.6:                               ##   in Loop: Header=BB0_5 Depth=2
	movq	_PACKET3_SET_CONTEXT_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	8(%r13), %esi
	callq	_PACKET3
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	12(%r13), %esi
	movq	_PACKET3_SET_CONTEXT_REG_START@GOTPCREL(%rip), %rax
	subl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_amdgpu_ring_write
	cmpl	$0, 8(%r13)
	jle	LBB0_9
## %bb.7:                               ##   in Loop: Header=BB0_5 Depth=2
	xorl	%r14d, %r14d
	.p2align	4, 0x90
LBB0_8:                                 ##   Parent Loop BB0_4 Depth=1
                                        ##     Parent Loop BB0_5 Depth=2
                                        ## =>    This Inner Loop Header: Depth=3
	movq	(%r13), %rax
	movl	(%rax,%r14,4), %esi
	movq	%rbx, %rdi
	callq	_amdgpu_ring_write
	incq	%r14
	movslq	8(%r13), %rax
	cmpq	%rax, %r14
	jl	LBB0_8
	jmp	LBB0_9
LBB0_11:
	movq	_GC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmPA_SC_TILE_STEERING_OVERRIDE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%r15d, %r15d
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %r12d
	movq	_PACKET3_SET_CONTEXT_REG_START@GOTPCREL(%rip), %rax
	subl	(%rax), %r12d
	movq	_PACKET3_SET_CONTEXT_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_PACKET3
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	%r12d, %esi
	callq	_amdgpu_ring_write
	movq	-48(%rbp), %r14                 ## 8-byte Reload
	movl	12(%r14), %esi
	movq	%rbx, %rdi
	callq	_amdgpu_ring_write
	movq	_PACKET3_PREAMBLE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET3
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_PACKET3_PREAMBLE_END_CLEAR_STATE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_amdgpu_ring_write
	movq	_PACKET3_CLEAR_STATE@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	xorl	%esi, %esi
	callq	_PACKET3
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
	movq	_PACKET3_SET_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$2, %esi
	callq	_PACKET3
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_CE_PARTITION_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_PACKET3_BASE_INDEX
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$32768, %esi                    ## imm = 0x8000
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$32768, %esi                    ## imm = 0x8000
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	callq	_amdgpu_ring_commit
	movq	(%r14), %rbx
	addq	$4, %rbx
	movq	%rbx, %rdi
	movl	$2, %esi
	callq	_amdgpu_ring_alloc
	testl	%eax, %eax
	je	LBB0_13
## %bb.12:
	movl	%eax, %r14d
	leaq	L_.str(%rip), %rdi
	movl	%eax, %esi
	callq	_DRM_ERROR
	movl	%r14d, %r15d
	jmp	LBB0_14
LBB0_13:
	movl	(%r12), %edi
	xorl	%esi, %esi
	callq	_PACKET3
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	callq	_amdgpu_ring_commit
LBB0_14:
	movl	%r15d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_GC,4,2                         ## @GC
	.comm	_mmCP_MAX_CONTEXT,4,2           ## @mmCP_MAX_CONTEXT
	.comm	_mmCP_DEVICE_ID,4,2             ## @mmCP_DEVICE_ID
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"amdgpu: cp failed to lock ring (%d).\n"

	.comm	_PACKET3_PREAMBLE_CNTL,4,2      ## @PACKET3_PREAMBLE_CNTL
	.comm	_PACKET3_PREAMBLE_BEGIN_CLEAR_STATE,4,2 ## @PACKET3_PREAMBLE_BEGIN_CLEAR_STATE
	.comm	_PACKET3_CONTEXT_CONTROL,4,2    ## @PACKET3_CONTEXT_CONTROL
	.comm	_gfx10_cs_data,8,3              ## @gfx10_cs_data
	.comm	_SECT_CONTEXT,8,3               ## @SECT_CONTEXT
	.comm	_PACKET3_SET_CONTEXT_REG,4,2    ## @PACKET3_SET_CONTEXT_REG
	.comm	_PACKET3_SET_CONTEXT_REG_START,4,2 ## @PACKET3_SET_CONTEXT_REG_START
	.comm	_mmPA_SC_TILE_STEERING_OVERRIDE,4,2 ## @mmPA_SC_TILE_STEERING_OVERRIDE
	.comm	_PACKET3_PREAMBLE_END_CLEAR_STATE,4,2 ## @PACKET3_PREAMBLE_END_CLEAR_STATE
	.comm	_PACKET3_CLEAR_STATE,4,2        ## @PACKET3_CLEAR_STATE
	.comm	_PACKET3_SET_BASE,4,2           ## @PACKET3_SET_BASE
	.comm	_CE_PARTITION_BASE,4,2          ## @CE_PARTITION_BASE
	.no_dead_strip	_gfx_v10_0_cp_gfx_start
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v10_0_cp_gfx_start
_gfx_v10_0_cp_gfx_start:                ; @gfx_v10_0_cp_gfx_start
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
Lloh0:
	adrp	x22, _GC@GOTPAGE
Lloh1:
	ldr	x22, [x22, _GC@GOTPAGEOFF]
	ldr	w0, [x22]
Lloh2:
	adrp	x8, _mmCP_MAX_CONTEXT@GOTPAGE
Lloh3:
	ldr	x8, [x8, _mmCP_MAX_CONTEXT@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	ldr	w8, [x19, #8]
	sub	w3, w8, #1
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh5:
	adrp	x8, _mmCP_DEVICE_ID@GOTPAGE
Lloh6:
	ldr	x8, [x8, _mmCP_DEVICE_ID@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #1
	bl	_WREG32_SOC15
	mov	x0, x19
	mov	w1, #1
	bl	_gfx_v10_0_cp_gfx_enable
	ldr	x20, [x19]
	mov	x0, x19
	bl	_gfx_v10_0_get_csb_size
	add	w1, w0, #4
	mov	x0, x20
	bl	_amdgpu_ring_alloc
	cbz	w0, LBB0_2
; %bb.1:
	mov	x21, x0
	b	LBB0_12
LBB0_2:
Lloh8:
	adrp	x23, _PACKET3_PREAMBLE_CNTL@GOTPAGE
Lloh9:
	ldr	x23, [x23, _PACKET3_PREAMBLE_CNTL@GOTPAGEOFF]
	ldr	w0, [x23]
	mov	w1, #0
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
Lloh10:
	adrp	x8, _PACKET3_PREAMBLE_BEGIN_CLEAR_STATE@GOTPAGE
Lloh11:
	ldr	x8, [x8, _PACKET3_PREAMBLE_BEGIN_CLEAR_STATE@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_amdgpu_ring_write
Lloh13:
	adrp	x8, _PACKET3_CONTEXT_CONTROL@GOTPAGE
Lloh14:
	ldr	x8, [x8, _PACKET3_CONTEXT_CONTROL@GOTPAGEOFF]
Lloh15:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
	mov	x0, x20
	mov	w1, #-2147483648
	bl	_amdgpu_ring_write
	mov	x0, x20
	mov	w1, #-2147483648
	bl	_amdgpu_ring_write
Lloh16:
	adrp	x8, _gfx10_cs_data@GOTPAGE
Lloh17:
	ldr	x8, [x8, _gfx10_cs_data@GOTPAGEOFF]
Lloh18:
	ldr	x25, [x8]
	ldr	x26, [x25, #8]
Lloh19:
	adrp	x21, _PACKET3_SET_CONTEXT_REG_START@GOTPAGE
Lloh20:
	ldr	x21, [x21, _PACKET3_SET_CONTEXT_REG_START@GOTPAGEOFF]
Lloh21:
	adrp	x24, _PACKET3_SET_CONTEXT_REG@GOTPAGE
Lloh22:
	ldr	x24, [x24, _PACKET3_SET_CONTEXT_REG@GOTPAGEOFF]
	cbz	x26, LBB0_11
; %bb.3:
Lloh23:
	adrp	x27, _SECT_CONTEXT@GOTPAGE
Lloh24:
	ldr	x27, [x27, _SECT_CONTEXT@GOTPAGEOFF]
	b	LBB0_5
LBB0_4:                                 ;   in Loop: Header=BB0_5 Depth=1
	ldr	x26, [x25, #24]
	add	x25, x25, #16
	cbz	x26, LBB0_11
LBB0_5:                                 ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
                                        ;       Child Loop BB0_10 Depth 3
	ldr	x8, [x26]
	cbnz	x8, LBB0_7
	b	LBB0_4
LBB0_6:                                 ;   in Loop: Header=BB0_7 Depth=2
	ldr	x8, [x26, #16]!
	cbz	x8, LBB0_4
LBB0_7:                                 ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_10 Depth 3
	ldr	x8, [x25]
	ldr	x9, [x27]
	cmp	x8, x9
	b.ne	LBB0_6
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=2
	ldr	w0, [x24]
	ldr	w1, [x26, #8]
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
	ldr	w8, [x26, #12]
	ldr	w9, [x21]
	sub	w1, w8, w9
	mov	x0, x20
	bl	_amdgpu_ring_write
	ldr	w8, [x26, #8]
	cmp	w8, #1
	b.lt	LBB0_6
; %bb.9:                                ;   in Loop: Header=BB0_7 Depth=2
	mov	x28, #0
LBB0_10:                                ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_7 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	ldr	x8, [x26]
	ldr	w1, [x8, x28, lsl #2]
	mov	x0, x20
	bl	_amdgpu_ring_write
	add	x28, x28, #1
	ldrsw	x8, [x26, #8]
	cmp	x28, x8
	b.lt	LBB0_10
	b	LBB0_6
LBB0_11:
	ldr	w0, [x22]
Lloh25:
	adrp	x8, _mmPA_SC_TILE_STEERING_OVERRIDE@GOTPAGE
Lloh26:
	ldr	x8, [x8, _mmPA_SC_TILE_STEERING_OVERRIDE@GOTPAGEOFF]
Lloh27:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x21]
	sub	w21, w0, w8
	ldr	w0, [x24]
	mov	w1, #1
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
	mov	x0, x20
	mov	x1, x21
	bl	_amdgpu_ring_write
	ldr	w1, [x19, #12]
	mov	x0, x20
	bl	_amdgpu_ring_write
	ldr	w0, [x23]
	mov	w1, #0
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
Lloh28:
	adrp	x8, _PACKET3_PREAMBLE_END_CLEAR_STATE@GOTPAGE
Lloh29:
	ldr	x8, [x8, _PACKET3_PREAMBLE_END_CLEAR_STATE@GOTPAGEOFF]
Lloh30:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_amdgpu_ring_write
Lloh31:
	adrp	x22, _PACKET3_CLEAR_STATE@GOTPAGE
Lloh32:
	ldr	x22, [x22, _PACKET3_CLEAR_STATE@GOTPAGEOFF]
	ldr	w0, [x22]
	mov	w1, #0
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
	mov	x0, x20
	mov	w1, #0
	bl	_amdgpu_ring_write
Lloh33:
	adrp	x8, _PACKET3_SET_BASE@GOTPAGE
Lloh34:
	ldr	x8, [x8, _PACKET3_SET_BASE@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	mov	w1, #2
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
Lloh36:
	adrp	x8, _CE_PARTITION_BASE@GOTPAGE
Lloh37:
	ldr	x8, [x8, _CE_PARTITION_BASE@GOTPAGEOFF]
Lloh38:
	ldr	w0, [x8]
	bl	_PACKET3_BASE_INDEX
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
	mov	x0, x20
	mov	w1, #32768
	bl	_amdgpu_ring_write
	mov	x0, x20
	mov	w1, #32768
	bl	_amdgpu_ring_write
	mov	x0, x20
	bl	_amdgpu_ring_commit
	ldr	x8, [x19]
	add	x19, x8, #4
	mov	x0, x19
	mov	w1, #2
	bl	_amdgpu_ring_alloc
	mov	x21, x0
	cbz	w0, LBB0_14
LBB0_12:
Lloh39:
	adrp	x0, l_.str@PAGE
Lloh40:
	add	x0, x0, l_.str@PAGEOFF
	mov	x1, x21
	bl	_DRM_ERROR
LBB0_13:
	mov	x0, x21
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
LBB0_14:
	ldr	w0, [x22]
	mov	w1, #0
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_ring_write
	mov	x0, x19
	bl	_amdgpu_ring_commit
	b	LBB0_13
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpAdd	Lloh39, Lloh40
	.cfi_endproc
                                        ; -- End function
	.comm	_GC,4,2                         ; @GC
	.comm	_mmCP_MAX_CONTEXT,4,2           ; @mmCP_MAX_CONTEXT
	.comm	_mmCP_DEVICE_ID,4,2             ; @mmCP_DEVICE_ID
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"amdgpu: cp failed to lock ring (%d).\n"

	.comm	_PACKET3_PREAMBLE_CNTL,4,2      ; @PACKET3_PREAMBLE_CNTL
	.comm	_PACKET3_PREAMBLE_BEGIN_CLEAR_STATE,4,2 ; @PACKET3_PREAMBLE_BEGIN_CLEAR_STATE
	.comm	_PACKET3_CONTEXT_CONTROL,4,2    ; @PACKET3_CONTEXT_CONTROL
	.comm	_gfx10_cs_data,8,3              ; @gfx10_cs_data
	.comm	_SECT_CONTEXT,8,3               ; @SECT_CONTEXT
	.comm	_PACKET3_SET_CONTEXT_REG,4,2    ; @PACKET3_SET_CONTEXT_REG
	.comm	_PACKET3_SET_CONTEXT_REG_START,4,2 ; @PACKET3_SET_CONTEXT_REG_START
	.comm	_mmPA_SC_TILE_STEERING_OVERRIDE,4,2 ; @mmPA_SC_TILE_STEERING_OVERRIDE
	.comm	_PACKET3_PREAMBLE_END_CLEAR_STATE,4,2 ; @PACKET3_PREAMBLE_END_CLEAR_STATE
	.comm	_PACKET3_CLEAR_STATE,4,2        ; @PACKET3_CLEAR_STATE
	.comm	_PACKET3_SET_BASE,4,2           ; @PACKET3_SET_BASE
	.comm	_CE_PARTITION_BASE,4,2          ; @CE_PARTITION_BASE
	.no_dead_strip	_gfx_v10_0_cp_gfx_start
.subsections_via_symbols
