	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mcde_dsi_start
_mcde_dsi_start:                        ## @mcde_dsi_start
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r13
	movq	_DSI_MCTL_INTEGRATION_MODE@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%rdi), %rsi
	xorl	%r14d, %r14d
	xorl	%edi, %edi
	callq	_writel
	movq	_DSI_MCTL_MAIN_DATA_CTL_LINK_EN@GOTPCREL(%rip), %rax
	movq	_DSI_MCTL_MAIN_DATA_CTL_BTA_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	orl	(%rax), %edi
	movq	_DSI_MCTL_MAIN_DATA_CTL_READ_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	_DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	16(%r13), %rcx
	movq	_MIPI_DSI_MODE_EOT_PACKET@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%rcx), %eax
	je	LBB0_2
## %bb.1:
	movq	_DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_2:
	orl	%eax, %edi
	movq	_DSI_MCTL_MAIN_DATA_CTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%r13), %rsi
	callq	_writel
	movq	_DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$1023, %edi                     ## imm = 0x3FF
	shll	%cl, %edi
	movq	_DSI_CMD_MODE_CTL@GOTPCREL(%rip), %r15
	movq	(%r15), %rsi
	addq	8(%r13), %rsi
	callq	_writel
	movl	24(%r13), %edi
	callq	_clk_get_rate
	movabsq	$4835703278458516699, %rcx      ## imm = 0x431BDE82D7B634DB
	mulq	%rcx
	movq	%rdx, %rcx
	shrq	$18, %rcx
	cmpq	$4000, %rcx                     ## imm = 0xFA0
	ja	LBB0_4
## %bb.3:
	movl	$4000, %eax                     ## imm = 0xFA0
	xorl	%edx, %edx
	divl	%ecx
	movl	%eax, %r14d
LBB0_4:
	movl	(%r13), %edi
	leaq	L_.str(%rip), %rsi
	movl	%r14d, %edx
	callq	_dev_dbg
	movq	_DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r14d
	movq	_DSI_MCTL_DPHY_STATIC_UI_X4_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %r14d
	movq	_DSI_MCTL_DPHY_STATIC@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%r13), %rsi
	movl	%r14d, %edi
	callq	_writel
	movq	_DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$15, %r12d
	movl	$15, %eax
	shll	%cl, %eax
	movq	16(%r13), %rcx
	xorl	%r14d, %r14d
	cmpl	$2, 4(%rcx)
	movl	$0, %edi
	jne	LBB0_6
## %bb.5:
	movq	_DSI_MCTL_MAIN_PHY_CTL_LANE2_EN@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edi
LBB0_6:
	movq	_MIPI_DSI_CLOCK_NON_CONTINUOUS@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	movl	$0, %edx
	andl	(%rcx), %esi
	jne	LBB0_8
## %bb.7:
	movq	_DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
LBB0_8:
	movq	_DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN@GOTPCREL(%rip), %rcx
	movq	_DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN@GOTPCREL(%rip), %rsi
	movq	_DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN@GOTPCREL(%rip), %rbx
	orl	%eax, %edi
	orl	(%rcx), %edi
	orl	%edx, %edi
	orl	(%rsi), %edi
	orl	(%rbx), %edi
	movq	_DSI_MCTL_MAIN_PHY_CTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%r13), %rsi
	callq	_writel
	movq	_DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	movq	_DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$1, %edi
	shll	%cl, %edi
	btsl	%eax, %edi
	movq	_DSI_MCTL_ULPOUT_TIME@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%r13), %rsi
	callq	_writel
	movq	_DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_DSI_DPHY_LANES_TRIM@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%r13), %rsi
	callq	_writel
	movq	_DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r12d
	movq	_DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$16383, %eax                    ## imm = 0x3FFF
	shll	%cl, %eax
	movl	$16383, %edi                    ## imm = 0x3FFF
	orl	%r12d, %eax
	movq	_DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edi
	orl	%eax, %edi
	movq	_DSI_MCTL_DPHY_TIMEOUT@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%r13), %rsi
	callq	_writel
	movq	_DSI_MCTL_MAIN_EN_PLL_START@GOTPCREL(%rip), %rax
	movq	_DSI_MCTL_MAIN_EN_CKLANE_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	orl	(%rax), %edi
	movq	_DSI_MCTL_MAIN_EN_DAT1_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	_DSI_MCTL_MAIN_EN_IF1_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	16(%r13), %rax
	cmpl	$2, 4(%rax)
	movl	$0, %eax
	jne	LBB0_10
## %bb.9:
	movq	_DSI_MCTL_MAIN_EN_DAT2_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_10:
	orl	%eax, %edi
	movq	_DSI_MCTL_MAIN_EN@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%r13), %rsi
	callq	_writel
	movq	_DSI_MCTL_MAIN_STS_PLL_LOCK@GOTPCREL(%rip), %rax
	movq	_DSI_MCTL_MAIN_STS_CLKLANE_READY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r12d
	orl	(%rax), %r12d
	movq	_DSI_MCTL_MAIN_STS_DAT1_READY@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
	movq	16(%r13), %rax
	cmpl	$2, 4(%rax)
	jne	LBB0_12
## %bb.11:
	movq	_DSI_MCTL_MAIN_STS_DAT2_READY@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
LBB0_12:
	orl	%r14d, %r12d
	movl	$101, %ebx
	movq	_DSI_MCTL_MAIN_STS@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_13:                                ## =>This Inner Loop Header: Depth=1
	movq	(%r14), %rdi
	addq	8(%r13), %rdi
	callq	_readl
	notl	%eax
	testl	%eax, %r12d
	je	LBB0_16
## %bb.14:                              ##   in Loop: Header=BB0_13 Depth=1
	movl	$1000, %edi                     ## imm = 0x3E8
	movl	$1500, %esi                     ## imm = 0x5DC
	callq	_usleep_range
	decl	%ebx
	jne	LBB0_13
## %bb.15:
	movl	(%r13), %edi
	leaq	L_.str.1(%rip), %rsi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_dev_warn                       ## TAILCALL
LBB0_16:
	movq	(%r15), %rdi
	addq	8(%r13), %rdi
	callq	_readl
	movq	_DSI_CMD_MODE_CTL_IF1_ID_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	notl	%edi
	andl	%eax, %edi
	movq	(%r15), %rsi
	addq	8(%r13), %rsi
	callq	_writel
	movl	$100, %edi
	movl	$200, %esi
	callq	_usleep_range
	movl	(%r13), %edi
	leaq	L_.str.2(%rip), %rsi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_dev_info                       ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_DSI_MCTL_INTEGRATION_MODE,8,3  ## @DSI_MCTL_INTEGRATION_MODE
	.comm	_DSI_MCTL_MAIN_DATA_CTL_LINK_EN,4,2 ## @DSI_MCTL_MAIN_DATA_CTL_LINK_EN
	.comm	_DSI_MCTL_MAIN_DATA_CTL_BTA_EN,4,2 ## @DSI_MCTL_MAIN_DATA_CTL_BTA_EN
	.comm	_DSI_MCTL_MAIN_DATA_CTL_READ_EN,4,2 ## @DSI_MCTL_MAIN_DATA_CTL_READ_EN
	.comm	_DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN,4,2 ## @DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN
	.comm	_MIPI_DSI_MODE_EOT_PACKET,4,2   ## @MIPI_DSI_MODE_EOT_PACKET
	.comm	_DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN,4,2 ## @DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN
	.comm	_DSI_MCTL_MAIN_DATA_CTL,8,3     ## @DSI_MCTL_MAIN_DATA_CTL
	.comm	_DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT,4,2 ## @DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT
	.comm	_DSI_CMD_MODE_CTL,8,3           ## @DSI_CMD_MODE_CTL
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"UI value: %d\n"

	.comm	_DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT,4,2 ## @DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT
	.comm	_DSI_MCTL_DPHY_STATIC_UI_X4_MASK,4,2 ## @DSI_MCTL_DPHY_STATIC_UI_X4_MASK
	.comm	_DSI_MCTL_DPHY_STATIC,8,3       ## @DSI_MCTL_DPHY_STATIC
	.comm	_DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT,4,2 ## @DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT
	.comm	_DSI_MCTL_MAIN_PHY_CTL_LANE2_EN,4,2 ## @DSI_MCTL_MAIN_PHY_CTL_LANE2_EN
	.comm	_MIPI_DSI_CLOCK_NON_CONTINUOUS,4,2 ## @MIPI_DSI_CLOCK_NON_CONTINUOUS
	.comm	_DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS,4,2 ## @DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS
	.comm	_DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN,4,2 ## @DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN
	.comm	_DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN,4,2 ## @DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN
	.comm	_DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN,4,2 ## @DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN
	.comm	_DSI_MCTL_MAIN_PHY_CTL,8,3      ## @DSI_MCTL_MAIN_PHY_CTL
	.comm	_DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT,4,2 ## @DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT
	.comm	_DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT,4,2 ## @DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT
	.comm	_DSI_MCTL_ULPOUT_TIME,8,3       ## @DSI_MCTL_ULPOUT_TIME
	.comm	_DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90,4,2 ## @DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90
	.comm	_DSI_DPHY_LANES_TRIM,8,3        ## @DSI_DPHY_LANES_TRIM
	.comm	_DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT,4,2 ## @DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT
	.comm	_DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT,4,2 ## @DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT
	.comm	_DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT,4,2 ## @DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT
	.comm	_DSI_MCTL_DPHY_TIMEOUT,8,3      ## @DSI_MCTL_DPHY_TIMEOUT
	.comm	_DSI_MCTL_MAIN_EN_PLL_START,4,2 ## @DSI_MCTL_MAIN_EN_PLL_START
	.comm	_DSI_MCTL_MAIN_EN_CKLANE_EN,4,2 ## @DSI_MCTL_MAIN_EN_CKLANE_EN
	.comm	_DSI_MCTL_MAIN_EN_DAT1_EN,4,2   ## @DSI_MCTL_MAIN_EN_DAT1_EN
	.comm	_DSI_MCTL_MAIN_EN_IF1_EN,4,2    ## @DSI_MCTL_MAIN_EN_IF1_EN
	.comm	_DSI_MCTL_MAIN_EN_DAT2_EN,4,2   ## @DSI_MCTL_MAIN_EN_DAT2_EN
	.comm	_DSI_MCTL_MAIN_EN,8,3           ## @DSI_MCTL_MAIN_EN
	.comm	_DSI_MCTL_MAIN_STS_PLL_LOCK,4,2 ## @DSI_MCTL_MAIN_STS_PLL_LOCK
	.comm	_DSI_MCTL_MAIN_STS_CLKLANE_READY,4,2 ## @DSI_MCTL_MAIN_STS_CLKLANE_READY
	.comm	_DSI_MCTL_MAIN_STS_DAT1_READY,4,2 ## @DSI_MCTL_MAIN_STS_DAT1_READY
	.comm	_DSI_MCTL_MAIN_STS_DAT2_READY,4,2 ## @DSI_MCTL_MAIN_STS_DAT2_READY
	.comm	_DSI_MCTL_MAIN_STS,8,3          ## @DSI_MCTL_MAIN_STS
L_.str.1:                               ## @.str.1
	.asciz	"DSI lanes did not start up\n"

	.comm	_DSI_CMD_MODE_CTL_IF1_ID_MASK,4,2 ## @DSI_CMD_MODE_CTL_IF1_ID_MASK
L_.str.2:                               ## @.str.2
	.asciz	"DSI link enabled\n"

	.no_dead_strip	_mcde_dsi_start
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mcde_dsi_start
_mcde_dsi_start:                        ; @mcde_dsi_start
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	x8, [x0, #8]
Lloh0:
	adrp	x9, _DSI_MCTL_INTEGRATION_MODE@GOTPAGE
Lloh1:
	ldr	x9, [x9, _DSI_MCTL_INTEGRATION_MODE@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #0
	bl	_writel
Lloh3:
	adrp	x8, _DSI_MCTL_MAIN_DATA_CTL_LINK_EN@GOTPAGE
Lloh4:
	ldr	x8, [x8, _DSI_MCTL_MAIN_DATA_CTL_LINK_EN@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
Lloh6:
	adrp	x9, _DSI_MCTL_MAIN_DATA_CTL_BTA_EN@GOTPAGE
Lloh7:
	ldr	x9, [x9, _DSI_MCTL_MAIN_DATA_CTL_BTA_EN@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh9:
	adrp	x9, _DSI_MCTL_MAIN_DATA_CTL_READ_EN@GOTPAGE
Lloh10:
	ldr	x9, [x9, _DSI_MCTL_MAIN_DATA_CTL_READ_EN@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh12:
	adrp	x9, _DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN@GOTPAGE
Lloh13:
	ldr	x9, [x9, _DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh15:
	adrp	x9, _MIPI_DSI_MODE_EOT_PACKET@GOTPAGE
Lloh16:
	ldr	x9, [x9, _MIPI_DSI_MODE_EOT_PACKET@GOTPAGEOFF]
	ldp	x11, x10, [x19, #8]
	ldr	w10, [x10]
Lloh17:
	ldr	w9, [x9]
	tst	w9, w10
Lloh18:
	adrp	x9, _DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN@GOTPAGE
Lloh19:
	ldr	x9, [x9, _DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	csel	w9, wzr, w9, eq
	orr	w0, w8, w9
Lloh21:
	adrp	x8, _DSI_MCTL_MAIN_DATA_CTL@GOTPAGE
Lloh22:
	ldr	x8, [x8, _DSI_MCTL_MAIN_DATA_CTL@GOTPAGEOFF]
Lloh23:
	ldr	x8, [x8]
	add	x1, x8, x11
	bl	_writel
Lloh24:
	adrp	x8, _DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT@GOTPAGE
Lloh25:
	ldr	x8, [x8, _DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	mov	w9, #1023
	lsl	w0, w9, w8
	ldr	x8, [x19, #8]
Lloh27:
	adrp	x21, _DSI_CMD_MODE_CTL@GOTPAGE
Lloh28:
	ldr	x21, [x21, _DSI_CMD_MODE_CTL@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x1, x9, x8
	bl	_writel
	ldr	w0, [x19, #24]
	bl	_clk_get_rate
	mov	x8, #13531
	movk	x8, #55222, lsl #16
	movk	x8, #56962, lsl #32
	movk	x8, #17179, lsl #48
	umulh	x8, x0, x8
	lsr	x8, x8, #18
	mov	w9, #4000
	ldr	w0, [x19]
	udiv	x20, x9, x8
Lloh29:
	adrp	x1, l_.str@PAGE
Lloh30:
	add	x1, x1, l_.str@PAGEOFF
	mov	x2, x20
	bl	_dev_dbg
Lloh31:
	adrp	x8, _DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT@GOTPAGE
Lloh32:
	ldr	x8, [x8, _DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
	lsl	w8, w20, w8
Lloh34:
	adrp	x9, _DSI_MCTL_DPHY_STATIC_UI_X4_MASK@GOTPAGE
Lloh35:
	ldr	x9, [x9, _DSI_MCTL_DPHY_STATIC_UI_X4_MASK@GOTPAGEOFF]
Lloh36:
	ldr	w9, [x9]
	and	w0, w8, w9
	ldr	x8, [x19, #8]
Lloh37:
	adrp	x9, _DSI_MCTL_DPHY_STATIC@GOTPAGE
Lloh38:
	ldr	x9, [x9, _DSI_MCTL_DPHY_STATIC@GOTPAGEOFF]
Lloh39:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
Lloh40:
	adrp	x8, _DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT@GOTPAGE
Lloh41:
	ldr	x8, [x8, _DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT@GOTPAGEOFF]
Lloh42:
	ldr	w8, [x8]
	mov	w20, #15
	lsl	w8, w20, w8
Lloh43:
	adrp	x9, _DSI_MCTL_MAIN_PHY_CTL_LANE2_EN@GOTPAGE
Lloh44:
	ldr	x9, [x9, _DSI_MCTL_MAIN_PHY_CTL_LANE2_EN@GOTPAGEOFF]
Lloh45:
	ldr	w9, [x9]
	ldp	x11, x10, [x19, #8]
	ldp	w10, w12, [x10]
	cmp	w12, #2
	csel	w9, w9, wzr, eq
Lloh46:
	adrp	x12, _MIPI_DSI_CLOCK_NON_CONTINUOUS@GOTPAGE
Lloh47:
	ldr	x12, [x12, _MIPI_DSI_CLOCK_NON_CONTINUOUS@GOTPAGEOFF]
Lloh48:
	ldr	w12, [x12]
Lloh49:
	adrp	x13, _DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS@GOTPAGE
Lloh50:
	ldr	x13, [x13, _DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS@GOTPAGEOFF]
Lloh51:
	ldr	w13, [x13]
	tst	w12, w10
	csel	w10, w13, wzr, eq
Lloh52:
	adrp	x12, _DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN@GOTPAGE
Lloh53:
	ldr	x12, [x12, _DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN@GOTPAGEOFF]
Lloh54:
	ldr	w12, [x12]
Lloh55:
	adrp	x13, _DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN@GOTPAGE
Lloh56:
	ldr	x13, [x13, _DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN@GOTPAGEOFF]
Lloh57:
	ldr	w13, [x13]
	orr	w8, w9, w8
Lloh58:
	adrp	x9, _DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN@GOTPAGE
Lloh59:
	ldr	x9, [x9, _DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN@GOTPAGEOFF]
Lloh60:
	ldr	w9, [x9]
	orr	w8, w8, w12
	orr	w8, w8, w10
	orr	w8, w8, w13
	orr	w0, w8, w9
Lloh61:
	adrp	x8, _DSI_MCTL_MAIN_PHY_CTL@GOTPAGE
Lloh62:
	ldr	x8, [x8, _DSI_MCTL_MAIN_PHY_CTL@GOTPAGEOFF]
Lloh63:
	ldr	x8, [x8]
	add	x1, x8, x11
	bl	_writel
Lloh64:
	adrp	x8, _DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT@GOTPAGE
Lloh65:
	ldr	x8, [x8, _DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT@GOTPAGEOFF]
Lloh66:
	ldr	w8, [x8]
	mov	w9, #1
	lsl	w8, w9, w8
Lloh67:
	adrp	x10, _DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT@GOTPAGE
Lloh68:
	ldr	x10, [x10, _DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT@GOTPAGEOFF]
Lloh69:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w0, w9, w8
	ldr	x8, [x19, #8]
Lloh70:
	adrp	x9, _DSI_MCTL_ULPOUT_TIME@GOTPAGE
Lloh71:
	ldr	x9, [x9, _DSI_MCTL_ULPOUT_TIME@GOTPAGEOFF]
Lloh72:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
Lloh73:
	adrp	x8, _DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90@GOTPAGE
Lloh74:
	ldr	x8, [x8, _DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90@GOTPAGEOFF]
Lloh75:
	ldr	w0, [x8]
	ldr	x8, [x19, #8]
Lloh76:
	adrp	x9, _DSI_DPHY_LANES_TRIM@GOTPAGE
Lloh77:
	ldr	x9, [x9, _DSI_DPHY_LANES_TRIM@GOTPAGEOFF]
Lloh78:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
Lloh79:
	adrp	x8, _DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT@GOTPAGE
Lloh80:
	ldr	x8, [x8, _DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT@GOTPAGEOFF]
Lloh81:
	ldr	w8, [x8]
	lsl	w8, w20, w8
Lloh82:
	adrp	x9, _DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT@GOTPAGE
Lloh83:
	ldr	x9, [x9, _DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT@GOTPAGEOFF]
Lloh84:
	ldr	w9, [x9]
	mov	w10, #16383
	lsl	w9, w10, w9
	orr	w8, w9, w8
Lloh85:
	adrp	x9, _DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT@GOTPAGE
Lloh86:
	ldr	x9, [x9, _DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT@GOTPAGEOFF]
Lloh87:
	ldr	w9, [x9]
	lsl	w9, w10, w9
	orr	w0, w8, w9
	ldr	x8, [x19, #8]
Lloh88:
	adrp	x9, _DSI_MCTL_DPHY_TIMEOUT@GOTPAGE
Lloh89:
	ldr	x9, [x9, _DSI_MCTL_DPHY_TIMEOUT@GOTPAGEOFF]
Lloh90:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
Lloh91:
	adrp	x8, _DSI_MCTL_MAIN_EN_PLL_START@GOTPAGE
Lloh92:
	ldr	x8, [x8, _DSI_MCTL_MAIN_EN_PLL_START@GOTPAGEOFF]
Lloh93:
	adrp	x9, _DSI_MCTL_MAIN_EN_CKLANE_EN@GOTPAGE
Lloh94:
	ldr	x9, [x9, _DSI_MCTL_MAIN_EN_CKLANE_EN@GOTPAGEOFF]
Lloh95:
	ldr	w8, [x8]
Lloh96:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh97:
	adrp	x9, _DSI_MCTL_MAIN_EN_DAT1_EN@GOTPAGE
Lloh98:
	ldr	x9, [x9, _DSI_MCTL_MAIN_EN_DAT1_EN@GOTPAGEOFF]
Lloh99:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh100:
	adrp	x9, _DSI_MCTL_MAIN_EN_IF1_EN@GOTPAGE
Lloh101:
	ldr	x9, [x9, _DSI_MCTL_MAIN_EN_IF1_EN@GOTPAGEOFF]
Lloh102:
	ldr	w9, [x9]
	orr	w8, w8, w9
	ldp	x10, x9, [x19, #8]
	ldr	w9, [x9, #4]
Lloh103:
	adrp	x11, _DSI_MCTL_MAIN_EN_DAT2_EN@GOTPAGE
Lloh104:
	ldr	x11, [x11, _DSI_MCTL_MAIN_EN_DAT2_EN@GOTPAGEOFF]
Lloh105:
	ldr	w11, [x11]
	cmp	w9, #2
	csel	w9, w11, wzr, eq
	orr	w0, w8, w9
Lloh106:
	adrp	x8, _DSI_MCTL_MAIN_EN@GOTPAGE
Lloh107:
	ldr	x8, [x8, _DSI_MCTL_MAIN_EN@GOTPAGEOFF]
Lloh108:
	ldr	x8, [x8]
	add	x1, x8, x10
	bl	_writel
Lloh109:
	adrp	x8, _DSI_MCTL_MAIN_STS_PLL_LOCK@GOTPAGE
Lloh110:
	ldr	x8, [x8, _DSI_MCTL_MAIN_STS_PLL_LOCK@GOTPAGEOFF]
Lloh111:
	adrp	x9, _DSI_MCTL_MAIN_STS_CLKLANE_READY@GOTPAGE
Lloh112:
	ldr	x9, [x9, _DSI_MCTL_MAIN_STS_CLKLANE_READY@GOTPAGEOFF]
Lloh113:
	ldr	w8, [x8]
Lloh114:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh115:
	adrp	x9, _DSI_MCTL_MAIN_STS_DAT1_READY@GOTPAGE
Lloh116:
	ldr	x9, [x9, _DSI_MCTL_MAIN_STS_DAT1_READY@GOTPAGEOFF]
Lloh117:
	ldr	w9, [x9]
	orr	w8, w8, w9
	ldr	x9, [x19, #16]
	ldr	w9, [x9, #4]
Lloh118:
	adrp	x10, _DSI_MCTL_MAIN_STS_DAT2_READY@GOTPAGE
Lloh119:
	ldr	x10, [x10, _DSI_MCTL_MAIN_STS_DAT2_READY@GOTPAGEOFF]
Lloh120:
	ldr	w10, [x10]
	cmp	w9, #2
	csel	w9, w10, wzr, eq
	orr	w20, w8, w9
	mov	w22, #101
Lloh121:
	adrp	x23, _DSI_MCTL_MAIN_STS@GOTPAGE
Lloh122:
	ldr	x23, [x23, _DSI_MCTL_MAIN_STS@GOTPAGEOFF]
LBB0_1:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #8]
	ldr	x9, [x23]
	add	x0, x9, x8
	bl	_readl
	bics	wzr, w20, w0
	b.eq	LBB0_4
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	mov	w0, #1000
	mov	w1, #1500
	bl	_usleep_range
	subs	w22, w22, #1
	b.ne	LBB0_1
; %bb.3:
	ldr	w0, [x19]
Lloh123:
	adrp	x1, l_.str.1@PAGE
Lloh124:
	add	x1, x1, l_.str.1@PAGEOFF
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_dev_warn
LBB0_4:
	ldr	x8, [x19, #8]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_readl
Lloh125:
	adrp	x8, _DSI_CMD_MODE_CTL_IF1_ID_MASK@GOTPAGE
Lloh126:
	ldr	x8, [x8, _DSI_CMD_MODE_CTL_IF1_ID_MASK@GOTPAGEOFF]
Lloh127:
	ldr	w8, [x8]
	bic	w0, w0, w8
	ldr	x8, [x19, #8]
	ldr	x9, [x21]
	add	x1, x9, x8
	bl	_writel
	mov	w0, #100
	mov	w1, #200
	bl	_usleep_range
	ldr	w0, [x19]
Lloh128:
	adrp	x1, l_.str.2@PAGE
Lloh129:
	add	x1, x1, l_.str.2@PAGEOFF
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_dev_info
	.loh AdrpLdrGot	Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh114
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh113
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh95
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpAdd	Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh123, Lloh124
	.loh AdrpAdd	Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.cfi_endproc
                                        ; -- End function
	.comm	_DSI_MCTL_INTEGRATION_MODE,8,3  ; @DSI_MCTL_INTEGRATION_MODE
	.comm	_DSI_MCTL_MAIN_DATA_CTL_LINK_EN,4,2 ; @DSI_MCTL_MAIN_DATA_CTL_LINK_EN
	.comm	_DSI_MCTL_MAIN_DATA_CTL_BTA_EN,4,2 ; @DSI_MCTL_MAIN_DATA_CTL_BTA_EN
	.comm	_DSI_MCTL_MAIN_DATA_CTL_READ_EN,4,2 ; @DSI_MCTL_MAIN_DATA_CTL_READ_EN
	.comm	_DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN,4,2 ; @DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN
	.comm	_MIPI_DSI_MODE_EOT_PACKET,4,2   ; @MIPI_DSI_MODE_EOT_PACKET
	.comm	_DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN,4,2 ; @DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN
	.comm	_DSI_MCTL_MAIN_DATA_CTL,8,3     ; @DSI_MCTL_MAIN_DATA_CTL
	.comm	_DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT,4,2 ; @DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT
	.comm	_DSI_CMD_MODE_CTL,8,3           ; @DSI_CMD_MODE_CTL
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"UI value: %d\n"

	.comm	_DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT,4,2 ; @DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT
	.comm	_DSI_MCTL_DPHY_STATIC_UI_X4_MASK,4,2 ; @DSI_MCTL_DPHY_STATIC_UI_X4_MASK
	.comm	_DSI_MCTL_DPHY_STATIC,8,3       ; @DSI_MCTL_DPHY_STATIC
	.comm	_DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT,4,2 ; @DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT
	.comm	_DSI_MCTL_MAIN_PHY_CTL_LANE2_EN,4,2 ; @DSI_MCTL_MAIN_PHY_CTL_LANE2_EN
	.comm	_MIPI_DSI_CLOCK_NON_CONTINUOUS,4,2 ; @MIPI_DSI_CLOCK_NON_CONTINUOUS
	.comm	_DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS,4,2 ; @DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS
	.comm	_DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN,4,2 ; @DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN
	.comm	_DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN,4,2 ; @DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN
	.comm	_DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN,4,2 ; @DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN
	.comm	_DSI_MCTL_MAIN_PHY_CTL,8,3      ; @DSI_MCTL_MAIN_PHY_CTL
	.comm	_DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT,4,2 ; @DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT
	.comm	_DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT,4,2 ; @DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT
	.comm	_DSI_MCTL_ULPOUT_TIME,8,3       ; @DSI_MCTL_ULPOUT_TIME
	.comm	_DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90,4,2 ; @DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90
	.comm	_DSI_DPHY_LANES_TRIM,8,3        ; @DSI_DPHY_LANES_TRIM
	.comm	_DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT,4,2 ; @DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT
	.comm	_DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT,4,2 ; @DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT
	.comm	_DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT,4,2 ; @DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT
	.comm	_DSI_MCTL_DPHY_TIMEOUT,8,3      ; @DSI_MCTL_DPHY_TIMEOUT
	.comm	_DSI_MCTL_MAIN_EN_PLL_START,4,2 ; @DSI_MCTL_MAIN_EN_PLL_START
	.comm	_DSI_MCTL_MAIN_EN_CKLANE_EN,4,2 ; @DSI_MCTL_MAIN_EN_CKLANE_EN
	.comm	_DSI_MCTL_MAIN_EN_DAT1_EN,4,2   ; @DSI_MCTL_MAIN_EN_DAT1_EN
	.comm	_DSI_MCTL_MAIN_EN_IF1_EN,4,2    ; @DSI_MCTL_MAIN_EN_IF1_EN
	.comm	_DSI_MCTL_MAIN_EN_DAT2_EN,4,2   ; @DSI_MCTL_MAIN_EN_DAT2_EN
	.comm	_DSI_MCTL_MAIN_EN,8,3           ; @DSI_MCTL_MAIN_EN
	.comm	_DSI_MCTL_MAIN_STS_PLL_LOCK,4,2 ; @DSI_MCTL_MAIN_STS_PLL_LOCK
	.comm	_DSI_MCTL_MAIN_STS_CLKLANE_READY,4,2 ; @DSI_MCTL_MAIN_STS_CLKLANE_READY
	.comm	_DSI_MCTL_MAIN_STS_DAT1_READY,4,2 ; @DSI_MCTL_MAIN_STS_DAT1_READY
	.comm	_DSI_MCTL_MAIN_STS_DAT2_READY,4,2 ; @DSI_MCTL_MAIN_STS_DAT2_READY
	.comm	_DSI_MCTL_MAIN_STS,8,3          ; @DSI_MCTL_MAIN_STS
l_.str.1:                               ; @.str.1
	.asciz	"DSI lanes did not start up\n"

	.comm	_DSI_CMD_MODE_CTL_IF1_ID_MASK,4,2 ; @DSI_CMD_MODE_CTL_IF1_ID_MASK
l_.str.2:                               ; @.str.2
	.asciz	"DSI link enabled\n"

	.no_dead_strip	_mcde_dsi_start
.subsections_via_symbols
