	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dce110_register_irq_handlers
_dce110_register_irq_handlers:          ## @dce110_register_irq_handlers
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	40(%rdi), %rax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	xorps	%xmm0, %xmm0
	movaps	%xmm0, -80(%rbp)
	movaps	%xmm0, -96(%rbp)
	movq	$0, -64(%rbp)
	movq	(%rdi), %rax
	movq	_CHIP_VEGA10@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_1
## %bb.2:
	movq	_AMDGPU_IRQ_CLIENTID_LEGACY@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_1:
	movq	_SOC15_IH_CLIENTID_DCE@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %r15d
	movq	_INTERRUPT_POLARITY_DEFAULT@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -72(%rbp)
	movq	%rax, -80(%rbp)
	movq	_VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	_VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r13d
	jg	LBB0_8
## %bb.4:
	leaq	56(%r12), %r14
	.p2align	4, 0x90
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r12, %rdi
	movl	%r15d, %esi
	movl	%r13d, %edx
	movq	%r14, %rcx
	callq	_amdgpu_irq_add_id
	testl	%eax, %eax
	jne	LBB0_6
## %bb.7:                               ##   in Loop: Header=BB0_5 Depth=1
	movq	_INTERRUPT_HIGH_IRQ_CONTEXT@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -88(%rbp)
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movl	%r13d, %esi
	xorl	%edx, %edx
	callq	_dc_interrupt_to_irq_source
	movq	%rax, -96(%rbp)
	movq	32(%r12), %rdx
	movq	%rax, %rsi
	movq	_DC_IRQ_SOURCE_VBLANK1@GOTPCREL(%rip), %rcx
	subq	(%rcx), %rsi
	shlq	$4, %rsi
	leaq	(%rdx,%rsi), %rcx
	movq	%r12, 8(%rdx,%rsi)
	movq	%rax, (%rdx,%rsi)
	movq	_dm_crtc_high_irq@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	leaq	-96(%rbp), %rsi
	callq	_amdgpu_dm_irq_register_interrupt
	leal	1(%r13), %eax
	movq	_VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %r13d
	movl	%eax, %r13d
	jl	LBB0_5
LBB0_8:
	movq	_VISLANDS30_IV_SRCID_D1_V_UPDATE_INT@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	_VISLANDS30_IV_SRCID_D6_V_UPDATE_INT@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r13d
	jg	LBB0_13
## %bb.9:
	leaq	52(%r12), %r14
	.p2align	4, 0x90
LBB0_10:                                ## =>This Inner Loop Header: Depth=1
	movq	%r12, %rdi
	movl	%r15d, %esi
	movl	%r13d, %edx
	movq	%r14, %rcx
	callq	_amdgpu_irq_add_id
	testl	%eax, %eax
	jne	LBB0_11
## %bb.12:                              ##   in Loop: Header=BB0_10 Depth=1
	movq	_INTERRUPT_HIGH_IRQ_CONTEXT@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -88(%rbp)
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movl	%r13d, %esi
	xorl	%edx, %edx
	callq	_dc_interrupt_to_irq_source
	movq	%rax, -96(%rbp)
	movq	24(%r12), %rdx
	movq	%rax, %rsi
	movq	_DC_IRQ_SOURCE_VUPDATE1@GOTPCREL(%rip), %rcx
	subq	(%rcx), %rsi
	shlq	$4, %rsi
	leaq	(%rdx,%rsi), %rcx
	movq	%r12, 8(%rdx,%rsi)
	movq	%rax, (%rdx,%rsi)
	movq	_dm_vupdate_high_irq@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	leaq	-96(%rbp), %rsi
	callq	_amdgpu_dm_irq_register_interrupt
	addl	$2, %r13d
	movq	_VISLANDS30_IV_SRCID_D6_V_UPDATE_INT@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r13d
	jle	LBB0_10
LBB0_13:
	movq	_VISLANDS30_IV_SRCID_D1_GRPH_PFLIP@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	_VISLANDS30_IV_SRCID_D6_GRPH_PFLIP@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r13d
	jg	LBB0_18
## %bb.14:
	leaq	48(%r12), %r14
	.p2align	4, 0x90
LBB0_15:                                ## =>This Inner Loop Header: Depth=1
	movq	%r12, %rdi
	movl	%r15d, %esi
	movl	%r13d, %edx
	movq	%r14, %rcx
	callq	_amdgpu_irq_add_id
	testl	%eax, %eax
	jne	LBB0_16
## %bb.17:                              ##   in Loop: Header=BB0_15 Depth=1
	movq	_INTERRUPT_HIGH_IRQ_CONTEXT@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -88(%rbp)
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movl	%r13d, %esi
	xorl	%edx, %edx
	callq	_dc_interrupt_to_irq_source
	movq	%rax, -96(%rbp)
	movq	16(%r12), %rdx
	movq	%rax, %rsi
	movq	_DC_IRQ_SOURCE_PFLIP_FIRST@GOTPCREL(%rip), %rcx
	subq	(%rcx), %rsi
	shlq	$4, %rsi
	leaq	(%rdx,%rsi), %rcx
	movq	%r12, 8(%rdx,%rsi)
	movq	%rax, (%rdx,%rsi)
	movq	_dm_pflip_high_irq@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	leaq	-96(%rbp), %rsi
	callq	_amdgpu_dm_irq_register_interrupt
	addl	$2, %r13d
	movq	_VISLANDS30_IV_SRCID_D6_GRPH_PFLIP@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r13d
	jle	LBB0_15
LBB0_18:
	movq	_VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	leaq	8(%r12), %rcx
	movq	%r12, %rdi
	movl	%r15d, %esi
	callq	_amdgpu_irq_add_id
	testl	%eax, %eax
	je	LBB0_20
## %bb.19:
	movl	%eax, %ebx
	leaq	L_.str.3(%rip), %rdi
	callq	_DRM_ERROR
	jmp	LBB0_21
LBB0_6:
	movl	%eax, %ebx
	leaq	L_.str(%rip), %rdi
	callq	_DRM_ERROR
	jmp	LBB0_21
LBB0_11:
	movl	%eax, %ebx
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_ERROR
	jmp	LBB0_21
LBB0_16:
	movl	%eax, %ebx
	leaq	L_.str.2(%rip), %rdi
	callq	_DRM_ERROR
	jmp	LBB0_21
LBB0_20:
	movq	%r12, %rdi
	callq	_register_hpd_handlers
	xorl	%ebx, %ebx
LBB0_21:
	movl	%ebx, %eax
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_IRQ_CLIENTID_LEGACY,4,2 ## @AMDGPU_IRQ_CLIENTID_LEGACY
	.comm	_CHIP_VEGA10,8,3                ## @CHIP_VEGA10
	.comm	_SOC15_IH_CLIENTID_DCE,4,2      ## @SOC15_IH_CLIENTID_DCE
	.comm	_INTERRUPT_POLARITY_DEFAULT,8,3 ## @INTERRUPT_POLARITY_DEFAULT
	.comm	_VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0,4,2 ## @VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0
	.comm	_VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0,4,2 ## @VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Failed to add crtc irq id!\n"

	.comm	_INTERRUPT_HIGH_IRQ_CONTEXT,8,3 ## @INTERRUPT_HIGH_IRQ_CONTEXT
	.comm	_DC_IRQ_SOURCE_VBLANK1,8,3      ## @DC_IRQ_SOURCE_VBLANK1
	.comm	_dm_crtc_high_irq,4,2           ## @dm_crtc_high_irq
	.comm	_VISLANDS30_IV_SRCID_D1_V_UPDATE_INT,4,2 ## @VISLANDS30_IV_SRCID_D1_V_UPDATE_INT
	.comm	_VISLANDS30_IV_SRCID_D6_V_UPDATE_INT,4,2 ## @VISLANDS30_IV_SRCID_D6_V_UPDATE_INT
L_.str.1:                               ## @.str.1
	.asciz	"Failed to add vupdate irq id!\n"

	.comm	_DC_IRQ_SOURCE_VUPDATE1,8,3     ## @DC_IRQ_SOURCE_VUPDATE1
	.comm	_dm_vupdate_high_irq,4,2        ## @dm_vupdate_high_irq
	.comm	_VISLANDS30_IV_SRCID_D1_GRPH_PFLIP,4,2 ## @VISLANDS30_IV_SRCID_D1_GRPH_PFLIP
	.comm	_VISLANDS30_IV_SRCID_D6_GRPH_PFLIP,4,2 ## @VISLANDS30_IV_SRCID_D6_GRPH_PFLIP
L_.str.2:                               ## @.str.2
	.asciz	"Failed to add page flip irq id!\n"

	.comm	_DC_IRQ_SOURCE_PFLIP_FIRST,8,3  ## @DC_IRQ_SOURCE_PFLIP_FIRST
	.comm	_dm_pflip_high_irq,4,2          ## @dm_pflip_high_irq
	.comm	_VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A,4,2 ## @VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A
L_.str.3:                               ## @.str.3
	.asciz	"Failed to add hpd irq id!\n"

	.no_dead_strip	_dce110_register_irq_handlers
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dce110_register_irq_handlers
_dce110_register_irq_handlers:          ; @dce110_register_irq_handlers
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #144
	.cfi_def_cfa_offset 144
	stp	x28, x27, [sp, #48]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #64]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #80]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #96]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #112]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #128]            ; 16-byte Folded Spill
	add	x29, sp, #128
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	x20, [x0, #40]
	str	xzr, [sp, #32]
	movi.2d	v0, #0000000000000000
	stp	q0, q0, [sp]
	ldr	x8, [x0]
Lloh0:
	adrp	x9, _CHIP_VEGA10@GOTPAGE
Lloh1:
	ldr	x9, [x9, _CHIP_VEGA10@GOTPAGEOFF]
Lloh2:
	adrp	x10, _AMDGPU_IRQ_CLIENTID_LEGACY@GOTPAGE
Lloh3:
	ldr	x10, [x10, _AMDGPU_IRQ_CLIENTID_LEGACY@GOTPAGEOFF]
Lloh4:
	ldr	x9, [x9]
Lloh5:
	adrp	x11, _SOC15_IH_CLIENTID_DCE@GOTPAGE
Lloh6:
	ldr	x11, [x11, _SOC15_IH_CLIENTID_DCE@GOTPAGEOFF]
	cmp	x8, x9
	csel	x8, x10, x11, lt
	ldr	w21, [x8]
Lloh7:
	adrp	x8, _INTERRUPT_POLARITY_DEFAULT@GOTPAGE
Lloh8:
	ldr	x8, [x8, _INTERRUPT_POLARITY_DEFAULT@GOTPAGEOFF]
Lloh9:
	ldr	x8, [x8]
Lloh10:
	adrp	x9, _VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0@GOTPAGE
Lloh11:
	ldr	x9, [x9, _VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0@GOTPAGEOFF]
	stp	x8, x8, [sp, #16]
Lloh12:
	ldr	w22, [x9]
Lloh13:
	adrp	x25, _VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0@GOTPAGE
Lloh14:
	ldr	x25, [x25, _VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0@GOTPAGEOFF]
	ldr	w8, [x25]
	cmp	w22, w8
	b.gt	LBB0_4
; %bb.1:
	add	x23, x19, #56
Lloh15:
	adrp	x26, _INTERRUPT_HIGH_IRQ_CONTEXT@GOTPAGE
Lloh16:
	ldr	x26, [x26, _INTERRUPT_HIGH_IRQ_CONTEXT@GOTPAGEOFF]
Lloh17:
	adrp	x27, _DC_IRQ_SOURCE_VBLANK1@GOTPAGE
Lloh18:
	ldr	x27, [x27, _DC_IRQ_SOURCE_VBLANK1@GOTPAGEOFF]
Lloh19:
	adrp	x28, _dm_crtc_high_irq@GOTPAGE
Lloh20:
	ldr	x28, [x28, _dm_crtc_high_irq@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x19
	mov	x1, x21
	mov	x2, x22
	mov	x3, x23
	bl	_amdgpu_irq_add_id
	cbnz	w0, LBB0_14
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	ldr	x8, [x26]
	str	x8, [sp, #8]
	mov	x0, x20
	mov	x1, x22
	mov	w2, #0
	bl	_dc_interrupt_to_irq_source
	str	x0, [sp]
	ldr	x8, [x19, #32]
	ldr	x9, [x27]
	sub	x9, x0, x9
	add	x3, x8, x9, lsl #4
	stp	x0, x19, [x3]
	ldr	w2, [x28]
	mov	x1, sp
	mov	x0, x19
	bl	_amdgpu_dm_irq_register_interrupt
	add	w8, w22, #1
	ldr	w9, [x25]
	cmp	w22, w9
	mov	x22, x8
	b.lt	LBB0_2
LBB0_4:
Lloh21:
	adrp	x8, _VISLANDS30_IV_SRCID_D1_V_UPDATE_INT@GOTPAGE
Lloh22:
	ldr	x8, [x8, _VISLANDS30_IV_SRCID_D1_V_UPDATE_INT@GOTPAGEOFF]
Lloh23:
	ldr	w22, [x8]
Lloh24:
	adrp	x25, _VISLANDS30_IV_SRCID_D6_V_UPDATE_INT@GOTPAGE
Lloh25:
	ldr	x25, [x25, _VISLANDS30_IV_SRCID_D6_V_UPDATE_INT@GOTPAGEOFF]
	ldr	w8, [x25]
	cmp	w22, w8
	b.gt	LBB0_8
; %bb.5:
	add	x23, x19, #52
Lloh26:
	adrp	x26, _INTERRUPT_HIGH_IRQ_CONTEXT@GOTPAGE
Lloh27:
	ldr	x26, [x26, _INTERRUPT_HIGH_IRQ_CONTEXT@GOTPAGEOFF]
Lloh28:
	adrp	x27, _DC_IRQ_SOURCE_VUPDATE1@GOTPAGE
Lloh29:
	ldr	x27, [x27, _DC_IRQ_SOURCE_VUPDATE1@GOTPAGEOFF]
Lloh30:
	adrp	x28, _dm_vupdate_high_irq@GOTPAGE
Lloh31:
	ldr	x28, [x28, _dm_vupdate_high_irq@GOTPAGEOFF]
LBB0_6:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x19
	mov	x1, x21
	mov	x2, x22
	mov	x3, x23
	bl	_amdgpu_irq_add_id
	cbnz	w0, LBB0_15
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=1
	ldr	x8, [x26]
	str	x8, [sp, #8]
	mov	x0, x20
	mov	x1, x22
	mov	w2, #0
	bl	_dc_interrupt_to_irq_source
	str	x0, [sp]
	ldr	x8, [x19, #24]
	ldr	x9, [x27]
	sub	x9, x0, x9
	add	x3, x8, x9, lsl #4
	stp	x0, x19, [x3]
	ldr	w2, [x28]
	mov	x1, sp
	mov	x0, x19
	bl	_amdgpu_dm_irq_register_interrupt
	add	w22, w22, #2
	ldr	w8, [x25]
	cmp	w22, w8
	b.le	LBB0_6
LBB0_8:
Lloh32:
	adrp	x8, _VISLANDS30_IV_SRCID_D1_GRPH_PFLIP@GOTPAGE
Lloh33:
	ldr	x8, [x8, _VISLANDS30_IV_SRCID_D1_GRPH_PFLIP@GOTPAGEOFF]
Lloh34:
	ldr	w22, [x8]
Lloh35:
	adrp	x25, _VISLANDS30_IV_SRCID_D6_GRPH_PFLIP@GOTPAGE
Lloh36:
	ldr	x25, [x25, _VISLANDS30_IV_SRCID_D6_GRPH_PFLIP@GOTPAGEOFF]
	ldr	w8, [x25]
	cmp	w22, w8
	b.gt	LBB0_12
; %bb.9:
	add	x23, x19, #48
Lloh37:
	adrp	x26, _INTERRUPT_HIGH_IRQ_CONTEXT@GOTPAGE
Lloh38:
	ldr	x26, [x26, _INTERRUPT_HIGH_IRQ_CONTEXT@GOTPAGEOFF]
Lloh39:
	adrp	x27, _DC_IRQ_SOURCE_PFLIP_FIRST@GOTPAGE
Lloh40:
	ldr	x27, [x27, _DC_IRQ_SOURCE_PFLIP_FIRST@GOTPAGEOFF]
Lloh41:
	adrp	x28, _dm_pflip_high_irq@GOTPAGE
Lloh42:
	ldr	x28, [x28, _dm_pflip_high_irq@GOTPAGEOFF]
LBB0_10:                                ; =>This Inner Loop Header: Depth=1
	mov	x0, x19
	mov	x1, x21
	mov	x2, x22
	mov	x3, x23
	bl	_amdgpu_irq_add_id
	cbnz	w0, LBB0_16
; %bb.11:                               ;   in Loop: Header=BB0_10 Depth=1
	ldr	x8, [x26]
	str	x8, [sp, #8]
	mov	x0, x20
	mov	x1, x22
	mov	w2, #0
	bl	_dc_interrupt_to_irq_source
	str	x0, [sp]
	ldr	x8, [x19, #16]
	ldr	x9, [x27]
	sub	x9, x0, x9
	add	x3, x8, x9, lsl #4
	stp	x0, x19, [x3]
	ldr	w2, [x28]
	mov	x1, sp
	mov	x0, x19
	bl	_amdgpu_dm_irq_register_interrupt
	add	w22, w22, #2
	ldr	w8, [x25]
	cmp	w22, w8
	b.le	LBB0_10
LBB0_12:
Lloh43:
	adrp	x8, _VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A@GOTPAGE
Lloh44:
	ldr	x8, [x8, _VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A@GOTPAGEOFF]
Lloh45:
	ldr	w2, [x8]
	add	x3, x19, #8
	mov	x0, x19
	mov	x1, x21
	bl	_amdgpu_irq_add_id
	mov	x24, x0
	cbz	w0, LBB0_17
; %bb.13:
Lloh46:
	adrp	x0, l_.str.3@PAGE
Lloh47:
	add	x0, x0, l_.str.3@PAGEOFF
	bl	_DRM_ERROR
	b	LBB0_18
LBB0_14:
	mov	x24, x0
Lloh48:
	adrp	x0, l_.str@PAGE
Lloh49:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_ERROR
	b	LBB0_18
LBB0_15:
	mov	x24, x0
Lloh50:
	adrp	x0, l_.str.1@PAGE
Lloh51:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_ERROR
	b	LBB0_18
LBB0_16:
	mov	x24, x0
Lloh52:
	adrp	x0, l_.str.2@PAGE
Lloh53:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	_DRM_ERROR
	b	LBB0_18
LBB0_17:
	mov	x0, x19
	bl	_register_hpd_handlers
LBB0_18:
	mov	x0, x24
	ldp	x29, x30, [sp, #128]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #112]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #96]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #80]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #64]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #144
	ret
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh4
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpAdd	Lloh46, Lloh47
	.loh AdrpAdd	Lloh48, Lloh49
	.loh AdrpAdd	Lloh50, Lloh51
	.loh AdrpAdd	Lloh52, Lloh53
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_IRQ_CLIENTID_LEGACY,4,2 ; @AMDGPU_IRQ_CLIENTID_LEGACY
	.comm	_CHIP_VEGA10,8,3                ; @CHIP_VEGA10
	.comm	_SOC15_IH_CLIENTID_DCE,4,2      ; @SOC15_IH_CLIENTID_DCE
	.comm	_INTERRUPT_POLARITY_DEFAULT,8,3 ; @INTERRUPT_POLARITY_DEFAULT
	.comm	_VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0,4,2 ; @VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0
	.comm	_VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0,4,2 ; @VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Failed to add crtc irq id!\n"

	.comm	_INTERRUPT_HIGH_IRQ_CONTEXT,8,3 ; @INTERRUPT_HIGH_IRQ_CONTEXT
	.comm	_DC_IRQ_SOURCE_VBLANK1,8,3      ; @DC_IRQ_SOURCE_VBLANK1
	.comm	_dm_crtc_high_irq,4,2           ; @dm_crtc_high_irq
	.comm	_VISLANDS30_IV_SRCID_D1_V_UPDATE_INT,4,2 ; @VISLANDS30_IV_SRCID_D1_V_UPDATE_INT
	.comm	_VISLANDS30_IV_SRCID_D6_V_UPDATE_INT,4,2 ; @VISLANDS30_IV_SRCID_D6_V_UPDATE_INT
l_.str.1:                               ; @.str.1
	.asciz	"Failed to add vupdate irq id!\n"

	.comm	_DC_IRQ_SOURCE_VUPDATE1,8,3     ; @DC_IRQ_SOURCE_VUPDATE1
	.comm	_dm_vupdate_high_irq,4,2        ; @dm_vupdate_high_irq
	.comm	_VISLANDS30_IV_SRCID_D1_GRPH_PFLIP,4,2 ; @VISLANDS30_IV_SRCID_D1_GRPH_PFLIP
	.comm	_VISLANDS30_IV_SRCID_D6_GRPH_PFLIP,4,2 ; @VISLANDS30_IV_SRCID_D6_GRPH_PFLIP
l_.str.2:                               ; @.str.2
	.asciz	"Failed to add page flip irq id!\n"

	.comm	_DC_IRQ_SOURCE_PFLIP_FIRST,8,3  ; @DC_IRQ_SOURCE_PFLIP_FIRST
	.comm	_dm_pflip_high_irq,4,2          ; @dm_pflip_high_irq
	.comm	_VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A,4,2 ; @VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A
l_.str.3:                               ; @.str.3
	.asciz	"Failed to add hpd irq id!\n"

	.no_dead_strip	_dce110_register_irq_handlers
.subsections_via_symbols
