	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vce_v4_0_mc_resume
_vce_v4_0_mc_resume:                    ## @vce_v4_0_mc_resume
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_VCE@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	movq	_mmVCE_CLOCK_GATING_A@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	movl	$-65537, %edx                   ## imm = 0xFFFEFFFF
	callq	_WREG32_P
	movl	(%r12), %edi
	movq	_mmVCE_UENC_CLOCK_GATING@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	$2093056, %esi                  ## imm = 0x1FF000
	movl	$6295551, %edx                  ## imm = 0x600FFF
	callq	_WREG32_P
	movl	(%r12), %edi
	movq	_mmVCE_UENC_REG_CLOCK_GATING@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	$63, %esi
	movl	$-64, %edx
	callq	_WREG32_P
	movl	(%r12), %edi
	movq	_mmVCE_CLOCK_GATING_B@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	$511, %esi                      ## imm = 0x1FF
	callq	_WREG32
	movl	(%r12), %edi
	movq	_mmVCE_LMI_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	$3768320, %esi                  ## imm = 0x398000
	callq	_WREG32
	movl	(%r12), %edi
	movq	_mmVCE_LMI_CACHE_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	movl	$-2, %edx
	callq	_WREG32_P
	movl	(%r12), %edi
	movq	_mmVCE_LMI_SWAP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r12), %edi
	movq	_mmVCE_LMI_SWAP_CNTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r12), %edi
	movq	_mmVCE_LMI_VM_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_AMDGPU_VCE_FIRMWARE_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	8(%r14), %r15
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rax
	movq	(%rax), %rbx
	movl	(%r12), %edi
	movq	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	cmpq	%rbx, %r15
	jne	LBB0_2
## %bb.1:
	movl	%eax, %edi
	callq	_WREG32
	movl	(%r12), %edi
	movq	_mmVCE_LMI_VCPU_CACHE_64BIT_BAR0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	callq	_WREG32
	movl	(%r12), %edi
	movq	_mmVCE_VCPU_CACHE_OFFSET0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	jmp	LBB0_3
LBB0_2:
	movl	(%r14), %esi
	sarl	$8, %esi
	movl	%eax, %edi
	callq	_WREG32
	movl	(%r12), %edi
	movq	_mmVCE_LMI_VCPU_CACHE_64BIT_BAR0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	callq	_WREG32
	movl	(%r12), %edi
	movq	_mmVCE_VCPU_CACHE_OFFSET0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%r13d, %esi
	andl	$-251658241, %esi               ## imm = 0xF0FFFFFF
	movl	%eax, %edi
LBB0_3:
	callq	_WREG32
	movq	_VCE_V4_0_FW_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	(%r12), %edi
	movq	_mmVCE_VCPU_CACHE_SIZE0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ebx, %ebx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	%r15d, %esi
	callq	_WREG32
	movl	(%r12), %edi
	movq	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r14), %esi
	sarl	$8, %esi
	movl	%eax, %edi
	callq	_WREG32
	movl	(%r12), %edi
	movq	_mmVCE_LMI_VCPU_CACHE_64BIT_BAR1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	callq	_WREG32
	movq	8(%r14), %rax
	addl	%r15d, %r13d
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	cmovel	%ebx, %r13d
	movq	_VCE_V4_0_STACK_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	(%r12), %edi
	movq	_mmVCE_VCPU_CACHE_OFFSET1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%r13d, %esi
	andl	$-251658241, %esi               ## imm = 0xF0FFFFFF
	orl	$16777216, %esi                 ## imm = 0x1000000
	movl	%eax, %edi
	callq	_WREG32
	movl	(%r12), %edi
	movq	_mmVCE_VCPU_CACHE_SIZE1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	%r15d, %esi
	callq	_WREG32
	movl	(%r12), %edi
	movq	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r14), %esi
	sarl	$8, %esi
	movl	%eax, %edi
	callq	_WREG32
	movl	(%r12), %edi
	movq	_mmVCE_LMI_VCPU_CACHE_64BIT_BAR2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	callq	_WREG32
	addl	%r15d, %r13d
	movq	_VCE_V4_0_DATA_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	(%r12), %edi
	movq	_mmVCE_VCPU_CACHE_OFFSET2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	andl	$-251658241, %r13d              ## imm = 0xF0FFFFFF
	orl	$33554432, %r13d                ## imm = 0x2000000
	movl	%eax, %edi
	movl	%r13d, %esi
	callq	_WREG32
	movl	(%r12), %edi
	movq	_mmVCE_VCPU_CACHE_SIZE2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	%r14d, %esi
	callq	_WREG32
	movl	(%r12), %edi
	movq	_mmVCE_LMI_CTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	movl	$-257, %edx                     ## imm = 0xFEFF
	callq	_WREG32_P
	movl	(%r12), %edi
	movq	_mmVCE_SYS_INT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_P                       ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_VCE,4,2                        ## @VCE
	.comm	_mmVCE_CLOCK_GATING_A,4,2       ## @mmVCE_CLOCK_GATING_A
	.comm	_mmVCE_UENC_CLOCK_GATING,4,2    ## @mmVCE_UENC_CLOCK_GATING
	.comm	_mmVCE_UENC_REG_CLOCK_GATING,4,2 ## @mmVCE_UENC_REG_CLOCK_GATING
	.comm	_mmVCE_CLOCK_GATING_B,4,2       ## @mmVCE_CLOCK_GATING_B
	.comm	_mmVCE_LMI_CTRL,4,2             ## @mmVCE_LMI_CTRL
	.comm	_mmVCE_LMI_CACHE_CTRL,4,2       ## @mmVCE_LMI_CACHE_CTRL
	.comm	_mmVCE_LMI_SWAP_CNTL,4,2        ## @mmVCE_LMI_SWAP_CNTL
	.comm	_mmVCE_LMI_SWAP_CNTL1,4,2       ## @mmVCE_LMI_SWAP_CNTL1
	.comm	_mmVCE_LMI_VM_CTRL,4,2          ## @mmVCE_LMI_VM_CTRL
	.comm	_AMDGPU_VCE_FIRMWARE_OFFSET,4,2 ## @AMDGPU_VCE_FIRMWARE_OFFSET
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_VCE,8,3        ## @AMDGPU_UCODE_ID_VCE
	.comm	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR0,4,2 ## @mmVCE_LMI_VCPU_CACHE_40BIT_BAR0
	.comm	_mmVCE_LMI_VCPU_CACHE_64BIT_BAR0,4,2 ## @mmVCE_LMI_VCPU_CACHE_64BIT_BAR0
	.comm	_mmVCE_VCPU_CACHE_OFFSET0,4,2   ## @mmVCE_VCPU_CACHE_OFFSET0
	.comm	_VCE_V4_0_FW_SIZE,4,2           ## @VCE_V4_0_FW_SIZE
	.comm	_mmVCE_VCPU_CACHE_SIZE0,4,2     ## @mmVCE_VCPU_CACHE_SIZE0
	.comm	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR1,4,2 ## @mmVCE_LMI_VCPU_CACHE_40BIT_BAR1
	.comm	_mmVCE_LMI_VCPU_CACHE_64BIT_BAR1,4,2 ## @mmVCE_LMI_VCPU_CACHE_64BIT_BAR1
	.comm	_VCE_V4_0_STACK_SIZE,4,2        ## @VCE_V4_0_STACK_SIZE
	.comm	_mmVCE_VCPU_CACHE_OFFSET1,4,2   ## @mmVCE_VCPU_CACHE_OFFSET1
	.comm	_mmVCE_VCPU_CACHE_SIZE1,4,2     ## @mmVCE_VCPU_CACHE_SIZE1
	.comm	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR2,4,2 ## @mmVCE_LMI_VCPU_CACHE_40BIT_BAR2
	.comm	_mmVCE_LMI_VCPU_CACHE_64BIT_BAR2,4,2 ## @mmVCE_LMI_VCPU_CACHE_64BIT_BAR2
	.comm	_VCE_V4_0_DATA_SIZE,4,2         ## @VCE_V4_0_DATA_SIZE
	.comm	_mmVCE_VCPU_CACHE_OFFSET2,4,2   ## @mmVCE_VCPU_CACHE_OFFSET2
	.comm	_mmVCE_VCPU_CACHE_SIZE2,4,2     ## @mmVCE_VCPU_CACHE_SIZE2
	.comm	_mmVCE_LMI_CTRL2,4,2            ## @mmVCE_LMI_CTRL2
	.comm	_mmVCE_SYS_INT_EN,4,2           ## @mmVCE_SYS_INT_EN
	.comm	_VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK,4,2 ## @VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK
	.no_dead_strip	_vce_v4_0_mc_resume
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vce_v4_0_mc_resume
_vce_v4_0_mc_resume:                    ; @vce_v4_0_mc_resume
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x21, _VCE@GOTPAGE
Lloh1:
	ldr	x21, [x21, _VCE@GOTPAGEOFF]
	ldr	w0, [x21]
Lloh2:
	adrp	x8, _mmVCE_CLOCK_GATING_A@GOTPAGE
Lloh3:
	ldr	x8, [x8, _mmVCE_CLOCK_GATING_A@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	mov	w2, #-65537
	bl	_WREG32_P
	ldr	w0, [x21]
Lloh5:
	adrp	x8, _mmVCE_UENC_CLOCK_GATING@GOTPAGE
Lloh6:
	ldr	x8, [x8, _mmVCE_UENC_CLOCK_GATING@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #2093056
	mov	w2, #4095
	movk	w2, #96, lsl #16
	bl	_WREG32_P
	ldr	w0, [x21]
Lloh8:
	adrp	x8, _mmVCE_UENC_REG_CLOCK_GATING@GOTPAGE
Lloh9:
	ldr	x8, [x8, _mmVCE_UENC_REG_CLOCK_GATING@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #63
	mov	w2, #-64
	bl	_WREG32_P
	ldr	w0, [x21]
Lloh11:
	adrp	x8, _mmVCE_CLOCK_GATING_B@GOTPAGE
Lloh12:
	ldr	x8, [x8, _mmVCE_CLOCK_GATING_B@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #511
	bl	_WREG32
	ldr	w0, [x21]
Lloh14:
	adrp	x8, _mmVCE_LMI_CTRL@GOTPAGE
Lloh15:
	ldr	x8, [x8, _mmVCE_LMI_CTRL@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #32768
	movk	w1, #57, lsl #16
	bl	_WREG32
	ldr	w0, [x21]
Lloh17:
	adrp	x8, _mmVCE_LMI_CACHE_CTRL@GOTPAGE
Lloh18:
	ldr	x8, [x8, _mmVCE_LMI_CACHE_CTRL@GOTPAGEOFF]
Lloh19:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	mov	w2, #-2
	bl	_WREG32_P
	ldr	w0, [x21]
Lloh20:
	adrp	x8, _mmVCE_LMI_SWAP_CNTL@GOTPAGE
Lloh21:
	ldr	x8, [x8, _mmVCE_LMI_SWAP_CNTL@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x21]
Lloh23:
	adrp	x8, _mmVCE_LMI_SWAP_CNTL1@GOTPAGE
Lloh24:
	ldr	x8, [x8, _mmVCE_LMI_SWAP_CNTL1@GOTPAGEOFF]
Lloh25:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x21]
Lloh26:
	adrp	x8, _mmVCE_LMI_VM_CTRL@GOTPAGE
Lloh27:
	ldr	x8, [x8, _mmVCE_LMI_VM_CTRL@GOTPAGEOFF]
Lloh28:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_WREG32
Lloh29:
	adrp	x8, _AMDGPU_VCE_FIRMWARE_OFFSET@GOTPAGE
Lloh30:
	ldr	x8, [x8, _AMDGPU_VCE_FIRMWARE_OFFSET@GOTPAGEOFF]
Lloh31:
	ldr	w22, [x8]
Lloh32:
	adrp	x23, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh33:
	ldr	x23, [x23, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
	ldr	x20, [x19, #8]
	ldr	x24, [x23]
	ldr	w0, [x21]
Lloh34:
	adrp	x8, _mmVCE_LMI_VCPU_CACHE_40BIT_BAR0@GOTPAGE
Lloh35:
	ldr	x8, [x8, _mmVCE_LMI_VCPU_CACHE_40BIT_BAR0@GOTPAGEOFF]
Lloh36:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	cmp	x20, x24
	b.ne	LBB0_2
; %bb.1:
	bl	_WREG32
	ldr	w0, [x21]
Lloh37:
	adrp	x8, _mmVCE_LMI_VCPU_CACHE_64BIT_BAR0@GOTPAGE
Lloh38:
	ldr	x8, [x8, _mmVCE_LMI_VCPU_CACHE_64BIT_BAR0@GOTPAGEOFF]
Lloh39:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	bl	_WREG32
	ldr	w0, [x21]
Lloh40:
	adrp	x8, _mmVCE_VCPU_CACHE_OFFSET0@GOTPAGE
Lloh41:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_OFFSET0@GOTPAGEOFF]
Lloh42:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	b	LBB0_3
LBB0_2:
	ldr	w8, [x19]
	asr	w1, w8, #8
	bl	_WREG32
	ldr	w0, [x21]
Lloh43:
	adrp	x8, _mmVCE_LMI_VCPU_CACHE_64BIT_BAR0@GOTPAGE
Lloh44:
	ldr	x8, [x8, _mmVCE_LMI_VCPU_CACHE_64BIT_BAR0@GOTPAGEOFF]
Lloh45:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	bl	_WREG32
	ldr	w0, [x21]
Lloh46:
	adrp	x8, _mmVCE_VCPU_CACHE_OFFSET0@GOTPAGE
Lloh47:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_OFFSET0@GOTPAGEOFF]
Lloh48:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	and	w1, w22, #0xf0ffffff
LBB0_3:
	bl	_WREG32
Lloh49:
	adrp	x8, _VCE_V4_0_FW_SIZE@GOTPAGE
Lloh50:
	ldr	x8, [x8, _VCE_V4_0_FW_SIZE@GOTPAGEOFF]
Lloh51:
	ldr	w20, [x8]
	ldr	w0, [x21]
Lloh52:
	adrp	x8, _mmVCE_VCPU_CACHE_SIZE0@GOTPAGE
Lloh53:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_SIZE0@GOTPAGEOFF]
Lloh54:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x1, x20
	bl	_WREG32
	ldr	w0, [x21]
Lloh55:
	adrp	x8, _mmVCE_LMI_VCPU_CACHE_40BIT_BAR1@GOTPAGE
Lloh56:
	ldr	x8, [x8, _mmVCE_LMI_VCPU_CACHE_40BIT_BAR1@GOTPAGEOFF]
Lloh57:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x19]
	asr	w1, w8, #8
	bl	_WREG32
	ldr	w0, [x21]
Lloh58:
	adrp	x8, _mmVCE_LMI_VCPU_CACHE_64BIT_BAR1@GOTPAGE
Lloh59:
	ldr	x8, [x8, _mmVCE_LMI_VCPU_CACHE_64BIT_BAR1@GOTPAGEOFF]
Lloh60:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	bl	_WREG32
	ldr	x8, [x19, #8]
	ldr	x9, [x23]
	add	w10, w20, w22
	cmp	x8, x9
Lloh61:
	adrp	x8, _VCE_V4_0_STACK_SIZE@GOTPAGE
Lloh62:
	ldr	x8, [x8, _VCE_V4_0_STACK_SIZE@GOTPAGEOFF]
	csel	w22, wzr, w10, eq
Lloh63:
	ldr	w20, [x8]
	ldr	w0, [x21]
Lloh64:
	adrp	x8, _mmVCE_VCPU_CACHE_OFFSET1@GOTPAGE
Lloh65:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_OFFSET1@GOTPAGEOFF]
Lloh66:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	and	w8, w22, #0xf0ffffff
	orr	w1, w8, #0x1000000
	bl	_WREG32
	ldr	w0, [x21]
Lloh67:
	adrp	x8, _mmVCE_VCPU_CACHE_SIZE1@GOTPAGE
Lloh68:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_SIZE1@GOTPAGEOFF]
Lloh69:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x1, x20
	bl	_WREG32
	ldr	w0, [x21]
Lloh70:
	adrp	x8, _mmVCE_LMI_VCPU_CACHE_40BIT_BAR2@GOTPAGE
Lloh71:
	ldr	x8, [x8, _mmVCE_LMI_VCPU_CACHE_40BIT_BAR2@GOTPAGEOFF]
Lloh72:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x19]
	asr	w1, w8, #8
	bl	_WREG32
	ldr	w0, [x21]
Lloh73:
	adrp	x8, _mmVCE_LMI_VCPU_CACHE_64BIT_BAR2@GOTPAGE
Lloh74:
	ldr	x8, [x8, _mmVCE_LMI_VCPU_CACHE_64BIT_BAR2@GOTPAGEOFF]
Lloh75:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	bl	_WREG32
Lloh76:
	adrp	x8, _VCE_V4_0_DATA_SIZE@GOTPAGE
Lloh77:
	ldr	x8, [x8, _VCE_V4_0_DATA_SIZE@GOTPAGEOFF]
	add	w20, w22, w20
Lloh78:
	ldr	w19, [x8]
	ldr	w0, [x21]
Lloh79:
	adrp	x8, _mmVCE_VCPU_CACHE_OFFSET2@GOTPAGE
Lloh80:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_OFFSET2@GOTPAGEOFF]
Lloh81:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	and	w8, w20, #0xf0ffffff
	orr	w1, w8, #0x2000000
	bl	_WREG32
	ldr	w0, [x21]
Lloh82:
	adrp	x8, _mmVCE_VCPU_CACHE_SIZE2@GOTPAGE
Lloh83:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_SIZE2@GOTPAGEOFF]
Lloh84:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x1, x19
	bl	_WREG32
	ldr	w0, [x21]
Lloh85:
	adrp	x8, _mmVCE_LMI_CTRL2@GOTPAGE
Lloh86:
	ldr	x8, [x8, _mmVCE_LMI_CTRL2@GOTPAGEOFF]
Lloh87:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	mov	w2, #-257
	bl	_WREG32_P
	ldr	w0, [x21]
Lloh88:
	adrp	x8, _mmVCE_SYS_INT_EN@GOTPAGE
Lloh89:
	ldr	x8, [x8, _mmVCE_SYS_INT_EN@GOTPAGEOFF]
Lloh90:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh91:
	adrp	x8, _VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK@GOTPAGE
Lloh92:
	ldr	x8, [x8, _VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK@GOTPAGEOFF]
Lloh93:
	ldr	w1, [x8]
	mvn	w2, w1
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_WREG32_P
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.cfi_endproc
                                        ; -- End function
	.comm	_VCE,4,2                        ; @VCE
	.comm	_mmVCE_CLOCK_GATING_A,4,2       ; @mmVCE_CLOCK_GATING_A
	.comm	_mmVCE_UENC_CLOCK_GATING,4,2    ; @mmVCE_UENC_CLOCK_GATING
	.comm	_mmVCE_UENC_REG_CLOCK_GATING,4,2 ; @mmVCE_UENC_REG_CLOCK_GATING
	.comm	_mmVCE_CLOCK_GATING_B,4,2       ; @mmVCE_CLOCK_GATING_B
	.comm	_mmVCE_LMI_CTRL,4,2             ; @mmVCE_LMI_CTRL
	.comm	_mmVCE_LMI_CACHE_CTRL,4,2       ; @mmVCE_LMI_CACHE_CTRL
	.comm	_mmVCE_LMI_SWAP_CNTL,4,2        ; @mmVCE_LMI_SWAP_CNTL
	.comm	_mmVCE_LMI_SWAP_CNTL1,4,2       ; @mmVCE_LMI_SWAP_CNTL1
	.comm	_mmVCE_LMI_VM_CTRL,4,2          ; @mmVCE_LMI_VM_CTRL
	.comm	_AMDGPU_VCE_FIRMWARE_OFFSET,4,2 ; @AMDGPU_VCE_FIRMWARE_OFFSET
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_VCE,8,3        ; @AMDGPU_UCODE_ID_VCE
	.comm	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR0,4,2 ; @mmVCE_LMI_VCPU_CACHE_40BIT_BAR0
	.comm	_mmVCE_LMI_VCPU_CACHE_64BIT_BAR0,4,2 ; @mmVCE_LMI_VCPU_CACHE_64BIT_BAR0
	.comm	_mmVCE_VCPU_CACHE_OFFSET0,4,2   ; @mmVCE_VCPU_CACHE_OFFSET0
	.comm	_VCE_V4_0_FW_SIZE,4,2           ; @VCE_V4_0_FW_SIZE
	.comm	_mmVCE_VCPU_CACHE_SIZE0,4,2     ; @mmVCE_VCPU_CACHE_SIZE0
	.comm	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR1,4,2 ; @mmVCE_LMI_VCPU_CACHE_40BIT_BAR1
	.comm	_mmVCE_LMI_VCPU_CACHE_64BIT_BAR1,4,2 ; @mmVCE_LMI_VCPU_CACHE_64BIT_BAR1
	.comm	_VCE_V4_0_STACK_SIZE,4,2        ; @VCE_V4_0_STACK_SIZE
	.comm	_mmVCE_VCPU_CACHE_OFFSET1,4,2   ; @mmVCE_VCPU_CACHE_OFFSET1
	.comm	_mmVCE_VCPU_CACHE_SIZE1,4,2     ; @mmVCE_VCPU_CACHE_SIZE1
	.comm	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR2,4,2 ; @mmVCE_LMI_VCPU_CACHE_40BIT_BAR2
	.comm	_mmVCE_LMI_VCPU_CACHE_64BIT_BAR2,4,2 ; @mmVCE_LMI_VCPU_CACHE_64BIT_BAR2
	.comm	_VCE_V4_0_DATA_SIZE,4,2         ; @VCE_V4_0_DATA_SIZE
	.comm	_mmVCE_VCPU_CACHE_OFFSET2,4,2   ; @mmVCE_VCPU_CACHE_OFFSET2
	.comm	_mmVCE_VCPU_CACHE_SIZE2,4,2     ; @mmVCE_VCPU_CACHE_SIZE2
	.comm	_mmVCE_LMI_CTRL2,4,2            ; @mmVCE_LMI_CTRL2
	.comm	_mmVCE_SYS_INT_EN,4,2           ; @mmVCE_SYS_INT_EN
	.comm	_VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK,4,2 ; @VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK
	.no_dead_strip	_vce_v4_0_mc_resume
.subsections_via_symbols
