	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function evergreen_pcie_gart_enable
_evergreen_pcie_gart_enable:            ## @evergreen_pcie_gart_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	cmpq	$0, 24(%rdi)
	je	LBB0_1
## %bb.2:
	movq	%r14, %rdi
	callq	_radeon_gart_table_vram_pin
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_11
## %bb.3:
	movq	_VM_L2_CNTL@GOTPCREL(%rip), %rax
	movq	_ENABLE_L2_CACHE@GOTPCREL(%rip), %rcx
	movq	_ENABLE_L2_FRAGMENT_PROCESSING@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	movl	(%rax), %r15d
	movq	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	$7, %edi
	callq	_EFFECTIVE_L2_QUEUE_SIZE
	orl	%eax, %ebx
	movl	%r15d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_VM_L2_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_VM_L2_CNTL3@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	xorl	%edi, %edi
	callq	_BANK_SELECT
	movl	%eax, %ebx
	movl	$2, %edi
	callq	_CACHE_UPDATE_MODE
	orl	%eax, %ebx
	movl	%r15d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_ENABLE_L1_TLB@GOTPCREL(%rip), %rax
	movq	_ENABLE_L1_FRAGMENT_PROCESSING@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	_SYSTEM_ACCESS_MODE_NOT_IN_SYS@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	$5, %edi
	callq	_EFFECTIVE_L1_TLB_SIZE
	movl	%eax, %r15d
	movl	$5, %edi
	callq	_EFFECTIVE_L1_QUEUE_SIZE
	movl	%eax, %r12d
	orl	%r15d, %r12d
	orl	%ebx, %r12d
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r14)
	je	LBB0_5
## %bb.4:
	movq	_FUS_MC_VM_MD_L1_TLB0_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_FUS_MC_VM_MD_L1_TLB1_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_FUS_MC_VM_MD_L1_TLB2_CNTL@GOTPCREL(%rip), %rax
LBB0_9:
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
LBB0_10:
	movq	_MC_VM_MB_L1_TLB0_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_MC_VM_MB_L1_TLB1_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_MC_VM_MB_L1_TLB2_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_MC_VM_MB_L1_TLB3_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_VM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	32(%r14), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_VM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	36(%r14), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	16(%r14), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_VM_CONTEXT0_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_ENABLE_CONTEXT@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	_PAGE_TABLE_DEPTH
	orl	%eax, %r12d
	movq	_RANGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
	movl	%r15d, %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	44(%r14), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_VM_CONTEXT1_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	%r14, %rdi
	callq	_evergreen_pcie_gart_tlb_flush
	movl	40(%r14), %esi
	sarl	$20, %esi
	movslq	16(%r14), %rdx
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_INFO
	movl	$1, 20(%r14)
	jmp	LBB0_11
LBB0_1:
	movl	48(%r14), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
LBB0_11:
	movl	%ebx, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_5:
	movq	_MC_VM_MD_L1_TLB0_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_MC_VM_MD_L1_TLB1_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_MC_VM_MD_L1_TLB2_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	8(%r14), %rcx
	movq	_CHIP_JUNIPER@GOTPCREL(%rip), %rdx
	movq	_MC_VM_MD_L1_TLB3_CNTL@GOTPCREL(%rip), %rax
	cmpq	(%rdx), %rcx
	je	LBB0_9
## %bb.6:
	movq	_CHIP_CYPRESS@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	je	LBB0_9
## %bb.7:
	movq	_CHIP_HEMLOCK@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	je	LBB0_9
## %bb.8:
	movq	_CHIP_BARTS@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_10
	jmp	LBB0_9
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"No VRAM object for PCIE GART.\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_VM_L2_CNTL,4,2                 ## @VM_L2_CNTL
	.comm	_ENABLE_L2_CACHE,4,2            ## @ENABLE_L2_CACHE
	.comm	_ENABLE_L2_FRAGMENT_PROCESSING,4,2 ## @ENABLE_L2_FRAGMENT_PROCESSING
	.comm	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE,4,2 ## @ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_VM_L2_CNTL2,4,2                ## @VM_L2_CNTL2
	.comm	_VM_L2_CNTL3,4,2                ## @VM_L2_CNTL3
	.comm	_ENABLE_L1_TLB,4,2              ## @ENABLE_L1_TLB
	.comm	_ENABLE_L1_FRAGMENT_PROCESSING,4,2 ## @ENABLE_L1_FRAGMENT_PROCESSING
	.comm	_SYSTEM_ACCESS_MODE_NOT_IN_SYS,4,2 ## @SYSTEM_ACCESS_MODE_NOT_IN_SYS
	.comm	_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU,4,2 ## @SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
	.comm	_FUS_MC_VM_MD_L1_TLB0_CNTL,4,2  ## @FUS_MC_VM_MD_L1_TLB0_CNTL
	.comm	_FUS_MC_VM_MD_L1_TLB1_CNTL,4,2  ## @FUS_MC_VM_MD_L1_TLB1_CNTL
	.comm	_FUS_MC_VM_MD_L1_TLB2_CNTL,4,2  ## @FUS_MC_VM_MD_L1_TLB2_CNTL
	.comm	_MC_VM_MD_L1_TLB0_CNTL,4,2      ## @MC_VM_MD_L1_TLB0_CNTL
	.comm	_MC_VM_MD_L1_TLB1_CNTL,4,2      ## @MC_VM_MD_L1_TLB1_CNTL
	.comm	_MC_VM_MD_L1_TLB2_CNTL,4,2      ## @MC_VM_MD_L1_TLB2_CNTL
	.comm	_CHIP_JUNIPER,8,3               ## @CHIP_JUNIPER
	.comm	_CHIP_CYPRESS,8,3               ## @CHIP_CYPRESS
	.comm	_CHIP_HEMLOCK,8,3               ## @CHIP_HEMLOCK
	.comm	_CHIP_BARTS,8,3                 ## @CHIP_BARTS
	.comm	_MC_VM_MD_L1_TLB3_CNTL,4,2      ## @MC_VM_MD_L1_TLB3_CNTL
	.comm	_MC_VM_MB_L1_TLB0_CNTL,4,2      ## @MC_VM_MB_L1_TLB0_CNTL
	.comm	_MC_VM_MB_L1_TLB1_CNTL,4,2      ## @MC_VM_MB_L1_TLB1_CNTL
	.comm	_MC_VM_MB_L1_TLB2_CNTL,4,2      ## @MC_VM_MB_L1_TLB2_CNTL
	.comm	_MC_VM_MB_L1_TLB3_CNTL,4,2      ## @MC_VM_MB_L1_TLB3_CNTL
	.comm	_VM_CONTEXT0_PAGE_TABLE_START_ADDR,4,2 ## @VM_CONTEXT0_PAGE_TABLE_START_ADDR
	.comm	_VM_CONTEXT0_PAGE_TABLE_END_ADDR,4,2 ## @VM_CONTEXT0_PAGE_TABLE_END_ADDR
	.comm	_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR,4,2 ## @VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
	.comm	_VM_CONTEXT0_CNTL,4,2           ## @VM_CONTEXT0_CNTL
	.comm	_ENABLE_CONTEXT,4,2             ## @ENABLE_CONTEXT
	.comm	_RANGE_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ## @RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,4,2 ## @VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
	.comm	_VM_CONTEXT1_CNTL,4,2           ## @VM_CONTEXT1_CNTL
L_.str.1:                               ## @.str.1
	.asciz	"PCIE GART of %uM enabled (table at 0x%016llX).\n"

	.no_dead_strip	_evergreen_pcie_gart_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function evergreen_pcie_gart_enable
_evergreen_pcie_gart_enable:            ; @evergreen_pcie_gart_enable
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x8, [x0, #24]
	cbz	x8, LBB0_6
; %bb.1:
	mov	x0, x19
	bl	_radeon_gart_table_vram_pin
	cbnz	w0, LBB0_7
; %bb.2:
Lloh0:
	adrp	x8, _VM_L2_CNTL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _VM_L2_CNTL@GOTPAGEOFF]
Lloh2:
	ldr	w20, [x8]
Lloh3:
	adrp	x8, _ENABLE_L2_CACHE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _ENABLE_L2_CACHE@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
Lloh6:
	adrp	x9, _ENABLE_L2_FRAGMENT_PROCESSING@GOTPAGE
Lloh7:
	ldr	x9, [x9, _ENABLE_L2_FRAGMENT_PROCESSING@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh9:
	adrp	x9, _ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGE
Lloh10:
	ldr	x9, [x9, _ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	orr	w21, w8, w9
	mov	w0, #7
	bl	_EFFECTIVE_L2_QUEUE_SIZE
	orr	w1, w21, w0
	mov	x0, x20
	bl	_WREG32
Lloh12:
	adrp	x8, _VM_L2_CNTL2@GOTPAGE
Lloh13:
	ldr	x8, [x8, _VM_L2_CNTL2@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh15:
	adrp	x8, _VM_L2_CNTL3@GOTPAGE
Lloh16:
	ldr	x8, [x8, _VM_L2_CNTL3@GOTPAGEOFF]
Lloh17:
	ldr	w20, [x8]
	mov	w0, #0
	bl	_BANK_SELECT
	mov	x21, x0
	mov	w0, #2
	bl	_CACHE_UPDATE_MODE
	orr	w1, w0, w21
	mov	x0, x20
	bl	_WREG32
Lloh18:
	adrp	x8, _ENABLE_L1_TLB@GOTPAGE
Lloh19:
	ldr	x8, [x8, _ENABLE_L1_TLB@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
Lloh21:
	adrp	x9, _ENABLE_L1_FRAGMENT_PROCESSING@GOTPAGE
Lloh22:
	ldr	x9, [x9, _ENABLE_L1_FRAGMENT_PROCESSING@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh24:
	adrp	x9, _SYSTEM_ACCESS_MODE_NOT_IN_SYS@GOTPAGE
Lloh25:
	ldr	x9, [x9, _SYSTEM_ACCESS_MODE_NOT_IN_SYS@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh27:
	adrp	x9, _SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU@GOTPAGE
Lloh28:
	ldr	x9, [x9, _SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	orr	w20, w8, w9
	mov	w0, #5
	bl	_EFFECTIVE_L1_TLB_SIZE
	orr	w20, w20, w0
	mov	w0, #5
	bl	_EFFECTIVE_L1_QUEUE_SIZE
	orr	w20, w20, w0
	ldr	w8, [x19]
Lloh30:
	adrp	x9, _RADEON_IS_IGP@GOTPAGE
Lloh31:
	ldr	x9, [x9, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_8
; %bb.3:
Lloh33:
	adrp	x8, _FUS_MC_VM_MD_L1_TLB0_CNTL@GOTPAGE
Lloh34:
	ldr	x8, [x8, _FUS_MC_VM_MD_L1_TLB0_CNTL@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh36:
	adrp	x8, _FUS_MC_VM_MD_L1_TLB1_CNTL@GOTPAGE
Lloh37:
	ldr	x8, [x8, _FUS_MC_VM_MD_L1_TLB1_CNTL@GOTPAGEOFF]
Lloh38:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh39:
	adrp	x8, _FUS_MC_VM_MD_L1_TLB2_CNTL@GOTPAGE
Lloh40:
	ldr	x8, [x8, _FUS_MC_VM_MD_L1_TLB2_CNTL@GOTPAGEOFF]
LBB0_4:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
LBB0_5:
Lloh41:
	adrp	x8, _MC_VM_MB_L1_TLB0_CNTL@GOTPAGE
Lloh42:
	ldr	x8, [x8, _MC_VM_MB_L1_TLB0_CNTL@GOTPAGEOFF]
Lloh43:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh44:
	adrp	x8, _MC_VM_MB_L1_TLB1_CNTL@GOTPAGE
Lloh45:
	ldr	x8, [x8, _MC_VM_MB_L1_TLB1_CNTL@GOTPAGEOFF]
Lloh46:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh47:
	adrp	x8, _MC_VM_MB_L1_TLB2_CNTL@GOTPAGE
Lloh48:
	ldr	x8, [x8, _MC_VM_MB_L1_TLB2_CNTL@GOTPAGEOFF]
Lloh49:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh50:
	adrp	x8, _MC_VM_MB_L1_TLB3_CNTL@GOTPAGE
Lloh51:
	ldr	x8, [x8, _MC_VM_MB_L1_TLB3_CNTL@GOTPAGEOFF]
Lloh52:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh53:
	adrp	x8, _VM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPAGE
Lloh54:
	ldr	x8, [x8, _VM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPAGEOFF]
Lloh55:
	ldr	w0, [x8]
	ldr	w8, [x19, #32]
	asr	w1, w8, #12
	bl	_WREG32
Lloh56:
	adrp	x8, _VM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPAGE
Lloh57:
	ldr	x8, [x8, _VM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPAGEOFF]
Lloh58:
	ldr	w0, [x8]
	ldr	w8, [x19, #36]
	asr	w1, w8, #12
	bl	_WREG32
Lloh59:
	adrp	x8, _VM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPAGE
Lloh60:
	ldr	x8, [x8, _VM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPAGEOFF]
Lloh61:
	ldr	w0, [x8]
	ldr	w8, [x19, #16]
	asr	w1, w8, #12
	bl	_WREG32
Lloh62:
	adrp	x8, _VM_CONTEXT0_CNTL@GOTPAGE
Lloh63:
	ldr	x8, [x8, _VM_CONTEXT0_CNTL@GOTPAGEOFF]
Lloh64:
	ldr	w20, [x8]
Lloh65:
	adrp	x8, _ENABLE_CONTEXT@GOTPAGE
Lloh66:
	ldr	x8, [x8, _ENABLE_CONTEXT@GOTPAGEOFF]
Lloh67:
	ldr	w21, [x8]
	mov	w0, #0
	bl	_PAGE_TABLE_DEPTH
	orr	w8, w0, w21
Lloh68:
	adrp	x9, _RANGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGE
Lloh69:
	ldr	x9, [x9, _RANGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGEOFF]
Lloh70:
	ldr	w9, [x9]
	orr	w1, w8, w9
	mov	x0, x20
	bl	_WREG32
Lloh71:
	adrp	x8, _VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR@GOTPAGE
Lloh72:
	ldr	x8, [x8, _VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR@GOTPAGEOFF]
Lloh73:
	ldr	w0, [x8]
	ldr	w8, [x19, #44]
	asr	w1, w8, #12
	bl	_WREG32
Lloh74:
	adrp	x8, _VM_CONTEXT1_CNTL@GOTPAGE
Lloh75:
	ldr	x8, [x8, _VM_CONTEXT1_CNTL@GOTPAGEOFF]
Lloh76:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	mov	x0, x19
	bl	_evergreen_pcie_gart_tlb_flush
	ldr	w8, [x19, #40]
	asr	w1, w8, #20
	ldrsw	x2, [x19, #16]
Lloh77:
	adrp	x0, l_.str.1@PAGE
Lloh78:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_INFO
	mov	w0, #0
	mov	w8, #1
	str	w8, [x19, #20]
	b	LBB0_7
LBB0_6:
	ldr	w0, [x19, #48]
Lloh79:
	adrp	x1, l_.str@PAGE
Lloh80:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
Lloh81:
	adrp	x8, _EINVAL@GOTPAGE
Lloh82:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh83:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_7:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_8:
Lloh84:
	adrp	x8, _MC_VM_MD_L1_TLB0_CNTL@GOTPAGE
Lloh85:
	ldr	x8, [x8, _MC_VM_MD_L1_TLB0_CNTL@GOTPAGEOFF]
Lloh86:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh87:
	adrp	x8, _MC_VM_MD_L1_TLB1_CNTL@GOTPAGE
Lloh88:
	ldr	x8, [x8, _MC_VM_MD_L1_TLB1_CNTL@GOTPAGEOFF]
Lloh89:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh90:
	adrp	x8, _MC_VM_MD_L1_TLB2_CNTL@GOTPAGE
Lloh91:
	ldr	x8, [x8, _MC_VM_MD_L1_TLB2_CNTL@GOTPAGEOFF]
Lloh92:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
	ldr	x9, [x19, #8]
Lloh93:
	adrp	x8, _CHIP_JUNIPER@GOTPAGE
Lloh94:
	ldr	x8, [x8, _CHIP_JUNIPER@GOTPAGEOFF]
Lloh95:
	ldr	x10, [x8]
Lloh96:
	adrp	x8, _MC_VM_MD_L1_TLB3_CNTL@GOTPAGE
Lloh97:
	ldr	x8, [x8, _MC_VM_MD_L1_TLB3_CNTL@GOTPAGEOFF]
	cmp	x9, x10
	b.eq	LBB0_4
; %bb.9:
Lloh98:
	adrp	x10, _CHIP_CYPRESS@GOTPAGE
Lloh99:
	ldr	x10, [x10, _CHIP_CYPRESS@GOTPAGEOFF]
Lloh100:
	ldr	x10, [x10]
	cmp	x9, x10
	b.eq	LBB0_4
; %bb.10:
Lloh101:
	adrp	x10, _CHIP_HEMLOCK@GOTPAGE
Lloh102:
	ldr	x10, [x10, _CHIP_HEMLOCK@GOTPAGEOFF]
Lloh103:
	ldr	x10, [x10]
	cmp	x9, x10
	b.eq	LBB0_4
; %bb.11:
Lloh104:
	adrp	x10, _CHIP_BARTS@GOTPAGE
Lloh105:
	ldr	x10, [x10, _CHIP_BARTS@GOTPAGEOFF]
Lloh106:
	ldr	x10, [x10]
	cmp	x9, x10
	b.ne	LBB0_5
	b	LBB0_4
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpAdd	Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpAdd	Lloh79, Lloh80
	.loh AdrpLdrGot	Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"No VRAM object for PCIE GART.\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_VM_L2_CNTL,4,2                 ; @VM_L2_CNTL
	.comm	_ENABLE_L2_CACHE,4,2            ; @ENABLE_L2_CACHE
	.comm	_ENABLE_L2_FRAGMENT_PROCESSING,4,2 ; @ENABLE_L2_FRAGMENT_PROCESSING
	.comm	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE,4,2 ; @ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_VM_L2_CNTL2,4,2                ; @VM_L2_CNTL2
	.comm	_VM_L2_CNTL3,4,2                ; @VM_L2_CNTL3
	.comm	_ENABLE_L1_TLB,4,2              ; @ENABLE_L1_TLB
	.comm	_ENABLE_L1_FRAGMENT_PROCESSING,4,2 ; @ENABLE_L1_FRAGMENT_PROCESSING
	.comm	_SYSTEM_ACCESS_MODE_NOT_IN_SYS,4,2 ; @SYSTEM_ACCESS_MODE_NOT_IN_SYS
	.comm	_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU,4,2 ; @SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
	.comm	_FUS_MC_VM_MD_L1_TLB0_CNTL,4,2  ; @FUS_MC_VM_MD_L1_TLB0_CNTL
	.comm	_FUS_MC_VM_MD_L1_TLB1_CNTL,4,2  ; @FUS_MC_VM_MD_L1_TLB1_CNTL
	.comm	_FUS_MC_VM_MD_L1_TLB2_CNTL,4,2  ; @FUS_MC_VM_MD_L1_TLB2_CNTL
	.comm	_MC_VM_MD_L1_TLB0_CNTL,4,2      ; @MC_VM_MD_L1_TLB0_CNTL
	.comm	_MC_VM_MD_L1_TLB1_CNTL,4,2      ; @MC_VM_MD_L1_TLB1_CNTL
	.comm	_MC_VM_MD_L1_TLB2_CNTL,4,2      ; @MC_VM_MD_L1_TLB2_CNTL
	.comm	_CHIP_JUNIPER,8,3               ; @CHIP_JUNIPER
	.comm	_CHIP_CYPRESS,8,3               ; @CHIP_CYPRESS
	.comm	_CHIP_HEMLOCK,8,3               ; @CHIP_HEMLOCK
	.comm	_CHIP_BARTS,8,3                 ; @CHIP_BARTS
	.comm	_MC_VM_MD_L1_TLB3_CNTL,4,2      ; @MC_VM_MD_L1_TLB3_CNTL
	.comm	_MC_VM_MB_L1_TLB0_CNTL,4,2      ; @MC_VM_MB_L1_TLB0_CNTL
	.comm	_MC_VM_MB_L1_TLB1_CNTL,4,2      ; @MC_VM_MB_L1_TLB1_CNTL
	.comm	_MC_VM_MB_L1_TLB2_CNTL,4,2      ; @MC_VM_MB_L1_TLB2_CNTL
	.comm	_MC_VM_MB_L1_TLB3_CNTL,4,2      ; @MC_VM_MB_L1_TLB3_CNTL
	.comm	_VM_CONTEXT0_PAGE_TABLE_START_ADDR,4,2 ; @VM_CONTEXT0_PAGE_TABLE_START_ADDR
	.comm	_VM_CONTEXT0_PAGE_TABLE_END_ADDR,4,2 ; @VM_CONTEXT0_PAGE_TABLE_END_ADDR
	.comm	_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR,4,2 ; @VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
	.comm	_VM_CONTEXT0_CNTL,4,2           ; @VM_CONTEXT0_CNTL
	.comm	_ENABLE_CONTEXT,4,2             ; @ENABLE_CONTEXT
	.comm	_RANGE_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ; @RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,4,2 ; @VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
	.comm	_VM_CONTEXT1_CNTL,4,2           ; @VM_CONTEXT1_CNTL
l_.str.1:                               ; @.str.1
	.asciz	"PCIE GART of %uM enabled (table at 0x%016llX).\n"

	.no_dead_strip	_evergreen_pcie_gart_enable
.subsections_via_symbols
