	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v9_0_ring_emit_hdp_flush
_gfx_v9_0_ring_emit_hdp_flush:          ## @gfx_v9_0_ring_emit_hdp_flush
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	8(%rdi), %rdx
	movq	16(%rdi), %rbx
	movq	(%rbx), %rax
	movq	16(%rax), %rcx
	movq	(%rdx), %rdx
	movq	_AMDGPU_RING_TYPE_COMPUTE@GOTPCREL(%rip), %rsi
	cmpq	(%rsi), %rdx
	jne	LBB0_6
## %bb.1:
	movl	(%r14), %edx
	cmpl	$2, %edx
	je	LBB0_5
## %bb.2:
	cmpl	$1, %edx
	jne	LBB0_8
## %bb.3:
	movl	(%rcx), %r13d
	jmp	LBB0_4
LBB0_6:
	movl	8(%rcx), %r13d
	movl	$1, %r15d
	jmp	LBB0_7
LBB0_5:
	movl	4(%rcx), %r13d
LBB0_4:
	movb	4(%r14), %cl
	shll	%cl, %r13d
	xorl	%r15d, %r15d
LBB0_7:
	movq	%rbx, %rdi
	callq	*8(%rax)
	movl	%eax, %r12d
	movq	(%rbx), %rax
	movq	%rbx, %rdi
	callq	*(%rax)
	subq	$8, %rsp
	movq	%r14, %rdi
	movl	%r15d, %esi
	xorl	%edx, %edx
	movl	$1, %ecx
	movl	%r12d, %r8d
	movl	%eax, %r9d
	pushq	$32
	pushq	%r13
	pushq	%r13
	callq	_gfx_v9_0_wait_reg_mem
	addq	$40, %rsp
LBB0_9:
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_8:
	addq	$8, %rsp
	jmp	LBB0_9
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_RING_TYPE_COMPUTE,8,3   ## @AMDGPU_RING_TYPE_COMPUTE
	.no_dead_strip	_gfx_v9_0_ring_emit_hdp_flush
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v9_0_ring_emit_hdp_flush
_gfx_v9_0_ring_emit_hdp_flush:          ; @gfx_v9_0_ring_emit_hdp_flush
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldp	x10, x20, [x0, #8]
	ldr	x8, [x20]
	ldr	x9, [x8, #16]
	ldr	x10, [x10]
Lloh0:
	adrp	x11, _AMDGPU_RING_TYPE_COMPUTE@GOTPAGE
Lloh1:
	ldr	x11, [x11, _AMDGPU_RING_TYPE_COMPUTE@GOTPAGEOFF]
Lloh2:
	ldr	x11, [x11]
	cmp	x10, x11
	b.ne	LBB0_4
; %bb.1:
	ldr	w10, [x19]
	cmp	w10, #2
	b.eq	LBB0_5
; %bb.2:
	cmp	w10, #1
	b.ne	LBB0_8
; %bb.3:
	mov	w21, #0
	ldr	w9, [x9]
	b	LBB0_6
LBB0_4:
	ldr	w22, [x9, #8]
	mov	w21, #1
	b	LBB0_7
LBB0_5:
	mov	w21, #0
	ldr	w9, [x9, #4]
LBB0_6:
	ldr	w10, [x19, #4]
	lsl	w22, w9, w10
LBB0_7:
	ldr	x8, [x8, #8]
	mov	x0, x20
	blr	x8
	mov	x23, x0
	ldr	x8, [x20]
	ldr	x8, [x8]
	mov	x0, x20
	blr	x8
	mov	x5, x0
	mov	w8, #32
	str	w8, [sp]
	mov	x0, x19
	mov	x1, x21
	mov	w2, #0
	mov	w3, #1
	mov	x4, x23
	mov	x6, x22
	mov	x7, x22
	bl	_gfx_v9_0_wait_reg_mem
LBB0_8:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_RING_TYPE_COMPUTE,8,3   ; @AMDGPU_RING_TYPE_COMPUTE
	.no_dead_strip	_gfx_v9_0_ring_emit_hdp_flush
.subsections_via_symbols
