	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function r700_read_disabled_bios
_r700_read_disabled_bios:               ## @r700_read_disabled_bios
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, -72(%rbp)                 ## 8-byte Spill
	movq	_RADEON_VIPH_CONTROL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32
	movl	%eax, %ebx
	movq	_R600_BUS_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r15d
	movq	_AVIVO_D1VGA_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r12d
	movq	_AVIVO_D2VGA_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r13d
	movq	_AVIVO_VGA_RENDER_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_R600_ROM_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movl	(%r14), %edi
	movq	_RADEON_VIPH_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	movl	%ebx, -64(%rbp)                 ## 4-byte Spill
	andl	%ebx, %esi
	callq	_WREG32
	movq	_R600_BUS_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_R600_BIOS_ROM_DIS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	movl	%r15d, -60(%rbp)                ## 4-byte Spill
	andl	%r15d, %esi
	callq	_WREG32
	movq	_AVIVO_D1VGA_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_AVIVO_DVGA_CONTROL_MODE_ENABLE@GOTPCREL(%rip), %r14
	movq	_AVIVO_DVGA_CONTROL_TIMING_SELECT@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	orl	(%r14), %esi
	notl	%esi
	movl	%r12d, -56(%rbp)                ## 4-byte Spill
	andl	%r12d, %esi
	callq	_WREG32
	movq	_AVIVO_D2VGA_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%rbx), %esi
	orl	(%r14), %esi
	notl	%esi
	movl	%r13d, -52(%rbp)                ## 4-byte Spill
	andl	%r13d, %esi
	callq	_WREG32
	movq	_AVIVO_VGA_RENDER_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_AVIVO_VGA_VSTATUS_CNTL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	-48(%rbp), %esi                 ## 4-byte Folded Reload
	callq	_WREG32
	movq	-72(%rbp), %rax                 ## 8-byte Reload
	movq	%rax, %r14
	movq	(%rax), %rax
	movq	_CHIP_RV730@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_4
## %bb.1:
	movq	_R600_ROM_CNTL@GOTPCREL(%rip), %r15
	movq	_R600_CG_SPLL_FUNC_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movl	%eax, %r13d
	movl	(%rbx), %edi
	movq	_R600_SPLL_BYPASS_EN@GOTPCREL(%rip), %rax
	movl	%r13d, %esi
	orl	(%rax), %esi
	callq	_WREG32
	movq	_R600_CG_SPLL_STATUS@GOTPCREL(%rip), %r12
	movq	_R600_SPLL_CHG_STATUS@GOTPCREL(%rip), %rbx
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r12), %edi
	callq	_RREG32
	testl	%eax, (%rbx)
	je	LBB0_2
## %bb.3:
	movl	(%r15), %edi
	movq	_R600_SCK_OVERWRITE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	andl	%eax, %esi
	callq	_WREG32
	jmp	LBB0_5
LBB0_4:
	movq	_R600_ROM_CNTL@GOTPCREL(%rip), %rax
	movq	%rax, %r15
	movl	(%rax), %edi
	movq	_R600_SCK_OVERWRITE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	-44(%rbp), %esi                 ## 4-byte Folded Reload
	callq	_WREG32
	xorl	%r13d, %r13d
LBB0_5:
	movq	%r14, %rdi
	callq	_radeon_read_bios
	movl	%eax, %r12d
	movq	(%r14), %rax
	movq	_CHIP_RV730@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_8
## %bb.6:
	movq	_R600_CG_SPLL_FUNC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r13d, %esi
	callq	_WREG32
	movq	_R600_CG_SPLL_STATUS@GOTPCREL(%rip), %r14
	movq	_R600_SPLL_CHG_STATUS@GOTPCREL(%rip), %rbx
	.p2align	4, 0x90
LBB0_7:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %edi
	callq	_RREG32
	testl	%eax, (%rbx)
	je	LBB0_7
LBB0_8:
	movq	_RADEON_VIPH_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-64(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_R600_BUS_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-60(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_AVIVO_D1VGA_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-56(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_AVIVO_D2VGA_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-52(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_AVIVO_VGA_RENDER_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-48(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movl	(%r15), %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movl	%r12d, %eax
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_VIPH_CONTROL,4,2        ## @RADEON_VIPH_CONTROL
	.comm	_R600_BUS_CNTL,4,2              ## @R600_BUS_CNTL
	.comm	_AVIVO_D1VGA_CONTROL,4,2        ## @AVIVO_D1VGA_CONTROL
	.comm	_AVIVO_D2VGA_CONTROL,4,2        ## @AVIVO_D2VGA_CONTROL
	.comm	_AVIVO_VGA_RENDER_CONTROL,4,2   ## @AVIVO_VGA_RENDER_CONTROL
	.comm	_R600_ROM_CNTL,4,2              ## @R600_ROM_CNTL
	.comm	_RADEON_VIPH_EN,4,2             ## @RADEON_VIPH_EN
	.comm	_R600_BIOS_ROM_DIS,4,2          ## @R600_BIOS_ROM_DIS
	.comm	_AVIVO_DVGA_CONTROL_MODE_ENABLE,4,2 ## @AVIVO_DVGA_CONTROL_MODE_ENABLE
	.comm	_AVIVO_DVGA_CONTROL_TIMING_SELECT,4,2 ## @AVIVO_DVGA_CONTROL_TIMING_SELECT
	.comm	_AVIVO_VGA_VSTATUS_CNTL_MASK,4,2 ## @AVIVO_VGA_VSTATUS_CNTL_MASK
	.comm	_CHIP_RV730,8,3                 ## @CHIP_RV730
	.comm	_R600_CG_SPLL_FUNC_CNTL,4,2     ## @R600_CG_SPLL_FUNC_CNTL
	.comm	_R600_SPLL_BYPASS_EN,4,2        ## @R600_SPLL_BYPASS_EN
	.comm	_R600_SPLL_CHG_STATUS,4,2       ## @R600_SPLL_CHG_STATUS
	.comm	_R600_CG_SPLL_STATUS,4,2        ## @R600_CG_SPLL_STATUS
	.comm	_R600_SCK_OVERWRITE,4,2         ## @R600_SCK_OVERWRITE
	.no_dead_strip	_r700_read_disabled_bios
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function r700_read_disabled_bios
_r700_read_disabled_bios:               ; @r700_read_disabled_bios
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #128
	.cfi_def_cfa_offset 128
	stp	x28, x27, [sp, #32]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #48]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #64]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #80]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #96]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #112]            ; 16-byte Folded Spill
	add	x29, sp, #112
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	str	x0, [sp, #8]                    ; 8-byte Folded Spill
Lloh0:
	adrp	x19, _RADEON_VIPH_CONTROL@GOTPAGE
Lloh1:
	ldr	x19, [x19, _RADEON_VIPH_CONTROL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32
	mov	x27, x0
Lloh2:
	adrp	x20, _R600_BUS_CNTL@GOTPAGE
Lloh3:
	ldr	x20, [x20, _R600_BUS_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	mov	x21, x0
Lloh4:
	adrp	x26, _AVIVO_D1VGA_CONTROL@GOTPAGE
Lloh5:
	ldr	x26, [x26, _AVIVO_D1VGA_CONTROL@GOTPAGEOFF]
	ldr	w0, [x26]
	bl	_RREG32
	mov	x22, x0
Lloh6:
	adrp	x28, _AVIVO_D2VGA_CONTROL@GOTPAGE
Lloh7:
	ldr	x28, [x28, _AVIVO_D2VGA_CONTROL@GOTPAGEOFF]
	ldr	w0, [x28]
	bl	_RREG32
	mov	x24, x0
Lloh8:
	adrp	x23, _AVIVO_VGA_RENDER_CONTROL@GOTPAGE
Lloh9:
	ldr	x23, [x23, _AVIVO_VGA_RENDER_CONTROL@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32
	mov	x25, x0
Lloh10:
	adrp	x8, _R600_ROM_CNTL@GOTPAGE
Lloh11:
	ldr	x8, [x8, _R600_ROM_CNTL@GOTPAGEOFF]
Lloh12:
	ldr	w0, [x8]
	bl	_RREG32
	str	w0, [sp]                        ; 4-byte Folded Spill
	ldr	w0, [x19]
Lloh13:
	adrp	x8, _RADEON_VIPH_EN@GOTPAGE
Lloh14:
	ldr	x8, [x8, _RADEON_VIPH_EN@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
	str	w27, [sp, #28]                  ; 4-byte Folded Spill
	bic	w1, w27, w8
	bl	_WREG32
	ldr	w0, [x20]
Lloh16:
	adrp	x8, _R600_BIOS_ROM_DIS@GOTPAGE
Lloh17:
	ldr	x8, [x8, _R600_BIOS_ROM_DIS@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	str	w21, [sp, #24]                  ; 4-byte Folded Spill
	bic	w1, w21, w8
	bl	_WREG32
	ldr	w0, [x26]
Lloh19:
	adrp	x19, _AVIVO_DVGA_CONTROL_MODE_ENABLE@GOTPAGE
Lloh20:
	ldr	x19, [x19, _AVIVO_DVGA_CONTROL_MODE_ENABLE@GOTPAGEOFF]
	ldr	w8, [x19]
Lloh21:
	adrp	x20, _AVIVO_DVGA_CONTROL_TIMING_SELECT@GOTPAGE
Lloh22:
	ldr	x20, [x20, _AVIVO_DVGA_CONTROL_TIMING_SELECT@GOTPAGEOFF]
	ldr	w9, [x20]
	orr	w8, w9, w8
	bic	w1, w22, w8
	bl	_WREG32
	ldr	w0, [x28]
	ldr	w8, [x19]
	ldr	w9, [x20]
	orr	w8, w9, w8
	str	w24, [sp, #20]                  ; 4-byte Folded Spill
	bic	w1, w24, w8
	bl	_WREG32
	ldr	w0, [x23]
Lloh23:
	adrp	x8, _AVIVO_VGA_VSTATUS_CNTL_MASK@GOTPAGE
Lloh24:
	ldr	x8, [x8, _AVIVO_VGA_VSTATUS_CNTL_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
	str	w25, [sp, #4]                   ; 4-byte Folded Spill
	bic	w1, w25, w8
	bl	_WREG32
	ldr	x8, [sp, #8]                    ; 8-byte Folded Reload
	mov	x21, x8
	ldr	x8, [x8]
Lloh26:
	adrp	x20, _CHIP_RV730@GOTPAGE
Lloh27:
	ldr	x20, [x20, _CHIP_RV730@GOTPAGEOFF]
Lloh28:
	adrp	x24, _R600_CG_SPLL_FUNC_CNTL@GOTPAGE
Lloh29:
	ldr	x24, [x24, _R600_CG_SPLL_FUNC_CNTL@GOTPAGEOFF]
	ldr	x9, [x20]
Lloh30:
	adrp	x28, _R600_CG_SPLL_STATUS@GOTPAGE
Lloh31:
	ldr	x28, [x28, _R600_CG_SPLL_STATUS@GOTPAGEOFF]
Lloh32:
	adrp	x19, _R600_SPLL_CHG_STATUS@GOTPAGE
Lloh33:
	ldr	x19, [x19, _R600_SPLL_CHG_STATUS@GOTPAGEOFF]
	cmp	x8, x9
	b.ne	LBB0_4
; %bb.1:
	ldr	w25, [sp]                       ; 4-byte Folded Reload
Lloh34:
	adrp	x23, _R600_ROM_CNTL@GOTPAGE
Lloh35:
	ldr	x23, [x23, _R600_ROM_CNTL@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_RREG32
	mov	x27, x0
	ldr	w0, [x24]
Lloh36:
	adrp	x8, _R600_SPLL_BYPASS_EN@GOTPAGE
Lloh37:
	ldr	x8, [x8, _R600_SPLL_BYPASS_EN@GOTPAGEOFF]
Lloh38:
	ldr	w8, [x8]
	orr	w1, w8, w27
	bl	_WREG32
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x28]
	bl	_RREG32
	ldr	w8, [x19]
	tst	w8, w0
	b.eq	LBB0_2
; %bb.3:
	ldr	w0, [x23]
Lloh39:
	adrp	x8, _R600_SCK_OVERWRITE@GOTPAGE
Lloh40:
	ldr	x8, [x8, _R600_SCK_OVERWRITE@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
	bic	w1, w25, w8
	bl	_WREG32
	b	LBB0_5
LBB0_4:
Lloh42:
	adrp	x23, _R600_ROM_CNTL@GOTPAGE
Lloh43:
	ldr	x23, [x23, _R600_ROM_CNTL@GOTPAGEOFF]
	ldr	w0, [x23]
Lloh44:
	adrp	x8, _R600_SCK_OVERWRITE@GOTPAGE
Lloh45:
	ldr	x8, [x8, _R600_SCK_OVERWRITE@GOTPAGEOFF]
Lloh46:
	ldr	w8, [x8]
	ldr	w25, [sp]                       ; 4-byte Folded Reload
	orr	w1, w8, w25
	bl	_WREG32
	mov	w27, #0
LBB0_5:
	mov	x0, x21
	bl	_radeon_read_bios
	mov	x26, x0
	ldr	x8, [x21]
	ldr	x9, [x20]
	cmp	x8, x9
	b.ne	LBB0_8
; %bb.6:
	ldr	w0, [x24]
	mov	x1, x27
	bl	_WREG32
LBB0_7:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x28]
	bl	_RREG32
	ldr	w8, [x19]
	tst	w8, w0
	b.eq	LBB0_7
LBB0_8:
Lloh47:
	adrp	x8, _RADEON_VIPH_CONTROL@GOTPAGE
Lloh48:
	ldr	x8, [x8, _RADEON_VIPH_CONTROL@GOTPAGEOFF]
Lloh49:
	ldr	w0, [x8]
	ldr	w1, [sp, #28]                   ; 4-byte Folded Reload
	bl	_WREG32
Lloh50:
	adrp	x8, _R600_BUS_CNTL@GOTPAGE
Lloh51:
	ldr	x8, [x8, _R600_BUS_CNTL@GOTPAGEOFF]
Lloh52:
	ldr	w0, [x8]
	ldr	w1, [sp, #24]                   ; 4-byte Folded Reload
	bl	_WREG32
Lloh53:
	adrp	x8, _AVIVO_D1VGA_CONTROL@GOTPAGE
Lloh54:
	ldr	x8, [x8, _AVIVO_D1VGA_CONTROL@GOTPAGEOFF]
Lloh55:
	ldr	w0, [x8]
	mov	x1, x22
	bl	_WREG32
Lloh56:
	adrp	x8, _AVIVO_D2VGA_CONTROL@GOTPAGE
Lloh57:
	ldr	x8, [x8, _AVIVO_D2VGA_CONTROL@GOTPAGEOFF]
Lloh58:
	ldr	w0, [x8]
	ldr	w1, [sp, #20]                   ; 4-byte Folded Reload
	bl	_WREG32
Lloh59:
	adrp	x8, _AVIVO_VGA_RENDER_CONTROL@GOTPAGE
Lloh60:
	ldr	x8, [x8, _AVIVO_VGA_RENDER_CONTROL@GOTPAGEOFF]
Lloh61:
	ldr	w0, [x8]
	ldr	w1, [sp, #4]                    ; 4-byte Folded Reload
	bl	_WREG32
	ldr	w0, [x23]
	mov	x1, x25
	bl	_WREG32
	mov	x0, x26
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	ret
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_VIPH_CONTROL,4,2        ; @RADEON_VIPH_CONTROL
	.comm	_R600_BUS_CNTL,4,2              ; @R600_BUS_CNTL
	.comm	_AVIVO_D1VGA_CONTROL,4,2        ; @AVIVO_D1VGA_CONTROL
	.comm	_AVIVO_D2VGA_CONTROL,4,2        ; @AVIVO_D2VGA_CONTROL
	.comm	_AVIVO_VGA_RENDER_CONTROL,4,2   ; @AVIVO_VGA_RENDER_CONTROL
	.comm	_R600_ROM_CNTL,4,2              ; @R600_ROM_CNTL
	.comm	_RADEON_VIPH_EN,4,2             ; @RADEON_VIPH_EN
	.comm	_R600_BIOS_ROM_DIS,4,2          ; @R600_BIOS_ROM_DIS
	.comm	_AVIVO_DVGA_CONTROL_MODE_ENABLE,4,2 ; @AVIVO_DVGA_CONTROL_MODE_ENABLE
	.comm	_AVIVO_DVGA_CONTROL_TIMING_SELECT,4,2 ; @AVIVO_DVGA_CONTROL_TIMING_SELECT
	.comm	_AVIVO_VGA_VSTATUS_CNTL_MASK,4,2 ; @AVIVO_VGA_VSTATUS_CNTL_MASK
	.comm	_CHIP_RV730,8,3                 ; @CHIP_RV730
	.comm	_R600_CG_SPLL_FUNC_CNTL,4,2     ; @R600_CG_SPLL_FUNC_CNTL
	.comm	_R600_SPLL_BYPASS_EN,4,2        ; @R600_SPLL_BYPASS_EN
	.comm	_R600_SPLL_CHG_STATUS,4,2       ; @R600_SPLL_CHG_STATUS
	.comm	_R600_CG_SPLL_STATUS,4,2        ; @R600_CG_SPLL_STATUS
	.comm	_R600_SCK_OVERWRITE,4,2         ; @R600_SCK_OVERWRITE
	.no_dead_strip	_r700_read_disabled_bios
.subsections_via_symbols
