	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gmc_v6_0_mc_init
_gmc_v6_0_mc_init:                      ## @gmc_v6_0_mc_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	movq	_mmMC_ARB_RAMCFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_MC_ARB_RAMCFG__CHANSIZE_MASK@GOTPCREL(%rip), %rcx
	xorl	%edx, %edx
	movl	(%rcx), %ecx
	andl	%eax, %ecx
	setne	%dl
	shll	$5, %edx
	addl	$32, %edx
	testl	$2048, %eax                     ## imm = 0x800
	movl	$16, %r14d
	cmovel	%edx, %r14d
	movq	_mmMC_SHARED_CHMAP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_MC_SHARED_CHMAP__NOOFCHAN_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_MC_SHARED_CHMAP__NOOFCHAN__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	decl	%eax
	movl	$1, %ecx
	cmpl	$7, %eax
	ja	LBB0_2
## %bb.1:
	cltq
	leaq	l_switch.table.gmc_v6_0_mc_init(%rip), %rcx
	movl	(%rcx,%rax,4), %ecx
LBB0_2:
	imull	%r14d, %ecx
	movl	%ecx, 8(%rbx)
	movq	_mmCONFIG_MEMSIZE@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32
	shlq	$20, %rax
	movq	%rax, 16(%rbx)
	movl	(%r14), %edi
	callq	_RREG32
	shlq	$20, %rax
	movq	%rax, 24(%rbx)
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rbx)
	je	LBB0_3
LBB0_4:
	leaq	8(%rbx), %r14
	movl	56(%rbx), %edi
	xorl	%esi, %esi
	callq	_pci_resource_start
	movl	%eax, 48(%rbx)
	movl	56(%rbx), %edi
	xorl	%esi, %esi
	callq	_pci_resource_len
	movl	%eax, 40(%rbx)
	movl	%eax, 44(%rbx)
	movq	_amdgpu_gart_size@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	cmpl	$-1, %eax
	je	LBB0_5
## %bb.8:
	shll	$20, %eax
	cltq
	movq	%rax, 32(%rbx)
	jmp	LBB0_9
LBB0_3:
	movq	%rbx, %rdi
	callq	_amdgpu_device_resize_fb_bar
	testl	%eax, %eax
	jne	LBB0_10
	jmp	LBB0_4
LBB0_5:
	movl	4(%rbx), %eax
	andl	$-4, %eax
	cmpl	$128, %eax
	jne	LBB0_6
## %bb.7:
	movq	$1073741824, 32(%rbx)           ## imm = 0x40000000
	jmp	LBB0_9
LBB0_6:
	movq	$268435456, 32(%rbx)            ## imm = 0x10000000
LBB0_9:
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	_gmc_v6_0_vram_gtt_location
	xorl	%eax, %eax
LBB0_10:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_mmMC_ARB_RAMCFG,4,2            ## @mmMC_ARB_RAMCFG
	.comm	_MC_ARB_RAMCFG__CHANSIZE_MASK,4,2 ## @MC_ARB_RAMCFG__CHANSIZE_MASK
	.comm	_mmMC_SHARED_CHMAP,4,2          ## @mmMC_SHARED_CHMAP
	.comm	_MC_SHARED_CHMAP__NOOFCHAN_MASK,4,2 ## @MC_SHARED_CHMAP__NOOFCHAN_MASK
	.comm	_MC_SHARED_CHMAP__NOOFCHAN__SHIFT,4,2 ## @MC_SHARED_CHMAP__NOOFCHAN__SHIFT
	.comm	_mmCONFIG_MEMSIZE,4,2           ## @mmCONFIG_MEMSIZE
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_amdgpu_gart_size,4,2           ## @amdgpu_gart_size
	.no_dead_strip	_gmc_v6_0_mc_init
	.section	__TEXT,__const
	.p2align	2                               ## @switch.table.gmc_v6_0_mc_init
l_switch.table.gmc_v6_0_mc_init:
	.long	2                               ## 0x2
	.long	4                               ## 0x4
	.long	8                               ## 0x8
	.long	3                               ## 0x3
	.long	6                               ## 0x6
	.long	10                              ## 0xa
	.long	12                              ## 0xc
	.long	16                              ## 0x10

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gmc_v6_0_mc_init
_gmc_v6_0_mc_init:                      ; @gmc_v6_0_mc_init
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, _mmMC_ARB_RAMCFG@GOTPAGE
Lloh1:
	ldr	x8, [x8, _mmMC_ARB_RAMCFG@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_RREG32
Lloh3:
	adrp	x8, _MC_ARB_RAMCFG__CHANSIZE_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _MC_ARB_RAMCFG__CHANSIZE_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	tst	w8, w0
	mov	w8, #64
	mov	w9, #32
	csel	w8, w9, w8, eq
	tst	w0, #0x800
	mov	w9, #16
	csel	w20, w8, w9, eq
Lloh6:
	adrp	x8, _mmMC_SHARED_CHMAP@GOTPAGE
Lloh7:
	ldr	x8, [x8, _mmMC_SHARED_CHMAP@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	bl	_RREG32
Lloh9:
	adrp	x8, _MC_SHARED_CHMAP__NOOFCHAN_MASK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _MC_SHARED_CHMAP__NOOFCHAN_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh12:
	adrp	x9, _MC_SHARED_CHMAP__NOOFCHAN__SHIFT@GOTPAGE
Lloh13:
	ldr	x9, [x9, _MC_SHARED_CHMAP__NOOFCHAN__SHIFT@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	asr	w8, w8, w9
	sub	w8, w8, #1
	cmp	w8, #7
	b.hi	LBB0_2
; %bb.1:
Lloh15:
	adrp	x9, l_switch.table.gmc_v6_0_mc_init@PAGE
Lloh16:
	add	x9, x9, l_switch.table.gmc_v6_0_mc_init@PAGEOFF
	ldr	w8, [x9, w8, sxtw #2]
	b	LBB0_3
LBB0_2:
	mov	w8, #1
LBB0_3:
	mul	w8, w8, w20
	mov	x20, x19
	str	w8, [x20, #8]!
Lloh17:
	adrp	x21, _mmCONFIG_MEMSIZE@GOTPAGE
Lloh18:
	ldr	x21, [x21, _mmCONFIG_MEMSIZE@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
	lsl	x8, x0, #20
	str	x8, [x19, #16]
	ldr	w0, [x21]
	bl	_RREG32
	lsl	x8, x0, #20
	str	x8, [x19, #24]
	ldr	w8, [x19]
Lloh19:
	adrp	x9, _AMD_IS_APU@GOTPAGE
Lloh20:
	ldr	x9, [x9, _AMD_IS_APU@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_6
LBB0_4:
	ldr	w0, [x19, #56]
	mov	w1, #0
	bl	_pci_resource_start
	str	w0, [x19, #48]
	ldr	w0, [x19, #56]
	mov	w1, #0
	bl	_pci_resource_len
	stp	w0, w0, [x19, #40]
Lloh22:
	adrp	x8, _amdgpu_gart_size@GOTPAGE
Lloh23:
	ldr	x8, [x8, _amdgpu_gart_size@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	cmn	w8, #1
	b.eq	LBB0_7
; %bb.5:
	lsl	w8, w8, #20
	sxtw	x8, w8
	b	LBB0_10
LBB0_6:
	mov	x0, x19
	bl	_amdgpu_device_resize_fb_bar
	cbnz	w0, LBB0_11
	b	LBB0_4
LBB0_7:
	ldr	w8, [x19, #4]
	and	w8, w8, #0xfffffffc
	cmp	w8, #128
	b.ne	LBB0_9
; %bb.8:
	mov	w8, #1073741824
	b	LBB0_10
LBB0_9:
	mov	w8, #268435456
LBB0_10:
	str	x8, [x19, #32]
	mov	x0, x19
	mov	x1, x20
	bl	_gmc_v6_0_vram_gtt_location
	mov	w0, #0
LBB0_11:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.cfi_endproc
                                        ; -- End function
	.comm	_mmMC_ARB_RAMCFG,4,2            ; @mmMC_ARB_RAMCFG
	.comm	_MC_ARB_RAMCFG__CHANSIZE_MASK,4,2 ; @MC_ARB_RAMCFG__CHANSIZE_MASK
	.comm	_mmMC_SHARED_CHMAP,4,2          ; @mmMC_SHARED_CHMAP
	.comm	_MC_SHARED_CHMAP__NOOFCHAN_MASK,4,2 ; @MC_SHARED_CHMAP__NOOFCHAN_MASK
	.comm	_MC_SHARED_CHMAP__NOOFCHAN__SHIFT,4,2 ; @MC_SHARED_CHMAP__NOOFCHAN__SHIFT
	.comm	_mmCONFIG_MEMSIZE,4,2           ; @mmCONFIG_MEMSIZE
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_amdgpu_gart_size,4,2           ; @amdgpu_gart_size
	.no_dead_strip	_gmc_v6_0_mc_init
	.section	__TEXT,__const
	.p2align	2                               ; @switch.table.gmc_v6_0_mc_init
l_switch.table.gmc_v6_0_mc_init:
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	10                              ; 0xa
	.long	12                              ; 0xc
	.long	16                              ; 0x10

.subsections_via_symbols
