	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4                               ## -- Begin function gfx_v8_0_gpu_early_init
LCPI0_0:
	.long	1                               ## 0x1
	.long	2                               ## 0x2
	.long	3                               ## 0x3
	.long	1                               ## 0x1
LCPI0_1:
	.long	1                               ## 0x1
	.long	2                               ## 0x2
	.long	8                               ## 0x8
	.long	1                               ## 0x1
LCPI0_2:
	.long	4                               ## 0x4
	.long	8                               ## 0x8
	.long	8                               ## 0x8
	.long	1                               ## 0x1
LCPI0_3:
	.long	4                               ## 0x4
	.long	16                              ## 0x10
	.long	16                              ## 0x10
	.long	1                               ## 0x1
LCPI0_4:
	.long	1                               ## 0x1
	.long	2                               ## 0x2
	.long	6                               ## 0x6
	.long	1                               ## 0x1
LCPI0_5:
	.long	2                               ## 0x2
	.long	4                               ## 0x4
	.long	2                               ## 0x2
	.long	1                               ## 0x1
LCPI0_6:
	.long	8                               ## 0x8
	.long	32                              ## 0x20
	.long	256                             ## 0x100
	.long	48                              ## 0x30
LCPI0_7:
	.long	3                               ## 0x3
	.long	3                               ## 0x3
	.long	3                               ## 0x3
	.long	3                               ## 0x3
LCPI0_8:
	.long	4294967291                      ## 0xfffffffb
	.long	4294967291                      ## 0xfffffffb
	.long	4294967291                      ## 0xfffffffb
	.long	4294967291                      ## 0xfffffffb
LCPI0_9:
	.long	12                              ## 0xc
	.long	12                              ## 0xc
	.long	12                              ## 0xc
	.long	12                              ## 0xc
LCPI0_10:
	.long	11                              ## 0xb
	.long	11                              ## 0xb
	.long	11                              ## 0xb
	.long	11                              ## 0xb
LCPI0_11:
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
LCPI0_12:
	.long	2                               ## 0x2
	.long	32                              ## 0x20
	.long	1                               ## 0x1
	.long	64                              ## 0x40
LCPI0_13:
	.long	1                               ## 0x1
	.long	32                              ## 0x20
	.long	1                               ## 0x1
	.long	64                              ## 0x40
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	4, 0x90
_gfx_v8_0_gpu_early_init:               ## @gfx_v8_0_gpu_early_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movl	(%rdi), %eax
	addl	$-128, %eax
	cmpl	$8, %eax
	ja	LBB0_6
## %bb.1:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_2:
	movq	%rbx, %rdi
	callq	_amdgpu_atombios_get_gfx_info
	testl	%eax, %eax
	jne	LBB0_24
## %bb.3:
	movq	_TONGA_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %rax
	movl	$32, %ecx
	jmp	LBB0_15
LBB0_4:
	movq	%rbx, %rdi
	callq	_amdgpu_atombios_get_gfx_info
	testl	%eax, %eax
	jne	LBB0_24
## %bb.5:
	movq	_POLARIS11_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %rax
	movl	$32, %ecx
	jmp	LBB0_15
LBB0_6:
	movaps	LCPI0_5(%rip), %xmm0            ## xmm0 = [2,4,2,1]
	movups	%xmm0, 8(%rbx)
	movl	$2, 24(%rbx)
	movq	_TONGA_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %rax
	movl	$32, %ecx
	movl	$4, %edx
	jmp	LBB0_14
LBB0_7:
	movaps	LCPI0_4(%rip), %xmm0            ## xmm0 = [1,2,6,1]
	movups	%xmm0, 8(%rbx)
	movl	$2, 24(%rbx)
	movq	_TOPAZ_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %rax
	jmp	LBB0_12
LBB0_8:
	movaps	LCPI0_2(%rip), %xmm0            ## xmm0 = [4,8,8,1]
	movups	%xmm0, 8(%rbx)
	movl	$2, 24(%rbx)
	movq	_TONGA_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %rax
	movl	$32, %ecx
	movl	$8, %edx
	jmp	LBB0_14
LBB0_9:
	movl	$1, 24(%rbx)
	movaps	LCPI0_0(%rip), %xmm0            ## xmm0 = [1,2,3,1]
	movups	%xmm0, 8(%rbx)
	movq	_CARRIZO_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %rax
	movl	$16, %ecx
	jmp	LBB0_13
LBB0_10:
	movaps	LCPI0_3(%rip), %xmm0            ## xmm0 = [4,16,16,1]
	movups	%xmm0, 8(%rbx)
	movl	$4, 24(%rbx)
	movq	_TONGA_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %rax
	movl	$32, %ecx
	movl	$16, %edx
	jmp	LBB0_14
LBB0_11:
	movl	$2, 24(%rbx)
	movaps	LCPI0_1(%rip), %xmm0            ## xmm0 = [1,2,8,1]
	movups	%xmm0, 8(%rbx)
	movq	_CARRIZO_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %rax
LBB0_12:
	movl	$32, %ecx
LBB0_13:
	movl	$2, %edx
LBB0_14:
	movl	%edx, 28(%rbx)
LBB0_15:
	movl	$256, 32(%rbx)                  ## imm = 0x100
	movl	%ecx, 36(%rbx)
	movaps	LCPI0_6(%rip), %xmm0            ## xmm0 = [8,32,256,48]
	movups	%xmm0, 40(%rbx)
	movl	$304, 56(%rbx)                  ## imm = 0x130
	movl	(%rax), %r14d
	movq	_mmMC_SHARED_CHMAP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_mmMC_ARB_RAMCFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, 60(%rbx)
	movl	12(%rbx), %ecx
	movl	%ecx, 64(%rbx)
	movl	$256, 68(%rbx)                  ## imm = 0x100
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, 4(%rbx)
	je	LBB0_18
## %bb.16:
	movl	%r14d, -44(%rbp)                ## 4-byte Spill
	movq	_mmMC_FUS_DRAM0_BANK_ADDR_MAPPING@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	%rax, %r12
	movq	_MC_FUS_DRAM0_BANK_ADDR_MAPPING@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	_DIMM0ADDRMAP@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	movl	%r12d, %edi
	callq	_REG_GET_FIELD
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movl	(%r13), %esi
	movq	_DIMM1ADDRMAP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r12d, %edi
	callq	_REG_GET_FIELD
	movl	%eax, %r12d
	movq	_mmMC_FUS_DRAM1_BANK_ADDR_MAPPING@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	%rax, %r13
	movq	_MC_FUS_DRAM1_BANK_ADDR_MAPPING@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movl	(%r14), %edx
	movl	%r13d, %edi
	callq	_REG_GET_FIELD
	movl	%eax, %r14d
	movl	(%r15), %esi
	movq	_DIMM1ADDRMAP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r13d, %edi
	callq	_REG_GET_FIELD
	movd	-48(%rbp), %xmm0                ## 4-byte Folded Reload
                                        ## xmm0 = mem[0],zero,zero,zero
	pinsrd	$1, %r12d, %xmm0
	pinsrd	$2, %r14d, %xmm0
	pinsrd	$3, %eax, %xmm0
	movdqa	LCPI0_7(%rip), %xmm1            ## xmm1 = [3,3,3,3]
	pcmpeqd	%xmm0, %xmm1
	movdqa	LCPI0_8(%rip), %xmm2            ## xmm2 = [4294967291,4294967291,4294967291,4294967291]
	pand	%xmm0, %xmm2
	pxor	%xmm3, %xmm3
	pcmpeqd	%xmm2, %xmm3
	movdqa	%xmm0, %xmm2
	pcmpgtd	LCPI0_9(%rip), %xmm2
	por	%xmm1, %xmm2
	por	%xmm3, %xmm2
	pcmpeqd	LCPI0_10(%rip), %xmm0
	pxor	LCPI0_11(%rip), %xmm2
	pand	%xmm0, %xmm2
	pslld	$31, %xmm2
	movmskps	%xmm2, %eax
	testl	%eax, %eax
	je	LBB0_21
## %bb.17:
	movaps	LCPI0_12(%rip), %xmm0           ## xmm0 = [2,32,1,64]
	movups	%xmm0, 72(%rbx)
	movl	$1, %ecx
	jmp	LBB0_22
LBB0_18:
	movq	_MC_ARB_RAMCFG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_NOOFCOLS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	callq	_REG_GET_FIELD
                                        ## kill: def $eax killed $eax def $rax
	leal	8(%rax), %ecx
	movl	$4, %eax
	movl	$4, %edx
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %edx
	cmpl	$5119, %edx                     ## imm = 0x13FF
	jg	LBB0_20
## %bb.19:
	leal	1023(%rdx), %eax
	testl	%edx, %edx
	cmovnsl	%edx, %eax
	sarl	$10, %eax
LBB0_20:
	movl	%eax, 72(%rbx)
	movabsq	$4294967328, %rcx               ## imm = 0x100000020
	movq	%rcx, 76(%rbx)
	movl	$64, 84(%rbx)
	xorl	%edx, %edx
	cmpl	$2, %eax
	sete	%dl
	cmpl	$4, %eax
	movl	$2, %ecx
	cmovnel	%edx, %ecx
	jmp	LBB0_23
LBB0_21:
	movaps	LCPI0_13(%rip), %xmm0           ## xmm0 = [1,32,1,64]
	movups	%xmm0, 72(%rbx)
	xorl	%ecx, %ecx
LBB0_22:
	movl	-44(%rbp), %r14d                ## 4-byte Reload
LBB0_23:
	movq	_GB_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_ROW_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r14d, %edi
	callq	_REG_SET_FIELD
	movl	%eax, 88(%rbx)
	xorl	%eax, %eax
LBB0_24:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_2, LBB0_2-LJTI0_0
.set L0_0_set_7, LBB0_7-LJTI0_0
.set L0_0_set_8, LBB0_8-LJTI0_0
.set L0_0_set_9, LBB0_9-LJTI0_0
.set L0_0_set_4, LBB0_4-LJTI0_0
.set L0_0_set_10, LBB0_10-LJTI0_0
.set L0_0_set_11, LBB0_11-LJTI0_0
LJTI0_0:
	.long	L0_0_set_2
	.long	L0_0_set_7
	.long	L0_0_set_8
	.long	L0_0_set_9
	.long	L0_0_set_4
	.long	L0_0_set_4
	.long	L0_0_set_2
	.long	L0_0_set_10
	.long	L0_0_set_11
	.end_data_region
                                        ## -- End function
	.comm	_TOPAZ_GB_ADDR_CONFIG_GOLDEN,4,2 ## @TOPAZ_GB_ADDR_CONFIG_GOLDEN
	.comm	_TONGA_GB_ADDR_CONFIG_GOLDEN,4,2 ## @TONGA_GB_ADDR_CONFIG_GOLDEN
	.comm	_POLARIS11_GB_ADDR_CONFIG_GOLDEN,4,2 ## @POLARIS11_GB_ADDR_CONFIG_GOLDEN
	.comm	_CARRIZO_GB_ADDR_CONFIG_GOLDEN,4,2 ## @CARRIZO_GB_ADDR_CONFIG_GOLDEN
	.comm	_mmMC_SHARED_CHMAP,4,2          ## @mmMC_SHARED_CHMAP
	.comm	_mmMC_ARB_RAMCFG,4,2            ## @mmMC_ARB_RAMCFG
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_mmMC_FUS_DRAM0_BANK_ADDR_MAPPING,4,2 ## @mmMC_FUS_DRAM0_BANK_ADDR_MAPPING
	.comm	_MC_FUS_DRAM0_BANK_ADDR_MAPPING,4,2 ## @MC_FUS_DRAM0_BANK_ADDR_MAPPING
	.comm	_DIMM0ADDRMAP,4,2               ## @DIMM0ADDRMAP
	.comm	_DIMM1ADDRMAP,4,2               ## @DIMM1ADDRMAP
	.comm	_mmMC_FUS_DRAM1_BANK_ADDR_MAPPING,4,2 ## @mmMC_FUS_DRAM1_BANK_ADDR_MAPPING
	.comm	_MC_FUS_DRAM1_BANK_ADDR_MAPPING,4,2 ## @MC_FUS_DRAM1_BANK_ADDR_MAPPING
	.comm	_MC_ARB_RAMCFG,4,2              ## @MC_ARB_RAMCFG
	.comm	_NOOFCOLS,4,2                   ## @NOOFCOLS
	.comm	_GB_ADDR_CONFIG,4,2             ## @GB_ADDR_CONFIG
	.comm	_ROW_SIZE,4,2                   ## @ROW_SIZE
	.no_dead_strip	_gfx_v8_0_gpu_early_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4                               ; -- Begin function gfx_v8_0_gpu_early_init
lCPI0_0:
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	1                               ; 0x1
lCPI0_1:
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	8                               ; 0x8
	.long	1                               ; 0x1
lCPI0_2:
	.long	4                               ; 0x4
	.long	8                               ; 0x8
	.long	8                               ; 0x8
	.long	1                               ; 0x1
lCPI0_3:
	.long	4                               ; 0x4
	.long	16                              ; 0x10
	.long	16                              ; 0x10
	.long	1                               ; 0x1
lCPI0_4:
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	6                               ; 0x6
	.long	1                               ; 0x1
lCPI0_5:
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	1                               ; 0x1
lCPI0_6:
	.long	8                               ; 0x8
	.long	32                              ; 0x20
	.long	256                             ; 0x100
	.long	48                              ; 0x30
lCPI0_7:
	.long	2                               ; 0x2
	.long	32                              ; 0x20
	.long	1                               ; 0x1
	.long	64                              ; 0x40
lCPI0_8:
	.long	1                               ; 0x1
	.long	32                              ; 0x20
	.long	1                               ; 0x1
	.long	64                              ; 0x40
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3
lCPI0_9:
	.long	32                              ; 0x20
	.long	1                               ; 0x1
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	2
_gfx_v8_0_gpu_early_init:               ; @gfx_v8_0_gpu_early_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldr	w8, [x0]
	sub	w8, w8, #128
	cmp	w8, #8
	b.hi	LBB0_6
; %bb.1:
Lloh0:
	adrp	x9, lJTI0_0@PAGE
Lloh1:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_2
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_2:
	mov	x0, x19
	bl	_amdgpu_atombios_get_gfx_info
	cbnz	w0, LBB0_20
; %bb.3:
Lloh2:
	adrp	x8, _TONGA_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh3:
	ldr	x8, [x8, _TONGA_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
	mov	w9, #32
	b	LBB0_14
LBB0_4:
	mov	x0, x19
	bl	_amdgpu_atombios_get_gfx_info
	cbnz	w0, LBB0_20
; %bb.5:
Lloh4:
	adrp	x8, _POLARIS11_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh5:
	ldr	x8, [x8, _POLARIS11_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
	mov	w9, #32
	b	LBB0_14
LBB0_6:
Lloh6:
	adrp	x8, lCPI0_5@PAGE
Lloh7:
	ldr	q0, [x8, lCPI0_5@PAGEOFF]
	stur	q0, [x19, #8]
	mov	w8, #2
	str	w8, [x19, #24]
Lloh8:
	adrp	x8, _TONGA_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh9:
	ldr	x8, [x8, _TONGA_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
	mov	w9, #32
	mov	w10, #4
	b	LBB0_13
LBB0_7:
Lloh10:
	adrp	x8, lCPI0_4@PAGE
Lloh11:
	ldr	q0, [x8, lCPI0_4@PAGEOFF]
	stur	q0, [x19, #8]
	mov	w10, #2
	str	w10, [x19, #24]
Lloh12:
	adrp	x8, _TOPAZ_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh13:
	ldr	x8, [x8, _TOPAZ_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
	b	LBB0_12
LBB0_8:
Lloh14:
	adrp	x8, lCPI0_2@PAGE
Lloh15:
	ldr	q0, [x8, lCPI0_2@PAGEOFF]
	stur	q0, [x19, #8]
	mov	w8, #2
	str	w8, [x19, #24]
Lloh16:
	adrp	x8, _TONGA_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh17:
	ldr	x8, [x8, _TONGA_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
	mov	w9, #32
	mov	w10, #8
	b	LBB0_13
LBB0_9:
	mov	w8, #1
	str	w8, [x19, #24]
Lloh18:
	adrp	x8, lCPI0_0@PAGE
Lloh19:
	ldr	q0, [x8, lCPI0_0@PAGEOFF]
	stur	q0, [x19, #8]
Lloh20:
	adrp	x8, _CARRIZO_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh21:
	ldr	x8, [x8, _CARRIZO_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
	mov	w9, #16
	mov	w10, #2
	b	LBB0_13
LBB0_10:
Lloh22:
	adrp	x8, lCPI0_3@PAGE
Lloh23:
	ldr	q0, [x8, lCPI0_3@PAGEOFF]
	stur	q0, [x19, #8]
	mov	w8, #4
	str	w8, [x19, #24]
Lloh24:
	adrp	x8, _TONGA_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh25:
	ldr	x8, [x8, _TONGA_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
	mov	w9, #32
	mov	w10, #16
	b	LBB0_13
LBB0_11:
	mov	w10, #2
	str	w10, [x19, #24]
Lloh26:
	adrp	x8, lCPI0_1@PAGE
Lloh27:
	ldr	q0, [x8, lCPI0_1@PAGEOFF]
	stur	q0, [x19, #8]
Lloh28:
	adrp	x8, _CARRIZO_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh29:
	ldr	x8, [x8, _CARRIZO_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
LBB0_12:
	mov	w9, #32
LBB0_13:
	str	w10, [x19, #28]
LBB0_14:
	mov	w21, #256
	stp	w21, w9, [x19, #32]
Lloh30:
	adrp	x9, lCPI0_6@PAGE
Lloh31:
	ldr	q0, [x9, lCPI0_6@PAGEOFF]
	stur	q0, [x19, #40]
	mov	w9, #304
	str	w9, [x19, #56]
	ldr	w20, [x8]
Lloh32:
	adrp	x8, _mmMC_SHARED_CHMAP@GOTPAGE
Lloh33:
	ldr	x8, [x8, _mmMC_SHARED_CHMAP@GOTPAGEOFF]
Lloh34:
	ldr	w0, [x8]
	bl	_RREG32
Lloh35:
	adrp	x8, _mmMC_ARB_RAMCFG@GOTPAGE
Lloh36:
	ldr	x8, [x8, _mmMC_ARB_RAMCFG@GOTPAGEOFF]
Lloh37:
	ldr	w0, [x8]
	bl	_RREG32
	ldr	w8, [x19, #12]
	stp	w0, w8, [x19, #60]
	str	w21, [x19, #68]
	ldr	w8, [x19, #4]
Lloh38:
	adrp	x9, _AMD_IS_APU@GOTPAGE
Lloh39:
	ldr	x9, [x9, _AMD_IS_APU@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_17
; %bb.15:
Lloh41:
	adrp	x8, _mmMC_FUS_DRAM0_BANK_ADDR_MAPPING@GOTPAGE
Lloh42:
	ldr	x8, [x8, _mmMC_FUS_DRAM0_BANK_ADDR_MAPPING@GOTPAGEOFF]
Lloh43:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x21, x0
Lloh44:
	adrp	x23, _MC_FUS_DRAM0_BANK_ADDR_MAPPING@GOTPAGE
Lloh45:
	ldr	x23, [x23, _MC_FUS_DRAM0_BANK_ADDR_MAPPING@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh46:
	adrp	x24, _DIMM0ADDRMAP@GOTPAGE
Lloh47:
	ldr	x24, [x24, _DIMM0ADDRMAP@GOTPAGEOFF]
	ldr	w2, [x24]
	bl	_REG_GET_FIELD
	mov	x22, x0
	ldr	w1, [x23]
Lloh48:
	adrp	x25, _DIMM1ADDRMAP@GOTPAGE
Lloh49:
	ldr	x25, [x25, _DIMM1ADDRMAP@GOTPAGEOFF]
	ldr	w2, [x25]
	mov	x0, x21
	bl	_REG_GET_FIELD
	mov	x21, x0
Lloh50:
	adrp	x8, _mmMC_FUS_DRAM1_BANK_ADDR_MAPPING@GOTPAGE
Lloh51:
	ldr	x8, [x8, _mmMC_FUS_DRAM1_BANK_ADDR_MAPPING@GOTPAGEOFF]
Lloh52:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x23, x0
Lloh53:
	adrp	x26, _MC_FUS_DRAM1_BANK_ADDR_MAPPING@GOTPAGE
Lloh54:
	ldr	x26, [x26, _MC_FUS_DRAM1_BANK_ADDR_MAPPING@GOTPAGEOFF]
	ldr	w1, [x26]
	ldr	w2, [x24]
	bl	_REG_GET_FIELD
	mov	x24, x0
	ldr	w1, [x26]
	ldr	w2, [x25]
	mov	x0, x23
	bl	_REG_GET_FIELD
	fmov	s0, w22
	mov.s	v0[1], w21
	mov.s	v0[2], w24
	mov.s	v0[3], w0
	movi.4s	v1, #3
	cmeq.4s	v1, v0, v1
	movi.4s	v2, #12
	cmgt.4s	v2, v0, v2
	movi.4s	v3, #11
	cmeq.4s	v3, v0, v3
	bic.4s	v0, #4
	cmeq.4s	v0, v0, #0
	orr.16b	v0, v1, v0
	orr.16b	v0, v2, v0
	xtn.4h	v0, v0
	xtn.4h	v1, v3
	movi.4h	v2, #1
	eor.8b	v0, v0, v2
	and.8b	v0, v0, v1
	umov.h	w8, v0[0]
	umov.h	w9, v0[1]
	and	w9, w9, #0x1
	bfi	w8, w9, #1, #1
	umov.h	w9, v0[2]
	and	w9, w9, #0x1
	bfi	w8, w9, #2, #1
	umov.h	w9, v0[3]
	bfi	w8, w9, #3, #29
	tst	w8, #0xf
	b.eq	LBB0_18
; %bb.16:
Lloh55:
	adrp	x8, lCPI0_7@PAGE
Lloh56:
	ldr	q0, [x8, lCPI0_7@PAGEOFF]
	stur	q0, [x19, #72]
	mov	w3, #1
	b	LBB0_19
LBB0_17:
Lloh57:
	adrp	x8, _MC_ARB_RAMCFG@GOTPAGE
Lloh58:
	ldr	x8, [x8, _MC_ARB_RAMCFG@GOTPAGEOFF]
Lloh59:
	ldr	w1, [x8]
Lloh60:
	adrp	x8, _NOOFCOLS@GOTPAGE
Lloh61:
	ldr	x8, [x8, _NOOFCOLS@GOTPAGEOFF]
Lloh62:
	ldr	w2, [x8]
                                        ; kill: def $w0 killed $w0 killed $x0
	bl	_REG_GET_FIELD
	add	w8, w0, #8
	mov	w9, #4
	lsl	w8, w9, w8
	add	w10, w8, #1023
	cmp	w8, #0
	csel	w10, w10, w8, lt
	asr	w10, w10, #10
	mov	w11, #5119
	cmp	w8, w11
	csel	w8, w9, w10, gt
	str	w8, [x19, #72]
Lloh63:
	adrp	x9, lCPI0_9@PAGE
Lloh64:
	ldr	d0, [x9, lCPI0_9@PAGEOFF]
	stur	d0, [x19, #76]
	mov	w9, #64
	str	w9, [x19, #84]
	cmp	w8, #2
	cset	w9, eq
	mov	w10, #2
	cmp	w8, #4
	csel	w3, w10, w9, eq
	b	LBB0_19
LBB0_18:
	mov	w3, #0
Lloh65:
	adrp	x8, lCPI0_8@PAGE
Lloh66:
	ldr	q0, [x8, lCPI0_8@PAGEOFF]
	stur	q0, [x19, #72]
LBB0_19:
Lloh67:
	adrp	x8, _GB_ADDR_CONFIG@GOTPAGE
Lloh68:
	ldr	x8, [x8, _GB_ADDR_CONFIG@GOTPAGEOFF]
Lloh69:
	ldr	w1, [x8]
Lloh70:
	adrp	x8, _ROW_SIZE@GOTPAGE
Lloh71:
	ldr	x8, [x8, _ROW_SIZE@GOTPAGEOFF]
Lloh72:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_REG_SET_FIELD
	mov	x8, x0
	mov	w0, #0
	str	w8, [x19, #88]
LBB0_20:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdr	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpAdrp	Lloh10, Lloh12
	.loh AdrpLdr	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdr	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpAdrp	Lloh18, Lloh20
	.loh AdrpLdr	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdr	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpAdrp	Lloh26, Lloh28
	.loh AdrpLdr	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdr	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGot	Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdr	Lloh55, Lloh56
	.loh AdrpLdr	Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdr	Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_7-LBB0_2)>>2
	.byte	(LBB0_8-LBB0_2)>>2
	.byte	(LBB0_9-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_10-LBB0_2)>>2
	.byte	(LBB0_11-LBB0_2)>>2
                                        ; -- End function
	.comm	_TOPAZ_GB_ADDR_CONFIG_GOLDEN,4,2 ; @TOPAZ_GB_ADDR_CONFIG_GOLDEN
	.comm	_TONGA_GB_ADDR_CONFIG_GOLDEN,4,2 ; @TONGA_GB_ADDR_CONFIG_GOLDEN
	.comm	_POLARIS11_GB_ADDR_CONFIG_GOLDEN,4,2 ; @POLARIS11_GB_ADDR_CONFIG_GOLDEN
	.comm	_CARRIZO_GB_ADDR_CONFIG_GOLDEN,4,2 ; @CARRIZO_GB_ADDR_CONFIG_GOLDEN
	.comm	_mmMC_SHARED_CHMAP,4,2          ; @mmMC_SHARED_CHMAP
	.comm	_mmMC_ARB_RAMCFG,4,2            ; @mmMC_ARB_RAMCFG
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_mmMC_FUS_DRAM0_BANK_ADDR_MAPPING,4,2 ; @mmMC_FUS_DRAM0_BANK_ADDR_MAPPING
	.comm	_MC_FUS_DRAM0_BANK_ADDR_MAPPING,4,2 ; @MC_FUS_DRAM0_BANK_ADDR_MAPPING
	.comm	_DIMM0ADDRMAP,4,2               ; @DIMM0ADDRMAP
	.comm	_DIMM1ADDRMAP,4,2               ; @DIMM1ADDRMAP
	.comm	_mmMC_FUS_DRAM1_BANK_ADDR_MAPPING,4,2 ; @mmMC_FUS_DRAM1_BANK_ADDR_MAPPING
	.comm	_MC_FUS_DRAM1_BANK_ADDR_MAPPING,4,2 ; @MC_FUS_DRAM1_BANK_ADDR_MAPPING
	.comm	_MC_ARB_RAMCFG,4,2              ; @MC_ARB_RAMCFG
	.comm	_NOOFCOLS,4,2                   ; @NOOFCOLS
	.comm	_GB_ADDR_CONFIG,4,2             ; @GB_ADDR_CONFIG
	.comm	_ROW_SIZE,4,2                   ; @ROW_SIZE
	.no_dead_strip	_gfx_v8_0_gpu_early_init
.subsections_via_symbols
