	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function cdv_intel_channel_eq_ok
_cdv_intel_channel_eq_ok:               ## @cdv_intel_channel_eq_ok
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	(%rdi), %r15
	movl	4(%r15), %edi
	movq	_DP_LANE_ALIGN_STATUS_UPDATED@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_cdv_intel_dp_link_status
	movq	_DP_INTERLANE_ALIGN_DONE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_5
## %bb.1:
	movl	$1, %r14d
	cmpl	$0, (%r15)
	jle	LBB0_6
## %bb.2:
	movq	_CHANNEL_EQ_BITS@GOTPCREL(%rip), %r12
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movl	4(%r15), %edi
	movl	%ebx, %esi
	callq	_cdv_intel_get_lane_status
	notl	%eax
	testl	%eax, (%r12)
	jne	LBB0_5
## %bb.3:                               ##   in Loop: Header=BB0_4 Depth=1
	incl	%ebx
	cmpl	(%r15), %ebx
	jl	LBB0_4
	jmp	LBB0_6
LBB0_5:
	xorl	%r14d, %r14d
LBB0_6:
	movl	%r14d, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DP_LANE_ALIGN_STATUS_UPDATED,4,2 ## @DP_LANE_ALIGN_STATUS_UPDATED
	.comm	_DP_INTERLANE_ALIGN_DONE,4,2    ## @DP_INTERLANE_ALIGN_DONE
	.comm	_CHANNEL_EQ_BITS,4,2            ## @CHANNEL_EQ_BITS
	.no_dead_strip	_cdv_intel_channel_eq_ok
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cdv_intel_channel_eq_ok
_cdv_intel_channel_eq_ok:               ; @cdv_intel_channel_eq_ok
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	ldr	x20, [x0]
	ldr	w0, [x20, #4]
Lloh0:
	adrp	x8, _DP_LANE_ALIGN_STATUS_UPDATED@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DP_LANE_ALIGN_STATUS_UPDATED@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	bl	_cdv_intel_dp_link_status
Lloh3:
	adrp	x8, _DP_INTERLANE_ALIGN_DONE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _DP_INTERLANE_ALIGN_DONE@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_6
; %bb.1:
	ldr	w8, [x20]
	cmp	w8, #1
	b.lt	LBB0_5
; %bb.2:
	mov	w19, #0
Lloh6:
	adrp	x21, _CHANNEL_EQ_BITS@GOTPAGE
Lloh7:
	ldr	x21, [x21, _CHANNEL_EQ_BITS@GOTPAGEOFF]
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x20, #4]
	mov	x1, x19
	bl	_cdv_intel_get_lane_status
	ldr	w8, [x21]
	bics	wzr, w8, w0
	b.ne	LBB0_6
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	add	w19, w19, #1
	ldr	w8, [x20]
	cmp	w19, w8
	b.lt	LBB0_3
LBB0_5:
	mov	w0, #1
	b	LBB0_7
LBB0_6:
	mov	w0, #0
LBB0_7:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh6, Lloh7
	.cfi_endproc
                                        ; -- End function
	.comm	_DP_LANE_ALIGN_STATUS_UPDATED,4,2 ; @DP_LANE_ALIGN_STATUS_UPDATED
	.comm	_DP_INTERLANE_ALIGN_DONE,4,2    ; @DP_INTERLANE_ALIGN_DONE
	.comm	_CHANNEL_EQ_BITS,4,2            ; @CHANNEL_EQ_BITS
	.no_dead_strip	_cdv_intel_channel_eq_ok
.subsections_via_symbols
