	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_gen11_enable_guc_interrupts    ## -- Begin function gen11_enable_guc_interrupts
	.p2align	4, 0x90
_gen11_enable_guc_interrupts:           ## @gen11_enable_guc_interrupts
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	callq	_guc_to_gt
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	_spin_lock_irq
	cmpl	$0, (%r14)
	jne	LBB0_2
## %bb.1:
	movq	_ENGINE1_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_GUC_INTR_GUC2HOST@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_REG_FIELD_PREP
	movl	%eax, %r15d
	movq	_GEN11_GUC@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_gen11_gt_reset_one_iir
	movl	%eax, %edi
	callq	_WARN_ON_ONCE
	movl	4(%rbx), %edi
	movq	_GEN11_GUC_SG_INTR_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r15d, %edx
	callq	_intel_uncore_write
	movl	4(%rbx), %edi
	movq	_GEN11_GUC_SG_INTR_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%r15d
	movl	%r15d, %edx
	callq	_intel_uncore_write
	movl	$1, (%r14)
LBB0_2:
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_spin_unlock_irq                ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_ENGINE1_MASK,4,2               ## @ENGINE1_MASK
	.comm	_GUC_INTR_GUC2HOST,4,2          ## @GUC_INTR_GUC2HOST
	.comm	_GEN11_GUC,4,2                  ## @GEN11_GUC
	.comm	_GEN11_GUC_SG_INTR_ENABLE,4,2   ## @GEN11_GUC_SG_INTR_ENABLE
	.comm	_GEN11_GUC_SG_INTR_MASK,4,2     ## @GEN11_GUC_SG_INTR_MASK
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_gen11_enable_guc_interrupts    ; -- Begin function gen11_enable_guc_interrupts
	.p2align	2
_gen11_enable_guc_interrupts:           ; @gen11_enable_guc_interrupts
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	bl	_guc_to_gt
	mov	x20, x0
	bl	_spin_lock_irq
	ldr	w8, [x19]
	cbnz	w8, LBB0_2
; %bb.1:
Lloh0:
	adrp	x8, _ENGINE1_MASK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _ENGINE1_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
Lloh3:
	adrp	x8, _GUC_INTR_GUC2HOST@GOTPAGE
Lloh4:
	ldr	x8, [x8, _GUC_INTR_GUC2HOST@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	bl	_REG_FIELD_PREP
	mov	x21, x0
Lloh6:
	adrp	x8, _GEN11_GUC@GOTPAGE
Lloh7:
	ldr	x8, [x8, _GEN11_GUC@GOTPAGEOFF]
Lloh8:
	ldr	w2, [x8]
	mov	x0, x20
	mov	w1, #0
	bl	_gen11_gt_reset_one_iir
	bl	_WARN_ON_ONCE
	ldr	w0, [x20, #4]
Lloh9:
	adrp	x8, _GEN11_GUC_SG_INTR_ENABLE@GOTPAGE
Lloh10:
	ldr	x8, [x8, _GEN11_GUC_SG_INTR_ENABLE@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x2, x21
	bl	_intel_uncore_write
	ldr	w0, [x20, #4]
Lloh12:
	adrp	x8, _GEN11_GUC_SG_INTR_MASK@GOTPAGE
Lloh13:
	ldr	x8, [x8, _GEN11_GUC_SG_INTR_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mvn	w2, w21
	bl	_intel_uncore_write
	mov	w8, #1
	str	w8, [x19]
LBB0_2:
	mov	x0, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_spin_unlock_irq
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_ENGINE1_MASK,4,2               ; @ENGINE1_MASK
	.comm	_GUC_INTR_GUC2HOST,4,2          ; @GUC_INTR_GUC2HOST
	.comm	_GEN11_GUC,4,2                  ; @GEN11_GUC
	.comm	_GEN11_GUC_SG_INTR_ENABLE,4,2   ; @GEN11_GUC_SG_INTR_ENABLE
	.comm	_GEN11_GUC_SG_INTR_MASK,4,2     ; @GEN11_GUC_SG_INTR_MASK
.subsections_via_symbols
