	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_meson_viu_init                 ## -- Begin function meson_viu_init
	.p2align	4, 0x90
_meson_viu_init:                        ## @meson_viu_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_VIU_OSD1_OSD_BLK_ENABLE@GOTPCREL(%rip), %r12
	movq	_VIU_OSD1_OSD_ENABLE@GOTPCREL(%rip), %r13
	movl	(%r13), %r15d
	orl	(%r12), %r15d
	movq	%rdi, %r14
	movq	16(%rdi), %rbx
	movq	_VIU_OSD1_CTRL_STAT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r15d, %edi
	xorl	%esi, %esi
	movq	%rbx, %rdx
	callq	_writel_bits_relaxed
	movl	(%r13), %r15d
	orl	(%r12), %r15d
	movq	16(%r14), %rbx
	movq	_VIU_OSD2_CTRL_STAT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r15d, %edi
	xorl	%esi, %esi
	movq	%rbx, %rdx
	callq	_writel_bits_relaxed
	movq	_VPU_COMPATIBLE_GXM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	jne	LBB0_2
## %bb.1:
	movq	_VPU_COMPATIBLE_GXL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_3
LBB0_2:
	movq	%r14, %rdi
	callq	_meson_viu_load_matrix
LBB0_5:
	movq	_VIU_OSD_DDR_PRIORITY_URGENT@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	$4, %edi
	callq	_VIU_OSD_HOLD_FIFO_LINES
	movl	%eax, %ebx
	movl	$32, %edi
	callq	_VIU_OSD_FIFO_DEPTH_VAL
	orl	%eax, %ebx
	movl	$4, %edi
	callq	_VIU_OSD_WORDS_PER_BURST
	orl	%eax, %ebx
	movl	$2, %edi
	callq	_VIU_OSD_FIFO_LIMITS
	orl	%eax, %ebx
	orl	%r15d, %ebx
	movq	_VPU_COMPATIBLE_G12A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	xorl	%edi, %edi
	testq	%rax, %rax
	sete	%dil
	shll	$5, %edi
	addl	$32, %edi
	callq	_meson_viu_osd_burst_length_reg
	orl	%eax, %ebx
	movq	16(%r14), %r15
	movq	_VIU_OSD1_FIFO_CTRL_STAT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %r15
	movl	%ebx, %edi
	movq	%r15, %rsi
	callq	_writel_relaxed
	movq	16(%r14), %r15
	movq	_VIU_OSD2_FIFO_CTRL_STAT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %r15
	movl	%ebx, %edi
	movq	%r15, %rsi
	callq	_writel_relaxed
	movq	_OSD_REPLACE_SHIFT@GOTPCREL(%rip), %r13
	movb	(%r13), %cl
	movl	$255, %ebx
	shll	%cl, %ebx
	movl	$255, %r15d
	movq	16(%r14), %r12
	movq	_VIU_OSD1_CTRL_STAT2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %r12
	movl	%ebx, %edi
	movl	%ebx, %esi
	movq	%r12, %rdx
	callq	_writel_bits_relaxed
	movb	(%r13), %cl
	shll	%cl, %r15d
	movq	16(%r14), %rbx
	movq	_VIU_OSD2_CTRL_STAT2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r15d, %edi
	movl	%r15d, %esi
	movq	%rbx, %rdx
	callq	_writel_bits_relaxed
	movq	_VIU_CTRL0_VD1_AFBC_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	16(%r14), %rbx
	movq	_VIU_MISC_CTRL0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r15d, %edi
	xorl	%esi, %esi
	movq	%rbx, %rdx
	callq	_writel_bits_relaxed
	movq	16(%r14), %rbx
	movq	_AFBC_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	xorl	%edi, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	16(%r14), %rbx
	movq	_VD1_IF0_LUMA_FIFO_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	$16711872, %edi                 ## imm = 0xFF00C0
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	16(%r14), %rbx
	movq	_VD2_IF0_LUMA_FIFO_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	$16711872, %edi                 ## imm = 0xFF00C0
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	_VPU_COMPATIBLE_G12A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_7
## %bb.6:
	xorl	%edi, %edi
	movl	$1, %esi
	callq	_VIU_OSD_BLEND_REORDER
	movl	%eax, %r15d
	movl	$1, %edi
	xorl	%esi, %esi
	callq	_VIU_OSD_BLEND_REORDER
	orl	%eax, %r15d
	movl	$2, %edi
	xorl	%esi, %esi
	callq	_VIU_OSD_BLEND_REORDER
	movl	%eax, %ebx
	movl	$3, %edi
	xorl	%esi, %esi
	callq	_VIU_OSD_BLEND_REORDER
	orl	%eax, %ebx
	orl	%r15d, %ebx
	movl	$1, %edi
	callq	_VIU_OSD_BLEND_DIN_EN
	orl	%eax, %ebx
	movq	_VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	$1, %edi
	callq	_VIU_OSD_BLEND_BLEN2_PREMULT_EN
	movl	%eax, %r15d
	movl	$4, %edi
	callq	_VIU_OSD_BLEND_HOLD_LINES
	orl	%eax, %r15d
	orl	%ebx, %r15d
	movq	16(%r14), %rbx
	movq	_VIU_OSD_BLEND_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r15d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	_OSD_BLEND_PATH_SEL_ENABLE@GOTPCREL(%rip), %r12
	movl	(%r12), %r15d
	movq	16(%r14), %rbx
	movq	_OSD1_BLEND_SRC_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r15d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	(%r12), %r15d
	movq	16(%r14), %rbx
	movq	_OSD2_BLEND_SRC_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r15d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	16(%r14), %rbx
	movq	_VD1_BLEND_SRC_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	xorl	%edi, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	16(%r14), %rbx
	movq	_VD2_BLEND_SRC_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	xorl	%edi, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	16(%r14), %rbx
	movq	_VIU_OSD_BLEND_DUMMY_DATA0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	xorl	%edi, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	16(%r14), %rbx
	movq	_VIU_OSD_BLEND_DUMMY_ALPHA@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	xorl	%edi, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	$12, %edi
	callq	_DOLBY_BYPASS_EN
	movl	%eax, %r15d
	movl	$12, %edi
	callq	_DOLBY_BYPASS_EN
	movl	%eax, %r12d
	movq	16(%r14), %rbx
	movq	_DOLBY_PATH_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r15d, %edi
	movl	%r12d, %esi
	movq	%rbx, %rdx
	callq	_writel_bits_relaxed
LBB0_7:
	movq	$0, (%r14)
	movl	$0, 8(%r14)
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_3:
	movq	_VPU_COMPATIBLE_G12A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	movq	_RGB709_to_YUV709l_coeff@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$1, %edx
	callq	_meson_viu_set_g12a_osd1_matrix
	jmp	LBB0_5
	.cfi_endproc
                                        ## -- End function
	.comm	_VIU_OSD1_OSD_BLK_ENABLE,4,2    ## @VIU_OSD1_OSD_BLK_ENABLE
	.comm	_VIU_OSD1_OSD_ENABLE,4,2        ## @VIU_OSD1_OSD_ENABLE
	.comm	_VIU_OSD1_CTRL_STAT,4,2         ## @VIU_OSD1_CTRL_STAT
	.comm	_VIU_OSD2_CTRL_STAT,4,2         ## @VIU_OSD2_CTRL_STAT
	.comm	_VPU_COMPATIBLE_GXM,4,2         ## @VPU_COMPATIBLE_GXM
	.comm	_VPU_COMPATIBLE_GXL,4,2         ## @VPU_COMPATIBLE_GXL
	.comm	_VPU_COMPATIBLE_G12A,4,2        ## @VPU_COMPATIBLE_G12A
	.comm	_RGB709_to_YUV709l_coeff,4,2    ## @RGB709_to_YUV709l_coeff
	.comm	_VIU_OSD_DDR_PRIORITY_URGENT,4,2 ## @VIU_OSD_DDR_PRIORITY_URGENT
	.comm	_VIU_OSD1_FIFO_CTRL_STAT,4,2    ## @VIU_OSD1_FIFO_CTRL_STAT
	.comm	_VIU_OSD2_FIFO_CTRL_STAT,4,2    ## @VIU_OSD2_FIFO_CTRL_STAT
	.comm	_OSD_REPLACE_SHIFT,4,2          ## @OSD_REPLACE_SHIFT
	.comm	_VIU_OSD1_CTRL_STAT2,4,2        ## @VIU_OSD1_CTRL_STAT2
	.comm	_VIU_OSD2_CTRL_STAT2,4,2        ## @VIU_OSD2_CTRL_STAT2
	.comm	_VIU_CTRL0_VD1_AFBC_MASK,4,2    ## @VIU_CTRL0_VD1_AFBC_MASK
	.comm	_VIU_MISC_CTRL0,4,2             ## @VIU_MISC_CTRL0
	.comm	_AFBC_ENABLE,4,2                ## @AFBC_ENABLE
	.comm	_VD1_IF0_LUMA_FIFO_SIZE,4,2     ## @VD1_IF0_LUMA_FIFO_SIZE
	.comm	_VD2_IF0_LUMA_FIFO_SIZE,4,2     ## @VD2_IF0_LUMA_FIFO_SIZE
	.comm	_VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1,4,2 ## @VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1
	.comm	_VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2,4,2 ## @VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2
	.comm	_VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0,4,2 ## @VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0
	.comm	_VIU_OSD_BLEND_CTRL,4,2         ## @VIU_OSD_BLEND_CTRL
	.comm	_OSD_BLEND_PATH_SEL_ENABLE,4,2  ## @OSD_BLEND_PATH_SEL_ENABLE
	.comm	_OSD1_BLEND_SRC_CTRL,4,2        ## @OSD1_BLEND_SRC_CTRL
	.comm	_OSD2_BLEND_SRC_CTRL,4,2        ## @OSD2_BLEND_SRC_CTRL
	.comm	_VD1_BLEND_SRC_CTRL,4,2         ## @VD1_BLEND_SRC_CTRL
	.comm	_VD2_BLEND_SRC_CTRL,4,2         ## @VD2_BLEND_SRC_CTRL
	.comm	_VIU_OSD_BLEND_DUMMY_DATA0,4,2  ## @VIU_OSD_BLEND_DUMMY_DATA0
	.comm	_VIU_OSD_BLEND_DUMMY_ALPHA,4,2  ## @VIU_OSD_BLEND_DUMMY_ALPHA
	.comm	_DOLBY_PATH_CTRL,4,2            ## @DOLBY_PATH_CTRL
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_meson_viu_init                 ; -- Begin function meson_viu_init
	.p2align	2
_meson_viu_init:                        ; @meson_viu_init
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x21, _VIU_OSD1_OSD_BLK_ENABLE@GOTPAGE
Lloh1:
	ldr	x21, [x21, _VIU_OSD1_OSD_BLK_ENABLE@GOTPAGEOFF]
	ldr	w8, [x21]
Lloh2:
	adrp	x22, _VIU_OSD1_OSD_ENABLE@GOTPAGE
Lloh3:
	ldr	x22, [x22, _VIU_OSD1_OSD_ENABLE@GOTPAGEOFF]
	ldr	w9, [x22]
	orr	w20, w9, w8
	ldr	x23, [x0, #16]
Lloh4:
	adrp	x8, _VIU_OSD1_CTRL_STAT@GOTPAGE
Lloh5:
	ldr	x8, [x8, _VIU_OSD1_CTRL_STAT@GOTPAGEOFF]
Lloh6:
	ldr	w0, [x8]
	bl	__REG
	add	x2, x0, x23
	mov	x0, x20
	mov	w1, #0
	bl	_writel_bits_relaxed
	ldr	w8, [x21]
	ldr	w9, [x22]
	orr	w20, w9, w8
	ldr	x21, [x19, #16]
Lloh7:
	adrp	x8, _VIU_OSD2_CTRL_STAT@GOTPAGE
Lloh8:
	ldr	x8, [x8, _VIU_OSD2_CTRL_STAT@GOTPAGEOFF]
Lloh9:
	ldr	w0, [x8]
	bl	__REG
	add	x2, x0, x21
	mov	x0, x20
	mov	w1, #0
	bl	_writel_bits_relaxed
Lloh10:
	adrp	x8, _VPU_COMPATIBLE_GXM@GOTPAGE
Lloh11:
	ldr	x8, [x8, _VPU_COMPATIBLE_GXM@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_meson_vpu_is_compatible
Lloh13:
	adrp	x21, _VPU_COMPATIBLE_G12A@GOTPAGE
Lloh14:
	ldr	x21, [x21, _VPU_COMPATIBLE_G12A@GOTPAGEOFF]
	cbnz	x0, LBB0_2
; %bb.1:
Lloh15:
	adrp	x8, _VPU_COMPATIBLE_GXL@GOTPAGE
Lloh16:
	ldr	x8, [x8, _VPU_COMPATIBLE_GXL@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_6
LBB0_2:
	mov	x0, x19
	bl	_meson_viu_load_matrix
LBB0_3:
Lloh18:
	adrp	x8, _VIU_OSD_DDR_PRIORITY_URGENT@GOTPAGE
Lloh19:
	ldr	x8, [x8, _VIU_OSD_DDR_PRIORITY_URGENT@GOTPAGEOFF]
Lloh20:
	ldr	w20, [x8]
	mov	w0, #4
	bl	_VIU_OSD_HOLD_FIFO_LINES
	orr	w20, w0, w20
	mov	w22, #32
	mov	w0, #32
	bl	_VIU_OSD_FIFO_DEPTH_VAL
	orr	w20, w20, w0
	mov	w0, #4
	bl	_VIU_OSD_WORDS_PER_BURST
	orr	w20, w20, w0
	mov	w0, #2
	bl	_VIU_OSD_FIFO_LIMITS
	orr	w20, w20, w0
	ldr	w1, [x21]
	mov	x0, x19
	bl	_meson_vpu_is_compatible
	cmp	x0, #0
	mov	w8, #64
	csel	w0, w8, w22, eq
	bl	_meson_viu_osd_burst_length_reg
	orr	w20, w20, w0
	ldr	x22, [x19, #16]
Lloh21:
	adrp	x8, _VIU_OSD1_FIFO_CTRL_STAT@GOTPAGE
Lloh22:
	ldr	x8, [x8, _VIU_OSD1_FIFO_CTRL_STAT@GOTPAGEOFF]
Lloh23:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x20
	bl	_writel_relaxed
	ldr	x22, [x19, #16]
Lloh24:
	adrp	x8, _VIU_OSD2_FIFO_CTRL_STAT@GOTPAGE
Lloh25:
	ldr	x8, [x8, _VIU_OSD2_FIFO_CTRL_STAT@GOTPAGEOFF]
Lloh26:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x20
	bl	_writel_relaxed
Lloh27:
	adrp	x22, _OSD_REPLACE_SHIFT@GOTPAGE
Lloh28:
	ldr	x22, [x22, _OSD_REPLACE_SHIFT@GOTPAGEOFF]
	ldr	w8, [x22]
	mov	w23, #255
	lsl	w20, w23, w8
	ldr	x24, [x19, #16]
Lloh29:
	adrp	x8, _VIU_OSD1_CTRL_STAT2@GOTPAGE
Lloh30:
	ldr	x8, [x8, _VIU_OSD1_CTRL_STAT2@GOTPAGEOFF]
Lloh31:
	ldr	w0, [x8]
	bl	__REG
	add	x2, x0, x24
	mov	x0, x20
	mov	x1, x20
	bl	_writel_bits_relaxed
	ldr	w8, [x22]
	lsl	w20, w23, w8
	ldr	x22, [x19, #16]
Lloh32:
	adrp	x8, _VIU_OSD2_CTRL_STAT2@GOTPAGE
Lloh33:
	ldr	x8, [x8, _VIU_OSD2_CTRL_STAT2@GOTPAGEOFF]
Lloh34:
	ldr	w0, [x8]
	bl	__REG
	add	x2, x0, x22
	mov	x0, x20
	mov	x1, x20
	bl	_writel_bits_relaxed
Lloh35:
	adrp	x8, _VIU_CTRL0_VD1_AFBC_MASK@GOTPAGE
Lloh36:
	ldr	x8, [x8, _VIU_CTRL0_VD1_AFBC_MASK@GOTPAGEOFF]
Lloh37:
	ldr	w20, [x8]
	ldr	x22, [x19, #16]
Lloh38:
	adrp	x8, _VIU_MISC_CTRL0@GOTPAGE
Lloh39:
	ldr	x8, [x8, _VIU_MISC_CTRL0@GOTPAGEOFF]
Lloh40:
	ldr	w0, [x8]
	bl	__REG
	add	x2, x0, x22
	mov	x0, x20
	mov	w1, #0
	bl	_writel_bits_relaxed
	ldr	x20, [x19, #16]
Lloh41:
	adrp	x8, _AFBC_ENABLE@GOTPAGE
Lloh42:
	ldr	x8, [x8, _AFBC_ENABLE@GOTPAGEOFF]
Lloh43:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x20
	mov	w0, #0
	bl	_writel_relaxed
	ldr	x20, [x19, #16]
Lloh44:
	adrp	x8, _VD1_IF0_LUMA_FIFO_SIZE@GOTPAGE
Lloh45:
	ldr	x8, [x8, _VD1_IF0_LUMA_FIFO_SIZE@GOTPAGEOFF]
Lloh46:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x20
	mov	w0, #192
	movk	w0, #255, lsl #16
	bl	_writel_relaxed
	ldr	x20, [x19, #16]
Lloh47:
	adrp	x8, _VD2_IF0_LUMA_FIFO_SIZE@GOTPAGE
Lloh48:
	ldr	x8, [x8, _VD2_IF0_LUMA_FIFO_SIZE@GOTPAGEOFF]
Lloh49:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x20
	mov	w0, #192
	movk	w0, #255, lsl #16
	bl	_writel_relaxed
	ldr	w1, [x21]
	mov	x0, x19
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_5
; %bb.4:
	mov	w0, #0
	mov	w1, #1
	bl	_VIU_OSD_BLEND_REORDER
	mov	x20, x0
	mov	w0, #1
	mov	w1, #0
	bl	_VIU_OSD_BLEND_REORDER
	orr	w20, w0, w20
	mov	w0, #2
	mov	w1, #0
	bl	_VIU_OSD_BLEND_REORDER
	orr	w20, w20, w0
	mov	w0, #3
	mov	w1, #0
	bl	_VIU_OSD_BLEND_REORDER
	orr	w20, w20, w0
	mov	w0, #1
	bl	_VIU_OSD_BLEND_DIN_EN
	orr	w8, w20, w0
Lloh50:
	adrp	x9, _VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1@GOTPAGE
Lloh51:
	ldr	x9, [x9, _VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1@GOTPAGEOFF]
Lloh52:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh53:
	adrp	x9, _VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2@GOTPAGE
Lloh54:
	ldr	x9, [x9, _VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2@GOTPAGEOFF]
Lloh55:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh56:
	adrp	x9, _VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0@GOTPAGE
Lloh57:
	ldr	x9, [x9, _VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0@GOTPAGEOFF]
Lloh58:
	ldr	w9, [x9]
	orr	w20, w8, w9
	mov	w0, #1
	bl	_VIU_OSD_BLEND_BLEN2_PREMULT_EN
	orr	w20, w20, w0
	mov	w0, #4
	bl	_VIU_OSD_BLEND_HOLD_LINES
	orr	w20, w20, w0
	ldr	x21, [x19, #16]
Lloh59:
	adrp	x8, _VIU_OSD_BLEND_CTRL@GOTPAGE
Lloh60:
	ldr	x8, [x8, _VIU_OSD_BLEND_CTRL@GOTPAGEOFF]
Lloh61:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x21
	mov	x0, x20
	bl	_writel_relaxed
Lloh62:
	adrp	x21, _OSD_BLEND_PATH_SEL_ENABLE@GOTPAGE
Lloh63:
	ldr	x21, [x21, _OSD_BLEND_PATH_SEL_ENABLE@GOTPAGEOFF]
	ldr	w20, [x21]
	ldr	x22, [x19, #16]
Lloh64:
	adrp	x8, _OSD1_BLEND_SRC_CTRL@GOTPAGE
Lloh65:
	ldr	x8, [x8, _OSD1_BLEND_SRC_CTRL@GOTPAGEOFF]
Lloh66:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x22
	mov	x0, x20
	bl	_writel_relaxed
	ldr	w20, [x21]
	ldr	x21, [x19, #16]
Lloh67:
	adrp	x8, _OSD2_BLEND_SRC_CTRL@GOTPAGE
Lloh68:
	ldr	x8, [x8, _OSD2_BLEND_SRC_CTRL@GOTPAGEOFF]
Lloh69:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x21
	mov	x0, x20
	bl	_writel_relaxed
	ldr	x20, [x19, #16]
Lloh70:
	adrp	x8, _VD1_BLEND_SRC_CTRL@GOTPAGE
Lloh71:
	ldr	x8, [x8, _VD1_BLEND_SRC_CTRL@GOTPAGEOFF]
Lloh72:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x20
	mov	w0, #0
	bl	_writel_relaxed
	ldr	x20, [x19, #16]
Lloh73:
	adrp	x8, _VD2_BLEND_SRC_CTRL@GOTPAGE
Lloh74:
	ldr	x8, [x8, _VD2_BLEND_SRC_CTRL@GOTPAGEOFF]
Lloh75:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x20
	mov	w0, #0
	bl	_writel_relaxed
	ldr	x20, [x19, #16]
Lloh76:
	adrp	x8, _VIU_OSD_BLEND_DUMMY_DATA0@GOTPAGE
Lloh77:
	ldr	x8, [x8, _VIU_OSD_BLEND_DUMMY_DATA0@GOTPAGEOFF]
Lloh78:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x20
	mov	w0, #0
	bl	_writel_relaxed
	ldr	x20, [x19, #16]
Lloh79:
	adrp	x8, _VIU_OSD_BLEND_DUMMY_ALPHA@GOTPAGE
Lloh80:
	ldr	x8, [x8, _VIU_OSD_BLEND_DUMMY_ALPHA@GOTPAGEOFF]
Lloh81:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x20
	mov	w0, #0
	bl	_writel_relaxed
	mov	w0, #12
	bl	_DOLBY_BYPASS_EN
	mov	x20, x0
	mov	w0, #12
	bl	_DOLBY_BYPASS_EN
	mov	x21, x0
	ldr	x22, [x19, #16]
Lloh82:
	adrp	x8, _DOLBY_PATH_CTRL@GOTPAGE
Lloh83:
	ldr	x8, [x8, _DOLBY_PATH_CTRL@GOTPAGEOFF]
Lloh84:
	ldr	w0, [x8]
	bl	__REG
	add	x2, x0, x22
	mov	x0, x20
	mov	x1, x21
	bl	_writel_bits_relaxed
LBB0_5:
	str	xzr, [x19]
	str	wzr, [x19, #8]
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_6:
	ldr	w1, [x21]
	mov	x0, x19
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_3
; %bb.7:
Lloh85:
	adrp	x8, _RGB709_to_YUV709l_coeff@GOTPAGE
Lloh86:
	ldr	x8, [x8, _RGB709_to_YUV709l_coeff@GOTPAGEOFF]
Lloh87:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_meson_viu_set_g12a_osd1_matrix
	b	LBB0_3
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGot	Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.cfi_endproc
                                        ; -- End function
	.comm	_VIU_OSD1_OSD_BLK_ENABLE,4,2    ; @VIU_OSD1_OSD_BLK_ENABLE
	.comm	_VIU_OSD1_OSD_ENABLE,4,2        ; @VIU_OSD1_OSD_ENABLE
	.comm	_VIU_OSD1_CTRL_STAT,4,2         ; @VIU_OSD1_CTRL_STAT
	.comm	_VIU_OSD2_CTRL_STAT,4,2         ; @VIU_OSD2_CTRL_STAT
	.comm	_VPU_COMPATIBLE_GXM,4,2         ; @VPU_COMPATIBLE_GXM
	.comm	_VPU_COMPATIBLE_GXL,4,2         ; @VPU_COMPATIBLE_GXL
	.comm	_VPU_COMPATIBLE_G12A,4,2        ; @VPU_COMPATIBLE_G12A
	.comm	_RGB709_to_YUV709l_coeff,4,2    ; @RGB709_to_YUV709l_coeff
	.comm	_VIU_OSD_DDR_PRIORITY_URGENT,4,2 ; @VIU_OSD_DDR_PRIORITY_URGENT
	.comm	_VIU_OSD1_FIFO_CTRL_STAT,4,2    ; @VIU_OSD1_FIFO_CTRL_STAT
	.comm	_VIU_OSD2_FIFO_CTRL_STAT,4,2    ; @VIU_OSD2_FIFO_CTRL_STAT
	.comm	_OSD_REPLACE_SHIFT,4,2          ; @OSD_REPLACE_SHIFT
	.comm	_VIU_OSD1_CTRL_STAT2,4,2        ; @VIU_OSD1_CTRL_STAT2
	.comm	_VIU_OSD2_CTRL_STAT2,4,2        ; @VIU_OSD2_CTRL_STAT2
	.comm	_VIU_CTRL0_VD1_AFBC_MASK,4,2    ; @VIU_CTRL0_VD1_AFBC_MASK
	.comm	_VIU_MISC_CTRL0,4,2             ; @VIU_MISC_CTRL0
	.comm	_AFBC_ENABLE,4,2                ; @AFBC_ENABLE
	.comm	_VD1_IF0_LUMA_FIFO_SIZE,4,2     ; @VD1_IF0_LUMA_FIFO_SIZE
	.comm	_VD2_IF0_LUMA_FIFO_SIZE,4,2     ; @VD2_IF0_LUMA_FIFO_SIZE
	.comm	_VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1,4,2 ; @VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1
	.comm	_VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2,4,2 ; @VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2
	.comm	_VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0,4,2 ; @VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0
	.comm	_VIU_OSD_BLEND_CTRL,4,2         ; @VIU_OSD_BLEND_CTRL
	.comm	_OSD_BLEND_PATH_SEL_ENABLE,4,2  ; @OSD_BLEND_PATH_SEL_ENABLE
	.comm	_OSD1_BLEND_SRC_CTRL,4,2        ; @OSD1_BLEND_SRC_CTRL
	.comm	_OSD2_BLEND_SRC_CTRL,4,2        ; @OSD2_BLEND_SRC_CTRL
	.comm	_VD1_BLEND_SRC_CTRL,4,2         ; @VD1_BLEND_SRC_CTRL
	.comm	_VD2_BLEND_SRC_CTRL,4,2         ; @VD2_BLEND_SRC_CTRL
	.comm	_VIU_OSD_BLEND_DUMMY_DATA0,4,2  ; @VIU_OSD_BLEND_DUMMY_DATA0
	.comm	_VIU_OSD_BLEND_DUMMY_ALPHA,4,2  ; @VIU_OSD_BLEND_DUMMY_ALPHA
	.comm	_DOLBY_PATH_CTRL,4,2            ; @DOLBY_PATH_CTRL
.subsections_via_symbols
