	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function si_init_smc_table
_si_init_smc_table:                     ## @si_init_smc_table
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	callq	_rv770_get_pi
	movq	%rax, %r13
	movq	%rbx, %rdi
	callq	_si_get_pi
	movq	%rax, %r15
	movq	16(%rbx), %r12
	leaq	8(%rax), %r14
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	_si_populate_smc_voltage_tables
	movl	(%rbx), %eax
	addl	$-128, %eax
	cmpl	$2, %eax
	ja	LBB0_1
## %bb.2:
	cltq
	leaq	l_switch.table.si_init_smc_table(%rip), %rcx
	movq	(%rcx,%rax,8), %rax
	jmp	LBB0_3
LBB0_1:
	movq	_PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %eax
	movl	%eax, 28(%r15)
	movl	8(%rbx), %eax
	movq	_ATOM_PP_PLATFORM_CAP_HARDWAREDC@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_5
## %bb.4:
	movq	_PPSMC_SYSTEMFLAG_GPIO_DC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	%ecx, 20(%r15)
LBB0_5:
	movq	_ATOM_PP_PLATFORM_CAP_REGULATOR_HOT@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_8
## %bb.6:
	movq	24(%rbx), %rcx
	movl	(%rcx), %ecx
	andl	$-2, %ecx
	cmpl	$26648, %ecx                    ## imm = 0x6818
	je	LBB0_8
## %bb.7:
	movq	_PPSMC_SYSTEMFLAG_REGULATOR_HOT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	%ecx, 20(%r15)
LBB0_8:
	movq	_ATOM_PP_PLATFORM_CAP_STEPVDDC@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_10
## %bb.9:
	movq	_PPSMC_SYSTEMFLAG_STEPVDDC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	%ecx, 20(%r15)
LBB0_10:
	cmpq	$0, (%r13)
	je	LBB0_12
## %bb.11:
	movq	_PPSMC_SYSTEMFLAG_GDDR5@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	%ecx, 20(%r15)
LBB0_12:
	movq	_ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_14
## %bb.13:
	movq	_PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	%ecx, 24(%r15)
LBB0_14:
	movq	_ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_16
## %bb.15:
	movq	_PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, 20(%r15)
	movl	12(%rbx), %edx
	movq	_SI_SMC_SOFT_REGISTER_vr_hot_gpio@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_si_write_smc_soft_register
LBB0_16:
	movq	%rbx, %rdi
	movq	%r12, %rsi
	movq	%r14, %rdx
	callq	_si_populate_smc_initial_state
	testl	%eax, %eax
	jne	LBB0_26
## %bb.17:
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	_si_populate_smc_acpi_state
	testl	%eax, %eax
	jne	LBB0_26
## %bb.18:
	movl	8(%r15), %eax
	movl	%eax, 16(%r15)
	movq	_SISLANDS_INITIAL_STATE_ARB_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	_si_do_program_memory_timing_parameters
	testl	%eax, %eax
	je	LBB0_19
LBB0_26:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_19:
	cmpq	$0, 48(%r15)
	je	LBB0_24
## %bb.20:
	cmpq	$0, 40(%r15)
	je	LBB0_24
## %bb.21:
	movq	%r15, %rsi
	addq	$12, %rsi
	movq	%rbx, %rdi
	callq	_si_populate_ulv_state
	testl	%eax, %eax
	jne	LBB0_26
## %bb.22:
	movq	%rbx, %rdi
	callq	_si_program_ulv_memory_timing_parameters
	testl	%eax, %eax
	jne	LBB0_26
## %bb.23:
	movq	_CG_ULV_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	36(%r15), %esi
	callq	_WREG32
	movq	_CG_ULV_PARAMETER@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	32(%r15), %esi
	callq	_WREG32
	movq	%rbx, %rdi
	callq	_radeon_get_pcie_lanes
	movq	_SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	%rbx, %rdi
	movl	%eax, %edx
	callq	_si_write_smc_soft_register
	jmp	LBB0_25
LBB0_24:
	movl	8(%r15), %eax
	movl	%eax, 12(%r15)
LBB0_25:
	movl	(%r15), %r8d
	movl	4(%r15), %esi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$24, %ecx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_si_copy_bytes_to_smc           ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PPSMC_THERMAL_PROTECT_TYPE_INTERNAL,4,2 ## @PPSMC_THERMAL_PROTECT_TYPE_INTERNAL
	.comm	_PPSMC_THERMAL_PROTECT_TYPE_NONE,4,2 ## @PPSMC_THERMAL_PROTECT_TYPE_NONE
	.comm	_PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL,4,2 ## @PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL
	.comm	_ATOM_PP_PLATFORM_CAP_HARDWAREDC,4,2 ## @ATOM_PP_PLATFORM_CAP_HARDWAREDC
	.comm	_PPSMC_SYSTEMFLAG_GPIO_DC,4,2   ## @PPSMC_SYSTEMFLAG_GPIO_DC
	.comm	_ATOM_PP_PLATFORM_CAP_REGULATOR_HOT,4,2 ## @ATOM_PP_PLATFORM_CAP_REGULATOR_HOT
	.comm	_PPSMC_SYSTEMFLAG_REGULATOR_HOT,4,2 ## @PPSMC_SYSTEMFLAG_REGULATOR_HOT
	.comm	_ATOM_PP_PLATFORM_CAP_STEPVDDC,4,2 ## @ATOM_PP_PLATFORM_CAP_STEPVDDC
	.comm	_PPSMC_SYSTEMFLAG_STEPVDDC,4,2  ## @PPSMC_SYSTEMFLAG_STEPVDDC
	.comm	_PPSMC_SYSTEMFLAG_GDDR5,4,2     ## @PPSMC_SYSTEMFLAG_GDDR5
	.comm	_ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY,4,2 ## @ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY
	.comm	_PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH,4,2 ## @PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH
	.comm	_ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE,4,2 ## @ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE
	.comm	_PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO,4,2 ## @PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO
	.comm	_SI_SMC_SOFT_REGISTER_vr_hot_gpio,4,2 ## @SI_SMC_SOFT_REGISTER_vr_hot_gpio
	.comm	_SISLANDS_INITIAL_STATE_ARB_INDEX,4,2 ## @SISLANDS_INITIAL_STATE_ARB_INDEX
	.comm	_CG_ULV_CONTROL,4,2             ## @CG_ULV_CONTROL
	.comm	_CG_ULV_PARAMETER,4,2           ## @CG_ULV_PARAMETER
	.comm	_SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width,4,2 ## @SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width
	.no_dead_strip	_si_init_smc_table
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.si_init_smc_table
l_switch.table.si_init_smc_table:
	.quad	_PPSMC_THERMAL_PROTECT_TYPE_INTERNAL
	.quad	_PPSMC_THERMAL_PROTECT_TYPE_NONE
	.quad	_PPSMC_THERMAL_PROTECT_TYPE_INTERNAL

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function si_init_smc_table
_si_init_smc_table:                     ; @si_init_smc_table
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	bl	_rv770_get_pi
	mov	x23, x0
	mov	x0, x19
	bl	_si_get_pi
	mov	x21, x0
	ldr	x22, [x19, #16]
	add	x20, x0, #8
	mov	x0, x19
	mov	x1, x20
	bl	_si_populate_smc_voltage_tables
	ldr	w8, [x19]
	sub	w8, w8, #128
	cmp	w8, #2
	b.hi	LBB0_2
; %bb.1:
Lloh0:
	adrp	x9, l_switch.table.si_init_smc_table@PAGE
Lloh1:
	add	x9, x9, l_switch.table.si_init_smc_table@PAGEOFF
	ldr	x8, [x9, w8, sxtw #3]
	b	LBB0_3
LBB0_2:
Lloh2:
	adrp	x8, _PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL@GOTPAGE
Lloh3:
	ldr	x8, [x8, _PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL@GOTPAGEOFF]
LBB0_3:
	ldr	w8, [x8]
	str	w8, [x21, #28]
	ldr	w8, [x19, #8]
Lloh4:
	adrp	x9, _ATOM_PP_PLATFORM_CAP_HARDWAREDC@GOTPAGE
Lloh5:
	ldr	x9, [x9, _ATOM_PP_PLATFORM_CAP_HARDWAREDC@GOTPAGEOFF]
Lloh6:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_5
; %bb.4:
Lloh7:
	adrp	x9, _PPSMC_SYSTEMFLAG_GPIO_DC@GOTPAGE
Lloh8:
	ldr	x9, [x9, _PPSMC_SYSTEMFLAG_GPIO_DC@GOTPAGEOFF]
Lloh9:
	ldr	w9, [x9]
	ldr	w10, [x21, #20]
	orr	w9, w10, w9
	str	w9, [x21, #20]
LBB0_5:
Lloh10:
	adrp	x9, _ATOM_PP_PLATFORM_CAP_REGULATOR_HOT@GOTPAGE
Lloh11:
	ldr	x9, [x9, _ATOM_PP_PLATFORM_CAP_REGULATOR_HOT@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_8
; %bb.6:
	ldr	x9, [x19, #24]
	ldr	w9, [x9]
	mov	w10, #13324
	cmp	w10, w9, lsr #1
	b.eq	LBB0_8
; %bb.7:
Lloh13:
	adrp	x9, _PPSMC_SYSTEMFLAG_REGULATOR_HOT@GOTPAGE
Lloh14:
	ldr	x9, [x9, _PPSMC_SYSTEMFLAG_REGULATOR_HOT@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	ldr	w10, [x21, #20]
	orr	w9, w10, w9
	str	w9, [x21, #20]
LBB0_8:
Lloh16:
	adrp	x9, _ATOM_PP_PLATFORM_CAP_STEPVDDC@GOTPAGE
Lloh17:
	ldr	x9, [x9, _ATOM_PP_PLATFORM_CAP_STEPVDDC@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_10
; %bb.9:
Lloh19:
	adrp	x9, _PPSMC_SYSTEMFLAG_STEPVDDC@GOTPAGE
Lloh20:
	ldr	x9, [x9, _PPSMC_SYSTEMFLAG_STEPVDDC@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	ldr	w10, [x21, #20]
	orr	w9, w10, w9
	str	w9, [x21, #20]
LBB0_10:
	ldr	x9, [x23]
	cbz	x9, LBB0_12
; %bb.11:
Lloh22:
	adrp	x9, _PPSMC_SYSTEMFLAG_GDDR5@GOTPAGE
Lloh23:
	ldr	x9, [x9, _PPSMC_SYSTEMFLAG_GDDR5@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	ldr	w10, [x21, #20]
	orr	w9, w10, w9
	str	w9, [x21, #20]
LBB0_12:
Lloh25:
	adrp	x9, _ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY@GOTPAGE
Lloh26:
	ldr	x9, [x9, _ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_14
; %bb.13:
Lloh28:
	adrp	x9, _PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH@GOTPAGE
Lloh29:
	ldr	x9, [x9, _PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
	ldr	w10, [x21, #24]
	orr	w9, w10, w9
	str	w9, [x21, #24]
LBB0_14:
Lloh31:
	adrp	x9, _ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE@GOTPAGE
Lloh32:
	ldr	x9, [x9, _ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE@GOTPAGEOFF]
Lloh33:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_16
; %bb.15:
Lloh34:
	adrp	x8, _PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO@GOTPAGE
Lloh35:
	ldr	x8, [x8, _PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO@GOTPAGEOFF]
Lloh36:
	ldr	w8, [x8]
	ldr	w9, [x21, #20]
	orr	w8, w9, w8
	str	w8, [x21, #20]
	ldr	w2, [x19, #12]
Lloh37:
	adrp	x8, _SI_SMC_SOFT_REGISTER_vr_hot_gpio@GOTPAGE
Lloh38:
	ldr	x8, [x8, _SI_SMC_SOFT_REGISTER_vr_hot_gpio@GOTPAGEOFF]
Lloh39:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_si_write_smc_soft_register
LBB0_16:
	mov	x0, x19
	mov	x1, x22
	mov	x2, x20
	bl	_si_populate_smc_initial_state
	cbnz	w0, LBB0_19
; %bb.17:
	mov	x0, x19
	mov	x1, x20
	bl	_si_populate_smc_acpi_state
	cbnz	w0, LBB0_19
; %bb.18:
	ldr	w8, [x21, #8]
	str	w8, [x21, #16]
Lloh40:
	adrp	x8, _SISLANDS_INITIAL_STATE_ARB_INDEX@GOTPAGE
Lloh41:
	ldr	x8, [x8, _SISLANDS_INITIAL_STATE_ARB_INDEX@GOTPAGEOFF]
Lloh42:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x22
	bl	_si_do_program_memory_timing_parameters
	cbz	w0, LBB0_20
LBB0_19:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_20:
	ldr	x8, [x21, #48]
	cbz	x8, LBB0_25
; %bb.21:
	ldr	x8, [x21, #40]
	cbz	x8, LBB0_25
; %bb.22:
	add	x1, x21, #12
	mov	x0, x19
	bl	_si_populate_ulv_state
	cbnz	w0, LBB0_19
; %bb.23:
	mov	x0, x19
	bl	_si_program_ulv_memory_timing_parameters
	cbnz	w0, LBB0_19
; %bb.24:
Lloh43:
	adrp	x8, _CG_ULV_CONTROL@GOTPAGE
Lloh44:
	ldr	x8, [x8, _CG_ULV_CONTROL@GOTPAGEOFF]
Lloh45:
	ldr	w0, [x8]
	ldr	w1, [x21, #36]
	bl	_WREG32
Lloh46:
	adrp	x8, _CG_ULV_PARAMETER@GOTPAGE
Lloh47:
	ldr	x8, [x8, _CG_ULV_PARAMETER@GOTPAGEOFF]
Lloh48:
	ldr	w0, [x8]
	ldr	w1, [x21, #32]
	bl	_WREG32
	mov	x0, x19
	bl	_radeon_get_pcie_lanes
	mov	x2, x0
Lloh49:
	adrp	x8, _SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width@GOTPAGE
Lloh50:
	ldr	x8, [x8, _SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width@GOTPAGEOFF]
Lloh51:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_si_write_smc_soft_register
	b	LBB0_26
LBB0_25:
	ldr	w8, [x21, #8]
	str	w8, [x21, #12]
LBB0_26:
	ldp	w4, w1, [x21]
	mov	x0, x19
	mov	x2, x20
	mov	w3, #24
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_si_copy_bytes_to_smc
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.cfi_endproc
                                        ; -- End function
	.comm	_PPSMC_THERMAL_PROTECT_TYPE_INTERNAL,4,2 ; @PPSMC_THERMAL_PROTECT_TYPE_INTERNAL
	.comm	_PPSMC_THERMAL_PROTECT_TYPE_NONE,4,2 ; @PPSMC_THERMAL_PROTECT_TYPE_NONE
	.comm	_PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL,4,2 ; @PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL
	.comm	_ATOM_PP_PLATFORM_CAP_HARDWAREDC,4,2 ; @ATOM_PP_PLATFORM_CAP_HARDWAREDC
	.comm	_PPSMC_SYSTEMFLAG_GPIO_DC,4,2   ; @PPSMC_SYSTEMFLAG_GPIO_DC
	.comm	_ATOM_PP_PLATFORM_CAP_REGULATOR_HOT,4,2 ; @ATOM_PP_PLATFORM_CAP_REGULATOR_HOT
	.comm	_PPSMC_SYSTEMFLAG_REGULATOR_HOT,4,2 ; @PPSMC_SYSTEMFLAG_REGULATOR_HOT
	.comm	_ATOM_PP_PLATFORM_CAP_STEPVDDC,4,2 ; @ATOM_PP_PLATFORM_CAP_STEPVDDC
	.comm	_PPSMC_SYSTEMFLAG_STEPVDDC,4,2  ; @PPSMC_SYSTEMFLAG_STEPVDDC
	.comm	_PPSMC_SYSTEMFLAG_GDDR5,4,2     ; @PPSMC_SYSTEMFLAG_GDDR5
	.comm	_ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY,4,2 ; @ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY
	.comm	_PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH,4,2 ; @PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH
	.comm	_ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE,4,2 ; @ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE
	.comm	_PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO,4,2 ; @PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO
	.comm	_SI_SMC_SOFT_REGISTER_vr_hot_gpio,4,2 ; @SI_SMC_SOFT_REGISTER_vr_hot_gpio
	.comm	_SISLANDS_INITIAL_STATE_ARB_INDEX,4,2 ; @SISLANDS_INITIAL_STATE_ARB_INDEX
	.comm	_CG_ULV_CONTROL,4,2             ; @CG_ULV_CONTROL
	.comm	_CG_ULV_PARAMETER,4,2           ; @CG_ULV_PARAMETER
	.comm	_SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width,4,2 ; @SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width
	.no_dead_strip	_si_init_smc_table
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.si_init_smc_table
l_switch.table.si_init_smc_table:
	.quad	_PPSMC_THERMAL_PROTECT_TYPE_INTERNAL
	.quad	_PPSMC_THERMAL_PROTECT_TYPE_NONE
	.quad	_PPSMC_THERMAL_PROTECT_TYPE_INTERNAL

.subsections_via_symbols
