	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function fw_type_convert
_fw_type_convert:                       ## @fw_type_convert
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
                                        ## kill: def $esi killed $esi def $rsi
	addl	$-128, %esi
	cmpl	$9, %esi
	ja	LBB0_5
## %bb.1:
	leaq	LJTI0_0(%rip), %rax
	movslq	(%rax,%rsi,4), %rcx
	addq	%rax, %rcx
	jmpq	*%rcx
LBB0_2:
	movq	_AMDGPU_UCODE_ID_CP_MEC1@GOTPCREL(%rip), %rax
	jmp	LBB0_13
LBB0_3:
	movq	_AMDGPU_UCODE_ID_CP_PFP@GOTPCREL(%rip), %rax
	jmp	LBB0_13
LBB0_4:
	movq	_AMDGPU_UCODE_ID_CP_CE@GOTPCREL(%rip), %rax
	jmp	LBB0_13
LBB0_5:
	movq	_AMDGPU_UCODE_ID_MAXIMUM@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	leaq	L_.str(%rip), %rdi
	callq	_DRM_ERROR
	jmp	LBB0_14
LBB0_6:
	movq	_AMDGPU_UCODE_ID_STORAGE@GOTPCREL(%rip), %rax
	jmp	LBB0_13
LBB0_7:
	movq	_AMDGPU_UCODE_ID_SDMA1@GOTPCREL(%rip), %rax
	jmp	LBB0_13
LBB0_8:
	movq	_AMDGPU_UCODE_ID_SDMA0@GOTPCREL(%rip), %rax
	jmp	LBB0_13
LBB0_9:
	movq	_AMDGPU_UCODE_ID_RLC_G@GOTPCREL(%rip), %rax
	jmp	LBB0_13
LBB0_10:
	movq	_adev@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movl	(%rax), %eax
	movq	_CHIP_TOPAZ@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jge	LBB0_2
## %bb.11:
	movq	_AMDGPU_UCODE_ID_CP_MEC2@GOTPCREL(%rip), %rax
	jmp	LBB0_13
LBB0_12:
	movq	_AMDGPU_UCODE_ID_CP_ME@GOTPCREL(%rip), %rax
LBB0_13:
	movl	(%rax), %ebx
LBB0_14:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_6, LBB0_6-LJTI0_0
.set L0_0_set_7, LBB0_7-LJTI0_0
.set L0_0_set_8, LBB0_8-LJTI0_0
.set L0_0_set_9, LBB0_9-LJTI0_0
.set L0_0_set_3, LBB0_3-LJTI0_0
.set L0_0_set_10, LBB0_10-LJTI0_0
.set L0_0_set_2, LBB0_2-LJTI0_0
.set L0_0_set_12, LBB0_12-LJTI0_0
.set L0_0_set_4, LBB0_4-LJTI0_0
LJTI0_0:
	.long	L0_0_set_6
	.long	L0_0_set_7
	.long	L0_0_set_8
	.long	L0_0_set_9
	.long	L0_0_set_3
	.long	L0_0_set_10
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_12
	.long	L0_0_set_4
	.end_data_region
                                        ## -- End function
	.comm	_CGS_FUNC_ADEV,4,2              ## @CGS_FUNC_ADEV
	.comm	_AMDGPU_UCODE_ID_MAXIMUM,4,2    ## @AMDGPU_UCODE_ID_MAXIMUM
	.comm	_AMDGPU_UCODE_ID_SDMA0,4,2      ## @AMDGPU_UCODE_ID_SDMA0
	.comm	_AMDGPU_UCODE_ID_SDMA1,4,2      ## @AMDGPU_UCODE_ID_SDMA1
	.comm	_AMDGPU_UCODE_ID_CP_CE,4,2      ## @AMDGPU_UCODE_ID_CP_CE
	.comm	_AMDGPU_UCODE_ID_CP_PFP,4,2     ## @AMDGPU_UCODE_ID_CP_PFP
	.comm	_AMDGPU_UCODE_ID_CP_ME,4,2      ## @AMDGPU_UCODE_ID_CP_ME
	.comm	_AMDGPU_UCODE_ID_CP_MEC1,4,2    ## @AMDGPU_UCODE_ID_CP_MEC1
	.comm	_adev,8,3                       ## @adev
	.comm	_CHIP_TOPAZ,4,2                 ## @CHIP_TOPAZ
	.comm	_AMDGPU_UCODE_ID_CP_MEC2,4,2    ## @AMDGPU_UCODE_ID_CP_MEC2
	.comm	_AMDGPU_UCODE_ID_RLC_G,4,2      ## @AMDGPU_UCODE_ID_RLC_G
	.comm	_AMDGPU_UCODE_ID_STORAGE,4,2    ## @AMDGPU_UCODE_ID_STORAGE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Firmware type not supported\n"

	.no_dead_strip	_fw_type_convert
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function fw_type_convert
_fw_type_convert:                       ; @fw_type_convert
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	sub	w8, w1, #128
	cmp	w8, #9
	b.hi	LBB0_5
; %bb.1:
Lloh0:
	adrp	x9, lJTI0_0@PAGE
Lloh1:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_2
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_2:
Lloh2:
	adrp	x8, _AMDGPU_UCODE_ID_CP_MEC1@GOTPAGE
Lloh3:
	ldr	x8, [x8, _AMDGPU_UCODE_ID_CP_MEC1@GOTPAGEOFF]
	b	LBB0_13
LBB0_3:
Lloh4:
	adrp	x8, _AMDGPU_UCODE_ID_CP_PFP@GOTPAGE
Lloh5:
	ldr	x8, [x8, _AMDGPU_UCODE_ID_CP_PFP@GOTPAGEOFF]
	b	LBB0_13
LBB0_4:
Lloh6:
	adrp	x8, _AMDGPU_UCODE_ID_CP_CE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _AMDGPU_UCODE_ID_CP_CE@GOTPAGEOFF]
	b	LBB0_13
LBB0_5:
Lloh8:
	adrp	x8, _AMDGPU_UCODE_ID_MAXIMUM@GOTPAGE
Lloh9:
	ldr	x8, [x8, _AMDGPU_UCODE_ID_MAXIMUM@GOTPAGEOFF]
Lloh10:
	ldr	w19, [x8]
Lloh11:
	adrp	x0, l_.str@PAGE
Lloh12:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_ERROR
	b	LBB0_14
LBB0_6:
Lloh13:
	adrp	x8, _AMDGPU_UCODE_ID_STORAGE@GOTPAGE
Lloh14:
	ldr	x8, [x8, _AMDGPU_UCODE_ID_STORAGE@GOTPAGEOFF]
	b	LBB0_13
LBB0_7:
Lloh15:
	adrp	x8, _AMDGPU_UCODE_ID_SDMA1@GOTPAGE
Lloh16:
	ldr	x8, [x8, _AMDGPU_UCODE_ID_SDMA1@GOTPAGEOFF]
	b	LBB0_13
LBB0_8:
Lloh17:
	adrp	x8, _AMDGPU_UCODE_ID_SDMA0@GOTPAGE
Lloh18:
	ldr	x8, [x8, _AMDGPU_UCODE_ID_SDMA0@GOTPAGEOFF]
	b	LBB0_13
LBB0_9:
Lloh19:
	adrp	x8, _AMDGPU_UCODE_ID_RLC_G@GOTPAGE
Lloh20:
	ldr	x8, [x8, _AMDGPU_UCODE_ID_RLC_G@GOTPAGEOFF]
	b	LBB0_13
LBB0_10:
Lloh21:
	adrp	x8, _adev@GOTPAGE
Lloh22:
	ldr	x8, [x8, _adev@GOTPAGEOFF]
Lloh23:
	ldr	x8, [x8]
	ldr	w8, [x8]
Lloh24:
	adrp	x9, _CHIP_TOPAZ@GOTPAGE
Lloh25:
	ldr	x9, [x9, _CHIP_TOPAZ@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ge	LBB0_2
; %bb.11:
Lloh27:
	adrp	x8, _AMDGPU_UCODE_ID_CP_MEC2@GOTPAGE
Lloh28:
	ldr	x8, [x8, _AMDGPU_UCODE_ID_CP_MEC2@GOTPAGEOFF]
	b	LBB0_13
LBB0_12:
Lloh29:
	adrp	x8, _AMDGPU_UCODE_ID_CP_ME@GOTPAGE
Lloh30:
	ldr	x8, [x8, _AMDGPU_UCODE_ID_CP_ME@GOTPAGEOFF]
LBB0_13:
	ldr	w19, [x8]
LBB0_14:
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpAdd	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh29, Lloh30
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_6-LBB0_2)>>2
	.byte	(LBB0_7-LBB0_2)>>2
	.byte	(LBB0_8-LBB0_2)>>2
	.byte	(LBB0_9-LBB0_2)>>2
	.byte	(LBB0_3-LBB0_2)>>2
	.byte	(LBB0_10-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_12-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
                                        ; -- End function
	.comm	_CGS_FUNC_ADEV,4,2              ; @CGS_FUNC_ADEV
	.comm	_AMDGPU_UCODE_ID_MAXIMUM,4,2    ; @AMDGPU_UCODE_ID_MAXIMUM
	.comm	_AMDGPU_UCODE_ID_SDMA0,4,2      ; @AMDGPU_UCODE_ID_SDMA0
	.comm	_AMDGPU_UCODE_ID_SDMA1,4,2      ; @AMDGPU_UCODE_ID_SDMA1
	.comm	_AMDGPU_UCODE_ID_CP_CE,4,2      ; @AMDGPU_UCODE_ID_CP_CE
	.comm	_AMDGPU_UCODE_ID_CP_PFP,4,2     ; @AMDGPU_UCODE_ID_CP_PFP
	.comm	_AMDGPU_UCODE_ID_CP_ME,4,2      ; @AMDGPU_UCODE_ID_CP_ME
	.comm	_AMDGPU_UCODE_ID_CP_MEC1,4,2    ; @AMDGPU_UCODE_ID_CP_MEC1
	.comm	_adev,8,3                       ; @adev
	.comm	_CHIP_TOPAZ,4,2                 ; @CHIP_TOPAZ
	.comm	_AMDGPU_UCODE_ID_CP_MEC2,4,2    ; @AMDGPU_UCODE_ID_CP_MEC2
	.comm	_AMDGPU_UCODE_ID_RLC_G,4,2      ; @AMDGPU_UCODE_ID_RLC_G
	.comm	_AMDGPU_UCODE_ID_STORAGE,4,2    ; @AMDGPU_UCODE_ID_STORAGE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Firmware type not supported\n"

	.no_dead_strip	_fw_type_convert
.subsections_via_symbols
