	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function arc_pgu_crtc_mode_set_nofb
_arc_pgu_crtc_mode_set_nofb:            ## @arc_pgu_crtc_mode_set_nofb
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	callq	_crtc_to_arcpgu_priv
	movq	%rax, %r15
	movq	(%r14), %rbx
	movq	_ARCPGU_REG_FMT@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	88(%rbx), %rsi
	movq	96(%rbx), %rdi
	callq	_ENCODE_PGU_XY
	movq	%r15, %rdi
	movl	%r12d, %esi
	movl	%eax, %edx
	callq	_arc_pgu_write
	movq	_ARCPGU_REG_HSYNC@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	80(%rbx), %rdi
	movq	64(%rbx), %rax
	movq	72(%rbx), %rsi
	subq	%rax, %rdi
	subq	%rax, %rsi
	callq	_ENCODE_PGU_XY
	movq	%r15, %rdi
	movl	%r12d, %esi
	movl	%eax, %edx
	callq	_arc_pgu_write
	movq	_ARCPGU_REG_VSYNC@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	56(%rbx), %rdi
	movq	40(%rbx), %rax
	movq	48(%rbx), %rsi
	subq	%rax, %rdi
	subq	%rax, %rsi
	callq	_ENCODE_PGU_XY
	movq	%r15, %rdi
	movl	%r12d, %esi
	movl	%eax, %edx
	callq	_arc_pgu_write
	movq	_ARCPGU_REG_ACTIVE@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	16(%rbx), %rsi
	movq	32(%rbx), %rdi
	subq	24(%rbx), %rdi
	subq	8(%rbx), %rsi
	callq	_ENCODE_PGU_XY
	movq	%r15, %rdi
	movl	%r12d, %esi
	movl	%eax, %edx
	callq	_arc_pgu_write
	movq	_ARCPGU_REG_CTRL@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_arc_pgu_read
	movl	(%rbx), %esi
	movq	_DRM_MODE_FLAG_PVSYNC@GOTPCREL(%rip), %rdx
	movq	_ARCPGU_CTRL_VS_POL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movq	_ARCPGU_CTRL_VS_POL_OFST@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edi
	movl	(%rdx), %ecx
	andl	%esi, %ecx
	movl	%edi, %edx
	orl	%eax, %edx
	notl	%edi
	andl	%eax, %edi
	testl	%ecx, %ecx
	cmovnel	%edx, %edi
	movq	_DRM_MODE_FLAG_PHSYNC@GOTPCREL(%rip), %rax
	andl	(%rax), %esi
	movq	_ARCPGU_CTRL_HS_POL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_ARCPGU_CTRL_HS_POL_OFST@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %edx
	movl	%edx, %eax
	orl	%edi, %eax
	notl	%edx
	andl	%edi, %edx
	testl	%esi, %esi
	cmovnel	%eax, %edx
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_arc_pgu_write
	movq	_ARCPGU_REG_STRIDE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_arc_pgu_write
	movq	_ARCPGU_REG_START_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$1, %edx
	callq	_arc_pgu_write
	movq	%r14, %rdi
	callq	_arc_pgu_set_pxl_fmt
	movl	(%r15), %edi
	imull	$1000, 4(%rbx), %esi            ## imm = 0x3E8
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_clk_set_rate                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_ARCPGU_REG_FMT,4,2             ## @ARCPGU_REG_FMT
	.comm	_ARCPGU_REG_HSYNC,4,2           ## @ARCPGU_REG_HSYNC
	.comm	_ARCPGU_REG_VSYNC,4,2           ## @ARCPGU_REG_VSYNC
	.comm	_ARCPGU_REG_ACTIVE,4,2          ## @ARCPGU_REG_ACTIVE
	.comm	_ARCPGU_REG_CTRL,4,2            ## @ARCPGU_REG_CTRL
	.comm	_DRM_MODE_FLAG_PVSYNC,4,2       ## @DRM_MODE_FLAG_PVSYNC
	.comm	_ARCPGU_CTRL_VS_POL_MASK,4,2    ## @ARCPGU_CTRL_VS_POL_MASK
	.comm	_ARCPGU_CTRL_VS_POL_OFST,4,2    ## @ARCPGU_CTRL_VS_POL_OFST
	.comm	_DRM_MODE_FLAG_PHSYNC,4,2       ## @DRM_MODE_FLAG_PHSYNC
	.comm	_ARCPGU_CTRL_HS_POL_MASK,4,2    ## @ARCPGU_CTRL_HS_POL_MASK
	.comm	_ARCPGU_CTRL_HS_POL_OFST,4,2    ## @ARCPGU_CTRL_HS_POL_OFST
	.comm	_ARCPGU_REG_STRIDE,4,2          ## @ARCPGU_REG_STRIDE
	.comm	_ARCPGU_REG_START_SET,4,2       ## @ARCPGU_REG_START_SET
	.no_dead_strip	_arc_pgu_crtc_mode_set_nofb
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function arc_pgu_crtc_mode_set_nofb
_arc_pgu_crtc_mode_set_nofb:            ; @arc_pgu_crtc_mode_set_nofb
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	bl	_crtc_to_arcpgu_priv
	mov	x20, x0
	ldr	x22, [x19]
Lloh0:
	adrp	x8, _ARCPGU_REG_FMT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _ARCPGU_REG_FMT@GOTPAGEOFF]
Lloh2:
	ldr	w21, [x8]
	ldp	x1, x0, [x22, #88]
	bl	_ENCODE_PGU_XY
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_arc_pgu_write
Lloh3:
	adrp	x8, _ARCPGU_REG_HSYNC@GOTPAGE
Lloh4:
	ldr	x8, [x8, _ARCPGU_REG_HSYNC@GOTPAGEOFF]
Lloh5:
	ldr	w21, [x8]
	ldp	x10, x8, [x22, #72]
	ldr	x9, [x22, #64]
	sub	x0, x8, x9
	sub	x1, x10, x9
	bl	_ENCODE_PGU_XY
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_arc_pgu_write
Lloh6:
	adrp	x8, _ARCPGU_REG_VSYNC@GOTPAGE
Lloh7:
	ldr	x8, [x8, _ARCPGU_REG_VSYNC@GOTPAGEOFF]
Lloh8:
	ldr	w21, [x8]
	ldp	x10, x8, [x22, #48]
	ldr	x9, [x22, #40]
	sub	x0, x8, x9
	sub	x1, x10, x9
	bl	_ENCODE_PGU_XY
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_arc_pgu_write
Lloh9:
	adrp	x8, _ARCPGU_REG_ACTIVE@GOTPAGE
Lloh10:
	ldr	x8, [x8, _ARCPGU_REG_ACTIVE@GOTPAGEOFF]
Lloh11:
	ldr	w21, [x8]
	ldp	x9, x8, [x22, #24]
	sub	x0, x8, x9
	ldp	x9, x8, [x22, #8]
	sub	x1, x8, x9
	bl	_ENCODE_PGU_XY
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_arc_pgu_write
Lloh12:
	adrp	x21, _ARCPGU_REG_CTRL@GOTPAGE
Lloh13:
	ldr	x21, [x21, _ARCPGU_REG_CTRL@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x20
	bl	_arc_pgu_read
	ldr	w8, [x22]
Lloh14:
	adrp	x9, _DRM_MODE_FLAG_PVSYNC@GOTPAGE
Lloh15:
	ldr	x9, [x9, _DRM_MODE_FLAG_PVSYNC@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
Lloh17:
	adrp	x10, _ARCPGU_CTRL_VS_POL_MASK@GOTPAGE
Lloh18:
	ldr	x10, [x10, _ARCPGU_CTRL_VS_POL_MASK@GOTPAGEOFF]
Lloh19:
	ldr	w10, [x10]
Lloh20:
	adrp	x11, _ARCPGU_CTRL_VS_POL_OFST@GOTPAGE
Lloh21:
	ldr	x11, [x11, _ARCPGU_CTRL_VS_POL_OFST@GOTPAGEOFF]
Lloh22:
	ldr	w11, [x11]
	lsl	w10, w10, w11
	orr	w11, w10, w0
	bic	w10, w0, w10
	tst	w9, w8
	csel	w9, w10, w11, eq
Lloh23:
	adrp	x10, _DRM_MODE_FLAG_PHSYNC@GOTPAGE
Lloh24:
	ldr	x10, [x10, _DRM_MODE_FLAG_PHSYNC@GOTPAGEOFF]
Lloh25:
	ldr	w10, [x10]
Lloh26:
	adrp	x11, _ARCPGU_CTRL_HS_POL_MASK@GOTPAGE
Lloh27:
	ldr	x11, [x11, _ARCPGU_CTRL_HS_POL_MASK@GOTPAGEOFF]
Lloh28:
	ldr	w11, [x11]
Lloh29:
	adrp	x12, _ARCPGU_CTRL_HS_POL_OFST@GOTPAGE
Lloh30:
	ldr	x12, [x12, _ARCPGU_CTRL_HS_POL_OFST@GOTPAGEOFF]
Lloh31:
	ldr	w12, [x12]
	lsl	w11, w11, w12
	orr	w12, w11, w9
	bic	w9, w9, w11
	tst	w10, w8
	csel	w2, w9, w12, eq
	ldr	w1, [x21]
	mov	x0, x20
	bl	_arc_pgu_write
Lloh32:
	adrp	x8, _ARCPGU_REG_STRIDE@GOTPAGE
Lloh33:
	ldr	x8, [x8, _ARCPGU_REG_STRIDE@GOTPAGEOFF]
Lloh34:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #0
	bl	_arc_pgu_write
Lloh35:
	adrp	x8, _ARCPGU_REG_START_SET@GOTPAGE
Lloh36:
	ldr	x8, [x8, _ARCPGU_REG_START_SET@GOTPAGEOFF]
Lloh37:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #1
	bl	_arc_pgu_write
	mov	x0, x19
	bl	_arc_pgu_set_pxl_fmt
	ldr	w0, [x20]
	ldr	w8, [x22, #4]
	mov	w9, #1000
	mul	w1, w8, w9
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_clk_set_rate
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_ARCPGU_REG_FMT,4,2             ; @ARCPGU_REG_FMT
	.comm	_ARCPGU_REG_HSYNC,4,2           ; @ARCPGU_REG_HSYNC
	.comm	_ARCPGU_REG_VSYNC,4,2           ; @ARCPGU_REG_VSYNC
	.comm	_ARCPGU_REG_ACTIVE,4,2          ; @ARCPGU_REG_ACTIVE
	.comm	_ARCPGU_REG_CTRL,4,2            ; @ARCPGU_REG_CTRL
	.comm	_DRM_MODE_FLAG_PVSYNC,4,2       ; @DRM_MODE_FLAG_PVSYNC
	.comm	_ARCPGU_CTRL_VS_POL_MASK,4,2    ; @ARCPGU_CTRL_VS_POL_MASK
	.comm	_ARCPGU_CTRL_VS_POL_OFST,4,2    ; @ARCPGU_CTRL_VS_POL_OFST
	.comm	_DRM_MODE_FLAG_PHSYNC,4,2       ; @DRM_MODE_FLAG_PHSYNC
	.comm	_ARCPGU_CTRL_HS_POL_MASK,4,2    ; @ARCPGU_CTRL_HS_POL_MASK
	.comm	_ARCPGU_CTRL_HS_POL_OFST,4,2    ; @ARCPGU_CTRL_HS_POL_OFST
	.comm	_ARCPGU_REG_STRIDE,4,2          ; @ARCPGU_REG_STRIDE
	.comm	_ARCPGU_REG_START_SET,4,2       ; @ARCPGU_REG_START_SET
	.no_dead_strip	_arc_pgu_crtc_mode_set_nofb
.subsections_via_symbols
