	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function amdgpu_ras_block_to_ta
_amdgpu_ras_block_to_ta:                ## @amdgpu_ras_block_to_ta
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movl	%edi, %edx
	leal	-128(%rdx), %eax
	cmpl	$14, %eax
	jae	LBB0_1
## %bb.2:
	cltq
	leaq	l_switch.table.amdgpu_ras_block_to_ta(%rip), %rcx
	movq	(%rcx,%rax,8), %rax
	jmp	LBB0_3
LBB0_1:
	leaq	L_.str(%rip), %rsi
	movl	$1, %edi
                                        ## kill: def $edx killed $edx killed $rdx
	callq	_WARN_ONCE
	movq	_TA_RAS_BLOCK__UMC@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %eax
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_TA_RAS_BLOCK__UMC,4,2          ## @TA_RAS_BLOCK__UMC
	.comm	_TA_RAS_BLOCK__SDMA,4,2         ## @TA_RAS_BLOCK__SDMA
	.comm	_TA_RAS_BLOCK__GFX,4,2          ## @TA_RAS_BLOCK__GFX
	.comm	_TA_RAS_BLOCK__MMHUB,4,2        ## @TA_RAS_BLOCK__MMHUB
	.comm	_TA_RAS_BLOCK__ATHUB,4,2        ## @TA_RAS_BLOCK__ATHUB
	.comm	_TA_RAS_BLOCK__PCIE_BIF,4,2     ## @TA_RAS_BLOCK__PCIE_BIF
	.comm	_TA_RAS_BLOCK__HDP,4,2          ## @TA_RAS_BLOCK__HDP
	.comm	_TA_RAS_BLOCK__XGMI_WAFL,4,2    ## @TA_RAS_BLOCK__XGMI_WAFL
	.comm	_TA_RAS_BLOCK__DF,4,2           ## @TA_RAS_BLOCK__DF
	.comm	_TA_RAS_BLOCK__SMN,4,2          ## @TA_RAS_BLOCK__SMN
	.comm	_TA_RAS_BLOCK__SEM,4,2          ## @TA_RAS_BLOCK__SEM
	.comm	_TA_RAS_BLOCK__MP0,4,2          ## @TA_RAS_BLOCK__MP0
	.comm	_TA_RAS_BLOCK__MP1,4,2          ## @TA_RAS_BLOCK__MP1
	.comm	_TA_RAS_BLOCK__FUSE,4,2         ## @TA_RAS_BLOCK__FUSE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"RAS ERROR: unexpected block id %d\n"

	.no_dead_strip	_amdgpu_ras_block_to_ta
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.amdgpu_ras_block_to_ta
l_switch.table.amdgpu_ras_block_to_ta:
	.quad	_TA_RAS_BLOCK__XGMI_WAFL
	.quad	_TA_RAS_BLOCK__UMC
	.quad	_TA_RAS_BLOCK__SMN
	.quad	_TA_RAS_BLOCK__SEM
	.quad	_TA_RAS_BLOCK__SDMA
	.quad	_TA_RAS_BLOCK__PCIE_BIF
	.quad	_TA_RAS_BLOCK__MP1
	.quad	_TA_RAS_BLOCK__MP0
	.quad	_TA_RAS_BLOCK__MMHUB
	.quad	_TA_RAS_BLOCK__HDP
	.quad	_TA_RAS_BLOCK__GFX
	.quad	_TA_RAS_BLOCK__FUSE
	.quad	_TA_RAS_BLOCK__DF
	.quad	_TA_RAS_BLOCK__ATHUB

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function amdgpu_ras_block_to_ta
_amdgpu_ras_block_to_ta:                ; @amdgpu_ras_block_to_ta
	.cfi_startproc
; %bb.0:
	stp	x29, x30, [sp, #-16]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 16
	mov	x29, sp
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	sub	w8, w0, #128
	cmp	w8, #14
	b.hs	LBB0_2
; %bb.1:
Lloh0:
	adrp	x9, l_switch.table.amdgpu_ras_block_to_ta@PAGE
Lloh1:
	add	x9, x9, l_switch.table.amdgpu_ras_block_to_ta@PAGEOFF
	ldr	x8, [x9, w8, sxtw #3]
	b	LBB0_3
LBB0_2:
	mov	x2, x0
Lloh2:
	adrp	x1, l_.str@PAGE
Lloh3:
	add	x1, x1, l_.str@PAGEOFF
	mov	w0, #1
	bl	_WARN_ONCE
Lloh4:
	adrp	x8, _TA_RAS_BLOCK__UMC@GOTPAGE
Lloh5:
	ldr	x8, [x8, _TA_RAS_BLOCK__UMC@GOTPAGEOFF]
LBB0_3:
	ldr	w0, [x8]
	ldp	x29, x30, [sp], #16             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpAdd	Lloh2, Lloh3
	.cfi_endproc
                                        ; -- End function
	.comm	_TA_RAS_BLOCK__UMC,4,2          ; @TA_RAS_BLOCK__UMC
	.comm	_TA_RAS_BLOCK__SDMA,4,2         ; @TA_RAS_BLOCK__SDMA
	.comm	_TA_RAS_BLOCK__GFX,4,2          ; @TA_RAS_BLOCK__GFX
	.comm	_TA_RAS_BLOCK__MMHUB,4,2        ; @TA_RAS_BLOCK__MMHUB
	.comm	_TA_RAS_BLOCK__ATHUB,4,2        ; @TA_RAS_BLOCK__ATHUB
	.comm	_TA_RAS_BLOCK__PCIE_BIF,4,2     ; @TA_RAS_BLOCK__PCIE_BIF
	.comm	_TA_RAS_BLOCK__HDP,4,2          ; @TA_RAS_BLOCK__HDP
	.comm	_TA_RAS_BLOCK__XGMI_WAFL,4,2    ; @TA_RAS_BLOCK__XGMI_WAFL
	.comm	_TA_RAS_BLOCK__DF,4,2           ; @TA_RAS_BLOCK__DF
	.comm	_TA_RAS_BLOCK__SMN,4,2          ; @TA_RAS_BLOCK__SMN
	.comm	_TA_RAS_BLOCK__SEM,4,2          ; @TA_RAS_BLOCK__SEM
	.comm	_TA_RAS_BLOCK__MP0,4,2          ; @TA_RAS_BLOCK__MP0
	.comm	_TA_RAS_BLOCK__MP1,4,2          ; @TA_RAS_BLOCK__MP1
	.comm	_TA_RAS_BLOCK__FUSE,4,2         ; @TA_RAS_BLOCK__FUSE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"RAS ERROR: unexpected block id %d\n"

	.no_dead_strip	_amdgpu_ras_block_to_ta
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.amdgpu_ras_block_to_ta
l_switch.table.amdgpu_ras_block_to_ta:
	.quad	_TA_RAS_BLOCK__XGMI_WAFL
	.quad	_TA_RAS_BLOCK__UMC
	.quad	_TA_RAS_BLOCK__SMN
	.quad	_TA_RAS_BLOCK__SEM
	.quad	_TA_RAS_BLOCK__SDMA
	.quad	_TA_RAS_BLOCK__PCIE_BIF
	.quad	_TA_RAS_BLOCK__MP1
	.quad	_TA_RAS_BLOCK__MP0
	.quad	_TA_RAS_BLOCK__MMHUB
	.quad	_TA_RAS_BLOCK__HDP
	.quad	_TA_RAS_BLOCK__GFX
	.quad	_TA_RAS_BLOCK__FUSE
	.quad	_TA_RAS_BLOCK__DF
	.quad	_TA_RAS_BLOCK__ATHUB

.subsections_via_symbols
