	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function si_program_aspm
_si_program_aspm:                       ## @si_program_aspm
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_amdgpu_aspm@GOTPCREL(%rip), %rax
	cmpq	$0, (%rax)
	je	LBB0_71
## %bb.1:
	movq	%rdi, %r14
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rdi)
	jne	LBB0_71
## %bb.2:
	movq	_PCIE_LC_N_FTS_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_RREG32_PCIE_PORT
	movl	%eax, %r15d
	movq	_LC_XMIT_N_FTS_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	notl	%ebx
	andl	%r15d, %ebx
	movl	$36, %edi
	callq	_LC_XMIT_N_FTS
	movq	_LC_XMIT_N_FTS_OVERRIDE_EN@GOTPCREL(%rip), %rcx
	orl	%ebx, %eax
	orl	(%rcx), %eax
	cmpl	%eax, %r15d
	je	LBB0_4
## %bb.3:
	movl	(%r12), %edi
	movl	%eax, %esi
	callq	_WREG32_PCIE_PORT
LBB0_4:
	movq	_PCIE_LC_CNTL3@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_GO_TO_RECOVERY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	%eax, %esi
	cmpl	%esi, %eax
	je	LBB0_6
## %bb.5:
	movl	(%rbx), %edi
	callq	_WREG32_PCIE_PORT
LBB0_6:
	movq	_PCIE_P_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE
	movq	_P_IGNORE_EDB_ERR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	%eax, %esi
	cmpl	%esi, %eax
	je	LBB0_8
## %bb.7:
	movl	(%rbx), %edi
	callq	_WREG32_PCIE
LBB0_8:
	movq	_PCIE_LC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PCIE_PORT
	movl	%eax, %r15d
	movq	_LC_L0S_INACTIVITY_MASK@GOTPCREL(%rip), %rcx
	movq	_LC_L1_INACTIVITY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	orl	(%rcx), %ebx
	notl	%ebx
	andl	%r15d, %ebx
	movq	_LC_PMI_TO_L1_DIS@GOTPCREL(%rip), %r13
	orl	(%r13), %ebx
	movl	$7, %edi
	callq	_LC_L0S_INACTIVITY
	movl	%eax, %r12d
	movl	$7, %edi
	callq	_LC_L1_INACTIVITY
	orl	%r12d, %eax
	orl	%ebx, %eax
	movl	(%r13), %esi
	notl	%esi
	andl	%eax, %esi
	cmpl	%esi, %r15d
	je	LBB0_10
## %bb.9:
	movq	_PCIE_LC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32_PCIE_PORT
LBB0_10:
	movq	_PB0_PIF_PWRDOWN_0@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy0_rreg
	movl	%eax, %r15d
	movq	_PLL_POWER_STATE_IN_OFF_0_MASK@GOTPCREL(%rip), %rax
	movq	_PLL_POWER_STATE_IN_TXS2_0_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	notl	%ebx
	andl	%r15d, %ebx
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_OFF_0
	movl	%eax, %r12d
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_TXS2_0
	orl	%r12d, %eax
	orl	%ebx, %eax
	cmpl	%eax, %r15d
	je	LBB0_12
## %bb.11:
	movl	(%r13), %esi
	movq	%r14, %rdi
	movl	%eax, %edx
	callq	_si_pif_phy0_wreg
LBB0_12:
	movq	_PB0_PIF_PWRDOWN_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy0_rreg
	movl	%eax, %r15d
	movq	_PLL_POWER_STATE_IN_OFF_1_MASK@GOTPCREL(%rip), %rax
	movq	_PLL_POWER_STATE_IN_TXS2_1_MASK@GOTPCREL(%rip), %r12
	movl	(%r12), %r13d
	orl	(%rax), %r13d
	notl	%r13d
	andl	%r15d, %r13d
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_OFF_1
	movl	%eax, %ebx
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_TXS2_1
	orl	%ebx, %eax
	orl	%r13d, %eax
	cmpl	%eax, %r15d
	je	LBB0_14
## %bb.13:
	movq	_PB0_PIF_PWRDOWN_1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	%r14, %rdi
	movl	%eax, %edx
	callq	_si_pif_phy0_wreg
LBB0_14:
	movq	_PB1_PIF_PWRDOWN_0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy1_rreg
	movl	%eax, %r13d
	movq	_PLL_POWER_STATE_IN_TXS2_0_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_PLL_POWER_STATE_IN_OFF_0_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	notl	%ebx
	andl	%r13d, %ebx
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_OFF_0
	movl	%eax, %r15d
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_TXS2_0
	orl	%r15d, %eax
	orl	%ebx, %eax
	cmpl	%eax, %r13d
	je	LBB0_16
## %bb.15:
	movq	_PB1_PIF_PWRDOWN_0@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	%r14, %rdi
	movl	%eax, %edx
	callq	_si_pif_phy1_wreg
LBB0_16:
	movq	_PB1_PIF_PWRDOWN_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy1_rreg
	movl	%eax, %r13d
	movl	(%r12), %ebx
	movq	_PLL_POWER_STATE_IN_OFF_1_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	notl	%ebx
	andl	%r13d, %ebx
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_OFF_1
	movl	%eax, %r15d
	movl	$7, %edi
	callq	_PLL_POWER_STATE_IN_TXS2_1
	orl	%r15d, %eax
	orl	%ebx, %eax
	cmpl	%eax, %r13d
	je	LBB0_18
## %bb.17:
	movq	_PB1_PIF_PWRDOWN_1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	%r14, %rdi
	movl	%eax, %edx
	callq	_si_pif_phy1_wreg
LBB0_18:
	movq	8(%r14), %rax
	movq	_CHIP_OLAND@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	movq	_PB0_PIF_PWRDOWN_0@GOTPCREL(%rip), %rbx
	je	LBB0_36
## %bb.19:
	movq	_CHIP_HAINAN@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_36
## %bb.20:
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy0_rreg
	movq	_PLL_RAMP_UP_TIME_0_MASK@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	notl	%edx
	andl	%eax, %edx
	cmpl	%edx, %eax
	je	LBB0_22
## %bb.21:
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy0_wreg
LBB0_22:
	movq	_PB0_PIF_PWRDOWN_1@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy0_rreg
	movq	_PLL_RAMP_UP_TIME_1_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	cmpl	%edx, %eax
	je	LBB0_24
## %bb.23:
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy0_wreg
LBB0_24:
	movq	_PB0_PIF_PWRDOWN_2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy0_rreg
	movq	_PLL_RAMP_UP_TIME_2_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	cmpl	%edx, %eax
	je	LBB0_26
## %bb.25:
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy0_wreg
LBB0_26:
	movq	_PB0_PIF_PWRDOWN_3@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy0_rreg
	movq	_PLL_RAMP_UP_TIME_3_MASK@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	notl	%edx
	andl	%eax, %edx
	cmpl	%edx, %eax
	je	LBB0_28
## %bb.27:
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy0_wreg
LBB0_28:
	movq	_PB1_PIF_PWRDOWN_0@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy1_rreg
	movl	(%r13), %edx
	notl	%edx
	andl	%eax, %edx
	cmpl	%edx, %eax
	je	LBB0_30
## %bb.29:
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy1_wreg
LBB0_30:
	movq	_PB1_PIF_PWRDOWN_1@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy1_rreg
	movq	_PLL_RAMP_UP_TIME_1_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	cmpl	%edx, %eax
	je	LBB0_32
## %bb.31:
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy1_wreg
LBB0_32:
	movq	_PB1_PIF_PWRDOWN_2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy1_rreg
	movq	_PLL_RAMP_UP_TIME_2_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	cmpl	%edx, %eax
	je	LBB0_34
## %bb.33:
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy1_wreg
LBB0_34:
	movq	_PB1_PIF_PWRDOWN_3@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy1_rreg
	movl	(%r12), %edx
	notl	%edx
	andl	%eax, %edx
	cmpl	%edx, %eax
	je	LBB0_36
## %bb.35:
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy1_wreg
LBB0_36:
	movq	_PCIE_LC_LINK_WIDTH_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32_PCIE_PORT
	movl	%eax, %r12d
	movq	_LC_DYN_LANES_PWR_STATE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	notl	%ebx
	andl	%r12d, %ebx
	movl	$3, %edi
	callq	_LC_DYN_LANES_PWR_STATE
	orl	%ebx, %eax
	cmpl	%eax, %r12d
	je	LBB0_38
## %bb.37:
	movl	(%r15), %edi
	movl	%eax, %esi
	callq	_WREG32_PCIE_PORT
LBB0_38:
	movq	_PB0_PIF_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy0_rreg
	movl	%eax, %r15d
	movq	_LS2_EXIT_TIME_MASK@GOTPCREL(%rip), %r12
	movl	(%r12), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movq	8(%r14), %rax
	movq	_CHIP_OLAND@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_40
## %bb.39:
	movq	_CHIP_HAINAN@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_41
LBB0_40:
	movl	$5, %edi
	callq	_LS2_EXIT_TIME
	orl	%eax, %ebx
LBB0_41:
	cmpl	%ebx, %r15d
	je	LBB0_43
## %bb.42:
	movl	(%r13), %esi
	movq	%r14, %rdi
	movl	%ebx, %edx
	callq	_si_pif_phy0_wreg
LBB0_43:
	movq	_PB1_PIF_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%r14, %rdi
	callq	_si_pif_phy1_rreg
	movl	%eax, %r15d
	movl	(%r12), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movq	8(%r14), %rax
	movq	_CHIP_OLAND@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_45
## %bb.44:
	movq	_CHIP_HAINAN@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_46
LBB0_45:
	movl	$5, %edi
	callq	_LS2_EXIT_TIME
	orl	%eax, %ebx
LBB0_46:
	cmpl	%ebx, %r15d
	je	LBB0_48
## %bb.47:
	movl	(%r13), %esi
	movq	%r14, %rdi
	movl	%ebx, %edx
	callq	_si_pif_phy1_wreg
LBB0_48:
	movq	16(%r14), %rax
	movq	(%rax), %rdi
	callq	_pci_is_root_bus
	testl	%eax, %eax
	movq	_PCIE_LC_N_FTS_CNTL@GOTPCREL(%rip), %r13
	je	LBB0_49
LBB0_64:
	movq	_PCIE_CNTL2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE
	movq	_SLV_MEM_LS_EN@GOTPCREL(%rip), %rcx
	movq	_MST_MEM_LS_EN@GOTPCREL(%rip), %rdx
	movl	(%rcx), %esi
	orl	%eax, %esi
	orl	(%rdx), %esi
	movq	_REPLAY_MEM_LS_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	cmpl	%esi, %eax
	je	LBB0_66
## %bb.65:
	movl	(%rbx), %edi
	callq	_WREG32_PCIE
LBB0_66:
	movl	(%r13), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_N_FTS_MASK@GOTPCREL(%rip), %rcx
	notl	%eax
	testl	%eax, (%rcx)
	jne	LBB0_71
## %bb.67:
	movq	_PCIE_LC_STATUS1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PCIE
	movq	_LC_REVERSE_XMIT@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_71
## %bb.68:
	movq	_LC_REVERSE_RCVR@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_71
## %bb.69:
	movq	_PCIE_LC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_L0S_INACTIVITY_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	cmpl	%esi, %eax
	je	LBB0_71
## %bb.70:
	movq	_PCIE_LC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32_PCIE_PORT
LBB0_71:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_49:
	movq	16(%r14), %rax
	movq	(%rax), %rax
	movq	(%rax), %rdi
	movq	_PCI_EXP_LNKCAP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-44(%rbp), %rdx
	callq	_pcie_capability_read_dword
	movq	_PCI_EXP_LNKCAP_CLKPM@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	-44(%rbp), %eax
	je	LBB0_64
## %bb.50:
	movq	_PCIE_LC_CNTL2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_ALLOW_PDWN_IN_L1@GOTPCREL(%rip), %rcx
	movq	_LC_ALLOW_PDWN_IN_L23@GOTPCREL(%rip), %rdx
	movl	(%rcx), %esi
	orl	%eax, %esi
	orl	(%rdx), %esi
	cmpl	%esi, %eax
	je	LBB0_52
## %bb.51:
	movl	(%rbx), %edi
	callq	_WREG32_PCIE_PORT
LBB0_52:
	movq	_THM_CLK_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32
	movl	%eax, %r14d
	movq	_CMON_CLK_SEL_MASK@GOTPCREL(%rip), %rax
	movq	_TMON_CLK_SEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	notl	%ebx
	andl	%r14d, %ebx
	movl	$1, %edi
	callq	_CMON_CLK_SEL
	movl	%eax, %r12d
	movl	$1, %edi
	callq	_TMON_CLK_SEL
	orl	%r12d, %eax
	orl	%ebx, %eax
	cmpl	%eax, %r14d
	je	LBB0_54
## %bb.53:
	movl	(%r15), %edi
	movl	%eax, %esi
	callq	_WREG32
LBB0_54:
	movq	_MISC_CLK_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32
	movl	%eax, %r14d
	movq	_DEEP_SLEEP_CLK_SEL_MASK@GOTPCREL(%rip), %rax
	movq	_ZCLK_SEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	notl	%ebx
	andl	%r14d, %ebx
	movl	$1, %edi
	callq	_DEEP_SLEEP_CLK_SEL
	movl	%eax, %r12d
	movl	$1, %edi
	callq	_ZCLK_SEL
	orl	%r12d, %eax
	orl	%ebx, %eax
	cmpl	%eax, %r14d
	je	LBB0_56
## %bb.55:
	movl	(%r15), %edi
	movl	%eax, %esi
	callq	_WREG32
LBB0_56:
	movq	_CG_CLKPIN_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_BCLK_AS_XCLK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	cmpl	%esi, %eax
	je	LBB0_58
## %bb.57:
	movl	(%rbx), %edi
	callq	_WREG32
LBB0_58:
	movq	_CG_CLKPIN_CNTL_2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_FORCE_BIF_REFCLK_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	cmpl	%esi, %eax
	je	LBB0_60
## %bb.59:
	movl	(%rbx), %edi
	callq	_WREG32
LBB0_60:
	movq	_MPLL_BYPASSCLK_SEL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32
	movl	%eax, %r15d
	movq	_MPLL_CLKOUT_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	notl	%ebx
	andl	%r15d, %ebx
	movl	$4, %edi
	callq	_MPLL_CLKOUT_SEL
	orl	%ebx, %eax
	cmpl	%eax, %r15d
	je	LBB0_62
## %bb.61:
	movl	(%r14), %edi
	movl	%eax, %esi
	callq	_WREG32
LBB0_62:
	movq	_SPLL_CNTL_MODE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_SPLL_REFCLK_SEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	cmpl	%esi, %eax
	je	LBB0_64
## %bb.63:
	movl	(%rbx), %edi
	callq	_WREG32
	jmp	LBB0_64
	.cfi_endproc
                                        ## -- End function
	.comm	_amdgpu_aspm,8,3                ## @amdgpu_aspm
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_PCIE_LC_N_FTS_CNTL,4,2         ## @PCIE_LC_N_FTS_CNTL
	.comm	_LC_XMIT_N_FTS_MASK,4,2         ## @LC_XMIT_N_FTS_MASK
	.comm	_LC_XMIT_N_FTS_OVERRIDE_EN,4,2  ## @LC_XMIT_N_FTS_OVERRIDE_EN
	.comm	_PCIE_LC_CNTL3,4,2              ## @PCIE_LC_CNTL3
	.comm	_LC_GO_TO_RECOVERY,4,2          ## @LC_GO_TO_RECOVERY
	.comm	_PCIE_P_CNTL,4,2                ## @PCIE_P_CNTL
	.comm	_P_IGNORE_EDB_ERR,4,2           ## @P_IGNORE_EDB_ERR
	.comm	_PCIE_LC_CNTL,4,2               ## @PCIE_LC_CNTL
	.comm	_LC_L0S_INACTIVITY_MASK,4,2     ## @LC_L0S_INACTIVITY_MASK
	.comm	_LC_L1_INACTIVITY_MASK,4,2      ## @LC_L1_INACTIVITY_MASK
	.comm	_LC_PMI_TO_L1_DIS,4,2           ## @LC_PMI_TO_L1_DIS
	.comm	_PB0_PIF_PWRDOWN_0,4,2          ## @PB0_PIF_PWRDOWN_0
	.comm	_PLL_POWER_STATE_IN_OFF_0_MASK,4,2 ## @PLL_POWER_STATE_IN_OFF_0_MASK
	.comm	_PLL_POWER_STATE_IN_TXS2_0_MASK,4,2 ## @PLL_POWER_STATE_IN_TXS2_0_MASK
	.comm	_PB0_PIF_PWRDOWN_1,4,2          ## @PB0_PIF_PWRDOWN_1
	.comm	_PLL_POWER_STATE_IN_OFF_1_MASK,4,2 ## @PLL_POWER_STATE_IN_OFF_1_MASK
	.comm	_PLL_POWER_STATE_IN_TXS2_1_MASK,4,2 ## @PLL_POWER_STATE_IN_TXS2_1_MASK
	.comm	_PB1_PIF_PWRDOWN_0,4,2          ## @PB1_PIF_PWRDOWN_0
	.comm	_PB1_PIF_PWRDOWN_1,4,2          ## @PB1_PIF_PWRDOWN_1
	.comm	_CHIP_OLAND,8,3                 ## @CHIP_OLAND
	.comm	_CHIP_HAINAN,8,3                ## @CHIP_HAINAN
	.comm	_PLL_RAMP_UP_TIME_0_MASK,4,2    ## @PLL_RAMP_UP_TIME_0_MASK
	.comm	_PLL_RAMP_UP_TIME_1_MASK,4,2    ## @PLL_RAMP_UP_TIME_1_MASK
	.comm	_PB0_PIF_PWRDOWN_2,4,2          ## @PB0_PIF_PWRDOWN_2
	.comm	_PLL_RAMP_UP_TIME_2_MASK,4,2    ## @PLL_RAMP_UP_TIME_2_MASK
	.comm	_PB0_PIF_PWRDOWN_3,4,2          ## @PB0_PIF_PWRDOWN_3
	.comm	_PLL_RAMP_UP_TIME_3_MASK,4,2    ## @PLL_RAMP_UP_TIME_3_MASK
	.comm	_PB1_PIF_PWRDOWN_2,4,2          ## @PB1_PIF_PWRDOWN_2
	.comm	_PB1_PIF_PWRDOWN_3,4,2          ## @PB1_PIF_PWRDOWN_3
	.comm	_PCIE_LC_LINK_WIDTH_CNTL,4,2    ## @PCIE_LC_LINK_WIDTH_CNTL
	.comm	_LC_DYN_LANES_PWR_STATE_MASK,4,2 ## @LC_DYN_LANES_PWR_STATE_MASK
	.comm	_PB0_PIF_CNTL,4,2               ## @PB0_PIF_CNTL
	.comm	_LS2_EXIT_TIME_MASK,4,2         ## @LS2_EXIT_TIME_MASK
	.comm	_PB1_PIF_CNTL,4,2               ## @PB1_PIF_CNTL
	.comm	_PCI_EXP_LNKCAP,4,2             ## @PCI_EXP_LNKCAP
	.comm	_PCI_EXP_LNKCAP_CLKPM,4,2       ## @PCI_EXP_LNKCAP_CLKPM
	.comm	_PCIE_LC_CNTL2,4,2              ## @PCIE_LC_CNTL2
	.comm	_LC_ALLOW_PDWN_IN_L1,4,2        ## @LC_ALLOW_PDWN_IN_L1
	.comm	_LC_ALLOW_PDWN_IN_L23,4,2       ## @LC_ALLOW_PDWN_IN_L23
	.comm	_THM_CLK_CNTL,4,2               ## @THM_CLK_CNTL
	.comm	_CMON_CLK_SEL_MASK,4,2          ## @CMON_CLK_SEL_MASK
	.comm	_TMON_CLK_SEL_MASK,4,2          ## @TMON_CLK_SEL_MASK
	.comm	_MISC_CLK_CNTL,4,2              ## @MISC_CLK_CNTL
	.comm	_DEEP_SLEEP_CLK_SEL_MASK,4,2    ## @DEEP_SLEEP_CLK_SEL_MASK
	.comm	_ZCLK_SEL_MASK,4,2              ## @ZCLK_SEL_MASK
	.comm	_CG_CLKPIN_CNTL,4,2             ## @CG_CLKPIN_CNTL
	.comm	_BCLK_AS_XCLK,4,2               ## @BCLK_AS_XCLK
	.comm	_CG_CLKPIN_CNTL_2,4,2           ## @CG_CLKPIN_CNTL_2
	.comm	_FORCE_BIF_REFCLK_EN,4,2        ## @FORCE_BIF_REFCLK_EN
	.comm	_MPLL_BYPASSCLK_SEL,4,2         ## @MPLL_BYPASSCLK_SEL
	.comm	_MPLL_CLKOUT_SEL_MASK,4,2       ## @MPLL_CLKOUT_SEL_MASK
	.comm	_SPLL_CNTL_MODE,4,2             ## @SPLL_CNTL_MODE
	.comm	_SPLL_REFCLK_SEL_MASK,4,2       ## @SPLL_REFCLK_SEL_MASK
	.comm	_PCIE_CNTL2,4,2                 ## @PCIE_CNTL2
	.comm	_SLV_MEM_LS_EN,4,2              ## @SLV_MEM_LS_EN
	.comm	_MST_MEM_LS_EN,4,2              ## @MST_MEM_LS_EN
	.comm	_REPLAY_MEM_LS_EN,4,2           ## @REPLAY_MEM_LS_EN
	.comm	_LC_N_FTS_MASK,4,2              ## @LC_N_FTS_MASK
	.comm	_PCIE_LC_STATUS1,4,2            ## @PCIE_LC_STATUS1
	.comm	_LC_REVERSE_XMIT,4,2            ## @LC_REVERSE_XMIT
	.comm	_LC_REVERSE_RCVR,4,2            ## @LC_REVERSE_RCVR
	.no_dead_strip	_si_program_aspm
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function si_program_aspm
_si_program_aspm:                       ; @si_program_aspm
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
Lloh0:
	adrp	x8, _amdgpu_aspm@GOTPAGE
Lloh1:
	ldr	x8, [x8, _amdgpu_aspm@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	cbz	x8, LBB0_56
; %bb.1:
	mov	x19, x0
	ldr	w8, [x0]
Lloh3:
	adrp	x9, _AMD_IS_APU@GOTPAGE
Lloh4:
	ldr	x9, [x9, _AMD_IS_APU@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_56
; %bb.2:
Lloh6:
	adrp	x22, _PCIE_LC_N_FTS_CNTL@GOTPAGE
Lloh7:
	ldr	x22, [x22, _PCIE_LC_N_FTS_CNTL@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_RREG32_PCIE_PORT
	mov	x20, x0
Lloh8:
	adrp	x8, _LC_XMIT_N_FTS_MASK@GOTPAGE
Lloh9:
	ldr	x8, [x8, _LC_XMIT_N_FTS_MASK@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	bic	w21, w0, w8
	mov	w0, #36
	bl	_LC_XMIT_N_FTS
Lloh11:
	adrp	x8, _LC_XMIT_N_FTS_OVERRIDE_EN@GOTPAGE
Lloh12:
	ldr	x8, [x8, _LC_XMIT_N_FTS_OVERRIDE_EN@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
	orr	w9, w21, w0
	orr	w1, w9, w8
	cmp	w20, w1
	b.eq	LBB0_4
; %bb.3:
	ldr	w0, [x22]
	bl	_WREG32_PCIE_PORT
LBB0_4:
Lloh14:
	adrp	x20, _PCIE_LC_CNTL3@GOTPAGE
Lloh15:
	ldr	x20, [x20, _PCIE_LC_CNTL3@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PCIE_PORT
Lloh16:
	adrp	x8, _LC_GO_TO_RECOVERY@GOTPAGE
Lloh17:
	ldr	x8, [x8, _LC_GO_TO_RECOVERY@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	orr	w1, w8, w0
	cmp	w0, w1
	b.eq	LBB0_6
; %bb.5:
	ldr	w0, [x20]
	bl	_WREG32_PCIE_PORT
LBB0_6:
Lloh19:
	adrp	x20, _PCIE_P_CNTL@GOTPAGE
Lloh20:
	ldr	x20, [x20, _PCIE_P_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PCIE
Lloh21:
	adrp	x8, _P_IGNORE_EDB_ERR@GOTPAGE
Lloh22:
	ldr	x8, [x8, _P_IGNORE_EDB_ERR@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	orr	w1, w8, w0
	cmp	w0, w1
	b.eq	LBB0_8
; %bb.7:
	ldr	w0, [x20]
	bl	_WREG32_PCIE
LBB0_8:
Lloh24:
	adrp	x23, _PCIE_LC_CNTL@GOTPAGE
Lloh25:
	ldr	x23, [x23, _PCIE_LC_CNTL@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32_PCIE_PORT
	mov	x20, x0
Lloh26:
	adrp	x8, _LC_L0S_INACTIVITY_MASK@GOTPAGE
Lloh27:
	ldr	x8, [x8, _LC_L0S_INACTIVITY_MASK@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
Lloh29:
	adrp	x9, _LC_L1_INACTIVITY_MASK@GOTPAGE
Lloh30:
	ldr	x9, [x9, _LC_L1_INACTIVITY_MASK@GOTPAGEOFF]
Lloh31:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
Lloh32:
	adrp	x21, _LC_PMI_TO_L1_DIS@GOTPAGE
Lloh33:
	ldr	x21, [x21, _LC_PMI_TO_L1_DIS@GOTPAGEOFF]
	ldr	w9, [x21]
	orr	w22, w8, w9
	mov	w0, #7
	bl	_LC_L0S_INACTIVITY
	orr	w22, w22, w0
	mov	w0, #7
	bl	_LC_L1_INACTIVITY
	orr	w8, w22, w0
	ldr	w9, [x21]
	bic	w1, w8, w9
	cmp	w20, w1
	b.eq	LBB0_10
; %bb.9:
	ldr	w0, [x23]
	bl	_WREG32_PCIE_PORT
LBB0_10:
Lloh34:
	adrp	x28, _PB0_PIF_PWRDOWN_0@GOTPAGE
Lloh35:
	ldr	x28, [x28, _PB0_PIF_PWRDOWN_0@GOTPAGEOFF]
	ldr	w1, [x28]
	mov	x0, x19
	bl	_si_pif_phy0_rreg
	mov	x20, x0
Lloh36:
	adrp	x24, _PLL_POWER_STATE_IN_OFF_0_MASK@GOTPAGE
Lloh37:
	ldr	x24, [x24, _PLL_POWER_STATE_IN_OFF_0_MASK@GOTPAGEOFF]
	ldr	w8, [x24]
Lloh38:
	adrp	x25, _PLL_POWER_STATE_IN_TXS2_0_MASK@GOTPAGE
Lloh39:
	ldr	x25, [x25, _PLL_POWER_STATE_IN_TXS2_0_MASK@GOTPAGEOFF]
	ldr	w9, [x25]
	orr	w8, w9, w8
	bic	w22, w0, w8
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_OFF_0
	mov	x21, x0
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_TXS2_0
	orr	w8, w0, w21
	orr	w2, w8, w22
	cmp	w20, w2
	b.eq	LBB0_12
; %bb.11:
	ldr	w1, [x28]
	mov	x0, x19
	bl	_si_pif_phy0_wreg
LBB0_12:
Lloh40:
	adrp	x23, _PB0_PIF_PWRDOWN_1@GOTPAGE
Lloh41:
	ldr	x23, [x23, _PB0_PIF_PWRDOWN_1@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x19
	bl	_si_pif_phy0_rreg
	mov	x20, x0
Lloh42:
	adrp	x26, _PLL_POWER_STATE_IN_OFF_1_MASK@GOTPAGE
Lloh43:
	ldr	x26, [x26, _PLL_POWER_STATE_IN_OFF_1_MASK@GOTPAGEOFF]
	ldr	w8, [x26]
Lloh44:
	adrp	x22, _PLL_POWER_STATE_IN_TXS2_1_MASK@GOTPAGE
Lloh45:
	ldr	x22, [x22, _PLL_POWER_STATE_IN_TXS2_1_MASK@GOTPAGEOFF]
	ldr	w9, [x22]
	orr	w8, w9, w8
	bic	w27, w0, w8
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_OFF_1
	mov	x21, x0
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_TXS2_1
	orr	w8, w0, w21
	orr	w2, w8, w27
	cmp	w20, w2
	b.eq	LBB0_14
; %bb.13:
	ldr	w1, [x23]
	mov	x0, x19
	bl	_si_pif_phy0_wreg
LBB0_14:
Lloh46:
	adrp	x27, _PB1_PIF_PWRDOWN_0@GOTPAGE
Lloh47:
	ldr	x27, [x27, _PB1_PIF_PWRDOWN_0@GOTPAGEOFF]
	ldr	w1, [x27]
	mov	x0, x19
	bl	_si_pif_phy1_rreg
	mov	x20, x0
	ldr	w8, [x24]
	ldr	w9, [x25]
	orr	w8, w9, w8
	bic	w24, w0, w8
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_OFF_0
	mov	x21, x0
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_TXS2_0
	orr	w8, w0, w21
	orr	w2, w8, w24
	cmp	w20, w2
	b.eq	LBB0_16
; %bb.15:
	ldr	w1, [x27]
	mov	x0, x19
	bl	_si_pif_phy1_wreg
LBB0_16:
Lloh48:
	adrp	x24, _PB1_PIF_PWRDOWN_1@GOTPAGE
Lloh49:
	ldr	x24, [x24, _PB1_PIF_PWRDOWN_1@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	x0, x19
	bl	_si_pif_phy1_rreg
	mov	x20, x0
	ldr	w8, [x26]
	ldr	w9, [x22]
	orr	w8, w9, w8
	bic	w22, w0, w8
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_OFF_1
	mov	x21, x0
	mov	w0, #7
	bl	_PLL_POWER_STATE_IN_TXS2_1
	orr	w8, w0, w21
	orr	w2, w8, w22
	cmp	w20, w2
	b.eq	LBB0_18
; %bb.17:
	ldr	w1, [x24]
	mov	x0, x19
	bl	_si_pif_phy1_wreg
LBB0_18:
	ldr	x8, [x19, #8]
Lloh50:
	adrp	x26, _CHIP_OLAND@GOTPAGE
Lloh51:
	ldr	x26, [x26, _CHIP_OLAND@GOTPAGEOFF]
	ldr	x9, [x26]
Lloh52:
	adrp	x25, _CHIP_HAINAN@GOTPAGE
Lloh53:
	ldr	x25, [x25, _CHIP_HAINAN@GOTPAGEOFF]
	cmp	x8, x9
	b.eq	LBB0_36
; %bb.19:
	ldr	x9, [x25]
	cmp	x8, x9
	b.eq	LBB0_36
; %bb.20:
	ldr	w1, [x28]
	mov	x0, x19
	bl	_si_pif_phy0_rreg
Lloh54:
	adrp	x20, _PLL_RAMP_UP_TIME_0_MASK@GOTPAGE
Lloh55:
	ldr	x20, [x20, _PLL_RAMP_UP_TIME_0_MASK@GOTPAGEOFF]
	ldr	w8, [x20]
	bic	w2, w0, w8
	cmp	w0, w2
	b.eq	LBB0_22
; %bb.21:
	ldr	w1, [x28]
	mov	x0, x19
	bl	_si_pif_phy0_wreg
LBB0_22:
	ldr	w1, [x23]
	mov	x0, x19
	bl	_si_pif_phy0_rreg
Lloh56:
	adrp	x21, _PLL_RAMP_UP_TIME_1_MASK@GOTPAGE
Lloh57:
	ldr	x21, [x21, _PLL_RAMP_UP_TIME_1_MASK@GOTPAGEOFF]
	ldr	w8, [x21]
	bic	w2, w0, w8
	cmp	w0, w2
	b.eq	LBB0_24
; %bb.23:
	ldr	w1, [x23]
	mov	x0, x19
	bl	_si_pif_phy0_wreg
LBB0_24:
Lloh58:
	adrp	x22, _PB0_PIF_PWRDOWN_2@GOTPAGE
Lloh59:
	ldr	x22, [x22, _PB0_PIF_PWRDOWN_2@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x19
	bl	_si_pif_phy0_rreg
Lloh60:
	adrp	x23, _PLL_RAMP_UP_TIME_2_MASK@GOTPAGE
Lloh61:
	ldr	x23, [x23, _PLL_RAMP_UP_TIME_2_MASK@GOTPAGEOFF]
	ldr	w8, [x23]
	bic	w2, w0, w8
	cmp	w0, w2
	b.eq	LBB0_26
; %bb.25:
	ldr	w1, [x22]
	mov	x0, x19
	bl	_si_pif_phy0_wreg
LBB0_26:
Lloh62:
	adrp	x22, _PB0_PIF_PWRDOWN_3@GOTPAGE
Lloh63:
	ldr	x22, [x22, _PB0_PIF_PWRDOWN_3@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x19
	bl	_si_pif_phy0_rreg
Lloh64:
	adrp	x28, _PLL_RAMP_UP_TIME_3_MASK@GOTPAGE
Lloh65:
	ldr	x28, [x28, _PLL_RAMP_UP_TIME_3_MASK@GOTPAGEOFF]
	ldr	w8, [x28]
	bic	w2, w0, w8
	cmp	w0, w2
	b.eq	LBB0_28
; %bb.27:
	ldr	w1, [x22]
	mov	x0, x19
	bl	_si_pif_phy0_wreg
LBB0_28:
	ldr	w1, [x27]
	mov	x0, x19
	bl	_si_pif_phy1_rreg
	ldr	w8, [x20]
	bic	w2, w0, w8
	cmp	w0, w2
	b.eq	LBB0_30
; %bb.29:
	ldr	w1, [x27]
	mov	x0, x19
	bl	_si_pif_phy1_wreg
LBB0_30:
	ldr	w1, [x24]
	mov	x0, x19
	bl	_si_pif_phy1_rreg
	ldr	w8, [x21]
	bic	w2, w0, w8
	cmp	w0, w2
	b.eq	LBB0_32
; %bb.31:
	ldr	w1, [x24]
	mov	x0, x19
	bl	_si_pif_phy1_wreg
LBB0_32:
Lloh66:
	adrp	x20, _PB1_PIF_PWRDOWN_2@GOTPAGE
Lloh67:
	ldr	x20, [x20, _PB1_PIF_PWRDOWN_2@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_si_pif_phy1_rreg
	ldr	w8, [x23]
	bic	w2, w0, w8
	cmp	w0, w2
	b.eq	LBB0_34
; %bb.33:
	ldr	w1, [x20]
	mov	x0, x19
	bl	_si_pif_phy1_wreg
LBB0_34:
Lloh68:
	adrp	x20, _PB1_PIF_PWRDOWN_3@GOTPAGE
Lloh69:
	ldr	x20, [x20, _PB1_PIF_PWRDOWN_3@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_si_pif_phy1_rreg
	ldr	w8, [x28]
	bic	w2, w0, w8
	cmp	w0, w2
	b.eq	LBB0_36
; %bb.35:
	ldr	w1, [x20]
	mov	x0, x19
	bl	_si_pif_phy1_wreg
LBB0_36:
Lloh70:
	adrp	x21, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGE
Lloh71:
	ldr	x21, [x21, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32_PCIE_PORT
	mov	x20, x0
Lloh72:
	adrp	x8, _LC_DYN_LANES_PWR_STATE_MASK@GOTPAGE
Lloh73:
	ldr	x8, [x8, _LC_DYN_LANES_PWR_STATE_MASK@GOTPAGEOFF]
Lloh74:
	ldr	w8, [x8]
	bic	w22, w0, w8
	mov	w0, #3
	bl	_LC_DYN_LANES_PWR_STATE
	orr	w1, w22, w0
	cmp	w20, w1
	b.eq	LBB0_38
; %bb.37:
	ldr	w0, [x21]
	bl	_WREG32_PCIE_PORT
LBB0_38:
Lloh75:
	adrp	x23, _PB0_PIF_CNTL@GOTPAGE
Lloh76:
	ldr	x23, [x23, _PB0_PIF_CNTL@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x19
	bl	_si_pif_phy0_rreg
	mov	x21, x0
Lloh77:
	adrp	x22, _LS2_EXIT_TIME_MASK@GOTPAGE
Lloh78:
	ldr	x22, [x22, _LS2_EXIT_TIME_MASK@GOTPAGEOFF]
	ldr	w8, [x22]
	bic	w20, w0, w8
	ldr	x8, [x19, #8]
	ldr	x9, [x26]
	cmp	x8, x9
	b.eq	LBB0_40
; %bb.39:
	ldr	x9, [x25]
	cmp	x8, x9
	b.ne	LBB0_41
LBB0_40:
	mov	w0, #5
	bl	_LS2_EXIT_TIME
	orr	w20, w0, w20
LBB0_41:
	cmp	w21, w20
	b.eq	LBB0_43
; %bb.42:
	ldr	w1, [x23]
	mov	x0, x19
	mov	x2, x20
	bl	_si_pif_phy0_wreg
LBB0_43:
Lloh79:
	adrp	x23, _PB1_PIF_CNTL@GOTPAGE
Lloh80:
	ldr	x23, [x23, _PB1_PIF_CNTL@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x19
	bl	_si_pif_phy1_rreg
	mov	x21, x0
	ldr	w8, [x22]
	bic	w20, w0, w8
	ldr	x8, [x19, #8]
	ldr	x9, [x26]
	cmp	x8, x9
	b.eq	LBB0_45
; %bb.44:
	ldr	x9, [x25]
	cmp	x8, x9
	b.ne	LBB0_46
LBB0_45:
	mov	w0, #5
	bl	_LS2_EXIT_TIME
	orr	w20, w0, w20
LBB0_46:
	cmp	w21, w20
	b.eq	LBB0_48
; %bb.47:
	ldr	w1, [x23]
	mov	x0, x19
	mov	x2, x20
	bl	_si_pif_phy1_wreg
LBB0_48:
	ldr	x8, [x19, #16]
	ldr	x0, [x8]
	bl	_pci_is_root_bus
Lloh81:
	adrp	x23, _PCIE_LC_N_FTS_CNTL@GOTPAGE
Lloh82:
	ldr	x23, [x23, _PCIE_LC_N_FTS_CNTL@GOTPAGEOFF]
	cbz	w0, LBB0_57
LBB0_49:
Lloh83:
	adrp	x19, _PCIE_CNTL2@GOTPAGE
Lloh84:
	ldr	x19, [x19, _PCIE_CNTL2@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PCIE
Lloh85:
	adrp	x8, _SLV_MEM_LS_EN@GOTPAGE
Lloh86:
	ldr	x8, [x8, _SLV_MEM_LS_EN@GOTPAGEOFF]
Lloh87:
	ldr	w8, [x8]
Lloh88:
	adrp	x9, _MST_MEM_LS_EN@GOTPAGE
Lloh89:
	ldr	x9, [x9, _MST_MEM_LS_EN@GOTPAGEOFF]
Lloh90:
	adrp	x10, _REPLAY_MEM_LS_EN@GOTPAGE
Lloh91:
	ldr	x10, [x10, _REPLAY_MEM_LS_EN@GOTPAGEOFF]
Lloh92:
	ldr	w9, [x9]
Lloh93:
	ldr	w10, [x10]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w1, w8, w10
	cmp	w0, w1
	b.eq	LBB0_51
; %bb.50:
	ldr	w0, [x19]
	bl	_WREG32_PCIE
LBB0_51:
	ldr	w0, [x23]
	bl	_RREG32_PCIE_PORT
Lloh94:
	adrp	x8, _LC_N_FTS_MASK@GOTPAGE
Lloh95:
	ldr	x8, [x8, _LC_N_FTS_MASK@GOTPAGEOFF]
Lloh96:
	ldr	w8, [x8]
	bics	wzr, w8, w0
	b.ne	LBB0_56
; %bb.52:
Lloh97:
	adrp	x8, _PCIE_LC_STATUS1@GOTPAGE
Lloh98:
	ldr	x8, [x8, _PCIE_LC_STATUS1@GOTPAGEOFF]
Lloh99:
	ldr	w0, [x8]
	bl	_RREG32_PCIE
Lloh100:
	adrp	x8, _LC_REVERSE_XMIT@GOTPAGE
Lloh101:
	ldr	x8, [x8, _LC_REVERSE_XMIT@GOTPAGEOFF]
Lloh102:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_56
; %bb.53:
Lloh103:
	adrp	x8, _LC_REVERSE_RCVR@GOTPAGE
Lloh104:
	ldr	x8, [x8, _LC_REVERSE_RCVR@GOTPAGEOFF]
Lloh105:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_56
; %bb.54:
Lloh106:
	adrp	x8, _PCIE_LC_CNTL@GOTPAGE
Lloh107:
	ldr	x8, [x8, _PCIE_LC_CNTL@GOTPAGEOFF]
Lloh108:
	ldr	w0, [x8]
	bl	_RREG32_PCIE_PORT
Lloh109:
	adrp	x8, _LC_L0S_INACTIVITY_MASK@GOTPAGE
Lloh110:
	ldr	x8, [x8, _LC_L0S_INACTIVITY_MASK@GOTPAGEOFF]
Lloh111:
	ldr	w8, [x8]
	bic	w1, w0, w8
	cmp	w0, w1
	b.eq	LBB0_56
; %bb.55:
Lloh112:
	adrp	x8, _PCIE_LC_CNTL@GOTPAGE
Lloh113:
	ldr	x8, [x8, _PCIE_LC_CNTL@GOTPAGEOFF]
Lloh114:
	ldr	w0, [x8]
	bl	_WREG32_PCIE_PORT
LBB0_56:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
LBB0_57:
	ldr	x8, [x19, #16]
	ldr	x8, [x8]
	ldr	x0, [x8]
Lloh115:
	adrp	x8, _PCI_EXP_LNKCAP@GOTPAGE
Lloh116:
	ldr	x8, [x8, _PCI_EXP_LNKCAP@GOTPAGEOFF]
Lloh117:
	ldr	w1, [x8]
	add	x2, sp, #12
	bl	_pcie_capability_read_dword
	ldr	w8, [sp, #12]
Lloh118:
	adrp	x9, _PCI_EXP_LNKCAP_CLKPM@GOTPAGE
Lloh119:
	ldr	x9, [x9, _PCI_EXP_LNKCAP_CLKPM@GOTPAGEOFF]
Lloh120:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_49
; %bb.58:
Lloh121:
	adrp	x19, _PCIE_LC_CNTL2@GOTPAGE
Lloh122:
	ldr	x19, [x19, _PCIE_LC_CNTL2@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PCIE_PORT
Lloh123:
	adrp	x8, _LC_ALLOW_PDWN_IN_L1@GOTPAGE
Lloh124:
	ldr	x8, [x8, _LC_ALLOW_PDWN_IN_L1@GOTPAGEOFF]
Lloh125:
	ldr	w8, [x8]
Lloh126:
	adrp	x9, _LC_ALLOW_PDWN_IN_L23@GOTPAGE
Lloh127:
	ldr	x9, [x9, _LC_ALLOW_PDWN_IN_L23@GOTPAGEOFF]
Lloh128:
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w1, w8, w9
	cmp	w0, w1
	b.eq	LBB0_60
; %bb.59:
	ldr	w0, [x19]
	bl	_WREG32_PCIE_PORT
LBB0_60:
Lloh129:
	adrp	x21, _THM_CLK_CNTL@GOTPAGE
Lloh130:
	ldr	x21, [x21, _THM_CLK_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
	mov	x19, x0
Lloh131:
	adrp	x8, _CMON_CLK_SEL_MASK@GOTPAGE
Lloh132:
	ldr	x8, [x8, _CMON_CLK_SEL_MASK@GOTPAGEOFF]
Lloh133:
	ldr	w8, [x8]
Lloh134:
	adrp	x9, _TMON_CLK_SEL_MASK@GOTPAGE
Lloh135:
	ldr	x9, [x9, _TMON_CLK_SEL_MASK@GOTPAGEOFF]
Lloh136:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w22, w0, w8
	mov	w0, #1
	bl	_CMON_CLK_SEL
	mov	x20, x0
	mov	w0, #1
	bl	_TMON_CLK_SEL
	orr	w8, w0, w20
	orr	w1, w8, w22
	cmp	w19, w1
	b.eq	LBB0_62
; %bb.61:
	ldr	w0, [x21]
	bl	_WREG32
LBB0_62:
Lloh137:
	adrp	x21, _MISC_CLK_CNTL@GOTPAGE
Lloh138:
	ldr	x21, [x21, _MISC_CLK_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
	mov	x19, x0
Lloh139:
	adrp	x8, _DEEP_SLEEP_CLK_SEL_MASK@GOTPAGE
Lloh140:
	ldr	x8, [x8, _DEEP_SLEEP_CLK_SEL_MASK@GOTPAGEOFF]
Lloh141:
	ldr	w8, [x8]
Lloh142:
	adrp	x9, _ZCLK_SEL_MASK@GOTPAGE
Lloh143:
	ldr	x9, [x9, _ZCLK_SEL_MASK@GOTPAGEOFF]
Lloh144:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w22, w0, w8
	mov	w0, #1
	bl	_DEEP_SLEEP_CLK_SEL
	mov	x20, x0
	mov	w0, #1
	bl	_ZCLK_SEL
	orr	w8, w0, w20
	orr	w1, w8, w22
	cmp	w19, w1
	b.eq	LBB0_64
; %bb.63:
	ldr	w0, [x21]
	bl	_WREG32
LBB0_64:
Lloh145:
	adrp	x19, _CG_CLKPIN_CNTL@GOTPAGE
Lloh146:
	ldr	x19, [x19, _CG_CLKPIN_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32
Lloh147:
	adrp	x8, _BCLK_AS_XCLK@GOTPAGE
Lloh148:
	ldr	x8, [x8, _BCLK_AS_XCLK@GOTPAGEOFF]
Lloh149:
	ldr	w8, [x8]
	bic	w1, w0, w8
	cmp	w0, w1
	b.eq	LBB0_66
; %bb.65:
	ldr	w0, [x19]
	bl	_WREG32
LBB0_66:
Lloh150:
	adrp	x19, _CG_CLKPIN_CNTL_2@GOTPAGE
Lloh151:
	ldr	x19, [x19, _CG_CLKPIN_CNTL_2@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32
Lloh152:
	adrp	x8, _FORCE_BIF_REFCLK_EN@GOTPAGE
Lloh153:
	ldr	x8, [x8, _FORCE_BIF_REFCLK_EN@GOTPAGEOFF]
Lloh154:
	ldr	w8, [x8]
	bic	w1, w0, w8
	cmp	w0, w1
	b.eq	LBB0_68
; %bb.67:
	ldr	w0, [x19]
	bl	_WREG32
LBB0_68:
Lloh155:
	adrp	x20, _MPLL_BYPASSCLK_SEL@GOTPAGE
Lloh156:
	ldr	x20, [x20, _MPLL_BYPASSCLK_SEL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	mov	x19, x0
Lloh157:
	adrp	x8, _MPLL_CLKOUT_SEL_MASK@GOTPAGE
Lloh158:
	ldr	x8, [x8, _MPLL_CLKOUT_SEL_MASK@GOTPAGEOFF]
Lloh159:
	ldr	w8, [x8]
	bic	w21, w0, w8
	mov	w0, #4
	bl	_MPLL_CLKOUT_SEL
	orr	w1, w21, w0
	cmp	w19, w1
	b.eq	LBB0_70
; %bb.69:
	ldr	w0, [x20]
	bl	_WREG32
LBB0_70:
Lloh160:
	adrp	x19, _SPLL_CNTL_MODE@GOTPAGE
Lloh161:
	ldr	x19, [x19, _SPLL_CNTL_MODE@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32
Lloh162:
	adrp	x8, _SPLL_REFCLK_SEL_MASK@GOTPAGE
Lloh163:
	ldr	x8, [x8, _SPLL_REFCLK_SEL_MASK@GOTPAGEOFF]
Lloh164:
	ldr	w8, [x8]
	bic	w1, w0, w8
	cmp	w0, w1
	b.eq	LBB0_49
; %bb.71:
	ldr	w0, [x19]
	bl	_WREG32
	b	LBB0_49
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh54, Lloh55
	.loh AdrpLdrGot	Lloh56, Lloh57
	.loh AdrpLdrGot	Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGot	Lloh64, Lloh65
	.loh AdrpLdrGot	Lloh62, Lloh63
	.loh AdrpLdrGot	Lloh66, Lloh67
	.loh AdrpLdrGot	Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGot	Lloh70, Lloh71
	.loh AdrpLdrGot	Lloh77, Lloh78
	.loh AdrpLdrGot	Lloh75, Lloh76
	.loh AdrpLdrGot	Lloh79, Lloh80
	.loh AdrpLdrGot	Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh92
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGot	Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh112, Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.loh AdrpLdrGotLdr	Lloh126, Lloh127, Lloh128
	.loh AdrpLdrGotLdr	Lloh123, Lloh124, Lloh125
	.loh AdrpLdrGot	Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh134, Lloh135, Lloh136
	.loh AdrpLdrGotLdr	Lloh131, Lloh132, Lloh133
	.loh AdrpLdrGot	Lloh129, Lloh130
	.loh AdrpLdrGotLdr	Lloh142, Lloh143, Lloh144
	.loh AdrpLdrGotLdr	Lloh139, Lloh140, Lloh141
	.loh AdrpLdrGot	Lloh137, Lloh138
	.loh AdrpLdrGotLdr	Lloh147, Lloh148, Lloh149
	.loh AdrpLdrGot	Lloh145, Lloh146
	.loh AdrpLdrGotLdr	Lloh152, Lloh153, Lloh154
	.loh AdrpLdrGot	Lloh150, Lloh151
	.loh AdrpLdrGotLdr	Lloh157, Lloh158, Lloh159
	.loh AdrpLdrGot	Lloh155, Lloh156
	.loh AdrpLdrGotLdr	Lloh162, Lloh163, Lloh164
	.loh AdrpLdrGot	Lloh160, Lloh161
	.cfi_endproc
                                        ; -- End function
	.comm	_amdgpu_aspm,8,3                ; @amdgpu_aspm
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_PCIE_LC_N_FTS_CNTL,4,2         ; @PCIE_LC_N_FTS_CNTL
	.comm	_LC_XMIT_N_FTS_MASK,4,2         ; @LC_XMIT_N_FTS_MASK
	.comm	_LC_XMIT_N_FTS_OVERRIDE_EN,4,2  ; @LC_XMIT_N_FTS_OVERRIDE_EN
	.comm	_PCIE_LC_CNTL3,4,2              ; @PCIE_LC_CNTL3
	.comm	_LC_GO_TO_RECOVERY,4,2          ; @LC_GO_TO_RECOVERY
	.comm	_PCIE_P_CNTL,4,2                ; @PCIE_P_CNTL
	.comm	_P_IGNORE_EDB_ERR,4,2           ; @P_IGNORE_EDB_ERR
	.comm	_PCIE_LC_CNTL,4,2               ; @PCIE_LC_CNTL
	.comm	_LC_L0S_INACTIVITY_MASK,4,2     ; @LC_L0S_INACTIVITY_MASK
	.comm	_LC_L1_INACTIVITY_MASK,4,2      ; @LC_L1_INACTIVITY_MASK
	.comm	_LC_PMI_TO_L1_DIS,4,2           ; @LC_PMI_TO_L1_DIS
	.comm	_PB0_PIF_PWRDOWN_0,4,2          ; @PB0_PIF_PWRDOWN_0
	.comm	_PLL_POWER_STATE_IN_OFF_0_MASK,4,2 ; @PLL_POWER_STATE_IN_OFF_0_MASK
	.comm	_PLL_POWER_STATE_IN_TXS2_0_MASK,4,2 ; @PLL_POWER_STATE_IN_TXS2_0_MASK
	.comm	_PB0_PIF_PWRDOWN_1,4,2          ; @PB0_PIF_PWRDOWN_1
	.comm	_PLL_POWER_STATE_IN_OFF_1_MASK,4,2 ; @PLL_POWER_STATE_IN_OFF_1_MASK
	.comm	_PLL_POWER_STATE_IN_TXS2_1_MASK,4,2 ; @PLL_POWER_STATE_IN_TXS2_1_MASK
	.comm	_PB1_PIF_PWRDOWN_0,4,2          ; @PB1_PIF_PWRDOWN_0
	.comm	_PB1_PIF_PWRDOWN_1,4,2          ; @PB1_PIF_PWRDOWN_1
	.comm	_CHIP_OLAND,8,3                 ; @CHIP_OLAND
	.comm	_CHIP_HAINAN,8,3                ; @CHIP_HAINAN
	.comm	_PLL_RAMP_UP_TIME_0_MASK,4,2    ; @PLL_RAMP_UP_TIME_0_MASK
	.comm	_PLL_RAMP_UP_TIME_1_MASK,4,2    ; @PLL_RAMP_UP_TIME_1_MASK
	.comm	_PB0_PIF_PWRDOWN_2,4,2          ; @PB0_PIF_PWRDOWN_2
	.comm	_PLL_RAMP_UP_TIME_2_MASK,4,2    ; @PLL_RAMP_UP_TIME_2_MASK
	.comm	_PB0_PIF_PWRDOWN_3,4,2          ; @PB0_PIF_PWRDOWN_3
	.comm	_PLL_RAMP_UP_TIME_3_MASK,4,2    ; @PLL_RAMP_UP_TIME_3_MASK
	.comm	_PB1_PIF_PWRDOWN_2,4,2          ; @PB1_PIF_PWRDOWN_2
	.comm	_PB1_PIF_PWRDOWN_3,4,2          ; @PB1_PIF_PWRDOWN_3
	.comm	_PCIE_LC_LINK_WIDTH_CNTL,4,2    ; @PCIE_LC_LINK_WIDTH_CNTL
	.comm	_LC_DYN_LANES_PWR_STATE_MASK,4,2 ; @LC_DYN_LANES_PWR_STATE_MASK
	.comm	_PB0_PIF_CNTL,4,2               ; @PB0_PIF_CNTL
	.comm	_LS2_EXIT_TIME_MASK,4,2         ; @LS2_EXIT_TIME_MASK
	.comm	_PB1_PIF_CNTL,4,2               ; @PB1_PIF_CNTL
	.comm	_PCI_EXP_LNKCAP,4,2             ; @PCI_EXP_LNKCAP
	.comm	_PCI_EXP_LNKCAP_CLKPM,4,2       ; @PCI_EXP_LNKCAP_CLKPM
	.comm	_PCIE_LC_CNTL2,4,2              ; @PCIE_LC_CNTL2
	.comm	_LC_ALLOW_PDWN_IN_L1,4,2        ; @LC_ALLOW_PDWN_IN_L1
	.comm	_LC_ALLOW_PDWN_IN_L23,4,2       ; @LC_ALLOW_PDWN_IN_L23
	.comm	_THM_CLK_CNTL,4,2               ; @THM_CLK_CNTL
	.comm	_CMON_CLK_SEL_MASK,4,2          ; @CMON_CLK_SEL_MASK
	.comm	_TMON_CLK_SEL_MASK,4,2          ; @TMON_CLK_SEL_MASK
	.comm	_MISC_CLK_CNTL,4,2              ; @MISC_CLK_CNTL
	.comm	_DEEP_SLEEP_CLK_SEL_MASK,4,2    ; @DEEP_SLEEP_CLK_SEL_MASK
	.comm	_ZCLK_SEL_MASK,4,2              ; @ZCLK_SEL_MASK
	.comm	_CG_CLKPIN_CNTL,4,2             ; @CG_CLKPIN_CNTL
	.comm	_BCLK_AS_XCLK,4,2               ; @BCLK_AS_XCLK
	.comm	_CG_CLKPIN_CNTL_2,4,2           ; @CG_CLKPIN_CNTL_2
	.comm	_FORCE_BIF_REFCLK_EN,4,2        ; @FORCE_BIF_REFCLK_EN
	.comm	_MPLL_BYPASSCLK_SEL,4,2         ; @MPLL_BYPASSCLK_SEL
	.comm	_MPLL_CLKOUT_SEL_MASK,4,2       ; @MPLL_CLKOUT_SEL_MASK
	.comm	_SPLL_CNTL_MODE,4,2             ; @SPLL_CNTL_MODE
	.comm	_SPLL_REFCLK_SEL_MASK,4,2       ; @SPLL_REFCLK_SEL_MASK
	.comm	_PCIE_CNTL2,4,2                 ; @PCIE_CNTL2
	.comm	_SLV_MEM_LS_EN,4,2              ; @SLV_MEM_LS_EN
	.comm	_MST_MEM_LS_EN,4,2              ; @MST_MEM_LS_EN
	.comm	_REPLAY_MEM_LS_EN,4,2           ; @REPLAY_MEM_LS_EN
	.comm	_LC_N_FTS_MASK,4,2              ; @LC_N_FTS_MASK
	.comm	_PCIE_LC_STATUS1,4,2            ; @PCIE_LC_STATUS1
	.comm	_LC_REVERSE_XMIT,4,2            ; @LC_REVERSE_XMIT
	.comm	_LC_REVERSE_RCVR,4,2            ; @LC_REVERSE_RCVR
	.no_dead_strip	_si_program_aspm
.subsections_via_symbols
