	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_ucode_init_bo           ## -- Begin function amdgpu_ucode_init_bo
	.p2align	4, 0x90
_amdgpu_ucode_init_bo:                  ## @amdgpu_ucode_init_bo
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_3
LBB0_1:
	movq	(%r15), %rax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	movq	%r15, -48(%rbp)                 ## 8-byte Spill
	jne	LBB0_5
## %bb.2:
	movq	_AMDGPU_UCODE_ID_MAXIMUM@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	jmp	LBB0_9
LBB0_3:
	cmpq	$0, 48(%r15)
	jne	LBB0_17
## %bb.4:
	cmpq	$0, 40(%r15)
	jne	LBB0_17
	jmp	LBB0_1
LBB0_5:
	movq	%r15, %rdi
	callq	_amdgpu_sriov_vf
	movq	_AMDGPU_UCODE_ID_MAXIMUM@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	testq	%rax, %rax
	je	LBB0_7
## %bb.6:
	addq	$-3, %rcx
	jmp	LBB0_8
LBB0_7:
	addq	$-4, %rcx
LBB0_8:
	movq	-48(%rbp), %r15                 ## 8-byte Reload
LBB0_9:
	movl	%ecx, 8(%r15)
	testl	%ecx, %ecx
	jle	LBB0_17
## %bb.10:
	xorl	%ebx, %ebx
	xorl	%r13d, %r13d
	xorl	%esi, %esi
	jmp	LBB0_13
	.p2align	4, 0x90
LBB0_11:                                ##   in Loop: Header=BB0_13 Depth=1
	movl	(%r14,%rbx), %edi
	movq	_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_ALIGN
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
	addq	%rax, %rsi
	movq	-48(%rbp), %r15                 ## 8-byte Reload
	movl	8(%r15), %ecx
LBB0_12:                                ##   in Loop: Header=BB0_13 Depth=1
	incq	%r13
	movslq	%ecx, %rax
	addq	$16, %rbx
	cmpq	%rax, %r13
	jge	LBB0_17
LBB0_13:                                ## =>This Inner Loop Header: Depth=1
	movq	32(%r15), %r14
	cmpq	$0, 8(%r14,%rbx)
	je	LBB0_12
## %bb.14:                              ##   in Loop: Header=BB0_13 Depth=1
	leaq	(%r14,%rbx), %r12
	movq	24(%r15), %rdx
	addq	%rsi, %rdx
	movq	16(%r15), %rcx
	movq	%rsi, -56(%rbp)                 ## 8-byte Spill
	addq	%rsi, %rcx
	movq	%r15, %rdi
	movq	%r12, %rsi
	callq	_amdgpu_ucode_init_single_fw
	movq	_AMDGPU_UCODE_ID_CP_MEC1@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	cmpq	%rax, %r13
	jne	LBB0_11
## %bb.15:                              ##   in Loop: Header=BB0_13 Depth=1
	movq	(%r15), %rax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_11
## %bb.16:                              ##   in Loop: Header=BB0_13 Depth=1
	movq	8(%r14,%rbx), %rax
	movq	(%rax), %rax
	movq	%rax, -64(%rbp)                 ## 8-byte Spill
	movq	24(%r15), %rsi
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	addq	%rax, %rsi
	movq	16(%r15), %rdx
	addq	%rax, %rdx
	movq	%rax, %r15
	movq	%r12, %rdi
	callq	_amdgpu_ucode_patch_jt
	movq	-64(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %edi
	callq	_le32_to_cpu
                                        ## kill: def $eax killed $eax def $rax
	leal	(,%rax,4), %edi
	movq	_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_ALIGN
	addq	%rax, %r15
	movq	%r15, -56(%rbp)                 ## 8-byte Spill
	jmp	LBB0_11
LBB0_17:
	xorl	%eax, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_MAXIMUM,8,3    ## @AMDGPU_UCODE_ID_MAXIMUM
	.comm	_AMDGPU_UCODE_ID_CP_MEC1,4,2    ## @AMDGPU_UCODE_ID_CP_MEC1
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_ucode_init_bo           ; -- Begin function amdgpu_ucode_init_bo
	.p2align	2
_amdgpu_ucode_init_bo:                  ; @amdgpu_ucode_init_bo
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_3
LBB0_1:
	ldr	x8, [x19]
Lloh0:
	adrp	x21, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh1:
	ldr	x21, [x21, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
	ldr	x9, [x21]
	cmp	x8, x9
	b.ne	LBB0_5
; %bb.2:
Lloh2:
	adrp	x8, _AMDGPU_UCODE_ID_MAXIMUM@GOTPAGE
Lloh3:
	ldr	x8, [x8, _AMDGPU_UCODE_ID_MAXIMUM@GOTPAGEOFF]
Lloh4:
	ldr	x8, [x8]
	b	LBB0_6
LBB0_3:
	ldr	x8, [x19, #48]
	cbnz	x8, LBB0_14
; %bb.4:
	ldr	x8, [x19, #40]
	cbnz	x8, LBB0_14
	b	LBB0_1
LBB0_5:
	mov	x0, x19
	bl	_amdgpu_sriov_vf
Lloh5:
	adrp	x8, _AMDGPU_UCODE_ID_MAXIMUM@GOTPAGE
Lloh6:
	ldr	x8, [x8, _AMDGPU_UCODE_ID_MAXIMUM@GOTPAGEOFF]
Lloh7:
	ldr	x8, [x8]
	sub	x9, x8, #4
	sub	x8, x8, #3
	cmp	x0, #0
	csel	x8, x9, x8, eq
LBB0_6:
	str	w8, [x19, #8]
	cmp	w8, #1
	b.lt	LBB0_14
; %bb.7:
	mov	x22, #0
	mov	x23, #0
	mov	x24, #0
Lloh8:
	adrp	x25, _AMDGPU_UCODE_ID_CP_MEC1@GOTPAGE
Lloh9:
	ldr	x25, [x25, _AMDGPU_UCODE_ID_CP_MEC1@GOTPAGEOFF]
Lloh10:
	adrp	x26, _PAGE_SIZE@GOTPAGE
Lloh11:
	ldr	x26, [x26, _PAGE_SIZE@GOTPAGEOFF]
	b	LBB0_10
LBB0_8:                                 ;   in Loop: Header=BB0_10 Depth=1
	ldr	w0, [x27, x22]
	ldr	w1, [x26]
	bl	_ALIGN
	add	x24, x0, x24
	ldr	w8, [x19, #8]
LBB0_9:                                 ;   in Loop: Header=BB0_10 Depth=1
	add	x23, x23, #1
	add	x22, x22, #16
	cmp	x23, w8, sxtw
	b.ge	LBB0_14
LBB0_10:                                ; =>This Inner Loop Header: Depth=1
	ldr	x27, [x19, #32]
	add	x20, x27, x22
	ldr	x9, [x20, #8]
	cbz	x9, LBB0_9
; %bb.11:                               ;   in Loop: Header=BB0_10 Depth=1
	ldp	x9, x8, [x19, #16]
	add	x2, x8, x24
	add	x3, x9, x24
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_ucode_init_single_fw
	ldr	w8, [x25]
	cmp	x23, x8
	b.ne	LBB0_8
; %bb.12:                               ;   in Loop: Header=BB0_10 Depth=1
	ldr	x8, [x19]
	ldr	x9, [x21]
	cmp	x8, x9
	b.eq	LBB0_8
; %bb.13:                               ;   in Loop: Header=BB0_10 Depth=1
	ldr	x8, [x20, #8]
	ldr	x28, [x8]
	ldp	x9, x8, [x19, #16]
	add	x1, x8, x24
	add	x2, x9, x24
	mov	x0, x20
	bl	_amdgpu_ucode_patch_jt
	ldr	w0, [x28]
	bl	_le32_to_cpu
	lsl	w0, w0, #2
	ldr	w1, [x26]
	bl	_ALIGN
	add	x24, x0, x24
	b	LBB0_8
LBB0_14:
	mov	w0, #0
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_MAXIMUM,8,3    ; @AMDGPU_UCODE_ID_MAXIMUM
	.comm	_AMDGPU_UCODE_ID_CP_MEC1,4,2    ; @AMDGPU_UCODE_ID_CP_MEC1
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
.subsections_via_symbols
