	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ci_update_vce_smc_table
_ci_update_vce_smc_table:               ## @ci_update_vce_smc_table
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	48(%rdi), %rax
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD@GOTPCREL(%rip), %rcx
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rbx
	orq	(%rcx), %rbx
	movq	40(%rdi), %r14
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK@GOTPCREL(%rip), %rcx
	orq	(%rcx), %rbx
	movq	32(%rdi), %r12
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPCREL(%rip), %rcx
	orq	(%rcx), %rbx
	xorl	%ecx, %ecx
	cmpq	$0, (%rax)
	setne	%cl
	movq	16(%rdi,%rcx,8), %r13
	movl	8(%rdi), %edi
	movq	_CGS_IND_REG__SMC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DPM_TABLE_475@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_VceBootLevel@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%r8d, %r8d
	callq	_PHM_WRITE_INDIRECT_FIELD
	movq	%r14, -48(%rbp)                 ## 8-byte Spill
	movl	$0, (%r14)
	movq	(%r12), %r14
	.p2align	4, 0x90
LBB0_1:                                 ## =>This Inner Loop Header: Depth=1
	movq	8(%r12), %rax
	cmpq	%r13, -8(%rax,%r14,8)
	jg	LBB0_3
## %bb.2:                               ##   in Loop: Header=BB0_1 Depth=1
	leal	-1(%r14), %ecx
	movl	$1, %eax
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %eax
	movq	-48(%rbp), %rcx                 ## 8-byte Reload
	orl	%eax, (%rcx)
LBB0_3:                                 ##   in Loop: Header=BB0_1 Depth=1
	testq	%rbx, (%r15)
	jne	LBB0_5
## %bb.4:                               ##   in Loop: Header=BB0_1 Depth=1
	movq	_PHM_PlatformCaps_VCEDPM@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_PP_CAP
	decq	%r14
	testl	%eax, %eax
	jne	LBB0_1
LBB0_5:
	movq	_PPSMC_MSG_VCEDPM_SetEnabledMask@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_ci_send_msg_to_smc_with_parameter
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD,8,3 ## @AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK,8,3 ## @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK,8,3 ## @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,8,3 ## @AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
	.comm	_CGS_IND_REG__SMC,4,2           ## @CGS_IND_REG__SMC
	.comm	_DPM_TABLE_475,4,2              ## @DPM_TABLE_475
	.comm	_VceBootLevel,4,2               ## @VceBootLevel
	.comm	_PHM_PlatformCaps_VCEDPM,4,2    ## @PHM_PlatformCaps_VCEDPM
	.comm	_PPSMC_MSG_VCEDPM_SetEnabledMask,4,2 ## @PPSMC_MSG_VCEDPM_SetEnabledMask
	.no_dead_strip	_ci_update_vce_smc_table
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ci_update_vce_smc_table
_ci_update_vce_smc_table:               ; @ci_update_vce_smc_table
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldp	x20, x8, [x0, #40]
	ldr	x21, [x0, #32]
Lloh0:
	adrp	x9, _AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
Lloh3:
	adrp	x10, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK@GOTPAGE
Lloh4:
	ldr	x10, [x10, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK@GOTPAGEOFF]
Lloh5:
	ldr	x10, [x10]
Lloh6:
	adrp	x11, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK@GOTPAGE
Lloh7:
	ldr	x11, [x11, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK@GOTPAGEOFF]
	orr	x9, x10, x9
Lloh8:
	ldr	x10, [x11]
	orr	x9, x9, x10
Lloh9:
	adrp	x10, _AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPAGE
Lloh10:
	ldr	x10, [x10, _AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPAGEOFF]
Lloh11:
	ldr	x10, [x10]
	orr	x22, x9, x10
	ldr	x8, [x8]
	mov	w9, #24
	mov	w10, #16
	cmp	x8, #0
	csel	x8, x10, x9, eq
	ldr	x23, [x0, x8]
	ldr	w0, [x0, #8]
Lloh12:
	adrp	x8, _CGS_IND_REG__SMC@GOTPAGE
Lloh13:
	ldr	x8, [x8, _CGS_IND_REG__SMC@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
Lloh15:
	adrp	x8, _DPM_TABLE_475@GOTPAGE
Lloh16:
	ldr	x8, [x8, _DPM_TABLE_475@GOTPAGEOFF]
Lloh17:
	ldr	w2, [x8]
Lloh18:
	adrp	x8, _VceBootLevel@GOTPAGE
Lloh19:
	ldr	x8, [x8, _VceBootLevel@GOTPAGEOFF]
Lloh20:
	ldr	w3, [x8]
	mov	w4, #0
	bl	_PHM_WRITE_INDIRECT_FIELD
	str	wzr, [x20]
	ldr	x24, [x21]
	mov	w25, #1
Lloh21:
	adrp	x26, _PHM_PlatformCaps_VCEDPM@GOTPAGE
Lloh22:
	ldr	x26, [x26, _PHM_PlatformCaps_VCEDPM@GOTPAGEOFF]
LBB0_1:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x21, #8]
	add	x8, x8, x24, lsl #3
	ldur	x8, [x8, #-8]
	cmp	x8, x23
	b.gt	LBB0_3
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	sub	w8, w24, #1
	lsl	w8, w25, w8
	ldr	w9, [x20]
	orr	w8, w9, w8
	str	w8, [x20]
LBB0_3:                                 ;   in Loop: Header=BB0_1 Depth=1
	ldr	x8, [x19]
	tst	x8, x22
	b.ne	LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_1 Depth=1
	ldr	w0, [x26]
	bl	_PP_CAP
	sub	x24, x24, #1
	cbnz	w0, LBB0_1
LBB0_5:
Lloh23:
	adrp	x8, _PPSMC_MSG_VCEDPM_SetEnabledMask@GOTPAGE
Lloh24:
	ldr	x8, [x8, _PPSMC_MSG_VCEDPM_SetEnabledMask@GOTPAGEOFF]
Lloh25:
	ldr	w1, [x8]
	ldr	w2, [x20]
	mov	x0, x19
	bl	_ci_send_msg_to_smc_with_parameter
	mov	w0, #0
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD,8,3 ; @AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK,8,3 ; @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK,8,3 ; @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,8,3 ; @AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
	.comm	_CGS_IND_REG__SMC,4,2           ; @CGS_IND_REG__SMC
	.comm	_DPM_TABLE_475,4,2              ; @DPM_TABLE_475
	.comm	_VceBootLevel,4,2               ; @VceBootLevel
	.comm	_PHM_PlatformCaps_VCEDPM,4,2    ; @PHM_PlatformCaps_VCEDPM
	.comm	_PPSMC_MSG_VCEDPM_SetEnabledMask,4,2 ; @PPSMC_MSG_VCEDPM_SetEnabledMask
	.no_dead_strip	_ci_update_vce_smc_table
.subsections_via_symbols
