	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function uvd_v5_0_enable_clock_gating
_uvd_v5_0_enable_clock_gating:          ## @uvd_v5_0_enable_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r12d
	movq	%rdi, %r14
	movq	_mmUVD_SUVD_CGC_GATE@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_RREG32
	movl	%eax, %r15d
	movq	_mmUVD_CGC_GATE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	testl	%r12d, %r12d
	je	LBB0_1
## %bb.2:
	movq	_UVD_CGC_GATE__SYS_MASK@GOTPCREL(%rip), %r8
	movq	_UVD_CGC_GATE__UDEC_MASK@GOTPCREL(%rip), %rdi
	movq	_UVD_CGC_GATE__MPEG2_MASK@GOTPCREL(%rip), %rdx
	movq	_AMD_PG_SUPPORT_UVD@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	movq	_UVD_CGC_GATE__MPRD_MASK@GOTPCREL(%rip), %rcx
	movq	_UVD_CGC_GATE__MPC_MASK@GOTPCREL(%rip), %r11
	movq	_UVD_CGC_GATE__LBSI_MASK@GOTPCREL(%rip), %r10
	movq	_UVD_CGC_GATE__LRBBM_MASK@GOTPCREL(%rip), %r13
	movq	_UVD_CGC_GATE__UDEC_RE_MASK@GOTPCREL(%rip), %r9
	movq	_UVD_CGC_GATE__UDEC_CM_MASK@GOTPCREL(%rip), %r12
	movq	_UVD_CGC_GATE__UDEC_IT_MASK@GOTPCREL(%rip), %rsi
	andl	(%r14), %ebx
	je	LBB0_4
## %bb.3:
	movq	_UVD_CGC_GATE__VCPU_MASK@GOTPCREL(%rip), %rbx
	movl	(%rbx), %ebx
LBB0_4:
	orl	(%r8), %eax
	orl	(%rdi), %eax
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__RBC_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__LMI_MC_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__IDCT_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	orl	(%rcx), %eax
	orl	(%r11), %eax
	orl	(%r10), %eax
	orl	(%r13), %eax
	orl	(%r9), %eax
	orl	(%r12), %eax
	orl	(%rsi), %eax
	movq	_UVD_CGC_GATE__UDEC_DB_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_GATE__UDEC_MP_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_GATE__WCB_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_GATE__JPEG_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_GATE__SCPU_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	orl	%ebx, %eax
	movq	_UVD_CGC_GATE__REGS_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r14d
	notl	%r14d
	andl	%eax, %r14d
	movq	_UVD_SUVD_CGC_GATE__SRE_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %r15d
	movq	_UVD_SUVD_CGC_GATE__SIT_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %r15d
	movq	_UVD_SUVD_CGC_GATE__SMP_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %r15d
	movq	_UVD_SUVD_CGC_GATE__SCM_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %r15d
	movq	_UVD_SUVD_CGC_GATE__SDB_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %r15d
	movq	_mmUVD_SUVD_CGC_GATE@GOTPCREL(%rip), %r13
	movq	_mmUVD_CGC_GATE@GOTPCREL(%rip), %rbx
	jmp	LBB0_5
LBB0_1:
	xorl	%r14d, %r14d
	xorl	%r15d, %r15d
LBB0_5:
	movl	(%r13), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movl	(%rbx), %edi
	movl	%r14d, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_mmUVD_SUVD_CGC_GATE,4,2        ## @mmUVD_SUVD_CGC_GATE
	.comm	_mmUVD_CGC_GATE,4,2             ## @mmUVD_CGC_GATE
	.comm	_UVD_SUVD_CGC_GATE__SRE_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SRE_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SIT_MASK
	.comm	_UVD_SUVD_CGC_GATE__SMP_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SMP_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SCM_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SDB_MASK
	.comm	_UVD_CGC_GATE__SYS_MASK,4,2     ## @UVD_CGC_GATE__SYS_MASK
	.comm	_UVD_CGC_GATE__UDEC_MASK,4,2    ## @UVD_CGC_GATE__UDEC_MASK
	.comm	_UVD_CGC_GATE__MPEG2_MASK,4,2   ## @UVD_CGC_GATE__MPEG2_MASK
	.comm	_UVD_CGC_GATE__RBC_MASK,4,2     ## @UVD_CGC_GATE__RBC_MASK
	.comm	_UVD_CGC_GATE__LMI_MC_MASK,4,2  ## @UVD_CGC_GATE__LMI_MC_MASK
	.comm	_UVD_CGC_GATE__IDCT_MASK,4,2    ## @UVD_CGC_GATE__IDCT_MASK
	.comm	_UVD_CGC_GATE__MPRD_MASK,4,2    ## @UVD_CGC_GATE__MPRD_MASK
	.comm	_UVD_CGC_GATE__MPC_MASK,4,2     ## @UVD_CGC_GATE__MPC_MASK
	.comm	_UVD_CGC_GATE__LBSI_MASK,4,2    ## @UVD_CGC_GATE__LBSI_MASK
	.comm	_UVD_CGC_GATE__LRBBM_MASK,4,2   ## @UVD_CGC_GATE__LRBBM_MASK
	.comm	_UVD_CGC_GATE__UDEC_RE_MASK,4,2 ## @UVD_CGC_GATE__UDEC_RE_MASK
	.comm	_UVD_CGC_GATE__UDEC_CM_MASK,4,2 ## @UVD_CGC_GATE__UDEC_CM_MASK
	.comm	_UVD_CGC_GATE__UDEC_IT_MASK,4,2 ## @UVD_CGC_GATE__UDEC_IT_MASK
	.comm	_UVD_CGC_GATE__UDEC_DB_MASK,4,2 ## @UVD_CGC_GATE__UDEC_DB_MASK
	.comm	_UVD_CGC_GATE__UDEC_MP_MASK,4,2 ## @UVD_CGC_GATE__UDEC_MP_MASK
	.comm	_UVD_CGC_GATE__WCB_MASK,4,2     ## @UVD_CGC_GATE__WCB_MASK
	.comm	_UVD_CGC_GATE__JPEG_MASK,4,2    ## @UVD_CGC_GATE__JPEG_MASK
	.comm	_UVD_CGC_GATE__SCPU_MASK,4,2    ## @UVD_CGC_GATE__SCPU_MASK
	.comm	_AMD_PG_SUPPORT_UVD,4,2         ## @AMD_PG_SUPPORT_UVD
	.comm	_UVD_CGC_GATE__VCPU_MASK,4,2    ## @UVD_CGC_GATE__VCPU_MASK
	.comm	_UVD_CGC_GATE__REGS_MASK,4,2    ## @UVD_CGC_GATE__REGS_MASK
	.no_dead_strip	_uvd_v5_0_enable_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function uvd_v5_0_enable_clock_gating
_uvd_v5_0_enable_clock_gating:          ; @uvd_v5_0_enable_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x1
	mov	x20, x0
Lloh0:
	adrp	x22, _mmUVD_SUVD_CGC_GATE@GOTPAGE
Lloh1:
	ldr	x22, [x22, _mmUVD_SUVD_CGC_GATE@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_RREG32
	mov	x19, x0
Lloh2:
	adrp	x23, _mmUVD_CGC_GATE@GOTPAGE
Lloh3:
	ldr	x23, [x23, _mmUVD_CGC_GATE@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32
	cbz	w21, LBB0_2
; %bb.1:
Lloh4:
	adrp	x8, _UVD_SUVD_CGC_GATE__SRE_MASK@GOTPAGE
Lloh5:
	ldr	x8, [x8, _UVD_SUVD_CGC_GATE__SRE_MASK@GOTPAGEOFF]
Lloh6:
	adrp	x10, _UVD_SUVD_CGC_GATE__SIT_MASK@GOTPAGE
Lloh7:
	ldr	x10, [x10, _UVD_SUVD_CGC_GATE__SIT_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x8]
Lloh9:
	ldr	w8, [x10]
Lloh10:
	adrp	x10, _UVD_SUVD_CGC_GATE__SMP_MASK@GOTPAGE
Lloh11:
	ldr	x10, [x10, _UVD_SUVD_CGC_GATE__SMP_MASK@GOTPAGEOFF]
Lloh12:
	adrp	x12, _UVD_SUVD_CGC_GATE__SCM_MASK@GOTPAGE
Lloh13:
	ldr	x12, [x12, _UVD_SUVD_CGC_GATE__SCM_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w11, [x10]
Lloh15:
	ldr	w10, [x12]
Lloh16:
	adrp	x12, _UVD_SUVD_CGC_GATE__SDB_MASK@GOTPAGE
Lloh17:
	ldr	x12, [x12, _UVD_SUVD_CGC_GATE__SDB_MASK@GOTPAGEOFF]
Lloh18:
	adrp	x13, _UVD_CGC_GATE__SYS_MASK@GOTPAGE
Lloh19:
	ldr	x13, [x13, _UVD_CGC_GATE__SYS_MASK@GOTPAGEOFF]
Lloh20:
	ldr	w12, [x12]
Lloh21:
	ldr	w13, [x13]
Lloh22:
	adrp	x14, _UVD_CGC_GATE__UDEC_MASK@GOTPAGE
Lloh23:
	ldr	x14, [x14, _UVD_CGC_GATE__UDEC_MASK@GOTPAGEOFF]
Lloh24:
	adrp	x15, _UVD_CGC_GATE__MPEG2_MASK@GOTPAGE
Lloh25:
	ldr	x15, [x15, _UVD_CGC_GATE__MPEG2_MASK@GOTPAGEOFF]
Lloh26:
	ldr	w14, [x14]
Lloh27:
	ldr	w15, [x15]
Lloh28:
	adrp	x16, _UVD_CGC_GATE__RBC_MASK@GOTPAGE
Lloh29:
	ldr	x16, [x16, _UVD_CGC_GATE__RBC_MASK@GOTPAGEOFF]
Lloh30:
	adrp	x17, _UVD_CGC_GATE__LMI_MC_MASK@GOTPAGE
Lloh31:
	ldr	x17, [x17, _UVD_CGC_GATE__LMI_MC_MASK@GOTPAGEOFF]
Lloh32:
	ldr	w16, [x16]
Lloh33:
	ldr	w17, [x17]
Lloh34:
	adrp	x1, _UVD_CGC_GATE__IDCT_MASK@GOTPAGE
Lloh35:
	ldr	x1, [x1, _UVD_CGC_GATE__IDCT_MASK@GOTPAGEOFF]
Lloh36:
	adrp	x2, _UVD_CGC_GATE__MPRD_MASK@GOTPAGE
Lloh37:
	ldr	x2, [x2, _UVD_CGC_GATE__MPRD_MASK@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x1]
Lloh39:
	ldr	w2, [x2]
Lloh40:
	adrp	x3, _UVD_CGC_GATE__MPC_MASK@GOTPAGE
Lloh41:
	ldr	x3, [x3, _UVD_CGC_GATE__MPC_MASK@GOTPAGEOFF]
Lloh42:
	adrp	x4, _UVD_CGC_GATE__LBSI_MASK@GOTPAGE
Lloh43:
	ldr	x4, [x4, _UVD_CGC_GATE__LBSI_MASK@GOTPAGEOFF]
Lloh44:
	ldr	w3, [x3]
Lloh45:
	ldr	w4, [x4]
Lloh46:
	adrp	x5, _UVD_CGC_GATE__LRBBM_MASK@GOTPAGE
Lloh47:
	ldr	x5, [x5, _UVD_CGC_GATE__LRBBM_MASK@GOTPAGEOFF]
Lloh48:
	adrp	x6, _UVD_CGC_GATE__UDEC_RE_MASK@GOTPAGE
Lloh49:
	ldr	x6, [x6, _UVD_CGC_GATE__UDEC_RE_MASK@GOTPAGEOFF]
Lloh50:
	ldr	w5, [x5]
Lloh51:
	ldr	w6, [x6]
Lloh52:
	adrp	x7, _UVD_CGC_GATE__UDEC_CM_MASK@GOTPAGE
Lloh53:
	ldr	x7, [x7, _UVD_CGC_GATE__UDEC_CM_MASK@GOTPAGEOFF]
Lloh54:
	adrp	x21, _UVD_CGC_GATE__UDEC_IT_MASK@GOTPAGE
Lloh55:
	ldr	x21, [x21, _UVD_CGC_GATE__UDEC_IT_MASK@GOTPAGEOFF]
Lloh56:
	ldr	w7, [x7]
Lloh57:
	ldr	w21, [x21]
Lloh58:
	adrp	x24, _UVD_CGC_GATE__UDEC_DB_MASK@GOTPAGE
Lloh59:
	ldr	x24, [x24, _UVD_CGC_GATE__UDEC_DB_MASK@GOTPAGEOFF]
Lloh60:
	adrp	x25, _UVD_CGC_GATE__UDEC_MP_MASK@GOTPAGE
Lloh61:
	ldr	x25, [x25, _UVD_CGC_GATE__UDEC_MP_MASK@GOTPAGEOFF]
Lloh62:
	ldr	w24, [x24]
Lloh63:
	ldr	w25, [x25]
Lloh64:
	adrp	x26, _UVD_CGC_GATE__WCB_MASK@GOTPAGE
Lloh65:
	ldr	x26, [x26, _UVD_CGC_GATE__WCB_MASK@GOTPAGEOFF]
Lloh66:
	adrp	x27, _UVD_CGC_GATE__JPEG_MASK@GOTPAGE
Lloh67:
	ldr	x27, [x27, _UVD_CGC_GATE__JPEG_MASK@GOTPAGEOFF]
Lloh68:
	ldr	w26, [x26]
Lloh69:
	ldr	w27, [x27]
Lloh70:
	adrp	x28, _UVD_CGC_GATE__SCPU_MASK@GOTPAGE
Lloh71:
	ldr	x28, [x28, _UVD_CGC_GATE__SCPU_MASK@GOTPAGEOFF]
Lloh72:
	adrp	x30, _AMD_PG_SUPPORT_UVD@GOTPAGE
Lloh73:
	ldr	x30, [x30, _AMD_PG_SUPPORT_UVD@GOTPAGEOFF]
	ldr	w20, [x20]
Lloh74:
	ldr	w30, [x30]
	tst	w30, w20
Lloh75:
	adrp	x20, _UVD_CGC_GATE__VCPU_MASK@GOTPAGE
Lloh76:
	ldr	x20, [x20, _UVD_CGC_GATE__VCPU_MASK@GOTPAGEOFF]
Lloh77:
	ldr	w20, [x20]
	csel	w20, wzr, w20, eq
	orr	w13, w13, w0
	orr	w13, w13, w14
	orr	w13, w13, w15
	orr	w13, w13, w16
Lloh78:
	ldr	w14, [x28]
	orr	w13, w13, w17
	orr	w13, w13, w1
	orr	w13, w13, w2
	orr	w13, w13, w3
	orr	w13, w13, w4
	orr	w13, w13, w5
	orr	w13, w13, w6
	orr	w13, w13, w7
	orr	w13, w13, w21
	orr	w13, w13, w24
	orr	w13, w13, w25
	orr	w13, w13, w26
	orr	w13, w13, w27
	orr	w13, w13, w14
	orr	w13, w13, w20
Lloh79:
	adrp	x14, _UVD_CGC_GATE__REGS_MASK@GOTPAGE
Lloh80:
	ldr	x14, [x14, _UVD_CGC_GATE__REGS_MASK@GOTPAGEOFF]
Lloh81:
	ldr	w14, [x14]
	bic	w20, w13, w14
	orr	w9, w9, w19
	orr	w8, w9, w8
	orr	w8, w8, w11
	orr	w8, w8, w10
	orr	w1, w8, w12
	b	LBB0_3
LBB0_2:
	mov	w20, #0
	mov	w1, #0
LBB0_3:
	ldr	w0, [x22]
	bl	_WREG32
	ldr	w0, [x23]
	mov	x1, x20
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_WREG32
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh78
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh68
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh62
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh56
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh50
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh44
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh38
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh32
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh26
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh20
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh14
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_mmUVD_SUVD_CGC_GATE,4,2        ; @mmUVD_SUVD_CGC_GATE
	.comm	_mmUVD_CGC_GATE,4,2             ; @mmUVD_CGC_GATE
	.comm	_UVD_SUVD_CGC_GATE__SRE_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SRE_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SIT_MASK
	.comm	_UVD_SUVD_CGC_GATE__SMP_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SMP_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SCM_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SDB_MASK
	.comm	_UVD_CGC_GATE__SYS_MASK,4,2     ; @UVD_CGC_GATE__SYS_MASK
	.comm	_UVD_CGC_GATE__UDEC_MASK,4,2    ; @UVD_CGC_GATE__UDEC_MASK
	.comm	_UVD_CGC_GATE__MPEG2_MASK,4,2   ; @UVD_CGC_GATE__MPEG2_MASK
	.comm	_UVD_CGC_GATE__RBC_MASK,4,2     ; @UVD_CGC_GATE__RBC_MASK
	.comm	_UVD_CGC_GATE__LMI_MC_MASK,4,2  ; @UVD_CGC_GATE__LMI_MC_MASK
	.comm	_UVD_CGC_GATE__IDCT_MASK,4,2    ; @UVD_CGC_GATE__IDCT_MASK
	.comm	_UVD_CGC_GATE__MPRD_MASK,4,2    ; @UVD_CGC_GATE__MPRD_MASK
	.comm	_UVD_CGC_GATE__MPC_MASK,4,2     ; @UVD_CGC_GATE__MPC_MASK
	.comm	_UVD_CGC_GATE__LBSI_MASK,4,2    ; @UVD_CGC_GATE__LBSI_MASK
	.comm	_UVD_CGC_GATE__LRBBM_MASK,4,2   ; @UVD_CGC_GATE__LRBBM_MASK
	.comm	_UVD_CGC_GATE__UDEC_RE_MASK,4,2 ; @UVD_CGC_GATE__UDEC_RE_MASK
	.comm	_UVD_CGC_GATE__UDEC_CM_MASK,4,2 ; @UVD_CGC_GATE__UDEC_CM_MASK
	.comm	_UVD_CGC_GATE__UDEC_IT_MASK,4,2 ; @UVD_CGC_GATE__UDEC_IT_MASK
	.comm	_UVD_CGC_GATE__UDEC_DB_MASK,4,2 ; @UVD_CGC_GATE__UDEC_DB_MASK
	.comm	_UVD_CGC_GATE__UDEC_MP_MASK,4,2 ; @UVD_CGC_GATE__UDEC_MP_MASK
	.comm	_UVD_CGC_GATE__WCB_MASK,4,2     ; @UVD_CGC_GATE__WCB_MASK
	.comm	_UVD_CGC_GATE__JPEG_MASK,4,2    ; @UVD_CGC_GATE__JPEG_MASK
	.comm	_UVD_CGC_GATE__SCPU_MASK,4,2    ; @UVD_CGC_GATE__SCPU_MASK
	.comm	_AMD_PG_SUPPORT_UVD,4,2         ; @AMD_PG_SUPPORT_UVD
	.comm	_UVD_CGC_GATE__VCPU_MASK,4,2    ; @UVD_CGC_GATE__VCPU_MASK
	.comm	_UVD_CGC_GATE__REGS_MASK,4,2    ; @UVD_CGC_GATE__REGS_MASK
	.no_dead_strip	_uvd_v5_0_enable_clock_gating
.subsections_via_symbols
