	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_intel_vgpu_init_cfg_space      ## -- Begin function intel_vgpu_init_cfg_space
	.p2align	4, 0x90
_intel_vgpu_init_cfg_space:             ## @intel_vgpu_init_cfg_space
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r15d
	movq	%rdi, %r13
	movq	8(%rdi), %r14
	callq	_vgpu_cfg_space
	movl	8(%r14), %esi
	movl	12(%r14), %edx
	movq	%rax, %rdi
	callq	_memcpy
	testl	%r15d, %r15d
	jne	LBB0_2
## %bb.1:
	movq	_INTEL_GVT_PCI_CLASS_VGA_OTHER@GOTPCREL(%rip), %r15
	movl	(%r15), %r12d
	movq	%r13, %rdi
	callq	_vgpu_cfg_space
	movq	_PCI_CLASS_DEVICE@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	%r12d, (%rax,%rcx,4)
	movl	(%r15), %r15d
	movq	%r13, %rdi
	callq	_vgpu_cfg_space
	movq	_PCI_CLASS_PROG@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	%r15d, (%rax,%rcx,4)
LBB0_2:
	movq	%r13, %rdi
	callq	_vgpu_cfg_space
	movq	_INTEL_GVT_PCI_GMCH_CONTROL@GOTPCREL(%rip), %rcx
	movslq	(%rcx), %rdx
	movq	_BDW_GMCH_GMS_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_BDW_GMCH_GMS_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %esi
	notl	%esi
	andl	%esi, (%rax,%rdx,4)
	movq	_PCI_BASE_ADDRESS_2@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	%r14, %rdi
	callq	_gvt_aperture_pa_base
	movq	%r13, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	movl	$1, %ecx
	callq	_intel_vgpu_write_pci_bar
	movq	_PCI_COMMAND_IO@GOTPCREL(%rip), %rax
	movq	_PCI_COMMAND_MEMORY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	_PCI_COMMAND_MASTER@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	notl	%ebx
	movq	%r13, %rdi
	callq	_vgpu_cfg_space
	movq	_PCI_COMMAND@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	andl	%ebx, (%rax,%rcx,4)
	movq	%r13, %rdi
	callq	_vgpu_cfg_space
	movq	_PCI_BASE_ADDRESS_1@GOTPCREL(%rip), %rcx
	movslq	(%rcx), %rcx
	leaq	(%rax,%rcx,4), %rdi
	xorl	%esi, %esi
	movl	$4, %edx
	callq	_memset
	movq	%r13, %rdi
	callq	_vgpu_cfg_space
	movq	_PCI_BASE_ADDRESS_3@GOTPCREL(%rip), %rcx
	movslq	(%rcx), %rcx
	leaq	(%rax,%rcx,4), %rdi
	xorl	%esi, %esi
	movl	$4, %edx
	callq	_memset
	movq	%r13, %rdi
	callq	_vgpu_cfg_space
	movq	_PCI_BASE_ADDRESS_4@GOTPCREL(%rip), %rcx
	movslq	(%rcx), %rcx
	leaq	(%rax,%rcx,4), %rdi
	xorl	%esi, %esi
	movl	$8, %edx
	callq	_memset
	movq	%r13, %rdi
	callq	_vgpu_cfg_space
	movq	_INTEL_GVT_PCI_OPREGION@GOTPCREL(%rip), %rcx
	movslq	(%rcx), %rcx
	leaq	(%rax,%rcx,4), %rdi
	xorl	%esi, %esi
	movl	$4, %edx
	callq	_memset
	movq	(%r14), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_pci_resource_len
	movq	(%r13), %rcx
	movq	_INTEL_GVT_PCI_BAR_GTTMMIO@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdx
	movq	%rax, (%rcx,%rdx,8)
	movq	(%r14), %rax
	movl	(%rax), %edi
	movl	$2, %esi
	callq	_pci_resource_len
	movq	(%r13), %rcx
	movq	_INTEL_GVT_PCI_BAR_APERTURE@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdx
	movq	%rax, (%rcx,%rdx,8)
	movq	%r13, %rdi
	callq	_vgpu_cfg_space
	movq	_PCI_ROM_ADDRESS@GOTPCREL(%rip), %rcx
	movslq	(%rcx), %rcx
	leaq	(%rax,%rcx,4), %rdi
	xorl	%esi, %esi
	movl	$4, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_memset                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_INTEL_GVT_PCI_CLASS_VGA_OTHER,4,2 ## @INTEL_GVT_PCI_CLASS_VGA_OTHER
	.comm	_PCI_CLASS_DEVICE,8,3           ## @PCI_CLASS_DEVICE
	.comm	_PCI_CLASS_PROG,8,3             ## @PCI_CLASS_PROG
	.comm	_INTEL_GVT_PCI_GMCH_CONTROL,4,2 ## @INTEL_GVT_PCI_GMCH_CONTROL
	.comm	_BDW_GMCH_GMS_MASK,4,2          ## @BDW_GMCH_GMS_MASK
	.comm	_BDW_GMCH_GMS_SHIFT,4,2         ## @BDW_GMCH_GMS_SHIFT
	.comm	_PCI_BASE_ADDRESS_2,4,2         ## @PCI_BASE_ADDRESS_2
	.comm	_PCI_COMMAND_IO,4,2             ## @PCI_COMMAND_IO
	.comm	_PCI_COMMAND_MEMORY,4,2         ## @PCI_COMMAND_MEMORY
	.comm	_PCI_COMMAND_MASTER,4,2         ## @PCI_COMMAND_MASTER
	.comm	_PCI_COMMAND,8,3                ## @PCI_COMMAND
	.comm	_PCI_BASE_ADDRESS_1,4,2         ## @PCI_BASE_ADDRESS_1
	.comm	_PCI_BASE_ADDRESS_3,4,2         ## @PCI_BASE_ADDRESS_3
	.comm	_PCI_BASE_ADDRESS_4,4,2         ## @PCI_BASE_ADDRESS_4
	.comm	_INTEL_GVT_PCI_OPREGION,4,2     ## @INTEL_GVT_PCI_OPREGION
	.comm	_INTEL_GVT_PCI_BAR_GTTMMIO,8,3  ## @INTEL_GVT_PCI_BAR_GTTMMIO
	.comm	_INTEL_GVT_PCI_BAR_APERTURE,8,3 ## @INTEL_GVT_PCI_BAR_APERTURE
	.comm	_PCI_ROM_ADDRESS,4,2            ## @PCI_ROM_ADDRESS
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_intel_vgpu_init_cfg_space      ; -- Begin function intel_vgpu_init_cfg_space
	.p2align	2
_intel_vgpu_init_cfg_space:             ; @intel_vgpu_init_cfg_space
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x21, x1
	mov	x19, x0
	ldr	x20, [x0, #8]
	bl	_vgpu_cfg_space
	ldp	w1, w2, [x20, #8]
	bl	_memcpy
	cbnz	w21, LBB0_2
; %bb.1:
Lloh0:
	adrp	x21, _INTEL_GVT_PCI_CLASS_VGA_OTHER@GOTPAGE
Lloh1:
	ldr	x21, [x21, _INTEL_GVT_PCI_CLASS_VGA_OTHER@GOTPAGEOFF]
	ldr	w22, [x21]
	mov	x0, x19
	bl	_vgpu_cfg_space
Lloh2:
	adrp	x8, _PCI_CLASS_DEVICE@GOTPAGE
Lloh3:
	ldr	x8, [x8, _PCI_CLASS_DEVICE@GOTPAGEOFF]
Lloh4:
	ldr	x8, [x8]
	str	w22, [x0, x8, lsl #2]
	ldr	w21, [x21]
	mov	x0, x19
	bl	_vgpu_cfg_space
Lloh5:
	adrp	x8, _PCI_CLASS_PROG@GOTPAGE
Lloh6:
	ldr	x8, [x8, _PCI_CLASS_PROG@GOTPAGEOFF]
Lloh7:
	ldr	x8, [x8]
	str	w21, [x0, x8, lsl #2]
LBB0_2:
	mov	x0, x19
	bl	_vgpu_cfg_space
Lloh8:
	adrp	x8, _INTEL_GVT_PCI_GMCH_CONTROL@GOTPAGE
Lloh9:
	ldr	x8, [x8, _INTEL_GVT_PCI_GMCH_CONTROL@GOTPAGEOFF]
Lloh10:
	ldrsw	x8, [x8]
	lsl	x8, x8, #2
Lloh11:
	adrp	x9, _BDW_GMCH_GMS_MASK@GOTPAGE
Lloh12:
	ldr	x9, [x9, _BDW_GMCH_GMS_MASK@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
Lloh14:
	adrp	x10, _BDW_GMCH_GMS_SHIFT@GOTPAGE
Lloh15:
	ldr	x10, [x10, _BDW_GMCH_GMS_SHIFT@GOTPAGEOFF]
Lloh16:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	ldr	w10, [x0, x8]
	bic	w9, w10, w9
	str	w9, [x0, x8]
Lloh17:
	adrp	x8, _PCI_BASE_ADDRESS_2@GOTPAGE
Lloh18:
	ldr	x8, [x8, _PCI_BASE_ADDRESS_2@GOTPAGEOFF]
Lloh19:
	ldr	w21, [x8]
	mov	x0, x20
	bl	_gvt_aperture_pa_base
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	mov	w3, #1
	bl	_intel_vgpu_write_pci_bar
Lloh20:
	adrp	x8, _PCI_COMMAND_IO@GOTPAGE
Lloh21:
	ldr	x8, [x8, _PCI_COMMAND_IO@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
Lloh23:
	adrp	x9, _PCI_COMMAND_MEMORY@GOTPAGE
Lloh24:
	ldr	x9, [x9, _PCI_COMMAND_MEMORY@GOTPAGEOFF]
Lloh25:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh26:
	adrp	x9, _PCI_COMMAND_MASTER@GOTPAGE
Lloh27:
	ldr	x9, [x9, _PCI_COMMAND_MASTER@GOTPAGEOFF]
Lloh28:
	ldr	w9, [x9]
	orr	w21, w8, w9
	mov	x0, x19
	bl	_vgpu_cfg_space
Lloh29:
	adrp	x8, _PCI_COMMAND@GOTPAGE
Lloh30:
	ldr	x8, [x8, _PCI_COMMAND@GOTPAGEOFF]
Lloh31:
	ldr	x8, [x8]
	lsl	x8, x8, #2
	ldr	w9, [x0, x8]
	bic	w9, w9, w21
	str	w9, [x0, x8]
	mov	x0, x19
	bl	_vgpu_cfg_space
Lloh32:
	adrp	x8, _PCI_BASE_ADDRESS_1@GOTPAGE
Lloh33:
	ldr	x8, [x8, _PCI_BASE_ADDRESS_1@GOTPAGEOFF]
Lloh34:
	ldrsw	x8, [x8]
	add	x0, x0, x8, lsl #2
	mov	w1, #0
	mov	w2, #4
	bl	_memset
	mov	x0, x19
	bl	_vgpu_cfg_space
Lloh35:
	adrp	x8, _PCI_BASE_ADDRESS_3@GOTPAGE
Lloh36:
	ldr	x8, [x8, _PCI_BASE_ADDRESS_3@GOTPAGEOFF]
Lloh37:
	ldrsw	x8, [x8]
	add	x0, x0, x8, lsl #2
	mov	w1, #0
	mov	w2, #4
	bl	_memset
	mov	x0, x19
	bl	_vgpu_cfg_space
Lloh38:
	adrp	x8, _PCI_BASE_ADDRESS_4@GOTPAGE
Lloh39:
	ldr	x8, [x8, _PCI_BASE_ADDRESS_4@GOTPAGEOFF]
Lloh40:
	ldrsw	x8, [x8]
	add	x0, x0, x8, lsl #2
	mov	w1, #0
	mov	w2, #8
	bl	_memset
	mov	x0, x19
	bl	_vgpu_cfg_space
Lloh41:
	adrp	x8, _INTEL_GVT_PCI_OPREGION@GOTPAGE
Lloh42:
	ldr	x8, [x8, _INTEL_GVT_PCI_OPREGION@GOTPAGEOFF]
Lloh43:
	ldrsw	x8, [x8]
	add	x0, x0, x8, lsl #2
	mov	w1, #0
	mov	w2, #4
	bl	_memset
	ldr	x8, [x20]
	ldr	w0, [x8]
	mov	w1, #0
	bl	_pci_resource_len
Lloh44:
	adrp	x8, _INTEL_GVT_PCI_BAR_GTTMMIO@GOTPAGE
Lloh45:
	ldr	x8, [x8, _INTEL_GVT_PCI_BAR_GTTMMIO@GOTPAGEOFF]
	ldr	x9, [x19]
Lloh46:
	ldr	x8, [x8]
	str	x0, [x9, x8, lsl #3]
	ldr	x8, [x20]
	ldr	w0, [x8]
	mov	w1, #2
	bl	_pci_resource_len
	ldr	x8, [x19]
Lloh47:
	adrp	x9, _INTEL_GVT_PCI_BAR_APERTURE@GOTPAGE
Lloh48:
	ldr	x9, [x9, _INTEL_GVT_PCI_BAR_APERTURE@GOTPAGEOFF]
Lloh49:
	ldr	x9, [x9]
	str	x0, [x8, x9, lsl #3]
	mov	x0, x19
	bl	_vgpu_cfg_space
Lloh50:
	adrp	x8, _PCI_ROM_ADDRESS@GOTPAGE
Lloh51:
	ldr	x8, [x8, _PCI_ROM_ADDRESS@GOTPAGEOFF]
Lloh52:
	ldrsw	x8, [x8]
	add	x0, x0, x8, lsl #2
	mov	w1, #0
	mov	w2, #4
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_memset
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.cfi_endproc
                                        ; -- End function
	.comm	_INTEL_GVT_PCI_CLASS_VGA_OTHER,4,2 ; @INTEL_GVT_PCI_CLASS_VGA_OTHER
	.comm	_PCI_CLASS_DEVICE,8,3           ; @PCI_CLASS_DEVICE
	.comm	_PCI_CLASS_PROG,8,3             ; @PCI_CLASS_PROG
	.comm	_INTEL_GVT_PCI_GMCH_CONTROL,4,2 ; @INTEL_GVT_PCI_GMCH_CONTROL
	.comm	_BDW_GMCH_GMS_MASK,4,2          ; @BDW_GMCH_GMS_MASK
	.comm	_BDW_GMCH_GMS_SHIFT,4,2         ; @BDW_GMCH_GMS_SHIFT
	.comm	_PCI_BASE_ADDRESS_2,4,2         ; @PCI_BASE_ADDRESS_2
	.comm	_PCI_COMMAND_IO,4,2             ; @PCI_COMMAND_IO
	.comm	_PCI_COMMAND_MEMORY,4,2         ; @PCI_COMMAND_MEMORY
	.comm	_PCI_COMMAND_MASTER,4,2         ; @PCI_COMMAND_MASTER
	.comm	_PCI_COMMAND,8,3                ; @PCI_COMMAND
	.comm	_PCI_BASE_ADDRESS_1,4,2         ; @PCI_BASE_ADDRESS_1
	.comm	_PCI_BASE_ADDRESS_3,4,2         ; @PCI_BASE_ADDRESS_3
	.comm	_PCI_BASE_ADDRESS_4,4,2         ; @PCI_BASE_ADDRESS_4
	.comm	_INTEL_GVT_PCI_OPREGION,4,2     ; @INTEL_GVT_PCI_OPREGION
	.comm	_INTEL_GVT_PCI_BAR_GTTMMIO,8,3  ; @INTEL_GVT_PCI_BAR_GTTMMIO
	.comm	_INTEL_GVT_PCI_BAR_APERTURE,8,3 ; @INTEL_GVT_PCI_BAR_APERTURE
	.comm	_PCI_ROM_ADDRESS,4,2            ; @PCI_ROM_ADDRESS
.subsections_via_symbols
