	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r100_cp_init                   ## -- Begin function r100_cp_init
	.p2align	4, 0x90
_r100_cp_init:                          ## @r100_cp_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %ebx
	movq	%rdi, %r12
	movq	8(%rdi), %r15
	movq	_RADEON_RING_TYPE_GFX_INDEX@GOTPCREL(%rip), %rax
	movq	(%rax), %r14
	callq	_r100_debugfs_cp_init
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	leaq	L_.str(%rip), %rdi
	xorl	%eax, %eax
	callq	_DRM_ERROR
LBB0_2:
	cmpl	$0, 40(%r12)
	je	LBB0_3
LBB0_5:
	leaq	(%r14,%r14,2), %r14
	leaq	(%r15,%r14,8), %r13
	shrl	$3, %ebx
	movl	%ebx, %edi
	callq	_order_base_2
	movq	%r15, -48(%rbp)                 ## 8-byte Spill
	movl	%eax, %r15d
	leal	1(%r15), %ecx
	movl	$4, %ebx
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %ebx
	movq	%r12, %rdi
	callq	_r100_cp_load_microcode
	movq	_RADEON_WB_CP_RPTR_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	_RADEON_CP_PACKET2@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	movq	%r12, %rdi
	movq	%r13, -56(%rbp)                 ## 8-byte Spill
	movq	%r13, %rsi
	movl	%ebx, %edx
	callq	_radeon_ring_init
	movl	%eax, %r13d
	testl	%eax, %eax
	jne	LBB0_14
## %bb.6:
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	$15, (%rax)
	movl	$1816, %edi                     ## imm = 0x718
	movl	$64, %esi
	callq	_WREG32
	movq	_RADEON_RB_BUFSZ@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r15d, %esi
	callq	_REG_SET
	movl	%eax, %r15d
	movq	_RADEON_RB_BLKSZ@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$9, %esi
	callq	_REG_SET
	movl	%eax, %ebx
	orl	%r15d, %ebx
	movq	_RADEON_MAX_FETCH@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_REG_SET
	movl	%eax, %r15d
	orl	%ebx, %r15d
	movq	_RADEON_CP_RB_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movq	_RADEON_RB_NO_UPDATE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	%r15d, %esi
	callq	_WREG32
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	movslq	4(%rbx,%r14,8), %rsi
	leaq	L_.str.2(%rip), %rdi
	callq	_DRM_INFO
	movq	_RADEON_CP_RB_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	4(%rbx,%r14,8), %esi
	callq	_WREG32
	movl	(%r13), %edi
	movq	_RADEON_RB_RPTR_WR_ENA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	%r15d, %esi
	movq	_RADEON_RB_NO_UPDATE@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	callq	_WREG32
	movq	_RADEON_CP_RB_RPTR_WR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%r13d, %r13d
	xorl	%esi, %esi
	callq	_WREG32
	movl	$0, 8(%rbx,%r14,8)
	movq	_RADEON_CP_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_R_00070C_CP_RB_RPTR_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_RADEON_WB_CP_RPTR_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	addl	24(%r12), %edi
	sarl	$2, %edi
	callq	_S_00070C_RB_RPTR_ADDR
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_R_000774_SCRATCH_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_WB_SCRATCH_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	24(%r12), %esi
	callq	_WREG32
	cmpq	$0, 32(%r12)
	movl	$255, %esi
	jne	LBB0_8
## %bb.7:
	movq	_RADEON_RB_NO_UPDATE@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	xorl	%esi, %esi
LBB0_8:
	orl	%r13d, %r15d
	movq	_R_000770_SCRATCH_UMSK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32
	movq	_RADEON_CP_RB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movl	$10, %edi
	callq	_udelay
	movq	_RADEON_CP_CSQ_MODE@GOTPCREL(%rip), %r13
	movl	(%r13), %r15d
	movq	_RADEON_INDIRECT2_START@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$80, %esi
	callq	_REG_SET
	movl	%eax, %ebx
	movq	_RADEON_INDIRECT1_START@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$16, %esi
	callq	_REG_SET
	orl	%eax, %ebx
	movl	%r15d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_RADEON_CP_RB_WPTR_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r13), %edi
	movl	$19789, %esi                    ## imm = 0x4D4D
	callq	_WREG32
	movq	_RADEON_CP_CSQ_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_CSQ_PRIBM_INDBM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_WREG32
	movl	16(%r12), %edi
	callq	_pci_set_master
	movq	_RADEON_RING_TYPE_GFX_INDEX@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rsi
	leaq	(%rsi,%rsi,2), %rdx
	shlq	$3, %rdx
	addq	8(%r12), %rdx
	movq	%r12, %rdi
	callq	_radeon_ring_start
	movq	(%rbx), %rsi
	movq	%r12, %rdi
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdx
	callq	_radeon_ring_test
	testl	%eax, %eax
	je	LBB0_10
## %bb.9:
	movl	%eax, %r13d
	leaq	L_.str.3(%rip), %rdi
	movl	%eax, %esi
	xorl	%eax, %eax
	callq	_DRM_ERROR
	jmp	LBB0_14
LBB0_3:
	movq	%r12, %rdi
	callq	_r100_cp_init_microcode
	testl	%eax, %eax
	je	LBB0_5
## %bb.4:
	movl	%eax, %r13d
	leaq	L_.str.1(%rip), %rdi
	xorl	%eax, %eax
	callq	_DRM_ERROR
	jmp	LBB0_14
LBB0_10:
	movq	-48(%rbp), %r15                 ## 8-byte Reload
	movl	$1, 12(%r15,%r14,8)
	movl	(%r12), %esi
	movq	%r12, %rdi
	callq	_radeon_ttm_set_active_vram_size
	xorl	%r13d, %r13d
	cmpq	$0, 16(%r15,%r14,8)
	jne	LBB0_14
## %bb.11:
	movq	%r12, %rdi
	movq	%rbx, %rsi
	callq	_radeon_ring_supports_scratch_reg
	testq	%rax, %rax
	je	LBB0_14
## %bb.12:
	leaq	(%r15,%r14,8), %rbx
	addq	$16, %rbx
	movq	%r12, %rdi
	movq	%rbx, %rsi
	callq	_radeon_scratch_get
	testl	%eax, %eax
	je	LBB0_14
## %bb.13:
	leaq	L_.str.4(%rip), %rdi
	xorl	%r13d, %r13d
	movl	%eax, %esi
	xorl	%eax, %eax
	callq	_DRM_ERROR
	movq	$0, (%rbx)
LBB0_14:
	movl	%r13d, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_RING_TYPE_GFX_INDEX,8,3 ## @RADEON_RING_TYPE_GFX_INDEX
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Failed to register debugfs file for CP !\n"

L_.str.1:                               ## @.str.1
	.asciz	"Failed to load firmware!\n"

	.comm	_RADEON_WB_CP_RPTR_OFFSET,4,2   ## @RADEON_WB_CP_RPTR_OFFSET
	.comm	_RADEON_CP_PACKET2,4,2          ## @RADEON_CP_PACKET2
	.comm	_RADEON_RB_BUFSZ,4,2            ## @RADEON_RB_BUFSZ
	.comm	_RADEON_RB_BLKSZ,4,2            ## @RADEON_RB_BLKSZ
	.comm	_RADEON_MAX_FETCH,4,2           ## @RADEON_MAX_FETCH
	.comm	_RADEON_CP_RB_CNTL,4,2          ## @RADEON_CP_RB_CNTL
	.comm	_RADEON_RB_NO_UPDATE,4,2        ## @RADEON_RB_NO_UPDATE
L_.str.2:                               ## @.str.2
	.asciz	"radeon: ring at 0x%016lX\n"

	.comm	_RADEON_CP_RB_BASE,4,2          ## @RADEON_CP_RB_BASE
	.comm	_RADEON_RB_RPTR_WR_ENA,4,2      ## @RADEON_RB_RPTR_WR_ENA
	.comm	_RADEON_CP_RB_RPTR_WR,4,2       ## @RADEON_CP_RB_RPTR_WR
	.comm	_RADEON_CP_RB_WPTR,4,2          ## @RADEON_CP_RB_WPTR
	.comm	_R_00070C_CP_RB_RPTR_ADDR,4,2   ## @R_00070C_CP_RB_RPTR_ADDR
	.comm	_R_000774_SCRATCH_ADDR,4,2      ## @R_000774_SCRATCH_ADDR
	.comm	_RADEON_WB_SCRATCH_OFFSET,4,2   ## @RADEON_WB_SCRATCH_OFFSET
	.comm	_R_000770_SCRATCH_UMSK,4,2      ## @R_000770_SCRATCH_UMSK
	.comm	_RADEON_CP_CSQ_MODE,4,2         ## @RADEON_CP_CSQ_MODE
	.comm	_RADEON_INDIRECT2_START,4,2     ## @RADEON_INDIRECT2_START
	.comm	_RADEON_INDIRECT1_START,4,2     ## @RADEON_INDIRECT1_START
	.comm	_RADEON_CP_RB_WPTR_DELAY,4,2    ## @RADEON_CP_RB_WPTR_DELAY
	.comm	_RADEON_CP_CSQ_CNTL,4,2         ## @RADEON_CP_CSQ_CNTL
	.comm	_RADEON_CSQ_PRIBM_INDBM,4,2     ## @RADEON_CSQ_PRIBM_INDBM
L_.str.3:                               ## @.str.3
	.asciz	"radeon: cp isn't working (%d).\n"

L_.str.4:                               ## @.str.4
	.asciz	"failed to get scratch reg for rptr save (%d).\n"

	.comm	_RADEON_BUF_SWAP_32BIT,4,2      ## @RADEON_BUF_SWAP_32BIT
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r100_cp_init                   ; -- Begin function r100_cp_init
	.p2align	2
_r100_cp_init:                          ; @r100_cp_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x22, x1
	mov	x19, x0
	ldr	x23, [x0, #8]
Lloh0:
	adrp	x25, _RADEON_RING_TYPE_GFX_INDEX@GOTPAGE
Lloh1:
	ldr	x25, [x25, _RADEON_RING_TYPE_GFX_INDEX@GOTPAGEOFF]
	ldr	x24, [x25]
	bl	_r100_debugfs_cp_init
	cbz	x0, LBB0_2
; %bb.1:
Lloh2:
	adrp	x0, l_.str@PAGE
Lloh3:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_ERROR
LBB0_2:
	ldr	w8, [x19, #40]
	cbz	w8, LBB0_6
LBB0_3:
	mov	w8, #24
	madd	x20, x24, x8, x23
	lsr	w0, w22, #3
	bl	_order_base_2
	mov	x22, x0
	add	w8, w0, #1
	mov	w9, #4
	lsl	w21, w9, w8
	mov	x0, x19
	bl	_r100_cp_load_microcode
Lloh4:
	adrp	x28, _RADEON_WB_CP_RPTR_OFFSET@GOTPAGE
Lloh5:
	ldr	x28, [x28, _RADEON_WB_CP_RPTR_OFFSET@GOTPAGEOFF]
	ldr	w3, [x28]
Lloh6:
	adrp	x8, _RADEON_CP_PACKET2@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_CP_PACKET2@GOTPAGEOFF]
Lloh8:
	ldr	w4, [x8]
	mov	x0, x19
	mov	x1, x20
	mov	x2, x21
	bl	_radeon_ring_init
	mov	x21, x0
	cbnz	w0, LBB0_10
; %bb.4:
	mov	w8, #15
	str	w8, [x20]
	mov	w0, #1816
	mov	w1, #64
	bl	_WREG32
Lloh9:
	adrp	x8, _RADEON_RB_BUFSZ@GOTPAGE
Lloh10:
	ldr	x8, [x8, _RADEON_RB_BUFSZ@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	mov	x1, x22
	bl	_REG_SET
	mov	x21, x0
Lloh12:
	adrp	x8, _RADEON_RB_BLKSZ@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RADEON_RB_BLKSZ@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	mov	w1, #9
	bl	_REG_SET
	orr	w21, w0, w21
Lloh15:
	adrp	x8, _RADEON_MAX_FETCH@GOTPAGE
Lloh16:
	ldr	x8, [x8, _RADEON_MAX_FETCH@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_REG_SET
Lloh18:
	adrp	x22, _RADEON_CP_RB_CNTL@GOTPAGE
Lloh19:
	ldr	x22, [x22, _RADEON_CP_RB_CNTL@GOTPAGEOFF]
	orr	w26, w21, w0
	ldr	w0, [x22]
Lloh20:
	adrp	x27, _RADEON_RB_NO_UPDATE@GOTPAGE
Lloh21:
	ldr	x27, [x27, _RADEON_RB_NO_UPDATE@GOTPAGEOFF]
	ldr	w8, [x27]
	orr	w1, w8, w26
	bl	_WREG32
	mov	w8, #24
	madd	x21, x24, x8, x23
	ldrsw	x1, [x21, #4]
Lloh22:
	adrp	x0, l_.str.2@PAGE
Lloh23:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	_DRM_INFO
Lloh24:
	adrp	x8, _RADEON_CP_RB_BASE@GOTPAGE
Lloh25:
	ldr	x8, [x8, _RADEON_CP_RB_BASE@GOTPAGEOFF]
Lloh26:
	ldr	w0, [x8]
	ldr	w1, [x21, #4]
	bl	_WREG32
	ldr	w0, [x22]
Lloh27:
	adrp	x8, _RADEON_RB_RPTR_WR_ENA@GOTPAGE
Lloh28:
	ldr	x8, [x8, _RADEON_RB_RPTR_WR_ENA@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	orr	w8, w8, w26
	ldr	w9, [x27]
	orr	w1, w8, w9
	bl	_WREG32
Lloh30:
	adrp	x8, _RADEON_CP_RB_RPTR_WR@GOTPAGE
Lloh31:
	ldr	x8, [x8, _RADEON_CP_RB_RPTR_WR@GOTPAGEOFF]
Lloh32:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	str	wzr, [x21, #8]
Lloh33:
	adrp	x8, _RADEON_CP_RB_WPTR@GOTPAGE
Lloh34:
	ldr	x8, [x8, _RADEON_CP_RB_WPTR@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh36:
	adrp	x8, _R_00070C_CP_RB_RPTR_ADDR@GOTPAGE
Lloh37:
	ldr	x8, [x8, _R_00070C_CP_RB_RPTR_ADDR@GOTPAGEOFF]
Lloh38:
	ldr	w21, [x8]
	ldr	w8, [x19, #24]
	ldr	w9, [x28]
	add	w8, w9, w8
	asr	w0, w8, #2
	bl	_S_00070C_RB_RPTR_ADDR
	mov	x1, x0
	mov	x0, x21
	bl	_WREG32
Lloh39:
	adrp	x8, _R_000774_SCRATCH_ADDR@GOTPAGE
Lloh40:
	ldr	x8, [x8, _R_000774_SCRATCH_ADDR@GOTPAGEOFF]
Lloh41:
	ldr	w0, [x8]
	ldr	w8, [x19, #24]
Lloh42:
	adrp	x9, _RADEON_WB_SCRATCH_OFFSET@GOTPAGE
Lloh43:
	ldr	x9, [x9, _RADEON_WB_SCRATCH_OFFSET@GOTPAGEOFF]
Lloh44:
	ldr	w9, [x9]
	add	w1, w9, w8
	bl	_WREG32
	ldr	x8, [x19, #32]
	ldr	w9, [x27]
	cmp	x8, #0
	mov	w8, #255
	csel	w1, wzr, w8, eq
	csel	w8, w9, wzr, eq
	orr	w21, w26, w8
Lloh45:
	adrp	x8, _R_000770_SCRATCH_UMSK@GOTPAGE
Lloh46:
	ldr	x8, [x8, _R_000770_SCRATCH_UMSK@GOTPAGEOFF]
Lloh47:
	ldr	w0, [x8]
	bl	_WREG32
	ldr	w0, [x22]
	mov	x1, x21
	bl	_WREG32
	mov	w0, #10
	bl	_udelay
Lloh48:
	adrp	x26, _RADEON_CP_CSQ_MODE@GOTPAGE
Lloh49:
	ldr	x26, [x26, _RADEON_CP_CSQ_MODE@GOTPAGEOFF]
	ldr	w21, [x26]
Lloh50:
	adrp	x8, _RADEON_INDIRECT2_START@GOTPAGE
Lloh51:
	ldr	x8, [x8, _RADEON_INDIRECT2_START@GOTPAGEOFF]
Lloh52:
	ldr	w0, [x8]
	mov	w1, #80
	bl	_REG_SET
	mov	x22, x0
Lloh53:
	adrp	x8, _RADEON_INDIRECT1_START@GOTPAGE
Lloh54:
	ldr	x8, [x8, _RADEON_INDIRECT1_START@GOTPAGEOFF]
Lloh55:
	ldr	w0, [x8]
	mov	w1, #16
	bl	_REG_SET
	orr	w1, w0, w22
	mov	x0, x21
	bl	_WREG32
Lloh56:
	adrp	x8, _RADEON_CP_RB_WPTR_DELAY@GOTPAGE
Lloh57:
	ldr	x8, [x8, _RADEON_CP_RB_WPTR_DELAY@GOTPAGEOFF]
Lloh58:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x26]
	mov	w1, #19789
	bl	_WREG32
Lloh59:
	adrp	x8, _RADEON_CP_CSQ_CNTL@GOTPAGE
Lloh60:
	ldr	x8, [x8, _RADEON_CP_CSQ_CNTL@GOTPAGEOFF]
Lloh61:
	ldr	w0, [x8]
Lloh62:
	adrp	x8, _RADEON_CSQ_PRIBM_INDBM@GOTPAGE
Lloh63:
	ldr	x8, [x8, _RADEON_CSQ_PRIBM_INDBM@GOTPAGEOFF]
Lloh64:
	ldr	w1, [x8]
	bl	_WREG32
	ldr	w0, [x19, #16]
	bl	_pci_set_master
	ldr	x1, [x25]
	ldr	x8, [x19, #8]
	mov	w9, #24
	madd	x2, x1, x9, x8
	mov	x0, x19
	bl	_radeon_ring_start
	ldr	x1, [x25]
	mov	x0, x19
	mov	x2, x20
	bl	_radeon_ring_test
	cbz	w0, LBB0_8
; %bb.5:
	mov	x21, x0
	str	x21, [sp]
Lloh65:
	adrp	x0, l_.str.3@PAGE
Lloh66:
	add	x0, x0, l_.str.3@PAGEOFF
	bl	_DRM_ERROR
	b	LBB0_10
LBB0_6:
	mov	x0, x19
	bl	_r100_cp_init_microcode
	cbz	w0, LBB0_3
; %bb.7:
	mov	x21, x0
Lloh67:
	adrp	x0, l_.str.1@PAGE
Lloh68:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_ERROR
	b	LBB0_10
LBB0_8:
	mov	w8, #24
	madd	x22, x24, x8, x23
	mov	w8, #1
	str	w8, [x22, #12]
	ldr	w1, [x19]
	mov	x0, x19
	bl	_radeon_ttm_set_active_vram_size
	ldr	x8, [x22, #16]!
	cbz	x8, LBB0_11
LBB0_9:
	mov	w21, #0
LBB0_10:
	mov	x0, x21
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
LBB0_11:
	mov	x0, x19
	mov	x1, x20
	bl	_radeon_ring_supports_scratch_reg
	cbz	x0, LBB0_9
; %bb.12:
	mov	x0, x19
	mov	x1, x22
	bl	_radeon_scratch_get
                                        ; kill: def $w0 killed $w0 def $x0
	cbz	w0, LBB0_9
; %bb.13:
	str	x0, [sp]
Lloh69:
	adrp	x0, l_.str.4@PAGE
Lloh70:
	add	x0, x0, l_.str.4@PAGEOFF
	bl	_DRM_ERROR
	mov	w21, #0
	str	xzr, [x22]
	b	LBB0_10
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpAdd	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpAdd	Lloh65, Lloh66
	.loh AdrpAdd	Lloh67, Lloh68
	.loh AdrpAdd	Lloh69, Lloh70
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_RING_TYPE_GFX_INDEX,8,3 ; @RADEON_RING_TYPE_GFX_INDEX
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Failed to register debugfs file for CP !\n"

l_.str.1:                               ; @.str.1
	.asciz	"Failed to load firmware!\n"

	.comm	_RADEON_WB_CP_RPTR_OFFSET,4,2   ; @RADEON_WB_CP_RPTR_OFFSET
	.comm	_RADEON_CP_PACKET2,4,2          ; @RADEON_CP_PACKET2
	.comm	_RADEON_RB_BUFSZ,4,2            ; @RADEON_RB_BUFSZ
	.comm	_RADEON_RB_BLKSZ,4,2            ; @RADEON_RB_BLKSZ
	.comm	_RADEON_MAX_FETCH,4,2           ; @RADEON_MAX_FETCH
	.comm	_RADEON_CP_RB_CNTL,4,2          ; @RADEON_CP_RB_CNTL
	.comm	_RADEON_RB_NO_UPDATE,4,2        ; @RADEON_RB_NO_UPDATE
l_.str.2:                               ; @.str.2
	.asciz	"radeon: ring at 0x%016lX\n"

	.comm	_RADEON_CP_RB_BASE,4,2          ; @RADEON_CP_RB_BASE
	.comm	_RADEON_RB_RPTR_WR_ENA,4,2      ; @RADEON_RB_RPTR_WR_ENA
	.comm	_RADEON_CP_RB_RPTR_WR,4,2       ; @RADEON_CP_RB_RPTR_WR
	.comm	_RADEON_CP_RB_WPTR,4,2          ; @RADEON_CP_RB_WPTR
	.comm	_R_00070C_CP_RB_RPTR_ADDR,4,2   ; @R_00070C_CP_RB_RPTR_ADDR
	.comm	_R_000774_SCRATCH_ADDR,4,2      ; @R_000774_SCRATCH_ADDR
	.comm	_RADEON_WB_SCRATCH_OFFSET,4,2   ; @RADEON_WB_SCRATCH_OFFSET
	.comm	_R_000770_SCRATCH_UMSK,4,2      ; @R_000770_SCRATCH_UMSK
	.comm	_RADEON_CP_CSQ_MODE,4,2         ; @RADEON_CP_CSQ_MODE
	.comm	_RADEON_INDIRECT2_START,4,2     ; @RADEON_INDIRECT2_START
	.comm	_RADEON_INDIRECT1_START,4,2     ; @RADEON_INDIRECT1_START
	.comm	_RADEON_CP_RB_WPTR_DELAY,4,2    ; @RADEON_CP_RB_WPTR_DELAY
	.comm	_RADEON_CP_CSQ_CNTL,4,2         ; @RADEON_CP_CSQ_CNTL
	.comm	_RADEON_CSQ_PRIBM_INDBM,4,2     ; @RADEON_CSQ_PRIBM_INDBM
l_.str.3:                               ; @.str.3
	.asciz	"radeon: cp isn't working (%d).\n"

l_.str.4:                               ; @.str.4
	.asciz	"failed to get scratch reg for rptr save (%d).\n"

	.comm	_RADEON_BUF_SWAP_32BIT,4,2      ; @RADEON_BUF_SWAP_32BIT
.subsections_via_symbols
