	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r600_copy_cpdma                ## -- Begin function r600_copy_cpdma
	.p2align	4, 0x90
_r600_copy_cpdma:                       ## @r600_copy_cpdma
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%r8, -64(%rbp)                  ## 8-byte Spill
	movl	%ecx, %ebx
	movl	%edx, %r14d
	movl	%esi, %r13d
	movq	%rdi, %r15
	movq	8(%rdi), %rax
	movslq	(%rax), %r12
	shlq	$2, %r12
	addq	(%rdi), %r12
	leaq	-48(%rbp), %rdi
	callq	_radeon_sync_create
	movq	_RADEON_GPU_PAGE_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %ebx
	movl	%ebx, %edi
	movl	$2097151, %esi                  ## imm = 0x1FFFFF
	callq	_DIV_ROUND_UP
                                        ## kill: def $eax killed $eax def $rax
	movq	%rax, -72(%rbp)                 ## 8-byte Spill
	leal	(%rax,%rax,2), %eax
	leal	(%rax,%rax), %edx
	addl	$24, %edx
	movq	%r15, -56(%rbp)                 ## 8-byte Spill
	movq	%r15, %rdi
	movq	%r12, %rsi
	callq	_radeon_ring_lock
	testl	%eax, %eax
	je	LBB0_2
## %bb.1:
	movl	%eax, %r15d
	leaq	L_.str(%rip), %rdi
	movl	%eax, %esi
	callq	_DRM_ERROR
	leaq	-48(%rbp), %rsi
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	xorl	%edx, %edx
	callq	_radeon_sync_free
	movl	%r15d, %edi
	callq	_ERR_PTR
	jmp	LBB0_9
LBB0_2:
	leaq	-48(%rbp), %rsi
	movq	-56(%rbp), %r15                 ## 8-byte Reload
	movq	%r15, %rdi
	movq	-64(%rbp), %rdx                 ## 8-byte Reload
	xorl	%ecx, %ecx
	callq	_radeon_sync_resv
	movl	(%r12), %edx
	movq	%r15, %rdi
	leaq	-48(%rbp), %rsi
	callq	_radeon_sync_rings
	movq	_PACKET3_SET_CONFIG_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_PACKET3
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movq	_WAIT_UNTIL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PACKET3_SET_CONFIG_REG_OFFSET@GOTPCREL(%rip), %rax
	subl	(%rax), %esi
	sarl	$2, %esi
	movq	%r12, %rdi
	callq	_radeon_ring_write
	movq	_WAIT_3D_IDLE_bit@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, -80(%rbp)                 ## 8-byte Spill
	movq	%r12, %rdi
	callq	_radeon_ring_write
	movq	-72(%rbp), %rax                 ## 8-byte Reload
	testl	%eax, %eax
	jg	LBB0_3
LBB0_6:
	movq	_PACKET3_SET_CONFIG_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_PACKET3
	movq	-80(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movq	_WAIT_UNTIL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PACKET3_SET_CONFIG_REG_OFFSET@GOTPCREL(%rip), %rax
	subl	(%rax), %esi
	sarl	$2, %esi
	movq	%rbx, %rdi
	callq	_radeon_ring_write
	movq	_WAIT_CP_DMA_IDLE_bit@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_radeon_ring_write
	movl	(%rbx), %edx
	leaq	-88(%rbp), %rsi
	movq	-56(%rbp), %r15                 ## 8-byte Reload
	movq	%r15, %rdi
	callq	_radeon_fence_emit
	testl	%eax, %eax
	je	LBB0_8
## %bb.7:
	movl	%eax, %r14d
	movq	%r15, %rdi
	movq	%rbx, %rsi
	callq	_radeon_ring_unlock_undo
	leaq	-48(%rbp), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_radeon_sync_free
	movl	%r14d, %edi
	callq	_ERR_PTR
	jmp	LBB0_9
	.p2align	4, 0x90
LBB0_5:                                 ##   in Loop: Header=BB0_3 Depth=1
	movzbl	%al, %r12d
	orl	%ecx, %r12d
	movq	_PACKET3_CP_DMA@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$4, %esi
	callq	_PACKET3
	movq	-80(%rbp), %r14                 ## 8-byte Reload
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movl	%r13d, %edi
	callq	_lower_32_bits
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movq	%r14, %rdi
	movl	%r12d, %esi
	callq	_radeon_ring_write
	movl	-64(%rbp), %r12d                ## 4-byte Reload
	movl	%r12d, %edi
	callq	_lower_32_bits
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movl	%r12d, %edi
	callq	_upper_32_bits
	movzbl	%al, %esi
	movq	%r14, %rdi
	callq	_radeon_ring_write
	movq	%r14, %rdi
	movl	%r12d, %r14d
	movl	%r15d, %esi
	callq	_radeon_ring_write
	addl	%r15d, %r13d
	addl	%r15d, %r14d
	movq	-72(%rbp), %rax                 ## 8-byte Reload
	decl	%eax
	je	LBB0_6
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movq	%rax, -72(%rbp)                 ## 8-byte Spill
	movl	%r14d, -64(%rbp)                ## 4-byte Spill
	cmpl	$2097151, %ebx                  ## imm = 0x1FFFFF
	movl	$2097151, %r15d                 ## imm = 0x1FFFFF
	cmovll	%ebx, %r15d
	movl	%r13d, %edi
	callq	_upper_32_bits
	xorl	%ecx, %ecx
	subl	%r15d, %ebx
	jne	LBB0_5
## %bb.4:                               ##   in Loop: Header=BB0_3 Depth=1
	movq	_PACKET3_CP_DMA_CP_SYNC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	jmp	LBB0_5
LBB0_8:
	movq	%r15, %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	_radeon_ring_unlock_commit
	movq	-88(%rbp), %rdx
	leaq	-48(%rbp), %rsi
	movq	%r15, %rdi
	callq	_radeon_sync_free
	movq	-88(%rbp), %rax
LBB0_9:
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_GPU_PAGE_SHIFT,4,2      ## @RADEON_GPU_PAGE_SHIFT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"radeon: moving bo (%d).\n"

	.comm	_PACKET3_SET_CONFIG_REG,4,2     ## @PACKET3_SET_CONFIG_REG
	.comm	_WAIT_UNTIL,4,2                 ## @WAIT_UNTIL
	.comm	_PACKET3_SET_CONFIG_REG_OFFSET,4,2 ## @PACKET3_SET_CONFIG_REG_OFFSET
	.comm	_WAIT_3D_IDLE_bit,4,2           ## @WAIT_3D_IDLE_bit
	.comm	_PACKET3_CP_DMA_CP_SYNC,4,2     ## @PACKET3_CP_DMA_CP_SYNC
	.comm	_PACKET3_CP_DMA,4,2             ## @PACKET3_CP_DMA
	.comm	_WAIT_CP_DMA_IDLE_bit,4,2       ## @WAIT_CP_DMA_IDLE_bit
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r600_copy_cpdma                ; -- Begin function r600_copy_cpdma
	.p2align	2
_r600_copy_cpdma:                       ; @r600_copy_cpdma
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #128
	.cfi_def_cfa_offset 128
	stp	x28, x27, [sp, #32]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #48]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #64]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #80]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #96]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #112]            ; 16-byte Folded Spill
	add	x29, sp, #112
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x25, x4
	mov	x23, x3
	mov	x21, x2
	mov	x22, x1
	mov	x19, x0
	ldp	x9, x8, [x0]
	ldrsw	x8, [x8]
	add	x20, x9, x8, lsl #2
	add	x0, sp, #16
	bl	_radeon_sync_create
Lloh0:
	adrp	x8, _RADEON_GPU_PAGE_SHIFT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_GPU_PAGE_SHIFT@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	lsl	w23, w23, w8
	mov	x0, x23
	mov	w1, #2097151
	bl	_DIV_ROUND_UP
	mov	x24, x0
	mov	w8, #6
	orr	w9, wzr, #0x18
	madd	w2, w0, w8, w9
	mov	x0, x19
	mov	x1, x20
	bl	_radeon_ring_lock
	cbz	w0, LBB0_2
; %bb.1:
	mov	x26, x0
Lloh3:
	adrp	x0, l_.str@PAGE
Lloh4:
	add	x0, x0, l_.str@PAGEOFF
	mov	x1, x26
	bl	_DRM_ERROR
	add	x1, sp, #16
	mov	x0, x19
	mov	x2, #0
	bl	_radeon_sync_free
	mov	x0, x26
	bl	_ERR_PTR
	b	LBB0_8
LBB0_2:
	add	x1, sp, #16
	mov	x0, x19
	mov	x2, x25
	mov	w3, #0
	bl	_radeon_sync_resv
	ldr	w2, [x20]
	add	x1, sp, #16
	str	x19, [sp, #8]                   ; 8-byte Folded Spill
	mov	x0, x19
	bl	_radeon_sync_rings
Lloh5:
	adrp	x8, _PACKET3_SET_CONFIG_REG@GOTPAGE
Lloh6:
	ldr	x8, [x8, _PACKET3_SET_CONFIG_REG@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x20
	bl	_radeon_ring_write
Lloh8:
	adrp	x8, _WAIT_UNTIL@GOTPAGE
Lloh9:
	ldr	x8, [x8, _WAIT_UNTIL@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
Lloh11:
	adrp	x9, _PACKET3_SET_CONFIG_REG_OFFSET@GOTPAGE
Lloh12:
	ldr	x9, [x9, _PACKET3_SET_CONFIG_REG_OFFSET@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	sub	w8, w8, w9
	asr	w1, w8, #2
	mov	x0, x20
	bl	_radeon_ring_write
Lloh14:
	adrp	x8, _WAIT_3D_IDLE_bit@GOTPAGE
Lloh15:
	ldr	x8, [x8, _WAIT_3D_IDLE_bit@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_radeon_ring_write
	cmp	w24, #1
	b.lt	LBB0_5
; %bb.3:
	mov	w28, #2097151
Lloh17:
	adrp	x27, _PACKET3_CP_DMA_CP_SYNC@GOTPAGE
Lloh18:
	ldr	x27, [x27, _PACKET3_CP_DMA_CP_SYNC@GOTPAGEOFF]
Lloh19:
	adrp	x19, _PACKET3_CP_DMA@GOTPAGE
Lloh20:
	ldr	x19, [x19, _PACKET3_CP_DMA@GOTPAGEOFF]
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
	cmp	w23, w28
	csel	w25, w23, w28, lt
	sub	w23, w23, w25
	mov	x0, x22
	bl	_upper_32_bits
	and	w8, w0, #0xff
	ldr	w9, [x27]
	cmp	w23, #0
	csel	w9, w9, wzr, eq
	orr	w26, w9, w8
	ldr	w0, [x19]
	mov	w1, #4
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x20
	bl	_radeon_ring_write
	mov	x0, x22
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_radeon_ring_write
	mov	x0, x20
	mov	x1, x26
	bl	_radeon_ring_write
	mov	x0, x21
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_radeon_ring_write
	mov	x0, x21
	bl	_upper_32_bits
	and	w1, w0, #0xff
	mov	x0, x20
	bl	_radeon_ring_write
	mov	x0, x20
	mov	x1, x25
	bl	_radeon_ring_write
	add	w22, w25, w22
	add	w21, w25, w21
	subs	w24, w24, #1
	b.ne	LBB0_4
LBB0_5:
Lloh21:
	adrp	x8, _PACKET3_SET_CONFIG_REG@GOTPAGE
Lloh22:
	ldr	x8, [x8, _PACKET3_SET_CONFIG_REG@GOTPAGEOFF]
Lloh23:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x20
	bl	_radeon_ring_write
Lloh24:
	adrp	x8, _WAIT_UNTIL@GOTPAGE
Lloh25:
	ldr	x8, [x8, _WAIT_UNTIL@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
Lloh27:
	adrp	x9, _PACKET3_SET_CONFIG_REG_OFFSET@GOTPAGE
Lloh28:
	ldr	x9, [x9, _PACKET3_SET_CONFIG_REG_OFFSET@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	sub	w8, w8, w9
	asr	w1, w8, #2
	mov	x0, x20
	bl	_radeon_ring_write
Lloh30:
	adrp	x8, _WAIT_CP_DMA_IDLE_bit@GOTPAGE
Lloh31:
	ldr	x8, [x8, _WAIT_CP_DMA_IDLE_bit@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_radeon_ring_write
	ldr	w2, [x20]
	add	x1, sp, #24
	ldr	x19, [sp, #8]                   ; 8-byte Folded Reload
	mov	x0, x19
	bl	_radeon_fence_emit
	cbz	w0, LBB0_7
; %bb.6:
	mov	x21, x0
	mov	x0, x19
	mov	x1, x20
	bl	_radeon_ring_unlock_undo
	add	x1, sp, #16
	mov	x0, x19
	mov	x2, #0
	bl	_radeon_sync_free
	mov	x0, x21
	bl	_ERR_PTR
	b	LBB0_8
LBB0_7:
	mov	x0, x19
	mov	x1, x20
	mov	w2, #0
	bl	_radeon_ring_unlock_commit
	ldr	x2, [sp, #24]
	add	x1, sp, #16
	mov	x0, x19
	bl	_radeon_sync_free
	ldr	x0, [sp, #24]
LBB0_8:
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_GPU_PAGE_SHIFT,4,2      ; @RADEON_GPU_PAGE_SHIFT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"radeon: moving bo (%d).\n"

	.comm	_PACKET3_SET_CONFIG_REG,4,2     ; @PACKET3_SET_CONFIG_REG
	.comm	_WAIT_UNTIL,4,2                 ; @WAIT_UNTIL
	.comm	_PACKET3_SET_CONFIG_REG_OFFSET,4,2 ; @PACKET3_SET_CONFIG_REG_OFFSET
	.comm	_WAIT_3D_IDLE_bit,4,2           ; @WAIT_3D_IDLE_bit
	.comm	_PACKET3_CP_DMA_CP_SYNC,4,2     ; @PACKET3_CP_DMA_CP_SYNC
	.comm	_PACKET3_CP_DMA,4,2             ; @PACKET3_CP_DMA
	.comm	_WAIT_CP_DMA_IDLE_bit,4,2       ; @WAIT_CP_DMA_IDLE_bit
.subsections_via_symbols
