	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function uvd_v7_0_ring_patch_cs_in_place
_uvd_v7_0_ring_patch_cs_in_place:       ## @uvd_v7_0_ring_patch_cs_in_place
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %r15
	movq	16(%rdi), %rax
	movq	(%rax), %rax
	movl	(%rax), %edi
	callq	_to_amdgpu_ring
	cmpl	$0, (%rax)
	je	LBB0_4
## %bb.1:
	movq	8(%r15), %rax
	movq	(%rax), %r12
	cmpl	$0, (%r12,%r14,4)
	je	LBB0_4
## %bb.2:
	xorl	%ebx, %ebx
	movq	_UVD_HWIP@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	callq	_amdgpu_get_ib_value
	movq	(%r15), %rcx
	movq	(%rcx), %rcx
	movq	(%r13), %rdx
	movq	(%rcx,%rdx,8), %rcx
	movq	(%rcx), %rdx
	movq	8(%rcx), %rcx
	subq	8(%rdx), %rax
	addq	8(%rcx), %rax
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	movq	%rax, %rcx
	callq	_amdgpu_set_ib_value
	addl	$2, %ebx
	cmpl	(%r12,%r14,4), %ebx
	jb	LBB0_3
LBB0_4:
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_UVD_HWIP,8,3                   ## @UVD_HWIP
	.no_dead_strip	_uvd_v7_0_ring_patch_cs_in_place
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function uvd_v7_0_ring_patch_cs_in_place
_uvd_v7_0_ring_patch_cs_in_place:       ; @uvd_v7_0_ring_patch_cs_in_place
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x1
	mov	x20, x0
	ldr	x8, [x0, #16]
	ldr	x8, [x8]
	ldr	w0, [x8]
	bl	_to_amdgpu_ring
	ldr	w8, [x0]
	cbz	w8, LBB0_4
; %bb.1:
	ldr	x8, [x20, #8]
	ldr	x22, [x8]
	ldr	w8, [x22, x19, lsl #2]
	cbz	w8, LBB0_4
; %bb.2:
	mov	w21, #0
Lloh0:
	adrp	x23, _UVD_HWIP@GOTPAGE
Lloh1:
	ldr	x23, [x23, _UVD_HWIP@GOTPAGEOFF]
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_amdgpu_get_ib_value
	ldr	x8, [x20]
	ldr	x8, [x8]
	ldr	x9, [x23]
	ldr	x8, [x8, x9, lsl #3]
	ldp	x9, x8, [x8]
	ldr	x9, [x9, #8]
	ldr	x8, [x8, #8]
	sub	x9, x0, x9
	add	x3, x9, x8
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	bl	_amdgpu_set_ib_value
	add	w21, w21, #2
	ldr	w8, [x22, x19, lsl #2]
	cmp	w21, w8
	b.lo	LBB0_3
LBB0_4:
	mov	w0, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_UVD_HWIP,8,3                   ; @UVD_HWIP
	.no_dead_strip	_uvd_v7_0_ring_patch_cs_in_place
.subsections_via_symbols
