	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function si_set_power_state_conditionally_enable_ulv
_si_set_power_state_conditionally_enable_ulv: ## @si_set_power_state_conditionally_enable_ulv
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r15
	movq	%rdi, %r14
	callq	_si_get_pi
	xorl	%ebx, %ebx
	cmpq	$0, (%rax)
	je	LBB0_3
## %bb.1:
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	_si_is_state_ulv_compatible
	testq	%rax, %rax
	je	LBB0_3
## %bb.2:
	movq	_PPSMC_MSG_EnableULV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_amdgpu_si_send_msg_to_smc
	movq	_PPSMC_Result_OK@GOTPCREL(%rip), %rcx
	movq	_EINVAL@GOTPCREL(%rip), %rdx
	xorl	%esi, %esi
	xorl	%ebx, %ebx
	subl	(%rdx), %ebx
	cmpq	(%rcx), %rax
	cmovel	%esi, %ebx
LBB0_3:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PPSMC_MSG_EnableULV,4,2        ## @PPSMC_MSG_EnableULV
	.comm	_PPSMC_Result_OK,8,3            ## @PPSMC_Result_OK
	.comm	_EINVAL,4,2                     ## @EINVAL
	.no_dead_strip	_si_set_power_state_conditionally_enable_ulv
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function si_set_power_state_conditionally_enable_ulv
_si_set_power_state_conditionally_enable_ulv: ; @si_set_power_state_conditionally_enable_ulv
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x20, x1
	mov	x19, x0
	bl	_si_get_pi
	ldr	x8, [x0]
	cbz	x8, LBB0_3
; %bb.1:
	mov	x0, x19
	mov	x1, x20
	bl	_si_is_state_ulv_compatible
	cbz	x0, LBB0_4
; %bb.2:
Lloh0:
	adrp	x8, _PPSMC_MSG_EnableULV@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PPSMC_MSG_EnableULV@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_amdgpu_si_send_msg_to_smc
Lloh3:
	adrp	x8, _PPSMC_Result_OK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PPSMC_Result_OK@GOTPAGEOFF]
Lloh5:
	ldr	x8, [x8]
Lloh6:
	adrp	x9, _EINVAL@GOTPAGE
Lloh7:
	ldr	x9, [x9, _EINVAL@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	cmp	x0, x8
	csneg	w0, wzr, w9, eq
	b	LBB0_4
LBB0_3:
	mov	w0, #0
LBB0_4:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_PPSMC_MSG_EnableULV,4,2        ; @PPSMC_MSG_EnableULV
	.comm	_PPSMC_Result_OK,8,3            ; @PPSMC_Result_OK
	.comm	_EINVAL,4,2                     ; @EINVAL
	.no_dead_strip	_si_set_power_state_conditionally_enable_ulv
.subsections_via_symbols
