	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function sun4i_hdmi_mode_set
_sun4i_hdmi_mode_set:                   ## @sun4i_hdmi_mode_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r15
	callq	_drm_encoder_to_sun4i_hdmi
	movq	%rax, %r14
	movl	20(%rax), %edi
	imull	$1000, (%r15), %esi             ## imm = 0x3E8
	callq	_clk_set_rate
	movl	16(%r14), %edi
	imull	$1000, (%r15), %esi             ## imm = 0x3E8
	callq	_clk_set_rate
	movq	_SUN4I_HDMI_UNKNOWN_INPUT_SYNC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_SUN4I_HDMI_UNKNOWN_REG@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%r14), %rsi
	callq	_writel
	movq	_SUN4I_HDMI_PAD_CTRL1_REG@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	addq	(%r14), %rdi
	callq	_readl
	movq	_SUN4I_HDMI_PAD_CTRL1_HALVE_CLK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	8(%r14), %rcx
	orl	(%rcx), %eax
	movq	(%rbx), %rsi
	addq	(%r14), %rsi
	movl	%eax, %edi
	callq	_writel
	movq	(%rbx), %rdi
	addq	(%r14), %rdi
	callq	_readl
	movl	4(%r15), %edi
	callq	_SUN4I_HDMI_VID_TIMING_X
	movl	%eax, %ebx
	movl	8(%r15), %edi
	callq	_SUN4I_HDMI_VID_TIMING_Y
	orl	%eax, %ebx
	movq	_SUN4I_HDMI_VID_TIMING_ACT_REG@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%r14), %rsi
	movl	%ebx, %edi
	callq	_writel
	movl	12(%r15), %edi
	movl	20(%r15), %ebx
	subl	16(%r15), %edi
	subl	24(%r15), %ebx
	callq	_SUN4I_HDMI_VID_TIMING_X
	movl	%eax, %r12d
	movl	%ebx, %edi
	callq	_SUN4I_HDMI_VID_TIMING_Y
	orl	%eax, %r12d
	movq	_SUN4I_HDMI_VID_TIMING_BP_REG@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%r14), %rsi
	movl	%r12d, %edi
	callq	_writel
	movl	16(%r15), %edi
	movl	24(%r15), %ebx
	subl	4(%r15), %edi
	subl	8(%r15), %ebx
	callq	_SUN4I_HDMI_VID_TIMING_X
	movl	%eax, %r12d
	movl	%ebx, %edi
	callq	_SUN4I_HDMI_VID_TIMING_Y
	orl	%eax, %r12d
	movq	_SUN4I_HDMI_VID_TIMING_FP_REG@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%r14), %rsi
	movl	%r12d, %edi
	callq	_writel
	movl	28(%r15), %edi
	movl	32(%r15), %ebx
	subl	16(%r15), %edi
	subl	24(%r15), %ebx
	callq	_SUN4I_HDMI_VID_TIMING_X
	movl	%eax, %r12d
	movl	%ebx, %edi
	callq	_SUN4I_HDMI_VID_TIMING_Y
	orl	%eax, %r12d
	movq	_SUN4I_HDMI_VID_TIMING_SPW_REG@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%r14), %rsi
	movl	%r12d, %edi
	callq	_writel
	movq	_SUN4I_HDMI_VID_TIMING_POL_TX_CLK@GOTPCREL(%rip), %rcx
	movl	36(%r15), %eax
	movq	_DRM_MODE_FLAG_PHSYNC@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edi
	andl	%eax, %edi
	je	LBB0_2
## %bb.1:
	movq	_SUN4I_HDMI_VID_TIMING_POL_HSYNC@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edi
LBB0_2:
	orl	(%rcx), %edi
	movq	_DRM_MODE_FLAG_PVSYNC@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	je	LBB0_4
## %bb.3:
	movq	_SUN4I_HDMI_VID_TIMING_POL_VSYNC@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_4:
	orl	%eax, %edi
	movq	_SUN4I_HDMI_VID_TIMING_POL_REG@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%r14), %rsi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_writel                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_SUN4I_HDMI_UNKNOWN_INPUT_SYNC,4,2 ## @SUN4I_HDMI_UNKNOWN_INPUT_SYNC
	.comm	_SUN4I_HDMI_UNKNOWN_REG,8,3     ## @SUN4I_HDMI_UNKNOWN_REG
	.comm	_SUN4I_HDMI_PAD_CTRL1_REG,8,3   ## @SUN4I_HDMI_PAD_CTRL1_REG
	.comm	_SUN4I_HDMI_PAD_CTRL1_HALVE_CLK,4,2 ## @SUN4I_HDMI_PAD_CTRL1_HALVE_CLK
	.comm	_SUN4I_HDMI_VID_TIMING_ACT_REG,8,3 ## @SUN4I_HDMI_VID_TIMING_ACT_REG
	.comm	_SUN4I_HDMI_VID_TIMING_BP_REG,8,3 ## @SUN4I_HDMI_VID_TIMING_BP_REG
	.comm	_SUN4I_HDMI_VID_TIMING_FP_REG,8,3 ## @SUN4I_HDMI_VID_TIMING_FP_REG
	.comm	_SUN4I_HDMI_VID_TIMING_SPW_REG,8,3 ## @SUN4I_HDMI_VID_TIMING_SPW_REG
	.comm	_SUN4I_HDMI_VID_TIMING_POL_TX_CLK,4,2 ## @SUN4I_HDMI_VID_TIMING_POL_TX_CLK
	.comm	_DRM_MODE_FLAG_PHSYNC,4,2       ## @DRM_MODE_FLAG_PHSYNC
	.comm	_SUN4I_HDMI_VID_TIMING_POL_HSYNC,4,2 ## @SUN4I_HDMI_VID_TIMING_POL_HSYNC
	.comm	_DRM_MODE_FLAG_PVSYNC,4,2       ## @DRM_MODE_FLAG_PVSYNC
	.comm	_SUN4I_HDMI_VID_TIMING_POL_VSYNC,4,2 ## @SUN4I_HDMI_VID_TIMING_POL_VSYNC
	.comm	_SUN4I_HDMI_VID_TIMING_POL_REG,8,3 ## @SUN4I_HDMI_VID_TIMING_POL_REG
	.no_dead_strip	_sun4i_hdmi_mode_set
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function sun4i_hdmi_mode_set
_sun4i_hdmi_mode_set:                   ; @sun4i_hdmi_mode_set
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	bl	_drm_encoder_to_sun4i_hdmi
	mov	x19, x0
	ldr	w0, [x0, #20]
	ldr	w8, [x20]
	mov	w21, #1000
	mul	w1, w8, w21
	bl	_clk_set_rate
	ldr	w0, [x19, #16]
	ldr	w8, [x20]
	mul	w1, w8, w21
	bl	_clk_set_rate
Lloh0:
	adrp	x8, _SUN4I_HDMI_UNKNOWN_INPUT_SYNC@GOTPAGE
Lloh1:
	ldr	x8, [x8, _SUN4I_HDMI_UNKNOWN_INPUT_SYNC@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	ldr	x8, [x19]
Lloh3:
	adrp	x9, _SUN4I_HDMI_UNKNOWN_REG@GOTPAGE
Lloh4:
	ldr	x9, [x9, _SUN4I_HDMI_UNKNOWN_REG@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
	ldr	x8, [x19]
Lloh6:
	adrp	x21, _SUN4I_HDMI_PAD_CTRL1_REG@GOTPAGE
Lloh7:
	ldr	x21, [x21, _SUN4I_HDMI_PAD_CTRL1_REG@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_readl
Lloh8:
	adrp	x8, _SUN4I_HDMI_PAD_CTRL1_HALVE_CLK@GOTPAGE
Lloh9:
	ldr	x8, [x8, _SUN4I_HDMI_PAD_CTRL1_HALVE_CLK@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	and	w8, w8, w0
	ldp	x10, x9, [x19]
	ldr	w9, [x9]
	orr	w0, w9, w8
	ldr	x8, [x21]
	add	x1, x8, x10
	bl	_writel
	ldr	x8, [x19]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_readl
	ldr	w0, [x20, #4]
	bl	_SUN4I_HDMI_VID_TIMING_X
	mov	x21, x0
	ldr	w0, [x20, #8]
	bl	_SUN4I_HDMI_VID_TIMING_Y
	orr	w0, w0, w21
	ldr	x8, [x19]
Lloh11:
	adrp	x9, _SUN4I_HDMI_VID_TIMING_ACT_REG@GOTPAGE
Lloh12:
	ldr	x9, [x9, _SUN4I_HDMI_VID_TIMING_ACT_REG@GOTPAGEOFF]
Lloh13:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
	ldp	w8, w9, [x20, #12]
	sub	w0, w8, w9
	ldp	w8, w9, [x20, #20]
	sub	w21, w8, w9
	bl	_SUN4I_HDMI_VID_TIMING_X
	mov	x22, x0
	mov	x0, x21
	bl	_SUN4I_HDMI_VID_TIMING_Y
	orr	w0, w0, w22
	ldr	x8, [x19]
Lloh14:
	adrp	x9, _SUN4I_HDMI_VID_TIMING_BP_REG@GOTPAGE
Lloh15:
	ldr	x9, [x9, _SUN4I_HDMI_VID_TIMING_BP_REG@GOTPAGEOFF]
Lloh16:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
	ldr	w8, [x20, #16]
	ldp	w9, w10, [x20, #4]
	sub	w0, w8, w9
	ldr	w8, [x20, #24]
	sub	w21, w8, w10
	bl	_SUN4I_HDMI_VID_TIMING_X
	mov	x22, x0
	mov	x0, x21
	bl	_SUN4I_HDMI_VID_TIMING_Y
	orr	w0, w0, w22
	ldr	x8, [x19]
Lloh17:
	adrp	x9, _SUN4I_HDMI_VID_TIMING_FP_REG@GOTPAGE
Lloh18:
	ldr	x9, [x9, _SUN4I_HDMI_VID_TIMING_FP_REG@GOTPAGEOFF]
Lloh19:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
	ldr	w8, [x20, #16]
	ldp	w10, w9, [x20, #24]
	sub	w0, w9, w8
	ldr	w8, [x20, #32]
	sub	w21, w8, w10
	bl	_SUN4I_HDMI_VID_TIMING_X
	mov	x22, x0
	mov	x0, x21
	bl	_SUN4I_HDMI_VID_TIMING_Y
	orr	w0, w0, w22
	ldr	x8, [x19]
Lloh20:
	adrp	x9, _SUN4I_HDMI_VID_TIMING_SPW_REG@GOTPAGE
Lloh21:
	ldr	x9, [x9, _SUN4I_HDMI_VID_TIMING_SPW_REG@GOTPAGEOFF]
Lloh22:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
Lloh23:
	adrp	x8, _SUN4I_HDMI_VID_TIMING_POL_TX_CLK@GOTPAGE
Lloh24:
	ldr	x8, [x8, _SUN4I_HDMI_VID_TIMING_POL_TX_CLK@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
Lloh26:
	adrp	x9, _DRM_MODE_FLAG_PHSYNC@GOTPAGE
Lloh27:
	ldr	x9, [x9, _DRM_MODE_FLAG_PHSYNC@GOTPAGEOFF]
	ldr	w10, [x20, #36]
Lloh28:
	ldr	w9, [x9]
Lloh29:
	adrp	x11, _SUN4I_HDMI_VID_TIMING_POL_HSYNC@GOTPAGE
Lloh30:
	ldr	x11, [x11, _SUN4I_HDMI_VID_TIMING_POL_HSYNC@GOTPAGEOFF]
Lloh31:
	ldr	w11, [x11]
	tst	w9, w10
	csel	w9, wzr, w11, eq
	orr	w8, w9, w8
Lloh32:
	adrp	x9, _DRM_MODE_FLAG_PVSYNC@GOTPAGE
Lloh33:
	ldr	x9, [x9, _DRM_MODE_FLAG_PVSYNC@GOTPAGEOFF]
Lloh34:
	adrp	x11, _SUN4I_HDMI_VID_TIMING_POL_VSYNC@GOTPAGE
Lloh35:
	ldr	x11, [x11, _SUN4I_HDMI_VID_TIMING_POL_VSYNC@GOTPAGEOFF]
Lloh36:
	ldr	w9, [x9]
Lloh37:
	ldr	w11, [x11]
	tst	w9, w10
	csel	w9, wzr, w11, eq
	orr	w0, w8, w9
	ldr	x8, [x19]
Lloh38:
	adrp	x9, _SUN4I_HDMI_VID_TIMING_POL_REG@GOTPAGE
Lloh39:
	ldr	x9, [x9, _SUN4I_HDMI_VID_TIMING_POL_REG@GOTPAGEOFF]
Lloh40:
	ldr	x9, [x9]
	add	x1, x9, x8
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_writel
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh36
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_SUN4I_HDMI_UNKNOWN_INPUT_SYNC,4,2 ; @SUN4I_HDMI_UNKNOWN_INPUT_SYNC
	.comm	_SUN4I_HDMI_UNKNOWN_REG,8,3     ; @SUN4I_HDMI_UNKNOWN_REG
	.comm	_SUN4I_HDMI_PAD_CTRL1_REG,8,3   ; @SUN4I_HDMI_PAD_CTRL1_REG
	.comm	_SUN4I_HDMI_PAD_CTRL1_HALVE_CLK,4,2 ; @SUN4I_HDMI_PAD_CTRL1_HALVE_CLK
	.comm	_SUN4I_HDMI_VID_TIMING_ACT_REG,8,3 ; @SUN4I_HDMI_VID_TIMING_ACT_REG
	.comm	_SUN4I_HDMI_VID_TIMING_BP_REG,8,3 ; @SUN4I_HDMI_VID_TIMING_BP_REG
	.comm	_SUN4I_HDMI_VID_TIMING_FP_REG,8,3 ; @SUN4I_HDMI_VID_TIMING_FP_REG
	.comm	_SUN4I_HDMI_VID_TIMING_SPW_REG,8,3 ; @SUN4I_HDMI_VID_TIMING_SPW_REG
	.comm	_SUN4I_HDMI_VID_TIMING_POL_TX_CLK,4,2 ; @SUN4I_HDMI_VID_TIMING_POL_TX_CLK
	.comm	_DRM_MODE_FLAG_PHSYNC,4,2       ; @DRM_MODE_FLAG_PHSYNC
	.comm	_SUN4I_HDMI_VID_TIMING_POL_HSYNC,4,2 ; @SUN4I_HDMI_VID_TIMING_POL_HSYNC
	.comm	_DRM_MODE_FLAG_PVSYNC,4,2       ; @DRM_MODE_FLAG_PVSYNC
	.comm	_SUN4I_HDMI_VID_TIMING_POL_VSYNC,4,2 ; @SUN4I_HDMI_VID_TIMING_POL_VSYNC
	.comm	_SUN4I_HDMI_VID_TIMING_POL_REG,8,3 ; @SUN4I_HDMI_VID_TIMING_POL_REG
	.no_dead_strip	_sun4i_hdmi_mode_set
.subsections_via_symbols
