	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v8_0_init_gds_vmid
_gfx_v8_0_init_gds_vmid:                ## @gfx_v8_0_init_gds_vmid
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	xorl	%ebx, %ebx
	movq	_amdgpu_gds_reg_offset@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_1:                                 ## =>This Inner Loop Header: Depth=1
	movq	(%r14), %rax
	movl	28(%rax,%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%r14), %rax
	movl	24(%rax,%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%r14), %rax
	movl	20(%rax,%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%r14), %rax
	movl	16(%rax,%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	addq	$16, %rbx
	cmpq	$240, %rbx
	jne	LBB0_1
## %bb.2:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_amdgpu_gds_reg_offset,8,3      ## @amdgpu_gds_reg_offset
	.no_dead_strip	_gfx_v8_0_init_gds_vmid
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v8_0_init_gds_vmid
_gfx_v8_0_init_gds_vmid:                ; @gfx_v8_0_init_gds_vmid
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, #0
Lloh0:
	adrp	x20, _amdgpu_gds_reg_offset@GOTPAGE
Lloh1:
	ldr	x20, [x20, _amdgpu_gds_reg_offset@GOTPAGEOFF]
LBB0_1:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x20]
	add	x8, x8, x19
	ldr	w0, [x8, #28]
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x20]
	add	x8, x8, x19
	ldr	w0, [x8, #24]
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x20]
	add	x8, x8, x19
	ldr	w0, [x8, #20]
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x20]
	add	x8, x8, x19
	ldr	w0, [x8, #16]
	mov	w1, #0
	bl	_WREG32
	add	x19, x19, #16
	cmp	x19, #240
	b.ne	LBB0_1
; %bb.2:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_amdgpu_gds_reg_offset,8,3      ; @amdgpu_gds_reg_offset
	.no_dead_strip	_gfx_v8_0_init_gds_vmid
.subsections_via_symbols
