	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_rv770_set_clk_bypass_mode      ## -- Begin function rv770_set_clk_bypass_mode
	.p2align	4, 0x90
_rv770_set_clk_bypass_mode:             ## @rv770_set_clk_bypass_mode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rdi)
	je	LBB0_1
## %bb.8:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_1:
	movq	%rdi, %r13
	movq	_CG_SPLL_FUNC_CNTL_2@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32
	movslq	%eax, %rbx
	movq	_SCLK_MUX_SEL_MASK@GOTPCREL(%rip), %rax
	andq	(%rax), %rbx
	movl	$1, %edi
	callq	_SCLK_MUX_SEL
	movq	%rax, %r14
	movq	_SCLK_MUX_UPDATE@GOTPCREL(%rip), %rax
	orq	%rbx, %r14
	orq	(%rax), %r14
	movl	(%r15), %edi
	movq	%r14, %rsi
	callq	_WREG32
	cmpq	$0, 8(%r13)
	jle	LBB0_5
## %bb.2:
	xorl	%ebx, %ebx
	movq	_CG_SPLL_STATUS@GOTPCREL(%rip), %r12
	movq	_SPLL_CHG_STATUS@GOTPCREL(%rip), %r15
	.p2align	4, 0x90
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r12), %edi
	callq	_RREG32
	testl	%eax, (%r15)
	jne	LBB0_5
## %bb.4:                               ##   in Loop: Header=BB0_3 Depth=1
	movl	$1, %edi
	callq	_udelay
	incq	%rbx
	cmpq	8(%r13), %rbx
	jl	LBB0_3
LBB0_5:
	movq	_SCLK_MUX_UPDATE@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	notq	%rax
	andq	%rax, %r14
	movq	_CG_SPLL_FUNC_CNTL_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	%r14, %rsi
	callq	_WREG32
	movq	_MPLL_CNTL_MODE@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32
	cltq
	movq	16(%r13), %rcx
	movq	_CHIP_RV710@GOTPCREL(%rip), %rdx
	movq	_CHIP_RV730@GOTPCREL(%rip), %rbx
	movq	_RV730_MPLL_MCLK_SEL@GOTPCREL(%rip), %rsi
	movq	%rsi, %rdi
	cmpq	(%rbx), %rcx
	je	LBB0_7
## %bb.6:
	movq	_MPLL_MCLK_SEL@GOTPCREL(%rip), %rdi
LBB0_7:
	cmpq	(%rdx), %rcx
	cmoveq	%rsi, %rdi
	movq	(%rdi), %rsi
	notq	%rsi
	andq	%rax, %rsi
	movl	(%r14), %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
	.comm	_CG_SPLL_FUNC_CNTL_2,4,2        ## @CG_SPLL_FUNC_CNTL_2
	.comm	_SCLK_MUX_SEL_MASK,8,3          ## @SCLK_MUX_SEL_MASK
	.comm	_SCLK_MUX_UPDATE,8,3            ## @SCLK_MUX_UPDATE
	.comm	_CG_SPLL_STATUS,4,2             ## @CG_SPLL_STATUS
	.comm	_SPLL_CHG_STATUS,4,2            ## @SPLL_CHG_STATUS
	.comm	_MPLL_CNTL_MODE,4,2             ## @MPLL_CNTL_MODE
	.comm	_CHIP_RV710,8,3                 ## @CHIP_RV710
	.comm	_CHIP_RV730,8,3                 ## @CHIP_RV730
	.comm	_RV730_MPLL_MCLK_SEL,8,3        ## @RV730_MPLL_MCLK_SEL
	.comm	_MPLL_MCLK_SEL,8,3              ## @MPLL_MCLK_SEL
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_rv770_set_clk_bypass_mode      ; -- Begin function rv770_set_clk_bypass_mode
	.p2align	2
_rv770_set_clk_bypass_mode:             ; @rv770_set_clk_bypass_mode
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _RADEON_IS_IGP@GOTPAGE
Lloh1:
	ldr	x9, [x9, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_2:
	mov	x19, x0
Lloh3:
	adrp	x21, _CG_SPLL_FUNC_CNTL_2@GOTPAGE
Lloh4:
	ldr	x21, [x21, _CG_SPLL_FUNC_CNTL_2@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
                                        ; kill: def $w0 killed $w0 def $x0
	sxtw	x8, w0
Lloh5:
	adrp	x9, _SCLK_MUX_SEL_MASK@GOTPAGE
Lloh6:
	ldr	x9, [x9, _SCLK_MUX_SEL_MASK@GOTPAGEOFF]
Lloh7:
	ldr	x9, [x9]
	and	x20, x9, x8
	mov	w0, #1
	bl	_SCLK_MUX_SEL
Lloh8:
	adrp	x22, _SCLK_MUX_UPDATE@GOTPAGE
Lloh9:
	ldr	x22, [x22, _SCLK_MUX_UPDATE@GOTPAGEOFF]
	ldr	x8, [x22]
	orr	x9, x20, x0
	orr	x20, x9, x8
	ldr	w0, [x21]
	mov	x1, x20
	bl	_WREG32
	ldr	x8, [x19, #8]
	cmp	x8, #1
	b.lt	LBB0_6
; %bb.3:
	mov	x23, #0
Lloh10:
	adrp	x24, _CG_SPLL_STATUS@GOTPAGE
Lloh11:
	ldr	x24, [x24, _CG_SPLL_STATUS@GOTPAGEOFF]
Lloh12:
	adrp	x25, _SPLL_CHG_STATUS@GOTPAGE
Lloh13:
	ldr	x25, [x25, _SPLL_CHG_STATUS@GOTPAGEOFF]
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x24]
	bl	_RREG32
	ldr	w8, [x25]
	tst	w8, w0
	b.ne	LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	mov	w0, #1
	bl	_udelay
	add	x23, x23, #1
	ldr	x8, [x19, #8]
	cmp	x23, x8
	b.lt	LBB0_4
LBB0_6:
	ldr	x8, [x22]
	bic	x1, x20, x8
	ldr	w0, [x21]
	bl	_WREG32
Lloh14:
	adrp	x20, _MPLL_CNTL_MODE@GOTPAGE
Lloh15:
	ldr	x20, [x20, _MPLL_CNTL_MODE@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
                                        ; kill: def $w0 killed $w0 def $x0
	sxtw	x8, w0
	ldr	x9, [x19, #16]
Lloh16:
	adrp	x10, _CHIP_RV710@GOTPAGE
Lloh17:
	ldr	x10, [x10, _CHIP_RV710@GOTPAGEOFF]
Lloh18:
	ldr	x10, [x10]
Lloh19:
	adrp	x11, _CHIP_RV730@GOTPAGE
Lloh20:
	ldr	x11, [x11, _CHIP_RV730@GOTPAGEOFF]
Lloh21:
	ldr	x11, [x11]
	cmp	x9, x11
	ccmp	x9, x10, #4, ne
Lloh22:
	adrp	x9, _RV730_MPLL_MCLK_SEL@GOTPAGE
Lloh23:
	ldr	x9, [x9, _RV730_MPLL_MCLK_SEL@GOTPAGEOFF]
Lloh24:
	adrp	x10, _MPLL_MCLK_SEL@GOTPAGE
Lloh25:
	ldr	x10, [x10, _MPLL_MCLK_SEL@GOTPAGEOFF]
	csel	x9, x9, x10, eq
	ldr	x9, [x9]
	bic	x1, x8, x9
	ldr	w0, [x20]
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_WREG32
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
	.comm	_CG_SPLL_FUNC_CNTL_2,4,2        ; @CG_SPLL_FUNC_CNTL_2
	.comm	_SCLK_MUX_SEL_MASK,8,3          ; @SCLK_MUX_SEL_MASK
	.comm	_SCLK_MUX_UPDATE,8,3            ; @SCLK_MUX_UPDATE
	.comm	_CG_SPLL_STATUS,4,2             ; @CG_SPLL_STATUS
	.comm	_SPLL_CHG_STATUS,4,2            ; @SPLL_CHG_STATUS
	.comm	_MPLL_CNTL_MODE,4,2             ; @MPLL_CNTL_MODE
	.comm	_CHIP_RV710,8,3                 ; @CHIP_RV710
	.comm	_CHIP_RV730,8,3                 ; @CHIP_RV730
	.comm	_RV730_MPLL_MCLK_SEL,8,3        ; @RV730_MPLL_MCLK_SEL
	.comm	_MPLL_MCLK_SEL,8,3              ; @MPLL_MCLK_SEL
.subsections_via_symbols
