	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function intel_pre_plane_update
_intel_pre_plane_update:                ## @intel_pre_plane_update
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r13
	movq	%rdi, %r12
	movl	24(%rdi), %edi
	callq	_to_intel_crtc
	movq	%rax, %rbx
	movq	16(%rax), %rdi
	movq	%rdi, -72(%rbp)                 ## 8-byte Spill
	callq	_to_i915
	movq	%rax, -80(%rbp)                 ## 8-byte Spill
	movq	16(%r12), %r15
	movq	%rbx, -48(%rbp)                 ## 8-byte Spill
	movq	8(%rbx), %r14
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_drm_atomic_get_old_plane_state
	movq	%rax, %rbx
	movq	%r13, %rdi
	callq	_needs_modeset
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movq	%r15, %rdi
	movq	%r13, %r15
	callq	_to_intel_atomic_state
	movq	%rax, -64(%rbp)                 ## 8-byte Spill
	movq	%r12, %rdi
	movq	%r13, %rsi
	callq	_hsw_pre_update_disable_ips
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	%r12, %rdi
	callq	_hsw_disable_ips
LBB0_2:
	movq	%rbx, %r13
	testq	%rbx, %rbx
	movq	-80(%rbp), %rbx                 ## 8-byte Reload
	je	LBB0_8
## %bb.3:
	movq	%r14, %rdi
	callq	_to_intel_plane
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	movl	%eax, %esi
	callq	_intel_atomic_get_new_plane_state
	movq	%rax, %r14
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movq	%r15, %rsi
	movq	%rax, %rdx
	callq	_intel_fbc_pre_update
	movq	%rbx, %rdi
	movl	$2, %esi
	callq	_IS_GEN
	testq	%rax, %rax
	je	LBB0_8
## %bb.4:
	cmpq	$0, (%r13)
	je	LBB0_8
## %bb.5:
	cmpl	$0, -52(%rbp)                   ## 4-byte Folded Reload
	jne	LBB0_7
## %bb.6:
	cmpl	$0, (%r14)
	jne	LBB0_8
LBB0_7:
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_intel_set_cpu_fifo_underrun_reporting
LBB0_8:
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	_needs_nv12_wa
	testq	%rax, %rax
	jne	LBB0_11
## %bb.9:
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	_needs_nv12_wa
	testq	%rax, %rax
	je	LBB0_11
## %bb.10:
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_skl_wa_827
LBB0_11:
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	_needs_scalerclk_wa
	testq	%rax, %rax
	jne	LBB0_14
## %bb.12:
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	_needs_scalerclk_wa
	testq	%rax, %rax
	je	LBB0_14
## %bb.13:
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_icl_wa_scalerclkgating
LBB0_14:
	movq	%rbx, %rdi
	callq	_HAS_GMCH
	testq	%rax, %rax
	je	LBB0_19
## %bb.15:
	cmpq	$0, 8(%r12)
	je	LBB0_19
## %bb.16:
	cmpq	$0, 40(%r15)
	je	LBB0_19
## %bb.17:
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_intel_set_memory_cxsr
	testq	%rax, %rax
	je	LBB0_19
## %bb.18:
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_intel_wait_for_vblank
LBB0_19:
	cmpq	$0, 32(%r15)
	je	LBB0_23
## %bb.20:
	movq	-72(%rbp), %rdi                 ## 8-byte Reload
	callq	_ilk_disable_lp_wm
	testq	%rax, %rax
	je	LBB0_23
## %bb.21:
	cmpq	$0, 8(%r12)
	je	LBB0_23
## %bb.22:
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_intel_wait_for_vblank
LBB0_23:
	movq	%r15, %rdi
	callq	_needs_modeset
	testl	%eax, %eax
	je	LBB0_24
LBB0_26:
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_24:
	movq	(%rbx), %rax
	testq	%rax, %rax
	je	LBB0_25
## %bb.27:
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	movq	%r15, %rsi
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmpq	*%rax                           ## TAILCALL
LBB0_25:
	cmpq	$0, (%r15)
	je	LBB0_26
## %bb.28:
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_intel_update_watermarks        ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.no_dead_strip	_intel_pre_plane_update
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function intel_pre_plane_update
_intel_pre_plane_update:                ; @intel_pre_plane_update
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x1
	mov	x22, x0
	ldr	w0, [x0, #24]
	bl	_to_intel_crtc
	mov	x20, x0
	ldr	x24, [x0, #16]
	mov	x0, x24
	bl	_to_i915
	mov	x21, x0
	ldr	x23, [x22, #16]
	ldr	x27, [x20, #8]
	mov	x0, x23
	mov	x1, x27
	bl	_drm_atomic_get_old_plane_state
	mov	x25, x0
	mov	x0, x19
	bl	_needs_modeset
	mov	x26, x0
	mov	x0, x23
	bl	_to_intel_atomic_state
	mov	x23, x0
	mov	x0, x22
	mov	x1, x19
	bl	_hsw_pre_update_disable_ips
	cbz	x0, LBB0_2
; %bb.1:
	mov	x0, x22
	bl	_hsw_disable_ips
LBB0_2:
	cbz	x25, LBB0_8
; %bb.3:
	mov	x0, x27
	bl	_to_intel_plane
	mov	x1, x0
	mov	x0, x23
	bl	_intel_atomic_get_new_plane_state
	mov	x27, x0
	mov	x0, x20
	mov	x1, x19
	mov	x2, x27
	bl	_intel_fbc_pre_update
	mov	x0, x21
	mov	w1, #2
	bl	_IS_GEN
	cbz	x0, LBB0_8
; %bb.4:
	ldr	x8, [x25]
	cbz	x8, LBB0_8
; %bb.5:
	cbnz	w26, LBB0_7
; %bb.6:
	ldr	w8, [x27]
	cbnz	w8, LBB0_8
LBB0_7:
	ldr	w1, [x20]
	mov	x0, x21
	mov	w2, #0
	bl	_intel_set_cpu_fifo_underrun_reporting
LBB0_8:
	mov	x0, x21
	mov	x1, x22
	bl	_needs_nv12_wa
	cbnz	x0, LBB0_11
; %bb.9:
	mov	x0, x21
	mov	x1, x19
	bl	_needs_nv12_wa
	cbz	x0, LBB0_11
; %bb.10:
	ldr	w1, [x20]
	mov	x0, x21
	mov	w2, #1
	bl	_skl_wa_827
LBB0_11:
	mov	x0, x21
	mov	x1, x22
	bl	_needs_scalerclk_wa
	cbnz	x0, LBB0_14
; %bb.12:
	mov	x0, x21
	mov	x1, x19
	bl	_needs_scalerclk_wa
	cbz	x0, LBB0_14
; %bb.13:
	ldr	w1, [x20]
	mov	x0, x21
	mov	w2, #1
	bl	_icl_wa_scalerclkgating
LBB0_14:
	mov	x0, x21
	bl	_HAS_GMCH
	cbz	x0, LBB0_19
; %bb.15:
	ldr	x8, [x22, #8]
	cbz	x8, LBB0_19
; %bb.16:
	ldr	x8, [x19, #40]
	cbz	x8, LBB0_19
; %bb.17:
	mov	x0, x21
	mov	w1, #0
	bl	_intel_set_memory_cxsr
	cbz	x0, LBB0_19
; %bb.18:
	ldr	w1, [x20]
	mov	x0, x21
	bl	_intel_wait_for_vblank
LBB0_19:
	ldr	x8, [x19, #32]
	cbz	x8, LBB0_23
; %bb.20:
	mov	x0, x24
	bl	_ilk_disable_lp_wm
	cbz	x0, LBB0_23
; %bb.21:
	ldr	x8, [x22, #8]
	cbz	x8, LBB0_23
; %bb.22:
	ldr	w1, [x20]
	mov	x0, x21
	bl	_intel_wait_for_vblank
LBB0_23:
	mov	x0, x19
	bl	_needs_modeset
	cbz	w0, LBB0_25
LBB0_24:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
LBB0_25:
	ldr	x2, [x21]
	cbz	x2, LBB0_27
; %bb.26:
	mov	x0, x23
	mov	x1, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	br	x2
LBB0_27:
	ldr	x8, [x19]
	cbz	x8, LBB0_24
; %bb.28:
	mov	x0, x20
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_intel_update_watermarks
	.cfi_endproc
                                        ; -- End function
	.no_dead_strip	_intel_pre_plane_update
.subsections_via_symbols
