	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_evergreen_tiling_fields        ## -- Begin function evergreen_tiling_fields
	.p2align	4, 0x90
_evergreen_tiling_fields:               ## @evergreen_tiling_fields
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	%rcx, %r9
	movq	_RADEON_TILING_EG_BANKW_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	%edi, %eax
	shrl	%cl, %eax
	movq	_RADEON_TILING_EG_BANKW_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movl	%eax, (%rsi)
	movq	_RADEON_TILING_EG_BANKH_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	%edi, %eax
	shrl	%cl, %eax
	movq	_RADEON_TILING_EG_BANKH_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movl	%eax, (%rdx)
	movq	_RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	%edi, %eax
	shrl	%cl, %eax
	movq	_RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movl	%eax, (%r9)
	movq	_RADEON_TILING_EG_TILE_SPLIT_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shrl	%cl, %edi
	movq	_RADEON_TILING_EG_TILE_SPLIT_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %edi
	movl	%edi, (%r8)
	movl	(%rsi), %ecx
	addl	$-2, %ecx
	cmpl	$6, %ecx
	ja	LBB0_1
## %bb.2:
	movslq	%ecx, %rax
	leaq	l_switch.table.evergreen_tiling_fields(%rip), %rcx
	movq	(%rcx,%rax,8), %rcx
	jmp	LBB0_3
LBB0_1:
	movq	_EVERGREEN_ADDR_SURF_BANK_WIDTH_1@GOTPCREL(%rip), %rcx
LBB0_3:
	movl	(%rcx), %eax
	movl	%eax, (%rsi)
	movl	(%rdx), %ecx
	addl	$-2, %ecx
	cmpl	$6, %ecx
	ja	LBB0_4
## %bb.5:
	movslq	%ecx, %rax
	leaq	l_switch.table.evergreen_tiling_fields.1(%rip), %rcx
	movq	(%rcx,%rax,8), %rcx
	jmp	LBB0_6
LBB0_4:
	movq	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_1@GOTPCREL(%rip), %rcx
LBB0_6:
	movl	(%rcx), %eax
	movl	%eax, (%rdx)
	movl	(%r9), %ecx
	addl	$-2, %ecx
	cmpl	$6, %ecx
	ja	LBB0_7
## %bb.8:
	movslq	%ecx, %rax
	leaq	l_switch.table.evergreen_tiling_fields.2(%rip), %rcx
	movq	(%rcx,%rax,8), %rcx
	jmp	LBB0_9
LBB0_7:
	movq	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1@GOTPCREL(%rip), %rcx
LBB0_9:
	movl	(%rcx), %eax
	movl	%eax, (%r9)
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_TILING_EG_BANKW_SHIFT,4,2 ## @RADEON_TILING_EG_BANKW_SHIFT
	.comm	_RADEON_TILING_EG_BANKW_MASK,4,2 ## @RADEON_TILING_EG_BANKW_MASK
	.comm	_RADEON_TILING_EG_BANKH_SHIFT,4,2 ## @RADEON_TILING_EG_BANKH_SHIFT
	.comm	_RADEON_TILING_EG_BANKH_MASK,4,2 ## @RADEON_TILING_EG_BANKH_MASK
	.comm	_RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT,4,2 ## @RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
	.comm	_RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK,4,2 ## @RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
	.comm	_RADEON_TILING_EG_TILE_SPLIT_SHIFT,4,2 ## @RADEON_TILING_EG_TILE_SPLIT_SHIFT
	.comm	_RADEON_TILING_EG_TILE_SPLIT_MASK,4,2 ## @RADEON_TILING_EG_TILE_SPLIT_MASK
	.comm	_EVERGREEN_ADDR_SURF_BANK_WIDTH_1,4,2 ## @EVERGREEN_ADDR_SURF_BANK_WIDTH_1
	.comm	_EVERGREEN_ADDR_SURF_BANK_WIDTH_2,4,2 ## @EVERGREEN_ADDR_SURF_BANK_WIDTH_2
	.comm	_EVERGREEN_ADDR_SURF_BANK_WIDTH_4,4,2 ## @EVERGREEN_ADDR_SURF_BANK_WIDTH_4
	.comm	_EVERGREEN_ADDR_SURF_BANK_WIDTH_8,4,2 ## @EVERGREEN_ADDR_SURF_BANK_WIDTH_8
	.comm	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_1,4,2 ## @EVERGREEN_ADDR_SURF_BANK_HEIGHT_1
	.comm	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_2,4,2 ## @EVERGREEN_ADDR_SURF_BANK_HEIGHT_2
	.comm	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_4,4,2 ## @EVERGREEN_ADDR_SURF_BANK_HEIGHT_4
	.comm	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_8,4,2 ## @EVERGREEN_ADDR_SURF_BANK_HEIGHT_8
	.comm	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1,4,2 ## @EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1
	.comm	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2,4,2 ## @EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2
	.comm	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4,4,2 ## @EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4
	.comm	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8,4,2 ## @EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.evergreen_tiling_fields
l_switch.table.evergreen_tiling_fields:
	.quad	_EVERGREEN_ADDR_SURF_BANK_WIDTH_2
	.quad	_EVERGREEN_ADDR_SURF_BANK_WIDTH_1
	.quad	_EVERGREEN_ADDR_SURF_BANK_WIDTH_4
	.quad	_EVERGREEN_ADDR_SURF_BANK_WIDTH_1
	.quad	_EVERGREEN_ADDR_SURF_BANK_WIDTH_1
	.quad	_EVERGREEN_ADDR_SURF_BANK_WIDTH_1
	.quad	_EVERGREEN_ADDR_SURF_BANK_WIDTH_8

	.p2align	3                               ## @switch.table.evergreen_tiling_fields.1
l_switch.table.evergreen_tiling_fields.1:
	.quad	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_2
	.quad	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_1
	.quad	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_4
	.quad	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_1
	.quad	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_1
	.quad	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_1
	.quad	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_8

	.p2align	3                               ## @switch.table.evergreen_tiling_fields.2
l_switch.table.evergreen_tiling_fields.2:
	.quad	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2
	.quad	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1
	.quad	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4
	.quad	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1
	.quad	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1
	.quad	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1
	.quad	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_evergreen_tiling_fields        ; -- Begin function evergreen_tiling_fields
	.p2align	2
_evergreen_tiling_fields:               ; @evergreen_tiling_fields
	.cfi_startproc
; %bb.0:
Lloh0:
	adrp	x8, _RADEON_TILING_EG_BANKW_SHIFT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_TILING_EG_BANKW_SHIFT@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	lsr	w8, w0, w8
Lloh3:
	adrp	x9, _RADEON_TILING_EG_BANKW_MASK@GOTPAGE
Lloh4:
	ldr	x9, [x9, _RADEON_TILING_EG_BANKW_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	and	w8, w8, w9
	str	w8, [x1]
Lloh6:
	adrp	x8, _RADEON_TILING_EG_BANKH_SHIFT@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_TILING_EG_BANKH_SHIFT@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	lsr	w8, w0, w8
Lloh9:
	adrp	x9, _RADEON_TILING_EG_BANKH_MASK@GOTPAGE
Lloh10:
	ldr	x9, [x9, _RADEON_TILING_EG_BANKH_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	and	w8, w8, w9
	str	w8, [x2]
Lloh12:
	adrp	x8, _RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	lsr	w8, w0, w8
Lloh15:
	adrp	x9, _RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK@GOTPAGE
Lloh16:
	ldr	x9, [x9, _RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	and	w8, w8, w9
	str	w8, [x3]
Lloh18:
	adrp	x8, _RADEON_TILING_EG_TILE_SPLIT_SHIFT@GOTPAGE
Lloh19:
	ldr	x8, [x8, _RADEON_TILING_EG_TILE_SPLIT_SHIFT@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	lsr	w8, w0, w8
Lloh21:
	adrp	x9, _RADEON_TILING_EG_TILE_SPLIT_MASK@GOTPAGE
Lloh22:
	ldr	x9, [x9, _RADEON_TILING_EG_TILE_SPLIT_MASK@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	and	w8, w8, w9
	str	w8, [x4]
	ldr	w8, [x1]
	sub	w8, w8, #2
	cmp	w8, #6
	b.hi	LBB0_2
; %bb.1:
Lloh24:
	adrp	x9, l_switch.table.evergreen_tiling_fields@PAGE
Lloh25:
	add	x9, x9, l_switch.table.evergreen_tiling_fields@PAGEOFF
	ldr	x8, [x9, w8, sxtw #3]
	b	LBB0_3
LBB0_2:
Lloh26:
	adrp	x8, _EVERGREEN_ADDR_SURF_BANK_WIDTH_1@GOTPAGE
Lloh27:
	ldr	x8, [x8, _EVERGREEN_ADDR_SURF_BANK_WIDTH_1@GOTPAGEOFF]
LBB0_3:
	ldr	w8, [x8]
	str	w8, [x1]
	ldr	w8, [x2]
	sub	w8, w8, #2
	cmp	w8, #6
	b.hi	LBB0_5
; %bb.4:
Lloh28:
	adrp	x9, l_switch.table.evergreen_tiling_fields.1@PAGE
Lloh29:
	add	x9, x9, l_switch.table.evergreen_tiling_fields.1@PAGEOFF
	ldr	x8, [x9, w8, sxtw #3]
	b	LBB0_6
LBB0_5:
Lloh30:
	adrp	x8, _EVERGREEN_ADDR_SURF_BANK_HEIGHT_1@GOTPAGE
Lloh31:
	ldr	x8, [x8, _EVERGREEN_ADDR_SURF_BANK_HEIGHT_1@GOTPAGEOFF]
LBB0_6:
	ldr	w8, [x8]
	str	w8, [x2]
	ldr	w8, [x3]
	sub	w8, w8, #2
	cmp	w8, #6
	b.hi	LBB0_8
; %bb.7:
Lloh32:
	adrp	x9, l_switch.table.evergreen_tiling_fields.2@PAGE
Lloh33:
	add	x9, x9, l_switch.table.evergreen_tiling_fields.2@PAGEOFF
	ldr	x8, [x9, w8, sxtw #3]
	b	LBB0_9
LBB0_8:
Lloh34:
	adrp	x8, _EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1@GOTPAGE
Lloh35:
	ldr	x8, [x8, _EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1@GOTPAGEOFF]
LBB0_9:
	ldr	w8, [x8]
	str	w8, [x3]
	ret
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpAdd	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpAdd	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh34, Lloh35
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_TILING_EG_BANKW_SHIFT,4,2 ; @RADEON_TILING_EG_BANKW_SHIFT
	.comm	_RADEON_TILING_EG_BANKW_MASK,4,2 ; @RADEON_TILING_EG_BANKW_MASK
	.comm	_RADEON_TILING_EG_BANKH_SHIFT,4,2 ; @RADEON_TILING_EG_BANKH_SHIFT
	.comm	_RADEON_TILING_EG_BANKH_MASK,4,2 ; @RADEON_TILING_EG_BANKH_MASK
	.comm	_RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT,4,2 ; @RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
	.comm	_RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK,4,2 ; @RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
	.comm	_RADEON_TILING_EG_TILE_SPLIT_SHIFT,4,2 ; @RADEON_TILING_EG_TILE_SPLIT_SHIFT
	.comm	_RADEON_TILING_EG_TILE_SPLIT_MASK,4,2 ; @RADEON_TILING_EG_TILE_SPLIT_MASK
	.comm	_EVERGREEN_ADDR_SURF_BANK_WIDTH_1,4,2 ; @EVERGREEN_ADDR_SURF_BANK_WIDTH_1
	.comm	_EVERGREEN_ADDR_SURF_BANK_WIDTH_2,4,2 ; @EVERGREEN_ADDR_SURF_BANK_WIDTH_2
	.comm	_EVERGREEN_ADDR_SURF_BANK_WIDTH_4,4,2 ; @EVERGREEN_ADDR_SURF_BANK_WIDTH_4
	.comm	_EVERGREEN_ADDR_SURF_BANK_WIDTH_8,4,2 ; @EVERGREEN_ADDR_SURF_BANK_WIDTH_8
	.comm	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_1,4,2 ; @EVERGREEN_ADDR_SURF_BANK_HEIGHT_1
	.comm	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_2,4,2 ; @EVERGREEN_ADDR_SURF_BANK_HEIGHT_2
	.comm	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_4,4,2 ; @EVERGREEN_ADDR_SURF_BANK_HEIGHT_4
	.comm	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_8,4,2 ; @EVERGREEN_ADDR_SURF_BANK_HEIGHT_8
	.comm	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1,4,2 ; @EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1
	.comm	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2,4,2 ; @EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2
	.comm	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4,4,2 ; @EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4
	.comm	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8,4,2 ; @EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.evergreen_tiling_fields
l_switch.table.evergreen_tiling_fields:
	.quad	_EVERGREEN_ADDR_SURF_BANK_WIDTH_2
	.quad	_EVERGREEN_ADDR_SURF_BANK_WIDTH_1
	.quad	_EVERGREEN_ADDR_SURF_BANK_WIDTH_4
	.quad	_EVERGREEN_ADDR_SURF_BANK_WIDTH_1
	.quad	_EVERGREEN_ADDR_SURF_BANK_WIDTH_1
	.quad	_EVERGREEN_ADDR_SURF_BANK_WIDTH_1
	.quad	_EVERGREEN_ADDR_SURF_BANK_WIDTH_8

	.p2align	3                               ; @switch.table.evergreen_tiling_fields.1
l_switch.table.evergreen_tiling_fields.1:
	.quad	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_2
	.quad	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_1
	.quad	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_4
	.quad	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_1
	.quad	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_1
	.quad	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_1
	.quad	_EVERGREEN_ADDR_SURF_BANK_HEIGHT_8

	.p2align	3                               ; @switch.table.evergreen_tiling_fields.2
l_switch.table.evergreen_tiling_fields.2:
	.quad	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2
	.quad	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1
	.quad	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4
	.quad	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1
	.quad	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1
	.quad	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1
	.quad	_EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8

.subsections_via_symbols
