	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4                               ## -- Begin function gfx_v6_0_constants_init
LCPI0_0:
	.long	1                               ## 0x1
	.long	4                               ## 0x4
	.long	5                               ## 0x5
	.long	1                               ## 0x1
LCPI0_1:
	.long	1                               ## 0x1
	.long	2                               ## 0x2
	.long	256                             ## 0x100
	.long	16                              ## 0x10
LCPI0_2:
	.long	8                               ## 0x8
	.long	32                              ## 0x20
	.long	64                              ## 0x40
	.long	48                              ## 0x30
LCPI0_3:
	.long	1                               ## 0x1
	.long	4                               ## 0x4
	.long	6                               ## 0x6
	.long	1                               ## 0x1
LCPI0_4:
	.long	2                               ## 0x2
	.long	4                               ## 0x4
	.long	256                             ## 0x100
	.long	16                              ## 0x10
LCPI0_5:
	.long	1                               ## 0x1
	.long	4                               ## 0x4
	.long	5                               ## 0x5
	.long	2                               ## 0x2
LCPI0_6:
	.long	4                               ## 0x4
	.long	4                               ## 0x4
	.long	256                             ## 0x100
	.long	32                              ## 0x20
LCPI0_7:
	.long	2                               ## 0x2
	.long	8                               ## 0x8
	.long	5                               ## 0x5
	.long	2                               ## 0x2
LCPI0_8:
	.long	4                               ## 0x4
	.long	8                               ## 0x8
	.long	256                             ## 0x100
	.long	32                              ## 0x20
LCPI0_9:
	.long	8                               ## 0x8
	.long	32                              ## 0x20
	.long	256                             ## 0x100
	.long	48                              ## 0x30
LCPI0_10:
	.long	2                               ## 0x2
	.long	12                              ## 0xc
	.long	8                               ## 0x8
	.long	2                               ## 0x2
LCPI0_11:
	.long	4                               ## 0x4
	.long	12                              ## 0xc
	.long	256                             ## 0x100
	.long	32                              ## 0x20
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	4, 0x90
_gfx_v6_0_constants_init:               ## @gfx_v6_0_constants_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movl	(%rdi), %eax
	addl	$-128, %eax
	cmpl	$4, %eax
	ja	LBB0_3
## %bb.1:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_2:
	movaps	LCPI0_5(%rip), %xmm0            ## xmm0 = [1,4,5,2]
	movups	%xmm0, 4(%r14)
	movaps	LCPI0_6(%rip), %xmm0            ## xmm0 = [4,4,256,32]
	jmp	LBB0_8
LBB0_3:
	xorl	%ebx, %ebx
	xorl	%eax, %eax
	callq	_BUG
	jmp	LBB0_11
LBB0_4:
	movaps	LCPI0_10(%rip), %xmm0           ## xmm0 = [2,12,8,2]
	movups	%xmm0, 4(%r14)
	movaps	LCPI0_11(%rip), %xmm0           ## xmm0 = [4,12,256,32]
	jmp	LBB0_6
LBB0_5:
	movaps	LCPI0_7(%rip), %xmm0            ## xmm0 = [2,8,5,2]
	movups	%xmm0, 4(%r14)
	movaps	LCPI0_8(%rip), %xmm0            ## xmm0 = [4,8,256,32]
LBB0_6:
	movups	%xmm0, 20(%r14)
	movaps	LCPI0_9(%rip), %xmm0            ## xmm0 = [8,32,256,48]
	movups	%xmm0, 36(%r14)
	movl	$304, 52(%r14)                  ## imm = 0x130
	movq	_TAHITI_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_7:
	movaps	LCPI0_3(%rip), %xmm0            ## xmm0 = [1,4,6,1]
	movups	%xmm0, 4(%r14)
	movaps	LCPI0_4(%rip), %xmm0            ## xmm0 = [2,4,256,16]
LBB0_8:
	movups	%xmm0, 20(%r14)
	movaps	LCPI0_2(%rip), %xmm0            ## xmm0 = [8,32,64,48]
	movups	%xmm0, 36(%r14)
	movl	$304, 52(%r14)                  ## imm = 0x130
	movq	_VERDE_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_9:
	movaps	LCPI0_0(%rip), %xmm0            ## xmm0 = [1,4,5,1]
	movups	%xmm0, 4(%r14)
	movaps	LCPI0_1(%rip), %xmm0            ## xmm0 = [1,2,256,16]
	movups	%xmm0, 20(%r14)
	movaps	LCPI0_2(%rip), %xmm0            ## xmm0 = [8,32,64,48]
	movups	%xmm0, 36(%r14)
	movl	$304, 52(%r14)                  ## imm = 0x130
	movq	_HAINAN_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %rax
LBB0_10:
	movl	(%rax), %ebx
LBB0_11:
	movq	_mmGRBM_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movq	_GRBM_CNTL__READ_TIMEOUT__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$255, %esi
	shll	%cl, %esi
	callq	_WREG32
	movq	_mmSRBM_INT_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	$1, %esi
	callq	_WREG32
	movq	_mmSRBM_INT_ACK@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	$1, %esi
	callq	_WREG32
	movq	_mmBIF_FB_EN@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movq	_BIF_FB_EN__FB_READ_EN_MASK@GOTPCREL(%rip), %rax
	movq	_BIF_FB_EN__FB_WRITE_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	callq	_WREG32
	movq	_mmMC_SHARED_CHMAP@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movq	_mmMC_ARB_RAMCFG@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, 56(%r14)
	movl	8(%r14), %ecx
	movl	%ecx, 60(%r14)
	movl	$256, 64(%r14)                  ## imm = 0x100
	movq	_MC_ARB_RAMCFG__NOOFCOLS_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_MC_ARB_RAMCFG__NOOFCOLS__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	leal	8(%rax), %ecx
	movl	$4, %eax
	movl	$4, %edx
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %edx
	cmpl	$5119, %edx                     ## imm = 0x13FF
	jg	LBB0_13
## %bb.12:
	leal	1023(%rdx), %eax
	testl	%edx, %edx
	cmovnsl	%edx, %eax
	sarl	$10, %eax
LBB0_13:
	movl	%eax, 68(%r14)
	movabsq	$4294967328, %rcx               ## imm = 0x100000020
	movq	%rcx, 72(%r14)
	movl	$64, 80(%r14)
	movq	_GB_ADDR_CONFIG__ROW_SIZE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%ecx, %ebx
	cmpl	$4, %eax
	je	LBB0_16
## %bb.14:
	cmpl	$2, %eax
	jne	LBB0_17
## %bb.15:
	movq	_GB_ADDR_CONFIG__ROW_SIZE__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	btsl	%eax, %ebx
	jmp	LBB0_17
LBB0_16:
	movq	_GB_ADDR_CONFIG__ROW_SIZE__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %eax
	shll	%cl, %eax
	orl	%eax, %ebx
LBB0_17:
	movq	_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%ebx, %eax
	movq	_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$1, %ebx
	shll	%cl, %ebx
	xorl	%ecx, %ecx
	cmpl	$2, 4(%r14)
	cmovnel	%ecx, %ebx
	orl	%eax, %ebx
	movl	%ebx, 84(%r14)
	movq	_mmGB_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_mmDMIF_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_mmDMIF_ADDR_CALC@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_mmHDP_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_mmDMA_TILING_CONFIG@GOTPCREL(%rip), %r15
	movq	_DMA0_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r15), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_DMA1_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r15), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	%r14, %rdi
	callq	_gfx_v6_0_tiling_mode_table_init
	movq	%r14, %rdi
	callq	_gfx_v6_0_setup_rb
	movq	%r14, %rdi
	callq	_gfx_v6_0_setup_spi
	movq	%r14, %rdi
	callq	_gfx_v6_0_get_cu_info
	movq	%r14, %rdi
	callq	_gfx_v6_0_config_init
	movq	_mmCP_QUEUE_THRESHOLDS@GOTPCREL(%rip), %rax
	movq	_CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$22, %edx
	shll	%cl, %edx
	movq	(%rax), %rdi
	movq	_CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$43, %esi
	shll	%cl, %esi
	orl	%edx, %esi
	callq	_WREG32
	movq	_mmCP_MEQ_THRESHOLDS@GOTPCREL(%rip), %rax
	movq	_CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$48, %edx
	shll	%cl, %edx
	movq	(%rax), %rdi
	movq	_CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$96, %esi
	shll	%cl, %esi
	orl	%edx, %esi
	callq	_WREG32
	movq	_mmSX_DEBUG_1@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	callq	_RREG32
	movq	(%rbx), %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmSPI_CONFIG_CNTL_1@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movq	_SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$4, %esi
	shll	%cl, %esi
	callq	_WREG32
	movq	_PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	40(%r14), %eax
	movl	44(%r14), %edx
	shll	%cl, %eax
	movq	_PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	movl	48(%r14), %ebx
	movq	_PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %ebx
	movq	_PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movq	_mmPA_SC_FIFO_SIZE@GOTPCREL(%rip), %rdi
	movl	52(%r14), %esi
	shll	%cl, %esi
	movq	(%rdi), %rdi
	orl	%eax, %edx
	orl	%ebx, %esi
	orl	%edx, %esi
	callq	_WREG32
	movq	_mmVGT_NUM_INSTANCES@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	$1, %esi
	callq	_WREG32
	movq	_mmCP_PERFMON_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmSQ_CONFIG@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmPA_SC_FORCE_EOV_MAX_CNTS@GOTPCREL(%rip), %rax
	movq	_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$4095, %edx                     ## imm = 0xFFF
	shll	%cl, %edx
	movq	(%rax), %rdi
	movq	_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$255, %esi
	shll	%cl, %esi
	orl	%edx, %esi
	callq	_WREG32
	movq	_mmVGT_CACHE_INVALIDATION@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movq	_VC_AND_TC@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	movq	_ES_AND_GS_AUTO@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %esi
	orl	%eax, %esi
	callq	_WREG32
	movq	_mmVGT_GS_VERTEX_REUSE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	$16, %esi
	callq	_WREG32
	movq	_mmPA_SC_LINE_STIPPLE_STATE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmCB_PERFCOUNTER0_SELECT0@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmCB_PERFCOUNTER0_SELECT1@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmCB_PERFCOUNTER1_SELECT0@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmCB_PERFCOUNTER1_SELECT1@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmCB_PERFCOUNTER2_SELECT0@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmCB_PERFCOUNTER2_SELECT1@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmCB_PERFCOUNTER3_SELECT0@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmCB_PERFCOUNTER3_SELECT1@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmHDP_HOST_PATH_CNTL@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	callq	_RREG32
	movq	(%rbx), %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmPA_CL_ENHANCE@GOTPCREL(%rip), %rax
	movq	_PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$3, %esi
	shll	%cl, %esi
	movq	(%rax), %rdi
	movq	_PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	callq	_WREG32
	movl	$50, %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_udelay                         ## TAILCALL
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_2, LBB0_2-LJTI0_0
.set L0_0_set_4, LBB0_4-LJTI0_0
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_7, LBB0_7-LJTI0_0
.set L0_0_set_9, LBB0_9-LJTI0_0
LJTI0_0:
	.long	L0_0_set_2
	.long	L0_0_set_4
	.long	L0_0_set_5
	.long	L0_0_set_7
	.long	L0_0_set_9
	.end_data_region
                                        ## -- End function
	.comm	_TAHITI_GB_ADDR_CONFIG_GOLDEN,4,2 ## @TAHITI_GB_ADDR_CONFIG_GOLDEN
	.comm	_VERDE_GB_ADDR_CONFIG_GOLDEN,4,2 ## @VERDE_GB_ADDR_CONFIG_GOLDEN
	.comm	_HAINAN_GB_ADDR_CONFIG_GOLDEN,4,2 ## @HAINAN_GB_ADDR_CONFIG_GOLDEN
	.comm	_mmGRBM_CNTL,8,3                ## @mmGRBM_CNTL
	.comm	_GRBM_CNTL__READ_TIMEOUT__SHIFT,4,2 ## @GRBM_CNTL__READ_TIMEOUT__SHIFT
	.comm	_mmSRBM_INT_CNTL,8,3            ## @mmSRBM_INT_CNTL
	.comm	_mmSRBM_INT_ACK,8,3             ## @mmSRBM_INT_ACK
	.comm	_mmBIF_FB_EN,8,3                ## @mmBIF_FB_EN
	.comm	_BIF_FB_EN__FB_READ_EN_MASK,4,2 ## @BIF_FB_EN__FB_READ_EN_MASK
	.comm	_BIF_FB_EN__FB_WRITE_EN_MASK,4,2 ## @BIF_FB_EN__FB_WRITE_EN_MASK
	.comm	_mmMC_SHARED_CHMAP,8,3          ## @mmMC_SHARED_CHMAP
	.comm	_mmMC_ARB_RAMCFG,8,3            ## @mmMC_ARB_RAMCFG
	.comm	_MC_ARB_RAMCFG__NOOFCOLS_MASK,4,2 ## @MC_ARB_RAMCFG__NOOFCOLS_MASK
	.comm	_MC_ARB_RAMCFG__NOOFCOLS__SHIFT,4,2 ## @MC_ARB_RAMCFG__NOOFCOLS__SHIFT
	.comm	_GB_ADDR_CONFIG__ROW_SIZE_MASK,4,2 ## @GB_ADDR_CONFIG__ROW_SIZE_MASK
	.comm	_GB_ADDR_CONFIG__ROW_SIZE__SHIFT,4,2 ## @GB_ADDR_CONFIG__ROW_SIZE__SHIFT
	.comm	_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK,4,2 ## @GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK
	.comm	_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT,4,2 ## @GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT
	.comm	_mmGB_ADDR_CONFIG,8,3           ## @mmGB_ADDR_CONFIG
	.comm	_mmDMIF_ADDR_CONFIG,8,3         ## @mmDMIF_ADDR_CONFIG
	.comm	_mmDMIF_ADDR_CALC,8,3           ## @mmDMIF_ADDR_CALC
	.comm	_mmHDP_ADDR_CONFIG,8,3          ## @mmHDP_ADDR_CONFIG
	.comm	_mmDMA_TILING_CONFIG,8,3        ## @mmDMA_TILING_CONFIG
	.comm	_DMA0_REGISTER_OFFSET,8,3       ## @DMA0_REGISTER_OFFSET
	.comm	_DMA1_REGISTER_OFFSET,8,3       ## @DMA1_REGISTER_OFFSET
	.comm	_mmCP_QUEUE_THRESHOLDS,8,3      ## @mmCP_QUEUE_THRESHOLDS
	.comm	_CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT,4,2 ## @CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT
	.comm	_CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT,4,2 ## @CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT
	.comm	_mmCP_MEQ_THRESHOLDS,8,3        ## @mmCP_MEQ_THRESHOLDS
	.comm	_CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT,4,2 ## @CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT
	.comm	_CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT,4,2 ## @CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT
	.comm	_mmSX_DEBUG_1,8,3               ## @mmSX_DEBUG_1
	.comm	_mmSPI_CONFIG_CNTL_1,8,3        ## @mmSPI_CONFIG_CNTL_1
	.comm	_SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT,4,2 ## @SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT
	.comm	_mmPA_SC_FIFO_SIZE,8,3          ## @mmPA_SC_FIFO_SIZE
	.comm	_PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT,4,2 ## @PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT
	.comm	_PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT,4,2 ## @PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT
	.comm	_PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT,4,2 ## @PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT
	.comm	_PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT,4,2 ## @PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT
	.comm	_mmVGT_NUM_INSTANCES,8,3        ## @mmVGT_NUM_INSTANCES
	.comm	_mmCP_PERFMON_CNTL,8,3          ## @mmCP_PERFMON_CNTL
	.comm	_mmSQ_CONFIG,8,3                ## @mmSQ_CONFIG
	.comm	_mmPA_SC_FORCE_EOV_MAX_CNTS,8,3 ## @mmPA_SC_FORCE_EOV_MAX_CNTS
	.comm	_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT,4,2 ## @PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT
	.comm	_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT,4,2 ## @PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT
	.comm	_mmVGT_CACHE_INVALIDATION,8,3   ## @mmVGT_CACHE_INVALIDATION
	.comm	_VC_AND_TC,4,2                  ## @VC_AND_TC
	.comm	_VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT,4,2 ## @VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT
	.comm	_ES_AND_GS_AUTO,4,2             ## @ES_AND_GS_AUTO
	.comm	_VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT,4,2 ## @VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT
	.comm	_mmVGT_GS_VERTEX_REUSE,8,3      ## @mmVGT_GS_VERTEX_REUSE
	.comm	_mmPA_SC_LINE_STIPPLE_STATE,8,3 ## @mmPA_SC_LINE_STIPPLE_STATE
	.comm	_mmCB_PERFCOUNTER0_SELECT0,8,3  ## @mmCB_PERFCOUNTER0_SELECT0
	.comm	_mmCB_PERFCOUNTER0_SELECT1,8,3  ## @mmCB_PERFCOUNTER0_SELECT1
	.comm	_mmCB_PERFCOUNTER1_SELECT0,8,3  ## @mmCB_PERFCOUNTER1_SELECT0
	.comm	_mmCB_PERFCOUNTER1_SELECT1,8,3  ## @mmCB_PERFCOUNTER1_SELECT1
	.comm	_mmCB_PERFCOUNTER2_SELECT0,8,3  ## @mmCB_PERFCOUNTER2_SELECT0
	.comm	_mmCB_PERFCOUNTER2_SELECT1,8,3  ## @mmCB_PERFCOUNTER2_SELECT1
	.comm	_mmCB_PERFCOUNTER3_SELECT0,8,3  ## @mmCB_PERFCOUNTER3_SELECT0
	.comm	_mmCB_PERFCOUNTER3_SELECT1,8,3  ## @mmCB_PERFCOUNTER3_SELECT1
	.comm	_mmHDP_HOST_PATH_CNTL,8,3       ## @mmHDP_HOST_PATH_CNTL
	.comm	_mmPA_CL_ENHANCE,8,3            ## @mmPA_CL_ENHANCE
	.comm	_PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK,4,2 ## @PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK
	.comm	_PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT,4,2 ## @PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT
	.comm	_mmUVD_UDEC_ADDR_CONFIG,8,3     ## @mmUVD_UDEC_ADDR_CONFIG
	.comm	_mmUVD_UDEC_DBW_ADDR_CONFIG,8,3 ## @mmUVD_UDEC_DBW_ADDR_CONFIG
	.comm	_mmUVD_UDEC_DB_ADDR_CONFIG,8,3  ## @mmUVD_UDEC_DB_ADDR_CONFIG
	.no_dead_strip	_gfx_v6_0_constants_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4                               ; -- Begin function gfx_v6_0_constants_init
lCPI0_0:
	.long	1                               ; 0x1
	.long	4                               ; 0x4
	.long	5                               ; 0x5
	.long	1                               ; 0x1
lCPI0_1:
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	256                             ; 0x100
	.long	16                              ; 0x10
lCPI0_2:
	.long	8                               ; 0x8
	.long	32                              ; 0x20
	.long	64                              ; 0x40
	.long	48                              ; 0x30
lCPI0_3:
	.long	1                               ; 0x1
	.long	4                               ; 0x4
	.long	6                               ; 0x6
	.long	1                               ; 0x1
lCPI0_4:
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	256                             ; 0x100
	.long	16                              ; 0x10
lCPI0_5:
	.long	1                               ; 0x1
	.long	4                               ; 0x4
	.long	5                               ; 0x5
	.long	2                               ; 0x2
lCPI0_6:
	.long	4                               ; 0x4
	.long	4                               ; 0x4
	.long	256                             ; 0x100
	.long	32                              ; 0x20
lCPI0_7:
	.long	2                               ; 0x2
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	2                               ; 0x2
lCPI0_8:
	.long	4                               ; 0x4
	.long	8                               ; 0x8
	.long	256                             ; 0x100
	.long	32                              ; 0x20
lCPI0_9:
	.long	8                               ; 0x8
	.long	32                              ; 0x20
	.long	256                             ; 0x100
	.long	48                              ; 0x30
lCPI0_10:
	.long	2                               ; 0x2
	.long	12                              ; 0xc
	.long	8                               ; 0x8
	.long	2                               ; 0x2
lCPI0_11:
	.long	4                               ; 0x4
	.long	12                              ; 0xc
	.long	256                             ; 0x100
	.long	32                              ; 0x20
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3
lCPI0_12:
	.long	32                              ; 0x20
	.long	1                               ; 0x1
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	2
_gfx_v6_0_constants_init:               ; @gfx_v6_0_constants_init
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	w8, [x0]
	sub	w8, w8, #128
	cmp	w8, #4
	b.hi	LBB0_3
; %bb.1:
Lloh0:
	adrp	x9, lJTI0_0@PAGE
Lloh1:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_2
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_2:
Lloh2:
	adrp	x8, lCPI0_5@PAGE
Lloh3:
	ldr	q0, [x8, lCPI0_5@PAGEOFF]
	stur	q0, [x19, #4]
Lloh4:
	adrp	x8, lCPI0_6@PAGE
Lloh5:
	ldr	q0, [x8, lCPI0_6@PAGEOFF]
	b	LBB0_8
LBB0_3:
	bl	_BUG
	mov	w20, #0
	b	LBB0_11
LBB0_4:
Lloh6:
	adrp	x8, lCPI0_10@PAGE
Lloh7:
	ldr	q0, [x8, lCPI0_10@PAGEOFF]
	stur	q0, [x19, #4]
Lloh8:
	adrp	x8, lCPI0_11@PAGE
Lloh9:
	ldr	q0, [x8, lCPI0_11@PAGEOFF]
	b	LBB0_6
LBB0_5:
Lloh10:
	adrp	x8, lCPI0_7@PAGE
Lloh11:
	ldr	q0, [x8, lCPI0_7@PAGEOFF]
	stur	q0, [x19, #4]
Lloh12:
	adrp	x8, lCPI0_8@PAGE
Lloh13:
	ldr	q0, [x8, lCPI0_8@PAGEOFF]
LBB0_6:
	stur	q0, [x19, #20]
Lloh14:
	adrp	x8, lCPI0_9@PAGE
Lloh15:
	ldr	q0, [x8, lCPI0_9@PAGEOFF]
	stur	q0, [x19, #36]
	mov	w8, #304
	str	w8, [x19, #52]
Lloh16:
	adrp	x8, _TAHITI_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh17:
	ldr	x8, [x8, _TAHITI_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
	b	LBB0_10
LBB0_7:
Lloh18:
	adrp	x8, lCPI0_3@PAGE
Lloh19:
	ldr	q0, [x8, lCPI0_3@PAGEOFF]
	stur	q0, [x19, #4]
Lloh20:
	adrp	x8, lCPI0_4@PAGE
Lloh21:
	ldr	q0, [x8, lCPI0_4@PAGEOFF]
LBB0_8:
	stur	q0, [x19, #20]
Lloh22:
	adrp	x8, lCPI0_2@PAGE
Lloh23:
	ldr	q0, [x8, lCPI0_2@PAGEOFF]
	stur	q0, [x19, #36]
	mov	w8, #304
	str	w8, [x19, #52]
Lloh24:
	adrp	x8, _VERDE_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh25:
	ldr	x8, [x8, _VERDE_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
	b	LBB0_10
LBB0_9:
Lloh26:
	adrp	x8, lCPI0_0@PAGE
Lloh27:
	ldr	q0, [x8, lCPI0_0@PAGEOFF]
	stur	q0, [x19, #4]
Lloh28:
	adrp	x8, lCPI0_1@PAGE
Lloh29:
	ldr	q0, [x8, lCPI0_1@PAGEOFF]
	stur	q0, [x19, #20]
Lloh30:
	adrp	x8, lCPI0_2@PAGE
Lloh31:
	ldr	q0, [x8, lCPI0_2@PAGEOFF]
	stur	q0, [x19, #36]
	mov	w8, #304
	str	w8, [x19, #52]
Lloh32:
	adrp	x8, _HAINAN_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh33:
	ldr	x8, [x8, _HAINAN_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
LBB0_10:
	ldr	w20, [x8]
LBB0_11:
Lloh34:
	adrp	x8, _mmGRBM_CNTL@GOTPAGE
Lloh35:
	ldr	x8, [x8, _mmGRBM_CNTL@GOTPAGEOFF]
Lloh36:
	ldr	x0, [x8]
Lloh37:
	adrp	x8, _GRBM_CNTL__READ_TIMEOUT__SHIFT@GOTPAGE
Lloh38:
	ldr	x8, [x8, _GRBM_CNTL__READ_TIMEOUT__SHIFT@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
	mov	w9, #255
	lsl	w1, w9, w8
	bl	_WREG32
Lloh40:
	adrp	x8, _mmSRBM_INT_CNTL@GOTPAGE
Lloh41:
	ldr	x8, [x8, _mmSRBM_INT_CNTL@GOTPAGEOFF]
Lloh42:
	ldr	x0, [x8]
	mov	w1, #1
	bl	_WREG32
Lloh43:
	adrp	x8, _mmSRBM_INT_ACK@GOTPAGE
Lloh44:
	ldr	x8, [x8, _mmSRBM_INT_ACK@GOTPAGEOFF]
Lloh45:
	ldr	x0, [x8]
	mov	w1, #1
	bl	_WREG32
Lloh46:
	adrp	x8, _mmBIF_FB_EN@GOTPAGE
Lloh47:
	ldr	x8, [x8, _mmBIF_FB_EN@GOTPAGEOFF]
Lloh48:
	adrp	x9, _BIF_FB_EN__FB_READ_EN_MASK@GOTPAGE
Lloh49:
	ldr	x9, [x9, _BIF_FB_EN__FB_READ_EN_MASK@GOTPAGEOFF]
Lloh50:
	ldr	x0, [x8]
Lloh51:
	ldr	w8, [x9]
Lloh52:
	adrp	x9, _BIF_FB_EN__FB_WRITE_EN_MASK@GOTPAGE
Lloh53:
	ldr	x9, [x9, _BIF_FB_EN__FB_WRITE_EN_MASK@GOTPAGEOFF]
Lloh54:
	ldr	w9, [x9]
	orr	w1, w9, w8
	bl	_WREG32
Lloh55:
	adrp	x8, _mmMC_SHARED_CHMAP@GOTPAGE
Lloh56:
	ldr	x8, [x8, _mmMC_SHARED_CHMAP@GOTPAGEOFF]
Lloh57:
	ldr	x0, [x8]
	bl	_RREG32
Lloh58:
	adrp	x8, _mmMC_ARB_RAMCFG@GOTPAGE
Lloh59:
	ldr	x8, [x8, _mmMC_ARB_RAMCFG@GOTPAGEOFF]
Lloh60:
	ldr	x0, [x8]
	bl	_RREG32
	ldr	w8, [x19, #8]
	stp	w0, w8, [x19, #56]
	mov	w8, #256
Lloh61:
	adrp	x9, _MC_ARB_RAMCFG__NOOFCOLS_MASK@GOTPAGE
Lloh62:
	ldr	x9, [x9, _MC_ARB_RAMCFG__NOOFCOLS_MASK@GOTPAGEOFF]
Lloh63:
	ldr	w9, [x9]
	and	w9, w9, w0
Lloh64:
	adrp	x10, _MC_ARB_RAMCFG__NOOFCOLS__SHIFT@GOTPAGE
Lloh65:
	ldr	x10, [x10, _MC_ARB_RAMCFG__NOOFCOLS__SHIFT@GOTPAGEOFF]
Lloh66:
	ldr	w10, [x10]
	asr	w9, w9, w10
	add	w9, w9, #8
	mov	w10, #4
	lsl	w9, w10, w9
	add	w11, w9, #1023
	cmp	w9, #0
	csel	w11, w11, w9, lt
	asr	w11, w11, #10
	mov	w12, #5119
	cmp	w9, w12
	csel	w9, w10, w11, gt
	stp	w8, w9, [x19, #64]
Lloh67:
	adrp	x8, lCPI0_12@PAGE
Lloh68:
	ldr	d0, [x8, lCPI0_12@PAGEOFF]
	str	d0, [x19, #72]
	mov	w8, #64
	str	w8, [x19, #80]
Lloh69:
	adrp	x8, _GB_ADDR_CONFIG__ROW_SIZE_MASK@GOTPAGE
Lloh70:
	ldr	x8, [x8, _GB_ADDR_CONFIG__ROW_SIZE_MASK@GOTPAGEOFF]
Lloh71:
	ldr	w8, [x8]
	bic	w8, w20, w8
	cmp	w9, #4
	b.eq	LBB0_14
; %bb.12:
	cmp	w9, #2
	b.ne	LBB0_16
; %bb.13:
Lloh72:
	adrp	x9, _GB_ADDR_CONFIG__ROW_SIZE__SHIFT@GOTPAGE
Lloh73:
	ldr	x9, [x9, _GB_ADDR_CONFIG__ROW_SIZE__SHIFT@GOTPAGEOFF]
Lloh74:
	ldr	w9, [x9]
	mov	w10, #1
	b	LBB0_15
LBB0_14:
Lloh75:
	adrp	x9, _GB_ADDR_CONFIG__ROW_SIZE__SHIFT@GOTPAGE
Lloh76:
	ldr	x9, [x9, _GB_ADDR_CONFIG__ROW_SIZE__SHIFT@GOTPAGEOFF]
Lloh77:
	ldr	w9, [x9]
	mov	w10, #2
LBB0_15:
	lsl	w9, w10, w9
	orr	w8, w9, w8
LBB0_16:
Lloh78:
	adrp	x9, _GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK@GOTPAGE
Lloh79:
	ldr	x9, [x9, _GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK@GOTPAGEOFF]
Lloh80:
	ldr	w9, [x9]
	bic	w8, w8, w9
	ldr	w9, [x19, #4]
Lloh81:
	adrp	x10, _GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT@GOTPAGE
Lloh82:
	ldr	x10, [x10, _GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT@GOTPAGEOFF]
Lloh83:
	ldr	w10, [x10]
	mov	w11, #1
	lsl	w10, w11, w10
	cmp	w9, #2
	csel	w9, w10, wzr, eq
	orr	w20, w9, w8
	str	w20, [x19, #84]
Lloh84:
	adrp	x8, _mmGB_ADDR_CONFIG@GOTPAGE
Lloh85:
	ldr	x8, [x8, _mmGB_ADDR_CONFIG@GOTPAGEOFF]
Lloh86:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh87:
	adrp	x8, _mmDMIF_ADDR_CONFIG@GOTPAGE
Lloh88:
	ldr	x8, [x8, _mmDMIF_ADDR_CONFIG@GOTPAGEOFF]
Lloh89:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh90:
	adrp	x8, _mmDMIF_ADDR_CALC@GOTPAGE
Lloh91:
	ldr	x8, [x8, _mmDMIF_ADDR_CALC@GOTPAGEOFF]
Lloh92:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh93:
	adrp	x8, _mmHDP_ADDR_CONFIG@GOTPAGE
Lloh94:
	ldr	x8, [x8, _mmHDP_ADDR_CONFIG@GOTPAGEOFF]
Lloh95:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh96:
	adrp	x21, _mmDMA_TILING_CONFIG@GOTPAGE
Lloh97:
	ldr	x21, [x21, _mmDMA_TILING_CONFIG@GOTPAGEOFF]
	ldr	x8, [x21]
Lloh98:
	adrp	x9, _DMA0_REGISTER_OFFSET@GOTPAGE
Lloh99:
	ldr	x9, [x9, _DMA0_REGISTER_OFFSET@GOTPAGEOFF]
Lloh100:
	ldr	x9, [x9]
	add	x0, x9, x8
	mov	x1, x20
	bl	_WREG32
	ldr	x8, [x21]
Lloh101:
	adrp	x9, _DMA1_REGISTER_OFFSET@GOTPAGE
Lloh102:
	ldr	x9, [x9, _DMA1_REGISTER_OFFSET@GOTPAGEOFF]
Lloh103:
	ldr	x9, [x9]
	add	x0, x9, x8
	mov	x1, x20
	bl	_WREG32
	mov	x0, x19
	bl	_gfx_v6_0_tiling_mode_table_init
	mov	x0, x19
	bl	_gfx_v6_0_setup_rb
	mov	x0, x19
	bl	_gfx_v6_0_setup_spi
	mov	x0, x19
	bl	_gfx_v6_0_get_cu_info
	mov	x0, x19
	bl	_gfx_v6_0_config_init
Lloh104:
	adrp	x8, _mmCP_QUEUE_THRESHOLDS@GOTPAGE
Lloh105:
	ldr	x8, [x8, _mmCP_QUEUE_THRESHOLDS@GOTPAGEOFF]
Lloh106:
	ldr	x0, [x8]
Lloh107:
	adrp	x8, _CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT@GOTPAGE
Lloh108:
	ldr	x8, [x8, _CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT@GOTPAGEOFF]
Lloh109:
	ldr	w8, [x8]
	mov	w9, #22
	lsl	w8, w9, w8
Lloh110:
	adrp	x9, _CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT@GOTPAGE
Lloh111:
	ldr	x9, [x9, _CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT@GOTPAGEOFF]
Lloh112:
	ldr	w9, [x9]
	mov	w10, #43
	lsl	w9, w10, w9
	orr	w1, w9, w8
	bl	_WREG32
Lloh113:
	adrp	x8, _mmCP_MEQ_THRESHOLDS@GOTPAGE
Lloh114:
	ldr	x8, [x8, _mmCP_MEQ_THRESHOLDS@GOTPAGEOFF]
Lloh115:
	ldr	x0, [x8]
Lloh116:
	adrp	x8, _CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT@GOTPAGE
Lloh117:
	ldr	x8, [x8, _CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT@GOTPAGEOFF]
Lloh118:
	ldr	w8, [x8]
	mov	w9, #48
	lsl	w8, w9, w8
Lloh119:
	adrp	x9, _CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT@GOTPAGE
Lloh120:
	ldr	x9, [x9, _CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT@GOTPAGEOFF]
Lloh121:
	ldr	w9, [x9]
	mov	w10, #96
	lsl	w9, w10, w9
	orr	w1, w9, w8
	bl	_WREG32
Lloh122:
	adrp	x20, _mmSX_DEBUG_1@GOTPAGE
Lloh123:
	ldr	x20, [x20, _mmSX_DEBUG_1@GOTPAGEOFF]
	ldr	x0, [x20]
	bl	_RREG32
	mov	x1, x0
	ldr	x0, [x20]
                                        ; kill: def $w1 killed $w1 killed $x1
	bl	_WREG32
Lloh124:
	adrp	x8, _mmSPI_CONFIG_CNTL_1@GOTPAGE
Lloh125:
	ldr	x8, [x8, _mmSPI_CONFIG_CNTL_1@GOTPAGEOFF]
Lloh126:
	ldr	x0, [x8]
Lloh127:
	adrp	x8, _SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT@GOTPAGE
Lloh128:
	ldr	x8, [x8, _SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT@GOTPAGEOFF]
Lloh129:
	ldr	w8, [x8]
	mov	w9, #4
	lsl	w1, w9, w8
	bl	_WREG32
Lloh130:
	adrp	x8, _mmPA_SC_FIFO_SIZE@GOTPAGE
Lloh131:
	ldr	x8, [x8, _mmPA_SC_FIFO_SIZE@GOTPAGEOFF]
Lloh132:
	ldr	x0, [x8]
Lloh133:
	adrp	x8, _PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT@GOTPAGE
Lloh134:
	ldr	x8, [x8, _PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT@GOTPAGEOFF]
Lloh135:
	ldr	w8, [x8]
	ldp	w9, w10, [x19, #40]
	lsl	w8, w9, w8
Lloh136:
	adrp	x9, _PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT@GOTPAGE
Lloh137:
	ldr	x9, [x9, _PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT@GOTPAGEOFF]
Lloh138:
	ldr	w9, [x9]
	lsl	w9, w10, w9
	orr	w8, w9, w8
Lloh139:
	adrp	x9, _PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT@GOTPAGE
Lloh140:
	ldr	x9, [x9, _PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT@GOTPAGEOFF]
Lloh141:
	ldr	w9, [x9]
	ldp	w10, w11, [x19, #48]
	lsl	w9, w10, w9
	orr	w8, w8, w9
Lloh142:
	adrp	x9, _PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT@GOTPAGE
Lloh143:
	ldr	x9, [x9, _PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT@GOTPAGEOFF]
Lloh144:
	ldr	w9, [x9]
	lsl	w9, w11, w9
	orr	w1, w8, w9
	bl	_WREG32
Lloh145:
	adrp	x8, _mmVGT_NUM_INSTANCES@GOTPAGE
Lloh146:
	ldr	x8, [x8, _mmVGT_NUM_INSTANCES@GOTPAGEOFF]
Lloh147:
	ldr	x0, [x8]
	mov	w1, #1
	bl	_WREG32
Lloh148:
	adrp	x8, _mmCP_PERFMON_CNTL@GOTPAGE
Lloh149:
	ldr	x8, [x8, _mmCP_PERFMON_CNTL@GOTPAGEOFF]
Lloh150:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh151:
	adrp	x8, _mmSQ_CONFIG@GOTPAGE
Lloh152:
	ldr	x8, [x8, _mmSQ_CONFIG@GOTPAGEOFF]
Lloh153:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh154:
	adrp	x8, _mmPA_SC_FORCE_EOV_MAX_CNTS@GOTPAGE
Lloh155:
	ldr	x8, [x8, _mmPA_SC_FORCE_EOV_MAX_CNTS@GOTPAGEOFF]
Lloh156:
	ldr	x0, [x8]
Lloh157:
	adrp	x8, _PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT@GOTPAGE
Lloh158:
	ldr	x8, [x8, _PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT@GOTPAGEOFF]
Lloh159:
	ldr	w8, [x8]
	mov	w9, #4095
	lsl	w8, w9, w8
Lloh160:
	adrp	x9, _PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT@GOTPAGE
Lloh161:
	ldr	x9, [x9, _PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT@GOTPAGEOFF]
Lloh162:
	ldr	w9, [x9]
	mov	w10, #255
	lsl	w9, w10, w9
	orr	w1, w9, w8
	bl	_WREG32
Lloh163:
	adrp	x8, _mmVGT_CACHE_INVALIDATION@GOTPAGE
Lloh164:
	ldr	x8, [x8, _mmVGT_CACHE_INVALIDATION@GOTPAGEOFF]
Lloh165:
	ldr	x0, [x8]
Lloh166:
	adrp	x8, _VC_AND_TC@GOTPAGE
Lloh167:
	ldr	x8, [x8, _VC_AND_TC@GOTPAGEOFF]
Lloh168:
	ldr	w8, [x8]
Lloh169:
	adrp	x9, _VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT@GOTPAGE
Lloh170:
	ldr	x9, [x9, _VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT@GOTPAGEOFF]
Lloh171:
	ldr	w9, [x9]
	lsl	w8, w8, w9
Lloh172:
	adrp	x9, _ES_AND_GS_AUTO@GOTPAGE
Lloh173:
	ldr	x9, [x9, _ES_AND_GS_AUTO@GOTPAGEOFF]
Lloh174:
	ldr	w9, [x9]
Lloh175:
	adrp	x10, _VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT@GOTPAGE
Lloh176:
	ldr	x10, [x10, _VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT@GOTPAGEOFF]
Lloh177:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w1, w9, w8
	bl	_WREG32
Lloh178:
	adrp	x8, _mmVGT_GS_VERTEX_REUSE@GOTPAGE
Lloh179:
	ldr	x8, [x8, _mmVGT_GS_VERTEX_REUSE@GOTPAGEOFF]
Lloh180:
	ldr	x0, [x8]
	mov	w1, #16
	bl	_WREG32
Lloh181:
	adrp	x8, _mmPA_SC_LINE_STIPPLE_STATE@GOTPAGE
Lloh182:
	ldr	x8, [x8, _mmPA_SC_LINE_STIPPLE_STATE@GOTPAGEOFF]
Lloh183:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh184:
	adrp	x8, _mmCB_PERFCOUNTER0_SELECT0@GOTPAGE
Lloh185:
	ldr	x8, [x8, _mmCB_PERFCOUNTER0_SELECT0@GOTPAGEOFF]
Lloh186:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh187:
	adrp	x8, _mmCB_PERFCOUNTER0_SELECT1@GOTPAGE
Lloh188:
	ldr	x8, [x8, _mmCB_PERFCOUNTER0_SELECT1@GOTPAGEOFF]
Lloh189:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh190:
	adrp	x8, _mmCB_PERFCOUNTER1_SELECT0@GOTPAGE
Lloh191:
	ldr	x8, [x8, _mmCB_PERFCOUNTER1_SELECT0@GOTPAGEOFF]
Lloh192:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh193:
	adrp	x8, _mmCB_PERFCOUNTER1_SELECT1@GOTPAGE
Lloh194:
	ldr	x8, [x8, _mmCB_PERFCOUNTER1_SELECT1@GOTPAGEOFF]
Lloh195:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh196:
	adrp	x8, _mmCB_PERFCOUNTER2_SELECT0@GOTPAGE
Lloh197:
	ldr	x8, [x8, _mmCB_PERFCOUNTER2_SELECT0@GOTPAGEOFF]
Lloh198:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh199:
	adrp	x8, _mmCB_PERFCOUNTER2_SELECT1@GOTPAGE
Lloh200:
	ldr	x8, [x8, _mmCB_PERFCOUNTER2_SELECT1@GOTPAGEOFF]
Lloh201:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh202:
	adrp	x8, _mmCB_PERFCOUNTER3_SELECT0@GOTPAGE
Lloh203:
	ldr	x8, [x8, _mmCB_PERFCOUNTER3_SELECT0@GOTPAGEOFF]
Lloh204:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh205:
	adrp	x8, _mmCB_PERFCOUNTER3_SELECT1@GOTPAGE
Lloh206:
	ldr	x8, [x8, _mmCB_PERFCOUNTER3_SELECT1@GOTPAGEOFF]
Lloh207:
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh208:
	adrp	x19, _mmHDP_HOST_PATH_CNTL@GOTPAGE
Lloh209:
	ldr	x19, [x19, _mmHDP_HOST_PATH_CNTL@GOTPAGEOFF]
	ldr	x0, [x19]
	bl	_RREG32
	mov	x1, x0
	ldr	x0, [x19]
                                        ; kill: def $w1 killed $w1 killed $x1
	bl	_WREG32
Lloh210:
	adrp	x8, _mmPA_CL_ENHANCE@GOTPAGE
Lloh211:
	ldr	x8, [x8, _mmPA_CL_ENHANCE@GOTPAGEOFF]
Lloh212:
	ldr	x0, [x8]
Lloh213:
	adrp	x8, _PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK@GOTPAGE
Lloh214:
	ldr	x8, [x8, _PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK@GOTPAGEOFF]
Lloh215:
	ldr	w8, [x8]
Lloh216:
	adrp	x9, _PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT@GOTPAGE
Lloh217:
	ldr	x9, [x9, _PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT@GOTPAGEOFF]
Lloh218:
	ldr	w9, [x9]
	mov	w10, #3
	lsl	w9, w10, w9
	orr	w1, w9, w8
	bl	_WREG32
	mov	w0, #50
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_udelay
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdr	Lloh4, Lloh5
	.loh AdrpAdrp	Lloh2, Lloh4
	.loh AdrpLdr	Lloh2, Lloh3
	.loh AdrpLdr	Lloh8, Lloh9
	.loh AdrpAdrp	Lloh6, Lloh8
	.loh AdrpLdr	Lloh6, Lloh7
	.loh AdrpLdr	Lloh12, Lloh13
	.loh AdrpAdrp	Lloh10, Lloh12
	.loh AdrpLdr	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdr	Lloh14, Lloh15
	.loh AdrpLdr	Lloh20, Lloh21
	.loh AdrpAdrp	Lloh18, Lloh20
	.loh AdrpLdr	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdr	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdr	Lloh30, Lloh31
	.loh AdrpAdrp	Lloh28, Lloh30
	.loh AdrpLdr	Lloh28, Lloh29
	.loh AdrpAdrp	Lloh26, Lloh28
	.loh AdrpLdr	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdr	Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh50
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh216, Lloh217, Lloh218
	.loh AdrpLdrGotLdr	Lloh213, Lloh214, Lloh215
	.loh AdrpLdrGotLdr	Lloh210, Lloh211, Lloh212
	.loh AdrpLdrGot	Lloh208, Lloh209
	.loh AdrpLdrGotLdr	Lloh205, Lloh206, Lloh207
	.loh AdrpLdrGotLdr	Lloh202, Lloh203, Lloh204
	.loh AdrpLdrGotLdr	Lloh199, Lloh200, Lloh201
	.loh AdrpLdrGotLdr	Lloh196, Lloh197, Lloh198
	.loh AdrpLdrGotLdr	Lloh193, Lloh194, Lloh195
	.loh AdrpLdrGotLdr	Lloh190, Lloh191, Lloh192
	.loh AdrpLdrGotLdr	Lloh187, Lloh188, Lloh189
	.loh AdrpLdrGotLdr	Lloh184, Lloh185, Lloh186
	.loh AdrpLdrGotLdr	Lloh181, Lloh182, Lloh183
	.loh AdrpLdrGotLdr	Lloh178, Lloh179, Lloh180
	.loh AdrpLdrGotLdr	Lloh175, Lloh176, Lloh177
	.loh AdrpLdrGotLdr	Lloh172, Lloh173, Lloh174
	.loh AdrpLdrGotLdr	Lloh169, Lloh170, Lloh171
	.loh AdrpLdrGotLdr	Lloh166, Lloh167, Lloh168
	.loh AdrpLdrGotLdr	Lloh163, Lloh164, Lloh165
	.loh AdrpLdrGotLdr	Lloh160, Lloh161, Lloh162
	.loh AdrpLdrGotLdr	Lloh157, Lloh158, Lloh159
	.loh AdrpLdrGotLdr	Lloh154, Lloh155, Lloh156
	.loh AdrpLdrGotLdr	Lloh151, Lloh152, Lloh153
	.loh AdrpLdrGotLdr	Lloh148, Lloh149, Lloh150
	.loh AdrpLdrGotLdr	Lloh145, Lloh146, Lloh147
	.loh AdrpLdrGotLdr	Lloh142, Lloh143, Lloh144
	.loh AdrpLdrGotLdr	Lloh139, Lloh140, Lloh141
	.loh AdrpLdrGotLdr	Lloh136, Lloh137, Lloh138
	.loh AdrpLdrGotLdr	Lloh133, Lloh134, Lloh135
	.loh AdrpLdrGotLdr	Lloh130, Lloh131, Lloh132
	.loh AdrpLdrGotLdr	Lloh127, Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGot	Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGot	Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_7-LBB0_2)>>2
	.byte	(LBB0_9-LBB0_2)>>2
                                        ; -- End function
	.comm	_TAHITI_GB_ADDR_CONFIG_GOLDEN,4,2 ; @TAHITI_GB_ADDR_CONFIG_GOLDEN
	.comm	_VERDE_GB_ADDR_CONFIG_GOLDEN,4,2 ; @VERDE_GB_ADDR_CONFIG_GOLDEN
	.comm	_HAINAN_GB_ADDR_CONFIG_GOLDEN,4,2 ; @HAINAN_GB_ADDR_CONFIG_GOLDEN
	.comm	_mmGRBM_CNTL,8,3                ; @mmGRBM_CNTL
	.comm	_GRBM_CNTL__READ_TIMEOUT__SHIFT,4,2 ; @GRBM_CNTL__READ_TIMEOUT__SHIFT
	.comm	_mmSRBM_INT_CNTL,8,3            ; @mmSRBM_INT_CNTL
	.comm	_mmSRBM_INT_ACK,8,3             ; @mmSRBM_INT_ACK
	.comm	_mmBIF_FB_EN,8,3                ; @mmBIF_FB_EN
	.comm	_BIF_FB_EN__FB_READ_EN_MASK,4,2 ; @BIF_FB_EN__FB_READ_EN_MASK
	.comm	_BIF_FB_EN__FB_WRITE_EN_MASK,4,2 ; @BIF_FB_EN__FB_WRITE_EN_MASK
	.comm	_mmMC_SHARED_CHMAP,8,3          ; @mmMC_SHARED_CHMAP
	.comm	_mmMC_ARB_RAMCFG,8,3            ; @mmMC_ARB_RAMCFG
	.comm	_MC_ARB_RAMCFG__NOOFCOLS_MASK,4,2 ; @MC_ARB_RAMCFG__NOOFCOLS_MASK
	.comm	_MC_ARB_RAMCFG__NOOFCOLS__SHIFT,4,2 ; @MC_ARB_RAMCFG__NOOFCOLS__SHIFT
	.comm	_GB_ADDR_CONFIG__ROW_SIZE_MASK,4,2 ; @GB_ADDR_CONFIG__ROW_SIZE_MASK
	.comm	_GB_ADDR_CONFIG__ROW_SIZE__SHIFT,4,2 ; @GB_ADDR_CONFIG__ROW_SIZE__SHIFT
	.comm	_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK,4,2 ; @GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK
	.comm	_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT,4,2 ; @GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT
	.comm	_mmGB_ADDR_CONFIG,8,3           ; @mmGB_ADDR_CONFIG
	.comm	_mmDMIF_ADDR_CONFIG,8,3         ; @mmDMIF_ADDR_CONFIG
	.comm	_mmDMIF_ADDR_CALC,8,3           ; @mmDMIF_ADDR_CALC
	.comm	_mmHDP_ADDR_CONFIG,8,3          ; @mmHDP_ADDR_CONFIG
	.comm	_mmDMA_TILING_CONFIG,8,3        ; @mmDMA_TILING_CONFIG
	.comm	_DMA0_REGISTER_OFFSET,8,3       ; @DMA0_REGISTER_OFFSET
	.comm	_DMA1_REGISTER_OFFSET,8,3       ; @DMA1_REGISTER_OFFSET
	.comm	_mmCP_QUEUE_THRESHOLDS,8,3      ; @mmCP_QUEUE_THRESHOLDS
	.comm	_CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT,4,2 ; @CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT
	.comm	_CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT,4,2 ; @CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT
	.comm	_mmCP_MEQ_THRESHOLDS,8,3        ; @mmCP_MEQ_THRESHOLDS
	.comm	_CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT,4,2 ; @CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT
	.comm	_CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT,4,2 ; @CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT
	.comm	_mmSX_DEBUG_1,8,3               ; @mmSX_DEBUG_1
	.comm	_mmSPI_CONFIG_CNTL_1,8,3        ; @mmSPI_CONFIG_CNTL_1
	.comm	_SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT,4,2 ; @SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT
	.comm	_mmPA_SC_FIFO_SIZE,8,3          ; @mmPA_SC_FIFO_SIZE
	.comm	_PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT,4,2 ; @PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT
	.comm	_PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT,4,2 ; @PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT
	.comm	_PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT,4,2 ; @PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT
	.comm	_PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT,4,2 ; @PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT
	.comm	_mmVGT_NUM_INSTANCES,8,3        ; @mmVGT_NUM_INSTANCES
	.comm	_mmCP_PERFMON_CNTL,8,3          ; @mmCP_PERFMON_CNTL
	.comm	_mmSQ_CONFIG,8,3                ; @mmSQ_CONFIG
	.comm	_mmPA_SC_FORCE_EOV_MAX_CNTS,8,3 ; @mmPA_SC_FORCE_EOV_MAX_CNTS
	.comm	_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT,4,2 ; @PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT
	.comm	_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT,4,2 ; @PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT
	.comm	_mmVGT_CACHE_INVALIDATION,8,3   ; @mmVGT_CACHE_INVALIDATION
	.comm	_VC_AND_TC,4,2                  ; @VC_AND_TC
	.comm	_VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT,4,2 ; @VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT
	.comm	_ES_AND_GS_AUTO,4,2             ; @ES_AND_GS_AUTO
	.comm	_VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT,4,2 ; @VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT
	.comm	_mmVGT_GS_VERTEX_REUSE,8,3      ; @mmVGT_GS_VERTEX_REUSE
	.comm	_mmPA_SC_LINE_STIPPLE_STATE,8,3 ; @mmPA_SC_LINE_STIPPLE_STATE
	.comm	_mmCB_PERFCOUNTER0_SELECT0,8,3  ; @mmCB_PERFCOUNTER0_SELECT0
	.comm	_mmCB_PERFCOUNTER0_SELECT1,8,3  ; @mmCB_PERFCOUNTER0_SELECT1
	.comm	_mmCB_PERFCOUNTER1_SELECT0,8,3  ; @mmCB_PERFCOUNTER1_SELECT0
	.comm	_mmCB_PERFCOUNTER1_SELECT1,8,3  ; @mmCB_PERFCOUNTER1_SELECT1
	.comm	_mmCB_PERFCOUNTER2_SELECT0,8,3  ; @mmCB_PERFCOUNTER2_SELECT0
	.comm	_mmCB_PERFCOUNTER2_SELECT1,8,3  ; @mmCB_PERFCOUNTER2_SELECT1
	.comm	_mmCB_PERFCOUNTER3_SELECT0,8,3  ; @mmCB_PERFCOUNTER3_SELECT0
	.comm	_mmCB_PERFCOUNTER3_SELECT1,8,3  ; @mmCB_PERFCOUNTER3_SELECT1
	.comm	_mmHDP_HOST_PATH_CNTL,8,3       ; @mmHDP_HOST_PATH_CNTL
	.comm	_mmPA_CL_ENHANCE,8,3            ; @mmPA_CL_ENHANCE
	.comm	_PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK,4,2 ; @PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK
	.comm	_PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT,4,2 ; @PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT
	.comm	_mmUVD_UDEC_ADDR_CONFIG,8,3     ; @mmUVD_UDEC_ADDR_CONFIG
	.comm	_mmUVD_UDEC_DBW_ADDR_CONFIG,8,3 ; @mmUVD_UDEC_DBW_ADDR_CONFIG
	.comm	_mmUVD_UDEC_DB_ADDR_CONFIG,8,3  ; @mmUVD_UDEC_DB_ADDR_CONFIG
	.no_dead_strip	_gfx_v6_0_constants_init
.subsections_via_symbols
