	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_meson_vid_pll_set              ## -- Begin function meson_vid_pll_set
	.p2align	4, 0x90
_meson_vid_pll_set:                     ## @meson_vid_pll_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r12d
	movq	%rdi, %rbx
	movl	(%rdi), %edi
	movq	_HHI_VID_PLL_CLK_DIV@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	_VID_PLL_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%r14d, %r14d
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	(%rbx), %edi
	movl	(%r13), %esi
	movq	_VID_PLL_PRESET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	leal	-128(%r12), %eax
	movl	$0, %r15d
	cmpl	$13, %eax
	ja	LBB0_2
## %bb.1:
	cltq
	leaq	l_switch.table.meson_vid_pll_set(%rip), %rcx
	movl	(%rcx,%rax,4), %r14d
	leaq	l_switch.table.meson_vid_pll_set.1(%rip), %rcx
	movl	(%rcx,%rax,4), %r15d
LBB0_2:
	movq	_VID_PLL_DIV_1@GOTPCREL(%rip), %rax
	movl	(%rbx), %edi
	movl	(%r13), %esi
	movq	_VID_PLL_BYPASS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	cmpl	%r12d, (%rax)
	jne	LBB0_4
## %bb.3:
	movl	%edx, %ecx
	jmp	LBB0_5
LBB0_4:
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	(%rbx), %edi
	movl	(%r13), %esi
	movl	$196608, %edx                   ## imm = 0x30000
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	(%rbx), %edi
	movl	(%r13), %esi
	movq	_VID_PLL_PRESET@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	(%rbx), %edi
	movl	(%r13), %esi
	movl	$32767, %edx                    ## imm = 0x7FFF
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	(%rbx), %edi
	movl	(%r13), %esi
	movl	$196608, %edx                   ## imm = 0x30000
	movl	%r15d, %ecx
	callq	_regmap_update_bits
	movl	(%rbx), %edi
	movl	(%r13), %esi
	movl	(%r12), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%rbx), %edi
	movl	(%r13), %esi
	movl	$32767, %edx                    ## imm = 0x7FFF
	movl	%r14d, %ecx
	callq	_regmap_update_bits
	movl	(%rbx), %edi
	movl	(%r13), %esi
	movl	(%r12), %edx
	xorl	%ecx, %ecx
LBB0_5:
	callq	_regmap_update_bits
	movl	(%rbx), %edi
	movl	(%r13), %esi
	movq	_VID_PLL_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_regmap_update_bits             ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_HHI_VID_PLL_CLK_DIV,4,2        ## @HHI_VID_PLL_CLK_DIV
	.comm	_VID_PLL_EN,4,2                 ## @VID_PLL_EN
	.comm	_VID_PLL_PRESET,4,2             ## @VID_PLL_PRESET
	.comm	_VID_PLL_DIV_1,4,2              ## @VID_PLL_DIV_1
	.comm	_VID_PLL_BYPASS,4,2             ## @VID_PLL_BYPASS
	.section	__TEXT,__const
	.p2align	2                               ## @switch.table.meson_vid_pll_set
l_switch.table.meson_vid_pll_set:
	.long	30960                           ## 0x78f0
	.long	15480                           ## 0x3c78
	.long	0                               ## 0x0
	.long	3640                            ## 0xe38
	.long	29596                           ## 0x739c
	.long	3276                            ## 0xccc
	.long	26214                           ## 0x6666
	.long	14028                           ## 0x36cc
	.long	3510                            ## 0xdb6
	.long	21140                           ## 0x5294
	.long	2730                            ## 0xaaa
	.long	32640                           ## 0x7f80
	.long	16256                           ## 0x3f80
	.long	4032                            ## 0xfc0

	.p2align	2                               ## @switch.table.meson_vid_pll_set.1
l_switch.table.meson_vid_pll_set.1:
	.long	131072                          ## 0x20000
	.long	65536                           ## 0x10000
	.long	196608                          ## 0x30000
	.long	0                               ## 0x0
	.long	131072                          ## 0x20000
	.long	0                               ## 0x0
	.long	131072                          ## 0x20000
	.long	65536                           ## 0x10000
	.long	0                               ## 0x0
	.long	131072                          ## 0x20000
	.long	0                               ## 0x0
	.long	131072                          ## 0x20000
	.long	65536                           ## 0x10000
	.long	0                               ## 0x0

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_meson_vid_pll_set              ; -- Begin function meson_vid_pll_set
	.p2align	2
_meson_vid_pll_set:                     ; @meson_vid_pll_set
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x22, x1
	mov	x19, x0
	ldr	w0, [x0]
Lloh0:
	adrp	x23, _HHI_VID_PLL_CLK_DIV@GOTPAGE
Lloh1:
	ldr	x23, [x23, _HHI_VID_PLL_CLK_DIV@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh2:
	adrp	x24, _VID_PLL_EN@GOTPAGE
Lloh3:
	ldr	x24, [x24, _VID_PLL_EN@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	w3, #0
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x23]
Lloh4:
	adrp	x25, _VID_PLL_PRESET@GOTPAGE
Lloh5:
	ldr	x25, [x25, _VID_PLL_PRESET@GOTPAGEOFF]
	ldr	w2, [x25]
	mov	w3, #0
	bl	_regmap_update_bits
	mov	w20, #0
	mov	w21, #0
	sub	w8, w22, #128
	cmp	w8, #13
	b.hi	LBB0_2
; %bb.1:
	sbfiz	x8, x8, #2, #32
Lloh6:
	adrp	x9, l_switch.table.meson_vid_pll_set@PAGE
Lloh7:
	add	x9, x9, l_switch.table.meson_vid_pll_set@PAGEOFF
	ldr	w20, [x9, x8]
Lloh8:
	adrp	x9, l_switch.table.meson_vid_pll_set.1@PAGE
Lloh9:
	add	x9, x9, l_switch.table.meson_vid_pll_set.1@PAGEOFF
	ldr	w21, [x9, x8]
LBB0_2:
Lloh10:
	adrp	x8, _VID_PLL_DIV_1@GOTPAGE
Lloh11:
	ldr	x8, [x8, _VID_PLL_DIV_1@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	ldr	w0, [x19]
	ldr	w1, [x23]
Lloh13:
	adrp	x9, _VID_PLL_BYPASS@GOTPAGE
Lloh14:
	ldr	x9, [x9, _VID_PLL_BYPASS@GOTPAGEOFF]
Lloh15:
	ldr	w2, [x9]
	cmp	w8, w22
	b.ne	LBB0_4
; %bb.3:
	mov	x3, x2
	b	LBB0_5
LBB0_4:
	mov	w3, #0
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x23]
	mov	w2, #196608
	mov	w3, #0
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x23]
	ldr	w2, [x25]
	mov	w3, #0
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x23]
	mov	w2, #32767
	mov	w3, #0
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x23]
	mov	w2, #196608
	mov	x3, x21
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x23]
	ldr	w2, [x25]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x23]
	mov	w2, #32767
	mov	x3, x20
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x23]
	ldr	w2, [x25]
	mov	w3, #0
LBB0_5:
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x23]
	ldr	w2, [x24]
	mov	x3, x2
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_regmap_update_bits
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.cfi_endproc
                                        ; -- End function
	.comm	_HHI_VID_PLL_CLK_DIV,4,2        ; @HHI_VID_PLL_CLK_DIV
	.comm	_VID_PLL_EN,4,2                 ; @VID_PLL_EN
	.comm	_VID_PLL_PRESET,4,2             ; @VID_PLL_PRESET
	.comm	_VID_PLL_DIV_1,4,2              ; @VID_PLL_DIV_1
	.comm	_VID_PLL_BYPASS,4,2             ; @VID_PLL_BYPASS
	.section	__TEXT,__const
	.p2align	2                               ; @switch.table.meson_vid_pll_set
l_switch.table.meson_vid_pll_set:
	.long	30960                           ; 0x78f0
	.long	15480                           ; 0x3c78
	.long	0                               ; 0x0
	.long	3640                            ; 0xe38
	.long	29596                           ; 0x739c
	.long	3276                            ; 0xccc
	.long	26214                           ; 0x6666
	.long	14028                           ; 0x36cc
	.long	3510                            ; 0xdb6
	.long	21140                           ; 0x5294
	.long	2730                            ; 0xaaa
	.long	32640                           ; 0x7f80
	.long	16256                           ; 0x3f80
	.long	4032                            ; 0xfc0

	.p2align	2                               ; @switch.table.meson_vid_pll_set.1
l_switch.table.meson_vid_pll_set.1:
	.long	131072                          ; 0x20000
	.long	65536                           ; 0x10000
	.long	196608                          ; 0x30000
	.long	0                               ; 0x0
	.long	131072                          ; 0x20000
	.long	0                               ; 0x0
	.long	131072                          ; 0x20000
	.long	65536                           ; 0x10000
	.long	0                               ; 0x0
	.long	131072                          ; 0x20000
	.long	0                               ; 0x0
	.long	131072                          ; 0x20000
	.long	65536                           ; 0x10000
	.long	0                               ; 0x0

.subsections_via_symbols
