	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_gpio_irq_set_type
_tegra_gpio_irq_set_type:               ## @tegra_gpio_irq_set_type
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %rbx
	movl	(%rdi), %r13d
	movl	%r13d, %edi
	callq	_GPIO_PORT
	movl	%eax, %r15d
	movq	%rbx, %rdi
	callq	_irq_data_get_irq_chip_data
	movq	_IRQ_TYPE_SENSE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%r14d, %ecx
	addl	$-128, %ecx
	cmpl	$5, %ecx
	jae	LBB0_1
## %bb.2:
	movl	%r14d, -44(%rbp)                ## 4-byte Spill
	movq	%rbx, -56(%rbp)                 ## 8-byte Spill
	movq	8(%rax), %r12
	movslq	%ecx, %rdx
	movq	%rax, %rsi
	movq	%rax, -64(%rbp)                 ## 8-byte Spill
	leaq	l_switch.table.tegra_gpio_irq_set_type(%rip), %rcx
	movq	(%rcx,%rdx,8), %rax
	movl	(%rax), %r14d
	movl	%r15d, %r15d
	shlq	$2, %r15
	movq	(%rsi), %rdi
	addq	%r15, %rdi
	callq	_spin_lock_irqsave
	movq	%r12, %rdi
	movl	%r13d, %esi
	callq	_GPIO_INT_LVL
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_tegra_gpio_readl
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_GPIO_INT_LVL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%r13d, %edi
	callq	_GPIO_BIT
	movl	%eax, %ecx
	shll	%cl, %ebx
	notl	%ebx
	andl	-48(%rbp), %ebx                 ## 4-byte Folded Reload
	movl	%r13d, %edi
	callq	_GPIO_BIT
	movl	%eax, %ecx
	shll	%cl, %r14d
	orl	%ebx, %r14d
	movq	%r12, %rdi
	movl	%r13d, %esi
	callq	_GPIO_INT_LVL
	movq	%r12, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_tegra_gpio_writel
	movq	-64(%rbp), %rax                 ## 8-byte Reload
	addq	(%rax), %r15
	movq	%r15, %rdi
	callq	_spin_unlock_irqrestore
	movq	%r12, %rdi
	movl	%r13d, %esi
	callq	_GPIO_MSK_OE
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	%r13d, %edx
	xorl	%ecx, %ecx
	callq	_tegra_gpio_mask_write
	movq	%r12, %rdi
	movl	%r13d, %esi
	callq	_tegra_gpio_enable
	leaq	4(%r12), %rdi
	movl	%r13d, %esi
	callq	_gpiochip_lock_as_irq
	testl	%eax, %eax
	je	LBB0_4
## %bb.3:
	movl	%eax, %ebx
	movl	(%r12), %edi
	leaq	L_.str(%rip), %rsi
	movl	%r13d, %edx
	callq	_dev_err
	movq	%r12, %rdi
	movl	%r13d, %esi
	callq	_tegra_gpio_disable
	jmp	LBB0_8
LBB0_1:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
LBB0_8:
	movl	%ebx, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_4:
	movl	-44(%rbp), %eax                 ## 4-byte Reload
	testb	$-127, %al
	je	LBB0_6
## %bb.5:
	movq	_handle_level_irq@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_irq_set_handler_locked
	xorl	%ebx, %ebx
	jmp	LBB0_8
LBB0_6:
	xorl	%ebx, %ebx
	testb	$-125, %al
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	je	LBB0_8
## %bb.7:
	movq	_handle_edge_irq@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_irq_set_handler_locked
	jmp	LBB0_8
	.cfi_endproc
                                        ## -- End function
	.comm	_IRQ_TYPE_SENSE_MASK,4,2        ## @IRQ_TYPE_SENSE_MASK
	.comm	_GPIO_INT_LVL_EDGE_RISING,4,2   ## @GPIO_INT_LVL_EDGE_RISING
	.comm	_GPIO_INT_LVL_EDGE_FALLING,4,2  ## @GPIO_INT_LVL_EDGE_FALLING
	.comm	_GPIO_INT_LVL_EDGE_BOTH,4,2     ## @GPIO_INT_LVL_EDGE_BOTH
	.comm	_GPIO_INT_LVL_LEVEL_HIGH,4,2    ## @GPIO_INT_LVL_LEVEL_HIGH
	.comm	_GPIO_INT_LVL_LEVEL_LOW,4,2     ## @GPIO_INT_LVL_LEVEL_LOW
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_GPIO_INT_LVL_MASK,4,2          ## @GPIO_INT_LVL_MASK
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"unable to lock Tegra GPIO %u as IRQ\n"

	.comm	_handle_level_irq,4,2           ## @handle_level_irq
	.comm	_handle_edge_irq,4,2            ## @handle_edge_irq
	.no_dead_strip	_tegra_gpio_irq_set_type
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.tegra_gpio_irq_set_type
l_switch.table.tegra_gpio_irq_set_type:
	.quad	_GPIO_INT_LVL_LEVEL_LOW
	.quad	_GPIO_INT_LVL_LEVEL_HIGH
	.quad	_GPIO_INT_LVL_EDGE_RISING
	.quad	_GPIO_INT_LVL_EDGE_FALLING
	.quad	_GPIO_INT_LVL_EDGE_BOTH

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_gpio_irq_set_type
_tegra_gpio_irq_set_type:               ; @tegra_gpio_irq_set_type
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x1
	mov	x19, x0
	ldr	w20, [x0]
	mov	x0, x20
	bl	_GPIO_PORT
	mov	x24, x0
	mov	x0, x19
	bl	_irq_data_get_irq_chip_data
Lloh0:
	adrp	x8, _IRQ_TYPE_SENSE_MASK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _IRQ_TYPE_SENSE_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	and	w8, w8, w21
	sub	w8, w8, #128
	cmp	w8, #5
	b.hs	LBB0_3
; %bb.1:
	mov	x23, x0
Lloh3:
	adrp	x9, l_switch.table.tegra_gpio_irq_set_type@PAGE
Lloh4:
	add	x9, x9, l_switch.table.tegra_gpio_irq_set_type@PAGEOFF
	ldr	x8, [x9, w8, sxtw #3]
	ldr	w25, [x8]
	ldp	x8, x22, [x0]
	mov	w9, w24
	lsl	x26, x9, #2
	add	x0, x8, x26
	bl	_spin_lock_irqsave
	mov	x0, x22
	mov	x1, x20
	bl	_GPIO_INT_LVL
	mov	x1, x0
	mov	x0, x22
	bl	_tegra_gpio_readl
	mov	x24, x0
Lloh5:
	adrp	x8, _GPIO_INT_LVL_MASK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _GPIO_INT_LVL_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w27, [x8]
	mov	x0, x20
	bl	_GPIO_BIT
	lsl	w8, w27, w0
	bic	w24, w24, w8
	mov	x0, x20
	bl	_GPIO_BIT
	lsl	w8, w25, w0
	orr	w24, w24, w8
	mov	x0, x22
	mov	x1, x20
	bl	_GPIO_INT_LVL
	mov	x2, x0
	mov	x0, x22
	mov	x1, x24
	bl	_tegra_gpio_writel
	ldr	x8, [x23]
	add	x0, x8, x26
	bl	_spin_unlock_irqrestore
	mov	x0, x22
	mov	x1, x20
	bl	_GPIO_MSK_OE
	mov	x1, x0
	mov	x0, x22
	mov	x2, x20
	mov	w3, #0
	bl	_tegra_gpio_mask_write
	mov	x0, x22
	mov	x1, x20
	bl	_tegra_gpio_enable
	add	x0, x22, #4
	mov	x1, x20
	bl	_gpiochip_lock_as_irq
	cbz	w0, LBB0_4
; %bb.2:
	mov	x23, x0
	ldr	w0, [x22]
Lloh8:
	adrp	x1, l_.str@PAGE
Lloh9:
	add	x1, x1, l_.str@PAGEOFF
	mov	x2, x20
	bl	_dev_err
	mov	x0, x22
	mov	x1, x20
	bl	_tegra_gpio_disable
	b	LBB0_10
LBB0_3:
Lloh10:
	adrp	x8, _EINVAL@GOTPAGE
Lloh11:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	neg	w23, w8
	b	LBB0_10
LBB0_4:
	mov	w8, #129
	tst	w21, w8
	b.eq	LBB0_6
; %bb.5:
Lloh13:
	adrp	x8, _handle_level_irq@GOTPAGE
Lloh14:
	ldr	x8, [x8, _handle_level_irq@GOTPAGEOFF]
	b	LBB0_8
LBB0_6:
	mov	w8, #131
	tst	w21, w8
	b.eq	LBB0_9
; %bb.7:
Lloh15:
	adrp	x8, _handle_edge_irq@GOTPAGE
Lloh16:
	ldr	x8, [x8, _handle_edge_irq@GOTPAGEOFF]
LBB0_8:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_irq_set_handler_locked
LBB0_9:
	mov	w23, #0
LBB0_10:
	mov	x0, x23
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh15, Lloh16
	.cfi_endproc
                                        ; -- End function
	.comm	_IRQ_TYPE_SENSE_MASK,4,2        ; @IRQ_TYPE_SENSE_MASK
	.comm	_GPIO_INT_LVL_EDGE_RISING,4,2   ; @GPIO_INT_LVL_EDGE_RISING
	.comm	_GPIO_INT_LVL_EDGE_FALLING,4,2  ; @GPIO_INT_LVL_EDGE_FALLING
	.comm	_GPIO_INT_LVL_EDGE_BOTH,4,2     ; @GPIO_INT_LVL_EDGE_BOTH
	.comm	_GPIO_INT_LVL_LEVEL_HIGH,4,2    ; @GPIO_INT_LVL_LEVEL_HIGH
	.comm	_GPIO_INT_LVL_LEVEL_LOW,4,2     ; @GPIO_INT_LVL_LEVEL_LOW
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_GPIO_INT_LVL_MASK,4,2          ; @GPIO_INT_LVL_MASK
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"unable to lock Tegra GPIO %u as IRQ\n"

	.comm	_handle_level_irq,4,2           ; @handle_level_irq
	.comm	_handle_edge_irq,4,2            ; @handle_edge_irq
	.no_dead_strip	_tegra_gpio_irq_set_type
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.tegra_gpio_irq_set_type
l_switch.table.tegra_gpio_irq_set_type:
	.quad	_GPIO_INT_LVL_LEVEL_LOW
	.quad	_GPIO_INT_LVL_LEVEL_HIGH
	.quad	_GPIO_INT_LVL_EDGE_RISING
	.quad	_GPIO_INT_LVL_EDGE_FALLING
	.quad	_GPIO_INT_LVL_EDGE_BOTH

.subsections_via_symbols
