	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_sor_setup_pwm
_tegra_sor_setup_pwm:                   ## @tegra_sor_setup_pwm
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, -56(%rbp)                 ## 8-byte Spill
	movq	%rdi, %r15
	movq	_SOR_PWM_DIV@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	callq	_tegra_sor_readl
	movq	_SOR_PWM_DIV_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	orl	$1024, %esi                     ## imm = 0x400
	movl	(%rbx), %edx
	movq	%r15, %rdi
	callq	_tegra_sor_writel
	movq	_SOR_PWM_CTL@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_PWM_CTL_DUTY_CYCLE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	orl	$1024, %ecx                     ## imm = 0x400
	movq	_SOR_PWM_CTL_CLK_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	%ecx, %esi
	movq	_SOR_PWM_CTL_TRIGGER@GOTPCREL(%rip), %r13
	orl	(%r13), %esi
	movl	(%r12), %edx
	movq	%r15, %rdi
	callq	_tegra_sor_writel
	movq	_jiffies@GOTPCREL(%rip), %r14
	movq	(%r14), %rax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_msecs_to_jiffies
	movq	%rax, %rbx
	addq	-48(%rbp), %rbx                 ## 8-byte Folded Reload
	.p2align	4, 0x90
LBB0_1:                                 ## =>This Inner Loop Header: Depth=1
	movq	(%r14), %rdi
	movq	%rbx, %rsi
	callq	_time_before
	testq	%rax, %rax
	je	LBB0_5
## %bb.2:                               ##   in Loop: Header=BB0_1 Depth=1
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	testl	%eax, (%r13)
	je	LBB0_3
## %bb.4:                               ##   in Loop: Header=BB0_1 Depth=1
	movl	$25, %edi
	movl	$100, %esi
	callq	_usleep_range
	jmp	LBB0_1
LBB0_5:
	movq	_ETIMEDOUT@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_6
LBB0_3:
	xorl	%eax, %eax
LBB0_6:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_SOR_PWM_DIV,4,2                ## @SOR_PWM_DIV
	.comm	_SOR_PWM_DIV_MASK,4,2           ## @SOR_PWM_DIV_MASK
	.comm	_SOR_PWM_CTL,4,2                ## @SOR_PWM_CTL
	.comm	_SOR_PWM_CTL_DUTY_CYCLE_MASK,4,2 ## @SOR_PWM_CTL_DUTY_CYCLE_MASK
	.comm	_SOR_PWM_CTL_CLK_SEL,4,2        ## @SOR_PWM_CTL_CLK_SEL
	.comm	_SOR_PWM_CTL_TRIGGER,4,2        ## @SOR_PWM_CTL_TRIGGER
	.comm	_jiffies,8,3                    ## @jiffies
	.comm	_ETIMEDOUT,4,2                  ## @ETIMEDOUT
	.no_dead_strip	_tegra_sor_setup_pwm
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_sor_setup_pwm
_tegra_sor_setup_pwm:                   ; @tegra_sor_setup_pwm
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x21, _SOR_PWM_DIV@GOTPAGE
Lloh1:
	ldr	x21, [x21, _SOR_PWM_DIV@GOTPAGEOFF]
	ldr	w1, [x21]
	bl	_tegra_sor_readl
Lloh2:
	adrp	x8, _SOR_PWM_DIV_MASK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _SOR_PWM_DIV_MASK@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	bic	w8, w0, w8
	orr	w1, w8, #0x400
	ldr	w2, [x21]
	mov	x0, x19
	bl	_tegra_sor_writel
Lloh5:
	adrp	x21, _SOR_PWM_CTL@GOTPAGE
Lloh6:
	ldr	x21, [x21, _SOR_PWM_CTL@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh7:
	adrp	x8, _SOR_PWM_CTL_DUTY_CYCLE_MASK@GOTPAGE
Lloh8:
	ldr	x8, [x8, _SOR_PWM_CTL_DUTY_CYCLE_MASK@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	bic	w8, w0, w8
	orr	w8, w8, #0x400
Lloh10:
	adrp	x9, _SOR_PWM_CTL_CLK_SEL@GOTPAGE
Lloh11:
	ldr	x9, [x9, _SOR_PWM_CTL_CLK_SEL@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
	bic	w8, w8, w9
Lloh13:
	adrp	x22, _SOR_PWM_CTL_TRIGGER@GOTPAGE
Lloh14:
	ldr	x22, [x22, _SOR_PWM_CTL_TRIGGER@GOTPAGEOFF]
	ldr	w9, [x22]
	orr	w1, w8, w9
	ldr	w2, [x21]
	mov	x0, x19
	bl	_tegra_sor_writel
Lloh15:
	adrp	x23, _jiffies@GOTPAGE
Lloh16:
	ldr	x23, [x23, _jiffies@GOTPAGEOFF]
	ldr	x24, [x23]
	mov	x0, x20
	bl	_msecs_to_jiffies
	add	x20, x0, x24
LBB0_1:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x0, [x23]
	mov	x1, x20
	bl	_time_before
	cbz	x0, LBB0_4
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	ldr	w1, [x21]
	mov	x0, x19
	bl	_tegra_sor_readl
	ldr	w8, [x22]
	tst	w8, w0
	b.eq	LBB0_5
; %bb.3:                                ;   in Loop: Header=BB0_1 Depth=1
	mov	w0, #25
	mov	w1, #100
	bl	_usleep_range
	b	LBB0_1
LBB0_4:
Lloh17:
	adrp	x8, _ETIMEDOUT@GOTPAGE
Lloh18:
	ldr	x8, [x8, _ETIMEDOUT@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_6
LBB0_5:
	mov	w0, #0
LBB0_6:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.cfi_endproc
                                        ; -- End function
	.comm	_SOR_PWM_DIV,4,2                ; @SOR_PWM_DIV
	.comm	_SOR_PWM_DIV_MASK,4,2           ; @SOR_PWM_DIV_MASK
	.comm	_SOR_PWM_CTL,4,2                ; @SOR_PWM_CTL
	.comm	_SOR_PWM_CTL_DUTY_CYCLE_MASK,4,2 ; @SOR_PWM_CTL_DUTY_CYCLE_MASK
	.comm	_SOR_PWM_CTL_CLK_SEL,4,2        ; @SOR_PWM_CTL_CLK_SEL
	.comm	_SOR_PWM_CTL_TRIGGER,4,2        ; @SOR_PWM_CTL_TRIGGER
	.comm	_jiffies,8,3                    ; @jiffies
	.comm	_ETIMEDOUT,4,2                  ; @ETIMEDOUT
	.no_dead_strip	_tegra_sor_setup_pwm
.subsections_via_symbols
