	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function legacy_read_disabled_bios
_legacy_read_disabled_bios:             ## @legacy_read_disabled_bios
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	_RADEON_SEPROM_CNTL1@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_RREG32
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	movq	_RADEON_VIPH_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movq	_RADEON_IS_PCIE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%rbx), %eax
	jne	LBB0_1
## %bb.2:
	movq	_RADEON_BUS_CNTL@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_1:
	movq	_RV370_BUS_CNTL@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r15d
	movq	_RADEON_CRTC_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r14d
	movq	_RADEON_CRTC_EXT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -60(%rbp)                 ## 4-byte Spill
	movq	8(%rbx), %rax
	movq	(%rax), %rax
	movq	(%rax), %rax
	movq	_PCI_DEVICE_ID_ATI_RADEON_QY@GOTPCREL(%rip), %rcx
	movl	$0, -44(%rbp)                   ## 4-byte Folded Spill
	movl	$0, -48(%rbp)                   ## 4-byte Folded Spill
	cmpq	(%rcx), %rax
	jne	LBB0_5
## %bb.4:
	movq	_RADEON_FP2_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
LBB0_5:
	movq	_RADEON_SINGLE_CRTC@GOTPCREL(%rip), %r12
	movl	(%r12), %eax
	testl	%eax, (%rbx)
	jne	LBB0_7
## %bb.6:
	movq	_RADEON_CRTC2_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
LBB0_7:
	movl	(%r13), %edi
	movq	_RADEON_SCK_PRESCALE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	-56(%rbp), %eax                 ## 4-byte Folded Reload
	movq	_RADEON_SCK_PRESCALE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$12, %esi
	shll	%cl, %esi
	orl	%eax, %esi
	callq	_WREG32
	movq	_RADEON_VIPH_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_VIPH_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	-52(%rbp), %esi                 ## 4-byte Folded Reload
	callq	_WREG32
	movq	_RADEON_IS_PCIE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%rbx), %eax
	movq	_RV370_BUS_CNTL@GOTPCREL(%rip), %r13
	movq	_RADEON_BUS_CNTL@GOTPCREL(%rip), %rax
	cmovneq	%r13, %rax
	movq	_RV370_BUS_BIOS_DIS_ROM@GOTPCREL(%rip), %rcx
	cmoveq	_RADEON_BUS_BIOS_DIS_ROM@GOTPCREL(%rip), %rcx
	movl	(%rax), %edi
	movl	(%rcx), %esi
	notl	%esi
	andl	%r15d, %esi
	callq	_WREG32
	movq	_RADEON_CRTC_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_CRTC_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	%r14d, %esi
	movq	_RADEON_CRTC_DISP_REQ_EN_B@GOTPCREL(%rip), %rax
	movq	_RADEON_CRTC_EXT_DISP_EN@GOTPCREL(%rip), %rcx
	orl	(%rax), %esi
	orl	(%rcx), %esi
	callq	_WREG32
	movl	(%r12), %eax
	testl	%eax, (%rbx)
	jne	LBB0_9
## %bb.8:
	movq	_RADEON_CRTC2_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_CRTC2_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	-44(%rbp), %esi                 ## 4-byte Folded Reload
	movq	_RADEON_CRTC2_DISP_REQ_EN_B@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	callq	_WREG32
LBB0_9:
	movq	_RADEON_CRTC_EXT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_CRTC_CRT_ON@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	-60(%rbp), %esi                 ## 4-byte Folded Reload
	movq	_RADEON_CRTC_SYNC_TRISTAT@GOTPCREL(%rip), %rax
	movq	_RADEON_CRTC_DISPLAY_DIS@GOTPCREL(%rip), %rcx
	orl	(%rax), %esi
	orl	(%rcx), %esi
	callq	_WREG32
	movq	8(%rbx), %rax
	movq	(%rax), %rax
	movq	(%rax), %rax
	movq	_PCI_DEVICE_ID_ATI_RADEON_QY@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_11
## %bb.10:
	movq	_RADEON_FP2_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_FP2_ON@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	-48(%rbp), %esi                 ## 4-byte Folded Reload
	callq	_WREG32
LBB0_11:
	movq	%rbx, %rdi
	callq	_radeon_read_bios
	movl	%eax, %r12d
	movq	_RADEON_SEPROM_CNTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-56(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_VIPH_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-52(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_RADEON_IS_PCIE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%rbx), %eax
	jne	LBB0_13
## %bb.12:
	movq	_RADEON_BUS_CNTL@GOTPCREL(%rip), %r13
LBB0_13:
	movl	(%r13), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movq	_RADEON_CRTC_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_RADEON_SINGLE_CRTC@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rbx)
	jne	LBB0_15
## %bb.14:
	movq	_RADEON_CRTC2_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
LBB0_15:
	movq	_RADEON_CRTC_EXT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-60(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	8(%rbx), %rax
	movq	(%rax), %rax
	movq	(%rax), %rax
	movq	_PCI_DEVICE_ID_ATI_RADEON_QY@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_17
## %bb.16:
	movq	_RADEON_FP2_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-48(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
LBB0_17:
	movl	%r12d, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_SEPROM_CNTL1,4,2        ## @RADEON_SEPROM_CNTL1
	.comm	_RADEON_VIPH_CONTROL,4,2        ## @RADEON_VIPH_CONTROL
	.comm	_RADEON_IS_PCIE,4,2             ## @RADEON_IS_PCIE
	.comm	_RV370_BUS_CNTL,4,2             ## @RV370_BUS_CNTL
	.comm	_RADEON_BUS_CNTL,4,2            ## @RADEON_BUS_CNTL
	.comm	_RADEON_CRTC_GEN_CNTL,4,2       ## @RADEON_CRTC_GEN_CNTL
	.comm	_RADEON_CRTC_EXT_CNTL,4,2       ## @RADEON_CRTC_EXT_CNTL
	.comm	_PCI_DEVICE_ID_ATI_RADEON_QY,8,3 ## @PCI_DEVICE_ID_ATI_RADEON_QY
	.comm	_RADEON_FP2_GEN_CNTL,4,2        ## @RADEON_FP2_GEN_CNTL
	.comm	_RADEON_SINGLE_CRTC,4,2         ## @RADEON_SINGLE_CRTC
	.comm	_RADEON_CRTC2_GEN_CNTL,4,2      ## @RADEON_CRTC2_GEN_CNTL
	.comm	_RADEON_SCK_PRESCALE_MASK,4,2   ## @RADEON_SCK_PRESCALE_MASK
	.comm	_RADEON_SCK_PRESCALE_SHIFT,4,2  ## @RADEON_SCK_PRESCALE_SHIFT
	.comm	_RADEON_VIPH_EN,4,2             ## @RADEON_VIPH_EN
	.comm	_RV370_BUS_BIOS_DIS_ROM,4,2     ## @RV370_BUS_BIOS_DIS_ROM
	.comm	_RADEON_BUS_BIOS_DIS_ROM,4,2    ## @RADEON_BUS_BIOS_DIS_ROM
	.comm	_RADEON_CRTC_EN,4,2             ## @RADEON_CRTC_EN
	.comm	_RADEON_CRTC_DISP_REQ_EN_B,4,2  ## @RADEON_CRTC_DISP_REQ_EN_B
	.comm	_RADEON_CRTC_EXT_DISP_EN,4,2    ## @RADEON_CRTC_EXT_DISP_EN
	.comm	_RADEON_CRTC2_EN,4,2            ## @RADEON_CRTC2_EN
	.comm	_RADEON_CRTC2_DISP_REQ_EN_B,4,2 ## @RADEON_CRTC2_DISP_REQ_EN_B
	.comm	_RADEON_CRTC_CRT_ON,4,2         ## @RADEON_CRTC_CRT_ON
	.comm	_RADEON_CRTC_SYNC_TRISTAT,4,2   ## @RADEON_CRTC_SYNC_TRISTAT
	.comm	_RADEON_CRTC_DISPLAY_DIS,4,2    ## @RADEON_CRTC_DISPLAY_DIS
	.comm	_RADEON_FP2_ON,4,2              ## @RADEON_FP2_ON
	.no_dead_strip	_legacy_read_disabled_bios
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function legacy_read_disabled_bios
_legacy_read_disabled_bios:             ; @legacy_read_disabled_bios
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
Lloh0:
	adrp	x28, _RADEON_SEPROM_CNTL1@GOTPAGE
Lloh1:
	ldr	x28, [x28, _RADEON_SEPROM_CNTL1@GOTPAGEOFF]
	ldr	w0, [x28]
	bl	_RREG32
	mov	x22, x0
Lloh2:
	adrp	x8, _RADEON_VIPH_CONTROL@GOTPAGE
Lloh3:
	ldr	x8, [x8, _RADEON_VIPH_CONTROL@GOTPAGEOFF]
Lloh4:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x23, x0
	ldr	w8, [x19]
Lloh5:
	adrp	x9, _RADEON_IS_PCIE@GOTPAGE
Lloh6:
	ldr	x9, [x9, _RADEON_IS_PCIE@GOTPAGEOFF]
Lloh7:
	adrp	x10, _RADEON_BUS_CNTL@GOTPAGE
Lloh8:
	ldr	x10, [x10, _RADEON_BUS_CNTL@GOTPAGEOFF]
Lloh9:
	ldr	w9, [x9]
Lloh10:
	adrp	x11, _RV370_BUS_CNTL@GOTPAGE
Lloh11:
	ldr	x11, [x11, _RV370_BUS_CNTL@GOTPAGEOFF]
	tst	w9, w8
	csel	x8, x10, x11, eq
	ldr	w0, [x8]
	bl	_RREG32
	mov	x24, x0
Lloh12:
	adrp	x8, _RADEON_CRTC_GEN_CNTL@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RADEON_CRTC_GEN_CNTL@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x25, x0
Lloh15:
	adrp	x27, _RADEON_CRTC_EXT_CNTL@GOTPAGE
Lloh16:
	ldr	x27, [x27, _RADEON_CRTC_EXT_CNTL@GOTPAGEOFF]
	ldr	w0, [x27]
	bl	_RREG32
	mov	x20, x0
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	ldr	x8, [x8]
Lloh17:
	adrp	x9, _PCI_DEVICE_ID_ATI_RADEON_QY@GOTPAGE
Lloh18:
	ldr	x9, [x9, _PCI_DEVICE_ID_ATI_RADEON_QY@GOTPAGEOFF]
Lloh19:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_2
; %bb.1:
Lloh20:
	adrp	x8, _RADEON_FP2_GEN_CNTL@GOTPAGE
Lloh21:
	ldr	x8, [x8, _RADEON_FP2_GEN_CNTL@GOTPAGEOFF]
Lloh22:
	ldr	w0, [x8]
	bl	_RREG32
	str	w0, [sp, #12]                   ; 4-byte Folded Spill
	b	LBB0_3
LBB0_2:
	str	wzr, [sp, #12]                  ; 4-byte Folded Spill
LBB0_3:
	ldr	w8, [x19]
Lloh23:
	adrp	x21, _RADEON_SINGLE_CRTC@GOTPAGE
Lloh24:
	ldr	x21, [x21, _RADEON_SINGLE_CRTC@GOTPAGEOFF]
	ldr	w9, [x21]
	tst	w9, w8
	b.eq	LBB0_5
; %bb.4:
	mov	w26, #0
	b	LBB0_6
LBB0_5:
Lloh25:
	adrp	x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGE
Lloh26:
	ldr	x8, [x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGEOFF]
Lloh27:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x26, x0
LBB0_6:
	ldr	w0, [x28]
Lloh28:
	adrp	x8, _RADEON_SCK_PRESCALE_MASK@GOTPAGE
Lloh29:
	ldr	x8, [x8, _RADEON_SCK_PRESCALE_MASK@GOTPAGEOFF]
Lloh30:
	ldr	w8, [x8]
	bic	w8, w22, w8
Lloh31:
	adrp	x9, _RADEON_SCK_PRESCALE_SHIFT@GOTPAGE
Lloh32:
	ldr	x9, [x9, _RADEON_SCK_PRESCALE_SHIFT@GOTPAGEOFF]
Lloh33:
	ldr	w9, [x9]
	mov	w10, #12
	lsl	w9, w10, w9
	orr	w1, w9, w8
	bl	_WREG32
Lloh34:
	adrp	x8, _RADEON_VIPH_CONTROL@GOTPAGE
Lloh35:
	ldr	x8, [x8, _RADEON_VIPH_CONTROL@GOTPAGEOFF]
Lloh36:
	ldr	w0, [x8]
Lloh37:
	adrp	x8, _RADEON_VIPH_EN@GOTPAGE
Lloh38:
	ldr	x8, [x8, _RADEON_VIPH_EN@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
	bic	w1, w23, w8
	bl	_WREG32
	ldr	w8, [x19]
Lloh40:
	adrp	x9, _RADEON_IS_PCIE@GOTPAGE
Lloh41:
	ldr	x9, [x9, _RADEON_IS_PCIE@GOTPAGEOFF]
Lloh42:
	ldr	w9, [x9]
	tst	w9, w8
Lloh43:
	adrp	x8, _RADEON_BUS_CNTL@GOTPAGE
Lloh44:
	ldr	x8, [x8, _RADEON_BUS_CNTL@GOTPAGEOFF]
Lloh45:
	adrp	x9, _RV370_BUS_CNTL@GOTPAGE
Lloh46:
	ldr	x9, [x9, _RV370_BUS_CNTL@GOTPAGEOFF]
	csel	x8, x8, x9, eq
Lloh47:
	adrp	x9, _RADEON_BUS_BIOS_DIS_ROM@GOTPAGE
Lloh48:
	ldr	x9, [x9, _RADEON_BUS_BIOS_DIS_ROM@GOTPAGEOFF]
	ldr	w0, [x8]
Lloh49:
	adrp	x8, _RV370_BUS_BIOS_DIS_ROM@GOTPAGE
Lloh50:
	ldr	x8, [x8, _RV370_BUS_BIOS_DIS_ROM@GOTPAGEOFF]
	csel	x8, x9, x8, eq
	ldr	w8, [x8]
	bic	w1, w24, w8
	bl	_WREG32
Lloh51:
	adrp	x8, _RADEON_CRTC_GEN_CNTL@GOTPAGE
Lloh52:
	ldr	x8, [x8, _RADEON_CRTC_GEN_CNTL@GOTPAGEOFF]
Lloh53:
	ldr	w0, [x8]
Lloh54:
	adrp	x8, _RADEON_CRTC_EN@GOTPAGE
Lloh55:
	ldr	x8, [x8, _RADEON_CRTC_EN@GOTPAGEOFF]
Lloh56:
	ldr	w8, [x8]
	bic	w8, w25, w8
Lloh57:
	adrp	x9, _RADEON_CRTC_DISP_REQ_EN_B@GOTPAGE
Lloh58:
	ldr	x9, [x9, _RADEON_CRTC_DISP_REQ_EN_B@GOTPAGEOFF]
Lloh59:
	ldr	w9, [x9]
Lloh60:
	adrp	x10, _RADEON_CRTC_EXT_DISP_EN@GOTPAGE
Lloh61:
	ldr	x10, [x10, _RADEON_CRTC_EXT_DISP_EN@GOTPAGEOFF]
Lloh62:
	ldr	w10, [x10]
	orr	w8, w8, w9
	orr	w1, w8, w10
	bl	_WREG32
	ldr	w8, [x19]
	ldr	w9, [x21]
	tst	w9, w8
	b.ne	LBB0_8
; %bb.7:
Lloh63:
	adrp	x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGE
Lloh64:
	ldr	x8, [x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGEOFF]
Lloh65:
	ldr	w0, [x8]
Lloh66:
	adrp	x8, _RADEON_CRTC2_EN@GOTPAGE
Lloh67:
	ldr	x8, [x8, _RADEON_CRTC2_EN@GOTPAGEOFF]
Lloh68:
	ldr	w8, [x8]
	bic	w8, w26, w8
Lloh69:
	adrp	x9, _RADEON_CRTC2_DISP_REQ_EN_B@GOTPAGE
Lloh70:
	ldr	x9, [x9, _RADEON_CRTC2_DISP_REQ_EN_B@GOTPAGEOFF]
Lloh71:
	ldr	w9, [x9]
	orr	w1, w8, w9
	bl	_WREG32
LBB0_8:
	mov	x28, x27
	ldr	w0, [x27]
Lloh72:
	adrp	x8, _RADEON_CRTC_CRT_ON@GOTPAGE
Lloh73:
	ldr	x8, [x8, _RADEON_CRTC_CRT_ON@GOTPAGEOFF]
Lloh74:
	ldr	w8, [x8]
	bic	w8, w20, w8
Lloh75:
	adrp	x9, _RADEON_CRTC_SYNC_TRISTAT@GOTPAGE
Lloh76:
	ldr	x9, [x9, _RADEON_CRTC_SYNC_TRISTAT@GOTPAGEOFF]
Lloh77:
	ldr	w9, [x9]
Lloh78:
	adrp	x10, _RADEON_CRTC_DISPLAY_DIS@GOTPAGE
Lloh79:
	ldr	x10, [x10, _RADEON_CRTC_DISPLAY_DIS@GOTPAGEOFF]
Lloh80:
	ldr	w10, [x10]
	orr	w8, w8, w9
	orr	w1, w8, w10
	bl	_WREG32
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	ldr	x8, [x8]
Lloh81:
	adrp	x9, _PCI_DEVICE_ID_ATI_RADEON_QY@GOTPAGE
Lloh82:
	ldr	x9, [x9, _PCI_DEVICE_ID_ATI_RADEON_QY@GOTPAGEOFF]
Lloh83:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_10
; %bb.9:
Lloh84:
	adrp	x8, _RADEON_FP2_GEN_CNTL@GOTPAGE
Lloh85:
	ldr	x8, [x8, _RADEON_FP2_GEN_CNTL@GOTPAGEOFF]
Lloh86:
	ldr	w0, [x8]
Lloh87:
	adrp	x8, _RADEON_FP2_ON@GOTPAGE
Lloh88:
	ldr	x8, [x8, _RADEON_FP2_ON@GOTPAGEOFF]
Lloh89:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]                   ; 4-byte Folded Reload
	bic	w1, w9, w8
	bl	_WREG32
LBB0_10:
	mov	x0, x19
	bl	_radeon_read_bios
	mov	x27, x0
Lloh90:
	adrp	x8, _RADEON_SEPROM_CNTL1@GOTPAGE
Lloh91:
	ldr	x8, [x8, _RADEON_SEPROM_CNTL1@GOTPAGEOFF]
Lloh92:
	ldr	w0, [x8]
	mov	x1, x22
	bl	_WREG32
Lloh93:
	adrp	x8, _RADEON_VIPH_CONTROL@GOTPAGE
Lloh94:
	ldr	x8, [x8, _RADEON_VIPH_CONTROL@GOTPAGEOFF]
Lloh95:
	ldr	w0, [x8]
	mov	x1, x23
	bl	_WREG32
	ldr	w8, [x19]
Lloh96:
	adrp	x9, _RADEON_IS_PCIE@GOTPAGE
Lloh97:
	ldr	x9, [x9, _RADEON_IS_PCIE@GOTPAGEOFF]
Lloh98:
	ldr	w9, [x9]
	tst	w9, w8
Lloh99:
	adrp	x8, _RADEON_BUS_CNTL@GOTPAGE
Lloh100:
	ldr	x8, [x8, _RADEON_BUS_CNTL@GOTPAGEOFF]
Lloh101:
	adrp	x9, _RV370_BUS_CNTL@GOTPAGE
Lloh102:
	ldr	x9, [x9, _RV370_BUS_CNTL@GOTPAGEOFF]
	csel	x8, x8, x9, eq
	ldr	w0, [x8]
	mov	x1, x24
	bl	_WREG32
Lloh103:
	adrp	x8, _RADEON_CRTC_GEN_CNTL@GOTPAGE
Lloh104:
	ldr	x8, [x8, _RADEON_CRTC_GEN_CNTL@GOTPAGEOFF]
Lloh105:
	ldr	w0, [x8]
	mov	x1, x25
	bl	_WREG32
	ldr	w8, [x19]
	ldr	w9, [x21]
	tst	w9, w8
	b.ne	LBB0_12
; %bb.11:
Lloh106:
	adrp	x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGE
Lloh107:
	ldr	x8, [x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGEOFF]
Lloh108:
	ldr	w0, [x8]
	mov	x1, x26
	bl	_WREG32
LBB0_12:
	ldr	w0, [x28]
	mov	x1, x20
	bl	_WREG32
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	ldr	x8, [x8]
Lloh109:
	adrp	x9, _PCI_DEVICE_ID_ATI_RADEON_QY@GOTPAGE
Lloh110:
	ldr	x9, [x9, _PCI_DEVICE_ID_ATI_RADEON_QY@GOTPAGEOFF]
Lloh111:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_14
; %bb.13:
Lloh112:
	adrp	x8, _RADEON_FP2_GEN_CNTL@GOTPAGE
Lloh113:
	ldr	x8, [x8, _RADEON_FP2_GEN_CNTL@GOTPAGEOFF]
Lloh114:
	ldr	w0, [x8]
	ldr	w1, [sp, #12]                   ; 4-byte Folded Reload
	bl	_WREG32
LBB0_14:
	mov	x0, x27
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh9
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGot	Lloh101, Lloh102
	.loh AdrpLdrGot	Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh112, Lloh113, Lloh114
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_SEPROM_CNTL1,4,2        ; @RADEON_SEPROM_CNTL1
	.comm	_RADEON_VIPH_CONTROL,4,2        ; @RADEON_VIPH_CONTROL
	.comm	_RADEON_IS_PCIE,4,2             ; @RADEON_IS_PCIE
	.comm	_RV370_BUS_CNTL,4,2             ; @RV370_BUS_CNTL
	.comm	_RADEON_BUS_CNTL,4,2            ; @RADEON_BUS_CNTL
	.comm	_RADEON_CRTC_GEN_CNTL,4,2       ; @RADEON_CRTC_GEN_CNTL
	.comm	_RADEON_CRTC_EXT_CNTL,4,2       ; @RADEON_CRTC_EXT_CNTL
	.comm	_PCI_DEVICE_ID_ATI_RADEON_QY,8,3 ; @PCI_DEVICE_ID_ATI_RADEON_QY
	.comm	_RADEON_FP2_GEN_CNTL,4,2        ; @RADEON_FP2_GEN_CNTL
	.comm	_RADEON_SINGLE_CRTC,4,2         ; @RADEON_SINGLE_CRTC
	.comm	_RADEON_CRTC2_GEN_CNTL,4,2      ; @RADEON_CRTC2_GEN_CNTL
	.comm	_RADEON_SCK_PRESCALE_MASK,4,2   ; @RADEON_SCK_PRESCALE_MASK
	.comm	_RADEON_SCK_PRESCALE_SHIFT,4,2  ; @RADEON_SCK_PRESCALE_SHIFT
	.comm	_RADEON_VIPH_EN,4,2             ; @RADEON_VIPH_EN
	.comm	_RV370_BUS_BIOS_DIS_ROM,4,2     ; @RV370_BUS_BIOS_DIS_ROM
	.comm	_RADEON_BUS_BIOS_DIS_ROM,4,2    ; @RADEON_BUS_BIOS_DIS_ROM
	.comm	_RADEON_CRTC_EN,4,2             ; @RADEON_CRTC_EN
	.comm	_RADEON_CRTC_DISP_REQ_EN_B,4,2  ; @RADEON_CRTC_DISP_REQ_EN_B
	.comm	_RADEON_CRTC_EXT_DISP_EN,4,2    ; @RADEON_CRTC_EXT_DISP_EN
	.comm	_RADEON_CRTC2_EN,4,2            ; @RADEON_CRTC2_EN
	.comm	_RADEON_CRTC2_DISP_REQ_EN_B,4,2 ; @RADEON_CRTC2_DISP_REQ_EN_B
	.comm	_RADEON_CRTC_CRT_ON,4,2         ; @RADEON_CRTC_CRT_ON
	.comm	_RADEON_CRTC_SYNC_TRISTAT,4,2   ; @RADEON_CRTC_SYNC_TRISTAT
	.comm	_RADEON_CRTC_DISPLAY_DIS,4,2    ; @RADEON_CRTC_DISPLAY_DIS
	.comm	_RADEON_FP2_ON,4,2              ; @RADEON_FP2_ON
	.no_dead_strip	_legacy_read_disabled_bios
.subsections_via_symbols
