	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function cnl_cdclk_pll_update
_cnl_cdclk_pll_update:                  ## @cnl_cdclk_pll_update
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rsi, %r14
	movq	_SKL_DSSM@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	_CNL_DSSM_CDCLK_PLL_REFCLK_24MHz@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movl	$19200, %eax                    ## imm = 0x4B00
	movl	$24000, %ecx                    ## imm = 0x5DC0
	cmovel	%eax, %ecx
	movl	%ecx, (%r14)
	movl	$0, 4(%r14)
	movq	_BXT_DE_PLL_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movl	%eax, %ebx
	movq	_BXT_DE_PLL_PLL_ENABLE@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_3
## %bb.1:
	movq	_BXT_DE_PLL_LOCK@GOTPCREL(%rip), %rax
	xorl	%edi, %edi
	movl	(%rax), %eax
	andl	%ebx, %eax
	sete	%dil
	callq	_WARN_ON
	testq	%rax, %rax
	jne	LBB0_3
## %bb.2:
	movq	_CNL_CDCLK_PLL_RATIO_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %ebx
	imull	(%r14), %ebx
	movl	%ebx, 4(%r14)
LBB0_3:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_SKL_DSSM,4,2                   ## @SKL_DSSM
	.comm	_CNL_DSSM_CDCLK_PLL_REFCLK_24MHz,4,2 ## @CNL_DSSM_CDCLK_PLL_REFCLK_24MHz
	.comm	_BXT_DE_PLL_ENABLE,4,2          ## @BXT_DE_PLL_ENABLE
	.comm	_BXT_DE_PLL_PLL_ENABLE,4,2      ## @BXT_DE_PLL_PLL_ENABLE
	.comm	_BXT_DE_PLL_LOCK,4,2            ## @BXT_DE_PLL_LOCK
	.comm	_CNL_CDCLK_PLL_RATIO_MASK,4,2   ## @CNL_CDCLK_PLL_RATIO_MASK
	.no_dead_strip	_cnl_cdclk_pll_update
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cnl_cdclk_pll_update
_cnl_cdclk_pll_update:                  ; @cnl_cdclk_pll_update
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x1
Lloh0:
	adrp	x8, _SKL_DSSM@GOTPAGE
Lloh1:
	ldr	x8, [x8, _SKL_DSSM@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_I915_READ
Lloh3:
	adrp	x8, _CNL_DSSM_CDCLK_PLL_REFCLK_24MHz@GOTPAGE
Lloh4:
	ldr	x8, [x8, _CNL_DSSM_CDCLK_PLL_REFCLK_24MHz@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	tst	w8, w0
	mov	w8, #24000
	mov	w9, #19200
	csel	w8, w9, w8, eq
	stp	w8, wzr, [x19]
Lloh6:
	adrp	x8, _BXT_DE_PLL_ENABLE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _BXT_DE_PLL_ENABLE@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	bl	_I915_READ
Lloh9:
	adrp	x8, _BXT_DE_PLL_PLL_ENABLE@GOTPAGE
Lloh10:
	ldr	x8, [x8, _BXT_DE_PLL_PLL_ENABLE@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_3
; %bb.1:
	mov	x20, x0
Lloh12:
	adrp	x8, _BXT_DE_PLL_LOCK@GOTPAGE
Lloh13:
	ldr	x8, [x8, _BXT_DE_PLL_LOCK@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	tst	w8, w0
	cset	w0, eq
	bl	_WARN_ON
	cbnz	x0, LBB0_3
; %bb.2:
Lloh15:
	adrp	x8, _CNL_CDCLK_PLL_RATIO_MASK@GOTPAGE
Lloh16:
	ldr	x8, [x8, _CNL_CDCLK_PLL_RATIO_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	and	w8, w8, w20
	ldr	w9, [x19]
	mul	w8, w8, w9
	str	w8, [x19, #4]
LBB0_3:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.cfi_endproc
                                        ; -- End function
	.comm	_SKL_DSSM,4,2                   ; @SKL_DSSM
	.comm	_CNL_DSSM_CDCLK_PLL_REFCLK_24MHz,4,2 ; @CNL_DSSM_CDCLK_PLL_REFCLK_24MHz
	.comm	_BXT_DE_PLL_ENABLE,4,2          ; @BXT_DE_PLL_ENABLE
	.comm	_BXT_DE_PLL_PLL_ENABLE,4,2      ; @BXT_DE_PLL_PLL_ENABLE
	.comm	_BXT_DE_PLL_LOCK,4,2            ; @BXT_DE_PLL_LOCK
	.comm	_CNL_CDCLK_PLL_RATIO_MASK,4,2   ; @CNL_CDCLK_PLL_RATIO_MASK
	.no_dead_strip	_cnl_cdclk_pll_update
.subsections_via_symbols
