	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function hdmi_8996_pll_prepare
_hdmi_8996_pll_prepare:                 ## @hdmi_8996_pll_prepare
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	callq	_hw_clk_to_pll
	movq	%rax, %r15
	movq	%rax, %rdi
	callq	_pll_get_phy
	movq	%rax, %r14
	movq	_REG_HDMI_8996_PHY_CFG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%rax, %rdi
	movl	$1, %edx
	callq	_hdmi_phy_write
	movl	$100, %edi
	callq	_udelay
	movl	(%rbx), %esi
	movq	%r14, %rdi
	movl	$25, %edx
	callq	_hdmi_phy_write
	movl	$100, %edi
	callq	_udelay
	movq	%r15, %rdi
	callq	_hdmi_8996_pll_lock_status
	testl	%eax, %eax
	je	LBB0_6
## %bb.1:
	movq	_HDMI_NUM_TX_CHANNEL@GOTPCREL(%rip), %r13
	cmpl	$0, (%r13)
	jle	LBB0_4
## %bb.2:
	xorl	%ebx, %ebx
	movq	_REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN@GOTPCREL(%rip), %r12
	.p2align	4, 0x90
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r12), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	movl	$111, %ecx
	callq	_hdmi_tx_chan_write
	incl	%ebx
	cmpl	(%r13), %ebx
	jl	LBB0_3
LBB0_4:
	movq	_REG_HDMI_PHY_QSERDES_COM_SSC_PER1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_SSC_PER2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$2, %edx
	callq	_hdmi_pll_write
	movq	%r14, %rdi
	callq	_hdmi_8996_phy_ready_status
	testl	%eax, %eax
	movq	_REG_HDMI_8996_PHY_CFG@GOTPCREL(%rip), %rbx
	je	LBB0_6
## %bb.5:
	movl	(%rbx), %esi
	movq	%r14, %rdi
	movl	$24, %edx
	callq	_hdmi_phy_write
	movl	$1, %edi
	callq	_udelay
	movl	(%rbx), %esi
	movq	%r14, %rdi
	movl	$25, %edx
	callq	_hdmi_phy_write
LBB0_6:
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_REG_HDMI_8996_PHY_CFG,4,2      ## @REG_HDMI_8996_PHY_CFG
	.comm	_HDMI_NUM_TX_CHANNEL,4,2        ## @HDMI_NUM_TX_CHANNEL
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN,4,2 ## @REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN
	.comm	_REG_HDMI_PHY_QSERDES_COM_SSC_PER1,4,2 ## @REG_HDMI_PHY_QSERDES_COM_SSC_PER1
	.comm	_REG_HDMI_PHY_QSERDES_COM_SSC_PER2,4,2 ## @REG_HDMI_PHY_QSERDES_COM_SSC_PER2
	.comm	_REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1,4,2 ## @REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1
	.comm	_REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2,4,2 ## @REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2
	.comm	_REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER,4,2 ## @REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER
	.no_dead_strip	_hdmi_8996_pll_prepare
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function hdmi_8996_pll_prepare
_hdmi_8996_pll_prepare:                 ; @hdmi_8996_pll_prepare
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	bl	_hw_clk_to_pll
	mov	x20, x0
	bl	_pll_get_phy
	mov	x19, x0
Lloh0:
	adrp	x22, _REG_HDMI_8996_PHY_CFG@GOTPAGE
Lloh1:
	ldr	x22, [x22, _REG_HDMI_8996_PHY_CFG@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	w2, #1
	bl	_hdmi_phy_write
	mov	w0, #100
	bl	_udelay
	ldr	w1, [x22]
	mov	x0, x19
	mov	w2, #25
	bl	_hdmi_phy_write
	mov	w0, #100
	bl	_udelay
	mov	x0, x20
	bl	_hdmi_8996_pll_lock_status
	cbz	w0, LBB0_6
; %bb.1:
Lloh2:
	adrp	x23, _HDMI_NUM_TX_CHANNEL@GOTPAGE
Lloh3:
	ldr	x23, [x23, _HDMI_NUM_TX_CHANNEL@GOTPAGEOFF]
	ldr	w8, [x23]
	cmp	w8, #1
	b.lt	LBB0_4
; %bb.2:
	mov	w21, #0
Lloh4:
	adrp	x24, _REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN@GOTPAGE
Lloh5:
	ldr	x24, [x24, _REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN@GOTPAGEOFF]
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w2, [x24]
	mov	x0, x20
	mov	x1, x21
	mov	w3, #111
	bl	_hdmi_tx_chan_write
	add	w21, w21, #1
	ldr	w8, [x23]
	cmp	w21, w8
	b.lt	LBB0_3
LBB0_4:
Lloh6:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_SSC_PER1@GOTPAGE
Lloh7:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_SSC_PER1@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #0
	bl	_hdmi_pll_write
Lloh9:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_SSC_PER2@GOTPAGE
Lloh10:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_SSC_PER2@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #0
	bl	_hdmi_pll_write
Lloh12:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1@GOTPAGE
Lloh13:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #0
	bl	_hdmi_pll_write
Lloh15:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2@GOTPAGE
Lloh16:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #0
	bl	_hdmi_pll_write
Lloh18:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER@GOTPAGE
Lloh19:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #2
	bl	_hdmi_pll_write
	mov	x0, x19
	bl	_hdmi_8996_phy_ready_status
	cbz	w0, LBB0_6
; %bb.5:
	ldr	w1, [x22]
	mov	x0, x19
	mov	w2, #24
	bl	_hdmi_phy_write
	mov	w0, #1
	bl	_udelay
	ldr	w1, [x22]
	mov	x0, x19
	mov	w2, #25
	bl	_hdmi_phy_write
LBB0_6:
	mov	w0, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_REG_HDMI_8996_PHY_CFG,4,2      ; @REG_HDMI_8996_PHY_CFG
	.comm	_HDMI_NUM_TX_CHANNEL,4,2        ; @HDMI_NUM_TX_CHANNEL
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN,4,2 ; @REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN
	.comm	_REG_HDMI_PHY_QSERDES_COM_SSC_PER1,4,2 ; @REG_HDMI_PHY_QSERDES_COM_SSC_PER1
	.comm	_REG_HDMI_PHY_QSERDES_COM_SSC_PER2,4,2 ; @REG_HDMI_PHY_QSERDES_COM_SSC_PER2
	.comm	_REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1,4,2 ; @REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1
	.comm	_REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2,4,2 ; @REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2
	.comm	_REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER,4,2 ; @REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER
	.no_dead_strip	_hdmi_8996_pll_prepare
.subsections_via_symbols
