	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function bxt_ddi_pll_enable
_bxt_ddi_pll_enable:                    ## @bxt_ddi_pll_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r12
	movq	%rdi, %r14
	movq	48(%rsi), %rax
	movl	(%rax), %r15d
	leaq	-48(%rbp), %rdx
	leaq	-44(%rbp), %rcx
	movl	%r15d, %esi
	callq	_bxt_port_to_phy_channel
	movl	%r15d, %edi
	callq	_BXT_PORT_PLL_ENABLE
	movl	%eax, %edi
	callq	_I915_READ
	movl	%eax, %ebx
	movq	_PORT_PLL_REF_SEL@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	%r15d, %edi
	callq	_BXT_PORT_PLL_ENABLE
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movq	%r14, %rdi
	callq	_IS_GEMINILAKE
	testq	%rax, %rax
	je	LBB0_3
## %bb.1:
	movl	%r15d, %edi
	callq	_BXT_PORT_PLL_ENABLE
	movl	%eax, %edi
	callq	_I915_READ
	movl	%eax, %ebx
	movq	_PORT_PLL_POWER_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	%r15d, %edi
	callq	_BXT_PORT_PLL_ENABLE
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movl	%r15d, %edi
	callq	_BXT_PORT_PLL_ENABLE
	movl	%eax, %edi
	callq	_I915_READ
	movq	_PORT_PLL_POWER_STATE@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movl	%eax, %edi
	movl	$200, %esi
	callq	_wait_for_us
	testq	%rax, %rax
	je	LBB0_3
## %bb.2:
	leaq	L_.str(%rip), %rdi
	movl	%r15d, %esi
	callq	_DRM_ERROR
LBB0_3:
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	callq	_BXT_PORT_PLL_EBB_4
	movl	%eax, %edi
	callq	_I915_READ
	movq	_PORT_PLL_10BIT_CLK_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	callq	_BXT_PORT_PLL_EBB_4
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	callq	_BXT_PORT_PLL_EBB_0
	movl	%eax, %edi
	callq	_I915_READ
	movq	_PORT_PLL_P1_MASK@GOTPCREL(%rip), %rcx
	movq	_PORT_PLL_P2_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	orl	(%r12), %ebx
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	callq	_BXT_PORT_PLL_EBB_0
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	xorl	%edx, %edx
	callq	_BXT_PORT_PLL
	movl	%eax, %edi
	callq	_I915_READ
	movq	_PORT_PLL_M2_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	orl	4(%r12), %ebx
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	xorl	%edx, %edx
	callq	_BXT_PORT_PLL
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	movl	$1, %edx
	callq	_BXT_PORT_PLL
	movl	%eax, %edi
	callq	_I915_READ
	movq	_PORT_PLL_N_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	orl	8(%r12), %ebx
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	movl	$1, %edx
	callq	_BXT_PORT_PLL
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	movl	$2, %edx
	callq	_BXT_PORT_PLL
	movl	%eax, %edi
	callq	_I915_READ
	movq	_PORT_PLL_M2_FRAC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	orl	12(%r12), %ebx
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	movl	$2, %edx
	callq	_BXT_PORT_PLL
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	movl	$3, %edx
	callq	_BXT_PORT_PLL
	movl	%eax, %edi
	callq	_I915_READ
	movq	_PORT_PLL_M2_FRAC_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	orl	16(%r12), %ebx
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	movl	$3, %edx
	callq	_BXT_PORT_PLL
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	movl	$6, %edx
	callq	_BXT_PORT_PLL
	movl	%eax, %edi
	callq	_I915_READ
	movq	_PORT_PLL_PROP_COEFF_MASK@GOTPCREL(%rip), %rcx
	movq	_PORT_PLL_INT_COEFF_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	movq	_PORT_PLL_GAIN_CTL_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	orl	20(%r12), %ebx
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	movl	$6, %edx
	callq	_BXT_PORT_PLL
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	movl	$8, %edx
	callq	_BXT_PORT_PLL
	movl	%eax, %edi
	callq	_I915_READ
	movq	_PORT_PLL_TARGET_CNT_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	orl	24(%r12), %ebx
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	movl	$8, %edx
	callq	_BXT_PORT_PLL
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	movl	$9, %edx
	callq	_BXT_PORT_PLL
	movl	%eax, %edi
	callq	_I915_READ
	movq	_PORT_PLL_LOCK_THRESHOLD_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	orl	28(%r12), %ebx
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	movl	$9, %edx
	callq	_BXT_PORT_PLL
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	movl	$10, %edx
	callq	_BXT_PORT_PLL
	movl	%eax, %edi
	callq	_I915_READ
	movq	_PORT_PLL_DCO_AMP_OVR_EN_H@GOTPCREL(%rip), %rcx
	movq	_PORT_PLL_DCO_AMP_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	orl	32(%r12), %ebx
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	movl	$10, %edx
	callq	_BXT_PORT_PLL
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	callq	_BXT_PORT_PLL_EBB_4
	movl	%eax, %edi
	callq	_I915_READ
	movl	%eax, %r13d
	movq	_PORT_PLL_RECALIBRATE@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	callq	_BXT_PORT_PLL_EBB_4
	movl	%eax, %edi
	movl	%r13d, %esi
	callq	_I915_WRITE
	movq	_PORT_PLL_10BIT_CLK_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	notl	%ebx
	andl	%r13d, %ebx
	orl	36(%r12), %ebx
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	callq	_BXT_PORT_PLL_EBB_4
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movl	%r15d, %edi
	callq	_BXT_PORT_PLL_ENABLE
	movl	%eax, %edi
	callq	_I915_READ
	movl	%eax, %ebx
	movq	_PORT_PLL_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	%r15d, %edi
	callq	_BXT_PORT_PLL_ENABLE
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movl	%r15d, %edi
	callq	_BXT_PORT_PLL_ENABLE
	movl	%eax, %edi
	callq	_POSTING_READ
	movl	%r15d, %edi
	callq	_BXT_PORT_PLL_ENABLE
	movl	%eax, %edi
	callq	_I915_READ
	movq	_PORT_PLL_LOCK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movl	%eax, %edi
	movl	$200, %esi
	callq	_wait_for_us
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	leaq	L_.str.1(%rip), %rdi
	movl	%r15d, %esi
	callq	_DRM_ERROR
LBB0_5:
	movq	%r14, %rdi
	callq	_IS_GEMINILAKE
	testq	%rax, %rax
	je	LBB0_7
## %bb.6:
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	callq	_BXT_PORT_TX_DW5_LN0
	movl	%eax, %edi
	callq	_I915_READ
	movl	%eax, %ebx
	movq	_DCC_DELAY_RANGE_2@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	callq	_BXT_PORT_TX_DW5_GRP
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
LBB0_7:
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	callq	_BXT_PORT_PCS_DW12_LN01
	movl	%eax, %edi
	callq	_I915_READ
	movq	_LANE_STAGGER_MASK@GOTPCREL(%rip), %rcx
	movq	_LANESTAGGER_STRAP_OVRD@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	orl	40(%r12), %ebx
	movl	-48(%rbp), %edi
	movl	-44(%rbp), %esi
	callq	_BXT_PORT_PCS_DW12_GRP
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PORT_PLL_REF_SEL,4,2           ## @PORT_PLL_REF_SEL
	.comm	_PORT_PLL_POWER_ENABLE,4,2      ## @PORT_PLL_POWER_ENABLE
	.comm	_PORT_PLL_POWER_STATE,4,2       ## @PORT_PLL_POWER_STATE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Power state not set for PLL:%d\n"

	.comm	_PORT_PLL_10BIT_CLK_ENABLE,4,2  ## @PORT_PLL_10BIT_CLK_ENABLE
	.comm	_PORT_PLL_P1_MASK,4,2           ## @PORT_PLL_P1_MASK
	.comm	_PORT_PLL_P2_MASK,4,2           ## @PORT_PLL_P2_MASK
	.comm	_PORT_PLL_M2_MASK,4,2           ## @PORT_PLL_M2_MASK
	.comm	_PORT_PLL_N_MASK,4,2            ## @PORT_PLL_N_MASK
	.comm	_PORT_PLL_M2_FRAC_MASK,4,2      ## @PORT_PLL_M2_FRAC_MASK
	.comm	_PORT_PLL_M2_FRAC_ENABLE,4,2    ## @PORT_PLL_M2_FRAC_ENABLE
	.comm	_PORT_PLL_PROP_COEFF_MASK,4,2   ## @PORT_PLL_PROP_COEFF_MASK
	.comm	_PORT_PLL_INT_COEFF_MASK,4,2    ## @PORT_PLL_INT_COEFF_MASK
	.comm	_PORT_PLL_GAIN_CTL_MASK,4,2     ## @PORT_PLL_GAIN_CTL_MASK
	.comm	_PORT_PLL_TARGET_CNT_MASK,4,2   ## @PORT_PLL_TARGET_CNT_MASK
	.comm	_PORT_PLL_LOCK_THRESHOLD_MASK,4,2 ## @PORT_PLL_LOCK_THRESHOLD_MASK
	.comm	_PORT_PLL_DCO_AMP_OVR_EN_H,4,2  ## @PORT_PLL_DCO_AMP_OVR_EN_H
	.comm	_PORT_PLL_DCO_AMP_MASK,4,2      ## @PORT_PLL_DCO_AMP_MASK
	.comm	_PORT_PLL_RECALIBRATE,4,2       ## @PORT_PLL_RECALIBRATE
	.comm	_PORT_PLL_ENABLE,4,2            ## @PORT_PLL_ENABLE
	.comm	_PORT_PLL_LOCK,4,2              ## @PORT_PLL_LOCK
L_.str.1:                               ## @.str.1
	.asciz	"PLL %d not locked\n"

	.comm	_DCC_DELAY_RANGE_2,4,2          ## @DCC_DELAY_RANGE_2
	.comm	_LANE_STAGGER_MASK,4,2          ## @LANE_STAGGER_MASK
	.comm	_LANESTAGGER_STRAP_OVRD,4,2     ## @LANESTAGGER_STRAP_OVRD
	.no_dead_strip	_bxt_ddi_pll_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function bxt_ddi_pll_enable
_bxt_ddi_pll_enable:                    ; @bxt_ddi_pll_enable
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x1
	mov	x20, x0
	ldr	x8, [x1, #48]
	ldr	w21, [x8]
	add	x2, sp, #12
	add	x3, sp, #8
	mov	x1, x21
	bl	_bxt_port_to_phy_channel
	mov	x0, x21
	bl	_BXT_PORT_PLL_ENABLE
	bl	_I915_READ
Lloh0:
	adrp	x8, _PORT_PLL_REF_SEL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PORT_PLL_REF_SEL@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	orr	w22, w8, w0
	mov	x0, x21
	bl	_BXT_PORT_PLL_ENABLE
	mov	x1, x22
	bl	_I915_WRITE
	mov	x0, x20
	bl	_IS_GEMINILAKE
	cbz	x0, LBB0_3
; %bb.1:
	mov	x0, x21
	bl	_BXT_PORT_PLL_ENABLE
	bl	_I915_READ
Lloh3:
	adrp	x8, _PORT_PLL_POWER_ENABLE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PORT_PLL_POWER_ENABLE@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	orr	w22, w8, w0
	mov	x0, x21
	bl	_BXT_PORT_PLL_ENABLE
	mov	x1, x22
	bl	_I915_WRITE
	mov	x0, x21
	bl	_BXT_PORT_PLL_ENABLE
	bl	_I915_READ
Lloh6:
	adrp	x8, _PORT_PLL_POWER_STATE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PORT_PLL_POWER_STATE@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	and	w0, w8, w0
	mov	w1, #200
	bl	_wait_for_us
	cbz	x0, LBB0_3
; %bb.2:
Lloh9:
	adrp	x0, l_.str@PAGE
Lloh10:
	add	x0, x0, l_.str@PAGEOFF
	mov	x1, x21
	bl	_DRM_ERROR
LBB0_3:
	ldp	w1, w0, [sp, #8]
	bl	_BXT_PORT_PLL_EBB_4
	bl	_I915_READ
Lloh11:
	adrp	x23, _PORT_PLL_10BIT_CLK_ENABLE@GOTPAGE
Lloh12:
	ldr	x23, [x23, _PORT_PLL_10BIT_CLK_ENABLE@GOTPAGEOFF]
	ldr	w8, [x23]
	bic	w22, w0, w8
	ldp	w1, w0, [sp, #8]
	bl	_BXT_PORT_PLL_EBB_4
	mov	x1, x22
	bl	_I915_WRITE
	ldp	w1, w0, [sp, #8]
	bl	_BXT_PORT_PLL_EBB_0
	bl	_I915_READ
Lloh13:
	adrp	x8, _PORT_PLL_P1_MASK@GOTPAGE
Lloh14:
	ldr	x8, [x8, _PORT_PLL_P1_MASK@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
Lloh16:
	adrp	x9, _PORT_PLL_P2_MASK@GOTPAGE
Lloh17:
	ldr	x9, [x9, _PORT_PLL_P2_MASK@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
	ldr	w9, [x19]
	orr	w22, w8, w9
	ldp	w1, w0, [sp, #8]
	bl	_BXT_PORT_PLL_EBB_0
	mov	x1, x22
	bl	_I915_WRITE
	ldp	w1, w0, [sp, #8]
	mov	w2, #0
	bl	_BXT_PORT_PLL
	bl	_I915_READ
Lloh19:
	adrp	x8, _PORT_PLL_M2_MASK@GOTPAGE
Lloh20:
	ldr	x8, [x8, _PORT_PLL_M2_MASK@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
	bic	w8, w0, w8
	ldr	w9, [x19, #4]
	orr	w22, w8, w9
	ldp	w1, w0, [sp, #8]
	mov	w2, #0
	bl	_BXT_PORT_PLL
	mov	x1, x22
	bl	_I915_WRITE
	ldp	w1, w0, [sp, #8]
	mov	w2, #1
	bl	_BXT_PORT_PLL
	bl	_I915_READ
Lloh22:
	adrp	x8, _PORT_PLL_N_MASK@GOTPAGE
Lloh23:
	ldr	x8, [x8, _PORT_PLL_N_MASK@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	bic	w8, w0, w8
	ldr	w9, [x19, #8]
	orr	w22, w8, w9
	ldp	w1, w0, [sp, #8]
	mov	w2, #1
	bl	_BXT_PORT_PLL
	mov	x1, x22
	bl	_I915_WRITE
	ldp	w1, w0, [sp, #8]
	mov	w2, #2
	bl	_BXT_PORT_PLL
	bl	_I915_READ
Lloh25:
	adrp	x8, _PORT_PLL_M2_FRAC_MASK@GOTPAGE
Lloh26:
	ldr	x8, [x8, _PORT_PLL_M2_FRAC_MASK@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
	bic	w8, w0, w8
	ldr	w9, [x19, #12]
	orr	w22, w8, w9
	ldp	w1, w0, [sp, #8]
	mov	w2, #2
	bl	_BXT_PORT_PLL
	mov	x1, x22
	bl	_I915_WRITE
	ldp	w1, w0, [sp, #8]
	mov	w2, #3
	bl	_BXT_PORT_PLL
	bl	_I915_READ
Lloh28:
	adrp	x8, _PORT_PLL_M2_FRAC_ENABLE@GOTPAGE
Lloh29:
	ldr	x8, [x8, _PORT_PLL_M2_FRAC_ENABLE@GOTPAGEOFF]
Lloh30:
	ldr	w8, [x8]
	bic	w8, w0, w8
	ldr	w9, [x19, #16]
	orr	w22, w8, w9
	ldp	w1, w0, [sp, #8]
	mov	w2, #3
	bl	_BXT_PORT_PLL
	mov	x1, x22
	bl	_I915_WRITE
	ldp	w1, w0, [sp, #8]
	mov	w2, #6
	bl	_BXT_PORT_PLL
	bl	_I915_READ
Lloh31:
	adrp	x8, _PORT_PLL_PROP_COEFF_MASK@GOTPAGE
Lloh32:
	ldr	x8, [x8, _PORT_PLL_PROP_COEFF_MASK@GOTPAGEOFF]
Lloh33:
	adrp	x9, _PORT_PLL_INT_COEFF_MASK@GOTPAGE
Lloh34:
	ldr	x9, [x9, _PORT_PLL_INT_COEFF_MASK@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
Lloh36:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh37:
	adrp	x9, _PORT_PLL_GAIN_CTL_MASK@GOTPAGE
Lloh38:
	ldr	x9, [x9, _PORT_PLL_GAIN_CTL_MASK@GOTPAGEOFF]
Lloh39:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w8, w0, w8
	ldr	w9, [x19, #20]
	orr	w22, w8, w9
	ldp	w1, w0, [sp, #8]
	mov	w2, #6
	bl	_BXT_PORT_PLL
	mov	x1, x22
	bl	_I915_WRITE
	ldp	w1, w0, [sp, #8]
	mov	w2, #8
	bl	_BXT_PORT_PLL
	bl	_I915_READ
Lloh40:
	adrp	x8, _PORT_PLL_TARGET_CNT_MASK@GOTPAGE
Lloh41:
	ldr	x8, [x8, _PORT_PLL_TARGET_CNT_MASK@GOTPAGEOFF]
Lloh42:
	ldr	w8, [x8]
	bic	w8, w0, w8
	ldr	w9, [x19, #24]
	orr	w22, w8, w9
	ldp	w1, w0, [sp, #8]
	mov	w2, #8
	bl	_BXT_PORT_PLL
	mov	x1, x22
	bl	_I915_WRITE
	ldp	w1, w0, [sp, #8]
	mov	w2, #9
	bl	_BXT_PORT_PLL
	bl	_I915_READ
Lloh43:
	adrp	x8, _PORT_PLL_LOCK_THRESHOLD_MASK@GOTPAGE
Lloh44:
	ldr	x8, [x8, _PORT_PLL_LOCK_THRESHOLD_MASK@GOTPAGEOFF]
Lloh45:
	ldr	w8, [x8]
	bic	w8, w0, w8
	ldr	w9, [x19, #28]
	orr	w22, w8, w9
	ldp	w1, w0, [sp, #8]
	mov	w2, #9
	bl	_BXT_PORT_PLL
	mov	x1, x22
	bl	_I915_WRITE
	ldp	w1, w0, [sp, #8]
	mov	w2, #10
	bl	_BXT_PORT_PLL
	bl	_I915_READ
Lloh46:
	adrp	x8, _PORT_PLL_DCO_AMP_OVR_EN_H@GOTPAGE
Lloh47:
	ldr	x8, [x8, _PORT_PLL_DCO_AMP_OVR_EN_H@GOTPAGEOFF]
Lloh48:
	ldr	w8, [x8]
Lloh49:
	adrp	x9, _PORT_PLL_DCO_AMP_MASK@GOTPAGE
Lloh50:
	ldr	x9, [x9, _PORT_PLL_DCO_AMP_MASK@GOTPAGEOFF]
Lloh51:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
	ldr	w9, [x19, #32]
	orr	w22, w8, w9
	ldp	w1, w0, [sp, #8]
	mov	w2, #10
	bl	_BXT_PORT_PLL
	mov	x1, x22
	bl	_I915_WRITE
	ldp	w1, w0, [sp, #8]
	bl	_BXT_PORT_PLL_EBB_4
	bl	_I915_READ
Lloh52:
	adrp	x8, _PORT_PLL_RECALIBRATE@GOTPAGE
Lloh53:
	ldr	x8, [x8, _PORT_PLL_RECALIBRATE@GOTPAGEOFF]
Lloh54:
	ldr	w8, [x8]
	orr	w22, w8, w0
	ldp	w1, w0, [sp, #8]
	bl	_BXT_PORT_PLL_EBB_4
	mov	x1, x22
	bl	_I915_WRITE
	ldr	w8, [x23]
	bic	w8, w22, w8
	ldr	w9, [x19, #36]
	orr	w22, w8, w9
	ldp	w1, w0, [sp, #8]
	bl	_BXT_PORT_PLL_EBB_4
	mov	x1, x22
	bl	_I915_WRITE
	mov	x0, x21
	bl	_BXT_PORT_PLL_ENABLE
	bl	_I915_READ
Lloh55:
	adrp	x8, _PORT_PLL_ENABLE@GOTPAGE
Lloh56:
	ldr	x8, [x8, _PORT_PLL_ENABLE@GOTPAGEOFF]
Lloh57:
	ldr	w8, [x8]
	orr	w22, w8, w0
	mov	x0, x21
	bl	_BXT_PORT_PLL_ENABLE
	mov	x1, x22
	bl	_I915_WRITE
	mov	x0, x21
	bl	_BXT_PORT_PLL_ENABLE
	bl	_POSTING_READ
	mov	x0, x21
	bl	_BXT_PORT_PLL_ENABLE
	bl	_I915_READ
Lloh58:
	adrp	x8, _PORT_PLL_LOCK@GOTPAGE
Lloh59:
	ldr	x8, [x8, _PORT_PLL_LOCK@GOTPAGEOFF]
Lloh60:
	ldr	w8, [x8]
	and	w0, w8, w0
	mov	w1, #200
	bl	_wait_for_us
	cbz	x0, LBB0_5
; %bb.4:
Lloh61:
	adrp	x0, l_.str.1@PAGE
Lloh62:
	add	x0, x0, l_.str.1@PAGEOFF
	mov	x1, x21
	bl	_DRM_ERROR
LBB0_5:
	mov	x0, x20
	bl	_IS_GEMINILAKE
	cbz	x0, LBB0_7
; %bb.6:
	ldp	w1, w0, [sp, #8]
	bl	_BXT_PORT_TX_DW5_LN0
	bl	_I915_READ
Lloh63:
	adrp	x8, _DCC_DELAY_RANGE_2@GOTPAGE
Lloh64:
	ldr	x8, [x8, _DCC_DELAY_RANGE_2@GOTPAGEOFF]
Lloh65:
	ldr	w8, [x8]
	orr	w20, w8, w0
	ldp	w1, w0, [sp, #8]
	bl	_BXT_PORT_TX_DW5_GRP
	mov	x1, x20
	bl	_I915_WRITE
LBB0_7:
	ldp	w1, w0, [sp, #8]
	bl	_BXT_PORT_PCS_DW12_LN01
	bl	_I915_READ
Lloh66:
	adrp	x8, _LANE_STAGGER_MASK@GOTPAGE
Lloh67:
	ldr	x8, [x8, _LANE_STAGGER_MASK@GOTPAGEOFF]
Lloh68:
	ldr	w8, [x8]
Lloh69:
	adrp	x9, _LANESTAGGER_STRAP_OVRD@GOTPAGE
Lloh70:
	ldr	x9, [x9, _LANESTAGGER_STRAP_OVRD@GOTPAGEOFF]
Lloh71:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
	ldr	w9, [x19, #40]
	orr	w19, w8, w9
	ldp	w1, w0, [sp, #8]
	bl	_BXT_PORT_PCS_DW12_GRP
	mov	x1, x19
	bl	_I915_WRITE
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpAdd	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh35
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpAdd	Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.cfi_endproc
                                        ; -- End function
	.comm	_PORT_PLL_REF_SEL,4,2           ; @PORT_PLL_REF_SEL
	.comm	_PORT_PLL_POWER_ENABLE,4,2      ; @PORT_PLL_POWER_ENABLE
	.comm	_PORT_PLL_POWER_STATE,4,2       ; @PORT_PLL_POWER_STATE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Power state not set for PLL:%d\n"

	.comm	_PORT_PLL_10BIT_CLK_ENABLE,4,2  ; @PORT_PLL_10BIT_CLK_ENABLE
	.comm	_PORT_PLL_P1_MASK,4,2           ; @PORT_PLL_P1_MASK
	.comm	_PORT_PLL_P2_MASK,4,2           ; @PORT_PLL_P2_MASK
	.comm	_PORT_PLL_M2_MASK,4,2           ; @PORT_PLL_M2_MASK
	.comm	_PORT_PLL_N_MASK,4,2            ; @PORT_PLL_N_MASK
	.comm	_PORT_PLL_M2_FRAC_MASK,4,2      ; @PORT_PLL_M2_FRAC_MASK
	.comm	_PORT_PLL_M2_FRAC_ENABLE,4,2    ; @PORT_PLL_M2_FRAC_ENABLE
	.comm	_PORT_PLL_PROP_COEFF_MASK,4,2   ; @PORT_PLL_PROP_COEFF_MASK
	.comm	_PORT_PLL_INT_COEFF_MASK,4,2    ; @PORT_PLL_INT_COEFF_MASK
	.comm	_PORT_PLL_GAIN_CTL_MASK,4,2     ; @PORT_PLL_GAIN_CTL_MASK
	.comm	_PORT_PLL_TARGET_CNT_MASK,4,2   ; @PORT_PLL_TARGET_CNT_MASK
	.comm	_PORT_PLL_LOCK_THRESHOLD_MASK,4,2 ; @PORT_PLL_LOCK_THRESHOLD_MASK
	.comm	_PORT_PLL_DCO_AMP_OVR_EN_H,4,2  ; @PORT_PLL_DCO_AMP_OVR_EN_H
	.comm	_PORT_PLL_DCO_AMP_MASK,4,2      ; @PORT_PLL_DCO_AMP_MASK
	.comm	_PORT_PLL_RECALIBRATE,4,2       ; @PORT_PLL_RECALIBRATE
	.comm	_PORT_PLL_ENABLE,4,2            ; @PORT_PLL_ENABLE
	.comm	_PORT_PLL_LOCK,4,2              ; @PORT_PLL_LOCK
l_.str.1:                               ; @.str.1
	.asciz	"PLL %d not locked\n"

	.comm	_DCC_DELAY_RANGE_2,4,2          ; @DCC_DELAY_RANGE_2
	.comm	_LANE_STAGGER_MASK,4,2          ; @LANE_STAGGER_MASK
	.comm	_LANESTAGGER_STRAP_OVRD,4,2     ; @LANESTAGGER_STRAP_OVRD
	.no_dead_strip	_bxt_ddi_pll_enable
.subsections_via_symbols
