	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function hsw_pll_to_ddi_pll_sel
_hsw_pll_to_ddi_pll_sel:                ## @hsw_pll_to_ddi_pll_sel
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	(%rdi), %rax
	movl	(%rax), %edi
	leal	-128(%rdi), %eax
	cmpl	$6, %eax
	jae	LBB0_1
## %bb.2:
	cltq
	leaq	l_switch.table.hsw_pll_to_ddi_pll_sel(%rip), %rcx
	movq	(%rcx,%rax,8), %rax
	jmp	LBB0_3
LBB0_1:
                                        ## kill: def $edi killed $edi killed $rdi
	callq	_MISSING_CASE
	movq	_PORT_CLK_SEL_NONE@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %eax
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PORT_CLK_SEL_WRPLL1,4,2        ## @PORT_CLK_SEL_WRPLL1
	.comm	_PORT_CLK_SEL_WRPLL2,4,2        ## @PORT_CLK_SEL_WRPLL2
	.comm	_PORT_CLK_SEL_SPLL,4,2          ## @PORT_CLK_SEL_SPLL
	.comm	_PORT_CLK_SEL_LCPLL_810,4,2     ## @PORT_CLK_SEL_LCPLL_810
	.comm	_PORT_CLK_SEL_LCPLL_1350,4,2    ## @PORT_CLK_SEL_LCPLL_1350
	.comm	_PORT_CLK_SEL_LCPLL_2700,4,2    ## @PORT_CLK_SEL_LCPLL_2700
	.comm	_PORT_CLK_SEL_NONE,4,2          ## @PORT_CLK_SEL_NONE
	.no_dead_strip	_hsw_pll_to_ddi_pll_sel
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.hsw_pll_to_ddi_pll_sel
l_switch.table.hsw_pll_to_ddi_pll_sel:
	.quad	_PORT_CLK_SEL_WRPLL2
	.quad	_PORT_CLK_SEL_WRPLL1
	.quad	_PORT_CLK_SEL_SPLL
	.quad	_PORT_CLK_SEL_LCPLL_810
	.quad	_PORT_CLK_SEL_LCPLL_2700
	.quad	_PORT_CLK_SEL_LCPLL_1350

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function hsw_pll_to_ddi_pll_sel
_hsw_pll_to_ddi_pll_sel:                ; @hsw_pll_to_ddi_pll_sel
	.cfi_startproc
; %bb.0:
	stp	x29, x30, [sp, #-16]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 16
	mov	x29, sp
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	ldr	x8, [x0]
	ldr	w0, [x8]
	sub	w8, w0, #128
	cmp	w8, #6
	b.hs	LBB0_2
; %bb.1:
Lloh0:
	adrp	x9, l_switch.table.hsw_pll_to_ddi_pll_sel@PAGE
Lloh1:
	add	x9, x9, l_switch.table.hsw_pll_to_ddi_pll_sel@PAGEOFF
	ldr	x8, [x9, w8, sxtw #3]
	b	LBB0_3
LBB0_2:
	bl	_MISSING_CASE
Lloh2:
	adrp	x8, _PORT_CLK_SEL_NONE@GOTPAGE
Lloh3:
	ldr	x8, [x8, _PORT_CLK_SEL_NONE@GOTPAGEOFF]
LBB0_3:
	ldr	w0, [x8]
	ldp	x29, x30, [sp], #16             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh2, Lloh3
	.cfi_endproc
                                        ; -- End function
	.comm	_PORT_CLK_SEL_WRPLL1,4,2        ; @PORT_CLK_SEL_WRPLL1
	.comm	_PORT_CLK_SEL_WRPLL2,4,2        ; @PORT_CLK_SEL_WRPLL2
	.comm	_PORT_CLK_SEL_SPLL,4,2          ; @PORT_CLK_SEL_SPLL
	.comm	_PORT_CLK_SEL_LCPLL_810,4,2     ; @PORT_CLK_SEL_LCPLL_810
	.comm	_PORT_CLK_SEL_LCPLL_1350,4,2    ; @PORT_CLK_SEL_LCPLL_1350
	.comm	_PORT_CLK_SEL_LCPLL_2700,4,2    ; @PORT_CLK_SEL_LCPLL_2700
	.comm	_PORT_CLK_SEL_NONE,4,2          ; @PORT_CLK_SEL_NONE
	.no_dead_strip	_hsw_pll_to_ddi_pll_sel
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.hsw_pll_to_ddi_pll_sel
l_switch.table.hsw_pll_to_ddi_pll_sel:
	.quad	_PORT_CLK_SEL_WRPLL2
	.quad	_PORT_CLK_SEL_WRPLL1
	.quad	_PORT_CLK_SEL_SPLL
	.quad	_PORT_CLK_SEL_LCPLL_810
	.quad	_PORT_CLK_SEL_LCPLL_2700
	.quad	_PORT_CLK_SEL_LCPLL_1350

.subsections_via_symbols
