	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function amdgpu_ucode_init_single_fw
_amdgpu_ucode_init_single_fw:           ## @amdgpu_ucode_init_single_fw
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %rbx
	movq	24(%rsi), %rsi
	testq	%rsi, %rsi
	je	LBB0_33
## %bb.1:
	movl	%edx, 32(%rbx)
	movq	%rcx, 16(%rbx)
	movq	(%rbx), %rax
	movq	_AMDGPU_UCODE_ID_STORAGE@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rax
	je	LBB0_33
## %bb.2:
	movq	(%rsi), %r15
	movq	48(%rdi), %rdx
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rsi
	cmpq	(%rsi), %rdx
	jne	LBB0_11
## %bb.3:
	movq	_AMDGPU_UCODE_ID_CP_MEC1@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rax
	sete	%dl
	movq	_AMDGPU_UCODE_ID_CP_MEC2@GOTPCREL(%rip), %rsi
	cmpq	(%rsi), %rax
	sete	%r13b
	orb	%dl, %r13b
	movq	_AMDGPU_UCODE_ID_CP_MEC1_JT@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rsi
	movq	_AMDGPU_UCODE_ID_CP_MEC2_JT@GOTPCREL(%rip), %rdx
	movq	(%rdx), %r11
	movq	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL@GOTPCREL(%rip), %rdx
	movq	(%rdx), %r10
	movq	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM@GOTPCREL(%rip), %rdx
	movq	(%rdx), %r9
	movq	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM@GOTPCREL(%rip), %rdx
	movq	(%rdx), %r8
	movq	_AMDGPU_UCODE_ID_DMCU_ERAM@GOTPCREL(%rip), %rdx
	movq	(%rdx), %r12
	movq	_AMDGPU_UCODE_ID_DMCU_INTV@GOTPCREL(%rip), %rdx
	movq	(%rdx), %r14
	jne	LBB0_12
## %bb.4:
	cmpq	%rsi, %rax
	je	LBB0_12
## %bb.5:
	cmpq	%r11, %rax
	je	LBB0_12
## %bb.6:
	cmpq	%r10, %rax
	je	LBB0_12
## %bb.7:
	cmpq	%r9, %rax
	je	LBB0_12
## %bb.8:
	cmpq	%r8, %rax
	je	LBB0_12
## %bb.9:
	cmpq	%r12, %rax
	je	LBB0_12
## %bb.10:
	cmpq	%r14, %rax
	je	LBB0_12
LBB0_11:
	movl	4(%r15), %edi
	callq	_le32_to_cpu
	movl	%eax, 8(%rbx)
LBB0_20:
	movq	16(%rbx), %r14
	movq	24(%rbx), %rax
	movq	(%rax), %r12
LBB0_21:
	movl	(%r15), %edi
	callq	_le32_to_cpu
LBB0_22:
	cltq
	leaq	(%r12,%rax,4), %rsi
	movl	8(%rbx), %edx
	movq	%r14, %rdi
LBB0_32:
	callq	_memcpy
LBB0_33:
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_12:
	testb	%r13b, %r13b
	je	LBB0_14
## %bb.13:
	movl	4(%r15), %edi
	callq	_le32_to_cpu
	movl	%eax, %r14d
	movl	4(%r15), %edi
	callq	_le32_to_cpu
	shll	$2, %eax
LBB0_19:
	subl	%eax, %r14d
	movl	%r14d, 8(%rbx)
	jmp	LBB0_20
LBB0_14:
	cmpq	%rsi, %rax
	je	LBB0_16
## %bb.15:
	cmpq	%r11, %rax
	je	LBB0_16
## %bb.17:
	cmpq	%r12, %rax
	jne	LBB0_23
## %bb.18:
	movl	4(%r15), %edi
	callq	_le32_to_cpu
	movl	%eax, %r14d
	movl	4(%r15), %edi
	callq	_le32_to_cpu
	jmp	LBB0_19
LBB0_16:
	movl	4(%r15), %edi
	callq	_le32_to_cpu
	shll	$2, %eax
	movl	%eax, 8(%rbx)
	movq	16(%rbx), %r14
	movq	24(%rbx), %rax
	movq	(%rax), %r12
	movl	(%r15), %edi
	callq	_le32_to_cpu
	cltq
	leaq	(%r12,%rax,4), %r12
	movl	(%r15), %edi
	callq	_le32_to_cpu
	shll	$2, %eax
	jmp	LBB0_22
LBB0_23:
	cmpq	%r14, %rax
	jne	LBB0_25
## %bb.24:
	movl	4(%r15), %edi
	callq	_le32_to_cpu
	movl	%eax, 8(%rbx)
	movq	16(%rbx), %r14
	movq	24(%rbx), %rax
	movq	(%rax), %r12
	movl	(%r15), %edi
	callq	_le32_to_cpu
	cltq
	leaq	(%r12,%rax,4), %r12
	jmp	LBB0_21
LBB0_25:
	cmpq	%r10, %rax
	jne	LBB0_27
## %bb.26:
	movl	(%rdi), %edx
	movl	%edx, 8(%rbx)
	movq	8(%rdi), %rsi
	jmp	LBB0_31
LBB0_27:
	cmpq	%r9, %rax
	jne	LBB0_29
## %bb.28:
	movl	16(%rdi), %edx
	movl	%edx, 8(%rbx)
	movq	24(%rdi), %rsi
	jmp	LBB0_31
LBB0_29:
	cmpq	%r8, %rax
	jne	LBB0_33
## %bb.30:
	movl	32(%rdi), %edx
	movl	%edx, 8(%rbx)
	movq	40(%rdi), %rsi
LBB0_31:
	movq	%rcx, %rdi
	jmp	LBB0_32
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_UCODE_ID_STORAGE,8,3    ## @AMDGPU_UCODE_ID_STORAGE
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_CP_MEC1,8,3    ## @AMDGPU_UCODE_ID_CP_MEC1
	.comm	_AMDGPU_UCODE_ID_CP_MEC2,8,3    ## @AMDGPU_UCODE_ID_CP_MEC2
	.comm	_AMDGPU_UCODE_ID_CP_MEC1_JT,8,3 ## @AMDGPU_UCODE_ID_CP_MEC1_JT
	.comm	_AMDGPU_UCODE_ID_CP_MEC2_JT,8,3 ## @AMDGPU_UCODE_ID_CP_MEC2_JT
	.comm	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,8,3 ## @AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
	.comm	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,8,3 ## @AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
	.comm	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,8,3 ## @AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
	.comm	_AMDGPU_UCODE_ID_DMCU_ERAM,8,3  ## @AMDGPU_UCODE_ID_DMCU_ERAM
	.comm	_AMDGPU_UCODE_ID_DMCU_INTV,8,3  ## @AMDGPU_UCODE_ID_DMCU_INTV
	.no_dead_strip	_amdgpu_ucode_init_single_fw
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function amdgpu_ucode_init_single_fw
_amdgpu_ucode_init_single_fw:           ; @amdgpu_ucode_init_single_fw
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	ldr	x9, [x1, #24]
	cbz	x9, LBB0_16
; %bb.1:
	mov	x19, x1
	str	w2, [x1, #32]
	str	x3, [x1, #16]
	ldr	x8, [x1]
Lloh0:
	adrp	x10, _AMDGPU_UCODE_ID_STORAGE@GOTPAGE
Lloh1:
	ldr	x10, [x10, _AMDGPU_UCODE_ID_STORAGE@GOTPAGEOFF]
Lloh2:
	ldr	x10, [x10]
	cmp	x8, x10
	b.eq	LBB0_16
; %bb.2:
	ldr	x21, [x9]
	ldr	x9, [x0, #48]
Lloh3:
	adrp	x10, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh4:
	ldr	x10, [x10, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh5:
	ldr	x10, [x10]
	cmp	x9, x10
	b.ne	LBB0_11
; %bb.3:
Lloh6:
	adrp	x9, _AMDGPU_UCODE_ID_CP_MEC1@GOTPAGE
Lloh7:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_CP_MEC1@GOTPAGEOFF]
Lloh8:
	ldr	x9, [x9]
	cmp	x8, x9
Lloh9:
	adrp	x9, _AMDGPU_UCODE_ID_CP_MEC2@GOTPAGE
Lloh10:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_CP_MEC2@GOTPAGEOFF]
Lloh11:
	ldr	x9, [x9]
	ccmp	x8, x9, #4, ne
	cset	w15, eq
Lloh12:
	adrp	x9, _AMDGPU_UCODE_ID_CP_MEC1_JT@GOTPAGE
Lloh13:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_CP_MEC1_JT@GOTPAGEOFF]
Lloh14:
	ldr	x13, [x9]
Lloh15:
	adrp	x9, _AMDGPU_UCODE_ID_CP_MEC2_JT@GOTPAGE
Lloh16:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_CP_MEC2_JT@GOTPAGEOFF]
Lloh17:
	ldr	x12, [x9]
Lloh18:
	adrp	x9, _AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL@GOTPAGE
Lloh19:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL@GOTPAGEOFF]
Lloh20:
	ldr	x11, [x9]
Lloh21:
	adrp	x9, _AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM@GOTPAGE
Lloh22:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM@GOTPAGEOFF]
Lloh23:
	ldr	x10, [x9]
Lloh24:
	adrp	x9, _AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM@GOTPAGE
Lloh25:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM@GOTPAGEOFF]
Lloh26:
	ldr	x9, [x9]
Lloh27:
	adrp	x14, _AMDGPU_UCODE_ID_DMCU_ERAM@GOTPAGE
Lloh28:
	ldr	x14, [x14, _AMDGPU_UCODE_ID_DMCU_ERAM@GOTPAGEOFF]
Lloh29:
	ldr	x16, [x14]
Lloh30:
	adrp	x14, _AMDGPU_UCODE_ID_DMCU_INTV@GOTPAGE
Lloh31:
	ldr	x14, [x14, _AMDGPU_UCODE_ID_DMCU_INTV@GOTPAGEOFF]
Lloh32:
	ldr	x14, [x14]
	b.eq	LBB0_17
; %bb.4:
	cmp	x8, x13
	b.eq	LBB0_17
; %bb.5:
	cmp	x8, x12
	b.eq	LBB0_17
; %bb.6:
	cmp	x8, x11
	b.eq	LBB0_17
; %bb.7:
	cmp	x8, x10
	b.eq	LBB0_17
; %bb.8:
	cmp	x8, x9
	b.eq	LBB0_17
; %bb.9:
	cmp	x8, x16
	b.eq	LBB0_17
; %bb.10:
	cmp	x8, x14
	b.eq	LBB0_17
LBB0_11:
	ldr	w0, [x21, #4]
	bl	_le32_to_cpu
	str	w0, [x19, #8]
LBB0_12:
	ldp	x20, x8, [x19, #16]
	ldr	x22, [x8]
LBB0_13:
	ldr	w0, [x21]
	bl	_le32_to_cpu
	add	x1, x22, w0, sxtw #2
LBB0_14:
	ldr	w2, [x19, #8]
	mov	x0, x20
LBB0_15:
	bl	_memcpy
LBB0_16:
	mov	w0, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_17:
	cbz	w15, LBB0_20
; %bb.18:
	ldr	w0, [x21, #4]
	bl	_le32_to_cpu
	mov	x20, x0
	ldr	w0, [x21, #4]
	bl	_le32_to_cpu
	sub	w8, w20, w0, lsl #2
LBB0_19:
	str	w8, [x19, #8]
	b	LBB0_12
LBB0_20:
	cmp	x8, x13
	b.eq	LBB0_24
; %bb.21:
	cmp	x8, x12
	b.eq	LBB0_24
; %bb.22:
	cmp	x8, x16
	b.ne	LBB0_25
; %bb.23:
	ldr	w0, [x21, #4]
	bl	_le32_to_cpu
	mov	x20, x0
	ldr	w0, [x21, #4]
	bl	_le32_to_cpu
	sub	w8, w20, w0
	b	LBB0_19
LBB0_24:
	ldr	w0, [x21, #4]
	bl	_le32_to_cpu
	lsl	w8, w0, #2
	str	w8, [x19, #8]
	ldp	x20, x8, [x19, #16]
	ldr	x22, [x8]
	ldr	w0, [x21]
	bl	_le32_to_cpu
	add	x22, x22, w0, sxtw #2
	ldr	w0, [x21]
	bl	_le32_to_cpu
	lsl	w8, w0, #2
	add	x1, x22, w8, sxtw #2
	b	LBB0_14
LBB0_25:
	cmp	x8, x14
	b.ne	LBB0_27
; %bb.26:
	ldr	w0, [x21, #4]
	bl	_le32_to_cpu
	str	w0, [x19, #8]
	ldp	x20, x8, [x19, #16]
	ldr	x22, [x8]
	ldr	w0, [x21]
	bl	_le32_to_cpu
	add	x22, x22, w0, sxtw #2
	b	LBB0_13
LBB0_27:
	cmp	x8, x11
	b.ne	LBB0_29
; %bb.28:
	ldr	w2, [x0]
	str	w2, [x19, #8]
	ldr	x1, [x0, #8]
	b	LBB0_33
LBB0_29:
	cmp	x8, x10
	b.ne	LBB0_31
; %bb.30:
	ldr	w2, [x0, #16]
	str	w2, [x19, #8]
	ldr	x1, [x0, #24]
	b	LBB0_33
LBB0_31:
	cmp	x8, x9
	b.ne	LBB0_16
; %bb.32:
	ldr	w2, [x0, #32]
	str	w2, [x19, #8]
	ldr	x1, [x0, #40]
LBB0_33:
	mov	x0, x3
	b	LBB0_15
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_UCODE_ID_STORAGE,8,3    ; @AMDGPU_UCODE_ID_STORAGE
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_CP_MEC1,8,3    ; @AMDGPU_UCODE_ID_CP_MEC1
	.comm	_AMDGPU_UCODE_ID_CP_MEC2,8,3    ; @AMDGPU_UCODE_ID_CP_MEC2
	.comm	_AMDGPU_UCODE_ID_CP_MEC1_JT,8,3 ; @AMDGPU_UCODE_ID_CP_MEC1_JT
	.comm	_AMDGPU_UCODE_ID_CP_MEC2_JT,8,3 ; @AMDGPU_UCODE_ID_CP_MEC2_JT
	.comm	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,8,3 ; @AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
	.comm	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,8,3 ; @AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
	.comm	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,8,3 ; @AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
	.comm	_AMDGPU_UCODE_ID_DMCU_ERAM,8,3  ; @AMDGPU_UCODE_ID_DMCU_ERAM
	.comm	_AMDGPU_UCODE_ID_DMCU_INTV,8,3  ; @AMDGPU_UCODE_ID_DMCU_INTV
	.no_dead_strip	_amdgpu_ucode_init_single_fw
.subsections_via_symbols
