	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dw_mipi_dsi_phy_init
_dw_mipi_dsi_phy_init:                  ## @dw_mipi_dsi_phy_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movl	(%rdi), %edi
	xorl	%ebx, %ebx
	cmpl	$200, %edi
	jl	LBB0_2
## %bb.1:
	leal	100(%rdi), %eax
	imulq	$1374389535, %rax, %rbx         ## imm = 0x51EB851F
	shrq	$38, %rbx
LBB0_2:
                                        ## kill: def $edi killed $edi killed $rdi
	callq	_max_mbps_to_parameter
	movl	%eax, %r15d
	testl	%eax, %eax
	js	LBB0_3
## %bb.4:
	movl	4(%r14), %edi
	callq	_clk_prepare_enable
	testl	%eax, %eax
	je	LBB0_6
## %bb.5:
	movl	%eax, %r12d
	movl	16(%r14), %edi
	leaq	L_.str.1(%rip), %rsi
	xorl	%eax, %eax
	callq	_DRM_DEV_ERROR
	movl	%r12d, %r15d
	jmp	LBB0_7
LBB0_3:
	movl	(%r14), %edx
	movl	16(%r14), %edi
	leaq	L_.str(%rip), %rsi
	xorl	%eax, %eax
	callq	_DRM_DEV_ERROR
	jmp	LBB0_7
LBB0_6:
	movq	_PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	_BYPASS_VCO_RANGE@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	%ebx, %edi
	callq	_VCO_RANGE_CON_SEL
	orl	%eax, %r13d
	movq	_VCO_IN_CAP_CON_LOW@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	movq	_REF_BIAS_CUR_SEL@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	movq	%r14, %rdi
	movl	%r12d, %esi
	movl	%r13d, %edx
	callq	_dw_mipi_dsi_phy_write
	movq	_PLL_CP_CONTROL_PLL_LOCK_BYPASS@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_dppa_map@GOTPCREL(%rip), %r12
	movq	(%r12), %rax
	movl	%r15d, %ecx
	shlq	$2, %rcx
	leaq	(%rcx,%rcx,2), %r13
	movl	8(%rax,%r13), %edi
	callq	_CP_CURRENT_SEL
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_dw_mipi_dsi_phy_write
	movq	_PLL_LPF_AND_CP_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_CP_PROGRAM_EN@GOTPCREL(%rip), %rax
	movq	_LPF_PROGRAM_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	(%r12), %rax
	movl	4(%rax,%r13), %edi
	callq	_LPF_RESISTORS_SEL
	orl	%eax, %ebx
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_dw_mipi_dsi_phy_write
	movq	_HS_RX_CONTROL_OF_LANE_0@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	(%r12), %rax
	movl	(%rax,%r13), %edi
	callq	_HSFREQRANGE_SEL
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_dw_mipi_dsi_phy_write
	movq	_PLL_INPUT_DIVIDER_RATIO@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	12(%r14), %edi
	callq	_INPUT_DIVIDER
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_dw_mipi_dsi_phy_write
	movq	_PLL_LOOP_DIVIDER_RATIO@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	8(%r14), %edi
	callq	_LOOP_DIV_LOW_SEL
	movq	_LOW_PROGRAM_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_dw_mipi_dsi_phy_write
	movq	_PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	_PLL_LOOP_DIV_EN@GOTPCREL(%rip), %r12
	movq	_PLL_INPUT_DIV_EN@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	orl	(%r12), %edx
	movq	%r14, %rdi
	callq	_dw_mipi_dsi_phy_write
	movq	_PLL_LOOP_DIVIDER_RATIO@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	8(%r14), %edi
	callq	_LOOP_DIV_HIGH_SEL
	movq	_HIGH_PROGRAM_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_dw_mipi_dsi_phy_write
	movl	(%r13), %esi
	movl	(%r15), %edx
	orl	(%r12), %edx
	movq	%r14, %rdi
	callq	_dw_mipi_dsi_phy_write
	movq	_AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY@GOTPCREL(%rip), %r12
	movl	(%r12), %r15d
	movq	_LOW_PROGRAM_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_BIASEXTR_127_7@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_BIASEXTR_SEL
	orl	%eax, %ebx
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_dw_mipi_dsi_phy_write
	movl	(%r12), %r15d
	movq	_HIGH_PROGRAM_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_BANDGAP_96_10@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_BANDGAP_SEL
	orl	%eax, %ebx
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_dw_mipi_dsi_phy_write
	movq	_POWER_CONTROL@GOTPCREL(%rip), %rax
	movq	_INTERNAL_REG_CURRENT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	_BANDGAP_AND_BIAS_CONTROL@GOTPCREL(%rip), %rax
	movq	_BIAS_BLOCK_ON@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movl	(%rax), %esi
	movq	_BANDGAP_ON@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	%r14, %rdi
	callq	_dw_mipi_dsi_phy_write
	movq	_TER_RESISTOR_LOW@GOTPCREL(%rip), %rax
	movq	_TER_CAL_DONE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	_TERMINATION_RESISTER_CONTROL@GOTPCREL(%rip), %rbx
	movq	_SETRD_MAX@GOTPCREL(%rip), %r15
	orl	(%r15), %edx
	movl	(%rbx), %esi
	movq	_TER_RESISTORS_ON@GOTPCREL(%rip), %r12
	orl	(%r12), %edx
	movq	%r14, %rdi
	callq	_dw_mipi_dsi_phy_write
	movq	_TER_RESISTOR_HIGH@GOTPCREL(%rip), %rax
	movq	_LEVEL_SHIFTERS_ON@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movl	(%rbx), %esi
	orl	(%r15), %edx
	movq	_POWER_MANAGE@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	orl	(%r12), %edx
	movq	%r14, %rdi
	callq	_dw_mipi_dsi_phy_write
	movq	_HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_TLP_PROGRAM_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	%r14, %rdi
	movl	$500, %esi                      ## imm = 0x1F4
	callq	_ns2bc
	orl	%eax, %ebx
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_dw_mipi_dsi_phy_write
	movq	_HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_THS_PRE_PROGRAM_EN@GOTPCREL(%rip), %r12
	movl	(%r12), %ebx
	movq	%r14, %rdi
	movl	$40, %esi
	callq	_ns2ui
	orl	%eax, %ebx
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_dw_mipi_dsi_phy_write
	movq	_HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_THS_ZERO_PROGRAM_EN@GOTPCREL(%rip), %r13
	movl	(%r13), %ebx
	movq	%r14, %rdi
	movl	$300, %esi                      ## imm = 0x12C
	callq	_ns2bc
	orl	%eax, %ebx
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_dw_mipi_dsi_phy_write
	movq	_HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	(%r12), %ebx
	movq	%r14, %rdi
	movl	$100, %esi
	callq	_ns2ui
	orl	%eax, %ebx
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_dw_mipi_dsi_phy_write
	movq	_HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	$5, %edi
	callq	_BIT
	movl	%eax, %ebx
	movq	%r14, %rdi
	movl	$100, %esi
	callq	_ns2bc
	orl	%eax, %ebx
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_dw_mipi_dsi_phy_write
	movq	_HS_TX_CLOCK_LANE_POST_TIME_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	$5, %edi
	callq	_BIT
	movl	%eax, %ebx
	movq	%r14, %rdi
	movl	$60, %esi
	callq	_ns2bc
                                        ## kill: def $eax killed $eax def $rax
	leal	7(%rax), %edx
	orl	%ebx, %edx
	movq	%r14, %rdi
	movl	%r15d, %esi
	callq	_dw_mipi_dsi_phy_write
	movq	_HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_TLP_PROGRAM_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	%r14, %rdi
	movl	$500, %esi                      ## imm = 0x1F4
	callq	_ns2bc
	orl	%eax, %ebx
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_dw_mipi_dsi_phy_write
	movq	_HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	(%r12), %ebx
	movq	%r14, %rdi
	movl	$50, %esi
	callq	_ns2ui
                                        ## kill: def $eax killed $eax def $rax
	leal	20(%rax), %edx
	orl	%ebx, %edx
	movq	%r14, %rdi
	movl	%r15d, %esi
	callq	_dw_mipi_dsi_phy_write
	movq	_HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	(%r13), %ebx
	movq	%r14, %rdi
	movl	$140, %esi
	callq	_ns2bc
                                        ## kill: def $eax killed $eax def $rax
	leal	2(%rax), %edx
	orl	%ebx, %edx
	movq	%r14, %rdi
	movl	%r15d, %esi
	callq	_dw_mipi_dsi_phy_write
	movq	_HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	(%r12), %ebx
	movq	%r14, %rdi
	movl	$60, %esi
	callq	_ns2ui
                                        ## kill: def $eax killed $eax def $rax
	leal	8(%rax), %edx
	orl	%ebx, %edx
	movq	%r14, %rdi
	movl	%r15d, %esi
	callq	_dw_mipi_dsi_phy_write
	movq	_HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	$5, %edi
	callq	_BIT
	movl	%eax, %ebx
	movq	%r14, %rdi
	movl	$100, %esi
	callq	_ns2bc
	orl	%eax, %ebx
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_dw_mipi_dsi_phy_write
	movl	4(%r14), %edi
	callq	_clk_disable_unprepare
	xorl	%r15d, %r15d
LBB0_7:
	movl	%r15d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"failed to get parameter for %dmbps clock\n"

L_.str.1:                               ## @.str.1
	.asciz	"Failed to enable phy_cfg_clk\n"

	.comm	_PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,4,2 ## @PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL
	.comm	_BYPASS_VCO_RANGE,4,2           ## @BYPASS_VCO_RANGE
	.comm	_VCO_IN_CAP_CON_LOW,4,2         ## @VCO_IN_CAP_CON_LOW
	.comm	_REF_BIAS_CUR_SEL,4,2           ## @REF_BIAS_CUR_SEL
	.comm	_PLL_CP_CONTROL_PLL_LOCK_BYPASS,4,2 ## @PLL_CP_CONTROL_PLL_LOCK_BYPASS
	.comm	_dppa_map,8,3                   ## @dppa_map
	.comm	_PLL_LPF_AND_CP_CONTROL,4,2     ## @PLL_LPF_AND_CP_CONTROL
	.comm	_CP_PROGRAM_EN,4,2              ## @CP_PROGRAM_EN
	.comm	_LPF_PROGRAM_EN,4,2             ## @LPF_PROGRAM_EN
	.comm	_HS_RX_CONTROL_OF_LANE_0,4,2    ## @HS_RX_CONTROL_OF_LANE_0
	.comm	_PLL_INPUT_DIVIDER_RATIO,4,2    ## @PLL_INPUT_DIVIDER_RATIO
	.comm	_PLL_LOOP_DIVIDER_RATIO,4,2     ## @PLL_LOOP_DIVIDER_RATIO
	.comm	_LOW_PROGRAM_EN,4,2             ## @LOW_PROGRAM_EN
	.comm	_PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,4,2 ## @PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL
	.comm	_PLL_LOOP_DIV_EN,4,2            ## @PLL_LOOP_DIV_EN
	.comm	_PLL_INPUT_DIV_EN,4,2           ## @PLL_INPUT_DIV_EN
	.comm	_HIGH_PROGRAM_EN,4,2            ## @HIGH_PROGRAM_EN
	.comm	_AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,4,2 ## @AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY
	.comm	_BIASEXTR_127_7,4,2             ## @BIASEXTR_127_7
	.comm	_BANDGAP_96_10,4,2              ## @BANDGAP_96_10
	.comm	_BANDGAP_AND_BIAS_CONTROL,4,2   ## @BANDGAP_AND_BIAS_CONTROL
	.comm	_POWER_CONTROL,4,2              ## @POWER_CONTROL
	.comm	_INTERNAL_REG_CURRENT,4,2       ## @INTERNAL_REG_CURRENT
	.comm	_BIAS_BLOCK_ON,4,2              ## @BIAS_BLOCK_ON
	.comm	_BANDGAP_ON,4,2                 ## @BANDGAP_ON
	.comm	_TERMINATION_RESISTER_CONTROL,4,2 ## @TERMINATION_RESISTER_CONTROL
	.comm	_TER_RESISTOR_LOW,4,2           ## @TER_RESISTOR_LOW
	.comm	_TER_CAL_DONE,4,2               ## @TER_CAL_DONE
	.comm	_SETRD_MAX,4,2                  ## @SETRD_MAX
	.comm	_TER_RESISTORS_ON,4,2           ## @TER_RESISTORS_ON
	.comm	_TER_RESISTOR_HIGH,4,2          ## @TER_RESISTOR_HIGH
	.comm	_LEVEL_SHIFTERS_ON,4,2          ## @LEVEL_SHIFTERS_ON
	.comm	_POWER_MANAGE,4,2               ## @POWER_MANAGE
	.comm	_HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,4,2 ## @HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL
	.comm	_TLP_PROGRAM_EN,4,2             ## @TLP_PROGRAM_EN
	.comm	_HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,4,2 ## @HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL
	.comm	_THS_PRE_PROGRAM_EN,4,2         ## @THS_PRE_PROGRAM_EN
	.comm	_HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,4,2 ## @HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL
	.comm	_THS_ZERO_PROGRAM_EN,4,2        ## @THS_ZERO_PROGRAM_EN
	.comm	_HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,4,2 ## @HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL
	.comm	_HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,4,2 ## @HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL
	.comm	_HS_TX_CLOCK_LANE_POST_TIME_CONTROL,4,2 ## @HS_TX_CLOCK_LANE_POST_TIME_CONTROL
	.comm	_HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,4,2 ## @HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL
	.comm	_HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,4,2 ## @HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL
	.comm	_HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,4,2 ## @HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL
	.comm	_HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,4,2 ## @HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL
	.comm	_HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,4,2 ## @HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL
	.no_dead_strip	_dw_mipi_dsi_phy_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dw_mipi_dsi_phy_init
_dw_mipi_dsi_phy_init:                  ; @dw_mipi_dsi_phy_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldr	w0, [x0]
	add	w8, w0, #100
	mov	w9, #34079
	movk	w9, #20971, lsl #16
	umull	x8, w8, w9
	lsr	x8, x8, #38
	cmp	w0, #200
	csel	w21, wzr, w8, lt
	bl	_max_mbps_to_parameter
	mov	x20, x0
	tbnz	w0, #31, LBB0_3
; %bb.1:
	ldr	w0, [x19, #4]
	bl	_clk_prepare_enable
	cbz	w0, LBB0_4
; %bb.2:
	mov	x22, x0
	ldr	w0, [x19, #16]
Lloh0:
	adrp	x1, l_.str.1@PAGE
Lloh1:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_DRM_DEV_ERROR
	mov	x20, x22
	b	LBB0_5
LBB0_3:
	ldr	w0, [x19, #16]
	ldr	w8, [x19]
	str	x8, [sp]
Lloh2:
	adrp	x1, l_.str@PAGE
Lloh3:
	add	x1, x1, l_.str@PAGEOFF
	bl	_DRM_DEV_ERROR
	b	LBB0_5
LBB0_4:
Lloh4:
	adrp	x8, _PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL@GOTPAGE
Lloh5:
	ldr	x8, [x8, _PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL@GOTPAGEOFF]
Lloh6:
	ldr	w22, [x8]
Lloh7:
	adrp	x8, _BYPASS_VCO_RANGE@GOTPAGE
Lloh8:
	ldr	x8, [x8, _BYPASS_VCO_RANGE@GOTPAGEOFF]
Lloh9:
	ldr	w23, [x8]
	mov	x0, x21
	bl	_VCO_RANGE_CON_SEL
	orr	w8, w0, w23
Lloh10:
	adrp	x9, _VCO_IN_CAP_CON_LOW@GOTPAGE
Lloh11:
	ldr	x9, [x9, _VCO_IN_CAP_CON_LOW@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh13:
	adrp	x9, _REF_BIAS_CUR_SEL@GOTPAGE
Lloh14:
	ldr	x9, [x9, _REF_BIAS_CUR_SEL@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x19
	mov	x1, x22
	bl	_dw_mipi_dsi_phy_write
Lloh16:
	adrp	x8, _PLL_CP_CONTROL_PLL_LOCK_BYPASS@GOTPAGE
Lloh17:
	ldr	x8, [x8, _PLL_CP_CONTROL_PLL_LOCK_BYPASS@GOTPAGEOFF]
Lloh18:
	adrp	x22, _dppa_map@GOTPAGE
Lloh19:
	ldr	x22, [x22, _dppa_map@GOTPAGEOFF]
Lloh20:
	ldr	w21, [x8]
	ldr	x8, [x22]
	mov	w23, #12
	umaddl	x8, w20, w23, x8
	umull	x24, w20, w23
	ldr	w0, [x8, #8]
	bl	_CP_CURRENT_SEL
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_dw_mipi_dsi_phy_write
Lloh21:
	adrp	x8, _PLL_LPF_AND_CP_CONTROL@GOTPAGE
Lloh22:
	ldr	x8, [x8, _PLL_LPF_AND_CP_CONTROL@GOTPAGEOFF]
Lloh23:
	ldr	w21, [x8]
Lloh24:
	adrp	x8, _CP_PROGRAM_EN@GOTPAGE
Lloh25:
	ldr	x8, [x8, _CP_PROGRAM_EN@GOTPAGEOFF]
Lloh26:
	adrp	x9, _LPF_PROGRAM_EN@GOTPAGE
Lloh27:
	ldr	x9, [x9, _LPF_PROGRAM_EN@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
Lloh29:
	ldr	w9, [x9]
	orr	w25, w9, w8
	ldr	x8, [x22]
	umaddl	x8, w20, w23, x8
	ldr	w0, [x8, #4]
	bl	_LPF_RESISTORS_SEL
	orr	w2, w25, w0
	mov	x0, x19
	mov	x1, x21
	bl	_dw_mipi_dsi_phy_write
Lloh30:
	adrp	x8, _HS_RX_CONTROL_OF_LANE_0@GOTPAGE
Lloh31:
	ldr	x8, [x8, _HS_RX_CONTROL_OF_LANE_0@GOTPAGEOFF]
Lloh32:
	ldr	w20, [x8]
	ldr	x8, [x22]
	ldr	w0, [x8, x24]
	bl	_HSFREQRANGE_SEL
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_dw_mipi_dsi_phy_write
Lloh33:
	adrp	x8, _PLL_INPUT_DIVIDER_RATIO@GOTPAGE
Lloh34:
	ldr	x8, [x8, _PLL_INPUT_DIVIDER_RATIO@GOTPAGEOFF]
Lloh35:
	ldr	w20, [x8]
	ldr	w0, [x19, #12]
	bl	_INPUT_DIVIDER
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_dw_mipi_dsi_phy_write
Lloh36:
	adrp	x21, _PLL_LOOP_DIVIDER_RATIO@GOTPAGE
Lloh37:
	ldr	x21, [x21, _PLL_LOOP_DIVIDER_RATIO@GOTPAGEOFF]
	ldr	w20, [x21]
	ldr	w0, [x19, #8]
	bl	_LOOP_DIV_LOW_SEL
Lloh38:
	adrp	x22, _LOW_PROGRAM_EN@GOTPAGE
Lloh39:
	ldr	x22, [x22, _LOW_PROGRAM_EN@GOTPAGEOFF]
	ldr	w8, [x22]
	orr	w2, w8, w0
	mov	x0, x19
	mov	x1, x20
	bl	_dw_mipi_dsi_phy_write
Lloh40:
	adrp	x23, _PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL@GOTPAGE
Lloh41:
	ldr	x23, [x23, _PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL@GOTPAGEOFF]
Lloh42:
	adrp	x24, _PLL_LOOP_DIV_EN@GOTPAGE
Lloh43:
	ldr	x24, [x24, _PLL_LOOP_DIV_EN@GOTPAGEOFF]
	ldr	w1, [x23]
	ldr	w8, [x24]
Lloh44:
	adrp	x25, _PLL_INPUT_DIV_EN@GOTPAGE
Lloh45:
	ldr	x25, [x25, _PLL_INPUT_DIV_EN@GOTPAGEOFF]
	ldr	w9, [x25]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_dw_mipi_dsi_phy_write
	ldr	w20, [x21]
	ldr	w0, [x19, #8]
	bl	_LOOP_DIV_HIGH_SEL
Lloh46:
	adrp	x21, _HIGH_PROGRAM_EN@GOTPAGE
Lloh47:
	ldr	x21, [x21, _HIGH_PROGRAM_EN@GOTPAGEOFF]
	ldr	w8, [x21]
	orr	w2, w8, w0
	mov	x0, x19
	mov	x1, x20
	bl	_dw_mipi_dsi_phy_write
	ldr	w1, [x23]
	ldr	w8, [x24]
	ldr	w9, [x25]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_dw_mipi_dsi_phy_write
Lloh48:
	adrp	x23, _AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY@GOTPAGE
Lloh49:
	ldr	x23, [x23, _AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY@GOTPAGEOFF]
	ldr	w20, [x23]
	ldr	w22, [x22]
Lloh50:
	adrp	x8, _BIASEXTR_127_7@GOTPAGE
Lloh51:
	ldr	x8, [x8, _BIASEXTR_127_7@GOTPAGEOFF]
Lloh52:
	ldr	w0, [x8]
	bl	_BIASEXTR_SEL
	orr	w2, w0, w22
	mov	x0, x19
	mov	x1, x20
	bl	_dw_mipi_dsi_phy_write
	ldr	w20, [x23]
	ldr	w21, [x21]
Lloh53:
	adrp	x8, _BANDGAP_96_10@GOTPAGE
Lloh54:
	ldr	x8, [x8, _BANDGAP_96_10@GOTPAGEOFF]
Lloh55:
	ldr	w0, [x8]
	bl	_BANDGAP_SEL
	orr	w2, w0, w21
	mov	x0, x19
	mov	x1, x20
	bl	_dw_mipi_dsi_phy_write
Lloh56:
	adrp	x8, _BANDGAP_AND_BIAS_CONTROL@GOTPAGE
Lloh57:
	ldr	x8, [x8, _BANDGAP_AND_BIAS_CONTROL@GOTPAGEOFF]
Lloh58:
	ldr	w1, [x8]
Lloh59:
	adrp	x8, _POWER_CONTROL@GOTPAGE
Lloh60:
	ldr	x8, [x8, _POWER_CONTROL@GOTPAGEOFF]
Lloh61:
	ldr	w8, [x8]
Lloh62:
	adrp	x9, _INTERNAL_REG_CURRENT@GOTPAGE
Lloh63:
	ldr	x9, [x9, _INTERNAL_REG_CURRENT@GOTPAGEOFF]
Lloh64:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh65:
	adrp	x9, _BIAS_BLOCK_ON@GOTPAGE
Lloh66:
	ldr	x9, [x9, _BIAS_BLOCK_ON@GOTPAGEOFF]
Lloh67:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh68:
	adrp	x9, _BANDGAP_ON@GOTPAGE
Lloh69:
	ldr	x9, [x9, _BANDGAP_ON@GOTPAGEOFF]
Lloh70:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x19
	bl	_dw_mipi_dsi_phy_write
Lloh71:
	adrp	x20, _TERMINATION_RESISTER_CONTROL@GOTPAGE
Lloh72:
	ldr	x20, [x20, _TERMINATION_RESISTER_CONTROL@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh73:
	adrp	x8, _TER_RESISTOR_LOW@GOTPAGE
Lloh74:
	ldr	x8, [x8, _TER_RESISTOR_LOW@GOTPAGEOFF]
Lloh75:
	ldr	w8, [x8]
Lloh76:
	adrp	x9, _TER_CAL_DONE@GOTPAGE
Lloh77:
	ldr	x9, [x9, _TER_CAL_DONE@GOTPAGEOFF]
Lloh78:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh79:
	adrp	x21, _SETRD_MAX@GOTPAGE
Lloh80:
	ldr	x21, [x21, _SETRD_MAX@GOTPAGEOFF]
	ldr	w9, [x21]
	orr	w8, w8, w9
Lloh81:
	adrp	x22, _TER_RESISTORS_ON@GOTPAGE
Lloh82:
	ldr	x22, [x22, _TER_RESISTORS_ON@GOTPAGEOFF]
	ldr	w9, [x22]
	orr	w2, w8, w9
	mov	x0, x19
	bl	_dw_mipi_dsi_phy_write
	ldr	w1, [x20]
Lloh83:
	adrp	x8, _TER_RESISTOR_HIGH@GOTPAGE
Lloh84:
	ldr	x8, [x8, _TER_RESISTOR_HIGH@GOTPAGEOFF]
Lloh85:
	ldr	w8, [x8]
Lloh86:
	adrp	x9, _LEVEL_SHIFTERS_ON@GOTPAGE
Lloh87:
	ldr	x9, [x9, _LEVEL_SHIFTERS_ON@GOTPAGEOFF]
Lloh88:
	ldr	w9, [x9]
	orr	w8, w9, w8
	ldr	w9, [x21]
	orr	w8, w8, w9
Lloh89:
	adrp	x9, _POWER_MANAGE@GOTPAGE
Lloh90:
	ldr	x9, [x9, _POWER_MANAGE@GOTPAGEOFF]
Lloh91:
	ldr	w9, [x9]
	orr	w8, w8, w9
	ldr	w9, [x22]
	orr	w2, w8, w9
	mov	x0, x19
	bl	_dw_mipi_dsi_phy_write
Lloh92:
	adrp	x8, _HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL@GOTPAGE
Lloh93:
	ldr	x8, [x8, _HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL@GOTPAGEOFF]
Lloh94:
	ldr	w20, [x8]
Lloh95:
	adrp	x23, _TLP_PROGRAM_EN@GOTPAGE
Lloh96:
	ldr	x23, [x23, _TLP_PROGRAM_EN@GOTPAGEOFF]
	ldr	w21, [x23]
	mov	x0, x19
	mov	w1, #500
	bl	_ns2bc
	orr	w2, w0, w21
	mov	x0, x19
	mov	x1, x20
	bl	_dw_mipi_dsi_phy_write
Lloh97:
	adrp	x8, _HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL@GOTPAGE
Lloh98:
	ldr	x8, [x8, _HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL@GOTPAGEOFF]
Lloh99:
	ldr	w20, [x8]
Lloh100:
	adrp	x22, _THS_PRE_PROGRAM_EN@GOTPAGE
Lloh101:
	ldr	x22, [x22, _THS_PRE_PROGRAM_EN@GOTPAGEOFF]
	ldr	w21, [x22]
	mov	x0, x19
	mov	w1, #40
	bl	_ns2ui
	orr	w2, w0, w21
	mov	x0, x19
	mov	x1, x20
	bl	_dw_mipi_dsi_phy_write
Lloh102:
	adrp	x8, _HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL@GOTPAGE
Lloh103:
	ldr	x8, [x8, _HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL@GOTPAGEOFF]
Lloh104:
	ldr	w20, [x8]
Lloh105:
	adrp	x24, _THS_ZERO_PROGRAM_EN@GOTPAGE
Lloh106:
	ldr	x24, [x24, _THS_ZERO_PROGRAM_EN@GOTPAGEOFF]
	ldr	w21, [x24]
	mov	x0, x19
	mov	w1, #300
	bl	_ns2bc
	orr	w2, w0, w21
	mov	x0, x19
	mov	x1, x20
	bl	_dw_mipi_dsi_phy_write
Lloh107:
	adrp	x8, _HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL@GOTPAGE
Lloh108:
	ldr	x8, [x8, _HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL@GOTPAGEOFF]
Lloh109:
	ldr	w20, [x8]
	ldr	w21, [x22]
	mov	x0, x19
	mov	w1, #100
	bl	_ns2ui
	orr	w2, w0, w21
	mov	x0, x19
	mov	x1, x20
	bl	_dw_mipi_dsi_phy_write
Lloh110:
	adrp	x8, _HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL@GOTPAGE
Lloh111:
	ldr	x8, [x8, _HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL@GOTPAGEOFF]
Lloh112:
	ldr	w20, [x8]
	mov	w0, #5
	bl	_BIT
	mov	x21, x0
	mov	x0, x19
	mov	w1, #100
	bl	_ns2bc
	orr	w2, w0, w21
	mov	x0, x19
	mov	x1, x20
	bl	_dw_mipi_dsi_phy_write
Lloh113:
	adrp	x8, _HS_TX_CLOCK_LANE_POST_TIME_CONTROL@GOTPAGE
Lloh114:
	ldr	x8, [x8, _HS_TX_CLOCK_LANE_POST_TIME_CONTROL@GOTPAGEOFF]
Lloh115:
	ldr	w20, [x8]
	mov	w0, #5
	bl	_BIT
	mov	x21, x0
	mov	x0, x19
	mov	w1, #60
	bl	_ns2bc
	add	w8, w0, #7
	orr	w2, w8, w21
	mov	x0, x19
	mov	x1, x20
	bl	_dw_mipi_dsi_phy_write
Lloh116:
	adrp	x8, _HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL@GOTPAGE
Lloh117:
	ldr	x8, [x8, _HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL@GOTPAGEOFF]
Lloh118:
	ldr	w20, [x8]
	ldr	w21, [x23]
	mov	x0, x19
	mov	w1, #500
	bl	_ns2bc
	orr	w2, w0, w21
	mov	x0, x19
	mov	x1, x20
	bl	_dw_mipi_dsi_phy_write
Lloh119:
	adrp	x8, _HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL@GOTPAGE
Lloh120:
	ldr	x8, [x8, _HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL@GOTPAGEOFF]
Lloh121:
	ldr	w20, [x8]
	ldr	w21, [x22]
	mov	x0, x19
	mov	w1, #50
	bl	_ns2ui
	add	w8, w0, #20
	orr	w2, w8, w21
	mov	x0, x19
	mov	x1, x20
	bl	_dw_mipi_dsi_phy_write
Lloh122:
	adrp	x8, _HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL@GOTPAGE
Lloh123:
	ldr	x8, [x8, _HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL@GOTPAGEOFF]
Lloh124:
	ldr	w20, [x8]
	ldr	w21, [x24]
	mov	x0, x19
	mov	w1, #140
	bl	_ns2bc
	add	w8, w0, #2
	orr	w2, w8, w21
	mov	x0, x19
	mov	x1, x20
	bl	_dw_mipi_dsi_phy_write
Lloh125:
	adrp	x8, _HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL@GOTPAGE
Lloh126:
	ldr	x8, [x8, _HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL@GOTPAGEOFF]
Lloh127:
	ldr	w20, [x8]
	ldr	w21, [x22]
	mov	x0, x19
	mov	w1, #60
	bl	_ns2ui
	add	w8, w0, #8
	orr	w2, w8, w21
	mov	x0, x19
	mov	x1, x20
	bl	_dw_mipi_dsi_phy_write
Lloh128:
	adrp	x8, _HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL@GOTPAGE
Lloh129:
	ldr	x8, [x8, _HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL@GOTPAGEOFF]
Lloh130:
	ldr	w20, [x8]
	mov	w0, #5
	bl	_BIT
	mov	x21, x0
	mov	x0, x19
	mov	w1, #100
	bl	_ns2bc
	orr	w2, w0, w21
	mov	x0, x19
	mov	x1, x20
	bl	_dw_mipi_dsi_phy_write
	ldr	w0, [x19, #4]
	bl	_clk_disable_unprepare
	mov	w20, #0
LBB0_5:
	mov	x0, x20
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh128, Lloh129, Lloh130
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGot	Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGot	Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGot	Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGot	Lloh81, Lloh82
	.loh AdrpLdrGot	Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGot	Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGot	Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh28
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh20
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"failed to get parameter for %dmbps clock\n"

l_.str.1:                               ; @.str.1
	.asciz	"Failed to enable phy_cfg_clk\n"

	.comm	_PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,4,2 ; @PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL
	.comm	_BYPASS_VCO_RANGE,4,2           ; @BYPASS_VCO_RANGE
	.comm	_VCO_IN_CAP_CON_LOW,4,2         ; @VCO_IN_CAP_CON_LOW
	.comm	_REF_BIAS_CUR_SEL,4,2           ; @REF_BIAS_CUR_SEL
	.comm	_PLL_CP_CONTROL_PLL_LOCK_BYPASS,4,2 ; @PLL_CP_CONTROL_PLL_LOCK_BYPASS
	.comm	_dppa_map,8,3                   ; @dppa_map
	.comm	_PLL_LPF_AND_CP_CONTROL,4,2     ; @PLL_LPF_AND_CP_CONTROL
	.comm	_CP_PROGRAM_EN,4,2              ; @CP_PROGRAM_EN
	.comm	_LPF_PROGRAM_EN,4,2             ; @LPF_PROGRAM_EN
	.comm	_HS_RX_CONTROL_OF_LANE_0,4,2    ; @HS_RX_CONTROL_OF_LANE_0
	.comm	_PLL_INPUT_DIVIDER_RATIO,4,2    ; @PLL_INPUT_DIVIDER_RATIO
	.comm	_PLL_LOOP_DIVIDER_RATIO,4,2     ; @PLL_LOOP_DIVIDER_RATIO
	.comm	_LOW_PROGRAM_EN,4,2             ; @LOW_PROGRAM_EN
	.comm	_PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,4,2 ; @PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL
	.comm	_PLL_LOOP_DIV_EN,4,2            ; @PLL_LOOP_DIV_EN
	.comm	_PLL_INPUT_DIV_EN,4,2           ; @PLL_INPUT_DIV_EN
	.comm	_HIGH_PROGRAM_EN,4,2            ; @HIGH_PROGRAM_EN
	.comm	_AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,4,2 ; @AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY
	.comm	_BIASEXTR_127_7,4,2             ; @BIASEXTR_127_7
	.comm	_BANDGAP_96_10,4,2              ; @BANDGAP_96_10
	.comm	_BANDGAP_AND_BIAS_CONTROL,4,2   ; @BANDGAP_AND_BIAS_CONTROL
	.comm	_POWER_CONTROL,4,2              ; @POWER_CONTROL
	.comm	_INTERNAL_REG_CURRENT,4,2       ; @INTERNAL_REG_CURRENT
	.comm	_BIAS_BLOCK_ON,4,2              ; @BIAS_BLOCK_ON
	.comm	_BANDGAP_ON,4,2                 ; @BANDGAP_ON
	.comm	_TERMINATION_RESISTER_CONTROL,4,2 ; @TERMINATION_RESISTER_CONTROL
	.comm	_TER_RESISTOR_LOW,4,2           ; @TER_RESISTOR_LOW
	.comm	_TER_CAL_DONE,4,2               ; @TER_CAL_DONE
	.comm	_SETRD_MAX,4,2                  ; @SETRD_MAX
	.comm	_TER_RESISTORS_ON,4,2           ; @TER_RESISTORS_ON
	.comm	_TER_RESISTOR_HIGH,4,2          ; @TER_RESISTOR_HIGH
	.comm	_LEVEL_SHIFTERS_ON,4,2          ; @LEVEL_SHIFTERS_ON
	.comm	_POWER_MANAGE,4,2               ; @POWER_MANAGE
	.comm	_HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,4,2 ; @HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL
	.comm	_TLP_PROGRAM_EN,4,2             ; @TLP_PROGRAM_EN
	.comm	_HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,4,2 ; @HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL
	.comm	_THS_PRE_PROGRAM_EN,4,2         ; @THS_PRE_PROGRAM_EN
	.comm	_HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,4,2 ; @HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL
	.comm	_THS_ZERO_PROGRAM_EN,4,2        ; @THS_ZERO_PROGRAM_EN
	.comm	_HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,4,2 ; @HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL
	.comm	_HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,4,2 ; @HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL
	.comm	_HS_TX_CLOCK_LANE_POST_TIME_CONTROL,4,2 ; @HS_TX_CLOCK_LANE_POST_TIME_CONTROL
	.comm	_HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,4,2 ; @HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL
	.comm	_HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,4,2 ; @HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL
	.comm	_HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,4,2 ; @HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL
	.comm	_HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,4,2 ; @HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL
	.comm	_HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,4,2 ; @HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL
	.no_dead_strip	_dw_mipi_dsi_phy_init
.subsections_via_symbols
