	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mmc35240_init
_mmc35240_init:                         ## @mmc35240_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -32(%rbp)
	movl	24(%rdi), %edi
	movq	_MMC35240_REG_ID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-68(%rbp), %rdx
	callq	_regmap_read
	movq	32(%r14), %rdi
	testl	%eax, %eax
	js	LBB0_6
## %bb.1:
	movl	-68(%rbp), %edx
	leaq	L_.str.1(%rip), %rsi
	callq	_dev_dbg
	movq	%r14, %rdi
	movl	$1, %esi
	callq	_mmc35240_hw_set
	testl	%eax, %eax
	js	LBB0_10
## %bb.2:
	movq	_MMC35240_WAIT_SET_RESET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	leaq	1(%rdi), %rsi
	callq	_usleep_range
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_mmc35240_hw_set
	testl	%eax, %eax
	js	LBB0_10
## %bb.3:
	movl	(%r14), %eax
	movl	24(%r14), %edi
	movq	_MMC35240_REG_CTRL1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_MMC35240_CTRL1_BW_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_MMC35240_CTRL1_BW_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	movl	%eax, %ecx
	callq	_regmap_update_bits
	testl	%eax, %eax
	js	LBB0_10
## %bb.4:
	movl	24(%r14), %edi
	movq	_MMC35240_OTP_START_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-64(%rbp), %rdx
	movl	$24, %ecx
	callq	_regmap_bulk_read
	testl	%eax, %eax
	js	LBB0_10
## %bb.5:
	movl	-60(%rbp), %eax
	movl	-56(%rbp), %edi
	shll	$4, %eax
	andl	$48, %eax
	sarl	$4, %edi
	orl	%eax, %edi
	callq	_MMC35240_OTP_CONVERT_Y
	movl	%eax, %r15d
	movl	-52(%rbp), %edi
	andl	$63, %edi
	callq	_MMC35240_OTP_CONVERT_Z
	movl	%eax, %ebx
	movl	$1, %edi
	callq	_MMC35240_X_COEFF
	movq	16(%r14), %rcx
	movl	%eax, (%rcx)
	movl	%r15d, %edi
	callq	_MMC35240_Y_COEFF
	movq	16(%r14), %rcx
	movl	%eax, 4(%rcx)
	movl	%ebx, %edi
	callq	_MMC35240_Z_COEFF
	movq	16(%r14), %rcx
	movl	%eax, 8(%rcx)
	movq	8(%r14), %rax
	movabsq	$4294967296001, %rcx            ## imm = 0x3E800000001
	movq	%rcx, (%rax)
	movl	$10000, 8(%rax)                 ## imm = 0x2710
	xorl	%ebx, %ebx
	jmp	LBB0_11
LBB0_10:
	movl	%eax, %ebx
	jmp	LBB0_11
LBB0_6:
	movl	%eax, %ebx
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
LBB0_11:
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	cmpq	-32(%rbp), %rax
	jne	LBB0_13
## %bb.12:
	movl	%ebx, %eax
	addq	$56, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_13:
	callq	___stack_chk_fail
	.cfi_endproc
                                        ## -- End function
	.comm	_MMC35240_REG_ID,4,2            ## @MMC35240_REG_ID
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Error reading product id\n"

L_.str.1:                               ## @.str.1
	.asciz	"MMC35240 chip id %x\n"

	.comm	_MMC35240_WAIT_SET_RESET,8,3    ## @MMC35240_WAIT_SET_RESET
	.comm	_MMC35240_REG_CTRL1,4,2         ## @MMC35240_REG_CTRL1
	.comm	_MMC35240_CTRL1_BW_MASK,4,2     ## @MMC35240_CTRL1_BW_MASK
	.comm	_MMC35240_CTRL1_BW_SHIFT,4,2    ## @MMC35240_CTRL1_BW_SHIFT
	.comm	_MMC35240_OTP_START_ADDR,4,2    ## @MMC35240_OTP_START_ADDR
	.no_dead_strip	_mmc35240_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3                               ; -- Begin function mmc35240_init
lCPI0_0:
	.long	1                               ; 0x1
	.long	1000                            ; 0x3e8
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	2
_mmc35240_init:                         ; @mmc35240_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, ___stack_chk_guard@GOTPAGE
Lloh1:
	ldr	x8, [x8, ___stack_chk_guard@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	str	x8, [sp, #40]
	ldr	w0, [x0, #24]
Lloh3:
	adrp	x8, _MMC35240_REG_ID@GOTPAGE
Lloh4:
	ldr	x8, [x8, _MMC35240_REG_ID@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	add	x2, sp, #12
	bl	_regmap_read
	mov	x20, x0
	ldr	x0, [x19, #32]
	tbnz	w20, #31, LBB0_7
; %bb.1:
	ldr	w2, [sp, #12]
Lloh6:
	adrp	x1, l_.str.1@PAGE
Lloh7:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_dbg
	mov	x0, x19
	mov	w1, #1
	bl	_mmc35240_hw_set
	tbnz	w0, #31, LBB0_6
; %bb.2:
Lloh8:
	adrp	x8, _MMC35240_WAIT_SET_RESET@GOTPAGE
Lloh9:
	ldr	x8, [x8, _MMC35240_WAIT_SET_RESET@GOTPAGEOFF]
Lloh10:
	ldr	x0, [x8]
	add	x1, x0, #1
	bl	_usleep_range
	mov	x0, x19
	mov	w1, #0
	bl	_mmc35240_hw_set
	tbnz	w0, #31, LBB0_6
; %bb.3:
	ldr	w0, [x19, #24]
Lloh11:
	adrp	x8, _MMC35240_REG_CTRL1@GOTPAGE
Lloh12:
	ldr	x8, [x8, _MMC35240_REG_CTRL1@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
Lloh14:
	adrp	x8, _MMC35240_CTRL1_BW_MASK@GOTPAGE
Lloh15:
	ldr	x8, [x8, _MMC35240_CTRL1_BW_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	ldr	w8, [x19]
Lloh17:
	adrp	x9, _MMC35240_CTRL1_BW_SHIFT@GOTPAGE
Lloh18:
	ldr	x9, [x9, _MMC35240_CTRL1_BW_SHIFT@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	lsl	w3, w8, w9
	bl	_regmap_update_bits
	tbnz	w0, #31, LBB0_6
; %bb.4:
	ldr	w0, [x19, #24]
Lloh20:
	adrp	x8, _MMC35240_OTP_START_ADDR@GOTPAGE
Lloh21:
	ldr	x8, [x8, _MMC35240_OTP_START_ADDR@GOTPAGEOFF]
Lloh22:
	ldr	w1, [x8]
	add	x2, sp, #16
	mov	w3, #24
	bl	_regmap_bulk_read
	tbnz	w0, #31, LBB0_6
; %bb.5:
	ldp	w8, w9, [sp, #20]
	ubfiz	w8, w8, #4, #2
	orr	w0, w8, w9, asr #4
	bl	_MMC35240_OTP_CONVERT_Y
	mov	x20, x0
	ldr	w8, [sp, #28]
	and	w0, w8, #0x3f
	bl	_MMC35240_OTP_CONVERT_Z
	mov	x21, x0
	mov	w0, #1
	bl	_MMC35240_X_COEFF
	ldr	x8, [x19, #16]
	str	w0, [x8]
	mov	x0, x20
	bl	_MMC35240_Y_COEFF
	ldr	x8, [x19, #16]
	str	w0, [x8, #4]
	mov	x0, x21
	bl	_MMC35240_Z_COEFF
	mov	w20, #0
	ldr	x8, [x19, #16]
	str	w0, [x8, #8]
	ldr	x8, [x19, #8]
Lloh23:
	adrp	x9, lCPI0_0@PAGE
Lloh24:
	ldr	d0, [x9, lCPI0_0@PAGEOFF]
	str	d0, [x8]
	mov	w9, #10000
	str	w9, [x8, #8]
	b	LBB0_8
LBB0_6:
	mov	x20, x0
	b	LBB0_8
LBB0_7:
Lloh25:
	adrp	x1, l_.str@PAGE
Lloh26:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
LBB0_8:
	ldr	x8, [sp, #40]
Lloh27:
	adrp	x9, ___stack_chk_guard@GOTPAGE
Lloh28:
	ldr	x9, [x9, ___stack_chk_guard@GOTPAGEOFF]
Lloh29:
	ldr	x9, [x9]
	cmp	x9, x8
	b.ne	LBB0_10
; %bb.9:
	mov	x0, x20
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_10:
	bl	___stack_chk_fail
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdr	Lloh23, Lloh24
	.loh AdrpAdd	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.cfi_endproc
                                        ; -- End function
	.comm	_MMC35240_REG_ID,4,2            ; @MMC35240_REG_ID
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Error reading product id\n"

l_.str.1:                               ; @.str.1
	.asciz	"MMC35240 chip id %x\n"

	.comm	_MMC35240_WAIT_SET_RESET,8,3    ; @MMC35240_WAIT_SET_RESET
	.comm	_MMC35240_REG_CTRL1,4,2         ; @MMC35240_REG_CTRL1
	.comm	_MMC35240_CTRL1_BW_MASK,4,2     ; @MMC35240_CTRL1_BW_MASK
	.comm	_MMC35240_CTRL1_BW_SHIFT,4,2    ; @MMC35240_CTRL1_BW_SHIFT
	.comm	_MMC35240_OTP_START_ADDR,4,2    ; @MMC35240_OTP_START_ADDR
	.no_dead_strip	_mmc35240_init
.subsections_via_symbols
