	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function valleyview_crtc_enable
_valleyview_crtc_enable:                ## @valleyview_crtc_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, -72(%rbp)                 ## 8-byte Spill
	movq	%rdi, %rbx
	movq	(%rdi), %r14
	movq	(%r14), %rdi
	callq	_to_i915
	movq	%rax, %r15
	movq	%r14, %rdi
	callq	_to_intel_crtc
	movq	%rax, %r13
	movl	(%rax), %r12d
	movl	4(%rax), %edi
	callq	_WARN_ON
	testq	%rax, %rax
	je	LBB0_1
## %bb.10:
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_1:
	movl	%r12d, -44(%rbp)                ## 4-byte Spill
	movq	%r14, -56(%rbp)                 ## 8-byte Spill
	movq	%r15, -64(%rbp)                 ## 8-byte Spill
	movq	%rbx, %rdi
	callq	_intel_crtc_has_dp_encoder
	testq	%rax, %rax
	je	LBB0_3
## %bb.2:
	movq	_M1_N1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_intel_dp_set_m_n
LBB0_3:
	movq	%rbx, %rdi
	callq	_intel_set_pipe_timings
	movq	%rbx, %rdi
	callq	_intel_set_pipe_src_size
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	callq	_IS_CHERRYVIEW
	testq	%rax, %rax
	movl	-44(%rbp), %r14d                ## 4-byte Reload
	movq	%r13, %r12
	je	LBB0_6
## %bb.4:
	movq	_PIPE_B@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r14d
	jne	LBB0_6
## %bb.5:
	movl	%r14d, %edi
	callq	_CHV_BLEND
	movq	_CHV_BLEND_LEGACY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_I915_WRITE
	movl	%r14d, %edi
	callq	_CHV_CANVAS
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_I915_WRITE
LBB0_6:
	movq	%rbx, %rdi
	callq	_i9xx_set_pipeconf
	movl	$1, 4(%r12)
	movq	-64(%rbp), %r13                 ## 8-byte Reload
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	$1, %edx
	callq	_intel_set_cpu_fifo_underrun_reporting
	movq	%r12, %rdi
	movq	%rbx, %rsi
	movq	-72(%rbp), %r14                 ## 8-byte Reload
	movq	%r14, %rdx
	callq	_intel_encoders_pre_pll_enable
	movq	%r13, %rdi
	callq	_IS_CHERRYVIEW
	movq	%r12, %rdi
	movq	%rbx, %rsi
	testq	%rax, %rax
	je	LBB0_8
## %bb.7:
	callq	_chv_prepare_pll
	movq	%r12, %rdi
	movq	%rbx, %rsi
	callq	_chv_enable_pll
	jmp	LBB0_9
LBB0_8:
	callq	_vlv_prepare_pll
	movq	%r12, %rdi
	movq	%rbx, %rsi
	callq	_vlv_enable_pll
LBB0_9:
	movq	-56(%rbp), %r15                 ## 8-byte Reload
	movq	%r12, %rdi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	callq	_intel_encoders_pre_enable
	movq	%rbx, %rdi
	callq	_i9xx_pfit_enable
	movq	%rbx, %rdi
	callq	_intel_color_load_luts
	movq	%rbx, %rdi
	callq	_intel_color_commit
	movq	%rbx, %rdi
	callq	_intel_disable_primary_plane
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	*(%r13)
	movq	%rbx, %rdi
	callq	_intel_enable_pipe
	movq	%r15, %rdi
	callq	_assert_vblank_disabled
	movq	%rbx, %rdi
	callq	_intel_crtc_vblank_on
	movq	%r12, %rdi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_intel_encoders_enable          ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_M1_N1,4,2                      ## @M1_N1
	.comm	_PIPE_B,4,2                     ## @PIPE_B
	.comm	_CHV_BLEND_LEGACY,4,2           ## @CHV_BLEND_LEGACY
	.no_dead_strip	_valleyview_crtc_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function valleyview_crtc_enable
_valleyview_crtc_enable:                ; @valleyview_crtc_enable
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x1
	mov	x20, x0
	ldr	x21, [x0]
	ldr	x0, [x21]
	bl	_to_i915
	mov	x23, x0
	mov	x0, x21
	bl	_to_intel_crtc
	mov	x22, x0
	ldp	w24, w0, [x0]
	bl	_WARN_ON
	cbz	x0, LBB0_2
; %bb.1:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_2:
	mov	x0, x20
	bl	_intel_crtc_has_dp_encoder
	cbz	x0, LBB0_4
; %bb.3:
Lloh0:
	adrp	x8, _M1_N1@GOTPAGE
Lloh1:
	ldr	x8, [x8, _M1_N1@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_intel_dp_set_m_n
LBB0_4:
	mov	x0, x20
	bl	_intel_set_pipe_timings
	mov	x0, x20
	bl	_intel_set_pipe_src_size
	mov	x0, x23
	bl	_IS_CHERRYVIEW
Lloh3:
	adrp	x8, _PIPE_B@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PIPE_B@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	cmp	x0, #0
	ccmp	w24, w8, #0, ne
	b.ne	LBB0_6
; %bb.5:
	mov	x0, x24
	bl	_CHV_BLEND
Lloh6:
	adrp	x8, _CHV_BLEND_LEGACY@GOTPAGE
Lloh7:
	ldr	x8, [x8, _CHV_BLEND_LEGACY@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	bl	_I915_WRITE
	mov	x0, x24
	bl	_CHV_CANVAS
	mov	w1, #0
	bl	_I915_WRITE
LBB0_6:
	mov	x0, x20
	bl	_i9xx_set_pipeconf
	mov	w8, #1
	str	w8, [x22, #4]
	mov	x0, x23
	mov	x1, x24
	mov	w2, #1
	bl	_intel_set_cpu_fifo_underrun_reporting
	mov	x0, x22
	mov	x1, x20
	mov	x2, x19
	bl	_intel_encoders_pre_pll_enable
	mov	x0, x23
	bl	_IS_CHERRYVIEW
	cbz	x0, LBB0_8
; %bb.7:
	mov	x0, x22
	mov	x1, x20
	bl	_chv_prepare_pll
	mov	x0, x22
	mov	x1, x20
	bl	_chv_enable_pll
	b	LBB0_9
LBB0_8:
	mov	x0, x22
	mov	x1, x20
	bl	_vlv_prepare_pll
	mov	x0, x22
	mov	x1, x20
	bl	_vlv_enable_pll
LBB0_9:
	mov	x0, x22
	mov	x1, x20
	mov	x2, x19
	bl	_intel_encoders_pre_enable
	mov	x0, x20
	bl	_i9xx_pfit_enable
	mov	x0, x20
	bl	_intel_color_load_luts
	mov	x0, x20
	bl	_intel_color_commit
	mov	x0, x20
	bl	_intel_disable_primary_plane
	ldr	x8, [x23]
	mov	x0, x19
	mov	x1, x20
	blr	x8
	mov	x0, x20
	bl	_intel_enable_pipe
	mov	x0, x21
	bl	_assert_vblank_disabled
	mov	x0, x20
	bl	_intel_crtc_vblank_on
	mov	x0, x22
	mov	x1, x20
	mov	x2, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_intel_encoders_enable
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_M1_N1,4,2                      ; @M1_N1
	.comm	_PIPE_B,4,2                     ; @PIPE_B
	.comm	_CHV_BLEND_LEGACY,4,2           ; @CHV_BLEND_LEGACY
	.no_dead_strip	_valleyview_crtc_enable
.subsections_via_symbols
