	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function sun8i_hdmi_phy_init_h3
_sun8i_hdmi_phy_init_h3:                ## @sun8i_hdmi_phy_init_h3
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	callq	_sun8i_hdmi_phy_unlock
	movl	4(%rbx), %edi
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_REG@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	movl	4(%rbx), %edi
	movl	(%r14), %esi
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_ENBI@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	$5, %edi
	callq	_udelay
	movl	4(%rbx), %edi
	movl	(%r14), %esi
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	4(%rbx), %edi
	movl	(%r14), %esi
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_ENVBS@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	$10, %edi
	movl	$20, %esi
	callq	_usleep_range
	movl	4(%rbx), %edi
	movl	(%r14), %esi
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_LDOEN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	$5, %edi
	callq	_udelay
	movl	4(%rbx), %edi
	movl	(%r14), %esi
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_CKEN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	$40, %edi
	movl	$100, %esi
	callq	_usleep_range
	movl	4(%rbx), %edi
	movl	(%r14), %esi
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	$100, %edi
	movl	$200, %esi
	callq	_usleep_range
	movl	4(%rbx), %edi
	movl	(%r14), %esi
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	4(%rbx), %edi
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0@GOTPCREL(%rip), %rax
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movl	(%r14), %esi
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	4(%rbx), %edi
	movq	_SUN8I_HDMI_PHY_ANA_STS_REG@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	xorl	%ecx, %ecx
	movl	$100, %r8d
	movl	$2000, %r9d                     ## imm = 0x7D0
	callq	_regmap_read_poll_timeout
	movl	4(%rbx), %edi
	movl	(%r14), %esi
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0@GOTPCREL(%rip), %rax
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movl	4(%rbx), %edi
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movl	(%r14), %esi
	movq	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	4(%rbx), %edi
	movq	_SUN8I_HDMI_PHY_ANA_CFG3_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SUN8I_HDMI_PHY_ANA_CFG3_SCLEN@GOTPCREL(%rip), %rax
	movq	_SUN8I_HDMI_PHY_ANA_CFG3_SDAEN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	4(%rbx), %edi
	movq	_SUN8I_HDMI_PHY_PLL_CFG1_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	4(%rbx), %edi
	movq	_SUN8I_HDMI_PHY_CEC_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	movl	4(%rbx), %edi
	movl	(%r15), %esi
	leaq	-28(%rbp), %rdx
	callq	_regmap_read
	movq	_SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	-28(%rbp), %eax
	shrl	$2, %eax
	movl	%eax, (%rbx)
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_REG,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_REG
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENBI,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_ENBI
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENVBS,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_ENVBS
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_LDOEN,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_LDOEN
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_CKEN,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_CKEN
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2
	.comm	_SUN8I_HDMI_PHY_ANA_STS_REG,4,2 ## @SUN8I_HDMI_PHY_ANA_STS_REG
	.comm	_SUN8I_HDMI_PHY_ANA_STS_RCALEND2D,4,2 ## @SUN8I_HDMI_PHY_ANA_STS_RCALEND2D
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK
	.comm	_SUN8I_HDMI_PHY_ANA_CFG3_REG,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG3_REG
	.comm	_SUN8I_HDMI_PHY_ANA_CFG3_SCLEN,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG3_SCLEN
	.comm	_SUN8I_HDMI_PHY_ANA_CFG3_SDAEN,4,2 ## @SUN8I_HDMI_PHY_ANA_CFG3_SDAEN
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_REG,4,2 ## @SUN8I_HDMI_PHY_PLL_CFG1_REG
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,4,2 ## @SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK
	.comm	_SUN8I_HDMI_PHY_CEC_REG,4,2     ## @SUN8I_HDMI_PHY_CEC_REG
	.comm	_SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK,4,2 ## @SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK
	.no_dead_strip	_sun8i_hdmi_phy_init_h3
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function sun8i_hdmi_phy_init_h3
_sun8i_hdmi_phy_init_h3:                ; @sun8i_hdmi_phy_init_h3
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	bl	_sun8i_hdmi_phy_unlock
	ldr	w0, [x19, #4]
Lloh0:
	adrp	x20, _SUN8I_HDMI_PHY_ANA_CFG1_REG@GOTPAGE
Lloh1:
	ldr	x20, [x20, _SUN8I_HDMI_PHY_ANA_CFG1_REG@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	w2, #0
	bl	_regmap_write
	ldr	w0, [x19, #4]
	ldr	w1, [x20]
Lloh2:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG1_ENBI@GOTPAGE
Lloh3:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG1_ENBI@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	mov	w0, #5
	bl	_udelay
	ldr	w0, [x19, #4]
	ldr	w1, [x20]
Lloh5:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN@GOTPAGE
Lloh6:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19, #4]
	ldr	w1, [x20]
Lloh8:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG1_ENVBS@GOTPAGE
Lloh9:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG1_ENVBS@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	mov	w0, #10
	mov	w1, #20
	bl	_usleep_range
	ldr	w0, [x19, #4]
	ldr	w1, [x20]
Lloh11:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG1_LDOEN@GOTPAGE
Lloh12:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG1_LDOEN@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	mov	w0, #5
	bl	_udelay
	ldr	w0, [x19, #4]
	ldr	w1, [x20]
Lloh14:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG1_CKEN@GOTPAGE
Lloh15:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG1_CKEN@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	mov	w0, #40
	mov	w1, #100
	bl	_usleep_range
	ldr	w0, [x19, #4]
	ldr	w1, [x20]
Lloh17:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL@GOTPAGE
Lloh18:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL@GOTPAGEOFF]
Lloh19:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	mov	w0, #100
	mov	w1, #200
	bl	_usleep_range
	ldr	w0, [x19, #4]
	ldr	w1, [x20]
Lloh20:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG@GOTPAGE
Lloh21:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19, #4]
	ldr	w1, [x20]
Lloh23:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0@GOTPAGE
Lloh24:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
Lloh26:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1@GOTPAGE
Lloh27:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1@GOTPAGEOFF]
Lloh28:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh29:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2@GOTPAGE
Lloh30:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2@GOTPAGEOFF]
Lloh31:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19, #4]
Lloh32:
	adrp	x21, _SUN8I_HDMI_PHY_ANA_STS_REG@GOTPAGE
Lloh33:
	ldr	x21, [x21, _SUN8I_HDMI_PHY_ANA_STS_REG@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	w3, #0
	mov	w4, #100
	mov	w5, #2000
	bl	_regmap_read_poll_timeout
	ldr	w0, [x19, #4]
	ldr	w1, [x20]
Lloh34:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK@GOTPAGE
Lloh35:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK@GOTPAGEOFF]
Lloh36:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19, #4]
	ldr	w1, [x20]
Lloh37:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0@GOTPAGE
Lloh38:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
Lloh40:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1@GOTPAGE
Lloh41:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1@GOTPAGEOFF]
Lloh42:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh43:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2@GOTPAGE
Lloh44:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2@GOTPAGEOFF]
Lloh45:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh46:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK@GOTPAGE
Lloh47:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK@GOTPAGEOFF]
Lloh48:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19, #4]
Lloh49:
	adrp	x8, _SUN8I_HDMI_PHY_ANA_CFG3_REG@GOTPAGE
Lloh50:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_ANA_CFG3_REG@GOTPAGEOFF]
Lloh51:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG3_SCLEN@GOTPAGE
Lloh52:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG3_SCLEN@GOTPAGEOFF]
Lloh53:
	ldr	w1, [x8]
Lloh54:
	ldr	w8, [x9]
Lloh55:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_CFG3_SDAEN@GOTPAGE
Lloh56:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_CFG3_SDAEN@GOTPAGEOFF]
Lloh57:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19, #4]
Lloh58:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG1_REG@GOTPAGE
Lloh59:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG1_REG@GOTPAGEOFF]
Lloh60:
	ldr	w1, [x8]
Lloh61:
	adrp	x8, _SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK@GOTPAGE
Lloh62:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK@GOTPAGEOFF]
Lloh63:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_regmap_update_bits
	ldr	w0, [x19, #4]
Lloh64:
	adrp	x8, _SUN8I_HDMI_PHY_CEC_REG@GOTPAGE
Lloh65:
	ldr	x8, [x8, _SUN8I_HDMI_PHY_CEC_REG@GOTPAGEOFF]
Lloh66:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_regmap_write
	ldr	w0, [x19, #4]
	ldr	w1, [x21]
	add	x2, sp, #12
	bl	_regmap_read
	ldr	w8, [sp, #12]
Lloh67:
	adrp	x9, _SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK@GOTPAGE
Lloh68:
	ldr	x9, [x9, _SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK@GOTPAGEOFF]
Lloh69:
	ldr	w9, [x9]
	and	w8, w9, w8
	lsr	w8, w8, #2
	str	w8, [x19]
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh53
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_REG,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_REG
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENBI,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_ENBI
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENVBS,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_ENVBS
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_LDOEN,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_LDOEN
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_CKEN,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_CKEN
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2
	.comm	_SUN8I_HDMI_PHY_ANA_STS_REG,4,2 ; @SUN8I_HDMI_PHY_ANA_STS_REG
	.comm	_SUN8I_HDMI_PHY_ANA_STS_RCALEND2D,4,2 ; @SUN8I_HDMI_PHY_ANA_STS_RCALEND2D
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2
	.comm	_SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK
	.comm	_SUN8I_HDMI_PHY_ANA_CFG3_REG,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG3_REG
	.comm	_SUN8I_HDMI_PHY_ANA_CFG3_SCLEN,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG3_SCLEN
	.comm	_SUN8I_HDMI_PHY_ANA_CFG3_SDAEN,4,2 ; @SUN8I_HDMI_PHY_ANA_CFG3_SDAEN
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_REG,4,2 ; @SUN8I_HDMI_PHY_PLL_CFG1_REG
	.comm	_SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,4,2 ; @SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK
	.comm	_SUN8I_HDMI_PHY_CEC_REG,4,2     ; @SUN8I_HDMI_PHY_CEC_REG
	.comm	_SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK,4,2 ; @SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK
	.no_dead_strip	_sun8i_hdmi_phy_init_h3
.subsections_via_symbols
