	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dce_v11_0_init_golden_registers
_dce_v11_0_init_golden_registers:       ## @dce_v11_0_init_golden_registers
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	(%rdi), %ecx
	addl	$-128, %ecx
	cmpl	$5, %ecx
	ja	LBB0_6
## %bb.1:
	movq	%rdi, %r15
	movq	_stoney_golden_settings_a11@GOTPCREL(%rip), %rax
	leaq	LJTI0_0(%rip), %rdx
	movslq	(%rdx,%rcx,4), %rcx
	addq	%rdx, %rcx
	jmpq	*%rcx
LBB0_4:
	movq	_polaris10_golden_settings_a11@GOTPCREL(%rip), %rax
	jmp	LBB0_5
LBB0_3:
	movq	_polaris11_golden_settings_a11@GOTPCREL(%rip), %rax
	jmp	LBB0_5
LBB0_6:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	movq	_cz_mgcg_cgcg_init@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%r14d, %edi
	callq	_ARRAY_SIZE
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_amdgpu_device_program_register_sequence
	movq	_cz_golden_settings_a11@GOTPCREL(%rip), %rax
LBB0_5:
	movl	(%rax), %ebx
	movl	%ebx, %edi
	callq	_ARRAY_SIZE
	movq	%r15, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_device_program_register_sequence ## TAILCALL
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_4, LBB0_4-LJTI0_0
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_3, LBB0_3-LJTI0_0
.set L0_0_set_2, LBB0_2-LJTI0_0
LJTI0_0:
	.long	L0_0_set_4
	.long	L0_0_set_5
	.long	L0_0_set_3
	.long	L0_0_set_3
	.long	L0_0_set_4
	.long	L0_0_set_2
	.end_data_region
                                        ## -- End function
	.comm	_cz_mgcg_cgcg_init,4,2          ## @cz_mgcg_cgcg_init
	.comm	_cz_golden_settings_a11,4,2     ## @cz_golden_settings_a11
	.comm	_stoney_golden_settings_a11,4,2 ## @stoney_golden_settings_a11
	.comm	_polaris11_golden_settings_a11,4,2 ## @polaris11_golden_settings_a11
	.comm	_polaris10_golden_settings_a11,4,2 ## @polaris10_golden_settings_a11
	.no_dead_strip	_dce_v11_0_init_golden_registers
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dce_v11_0_init_golden_registers
_dce_v11_0_init_golden_registers:       ; @dce_v11_0_init_golden_registers
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	w8, [x0]
	sub	w9, w8, #128
	cmp	w9, #5
	b.hi	LBB0_4
; %bb.1:
	mov	x19, x0
Lloh0:
	adrp	x8, _stoney_golden_settings_a11@GOTPAGE
Lloh1:
	ldr	x8, [x8, _stoney_golden_settings_a11@GOTPAGEOFF]
Lloh2:
	adrp	x10, lJTI0_0@PAGE
Lloh3:
	add	x10, x10, lJTI0_0@PAGEOFF
	adr	x11, LBB0_2
	ldrb	w12, [x10, x9]
	add	x11, x11, x12, lsl #2
	br	x11
LBB0_2:
Lloh4:
	adrp	x8, _polaris10_golden_settings_a11@GOTPAGE
Lloh5:
	ldr	x8, [x8, _polaris10_golden_settings_a11@GOTPAGEOFF]
	b	LBB0_6
LBB0_3:
Lloh6:
	adrp	x8, _polaris11_golden_settings_a11@GOTPAGE
Lloh7:
	ldr	x8, [x8, _polaris11_golden_settings_a11@GOTPAGEOFF]
	b	LBB0_6
LBB0_4:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_5:
Lloh8:
	adrp	x8, _cz_mgcg_cgcg_init@GOTPAGE
Lloh9:
	ldr	x8, [x8, _cz_mgcg_cgcg_init@GOTPAGEOFF]
Lloh10:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_device_program_register_sequence
Lloh11:
	adrp	x8, _cz_golden_settings_a11@GOTPAGE
Lloh12:
	ldr	x8, [x8, _cz_golden_settings_a11@GOTPAGEOFF]
LBB0_6:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_amdgpu_device_program_register_sequence
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_6-LBB0_2)>>2
	.byte	(LBB0_3-LBB0_2)>>2
	.byte	(LBB0_3-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
                                        ; -- End function
	.comm	_cz_mgcg_cgcg_init,4,2          ; @cz_mgcg_cgcg_init
	.comm	_cz_golden_settings_a11,4,2     ; @cz_golden_settings_a11
	.comm	_stoney_golden_settings_a11,4,2 ; @stoney_golden_settings_a11
	.comm	_polaris11_golden_settings_a11,4,2 ; @polaris11_golden_settings_a11
	.comm	_polaris10_golden_settings_a11,4,2 ; @polaris10_golden_settings_a11
	.no_dead_strip	_dce_v11_0_init_golden_registers
.subsections_via_symbols
