	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function r100_get_accessible_vram
_r100_get_accessible_vram:              ## @r100_get_accessible_vram
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	subq	$16, %rsp
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	movq	_RADEON_CONFIG_APER_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r14d
	movq	(%rbx), %rax
	movq	_CHIP_RV280@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_2
## %bb.1:
	movq	_CHIP_RV350@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_2
## %bb.3:
	movl	8(%rbx), %edi
	leaq	-20(%rbp), %rdx
	movl	$14, %esi
	callq	_pci_read_config_byte
	testb	$-128, -20(%rbp)
	jne	LBB0_4
## %bb.5:
	movq	_RADEON_HOST_PATH_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_RADEON_HDP_APER_CNTL@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	setne	%cl
	shll	%cl, %r14d
	jmp	LBB0_6
LBB0_2:
	movq	_RADEON_HOST_PATH_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_HDP_APER_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%esi, %edx
	notl	%edx
	callq	_WREG32_P
	leaq	L_.str(%rip), %rdi
	callq	_DRM_INFO
	addl	%r14d, %r14d
	jmp	LBB0_6
LBB0_4:
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_INFO
	leaq	L_.str.2(%rip), %rdi
	callq	_DRM_INFO
LBB0_6:
	movl	%r14d, %eax
	addq	$16, %rsp
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_CONFIG_APER_SIZE,4,2    ## @RADEON_CONFIG_APER_SIZE
	.comm	_CHIP_RV280,8,3                 ## @CHIP_RV280
	.comm	_CHIP_RV350,8,3                 ## @CHIP_RV350
	.comm	_RADEON_HOST_PATH_CNTL,4,2      ## @RADEON_HOST_PATH_CNTL
	.comm	_RADEON_HDP_APER_CNTL,4,2       ## @RADEON_HDP_APER_CNTL
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Generation 2 PCI interface, using max accessible memory\n"

L_.str.1:                               ## @.str.1
	.asciz	"Generation 1 PCI interface in multifunction mode\n"

L_.str.2:                               ## @.str.2
	.asciz	"Limiting VRAM to one aperture\n"

	.no_dead_strip	_r100_get_accessible_vram
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function r100_get_accessible_vram
_r100_get_accessible_vram:              ; @r100_get_accessible_vram
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #48
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x20, x0
Lloh0:
	adrp	x8, _RADEON_CONFIG_APER_SIZE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_CONFIG_APER_SIZE@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x19, x0
	ldr	x8, [x20]
Lloh3:
	adrp	x9, _CHIP_RV280@GOTPAGE
Lloh4:
	ldr	x9, [x9, _CHIP_RV280@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
Lloh6:
	adrp	x10, _CHIP_RV350@GOTPAGE
Lloh7:
	ldr	x10, [x10, _CHIP_RV350@GOTPAGEOFF]
Lloh8:
	ldr	x10, [x10]
	cmp	x8, x9
	ccmp	x8, x10, #0, ne
	b.lt	LBB0_2
; %bb.1:
Lloh9:
	adrp	x8, _RADEON_HOST_PATH_CNTL@GOTPAGE
Lloh10:
	ldr	x8, [x8, _RADEON_HOST_PATH_CNTL@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
Lloh12:
	adrp	x8, _RADEON_HDP_APER_CNTL@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RADEON_HDP_APER_CNTL@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mvn	w2, w1
	bl	_WREG32_P
Lloh15:
	adrp	x0, l_.str@PAGE
Lloh16:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_INFO
	lsl	w19, w19, #1
	b	LBB0_5
LBB0_2:
	ldr	w0, [x20, #8]
	add	x2, sp, #12
	mov	w1, #14
	bl	_pci_read_config_byte
	ldrb	w8, [sp, #12]
	tbnz	w8, #7, LBB0_4
; %bb.3:
Lloh17:
	adrp	x8, _RADEON_HOST_PATH_CNTL@GOTPAGE
Lloh18:
	ldr	x8, [x8, _RADEON_HOST_PATH_CNTL@GOTPAGEOFF]
Lloh19:
	ldr	w0, [x8]
	bl	_RREG32
Lloh20:
	adrp	x8, _RADEON_HDP_APER_CNTL@GOTPAGE
Lloh21:
	ldr	x8, [x8, _RADEON_HDP_APER_CNTL@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
	tst	w8, w0
	cset	w8, ne
	lsl	w19, w19, w8
	b	LBB0_5
LBB0_4:
Lloh23:
	adrp	x0, l_.str.1@PAGE
Lloh24:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_INFO
Lloh25:
	adrp	x0, l_.str.2@PAGE
Lloh26:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	_DRM_INFO
LBB0_5:
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpAdd	Lloh25, Lloh26
	.loh AdrpAdd	Lloh23, Lloh24
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_CONFIG_APER_SIZE,4,2    ; @RADEON_CONFIG_APER_SIZE
	.comm	_CHIP_RV280,8,3                 ; @CHIP_RV280
	.comm	_CHIP_RV350,8,3                 ; @CHIP_RV350
	.comm	_RADEON_HOST_PATH_CNTL,4,2      ; @RADEON_HOST_PATH_CNTL
	.comm	_RADEON_HDP_APER_CNTL,4,2       ; @RADEON_HDP_APER_CNTL
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Generation 2 PCI interface, using max accessible memory\n"

l_.str.1:                               ; @.str.1
	.asciz	"Generation 1 PCI interface in multifunction mode\n"

l_.str.2:                               ; @.str.2
	.asciz	"Limiting VRAM to one aperture\n"

	.no_dead_strip	_r100_get_accessible_vram
.subsections_via_symbols
