	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_crtc_do_set_base        ## -- Begin function radeon_crtc_do_set_base
	.p2align	4, 0x90
_radeon_crtc_do_set_base:               ## @radeon_crtc_do_set_base
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$88, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%r8d, %r12d
	movl	%ecx, %r13d
                                        ## kill: def $edx killed $edx def $rdx
	movq	%rdx, -96(%rbp)                 ## 8-byte Spill
	movq	%rsi, %r15
	movq	%rdi, %rbx
	movq	8(%rdi), %rax
	movq	(%rax), %r14
	callq	_to_radeon_crtc
	movq	%rax, -128(%rbp)                ## 8-byte Spill
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	movq	%r15, %rax
	movl	%r12d, -68(%rbp)                ## 4-byte Spill
	testl	%r12d, %r12d
	jne	LBB0_3
## %bb.1:
	movq	(%rbx), %rax
	movq	(%rax), %rax
	testq	%rax, %rax
	je	LBB0_2
LBB0_3:
	movq	%r13, -56(%rbp)                 ## 8-byte Spill
	movq	%rbx, -120(%rbp)                ## 8-byte Spill
	movq	%r14, -80(%rbp)                 ## 8-byte Spill
	movq	%rax, -88(%rbp)                 ## 8-byte Spill
	movq	16(%rax), %rax
	movq	(%rax), %rax
	movl	(%rax), %r13d
	decl	%r13d
	andl	$536870911, %r13d               ## imm = 0x1FFFFFFF
	xorl	%r12d, %r12d
	cmpl	$3, %r13d
	ja	LBB0_49
## %bb.4:
	movq	-88(%rbp), %rax                 ## 8-byte Reload
	movq	8(%rax), %rax
	movq	(%rax), %rdi
	callq	_gem_to_radeon_bo
	movq	%rax, %r14
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	_radeon_bo_reserve
	movl	%eax, %r12d
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	callq	_unlikely
	testq	%rax, %rax
	jne	LBB0_49
## %bb.5:
	movl	%r13d, %eax
	leaq	L_switch.table.radeon_crtc_do_set_base(%rip), %rcx
	movl	(%rcx,%rax,4), %r13d
	.p2align	4, 0x90
LBB0_6:                                 ## =>This Inner Loop Header: Depth=1
	movq	_RADEON_GEM_DOMAIN_VRAM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$134217728, %edx                ## imm = 0x8000000
	leaq	-44(%rbp), %rcx
	callq	_radeon_bo_pin_restricted
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	callq	_unlikely
	testq	%rax, %rax
	je	LBB0_14
## %bb.7:                               ##   in Loop: Header=BB0_6 Depth=1
	movq	%r14, %rdi
	callq	_radeon_bo_unreserve
	cmpl	$0, -68(%rbp)                   ## 4-byte Folded Reload
	movq	-120(%rbp), %rax                ## 8-byte Reload
	jne	LBB0_13
## %bb.8:                               ##   in Loop: Header=BB0_6 Depth=1
	testq	%r15, %r15
	je	LBB0_13
## %bb.9:                               ##   in Loop: Header=BB0_6 Depth=1
	movq	(%rax), %rax
	cmpq	(%rax), %r15
	je	LBB0_13
## %bb.10:                              ##   in Loop: Header=BB0_6 Depth=1
	movq	8(%r15), %rax
	movq	(%rax), %rdi
	callq	_gem_to_radeon_bo
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	_radeon_bo_size
	movq	%rax, %r12
	movq	%r14, %rdi
	callq	_radeon_bo_size
	cmpq	%r12, %rax
	ja	LBB0_13
## %bb.11:                              ##   in Loop: Header=BB0_6 Depth=1
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_radeon_bo_reserve
	testl	%eax, %eax
	jne	LBB0_13
## %bb.12:                              ##   in Loop: Header=BB0_6 Depth=1
	movq	%rbx, %rdi
	callq	_radeon_bo_unpin
	movq	%rbx, %rdi
	callq	_radeon_bo_unreserve
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_radeon_bo_reserve
	movl	%eax, %r12d
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	callq	_unlikely
	movl	$0, %r15d
	testq	%rax, %rax
	je	LBB0_6
	jmp	LBB0_49
LBB0_2:
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_DEBUG_KMS
LBB0_48:
	xorl	%r12d, %r12d
	jmp	LBB0_49
LBB0_13:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r12d, %r12d
	subl	(%rax), %r12d
LBB0_49:
	movl	%r12d, %eax
	addq	$88, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_14:
	movl	%r13d, -100(%rbp)               ## 4-byte Spill
	leaq	-64(%rbp), %rsi
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	_radeon_bo_get_tiling_flags
	movq	%r14, %rdi
	callq	_radeon_bo_unreserve
	movq	_RADEON_TILING_MICRO@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, -64(%rbp)
	je	LBB0_16
## %bb.15:
	leaq	L_.str.2(%rip), %rdi
	callq	_DRM_ERROR
LBB0_16:
	movq	-80(%rbp), %r14                 ## 8-byte Reload
	movl	(%r14), %eax
	movq	-128(%rbp), %rbx                ## 8-byte Reload
	movl	%eax, (%rbx)
	subl	%eax, -44(%rbp)
	movq	-88(%rbp), %rcx                 ## 8-byte Reload
	movq	(%rcx), %rax
	movq	16(%rcx), %rcx
	movl	(%rax), %eax
	movq	(%rcx), %rcx
	movl	(%rcx), %esi
	cltd
	idivl	%esi
                                        ## kill: def $eax killed $eax def $rax
	movl	%esi, %edi
	movq	%rax, -112(%rbp)                ## 8-byte Spill
	imull	%eax, %edi
	shll	$3, %edi
	shll	$6, %esi
	callq	_DIV_ROUND_UP
	movl	%eax, -60(%rbp)                 ## 4-byte Spill
	movq	_RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	_RADEON_TILING_MACRO@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	andl	-64(%rbp), %r12d
	movq	%r14, %rdi
	callq	_ASIC_IS_R300
	testl	%r12d, %r12d
	je	LBB0_20
## %bb.17:
	testq	%rax, %rax
	je	LBB0_19
## %bb.18:
	movq	_R300_CRTC_X_Y_MODE_EN@GOTPCREL(%rip), %rax
	movq	_R300_CRTC_MICRO_TILE_BUFFER_DIS@GOTPCREL(%rip), %rcx
	movq	_R300_CRTC_MACRO_TILE_EN@GOTPCREL(%rip), %rdx
	orl	(%rax), %r13d
	orl	(%rcx), %r13d
	orl	(%rdx), %r13d
	jmp	LBB0_23
LBB0_20:
	testq	%rax, %rax
	je	LBB0_22
## %bb.21:
	movq	_R300_CRTC_X_Y_MODE_EN@GOTPCREL(%rip), %rax
	movq	_R300_CRTC_MICRO_TILE_BUFFER_DIS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	_R300_CRTC_MACRO_TILE_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	notl	%ecx
	andl	%ecx, %r13d
	jmp	LBB0_23
LBB0_19:
	movq	_RADEON_CRTC_TILE_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	jmp	LBB0_23
LBB0_22:
	movq	_RADEON_CRTC_TILE_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r13d
LBB0_23:
	movq	_RADEON_TILING_MACRO@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, -64(%rbp)
	je	LBB0_27
## %bb.24:
	movq	%rbx, %r12
	movq	-80(%rbp), %rdi                 ## 8-byte Reload
	callq	_ASIC_IS_R300
	testq	%rax, %rax
	je	LBB0_26
## %bb.25:
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	shll	$16, %eax
	orl	-96(%rbp), %eax                 ## 4-byte Folded Reload
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
	movl	$-2048, %ebx                    ## imm = 0xF800
	andl	-44(%rbp), %ebx
	jmp	LBB0_34
LBB0_27:
	movq	-88(%rbp), %rax                 ## 8-byte Reload
	movq	16(%rax), %rax
	movq	(%rax), %rax
	movl	(%rax), %eax
	decl	%eax
	andl	$536870911, %eax                ## imm = 0x1FFFFFFF
	cmpl	$3, %eax
	ja	LBB0_48
## %bb.28:
	movq	%rbx, %r12
	movq	-112(%rbp), %rbx                ## 8-byte Reload
	imull	-56(%rbp), %ebx                 ## 4-byte Folded Reload
	addl	-96(%rbp), %ebx                 ## 4-byte Folded Reload
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_29:
	addl	%ebx, %ebx
	jmp	LBB0_32
LBB0_26:
	movq	-88(%rbp), %rax                 ## 8-byte Reload
	movq	16(%rax), %rax
	movq	(%rax), %rax
	movl	(%rax), %eax
	shrl	%eax
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
	movl	%esi, %ecx
	sarl	$3, %ecx
	movq	-112(%rbp), %rbx                ## 8-byte Reload
	imull	%ecx, %ebx
	movq	-96(%rbp), %rdi                 ## 8-byte Reload
	addl	%edi, %ebx
	movb	$8, %cl
	subb	%al, %cl
	sarl	%cl, %ebx
	shll	$11, %ebx
	movl	%eax, %ecx
	shll	%cl, %edi
	leal	255(%rdi), %eax
	testl	%edi, %edi
	cmovnsl	%edi, %eax
	andl	$-256, %eax
	subl	%eax, %edi
	leal	7(%rsi), %eax
	leal	15(%rsi), %ecx
	testl	%esi, %esi
	cmovnsl	%esi, %eax
	cmovnsl	%esi, %ecx
	andl	$16777208, %eax                 ## imm = 0xFFFFF8
	movl	%esi, %edx
	subl	%eax, %edx
	shll	$8, %edx
	addl	-44(%rbp), %edx
	addl	%edi, %edx
	addl	%edx, %ebx
	andl	$-16, %ecx
	subl	%ecx, %esi
	orl	%esi, %r13d
	jmp	LBB0_33
LBB0_30:
	leal	(%rbx,%rbx,2), %ebx
	jmp	LBB0_32
LBB0_31:
	shll	$2, %ebx
LBB0_32:
	addl	-44(%rbp), %ebx
LBB0_33:
	xorl	%eax, %eax
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
LBB0_34:
	movl	-60(%rbp), %ecx                 ## 4-byte Reload
	movl	%ecx, %r14d
	shll	$16, %r14d
	andl	$-8, %ebx
	movl	%ebx, -44(%rbp)
	movq	%r12, %rbx
	cmpl	$1, 4(%r12)
	jne	LBB0_35
## %bb.36:
	movq	_RADEON_CRTC2_GEN_CNTL@GOTPCREL(%rip), %rax
	jmp	LBB0_37
LBB0_35:
	movq	_RADEON_CRTC_GEN_CNTL@GOTPCREL(%rip), %rax
LBB0_37:
	orl	%ecx, %r14d
	movl	(%rax), %r12d
	movl	%r12d, %edi
	callq	_RREG32
	andl	$-3841, %eax                    ## imm = 0xF0FF
	movl	-100(%rbp), %ecx                ## 4-byte Reload
	orl	%eax, %ecx
	movq	_RADEON_CRTC_VSTAT_MODE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	%ecx, %esi
	movl	%r12d, %edi
	callq	_WREG32
	movl	-44(%rbp), %r12d
	movq	_RADEON_DISPLAY_BASE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rbx), %esi
	movl	8(%rbx), %edi
	addl	(%rax), %edi
	callq	_WREG32
	movq	-80(%rbp), %rdi                 ## 8-byte Reload
	callq	_ASIC_IS_R300
	testq	%rax, %rax
	je	LBB0_42
## %bb.38:
	cmpl	$0, 4(%rbx)
	jne	LBB0_39
## %bb.40:
	movq	_R300_CRTC_TILE_X0_Y0@GOTPCREL(%rip), %rax
	jmp	LBB0_41
LBB0_39:
	movq	_R300_CRTC2_TILE_X0_Y0@GOTPCREL(%rip), %rax
LBB0_41:
	movl	(%rax), %edi
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
                                        ## kill: def $esi killed $esi killed $rsi
	callq	_WREG32
LBB0_42:
	movq	_RADEON_CRTC_OFFSET_CNTL@GOTPCREL(%rip), %rax
	movl	8(%rbx), %edi
	addl	(%rax), %edi
	movl	%r13d, %esi
	callq	_WREG32
	movq	_RADEON_CRTC_OFFSET@GOTPCREL(%rip), %rax
	movl	8(%rbx), %edi
	addl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_RADEON_CRTC_PITCH@GOTPCREL(%rip), %rax
	movl	8(%rbx), %edi
	addl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	cmpl	$0, -68(%rbp)                   ## 4-byte Folded Reload
	jne	LBB0_47
## %bb.43:
	testq	%r15, %r15
	je	LBB0_47
## %bb.44:
	movq	-120(%rbp), %rax                ## 8-byte Reload
	movq	(%rax), %rax
	cmpq	(%rax), %r15
	je	LBB0_47
## %bb.45:
	movq	8(%r15), %rax
	movq	(%rax), %rdi
	callq	_gem_to_radeon_bo
	movq	%rax, %rbx
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	_radeon_bo_reserve
	movl	%eax, %r12d
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	callq	_unlikely
	testq	%rax, %rax
	jne	LBB0_49
## %bb.46:
	movq	%rbx, %rdi
	callq	_radeon_bo_unpin
	movq	%rbx, %rdi
	callq	_radeon_bo_unreserve
LBB0_47:
	movq	-80(%rbp), %rdi                 ## 8-byte Reload
	callq	_radeon_bandwidth_update
	jmp	LBB0_48
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_32, LBB0_32-LJTI0_0
.set L0_0_set_29, LBB0_29-LJTI0_0
.set L0_0_set_30, LBB0_30-LJTI0_0
.set L0_0_set_31, LBB0_31-LJTI0_0
LJTI0_0:
	.long	L0_0_set_32
	.long	L0_0_set_29
	.long	L0_0_set_30
	.long	L0_0_set_31
	.end_data_region
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"\n"

L_.str.1:                               ## @.str.1
	.asciz	"No FB bound\n"

	.comm	_RADEON_GEM_DOMAIN_VRAM,4,2     ## @RADEON_GEM_DOMAIN_VRAM
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_RADEON_TILING_MICRO,4,2        ## @RADEON_TILING_MICRO
L_.str.2:                               ## @.str.2
	.asciz	"trying to scanout microtiled buffer\n"

	.comm	_RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN,4,2 ## @RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN
	.comm	_RADEON_TILING_MACRO,4,2        ## @RADEON_TILING_MACRO
	.comm	_R300_CRTC_X_Y_MODE_EN,4,2      ## @R300_CRTC_X_Y_MODE_EN
	.comm	_R300_CRTC_MICRO_TILE_BUFFER_DIS,4,2 ## @R300_CRTC_MICRO_TILE_BUFFER_DIS
	.comm	_R300_CRTC_MACRO_TILE_EN,4,2    ## @R300_CRTC_MACRO_TILE_EN
	.comm	_RADEON_CRTC_TILE_EN,4,2        ## @RADEON_CRTC_TILE_EN
	.comm	_RADEON_CRTC2_GEN_CNTL,4,2      ## @RADEON_CRTC2_GEN_CNTL
	.comm	_RADEON_CRTC_GEN_CNTL,4,2       ## @RADEON_CRTC_GEN_CNTL
	.comm	_RADEON_CRTC_VSTAT_MODE_MASK,4,2 ## @RADEON_CRTC_VSTAT_MODE_MASK
	.comm	_RADEON_DISPLAY_BASE_ADDR,4,2   ## @RADEON_DISPLAY_BASE_ADDR
	.comm	_R300_CRTC2_TILE_X0_Y0,4,2      ## @R300_CRTC2_TILE_X0_Y0
	.comm	_R300_CRTC_TILE_X0_Y0,4,2       ## @R300_CRTC_TILE_X0_Y0
	.comm	_RADEON_CRTC_OFFSET_CNTL,4,2    ## @RADEON_CRTC_OFFSET_CNTL
	.comm	_RADEON_CRTC_OFFSET,4,2         ## @RADEON_CRTC_OFFSET
	.comm	_RADEON_CRTC_PITCH,4,2          ## @RADEON_CRTC_PITCH
	.section	__TEXT,__literal16,16byte_literals
	.p2align	2                               ## @switch.table.radeon_crtc_do_set_base
L_switch.table.radeon_crtc_do_set_base:
	.long	512                             ## 0x200
	.long	1024                            ## 0x400
	.long	1280                            ## 0x500
	.long	1536                            ## 0x600

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_crtc_do_set_base        ; -- Begin function radeon_crtc_do_set_base
	.p2align	2
_radeon_crtc_do_set_base:               ; @radeon_crtc_do_set_base
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #128
	.cfi_def_cfa_offset 128
	stp	x28, x27, [sp, #32]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #48]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #64]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #80]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #96]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #112]            ; 16-byte Folded Spill
	add	x29, sp, #112
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x4
	mov	x24, x3
	mov	x25, x2
	mov	x23, x1
	mov	x20, x0
	ldr	x8, [x0, #8]
	ldr	x26, [x8]
	bl	_to_radeon_crtc
	mov	x22, x0
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_KMS
	mov	x28, x23
	cbnz	w21, LBB0_2
; %bb.1:
	ldr	x8, [x20]
	ldr	x28, [x8]
	cbz	x28, LBB0_12
LBB0_2:
	ldr	x8, [x28, #16]
	ldr	x8, [x8]
	ldr	w8, [x8]
	sub	w8, w8, #1
	and	w19, w8, #0x1fffffff
	cmp	w19, #3
	b.hi	LBB0_13
; %bb.3:
	str	x26, [sp, #16]                  ; 8-byte Folded Spill
	ldr	x8, [x28, #8]
	ldr	x0, [x8]
	bl	_gem_to_radeon_bo
	mov	x26, x0
	mov	w1, #0
	bl	_radeon_bo_reserve
	mov	x27, x0
	cmp	w0, #0
	cset	w0, ne
	bl	_unlikely
	cbnz	x0, LBB0_14
; %bb.4:
Lloh2:
	adrp	x8, l_switch.table.radeon_crtc_do_set_base@PAGE
Lloh3:
	add	x8, x8, l_switch.table.radeon_crtc_do_set_base@PAGEOFF
	ldr	w8, [x8, w19, uxtw #2]
	str	w8, [sp, #12]                   ; 4-byte Folded Spill
Lloh4:
	adrp	x19, _RADEON_GEM_DOMAIN_VRAM@GOTPAGE
Lloh5:
	ldr	x19, [x19, _RADEON_GEM_DOMAIN_VRAM@GOTPAGEOFF]
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x19]
	add	x3, sp, #28
	mov	x0, x26
	mov	w2, #134217728
	bl	_radeon_bo_pin_restricted
	cmp	w0, #0
	cset	w0, ne
	bl	_unlikely
	cbz	x0, LBB0_16
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	mov	x0, x26
	bl	_radeon_bo_unreserve
	cbnz	w21, LBB0_15
; %bb.7:                                ;   in Loop: Header=BB0_5 Depth=1
	cbz	x23, LBB0_15
; %bb.8:                                ;   in Loop: Header=BB0_5 Depth=1
	ldr	x8, [x20]
	ldr	x8, [x8]
	cmp	x23, x8
	b.eq	LBB0_15
; %bb.9:                                ;   in Loop: Header=BB0_5 Depth=1
	ldr	x8, [x23, #8]
	ldr	x0, [x8]
	bl	_gem_to_radeon_bo
	mov	x23, x0
	bl	_radeon_bo_size
	mov	x27, x0
	mov	x0, x26
	bl	_radeon_bo_size
	cmp	x0, x27
	b.hi	LBB0_15
; %bb.10:                               ;   in Loop: Header=BB0_5 Depth=1
	mov	x0, x23
	mov	w1, #0
	bl	_radeon_bo_reserve
	cbnz	w0, LBB0_15
; %bb.11:                               ;   in Loop: Header=BB0_5 Depth=1
	mov	x0, x23
	bl	_radeon_bo_unpin
	mov	x0, x23
	bl	_radeon_bo_unreserve
	mov	x0, x26
	mov	w1, #0
	bl	_radeon_bo_reserve
	mov	x27, x0
	cmp	w0, #0
	cset	w0, ne
	bl	_unlikely
	mov	x23, #0
	cbz	x0, LBB0_5
	b	LBB0_14
LBB0_12:
Lloh6:
	adrp	x0, l_.str.1@PAGE
Lloh7:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_DEBUG_KMS
LBB0_13:
	mov	w27, #0
LBB0_14:
	mov	x0, x27
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	ret
LBB0_15:
Lloh8:
	adrp	x8, _EINVAL@GOTPAGE
Lloh9:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	neg	w27, w8
	b	LBB0_14
LBB0_16:
	add	x1, sp, #24
	mov	x0, x26
	mov	x2, #0
	bl	_radeon_bo_get_tiling_flags
	mov	x0, x26
	bl	_radeon_bo_unreserve
	ldr	w8, [sp, #24]
Lloh11:
	adrp	x9, _RADEON_TILING_MICRO@GOTPAGE
Lloh12:
	ldr	x9, [x9, _RADEON_TILING_MICRO@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_18
; %bb.17:
Lloh14:
	adrp	x0, l_.str.2@PAGE
Lloh15:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	_DRM_ERROR
LBB0_18:
	ldr	x19, [sp, #16]                  ; 8-byte Folded Reload
	ldr	w8, [x19]
	str	w8, [x22]
	ldr	w9, [sp, #28]
	sub	w8, w9, w8
	str	w8, [sp, #28]
	ldr	x8, [x28]
	ldr	w8, [x8]
	ldr	x9, [x28, #16]
	ldr	x9, [x9]
	ldr	w9, [x9]
	sdiv	w8, w8, w9
	str	w8, [sp, #4]                    ; 4-byte Folded Spill
	mul	w8, w9, w8
	lsl	w0, w8, #3
	lsl	w1, w9, #6
	bl	_DIV_ROUND_UP
	str	w0, [sp, #8]                    ; 4-byte Folded Spill
Lloh16:
	adrp	x8, _RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN@GOTPAGE
Lloh17:
	ldr	x8, [x8, _RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN@GOTPAGEOFF]
Lloh18:
	ldr	w26, [x8]
	ldr	w8, [sp, #24]
Lloh19:
	adrp	x9, _RADEON_TILING_MACRO@GOTPAGE
Lloh20:
	ldr	x9, [x9, _RADEON_TILING_MACRO@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	and	w27, w9, w8
	mov	x0, x19
	bl	_ASIC_IS_R300
	cbz	w27, LBB0_21
; %bb.19:
	cbz	x0, LBB0_23
; %bb.20:
Lloh22:
	adrp	x8, _R300_CRTC_X_Y_MODE_EN@GOTPAGE
Lloh23:
	ldr	x8, [x8, _R300_CRTC_X_Y_MODE_EN@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
Lloh25:
	adrp	x9, _R300_CRTC_MICRO_TILE_BUFFER_DIS@GOTPAGE
Lloh26:
	ldr	x9, [x9, _R300_CRTC_MICRO_TILE_BUFFER_DIS@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
Lloh28:
	adrp	x10, _R300_CRTC_MACRO_TILE_EN@GOTPAGE
Lloh29:
	ldr	x10, [x10, _R300_CRTC_MACRO_TILE_EN@GOTPAGEOFF]
Lloh30:
	ldr	w10, [x10]
	orr	w8, w8, w26
	orr	w8, w8, w9
	orr	w26, w8, w10
	b	LBB0_26
LBB0_21:
	cbz	x0, LBB0_24
; %bb.22:
Lloh31:
	adrp	x8, _R300_CRTC_X_Y_MODE_EN@GOTPAGE
Lloh32:
	ldr	x8, [x8, _R300_CRTC_X_Y_MODE_EN@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
Lloh34:
	adrp	x9, _R300_CRTC_MICRO_TILE_BUFFER_DIS@GOTPAGE
Lloh35:
	ldr	x9, [x9, _R300_CRTC_MICRO_TILE_BUFFER_DIS@GOTPAGEOFF]
Lloh36:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh37:
	adrp	x9, _R300_CRTC_MACRO_TILE_EN@GOTPAGE
Lloh38:
	ldr	x9, [x9, _R300_CRTC_MACRO_TILE_EN@GOTPAGEOFF]
Lloh39:
	ldr	w9, [x9]
	orr	w8, w8, w9
	b	LBB0_25
LBB0_23:
Lloh40:
	adrp	x8, _RADEON_CRTC_TILE_EN@GOTPAGE
Lloh41:
	ldr	x8, [x8, _RADEON_CRTC_TILE_EN@GOTPAGEOFF]
Lloh42:
	ldr	w8, [x8]
	orr	w26, w8, w26
	b	LBB0_26
LBB0_24:
Lloh43:
	adrp	x8, _RADEON_CRTC_TILE_EN@GOTPAGE
Lloh44:
	ldr	x8, [x8, _RADEON_CRTC_TILE_EN@GOTPAGEOFF]
Lloh45:
	ldr	w8, [x8]
LBB0_25:
	bic	w26, w26, w8
LBB0_26:
	ldr	w8, [sp, #24]
Lloh46:
	adrp	x9, _RADEON_TILING_MACRO@GOTPAGE
Lloh47:
	ldr	x9, [x9, _RADEON_TILING_MACRO@GOTPAGEOFF]
Lloh48:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_29
; %bb.27:
	ldr	x0, [sp, #16]                   ; 8-byte Folded Reload
	bl	_ASIC_IS_R300
	cbz	x0, LBB0_32
; %bb.28:
	orr	w27, w25, w24, lsl #16
	ldr	w8, [sp, #28]
	and	w8, w8, #0xfffff800
	b	LBB0_36
LBB0_29:
	ldr	x8, [x28, #16]
	ldr	x8, [x8]
	ldr	w8, [x8]
	sub	w8, w8, #1
	and	w9, w8, #0x1fffffff
	cmp	w9, #3
	b.hi	LBB0_13
; %bb.30:
	ldr	w8, [sp, #4]                    ; 4-byte Folded Reload
	madd	w8, w8, w24, w25
Lloh49:
	adrp	x10, lJTI0_0@PAGE
Lloh50:
	add	x10, x10, lJTI0_0@PAGEOFF
	adr	x11, LBB0_31
	ldrb	w12, [x10, x9]
	add	x11, x11, x12, lsl #2
	br	x11
LBB0_31:
	lsl	w8, w8, #1
	b	LBB0_35
LBB0_32:
	mov	w27, #0
	ldr	x8, [x28, #16]
	ldr	x8, [x8]
	ldr	w8, [x8]
	asr	w8, w8, #1
	asr	w9, w24, #3
	ldr	w10, [sp, #4]                   ; 4-byte Folded Reload
	madd	w9, w10, w9, w25
	mov	w10, #8
	sub	w10, w10, w8
	asr	w9, w9, w10
	lsl	w8, w25, w8
	and	w10, w8, #0xff
	negs	w8, w8
	and	w8, w8, #0xff
	csneg	w8, w10, w8, mi
	negs	w10, w24
	and	w11, w10, #0x7
	and	w12, w24, #0x7
	csneg	w11, w12, w11, mi
	ldr	w12, [sp, #28]
	add	w11, w12, w11, lsl #8
	add	w8, w11, w8
	add	w8, w8, w9, lsl #11
	and	w9, w10, #0xf
	and	w10, w24, #0xf
	csneg	w9, w10, w9, mi
	orr	w26, w26, w9
	b	LBB0_36
LBB0_33:
	add	w8, w8, w8, lsl #1
	b	LBB0_35
LBB0_34:
	lsl	w8, w8, #2
LBB0_35:
	mov	w27, #0
	ldr	w9, [sp, #28]
	add	w8, w9, w8
LBB0_36:
	ldr	w9, [sp, #8]                    ; 4-byte Folded Reload
	orr	w24, w9, w9, lsl #16
	and	w8, w8, #0xfffffff8
	str	w8, [sp, #28]
Lloh51:
	adrp	x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGE
Lloh52:
	ldr	x8, [x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGEOFF]
	ldr	w9, [x22, #4]
Lloh53:
	adrp	x10, _RADEON_CRTC_GEN_CNTL@GOTPAGE
Lloh54:
	ldr	x10, [x10, _RADEON_CRTC_GEN_CNTL@GOTPAGEOFF]
	cmp	w9, #1
	csel	x8, x8, x10, eq
	ldr	w25, [x8]
	mov	x0, x25
	bl	_RREG32
	and	w8, w0, #0xfffff0ff
	ldr	w9, [sp, #12]                   ; 4-byte Folded Reload
	orr	w8, w8, w9
Lloh55:
	adrp	x9, _RADEON_CRTC_VSTAT_MODE_MASK@GOTPAGE
Lloh56:
	ldr	x9, [x9, _RADEON_CRTC_VSTAT_MODE_MASK@GOTPAGEOFF]
Lloh57:
	ldr	w9, [x9]
	bic	w1, w8, w9
	mov	x0, x25
	bl	_WREG32
	ldr	w25, [sp, #28]
Lloh58:
	adrp	x8, _RADEON_DISPLAY_BASE_ADDR@GOTPAGE
Lloh59:
	ldr	x8, [x8, _RADEON_DISPLAY_BASE_ADDR@GOTPAGEOFF]
Lloh60:
	ldr	w8, [x8]
	ldr	w9, [x22, #8]
	add	w0, w9, w8
	ldr	w1, [x22]
	bl	_WREG32
	ldr	x0, [sp, #16]                   ; 8-byte Folded Reload
	bl	_ASIC_IS_R300
	cbz	x0, LBB0_38
; %bb.37:
Lloh61:
	adrp	x8, _R300_CRTC_TILE_X0_Y0@GOTPAGE
Lloh62:
	ldr	x8, [x8, _R300_CRTC_TILE_X0_Y0@GOTPAGEOFF]
	ldr	w9, [x22, #4]
Lloh63:
	adrp	x10, _R300_CRTC2_TILE_X0_Y0@GOTPAGE
Lloh64:
	ldr	x10, [x10, _R300_CRTC2_TILE_X0_Y0@GOTPAGEOFF]
	cmp	w9, #0
	csel	x8, x8, x10, eq
	ldr	w0, [x8]
	mov	x1, x27
	bl	_WREG32
LBB0_38:
Lloh65:
	adrp	x8, _RADEON_CRTC_OFFSET_CNTL@GOTPAGE
Lloh66:
	ldr	x8, [x8, _RADEON_CRTC_OFFSET_CNTL@GOTPAGEOFF]
Lloh67:
	ldr	w8, [x8]
	ldr	w9, [x22, #8]
	add	w0, w9, w8
	mov	x1, x26
	bl	_WREG32
Lloh68:
	adrp	x8, _RADEON_CRTC_OFFSET@GOTPAGE
Lloh69:
	ldr	x8, [x8, _RADEON_CRTC_OFFSET@GOTPAGEOFF]
Lloh70:
	ldr	w8, [x8]
	ldr	w9, [x22, #8]
	add	w0, w9, w8
	mov	x1, x25
	bl	_WREG32
Lloh71:
	adrp	x8, _RADEON_CRTC_PITCH@GOTPAGE
Lloh72:
	ldr	x8, [x8, _RADEON_CRTC_PITCH@GOTPAGEOFF]
Lloh73:
	ldr	w8, [x8]
	ldr	w9, [x22, #8]
	add	w0, w9, w8
	mov	x1, x24
	bl	_WREG32
	cbnz	w21, LBB0_43
; %bb.39:
	cbz	x23, LBB0_43
; %bb.40:
	ldr	x8, [x20]
	ldr	x8, [x8]
	cmp	x23, x8
	b.eq	LBB0_43
; %bb.41:
	ldr	x8, [x23, #8]
	ldr	x0, [x8]
	bl	_gem_to_radeon_bo
	mov	x20, x0
	mov	w1, #0
	bl	_radeon_bo_reserve
	mov	x27, x0
	cmp	w0, #0
	cset	w0, ne
	bl	_unlikely
	cbnz	x0, LBB0_14
; %bb.42:
	mov	x0, x20
	bl	_radeon_bo_unpin
	mov	x0, x20
	bl	_radeon_bo_unreserve
LBB0_43:
	ldr	x0, [sp, #16]                   ; 8-byte Folded Reload
	bl	_radeon_bandwidth_update
	b	LBB0_13
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpAdd	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpAdd	Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_35-LBB0_31)>>2
	.byte	(LBB0_31-LBB0_31)>>2
	.byte	(LBB0_33-LBB0_31)>>2
	.byte	(LBB0_34-LBB0_31)>>2
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"\n"

l_.str.1:                               ; @.str.1
	.asciz	"No FB bound\n"

	.comm	_RADEON_GEM_DOMAIN_VRAM,4,2     ; @RADEON_GEM_DOMAIN_VRAM
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_RADEON_TILING_MICRO,4,2        ; @RADEON_TILING_MICRO
l_.str.2:                               ; @.str.2
	.asciz	"trying to scanout microtiled buffer\n"

	.comm	_RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN,4,2 ; @RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN
	.comm	_RADEON_TILING_MACRO,4,2        ; @RADEON_TILING_MACRO
	.comm	_R300_CRTC_X_Y_MODE_EN,4,2      ; @R300_CRTC_X_Y_MODE_EN
	.comm	_R300_CRTC_MICRO_TILE_BUFFER_DIS,4,2 ; @R300_CRTC_MICRO_TILE_BUFFER_DIS
	.comm	_R300_CRTC_MACRO_TILE_EN,4,2    ; @R300_CRTC_MACRO_TILE_EN
	.comm	_RADEON_CRTC_TILE_EN,4,2        ; @RADEON_CRTC_TILE_EN
	.comm	_RADEON_CRTC2_GEN_CNTL,4,2      ; @RADEON_CRTC2_GEN_CNTL
	.comm	_RADEON_CRTC_GEN_CNTL,4,2       ; @RADEON_CRTC_GEN_CNTL
	.comm	_RADEON_CRTC_VSTAT_MODE_MASK,4,2 ; @RADEON_CRTC_VSTAT_MODE_MASK
	.comm	_RADEON_DISPLAY_BASE_ADDR,4,2   ; @RADEON_DISPLAY_BASE_ADDR
	.comm	_R300_CRTC2_TILE_X0_Y0,4,2      ; @R300_CRTC2_TILE_X0_Y0
	.comm	_R300_CRTC_TILE_X0_Y0,4,2       ; @R300_CRTC_TILE_X0_Y0
	.comm	_RADEON_CRTC_OFFSET_CNTL,4,2    ; @RADEON_CRTC_OFFSET_CNTL
	.comm	_RADEON_CRTC_OFFSET,4,2         ; @RADEON_CRTC_OFFSET
	.comm	_RADEON_CRTC_PITCH,4,2          ; @RADEON_CRTC_PITCH
	.section	__TEXT,__literal16,16byte_literals
	.p2align	2                               ; @switch.table.radeon_crtc_do_set_base
l_switch.table.radeon_crtc_do_set_base:
	.long	512                             ; 0x200
	.long	1024                            ; 0x400
	.long	1280                            ; 0x500
	.long	1536                            ; 0x600

.subsections_via_symbols
