	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_meson_vpp_init                 ## -- Begin function meson_vpp_init
	.p2align	4, 0x90
_meson_vpp_init:                        ## @meson_vpp_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	_VPU_COMPATIBLE_GXL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_meson_vpu_is_compatible
	movl	$1081472, %r14d                 ## imm = 0x108080
	movq	_VPP_DUMMY_DATA1@GOTPCREL(%rip), %r13
	testq	%rax, %rax
	jne	LBB0_5
## %bb.1:
	movq	_VPU_COMPATIBLE_GXM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_3
## %bb.2:
	movq	(%r12), %r14
	movq	_VIU_MISC_CTRL1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %r14
	movl	$16711680, %edi                 ## imm = 0xFF0000
	movl	$16711680, %esi                 ## imm = 0xFF0000
	movq	%r14, %rdx
	callq	_writel_bits_relaxed
	movq	_VPP_PPS_DUMMY_DATA_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	(%r12), %r15
	movq	_VPP_DOLBY_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %r15
	movl	%r14d, %edi
	movq	%r15, %rsi
	callq	_writel_relaxed
	movl	$16908416, %r14d                ## imm = 0x1020080
	jmp	LBB0_5
LBB0_3:
	movq	_VPU_COMPATIBLE_G12A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_6
## %bb.4:
	movl	$15, %r14d
	movq	_DOLBY_PATH_CTRL@GOTPCREL(%rip), %r13
LBB0_5:
	movq	(%r12), %rbx
	movl	(%r13), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r14d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
LBB0_6:
	movq	_VPU_COMPATIBLE_G12A@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r12, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_8
## %bb.7:
	movq	_VPP_OFIFO_SIZE_DEFAULT@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	(%r12), %rbx
	movq	_VPP_OFIFO_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r14d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	jmp	LBB0_9
LBB0_8:
	movq	_VPP_OFIFO_SIZE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	(%r12), %rbx
	movq	_VPP_OFIFO_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r14d, %edi
	movl	$1919, %esi                     ## imm = 0x77F
	movq	%rbx, %rdx
	callq	_writel_bits_relaxed
LBB0_9:
	movl	$4, %edi
	callq	_VPP_POSTBLEND_HOLD_LINES
	movl	%eax, %r14d
	movl	$4, %edi
	callq	_VPP_PREBLEND_HOLD_LINES
	orl	%eax, %r14d
	movq	(%r12), %rbx
	movq	_VPP_HOLD_LINES@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r14d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	(%r15), %esi
	movq	%r12, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	jne	LBB0_11
## %bb.10:
	movq	_VPP_PREBLEND_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	(%r12), %rbx
	movq	_VPP_MISC@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r14d, %edi
	xorl	%esi, %esi
	movq	%rbx, %rdx
	callq	_writel_bits_relaxed
	movq	_VPP_POSTBLEND_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	(%r12), %rbx
	movl	(%r15), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r14d, %edi
	xorl	%esi, %esi
	movq	%rbx, %rdx
	callq	_writel_bits_relaxed
	movq	_VPP_OSD1_POSTBLEND@GOTPCREL(%rip), %rax
	movq	_VPP_OSD2_POSTBLEND@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	_VPP_VD1_POSTBLEND@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_VPP_VD2_POSTBLEND@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_VPP_VD1_PREBLEND@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_VPP_VD2_PREBLEND@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	(%r12), %r14
	movl	(%r15), %edi
	callq	__REG
	addq	%rax, %r14
	movl	%ebx, %edi
	xorl	%esi, %esi
	movq	%r14, %rdx
	callq	_writel_bits_relaxed
	movq	(%r12), %rbx
	movq	_VPP_PREBLEND_VD1_H_START_END@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	$4096, %edi                     ## imm = 0x1000
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	(%r12), %rbx
	movq	_VPP_BLEND_VD2_H_START_END@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	$4096, %edi                     ## imm = 0x1000
	movq	%rbx, %rsi
	callq	_writel_relaxed
LBB0_11:
	movq	(%r12), %rbx
	movq	_VPP_OSD_SC_CTRL0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	xorl	%edi, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	(%r12), %rbx
	movq	_VPP_OSD_VSC_CTRL0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	xorl	%edi, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	(%r12), %rbx
	movq	_VPP_OSD_HSC_CTRL0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	xorl	%edi, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movl	$4, %edi
	callq	_VPP_VSC_BANK_LENGTH
	movl	%eax, %ebx
	movl	$4, %edi
	callq	_VPP_HSC_BANK_LENGTH
	orl	%eax, %ebx
	movq	_VPP_SC_VD_EN_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	(%r12), %r14
	movq	_VPP_SC_MISC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %r14
	movl	%ebx, %edi
	movq	%r14, %rsi
	callq	_writel_relaxed
	movq	_VPP_MINUS_BLACK_LVL_VADJ1_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	(%r12), %rbx
	movq	_VPP_VADJ_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r14d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	_vpp_filter_coefs_4point_bspline@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_meson_vpp_write_scaling_filter_coefs
	movl	(%rbx), %esi
	movq	%r12, %rdi
	movl	$1, %edx
	callq	_meson_vpp_write_scaling_filter_coefs
	movq	_vpp_filter_coefs_bicubic@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_meson_vpp_write_vd_scaling_filter_coefs
	movl	(%rbx), %esi
	movq	%r12, %rdi
	movl	$1, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_meson_vpp_write_vd_scaling_filter_coefs ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_VPU_COMPATIBLE_GXL,4,2         ## @VPU_COMPATIBLE_GXL
	.comm	_VPP_DUMMY_DATA1,4,2            ## @VPP_DUMMY_DATA1
	.comm	_VPU_COMPATIBLE_GXM,4,2         ## @VPU_COMPATIBLE_GXM
	.comm	_VIU_MISC_CTRL1,4,2             ## @VIU_MISC_CTRL1
	.comm	_VPP_PPS_DUMMY_DATA_MODE,4,2    ## @VPP_PPS_DUMMY_DATA_MODE
	.comm	_VPP_DOLBY_CTRL,4,2             ## @VPP_DOLBY_CTRL
	.comm	_VPU_COMPATIBLE_G12A,4,2        ## @VPU_COMPATIBLE_G12A
	.comm	_DOLBY_PATH_CTRL,4,2            ## @DOLBY_PATH_CTRL
	.comm	_VPP_OFIFO_SIZE_DEFAULT,4,2     ## @VPP_OFIFO_SIZE_DEFAULT
	.comm	_VPP_OFIFO_SIZE,4,2             ## @VPP_OFIFO_SIZE
	.comm	_VPP_OFIFO_SIZE_MASK,4,2        ## @VPP_OFIFO_SIZE_MASK
	.comm	_VPP_HOLD_LINES,4,2             ## @VPP_HOLD_LINES
	.comm	_VPP_PREBLEND_ENABLE,4,2        ## @VPP_PREBLEND_ENABLE
	.comm	_VPP_MISC,4,2                   ## @VPP_MISC
	.comm	_VPP_POSTBLEND_ENABLE,4,2       ## @VPP_POSTBLEND_ENABLE
	.comm	_VPP_OSD1_POSTBLEND,4,2         ## @VPP_OSD1_POSTBLEND
	.comm	_VPP_OSD2_POSTBLEND,4,2         ## @VPP_OSD2_POSTBLEND
	.comm	_VPP_VD1_POSTBLEND,4,2          ## @VPP_VD1_POSTBLEND
	.comm	_VPP_VD2_POSTBLEND,4,2          ## @VPP_VD2_POSTBLEND
	.comm	_VPP_VD1_PREBLEND,4,2           ## @VPP_VD1_PREBLEND
	.comm	_VPP_VD2_PREBLEND,4,2           ## @VPP_VD2_PREBLEND
	.comm	_VPP_PREBLEND_VD1_H_START_END,4,2 ## @VPP_PREBLEND_VD1_H_START_END
	.comm	_VPP_BLEND_VD2_H_START_END,4,2  ## @VPP_BLEND_VD2_H_START_END
	.comm	_VPP_OSD_SC_CTRL0,4,2           ## @VPP_OSD_SC_CTRL0
	.comm	_VPP_OSD_VSC_CTRL0,4,2          ## @VPP_OSD_VSC_CTRL0
	.comm	_VPP_OSD_HSC_CTRL0,4,2          ## @VPP_OSD_HSC_CTRL0
	.comm	_VPP_SC_VD_EN_ENABLE,4,2        ## @VPP_SC_VD_EN_ENABLE
	.comm	_VPP_SC_MISC,4,2                ## @VPP_SC_MISC
	.comm	_VPP_MINUS_BLACK_LVL_VADJ1_ENABLE,4,2 ## @VPP_MINUS_BLACK_LVL_VADJ1_ENABLE
	.comm	_VPP_VADJ_CTRL,4,2              ## @VPP_VADJ_CTRL
	.comm	_vpp_filter_coefs_4point_bspline,4,2 ## @vpp_filter_coefs_4point_bspline
	.comm	_vpp_filter_coefs_bicubic,4,2   ## @vpp_filter_coefs_bicubic
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_meson_vpp_init                 ; -- Begin function meson_vpp_init
	.p2align	2
_meson_vpp_init:                        ; @meson_vpp_init
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	mov	w20, #32896
	movk	w20, #16, lsl #16
Lloh0:
	adrp	x8, _VPU_COMPATIBLE_GXL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _VPU_COMPATIBLE_GXL@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	bl	_meson_vpu_is_compatible
Lloh3:
	adrp	x22, _VPU_COMPATIBLE_G12A@GOTPAGE
Lloh4:
	ldr	x22, [x22, _VPU_COMPATIBLE_G12A@GOTPAGEOFF]
	cbnz	x0, LBB0_3
; %bb.1:
Lloh5:
	adrp	x8, _VPU_COMPATIBLE_GXM@GOTPAGE
Lloh6:
	ldr	x8, [x8, _VPU_COMPATIBLE_GXM@GOTPAGEOFF]
Lloh7:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_11
; %bb.2:
	ldr	x21, [x19]
Lloh8:
	adrp	x8, _VIU_MISC_CTRL1@GOTPAGE
Lloh9:
	ldr	x8, [x8, _VIU_MISC_CTRL1@GOTPAGEOFF]
Lloh10:
	ldr	w0, [x8]
	bl	__REG
	add	x2, x0, x21
	mov	w0, #16711680
	mov	w1, #16711680
	bl	_writel_bits_relaxed
Lloh11:
	adrp	x8, _VPP_PPS_DUMMY_DATA_MODE@GOTPAGE
Lloh12:
	ldr	x8, [x8, _VPP_PPS_DUMMY_DATA_MODE@GOTPAGEOFF]
Lloh13:
	ldr	w21, [x8]
	ldr	x23, [x19]
Lloh14:
	adrp	x8, _VPP_DOLBY_CTRL@GOTPAGE
Lloh15:
	ldr	x8, [x8, _VPP_DOLBY_CTRL@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x23
	mov	x0, x21
	bl	_writel_relaxed
	add	w20, w20, #3864, lsl #12        ; =15826944
LBB0_3:
Lloh17:
	adrp	x8, _VPP_DUMMY_DATA1@GOTPAGE
Lloh18:
	ldr	x8, [x8, _VPP_DUMMY_DATA1@GOTPAGEOFF]
LBB0_4:
	ldr	x21, [x19]
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x21
	mov	x0, x20
	bl	_writel_relaxed
LBB0_5:
	ldr	w1, [x22]
	mov	x0, x19
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_7
; %bb.6:
Lloh19:
	adrp	x8, _VPP_OFIFO_SIZE_DEFAULT@GOTPAGE
Lloh20:
	ldr	x8, [x8, _VPP_OFIFO_SIZE_DEFAULT@GOTPAGEOFF]
Lloh21:
	ldr	w20, [x8]
	ldr	x21, [x19]
Lloh22:
	adrp	x8, _VPP_OFIFO_SIZE@GOTPAGE
Lloh23:
	ldr	x8, [x8, _VPP_OFIFO_SIZE@GOTPAGEOFF]
Lloh24:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x21
	mov	x0, x20
	bl	_writel_relaxed
	b	LBB0_8
LBB0_7:
Lloh25:
	adrp	x8, _VPP_OFIFO_SIZE_MASK@GOTPAGE
Lloh26:
	ldr	x8, [x8, _VPP_OFIFO_SIZE_MASK@GOTPAGEOFF]
Lloh27:
	ldr	w20, [x8]
	ldr	x21, [x19]
Lloh28:
	adrp	x8, _VPP_OFIFO_SIZE@GOTPAGE
Lloh29:
	ldr	x8, [x8, _VPP_OFIFO_SIZE@GOTPAGEOFF]
Lloh30:
	ldr	w0, [x8]
	bl	__REG
	add	x2, x0, x21
	mov	x0, x20
	mov	w1, #1919
	bl	_writel_bits_relaxed
LBB0_8:
	mov	w0, #4
	bl	_VPP_POSTBLEND_HOLD_LINES
	mov	x20, x0
	mov	w0, #4
	bl	_VPP_PREBLEND_HOLD_LINES
	orr	w20, w0, w20
	ldr	x21, [x19]
Lloh31:
	adrp	x8, _VPP_HOLD_LINES@GOTPAGE
Lloh32:
	ldr	x8, [x8, _VPP_HOLD_LINES@GOTPAGEOFF]
Lloh33:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x21
	mov	x0, x20
	bl	_writel_relaxed
	ldr	w1, [x22]
	mov	x0, x19
	bl	_meson_vpu_is_compatible
	cbnz	x0, LBB0_10
; %bb.9:
Lloh34:
	adrp	x8, _VPP_PREBLEND_ENABLE@GOTPAGE
Lloh35:
	ldr	x8, [x8, _VPP_PREBLEND_ENABLE@GOTPAGEOFF]
Lloh36:
	ldr	w20, [x8]
	ldr	x21, [x19]
Lloh37:
	adrp	x22, _VPP_MISC@GOTPAGE
Lloh38:
	ldr	x22, [x22, _VPP_MISC@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	__REG
	add	x2, x0, x21
	mov	x0, x20
	mov	w1, #0
	bl	_writel_bits_relaxed
Lloh39:
	adrp	x8, _VPP_POSTBLEND_ENABLE@GOTPAGE
Lloh40:
	ldr	x8, [x8, _VPP_POSTBLEND_ENABLE@GOTPAGEOFF]
Lloh41:
	ldr	w20, [x8]
	ldr	x21, [x19]
	ldr	w0, [x22]
	bl	__REG
	add	x2, x0, x21
	mov	x0, x20
	mov	w1, #0
	bl	_writel_bits_relaxed
Lloh42:
	adrp	x8, _VPP_OSD1_POSTBLEND@GOTPAGE
Lloh43:
	ldr	x8, [x8, _VPP_OSD1_POSTBLEND@GOTPAGEOFF]
Lloh44:
	ldr	w8, [x8]
Lloh45:
	adrp	x9, _VPP_OSD2_POSTBLEND@GOTPAGE
Lloh46:
	ldr	x9, [x9, _VPP_OSD2_POSTBLEND@GOTPAGEOFF]
Lloh47:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh48:
	adrp	x9, _VPP_VD1_POSTBLEND@GOTPAGE
Lloh49:
	ldr	x9, [x9, _VPP_VD1_POSTBLEND@GOTPAGEOFF]
Lloh50:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh51:
	adrp	x9, _VPP_VD2_POSTBLEND@GOTPAGE
Lloh52:
	ldr	x9, [x9, _VPP_VD2_POSTBLEND@GOTPAGEOFF]
Lloh53:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh54:
	adrp	x9, _VPP_VD1_PREBLEND@GOTPAGE
Lloh55:
	ldr	x9, [x9, _VPP_VD1_PREBLEND@GOTPAGEOFF]
Lloh56:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh57:
	adrp	x9, _VPP_VD2_PREBLEND@GOTPAGE
Lloh58:
	ldr	x9, [x9, _VPP_VD2_PREBLEND@GOTPAGEOFF]
Lloh59:
	ldr	w9, [x9]
	orr	w20, w8, w9
	ldr	x21, [x19]
	ldr	w0, [x22]
	bl	__REG
	add	x2, x0, x21
	mov	x0, x20
	mov	w1, #0
	bl	_writel_bits_relaxed
	ldr	x20, [x19]
Lloh60:
	adrp	x8, _VPP_PREBLEND_VD1_H_START_END@GOTPAGE
Lloh61:
	ldr	x8, [x8, _VPP_PREBLEND_VD1_H_START_END@GOTPAGEOFF]
Lloh62:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x20
	mov	w0, #4096
	bl	_writel_relaxed
	ldr	x20, [x19]
Lloh63:
	adrp	x8, _VPP_BLEND_VD2_H_START_END@GOTPAGE
Lloh64:
	ldr	x8, [x8, _VPP_BLEND_VD2_H_START_END@GOTPAGEOFF]
Lloh65:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x20
	mov	w0, #4096
	bl	_writel_relaxed
LBB0_10:
	ldr	x20, [x19]
Lloh66:
	adrp	x8, _VPP_OSD_SC_CTRL0@GOTPAGE
Lloh67:
	ldr	x8, [x8, _VPP_OSD_SC_CTRL0@GOTPAGEOFF]
Lloh68:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x20
	mov	w0, #0
	bl	_writel_relaxed
	ldr	x20, [x19]
Lloh69:
	adrp	x8, _VPP_OSD_VSC_CTRL0@GOTPAGE
Lloh70:
	ldr	x8, [x8, _VPP_OSD_VSC_CTRL0@GOTPAGEOFF]
Lloh71:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x20
	mov	w0, #0
	bl	_writel_relaxed
	ldr	x20, [x19]
Lloh72:
	adrp	x8, _VPP_OSD_HSC_CTRL0@GOTPAGE
Lloh73:
	ldr	x8, [x8, _VPP_OSD_HSC_CTRL0@GOTPAGEOFF]
Lloh74:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x20
	mov	w0, #0
	bl	_writel_relaxed
	mov	w0, #4
	bl	_VPP_VSC_BANK_LENGTH
	mov	x20, x0
	mov	w0, #4
	bl	_VPP_HSC_BANK_LENGTH
	orr	w8, w0, w20
Lloh75:
	adrp	x9, _VPP_SC_VD_EN_ENABLE@GOTPAGE
Lloh76:
	ldr	x9, [x9, _VPP_SC_VD_EN_ENABLE@GOTPAGEOFF]
Lloh77:
	ldr	w9, [x9]
	orr	w20, w8, w9
	ldr	x21, [x19]
Lloh78:
	adrp	x8, _VPP_SC_MISC@GOTPAGE
Lloh79:
	ldr	x8, [x8, _VPP_SC_MISC@GOTPAGEOFF]
Lloh80:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x21
	mov	x0, x20
	bl	_writel_relaxed
Lloh81:
	adrp	x8, _VPP_MINUS_BLACK_LVL_VADJ1_ENABLE@GOTPAGE
Lloh82:
	ldr	x8, [x8, _VPP_MINUS_BLACK_LVL_VADJ1_ENABLE@GOTPAGEOFF]
Lloh83:
	ldr	w20, [x8]
	ldr	x21, [x19]
Lloh84:
	adrp	x8, _VPP_VADJ_CTRL@GOTPAGE
Lloh85:
	ldr	x8, [x8, _VPP_VADJ_CTRL@GOTPAGEOFF]
Lloh86:
	ldr	w0, [x8]
	bl	__REG
	add	x1, x0, x21
	mov	x0, x20
	bl	_writel_relaxed
Lloh87:
	adrp	x20, _vpp_filter_coefs_4point_bspline@GOTPAGE
Lloh88:
	ldr	x20, [x20, _vpp_filter_coefs_4point_bspline@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	mov	w2, #0
	bl	_meson_vpp_write_scaling_filter_coefs
	ldr	w1, [x20]
	mov	x0, x19
	mov	w2, #1
	bl	_meson_vpp_write_scaling_filter_coefs
Lloh89:
	adrp	x20, _vpp_filter_coefs_bicubic@GOTPAGE
Lloh90:
	ldr	x20, [x20, _vpp_filter_coefs_bicubic@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	mov	w2, #0
	bl	_meson_vpp_write_vd_scaling_filter_coefs
	ldr	w1, [x20]
	mov	x0, x19
	mov	w2, #1
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_meson_vpp_write_vd_scaling_filter_coefs
LBB0_11:
	ldr	w1, [x22]
	mov	x0, x19
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_5
; %bb.12:
	mov	w20, #15
Lloh91:
	adrp	x8, _DOLBY_PATH_CTRL@GOTPAGE
Lloh92:
	ldr	x8, [x8, _DOLBY_PATH_CTRL@GOTPAGEOFF]
	b	LBB0_4
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh89, Lloh90
	.loh AdrpLdrGot	Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGot	Lloh91, Lloh92
	.cfi_endproc
                                        ; -- End function
	.comm	_VPU_COMPATIBLE_GXL,4,2         ; @VPU_COMPATIBLE_GXL
	.comm	_VPP_DUMMY_DATA1,4,2            ; @VPP_DUMMY_DATA1
	.comm	_VPU_COMPATIBLE_GXM,4,2         ; @VPU_COMPATIBLE_GXM
	.comm	_VIU_MISC_CTRL1,4,2             ; @VIU_MISC_CTRL1
	.comm	_VPP_PPS_DUMMY_DATA_MODE,4,2    ; @VPP_PPS_DUMMY_DATA_MODE
	.comm	_VPP_DOLBY_CTRL,4,2             ; @VPP_DOLBY_CTRL
	.comm	_VPU_COMPATIBLE_G12A,4,2        ; @VPU_COMPATIBLE_G12A
	.comm	_DOLBY_PATH_CTRL,4,2            ; @DOLBY_PATH_CTRL
	.comm	_VPP_OFIFO_SIZE_DEFAULT,4,2     ; @VPP_OFIFO_SIZE_DEFAULT
	.comm	_VPP_OFIFO_SIZE,4,2             ; @VPP_OFIFO_SIZE
	.comm	_VPP_OFIFO_SIZE_MASK,4,2        ; @VPP_OFIFO_SIZE_MASK
	.comm	_VPP_HOLD_LINES,4,2             ; @VPP_HOLD_LINES
	.comm	_VPP_PREBLEND_ENABLE,4,2        ; @VPP_PREBLEND_ENABLE
	.comm	_VPP_MISC,4,2                   ; @VPP_MISC
	.comm	_VPP_POSTBLEND_ENABLE,4,2       ; @VPP_POSTBLEND_ENABLE
	.comm	_VPP_OSD1_POSTBLEND,4,2         ; @VPP_OSD1_POSTBLEND
	.comm	_VPP_OSD2_POSTBLEND,4,2         ; @VPP_OSD2_POSTBLEND
	.comm	_VPP_VD1_POSTBLEND,4,2          ; @VPP_VD1_POSTBLEND
	.comm	_VPP_VD2_POSTBLEND,4,2          ; @VPP_VD2_POSTBLEND
	.comm	_VPP_VD1_PREBLEND,4,2           ; @VPP_VD1_PREBLEND
	.comm	_VPP_VD2_PREBLEND,4,2           ; @VPP_VD2_PREBLEND
	.comm	_VPP_PREBLEND_VD1_H_START_END,4,2 ; @VPP_PREBLEND_VD1_H_START_END
	.comm	_VPP_BLEND_VD2_H_START_END,4,2  ; @VPP_BLEND_VD2_H_START_END
	.comm	_VPP_OSD_SC_CTRL0,4,2           ; @VPP_OSD_SC_CTRL0
	.comm	_VPP_OSD_VSC_CTRL0,4,2          ; @VPP_OSD_VSC_CTRL0
	.comm	_VPP_OSD_HSC_CTRL0,4,2          ; @VPP_OSD_HSC_CTRL0
	.comm	_VPP_SC_VD_EN_ENABLE,4,2        ; @VPP_SC_VD_EN_ENABLE
	.comm	_VPP_SC_MISC,4,2                ; @VPP_SC_MISC
	.comm	_VPP_MINUS_BLACK_LVL_VADJ1_ENABLE,4,2 ; @VPP_MINUS_BLACK_LVL_VADJ1_ENABLE
	.comm	_VPP_VADJ_CTRL,4,2              ; @VPP_VADJ_CTRL
	.comm	_vpp_filter_coefs_4point_bspline,4,2 ; @vpp_filter_coefs_4point_bspline
	.comm	_vpp_filter_coefs_bicubic,4,2   ; @vpp_filter_coefs_bicubic
.subsections_via_symbols
