	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rs780_initialize_dpm_power_state
_rs780_initialize_dpm_power_state:      ## @rs780_initialize_dpm_power_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	subq	$32, %rsp
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	%rsi, %rdi
	callq	_rs780_get_ps
	movq	_COMPUTE_ENGINE_PLL_PARAM@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	(%rax), %edx
	leaq	-56(%rbp), %r8
	movq	%r15, %rdi
	xorl	%ecx, %ecx
	callq	_radeon_atom_get_clock_dividers
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	LBB0_4
## %bb.1:
	movl	-40(%rbp), %edx
	xorl	%r14d, %r14d
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_r600_engine_clock_entry_set_reference_divider
	movl	-44(%rbp), %edx
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_r600_engine_clock_entry_set_feedback_divider
	movl	-48(%rbp), %edx
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_r600_engine_clock_entry_set_post_divider
	xorl	%edx, %edx
	cmpq	$0, -56(%rbp)
	setne	%dl
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_r600_engine_clock_entry_enable_post_divider
	movq	_R600_SST_DFLT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_r600_engine_clock_entry_set_step_time
	movq	%r15, %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_r600_engine_clock_entry_enable_pulse_skipping
	movl	$1, %ebx
	movq	%r15, %rdi
	xorl	%esi, %esi
	movl	$1, %edx
	callq	_r600_engine_clock_entry_enable
	movq	_R600_PM_NUMBER_OF_SCLKS@GOTPCREL(%rip), %r12
	cmpl	$2, (%r12)
	jl	LBB0_3
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	%ebx, %esi
	xorl	%edx, %edx
	callq	_r600_engine_clock_entry_enable
	incl	%ebx
	cmpl	(%r12), %ebx
	jl	LBB0_2
LBB0_3:
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_r600_enable_mclk_control
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_r600_voltage_control_enable_pins
LBB0_4:
	movl	%r14d, %eax
	addq	$32, %rsp
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_COMPUTE_ENGINE_PLL_PARAM,4,2   ## @COMPUTE_ENGINE_PLL_PARAM
	.comm	_R600_SST_DFLT,4,2              ## @R600_SST_DFLT
	.comm	_R600_PM_NUMBER_OF_SCLKS,4,2    ## @R600_PM_NUMBER_OF_SCLKS
	.no_dead_strip	_rs780_initialize_dpm_power_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rs780_initialize_dpm_power_state
_rs780_initialize_dpm_power_state:      ; @rs780_initialize_dpm_power_state
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	mov	x0, x1
	bl	_rs780_get_ps
Lloh0:
	adrp	x8, _COMPUTE_ENGINE_PLL_PARAM@GOTPAGE
Lloh1:
	ldr	x8, [x8, _COMPUTE_ENGINE_PLL_PARAM@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	ldr	w2, [x0]
	add	x4, sp, #8
	mov	x0, x19
	mov	w3, #0
	bl	_radeon_atom_get_clock_dividers
	cbnz	w0, LBB0_5
; %bb.1:
	ldr	w2, [sp, #24]
	mov	x0, x19
	mov	w1, #0
	bl	_r600_engine_clock_entry_set_reference_divider
	ldr	w2, [sp, #20]
	mov	x0, x19
	mov	w1, #0
	bl	_r600_engine_clock_entry_set_feedback_divider
	ldr	w2, [sp, #16]
	mov	x0, x19
	mov	w1, #0
	bl	_r600_engine_clock_entry_set_post_divider
	ldr	x8, [sp, #8]
	cmp	x8, #0
	cset	w2, ne
	mov	x0, x19
	mov	w1, #0
	bl	_r600_engine_clock_entry_enable_post_divider
Lloh3:
	adrp	x8, _R600_SST_DFLT@GOTPAGE
Lloh4:
	ldr	x8, [x8, _R600_SST_DFLT@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w1, #0
	bl	_r600_engine_clock_entry_set_step_time
	mov	x0, x19
	mov	w1, #0
	mov	w2, #0
	bl	_r600_engine_clock_entry_enable_pulse_skipping
	mov	x0, x19
	mov	w1, #0
	mov	w2, #1
	bl	_r600_engine_clock_entry_enable
Lloh6:
	adrp	x21, _R600_PM_NUMBER_OF_SCLKS@GOTPAGE
Lloh7:
	ldr	x21, [x21, _R600_PM_NUMBER_OF_SCLKS@GOTPAGEOFF]
	ldr	w8, [x21]
	cmp	w8, #2
	b.lt	LBB0_4
; %bb.2:
	mov	w20, #1
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x19
	mov	x1, x20
	mov	w2, #0
	bl	_r600_engine_clock_entry_enable
	add	w20, w20, #1
	ldr	w8, [x21]
	cmp	w20, w8
	b.lt	LBB0_3
LBB0_4:
	mov	x0, x19
	mov	w1, #0
	bl	_r600_enable_mclk_control
	mov	x0, x19
	mov	w1, #0
	bl	_r600_voltage_control_enable_pins
	mov	w0, #0
LBB0_5:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_COMPUTE_ENGINE_PLL_PARAM,4,2   ; @COMPUTE_ENGINE_PLL_PARAM
	.comm	_R600_SST_DFLT,4,2              ; @R600_SST_DFLT
	.comm	_R600_PM_NUMBER_OF_SCLKS,4,2    ; @R600_PM_NUMBER_OF_SCLKS
	.no_dead_strip	_rs780_initialize_dpm_power_state
.subsections_via_symbols
