	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_uvd_ring_begin_use      ## -- Begin function amdgpu_uvd_ring_begin_use
	.p2align	4, 0x90
_amdgpu_uvd_ring_begin_use:             ## @amdgpu_uvd_ring_begin_use
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	(%rdi), %rbx
	movq	%rbx, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	jne	LBB0_4
## %bb.1:
	leaq	8(%rbx), %rdi
	callq	_cancel_delayed_work_sync
	testl	%eax, %eax
	je	LBB0_2
LBB0_4:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
LBB0_2:
	cmpq	$0, (%rbx)
	je	LBB0_3
## %bb.5:
	movq	%rbx, %rdi
	movl	$1, %esi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_amdgpu_dpm_enable_uvd          ## TAILCALL
LBB0_3:
	movq	%rbx, %rdi
	movl	$53300, %esi                    ## imm = 0xD034
	movl	$40000, %edx                    ## imm = 0x9C40
	callq	_amdgpu_asic_set_uvd_clocks
	movq	_AMD_IP_BLOCK_TYPE_UVD@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	_AMD_CG_STATE_UNGATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_amdgpu_device_ip_set_clockgating_state
	movl	(%r14), %esi
	movq	_AMD_PG_STATE_UNGATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_amdgpu_device_ip_set_powergating_state ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_IP_BLOCK_TYPE_UVD,4,2      ## @AMD_IP_BLOCK_TYPE_UVD
	.comm	_AMD_CG_STATE_UNGATE,4,2        ## @AMD_CG_STATE_UNGATE
	.comm	_AMD_PG_STATE_UNGATE,4,2        ## @AMD_PG_STATE_UNGATE
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_uvd_ring_begin_use      ; -- Begin function amdgpu_uvd_ring_begin_use
	.p2align	2
_amdgpu_uvd_ring_begin_use:             ; @amdgpu_uvd_ring_begin_use
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	x19, [x0]
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbnz	x0, LBB0_2
; %bb.1:
	add	x0, x19, #8
	bl	_cancel_delayed_work_sync
	cbz	w0, LBB0_3
LBB0_2:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_3:
	ldr	x8, [x19]
	cbz	x8, LBB0_5
; %bb.4:
	mov	x0, x19
	mov	w1, #1
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_amdgpu_dpm_enable_uvd
LBB0_5:
	mov	x0, x19
	mov	w1, #53300
	mov	w2, #40000
	bl	_amdgpu_asic_set_uvd_clocks
Lloh0:
	adrp	x20, _AMD_IP_BLOCK_TYPE_UVD@GOTPAGE
Lloh1:
	ldr	x20, [x20, _AMD_IP_BLOCK_TYPE_UVD@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh2:
	adrp	x8, _AMD_CG_STATE_UNGATE@GOTPAGE
Lloh3:
	ldr	x8, [x8, _AMD_CG_STATE_UNGATE@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_amdgpu_device_ip_set_clockgating_state
	ldr	w1, [x20]
Lloh5:
	adrp	x8, _AMD_PG_STATE_UNGATE@GOTPAGE
Lloh6:
	ldr	x8, [x8, _AMD_PG_STATE_UNGATE@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_amdgpu_device_ip_set_powergating_state
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_IP_BLOCK_TYPE_UVD,4,2      ; @AMD_IP_BLOCK_TYPE_UVD
	.comm	_AMD_CG_STATE_UNGATE,4,2        ; @AMD_CG_STATE_UNGATE
	.comm	_AMD_PG_STATE_UNGATE,4,2        ; @AMD_PG_STATE_UNGATE
.subsections_via_symbols
