	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v2_0_mc_resume_dpg_mode
_vcn_v2_0_mc_resume_dpg_mode:           ## @vcn_v2_0_mc_resume_dpg_mode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r13d
	movq	%rdi, %r12
	movq	16(%rdi), %rax
	movq	(%rax), %rdi
	addq	$4, %rdi
	callq	_AMDGPU_GPU_PAGE_ALIGN
	movl	%eax, %r15d
	movq	24(%r12), %rax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	movq	%r12, -48(%rbp)                 ## 8-byte Spill
	jne	LBB0_5
## %bb.1:
	movl	%r15d, %r14d
	movq	_UVD@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	testl	%r13d, %r13d
	je	LBB0_2
## %bb.4:
	xorl	%r15d, %r15d
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	movl	%r13d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%rbx), %edi
	movq	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	movl	%r13d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%rbx), %edi
	movq	_mmUVD_VCPU_CACHE_OFFSET0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	movl	%r13d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	jmp	LBB0_7
LBB0_5:
	movq	_UVD@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movq	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %ebx
	movq	8(%r12), %rax
	movl	(%rax), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	xorl	%edx, %edx
	movl	%r13d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%r14), %edi
	movq	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %ebx
	movq	8(%r12), %rax
	movl	(%rax), %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	xorl	%edx, %edx
	movl	%r13d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%r14), %edi
	movq	_mmUVD_VCPU_CACHE_OFFSET0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movq	_AMDGPU_UVD_FIRMWARE_OFFSET@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	sarl	$3, %esi
	movl	%eax, %edi
	xorl	%edx, %edx
	movl	%r13d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	%r15d, %ebx
	testl	%r13d, %r13d
	je	LBB0_3
## %bb.6:
	movl	%ebx, %r15d
LBB0_7:
	movq	_UVD@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_mmUVD_VCPU_CACHE_SIZE0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	movl	%r13d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%rbx), %edi
	movq	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	movl	%r13d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%rbx), %edi
	movq	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	movl	%r13d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	%r13d, %ebx
	jmp	LBB0_8
LBB0_2:
	movq	32(%r12), %rcx
	movq	_AMDGPU_UCODE_ID_VCN@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdx
	movl	(%rcx,%rdx,8), %esi
	xorl	%r15d, %r15d
	movl	%eax, %edi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%rbx), %edi
	movq	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movq	32(%r12), %rcx
	movq	_AMDGPU_UCODE_ID_VCN@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdx
	movl	4(%rcx,%rdx,8), %esi
	movl	%eax, %edi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%rbx), %edi
	movq	_mmUVD_VCPU_CACHE_OFFSET0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	%r14d, %ebx
LBB0_3:
	movq	_UVD@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movq	_mmUVD_VCPU_CACHE_SIZE0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	movl	%ebx, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%r14), %edi
	movq	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %ebx
	movq	8(%r12), %rax
	movl	(%rax), %edi
	addl	%r15d, %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%r14), %edi
	movq	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %ebx
	movq	8(%r12), %rax
	movl	(%rax), %edi
	addl	%r15d, %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	xorl	%ebx, %ebx
	movl	%eax, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
LBB0_8:
	movq	_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	%rax, %r14
	movq	_mmUVD_VCPU_CACHE_OFFSET1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	movl	%ebx, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%r14), %edi
	movq	%r14, %rbx
	movq	_mmUVD_VCPU_CACHE_SIZE1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movq	_AMDGPU_VCN_STACK_SIZE@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movl	%eax, %edi
	xorl	%edx, %edx
	movl	%r13d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%rbx), %edi
	movq	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %ebx
	movq	-48(%rbp), %r12                 ## 8-byte Reload
	movq	8(%r12), %rax
	movl	(%rax), %edi
	addl	%r15d, %edi
	addl	(%r14), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	xorl	%edx, %edx
	movl	%r13d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movq	_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %ebx
	movq	8(%r12), %rax
	addl	(%rax), %r15d
	addl	(%r14), %r15d
	movl	%r15d, %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	xorl	%edx, %edx
	movl	%r13d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movq	_UVD@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_mmUVD_VCPU_CACHE_OFFSET2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	movl	%r13d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%rbx), %edi
	movq	_mmUVD_VCPU_CACHE_SIZE2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movq	_AMDGPU_VCN_CONTEXT_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	xorl	%edx, %edx
	movl	%r13d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%rbx), %edi
	movq	_mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	movl	%r13d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%rbx), %edi
	movq	_mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	movl	%r13d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%rbx), %edi
	movq	_mmUVD_VCPU_NONCACHE_OFFSET0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	movl	%r13d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%rbx), %edi
	movq	_mmUVD_VCPU_NONCACHE_SIZE0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	movl	%r13d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%rbx), %edi
	movq	_mmUVD_GFX10_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	(%r12), %esi
	movl	%eax, %edi
	xorl	%edx, %edx
	movl	%r13d, %ecx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_SOC15_DPG_MODE_2_0      ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
	.comm	_AMDGPU_UCODE_ID_VCN,8,3        ## @AMDGPU_UCODE_ID_VCN
	.comm	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET0,4,2   ## @mmUVD_VCPU_CACHE_OFFSET0
	.comm	_AMDGPU_UVD_FIRMWARE_OFFSET,4,2 ## @AMDGPU_UVD_FIRMWARE_OFFSET
	.comm	_mmUVD_VCPU_CACHE_SIZE0,4,2     ## @mmUVD_VCPU_CACHE_SIZE0
	.comm	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET1,4,2   ## @mmUVD_VCPU_CACHE_OFFSET1
	.comm	_mmUVD_VCPU_CACHE_SIZE1,4,2     ## @mmUVD_VCPU_CACHE_SIZE1
	.comm	_AMDGPU_VCN_STACK_SIZE,4,2      ## @AMDGPU_VCN_STACK_SIZE
	.comm	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET2,4,2   ## @mmUVD_VCPU_CACHE_OFFSET2
	.comm	_mmUVD_VCPU_CACHE_SIZE2,4,2     ## @mmUVD_VCPU_CACHE_SIZE2
	.comm	_AMDGPU_VCN_CONTEXT_SIZE,4,2    ## @AMDGPU_VCN_CONTEXT_SIZE
	.comm	_mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_NONCACHE_OFFSET0,4,2 ## @mmUVD_VCPU_NONCACHE_OFFSET0
	.comm	_mmUVD_VCPU_NONCACHE_SIZE0,4,2  ## @mmUVD_VCPU_NONCACHE_SIZE0
	.comm	_mmUVD_GFX10_ADDR_CONFIG,4,2    ## @mmUVD_GFX10_ADDR_CONFIG
	.no_dead_strip	_vcn_v2_0_mc_resume_dpg_mode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v2_0_mc_resume_dpg_mode
_vcn_v2_0_mc_resume_dpg_mode:           ; @vcn_v2_0_mc_resume_dpg_mode
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x1
	mov	x20, x0
	ldr	x8, [x0, #16]
	ldr	x8, [x8]
	add	x0, x8, #4
	bl	_AMDGPU_GPU_PAGE_ALIGN
	mov	x21, x0
	ldr	x8, [x20, #24]
Lloh0:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
Lloh3:
	adrp	x23, _UVD@GOTPAGE
Lloh4:
	ldr	x23, [x23, _UVD@GOTPAGEOFF]
	cmp	x8, x9
	b.ne	LBB0_3
; %bb.1:
	ldr	w0, [x23]
Lloh5:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW@GOTPAGE
Lloh6:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	cbz	w19, LBB0_5
; %bb.2:
	mov	w1, #0
	mov	w2, #0
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh8:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPAGE
Lloh9:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	w1, #0
	mov	w2, #0
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh11:
	adrp	x8, _mmUVD_VCPU_CACHE_OFFSET0@GOTPAGE
Lloh12:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_OFFSET0@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	w1, #0
	mov	w2, #0
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	mov	w21, #0
	b	LBB0_4
LBB0_3:
	ldr	w0, [x23]
Lloh14:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW@GOTPAGE
Lloh15:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	x22, x0
	ldr	x8, [x20, #8]
	ldr	w0, [x8]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x22
	mov	w2, #0
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh17:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPAGE
Lloh18:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh19:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	x22, x0
	ldr	x8, [x20, #8]
	ldr	w0, [x8]
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x22
	mov	w2, #0
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh20:
	adrp	x8, _mmUVD_VCPU_CACHE_OFFSET0@GOTPAGE
Lloh21:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_OFFSET0@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
Lloh23:
	adrp	x8, _AMDGPU_UVD_FIRMWARE_OFFSET@GOTPAGE
Lloh24:
	ldr	x8, [x8, _AMDGPU_UVD_FIRMWARE_OFFSET@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
	asr	w1, w8, #3
	mov	w2, #0
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	mov	x24, x21
	cbz	w19, LBB0_6
LBB0_4:
	ldr	w0, [x23]
Lloh26:
	adrp	x8, _mmUVD_VCPU_CACHE_SIZE0@GOTPAGE
Lloh27:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_SIZE0@GOTPAGEOFF]
Lloh28:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	w1, #0
	mov	w2, #0
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh29:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW@GOTPAGE
Lloh30:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh31:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	w1, #0
	mov	w2, #0
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh32:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH@GOTPAGE
Lloh33:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh34:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	w1, #0
	mov	w2, #0
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	mov	x22, x19
	b	LBB0_7
LBB0_5:
	ldr	x8, [x20, #32]
Lloh35:
	adrp	x22, _AMDGPU_UCODE_ID_VCN@GOTPAGE
Lloh36:
	ldr	x22, [x22, _AMDGPU_UCODE_ID_VCN@GOTPAGEOFF]
	ldr	x9, [x22]
	lsl	x9, x9, #3
	ldr	w1, [x8, x9]
	mov	w2, #0
	mov	w3, #0
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh37:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPAGE
Lloh38:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh39:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	ldr	x8, [x20, #32]
	ldr	x9, [x22]
	add	x8, x8, x9, lsl #3
	ldr	w1, [x8, #4]
	mov	w2, #0
	mov	w3, #0
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh40:
	adrp	x8, _mmUVD_VCPU_CACHE_OFFSET0@GOTPAGE
Lloh41:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_OFFSET0@GOTPAGEOFF]
Lloh42:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	w1, #0
	mov	w2, #0
	mov	w3, #0
	bl	_WREG32_SOC15_DPG_MODE_2_0
	mov	w24, #0
LBB0_6:
	ldr	w0, [x23]
Lloh43:
	adrp	x8, _mmUVD_VCPU_CACHE_SIZE0@GOTPAGE
Lloh44:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_SIZE0@GOTPAGEOFF]
Lloh45:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	x1, x21
	mov	w2, #0
	mov	w3, #0
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh46:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW@GOTPAGE
Lloh47:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh48:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	x21, x0
	ldr	x8, [x20, #8]
	ldr	w8, [x8]
	add	w0, w8, w24
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x21
	mov	w2, #0
	mov	w3, #0
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh49:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH@GOTPAGE
Lloh50:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh51:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	x21, x0
	ldr	x8, [x20, #8]
	ldr	w8, [x8]
	add	w0, w8, w24
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x21
	mov	w2, #0
	mov	w3, #0
	bl	_WREG32_SOC15_DPG_MODE_2_0
	mov	w22, #0
	mov	x21, x24
LBB0_7:
	ldr	w0, [x23]
Lloh52:
	adrp	x8, _mmUVD_VCPU_CACHE_OFFSET1@GOTPAGE
Lloh53:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_OFFSET1@GOTPAGEOFF]
Lloh54:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	w1, #0
	mov	w2, #0
	mov	x3, x22
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh55:
	adrp	x8, _mmUVD_VCPU_CACHE_SIZE1@GOTPAGE
Lloh56:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_SIZE1@GOTPAGEOFF]
Lloh57:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
Lloh58:
	adrp	x24, _AMDGPU_VCN_STACK_SIZE@GOTPAGE
Lloh59:
	ldr	x24, [x24, _AMDGPU_VCN_STACK_SIZE@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	w2, #0
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh60:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW@GOTPAGE
Lloh61:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh62:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	x22, x0
	ldr	x8, [x20, #8]
	ldr	w8, [x8]
	ldr	w9, [x24]
	add	w8, w8, w21
	add	w0, w8, w9
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x22
	mov	w2, #0
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh63:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH@GOTPAGE
Lloh64:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh65:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	x22, x0
	ldr	x8, [x20, #8]
	ldr	w8, [x8]
	ldr	w9, [x24]
	add	w8, w8, w21
	add	w0, w8, w9
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x22
	mov	w2, #0
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh66:
	adrp	x8, _mmUVD_VCPU_CACHE_OFFSET2@GOTPAGE
Lloh67:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_OFFSET2@GOTPAGEOFF]
Lloh68:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	w1, #0
	mov	w2, #0
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh69:
	adrp	x8, _mmUVD_VCPU_CACHE_SIZE2@GOTPAGE
Lloh70:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_SIZE2@GOTPAGEOFF]
Lloh71:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
Lloh72:
	adrp	x8, _AMDGPU_VCN_CONTEXT_SIZE@GOTPAGE
Lloh73:
	ldr	x8, [x8, _AMDGPU_VCN_CONTEXT_SIZE@GOTPAGEOFF]
Lloh74:
	ldr	w1, [x8]
	mov	w2, #0
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh75:
	adrp	x8, _mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW@GOTPAGE
Lloh76:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh77:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	w1, #0
	mov	w2, #0
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh78:
	adrp	x8, _mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH@GOTPAGE
Lloh79:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh80:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	w1, #0
	mov	w2, #0
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh81:
	adrp	x8, _mmUVD_VCPU_NONCACHE_OFFSET0@GOTPAGE
Lloh82:
	ldr	x8, [x8, _mmUVD_VCPU_NONCACHE_OFFSET0@GOTPAGEOFF]
Lloh83:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	w1, #0
	mov	w2, #0
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh84:
	adrp	x8, _mmUVD_VCPU_NONCACHE_SIZE0@GOTPAGE
Lloh85:
	ldr	x8, [x8, _mmUVD_VCPU_NONCACHE_SIZE0@GOTPAGEOFF]
Lloh86:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	w1, #0
	mov	w2, #0
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x23]
Lloh87:
	adrp	x8, _mmUVD_GFX10_ADDR_CONFIG@GOTPAGE
Lloh88:
	ldr	x8, [x8, _mmUVD_GFX10_ADDR_CONFIG@GOTPAGEOFF]
Lloh89:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	ldr	w1, [x20]
	mov	w2, #0
	mov	x3, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_WREG32_SOC15_DPG_MODE_2_0
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
	.comm	_AMDGPU_UCODE_ID_VCN,8,3        ; @AMDGPU_UCODE_ID_VCN
	.comm	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET0,4,2   ; @mmUVD_VCPU_CACHE_OFFSET0
	.comm	_AMDGPU_UVD_FIRMWARE_OFFSET,4,2 ; @AMDGPU_UVD_FIRMWARE_OFFSET
	.comm	_mmUVD_VCPU_CACHE_SIZE0,4,2     ; @mmUVD_VCPU_CACHE_SIZE0
	.comm	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET1,4,2   ; @mmUVD_VCPU_CACHE_OFFSET1
	.comm	_mmUVD_VCPU_CACHE_SIZE1,4,2     ; @mmUVD_VCPU_CACHE_SIZE1
	.comm	_AMDGPU_VCN_STACK_SIZE,4,2      ; @AMDGPU_VCN_STACK_SIZE
	.comm	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET2,4,2   ; @mmUVD_VCPU_CACHE_OFFSET2
	.comm	_mmUVD_VCPU_CACHE_SIZE2,4,2     ; @mmUVD_VCPU_CACHE_SIZE2
	.comm	_AMDGPU_VCN_CONTEXT_SIZE,4,2    ; @AMDGPU_VCN_CONTEXT_SIZE
	.comm	_mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_NONCACHE_OFFSET0,4,2 ; @mmUVD_VCPU_NONCACHE_OFFSET0
	.comm	_mmUVD_VCPU_NONCACHE_SIZE0,4,2  ; @mmUVD_VCPU_NONCACHE_SIZE0
	.comm	_mmUVD_GFX10_ADDR_CONFIG,4,2    ; @mmUVD_GFX10_ADDR_CONFIG
	.no_dead_strip	_vcn_v2_0_mc_resume_dpg_mode
.subsections_via_symbols
