	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_display_crtc_idx_to_irq_type ## -- Begin function amdgpu_display_crtc_idx_to_irq_type
	.p2align	4, 0x90
_amdgpu_display_crtc_idx_to_irq_type:   ## @amdgpu_display_crtc_idx_to_irq_type
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	_AMDGPU_CRTC_IRQ_NONE@GOTPCREL(%rip), %rax
	testl	%esi, %esi
	js	LBB0_4
## %bb.1:
	cmpl	%esi, (%rdi)
	jle	LBB0_4
## %bb.2:
	cmpl	$5, %esi
	ja	LBB0_4
## %bb.3:
	movslq	%esi, %rax
	leaq	l_switch.table.amdgpu_display_crtc_idx_to_irq_type(%rip), %rcx
	movq	(%rcx,%rax,8), %rax
LBB0_4:
	movl	(%rax), %eax
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_CRTC_IRQ_NONE,4,2       ## @AMDGPU_CRTC_IRQ_NONE
	.comm	_AMDGPU_CRTC_IRQ_VBLANK1,4,2    ## @AMDGPU_CRTC_IRQ_VBLANK1
	.comm	_AMDGPU_CRTC_IRQ_VBLANK2,4,2    ## @AMDGPU_CRTC_IRQ_VBLANK2
	.comm	_AMDGPU_CRTC_IRQ_VBLANK3,4,2    ## @AMDGPU_CRTC_IRQ_VBLANK3
	.comm	_AMDGPU_CRTC_IRQ_VBLANK4,4,2    ## @AMDGPU_CRTC_IRQ_VBLANK4
	.comm	_AMDGPU_CRTC_IRQ_VBLANK5,4,2    ## @AMDGPU_CRTC_IRQ_VBLANK5
	.comm	_AMDGPU_CRTC_IRQ_VBLANK6,4,2    ## @AMDGPU_CRTC_IRQ_VBLANK6
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.amdgpu_display_crtc_idx_to_irq_type
l_switch.table.amdgpu_display_crtc_idx_to_irq_type:
	.quad	_AMDGPU_CRTC_IRQ_VBLANK1
	.quad	_AMDGPU_CRTC_IRQ_VBLANK2
	.quad	_AMDGPU_CRTC_IRQ_VBLANK3
	.quad	_AMDGPU_CRTC_IRQ_VBLANK4
	.quad	_AMDGPU_CRTC_IRQ_VBLANK5
	.quad	_AMDGPU_CRTC_IRQ_VBLANK6

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_display_crtc_idx_to_irq_type ; -- Begin function amdgpu_display_crtc_idx_to_irq_type
	.p2align	2
_amdgpu_display_crtc_idx_to_irq_type:   ; @amdgpu_display_crtc_idx_to_irq_type
	.cfi_startproc
; %bb.0:
	tbnz	w1, #31, LBB0_2
; %bb.1:
	ldr	w8, [x0]
	cmp	w8, w1
	ccmp	w1, #5, #2, gt
	b.ls	LBB0_3
LBB0_2:
Lloh0:
	adrp	x8, _AMDGPU_CRTC_IRQ_NONE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPU_CRTC_IRQ_NONE@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	ret
LBB0_3:
Lloh3:
	adrp	x8, l_switch.table.amdgpu_display_crtc_idx_to_irq_type@PAGE
Lloh4:
	add	x8, x8, l_switch.table.amdgpu_display_crtc_idx_to_irq_type@PAGEOFF
	ldr	x8, [x8, w1, sxtw #3]
	ldr	w0, [x8]
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_CRTC_IRQ_NONE,4,2       ; @AMDGPU_CRTC_IRQ_NONE
	.comm	_AMDGPU_CRTC_IRQ_VBLANK1,4,2    ; @AMDGPU_CRTC_IRQ_VBLANK1
	.comm	_AMDGPU_CRTC_IRQ_VBLANK2,4,2    ; @AMDGPU_CRTC_IRQ_VBLANK2
	.comm	_AMDGPU_CRTC_IRQ_VBLANK3,4,2    ; @AMDGPU_CRTC_IRQ_VBLANK3
	.comm	_AMDGPU_CRTC_IRQ_VBLANK4,4,2    ; @AMDGPU_CRTC_IRQ_VBLANK4
	.comm	_AMDGPU_CRTC_IRQ_VBLANK5,4,2    ; @AMDGPU_CRTC_IRQ_VBLANK5
	.comm	_AMDGPU_CRTC_IRQ_VBLANK6,4,2    ; @AMDGPU_CRTC_IRQ_VBLANK6
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.amdgpu_display_crtc_idx_to_irq_type
l_switch.table.amdgpu_display_crtc_idx_to_irq_type:
	.quad	_AMDGPU_CRTC_IRQ_VBLANK1
	.quad	_AMDGPU_CRTC_IRQ_VBLANK2
	.quad	_AMDGPU_CRTC_IRQ_VBLANK3
	.quad	_AMDGPU_CRTC_IRQ_VBLANK4
	.quad	_AMDGPU_CRTC_IRQ_VBLANK5
	.quad	_AMDGPU_CRTC_IRQ_VBLANK6

.subsections_via_symbols
