	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_dcn20_hw_sequencer_construct   ## -- Begin function dcn20_hw_sequencer_construct
	.p2align	4, 0x90
_dcn20_hw_sequencer_construct:          ## @dcn20_hw_sequencer_construct
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	callq	_dcn10_hw_sequencer_construct
	movq	_dcn20_unblank_stream@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 160(%rbx)
	movq	_dcn20_update_plane_addr@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 156(%rbx)
	movq	_dcn20_enable_stream_timing@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 152(%rbx)
	movq	_dcn20_program_tripleBuffer@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 148(%rbx)
	movq	_dcn20_set_input_transfer_func@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 144(%rbx)
	movq	_dcn20_set_output_transfer_func@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 140(%rbx)
	movq	_dcn20_apply_ctx_for_surface@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 136(%rbx)
	movq	_dcn20_pipe_control_lock@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 132(%rbx)
	movq	_dcn20_pipe_control_lock_global@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 128(%rbx)
	movq	_dcn20_optimize_bandwidth@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 124(%rbx)
	movq	_dcn20_prepare_bandwidth@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 120(%rbx)
	movq	_dcn20_update_bandwidth@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 116(%rbx)
	movq	_dcn20_enable_writeback@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 112(%rbx)
	movq	_dcn20_disable_writeback@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 108(%rbx)
	movq	_dcn20_program_output_csc@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 104(%rbx)
	movq	_dcn20_update_odm@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 100(%rbx)
	movq	_dcn20_blank_pixel_data@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 96(%rbx)
	movq	_dcn20_dmdata_status_done@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 92(%rbx)
	movq	_dcn20_program_dmdata_engine@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 88(%rbx)
	movq	_dcn20_enable_stream@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 84(%rbx)
	movq	_dcn20_disable_stream@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 80(%rbx)
	movq	_dcn20_init_sys_ctx@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 76(%rbx)
	movq	_dcn20_init_vm_ctx@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 72(%rbx)
	movq	_dcn20_disable_stream_gating@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 68(%rbx)
	movq	_dcn20_enable_stream_gating@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 64(%rbx)
	movq	_dcn20_setup_vupdate_interrupt@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 60(%rbx)
	movq	_dcn20_reset_hw_ctx_wrap@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 56(%rbx)
	movq	_dcn20_update_mpcc@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 52(%rbx)
	movq	_dcn20_set_flip_control_gsl@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 48(%rbx)
	movq	_dcn20_init_blank@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 44(%rbx)
	movq	_dcn20_disable_plane@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 40(%rbx)
	movq	_dcn20_plane_atomic_disable@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 36(%rbx)
	movq	_dcn20_enable_power_gating_plane@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 32(%rbx)
	movq	_dcn20_dpp_pg_control@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 28(%rbx)
	movq	_dcn20_hubp_pg_control@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 24(%rbx)
	movq	$0, 16(%rbx)
	movq	_dcn20_disable_vga@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 12(%rbx)
	movq	168(%rbx), %rax
	movl	(%rax), %edi
	callq	_IS_FPGA_MAXIMUS_DC
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	_dcn20_fpga_init_hw@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 8(%rbx)
	movq	$0, (%rbx)
LBB0_2:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_dcn20_unblank_stream,4,2       ## @dcn20_unblank_stream
	.comm	_dcn20_update_plane_addr,4,2    ## @dcn20_update_plane_addr
	.comm	_dcn20_enable_stream_timing,4,2 ## @dcn20_enable_stream_timing
	.comm	_dcn20_program_tripleBuffer,4,2 ## @dcn20_program_tripleBuffer
	.comm	_dcn20_set_input_transfer_func,4,2 ## @dcn20_set_input_transfer_func
	.comm	_dcn20_set_output_transfer_func,4,2 ## @dcn20_set_output_transfer_func
	.comm	_dcn20_apply_ctx_for_surface,4,2 ## @dcn20_apply_ctx_for_surface
	.comm	_dcn20_pipe_control_lock,4,2    ## @dcn20_pipe_control_lock
	.comm	_dcn20_pipe_control_lock_global,4,2 ## @dcn20_pipe_control_lock_global
	.comm	_dcn20_optimize_bandwidth,4,2   ## @dcn20_optimize_bandwidth
	.comm	_dcn20_prepare_bandwidth,4,2    ## @dcn20_prepare_bandwidth
	.comm	_dcn20_update_bandwidth,4,2     ## @dcn20_update_bandwidth
	.comm	_dcn20_enable_writeback,4,2     ## @dcn20_enable_writeback
	.comm	_dcn20_disable_writeback,4,2    ## @dcn20_disable_writeback
	.comm	_dcn20_program_output_csc,4,2   ## @dcn20_program_output_csc
	.comm	_dcn20_update_odm,4,2           ## @dcn20_update_odm
	.comm	_dcn20_blank_pixel_data,4,2     ## @dcn20_blank_pixel_data
	.comm	_dcn20_dmdata_status_done,4,2   ## @dcn20_dmdata_status_done
	.comm	_dcn20_program_dmdata_engine,4,2 ## @dcn20_program_dmdata_engine
	.comm	_dcn20_enable_stream,4,2        ## @dcn20_enable_stream
	.comm	_dcn20_disable_stream,4,2       ## @dcn20_disable_stream
	.comm	_dcn20_init_sys_ctx,4,2         ## @dcn20_init_sys_ctx
	.comm	_dcn20_init_vm_ctx,4,2          ## @dcn20_init_vm_ctx
	.comm	_dcn20_disable_stream_gating,4,2 ## @dcn20_disable_stream_gating
	.comm	_dcn20_enable_stream_gating,4,2 ## @dcn20_enable_stream_gating
	.comm	_dcn20_setup_vupdate_interrupt,4,2 ## @dcn20_setup_vupdate_interrupt
	.comm	_dcn20_reset_hw_ctx_wrap,4,2    ## @dcn20_reset_hw_ctx_wrap
	.comm	_dcn20_update_mpcc,4,2          ## @dcn20_update_mpcc
	.comm	_dcn20_set_flip_control_gsl,4,2 ## @dcn20_set_flip_control_gsl
	.comm	_dcn20_init_blank,4,2           ## @dcn20_init_blank
	.comm	_dcn20_disable_plane,4,2        ## @dcn20_disable_plane
	.comm	_dcn20_plane_atomic_disable,4,2 ## @dcn20_plane_atomic_disable
	.comm	_dcn20_enable_power_gating_plane,4,2 ## @dcn20_enable_power_gating_plane
	.comm	_dcn20_dpp_pg_control,4,2       ## @dcn20_dpp_pg_control
	.comm	_dcn20_hubp_pg_control,4,2      ## @dcn20_hubp_pg_control
	.comm	_dcn20_disable_vga,4,2          ## @dcn20_disable_vga
	.comm	_dcn20_fpga_init_hw,4,2         ## @dcn20_fpga_init_hw
	.comm	_dcn20_dsc_pg_control,8,3       ## @dcn20_dsc_pg_control
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_dcn20_hw_sequencer_construct   ; -- Begin function dcn20_hw_sequencer_construct
	.p2align	2
_dcn20_hw_sequencer_construct:          ; @dcn20_hw_sequencer_construct
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_dcn10_hw_sequencer_construct
Lloh0:
	adrp	x8, _dcn20_unblank_stream@GOTPAGE
Lloh1:
	ldr	x8, [x8, _dcn20_unblank_stream@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	str	w8, [x19, #160]
Lloh3:
	adrp	x8, _dcn20_update_plane_addr@GOTPAGE
Lloh4:
	ldr	x8, [x8, _dcn20_update_plane_addr@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
Lloh6:
	adrp	x9, _dcn20_enable_stream_timing@GOTPAGE
Lloh7:
	ldr	x9, [x9, _dcn20_enable_stream_timing@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #152]
Lloh9:
	adrp	x8, _dcn20_program_tripleBuffer@GOTPAGE
Lloh10:
	ldr	x8, [x8, _dcn20_program_tripleBuffer@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
Lloh12:
	adrp	x9, _dcn20_set_input_transfer_func@GOTPAGE
Lloh13:
	ldr	x9, [x9, _dcn20_set_input_transfer_func@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
Lloh15:
	adrp	x10, _dcn20_set_output_transfer_func@GOTPAGE
Lloh16:
	ldr	x10, [x10, _dcn20_set_output_transfer_func@GOTPAGEOFF]
	stp	w9, w8, [x19, #144]
Lloh17:
	ldr	w8, [x10]
Lloh18:
	adrp	x9, _dcn20_apply_ctx_for_surface@GOTPAGE
Lloh19:
	ldr	x9, [x9, _dcn20_apply_ctx_for_surface@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #136]
Lloh21:
	adrp	x8, _dcn20_pipe_control_lock@GOTPAGE
Lloh22:
	ldr	x8, [x8, _dcn20_pipe_control_lock@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
Lloh24:
	adrp	x9, _dcn20_pipe_control_lock_global@GOTPAGE
Lloh25:
	ldr	x9, [x9, _dcn20_pipe_control_lock_global@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #128]
Lloh27:
	adrp	x8, _dcn20_optimize_bandwidth@GOTPAGE
Lloh28:
	ldr	x8, [x8, _dcn20_optimize_bandwidth@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
Lloh30:
	adrp	x9, _dcn20_prepare_bandwidth@GOTPAGE
Lloh31:
	ldr	x9, [x9, _dcn20_prepare_bandwidth@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
Lloh33:
	adrp	x10, _dcn20_update_bandwidth@GOTPAGE
Lloh34:
	ldr	x10, [x10, _dcn20_update_bandwidth@GOTPAGEOFF]
	stp	w9, w8, [x19, #120]
Lloh35:
	ldr	w8, [x10]
Lloh36:
	adrp	x9, _dcn20_enable_writeback@GOTPAGE
Lloh37:
	ldr	x9, [x9, _dcn20_enable_writeback@GOTPAGEOFF]
Lloh38:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #112]
Lloh39:
	adrp	x8, _dcn20_disable_writeback@GOTPAGE
Lloh40:
	ldr	x8, [x8, _dcn20_disable_writeback@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
Lloh42:
	adrp	x9, _dcn20_program_output_csc@GOTPAGE
Lloh43:
	ldr	x9, [x9, _dcn20_program_output_csc@GOTPAGEOFF]
Lloh44:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #104]
Lloh45:
	adrp	x8, _dcn20_update_odm@GOTPAGE
Lloh46:
	ldr	x8, [x8, _dcn20_update_odm@GOTPAGEOFF]
Lloh47:
	ldr	w8, [x8]
Lloh48:
	adrp	x9, _dcn20_blank_pixel_data@GOTPAGE
Lloh49:
	ldr	x9, [x9, _dcn20_blank_pixel_data@GOTPAGEOFF]
Lloh50:
	ldr	w9, [x9]
Lloh51:
	adrp	x10, _dcn20_dmdata_status_done@GOTPAGE
Lloh52:
	ldr	x10, [x10, _dcn20_dmdata_status_done@GOTPAGEOFF]
	stp	w9, w8, [x19, #96]
Lloh53:
	ldr	w8, [x10]
Lloh54:
	adrp	x9, _dcn20_program_dmdata_engine@GOTPAGE
Lloh55:
	ldr	x9, [x9, _dcn20_program_dmdata_engine@GOTPAGEOFF]
Lloh56:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #88]
Lloh57:
	adrp	x8, _dcn20_enable_stream@GOTPAGE
Lloh58:
	ldr	x8, [x8, _dcn20_enable_stream@GOTPAGEOFF]
Lloh59:
	ldr	w8, [x8]
Lloh60:
	adrp	x9, _dcn20_disable_stream@GOTPAGE
Lloh61:
	ldr	x9, [x9, _dcn20_disable_stream@GOTPAGEOFF]
Lloh62:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #80]
Lloh63:
	adrp	x8, _dcn20_init_sys_ctx@GOTPAGE
Lloh64:
	ldr	x8, [x8, _dcn20_init_sys_ctx@GOTPAGEOFF]
Lloh65:
	ldr	w8, [x8]
Lloh66:
	adrp	x9, _dcn20_init_vm_ctx@GOTPAGE
Lloh67:
	ldr	x9, [x9, _dcn20_init_vm_ctx@GOTPAGEOFF]
Lloh68:
	ldr	w9, [x9]
Lloh69:
	adrp	x10, _dcn20_disable_stream_gating@GOTPAGE
Lloh70:
	ldr	x10, [x10, _dcn20_disable_stream_gating@GOTPAGEOFF]
	stp	w9, w8, [x19, #72]
Lloh71:
	ldr	w8, [x10]
Lloh72:
	adrp	x9, _dcn20_enable_stream_gating@GOTPAGE
Lloh73:
	ldr	x9, [x9, _dcn20_enable_stream_gating@GOTPAGEOFF]
Lloh74:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #64]
Lloh75:
	adrp	x8, _dcn20_setup_vupdate_interrupt@GOTPAGE
Lloh76:
	ldr	x8, [x8, _dcn20_setup_vupdate_interrupt@GOTPAGEOFF]
Lloh77:
	ldr	w8, [x8]
Lloh78:
	adrp	x9, _dcn20_reset_hw_ctx_wrap@GOTPAGE
Lloh79:
	ldr	x9, [x9, _dcn20_reset_hw_ctx_wrap@GOTPAGEOFF]
Lloh80:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #56]
Lloh81:
	adrp	x8, _dcn20_update_mpcc@GOTPAGE
Lloh82:
	ldr	x8, [x8, _dcn20_update_mpcc@GOTPAGEOFF]
Lloh83:
	ldr	w8, [x8]
Lloh84:
	adrp	x9, _dcn20_set_flip_control_gsl@GOTPAGE
Lloh85:
	ldr	x9, [x9, _dcn20_set_flip_control_gsl@GOTPAGEOFF]
Lloh86:
	ldr	w9, [x9]
Lloh87:
	adrp	x10, _dcn20_init_blank@GOTPAGE
Lloh88:
	ldr	x10, [x10, _dcn20_init_blank@GOTPAGEOFF]
	stp	w9, w8, [x19, #48]
Lloh89:
	ldr	w8, [x10]
Lloh90:
	adrp	x9, _dcn20_disable_plane@GOTPAGE
Lloh91:
	ldr	x9, [x9, _dcn20_disable_plane@GOTPAGEOFF]
Lloh92:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #40]
Lloh93:
	adrp	x8, _dcn20_plane_atomic_disable@GOTPAGE
Lloh94:
	ldr	x8, [x8, _dcn20_plane_atomic_disable@GOTPAGEOFF]
Lloh95:
	ldr	w8, [x8]
Lloh96:
	adrp	x9, _dcn20_enable_power_gating_plane@GOTPAGE
Lloh97:
	ldr	x9, [x9, _dcn20_enable_power_gating_plane@GOTPAGEOFF]
Lloh98:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #32]
Lloh99:
	adrp	x8, _dcn20_dpp_pg_control@GOTPAGE
Lloh100:
	ldr	x8, [x8, _dcn20_dpp_pg_control@GOTPAGEOFF]
Lloh101:
	ldr	w8, [x8]
Lloh102:
	adrp	x9, _dcn20_hubp_pg_control@GOTPAGE
Lloh103:
	ldr	x9, [x9, _dcn20_hubp_pg_control@GOTPAGEOFF]
Lloh104:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #24]
	str	xzr, [x19, #16]
Lloh105:
	adrp	x8, _dcn20_disable_vga@GOTPAGE
Lloh106:
	ldr	x8, [x8, _dcn20_disable_vga@GOTPAGEOFF]
Lloh107:
	ldr	w8, [x8]
	str	w8, [x19, #12]
	ldr	x8, [x19, #168]
	ldr	w0, [x8]
	bl	_IS_FPGA_MAXIMUS_DC
	cbz	x0, LBB0_2
; %bb.1:
Lloh108:
	adrp	x8, _dcn20_fpga_init_hw@GOTPAGE
Lloh109:
	ldr	x8, [x8, _dcn20_fpga_init_hw@GOTPAGEOFF]
Lloh110:
	ldr	w8, [x8]
	str	w8, [x19, #8]
	str	xzr, [x19]
LBB0_2:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.cfi_endproc
                                        ; -- End function
	.comm	_dcn20_unblank_stream,4,2       ; @dcn20_unblank_stream
	.comm	_dcn20_update_plane_addr,4,2    ; @dcn20_update_plane_addr
	.comm	_dcn20_enable_stream_timing,4,2 ; @dcn20_enable_stream_timing
	.comm	_dcn20_program_tripleBuffer,4,2 ; @dcn20_program_tripleBuffer
	.comm	_dcn20_set_input_transfer_func,4,2 ; @dcn20_set_input_transfer_func
	.comm	_dcn20_set_output_transfer_func,4,2 ; @dcn20_set_output_transfer_func
	.comm	_dcn20_apply_ctx_for_surface,4,2 ; @dcn20_apply_ctx_for_surface
	.comm	_dcn20_pipe_control_lock,4,2    ; @dcn20_pipe_control_lock
	.comm	_dcn20_pipe_control_lock_global,4,2 ; @dcn20_pipe_control_lock_global
	.comm	_dcn20_optimize_bandwidth,4,2   ; @dcn20_optimize_bandwidth
	.comm	_dcn20_prepare_bandwidth,4,2    ; @dcn20_prepare_bandwidth
	.comm	_dcn20_update_bandwidth,4,2     ; @dcn20_update_bandwidth
	.comm	_dcn20_enable_writeback,4,2     ; @dcn20_enable_writeback
	.comm	_dcn20_disable_writeback,4,2    ; @dcn20_disable_writeback
	.comm	_dcn20_program_output_csc,4,2   ; @dcn20_program_output_csc
	.comm	_dcn20_update_odm,4,2           ; @dcn20_update_odm
	.comm	_dcn20_blank_pixel_data,4,2     ; @dcn20_blank_pixel_data
	.comm	_dcn20_dmdata_status_done,4,2   ; @dcn20_dmdata_status_done
	.comm	_dcn20_program_dmdata_engine,4,2 ; @dcn20_program_dmdata_engine
	.comm	_dcn20_enable_stream,4,2        ; @dcn20_enable_stream
	.comm	_dcn20_disable_stream,4,2       ; @dcn20_disable_stream
	.comm	_dcn20_init_sys_ctx,4,2         ; @dcn20_init_sys_ctx
	.comm	_dcn20_init_vm_ctx,4,2          ; @dcn20_init_vm_ctx
	.comm	_dcn20_disable_stream_gating,4,2 ; @dcn20_disable_stream_gating
	.comm	_dcn20_enable_stream_gating,4,2 ; @dcn20_enable_stream_gating
	.comm	_dcn20_setup_vupdate_interrupt,4,2 ; @dcn20_setup_vupdate_interrupt
	.comm	_dcn20_reset_hw_ctx_wrap,4,2    ; @dcn20_reset_hw_ctx_wrap
	.comm	_dcn20_update_mpcc,4,2          ; @dcn20_update_mpcc
	.comm	_dcn20_set_flip_control_gsl,4,2 ; @dcn20_set_flip_control_gsl
	.comm	_dcn20_init_blank,4,2           ; @dcn20_init_blank
	.comm	_dcn20_disable_plane,4,2        ; @dcn20_disable_plane
	.comm	_dcn20_plane_atomic_disable,4,2 ; @dcn20_plane_atomic_disable
	.comm	_dcn20_enable_power_gating_plane,4,2 ; @dcn20_enable_power_gating_plane
	.comm	_dcn20_dpp_pg_control,4,2       ; @dcn20_dpp_pg_control
	.comm	_dcn20_hubp_pg_control,4,2      ; @dcn20_hubp_pg_control
	.comm	_dcn20_disable_vga,4,2          ; @dcn20_disable_vga
	.comm	_dcn20_fpga_init_hw,4,2         ; @dcn20_fpga_init_hw
	.comm	_dcn20_dsc_pg_control,8,3       ; @dcn20_dsc_pg_control
.subsections_via_symbols
