	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_irq_kms_enable_hpd      ## -- Begin function radeon_irq_kms_enable_hpd
	.p2align	4, 0x90
_radeon_irq_kms_enable_hpd:             ## @radeon_irq_kms_enable_hpd
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	16(%rdi), %rax
	cmpl	$0, (%rax)
	je	LBB0_5
## %bb.1:
	movl	%esi, %ebx
	movq	%rdi, %r14
	leaq	8(%rdi), %r15
	movq	%r15, %rdi
	callq	_spin_lock_irqsave
	movq	_RADEON_MAX_HPD_PINS@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	jle	LBB0_4
## %bb.2:
	movq	(%r14), %rcx
	xorl	%edx, %edx
	.p2align	4, 0x90
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	xorl	%esi, %esi
	btl	%edx, %ebx
	setb	%sil
	orl	%esi, (%rcx,%rdx,4)
	incq	%rdx
	movslq	(%rax), %rsi
	cmpq	%rsi, %rdx
	jl	LBB0_3
LBB0_4:
	movq	%r14, %rdi
	callq	_radeon_irq_set
	movq	%r15, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_spin_unlock_irqrestore         ## TAILCALL
LBB0_5:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_MAX_HPD_PINS,4,2        ## @RADEON_MAX_HPD_PINS
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_irq_kms_enable_hpd      ; -- Begin function radeon_irq_kms_enable_hpd
	.p2align	2
_radeon_irq_kms_enable_hpd:             ; @radeon_irq_kms_enable_hpd
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	ldr	x8, [x0, #16]
	ldr	w8, [x8]
	cbz	w8, LBB0_5
; %bb.1:
	mov	x20, x1
	mov	x19, x0
	add	x21, x0, #8
	mov	x0, x21
	bl	_spin_lock_irqsave
Lloh0:
	adrp	x8, _RADEON_MAX_HPD_PINS@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_MAX_HPD_PINS@GOTPAGEOFF]
	ldr	w9, [x8]
	cmp	w9, #1
	b.lt	LBB0_4
; %bb.2:
	mov	x9, #0
	ldr	x10, [x19]
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	lsr	w11, w20, w9
	and	w11, w11, #0x1
	lsl	x12, x9, #2
	ldr	w13, [x10, x12]
	orr	w11, w13, w11
	str	w11, [x10, x12]
	add	x9, x9, #1
	ldrsw	x11, [x8]
	cmp	x9, x11
	b.lt	LBB0_3
LBB0_4:
	mov	x0, x19
	bl	_radeon_irq_set
	mov	x0, x21
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_spin_unlock_irqrestore
LBB0_5:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_MAX_HPD_PINS,4,2        ; @RADEON_MAX_HPD_PINS
.subsections_via_symbols
