	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v8_0_init_compute_vmid
_gfx_v8_0_init_compute_vmid:            ## @gfx_v8_0_init_compute_vmid
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_DEFAULT_SH_MEM_BASES@GOTPCREL(%rip), %rax
	movq	_SH_MEM_ADDRESS_MODE_HSA64@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_SH_MEM_CONFIG__ADDRESS_MODE__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	movl	(%rax), %r13d
	movq	_SH_MEM_ALIGNMENT_MODE_UNALIGNED@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	orl	%edx, %eax
	movq	_MTYPE_CC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r15d
	movq	_SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r15d
	orl	%eax, %r15d
	movq	_SH_MEM_CONFIG__PRIVATE_ATC_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %r15d
	callq	_mutex_lock
	movq	_FIRST_COMPUTE_VMID@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_LAST_COMPUTE_VMID@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	jge	LBB0_3
## %bb.1:
	movl	%r13d, %r12d
	shll	$16, %r12d
	orl	%r13d, %r12d
	movq	_mmSH_MEM_BASES@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	movl	%ebx, %r8d
	callq	_vi_srbm_select
	movq	_mmSH_MEM_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movq	_mmSH_MEM_APE1_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_WREG32
	movq	_mmSH_MEM_APE1_LIMIT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r13), %edi
	movl	%r12d, %esi
	callq	_WREG32
	incl	%ebx
	movq	_LAST_COMPUTE_VMID@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	jl	LBB0_2
LBB0_3:
	movq	%r14, %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	xorl	%r8d, %r8d
	callq	_vi_srbm_select
	movq	%r14, %rdi
	callq	_mutex_unlock
	movq	_FIRST_COMPUTE_VMID@GOTPCREL(%rip), %rax
	movslq	(%rax), %r14
	movq	_LAST_COMPUTE_VMID@GOTPCREL(%rip), %r12
	cmpl	(%r12), %r14d
	jge	LBB0_6
## %bb.4:
	movq	%r14, %rbx
	shlq	$4, %rbx
	movq	_amdgpu_gds_reg_offset@GOTPCREL(%rip), %r15
	.p2align	4, 0x90
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	movq	(%r15), %rax
	movl	12(%rax,%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%r15), %rax
	movl	8(%rax,%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%r15), %rax
	movl	4(%rax,%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%r15), %rax
	movl	(%rax,%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	incq	%r14
	movslq	(%r12), %rax
	addq	$16, %rbx
	cmpq	%rax, %r14
	jl	LBB0_5
LBB0_6:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DEFAULT_SH_MEM_BASES,4,2       ## @DEFAULT_SH_MEM_BASES
	.comm	_SH_MEM_ADDRESS_MODE_HSA64,4,2  ## @SH_MEM_ADDRESS_MODE_HSA64
	.comm	_SH_MEM_CONFIG__ADDRESS_MODE__SHIFT,4,2 ## @SH_MEM_CONFIG__ADDRESS_MODE__SHIFT
	.comm	_SH_MEM_ALIGNMENT_MODE_UNALIGNED,4,2 ## @SH_MEM_ALIGNMENT_MODE_UNALIGNED
	.comm	_SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT,4,2 ## @SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT
	.comm	_MTYPE_CC,4,2                   ## @MTYPE_CC
	.comm	_SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT,4,2 ## @SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT
	.comm	_SH_MEM_CONFIG__PRIVATE_ATC_MASK,4,2 ## @SH_MEM_CONFIG__PRIVATE_ATC_MASK
	.comm	_FIRST_COMPUTE_VMID,4,2         ## @FIRST_COMPUTE_VMID
	.comm	_LAST_COMPUTE_VMID,4,2          ## @LAST_COMPUTE_VMID
	.comm	_mmSH_MEM_CONFIG,4,2            ## @mmSH_MEM_CONFIG
	.comm	_mmSH_MEM_APE1_BASE,4,2         ## @mmSH_MEM_APE1_BASE
	.comm	_mmSH_MEM_APE1_LIMIT,4,2        ## @mmSH_MEM_APE1_LIMIT
	.comm	_mmSH_MEM_BASES,4,2             ## @mmSH_MEM_BASES
	.comm	_amdgpu_gds_reg_offset,8,3      ## @amdgpu_gds_reg_offset
	.no_dead_strip	_gfx_v8_0_init_compute_vmid
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v8_0_init_compute_vmid
_gfx_v8_0_init_compute_vmid:            ; @gfx_v8_0_init_compute_vmid
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
Lloh0:
	adrp	x8, _DEFAULT_SH_MEM_BASES@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DEFAULT_SH_MEM_BASES@GOTPAGEOFF]
Lloh2:
	ldr	w21, [x8]
Lloh3:
	adrp	x8, _SH_MEM_ADDRESS_MODE_HSA64@GOTPAGE
Lloh4:
	ldr	x8, [x8, _SH_MEM_ADDRESS_MODE_HSA64@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	str	w8, [sp, #12]                   ; 4-byte Folded Spill
Lloh6:
	adrp	x8, _SH_MEM_CONFIG__ADDRESS_MODE__SHIFT@GOTPAGE
Lloh7:
	ldr	x8, [x8, _SH_MEM_CONFIG__ADDRESS_MODE__SHIFT@GOTPAGEOFF]
Lloh8:
	ldr	w27, [x8]
Lloh9:
	adrp	x8, _SH_MEM_ALIGNMENT_MODE_UNALIGNED@GOTPAGE
Lloh10:
	ldr	x8, [x8, _SH_MEM_ALIGNMENT_MODE_UNALIGNED@GOTPAGEOFF]
Lloh11:
	ldr	w25, [x8]
Lloh12:
	adrp	x8, _SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT@GOTPAGE
Lloh13:
	ldr	x8, [x8, _SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT@GOTPAGEOFF]
Lloh14:
	ldr	w28, [x8]
Lloh15:
	adrp	x8, _MTYPE_CC@GOTPAGE
Lloh16:
	ldr	x8, [x8, _MTYPE_CC@GOTPAGEOFF]
Lloh17:
	ldr	w26, [x8]
Lloh18:
	adrp	x8, _SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT@GOTPAGE
Lloh19:
	ldr	x8, [x8, _SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT@GOTPAGEOFF]
Lloh20:
	ldr	w24, [x8]
Lloh21:
	adrp	x8, _SH_MEM_CONFIG__PRIVATE_ATC_MASK@GOTPAGE
Lloh22:
	ldr	x8, [x8, _SH_MEM_CONFIG__PRIVATE_ATC_MASK@GOTPAGEOFF]
Lloh23:
	ldr	w22, [x8]
	bl	_mutex_lock
Lloh24:
	adrp	x8, _FIRST_COMPUTE_VMID@GOTPAGE
Lloh25:
	ldr	x8, [x8, _FIRST_COMPUTE_VMID@GOTPAGEOFF]
Lloh26:
	ldr	w20, [x8]
Lloh27:
	adrp	x23, _LAST_COMPUTE_VMID@GOTPAGE
Lloh28:
	ldr	x23, [x23, _LAST_COMPUTE_VMID@GOTPAGEOFF]
	ldr	w8, [x23]
	cmp	w20, w8
	b.ge	LBB0_3
; %bb.1:
	orr	w21, w21, w21, lsl #16
	ldr	w8, [sp, #12]                   ; 4-byte Folded Reload
	lsl	w8, w8, w27
	lsl	w9, w25, w28
	orr	w8, w9, w8
	lsl	w9, w26, w24
	orr	w8, w8, w9
	orr	w22, w8, w22
Lloh29:
	adrp	x25, _mmSH_MEM_CONFIG@GOTPAGE
Lloh30:
	ldr	x25, [x25, _mmSH_MEM_CONFIG@GOTPAGEOFF]
Lloh31:
	adrp	x26, _mmSH_MEM_APE1_BASE@GOTPAGE
Lloh32:
	ldr	x26, [x26, _mmSH_MEM_APE1_BASE@GOTPAGEOFF]
Lloh33:
	adrp	x27, _mmSH_MEM_APE1_LIMIT@GOTPAGE
Lloh34:
	ldr	x27, [x27, _mmSH_MEM_APE1_LIMIT@GOTPAGEOFF]
Lloh35:
	adrp	x28, _mmSH_MEM_BASES@GOTPAGE
Lloh36:
	ldr	x28, [x28, _mmSH_MEM_BASES@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x19
	mov	w1, #0
	mov	w2, #0
	mov	w3, #0
	mov	x4, x20
	bl	_vi_srbm_select
	ldr	w0, [x25]
	mov	x1, x22
	bl	_WREG32
	ldr	w0, [x26]
	mov	w1, #1
	bl	_WREG32
	ldr	w0, [x27]
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x28]
	mov	x1, x21
	bl	_WREG32
	add	w20, w20, #1
	ldr	w8, [x23]
	cmp	w20, w8
	b.lt	LBB0_2
LBB0_3:
	mov	x0, x19
	mov	w1, #0
	mov	w2, #0
	mov	w3, #0
	mov	w4, #0
	bl	_vi_srbm_select
	mov	x0, x19
	bl	_mutex_unlock
Lloh37:
	adrp	x8, _FIRST_COMPUTE_VMID@GOTPAGE
Lloh38:
	ldr	x8, [x8, _FIRST_COMPUTE_VMID@GOTPAGEOFF]
Lloh39:
	ldrsw	x19, [x8]
	ldr	w8, [x23]
	cmp	w19, w8
	b.ge	LBB0_6
; %bb.4:
	lsl	x20, x19, #4
Lloh40:
	adrp	x21, _amdgpu_gds_reg_offset@GOTPAGE
Lloh41:
	ldr	x21, [x21, _amdgpu_gds_reg_offset@GOTPAGEOFF]
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x21]
	add	x8, x8, x20
	ldr	w0, [x8, #12]
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x21]
	add	x8, x8, x20
	ldr	w0, [x8, #8]
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x21]
	add	x8, x8, x20
	ldr	w0, [x8, #4]
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x21]
	ldr	w0, [x8, x20]
	mov	w1, #0
	bl	_WREG32
	add	x19, x19, #1
	ldrsw	x8, [x23]
	add	x20, x20, #16
	cmp	x19, x8
	b.lt	LBB0_5
LBB0_6:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh40, Lloh41
	.cfi_endproc
                                        ; -- End function
	.comm	_DEFAULT_SH_MEM_BASES,4,2       ; @DEFAULT_SH_MEM_BASES
	.comm	_SH_MEM_ADDRESS_MODE_HSA64,4,2  ; @SH_MEM_ADDRESS_MODE_HSA64
	.comm	_SH_MEM_CONFIG__ADDRESS_MODE__SHIFT,4,2 ; @SH_MEM_CONFIG__ADDRESS_MODE__SHIFT
	.comm	_SH_MEM_ALIGNMENT_MODE_UNALIGNED,4,2 ; @SH_MEM_ALIGNMENT_MODE_UNALIGNED
	.comm	_SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT,4,2 ; @SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT
	.comm	_MTYPE_CC,4,2                   ; @MTYPE_CC
	.comm	_SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT,4,2 ; @SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT
	.comm	_SH_MEM_CONFIG__PRIVATE_ATC_MASK,4,2 ; @SH_MEM_CONFIG__PRIVATE_ATC_MASK
	.comm	_FIRST_COMPUTE_VMID,4,2         ; @FIRST_COMPUTE_VMID
	.comm	_LAST_COMPUTE_VMID,4,2          ; @LAST_COMPUTE_VMID
	.comm	_mmSH_MEM_CONFIG,4,2            ; @mmSH_MEM_CONFIG
	.comm	_mmSH_MEM_APE1_BASE,4,2         ; @mmSH_MEM_APE1_BASE
	.comm	_mmSH_MEM_APE1_LIMIT,4,2        ; @mmSH_MEM_APE1_LIMIT
	.comm	_mmSH_MEM_BASES,4,2             ; @mmSH_MEM_BASES
	.comm	_amdgpu_gds_reg_offset,8,3      ; @amdgpu_gds_reg_offset
	.no_dead_strip	_gfx_v8_0_init_compute_vmid
.subsections_via_symbols
