	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_vcn_ring_begin_use      ## -- Begin function amdgpu_vcn_ring_begin_use
	.p2align	4, 0x90
_amdgpu_vcn_ring_begin_use:             ## @amdgpu_vcn_ring_begin_use
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	16(%rdi), %r15
	leaq	40(%r15), %rdi
	callq	_cancel_delayed_work_sync
	testl	%eax, %eax
	jne	LBB0_5
## %bb.1:
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_gfx_off_ctrl
	movq	(%r15), %rax
	movq	_CHIP_ARCTURUS@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_4
## %bb.2:
	cmpq	$0, 48(%r15)
	je	LBB0_4
## %bb.3:
	movq	%r15, %rdi
	movl	$1, %esi
	callq	_amdgpu_dpm_enable_uvd
	jmp	LBB0_5
LBB0_4:
	movq	_AMD_IP_BLOCK_TYPE_VCN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AMD_PG_STATE_UNGATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_amdgpu_device_ip_set_powergating_state
LBB0_5:
	movq	_AMD_PG_SUPPORT_VCN_DPG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 8(%r15)
	je	LBB0_20
## %bb.6:
	cmpl	$0, 16(%r15)
	je	LBB0_11
## %bb.7:
	xorl	%r13d, %r13d
	xorl	%ebx, %ebx
	xorl	%r12d, %r12d
	.p2align	4, 0x90
LBB0_8:                                 ## =>This Inner Loop Header: Depth=1
	movq	32(%r15), %rax
	movq	(%r14), %rcx
	shlq	$4, %rcx
	movq	8(%rax,%rcx), %rdi
	addq	%r13, %rdi
	callq	_amdgpu_fence_count_emitted
	addl	%eax, %r12d
	incq	%rbx
	movl	16(%r15), %eax
	addq	$4, %r13
	cmpq	%rax, %rbx
	jb	LBB0_8
## %bb.9:
	testl	%r12d, %r12d
	je	LBB0_11
## %bb.10:
	movq	_VCN_DPG_STATE__PAUSE@GOTPCREL(%rip), %rax
	jmp	LBB0_12
LBB0_11:
	movq	_VCN_DPG_STATE__UNPAUSE@GOTPCREL(%rip), %rax
LBB0_12:
	movq	(%rax), %rax
	movq	%rax, -48(%rbp)
	movq	(%r14), %rdi
	shlq	$4, %rdi
	addq	32(%r15), %rdi
	callq	_amdgpu_fence_count_emitted
	testq	%rax, %rax
	jne	LBB0_13
## %bb.14:
	movq	_VCN_DPG_STATE__UNPAUSE@GOTPCREL(%rip), %rax
	jmp	LBB0_15
LBB0_13:
	movq	_VCN_DPG_STATE__PAUSE@GOTPCREL(%rip), %rax
LBB0_15:
	movq	(%rax), %rax
	movq	%rax, -56(%rbp)
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movq	_AMDGPU_RING_TYPE_VCN_ENC@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_17
## %bb.16:
	movq	_VCN_DPG_STATE__PAUSE@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -48(%rbp)
	jmp	LBB0_19
LBB0_17:
	movq	_AMDGPU_RING_TYPE_VCN_JPEG@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_19
## %bb.18:
	movq	_VCN_DPG_STATE__PAUSE@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -56(%rbp)
LBB0_19:
	leaq	-56(%rbp), %rsi
	movq	%r15, %rdi
	callq	*24(%r15)
LBB0_20:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CHIP_ARCTURUS,8,3              ## @CHIP_ARCTURUS
	.comm	_AMD_IP_BLOCK_TYPE_VCN,4,2      ## @AMD_IP_BLOCK_TYPE_VCN
	.comm	_AMD_PG_STATE_UNGATE,4,2        ## @AMD_PG_STATE_UNGATE
	.comm	_AMD_PG_SUPPORT_VCN_DPG,4,2     ## @AMD_PG_SUPPORT_VCN_DPG
	.comm	_VCN_DPG_STATE__PAUSE,8,3       ## @VCN_DPG_STATE__PAUSE
	.comm	_VCN_DPG_STATE__UNPAUSE,8,3     ## @VCN_DPG_STATE__UNPAUSE
	.comm	_AMDGPU_RING_TYPE_VCN_ENC,8,3   ## @AMDGPU_RING_TYPE_VCN_ENC
	.comm	_AMDGPU_RING_TYPE_VCN_JPEG,8,3  ## @AMDGPU_RING_TYPE_VCN_JPEG
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_vcn_ring_begin_use      ; -- Begin function amdgpu_vcn_ring_begin_use
	.p2align	2
_amdgpu_vcn_ring_begin_use:             ; @amdgpu_vcn_ring_begin_use
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x0
	ldr	x19, [x0, #16]
	add	x0, x19, #40
	bl	_cancel_delayed_work_sync
	cbnz	w0, LBB0_5
; %bb.1:
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_gfx_off_ctrl
	ldr	x8, [x19]
Lloh0:
	adrp	x9, _CHIP_ARCTURUS@GOTPAGE
Lloh1:
	ldr	x9, [x9, _CHIP_ARCTURUS@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_4
; %bb.2:
	ldr	x8, [x19, #48]
	cbz	x8, LBB0_4
; %bb.3:
	mov	x0, x19
	mov	w1, #1
	bl	_amdgpu_dpm_enable_uvd
	b	LBB0_5
LBB0_4:
Lloh3:
	adrp	x8, _AMD_IP_BLOCK_TYPE_VCN@GOTPAGE
Lloh4:
	ldr	x8, [x8, _AMD_IP_BLOCK_TYPE_VCN@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
Lloh6:
	adrp	x8, _AMD_PG_STATE_UNGATE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _AMD_PG_STATE_UNGATE@GOTPAGEOFF]
Lloh8:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_amdgpu_device_ip_set_powergating_state
LBB0_5:
	ldr	w8, [x19, #8]
Lloh9:
	adrp	x9, _AMD_PG_SUPPORT_VCN_DPG@GOTPAGE
Lloh10:
	ldr	x9, [x9, _AMD_PG_SUPPORT_VCN_DPG@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_17
; %bb.6:
	ldr	w8, [x19, #16]
Lloh12:
	adrp	x21, _VCN_DPG_STATE__PAUSE@GOTPAGE
Lloh13:
	ldr	x21, [x21, _VCN_DPG_STATE__PAUSE@GOTPAGEOFF]
	cbz	w8, LBB0_11
; %bb.7:
	mov	x22, #0
	mov	x24, #0
	mov	w23, #0
LBB0_8:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #32]
	ldr	x9, [x20]
	add	x8, x8, x9, lsl #4
	ldr	x8, [x8, #8]
	add	x0, x8, x22
	bl	_amdgpu_fence_count_emitted
	add	w23, w23, w0
	add	x24, x24, #1
	ldr	w8, [x19, #16]
	add	x22, x22, #4
	cmp	x24, x8
	b.lo	LBB0_8
; %bb.9:
	cbz	w23, LBB0_11
; %bb.10:
Lloh14:
	adrp	x8, _VCN_DPG_STATE__PAUSE@GOTPAGE
Lloh15:
	ldr	x8, [x8, _VCN_DPG_STATE__PAUSE@GOTPAGEOFF]
	b	LBB0_12
LBB0_11:
Lloh16:
	adrp	x8, _VCN_DPG_STATE__UNPAUSE@GOTPAGE
Lloh17:
	ldr	x8, [x8, _VCN_DPG_STATE__UNPAUSE@GOTPAGEOFF]
LBB0_12:
	ldr	x8, [x8]
	str	x8, [sp, #8]
	ldr	x8, [x19, #32]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #4
	bl	_amdgpu_fence_count_emitted
Lloh18:
	adrp	x8, _VCN_DPG_STATE__UNPAUSE@GOTPAGE
Lloh19:
	ldr	x8, [x8, _VCN_DPG_STATE__UNPAUSE@GOTPAGEOFF]
	cmp	x0, #0
	csel	x8, x8, x21, eq
	ldr	x8, [x8]
	str	x8, [sp]
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
Lloh20:
	adrp	x9, _AMDGPU_RING_TYPE_VCN_ENC@GOTPAGE
Lloh21:
	ldr	x9, [x9, _AMDGPU_RING_TYPE_VCN_ENC@GOTPAGEOFF]
Lloh22:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_14
; %bb.13:
	ldr	x8, [x21]
	str	x8, [sp, #8]
	b	LBB0_16
LBB0_14:
Lloh23:
	adrp	x9, _AMDGPU_RING_TYPE_VCN_JPEG@GOTPAGE
Lloh24:
	ldr	x9, [x9, _AMDGPU_RING_TYPE_VCN_JPEG@GOTPAGEOFF]
Lloh25:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_16
; %bb.15:
	ldr	x8, [x21]
	str	x8, [sp]
LBB0_16:
	ldr	x8, [x19, #24]
	mov	x1, sp
	mov	x0, x19
	blr	x8
LBB0_17:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.cfi_endproc
                                        ; -- End function
	.comm	_CHIP_ARCTURUS,8,3              ; @CHIP_ARCTURUS
	.comm	_AMD_IP_BLOCK_TYPE_VCN,4,2      ; @AMD_IP_BLOCK_TYPE_VCN
	.comm	_AMD_PG_STATE_UNGATE,4,2        ; @AMD_PG_STATE_UNGATE
	.comm	_AMD_PG_SUPPORT_VCN_DPG,4,2     ; @AMD_PG_SUPPORT_VCN_DPG
	.comm	_VCN_DPG_STATE__PAUSE,8,3       ; @VCN_DPG_STATE__PAUSE
	.comm	_VCN_DPG_STATE__UNPAUSE,8,3     ; @VCN_DPG_STATE__UNPAUSE
	.comm	_AMDGPU_RING_TYPE_VCN_ENC,8,3   ; @AMDGPU_RING_TYPE_VCN_ENC
	.comm	_AMDGPU_RING_TYPE_VCN_JPEG,8,3  ; @AMDGPU_RING_TYPE_VCN_JPEG
.subsections_via_symbols
