	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ingenic_drm_encoder_atomic_mode_set
_ingenic_drm_encoder_atomic_mode_set:   ## @ingenic_drm_encoder_atomic_mode_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdx, %rbx
	movq	%rsi, %r14
	callq	_drm_encoder_get_priv
	movq	(%rbx), %r8
	movl	8(%r8), %edi
	movq	_DRM_BUS_FLAG_SHARP_SIGNALS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	andl	%edi, %esi
	movl	%esi, (%rax)
	je	LBB0_2
## %bb.1:
	movq	_JZ_LCD_CFG_REV_POLARITY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	_JZ_LCD_CFG_MODE_SPECIAL_TFT_1@GOTPCREL(%rip), %rbx
	jmp	LBB0_3
LBB0_2:
	movq	_JZ_LCD_CFG_PS_DISABLE@GOTPCREL(%rip), %rdx
	movq	_JZ_LCD_CFG_CLS_DISABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rdx), %ecx
	movq	_JZ_LCD_CFG_SPL_DISABLE@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_JZ_LCD_CFG_REV_DISABLE@GOTPCREL(%rip), %rbx
LBB0_3:
	movl	(%r14), %r9d
	movq	_DRM_MODE_FLAG_NHSYNC@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	andl	%r9d, %edx
	je	LBB0_5
## %bb.4:
	movq	_JZ_LCD_CFG_HSYNC_ACTIVE_LOW@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
LBB0_5:
	orl	(%rbx), %ecx
	movq	_DRM_MODE_FLAG_NVSYNC@GOTPCREL(%rip), %rbx
	movl	(%rbx), %ebx
	andl	%r9d, %ebx
	je	LBB0_7
## %bb.6:
	movq	_JZ_LCD_CFG_VSYNC_ACTIVE_LOW@GOTPCREL(%rip), %rbx
	movl	(%rbx), %ebx
LBB0_7:
	orl	%ecx, %edx
	movq	_DRM_BUS_FLAG_DE_LOW@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%edi, %ecx
	je	LBB0_9
## %bb.8:
	movq	_JZ_LCD_CFG_DE_ACTIVE_LOW@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_9:
	orl	%ecx, %ebx
	orl	%ebx, %edx
	movq	_DRM_BUS_FLAG_PIXDATA_NEGEDGE@GOTPCREL(%rip), %rcx
	andl	(%rcx), %edi
	je	LBB0_11
## %bb.10:
	movq	_JZ_LCD_CFG_PCLK_FALLING_EDGE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
LBB0_11:
	orl	%edi, %edx
	testl	%esi, %esi
	jne	LBB0_23
## %bb.12:
	movq	(%r8), %rcx
	movq	_DRM_MODE_CONNECTOR_TV@GOTPCREL(%rip), %rsi
	cmpq	(%rsi), %rcx
	jne	LBB0_16
## %bb.13:
	movq	_DRM_MODE_FLAG_INTERLACE@GOTPCREL(%rip), %rcx
	testl	%r9d, (%rcx)
	je	LBB0_15
## %bb.14:
	movq	_JZ_LCD_CFG_MODE_TV_OUT_I@GOTPCREL(%rip), %rcx
	jmp	LBB0_22
LBB0_16:
	movq	16(%r8), %rcx
	movl	(%rcx), %ecx
	addl	$-128, %ecx
	cmpl	$3, %ecx
	ja	LBB0_23
## %bb.17:
	leaq	LJTI0_0(%rip), %rsi
	movslq	(%rsi,%rcx,4), %rcx
	addq	%rsi, %rcx
	jmpq	*%rcx
LBB0_21:
	movq	_JZ_LCD_CFG_MODE_8BIT_SERIAL@GOTPCREL(%rip), %rcx
	jmp	LBB0_22
LBB0_15:
	movq	_JZ_LCD_CFG_MODE_TV_OUT_P@GOTPCREL(%rip), %rcx
	jmp	LBB0_22
LBB0_20:
	movq	_JZ_LCD_CFG_MODE_GENERIC_24BIT@GOTPCREL(%rip), %rcx
	jmp	LBB0_22
LBB0_19:
	movq	_JZ_LCD_CFG_MODE_GENERIC_18BIT@GOTPCREL(%rip), %rcx
	jmp	LBB0_22
LBB0_18:
	movq	_JZ_LCD_CFG_MODE_GENERIC_16BIT@GOTPCREL(%rip), %rcx
LBB0_22:
	orl	(%rcx), %edx
LBB0_23:
	movl	4(%rax), %edi
	movq	_JZ_REG_LCD_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_regmap_write                   ## TAILCALL
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_21, LBB0_21-LJTI0_0
.set L0_0_set_20, LBB0_20-LJTI0_0
.set L0_0_set_19, LBB0_19-LJTI0_0
.set L0_0_set_18, LBB0_18-LJTI0_0
LJTI0_0:
	.long	L0_0_set_21
	.long	L0_0_set_20
	.long	L0_0_set_19
	.long	L0_0_set_18
	.end_data_region
                                        ## -- End function
	.comm	_DRM_BUS_FLAG_SHARP_SIGNALS,4,2 ## @DRM_BUS_FLAG_SHARP_SIGNALS
	.comm	_JZ_LCD_CFG_MODE_SPECIAL_TFT_1,4,2 ## @JZ_LCD_CFG_MODE_SPECIAL_TFT_1
	.comm	_JZ_LCD_CFG_REV_POLARITY,4,2    ## @JZ_LCD_CFG_REV_POLARITY
	.comm	_JZ_LCD_CFG_PS_DISABLE,4,2      ## @JZ_LCD_CFG_PS_DISABLE
	.comm	_JZ_LCD_CFG_CLS_DISABLE,4,2     ## @JZ_LCD_CFG_CLS_DISABLE
	.comm	_JZ_LCD_CFG_SPL_DISABLE,4,2     ## @JZ_LCD_CFG_SPL_DISABLE
	.comm	_JZ_LCD_CFG_REV_DISABLE,4,2     ## @JZ_LCD_CFG_REV_DISABLE
	.comm	_DRM_MODE_FLAG_NHSYNC,4,2       ## @DRM_MODE_FLAG_NHSYNC
	.comm	_JZ_LCD_CFG_HSYNC_ACTIVE_LOW,4,2 ## @JZ_LCD_CFG_HSYNC_ACTIVE_LOW
	.comm	_DRM_MODE_FLAG_NVSYNC,4,2       ## @DRM_MODE_FLAG_NVSYNC
	.comm	_JZ_LCD_CFG_VSYNC_ACTIVE_LOW,4,2 ## @JZ_LCD_CFG_VSYNC_ACTIVE_LOW
	.comm	_DRM_BUS_FLAG_DE_LOW,4,2        ## @DRM_BUS_FLAG_DE_LOW
	.comm	_JZ_LCD_CFG_DE_ACTIVE_LOW,4,2   ## @JZ_LCD_CFG_DE_ACTIVE_LOW
	.comm	_DRM_BUS_FLAG_PIXDATA_NEGEDGE,4,2 ## @DRM_BUS_FLAG_PIXDATA_NEGEDGE
	.comm	_JZ_LCD_CFG_PCLK_FALLING_EDGE,4,2 ## @JZ_LCD_CFG_PCLK_FALLING_EDGE
	.comm	_DRM_MODE_CONNECTOR_TV,8,3      ## @DRM_MODE_CONNECTOR_TV
	.comm	_DRM_MODE_FLAG_INTERLACE,4,2    ## @DRM_MODE_FLAG_INTERLACE
	.comm	_JZ_LCD_CFG_MODE_TV_OUT_I,4,2   ## @JZ_LCD_CFG_MODE_TV_OUT_I
	.comm	_JZ_LCD_CFG_MODE_TV_OUT_P,4,2   ## @JZ_LCD_CFG_MODE_TV_OUT_P
	.comm	_JZ_LCD_CFG_MODE_GENERIC_16BIT,4,2 ## @JZ_LCD_CFG_MODE_GENERIC_16BIT
	.comm	_JZ_LCD_CFG_MODE_GENERIC_18BIT,4,2 ## @JZ_LCD_CFG_MODE_GENERIC_18BIT
	.comm	_JZ_LCD_CFG_MODE_GENERIC_24BIT,4,2 ## @JZ_LCD_CFG_MODE_GENERIC_24BIT
	.comm	_JZ_LCD_CFG_MODE_8BIT_SERIAL,4,2 ## @JZ_LCD_CFG_MODE_8BIT_SERIAL
	.comm	_JZ_REG_LCD_CFG,4,2             ## @JZ_REG_LCD_CFG
	.no_dead_strip	_ingenic_drm_encoder_atomic_mode_set
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ingenic_drm_encoder_atomic_mode_set
_ingenic_drm_encoder_atomic_mode_set:   ; @ingenic_drm_encoder_atomic_mode_set
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x20, x2
	mov	x19, x1
	bl	_drm_encoder_get_priv
	ldr	x8, [x20]
	ldr	w10, [x8, #8]
Lloh0:
	adrp	x9, _DRM_BUS_FLAG_SHARP_SIGNALS@GOTPAGE
Lloh1:
	ldr	x9, [x9, _DRM_BUS_FLAG_SHARP_SIGNALS@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	ands	w9, w9, w10
	str	w9, [x0]
	b.eq	LBB0_2
; %bb.1:
Lloh3:
	adrp	x11, _JZ_LCD_CFG_REV_POLARITY@GOTPAGE
Lloh4:
	ldr	x11, [x11, _JZ_LCD_CFG_REV_POLARITY@GOTPAGEOFF]
Lloh5:
	ldr	w11, [x11]
Lloh6:
	adrp	x12, _JZ_LCD_CFG_MODE_SPECIAL_TFT_1@GOTPAGE
Lloh7:
	ldr	x12, [x12, _JZ_LCD_CFG_MODE_SPECIAL_TFT_1@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:
Lloh8:
	adrp	x11, _JZ_LCD_CFG_PS_DISABLE@GOTPAGE
Lloh9:
	ldr	x11, [x11, _JZ_LCD_CFG_PS_DISABLE@GOTPAGEOFF]
Lloh10:
	ldr	w11, [x11]
Lloh11:
	adrp	x12, _JZ_LCD_CFG_CLS_DISABLE@GOTPAGE
Lloh12:
	ldr	x12, [x12, _JZ_LCD_CFG_CLS_DISABLE@GOTPAGEOFF]
Lloh13:
	ldr	w12, [x12]
	orr	w11, w12, w11
Lloh14:
	adrp	x12, _JZ_LCD_CFG_SPL_DISABLE@GOTPAGE
Lloh15:
	ldr	x12, [x12, _JZ_LCD_CFG_SPL_DISABLE@GOTPAGEOFF]
Lloh16:
	ldr	w12, [x12]
	orr	w11, w11, w12
Lloh17:
	adrp	x12, _JZ_LCD_CFG_REV_DISABLE@GOTPAGE
Lloh18:
	ldr	x12, [x12, _JZ_LCD_CFG_REV_DISABLE@GOTPAGEOFF]
LBB0_3:
	ldr	w12, [x12]
	orr	w12, w11, w12
	ldr	w11, [x19]
Lloh19:
	adrp	x13, _DRM_MODE_FLAG_NHSYNC@GOTPAGE
Lloh20:
	ldr	x13, [x13, _DRM_MODE_FLAG_NHSYNC@GOTPAGEOFF]
Lloh21:
	ldr	w13, [x13]
Lloh22:
	adrp	x14, _JZ_LCD_CFG_HSYNC_ACTIVE_LOW@GOTPAGE
Lloh23:
	ldr	x14, [x14, _JZ_LCD_CFG_HSYNC_ACTIVE_LOW@GOTPAGEOFF]
Lloh24:
	ldr	w14, [x14]
	tst	w13, w11
	csel	w13, wzr, w14, eq
	orr	w12, w13, w12
Lloh25:
	adrp	x13, _DRM_MODE_FLAG_NVSYNC@GOTPAGE
Lloh26:
	ldr	x13, [x13, _DRM_MODE_FLAG_NVSYNC@GOTPAGEOFF]
Lloh27:
	ldr	w13, [x13]
Lloh28:
	adrp	x14, _JZ_LCD_CFG_VSYNC_ACTIVE_LOW@GOTPAGE
Lloh29:
	ldr	x14, [x14, _JZ_LCD_CFG_VSYNC_ACTIVE_LOW@GOTPAGEOFF]
Lloh30:
	ldr	w14, [x14]
	tst	w13, w11
	csel	w13, wzr, w14, eq
	orr	w12, w12, w13
Lloh31:
	adrp	x13, _DRM_BUS_FLAG_DE_LOW@GOTPAGE
Lloh32:
	ldr	x13, [x13, _DRM_BUS_FLAG_DE_LOW@GOTPAGEOFF]
Lloh33:
	ldr	w13, [x13]
Lloh34:
	adrp	x14, _JZ_LCD_CFG_DE_ACTIVE_LOW@GOTPAGE
Lloh35:
	ldr	x14, [x14, _JZ_LCD_CFG_DE_ACTIVE_LOW@GOTPAGEOFF]
Lloh36:
	ldr	w14, [x14]
	tst	w13, w10
	csel	w13, wzr, w14, eq
	orr	w12, w12, w13
Lloh37:
	adrp	x13, _DRM_BUS_FLAG_PIXDATA_NEGEDGE@GOTPAGE
Lloh38:
	ldr	x13, [x13, _DRM_BUS_FLAG_PIXDATA_NEGEDGE@GOTPAGEOFF]
Lloh39:
	ldr	w13, [x13]
Lloh40:
	adrp	x14, _JZ_LCD_CFG_PCLK_FALLING_EDGE@GOTPAGE
Lloh41:
	ldr	x14, [x14, _JZ_LCD_CFG_PCLK_FALLING_EDGE@GOTPAGEOFF]
Lloh42:
	ldr	w14, [x14]
	tst	w13, w10
	csel	w10, wzr, w14, eq
	orr	w2, w12, w10
	cbnz	w9, LBB0_15
; %bb.4:
	ldr	x9, [x8]
Lloh43:
	adrp	x10, _DRM_MODE_CONNECTOR_TV@GOTPAGE
Lloh44:
	ldr	x10, [x10, _DRM_MODE_CONNECTOR_TV@GOTPAGEOFF]
Lloh45:
	ldr	x10, [x10]
	cmp	x9, x10
	b.ne	LBB0_7
; %bb.5:
Lloh46:
	adrp	x8, _DRM_MODE_FLAG_INTERLACE@GOTPAGE
Lloh47:
	ldr	x8, [x8, _DRM_MODE_FLAG_INTERLACE@GOTPAGEOFF]
Lloh48:
	ldr	w8, [x8]
	tst	w8, w11
	b.eq	LBB0_10
; %bb.6:
Lloh49:
	adrp	x8, _JZ_LCD_CFG_MODE_TV_OUT_I@GOTPAGE
Lloh50:
	ldr	x8, [x8, _JZ_LCD_CFG_MODE_TV_OUT_I@GOTPAGEOFF]
	b	LBB0_14
LBB0_7:
	ldr	x8, [x8, #16]
	ldr	w8, [x8]
	sub	w8, w8, #128
	cmp	w8, #3
	b.hi	LBB0_15
; %bb.8:
Lloh51:
	adrp	x9, lJTI0_0@PAGE
Lloh52:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_9
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_9:
Lloh53:
	adrp	x8, _JZ_LCD_CFG_MODE_8BIT_SERIAL@GOTPAGE
Lloh54:
	ldr	x8, [x8, _JZ_LCD_CFG_MODE_8BIT_SERIAL@GOTPAGEOFF]
	b	LBB0_14
LBB0_10:
Lloh55:
	adrp	x8, _JZ_LCD_CFG_MODE_TV_OUT_P@GOTPAGE
Lloh56:
	ldr	x8, [x8, _JZ_LCD_CFG_MODE_TV_OUT_P@GOTPAGEOFF]
	b	LBB0_14
LBB0_11:
Lloh57:
	adrp	x8, _JZ_LCD_CFG_MODE_GENERIC_24BIT@GOTPAGE
Lloh58:
	ldr	x8, [x8, _JZ_LCD_CFG_MODE_GENERIC_24BIT@GOTPAGEOFF]
	b	LBB0_14
LBB0_12:
Lloh59:
	adrp	x8, _JZ_LCD_CFG_MODE_GENERIC_18BIT@GOTPAGE
Lloh60:
	ldr	x8, [x8, _JZ_LCD_CFG_MODE_GENERIC_18BIT@GOTPAGEOFF]
	b	LBB0_14
LBB0_13:
Lloh61:
	adrp	x8, _JZ_LCD_CFG_MODE_GENERIC_16BIT@GOTPAGE
Lloh62:
	ldr	x8, [x8, _JZ_LCD_CFG_MODE_GENERIC_16BIT@GOTPAGEOFF]
LBB0_14:
	ldr	w8, [x8]
	orr	w2, w8, w2
LBB0_15:
	ldr	w0, [x0, #4]
Lloh63:
	adrp	x8, _JZ_REG_LCD_CFG@GOTPAGE
Lloh64:
	ldr	x8, [x8, _JZ_REG_LCD_CFG@GOTPAGEOFF]
Lloh65:
	ldr	w1, [x8]
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_regmap_write
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpAdd	Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpLdrGot	Lloh59, Lloh60
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_9-LBB0_9)>>2
	.byte	(LBB0_11-LBB0_9)>>2
	.byte	(LBB0_12-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
                                        ; -- End function
	.comm	_DRM_BUS_FLAG_SHARP_SIGNALS,4,2 ; @DRM_BUS_FLAG_SHARP_SIGNALS
	.comm	_JZ_LCD_CFG_MODE_SPECIAL_TFT_1,4,2 ; @JZ_LCD_CFG_MODE_SPECIAL_TFT_1
	.comm	_JZ_LCD_CFG_REV_POLARITY,4,2    ; @JZ_LCD_CFG_REV_POLARITY
	.comm	_JZ_LCD_CFG_PS_DISABLE,4,2      ; @JZ_LCD_CFG_PS_DISABLE
	.comm	_JZ_LCD_CFG_CLS_DISABLE,4,2     ; @JZ_LCD_CFG_CLS_DISABLE
	.comm	_JZ_LCD_CFG_SPL_DISABLE,4,2     ; @JZ_LCD_CFG_SPL_DISABLE
	.comm	_JZ_LCD_CFG_REV_DISABLE,4,2     ; @JZ_LCD_CFG_REV_DISABLE
	.comm	_DRM_MODE_FLAG_NHSYNC,4,2       ; @DRM_MODE_FLAG_NHSYNC
	.comm	_JZ_LCD_CFG_HSYNC_ACTIVE_LOW,4,2 ; @JZ_LCD_CFG_HSYNC_ACTIVE_LOW
	.comm	_DRM_MODE_FLAG_NVSYNC,4,2       ; @DRM_MODE_FLAG_NVSYNC
	.comm	_JZ_LCD_CFG_VSYNC_ACTIVE_LOW,4,2 ; @JZ_LCD_CFG_VSYNC_ACTIVE_LOW
	.comm	_DRM_BUS_FLAG_DE_LOW,4,2        ; @DRM_BUS_FLAG_DE_LOW
	.comm	_JZ_LCD_CFG_DE_ACTIVE_LOW,4,2   ; @JZ_LCD_CFG_DE_ACTIVE_LOW
	.comm	_DRM_BUS_FLAG_PIXDATA_NEGEDGE,4,2 ; @DRM_BUS_FLAG_PIXDATA_NEGEDGE
	.comm	_JZ_LCD_CFG_PCLK_FALLING_EDGE,4,2 ; @JZ_LCD_CFG_PCLK_FALLING_EDGE
	.comm	_DRM_MODE_CONNECTOR_TV,8,3      ; @DRM_MODE_CONNECTOR_TV
	.comm	_DRM_MODE_FLAG_INTERLACE,4,2    ; @DRM_MODE_FLAG_INTERLACE
	.comm	_JZ_LCD_CFG_MODE_TV_OUT_I,4,2   ; @JZ_LCD_CFG_MODE_TV_OUT_I
	.comm	_JZ_LCD_CFG_MODE_TV_OUT_P,4,2   ; @JZ_LCD_CFG_MODE_TV_OUT_P
	.comm	_JZ_LCD_CFG_MODE_GENERIC_16BIT,4,2 ; @JZ_LCD_CFG_MODE_GENERIC_16BIT
	.comm	_JZ_LCD_CFG_MODE_GENERIC_18BIT,4,2 ; @JZ_LCD_CFG_MODE_GENERIC_18BIT
	.comm	_JZ_LCD_CFG_MODE_GENERIC_24BIT,4,2 ; @JZ_LCD_CFG_MODE_GENERIC_24BIT
	.comm	_JZ_LCD_CFG_MODE_8BIT_SERIAL,4,2 ; @JZ_LCD_CFG_MODE_8BIT_SERIAL
	.comm	_JZ_REG_LCD_CFG,4,2             ; @JZ_REG_LCD_CFG
	.no_dead_strip	_ingenic_drm_encoder_atomic_mode_set
.subsections_via_symbols
