	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gen11_emit_flush_render
_gen11_emit_flush_render:               ## @gen11_emit_flush_render
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r12d
	movq	%rdi, %r15
	movq	(%rdi), %rax
	movl	(%rax), %edi
	movq	_INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_intel_gt_scratch_offset
	movl	%eax, %r14d
	movq	_EMIT_FLUSH@GOTPCREL(%rip), %rax
	testl	%r12d, (%rax)
	je	LBB0_3
## %bb.1:
	movl	%r14d, -68(%rbp)                ## 4-byte Spill
	movq	_PIPE_CONTROL_CS_STALL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -64(%rbp)                 ## 4-byte Spill
	movq	_PIPE_CONTROL_TILE_CACHE_FLUSH@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_PIPE_CONTROL_DEPTH_CACHE_FLUSH@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -60(%rbp)                 ## 4-byte Spill
	movq	_PIPE_CONTROL_DC_FLUSH_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	movq	_PIPE_CONTROL_FLUSH_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movq	_PIPE_CONTROL_QW_WRITE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_PIPE_CONTROL_GLOBAL_GTT_IVB@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	%r15, %rdi
	movl	$6, %esi
	callq	_intel_ring_begin
	movq	%rax, %r13
	movq	%rax, %rdi
	callq	_IS_ERR
	testq	%rax, %rax
	je	LBB0_2
## %bb.7:
	movq	%r13, %rdi
	jmp	LBB0_8
LBB0_2:
	orl	-64(%rbp), %ebx                 ## 4-byte Folded Reload
	orl	%r14d, %ebx
	orl	-60(%rbp), %ebx                 ## 4-byte Folded Reload
	orl	-56(%rbp), %ebx                 ## 4-byte Folded Reload
	orl	-52(%rbp), %ebx                 ## 4-byte Folded Reload
	orl	-48(%rbp), %ebx                 ## 4-byte Folded Reload
	orl	-44(%rbp), %ebx                 ## 4-byte Folded Reload
	movq	%r13, %rdi
	movl	%ebx, %esi
	movl	-68(%rbp), %r14d                ## 4-byte Reload
	movl	%r14d, %edx
	callq	_gen8_emit_pipe_control
	movq	%r15, %rdi
	movq	%rax, %rsi
	callq	_intel_ring_advance
LBB0_3:
	movq	_EMIT_INVALIDATE@GOTPCREL(%rip), %rax
	testl	%r12d, (%rax)
	je	LBB0_6
## %bb.4:
	movq	_PIPE_CONTROL_CS_STALL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -68(%rbp)                 ## 4-byte Spill
	movq	_PIPE_CONTROL_COMMAND_CACHE_INVALIDATE@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_PIPE_CONTROL_TLB_INVALIDATE@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -64(%rbp)                 ## 4-byte Spill
	movq	_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -60(%rbp)                 ## 4-byte Spill
	movq	_PIPE_CONTROL_VF_CACHE_INVALIDATE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	movq	_PIPE_CONTROL_CONST_CACHE_INVALIDATE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movq	_PIPE_CONTROL_STATE_CACHE_INVALIDATE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_PIPE_CONTROL_QW_WRITE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	_PIPE_CONTROL_GLOBAL_GTT_IVB@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -72(%rbp)                 ## 4-byte Spill
	movq	%r15, %rdi
	movl	$6, %esi
	callq	_intel_ring_begin
	movq	%rax, %r12
	movq	%rax, %rdi
	callq	_IS_ERR
	testq	%rax, %rax
	je	LBB0_5
## %bb.9:
	movq	%r12, %rdi
LBB0_8:
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_PTR_ERR                        ## TAILCALL
LBB0_5:
	orl	-68(%rbp), %ebx                 ## 4-byte Folded Reload
	orl	%r13d, %ebx
	orl	-64(%rbp), %ebx                 ## 4-byte Folded Reload
	orl	-60(%rbp), %ebx                 ## 4-byte Folded Reload
	orl	-56(%rbp), %ebx                 ## 4-byte Folded Reload
	orl	-52(%rbp), %ebx                 ## 4-byte Folded Reload
	orl	-48(%rbp), %ebx                 ## 4-byte Folded Reload
	orl	-44(%rbp), %ebx                 ## 4-byte Folded Reload
	orl	-72(%rbp), %ebx                 ## 4-byte Folded Reload
	movq	%r12, %rdi
	movl	%ebx, %esi
	movl	%r14d, %edx
	callq	_gen8_emit_pipe_control
	movq	%r15, %rdi
	movq	%rax, %rsi
	callq	_intel_ring_advance
LBB0_6:
	xorl	%eax, %eax
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH,4,2 ## @INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH
	.comm	_EMIT_FLUSH,4,2                 ## @EMIT_FLUSH
	.comm	_PIPE_CONTROL_CS_STALL,4,2      ## @PIPE_CONTROL_CS_STALL
	.comm	_PIPE_CONTROL_TILE_CACHE_FLUSH,4,2 ## @PIPE_CONTROL_TILE_CACHE_FLUSH
	.comm	_PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH,4,2 ## @PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
	.comm	_PIPE_CONTROL_DEPTH_CACHE_FLUSH,4,2 ## @PIPE_CONTROL_DEPTH_CACHE_FLUSH
	.comm	_PIPE_CONTROL_DC_FLUSH_ENABLE,4,2 ## @PIPE_CONTROL_DC_FLUSH_ENABLE
	.comm	_PIPE_CONTROL_FLUSH_ENABLE,4,2  ## @PIPE_CONTROL_FLUSH_ENABLE
	.comm	_PIPE_CONTROL_QW_WRITE,4,2      ## @PIPE_CONTROL_QW_WRITE
	.comm	_PIPE_CONTROL_GLOBAL_GTT_IVB,4,2 ## @PIPE_CONTROL_GLOBAL_GTT_IVB
	.comm	_EMIT_INVALIDATE,4,2            ## @EMIT_INVALIDATE
	.comm	_PIPE_CONTROL_COMMAND_CACHE_INVALIDATE,4,2 ## @PIPE_CONTROL_COMMAND_CACHE_INVALIDATE
	.comm	_PIPE_CONTROL_TLB_INVALIDATE,4,2 ## @PIPE_CONTROL_TLB_INVALIDATE
	.comm	_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE,4,2 ## @PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
	.comm	_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE,4,2 ## @PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
	.comm	_PIPE_CONTROL_VF_CACHE_INVALIDATE,4,2 ## @PIPE_CONTROL_VF_CACHE_INVALIDATE
	.comm	_PIPE_CONTROL_CONST_CACHE_INVALIDATE,4,2 ## @PIPE_CONTROL_CONST_CACHE_INVALIDATE
	.comm	_PIPE_CONTROL_STATE_CACHE_INVALIDATE,4,2 ## @PIPE_CONTROL_STATE_CACHE_INVALIDATE
	.no_dead_strip	_gen11_emit_flush_render
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gen11_emit_flush_render
_gen11_emit_flush_render:               ; @gen11_emit_flush_render
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x1
	mov	x19, x0
	ldr	x8, [x0]
	ldr	w0, [x8]
Lloh0:
	adrp	x8, _INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH@GOTPAGE
Lloh1:
	ldr	x8, [x8, _INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	bl	_intel_gt_scratch_offset
	mov	x20, x0
Lloh3:
	adrp	x8, _EMIT_FLUSH@GOTPAGE
Lloh4:
	ldr	x8, [x8, _EMIT_FLUSH@GOTPAGEOFF]
Lloh5:
	adrp	x11, _PIPE_CONTROL_CS_STALL@GOTPAGE
Lloh6:
	ldr	x11, [x11, _PIPE_CONTROL_CS_STALL@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
Lloh8:
	adrp	x9, _PIPE_CONTROL_QW_WRITE@GOTPAGE
Lloh9:
	ldr	x9, [x9, _PIPE_CONTROL_QW_WRITE@GOTPAGEOFF]
Lloh10:
	adrp	x10, _PIPE_CONTROL_GLOBAL_GTT_IVB@GOTPAGE
Lloh11:
	ldr	x10, [x10, _PIPE_CONTROL_GLOBAL_GTT_IVB@GOTPAGEOFF]
	tst	w8, w21
	b.eq	LBB0_4
; %bb.1:
	ldr	w8, [x11]
	stp	w8, w20, [sp, #8]               ; 8-byte Folded Spill
Lloh12:
	adrp	x8, _PIPE_CONTROL_TILE_CACHE_FLUSH@GOTPAGE
Lloh13:
	ldr	x8, [x8, _PIPE_CONTROL_TILE_CACHE_FLUSH@GOTPAGEOFF]
Lloh14:
	ldr	w27, [x8]
Lloh15:
	adrp	x8, _PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH@GOTPAGE
Lloh16:
	ldr	x8, [x8, _PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH@GOTPAGEOFF]
Lloh17:
	ldr	w28, [x8]
Lloh18:
	adrp	x8, _PIPE_CONTROL_DEPTH_CACHE_FLUSH@GOTPAGE
Lloh19:
	ldr	x8, [x8, _PIPE_CONTROL_DEPTH_CACHE_FLUSH@GOTPAGEOFF]
Lloh20:
	ldr	w23, [x8]
Lloh21:
	adrp	x8, _PIPE_CONTROL_DC_FLUSH_ENABLE@GOTPAGE
Lloh22:
	ldr	x8, [x8, _PIPE_CONTROL_DC_FLUSH_ENABLE@GOTPAGEOFF]
Lloh23:
	ldr	w24, [x8]
Lloh24:
	adrp	x8, _PIPE_CONTROL_FLUSH_ENABLE@GOTPAGE
Lloh25:
	ldr	x8, [x8, _PIPE_CONTROL_FLUSH_ENABLE@GOTPAGEOFF]
Lloh26:
	ldr	w20, [x8]
	ldr	w25, [x9]
	ldr	w26, [x10]
	mov	x0, x19
	mov	w1, #6
	bl	_intel_ring_begin
	mov	x22, x0
	bl	_IS_ERR
	cbz	x0, LBB0_3
; %bb.2:
	mov	x0, x22
	b	LBB0_7
LBB0_3:
	ldr	w8, [sp, #8]                    ; 4-byte Folded Reload
	orr	w8, w27, w8
	orr	w8, w8, w28
	orr	w8, w8, w23
	orr	w8, w8, w24
	orr	w8, w8, w20
	orr	w8, w8, w25
	orr	w1, w8, w26
	mov	x0, x22
	ldr	w20, [sp, #12]                  ; 4-byte Folded Reload
	mov	x2, x20
	bl	_gen8_emit_pipe_control
	mov	x1, x0
	mov	x0, x19
	bl	_intel_ring_advance
Lloh27:
	adrp	x9, _PIPE_CONTROL_QW_WRITE@GOTPAGE
Lloh28:
	ldr	x9, [x9, _PIPE_CONTROL_QW_WRITE@GOTPAGEOFF]
Lloh29:
	adrp	x10, _PIPE_CONTROL_GLOBAL_GTT_IVB@GOTPAGE
Lloh30:
	ldr	x10, [x10, _PIPE_CONTROL_GLOBAL_GTT_IVB@GOTPAGEOFF]
Lloh31:
	adrp	x11, _PIPE_CONTROL_CS_STALL@GOTPAGE
Lloh32:
	ldr	x11, [x11, _PIPE_CONTROL_CS_STALL@GOTPAGEOFF]
LBB0_4:
Lloh33:
	adrp	x8, _EMIT_INVALIDATE@GOTPAGE
Lloh34:
	ldr	x8, [x8, _EMIT_INVALIDATE@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
	tst	w8, w21
	b.eq	LBB0_9
; %bb.5:
	ldr	w8, [x11]
	str	w8, [sp, #12]                   ; 4-byte Folded Spill
Lloh36:
	adrp	x8, _PIPE_CONTROL_COMMAND_CACHE_INVALIDATE@GOTPAGE
Lloh37:
	ldr	x8, [x8, _PIPE_CONTROL_COMMAND_CACHE_INVALIDATE@GOTPAGEOFF]
Lloh38:
	ldr	w8, [x8]
	str	w8, [sp, #8]                    ; 4-byte Folded Spill
Lloh39:
	adrp	x8, _PIPE_CONTROL_TLB_INVALIDATE@GOTPAGE
Lloh40:
	ldr	x8, [x8, _PIPE_CONTROL_TLB_INVALIDATE@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
	str	w8, [sp, #4]                    ; 4-byte Folded Spill
Lloh42:
	adrp	x8, _PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE@GOTPAGE
Lloh43:
	ldr	x8, [x8, _PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE@GOTPAGEOFF]
Lloh44:
	ldr	w27, [x8]
Lloh45:
	adrp	x8, _PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE@GOTPAGE
Lloh46:
	ldr	x8, [x8, _PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE@GOTPAGEOFF]
Lloh47:
	ldr	w28, [x8]
Lloh48:
	adrp	x8, _PIPE_CONTROL_VF_CACHE_INVALIDATE@GOTPAGE
Lloh49:
	ldr	x8, [x8, _PIPE_CONTROL_VF_CACHE_INVALIDATE@GOTPAGEOFF]
Lloh50:
	ldr	w22, [x8]
Lloh51:
	adrp	x8, _PIPE_CONTROL_CONST_CACHE_INVALIDATE@GOTPAGE
Lloh52:
	ldr	x8, [x8, _PIPE_CONTROL_CONST_CACHE_INVALIDATE@GOTPAGEOFF]
Lloh53:
	ldr	w25, [x8]
Lloh54:
	adrp	x8, _PIPE_CONTROL_STATE_CACHE_INVALIDATE@GOTPAGE
Lloh55:
	ldr	x8, [x8, _PIPE_CONTROL_STATE_CACHE_INVALIDATE@GOTPAGEOFF]
Lloh56:
	ldr	w23, [x8]
	ldr	w26, [x9]
	ldr	w24, [x10]
	mov	x0, x19
	mov	w1, #6
	bl	_intel_ring_begin
	mov	x21, x0
	bl	_IS_ERR
	cbz	x0, LBB0_8
; %bb.6:
	mov	x0, x21
LBB0_7:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	b	_PTR_ERR
LBB0_8:
	ldp	w9, w8, [sp, #8]                ; 8-byte Folded Reload
	orr	w8, w9, w8
	ldr	w9, [sp, #4]                    ; 4-byte Folded Reload
	orr	w8, w8, w9
	orr	w8, w8, w27
	orr	w8, w8, w28
	orr	w8, w8, w22
	orr	w8, w8, w25
	orr	w8, w8, w23
	orr	w8, w8, w26
	orr	w1, w8, w24
	mov	x0, x21
	mov	x2, x20
	bl	_gen8_emit_pipe_control
	mov	x1, x0
	mov	x0, x19
	bl	_intel_ring_advance
LBB0_9:
	mov	w0, #0
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh7
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.cfi_endproc
                                        ; -- End function
	.comm	_INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH,4,2 ; @INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH
	.comm	_EMIT_FLUSH,4,2                 ; @EMIT_FLUSH
	.comm	_PIPE_CONTROL_CS_STALL,4,2      ; @PIPE_CONTROL_CS_STALL
	.comm	_PIPE_CONTROL_TILE_CACHE_FLUSH,4,2 ; @PIPE_CONTROL_TILE_CACHE_FLUSH
	.comm	_PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH,4,2 ; @PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
	.comm	_PIPE_CONTROL_DEPTH_CACHE_FLUSH,4,2 ; @PIPE_CONTROL_DEPTH_CACHE_FLUSH
	.comm	_PIPE_CONTROL_DC_FLUSH_ENABLE,4,2 ; @PIPE_CONTROL_DC_FLUSH_ENABLE
	.comm	_PIPE_CONTROL_FLUSH_ENABLE,4,2  ; @PIPE_CONTROL_FLUSH_ENABLE
	.comm	_PIPE_CONTROL_QW_WRITE,4,2      ; @PIPE_CONTROL_QW_WRITE
	.comm	_PIPE_CONTROL_GLOBAL_GTT_IVB,4,2 ; @PIPE_CONTROL_GLOBAL_GTT_IVB
	.comm	_EMIT_INVALIDATE,4,2            ; @EMIT_INVALIDATE
	.comm	_PIPE_CONTROL_COMMAND_CACHE_INVALIDATE,4,2 ; @PIPE_CONTROL_COMMAND_CACHE_INVALIDATE
	.comm	_PIPE_CONTROL_TLB_INVALIDATE,4,2 ; @PIPE_CONTROL_TLB_INVALIDATE
	.comm	_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE,4,2 ; @PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
	.comm	_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE,4,2 ; @PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
	.comm	_PIPE_CONTROL_VF_CACHE_INVALIDATE,4,2 ; @PIPE_CONTROL_VF_CACHE_INVALIDATE
	.comm	_PIPE_CONTROL_CONST_CACHE_INVALIDATE,4,2 ; @PIPE_CONTROL_CONST_CACHE_INVALIDATE
	.comm	_PIPE_CONTROL_STATE_CACHE_INVALIDATE,4,2 ; @PIPE_CONTROL_STATE_CACHE_INVALIDATE
	.no_dead_strip	_gen11_emit_flush_render
.subsections_via_symbols
