	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx10_kiq_map_queues
_gfx10_kiq_map_queues:                  ## @gfx10_kiq_map_queues
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r13
	movq	%rdi, %r12
	movq	40(%rdi), %rbx
	movl	32(%rsi), %edi
	callq	_amdgpu_bo_gpu_offset
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movslq	(%r13), %rax
	shlq	$2, %rax
	addq	(%rbx), %rax
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
	movq	24(%r13), %rax
	movq	(%rax), %rax
	movq	_AMDGPU_RING_TYPE_GFX@GOTPCREL(%rip), %rcx
	xorl	%ebx, %ebx
	cmpq	(%rcx), %rax
	sete	%bl
	shll	$2, %ebx
	movq	_PACKET3_MAP_QUEUES@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$5, %esi
	callq	_PACKET3
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	xorl	%edi, %edi
	callq	_PACKET3_MAP_QUEUES_QUEUE_SEL
	movl	%eax, %r15d
	xorl	%edi, %edi
	callq	_PACKET3_MAP_QUEUES_VMID
	orl	%eax, %r15d
	movl	16(%r13), %edi
	callq	_PACKET3_MAP_QUEUES_QUEUE
	orl	%eax, %r15d
	movl	12(%r13), %edi
	callq	_PACKET3_MAP_QUEUES_PIPE
	orl	%eax, %r15d
	xorl	%edi, %edi
	cmpl	$1, 4(%r13)
	setne	%dil
	callq	_PACKET3_MAP_QUEUES_ME
	movl	%eax, %r14d
	xorl	%edi, %edi
	callq	_PACKET3_MAP_QUEUES_QUEUE_TYPE
	orl	%eax, %r15d
	orl	%r14d, %r15d
	xorl	%edi, %edi
	callq	_PACKET3_MAP_QUEUES_ALLOC_FORMAT
	orl	%eax, %r15d
	movl	%ebx, %edi
	callq	_PACKET3_MAP_QUEUES_ENGINE_SEL
	movl	%eax, %ebx
	movl	$1, %edi
	callq	_PACKET3_MAP_QUEUES_NUM_QUEUES
	orl	%eax, %r15d
	orl	%ebx, %r15d
	movq	%r12, %rdi
	movl	%r15d, %esi
	callq	_amdgpu_ring_write
	movl	8(%r13), %edi
	callq	_PACKET3_MAP_QUEUES_DOORBELL_OFFSET
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	callq	_lower_32_bits
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	callq	_upper_32_bits
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	callq	_lower_32_bits
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	callq	_upper_32_bits
	movq	%r12, %rdi
	movl	%eax, %esi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_write              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_RING_TYPE_GFX,8,3       ## @AMDGPU_RING_TYPE_GFX
	.comm	_PACKET3_MAP_QUEUES,4,2         ## @PACKET3_MAP_QUEUES
	.no_dead_strip	_gfx10_kiq_map_queues
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx10_kiq_map_queues
_gfx10_kiq_map_queues:                  ; @gfx10_kiq_map_queues
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x22, x1
	mov	x19, x0
	ldr	x20, [x0, #40]
	ldr	w0, [x1, #32]
	bl	_amdgpu_bo_gpu_offset
	mov	x21, x0
	ldr	x8, [x20]
	ldrsw	x9, [x22]
	add	x20, x8, x9, lsl #2
	ldr	x8, [x22, #24]
	ldr	x8, [x8]
Lloh0:
	adrp	x9, _AMDGPU_RING_TYPE_GFX@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMDGPU_RING_TYPE_GFX@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	cset	w8, eq
	lsl	w23, w8, #2
Lloh3:
	adrp	x8, _PACKET3_MAP_QUEUES@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PACKET3_MAP_QUEUES@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	mov	w1, #5
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	w0, #0
	bl	_PACKET3_MAP_QUEUES_QUEUE_SEL
	mov	x24, x0
	mov	w0, #0
	bl	_PACKET3_MAP_QUEUES_VMID
	orr	w24, w0, w24
	ldr	w0, [x22, #16]
	bl	_PACKET3_MAP_QUEUES_QUEUE
	orr	w24, w24, w0
	ldr	w0, [x22, #12]
	bl	_PACKET3_MAP_QUEUES_PIPE
	orr	w24, w24, w0
	ldr	w8, [x22, #4]
	cmp	w8, #1
	cset	w0, ne
	bl	_PACKET3_MAP_QUEUES_ME
	orr	w24, w24, w0
	mov	w0, #0
	bl	_PACKET3_MAP_QUEUES_QUEUE_TYPE
	orr	w24, w24, w0
	mov	w0, #0
	bl	_PACKET3_MAP_QUEUES_ALLOC_FORMAT
	orr	w24, w24, w0
	mov	x0, x23
	bl	_PACKET3_MAP_QUEUES_ENGINE_SEL
	orr	w23, w24, w0
	mov	w0, #1
	bl	_PACKET3_MAP_QUEUES_NUM_QUEUES
	orr	w1, w23, w0
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x22, #8]
	bl	_PACKET3_MAP_QUEUES_DOORBELL_OFFSET
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x21
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x21
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x20
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x20
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_amdgpu_ring_write
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_RING_TYPE_GFX,8,3       ; @AMDGPU_RING_TYPE_GFX
	.comm	_PACKET3_MAP_QUEUES,4,2         ; @PACKET3_MAP_QUEUES
	.no_dead_strip	_gfx10_kiq_map_queues
.subsections_via_symbols
