	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function evergreen_gpu_soft_reset
_evergreen_gpu_soft_reset:              ## @evergreen_gpu_soft_reset
	.cfi_startproc
## %bb.0:
	testl	%esi, %esi
	je	LBB0_31
## %bb.1:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r15d
	movq	%rdi, %r14
	movl	4(%rdi), %edi
	leaq	L_.str(%rip), %rsi
	movl	%r15d, %edx
	callq	_dev_info
	movq	%r14, %rdi
	callq	_evergreen_print_gpu_status_regs
	movq	_CP_ME_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_CP_ME_HALT@GOTPCREL(%rip), %rax
	movq	_CP_PFP_HALT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	callq	_WREG32
	movq	_RADEON_RESET_DMA@GOTPCREL(%rip), %r12
	testl	%r15d, (%r12)
	je	LBB0_3
## %bb.2:
	movq	_DMA_RB_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_DMA_RB_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32
LBB0_3:
	movl	$50, %edi
	callq	_udelay
	leaq	-48(%rbp), %rsi
	movq	%r14, %rdi
	callq	_evergreen_mc_stop
	movq	%r14, %rdi
	callq	_evergreen_mc_wait_for_idle
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	movl	4(%r14), %edi
	leaq	L_.str.1(%rip), %rsi
	callq	_dev_warn
LBB0_5:
	movq	_RADEON_RESET_GFX@GOTPCREL(%rip), %rax
	movq	_RADEON_RESET_COMPUTE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	testl	%r15d, %ecx
	je	LBB0_6
## %bb.7:
	movq	_SOFT_RESET_DB@GOTPCREL(%rip), %rax
	movq	_SOFT_RESET_CB@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	_SOFT_RESET_PA@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SOFT_RESET_SC@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SOFT_RESET_SPI@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SOFT_RESET_SX@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SOFT_RESET_SH@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SOFT_RESET_TC@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SOFT_RESET_TA@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SOFT_RESET_VC@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SOFT_RESET_VGT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	jmp	LBB0_8
LBB0_6:
	xorl	%ebx, %ebx
LBB0_8:
	movq	_RADEON_RESET_CP@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_9
## %bb.10:
	movq	_SOFT_RESET_CP@GOTPCREL(%rip), %rax
	movq	_SOFT_RESET_VGT@GOTPCREL(%rip), %rcx
	orl	(%rax), %ebx
	orl	(%rcx), %ebx
	movq	_SOFT_RESET_GRBM@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, %ecx
	jmp	LBB0_11
LBB0_9:
	movq	_SOFT_RESET_GRBM@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	xorl	%ecx, %ecx
LBB0_11:
	movl	(%r12), %r12d
	andl	%r15d, %r12d
	je	LBB0_13
## %bb.12:
	movq	_SOFT_RESET_DMA@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r12d
LBB0_13:
	movq	_RADEON_RESET_DISPLAY@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	andl	%r15d, %edx
	je	LBB0_15
## %bb.14:
	movq	_SOFT_RESET_DC@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
LBB0_15:
	movq	_RADEON_RESET_RLC@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	andl	%r15d, %esi
	je	LBB0_17
## %bb.16:
	movq	_SOFT_RESET_RLC@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
LBB0_17:
	orl	%esi, %edx
	orl	%ecx, %r12d
	movq	_RADEON_RESET_SEM@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%r15d, %ecx
	je	LBB0_19
## %bb.18:
	movq	_SOFT_RESET_SEM@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_19:
	orl	%edx, %r12d
	movq	_RADEON_RESET_IH@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	andl	%r15d, %edx
	je	LBB0_21
## %bb.20:
	movq	_SOFT_RESET_IH@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
LBB0_21:
	orl	%edx, %ecx
	movq	_RADEON_RESET_GRBM@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	andl	%r15d, %edx
	cmovel	%edx, %eax
	orl	%ecx, %eax
	orl	%eax, %r12d
	movq	_RADEON_RESET_VMC@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r15d, %eax
	je	LBB0_23
## %bb.22:
	movq	_SOFT_RESET_VMC@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_23:
	orl	%eax, %r12d
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r14)
	jne	LBB0_26
## %bb.24:
	movq	_RADEON_RESET_MC@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_26
## %bb.25:
	movq	_SOFT_RESET_MC@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
LBB0_26:
	testl	%ebx, %ebx
	je	LBB0_28
## %bb.27:
	movq	_GRBM_SOFT_RESET@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_RREG32
	movl	%eax, %r15d
	orl	%ebx, %r15d
	movl	4(%r14), %edi
	leaq	L_.str.2(%rip), %rsi
	movl	%r15d, %edx
	callq	_dev_info
	movl	(%r13), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movl	(%r13), %edi
	callq	_RREG32
	movl	%eax, %r15d
	movl	$50, %edi
	callq	_udelay
	notl	%ebx
	andl	%r15d, %ebx
	movl	(%r13), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r13), %edi
	callq	_RREG32
LBB0_28:
	testl	%r12d, %r12d
	je	LBB0_30
## %bb.29:
	movq	_SRBM_SOFT_RESET@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32
	movl	%eax, %ebx
	orl	%r12d, %ebx
	movl	4(%r14), %edi
	leaq	L_.str.3(%rip), %rsi
	movl	%ebx, %edx
	callq	_dev_info
	movl	(%r15), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r15), %edi
	callq	_RREG32
	movl	%eax, %ebx
	movl	$50, %edi
	callq	_udelay
	notl	%r12d
	andl	%ebx, %r12d
	movl	(%r15), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movl	(%r15), %edi
	callq	_RREG32
LBB0_30:
	movl	$50, %edi
	callq	_udelay
	leaq	-48(%rbp), %rsi
	movq	%r14, %rdi
	callq	_evergreen_mc_resume
	movl	$50, %edi
	callq	_udelay
	movq	%r14, %rdi
	callq	_evergreen_print_gpu_status_regs
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
LBB0_31:
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"GPU softreset: 0x%08X\n"

	.comm	_CP_ME_CNTL,4,2                 ## @CP_ME_CNTL
	.comm	_CP_ME_HALT,4,2                 ## @CP_ME_HALT
	.comm	_CP_PFP_HALT,4,2                ## @CP_PFP_HALT
	.comm	_RADEON_RESET_DMA,4,2           ## @RADEON_RESET_DMA
	.comm	_DMA_RB_CNTL,4,2                ## @DMA_RB_CNTL
	.comm	_DMA_RB_ENABLE,4,2              ## @DMA_RB_ENABLE
L_.str.1:                               ## @.str.1
	.asciz	"Wait for MC idle timedout !\n"

	.comm	_RADEON_RESET_GFX,4,2           ## @RADEON_RESET_GFX
	.comm	_RADEON_RESET_COMPUTE,4,2       ## @RADEON_RESET_COMPUTE
	.comm	_SOFT_RESET_DB,4,2              ## @SOFT_RESET_DB
	.comm	_SOFT_RESET_CB,4,2              ## @SOFT_RESET_CB
	.comm	_SOFT_RESET_PA,4,2              ## @SOFT_RESET_PA
	.comm	_SOFT_RESET_SC,4,2              ## @SOFT_RESET_SC
	.comm	_SOFT_RESET_SPI,4,2             ## @SOFT_RESET_SPI
	.comm	_SOFT_RESET_SX,4,2              ## @SOFT_RESET_SX
	.comm	_SOFT_RESET_SH,4,2              ## @SOFT_RESET_SH
	.comm	_SOFT_RESET_TC,4,2              ## @SOFT_RESET_TC
	.comm	_SOFT_RESET_TA,4,2              ## @SOFT_RESET_TA
	.comm	_SOFT_RESET_VC,4,2              ## @SOFT_RESET_VC
	.comm	_SOFT_RESET_VGT,4,2             ## @SOFT_RESET_VGT
	.comm	_RADEON_RESET_CP,4,2            ## @RADEON_RESET_CP
	.comm	_SOFT_RESET_CP,4,2              ## @SOFT_RESET_CP
	.comm	_SOFT_RESET_GRBM,4,2            ## @SOFT_RESET_GRBM
	.comm	_SOFT_RESET_DMA,4,2             ## @SOFT_RESET_DMA
	.comm	_RADEON_RESET_DISPLAY,4,2       ## @RADEON_RESET_DISPLAY
	.comm	_SOFT_RESET_DC,4,2              ## @SOFT_RESET_DC
	.comm	_RADEON_RESET_RLC,4,2           ## @RADEON_RESET_RLC
	.comm	_SOFT_RESET_RLC,4,2             ## @SOFT_RESET_RLC
	.comm	_RADEON_RESET_SEM,4,2           ## @RADEON_RESET_SEM
	.comm	_SOFT_RESET_SEM,4,2             ## @SOFT_RESET_SEM
	.comm	_RADEON_RESET_IH,4,2            ## @RADEON_RESET_IH
	.comm	_SOFT_RESET_IH,4,2              ## @SOFT_RESET_IH
	.comm	_RADEON_RESET_GRBM,4,2          ## @RADEON_RESET_GRBM
	.comm	_RADEON_RESET_VMC,4,2           ## @RADEON_RESET_VMC
	.comm	_SOFT_RESET_VMC,4,2             ## @SOFT_RESET_VMC
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
	.comm	_RADEON_RESET_MC,4,2            ## @RADEON_RESET_MC
	.comm	_SOFT_RESET_MC,4,2              ## @SOFT_RESET_MC
	.comm	_GRBM_SOFT_RESET,4,2            ## @GRBM_SOFT_RESET
L_.str.2:                               ## @.str.2
	.asciz	"GRBM_SOFT_RESET=0x%08X\n"

	.comm	_SRBM_SOFT_RESET,4,2            ## @SRBM_SOFT_RESET
L_.str.3:                               ## @.str.3
	.asciz	"SRBM_SOFT_RESET=0x%08X\n"

	.no_dead_strip	_evergreen_gpu_soft_reset
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function evergreen_gpu_soft_reset
_evergreen_gpu_soft_reset:              ; @evergreen_gpu_soft_reset
	.cfi_startproc
; %bb.0:
	cbz	w1, LBB0_19
; %bb.1:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x1
	mov	x19, x0
	ldr	w0, [x0, #4]
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	mov	x2, x20
	bl	_dev_info
	mov	x0, x19
	bl	_evergreen_print_gpu_status_regs
Lloh2:
	adrp	x8, _CP_ME_CNTL@GOTPAGE
Lloh3:
	ldr	x8, [x8, _CP_ME_CNTL@GOTPAGEOFF]
Lloh4:
	adrp	x9, _CP_ME_HALT@GOTPAGE
Lloh5:
	ldr	x9, [x9, _CP_ME_HALT@GOTPAGEOFF]
Lloh6:
	ldr	w0, [x8]
Lloh7:
	ldr	w8, [x9]
Lloh8:
	adrp	x9, _CP_PFP_HALT@GOTPAGE
Lloh9:
	ldr	x9, [x9, _CP_PFP_HALT@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
	orr	w1, w9, w8
	bl	_WREG32
Lloh11:
	adrp	x22, _RADEON_RESET_DMA@GOTPAGE
Lloh12:
	ldr	x22, [x22, _RADEON_RESET_DMA@GOTPAGEOFF]
	ldr	w8, [x22]
	tst	w8, w20
	b.eq	LBB0_3
; %bb.2:
Lloh13:
	adrp	x21, _DMA_RB_CNTL@GOTPAGE
Lloh14:
	ldr	x21, [x21, _DMA_RB_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
Lloh15:
	adrp	x8, _DMA_RB_ENABLE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _DMA_RB_ENABLE@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w0, [x21]
	bl	_WREG32
LBB0_3:
	mov	w0, #50
	bl	_udelay
	add	x1, sp, #8
	mov	x0, x19
	bl	_evergreen_mc_stop
	mov	x0, x19
	bl	_evergreen_mc_wait_for_idle
	cbz	x0, LBB0_5
; %bb.4:
	ldr	w0, [x19, #4]
Lloh18:
	adrp	x1, l_.str.1@PAGE
Lloh19:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_warn
LBB0_5:
Lloh20:
	adrp	x8, _RADEON_RESET_GFX@GOTPAGE
Lloh21:
	ldr	x8, [x8, _RADEON_RESET_GFX@GOTPAGEOFF]
Lloh22:
	adrp	x9, _RADEON_RESET_COMPUTE@GOTPAGE
Lloh23:
	ldr	x9, [x9, _RADEON_RESET_COMPUTE@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
Lloh25:
	ldr	w9, [x9]
	orr	w9, w9, w8
Lloh26:
	adrp	x8, _SOFT_RESET_VGT@GOTPAGE
Lloh27:
	ldr	x8, [x8, _SOFT_RESET_VGT@GOTPAGEOFF]
	tst	w9, w20
	b.eq	LBB0_7
; %bb.6:
Lloh28:
	adrp	x9, _SOFT_RESET_DB@GOTPAGE
Lloh29:
	ldr	x9, [x9, _SOFT_RESET_DB@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
Lloh31:
	adrp	x10, _SOFT_RESET_CB@GOTPAGE
Lloh32:
	ldr	x10, [x10, _SOFT_RESET_CB@GOTPAGEOFF]
Lloh33:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh34:
	adrp	x10, _SOFT_RESET_PA@GOTPAGE
Lloh35:
	ldr	x10, [x10, _SOFT_RESET_PA@GOTPAGEOFF]
Lloh36:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh37:
	adrp	x10, _SOFT_RESET_SC@GOTPAGE
Lloh38:
	ldr	x10, [x10, _SOFT_RESET_SC@GOTPAGEOFF]
Lloh39:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh40:
	adrp	x10, _SOFT_RESET_SPI@GOTPAGE
Lloh41:
	ldr	x10, [x10, _SOFT_RESET_SPI@GOTPAGEOFF]
Lloh42:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh43:
	adrp	x10, _SOFT_RESET_SX@GOTPAGE
Lloh44:
	ldr	x10, [x10, _SOFT_RESET_SX@GOTPAGEOFF]
Lloh45:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh46:
	adrp	x10, _SOFT_RESET_SH@GOTPAGE
Lloh47:
	ldr	x10, [x10, _SOFT_RESET_SH@GOTPAGEOFF]
Lloh48:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh49:
	adrp	x10, _SOFT_RESET_TC@GOTPAGE
Lloh50:
	ldr	x10, [x10, _SOFT_RESET_TC@GOTPAGEOFF]
Lloh51:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh52:
	adrp	x10, _SOFT_RESET_TA@GOTPAGE
Lloh53:
	ldr	x10, [x10, _SOFT_RESET_TA@GOTPAGEOFF]
Lloh54:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh55:
	adrp	x10, _SOFT_RESET_VC@GOTPAGE
Lloh56:
	ldr	x10, [x10, _SOFT_RESET_VC@GOTPAGEOFF]
Lloh57:
	ldr	w10, [x10]
	orr	w9, w9, w10
	ldr	w10, [x8]
	orr	w21, w9, w10
	b	LBB0_8
LBB0_7:
	mov	w21, #0
LBB0_8:
Lloh58:
	adrp	x9, _RADEON_RESET_CP@GOTPAGE
Lloh59:
	ldr	x9, [x9, _RADEON_RESET_CP@GOTPAGEOFF]
Lloh60:
	ldr	w9, [x9]
	tst	w9, w20
	b.eq	LBB0_10
; %bb.9:
Lloh61:
	adrp	x9, _SOFT_RESET_CP@GOTPAGE
Lloh62:
	ldr	x9, [x9, _SOFT_RESET_CP@GOTPAGEOFF]
Lloh63:
	ldr	w9, [x9]
	ldr	w8, [x8]
	orr	w9, w9, w21
	orr	w21, w9, w8
Lloh64:
	adrp	x8, _SOFT_RESET_GRBM@GOTPAGE
Lloh65:
	ldr	x8, [x8, _SOFT_RESET_GRBM@GOTPAGEOFF]
Lloh66:
	ldr	w8, [x8]
	mov	x9, x8
	b	LBB0_11
LBB0_10:
	mov	w9, #0
Lloh67:
	adrp	x8, _SOFT_RESET_GRBM@GOTPAGE
Lloh68:
	ldr	x8, [x8, _SOFT_RESET_GRBM@GOTPAGEOFF]
Lloh69:
	ldr	w8, [x8]
LBB0_11:
	ldr	w10, [x22]
Lloh70:
	adrp	x11, _SOFT_RESET_DMA@GOTPAGE
Lloh71:
	ldr	x11, [x11, _SOFT_RESET_DMA@GOTPAGEOFF]
Lloh72:
	ldr	w11, [x11]
	tst	w10, w20
	csel	w10, wzr, w11, eq
	orr	w9, w10, w9
Lloh73:
	adrp	x10, _RADEON_RESET_DISPLAY@GOTPAGE
Lloh74:
	ldr	x10, [x10, _RADEON_RESET_DISPLAY@GOTPAGEOFF]
Lloh75:
	ldr	w10, [x10]
Lloh76:
	adrp	x11, _SOFT_RESET_DC@GOTPAGE
Lloh77:
	ldr	x11, [x11, _SOFT_RESET_DC@GOTPAGEOFF]
Lloh78:
	ldr	w11, [x11]
	tst	w10, w20
	csel	w10, wzr, w11, eq
	orr	w9, w9, w10
Lloh79:
	adrp	x10, _RADEON_RESET_RLC@GOTPAGE
Lloh80:
	ldr	x10, [x10, _RADEON_RESET_RLC@GOTPAGEOFF]
Lloh81:
	ldr	w10, [x10]
Lloh82:
	adrp	x11, _SOFT_RESET_RLC@GOTPAGE
Lloh83:
	ldr	x11, [x11, _SOFT_RESET_RLC@GOTPAGEOFF]
Lloh84:
	ldr	w11, [x11]
	tst	w10, w20
	csel	w10, wzr, w11, eq
	orr	w9, w9, w10
Lloh85:
	adrp	x10, _RADEON_RESET_SEM@GOTPAGE
Lloh86:
	ldr	x10, [x10, _RADEON_RESET_SEM@GOTPAGEOFF]
Lloh87:
	ldr	w10, [x10]
Lloh88:
	adrp	x11, _SOFT_RESET_SEM@GOTPAGE
Lloh89:
	ldr	x11, [x11, _SOFT_RESET_SEM@GOTPAGEOFF]
Lloh90:
	ldr	w11, [x11]
	tst	w10, w20
	csel	w10, wzr, w11, eq
	orr	w9, w9, w10
Lloh91:
	adrp	x10, _RADEON_RESET_IH@GOTPAGE
Lloh92:
	ldr	x10, [x10, _RADEON_RESET_IH@GOTPAGEOFF]
Lloh93:
	ldr	w10, [x10]
Lloh94:
	adrp	x11, _SOFT_RESET_IH@GOTPAGE
Lloh95:
	ldr	x11, [x11, _SOFT_RESET_IH@GOTPAGEOFF]
Lloh96:
	ldr	w11, [x11]
	tst	w10, w20
	csel	w10, wzr, w11, eq
	orr	w9, w9, w10
Lloh97:
	adrp	x10, _RADEON_RESET_GRBM@GOTPAGE
Lloh98:
	ldr	x10, [x10, _RADEON_RESET_GRBM@GOTPAGEOFF]
Lloh99:
	ldr	w10, [x10]
	tst	w10, w20
	csel	w8, wzr, w8, eq
	orr	w8, w9, w8
Lloh100:
	adrp	x9, _RADEON_RESET_VMC@GOTPAGE
Lloh101:
	ldr	x9, [x9, _RADEON_RESET_VMC@GOTPAGEOFF]
Lloh102:
	ldr	w9, [x9]
Lloh103:
	adrp	x10, _SOFT_RESET_VMC@GOTPAGE
Lloh104:
	ldr	x10, [x10, _SOFT_RESET_VMC@GOTPAGEOFF]
Lloh105:
	ldr	w10, [x10]
	tst	w9, w20
	csel	w9, wzr, w10, eq
	orr	w22, w8, w9
	ldr	w8, [x19]
Lloh106:
	adrp	x9, _RADEON_IS_IGP@GOTPAGE
Lloh107:
	ldr	x9, [x9, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh108:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_14
; %bb.12:
Lloh109:
	adrp	x8, _RADEON_RESET_MC@GOTPAGE
Lloh110:
	ldr	x8, [x8, _RADEON_RESET_MC@GOTPAGEOFF]
Lloh111:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_14
; %bb.13:
Lloh112:
	adrp	x8, _SOFT_RESET_MC@GOTPAGE
Lloh113:
	ldr	x8, [x8, _SOFT_RESET_MC@GOTPAGEOFF]
Lloh114:
	ldr	w8, [x8]
	orr	w22, w8, w22
LBB0_14:
	cbz	w21, LBB0_16
; %bb.15:
Lloh115:
	adrp	x23, _GRBM_SOFT_RESET@GOTPAGE
Lloh116:
	ldr	x23, [x23, _GRBM_SOFT_RESET@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32
	orr	w20, w0, w21
	ldr	w0, [x19, #4]
Lloh117:
	adrp	x1, l_.str.2@PAGE
Lloh118:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x2, x20
	bl	_dev_info
	ldr	w0, [x23]
	mov	x1, x20
	bl	_WREG32
	ldr	w0, [x23]
	bl	_RREG32
	mov	x20, x0
	mov	w0, #50
	bl	_udelay
	bic	w1, w20, w21
	ldr	w0, [x23]
	bl	_WREG32
	ldr	w0, [x23]
	bl	_RREG32
LBB0_16:
	cbz	w22, LBB0_18
; %bb.17:
Lloh119:
	adrp	x21, _SRBM_SOFT_RESET@GOTPAGE
Lloh120:
	ldr	x21, [x21, _SRBM_SOFT_RESET@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
	orr	w20, w0, w22
	ldr	w0, [x19, #4]
Lloh121:
	adrp	x1, l_.str.3@PAGE
Lloh122:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x2, x20
	bl	_dev_info
	ldr	w0, [x21]
	mov	x1, x20
	bl	_WREG32
	ldr	w0, [x21]
	bl	_RREG32
	mov	x20, x0
	mov	w0, #50
	bl	_udelay
	bic	w1, w20, w22
	ldr	w0, [x21]
	bl	_WREG32
	ldr	w0, [x21]
	bl	_RREG32
LBB0_18:
	mov	w0, #50
	bl	_udelay
	add	x1, sp, #8
	mov	x0, x19
	bl	_evergreen_mc_resume
	mov	w0, #50
	bl	_udelay
	mov	x0, x19
	bl	_evergreen_print_gpu_status_regs
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
LBB0_19:
	.cfi_def_cfa wsp, 0
	.cfi_same_value w30
	.cfi_same_value w29
	.cfi_same_value w19
	.cfi_same_value w20
	.cfi_same_value w21
	.cfi_same_value w22
	.cfi_same_value w23
	.cfi_same_value w24
	ret
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh6
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpAdd	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh24
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh112, Lloh113, Lloh114
	.loh AdrpAdd	Lloh117, Lloh118
	.loh AdrpLdrGot	Lloh115, Lloh116
	.loh AdrpAdd	Lloh121, Lloh122
	.loh AdrpLdrGot	Lloh119, Lloh120
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"GPU softreset: 0x%08X\n"

	.comm	_CP_ME_CNTL,4,2                 ; @CP_ME_CNTL
	.comm	_CP_ME_HALT,4,2                 ; @CP_ME_HALT
	.comm	_CP_PFP_HALT,4,2                ; @CP_PFP_HALT
	.comm	_RADEON_RESET_DMA,4,2           ; @RADEON_RESET_DMA
	.comm	_DMA_RB_CNTL,4,2                ; @DMA_RB_CNTL
	.comm	_DMA_RB_ENABLE,4,2              ; @DMA_RB_ENABLE
l_.str.1:                               ; @.str.1
	.asciz	"Wait for MC idle timedout !\n"

	.comm	_RADEON_RESET_GFX,4,2           ; @RADEON_RESET_GFX
	.comm	_RADEON_RESET_COMPUTE,4,2       ; @RADEON_RESET_COMPUTE
	.comm	_SOFT_RESET_DB,4,2              ; @SOFT_RESET_DB
	.comm	_SOFT_RESET_CB,4,2              ; @SOFT_RESET_CB
	.comm	_SOFT_RESET_PA,4,2              ; @SOFT_RESET_PA
	.comm	_SOFT_RESET_SC,4,2              ; @SOFT_RESET_SC
	.comm	_SOFT_RESET_SPI,4,2             ; @SOFT_RESET_SPI
	.comm	_SOFT_RESET_SX,4,2              ; @SOFT_RESET_SX
	.comm	_SOFT_RESET_SH,4,2              ; @SOFT_RESET_SH
	.comm	_SOFT_RESET_TC,4,2              ; @SOFT_RESET_TC
	.comm	_SOFT_RESET_TA,4,2              ; @SOFT_RESET_TA
	.comm	_SOFT_RESET_VC,4,2              ; @SOFT_RESET_VC
	.comm	_SOFT_RESET_VGT,4,2             ; @SOFT_RESET_VGT
	.comm	_RADEON_RESET_CP,4,2            ; @RADEON_RESET_CP
	.comm	_SOFT_RESET_CP,4,2              ; @SOFT_RESET_CP
	.comm	_SOFT_RESET_GRBM,4,2            ; @SOFT_RESET_GRBM
	.comm	_SOFT_RESET_DMA,4,2             ; @SOFT_RESET_DMA
	.comm	_RADEON_RESET_DISPLAY,4,2       ; @RADEON_RESET_DISPLAY
	.comm	_SOFT_RESET_DC,4,2              ; @SOFT_RESET_DC
	.comm	_RADEON_RESET_RLC,4,2           ; @RADEON_RESET_RLC
	.comm	_SOFT_RESET_RLC,4,2             ; @SOFT_RESET_RLC
	.comm	_RADEON_RESET_SEM,4,2           ; @RADEON_RESET_SEM
	.comm	_SOFT_RESET_SEM,4,2             ; @SOFT_RESET_SEM
	.comm	_RADEON_RESET_IH,4,2            ; @RADEON_RESET_IH
	.comm	_SOFT_RESET_IH,4,2              ; @SOFT_RESET_IH
	.comm	_RADEON_RESET_GRBM,4,2          ; @RADEON_RESET_GRBM
	.comm	_RADEON_RESET_VMC,4,2           ; @RADEON_RESET_VMC
	.comm	_SOFT_RESET_VMC,4,2             ; @SOFT_RESET_VMC
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
	.comm	_RADEON_RESET_MC,4,2            ; @RADEON_RESET_MC
	.comm	_SOFT_RESET_MC,4,2              ; @SOFT_RESET_MC
	.comm	_GRBM_SOFT_RESET,4,2            ; @GRBM_SOFT_RESET
l_.str.2:                               ; @.str.2
	.asciz	"GRBM_SOFT_RESET=0x%08X\n"

	.comm	_SRBM_SOFT_RESET,4,2            ; @SRBM_SOFT_RESET
l_.str.3:                               ; @.str.3
	.asciz	"SRBM_SOFT_RESET=0x%08X\n"

	.no_dead_strip	_evergreen_gpu_soft_reset
.subsections_via_symbols
