	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function psp_v11_0_init_microcode
_psp_v11_0_init_microcode:              ## @psp_v11_0_init_microcode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -48(%rbp)
	movq	(%rdi), %r13
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG
	movl	(%r13), %eax
	addl	$-128, %eax
	cmpl	$5, %eax
	jae	LBB0_1
## %bb.2:
	cltq
	leaq	l_reltable.psp_v11_0_init_microcode(%rip), %rcx
	movslq	(%rcx,%rax,4), %r14
	addq	%rcx, %r14
	jmp	LBB0_3
LBB0_1:
	xorl	%eax, %eax
	callq	_BUG
                                        ## implicit-def: $r14
LBB0_3:
	leaq	L_.str.6(%rip), %rdx
	leaq	-80(%rbp), %r15
	movq	%r15, %rdi
	movl	$30, %esi
	movq	%r14, %rcx
	callq	_snprintf
	leaq	64(%r13), %rbx
	movl	144(%r13), %edx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	_request_firmware
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	LBB0_21
## %bb.4:
	movq	(%rbx), %rdi
	callq	_amdgpu_ucode_validate
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	LBB0_21
## %bb.5:
	movq	(%rbx), %rax
	movq	(%rax), %rbx
	movq	%rbx, %rdi
	callq	_amdgpu_ucode_print_psp_hdr
	cmpl	$1, (%rbx)
	jne	LBB0_24
## %bb.6:
	movl	16(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 8(%r13)
	movl	20(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 12(%r13)
	movl	28(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 16(%r13)
	movl	24(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 20(%r13)
	movl	8(%rbx), %edi
	callq	_le32_to_cpu
	cltq
	leaq	(%rbx,%rax,4), %r15
	movq	%r15, 112(%r13)
	movl	24(%rbx), %edi
	callq	_le32_to_cpu
	cltq
	leaq	(%r15,%rax,4), %rax
	movq	%rax, 136(%r13)
	movl	4(%rbx), %eax
	cmpl	$1, %eax
	jne	LBB0_8
## %bb.7:
	movq	64(%r13), %rax
	movq	(%rax), %r15
	movl	12(%r15), %edi
	callq	_le32_to_cpu
	movl	%eax, 24(%r13)
	movq	112(%r13), %r12
	movl	8(%r15), %edi
	callq	_le32_to_cpu
	cltq
	leaq	(%r12,%rax,4), %rax
	movq	%rax, 128(%r13)
	movl	4(%r15), %edi
	callq	_le32_to_cpu
	movl	%eax, 28(%r13)
	movq	112(%r13), %r12
	movl	(%r15), %edi
	callq	_le32_to_cpu
	cltq
	leaq	(%r12,%rax,4), %rax
	movq	%rax, 120(%r13)
	movl	4(%rbx), %eax
LBB0_8:
	cmpl	$2, %eax
	jne	LBB0_10
## %bb.9:
	movq	64(%r13), %rax
	movq	(%rax), %rbx
	movl	4(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 28(%r13)
	movq	112(%r13), %r15
	movl	(%rbx), %edi
	callq	_le32_to_cpu
	cltq
	leaq	(%r15,%rax,4), %rax
	movq	%rax, 120(%r13)
LBB0_10:
	leaq	L_.str.8(%rip), %rdx
	leaq	-80(%rbp), %rbx
	movq	%rbx, %rdi
	movl	$30, %esi
	movq	%r14, %rcx
	callq	_snprintf
	leaq	72(%r13), %r15
	movl	144(%r13), %edx
	movq	%r15, %rdi
	movq	%rbx, %rsi
	callq	_request_firmware
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	LBB0_20
## %bb.11:
	movq	(%r15), %rdi
	callq	_amdgpu_ucode_validate
	movl	%eax, %r12d
	testl	%eax, %eax
	je	LBB0_12
LBB0_20:
	movq	(%r15), %rdi
	callq	_release_firmware
	movq	$0, (%r15)
	jmp	LBB0_21
LBB0_24:
	movl	144(%r13), %edi
	leaq	L_.str.7(%rip), %rsi
	xorl	%r12d, %r12d
	xorl	%eax, %eax
	callq	_dev_err
	movq	_EINVAL@GOTPCREL(%rip), %rax
	subl	(%rax), %r12d
LBB0_21:
	movl	144(%r13), %edi
	leaq	L_.str.10(%rip), %rsi
	leaq	-80(%rbp), %rdx
	xorl	%eax, %eax
	callq	_dev_err
	movq	64(%r13), %rdi
	callq	_release_firmware
	movq	$0, 64(%r13)
LBB0_22:
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	cmpq	-48(%rbp), %rax
	jne	LBB0_25
## %bb.23:
	movl	%r12d, %eax
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_12:
	movq	72(%r13), %rax
	movq	(%rax), %rbx
	movl	16(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 32(%r13)
	movl	20(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 36(%r13)
	movl	12(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 40(%r13)
	movl	8(%rbx), %edi
	callq	_le32_to_cpu
	cltq
	leaq	(%rbx,%rax,4), %rax
	movq	%rax, 104(%r13)
	movl	(%r13), %eax
	xorl	%r12d, %r12d
	leal	-129(%rax), %ecx
	cmpl	$4, %ecx
	jb	LBB0_22
## %bb.13:
	cmpl	$128, %eax
	jne	LBB0_18
## %bb.14:
	leaq	L_.str.9(%rip), %rdx
	leaq	-80(%rbp), %rbx
	movq	%rbx, %rdi
	movl	$30, %esi
	movq	%r14, %rcx
	callq	_snprintf
	leaq	80(%r13), %r14
	movl	144(%r13), %edx
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	_request_firmware
	movq	80(%r13), %rdi
	testl	%eax, %eax
	je	LBB0_16
## %bb.15:
	callq	_release_firmware
	movq	$0, 80(%r13)
	movl	144(%r13), %edi
	leaq	L_.str.10(%rip), %rsi
	leaq	-80(%rbp), %rdx
	callq	_dev_info
	jmp	LBB0_22
LBB0_18:
	xorl	%r12d, %r12d
	xorl	%eax, %eax
	callq	_BUG
	jmp	LBB0_22
LBB0_16:
	callq	_amdgpu_ucode_validate
	movq	(%r14), %rdi
	testl	%eax, %eax
	je	LBB0_17
## %bb.19:
	movl	%eax, %ebx
	callq	_release_firmware
	movq	$0, (%r14)
	movl	%ebx, %r12d
	jmp	LBB0_20
LBB0_17:
	movq	(%rdi), %rbx
	movl	24(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 44(%r13)
	movl	20(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 48(%r13)
	movl	16(%rbx), %edi
	callq	_le32_to_cpu
	cltq
	leaq	(%rbx,%rax,4), %rax
	movq	%rax, 88(%r13)
	movl	12(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 52(%r13)
	movl	8(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 56(%r13)
	movl	4(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 60(%r13)
	movq	88(%r13), %r14
	movl	(%rbx), %edi
	callq	_le32_to_cpu
	cltq
	leaq	(%r14,%rax,4), %rax
	movq	%rax, 96(%r13)
	jmp	LBB0_22
LBB0_25:
	callq	___stack_chk_fail
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"\n"

L_.str.1:                               ## @.str.1
	.asciz	"vega20"

L_.str.2:                               ## @.str.2
	.asciz	"navi10"

L_.str.3:                               ## @.str.3
	.asciz	"navi14"

L_.str.4:                               ## @.str.4
	.asciz	"navi12"

L_.str.5:                               ## @.str.5
	.asciz	"arcturus"

L_.str.6:                               ## @.str.6
	.asciz	"amdgpu/%s_sos.bin"

L_.str.7:                               ## @.str.7
	.asciz	"Unsupported psp sos firmware\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
L_.str.8:                               ## @.str.8
	.asciz	"amdgpu/%s_asd.bin"

L_.str.9:                               ## @.str.9
	.asciz	"amdgpu/%s_ta.bin"

L_.str.10:                              ## @.str.10
	.asciz	"psp v11.0: Failed to load firmware \"%s\"\n"

	.no_dead_strip	_psp_v11_0_init_microcode
	.section	__TEXT,__const
	.p2align	2                               ## @reltable.psp_v11_0_init_microcode
l_reltable.psp_v11_0_init_microcode:
	.long	L_.str.1-l_reltable.psp_v11_0_init_microcode
	.long	L_.str.3-l_reltable.psp_v11_0_init_microcode
	.long	L_.str.4-l_reltable.psp_v11_0_init_microcode
	.long	L_.str.2-l_reltable.psp_v11_0_init_microcode
	.long	L_.str.5-l_reltable.psp_v11_0_init_microcode

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function psp_v11_0_init_microcode
_psp_v11_0_init_microcode:              ; @psp_v11_0_init_microcode
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
Lloh0:
	adrp	x8, ___stack_chk_guard@GOTPAGE
Lloh1:
	ldr	x8, [x8, ___stack_chk_guard@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	str	x8, [sp, #40]
	ldr	x22, [x0]
Lloh3:
	adrp	x0, l_.str@PAGE
Lloh4:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG
	ldr	w8, [x22]
	sub	w8, w8, #128
	cmp	w8, #5
	b.hs	LBB0_2
; %bb.1:
Lloh5:
	adrp	x9, l_switch.table.psp_v11_0_init_microcode@PAGE
Lloh6:
	add	x9, x9, l_switch.table.psp_v11_0_init_microcode@PAGEOFF
	ldr	x19, [x9, w8, sxtw #3]
	b	LBB0_3
LBB0_2:
	bl	_BUG
                                        ; implicit-def: $x19
LBB0_3:
Lloh7:
	adrp	x2, l_.str.6@PAGE
Lloh8:
	add	x2, x2, l_.str.6@PAGEOFF
	add	x23, sp, #10
	add	x0, sp, #10
	mov	w1, #30
	mov	x3, x19
	bl	_snprintf
	add	x20, x22, #64
	ldr	w2, [x22, #144]
	add	x1, sp, #10
	mov	x0, x20
	bl	_request_firmware
	mov	x21, x0
	cbnz	w0, LBB0_14
; %bb.4:
	ldr	x0, [x20]
	bl	_amdgpu_ucode_validate
	mov	x21, x0
	cbnz	w0, LBB0_14
; %bb.5:
	ldr	x8, [x20]
	ldr	x20, [x8]
	mov	x0, x20
	bl	_amdgpu_ucode_print_psp_hdr
	ldr	w8, [x20]
	cmp	w8, #1
	b.ne	LBB0_13
; %bb.6:
	ldr	w0, [x20, #16]
	bl	_le32_to_cpu
	str	w0, [x22, #8]
	ldr	w0, [x20, #20]
	bl	_le32_to_cpu
	str	w0, [x22, #12]
	ldr	w0, [x20, #28]
	bl	_le32_to_cpu
	str	w0, [x22, #16]
	ldr	w0, [x20, #24]
	bl	_le32_to_cpu
	str	w0, [x22, #20]
	ldr	w0, [x20, #8]
	bl	_le32_to_cpu
	add	x21, x20, w0, sxtw #2
	str	x21, [x22, #112]
	ldr	w0, [x20, #24]
	bl	_le32_to_cpu
	add	x8, x21, w0, sxtw #2
	str	x8, [x22, #136]
	ldr	w8, [x20, #4]
	cmp	w8, #1
	b.ne	LBB0_8
; %bb.7:
	ldr	x8, [x22, #64]
	ldr	x21, [x8]
	ldr	w0, [x21, #12]
	bl	_le32_to_cpu
	str	w0, [x22, #24]
	ldr	x24, [x22, #112]
	ldr	w0, [x21, #8]
	bl	_le32_to_cpu
	add	x8, x24, w0, sxtw #2
	str	x8, [x22, #128]
	ldr	w0, [x21, #4]
	bl	_le32_to_cpu
	str	w0, [x22, #28]
	ldr	x24, [x22, #112]
	ldr	w0, [x21]
	bl	_le32_to_cpu
	add	x8, x24, w0, sxtw #2
	str	x8, [x22, #120]
	ldr	w8, [x20, #4]
LBB0_8:
	cmp	w8, #2
	b.ne	LBB0_10
; %bb.9:
	ldr	x8, [x22, #64]
	ldr	x20, [x8]
	ldr	w0, [x20, #4]
	bl	_le32_to_cpu
	str	w0, [x22, #28]
	ldr	x21, [x22, #112]
	ldr	w0, [x20]
	bl	_le32_to_cpu
	add	x8, x21, w0, sxtw #2
	str	x8, [x22, #120]
LBB0_10:
Lloh9:
	adrp	x2, l_.str.8@PAGE
Lloh10:
	add	x2, x2, l_.str.8@PAGEOFF
	add	x0, sp, #10
	mov	w1, #30
	mov	x3, x19
	bl	_snprintf
	add	x20, x22, #72
	ldr	w2, [x22, #144]
	add	x1, sp, #10
	mov	x0, x20
	bl	_request_firmware
	mov	x21, x0
	cbnz	w0, LBB0_12
; %bb.11:
	ldr	x0, [x20]
	bl	_amdgpu_ucode_validate
	mov	x21, x0
	cbz	w0, LBB0_17
LBB0_12:
	ldr	x0, [x20]
	bl	_release_firmware
	str	xzr, [x20]
	b	LBB0_14
LBB0_13:
	ldr	w0, [x22, #144]
Lloh11:
	adrp	x1, l_.str.7@PAGE
Lloh12:
	add	x1, x1, l_.str.7@PAGEOFF
	bl	_dev_err
Lloh13:
	adrp	x8, _EINVAL@GOTPAGE
Lloh14:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
	neg	w21, w8
LBB0_14:
	ldr	w0, [x22, #144]
	str	x23, [sp]
Lloh16:
	adrp	x1, l_.str.10@PAGE
Lloh17:
	add	x1, x1, l_.str.10@PAGEOFF
	bl	_dev_err
	ldr	x0, [x22, #64]
	bl	_release_firmware
	str	xzr, [x22, #64]
LBB0_15:
	ldr	x8, [sp, #40]
Lloh18:
	adrp	x9, ___stack_chk_guard@GOTPAGE
Lloh19:
	ldr	x9, [x9, ___stack_chk_guard@GOTPAGEOFF]
Lloh20:
	ldr	x9, [x9]
	cmp	x9, x8
	b.ne	LBB0_26
; %bb.16:
	mov	x0, x21
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
LBB0_17:
	ldr	x8, [x22, #72]
	ldr	x21, [x8]
	ldr	w0, [x21, #16]
	bl	_le32_to_cpu
	str	w0, [x22, #32]
	ldr	w0, [x21, #20]
	bl	_le32_to_cpu
	str	w0, [x22, #36]
	ldr	w0, [x21, #12]
	bl	_le32_to_cpu
	str	w0, [x22, #40]
	ldr	w0, [x21, #8]
	bl	_le32_to_cpu
	add	x8, x21, w0, sxtw #2
	str	x8, [x22, #104]
	ldr	w8, [x22]
	sub	w9, w8, #129
	cmp	w9, #4
	b.hs	LBB0_19
; %bb.18:
	mov	w21, #0
	b	LBB0_15
LBB0_19:
	cmp	w8, #128
	b.ne	LBB0_22
; %bb.20:
Lloh21:
	adrp	x2, l_.str.9@PAGE
Lloh22:
	add	x2, x2, l_.str.9@PAGEOFF
	add	x0, sp, #10
	mov	w1, #30
	mov	x3, x19
	bl	_snprintf
	add	x19, x22, #80
	ldr	w2, [x22, #144]
	add	x1, sp, #10
	mov	x0, x19
	bl	_request_firmware
	mov	x8, x0
	ldr	x0, [x22, #80]
	cbz	w8, LBB0_23
; %bb.21:
	bl	_release_firmware
	str	xzr, [x22, #80]
	ldr	w0, [x22, #144]
Lloh23:
	adrp	x1, l_.str.10@PAGE
Lloh24:
	add	x1, x1, l_.str.10@PAGEOFF
	add	x2, sp, #10
	bl	_dev_info
	mov	w21, #0
	b	LBB0_15
LBB0_22:
	bl	_BUG
	mov	w21, #0
	b	LBB0_15
LBB0_23:
	bl	_amdgpu_ucode_validate
	mov	x21, x0
	ldr	x0, [x19]
	cbz	w21, LBB0_25
; %bb.24:
	bl	_release_firmware
	str	xzr, [x19]
	b	LBB0_12
LBB0_25:
	ldr	x19, [x0]
	ldr	w0, [x19, #24]
	bl	_le32_to_cpu
	str	w0, [x22, #44]
	ldr	w0, [x19, #20]
	bl	_le32_to_cpu
	str	w0, [x22, #48]
	ldr	w0, [x19, #16]
	bl	_le32_to_cpu
	add	x8, x19, w0, sxtw #2
	str	x8, [x22, #88]
	ldr	w0, [x19, #12]
	bl	_le32_to_cpu
	str	w0, [x22, #52]
	ldr	w0, [x19, #8]
	bl	_le32_to_cpu
	str	w0, [x22, #56]
	ldr	w0, [x19, #4]
	bl	_le32_to_cpu
	str	w0, [x22, #60]
	ldr	x20, [x22, #88]
	ldr	w0, [x19]
	bl	_le32_to_cpu
	add	x8, x20, w0, sxtw #2
	str	x8, [x22, #96]
	b	LBB0_15
LBB0_26:
	bl	___stack_chk_fail
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpAdd	Lloh7, Lloh8
	.loh AdrpAdd	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpAdd	Lloh11, Lloh12
	.loh AdrpAdd	Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpAdd	Lloh21, Lloh22
	.loh AdrpAdd	Lloh23, Lloh24
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"\n"

l_.str.1:                               ; @.str.1
	.asciz	"vega20"

l_.str.2:                               ; @.str.2
	.asciz	"navi10"

l_.str.3:                               ; @.str.3
	.asciz	"navi14"

l_.str.4:                               ; @.str.4
	.asciz	"navi12"

l_.str.5:                               ; @.str.5
	.asciz	"arcturus"

l_.str.6:                               ; @.str.6
	.asciz	"amdgpu/%s_sos.bin"

l_.str.7:                               ; @.str.7
	.asciz	"Unsupported psp sos firmware\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
l_.str.8:                               ; @.str.8
	.asciz	"amdgpu/%s_asd.bin"

l_.str.9:                               ; @.str.9
	.asciz	"amdgpu/%s_ta.bin"

l_.str.10:                              ; @.str.10
	.asciz	"psp v11.0: Failed to load firmware \"%s\"\n"

	.no_dead_strip	_psp_v11_0_init_microcode
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.psp_v11_0_init_microcode
l_switch.table.psp_v11_0_init_microcode:
	.quad	l_.str.1
	.quad	l_.str.3
	.quad	l_.str.4
	.quad	l_.str.2
	.quad	l_.str.5

.subsections_via_symbols
