	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_fence_driver_start_ring ## -- Begin function radeon_fence_driver_start_ring
	.p2align	4, 0x90
_radeon_fence_driver_start_ring:        ## @radeon_fence_driver_start_ring
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %rbx
	movq	(%rdi), %rax
	movslq	%esi, %r15
	movq	%r15, %r12
	shlq	$5, %r12
	movl	(%rax,%r12), %esi
	callq	_radeon_scratch_free
	cmpq	$0, 32(%rbx)
	je	LBB0_1
LBB0_2:
	movq	(%rbx), %rax
	movl	$0, (%rax,%r12)
	movq	_R600_RING_TYPE_UVD_INDEX@GOTPCREL(%rip), %rcx
	cmpl	%r14d, (%rcx)
	jne	LBB0_3
## %bb.4:
	movq	64(%rbx), %rax
	movl	(%rax), %edi
	movl	$8, %esi
	callq	_ALIGN
	movslq	%eax, %rcx
	leaq	(,%rcx,4), %rdx
	addq	56(%rbx), %rdx
	movq	(%rbx), %rax
	movq	%rdx, 8(%rax,%r12)
	addq	48(%rbx), %rcx
	jmp	LBB0_9
LBB0_1:
	leaq	(,%r15,4), %rsi
	addq	72(%rbx), %rsi
	movq	%rbx, %rdi
	callq	_radeon_ring_supports_scratch_reg
	testl	%eax, %eax
	je	LBB0_2
## %bb.5:
	movq	(%rbx), %rsi
	addq	%r12, %rsi
	movq	%rbx, %rdi
	callq	_radeon_scratch_get
	testl	%eax, %eax
	je	LBB0_7
## %bb.6:
	movl	%eax, %r15d
	movl	8(%rbx), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
	jmp	LBB0_10
LBB0_3:
	movq	_R600_WB_EVENT_OFFSET@GOTPCREL(%rip), %rcx
	movslq	(%rcx), %rcx
	leaq	(%rcx,%r15,4), %rcx
	leal	3(%rcx), %edx
	testl	%ecx, %ecx
	cmovnsl	%ecx, %edx
	sarl	$2, %edx
	movslq	%edx, %rdx
	shlq	$2, %rdx
	addq	24(%rbx), %rdx
	movq	%rdx, 8(%rax,%r12)
	jmp	LBB0_8
LBB0_7:
	movq	_RADEON_WB_SCRATCH_OFFSET@GOTPCREL(%rip), %rcx
	movq	(%rbx), %rax
	movl	(%rax,%r12), %edx
	addl	(%rcx), %edx
	subl	40(%rbx), %edx
	leal	3(%rdx), %ecx
	testl	%edx, %edx
	cmovnsl	%edx, %ecx
	sarl	$2, %ecx
	movslq	%ecx, %rcx
	shlq	$2, %rcx
	addq	24(%rbx), %rcx
	movq	%rcx, 8(%rax,%r12)
	movslq	%edx, %rcx
LBB0_8:
	addq	16(%rbx), %rcx
LBB0_9:
	movq	%rcx, 16(%rax,%r12)
	leaq	(%rax,%r12), %rdi
	addq	$24, %rdi
	callq	_atomic64_read
	movq	%rbx, %rdi
	movl	%eax, %esi
	movl	%r14d, %edx
	callq	_radeon_fence_write
	movq	(%rbx), %rax
	movl	$1, 4(%rax,%r12)
	movl	8(%rbx), %edi
	movq	8(%rax,%r12), %r8
	movq	16(%rax,%r12), %rcx
	leaq	L_.str.1(%rip), %rsi
	movl	%r14d, %edx
	callq	_dev_info
	xorl	%r15d, %r15d
LBB0_10:
	movl	%r15d, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_R600_RING_TYPE_UVD_INDEX,4,2   ## @R600_RING_TYPE_UVD_INDEX
	.comm	_R600_WB_EVENT_OFFSET,4,2       ## @R600_WB_EVENT_OFFSET
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"fence failed to get scratch register\n"

	.comm	_RADEON_WB_SCRATCH_OFFSET,4,2   ## @RADEON_WB_SCRATCH_OFFSET
L_.str.1:                               ## @.str.1
	.asciz	"fence driver on ring %d use gpu addr 0x%016llx and cpu addr 0x%p\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_fence_driver_start_ring ; -- Begin function radeon_fence_driver_start_ring
	.p2align	2
_radeon_fence_driver_start_ring:        ; @radeon_fence_driver_start_ring
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x1
	mov	x20, x0
	ldr	x8, [x0]
	sxtw	x23, w19
	sbfiz	x9, x19, #5, #32
	ldr	w1, [x8, x9]
	bl	_radeon_scratch_free
	ldr	x8, [x20, #32]
	lsl	x22, x23, #5
	cbz	x8, LBB0_3
LBB0_1:
	ldr	x8, [x20]
	str	wzr, [x8, x22]
Lloh0:
	adrp	x9, _R600_RING_TYPE_UVD_INDEX@GOTPAGE
Lloh1:
	ldr	x9, [x9, _R600_RING_TYPE_UVD_INDEX@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	cmp	w9, w19
	b.ne	LBB0_6
; %bb.2:
	ldr	x8, [x20, #64]
	ldr	w0, [x8]
	mov	w1, #8
	bl	_ALIGN
	ldp	x9, x8, [x20, #48]
	add	x10, x8, w0, sxtw #2
	ldr	x8, [x20]
	add	x11, x8, x23, lsl #5
	str	x10, [x11, #8]
	add	x9, x9, w0, sxtw
	b	LBB0_8
LBB0_3:
	ldr	x8, [x20, #72]
	add	x1, x8, x23, lsl #2
	mov	x0, x20
	bl	_radeon_ring_supports_scratch_reg
	cbz	w0, LBB0_1
; %bb.4:
	ldr	x8, [x20]
	add	x1, x8, x23, lsl #5
	mov	x0, x20
	bl	_radeon_scratch_get
	cbz	w0, LBB0_7
; %bb.5:
	mov	x21, x0
	ldr	w0, [x20, #8]
Lloh3:
	adrp	x1, l_.str@PAGE
Lloh4:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
	b	LBB0_9
LBB0_6:
Lloh5:
	adrp	x9, _R600_WB_EVENT_OFFSET@GOTPAGE
Lloh6:
	ldr	x9, [x9, _R600_WB_EVENT_OFFSET@GOTPAGEOFF]
Lloh7:
	ldrsw	x9, [x9]
	add	x9, x9, w19, sxtw #2
	add	w10, w9, #3
	cmp	w9, #0
	csel	w10, w10, w9, lt
	asr	w10, w10, #2
	ldp	x12, x11, [x20, #16]
	add	x10, x11, w10, sxtw #2
	add	x11, x8, x23, lsl #5
	str	x10, [x11, #8]
	add	x9, x12, x9
	b	LBB0_8
LBB0_7:
Lloh8:
	adrp	x8, _RADEON_WB_SCRATCH_OFFSET@GOTPAGE
Lloh9:
	ldr	x8, [x8, _RADEON_WB_SCRATCH_OFFSET@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x8]
	ldr	x8, [x20]
	add	x10, x8, x23, lsl #5
	ldr	w11, [x10]
	ldr	w12, [x20, #40]
	add	w9, w11, w9
	sub	w9, w9, w12
	add	w11, w9, #3
	cmp	w9, #0
	csel	w11, w11, w9, lt
	asr	w11, w11, #2
	ldp	x13, x12, [x20, #16]
	add	x11, x12, w11, sxtw #2
	str	x11, [x10, #8]
	add	x9, x13, w9, sxtw
LBB0_8:
	add	x8, x8, x22
	str	x9, [x8, #16]
	add	x0, x8, #24
	bl	_atomic64_read
	mov	x1, x0
	mov	x0, x20
	mov	x2, x19
	bl	_radeon_fence_write
	ldr	x8, [x20]
	add	x8, x8, x22
	mov	w9, #1
	str	w9, [x8, #4]
	ldr	w0, [x20, #8]
	ldp	x4, x3, [x8, #8]
Lloh11:
	adrp	x1, l_.str.1@PAGE
Lloh12:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x2, x19
	bl	_dev_info
	mov	w21, #0
LBB0_9:
	mov	x0, x21
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpAdd	Lloh11, Lloh12
	.cfi_endproc
                                        ; -- End function
	.comm	_R600_RING_TYPE_UVD_INDEX,4,2   ; @R600_RING_TYPE_UVD_INDEX
	.comm	_R600_WB_EVENT_OFFSET,4,2       ; @R600_WB_EVENT_OFFSET
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"fence failed to get scratch register\n"

	.comm	_RADEON_WB_SCRATCH_OFFSET,4,2   ; @RADEON_WB_SCRATCH_OFFSET
l_.str.1:                               ; @.str.1
	.asciz	"fence driver on ring %d use gpu addr 0x%016llx and cpu addr 0x%p\n"

.subsections_via_symbols
