	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v2_0_enable_static_power_gating
_vcn_v2_0_enable_static_power_gating:   ## @vcn_v2_0_enable_static_power_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_AMD_PG_SUPPORT_VCN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rdi)
	je	LBB0_1
## %bb.2:
	movq	_VCN@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movq	_mmUVD_POWER_STATUS@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_UVD_POWER_STATUS__UVD_POWER_STATUS_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movq	_UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movl	(%r14), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movq	_UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %edx
	shll	%cl, %edx
	movq	_UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %esi
	shll	%cl, %esi
	movq	_UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %edi
	shll	%cl, %edi
	movq	_UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %eax
	shll	%cl, %eax
	movq	_UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %ebx
	shll	%cl, %ebx
	orl	%edx, %esi
	movq	_UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %edx
	shll	%cl, %edx
	orl	%edi, %eax
	orl	%esi, %eax
	movq	_UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %esi
	shll	%cl, %esi
	orl	%ebx, %edx
	orl	%edx, %esi
	movq	_UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %edx
	shll	%cl, %edx
	movl	$2, %r15d
	orl	%eax, %esi
	movq	_UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %edi
	shll	%cl, %edi
	orl	%edx, %edi
	movq	_UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %eax
	shll	%cl, %eax
	orl	%edi, %eax
	orl	%esi, %eax
	movl	(%r14), %edi
	movq	_mmUVD_PGFSM_CONFIG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	_UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %edx
	shll	%cl, %edx
	movq	_UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %esi
	shll	%cl, %esi
	movq	_UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %edi
	shll	%cl, %edi
	movq	_UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %eax
	shll	%cl, %eax
	movq	_UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %ebx
	shll	%cl, %ebx
	orl	%edx, %esi
	movq	_UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %edx
	shll	%cl, %edx
	orl	%edi, %eax
	orl	%esi, %eax
	movq	_UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %esi
	shll	%cl, %esi
	orl	%ebx, %edx
	orl	%edx, %esi
	movq	_UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %edx
	shll	%cl, %edx
	orl	%eax, %esi
	movq	_UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %eax
	shll	%cl, %eax
	movq	_UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r15d
	orl	%edx, %eax
	orl	%eax, %r15d
	orl	%esi, %r15d
	movl	(%r14), %edi
	movq	_mmUVD_PGFSM_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	movl	%r15d, %ecx
	movl	$1048575, %r8d                  ## imm = 0xFFFFF
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_SOC15_WAIT_ON_RREG             ## TAILCALL
LBB0_1:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_PG_SUPPORT_VCN,4,2         ## @AMD_PG_SUPPORT_VCN
	.comm	_VCN,4,2                        ## @VCN
	.comm	_mmUVD_POWER_STATUS,4,2         ## @mmUVD_POWER_STATUS
	.comm	_UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,4,2 ## @UVD_POWER_STATUS__UVD_POWER_STATUS_MASK
	.comm	_UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,4,2 ## @UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF
	.comm	_UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
	.comm	_mmUVD_PGFSM_CONFIG,4,2         ## @mmUVD_PGFSM_CONFIG
	.comm	_UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT,4,2 ## @UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
	.comm	_UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT,4,2 ## @UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
	.comm	_UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT,4,2 ## @UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
	.comm	_UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT,4,2 ## @UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
	.comm	_UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT,4,2 ## @UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
	.comm	_UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT,4,2 ## @UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
	.comm	_UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT,4,2 ## @UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
	.comm	_UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT,4,2 ## @UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
	.comm	_UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT,4,2 ## @UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
	.comm	_UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT,4,2 ## @UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
	.comm	_mmUVD_PGFSM_STATUS,4,2         ## @mmUVD_PGFSM_STATUS
	.no_dead_strip	_vcn_v2_0_enable_static_power_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v2_0_enable_static_power_gating
_vcn_v2_0_enable_static_power_gating:   ; @vcn_v2_0_enable_static_power_gating
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _AMD_PG_SUPPORT_VCN@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_PG_SUPPORT_VCN@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
Lloh3:
	adrp	x19, _VCN@GOTPAGE
Lloh4:
	ldr	x19, [x19, _VCN@GOTPAGEOFF]
	ldr	w0, [x19]
Lloh5:
	adrp	x20, _mmUVD_POWER_STATUS@GOTPAGE
Lloh6:
	ldr	x20, [x20, _mmUVD_POWER_STATUS@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh7:
	adrp	x8, _UVD_POWER_STATUS__UVD_POWER_STATUS_MASK@GOTPAGE
Lloh8:
	ldr	x8, [x8, _UVD_POWER_STATUS__UVD_POWER_STATUS_MASK@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh10:
	adrp	x9, _UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF@GOTPAGE
Lloh11:
	ldr	x9, [x9, _UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
	orr	w3, w8, w9
	ldr	w0, [x19]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_WREG32_SOC15
Lloh13:
	adrp	x8, _UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT@GOTPAGE
Lloh14:
	ldr	x8, [x8, _UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
	mov	w20, #2
Lloh16:
	adrp	x9, _UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT@GOTPAGE
Lloh17:
	ldr	x9, [x9, _UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT@GOTPAGEOFF]
	lsl	w8, w20, w8
Lloh18:
	ldr	w9, [x9]
	lsl	w9, w20, w9
	orr	w8, w9, w8
Lloh19:
	adrp	x9, _UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT@GOTPAGE
Lloh20:
	ldr	x9, [x9, _UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	lsl	w9, w20, w9
	orr	w8, w8, w9
Lloh22:
	adrp	x9, _UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT@GOTPAGE
Lloh23:
	ldr	x9, [x9, _UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	lsl	w9, w20, w9
	orr	w8, w8, w9
Lloh25:
	adrp	x9, _UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT@GOTPAGE
Lloh26:
	ldr	x9, [x9, _UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
	lsl	w9, w20, w9
	orr	w8, w8, w9
Lloh28:
	adrp	x9, _UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT@GOTPAGE
Lloh29:
	ldr	x9, [x9, _UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
	lsl	w9, w20, w9
	orr	w8, w8, w9
Lloh31:
	adrp	x9, _UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT@GOTPAGE
Lloh32:
	ldr	x9, [x9, _UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh33:
	ldr	w9, [x9]
	lsl	w9, w20, w9
Lloh34:
	adrp	x10, _UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT@GOTPAGE
Lloh35:
	ldr	x10, [x10, _UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh36:
	ldr	w9, [x10]
	lsl	w9, w20, w9
	orr	w8, w8, w9
Lloh37:
	adrp	x9, _UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT@GOTPAGE
Lloh38:
	ldr	x9, [x9, _UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh39:
	ldr	w9, [x9]
	lsl	w9, w20, w9
	orr	w8, w8, w9
Lloh40:
	adrp	x9, _UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT@GOTPAGE
Lloh41:
	ldr	x9, [x9, _UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh42:
	ldr	w9, [x9]
	lsl	w9, w20, w9
	orr	w3, w8, w9
	ldr	w0, [x19]
Lloh43:
	adrp	x8, _mmUVD_PGFSM_CONFIG@GOTPAGE
Lloh44:
	ldr	x8, [x8, _mmUVD_PGFSM_CONFIG@GOTPAGEOFF]
Lloh45:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
Lloh46:
	adrp	x8, _UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT@GOTPAGE
Lloh47:
	ldr	x8, [x8, _UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT@GOTPAGEOFF]
Lloh48:
	ldr	w8, [x8]
	lsl	w8, w20, w8
Lloh49:
	adrp	x9, _UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT@GOTPAGE
Lloh50:
	ldr	x9, [x9, _UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT@GOTPAGEOFF]
Lloh51:
	ldr	w9, [x9]
	lsl	w9, w20, w9
Lloh52:
	adrp	x10, _UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT@GOTPAGE
Lloh53:
	ldr	x10, [x10, _UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh54:
	ldr	w9, [x10]
	lsl	w9, w20, w9
	orr	w8, w8, w9
Lloh55:
	adrp	x9, _UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT@GOTPAGE
Lloh56:
	ldr	x9, [x9, _UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT@GOTPAGEOFF]
Lloh57:
	ldr	w9, [x9]
	lsl	w9, w20, w9
	orr	w8, w8, w9
Lloh58:
	adrp	x9, _UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT@GOTPAGE
Lloh59:
	ldr	x9, [x9, _UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT@GOTPAGEOFF]
Lloh60:
	ldr	w9, [x9]
	lsl	w9, w20, w9
	orr	w8, w8, w9
Lloh61:
	adrp	x9, _UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT@GOTPAGE
Lloh62:
	ldr	x9, [x9, _UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT@GOTPAGEOFF]
Lloh63:
	ldr	w9, [x9]
	lsl	w9, w20, w9
	orr	w8, w8, w9
Lloh64:
	adrp	x9, _UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT@GOTPAGE
Lloh65:
	ldr	x9, [x9, _UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT@GOTPAGEOFF]
Lloh66:
	ldr	w9, [x9]
	lsl	w9, w20, w9
	orr	w8, w8, w9
Lloh67:
	adrp	x9, _UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT@GOTPAGE
Lloh68:
	ldr	x9, [x9, _UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT@GOTPAGEOFF]
Lloh69:
	ldr	w9, [x9]
	lsl	w9, w20, w9
Lloh70:
	adrp	x10, _UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT@GOTPAGE
Lloh71:
	ldr	x10, [x10, _UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh72:
	ldr	w9, [x10]
	lsl	w9, w20, w9
	orr	w8, w8, w9
Lloh73:
	adrp	x9, _UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT@GOTPAGE
Lloh74:
	ldr	x9, [x9, _UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT@GOTPAGEOFF]
Lloh75:
	ldr	w9, [x9]
	lsl	w9, w20, w9
	orr	w3, w8, w9
	ldr	w0, [x19]
Lloh76:
	adrp	x8, _mmUVD_PGFSM_STATUS@GOTPAGE
Lloh77:
	ldr	x8, [x8, _mmUVD_PGFSM_STATUS@GOTPAGEOFF]
Lloh78:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w4, #1048575
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_SOC15_WAIT_ON_RREG
LBB0_2:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_PG_SUPPORT_VCN,4,2         ; @AMD_PG_SUPPORT_VCN
	.comm	_VCN,4,2                        ; @VCN
	.comm	_mmUVD_POWER_STATUS,4,2         ; @mmUVD_POWER_STATUS
	.comm	_UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,4,2 ; @UVD_POWER_STATUS__UVD_POWER_STATUS_MASK
	.comm	_UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,4,2 ; @UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF
	.comm	_UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
	.comm	_mmUVD_PGFSM_CONFIG,4,2         ; @mmUVD_PGFSM_CONFIG
	.comm	_UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT,4,2 ; @UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
	.comm	_UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT,4,2 ; @UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
	.comm	_UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT,4,2 ; @UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
	.comm	_UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT,4,2 ; @UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
	.comm	_UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT,4,2 ; @UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
	.comm	_UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT,4,2 ; @UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
	.comm	_UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT,4,2 ; @UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
	.comm	_UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT,4,2 ; @UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
	.comm	_UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT,4,2 ; @UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
	.comm	_UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT,4,2 ; @UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
	.comm	_mmUVD_PGFSM_STATUS,4,2         ; @mmUVD_PGFSM_STATUS
	.no_dead_strip	_vcn_v2_0_enable_static_power_gating
.subsections_via_symbols
