	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_dsi_set_phy_timing
_tegra_dsi_set_phy_timing:              ## @tegra_dsi_set_phy_timing
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r14
	movq	%rsi, %r13
	movq	%rdi, %r15
	movl	%r13d, %eax
	shll	$8, %eax
	subl	%r13d, %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	.p2align	4, 0x90
LBB0_1:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %edi
	movq	%r13, %rsi
	movl	$1, %edx
	callq	_DSI_TIMING_FIELD
	movl	%eax, %ebx
	shll	$24, %ebx
	movl	4(%r14), %edi
	movq	%r13, %rsi
	xorl	%edx, %edx
	callq	_DSI_TIMING_FIELD
	shll	$16, %eax
	orl	%eax, %ebx
	movl	8(%r14), %edi
	movq	%r13, %rsi
	movl	$3, %edx
	callq	_DSI_TIMING_FIELD
	movl	%eax, %r12d
	shll	$8, %r12d
	movl	12(%r14), %edi
	movq	%r13, %rsi
	movl	$1, %edx
	callq	_DSI_TIMING_FIELD
	orl	%eax, %r12d
	orl	%ebx, %r12d
	movq	_DSI_PHY_TIMING_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%r12d, %esi
	callq	_tegra_dsi_writel
	movl	16(%r14), %edi
	movq	%r13, %rsi
	movl	$1, %edx
	callq	_DSI_TIMING_FIELD
	movl	%eax, %r12d
	shll	$24, %r12d
	movl	20(%r14), %edi
	movq	%r13, %rsi
	movl	$1, %edx
	callq	_DSI_TIMING_FIELD
	shll	$16, %eax
	orl	%eax, %r12d
	movl	24(%r14), %edi
	movq	%r13, %rsi
	movl	$1, %edx
	callq	_DSI_TIMING_FIELD
	movl	%eax, %ebx
	shll	$8, %ebx
	movl	28(%r14), %edi
	movq	%r13, %rsi
	movl	$1, %edx
	callq	_DSI_TIMING_FIELD
	orl	%eax, %ebx
	orl	%r12d, %ebx
	movq	_DSI_PHY_TIMING_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_tegra_dsi_writel
	movl	32(%r14), %edi
	movq	%r13, %rsi
	movl	$1, %edx
	callq	_DSI_TIMING_FIELD
	movl	%eax, %ebx
	shll	$16, %ebx
	movl	36(%r14), %edi
	movq	%r13, %rsi
	movl	$1, %edx
	callq	_DSI_TIMING_FIELD
	shll	$8, %eax
	orl	%eax, %ebx
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	movq	%r13, %rsi
	xorl	%edx, %edx
	callq	_DSI_TIMING_FIELD
	orl	%eax, %ebx
	movq	_DSI_PHY_TIMING_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_tegra_dsi_writel
	movl	40(%r14), %edi
	movq	%r13, %rsi
	movl	$1, %edx
	callq	_DSI_TIMING_FIELD
	movl	%eax, %ebx
	shll	$16, %ebx
	movl	44(%r14), %edi
	movq	%r13, %rsi
	movl	$1, %edx
	callq	_DSI_TIMING_FIELD
	shll	$8, %eax
	orl	%eax, %ebx
	movl	48(%r14), %edi
	movq	%r13, %rsi
	movl	$1, %edx
	callq	_DSI_TIMING_FIELD
	orl	%eax, %ebx
	movq	_DSI_BTA_TIMING@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_tegra_dsi_writel
	movq	(%r15), %r15
	testq	%r15, %r15
	jne	LBB0_1
## %bb.2:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DSI_PHY_TIMING_0,4,2           ## @DSI_PHY_TIMING_0
	.comm	_DSI_PHY_TIMING_1,4,2           ## @DSI_PHY_TIMING_1
	.comm	_DSI_PHY_TIMING_2,4,2           ## @DSI_PHY_TIMING_2
	.comm	_DSI_BTA_TIMING,4,2             ## @DSI_BTA_TIMING
	.no_dead_strip	_tegra_dsi_set_phy_timing
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_dsi_set_phy_timing
_tegra_dsi_set_phy_timing:              ; @tegra_dsi_set_phy_timing
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x2
	mov	x20, x1
	mov	x21, x0
	lsl	w8, w20, #8
	sub	w22, w8, w20
Lloh0:
	adrp	x24, _DSI_PHY_TIMING_0@GOTPAGE
Lloh1:
	ldr	x24, [x24, _DSI_PHY_TIMING_0@GOTPAGEOFF]
Lloh2:
	adrp	x25, _DSI_PHY_TIMING_1@GOTPAGE
Lloh3:
	ldr	x25, [x25, _DSI_PHY_TIMING_1@GOTPAGEOFF]
Lloh4:
	adrp	x26, _DSI_PHY_TIMING_2@GOTPAGE
Lloh5:
	ldr	x26, [x26, _DSI_PHY_TIMING_2@GOTPAGEOFF]
Lloh6:
	adrp	x27, _DSI_BTA_TIMING@GOTPAGE
Lloh7:
	ldr	x27, [x27, _DSI_BTA_TIMING@GOTPAGEOFF]
LBB0_1:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x19]
	mov	x1, x20
	mov	w2, #1
	bl	_DSI_TIMING_FIELD
	mov	x23, x0
	ldr	w0, [x19, #4]
	mov	x1, x20
	mov	w2, #0
	bl	_DSI_TIMING_FIELD
	lsl	w8, w0, #16
	orr	w23, w8, w23, lsl #24
	ldr	w0, [x19, #8]
	mov	x1, x20
	mov	w2, #3
	bl	_DSI_TIMING_FIELD
	orr	w23, w23, w0, lsl #8
	ldr	w0, [x19, #12]
	mov	x1, x20
	mov	w2, #1
	bl	_DSI_TIMING_FIELD
	orr	w1, w23, w0
	ldr	w2, [x24]
	mov	x0, x21
	bl	_tegra_dsi_writel
	ldr	w0, [x19, #16]
	mov	x1, x20
	mov	w2, #1
	bl	_DSI_TIMING_FIELD
	mov	x23, x0
	ldr	w0, [x19, #20]
	mov	x1, x20
	mov	w2, #1
	bl	_DSI_TIMING_FIELD
	lsl	w8, w0, #16
	orr	w23, w8, w23, lsl #24
	ldr	w0, [x19, #24]
	mov	x1, x20
	mov	w2, #1
	bl	_DSI_TIMING_FIELD
	orr	w23, w23, w0, lsl #8
	ldr	w0, [x19, #28]
	mov	x1, x20
	mov	w2, #1
	bl	_DSI_TIMING_FIELD
	orr	w1, w23, w0
	ldr	w2, [x25]
	mov	x0, x21
	bl	_tegra_dsi_writel
	ldr	w0, [x19, #32]
	mov	x1, x20
	mov	w2, #1
	bl	_DSI_TIMING_FIELD
	mov	x23, x0
	ldr	w0, [x19, #36]
	mov	x1, x20
	mov	w2, #1
	bl	_DSI_TIMING_FIELD
	lsl	w8, w0, #8
	orr	w23, w8, w23, lsl #16
	mov	x0, x22
	mov	x1, x20
	mov	w2, #0
	bl	_DSI_TIMING_FIELD
	orr	w1, w23, w0
	ldr	w2, [x26]
	mov	x0, x21
	bl	_tegra_dsi_writel
	ldr	w0, [x19, #40]
	mov	x1, x20
	mov	w2, #1
	bl	_DSI_TIMING_FIELD
	mov	x23, x0
	ldr	w0, [x19, #44]
	mov	x1, x20
	mov	w2, #1
	bl	_DSI_TIMING_FIELD
	lsl	w8, w0, #8
	orr	w23, w8, w23, lsl #16
	ldr	w0, [x19, #48]
	mov	x1, x20
	mov	w2, #1
	bl	_DSI_TIMING_FIELD
	orr	w1, w23, w0
	ldr	w2, [x27]
	mov	x0, x21
	bl	_tegra_dsi_writel
	ldr	x21, [x21]
	cbnz	x21, LBB0_1
; %bb.2:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_DSI_PHY_TIMING_0,4,2           ; @DSI_PHY_TIMING_0
	.comm	_DSI_PHY_TIMING_1,4,2           ; @DSI_PHY_TIMING_1
	.comm	_DSI_PHY_TIMING_2,4,2           ; @DSI_PHY_TIMING_2
	.comm	_DSI_BTA_TIMING,4,2             ; @DSI_BTA_TIMING
	.no_dead_strip	_tegra_dsi_set_phy_timing
.subsections_via_symbols
