	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dsi_pll_enable_pll_bias
_dsi_pll_enable_pll_bias:               ## @dsi_pll_enable_pll_bias
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_REG_DSI_10nm_PHY_CMN_CTRL_0@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	addq	8(%r14), %rdi
	callq	_pll_read
	movl	%eax, %r15d
	movq	(%rbx), %rbx
	addq	8(%r14), %rbx
	movl	$5, %edi
	callq	_BIT
	orl	%eax, %r15d
	movq	%rbx, %rdi
	movl	%r15d, %esi
	callq	_pll_write
	movq	_REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r14), %rdi
	movl	$192, %esi
	callq	_pll_write
	movl	$250, %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_ndelay                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_REG_DSI_10nm_PHY_CMN_CTRL_0,8,3 ## @REG_DSI_10nm_PHY_CMN_CTRL_0
	.comm	_REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES,8,3 ## @REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES
	.no_dead_strip	_dsi_pll_enable_pll_bias
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dsi_pll_enable_pll_bias
_dsi_pll_enable_pll_bias:               ; @dsi_pll_enable_pll_bias
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x8, [x0, #8]
Lloh0:
	adrp	x21, _REG_DSI_10nm_PHY_CMN_CTRL_0@GOTPAGE
Lloh1:
	ldr	x21, [x21, _REG_DSI_10nm_PHY_CMN_CTRL_0@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_pll_read
	mov	x20, x0
	ldr	x8, [x19, #8]
	ldr	x9, [x21]
	add	x21, x9, x8
	mov	w0, #5
	bl	_BIT
	orr	w1, w0, w20
	mov	x0, x21
	bl	_pll_write
	ldr	x8, [x19]
Lloh2:
	adrp	x9, _REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES@GOTPAGE
Lloh3:
	ldr	x9, [x9, _REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES@GOTPAGEOFF]
Lloh4:
	ldr	x9, [x9]
	add	x0, x9, x8
	mov	w1, #192
	bl	_pll_write
	mov	w0, #250
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_ndelay
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_REG_DSI_10nm_PHY_CMN_CTRL_0,8,3 ; @REG_DSI_10nm_PHY_CMN_CTRL_0
	.comm	_REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES,8,3 ; @REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES
	.no_dead_strip	_dsi_pll_enable_pll_bias
.subsections_via_symbols
