	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v2_5_start
_vcn_v2_5_start:                        ## @vcn_v2_5_start
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	(%rdi), %eax
	testl	%eax, %eax
	movq	%rdi, -48(%rbp)                 ## 8-byte Spill
	jle	LBB0_5
## %bb.1:
	xorl	%ebx, %ebx
	movq	_UVD@GOTPCREL(%rip), %r14
	movq	_UVD_POWER_STATUS__UVD_POWER_STATUS_MASK@GOTPCREL(%rip), %r12
	movq	_mmUVD_STATUS@GOTPCREL(%rip), %r13
	movq	_UVD_STATUS__UVD_BUSY@GOTPCREL(%rip), %r15
	jmp	LBB0_2
	.p2align	4, 0x90
LBB0_4:                                 ##   in Loop: Header=BB0_2 Depth=1
	incl	%ebx
	cmpl	%eax, %ebx
	jge	LBB0_5
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movl	4(%rdi), %ecx
	btl	%ebx, %ecx
	jb	LBB0_4
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movl	(%r14), %edi
	movq	_mmUVD_POWER_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%ebx, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r12), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	(%r14), %edi
	movl	(%r13), %edx
	movl	%ebx, %esi
	callq	_RREG32_SOC15
	orl	(%r15), %eax
	movl	(%r14), %edi
	movl	(%r13), %edx
	movl	%ebx, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movl	(%rdi), %eax
	jmp	LBB0_4
LBB0_5:
	callq	_vcn_v2_5_disable_clock_gating
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movl	(%rdi), %eax
	testl	%eax, %eax
	jle	LBB0_10
## %bb.6:
	xorl	%r15d, %r15d
	movq	_UVD@GOTPCREL(%rip), %r14
	movq	_mmUVD_LMI_CTRL@GOTPCREL(%rip), %r12
	movq	_mmUVD_MPC_CNTL@GOTPCREL(%rip), %r13
	jmp	LBB0_7
	.p2align	4, 0x90
LBB0_9:                                 ##   in Loop: Header=BB0_7 Depth=1
	incl	%r15d
	cmpl	%eax, %r15d
	jge	LBB0_10
LBB0_7:                                 ## =>This Inner Loop Header: Depth=1
	movl	4(%rdi), %ecx
	btl	%r15d, %ecx
	jb	LBB0_9
## %bb.8:                               ##   in Loop: Header=BB0_7 Depth=1
	movl	(%r14), %edi
	movq	_mmUVD_VCPU_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_VCPU_CNTL__CLK_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	callq	_WREG32_P
	movl	(%r14), %edi
	movq	_mmUVD_MASTINT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_MASTINT_EN__VCPU_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	(%r14), %edi
	movl	(%r12), %edx
	movl	%r15d, %esi
	callq	_RREG32_SOC15
	andl	$-256, %eax
	movl	(%r14), %edi
	movq	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_LMI_CTRL__MASK_MC_URGENT_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r12), %edx
	movq	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	orl	$8, %eax
	movl	%r15d, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movl	(%r13), %edx
	movl	%r15d, %esi
	callq	_RREG32_SOC15
	movq	_UVD_MPC_CNTL__REPLACEMENT_MODE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movq	_UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT@GOTPCREL(%rip), %rcx
	movzbl	(%rcx), %ecx
	movl	$2, %ebx
	shll	%cl, %ebx
	andl	%eax, %edx
	orl	%edx, %ebx
	movq	_VCN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r13), %edx
	movl	%r15d, %esi
	movl	%ebx, %ecx
	callq	_WREG32_SOC15
	movq	_UVD_MPC_SET_MUXA0__VARA_2__SHIFT@GOTPCREL(%rip), %rax
	movzbl	(%rax), %ecx
	movl	$2, %esi
	shll	%cl, %esi
	movl	(%r14), %edi
	movq	_UVD_MPC_SET_MUXA0__VARA_1__SHIFT@GOTPCREL(%rip), %rax
	movzbl	(%rax), %edx
	movq	_UVD_MPC_SET_MUXA0__VARA_3__SHIFT@GOTPCREL(%rip), %rax
	movzbl	(%rax), %ecx
	movl	$3, %ebx
	shll	%cl, %ebx
	movq	_UVD_MPC_SET_MUXA0__VARA_4__SHIFT@GOTPCREL(%rip), %rax
	movzbl	(%rax), %ecx
	movl	$4, %eax
	shll	%cl, %eax
	btsl	%edx, %esi
	movq	_mmUVD_MPC_SET_MUXA0@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	%ebx, %eax
	orl	%esi, %eax
	movl	%r15d, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	_UVD_MPC_SET_MUXB0__VARB_2__SHIFT@GOTPCREL(%rip), %rax
	movzbl	(%rax), %ecx
	movl	$2, %esi
	shll	%cl, %esi
	movl	(%r14), %edi
	movq	_UVD_MPC_SET_MUXB0__VARB_1__SHIFT@GOTPCREL(%rip), %rax
	movzbl	(%rax), %edx
	movq	_UVD_MPC_SET_MUXB0__VARB_3__SHIFT@GOTPCREL(%rip), %rax
	movzbl	(%rax), %ecx
	movl	$3, %ebx
	shll	%cl, %ebx
	movq	_UVD_MPC_SET_MUXB0__VARB_4__SHIFT@GOTPCREL(%rip), %rax
	movzbl	(%rax), %ecx
	movl	$4, %eax
	shll	%cl, %eax
	btsl	%edx, %esi
	movq	_mmUVD_MPC_SET_MUXB0@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	%ebx, %eax
	orl	%esi, %eax
	movl	%r15d, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_MPC_SET_MUX@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_UVD_MPC_SET_MUX__SET_1__SHIFT@GOTPCREL(%rip), %rax
	movzbl	(%rax), %esi
	movq	_UVD_MPC_SET_MUX__SET_2__SHIFT@GOTPCREL(%rip), %rax
	movzbl	(%rax), %ecx
	movl	$2, %eax
	shll	%cl, %eax
	btsl	%esi, %eax
	movl	%r15d, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movl	(%rdi), %eax
	jmp	LBB0_9
LBB0_10:
	callq	_vcn_v2_5_mc_resume
	movq	-48(%rbp), %rsi                 ## 8-byte Reload
	movl	(%rsi), %eax
	testl	%eax, %eax
	jle	LBB0_24
## %bb.11:
	xorl	%r15d, %r15d
	movq	_UVD@GOTPCREL(%rip), %r12
	movq	_mmUVD_VCPU_CNTL@GOTPCREL(%rip), %r13
	jmp	LBB0_12
	.p2align	4, 0x90
LBB0_22:                                ##   in Loop: Header=BB0_12 Depth=1
	movl	(%r12), %edi
	movq	_mmUVD_MASTINT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_MASTINT_EN__VCPU_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	callq	_WREG32_P
	movl	(%r12), %edi
	movq	_mmUVD_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_STATUS__VCPU_REPORT__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %edx
	shll	%cl, %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	(%r12), %edi
	movq	_mmUVD_LMI_RBC_RB_VMID@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movq	8(%rax), %r13
	leaq	(,%r15,8), %rax
	leaq	(%rax,%rax,2), %r14
	movl	8(%r13,%r14), %edi
	callq	_order_base_2
	movq	_UVD_RBC_RB_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_RB_BUFSZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%edi, %edi
	movl	%eax, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_BLKSZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_NO_FETCH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_NO_UPDATE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_RPTR_WR_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r12), %edi
	movq	_mmUVD_RBC_RB_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%r15d, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %ebx
	movq	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movl	12(%r13,%r14), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%r15d, %esi
	movl	-52(%rbp), %edx                 ## 4-byte Reload
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %ebx
	movq	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movl	12(%r13,%r14), %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	movl	%r15d, %esi
	movl	-52(%rbp), %edx                 ## 4-byte Reload
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmUVD_RBC_RB_RPTR@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movl	%r15d, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movl	(%rbx), %edx
	movl	%r15d, %esi
	callq	_RREG32_SOC15
	movl	%eax, 16(%r13,%r14)
	movq	%r14, -64(%rbp)                 ## 8-byte Spill
	movl	(%r12), %ebx
	movq	_mmUVD_RBC_RB_WPTR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r13d
	movl	%eax, %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%r15d, %esi
	movl	%r13d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movq	8(%rax), %rax
	movq	(%rax,%r14), %r13
	movl	(%r12), %ebx
	movq	_mmUVD_RB_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	8(%r13), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%r15d, %esi
	movl	%r14d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %ebx
	movq	_mmUVD_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	8(%r13), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%r15d, %esi
	movl	%r14d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmUVD_RB_BASE_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	4(%r13), %ecx
	movl	%r15d, %esi
	callq	_WREG32_SOC15
	movl	(%r12), %ebx
	movq	_mmUVD_RB_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	4(%r13), %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	movl	%r15d, %esi
	movl	%r14d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmUVD_RB_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r13), %eax
	leal	3(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$2, %ecx
	movl	%r15d, %esi
	callq	_WREG32_SOC15
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movq	8(%rax), %rax
	movq	-64(%rbp), %rcx                 ## 8-byte Reload
	movq	(%rax,%rcx), %r14
	movl	(%r12), %ebx
	movq	_mmUVD_RB_RPTR2@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	20(%r14), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%r15d, %esi
	movl	%r13d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %ebx
	movq	_mmUVD_RB_WPTR2@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	20(%r14), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%r15d, %esi
	movl	%r13d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmUVD_RB_BASE_LO2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	16(%r14), %ecx
	movl	%r15d, %esi
	callq	_WREG32_SOC15
	movl	(%r12), %ebx
	movq	_mmUVD_RB_BASE_HI2@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	16(%r14), %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	movl	%r15d, %esi
	movl	%r13d, %edx
	movq	_mmUVD_VCPU_CNTL@GOTPCREL(%rip), %r13
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmUVD_RB_SIZE2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	12(%r14), %eax
	leal	3(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$2, %ecx
	movl	%r15d, %esi
	callq	_WREG32_SOC15
	movq	-48(%rbp), %rsi                 ## 8-byte Reload
	movl	(%rsi), %eax
LBB0_23:                                ##   in Loop: Header=BB0_12 Depth=1
	incq	%r15
	movslq	%eax, %rcx
	cmpq	%rcx, %r15
	jge	LBB0_24
LBB0_12:                                ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_14 Depth 2
                                        ##       Child Loop BB0_15 Depth 3
	movl	4(%rsi), %ecx
	btl	%r15d, %ecx
	jb	LBB0_23
## %bb.13:                              ##   in Loop: Header=BB0_12 Depth=1
	movl	(%r12), %edi
	movq	_mmUVD_GFX8_ADDR_CONFIG@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	movl	16(%rsi), %ecx
	movq	%rsi, %rbx
	movl	%r15d, %esi
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movl	(%r14), %edx
	movl	16(%rbx), %ecx
	movl	%r15d, %esi
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmUVD_LMI_CTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	xorl	%r14d, %r14d
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	(%r12), %edi
	movq	_mmUVD_RB_ARB_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_RB_ARB_CTRL__VCPU_DIS_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	(%r12), %edi
	movl	(%r13), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_VCPU_CNTL__BLK_RST_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
LBB0_14:                                ##   Parent Loop BB0_12 Depth=1
                                        ## =>  This Loop Header: Depth=2
                                        ##       Child Loop BB0_15 Depth 3
	movl	$100, %ebx
	jmp	LBB0_15
	.p2align	4, 0x90
LBB0_18:                                ##   in Loop: Header=BB0_15 Depth=3
	movl	$10, %edi
	callq	_mdelay
	decl	%ebx
	je	LBB0_20
LBB0_15:                                ##   Parent Loop BB0_12 Depth=1
                                        ##     Parent Loop BB0_14 Depth=2
                                        ## =>    This Inner Loop Header: Depth=3
	movl	(%r12), %edi
	movq	_mmUVD_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_RREG32_SOC15
	testb	$2, %al
	jne	LBB0_22
## %bb.16:                              ##   in Loop: Header=BB0_15 Depth=3
	movq	_amdgpu_emu_mode@GOTPCREL(%rip), %rax
	cmpl	$1, (%rax)
	jne	LBB0_18
## %bb.17:                              ##   in Loop: Header=BB0_15 Depth=3
	movl	$500, %edi                      ## imm = 0x1F4
	callq	_msleep
	decl	%ebx
	jne	LBB0_15
LBB0_20:                                ##   in Loop: Header=BB0_14 Depth=2
	leaq	L_.str(%rip), %rdi
	callq	_DRM_ERROR
	movl	(%r12), %edi
	movl	(%r13), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_VCPU_CNTL__BLK_RST_MASK@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	callq	_WREG32_P
	movl	$10, %edi
	callq	_mdelay
	movl	(%r12), %edi
	movl	(%r13), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%rbx), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	$10, %edi
	callq	_mdelay
	incl	%r14d
	cmpl	$10, %r14d
	jne	LBB0_14
## %bb.21:
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_ERROR
	movl	$-1, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_24:
	movq	%rsi, %rdi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_jpeg_v2_5_start                ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_POWER_STATUS,4,2         ## @mmUVD_POWER_STATUS
	.comm	_UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,4,2 ## @UVD_POWER_STATUS__UVD_POWER_STATUS_MASK
	.comm	_mmUVD_STATUS,4,2               ## @mmUVD_STATUS
	.comm	_UVD_STATUS__UVD_BUSY,4,2       ## @UVD_STATUS__UVD_BUSY
	.comm	_mmUVD_VCPU_CNTL,4,2            ## @mmUVD_VCPU_CNTL
	.comm	_UVD_VCPU_CNTL__CLK_EN_MASK,4,2 ## @UVD_VCPU_CNTL__CLK_EN_MASK
	.comm	_mmUVD_MASTINT_EN,4,2           ## @mmUVD_MASTINT_EN
	.comm	_UVD_MASTINT_EN__VCPU_EN_MASK,4,2 ## @UVD_MASTINT_EN__VCPU_EN_MASK
	.comm	_mmUVD_LMI_CTRL,4,2             ## @mmUVD_LMI_CTRL
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK,4,2 ## @UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK
	.comm	_UVD_LMI_CTRL__MASK_MC_URGENT_MASK,4,2 ## @UVD_LMI_CTRL__MASK_MC_URGENT_MASK
	.comm	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK,4,2 ## @UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK,4,2 ## @UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
	.comm	_mmUVD_MPC_CNTL,4,2             ## @mmUVD_MPC_CNTL
	.comm	_UVD_MPC_CNTL__REPLACEMENT_MODE_MASK,4,2 ## @UVD_MPC_CNTL__REPLACEMENT_MODE_MASK
	.comm	_UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT,4,2 ## @UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT
	.comm	_VCN,4,2                        ## @VCN
	.comm	_mmUVD_MPC_SET_MUXA0,4,2        ## @mmUVD_MPC_SET_MUXA0
	.comm	_UVD_MPC_SET_MUXA0__VARA_1__SHIFT,4,2 ## @UVD_MPC_SET_MUXA0__VARA_1__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_2__SHIFT,4,2 ## @UVD_MPC_SET_MUXA0__VARA_2__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_3__SHIFT,4,2 ## @UVD_MPC_SET_MUXA0__VARA_3__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_4__SHIFT,4,2 ## @UVD_MPC_SET_MUXA0__VARA_4__SHIFT
	.comm	_mmUVD_MPC_SET_MUXB0,4,2        ## @mmUVD_MPC_SET_MUXB0
	.comm	_UVD_MPC_SET_MUXB0__VARB_1__SHIFT,4,2 ## @UVD_MPC_SET_MUXB0__VARB_1__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_2__SHIFT,4,2 ## @UVD_MPC_SET_MUXB0__VARB_2__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_3__SHIFT,4,2 ## @UVD_MPC_SET_MUXB0__VARB_3__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_4__SHIFT,4,2 ## @UVD_MPC_SET_MUXB0__VARB_4__SHIFT
	.comm	_mmUVD_MPC_SET_MUX,4,2          ## @mmUVD_MPC_SET_MUX
	.comm	_UVD_MPC_SET_MUX__SET_0__SHIFT,4,2 ## @UVD_MPC_SET_MUX__SET_0__SHIFT
	.comm	_UVD_MPC_SET_MUX__SET_1__SHIFT,4,2 ## @UVD_MPC_SET_MUX__SET_1__SHIFT
	.comm	_UVD_MPC_SET_MUX__SET_2__SHIFT,4,2 ## @UVD_MPC_SET_MUX__SET_2__SHIFT
	.comm	_mmUVD_GFX8_ADDR_CONFIG,4,2     ## @mmUVD_GFX8_ADDR_CONFIG
	.comm	_mmUVD_LMI_CTRL2,4,2            ## @mmUVD_LMI_CTRL2
	.comm	_UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,4,2 ## @UVD_LMI_CTRL2__STALL_ARB_UMC_MASK
	.comm	_mmUVD_RB_ARB_CTRL,4,2          ## @mmUVD_RB_ARB_CTRL
	.comm	_UVD_RB_ARB_CTRL__VCPU_DIS_MASK,4,2 ## @UVD_RB_ARB_CTRL__VCPU_DIS_MASK
	.comm	_UVD_VCPU_CNTL__BLK_RST_MASK,4,2 ## @UVD_VCPU_CNTL__BLK_RST_MASK
	.comm	_amdgpu_emu_mode,4,2            ## @amdgpu_emu_mode
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"VCN decode not responding, trying to reset the VCPU!!!\n"

L_.str.1:                               ## @.str.1
	.asciz	"VCN decode not responding, giving up!!!\n"

	.comm	_UVD_STATUS__VCPU_REPORT__SHIFT,4,2 ## @UVD_STATUS__VCPU_REPORT__SHIFT
	.comm	_mmUVD_LMI_RBC_RB_VMID,4,2      ## @mmUVD_LMI_RBC_RB_VMID
	.comm	_UVD_RBC_RB_CNTL,4,2            ## @UVD_RBC_RB_CNTL
	.comm	_RB_BUFSZ,4,2                   ## @RB_BUFSZ
	.comm	_RB_BLKSZ,4,2                   ## @RB_BLKSZ
	.comm	_RB_NO_FETCH,4,2                ## @RB_NO_FETCH
	.comm	_RB_NO_UPDATE,4,2               ## @RB_NO_UPDATE
	.comm	_RB_RPTR_WR_EN,4,2              ## @RB_RPTR_WR_EN
	.comm	_mmUVD_RBC_RB_CNTL,4,2          ## @mmUVD_RBC_RB_CNTL
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
	.comm	_mmUVD_RBC_RB_RPTR,4,2          ## @mmUVD_RBC_RB_RPTR
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ## @mmUVD_RBC_RB_WPTR
	.comm	_mmUVD_RB_RPTR,4,2              ## @mmUVD_RB_RPTR
	.comm	_mmUVD_RB_WPTR,4,2              ## @mmUVD_RB_WPTR
	.comm	_mmUVD_RB_BASE_LO,4,2           ## @mmUVD_RB_BASE_LO
	.comm	_mmUVD_RB_BASE_HI,4,2           ## @mmUVD_RB_BASE_HI
	.comm	_mmUVD_RB_SIZE,4,2              ## @mmUVD_RB_SIZE
	.comm	_mmUVD_RB_RPTR2,4,2             ## @mmUVD_RB_RPTR2
	.comm	_mmUVD_RB_WPTR2,4,2             ## @mmUVD_RB_WPTR2
	.comm	_mmUVD_RB_BASE_LO2,4,2          ## @mmUVD_RB_BASE_LO2
	.comm	_mmUVD_RB_BASE_HI2,4,2          ## @mmUVD_RB_BASE_HI2
	.comm	_mmUVD_RB_SIZE2,4,2             ## @mmUVD_RB_SIZE2
	.no_dead_strip	_vcn_v2_5_start
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v2_5_start
_vcn_v2_5_start:                        ; @vcn_v2_5_start
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	w8, [x0]
Lloh0:
	adrp	x24, _UVD@GOTPAGE
Lloh1:
	ldr	x24, [x24, _UVD@GOTPAGEOFF]
Lloh2:
	adrp	x25, _mmUVD_STATUS@GOTPAGE
Lloh3:
	ldr	x25, [x25, _mmUVD_STATUS@GOTPAGEOFF]
	cmp	w8, #1
	b.lt	LBB0_5
; %bb.1:
	mov	w20, #0
Lloh4:
	adrp	x21, _mmUVD_POWER_STATUS@GOTPAGE
Lloh5:
	ldr	x21, [x21, _mmUVD_POWER_STATUS@GOTPAGEOFF]
Lloh6:
	adrp	x22, _UVD_POWER_STATUS__UVD_POWER_STATUS_MASK@GOTPAGE
Lloh7:
	ldr	x22, [x22, _UVD_POWER_STATUS__UVD_POWER_STATUS_MASK@GOTPAGEOFF]
Lloh8:
	adrp	x23, _UVD_STATUS__UVD_BUSY@GOTPAGE
Lloh9:
	ldr	x23, [x23, _UVD_STATUS__UVD_BUSY@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:                                 ;   in Loop: Header=BB0_3 Depth=1
	add	w20, w20, #1
	cmp	w20, w8
	b.ge	LBB0_5
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w9, [x19, #4]
	lsr	w9, w9, w20
	tbnz	w9, #0, LBB0_2
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	ldr	w0, [x24]
	ldr	w2, [x21]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x22]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w0, [x24]
	ldr	w2, [x25]
	mov	x1, x20
	bl	_RREG32_SOC15
	ldr	w8, [x23]
	orr	w3, w8, w0
	ldr	w0, [x24]
	ldr	w2, [x25]
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w8, [x19]
	b	LBB0_2
LBB0_5:
	mov	x0, x19
	bl	_vcn_v2_5_disable_clock_gating
	ldr	w8, [x19]
	cmp	w8, #1
	b.lt	LBB0_10
; %bb.6:
	mov	w20, #0
Lloh10:
	adrp	x22, _mmUVD_LMI_CTRL@GOTPAGE
Lloh11:
	ldr	x22, [x22, _mmUVD_LMI_CTRL@GOTPAGEOFF]
Lloh12:
	adrp	x21, _mmUVD_MPC_CNTL@GOTPAGE
Lloh13:
	ldr	x21, [x21, _mmUVD_MPC_CNTL@GOTPAGEOFF]
	mov	w26, #2
	mov	w28, #1
	mov	w27, #3
	mov	w23, #4
	b	LBB0_8
LBB0_7:                                 ;   in Loop: Header=BB0_8 Depth=1
	add	w20, w20, #1
	cmp	w20, w8
	b.ge	LBB0_10
LBB0_8:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w9, [x19, #4]
	lsr	w9, w9, w20
	tbnz	w9, #0, LBB0_7
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=1
	ldr	w0, [x24]
Lloh14:
	adrp	x8, _mmUVD_VCPU_CNTL@GOTPAGE
Lloh15:
	ldr	x8, [x8, _mmUVD_VCPU_CNTL@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
Lloh17:
	adrp	x8, _UVD_VCPU_CNTL__CLK_EN_MASK@GOTPAGE
Lloh18:
	ldr	x8, [x8, _UVD_VCPU_CNTL__CLK_EN_MASK@GOTPAGEOFF]
Lloh19:
	ldr	w1, [x8]
	mvn	w2, w1
	bl	_WREG32_P
	ldr	w0, [x24]
Lloh20:
	adrp	x8, _mmUVD_MASTINT_EN@GOTPAGE
Lloh21:
	ldr	x8, [x8, _mmUVD_MASTINT_EN@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
Lloh23:
	adrp	x8, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGE
Lloh24:
	ldr	x8, [x8, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w0, [x24]
	ldr	w2, [x22]
	mov	x1, x20
	bl	_RREG32_SOC15
	and	w8, w0, #0xffffff00
	ldr	w0, [x24]
	ldr	w2, [x22]
Lloh26:
	adrp	x9, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPAGE
Lloh27:
	ldr	x9, [x9, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPAGEOFF]
Lloh28:
	ldr	w9, [x9]
Lloh29:
	adrp	x10, _UVD_LMI_CTRL__MASK_MC_URGENT_MASK@GOTPAGE
Lloh30:
	ldr	x10, [x10, _UVD_LMI_CTRL__MASK_MC_URGENT_MASK@GOTPAGEOFF]
Lloh31:
	ldr	w10, [x10]
Lloh32:
	adrp	x11, _UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPAGE
Lloh33:
	ldr	x11, [x11, _UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPAGEOFF]
Lloh34:
	ldr	w11, [x11]
Lloh35:
	adrp	x12, _UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPAGE
Lloh36:
	ldr	x12, [x12, _UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPAGEOFF]
Lloh37:
	ldr	w12, [x12]
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w3, w8, #0x8
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w0, [x24]
	ldr	w2, [x21]
	mov	x1, x20
	bl	_RREG32_SOC15
Lloh38:
	adrp	x8, _UVD_MPC_CNTL__REPLACEMENT_MODE_MASK@GOTPAGE
Lloh39:
	ldr	x8, [x8, _UVD_MPC_CNTL__REPLACEMENT_MODE_MASK@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh41:
	adrp	x9, _UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT@GOTPAGE
Lloh42:
	ldr	x9, [x9, _UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
	lsl	w9, w26, w9
	orr	w3, w9, w8
Lloh44:
	adrp	x8, _VCN@GOTPAGE
Lloh45:
	ldr	x8, [x8, _VCN@GOTPAGEOFF]
Lloh46:
	ldr	w0, [x8]
	ldr	w2, [x21]
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh47:
	adrp	x8, _mmUVD_MPC_SET_MUXA0@GOTPAGE
Lloh48:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXA0@GOTPAGEOFF]
Lloh49:
	ldr	w2, [x8]
Lloh50:
	adrp	x8, _UVD_MPC_SET_MUXA0__VARA_1__SHIFT@GOTPAGE
Lloh51:
	ldr	x8, [x8, _UVD_MPC_SET_MUXA0__VARA_1__SHIFT@GOTPAGEOFF]
Lloh52:
	ldr	w8, [x8]
	lsl	w8, w28, w8
Lloh53:
	adrp	x9, _UVD_MPC_SET_MUXA0__VARA_2__SHIFT@GOTPAGE
Lloh54:
	ldr	x9, [x9, _UVD_MPC_SET_MUXA0__VARA_2__SHIFT@GOTPAGEOFF]
Lloh55:
	ldr	w9, [x9]
	lsl	w9, w26, w9
	orr	w8, w9, w8
Lloh56:
	adrp	x9, _UVD_MPC_SET_MUXA0__VARA_3__SHIFT@GOTPAGE
Lloh57:
	ldr	x9, [x9, _UVD_MPC_SET_MUXA0__VARA_3__SHIFT@GOTPAGEOFF]
Lloh58:
	ldr	w9, [x9]
	lsl	w9, w27, w9
	orr	w8, w8, w9
Lloh59:
	adrp	x9, _UVD_MPC_SET_MUXA0__VARA_4__SHIFT@GOTPAGE
Lloh60:
	ldr	x9, [x9, _UVD_MPC_SET_MUXA0__VARA_4__SHIFT@GOTPAGEOFF]
Lloh61:
	ldr	w9, [x9]
	lsl	w9, w23, w9
	orr	w3, w8, w9
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh62:
	adrp	x8, _mmUVD_MPC_SET_MUXB0@GOTPAGE
Lloh63:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXB0@GOTPAGEOFF]
Lloh64:
	ldr	w2, [x8]
Lloh65:
	adrp	x8, _UVD_MPC_SET_MUXB0__VARB_1__SHIFT@GOTPAGE
Lloh66:
	ldr	x8, [x8, _UVD_MPC_SET_MUXB0__VARB_1__SHIFT@GOTPAGEOFF]
Lloh67:
	ldr	w8, [x8]
	lsl	w8, w28, w8
Lloh68:
	adrp	x9, _UVD_MPC_SET_MUXB0__VARB_2__SHIFT@GOTPAGE
Lloh69:
	ldr	x9, [x9, _UVD_MPC_SET_MUXB0__VARB_2__SHIFT@GOTPAGEOFF]
Lloh70:
	ldr	w9, [x9]
	lsl	w9, w26, w9
	orr	w8, w9, w8
Lloh71:
	adrp	x9, _UVD_MPC_SET_MUXB0__VARB_3__SHIFT@GOTPAGE
Lloh72:
	ldr	x9, [x9, _UVD_MPC_SET_MUXB0__VARB_3__SHIFT@GOTPAGEOFF]
Lloh73:
	ldr	w9, [x9]
	lsl	w9, w27, w9
	orr	w8, w8, w9
Lloh74:
	adrp	x9, _UVD_MPC_SET_MUXB0__VARB_4__SHIFT@GOTPAGE
Lloh75:
	ldr	x9, [x9, _UVD_MPC_SET_MUXB0__VARB_4__SHIFT@GOTPAGEOFF]
Lloh76:
	ldr	w9, [x9]
	lsl	w9, w23, w9
	orr	w3, w8, w9
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh77:
	adrp	x8, _mmUVD_MPC_SET_MUX@GOTPAGE
Lloh78:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUX@GOTPAGEOFF]
Lloh79:
	ldr	w2, [x8]
Lloh80:
	adrp	x8, _UVD_MPC_SET_MUX__SET_1__SHIFT@GOTPAGE
Lloh81:
	ldr	x8, [x8, _UVD_MPC_SET_MUX__SET_1__SHIFT@GOTPAGEOFF]
Lloh82:
	ldr	w8, [x8]
	lsl	w8, w28, w8
Lloh83:
	adrp	x9, _UVD_MPC_SET_MUX__SET_2__SHIFT@GOTPAGE
Lloh84:
	ldr	x9, [x9, _UVD_MPC_SET_MUX__SET_2__SHIFT@GOTPAGEOFF]
Lloh85:
	ldr	w9, [x9]
	lsl	w9, w26, w9
	orr	w3, w9, w8
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w8, [x19]
	b	LBB0_7
LBB0_10:
	mov	x0, x19
	bl	_vcn_v2_5_mc_resume
	ldr	w8, [x19]
	cmp	w8, #1
	b.lt	LBB0_23
; %bb.11:
	mov	x20, #0
Lloh86:
	adrp	x21, _UVD_VCPU_CNTL__BLK_RST_MASK@GOTPAGE
Lloh87:
	ldr	x21, [x21, _UVD_VCPU_CNTL__BLK_RST_MASK@GOTPAGEOFF]
Lloh88:
	adrp	x28, _amdgpu_emu_mode@GOTPAGE
Lloh89:
	ldr	x28, [x28, _amdgpu_emu_mode@GOTPAGEOFF]
	b	LBB0_14
LBB0_12:                                ;   in Loop: Header=BB0_14 Depth=1
	ldr	w0, [x24]
Lloh90:
	adrp	x8, _mmUVD_MASTINT_EN@GOTPAGE
Lloh91:
	ldr	x8, [x8, _mmUVD_MASTINT_EN@GOTPAGEOFF]
Lloh92:
	ldr	w2, [x8]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
Lloh93:
	adrp	x8, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGE
Lloh94:
	ldr	x8, [x8, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGEOFF]
Lloh95:
	ldr	w1, [x8]
	mvn	w2, w1
	bl	_WREG32_P
	ldr	w0, [x24]
	ldr	w2, [x25]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
Lloh96:
	adrp	x8, _UVD_STATUS__VCPU_REPORT__SHIFT@GOTPAGE
Lloh97:
	ldr	x8, [x8, _UVD_STATUS__VCPU_REPORT__SHIFT@GOTPAGEOFF]
Lloh98:
	ldr	w8, [x8]
	mov	w9, #2
	lsl	w8, w9, w8
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w0, [x24]
Lloh99:
	adrp	x8, _mmUVD_LMI_RBC_RB_VMID@GOTPAGE
Lloh100:
	ldr	x8, [x8, _mmUVD_LMI_RBC_RB_VMID@GOTPAGEOFF]
Lloh101:
	ldr	w2, [x8]
	mov	x1, x20
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	x8, [x19, #8]
	add	x9, x20, x20, lsl #1
	lsl	x26, x9, #3
	add	x27, x8, x26
	ldr	w0, [x27, #8]
	bl	_order_base_2
	mov	x3, x0
Lloh102:
	adrp	x22, _UVD_RBC_RB_CNTL@GOTPAGE
Lloh103:
	ldr	x22, [x22, _UVD_RBC_RB_CNTL@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh104:
	adrp	x8, _RB_BUFSZ@GOTPAGE
Lloh105:
	ldr	x8, [x8, _RB_BUFSZ@GOTPAGEOFF]
Lloh106:
	ldr	w2, [x8]
	mov	w0, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x22]
Lloh107:
	adrp	x8, _RB_BLKSZ@GOTPAGE
Lloh108:
	ldr	x8, [x8, _RB_BLKSZ@GOTPAGEOFF]
Lloh109:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x22]
Lloh110:
	adrp	x8, _RB_NO_FETCH@GOTPAGE
Lloh111:
	ldr	x8, [x8, _RB_NO_FETCH@GOTPAGEOFF]
Lloh112:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x22]
Lloh113:
	adrp	x8, _RB_NO_UPDATE@GOTPAGE
Lloh114:
	ldr	x8, [x8, _RB_NO_UPDATE@GOTPAGEOFF]
Lloh115:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x22]
Lloh116:
	adrp	x8, _RB_RPTR_WR_EN@GOTPAGE
Lloh117:
	ldr	x8, [x8, _RB_RPTR_WR_EN@GOTPAGEOFF]
Lloh118:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x24]
Lloh119:
	adrp	x8, _mmUVD_RBC_RB_CNTL@GOTPAGE
Lloh120:
	ldr	x8, [x8, _mmUVD_RBC_RB_CNTL@GOTPAGEOFF]
Lloh121:
	ldr	w2, [x8]
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w22, [x24]
Lloh122:
	adrp	x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPAGE
Lloh123:
	ldr	x8, [x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh124:
	ldr	w23, [x8]
	ldr	w0, [x27, #12]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x20
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w22, [x24]
Lloh125:
	adrp	x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPAGE
Lloh126:
	ldr	x8, [x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh127:
	ldr	w23, [x8]
	ldr	w0, [x27, #12]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x20
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh128:
	adrp	x22, _mmUVD_RBC_RB_RPTR@GOTPAGE
Lloh129:
	ldr	x22, [x22, _mmUVD_RBC_RB_RPTR@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	x1, x20
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x24]
	ldr	w2, [x22]
	mov	x1, x20
	bl	_RREG32_SOC15
	str	w0, [x27, #16]
	ldr	w22, [x24]
Lloh130:
	adrp	x8, _mmUVD_RBC_RB_WPTR@GOTPAGE
Lloh131:
	ldr	x8, [x8, _mmUVD_RBC_RB_WPTR@GOTPAGEOFF]
Lloh132:
	ldr	w23, [x8]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x20
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	x8, [x19, #8]
	ldr	x27, [x8, x26]
	ldr	w22, [x24]
Lloh133:
	adrp	x8, _mmUVD_RB_RPTR@GOTPAGE
Lloh134:
	ldr	x8, [x8, _mmUVD_RB_RPTR@GOTPAGEOFF]
Lloh135:
	ldr	w23, [x8]
	ldr	w0, [x27, #8]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x20
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w22, [x24]
Lloh136:
	adrp	x8, _mmUVD_RB_WPTR@GOTPAGE
Lloh137:
	ldr	x8, [x8, _mmUVD_RB_WPTR@GOTPAGEOFF]
Lloh138:
	ldr	w23, [x8]
	ldr	w0, [x27, #8]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x20
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh139:
	adrp	x8, _mmUVD_RB_BASE_LO@GOTPAGE
Lloh140:
	ldr	x8, [x8, _mmUVD_RB_BASE_LO@GOTPAGEOFF]
Lloh141:
	ldr	w2, [x8]
	ldr	w3, [x27, #4]
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w22, [x24]
Lloh142:
	adrp	x8, _mmUVD_RB_BASE_HI@GOTPAGE
Lloh143:
	ldr	x8, [x8, _mmUVD_RB_BASE_HI@GOTPAGEOFF]
Lloh144:
	ldr	w23, [x8]
	ldr	w0, [x27, #4]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x20
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh145:
	adrp	x8, _mmUVD_RB_SIZE@GOTPAGE
Lloh146:
	ldr	x8, [x8, _mmUVD_RB_SIZE@GOTPAGEOFF]
Lloh147:
	ldr	w2, [x8]
	ldr	w8, [x27]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w3, w8, #2
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	x8, [x19, #8]
	ldr	x26, [x8, x26]
	ldr	w22, [x24]
Lloh148:
	adrp	x8, _mmUVD_RB_RPTR2@GOTPAGE
Lloh149:
	ldr	x8, [x8, _mmUVD_RB_RPTR2@GOTPAGEOFF]
Lloh150:
	ldr	w23, [x8]
	ldr	w0, [x26, #20]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x20
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w22, [x24]
Lloh151:
	adrp	x8, _mmUVD_RB_WPTR2@GOTPAGE
Lloh152:
	ldr	x8, [x8, _mmUVD_RB_WPTR2@GOTPAGEOFF]
Lloh153:
	ldr	w23, [x8]
	ldr	w0, [x26, #20]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x20
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh154:
	adrp	x8, _mmUVD_RB_BASE_LO2@GOTPAGE
Lloh155:
	ldr	x8, [x8, _mmUVD_RB_BASE_LO2@GOTPAGEOFF]
Lloh156:
	ldr	w2, [x8]
	ldr	w3, [x26, #16]
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w22, [x24]
Lloh157:
	adrp	x8, _mmUVD_RB_BASE_HI2@GOTPAGE
Lloh158:
	ldr	x8, [x8, _mmUVD_RB_BASE_HI2@GOTPAGEOFF]
Lloh159:
	ldr	w23, [x8]
	ldr	w0, [x26, #16]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x20
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh160:
	adrp	x8, _mmUVD_RB_SIZE2@GOTPAGE
Lloh161:
	ldr	x8, [x8, _mmUVD_RB_SIZE2@GOTPAGEOFF]
Lloh162:
	ldr	w2, [x8]
	ldr	w8, [x26, #12]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w3, w8, #2
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w8, [x19]
LBB0_13:                                ;   in Loop: Header=BB0_14 Depth=1
	add	x20, x20, #1
	cmp	x20, w8, sxtw
	b.ge	LBB0_23
LBB0_14:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_16 Depth 2
                                        ;       Child Loop BB0_18 Depth 3
	ldr	w9, [x19, #4]
	lsr	w9, w9, w20
	tbnz	w9, #0, LBB0_13
; %bb.15:                               ;   in Loop: Header=BB0_14 Depth=1
	ldr	w0, [x24]
Lloh163:
	adrp	x22, _mmUVD_GFX8_ADDR_CONFIG@GOTPAGE
Lloh164:
	ldr	x22, [x22, _mmUVD_GFX8_ADDR_CONFIG@GOTPAGEOFF]
	ldr	w2, [x22]
	ldr	w3, [x19, #16]
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w0, [x24]
	ldr	w2, [x22]
	ldr	w3, [x19, #16]
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh165:
	adrp	x8, _mmUVD_LMI_CTRL2@GOTPAGE
Lloh166:
	ldr	x8, [x8, _mmUVD_LMI_CTRL2@GOTPAGEOFF]
Lloh167:
	ldr	w2, [x8]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
Lloh168:
	adrp	x8, _UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPAGE
Lloh169:
	ldr	x8, [x8, _UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPAGEOFF]
Lloh170:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w0, [x24]
Lloh171:
	adrp	x8, _mmUVD_RB_ARB_CTRL@GOTPAGE
Lloh172:
	ldr	x8, [x8, _mmUVD_RB_ARB_CTRL@GOTPAGEOFF]
Lloh173:
	ldr	w2, [x8]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
Lloh174:
	adrp	x8, _UVD_RB_ARB_CTRL__VCPU_DIS_MASK@GOTPAGE
Lloh175:
	ldr	x8, [x8, _UVD_RB_ARB_CTRL__VCPU_DIS_MASK@GOTPAGEOFF]
Lloh176:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w0, [x24]
Lloh177:
	adrp	x8, _mmUVD_VCPU_CNTL@GOTPAGE
Lloh178:
	ldr	x8, [x8, _mmUVD_VCPU_CNTL@GOTPAGEOFF]
Lloh179:
	ldr	w2, [x8]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x21]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	mov	w22, #0
LBB0_16:                                ;   Parent Loop BB0_14 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_18 Depth 3
	mov	w23, #100
	b	LBB0_18
LBB0_17:                                ;   in Loop: Header=BB0_18 Depth=3
	mov	w0, #10
	bl	_mdelay
	subs	w23, w23, #1
	b.eq	LBB0_21
LBB0_18:                                ;   Parent Loop BB0_14 Depth=1
                                        ;     Parent Loop BB0_16 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	ldr	w0, [x24]
	ldr	w2, [x25]
	mov	x1, x20
	bl	_RREG32_SOC15
	tbnz	w0, #1, LBB0_12
; %bb.19:                               ;   in Loop: Header=BB0_18 Depth=3
	ldr	w8, [x28]
	cmp	w8, #1
	b.ne	LBB0_17
; %bb.20:                               ;   in Loop: Header=BB0_18 Depth=3
	mov	w0, #500
	bl	_msleep
	subs	w23, w23, #1
	b.ne	LBB0_18
LBB0_21:                                ;   in Loop: Header=BB0_16 Depth=2
Lloh180:
	adrp	x0, l_.str@PAGE
Lloh181:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_ERROR
	ldr	w0, [x24]
Lloh182:
	adrp	x23, _mmUVD_VCPU_CNTL@GOTPAGE
Lloh183:
	ldr	x23, [x23, _mmUVD_VCPU_CNTL@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	ldr	w1, [x21]
	mvn	w2, w1
	bl	_WREG32_P
	mov	w0, #10
	bl	_mdelay
	ldr	w0, [x24]
	ldr	w2, [x23]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x21]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	mov	w0, #10
	bl	_mdelay
	add	w22, w22, #1
	cmp	w22, #10
	b.ne	LBB0_16
; %bb.22:
Lloh184:
	adrp	x0, l_.str.1@PAGE
Lloh185:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_ERROR
	mov	w0, #-1
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
LBB0_23:
	mov	x0, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_jpeg_v2_5_start
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh88, Lloh89
	.loh AdrpLdrGot	Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh160, Lloh161, Lloh162
	.loh AdrpLdrGotLdr	Lloh157, Lloh158, Lloh159
	.loh AdrpLdrGotLdr	Lloh154, Lloh155, Lloh156
	.loh AdrpLdrGotLdr	Lloh151, Lloh152, Lloh153
	.loh AdrpLdrGotLdr	Lloh148, Lloh149, Lloh150
	.loh AdrpLdrGotLdr	Lloh145, Lloh146, Lloh147
	.loh AdrpLdrGotLdr	Lloh142, Lloh143, Lloh144
	.loh AdrpLdrGotLdr	Lloh139, Lloh140, Lloh141
	.loh AdrpLdrGotLdr	Lloh136, Lloh137, Lloh138
	.loh AdrpLdrGotLdr	Lloh133, Lloh134, Lloh135
	.loh AdrpLdrGotLdr	Lloh130, Lloh131, Lloh132
	.loh AdrpLdrGot	Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGot	Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh177, Lloh178, Lloh179
	.loh AdrpLdrGotLdr	Lloh174, Lloh175, Lloh176
	.loh AdrpLdrGotLdr	Lloh171, Lloh172, Lloh173
	.loh AdrpLdrGotLdr	Lloh168, Lloh169, Lloh170
	.loh AdrpLdrGotLdr	Lloh165, Lloh166, Lloh167
	.loh AdrpLdrGot	Lloh163, Lloh164
	.loh AdrpLdrGot	Lloh182, Lloh183
	.loh AdrpAdd	Lloh180, Lloh181
	.loh AdrpAdd	Lloh184, Lloh185
	.cfi_endproc
                                        ; -- End function
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_POWER_STATUS,4,2         ; @mmUVD_POWER_STATUS
	.comm	_UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,4,2 ; @UVD_POWER_STATUS__UVD_POWER_STATUS_MASK
	.comm	_mmUVD_STATUS,4,2               ; @mmUVD_STATUS
	.comm	_UVD_STATUS__UVD_BUSY,4,2       ; @UVD_STATUS__UVD_BUSY
	.comm	_mmUVD_VCPU_CNTL,4,2            ; @mmUVD_VCPU_CNTL
	.comm	_UVD_VCPU_CNTL__CLK_EN_MASK,4,2 ; @UVD_VCPU_CNTL__CLK_EN_MASK
	.comm	_mmUVD_MASTINT_EN,4,2           ; @mmUVD_MASTINT_EN
	.comm	_UVD_MASTINT_EN__VCPU_EN_MASK,4,2 ; @UVD_MASTINT_EN__VCPU_EN_MASK
	.comm	_mmUVD_LMI_CTRL,4,2             ; @mmUVD_LMI_CTRL
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK,4,2 ; @UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK
	.comm	_UVD_LMI_CTRL__MASK_MC_URGENT_MASK,4,2 ; @UVD_LMI_CTRL__MASK_MC_URGENT_MASK
	.comm	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK,4,2 ; @UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK,4,2 ; @UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
	.comm	_mmUVD_MPC_CNTL,4,2             ; @mmUVD_MPC_CNTL
	.comm	_UVD_MPC_CNTL__REPLACEMENT_MODE_MASK,4,2 ; @UVD_MPC_CNTL__REPLACEMENT_MODE_MASK
	.comm	_UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT,4,2 ; @UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT
	.comm	_VCN,4,2                        ; @VCN
	.comm	_mmUVD_MPC_SET_MUXA0,4,2        ; @mmUVD_MPC_SET_MUXA0
	.comm	_UVD_MPC_SET_MUXA0__VARA_1__SHIFT,4,2 ; @UVD_MPC_SET_MUXA0__VARA_1__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_2__SHIFT,4,2 ; @UVD_MPC_SET_MUXA0__VARA_2__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_3__SHIFT,4,2 ; @UVD_MPC_SET_MUXA0__VARA_3__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_4__SHIFT,4,2 ; @UVD_MPC_SET_MUXA0__VARA_4__SHIFT
	.comm	_mmUVD_MPC_SET_MUXB0,4,2        ; @mmUVD_MPC_SET_MUXB0
	.comm	_UVD_MPC_SET_MUXB0__VARB_1__SHIFT,4,2 ; @UVD_MPC_SET_MUXB0__VARB_1__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_2__SHIFT,4,2 ; @UVD_MPC_SET_MUXB0__VARB_2__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_3__SHIFT,4,2 ; @UVD_MPC_SET_MUXB0__VARB_3__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_4__SHIFT,4,2 ; @UVD_MPC_SET_MUXB0__VARB_4__SHIFT
	.comm	_mmUVD_MPC_SET_MUX,4,2          ; @mmUVD_MPC_SET_MUX
	.comm	_UVD_MPC_SET_MUX__SET_0__SHIFT,4,2 ; @UVD_MPC_SET_MUX__SET_0__SHIFT
	.comm	_UVD_MPC_SET_MUX__SET_1__SHIFT,4,2 ; @UVD_MPC_SET_MUX__SET_1__SHIFT
	.comm	_UVD_MPC_SET_MUX__SET_2__SHIFT,4,2 ; @UVD_MPC_SET_MUX__SET_2__SHIFT
	.comm	_mmUVD_GFX8_ADDR_CONFIG,4,2     ; @mmUVD_GFX8_ADDR_CONFIG
	.comm	_mmUVD_LMI_CTRL2,4,2            ; @mmUVD_LMI_CTRL2
	.comm	_UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,4,2 ; @UVD_LMI_CTRL2__STALL_ARB_UMC_MASK
	.comm	_mmUVD_RB_ARB_CTRL,4,2          ; @mmUVD_RB_ARB_CTRL
	.comm	_UVD_RB_ARB_CTRL__VCPU_DIS_MASK,4,2 ; @UVD_RB_ARB_CTRL__VCPU_DIS_MASK
	.comm	_UVD_VCPU_CNTL__BLK_RST_MASK,4,2 ; @UVD_VCPU_CNTL__BLK_RST_MASK
	.comm	_amdgpu_emu_mode,4,2            ; @amdgpu_emu_mode
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"VCN decode not responding, trying to reset the VCPU!!!\n"

l_.str.1:                               ; @.str.1
	.asciz	"VCN decode not responding, giving up!!!\n"

	.comm	_UVD_STATUS__VCPU_REPORT__SHIFT,4,2 ; @UVD_STATUS__VCPU_REPORT__SHIFT
	.comm	_mmUVD_LMI_RBC_RB_VMID,4,2      ; @mmUVD_LMI_RBC_RB_VMID
	.comm	_UVD_RBC_RB_CNTL,4,2            ; @UVD_RBC_RB_CNTL
	.comm	_RB_BUFSZ,4,2                   ; @RB_BUFSZ
	.comm	_RB_BLKSZ,4,2                   ; @RB_BLKSZ
	.comm	_RB_NO_FETCH,4,2                ; @RB_NO_FETCH
	.comm	_RB_NO_UPDATE,4,2               ; @RB_NO_UPDATE
	.comm	_RB_RPTR_WR_EN,4,2              ; @RB_RPTR_WR_EN
	.comm	_mmUVD_RBC_RB_CNTL,4,2          ; @mmUVD_RBC_RB_CNTL
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
	.comm	_mmUVD_RBC_RB_RPTR,4,2          ; @mmUVD_RBC_RB_RPTR
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ; @mmUVD_RBC_RB_WPTR
	.comm	_mmUVD_RB_RPTR,4,2              ; @mmUVD_RB_RPTR
	.comm	_mmUVD_RB_WPTR,4,2              ; @mmUVD_RB_WPTR
	.comm	_mmUVD_RB_BASE_LO,4,2           ; @mmUVD_RB_BASE_LO
	.comm	_mmUVD_RB_BASE_HI,4,2           ; @mmUVD_RB_BASE_HI
	.comm	_mmUVD_RB_SIZE,4,2              ; @mmUVD_RB_SIZE
	.comm	_mmUVD_RB_RPTR2,4,2             ; @mmUVD_RB_RPTR2
	.comm	_mmUVD_RB_WPTR2,4,2             ; @mmUVD_RB_WPTR2
	.comm	_mmUVD_RB_BASE_LO2,4,2          ; @mmUVD_RB_BASE_LO2
	.comm	_mmUVD_RB_BASE_HI2,4,2          ; @mmUVD_RB_BASE_HI2
	.comm	_mmUVD_RB_SIZE2,4,2             ; @mmUVD_RB_SIZE2
	.no_dead_strip	_vcn_v2_5_start
.subsections_via_symbols
