	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v10_0_update_3d_clock_gating
_gfx_v10_0_update_3d_clock_gating:      ## @gfx_v10_0_update_3d_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	testl	%esi, %esi
	je	LBB0_9
## %bb.1:
	movq	%rdi, %r14
	movq	_AMD_CG_SUPPORT_GFX_3D_CGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rdi)
	je	LBB0_9
## %bb.2:
	movq	_GC@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	movq	_mmRLC_CGTT_MGCG_OVERRIDE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	cmpl	%ecx, %eax
	je	LBB0_4
## %bb.3:
	movl	(%r15), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
LBB0_4:
	movl	(%r15), %edi
	movq	_mmRLC_CGCG_CGLS_CTRL_3D@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$54, %ebx
	shll	%cl, %ebx
	movq	_RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_AMD_CG_SUPPORT_GFX_3D_CGLS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, (%r14)
	je	LBB0_6
## %bb.5:
	movq	_RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$15, %edx
	shll	%cl, %edx
	movq	_RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	orl	%edx, %ebx
LBB0_6:
	cmpl	%ebx, %eax
	je	LBB0_8
## %bb.7:
	movl	(%r15), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	movl	%ebx, %ecx
	callq	_WREG32_SOC15
LBB0_8:
	movl	(%r15), %edi
	movq	_mmCP_RB_WPTR_POLL_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$256, %edx                      ## imm = 0x100
	shll	%cl, %edx
	movq	_CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$144, %ebx
	shll	%cl, %ebx
	orl	%edx, %ebx
	cmpl	%ebx, %eax
	je	LBB0_11
LBB0_12:
	movq	_GC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r14), %edx
	xorl	%esi, %esi
	movl	%ebx, %ecx
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_SOC15                   ## TAILCALL
LBB0_9:
	movq	_GC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmRLC_CGCG_CGLS_CTRL_3D@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK@GOTPCREL(%rip), %rcx
	movq	_RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	cmpl	%ebx, %eax
	jne	LBB0_12
LBB0_11:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_CG_SUPPORT_GFX_3D_CGCG,4,2 ## @AMD_CG_SUPPORT_GFX_3D_CGCG
	.comm	_GC,4,2                         ## @GC
	.comm	_mmRLC_CGTT_MGCG_OVERRIDE,4,2   ## @mmRLC_CGTT_MGCG_OVERRIDE
	.comm	_RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK,4,2 ## @RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK
	.comm	_mmRLC_CGCG_CGLS_CTRL_3D,4,2    ## @mmRLC_CGCG_CGLS_CTRL_3D
	.comm	_RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT,4,2 ## @RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT
	.comm	_RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK,4,2 ## @RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK
	.comm	_AMD_CG_SUPPORT_GFX_3D_CGLS,4,2 ## @AMD_CG_SUPPORT_GFX_3D_CGLS
	.comm	_RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT,4,2 ## @RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT
	.comm	_RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK,4,2 ## @RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK
	.comm	_mmCP_RB_WPTR_POLL_CNTL,4,2     ## @mmCP_RB_WPTR_POLL_CNTL
	.comm	_CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT,4,2 ## @CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT
	.comm	_CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT,4,2 ## @CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT
	.no_dead_strip	_gfx_v10_0_update_3d_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v10_0_update_3d_clock_gating
_gfx_v10_0_update_3d_clock_gating:      ; @gfx_v10_0_update_3d_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	cbz	w1, LBB0_10
; %bb.1:
	mov	x19, x0
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _AMD_CG_SUPPORT_GFX_3D_CGCG@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_CG_SUPPORT_GFX_3D_CGCG@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_10
; %bb.2:
Lloh3:
	adrp	x20, _GC@GOTPAGE
Lloh4:
	ldr	x20, [x20, _GC@GOTPAGEOFF]
	ldr	w0, [x20]
Lloh5:
	adrp	x21, _mmRLC_CGTT_MGCG_OVERRIDE@GOTPAGE
Lloh6:
	ldr	x21, [x21, _mmRLC_CGTT_MGCG_OVERRIDE@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh7:
	adrp	x8, _RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK@GOTPAGE
Lloh8:
	ldr	x8, [x8, _RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	bic	w3, w0, w8
	cmp	w0, w3
	b.eq	LBB0_4
; %bb.3:
	ldr	w0, [x20]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_WREG32_SOC15
LBB0_4:
	ldr	w0, [x20]
Lloh10:
	adrp	x21, _mmRLC_CGCG_CGLS_CTRL_3D@GOTPAGE
Lloh11:
	ldr	x21, [x21, _mmRLC_CGCG_CGLS_CTRL_3D@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh12:
	adrp	x8, _RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	mov	w9, #54
	lsl	w8, w9, w8
Lloh15:
	adrp	x9, _RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK@GOTPAGE
Lloh16:
	ldr	x9, [x9, _RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	orr	w3, w8, w9
	ldr	w8, [x19]
Lloh18:
	adrp	x9, _AMD_CG_SUPPORT_GFX_3D_CGLS@GOTPAGE
Lloh19:
	ldr	x9, [x9, _AMD_CG_SUPPORT_GFX_3D_CGLS@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_6
; %bb.5:
Lloh21:
	adrp	x8, _RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT@GOTPAGE
Lloh22:
	ldr	x8, [x8, _RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	mov	w9, #15
	lsl	w8, w9, w8
Lloh24:
	adrp	x9, _RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK@GOTPAGE
Lloh25:
	ldr	x9, [x9, _RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	orr	w9, w9, w3
	orr	w3, w9, w8
LBB0_6:
	cmp	w0, w3
	b.eq	LBB0_8
; %bb.7:
	ldr	w0, [x20]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_WREG32_SOC15
LBB0_8:
	ldr	w0, [x20]
Lloh27:
	adrp	x19, _mmCP_RB_WPTR_POLL_CNTL@GOTPAGE
Lloh28:
	ldr	x19, [x19, _mmCP_RB_WPTR_POLL_CNTL@GOTPAGEOFF]
	ldr	w2, [x19]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh29:
	adrp	x8, _CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT@GOTPAGE
Lloh30:
	ldr	x8, [x8, _CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT@GOTPAGEOFF]
Lloh31:
	ldr	w8, [x8]
	mov	w9, #256
Lloh32:
	adrp	x10, _CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT@GOTPAGE
Lloh33:
	ldr	x10, [x10, _CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT@GOTPAGEOFF]
	lsl	w8, w9, w8
Lloh34:
	ldr	w9, [x10]
	mov	w10, #144
	lsl	w9, w10, w9
	orr	w3, w9, w8
	cmp	w0, w3
	b.eq	LBB0_11
LBB0_9:
Lloh35:
	adrp	x8, _GC@GOTPAGE
Lloh36:
	ldr	x8, [x8, _GC@GOTPAGEOFF]
Lloh37:
	ldr	w0, [x8]
	ldr	w2, [x19]
	mov	w1, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32_SOC15
LBB0_10:
Lloh38:
	adrp	x8, _GC@GOTPAGE
Lloh39:
	ldr	x8, [x8, _GC@GOTPAGEOFF]
Lloh40:
	ldr	w0, [x8]
Lloh41:
	adrp	x19, _mmRLC_CGCG_CGLS_CTRL_3D@GOTPAGE
Lloh42:
	ldr	x19, [x19, _mmRLC_CGCG_CGLS_CTRL_3D@GOTPAGEOFF]
	ldr	w2, [x19]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh43:
	adrp	x8, _RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK@GOTPAGE
Lloh44:
	ldr	x8, [x8, _RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK@GOTPAGEOFF]
Lloh45:
	ldr	w8, [x8]
Lloh46:
	adrp	x9, _RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK@GOTPAGE
Lloh47:
	ldr	x9, [x9, _RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK@GOTPAGEOFF]
Lloh48:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w3, w0, w8
	cmp	w0, w3
	b.ne	LBB0_9
LBB0_11:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_CG_SUPPORT_GFX_3D_CGCG,4,2 ; @AMD_CG_SUPPORT_GFX_3D_CGCG
	.comm	_GC,4,2                         ; @GC
	.comm	_mmRLC_CGTT_MGCG_OVERRIDE,4,2   ; @mmRLC_CGTT_MGCG_OVERRIDE
	.comm	_RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK,4,2 ; @RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK
	.comm	_mmRLC_CGCG_CGLS_CTRL_3D,4,2    ; @mmRLC_CGCG_CGLS_CTRL_3D
	.comm	_RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT,4,2 ; @RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT
	.comm	_RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK,4,2 ; @RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK
	.comm	_AMD_CG_SUPPORT_GFX_3D_CGLS,4,2 ; @AMD_CG_SUPPORT_GFX_3D_CGLS
	.comm	_RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT,4,2 ; @RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT
	.comm	_RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK,4,2 ; @RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK
	.comm	_mmCP_RB_WPTR_POLL_CNTL,4,2     ; @mmCP_RB_WPTR_POLL_CNTL
	.comm	_CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT,4,2 ; @CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT
	.comm	_CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT,4,2 ; @CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT
	.no_dead_strip	_gfx_v10_0_update_3d_clock_gating
.subsections_via_symbols
