	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vega20_power_gate_vce
_vega20_power_gate_vce:                 ## @vega20_power_gate_vce
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	8(%rdi), %rax
	cmpl	%esi, (%rax)
	jne	LBB0_1
## %bb.3:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
LBB0_1:
	movq	%rdi, %rbx
	movl	%esi, (%rax)
	testl	%esi, %esi
	je	LBB0_2
## %bb.4:
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_vega20_enable_disable_vce_dpm
	movl	(%rbx), %edi
	movq	_AMD_IP_BLOCK_TYPE_VCE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AMD_PG_STATE_GATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_amdgpu_device_ip_set_powergating_state ## TAILCALL
LBB0_2:
	movl	(%rbx), %edi
	movq	_AMD_IP_BLOCK_TYPE_VCE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AMD_PG_STATE_UNGATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_amdgpu_device_ip_set_powergating_state
	movq	%rbx, %rdi
	movl	$1, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_vega20_enable_disable_vce_dpm  ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_IP_BLOCK_TYPE_VCE,4,2      ## @AMD_IP_BLOCK_TYPE_VCE
	.comm	_AMD_PG_STATE_GATE,4,2          ## @AMD_PG_STATE_GATE
	.comm	_AMD_PG_STATE_UNGATE,4,2        ## @AMD_PG_STATE_UNGATE
	.no_dead_strip	_vega20_power_gate_vce
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vega20_power_gate_vce
_vega20_power_gate_vce:                 ; @vega20_power_gate_vce
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	x8, [x0, #8]
	ldr	w9, [x8]
	cmp	w9, w1
	b.ne	LBB0_2
; %bb.1:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_2:
	mov	x19, x0
	str	w1, [x8]
	cbz	w1, LBB0_4
; %bb.3:
	mov	x0, x19
	mov	w1, #0
	bl	_vega20_enable_disable_vce_dpm
	ldr	w0, [x19]
Lloh0:
	adrp	x8, _AMD_IP_BLOCK_TYPE_VCE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMD_IP_BLOCK_TYPE_VCE@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
Lloh3:
	adrp	x8, _AMD_PG_STATE_GATE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _AMD_PG_STATE_GATE@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_amdgpu_device_ip_set_powergating_state
LBB0_4:
	ldr	w0, [x19]
Lloh6:
	adrp	x8, _AMD_IP_BLOCK_TYPE_VCE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _AMD_IP_BLOCK_TYPE_VCE@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
Lloh9:
	adrp	x8, _AMD_PG_STATE_UNGATE@GOTPAGE
Lloh10:
	ldr	x8, [x8, _AMD_PG_STATE_UNGATE@GOTPAGEOFF]
Lloh11:
	ldr	w2, [x8]
	bl	_amdgpu_device_ip_set_powergating_state
	mov	x0, x19
	mov	w1, #1
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_vega20_enable_disable_vce_dpm
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_IP_BLOCK_TYPE_VCE,4,2      ; @AMD_IP_BLOCK_TYPE_VCE
	.comm	_AMD_PG_STATE_GATE,4,2          ; @AMD_PG_STATE_GATE
	.comm	_AMD_PG_STATE_UNGATE,4,2        ; @AMD_PG_STATE_UNGATE
	.no_dead_strip	_vega20_power_gate_vce
.subsections_via_symbols
