	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_pll_write_update
_radeon_pll_write_update:               ## @radeon_pll_write_update
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	_RADEON_PPLL_REF_DIV@GOTPCREL(%rip), %r14
	movq	_RADEON_PPLL_ATOMIC_UPDATE_R@GOTPCREL(%rip), %rbx
	.p2align	4, 0x90
LBB0_1:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %edi
	callq	_RREG32_PLL
	testl	%eax, (%rbx)
	jne	LBB0_1
## %bb.2:
	movl	(%r14), %edi
	movq	_RADEON_PPLL_ATOMIC_UPDATE_W@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%esi, %edx
	notl	%edx
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_WREG32_PLL_P                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_PPLL_REF_DIV,4,2        ## @RADEON_PPLL_REF_DIV
	.comm	_RADEON_PPLL_ATOMIC_UPDATE_R,4,2 ## @RADEON_PPLL_ATOMIC_UPDATE_R
	.comm	_RADEON_PPLL_ATOMIC_UPDATE_W,4,2 ## @RADEON_PPLL_ATOMIC_UPDATE_W
	.no_dead_strip	_radeon_pll_write_update
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_pll_write_update
_radeon_pll_write_update:               ; @radeon_pll_write_update
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
Lloh0:
	adrp	x19, _RADEON_PPLL_REF_DIV@GOTPAGE
Lloh1:
	ldr	x19, [x19, _RADEON_PPLL_REF_DIV@GOTPAGEOFF]
Lloh2:
	adrp	x20, _RADEON_PPLL_ATOMIC_UPDATE_R@GOTPAGE
Lloh3:
	ldr	x20, [x20, _RADEON_PPLL_ATOMIC_UPDATE_R@GOTPAGEOFF]
LBB0_1:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x19]
	bl	_RREG32_PLL
	ldr	w8, [x20]
	tst	w8, w0
	b.ne	LBB0_1
; %bb.2:
Lloh4:
	adrp	x8, _RADEON_PPLL_ATOMIC_UPDATE_W@GOTPAGE
Lloh5:
	ldr	x8, [x8, _RADEON_PPLL_ATOMIC_UPDATE_W@GOTPAGEOFF]
	ldr	w0, [x19]
Lloh6:
	ldr	w1, [x8]
	mvn	w2, w1
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_WREG32_PLL_P
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_PPLL_REF_DIV,4,2        ; @RADEON_PPLL_REF_DIV
	.comm	_RADEON_PPLL_ATOMIC_UPDATE_R,4,2 ; @RADEON_PPLL_ATOMIC_UPDATE_R
	.comm	_RADEON_PPLL_ATOMIC_UPDATE_W,4,2 ; @RADEON_PPLL_ATOMIC_UPDATE_W
	.no_dead_strip	_radeon_pll_write_update
.subsections_via_symbols
