	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function uvd_v7_0_mc_resume
_uvd_v7_0_mc_resume:                    ## @uvd_v7_0_mc_resume
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	callq	_AMDGPU_UVD_FIRMWARE_SIZE
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movl	(%r15), %eax
	testl	%eax, %eax
	jle	LBB0_10
## %bb.1:
	xorl	%ebx, %ebx
	movq	_UVD@GOTPCREL(%rip), %r14
	jmp	LBB0_2
LBB0_7:                                 ##   in Loop: Header=BB0_2 Depth=1
	movq	16(%r15), %rax
	movl	(%rax,%rbx,4), %edi
	callq	_lower_32_bits
	movl	%r13d, %edi
	movl	%ebx, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %r12d
	movq	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	16(%r15), %rax
	movl	(%rax,%rbx,4), %edi
	callq	_upper_32_bits
	movl	%r12d, %edi
	movl	%ebx, %esi
	movl	%r13d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_VCPU_CACHE_OFFSET0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_AMDGPU_UVD_FIRMWARE_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	sarl	$3, %ecx
	movl	%ebx, %esi
	callq	_WREG32_SOC15
	movl	-44(%rbp), %ecx                 ## 4-byte Reload
	movl	%ecx, %r12d
LBB0_8:                                 ##   in Loop: Header=BB0_2 Depth=1
	movl	(%r14), %edi
	movq	_mmUVD_VCPU_CACHE_SIZE0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%ebx, %esi
	callq	_WREG32_SOC15
	movl	(%r14), %r13d
	movq	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	16(%r15), %rax
	movl	(%rax,%rbx,4), %edi
	addl	%r12d, %edi
	callq	_lower_32_bits
	movl	%r13d, %edi
	movl	%ebx, %esi
	movl	%r14d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	16(%r15), %rax
	movl	(%rax,%rbx,4), %edi
	addl	%r12d, %edi
	callq	_upper_32_bits
	movl	%r14d, %edi
	movl	%ebx, %esi
	movl	%r13d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmUVD_VCPU_CACHE_OFFSET1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%ebx, %esi
	movl	$2097152, %ecx                  ## imm = 0x200000
	callq	_WREG32_SOC15
	movq	_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmUVD_VCPU_CACHE_SIZE1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_AMDGPU_UVD_HEAP_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ebx, %esi
	callq	_WREG32_SOC15
	movq	_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	16(%r15), %rax
	movl	(%rax,%rbx,4), %edi
	addl	%r12d, %edi
	movq	_AMDGPU_UVD_HEAP_SIZE@GOTPCREL(%rip), %rax
	addl	(%rax), %edi
	callq	_lower_32_bits
	movl	%r14d, %edi
	movl	%ebx, %esi
	movl	%r13d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	16(%r15), %rax
	addl	(%rax,%rbx,4), %r12d
	movq	_AMDGPU_UVD_HEAP_SIZE@GOTPCREL(%rip), %rax
	addl	(%rax), %r12d
	movl	%r12d, %edi
	callq	_upper_32_bits
	movl	%r14d, %edi
	movq	_UVD@GOTPCREL(%rip), %r14
	movl	%ebx, %esi
	movl	%r13d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_VCPU_CACHE_OFFSET2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%ebx, %esi
	movl	$4194304, %ecx                  ## imm = 0x400000
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_VCPU_CACHE_SIZE2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_AMDGPU_UVD_SESSION_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	leal	(%rax,%rax,4), %ecx
	shll	$3, %ecx
	movq	_AMDGPU_UVD_STACK_SIZE@GOTPCREL(%rip), %rax
	addl	(%rax), %ecx
	movl	%ebx, %esi
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_UDEC_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	24(%r15), %ecx
	movl	%ebx, %esi
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_UDEC_DB_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	24(%r15), %ecx
	movl	%ebx, %esi
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_UDEC_DBW_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	24(%r15), %ecx
	movl	%ebx, %esi
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_GP_SCRATCH4@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	8(%r15), %ecx
	movl	%ebx, %esi
	callq	_WREG32_SOC15
	movl	(%r15), %eax
LBB0_9:                                 ##   in Loop: Header=BB0_2 Depth=1
	incq	%rbx
	movslq	%eax, %rcx
	cmpq	%rcx, %rbx
	jge	LBB0_10
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movl	4(%r15), %ecx
	btl	%ebx, %ecx
	jb	LBB0_9
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	32(%r15), %rax
	movl	(%r14), %r13d
	movq	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r12d
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_7
## %bb.4:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	_AMDGPU_UCODE_ID_UVD1@GOTPCREL(%rip), %r14
	testq	%rbx, %rbx
	jne	LBB0_6
## %bb.5:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	_AMDGPU_UCODE_ID_UVD@GOTPCREL(%rip), %r14
LBB0_6:                                 ##   in Loop: Header=BB0_2 Depth=1
	movq	40(%r15), %rax
	movq	(%r14), %rcx
	movl	(%rax,%rcx,8), %ecx
	movl	%r13d, %edi
	movl	%ebx, %esi
	movl	%r12d, %edx
	callq	_WREG32_SOC15
	movq	_UVD@GOTPCREL(%rip), %rsi
	movl	(%rsi), %edi
	movq	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	40(%r15), %rax
	movq	(%r14), %rcx
	movq	%rsi, %r14
	movl	4(%rax,%rcx,8), %ecx
	movl	%ebx, %esi
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_VCPU_CACHE_OFFSET0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%r12d, %r12d
	movl	%ebx, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	-44(%rbp), %ecx                 ## 4-byte Reload
	jmp	LBB0_8
LBB0_10:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
	.comm	_AMDGPU_UCODE_ID_UVD,8,3        ## @AMDGPU_UCODE_ID_UVD
	.comm	_AMDGPU_UCODE_ID_UVD1,8,3       ## @AMDGPU_UCODE_ID_UVD1
	.comm	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET0,4,2   ## @mmUVD_VCPU_CACHE_OFFSET0
	.comm	_AMDGPU_UVD_FIRMWARE_OFFSET,4,2 ## @AMDGPU_UVD_FIRMWARE_OFFSET
	.comm	_mmUVD_VCPU_CACHE_SIZE0,4,2     ## @mmUVD_VCPU_CACHE_SIZE0
	.comm	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET1,4,2   ## @mmUVD_VCPU_CACHE_OFFSET1
	.comm	_mmUVD_VCPU_CACHE_SIZE1,4,2     ## @mmUVD_VCPU_CACHE_SIZE1
	.comm	_AMDGPU_UVD_HEAP_SIZE,4,2       ## @AMDGPU_UVD_HEAP_SIZE
	.comm	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET2,4,2   ## @mmUVD_VCPU_CACHE_OFFSET2
	.comm	_mmUVD_VCPU_CACHE_SIZE2,4,2     ## @mmUVD_VCPU_CACHE_SIZE2
	.comm	_AMDGPU_UVD_STACK_SIZE,4,2      ## @AMDGPU_UVD_STACK_SIZE
	.comm	_AMDGPU_UVD_SESSION_SIZE,4,2    ## @AMDGPU_UVD_SESSION_SIZE
	.comm	_mmUVD_UDEC_ADDR_CONFIG,4,2     ## @mmUVD_UDEC_ADDR_CONFIG
	.comm	_mmUVD_UDEC_DB_ADDR_CONFIG,4,2  ## @mmUVD_UDEC_DB_ADDR_CONFIG
	.comm	_mmUVD_UDEC_DBW_ADDR_CONFIG,4,2 ## @mmUVD_UDEC_DBW_ADDR_CONFIG
	.comm	_mmUVD_GP_SCRATCH4,4,2          ## @mmUVD_GP_SCRATCH4
	.no_dead_strip	_uvd_v7_0_mc_resume
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function uvd_v7_0_mc_resume
_uvd_v7_0_mc_resume:                    ; @uvd_v7_0_mc_resume
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	bl	_AMDGPU_UVD_FIRMWARE_SIZE
	ldr	w8, [x19]
	cmp	w8, #1
	b.lt	LBB0_8
; %bb.1:
	mov	x26, x0
	mov	x21, #0
Lloh0:
	adrp	x25, _UVD@GOTPAGE
Lloh1:
	ldr	x25, [x25, _UVD@GOTPAGEOFF]
Lloh2:
	adrp	x27, _AMDGPU_UVD_HEAP_SIZE@GOTPAGE
Lloh3:
	ldr	x27, [x27, _AMDGPU_UVD_HEAP_SIZE@GOTPAGEOFF]
Lloh4:
	adrp	x28, _mmUVD_GP_SCRATCH4@GOTPAGE
Lloh5:
	ldr	x28, [x28, _mmUVD_GP_SCRATCH4@GOTPAGEOFF]
	b	LBB0_5
LBB0_2:                                 ;   in Loop: Header=BB0_5 Depth=1
	ldr	x8, [x19, #16]
	ldr	w0, [x8, x24]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x23
	mov	x1, x21
	mov	x2, x22
	bl	_WREG32_SOC15
	ldr	w22, [x25]
Lloh6:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPAGE
Lloh7:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh8:
	ldr	w23, [x8]
	ldr	x8, [x19, #16]
	ldr	w0, [x8, x24]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x21
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w0, [x25]
Lloh9:
	adrp	x8, _mmUVD_VCPU_CACHE_OFFSET0@GOTPAGE
Lloh10:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_OFFSET0@GOTPAGEOFF]
Lloh11:
	ldr	w2, [x8]
Lloh12:
	adrp	x8, _AMDGPU_UVD_FIRMWARE_OFFSET@GOTPAGE
Lloh13:
	ldr	x8, [x8, _AMDGPU_UVD_FIRMWARE_OFFSET@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	asr	w3, w8, #3
	mov	x1, x21
	bl	_WREG32_SOC15
	mov	x20, x26
LBB0_3:                                 ;   in Loop: Header=BB0_5 Depth=1
	ldr	w0, [x25]
Lloh15:
	adrp	x8, _mmUVD_VCPU_CACHE_SIZE0@GOTPAGE
Lloh16:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_SIZE0@GOTPAGEOFF]
Lloh17:
	ldr	w2, [x8]
	mov	x1, x21
	mov	x3, x26
	bl	_WREG32_SOC15
	ldr	w22, [x25]
Lloh18:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW@GOTPAGE
Lloh19:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh20:
	ldr	w23, [x8]
	ldr	x8, [x19, #16]
	ldr	w8, [x8, x24]
	add	w0, w8, w20
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x21
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w22, [x25]
Lloh21:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH@GOTPAGE
Lloh22:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh23:
	ldr	w23, [x8]
	ldr	x8, [x19, #16]
	ldr	w8, [x8, x24]
	add	w0, w8, w20
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x21
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w0, [x25]
Lloh24:
	adrp	x8, _mmUVD_VCPU_CACHE_OFFSET1@GOTPAGE
Lloh25:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_OFFSET1@GOTPAGEOFF]
Lloh26:
	ldr	w2, [x8]
	mov	x1, x21
	mov	w3, #2097152
	bl	_WREG32_SOC15
	ldr	w0, [x25]
Lloh27:
	adrp	x8, _mmUVD_VCPU_CACHE_SIZE1@GOTPAGE
Lloh28:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_SIZE1@GOTPAGEOFF]
Lloh29:
	ldr	w2, [x8]
	ldr	w3, [x27]
	mov	x1, x21
	bl	_WREG32_SOC15
	ldr	w22, [x25]
Lloh30:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW@GOTPAGE
Lloh31:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh32:
	ldr	w23, [x8]
	ldr	x8, [x19, #16]
	ldr	w8, [x8, x24]
	ldr	w9, [x27]
	add	w8, w8, w20
	add	w0, w8, w9
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x21
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w22, [x25]
Lloh33:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH@GOTPAGE
Lloh34:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh35:
	ldr	w23, [x8]
	ldr	x8, [x19, #16]
	ldr	w8, [x8, x24]
	ldr	w9, [x27]
	add	w8, w8, w20
	add	w0, w8, w9
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x21
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w0, [x25]
Lloh36:
	adrp	x8, _mmUVD_VCPU_CACHE_OFFSET2@GOTPAGE
Lloh37:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_OFFSET2@GOTPAGEOFF]
Lloh38:
	ldr	w2, [x8]
	mov	x1, x21
	mov	w3, #4194304
	bl	_WREG32_SOC15
	ldr	w0, [x25]
Lloh39:
	adrp	x8, _mmUVD_VCPU_CACHE_SIZE2@GOTPAGE
Lloh40:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_SIZE2@GOTPAGEOFF]
Lloh41:
	ldr	w2, [x8]
Lloh42:
	adrp	x8, _AMDGPU_UVD_STACK_SIZE@GOTPAGE
Lloh43:
	ldr	x8, [x8, _AMDGPU_UVD_STACK_SIZE@GOTPAGEOFF]
Lloh44:
	ldr	w8, [x8]
Lloh45:
	adrp	x9, _AMDGPU_UVD_SESSION_SIZE@GOTPAGE
Lloh46:
	ldr	x9, [x9, _AMDGPU_UVD_SESSION_SIZE@GOTPAGEOFF]
Lloh47:
	ldr	w9, [x9]
	mov	w10, #40
	madd	w3, w9, w10, w8
	mov	x1, x21
	bl	_WREG32_SOC15
	ldr	w0, [x25]
Lloh48:
	adrp	x8, _mmUVD_UDEC_ADDR_CONFIG@GOTPAGE
Lloh49:
	ldr	x8, [x8, _mmUVD_UDEC_ADDR_CONFIG@GOTPAGEOFF]
Lloh50:
	ldr	w2, [x8]
	ldr	w3, [x19, #24]
	mov	x1, x21
	bl	_WREG32_SOC15
	ldr	w0, [x25]
Lloh51:
	adrp	x8, _mmUVD_UDEC_DB_ADDR_CONFIG@GOTPAGE
Lloh52:
	ldr	x8, [x8, _mmUVD_UDEC_DB_ADDR_CONFIG@GOTPAGEOFF]
Lloh53:
	ldr	w2, [x8]
	ldr	w3, [x19, #24]
	mov	x1, x21
	bl	_WREG32_SOC15
	ldr	w0, [x25]
Lloh54:
	adrp	x8, _mmUVD_UDEC_DBW_ADDR_CONFIG@GOTPAGE
Lloh55:
	ldr	x8, [x8, _mmUVD_UDEC_DBW_ADDR_CONFIG@GOTPAGEOFF]
Lloh56:
	ldr	w2, [x8]
	ldr	w3, [x19, #24]
	mov	x1, x21
	bl	_WREG32_SOC15
	ldr	w0, [x25]
	ldr	w2, [x28]
	ldr	w3, [x19, #8]
	mov	x1, x21
	bl	_WREG32_SOC15
	ldr	w8, [x19]
LBB0_4:                                 ;   in Loop: Header=BB0_5 Depth=1
	add	x21, x21, #1
	cmp	x21, w8, sxtw
	b.ge	LBB0_8
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w9, [x19, #4]
	lsr	w9, w9, w21
	tbnz	w9, #0, LBB0_4
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	ldr	x8, [x19, #32]
Lloh57:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh58:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh59:
	ldr	x9, [x9]
	ldr	w23, [x25]
Lloh60:
	adrp	x10, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW@GOTPAGE
Lloh61:
	ldr	x10, [x10, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh62:
	ldr	w22, [x10]
	lsl	x24, x21, #2
	cmp	x8, x9
	b.ne	LBB0_2
; %bb.7:                                ;   in Loop: Header=BB0_5 Depth=1
	ldr	x8, [x19, #40]
	cmp	x21, #0
Lloh63:
	adrp	x9, _AMDGPU_UCODE_ID_UVD@GOTPAGE
Lloh64:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_UVD@GOTPAGEOFF]
Lloh65:
	adrp	x10, _AMDGPU_UCODE_ID_UVD1@GOTPAGE
Lloh66:
	ldr	x10, [x10, _AMDGPU_UCODE_ID_UVD1@GOTPAGEOFF]
	csel	x20, x9, x10, eq
	ldr	x9, [x20]
	lsl	x9, x9, #3
	ldr	w3, [x8, x9]
	mov	x0, x23
	mov	x1, x21
	mov	x2, x22
	bl	_WREG32_SOC15
	ldr	w0, [x25]
Lloh67:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPAGE
Lloh68:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh69:
	ldr	w2, [x8]
	ldr	x8, [x19, #40]
	ldr	x9, [x20]
	add	x8, x8, x9, lsl #3
	ldr	w3, [x8, #4]
	mov	x1, x21
	bl	_WREG32_SOC15
	ldr	w0, [x25]
Lloh70:
	adrp	x8, _mmUVD_VCPU_CACHE_OFFSET0@GOTPAGE
Lloh71:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_OFFSET0@GOTPAGEOFF]
Lloh72:
	ldr	w2, [x8]
	mov	x1, x21
	mov	w3, #0
	bl	_WREG32_SOC15
	mov	w20, #0
	b	LBB0_3
LBB0_8:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGot	Lloh63, Lloh64
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
	.comm	_AMDGPU_UCODE_ID_UVD,8,3        ; @AMDGPU_UCODE_ID_UVD
	.comm	_AMDGPU_UCODE_ID_UVD1,8,3       ; @AMDGPU_UCODE_ID_UVD1
	.comm	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET0,4,2   ; @mmUVD_VCPU_CACHE_OFFSET0
	.comm	_AMDGPU_UVD_FIRMWARE_OFFSET,4,2 ; @AMDGPU_UVD_FIRMWARE_OFFSET
	.comm	_mmUVD_VCPU_CACHE_SIZE0,4,2     ; @mmUVD_VCPU_CACHE_SIZE0
	.comm	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET1,4,2   ; @mmUVD_VCPU_CACHE_OFFSET1
	.comm	_mmUVD_VCPU_CACHE_SIZE1,4,2     ; @mmUVD_VCPU_CACHE_SIZE1
	.comm	_AMDGPU_UVD_HEAP_SIZE,4,2       ; @AMDGPU_UVD_HEAP_SIZE
	.comm	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET2,4,2   ; @mmUVD_VCPU_CACHE_OFFSET2
	.comm	_mmUVD_VCPU_CACHE_SIZE2,4,2     ; @mmUVD_VCPU_CACHE_SIZE2
	.comm	_AMDGPU_UVD_STACK_SIZE,4,2      ; @AMDGPU_UVD_STACK_SIZE
	.comm	_AMDGPU_UVD_SESSION_SIZE,4,2    ; @AMDGPU_UVD_SESSION_SIZE
	.comm	_mmUVD_UDEC_ADDR_CONFIG,4,2     ; @mmUVD_UDEC_ADDR_CONFIG
	.comm	_mmUVD_UDEC_DB_ADDR_CONFIG,4,2  ; @mmUVD_UDEC_DB_ADDR_CONFIG
	.comm	_mmUVD_UDEC_DBW_ADDR_CONFIG,4,2 ; @mmUVD_UDEC_DBW_ADDR_CONFIG
	.comm	_mmUVD_GP_SCRATCH4,4,2          ; @mmUVD_GP_SCRATCH4
	.no_dead_strip	_uvd_v7_0_mc_resume
.subsections_via_symbols
