	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vega10_ih_disable_interrupts
_vega10_ih_disable_interrupts:          ## @vega10_ih_disable_interrupts
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_OSSSYS@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	movq	_mmIH_RB_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_IH_RB_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_RB_ENABLE@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movq	%rax, %rdi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_ENABLE_INTR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%rax, %rdi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movq	%rax, %rbx
	movq	%r14, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_4
## %bb.1:
	leaq	64(%r14), %rdi
	movq	_PSP_REG_IH_RB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdx
	callq	_psp_reg_program
	testq	%rax, %rax
	je	LBB0_5
## %bb.2:
	leaq	L_.str(%rip), %rdi
	jmp	LBB0_3
LBB0_4:
	movl	(%r15), %edi
	movl	(%r13), %edx
	xorl	%esi, %esi
	movq	%rbx, %rcx
	callq	_WREG32_SOC15
LBB0_5:
	movl	(%r15), %edi
	movq	_mmIH_RB_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r15), %edi
	movq	_mmIH_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	$0, 48(%r14)
	movq	$0, 56(%r14)
	cmpq	$0, 40(%r14)
	je	LBB0_11
## %bb.6:
	movl	(%r15), %edi
	movq	_mmIH_RB_CNTL_RING1@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_IH_RB_CNTL_RING1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	(%r12), %edx
	movq	%rax, %rdi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movq	%rax, %rbx
	movq	%r14, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_9
## %bb.7:
	leaq	64(%r14), %rdi
	movq	_PSP_REG_IH_RB_CNTL_RING1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdx
	callq	_psp_reg_program
	testq	%rax, %rax
	je	LBB0_10
## %bb.8:
	leaq	L_.str.1(%rip), %rdi
	jmp	LBB0_3
LBB0_9:
	movl	(%r15), %edi
	movl	(%r13), %edx
	xorl	%esi, %esi
	movq	%rbx, %rcx
	callq	_WREG32_SOC15
LBB0_10:
	movl	(%r15), %edi
	movq	_mmIH_RB_RPTR_RING1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r15), %edi
	movq	_mmIH_RB_WPTR_RING1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	$0, 24(%r14)
	movq	$0, 32(%r14)
LBB0_11:
	cmpq	$0, 16(%r14)
	je	LBB0_17
## %bb.12:
	movl	(%r15), %edi
	movq	_mmIH_RB_CNTL_RING2@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_IH_RB_CNTL_RING2@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	(%r12), %edx
	movq	%rax, %rdi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movq	%rax, %rbx
	movq	%r14, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_15
## %bb.13:
	leaq	64(%r14), %rdi
	movq	_PSP_REG_IH_RB_CNTL_RING2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdx
	callq	_psp_reg_program
	testq	%rax, %rax
	je	LBB0_16
## %bb.14:
	leaq	L_.str.2(%rip), %rdi
LBB0_3:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_DRM_ERROR                      ## TAILCALL
LBB0_15:
	movl	(%r15), %edi
	movl	(%r13), %edx
	xorl	%esi, %esi
	movq	%rbx, %rcx
	callq	_WREG32_SOC15
LBB0_16:
	movl	(%r15), %edi
	movq	_mmIH_RB_RPTR_RING2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r15), %edi
	movq	_mmIH_RB_WPTR_RING2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	$0, (%r14)
	movq	$0, 8(%r14)
LBB0_17:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_OSSSYS,4,2                     ## @OSSSYS
	.comm	_mmIH_RB_CNTL,4,2               ## @mmIH_RB_CNTL
	.comm	_IH_RB_CNTL,4,2                 ## @IH_RB_CNTL
	.comm	_RB_ENABLE,4,2                  ## @RB_ENABLE
	.comm	_ENABLE_INTR,4,2                ## @ENABLE_INTR
	.comm	_PSP_REG_IH_RB_CNTL,4,2         ## @PSP_REG_IH_RB_CNTL
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"PSP program IH_RB_CNTL failed!\n"

	.comm	_mmIH_RB_RPTR,4,2               ## @mmIH_RB_RPTR
	.comm	_mmIH_RB_WPTR,4,2               ## @mmIH_RB_WPTR
	.comm	_mmIH_RB_CNTL_RING1,4,2         ## @mmIH_RB_CNTL_RING1
	.comm	_IH_RB_CNTL_RING1,4,2           ## @IH_RB_CNTL_RING1
	.comm	_PSP_REG_IH_RB_CNTL_RING1,4,2   ## @PSP_REG_IH_RB_CNTL_RING1
L_.str.1:                               ## @.str.1
	.asciz	"program IH_RB_CNTL_RING1 failed!\n"

	.comm	_mmIH_RB_RPTR_RING1,4,2         ## @mmIH_RB_RPTR_RING1
	.comm	_mmIH_RB_WPTR_RING1,4,2         ## @mmIH_RB_WPTR_RING1
	.comm	_mmIH_RB_CNTL_RING2,4,2         ## @mmIH_RB_CNTL_RING2
	.comm	_IH_RB_CNTL_RING2,4,2           ## @IH_RB_CNTL_RING2
	.comm	_PSP_REG_IH_RB_CNTL_RING2,4,2   ## @PSP_REG_IH_RB_CNTL_RING2
L_.str.2:                               ## @.str.2
	.asciz	"program IH_RB_CNTL_RING2 failed!\n"

	.comm	_mmIH_RB_RPTR_RING2,4,2         ## @mmIH_RB_RPTR_RING2
	.comm	_mmIH_RB_WPTR_RING2,4,2         ## @mmIH_RB_WPTR_RING2
	.no_dead_strip	_vega10_ih_disable_interrupts
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vega10_ih_disable_interrupts
_vega10_ih_disable_interrupts:          ; @vega10_ih_disable_interrupts
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x21, _OSSSYS@GOTPAGE
Lloh1:
	ldr	x21, [x21, _OSSSYS@GOTPAGEOFF]
	ldr	w0, [x21]
Lloh2:
	adrp	x23, _mmIH_RB_CNTL@GOTPAGE
Lloh3:
	ldr	x23, [x23, _mmIH_RB_CNTL@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh4:
	adrp	x20, _IH_RB_CNTL@GOTPAGE
Lloh5:
	ldr	x20, [x20, _IH_RB_CNTL@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh6:
	adrp	x22, _RB_ENABLE@GOTPAGE
Lloh7:
	ldr	x22, [x22, _RB_ENABLE@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x20]
Lloh8:
	adrp	x8, _ENABLE_INTR@GOTPAGE
Lloh9:
	ldr	x8, [x8, _ENABLE_INTR@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	mov	x20, x0
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_3
; %bb.1:
	add	x0, x19, #64
Lloh11:
	adrp	x8, _PSP_REG_IH_RB_CNTL@GOTPAGE
Lloh12:
	ldr	x8, [x8, _PSP_REG_IH_RB_CNTL@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
	mov	x2, x20
	bl	_psp_reg_program
	cbz	x0, LBB0_4
; %bb.2:
Lloh14:
	adrp	x0, l_.str@PAGE
Lloh15:
	add	x0, x0, l_.str@PAGEOFF
	b	LBB0_14
LBB0_3:
	ldr	w0, [x21]
	ldr	w2, [x23]
	mov	w1, #0
	mov	x3, x20
	bl	_WREG32_SOC15
LBB0_4:
	ldr	w0, [x21]
Lloh16:
	adrp	x8, _mmIH_RB_RPTR@GOTPAGE
Lloh17:
	ldr	x8, [x8, _mmIH_RB_RPTR@GOTPAGEOFF]
Lloh18:
	ldr	w2, [x8]
	mov	w1, #0
	mov	x3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x21]
Lloh19:
	adrp	x8, _mmIH_RB_WPTR@GOTPAGE
Lloh20:
	ldr	x8, [x8, _mmIH_RB_WPTR@GOTPAGEOFF]
Lloh21:
	ldr	w2, [x8]
	mov	w1, #0
	mov	x3, #0
	bl	_WREG32_SOC15
	str	wzr, [x19, #48]
	str	xzr, [x19, #56]
	ldr	x8, [x19, #40]
	cbz	x8, LBB0_10
; %bb.5:
	ldr	w0, [x21]
Lloh22:
	adrp	x23, _mmIH_RB_CNTL_RING1@GOTPAGE
Lloh23:
	ldr	x23, [x23, _mmIH_RB_CNTL_RING1@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh24:
	adrp	x8, _IH_RB_CNTL_RING1@GOTPAGE
Lloh25:
	ldr	x8, [x8, _IH_RB_CNTL_RING1@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	ldr	w2, [x22]
	mov	w3, #0
	bl	_REG_SET_FIELD
	mov	x20, x0
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_8
; %bb.6:
	add	x0, x19, #64
Lloh27:
	adrp	x8, _PSP_REG_IH_RB_CNTL_RING1@GOTPAGE
Lloh28:
	ldr	x8, [x8, _PSP_REG_IH_RB_CNTL_RING1@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	mov	x2, x20
	bl	_psp_reg_program
	cbz	x0, LBB0_9
; %bb.7:
Lloh30:
	adrp	x0, l_.str.1@PAGE
Lloh31:
	add	x0, x0, l_.str.1@PAGEOFF
	b	LBB0_14
LBB0_8:
	ldr	w0, [x21]
	ldr	w2, [x23]
	mov	w1, #0
	mov	x3, x20
	bl	_WREG32_SOC15
LBB0_9:
	ldr	w0, [x21]
Lloh32:
	adrp	x8, _mmIH_RB_RPTR_RING1@GOTPAGE
Lloh33:
	ldr	x8, [x8, _mmIH_RB_RPTR_RING1@GOTPAGEOFF]
Lloh34:
	ldr	w2, [x8]
	mov	w1, #0
	mov	x3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x21]
Lloh35:
	adrp	x8, _mmIH_RB_WPTR_RING1@GOTPAGE
Lloh36:
	ldr	x8, [x8, _mmIH_RB_WPTR_RING1@GOTPAGEOFF]
Lloh37:
	ldr	w2, [x8]
	mov	w1, #0
	mov	x3, #0
	bl	_WREG32_SOC15
	str	wzr, [x19, #24]
	str	xzr, [x19, #32]
LBB0_10:
	ldr	x8, [x19, #16]
	cbz	x8, LBB0_17
; %bb.11:
	ldr	w0, [x21]
Lloh38:
	adrp	x23, _mmIH_RB_CNTL_RING2@GOTPAGE
Lloh39:
	ldr	x23, [x23, _mmIH_RB_CNTL_RING2@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh40:
	adrp	x8, _IH_RB_CNTL_RING2@GOTPAGE
Lloh41:
	ldr	x8, [x8, _IH_RB_CNTL_RING2@GOTPAGEOFF]
Lloh42:
	ldr	w1, [x8]
	ldr	w2, [x22]
	mov	w3, #0
	bl	_REG_SET_FIELD
	mov	x20, x0
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_15
; %bb.12:
	add	x0, x19, #64
Lloh43:
	adrp	x8, _PSP_REG_IH_RB_CNTL_RING2@GOTPAGE
Lloh44:
	ldr	x8, [x8, _PSP_REG_IH_RB_CNTL_RING2@GOTPAGEOFF]
Lloh45:
	ldr	w1, [x8]
	mov	x2, x20
	bl	_psp_reg_program
	cbz	x0, LBB0_16
; %bb.13:
Lloh46:
	adrp	x0, l_.str.2@PAGE
Lloh47:
	add	x0, x0, l_.str.2@PAGEOFF
LBB0_14:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_DRM_ERROR
LBB0_15:
	ldr	w0, [x21]
	ldr	w2, [x23]
	mov	w1, #0
	mov	x3, x20
	bl	_WREG32_SOC15
LBB0_16:
	ldr	w0, [x21]
Lloh48:
	adrp	x8, _mmIH_RB_RPTR_RING2@GOTPAGE
Lloh49:
	ldr	x8, [x8, _mmIH_RB_RPTR_RING2@GOTPAGEOFF]
Lloh50:
	ldr	w2, [x8]
	mov	w1, #0
	mov	x3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x21]
Lloh51:
	adrp	x8, _mmIH_RB_WPTR_RING2@GOTPAGE
Lloh52:
	ldr	x8, [x8, _mmIH_RB_WPTR_RING2@GOTPAGEOFF]
Lloh53:
	ldr	w2, [x8]
	mov	w1, #0
	mov	x3, #0
	bl	_WREG32_SOC15
	str	wzr, [x19]
	str	xzr, [x19, #8]
LBB0_17:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpAdd	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpAdd	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpAdd	Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.cfi_endproc
                                        ; -- End function
	.comm	_OSSSYS,4,2                     ; @OSSSYS
	.comm	_mmIH_RB_CNTL,4,2               ; @mmIH_RB_CNTL
	.comm	_IH_RB_CNTL,4,2                 ; @IH_RB_CNTL
	.comm	_RB_ENABLE,4,2                  ; @RB_ENABLE
	.comm	_ENABLE_INTR,4,2                ; @ENABLE_INTR
	.comm	_PSP_REG_IH_RB_CNTL,4,2         ; @PSP_REG_IH_RB_CNTL
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"PSP program IH_RB_CNTL failed!\n"

	.comm	_mmIH_RB_RPTR,4,2               ; @mmIH_RB_RPTR
	.comm	_mmIH_RB_WPTR,4,2               ; @mmIH_RB_WPTR
	.comm	_mmIH_RB_CNTL_RING1,4,2         ; @mmIH_RB_CNTL_RING1
	.comm	_IH_RB_CNTL_RING1,4,2           ; @IH_RB_CNTL_RING1
	.comm	_PSP_REG_IH_RB_CNTL_RING1,4,2   ; @PSP_REG_IH_RB_CNTL_RING1
l_.str.1:                               ; @.str.1
	.asciz	"program IH_RB_CNTL_RING1 failed!\n"

	.comm	_mmIH_RB_RPTR_RING1,4,2         ; @mmIH_RB_RPTR_RING1
	.comm	_mmIH_RB_WPTR_RING1,4,2         ; @mmIH_RB_WPTR_RING1
	.comm	_mmIH_RB_CNTL_RING2,4,2         ; @mmIH_RB_CNTL_RING2
	.comm	_IH_RB_CNTL_RING2,4,2           ; @IH_RB_CNTL_RING2
	.comm	_PSP_REG_IH_RB_CNTL_RING2,4,2   ; @PSP_REG_IH_RB_CNTL_RING2
l_.str.2:                               ; @.str.2
	.asciz	"program IH_RB_CNTL_RING2 failed!\n"

	.comm	_mmIH_RB_RPTR_RING2,4,2         ; @mmIH_RB_RPTR_RING2
	.comm	_mmIH_RB_WPTR_RING2,4,2         ; @mmIH_RB_WPTR_RING2
	.no_dead_strip	_vega10_ih_disable_interrupts
.subsections_via_symbols
