	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v1_0_stop_dpg_mode
_vcn_v1_0_stop_dpg_mode:                ## @vcn_v1_0_stop_dpg_mode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_UVD@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_mmUVD_POWER_STATUS@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	movq	_UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF@GOTPCREL(%rip), %r15
	movl	(%r15), %ecx
	movq	_UVD_POWER_STATUS__UVD_POWER_STATUS_MASK@GOTPCREL(%rip), %r12
	movl	(%r12), %r8d
	xorl	%esi, %esi
	xorl	%r9d, %r9d
	callq	_SOC15_WAIT_ON_RREG
	movl	(%rbx), %edi
	movq	_mmUVD_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	(%rbx), %edi
	movq	_mmUVD_RB_RPTR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_SOC15_WAIT_ON_RREG
	movl	(%rbx), %edi
	movq	_mmUVD_RB_WPTR2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	(%rbx), %edi
	movq	_mmUVD_RB_RPTR2@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_SOC15_WAIT_ON_RREG
	movl	(%rbx), %edi
	movq	_mmUVD_JRBC_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	(%rbx), %edi
	movq	_mmUVD_JRBC_RB_RPTR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_SOC15_WAIT_ON_RREG
	movl	(%rbx), %edi
	movq	_mmUVD_RBC_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	andl	$2147483647, %eax               ## imm = 0x7FFFFFFF
	movl	(%rbx), %edi
	movq	_mmUVD_RBC_RB_RPTR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_SOC15_WAIT_ON_RREG
	movl	(%rbx), %edi
	movl	(%r14), %edx
	movl	(%r15), %ecx
	movl	(%r12), %r8d
	xorl	%esi, %esi
	xorl	%r9d, %r9d
	callq	_SOC15_WAIT_ON_RREG
	movl	(%rbx), %edi
	movl	(%r14), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_POWER_STATUS__UVD_PG_MODE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_POWER_STATUS,4,2         ## @mmUVD_POWER_STATUS
	.comm	_UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,4,2 ## @UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF
	.comm	_UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,4,2 ## @UVD_POWER_STATUS__UVD_POWER_STATUS_MASK
	.comm	_mmUVD_RB_WPTR,4,2              ## @mmUVD_RB_WPTR
	.comm	_mmUVD_RB_RPTR,4,2              ## @mmUVD_RB_RPTR
	.comm	_mmUVD_RB_WPTR2,4,2             ## @mmUVD_RB_WPTR2
	.comm	_mmUVD_RB_RPTR2,4,2             ## @mmUVD_RB_RPTR2
	.comm	_mmUVD_JRBC_RB_WPTR,4,2         ## @mmUVD_JRBC_RB_WPTR
	.comm	_mmUVD_JRBC_RB_RPTR,4,2         ## @mmUVD_JRBC_RB_RPTR
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ## @mmUVD_RBC_RB_WPTR
	.comm	_mmUVD_RBC_RB_RPTR,4,2          ## @mmUVD_RBC_RB_RPTR
	.comm	_UVD_POWER_STATUS__UVD_PG_MODE_MASK,4,2 ## @UVD_POWER_STATUS__UVD_PG_MODE_MASK
	.no_dead_strip	_vcn_v1_0_stop_dpg_mode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v1_0_stop_dpg_mode
_vcn_v1_0_stop_dpg_mode:                ; @vcn_v1_0_stop_dpg_mode
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
Lloh0:
	adrp	x19, _UVD@GOTPAGE
Lloh1:
	ldr	x19, [x19, _UVD@GOTPAGEOFF]
	ldr	w0, [x19]
Lloh2:
	adrp	x20, _mmUVD_POWER_STATUS@GOTPAGE
Lloh3:
	ldr	x20, [x20, _mmUVD_POWER_STATUS@GOTPAGEOFF]
	ldr	w2, [x20]
Lloh4:
	adrp	x21, _UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF@GOTPAGE
Lloh5:
	ldr	x21, [x21, _UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF@GOTPAGEOFF]
	ldr	w3, [x21]
Lloh6:
	adrp	x22, _UVD_POWER_STATUS__UVD_POWER_STATUS_MASK@GOTPAGE
Lloh7:
	ldr	x22, [x22, _UVD_POWER_STATUS__UVD_POWER_STATUS_MASK@GOTPAGEOFF]
	ldr	w4, [x22]
	mov	w1, #0
	mov	w5, #0
	bl	_SOC15_WAIT_ON_RREG
	ldr	w0, [x19]
Lloh8:
	adrp	x8, _mmUVD_RB_WPTR@GOTPAGE
Lloh9:
	ldr	x8, [x8, _mmUVD_RB_WPTR@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_RREG32_SOC15
	mov	x3, x0
	ldr	w0, [x19]
Lloh11:
	adrp	x8, _mmUVD_RB_RPTR@GOTPAGE
Lloh12:
	ldr	x8, [x8, _mmUVD_RB_RPTR@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_SOC15_WAIT_ON_RREG
	ldr	w0, [x19]
Lloh14:
	adrp	x8, _mmUVD_RB_WPTR2@GOTPAGE
Lloh15:
	ldr	x8, [x8, _mmUVD_RB_WPTR2@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_RREG32_SOC15
	mov	x3, x0
	ldr	w0, [x19]
Lloh17:
	adrp	x8, _mmUVD_RB_RPTR2@GOTPAGE
Lloh18:
	ldr	x8, [x8, _mmUVD_RB_RPTR2@GOTPAGEOFF]
Lloh19:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_SOC15_WAIT_ON_RREG
	ldr	w0, [x19]
Lloh20:
	adrp	x8, _mmUVD_JRBC_RB_WPTR@GOTPAGE
Lloh21:
	ldr	x8, [x8, _mmUVD_JRBC_RB_WPTR@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_RREG32_SOC15
	mov	x3, x0
	ldr	w0, [x19]
Lloh23:
	adrp	x8, _mmUVD_JRBC_RB_RPTR@GOTPAGE
Lloh24:
	ldr	x8, [x8, _mmUVD_JRBC_RB_RPTR@GOTPAGEOFF]
Lloh25:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_SOC15_WAIT_ON_RREG
	ldr	w0, [x19]
Lloh26:
	adrp	x8, _mmUVD_RBC_RB_WPTR@GOTPAGE
Lloh27:
	ldr	x8, [x8, _mmUVD_RBC_RB_WPTR@GOTPAGEOFF]
Lloh28:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_RREG32_SOC15
	and	w3, w0, #0x7fffffff
	ldr	w0, [x19]
Lloh29:
	adrp	x8, _mmUVD_RBC_RB_RPTR@GOTPAGE
Lloh30:
	ldr	x8, [x8, _mmUVD_RBC_RB_RPTR@GOTPAGEOFF]
Lloh31:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_SOC15_WAIT_ON_RREG
	ldr	w0, [x19]
	ldr	w2, [x20]
	ldr	w3, [x21]
	ldr	w4, [x22]
	mov	w1, #0
	mov	w5, #0
	bl	_SOC15_WAIT_ON_RREG
	ldr	w0, [x19]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh32:
	adrp	x8, _UVD_POWER_STATUS__UVD_PG_MODE_MASK@GOTPAGE
Lloh33:
	ldr	x8, [x8, _UVD_POWER_STATUS__UVD_PG_MODE_MASK@GOTPAGEOFF]
Lloh34:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	mov	w0, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_POWER_STATUS,4,2         ; @mmUVD_POWER_STATUS
	.comm	_UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,4,2 ; @UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF
	.comm	_UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,4,2 ; @UVD_POWER_STATUS__UVD_POWER_STATUS_MASK
	.comm	_mmUVD_RB_WPTR,4,2              ; @mmUVD_RB_WPTR
	.comm	_mmUVD_RB_RPTR,4,2              ; @mmUVD_RB_RPTR
	.comm	_mmUVD_RB_WPTR2,4,2             ; @mmUVD_RB_WPTR2
	.comm	_mmUVD_RB_RPTR2,4,2             ; @mmUVD_RB_RPTR2
	.comm	_mmUVD_JRBC_RB_WPTR,4,2         ; @mmUVD_JRBC_RB_WPTR
	.comm	_mmUVD_JRBC_RB_RPTR,4,2         ; @mmUVD_JRBC_RB_RPTR
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ; @mmUVD_RBC_RB_WPTR
	.comm	_mmUVD_RBC_RB_RPTR,4,2          ; @mmUVD_RBC_RB_RPTR
	.comm	_UVD_POWER_STATUS__UVD_PG_MODE_MASK,4,2 ; @UVD_POWER_STATUS__UVD_PG_MODE_MASK
	.no_dead_strip	_vcn_v1_0_stop_dpg_mode
.subsections_via_symbols
