	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ironlake_compute_dpll
_ironlake_compute_dpll:                 ## @ironlake_compute_dpll
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r12
	movq	%rsi, %r13
	movl	(%rdi), %edi
	callq	_to_i915
	movq	%rax, %r14
	movq	_INTEL_OUTPUT_LVDS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_intel_crtc_has_type
	testq	%rax, %rax
	je	LBB0_6
## %bb.1:
	movq	%r14, %rdi
	callq	_intel_panel_use_ssc
	testq	%rax, %rax
	je	LBB0_3
## %bb.2:
	cmpl	$100000, (%r14)                 ## imm = 0x186A0
	je	LBB0_5
LBB0_3:
	movq	%r14, %rdi
	callq	_HAS_PCH_IBX
	movl	$21, %ebx
	testq	%rax, %rax
	je	LBB0_7
## %bb.4:
	movq	%r14, %rdi
	callq	_intel_is_dual_link_lvds
	testq	%rax, %rax
	je	LBB0_7
LBB0_5:
	movl	$25, %ebx
	jmp	LBB0_7
LBB0_6:
	xorl	%ebx, %ebx
	cmpq	$0, 32(%r13)
	sete	%bl
	orl	$20, %ebx
LBB0_7:
	movq	%r14, -56(%rbp)                 ## 8-byte Spill
	leaq	16(%r13), %r14
	movq	%r14, %rdi
	callq	_i9xx_dpll_compute_fp
	movl	%eax, %r15d
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_ironlake_needs_fb_cb_tune
	xorl	%r14d, %r14d
	movq	_FP_CB_TUNE@GOTPCREL(%rip), %rcx
	testq	%rax, %rax
	je	LBB0_9
## %bb.8:
	movl	(%rcx), %r14d
LBB0_9:
	orl	%r15d, %r14d
	movl	%r14d, %eax
	testq	%r12, %r12
	je	LBB0_12
## %bb.10:
	movq	%rcx, %r15
	movq	%r12, %rdi
	callq	_i9xx_dpll_compute_fp
	imull	4(%r12), %ebx
	cmpl	%ebx, (%r12)
	jge	LBB0_12
## %bb.11:
	orl	(%r15), %eax
LBB0_12:
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	_INTEL_OUTPUT_LVDS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_intel_crtc_has_type
	testq	%rax, %rax
	jne	LBB0_13
## %bb.14:
	movq	_DPLLB_MODE_DAC_SERIAL@GOTPCREL(%rip), %rax
	jmp	LBB0_15
LBB0_13:
	movq	_DPLLB_MODE_LVDS@GOTPCREL(%rip), %rax
LBB0_15:
	movl	(%r13), %ebx
	decl	%ebx
	movq	_PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %ebx
	orl	(%rax), %ebx
	movq	_INTEL_OUTPUT_SDVO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_intel_crtc_has_type
	testq	%rax, %rax
	jne	LBB0_17
## %bb.16:
	movq	_INTEL_OUTPUT_HDMI@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_intel_crtc_has_type
	testq	%rax, %rax
	je	LBB0_18
LBB0_17:
	movq	_DPLL_SDVO_HIGH_SPEED@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
LBB0_18:
	movq	%r13, %rdi
	callq	_intel_crtc_has_dp_encoder
	xorl	%r12d, %r12d
	movq	_DPLL_SDVO_HIGH_SPEED@GOTPCREL(%rip), %r15
	testq	%rax, %rax
	je	LBB0_20
## %bb.19:
	movl	(%r15), %r12d
LBB0_20:
	orl	%ebx, %r12d
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_INTEL_INFO
	cmpl	$3, (%rax)
	jne	LBB0_23
## %bb.21:
	movq	_INTEL_OUTPUT_ANALOG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_intel_crtc_has_type
	testq	%rax, %rax
	je	LBB0_23
## %bb.22:
	orl	(%r15), %r12d
LBB0_23:
	movb	24(%r13), %cl
	decb	%cl
	movl	$1, %ebx
	shll	%cl, %ebx
	movq	_DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	%ebx, %eax
	shll	%cl, %eax
	movq	_DPLL_FPA1_P1_POST_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %ebx
	orl	%r12d, %ebx
	orl	%eax, %ebx
	movl	28(%r13), %eax
	addl	$-5, %eax
	cmpl	$9, %eax
	ja	LBB0_30
## %bb.24:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_25:
	movq	_DPLL_DAC_SERIAL_P2_CLOCK_DIV_5@GOTPCREL(%rip), %rax
	jmp	LBB0_29
LBB0_26:
	movq	_DPLLB_LVDS_P2_CLOCK_DIV_7@GOTPCREL(%rip), %rax
	jmp	LBB0_29
LBB0_27:
	movq	_DPLL_DAC_SERIAL_P2_CLOCK_DIV_10@GOTPCREL(%rip), %rax
	jmp	LBB0_29
LBB0_28:
	movq	_DPLLB_LVDS_P2_CLOCK_DIV_14@GOTPCREL(%rip), %rax
LBB0_29:
	orl	(%rax), %ebx
LBB0_30:
	movq	_INTEL_OUTPUT_LVDS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_intel_crtc_has_type
	testq	%rax, %rax
	je	LBB0_33
## %bb.31:
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_intel_panel_use_ssc
	testq	%rax, %rax
	je	LBB0_33
## %bb.32:
	movq	_PLLB_REF_INPUT_SPREADSPECTRUMIN@GOTPCREL(%rip), %rax
	jmp	LBB0_34
LBB0_33:
	movq	_PLL_REF_INPUT_DREFCLK@GOTPCREL(%rip), %rax
LBB0_34:
	movl	-44(%rbp), %ecx                 ## 4-byte Reload
	orl	(%rax), %ebx
	movq	_DPLL_VCO_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	%ebx, 4(%r13)
	movl	%r14d, 8(%r13)
	movl	%ecx, 12(%r13)
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_25, LBB0_25-LJTI0_0
.set L0_0_set_30, LBB0_30-LJTI0_0
.set L0_0_set_26, LBB0_26-LJTI0_0
.set L0_0_set_27, LBB0_27-LJTI0_0
.set L0_0_set_28, LBB0_28-LJTI0_0
LJTI0_0:
	.long	L0_0_set_25
	.long	L0_0_set_30
	.long	L0_0_set_26
	.long	L0_0_set_30
	.long	L0_0_set_30
	.long	L0_0_set_27
	.long	L0_0_set_30
	.long	L0_0_set_30
	.long	L0_0_set_30
	.long	L0_0_set_28
	.end_data_region
                                        ## -- End function
	.comm	_INTEL_OUTPUT_LVDS,4,2          ## @INTEL_OUTPUT_LVDS
	.comm	_FP_CB_TUNE,4,2                 ## @FP_CB_TUNE
	.comm	_DPLLB_MODE_LVDS,4,2            ## @DPLLB_MODE_LVDS
	.comm	_DPLLB_MODE_DAC_SERIAL,4,2      ## @DPLLB_MODE_DAC_SERIAL
	.comm	_PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT,4,2 ## @PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
	.comm	_INTEL_OUTPUT_SDVO,4,2          ## @INTEL_OUTPUT_SDVO
	.comm	_INTEL_OUTPUT_HDMI,4,2          ## @INTEL_OUTPUT_HDMI
	.comm	_DPLL_SDVO_HIGH_SPEED,4,2       ## @DPLL_SDVO_HIGH_SPEED
	.comm	_INTEL_OUTPUT_ANALOG,4,2        ## @INTEL_OUTPUT_ANALOG
	.comm	_DPLL_FPA01_P1_POST_DIV_SHIFT,4,2 ## @DPLL_FPA01_P1_POST_DIV_SHIFT
	.comm	_DPLL_FPA1_P1_POST_DIV_SHIFT,4,2 ## @DPLL_FPA1_P1_POST_DIV_SHIFT
	.comm	_DPLL_DAC_SERIAL_P2_CLOCK_DIV_5,4,2 ## @DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
	.comm	_DPLLB_LVDS_P2_CLOCK_DIV_7,4,2  ## @DPLLB_LVDS_P2_CLOCK_DIV_7
	.comm	_DPLL_DAC_SERIAL_P2_CLOCK_DIV_10,4,2 ## @DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
	.comm	_DPLLB_LVDS_P2_CLOCK_DIV_14,4,2 ## @DPLLB_LVDS_P2_CLOCK_DIV_14
	.comm	_PLLB_REF_INPUT_SPREADSPECTRUMIN,4,2 ## @PLLB_REF_INPUT_SPREADSPECTRUMIN
	.comm	_PLL_REF_INPUT_DREFCLK,4,2      ## @PLL_REF_INPUT_DREFCLK
	.comm	_DPLL_VCO_ENABLE,4,2            ## @DPLL_VCO_ENABLE
	.no_dead_strip	_ironlake_compute_dpll
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ironlake_compute_dpll
_ironlake_compute_dpll:                 ; @ironlake_compute_dpll
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x22, x2
	mov	x19, x1
	ldr	w0, [x0]
	bl	_to_i915
	mov	x20, x0
Lloh0:
	adrp	x25, _INTEL_OUTPUT_LVDS@GOTPAGE
Lloh1:
	ldr	x25, [x25, _INTEL_OUTPUT_LVDS@GOTPAGEOFF]
	ldr	w1, [x25]
	mov	x0, x19
	bl	_intel_crtc_has_type
	cbz	x0, LBB0_6
; %bb.1:
	mov	x0, x20
	bl	_intel_panel_use_ssc
	cbz	x0, LBB0_3
; %bb.2:
	ldr	w8, [x20]
	sub	w8, w8, #24, lsl #12            ; =98304
	cmp	w8, #1696
	b.eq	LBB0_5
LBB0_3:
	mov	x0, x20
	bl	_HAS_PCH_IBX
	cbz	x0, LBB0_7
; %bb.4:
	mov	x0, x20
	bl	_intel_is_dual_link_lvds
	cbz	x0, LBB0_7
LBB0_5:
	mov	w23, #25
	b	LBB0_8
LBB0_6:
	ldr	x8, [x19, #32]
	cmp	x8, #0
	mov	w8, #20
	cinc	w23, w8, eq
	b	LBB0_8
LBB0_7:
	mov	w23, #21
LBB0_8:
	add	x21, x19, #16
	mov	x0, x21
	bl	_i9xx_dpll_compute_fp
	mov	x24, x0
	mov	x0, x21
	mov	x1, x23
	bl	_ironlake_needs_fb_cb_tune
Lloh2:
	adrp	x26, _FP_CB_TUNE@GOTPAGE
Lloh3:
	ldr	x26, [x26, _FP_CB_TUNE@GOTPAGEOFF]
	ldr	w8, [x26]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w24, w8, w24
	mov	x21, x24
	cbz	x22, LBB0_11
; %bb.9:
	mov	x0, x22
	bl	_i9xx_dpll_compute_fp
	mov	x21, x0
	ldp	w8, w9, [x22]
	mul	w9, w9, w23
	cmp	w8, w9
	b.ge	LBB0_11
; %bb.10:
	ldr	w8, [x26]
	orr	w21, w8, w21
LBB0_11:
	ldr	w1, [x25]
	mov	x0, x19
	bl	_intel_crtc_has_type
Lloh4:
	adrp	x8, _DPLLB_MODE_DAC_SERIAL@GOTPAGE
Lloh5:
	ldr	x8, [x8, _DPLLB_MODE_DAC_SERIAL@GOTPAGEOFF]
Lloh6:
	adrp	x9, _DPLLB_MODE_LVDS@GOTPAGE
Lloh7:
	ldr	x9, [x9, _DPLLB_MODE_LVDS@GOTPAGEOFF]
	cmp	x0, #0
	csel	x8, x8, x9, eq
	ldr	w8, [x8]
	ldr	w9, [x19]
	sub	w9, w9, #1
Lloh8:
	adrp	x10, _PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT@GOTPAGE
Lloh9:
	ldr	x10, [x10, _PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT@GOTPAGEOFF]
Lloh10:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w23, w9, w8
Lloh11:
	adrp	x8, _INTEL_OUTPUT_SDVO@GOTPAGE
Lloh12:
	ldr	x8, [x8, _INTEL_OUTPUT_SDVO@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_intel_crtc_has_type
Lloh14:
	adrp	x22, _DPLL_SDVO_HIGH_SPEED@GOTPAGE
Lloh15:
	ldr	x22, [x22, _DPLL_SDVO_HIGH_SPEED@GOTPAGEOFF]
	cbnz	x0, LBB0_13
; %bb.12:
Lloh16:
	adrp	x8, _INTEL_OUTPUT_HDMI@GOTPAGE
Lloh17:
	ldr	x8, [x8, _INTEL_OUTPUT_HDMI@GOTPAGEOFF]
Lloh18:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_intel_crtc_has_type
	cbz	x0, LBB0_14
LBB0_13:
	ldr	w8, [x22]
	orr	w23, w8, w23
LBB0_14:
	mov	x0, x19
	bl	_intel_crtc_has_dp_encoder
	ldr	w8, [x22]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w23, w8, w23
	mov	x0, x20
	bl	_INTEL_INFO
	ldr	w8, [x0]
	cmp	w8, #3
	b.ne	LBB0_17
; %bb.15:
Lloh19:
	adrp	x8, _INTEL_OUTPUT_ANALOG@GOTPAGE
Lloh20:
	ldr	x8, [x8, _INTEL_OUTPUT_ANALOG@GOTPAGEOFF]
Lloh21:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_intel_crtc_has_type
	cbz	x0, LBB0_17
; %bb.16:
	ldr	w8, [x22]
	orr	w23, w8, w23
LBB0_17:
	ldp	w8, w9, [x19, #24]
	sub	w8, w8, #1
	mov	w10, #1
	lsl	w8, w10, w8
Lloh22:
	adrp	x10, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGE
Lloh23:
	ldr	x10, [x10, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGEOFF]
Lloh24:
	ldr	w10, [x10]
	lsl	w10, w8, w10
Lloh25:
	adrp	x11, _DPLL_FPA1_P1_POST_DIV_SHIFT@GOTPAGE
Lloh26:
	ldr	x11, [x11, _DPLL_FPA1_P1_POST_DIV_SHIFT@GOTPAGEOFF]
	orr	w10, w10, w23
Lloh27:
	ldr	w11, [x11]
	lsl	w8, w8, w11
	orr	w22, w10, w8
	sub	w8, w9, #5
	cmp	w8, #9
	b.hi	LBB0_24
; %bb.18:
Lloh28:
	adrp	x9, lJTI0_0@PAGE
Lloh29:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_19
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_19:
Lloh30:
	adrp	x8, _DPLL_DAC_SERIAL_P2_CLOCK_DIV_5@GOTPAGE
Lloh31:
	ldr	x8, [x8, _DPLL_DAC_SERIAL_P2_CLOCK_DIV_5@GOTPAGEOFF]
	b	LBB0_23
LBB0_20:
Lloh32:
	adrp	x8, _DPLLB_LVDS_P2_CLOCK_DIV_7@GOTPAGE
Lloh33:
	ldr	x8, [x8, _DPLLB_LVDS_P2_CLOCK_DIV_7@GOTPAGEOFF]
	b	LBB0_23
LBB0_21:
Lloh34:
	adrp	x8, _DPLL_DAC_SERIAL_P2_CLOCK_DIV_10@GOTPAGE
Lloh35:
	ldr	x8, [x8, _DPLL_DAC_SERIAL_P2_CLOCK_DIV_10@GOTPAGEOFF]
	b	LBB0_23
LBB0_22:
Lloh36:
	adrp	x8, _DPLLB_LVDS_P2_CLOCK_DIV_14@GOTPAGE
Lloh37:
	ldr	x8, [x8, _DPLLB_LVDS_P2_CLOCK_DIV_14@GOTPAGEOFF]
LBB0_23:
	ldr	w8, [x8]
	orr	w22, w8, w22
LBB0_24:
	ldr	w1, [x25]
	mov	x0, x19
	bl	_intel_crtc_has_type
	cbz	x0, LBB0_27
; %bb.25:
	mov	x0, x20
	bl	_intel_panel_use_ssc
	cbz	x0, LBB0_27
; %bb.26:
Lloh38:
	adrp	x8, _PLLB_REF_INPUT_SPREADSPECTRUMIN@GOTPAGE
Lloh39:
	ldr	x8, [x8, _PLLB_REF_INPUT_SPREADSPECTRUMIN@GOTPAGEOFF]
	b	LBB0_28
LBB0_27:
Lloh40:
	adrp	x8, _PLL_REF_INPUT_DREFCLK@GOTPAGE
Lloh41:
	ldr	x8, [x8, _PLL_REF_INPUT_DREFCLK@GOTPAGEOFF]
LBB0_28:
	ldr	w8, [x8]
Lloh42:
	adrp	x9, _DPLL_VCO_ENABLE@GOTPAGE
Lloh43:
	ldr	x9, [x9, _DPLL_VCO_ENABLE@GOTPAGEOFF]
	orr	w8, w8, w22
Lloh44:
	ldr	w9, [x9]
	orr	w8, w8, w9
	stp	w8, w24, [x19, #4]
	str	w21, [x19, #12]
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpAdd	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_19-LBB0_19)>>2
	.byte	(LBB0_24-LBB0_19)>>2
	.byte	(LBB0_20-LBB0_19)>>2
	.byte	(LBB0_24-LBB0_19)>>2
	.byte	(LBB0_24-LBB0_19)>>2
	.byte	(LBB0_21-LBB0_19)>>2
	.byte	(LBB0_24-LBB0_19)>>2
	.byte	(LBB0_24-LBB0_19)>>2
	.byte	(LBB0_24-LBB0_19)>>2
	.byte	(LBB0_22-LBB0_19)>>2
                                        ; -- End function
	.comm	_INTEL_OUTPUT_LVDS,4,2          ; @INTEL_OUTPUT_LVDS
	.comm	_FP_CB_TUNE,4,2                 ; @FP_CB_TUNE
	.comm	_DPLLB_MODE_LVDS,4,2            ; @DPLLB_MODE_LVDS
	.comm	_DPLLB_MODE_DAC_SERIAL,4,2      ; @DPLLB_MODE_DAC_SERIAL
	.comm	_PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT,4,2 ; @PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
	.comm	_INTEL_OUTPUT_SDVO,4,2          ; @INTEL_OUTPUT_SDVO
	.comm	_INTEL_OUTPUT_HDMI,4,2          ; @INTEL_OUTPUT_HDMI
	.comm	_DPLL_SDVO_HIGH_SPEED,4,2       ; @DPLL_SDVO_HIGH_SPEED
	.comm	_INTEL_OUTPUT_ANALOG,4,2        ; @INTEL_OUTPUT_ANALOG
	.comm	_DPLL_FPA01_P1_POST_DIV_SHIFT,4,2 ; @DPLL_FPA01_P1_POST_DIV_SHIFT
	.comm	_DPLL_FPA1_P1_POST_DIV_SHIFT,4,2 ; @DPLL_FPA1_P1_POST_DIV_SHIFT
	.comm	_DPLL_DAC_SERIAL_P2_CLOCK_DIV_5,4,2 ; @DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
	.comm	_DPLLB_LVDS_P2_CLOCK_DIV_7,4,2  ; @DPLLB_LVDS_P2_CLOCK_DIV_7
	.comm	_DPLL_DAC_SERIAL_P2_CLOCK_DIV_10,4,2 ; @DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
	.comm	_DPLLB_LVDS_P2_CLOCK_DIV_14,4,2 ; @DPLLB_LVDS_P2_CLOCK_DIV_14
	.comm	_PLLB_REF_INPUT_SPREADSPECTRUMIN,4,2 ; @PLLB_REF_INPUT_SPREADSPECTRUMIN
	.comm	_PLL_REF_INPUT_DREFCLK,4,2      ; @PLL_REF_INPUT_DREFCLK
	.comm	_DPLL_VCO_ENABLE,4,2            ; @DPLL_VCO_ENABLE
	.no_dead_strip	_ironlake_compute_dpll
.subsections_via_symbols
