	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_is_support_sw_smu              ## -- Begin function is_support_sw_smu
	.p2align	4, 0x90
_is_support_sw_smu:                     ## @is_support_sw_smu
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	(%rdi), %rax
	movq	_amdgpu_dpm@GOTPCREL(%rip), %rcx
	xorl	%edx, %edx
	cmpl	$2, (%rcx)
	sete	%dl
	movq	_CHIP_ARCTURUS@GOTPCREL(%rip), %rcx
	xorl	%esi, %esi
	cmpq	(%rcx), %rax
	movq	_CHIP_VEGA20@GOTPCREL(%rip), %rcx
	setge	%sil
	cmpq	(%rcx), %rax
	cmovnel	%esi, %edx
	movzbl	%dl, %eax
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CHIP_VEGA20,8,3                ## @CHIP_VEGA20
	.comm	_amdgpu_dpm,4,2                 ## @amdgpu_dpm
	.comm	_CHIP_ARCTURUS,8,3              ## @CHIP_ARCTURUS
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_is_support_sw_smu              ; -- Begin function is_support_sw_smu
	.p2align	2
_is_support_sw_smu:                     ; @is_support_sw_smu
	.cfi_startproc
; %bb.0:
	ldr	x8, [x0]
Lloh0:
	adrp	x9, _CHIP_VEGA20@GOTPAGE
Lloh1:
	ldr	x9, [x9, _CHIP_VEGA20@GOTPAGEOFF]
Lloh2:
	adrp	x10, _amdgpu_dpm@GOTPAGE
Lloh3:
	ldr	x10, [x10, _amdgpu_dpm@GOTPAGEOFF]
Lloh4:
	ldr	x9, [x9]
Lloh5:
	ldr	w10, [x10]
	cmp	w10, #2
	cset	w10, eq
Lloh6:
	adrp	x11, _CHIP_ARCTURUS@GOTPAGE
Lloh7:
	ldr	x11, [x11, _CHIP_ARCTURUS@GOTPAGEOFF]
Lloh8:
	ldr	x11, [x11]
	cmp	x8, x11
	cset	w11, ge
	cmp	x8, x9
	csel	w0, w10, w11, eq
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_CHIP_VEGA20,8,3                ; @CHIP_VEGA20
	.comm	_amdgpu_dpm,4,2                 ; @amdgpu_dpm
	.comm	_CHIP_ARCTURUS,8,3              ; @CHIP_ARCTURUS
.subsections_via_symbols
