	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v7_0_constants_init
_gfx_v7_0_constants_init:               ## @gfx_v7_0_constants_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	_mmGRBM_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_GRBM_CNTL__READ_TIMEOUT__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$255, %esi
	shll	%cl, %esi
	callq	_WREG32
	movq	_mmGB_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	4(%r15), %esi
	callq	_WREG32
	movq	_mmHDP_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	4(%r15), %esi
	callq	_WREG32
	movq	_mmDMIF_ADDR_CALC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	4(%r15), %esi
	callq	_WREG32
	movq	%r15, %rdi
	callq	_gfx_v7_0_tiling_mode_table_init
	movq	%r15, %rdi
	callq	_gfx_v7_0_setup_rb
	movq	%r15, %rdi
	callq	_gfx_v7_0_get_cu_info
	movq	%r15, %rdi
	callq	_gfx_v7_0_config_init
	movq	_mmCP_MEQ_THRESHOLDS@GOTPCREL(%rip), %rax
	movq	_CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$48, %edx
	shll	%cl, %edx
	movl	(%rax), %edi
	movq	_CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$96, %esi
	shll	%cl, %esi
	orl	%edx, %esi
	callq	_WREG32
	movq	%r15, %rdi
	callq	_mutex_lock
	movq	%r15, %rdi
	movl	$-1, %esi
	movl	$-1, %edx
	movl	$-1, %ecx
	callq	_gfx_v7_0_select_se_sh
	movq	_SH_MEM_CONFIG@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	_ALIGNMENT_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_SH_MEM_ALIGNMENT_MODE_UNALIGNED@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	_REG_SET_FIELD
	movl	(%r14), %esi
	movq	_DEFAULT_MTYPE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_MTYPE_NC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%eax, %edi
	callq	_REG_SET_FIELD
	movl	(%r14), %esi
	movq	_APE1_MTYPE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_MTYPE_UC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%eax, %edi
	callq	_REG_SET_FIELD
	movl	(%r14), %esi
	movq	_PRIVATE_ATC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	%eax, %r13d
	movq	_SH_STATIC_MEM_CONFIG@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	_SWIZZLE_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%edi, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r14), %esi
	movq	_ELEMENT_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r14), %esi
	movq	_INDEX_STRIDE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$3, %ecx
	callq	_REG_SET_FIELD
	movq	_mmSH_STATIC_MEM_CONFIG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%eax, %esi
	callq	_WREG32
	leaq	24(%r15), %rdi
	movq	%rdi, -48(%rbp)                 ## 8-byte Spill
	callq	_mutex_lock
	movq	%r15, %r14
	movq	32(%r15), %rax
	cmpl	$0, (%rax)
	jle	LBB0_3
## %bb.1:
	movq	_mmSH_MEM_APE1_LIMIT@GOTPCREL(%rip), %r12
	movq	_mmSH_MEM_BASES@GOTPCREL(%rip), %r15
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	movl	%ebx, %r8d
	callq	_cik_srbm_select
	movq	_mmSH_MEM_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r13d, %esi
	callq	_WREG32
	movq	_mmSH_MEM_APE1_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_WREG32
	movl	(%r12), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r15), %edi
	xorl	%esi, %esi
	callq	_WREG32
	incl	%ebx
	movq	32(%r14), %rax
	cmpl	(%rax), %ebx
	jl	LBB0_2
LBB0_3:
	movq	%r14, %r15
	movq	%r14, %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	xorl	%r8d, %r8d
	callq	_cik_srbm_select
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_mutex_unlock
	movq	%r14, %rdi
	callq	_gfx_v7_0_init_compute_vmid
	movq	%r14, %rdi
	callq	_gfx_v7_0_init_gds_vmid
	movq	_mmSX_DEBUG_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$32, %esi
	callq	_WREG32
	movq	_mmTA_CNTL_AUX@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$65536, %esi                    ## imm = 0x10000
	callq	_WREG32
	movq	_mmSPI_CONFIG_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	orl	$50331648, %eax                 ## imm = 0x3000000
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmSQ_CONFIG@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movl	$1, %esi
	callq	_WREG32
	movq	_mmDB_DEBUG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmDB_DEBUG2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
                                        ## kill: def $eax killed $eax def $rax
	andl	$267386880, %eax                ## imm = 0xFF00000
	leal	1024(%rax), %esi
	movl	(%rbx), %edi
	callq	_WREG32
	movq	_mmDB_DEBUG3@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
                                        ## kill: def $eax killed $eax def $rax
	andl	$-131613, %eax                  ## imm = 0xFFFDFDE3
	leal	131584(%rax), %esi
	movl	(%rbx), %edi
	callq	_WREG32
	movq	_mmCB_HW_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	orl	$98824, %eax                    ## imm = 0x18208
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmSPI_CONFIG_CNTL_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$4, %esi
	shll	%cl, %esi
	callq	_WREG32
	movq	_PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	8(%r15), %eax
	movl	12(%r15), %edx
	shll	%cl, %eax
	movq	_PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	movl	16(%r15), %ebx
	movq	_PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %ebx
	movq	_mmPA_SC_FIFO_SIZE@GOTPCREL(%rip), %rdi
	movq	_PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	20(%r15), %esi
	shll	%cl, %esi
	movl	(%rdi), %edi
	orl	%eax, %edx
	orl	%ebx, %esi
	orl	%edx, %esi
	callq	_WREG32
	movq	_mmVGT_NUM_INSTANCES@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_WREG32
	movq	_mmCP_PERFMON_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r14), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$4095, %eax                     ## imm = 0xFFF
	shll	%cl, %eax
	movq	_mmPA_SC_FORCE_EOV_MAX_CNTS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movq	_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$255, %esi
	shll	%cl, %esi
	orl	%eax, %esi
	callq	_WREG32
	movq	_mmVGT_CACHE_INVALIDATION@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_VC_AND_TC@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	movq	_ES_AND_GS_AUTO@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %esi
	orl	%eax, %esi
	callq	_WREG32
	movq	_mmVGT_GS_VERTEX_REUSE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$16, %esi
	callq	_WREG32
	movq	_mmPA_SC_LINE_STIPPLE_STATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmPA_CL_ENHANCE@GOTPCREL(%rip), %rax
	movq	_PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$3, %esi
	shll	%cl, %esi
	movl	(%rax), %edi
	movq	_PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	callq	_WREG32
	movq	_mmPA_SC_ENHANCE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_WREG32
	movq	_mmSPI_ARB_PRIORITY@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32
	movq	_SPI_ARB_PRIORITY@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_PIPE_ORDER_TS0@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$2, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_PIPE_ORDER_TS1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$2, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_PIPE_ORDER_TS2@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$2, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_PIPE_ORDER_TS3@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$2, %ecx
	callq	_REG_SET_FIELD
	movl	(%r14), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	%r15, %rdi
	callq	_mutex_unlock
	movl	$50, %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_udelay                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_mmGRBM_CNTL,4,2                ## @mmGRBM_CNTL
	.comm	_GRBM_CNTL__READ_TIMEOUT__SHIFT,4,2 ## @GRBM_CNTL__READ_TIMEOUT__SHIFT
	.comm	_mmGB_ADDR_CONFIG,4,2           ## @mmGB_ADDR_CONFIG
	.comm	_mmHDP_ADDR_CONFIG,4,2          ## @mmHDP_ADDR_CONFIG
	.comm	_mmDMIF_ADDR_CALC,4,2           ## @mmDMIF_ADDR_CALC
	.comm	_mmCP_MEQ_THRESHOLDS,4,2        ## @mmCP_MEQ_THRESHOLDS
	.comm	_CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT,4,2 ## @CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT
	.comm	_CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT,4,2 ## @CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT
	.comm	_SH_MEM_CONFIG,4,2              ## @SH_MEM_CONFIG
	.comm	_ALIGNMENT_MODE,4,2             ## @ALIGNMENT_MODE
	.comm	_SH_MEM_ALIGNMENT_MODE_UNALIGNED,4,2 ## @SH_MEM_ALIGNMENT_MODE_UNALIGNED
	.comm	_DEFAULT_MTYPE,4,2              ## @DEFAULT_MTYPE
	.comm	_MTYPE_NC,4,2                   ## @MTYPE_NC
	.comm	_APE1_MTYPE,4,2                 ## @APE1_MTYPE
	.comm	_MTYPE_UC,4,2                   ## @MTYPE_UC
	.comm	_PRIVATE_ATC,4,2                ## @PRIVATE_ATC
	.comm	_SH_STATIC_MEM_CONFIG,4,2       ## @SH_STATIC_MEM_CONFIG
	.comm	_SWIZZLE_ENABLE,4,2             ## @SWIZZLE_ENABLE
	.comm	_ELEMENT_SIZE,4,2               ## @ELEMENT_SIZE
	.comm	_INDEX_STRIDE,4,2               ## @INDEX_STRIDE
	.comm	_mmSH_STATIC_MEM_CONFIG,4,2     ## @mmSH_STATIC_MEM_CONFIG
	.comm	_mmSH_MEM_CONFIG,4,2            ## @mmSH_MEM_CONFIG
	.comm	_mmSH_MEM_APE1_BASE,4,2         ## @mmSH_MEM_APE1_BASE
	.comm	_mmSH_MEM_APE1_LIMIT,4,2        ## @mmSH_MEM_APE1_LIMIT
	.comm	_mmSH_MEM_BASES,4,2             ## @mmSH_MEM_BASES
	.comm	_mmSX_DEBUG_1,4,2               ## @mmSX_DEBUG_1
	.comm	_mmTA_CNTL_AUX,4,2              ## @mmTA_CNTL_AUX
	.comm	_mmSPI_CONFIG_CNTL,4,2          ## @mmSPI_CONFIG_CNTL
	.comm	_mmSQ_CONFIG,4,2                ## @mmSQ_CONFIG
	.comm	_mmDB_DEBUG,4,2                 ## @mmDB_DEBUG
	.comm	_mmDB_DEBUG2,4,2                ## @mmDB_DEBUG2
	.comm	_mmDB_DEBUG3,4,2                ## @mmDB_DEBUG3
	.comm	_mmCB_HW_CONTROL,4,2            ## @mmCB_HW_CONTROL
	.comm	_mmSPI_CONFIG_CNTL_1,4,2        ## @mmSPI_CONFIG_CNTL_1
	.comm	_SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT,4,2 ## @SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT
	.comm	_mmPA_SC_FIFO_SIZE,4,2          ## @mmPA_SC_FIFO_SIZE
	.comm	_PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT,4,2 ## @PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT
	.comm	_PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT,4,2 ## @PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT
	.comm	_PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT,4,2 ## @PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT
	.comm	_PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT,4,2 ## @PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT
	.comm	_mmVGT_NUM_INSTANCES,4,2        ## @mmVGT_NUM_INSTANCES
	.comm	_mmCP_PERFMON_CNTL,4,2          ## @mmCP_PERFMON_CNTL
	.comm	_mmPA_SC_FORCE_EOV_MAX_CNTS,4,2 ## @mmPA_SC_FORCE_EOV_MAX_CNTS
	.comm	_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT,4,2 ## @PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT
	.comm	_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT,4,2 ## @PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT
	.comm	_mmVGT_CACHE_INVALIDATION,4,2   ## @mmVGT_CACHE_INVALIDATION
	.comm	_VC_AND_TC,4,2                  ## @VC_AND_TC
	.comm	_VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT,4,2 ## @VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT
	.comm	_ES_AND_GS_AUTO,4,2             ## @ES_AND_GS_AUTO
	.comm	_VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT,4,2 ## @VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT
	.comm	_mmVGT_GS_VERTEX_REUSE,4,2      ## @mmVGT_GS_VERTEX_REUSE
	.comm	_mmPA_SC_LINE_STIPPLE_STATE,4,2 ## @mmPA_SC_LINE_STIPPLE_STATE
	.comm	_mmPA_CL_ENHANCE,4,2            ## @mmPA_CL_ENHANCE
	.comm	_PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK,4,2 ## @PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK
	.comm	_PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT,4,2 ## @PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT
	.comm	_mmPA_SC_ENHANCE,4,2            ## @mmPA_SC_ENHANCE
	.comm	_PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK,4,2 ## @PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK
	.comm	_mmSPI_ARB_PRIORITY,4,2         ## @mmSPI_ARB_PRIORITY
	.comm	_SPI_ARB_PRIORITY,4,2           ## @SPI_ARB_PRIORITY
	.comm	_PIPE_ORDER_TS0,4,2             ## @PIPE_ORDER_TS0
	.comm	_PIPE_ORDER_TS1,4,2             ## @PIPE_ORDER_TS1
	.comm	_PIPE_ORDER_TS2,4,2             ## @PIPE_ORDER_TS2
	.comm	_PIPE_ORDER_TS3,4,2             ## @PIPE_ORDER_TS3
	.no_dead_strip	_gfx_v7_0_constants_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v7_0_constants_init
_gfx_v7_0_constants_init:               ; @gfx_v7_0_constants_init
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
Lloh0:
	adrp	x8, _mmGRBM_CNTL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _mmGRBM_CNTL@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
Lloh3:
	adrp	x8, _GRBM_CNTL__READ_TIMEOUT__SHIFT@GOTPAGE
Lloh4:
	ldr	x8, [x8, _GRBM_CNTL__READ_TIMEOUT__SHIFT@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	mov	w23, #255
	lsl	w1, w23, w8
	bl	_WREG32
Lloh6:
	adrp	x8, _mmGB_ADDR_CONFIG@GOTPAGE
Lloh7:
	ldr	x8, [x8, _mmGB_ADDR_CONFIG@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	ldr	w1, [x19, #4]
	bl	_WREG32
Lloh9:
	adrp	x8, _mmHDP_ADDR_CONFIG@GOTPAGE
Lloh10:
	ldr	x8, [x8, _mmHDP_ADDR_CONFIG@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	ldr	w1, [x19, #4]
	bl	_WREG32
Lloh12:
	adrp	x8, _mmDMIF_ADDR_CALC@GOTPAGE
Lloh13:
	ldr	x8, [x8, _mmDMIF_ADDR_CALC@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	ldr	w1, [x19, #4]
	bl	_WREG32
	mov	x0, x19
	bl	_gfx_v7_0_tiling_mode_table_init
	mov	x0, x19
	bl	_gfx_v7_0_setup_rb
	mov	x0, x19
	bl	_gfx_v7_0_get_cu_info
	mov	x0, x19
	bl	_gfx_v7_0_config_init
Lloh15:
	adrp	x8, _mmCP_MEQ_THRESHOLDS@GOTPAGE
Lloh16:
	ldr	x8, [x8, _mmCP_MEQ_THRESHOLDS@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
Lloh18:
	adrp	x8, _CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT@GOTPAGE
Lloh19:
	ldr	x8, [x8, _CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	mov	w9, #48
	lsl	w8, w9, w8
Lloh21:
	adrp	x9, _CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT@GOTPAGE
Lloh22:
	ldr	x9, [x9, _CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	mov	w10, #96
	lsl	w9, w10, w9
	orr	w1, w9, w8
	bl	_WREG32
	mov	x0, x19
	bl	_mutex_lock
	mov	x0, x19
	mov	w1, #-1
	mov	w2, #-1
	mov	w3, #-1
	bl	_gfx_v7_0_select_se_sh
Lloh24:
	adrp	x20, _SH_MEM_CONFIG@GOTPAGE
Lloh25:
	ldr	x20, [x20, _SH_MEM_CONFIG@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh26:
	adrp	x8, _ALIGNMENT_MODE@GOTPAGE
Lloh27:
	ldr	x8, [x8, _ALIGNMENT_MODE@GOTPAGEOFF]
Lloh28:
	ldr	w2, [x8]
Lloh29:
	adrp	x8, _SH_MEM_ALIGNMENT_MODE_UNALIGNED@GOTPAGE
Lloh30:
	ldr	x8, [x8, _SH_MEM_ALIGNMENT_MODE_UNALIGNED@GOTPAGEOFF]
Lloh31:
	ldr	w3, [x8]
	mov	w0, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x20]
Lloh32:
	adrp	x8, _DEFAULT_MTYPE@GOTPAGE
Lloh33:
	ldr	x8, [x8, _DEFAULT_MTYPE@GOTPAGEOFF]
Lloh34:
	ldr	w2, [x8]
Lloh35:
	adrp	x8, _MTYPE_NC@GOTPAGE
Lloh36:
	ldr	x8, [x8, _MTYPE_NC@GOTPAGEOFF]
Lloh37:
	ldr	w3, [x8]
	bl	_REG_SET_FIELD
	ldr	w1, [x20]
Lloh38:
	adrp	x8, _APE1_MTYPE@GOTPAGE
Lloh39:
	ldr	x8, [x8, _APE1_MTYPE@GOTPAGEOFF]
Lloh40:
	ldr	w2, [x8]
Lloh41:
	adrp	x8, _MTYPE_UC@GOTPAGE
Lloh42:
	ldr	x8, [x8, _MTYPE_UC@GOTPAGEOFF]
Lloh43:
	ldr	w3, [x8]
	bl	_REG_SET_FIELD
	ldr	w1, [x20]
Lloh44:
	adrp	x8, _PRIVATE_ATC@GOTPAGE
Lloh45:
	ldr	x8, [x8, _PRIVATE_ATC@GOTPAGEOFF]
Lloh46:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	mov	x20, x0
Lloh47:
	adrp	x21, _SH_STATIC_MEM_CONFIG@GOTPAGE
Lloh48:
	ldr	x21, [x21, _SH_STATIC_MEM_CONFIG@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh49:
	adrp	x8, _SWIZZLE_ENABLE@GOTPAGE
Lloh50:
	ldr	x8, [x8, _SWIZZLE_ENABLE@GOTPAGEOFF]
Lloh51:
	ldr	w2, [x8]
	mov	w0, #0
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x21]
Lloh52:
	adrp	x8, _ELEMENT_SIZE@GOTPAGE
Lloh53:
	ldr	x8, [x8, _ELEMENT_SIZE@GOTPAGEOFF]
Lloh54:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x21]
Lloh55:
	adrp	x8, _INDEX_STRIDE@GOTPAGE
Lloh56:
	ldr	x8, [x8, _INDEX_STRIDE@GOTPAGEOFF]
Lloh57:
	ldr	w2, [x8]
	mov	w24, #3
	mov	w3, #3
	bl	_REG_SET_FIELD
	mov	x1, x0
Lloh58:
	adrp	x8, _mmSH_STATIC_MEM_CONFIG@GOTPAGE
Lloh59:
	ldr	x8, [x8, _mmSH_STATIC_MEM_CONFIG@GOTPAGEOFF]
Lloh60:
	ldr	w0, [x8]
	bl	_WREG32
	add	x21, x19, #24
	mov	x0, x21
	bl	_mutex_lock
	ldr	x8, [x19, #32]
	ldr	w8, [x8]
	cmp	w8, #1
	b.lt	LBB0_3
; %bb.1:
	mov	w22, #0
Lloh61:
	adrp	x25, _mmSH_MEM_CONFIG@GOTPAGE
Lloh62:
	ldr	x25, [x25, _mmSH_MEM_CONFIG@GOTPAGEOFF]
Lloh63:
	adrp	x26, _mmSH_MEM_APE1_BASE@GOTPAGE
Lloh64:
	ldr	x26, [x26, _mmSH_MEM_APE1_BASE@GOTPAGEOFF]
Lloh65:
	adrp	x27, _mmSH_MEM_APE1_LIMIT@GOTPAGE
Lloh66:
	ldr	x27, [x27, _mmSH_MEM_APE1_LIMIT@GOTPAGEOFF]
Lloh67:
	adrp	x28, _mmSH_MEM_BASES@GOTPAGE
Lloh68:
	ldr	x28, [x28, _mmSH_MEM_BASES@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x19
	mov	w1, #0
	mov	w2, #0
	mov	w3, #0
	mov	x4, x22
	bl	_cik_srbm_select
	ldr	w0, [x25]
	mov	x1, x20
	bl	_WREG32
	ldr	w0, [x26]
	mov	w1, #1
	bl	_WREG32
	ldr	w0, [x27]
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x28]
	mov	w1, #0
	bl	_WREG32
	add	w22, w22, #1
	ldr	x8, [x19, #32]
	ldr	w8, [x8]
	cmp	w22, w8
	b.lt	LBB0_2
LBB0_3:
	mov	x0, x19
	mov	w1, #0
	mov	w2, #0
	mov	w3, #0
	mov	w4, #0
	bl	_cik_srbm_select
	mov	x0, x21
	bl	_mutex_unlock
	mov	x0, x19
	bl	_gfx_v7_0_init_compute_vmid
	mov	x0, x19
	bl	_gfx_v7_0_init_gds_vmid
Lloh69:
	adrp	x8, _mmSX_DEBUG_1@GOTPAGE
Lloh70:
	ldr	x8, [x8, _mmSX_DEBUG_1@GOTPAGEOFF]
Lloh71:
	ldr	w0, [x8]
	mov	w1, #32
	bl	_WREG32
Lloh72:
	adrp	x8, _mmTA_CNTL_AUX@GOTPAGE
Lloh73:
	ldr	x8, [x8, _mmTA_CNTL_AUX@GOTPAGEOFF]
Lloh74:
	ldr	w0, [x8]
	mov	w1, #65536
	bl	_WREG32
Lloh75:
	adrp	x20, _mmSPI_CONFIG_CNTL@GOTPAGE
Lloh76:
	ldr	x20, [x20, _mmSPI_CONFIG_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	orr	w1, w0, #0x3000000
	ldr	w0, [x20]
	bl	_WREG32
Lloh77:
	adrp	x20, _mmSQ_CONFIG@GOTPAGE
Lloh78:
	ldr	x20, [x20, _mmSQ_CONFIG@GOTPAGEOFF]
	ldr	w0, [x20]
	mov	w1, #1
	bl	_WREG32
Lloh79:
	adrp	x8, _mmDB_DEBUG@GOTPAGE
Lloh80:
	ldr	x8, [x8, _mmDB_DEBUG@GOTPAGEOFF]
Lloh81:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh82:
	adrp	x21, _mmDB_DEBUG2@GOTPAGE
Lloh83:
	ldr	x21, [x21, _mmDB_DEBUG2@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
	and	w8, w0, #0xff00000
	orr	w1, w8, #0x400
	ldr	w0, [x21]
	bl	_WREG32
Lloh84:
	adrp	x21, _mmDB_DEBUG3@GOTPAGE
Lloh85:
	ldr	x21, [x21, _mmDB_DEBUG3@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
	and	w8, w0, #0xffffffe3
	mov	w9, #512
	movk	w9, #2, lsl #16
	orr	w1, w8, w9
	ldr	w0, [x21]
	bl	_WREG32
Lloh86:
	adrp	x21, _mmCB_HW_CONTROL@GOTPAGE
Lloh87:
	ldr	x21, [x21, _mmCB_HW_CONTROL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
	mov	w8, #33288
	movk	w8, #1, lsl #16
	orr	w1, w0, w8
	ldr	w0, [x21]
	bl	_WREG32
Lloh88:
	adrp	x8, _mmSPI_CONFIG_CNTL_1@GOTPAGE
Lloh89:
	ldr	x8, [x8, _mmSPI_CONFIG_CNTL_1@GOTPAGEOFF]
Lloh90:
	ldr	w0, [x8]
Lloh91:
	adrp	x8, _SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT@GOTPAGE
Lloh92:
	ldr	x8, [x8, _SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT@GOTPAGEOFF]
Lloh93:
	ldr	w8, [x8]
	mov	w9, #4
	lsl	w1, w9, w8
	bl	_WREG32
Lloh94:
	adrp	x8, _PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT@GOTPAGE
Lloh95:
	ldr	x8, [x8, _PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT@GOTPAGEOFF]
Lloh96:
	ldr	w8, [x8]
	ldp	w9, w10, [x19, #8]
	lsl	w8, w9, w8
Lloh97:
	adrp	x9, _PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT@GOTPAGE
Lloh98:
	ldr	x9, [x9, _PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT@GOTPAGEOFF]
Lloh99:
	ldr	w9, [x9]
	lsl	w9, w10, w9
	orr	w8, w9, w8
Lloh100:
	adrp	x9, _PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT@GOTPAGE
Lloh101:
	ldr	x9, [x9, _PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT@GOTPAGEOFF]
Lloh102:
	ldr	w9, [x9]
	ldp	w10, w11, [x19, #16]
	lsl	w9, w10, w9
Lloh103:
	adrp	x10, _mmPA_SC_FIFO_SIZE@GOTPAGE
Lloh104:
	ldr	x10, [x10, _mmPA_SC_FIFO_SIZE@GOTPAGEOFF]
Lloh105:
	ldr	w0, [x10]
	orr	w8, w8, w9
Lloh106:
	adrp	x9, _PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT@GOTPAGE
Lloh107:
	ldr	x9, [x9, _PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT@GOTPAGEOFF]
Lloh108:
	ldr	w9, [x9]
	lsl	w9, w11, w9
	orr	w1, w8, w9
	bl	_WREG32
Lloh109:
	adrp	x8, _mmVGT_NUM_INSTANCES@GOTPAGE
Lloh110:
	ldr	x8, [x8, _mmVGT_NUM_INSTANCES@GOTPAGEOFF]
Lloh111:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_WREG32
Lloh112:
	adrp	x8, _mmCP_PERFMON_CNTL@GOTPAGE
Lloh113:
	ldr	x8, [x8, _mmCP_PERFMON_CNTL@GOTPAGEOFF]
Lloh114:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x20]
	mov	w1, #0
	bl	_WREG32
Lloh115:
	adrp	x8, _mmPA_SC_FORCE_EOV_MAX_CNTS@GOTPAGE
Lloh116:
	ldr	x8, [x8, _mmPA_SC_FORCE_EOV_MAX_CNTS@GOTPAGEOFF]
Lloh117:
	ldr	w0, [x8]
Lloh118:
	adrp	x8, _PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT@GOTPAGE
Lloh119:
	ldr	x8, [x8, _PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT@GOTPAGEOFF]
Lloh120:
	ldr	w8, [x8]
	mov	w9, #4095
	lsl	w8, w9, w8
Lloh121:
	adrp	x9, _PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT@GOTPAGE
Lloh122:
	ldr	x9, [x9, _PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT@GOTPAGEOFF]
Lloh123:
	ldr	w9, [x9]
	lsl	w9, w23, w9
	orr	w1, w9, w8
	bl	_WREG32
Lloh124:
	adrp	x8, _mmVGT_CACHE_INVALIDATION@GOTPAGE
Lloh125:
	ldr	x8, [x8, _mmVGT_CACHE_INVALIDATION@GOTPAGEOFF]
Lloh126:
	ldr	w0, [x8]
Lloh127:
	adrp	x8, _VC_AND_TC@GOTPAGE
Lloh128:
	ldr	x8, [x8, _VC_AND_TC@GOTPAGEOFF]
Lloh129:
	ldr	w8, [x8]
Lloh130:
	adrp	x9, _VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT@GOTPAGE
Lloh131:
	ldr	x9, [x9, _VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT@GOTPAGEOFF]
Lloh132:
	ldr	w9, [x9]
	lsl	w8, w8, w9
Lloh133:
	adrp	x9, _ES_AND_GS_AUTO@GOTPAGE
Lloh134:
	ldr	x9, [x9, _ES_AND_GS_AUTO@GOTPAGEOFF]
Lloh135:
	ldr	w9, [x9]
Lloh136:
	adrp	x10, _VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT@GOTPAGE
Lloh137:
	ldr	x10, [x10, _VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT@GOTPAGEOFF]
Lloh138:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w1, w9, w8
	bl	_WREG32
Lloh139:
	adrp	x8, _mmVGT_GS_VERTEX_REUSE@GOTPAGE
Lloh140:
	ldr	x8, [x8, _mmVGT_GS_VERTEX_REUSE@GOTPAGEOFF]
Lloh141:
	ldr	w0, [x8]
	mov	w1, #16
	bl	_WREG32
Lloh142:
	adrp	x8, _mmPA_SC_LINE_STIPPLE_STATE@GOTPAGE
Lloh143:
	ldr	x8, [x8, _mmPA_SC_LINE_STIPPLE_STATE@GOTPAGEOFF]
Lloh144:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh145:
	adrp	x8, _mmPA_CL_ENHANCE@GOTPAGE
Lloh146:
	ldr	x8, [x8, _mmPA_CL_ENHANCE@GOTPAGEOFF]
Lloh147:
	ldr	w0, [x8]
Lloh148:
	adrp	x8, _PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK@GOTPAGE
Lloh149:
	ldr	x8, [x8, _PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK@GOTPAGEOFF]
Lloh150:
	ldr	w8, [x8]
Lloh151:
	adrp	x9, _PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT@GOTPAGE
Lloh152:
	ldr	x9, [x9, _PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT@GOTPAGEOFF]
Lloh153:
	ldr	w9, [x9]
	lsl	w9, w24, w9
	orr	w1, w9, w8
	bl	_WREG32
Lloh154:
	adrp	x8, _mmPA_SC_ENHANCE@GOTPAGE
Lloh155:
	ldr	x8, [x8, _mmPA_SC_ENHANCE@GOTPAGEOFF]
Lloh156:
	ldr	w0, [x8]
Lloh157:
	adrp	x8, _PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK@GOTPAGE
Lloh158:
	ldr	x8, [x8, _PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK@GOTPAGEOFF]
Lloh159:
	ldr	w1, [x8]
	bl	_WREG32
Lloh160:
	adrp	x20, _mmSPI_ARB_PRIORITY@GOTPAGE
Lloh161:
	ldr	x20, [x20, _mmSPI_ARB_PRIORITY@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh162:
	adrp	x21, _SPI_ARB_PRIORITY@GOTPAGE
Lloh163:
	ldr	x21, [x21, _SPI_ARB_PRIORITY@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh164:
	adrp	x8, _PIPE_ORDER_TS0@GOTPAGE
Lloh165:
	ldr	x8, [x8, _PIPE_ORDER_TS0@GOTPAGEOFF]
Lloh166:
	ldr	w2, [x8]
	mov	w3, #2
	bl	_REG_SET_FIELD
	ldr	w1, [x21]
Lloh167:
	adrp	x8, _PIPE_ORDER_TS1@GOTPAGE
Lloh168:
	ldr	x8, [x8, _PIPE_ORDER_TS1@GOTPAGEOFF]
Lloh169:
	ldr	w2, [x8]
	mov	w3, #2
	bl	_REG_SET_FIELD
	ldr	w1, [x21]
Lloh170:
	adrp	x8, _PIPE_ORDER_TS2@GOTPAGE
Lloh171:
	ldr	x8, [x8, _PIPE_ORDER_TS2@GOTPAGEOFF]
Lloh172:
	ldr	w2, [x8]
	mov	w3, #2
	bl	_REG_SET_FIELD
	ldr	w1, [x21]
Lloh173:
	adrp	x8, _PIPE_ORDER_TS3@GOTPAGE
Lloh174:
	ldr	x8, [x8, _PIPE_ORDER_TS3@GOTPAGEOFF]
Lloh175:
	ldr	w2, [x8]
	mov	w3, #2
	bl	_REG_SET_FIELD
	mov	x1, x0
	ldr	w0, [x20]
	bl	_WREG32
	mov	x0, x19
	bl	_mutex_unlock
	mov	w0, #50
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_udelay
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh67, Lloh68
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGot	Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh173, Lloh174, Lloh175
	.loh AdrpLdrGotLdr	Lloh170, Lloh171, Lloh172
	.loh AdrpLdrGotLdr	Lloh167, Lloh168, Lloh169
	.loh AdrpLdrGotLdr	Lloh164, Lloh165, Lloh166
	.loh AdrpLdrGot	Lloh162, Lloh163
	.loh AdrpLdrGot	Lloh160, Lloh161
	.loh AdrpLdrGotLdr	Lloh157, Lloh158, Lloh159
	.loh AdrpLdrGotLdr	Lloh154, Lloh155, Lloh156
	.loh AdrpLdrGotLdr	Lloh151, Lloh152, Lloh153
	.loh AdrpLdrGotLdr	Lloh148, Lloh149, Lloh150
	.loh AdrpLdrGotLdr	Lloh145, Lloh146, Lloh147
	.loh AdrpLdrGotLdr	Lloh142, Lloh143, Lloh144
	.loh AdrpLdrGotLdr	Lloh139, Lloh140, Lloh141
	.loh AdrpLdrGotLdr	Lloh136, Lloh137, Lloh138
	.loh AdrpLdrGotLdr	Lloh133, Lloh134, Lloh135
	.loh AdrpLdrGotLdr	Lloh130, Lloh131, Lloh132
	.loh AdrpLdrGotLdr	Lloh127, Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.loh AdrpLdrGotLdr	Lloh112, Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGot	Lloh86, Lloh87
	.loh AdrpLdrGot	Lloh84, Lloh85
	.loh AdrpLdrGot	Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGot	Lloh77, Lloh78
	.loh AdrpLdrGot	Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.cfi_endproc
                                        ; -- End function
	.comm	_mmGRBM_CNTL,4,2                ; @mmGRBM_CNTL
	.comm	_GRBM_CNTL__READ_TIMEOUT__SHIFT,4,2 ; @GRBM_CNTL__READ_TIMEOUT__SHIFT
	.comm	_mmGB_ADDR_CONFIG,4,2           ; @mmGB_ADDR_CONFIG
	.comm	_mmHDP_ADDR_CONFIG,4,2          ; @mmHDP_ADDR_CONFIG
	.comm	_mmDMIF_ADDR_CALC,4,2           ; @mmDMIF_ADDR_CALC
	.comm	_mmCP_MEQ_THRESHOLDS,4,2        ; @mmCP_MEQ_THRESHOLDS
	.comm	_CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT,4,2 ; @CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT
	.comm	_CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT,4,2 ; @CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT
	.comm	_SH_MEM_CONFIG,4,2              ; @SH_MEM_CONFIG
	.comm	_ALIGNMENT_MODE,4,2             ; @ALIGNMENT_MODE
	.comm	_SH_MEM_ALIGNMENT_MODE_UNALIGNED,4,2 ; @SH_MEM_ALIGNMENT_MODE_UNALIGNED
	.comm	_DEFAULT_MTYPE,4,2              ; @DEFAULT_MTYPE
	.comm	_MTYPE_NC,4,2                   ; @MTYPE_NC
	.comm	_APE1_MTYPE,4,2                 ; @APE1_MTYPE
	.comm	_MTYPE_UC,4,2                   ; @MTYPE_UC
	.comm	_PRIVATE_ATC,4,2                ; @PRIVATE_ATC
	.comm	_SH_STATIC_MEM_CONFIG,4,2       ; @SH_STATIC_MEM_CONFIG
	.comm	_SWIZZLE_ENABLE,4,2             ; @SWIZZLE_ENABLE
	.comm	_ELEMENT_SIZE,4,2               ; @ELEMENT_SIZE
	.comm	_INDEX_STRIDE,4,2               ; @INDEX_STRIDE
	.comm	_mmSH_STATIC_MEM_CONFIG,4,2     ; @mmSH_STATIC_MEM_CONFIG
	.comm	_mmSH_MEM_CONFIG,4,2            ; @mmSH_MEM_CONFIG
	.comm	_mmSH_MEM_APE1_BASE,4,2         ; @mmSH_MEM_APE1_BASE
	.comm	_mmSH_MEM_APE1_LIMIT,4,2        ; @mmSH_MEM_APE1_LIMIT
	.comm	_mmSH_MEM_BASES,4,2             ; @mmSH_MEM_BASES
	.comm	_mmSX_DEBUG_1,4,2               ; @mmSX_DEBUG_1
	.comm	_mmTA_CNTL_AUX,4,2              ; @mmTA_CNTL_AUX
	.comm	_mmSPI_CONFIG_CNTL,4,2          ; @mmSPI_CONFIG_CNTL
	.comm	_mmSQ_CONFIG,4,2                ; @mmSQ_CONFIG
	.comm	_mmDB_DEBUG,4,2                 ; @mmDB_DEBUG
	.comm	_mmDB_DEBUG2,4,2                ; @mmDB_DEBUG2
	.comm	_mmDB_DEBUG3,4,2                ; @mmDB_DEBUG3
	.comm	_mmCB_HW_CONTROL,4,2            ; @mmCB_HW_CONTROL
	.comm	_mmSPI_CONFIG_CNTL_1,4,2        ; @mmSPI_CONFIG_CNTL_1
	.comm	_SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT,4,2 ; @SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT
	.comm	_mmPA_SC_FIFO_SIZE,4,2          ; @mmPA_SC_FIFO_SIZE
	.comm	_PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT,4,2 ; @PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT
	.comm	_PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT,4,2 ; @PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT
	.comm	_PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT,4,2 ; @PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT
	.comm	_PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT,4,2 ; @PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT
	.comm	_mmVGT_NUM_INSTANCES,4,2        ; @mmVGT_NUM_INSTANCES
	.comm	_mmCP_PERFMON_CNTL,4,2          ; @mmCP_PERFMON_CNTL
	.comm	_mmPA_SC_FORCE_EOV_MAX_CNTS,4,2 ; @mmPA_SC_FORCE_EOV_MAX_CNTS
	.comm	_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT,4,2 ; @PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT
	.comm	_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT,4,2 ; @PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT
	.comm	_mmVGT_CACHE_INVALIDATION,4,2   ; @mmVGT_CACHE_INVALIDATION
	.comm	_VC_AND_TC,4,2                  ; @VC_AND_TC
	.comm	_VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT,4,2 ; @VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT
	.comm	_ES_AND_GS_AUTO,4,2             ; @ES_AND_GS_AUTO
	.comm	_VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT,4,2 ; @VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT
	.comm	_mmVGT_GS_VERTEX_REUSE,4,2      ; @mmVGT_GS_VERTEX_REUSE
	.comm	_mmPA_SC_LINE_STIPPLE_STATE,4,2 ; @mmPA_SC_LINE_STIPPLE_STATE
	.comm	_mmPA_CL_ENHANCE,4,2            ; @mmPA_CL_ENHANCE
	.comm	_PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK,4,2 ; @PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK
	.comm	_PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT,4,2 ; @PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT
	.comm	_mmPA_SC_ENHANCE,4,2            ; @mmPA_SC_ENHANCE
	.comm	_PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK,4,2 ; @PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK
	.comm	_mmSPI_ARB_PRIORITY,4,2         ; @mmSPI_ARB_PRIORITY
	.comm	_SPI_ARB_PRIORITY,4,2           ; @SPI_ARB_PRIORITY
	.comm	_PIPE_ORDER_TS0,4,2             ; @PIPE_ORDER_TS0
	.comm	_PIPE_ORDER_TS1,4,2             ; @PIPE_ORDER_TS1
	.comm	_PIPE_ORDER_TS2,4,2             ; @PIPE_ORDER_TS2
	.comm	_PIPE_ORDER_TS3,4,2             ; @PIPE_ORDER_TS3
	.no_dead_strip	_gfx_v7_0_constants_init
.subsections_via_symbols
