	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function amdgpu_set_pp_dpm_pcie
_amdgpu_set_pp_dpm_pcie:                ## @amdgpu_set_pp_dpm_pcie
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rcx, %r14
	movq	%rdx, %rbx
	callq	_dev_get_drvdata
	movq	(%rax), %r15
	movl	$0, -28(%rbp)
	leaq	-28(%rbp), %rdx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	_amdgpu_read_mask
	testl	%eax, %eax
	jne	LBB0_8
## %bb.1:
	movq	%r15, %rdi
	callq	_is_support_sw_smu
	testq	%rax, %rax
	je	LBB0_3
## %bb.2:
	addq	$8, %r15
	movq	_SMU_PCIE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-28(%rbp), %edx
	movq	%r15, %rdi
	callq	_smu_force_clk_levels
	testl	%eax, %eax
	jne	LBB0_6
	jmp	LBB0_7
LBB0_3:
	movq	(%r15), %rax
	cmpq	$0, (%rax)
	je	LBB0_7
## %bb.4:
	movq	_PP_PCIE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-28(%rbp), %edx
	movq	%r15, %rdi
	callq	_amdgpu_dpm_force_clock_level
	testl	%eax, %eax
	je	LBB0_7
LBB0_6:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_8
LBB0_7:
	movl	%r14d, %eax
LBB0_8:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_SMU_PCIE,4,2                   ## @SMU_PCIE
	.comm	_PP_PCIE,4,2                    ## @PP_PCIE
	.comm	_EINVAL,4,2                     ## @EINVAL
	.no_dead_strip	_amdgpu_set_pp_dpm_pcie
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function amdgpu_set_pp_dpm_pcie
_amdgpu_set_pp_dpm_pcie:                ; @amdgpu_set_pp_dpm_pcie
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x3
	mov	x21, x2
	bl	_dev_get_drvdata
	ldr	x20, [x0]
	str	wzr, [sp, #12]
	add	x2, sp, #12
	mov	x0, x21
	mov	x1, x19
	bl	_amdgpu_read_mask
	cbnz	w0, LBB0_7
; %bb.1:
	mov	x0, x20
	bl	_is_support_sw_smu
	cbz	x0, LBB0_3
; %bb.2:
	add	x0, x20, #8
Lloh0:
	adrp	x8, _SMU_PCIE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _SMU_PCIE@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	ldr	w2, [sp, #12]
	bl	_smu_force_clk_levels
	cbnz	w0, LBB0_5
	b	LBB0_6
LBB0_3:
	ldr	x8, [x20]
	ldr	x8, [x8]
	cbz	x8, LBB0_6
; %bb.4:
Lloh3:
	adrp	x8, _PP_PCIE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PP_PCIE@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	ldr	w2, [sp, #12]
	mov	x0, x20
	bl	_amdgpu_dpm_force_clock_level
	cbz	w0, LBB0_6
LBB0_5:
Lloh6:
	adrp	x8, _EINVAL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_7
LBB0_6:
	mov	x0, x19
LBB0_7:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_SMU_PCIE,4,2                   ; @SMU_PCIE
	.comm	_PP_PCIE,4,2                    ; @PP_PCIE
	.comm	_EINVAL,4,2                     ; @EINVAL
	.no_dead_strip	_amdgpu_set_pp_dpm_pcie
.subsections_via_symbols
