	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_gen11_disable_guc_interrupts   ## -- Begin function gen11_disable_guc_interrupts
	.p2align	4, 0x90
_gen11_disable_guc_interrupts:          ## @gen11_disable_guc_interrupts
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	callq	_guc_to_gt
	movq	%rax, %rbx
	leaq	4(%rax), %r15
	movq	%r15, %rdi
	callq	_spin_lock_irq
	movl	$0, (%r14)
	movl	8(%rbx), %edi
	movq	_GEN11_GUC_SG_INTR_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$-1, %edx
	callq	_intel_uncore_write
	movl	8(%rbx), %edi
	movq	_GEN11_GUC_SG_INTR_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_intel_uncore_write
	movq	%r15, %rdi
	callq	_spin_unlock_irq
	movl	(%rbx), %edi
	callq	_intel_synchronize_irq
	movq	%r14, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_gen11_reset_guc_interrupts     ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_GEN11_GUC_SG_INTR_MASK,4,2     ## @GEN11_GUC_SG_INTR_MASK
	.comm	_GEN11_GUC_SG_INTR_ENABLE,4,2   ## @GEN11_GUC_SG_INTR_ENABLE
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_gen11_disable_guc_interrupts   ; -- Begin function gen11_disable_guc_interrupts
	.p2align	2
_gen11_disable_guc_interrupts:          ; @gen11_disable_guc_interrupts
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	bl	_guc_to_gt
	mov	x20, x0
	add	x21, x0, #4
	mov	x0, x21
	bl	_spin_lock_irq
	str	wzr, [x19]
	ldr	w0, [x20, #8]
Lloh0:
	adrp	x8, _GEN11_GUC_SG_INTR_MASK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _GEN11_GUC_SG_INTR_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	w2, #-1
	bl	_intel_uncore_write
	ldr	w0, [x20, #8]
Lloh3:
	adrp	x8, _GEN11_GUC_SG_INTR_ENABLE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _GEN11_GUC_SG_INTR_ENABLE@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_intel_uncore_write
	mov	x0, x21
	bl	_spin_unlock_irq
	ldr	w0, [x20]
	bl	_intel_synchronize_irq
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_gen11_reset_guc_interrupts
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_GEN11_GUC_SG_INTR_MASK,4,2     ; @GEN11_GUC_SG_INTR_MASK
	.comm	_GEN11_GUC_SG_INTR_ENABLE,4,2   ; @GEN11_GUC_SG_INTR_ENABLE
.subsections_via_symbols
