	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_dce120_timing_generator_tear_down_global_swap_lock ## -- Begin function dce120_timing_generator_tear_down_global_swap_lock
	.p2align	4, 0x90
_dce120_timing_generator_tear_down_global_swap_lock: ## @dce120_timing_generator_tear_down_global_swap_lock
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	callq	_DCE110TG_FROM_TG
	movq	_DCP0_DCP_GSL_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_FD
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	_DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_FD
	movl	%eax, %r13d
	movq	_DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_FD
                                        ## kill: def $eax killed $eax def $rax
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
	movq	_HFLIP_READY_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_FD
	movl	%eax, %ebx
	movq	_HFLIP_CHECK_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	_DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_FD
	movl	%eax, %r14d
	movq	_DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_FD
                                        ## kill: def $eax killed $eax def $rax
	movl	-48(%rbp), %edi                 ## 4-byte Reload
	movl	$6, %esi
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	xorl	%ecx, %ecx
	movl	%r13d, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	pushq	%rax
	pushq	$0
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	pushq	%r15
	pushq	-56(%rbp)                       ## 8-byte Folded Reload
	callq	_CRTC_REG_SET_N
	addq	$64, %rsp
	movq	_CRTC0_CRTC_GSL_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_CRTC_GSL_CHECK_LINE_NUM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_CRTC_GSL_FORCE_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%edx, %edx
	movl	$2, %r8d
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_CRTC_REG_SET_2                 ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_DCP0_DCP_GSL_CONTROL,4,2       ## @DCP0_DCP_GSL_CONTROL
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN,4,2 ## @DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN,4,2 ## @DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY,4,2 ## @DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY
	.comm	_HFLIP_READY_DELAY,4,2          ## @HFLIP_READY_DELAY
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY,4,2 ## @DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY
	.comm	_HFLIP_CHECK_DELAY,4,2          ## @HFLIP_CHECK_DELAY
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE,4,2 ## @DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING,4,2 ## @DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING
	.comm	_CRTC0_CRTC_GSL_CONTROL,4,2     ## @CRTC0_CRTC_GSL_CONTROL
	.comm	_CRTC_GSL_CHECK_LINE_NUM,4,2    ## @CRTC_GSL_CHECK_LINE_NUM
	.comm	_CRTC_GSL_FORCE_DELAY,4,2       ## @CRTC_GSL_FORCE_DELAY
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_dce120_timing_generator_tear_down_global_swap_lock ; -- Begin function dce120_timing_generator_tear_down_global_swap_lock
	.p2align	2
_dce120_timing_generator_tear_down_global_swap_lock: ; @dce120_timing_generator_tear_down_global_swap_lock
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	bl	_DCE110TG_FROM_TG
Lloh0:
	adrp	x8, _DCP0_DCP_GSL_CONTROL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DCP0_DCP_GSL_CONTROL@GOTPAGEOFF]
Lloh2:
	ldr	w19, [x8]
Lloh3:
	adrp	x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN@GOTPAGE
Lloh4:
	ldr	x8, [x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	bl	_FD
	mov	x20, x0
Lloh6:
	adrp	x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN@GOTPAGE
Lloh7:
	ldr	x8, [x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	bl	_FD
	mov	x21, x0
Lloh9:
	adrp	x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY@GOTPAGE
Lloh10:
	ldr	x8, [x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	bl	_FD
	mov	x22, x0
Lloh12:
	adrp	x8, _HFLIP_READY_DELAY@GOTPAGE
Lloh13:
	ldr	x8, [x8, _HFLIP_READY_DELAY@GOTPAGEOFF]
Lloh14:
	ldr	w23, [x8]
Lloh15:
	adrp	x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY@GOTPAGE
Lloh16:
	ldr	x8, [x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	bl	_FD
	mov	x24, x0
Lloh18:
	adrp	x8, _HFLIP_CHECK_DELAY@GOTPAGE
Lloh19:
	ldr	x8, [x8, _HFLIP_CHECK_DELAY@GOTPAGEOFF]
Lloh20:
	ldr	w26, [x8]
Lloh21:
	adrp	x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE@GOTPAGE
Lloh22:
	ldr	x8, [x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE@GOTPAGEOFF]
Lloh23:
	ldr	w0, [x8]
	bl	_FD
	mov	x25, x0
Lloh24:
	adrp	x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING@GOTPAGE
Lloh25:
	ldr	x8, [x8, _DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING@GOTPAGEOFF]
Lloh26:
	ldr	w0, [x8]
	bl	_FD
	stp	w0, wzr, [sp, #16]
	stp	w25, wzr, [sp, #8]
	stp	w24, w26, [sp]
	mov	x0, x19
	mov	w1, #6
	mov	x2, x20
	mov	w3, #0
	mov	x4, x21
	mov	w5, #0
	mov	x6, x22
	mov	x7, x23
	bl	_CRTC_REG_SET_N
Lloh27:
	adrp	x8, _CRTC0_CRTC_GSL_CONTROL@GOTPAGE
Lloh28:
	ldr	x8, [x8, _CRTC0_CRTC_GSL_CONTROL@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
Lloh30:
	adrp	x8, _CRTC_GSL_CHECK_LINE_NUM@GOTPAGE
Lloh31:
	ldr	x8, [x8, _CRTC_GSL_CHECK_LINE_NUM@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
Lloh33:
	adrp	x8, _CRTC_GSL_FORCE_DELAY@GOTPAGE
Lloh34:
	ldr	x8, [x8, _CRTC_GSL_FORCE_DELAY@GOTPAGEOFF]
Lloh35:
	ldr	w3, [x8]
	mov	w2, #0
	mov	w4, #2
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #112
	b	_CRTC_REG_SET_2
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_DCP0_DCP_GSL_CONTROL,4,2       ; @DCP0_DCP_GSL_CONTROL
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN,4,2 ; @DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN,4,2 ; @DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY,4,2 ; @DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY
	.comm	_HFLIP_READY_DELAY,4,2          ; @HFLIP_READY_DELAY
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY,4,2 ; @DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY
	.comm	_HFLIP_CHECK_DELAY,4,2          ; @HFLIP_CHECK_DELAY
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE,4,2 ; @DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE
	.comm	_DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING,4,2 ; @DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING
	.comm	_CRTC0_CRTC_GSL_CONTROL,4,2     ; @CRTC0_CRTC_GSL_CONTROL
	.comm	_CRTC_GSL_CHECK_LINE_NUM,4,2    ; @CRTC_GSL_CHECK_LINE_NUM
	.comm	_CRTC_GSL_FORCE_DELAY,4,2       ; @CRTC_GSL_FORCE_DELAY
.subsections_via_symbols
