	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gmc_v9_0_gart_enable
_gmc_v9_0_gart_enable:                  ## @gmc_v9_0_gart_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	_golden_settings_vega10_hdp@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%ebx, %edi
	callq	_ARRAY_SIZE
	movq	%r15, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_amdgpu_device_program_register_sequence
	cmpq	$0, 16(%r15)
	je	LBB0_1
## %bb.2:
	movq	%r15, %rdi
	callq	_amdgpu_gart_table_vram_pin
	testl	%eax, %eax
	jne	LBB0_17
## %bb.3:
	cmpl	$128, (%r15)
	jne	LBB0_5
## %bb.4:
	movq	%r15, %rdi
	movl	$1, %esi
	callq	_mmhub_v1_0_update_power_gating
LBB0_5:
	movq	%r15, %rdi
	callq	_gfxhub_v1_0_gart_enable
	testl	%eax, %eax
	jne	LBB0_17
## %bb.6:
	movl	(%r15), %eax
	movq	_CHIP_ARCTURUS@GOTPCREL(%rip), %r12
	cmpl	(%r12), %eax
	jne	LBB0_8
## %bb.7:
	movq	%r15, %rdi
	callq	_mmhub_v9_4_gart_enable
	testl	%eax, %eax
	jne	LBB0_17
	jmp	LBB0_10
LBB0_1:
	movl	40(%r15), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_17:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_8:
	movq	%r15, %rdi
	callq	_mmhub_v1_0_gart_enable
	testl	%eax, %eax
	jne	LBB0_17
LBB0_10:
	movq	_HDP@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movq	_HDP_MISC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_FLUSH_INVALIDATE_CACHE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%esi, %esi
	movl	$1, %r8d
	callq	_WREG32_FIELD15
	movl	(%r14), %edi
	movq	_mmHDP_HOST_PATH_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	(%r14), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmHDP_NONSURFACE_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	24(%r15), %ecx
	sarl	$8, %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmHDP_NONSURFACE_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movq	32(%r15), %rax
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	*(%rax)
	movq	_amdgpu_vm_fault_stop@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_AMDGPU_VM_FAULT_STOP_ALWAYS@GOTPCREL(%rip), %rcx
	xorl	%r14d, %r14d
	cmpq	(%rcx), %rax
	setne	%r14b
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_gfxhub_v1_0_set_fault_enable_default
	movl	(%r15), %eax
	cmpl	(%r12), %eax
	jne	LBB0_12
## %bb.11:
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_mmhub_v9_4_set_fault_enable_default
	jmp	LBB0_13
LBB0_12:
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_mmhub_v1_0_set_fault_enable_default
LBB0_13:
	cmpl	$0, 4(%r15)
	jle	LBB0_16
## %bb.14:
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_15:                                ## =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	xorl	%esi, %esi
	movl	%ebx, %edx
	xorl	%ecx, %ecx
	callq	_gmc_v9_0_flush_gpu_tlb
	incl	%ebx
	cmpl	4(%r15), %ebx
	jl	LBB0_15
LBB0_16:
	movl	28(%r15), %ebx
	sarl	$20, %ebx
	movq	16(%r15), %rdi
	callq	_amdgpu_bo_gpu_offset
	leaq	L_.str.1(%rip), %rdi
	movl	%ebx, %esi
	movq	%rax, %rdx
	callq	_DRM_INFO
	movl	$1, 8(%r15)
	xorl	%eax, %eax
	jmp	LBB0_17
	.cfi_endproc
                                        ## -- End function
	.comm	_golden_settings_vega10_hdp,4,2 ## @golden_settings_vega10_hdp
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"No VRAM object for PCIE GART.\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_CHIP_ARCTURUS,4,2              ## @CHIP_ARCTURUS
	.comm	_HDP,4,2                        ## @HDP
	.comm	_HDP_MISC_CNTL,4,2              ## @HDP_MISC_CNTL
	.comm	_FLUSH_INVALIDATE_CACHE,4,2     ## @FLUSH_INVALIDATE_CACHE
	.comm	_mmHDP_HOST_PATH_CNTL,4,2       ## @mmHDP_HOST_PATH_CNTL
	.comm	_mmHDP_NONSURFACE_BASE,4,2      ## @mmHDP_NONSURFACE_BASE
	.comm	_mmHDP_NONSURFACE_BASE_HI,4,2   ## @mmHDP_NONSURFACE_BASE_HI
	.comm	_amdgpu_vm_fault_stop,8,3       ## @amdgpu_vm_fault_stop
	.comm	_AMDGPU_VM_FAULT_STOP_ALWAYS,8,3 ## @AMDGPU_VM_FAULT_STOP_ALWAYS
L_.str.1:                               ## @.str.1
	.asciz	"PCIE GART of %uM enabled (table at 0x%016llX).\n"

	.no_dead_strip	_gmc_v9_0_gart_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gmc_v9_0_gart_enable
_gmc_v9_0_gart_enable:                  ; @gmc_v9_0_gart_enable
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, _golden_settings_vega10_hdp@GOTPAGE
Lloh1:
	ldr	x8, [x8, _golden_settings_vega10_hdp@GOTPAGEOFF]
Lloh2:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_device_program_register_sequence
	ldr	x8, [x19, #16]
	cbz	x8, LBB0_7
; %bb.1:
	mov	x0, x19
	bl	_amdgpu_gart_table_vram_pin
	cbnz	w0, LBB0_8
; %bb.2:
	ldr	w8, [x19]
	cmp	w8, #128
	b.ne	LBB0_4
; %bb.3:
	mov	x0, x19
	mov	w1, #1
	bl	_mmhub_v1_0_update_power_gating
LBB0_4:
	mov	x0, x19
	bl	_gfxhub_v1_0_gart_enable
	cbnz	w0, LBB0_8
; %bb.5:
	ldr	w8, [x19]
Lloh3:
	adrp	x21, _CHIP_ARCTURUS@GOTPAGE
Lloh4:
	ldr	x21, [x21, _CHIP_ARCTURUS@GOTPAGEOFF]
	ldr	w9, [x21]
	mov	x0, x19
	cmp	w8, w9
	b.ne	LBB0_9
; %bb.6:
	bl	_mmhub_v9_4_gart_enable
	cbnz	w0, LBB0_8
	b	LBB0_10
LBB0_7:
	ldr	w0, [x19, #40]
Lloh5:
	adrp	x1, l_.str@PAGE
Lloh6:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
Lloh7:
	adrp	x8, _EINVAL@GOTPAGE
Lloh8:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_8:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_9:
	bl	_mmhub_v1_0_gart_enable
	cbnz	w0, LBB0_8
LBB0_10:
Lloh10:
	adrp	x20, _HDP@GOTPAGE
Lloh11:
	ldr	x20, [x20, _HDP@GOTPAGEOFF]
	ldr	w0, [x20]
Lloh12:
	adrp	x8, _HDP_MISC_CNTL@GOTPAGE
Lloh13:
	ldr	x8, [x8, _HDP_MISC_CNTL@GOTPAGEOFF]
Lloh14:
	ldr	w2, [x8]
Lloh15:
	adrp	x8, _FLUSH_INVALIDATE_CACHE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _FLUSH_INVALIDATE_CACHE@GOTPAGEOFF]
Lloh17:
	ldr	w3, [x8]
	mov	w1, #0
	mov	w4, #1
	bl	_WREG32_FIELD15
	ldr	w0, [x20]
Lloh18:
	adrp	x22, _mmHDP_HOST_PATH_CNTL@GOTPAGE
Lloh19:
	ldr	x22, [x22, _mmHDP_HOST_PATH_CNTL@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	w1, #0
	bl	_RREG32_SOC15
	mov	x3, x0
	ldr	w0, [x20]
	ldr	w2, [x22]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x20]
Lloh20:
	adrp	x8, _mmHDP_NONSURFACE_BASE@GOTPAGE
Lloh21:
	ldr	x8, [x8, _mmHDP_NONSURFACE_BASE@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
	ldr	w8, [x19, #24]
	asr	w3, w8, #8
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x20]
Lloh23:
	adrp	x8, _mmHDP_NONSURFACE_BASE_HI@GOTPAGE
Lloh24:
	ldr	x8, [x8, _mmHDP_NONSURFACE_BASE_HI@GOTPAGEOFF]
Lloh25:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	x8, [x19, #32]
	ldr	x8, [x8]
	mov	x0, x19
	mov	x1, #0
	blr	x8
Lloh26:
	adrp	x8, _amdgpu_vm_fault_stop@GOTPAGE
Lloh27:
	ldr	x8, [x8, _amdgpu_vm_fault_stop@GOTPAGEOFF]
Lloh28:
	ldr	x8, [x8]
Lloh29:
	adrp	x9, _AMDGPU_VM_FAULT_STOP_ALWAYS@GOTPAGE
Lloh30:
	ldr	x9, [x9, _AMDGPU_VM_FAULT_STOP_ALWAYS@GOTPAGEOFF]
Lloh31:
	ldr	x9, [x9]
	cmp	x8, x9
	cset	w20, ne
	mov	x0, x19
	mov	x1, x20
	bl	_gfxhub_v1_0_set_fault_enable_default
	ldr	w8, [x19]
	ldr	w9, [x21]
	mov	x0, x19
	mov	x1, x20
	cmp	w8, w9
	b.ne	LBB0_12
; %bb.11:
	bl	_mmhub_v9_4_set_fault_enable_default
	b	LBB0_13
LBB0_12:
	bl	_mmhub_v1_0_set_fault_enable_default
LBB0_13:
	ldr	w8, [x19, #4]
	cmp	w8, #1
	b.lt	LBB0_16
; %bb.14:
	mov	w20, #0
LBB0_15:                                ; =>This Inner Loop Header: Depth=1
	mov	x0, x19
	mov	w1, #0
	mov	x2, x20
	mov	w3, #0
	bl	_gmc_v9_0_flush_gpu_tlb
	add	w20, w20, #1
	ldr	w8, [x19, #4]
	cmp	w20, w8
	b.lt	LBB0_15
LBB0_16:
	ldr	w8, [x19, #28]
	asr	w20, w8, #20
	ldr	x0, [x19, #16]
	bl	_amdgpu_bo_gpu_offset
	mov	x2, x0
Lloh32:
	adrp	x0, l_.str.1@PAGE
Lloh33:
	add	x0, x0, l_.str.1@PAGEOFF
	mov	x1, x20
	bl	_DRM_INFO
	mov	w0, #0
	mov	w8, #1
	str	w8, [x19, #8]
	b	LBB0_8
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpAdd	Lloh32, Lloh33
	.cfi_endproc
                                        ; -- End function
	.comm	_golden_settings_vega10_hdp,4,2 ; @golden_settings_vega10_hdp
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"No VRAM object for PCIE GART.\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_CHIP_ARCTURUS,4,2              ; @CHIP_ARCTURUS
	.comm	_HDP,4,2                        ; @HDP
	.comm	_HDP_MISC_CNTL,4,2              ; @HDP_MISC_CNTL
	.comm	_FLUSH_INVALIDATE_CACHE,4,2     ; @FLUSH_INVALIDATE_CACHE
	.comm	_mmHDP_HOST_PATH_CNTL,4,2       ; @mmHDP_HOST_PATH_CNTL
	.comm	_mmHDP_NONSURFACE_BASE,4,2      ; @mmHDP_NONSURFACE_BASE
	.comm	_mmHDP_NONSURFACE_BASE_HI,4,2   ; @mmHDP_NONSURFACE_BASE_HI
	.comm	_amdgpu_vm_fault_stop,8,3       ; @amdgpu_vm_fault_stop
	.comm	_AMDGPU_VM_FAULT_STOP_ALWAYS,8,3 ; @AMDGPU_VM_FAULT_STOP_ALWAYS
l_.str.1:                               ; @.str.1
	.asciz	"PCIE GART of %uM enabled (table at 0x%016llX).\n"

	.no_dead_strip	_gmc_v9_0_gart_enable
.subsections_via_symbols
