	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_drm_cvt_mode                   ## -- Begin function drm_cvt_mode
	.p2align	4, 0x90
_drm_cvt_mode:                          ## @drm_cvt_mode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	xorl	%r13d, %r13d
	testl	%esi, %esi
	je	LBB0_28
## %bb.1:
	movl	%edx, %ebx
	testl	%edx, %edx
	je	LBB0_28
## %bb.2:
	movl	%r8d, %r15d
	movl	%ecx, %r14d
	movl	%esi, %r12d
	movl	%r9d, -44(%rbp)                 ## 4-byte Spill
	callq	_drm_mode_create
	testq	%rax, %rax
	je	LBB0_3
## %bb.4:
	movq	%rax, %r13
	testl	%r14d, %r14d
	movl	$60, %r9d
	cmovnel	%r14d, %r9d
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	testl	%edi, %edi
	setne	%cl
	shll	%cl, %r9d
	leal	7(%r12), %r8d
	testl	%r12d, %r12d
	cmovnsl	%r12d, %r8d
	andl	$-8, %r8d
	cmpl	$0, 16(%rbp)
	je	LBB0_5
## %bb.8:
	leal	(%r8,%r8), %eax
	leal	(%rax,%rax,8), %eax
	cltq
	imulq	$274877907, %rax, %rdx          ## imm = 0x10624DD3
	movq	%rdx, %rsi
	shrq	$63, %rsi
	sarq	$38, %rdx
	leal	(%rdx,%rsi), %eax
	addl	$7, %eax
                                        ## kill: def $edx killed $edx killed $rdx
	addl	%esi, %edx
	cmovnsl	%edx, %eax
	andl	$-8, %eax
	movl	%ebx, %r14d
	testl	%edi, %edi
	je	LBB0_10
## %bb.9:
	movl	%ebx, %r14d
	shrl	$31, %r14d
	addl	%ebx, %r14d
	sarl	%r14d
LBB0_10:
	leal	(%r8,%rax,2), %r8d
	leal	(%r14,%r14), %eax
	leal	(%rax,%rax,8), %eax
	cltq
	imulq	$274877907, %rax, %rsi          ## imm = 0x10624DD3
	movq	%rsi, %rax
	shrq	$63, %rax
	sarq	$38, %rsi
	addl	%eax, %esi
	addl	%esi, %esi
	jmp	LBB0_11
LBB0_3:
	xorl	%r13d, %r13d
	jmp	LBB0_28
LBB0_5:
	movl	%ebx, %r14d
	testl	%edi, %edi
	je	LBB0_7
## %bb.6:
	movl	%ebx, %r14d
	shrl	$31, %r14d
	addl	%ebx, %r14d
	sarl	%r14d
LBB0_7:
	xorl	%esi, %esi
LBB0_11:
	movl	%r8d, (%r13)
	leal	(%rsi,%rbx), %edi
	movl	%edi, 4(%r13)
	imull	$-1431655765, %ebx, %eax        ## imm = 0xAAAAAAAB
	addl	$715827882, %eax                ## imm = 0x2AAAAAAA
	cmpl	$1431655764, %eax               ## imm = 0x55555554
	ja	LBB0_13
## %bb.12:
	leal	(,%rbx,4), %eax
	cltq
	imulq	$1431655766, %rax, %rax         ## imm = 0x55555556
	movq	%rax, %rdx
	shrq	$63, %rdx
	shrq	$32, %rax
	addl	%edx, %eax
	movl	$4, %r10d
	cmpl	%r12d, %eax
	je	LBB0_22
LBB0_13:
	movslq	%ebx, %rax
	imulq	$954437177, %rax, %rax          ## imm = 0x38E38E39
	movq	%rax, %rdx
	shrq	$63, %rdx
	sarq	$33, %rax
	addl	%edx, %eax
	leal	(%rax,%rax,8), %edx
	movl	%ebx, %r11d
	subl	%edx, %r11d
	jne	LBB0_15
## %bb.14:
	movl	%ebx, %edx
	shll	$4, %edx
	movslq	%edx, %rdx
	imulq	$954437177, %rdx, %rdx          ## imm = 0x38E38E39
	movq	%rdx, %rax
	shrq	$63, %rax
	sarq	$33, %rdx
	addl	%eax, %edx
	movl	$5, %r10d
	cmpl	%r12d, %edx
	je	LBB0_22
LBB0_15:
	imull	$-858993459, %ebx, %eax         ## imm = 0xCCCCCCCD
	addl	$429496728, %eax                ## imm = 0x19999998
	rorl	%eax
	cmpl	$429496728, %eax                ## imm = 0x19999998
	ja	LBB0_17
## %bb.16:
	movl	%ebx, %eax
	shll	$4, %eax
	cltq
	imulq	$1717986919, %rax, %rax         ## imm = 0x66666667
	movq	%rax, %rdx
	shrq	$63, %rdx
	sarq	$34, %rax
	addl	%edx, %eax
	movl	$6, %r10d
	cmpl	%r12d, %eax
	je	LBB0_22
LBB0_17:
	testb	$3, %bl
	jne	LBB0_19
## %bb.18:
	leal	(%rbx,%rbx,4), %eax
	leal	(%rbx,%rbx,4), %edx
	addl	$3, %edx
	testl	%eax, %eax
	cmovnsl	%eax, %edx
	sarl	$2, %edx
	movl	$7, %r10d
	cmpl	%r12d, %edx
	je	LBB0_22
LBB0_19:
	testl	%r11d, %r11d
	jne	LBB0_21
## %bb.20:
	leal	(%rbx,%rbx,4), %eax
	leal	(%rax,%rax,2), %eax
	cltq
	imulq	$954437177, %rax, %rax          ## imm = 0x38E38E39
	movq	%rax, %rdx
	shrq	$63, %rdx
	sarq	$33, %rax
	addl	%edx, %eax
	movl	$7, %r10d
	cmpl	%r12d, %eax
	je	LBB0_22
LBB0_21:
	movl	$10, %r10d
LBB0_22:
	testl	%r15d, %r15d
	je	LBB0_23
## %bb.24:
	imull	$-460000, %r9d, %eax            ## imm = 0xFFF8FB20
	addl	$1000000000, %eax               ## imm = 0x3B9ACA00
	addl	%r14d, %esi
	imull	%esi, %r9d
	xorl	%edx, %edx
	divl	%r9d
	movl	%eax, %r9d
	movl	$460000, %eax                   ## imm = 0x704E0
	xorl	%edx, %edx
	divl	%r9d
	movl	%eax, %ecx
	incl	%ecx
	leal	9(%r10), %eax
	cmpl	%eax, %ecx
	cmovbel	%eax, %ecx
	addl	%esi, %ecx
	leal	160(%r8), %eax
	leal	80(%r8), %edx
	addl	$48, %r8d
	jmp	LBB0_25
LBB0_23:
	xorl	%eax, %eax
	movb	%cl, %al
	addl	%r14d, %esi
	leal	(%rax,%rsi,2), %ecx
	addl	$6, %ecx
	imull	$-1100000, %r9d, %eax           ## imm = 0xFFEF3720
	addl	$2000000000, %eax               ## imm = 0x77359400
	imull	%r9d, %ecx
	xorl	%edx, %edx
	divl	%ecx
	movl	%eax, %r9d
	movl	$550000, %eax                   ## imm = 0x86470
	xorl	%edx, %edx
	divl	%r9d
                                        ## kill: def $eax killed $eax def $rax
	incl	%eax
	leal	3(%r10), %ecx
	cmpl	%ecx, %eax
	cmovbel	%ecx, %eax
	leal	(%rax,%rsi), %ecx
	addl	$3, %ecx
	imull	$300, %r9d, %eax                ## imm = 0x12C
	imulq	$274877907, %rax, %rax          ## imm = 0x10624DD3
	shrq	$38, %rax
	movl	$30000, %edx                    ## imm = 0x7530
	subl	%eax, %edx
	cmpl	$20001, %edx                    ## imm = 0x4E21
	movl	$20000, %eax                    ## imm = 0x4E20
	cmovael	%edx, %eax
	movl	$100000, %esi                   ## imm = 0x186A0
	subl	%eax, %esi
	imull	%r8d, %eax
	xorl	%edx, %edx
	divl	%esi
                                        ## kill: def $eax killed $eax def $rax
	leal	15(%rax), %edx
	testl	%eax, %eax
	cmovnsl	%eax, %edx
	andl	$-16, %edx
	leal	(%rdx,%r8), %eax
	sarl	%edx
	addl	%r8d, %edx
	leal	(,%rax,8), %esi
	movslq	%esi, %rsi
	imulq	$-1374389535, %rsi, %rsi        ## imm = 0xAE147AE1
	movq	%rdi, %rbx
	movq	%rsi, %rdi
	shrq	$63, %rdi
	sarq	$37, %rsi
	addl	%edi, %esi
	movq	%rbx, %rdi
	leal	(%rsi,%rdx), %r8d
	addl	$7, %r8d
                                        ## kill: def $esi killed $esi killed $rsi
	addl	%edx, %esi
	cmovnsl	%esi, %r8d
	andl	$-8, %r8d
	addl	$8, %r8d
LBB0_25:
	movl	%edi, %esi
	addl	$3, %esi
	leal	(%r10,%rdi), %ebx
	addl	$3, %ebx
	movl	%ecx, 8(%r13)
	movl	%eax, 12(%r13)
	movl	%edx, 16(%r13)
	movl	%r8d, 20(%r13)
	movl	%esi, 24(%r13)
	movl	%ebx, 28(%r13)
	imull	$1000000, %eax, %ebx            ## imm = 0xF4240
	movl	%ebx, %edi
	movl	%r9d, %esi
	callq	_do_div
	movslq	32(%r13), %rax
	imulq	$274877907, %rax, %rcx          ## imm = 0x10624DD3
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$36, %rcx
	addl	%edx, %ecx
	imull	$250, %ecx, %ecx
	subl	%eax, %ecx
	addl	%ebx, %ecx
	movl	%ecx, 32(%r13)
	cmpl	$0, -44(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_27
## %bb.26:
	shll	8(%r13)
	movq	_DRM_MODE_FLAG_INTERLACE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, 36(%r13)
LBB0_27:
	movq	%r13, %rdi
	callq	_drm_mode_set_name
	movq	_DRM_MODE_FLAG_PVSYNC@GOTPCREL(%rip), %rax
	movq	_DRM_MODE_FLAG_PHSYNC@GOTPCREL(%rip), %rcx
	movq	_DRM_MODE_FLAG_NHSYNC@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movq	_DRM_MODE_FLAG_NVSYNC@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	orl	(%rax), %edx
	orl	(%rcx), %esi
	testl	%r15d, %r15d
	cmovel	%edx, %esi
	orl	%esi, 36(%r13)
LBB0_28:
	movq	%r13, %rax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DRM_MODE_FLAG_INTERLACE,4,2    ## @DRM_MODE_FLAG_INTERLACE
	.comm	_DRM_MODE_FLAG_PHSYNC,4,2       ## @DRM_MODE_FLAG_PHSYNC
	.comm	_DRM_MODE_FLAG_NVSYNC,4,2       ## @DRM_MODE_FLAG_NVSYNC
	.comm	_DRM_MODE_FLAG_PVSYNC,4,2       ## @DRM_MODE_FLAG_PVSYNC
	.comm	_DRM_MODE_FLAG_NHSYNC,4,2       ## @DRM_MODE_FLAG_NHSYNC
	.comm	_CVT_CLOCK_STEP,4,2             ## @CVT_CLOCK_STEP
	.comm	_CVT_C_PRIME,4,2                ## @CVT_C_PRIME
	.comm	_CVT_HSYNC_PERCENTAGE,4,2       ## @CVT_HSYNC_PERCENTAGE
	.comm	_CVT_H_GRANULARITY,4,2          ## @CVT_H_GRANULARITY
	.comm	_CVT_MARGIN_PERCENTAGE,4,2      ## @CVT_MARGIN_PERCENTAGE
	.comm	_CVT_MIN_VSYNC_BP,4,2           ## @CVT_MIN_VSYNC_BP
	.comm	_CVT_MIN_V_BPORCH,4,2           ## @CVT_MIN_V_BPORCH
	.comm	_CVT_MIN_V_PORCH,4,2            ## @CVT_MIN_V_PORCH
	.comm	_CVT_M_PRIME,4,2                ## @CVT_M_PRIME
	.comm	_CVT_RB_H_BLANK,4,2             ## @CVT_RB_H_BLANK
	.comm	_CVT_RB_H_SYNC,4,2              ## @CVT_RB_H_SYNC
	.comm	_CVT_RB_MIN_VBLANK,4,2          ## @CVT_RB_MIN_VBLANK
	.comm	_CVT_RB_VFPORCH,4,2             ## @CVT_RB_VFPORCH
	.comm	_HV_FACTOR,4,2                  ## @HV_FACTOR
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_drm_cvt_mode                   ; -- Begin function drm_cvt_mode
	.p2align	2
_drm_cvt_mode:                          ; @drm_cvt_mode
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, #0
	cbz	w1, LBB0_26
; %bb.1:
	mov	x23, x2
	cbz	w2, LBB0_26
; %bb.2:
	mov	x24, x6
	mov	x21, x5
	mov	x20, x4
	mov	x25, x3
	mov	x22, x1
	bl	_drm_mode_create
	mov	x19, x0
	cbz	x0, LBB0_26
; %bb.3:
	mov	w8, #60
	cmp	w25, #0
	csel	w11, w8, w25, eq
	cmp	w21, #0
	cset	w10, ne
	negs	w8, w22
	and	w8, w8, #0x7
	and	w9, w22, #0x7
	csneg	w8, w9, w8, mi
	sub	w8, w22, w8
	cbz	w24, LBB0_5
; %bb.4:
	add	w9, w8, w8, lsl #3
	lsl	w9, w9, #1
	mov	w13, #19923
	movk	w13, #4194, lsl #16
	smull	x9, w9, w13
	lsr	x12, x9, #63
	asr	x9, x9, #38
	add	w9, w9, w12
	negs	w12, w9
	and	w14, w9, #0x7
	and	w12, w12, #0x7
	csneg	w12, w14, w12, mi
	sub	w9, w9, w12
	add	w8, w8, w9, lsl #1
	cmp	w23, #0
	cinc	w9, w23, lt
	asr	w9, w9, #1
	cmp	w21, #0
	csel	w12, w23, w9, eq
	add	w9, w12, w12, lsl #3
	lsl	w9, w9, #1
	smull	x9, w9, w13
	lsr	x13, x9, #63
	asr	x9, x9, #38
	add	w9, w9, w13
	lsl	w13, w9, #1
	b	LBB0_6
LBB0_5:
	mov	w13, #0
	cmp	w23, #0
	cinc	w9, w23, lt
	asr	w9, w9, #1
	cmp	w21, #0
	csel	w12, w23, w9, eq
LBB0_6:
	add	w9, w13, w23
	stp	w8, w9, [x19]
	mov	w14, #43691
	movk	w14, #43690, lsl #16
	mov	w15, #43690
	movk	w15, #10922, lsl #16
	madd	w14, w23, w14, w15
	mov	w15, #21844
	movk	w15, #21845, lsl #16
	cmp	w14, w15
	b.hi	LBB0_9
; %bb.7:
	lsl	w14, w23, #2
	mov	w15, #21846
	movk	w15, #21845, lsl #16
	smull	x14, w14, w15
	lsr	x15, x14, #63
	lsr	x14, x14, #32
	add	w14, w14, w15
	cmp	w14, w22
	b.ne	LBB0_9
; %bb.8:
	mov	w14, #4
	lsl	w11, w11, w10
	cbnz	w20, LBB0_22
	b	LBB0_20
LBB0_9:
	mov	w15, #36409
	movk	w15, #14563, lsl #16
	smull	x14, w23, w15
	lsr	x16, x14, #63
	asr	x14, x14, #33
	add	w14, w14, w16
	add	w14, w14, w14, lsl #3
	subs	w14, w23, w14
	b.ne	LBB0_12
; %bb.10:
	lsl	w16, w23, #4
	smull	x15, w16, w15
	lsr	x16, x15, #63
	asr	x15, x15, #33
	add	w15, w15, w16
	cmp	w15, w22
	b.ne	LBB0_12
; %bb.11:
	mov	w14, #5
	lsl	w11, w11, w10
	cbnz	w20, LBB0_22
	b	LBB0_20
LBB0_12:
	mov	w15, #52429
	movk	w15, #52428, lsl #16
	mov	w16, #39320
	movk	w16, #6553, lsl #16
	madd	w15, w23, w15, w16
	ror	w15, w15, #1
	cmp	w15, w16
	b.hi	LBB0_15
; %bb.13:
	lsl	w15, w23, #4
	mov	w16, #26215
	movk	w16, #26214, lsl #16
	smull	x15, w15, w16
	lsr	x16, x15, #63
	asr	x15, x15, #34
	add	w15, w15, w16
	cmp	w15, w22
	b.ne	LBB0_15
; %bb.14:
	mov	w14, #6
	lsl	w11, w11, w10
	cbnz	w20, LBB0_22
	b	LBB0_20
LBB0_15:
	tst	w23, #0x3
	b.ne	LBB0_17
; %bb.16:
	add	w15, w23, w23, lsl #2
	add	w16, w15, #3
	cmp	w15, #0
	csel	w15, w16, w15, lt
	cmp	w22, w15, asr #2
	b.eq	LBB0_19
LBB0_17:
	cbnz	w14, LBB0_21
; %bb.18:
	lsl	w14, w23, #4
	sub	w14, w14, w23
	mov	w15, #36409
	movk	w15, #14563, lsl #16
	smull	x14, w14, w15
	lsr	x15, x14, #63
	asr	x14, x14, #33
	add	w14, w14, w15
	cmp	w14, w22
	b.ne	LBB0_21
LBB0_19:
	mov	w14, #7
	lsl	w11, w11, w10
	cbnz	w20, LBB0_22
LBB0_20:
	add	w12, w13, w12
	bfi	w10, w12, #1, #31
	add	w10, w10, #6
	mov	w13, #14112
	movk	w13, #65519, lsl #16
	mov	w15, #37888
	movk	w15, #30517, lsl #16
	madd	w13, w11, w13, w15
	mul	w10, w10, w11
	udiv	w1, w13, w10
	mov	w10, #25712
	movk	w10, #8, lsl #16
	udiv	w10, w10, w1
	add	w11, w10, #1
	add	w13, w14, #3
	cmp	w11, w13
	csinc	w10, w13, w10, ls
	add	w10, w12, w10
	add	w10, w10, #3
	mov	w11, #300
	mul	w11, w1, w11
	mov	w12, #19923
	movk	w12, #4194, lsl #16
	umull	x11, w11, w12
	lsr	x11, x11, #38
	mov	w12, #30000
	mov	w13, #20000
	sub	w11, w12, w11
	cmp	w11, w13
	csel	w11, w11, w13, hi
	mul	w12, w11, w8
	mov	w13, #34464
	movk	w13, #1, lsl #16
	sub	w11, w13, w11
	udiv	w11, w12, w11
	and	w12, w11, #0xf
	negs	w13, w11
	and	w13, w13, #0xf
	csneg	w12, w12, w13, mi
	sub	w12, w11, w12
	add	w11, w12, w8
	cmp	w12, #0
	cinc	w12, w12, lt
	add	w12, w8, w12, asr #1
	lsl	w8, w11, #3
	mov	w13, #31457
	movk	w13, #44564, lsl #16
	smull	x8, w8, w13
	lsr	x13, x8, #63
	asr	x8, x8, #37
	add	w8, w8, w13
	add	w8, w8, w12
	and	w13, w8, #0x7
	negs	w15, w8
	and	w15, w15, #0x7
	csneg	w13, w13, w15, mi
	sub	w8, w8, w13
	add	w8, w8, #8
	b	LBB0_23
LBB0_21:
	mov	w14, #10
	lsl	w11, w11, w10
	cbz	w20, LBB0_20
LBB0_22:
	mov	w10, #64288
	movk	w10, #65528, lsl #16
	mov	w15, #51712
	movk	w15, #15258, lsl #16
	madd	w10, w11, w10, w15
	add	w12, w13, w12
	mul	w11, w12, w11
	udiv	w1, w10, w11
	mov	w10, #1248
	movk	w10, #7, lsl #16
	udiv	w10, w10, w1
	add	w11, w10, #1
	add	w13, w14, #9
	cmp	w11, w13
	csinc	w10, w13, w10, ls
	add	w10, w10, w12
	add	w11, w8, #160
	add	w12, w8, #80
	add	w8, w8, #48
LBB0_23:
	add	w9, w9, #3
	add	w13, w14, w9
	stp	w10, w11, [x19, #8]
	stp	w12, w8, [x19, #16]
	stp	w9, w13, [x19, #24]
	mov	w8, #16960
	movk	w8, #15, lsl #16
	mul	w22, w11, w8
	mov	x0, x22
	bl	_do_div
	ldrsw	x8, [x19, #32]
	mov	w9, #19923
	movk	w9, #4194, lsl #16
	mul	x9, x8, x9
	lsr	x10, x9, #32
	lsr	x9, x9, #63
	add	w9, w9, w10, asr #4
	mov	w10, #250
	neg	w8, w8
	madd	w8, w9, w10, w8
	add	w8, w22, w8
	str	w8, [x19, #32]
	cbz	w21, LBB0_25
; %bb.24:
	ldr	w8, [x19, #8]
	lsl	w8, w8, #1
	str	w8, [x19, #8]
Lloh0:
	adrp	x8, _DRM_MODE_FLAG_INTERLACE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DRM_MODE_FLAG_INTERLACE@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	ldr	w9, [x19, #36]
	orr	w8, w9, w8
	str	w8, [x19, #36]
LBB0_25:
	mov	x0, x19
	bl	_drm_mode_set_name
Lloh3:
	adrp	x8, _DRM_MODE_FLAG_PVSYNC@GOTPAGE
Lloh4:
	ldr	x8, [x8, _DRM_MODE_FLAG_PVSYNC@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
Lloh6:
	adrp	x9, _DRM_MODE_FLAG_PHSYNC@GOTPAGE
Lloh7:
	ldr	x9, [x9, _DRM_MODE_FLAG_PHSYNC@GOTPAGEOFF]
Lloh8:
	adrp	x10, _DRM_MODE_FLAG_NHSYNC@GOTPAGE
Lloh9:
	ldr	x10, [x10, _DRM_MODE_FLAG_NHSYNC@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
Lloh11:
	ldr	w10, [x10]
Lloh12:
	adrp	x11, _DRM_MODE_FLAG_NVSYNC@GOTPAGE
Lloh13:
	ldr	x11, [x11, _DRM_MODE_FLAG_NVSYNC@GOTPAGEOFF]
Lloh14:
	ldr	w11, [x11]
	orr	w8, w10, w8
	orr	w9, w11, w9
	cmp	w20, #0
	csel	w8, w8, w9, eq
	ldr	w9, [x19, #36]
	orr	w8, w8, w9
	str	w8, [x19, #36]
LBB0_26:
	mov	x0, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh10
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_DRM_MODE_FLAG_INTERLACE,4,2    ; @DRM_MODE_FLAG_INTERLACE
	.comm	_DRM_MODE_FLAG_PHSYNC,4,2       ; @DRM_MODE_FLAG_PHSYNC
	.comm	_DRM_MODE_FLAG_NVSYNC,4,2       ; @DRM_MODE_FLAG_NVSYNC
	.comm	_DRM_MODE_FLAG_PVSYNC,4,2       ; @DRM_MODE_FLAG_PVSYNC
	.comm	_DRM_MODE_FLAG_NHSYNC,4,2       ; @DRM_MODE_FLAG_NHSYNC
	.comm	_CVT_CLOCK_STEP,4,2             ; @CVT_CLOCK_STEP
	.comm	_CVT_C_PRIME,4,2                ; @CVT_C_PRIME
	.comm	_CVT_HSYNC_PERCENTAGE,4,2       ; @CVT_HSYNC_PERCENTAGE
	.comm	_CVT_H_GRANULARITY,4,2          ; @CVT_H_GRANULARITY
	.comm	_CVT_MARGIN_PERCENTAGE,4,2      ; @CVT_MARGIN_PERCENTAGE
	.comm	_CVT_MIN_VSYNC_BP,4,2           ; @CVT_MIN_VSYNC_BP
	.comm	_CVT_MIN_V_BPORCH,4,2           ; @CVT_MIN_V_BPORCH
	.comm	_CVT_MIN_V_PORCH,4,2            ; @CVT_MIN_V_PORCH
	.comm	_CVT_M_PRIME,4,2                ; @CVT_M_PRIME
	.comm	_CVT_RB_H_BLANK,4,2             ; @CVT_RB_H_BLANK
	.comm	_CVT_RB_H_SYNC,4,2              ; @CVT_RB_H_SYNC
	.comm	_CVT_RB_MIN_VBLANK,4,2          ; @CVT_RB_MIN_VBLANK
	.comm	_CVT_RB_VFPORCH,4,2             ; @CVT_RB_VFPORCH
	.comm	_HV_FACTOR,4,2                  ; @HV_FACTOR
.subsections_via_symbols
