	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vce_v3_0_ring_set_wptr
_vce_v3_0_ring_set_wptr:                ## @vce_v3_0_ring_set_wptr
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	8(%rdi), %r14
	movq	%r14, %rdi
	callq	_mutex_lock
	movq	8(%r14), %rax
	xorl	%edi, %edi
	testq	%rax, %rax
	je	LBB0_3
## %bb.1:
	movq	_AMDGPU_VCE_HARVEST_VCE1@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_3
## %bb.2:
	movq	_AMDGPU_VCE_HARVEST_VCE0@GOTPCREL(%rip), %rcx
	movl	$1, %edi
	cmpq	(%rcx), %rax
	jne	LBB0_4
LBB0_3:
	movq	_mmGRBM_GFX_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	callq	_GET_VCE_INSTANCE
	movl	%r15d, %edi
	movl	%eax, %esi
	callq	_WREG32
LBB0_4:
	movl	(%rbx), %ecx
	cmpl	$1, %ecx
	jne	LBB0_5
## %bb.6:
	movq	_mmVCE_RB_WPTR2@GOTPCREL(%rip), %rax
	jmp	LBB0_7
LBB0_5:
	movq	_mmVCE_RB_WPTR3@GOTPCREL(%rip), %rax
LBB0_7:
	movl	4(%rbx), %edi
	testl	%ecx, %ecx
	jne	LBB0_9
## %bb.8:
	movq	_mmVCE_RB_WPTR@GOTPCREL(%rip), %rax
LBB0_9:
	movl	(%rax), %ebx
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmGRBM_GFX_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmGRBM_GFX_INDEX_DEFAULT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_WREG32
	movq	%r14, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_mutex_unlock                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_VCE_HARVEST_VCE1,8,3    ## @AMDGPU_VCE_HARVEST_VCE1
	.comm	_mmGRBM_GFX_INDEX,4,2           ## @mmGRBM_GFX_INDEX
	.comm	_AMDGPU_VCE_HARVEST_VCE0,8,3    ## @AMDGPU_VCE_HARVEST_VCE0
	.comm	_mmVCE_RB_WPTR,4,2              ## @mmVCE_RB_WPTR
	.comm	_mmVCE_RB_WPTR2,4,2             ## @mmVCE_RB_WPTR2
	.comm	_mmVCE_RB_WPTR3,4,2             ## @mmVCE_RB_WPTR3
	.comm	_mmGRBM_GFX_INDEX_DEFAULT,4,2   ## @mmGRBM_GFX_INDEX_DEFAULT
	.no_dead_strip	_vce_v3_0_ring_set_wptr
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vce_v3_0_ring_set_wptr
_vce_v3_0_ring_set_wptr:                ; @vce_v3_0_ring_set_wptr
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x0
	ldr	x19, [x0, #8]
	mov	x0, x19
	bl	_mutex_lock
Lloh0:
	adrp	x9, _AMDGPU_VCE_HARVEST_VCE1@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMDGPU_VCE_HARVEST_VCE1@GOTPAGEOFF]
	ldr	x8, [x19, #8]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, #0
	ccmp	x8, x9, #4, ne
Lloh3:
	adrp	x22, _mmGRBM_GFX_INDEX@GOTPAGE
Lloh4:
	ldr	x22, [x22, _mmGRBM_GFX_INDEX@GOTPAGEOFF]
	b.ne	LBB0_2
; %bb.1:
	mov	w0, #0
	b	LBB0_4
LBB0_2:
Lloh5:
	adrp	x9, _AMDGPU_VCE_HARVEST_VCE0@GOTPAGE
Lloh6:
	ldr	x9, [x9, _AMDGPU_VCE_HARVEST_VCE0@GOTPAGEOFF]
Lloh7:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_5
; %bb.3:
	mov	w0, #1
LBB0_4:
	ldr	w21, [x22]
	bl	_GET_VCE_INSTANCE
	mov	x1, x0
	mov	x0, x21
	bl	_WREG32
LBB0_5:
Lloh8:
	adrp	x8, _mmVCE_RB_WPTR@GOTPAGE
Lloh9:
	ldr	x8, [x8, _mmVCE_RB_WPTR@GOTPAGEOFF]
Lloh10:
	adrp	x9, _mmVCE_RB_WPTR2@GOTPAGE
Lloh11:
	ldr	x9, [x9, _mmVCE_RB_WPTR2@GOTPAGEOFF]
Lloh12:
	adrp	x10, _mmVCE_RB_WPTR3@GOTPAGE
Lloh13:
	ldr	x10, [x10, _mmVCE_RB_WPTR3@GOTPAGEOFF]
	ldp	w11, w0, [x20]
	cmp	w11, #1
	csel	x9, x9, x10, eq
	cmp	w11, #0
	csel	x8, x8, x9, eq
	ldr	w20, [x8]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
	ldr	w0, [x22]
Lloh14:
	adrp	x8, _mmGRBM_GFX_INDEX_DEFAULT@GOTPAGE
Lloh15:
	ldr	x8, [x8, _mmGRBM_GFX_INDEX_DEFAULT@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
	bl	_WREG32
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_mutex_unlock
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_VCE_HARVEST_VCE1,8,3    ; @AMDGPU_VCE_HARVEST_VCE1
	.comm	_mmGRBM_GFX_INDEX,4,2           ; @mmGRBM_GFX_INDEX
	.comm	_AMDGPU_VCE_HARVEST_VCE0,8,3    ; @AMDGPU_VCE_HARVEST_VCE0
	.comm	_mmVCE_RB_WPTR,4,2              ; @mmVCE_RB_WPTR
	.comm	_mmVCE_RB_WPTR2,4,2             ; @mmVCE_RB_WPTR2
	.comm	_mmVCE_RB_WPTR3,4,2             ; @mmVCE_RB_WPTR3
	.comm	_mmGRBM_GFX_INDEX_DEFAULT,4,2   ; @mmGRBM_GFX_INDEX_DEFAULT
	.no_dead_strip	_vce_v3_0_ring_set_wptr
.subsections_via_symbols
