	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function meson_vclk_set
_meson_vclk_set:                        ## @meson_vclk_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%r9d, -92(%rbp)                 ## 4-byte Spill
	movl	%r8d, %ebx
	movl	%ecx, %r12d
	movl	%edx, %r14d
	movl	%esi, -80(%rbp)                 ## 4-byte Spill
	movq	%rdi, %r15
	movl	48(%rbp), %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movl	40(%rbp), %eax
	movl	%eax, -60(%rbp)                 ## 4-byte Spill
	movl	32(%rbp), %eax
	movq	%rax, -88(%rbp)                 ## 8-byte Spill
	movl	24(%rbp), %eax
	movq	%rax, -72(%rbp)                 ## 8-byte Spill
	movl	16(%rbp), %eax
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	movl	(%rdi), %edi
	movq	_CTS_HDMI_SYS_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_HHI_HDMI_CLK_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	(%r15), %edi
	movl	(%r13), %esi
	movq	_CTS_HDMI_SYS_DIV_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	(%r15), %edi
	movl	(%r13), %esi
	movq	_CTS_HDMI_SYS_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	%r12d, -48(%rbp)                ## 4-byte Spill
	movl	%r14d, -76(%rbp)                ## 4-byte Spill
	orl	%r14d, %r12d
	movl	%ebx, -52(%rbp)                 ## 4-byte Spill
	orl	%ebx, %r12d
	je	LBB0_6
## %bb.1:
	movl	-80(%rbp), %r12d                ## 4-byte Reload
	movq	_VPU_COMPATIBLE_GXBB@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_7
## %bb.2:
	cmpl	$5940000, %r12d                 ## imm = 0x5AA320
	movq	-88(%rbp), %r13                 ## 8-byte Reload
	je	LBB0_13
## %bb.3:
	cmpl	$4320000, %r12d                 ## imm = 0x41EB00
	movl	-56(%rbp), %r14d                ## 4-byte Reload
	movq	-72(%rbp), %rbx                 ## 8-byte Reload
	je	LBB0_14
## %bb.4:
	xorl	%esi, %esi
	movl	$0, %edx
	cmpl	$2970000, %r12d                 ## imm = 0x2D5190
	movl	-52(%rbp), %r9d                 ## 4-byte Reload
	movl	-48(%rbp), %r8d                 ## 4-byte Reload
	jne	LBB0_16
## %bb.5:
	cmpl	$0, -44(%rbp)                   ## 4-byte Folded Reload
	movl	$3584, %eax                     ## imm = 0xE00
	movl	$3330, %edx                     ## imm = 0xD02
	cmovel	%eax, %edx
	movl	$61, %esi
	jmp	LBB0_16
LBB0_6:
	movq	%r15, %rdi
	movl	-80(%rbp), %esi                 ## 4-byte Reload
	callq	_meson_hdmi_pll_generic_set
	movq	-88(%rbp), %r13                 ## 8-byte Reload
	movl	-56(%rbp), %r14d                ## 4-byte Reload
	movq	-72(%rbp), %rbx                 ## 8-byte Reload
	jmp	LBB0_22
LBB0_7:
	movq	_VPU_COMPATIBLE_GXM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	movq	-88(%rbp), %r13                 ## 8-byte Reload
	jne	LBB0_9
## %bb.8:
	movq	_VPU_COMPATIBLE_GXL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_56
LBB0_9:
	cmpl	$5940000, %r12d                 ## imm = 0x5AA320
	je	LBB0_17
## %bb.10:
	xorl	%esi, %esi
	cmpl	$4320000, %r12d                 ## imm = 0x41EB00
	je	LBB0_18
## %bb.11:
	movl	$0, %edx
	cmpl	$2970000, %r12d                 ## imm = 0x2D5190
	movl	-56(%rbp), %r14d                ## 4-byte Reload
	movq	-72(%rbp), %rbx                 ## 8-byte Reload
	jne	LBB0_20
## %bb.12:
	cmpl	$0, -44(%rbp)                   ## 4-byte Folded Reload
	movl	$768, %eax                      ## imm = 0x300
	movl	$641, %edx                      ## imm = 0x281
	cmovel	%eax, %edx
	movl	$123, %esi
	jmp	LBB0_20
LBB0_13:
	cmpl	$0, -44(%rbp)                   ## 4-byte Folded Reload
	movl	$3072, %eax                     ## imm = 0xC00
	movl	$2565, %edx                     ## imm = 0xA05
	cmovel	%eax, %edx
	movl	$123, %esi
	movl	-56(%rbp), %r14d                ## 4-byte Reload
	movq	-72(%rbp), %rbx                 ## 8-byte Reload
	jmp	LBB0_15
LBB0_14:
	xorl	%esi, %esi
	movl	-44(%rbp), %eax                 ## 4-byte Reload
	testl	%eax, %eax
	sete	%sil
	movl	$3727, %edx                     ## imm = 0xE8F
	cmovel	%eax, %edx
	addl	$89, %esi
LBB0_15:
	movl	-52(%rbp), %r9d                 ## 4-byte Reload
	movl	-48(%rbp), %r8d                 ## 4-byte Reload
LBB0_16:
	movq	%r15, %rdi
	movl	-76(%rbp), %ecx                 ## 4-byte Reload
	jmp	LBB0_21
LBB0_17:
	cmpl	$0, -44(%rbp)                   ## 4-byte Folded Reload
	movl	$512, %eax                      ## imm = 0x200
	movl	$258, %edx                      ## imm = 0x102
	cmovel	%eax, %edx
	movl	$247, %esi
	jmp	LBB0_19
LBB0_18:
	movl	-44(%rbp), %eax                 ## 4-byte Reload
	testl	%eax, %eax
	sete	%sil
	movl	$839, %edx                      ## imm = 0x347
	cmovel	%eax, %edx
	addl	$179, %esi
LBB0_19:
	movl	-56(%rbp), %r14d                ## 4-byte Reload
	movq	-72(%rbp), %rbx                 ## 8-byte Reload
LBB0_20:
	movq	%r15, %rdi
	movl	-76(%rbp), %ecx                 ## 4-byte Reload
	movl	-48(%rbp), %r8d                 ## 4-byte Reload
	movl	-52(%rbp), %r9d                 ## 4-byte Reload
LBB0_21:
	callq	_meson_hdmi_pll_set_params
LBB0_22:
	movq	%r15, %rdi
	movl	-92(%rbp), %esi                 ## 4-byte Reload
	callq	_meson_vid_pll_set
	movl	(%r15), %edi
	movq	_HHI_VID_CLK_CNTL@GOTPCREL(%rip), %rax
	movq	%rax, %r12
	movl	(%rax), %esi
	movq	_VCLK_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	(%r15), %edi
	movq	_HHI_VID_CLK_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_VCLK_DIV_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	decl	%r14d
	movl	%r14d, %ecx
	callq	_regmap_update_bits
	decl	%ebx
	cmpl	$11, %ebx
	ja	LBB0_31
## %bb.23:
	leaq	LJTI0_0(%rip), %rax
	movslq	(%rax,%rbx,4), %rcx
	addq	%rax, %rcx
	jmpq	*%rcx
LBB0_24:
	movl	(%r15), %edi
	movl	(%r12), %esi
	movq	_VCLK_DIV1_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r15), %edi
	movq	_HHI_HDMI_CLK_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_HDMI_TX_PIXEL_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
	jmp	LBB0_30
LBB0_25:
	movl	(%r15), %edi
	movl	(%r12), %esi
	movq	_VCLK_DIV2_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r15), %edi
	movq	_HHI_HDMI_CLK_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_HDMI_TX_PIXEL_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_HDMI_TX_PIXEL_SEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$1, %eax
	jmp	LBB0_29
LBB0_26:
	movl	(%r15), %edi
	movl	(%r12), %esi
	movq	_VCLK_DIV4_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r15), %edi
	movq	_HHI_HDMI_CLK_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_HDMI_TX_PIXEL_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_HDMI_TX_PIXEL_SEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %eax
	jmp	LBB0_29
LBB0_27:
	movl	(%r15), %edi
	movl	(%r12), %esi
	movq	_VCLK_DIV6_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r15), %edi
	movq	_HHI_HDMI_CLK_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_HDMI_TX_PIXEL_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_HDMI_TX_PIXEL_SEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$3, %eax
	jmp	LBB0_29
LBB0_28:
	movl	(%r15), %edi
	movl	(%r12), %esi
	movq	_VCLK_DIV12_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r15), %edi
	movq	_HHI_HDMI_CLK_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_HDMI_TX_PIXEL_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_HDMI_TX_PIXEL_SEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$4, %eax
LBB0_29:
	shll	%cl, %eax
	movl	%eax, %ecx
LBB0_30:
	callq	_regmap_update_bits
LBB0_31:
	movl	(%r15), %edi
	movq	_HHI_VID_CLK_CNTL2@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	_HDMI_TX_PIXEL_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	decl	%r13d
	cmpl	$11, %r13d
	ja	LBB0_37
## %bb.32:
	leaq	LJTI0_1(%rip), %rax
	movslq	(%rax,%r13,4), %rcx
	addq	%rax, %rcx
	jmpq	*%rcx
LBB0_33:
	movl	(%r15), %edi
	movl	(%r12), %esi
	movq	_VCLK_DIV1_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r15), %edi
	movq	_HHI_VID_CLK_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	cmpl	$0, -60(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_47
## %bb.34:
	movq	_CTS_ENCI_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
	jmp	LBB0_45
LBB0_35:
	movl	(%r15), %edi
	movl	(%r12), %esi
	movq	_VCLK_DIV2_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r15), %edi
	movq	_HHI_VID_CLK_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	cmpl	$0, -60(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_48
## %bb.36:
	movq	_CTS_ENCI_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_CTS_ENCI_SEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$1, %eax
	jmp	LBB0_44
LBB0_37:
	cmpl	$0, -60(%rbp)                   ## 4-byte Folded Reload
	jne	LBB0_46
	jmp	LBB0_54
LBB0_38:
	movl	(%r15), %edi
	movl	(%r12), %esi
	movq	_VCLK_DIV4_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r15), %edi
	movq	_HHI_VID_CLK_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	cmpl	$0, -60(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_49
## %bb.39:
	movq	_CTS_ENCI_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_CTS_ENCI_SEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %eax
	jmp	LBB0_44
LBB0_40:
	movl	(%r15), %edi
	movl	(%r12), %esi
	movq	_VCLK_DIV6_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r15), %edi
	movq	_HHI_VID_CLK_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	cmpl	$0, -60(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_50
## %bb.41:
	movq	_CTS_ENCI_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_CTS_ENCI_SEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$3, %eax
	jmp	LBB0_44
LBB0_42:
	movl	(%r15), %edi
	movl	(%r12), %esi
	movq	_VCLK_DIV12_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r15), %edi
	movq	_HHI_VID_CLK_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	cmpl	$0, -60(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_51
## %bb.43:
	movq	_CTS_ENCI_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_CTS_ENCI_SEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$4, %eax
LBB0_44:
	shll	%cl, %eax
	movl	%eax, %ecx
LBB0_45:
	callq	_regmap_update_bits
LBB0_46:
	movl	(%r15), %edi
	movl	(%r14), %esi
	movq	_CTS_ENCI_EN@GOTPCREL(%rip), %rax
	jmp	LBB0_55
LBB0_47:
	movq	_CTS_ENCP_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
	jmp	LBB0_53
LBB0_48:
	movq	_CTS_ENCP_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_CTS_ENCP_SEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$1, %eax
	jmp	LBB0_52
LBB0_49:
	movq	_CTS_ENCP_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_CTS_ENCP_SEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %eax
	jmp	LBB0_52
LBB0_50:
	movq	_CTS_ENCP_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_CTS_ENCP_SEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$3, %eax
	jmp	LBB0_52
LBB0_51:
	movq	_CTS_ENCP_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_CTS_ENCP_SEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$4, %eax
LBB0_52:
	shll	%cl, %eax
	movl	%eax, %ecx
LBB0_53:
	callq	_regmap_update_bits
LBB0_54:
	movl	(%r15), %edi
	movl	(%r14), %esi
	movq	_CTS_ENCP_EN@GOTPCREL(%rip), %rax
LBB0_55:
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r15), %edi
	movl	(%r12), %esi
	movq	_VCLK_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_regmap_update_bits             ## TAILCALL
LBB0_56:
	movq	_VPU_COMPATIBLE_G12A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	movl	-56(%rbp), %r14d                ## 4-byte Reload
	movq	-72(%rbp), %rbx                 ## 8-byte Reload
	je	LBB0_22
## %bb.57:
	cmpl	$5940000, %r12d                 ## imm = 0x5AA320
	je	LBB0_61
## %bb.58:
	xorl	%esi, %esi
	cmpl	$4320000, %r12d                 ## imm = 0x41EB00
	je	LBB0_62
## %bb.59:
	movl	$0, %edx
	cmpl	$2970000, %r12d                 ## imm = 0x2D5190
	movl	-52(%rbp), %r9d                 ## 4-byte Reload
	movl	-48(%rbp), %r8d                 ## 4-byte Reload
	jne	LBB0_16
## %bb.60:
	cmpl	$0, -44(%rbp)                   ## 4-byte Folded Reload
	movl	$98304, %eax                    ## imm = 0x18000
	movl	$82100, %edx                    ## imm = 0x140B4
	cmovel	%eax, %edx
	movl	$123, %esi
	jmp	LBB0_16
LBB0_61:
	cmpl	$0, -44(%rbp)                   ## 4-byte Folded Reload
	movl	$65536, %eax                    ## imm = 0x10000
	movl	$33096, %edx                    ## imm = 0x8148
	cmovel	%eax, %edx
	movl	$247, %esi
	jmp	LBB0_15
LBB0_62:
	movl	-44(%rbp), %eax                 ## 4-byte Reload
	testl	%eax, %eax
	sete	%sil
	movl	$107502, %edx                   ## imm = 0x1A3EE
	cmovel	%eax, %edx
	addl	$179, %esi
	jmp	LBB0_15
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_24, LBB0_24-LJTI0_0
.set L0_0_set_25, LBB0_25-LJTI0_0
.set L0_0_set_31, LBB0_31-LJTI0_0
.set L0_0_set_26, LBB0_26-LJTI0_0
.set L0_0_set_27, LBB0_27-LJTI0_0
.set L0_0_set_28, LBB0_28-LJTI0_0
LJTI0_0:
	.long	L0_0_set_24
	.long	L0_0_set_25
	.long	L0_0_set_31
	.long	L0_0_set_26
	.long	L0_0_set_31
	.long	L0_0_set_27
	.long	L0_0_set_31
	.long	L0_0_set_31
	.long	L0_0_set_31
	.long	L0_0_set_31
	.long	L0_0_set_31
	.long	L0_0_set_28
.set L0_1_set_33, LBB0_33-LJTI0_1
.set L0_1_set_35, LBB0_35-LJTI0_1
.set L0_1_set_37, LBB0_37-LJTI0_1
.set L0_1_set_38, LBB0_38-LJTI0_1
.set L0_1_set_40, LBB0_40-LJTI0_1
.set L0_1_set_42, LBB0_42-LJTI0_1
LJTI0_1:
	.long	L0_1_set_33
	.long	L0_1_set_35
	.long	L0_1_set_37
	.long	L0_1_set_38
	.long	L0_1_set_37
	.long	L0_1_set_40
	.long	L0_1_set_37
	.long	L0_1_set_37
	.long	L0_1_set_37
	.long	L0_1_set_37
	.long	L0_1_set_37
	.long	L0_1_set_42
	.end_data_region
                                        ## -- End function
	.comm	_HHI_HDMI_CLK_CNTL,4,2          ## @HHI_HDMI_CLK_CNTL
	.comm	_CTS_HDMI_SYS_SEL_MASK,4,2      ## @CTS_HDMI_SYS_SEL_MASK
	.comm	_CTS_HDMI_SYS_DIV_MASK,4,2      ## @CTS_HDMI_SYS_DIV_MASK
	.comm	_CTS_HDMI_SYS_EN,4,2            ## @CTS_HDMI_SYS_EN
	.comm	_VPU_COMPATIBLE_GXBB,4,2        ## @VPU_COMPATIBLE_GXBB
	.comm	_VPU_COMPATIBLE_GXM,4,2         ## @VPU_COMPATIBLE_GXM
	.comm	_VPU_COMPATIBLE_GXL,4,2         ## @VPU_COMPATIBLE_GXL
	.comm	_VPU_COMPATIBLE_G12A,4,2        ## @VPU_COMPATIBLE_G12A
	.comm	_HHI_VID_CLK_CNTL,4,2           ## @HHI_VID_CLK_CNTL
	.comm	_VCLK_SEL_MASK,4,2              ## @VCLK_SEL_MASK
	.comm	_HHI_VID_CLK_DIV,4,2            ## @HHI_VID_CLK_DIV
	.comm	_VCLK_DIV_MASK,4,2              ## @VCLK_DIV_MASK
	.comm	_VCLK_DIV1_EN,4,2               ## @VCLK_DIV1_EN
	.comm	_HDMI_TX_PIXEL_SEL_MASK,4,2     ## @HDMI_TX_PIXEL_SEL_MASK
	.comm	_VCLK_DIV2_EN,4,2               ## @VCLK_DIV2_EN
	.comm	_HDMI_TX_PIXEL_SEL_SHIFT,4,2    ## @HDMI_TX_PIXEL_SEL_SHIFT
	.comm	_VCLK_DIV4_EN,4,2               ## @VCLK_DIV4_EN
	.comm	_VCLK_DIV6_EN,4,2               ## @VCLK_DIV6_EN
	.comm	_VCLK_DIV12_EN,4,2              ## @VCLK_DIV12_EN
	.comm	_HHI_VID_CLK_CNTL2,4,2          ## @HHI_VID_CLK_CNTL2
	.comm	_HDMI_TX_PIXEL_EN,4,2           ## @HDMI_TX_PIXEL_EN
	.comm	_CTS_ENCI_SEL_MASK,4,2          ## @CTS_ENCI_SEL_MASK
	.comm	_CTS_ENCP_SEL_MASK,4,2          ## @CTS_ENCP_SEL_MASK
	.comm	_CTS_ENCI_SEL_SHIFT,4,2         ## @CTS_ENCI_SEL_SHIFT
	.comm	_CTS_ENCP_SEL_SHIFT,4,2         ## @CTS_ENCP_SEL_SHIFT
	.comm	_CTS_ENCI_EN,4,2                ## @CTS_ENCI_EN
	.comm	_CTS_ENCP_EN,4,2                ## @CTS_ENCP_EN
	.comm	_VCLK_EN,4,2                    ## @VCLK_EN
	.no_dead_strip	_meson_vclk_set
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function meson_vclk_set
_meson_vclk_set:                        ; @meson_vclk_set
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x20, x7
	mov	x21, x6
	mov	x22, x5
	mov	x23, x4
	mov	x24, x3
	mov	x25, x2
	mov	x26, x1
	mov	x19, x0
	ldp	w8, w28, [x29, #20]
	str	w8, [sp, #8]                    ; 4-byte Folded Spill
	ldr	w8, [x29, #16]
	str	w8, [sp, #12]                   ; 4-byte Folded Spill
	ldr	w0, [x0]
Lloh0:
	adrp	x27, _HHI_HDMI_CLK_CNTL@GOTPAGE
Lloh1:
	ldr	x27, [x27, _HHI_HDMI_CLK_CNTL@GOTPAGEOFF]
	ldr	w1, [x27]
Lloh2:
	adrp	x8, _CTS_HDMI_SYS_SEL_MASK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _CTS_HDMI_SYS_SEL_MASK@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x27]
Lloh5:
	adrp	x8, _CTS_HDMI_SYS_DIV_MASK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _CTS_HDMI_SYS_DIV_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x27]
Lloh8:
	adrp	x8, _CTS_HDMI_SYS_EN@GOTPAGE
Lloh9:
	ldr	x8, [x8, _CTS_HDMI_SYS_EN@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	orr	w8, w24, w25
	orr	w8, w8, w23
	cbz	w8, LBB0_3
; %bb.1:
Lloh11:
	adrp	x8, _VPU_COMPATIBLE_GXBB@GOTPAGE
Lloh12:
	ldr	x8, [x8, _VPU_COMPATIBLE_GXBB@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_4
; %bb.2:
	mov	w8, #41760
	movk	w8, #90, lsl #16
	mov	w9, #2565
	mov	w10, #3072
	cmp	w28, #0
	csel	w9, w10, w9, eq
	mov	w10, #123
	mov	w11, #60160
	movk	w11, #65, lsl #16
	mov	w12, #89
	mov	w13, #3727
	cmp	w28, #0
	csel	w13, wzr, w13, eq
	cinc	w12, w12, eq
	mov	w14, #20880
	movk	w14, #45, lsl #16
	mov	w15, #3330
	mov	w16, #3584
	cmp	w28, #0
	csel	w15, w16, w15, eq
	mov	w16, #61
	b	LBB0_8
LBB0_3:
	mov	x0, x19
	mov	x1, x26
	bl	_meson_hdmi_pll_generic_set
	b	LBB0_9
LBB0_4:
Lloh14:
	adrp	x8, _VPU_COMPATIBLE_GXM@GOTPAGE
Lloh15:
	ldr	x8, [x8, _VPU_COMPATIBLE_GXM@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_meson_vpu_is_compatible
	cbnz	x0, LBB0_6
; %bb.5:
Lloh17:
	adrp	x8, _VPU_COMPATIBLE_GXL@GOTPAGE
Lloh18:
	ldr	x8, [x8, _VPU_COMPATIBLE_GXL@GOTPAGEOFF]
Lloh19:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_43
LBB0_6:
	mov	w8, #41760
	movk	w8, #90, lsl #16
	mov	w9, #258
	mov	w10, #512
	cmp	w28, #0
	csel	w9, w10, w9, eq
	mov	w10, #247
	mov	w11, #60160
	movk	w11, #65, lsl #16
	mov	w12, #179
	mov	w13, #839
	cmp	w28, #0
	csel	w13, wzr, w13, eq
	cinc	w12, w12, eq
	mov	w14, #20880
	movk	w14, #45, lsl #16
	mov	w15, #641
	mov	w16, #768
LBB0_7:
	cmp	w28, #0
	csel	w15, w16, w15, eq
	mov	w16, #123
LBB0_8:
	cmp	w26, w14
	csel	w14, wzr, w16, ne
	csel	w15, wzr, w15, ne
	cmp	w26, w11
	csel	w11, w12, w14, eq
	csel	w12, w13, w15, eq
	cmp	w26, w8
	csel	w1, w10, w11, eq
	csel	w2, w9, w12, eq
	mov	x0, x19
	mov	x3, x25
	mov	x4, x24
	mov	x5, x23
	bl	_meson_hdmi_pll_set_params
LBB0_9:
	mov	x0, x19
	mov	x1, x22
	bl	_meson_vid_pll_set
	ldr	w0, [x19]
Lloh20:
	adrp	x22, _HHI_VID_CLK_CNTL@GOTPAGE
Lloh21:
	ldr	x22, [x22, _HHI_VID_CLK_CNTL@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh22:
	adrp	x8, _VCLK_SEL_MASK@GOTPAGE
Lloh23:
	ldr	x8, [x8, _VCLK_SEL_MASK@GOTPAGEOFF]
Lloh24:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_regmap_update_bits
Lloh25:
	adrp	x23, _HHI_VID_CLK_DIV@GOTPAGE
Lloh26:
	ldr	x23, [x23, _HHI_VID_CLK_DIV@GOTPAGEOFF]
	ldr	w0, [x19]
	ldr	w1, [x23]
Lloh27:
	adrp	x8, _VCLK_DIV_MASK@GOTPAGE
Lloh28:
	ldr	x8, [x8, _VCLK_DIV_MASK@GOTPAGEOFF]
Lloh29:
	ldr	w2, [x8]
	sub	w3, w21, #1
	bl	_regmap_update_bits
	sub	w8, w20, #1
	cmp	w8, #11
	b.hi	LBB0_18
; %bb.10:
Lloh30:
	adrp	x9, lJTI0_0@PAGE
Lloh31:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_11
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_11:
	ldr	w0, [x19]
	ldr	w1, [x22]
Lloh32:
	adrp	x8, _VCLK_DIV1_EN@GOTPAGE
Lloh33:
	ldr	x8, [x8, _VCLK_DIV1_EN@GOTPAGEOFF]
Lloh34:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x27]
Lloh35:
	adrp	x8, _HDMI_TX_PIXEL_SEL_MASK@GOTPAGE
Lloh36:
	ldr	x8, [x8, _HDMI_TX_PIXEL_SEL_MASK@GOTPAGEOFF]
Lloh37:
	ldr	w2, [x8]
	mov	w3, #0
	b	LBB0_17
LBB0_12:
	ldr	w0, [x19]
	ldr	w1, [x22]
Lloh38:
	adrp	x8, _VCLK_DIV2_EN@GOTPAGE
Lloh39:
	ldr	x8, [x8, _VCLK_DIV2_EN@GOTPAGEOFF]
Lloh40:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x27]
Lloh41:
	adrp	x8, _HDMI_TX_PIXEL_SEL_MASK@GOTPAGE
Lloh42:
	ldr	x8, [x8, _HDMI_TX_PIXEL_SEL_MASK@GOTPAGEOFF]
Lloh43:
	ldr	w2, [x8]
Lloh44:
	adrp	x8, _HDMI_TX_PIXEL_SEL_SHIFT@GOTPAGE
Lloh45:
	ldr	x8, [x8, _HDMI_TX_PIXEL_SEL_SHIFT@GOTPAGEOFF]
Lloh46:
	ldr	w8, [x8]
	mov	w9, #1
	b	LBB0_16
LBB0_13:
	ldr	w0, [x19]
	ldr	w1, [x22]
Lloh47:
	adrp	x8, _VCLK_DIV4_EN@GOTPAGE
Lloh48:
	ldr	x8, [x8, _VCLK_DIV4_EN@GOTPAGEOFF]
Lloh49:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x27]
Lloh50:
	adrp	x8, _HDMI_TX_PIXEL_SEL_MASK@GOTPAGE
Lloh51:
	ldr	x8, [x8, _HDMI_TX_PIXEL_SEL_MASK@GOTPAGEOFF]
Lloh52:
	ldr	w2, [x8]
Lloh53:
	adrp	x8, _HDMI_TX_PIXEL_SEL_SHIFT@GOTPAGE
Lloh54:
	ldr	x8, [x8, _HDMI_TX_PIXEL_SEL_SHIFT@GOTPAGEOFF]
Lloh55:
	ldr	w8, [x8]
	mov	w9, #2
	b	LBB0_16
LBB0_14:
	ldr	w0, [x19]
	ldr	w1, [x22]
Lloh56:
	adrp	x8, _VCLK_DIV6_EN@GOTPAGE
Lloh57:
	ldr	x8, [x8, _VCLK_DIV6_EN@GOTPAGEOFF]
Lloh58:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x27]
Lloh59:
	adrp	x8, _HDMI_TX_PIXEL_SEL_MASK@GOTPAGE
Lloh60:
	ldr	x8, [x8, _HDMI_TX_PIXEL_SEL_MASK@GOTPAGEOFF]
Lloh61:
	ldr	w2, [x8]
Lloh62:
	adrp	x8, _HDMI_TX_PIXEL_SEL_SHIFT@GOTPAGE
Lloh63:
	ldr	x8, [x8, _HDMI_TX_PIXEL_SEL_SHIFT@GOTPAGEOFF]
Lloh64:
	ldr	w8, [x8]
	mov	w9, #3
	b	LBB0_16
LBB0_15:
	ldr	w0, [x19]
	ldr	w1, [x22]
Lloh65:
	adrp	x8, _VCLK_DIV12_EN@GOTPAGE
Lloh66:
	ldr	x8, [x8, _VCLK_DIV12_EN@GOTPAGEOFF]
Lloh67:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x27]
Lloh68:
	adrp	x8, _HDMI_TX_PIXEL_SEL_MASK@GOTPAGE
Lloh69:
	ldr	x8, [x8, _HDMI_TX_PIXEL_SEL_MASK@GOTPAGEOFF]
Lloh70:
	ldr	w2, [x8]
Lloh71:
	adrp	x8, _HDMI_TX_PIXEL_SEL_SHIFT@GOTPAGE
Lloh72:
	ldr	x8, [x8, _HDMI_TX_PIXEL_SEL_SHIFT@GOTPAGEOFF]
Lloh73:
	ldr	w8, [x8]
	mov	w9, #4
LBB0_16:
	lsl	w3, w9, w8
LBB0_17:
	bl	_regmap_update_bits
LBB0_18:
	ldr	w0, [x19]
Lloh74:
	adrp	x20, _HHI_VID_CLK_CNTL2@GOTPAGE
Lloh75:
	ldr	x20, [x20, _HHI_VID_CLK_CNTL2@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh76:
	adrp	x8, _HDMI_TX_PIXEL_EN@GOTPAGE
Lloh77:
	ldr	x8, [x8, _HDMI_TX_PIXEL_EN@GOTPAGEOFF]
Lloh78:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w8, [sp, #12]                   ; 4-byte Folded Reload
	sub	w8, w8, #1
	cmp	w8, #11
	b.hi	LBB0_24
; %bb.19:
Lloh79:
	adrp	x9, lJTI0_1@PAGE
Lloh80:
	add	x9, x9, lJTI0_1@PAGEOFF
	adr	x10, LBB0_20
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_20:
	ldr	w0, [x19]
	ldr	w1, [x22]
Lloh81:
	adrp	x8, _VCLK_DIV1_EN@GOTPAGE
Lloh82:
	ldr	x8, [x8, _VCLK_DIV1_EN@GOTPAGEOFF]
Lloh83:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x23]
	ldr	w8, [sp, #8]                    ; 4-byte Folded Reload
	cbz	w8, LBB0_34
; %bb.21:
Lloh84:
	adrp	x8, _CTS_ENCI_SEL_MASK@GOTPAGE
Lloh85:
	ldr	x8, [x8, _CTS_ENCI_SEL_MASK@GOTPAGEOFF]
Lloh86:
	ldr	w2, [x8]
	mov	w3, #0
	b	LBB0_32
LBB0_22:
	ldr	w0, [x19]
	ldr	w1, [x22]
Lloh87:
	adrp	x8, _VCLK_DIV2_EN@GOTPAGE
Lloh88:
	ldr	x8, [x8, _VCLK_DIV2_EN@GOTPAGEOFF]
Lloh89:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x23]
	ldr	w8, [sp, #8]                    ; 4-byte Folded Reload
	cbz	w8, LBB0_35
; %bb.23:
Lloh90:
	adrp	x8, _CTS_ENCI_SEL_MASK@GOTPAGE
Lloh91:
	ldr	x8, [x8, _CTS_ENCI_SEL_MASK@GOTPAGEOFF]
Lloh92:
	ldr	w2, [x8]
Lloh93:
	adrp	x8, _CTS_ENCI_SEL_SHIFT@GOTPAGE
Lloh94:
	ldr	x8, [x8, _CTS_ENCI_SEL_SHIFT@GOTPAGEOFF]
Lloh95:
	ldr	w8, [x8]
	mov	w9, #1
	b	LBB0_31
LBB0_24:
	ldr	w8, [sp, #8]                    ; 4-byte Folded Reload
	cbnz	w8, LBB0_33
	b	LBB0_41
LBB0_25:
	ldr	w0, [x19]
	ldr	w1, [x22]
Lloh96:
	adrp	x8, _VCLK_DIV4_EN@GOTPAGE
Lloh97:
	ldr	x8, [x8, _VCLK_DIV4_EN@GOTPAGEOFF]
Lloh98:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x23]
	ldr	w8, [sp, #8]                    ; 4-byte Folded Reload
	cbz	w8, LBB0_36
; %bb.26:
Lloh99:
	adrp	x8, _CTS_ENCI_SEL_MASK@GOTPAGE
Lloh100:
	ldr	x8, [x8, _CTS_ENCI_SEL_MASK@GOTPAGEOFF]
Lloh101:
	ldr	w2, [x8]
Lloh102:
	adrp	x8, _CTS_ENCI_SEL_SHIFT@GOTPAGE
Lloh103:
	ldr	x8, [x8, _CTS_ENCI_SEL_SHIFT@GOTPAGEOFF]
Lloh104:
	ldr	w8, [x8]
	mov	w9, #2
	b	LBB0_31
LBB0_27:
	ldr	w0, [x19]
	ldr	w1, [x22]
Lloh105:
	adrp	x8, _VCLK_DIV6_EN@GOTPAGE
Lloh106:
	ldr	x8, [x8, _VCLK_DIV6_EN@GOTPAGEOFF]
Lloh107:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x23]
	ldr	w8, [sp, #8]                    ; 4-byte Folded Reload
	cbz	w8, LBB0_37
; %bb.28:
Lloh108:
	adrp	x8, _CTS_ENCI_SEL_MASK@GOTPAGE
Lloh109:
	ldr	x8, [x8, _CTS_ENCI_SEL_MASK@GOTPAGEOFF]
Lloh110:
	ldr	w2, [x8]
Lloh111:
	adrp	x8, _CTS_ENCI_SEL_SHIFT@GOTPAGE
Lloh112:
	ldr	x8, [x8, _CTS_ENCI_SEL_SHIFT@GOTPAGEOFF]
Lloh113:
	ldr	w8, [x8]
	mov	w9, #3
	b	LBB0_31
LBB0_29:
	ldr	w0, [x19]
	ldr	w1, [x22]
Lloh114:
	adrp	x8, _VCLK_DIV12_EN@GOTPAGE
Lloh115:
	ldr	x8, [x8, _VCLK_DIV12_EN@GOTPAGEOFF]
Lloh116:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x23]
	ldr	w8, [sp, #8]                    ; 4-byte Folded Reload
	cbz	w8, LBB0_38
; %bb.30:
Lloh117:
	adrp	x8, _CTS_ENCI_SEL_MASK@GOTPAGE
Lloh118:
	ldr	x8, [x8, _CTS_ENCI_SEL_MASK@GOTPAGEOFF]
Lloh119:
	ldr	w2, [x8]
Lloh120:
	adrp	x8, _CTS_ENCI_SEL_SHIFT@GOTPAGE
Lloh121:
	ldr	x8, [x8, _CTS_ENCI_SEL_SHIFT@GOTPAGEOFF]
Lloh122:
	ldr	w8, [x8]
	mov	w9, #4
LBB0_31:
	lsl	w3, w9, w8
LBB0_32:
	bl	_regmap_update_bits
LBB0_33:
	ldr	w0, [x19]
	ldr	w1, [x20]
Lloh123:
	adrp	x8, _CTS_ENCI_EN@GOTPAGE
Lloh124:
	ldr	x8, [x8, _CTS_ENCI_EN@GOTPAGEOFF]
	b	LBB0_42
LBB0_34:
Lloh125:
	adrp	x8, _CTS_ENCP_SEL_MASK@GOTPAGE
Lloh126:
	ldr	x8, [x8, _CTS_ENCP_SEL_MASK@GOTPAGEOFF]
Lloh127:
	ldr	w2, [x8]
	mov	w3, #0
	b	LBB0_40
LBB0_35:
Lloh128:
	adrp	x8, _CTS_ENCP_SEL_MASK@GOTPAGE
Lloh129:
	ldr	x8, [x8, _CTS_ENCP_SEL_MASK@GOTPAGEOFF]
Lloh130:
	ldr	w2, [x8]
Lloh131:
	adrp	x8, _CTS_ENCP_SEL_SHIFT@GOTPAGE
Lloh132:
	ldr	x8, [x8, _CTS_ENCP_SEL_SHIFT@GOTPAGEOFF]
Lloh133:
	ldr	w8, [x8]
	mov	w9, #1
	b	LBB0_39
LBB0_36:
Lloh134:
	adrp	x8, _CTS_ENCP_SEL_MASK@GOTPAGE
Lloh135:
	ldr	x8, [x8, _CTS_ENCP_SEL_MASK@GOTPAGEOFF]
Lloh136:
	ldr	w2, [x8]
Lloh137:
	adrp	x8, _CTS_ENCP_SEL_SHIFT@GOTPAGE
Lloh138:
	ldr	x8, [x8, _CTS_ENCP_SEL_SHIFT@GOTPAGEOFF]
Lloh139:
	ldr	w8, [x8]
	mov	w9, #2
	b	LBB0_39
LBB0_37:
Lloh140:
	adrp	x8, _CTS_ENCP_SEL_MASK@GOTPAGE
Lloh141:
	ldr	x8, [x8, _CTS_ENCP_SEL_MASK@GOTPAGEOFF]
Lloh142:
	ldr	w2, [x8]
Lloh143:
	adrp	x8, _CTS_ENCP_SEL_SHIFT@GOTPAGE
Lloh144:
	ldr	x8, [x8, _CTS_ENCP_SEL_SHIFT@GOTPAGEOFF]
Lloh145:
	ldr	w8, [x8]
	mov	w9, #3
	b	LBB0_39
LBB0_38:
Lloh146:
	adrp	x8, _CTS_ENCP_SEL_MASK@GOTPAGE
Lloh147:
	ldr	x8, [x8, _CTS_ENCP_SEL_MASK@GOTPAGEOFF]
Lloh148:
	ldr	w2, [x8]
Lloh149:
	adrp	x8, _CTS_ENCP_SEL_SHIFT@GOTPAGE
Lloh150:
	ldr	x8, [x8, _CTS_ENCP_SEL_SHIFT@GOTPAGEOFF]
Lloh151:
	ldr	w8, [x8]
	mov	w9, #4
LBB0_39:
	lsl	w3, w9, w8
LBB0_40:
	bl	_regmap_update_bits
LBB0_41:
	ldr	w0, [x19]
	ldr	w1, [x20]
Lloh152:
	adrp	x8, _CTS_ENCP_EN@GOTPAGE
Lloh153:
	ldr	x8, [x8, _CTS_ENCP_EN@GOTPAGEOFF]
LBB0_42:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
Lloh154:
	adrp	x8, _VCLK_EN@GOTPAGE
Lloh155:
	ldr	x8, [x8, _VCLK_EN@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh156:
	ldr	w2, [x8]
	mov	x3, x2
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	b	_regmap_update_bits
LBB0_43:
Lloh157:
	adrp	x8, _VPU_COMPATIBLE_G12A@GOTPAGE
Lloh158:
	ldr	x8, [x8, _VPU_COMPATIBLE_G12A@GOTPAGEOFF]
Lloh159:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_9
; %bb.44:
	mov	w8, #41760
	movk	w8, #90, lsl #16
	mov	w9, #33096
	mov	w10, #65536
	cmp	w28, #0
	csel	w9, w10, w9, eq
	mov	w10, #247
	mov	w11, #60160
	movk	w11, #65, lsl #16
	mov	w12, #179
	mov	w13, #41966
	movk	w13, #1, lsl #16
	cmp	w28, #0
	csel	w13, wzr, w13, eq
	cinc	w12, w12, eq
	mov	w14, #20880
	movk	w14, #45, lsl #16
	mov	w15, #16564
	movk	w15, #1, lsl #16
	mov	w16, #98304
	b	LBB0_7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpAdd	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGot	Lloh74, Lloh75
	.loh AdrpAdd	Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh120, Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpLdrGot	Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh131, Lloh132, Lloh133
	.loh AdrpLdrGotLdr	Lloh128, Lloh129, Lloh130
	.loh AdrpLdrGotLdr	Lloh137, Lloh138, Lloh139
	.loh AdrpLdrGotLdr	Lloh134, Lloh135, Lloh136
	.loh AdrpLdrGotLdr	Lloh143, Lloh144, Lloh145
	.loh AdrpLdrGotLdr	Lloh140, Lloh141, Lloh142
	.loh AdrpLdrGotLdr	Lloh149, Lloh150, Lloh151
	.loh AdrpLdrGotLdr	Lloh146, Lloh147, Lloh148
	.loh AdrpLdrGot	Lloh152, Lloh153
	.loh AdrpLdrGotLdr	Lloh154, Lloh155, Lloh156
	.loh AdrpLdrGotLdr	Lloh157, Lloh158, Lloh159
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_11-LBB0_11)>>2
	.byte	(LBB0_12-LBB0_11)>>2
	.byte	(LBB0_18-LBB0_11)>>2
	.byte	(LBB0_13-LBB0_11)>>2
	.byte	(LBB0_18-LBB0_11)>>2
	.byte	(LBB0_14-LBB0_11)>>2
	.byte	(LBB0_18-LBB0_11)>>2
	.byte	(LBB0_18-LBB0_11)>>2
	.byte	(LBB0_18-LBB0_11)>>2
	.byte	(LBB0_18-LBB0_11)>>2
	.byte	(LBB0_18-LBB0_11)>>2
	.byte	(LBB0_15-LBB0_11)>>2
lJTI0_1:
	.byte	(LBB0_20-LBB0_20)>>2
	.byte	(LBB0_22-LBB0_20)>>2
	.byte	(LBB0_24-LBB0_20)>>2
	.byte	(LBB0_25-LBB0_20)>>2
	.byte	(LBB0_24-LBB0_20)>>2
	.byte	(LBB0_27-LBB0_20)>>2
	.byte	(LBB0_24-LBB0_20)>>2
	.byte	(LBB0_24-LBB0_20)>>2
	.byte	(LBB0_24-LBB0_20)>>2
	.byte	(LBB0_24-LBB0_20)>>2
	.byte	(LBB0_24-LBB0_20)>>2
	.byte	(LBB0_29-LBB0_20)>>2
                                        ; -- End function
	.comm	_HHI_HDMI_CLK_CNTL,4,2          ; @HHI_HDMI_CLK_CNTL
	.comm	_CTS_HDMI_SYS_SEL_MASK,4,2      ; @CTS_HDMI_SYS_SEL_MASK
	.comm	_CTS_HDMI_SYS_DIV_MASK,4,2      ; @CTS_HDMI_SYS_DIV_MASK
	.comm	_CTS_HDMI_SYS_EN,4,2            ; @CTS_HDMI_SYS_EN
	.comm	_VPU_COMPATIBLE_GXBB,4,2        ; @VPU_COMPATIBLE_GXBB
	.comm	_VPU_COMPATIBLE_GXM,4,2         ; @VPU_COMPATIBLE_GXM
	.comm	_VPU_COMPATIBLE_GXL,4,2         ; @VPU_COMPATIBLE_GXL
	.comm	_VPU_COMPATIBLE_G12A,4,2        ; @VPU_COMPATIBLE_G12A
	.comm	_HHI_VID_CLK_CNTL,4,2           ; @HHI_VID_CLK_CNTL
	.comm	_VCLK_SEL_MASK,4,2              ; @VCLK_SEL_MASK
	.comm	_HHI_VID_CLK_DIV,4,2            ; @HHI_VID_CLK_DIV
	.comm	_VCLK_DIV_MASK,4,2              ; @VCLK_DIV_MASK
	.comm	_VCLK_DIV1_EN,4,2               ; @VCLK_DIV1_EN
	.comm	_HDMI_TX_PIXEL_SEL_MASK,4,2     ; @HDMI_TX_PIXEL_SEL_MASK
	.comm	_VCLK_DIV2_EN,4,2               ; @VCLK_DIV2_EN
	.comm	_HDMI_TX_PIXEL_SEL_SHIFT,4,2    ; @HDMI_TX_PIXEL_SEL_SHIFT
	.comm	_VCLK_DIV4_EN,4,2               ; @VCLK_DIV4_EN
	.comm	_VCLK_DIV6_EN,4,2               ; @VCLK_DIV6_EN
	.comm	_VCLK_DIV12_EN,4,2              ; @VCLK_DIV12_EN
	.comm	_HHI_VID_CLK_CNTL2,4,2          ; @HHI_VID_CLK_CNTL2
	.comm	_HDMI_TX_PIXEL_EN,4,2           ; @HDMI_TX_PIXEL_EN
	.comm	_CTS_ENCI_SEL_MASK,4,2          ; @CTS_ENCI_SEL_MASK
	.comm	_CTS_ENCP_SEL_MASK,4,2          ; @CTS_ENCP_SEL_MASK
	.comm	_CTS_ENCI_SEL_SHIFT,4,2         ; @CTS_ENCI_SEL_SHIFT
	.comm	_CTS_ENCP_SEL_SHIFT,4,2         ; @CTS_ENCP_SEL_SHIFT
	.comm	_CTS_ENCI_EN,4,2                ; @CTS_ENCI_EN
	.comm	_CTS_ENCP_EN,4,2                ; @CTS_ENCP_EN
	.comm	_VCLK_EN,4,2                    ; @VCLK_EN
	.no_dead_strip	_meson_vclk_set
.subsections_via_symbols
