	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mmhub_v2_0_update_medium_grain_clock_gating
_mmhub_v2_0_update_medium_grain_clock_gating: ## @mmhub_v2_0_update_medium_grain_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %ebx
	movq	%rdi, %r12
	movq	_MMHUB@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movq	_mmMM_ATC_L2_MISC_CG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	%eax, %r15d
	movl	(%r13), %edi
	movq	_mmDAGB0_CNTL_MISC2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	%eax, %r14d
	testl	%ebx, %ebx
	je	LBB0_3
## %bb.1:
	movq	_AMD_CG_SUPPORT_MC_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r12)
	je	LBB0_3
## %bb.2:
	movq	_MM_ATC_L2_MISC_CG__ENABLE_MASK@GOTPCREL(%rip), %rax
	movq	_DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPCREL(%rip), %rcx
	movq	_DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	movl	(%rax), %ecx
	movq	_DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	orl	%r15d, %ecx
	movq	_DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	notl	%ebx
	andl	%r14d, %ebx
	cmpl	%ecx, %r15d
	jne	LBB0_5
	jmp	LBB0_6
LBB0_3:
	movq	_MM_ATC_L2_MISC_CG__ENABLE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	notl	%ecx
	andl	%r15d, %ecx
	movq	_DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPCREL(%rip), %rax
	movq	_DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPCREL(%rip), %rdx
	movq	_DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPCREL(%rip), %rsi
	movq	_DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPCREL(%rip), %rdi
	movq	_DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPCREL(%rip), %r8
	movq	_DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPCREL(%rip), %r9
	movl	(%rax), %ebx
	orl	%r14d, %ebx
	orl	(%rdx), %ebx
	orl	(%rsi), %ebx
	orl	(%rdi), %ebx
	orl	(%r8), %ebx
	orl	(%r9), %ebx
	cmpl	%ecx, %r15d
	je	LBB0_6
LBB0_5:
	movl	(%r13), %edi
	movq	_mmMM_ATC_L2_MISC_CG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
LBB0_6:
	cmpl	%ebx, %r14d
	jne	LBB0_8
## %bb.7:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_8:
	movl	(%r13), %edi
	movq	_mmDAGB0_CNTL_MISC2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	movl	%ebx, %ecx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_SOC15                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_MMHUB,4,2                      ## @MMHUB
	.comm	_mmMM_ATC_L2_MISC_CG,4,2        ## @mmMM_ATC_L2_MISC_CG
	.comm	_mmDAGB0_CNTL_MISC2,4,2         ## @mmDAGB0_CNTL_MISC2
	.comm	_AMD_CG_SUPPORT_MC_MGCG,4,2     ## @AMD_CG_SUPPORT_MC_MGCG
	.comm	_MM_ATC_L2_MISC_CG__ENABLE_MASK,4,2 ## @MM_ATC_L2_MISC_CG__ENABLE_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK
	.no_dead_strip	_mmhub_v2_0_update_medium_grain_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mmhub_v2_0_update_medium_grain_clock_gating
_mmhub_v2_0_update_medium_grain_clock_gating: ; @mmhub_v2_0_update_medium_grain_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x22, x1
	mov	x21, x0
Lloh0:
	adrp	x23, _MMHUB@GOTPAGE
Lloh1:
	ldr	x23, [x23, _MMHUB@GOTPAGEOFF]
	ldr	w0, [x23]
Lloh2:
	adrp	x25, _mmMM_ATC_L2_MISC_CG@GOTPAGE
Lloh3:
	ldr	x25, [x25, _mmMM_ATC_L2_MISC_CG@GOTPAGEOFF]
	ldr	w2, [x25]
	mov	w1, #0
	bl	_RREG32_SOC15
	mov	x20, x0
	ldr	w0, [x23]
Lloh4:
	adrp	x24, _mmDAGB0_CNTL_MISC2@GOTPAGE
Lloh5:
	ldr	x24, [x24, _mmDAGB0_CNTL_MISC2@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	w1, #0
	bl	_RREG32_SOC15
	mov	x19, x0
	cbz	w22, LBB0_3
; %bb.1:
	ldr	w8, [x21]
Lloh6:
	adrp	x9, _AMD_CG_SUPPORT_MC_MGCG@GOTPAGE
Lloh7:
	ldr	x9, [x9, _AMD_CG_SUPPORT_MC_MGCG@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_3
; %bb.2:
Lloh9:
	adrp	x8, _MM_ATC_L2_MISC_CG__ENABLE_MASK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _MM_ATC_L2_MISC_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh11:
	adrp	x9, _DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPAGE
Lloh12:
	ldr	x9, [x9, _DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
Lloh14:
	ldr	w9, [x9]
Lloh15:
	adrp	x10, _DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPAGE
Lloh16:
	ldr	x10, [x10, _DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh18:
	adrp	x10, _DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPAGE
Lloh19:
	ldr	x10, [x10, _DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPAGEOFF]
Lloh20:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh21:
	adrp	x10, _DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPAGE
Lloh22:
	ldr	x10, [x10, _DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPAGEOFF]
	orr	w3, w8, w20
Lloh23:
	ldr	w8, [x10]
	orr	w8, w9, w8
Lloh24:
	adrp	x9, _DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPAGE
Lloh25:
	ldr	x9, [x9, _DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh27:
	adrp	x9, _DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPAGE
Lloh28:
	ldr	x9, [x9, _DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w21, w19, w8
	cmp	w20, w3
	b.ne	LBB0_4
	b	LBB0_5
LBB0_3:
Lloh30:
	adrp	x8, _MM_ATC_L2_MISC_CG__ENABLE_MASK@GOTPAGE
Lloh31:
	ldr	x8, [x8, _MM_ATC_L2_MISC_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
	bic	w3, w20, w8
Lloh33:
	adrp	x8, _DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPAGE
Lloh34:
	ldr	x8, [x8, _DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
Lloh36:
	adrp	x9, _DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPAGE
Lloh37:
	ldr	x9, [x9, _DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPAGEOFF]
Lloh38:
	ldr	w9, [x9]
Lloh39:
	adrp	x10, _DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPAGE
Lloh40:
	ldr	x10, [x10, _DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPAGEOFF]
Lloh41:
	ldr	w10, [x10]
Lloh42:
	adrp	x11, _DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPAGE
Lloh43:
	ldr	x11, [x11, _DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPAGEOFF]
Lloh44:
	ldr	w11, [x11]
Lloh45:
	adrp	x12, _DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPAGE
Lloh46:
	ldr	x12, [x12, _DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPAGEOFF]
Lloh47:
	ldr	w12, [x12]
Lloh48:
	adrp	x13, _DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPAGE
Lloh49:
	ldr	x13, [x13, _DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPAGEOFF]
Lloh50:
	ldr	w13, [x13]
	orr	w8, w8, w19
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w21, w8, w13
	cmp	w20, w3
	b.eq	LBB0_5
LBB0_4:
	ldr	w0, [x23]
	ldr	w2, [x25]
	mov	w1, #0
	bl	_WREG32_SOC15
LBB0_5:
	cmp	w19, w21
	b.ne	LBB0_7
; %bb.6:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_7:
	ldr	w0, [x23]
	ldr	w2, [x24]
	mov	w1, #0
	mov	x3, x21
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_WREG32_SOC15
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh13
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.cfi_endproc
                                        ; -- End function
	.comm	_MMHUB,4,2                      ; @MMHUB
	.comm	_mmMM_ATC_L2_MISC_CG,4,2        ; @mmMM_ATC_L2_MISC_CG
	.comm	_mmDAGB0_CNTL_MISC2,4,2         ; @mmDAGB0_CNTL_MISC2
	.comm	_AMD_CG_SUPPORT_MC_MGCG,4,2     ; @AMD_CG_SUPPORT_MC_MGCG
	.comm	_MM_ATC_L2_MISC_CG__ENABLE_MASK,4,2 ; @MM_ATC_L2_MISC_CG__ENABLE_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK
	.no_dead_strip	_mmhub_v2_0_update_medium_grain_clock_gating
.subsections_via_symbols
