	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r100_hpd_set_polarity          ## -- Begin function r100_hpd_set_polarity
	.p2align	4, 0x90
_r100_hpd_set_polarity:                 ## @r100_hpd_set_polarity
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movl	%esi, %ebx
	callq	_r100_hpd_sense
	movl	%eax, %r14d
	cmpl	$128, %ebx
	je	LBB0_3
## %bb.1:
	cmpl	$129, %ebx
	jne	LBB0_5
## %bb.2:
	movq	_RADEON_FP_GEN_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_RADEON_FP_DETECT_INT_POL@GOTPCREL(%rip), %rcx
	jmp	LBB0_4
LBB0_3:
	movq	_RADEON_FP2_GEN_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_RADEON_FP2_DETECT_INT_POL@GOTPCREL(%rip), %rcx
LBB0_4:
	movl	(%rcx), %esi
	movl	%esi, %ecx
	notl	%ecx
	andl	%eax, %ecx
	orl	%eax, %esi
	testl	%r14d, %r14d
	cmovnel	%ecx, %esi
	movl	(%rbx), %edi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
LBB0_5:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_FP_GEN_CNTL,4,2         ## @RADEON_FP_GEN_CNTL
	.comm	_RADEON_FP_DETECT_INT_POL,4,2   ## @RADEON_FP_DETECT_INT_POL
	.comm	_RADEON_FP2_GEN_CNTL,4,2        ## @RADEON_FP2_GEN_CNTL
	.comm	_RADEON_FP2_DETECT_INT_POL,4,2  ## @RADEON_FP2_DETECT_INT_POL
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r100_hpd_set_polarity          ; -- Begin function r100_hpd_set_polarity
	.p2align	2
_r100_hpd_set_polarity:                 ; @r100_hpd_set_polarity
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x20, x1
	bl	_r100_hpd_sense
	mov	x19, x0
	cmp	w20, #128
	b.eq	LBB0_3
; %bb.1:
	cmp	w20, #129
	b.ne	LBB0_5
; %bb.2:
Lloh0:
	adrp	x20, _RADEON_FP_GEN_CNTL@GOTPAGE
Lloh1:
	ldr	x20, [x20, _RADEON_FP_GEN_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh2:
	adrp	x8, _RADEON_FP_DETECT_INT_POL@GOTPAGE
Lloh3:
	ldr	x8, [x8, _RADEON_FP_DETECT_INT_POL@GOTPAGEOFF]
	b	LBB0_4
LBB0_3:
Lloh4:
	adrp	x20, _RADEON_FP2_GEN_CNTL@GOTPAGE
Lloh5:
	ldr	x20, [x20, _RADEON_FP2_GEN_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh6:
	adrp	x8, _RADEON_FP2_DETECT_INT_POL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_FP2_DETECT_INT_POL@GOTPAGEOFF]
LBB0_4:
	ldr	w8, [x8]
	bic	w9, w0, w8
	orr	w8, w8, w0
	cmp	w19, #0
	csel	w1, w8, w9, eq
	ldr	w0, [x20]
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_WREG32
LBB0_5:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_FP_GEN_CNTL,4,2         ; @RADEON_FP_GEN_CNTL
	.comm	_RADEON_FP_DETECT_INT_POL,4,2   ; @RADEON_FP_DETECT_INT_POL
	.comm	_RADEON_FP2_GEN_CNTL,4,2        ; @RADEON_FP2_GEN_CNTL
	.comm	_RADEON_FP2_DETECT_INT_POL,4,2  ; @RADEON_FP2_DETECT_INT_POL
.subsections_via_symbols
