	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function pipe_reg_read
_pipe_reg_read:                         ## @pipe_reg_read
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r13
	movq	%rsi, -64(%rbp)                 ## 8-byte Spill
	movq	%rdi, %r14
	movq	_VIVS_HI_CLOCK_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_gpu_read
	movq	%rax, %rbx
	xorl	%r15d, %r15d
	cmpl	$0, (%r14)
	je	LBB0_1
## %bb.2:
	movq	%r13, -48(%rbp)                 ## 8-byte Spill
	xorl	%r13d, %r13d
	movq	%r14, -56(%rbp)                 ## 8-byte Spill
	movq	-56(%rbp), %r14                 ## 8-byte Reload
	.p2align	4, 0x90
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movq	_VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %r12
	notq	%r12
	andq	%rbx, %r12
	movl	%r15d, %edi
	callq	_VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE
	movq	%rax, %rbx
	orq	%r12, %rbx
	movq	_VIVS_HI_CLOCK_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movq	%rbx, %rdx
	callq	_gpu_write
	movq	-64(%rbp), %r12                 ## 8-byte Reload
	movl	4(%r12), %esi
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rdx
	movq	%r14, %rdi
	callq	_gpu_write
	movl	(%r12), %esi
	movq	%r14, %rdi
	callq	_gpu_read
	addq	%rax, %r13
	incl	%r15d
	cmpl	(%r14), %r15d
	jb	LBB0_3
	jmp	LBB0_4
LBB0_1:
	xorl	%r13d, %r13d
LBB0_4:
	movq	_VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %r15
	notq	%r15
	andq	%rbx, %r15
	xorl	%edi, %edi
	callq	_VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE
	orq	%rax, %r15
	movq	_VIVS_HI_CLOCK_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movq	%r15, %rdx
	callq	_gpu_write
	movq	%r13, %rax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_VIVS_HI_CLOCK_CONTROL,4,2      ## @VIVS_HI_CLOCK_CONTROL
	.comm	_VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK,8,3 ## @VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK
	.no_dead_strip	_pipe_reg_read
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function pipe_reg_read
_pipe_reg_read:                         ; @pipe_reg_read
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x2
	mov	x22, x1
	mov	x19, x0
Lloh0:
	adrp	x25, _VIVS_HI_CLOCK_CONTROL@GOTPAGE
Lloh1:
	ldr	x25, [x25, _VIVS_HI_CLOCK_CONTROL@GOTPAGEOFF]
	ldr	w1, [x25]
	bl	_gpu_read
	mov	x23, x0
	ldr	w8, [x19]
Lloh2:
	adrp	x26, _VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK@GOTPAGE
Lloh3:
	ldr	x26, [x26, _VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK@GOTPAGEOFF]
	cbz	w8, LBB0_3
; %bb.1:
	mov	w24, #0
	mov	x21, #0
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x26]
	bic	x23, x23, x8
	mov	x0, x24
	bl	_VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE
	orr	x23, x23, x0
	ldr	w1, [x25]
	mov	x0, x19
	mov	x2, x23
	bl	_gpu_write
	ldr	w1, [x22, #4]
	ldr	x2, [x20]
	mov	x0, x19
	bl	_gpu_write
	ldr	w1, [x22]
	mov	x0, x19
	bl	_gpu_read
	add	x21, x0, x21
	add	w24, w24, #1
	ldr	w8, [x19]
	cmp	w24, w8
	b.lo	LBB0_2
	b	LBB0_4
LBB0_3:
	mov	x21, #0
LBB0_4:
	ldr	x8, [x26]
	bic	x20, x23, x8
	mov	w0, #0
	bl	_VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE
	orr	x2, x20, x0
	ldr	w1, [x25]
	mov	x0, x19
	bl	_gpu_write
	mov	x0, x21
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_VIVS_HI_CLOCK_CONTROL,4,2      ; @VIVS_HI_CLOCK_CONTROL
	.comm	_VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK,8,3 ; @VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK
	.no_dead_strip	_pipe_reg_read
.subsections_via_symbols
