	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function smu_enable_umd_pstate
_smu_enable_umd_pstate:                 ## @smu_enable_umd_pstate
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	cmpl	$0, 4(%rdi)
	je	LBB0_2
## %bb.1:
	movq	%rdi, %rbx
	cmpl	$0, 20(%rdi)
	je	LBB0_2
## %bb.3:
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD@GOTPCREL(%rip), %rcx
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	(%rcx), %eax
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	8(%rbx), %edx
	movl	(%rsi), %ecx
	xorl	%r14d, %r14d
	testl	%eax, %edx
	je	LBB0_4
## %bb.6:
	testl	%eax, %ecx
	jne	LBB0_11
## %bb.7:
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_EXIT@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ecx
	jne	LBB0_9
## %bb.8:
	movl	12(%rbx), %eax
	movl	%eax, (%rsi)
LBB0_9:
	movl	$0, 16(%rbx)
	movl	(%rbx), %edi
	movq	_AMD_IP_BLOCK_TYPE_GFX@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_AMD_CG_STATE_GATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_amdgpu_device_ip_set_clockgating_state
	movl	(%rbx), %edi
	movl	(%r15), %esi
	movq	_AMD_PG_STATE_GATE@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_2:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r14d, %r14d
	subl	(%rax), %r14d
	jmp	LBB0_11
LBB0_4:
	testl	%eax, %ecx
	je	LBB0_11
## %bb.5:
	movl	%edx, 12(%rbx)
	movl	$1, 16(%rbx)
	movl	(%rbx), %edi
	movq	_AMD_IP_BLOCK_TYPE_GFX@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_AMD_CG_STATE_UNGATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_amdgpu_device_ip_set_clockgating_state
	movl	(%rbx), %edi
	movl	(%r15), %esi
	movq	_AMD_PG_STATE_UNGATE@GOTPCREL(%rip), %rax
LBB0_10:
	movl	(%rax), %edx
	callq	_amdgpu_device_ip_set_powergating_state
LBB0_11:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD,4,2 ## @AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK,4,2 ## @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK,4,2 ## @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,4,2 ## @AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_AMD_IP_BLOCK_TYPE_GFX,4,2      ## @AMD_IP_BLOCK_TYPE_GFX
	.comm	_AMD_CG_STATE_UNGATE,4,2        ## @AMD_CG_STATE_UNGATE
	.comm	_AMD_PG_STATE_UNGATE,4,2        ## @AMD_PG_STATE_UNGATE
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_EXIT,4,2 ## @AMD_DPM_FORCED_LEVEL_PROFILE_EXIT
	.comm	_AMD_CG_STATE_GATE,4,2          ## @AMD_CG_STATE_GATE
	.comm	_AMD_PG_STATE_GATE,4,2          ## @AMD_PG_STATE_GATE
	.no_dead_strip	_smu_enable_umd_pstate
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function smu_enable_umd_pstate
_smu_enable_umd_pstate:                 ; @smu_enable_umd_pstate
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	w8, [x0, #4]
	cbz	w8, LBB0_7
; %bb.1:
	mov	x19, x0
	ldr	w8, [x0, #20]
	cbz	w8, LBB0_7
; %bb.2:
Lloh0:
	adrp	x8, _AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK@GOTPAGE
Lloh4:
	ldr	x9, [x9, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh6:
	adrp	x9, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK@GOTPAGE
Lloh7:
	ldr	x9, [x9, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh9:
	adrp	x9, _AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPAGE
Lloh10:
	ldr	x9, [x9, _AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	orr	w11, w8, w9
	ldr	w8, [x19, #8]
	ldr	w9, [x1]
	and	w10, w9, w11
	tst	w8, w11
	b.eq	LBB0_8
; %bb.3:
	cbnz	w10, LBB0_11
; %bb.4:
Lloh12:
	adrp	x8, _AMD_DPM_FORCED_LEVEL_PROFILE_EXIT@GOTPAGE
Lloh13:
	ldr	x8, [x8, _AMD_DPM_FORCED_LEVEL_PROFILE_EXIT@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	cmp	w9, w8
	b.ne	LBB0_6
; %bb.5:
	ldr	w8, [x19, #12]
	str	w8, [x1]
LBB0_6:
	str	wzr, [x19, #16]
	ldr	w0, [x19]
Lloh15:
	adrp	x20, _AMD_IP_BLOCK_TYPE_GFX@GOTPAGE
Lloh16:
	ldr	x20, [x20, _AMD_IP_BLOCK_TYPE_GFX@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh17:
	adrp	x8, _AMD_CG_STATE_GATE@GOTPAGE
Lloh18:
	ldr	x8, [x8, _AMD_CG_STATE_GATE@GOTPAGEOFF]
Lloh19:
	ldr	w2, [x8]
	bl	_amdgpu_device_ip_set_clockgating_state
	ldr	w0, [x19]
	ldr	w1, [x20]
Lloh20:
	adrp	x8, _AMD_PG_STATE_GATE@GOTPAGE
Lloh21:
	ldr	x8, [x8, _AMD_PG_STATE_GATE@GOTPAGEOFF]
	b	LBB0_10
LBB0_7:
Lloh22:
	adrp	x8, _EINVAL@GOTPAGE
Lloh23:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_12
LBB0_8:
	cbz	w10, LBB0_11
; %bb.9:
	mov	w9, #1
	stp	w8, w9, [x19, #12]
	ldr	w0, [x19]
Lloh25:
	adrp	x20, _AMD_IP_BLOCK_TYPE_GFX@GOTPAGE
Lloh26:
	ldr	x20, [x20, _AMD_IP_BLOCK_TYPE_GFX@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh27:
	adrp	x8, _AMD_CG_STATE_UNGATE@GOTPAGE
Lloh28:
	ldr	x8, [x8, _AMD_CG_STATE_UNGATE@GOTPAGEOFF]
Lloh29:
	ldr	w2, [x8]
	bl	_amdgpu_device_ip_set_clockgating_state
	ldr	w0, [x19]
	ldr	w1, [x20]
Lloh30:
	adrp	x8, _AMD_PG_STATE_UNGATE@GOTPAGE
Lloh31:
	ldr	x8, [x8, _AMD_PG_STATE_UNGATE@GOTPAGEOFF]
LBB0_10:
	ldr	w2, [x8]
	bl	_amdgpu_device_ip_set_powergating_state
LBB0_11:
	mov	w0, #0
LBB0_12:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh25, Lloh26
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD,4,2 ; @AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK,4,2 ; @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK,4,2 ; @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,4,2 ; @AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_AMD_IP_BLOCK_TYPE_GFX,4,2      ; @AMD_IP_BLOCK_TYPE_GFX
	.comm	_AMD_CG_STATE_UNGATE,4,2        ; @AMD_CG_STATE_UNGATE
	.comm	_AMD_PG_STATE_UNGATE,4,2        ; @AMD_PG_STATE_UNGATE
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_EXIT,4,2 ; @AMD_DPM_FORCED_LEVEL_PROFILE_EXIT
	.comm	_AMD_CG_STATE_GATE,4,2          ; @AMD_CG_STATE_GATE
	.comm	_AMD_PG_STATE_GATE,4,2          ; @AMD_PG_STATE_GATE
	.no_dead_strip	_smu_enable_umd_pstate
.subsections_via_symbols
