	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v9_0_cp_compute_load_microcode
_gfx_v9_0_cp_compute_load_microcode:    ## @gfx_v9_0_cp_compute_load_microcode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	cmpq	$0, 8(%rdi)
	je	LBB0_1
## %bb.2:
	movq	%rdi, %r15
	xorl	%esi, %esi
	callq	_gfx_v9_0_cp_compute_enable
	movq	8(%r15), %rax
	movq	(%rax), %rbx
	movq	%rbx, -56(%rbp)                 ## 8-byte Spill
	leaq	8(%rbx), %rdi
	callq	_amdgpu_ucode_print_gfx_hdr
	movq	8(%r15), %rax
	movq	(%rax), %rax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movl	8(%rbx), %edi
	callq	_le32_to_cpu
	movq	%rax, %r14
	movq	_CP_CPC_IC_BASE_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	_VMID@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%edi, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%r12), %esi
	movq	_CACHE_POLICY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movq	_GC@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_mmCP_CPC_IC_BASE_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%rbx), %edi
	movq	_mmCP_CPC_IC_BASE_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	$-4096, %ecx                    ## imm = 0xF000
	andl	4(%r15), %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%rbx), %r12d
	movq	_mmCP_CPC_IC_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	%r15, -64(%rbp)                 ## 8-byte Spill
	movl	4(%r15), %edi
	callq	_upper_32_bits
	movl	%r12d, %edi
	xorl	%esi, %esi
	movl	%r13d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%rbx), %edi
	movq	_mmCP_MEC_ME1_UCODE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	-56(%rbp), %r15                 ## 8-byte Reload
	movl	(%r15), %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	cmpl	$0, 4(%r15)
	je	LBB0_5
## %bb.3:
	movq	%r15, %rcx
	addq	-48(%rbp), %r14                 ## 8-byte Folded Reload
	xorl	%r13d, %r13d
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%rbx), %r15d
	movq	_mmCP_MEC_ME1_UCODE_DATA@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movslq	(%rcx), %rax
	leaq	(%r14,%rax,4), %rdi
	movq	%r14, %r12
	movq	%rcx, %r14
	callq	_le32_to_cpup
	movl	%r15d, %edi
	xorl	%esi, %esi
	movl	-48(%rbp), %edx                 ## 4-byte Reload
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	%r14, %rcx
	movq	%r12, %r14
	incq	%r13
	movl	4(%rcx), %eax
	addq	$4, %r14
	cmpq	%rax, %r13
	jb	LBB0_4
LBB0_5:
	movl	(%rbx), %edi
	movq	_mmCP_MEC_ME1_UCODE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	-64(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	xorl	%eax, %eax
	jmp	LBB0_6
LBB0_1:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_6:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_CP_CPC_IC_BASE_CNTL,4,2        ## @CP_CPC_IC_BASE_CNTL
	.comm	_VMID,4,2                       ## @VMID
	.comm	_CACHE_POLICY,4,2               ## @CACHE_POLICY
	.comm	_GC,4,2                         ## @GC
	.comm	_mmCP_CPC_IC_BASE_CNTL,4,2      ## @mmCP_CPC_IC_BASE_CNTL
	.comm	_mmCP_CPC_IC_BASE_LO,4,2        ## @mmCP_CPC_IC_BASE_LO
	.comm	_mmCP_CPC_IC_BASE_HI,4,2        ## @mmCP_CPC_IC_BASE_HI
	.comm	_mmCP_MEC_ME1_UCODE_ADDR,4,2    ## @mmCP_MEC_ME1_UCODE_ADDR
	.comm	_mmCP_MEC_ME1_UCODE_DATA,4,2    ## @mmCP_MEC_ME1_UCODE_DATA
	.no_dead_strip	_gfx_v9_0_cp_compute_load_microcode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v9_0_cp_compute_load_microcode
_gfx_v9_0_cp_compute_load_microcode:    ; @gfx_v9_0_cp_compute_load_microcode
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	ldr	x8, [x0, #8]
	cbz	x8, LBB0_5
; %bb.1:
	mov	x19, x0
	mov	w1, #0
	bl	_gfx_v9_0_cp_compute_enable
	ldr	x8, [x19, #8]
	ldr	x23, [x8]
	add	x0, x23, #8
	bl	_amdgpu_ucode_print_gfx_hdr
	ldr	x8, [x19, #8]
	ldr	x25, [x8]
	ldr	w0, [x23, #8]
	bl	_le32_to_cpu
	mov	x20, x0
Lloh0:
	adrp	x21, _CP_CPC_IC_BASE_CNTL@GOTPAGE
Lloh1:
	ldr	x21, [x21, _CP_CPC_IC_BASE_CNTL@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh2:
	adrp	x8, _VMID@GOTPAGE
Lloh3:
	ldr	x8, [x8, _VMID@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	mov	w0, #0
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x21]
Lloh5:
	adrp	x8, _CACHE_POLICY@GOTPAGE
Lloh6:
	ldr	x8, [x8, _CACHE_POLICY@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	mov	x3, x0
Lloh8:
	adrp	x24, _GC@GOTPAGE
Lloh9:
	ldr	x24, [x24, _GC@GOTPAGEOFF]
	ldr	w0, [x24]
Lloh10:
	adrp	x8, _mmCP_CPC_IC_BASE_CNTL@GOTPAGE
Lloh11:
	ldr	x8, [x8, _mmCP_CPC_IC_BASE_CNTL@GOTPAGEOFF]
Lloh12:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh13:
	adrp	x8, _mmCP_CPC_IC_BASE_LO@GOTPAGE
Lloh14:
	ldr	x8, [x8, _mmCP_CPC_IC_BASE_LO@GOTPAGEOFF]
Lloh15:
	ldr	w2, [x8]
	ldr	w8, [x19, #4]
	and	w3, w8, #0xfffff000
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w21, [x24]
Lloh16:
	adrp	x8, _mmCP_CPC_IC_BASE_HI@GOTPAGE
Lloh17:
	ldr	x8, [x8, _mmCP_CPC_IC_BASE_HI@GOTPAGEOFF]
Lloh18:
	ldr	w22, [x8]
	ldr	w0, [x19, #4]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x21
	mov	w1, #0
	mov	x2, x22
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh19:
	adrp	x22, _mmCP_MEC_ME1_UCODE_ADDR@GOTPAGE
Lloh20:
	ldr	x22, [x22, _mmCP_MEC_ME1_UCODE_ADDR@GOTPAGEOFF]
	ldr	w2, [x22]
	ldr	w3, [x23]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w8, [x23, #4]
	cbz	w8, LBB0_4
; %bb.2:
	mov	x26, #0
	add	x25, x20, x25
Lloh21:
	adrp	x27, _mmCP_MEC_ME1_UCODE_DATA@GOTPAGE
Lloh22:
	ldr	x27, [x27, _mmCP_MEC_ME1_UCODE_DATA@GOTPAGEOFF]
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w20, [x24]
	ldr	w21, [x27]
	ldrsw	x8, [x23]
	add	x0, x25, x8, lsl #2
	bl	_le32_to_cpup
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	add	x26, x26, #1
	ldr	w8, [x23, #4]
	add	x25, x25, #4
	cmp	x26, x8
	b.lo	LBB0_3
LBB0_4:
	ldr	w0, [x24]
	ldr	w2, [x22]
	ldr	w3, [x19]
	mov	w1, #0
	bl	_WREG32_SOC15
	mov	w0, #0
	b	LBB0_6
LBB0_5:
Lloh23:
	adrp	x8, _EINVAL@GOTPAGE
Lloh24:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_6:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.cfi_endproc
                                        ; -- End function
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_CP_CPC_IC_BASE_CNTL,4,2        ; @CP_CPC_IC_BASE_CNTL
	.comm	_VMID,4,2                       ; @VMID
	.comm	_CACHE_POLICY,4,2               ; @CACHE_POLICY
	.comm	_GC,4,2                         ; @GC
	.comm	_mmCP_CPC_IC_BASE_CNTL,4,2      ; @mmCP_CPC_IC_BASE_CNTL
	.comm	_mmCP_CPC_IC_BASE_LO,4,2        ; @mmCP_CPC_IC_BASE_LO
	.comm	_mmCP_CPC_IC_BASE_HI,4,2        ; @mmCP_CPC_IC_BASE_HI
	.comm	_mmCP_MEC_ME1_UCODE_ADDR,4,2    ; @mmCP_MEC_ME1_UCODE_ADDR
	.comm	_mmCP_MEC_ME1_UCODE_DATA,4,2    ; @mmCP_MEC_ME1_UCODE_DATA
	.no_dead_strip	_gfx_v9_0_cp_compute_load_microcode
.subsections_via_symbols
