	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v2_0_enable_clock_gating
_vcn_v2_0_enable_clock_gating:          ## @vcn_v2_0_enable_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	_VCN@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movq	_mmUVD_CGC_CTRL@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_AMD_CG_SUPPORT_VCN_MGCG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	andl	(%rbx), %edx
	movq	_UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$1, %esi
	shll	%cl, %esi
	testl	%edx, %edx
	cmovel	%edx, %esi
	orl	%eax, %esi
	movq	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %dl
	movq	_UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$4, %eax
	shll	%cl, %eax
	btsl	%edx, %esi
	orl	%esi, %eax
	movl	(%r14), %edi
	movl	(%r15), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movl	(%r15), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__SYS_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__REGS_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__RBC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__MPC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__WCB_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__SCPU_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r14), %edi
	movl	(%r15), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_SUVD_CGC_CTRL@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_UVD_SUVD_CGC_CTRL__SRE_MODE_MASK@GOTPCREL(%rip), %rcx
	movq	_UVD_SUVD_CGC_CTRL__SIT_MODE_MASK@GOTPCREL(%rip), %rdx
	movq	_UVD_SUVD_CGC_CTRL__SMP_MODE_MASK@GOTPCREL(%rip), %rsi
	movq	_UVD_SUVD_CGC_CTRL__SCM_MODE_MASK@GOTPCREL(%rip), %rdi
	movq	_UVD_SUVD_CGC_CTRL__SDB_MODE_MASK@GOTPCREL(%rip), %rbx
	movq	_UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK@GOTPCREL(%rip), %r8
	movq	_UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK@GOTPCREL(%rip), %r9
	movq	_UVD_SUVD_CGC_CTRL__ENT_MODE_MASK@GOTPCREL(%rip), %r10
	movq	_UVD_SUVD_CGC_CTRL__IME_MODE_MASK@GOTPCREL(%rip), %r11
	movq	_UVD_SUVD_CGC_CTRL__SITE_MODE_MASK@GOTPCREL(%rip), %r12
	orl	(%rcx), %eax
	orl	(%rdx), %eax
	orl	(%rsi), %eax
	orl	(%rdi), %eax
	orl	(%rbx), %eax
	orl	(%r8), %eax
	orl	(%r9), %eax
	orl	(%r10), %eax
	orl	(%r11), %eax
	orl	(%r12), %eax
	movl	(%r14), %edi
	movl	(%r15), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_SOC15                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_VCN,4,2                        ## @VCN
	.comm	_mmUVD_CGC_CTRL,4,2             ## @mmUVD_CGC_CTRL
	.comm	_AMD_CG_SUPPORT_VCN_MGCG,4,2    ## @AMD_CG_SUPPORT_VCN_MGCG
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT,4,2 ## @UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT
	.comm	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT,4,2 ## @UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
	.comm	_UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT,4,2 ## @UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT
	.comm	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_RE_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_CM_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_IT_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_DB_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_MP_MODE_MASK
	.comm	_UVD_CGC_CTRL__SYS_MODE_MASK,4,2 ## @UVD_CGC_CTRL__SYS_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPEG2_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPEG2_MODE_MASK
	.comm	_UVD_CGC_CTRL__REGS_MODE_MASK,4,2 ## @UVD_CGC_CTRL__REGS_MODE_MASK
	.comm	_UVD_CGC_CTRL__RBC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__RBC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_MC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LMI_MC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LMI_UMC_MODE_MASK
	.comm	_UVD_CGC_CTRL__IDCT_MODE_MASK,4,2 ## @UVD_CGC_CTRL__IDCT_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPRD_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPRD_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LBSI_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LBSI_MODE_MASK
	.comm	_UVD_CGC_CTRL__LRBBM_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LRBBM_MODE_MASK
	.comm	_UVD_CGC_CTRL__WCB_MODE_MASK,4,2 ## @UVD_CGC_CTRL__WCB_MODE_MASK
	.comm	_UVD_CGC_CTRL__VCPU_MODE_MASK,4,2 ## @UVD_CGC_CTRL__VCPU_MODE_MASK
	.comm	_UVD_CGC_CTRL__SCPU_MODE_MASK,4,2 ## @UVD_CGC_CTRL__SCPU_MODE_MASK
	.comm	_mmUVD_SUVD_CGC_CTRL,4,2        ## @mmUVD_SUVD_CGC_CTRL
	.comm	_UVD_SUVD_CGC_CTRL__SRE_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SIT_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SMP_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SCM_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SDB_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__ENT_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__IME_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__IME_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SITE_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
	.no_dead_strip	_vcn_v2_0_enable_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v2_0_enable_clock_gating
_vcn_v2_0_enable_clock_gating:          ; @vcn_v2_0_enable_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x20, _VCN@GOTPAGE
Lloh1:
	ldr	x20, [x20, _VCN@GOTPAGEOFF]
	ldr	w0, [x20]
Lloh2:
	adrp	x21, _mmUVD_CGC_CTRL@GOTPAGE
Lloh3:
	ldr	x21, [x21, _mmUVD_CGC_CTRL@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_RREG32_SOC15
	ldr	w8, [x19]
Lloh4:
	adrp	x9, _AMD_CG_SUPPORT_VCN_MGCG@GOTPAGE
Lloh5:
	ldr	x9, [x9, _AMD_CG_SUPPORT_VCN_MGCG@GOTPAGEOFF]
Lloh6:
	ldr	w9, [x9]
Lloh7:
	adrp	x10, _UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPAGE
Lloh8:
	ldr	x10, [x10, _UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPAGEOFF]
Lloh9:
	ldr	w10, [x10]
	mov	w11, #1
	lsl	w10, w11, w10
	tst	w9, w8
	csel	w8, wzr, w10, eq
Lloh10:
	adrp	x9, _UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPAGE
Lloh11:
	ldr	x9, [x9, _UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPAGEOFF]
	orr	w8, w8, w0
Lloh12:
	ldr	w9, [x9]
	lsl	w9, w11, w9
	orr	w8, w8, w9
Lloh13:
	adrp	x9, _UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPAGE
Lloh14:
	ldr	x9, [x9, _UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	mov	w10, #4
	lsl	w9, w10, w9
	orr	w3, w8, w9
	ldr	w0, [x20]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x20]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh16:
	adrp	x8, _UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPAGE
Lloh17:
	ldr	x8, [x8, _UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPAGEOFF]
Lloh18:
	adrp	x9, _UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPAGE
Lloh19:
	ldr	x9, [x9, _UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
Lloh21:
	ldr	w9, [x9]
Lloh22:
	adrp	x10, _UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPAGE
Lloh23:
	ldr	x10, [x10, _UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPAGEOFF]
Lloh24:
	adrp	x11, _UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPAGE
Lloh25:
	ldr	x11, [x11, _UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPAGEOFF]
Lloh26:
	ldr	w10, [x10]
Lloh27:
	ldr	w11, [x11]
Lloh28:
	adrp	x12, _UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPAGE
Lloh29:
	ldr	x12, [x12, _UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPAGEOFF]
Lloh30:
	adrp	x13, _UVD_CGC_CTRL__SYS_MODE_MASK@GOTPAGE
Lloh31:
	ldr	x13, [x13, _UVD_CGC_CTRL__SYS_MODE_MASK@GOTPAGEOFF]
Lloh32:
	ldr	w12, [x12]
Lloh33:
	ldr	w13, [x13]
Lloh34:
	adrp	x14, _UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPAGE
Lloh35:
	ldr	x14, [x14, _UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPAGEOFF]
Lloh36:
	adrp	x15, _UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPAGE
Lloh37:
	ldr	x15, [x15, _UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPAGEOFF]
Lloh38:
	ldr	w14, [x14]
Lloh39:
	ldr	w15, [x15]
Lloh40:
	adrp	x16, _UVD_CGC_CTRL__REGS_MODE_MASK@GOTPAGE
Lloh41:
	ldr	x16, [x16, _UVD_CGC_CTRL__REGS_MODE_MASK@GOTPAGEOFF]
Lloh42:
	adrp	x17, _UVD_CGC_CTRL__RBC_MODE_MASK@GOTPAGE
Lloh43:
	ldr	x17, [x17, _UVD_CGC_CTRL__RBC_MODE_MASK@GOTPAGEOFF]
Lloh44:
	ldr	w16, [x16]
Lloh45:
	ldr	w17, [x17]
Lloh46:
	adrp	x1, _UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPAGE
Lloh47:
	ldr	x1, [x1, _UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPAGEOFF]
Lloh48:
	adrp	x2, _UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPAGE
Lloh49:
	ldr	x2, [x2, _UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPAGEOFF]
Lloh50:
	ldr	w1, [x1]
Lloh51:
	ldr	w2, [x2]
Lloh52:
	adrp	x3, _UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPAGE
Lloh53:
	ldr	x3, [x3, _UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPAGEOFF]
Lloh54:
	adrp	x4, _UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPAGE
Lloh55:
	ldr	x4, [x4, _UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPAGEOFF]
Lloh56:
	ldr	w3, [x3]
Lloh57:
	ldr	w4, [x4]
Lloh58:
	adrp	x5, _UVD_CGC_CTRL__MPC_MODE_MASK@GOTPAGE
Lloh59:
	ldr	x5, [x5, _UVD_CGC_CTRL__MPC_MODE_MASK@GOTPAGEOFF]
Lloh60:
	adrp	x6, _UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPAGE
Lloh61:
	ldr	x6, [x6, _UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPAGEOFF]
Lloh62:
	ldr	w5, [x5]
Lloh63:
	ldr	w6, [x6]
Lloh64:
	adrp	x7, _UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPAGE
Lloh65:
	ldr	x7, [x7, _UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPAGEOFF]
Lloh66:
	adrp	x19, _UVD_CGC_CTRL__WCB_MODE_MASK@GOTPAGE
Lloh67:
	ldr	x19, [x19, _UVD_CGC_CTRL__WCB_MODE_MASK@GOTPAGEOFF]
Lloh68:
	ldr	w7, [x7]
Lloh69:
	ldr	w19, [x19]
Lloh70:
	adrp	x22, _UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPAGE
Lloh71:
	ldr	x22, [x22, _UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPAGEOFF]
Lloh72:
	adrp	x23, _UVD_CGC_CTRL__SCPU_MODE_MASK@GOTPAGE
Lloh73:
	ldr	x23, [x23, _UVD_CGC_CTRL__SCPU_MODE_MASK@GOTPAGEOFF]
Lloh74:
	ldr	w22, [x22]
Lloh75:
	ldr	w23, [x23]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w8, w8, w13
	orr	w8, w8, w14
	orr	w8, w8, w15
	orr	w8, w8, w16
	orr	w8, w8, w17
	orr	w8, w8, w1
	orr	w8, w8, w2
	orr	w8, w8, w3
	orr	w8, w8, w4
	orr	w8, w8, w5
	orr	w8, w8, w6
	orr	w8, w8, w7
	orr	w8, w8, w19
	orr	w8, w8, w22
	orr	w3, w8, w23
	ldr	w0, [x20]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x20]
Lloh76:
	adrp	x19, _mmUVD_SUVD_CGC_CTRL@GOTPAGE
Lloh77:
	ldr	x19, [x19, _mmUVD_SUVD_CGC_CTRL@GOTPAGEOFF]
	ldr	w2, [x19]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh78:
	adrp	x8, _UVD_SUVD_CGC_CTRL__SRE_MODE_MASK@GOTPAGE
Lloh79:
	ldr	x8, [x8, _UVD_SUVD_CGC_CTRL__SRE_MODE_MASK@GOTPAGEOFF]
Lloh80:
	adrp	x9, _UVD_SUVD_CGC_CTRL__SIT_MODE_MASK@GOTPAGE
Lloh81:
	ldr	x9, [x9, _UVD_SUVD_CGC_CTRL__SIT_MODE_MASK@GOTPAGEOFF]
Lloh82:
	ldr	w8, [x8]
Lloh83:
	ldr	w9, [x9]
Lloh84:
	adrp	x10, _UVD_SUVD_CGC_CTRL__SMP_MODE_MASK@GOTPAGE
Lloh85:
	ldr	x10, [x10, _UVD_SUVD_CGC_CTRL__SMP_MODE_MASK@GOTPAGEOFF]
Lloh86:
	adrp	x11, _UVD_SUVD_CGC_CTRL__SCM_MODE_MASK@GOTPAGE
Lloh87:
	ldr	x11, [x11, _UVD_SUVD_CGC_CTRL__SCM_MODE_MASK@GOTPAGEOFF]
Lloh88:
	ldr	w10, [x10]
Lloh89:
	ldr	w11, [x11]
Lloh90:
	adrp	x12, _UVD_SUVD_CGC_CTRL__SDB_MODE_MASK@GOTPAGE
Lloh91:
	ldr	x12, [x12, _UVD_SUVD_CGC_CTRL__SDB_MODE_MASK@GOTPAGEOFF]
Lloh92:
	adrp	x13, _UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK@GOTPAGE
Lloh93:
	ldr	x13, [x13, _UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK@GOTPAGEOFF]
Lloh94:
	ldr	w12, [x12]
Lloh95:
	ldr	w13, [x13]
Lloh96:
	adrp	x14, _UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK@GOTPAGE
Lloh97:
	ldr	x14, [x14, _UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK@GOTPAGEOFF]
Lloh98:
	adrp	x15, _UVD_SUVD_CGC_CTRL__ENT_MODE_MASK@GOTPAGE
Lloh99:
	ldr	x15, [x15, _UVD_SUVD_CGC_CTRL__ENT_MODE_MASK@GOTPAGEOFF]
Lloh100:
	ldr	w14, [x14]
Lloh101:
	ldr	w15, [x15]
Lloh102:
	adrp	x16, _UVD_SUVD_CGC_CTRL__IME_MODE_MASK@GOTPAGE
Lloh103:
	ldr	x16, [x16, _UVD_SUVD_CGC_CTRL__IME_MODE_MASK@GOTPAGEOFF]
Lloh104:
	adrp	x17, _UVD_SUVD_CGC_CTRL__SITE_MODE_MASK@GOTPAGE
Lloh105:
	ldr	x17, [x17, _UVD_SUVD_CGC_CTRL__SITE_MODE_MASK@GOTPAGEOFF]
Lloh106:
	ldr	w16, [x16]
Lloh107:
	ldr	w17, [x17]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w8, w8, w13
	orr	w8, w8, w14
	orr	w8, w8, w15
	orr	w8, w8, w16
	orr	w3, w8, w17
	ldr	w0, [x20]
	ldr	w2, [x19]
	mov	w1, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_WREG32_SOC15
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh106
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh100
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh94
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh88
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh82
	.loh AdrpLdrGot	Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh74
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh68
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh62
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh56
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh50
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh44
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh38
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh32
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh26
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh20
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_VCN,4,2                        ; @VCN
	.comm	_mmUVD_CGC_CTRL,4,2             ; @mmUVD_CGC_CTRL
	.comm	_AMD_CG_SUPPORT_VCN_MGCG,4,2    ; @AMD_CG_SUPPORT_VCN_MGCG
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT,4,2 ; @UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT
	.comm	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT,4,2 ; @UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
	.comm	_UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT,4,2 ; @UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT
	.comm	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_RE_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_CM_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_IT_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_DB_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_MP_MODE_MASK
	.comm	_UVD_CGC_CTRL__SYS_MODE_MASK,4,2 ; @UVD_CGC_CTRL__SYS_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPEG2_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPEG2_MODE_MASK
	.comm	_UVD_CGC_CTRL__REGS_MODE_MASK,4,2 ; @UVD_CGC_CTRL__REGS_MODE_MASK
	.comm	_UVD_CGC_CTRL__RBC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__RBC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_MC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LMI_MC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LMI_UMC_MODE_MASK
	.comm	_UVD_CGC_CTRL__IDCT_MODE_MASK,4,2 ; @UVD_CGC_CTRL__IDCT_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPRD_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPRD_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LBSI_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LBSI_MODE_MASK
	.comm	_UVD_CGC_CTRL__LRBBM_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LRBBM_MODE_MASK
	.comm	_UVD_CGC_CTRL__WCB_MODE_MASK,4,2 ; @UVD_CGC_CTRL__WCB_MODE_MASK
	.comm	_UVD_CGC_CTRL__VCPU_MODE_MASK,4,2 ; @UVD_CGC_CTRL__VCPU_MODE_MASK
	.comm	_UVD_CGC_CTRL__SCPU_MODE_MASK,4,2 ; @UVD_CGC_CTRL__SCPU_MODE_MASK
	.comm	_mmUVD_SUVD_CGC_CTRL,4,2        ; @mmUVD_SUVD_CGC_CTRL
	.comm	_UVD_SUVD_CGC_CTRL__SRE_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SIT_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SMP_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SCM_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SDB_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__ENT_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__IME_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__IME_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SITE_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
	.no_dead_strip	_vcn_v2_0_enable_clock_gating
.subsections_via_symbols
