	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v6_0_enable_mgcg
_gfx_v6_0_enable_mgcg:                  ## @gfx_v6_0_enable_mgcg
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	testl	%esi, %esi
	je	LBB0_11
## %bb.1:
	movq	_AMD_CG_SUPPORT_GFX_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r15)
	je	LBB0_11
## %bb.2:
	movq	_mmCGTS_SM_CTRL_REG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	cmpl	$-1768685056, %eax              ## imm = 0x96940200
	je	LBB0_4
## %bb.3:
	movl	(%rbx), %edi
	movl	$-1768685056, %esi              ## imm = 0x96940200
	callq	_WREG32
LBB0_4:
	movq	_AMD_CG_SUPPORT_GFX_CP_LS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r15)
	je	LBB0_7
## %bb.5:
	movq	_mmCP_MEM_SLP_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	%eax, %esi
	cmpl	%esi, %eax
	je	LBB0_7
## %bb.6:
	movl	(%rbx), %edi
	callq	_WREG32
LBB0_7:
	movq	_mmRLC_CGTT_MGCG_OVERRIDE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movl	%eax, %esi
	andl	$-64, %esi
	cmpl	%esi, %eax
	je	LBB0_9
## %bb.8:
	movl	(%rbx), %edi
	callq	_WREG32
LBB0_9:
	movq	%r15, %rdi
	callq	_gfx_v6_0_halt_rlc
	movl	%eax, %r14d
	movq	_mmRLC_SERDES_WR_MASTER_MASK_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$-1, %esi
	callq	_WREG32
	movq	_mmRLC_SERDES_WR_MASTER_MASK_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$-1, %esi
	callq	_WREG32
	movq	_mmRLC_SERDES_WR_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$13631743, %esi                 ## imm = 0xD000FF
	callq	_WREG32
	movq	%r15, %rdi
	movl	%r14d, %esi
	jmp	LBB0_10
LBB0_11:
	movq	_mmRLC_CGTT_MGCG_OVERRIDE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movl	%eax, %esi
	orl	$3, %esi
	cmpl	%esi, %eax
	je	LBB0_13
## %bb.12:
	movl	(%rbx), %edi
	callq	_WREG32
LBB0_13:
	movq	_mmCP_MEM_SLP_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%eax, %ecx
	je	LBB0_15
## %bb.14:
	notl	%ecx
	andl	%ecx, %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
LBB0_15:
	movq	_mmCGTS_SM_CTRL_REG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK@GOTPCREL(%rip), %rcx
	movq	_CGTS_SM_CTRL_REG__OVERRIDE_MASK@GOTPCREL(%rip), %rdx
	movl	(%rcx), %esi
	orl	%eax, %esi
	orl	(%rdx), %esi
	cmpl	%esi, %eax
	je	LBB0_17
## %bb.16:
	movl	(%rbx), %edi
	callq	_WREG32
LBB0_17:
	movq	%r15, %rdi
	callq	_gfx_v6_0_halt_rlc
	movl	%eax, %ebx
	movq	_mmRLC_SERDES_WR_MASTER_MASK_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$-1, %esi
	callq	_WREG32
	movq	_mmRLC_SERDES_WR_MASTER_MASK_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$-1, %esi
	callq	_WREG32
	movq	_mmRLC_SERDES_WR_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$14680319, %esi                 ## imm = 0xE000FF
	callq	_WREG32
	movq	%r15, %rdi
	movl	%ebx, %esi
LBB0_10:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_gfx_v6_0_update_rlc            ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_CG_SUPPORT_GFX_MGCG,4,2    ## @AMD_CG_SUPPORT_GFX_MGCG
	.comm	_mmCGTS_SM_CTRL_REG,4,2         ## @mmCGTS_SM_CTRL_REG
	.comm	_AMD_CG_SUPPORT_GFX_CP_LS,4,2   ## @AMD_CG_SUPPORT_GFX_CP_LS
	.comm	_mmCP_MEM_SLP_CNTL,4,2          ## @mmCP_MEM_SLP_CNTL
	.comm	_CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK,4,2 ## @CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK
	.comm	_mmRLC_CGTT_MGCG_OVERRIDE,4,2   ## @mmRLC_CGTT_MGCG_OVERRIDE
	.comm	_mmRLC_SERDES_WR_MASTER_MASK_0,4,2 ## @mmRLC_SERDES_WR_MASTER_MASK_0
	.comm	_mmRLC_SERDES_WR_MASTER_MASK_1,4,2 ## @mmRLC_SERDES_WR_MASTER_MASK_1
	.comm	_mmRLC_SERDES_WR_CTRL,4,2       ## @mmRLC_SERDES_WR_CTRL
	.comm	_CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK,4,2 ## @CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK
	.comm	_CGTS_SM_CTRL_REG__OVERRIDE_MASK,4,2 ## @CGTS_SM_CTRL_REG__OVERRIDE_MASK
	.no_dead_strip	_gfx_v6_0_enable_mgcg
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v6_0_enable_mgcg
_gfx_v6_0_enable_mgcg:                  ; @gfx_v6_0_enable_mgcg
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	cbz	w1, LBB0_10
; %bb.1:
	ldr	w8, [x19]
Lloh0:
	adrp	x9, _AMD_CG_SUPPORT_GFX_MGCG@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_CG_SUPPORT_GFX_MGCG@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_10
; %bb.2:
	mov	w21, #512
	movk	w21, #38548, lsl #16
Lloh3:
	adrp	x20, _mmCGTS_SM_CTRL_REG@GOTPAGE
Lloh4:
	ldr	x20, [x20, _mmCGTS_SM_CTRL_REG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	cmp	w0, w21
	b.eq	LBB0_4
; %bb.3:
	ldr	w0, [x20]
	mov	w1, #512
	movk	w1, #38548, lsl #16
	bl	_WREG32
LBB0_4:
	ldr	w8, [x19]
Lloh5:
	adrp	x9, _AMD_CG_SUPPORT_GFX_CP_LS@GOTPAGE
Lloh6:
	ldr	x9, [x9, _AMD_CG_SUPPORT_GFX_CP_LS@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_7
; %bb.5:
Lloh8:
	adrp	x20, _mmCP_MEM_SLP_CNTL@GOTPAGE
Lloh9:
	ldr	x20, [x20, _mmCP_MEM_SLP_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh10:
	adrp	x8, _CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPAGE
Lloh11:
	ldr	x8, [x8, _CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	orr	w1, w8, w0
	cmp	w0, w1
	b.eq	LBB0_7
; %bb.6:
	ldr	w0, [x20]
	bl	_WREG32
LBB0_7:
Lloh13:
	adrp	x20, _mmRLC_CGTT_MGCG_OVERRIDE@GOTPAGE
Lloh14:
	ldr	x20, [x20, _mmRLC_CGTT_MGCG_OVERRIDE@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	and	w1, w0, #0xffffffc0
	cmp	w0, w1
	b.eq	LBB0_9
; %bb.8:
	ldr	w0, [x20]
	bl	_WREG32
LBB0_9:
	mov	x0, x19
	bl	_gfx_v6_0_halt_rlc
	mov	x20, x0
Lloh15:
	adrp	x8, _mmRLC_SERDES_WR_MASTER_MASK_0@GOTPAGE
Lloh16:
	ldr	x8, [x8, _mmRLC_SERDES_WR_MASTER_MASK_0@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	mov	w1, #-1
	bl	_WREG32
Lloh18:
	adrp	x8, _mmRLC_SERDES_WR_MASTER_MASK_1@GOTPAGE
Lloh19:
	ldr	x8, [x8, _mmRLC_SERDES_WR_MASTER_MASK_1@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
	mov	w1, #-1
	bl	_WREG32
Lloh21:
	adrp	x8, _mmRLC_SERDES_WR_CTRL@GOTPAGE
Lloh22:
	ldr	x8, [x8, _mmRLC_SERDES_WR_CTRL@GOTPAGEOFF]
Lloh23:
	ldr	w0, [x8]
	mov	w1, #255
	movk	w1, #208, lsl #16
	b	LBB0_17
LBB0_10:
Lloh24:
	adrp	x20, _mmRLC_CGTT_MGCG_OVERRIDE@GOTPAGE
Lloh25:
	ldr	x20, [x20, _mmRLC_CGTT_MGCG_OVERRIDE@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	orr	w1, w0, #0x3
	cmp	w0, w1
	b.eq	LBB0_12
; %bb.11:
	ldr	w0, [x20]
	bl	_WREG32
LBB0_12:
Lloh26:
	adrp	x20, _mmCP_MEM_SLP_CNTL@GOTPAGE
Lloh27:
	ldr	x20, [x20, _mmCP_MEM_SLP_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh28:
	adrp	x8, _CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPAGE
Lloh29:
	ldr	x8, [x8, _CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh30:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_14
; %bb.13:
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32
LBB0_14:
Lloh31:
	adrp	x20, _mmCGTS_SM_CTRL_REG@GOTPAGE
Lloh32:
	ldr	x20, [x20, _mmCGTS_SM_CTRL_REG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh33:
	adrp	x8, _CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK@GOTPAGE
Lloh34:
	ldr	x8, [x8, _CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
Lloh36:
	adrp	x9, _CGTS_SM_CTRL_REG__OVERRIDE_MASK@GOTPAGE
Lloh37:
	ldr	x9, [x9, _CGTS_SM_CTRL_REG__OVERRIDE_MASK@GOTPAGEOFF]
Lloh38:
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w1, w8, w9
	cmp	w0, w1
	b.eq	LBB0_16
; %bb.15:
	ldr	w0, [x20]
	bl	_WREG32
LBB0_16:
	mov	x0, x19
	bl	_gfx_v6_0_halt_rlc
	mov	x20, x0
Lloh39:
	adrp	x8, _mmRLC_SERDES_WR_MASTER_MASK_0@GOTPAGE
Lloh40:
	ldr	x8, [x8, _mmRLC_SERDES_WR_MASTER_MASK_0@GOTPAGEOFF]
Lloh41:
	ldr	w0, [x8]
	mov	w1, #-1
	bl	_WREG32
Lloh42:
	adrp	x8, _mmRLC_SERDES_WR_MASTER_MASK_1@GOTPAGE
Lloh43:
	ldr	x8, [x8, _mmRLC_SERDES_WR_MASTER_MASK_1@GOTPAGEOFF]
Lloh44:
	ldr	w0, [x8]
	mov	w1, #-1
	bl	_WREG32
Lloh45:
	adrp	x8, _mmRLC_SERDES_WR_CTRL@GOTPAGE
Lloh46:
	ldr	x8, [x8, _mmRLC_SERDES_WR_CTRL@GOTPAGEOFF]
Lloh47:
	ldr	w0, [x8]
	mov	w8, #255
	movk	w8, #208, lsl #16
	add	w1, w8, #256, lsl #12           ; =1048576
LBB0_17:
	bl	_WREG32
	mov	x0, x19
	mov	x1, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_gfx_v6_0_update_rlc
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_CG_SUPPORT_GFX_MGCG,4,2    ; @AMD_CG_SUPPORT_GFX_MGCG
	.comm	_mmCGTS_SM_CTRL_REG,4,2         ; @mmCGTS_SM_CTRL_REG
	.comm	_AMD_CG_SUPPORT_GFX_CP_LS,4,2   ; @AMD_CG_SUPPORT_GFX_CP_LS
	.comm	_mmCP_MEM_SLP_CNTL,4,2          ; @mmCP_MEM_SLP_CNTL
	.comm	_CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK,4,2 ; @CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK
	.comm	_mmRLC_CGTT_MGCG_OVERRIDE,4,2   ; @mmRLC_CGTT_MGCG_OVERRIDE
	.comm	_mmRLC_SERDES_WR_MASTER_MASK_0,4,2 ; @mmRLC_SERDES_WR_MASTER_MASK_0
	.comm	_mmRLC_SERDES_WR_MASTER_MASK_1,4,2 ; @mmRLC_SERDES_WR_MASTER_MASK_1
	.comm	_mmRLC_SERDES_WR_CTRL,4,2       ; @mmRLC_SERDES_WR_CTRL
	.comm	_CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK,4,2 ; @CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK
	.comm	_CGTS_SM_CTRL_REG__OVERRIDE_MASK,4,2 ; @CGTS_SM_CTRL_REG__OVERRIDE_MASK
	.no_dead_strip	_gfx_v6_0_enable_mgcg
.subsections_via_symbols
