	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v8_0_get_clockgating_state
_gfx_v8_0_get_clockgating_state:        ## @gfx_v8_0_get_clockgating_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rsi, %rbx
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movl	$0, (%rbx)
LBB0_2:
	movq	_mmRLC_CGTT_MGCG_OVERRIDE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_RLC_CGTT_MGCG_OVERRIDE__CPF_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	jne	LBB0_4
## %bb.3:
	movq	_AMD_CG_SUPPORT_GFX_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%rbx)
LBB0_4:
	movq	_mmRLC_CGCG_CGLS_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_6
## %bb.5:
	movq	_AMD_CG_SUPPORT_GFX_CGCG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	%ecx, (%rbx)
LBB0_6:
	movq	_RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_8
## %bb.7:
	movq	_AMD_CG_SUPPORT_GFX_CGLS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%rbx)
LBB0_8:
	movq	_mmCGTS_SM_CTRL_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_CGTS_SM_CTRL_REG__OVERRIDE_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	jne	LBB0_10
## %bb.9:
	movq	_AMD_CG_SUPPORT_GFX_CGTS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	%ecx, (%rbx)
LBB0_10:
	movq	_CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	jne	LBB0_12
## %bb.11:
	movq	_AMD_CG_SUPPORT_GFX_CGTS_LS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%rbx)
LBB0_12:
	movq	_mmRLC_MEM_SLP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_14
## %bb.13:
	movq	_AMD_CG_SUPPORT_GFX_RLC_LS@GOTPCREL(%rip), %rax
	movq	_AMD_CG_SUPPORT_GFX_MGLS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	orl	%ecx, (%rbx)
LBB0_14:
	movq	_mmCP_MEM_SLP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_16
## %bb.15:
	movq	_AMD_CG_SUPPORT_GFX_CP_LS@GOTPCREL(%rip), %rax
	movq	_AMD_CG_SUPPORT_GFX_MGLS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	orl	%ecx, (%rbx)
LBB0_16:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_mmRLC_CGTT_MGCG_OVERRIDE,4,2   ## @mmRLC_CGTT_MGCG_OVERRIDE
	.comm	_RLC_CGTT_MGCG_OVERRIDE__CPF_MASK,4,2 ## @RLC_CGTT_MGCG_OVERRIDE__CPF_MASK
	.comm	_AMD_CG_SUPPORT_GFX_MGCG,4,2    ## @AMD_CG_SUPPORT_GFX_MGCG
	.comm	_mmRLC_CGCG_CGLS_CTRL,4,2       ## @mmRLC_CGCG_CGLS_CTRL
	.comm	_RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK,4,2 ## @RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK
	.comm	_AMD_CG_SUPPORT_GFX_CGCG,4,2    ## @AMD_CG_SUPPORT_GFX_CGCG
	.comm	_RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK,4,2 ## @RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK
	.comm	_AMD_CG_SUPPORT_GFX_CGLS,4,2    ## @AMD_CG_SUPPORT_GFX_CGLS
	.comm	_mmCGTS_SM_CTRL_REG,4,2         ## @mmCGTS_SM_CTRL_REG
	.comm	_CGTS_SM_CTRL_REG__OVERRIDE_MASK,4,2 ## @CGTS_SM_CTRL_REG__OVERRIDE_MASK
	.comm	_AMD_CG_SUPPORT_GFX_CGTS,4,2    ## @AMD_CG_SUPPORT_GFX_CGTS
	.comm	_CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK,4,2 ## @CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK
	.comm	_AMD_CG_SUPPORT_GFX_CGTS_LS,4,2 ## @AMD_CG_SUPPORT_GFX_CGTS_LS
	.comm	_mmRLC_MEM_SLP_CNTL,4,2         ## @mmRLC_MEM_SLP_CNTL
	.comm	_RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK,4,2 ## @RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK
	.comm	_AMD_CG_SUPPORT_GFX_RLC_LS,4,2  ## @AMD_CG_SUPPORT_GFX_RLC_LS
	.comm	_AMD_CG_SUPPORT_GFX_MGLS,4,2    ## @AMD_CG_SUPPORT_GFX_MGLS
	.comm	_mmCP_MEM_SLP_CNTL,4,2          ## @mmCP_MEM_SLP_CNTL
	.comm	_CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK,4,2 ## @CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK
	.comm	_AMD_CG_SUPPORT_GFX_CP_LS,4,2   ## @AMD_CG_SUPPORT_GFX_CP_LS
	.no_dead_strip	_gfx_v8_0_get_clockgating_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v8_0_get_clockgating_state
_gfx_v8_0_get_clockgating_state:        ; @gfx_v8_0_get_clockgating_state
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x1
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_2
; %bb.1:
	str	wzr, [x19]
LBB0_2:
Lloh0:
	adrp	x8, _mmRLC_CGTT_MGCG_OVERRIDE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _mmRLC_CGTT_MGCG_OVERRIDE@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_RREG32
Lloh3:
	adrp	x8, _RLC_CGTT_MGCG_OVERRIDE__CPF_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _RLC_CGTT_MGCG_OVERRIDE__CPF_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	tst	w8, w0
	b.ne	LBB0_4
; %bb.3:
Lloh6:
	adrp	x8, _AMD_CG_SUPPORT_GFX_MGCG@GOTPAGE
Lloh7:
	ldr	x8, [x8, _AMD_CG_SUPPORT_GFX_MGCG@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_4:
Lloh9:
	adrp	x8, _mmRLC_CGCG_CGLS_CTRL@GOTPAGE
Lloh10:
	ldr	x8, [x8, _mmRLC_CGCG_CGLS_CTRL@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	bl	_RREG32
Lloh12:
	adrp	x8, _RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_6
; %bb.5:
Lloh15:
	adrp	x8, _AMD_CG_SUPPORT_GFX_CGCG@GOTPAGE
Lloh16:
	ldr	x8, [x8, _AMD_CG_SUPPORT_GFX_CGCG@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_6:
Lloh18:
	adrp	x8, _RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK@GOTPAGE
Lloh19:
	ldr	x8, [x8, _RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_8
; %bb.7:
Lloh21:
	adrp	x8, _AMD_CG_SUPPORT_GFX_CGLS@GOTPAGE
Lloh22:
	ldr	x8, [x8, _AMD_CG_SUPPORT_GFX_CGLS@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_8:
Lloh24:
	adrp	x8, _mmCGTS_SM_CTRL_REG@GOTPAGE
Lloh25:
	ldr	x8, [x8, _mmCGTS_SM_CTRL_REG@GOTPAGEOFF]
Lloh26:
	ldr	w0, [x8]
	bl	_RREG32
Lloh27:
	adrp	x8, _CGTS_SM_CTRL_REG__OVERRIDE_MASK@GOTPAGE
Lloh28:
	ldr	x8, [x8, _CGTS_SM_CTRL_REG__OVERRIDE_MASK@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	tst	w8, w0
	b.ne	LBB0_10
; %bb.9:
Lloh30:
	adrp	x8, _AMD_CG_SUPPORT_GFX_CGTS@GOTPAGE
Lloh31:
	ldr	x8, [x8, _AMD_CG_SUPPORT_GFX_CGTS@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_10:
Lloh33:
	adrp	x8, _CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK@GOTPAGE
Lloh34:
	ldr	x8, [x8, _CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
	tst	w8, w0
	b.ne	LBB0_12
; %bb.11:
Lloh36:
	adrp	x8, _AMD_CG_SUPPORT_GFX_CGTS_LS@GOTPAGE
Lloh37:
	ldr	x8, [x8, _AMD_CG_SUPPORT_GFX_CGTS_LS@GOTPAGEOFF]
Lloh38:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_12:
Lloh39:
	adrp	x8, _mmRLC_MEM_SLP_CNTL@GOTPAGE
Lloh40:
	ldr	x8, [x8, _mmRLC_MEM_SLP_CNTL@GOTPAGEOFF]
Lloh41:
	ldr	w0, [x8]
	bl	_RREG32
Lloh42:
	adrp	x8, _RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK@GOTPAGE
Lloh43:
	ldr	x8, [x8, _RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh44:
	ldr	w8, [x8]
Lloh45:
	adrp	x20, _AMD_CG_SUPPORT_GFX_MGLS@GOTPAGE
Lloh46:
	ldr	x20, [x20, _AMD_CG_SUPPORT_GFX_MGLS@GOTPAGEOFF]
	tst	w8, w0
	b.eq	LBB0_14
; %bb.13:
Lloh47:
	adrp	x8, _AMD_CG_SUPPORT_GFX_RLC_LS@GOTPAGE
Lloh48:
	ldr	x8, [x8, _AMD_CG_SUPPORT_GFX_RLC_LS@GOTPAGEOFF]
Lloh49:
	ldr	w8, [x8]
	ldr	w9, [x20]
	orr	w8, w9, w8
	ldr	w9, [x19]
	orr	w8, w8, w9
	str	w8, [x19]
LBB0_14:
Lloh50:
	adrp	x8, _mmCP_MEM_SLP_CNTL@GOTPAGE
Lloh51:
	ldr	x8, [x8, _mmCP_MEM_SLP_CNTL@GOTPAGEOFF]
Lloh52:
	ldr	w0, [x8]
	bl	_RREG32
Lloh53:
	adrp	x8, _CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPAGE
Lloh54:
	ldr	x8, [x8, _CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh55:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_16
; %bb.15:
Lloh56:
	adrp	x8, _AMD_CG_SUPPORT_GFX_CP_LS@GOTPAGE
Lloh57:
	ldr	x8, [x8, _AMD_CG_SUPPORT_GFX_CP_LS@GOTPAGEOFF]
Lloh58:
	ldr	w8, [x8]
	ldr	w9, [x20]
	orr	w8, w9, w8
	ldr	w9, [x19]
	orr	w8, w8, w9
	str	w8, [x19]
LBB0_16:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.cfi_endproc
                                        ; -- End function
	.comm	_mmRLC_CGTT_MGCG_OVERRIDE,4,2   ; @mmRLC_CGTT_MGCG_OVERRIDE
	.comm	_RLC_CGTT_MGCG_OVERRIDE__CPF_MASK,4,2 ; @RLC_CGTT_MGCG_OVERRIDE__CPF_MASK
	.comm	_AMD_CG_SUPPORT_GFX_MGCG,4,2    ; @AMD_CG_SUPPORT_GFX_MGCG
	.comm	_mmRLC_CGCG_CGLS_CTRL,4,2       ; @mmRLC_CGCG_CGLS_CTRL
	.comm	_RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK,4,2 ; @RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK
	.comm	_AMD_CG_SUPPORT_GFX_CGCG,4,2    ; @AMD_CG_SUPPORT_GFX_CGCG
	.comm	_RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK,4,2 ; @RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK
	.comm	_AMD_CG_SUPPORT_GFX_CGLS,4,2    ; @AMD_CG_SUPPORT_GFX_CGLS
	.comm	_mmCGTS_SM_CTRL_REG,4,2         ; @mmCGTS_SM_CTRL_REG
	.comm	_CGTS_SM_CTRL_REG__OVERRIDE_MASK,4,2 ; @CGTS_SM_CTRL_REG__OVERRIDE_MASK
	.comm	_AMD_CG_SUPPORT_GFX_CGTS,4,2    ; @AMD_CG_SUPPORT_GFX_CGTS
	.comm	_CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK,4,2 ; @CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK
	.comm	_AMD_CG_SUPPORT_GFX_CGTS_LS,4,2 ; @AMD_CG_SUPPORT_GFX_CGTS_LS
	.comm	_mmRLC_MEM_SLP_CNTL,4,2         ; @mmRLC_MEM_SLP_CNTL
	.comm	_RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK,4,2 ; @RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK
	.comm	_AMD_CG_SUPPORT_GFX_RLC_LS,4,2  ; @AMD_CG_SUPPORT_GFX_RLC_LS
	.comm	_AMD_CG_SUPPORT_GFX_MGLS,4,2    ; @AMD_CG_SUPPORT_GFX_MGLS
	.comm	_mmCP_MEM_SLP_CNTL,4,2          ; @mmCP_MEM_SLP_CNTL
	.comm	_CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK,4,2 ; @CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK
	.comm	_AMD_CG_SUPPORT_GFX_CP_LS,4,2   ; @AMD_CG_SUPPORT_GFX_CP_LS
	.no_dead_strip	_gfx_v8_0_get_clockgating_state
.subsections_via_symbols
