	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_pp_nv_set_hard_min_uclk_by_freq ## -- Begin function pp_nv_set_hard_min_uclk_by_freq
	.p2align	4, 0x90
_pp_nv_set_hard_min_uclk_by_freq:       ## @pp_nv_set_hard_min_uclk_by_freq
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	subq	$16, %rsp
	movq	(%rdi), %rax
	movq	(%rax), %rdi
	cmpl	$0, (%rdi)
	je	LBB0_1
## %bb.2:
	movq	_amd_pp_mem_clock@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -4(%rbp)
	imull	$1000, %esi, %eax               ## imm = 0x3E8
	movl	%eax, -8(%rbp)
	leaq	-8(%rbp), %rsi
	callq	_smu_display_clock_voltage_request
	testq	%rax, %rax
	jne	LBB0_3
## %bb.4:
	movq	_PP_SMU_RESULT_OK@GOTPCREL(%rip), %rax
	jmp	LBB0_5
LBB0_1:
	movq	_PP_SMU_RESULT_UNSUPPORTED@GOTPCREL(%rip), %rax
	jmp	LBB0_5
LBB0_3:
	movq	_PP_SMU_RESULT_FAIL@GOTPCREL(%rip), %rax
LBB0_5:
	movl	(%rax), %eax
	addq	$16, %rsp
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PP_SMU_RESULT_UNSUPPORTED,4,2  ## @PP_SMU_RESULT_UNSUPPORTED
	.comm	_amd_pp_mem_clock,4,2           ## @amd_pp_mem_clock
	.comm	_PP_SMU_RESULT_FAIL,4,2         ## @PP_SMU_RESULT_FAIL
	.comm	_PP_SMU_RESULT_OK,4,2           ## @PP_SMU_RESULT_OK
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_pp_nv_set_hard_min_uclk_by_freq ; -- Begin function pp_nv_set_hard_min_uclk_by_freq
	.p2align	2
_pp_nv_set_hard_min_uclk_by_freq:       ; @pp_nv_set_hard_min_uclk_by_freq
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #32
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	ldr	x8, [x0]
	ldr	x0, [x8]
	ldr	w8, [x0]
	cbz	w8, LBB0_2
; %bb.1:
Lloh0:
	adrp	x8, _amd_pp_mem_clock@GOTPAGE
Lloh1:
	ldr	x8, [x8, _amd_pp_mem_clock@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	mov	w9, #1000
	mul	w9, w1, w9
	stp	w9, w8, [sp, #8]
	add	x1, sp, #8
	bl	_smu_display_clock_voltage_request
Lloh3:
	adrp	x8, _PP_SMU_RESULT_FAIL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PP_SMU_RESULT_FAIL@GOTPAGEOFF]
Lloh5:
	adrp	x9, _PP_SMU_RESULT_OK@GOTPAGE
Lloh6:
	ldr	x9, [x9, _PP_SMU_RESULT_OK@GOTPAGEOFF]
	cmp	x0, #0
	csel	x8, x9, x8, eq
	b	LBB0_3
LBB0_2:
Lloh7:
	adrp	x8, _PP_SMU_RESULT_UNSUPPORTED@GOTPAGE
Lloh8:
	ldr	x8, [x8, _PP_SMU_RESULT_UNSUPPORTED@GOTPAGEOFF]
LBB0_3:
	ldr	w0, [x8]
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #32
	ret
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_PP_SMU_RESULT_UNSUPPORTED,4,2  ; @PP_SMU_RESULT_UNSUPPORTED
	.comm	_amd_pp_mem_clock,4,2           ; @amd_pp_mem_clock
	.comm	_PP_SMU_RESULT_FAIL,4,2         ; @PP_SMU_RESULT_FAIL
	.comm	_PP_SMU_RESULT_OK,4,2           ; @PP_SMU_RESULT_OK
.subsections_via_symbols
