	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function intel_post_plane_update
_intel_post_plane_update:               ## @intel_post_plane_update
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movl	16(%rdi), %edi
	callq	_to_intel_crtc
	movq	%rax, %r12
	movq	8(%rax), %rdi
	callq	_to_i915
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
	movq	%rbx, -48(%rbp)                 ## 8-byte Spill
	movq	8(%rbx), %r13
	movq	%r13, %rdi
	callq	_to_intel_atomic_state
	movl	%eax, %edi
	movq	%r12, %rsi
	callq	_intel_atomic_get_new_crtc_state
	movq	%rax, %r15
	movq	16(%r12), %r14
	movq	%r13, %rdi
	movq	%r14, %rsi
	callq	_drm_atomic_get_old_plane_state
	movq	%rax, %rbx
	movq	8(%r12), %rdi
	callq	_to_i915
	movl	32(%r15), %esi
	movq	%rax, %rdi
	callq	_intel_frontbuffer_flip
	cmpq	$0, 24(%r15)
	je	LBB0_3
## %bb.1:
	cmpq	$0, (%r15)
	je	LBB0_3
## %bb.2:
	movq	%r12, %rdi
	callq	_intel_update_watermarks
LBB0_3:
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movq	%r15, %rsi
	callq	_hsw_post_update_enable_ips
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	movq	%r15, %rdi
	callq	_hsw_enable_ips
LBB0_5:
	testq	%rbx, %rbx
	je	LBB0_10
## %bb.6:
	movq	%r13, %rdi
	movq	%r14, %rsi
	callq	_drm_atomic_get_new_plane_state
	movq	%rax, %r14
	movq	%r12, %rdi
	callq	_intel_fbc_post_update
	cmpq	$0, (%r14)
	je	LBB0_10
## %bb.7:
	movq	%r15, %rdi
	callq	_needs_modeset
	testq	%rax, %rax
	jne	LBB0_9
## %bb.8:
	cmpq	$0, (%rbx)
	jne	LBB0_10
LBB0_9:
	movq	%r12, %rdi
	addq	$8, %rdi
	movq	%r15, %rsi
	callq	_intel_post_enable_primary
LBB0_10:
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	movq	-48(%rbp), %rsi                 ## 8-byte Reload
	callq	_needs_nv12_wa
	testq	%rax, %rax
	je	LBB0_13
## %bb.11:
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	_needs_nv12_wa
	testq	%rax, %rax
	jne	LBB0_13
## %bb.12:
	movl	(%r12), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_skl_wa_827
LBB0_13:
	movq	%rbx, %rdi
	movq	-48(%rbp), %rsi                 ## 8-byte Reload
	callq	_needs_scalerclk_wa
	testq	%rax, %rax
	je	LBB0_15
## %bb.14:
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	_needs_scalerclk_wa
	testq	%rax, %rax
	je	LBB0_16
LBB0_15:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_16:
	movl	(%r12), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_icl_wa_scalerclkgating         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.no_dead_strip	_intel_post_plane_update
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function intel_post_plane_update
_intel_post_plane_update:               ; @intel_post_plane_update
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x21, x0
	ldr	w0, [x0, #16]
	bl	_to_intel_crtc
	mov	x19, x0
	mov	x23, x0
	ldr	x0, [x23, #8]!
	bl	_to_i915
	mov	x20, x0
	ldr	x25, [x21, #8]
	mov	x0, x25
	bl	_to_intel_atomic_state
	mov	x1, x19
	bl	_intel_atomic_get_new_crtc_state
	mov	x22, x0
	ldr	x26, [x19, #16]
	mov	x0, x25
	mov	x1, x26
	bl	_drm_atomic_get_old_plane_state
	mov	x24, x0
	ldr	x0, [x23]
	bl	_to_i915
	ldr	w1, [x22, #32]
	bl	_intel_frontbuffer_flip
	ldr	x8, [x22, #24]
	cbz	x8, LBB0_3
; %bb.1:
	ldr	x8, [x22]
	cbz	x8, LBB0_3
; %bb.2:
	mov	x0, x19
	bl	_intel_update_watermarks
LBB0_3:
	mov	x0, x21
	mov	x1, x22
	bl	_hsw_post_update_enable_ips
	cbz	x0, LBB0_5
; %bb.4:
	mov	x0, x22
	bl	_hsw_enable_ips
LBB0_5:
	cbz	x24, LBB0_10
; %bb.6:
	mov	x0, x25
	mov	x1, x26
	bl	_drm_atomic_get_new_plane_state
	mov	x25, x0
	mov	x0, x19
	bl	_intel_fbc_post_update
	ldr	x8, [x25]
	cbz	x8, LBB0_10
; %bb.7:
	mov	x0, x22
	bl	_needs_modeset
	cbnz	x0, LBB0_9
; %bb.8:
	ldr	x8, [x24]
	cbnz	x8, LBB0_10
LBB0_9:
	mov	x0, x23
	mov	x1, x22
	bl	_intel_post_enable_primary
LBB0_10:
	mov	x0, x20
	mov	x1, x21
	bl	_needs_nv12_wa
	cbz	x0, LBB0_13
; %bb.11:
	mov	x0, x20
	mov	x1, x22
	bl	_needs_nv12_wa
	cbnz	x0, LBB0_13
; %bb.12:
	ldr	w1, [x19]
	mov	x0, x20
	mov	w2, #0
	bl	_skl_wa_827
LBB0_13:
	mov	x0, x20
	mov	x1, x21
	bl	_needs_scalerclk_wa
	cbz	x0, LBB0_15
; %bb.14:
	mov	x0, x20
	mov	x1, x22
	bl	_needs_scalerclk_wa
	cbz	x0, LBB0_16
LBB0_15:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_16:
	ldr	w1, [x19]
	mov	x0, x20
	mov	w2, #0
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_icl_wa_scalerclkgating
	.cfi_endproc
                                        ; -- End function
	.no_dead_strip	_intel_post_plane_update
.subsections_via_symbols
