	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4                               ## -- Begin function cik_gpu_init
LCPI0_0:
	.long	1                               ## 0x1
	.long	4                               ## 0x4
	.long	8                               ## 0x8
	.long	1                               ## 0x1
LCPI0_1:
	.long	4                               ## 0x4
	.long	16                              ## 0x10
	.long	11                              ## 0xb
	.long	1                               ## 0x1
LCPI0_2:
	.long	2                               ## 0x2
	.long	4                               ## 0x4
	.long	7                               ## 0x7
	.long	1                               ## 0x1
LCPI0_3:
	.long	1                               ## 0x1
	.long	2                               ## 0x2
	.long	2                               ## 0x2
	.long	1                               ## 0x1
LCPI0_4:
	.long	8                               ## 0x8
	.long	32                              ## 0x20
	.long	256                             ## 0x100
	.long	48                              ## 0x30
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	4, 0x90
_cik_gpu_init:                          ## @cik_gpu_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	_GB_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	(%r12), %eax
	cmpl	$129, %eax
	je	LBB0_5
## %bb.1:
	cmpl	$131, %eax
	je	LBB0_4
## %bb.2:
	cmpl	$132, %eax
	jne	LBB0_6
## %bb.3:
	movaps	LCPI0_2(%rip), %xmm0            ## xmm0 = [2,4,7,1]
	movups	%xmm0, 8(%r12)
	movl	$2, 24(%r12)
	movq	_BONAIRE_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %rax
	movl	$32, %ecx
	movl	$4, %edx
	jmp	LBB0_7
LBB0_5:
	movl	$2, 24(%r12)
	movaps	LCPI0_0(%rip), %xmm0            ## xmm0 = [1,4,8,1]
	movups	%xmm0, 8(%r12)
	movq	_BONAIRE_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %rax
	movl	$16, %ecx
	movl	$4, %edx
	jmp	LBB0_7
LBB0_4:
	movaps	LCPI0_1(%rip), %xmm0            ## xmm0 = [4,16,11,1]
	movups	%xmm0, 8(%r12)
	movl	$4, 24(%r12)
	movq	_HAWAII_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %rax
	movl	$32, %ecx
	movl	$16, %edx
	jmp	LBB0_7
LBB0_6:
	movaps	LCPI0_3(%rip), %xmm0            ## xmm0 = [1,2,2,1]
	movups	%xmm0, 8(%r12)
	movl	$1, 24(%r12)
	movq	_BONAIRE_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %rax
	movl	$16, %ecx
	movl	$2, %edx
LBB0_7:
	movl	%edx, 28(%r12)
	movl	$256, 32(%r12)                  ## imm = 0x100
	movl	%ecx, 36(%r12)
	movaps	LCPI0_4(%rip), %xmm0            ## xmm0 = [8,32,256,48]
	movups	%xmm0, 40(%r12)
	movl	$304, 56(%r12)                  ## imm = 0x130
	movl	(%rax), %r13d
	movl	$11284, %ebx                    ## imm = 0x2C14
	.p2align	4, 0x90
LBB0_8:                                 ## =>This Inner Loop Header: Depth=1
	movl	%ebx, %edi
	xorl	%esi, %esi
	callq	_WREG32
	leal	4(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	leal	8(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	leal	12(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	leal	16(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	addl	$24, %ebx
	cmpl	$12052, %ebx                    ## imm = 0x2F14
	jne	LBB0_8
## %bb.9:
	movq	_GRBM_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$255, %edi
	callq	_GRBM_READ_TIMEOUT
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_SRBM_INT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_WREG32
	movq	_SRBM_INT_ACK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_WREG32
	movq	_BIF_FB_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_FB_READ_EN@GOTPCREL(%rip), %rax
	movq	_FB_WRITE_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	callq	_WREG32
	movq	_MC_SHARED_CHMAP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_MC_ARB_RAMCFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r15d
	movl	12(%r12), %eax
	movl	%eax, 60(%r12)
	movl	$256, 64(%r12)                  ## imm = 0x100
	movq	_NOOFCOLS_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r15d, %eax
	movq	_NOOFCOLS_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	addb	$8, %al
	movl	$4, %edx
	movl	$4, %esi
	movl	%eax, %ecx
	shll	%cl, %esi
	cmpl	$5119, %esi                     ## imm = 0x13FF
	jg	LBB0_11
## %bb.10:
	leal	1023(%rsi), %edx
	testl	%esi, %esi
	cmovnsl	%esi, %edx
	sarl	$10, %edx
LBB0_11:
	movl	%edx, 68(%r12)
	movabsq	$4294967328, %rax               ## imm = 0x100000020
	movq	%rax, 72(%r12)
	movl	$64, 80(%r12)
	movq	_ROW_SIZE_MASK@GOTPCREL(%rip), %rbx
	movl	(%rbx), %eax
	notl	%eax
	andl	%eax, %r13d
	xorl	%eax, %eax
	cmpl	$2, %edx
	sete	%al
	cmpl	$4, %edx
	movl	$2, %edi
	cmovnel	%eax, %edi
	callq	_ROW_SIZE
	movl	%eax, %r14d
	orl	%r13d, %r14d
	movl	60(%r12), %ecx
	decl	%ecx
	movl	$3, %eax
	cmpl	$3, %ecx
	ja	LBB0_13
## %bb.12:
	movslq	%ecx, %rax
	leaq	L_switch.table.cik_gpu_init(%rip), %rcx
	movl	(%rcx,%rax,4), %eax
LBB0_13:
	movq	_NOOFBANK_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %r15d
	movq	_NOOFBANK_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %r15d
	shll	$4, %r15d
	orl	%eax, %r15d
	movq	_PIPE_INTERLEAVE_SIZE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r14d, %eax
	movq	_PIPE_INTERLEAVE_SIZE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	shll	$8, %eax
	orl	%r15d, %eax
	movl	(%rbx), %edx
	andl	%r14d, %edx
	movq	_ROW_SIZE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %edx
	shll	$12, %edx
	orl	%eax, %edx
	movl	%edx, 84(%r12)
	movq	_GB_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_HDP_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_DMIF_ADDR_CALC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_SDMA0_TILING_CONFIG@GOTPCREL(%rip), %r15
	movq	_SDMA0_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	addl	(%r15), %edi
	movl	%r14d, %ebx
	andl	$112, %ebx
	movl	%ebx, %esi
	callq	_WREG32
	movq	_SDMA1_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	addl	(%r15), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_UVD_UDEC_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_UVD_UDEC_DB_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_UVD_UDEC_DBW_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	%r12, %rdi
	callq	_cik_tiling_mode_table_init
	movl	8(%r12), %esi
	movl	20(%r12), %edx
	movl	24(%r12), %ecx
	movq	%r12, %rdi
	callq	_cik_setup_rb
	movq	$0, 88(%r12)
	movl	8(%r12), %ecx
	testl	%ecx, %ecx
	jle	LBB0_20
## %bb.14:
	movl	20(%r12), %eax
	xorl	%r14d, %r14d
	jmp	LBB0_15
	.p2align	4, 0x90
LBB0_19:                                ##   in Loop: Header=BB0_15 Depth=1
	incl	%r14d
	cmpl	%ecx, %r14d
	jge	LBB0_20
LBB0_15:                                ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_17 Depth 2
	testl	%eax, %eax
	jle	LBB0_19
## %bb.16:                              ##   in Loop: Header=BB0_15 Depth=1
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_17:                                ##   Parent Loop BB0_15 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movq	%r12, %rdi
	movl	%r14d, %esi
	movl	%ebx, %edx
	callq	_cik_get_cu_active_bitmap
	movl	%eax, %edi
	callq	_hweight32
	addq	%rax, 88(%r12)
	incl	%ebx
	movl	20(%r12), %eax
	cmpl	%eax, %ebx
	jl	LBB0_17
## %bb.18:                              ##   in Loop: Header=BB0_15 Depth=1
	movl	8(%r12), %ecx
	jmp	LBB0_19
LBB0_20:
	movq	_CP_MEQ_THRESHOLDS@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	$48, %edi
	callq	_MEQ1_START
	movl	%eax, %ebx
	movl	$96, %edi
	callq	_MEQ2_START
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_SX_DEBUG_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$32, %esi
	callq	_WREG32
	movq	_TA_CNTL_AUX@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$65536, %esi                    ## imm = 0x10000
	callq	_WREG32
	movq	_SPI_CONFIG_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	orl	$50331648, %eax                 ## imm = 0x3000000
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_SQ_CONFIG@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movl	$1, %esi
	callq	_WREG32
	movq	_DB_DEBUG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_DB_DEBUG2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
                                        ## kill: def $eax killed $eax def $rax
	andl	$267386880, %eax                ## imm = 0xFF00000
	leal	1024(%rax), %esi
	movl	(%rbx), %edi
	callq	_WREG32
	movq	_DB_DEBUG3@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
                                        ## kill: def $eax killed $eax def $rax
	andl	$-131613, %eax                  ## imm = 0xFFFDFDE3
	leal	131584(%rax), %esi
	movl	(%rbx), %edi
	callq	_WREG32
	movq	_CB_HW_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	orl	$98824, %eax                    ## imm = 0x18208
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_SPI_CONFIG_CNTL_1@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$4, %edi
	callq	_VTX_DONE_DELAY
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_PA_SC_FIFO_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	44(%r12), %edi
	callq	_SC_FRONTEND_PRIM_FIFO_SIZE
	movl	%eax, %r15d
	movl	48(%r12), %edi
	callq	_SC_BACKEND_PRIM_FIFO_SIZE
	orl	%eax, %r15d
	movl	52(%r12), %edi
	callq	_SC_HIZ_TILE_FIFO_SIZE
	movl	%eax, %ebx
	movl	56(%r12), %edi
	callq	_SC_EARLYZ_TILE_FIFO_SIZE
	orl	%eax, %ebx
	orl	%r15d, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_VGT_NUM_INSTANCES@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_WREG32
	movq	_CP_PERFMON_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r13), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_PA_SC_FORCE_EOV_MAX_CNTS@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	$4095, %edi                     ## imm = 0xFFF
	callq	_FORCE_EOV_MAX_CLK_CNT
	movl	%eax, %ebx
	movl	$255, %edi
	callq	_FORCE_EOV_MAX_REZ_CNT
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_VGT_CACHE_INVALIDATION@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_VC_AND_TC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_CACHE_INVALIDATION
	movl	%eax, %ebx
	movq	_ES_AND_GS_AUTO@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_AUTO_INVLD_EN
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_VGT_GS_VERTEX_REUSE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$16, %esi
	callq	_WREG32
	movq	_PA_SC_LINE_STIPPLE_STATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_HDP_MISC_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_HDP_FLUSH_INVALIDATE_CACHE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_HDP_HOST_PATH_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_PA_CL_ENHANCE@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_CLIP_VTX_REORDER_ENA@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$3, %edi
	callq	_NUM_CLIP_SEQ
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_PA_SC_ENHANCE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_ENABLE_PA_SC_OUT_OF_ORDER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_WREG32
	movl	$50, %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_udelay                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_GB_ADDR_CONFIG,4,2             ## @GB_ADDR_CONFIG
	.comm	_BONAIRE_GB_ADDR_CONFIG_GOLDEN,4,2 ## @BONAIRE_GB_ADDR_CONFIG_GOLDEN
	.comm	_HAWAII_GB_ADDR_CONFIG_GOLDEN,4,2 ## @HAWAII_GB_ADDR_CONFIG_GOLDEN
	.comm	_GRBM_CNTL,4,2                  ## @GRBM_CNTL
	.comm	_SRBM_INT_CNTL,4,2              ## @SRBM_INT_CNTL
	.comm	_SRBM_INT_ACK,4,2               ## @SRBM_INT_ACK
	.comm	_BIF_FB_EN,4,2                  ## @BIF_FB_EN
	.comm	_FB_READ_EN,4,2                 ## @FB_READ_EN
	.comm	_FB_WRITE_EN,4,2                ## @FB_WRITE_EN
	.comm	_MC_SHARED_CHMAP,4,2            ## @MC_SHARED_CHMAP
	.comm	_MC_ARB_RAMCFG,4,2              ## @MC_ARB_RAMCFG
	.comm	_NOOFCOLS_MASK,4,2              ## @NOOFCOLS_MASK
	.comm	_NOOFCOLS_SHIFT,4,2             ## @NOOFCOLS_SHIFT
	.comm	_ROW_SIZE_MASK,4,2              ## @ROW_SIZE_MASK
	.comm	_NOOFBANK_MASK,4,2              ## @NOOFBANK_MASK
	.comm	_NOOFBANK_SHIFT,4,2             ## @NOOFBANK_SHIFT
	.comm	_PIPE_INTERLEAVE_SIZE_MASK,4,2  ## @PIPE_INTERLEAVE_SIZE_MASK
	.comm	_PIPE_INTERLEAVE_SIZE_SHIFT,4,2 ## @PIPE_INTERLEAVE_SIZE_SHIFT
	.comm	_ROW_SIZE_SHIFT,4,2             ## @ROW_SIZE_SHIFT
	.comm	_HDP_ADDR_CONFIG,4,2            ## @HDP_ADDR_CONFIG
	.comm	_DMIF_ADDR_CALC,4,2             ## @DMIF_ADDR_CALC
	.comm	_SDMA0_TILING_CONFIG,4,2        ## @SDMA0_TILING_CONFIG
	.comm	_SDMA0_REGISTER_OFFSET,4,2      ## @SDMA0_REGISTER_OFFSET
	.comm	_SDMA1_REGISTER_OFFSET,4,2      ## @SDMA1_REGISTER_OFFSET
	.comm	_UVD_UDEC_ADDR_CONFIG,4,2       ## @UVD_UDEC_ADDR_CONFIG
	.comm	_UVD_UDEC_DB_ADDR_CONFIG,4,2    ## @UVD_UDEC_DB_ADDR_CONFIG
	.comm	_UVD_UDEC_DBW_ADDR_CONFIG,4,2   ## @UVD_UDEC_DBW_ADDR_CONFIG
	.comm	_CP_MEQ_THRESHOLDS,4,2          ## @CP_MEQ_THRESHOLDS
	.comm	_SX_DEBUG_1,4,2                 ## @SX_DEBUG_1
	.comm	_TA_CNTL_AUX,4,2                ## @TA_CNTL_AUX
	.comm	_SPI_CONFIG_CNTL,4,2            ## @SPI_CONFIG_CNTL
	.comm	_SQ_CONFIG,4,2                  ## @SQ_CONFIG
	.comm	_DB_DEBUG,4,2                   ## @DB_DEBUG
	.comm	_DB_DEBUG2,4,2                  ## @DB_DEBUG2
	.comm	_DB_DEBUG3,4,2                  ## @DB_DEBUG3
	.comm	_CB_HW_CONTROL,4,2              ## @CB_HW_CONTROL
	.comm	_SPI_CONFIG_CNTL_1,4,2          ## @SPI_CONFIG_CNTL_1
	.comm	_PA_SC_FIFO_SIZE,4,2            ## @PA_SC_FIFO_SIZE
	.comm	_VGT_NUM_INSTANCES,4,2          ## @VGT_NUM_INSTANCES
	.comm	_CP_PERFMON_CNTL,4,2            ## @CP_PERFMON_CNTL
	.comm	_PA_SC_FORCE_EOV_MAX_CNTS,4,2   ## @PA_SC_FORCE_EOV_MAX_CNTS
	.comm	_VGT_CACHE_INVALIDATION,4,2     ## @VGT_CACHE_INVALIDATION
	.comm	_VC_AND_TC,4,2                  ## @VC_AND_TC
	.comm	_ES_AND_GS_AUTO,4,2             ## @ES_AND_GS_AUTO
	.comm	_VGT_GS_VERTEX_REUSE,4,2        ## @VGT_GS_VERTEX_REUSE
	.comm	_PA_SC_LINE_STIPPLE_STATE,4,2   ## @PA_SC_LINE_STIPPLE_STATE
	.comm	_HDP_MISC_CNTL,4,2              ## @HDP_MISC_CNTL
	.comm	_HDP_FLUSH_INVALIDATE_CACHE,4,2 ## @HDP_FLUSH_INVALIDATE_CACHE
	.comm	_HDP_HOST_PATH_CNTL,4,2         ## @HDP_HOST_PATH_CNTL
	.comm	_PA_CL_ENHANCE,4,2              ## @PA_CL_ENHANCE
	.comm	_CLIP_VTX_REORDER_ENA,4,2       ## @CLIP_VTX_REORDER_ENA
	.comm	_PA_SC_ENHANCE,4,2              ## @PA_SC_ENHANCE
	.comm	_ENABLE_PA_SC_OUT_OF_ORDER,4,2  ## @ENABLE_PA_SC_OUT_OF_ORDER
	.no_dead_strip	_cik_gpu_init
	.section	__TEXT,__literal16,16byte_literals
	.p2align	2                               ## @switch.table.cik_gpu_init
L_switch.table.cik_gpu_init:
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	3                               ## 0x3
	.long	2                               ## 0x2

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4                               ; -- Begin function cik_gpu_init
lCPI0_0:
	.long	1                               ; 0x1
	.long	4                               ; 0x4
	.long	8                               ; 0x8
	.long	1                               ; 0x1
lCPI0_1:
	.long	4                               ; 0x4
	.long	16                              ; 0x10
	.long	11                              ; 0xb
	.long	1                               ; 0x1
lCPI0_2:
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	1                               ; 0x1
lCPI0_3:
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	1                               ; 0x1
lCPI0_4:
	.long	8                               ; 0x8
	.long	32                              ; 0x20
	.long	256                             ; 0x100
	.long	48                              ; 0x30
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3
lCPI0_5:
	.long	32                              ; 0x20
	.long	1                               ; 0x1
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	2
_cik_gpu_init:                          ; @cik_gpu_init
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
Lloh0:
	adrp	x22, _GB_ADDR_CONFIG@GOTPAGE
Lloh1:
	ldr	x22, [x22, _GB_ADDR_CONFIG@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_RREG32
	ldr	w8, [x19]
	cmp	w8, #129
	b.eq	LBB0_4
; %bb.1:
	cmp	w8, #131
	b.eq	LBB0_5
; %bb.2:
	cmp	w8, #132
	b.ne	LBB0_6
; %bb.3:
Lloh2:
	adrp	x8, lCPI0_2@PAGE
Lloh3:
	ldr	q0, [x8, lCPI0_2@PAGEOFF]
	stur	q0, [x19, #8]
	mov	w8, #2
	str	w8, [x19, #24]
Lloh4:
	adrp	x8, _BONAIRE_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh5:
	ldr	x8, [x8, _BONAIRE_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
	mov	w9, #32
	mov	w10, #4
	b	LBB0_7
LBB0_4:
	mov	w8, #2
	str	w8, [x19, #24]
Lloh6:
	adrp	x8, lCPI0_0@PAGE
Lloh7:
	ldr	q0, [x8, lCPI0_0@PAGEOFF]
	stur	q0, [x19, #8]
Lloh8:
	adrp	x8, _BONAIRE_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh9:
	ldr	x8, [x8, _BONAIRE_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
	mov	w9, #16
	mov	w10, #4
	b	LBB0_7
LBB0_5:
Lloh10:
	adrp	x8, lCPI0_1@PAGE
Lloh11:
	ldr	q0, [x8, lCPI0_1@PAGEOFF]
	stur	q0, [x19, #8]
	mov	w8, #4
	str	w8, [x19, #24]
Lloh12:
	adrp	x8, _HAWAII_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh13:
	ldr	x8, [x8, _HAWAII_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
	mov	w9, #32
	mov	w10, #16
	b	LBB0_7
LBB0_6:
Lloh14:
	adrp	x8, lCPI0_3@PAGE
Lloh15:
	ldr	q0, [x8, lCPI0_3@PAGEOFF]
	stur	q0, [x19, #8]
	mov	w8, #1
	str	w8, [x19, #24]
Lloh16:
	adrp	x8, _BONAIRE_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh17:
	ldr	x8, [x8, _BONAIRE_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
	mov	w9, #16
	mov	w10, #2
LBB0_7:
	mov	w21, #0
	mov	w11, #256
	stp	w10, w11, [x19, #28]
	str	w9, [x19, #36]
Lloh18:
	adrp	x9, lCPI0_4@PAGE
Lloh19:
	ldr	q0, [x9, lCPI0_4@PAGEOFF]
	stur	q0, [x19, #40]
	mov	w9, #304
	str	w9, [x19, #56]
	mov	w24, #11292
	ldr	w23, [x8]
	mov	w25, #11284
	mov	w26, #11288
	mov	w27, #11296
	mov	w28, #11300
LBB0_8:                                 ; =>This Inner Loop Header: Depth=1
	add	w20, w21, w24
	add	w0, w21, w25
	mov	w1, #0
	bl	_WREG32
	add	w0, w21, w26
	mov	w1, #0
	bl	_WREG32
	mov	x0, x20
	mov	w1, #0
	bl	_WREG32
	add	w0, w21, w27
	mov	w1, #0
	bl	_WREG32
	add	w0, w21, w28
	mov	w1, #0
	bl	_WREG32
	add	w21, w21, #24
	cmp	w21, #768
	b.ne	LBB0_8
; %bb.9:
Lloh20:
	adrp	x8, _GRBM_CNTL@GOTPAGE
Lloh21:
	ldr	x8, [x8, _GRBM_CNTL@GOTPAGEOFF]
Lloh22:
	ldr	w20, [x8]
	mov	w0, #255
	bl	_GRBM_READ_TIMEOUT
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
Lloh23:
	adrp	x8, _SRBM_INT_CNTL@GOTPAGE
Lloh24:
	ldr	x8, [x8, _SRBM_INT_CNTL@GOTPAGEOFF]
Lloh25:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_WREG32
Lloh26:
	adrp	x8, _SRBM_INT_ACK@GOTPAGE
Lloh27:
	ldr	x8, [x8, _SRBM_INT_ACK@GOTPAGEOFF]
Lloh28:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_WREG32
Lloh29:
	adrp	x8, _BIF_FB_EN@GOTPAGE
Lloh30:
	ldr	x8, [x8, _BIF_FB_EN@GOTPAGEOFF]
Lloh31:
	adrp	x9, _FB_READ_EN@GOTPAGE
Lloh32:
	ldr	x9, [x9, _FB_READ_EN@GOTPAGEOFF]
Lloh33:
	ldr	w0, [x8]
Lloh34:
	ldr	w8, [x9]
Lloh35:
	adrp	x9, _FB_WRITE_EN@GOTPAGE
Lloh36:
	ldr	x9, [x9, _FB_WRITE_EN@GOTPAGEOFF]
Lloh37:
	ldr	w9, [x9]
	orr	w1, w9, w8
	bl	_WREG32
Lloh38:
	adrp	x8, _MC_SHARED_CHMAP@GOTPAGE
Lloh39:
	ldr	x8, [x8, _MC_SHARED_CHMAP@GOTPAGEOFF]
Lloh40:
	ldr	w0, [x8]
	bl	_RREG32
Lloh41:
	adrp	x8, _MC_ARB_RAMCFG@GOTPAGE
Lloh42:
	ldr	x8, [x8, _MC_ARB_RAMCFG@GOTPAGEOFF]
Lloh43:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x21, x0
	ldr	w8, [x19, #12]
	mov	w9, #256
	stp	w8, w9, [x19, #60]
Lloh44:
	adrp	x8, _NOOFCOLS_MASK@GOTPAGE
Lloh45:
	ldr	x8, [x8, _NOOFCOLS_MASK@GOTPAGEOFF]
Lloh46:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh47:
	adrp	x9, _NOOFCOLS_SHIFT@GOTPAGE
Lloh48:
	ldr	x9, [x9, _NOOFCOLS_SHIFT@GOTPAGEOFF]
Lloh49:
	ldr	w9, [x9]
	asr	w8, w8, w9
	add	w8, w8, #8
	mov	w9, #4
	lsl	w8, w9, w8
	add	w10, w8, #1023
	cmp	w8, #0
	csel	w10, w10, w8, lt
	asr	w10, w10, #10
	mov	w11, #5119
	cmp	w8, w11
	csel	w8, w9, w10, gt
	str	w8, [x19, #68]
Lloh50:
	adrp	x9, lCPI0_5@PAGE
Lloh51:
	ldr	d0, [x9, lCPI0_5@PAGEOFF]
	str	d0, [x19, #72]
	mov	w9, #64
	str	w9, [x19, #80]
Lloh52:
	adrp	x24, _ROW_SIZE_MASK@GOTPAGE
Lloh53:
	ldr	x24, [x24, _ROW_SIZE_MASK@GOTPAGEOFF]
	ldr	w9, [x24]
	bic	w20, w23, w9
	cmp	w8, #2
	cset	w9, eq
	mov	w10, #2
	cmp	w8, #4
	csel	w0, w10, w9, eq
	bl	_ROW_SIZE
	orr	w20, w0, w20
	ldr	w8, [x19, #60]
	sub	w8, w8, #1
	cmp	w8, #3
	b.hi	LBB0_11
; %bb.10:
Lloh54:
	adrp	x9, l_switch.table.cik_gpu_init@PAGE
Lloh55:
	add	x9, x9, l_switch.table.cik_gpu_init@PAGEOFF
	ldr	w8, [x9, w8, sxtw #2]
	b	LBB0_12
LBB0_11:
	mov	w8, #3
LBB0_12:
Lloh56:
	adrp	x9, _NOOFBANK_MASK@GOTPAGE
Lloh57:
	ldr	x9, [x9, _NOOFBANK_MASK@GOTPAGEOFF]
Lloh58:
	ldr	w9, [x9]
	and	w9, w9, w21
Lloh59:
	adrp	x10, _NOOFBANK_SHIFT@GOTPAGE
Lloh60:
	ldr	x10, [x10, _NOOFBANK_SHIFT@GOTPAGEOFF]
Lloh61:
	ldr	w10, [x10]
	asr	w9, w9, w10
	orr	w8, w8, w9, lsl #4
Lloh62:
	adrp	x9, _PIPE_INTERLEAVE_SIZE_MASK@GOTPAGE
Lloh63:
	ldr	x9, [x9, _PIPE_INTERLEAVE_SIZE_MASK@GOTPAGEOFF]
Lloh64:
	ldr	w9, [x9]
	and	w9, w9, w20
Lloh65:
	adrp	x10, _PIPE_INTERLEAVE_SIZE_SHIFT@GOTPAGE
Lloh66:
	ldr	x10, [x10, _PIPE_INTERLEAVE_SIZE_SHIFT@GOTPAGEOFF]
Lloh67:
	ldr	w10, [x10]
	asr	w9, w9, w10
	orr	w8, w8, w9, lsl #8
	ldr	w9, [x24]
Lloh68:
	adrp	x10, _ROW_SIZE_SHIFT@GOTPAGE
Lloh69:
	ldr	x10, [x10, _ROW_SIZE_SHIFT@GOTPAGEOFF]
	and	w9, w9, w20
Lloh70:
	ldr	w10, [x10]
	asr	w9, w9, w10
	orr	w8, w8, w9, lsl #12
	str	w8, [x19, #84]
	ldr	w0, [x22]
	mov	x1, x20
	bl	_WREG32
Lloh71:
	adrp	x8, _HDP_ADDR_CONFIG@GOTPAGE
Lloh72:
	ldr	x8, [x8, _HDP_ADDR_CONFIG@GOTPAGEOFF]
Lloh73:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh74:
	adrp	x8, _DMIF_ADDR_CALC@GOTPAGE
Lloh75:
	ldr	x8, [x8, _DMIF_ADDR_CALC@GOTPAGEOFF]
Lloh76:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh77:
	adrp	x22, _SDMA0_TILING_CONFIG@GOTPAGE
Lloh78:
	ldr	x22, [x22, _SDMA0_TILING_CONFIG@GOTPAGEOFF]
	ldr	w8, [x22]
Lloh79:
	adrp	x9, _SDMA0_REGISTER_OFFSET@GOTPAGE
Lloh80:
	ldr	x9, [x9, _SDMA0_REGISTER_OFFSET@GOTPAGEOFF]
Lloh81:
	ldr	w9, [x9]
	add	w0, w9, w8
	and	w21, w20, #0x70
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x22]
Lloh82:
	adrp	x9, _SDMA1_REGISTER_OFFSET@GOTPAGE
Lloh83:
	ldr	x9, [x9, _SDMA1_REGISTER_OFFSET@GOTPAGEOFF]
Lloh84:
	ldr	w9, [x9]
	add	w0, w9, w8
	mov	x1, x21
	bl	_WREG32
Lloh85:
	adrp	x8, _UVD_UDEC_ADDR_CONFIG@GOTPAGE
Lloh86:
	ldr	x8, [x8, _UVD_UDEC_ADDR_CONFIG@GOTPAGEOFF]
Lloh87:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh88:
	adrp	x8, _UVD_UDEC_DB_ADDR_CONFIG@GOTPAGE
Lloh89:
	ldr	x8, [x8, _UVD_UDEC_DB_ADDR_CONFIG@GOTPAGEOFF]
Lloh90:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh91:
	adrp	x8, _UVD_UDEC_DBW_ADDR_CONFIG@GOTPAGE
Lloh92:
	ldr	x8, [x8, _UVD_UDEC_DBW_ADDR_CONFIG@GOTPAGEOFF]
Lloh93:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
	mov	x0, x19
	bl	_cik_tiling_mode_table_init
	ldr	w1, [x19, #8]
	ldp	w2, w3, [x19, #20]
	mov	x0, x19
	bl	_cik_setup_rb
	str	xzr, [x19, #88]
	ldr	w9, [x19, #8]
	cmp	w9, #1
	b.lt	LBB0_19
; %bb.13:
	mov	w20, #0
	ldr	w8, [x19, #20]
	b	LBB0_15
LBB0_14:                                ;   in Loop: Header=BB0_15 Depth=1
	add	w20, w20, #1
	cmp	w20, w9
	b.ge	LBB0_19
LBB0_15:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_17 Depth 2
	cmp	w8, #1
	b.lt	LBB0_14
; %bb.16:                               ;   in Loop: Header=BB0_15 Depth=1
	mov	w21, #0
LBB0_17:                                ;   Parent Loop BB0_15 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	mov	x0, x19
	mov	x1, x20
	mov	x2, x21
	bl	_cik_get_cu_active_bitmap
	bl	_hweight32
	ldr	x8, [x19, #88]
	add	x8, x8, x0
	str	x8, [x19, #88]
	add	w21, w21, #1
	ldr	w8, [x19, #20]
	cmp	w21, w8
	b.lt	LBB0_17
; %bb.18:                               ;   in Loop: Header=BB0_15 Depth=1
	ldr	w9, [x19, #8]
	b	LBB0_14
LBB0_19:
Lloh94:
	adrp	x8, _CP_MEQ_THRESHOLDS@GOTPAGE
Lloh95:
	ldr	x8, [x8, _CP_MEQ_THRESHOLDS@GOTPAGEOFF]
Lloh96:
	ldr	w20, [x8]
	mov	w0, #48
	bl	_MEQ1_START
	mov	x21, x0
	mov	w0, #96
	bl	_MEQ2_START
	orr	w1, w0, w21
	mov	x0, x20
	bl	_WREG32
Lloh97:
	adrp	x8, _SX_DEBUG_1@GOTPAGE
Lloh98:
	ldr	x8, [x8, _SX_DEBUG_1@GOTPAGEOFF]
Lloh99:
	ldr	w0, [x8]
	mov	w1, #32
	bl	_WREG32
Lloh100:
	adrp	x8, _TA_CNTL_AUX@GOTPAGE
Lloh101:
	ldr	x8, [x8, _TA_CNTL_AUX@GOTPAGEOFF]
Lloh102:
	ldr	w0, [x8]
	mov	w1, #65536
	bl	_WREG32
Lloh103:
	adrp	x20, _SPI_CONFIG_CNTL@GOTPAGE
Lloh104:
	ldr	x20, [x20, _SPI_CONFIG_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	orr	w1, w0, #0x3000000
	ldr	w0, [x20]
	bl	_WREG32
Lloh105:
	adrp	x22, _SQ_CONFIG@GOTPAGE
Lloh106:
	ldr	x22, [x22, _SQ_CONFIG@GOTPAGEOFF]
	ldr	w0, [x22]
	mov	w1, #1
	bl	_WREG32
Lloh107:
	adrp	x8, _DB_DEBUG@GOTPAGE
Lloh108:
	ldr	x8, [x8, _DB_DEBUG@GOTPAGEOFF]
Lloh109:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh110:
	adrp	x20, _DB_DEBUG2@GOTPAGE
Lloh111:
	ldr	x20, [x20, _DB_DEBUG2@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	and	w8, w0, #0xff00000
	orr	w1, w8, #0x400
	ldr	w0, [x20]
	bl	_WREG32
Lloh112:
	adrp	x20, _DB_DEBUG3@GOTPAGE
Lloh113:
	ldr	x20, [x20, _DB_DEBUG3@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	and	w8, w0, #0xffffffe3
	mov	w9, #512
	movk	w9, #2, lsl #16
	orr	w1, w8, w9
	ldr	w0, [x20]
	bl	_WREG32
Lloh114:
	adrp	x20, _CB_HW_CONTROL@GOTPAGE
Lloh115:
	ldr	x20, [x20, _CB_HW_CONTROL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	mov	w8, #33288
	movk	w8, #1, lsl #16
	orr	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32
Lloh116:
	adrp	x8, _SPI_CONFIG_CNTL_1@GOTPAGE
Lloh117:
	ldr	x8, [x8, _SPI_CONFIG_CNTL_1@GOTPAGEOFF]
Lloh118:
	ldr	w20, [x8]
	mov	w0, #4
	bl	_VTX_DONE_DELAY
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
Lloh119:
	adrp	x8, _PA_SC_FIFO_SIZE@GOTPAGE
Lloh120:
	ldr	x8, [x8, _PA_SC_FIFO_SIZE@GOTPAGEOFF]
Lloh121:
	ldr	w20, [x8]
	ldr	w0, [x19, #44]
	bl	_SC_FRONTEND_PRIM_FIFO_SIZE
	mov	x21, x0
	ldr	w0, [x19, #48]
	bl	_SC_BACKEND_PRIM_FIFO_SIZE
	orr	w21, w0, w21
	ldr	w0, [x19, #52]
	bl	_SC_HIZ_TILE_FIFO_SIZE
	orr	w21, w21, w0
	ldr	w0, [x19, #56]
	bl	_SC_EARLYZ_TILE_FIFO_SIZE
	orr	w1, w21, w0
	mov	x0, x20
	bl	_WREG32
Lloh122:
	adrp	x8, _VGT_NUM_INSTANCES@GOTPAGE
Lloh123:
	ldr	x8, [x8, _VGT_NUM_INSTANCES@GOTPAGEOFF]
Lloh124:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_WREG32
Lloh125:
	adrp	x8, _CP_PERFMON_CNTL@GOTPAGE
Lloh126:
	ldr	x8, [x8, _CP_PERFMON_CNTL@GOTPAGEOFF]
Lloh127:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x22]
	mov	w1, #0
	bl	_WREG32
Lloh128:
	adrp	x8, _PA_SC_FORCE_EOV_MAX_CNTS@GOTPAGE
Lloh129:
	ldr	x8, [x8, _PA_SC_FORCE_EOV_MAX_CNTS@GOTPAGEOFF]
Lloh130:
	ldr	w19, [x8]
	mov	w0, #4095
	bl	_FORCE_EOV_MAX_CLK_CNT
	mov	x20, x0
	mov	w0, #255
	bl	_FORCE_EOV_MAX_REZ_CNT
	orr	w1, w0, w20
	mov	x0, x19
	bl	_WREG32
Lloh131:
	adrp	x8, _VGT_CACHE_INVALIDATION@GOTPAGE
Lloh132:
	ldr	x8, [x8, _VGT_CACHE_INVALIDATION@GOTPAGEOFF]
Lloh133:
	ldr	w19, [x8]
Lloh134:
	adrp	x8, _VC_AND_TC@GOTPAGE
Lloh135:
	ldr	x8, [x8, _VC_AND_TC@GOTPAGEOFF]
Lloh136:
	ldr	w0, [x8]
	bl	_CACHE_INVALIDATION
	mov	x20, x0
Lloh137:
	adrp	x8, _ES_AND_GS_AUTO@GOTPAGE
Lloh138:
	ldr	x8, [x8, _ES_AND_GS_AUTO@GOTPAGEOFF]
Lloh139:
	ldr	w0, [x8]
	bl	_AUTO_INVLD_EN
	orr	w1, w0, w20
	mov	x0, x19
	bl	_WREG32
Lloh140:
	adrp	x8, _VGT_GS_VERTEX_REUSE@GOTPAGE
Lloh141:
	ldr	x8, [x8, _VGT_GS_VERTEX_REUSE@GOTPAGEOFF]
Lloh142:
	ldr	w0, [x8]
	mov	w1, #16
	bl	_WREG32
Lloh143:
	adrp	x8, _PA_SC_LINE_STIPPLE_STATE@GOTPAGE
Lloh144:
	ldr	x8, [x8, _PA_SC_LINE_STIPPLE_STATE@GOTPAGEOFF]
Lloh145:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh146:
	adrp	x19, _HDP_MISC_CNTL@GOTPAGE
Lloh147:
	ldr	x19, [x19, _HDP_MISC_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32
Lloh148:
	adrp	x8, _HDP_FLUSH_INVALIDATE_CACHE@GOTPAGE
Lloh149:
	ldr	x8, [x8, _HDP_FLUSH_INVALIDATE_CACHE@GOTPAGEOFF]
Lloh150:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x19]
	bl	_WREG32
Lloh151:
	adrp	x19, _HDP_HOST_PATH_CNTL@GOTPAGE
Lloh152:
	ldr	x19, [x19, _HDP_HOST_PATH_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32
	mov	x1, x0
	ldr	w0, [x19]
	bl	_WREG32
Lloh153:
	adrp	x8, _PA_CL_ENHANCE@GOTPAGE
Lloh154:
	ldr	x8, [x8, _PA_CL_ENHANCE@GOTPAGEOFF]
Lloh155:
	ldr	w19, [x8]
Lloh156:
	adrp	x8, _CLIP_VTX_REORDER_ENA@GOTPAGE
Lloh157:
	ldr	x8, [x8, _CLIP_VTX_REORDER_ENA@GOTPAGEOFF]
Lloh158:
	ldr	w20, [x8]
	mov	w0, #3
	bl	_NUM_CLIP_SEQ
	orr	w1, w0, w20
	mov	x0, x19
	bl	_WREG32
Lloh159:
	adrp	x8, _PA_SC_ENHANCE@GOTPAGE
Lloh160:
	ldr	x8, [x8, _PA_SC_ENHANCE@GOTPAGEOFF]
Lloh161:
	ldr	w0, [x8]
Lloh162:
	adrp	x8, _ENABLE_PA_SC_OUT_OF_ORDER@GOTPAGE
Lloh163:
	ldr	x8, [x8, _ENABLE_PA_SC_OUT_OF_ORDER@GOTPAGEOFF]
Lloh164:
	ldr	w1, [x8]
	bl	_WREG32
	mov	w0, #50
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_udelay
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdr	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpAdrp	Lloh6, Lloh8
	.loh AdrpLdr	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdr	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdr	Lloh14, Lloh15
	.loh AdrpLdr	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdr	Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh33
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpAdd	Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGot	Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh162, Lloh163, Lloh164
	.loh AdrpLdrGotLdr	Lloh159, Lloh160, Lloh161
	.loh AdrpLdrGotLdr	Lloh156, Lloh157, Lloh158
	.loh AdrpLdrGotLdr	Lloh153, Lloh154, Lloh155
	.loh AdrpLdrGot	Lloh151, Lloh152
	.loh AdrpLdrGotLdr	Lloh148, Lloh149, Lloh150
	.loh AdrpLdrGot	Lloh146, Lloh147
	.loh AdrpLdrGotLdr	Lloh143, Lloh144, Lloh145
	.loh AdrpLdrGotLdr	Lloh140, Lloh141, Lloh142
	.loh AdrpLdrGotLdr	Lloh137, Lloh138, Lloh139
	.loh AdrpLdrGotLdr	Lloh134, Lloh135, Lloh136
	.loh AdrpLdrGotLdr	Lloh131, Lloh132, Lloh133
	.loh AdrpLdrGotLdr	Lloh128, Lloh129, Lloh130
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGot	Lloh114, Lloh115
	.loh AdrpLdrGot	Lloh112, Lloh113
	.loh AdrpLdrGot	Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGot	Lloh105, Lloh106
	.loh AdrpLdrGot	Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.cfi_endproc
                                        ; -- End function
	.comm	_GB_ADDR_CONFIG,4,2             ; @GB_ADDR_CONFIG
	.comm	_BONAIRE_GB_ADDR_CONFIG_GOLDEN,4,2 ; @BONAIRE_GB_ADDR_CONFIG_GOLDEN
	.comm	_HAWAII_GB_ADDR_CONFIG_GOLDEN,4,2 ; @HAWAII_GB_ADDR_CONFIG_GOLDEN
	.comm	_GRBM_CNTL,4,2                  ; @GRBM_CNTL
	.comm	_SRBM_INT_CNTL,4,2              ; @SRBM_INT_CNTL
	.comm	_SRBM_INT_ACK,4,2               ; @SRBM_INT_ACK
	.comm	_BIF_FB_EN,4,2                  ; @BIF_FB_EN
	.comm	_FB_READ_EN,4,2                 ; @FB_READ_EN
	.comm	_FB_WRITE_EN,4,2                ; @FB_WRITE_EN
	.comm	_MC_SHARED_CHMAP,4,2            ; @MC_SHARED_CHMAP
	.comm	_MC_ARB_RAMCFG,4,2              ; @MC_ARB_RAMCFG
	.comm	_NOOFCOLS_MASK,4,2              ; @NOOFCOLS_MASK
	.comm	_NOOFCOLS_SHIFT,4,2             ; @NOOFCOLS_SHIFT
	.comm	_ROW_SIZE_MASK,4,2              ; @ROW_SIZE_MASK
	.comm	_NOOFBANK_MASK,4,2              ; @NOOFBANK_MASK
	.comm	_NOOFBANK_SHIFT,4,2             ; @NOOFBANK_SHIFT
	.comm	_PIPE_INTERLEAVE_SIZE_MASK,4,2  ; @PIPE_INTERLEAVE_SIZE_MASK
	.comm	_PIPE_INTERLEAVE_SIZE_SHIFT,4,2 ; @PIPE_INTERLEAVE_SIZE_SHIFT
	.comm	_ROW_SIZE_SHIFT,4,2             ; @ROW_SIZE_SHIFT
	.comm	_HDP_ADDR_CONFIG,4,2            ; @HDP_ADDR_CONFIG
	.comm	_DMIF_ADDR_CALC,4,2             ; @DMIF_ADDR_CALC
	.comm	_SDMA0_TILING_CONFIG,4,2        ; @SDMA0_TILING_CONFIG
	.comm	_SDMA0_REGISTER_OFFSET,4,2      ; @SDMA0_REGISTER_OFFSET
	.comm	_SDMA1_REGISTER_OFFSET,4,2      ; @SDMA1_REGISTER_OFFSET
	.comm	_UVD_UDEC_ADDR_CONFIG,4,2       ; @UVD_UDEC_ADDR_CONFIG
	.comm	_UVD_UDEC_DB_ADDR_CONFIG,4,2    ; @UVD_UDEC_DB_ADDR_CONFIG
	.comm	_UVD_UDEC_DBW_ADDR_CONFIG,4,2   ; @UVD_UDEC_DBW_ADDR_CONFIG
	.comm	_CP_MEQ_THRESHOLDS,4,2          ; @CP_MEQ_THRESHOLDS
	.comm	_SX_DEBUG_1,4,2                 ; @SX_DEBUG_1
	.comm	_TA_CNTL_AUX,4,2                ; @TA_CNTL_AUX
	.comm	_SPI_CONFIG_CNTL,4,2            ; @SPI_CONFIG_CNTL
	.comm	_SQ_CONFIG,4,2                  ; @SQ_CONFIG
	.comm	_DB_DEBUG,4,2                   ; @DB_DEBUG
	.comm	_DB_DEBUG2,4,2                  ; @DB_DEBUG2
	.comm	_DB_DEBUG3,4,2                  ; @DB_DEBUG3
	.comm	_CB_HW_CONTROL,4,2              ; @CB_HW_CONTROL
	.comm	_SPI_CONFIG_CNTL_1,4,2          ; @SPI_CONFIG_CNTL_1
	.comm	_PA_SC_FIFO_SIZE,4,2            ; @PA_SC_FIFO_SIZE
	.comm	_VGT_NUM_INSTANCES,4,2          ; @VGT_NUM_INSTANCES
	.comm	_CP_PERFMON_CNTL,4,2            ; @CP_PERFMON_CNTL
	.comm	_PA_SC_FORCE_EOV_MAX_CNTS,4,2   ; @PA_SC_FORCE_EOV_MAX_CNTS
	.comm	_VGT_CACHE_INVALIDATION,4,2     ; @VGT_CACHE_INVALIDATION
	.comm	_VC_AND_TC,4,2                  ; @VC_AND_TC
	.comm	_ES_AND_GS_AUTO,4,2             ; @ES_AND_GS_AUTO
	.comm	_VGT_GS_VERTEX_REUSE,4,2        ; @VGT_GS_VERTEX_REUSE
	.comm	_PA_SC_LINE_STIPPLE_STATE,4,2   ; @PA_SC_LINE_STIPPLE_STATE
	.comm	_HDP_MISC_CNTL,4,2              ; @HDP_MISC_CNTL
	.comm	_HDP_FLUSH_INVALIDATE_CACHE,4,2 ; @HDP_FLUSH_INVALIDATE_CACHE
	.comm	_HDP_HOST_PATH_CNTL,4,2         ; @HDP_HOST_PATH_CNTL
	.comm	_PA_CL_ENHANCE,4,2              ; @PA_CL_ENHANCE
	.comm	_CLIP_VTX_REORDER_ENA,4,2       ; @CLIP_VTX_REORDER_ENA
	.comm	_PA_SC_ENHANCE,4,2              ; @PA_SC_ENHANCE
	.comm	_ENABLE_PA_SC_OUT_OF_ORDER,4,2  ; @ENABLE_PA_SC_OUT_OF_ORDER
	.no_dead_strip	_cik_gpu_init
	.section	__TEXT,__literal16,16byte_literals
	.p2align	2                               ; @switch.table.cik_gpu_init
l_switch.table.cik_gpu_init:
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	3                               ; 0x3
	.long	2                               ; 0x2

.subsections_via_symbols
