	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dispc_ovl_set_accu_uv
_dispc_ovl_set_accu_uv:                 ## @dispc_ovl_set_accu_uv
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %r15
	movl	24(%rbp), %eax
	movq	_DRM_MODE_ROTATE_MASK@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	andl	32(%rbp), %esi
	addl	$-128, %esi
	cmpl	$2, %esi
	ja	LBB0_1
## %bb.2:
	movslq	%esi, %rsi
	leaq	l_switch.table.dispc_ovl_set_accu_uv(%rip), %rdi
	movq	(%rdi,%rsi,8), %rbx
	jmp	LBB0_3
LBB0_1:
	xorl	%ebx, %ebx
LBB0_3:
	leal	-132(%rax), %esi
	cmpl	$2, %esi
	jae	LBB0_5
## %bb.4:
	leaq	_dispc_ovl_set_accu_uv.accu_yuv(%rip), %rsi
	jmp	LBB0_7
LBB0_5:
	cmpl	$134, %eax
	jne	LBB0_8
## %bb.6:
	cmpl	$0, 16(%rbp)
	leaq	_dispc_ovl_set_accu_uv.accu_nv12(%rip), %rax
	leaq	_dispc_ovl_set_accu_uv.accu_nv12_ilace(%rip), %rsi
	cmoveq	%rax, %rsi
LBB0_7:
	shll	$10, %edx
	movl	%edx, %eax
	cltd
	idivl	%r8d
	movl	%eax, %edi
	shll	$10, %ecx
	movl	%ecx, %eax
	cltd
	idivl	%r9d
	movl	%eax, %r9d
	shlq	$5, %rbx
	movl	(%rsi,%rbx), %eax
	imull	%edi, %eax
	cltd
	idivl	4(%rsi,%rbx)
	movl	%eax, %r8d
	leal	1023(%r8), %eax
	testl	%r8d, %r8d
	cmovnsl	%r8d, %eax
	andl	$-1024, %eax                    ## imm = 0xFC00
	imull	8(%rsi,%rbx), %edi
	subl	%eax, %r8d
	movl	%edi, %eax
	cltd
	idivl	12(%rsi,%rbx)
	movl	%eax, %r12d
	leal	1023(%r12), %eax
	testl	%r12d, %r12d
	cmovnsl	%r12d, %eax
	andl	$-1024, %eax                    ## imm = 0xFC00
	subl	%eax, %r12d
	movl	16(%rsi,%rbx), %eax
	imull	%r9d, %eax
	cltd
	idivl	20(%rsi,%rbx)
	movl	%eax, %ecx
	leal	1023(%rcx), %eax
	testl	%ecx, %ecx
	cmovnsl	%ecx, %eax
	andl	$-1024, %eax                    ## imm = 0xFC00
	subl	%eax, %ecx
	imull	24(%rsi,%rbx), %r9d
	movl	%r9d, %eax
	cltd
	idivl	28(%rsi,%rbx)
	movl	%eax, %ebx
	leal	1023(%rbx), %eax
	testl	%ebx, %ebx
	cmovnsl	%ebx, %eax
	andl	$-1024, %eax                    ## imm = 0xFC00
	subl	%eax, %ebx
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%r8d, %edx
                                        ## kill: def $ecx killed $ecx killed $rcx
	callq	_dispc_ovl_set_vid_accu2_0
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%r12d, %edx
	movl	%ebx, %ecx
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_dispc_ovl_set_vid_accu2_1      ## TAILCALL
LBB0_8:
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_BUG                            ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__const
	.p2align	4                               ## @dispc_ovl_set_accu_uv.accu_nv12
_dispc_ovl_set_accu_uv.accu_nv12:
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	4294967295                      ## 0xffffffff
	.long	2                               ## 0x2
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	2                               ## 0x2
	.long	4294967293                      ## 0xfffffffd
	.long	4                               ## 0x4
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	4294967295                      ## 0xffffffff
	.long	2                               ## 0x2
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	4294967295                      ## 0xffffffff
	.long	2                               ## 0x2
	.long	4294967295                      ## 0xffffffff
	.long	2                               ## 0x2
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1

	.p2align	4                               ## @dispc_ovl_set_accu_uv.accu_nv12_ilace
_dispc_ovl_set_accu_uv.accu_nv12_ilace:
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	4294967293                      ## 0xfffffffd
	.long	4                               ## 0x4
	.long	4294967295                      ## 0xffffffff
	.long	4                               ## 0x4
	.long	4294967295                      ## 0xffffffff
	.long	4                               ## 0x4
	.long	4294967293                      ## 0xfffffffd
	.long	4                               ## 0x4
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	4294967295                      ## 0xffffffff
	.long	4                               ## 0x4
	.long	4294967293                      ## 0xfffffffd
	.long	4                               ## 0x4
	.long	4294967293                      ## 0xfffffffd
	.long	4                               ## 0x4
	.long	4294967293                      ## 0xfffffffd
	.long	4                               ## 0x4
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1

	.p2align	4                               ## @dispc_ovl_set_accu_uv.accu_yuv
_dispc_ovl_set_accu_uv.accu_yuv:
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.long	1                               ## 0x1

	.comm	_DRM_MODE_ROTATE_MASK,4,2       ## @DRM_MODE_ROTATE_MASK
	.no_dead_strip	_dispc_ovl_set_accu_uv
	.p2align	3                               ## @switch.table.dispc_ovl_set_accu_uv
l_switch.table.dispc_ovl_set_accu_uv:
	.quad	3                               ## 0x3
	.quad	1                               ## 0x1
	.quad	2                               ## 0x2

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dispc_ovl_set_accu_uv
_dispc_ovl_set_accu_uv:                 ; @dispc_ovl_set_accu_uv
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x1
	mov	x20, x0
	ldr	w8, [x29, #16]
Lloh0:
	adrp	x9, _DRM_MODE_ROTATE_MASK@GOTPAGE
Lloh1:
	ldr	x9, [x9, _DRM_MODE_ROTATE_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	and	w8, w9, w8
	sub	w8, w8, #128
	cmp	w8, #2
	b.hi	LBB0_2
; %bb.1:
Lloh3:
	adrp	x9, l_switch.table.dispc_ovl_set_accu_uv@PAGE
Lloh4:
	add	x9, x9, l_switch.table.dispc_ovl_set_accu_uv@PAGEOFF
	ldr	x8, [x9, w8, sxtw #3]
	b	LBB0_3
LBB0_2:
	mov	x8, #0
LBB0_3:
	sub	w9, w7, #132
	cmp	w9, #2
	b.hs	LBB0_5
; %bb.4:
Lloh5:
	adrp	x9, _dispc_ovl_set_accu_uv.accu_yuv@PAGE
Lloh6:
	add	x9, x9, _dispc_ovl_set_accu_uv.accu_yuv@PAGEOFF
	b	LBB0_7
LBB0_5:
	cmp	w7, #134
	b.ne	LBB0_8
; %bb.6:
Lloh7:
	adrp	x9, _dispc_ovl_set_accu_uv.accu_nv12_ilace@PAGE
Lloh8:
	add	x9, x9, _dispc_ovl_set_accu_uv.accu_nv12_ilace@PAGEOFF
Lloh9:
	adrp	x10, _dispc_ovl_set_accu_uv.accu_nv12@PAGE
Lloh10:
	add	x10, x10, _dispc_ovl_set_accu_uv.accu_nv12@PAGEOFF
	cmp	w6, #0
	csel	x9, x10, x9, eq
LBB0_7:
	lsl	w10, w2, #10
	sdiv	w10, w10, w4
	lsl	w11, w3, #10
	sdiv	w11, w11, w5
	add	x8, x9, x8, lsl #5
	ldp	w9, w12, [x8]
	mul	w9, w9, w10
	sdiv	w9, w9, w12
	and	w12, w9, #0x3ff
	negs	w9, w9
	and	w9, w9, #0x3ff
	csneg	w2, w12, w9, mi
	ldp	w9, w12, [x8, #8]
	mul	w9, w9, w10
	sdiv	w9, w9, w12
	and	w10, w9, #0x3ff
	negs	w9, w9
	and	w9, w9, #0x3ff
	csneg	w21, w10, w9, mi
	ldp	w9, w10, [x8, #16]
	mul	w9, w9, w11
	sdiv	w9, w9, w10
	and	w10, w9, #0x3ff
	negs	w9, w9
	and	w9, w9, #0x3ff
	csneg	w3, w10, w9, mi
	ldp	w9, w8, [x8, #24]
	mul	w9, w9, w11
	sdiv	w8, w9, w8
	and	w9, w8, #0x3ff
	negs	w8, w8
	and	w8, w8, #0x3ff
	csneg	w22, w9, w8, mi
	mov	x0, x20
	mov	x1, x19
	bl	_dispc_ovl_set_vid_accu2_0
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	mov	x3, x22
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_dispc_ovl_set_vid_accu2_1
LBB0_8:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_BUG
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpAdd	Lloh9, Lloh10
	.loh AdrpAdd	Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__const
	.p2align	2                               ; @dispc_ovl_set_accu_uv.accu_nv12
_dispc_ovl_set_accu_uv.accu_nv12:
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	4294967293                      ; 0xfffffffd
	.long	4                               ; 0x4
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1

	.p2align	2                               ; @dispc_ovl_set_accu_uv.accu_nv12_ilace
_dispc_ovl_set_accu_uv.accu_nv12_ilace:
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	4294967293                      ; 0xfffffffd
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	4294967293                      ; 0xfffffffd
	.long	4                               ; 0x4
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	4294967293                      ; 0xfffffffd
	.long	4                               ; 0x4
	.long	4294967293                      ; 0xfffffffd
	.long	4                               ; 0x4
	.long	4294967293                      ; 0xfffffffd
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1

	.p2align	2                               ; @dispc_ovl_set_accu_uv.accu_yuv
_dispc_ovl_set_accu_uv.accu_yuv:
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	1                               ; 0x1

	.comm	_DRM_MODE_ROTATE_MASK,4,2       ; @DRM_MODE_ROTATE_MASK
	.no_dead_strip	_dispc_ovl_set_accu_uv
	.p2align	3                               ; @switch.table.dispc_ovl_set_accu_uv
l_switch.table.dispc_ovl_set_accu_uv:
	.quad	3                               ; 0x3
	.quad	1                               ; 0x1
	.quad	2                               ; 0x2

.subsections_via_symbols
