	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_mmhub_v9_4_get_clockgating     ## -- Begin function mmhub_v9_4_get_clockgating
	.p2align	4, 0x90
_mmhub_v9_4_get_clockgating:            ## @mmhub_v9_4_get_clockgating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movl	$0, (%r14)
LBB0_2:
	movq	_MMHUB@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	movq	_mmATCL2_0_ATC_L2_MISC_CG@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	%eax, %ebx
	movl	(%r15), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK@GOTPCREL(%rip), %rcx
	testl	%ebx, (%rcx)
	je	LBB0_5
## %bb.3:
	movq	_DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPCREL(%rip), %rcx
	movq	_DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	movq	_DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	_DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	_DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	_DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	testl	%eax, %edx
	jne	LBB0_5
## %bb.4:
	movq	_AMD_CG_SUPPORT_MC_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r14)
LBB0_5:
	movq	_ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_7
## %bb.6:
	movq	_AMD_CG_SUPPORT_MC_LS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r14)
LBB0_7:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MMHUB,4,2                      ## @MMHUB
	.comm	_mmATCL2_0_ATC_L2_MISC_CG,4,2   ## @mmATCL2_0_ATC_L2_MISC_CG
	.comm	_ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK,4,2 ## @ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK
	.comm	_AMD_CG_SUPPORT_MC_MGCG,4,2     ## @AMD_CG_SUPPORT_MC_MGCG
	.comm	_ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK,4,2 ## @ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK
	.comm	_AMD_CG_SUPPORT_MC_LS,4,2       ## @AMD_CG_SUPPORT_MC_LS
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_mmhub_v9_4_get_clockgating     ; -- Begin function mmhub_v9_4_get_clockgating
	.p2align	2
_mmhub_v9_4_get_clockgating:            ; @mmhub_v9_4_get_clockgating
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x1
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_2
; %bb.1:
	str	wzr, [x19]
LBB0_2:
Lloh0:
	adrp	x21, _MMHUB@GOTPAGE
Lloh1:
	ldr	x21, [x21, _MMHUB@GOTPAGEOFF]
	ldr	w0, [x21]
Lloh2:
	adrp	x22, _mmATCL2_0_ATC_L2_MISC_CG@GOTPAGE
Lloh3:
	ldr	x22, [x22, _mmATCL2_0_ATC_L2_MISC_CG@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	w1, #0
	bl	_RREG32_SOC15
	mov	x20, x0
	ldr	w0, [x21]
	ldr	w2, [x22]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh4:
	adrp	x8, _ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK@GOTPAGE
Lloh5:
	ldr	x8, [x8, _ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_5
; %bb.3:
Lloh7:
	adrp	x8, _DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPAGE
Lloh8:
	ldr	x8, [x8, _DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
Lloh10:
	adrp	x9, _DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPAGE
Lloh11:
	ldr	x9, [x9, _DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh13:
	adrp	x9, _DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPAGE
Lloh14:
	ldr	x9, [x9, _DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
Lloh16:
	adrp	x10, _DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPAGE
Lloh17:
	ldr	x10, [x10, _DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh18:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh19:
	adrp	x9, _DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPAGE
Lloh20:
	ldr	x9, [x9, _DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh22:
	adrp	x9, _DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPAGE
Lloh23:
	ldr	x9, [x9, _DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	orr	w8, w8, w9
	tst	w8, w0
	b.ne	LBB0_5
; %bb.4:
Lloh25:
	adrp	x8, _AMD_CG_SUPPORT_MC_MGCG@GOTPAGE
Lloh26:
	ldr	x8, [x8, _AMD_CG_SUPPORT_MC_MGCG@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_5:
Lloh28:
	adrp	x8, _ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK@GOTPAGE
Lloh29:
	ldr	x8, [x8, _ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK@GOTPAGEOFF]
Lloh30:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_7
; %bb.6:
Lloh31:
	adrp	x8, _AMD_CG_SUPPORT_MC_LS@GOTPAGE
Lloh32:
	ldr	x8, [x8, _AMD_CG_SUPPORT_MC_LS@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_7:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.cfi_endproc
                                        ; -- End function
	.comm	_MMHUB,4,2                      ; @MMHUB
	.comm	_mmATCL2_0_ATC_L2_MISC_CG,4,2   ; @mmATCL2_0_ATC_L2_MISC_CG
	.comm	_ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK,4,2 ; @ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK
	.comm	_AMD_CG_SUPPORT_MC_MGCG,4,2     ; @AMD_CG_SUPPORT_MC_MGCG
	.comm	_ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK,4,2 ; @ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK
	.comm	_AMD_CG_SUPPORT_MC_LS,4,2       ; @AMD_CG_SUPPORT_MC_LS
.subsections_via_symbols
