	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_xgpu_vi_mailbox_get_irq        ## -- Begin function xgpu_vi_mailbox_get_irq
	.p2align	4, 0x90
_xgpu_vi_mailbox_get_irq:               ## @xgpu_vi_mailbox_get_irq
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	leaq	4(%rdi), %r14
	movq	%r14, %rsi
	xorl	%edx, %edx
	callq	_amdgpu_irq_get
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	LBB0_4
## %bb.1:
	leaq	8(%rbx), %rsi
	xorl	%r15d, %r15d
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_amdgpu_irq_get
	testl	%eax, %eax
	je	LBB0_3
## %bb.2:
	movl	%eax, %r12d
	movq	%rbx, %rdi
	movq	%r14, %rsi
	xorl	%edx, %edx
	callq	_amdgpu_irq_put
	movl	%r12d, %r15d
	jmp	LBB0_4
LBB0_3:
	movq	_xgpu_vi_mailbox_flr_work@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_INIT_WORK
LBB0_4:
	movl	%r15d, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_xgpu_vi_mailbox_flr_work,4,2   ## @xgpu_vi_mailbox_flr_work
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_xgpu_vi_mailbox_get_irq        ; -- Begin function xgpu_vi_mailbox_get_irq
	.p2align	2
_xgpu_vi_mailbox_get_irq:               ; @xgpu_vi_mailbox_get_irq
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	add	x20, x0, #4
	mov	x1, x20
	mov	w2, #0
	bl	_amdgpu_irq_get
	mov	x21, x0
	cbnz	w0, LBB0_4
; %bb.1:
	add	x1, x19, #8
	mov	x0, x19
	mov	w2, #0
	bl	_amdgpu_irq_get
	mov	x21, x0
	cbz	w0, LBB0_3
; %bb.2:
	mov	x0, x19
	mov	x1, x20
	mov	w2, #0
	bl	_amdgpu_irq_put
	b	LBB0_4
LBB0_3:
Lloh0:
	adrp	x8, _xgpu_vi_mailbox_flr_work@GOTPAGE
Lloh1:
	ldr	x8, [x8, _xgpu_vi_mailbox_flr_work@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_INIT_WORK
LBB0_4:
	mov	x0, x21
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_xgpu_vi_mailbox_flr_work,4,2   ; @xgpu_vi_mailbox_flr_work
.subsections_via_symbols
