	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vega20_apply_clocks_adjust_rules
_vega20_apply_clocks_adjust_rules:      ## @vega20_apply_clocks_adjust_rules
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	8(%rdi), %rax
	movq	16(%rdi), %rbx
	cmpl	$2, (%rax)
	jl	LBB0_3
## %bb.1:
	cmpl	$0, 24(%rax)
	je	LBB0_2
LBB0_3:
	xorl	%r13d, %r13d
LBB0_4:
	movl	4(%rax), %r15d
	movq	248(%rbx), %rax
	movl	(%rax), %eax
	movl	%eax, 256(%rbx)
	movq	_VG20_CLOCK_MAX_DEFAULT@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	%ecx, 260(%rbx)
	movl	%eax, 264(%rbx)
	movq	%rcx, 272(%rbx)
	movq	_PHM_PlatformCaps_UMDPState@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_PP_CAP
	testq	%rax, %rax
	je	LBB0_11
## %bb.5:
	movq	_VEGA20_UMD_PSTATE_GFXCLK_LEVEL@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	240(%rbx), %rax
	cmpq	%rax, %rcx
	jae	LBB0_7
## %bb.6:
	movq	248(%rbx), %rdx
	movl	(%rdx,%rcx,4), %ecx
	movl	%ecx, 256(%rbx)
	movl	%ecx, 260(%rbx)
LBB0_7:
	movq	(%r14), %rcx
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_9
## %bb.8:
	movq	248(%rbx), %rdx
	movl	(%rdx), %edx
	movl	%edx, 256(%rbx)
	movl	%edx, 260(%rbx)
LBB0_9:
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_11
## %bb.10:
	movq	248(%rbx), %rcx
	movl	-4(%rcx,%rax,4), %eax
	movl	%eax, 256(%rbx)
	movl	%eax, 260(%rbx)
LBB0_11:
	movq	208(%rbx), %rax
	movl	(%rax), %eax
	movl	%eax, 216(%rbx)
	movq	_VG20_CLOCK_MAX_DEFAULT@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	%ecx, 220(%rbx)
	movl	%eax, 224(%rbx)
	movq	%rcx, 232(%rbx)
	movl	(%r12), %edi
	callq	_PP_CAP
	testq	%rax, %rax
	je	LBB0_18
## %bb.12:
	movq	_VEGA20_UMD_PSTATE_MCLK_LEVEL@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	200(%rbx), %rax
	cmpq	%rax, %rcx
	jae	LBB0_14
## %bb.13:
	movq	208(%rbx), %rdx
	movl	(%rdx,%rcx,4), %ecx
	movl	%ecx, 216(%rbx)
	movl	%ecx, 220(%rbx)
LBB0_14:
	movq	(%r14), %rcx
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_16
## %bb.15:
	movq	208(%rbx), %rdx
	movl	(%rdx), %edx
	movl	%edx, 216(%rbx)
	movl	%edx, 220(%rbx)
LBB0_16:
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_18
## %bb.17:
	movq	208(%rbx), %rcx
	movl	-4(%rcx,%rax,4), %eax
	movl	%eax, 216(%rbx)
	movl	%eax, 220(%rbx)
LBB0_18:
	movl	224(%rbx), %edx
	movq	8(%r14), %r9
	movslq	8(%r9), %rax
	imulq	$1374389535, %rax, %rax         ## imm = 0x51EB851F
	movq	%rax, %rcx
	shrq	$63, %rcx
	sarq	$37, %rax
	addl	%ecx, %eax
	cmpl	%eax, %edx
	jge	LBB0_20
## %bb.19:
	movl	%eax, 224(%rbx)
	movl	%eax, %edx
LBB0_20:
	testb	%r13b, %r13b
	je	LBB0_28
## %bb.21:
	movq	200(%rbx), %rcx
	movq	208(%rbx), %r10
	movl	-4(%r10,%rcx,4), %r8d
	movl	%r8d, 224(%rbx)
	movl	280(%rbx), %esi
	cmpl	$2, %esi
	jl	LBB0_27
## %bb.22:
	decl	%esi
	movq	288(%rbx), %rcx
	xorl	%edi, %edi
	jmp	LBB0_23
	.p2align	4, 0x90
LBB0_26:                                ##   in Loop: Header=BB0_23 Depth=1
	incq	%rdi
	cmpq	%rdi, %rsi
	je	LBB0_27
LBB0_23:                                ## =>This Inner Loop Header: Depth=1
	cmpl	%r15d, (%rcx,%rdi,4)
	jg	LBB0_26
## %bb.24:                              ##   in Loop: Header=BB0_23 Depth=1
	movl	(%r10,%rdi,4), %edx
	cmpl	%eax, %edx
	jl	LBB0_26
## %bb.25:
	movl	%edx, 224(%rbx)
	jmp	LBB0_28
LBB0_27:
	movl	%r8d, %edx
LBB0_28:
	movq	16(%r9), %rsi
	testq	%rsi, %rsi
	je	LBB0_30
## %bb.29:
	movq	200(%rbx), %rcx
	movq	208(%rbx), %rdx
	movl	-4(%rdx,%rcx,4), %edx
	movl	%edx, 224(%rbx)
LBB0_30:
	movq	208(%rbx), %rcx
	movq	168(%rbx), %r8
	movq	200(%rbx), %rdi
	movl	-4(%rcx,%rdi,4), %edi
	cmpl	%edi, %edx
	sete	%r9b
	movl	(%r8), %edx
	movl	%edx, 176(%rbx)
	movq	_VG20_CLOCK_MAX_DEFAULT@GOTPCREL(%rip), %r15
	movq	(%r15), %rcx
	movl	%ecx, 180(%rbx)
	movl	%edx, 184(%rbx)
	movq	%rcx, 192(%rbx)
	testq	%rsi, %rsi
	jne	LBB0_33
## %bb.31:
	andb	%r9b, %r13b
	jne	LBB0_33
## %bb.32:
	cmpl	%edi, %eax
	jl	LBB0_34
LBB0_33:
	movq	160(%rbx), %rax
	movl	-4(%r8,%rax,4), %eax
	movl	%eax, 176(%rbx)
LBB0_34:
	movq	128(%rbx), %rax
	movl	(%rax), %eax
	movl	%eax, 136(%rbx)
	movl	%ecx, 140(%rbx)
	movl	%eax, 144(%rbx)
	movq	%rcx, 152(%rbx)
	movl	(%r12), %edi
	callq	_PP_CAP
	testq	%rax, %rax
	je	LBB0_39
## %bb.35:
	movq	_VEGA20_UMD_PSTATE_UVDCLK_LEVEL@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	120(%rbx), %rax
	cmpq	%rax, %rcx
	jae	LBB0_37
## %bb.36:
	movq	128(%rbx), %rdx
	movl	(%rdx,%rcx,4), %ecx
	movl	%ecx, 136(%rbx)
	movl	%ecx, 140(%rbx)
LBB0_37:
	movq	(%r14), %rcx
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_39
## %bb.38:
	movq	128(%rbx), %rcx
	movl	-4(%rcx,%rax,4), %eax
	movl	%eax, 136(%rbx)
	movl	%eax, 140(%rbx)
LBB0_39:
	movq	88(%rbx), %rax
	movl	(%rax), %eax
	movl	%eax, 96(%rbx)
	movq	(%r15), %rcx
	movl	%ecx, 100(%rbx)
	movl	%eax, 104(%rbx)
	movq	%rcx, 112(%rbx)
	movl	(%r12), %edi
	callq	_PP_CAP
	testq	%rax, %rax
	je	LBB0_44
## %bb.40:
	movq	_VEGA20_UMD_PSTATE_UVDCLK_LEVEL@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	80(%rbx), %rax
	cmpq	%rax, %rcx
	jae	LBB0_42
## %bb.41:
	movq	88(%rbx), %rdx
	movl	(%rdx,%rcx,4), %ecx
	movl	%ecx, 96(%rbx)
	movl	%ecx, 100(%rbx)
LBB0_42:
	movq	(%r14), %rcx
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_44
## %bb.43:
	movq	88(%rbx), %rcx
	movl	-4(%rcx,%rax,4), %eax
	movl	%eax, 96(%rbx)
	movl	%eax, 100(%rbx)
LBB0_44:
	movq	48(%rbx), %rax
	movl	(%rax), %eax
	movl	%eax, 56(%rbx)
	movq	(%r15), %rcx
	movl	%ecx, 60(%rbx)
	movl	%eax, 64(%rbx)
	movq	%rcx, 72(%rbx)
	movl	(%r12), %edi
	callq	_PP_CAP
	testq	%rax, %rax
	je	LBB0_49
## %bb.45:
	movq	_VEGA20_UMD_PSTATE_SOCCLK_LEVEL@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	40(%rbx), %rax
	cmpq	%rax, %rcx
	jae	LBB0_47
## %bb.46:
	movq	48(%rbx), %rdx
	movl	(%rdx,%rcx,4), %ecx
	movl	%ecx, 56(%rbx)
	movl	%ecx, 60(%rbx)
LBB0_47:
	movq	(%r14), %rcx
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_49
## %bb.48:
	movq	48(%rbx), %rcx
	movl	-4(%rcx,%rax,4), %eax
	movl	%eax, 56(%rbx)
	movl	%eax, 60(%rbx)
LBB0_49:
	movq	8(%rbx), %rax
	movl	(%rax), %eax
	movl	%eax, 16(%rbx)
	movq	(%r15), %rcx
	movl	%ecx, 20(%rbx)
	movl	%eax, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movl	(%r12), %edi
	callq	_PP_CAP
	testq	%rax, %rax
	je	LBB0_54
## %bb.50:
	movq	_VEGA20_UMD_PSTATE_VCEMCLK_LEVEL@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	(%rbx), %rax
	cmpq	%rax, %rcx
	jae	LBB0_52
## %bb.51:
	movq	8(%rbx), %rdx
	movl	(%rdx,%rcx,4), %ecx
	movl	%ecx, 16(%rbx)
	movl	%ecx, 20(%rbx)
LBB0_52:
	movq	(%r14), %rcx
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_54
## %bb.53:
	movq	8(%rbx), %rcx
	movl	-4(%rcx,%rax,4), %eax
	movl	%eax, 16(%rbx)
	movl	%eax, 20(%rbx)
LBB0_54:
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	movb	$1, %r13b
	jmp	LBB0_4
	.cfi_endproc
                                        ## -- End function
	.comm	_VG20_CLOCK_MAX_DEFAULT,8,3     ## @VG20_CLOCK_MAX_DEFAULT
	.comm	_PHM_PlatformCaps_UMDPState,4,2 ## @PHM_PlatformCaps_UMDPState
	.comm	_VEGA20_UMD_PSTATE_GFXCLK_LEVEL,8,3 ## @VEGA20_UMD_PSTATE_GFXCLK_LEVEL
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK,8,3 ## @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,8,3 ## @AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
	.comm	_VEGA20_UMD_PSTATE_MCLK_LEVEL,8,3 ## @VEGA20_UMD_PSTATE_MCLK_LEVEL
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK,8,3 ## @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
	.comm	_VEGA20_UMD_PSTATE_UVDCLK_LEVEL,8,3 ## @VEGA20_UMD_PSTATE_UVDCLK_LEVEL
	.comm	_VEGA20_UMD_PSTATE_SOCCLK_LEVEL,8,3 ## @VEGA20_UMD_PSTATE_SOCCLK_LEVEL
	.comm	_VEGA20_UMD_PSTATE_VCEMCLK_LEVEL,8,3 ## @VEGA20_UMD_PSTATE_VCEMCLK_LEVEL
	.no_dead_strip	_vega20_apply_clocks_adjust_rules
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vega20_apply_clocks_adjust_rules
_vega20_apply_clocks_adjust_rules:      ; @vega20_apply_clocks_adjust_rules
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldp	x8, x20, [x0, #8]
	ldr	w9, [x8]
	cmp	w9, #2
	b.lt	LBB0_2
; %bb.1:
	ldr	w9, [x8, #24]
	cbz	w9, LBB0_53
LBB0_2:
	mov	w24, #0
LBB0_3:
	ldr	w25, [x8, #4]
	ldr	x8, [x20, #248]
	ldr	w8, [x8]
	str	w8, [x20, #256]
Lloh0:
	adrp	x22, _VG20_CLOCK_MAX_DEFAULT@GOTPAGE
Lloh1:
	ldr	x22, [x22, _VG20_CLOCK_MAX_DEFAULT@GOTPAGEOFF]
	ldr	x9, [x22]
	str	w9, [x20, #260]
	str	w8, [x20, #264]
	str	x9, [x20, #272]
Lloh2:
	adrp	x23, _PHM_PlatformCaps_UMDPState@GOTPAGE
Lloh3:
	ldr	x23, [x23, _PHM_PlatformCaps_UMDPState@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_PP_CAP
Lloh4:
	adrp	x21, _AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPAGE
Lloh5:
	ldr	x21, [x21, _AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPAGEOFF]
	cbz	x0, LBB0_10
; %bb.4:
Lloh6:
	adrp	x8, _VEGA20_UMD_PSTATE_GFXCLK_LEVEL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _VEGA20_UMD_PSTATE_GFXCLK_LEVEL@GOTPAGEOFF]
Lloh8:
	ldr	x9, [x8]
	ldr	x8, [x20, #240]
	cmp	x9, x8
	b.hs	LBB0_6
; %bb.5:
	ldr	x10, [x20, #248]
	ldr	w9, [x10, x9, lsl #2]
	str	w9, [x20, #256]
	str	w9, [x20, #260]
LBB0_6:
	ldr	x9, [x19]
Lloh9:
	adrp	x10, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK@GOTPAGE
Lloh10:
	ldr	x10, [x10, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK@GOTPAGEOFF]
Lloh11:
	ldr	x10, [x10]
	cmp	x9, x10
	b.ne	LBB0_8
; %bb.7:
	ldr	x10, [x20, #248]
	ldr	w10, [x10]
	str	w10, [x20, #256]
	str	w10, [x20, #260]
LBB0_8:
	ldr	x10, [x21]
	cmp	x9, x10
	b.ne	LBB0_10
; %bb.9:
	ldr	x9, [x20, #248]
	add	x8, x9, x8, lsl #2
	ldur	w8, [x8, #-4]
	str	w8, [x20, #256]
	str	w8, [x20, #260]
LBB0_10:
	ldr	x8, [x20, #208]
	ldr	w8, [x8]
	ldr	x9, [x22]
	stp	w8, w9, [x20, #216]
	str	w8, [x20, #224]
	str	x9, [x20, #232]
	ldr	w0, [x23]
	bl	_PP_CAP
	cbz	x0, LBB0_17
; %bb.11:
Lloh12:
	adrp	x8, _VEGA20_UMD_PSTATE_MCLK_LEVEL@GOTPAGE
Lloh13:
	ldr	x8, [x8, _VEGA20_UMD_PSTATE_MCLK_LEVEL@GOTPAGEOFF]
Lloh14:
	ldr	x9, [x8]
	ldr	x8, [x20, #200]
	cmp	x9, x8
	b.hs	LBB0_13
; %bb.12:
	ldr	x10, [x20, #208]
	ldr	w9, [x10, x9, lsl #2]
	stp	w9, w9, [x20, #216]
LBB0_13:
	ldr	x9, [x19]
Lloh15:
	adrp	x10, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK@GOTPAGE
Lloh16:
	ldr	x10, [x10, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK@GOTPAGEOFF]
Lloh17:
	ldr	x10, [x10]
	cmp	x9, x10
	b.ne	LBB0_15
; %bb.14:
	ldr	x10, [x20, #208]
	ldr	w10, [x10]
	stp	w10, w10, [x20, #216]
LBB0_15:
	ldr	x10, [x21]
	cmp	x9, x10
	b.ne	LBB0_17
; %bb.16:
	ldr	x9, [x20, #208]
	add	x8, x9, x8, lsl #2
	ldur	w8, [x8, #-4]
	stp	w8, w8, [x20, #216]
LBB0_17:
	ldr	w9, [x20, #224]
	ldr	x10, [x19, #8]
	ldrsw	x8, [x10, #8]
	mov	w11, #34079
	movk	w11, #20971, lsl #16
	mul	x8, x8, x11
	lsr	x11, x8, #63
	asr	x8, x8, #37
	add	w8, w8, w11
	cmp	w9, w8
	b.ge	LBB0_19
; %bb.18:
	str	w8, [x20, #224]
	mov	x9, x8
LBB0_19:
	cbz	w24, LBB0_26
; %bb.20:
	ldp	x9, x11, [x20, #200]
	add	x9, x11, x9, lsl #2
	ldur	w9, [x9, #-4]
	str	w9, [x20, #224]
	ldr	w12, [x20, #280]
	cmp	w12, #2
	b.lt	LBB0_26
; %bb.21:
	sub	w12, w12, #1
	ldr	x13, [x20, #288]
	b	LBB0_23
LBB0_22:                                ;   in Loop: Header=BB0_23 Depth=1
	add	x13, x13, #4
	add	x11, x11, #4
	subs	x12, x12, #1
	b.eq	LBB0_26
LBB0_23:                                ; =>This Inner Loop Header: Depth=1
	ldr	w14, [x13]
	cmp	w14, w25
	b.gt	LBB0_22
; %bb.24:                               ;   in Loop: Header=BB0_23 Depth=1
	ldr	w14, [x11]
	cmp	w14, w8
	b.lt	LBB0_22
; %bb.25:
	str	w14, [x20, #224]
	mov	x9, x14
LBB0_26:
	ldr	x10, [x10, #16]
	cbz	x10, LBB0_28
; %bb.27:
	ldp	x11, x9, [x20, #200]
	add	x9, x9, x11, lsl #2
	ldur	w9, [x9, #-4]
	str	w9, [x20, #224]
LBB0_28:
	ldp	x12, x11, [x20, #200]
	add	x11, x11, x12, lsl #2
	ldur	w12, [x11, #-4]
	cmp	w9, w12
	cset	w13, eq
	ldr	x11, [x20, #168]
	ldr	w14, [x11]
	ldr	x9, [x22]
	stp	w14, w9, [x20, #176]
	str	w14, [x20, #184]
	str	x9, [x20, #192]
	cbnz	x10, LBB0_31
; %bb.29:
	and	w10, w24, w13
	tbnz	w10, #0, LBB0_31
; %bb.30:
	cmp	w8, w12
	b.lt	LBB0_32
LBB0_31:
	ldr	x8, [x20, #160]
	add	x8, x11, x8, lsl #2
	ldur	w8, [x8, #-4]
	str	w8, [x20, #176]
LBB0_32:
	ldr	x8, [x20, #128]
	ldr	w8, [x8]
	stp	w8, w9, [x20, #136]
	str	w8, [x20, #144]
	str	x9, [x20, #152]
	ldr	w0, [x23]
	bl	_PP_CAP
Lloh18:
	adrp	x24, _VEGA20_UMD_PSTATE_UVDCLK_LEVEL@GOTPAGE
Lloh19:
	ldr	x24, [x24, _VEGA20_UMD_PSTATE_UVDCLK_LEVEL@GOTPAGEOFF]
	cbz	x0, LBB0_37
; %bb.33:
	ldr	x9, [x24]
	ldr	x8, [x20, #120]
	cmp	x9, x8
	b.hs	LBB0_35
; %bb.34:
	ldr	x10, [x20, #128]
	ldr	w9, [x10, x9, lsl #2]
	stp	w9, w9, [x20, #136]
LBB0_35:
	ldr	x9, [x19]
	ldr	x10, [x21]
	cmp	x9, x10
	b.ne	LBB0_37
; %bb.36:
	ldr	x9, [x20, #128]
	add	x8, x9, x8, lsl #2
	ldur	w8, [x8, #-4]
	stp	w8, w8, [x20, #136]
LBB0_37:
	ldr	x8, [x20, #88]
	ldr	w8, [x8]
	ldr	x9, [x22]
	stp	w8, w9, [x20, #96]
	str	w8, [x20, #104]
	str	x9, [x20, #112]
	ldr	w0, [x23]
	bl	_PP_CAP
	cbz	x0, LBB0_42
; %bb.38:
	ldr	x9, [x24]
	ldr	x8, [x20, #80]
	cmp	x9, x8
	b.hs	LBB0_40
; %bb.39:
	ldr	x10, [x20, #88]
	ldr	w9, [x10, x9, lsl #2]
	stp	w9, w9, [x20, #96]
LBB0_40:
	ldr	x9, [x19]
	ldr	x10, [x21]
	cmp	x9, x10
	b.ne	LBB0_42
; %bb.41:
	ldr	x9, [x20, #88]
	add	x8, x9, x8, lsl #2
	ldur	w8, [x8, #-4]
	stp	w8, w8, [x20, #96]
LBB0_42:
	ldr	x8, [x20, #48]
	ldr	w8, [x8]
	ldr	x9, [x22]
	stp	w8, w9, [x20, #56]
	str	w8, [x20, #64]
	str	x9, [x20, #72]
	ldr	w0, [x23]
	bl	_PP_CAP
	cbz	x0, LBB0_47
; %bb.43:
Lloh20:
	adrp	x8, _VEGA20_UMD_PSTATE_SOCCLK_LEVEL@GOTPAGE
Lloh21:
	ldr	x8, [x8, _VEGA20_UMD_PSTATE_SOCCLK_LEVEL@GOTPAGEOFF]
Lloh22:
	ldr	x9, [x8]
	ldr	x8, [x20, #40]
	cmp	x9, x8
	b.hs	LBB0_45
; %bb.44:
	ldr	x10, [x20, #48]
	ldr	w9, [x10, x9, lsl #2]
	stp	w9, w9, [x20, #56]
LBB0_45:
	ldr	x9, [x19]
	ldr	x10, [x21]
	cmp	x9, x10
	b.ne	LBB0_47
; %bb.46:
	ldr	x9, [x20, #48]
	add	x8, x9, x8, lsl #2
	ldur	w8, [x8, #-4]
	stp	w8, w8, [x20, #56]
LBB0_47:
	ldr	x8, [x20, #8]
	ldr	w8, [x8]
	ldr	x9, [x22]
	stp	w8, w9, [x20, #16]
	str	w8, [x20, #24]
	str	x9, [x20, #32]
	ldr	w0, [x23]
	bl	_PP_CAP
	cbz	x0, LBB0_52
; %bb.48:
Lloh23:
	adrp	x8, _VEGA20_UMD_PSTATE_VCEMCLK_LEVEL@GOTPAGE
Lloh24:
	ldr	x8, [x8, _VEGA20_UMD_PSTATE_VCEMCLK_LEVEL@GOTPAGEOFF]
Lloh25:
	ldr	x9, [x8]
	ldr	x8, [x20]
	cmp	x9, x8
	b.hs	LBB0_50
; %bb.49:
	ldr	x10, [x20, #8]
	ldr	w9, [x10, x9, lsl #2]
	stp	w9, w9, [x20, #16]
LBB0_50:
	ldr	x9, [x19]
	ldr	x10, [x21]
	cmp	x9, x10
	b.ne	LBB0_52
; %bb.51:
	ldr	x9, [x20, #8]
	add	x8, x9, x8, lsl #2
	ldur	w8, [x8, #-4]
	stp	w8, w8, [x20, #16]
LBB0_52:
	mov	w0, #0
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_53:
	mov	w24, #1
	b	LBB0_3
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.cfi_endproc
                                        ; -- End function
	.comm	_VG20_CLOCK_MAX_DEFAULT,8,3     ; @VG20_CLOCK_MAX_DEFAULT
	.comm	_PHM_PlatformCaps_UMDPState,4,2 ; @PHM_PlatformCaps_UMDPState
	.comm	_VEGA20_UMD_PSTATE_GFXCLK_LEVEL,8,3 ; @VEGA20_UMD_PSTATE_GFXCLK_LEVEL
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK,8,3 ; @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,8,3 ; @AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
	.comm	_VEGA20_UMD_PSTATE_MCLK_LEVEL,8,3 ; @VEGA20_UMD_PSTATE_MCLK_LEVEL
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK,8,3 ; @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
	.comm	_VEGA20_UMD_PSTATE_UVDCLK_LEVEL,8,3 ; @VEGA20_UMD_PSTATE_UVDCLK_LEVEL
	.comm	_VEGA20_UMD_PSTATE_SOCCLK_LEVEL,8,3 ; @VEGA20_UMD_PSTATE_SOCCLK_LEVEL
	.comm	_VEGA20_UMD_PSTATE_VCEMCLK_LEVEL,8,3 ; @VEGA20_UMD_PSTATE_VCEMCLK_LEVEL
	.no_dead_strip	_vega20_apply_clocks_adjust_rules
.subsections_via_symbols
