	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_dce120_timing_generator_disable_vga ## -- Begin function dce120_timing_generator_disable_vga
	.p2align	4, 0x90
_dce120_timing_generator_disable_vga:   ## @dce120_timing_generator_disable_vga
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	callq	_DCE110TG_FROM_TG
	movl	(%rax), %eax
	addl	$-128, %eax
	cmpl	$4, %eax
	ja	LBB0_2
## %bb.1:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_7:
	movq	_mmD6VGA_CONTROL@GOTPCREL(%rip), %rax
	jmp	LBB0_8
LBB0_2:
	movq	_mmD1VGA_CONTROL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	xorl	%r15d, %r15d
	jmp	LBB0_9
LBB0_6:
	movq	_mmD5VGA_CONTROL@GOTPCREL(%rip), %rax
	jmp	LBB0_8
LBB0_5:
	movq	_mmD4VGA_CONTROL@GOTPCREL(%rip), %rax
	jmp	LBB0_8
LBB0_4:
	movq	_mmD3VGA_CONTROL@GOTPCREL(%rip), %rax
	jmp	LBB0_8
LBB0_3:
	movq	_mmD2VGA_CONTROL@GOTPCREL(%rip), %rax
LBB0_8:
	movq	(%rax), %r15
	movq	_mmD1VGA_CONTROL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	subq	%rsi, %r15
LBB0_9:
	movl	(%r14), %edi
	movq	%r15, %rdx
	callq	_dm_read_reg_soc15
	movq	%rax, %rbx
	movq	_D1VGA_CONTROL@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movq	_D1VGA_MODE_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_set_reg_field_value
	movl	(%r12), %edx
	movq	_D1VGA_TIMING_SELECT@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_set_reg_field_value
	movl	(%r12), %edx
	movq	_D1VGA_SYNC_POLARITY_SELECT@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_set_reg_field_value
	movl	(%r12), %edx
	movq	_D1VGA_OVERSCAN_COLOR_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_set_reg_field_value
	movl	(%r14), %edi
	movq	_mmD1VGA_CONTROL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdx
	movq	%rbx, %rcx
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_dm_write_reg_soc15             ## TAILCALL
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_7, LBB0_7-LJTI0_0
.set L0_0_set_6, LBB0_6-LJTI0_0
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_4, LBB0_4-LJTI0_0
.set L0_0_set_3, LBB0_3-LJTI0_0
LJTI0_0:
	.long	L0_0_set_7
	.long	L0_0_set_6
	.long	L0_0_set_5
	.long	L0_0_set_4
	.long	L0_0_set_3
	.end_data_region
                                        ## -- End function
	.comm	_mmD2VGA_CONTROL,8,3            ## @mmD2VGA_CONTROL
	.comm	_mmD1VGA_CONTROL,8,3            ## @mmD1VGA_CONTROL
	.comm	_mmD3VGA_CONTROL,8,3            ## @mmD3VGA_CONTROL
	.comm	_mmD4VGA_CONTROL,8,3            ## @mmD4VGA_CONTROL
	.comm	_mmD5VGA_CONTROL,8,3            ## @mmD5VGA_CONTROL
	.comm	_mmD6VGA_CONTROL,8,3            ## @mmD6VGA_CONTROL
	.comm	_D1VGA_CONTROL,4,2              ## @D1VGA_CONTROL
	.comm	_D1VGA_MODE_ENABLE,4,2          ## @D1VGA_MODE_ENABLE
	.comm	_D1VGA_TIMING_SELECT,4,2        ## @D1VGA_TIMING_SELECT
	.comm	_D1VGA_SYNC_POLARITY_SELECT,4,2 ## @D1VGA_SYNC_POLARITY_SELECT
	.comm	_D1VGA_OVERSCAN_COLOR_EN,4,2    ## @D1VGA_OVERSCAN_COLOR_EN
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_dce120_timing_generator_disable_vga ; -- Begin function dce120_timing_generator_disable_vga
	.p2align	2
_dce120_timing_generator_disable_vga:   ; @dce120_timing_generator_disable_vga
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	bl	_DCE110TG_FROM_TG
	ldr	w8, [x0]
	sub	w8, w8, #128
Lloh0:
	adrp	x22, _mmD1VGA_CONTROL@GOTPAGE
Lloh1:
	ldr	x22, [x22, _mmD1VGA_CONTROL@GOTPAGEOFF]
	cmp	w8, #4
	b.hi	LBB0_3
; %bb.1:
Lloh2:
	adrp	x9, lJTI0_0@PAGE
Lloh3:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_2
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_2:
Lloh4:
	adrp	x8, _mmD6VGA_CONTROL@GOTPAGE
Lloh5:
	ldr	x8, [x8, _mmD6VGA_CONTROL@GOTPAGEOFF]
	b	LBB0_8
LBB0_3:
	mov	x20, #0
	ldr	x1, [x22]
	b	LBB0_9
LBB0_4:
Lloh6:
	adrp	x8, _mmD5VGA_CONTROL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _mmD5VGA_CONTROL@GOTPAGEOFF]
	b	LBB0_8
LBB0_5:
Lloh8:
	adrp	x8, _mmD4VGA_CONTROL@GOTPAGE
Lloh9:
	ldr	x8, [x8, _mmD4VGA_CONTROL@GOTPAGEOFF]
	b	LBB0_8
LBB0_6:
Lloh10:
	adrp	x8, _mmD3VGA_CONTROL@GOTPAGE
Lloh11:
	ldr	x8, [x8, _mmD3VGA_CONTROL@GOTPAGEOFF]
	b	LBB0_8
LBB0_7:
Lloh12:
	adrp	x8, _mmD2VGA_CONTROL@GOTPAGE
Lloh13:
	ldr	x8, [x8, _mmD2VGA_CONTROL@GOTPAGEOFF]
LBB0_8:
	ldr	x8, [x8]
	ldr	x1, [x22]
	sub	x20, x8, x1
LBB0_9:
	ldr	w0, [x19]
	mov	x2, x20
	bl	_dm_read_reg_soc15
	mov	x21, x0
Lloh14:
	adrp	x23, _D1VGA_CONTROL@GOTPAGE
Lloh15:
	ldr	x23, [x23, _D1VGA_CONTROL@GOTPAGEOFF]
	ldr	w2, [x23]
Lloh16:
	adrp	x8, _D1VGA_MODE_ENABLE@GOTPAGE
Lloh17:
	ldr	x8, [x8, _D1VGA_MODE_ENABLE@GOTPAGEOFF]
Lloh18:
	ldr	w3, [x8]
	mov	w1, #0
	bl	_set_reg_field_value
	ldr	w2, [x23]
Lloh19:
	adrp	x8, _D1VGA_TIMING_SELECT@GOTPAGE
Lloh20:
	ldr	x8, [x8, _D1VGA_TIMING_SELECT@GOTPAGEOFF]
Lloh21:
	ldr	w3, [x8]
	mov	x0, x21
	mov	w1, #0
	bl	_set_reg_field_value
	ldr	w2, [x23]
Lloh22:
	adrp	x8, _D1VGA_SYNC_POLARITY_SELECT@GOTPAGE
Lloh23:
	ldr	x8, [x8, _D1VGA_SYNC_POLARITY_SELECT@GOTPAGEOFF]
Lloh24:
	ldr	w3, [x8]
	mov	x0, x21
	mov	w1, #0
	bl	_set_reg_field_value
	ldr	w2, [x23]
Lloh25:
	adrp	x8, _D1VGA_OVERSCAN_COLOR_EN@GOTPAGE
Lloh26:
	ldr	x8, [x8, _D1VGA_OVERSCAN_COLOR_EN@GOTPAGEOFF]
Lloh27:
	ldr	w3, [x8]
	mov	x0, x21
	mov	w1, #0
	bl	_set_reg_field_value
	ldr	w0, [x19]
	ldr	x1, [x22]
	mov	x2, x20
	mov	x3, x21
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_dm_write_reg_soc15
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_6-LBB0_2)>>2
	.byte	(LBB0_7-LBB0_2)>>2
                                        ; -- End function
	.comm	_mmD2VGA_CONTROL,8,3            ; @mmD2VGA_CONTROL
	.comm	_mmD1VGA_CONTROL,8,3            ; @mmD1VGA_CONTROL
	.comm	_mmD3VGA_CONTROL,8,3            ; @mmD3VGA_CONTROL
	.comm	_mmD4VGA_CONTROL,8,3            ; @mmD4VGA_CONTROL
	.comm	_mmD5VGA_CONTROL,8,3            ; @mmD5VGA_CONTROL
	.comm	_mmD6VGA_CONTROL,8,3            ; @mmD6VGA_CONTROL
	.comm	_D1VGA_CONTROL,4,2              ; @D1VGA_CONTROL
	.comm	_D1VGA_MODE_ENABLE,4,2          ; @D1VGA_MODE_ENABLE
	.comm	_D1VGA_TIMING_SELECT,4,2        ; @D1VGA_TIMING_SELECT
	.comm	_D1VGA_SYNC_POLARITY_SELECT,4,2 ; @D1VGA_SYNC_POLARITY_SELECT
	.comm	_D1VGA_OVERSCAN_COLOR_EN,4,2    ; @D1VGA_OVERSCAN_COLOR_EN
.subsections_via_symbols
