	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_d40_phy_cfg                    ## -- Begin function d40_phy_cfg
	.p2align	4, 0x90
_d40_phy_cfg:                           ## @d40_phy_cfg
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, -56(%rbp)                 ## 8-byte Spill
	movq	%rsi, -48(%rbp)                 ## 8-byte Spill
	movq	%rdi, %r12
	movq	(%rdi), %rax
	movq	_DMA_DEV_TO_MEM@GOTPCREL(%rip), %rcx
	movq	_DMA_DEV_TO_DEV@GOTPCREL(%rip), %r15
	cmpq	(%rcx), %rax
	je	LBB0_2
## %bb.1:
	xorl	%r13d, %r13d
	cmpq	(%r15), %rax
	jne	LBB0_6
LBB0_2:
	movq	_D40_SREG_CFG_MST_POS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_BIT
	movl	%eax, %r14d
	movl	80(%r12), %edi
	callq	_D40_TYPE_TO_EVENT
	movl	%eax, %ebx
	orl	%r14d, %ebx
	movq	40(%r12), %rax
	movq	_STEDMA40_NO_FLOW_CTRL@GOTPCREL(%rip), %rdx
	movq	_D40_SREG_CFG_PHY_TM_POS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	cmpq	(%rdx), %rax
	jne	LBB0_4
## %bb.3:
	movl	%ecx, %edi
	callq	_BIT
	movl	%eax, %r13d
	jmp	LBB0_5
LBB0_4:
	movl	$3, %r13d
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %r13d
LBB0_5:
	orl	%ebx, %r13d
LBB0_6:
	movq	(%r12), %rax
	movq	_DMA_MEM_TO_DEV@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_8
## %bb.7:
	xorl	%ebx, %ebx
	cmpq	(%r15), %rax
	jne	LBB0_12
LBB0_8:
	movq	_D40_SREG_CFG_MST_POS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_BIT
	movl	%eax, %ebx
	movl	80(%r12), %edi
	callq	_D40_TYPE_TO_EVENT
	movl	%eax, %r14d
	orl	%ebx, %r14d
	movq	8(%r12), %rax
	movq	_STEDMA40_NO_FLOW_CTRL@GOTPCREL(%rip), %rdx
	movq	_D40_SREG_CFG_PHY_TM_POS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	cmpq	(%rdx), %rax
	jne	LBB0_10
## %bb.9:
	movl	%ecx, %edi
	callq	_BIT
	movl	%eax, %ebx
	jmp	LBB0_11
LBB0_10:
	movl	$3, %ebx
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %ebx
LBB0_11:
	orl	%r14d, %ebx
LBB0_12:
	movq	_D40_SREG_CFG_TIM_POS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_BIT
	movl	%eax, %r14d
	orl	%ebx, %r14d
	movq	_D40_SREG_CFG_EIM_POS@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_BIT
	movl	%eax, %r15d
	orl	%r13d, %r15d
	movl	(%rbx), %edi
	callq	_BIT
	movl	%eax, %ebx
	movl	48(%r12), %eax
	movq	_STEDMA40_PSIZE_PHY_1@GOTPCREL(%rip), %r13
	cmpl	(%r13), %eax
	je	LBB0_14
## %bb.13:
	movq	_D40_SREG_CFG_PHY_PEN_POS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_BIT
	orl	%r15d, %eax
	movl	48(%r12), %r15d
	movq	_D40_SREG_CFG_PSIZE_POS@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r15d
	orl	%eax, %r15d
	movl	(%r13), %eax
LBB0_14:
	orl	%ebx, %r14d
	cmpl	%eax, 16(%r12)
	je	LBB0_16
## %bb.15:
	movq	_D40_SREG_CFG_PHY_PEN_POS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_BIT
	orl	%r14d, %eax
	movl	16(%r12), %r14d
	movq	_D40_SREG_CFG_PSIZE_POS@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r14d
	orl	%eax, %r14d
LBB0_16:
	movl	64(%r12), %edi
	callq	_d40_width_to_bits
	movl	%eax, %r13d
	movq	_D40_SREG_CFG_ESIZE_POS@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r13d
	orl	%r15d, %r13d
	movl	32(%r12), %edi
	callq	_d40_width_to_bits
	movl	%eax, %ebx
	movq	_D40_SREG_CFG_ESIZE_POS@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %ebx
	orl	%r14d, %ebx
	cmpq	$0, 72(%r12)
	je	LBB0_18
## %bb.17:
	movq	_D40_SREG_CFG_PRI_POS@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_BIT
	orl	%eax, %r13d
	movl	(%r14), %edi
	callq	_BIT
	orl	%eax, %ebx
LBB0_18:
	cmpq	$0, 56(%r12)
	je	LBB0_20
## %bb.19:
	movq	_D40_SREG_CFG_LBE_POS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_BIT
	orl	%eax, %r13d
LBB0_20:
	cmpq	$0, 24(%r12)
	je	LBB0_22
## %bb.21:
	movq	_D40_SREG_CFG_LBE_POS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_BIT
	orl	%eax, %ebx
LBB0_22:
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movq	-48(%rbp), %rcx                 ## 8-byte Reload
	movl	%r13d, (%rcx)
	movl	%ebx, (%rax)
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DMA_DEV_TO_MEM,8,3             ## @DMA_DEV_TO_MEM
	.comm	_DMA_DEV_TO_DEV,8,3             ## @DMA_DEV_TO_DEV
	.comm	_D40_SREG_CFG_MST_POS,4,2       ## @D40_SREG_CFG_MST_POS
	.comm	_STEDMA40_NO_FLOW_CTRL,8,3      ## @STEDMA40_NO_FLOW_CTRL
	.comm	_D40_SREG_CFG_PHY_TM_POS,4,2    ## @D40_SREG_CFG_PHY_TM_POS
	.comm	_DMA_MEM_TO_DEV,8,3             ## @DMA_MEM_TO_DEV
	.comm	_D40_SREG_CFG_TIM_POS,4,2       ## @D40_SREG_CFG_TIM_POS
	.comm	_D40_SREG_CFG_EIM_POS,4,2       ## @D40_SREG_CFG_EIM_POS
	.comm	_STEDMA40_PSIZE_PHY_1,4,2       ## @STEDMA40_PSIZE_PHY_1
	.comm	_D40_SREG_CFG_PHY_PEN_POS,4,2   ## @D40_SREG_CFG_PHY_PEN_POS
	.comm	_D40_SREG_CFG_PSIZE_POS,4,2     ## @D40_SREG_CFG_PSIZE_POS
	.comm	_D40_SREG_CFG_ESIZE_POS,4,2     ## @D40_SREG_CFG_ESIZE_POS
	.comm	_D40_SREG_CFG_PRI_POS,4,2       ## @D40_SREG_CFG_PRI_POS
	.comm	_D40_SREG_CFG_LBE_POS,4,2       ## @D40_SREG_CFG_LBE_POS
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_d40_phy_cfg                    ; -- Begin function d40_phy_cfg
	.p2align	2
_d40_phy_cfg:                           ; @d40_phy_cfg
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x2
	mov	x20, x1
	mov	x21, x0
	ldr	x8, [x0]
Lloh0:
	adrp	x9, _DMA_DEV_TO_MEM@GOTPAGE
Lloh1:
	ldr	x9, [x9, _DMA_DEV_TO_MEM@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
Lloh3:
	adrp	x27, _DMA_DEV_TO_DEV@GOTPAGE
Lloh4:
	ldr	x27, [x27, _DMA_DEV_TO_DEV@GOTPAGEOFF]
	ldr	x10, [x27]
	cmp	x8, x9
	ccmp	x8, x10, #4, ne
Lloh5:
	adrp	x26, _D40_SREG_CFG_MST_POS@GOTPAGE
Lloh6:
	ldr	x26, [x26, _D40_SREG_CFG_MST_POS@GOTPAGEOFF]
Lloh7:
	adrp	x24, _STEDMA40_NO_FLOW_CTRL@GOTPAGE
Lloh8:
	ldr	x24, [x24, _STEDMA40_NO_FLOW_CTRL@GOTPAGEOFF]
Lloh9:
	adrp	x25, _D40_SREG_CFG_PHY_TM_POS@GOTPAGE
Lloh10:
	ldr	x25, [x25, _D40_SREG_CFG_PHY_TM_POS@GOTPAGEOFF]
	b.ne	LBB0_3
; %bb.1:
	ldr	w0, [x26]
	bl	_BIT
	mov	x22, x0
	ldr	w0, [x21, #80]
	bl	_D40_TYPE_TO_EVENT
	orr	w22, w0, w22
	ldr	x8, [x21, #40]
	ldr	x9, [x24]
	ldr	w0, [x25]
	cmp	x8, x9
	b.ne	LBB0_4
; %bb.2:
	bl	_BIT
	orr	w23, w0, w22
	b	LBB0_5
LBB0_3:
	mov	w23, #0
	b	LBB0_5
LBB0_4:
	mov	w8, #3
	lsl	w8, w8, w0
	orr	w23, w8, w22
LBB0_5:
	ldr	x8, [x21]
Lloh11:
	adrp	x9, _DMA_MEM_TO_DEV@GOTPAGE
Lloh12:
	ldr	x9, [x9, _DMA_MEM_TO_DEV@GOTPAGEOFF]
Lloh13:
	ldr	x9, [x9]
	ldr	x10, [x27]
	cmp	x8, x9
	ccmp	x8, x10, #4, ne
	b.ne	LBB0_8
; %bb.6:
	ldr	w0, [x26]
	bl	_BIT
	mov	x22, x0
	ldr	w0, [x21, #80]
	bl	_D40_TYPE_TO_EVENT
	orr	w22, w0, w22
	ldr	x8, [x21, #8]
	ldr	x9, [x24]
	ldr	w0, [x25]
	cmp	x8, x9
	b.ne	LBB0_9
; %bb.7:
	bl	_BIT
	orr	w22, w0, w22
	b	LBB0_10
LBB0_8:
	mov	w22, #0
	b	LBB0_10
LBB0_9:
	mov	w8, #3
	lsl	w8, w8, w0
	orr	w22, w8, w22
LBB0_10:
Lloh14:
	adrp	x8, _D40_SREG_CFG_TIM_POS@GOTPAGE
Lloh15:
	ldr	x8, [x8, _D40_SREG_CFG_TIM_POS@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
	bl	_BIT
	orr	w24, w0, w22
Lloh17:
	adrp	x25, _D40_SREG_CFG_EIM_POS@GOTPAGE
Lloh18:
	ldr	x25, [x25, _D40_SREG_CFG_EIM_POS@GOTPAGEOFF]
	ldr	w0, [x25]
	bl	_BIT
	orr	w22, w0, w23
	ldr	w0, [x25]
	bl	_BIT
	orr	w23, w24, w0
	ldr	w8, [x21, #48]
Lloh19:
	adrp	x26, _STEDMA40_PSIZE_PHY_1@GOTPAGE
Lloh20:
	ldr	x26, [x26, _STEDMA40_PSIZE_PHY_1@GOTPAGEOFF]
	ldr	w9, [x26]
Lloh21:
	adrp	x25, _D40_SREG_CFG_PHY_PEN_POS@GOTPAGE
Lloh22:
	ldr	x25, [x25, _D40_SREG_CFG_PHY_PEN_POS@GOTPAGEOFF]
Lloh23:
	adrp	x24, _D40_SREG_CFG_PSIZE_POS@GOTPAGE
Lloh24:
	ldr	x24, [x24, _D40_SREG_CFG_PSIZE_POS@GOTPAGEOFF]
	cmp	w8, w9
	b.eq	LBB0_12
; %bb.11:
	ldr	w0, [x25]
	bl	_BIT
	orr	w8, w0, w22
	ldr	w9, [x21, #48]
	ldr	w10, [x24]
	lsl	w9, w9, w10
	orr	w22, w8, w9
	ldr	w8, [x26]
LBB0_12:
	ldr	w9, [x21, #16]
	cmp	w9, w8
	b.eq	LBB0_14
; %bb.13:
	ldr	w0, [x25]
	bl	_BIT
	orr	w8, w0, w23
	ldr	w9, [x21, #16]
	ldr	w10, [x24]
	lsl	w9, w9, w10
	orr	w23, w8, w9
LBB0_14:
	ldr	w0, [x21, #64]
	bl	_d40_width_to_bits
Lloh25:
	adrp	x24, _D40_SREG_CFG_ESIZE_POS@GOTPAGE
Lloh26:
	ldr	x24, [x24, _D40_SREG_CFG_ESIZE_POS@GOTPAGEOFF]
	ldr	w8, [x24]
	lsl	w8, w0, w8
	orr	w22, w8, w22
	ldr	w0, [x21, #32]
	bl	_d40_width_to_bits
	ldr	w8, [x24]
	lsl	w8, w0, w8
	orr	w23, w8, w23
	ldr	x8, [x21, #72]
	cbz	x8, LBB0_16
; %bb.15:
Lloh27:
	adrp	x24, _D40_SREG_CFG_PRI_POS@GOTPAGE
Lloh28:
	ldr	x24, [x24, _D40_SREG_CFG_PRI_POS@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_BIT
	orr	w22, w0, w22
	ldr	w0, [x24]
	bl	_BIT
	orr	w23, w0, w23
LBB0_16:
	ldr	x8, [x21, #56]
Lloh29:
	adrp	x24, _D40_SREG_CFG_LBE_POS@GOTPAGE
Lloh30:
	ldr	x24, [x24, _D40_SREG_CFG_LBE_POS@GOTPAGEOFF]
	cbz	x8, LBB0_18
; %bb.17:
	ldr	w0, [x24]
	bl	_BIT
	orr	w22, w0, w22
LBB0_18:
	ldr	x8, [x21, #24]
	cbz	x8, LBB0_20
; %bb.19:
	ldr	w0, [x24]
	bl	_BIT
	orr	w23, w0, w23
LBB0_20:
	str	w22, [x20]
	str	w23, [x19]
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh29, Lloh30
	.cfi_endproc
                                        ; -- End function
	.comm	_DMA_DEV_TO_MEM,8,3             ; @DMA_DEV_TO_MEM
	.comm	_DMA_DEV_TO_DEV,8,3             ; @DMA_DEV_TO_DEV
	.comm	_D40_SREG_CFG_MST_POS,4,2       ; @D40_SREG_CFG_MST_POS
	.comm	_STEDMA40_NO_FLOW_CTRL,8,3      ; @STEDMA40_NO_FLOW_CTRL
	.comm	_D40_SREG_CFG_PHY_TM_POS,4,2    ; @D40_SREG_CFG_PHY_TM_POS
	.comm	_DMA_MEM_TO_DEV,8,3             ; @DMA_MEM_TO_DEV
	.comm	_D40_SREG_CFG_TIM_POS,4,2       ; @D40_SREG_CFG_TIM_POS
	.comm	_D40_SREG_CFG_EIM_POS,4,2       ; @D40_SREG_CFG_EIM_POS
	.comm	_STEDMA40_PSIZE_PHY_1,4,2       ; @STEDMA40_PSIZE_PHY_1
	.comm	_D40_SREG_CFG_PHY_PEN_POS,4,2   ; @D40_SREG_CFG_PHY_PEN_POS
	.comm	_D40_SREG_CFG_PSIZE_POS,4,2     ; @D40_SREG_CFG_PSIZE_POS
	.comm	_D40_SREG_CFG_ESIZE_POS,4,2     ; @D40_SREG_CFG_ESIZE_POS
	.comm	_D40_SREG_CFG_PRI_POS,4,2       ; @D40_SREG_CFG_PRI_POS
	.comm	_D40_SREG_CFG_LBE_POS,4,2       ; @D40_SREG_CFG_LBE_POS
.subsections_via_symbols
