	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function smu_v11_0_init_microcode
_smu_v11_0_init_microcode:              ## @smu_v11_0_init_microcode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -32(%rbp)
	movq	(%rdi), %r15
	movl	(%r15), %eax
	addl	$-128, %eax
	cmpl	$5, %eax
	jae	LBB0_8
## %bb.1:
	cltq
	leaq	l_reltable.smu_v11_0_init_microcode(%rip), %rdx
	movslq	(%rdx,%rax,4), %rcx
	addq	%rdx, %rcx
	leaq	L_.str.5(%rip), %rdx
	leaq	-64(%rbp), %r14
	movq	%r14, %rdi
	movl	$30, %esi
	callq	_snprintf
	leaq	8(%r15), %rbx
	movl	48(%r15), %edx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	_request_firmware
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	LBB0_5
## %bb.2:
	movq	(%rbx), %rdi
	callq	_amdgpu_ucode_validate
	movl	%eax, %r14d
	testl	%eax, %eax
	je	LBB0_3
LBB0_5:
	leaq	L_.str.6(%rip), %rdi
	leaq	-64(%rbp), %rsi
	callq	_DRM_ERROR
	movq	(%rbx), %rdi
	callq	_release_firmware
	movq	$0, (%rbx)
LBB0_6:
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	cmpq	-32(%rbp), %rax
	jne	LBB0_9
## %bb.7:
	movl	%r14d, %eax
	addq	$40, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_3:
	movq	8(%r15), %rax
	movq	(%rax), %rbx
	movq	%rbx, %rdi
	callq	_amdgpu_ucode_print_smc_hdr
	movl	(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 16(%r15)
	movq	24(%r15), %rax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	xorl	%r14d, %r14d
	cmpq	(%rcx), %rax
	jne	LBB0_6
## %bb.4:
	movq	40(%r15), %rax
	movq	_AMDGPU_UCODE_ID_SMC@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	8(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movq	(%rcx), %rax
	movl	(%rax), %edi
	callq	_le32_to_cpu
	movq	_PAGE_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_ALIGN
	addl	%eax, 32(%r15)
	jmp	LBB0_6
LBB0_9:
	callq	___stack_chk_fail
LBB0_8:
	xorl	%eax, %eax
	callq	_BUG
	ud2
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"vega20"

L_.str.1:                               ## @.str.1
	.asciz	"arcturus"

L_.str.2:                               ## @.str.2
	.asciz	"navi10"

L_.str.3:                               ## @.str.3
	.asciz	"navi14"

L_.str.4:                               ## @.str.4
	.asciz	"navi12"

L_.str.5:                               ## @.str.5
	.asciz	"amdgpu/%s_smc.bin"

	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_SMC,8,3        ## @AMDGPU_UCODE_ID_SMC
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
L_.str.6:                               ## @.str.6
	.asciz	"smu_v11_0: Failed to load firmware \"%s\"\n"

	.no_dead_strip	_smu_v11_0_init_microcode
	.section	__TEXT,__const
	.p2align	2                               ## @reltable.smu_v11_0_init_microcode
l_reltable.smu_v11_0_init_microcode:
	.long	L_.str-l_reltable.smu_v11_0_init_microcode
	.long	L_.str.3-l_reltable.smu_v11_0_init_microcode
	.long	L_.str.4-l_reltable.smu_v11_0_init_microcode
	.long	L_.str.2-l_reltable.smu_v11_0_init_microcode
	.long	L_.str.1-l_reltable.smu_v11_0_init_microcode

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function smu_v11_0_init_microcode
_smu_v11_0_init_microcode:              ; @smu_v11_0_init_microcode
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
Lloh0:
	adrp	x8, ___stack_chk_guard@GOTPAGE
Lloh1:
	ldr	x8, [x8, ___stack_chk_guard@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	str	x8, [sp, #40]
	ldr	x21, [x0]
	ldr	w8, [x21]
	sub	w8, w8, #128
	cmp	w8, #5
	b.hs	LBB0_10
; %bb.1:
Lloh3:
	adrp	x9, l_switch.table.smu_v11_0_init_microcode@PAGE
Lloh4:
	add	x9, x9, l_switch.table.smu_v11_0_init_microcode@PAGEOFF
	ldr	x3, [x9, w8, sxtw #3]
Lloh5:
	adrp	x2, l_.str.5@PAGE
Lloh6:
	add	x2, x2, l_.str.5@PAGEOFF
	add	x0, sp, #10
	mov	w1, #30
	bl	_snprintf
	add	x20, x21, #8
	ldr	w2, [x21, #48]
	add	x1, sp, #10
	mov	x0, x20
	bl	_request_firmware
	mov	x19, x0
	cbnz	w0, LBB0_3
; %bb.2:
	ldr	x0, [x20]
	bl	_amdgpu_ucode_validate
	mov	x19, x0
	cbz	w0, LBB0_6
LBB0_3:
Lloh7:
	adrp	x0, l_.str.6@PAGE
Lloh8:
	add	x0, x0, l_.str.6@PAGEOFF
	add	x1, sp, #10
	bl	_DRM_ERROR
	ldr	x0, [x20]
	bl	_release_firmware
	str	xzr, [x20]
LBB0_4:
	ldr	x8, [sp, #40]
Lloh9:
	adrp	x9, ___stack_chk_guard@GOTPAGE
Lloh10:
	ldr	x9, [x9, ___stack_chk_guard@GOTPAGEOFF]
Lloh11:
	ldr	x9, [x9]
	cmp	x9, x8
	b.ne	LBB0_9
; %bb.5:
	mov	x0, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_6:
	ldr	x8, [x21, #8]
	ldr	x19, [x8]
	mov	x0, x19
	bl	_amdgpu_ucode_print_smc_hdr
	ldr	w0, [x19]
	bl	_le32_to_cpu
	str	w0, [x21, #16]
	ldr	x8, [x21, #24]
Lloh12:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh13:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh14:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_8
; %bb.7:
	ldr	x8, [x21, #40]
Lloh15:
	adrp	x9, _AMDGPU_UCODE_ID_SMC@GOTPAGE
Lloh16:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_SMC@GOTPAGEOFF]
Lloh17:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x21, #8]
	str	x9, [x8, #8]
	ldr	x8, [x9]
	ldr	w0, [x8]
	bl	_le32_to_cpu
Lloh18:
	adrp	x8, _PAGE_SIZE@GOTPAGE
Lloh19:
	ldr	x8, [x8, _PAGE_SIZE@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	bl	_ALIGN
	mov	w19, #0
	ldr	w8, [x21, #32]
	add	w8, w8, w0
	str	w8, [x21, #32]
	b	LBB0_4
LBB0_8:
	mov	w19, #0
	b	LBB0_4
LBB0_9:
	bl	___stack_chk_fail
LBB0_10:
	bl	_BUG
	brk	#0x1
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpAdd	Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"vega20"

l_.str.1:                               ; @.str.1
	.asciz	"arcturus"

l_.str.2:                               ; @.str.2
	.asciz	"navi10"

l_.str.3:                               ; @.str.3
	.asciz	"navi14"

l_.str.4:                               ; @.str.4
	.asciz	"navi12"

l_.str.5:                               ; @.str.5
	.asciz	"amdgpu/%s_smc.bin"

	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_SMC,8,3        ; @AMDGPU_UCODE_ID_SMC
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
l_.str.6:                               ; @.str.6
	.asciz	"smu_v11_0: Failed to load firmware \"%s\"\n"

	.no_dead_strip	_smu_v11_0_init_microcode
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.smu_v11_0_init_microcode
l_switch.table.smu_v11_0_init_microcode:
	.quad	l_.str
	.quad	l_.str.3
	.quad	l_.str.4
	.quad	l_.str.2
	.quad	l_.str.1

.subsections_via_symbols
