	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function a6xx_set_hwcg
_a6xx_set_hwcg:                         ## @a6xx_set_hwcg
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %rbx
	callq	_to_adreno_gpu
	movq	%rax, %rdi
	callq	_to_a6xx_gpu
	movq	%rax, %r15
	movq	_REG_A6XX_RBBM_CLOCK_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_gpu_read
	xorl	%ecx, %ecx
	testl	%eax, %eax
	sete	%cl
	xorl	%edx, %edx
	cmpl	$-1968657918, %eax              ## imm = 0x8AA8AA02
	sete	%dl
	testl	%r14d, %r14d
	cmovel	%ecx, %edx
	testb	%dl, %dl
	je	LBB0_1
## %bb.7:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_1:
	movq	_REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$1, %edx
	xorl	%ecx, %ecx
	callq	_gmu_rmw
	movq	_a6xx_hwcg@GOTPCREL(%rip), %r13
	movq	(%r13), %rdi
	callq	_ARRAY_SIZE
	testl	%eax, %eax
	je	LBB0_6
## %bb.2:
	xorl	%r12d, %r12d
	jmp	LBB0_3
	.p2align	4, 0x90
LBB0_5:                                 ##   in Loop: Header=BB0_3 Depth=1
	movl	4(%rax,%r12,8), %esi
	movq	%rbx, %rdi
	callq	_gpu_write
	incq	%r12
	movq	(%r13), %rdi
	callq	_ARRAY_SIZE
	movl	%eax, %eax
	cmpq	%rax, %r12
	jae	LBB0_6
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movq	(%r13), %rax
	movl	$0, %edx
	testl	%r14d, %r14d
	je	LBB0_5
## %bb.4:                               ##   in Loop: Header=BB0_3 Depth=1
	movl	(%rax,%r12,8), %edx
	jmp	LBB0_5
LBB0_6:
	movq	_REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	movl	$1, %ecx
	callq	_gmu_rmw
	testl	%r14d, %r14d
	movq	_REG_A6XX_RBBM_CLOCK_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$-1968657918, %edx              ## imm = 0x8AA8AA02
	cmovel	%r14d, %edx
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_gpu_write                      ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_REG_A6XX_RBBM_CLOCK_CNTL,4,2   ## @REG_A6XX_RBBM_CLOCK_CNTL
	.comm	_REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL,4,2 ## @REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL
	.comm	_a6xx_hwcg,8,3                  ## @a6xx_hwcg
	.no_dead_strip	_a6xx_set_hwcg
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function a6xx_set_hwcg
_a6xx_set_hwcg:                         ; @a6xx_set_hwcg
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x20, x1
	mov	x19, x0
	mov	w22, #43522
	movk	w22, #35496, lsl #16
	bl	_to_adreno_gpu
	bl	_to_a6xx_gpu
	mov	x21, x0
Lloh0:
	adrp	x23, _REG_A6XX_RBBM_CLOCK_CNTL@GOTPAGE
Lloh1:
	ldr	x23, [x23, _REG_A6XX_RBBM_CLOCK_CNTL@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x19
	bl	_gpu_read
	cmp	w0, #0
	cset	w8, eq
	cmp	w0, w22
	cset	w9, eq
	cmp	w20, #0
	csel	w8, w8, w9, eq
	tbz	w8, #0, LBB0_2
; %bb.1:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
LBB0_2:
Lloh2:
	adrp	x24, _REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL@GOTPAGE
Lloh3:
	ldr	x24, [x24, _REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	x0, x21
	mov	w2, #1
	mov	w3, #0
	bl	_gmu_rmw
Lloh4:
	adrp	x25, _a6xx_hwcg@GOTPAGE
Lloh5:
	ldr	x25, [x25, _a6xx_hwcg@GOTPAGEOFF]
	ldr	x0, [x25]
	bl	_ARRAY_SIZE
	cbz	w0, LBB0_8
; %bb.3:
	mov	x26, #0
	mov	x27, #0
	b	LBB0_6
LBB0_4:                                 ;   in Loop: Header=BB0_6 Depth=1
	ldr	w2, [x8, x26]
LBB0_5:                                 ;   in Loop: Header=BB0_6 Depth=1
	add	x8, x8, x26
	ldr	w1, [x8, #4]
	mov	x0, x19
	bl	_gpu_write
	add	x27, x27, #1
	ldr	x0, [x25]
	bl	_ARRAY_SIZE
	add	x26, x26, #8
	cmp	x27, w0, uxtw
	b.hs	LBB0_8
LBB0_6:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x25]
	cbnz	w20, LBB0_4
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=1
	mov	w2, #0
	b	LBB0_5
LBB0_8:
	ldr	w1, [x24]
	mov	x0, x21
	mov	w2, #0
	mov	w3, #1
	bl	_gmu_rmw
	ldr	w1, [x23]
	cmp	w20, #0
	csel	w2, wzr, w22, eq
	mov	x0, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_gpu_write
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.cfi_endproc
                                        ; -- End function
	.comm	_REG_A6XX_RBBM_CLOCK_CNTL,4,2   ; @REG_A6XX_RBBM_CLOCK_CNTL
	.comm	_REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL,4,2 ; @REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL
	.comm	_a6xx_hwcg,8,3                  ; @a6xx_hwcg
	.no_dead_strip	_a6xx_set_hwcg
.subsections_via_symbols
