	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gmc_v10_0_vm_fault_interrupt_state
_gmc_v10_0_vm_fault_interrupt_state:    ## @gmc_v10_0_vm_fault_interrupt_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %ebx
	movq	%rdi, %r12
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -48(%rbp)
	movq	_AMDGPU_MAX_VMHUBS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	shlq	$2, %rax
	callq	____chkstk_darwin
	addq	$15, %rax
	andq	$-16, %rax
	subq	%rax, %rsp
	movq	%rsp, %r15
	movq	_GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rcx
	movq	_GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	(%rcx), %eax
	movq	_GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rcx
	movq	_MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	movq	_MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	_MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	_AMDGPU_GFXHUB_0@GOTPCREL(%rip), %rsi
	movq	_MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	_MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	(%rsi), %rcx
	movl	%eax, (%r15,%rcx,4)
	movq	_MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_AMDGPU_MMHUB_0@GOTPCREL(%rip), %rax
	movq	(%rax), %r14
	movl	%edx, (%r15,%r14,4)
	cmpl	$128, %ebx
	je	LBB0_6
## %bb.1:
	cmpl	$129, %ebx
	jne	LBB0_10
## %bb.2:
	movq	%r12, -56(%rbp)                 ## 8-byte Spill
	movq	(%r12), %r12
	xorl	%r13d, %r13d
	.p2align	4, 0x90
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r12,%r14,4), %ebx
	addl	%r13d, %ebx
	movl	%ebx, %edi
	callq	_RREG32
	movq	_AMDGPU_MMHUB_0@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	(%r15,%rcx,4), %esi
	notl	%esi
	andl	%eax, %esi
	movl	%ebx, %edi
	callq	_WREG32
	incl	%r13d
	cmpl	$16, %r13d
	jne	LBB0_3
## %bb.4:
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %r14
	movq	_AMDGPU_GFXHUB_0@GOTPCREL(%rip), %rax
	movq	(%rax), %r12
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r14,%r12,4), %r13d
	addl	%ebx, %r13d
	movl	%r13d, %edi
	callq	_RREG32
	movq	_AMDGPU_GFXHUB_0@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	(%r15,%rcx,4), %esi
	notl	%esi
	andl	%eax, %esi
	movl	%r13d, %edi
	callq	_WREG32
	incl	%ebx
	cmpl	$16, %ebx
	jne	LBB0_5
	jmp	LBB0_10
LBB0_6:
	movq	%r12, -56(%rbp)                 ## 8-byte Spill
	movq	(%r12), %r12
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_7:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r12,%r14,4), %r13d
	addl	%ebx, %r13d
	movl	%r13d, %edi
	callq	_RREG32
	movq	_AMDGPU_MMHUB_0@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	orl	(%r15,%rcx,4), %eax
	movl	%r13d, %edi
	movl	%eax, %esi
	callq	_WREG32
	incl	%ebx
	cmpl	$16, %ebx
	jne	LBB0_7
## %bb.8:
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %r14
	movq	_AMDGPU_GFXHUB_0@GOTPCREL(%rip), %rax
	movq	(%rax), %r12
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_9:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r14,%r12,4), %r13d
	addl	%ebx, %r13d
	movl	%r13d, %edi
	callq	_RREG32
	movq	_AMDGPU_GFXHUB_0@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	orl	(%r15,%rcx,4), %eax
	movl	%r13d, %edi
	movl	%eax, %esi
	callq	_WREG32
	incl	%ebx
	cmpl	$16, %ebx
	jne	LBB0_9
LBB0_10:
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	cmpq	-48(%rbp), %rax
	jne	LBB0_12
## %bb.11:
	xorl	%eax, %eax
	leaq	-40(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_12:
	callq	___stack_chk_fail
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_MAX_VMHUBS,4,2          ## @AMDGPU_MAX_VMHUBS
	.comm	_GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ## @GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ## @GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ## @GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ## @GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ## @GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ## @GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ## @GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_AMDGPU_GFXHUB_0,8,3            ## @AMDGPU_GFXHUB_0
	.comm	_MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ## @MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ## @MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ## @MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ## @MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ## @MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ## @MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ## @MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_AMDGPU_MMHUB_0,8,3             ## @AMDGPU_MMHUB_0
	.no_dead_strip	_gmc_v10_0_vm_fault_interrupt_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gmc_v10_0_vm_fault_interrupt_state
_gmc_v10_0_vm_fault_interrupt_state:    ; @gmc_v10_0_vm_fault_interrupt_state
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	sub	sp, sp, #16
	mov	x19, x0
Lloh0:
	adrp	x8, ___stack_chk_guard@GOTPAGE
Lloh1:
	ldr	x8, [x8, ___stack_chk_guard@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	stur	x8, [x29, #-72]
Lloh3:
	adrp	x8, _AMDGPU_MAX_VMHUBS@GOTPAGE
Lloh4:
	ldr	x8, [x8, _AMDGPU_MAX_VMHUBS@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	lsl	x8, x8, #2
	mov	x9, x8
Lloh6:
	adrp	x16, ___chkstk_darwin@GOTPAGE
Lloh7:
	ldr	x16, [x16, ___chkstk_darwin@GOTPAGEOFF]
	blr	x16
	mov	x9, sp
	add	x8, x8, #15
	and	x8, x8, #0x7fffffff0
	sub	x21, x9, x8
	mov	sp, x21
Lloh8:
	adrp	x8, _GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh9:
	ldr	x8, [x8, _GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
Lloh11:
	adrp	x9, _GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh12:
	ldr	x9, [x9, _GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh14:
	adrp	x9, _GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh15:
	ldr	x9, [x9, _GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh17:
	adrp	x9, _GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh18:
	ldr	x9, [x9, _GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh20:
	adrp	x9, _GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh21:
	ldr	x9, [x9, _GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh23:
	adrp	x9, _GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh24:
	ldr	x9, [x9, _GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh26:
	adrp	x9, _GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh27:
	ldr	x9, [x9, _GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
Lloh28:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh29:
	adrp	x22, _AMDGPU_GFXHUB_0@GOTPAGE
Lloh30:
	ldr	x22, [x22, _AMDGPU_GFXHUB_0@GOTPAGEOFF]
	ldr	x9, [x22]
	str	w8, [x21, x9, lsl #2]
Lloh31:
	adrp	x8, _MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh32:
	ldr	x8, [x8, _MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
Lloh34:
	adrp	x9, _MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh35:
	ldr	x9, [x9, _MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
Lloh36:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh37:
	adrp	x9, _MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh38:
	ldr	x9, [x9, _MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
Lloh39:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh40:
	adrp	x9, _MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh41:
	ldr	x9, [x9, _MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
Lloh42:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh43:
	adrp	x9, _MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh44:
	ldr	x9, [x9, _MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
Lloh45:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh46:
	adrp	x9, _MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh47:
	ldr	x9, [x9, _MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
Lloh48:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh49:
	adrp	x9, _MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGE
Lloh50:
	ldr	x9, [x9, _MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK@GOTPAGEOFF]
Lloh51:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh52:
	adrp	x23, _AMDGPU_MMHUB_0@GOTPAGE
Lloh53:
	ldr	x23, [x23, _AMDGPU_MMHUB_0@GOTPAGEOFF]
	ldr	x24, [x23]
	str	w8, [x21, x24, lsl #2]
	cmp	w3, #128
	b.eq	LBB0_6
; %bb.1:
	cmp	w3, #129
	b.ne	LBB0_10
; %bb.2:
	mov	w25, #0
	ldr	x26, [x19]
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w8, [x26, x24, lsl #2]
	add	w20, w25, w8
	mov	x0, x20
	bl	_RREG32
	ldr	x8, [x23]
	ldr	w8, [x21, x8, lsl #2]
	bic	w1, w0, w8
	mov	x0, x20
	bl	_WREG32
	add	w25, w25, #1
	cmp	w25, #16
	b.ne	LBB0_3
; %bb.4:
	mov	w20, #0
	ldr	x23, [x19]
	ldr	x24, [x22]
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w8, [x23, x24, lsl #2]
	add	w19, w20, w8
	mov	x0, x19
	bl	_RREG32
	ldr	x8, [x22]
	ldr	w8, [x21, x8, lsl #2]
	bic	w1, w0, w8
	mov	x0, x19
	bl	_WREG32
	add	w20, w20, #1
	cmp	w20, #16
	b.ne	LBB0_5
	b	LBB0_10
LBB0_6:
	mov	w25, #0
	ldr	x26, [x19]
LBB0_7:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w8, [x26, x24, lsl #2]
	add	w20, w25, w8
	mov	x0, x20
	bl	_RREG32
	ldr	x8, [x23]
	ldr	w8, [x21, x8, lsl #2]
	orr	w1, w8, w0
	mov	x0, x20
	bl	_WREG32
	add	w25, w25, #1
	cmp	w25, #16
	b.ne	LBB0_7
; %bb.8:
	mov	w20, #0
	ldr	x23, [x19]
	ldr	x24, [x22]
LBB0_9:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w8, [x23, x24, lsl #2]
	add	w19, w20, w8
	mov	x0, x19
	bl	_RREG32
	ldr	x8, [x22]
	ldr	w8, [x21, x8, lsl #2]
	orr	w1, w8, w0
	mov	x0, x19
	bl	_WREG32
	add	w20, w20, #1
	cmp	w20, #16
	b.ne	LBB0_9
LBB0_10:
	ldur	x8, [x29, #-72]
Lloh54:
	adrp	x9, ___stack_chk_guard@GOTPAGE
Lloh55:
	ldr	x9, [x9, ___stack_chk_guard@GOTPAGEOFF]
Lloh56:
	ldr	x9, [x9]
	cmp	x9, x8
	b.ne	LBB0_12
; %bb.11:
	mov	w0, #0
	sub	sp, x29, #64
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_12:
	bl	___stack_chk_fail
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_MAX_VMHUBS,4,2          ; @AMDGPU_MAX_VMHUBS
	.comm	_GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ; @GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ; @GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ; @GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ; @GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ; @GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ; @GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ; @GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_AMDGPU_GFXHUB_0,8,3            ; @AMDGPU_GFXHUB_0
	.comm	_MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ; @MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ; @MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ; @MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ; @MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ; @MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ; @MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,2 ; @MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.comm	_AMDGPU_MMHUB_0,8,3             ; @AMDGPU_MMHUB_0
	.no_dead_strip	_gmc_v10_0_vm_fault_interrupt_state
.subsections_via_symbols
