	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function r600_gpu_pci_config_reset
_r600_gpu_pci_config_reset:             ## @r600_gpu_pci_config_reset
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r13
	movl	16(%rdi), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_info
	movq	(%r13), %rbx
	movq	_CHIP_RV770@GOTPCREL(%rip), %rax
	movq	(%rax), %r12
	movq	_R_0086D8_CP_ME_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	$1, %edi
	callq	_S_0086D8_CP_ME_HALT
	movq	%rax, %r15
	cmpq	%r12, %rbx
	jl	LBB0_2
## %bb.1:
	movl	$1, %edi
	callq	_S_0086D8_CP_PFP_HALT
	orq	%rax, %r15
LBB0_2:
	movl	%r14d, %edi
	movq	%r15, %rsi
	callq	_WREG32
	movq	_RLC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_DMA_RB_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	cltq
	movq	_DMA_RB_ENABLE@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rsi
	notq	%rsi
	andq	%rax, %rsi
	movl	(%rbx), %edi
	callq	_WREG32
	movl	$50, %edi
	callq	_mdelay
	movq	(%r13), %rax
	movq	_CHIP_RV770@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_4
## %bb.3:
	movq	%r13, %rdi
	callq	_rv770_set_clk_bypass_mode
LBB0_4:
	movl	20(%r13), %edi
	callq	_pci_clear_master
	leaq	-48(%rbp), %rsi
	movq	%r13, %rdi
	callq	_rv515_mc_stop
	movq	%r13, %rdi
	callq	_r600_mc_wait_for_idle
	testq	%rax, %rax
	je	LBB0_6
## %bb.5:
	movl	16(%r13), %edi
	leaq	L_.str.1(%rip), %rsi
	callq	_dev_warn
LBB0_6:
	movq	_BUS_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movslq	%eax, %rsi
	movq	_VGA_COHE_SPEC_TIMER_DIS@GOTPCREL(%rip), %rax
	orq	(%rax), %rsi
	movl	(%rbx), %edi
	callq	_WREG32
	movq	_BIF_SCRATCH0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	%r13, %rdi
	callq	_radeon_pci_config_reset
	movl	$1, %edi
	callq	_mdelay
	movq	_SOFT_RESET_BIF@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_SRBM_SOFT_RESET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_WREG32
	movl	$1, %edi
	callq	_mdelay
	movl	(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	cmpq	$0, 8(%r13)
	jle	LBB0_10
## %bb.7:
	xorl	%ebx, %ebx
	movq	_CONFIG_MEMSIZE@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_8:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %edi
	callq	_RREG32
	cmpl	$-1, %eax
	jne	LBB0_10
## %bb.9:                               ##   in Loop: Header=BB0_8 Depth=1
	movl	$1, %edi
	callq	_udelay
	incq	%rbx
	cmpq	8(%r13), %rbx
	jl	LBB0_8
LBB0_10:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"GPU pci config reset\n"

	.comm	_CHIP_RV770,8,3                 ## @CHIP_RV770
	.comm	_R_0086D8_CP_ME_CNTL,4,2        ## @R_0086D8_CP_ME_CNTL
	.comm	_RLC_CNTL,4,2                   ## @RLC_CNTL
	.comm	_DMA_RB_CNTL,4,2                ## @DMA_RB_CNTL
	.comm	_DMA_RB_ENABLE,8,3              ## @DMA_RB_ENABLE
L_.str.1:                               ## @.str.1
	.asciz	"Wait for MC idle timedout !\n"

	.comm	_BUS_CNTL,4,2                   ## @BUS_CNTL
	.comm	_VGA_COHE_SPEC_TIMER_DIS,8,3    ## @VGA_COHE_SPEC_TIMER_DIS
	.comm	_BIF_SCRATCH0,4,2               ## @BIF_SCRATCH0
	.comm	_SOFT_RESET_BIF,8,3             ## @SOFT_RESET_BIF
	.comm	_SRBM_SOFT_RESET,4,2            ## @SRBM_SOFT_RESET
	.comm	_CONFIG_MEMSIZE,4,2             ## @CONFIG_MEMSIZE
	.no_dead_strip	_r600_gpu_pci_config_reset
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function r600_gpu_pci_config_reset
_r600_gpu_pci_config_reset:             ; @r600_gpu_pci_config_reset
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	w0, [x0, #16]
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_info
	ldr	x23, [x19]
Lloh2:
	adrp	x22, _CHIP_RV770@GOTPAGE
Lloh3:
	ldr	x22, [x22, _CHIP_RV770@GOTPAGEOFF]
	ldr	x24, [x22]
Lloh4:
	adrp	x8, _R_0086D8_CP_ME_CNTL@GOTPAGE
Lloh5:
	ldr	x8, [x8, _R_0086D8_CP_ME_CNTL@GOTPAGEOFF]
Lloh6:
	ldr	w20, [x8]
	mov	w0, #1
	bl	_S_0086D8_CP_ME_HALT
	mov	x21, x0
	cmp	x23, x24
	b.lt	LBB0_2
; %bb.1:
	mov	w0, #1
	bl	_S_0086D8_CP_PFP_HALT
	orr	x21, x0, x21
LBB0_2:
	mov	x0, x20
	mov	x1, x21
	bl	_WREG32
Lloh7:
	adrp	x8, _RLC_CNTL@GOTPAGE
Lloh8:
	ldr	x8, [x8, _RLC_CNTL@GOTPAGEOFF]
Lloh9:
	ldr	w0, [x8]
	mov	x1, #0
	bl	_WREG32
Lloh10:
	adrp	x20, _DMA_RB_CNTL@GOTPAGE
Lloh11:
	ldr	x20, [x20, _DMA_RB_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
                                        ; kill: def $w0 killed $w0 def $x0
	sxtw	x8, w0
Lloh12:
	adrp	x9, _DMA_RB_ENABLE@GOTPAGE
Lloh13:
	ldr	x9, [x9, _DMA_RB_ENABLE@GOTPAGEOFF]
Lloh14:
	ldr	x9, [x9]
	bic	x1, x8, x9
	ldr	w0, [x20]
	bl	_WREG32
	mov	w0, #50
	bl	_mdelay
	ldr	x8, [x19]
	ldr	x9, [x22]
	cmp	x8, x9
	b.lt	LBB0_4
; %bb.3:
	mov	x0, x19
	bl	_rv770_set_clk_bypass_mode
LBB0_4:
	ldr	w0, [x19, #20]
	bl	_pci_clear_master
	add	x1, sp, #8
	mov	x0, x19
	bl	_rv515_mc_stop
	mov	x0, x19
	bl	_r600_mc_wait_for_idle
	cbz	x0, LBB0_6
; %bb.5:
	ldr	w0, [x19, #16]
Lloh15:
	adrp	x1, l_.str.1@PAGE
Lloh16:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_warn
LBB0_6:
Lloh17:
	adrp	x20, _BUS_CNTL@GOTPAGE
Lloh18:
	ldr	x20, [x20, _BUS_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
                                        ; kill: def $w0 killed $w0 def $x0
	sxtw	x8, w0
Lloh19:
	adrp	x9, _VGA_COHE_SPEC_TIMER_DIS@GOTPAGE
Lloh20:
	ldr	x9, [x9, _VGA_COHE_SPEC_TIMER_DIS@GOTPAGEOFF]
Lloh21:
	ldr	x9, [x9]
	orr	x1, x9, x8
	ldr	w0, [x20]
	bl	_WREG32
Lloh22:
	adrp	x8, _BIF_SCRATCH0@GOTPAGE
Lloh23:
	ldr	x8, [x8, _BIF_SCRATCH0@GOTPAGEOFF]
Lloh24:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x0, x19
	bl	_radeon_pci_config_reset
	mov	w0, #1
	bl	_mdelay
Lloh25:
	adrp	x8, _SOFT_RESET_BIF@GOTPAGE
Lloh26:
	ldr	x8, [x8, _SOFT_RESET_BIF@GOTPAGEOFF]
Lloh27:
	ldr	x1, [x8]
Lloh28:
	adrp	x20, _SRBM_SOFT_RESET@GOTPAGE
Lloh29:
	ldr	x20, [x20, _SRBM_SOFT_RESET@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_WREG32
	mov	w0, #1
	bl	_mdelay
	ldr	w0, [x20]
	mov	x1, #0
	bl	_WREG32
	ldr	x8, [x19, #8]
	cmp	x8, #1
	b.lt	LBB0_10
; %bb.7:
	mov	x20, #0
Lloh30:
	adrp	x21, _CONFIG_MEMSIZE@GOTPAGE
Lloh31:
	ldr	x21, [x21, _CONFIG_MEMSIZE@GOTPAGEOFF]
LBB0_8:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x21]
	bl	_RREG32
	cmn	w0, #1
	b.ne	LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=1
	mov	w0, #1
	bl	_udelay
	add	x20, x20, #1
	ldr	x8, [x19, #8]
	cmp	x20, x8
	b.lt	LBB0_8
LBB0_10:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh30, Lloh31
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"GPU pci config reset\n"

	.comm	_CHIP_RV770,8,3                 ; @CHIP_RV770
	.comm	_R_0086D8_CP_ME_CNTL,4,2        ; @R_0086D8_CP_ME_CNTL
	.comm	_RLC_CNTL,4,2                   ; @RLC_CNTL
	.comm	_DMA_RB_CNTL,4,2                ; @DMA_RB_CNTL
	.comm	_DMA_RB_ENABLE,8,3              ; @DMA_RB_ENABLE
l_.str.1:                               ; @.str.1
	.asciz	"Wait for MC idle timedout !\n"

	.comm	_BUS_CNTL,4,2                   ; @BUS_CNTL
	.comm	_VGA_COHE_SPEC_TIMER_DIS,8,3    ; @VGA_COHE_SPEC_TIMER_DIS
	.comm	_BIF_SCRATCH0,4,2               ; @BIF_SCRATCH0
	.comm	_SOFT_RESET_BIF,8,3             ; @SOFT_RESET_BIF
	.comm	_SRBM_SOFT_RESET,4,2            ; @SRBM_SOFT_RESET
	.comm	_CONFIG_MEMSIZE,4,2             ; @CONFIG_MEMSIZE
	.no_dead_strip	_r600_gpu_pci_config_reset
.subsections_via_symbols
