	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function _dpu_encoder_phys_cmd_update_intf_cfg
__dpu_encoder_phys_cmd_update_intf_cfg: ## @_dpu_encoder_phys_cmd_update_intf_cfg
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	subq	$32, %rsp
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	callq	_to_dpu_encoder_phys_cmd
	movl	$0, -24(%rbp)
	testq	%rbx, %rbx
	je	LBB0_4
## %bb.1:
	movq	8(%rbx), %r14
	testq	%r14, %r14
	je	LBB0_4
## %bb.2:
	cmpq	$0, (%r14)
	je	LBB0_4
## %bb.3:
	movl	(%rbx), %ecx
	movl	%ecx, -28(%rbp)
	movq	_DPU_CTL_MODE_SEL_CMD@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, -32(%rbp)
	movl	(%rax), %eax
	movl	%eax, -36(%rbp)
	movq	%rbx, %rdi
	callq	_dpu_encoder_helper_get_3d_blend_mode
	movl	%eax, -40(%rbp)
	leaq	-40(%rbp), %rsi
	movq	%r14, %rdi
	callq	*(%r14)
LBB0_4:
	addq	$32, %rsp
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DPU_CTL_MODE_SEL_CMD,4,2       ## @DPU_CTL_MODE_SEL_CMD
	.no_dead_strip	__dpu_encoder_phys_cmd_update_intf_cfg
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function _dpu_encoder_phys_cmd_update_intf_cfg
__dpu_encoder_phys_cmd_update_intf_cfg: ; @_dpu_encoder_phys_cmd_update_intf_cfg
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_to_dpu_encoder_phys_cmd
	str	wzr, [sp, #24]
	cbz	x19, LBB0_4
; %bb.1:
	ldr	x20, [x19, #8]
	cbz	x20, LBB0_4
; %bb.2:
	ldr	x8, [x20]
	cbz	x8, LBB0_4
; %bb.3:
Lloh0:
	adrp	x8, _DPU_CTL_MODE_SEL_CMD@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DPU_CTL_MODE_SEL_CMD@GOTPAGEOFF]
	ldr	w9, [x19]
Lloh2:
	ldr	w8, [x8]
	stp	w8, w9, [sp, #16]
	ldr	w8, [x0]
	str	w8, [sp, #12]
	mov	x0, x19
	bl	_dpu_encoder_helper_get_3d_blend_mode
	str	w0, [sp, #8]
	ldr	x8, [x20]
	add	x1, sp, #8
	mov	x0, x20
	blr	x8
LBB0_4:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_DPU_CTL_MODE_SEL_CMD,4,2       ; @DPU_CTL_MODE_SEL_CMD
	.no_dead_strip	__dpu_encoder_phys_cmd_update_intf_cfg
.subsections_via_symbols
