	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function navi10_ih_irq_init
_navi10_ih_irq_init:                    ## @navi10_ih_irq_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	leaq	32(%rdi), %r14
	callq	_navi10_ih_disable_interrupts
	movq	8(%r15), %rax
	movq	%r15, %rdi
	callq	*8(%rax)
	movq	_OSSSYS@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	movq	_mmIH_RB_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	32(%r15), %ecx
	sarl	$8, %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmIH_RB_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmIH_RB_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_navi10_ih_rb_cntl
	movq	_IH_RB_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_RPTR_REARM@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%ecx, %ecx
	cmpl	$0, 24(%r15)
	setne	%cl
	movl	%eax, %edi
	callq	_REG_SET_FIELD
	movl	%eax, %r14d
	movq	16(%r15), %rax
	movq	_AMDGPU_FW_LOAD_DIRECT@GOTPCREL(%rip), %rcx
	xorl	%edi, %edi
	cmpq	(%rcx), %rax
	sete	%dil
	callq	_unlikely
	testq	%rax, %rax
	je	LBB0_3
## %bb.1:
	cmpq	$0, 56(%r15)
	je	LBB0_3
## %bb.2:
	movl	(%r12), %edi
	movq	_mmIH_CHICKEN@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_IH_CHICKEN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_MC_SPACE_GPA_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r12), %edi
	movl	(%r13), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
LBB0_3:
	movl	(%r12), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	movl	%r14d, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %ebx
	movq	_mmIH_RB_WPTR_ADDR_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	48(%r15), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r14d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %ebx
	movq	_mmIH_RB_WPTR_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	48(%r15), %edi
	callq	_upper_32_bits
	movzwl	%ax, %ecx
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r14d, %edx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmIH_RB_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmIH_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmIH_DOORBELL_RPTR@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	cmpq	$0, 40(%r15)
	movq	_IH_DOORBELL_RPTR@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	je	LBB0_5
## %bb.4:
	movq	_OFFSET@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	36(%r15), %ecx
	movl	%eax, %edi
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	jmp	LBB0_6
LBB0_5:
	movq	_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
LBB0_6:
	callq	_REG_SET_FIELD
	movl	(%r12), %edi
	movl	(%r14), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	8(%r15), %rax
	movq	40(%r15), %rsi
	movl	36(%r15), %edx
	movq	%r15, %rdi
	callq	*(%rax)
	movl	(%r12), %edi
	movq	_mmIH_STORM_CLIENT_LIST_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_IH_STORM_CLIENT_LIST_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_CLIENT18_IS_STORM_CLIENT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r12), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmIH_INT_FLOOD_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_IH_INT_FLOOD_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_FLOOD_CNTL_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r12), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r15), %edi
	callq	_pci_set_master
	movq	%r15, %rdi
	callq	_navi10_ih_enable_interrupts
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_OSSSYS,4,2                     ## @OSSSYS
	.comm	_mmIH_RB_BASE,4,2               ## @mmIH_RB_BASE
	.comm	_mmIH_RB_BASE_HI,4,2            ## @mmIH_RB_BASE_HI
	.comm	_mmIH_RB_CNTL,4,2               ## @mmIH_RB_CNTL
	.comm	_IH_RB_CNTL,4,2                 ## @IH_RB_CNTL
	.comm	_RPTR_REARM,4,2                 ## @RPTR_REARM
	.comm	_AMDGPU_FW_LOAD_DIRECT,8,3      ## @AMDGPU_FW_LOAD_DIRECT
	.comm	_mmIH_CHICKEN,4,2               ## @mmIH_CHICKEN
	.comm	_IH_CHICKEN,4,2                 ## @IH_CHICKEN
	.comm	_MC_SPACE_GPA_ENABLE,4,2        ## @MC_SPACE_GPA_ENABLE
	.comm	_mmIH_RB_WPTR_ADDR_LO,4,2       ## @mmIH_RB_WPTR_ADDR_LO
	.comm	_mmIH_RB_WPTR_ADDR_HI,4,2       ## @mmIH_RB_WPTR_ADDR_HI
	.comm	_mmIH_RB_RPTR,4,2               ## @mmIH_RB_RPTR
	.comm	_mmIH_RB_WPTR,4,2               ## @mmIH_RB_WPTR
	.comm	_mmIH_DOORBELL_RPTR,4,2         ## @mmIH_DOORBELL_RPTR
	.comm	_IH_DOORBELL_RPTR,4,2           ## @IH_DOORBELL_RPTR
	.comm	_OFFSET,4,2                     ## @OFFSET
	.comm	_ENABLE,4,2                     ## @ENABLE
	.comm	_mmIH_STORM_CLIENT_LIST_CNTL,4,2 ## @mmIH_STORM_CLIENT_LIST_CNTL
	.comm	_IH_STORM_CLIENT_LIST_CNTL,4,2  ## @IH_STORM_CLIENT_LIST_CNTL
	.comm	_CLIENT18_IS_STORM_CLIENT,4,2   ## @CLIENT18_IS_STORM_CLIENT
	.comm	_mmIH_INT_FLOOD_CNTL,4,2        ## @mmIH_INT_FLOOD_CNTL
	.comm	_IH_INT_FLOOD_CNTL,4,2          ## @IH_INT_FLOOD_CNTL
	.comm	_FLOOD_CNTL_ENABLE,4,2          ## @FLOOD_CNTL_ENABLE
	.no_dead_strip	_navi10_ih_irq_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function navi10_ih_irq_init
_navi10_ih_irq_init:                    ; @navi10_ih_irq_init
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	bl	_navi10_ih_disable_interrupts
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	mov	x0, x19
	blr	x8
Lloh0:
	adrp	x22, _OSSSYS@GOTPAGE
Lloh1:
	ldr	x22, [x22, _OSSSYS@GOTPAGEOFF]
Lloh2:
	adrp	x8, _mmIH_RB_BASE@GOTPAGE
Lloh3:
	ldr	x8, [x8, _mmIH_RB_BASE@GOTPAGEOFF]
	ldr	w0, [x22]
Lloh4:
	ldr	w2, [x8]
	mov	x21, x19
	ldr	w8, [x21, #32]!
	asr	w3, w8, #8
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh5:
	adrp	x8, _mmIH_RB_BASE_HI@GOTPAGE
Lloh6:
	ldr	x8, [x8, _mmIH_RB_BASE_HI@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh8:
	adrp	x23, _mmIH_RB_CNTL@GOTPAGE
Lloh9:
	ldr	x23, [x23, _mmIH_RB_CNTL@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	w1, #0
	bl	_RREG32_SOC15
	mov	x1, x0
	mov	x0, x21
	bl	_navi10_ih_rb_cntl
Lloh10:
	adrp	x8, _IH_RB_CNTL@GOTPAGE
Lloh11:
	ldr	x8, [x8, _IH_RB_CNTL@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
Lloh13:
	adrp	x8, _RPTR_REARM@GOTPAGE
Lloh14:
	ldr	x8, [x8, _RPTR_REARM@GOTPAGEOFF]
Lloh15:
	ldr	w2, [x8]
	ldur	w8, [x21, #-8]
	cmp	w8, #0
	cset	w3, ne
	bl	_REG_SET_FIELD
	mov	x20, x0
	ldur	x8, [x21, #-16]
Lloh16:
	adrp	x9, _AMDGPU_FW_LOAD_DIRECT@GOTPAGE
Lloh17:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_DIRECT@GOTPAGEOFF]
Lloh18:
	ldr	x9, [x9]
	cmp	x8, x9
	cset	w0, eq
	bl	_unlikely
	cbz	x0, LBB0_3
; %bb.1:
	ldr	x8, [x19, #56]
	cbz	x8, LBB0_3
; %bb.2:
	ldr	w0, [x22]
Lloh19:
	adrp	x21, _mmIH_CHICKEN@GOTPAGE
Lloh20:
	ldr	x21, [x21, _mmIH_CHICKEN@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh21:
	adrp	x8, _IH_CHICKEN@GOTPAGE
Lloh22:
	ldr	x8, [x8, _IH_CHICKEN@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
Lloh24:
	adrp	x8, _MC_SPACE_GPA_ENABLE@GOTPAGE
Lloh25:
	ldr	x8, [x8, _MC_SPACE_GPA_ENABLE@GOTPAGEOFF]
Lloh26:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x22]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_WREG32_SOC15
LBB0_3:
	ldr	w0, [x22]
	ldr	w2, [x23]
	mov	w1, #0
	mov	x3, x20
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh27:
	adrp	x8, _mmIH_RB_WPTR_ADDR_LO@GOTPAGE
Lloh28:
	ldr	x8, [x8, _mmIH_RB_WPTR_ADDR_LO@GOTPAGEOFF]
Lloh29:
	ldr	w21, [x8]
	ldr	w0, [x19, #48]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh30:
	adrp	x8, _mmIH_RB_WPTR_ADDR_HI@GOTPAGE
Lloh31:
	ldr	x8, [x8, _mmIH_RB_WPTR_ADDR_HI@GOTPAGEOFF]
Lloh32:
	ldr	w21, [x8]
	ldr	w0, [x19, #48]
	bl	_upper_32_bits
	and	w3, w0, #0xffff
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh33:
	adrp	x8, _mmIH_RB_RPTR@GOTPAGE
Lloh34:
	ldr	x8, [x8, _mmIH_RB_RPTR@GOTPAGEOFF]
Lloh35:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh36:
	adrp	x8, _mmIH_RB_WPTR@GOTPAGE
Lloh37:
	ldr	x8, [x8, _mmIH_RB_WPTR@GOTPAGEOFF]
Lloh38:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh39:
	adrp	x20, _mmIH_DOORBELL_RPTR@GOTPAGE
Lloh40:
	ldr	x20, [x20, _mmIH_DOORBELL_RPTR@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_RREG32_SOC15
	ldr	x8, [x19, #40]
Lloh41:
	adrp	x21, _IH_DOORBELL_RPTR@GOTPAGE
Lloh42:
	ldr	x21, [x21, _IH_DOORBELL_RPTR@GOTPAGEOFF]
	ldr	w1, [x21]
	cbz	x8, LBB0_5
; %bb.4:
Lloh43:
	adrp	x8, _OFFSET@GOTPAGE
Lloh44:
	ldr	x8, [x8, _OFFSET@GOTPAGEOFF]
Lloh45:
	ldr	w2, [x8]
	ldr	w3, [x19, #36]
	bl	_REG_SET_FIELD
	ldr	w1, [x21]
Lloh46:
	adrp	x8, _ENABLE@GOTPAGE
Lloh47:
	ldr	x8, [x8, _ENABLE@GOTPAGEOFF]
Lloh48:
	ldr	w2, [x8]
	mov	w3, #1
	b	LBB0_6
LBB0_5:
Lloh49:
	adrp	x8, _ENABLE@GOTPAGE
Lloh50:
	ldr	x8, [x8, _ENABLE@GOTPAGEOFF]
Lloh51:
	ldr	w2, [x8]
	mov	w3, #0
LBB0_6:
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x22]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	ldr	x1, [x19, #40]
	ldr	w2, [x19, #36]
	mov	x0, x19
	blr	x8
	ldr	w0, [x22]
Lloh52:
	adrp	x20, _mmIH_STORM_CLIENT_LIST_CNTL@GOTPAGE
Lloh53:
	ldr	x20, [x20, _mmIH_STORM_CLIENT_LIST_CNTL@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh54:
	adrp	x8, _IH_STORM_CLIENT_LIST_CNTL@GOTPAGE
Lloh55:
	ldr	x8, [x8, _IH_STORM_CLIENT_LIST_CNTL@GOTPAGEOFF]
Lloh56:
	ldr	w1, [x8]
Lloh57:
	adrp	x8, _CLIENT18_IS_STORM_CLIENT@GOTPAGE
Lloh58:
	ldr	x8, [x8, _CLIENT18_IS_STORM_CLIENT@GOTPAGEOFF]
Lloh59:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x22]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh60:
	adrp	x20, _mmIH_INT_FLOOD_CNTL@GOTPAGE
Lloh61:
	ldr	x20, [x20, _mmIH_INT_FLOOD_CNTL@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh62:
	adrp	x8, _IH_INT_FLOOD_CNTL@GOTPAGE
Lloh63:
	ldr	x8, [x8, _IH_INT_FLOOD_CNTL@GOTPAGEOFF]
Lloh64:
	ldr	w1, [x8]
Lloh65:
	adrp	x8, _FLOOD_CNTL_ENABLE@GOTPAGE
Lloh66:
	ldr	x8, [x8, _FLOOD_CNTL_ENABLE@GOTPAGEOFF]
Lloh67:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x22]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x19]
	bl	_pci_set_master
	mov	x0, x19
	bl	_navi10_ih_enable_interrupts
	mov	w0, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh52, Lloh53
	.cfi_endproc
                                        ; -- End function
	.comm	_OSSSYS,4,2                     ; @OSSSYS
	.comm	_mmIH_RB_BASE,4,2               ; @mmIH_RB_BASE
	.comm	_mmIH_RB_BASE_HI,4,2            ; @mmIH_RB_BASE_HI
	.comm	_mmIH_RB_CNTL,4,2               ; @mmIH_RB_CNTL
	.comm	_IH_RB_CNTL,4,2                 ; @IH_RB_CNTL
	.comm	_RPTR_REARM,4,2                 ; @RPTR_REARM
	.comm	_AMDGPU_FW_LOAD_DIRECT,8,3      ; @AMDGPU_FW_LOAD_DIRECT
	.comm	_mmIH_CHICKEN,4,2               ; @mmIH_CHICKEN
	.comm	_IH_CHICKEN,4,2                 ; @IH_CHICKEN
	.comm	_MC_SPACE_GPA_ENABLE,4,2        ; @MC_SPACE_GPA_ENABLE
	.comm	_mmIH_RB_WPTR_ADDR_LO,4,2       ; @mmIH_RB_WPTR_ADDR_LO
	.comm	_mmIH_RB_WPTR_ADDR_HI,4,2       ; @mmIH_RB_WPTR_ADDR_HI
	.comm	_mmIH_RB_RPTR,4,2               ; @mmIH_RB_RPTR
	.comm	_mmIH_RB_WPTR,4,2               ; @mmIH_RB_WPTR
	.comm	_mmIH_DOORBELL_RPTR,4,2         ; @mmIH_DOORBELL_RPTR
	.comm	_IH_DOORBELL_RPTR,4,2           ; @IH_DOORBELL_RPTR
	.comm	_OFFSET,4,2                     ; @OFFSET
	.comm	_ENABLE,4,2                     ; @ENABLE
	.comm	_mmIH_STORM_CLIENT_LIST_CNTL,4,2 ; @mmIH_STORM_CLIENT_LIST_CNTL
	.comm	_IH_STORM_CLIENT_LIST_CNTL,4,2  ; @IH_STORM_CLIENT_LIST_CNTL
	.comm	_CLIENT18_IS_STORM_CLIENT,4,2   ; @CLIENT18_IS_STORM_CLIENT
	.comm	_mmIH_INT_FLOOD_CNTL,4,2        ; @mmIH_INT_FLOOD_CNTL
	.comm	_IH_INT_FLOOD_CNTL,4,2          ; @IH_INT_FLOOD_CNTL
	.comm	_FLOOD_CNTL_ENABLE,4,2          ; @FLOOD_CNTL_ENABLE
	.no_dead_strip	_navi10_ih_irq_init
.subsections_via_symbols
