	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v2_5_early_init
_vcn_v2_5_early_init:                   ## @vcn_v2_5_early_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	(%rdi), %rax
	movq	_CHIP_ARCTURUS@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_8
## %bb.1:
	movq	_VCN25_MAX_HW_INSTANCES_ARCTURUS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 8(%r14)
	testl	%eax, %eax
	jle	LBB0_6
## %bb.2:
	xorl	%ebx, %ebx
	movq	_UVD@GOTPCREL(%rip), %r15
	movq	_mmCC_UVD_HARVESTING@GOTPCREL(%rip), %r12
	movq	_CC_UVD_HARVESTING__UVD_DISABLE_MASK@GOTPCREL(%rip), %r13
	jmp	LBB0_3
	.p2align	4, 0x90
LBB0_5:                                 ##   in Loop: Header=BB0_3 Depth=1
	incl	%ebx
	cmpl	8(%r14), %ebx
	jge	LBB0_6
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r15), %edi
	movl	(%r12), %edx
	movl	%ebx, %esi
	callq	_RREG32_SOC15
	testl	%eax, (%r13)
	je	LBB0_5
## %bb.4:                               ##   in Loop: Header=BB0_3 Depth=1
	movl	$1, %eax
	movl	%ebx, %ecx
	shll	%cl, %eax
	orl	%eax, 12(%r14)
	jmp	LBB0_5
LBB0_8:
	movl	$1, 8(%r14)
	jmp	LBB0_9
LBB0_6:
	movq	_AMDGPU_VCN_HARVEST_VCN0@GOTPCREL(%rip), %rax
	movq	_AMDGPU_VCN_HARVEST_VCN1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	cmpl	%ecx, 12(%r14)
	jne	LBB0_9
## %bb.7:
	movq	_ENOENT@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_10
LBB0_9:
	movl	$2, 16(%r14)
	movq	%r14, %rdi
	callq	_vcn_v2_5_set_dec_ring_funcs
	movq	%r14, %rdi
	callq	_vcn_v2_5_set_enc_ring_funcs
	movq	%r14, %rdi
	callq	_vcn_v2_5_set_jpeg_ring_funcs
	movq	%r14, %rdi
	callq	_vcn_v2_5_set_irq_funcs
	xorl	%eax, %eax
LBB0_10:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CHIP_ARCTURUS,8,3              ## @CHIP_ARCTURUS
	.comm	_VCN25_MAX_HW_INSTANCES_ARCTURUS,4,2 ## @VCN25_MAX_HW_INSTANCES_ARCTURUS
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmCC_UVD_HARVESTING,4,2        ## @mmCC_UVD_HARVESTING
	.comm	_CC_UVD_HARVESTING__UVD_DISABLE_MASK,4,2 ## @CC_UVD_HARVESTING__UVD_DISABLE_MASK
	.comm	_AMDGPU_VCN_HARVEST_VCN0,4,2    ## @AMDGPU_VCN_HARVEST_VCN0
	.comm	_AMDGPU_VCN_HARVEST_VCN1,4,2    ## @AMDGPU_VCN_HARVEST_VCN1
	.comm	_ENOENT,4,2                     ## @ENOENT
	.no_dead_strip	_vcn_v2_5_early_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v2_5_early_init
_vcn_v2_5_early_init:                   ; @vcn_v2_5_early_init
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	x8, [x0]
Lloh0:
	adrp	x9, _CHIP_ARCTURUS@GOTPAGE
Lloh1:
	ldr	x9, [x9, _CHIP_ARCTURUS@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_6
; %bb.1:
Lloh3:
	adrp	x8, _VCN25_MAX_HW_INSTANCES_ARCTURUS@GOTPAGE
Lloh4:
	ldr	x8, [x8, _VCN25_MAX_HW_INSTANCES_ARCTURUS@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	str	w8, [x19, #8]
	cmp	w8, #1
	b.lt	LBB0_7
; %bb.2:
	mov	w20, #0
Lloh6:
	adrp	x21, _UVD@GOTPAGE
Lloh7:
	ldr	x21, [x21, _UVD@GOTPAGEOFF]
Lloh8:
	adrp	x22, _mmCC_UVD_HARVESTING@GOTPAGE
Lloh9:
	ldr	x22, [x22, _mmCC_UVD_HARVESTING@GOTPAGEOFF]
	mov	w23, #1
Lloh10:
	adrp	x24, _CC_UVD_HARVESTING__UVD_DISABLE_MASK@GOTPAGE
Lloh11:
	ldr	x24, [x24, _CC_UVD_HARVESTING__UVD_DISABLE_MASK@GOTPAGEOFF]
	b	LBB0_4
LBB0_3:                                 ;   in Loop: Header=BB0_4 Depth=1
	add	w20, w20, #1
	ldr	w8, [x19, #8]
	cmp	w20, w8
	b.ge	LBB0_7
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x21]
	ldr	w2, [x22]
	mov	x1, x20
	bl	_RREG32_SOC15
	ldr	w8, [x24]
	tst	w8, w0
	b.eq	LBB0_3
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	lsl	w8, w23, w20
	ldr	w9, [x19, #12]
	orr	w8, w9, w8
	str	w8, [x19, #12]
	b	LBB0_3
LBB0_6:
	mov	w8, #1
	str	w8, [x19, #8]
	b	LBB0_9
LBB0_7:
	ldr	w8, [x19, #12]
Lloh12:
	adrp	x9, _AMDGPU_VCN_HARVEST_VCN0@GOTPAGE
Lloh13:
	ldr	x9, [x9, _AMDGPU_VCN_HARVEST_VCN0@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
Lloh15:
	adrp	x10, _AMDGPU_VCN_HARVEST_VCN1@GOTPAGE
Lloh16:
	ldr	x10, [x10, _AMDGPU_VCN_HARVEST_VCN1@GOTPAGEOFF]
Lloh17:
	ldr	w10, [x10]
	orr	w9, w10, w9
	cmp	w8, w9
	b.ne	LBB0_9
; %bb.8:
Lloh18:
	adrp	x8, _ENOENT@GOTPAGE
Lloh19:
	ldr	x8, [x8, _ENOENT@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_10
LBB0_9:
	mov	w8, #2
	str	w8, [x19, #16]
	mov	x0, x19
	bl	_vcn_v2_5_set_dec_ring_funcs
	mov	x0, x19
	bl	_vcn_v2_5_set_enc_ring_funcs
	mov	x0, x19
	bl	_vcn_v2_5_set_jpeg_ring_funcs
	mov	x0, x19
	bl	_vcn_v2_5_set_irq_funcs
	mov	w0, #0
LBB0_10:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.cfi_endproc
                                        ; -- End function
	.comm	_CHIP_ARCTURUS,8,3              ; @CHIP_ARCTURUS
	.comm	_VCN25_MAX_HW_INSTANCES_ARCTURUS,4,2 ; @VCN25_MAX_HW_INSTANCES_ARCTURUS
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmCC_UVD_HARVESTING,4,2        ; @mmCC_UVD_HARVESTING
	.comm	_CC_UVD_HARVESTING__UVD_DISABLE_MASK,4,2 ; @CC_UVD_HARVESTING__UVD_DISABLE_MASK
	.comm	_AMDGPU_VCN_HARVEST_VCN0,4,2    ; @AMDGPU_VCN_HARVEST_VCN0
	.comm	_AMDGPU_VCN_HARVEST_VCN1,4,2    ; @AMDGPU_VCN_HARVEST_VCN1
	.comm	_ENOENT,4,2                     ; @ENOENT
	.no_dead_strip	_vcn_v2_5_early_init
.subsections_via_symbols
