	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rv6xx_enable_bif_dynamic_pcie_gen2
_rv6xx_enable_bif_dynamic_pcie_gen2:    ## @rv6xx_enable_bif_dynamic_pcie_gen2
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r15d
	movq	_PCIE_LC_SPEED_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_RREG32_PCIE_PORT
	movl	%eax, %r14d
	movq	_LC_HW_VOLTAGE_IF_CONTROL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	xorl	%edi, %edi
	testl	%r15d, %r15d
	setne	%dil
	callq	_LC_HW_VOLTAGE_IF_CONTROL
	notl	%ebx
	andl	%r14d, %ebx
	orl	%eax, %ebx
	movl	(%r12), %edi
	movl	%ebx, %esi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_PCIE_PORT               ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PCIE_LC_SPEED_CNTL,4,2         ## @PCIE_LC_SPEED_CNTL
	.comm	_LC_HW_VOLTAGE_IF_CONTROL_MASK,4,2 ## @LC_HW_VOLTAGE_IF_CONTROL_MASK
	.no_dead_strip	_rv6xx_enable_bif_dynamic_pcie_gen2
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rv6xx_enable_bif_dynamic_pcie_gen2
_rv6xx_enable_bif_dynamic_pcie_gen2:    ; @rv6xx_enable_bif_dynamic_pcie_gen2
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x1
Lloh0:
	adrp	x21, _PCIE_LC_SPEED_CNTL@GOTPAGE
Lloh1:
	ldr	x21, [x21, _PCIE_LC_SPEED_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32_PCIE_PORT
	mov	x20, x0
Lloh2:
	adrp	x8, _LC_HW_VOLTAGE_IF_CONTROL_MASK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _LC_HW_VOLTAGE_IF_CONTROL_MASK@GOTPAGEOFF]
Lloh4:
	ldr	w22, [x8]
	cmp	w19, #0
	cset	w0, ne
	bl	_LC_HW_VOLTAGE_IF_CONTROL
	bic	w8, w20, w22
	orr	w1, w0, w8
	ldr	w0, [x21]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32_PCIE_PORT
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_PCIE_LC_SPEED_CNTL,4,2         ; @PCIE_LC_SPEED_CNTL
	.comm	_LC_HW_VOLTAGE_IF_CONTROL_MASK,4,2 ; @LC_HW_VOLTAGE_IF_CONTROL_MASK
	.no_dead_strip	_rv6xx_enable_bif_dynamic_pcie_gen2
.subsections_via_symbols
