	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_legacy_tv_detect
_radeon_legacy_tv_detect:               ## @radeon_legacy_tv_detect
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %rbx
	movq	(%rdi), %rax
	movq	(%rax), %rdi
	callq	_ASIC_IS_R300
	testq	%rax, %rax
	je	LBB0_1
## %bb.7:
	movq	%rbx, %rdi
	movq	%r14, %rsi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_r300_legacy_tv_detect          ## TAILCALL
LBB0_1:
	movq	_RADEON_DAC_CNTL2@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32
	movl	%eax, %r13d
	movq	_RADEON_TV_MASTER_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r14d
	movq	_RADEON_TV_DAC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_RADEON_CONFIG_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %ebx
	movq	_RADEON_TV_PRE_DAC_MUX_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_RREG32
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	_RADEON_DAC2_DAC2_CLK_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	movl	%r13d, -52(%rbp)                ## 4-byte Spill
	andl	%r13d, %esi
	movq	%r12, %r13
	movl	(%r15), %edi
	movq	_RADEON_TV_MASTER_CNTL@GOTPCREL(%rip), %r12
	movq	_RADEON_TV_DAC_CNTL@GOTPCREL(%rip), %r15
	callq	_WREG32
	movq	_RADEON_TV_ON@GOTPCREL(%rip), %rax
	movl	%r14d, %ecx
	orl	(%rax), %ecx
	movq	_RADEON_TV_ASYNC_RST@GOTPCREL(%rip), %rax
	movq	_RADEON_RESTART_PHASE_FIX@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rax), %edx
	movq	_RADEON_CRT_FIFO_CE_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_RADEON_TV_FIFO_CE_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_RADEON_RE_SYNC_NOW_SEL_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	notl	%edx
	andl	%ecx, %edx
	movq	_RADEON_TV_FIFO_ASYNC_RST@GOTPCREL(%rip), %rax
	movq	_RADEON_CRT_ASYNC_RST@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	orl	%edx, %esi
	movl	(%r12), %edi
	callq	_WREG32
	movq	_RADEON_TV_DAC_NBLANK@GOTPCREL(%rip), %rax
	movq	_RADEON_TV_DAC_NHOLD@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	_RADEON_TV_MONITOR_DETECT_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_RADEON_TV_DAC_STD_NTSC@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_RADEON_TV_DAC_BGADJ_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$8, %eax
	shll	%cl, %eax
	orl	%edx, %eax
	movq	_RADEON_CFG_ATI_REV_ID_MASK@GOTPCREL(%rip), %rcx
	xorl	%edx, %edx
	andl	(%rcx), %ebx
	sete	%dl
	movq	_RADEON_TV_DAC_DACADJ_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	leal	4(,%rdx,4), %esi
	shll	%cl, %esi
	orl	%eax, %esi
	movl	(%r15), %edi
	callq	_WREG32
	movq	_RADEON_C_GRN_EN@GOTPCREL(%rip), %rax
	movq	_RADEON_CMP_BLU_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	_RADEON_RED_MX_FORCE_DAC_DATA@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_RADEON_GRN_MX_FORCE_DAC_DATA@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_RADEON_BLU_MX_FORCE_DAC_DATA@GOTPCREL(%rip), %rax
	movq	_RADEON_TV_FORCE_DAC_DATA_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$265, %esi                      ## imm = 0x109
	shll	%cl, %esi
	orl	(%rax), %edx
	orl	%edx, %esi
	movl	(%r13), %edi
	callq	_WREG32
	movl	$3, %edi
	callq	_mdelay
	movl	(%r15), %edi
	callq	_RREG32
	movq	_RADEON_TV_DAC_GDACDET@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_3
## %bb.2:
	leaq	L_.str(%rip), %rdi
	jmp	LBB0_5
LBB0_3:
	movq	_RADEON_TV_DAC_BDACDET@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_8
## %bb.4:
	leaq	L_.str.1(%rip), %rdi
LBB0_5:
	callq	_DRM_DEBUG_KMS
	movl	$1, %ebx
LBB0_6:
	movl	(%r13), %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movl	(%r15), %edi
	movl	-48(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movl	(%r12), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_RADEON_DAC_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-52(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movl	%ebx, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_8:
	xorl	%ebx, %ebx
	jmp	LBB0_6
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_DAC_CNTL2,4,2           ## @RADEON_DAC_CNTL2
	.comm	_RADEON_TV_MASTER_CNTL,4,2      ## @RADEON_TV_MASTER_CNTL
	.comm	_RADEON_TV_DAC_CNTL,4,2         ## @RADEON_TV_DAC_CNTL
	.comm	_RADEON_CONFIG_CNTL,4,2         ## @RADEON_CONFIG_CNTL
	.comm	_RADEON_TV_PRE_DAC_MUX_CNTL,4,2 ## @RADEON_TV_PRE_DAC_MUX_CNTL
	.comm	_RADEON_DAC2_DAC2_CLK_SEL,4,2   ## @RADEON_DAC2_DAC2_CLK_SEL
	.comm	_RADEON_TV_ON,4,2               ## @RADEON_TV_ON
	.comm	_RADEON_TV_ASYNC_RST,4,2        ## @RADEON_TV_ASYNC_RST
	.comm	_RADEON_RESTART_PHASE_FIX,4,2   ## @RADEON_RESTART_PHASE_FIX
	.comm	_RADEON_CRT_FIFO_CE_EN,4,2      ## @RADEON_CRT_FIFO_CE_EN
	.comm	_RADEON_TV_FIFO_CE_EN,4,2       ## @RADEON_TV_FIFO_CE_EN
	.comm	_RADEON_RE_SYNC_NOW_SEL_MASK,4,2 ## @RADEON_RE_SYNC_NOW_SEL_MASK
	.comm	_RADEON_TV_FIFO_ASYNC_RST,4,2   ## @RADEON_TV_FIFO_ASYNC_RST
	.comm	_RADEON_CRT_ASYNC_RST,4,2       ## @RADEON_CRT_ASYNC_RST
	.comm	_RADEON_TV_DAC_NBLANK,4,2       ## @RADEON_TV_DAC_NBLANK
	.comm	_RADEON_TV_DAC_NHOLD,4,2        ## @RADEON_TV_DAC_NHOLD
	.comm	_RADEON_TV_MONITOR_DETECT_EN,4,2 ## @RADEON_TV_MONITOR_DETECT_EN
	.comm	_RADEON_TV_DAC_STD_NTSC,4,2     ## @RADEON_TV_DAC_STD_NTSC
	.comm	_RADEON_TV_DAC_BGADJ_SHIFT,4,2  ## @RADEON_TV_DAC_BGADJ_SHIFT
	.comm	_RADEON_CFG_ATI_REV_ID_MASK,4,2 ## @RADEON_CFG_ATI_REV_ID_MASK
	.comm	_RADEON_TV_DAC_DACADJ_SHIFT,4,2 ## @RADEON_TV_DAC_DACADJ_SHIFT
	.comm	_RADEON_C_GRN_EN,4,2            ## @RADEON_C_GRN_EN
	.comm	_RADEON_CMP_BLU_EN,4,2          ## @RADEON_CMP_BLU_EN
	.comm	_RADEON_RED_MX_FORCE_DAC_DATA,4,2 ## @RADEON_RED_MX_FORCE_DAC_DATA
	.comm	_RADEON_GRN_MX_FORCE_DAC_DATA,4,2 ## @RADEON_GRN_MX_FORCE_DAC_DATA
	.comm	_RADEON_BLU_MX_FORCE_DAC_DATA,4,2 ## @RADEON_BLU_MX_FORCE_DAC_DATA
	.comm	_RADEON_TV_FORCE_DAC_DATA_SHIFT,4,2 ## @RADEON_TV_FORCE_DAC_DATA_SHIFT
	.comm	_RADEON_TV_DAC_GDACDET,4,2      ## @RADEON_TV_DAC_GDACDET
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"S-video TV connection detected\n"

	.comm	_RADEON_TV_DAC_BDACDET,4,2      ## @RADEON_TV_DAC_BDACDET
L_.str.1:                               ## @.str.1
	.asciz	"Composite TV connection detected\n"

	.no_dead_strip	_radeon_legacy_tv_detect
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_legacy_tv_detect
_radeon_legacy_tv_detect:               ; @radeon_legacy_tv_detect
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x1
	mov	x20, x0
	ldr	x8, [x0]
	ldr	x0, [x8]
	bl	_ASIC_IS_R300
	cbz	x0, LBB0_2
; %bb.1:
	mov	x0, x20
	mov	x1, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_r300_legacy_tv_detect
LBB0_2:
Lloh0:
	adrp	x24, _RADEON_DAC_CNTL2@GOTPAGE
Lloh1:
	ldr	x24, [x24, _RADEON_DAC_CNTL2@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_RREG32
	mov	x19, x0
Lloh2:
	adrp	x25, _RADEON_TV_MASTER_CNTL@GOTPAGE
Lloh3:
	ldr	x25, [x25, _RADEON_TV_MASTER_CNTL@GOTPAGEOFF]
	ldr	w0, [x25]
	bl	_RREG32
	mov	x20, x0
Lloh4:
	adrp	x26, _RADEON_TV_DAC_CNTL@GOTPAGE
Lloh5:
	ldr	x26, [x26, _RADEON_TV_DAC_CNTL@GOTPAGEOFF]
	ldr	w0, [x26]
	bl	_RREG32
	mov	x21, x0
Lloh6:
	adrp	x8, _RADEON_CONFIG_CNTL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_CONFIG_CNTL@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x23, x0
Lloh9:
	adrp	x27, _RADEON_TV_PRE_DAC_MUX_CNTL@GOTPAGE
Lloh10:
	ldr	x27, [x27, _RADEON_TV_PRE_DAC_MUX_CNTL@GOTPAGEOFF]
	ldr	w0, [x27]
	bl	_RREG32
	mov	x22, x0
Lloh11:
	adrp	x8, _RADEON_DAC2_DAC2_CLK_SEL@GOTPAGE
Lloh12:
	ldr	x8, [x8, _RADEON_DAC2_DAC2_CLK_SEL@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
	bic	w1, w19, w8
	ldr	w0, [x24]
	bl	_WREG32
Lloh14:
	adrp	x8, _RADEON_TV_ON@GOTPAGE
Lloh15:
	ldr	x8, [x8, _RADEON_TV_ON@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
	orr	w8, w8, w20
Lloh17:
	adrp	x9, _RADEON_TV_ASYNC_RST@GOTPAGE
Lloh18:
	ldr	x9, [x9, _RADEON_TV_ASYNC_RST@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
Lloh20:
	adrp	x10, _RADEON_RESTART_PHASE_FIX@GOTPAGE
Lloh21:
	ldr	x10, [x10, _RADEON_RESTART_PHASE_FIX@GOTPAGEOFF]
Lloh22:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh23:
	adrp	x10, _RADEON_CRT_FIFO_CE_EN@GOTPAGE
Lloh24:
	ldr	x10, [x10, _RADEON_CRT_FIFO_CE_EN@GOTPAGEOFF]
Lloh25:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh26:
	adrp	x10, _RADEON_TV_FIFO_CE_EN@GOTPAGE
Lloh27:
	ldr	x10, [x10, _RADEON_TV_FIFO_CE_EN@GOTPAGEOFF]
Lloh28:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh29:
	adrp	x10, _RADEON_RE_SYNC_NOW_SEL_MASK@GOTPAGE
Lloh30:
	ldr	x10, [x10, _RADEON_RE_SYNC_NOW_SEL_MASK@GOTPAGEOFF]
Lloh31:
	ldr	w10, [x10]
	orr	w9, w9, w10
	bic	w8, w8, w9
Lloh32:
	adrp	x9, _RADEON_TV_FIFO_ASYNC_RST@GOTPAGE
Lloh33:
	ldr	x9, [x9, _RADEON_TV_FIFO_ASYNC_RST@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
Lloh35:
	adrp	x10, _RADEON_CRT_ASYNC_RST@GOTPAGE
Lloh36:
	ldr	x10, [x10, _RADEON_CRT_ASYNC_RST@GOTPAGEOFF]
Lloh37:
	ldr	w10, [x10]
	orr	w9, w10, w9
	orr	w1, w9, w8
	ldr	w0, [x25]
	bl	_WREG32
Lloh38:
	adrp	x8, _RADEON_TV_DAC_NBLANK@GOTPAGE
Lloh39:
	ldr	x8, [x8, _RADEON_TV_DAC_NBLANK@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
Lloh41:
	adrp	x9, _RADEON_TV_DAC_NHOLD@GOTPAGE
Lloh42:
	ldr	x9, [x9, _RADEON_TV_DAC_NHOLD@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh44:
	adrp	x9, _RADEON_TV_MONITOR_DETECT_EN@GOTPAGE
Lloh45:
	ldr	x9, [x9, _RADEON_TV_MONITOR_DETECT_EN@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh47:
	adrp	x9, _RADEON_TV_DAC_STD_NTSC@GOTPAGE
Lloh48:
	ldr	x9, [x9, _RADEON_TV_DAC_STD_NTSC@GOTPAGEOFF]
Lloh49:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh50:
	adrp	x9, _RADEON_TV_DAC_BGADJ_SHIFT@GOTPAGE
Lloh51:
	ldr	x9, [x9, _RADEON_TV_DAC_BGADJ_SHIFT@GOTPAGEOFF]
Lloh52:
	ldr	w9, [x9]
	mov	w10, #8
	lsl	w9, w10, w9
	orr	w8, w8, w9
Lloh53:
	adrp	x9, _RADEON_CFG_ATI_REV_ID_MASK@GOTPAGE
Lloh54:
	ldr	x9, [x9, _RADEON_CFG_ATI_REV_ID_MASK@GOTPAGEOFF]
Lloh55:
	ldr	w9, [x9]
Lloh56:
	adrp	x11, _RADEON_TV_DAC_DACADJ_SHIFT@GOTPAGE
Lloh57:
	ldr	x11, [x11, _RADEON_TV_DAC_DACADJ_SHIFT@GOTPAGEOFF]
Lloh58:
	ldr	w11, [x11]
	tst	w9, w23
	mov	w9, #4
	csel	w9, w10, w9, eq
	lsl	w9, w9, w11
	orr	w1, w8, w9
	ldr	w0, [x26]
	bl	_WREG32
Lloh59:
	adrp	x8, _RADEON_C_GRN_EN@GOTPAGE
Lloh60:
	ldr	x8, [x8, _RADEON_C_GRN_EN@GOTPAGEOFF]
Lloh61:
	ldr	w8, [x8]
Lloh62:
	adrp	x9, _RADEON_CMP_BLU_EN@GOTPAGE
Lloh63:
	ldr	x9, [x9, _RADEON_CMP_BLU_EN@GOTPAGEOFF]
Lloh64:
	ldr	w9, [x9]
Lloh65:
	adrp	x10, _RADEON_RED_MX_FORCE_DAC_DATA@GOTPAGE
Lloh66:
	ldr	x10, [x10, _RADEON_RED_MX_FORCE_DAC_DATA@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh67:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh68:
	adrp	x9, _RADEON_GRN_MX_FORCE_DAC_DATA@GOTPAGE
Lloh69:
	ldr	x9, [x9, _RADEON_GRN_MX_FORCE_DAC_DATA@GOTPAGEOFF]
Lloh70:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh71:
	adrp	x9, _RADEON_BLU_MX_FORCE_DAC_DATA@GOTPAGE
Lloh72:
	ldr	x9, [x9, _RADEON_BLU_MX_FORCE_DAC_DATA@GOTPAGEOFF]
Lloh73:
	ldr	w9, [x9]
Lloh74:
	adrp	x10, _RADEON_TV_FORCE_DAC_DATA_SHIFT@GOTPAGE
Lloh75:
	ldr	x10, [x10, _RADEON_TV_FORCE_DAC_DATA_SHIFT@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh76:
	ldr	w9, [x10]
	mov	w10, #265
	lsl	w9, w10, w9
	orr	w1, w8, w9
	ldr	w0, [x27]
	bl	_WREG32
	mov	w0, #3
	bl	_mdelay
	ldr	w0, [x26]
	bl	_RREG32
Lloh77:
	adrp	x8, _RADEON_TV_DAC_GDACDET@GOTPAGE
Lloh78:
	ldr	x8, [x8, _RADEON_TV_DAC_GDACDET@GOTPAGEOFF]
Lloh79:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_4
; %bb.3:
Lloh80:
	adrp	x0, l_.str@PAGE
Lloh81:
	add	x0, x0, l_.str@PAGEOFF
	b	LBB0_6
LBB0_4:
Lloh82:
	adrp	x8, _RADEON_TV_DAC_BDACDET@GOTPAGE
Lloh83:
	ldr	x8, [x8, _RADEON_TV_DAC_BDACDET@GOTPAGEOFF]
Lloh84:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_8
; %bb.5:
Lloh85:
	adrp	x0, l_.str.1@PAGE
Lloh86:
	add	x0, x0, l_.str.1@PAGEOFF
LBB0_6:
	bl	_DRM_DEBUG_KMS
	mov	w23, #1
LBB0_7:
	ldr	w0, [x27]
	mov	x1, x22
	bl	_WREG32
	ldr	w0, [x26]
	mov	x1, x21
	bl	_WREG32
	ldr	w0, [x25]
	mov	x1, x20
	bl	_WREG32
	ldr	w0, [x24]
	mov	x1, x19
	bl	_WREG32
	mov	x0, x23
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
LBB0_8:
	mov	w23, #0
	b	LBB0_7
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpAdd	Lloh85, Lloh86
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_DAC_CNTL2,4,2           ; @RADEON_DAC_CNTL2
	.comm	_RADEON_TV_MASTER_CNTL,4,2      ; @RADEON_TV_MASTER_CNTL
	.comm	_RADEON_TV_DAC_CNTL,4,2         ; @RADEON_TV_DAC_CNTL
	.comm	_RADEON_CONFIG_CNTL,4,2         ; @RADEON_CONFIG_CNTL
	.comm	_RADEON_TV_PRE_DAC_MUX_CNTL,4,2 ; @RADEON_TV_PRE_DAC_MUX_CNTL
	.comm	_RADEON_DAC2_DAC2_CLK_SEL,4,2   ; @RADEON_DAC2_DAC2_CLK_SEL
	.comm	_RADEON_TV_ON,4,2               ; @RADEON_TV_ON
	.comm	_RADEON_TV_ASYNC_RST,4,2        ; @RADEON_TV_ASYNC_RST
	.comm	_RADEON_RESTART_PHASE_FIX,4,2   ; @RADEON_RESTART_PHASE_FIX
	.comm	_RADEON_CRT_FIFO_CE_EN,4,2      ; @RADEON_CRT_FIFO_CE_EN
	.comm	_RADEON_TV_FIFO_CE_EN,4,2       ; @RADEON_TV_FIFO_CE_EN
	.comm	_RADEON_RE_SYNC_NOW_SEL_MASK,4,2 ; @RADEON_RE_SYNC_NOW_SEL_MASK
	.comm	_RADEON_TV_FIFO_ASYNC_RST,4,2   ; @RADEON_TV_FIFO_ASYNC_RST
	.comm	_RADEON_CRT_ASYNC_RST,4,2       ; @RADEON_CRT_ASYNC_RST
	.comm	_RADEON_TV_DAC_NBLANK,4,2       ; @RADEON_TV_DAC_NBLANK
	.comm	_RADEON_TV_DAC_NHOLD,4,2        ; @RADEON_TV_DAC_NHOLD
	.comm	_RADEON_TV_MONITOR_DETECT_EN,4,2 ; @RADEON_TV_MONITOR_DETECT_EN
	.comm	_RADEON_TV_DAC_STD_NTSC,4,2     ; @RADEON_TV_DAC_STD_NTSC
	.comm	_RADEON_TV_DAC_BGADJ_SHIFT,4,2  ; @RADEON_TV_DAC_BGADJ_SHIFT
	.comm	_RADEON_CFG_ATI_REV_ID_MASK,4,2 ; @RADEON_CFG_ATI_REV_ID_MASK
	.comm	_RADEON_TV_DAC_DACADJ_SHIFT,4,2 ; @RADEON_TV_DAC_DACADJ_SHIFT
	.comm	_RADEON_C_GRN_EN,4,2            ; @RADEON_C_GRN_EN
	.comm	_RADEON_CMP_BLU_EN,4,2          ; @RADEON_CMP_BLU_EN
	.comm	_RADEON_RED_MX_FORCE_DAC_DATA,4,2 ; @RADEON_RED_MX_FORCE_DAC_DATA
	.comm	_RADEON_GRN_MX_FORCE_DAC_DATA,4,2 ; @RADEON_GRN_MX_FORCE_DAC_DATA
	.comm	_RADEON_BLU_MX_FORCE_DAC_DATA,4,2 ; @RADEON_BLU_MX_FORCE_DAC_DATA
	.comm	_RADEON_TV_FORCE_DAC_DATA_SHIFT,4,2 ; @RADEON_TV_FORCE_DAC_DATA_SHIFT
	.comm	_RADEON_TV_DAC_GDACDET,4,2      ; @RADEON_TV_DAC_GDACDET
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"S-video TV connection detected\n"

	.comm	_RADEON_TV_DAC_BDACDET,4,2      ; @RADEON_TV_DAC_BDACDET
l_.str.1:                               ; @.str.1
	.asciz	"Composite TV connection detected\n"

	.no_dead_strip	_radeon_legacy_tv_detect
.subsections_via_symbols
