	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vi_get_xclk
_vi_get_xclk:                           ## @vi_get_xclk
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movl	4(%rdi), %ebx
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rdi)
	je	LBB0_2
LBB0_5:
	movl	%ebx, %eax
	jmp	LBB0_6
LBB0_2:
	movq	_ixCG_CLKPIN_CNTL_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_SMC
	movq	_CG_CLKPIN_CNTL_2@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_MUX_TCLK_TO_XCLK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	callq	_REG_GET_FIELD
	movq	%rax, %rcx
	movl	$1000, %eax                     ## imm = 0x3E8
	testq	%rcx, %rcx
	jne	LBB0_6
## %bb.3:
	movq	_ixCG_CLKPIN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_SMC
	movq	_CG_CLKPIN_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_XTALIN_DIVIDE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	callq	_REG_GET_FIELD
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	leal	3(%rbx), %eax
	testl	%ebx, %ebx
	cmovnsl	%ebx, %eax
	sarl	$2, %eax
LBB0_6:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_ixCG_CLKPIN_CNTL_2,4,2         ## @ixCG_CLKPIN_CNTL_2
	.comm	_CG_CLKPIN_CNTL_2,4,2           ## @CG_CLKPIN_CNTL_2
	.comm	_MUX_TCLK_TO_XCLK,4,2           ## @MUX_TCLK_TO_XCLK
	.comm	_ixCG_CLKPIN_CNTL,4,2           ## @ixCG_CLKPIN_CNTL
	.comm	_CG_CLKPIN_CNTL,4,2             ## @CG_CLKPIN_CNTL
	.comm	_XTALIN_DIVIDE,4,2              ## @XTALIN_DIVIDE
	.no_dead_strip	_vi_get_xclk
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vi_get_xclk
_vi_get_xclk:                           ; @vi_get_xclk
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldp	w8, w19, [x0]
Lloh0:
	adrp	x9, _AMD_IS_APU@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_IS_APU@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_5
; %bb.1:
Lloh3:
	adrp	x8, _ixCG_CLKPIN_CNTL_2@GOTPAGE
Lloh4:
	ldr	x8, [x8, _ixCG_CLKPIN_CNTL_2@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	bl	_RREG32_SMC
Lloh6:
	adrp	x8, _CG_CLKPIN_CNTL_2@GOTPAGE
Lloh7:
	ldr	x8, [x8, _CG_CLKPIN_CNTL_2@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
Lloh9:
	adrp	x8, _MUX_TCLK_TO_XCLK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _MUX_TCLK_TO_XCLK@GOTPAGEOFF]
Lloh11:
	ldr	w2, [x8]
	bl	_REG_GET_FIELD
	cbz	x0, LBB0_3
; %bb.2:
	mov	w19, #1000
	b	LBB0_5
LBB0_3:
Lloh12:
	adrp	x8, _ixCG_CLKPIN_CNTL@GOTPAGE
Lloh13:
	ldr	x8, [x8, _ixCG_CLKPIN_CNTL@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	bl	_RREG32_SMC
Lloh15:
	adrp	x8, _CG_CLKPIN_CNTL@GOTPAGE
Lloh16:
	ldr	x8, [x8, _CG_CLKPIN_CNTL@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
Lloh18:
	adrp	x8, _XTALIN_DIVIDE@GOTPAGE
Lloh19:
	ldr	x8, [x8, _XTALIN_DIVIDE@GOTPAGEOFF]
Lloh20:
	ldr	w2, [x8]
	bl	_REG_GET_FIELD
	cbz	x0, LBB0_5
; %bb.4:
	add	w8, w19, #3
	cmp	w19, #0
	csel	w8, w8, w19, lt
	asr	w19, w8, #2
LBB0_5:
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_ixCG_CLKPIN_CNTL_2,4,2         ; @ixCG_CLKPIN_CNTL_2
	.comm	_CG_CLKPIN_CNTL_2,4,2           ; @CG_CLKPIN_CNTL_2
	.comm	_MUX_TCLK_TO_XCLK,4,2           ; @MUX_TCLK_TO_XCLK
	.comm	_ixCG_CLKPIN_CNTL,4,2           ; @ixCG_CLKPIN_CNTL
	.comm	_CG_CLKPIN_CNTL,4,2             ; @CG_CLKPIN_CNTL
	.comm	_XTALIN_DIVIDE,4,2              ; @XTALIN_DIVIDE
	.no_dead_strip	_vi_get_xclk
.subsections_via_symbols
