	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_compute_pll_avivo       ## -- Begin function radeon_compute_pll_avivo
	.p2align	4, 0x90
_radeon_compute_pll_avivo:              ## @radeon_compute_pll_avivo
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$104, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, -104(%rbp)                ## 8-byte Spill
	movl	%esi, %r13d
	movl	(%rdi), %r10d
	movq	_RADEON_PLL_USE_FRAC_FB_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r10d, %eax
	movslq	%esi, %rdx
	imulq	$1717986919, %rdx, %r15         ## imm = 0x66666667
	movq	%r15, %rdx
	shrq	$63, %rdx
	sarq	$34, %r15
	addl	%edx, %r15d
	movl	8(%rdi), %esi
	movq	_RADEON_PLL_USE_REF_DIV@GOTPCREL(%rip), %rdx
	xorl	%ebx, %ebx
	movl	(%rdx), %edx
	andl	%r10d, %edx
	sete	%bl
	movl	12(%rdi,%rbx,4), %ebx
	testl	%eax, %eax
	leal	(%rsi,%rsi), %eax
	leal	(%rax,%rax,4), %eax
	cmovel	%esi, %eax
	movl	%eax, -84(%rbp)                 ## 4-byte Spill
	movl	4(%rdi), %eax
	leal	(%rax,%rax), %esi
	leal	(%rsi,%rsi,4), %esi
	cmovel	%eax, %esi
	movl	%esi, -52(%rbp)                 ## 4-byte Spill
	cmovnel	%r13d, %r15d
	movq	%rdi, -72(%rbp)                 ## 8-byte Spill
	movq	%r8, -128(%rbp)                 ## 8-byte Spill
	je	LBB0_3
## %bb.1:
	testl	%edx, %edx
	je	LBB0_3
## %bb.2:
	movl	12(%rdi), %eax
	jmp	LBB0_5
LBB0_3:
	movq	_RADEON_PLL_PREFER_MINM_OVER_MAXP@GOTPCREL(%rip), %rdx
	movl	20(%rdi), %eax
	testl	%r10d, (%rdx)
	je	LBB0_5
## %bb.4:
	movl	%eax, %edi
	movl	$7, %esi
	movq	%r9, %r14
	movq	%rcx, %r12
	callq	_min
	movq	%r12, %rcx
	movq	%r14, %r9
	movq	-72(%rbp), %rdi                 ## 8-byte Reload
	movl	(%rdi), %r10d
LBB0_5:
	movq	_RADEON_PLL_USE_POST_DIV@GOTPCREL(%rip), %rdx
	testl	%r10d, (%rdx)
	movl	%r13d, -92(%rbp)                ## 4-byte Spill
	movq	%rcx, -120(%rbp)                ## 8-byte Spill
	movq	%r9, -112(%rbp)                 ## 8-byte Spill
	movl	%ebx, -88(%rbp)                 ## 4-byte Spill
	movl	%eax, -76(%rbp)                 ## 4-byte Spill
	je	LBB0_7
## %bb.6:
	movl	24(%rdi), %r13d
	movl	%r13d, %r14d
	jmp	LBB0_8
LBB0_7:
	movq	_RADEON_PLL_IS_LCD@GOTPCREL(%rip), %rcx
	xorl	%edx, %edx
	testl	%r10d, (%rcx)
	sete	%dl
	movl	28(%rdi,%rdx,8), %ebx
	movl	32(%rdi,%rdx,8), %edx
	leal	(%rbx,%rbx), %r8d
	leal	(%rdx,%rdx), %esi
	movq	_RADEON_PLL_USE_FRAC_FB_DIV@GOTPCREL(%rip), %rcx
	testl	%r10d, (%rcx)
	leal	(%r8,%r8,4), %ecx
	leal	(%rsi,%rsi,4), %esi
	cmovel	%ebx, %ecx
	cmovel	%edx, %esi
	movl	%ecx, %eax
	xorl	%edx, %edx
	divl	%r15d
	movl	%eax, %r13d
	imull	%r15d, %eax
	cmpl	%ecx, %eax
	adcl	$0, %r13d
	movl	44(%rdi), %eax
	cmpl	%eax, %r13d
	cmovbel	%eax, %r13d
	movl	48(%rdi), %ecx
	movl	%esi, %eax
	xorl	%edx, %edx
	divl	%r15d
	movl	%eax, %r14d
	imull	%r15d, %eax
	cmpl	%eax, %esi
	sbbl	$0, %r14d
	cmpl	%ecx, %r14d
	cmovael	%ecx, %r14d
LBB0_8:
	movl	%r15d, -60(%rbp)
	movl	52(%rdi), %eax
	movl	%eax, -56(%rbp)
	leaq	-60(%rbp), %rdi
	leaq	-56(%rbp), %rsi
	movl	-52(%rbp), %edx                 ## 4-byte Reload
	movl	%r13d, %ecx
	callq	_avivo_reduce_ratio
	movq	_RADEON_PLL_PREFER_MINM_OVER_MAXP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	-72(%rbp), %rcx                 ## 8-byte Reload
	testl	%eax, (%rcx)
	movl	%r13d, %eax
	cmovel	%r14d, %eax
	movl	%eax, -80(%rbp)                 ## 4-byte Spill
	cmpl	%r14d, %r13d
	jbe	LBB0_10
## %bb.9:
	movl	-76(%rbp), %r8d                 ## 4-byte Reload
LBB0_16:
	movl	-60(%rbp), %edi
	movl	-56(%rbp), %esi
	leaq	-48(%rbp), %r14
	movq	%r14, (%rsp)
	leaq	-44(%rbp), %r12
	movl	-80(%rbp), %r15d                ## 4-byte Reload
	movl	%r15d, %edx
	movl	-84(%rbp), %ecx                 ## 4-byte Reload
	movq	%r12, %r9
	callq	_avivo_get_fb_ref_div
	movq	%r12, %rdi
	movq	%r14, %rsi
	movl	-52(%rbp), %edx                 ## 4-byte Reload
	movl	-88(%rbp), %ecx                 ## 4-byte Reload
	callq	_avivo_reduce_ratio
	movq	_RADEON_PLL_USE_FRAC_FB_DIV@GOTPCREL(%rip), %r14
	movl	(%r14), %eax
	movq	-72(%rbp), %rbx                 ## 8-byte Reload
	testl	%eax, (%rbx)
	je	LBB0_20
## %bb.17:
	movl	-44(%rbp), %eax
	movl	$3435973837, %ecx               ## imm = 0xCCCCCCCD
	imulq	%rax, %rcx
	shrq	$35, %rcx
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	je	LBB0_20
## %bb.18:
	movl	$9, %ecx
	subl	%eax, %ecx
	leal	(%rcx,%rcx,4), %eax
	leal	50(,%rax,4), %esi
	movl	-52(%rbp), %edi                 ## 4-byte Reload
	callq	_max
	movq	-72(%rbp), %rbx                 ## 8-byte Reload
	movl	-44(%rbp), %esi
	cmpl	%eax, %esi
	jae	LBB0_20
## %bb.19:
	movl	%eax, %edi
	callq	_DIV_ROUND_UP
	movq	-72(%rbp), %rbx                 ## 8-byte Reload
	movl	-44(%rbp), %ecx
	imull	%eax, %ecx
	movl	%ecx, -44(%rbp)
	imull	-48(%rbp), %eax
	movl	%eax, -48(%rbp)
LBB0_20:
	movq	16(%rbp), %r8
	movl	(%r14), %edx
	movl	-44(%rbp), %eax
	testl	%edx, (%rbx)
	movl	-92(%rbp), %esi                 ## 4-byte Reload
	movq	-128(%rbp), %r11                ## 8-byte Reload
	movq	-120(%rbp), %rcx                ## 8-byte Reload
	movq	-112(%rbp), %r10                ## 8-byte Reload
	je	LBB0_22
## %bb.21:
	movl	%eax, %edx
	movl	$3435973837, %edi               ## imm = 0xCCCCCCCD
	imulq	%rdx, %rdi
	shrq	$35, %rdi
	movl	%edi, (%rcx)
	addl	%edi, %edi
	leal	(%rdi,%rdi,4), %edx
	subl	%edx, %eax
	jmp	LBB0_23
LBB0_10:
	movl	$-1, %r12d
	movl	-76(%rbp), %r8d                 ## 4-byte Reload
	jmp	LBB0_11
	.p2align	4, 0x90
LBB0_14:                                ##   in Loop: Header=BB0_11 Depth=1
	movl	%r13d, -80(%rbp)                ## 4-byte Spill
	movl	%eax, %r12d
LBB0_15:                                ##   in Loop: Header=BB0_11 Depth=1
	incl	%r13d
	cmpl	%r14d, %r13d
	movl	%ebx, %r8d
	ja	LBB0_16
LBB0_11:                                ## =>This Inner Loop Header: Depth=1
	movl	-60(%rbp), %edi
	movl	-56(%rbp), %esi
	leaq	-48(%rbp), %rax
	movq	%rax, (%rsp)
	movl	%r13d, %edx
	movl	-84(%rbp), %ecx                 ## 4-byte Reload
	movl	%r8d, %ebx
	leaq	-44(%rbp), %r9
	callq	_avivo_get_fb_ref_div
	movl	-44(%rbp), %eax
	movq	-72(%rbp), %rsi                 ## 8-byte Reload
	imull	52(%rsi), %eax
	movl	-48(%rbp), %ecx
	imull	%r13d, %ecx
	xorl	%edx, %edx
	divl	%ecx
	movl	%r15d, %ecx
	subl	%eax, %ecx
	movl	%ecx, %eax
	negl	%eax
	cmovsl	%ecx, %eax
	cmpl	%r12d, %eax
	jb	LBB0_14
## %bb.12:                              ##   in Loop: Header=BB0_11 Depth=1
	jne	LBB0_15
## %bb.13:                              ##   in Loop: Header=BB0_11 Depth=1
	movq	_RADEON_PLL_PREFER_MINM_OVER_MAXP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, (%rsi)
	jne	LBB0_15
	jmp	LBB0_14
LBB0_22:
	movl	%eax, (%rcx)
	xorl	%eax, %eax
LBB0_23:
	movl	%eax, (%r11)
	movl	(%rcx), %edx
	leal	(%rdx,%rdx,4), %edx
	leal	(%rax,%rdx,2), %eax
	imull	52(%rbx), %eax
	movl	-48(%rbp), %r9d
	movl	%r15d, %edx
	imull	%r9d, %edx
	addl	%edx, %edx
	leal	(%rdx,%rdx,4), %edi
	xorl	%edx, %edx
	divl	%edi
	movq	-104(%rbp), %rdx                ## 8-byte Reload
	movl	%eax, (%rdx)
	movl	%r9d, (%r10)
	movl	%r15d, (%r8)
	movl	(%rdx), %eax
	addl	%eax, %eax
	leal	(%rax,%rax,4), %edx
	movl	(%rcx), %ecx
	movl	(%r11), %r8d
	movl	%r15d, (%rsp)
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	addq	$104, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_PLL_USE_FRAC_FB_DIV,4,2 ## @RADEON_PLL_USE_FRAC_FB_DIV
	.comm	_RADEON_PLL_USE_REF_DIV,4,2     ## @RADEON_PLL_USE_REF_DIV
	.comm	_RADEON_PLL_PREFER_MINM_OVER_MAXP,4,2 ## @RADEON_PLL_PREFER_MINM_OVER_MAXP
	.comm	_RADEON_PLL_USE_POST_DIV,4,2    ## @RADEON_PLL_USE_POST_DIV
	.comm	_RADEON_PLL_IS_LCD,4,2          ## @RADEON_PLL_IS_LCD
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_compute_pll_avivo       ; -- Begin function radeon_compute_pll_avivo
	.p2align	2
_radeon_compute_pll_avivo:              ; @radeon_compute_pll_avivo
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #160
	.cfi_def_cfa_offset 160
	stp	x28, x27, [sp, #64]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #80]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #96]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #112]            ; 16-byte Folded Spill
	stp	x20, x19, [sp, #128]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #144]            ; 16-byte Folded Spill
	add	x29, sp, #144
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	stp	x5, x6, [sp, #8]                ; 16-byte Folded Spill
	stp	x3, x4, [sp, #24]               ; 16-byte Folded Spill
	str	x2, [sp]                        ; 8-byte Folded Spill
	mov	x25, x0
Lloh0:
	adrp	x19, _RADEON_PLL_USE_FRAC_FB_DIV@GOTPAGE
Lloh1:
	ldr	x19, [x19, _RADEON_PLL_USE_FRAC_FB_DIV@GOTPAGEOFF]
	ldr	w9, [x19]
	mov	w8, #26215
	movk	w8, #26214, lsl #16
	smull	x8, w1, w8
	lsr	x10, x8, #63
	asr	x8, x8, #34
	add	w10, w8, w10
	ldp	w8, w11, [x0]
	ands	w9, w9, w8
	str	w1, [sp, #40]                   ; 4-byte Folded Spill
	csel	w24, w10, w1, eq
	ldr	w10, [x0, #8]
	add	w12, w11, w11, lsl #2
	lsl	w12, w12, #1
	add	w13, w10, w10, lsl #2
	lsl	w13, w13, #1
	csel	w27, w10, w13, eq
Lloh2:
	adrp	x10, _RADEON_PLL_USE_REF_DIV@GOTPAGE
Lloh3:
	ldr	x10, [x10, _RADEON_PLL_USE_REF_DIV@GOTPAGEOFF]
	csel	w26, w11, w12, eq
Lloh4:
	ldr	w10, [x10]
	ands	w10, w10, w8
	mov	w11, #12
	mov	w12, #16
	csel	x11, x12, x11, eq
	ldr	w20, [x0, x11]
	cmp	w9, #0
	ccmp	w10, #0, #4, ne
Lloh5:
	adrp	x28, _RADEON_PLL_PREFER_MINM_OVER_MAXP@GOTPAGE
Lloh6:
	ldr	x28, [x28, _RADEON_PLL_PREFER_MINM_OVER_MAXP@GOTPAGEOFF]
	b.ne	LBB0_3
; %bb.1:
	ldr	w9, [x28]
	ldr	w23, [x25, #20]
	tst	w9, w8
	b.eq	LBB0_4
; %bb.2:
	mov	x0, x23
	mov	w1, #7
	bl	_min
	mov	x23, x0
	ldr	w8, [x25]
	b	LBB0_4
LBB0_3:
	ldr	w23, [x25, #12]
LBB0_4:
Lloh7:
	adrp	x9, _RADEON_PLL_USE_POST_DIV@GOTPAGE
Lloh8:
	ldr	x9, [x9, _RADEON_PLL_USE_POST_DIV@GOTPAGEOFF]
Lloh9:
	ldr	w9, [x9]
	tst	w9, w8
	str	w20, [sp, #44]                  ; 4-byte Folded Spill
	b.eq	LBB0_6
; %bb.5:
	ldr	w22, [x25, #24]
	mov	x19, x22
	b	LBB0_7
LBB0_6:
Lloh10:
	adrp	x9, _RADEON_PLL_IS_LCD@GOTPAGE
Lloh11:
	ldr	x9, [x9, _RADEON_PLL_IS_LCD@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
	tst	w9, w8
	mov	w9, #28
	mov	w10, #36
	csel	x9, x10, x9, eq
	mov	w10, #32
	mov	w11, #40
	csel	x10, x11, x10, eq
	ldr	w10, [x25, x10]
	ldr	w9, [x25, x9]
	ldr	w11, [x19]
	add	w12, w9, w9, lsl #2
	lsl	w12, w12, #1
	add	w13, w10, w10, lsl #2
	lsl	w13, w13, #1
	tst	w11, w8
	csel	w8, w9, w12, eq
	csel	w9, w10, w13, eq
	udiv	w10, w8, w24
	mul	w11, w10, w24
	cmp	w11, w8
	cinc	w8, w10, lo
	ldp	w10, w11, [x25, #44]
	cmp	w8, w10
	csel	w22, w8, w10, hi
	udiv	w8, w9, w24
	mul	w10, w8, w24
	cmp	w10, w9
	cset	w9, hi
	sub	w8, w8, w9
	cmp	w8, w11
	csel	w19, w8, w11, lo
LBB0_7:
	ldr	w8, [x25, #52]
	stp	w8, w24, [sp, #48]
	add	x0, sp, #52
	add	x1, sp, #48
	mov	x2, x26
	mov	x3, x22
	bl	_avivo_reduce_ratio
	ldr	w8, [x25]
	ldr	w9, [x28]
	tst	w9, w8
	csel	w20, w19, w22, eq
	cmp	w22, w19
	b.ls	LBB0_14
LBB0_8:
	ldp	w1, w0, [sp, #48]
	add	x5, sp, #60
	add	x6, sp, #56
	mov	x2, x20
	mov	x3, x27
	mov	x4, x23
	bl	_avivo_get_fb_ref_div
	add	x0, sp, #60
	add	x1, sp, #56
	mov	x2, x26
	ldr	w3, [sp, #44]                   ; 4-byte Folded Reload
	bl	_avivo_reduce_ratio
	ldr	w8, [x25]
Lloh13:
	adrp	x19, _RADEON_PLL_USE_FRAC_FB_DIV@GOTPAGE
Lloh14:
	ldr	x19, [x19, _RADEON_PLL_USE_FRAC_FB_DIV@GOTPAGEOFF]
	ldr	w9, [x19]
	tst	w9, w8
	b.eq	LBB0_12
; %bb.9:
	ldr	w8, [sp, #60]
	mov	w9, #52429
	movk	w9, #52428, lsl #16
	mul	x9, x8, x9
	lsr	x9, x9, #35
	mov	w10, #10
	msub	w8, w9, w10, w8
	cbz	w8, LBB0_12
; %bb.10:
	mov	w9, #9
	sub	w8, w9, w8
	mov	w9, #20
	mul	w8, w8, w9
	add	w1, w8, #50
	mov	x0, x26
	bl	_max
	ldr	w1, [sp, #60]
	cmp	w1, w0
	b.hs	LBB0_12
; %bb.11:
	bl	_DIV_ROUND_UP
	ldr	w8, [sp, #60]
	mul	w9, w8, w0
	ldr	w8, [sp, #56]
	mul	w8, w8, w0
	stp	w8, w9, [sp, #56]
LBB0_12:
	ldr	w8, [x25]
	ldr	w10, [x19]
	ldr	w9, [sp, #60]
	tst	w10, w8
	b.eq	LBB0_20
; %bb.13:
	mov	w8, #52429
	movk	w8, #52428, lsl #16
	umull	x8, w9, w8
	lsr	x8, x8, #35
	ldr	x13, [sp, #24]                  ; 8-byte Folded Reload
	str	w8, [x13]
	mov	w10, #10
	msub	w8, w8, w10, w9
	b	LBB0_21
LBB0_14:
	mov	w21, #-1
	b	LBB0_17
LBB0_15:                                ;   in Loop: Header=BB0_17 Depth=1
	mov	x20, x22
	mov	x21, x8
LBB0_16:                                ;   in Loop: Header=BB0_17 Depth=1
	add	w22, w22, #1
	cmp	w22, w19
	b.hi	LBB0_8
LBB0_17:                                ; =>This Inner Loop Header: Depth=1
	ldp	w1, w0, [sp, #48]
	add	x5, sp, #60
	add	x6, sp, #56
	mov	x2, x22
	mov	x3, x27
	mov	x4, x23
	bl	_avivo_get_fb_ref_div
	ldr	w8, [x25, #52]
	ldr	w9, [sp, #60]
	mul	w8, w9, w8
	ldr	w9, [sp, #56]
	mul	w9, w9, w22
	udiv	w8, w8, w9
	sub	w8, w24, w8
	cmp	w8, #0
	cneg	w8, w8, mi
	cmp	w8, w21
	b.lo	LBB0_15
; %bb.18:                               ;   in Loop: Header=BB0_17 Depth=1
	b.ne	LBB0_16
; %bb.19:                               ;   in Loop: Header=BB0_17 Depth=1
	ldr	w9, [x25]
	ldr	w10, [x28]
	tst	w10, w9
	b.ne	LBB0_16
	b	LBB0_15
LBB0_20:
	mov	w8, #0
	ldr	x13, [sp, #24]                  ; 8-byte Folded Reload
	str	w9, [x13]
LBB0_21:
	ldr	w1, [sp, #40]                   ; 4-byte Folded Reload
	ldr	x12, [sp, #32]                  ; 8-byte Folded Reload
	ldp	x15, x14, [sp, #8]              ; 16-byte Folded Reload
	ldr	x16, [sp]                       ; 8-byte Folded Reload
	str	w8, [x12]
	ldr	w9, [x25, #52]
	ldr	w10, [x13]
	mov	w11, #10
	madd	w8, w10, w11, w8
	mul	w8, w8, w9
	ldr	w5, [sp, #56]
	mul	w9, w20, w5
	add	w9, w9, w9, lsl #2
	lsl	w9, w9, #1
	udiv	w8, w8, w9
	str	w8, [x16]
	str	w5, [x15]
	str	w20, [x14]
	ldr	w8, [x16]
	add	w8, w8, w8, lsl #2
	lsl	w2, w8, #1
	ldr	w3, [x13]
	ldr	w4, [x12]
Lloh15:
	adrp	x0, l_.str@PAGE
Lloh16:
	add	x0, x0, l_.str@PAGEOFF
	mov	x6, x20
	bl	_DRM_DEBUG_KMS
	ldp	x29, x30, [sp, #144]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #128]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #112]            ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #96]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #80]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #64]             ; 16-byte Folded Reload
	add	sp, sp, #160
	ret
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpAdd	Lloh15, Lloh16
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_PLL_USE_FRAC_FB_DIV,4,2 ; @RADEON_PLL_USE_FRAC_FB_DIV
	.comm	_RADEON_PLL_USE_REF_DIV,4,2     ; @RADEON_PLL_USE_REF_DIV
	.comm	_RADEON_PLL_PREFER_MINM_OVER_MAXP,4,2 ; @RADEON_PLL_PREFER_MINM_OVER_MAXP
	.comm	_RADEON_PLL_USE_POST_DIV,4,2    ; @RADEON_PLL_USE_POST_DIV
	.comm	_RADEON_PLL_IS_LCD,4,2          ; @RADEON_PLL_IS_LCD
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n"

.subsections_via_symbols
