	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dce12_update_clocks
_dce12_update_clocks:                   ## @dce12_update_clocks
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, -44(%rbp)                 ## 4-byte Spill
	movq	%rsi, %r14
	movq	%rdi, %r13
	callq	_TO_CLK_MGR_INTERNAL
	movq	%rax, %r12
	movl	$0, -48(%rbp)
	movq	$0, -56(%rbp)
	movq	%r14, %rdi
	callq	_dce_get_max_pixel_clock_for_all_paths
	movl	%eax, %r15d
	movl	(%r14), %ebx
	cmpl	$0, 8(%r12)
	jne	LBB0_2
## %bb.1:
	imull	$115, %ebx, %eax
	cltq
	imulq	$1374389535, %rax, %rbx         ## imm = 0x51EB851F
	movq	%rbx, %rax
	shrq	$63, %rax
	sarq	$37, %rbx
	addl	%eax, %ebx
LBB0_2:
	movl	8(%r13), %edx
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	movl	%ebx, %esi
	callq	_should_set_clock
	testq	%rax, %rax
	je	LBB0_6
## %bb.3:
	movq	_DM_PP_CLOCK_TYPE_DISPLAY_CLK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -52(%rbp)
	cmpq	$0, (%r12)
	je	LBB0_5
## %bb.4:
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_dce_adjust_dp_ref_freq_for_ss
	movl	%eax, %ebx
LBB0_5:
	movl	%ebx, -56(%rbp)
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_dce112_set_clock
	movl	%eax, 8(%r13)
	movq	(%r13), %rdi
	leaq	-56(%rbp), %rsi
	callq	_dm_pp_apply_clock_for_voltage_request
LBB0_6:
	movl	12(%r13), %edx
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	movl	%r15d, %esi
	callq	_should_set_clock
	testq	%rax, %rax
	je	LBB0_8
## %bb.7:
	movq	_DM_PP_CLOCK_TYPE_DISPLAYPHYCLK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -52(%rbp)
	movl	%r15d, -56(%rbp)
	movl	%r15d, 12(%r13)
	movq	(%r13), %rdi
	leaq	-56(%rbp), %rsi
	callq	_dm_pp_apply_clock_for_voltage_request
LBB0_8:
	movq	(%r13), %rax
	movl	(%rax), %edi
	movq	%r14, %rsi
	callq	_dce11_pplib_apply_display_requirements
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DM_PP_CLOCK_TYPE_DISPLAY_CLK,4,2 ## @DM_PP_CLOCK_TYPE_DISPLAY_CLK
	.comm	_DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,4,2 ## @DM_PP_CLOCK_TYPE_DISPLAYPHYCLK
	.no_dead_strip	_dce12_update_clocks
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dce12_update_clocks
_dce12_update_clocks:                   ; @dce12_update_clocks
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x21, x2
	mov	x19, x1
	mov	x20, x0
	bl	_TO_CLK_MGR_INTERNAL
	mov	x23, x0
	str	wzr, [sp, #8]
	str	xzr, [sp]
	mov	x0, x19
	bl	_dce_get_max_pixel_clock_for_all_paths
	mov	x22, x0
	ldr	w24, [x19]
	ldr	w8, [x23, #8]
	cbnz	w8, LBB0_2
; %bb.1:
	mov	w8, #115
	mul	w8, w24, w8
	mov	w9, #34079
	movk	w9, #20971, lsl #16
	smull	x8, w8, w9
	lsr	x9, x8, #63
	asr	x8, x8, #37
	add	w24, w8, w9
LBB0_2:
	ldr	w2, [x20, #8]
	mov	x0, x21
	mov	x1, x24
	bl	_should_set_clock
	cbz	x0, LBB0_6
; %bb.3:
Lloh0:
	adrp	x8, _DM_PP_CLOCK_TYPE_DISPLAY_CLK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DM_PP_CLOCK_TYPE_DISPLAY_CLK@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	str	w8, [sp, #4]
	ldr	x8, [x23]
	cbz	x8, LBB0_5
; %bb.4:
	mov	x0, x23
	mov	x1, x24
	bl	_dce_adjust_dp_ref_freq_for_ss
	mov	x24, x0
LBB0_5:
	str	w24, [sp]
	mov	x0, x20
	mov	x1, x24
	bl	_dce112_set_clock
	str	w0, [x20, #8]
	ldr	x0, [x20]
	mov	x1, sp
	bl	_dm_pp_apply_clock_for_voltage_request
LBB0_6:
	ldr	w2, [x20, #12]
	mov	x0, x21
	mov	x1, x22
	bl	_should_set_clock
	cbz	x0, LBB0_8
; %bb.7:
Lloh3:
	adrp	x8, _DM_PP_CLOCK_TYPE_DISPLAYPHYCLK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _DM_PP_CLOCK_TYPE_DISPLAYPHYCLK@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	stp	w22, w8, [sp]
	str	w22, [x20, #12]
	ldr	x0, [x20]
	mov	x1, sp
	bl	_dm_pp_apply_clock_for_voltage_request
LBB0_8:
	ldr	x8, [x20]
	ldr	w0, [x8]
	mov	x1, x19
	bl	_dce11_pplib_apply_display_requirements
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_DM_PP_CLOCK_TYPE_DISPLAY_CLK,4,2 ; @DM_PP_CLOCK_TYPE_DISPLAY_CLK
	.comm	_DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,4,2 ; @DM_PP_CLOCK_TYPE_DISPLAYPHYCLK
	.no_dead_strip	_dce12_update_clocks
.subsections_via_symbols
