	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function amdgpu_atombios_crtc_adjust_pll
_amdgpu_atombios_crtc_adjust_pll:       ## @amdgpu_atombios_crtc_adjust_pll
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$136, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %rbx
	callq	_to_amdgpu_crtc
	movq	%rax, %r12
	movq	(%rbx), %rax
	movq	(%rax), %rax
	movq	%rax, -168(%rbp)                ## 8-byte Spill
	movq	48(%r12), %r15
	movq	%r15, %rdi
	callq	_to_amdgpu_encoder
	movq	%rax, %r13
	movq	%r15, %rdi
	callq	_amdgpu_get_connector_for_encoder
	movq	%rax, -80(%rbp)                 ## 8-byte Spill
	movl	(%r14), %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	%r15, %rdi
	callq	_amdgpu_atombios_encoder_get_encoder_mode
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	%r14, -160(%rbp)                ## 8-byte Spill
	movl	(%r14), %r14d
	movl	(%r12), %eax
	movl	%eax, -64(%rbp)                 ## 4-byte Spill
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_amdgpu_dig_monitor_is_duallink
	movq	_AMDGPU_PLL_USE_FRAC_FB_DIV@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	%r12, -56(%rbp)                 ## 8-byte Spill
	movl	%ecx, 8(%r12)
	movq	_ATOM_DEVICE_LCD_SUPPORT@GOTPCREL(%rip), %r12
	movq	_ATOM_DEVICE_DFP_SUPPORT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%r12), %ecx
	movq	%r13, %rbx
	testl	%ecx, (%r13)
	movq	%r15, -152(%rbp)                ## 8-byte Spill
	movl	%eax, -60(%rbp)                 ## 4-byte Spill
	je	LBB0_1
## %bb.3:
	movl	%r14d, %r13d
	movq	-80(%rbp), %rdi                 ## 8-byte Reload
	testq	%rdi, %rdi
	movq	-56(%rbp), %r15                 ## 8-byte Reload
	jne	LBB0_4
	jmp	LBB0_5
LBB0_1:
	movq	%r15, %rdi
	callq	_amdgpu_encoder_get_dp_bridge_encoder_id
	movq	_ENCODER_OBJECT_ID_NONE@GOTPCREL(%rip), %rcx
	movl	%r14d, %r13d
	cmpq	(%rcx), %rax
	movq	-56(%rbp), %r15                 ## 8-byte Reload
	movq	-80(%rbp), %rdi                 ## 8-byte Reload
	je	LBB0_5
## %bb.2:
	movl	%r14d, %r13d
	testq	%rdi, %rdi
	je	LBB0_5
LBB0_4:
	callq	_to_amdgpu_connector
	movq	(%rax), %rax
	movl	(%rax), %r13d
LBB0_5:
	movl	(%r12), %eax
	andl	(%rbx), %eax
	je	LBB0_9
## %bb.6:
	cmpq	$0, 40(%r15)
	je	LBB0_9
## %bb.7:
	movq	32(%r15), %rcx
	testq	%rcx, %rcx
	je	LBB0_9
## %bb.8:
	movq	_AMDGPU_PLL_USE_REF_DIV@GOTPCREL(%rip), %rdx
	movl	8(%r15), %esi
	orl	(%rdx), %esi
	movq	%rcx, 16(%r15)
	movq	_AMDGPU_PLL_USE_FRAC_FB_DIV@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movl	%esi, 8(%r15)
LBB0_9:
	movq	8(%rbx), %rcx
	movq	_ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	movq	-168(%rbp), %r12                ## 8-byte Reload
	jne	LBB0_11
## %bb.10:
	movq	-160(%rbp), %rcx                ## 8-byte Reload
	movl	(%rcx), %ecx
	addl	%ecx, %ecx
	movl	%ecx, -44(%rbp)                 ## 4-byte Spill
LBB0_11:
	movq	_ATOM_DEVICE_TV_SUPPORT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, 16(%rbx)
	je	LBB0_13
## %bb.12:
	movq	_AMDGPU_PLL_PREFER_CLOSEST_LOWER@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	%ecx, 8(%r15)
LBB0_13:
	testl	%eax, %eax
	je	LBB0_15
## %bb.14:
	movq	_AMDGPU_PLL_IS_LCD@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, 8(%r15)
LBB0_15:
	movq	_ATOM_ENCODER_MODE_HDMI@GOTPCREL(%rip), %rax
	movl	-48(%rbp), %ecx                 ## 4-byte Reload
	cmpl	(%rax), %ecx
	jne	LBB0_22
## %bb.16:
	movl	-64(%rbp), %eax                 ## 4-byte Reload
	cmpl	$16, %eax
	je	LBB0_21
## %bb.17:
	cmpl	$12, %eax
	je	LBB0_20
## %bb.18:
	cmpl	$10, %eax
	jne	LBB0_22
## %bb.19:
	leal	(%r14,%r14,4), %eax
	leal	(%r14,%r14,4), %r14d
	addl	$3, %r14d
	testl	%eax, %eax
	cmovnsl	%eax, %r14d
	sarl	$2, %r14d
	jmp	LBB0_22
LBB0_21:
	addl	%r14d, %r14d
	jmp	LBB0_22
LBB0_20:
	leal	(%r14,%r14,2), %eax
	movl	%eax, %r14d
	shrl	$31, %r14d
	addl	%eax, %r14d
	sarl	%r14d
LBB0_22:
	movq	_COMMAND@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_AdjustDisplayPll@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_GetIndexIntoMasterTable
	movl	(%r12), %edi
	leaq	-72(%rbp), %rdx
	leaq	-68(%rbp), %rcx
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	movl	%eax, %esi
	callq	_amdgpu_atom_parse_cmd_header
	testl	%eax, %eax
	je	LBB0_51
## %bb.23:
	leaq	-144(%rbp), %rdi
	xorl	%esi, %esi
	movl	$64, %edx
	callq	_memset
	movl	-72(%rbp), %esi
	movl	-68(%rbp), %edx
	cmpl	$1, %esi
	jne	LBB0_49
## %bb.24:
	leal	-1(%rdx), %eax
	cmpl	$2, %eax
	jae	LBB0_25
## %bb.31:
	movslq	%r14d, %rax
	imulq	$1717986919, %rax, %rdi         ## imm = 0x66666667
	movq	%rdi, %rax
	shrq	$63, %rax
	sarq	$34, %rdi
	addl	%eax, %edi
                                        ## kill: def $edi killed $edi killed $rdi
	callq	_cpu_to_le16
	movq	%rax, -128(%rbp)
	movq	8(%rbx), %rax
	movq	%rax, -144(%rbp)
	movl	-48(%rbp), %eax                 ## 4-byte Reload
	movl	%eax, -136(%rbp)
	cmpq	$0, 40(%r15)
	je	LBB0_34
## %bb.32:
	cmpl	$0, 24(%r15)
	je	LBB0_34
## %bb.33:
	movq	_ADJUST_DISPLAY_CONFIG_SS_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, -120(%rbp)
LBB0_34:
	movl	(%r12), %edi
	leaq	-144(%rbp), %rdx
	movl	-56(%rbp), %esi                 ## 4-byte Reload
	callq	_amdgpu_atom_execute_table
	movq	-128(%rbp), %rdi
	callq	_le16_to_cpu
                                        ## kill: def $eax killed $eax def $rax
	jmp	LBB0_47
LBB0_49:
	leaq	L_.str(%rip), %rdi
	jmp	LBB0_50
LBB0_25:
	cmpl	$3, %edx
	jne	LBB0_48
## %bb.26:
	movslq	%r14d, %rax
	imulq	$1717986919, %rax, %rdi         ## imm = 0x66666667
	movq	%rdi, %rax
	shrq	$63, %rax
	sarq	$34, %rdi
	addl	%eax, %edi
                                        ## kill: def $edi killed $edi killed $rdi
	callq	_cpu_to_le16
	movq	%rax, -88(%rbp)
	movq	8(%rbx), %rax
	movq	%rax, -120(%rbp)
	movl	-48(%rbp), %eax                 ## 4-byte Reload
	movl	%eax, -112(%rbp)
	movl	$0, -96(%rbp)
	cmpq	$0, 40(%r15)
	je	LBB0_29
## %bb.27:
	cmpl	$0, 24(%r15)
	je	LBB0_29
## %bb.28:
	movq	_DISPPLL_CONFIG_SS_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -96(%rbp)
LBB0_29:
	movl	-48(%rbp), %edi                 ## 4-byte Reload
	callq	_ENCODER_MODE_IS_DP
	testl	%eax, %eax
	movq	-152(%rbp), %r14                ## 8-byte Reload
	je	LBB0_35
## %bb.30:
	movq	_DISPPLL_CONFIG_COHERENT_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, -96(%rbp)
	movslq	%r13d, %rax
	imulq	$1717986919, %rax, %rdi         ## imm = 0x66666667
	movq	%rdi, %rax
	shrq	$63, %rax
	sarq	$34, %rdi
	addl	%eax, %edi
                                        ## kill: def $edi killed $edi killed $rdi
	callq	_cpu_to_le16
	movq	%rax, -88(%rbp)
	jmp	LBB0_40
LBB0_48:
	leaq	L_.str(%rip), %rdi
	movl	$1, %esi
LBB0_50:
                                        ## kill: def $edx killed $edx killed $rdx
	callq	_DRM_ERROR
LBB0_51:
	movl	-44(%rbp), %eax                 ## 4-byte Reload
	jmp	LBB0_52
LBB0_35:
	movq	_ATOM_DEVICE_DFP_SUPPORT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rbx)
	je	LBB0_40
## %bb.36:
	movq	24(%rbx), %rax
	cmpl	$0, (%rax)
	je	LBB0_38
## %bb.37:
	movq	_DISPPLL_CONFIG_COHERENT_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, -96(%rbp)
LBB0_38:
	cmpl	$0, -60(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_40
## %bb.39:
	movq	_DISPPLL_CONFIG_DUAL_LINK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, -96(%rbp)
LBB0_40:
	movq	%r14, %rdi
	callq	_amdgpu_encoder_get_dp_bridge_encoder_id
	movq	_ENCODER_OBJECT_ID_NONE@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_42
## %bb.41:
	xorl	%eax, %eax
	jmp	LBB0_43
LBB0_42:
	movq	%r14, %rdi
	callq	_amdgpu_encoder_get_dp_bridge_encoder_id
LBB0_43:
	movq	%rax, -104(%rbp)
	movl	(%r12), %edi
	leaq	-144(%rbp), %rdx
	movl	-56(%rbp), %esi                 ## 4-byte Reload
	callq	_amdgpu_atom_execute_table
	movl	-128(%rbp), %edi
	callq	_le32_to_cpu
                                        ## kill: def $eax killed $eax def $rax
	cmpq	$0, -136(%rbp)
	je	LBB0_45
## %bb.44:
	movl	8(%r15), %ecx
	movq	_AMDGPU_PLL_USE_FRAC_FB_DIV@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_AMDGPU_PLL_USE_REF_DIV@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movl	%ecx, 8(%r15)
	movq	-136(%rbp), %rcx
	movq	%rcx, 16(%r15)
LBB0_45:
	movl	-144(%rbp), %ecx
	testl	%ecx, %ecx
	je	LBB0_47
## %bb.46:
	movl	8(%r15), %edx
	movq	_AMDGPU_PLL_USE_FRAC_FB_DIV@GOTPCREL(%rip), %rsi
	orl	(%rsi), %edx
	movq	_AMDGPU_PLL_USE_POST_DIV@GOTPCREL(%rip), %rsi
	orl	(%rsi), %edx
	movl	%edx, 8(%r15)
	movl	%ecx, 4(%r15)
LBB0_47:
	addl	%eax, %eax
	leal	(%rax,%rax,4), %eax
LBB0_52:
	addq	$136, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_PLL_USE_FRAC_FB_DIV,4,2 ## @AMDGPU_PLL_USE_FRAC_FB_DIV
	.comm	_ATOM_DEVICE_LCD_SUPPORT,4,2    ## @ATOM_DEVICE_LCD_SUPPORT
	.comm	_ATOM_DEVICE_DFP_SUPPORT,4,2    ## @ATOM_DEVICE_DFP_SUPPORT
	.comm	_ENCODER_OBJECT_ID_NONE,8,3     ## @ENCODER_OBJECT_ID_NONE
	.comm	_AMDGPU_PLL_USE_REF_DIV,4,2     ## @AMDGPU_PLL_USE_REF_DIV
	.comm	_ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1,8,3 ## @ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
	.comm	_ATOM_DEVICE_TV_SUPPORT,4,2     ## @ATOM_DEVICE_TV_SUPPORT
	.comm	_AMDGPU_PLL_PREFER_CLOSEST_LOWER,4,2 ## @AMDGPU_PLL_PREFER_CLOSEST_LOWER
	.comm	_AMDGPU_PLL_IS_LCD,4,2          ## @AMDGPU_PLL_IS_LCD
	.comm	_ATOM_ENCODER_MODE_HDMI,4,2     ## @ATOM_ENCODER_MODE_HDMI
	.comm	_COMMAND,4,2                    ## @COMMAND
	.comm	_AdjustDisplayPll,4,2           ## @AdjustDisplayPll
	.comm	_ADJUST_DISPLAY_CONFIG_SS_ENABLE,4,2 ## @ADJUST_DISPLAY_CONFIG_SS_ENABLE
	.comm	_DISPPLL_CONFIG_SS_ENABLE,4,2   ## @DISPPLL_CONFIG_SS_ENABLE
	.comm	_DISPPLL_CONFIG_COHERENT_MODE,4,2 ## @DISPPLL_CONFIG_COHERENT_MODE
	.comm	_DISPPLL_CONFIG_DUAL_LINK,4,2   ## @DISPPLL_CONFIG_DUAL_LINK
	.comm	_AMDGPU_PLL_USE_POST_DIV,4,2    ## @AMDGPU_PLL_USE_POST_DIV
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Unknown table version %d %d\n"

	.no_dead_strip	_amdgpu_atombios_crtc_adjust_pll
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function amdgpu_atombios_crtc_adjust_pll
_amdgpu_atombios_crtc_adjust_pll:       ; @amdgpu_atombios_crtc_adjust_pll
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #192
	.cfi_def_cfa_offset 192
	stp	x28, x27, [sp, #96]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #112]            ; 16-byte Folded Spill
	stp	x24, x23, [sp, #128]            ; 16-byte Folded Spill
	stp	x22, x21, [sp, #144]            ; 16-byte Folded Spill
	stp	x20, x19, [sp, #160]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #176]            ; 16-byte Folded Spill
	add	x29, sp, #176
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x26, x1
	mov	x20, x0
	bl	_to_amdgpu_crtc
	mov	x19, x0
	ldr	x8, [x20]
	ldr	x8, [x8]
	str	x8, [sp, #16]                   ; 8-byte Folded Spill
	ldr	x20, [x0, #48]
	mov	x0, x20
	bl	_to_amdgpu_encoder
	mov	x21, x0
	mov	x0, x20
	bl	_amdgpu_get_connector_for_encoder
	mov	x27, x0
	ldr	w24, [x26]
	mov	x0, x20
	bl	_amdgpu_atombios_encoder_get_encoder_mode
	mov	x22, x0
	ldr	w25, [x26]
	str	w25, [sp, #12]                  ; 4-byte Folded Spill
	ldr	w28, [x19]
	mov	x0, x20
	mov	x1, x25
	bl	_amdgpu_dig_monitor_is_duallink
	str	w0, [sp, #8]                    ; 4-byte Folded Spill
Lloh0:
	adrp	x8, _AMDGPU_PLL_USE_FRAC_FB_DIV@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPU_PLL_USE_FRAC_FB_DIV@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	str	w8, [x19, #8]
	ldr	w8, [x21]
Lloh3:
	adrp	x23, _ATOM_DEVICE_LCD_SUPPORT@GOTPAGE
Lloh4:
	ldr	x23, [x23, _ATOM_DEVICE_LCD_SUPPORT@GOTPAGEOFF]
	ldr	w9, [x23]
Lloh5:
	adrp	x10, _ATOM_DEVICE_DFP_SUPPORT@GOTPAGE
Lloh6:
	ldr	x10, [x10, _ATOM_DEVICE_DFP_SUPPORT@GOTPAGEOFF]
Lloh7:
	ldr	w10, [x10]
	orr	w9, w10, w9
	tst	w9, w8
	b.eq	LBB0_20
; %bb.1:
	cbz	x27, LBB0_3
LBB0_2:
	mov	x0, x27
	bl	_to_amdgpu_connector
	ldr	x8, [x0]
	ldr	w8, [x8]
	str	w8, [sp, #12]                   ; 4-byte Folded Spill
LBB0_3:
	ldr	w8, [x21]
	ldr	w9, [x23]
	ands	w8, w9, w8
	b.eq	LBB0_7
; %bb.4:
	ldr	x9, [x19, #40]
	cbz	x9, LBB0_7
; %bb.5:
	ldr	x9, [x19, #32]
	cbz	x9, LBB0_7
; %bb.6:
Lloh8:
	adrp	x10, _AMDGPU_PLL_USE_REF_DIV@GOTPAGE
Lloh9:
	ldr	x10, [x10, _AMDGPU_PLL_USE_REF_DIV@GOTPAGEOFF]
Lloh10:
	ldr	w10, [x10]
	ldr	w11, [x19, #8]
	orr	w10, w11, w10
	str	x9, [x19, #16]
Lloh11:
	adrp	x9, _AMDGPU_PLL_USE_FRAC_FB_DIV@GOTPAGE
Lloh12:
	ldr	x9, [x9, _AMDGPU_PLL_USE_FRAC_FB_DIV@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	orr	w9, w9, w10
	str	w9, [x19, #8]
LBB0_7:
	ldr	x9, [x21, #8]
Lloh14:
	adrp	x10, _ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1@GOTPAGE
Lloh15:
	ldr	x10, [x10, _ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1@GOTPAGEOFF]
Lloh16:
	ldr	x10, [x10]
	cmp	x9, x10
	ldr	x23, [sp, #16]                  ; 8-byte Folded Reload
	b.ne	LBB0_9
; %bb.8:
	ldr	w9, [x26]
	lsl	w24, w9, #1
LBB0_9:
	ldr	w9, [x21, #16]
Lloh17:
	adrp	x10, _ATOM_DEVICE_TV_SUPPORT@GOTPAGE
Lloh18:
	ldr	x10, [x10, _ATOM_DEVICE_TV_SUPPORT@GOTPAGEOFF]
Lloh19:
	ldr	w10, [x10]
	tst	w10, w9
	b.eq	LBB0_11
; %bb.10:
Lloh20:
	adrp	x9, _AMDGPU_PLL_PREFER_CLOSEST_LOWER@GOTPAGE
Lloh21:
	ldr	x9, [x9, _AMDGPU_PLL_PREFER_CLOSEST_LOWER@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	ldr	w10, [x19, #8]
	orr	w9, w10, w9
	str	w9, [x19, #8]
LBB0_11:
	cbz	w8, LBB0_13
; %bb.12:
Lloh23:
	adrp	x8, _AMDGPU_PLL_IS_LCD@GOTPAGE
Lloh24:
	ldr	x8, [x8, _AMDGPU_PLL_IS_LCD@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
	ldr	w9, [x19, #8]
	orr	w8, w9, w8
	str	w8, [x19, #8]
LBB0_13:
Lloh26:
	adrp	x8, _ATOM_ENCODER_MODE_HDMI@GOTPAGE
Lloh27:
	ldr	x8, [x8, _ATOM_ENCODER_MODE_HDMI@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
	lsl	w9, w25, #1
	add	w10, w25, w25, lsl #1
	cmp	w10, #0
	cinc	w10, w10, lt
	asr	w10, w10, #1
	add	w11, w25, w25, lsl #2
	add	w12, w11, #3
	cmp	w11, #0
	csel	w11, w12, w11, lt
	asr	w11, w11, #2
	cmp	w28, #10
	csel	w11, w25, w11, ne
	cmp	w28, #12
	csel	w10, w10, w11, eq
	cmp	w28, #16
	csel	w9, w9, w10, eq
	cmp	w22, w8
	csel	w26, w25, w9, ne
Lloh29:
	adrp	x8, _COMMAND@GOTPAGE
Lloh30:
	ldr	x8, [x8, _COMMAND@GOTPAGEOFF]
Lloh31:
	ldr	w0, [x8]
Lloh32:
	adrp	x8, _AdjustDisplayPll@GOTPAGE
Lloh33:
	ldr	x8, [x8, _AdjustDisplayPll@GOTPAGEOFF]
Lloh34:
	ldr	w1, [x8]
	bl	_GetIndexIntoMasterTable
	mov	x25, x0
	ldr	w0, [x23]
	add	x2, sp, #28
	add	x3, sp, #24
	mov	x1, x25
	bl	_amdgpu_atom_parse_cmd_header
	cbz	w0, LBB0_43
; %bb.14:
	add	x0, sp, #32
	mov	w1, #0
	mov	w2, #64
	bl	_memset
	ldp	w2, w1, [sp, #24]
	cmp	w1, #1
	b.ne	LBB0_21
; %bb.15:
	sub	w8, w2, #1
	cmp	w8, #2
	b.hs	LBB0_22
; %bb.16:
	mov	w8, #26215
	movk	w8, #26214, lsl #16
	smull	x8, w26, w8
	lsr	x9, x8, #63
	asr	x8, x8, #34
	add	w0, w8, w9
	bl	_cpu_to_le16
	str	x0, [sp, #48]
	ldr	x8, [x21, #8]
	str	x8, [sp, #32]
	str	w22, [sp, #40]
	ldr	x8, [x19, #40]
	cbz	x8, LBB0_19
; %bb.17:
	ldr	w8, [x19, #24]
	cbz	w8, LBB0_19
; %bb.18:
Lloh35:
	adrp	x8, _ADJUST_DISPLAY_CONFIG_SS_ENABLE@GOTPAGE
Lloh36:
	ldr	x8, [x8, _ADJUST_DISPLAY_CONFIG_SS_ENABLE@GOTPAGEOFF]
Lloh37:
	ldr	w8, [x8]
	ldr	w9, [sp, #56]
	orr	w8, w9, w8
	str	w8, [sp, #56]
LBB0_19:
	ldr	w0, [x23]
	add	x2, sp, #32
	mov	x1, x25
	bl	_amdgpu_atom_execute_table
	ldr	x0, [sp, #48]
	bl	_le16_to_cpu
	b	LBB0_42
LBB0_20:
	mov	x0, x20
	bl	_amdgpu_encoder_get_dp_bridge_encoder_id
Lloh38:
	adrp	x8, _ENCODER_OBJECT_ID_NONE@GOTPAGE
Lloh39:
	ldr	x8, [x8, _ENCODER_OBJECT_ID_NONE@GOTPAGEOFF]
Lloh40:
	ldr	x8, [x8]
	cmp	x0, x8
	ccmp	x27, #0, #4, ne
	b.ne	LBB0_2
	b	LBB0_3
LBB0_21:
Lloh41:
	adrp	x0, l_.str@PAGE
Lloh42:
	add	x0, x0, l_.str@PAGEOFF
	b	LBB0_29
LBB0_22:
	cmp	w2, #3
	b.ne	LBB0_28
; %bb.23:
	mov	w8, #26215
	movk	w8, #26214, lsl #16
	smull	x8, w26, w8
	lsr	x9, x8, #32
	lsr	x8, x8, #63
	add	w0, w8, w9, asr #2
	bl	_cpu_to_le16
	str	x0, [sp, #88]
	ldr	x8, [x21, #8]
	str	x8, [sp, #56]
	str	w22, [sp, #64]
	str	wzr, [sp, #80]
	ldr	x8, [x19, #40]
	cbz	x8, LBB0_26
; %bb.24:
	ldr	w8, [x19, #24]
	cbz	w8, LBB0_26
; %bb.25:
Lloh43:
	adrp	x8, _DISPPLL_CONFIG_SS_ENABLE@GOTPAGE
Lloh44:
	ldr	x8, [x8, _DISPPLL_CONFIG_SS_ENABLE@GOTPAGEOFF]
Lloh45:
	ldr	w8, [x8]
	str	w8, [sp, #80]
LBB0_26:
	mov	x0, x22
	bl	_ENCODER_MODE_IS_DP
	cbz	w0, LBB0_30
; %bb.27:
Lloh46:
	adrp	x8, _DISPPLL_CONFIG_COHERENT_MODE@GOTPAGE
Lloh47:
	ldr	x8, [x8, _DISPPLL_CONFIG_COHERENT_MODE@GOTPAGEOFF]
Lloh48:
	ldr	w8, [x8]
	ldr	w9, [sp, #80]
	orr	w8, w9, w8
	str	w8, [sp, #80]
	mov	w8, #26215
	movk	w8, #26214, lsl #16
	ldr	w9, [sp, #12]                   ; 4-byte Folded Reload
	smull	x8, w9, w8
	lsr	x9, x8, #63
	asr	x8, x8, #34
	add	w0, w8, w9
	bl	_cpu_to_le16
	str	x0, [sp, #88]
	b	LBB0_35
LBB0_28:
Lloh49:
	adrp	x0, l_.str@PAGE
Lloh50:
	add	x0, x0, l_.str@PAGEOFF
	mov	w1, #1
LBB0_29:
	bl	_DRM_ERROR
	b	LBB0_43
LBB0_30:
	ldr	w8, [x21]
Lloh51:
	adrp	x9, _ATOM_DEVICE_DFP_SUPPORT@GOTPAGE
Lloh52:
	ldr	x9, [x9, _ATOM_DEVICE_DFP_SUPPORT@GOTPAGEOFF]
Lloh53:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_35
; %bb.31:
	ldr	x8, [x21, #24]
	ldr	w8, [x8]
	cbz	w8, LBB0_33
; %bb.32:
Lloh54:
	adrp	x8, _DISPPLL_CONFIG_COHERENT_MODE@GOTPAGE
Lloh55:
	ldr	x8, [x8, _DISPPLL_CONFIG_COHERENT_MODE@GOTPAGEOFF]
Lloh56:
	ldr	w8, [x8]
	ldr	w9, [sp, #80]
	orr	w8, w9, w8
	str	w8, [sp, #80]
LBB0_33:
	ldr	w8, [sp, #8]                    ; 4-byte Folded Reload
	cbz	w8, LBB0_35
; %bb.34:
Lloh57:
	adrp	x8, _DISPPLL_CONFIG_DUAL_LINK@GOTPAGE
Lloh58:
	ldr	x8, [x8, _DISPPLL_CONFIG_DUAL_LINK@GOTPAGEOFF]
Lloh59:
	ldr	w8, [x8]
	ldr	w9, [sp, #80]
	orr	w8, w9, w8
	str	w8, [sp, #80]
LBB0_35:
	mov	x0, x20
	bl	_amdgpu_encoder_get_dp_bridge_encoder_id
Lloh60:
	adrp	x8, _ENCODER_OBJECT_ID_NONE@GOTPAGE
Lloh61:
	ldr	x8, [x8, _ENCODER_OBJECT_ID_NONE@GOTPAGEOFF]
Lloh62:
	ldr	x8, [x8]
	cmp	x0, x8
	b.ne	LBB0_37
; %bb.36:
	mov	x0, #0
	b	LBB0_38
LBB0_37:
	mov	x0, x20
	bl	_amdgpu_encoder_get_dp_bridge_encoder_id
LBB0_38:
	str	x0, [sp, #72]
	ldr	w0, [x23]
	add	x2, sp, #32
	mov	x1, x25
	bl	_amdgpu_atom_execute_table
	ldr	w0, [sp, #48]
	bl	_le32_to_cpu
	ldr	x8, [sp, #40]
	cbz	x8, LBB0_40
; %bb.39:
Lloh63:
	adrp	x8, _AMDGPU_PLL_USE_FRAC_FB_DIV@GOTPAGE
Lloh64:
	ldr	x8, [x8, _AMDGPU_PLL_USE_FRAC_FB_DIV@GOTPAGEOFF]
Lloh65:
	ldr	w8, [x8]
	ldr	w9, [x19, #8]
Lloh66:
	adrp	x10, _AMDGPU_PLL_USE_REF_DIV@GOTPAGE
Lloh67:
	ldr	x10, [x10, _AMDGPU_PLL_USE_REF_DIV@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh68:
	ldr	w9, [x10]
	orr	w8, w9, w8
	str	w8, [x19, #8]
	ldr	x8, [sp, #40]
	str	x8, [x19, #16]
LBB0_40:
	ldr	w8, [sp, #32]
	cbz	w8, LBB0_42
; %bb.41:
Lloh69:
	adrp	x9, _AMDGPU_PLL_USE_FRAC_FB_DIV@GOTPAGE
Lloh70:
	ldr	x9, [x9, _AMDGPU_PLL_USE_FRAC_FB_DIV@GOTPAGEOFF]
Lloh71:
	ldr	w9, [x9]
	ldr	w10, [x19, #8]
	orr	w9, w10, w9
Lloh72:
	adrp	x10, _AMDGPU_PLL_USE_POST_DIV@GOTPAGE
Lloh73:
	ldr	x10, [x10, _AMDGPU_PLL_USE_POST_DIV@GOTPAGEOFF]
Lloh74:
	ldr	w10, [x10]
	orr	w9, w10, w9
	stp	w8, w9, [x19, #4]
LBB0_42:
	add	w8, w0, w0, lsl #2
	lsl	w24, w8, #1
LBB0_43:
	mov	x0, x24
	ldp	x29, x30, [sp, #176]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #160]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #144]            ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #128]            ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #112]            ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #96]             ; 16-byte Folded Reload
	add	sp, sp, #192
	ret
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpAdd	Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpAdd	Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_PLL_USE_FRAC_FB_DIV,4,2 ; @AMDGPU_PLL_USE_FRAC_FB_DIV
	.comm	_ATOM_DEVICE_LCD_SUPPORT,4,2    ; @ATOM_DEVICE_LCD_SUPPORT
	.comm	_ATOM_DEVICE_DFP_SUPPORT,4,2    ; @ATOM_DEVICE_DFP_SUPPORT
	.comm	_ENCODER_OBJECT_ID_NONE,8,3     ; @ENCODER_OBJECT_ID_NONE
	.comm	_AMDGPU_PLL_USE_REF_DIV,4,2     ; @AMDGPU_PLL_USE_REF_DIV
	.comm	_ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1,8,3 ; @ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
	.comm	_ATOM_DEVICE_TV_SUPPORT,4,2     ; @ATOM_DEVICE_TV_SUPPORT
	.comm	_AMDGPU_PLL_PREFER_CLOSEST_LOWER,4,2 ; @AMDGPU_PLL_PREFER_CLOSEST_LOWER
	.comm	_AMDGPU_PLL_IS_LCD,4,2          ; @AMDGPU_PLL_IS_LCD
	.comm	_ATOM_ENCODER_MODE_HDMI,4,2     ; @ATOM_ENCODER_MODE_HDMI
	.comm	_COMMAND,4,2                    ; @COMMAND
	.comm	_AdjustDisplayPll,4,2           ; @AdjustDisplayPll
	.comm	_ADJUST_DISPLAY_CONFIG_SS_ENABLE,4,2 ; @ADJUST_DISPLAY_CONFIG_SS_ENABLE
	.comm	_DISPPLL_CONFIG_SS_ENABLE,4,2   ; @DISPPLL_CONFIG_SS_ENABLE
	.comm	_DISPPLL_CONFIG_COHERENT_MODE,4,2 ; @DISPPLL_CONFIG_COHERENT_MODE
	.comm	_DISPPLL_CONFIG_DUAL_LINK,4,2   ; @DISPPLL_CONFIG_DUAL_LINK
	.comm	_AMDGPU_PLL_USE_POST_DIV,4,2    ; @AMDGPU_PLL_USE_POST_DIV
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Unknown table version %d %d\n"

	.no_dead_strip	_amdgpu_atombios_crtc_adjust_pll
.subsections_via_symbols
