	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_legacy_lvds_mode_set
_radeon_legacy_lvds_mode_set:           ## @radeon_legacy_lvds_mode_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r15
	movq	%rdi, %rbx
	movq	8(%rdi), %rax
	movq	(%rax), %r14
	movl	(%rdi), %edi
	callq	_to_radeon_crtc
	movq	%rax, -64(%rbp)                 ## 8-byte Spill
	movq	%rbx, %rdi
	callq	_to_radeon_encoder
	movq	%rax, %r13
	leaq	L_.str(%rip), %rdi
	xorl	%eax, %eax
	callq	_DRM_DEBUG_KMS
	movq	_RADEON_LVDS_PLL_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_RADEON_LVDS_PLL_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r12d
	notl	%r12d
	andl	%eax, %r12d
	movq	_RADEON_LVDS_SS_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	cmpq	$0, 8(%r14)
	movq	%rbx, -56(%rbp)                 ## 8-byte Spill
	movq	%r13, -72(%rbp)                 ## 8-byte Spill
	je	LBB0_2
## %bb.1:
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movl	(%r15), %eax
	movl	%eax, 16(%r13)
	movq	_PANEL_ENCODER_ACTION_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_atombios_digital_setup
LBB0_5:
	movq	_RADEON_LVDS_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	jmp	LBB0_6
LBB0_2:
	movq	8(%r13), %r15
	testq	%r15, %r15
	je	LBB0_4
## %bb.3:
	movl	(%r15), %esi
	leaq	L_.str.1(%rip), %rdi
	movl	%eax, %ebx
	xorl	%eax, %eax
	callq	_DRM_DEBUG_KMS
	movl	(%r15), %eax
	movl	4(%r15), %edi
	movq	_RADEON_LVDS_PWRSEQ_DELAY1_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %r8b
	movl	$15, %esi
	movl	$15, %edx
	movl	%r8d, %ecx
	shll	%cl, %edx
	movq	_RADEON_LVDS_PWRSEQ_DELAY2_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %r9b
	movl	%r9d, %ecx
	shll	%cl, %esi
	orl	%edx, %esi
	movl	%r8d, %ecx
	shll	%cl, %edi
	movl	8(%r15), %edx
	movl	%r9d, %ecx
	shll	%cl, %edx
	notl	%esi
	andl	%esi, %ebx
	orl	%edi, %edx
	orl	%edx, %ebx
	movl	%ebx, -44(%rbp)                 ## 4-byte Spill
LBB0_6:
	movq	-64(%rbp), %r13                 ## 8-byte Reload
	movq	_RADEON_LVDS_DISPLAY_DIS@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_LVDS_ON@GOTPCREL(%rip), %rcx
	movq	_RADEON_LVDS_BLON@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r15d
	orl	(%rcx), %r15d
	movq	_RADEON_LVDS_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r15d
	movq	_RADEON_LVDS_RST_FM@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r15d
	notl	%r15d
	andl	%eax, %r15d
	movq	%r14, %rdi
	callq	_ASIC_IS_R300
	movq	_R300_LVDS_SRC_SEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	xorl	%edx, %edx
	cmpq	$1, %rax
	sbbl	%edx, %edx
	notl	%ecx
	orl	%ecx, %edx
	andl	%edx, %r12d
	movq	%r14, %rdi
	movq	%r13, %r14
	movq	(%r13), %r13
	movq	%rdi, %rbx
	callq	_ASIC_IS_R300
	testq	%r13, %r13
	je	LBB0_7
## %bb.11:
	testq	%rax, %rax
	je	LBB0_13
## %bb.12:
	movq	_R300_LVDS_SRC_SEL_CRTC2@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
	jmp	LBB0_14
LBB0_7:
	testq	%rax, %rax
	je	LBB0_10
## %bb.8:
	movq	-72(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rax
	movq	_RMX_OFF@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	movq	%r14, %r13
	movq	-56(%rbp), %r14                 ## 8-byte Reload
	je	LBB0_15
## %bb.9:
	movq	_R300_LVDS_SRC_SEL_RMX@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
	jmp	LBB0_15
LBB0_13:
	movq	_RADEON_LVDS_SEL_CRTC2@GOTPCREL(%rip), %rax
	orl	(%rax), %r15d
	jmp	LBB0_14
LBB0_4:
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	jmp	LBB0_5
LBB0_10:
	movq	_RADEON_LVDS_SEL_CRTC2@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r15d
LBB0_14:
	movq	%r14, %r13
	movq	-56(%rbp), %r14                 ## 8-byte Reload
LBB0_15:
	movq	_RADEON_LVDS_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movq	_RADEON_LVDS_PLL_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_RADEON_LVDS_SS_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	(%rbx), %rax
	movq	_CHIP_RV410@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_17
## %bb.16:
	movq	_RADEON_CLOCK_CNTL_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
LBB0_17:
	cmpq	$0, 8(%rbx)
	movq	(%r13), %rsi
	movq	%r14, %rdi
	je	LBB0_19
## %bb.18:
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_atombios_encoder_crtc_scratch_regs ## TAILCALL
LBB0_19:
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_combios_encoder_crtc_scratch_regs ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"\n"

	.comm	_RADEON_LVDS_PLL_CNTL,4,2       ## @RADEON_LVDS_PLL_CNTL
	.comm	_RADEON_LVDS_PLL_EN,4,2         ## @RADEON_LVDS_PLL_EN
	.comm	_RADEON_LVDS_SS_GEN_CNTL,4,2    ## @RADEON_LVDS_SS_GEN_CNTL
	.comm	_PANEL_ENCODER_ACTION_ENABLE,4,2 ## @PANEL_ENCODER_ACTION_ENABLE
	.comm	_RADEON_LVDS_GEN_CNTL,4,2       ## @RADEON_LVDS_GEN_CNTL
L_.str.1:                               ## @.str.1
	.asciz	"bios LVDS_GEN_CNTL: 0x%x\n"

	.comm	_RADEON_LVDS_PWRSEQ_DELAY1_SHIFT,4,2 ## @RADEON_LVDS_PWRSEQ_DELAY1_SHIFT
	.comm	_RADEON_LVDS_PWRSEQ_DELAY2_SHIFT,4,2 ## @RADEON_LVDS_PWRSEQ_DELAY2_SHIFT
	.comm	_RADEON_LVDS_DISPLAY_DIS,4,2    ## @RADEON_LVDS_DISPLAY_DIS
	.comm	_RADEON_LVDS_ON,4,2             ## @RADEON_LVDS_ON
	.comm	_RADEON_LVDS_BLON,4,2           ## @RADEON_LVDS_BLON
	.comm	_RADEON_LVDS_EN,4,2             ## @RADEON_LVDS_EN
	.comm	_RADEON_LVDS_RST_FM,4,2         ## @RADEON_LVDS_RST_FM
	.comm	_R300_LVDS_SRC_SEL_MASK,4,2     ## @R300_LVDS_SRC_SEL_MASK
	.comm	_RMX_OFF,8,3                    ## @RMX_OFF
	.comm	_R300_LVDS_SRC_SEL_RMX,4,2      ## @R300_LVDS_SRC_SEL_RMX
	.comm	_RADEON_LVDS_SEL_CRTC2,4,2      ## @RADEON_LVDS_SEL_CRTC2
	.comm	_R300_LVDS_SRC_SEL_CRTC2,4,2    ## @R300_LVDS_SRC_SEL_CRTC2
	.comm	_CHIP_RV410,8,3                 ## @CHIP_RV410
	.comm	_RADEON_CLOCK_CNTL_INDEX,4,2    ## @RADEON_CLOCK_CNTL_INDEX
	.no_dead_strip	_radeon_legacy_lvds_mode_set
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_legacy_lvds_mode_set
_radeon_legacy_lvds_mode_set:           ; @radeon_legacy_lvds_mode_set
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x24, x2
	mov	x19, x0
	ldr	x8, [x0, #8]
	ldr	x20, [x8]
	ldr	w0, [x0]
	bl	_to_radeon_crtc
	str	x0, [sp, #8]                    ; 8-byte Folded Spill
	mov	x0, x19
	bl	_to_radeon_encoder
	mov	x23, x0
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_KMS
Lloh2:
	adrp	x27, _RADEON_LVDS_PLL_CNTL@GOTPAGE
Lloh3:
	ldr	x27, [x27, _RADEON_LVDS_PLL_CNTL@GOTPAGEOFF]
	ldr	w0, [x27]
	bl	_RREG32
Lloh4:
	adrp	x8, _RADEON_LVDS_PLL_EN@GOTPAGE
Lloh5:
	ldr	x8, [x8, _RADEON_LVDS_PLL_EN@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
	bic	w25, w0, w8
Lloh7:
	adrp	x28, _RADEON_LVDS_SS_GEN_CNTL@GOTPAGE
Lloh8:
	ldr	x28, [x28, _RADEON_LVDS_SS_GEN_CNTL@GOTPAGEOFF]
	ldr	w0, [x28]
	bl	_RREG32
	mov	x22, x0
	ldr	x8, [x20, #8]
Lloh9:
	adrp	x26, _RADEON_LVDS_GEN_CNTL@GOTPAGE
Lloh10:
	ldr	x26, [x26, _RADEON_LVDS_GEN_CNTL@GOTPAGEOFF]
	cbz	x8, LBB0_3
; %bb.1:
	ldr	w8, [x24]
	str	w8, [x23, #16]
Lloh11:
	adrp	x8, _PANEL_ENCODER_ACTION_ENABLE@GOTPAGE
Lloh12:
	ldr	x8, [x8, _PANEL_ENCODER_ACTION_ENABLE@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_atombios_digital_setup
LBB0_2:
	mov	x21, x26
	ldr	w0, [x26]
	bl	_RREG32
	b	LBB0_5
LBB0_3:
	ldr	x24, [x23, #8]
	cbz	x24, LBB0_2
; %bb.4:
	mov	x21, x26
	ldr	w8, [x24]
	str	x8, [sp]
Lloh14:
	adrp	x0, l_.str.1@PAGE
Lloh15:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_DEBUG_KMS
Lloh16:
	adrp	x8, _RADEON_LVDS_PWRSEQ_DELAY1_SHIFT@GOTPAGE
Lloh17:
	ldr	x8, [x8, _RADEON_LVDS_PWRSEQ_DELAY1_SHIFT@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	mov	w9, #15
Lloh19:
	adrp	x10, _RADEON_LVDS_PWRSEQ_DELAY2_SHIFT@GOTPAGE
Lloh20:
	ldr	x10, [x10, _RADEON_LVDS_PWRSEQ_DELAY2_SHIFT@GOTPAGEOFF]
	lsl	w11, w9, w8
Lloh21:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w9, w9, w11
	bic	w9, w22, w9
	ldp	w0, w11, [x24]
	lsl	w8, w11, w8
	ldr	w11, [x24, #8]
	lsl	w10, w11, w10
	orr	w8, w10, w8
	orr	w22, w8, w9
LBB0_5:
Lloh22:
	adrp	x8, _RADEON_LVDS_DISPLAY_DIS@GOTPAGE
Lloh23:
	ldr	x8, [x8, _RADEON_LVDS_DISPLAY_DIS@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh25:
	adrp	x9, _RADEON_LVDS_ON@GOTPAGE
Lloh26:
	ldr	x9, [x9, _RADEON_LVDS_ON@GOTPAGEOFF]
Lloh27:
	adrp	x10, _RADEON_LVDS_BLON@GOTPAGE
Lloh28:
	ldr	x10, [x10, _RADEON_LVDS_BLON@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
Lloh30:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh31:
	adrp	x10, _RADEON_LVDS_EN@GOTPAGE
Lloh32:
	ldr	x10, [x10, _RADEON_LVDS_EN@GOTPAGEOFF]
Lloh33:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh34:
	adrp	x10, _RADEON_LVDS_RST_FM@GOTPAGE
Lloh35:
	ldr	x10, [x10, _RADEON_LVDS_RST_FM@GOTPAGEOFF]
Lloh36:
	ldr	w10, [x10]
	orr	w9, w9, w10
	bic	w24, w8, w9
	mov	x0, x20
	bl	_ASIC_IS_R300
Lloh37:
	adrp	x8, _R300_LVDS_SRC_SEL_MASK@GOTPAGE
Lloh38:
	ldr	x8, [x8, _R300_LVDS_SRC_SEL_MASK@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
	cmp	x0, #0
	mov	w9, #-1
	csinv	w8, w9, w8, eq
	and	w25, w25, w8
	ldr	x8, [sp, #8]                    ; 8-byte Folded Reload
	ldr	x26, [x8]
	mov	x0, x20
	bl	_ASIC_IS_R300
	cbz	x26, LBB0_8
; %bb.6:
	cbz	x0, LBB0_12
; %bb.7:
Lloh40:
	adrp	x8, _R300_LVDS_SRC_SEL_CRTC2@GOTPAGE
Lloh41:
	ldr	x8, [x8, _R300_LVDS_SRC_SEL_CRTC2@GOTPAGEOFF]
	b	LBB0_11
LBB0_8:
	cbz	x0, LBB0_13
; %bb.9:
	ldr	x8, [x23]
Lloh42:
	adrp	x9, _RMX_OFF@GOTPAGE
Lloh43:
	ldr	x9, [x9, _RMX_OFF@GOTPAGEOFF]
Lloh44:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_14
; %bb.10:
Lloh45:
	adrp	x8, _R300_LVDS_SRC_SEL_RMX@GOTPAGE
Lloh46:
	ldr	x8, [x8, _R300_LVDS_SRC_SEL_RMX@GOTPAGEOFF]
LBB0_11:
	ldr	w8, [x8]
	orr	w25, w8, w25
	b	LBB0_14
LBB0_12:
Lloh47:
	adrp	x8, _RADEON_LVDS_SEL_CRTC2@GOTPAGE
Lloh48:
	ldr	x8, [x8, _RADEON_LVDS_SEL_CRTC2@GOTPAGEOFF]
Lloh49:
	ldr	w8, [x8]
	orr	w24, w8, w24
	b	LBB0_14
LBB0_13:
Lloh50:
	adrp	x8, _RADEON_LVDS_SEL_CRTC2@GOTPAGE
Lloh51:
	ldr	x8, [x8, _RADEON_LVDS_SEL_CRTC2@GOTPAGEOFF]
Lloh52:
	ldr	w8, [x8]
	bic	w24, w24, w8
LBB0_14:
	ldr	w0, [x21]
	mov	x1, x24
	bl	_WREG32
	ldr	w0, [x27]
	mov	x1, x25
	bl	_WREG32
	ldr	w0, [x28]
	mov	x1, x22
	bl	_WREG32
	ldr	x8, [x20]
Lloh53:
	adrp	x9, _CHIP_RV410@GOTPAGE
Lloh54:
	ldr	x9, [x9, _CHIP_RV410@GOTPAGEOFF]
Lloh55:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_16
; %bb.15:
Lloh56:
	adrp	x8, _RADEON_CLOCK_CNTL_INDEX@GOTPAGE
Lloh57:
	ldr	x8, [x8, _RADEON_CLOCK_CNTL_INDEX@GOTPAGEOFF]
Lloh58:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
LBB0_16:
	ldr	x8, [x20, #8]
	ldr	x9, [sp, #8]                    ; 8-byte Folded Reload
	ldr	x1, [x9]
	mov	x0, x19
	cbz	x8, LBB0_18
; %bb.17:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	b	_radeon_atombios_encoder_crtc_scratch_regs
LBB0_18:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	b	_radeon_combios_encoder_crtc_scratch_regs
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpAdd	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh29
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"\n"

	.comm	_RADEON_LVDS_PLL_CNTL,4,2       ; @RADEON_LVDS_PLL_CNTL
	.comm	_RADEON_LVDS_PLL_EN,4,2         ; @RADEON_LVDS_PLL_EN
	.comm	_RADEON_LVDS_SS_GEN_CNTL,4,2    ; @RADEON_LVDS_SS_GEN_CNTL
	.comm	_PANEL_ENCODER_ACTION_ENABLE,4,2 ; @PANEL_ENCODER_ACTION_ENABLE
	.comm	_RADEON_LVDS_GEN_CNTL,4,2       ; @RADEON_LVDS_GEN_CNTL
l_.str.1:                               ; @.str.1
	.asciz	"bios LVDS_GEN_CNTL: 0x%x\n"

	.comm	_RADEON_LVDS_PWRSEQ_DELAY1_SHIFT,4,2 ; @RADEON_LVDS_PWRSEQ_DELAY1_SHIFT
	.comm	_RADEON_LVDS_PWRSEQ_DELAY2_SHIFT,4,2 ; @RADEON_LVDS_PWRSEQ_DELAY2_SHIFT
	.comm	_RADEON_LVDS_DISPLAY_DIS,4,2    ; @RADEON_LVDS_DISPLAY_DIS
	.comm	_RADEON_LVDS_ON,4,2             ; @RADEON_LVDS_ON
	.comm	_RADEON_LVDS_BLON,4,2           ; @RADEON_LVDS_BLON
	.comm	_RADEON_LVDS_EN,4,2             ; @RADEON_LVDS_EN
	.comm	_RADEON_LVDS_RST_FM,4,2         ; @RADEON_LVDS_RST_FM
	.comm	_R300_LVDS_SRC_SEL_MASK,4,2     ; @R300_LVDS_SRC_SEL_MASK
	.comm	_RMX_OFF,8,3                    ; @RMX_OFF
	.comm	_R300_LVDS_SRC_SEL_RMX,4,2      ; @R300_LVDS_SRC_SEL_RMX
	.comm	_RADEON_LVDS_SEL_CRTC2,4,2      ; @RADEON_LVDS_SEL_CRTC2
	.comm	_R300_LVDS_SRC_SEL_CRTC2,4,2    ; @R300_LVDS_SRC_SEL_CRTC2
	.comm	_CHIP_RV410,8,3                 ; @CHIP_RV410
	.comm	_RADEON_CLOCK_CNTL_INDEX,4,2    ; @RADEON_CLOCK_CNTL_INDEX
	.no_dead_strip	_radeon_legacy_lvds_mode_set
.subsections_via_symbols
