	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function r100_pll_errata_after_data
_r100_pll_errata_after_data:            ## @r100_pll_errata_after_data
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movl	(%rdi), %eax
	movq	_CHIP_ERRATA_PLL_DELAY@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_2
## %bb.1:
	movq	%rdi, %rbx
	movl	$5, %edi
	callq	_mdelay
	movl	(%rbx), %eax
LBB0_2:
	movq	_CHIP_ERRATA_R300_CG@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_3
## %bb.4:
	movq	_RADEON_CLOCK_CNTL_INDEX@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32
	movl	%eax, %ebx
	movq	_RADEON_PLL_WR_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	%ebx, %esi
	andl	$-64, %esi
	movl	(%r14), %edi
	callq	_WREG32
	movq	_RADEON_CLOCK_CNTL_DATA@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	(%r14), %edi
	movl	%ebx, %esi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
LBB0_3:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CHIP_ERRATA_PLL_DELAY,4,2      ## @CHIP_ERRATA_PLL_DELAY
	.comm	_CHIP_ERRATA_R300_CG,4,2        ## @CHIP_ERRATA_R300_CG
	.comm	_RADEON_CLOCK_CNTL_INDEX,4,2    ## @RADEON_CLOCK_CNTL_INDEX
	.comm	_RADEON_PLL_WR_EN,4,2           ## @RADEON_PLL_WR_EN
	.comm	_RADEON_CLOCK_CNTL_DATA,4,2     ## @RADEON_CLOCK_CNTL_DATA
	.no_dead_strip	_r100_pll_errata_after_data
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function r100_pll_errata_after_data
_r100_pll_errata_after_data:            ; @r100_pll_errata_after_data
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _CHIP_ERRATA_PLL_DELAY@GOTPAGE
Lloh1:
	ldr	x9, [x9, _CHIP_ERRATA_PLL_DELAY@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
	mov	x19, x0
	mov	w0, #5
	bl	_mdelay
	ldr	w8, [x19]
LBB0_2:
Lloh3:
	adrp	x9, _CHIP_ERRATA_R300_CG@GOTPAGE
Lloh4:
	ldr	x9, [x9, _CHIP_ERRATA_R300_CG@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_4
; %bb.3:
Lloh6:
	adrp	x20, _RADEON_CLOCK_CNTL_INDEX@GOTPAGE
Lloh7:
	ldr	x20, [x20, _RADEON_CLOCK_CNTL_INDEX@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	mov	x19, x0
Lloh8:
	adrp	x8, _RADEON_PLL_WR_EN@GOTPAGE
Lloh9:
	ldr	x8, [x8, _RADEON_PLL_WR_EN@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	bic	w8, w0, w8
	and	w1, w8, #0xffffffc0
	ldr	w0, [x20]
	bl	_WREG32
Lloh11:
	adrp	x8, _RADEON_CLOCK_CNTL_DATA@GOTPAGE
Lloh12:
	ldr	x8, [x8, _RADEON_CLOCK_CNTL_DATA@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
	bl	_RREG32
	ldr	w0, [x20]
	mov	x1, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_WREG32
LBB0_4:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.cfi_endproc
                                        ; -- End function
	.comm	_CHIP_ERRATA_PLL_DELAY,4,2      ; @CHIP_ERRATA_PLL_DELAY
	.comm	_CHIP_ERRATA_R300_CG,4,2        ; @CHIP_ERRATA_R300_CG
	.comm	_RADEON_CLOCK_CNTL_INDEX,4,2    ; @RADEON_CLOCK_CNTL_INDEX
	.comm	_RADEON_PLL_WR_EN,4,2           ; @RADEON_PLL_WR_EN
	.comm	_RADEON_CLOCK_CNTL_DATA,4,2     ; @RADEON_CLOCK_CNTL_DATA
	.no_dead_strip	_r100_pll_errata_after_data
.subsections_via_symbols
