	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function smu10_powergate_vcn
_smu10_powergate_vcn:                   ## @smu10_powergate_vcn
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	8(%rdi), %r14
	testl	%esi, %esi
	je	LBB0_2
## %bb.1:
	movl	(%rbx), %edi
	movq	_AMD_IP_BLOCK_TYPE_VCN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AMD_PG_STATE_GATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_amdgpu_device_ip_set_powergating_state
	movq	_PPSMC_MSG_PowerDownVcn@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_smum_send_msg_to_smc_with_parameter
	movl	$1, %r15d
	jmp	LBB0_3
LBB0_2:
	movq	_PPSMC_MSG_PowerUpVcn@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%r15d, %r15d
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_smum_send_msg_to_smc_with_parameter
	movl	(%rbx), %edi
	movq	_AMD_IP_BLOCK_TYPE_VCN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AMD_PG_STATE_UNGATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_amdgpu_device_ip_set_powergating_state
LBB0_3:
	movl	%r15d, (%r14)
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_IP_BLOCK_TYPE_VCN,4,2      ## @AMD_IP_BLOCK_TYPE_VCN
	.comm	_AMD_PG_STATE_GATE,4,2          ## @AMD_PG_STATE_GATE
	.comm	_PPSMC_MSG_PowerDownVcn,4,2     ## @PPSMC_MSG_PowerDownVcn
	.comm	_PPSMC_MSG_PowerUpVcn,4,2       ## @PPSMC_MSG_PowerUpVcn
	.comm	_AMD_PG_STATE_UNGATE,4,2        ## @AMD_PG_STATE_UNGATE
	.no_dead_strip	_smu10_powergate_vcn
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function smu10_powergate_vcn
_smu10_powergate_vcn:                   ; @smu10_powergate_vcn
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	x20, [x0, #8]
	cbz	w1, LBB0_2
; %bb.1:
	ldr	w0, [x19]
Lloh0:
	adrp	x8, _AMD_IP_BLOCK_TYPE_VCN@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMD_IP_BLOCK_TYPE_VCN@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
Lloh3:
	adrp	x8, _AMD_PG_STATE_GATE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _AMD_PG_STATE_GATE@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	bl	_amdgpu_device_ip_set_powergating_state
Lloh6:
	adrp	x8, _PPSMC_MSG_PowerDownVcn@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PPSMC_MSG_PowerDownVcn@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_smum_send_msg_to_smc_with_parameter
	mov	w8, #1
	b	LBB0_3
LBB0_2:
Lloh9:
	adrp	x8, _PPSMC_MSG_PowerUpVcn@GOTPAGE
Lloh10:
	ldr	x8, [x8, _PPSMC_MSG_PowerUpVcn@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_smum_send_msg_to_smc_with_parameter
	ldr	w0, [x19]
Lloh12:
	adrp	x8, _AMD_IP_BLOCK_TYPE_VCN@GOTPAGE
Lloh13:
	ldr	x8, [x8, _AMD_IP_BLOCK_TYPE_VCN@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
Lloh15:
	adrp	x8, _AMD_PG_STATE_UNGATE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _AMD_PG_STATE_UNGATE@GOTPAGEOFF]
Lloh17:
	ldr	w2, [x8]
	bl	_amdgpu_device_ip_set_powergating_state
	mov	w8, #0
LBB0_3:
	str	w8, [x20]
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_IP_BLOCK_TYPE_VCN,4,2      ; @AMD_IP_BLOCK_TYPE_VCN
	.comm	_AMD_PG_STATE_GATE,4,2          ; @AMD_PG_STATE_GATE
	.comm	_PPSMC_MSG_PowerDownVcn,4,2     ; @PPSMC_MSG_PowerDownVcn
	.comm	_PPSMC_MSG_PowerUpVcn,4,2       ; @PPSMC_MSG_PowerUpVcn
	.comm	_AMD_PG_STATE_UNGATE,4,2        ; @AMD_PG_STATE_UNGATE
	.no_dead_strip	_smu10_powergate_vcn
.subsections_via_symbols
