	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function uvd_v7_0_hw_init
_uvd_v7_0_hw_init:                      ## @uvd_v7_0_hw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	callq	_amdgpu_sriov_vf
	movq	%r12, %rdi
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	callq	_uvd_v7_0_sriov_start
	jmp	LBB0_3
LBB0_2:
	callq	_uvd_v7_0_start
LBB0_3:
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	LBB0_18
## %bb.4:
	cmpl	$0, (%r12)
	jle	LBB0_16
## %bb.5:
	xorl	%r14d, %r14d
	jmp	LBB0_7
	.p2align	4, 0x90
LBB0_6:                                 ##   in Loop: Header=BB0_7 Depth=1
	incq	%r14
	movslq	(%r12), %rax
	cmpq	%rax, %r14
	jge	LBB0_16
LBB0_7:                                 ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_14 Depth 2
	movl	4(%r12), %eax
	btl	%r14d, %eax
	jb	LBB0_6
## %bb.8:                               ##   in Loop: Header=BB0_7 Depth=1
	movq	16(%r12), %rbx
	movq	%r14, %rax
	shlq	$4, %rax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movq	%r12, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	jne	LBB0_12
## %bb.9:                               ##   in Loop: Header=BB0_7 Depth=1
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	addq	%rax, %rbx
	addq	$8, %rbx
	movq	%rbx, %rdi
	callq	_amdgpu_ring_test_helper
	testl	%eax, %eax
	jne	LBB0_17
## %bb.10:                              ##   in Loop: Header=BB0_7 Depth=1
	movq	%rbx, %rdi
	movl	$10, %esi
	callq	_amdgpu_ring_alloc
	testl	%eax, %eax
	jne	LBB0_20
## %bb.11:                              ##   in Loop: Header=BB0_7 Depth=1
	movq	_UVD@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	movq	_mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r14d, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$1048575, %esi                  ## imm = 0xFFFFF
	callq	_amdgpu_ring_write
	movl	(%r15), %edi
	movq	_mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r14d, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$1048575, %esi                  ## imm = 0xFFFFF
	callq	_amdgpu_ring_write
	movl	(%r15), %edi
	movq	_mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r14d, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$1048575, %esi                  ## imm = 0xFFFFF
	callq	_amdgpu_ring_write
	movl	(%r15), %edi
	movq	_mmUVD_SEMA_TIMEOUT_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r14d, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$8, %esi
	callq	_amdgpu_ring_write
	movl	(%r15), %edi
	movq	_mmUVD_SEMA_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r14d, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$3, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	callq	_amdgpu_ring_commit
LBB0_12:                                ##   in Loop: Header=BB0_7 Depth=1
	cmpl	$0, 8(%r12)
	jle	LBB0_6
## %bb.13:                              ##   in Loop: Header=BB0_7 Depth=1
	xorl	%ebx, %ebx
	xorl	%r13d, %r13d
	.p2align	4, 0x90
LBB0_14:                                ##   Parent Loop BB0_7 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movq	16(%r12), %rax
	movq	-48(%rbp), %rcx                 ## 8-byte Reload
	movq	(%rax,%rcx), %rdi
	addq	%rbx, %rdi
	callq	_amdgpu_ring_test_helper
	testl	%eax, %eax
	jne	LBB0_17
## %bb.15:                              ##   in Loop: Header=BB0_14 Depth=2
	incq	%r13
	movslq	8(%r12), %rax
	addq	$4, %rbx
	cmpq	%rax, %r13
	jl	LBB0_14
	jmp	LBB0_6
LBB0_17:
	movl	%eax, %r15d
	jmp	LBB0_18
LBB0_16:
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_INFO
	xorl	%r15d, %r15d
LBB0_18:
	movl	%r15d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_20:
	movl	%eax, %r15d
	leaq	L_.str(%rip), %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_DRM_ERROR
	jmp	LBB0_18
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"amdgpu: (%d)ring failed to lock UVD ring (%d).\n"

	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL,4,2 ## @mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
	.comm	_mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL,4,2 ## @mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
	.comm	_mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL,4,2 ## @mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
	.comm	_mmUVD_SEMA_TIMEOUT_STATUS,4,2  ## @mmUVD_SEMA_TIMEOUT_STATUS
	.comm	_mmUVD_SEMA_CNTL,4,2            ## @mmUVD_SEMA_CNTL
L_.str.1:                               ## @.str.1
	.asciz	"UVD and UVD ENC initialized successfully.\n"

	.no_dead_strip	_uvd_v7_0_hw_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function uvd_v7_0_hw_init
_uvd_v7_0_hw_init:                      ; @uvd_v7_0_hw_init
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_2
; %bb.1:
	mov	x0, x19
	bl	_uvd_v7_0_sriov_start
	mov	x22, x0
	cbnz	w0, LBB0_17
	b	LBB0_3
LBB0_2:
	mov	x0, x19
	bl	_uvd_v7_0_start
	mov	x22, x0
	cbnz	w0, LBB0_17
LBB0_3:
	ldr	w8, [x19]
	cmp	w8, #1
	b.lt	LBB0_16
; %bb.4:
	mov	x20, #0
Lloh0:
	adrp	x23, _UVD@GOTPAGE
Lloh1:
	ldr	x23, [x23, _UVD@GOTPAGEOFF]
Lloh2:
	adrp	x25, _mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL@GOTPAGE
Lloh3:
	ldr	x25, [x25, _mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL@GOTPAGEOFF]
Lloh4:
	adrp	x26, _mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL@GOTPAGE
Lloh5:
	ldr	x26, [x26, _mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL@GOTPAGEOFF]
Lloh6:
	adrp	x27, _mmUVD_SEMA_TIMEOUT_STATUS@GOTPAGE
Lloh7:
	ldr	x27, [x27, _mmUVD_SEMA_TIMEOUT_STATUS@GOTPAGEOFF]
Lloh8:
	adrp	x28, _mmUVD_SEMA_CNTL@GOTPAGE
Lloh9:
	ldr	x28, [x28, _mmUVD_SEMA_CNTL@GOTPAGEOFF]
	b	LBB0_6
LBB0_5:                                 ;   in Loop: Header=BB0_6 Depth=1
	add	x20, x20, #1
	ldrsw	x8, [x19]
	cmp	x20, x8
	b.ge	LBB0_16
LBB0_6:                                 ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_13 Depth 2
	ldr	w8, [x19, #4]
	lsr	w8, w8, w20
	tbnz	w8, #0, LBB0_5
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=1
	ldr	x21, [x19, #16]
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbnz	x0, LBB0_11
; %bb.8:                                ;   in Loop: Header=BB0_6 Depth=1
	add	x8, x21, x20, lsl #4
	add	x21, x8, #8
	mov	x0, x21
	bl	_amdgpu_ring_test_helper
	cbnz	w0, LBB0_15
; %bb.9:                                ;   in Loop: Header=BB0_6 Depth=1
	mov	x0, x21
	mov	w1, #10
	bl	_amdgpu_ring_alloc
	cbnz	w0, LBB0_18
; %bb.10:                               ;   in Loop: Header=BB0_6 Depth=1
	ldr	w0, [x23]
Lloh10:
	adrp	x8, _mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL@GOTPAGE
Lloh11:
	ldr	x8, [x8, _mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL@GOTPAGEOFF]
Lloh12:
	ldr	w2, [x8]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x21
	bl	_amdgpu_ring_write
	mov	x0, x21
	mov	w1, #1048575
	bl	_amdgpu_ring_write
	ldr	w0, [x23]
	ldr	w2, [x25]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x21
	bl	_amdgpu_ring_write
	mov	x0, x21
	mov	w1, #1048575
	bl	_amdgpu_ring_write
	ldr	w0, [x23]
	ldr	w2, [x26]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x21
	bl	_amdgpu_ring_write
	mov	x0, x21
	mov	w1, #1048575
	bl	_amdgpu_ring_write
	ldr	w0, [x23]
	ldr	w2, [x27]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x21
	bl	_amdgpu_ring_write
	mov	x0, x21
	mov	w1, #8
	bl	_amdgpu_ring_write
	ldr	w0, [x23]
	ldr	w2, [x28]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x21
	bl	_amdgpu_ring_write
	mov	x0, x21
	mov	w1, #3
	bl	_amdgpu_ring_write
	mov	x0, x21
	bl	_amdgpu_ring_commit
LBB0_11:                                ;   in Loop: Header=BB0_6 Depth=1
	ldr	w8, [x19, #8]
	cmp	w8, #1
	b.lt	LBB0_5
; %bb.12:                               ;   in Loop: Header=BB0_6 Depth=1
	mov	x21, #0
	mov	x24, #0
LBB0_13:                                ;   Parent Loop BB0_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ldr	x8, [x19, #16]
	lsl	x9, x20, #4
	ldr	x8, [x8, x9]
	add	x0, x8, x21
	bl	_amdgpu_ring_test_helper
	cbnz	w0, LBB0_15
; %bb.14:                               ;   in Loop: Header=BB0_13 Depth=2
	add	x24, x24, #1
	ldrsw	x8, [x19, #8]
	add	x21, x21, #4
	cmp	x24, x8
	b.lt	LBB0_13
	b	LBB0_5
LBB0_15:
	mov	x22, x0
	b	LBB0_17
LBB0_16:
Lloh13:
	adrp	x0, l_.str.1@PAGE
Lloh14:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_INFO
	mov	w22, #0
LBB0_17:
	mov	x0, x22
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
LBB0_18:
	mov	x22, x0
Lloh15:
	adrp	x0, l_.str@PAGE
Lloh16:
	add	x0, x0, l_.str@PAGEOFF
	mov	x1, x20
	mov	x2, x22
	bl	_DRM_ERROR
	b	LBB0_17
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpAdd	Lloh13, Lloh14
	.loh AdrpAdd	Lloh15, Lloh16
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"amdgpu: (%d)ring failed to lock UVD ring (%d).\n"

	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL,4,2 ; @mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
	.comm	_mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL,4,2 ; @mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
	.comm	_mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL,4,2 ; @mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
	.comm	_mmUVD_SEMA_TIMEOUT_STATUS,4,2  ; @mmUVD_SEMA_TIMEOUT_STATUS
	.comm	_mmUVD_SEMA_CNTL,4,2            ; @mmUVD_SEMA_CNTL
l_.str.1:                               ; @.str.1
	.asciz	"UVD and UVD ENC initialized successfully.\n"

	.no_dead_strip	_uvd_v7_0_hw_init
.subsections_via_symbols
