	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v9_0_init_cp_compute_microcode
_gfx_v9_0_init_cp_compute_microcode:    ## @gfx_v9_0_init_cp_compute_microcode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r15
	movq	%rdi, %r12
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -48(%rbp)
	leaq	L_.str(%rip), %rdx
	leaq	-80(%rbp), %r14
	movq	%r14, %rdi
	movl	$30, %esi
	movq	%r15, %rcx
	callq	_snprintf
	leaq	32(%r12), %rbx
	movl	40(%r12), %edx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	_request_firmware
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	LBB0_10
## %bb.1:
	movq	(%rbx), %rdi
	callq	_amdgpu_ucode_validate
	movl	%eax, %r14d
	testl	%eax, %eax
	je	LBB0_2
LBB0_10:
	movq	%r12, %rdi
	callq	_gfx_v9_0_check_if_need_gfxoff
	movq	%r12, %rdi
	callq	_gfx_v9_0_check_fw_write_wait
	testl	%r14d, %r14d
	je	LBB0_12
## %bb.11:
	movl	40(%r12), %edi
	leaq	L_.str.2(%rip), %rsi
	leaq	-80(%rbp), %rdx
	callq	_dev_err
	movq	32(%r12), %rdi
	callq	_release_firmware
	movq	$0, 32(%r12)
	movq	24(%r12), %rdi
	callq	_release_firmware
	movq	$0, 24(%r12)
LBB0_12:
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	cmpq	-48(%rbp), %rax
	jne	LBB0_14
## %bb.13:
	movl	%r14d, %eax
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	movq	32(%r12), %rax
	movq	(%rax), %rbx
	movl	8(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 8(%r12)
	movl	4(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 12(%r12)
	leaq	L_.str.1(%rip), %rdx
	leaq	-80(%rbp), %r14
	movq	%r14, %rdi
	movl	$30, %esi
	movq	%r15, %rcx
	callq	_snprintf
	leaq	24(%r12), %rbx
	movl	40(%r12), %edx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	_request_firmware
	testl	%eax, %eax
	je	LBB0_3
## %bb.5:
	movq	$0, (%rbx)
LBB0_6:
	movq	48(%r12), %rax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	xorl	%r14d, %r14d
	cmpq	(%rcx), %rax
	jne	LBB0_10
## %bb.7:
	movq	64(%r12), %rax
	movq	_AMDGPU_UCODE_ID_CP_MEC1@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	32(%r12), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movq	(%rcx), %r13
	movl	(%r13), %edi
	callq	_le32_to_cpu
	movl	%eax, %ebx
	movl	(%r13), %edi
	callq	_le32_to_cpu
	shll	$2, %eax
	subl	%eax, %ebx
	movq	_PAGE_SIZE@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movl	%ebx, %edi
	callq	_ALIGN
	addl	%eax, 56(%r12)
	movq	64(%r12), %rax
	movq	_AMDGPU_UCODE_ID_CP_MEC1_JT@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	32(%r12), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movl	(%r13), %edi
	callq	_le32_to_cpu
                                        ## kill: def $eax killed $eax def $rax
	leal	(,%rax,4), %edi
	movl	(%r15), %esi
	callq	_ALIGN
	addl	%eax, 56(%r12)
	movq	24(%r12), %rax
	testq	%rax, %rax
	je	LBB0_10
## %bb.8:
	movq	64(%r12), %rcx
	movq	_AMDGPU_UCODE_ID_CP_MEC2@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdx
	movq	%rdx, %rsi
	shlq	$4, %rsi
	movq	%rdx, (%rcx,%rsi)
	movq	%rax, 8(%rcx,%rsi)
	movq	(%rax), %r13
	movl	(%r13), %edi
	callq	_le32_to_cpu
	movl	%eax, %ebx
	movl	(%r13), %edi
	callq	_le32_to_cpu
	shll	$2, %eax
	subl	%eax, %ebx
	movl	(%r15), %esi
	movl	%ebx, %edi
	callq	_ALIGN
	addl	%eax, 56(%r12)
	movq	(%r12), %rax
	movq	_CHIP_ARCTURUS@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_10
## %bb.9:
	movq	64(%r12), %rax
	movq	_AMDGPU_UCODE_ID_CP_MEC2_JT@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	24(%r12), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movl	(%r13), %edi
	callq	_le32_to_cpu
                                        ## kill: def $eax killed $eax def $rax
	leal	(,%rax,4), %edi
	movl	(%r15), %esi
	callq	_ALIGN
	addl	%eax, 56(%r12)
	jmp	LBB0_10
LBB0_3:
	movq	(%rbx), %rdi
	callq	_amdgpu_ucode_validate
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	LBB0_10
## %bb.4:
	movq	24(%r12), %rax
	movq	(%rax), %rbx
	movl	8(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 16(%r12)
	movl	4(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 20(%r12)
	jmp	LBB0_6
LBB0_14:
	callq	___stack_chk_fail
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"amdgpu/%s_mec.bin"

L_.str.1:                               ## @.str.1
	.asciz	"amdgpu/%s_mec2.bin"

	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_CP_MEC1,8,3    ## @AMDGPU_UCODE_ID_CP_MEC1
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
	.comm	_AMDGPU_UCODE_ID_CP_MEC1_JT,8,3 ## @AMDGPU_UCODE_ID_CP_MEC1_JT
	.comm	_AMDGPU_UCODE_ID_CP_MEC2,8,3    ## @AMDGPU_UCODE_ID_CP_MEC2
	.comm	_CHIP_ARCTURUS,8,3              ## @CHIP_ARCTURUS
	.comm	_AMDGPU_UCODE_ID_CP_MEC2_JT,8,3 ## @AMDGPU_UCODE_ID_CP_MEC2_JT
L_.str.2:                               ## @.str.2
	.asciz	"gfx9: Failed to load firmware \"%s\"\n"

	.no_dead_strip	_gfx_v9_0_init_cp_compute_microcode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v9_0_init_cp_compute_microcode
_gfx_v9_0_init_cp_compute_microcode:    ; @gfx_v9_0_init_cp_compute_microcode
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x21, x1
	mov	x19, x0
Lloh0:
	adrp	x8, ___stack_chk_guard@GOTPAGE
Lloh1:
	ldr	x8, [x8, ___stack_chk_guard@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	str	x8, [sp, #40]
Lloh3:
	adrp	x2, l_.str@PAGE
Lloh4:
	add	x2, x2, l_.str@PAGEOFF
	add	x0, sp, #10
	mov	w1, #30
	mov	x3, x21
	bl	_snprintf
	add	x22, x19, #32
	ldr	w2, [x19, #40]
	add	x1, sp, #10
	mov	x0, x22
	bl	_request_firmware
	mov	x20, x0
	cbnz	w0, LBB0_11
; %bb.1:
	ldr	x0, [x22]
	bl	_amdgpu_ucode_validate
	mov	x20, x0
	cbnz	w0, LBB0_11
; %bb.2:
	ldr	x8, [x19, #32]
	ldr	x20, [x8]
	ldr	w0, [x20, #8]
	bl	_le32_to_cpu
	str	w0, [x19, #8]
	ldr	w0, [x20, #4]
	bl	_le32_to_cpu
	str	w0, [x19, #12]
Lloh5:
	adrp	x2, l_.str.1@PAGE
Lloh6:
	add	x2, x2, l_.str.1@PAGEOFF
	add	x0, sp, #10
	mov	w1, #30
	mov	x3, x21
	bl	_snprintf
	add	x20, x19, #24
	ldr	w2, [x19, #40]
	add	x1, sp, #10
	mov	x0, x20
	bl	_request_firmware
	cbz	w0, LBB0_8
; %bb.3:
	str	xzr, [x20]
LBB0_4:
	ldr	x8, [x19, #48]
Lloh7:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh8:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh9:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_7
; %bb.5:
	ldr	x8, [x19, #64]
Lloh10:
	adrp	x9, _AMDGPU_UCODE_ID_CP_MEC1@GOTPAGE
Lloh11:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_CP_MEC1@GOTPAGEOFF]
Lloh12:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19, #32]
	str	x9, [x8, #8]
	ldr	x22, [x9]
	ldr	w0, [x22]
	bl	_le32_to_cpu
	mov	x20, x0
	ldr	w0, [x22]
	bl	_le32_to_cpu
	sub	w0, w20, w0, lsl #2
Lloh13:
	adrp	x21, _PAGE_SIZE@GOTPAGE
Lloh14:
	ldr	x21, [x21, _PAGE_SIZE@GOTPAGEOFF]
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #56]
	add	w8, w8, w0
	str	w8, [x19, #56]
	ldr	x8, [x19, #64]
Lloh15:
	adrp	x9, _AMDGPU_UCODE_ID_CP_MEC1_JT@GOTPAGE
Lloh16:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_CP_MEC1_JT@GOTPAGEOFF]
Lloh17:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19, #32]
	str	x9, [x8, #8]
	ldr	w0, [x22]
	bl	_le32_to_cpu
	lsl	w0, w0, #2
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #56]
	add	w8, w8, w0
	str	w8, [x19, #56]
	ldr	x8, [x19, #24]
	cbz	x8, LBB0_7
; %bb.6:
	ldr	x9, [x19, #64]
Lloh18:
	adrp	x10, _AMDGPU_UCODE_ID_CP_MEC2@GOTPAGE
Lloh19:
	ldr	x10, [x10, _AMDGPU_UCODE_ID_CP_MEC2@GOTPAGEOFF]
Lloh20:
	ldr	x10, [x10]
	add	x9, x9, x10, lsl #4
	stp	x10, x8, [x9]
	ldr	x22, [x8]
	ldr	w0, [x22]
	bl	_le32_to_cpu
	mov	x20, x0
	ldr	w0, [x22]
	bl	_le32_to_cpu
	sub	w0, w20, w0, lsl #2
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #56]
	add	w8, w8, w0
	str	w8, [x19, #56]
	ldr	x8, [x19]
Lloh21:
	adrp	x9, _CHIP_ARCTURUS@GOTPAGE
Lloh22:
	ldr	x9, [x9, _CHIP_ARCTURUS@GOTPAGEOFF]
Lloh23:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_10
LBB0_7:
	mov	w20, #0
	b	LBB0_11
LBB0_8:
	ldr	x0, [x20]
	bl	_amdgpu_ucode_validate
	mov	x20, x0
	cbnz	w0, LBB0_11
; %bb.9:
	ldr	x8, [x19, #24]
	ldr	x20, [x8]
	ldr	w0, [x20, #8]
	bl	_le32_to_cpu
	str	w0, [x19, #16]
	ldr	w0, [x20, #4]
	bl	_le32_to_cpu
	str	w0, [x19, #20]
	b	LBB0_4
LBB0_10:
	ldr	x8, [x19, #64]
Lloh24:
	adrp	x9, _AMDGPU_UCODE_ID_CP_MEC2_JT@GOTPAGE
Lloh25:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_CP_MEC2_JT@GOTPAGEOFF]
Lloh26:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19, #24]
	str	x9, [x8, #8]
	ldr	w0, [x22]
	bl	_le32_to_cpu
	lsl	w0, w0, #2
	ldr	w1, [x21]
	bl	_ALIGN
	mov	w20, #0
	ldr	w8, [x19, #56]
	add	w8, w8, w0
	str	w8, [x19, #56]
LBB0_11:
	mov	x0, x19
	bl	_gfx_v9_0_check_if_need_gfxoff
	mov	x0, x19
	bl	_gfx_v9_0_check_fw_write_wait
	cbz	w20, LBB0_13
; %bb.12:
	ldr	w0, [x19, #40]
Lloh27:
	adrp	x1, l_.str.2@PAGE
Lloh28:
	add	x1, x1, l_.str.2@PAGEOFF
	add	x2, sp, #10
	bl	_dev_err
	ldr	x0, [x19, #32]
	bl	_release_firmware
	str	xzr, [x19, #32]
	ldr	x0, [x19, #24]
	bl	_release_firmware
	str	xzr, [x19, #24]
LBB0_13:
	ldr	x8, [sp, #40]
Lloh29:
	adrp	x9, ___stack_chk_guard@GOTPAGE
Lloh30:
	ldr	x9, [x9, ___stack_chk_guard@GOTPAGEOFF]
Lloh31:
	ldr	x9, [x9]
	cmp	x9, x8
	b.ne	LBB0_15
; %bb.14:
	mov	x0, x20
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_15:
	bl	___stack_chk_fail
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpAdd	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"amdgpu/%s_mec.bin"

l_.str.1:                               ; @.str.1
	.asciz	"amdgpu/%s_mec2.bin"

	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_CP_MEC1,8,3    ; @AMDGPU_UCODE_ID_CP_MEC1
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
	.comm	_AMDGPU_UCODE_ID_CP_MEC1_JT,8,3 ; @AMDGPU_UCODE_ID_CP_MEC1_JT
	.comm	_AMDGPU_UCODE_ID_CP_MEC2,8,3    ; @AMDGPU_UCODE_ID_CP_MEC2
	.comm	_CHIP_ARCTURUS,8,3              ; @CHIP_ARCTURUS
	.comm	_AMDGPU_UCODE_ID_CP_MEC2_JT,8,3 ; @AMDGPU_UCODE_ID_CP_MEC2_JT
l_.str.2:                               ; @.str.2
	.asciz	"gfx9: Failed to load firmware \"%s\"\n"

	.no_dead_strip	_gfx_v9_0_init_cp_compute_microcode
.subsections_via_symbols
