	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function amdgpu_vm_fragment
_amdgpu_vm_fragment:                    ## @amdgpu_vm_fragment
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%r9, %r14
	movq	%r8, %r12
	movq	%rdx, %rbx
	movq	%rsi, %r15
	movq	8(%rdi), %rax
	movq	(%rax), %rcx
	movq	_CHIP_VEGA10@GOTPCREL(%rip), %rdx
	movl	$31, %r13d
	cmpq	(%rdx), %rcx
	jge	LBB0_2
## %bb.1:
	movl	8(%rax), %r13d
LBB0_2:
	cmpq	$0, (%rdi)
	je	LBB0_4
## %bb.3:
	movl	$0, (%r12)
	jmp	LBB0_7
LBB0_4:
	movq	%r15, %rdi
	callq	_ffs
	decl	%eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	%rbx, %rdi
	subq	%r15, %rdi
	callq	_fls64
	leal	-1(%rax), %esi
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	callq	_min
	movl	%eax, (%r12)
	cmpl	%r13d, %eax
	jae	LBB0_5
## %bb.6:
	movl	$1, %edx
	movl	%eax, %ecx
	shll	%cl, %edx
	movslq	%edx, %rbx
	addq	%r15, %rbx
	jmp	LBB0_7
LBB0_5:
	movl	%r13d, %ecx
	shrq	%cl, %rbx
	movl	%r13d, (%r12)
	shlq	%cl, %rbx
LBB0_7:
	movq	%rbx, (%r14)
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CHIP_VEGA10,8,3                ## @CHIP_VEGA10
	.no_dead_strip	_amdgpu_vm_fragment
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function amdgpu_vm_fragment
_amdgpu_vm_fragment:                    ; @amdgpu_vm_fragment
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x5
	mov	x21, x4
	mov	x20, x2
	mov	x22, x1
	ldr	x8, [x0, #8]
	ldr	x9, [x8]
Lloh0:
	adrp	x10, _CHIP_VEGA10@GOTPAGE
Lloh1:
	ldr	x10, [x10, _CHIP_VEGA10@GOTPAGEOFF]
Lloh2:
	ldr	x10, [x10]
	cmp	x9, x10
	b.ge	LBB0_3
; %bb.1:
	ldr	w24, [x8, #8]
	ldr	x8, [x0]
	cbz	x8, LBB0_4
LBB0_2:
	str	wzr, [x21]
	b	LBB0_7
LBB0_3:
	mov	w24, #31
	ldr	x8, [x0]
	cbnz	x8, LBB0_2
LBB0_4:
	mov	x0, x22
	bl	_ffs
	sub	w23, w0, #1
	sub	x0, x20, x22
	bl	_fls64
	sub	w1, w0, #1
	mov	x0, x23
	bl	_min
	str	w0, [x21]
	cmp	w0, w24
	b.hs	LBB0_6
; %bb.5:
	mov	w8, #1
	lsl	w8, w8, w0
	add	x20, x22, w8, sxtw
	b	LBB0_7
LBB0_6:
	str	w24, [x21]
	mov	x8, #-1
	lsl	x8, x8, x24
	and	x20, x8, x20
LBB0_7:
	str	x20, [x19]
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_CHIP_VEGA10,8,3                ; @CHIP_VEGA10
	.no_dead_strip	_amdgpu_vm_fragment
.subsections_via_symbols
