	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_panel_mode_fixup        ## -- Begin function radeon_panel_mode_fixup
	.p2align	4, 0x90
_radeon_panel_mode_fixup:               ## @radeon_panel_mode_fixup
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %r15
	callq	_to_radeon_encoder
	movq	%rax, %rbx
	movq	(%r15), %rax
	movq	(%rax), %rdi
	movl	(%rbx), %r15d
	movl	4(%rbx), %eax
	subl	%eax, %r15d
	movl	8(%rbx), %edx
	movl	12(%rbx), %ecx
	subl	%ecx, %edx
	movq	%rdx, -56(%rbp)                 ## 8-byte Spill
	movl	16(%rbx), %r13d
	movl	20(%rbx), %r12d
	movl	24(%rbx), %edx
	subl	%r13d, %edx
	movl	%edx, -44(%rbp)                 ## 4-byte Spill
	subl	%eax, %r13d
	movl	28(%rbx), %eax
	subl	%r12d, %eax
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	subl	%ecx, %r12d
	movl	68(%rbx), %eax
	movl	%eax, 68(%r14)
	movl	64(%rbx), %eax
	movl	%eax, 64(%r14)
	movq	%rdi, -64(%rbp)                 ## 8-byte Spill
	callq	_ASIC_IS_AVIVO
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movl	4(%rbx), %eax
	movl	%eax, 4(%r14)
	movl	12(%rbx), %eax
	movl	%eax, 12(%r14)
LBB0_2:
	movl	4(%rbx), %eax
	leal	(%rax,%r15), %ecx
	movl	%ecx, (%r14)
	addl	%r13d, %eax
	movl	%eax, 16(%r14)
	addl	-44(%rbp), %eax                 ## 4-byte Folded Reload
	movl	%eax, 24(%r14)
	movl	12(%rbx), %eax
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	addl	%eax, %ecx
	movl	%ecx, 8(%r14)
	addl	%r12d, %eax
	movl	%eax, 20(%r14)
	addl	-48(%rbp), %eax                 ## 4-byte Folded Reload
	movl	%eax, 28(%r14)
	movq	_CRTC_INTERLACE_HALVE_V@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_drm_mode_set_crtcinfo
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	callq	_ASIC_IS_AVIVO
	testq	%rax, %rax
	je	LBB0_3
## %bb.4:
	movl	4(%rbx), %ecx
	movl	%ecx, 32(%r14)
	movl	12(%rbx), %eax
	movl	%eax, 36(%r14)
	jmp	LBB0_5
LBB0_3:
	movl	32(%r14), %ecx
	movl	36(%r14), %eax
LBB0_5:
	addl	%ecx, %r15d
	movl	%r15d, 40(%r14)
	addl	%ecx, %r13d
	movl	%r13d, 44(%r14)
	addl	-44(%rbp), %r13d                ## 4-byte Folded Reload
	movl	%r13d, 48(%r14)
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	addl	%eax, %ecx
	movl	%ecx, 52(%r14)
	addl	%eax, %r12d
	movl	%r12d, 56(%r14)
	addl	-48(%rbp), %r12d                ## 4-byte Folded Reload
	movl	%r12d, 60(%r14)
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CRTC_INTERLACE_HALVE_V,4,2     ## @CRTC_INTERLACE_HALVE_V
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_panel_mode_fixup        ; -- Begin function radeon_panel_mode_fixup
	.p2align	2
_radeon_panel_mode_fixup:               ; @radeon_panel_mode_fixup
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x1
	mov	x21, x0
	bl	_to_radeon_encoder
	mov	x20, x0
	ldr	x8, [x21]
	ldr	x21, [x8]
	ldp	w8, w9, [x0]
	sub	w22, w8, w9
	ldp	w8, w10, [x0, #16]
	sub	w24, w8, w9
	ldp	w9, w11, [x0, #24]
	sub	w27, w9, w8
	ldp	w8, w9, [x0, #8]
	sub	w26, w8, w9
	sub	w25, w10, w9
	sub	w23, w11, w10
	ldr	d0, [x0, #64]
	str	d0, [x19, #64]
	mov	x0, x21
	bl	_ASIC_IS_AVIVO
	cbz	x0, LBB0_2
; %bb.1:
	ldr	w8, [x20, #4]
	str	w8, [x19, #4]
	ldr	w8, [x20, #12]
	str	w8, [x19, #12]
LBB0_2:
	ldr	w8, [x20, #4]
	add	w9, w8, w22
	str	w9, [x19]
	add	w8, w8, w24
	add	w9, w8, w27
	ldr	w10, [x20, #12]
	add	w11, w10, w26
	str	w11, [x19, #8]
	add	w10, w10, w25
	add	w11, w10, w23
	stp	w8, w10, [x19, #16]
	stp	w9, w11, [x19, #24]
Lloh0:
	adrp	x8, _CRTC_INTERLACE_HALVE_V@GOTPAGE
Lloh1:
	ldr	x8, [x8, _CRTC_INTERLACE_HALVE_V@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_drm_mode_set_crtcinfo
	mov	x0, x21
	bl	_ASIC_IS_AVIVO
	cbz	x0, LBB0_4
; %bb.3:
	ldr	w9, [x20, #4]
	ldr	w8, [x20, #12]
	stp	w9, w8, [x19, #32]
	b	LBB0_5
LBB0_4:
	ldp	w9, w8, [x19, #32]
LBB0_5:
	add	w10, w9, w22
	add	w9, w9, w24
	add	w11, w9, w27
	stp	w10, w9, [x19, #40]
	add	w9, w8, w26
	stp	w11, w9, [x19, #48]
	add	w8, w8, w25
	add	w9, w8, w23
	stp	w8, w9, [x19, #56]
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_CRTC_INTERLACE_HALVE_V,4,2     ; @CRTC_INTERLACE_HALVE_V
.subsections_via_symbols
