	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function nv_common_get_clockgating_state
_nv_common_get_clockgating_state:       ## @nv_common_get_clockgating_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rsi, %r14
	movq	%rdi, %rbx
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movl	$0, (%r14)
LBB0_2:
	movq	(%rbx), %rax
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	*(%rax)
	movq	_HDP@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_mmHDP_CLK_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK@GOTPCREL(%rip), %rcx
	movq	_HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	movq	_HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	_HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	_HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	_HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	testl	%eax, %edx
	jne	LBB0_4
## %bb.3:
	movq	_AMD_CG_SUPPORT_HDP_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r14)
LBB0_4:
	movl	(%rbx), %edi
	movq	_mmHDP_MEM_POWER_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_6
## %bb.5:
	movq	_AMD_CG_SUPPORT_HDP_LS@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_6:
	movq	_HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_8
## %bb.7:
	movq	_AMD_CG_SUPPORT_HDP_DS@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_8:
	movq	_HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_11
## %bb.9:
	movq	_AMD_CG_SUPPORT_HDP_SD@GOTPCREL(%rip), %rax
LBB0_10:
	movl	(%rax), %eax
	orl	%eax, (%r14)
LBB0_11:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_HDP,4,2                        ## @HDP
	.comm	_mmHDP_CLK_CNTL,4,2             ## @mmHDP_CLK_CNTL
	.comm	_HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK,4,2 ## @HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK
	.comm	_HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK,4,2 ## @HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK
	.comm	_HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK,4,2 ## @HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK
	.comm	_HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK,4,2 ## @HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK
	.comm	_HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK,4,2 ## @HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK
	.comm	_HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK,4,2 ## @HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK
	.comm	_AMD_CG_SUPPORT_HDP_MGCG,4,2    ## @AMD_CG_SUPPORT_HDP_MGCG
	.comm	_mmHDP_MEM_POWER_CTRL,4,2       ## @mmHDP_MEM_POWER_CTRL
	.comm	_HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK,4,2 ## @HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK
	.comm	_AMD_CG_SUPPORT_HDP_LS,4,2      ## @AMD_CG_SUPPORT_HDP_LS
	.comm	_HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK,4,2 ## @HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK
	.comm	_AMD_CG_SUPPORT_HDP_DS,4,2      ## @AMD_CG_SUPPORT_HDP_DS
	.comm	_HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK,4,2 ## @HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK
	.comm	_AMD_CG_SUPPORT_HDP_SD,4,2      ## @AMD_CG_SUPPORT_HDP_SD
	.no_dead_strip	_nv_common_get_clockgating_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function nv_common_get_clockgating_state
_nv_common_get_clockgating_state:       ; @nv_common_get_clockgating_state
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x1
	mov	x20, x0
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_2
; %bb.1:
	str	wzr, [x19]
LBB0_2:
	ldr	x8, [x20]
	ldr	x8, [x8]
	mov	x0, x20
	mov	x1, x19
	blr	x8
Lloh0:
	adrp	x20, _HDP@GOTPAGE
Lloh1:
	ldr	x20, [x20, _HDP@GOTPAGEOFF]
	ldr	w0, [x20]
Lloh2:
	adrp	x8, _mmHDP_CLK_CNTL@GOTPAGE
Lloh3:
	ldr	x8, [x8, _mmHDP_CLK_CNTL@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh5:
	adrp	x8, _HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
Lloh8:
	adrp	x9, _HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK@GOTPAGE
Lloh9:
	ldr	x9, [x9, _HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh11:
	adrp	x9, _HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK@GOTPAGE
Lloh12:
	ldr	x9, [x9, _HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
Lloh14:
	adrp	x10, _HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK@GOTPAGE
Lloh15:
	ldr	x10, [x10, _HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh16:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh17:
	adrp	x9, _HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK@GOTPAGE
Lloh18:
	ldr	x9, [x9, _HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh20:
	adrp	x9, _HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK@GOTPAGE
Lloh21:
	ldr	x9, [x9, _HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	orr	w8, w8, w9
	tst	w8, w0
	b.ne	LBB0_4
; %bb.3:
Lloh23:
	adrp	x8, _AMD_CG_SUPPORT_HDP_MGCG@GOTPAGE
Lloh24:
	ldr	x8, [x8, _AMD_CG_SUPPORT_HDP_MGCG@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_4:
	ldr	w0, [x20]
Lloh26:
	adrp	x8, _mmHDP_MEM_POWER_CTRL@GOTPAGE
Lloh27:
	ldr	x8, [x8, _mmHDP_MEM_POWER_CTRL@GOTPAGEOFF]
Lloh28:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh29:
	adrp	x8, _HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK@GOTPAGE
Lloh30:
	ldr	x8, [x8, _HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK@GOTPAGEOFF]
Lloh31:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_6
; %bb.5:
Lloh32:
	adrp	x8, _AMD_CG_SUPPORT_HDP_LS@GOTPAGE
Lloh33:
	ldr	x8, [x8, _AMD_CG_SUPPORT_HDP_LS@GOTPAGEOFF]
	b	LBB0_10
LBB0_6:
Lloh34:
	adrp	x8, _HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK@GOTPAGE
Lloh35:
	ldr	x8, [x8, _HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK@GOTPAGEOFF]
Lloh36:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_8
; %bb.7:
Lloh37:
	adrp	x8, _AMD_CG_SUPPORT_HDP_DS@GOTPAGE
Lloh38:
	ldr	x8, [x8, _AMD_CG_SUPPORT_HDP_DS@GOTPAGEOFF]
	b	LBB0_10
LBB0_8:
Lloh39:
	adrp	x8, _HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK@GOTPAGE
Lloh40:
	ldr	x8, [x8, _HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_11
; %bb.9:
Lloh42:
	adrp	x8, _AMD_CG_SUPPORT_HDP_SD@GOTPAGE
Lloh43:
	ldr	x8, [x8, _AMD_CG_SUPPORT_HDP_SD@GOTPAGEOFF]
LBB0_10:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_11:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh42, Lloh43
	.cfi_endproc
                                        ; -- End function
	.comm	_HDP,4,2                        ; @HDP
	.comm	_mmHDP_CLK_CNTL,4,2             ; @mmHDP_CLK_CNTL
	.comm	_HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK,4,2 ; @HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK
	.comm	_HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK,4,2 ; @HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK
	.comm	_HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK,4,2 ; @HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK
	.comm	_HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK,4,2 ; @HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK
	.comm	_HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK,4,2 ; @HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK
	.comm	_HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK,4,2 ; @HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK
	.comm	_AMD_CG_SUPPORT_HDP_MGCG,4,2    ; @AMD_CG_SUPPORT_HDP_MGCG
	.comm	_mmHDP_MEM_POWER_CTRL,4,2       ; @mmHDP_MEM_POWER_CTRL
	.comm	_HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK,4,2 ; @HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK
	.comm	_AMD_CG_SUPPORT_HDP_LS,4,2      ; @AMD_CG_SUPPORT_HDP_LS
	.comm	_HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK,4,2 ; @HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK
	.comm	_AMD_CG_SUPPORT_HDP_DS,4,2      ; @AMD_CG_SUPPORT_HDP_DS
	.comm	_HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK,4,2 ; @HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK
	.comm	_AMD_CG_SUPPORT_HDP_SD,4,2      ; @AMD_CG_SUPPORT_HDP_SD
	.no_dead_strip	_nv_common_get_clockgating_state
.subsections_via_symbols
