	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function xgene_dma_setup_ring
_xgene_dma_setup_ring:                  ## @xgene_dma_setup_ring
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	56(%rdi), %r14
	movl	4(%rdi), %eax
	movl	52(%rdi), %r15d
	movq	_XGENE_DMA_RING_WQ_DESC_SIZE@GOTPCREL(%rip), %rcx
	cltd
	idivl	(%rcx)
	movl	%eax, (%rdi)
	callq	_xgene_dma_clr_ring_state
	movq	_XGENE_DMA_RING_TYPE_REGULAR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_XGENE_DMA_RING_TYPE_SET
	movq	8(%r12), %rax
	movq	_XGENE_DMA_RING_OWNER_DMA@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_2
## %bb.1:
	movq	%r14, %rdi
	callq	_XGENE_DMA_RING_RECOMBBUF_SET
	movq	%r14, %rdi
	callq	_XGENE_DMA_RING_RECOMTIMEOUTL_SET
	movq	%r14, %rdi
	callq	_XGENE_DMA_RING_RECOMTIMEOUTH_SET
LBB0_2:
	movq	%r14, %rdi
	callq	_XGENE_DMA_RING_SELTHRSH_SET
	movq	%r14, %rdi
	callq	_XGENE_DMA_RING_ACCEPTLERR_SET
	movq	%r14, %rdi
	callq	_XGENE_DMA_RING_COHERENT_SET
	movq	%r14, %rdi
	movl	%r15d, %esi
	callq	_XGENE_DMA_RING_ADDRL_SET
	movq	%r14, %rdi
	movl	%r15d, %esi
	callq	_XGENE_DMA_RING_ADDRH_SET
	movl	48(%r12), %esi
	movq	%r14, %rdi
	callq	_XGENE_DMA_RING_SIZE_SET
	movq	%r12, %rdi
	callq	_xgene_dma_wr_ring_state
	movl	44(%r12), %edi
	callq	_XGENE_DMA_RING_ID_SETUP
	movq	16(%r12), %rcx
	movq	_XGENE_DMA_RING_ID@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rsi
	addq	(%rcx), %rsi
	movq	%rax, %rdi
	callq	_iowrite32
	movl	40(%r12), %edi
	callq	_XGENE_DMA_RING_ID_BUF_SETUP
	movq	16(%r12), %rcx
	movq	_XGENE_DMA_RING_ID_BUF@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rsi
	addq	(%rcx), %rsi
	movq	%rax, %rdi
	callq	_iowrite32
	movq	8(%r12), %rax
	movq	_XGENE_DMA_RING_OWNER_CPU@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_7
## %bb.3:
	cmpl	$0, (%r12)
	je	LBB0_6
## %bb.4:
	xorl	%ebx, %ebx
	movq	_XGENE_DMA_DESC_EMPTY_SIGNATURE@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	movq	32(%r12), %r15
	movl	(%r14), %edi
	callq	_cpu_to_le64
	movl	%eax, (%r15,%rbx,4)
	incq	%rbx
	movslq	(%r12), %rax
	cmpq	%rax, %rbx
	jb	LBB0_5
LBB0_6:
	movq	16(%r12), %rax
	movq	_XGENE_DMA_RING_NE_INT_MODE@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	addq	(%rax), %rdi
	callq	_ioread32
	movq	%rax, %r14
	movl	24(%r12), %esi
	movq	%rax, %rdi
	callq	_XGENE_DMA_RING_NE_INT_MODE_SET
	movq	16(%r12), %rax
	movq	(%rbx), %rsi
	addq	(%rax), %rsi
	movq	%r14, %rdi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_iowrite32                      ## TAILCALL
LBB0_7:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_XGENE_DMA_RING_WQ_DESC_SIZE,4,2 ## @XGENE_DMA_RING_WQ_DESC_SIZE
	.comm	_XGENE_DMA_RING_TYPE_REGULAR,4,2 ## @XGENE_DMA_RING_TYPE_REGULAR
	.comm	_XGENE_DMA_RING_OWNER_DMA,8,3   ## @XGENE_DMA_RING_OWNER_DMA
	.comm	_XGENE_DMA_RING_ID,8,3          ## @XGENE_DMA_RING_ID
	.comm	_XGENE_DMA_RING_ID_BUF,8,3      ## @XGENE_DMA_RING_ID_BUF
	.comm	_XGENE_DMA_RING_OWNER_CPU,8,3   ## @XGENE_DMA_RING_OWNER_CPU
	.comm	_XGENE_DMA_DESC_EMPTY_SIGNATURE,4,2 ## @XGENE_DMA_DESC_EMPTY_SIGNATURE
	.comm	_XGENE_DMA_RING_NE_INT_MODE,8,3 ## @XGENE_DMA_RING_NE_INT_MODE
	.no_dead_strip	_xgene_dma_setup_ring
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function xgene_dma_setup_ring
_xgene_dma_setup_ring:                  ; @xgene_dma_setup_ring
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x20, [x0, #56]
	ldr	w21, [x0, #52]
	ldr	w8, [x0, #4]
Lloh0:
	adrp	x9, _XGENE_DMA_RING_WQ_DESC_SIZE@GOTPAGE
Lloh1:
	ldr	x9, [x9, _XGENE_DMA_RING_WQ_DESC_SIZE@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	sdiv	w8, w8, w9
	str	w8, [x0]
	bl	_xgene_dma_clr_ring_state
Lloh3:
	adrp	x8, _XGENE_DMA_RING_TYPE_REGULAR@GOTPAGE
Lloh4:
	ldr	x8, [x8, _XGENE_DMA_RING_TYPE_REGULAR@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_XGENE_DMA_RING_TYPE_SET
	ldr	x8, [x19, #8]
Lloh6:
	adrp	x9, _XGENE_DMA_RING_OWNER_DMA@GOTPAGE
Lloh7:
	ldr	x9, [x9, _XGENE_DMA_RING_OWNER_DMA@GOTPAGEOFF]
Lloh8:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_2
; %bb.1:
	mov	x0, x20
	bl	_XGENE_DMA_RING_RECOMBBUF_SET
	mov	x0, x20
	bl	_XGENE_DMA_RING_RECOMTIMEOUTL_SET
	mov	x0, x20
	bl	_XGENE_DMA_RING_RECOMTIMEOUTH_SET
LBB0_2:
	mov	x0, x20
	bl	_XGENE_DMA_RING_SELTHRSH_SET
	mov	x0, x20
	bl	_XGENE_DMA_RING_ACCEPTLERR_SET
	mov	x0, x20
	bl	_XGENE_DMA_RING_COHERENT_SET
	mov	x0, x20
	mov	x1, x21
	bl	_XGENE_DMA_RING_ADDRL_SET
	mov	x0, x20
	mov	x1, x21
	bl	_XGENE_DMA_RING_ADDRH_SET
	ldr	w1, [x19, #48]
	mov	x0, x20
	bl	_XGENE_DMA_RING_SIZE_SET
	mov	x0, x19
	bl	_xgene_dma_wr_ring_state
	ldr	w0, [x19, #44]
	bl	_XGENE_DMA_RING_ID_SETUP
	ldr	x8, [x19, #16]
	ldr	x8, [x8]
Lloh9:
	adrp	x9, _XGENE_DMA_RING_ID@GOTPAGE
Lloh10:
	ldr	x9, [x9, _XGENE_DMA_RING_ID@GOTPAGEOFF]
Lloh11:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_iowrite32
	ldr	w0, [x19, #40]
	bl	_XGENE_DMA_RING_ID_BUF_SETUP
	ldr	x8, [x19, #16]
	ldr	x8, [x8]
Lloh12:
	adrp	x9, _XGENE_DMA_RING_ID_BUF@GOTPAGE
Lloh13:
	ldr	x9, [x9, _XGENE_DMA_RING_ID_BUF@GOTPAGEOFF]
Lloh14:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_iowrite32
	ldr	x8, [x19, #8]
Lloh15:
	adrp	x9, _XGENE_DMA_RING_OWNER_CPU@GOTPAGE
Lloh16:
	ldr	x9, [x9, _XGENE_DMA_RING_OWNER_CPU@GOTPAGEOFF]
Lloh17:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_7
; %bb.3:
	ldr	w8, [x19]
	cbz	w8, LBB0_6
; %bb.4:
	mov	x20, #0
Lloh18:
	adrp	x21, _XGENE_DMA_DESC_EMPTY_SIGNATURE@GOTPAGE
Lloh19:
	ldr	x21, [x21, _XGENE_DMA_DESC_EMPTY_SIGNATURE@GOTPAGEOFF]
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x22, [x19, #32]
	ldr	w0, [x21]
	bl	_cpu_to_le64
	str	w0, [x22, x20, lsl #2]
	add	x20, x20, #1
	ldrsw	x8, [x19]
	cmp	x20, x8
	b.lo	LBB0_5
LBB0_6:
	ldr	x8, [x19, #16]
	ldr	x8, [x8]
Lloh20:
	adrp	x21, _XGENE_DMA_RING_NE_INT_MODE@GOTPAGE
Lloh21:
	ldr	x21, [x21, _XGENE_DMA_RING_NE_INT_MODE@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_ioread32
	mov	x20, x0
	ldr	w1, [x19, #24]
	bl	_XGENE_DMA_RING_NE_INT_MODE_SET
	ldr	x8, [x19, #16]
	ldr	x8, [x8]
	ldr	x9, [x21]
	add	x1, x9, x8
	mov	x0, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_iowrite32
LBB0_7:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh20, Lloh21
	.cfi_endproc
                                        ; -- End function
	.comm	_XGENE_DMA_RING_WQ_DESC_SIZE,4,2 ; @XGENE_DMA_RING_WQ_DESC_SIZE
	.comm	_XGENE_DMA_RING_TYPE_REGULAR,4,2 ; @XGENE_DMA_RING_TYPE_REGULAR
	.comm	_XGENE_DMA_RING_OWNER_DMA,8,3   ; @XGENE_DMA_RING_OWNER_DMA
	.comm	_XGENE_DMA_RING_ID,8,3          ; @XGENE_DMA_RING_ID
	.comm	_XGENE_DMA_RING_ID_BUF,8,3      ; @XGENE_DMA_RING_ID_BUF
	.comm	_XGENE_DMA_RING_OWNER_CPU,8,3   ; @XGENE_DMA_RING_OWNER_CPU
	.comm	_XGENE_DMA_DESC_EMPTY_SIGNATURE,4,2 ; @XGENE_DMA_DESC_EMPTY_SIGNATURE
	.comm	_XGENE_DMA_RING_NE_INT_MODE,8,3 ; @XGENE_DMA_RING_NE_INT_MODE
	.no_dead_strip	_xgene_dma_setup_ring
.subsections_via_symbols
