	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function si_dpm_set_power_state
_si_dpm_set_power_state:                ## @si_dpm_set_power_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	callq	_evergreen_get_pi
	movq	%rax, %r13
	movq	%r12, %rdi
	callq	_si_disable_ulv
	testl	%eax, %eax
	je	LBB0_2
## %bb.1:
	movl	%eax, %ebx
	leaq	L_.str(%rip), %r14
	jmp	LBB0_34
LBB0_2:
	movq	%r12, %rdi
	callq	_si_restrict_performance_levels_before_switch
	testl	%eax, %eax
	je	LBB0_4
## %bb.3:
	movl	%eax, %ebx
	leaq	L_.str.1(%rip), %r14
	jmp	LBB0_34
LBB0_4:
	leaq	20(%r13), %r14
	movq	%r13, %r15
	addq	$16, %r15
	cmpq	$0, (%r13)
	je	LBB0_6
## %bb.5:
	movq	%r12, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	callq	_si_request_link_speed_change_before_state_change
LBB0_6:
	movq	%r12, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	callq	_ni_set_uvd_clock_before_set_eng_clock
	movq	%r12, %rdi
	movq	%r14, %rsi
	xorl	%edx, %edx
	callq	_si_enable_power_containment
	movl	%eax, %ebx
	leaq	L_.str.2(%rip), %rax
	testl	%ebx, %ebx
	je	LBB0_8
## %bb.7:
	movq	%rax, %r14
	jmp	LBB0_34
LBB0_8:
	movq	%r12, %rdi
	movq	%r14, %rsi
	xorl	%edx, %edx
	callq	_si_enable_smc_cac
	movl	%eax, %ebx
	movq	%r14, %rax
	leaq	L_.str.3(%rip), %r14
	testl	%ebx, %ebx
	jne	LBB0_34
## %bb.9:
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movq	%r12, %rdi
	callq	_si_halt_smc
	testl	%eax, %eax
	je	LBB0_11
## %bb.10:
	movl	%eax, %ebx
	leaq	L_.str.4(%rip), %r14
	jmp	LBB0_34
LBB0_11:
	movq	%r12, %rdi
	movq	-48(%rbp), %rsi                 ## 8-byte Reload
	callq	_si_upload_sw_state
	testl	%eax, %eax
	je	LBB0_13
## %bb.12:
	movl	%eax, %ebx
	leaq	L_.str.5(%rip), %r14
	jmp	LBB0_34
LBB0_13:
	movq	%r12, %rdi
	callq	_si_upload_smc_data
	testl	%eax, %eax
	je	LBB0_15
## %bb.14:
	movl	%eax, %ebx
	leaq	L_.str.6(%rip), %r14
	jmp	LBB0_34
LBB0_15:
	movq	%r12, %rdi
	callq	_si_upload_ulv_state
	testl	%eax, %eax
	je	LBB0_17
## %bb.16:
	movl	%eax, %ebx
	leaq	L_.str.7(%rip), %r14
LBB0_34:
	movq	%r14, %rdi
	callq	_DRM_ERROR
LBB0_35:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_17:
	cmpq	$0, 8(%r13)
	je	LBB0_20
## %bb.18:
	movq	%r12, %rdi
	movq	-48(%rbp), %rsi                 ## 8-byte Reload
	callq	_si_upload_mc_reg_table
	testl	%eax, %eax
	je	LBB0_20
## %bb.19:
	movl	%eax, %ebx
	leaq	L_.str.8(%rip), %r14
	jmp	LBB0_34
LBB0_20:
	movq	%r12, %rdi
	movq	-48(%rbp), %rsi                 ## 8-byte Reload
	callq	_si_program_memory_timing_parameters
	testl	%eax, %eax
	je	LBB0_22
## %bb.21:
	movl	%eax, %ebx
	leaq	L_.str.9(%rip), %r14
	jmp	LBB0_34
LBB0_22:
	movq	%r12, %rdi
	movq	-48(%rbp), %rsi                 ## 8-byte Reload
	movq	%r15, %rdx
	callq	_si_set_pcie_lane_width_in_smc
	movq	%r12, %rdi
	callq	_si_resume_smc
	testl	%eax, %eax
	je	LBB0_24
## %bb.23:
	movl	%eax, %ebx
	leaq	L_.str.10(%rip), %r14
	jmp	LBB0_34
LBB0_24:
	movq	%r12, %rdi
	callq	_si_set_sw_state
	testl	%eax, %eax
	je	LBB0_26
## %bb.25:
	movl	%eax, %ebx
	leaq	L_.str.11(%rip), %r14
	jmp	LBB0_34
LBB0_26:
	movq	%r12, %rdi
	movq	-48(%rbp), %rsi                 ## 8-byte Reload
	movq	%r15, %rdx
	callq	_ni_set_uvd_clock_after_set_eng_clock
	cmpq	$0, (%r13)
	je	LBB0_28
## %bb.27:
	movq	%r12, %rdi
	movq	-48(%rbp), %rsi                 ## 8-byte Reload
	movq	%r15, %rdx
	callq	_si_notify_link_speed_change_after_state_change
LBB0_28:
	movq	%r12, %rdi
	movq	-48(%rbp), %rsi                 ## 8-byte Reload
	callq	_si_set_power_state_conditionally_enable_ulv
	testl	%eax, %eax
	je	LBB0_30
## %bb.29:
	movl	%eax, %ebx
	leaq	L_.str.12(%rip), %r14
	jmp	LBB0_34
LBB0_30:
	movq	%r12, %rdi
	movq	-48(%rbp), %rsi                 ## 8-byte Reload
	movl	$1, %edx
	callq	_si_enable_smc_cac
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_34
## %bb.31:
	movq	%r12, %rdi
	movq	-48(%rbp), %rsi                 ## 8-byte Reload
	movl	$1, %edx
	callq	_si_enable_power_containment
	movl	%eax, %ebx
	leaq	L_.str.2(%rip), %r14
	testl	%eax, %eax
	jne	LBB0_34
## %bb.32:
	movq	%r12, %rdi
	callq	_si_power_control_set_level
	testl	%eax, %eax
	je	LBB0_36
## %bb.33:
	movl	%eax, %ebx
	leaq	L_.str.13(%rip), %r14
	jmp	LBB0_34
LBB0_36:
	xorl	%ebx, %ebx
	jmp	LBB0_35
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"si_disable_ulv failed\n"

L_.str.1:                               ## @.str.1
	.asciz	"si_restrict_performance_levels_before_switch failed\n"

L_.str.2:                               ## @.str.2
	.asciz	"si_enable_power_containment failed\n"

L_.str.3:                               ## @.str.3
	.asciz	"si_enable_smc_cac failed\n"

L_.str.4:                               ## @.str.4
	.asciz	"si_halt_smc failed\n"

L_.str.5:                               ## @.str.5
	.asciz	"si_upload_sw_state failed\n"

L_.str.6:                               ## @.str.6
	.asciz	"si_upload_smc_data failed\n"

L_.str.7:                               ## @.str.7
	.asciz	"si_upload_ulv_state failed\n"

L_.str.8:                               ## @.str.8
	.asciz	"si_upload_mc_reg_table failed\n"

L_.str.9:                               ## @.str.9
	.asciz	"si_program_memory_timing_parameters failed\n"

L_.str.10:                              ## @.str.10
	.asciz	"si_resume_smc failed\n"

L_.str.11:                              ## @.str.11
	.asciz	"si_set_sw_state failed\n"

L_.str.12:                              ## @.str.12
	.asciz	"si_set_power_state_conditionally_enable_ulv failed\n"

L_.str.13:                              ## @.str.13
	.asciz	"si_power_control_set_level failed\n"

	.no_dead_strip	_si_dpm_set_power_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function si_dpm_set_power_state
_si_dpm_set_power_state:                ; @si_dpm_set_power_state
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	bl	_evergreen_get_pi
	mov	x22, x0
	mov	x0, x19
	bl	_si_disable_ulv
	cbz	w0, LBB0_2
; %bb.1:
	mov	x20, x0
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	b	LBB0_18
LBB0_2:
	mov	x0, x19
	bl	_si_restrict_performance_levels_before_switch
	cbz	w0, LBB0_4
; %bb.3:
	mov	x20, x0
Lloh2:
	adrp	x0, l_.str.1@PAGE
Lloh3:
	add	x0, x0, l_.str.1@PAGEOFF
	b	LBB0_18
LBB0_4:
	add	x21, x22, #20
	add	x23, x22, #16
	ldr	x8, [x22]
	cbz	x8, LBB0_6
; %bb.5:
	mov	x0, x19
	mov	x1, x21
	mov	x2, x23
	bl	_si_request_link_speed_change_before_state_change
LBB0_6:
	mov	x0, x19
	mov	x1, x21
	mov	x2, x23
	bl	_ni_set_uvd_clock_before_set_eng_clock
	mov	x0, x19
	mov	x1, x21
	mov	w2, #0
	bl	_si_enable_power_containment
	cbz	w0, LBB0_8
LBB0_7:
	mov	x20, x0
Lloh4:
	adrp	x0, l_.str.2@PAGE
Lloh5:
	add	x0, x0, l_.str.2@PAGEOFF
	b	LBB0_18
LBB0_8:
	mov	x0, x19
	mov	x1, x21
	mov	w2, #0
	bl	_si_enable_smc_cac
	cbz	w0, LBB0_10
LBB0_9:
	mov	x20, x0
Lloh6:
	adrp	x0, l_.str.3@PAGE
Lloh7:
	add	x0, x0, l_.str.3@PAGEOFF
	b	LBB0_18
LBB0_10:
	mov	x0, x19
	bl	_si_halt_smc
	cbz	w0, LBB0_12
; %bb.11:
	mov	x20, x0
Lloh8:
	adrp	x0, l_.str.4@PAGE
Lloh9:
	add	x0, x0, l_.str.4@PAGEOFF
	b	LBB0_18
LBB0_12:
	mov	x0, x19
	mov	x1, x21
	bl	_si_upload_sw_state
	cbz	w0, LBB0_14
; %bb.13:
	mov	x20, x0
Lloh10:
	adrp	x0, l_.str.5@PAGE
Lloh11:
	add	x0, x0, l_.str.5@PAGEOFF
	b	LBB0_18
LBB0_14:
	mov	x0, x19
	bl	_si_upload_smc_data
	cbz	w0, LBB0_16
; %bb.15:
	mov	x20, x0
Lloh12:
	adrp	x0, l_.str.6@PAGE
Lloh13:
	add	x0, x0, l_.str.6@PAGEOFF
	b	LBB0_18
LBB0_16:
	mov	x0, x19
	bl	_si_upload_ulv_state
	cbz	w0, LBB0_20
; %bb.17:
	mov	x20, x0
Lloh14:
	adrp	x0, l_.str.7@PAGE
Lloh15:
	add	x0, x0, l_.str.7@PAGEOFF
LBB0_18:
	bl	_DRM_ERROR
LBB0_19:
	mov	x0, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_20:
	ldr	x8, [x22, #8]
	cbz	x8, LBB0_23
; %bb.21:
	mov	x0, x19
	mov	x1, x21
	bl	_si_upload_mc_reg_table
	cbz	w0, LBB0_23
; %bb.22:
	mov	x20, x0
Lloh16:
	adrp	x0, l_.str.8@PAGE
Lloh17:
	add	x0, x0, l_.str.8@PAGEOFF
	b	LBB0_18
LBB0_23:
	mov	x0, x19
	mov	x1, x21
	bl	_si_program_memory_timing_parameters
	cbz	w0, LBB0_25
; %bb.24:
	mov	x20, x0
Lloh18:
	adrp	x0, l_.str.9@PAGE
Lloh19:
	add	x0, x0, l_.str.9@PAGEOFF
	b	LBB0_18
LBB0_25:
	mov	x0, x19
	mov	x1, x21
	mov	x2, x23
	bl	_si_set_pcie_lane_width_in_smc
	mov	x0, x19
	bl	_si_resume_smc
	cbz	w0, LBB0_27
; %bb.26:
	mov	x20, x0
Lloh20:
	adrp	x0, l_.str.10@PAGE
Lloh21:
	add	x0, x0, l_.str.10@PAGEOFF
	b	LBB0_18
LBB0_27:
	mov	x0, x19
	bl	_si_set_sw_state
	cbz	w0, LBB0_29
; %bb.28:
	mov	x20, x0
Lloh22:
	adrp	x0, l_.str.11@PAGE
Lloh23:
	add	x0, x0, l_.str.11@PAGEOFF
	b	LBB0_18
LBB0_29:
	mov	x0, x19
	mov	x1, x21
	mov	x2, x23
	bl	_ni_set_uvd_clock_after_set_eng_clock
	ldr	x8, [x22]
	cbz	x8, LBB0_31
; %bb.30:
	mov	x0, x19
	mov	x1, x21
	mov	x2, x23
	bl	_si_notify_link_speed_change_after_state_change
LBB0_31:
	mov	x0, x19
	mov	x1, x21
	bl	_si_set_power_state_conditionally_enable_ulv
	cbz	w0, LBB0_33
; %bb.32:
	mov	x20, x0
Lloh24:
	adrp	x0, l_.str.12@PAGE
Lloh25:
	add	x0, x0, l_.str.12@PAGEOFF
	b	LBB0_18
LBB0_33:
	mov	x0, x19
	mov	x1, x21
	mov	w2, #1
	bl	_si_enable_smc_cac
	cbnz	w0, LBB0_9
; %bb.34:
	mov	x0, x19
	mov	x1, x21
	mov	w2, #1
	bl	_si_enable_power_containment
	cbnz	w0, LBB0_7
; %bb.35:
	mov	x0, x19
	bl	_si_power_control_set_level
	mov	x20, x0
	cbz	w0, LBB0_19
; %bb.36:
Lloh26:
	adrp	x0, l_.str.13@PAGE
Lloh27:
	add	x0, x0, l_.str.13@PAGEOFF
	b	LBB0_18
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpAdd	Lloh12, Lloh13
	.loh AdrpAdd	Lloh14, Lloh15
	.loh AdrpAdd	Lloh16, Lloh17
	.loh AdrpAdd	Lloh18, Lloh19
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpAdd	Lloh22, Lloh23
	.loh AdrpAdd	Lloh24, Lloh25
	.loh AdrpAdd	Lloh26, Lloh27
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"si_disable_ulv failed\n"

l_.str.1:                               ; @.str.1
	.asciz	"si_restrict_performance_levels_before_switch failed\n"

l_.str.2:                               ; @.str.2
	.asciz	"si_enable_power_containment failed\n"

l_.str.3:                               ; @.str.3
	.asciz	"si_enable_smc_cac failed\n"

l_.str.4:                               ; @.str.4
	.asciz	"si_halt_smc failed\n"

l_.str.5:                               ; @.str.5
	.asciz	"si_upload_sw_state failed\n"

l_.str.6:                               ; @.str.6
	.asciz	"si_upload_smc_data failed\n"

l_.str.7:                               ; @.str.7
	.asciz	"si_upload_ulv_state failed\n"

l_.str.8:                               ; @.str.8
	.asciz	"si_upload_mc_reg_table failed\n"

l_.str.9:                               ; @.str.9
	.asciz	"si_program_memory_timing_parameters failed\n"

l_.str.10:                              ; @.str.10
	.asciz	"si_resume_smc failed\n"

l_.str.11:                              ; @.str.11
	.asciz	"si_set_sw_state failed\n"

l_.str.12:                              ; @.str.12
	.asciz	"si_set_power_state_conditionally_enable_ulv failed\n"

l_.str.13:                              ; @.str.13
	.asciz	"si_power_control_set_level failed\n"

	.no_dead_strip	_si_dpm_set_power_state
.subsections_via_symbols
