	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tda998x_reset
_tda998x_reset:                         ## @tda998x_reset
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	_REG_SOFTRESET@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	_SOFTRESET_AUDIO@GOTPCREL(%rip), %rax
	movq	_SOFTRESET_I2C_MASTER@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	callq	_reg_write
	movl	$50, %edi
	callq	_msleep
	movl	(%r14), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_reg_write
	movl	$50, %edi
	callq	_msleep
	movq	_REG_MAIN_CNTRL0@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	_MAIN_CNTRL0_SR@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	movq	%rbx, %rdi
	callq	_reg_set
	movl	(%r14), %esi
	movl	(%r15), %edx
	movq	%rbx, %rdi
	callq	_reg_clear
	movq	_REG_PLL_SERIAL_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_reg_write
	movq	_REG_PLL_SERIAL_2@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	$1, %edi
	callq	_PLL_SERIAL_2_SRL_NOSC
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_reg_write
	movq	_REG_PLL_SERIAL_3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_reg_write
	movq	_REG_SERIALIZER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_reg_write
	movq	_REG_BUFFER_OUT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_reg_write
	movq	_REG_PLL_SCG1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_reg_write
	movq	_REG_AUDIO_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AUDIO_DIV_SERCLK_8@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_reg_write
	movq	_REG_SEL_CLK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SEL_CLK_SEL_CLK1@GOTPCREL(%rip), %rax
	movq	_SEL_CLK_ENA_SC_CLK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_reg_write
	movq	_REG_PLL_SCGN1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$250, %edx
	callq	_reg_write
	movq	_REG_PLL_SCGN2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_reg_write
	movq	_REG_PLL_SCGR1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$91, %edx
	callq	_reg_write
	movq	_REG_PLL_SCGR2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_reg_write
	movq	_REG_PLL_SCG2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$16, %edx
	callq	_reg_write
	movq	_REG_MUX_VP_VIP_OUT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$36, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_reg_write                      ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_REG_SOFTRESET,4,2              ## @REG_SOFTRESET
	.comm	_SOFTRESET_AUDIO,4,2            ## @SOFTRESET_AUDIO
	.comm	_SOFTRESET_I2C_MASTER,4,2       ## @SOFTRESET_I2C_MASTER
	.comm	_REG_MAIN_CNTRL0,4,2            ## @REG_MAIN_CNTRL0
	.comm	_MAIN_CNTRL0_SR,4,2             ## @MAIN_CNTRL0_SR
	.comm	_REG_PLL_SERIAL_1,4,2           ## @REG_PLL_SERIAL_1
	.comm	_REG_PLL_SERIAL_2,4,2           ## @REG_PLL_SERIAL_2
	.comm	_REG_PLL_SERIAL_3,4,2           ## @REG_PLL_SERIAL_3
	.comm	_REG_SERIALIZER,4,2             ## @REG_SERIALIZER
	.comm	_REG_BUFFER_OUT,4,2             ## @REG_BUFFER_OUT
	.comm	_REG_PLL_SCG1,4,2               ## @REG_PLL_SCG1
	.comm	_REG_AUDIO_DIV,4,2              ## @REG_AUDIO_DIV
	.comm	_AUDIO_DIV_SERCLK_8,4,2         ## @AUDIO_DIV_SERCLK_8
	.comm	_REG_SEL_CLK,4,2                ## @REG_SEL_CLK
	.comm	_SEL_CLK_SEL_CLK1,4,2           ## @SEL_CLK_SEL_CLK1
	.comm	_SEL_CLK_ENA_SC_CLK,4,2         ## @SEL_CLK_ENA_SC_CLK
	.comm	_REG_PLL_SCGN1,4,2              ## @REG_PLL_SCGN1
	.comm	_REG_PLL_SCGN2,4,2              ## @REG_PLL_SCGN2
	.comm	_REG_PLL_SCGR1,4,2              ## @REG_PLL_SCGR1
	.comm	_REG_PLL_SCGR2,4,2              ## @REG_PLL_SCGR2
	.comm	_REG_PLL_SCG2,4,2               ## @REG_PLL_SCG2
	.comm	_REG_MUX_VP_VIP_OUT,4,2         ## @REG_MUX_VP_VIP_OUT
	.no_dead_strip	_tda998x_reset
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tda998x_reset
_tda998x_reset:                         ; @tda998x_reset
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x20, _REG_SOFTRESET@GOTPAGE
Lloh1:
	ldr	x20, [x20, _REG_SOFTRESET@GOTPAGEOFF]
Lloh2:
	adrp	x8, _SOFTRESET_AUDIO@GOTPAGE
Lloh3:
	ldr	x8, [x8, _SOFTRESET_AUDIO@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh4:
	ldr	w8, [x8]
Lloh5:
	adrp	x9, _SOFTRESET_I2C_MASTER@GOTPAGE
Lloh6:
	ldr	x9, [x9, _SOFTRESET_I2C_MASTER@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	orr	w2, w9, w8
	bl	_reg_write
	mov	w0, #50
	bl	_msleep
	ldr	w1, [x20]
	mov	x0, x19
	mov	w2, #0
	bl	_reg_write
	mov	w0, #50
	bl	_msleep
Lloh8:
	adrp	x20, _REG_MAIN_CNTRL0@GOTPAGE
Lloh9:
	ldr	x20, [x20, _REG_MAIN_CNTRL0@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh10:
	adrp	x21, _MAIN_CNTRL0_SR@GOTPAGE
Lloh11:
	ldr	x21, [x21, _MAIN_CNTRL0_SR@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	x0, x19
	bl	_reg_set
	ldr	w1, [x20]
	ldr	w2, [x21]
	mov	x0, x19
	bl	_reg_clear
Lloh12:
	adrp	x8, _REG_PLL_SERIAL_1@GOTPAGE
Lloh13:
	ldr	x8, [x8, _REG_PLL_SERIAL_1@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_reg_write
Lloh15:
	adrp	x8, _REG_PLL_SERIAL_2@GOTPAGE
Lloh16:
	ldr	x8, [x8, _REG_PLL_SERIAL_2@GOTPAGEOFF]
Lloh17:
	ldr	w20, [x8]
	mov	w0, #1
	bl	_PLL_SERIAL_2_SRL_NOSC
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_reg_write
Lloh18:
	adrp	x8, _REG_PLL_SERIAL_3@GOTPAGE
Lloh19:
	ldr	x8, [x8, _REG_PLL_SERIAL_3@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_reg_write
Lloh21:
	adrp	x8, _REG_SERIALIZER@GOTPAGE
Lloh22:
	ldr	x8, [x8, _REG_SERIALIZER@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_reg_write
Lloh24:
	adrp	x8, _REG_BUFFER_OUT@GOTPAGE
Lloh25:
	ldr	x8, [x8, _REG_BUFFER_OUT@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_reg_write
Lloh27:
	adrp	x8, _REG_PLL_SCG1@GOTPAGE
Lloh28:
	ldr	x8, [x8, _REG_PLL_SCG1@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_reg_write
Lloh30:
	adrp	x8, _REG_AUDIO_DIV@GOTPAGE
Lloh31:
	ldr	x8, [x8, _REG_AUDIO_DIV@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
Lloh33:
	adrp	x8, _AUDIO_DIV_SERCLK_8@GOTPAGE
Lloh34:
	ldr	x8, [x8, _AUDIO_DIV_SERCLK_8@GOTPAGEOFF]
Lloh35:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_reg_write
Lloh36:
	adrp	x8, _REG_SEL_CLK@GOTPAGE
Lloh37:
	ldr	x8, [x8, _REG_SEL_CLK@GOTPAGEOFF]
Lloh38:
	adrp	x9, _SEL_CLK_SEL_CLK1@GOTPAGE
Lloh39:
	ldr	x9, [x9, _SEL_CLK_SEL_CLK1@GOTPAGEOFF]
Lloh40:
	ldr	w1, [x8]
Lloh41:
	ldr	w8, [x9]
Lloh42:
	adrp	x9, _SEL_CLK_ENA_SC_CLK@GOTPAGE
Lloh43:
	ldr	x9, [x9, _SEL_CLK_ENA_SC_CLK@GOTPAGEOFF]
Lloh44:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_reg_write
Lloh45:
	adrp	x8, _REG_PLL_SCGN1@GOTPAGE
Lloh46:
	ldr	x8, [x8, _REG_PLL_SCGN1@GOTPAGEOFF]
Lloh47:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #250
	bl	_reg_write
Lloh48:
	adrp	x8, _REG_PLL_SCGN2@GOTPAGE
Lloh49:
	ldr	x8, [x8, _REG_PLL_SCGN2@GOTPAGEOFF]
Lloh50:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_reg_write
Lloh51:
	adrp	x8, _REG_PLL_SCGR1@GOTPAGE
Lloh52:
	ldr	x8, [x8, _REG_PLL_SCGR1@GOTPAGEOFF]
Lloh53:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #91
	bl	_reg_write
Lloh54:
	adrp	x8, _REG_PLL_SCGR2@GOTPAGE
Lloh55:
	ldr	x8, [x8, _REG_PLL_SCGR2@GOTPAGEOFF]
Lloh56:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_reg_write
Lloh57:
	adrp	x8, _REG_PLL_SCG2@GOTPAGE
Lloh58:
	ldr	x8, [x8, _REG_PLL_SCG2@GOTPAGEOFF]
Lloh59:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #16
	bl	_reg_write
Lloh60:
	adrp	x8, _REG_MUX_VP_VIP_OUT@GOTPAGE
Lloh61:
	ldr	x8, [x8, _REG_MUX_VP_VIP_OUT@GOTPAGEOFF]
Lloh62:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #36
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_reg_write
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh40
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_REG_SOFTRESET,4,2              ; @REG_SOFTRESET
	.comm	_SOFTRESET_AUDIO,4,2            ; @SOFTRESET_AUDIO
	.comm	_SOFTRESET_I2C_MASTER,4,2       ; @SOFTRESET_I2C_MASTER
	.comm	_REG_MAIN_CNTRL0,4,2            ; @REG_MAIN_CNTRL0
	.comm	_MAIN_CNTRL0_SR,4,2             ; @MAIN_CNTRL0_SR
	.comm	_REG_PLL_SERIAL_1,4,2           ; @REG_PLL_SERIAL_1
	.comm	_REG_PLL_SERIAL_2,4,2           ; @REG_PLL_SERIAL_2
	.comm	_REG_PLL_SERIAL_3,4,2           ; @REG_PLL_SERIAL_3
	.comm	_REG_SERIALIZER,4,2             ; @REG_SERIALIZER
	.comm	_REG_BUFFER_OUT,4,2             ; @REG_BUFFER_OUT
	.comm	_REG_PLL_SCG1,4,2               ; @REG_PLL_SCG1
	.comm	_REG_AUDIO_DIV,4,2              ; @REG_AUDIO_DIV
	.comm	_AUDIO_DIV_SERCLK_8,4,2         ; @AUDIO_DIV_SERCLK_8
	.comm	_REG_SEL_CLK,4,2                ; @REG_SEL_CLK
	.comm	_SEL_CLK_SEL_CLK1,4,2           ; @SEL_CLK_SEL_CLK1
	.comm	_SEL_CLK_ENA_SC_CLK,4,2         ; @SEL_CLK_ENA_SC_CLK
	.comm	_REG_PLL_SCGN1,4,2              ; @REG_PLL_SCGN1
	.comm	_REG_PLL_SCGN2,4,2              ; @REG_PLL_SCGN2
	.comm	_REG_PLL_SCGR1,4,2              ; @REG_PLL_SCGR1
	.comm	_REG_PLL_SCGR2,4,2              ; @REG_PLL_SCGR2
	.comm	_REG_PLL_SCG2,4,2               ; @REG_PLL_SCG2
	.comm	_REG_MUX_VP_VIP_OUT,4,2         ; @REG_MUX_VP_VIP_OUT
	.no_dead_strip	_tda998x_reset
.subsections_via_symbols
