	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v1_0_dec_ring_emit_fence
_vcn_v1_0_dec_ring_emit_fence:          ## @vcn_v1_0_dec_ring_emit_fence
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r15d
	movl	%esi, %r14d
	movq	%rdi, %rbx
	movq	_AMDGPU_FENCE_FLAG_64BIT@GOTPCREL(%rip), %rax
	andl	(%rax), %ecx
	movl	%ecx, %edi
	callq	_WARN_ON
	movq	_UVD@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	movq	_mmUVD_CONTEXT_ID@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	%r15d, %esi
	callq	_amdgpu_ring_write
	movl	(%r12), %edi
	movq	_mmUVD_GPCOM_VCPU_DATA0@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_amdgpu_ring_write
	movl	(%r12), %edi
	movq	_mmUVD_GPCOM_VCPU_DATA1@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	%r14d, %edi
	callq	_upper_32_bits
	movzbl	%al, %esi
	movq	%rbx, %rdi
	callq	_amdgpu_ring_write
	movl	(%r12), %edi
	movq	_mmUVD_GPCOM_VCPU_CMD@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_VCN_DEC_CMD_FENCE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%esi, %esi
	movq	%rbx, %rdi
	callq	_amdgpu_ring_write
	movl	(%r12), %edi
	movl	(%r15), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
	movl	(%r12), %edi
	movl	(%r13), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
	movl	(%r12), %edi
	movl	(%r14), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_VCN_DEC_CMD_TRAP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%esi, %esi
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_write              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_FENCE_FLAG_64BIT,4,2    ## @AMDGPU_FENCE_FLAG_64BIT
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_CONTEXT_ID,4,2           ## @mmUVD_CONTEXT_ID
	.comm	_mmUVD_GPCOM_VCPU_DATA0,4,2     ## @mmUVD_GPCOM_VCPU_DATA0
	.comm	_mmUVD_GPCOM_VCPU_DATA1,4,2     ## @mmUVD_GPCOM_VCPU_DATA1
	.comm	_mmUVD_GPCOM_VCPU_CMD,4,2       ## @mmUVD_GPCOM_VCPU_CMD
	.comm	_VCN_DEC_CMD_FENCE,4,2          ## @VCN_DEC_CMD_FENCE
	.comm	_VCN_DEC_CMD_TRAP,4,2           ## @VCN_DEC_CMD_TRAP
	.no_dead_strip	_vcn_v1_0_dec_ring_emit_fence
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v1_0_dec_ring_emit_fence
_vcn_v1_0_dec_ring_emit_fence:          ; @vcn_v1_0_dec_ring_emit_fence
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x21, x2
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x8, _AMDGPU_FENCE_FLAG_64BIT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPU_FENCE_FLAG_64BIT@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	and	w0, w8, w3
	bl	_WARN_ON
Lloh3:
	adrp	x22, _UVD@GOTPAGE
Lloh4:
	ldr	x22, [x22, _UVD@GOTPAGEOFF]
	ldr	w0, [x22]
Lloh5:
	adrp	x8, _mmUVD_CONTEXT_ID@GOTPAGE
Lloh6:
	ldr	x8, [x8, _mmUVD_CONTEXT_ID@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	x1, x21
	bl	_amdgpu_ring_write
	ldr	w0, [x22]
Lloh8:
	adrp	x21, _mmUVD_GPCOM_VCPU_DATA0@GOTPAGE
Lloh9:
	ldr	x21, [x21, _mmUVD_GPCOM_VCPU_DATA0@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_ring_write
	ldr	w0, [x22]
Lloh10:
	adrp	x23, _mmUVD_GPCOM_VCPU_DATA1@GOTPAGE
Lloh11:
	ldr	x23, [x23, _mmUVD_GPCOM_VCPU_DATA1@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x20
	bl	_upper_32_bits
	and	w1, w0, #0xff
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x22]
Lloh12:
	adrp	x20, _mmUVD_GPCOM_VCPU_CMD@GOTPAGE
Lloh13:
	ldr	x20, [x20, _mmUVD_GPCOM_VCPU_CMD@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh14:
	adrp	x8, _VCN_DEC_CMD_FENCE@GOTPAGE
Lloh15:
	ldr	x8, [x8, _VCN_DEC_CMD_FENCE@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
	lsl	w1, w8, #1
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x22]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_ring_write
	ldr	w0, [x22]
	ldr	w2, [x23]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_ring_write
	ldr	w0, [x22]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh17:
	adrp	x8, _VCN_DEC_CMD_TRAP@GOTPAGE
Lloh18:
	ldr	x8, [x8, _VCN_DEC_CMD_TRAP@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
	lsl	w1, w8, #1
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_amdgpu_ring_write
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_FENCE_FLAG_64BIT,4,2    ; @AMDGPU_FENCE_FLAG_64BIT
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_CONTEXT_ID,4,2           ; @mmUVD_CONTEXT_ID
	.comm	_mmUVD_GPCOM_VCPU_DATA0,4,2     ; @mmUVD_GPCOM_VCPU_DATA0
	.comm	_mmUVD_GPCOM_VCPU_DATA1,4,2     ; @mmUVD_GPCOM_VCPU_DATA1
	.comm	_mmUVD_GPCOM_VCPU_CMD,4,2       ; @mmUVD_GPCOM_VCPU_CMD
	.comm	_VCN_DEC_CMD_FENCE,4,2          ; @VCN_DEC_CMD_FENCE
	.comm	_VCN_DEC_CMD_TRAP,4,2           ; @VCN_DEC_CMD_TRAP
	.no_dead_strip	_vcn_v1_0_dec_ring_emit_fence
.subsections_via_symbols
