	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function set_vm_context_page_table_base
_set_vm_context_page_table_base:        ## @set_vm_context_page_table_base
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r12d
	movl	%esi, %ebx
	callq	_get_amdgpu_device
	movq	%rax, %r15
	movq	_AMDGPU_PTE_VALID@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_amdgpu_amdkfd_is_kfd_vmid
	testl	%eax, %eax
	je	LBB0_1
## %bb.2:
	orl	%r12d, %r14d
	movq	_GC@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movq	_mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	addl	%ebx, %ebx
	movslq	%ebx, %rbx
	leaq	(%rax,%rbx), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r13), %edi
	movq	_mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	leaq	(%rax,%rbx), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r13), %edi
	movq	_mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	leaq	(%rax,%rbx), %r12
	movl	(%r15), %edi
	decl	%edi
	callq	_lower_32_bits
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_WREG32
	movl	(%r13), %edi
	movq	_mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	leaq	(%rax,%rbx), %r12
	movl	(%r15), %edi
	decl	%edi
	callq	_upper_32_bits
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_WREG32
	movl	(%r13), %edi
	movq	_mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	leaq	(%rax,%rbx), %r15
	movl	%r14d, %edi
	callq	_lower_32_bits
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_WREG32
	movl	(%r13), %edi
	movq	_mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	addq	%rax, %rbx
	movl	%r14d, %edi
	callq	_upper_32_bits
	movq	%rbx, %rdi
	movl	%eax, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
LBB0_1:
	leaq	L_.str(%rip), %rdi
	movl	%ebx, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_pr_err                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_PTE_VALID,4,2           ## @AMDGPU_PTE_VALID
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"trying to set page table base for wrong VMID %u\n"

	.comm	_GC,4,2                         ## @GC
	.comm	_mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,4,2 ## @mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
	.comm	_mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,4,2 ## @mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
	.comm	_mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,4,2 ## @mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
	.comm	_mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,4,2 ## @mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
	.comm	_mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,4,2 ## @mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
	.comm	_mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,4,2 ## @mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
	.no_dead_strip	_set_vm_context_page_table_base
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function set_vm_context_page_table_base
_set_vm_context_page_table_base:        ; @set_vm_context_page_table_base
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x2
	mov	x21, x1
	bl	_get_amdgpu_device
	mov	x20, x0
Lloh0:
	adrp	x8, _AMDGPU_PTE_VALID@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPU_PTE_VALID@GOTPAGEOFF]
Lloh2:
	ldr	w22, [x8]
	mov	x1, x21
	bl	_amdgpu_amdkfd_is_kfd_vmid
	cbz	w0, LBB0_2
; %bb.1:
	orr	w19, w22, w19
Lloh3:
	adrp	x22, _GC@GOTPAGE
Lloh4:
	ldr	x22, [x22, _GC@GOTPAGEOFF]
	ldr	w0, [x22]
Lloh5:
	adrp	x8, _mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32@GOTPAGE
Lloh6:
	ldr	x8, [x8, _mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	lsl	w8, w21, #1
	sxtw	x23, w8
	add	x0, x0, x23
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x22]
Lloh8:
	adrp	x8, _mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32@GOTPAGE
Lloh9:
	ldr	x8, [x8, _mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	add	x0, x0, x23
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x22]
Lloh11:
	adrp	x8, _mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32@GOTPAGE
Lloh12:
	ldr	x8, [x8, _mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	add	x21, x0, x23
	ldr	w8, [x20]
	sub	w0, w8, #1
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x21
	bl	_WREG32
	ldr	w0, [x22]
Lloh14:
	adrp	x8, _mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32@GOTPAGE
Lloh15:
	ldr	x8, [x8, _mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	add	x21, x0, x23
	ldr	w8, [x20]
	sub	w0, w8, #1
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x21
	bl	_WREG32
	ldr	w0, [x22]
Lloh17:
	adrp	x8, _mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32@GOTPAGE
Lloh18:
	ldr	x8, [x8, _mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32@GOTPAGEOFF]
Lloh19:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	add	x20, x0, x23
	mov	x0, x19
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
	ldr	w0, [x22]
Lloh20:
	adrp	x8, _mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32@GOTPAGE
Lloh21:
	ldr	x8, [x8, _mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	add	x20, x0, x23
	mov	x0, x19
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_WREG32
LBB0_2:
Lloh23:
	adrp	x0, l_.str@PAGE
Lloh24:
	add	x0, x0, l_.str@PAGEOFF
	mov	x1, x21
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_pr_err
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpAdd	Lloh23, Lloh24
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_PTE_VALID,4,2           ; @AMDGPU_PTE_VALID
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"trying to set page table base for wrong VMID %u\n"

	.comm	_GC,4,2                         ; @GC
	.comm	_mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,4,2 ; @mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
	.comm	_mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,4,2 ; @mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
	.comm	_mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,4,2 ; @mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
	.comm	_mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,4,2 ; @mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
	.comm	_mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,4,2 ; @mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
	.comm	_mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,4,2 ; @mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
	.no_dead_strip	_set_vm_context_page_table_base
.subsections_via_symbols
