	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v1_0_start_spg_mode
_vcn_v1_0_start_spg_mode:               ## @vcn_v1_0_start_spg_mode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	(%rdi), %rax
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
	callq	_vcn_1_0_disable_static_power_gating
	movq	_UVD@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movq	_mmUVD_STATUS@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movl	$0, -44(%rbp)                   ## 4-byte Folded Spill
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_UVD_STATUS__UVD_BUSY@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r13), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	%r15, %rdi
	callq	_vcn_v1_0_disable_clock_gating
	movl	(%r13), %edi
	movq	_mmUVD_MASTINT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_MASTINT_EN__VCPU_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	(%r13), %edi
	movq	_mmUVD_LMI_CTRL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_LMI_CTRL__MASK_MC_URGENT_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r13), %edi
	movq	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edx
	movq	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmUVD_LMI_SWAP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmUVD_MPC_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_UVD_MPC_CNTL__REPLACEMENT_MODE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	_UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %eax
	shll	%cl, %eax
	orl	%edx, %eax
	movl	(%r13), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmUVD_MPC_SET_MUXA0@GOTPCREL(%rip), %rax
	movq	_UVD_MPC_SET_MUXA0__VARA_2__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %esi
	shll	%cl, %esi
	movl	(%rax), %edx
	movq	_UVD_MPC_SET_MUXA0__VARA_1__SHIFT@GOTPCREL(%rip), %rax
	movq	_UVD_MPC_SET_MUXA0__VARA_3__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$3, %r8d
	shll	%cl, %r8d
	movb	(%rax), %al
	btsl	%eax, %esi
	movq	_UVD_MPC_SET_MUXA0__VARA_4__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$4, %eax
	shll	%cl, %eax
	movl	$3, %r14d
	movl	$4, %ebx
	orl	%r8d, %eax
	orl	%esi, %eax
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_UVD_MPC_SET_MUXB0__VARB_2__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %eax
	shll	%cl, %eax
	movq	_UVD_MPC_SET_MUXB0__VARB_3__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r14d
	movq	_mmUVD_MPC_SET_MUXB0@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_UVD_MPC_SET_MUXB0__VARB_4__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movq	_UVD_MPC_SET_MUXB0__VARB_1__SHIFT@GOTPCREL(%rip), %rsi
	shll	%cl, %ebx
	movb	(%rsi), %cl
	btsl	%ecx, %eax
	orl	%r14d, %ebx
	orl	%eax, %ebx
	xorl	%esi, %esi
	movl	%ebx, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmUVD_MPC_SET_MUX@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_UVD_MPC_SET_MUX__SET_1__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	movq	_UVD_MPC_SET_MUX__SET_2__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %esi
	shll	%cl, %esi
	btsl	%eax, %esi
	movl	%esi, %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movq	%r15, -64(%rbp)                 ## 8-byte Spill
	movq	%r15, %rdi
	callq	_vcn_v1_0_mc_resume_spg_mode
	movl	(%r13), %edi
	movq	_mmUVD_REG_XX_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	movl	$16, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %ebx
	movq	_mmUVD_RBC_XX_IB_REG_CHECK@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r14d, %edx
	callq	_RREG32_SOC15
	orl	$3, %eax
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r14d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmUVD_VCPU_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_UVD_VCPU_CNTL__CLK_EN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmUVD_SOFT_RESET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	(%r13), %edi
	movq	_mmUVD_LMI_CTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	(%r13), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPCREL(%rip), %rdx
	movq	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rdx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movq	%r13, %r15
	movl	(%r13), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movq	_UVD_STATUS__IDLE@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_1:                                 ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_2 Depth 2
	movl	$100, %r13d
	.p2align	4, 0x90
LBB0_2:                                 ##   Parent Loop BB0_1 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movl	(%r15), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	%eax, %ebx
	movl	(%r14), %eax
	testl	%ebx, %eax
	jne	LBB0_5
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=2
	movl	$10, %edi
	callq	_mdelay
	decl	%r13d
	jne	LBB0_2
## %bb.4:                               ##   in Loop: Header=BB0_1 Depth=1
	movl	(%r14), %eax
LBB0_5:                                 ##   in Loop: Header=BB0_1 Depth=1
	testl	%ebx, %eax
	jne	LBB0_8
## %bb.6:                               ##   in Loop: Header=BB0_1 Depth=1
	leaq	L_.str(%rip), %rdi
	callq	_DRM_ERROR
	movq	%r15, %rbx
	movl	(%r15), %edi
	movq	_mmUVD_SOFT_RESET@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	callq	_WREG32_P
	movl	$10, %edi
	callq	_mdelay
	movl	(%r15), %edi
	movl	(%r13), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	$10, %edi
	callq	_mdelay
	movl	-44(%rbp), %eax                 ## 4-byte Reload
	incl	%eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	cmpl	$10, %eax
	jne	LBB0_1
## %bb.7:
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_ERROR
	movl	$-1, %eax
	jmp	LBB0_9
LBB0_8:
	movq	%r15, %r13
	movl	(%r15), %edi
	movq	_mmUVD_MASTINT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_MASTINT_EN__VCPU_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	callq	_WREG32_P
	movl	(%r15), %edi
	movq	_mmUVD_SYS_INT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_SYS_INT_EN__UVD_JRBC_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	callq	_WREG32_P
	movl	(%r15), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_UVD_STATUS__UVD_BUSY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movl	(%r15), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movq	-56(%rbp), %r14                 ## 8-byte Reload
	movl	24(%r14), %edi
	callq	_order_base_2
	movq	_UVD_RBC_RB_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_RB_BUFSZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%edi, %edi
	movl	%eax, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_BLKSZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_NO_FETCH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_NO_UPDATE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_RPTR_WR_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r15), %edi
	movq	_mmUVD_RBC_RB_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmUVD_RBC_RB_WPTR_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %ebx
	movq	_mmUVD_RBC_RB_RPTR_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	28(%r14), %edi
	callq	_upper_32_bits
	sarl	$2, %eax
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %ebx
	movq	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	28(%r14), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %ebx
	movq	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	28(%r14), %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmUVD_RBC_RB_RPTR@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmUVD_SCRATCH2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	%eax, 32(%r14)
	movl	(%r13), %ebx
	movq	_mmUVD_RBC_RB_WPTR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r12d
	movl	%eax, %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movl	(%r15), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movq	-64(%rbp), %r15                 ## 8-byte Reload
	movq	(%r15), %rax
	movq	16(%rax), %rbx
	movl	(%r13), %r14d
	movq	_mmUVD_RB_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	8(%rbx), %edi
	callq	_lower_32_bits
	movl	%r14d, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %r14d
	movq	_mmUVD_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	8(%rbx), %edi
	callq	_lower_32_bits
	movl	%r14d, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmUVD_RB_BASE_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	4(%rbx), %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r13), %r14d
	movq	_mmUVD_RB_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	4(%rbx), %edi
	callq	_upper_32_bits
	movl	%r14d, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmUVD_RB_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%rbx), %eax
	leal	3(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$2, %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movq	(%r15), %rax
	movq	16(%rax), %rbx
	movl	(%r13), %r14d
	movq	_mmUVD_RB_RPTR2@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	24(%rbx), %edi
	callq	_lower_32_bits
	movl	%r14d, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %r14d
	movq	_mmUVD_RB_WPTR2@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	24(%rbx), %edi
	callq	_lower_32_bits
	movl	%r14d, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmUVD_RB_BASE_LO2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	20(%rbx), %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r13), %r14d
	movq	_mmUVD_RB_BASE_HI2@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	20(%rbx), %edi
	callq	_upper_32_bits
	movl	%r14d, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmUVD_RB_SIZE2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	16(%rbx), %eax
	leal	3(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$2, %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movq	(%r15), %r15
	movl	(%r13), %edi
	movq	_mmUVD_LMI_JRBC_RB_VMID@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmUVD_JRBC_RB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK@GOTPCREL(%rip), %rax
	movq	_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK@GOTPCREL(%rip), %r14
	movl	(%r14), %ecx
	orl	(%rax), %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r13), %ebx
	movq	_mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	4(%r15), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %ebx
	movq	_mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	4(%r15), %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmUVD_JRBC_RB_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmUVD_JRBC_RB_WPTR@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movq	_mmUVD_JRBC_RB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r14), %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r13), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	%eax, 8(%r15)
	movq	_amdgpu_sched_hw_submission@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	imull	12(%r15), %esi
	addl	%eax, %esi
	movq	%r15, %rdi
	callq	_vcn_v1_0_jpeg_ring_set_patch_ring
	xorl	%eax, %eax
LBB0_9:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_STATUS,4,2               ## @mmUVD_STATUS
	.comm	_UVD_STATUS__UVD_BUSY,4,2       ## @UVD_STATUS__UVD_BUSY
	.comm	_mmUVD_MASTINT_EN,4,2           ## @mmUVD_MASTINT_EN
	.comm	_UVD_MASTINT_EN__VCPU_EN_MASK,4,2 ## @UVD_MASTINT_EN__VCPU_EN_MASK
	.comm	_mmUVD_LMI_CTRL,4,2             ## @mmUVD_LMI_CTRL
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK,4,2 ## @UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK
	.comm	_UVD_LMI_CTRL__MASK_MC_URGENT_MASK,4,2 ## @UVD_LMI_CTRL__MASK_MC_URGENT_MASK
	.comm	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK,4,2 ## @UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK,4,2 ## @UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
	.comm	_mmUVD_LMI_SWAP_CNTL,4,2        ## @mmUVD_LMI_SWAP_CNTL
	.comm	_mmUVD_MPC_CNTL,4,2             ## @mmUVD_MPC_CNTL
	.comm	_UVD_MPC_CNTL__REPLACEMENT_MODE_MASK,4,2 ## @UVD_MPC_CNTL__REPLACEMENT_MODE_MASK
	.comm	_UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT,4,2 ## @UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT
	.comm	_mmUVD_MPC_SET_MUXA0,4,2        ## @mmUVD_MPC_SET_MUXA0
	.comm	_UVD_MPC_SET_MUXA0__VARA_1__SHIFT,4,2 ## @UVD_MPC_SET_MUXA0__VARA_1__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_2__SHIFT,4,2 ## @UVD_MPC_SET_MUXA0__VARA_2__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_3__SHIFT,4,2 ## @UVD_MPC_SET_MUXA0__VARA_3__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_4__SHIFT,4,2 ## @UVD_MPC_SET_MUXA0__VARA_4__SHIFT
	.comm	_mmUVD_MPC_SET_MUXB0,4,2        ## @mmUVD_MPC_SET_MUXB0
	.comm	_UVD_MPC_SET_MUXB0__VARB_1__SHIFT,4,2 ## @UVD_MPC_SET_MUXB0__VARB_1__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_2__SHIFT,4,2 ## @UVD_MPC_SET_MUXB0__VARB_2__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_3__SHIFT,4,2 ## @UVD_MPC_SET_MUXB0__VARB_3__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_4__SHIFT,4,2 ## @UVD_MPC_SET_MUXB0__VARB_4__SHIFT
	.comm	_mmUVD_MPC_SET_MUX,4,2          ## @mmUVD_MPC_SET_MUX
	.comm	_UVD_MPC_SET_MUX__SET_0__SHIFT,4,2 ## @UVD_MPC_SET_MUX__SET_0__SHIFT
	.comm	_UVD_MPC_SET_MUX__SET_1__SHIFT,4,2 ## @UVD_MPC_SET_MUX__SET_1__SHIFT
	.comm	_UVD_MPC_SET_MUX__SET_2__SHIFT,4,2 ## @UVD_MPC_SET_MUX__SET_2__SHIFT
	.comm	_mmUVD_REG_XX_MASK,4,2          ## @mmUVD_REG_XX_MASK
	.comm	_mmUVD_RBC_XX_IB_REG_CHECK,4,2  ## @mmUVD_RBC_XX_IB_REG_CHECK
	.comm	_mmUVD_VCPU_CNTL,4,2            ## @mmUVD_VCPU_CNTL
	.comm	_UVD_VCPU_CNTL__CLK_EN_MASK,4,2 ## @UVD_VCPU_CNTL__CLK_EN_MASK
	.comm	_mmUVD_SOFT_RESET,4,2           ## @mmUVD_SOFT_RESET
	.comm	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
	.comm	_mmUVD_LMI_CTRL2,4,2            ## @mmUVD_LMI_CTRL2
	.comm	_UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,4,2 ## @UVD_LMI_CTRL2__STALL_ARB_UMC_MASK
	.comm	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
	.comm	_UVD_STATUS__IDLE,4,2           ## @UVD_STATUS__IDLE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"VCN decode not responding, trying to reset the VCPU!!!\n"

L_.str.1:                               ## @.str.1
	.asciz	"VCN decode not responding, giving up!!!\n"

	.comm	_mmUVD_SYS_INT_EN,4,2           ## @mmUVD_SYS_INT_EN
	.comm	_UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,4,2 ## @UVD_SYS_INT_EN__UVD_JRBC_EN_MASK
	.comm	_UVD_RBC_RB_CNTL,4,2            ## @UVD_RBC_RB_CNTL
	.comm	_RB_BUFSZ,4,2                   ## @RB_BUFSZ
	.comm	_RB_BLKSZ,4,2                   ## @RB_BLKSZ
	.comm	_RB_NO_FETCH,4,2                ## @RB_NO_FETCH
	.comm	_RB_NO_UPDATE,4,2               ## @RB_NO_UPDATE
	.comm	_RB_RPTR_WR_EN,4,2              ## @RB_RPTR_WR_EN
	.comm	_mmUVD_RBC_RB_CNTL,4,2          ## @mmUVD_RBC_RB_CNTL
	.comm	_mmUVD_RBC_RB_WPTR_CNTL,4,2     ## @mmUVD_RBC_RB_WPTR_CNTL
	.comm	_mmUVD_RBC_RB_RPTR_ADDR,4,2     ## @mmUVD_RBC_RB_RPTR_ADDR
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
	.comm	_mmUVD_RBC_RB_RPTR,4,2          ## @mmUVD_RBC_RB_RPTR
	.comm	_mmUVD_SCRATCH2,4,2             ## @mmUVD_SCRATCH2
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ## @mmUVD_RBC_RB_WPTR
	.comm	_UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK,4,2 ## @UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK
	.comm	_mmUVD_RB_RPTR,4,2              ## @mmUVD_RB_RPTR
	.comm	_mmUVD_RB_WPTR,4,2              ## @mmUVD_RB_WPTR
	.comm	_mmUVD_RB_BASE_LO,4,2           ## @mmUVD_RB_BASE_LO
	.comm	_mmUVD_RB_BASE_HI,4,2           ## @mmUVD_RB_BASE_HI
	.comm	_mmUVD_RB_SIZE,4,2              ## @mmUVD_RB_SIZE
	.comm	_mmUVD_RB_RPTR2,4,2             ## @mmUVD_RB_RPTR2
	.comm	_mmUVD_RB_WPTR2,4,2             ## @mmUVD_RB_WPTR2
	.comm	_mmUVD_RB_BASE_LO2,4,2          ## @mmUVD_RB_BASE_LO2
	.comm	_mmUVD_RB_BASE_HI2,4,2          ## @mmUVD_RB_BASE_HI2
	.comm	_mmUVD_RB_SIZE2,4,2             ## @mmUVD_RB_SIZE2
	.comm	_mmUVD_LMI_JRBC_RB_VMID,4,2     ## @mmUVD_LMI_JRBC_RB_VMID
	.comm	_mmUVD_JRBC_RB_CNTL,4,2         ## @mmUVD_JRBC_RB_CNTL
	.comm	_UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK,4,2 ## @UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK
	.comm	_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK,4,2 ## @UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK
	.comm	_mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH
	.comm	_mmUVD_JRBC_RB_RPTR,4,2         ## @mmUVD_JRBC_RB_RPTR
	.comm	_mmUVD_JRBC_RB_WPTR,4,2         ## @mmUVD_JRBC_RB_WPTR
	.comm	_amdgpu_sched_hw_submission,4,2 ## @amdgpu_sched_hw_submission
	.no_dead_strip	_vcn_v1_0_start_spg_mode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v1_0_start_spg_mode
_vcn_v1_0_start_spg_mode:               ; @vcn_v1_0_start_spg_mode
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	x8, [x0]
	str	x8, [sp, #8]                    ; 8-byte Folded Spill
	bl	_vcn_1_0_disable_static_power_gating
Lloh0:
	adrp	x22, _UVD@GOTPAGE
Lloh1:
	ldr	x22, [x22, _UVD@GOTPAGEOFF]
	ldr	w0, [x22]
Lloh2:
	adrp	x24, _mmUVD_STATUS@GOTPAGE
Lloh3:
	ldr	x24, [x24, _mmUVD_STATUS@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh4:
	adrp	x8, _UVD_STATUS__UVD_BUSY@GOTPAGE
Lloh5:
	ldr	x8, [x8, _UVD_STATUS__UVD_BUSY@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
	orr	w3, w8, w0
	ldr	w0, [x22]
	ldr	w2, [x24]
	mov	w1, #0
	bl	_WREG32_SOC15
	mov	x0, x19
	bl	_vcn_v1_0_disable_clock_gating
	ldr	w0, [x22]
Lloh7:
	adrp	x8, _mmUVD_MASTINT_EN@GOTPAGE
Lloh8:
	ldr	x8, [x8, _mmUVD_MASTINT_EN@GOTPAGEOFF]
Lloh9:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh10:
	adrp	x8, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGE
Lloh11:
	ldr	x8, [x8, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w0, [x22]
Lloh13:
	adrp	x20, _mmUVD_LMI_CTRL@GOTPAGE
Lloh14:
	ldr	x20, [x20, _mmUVD_LMI_CTRL@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_RREG32_SOC15
	ldr	w8, [x22]
	ldr	w2, [x20]
Lloh15:
	adrp	x9, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPAGE
Lloh16:
	ldr	x9, [x9, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	orr	w9, w9, w0
Lloh18:
	adrp	x10, _UVD_LMI_CTRL__MASK_MC_URGENT_MASK@GOTPAGE
Lloh19:
	ldr	x10, [x10, _UVD_LMI_CTRL__MASK_MC_URGENT_MASK@GOTPAGEOFF]
Lloh20:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh21:
	adrp	x10, _UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPAGE
Lloh22:
	ldr	x10, [x10, _UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPAGEOFF]
Lloh23:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh24:
	adrp	x10, _UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPAGE
Lloh25:
	ldr	x10, [x10, _UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPAGEOFF]
Lloh26:
	ldr	w10, [x10]
	orr	w3, w9, w10
	mov	x0, x8
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh27:
	adrp	x8, _mmUVD_LMI_SWAP_CNTL@GOTPAGE
Lloh28:
	ldr	x8, [x8, _mmUVD_LMI_SWAP_CNTL@GOTPAGEOFF]
Lloh29:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh30:
	adrp	x21, _mmUVD_MPC_CNTL@GOTPAGE
Lloh31:
	ldr	x21, [x21, _mmUVD_MPC_CNTL@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh32:
	adrp	x8, _UVD_MPC_CNTL__REPLACEMENT_MODE_MASK@GOTPAGE
Lloh33:
	ldr	x8, [x8, _UVD_MPC_CNTL__REPLACEMENT_MODE_MASK@GOTPAGEOFF]
Lloh34:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh35:
	adrp	x9, _UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT@GOTPAGE
Lloh36:
	ldr	x9, [x9, _UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT@GOTPAGEOFF]
Lloh37:
	ldr	w9, [x9]
	mov	w20, #2
	lsl	w9, w20, w9
	orr	w3, w9, w8
	ldr	w0, [x22]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_WREG32_SOC15
Lloh38:
	adrp	x8, _mmUVD_MPC_SET_MUXA0@GOTPAGE
Lloh39:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXA0@GOTPAGEOFF]
	ldr	w0, [x22]
Lloh40:
	ldr	w2, [x8]
Lloh41:
	adrp	x8, _UVD_MPC_SET_MUXA0__VARA_1__SHIFT@GOTPAGE
Lloh42:
	ldr	x8, [x8, _UVD_MPC_SET_MUXA0__VARA_1__SHIFT@GOTPAGEOFF]
Lloh43:
	ldr	w8, [x8]
	mov	w21, #1
	lsl	w8, w21, w8
Lloh44:
	adrp	x9, _UVD_MPC_SET_MUXA0__VARA_2__SHIFT@GOTPAGE
Lloh45:
	ldr	x9, [x9, _UVD_MPC_SET_MUXA0__VARA_2__SHIFT@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
	lsl	w9, w20, w9
	orr	w8, w9, w8
Lloh47:
	adrp	x9, _UVD_MPC_SET_MUXA0__VARA_3__SHIFT@GOTPAGE
Lloh48:
	ldr	x9, [x9, _UVD_MPC_SET_MUXA0__VARA_3__SHIFT@GOTPAGEOFF]
Lloh49:
	ldr	w9, [x9]
	mov	w23, #3
	lsl	w9, w23, w9
	orr	w8, w8, w9
Lloh50:
	adrp	x9, _UVD_MPC_SET_MUXA0__VARA_4__SHIFT@GOTPAGE
Lloh51:
	ldr	x9, [x9, _UVD_MPC_SET_MUXA0__VARA_4__SHIFT@GOTPAGEOFF]
Lloh52:
	ldr	w9, [x9]
	mov	w25, #4
	lsl	w9, w25, w9
	orr	w3, w8, w9
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh53:
	adrp	x8, _mmUVD_MPC_SET_MUXB0@GOTPAGE
Lloh54:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXB0@GOTPAGEOFF]
Lloh55:
	adrp	x9, _UVD_MPC_SET_MUXB0__VARB_1__SHIFT@GOTPAGE
Lloh56:
	ldr	x9, [x9, _UVD_MPC_SET_MUXB0__VARB_1__SHIFT@GOTPAGEOFF]
Lloh57:
	ldr	w2, [x8]
Lloh58:
	ldr	w8, [x9]
	lsl	w8, w21, w8
Lloh59:
	adrp	x9, _UVD_MPC_SET_MUXB0__VARB_2__SHIFT@GOTPAGE
Lloh60:
	ldr	x9, [x9, _UVD_MPC_SET_MUXB0__VARB_2__SHIFT@GOTPAGEOFF]
Lloh61:
	ldr	w9, [x9]
	lsl	w9, w20, w9
	orr	w8, w9, w8
Lloh62:
	adrp	x9, _UVD_MPC_SET_MUXB0__VARB_3__SHIFT@GOTPAGE
Lloh63:
	ldr	x9, [x9, _UVD_MPC_SET_MUXB0__VARB_3__SHIFT@GOTPAGEOFF]
Lloh64:
	ldr	w9, [x9]
	lsl	w9, w23, w9
	orr	w8, w8, w9
Lloh65:
	adrp	x9, _UVD_MPC_SET_MUXB0__VARB_4__SHIFT@GOTPAGE
Lloh66:
	ldr	x9, [x9, _UVD_MPC_SET_MUXB0__VARB_4__SHIFT@GOTPAGEOFF]
Lloh67:
	ldr	w9, [x9]
	lsl	w9, w25, w9
	orr	w3, w8, w9
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh68:
	adrp	x8, _mmUVD_MPC_SET_MUX@GOTPAGE
Lloh69:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUX@GOTPAGEOFF]
Lloh70:
	ldr	w2, [x8]
Lloh71:
	adrp	x8, _UVD_MPC_SET_MUX__SET_1__SHIFT@GOTPAGE
Lloh72:
	ldr	x8, [x8, _UVD_MPC_SET_MUX__SET_1__SHIFT@GOTPAGEOFF]
Lloh73:
	ldr	w8, [x8]
	lsl	w8, w21, w8
Lloh74:
	adrp	x9, _UVD_MPC_SET_MUX__SET_2__SHIFT@GOTPAGE
Lloh75:
	ldr	x9, [x9, _UVD_MPC_SET_MUX__SET_2__SHIFT@GOTPAGEOFF]
Lloh76:
	ldr	w9, [x9]
	lsl	w9, w20, w9
	orr	w3, w9, w8
	mov	w1, #0
	bl	_WREG32_SOC15
	mov	x0, x19
	bl	_vcn_v1_0_mc_resume_spg_mode
	ldr	w0, [x22]
Lloh77:
	adrp	x8, _mmUVD_REG_XX_MASK@GOTPAGE
Lloh78:
	ldr	x8, [x8, _mmUVD_REG_XX_MASK@GOTPAGEOFF]
Lloh79:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #16
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh80:
	adrp	x8, _mmUVD_RBC_XX_IB_REG_CHECK@GOTPAGE
Lloh81:
	ldr	x8, [x8, _mmUVD_RBC_XX_IB_REG_CHECK@GOTPAGEOFF]
Lloh82:
	ldr	w21, [x8]
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_RREG32_SOC15
	orr	w3, w0, #0x3
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh83:
	adrp	x8, _mmUVD_VCPU_CNTL@GOTPAGE
Lloh84:
	ldr	x8, [x8, _mmUVD_VCPU_CNTL@GOTPAGEOFF]
Lloh85:
	ldr	w2, [x8]
Lloh86:
	adrp	x8, _UVD_VCPU_CNTL__CLK_EN_MASK@GOTPAGE
Lloh87:
	ldr	x8, [x8, _UVD_VCPU_CNTL__CLK_EN_MASK@GOTPAGEOFF]
Lloh88:
	ldr	w3, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh89:
	adrp	x28, _mmUVD_SOFT_RESET@GOTPAGE
Lloh90:
	ldr	x28, [x28, _mmUVD_SOFT_RESET@GOTPAGEOFF]
	ldr	w2, [x28]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh91:
	adrp	x25, _UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPAGE
Lloh92:
	ldr	x25, [x25, _UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPAGEOFF]
	ldr	w8, [x25]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w0, [x22]
Lloh93:
	adrp	x8, _mmUVD_LMI_CTRL2@GOTPAGE
Lloh94:
	ldr	x8, [x8, _mmUVD_LMI_CTRL2@GOTPAGEOFF]
Lloh95:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh96:
	adrp	x8, _UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPAGE
Lloh97:
	ldr	x8, [x8, _UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPAGEOFF]
Lloh98:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w0, [x22]
	ldr	w2, [x28]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh99:
	adrp	x8, _UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPAGE
Lloh100:
	ldr	x8, [x8, _UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh101:
	adrp	x9, _UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPAGE
Lloh102:
	ldr	x9, [x9, _UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh103:
	ldr	w8, [x8]
Lloh104:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w3, w0, w8
	ldr	w0, [x22]
	ldr	w2, [x28]
	mov	w1, #0
	bl	_WREG32_SOC15
	mov	w26, #0
Lloh105:
	adrp	x27, _UVD_STATUS__IDLE@GOTPAGE
Lloh106:
	ldr	x27, [x27, _UVD_STATUS__IDLE@GOTPAGEOFF]
Lloh107:
	adrp	x20, l_.str@PAGE
Lloh108:
	add	x20, x20, l_.str@PAGEOFF
LBB0_1:                                 ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
	mov	w23, #100
LBB0_2:                                 ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ldr	w0, [x22]
	ldr	w2, [x24]
	mov	w1, #0
	bl	_RREG32_SOC15
	mov	x21, x0
	ldr	w8, [x27]
	tst	w8, w0
	b.ne	LBB0_5
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=2
	mov	w0, #10
	bl	_mdelay
	subs	w23, w23, #1
	b.ne	LBB0_2
; %bb.4:                                ;   in Loop: Header=BB0_1 Depth=1
	ldr	w8, [x27]
LBB0_5:                                 ;   in Loop: Header=BB0_1 Depth=1
	tst	w8, w21
	b.ne	LBB0_8
; %bb.6:                                ;   in Loop: Header=BB0_1 Depth=1
	mov	x0, x20
	bl	_DRM_ERROR
	ldr	w0, [x22]
	ldr	w2, [x28]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w1, [x25]
	mvn	w2, w1
	bl	_WREG32_P
	mov	w0, #10
	bl	_mdelay
	ldr	w0, [x22]
	ldr	w2, [x28]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x25]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	mov	w0, #10
	bl	_mdelay
	add	w26, w26, #1
	cmp	w26, #10
	b.ne	LBB0_1
; %bb.7:
Lloh109:
	adrp	x0, l_.str.1@PAGE
Lloh110:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_ERROR
	mov	w0, #-1
	b	LBB0_9
LBB0_8:
	ldr	w0, [x22]
Lloh111:
	adrp	x8, _mmUVD_MASTINT_EN@GOTPAGE
Lloh112:
	ldr	x8, [x8, _mmUVD_MASTINT_EN@GOTPAGEOFF]
Lloh113:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh114:
	adrp	x8, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGE
Lloh115:
	ldr	x8, [x8, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGEOFF]
Lloh116:
	ldr	w1, [x8]
	mvn	w2, w1
	bl	_WREG32_P
	ldr	w0, [x22]
Lloh117:
	adrp	x8, _mmUVD_SYS_INT_EN@GOTPAGE
Lloh118:
	ldr	x8, [x8, _mmUVD_SYS_INT_EN@GOTPAGEOFF]
Lloh119:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh120:
	adrp	x8, _UVD_SYS_INT_EN__UVD_JRBC_EN_MASK@GOTPAGE
Lloh121:
	ldr	x8, [x8, _UVD_SYS_INT_EN__UVD_JRBC_EN_MASK@GOTPAGEOFF]
Lloh122:
	ldr	w1, [x8]
	mvn	w2, w1
	bl	_WREG32_P
	ldr	w0, [x22]
	ldr	w2, [x24]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh123:
	adrp	x8, _UVD_STATUS__UVD_BUSY@GOTPAGE
Lloh124:
	ldr	x8, [x8, _UVD_STATUS__UVD_BUSY@GOTPAGEOFF]
Lloh125:
	ldr	w8, [x8]
	bic	w3, w0, w8
	ldr	w0, [x22]
	ldr	w2, [x24]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	x23, [sp, #8]                   ; 8-byte Folded Reload
	ldr	w0, [x23, #24]
	bl	_order_base_2
	mov	x3, x0
Lloh126:
	adrp	x20, _UVD_RBC_RB_CNTL@GOTPAGE
Lloh127:
	ldr	x20, [x20, _UVD_RBC_RB_CNTL@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh128:
	adrp	x8, _RB_BUFSZ@GOTPAGE
Lloh129:
	ldr	x8, [x8, _RB_BUFSZ@GOTPAGEOFF]
Lloh130:
	ldr	w2, [x8]
	mov	w0, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x20]
Lloh131:
	adrp	x8, _RB_BLKSZ@GOTPAGE
Lloh132:
	ldr	x8, [x8, _RB_BLKSZ@GOTPAGEOFF]
Lloh133:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x20]
Lloh134:
	adrp	x8, _RB_NO_FETCH@GOTPAGE
Lloh135:
	ldr	x8, [x8, _RB_NO_FETCH@GOTPAGEOFF]
Lloh136:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x20]
Lloh137:
	adrp	x8, _RB_NO_UPDATE@GOTPAGE
Lloh138:
	ldr	x8, [x8, _RB_NO_UPDATE@GOTPAGEOFF]
Lloh139:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x20]
Lloh140:
	adrp	x8, _RB_RPTR_WR_EN@GOTPAGE
Lloh141:
	ldr	x8, [x8, _RB_RPTR_WR_EN@GOTPAGEOFF]
Lloh142:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x22]
Lloh143:
	adrp	x24, _mmUVD_RBC_RB_CNTL@GOTPAGE
Lloh144:
	ldr	x24, [x24, _mmUVD_RBC_RB_CNTL@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh145:
	adrp	x8, _mmUVD_RBC_RB_WPTR_CNTL@GOTPAGE
Lloh146:
	ldr	x8, [x8, _mmUVD_RBC_RB_WPTR_CNTL@GOTPAGEOFF]
Lloh147:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh148:
	adrp	x8, _mmUVD_RBC_RB_RPTR_ADDR@GOTPAGE
Lloh149:
	ldr	x8, [x8, _mmUVD_RBC_RB_RPTR_ADDR@GOTPAGEOFF]
Lloh150:
	ldr	w21, [x8]
	ldr	w0, [x23, #28]
	bl	_upper_32_bits
	asr	w3, w0, #2
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh151:
	adrp	x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPAGE
Lloh152:
	ldr	x8, [x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh153:
	ldr	w21, [x8]
	ldr	w0, [x23, #28]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh154:
	adrp	x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPAGE
Lloh155:
	ldr	x8, [x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh156:
	ldr	w21, [x8]
	ldr	w0, [x23, #28]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh157:
	adrp	x20, _mmUVD_RBC_RB_RPTR@GOTPAGE
Lloh158:
	ldr	x20, [x20, _mmUVD_RBC_RB_RPTR@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh159:
	adrp	x8, _mmUVD_SCRATCH2@GOTPAGE
Lloh160:
	ldr	x8, [x8, _mmUVD_SCRATCH2@GOTPAGEOFF]
Lloh161:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_RREG32_SOC15
	str	w0, [x23, #32]
	ldr	w20, [x22]
Lloh162:
	adrp	x8, _mmUVD_RBC_RB_WPTR@GOTPAGE
Lloh163:
	ldr	x8, [x8, _mmUVD_RBC_RB_WPTR@GOTPAGEOFF]
Lloh164:
	ldr	w21, [x8]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w0, [x22]
	ldr	w2, [x24]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh165:
	adrp	x8, _UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK@GOTPAGE
Lloh166:
	ldr	x8, [x8, _UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK@GOTPAGEOFF]
Lloh167:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	x8, [x19]
	ldr	x23, [x8, #16]
	ldr	w20, [x22]
Lloh168:
	adrp	x8, _mmUVD_RB_RPTR@GOTPAGE
Lloh169:
	ldr	x8, [x8, _mmUVD_RB_RPTR@GOTPAGEOFF]
Lloh170:
	ldr	w21, [x8]
	ldr	w0, [x23, #8]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh171:
	adrp	x8, _mmUVD_RB_WPTR@GOTPAGE
Lloh172:
	ldr	x8, [x8, _mmUVD_RB_WPTR@GOTPAGEOFF]
Lloh173:
	ldr	w21, [x8]
	ldr	w0, [x23, #8]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh174:
	adrp	x8, _mmUVD_RB_BASE_LO@GOTPAGE
Lloh175:
	ldr	x8, [x8, _mmUVD_RB_BASE_LO@GOTPAGEOFF]
Lloh176:
	ldr	w2, [x8]
	ldr	w3, [x23, #4]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh177:
	adrp	x8, _mmUVD_RB_BASE_HI@GOTPAGE
Lloh178:
	ldr	x8, [x8, _mmUVD_RB_BASE_HI@GOTPAGEOFF]
Lloh179:
	ldr	w21, [x8]
	ldr	w0, [x23, #4]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh180:
	adrp	x8, _mmUVD_RB_SIZE@GOTPAGE
Lloh181:
	ldr	x8, [x8, _mmUVD_RB_SIZE@GOTPAGEOFF]
Lloh182:
	ldr	w2, [x8]
	ldr	w8, [x23]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w3, w8, #2
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	x8, [x19]
	ldr	x23, [x8, #16]
	ldr	w20, [x22]
Lloh183:
	adrp	x8, _mmUVD_RB_RPTR2@GOTPAGE
Lloh184:
	ldr	x8, [x8, _mmUVD_RB_RPTR2@GOTPAGEOFF]
Lloh185:
	ldr	w21, [x8]
	ldr	w0, [x23, #24]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh186:
	adrp	x8, _mmUVD_RB_WPTR2@GOTPAGE
Lloh187:
	ldr	x8, [x8, _mmUVD_RB_WPTR2@GOTPAGEOFF]
Lloh188:
	ldr	w21, [x8]
	ldr	w0, [x23, #24]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh189:
	adrp	x8, _mmUVD_RB_BASE_LO2@GOTPAGE
Lloh190:
	ldr	x8, [x8, _mmUVD_RB_BASE_LO2@GOTPAGEOFF]
Lloh191:
	ldr	w2, [x8]
	ldr	w3, [x23, #20]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh192:
	adrp	x8, _mmUVD_RB_BASE_HI2@GOTPAGE
Lloh193:
	ldr	x8, [x8, _mmUVD_RB_BASE_HI2@GOTPAGEOFF]
Lloh194:
	ldr	w21, [x8]
	ldr	w0, [x23, #20]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh195:
	adrp	x8, _mmUVD_RB_SIZE2@GOTPAGE
Lloh196:
	ldr	x8, [x8, _mmUVD_RB_SIZE2@GOTPAGEOFF]
Lloh197:
	ldr	w2, [x8]
	ldr	w8, [x23, #16]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w3, w8, #2
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	x19, [x19]
	ldr	w0, [x22]
Lloh198:
	adrp	x8, _mmUVD_LMI_JRBC_RB_VMID@GOTPAGE
Lloh199:
	ldr	x8, [x8, _mmUVD_LMI_JRBC_RB_VMID@GOTPAGEOFF]
Lloh200:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh201:
	adrp	x23, _mmUVD_JRBC_RB_CNTL@GOTPAGE
Lloh202:
	ldr	x23, [x23, _mmUVD_JRBC_RB_CNTL@GOTPAGEOFF]
Lloh203:
	adrp	x8, _UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK@GOTPAGE
Lloh204:
	ldr	x8, [x8, _UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK@GOTPAGEOFF]
	ldr	w2, [x23]
Lloh205:
	ldr	w8, [x8]
Lloh206:
	adrp	x24, _UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK@GOTPAGE
Lloh207:
	ldr	x24, [x24, _UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK@GOTPAGEOFF]
	ldr	w9, [x24]
	orr	w3, w9, w8
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh208:
	adrp	x8, _mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW@GOTPAGE
Lloh209:
	ldr	x8, [x8, _mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh210:
	ldr	w21, [x8]
	ldr	w0, [x19, #4]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh211:
	adrp	x8, _mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH@GOTPAGE
Lloh212:
	ldr	x8, [x8, _mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh213:
	ldr	w21, [x8]
	ldr	w0, [x19, #4]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh214:
	adrp	x8, _mmUVD_JRBC_RB_RPTR@GOTPAGE
Lloh215:
	ldr	x8, [x8, _mmUVD_JRBC_RB_RPTR@GOTPAGEOFF]
Lloh216:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh217:
	adrp	x20, _mmUVD_JRBC_RB_WPTR@GOTPAGE
Lloh218:
	ldr	x20, [x20, _mmUVD_JRBC_RB_WPTR@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
	ldr	w2, [x23]
	ldr	w3, [x24]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_RREG32_SOC15
	str	w0, [x19, #8]
	ldr	w8, [x19, #12]
Lloh219:
	adrp	x9, _amdgpu_sched_hw_submission@GOTPAGE
Lloh220:
	ldr	x9, [x9, _amdgpu_sched_hw_submission@GOTPAGEOFF]
Lloh221:
	ldr	w9, [x9]
	madd	w1, w9, w8, w0
	mov	x0, x19
	bl	_vcn_v1_0_jpeg_ring_set_patch_ring
	mov	w0, #0
LBB0_9:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpAdd	Lloh107, Lloh108
	.loh AdrpLdrGot	Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh103
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGot	Lloh91, Lloh92
	.loh AdrpLdrGot	Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh57
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh219, Lloh220, Lloh221
	.loh AdrpLdrGot	Lloh217, Lloh218
	.loh AdrpLdrGotLdr	Lloh214, Lloh215, Lloh216
	.loh AdrpLdrGotLdr	Lloh211, Lloh212, Lloh213
	.loh AdrpLdrGotLdr	Lloh208, Lloh209, Lloh210
	.loh AdrpLdrGot	Lloh206, Lloh207
	.loh AdrpLdrGotLdr	Lloh203, Lloh204, Lloh205
	.loh AdrpLdrGot	Lloh201, Lloh202
	.loh AdrpLdrGotLdr	Lloh198, Lloh199, Lloh200
	.loh AdrpLdrGotLdr	Lloh195, Lloh196, Lloh197
	.loh AdrpLdrGotLdr	Lloh192, Lloh193, Lloh194
	.loh AdrpLdrGotLdr	Lloh189, Lloh190, Lloh191
	.loh AdrpLdrGotLdr	Lloh186, Lloh187, Lloh188
	.loh AdrpLdrGotLdr	Lloh183, Lloh184, Lloh185
	.loh AdrpLdrGotLdr	Lloh180, Lloh181, Lloh182
	.loh AdrpLdrGotLdr	Lloh177, Lloh178, Lloh179
	.loh AdrpLdrGotLdr	Lloh174, Lloh175, Lloh176
	.loh AdrpLdrGotLdr	Lloh171, Lloh172, Lloh173
	.loh AdrpLdrGotLdr	Lloh168, Lloh169, Lloh170
	.loh AdrpLdrGotLdr	Lloh165, Lloh166, Lloh167
	.loh AdrpLdrGotLdr	Lloh162, Lloh163, Lloh164
	.loh AdrpLdrGotLdr	Lloh159, Lloh160, Lloh161
	.loh AdrpLdrGot	Lloh157, Lloh158
	.loh AdrpLdrGotLdr	Lloh154, Lloh155, Lloh156
	.loh AdrpLdrGotLdr	Lloh151, Lloh152, Lloh153
	.loh AdrpLdrGotLdr	Lloh148, Lloh149, Lloh150
	.loh AdrpLdrGotLdr	Lloh145, Lloh146, Lloh147
	.loh AdrpLdrGot	Lloh143, Lloh144
	.loh AdrpLdrGotLdr	Lloh140, Lloh141, Lloh142
	.loh AdrpLdrGotLdr	Lloh137, Lloh138, Lloh139
	.loh AdrpLdrGotLdr	Lloh134, Lloh135, Lloh136
	.loh AdrpLdrGotLdr	Lloh131, Lloh132, Lloh133
	.loh AdrpLdrGotLdr	Lloh128, Lloh129, Lloh130
	.loh AdrpLdrGot	Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh123, Lloh124, Lloh125
	.loh AdrpLdrGotLdr	Lloh120, Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.cfi_endproc
                                        ; -- End function
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_STATUS,4,2               ; @mmUVD_STATUS
	.comm	_UVD_STATUS__UVD_BUSY,4,2       ; @UVD_STATUS__UVD_BUSY
	.comm	_mmUVD_MASTINT_EN,4,2           ; @mmUVD_MASTINT_EN
	.comm	_UVD_MASTINT_EN__VCPU_EN_MASK,4,2 ; @UVD_MASTINT_EN__VCPU_EN_MASK
	.comm	_mmUVD_LMI_CTRL,4,2             ; @mmUVD_LMI_CTRL
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK,4,2 ; @UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK
	.comm	_UVD_LMI_CTRL__MASK_MC_URGENT_MASK,4,2 ; @UVD_LMI_CTRL__MASK_MC_URGENT_MASK
	.comm	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK,4,2 ; @UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK,4,2 ; @UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
	.comm	_mmUVD_LMI_SWAP_CNTL,4,2        ; @mmUVD_LMI_SWAP_CNTL
	.comm	_mmUVD_MPC_CNTL,4,2             ; @mmUVD_MPC_CNTL
	.comm	_UVD_MPC_CNTL__REPLACEMENT_MODE_MASK,4,2 ; @UVD_MPC_CNTL__REPLACEMENT_MODE_MASK
	.comm	_UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT,4,2 ; @UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT
	.comm	_mmUVD_MPC_SET_MUXA0,4,2        ; @mmUVD_MPC_SET_MUXA0
	.comm	_UVD_MPC_SET_MUXA0__VARA_1__SHIFT,4,2 ; @UVD_MPC_SET_MUXA0__VARA_1__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_2__SHIFT,4,2 ; @UVD_MPC_SET_MUXA0__VARA_2__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_3__SHIFT,4,2 ; @UVD_MPC_SET_MUXA0__VARA_3__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_4__SHIFT,4,2 ; @UVD_MPC_SET_MUXA0__VARA_4__SHIFT
	.comm	_mmUVD_MPC_SET_MUXB0,4,2        ; @mmUVD_MPC_SET_MUXB0
	.comm	_UVD_MPC_SET_MUXB0__VARB_1__SHIFT,4,2 ; @UVD_MPC_SET_MUXB0__VARB_1__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_2__SHIFT,4,2 ; @UVD_MPC_SET_MUXB0__VARB_2__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_3__SHIFT,4,2 ; @UVD_MPC_SET_MUXB0__VARB_3__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_4__SHIFT,4,2 ; @UVD_MPC_SET_MUXB0__VARB_4__SHIFT
	.comm	_mmUVD_MPC_SET_MUX,4,2          ; @mmUVD_MPC_SET_MUX
	.comm	_UVD_MPC_SET_MUX__SET_0__SHIFT,4,2 ; @UVD_MPC_SET_MUX__SET_0__SHIFT
	.comm	_UVD_MPC_SET_MUX__SET_1__SHIFT,4,2 ; @UVD_MPC_SET_MUX__SET_1__SHIFT
	.comm	_UVD_MPC_SET_MUX__SET_2__SHIFT,4,2 ; @UVD_MPC_SET_MUX__SET_2__SHIFT
	.comm	_mmUVD_REG_XX_MASK,4,2          ; @mmUVD_REG_XX_MASK
	.comm	_mmUVD_RBC_XX_IB_REG_CHECK,4,2  ; @mmUVD_RBC_XX_IB_REG_CHECK
	.comm	_mmUVD_VCPU_CNTL,4,2            ; @mmUVD_VCPU_CNTL
	.comm	_UVD_VCPU_CNTL__CLK_EN_MASK,4,2 ; @UVD_VCPU_CNTL__CLK_EN_MASK
	.comm	_mmUVD_SOFT_RESET,4,2           ; @mmUVD_SOFT_RESET
	.comm	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
	.comm	_mmUVD_LMI_CTRL2,4,2            ; @mmUVD_LMI_CTRL2
	.comm	_UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,4,2 ; @UVD_LMI_CTRL2__STALL_ARB_UMC_MASK
	.comm	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
	.comm	_UVD_STATUS__IDLE,4,2           ; @UVD_STATUS__IDLE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"VCN decode not responding, trying to reset the VCPU!!!\n"

l_.str.1:                               ; @.str.1
	.asciz	"VCN decode not responding, giving up!!!\n"

	.comm	_mmUVD_SYS_INT_EN,4,2           ; @mmUVD_SYS_INT_EN
	.comm	_UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,4,2 ; @UVD_SYS_INT_EN__UVD_JRBC_EN_MASK
	.comm	_UVD_RBC_RB_CNTL,4,2            ; @UVD_RBC_RB_CNTL
	.comm	_RB_BUFSZ,4,2                   ; @RB_BUFSZ
	.comm	_RB_BLKSZ,4,2                   ; @RB_BLKSZ
	.comm	_RB_NO_FETCH,4,2                ; @RB_NO_FETCH
	.comm	_RB_NO_UPDATE,4,2               ; @RB_NO_UPDATE
	.comm	_RB_RPTR_WR_EN,4,2              ; @RB_RPTR_WR_EN
	.comm	_mmUVD_RBC_RB_CNTL,4,2          ; @mmUVD_RBC_RB_CNTL
	.comm	_mmUVD_RBC_RB_WPTR_CNTL,4,2     ; @mmUVD_RBC_RB_WPTR_CNTL
	.comm	_mmUVD_RBC_RB_RPTR_ADDR,4,2     ; @mmUVD_RBC_RB_RPTR_ADDR
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
	.comm	_mmUVD_RBC_RB_RPTR,4,2          ; @mmUVD_RBC_RB_RPTR
	.comm	_mmUVD_SCRATCH2,4,2             ; @mmUVD_SCRATCH2
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ; @mmUVD_RBC_RB_WPTR
	.comm	_UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK,4,2 ; @UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK
	.comm	_mmUVD_RB_RPTR,4,2              ; @mmUVD_RB_RPTR
	.comm	_mmUVD_RB_WPTR,4,2              ; @mmUVD_RB_WPTR
	.comm	_mmUVD_RB_BASE_LO,4,2           ; @mmUVD_RB_BASE_LO
	.comm	_mmUVD_RB_BASE_HI,4,2           ; @mmUVD_RB_BASE_HI
	.comm	_mmUVD_RB_SIZE,4,2              ; @mmUVD_RB_SIZE
	.comm	_mmUVD_RB_RPTR2,4,2             ; @mmUVD_RB_RPTR2
	.comm	_mmUVD_RB_WPTR2,4,2             ; @mmUVD_RB_WPTR2
	.comm	_mmUVD_RB_BASE_LO2,4,2          ; @mmUVD_RB_BASE_LO2
	.comm	_mmUVD_RB_BASE_HI2,4,2          ; @mmUVD_RB_BASE_HI2
	.comm	_mmUVD_RB_SIZE2,4,2             ; @mmUVD_RB_SIZE2
	.comm	_mmUVD_LMI_JRBC_RB_VMID,4,2     ; @mmUVD_LMI_JRBC_RB_VMID
	.comm	_mmUVD_JRBC_RB_CNTL,4,2         ; @mmUVD_JRBC_RB_CNTL
	.comm	_UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK,4,2 ; @UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK
	.comm	_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK,4,2 ; @UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK
	.comm	_mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH
	.comm	_mmUVD_JRBC_RB_RPTR,4,2         ; @mmUVD_JRBC_RB_RPTR
	.comm	_mmUVD_JRBC_RB_WPTR,4,2         ; @mmUVD_JRBC_RB_WPTR
	.comm	_amdgpu_sched_hw_submission,4,2 ; @amdgpu_sched_hw_submission
	.no_dead_strip	_vcn_v1_0_start_spg_mode
.subsections_via_symbols
