	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4                               ## -- Begin function amdgpu_atombios_get_clock_info
LCPI0_0:
	.long	9                               ## 0x9
	.long	2                               ## 0x2
	.long	1023                            ## 0x3ff
	.long	4                               ## 0x4
LCPI0_1:
	.long	2                               ## 0x2
	.long	255                             ## 0xff
	.long	4                               ## 0x4
	.long	255                             ## 0xff
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_amdgpu_atombios_get_clock_info
	.p2align	4, 0x90
_amdgpu_atombios_get_clock_info:        ## @amdgpu_atombios_get_clock_info
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	subq	$16, %rsp
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	_DATA@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_FirmwareInfo@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_GetIndexIntoMasterTable
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%r14d, %r14d
	subl	(%rcx), %r14d
	movq	224(%r12), %rdi
	leaq	-48(%rbp), %rcx
	leaq	-44(%rbp), %r8
	leaq	-40(%rbp), %r9
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_amdgpu_atom_parse_data_header
	testq	%rax, %rax
	je	LBB0_20
## %bb.1:
	movq	32(%r12), %rbx
	movq	224(%r12), %rax
	movq	(%rax), %r14
	movq	-40(%rbp), %r15
	movl	60(%r15,%r14), %edi
	callq	_le16_to_cpu
	movl	%eax, (%rbx)
	movq	$0, 64(%rbx)
	movl	(%r15,%r14), %edi
	callq	_le32_to_cpu
	movl	%eax, 4(%rbx)
	movl	56(%r15,%r14), %edi
	callq	_le32_to_cpu
	movl	%eax, 8(%rbx)
	movl	4(%r15,%r14), %edi
	callq	_le16_to_cpu
	imull	$100, %eax, %ecx
	movl	%ecx, 12(%rbx)
	testl	%eax, %eax
	jne	LBB0_3
## %bb.2:
	movl	4(%rbx), %eax
	movl	%eax, 12(%rbx)
LBB0_3:
	movl	(%r14,%r15), %edi
	callq	_le16_to_cpu
	imull	$100, %eax, %ecx
	movl	%ecx, 16(%rbx)
	testl	%eax, %eax
	je	LBB0_4
## %bb.5:
	cmpl	$0, 4(%rbx)
	jne	LBB0_7
LBB0_6:
	movl	$64800, 4(%rbx)                 ## imm = 0xFD20
LBB0_7:
	movl	52(%r14,%r15), %edi
	callq	_le16_to_cpu
	movl	%eax, 20(%rbx)
	movl	48(%r14,%r15), %edi
	callq	_le16_to_cpu
	movl	%eax, 24(%rbx)
	movabsq	$545460846594, %rax             ## imm = 0x7F00000002
	movq	%rax, 28(%rbx)
	movq	$0, 72(%rbx)
	movaps	LCPI0_0(%rip), %xmm0            ## xmm0 = [9,2,1023,4]
	movups	%xmm0, 36(%rbx)
	movl	$4095, 52(%rbx)                 ## imm = 0xFFF
	movq	$0, 56(%rbx)
	movq	_AMDGPU_MAX_PPLL@GOTPCREL(%rip), %rax
	cmpl	$2, (%rax)
	jl	LBB0_10
## %bb.8:
	movl	$1, %ecx
	movl	$80, %edx
	.p2align	4, 0x90
LBB0_9:                                 ## =>This Inner Loop Header: Depth=1
	movq	32(%r12), %rsi
	movups	64(%rbx), %xmm0
	movups	%xmm0, 64(%rsi,%rdx)
	movups	(%rbx), %xmm0
	movups	16(%rbx), %xmm1
	movups	32(%rbx), %xmm2
	movups	48(%rbx), %xmm3
	movups	%xmm3, 48(%rsi,%rdx)
	movups	%xmm2, 32(%rsi,%rdx)
	movups	%xmm1, 16(%rsi,%rdx)
	movups	%xmm0, (%rsi,%rdx)
	incq	%rcx
	movslq	(%rax), %rsi
	addq	$80, %rdx
	cmpq	%rsi, %rcx
	jl	LBB0_9
LBB0_10:
	movl	12(%r14,%r15), %edi
	callq	_le16_to_cpu
	movl	%eax, 120(%r12)
	movq	$0, 184(%r12)
	movl	44(%r14,%r15), %edi
	callq	_le16_to_cpu
	movl	%eax, 124(%r12)
	movl	40(%r14,%r15), %edi
	callq	_le32_to_cpu
	movl	%eax, 128(%r12)
	cmpl	$0, 124(%r12)
	jne	LBB0_12
## %bb.11:
	movl	$64800, 124(%r12)               ## imm = 0xFD20
LBB0_12:
	movl	36(%r14,%r15), %edi
	callq	_le16_to_cpu
	movl	%eax, 140(%r12)
	movl	32(%r14,%r15), %edi
	callq	_le16_to_cpu
	movl	%eax, 144(%r12)
	movabsq	$4294967297, %rbx               ## imm = 0x100000001
	movq	%rbx, 148(%r12)
	movaps	LCPI0_1(%rip), %xmm0            ## xmm0 = [2,255,4,255]
	movups	%xmm0, 160(%r12)
	movq	$0, 176(%r12)
	movl	8(%r14,%r15), %edi
	callq	_le16_to_cpu
	movl	%eax, 40(%r12)
	movq	$0, 104(%r12)
	movl	28(%r14,%r15), %edi
	callq	_le16_to_cpu
	movl	%eax, 44(%r12)
	movl	24(%r14,%r15), %edi
	callq	_le32_to_cpu
	movl	%eax, 48(%r12)
	cmpl	$0, 44(%r12)
	jne	LBB0_14
## %bb.13:
	movl	$64800, 44(%r12)                ## imm = 0xFD20
LBB0_14:
	movl	20(%r14,%r15), %edi
	callq	_le16_to_cpu
	movl	%eax, 60(%r12)
	movl	16(%r14,%r15), %edi
	callq	_le16_to_cpu
	movl	%eax, 64(%r12)
	movl	12(%r14,%r15), %edi
	callq	_le32_to_cpu
	movq	%rax, 24(%r12)
	movl	8(%r14,%r15), %edi
	callq	_le32_to_cpu
	movq	%rax, 16(%r12)
	movq	%rbx, 68(%r12)
	movaps	LCPI0_1(%rip), %xmm0            ## xmm0 = [2,255,4,255]
	movups	%xmm0, 80(%r12)
	movq	$0, 96(%r12)
	movl	4(%r14,%r15), %edi
	callq	_le32_to_cpu
	movl	%eax, (%r12)
	cmpl	$53899, %eax                    ## imm = 0xD28B
	jg	LBB0_16
## %bb.15:
	cltq
	imulq	$1374389535, %rax, %rsi         ## imm = 0x51EB851F
	movq	%rsi, %rax
	shrq	$63, %rax
	sarq	$37, %rsi
	addl	%eax, %esi
	leaq	L_.str(%rip), %rdi
                                        ## kill: def $esi killed $esi killed $rsi
	callq	_DRM_DEBUG
	movl	$60000, %eax                    ## imm = 0xEA60
	jmp	LBB0_18
LBB0_16:
	cmpl	$60000, %eax                    ## imm = 0xEA60
	ja	LBB0_19
## %bb.17:
	movzwl	%ax, %eax
	shrl	$2, %eax
	imull	$5243, %eax, %esi               ## imm = 0x147B
	shrl	$17, %esi
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_DEBUG
	movl	$62500, %eax                    ## imm = 0xF424
LBB0_18:
	movl	%eax, (%r12)
LBB0_19:
	movl	(%r14,%r15), %edi
	callq	_le16_to_cpu
	movl	%eax, 4(%r12)
	movl	(%r12), %eax
	movl	%eax, 8(%r12)
	movl	4(%r14,%r15), %edi
	callq	_le16_to_cpu
	testl	%eax, %eax
	movl	$40000, %ecx                    ## imm = 0x9C40
	cmovnel	%eax, %ecx
	movl	%ecx, 12(%r12)
	movl	(%r14,%r15), %edi
	callq	_le16_to_cpu
	movl	%eax, 216(%r12)
	xorl	%r14d, %r14d
LBB0_20:
	movups	16(%r12), %xmm0
	movups	%xmm0, 200(%r12)
	movl	%r14d, %eax
	addq	$16, %rsp
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_4:
	movl	8(%rbx), %eax
	movl	%eax, 16(%rbx)
	cmpl	$0, 4(%rbx)
	jne	LBB0_7
	jmp	LBB0_6
	.cfi_endproc
                                        ## -- End function
	.comm	_DATA,4,2                       ## @DATA
	.comm	_FirmwareInfo,4,2               ## @FirmwareInfo
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_AMDGPU_MAX_PPLL,4,2            ## @AMDGPU_MAX_PPLL
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Changing default dispclk from %dMhz to 600Mhz\n"

L_.str.1:                               ## @.str.1
	.asciz	"Changing default dispclk from %dMhz to 625Mhz\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3                               ; -- Begin function amdgpu_atombios_get_clock_info
lCPI0_0:
	.long	2                               ; 0x2
	.long	127                             ; 0x7f
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4
lCPI0_1:
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	1023                            ; 0x3ff
	.long	4                               ; 0x4
lCPI0_2:
	.long	2                               ; 0x2
	.long	255                             ; 0xff
	.long	4                               ; 0x4
	.long	255                             ; 0xff
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_amdgpu_atombios_get_clock_info
	.p2align	2
_amdgpu_atombios_get_clock_info:        ; @amdgpu_atombios_get_clock_info
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	d9, d8, [sp, #32]               ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset b8, -56
	.cfi_offset b9, -64
	mov	x19, x0
Lloh0:
	adrp	x8, _DATA@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DATA@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
Lloh3:
	adrp	x8, _FirmwareInfo@GOTPAGE
Lloh4:
	ldr	x8, [x8, _FirmwareInfo@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	bl	_GetIndexIntoMasterTable
	mov	x1, x0
Lloh6:
	adrp	x8, _EINVAL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh8:
	ldr	w20, [x8]
	ldr	x0, [x19, #224]
	add	x3, sp, #28
	add	x4, sp, #24
	add	x5, sp, #16
	mov	x2, #0
	bl	_amdgpu_atom_parse_data_header
	cbz	x0, LBB0_15
; %bb.1:
	ldr	x21, [x19, #32]
	ldr	x8, [x19, #224]
	ldr	x8, [x8]
	ldr	x9, [sp, #16]
	add	x20, x9, x8
	ldr	w0, [x20, #60]
	bl	_le16_to_cpu
	str	w0, [x21]
	str	xzr, [x21, #64]
	ldr	w0, [x20]
	bl	_le32_to_cpu
	str	w0, [x21, #4]
	ldr	w0, [x20, #56]
	bl	_le32_to_cpu
	str	w0, [x21, #8]
	ldr	w0, [x20, #4]
	bl	_le16_to_cpu
	mov	w22, #100
	mul	w8, w0, w22
	str	w8, [x21, #12]
	cbnz	w0, LBB0_3
; %bb.2:
	ldr	w8, [x21, #4]
	str	w8, [x21, #12]
LBB0_3:
	ldr	w0, [x20]
	bl	_le16_to_cpu
	mul	w8, w0, w22
	str	w8, [x21, #16]
	cbz	w0, LBB0_21
; %bb.4:
	ldr	w8, [x21, #4]
	cbnz	w8, LBB0_6
LBB0_5:
	mov	w8, #64800
	str	w8, [x21, #4]
LBB0_6:
	ldr	w0, [x20, #52]
	bl	_le16_to_cpu
	str	w0, [x21, #20]
	ldr	w0, [x20, #48]
	bl	_le16_to_cpu
	str	w0, [x21, #24]
Lloh9:
	adrp	x8, lCPI0_0@PAGE
Lloh10:
	ldr	d0, [x8, lCPI0_0@PAGEOFF]
	stur	d0, [x21, #28]
	str	xzr, [x21, #72]
Lloh11:
	adrp	x8, lCPI0_1@PAGE
Lloh12:
	ldr	q0, [x8, lCPI0_1@PAGEOFF]
	stur	q0, [x21, #36]
	mov	w8, #4095
	str	w8, [x21, #52]
	str	xzr, [x21, #56]
Lloh13:
	adrp	x8, _AMDGPU_MAX_PPLL@GOTPAGE
Lloh14:
	ldr	x8, [x8, _AMDGPU_MAX_PPLL@GOTPAGEOFF]
	ldr	w9, [x8]
	cmp	w9, #2
	b.lt	LBB0_9
; %bb.7:
	mov	w9, #1
	mov	w10, #80
LBB0_8:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x11, [x19, #32]
	add	x11, x11, x10
	ldr	q0, [x21]
	str	q0, [x11]
	ldp	q0, q1, [x21, #16]
	ldp	q2, q3, [x21, #48]
	stp	q2, q3, [x11, #48]
	stp	q0, q1, [x11, #16]
	add	x9, x9, #1
	ldrsw	x11, [x8]
	add	x10, x10, #80
	cmp	x9, x11
	b.lt	LBB0_8
LBB0_9:
	ldr	w0, [x20, #12]
	bl	_le16_to_cpu
	str	w0, [x19, #120]
	str	xzr, [x19, #184]
	ldr	w0, [x20, #44]
	bl	_le16_to_cpu
	str	w0, [x19, #124]
	ldr	w0, [x20, #40]
	bl	_le32_to_cpu
	str	w0, [x19, #128]
	ldr	w8, [x19, #124]
	cbnz	w8, LBB0_11
; %bb.10:
	mov	w8, #64800
	str	w8, [x19, #124]
LBB0_11:
	ldr	w0, [x20, #36]
	bl	_le16_to_cpu
	str	w0, [x19, #140]
	ldr	w0, [x20, #32]
	bl	_le16_to_cpu
	str	w0, [x19, #144]
	movi.2s	v8, #1
	stur	d8, [x19, #148]
Lloh15:
	adrp	x8, lCPI0_2@PAGE
Lloh16:
	ldr	q0, [x8, lCPI0_2@PAGEOFF]
	str	q0, [sp]                        ; 16-byte Folded Spill
	str	q0, [x19, #160]
	str	xzr, [x19, #176]
	ldr	w0, [x20, #8]
	bl	_le16_to_cpu
	str	w0, [x19, #40]
	str	xzr, [x19, #104]
	ldr	w0, [x20, #28]
	bl	_le16_to_cpu
	str	w0, [x19, #44]
	ldr	w0, [x20, #24]
	bl	_le32_to_cpu
	str	w0, [x19, #48]
	ldr	w8, [x19, #44]
	cbnz	w8, LBB0_13
; %bb.12:
	mov	w8, #64800
	str	w8, [x19, #44]
LBB0_13:
	ldr	w0, [x20, #20]
	bl	_le16_to_cpu
	str	w0, [x19, #60]
	ldr	w0, [x20, #16]
	bl	_le16_to_cpu
	str	w0, [x19, #64]
	ldr	w0, [x20, #12]
	bl	_le32_to_cpu
	str	x0, [x19, #24]
	ldr	w0, [x20, #8]
	bl	_le32_to_cpu
	str	x0, [x19, #16]
	stur	d8, [x19, #68]
	ldr	q0, [sp]                        ; 16-byte Folded Reload
	str	q0, [x19, #80]
	str	xzr, [x19, #96]
	ldr	w0, [x20, #4]
	bl	_le32_to_cpu
	str	w0, [x19]
	mov	w8, #53899
	cmp	w0, w8
	b.gt	LBB0_16
; %bb.14:
	mov	w8, #34079
	movk	w8, #20971, lsl #16
	smull	x8, w0, w8
	lsr	x9, x8, #63
	asr	x8, x8, #37
	add	w1, w8, w9
Lloh17:
	adrp	x0, l_.str@PAGE
Lloh18:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG
	mov	w8, #60000
	b	LBB0_18
LBB0_15:
	neg	w0, w20
	b	LBB0_20
LBB0_16:
	mov	w8, #60000
	cmp	w0, w8
	b.hi	LBB0_19
; %bb.17:
	ubfx	w8, w0, #2, #14
	mov	w9, #5243
	mul	w8, w8, w9
	lsr	w1, w8, #17
Lloh19:
	adrp	x0, l_.str.1@PAGE
Lloh20:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_DEBUG
	mov	w8, #62500
LBB0_18:
	str	w8, [x19]
LBB0_19:
	ldr	w0, [x20]
	bl	_le16_to_cpu
	ldr	w8, [x19]
	stp	w0, w8, [x19, #4]
	ldr	w0, [x20, #4]
	bl	_le16_to_cpu
	mov	w8, #40000
	cmp	w0, #0
	csel	w8, w8, w0, eq
	str	w8, [x19, #12]
	ldr	w0, [x20]
	bl	_le16_to_cpu
	mov	x8, x0
	mov	w0, #0
	str	w8, [x19, #216]
LBB0_20:
	ldp	x9, x8, [x19, #16]
	stp	x9, x8, [x19, #200]
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	d9, d8, [sp, #32]               ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_21:
	ldr	w8, [x21, #8]
	str	w8, [x21, #16]
	ldr	w8, [x21, #4]
	cbnz	w8, LBB0_6
	b	LBB0_5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdr	Lloh11, Lloh12
	.loh AdrpAdrp	Lloh9, Lloh11
	.loh AdrpLdr	Lloh9, Lloh10
	.loh AdrpLdr	Lloh15, Lloh16
	.loh AdrpAdd	Lloh17, Lloh18
	.loh AdrpAdd	Lloh19, Lloh20
	.cfi_endproc
                                        ; -- End function
	.comm	_DATA,4,2                       ; @DATA
	.comm	_FirmwareInfo,4,2               ; @FirmwareInfo
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_AMDGPU_MAX_PPLL,4,2            ; @AMDGPU_MAX_PPLL
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Changing default dispclk from %dMhz to 600Mhz\n"

l_.str.1:                               ; @.str.1
	.asciz	"Changing default dispclk from %dMhz to 625Mhz\n"

.subsections_via_symbols
