	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v8_0_sw_init
_gfx_v8_0_sw_init:                      ## @gfx_v8_0_sw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movl	(%rdi), %eax
	addl	$-128, %eax
	movl	$1, %ecx
	cmpl	$8, %eax
	ja	LBB0_2
## %bb.1:
	cltq
	leaq	l_switch.table.gfx_v8_0_sw_init(%rip), %rcx
	movl	(%rcx,%rax,4), %ecx
LBB0_2:
	movl	%ecx, 24(%r15)
	movabsq	$34359738372, %rax              ## imm = 0x800000004
	movq	%rax, 28(%r15)
	movq	_AMDGPU_IRQ_CLIENTID_LEGACY@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	_VISLANDS30_IV_SRCID_CP_END_OF_PIPE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	leaq	36(%r15), %r14
	movq	%r15, %rdi
	movq	%r14, %rcx
	callq	_amdgpu_irq_add_id
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_15
## %bb.3:
	movl	(%r12), %esi
	movq	_VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	leaq	76(%r15), %rcx
	movq	%r15, %rdi
	callq	_amdgpu_irq_add_id
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_15
## %bb.4:
	movl	(%r12), %esi
	movq	_VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	leaq	72(%r15), %rcx
	movq	%r15, %rdi
	callq	_amdgpu_irq_add_id
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_15
## %bb.5:
	movl	(%r12), %esi
	movq	_VISLANDS30_IV_SRCID_CP_ECC_ERROR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	leaq	68(%r15), %rcx
	movq	%r15, %rdi
	callq	_amdgpu_irq_add_id
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_15
## %bb.6:
	movl	(%r12), %esi
	movq	_VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	leaq	64(%r15), %rcx
	movq	%r15, %rdi
	callq	_amdgpu_irq_add_id
	testl	%eax, %eax
	je	LBB0_8
## %bb.7:
	movl	%eax, %ebx
	leaq	L_.str(%rip), %rdi
	movl	%eax, %esi
	xorl	%eax, %eax
	callq	_DRM_ERROR
	jmp	LBB0_15
LBB0_8:
	leaq	60(%r15), %rdi
	movq	_gfx_v8_0_sq_irq_work_func@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_WORK
	movq	_AMDGPU_GFX_NORMAL_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 56(%r15)
	movq	%r15, %rdi
	callq	_gfx_v8_0_scratch_init
	movq	%r15, %rdi
	callq	_gfx_v8_0_init_microcode
	testl	%eax, %eax
	je	LBB0_10
## %bb.9:
	movl	%eax, %ebx
	leaq	L_.str.1(%rip), %rdi
	jmp	LBB0_14
LBB0_10:
	movq	48(%r15), %rax
	movq	%r15, %rdi
	callq	*(%rax)
	testl	%eax, %eax
	je	LBB0_12
## %bb.11:
	movl	%eax, %ebx
	leaq	L_.str.2(%rip), %rdi
	jmp	LBB0_14
LBB0_12:
	movq	%r15, %rdi
	callq	_gfx_v8_0_mec_init
	testl	%eax, %eax
	je	LBB0_16
## %bb.13:
	movl	%eax, %ebx
	leaq	L_.str.3(%rip), %rdi
LBB0_14:
	xorl	%eax, %eax
	callq	_DRM_ERROR
LBB0_15:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_16:
	cmpl	$0, 8(%r15)
	jle	LBB0_22
## %bb.17:
	xorl	%r13d, %r13d
	xorl	%r12d, %r12d
LBB0_18:                                ## =>This Inner Loop Header: Depth=1
	movq	40(%r15), %rbx
	leaq	(%rbx,%r13), %rax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movq	$0, 16(%rbx,%r13)
	movl	8(%rbx,%r13), %edi
	leaq	L_.str.4(%rip), %rsi
	callq	_sprintf
	cmpl	$129, (%r15)
	je	LBB0_20
## %bb.19:                              ##   in Loop: Header=BB0_18 Depth=1
	movl	$1, (%rbx,%r13)
	movl	80(%r15), %eax
	movl	%eax, 4(%rbx,%r13)
LBB0_20:                                ##   in Loop: Header=BB0_18 Depth=1
	movq	_AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	movq	%r15, %rdi
	movq	-48(%rbp), %rsi                 ## 8-byte Reload
	movl	$1024, %edx                     ## imm = 0x400
	movq	%r14, %rcx
	callq	_amdgpu_ring_init
	testl	%eax, %eax
	jne	LBB0_39
## %bb.21:                              ##   in Loop: Header=BB0_18 Depth=1
	incq	%r12
	movslq	8(%r15), %rax
	addq	$24, %r13
	cmpq	%rax, %r12
	jl	LBB0_18
LBB0_22:
	movl	24(%r15), %ecx
	testl	%ecx, %ecx
	jle	LBB0_36
## %bb.23:
	movl	32(%r15), %eax
	movl	$0, -48(%rbp)                   ## 4-byte Folded Spill
	xorl	%r12d, %r12d
LBB0_24:                                ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_28 Depth 2
                                        ##       Child Loop BB0_31 Depth 3
	testl	%eax, %eax
	jle	LBB0_35
## %bb.25:                              ##   in Loop: Header=BB0_24 Depth=1
	movl	28(%r15), %ecx
	xorl	%ebx, %ebx
	jmp	LBB0_28
LBB0_26:                                ##   in Loop: Header=BB0_28 Depth=2
	movl	32(%r15), %eax
LBB0_27:                                ##   in Loop: Header=BB0_28 Depth=2
	incl	%ebx
	cmpl	%eax, %ebx
	jge	LBB0_34
LBB0_28:                                ##   Parent Loop BB0_24 Depth=1
                                        ## =>  This Loop Header: Depth=2
                                        ##       Child Loop BB0_31 Depth 3
	testl	%ecx, %ecx
	jle	LBB0_27
## %bb.29:                              ##   in Loop: Header=BB0_28 Depth=2
	xorl	%r14d, %r14d
	jmp	LBB0_31
LBB0_30:                                ##   in Loop: Header=BB0_31 Depth=3
	incl	%r14d
	movl	28(%r15), %ecx
	cmpl	%ecx, %r14d
	jge	LBB0_26
LBB0_31:                                ##   Parent Loop BB0_24 Depth=1
                                        ##     Parent Loop BB0_28 Depth=2
                                        ## =>    This Inner Loop Header: Depth=3
	movq	%r15, %rdi
	movl	-48(%rbp), %esi                 ## 4-byte Reload
	movl	%r14d, %edx
	movl	%ebx, %ecx
	callq	_amdgpu_gfx_is_mec_queue_enabled
	testl	%eax, %eax
	je	LBB0_30
## %bb.32:                              ##   in Loop: Header=BB0_31 Depth=3
	movq	%r15, %rdi
	movl	%r12d, %esi
	movl	-48(%rbp), %edx                 ## 4-byte Reload
	movl	%r14d, %ecx
	movl	%ebx, %r13d
	movl	%ebx, %r8d
	callq	_gfx_v8_0_compute_ring_init
	testl	%eax, %eax
	jne	LBB0_39
## %bb.33:                              ##   in Loop: Header=BB0_31 Depth=3
	incl	%r12d
	movl	%r13d, %ebx
	jmp	LBB0_30
LBB0_34:                                ##   in Loop: Header=BB0_24 Depth=1
	movl	24(%r15), %ecx
LBB0_35:                                ##   in Loop: Header=BB0_24 Depth=1
	movl	-48(%rbp), %edx                 ## 4-byte Reload
	incl	%edx
	movl	%edx, -48(%rbp)                 ## 4-byte Spill
	cmpl	%ecx, %edx
	jl	LBB0_24
LBB0_36:
	movq	_GFX8_MEC_HPD_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_amdgpu_gfx_kiq_init
	testl	%eax, %eax
	je	LBB0_40
## %bb.37:
	movl	%eax, %ebx
	leaq	L_.str.5(%rip), %rdi
	jmp	LBB0_14
LBB0_39:
	movl	%eax, %ebx
	jmp	LBB0_15
LBB0_40:
	leaq	16(%r15), %rdx
	leaq	20(%r15), %rsi
	movq	%r15, %rdi
	callq	_amdgpu_gfx_kiq_init_ring
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_15
## %bb.41:
	movq	%r15, %rdi
	movl	$4, %esi
	callq	_amdgpu_gfx_mqd_sw_init
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_15
## %bb.42:
	movl	$32768, 12(%r15)                ## imm = 0x8000
	movq	%r15, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_gfx_v8_0_gpu_early_init        ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_IRQ_CLIENTID_LEGACY,4,2 ## @AMDGPU_IRQ_CLIENTID_LEGACY
	.comm	_VISLANDS30_IV_SRCID_CP_END_OF_PIPE,4,2 ## @VISLANDS30_IV_SRCID_CP_END_OF_PIPE
	.comm	_VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT,4,2 ## @VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT
	.comm	_VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT,4,2 ## @VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT
	.comm	_VISLANDS30_IV_SRCID_CP_ECC_ERROR,4,2 ## @VISLANDS30_IV_SRCID_CP_ECC_ERROR
	.comm	_VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG,4,2 ## @VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"amdgpu_irq_add() for SQ failed: %d\n"

	.comm	_gfx_v8_0_sq_irq_work_func,4,2  ## @gfx_v8_0_sq_irq_work_func
	.comm	_AMDGPU_GFX_NORMAL_MODE,4,2     ## @AMDGPU_GFX_NORMAL_MODE
L_.str.1:                               ## @.str.1
	.asciz	"Failed to load gfx firmware!\n"

L_.str.2:                               ## @.str.2
	.asciz	"Failed to init rlc BOs!\n"

L_.str.3:                               ## @.str.3
	.asciz	"Failed to init MEC BOs!\n"

L_.str.4:                               ## @.str.4
	.asciz	"gfx"

	.comm	_AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP,4,2 ## @AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP
	.comm	_GFX8_MEC_HPD_SIZE,4,2          ## @GFX8_MEC_HPD_SIZE
L_.str.5:                               ## @.str.5
	.asciz	"Failed to init KIQ BOs!\n"

	.no_dead_strip	_gfx_v8_0_sw_init
	.section	__TEXT,__const
	.p2align	2                               ## @switch.table.gfx_v8_0_sw_init
l_switch.table.gfx_v8_0_sw_init:
	.long	2                               ## 0x2
	.long	1                               ## 0x1
	.long	2                               ## 0x2
	.long	1                               ## 0x1
	.long	2                               ## 0x2
	.long	2                               ## 0x2
	.long	2                               ## 0x2
	.long	2                               ## 0x2
	.long	2                               ## 0x2

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3                               ; -- Begin function gfx_v8_0_sw_init
lCPI0_0:
	.long	4                               ; 0x4
	.long	8                               ; 0x8
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	2
_gfx_v8_0_sw_init:                      ; @gfx_v8_0_sw_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldr	w8, [x0]
	sub	w8, w8, #128
	cmp	w8, #8
	b.hi	LBB0_2
; %bb.1:
Lloh0:
	adrp	x9, l_switch.table.gfx_v8_0_sw_init@PAGE
Lloh1:
	add	x9, x9, l_switch.table.gfx_v8_0_sw_init@PAGEOFF
	ldr	w8, [x9, w8, sxtw #2]
	b	LBB0_3
LBB0_2:
	mov	w8, #1
LBB0_3:
	str	w8, [x19, #24]
Lloh2:
	adrp	x8, lCPI0_0@PAGE
Lloh3:
	ldr	d0, [x8, lCPI0_0@PAGEOFF]
Lloh4:
	adrp	x21, _AMDGPU_IRQ_CLIENTID_LEGACY@GOTPAGE
Lloh5:
	ldr	x21, [x21, _AMDGPU_IRQ_CLIENTID_LEGACY@GOTPAGEOFF]
	stur	d0, [x19, #28]
	ldr	w1, [x21]
Lloh6:
	adrp	x8, _VISLANDS30_IV_SRCID_CP_END_OF_PIPE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _VISLANDS30_IV_SRCID_CP_END_OF_PIPE@GOTPAGEOFF]
Lloh8:
	ldr	w2, [x8]
	add	x20, x19, #36
	mov	x0, x19
	mov	x3, x20
	bl	_amdgpu_irq_add_id
	mov	x22, x0
	cbnz	w0, LBB0_16
; %bb.4:
	ldr	w1, [x21]
Lloh9:
	adrp	x8, _VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT@GOTPAGE
Lloh10:
	ldr	x8, [x8, _VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT@GOTPAGEOFF]
Lloh11:
	ldr	w2, [x8]
	add	x3, x19, #76
	mov	x0, x19
	bl	_amdgpu_irq_add_id
	mov	x22, x0
	cbnz	w0, LBB0_16
; %bb.5:
	ldr	w1, [x21]
Lloh12:
	adrp	x8, _VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT@GOTPAGE
Lloh13:
	ldr	x8, [x8, _VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT@GOTPAGEOFF]
Lloh14:
	ldr	w2, [x8]
	add	x3, x19, #72
	mov	x0, x19
	bl	_amdgpu_irq_add_id
	mov	x22, x0
	cbnz	w0, LBB0_16
; %bb.6:
	ldr	w1, [x21]
Lloh15:
	adrp	x8, _VISLANDS30_IV_SRCID_CP_ECC_ERROR@GOTPAGE
Lloh16:
	ldr	x8, [x8, _VISLANDS30_IV_SRCID_CP_ECC_ERROR@GOTPAGEOFF]
Lloh17:
	ldr	w2, [x8]
	add	x3, x19, #68
	mov	x0, x19
	bl	_amdgpu_irq_add_id
	mov	x22, x0
	cbnz	w0, LBB0_16
; %bb.7:
	ldr	w1, [x21]
Lloh18:
	adrp	x8, _VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG@GOTPAGE
Lloh19:
	ldr	x8, [x8, _VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG@GOTPAGEOFF]
Lloh20:
	ldr	w2, [x8]
	add	x3, x19, #64
	mov	x0, x19
	bl	_amdgpu_irq_add_id
	cbz	w0, LBB0_9
; %bb.8:
	mov	x22, x0
	str	x22, [sp]
Lloh21:
	adrp	x0, l_.str@PAGE
Lloh22:
	add	x0, x0, l_.str@PAGEOFF
	b	LBB0_15
LBB0_9:
	add	x0, x19, #60
Lloh23:
	adrp	x8, _gfx_v8_0_sq_irq_work_func@GOTPAGE
Lloh24:
	ldr	x8, [x8, _gfx_v8_0_sq_irq_work_func@GOTPAGEOFF]
Lloh25:
	ldr	w1, [x8]
	bl	_INIT_WORK
Lloh26:
	adrp	x8, _AMDGPU_GFX_NORMAL_MODE@GOTPAGE
Lloh27:
	ldr	x8, [x8, _AMDGPU_GFX_NORMAL_MODE@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
	str	w8, [x19, #56]
	mov	x0, x19
	bl	_gfx_v8_0_scratch_init
	mov	x0, x19
	bl	_gfx_v8_0_init_microcode
	cbz	w0, LBB0_11
; %bb.10:
	mov	x22, x0
Lloh29:
	adrp	x0, l_.str.1@PAGE
Lloh30:
	add	x0, x0, l_.str.1@PAGEOFF
	b	LBB0_15
LBB0_11:
	ldr	x8, [x19, #48]
	ldr	x8, [x8]
	mov	x0, x19
	blr	x8
	cbz	w0, LBB0_13
; %bb.12:
	mov	x22, x0
Lloh31:
	adrp	x0, l_.str.2@PAGE
Lloh32:
	add	x0, x0, l_.str.2@PAGEOFF
	b	LBB0_15
LBB0_13:
	mov	x0, x19
	bl	_gfx_v8_0_mec_init
	cbz	w0, LBB0_17
; %bb.14:
	mov	x22, x0
Lloh33:
	adrp	x0, l_.str.3@PAGE
Lloh34:
	add	x0, x0, l_.str.3@PAGEOFF
LBB0_15:
	bl	_DRM_ERROR
LBB0_16:
	mov	x0, x22
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_17:
	ldr	w8, [x19, #8]
	cmp	w8, #1
	b.lt	LBB0_23
; %bb.18:
	mov	x23, #0
	mov	x24, #0
Lloh35:
	adrp	x25, _AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP@GOTPAGE
Lloh36:
	ldr	x25, [x25, _AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP@GOTPAGEOFF]
	mov	w26, #1
Lloh37:
	adrp	x21, l_.str.4@PAGE
Lloh38:
	add	x21, x21, l_.str.4@PAGEOFF
LBB0_19:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #40]
	add	x22, x8, x23
	str	xzr, [x22, #16]
	ldr	w0, [x22, #8]
	mov	x1, x21
	bl	_sprintf
	ldr	w8, [x19]
	cmp	w8, #129
	b.eq	LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_19 Depth=1
	ldr	w8, [x19, #80]
	stp	w26, w8, [x22]
LBB0_21:                                ;   in Loop: Header=BB0_19 Depth=1
	ldr	w4, [x25]
	mov	x0, x19
	mov	x1, x22
	mov	w2, #1024
	mov	x3, x20
	bl	_amdgpu_ring_init
	cbnz	w0, LBB0_39
; %bb.22:                               ;   in Loop: Header=BB0_19 Depth=1
	add	x24, x24, #1
	ldrsw	x8, [x19, #8]
	add	x23, x23, #24
	cmp	x24, x8
	b.lt	LBB0_19
LBB0_23:
	ldr	w9, [x19, #24]
	cmp	w9, #1
	b.lt	LBB0_37
; %bb.24:
	mov	w20, #0
	mov	w21, #0
	ldr	w8, [x19, #32]
LBB0_25:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_29 Depth 2
                                        ;       Child Loop BB0_32 Depth 3
	cmp	w8, #1
	b.lt	LBB0_36
; %bb.26:                               ;   in Loop: Header=BB0_25 Depth=1
	mov	w23, #0
	ldr	w9, [x19, #28]
	b	LBB0_29
LBB0_27:                                ;   in Loop: Header=BB0_29 Depth=2
	ldr	w8, [x19, #32]
LBB0_28:                                ;   in Loop: Header=BB0_29 Depth=2
	add	w23, w23, #1
	cmp	w23, w8
	b.ge	LBB0_35
LBB0_29:                                ;   Parent Loop BB0_25 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_32 Depth 3
	cmp	w9, #1
	b.lt	LBB0_28
; %bb.30:                               ;   in Loop: Header=BB0_29 Depth=2
	mov	w24, #0
	b	LBB0_32
LBB0_31:                                ;   in Loop: Header=BB0_32 Depth=3
	add	w24, w24, #1
	ldr	w9, [x19, #28]
	cmp	w24, w9
	b.ge	LBB0_27
LBB0_32:                                ;   Parent Loop BB0_25 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	mov	x0, x19
	mov	x1, x20
	mov	x2, x24
	mov	x3, x23
	bl	_amdgpu_gfx_is_mec_queue_enabled
	cbz	w0, LBB0_31
; %bb.33:                               ;   in Loop: Header=BB0_32 Depth=3
	mov	x0, x19
	mov	x1, x21
	mov	x2, x20
	mov	x3, x24
	mov	x4, x23
	bl	_gfx_v8_0_compute_ring_init
	cbnz	w0, LBB0_39
; %bb.34:                               ;   in Loop: Header=BB0_32 Depth=3
	add	w21, w21, #1
	b	LBB0_31
LBB0_35:                                ;   in Loop: Header=BB0_25 Depth=1
	ldr	w9, [x19, #24]
LBB0_36:                                ;   in Loop: Header=BB0_25 Depth=1
	add	w20, w20, #1
	cmp	w20, w9
	b.lt	LBB0_25
LBB0_37:
Lloh39:
	adrp	x8, _GFX8_MEC_HPD_SIZE@GOTPAGE
Lloh40:
	ldr	x8, [x8, _GFX8_MEC_HPD_SIZE@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_amdgpu_gfx_kiq_init
	cbz	w0, LBB0_40
; %bb.38:
	mov	x22, x0
Lloh42:
	adrp	x0, l_.str.5@PAGE
Lloh43:
	add	x0, x0, l_.str.5@PAGEOFF
	b	LBB0_15
LBB0_39:
	mov	x22, x0
	b	LBB0_16
LBB0_40:
	add	x2, x19, #16
	add	x1, x19, #20
	mov	x0, x19
	bl	_amdgpu_gfx_kiq_init_ring
	mov	x22, x0
	cbnz	w0, LBB0_16
; %bb.41:
	mov	x0, x19
	mov	w1, #4
	bl	_amdgpu_gfx_mqd_sw_init
	mov	x22, x0
	cbnz	w0, LBB0_16
; %bb.42:
	mov	w8, #32768
	str	w8, [x19, #12]
	mov	x0, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	b	_gfx_v8_0_gpu_early_init
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpAdrp	Lloh2, Lloh6
	.loh AdrpLdr	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpAdd	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpAdd	Lloh29, Lloh30
	.loh AdrpAdd	Lloh31, Lloh32
	.loh AdrpAdd	Lloh33, Lloh34
	.loh AdrpAdd	Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpAdd	Lloh42, Lloh43
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_IRQ_CLIENTID_LEGACY,4,2 ; @AMDGPU_IRQ_CLIENTID_LEGACY
	.comm	_VISLANDS30_IV_SRCID_CP_END_OF_PIPE,4,2 ; @VISLANDS30_IV_SRCID_CP_END_OF_PIPE
	.comm	_VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT,4,2 ; @VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT
	.comm	_VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT,4,2 ; @VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT
	.comm	_VISLANDS30_IV_SRCID_CP_ECC_ERROR,4,2 ; @VISLANDS30_IV_SRCID_CP_ECC_ERROR
	.comm	_VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG,4,2 ; @VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"amdgpu_irq_add() for SQ failed: %d\n"

	.comm	_gfx_v8_0_sq_irq_work_func,4,2  ; @gfx_v8_0_sq_irq_work_func
	.comm	_AMDGPU_GFX_NORMAL_MODE,4,2     ; @AMDGPU_GFX_NORMAL_MODE
l_.str.1:                               ; @.str.1
	.asciz	"Failed to load gfx firmware!\n"

l_.str.2:                               ; @.str.2
	.asciz	"Failed to init rlc BOs!\n"

l_.str.3:                               ; @.str.3
	.asciz	"Failed to init MEC BOs!\n"

l_.str.4:                               ; @.str.4
	.asciz	"gfx"

	.comm	_AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP,4,2 ; @AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP
	.comm	_GFX8_MEC_HPD_SIZE,4,2          ; @GFX8_MEC_HPD_SIZE
l_.str.5:                               ; @.str.5
	.asciz	"Failed to init KIQ BOs!\n"

	.no_dead_strip	_gfx_v8_0_sw_init
	.section	__TEXT,__const
	.p2align	2                               ; @switch.table.gfx_v8_0_sw_init
l_switch.table.gfx_v8_0_sw_init:
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	2                               ; 0x2

.subsections_via_symbols
