	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_irq_update              ## -- Begin function amdgpu_irq_update
	.p2align	4, 0x90
_amdgpu_irq_update:                     ## @amdgpu_irq_update
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r14d
	movq	%rsi, %r15
	movq	%rdi, %rbx
	callq	_spin_lock_irqsave
	movq	%rbx, %rdi
	movq	%r15, %rsi
	movl	%r14d, %edx
	callq	_amdgpu_irq_enabled
	testq	%rax, %rax
	jne	LBB0_1
## %bb.2:
	movq	_AMDGPU_IRQ_STATE_DISABLE@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_1:
	movq	_AMDGPU_IRQ_STATE_ENABLE@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %ecx
	movq	(%r15), %rax
	movq	%rbx, %rdi
	movq	%r15, %rsi
	movl	%r14d, %edx
	callq	*(%rax)
	movl	%eax, %r14d
	movq	%rbx, %rdi
	callq	_spin_unlock_irqrestore
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_IRQ_STATE_ENABLE,4,2    ## @AMDGPU_IRQ_STATE_ENABLE
	.comm	_AMDGPU_IRQ_STATE_DISABLE,4,2   ## @AMDGPU_IRQ_STATE_DISABLE
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_irq_update              ; -- Begin function amdgpu_irq_update
	.p2align	2
_amdgpu_irq_update:                     ; @amdgpu_irq_update
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x2
	mov	x20, x1
	mov	x21, x0
	bl	_spin_lock_irqsave
	mov	x0, x21
	mov	x1, x20
	mov	x2, x19
	bl	_amdgpu_irq_enabled
Lloh0:
	adrp	x8, _AMDGPU_IRQ_STATE_DISABLE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPU_IRQ_STATE_DISABLE@GOTPAGEOFF]
Lloh2:
	adrp	x9, _AMDGPU_IRQ_STATE_ENABLE@GOTPAGE
Lloh3:
	ldr	x9, [x9, _AMDGPU_IRQ_STATE_ENABLE@GOTPAGEOFF]
	cmp	x0, #0
	csel	x8, x8, x9, eq
	ldr	w3, [x8]
	ldr	x8, [x20]
	ldr	x8, [x8]
	mov	x0, x21
	mov	x1, x20
	mov	x2, x19
	blr	x8
	mov	x19, x0
	mov	x0, x21
	bl	_spin_unlock_irqrestore
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_IRQ_STATE_ENABLE,4,2    ; @AMDGPU_IRQ_STATE_ENABLE
	.comm	_AMDGPU_IRQ_STATE_DISABLE,4,2   ; @AMDGPU_IRQ_STATE_DISABLE
.subsections_via_symbols
