	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_pll_compute             ## -- Begin function amdgpu_pll_compute
	.p2align	4, 0x90
_amdgpu_pll_compute:                    ## @amdgpu_pll_compute
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$88, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	(%rdi), %r11d
	movq	_AMDGPU_PLL_USE_FRAC_FB_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movslq	%esi, %rax
	imulq	$1717986919, %rax, %r12         ## imm = 0x66666667
	movq	%r12, %rax
	shrq	$63, %rax
	sarq	$34, %r12
	addl	%eax, %r12d
	movl	4(%rdi), %r13d
	movl	8(%rdi), %r10d
	leal	(%r13,%r13), %r15d
	leal	(%r10,%r10), %r14d
	movl	%ebx, -56(%rbp)                 ## 4-byte Spill
	testl	%r11d, %ebx
	leal	(%r15,%r15,4), %ebx
	leal	(%r14,%r14,4), %eax
	cmovel	%r10d, %eax
	movl	%eax, -76(%rbp)                 ## 4-byte Spill
	cmovel	%r13d, %ebx
	movl	%ebx, -60(%rbp)                 ## 4-byte Spill
	movq	%r9, -104(%rbp)                 ## 8-byte Spill
	movq	%rdi, %rbx
	movq	%r8, -120(%rbp)                 ## 8-byte Spill
	movq	%rdx, -112(%rbp)                ## 8-byte Spill
	sete	%al
	movl	%esi, -84(%rbp)                 ## 4-byte Spill
	cmovnel	%esi, %r12d
	movq	_AMDGPU_PLL_USE_REF_DIV@GOTPCREL(%rip), %rsi
	xorl	%edx, %edx
	testl	%r11d, (%rsi)
	sete	%dl
	movl	12(%rdi,%rdx,4), %esi
	movl	%esi, -80(%rbp)                 ## 4-byte Spill
	orb	%al, %dl
	movzbl	%dl, %eax
	movl	12(%rdi,%rax,8), %eax
	movl	%eax, -72(%rbp)                 ## 4-byte Spill
	movq	_AMDGPU_PLL_USE_POST_DIV@GOTPCREL(%rip), %rax
	testl	%r11d, (%rax)
	movq	%rcx, -96(%rbp)                 ## 8-byte Spill
	je	LBB0_2
## %bb.1:
	movl	24(%rbx), %r13d
	movl	%r13d, %r15d
	jmp	LBB0_3
LBB0_2:
	movq	_AMDGPU_PLL_IS_LCD@GOTPCREL(%rip), %rax
	xorl	%ecx, %ecx
	testl	%r11d, (%rax)
	sete	%cl
	movl	28(%rbx,%rcx,8), %eax
	movl	32(%rbx,%rcx,8), %edx
	leal	(%rax,%rax), %ecx
	leal	(%rdx,%rdx), %esi
	testl	%r11d, -56(%rbp)                ## 4-byte Folded Reload
	leal	(%rcx,%rcx,4), %ecx
	leal	(%rsi,%rsi,4), %esi
	cmovel	%eax, %ecx
	cmovel	%edx, %esi
	movl	%ecx, %eax
	xorl	%edx, %edx
	divl	%r12d
	movl	%eax, %r13d
	imull	%r12d, %eax
	cmpl	%ecx, %eax
	adcl	$0, %r13d
	movl	44(%rbx), %eax
	cmpl	%eax, %r13d
	cmovbel	%eax, %r13d
	movl	48(%rbx), %ecx
	movl	%esi, %eax
	xorl	%edx, %edx
	divl	%r12d
	movl	%eax, %r15d
	imull	%r12d, %eax
	cmpl	%eax, %esi
	sbbl	$0, %r15d
	cmpl	%ecx, %r15d
	cmovael	%ecx, %r15d
LBB0_3:
	movl	%r12d, -68(%rbp)
	movl	52(%rbx), %eax
	movl	%eax, -64(%rbp)
	leaq	-68(%rbp), %rdi
	leaq	-64(%rbp), %rsi
	movl	-60(%rbp), %edx                 ## 4-byte Reload
	movl	%r13d, %ecx
	movq	%rbx, -56(%rbp)                 ## 8-byte Spill
	callq	_amdgpu_pll_reduce_ratio
	movq	_AMDGPU_PLL_PREFER_MINM_OVER_MAXP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	testl	%eax, (%rcx)
	movl	%r13d, %ebx
	cmovel	%r15d, %ebx
	cmpl	%r15d, %r13d
	jbe	LBB0_4
LBB0_10:
	movl	-68(%rbp), %edi
	movl	-64(%rbp), %esi
	leaq	-48(%rbp), %r15
	movq	%r15, (%rsp)
	leaq	-44(%rbp), %r13
	movl	%ebx, %r12d
	movl	%ebx, %edx
	movl	-76(%rbp), %ecx                 ## 4-byte Reload
	movl	-72(%rbp), %r8d                 ## 4-byte Reload
	movq	%r13, %r9
	callq	_amdgpu_pll_get_fb_ref_div
	movq	%r13, %rdi
	movq	%r15, %rsi
	movl	-60(%rbp), %edx                 ## 4-byte Reload
	movl	-80(%rbp), %ecx                 ## 4-byte Reload
	callq	_amdgpu_pll_reduce_ratio
	movq	_AMDGPU_PLL_USE_FRAC_FB_DIV@GOTPCREL(%rip), %r14
	movl	(%r14), %eax
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	testl	%eax, (%rbx)
	je	LBB0_14
## %bb.11:
	movl	-44(%rbp), %eax
	movl	$3435973837, %ecx               ## imm = 0xCCCCCCCD
	imulq	%rax, %rcx
	shrq	$35, %rcx
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	je	LBB0_14
## %bb.12:
	movl	$9, %ecx
	subl	%eax, %ecx
	leal	(%rcx,%rcx,4), %eax
	leal	60(,%rax,4), %esi
	movl	-60(%rbp), %edi                 ## 4-byte Reload
	callq	_max
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movl	-44(%rbp), %esi
	cmpl	%eax, %esi
	jae	LBB0_14
## %bb.13:
	movl	%eax, %edi
	callq	_DIV_ROUND_UP
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movl	-44(%rbp), %ecx
	imull	%eax, %ecx
	movl	%ecx, -44(%rbp)
	imull	-48(%rbp), %eax
	movl	%eax, -48(%rbp)
LBB0_14:
	movq	16(%rbp), %r8
	movl	(%r14), %edx
	movl	-44(%rbp), %eax
	testl	%edx, (%rbx)
	je	LBB0_16
## %bb.15:
	movl	%eax, %edx
	movl	$3435973837, %esi               ## imm = 0xCCCCCCCD
	imulq	%rdx, %rsi
	shrq	$35, %rsi
	movq	-96(%rbp), %rcx                 ## 8-byte Reload
	movl	%esi, (%rcx)
	addl	%esi, %esi
	leal	(%rsi,%rsi,4), %edx
	subl	%edx, %eax
	jmp	LBB0_17
LBB0_4:
	movl	$-1, %r14d
	jmp	LBB0_5
	.p2align	4, 0x90
LBB0_8:                                 ##   in Loop: Header=BB0_5 Depth=1
	movl	%r13d, %ebx
	movl	%eax, %r14d
LBB0_9:                                 ##   in Loop: Header=BB0_5 Depth=1
	incl	%r13d
	cmpl	%r15d, %r13d
	ja	LBB0_10
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	movl	-68(%rbp), %edi
	movl	-64(%rbp), %esi
	leaq	-48(%rbp), %rax
	movq	%rax, (%rsp)
	movl	%r13d, %edx
	movl	-76(%rbp), %ecx                 ## 4-byte Reload
	movl	-72(%rbp), %r8d                 ## 4-byte Reload
	leaq	-44(%rbp), %r9
	callq	_amdgpu_pll_get_fb_ref_div
	movl	-44(%rbp), %eax
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
	imull	52(%rsi), %eax
	movl	-48(%rbp), %ecx
	imull	%r13d, %ecx
	xorl	%edx, %edx
	divl	%ecx
	movl	%r12d, %ecx
	subl	%eax, %ecx
	movl	%ecx, %eax
	negl	%eax
	cmovsl	%ecx, %eax
	cmpl	%r14d, %eax
	jb	LBB0_8
## %bb.6:                               ##   in Loop: Header=BB0_5 Depth=1
	jne	LBB0_9
## %bb.7:                               ##   in Loop: Header=BB0_5 Depth=1
	movq	_AMDGPU_PLL_PREFER_MINM_OVER_MAXP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, (%rsi)
	jne	LBB0_9
	jmp	LBB0_8
LBB0_16:
	movq	-96(%rbp), %rcx                 ## 8-byte Reload
	movl	%eax, (%rcx)
	xorl	%eax, %eax
LBB0_17:
	movq	-120(%rbp), %rdi                ## 8-byte Reload
	movl	%eax, (%rdi)
	movl	(%rcx), %edx
	leal	(%rdx,%rdx,4), %edx
	leal	(%rax,%rdx,2), %eax
	imull	52(%rbx), %eax
	movl	-48(%rbp), %r9d
	movl	%r12d, %edx
	imull	%r9d, %edx
	addl	%edx, %edx
	leal	(%rdx,%rdx,4), %esi
	xorl	%edx, %edx
	divl	%esi
	movq	-112(%rbp), %rdx                ## 8-byte Reload
	movl	%eax, (%rdx)
	movq	-104(%rbp), %rax                ## 8-byte Reload
	movl	%r9d, (%rax)
	movl	%r12d, (%r8)
	movl	(%rdx), %eax
	addl	%eax, %eax
	leal	(%rax,%rax,4), %edx
	movl	(%rcx), %ecx
	movl	(%rdi), %r8d
	movl	%r12d, (%rsp)
	leaq	L_.str(%rip), %rdi
	movl	-84(%rbp), %esi                 ## 4-byte Reload
	callq	_DRM_DEBUG_KMS
	addq	$88, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_PLL_USE_FRAC_FB_DIV,4,2 ## @AMDGPU_PLL_USE_FRAC_FB_DIV
	.comm	_AMDGPU_PLL_USE_REF_DIV,4,2     ## @AMDGPU_PLL_USE_REF_DIV
	.comm	_AMDGPU_PLL_USE_POST_DIV,4,2    ## @AMDGPU_PLL_USE_POST_DIV
	.comm	_AMDGPU_PLL_IS_LCD,4,2          ## @AMDGPU_PLL_IS_LCD
	.comm	_AMDGPU_PLL_PREFER_MINM_OVER_MAXP,4,2 ## @AMDGPU_PLL_PREFER_MINM_OVER_MAXP
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_pll_compute             ; -- Begin function amdgpu_pll_compute
	.p2align	2
_amdgpu_pll_compute:                    ; @amdgpu_pll_compute
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #176
	.cfi_def_cfa_offset 176
	stp	x28, x27, [sp, #80]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #96]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #112]            ; 16-byte Folded Spill
	stp	x22, x21, [sp, #128]            ; 16-byte Folded Spill
	stp	x20, x19, [sp, #144]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #160]            ; 16-byte Folded Spill
	add	x29, sp, #160
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	stp	x5, x6, [sp, #24]               ; 16-byte Folded Spill
	str	x4, [sp, #48]                   ; 8-byte Folded Spill
	str	x2, [sp, #16]                   ; 8-byte Folded Spill
	mov	x25, x0
Lloh0:
	adrp	x8, _AMDGPU_PLL_USE_FRAC_FB_DIV@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPU_PLL_USE_FRAC_FB_DIV@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	mov	w9, #26215
	movk	w9, #26214, lsl #16
	smull	x9, w1, w9
	lsr	x10, x9, #63
	asr	x9, x9, #34
	add	w10, w9, w10
	ldp	w9, w11, [x0]
	ands	w8, w8, w9
	str	w1, [sp, #60]                   ; 4-byte Folded Spill
	csel	w24, w10, w1, eq
	ldr	w10, [x0, #8]
	add	w12, w11, w11, lsl #2
	lsl	w12, w12, #1
	add	w13, w10, w10, lsl #2
	lsl	w13, w13, #1
	csel	w28, w10, w13, eq
Lloh3:
	adrp	x10, _AMDGPU_PLL_USE_REF_DIV@GOTPAGE
Lloh4:
	ldr	x10, [x10, _AMDGPU_PLL_USE_REF_DIV@GOTPAGEOFF]
	csel	w26, w11, w12, eq
Lloh5:
	ldr	w10, [x10]
	tst	w10, w9
	mov	w11, #12
	mov	w12, #16
	csel	x12, x12, x11, eq
	tst	w10, w9
	ccmp	w8, #0, #4, ne
	ldr	w10, [x0, x12]
	str	w10, [sp, #12]                  ; 4-byte Folded Spill
	mov	w10, #20
	csel	x10, x10, x11, eq
	ldr	w23, [x0, x10]
Lloh6:
	adrp	x10, _AMDGPU_PLL_USE_POST_DIV@GOTPAGE
Lloh7:
	ldr	x10, [x10, _AMDGPU_PLL_USE_POST_DIV@GOTPAGEOFF]
Lloh8:
	ldr	w10, [x10]
	tst	w10, w9
	str	x3, [sp, #40]                   ; 8-byte Folded Spill
	b.eq	LBB0_2
; %bb.1:
	ldr	w27, [x25, #24]
	mov	x22, x27
	b	LBB0_3
LBB0_2:
Lloh9:
	adrp	x10, _AMDGPU_PLL_IS_LCD@GOTPAGE
Lloh10:
	ldr	x10, [x10, _AMDGPU_PLL_IS_LCD@GOTPAGEOFF]
Lloh11:
	ldr	w10, [x10]
	tst	w10, w9
	mov	w9, #28
	mov	w10, #36
	csel	x9, x10, x9, eq
	mov	w10, #32
	mov	w11, #40
	csel	x10, x11, x10, eq
	ldr	w10, [x25, x10]
	ldr	w9, [x25, x9]
	add	w11, w9, w9, lsl #2
	lsl	w11, w11, #1
	add	w12, w10, w10, lsl #2
	lsl	w12, w12, #1
	cmp	w8, #0
	csel	w8, w9, w11, eq
	csel	w9, w10, w12, eq
	udiv	w10, w8, w24
	mul	w11, w10, w24
	cmp	w11, w8
	cinc	w8, w10, lo
	ldp	w10, w11, [x25, #44]
	cmp	w8, w10
	csel	w27, w8, w10, hi
	udiv	w8, w9, w24
	mul	w10, w8, w24
	cmp	w10, w9
	cset	w9, hi
	sub	w8, w8, w9
	cmp	w8, w11
	csel	w22, w8, w11, lo
LBB0_3:
	ldr	w8, [x25, #52]
	stp	w8, w24, [sp, #64]
	add	x0, sp, #68
	add	x1, sp, #64
	mov	x2, x26
	mov	x3, x27
	bl	_amdgpu_pll_reduce_ratio
	ldr	w8, [x25]
Lloh12:
	adrp	x19, _AMDGPU_PLL_PREFER_MINM_OVER_MAXP@GOTPAGE
Lloh13:
	ldr	x19, [x19, _AMDGPU_PLL_PREFER_MINM_OVER_MAXP@GOTPAGEOFF]
	ldr	w9, [x19]
	tst	w9, w8
	csel	w20, w22, w27, eq
	cmp	w27, w22
	b.ls	LBB0_10
LBB0_4:
	ldp	w1, w0, [sp, #64]
	add	x5, sp, #76
	add	x6, sp, #72
	mov	x2, x20
	mov	x3, x28
	mov	x4, x23
	bl	_amdgpu_pll_get_fb_ref_div
	add	x0, sp, #76
	add	x1, sp, #72
	mov	x2, x26
	ldr	w3, [sp, #12]                   ; 4-byte Folded Reload
	bl	_amdgpu_pll_reduce_ratio
	ldr	w8, [x25]
Lloh14:
	adrp	x19, _AMDGPU_PLL_USE_FRAC_FB_DIV@GOTPAGE
Lloh15:
	ldr	x19, [x19, _AMDGPU_PLL_USE_FRAC_FB_DIV@GOTPAGEOFF]
	ldr	w9, [x19]
	tst	w9, w8
	b.eq	LBB0_8
; %bb.5:
	ldr	w8, [sp, #76]
	mov	w9, #52429
	movk	w9, #52428, lsl #16
	mul	x9, x8, x9
	lsr	x9, x9, #35
	mov	w10, #10
	msub	w8, w9, w10, w8
	cbz	w8, LBB0_8
; %bb.6:
	mov	w9, #9
	sub	w8, w9, w8
	mov	w9, #20
	orr	w10, wzr, #0x3c
	madd	w1, w8, w9, w10
	mov	x0, x26
	bl	_max
	ldr	w1, [sp, #76]
	cmp	w1, w0
	b.hs	LBB0_8
; %bb.7:
	bl	_DIV_ROUND_UP
	ldr	w8, [sp, #76]
	mul	w9, w8, w0
	ldr	w8, [sp, #72]
	mul	w8, w8, w0
	stp	w8, w9, [sp, #72]
LBB0_8:
	ldr	w8, [x25]
	ldr	w10, [x19]
	ldr	w9, [sp, #76]
	tst	w10, w8
	b.eq	LBB0_16
; %bb.9:
	mov	w8, #52429
	movk	w8, #52428, lsl #16
	umull	x8, w9, w8
	lsr	x8, x8, #35
	ldr	x13, [sp, #40]                  ; 8-byte Folded Reload
	str	w8, [x13]
	mov	w10, #10
	msub	w8, w8, w10, w9
	b	LBB0_17
LBB0_10:
	mov	w21, #-1
	b	LBB0_13
LBB0_11:                                ;   in Loop: Header=BB0_13 Depth=1
	mov	x20, x27
	mov	x21, x8
LBB0_12:                                ;   in Loop: Header=BB0_13 Depth=1
	add	w27, w27, #1
	cmp	w27, w22
	b.hi	LBB0_4
LBB0_13:                                ; =>This Inner Loop Header: Depth=1
	ldp	w1, w0, [sp, #64]
	add	x5, sp, #76
	add	x6, sp, #72
	mov	x2, x27
	mov	x3, x28
	mov	x4, x23
	bl	_amdgpu_pll_get_fb_ref_div
	ldr	w8, [x25, #52]
	ldr	w9, [sp, #76]
	mul	w8, w9, w8
	ldr	w9, [sp, #72]
	mul	w9, w9, w27
	udiv	w8, w8, w9
	sub	w8, w24, w8
	cmp	w8, #0
	cneg	w8, w8, mi
	cmp	w8, w21
	b.lo	LBB0_11
; %bb.14:                               ;   in Loop: Header=BB0_13 Depth=1
	b.ne	LBB0_12
; %bb.15:                               ;   in Loop: Header=BB0_13 Depth=1
	ldr	w9, [x25]
	ldr	w10, [x19]
	tst	w10, w9
	b.ne	LBB0_12
	b	LBB0_11
LBB0_16:
	mov	w8, #0
	ldr	x13, [sp, #40]                  ; 8-byte Folded Reload
	str	w9, [x13]
LBB0_17:
	ldr	x12, [sp, #48]                  ; 8-byte Folded Reload
	str	w8, [x12]
	ldr	w9, [x25, #52]
	ldr	w10, [x13]
	mov	w11, #10
	madd	w8, w10, w11, w8
	mul	w8, w8, w9
	ldr	w5, [sp, #72]
	mul	w9, w20, w5
	add	w9, w9, w9, lsl #2
	lsl	w9, w9, #1
	udiv	w8, w8, w9
	ldr	x9, [sp, #16]                   ; 8-byte Folded Reload
	str	w8, [x9]
	ldr	x8, [sp, #24]                   ; 8-byte Folded Reload
	str	w5, [x8]
	ldr	x8, [sp, #32]                   ; 8-byte Folded Reload
	str	w20, [x8]
	ldr	w8, [x9]
	add	w8, w8, w8, lsl #2
	lsl	w2, w8, #1
	ldr	w3, [x13]
	ldr	w4, [x12]
Lloh16:
	adrp	x0, l_.str@PAGE
Lloh17:
	add	x0, x0, l_.str@PAGEOFF
	ldr	w1, [sp, #60]                   ; 4-byte Folded Reload
	mov	x6, x20
	bl	_DRM_DEBUG_KMS
	ldp	x29, x30, [sp, #160]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #144]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #128]            ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #112]            ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #96]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #80]             ; 16-byte Folded Reload
	add	sp, sp, #176
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpAdd	Lloh16, Lloh17
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_PLL_USE_FRAC_FB_DIV,4,2 ; @AMDGPU_PLL_USE_FRAC_FB_DIV
	.comm	_AMDGPU_PLL_USE_REF_DIV,4,2     ; @AMDGPU_PLL_USE_REF_DIV
	.comm	_AMDGPU_PLL_USE_POST_DIV,4,2    ; @AMDGPU_PLL_USE_POST_DIV
	.comm	_AMDGPU_PLL_IS_LCD,4,2          ; @AMDGPU_PLL_IS_LCD
	.comm	_AMDGPU_PLL_PREFER_MINM_OVER_MAXP,4,2 ; @AMDGPU_PLL_PREFER_MINM_OVER_MAXP
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n"

.subsections_via_symbols
