	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function psb_intel_crtc_clock_get
_psb_intel_crtc_clock_get:              ## @psb_intel_crtc_clock_get
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	%rsi, %rdi
	callq	_to_gma_crtc
	movq	(%rbx), %r12
	movslq	(%rax), %r13
	movq	16(%r12), %r15
	movq	8(%r12), %r14
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_gma_power_begin
	testq	%rax, %rax
	je	LBB0_4
## %bb.1:
	movq	%rbx, -72(%rbp)                 ## 8-byte Spill
	leaq	(,%r13,2), %rbx
	addq	%r13, %rbx
	leaq	(%r15,%rbx,4), %r12
	movl	8(%r15,%rbx,4), %edi
	callq	_REG_READ
	movl	%eax, %r14d
	movq	_DISPLAY_RATE_SELECT_FPA1@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r14d, %eax
	leaq	4(%r15,%rbx,4), %rax
	cmovneq	%r12, %rax
	movl	(%rax), %edi
	callq	_REG_READ
	movl	%eax, %ebx
	cmpl	$1, %r13d
	movl	$0, %r15d
	jne	LBB0_3
## %bb.2:
	movq	_LVDS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_REG_READ
	movq	_LVDS_PORT_EN@GOTPCREL(%rip), %rcx
	xorl	%r15d, %r15d
	testl	%eax, (%rcx)
	setne	%r15b
LBB0_3:
	movq	-72(%rbp), %rdi                 ## 8-byte Reload
	callq	_gma_power_end
	jmp	LBB0_6
LBB0_4:
	leaq	(,%r13,2), %rax
	addq	%r13, %rax
	leaq	(%r14,%rax,4), %rcx
	movl	(%r14,%rax,4), %r14d
	movq	_DISPLAY_RATE_SELECT_FPA1@GOTPCREL(%rip), %rax
	xorl	%edx, %edx
	testl	%r14d, (%rax)
	setne	%dl
	movl	4(%rcx,%rdx,4), %ebx
	xorl	%r15d, %r15d
	cmpl	$1, %r13d
	jne	LBB0_6
## %bb.5:
	movq	_LVDS_PORT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	xorl	%r15d, %r15d
	testl	%eax, (%r12)
	setne	%r15b
LBB0_6:
	movq	_FP_M1_DIV_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%ebx, %eax
	movq	_FP_M1_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	movq	_FP_M2_DIV_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	andl	%ebx, %edx
	movq	_FP_M2_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %edx
	movq	_FP_N_DIV_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %ebx
	movq	_FP_N_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %ebx
	movl	%eax, -64(%rbp)
	movl	%edx, -60(%rbp)
	movl	%ebx, -56(%rbp)
	testl	%r15d, %r15d
	je	LBB0_8
## %bb.7:
	movq	_DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r14d, %eax
	movq	_DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	bsfl	%eax, %eax
	movl	$-1, %ecx
	cmovnel	%eax, %ecx
	incl	%ecx
	movl	%ecx, -52(%rbp)
	movq	_PLL_REF_INPUT_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %r14d
	movl	$14, -48(%rbp)
	movq	_PLLB_REF_INPUT_SPREADSPECTRUMIN@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r14d
	movl	$66000, %eax                    ## imm = 0x101D0
	movl	$48000, %edi                    ## imm = 0xBB80
	cmovel	%eax, %edi
	jmp	LBB0_11
LBB0_8:
	movq	_PLL_P1_DIVIDE_BY_TWO@GOTPCREL(%rip), %rcx
	movl	$2, %eax
	testl	%r14d, (%rcx)
	jne	LBB0_10
## %bb.9:
	movq	_DPLL_FPA01_P1_POST_DIV_MASK_I830@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r14d, %eax
	movq	_DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	addl	$2, %eax
LBB0_10:
	movl	%eax, -52(%rbp)
	movq	_PLL_P2_DIVIDE_BY_4@GOTPCREL(%rip), %rax
	xorl	%ecx, %ecx
	andl	(%rax), %r14d
	setne	%cl
	leal	(%rcx,%rcx), %eax
	addl	$2, %eax
	movl	%eax, -48(%rbp)
	movl	$48000, %edi                    ## imm = 0xBB80
LBB0_11:
	leaq	-64(%rbp), %rsi
	callq	_psb_intel_clock
	movl	-44(%rbp), %eax
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DISPLAY_RATE_SELECT_FPA1,4,2   ## @DISPLAY_RATE_SELECT_FPA1
	.comm	_LVDS,4,2                       ## @LVDS
	.comm	_LVDS_PORT_EN,4,2               ## @LVDS_PORT_EN
	.comm	_FP_M1_DIV_MASK,4,2             ## @FP_M1_DIV_MASK
	.comm	_FP_M1_DIV_SHIFT,4,2            ## @FP_M1_DIV_SHIFT
	.comm	_FP_M2_DIV_MASK,4,2             ## @FP_M2_DIV_MASK
	.comm	_FP_M2_DIV_SHIFT,4,2            ## @FP_M2_DIV_SHIFT
	.comm	_FP_N_DIV_MASK,4,2              ## @FP_N_DIV_MASK
	.comm	_FP_N_DIV_SHIFT,4,2             ## @FP_N_DIV_SHIFT
	.comm	_DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS,4,2 ## @DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
	.comm	_DPLL_FPA01_P1_POST_DIV_SHIFT,4,2 ## @DPLL_FPA01_P1_POST_DIV_SHIFT
	.comm	_PLL_REF_INPUT_MASK,4,2         ## @PLL_REF_INPUT_MASK
	.comm	_PLLB_REF_INPUT_SPREADSPECTRUMIN,4,2 ## @PLLB_REF_INPUT_SPREADSPECTRUMIN
	.comm	_PLL_P1_DIVIDE_BY_TWO,4,2       ## @PLL_P1_DIVIDE_BY_TWO
	.comm	_DPLL_FPA01_P1_POST_DIV_MASK_I830,4,2 ## @DPLL_FPA01_P1_POST_DIV_MASK_I830
	.comm	_PLL_P2_DIVIDE_BY_4,4,2         ## @PLL_P2_DIVIDE_BY_4
	.no_dead_strip	_psb_intel_crtc_clock_get
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function psb_intel_crtc_clock_get
_psb_intel_crtc_clock_get:              ; @psb_intel_crtc_clock_get
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x21, x0
	mov	x0, x1
	bl	_to_gma_crtc
	ldr	x23, [x21]
	ldrsw	x22, [x0]
	ldp	x20, x19, [x23, #8]
	mov	x0, x21
	mov	w1, #0
	bl	_gma_power_begin
	mov	w8, #12
	cbz	x0, LBB0_3
; %bb.1:
	madd	x20, x22, x8, x19
	ldr	w0, [x20, #8]
	bl	_REG_READ
	mov	x19, x0
Lloh0:
	adrp	x8, _DISPLAY_RATE_SELECT_FPA1@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DISPLAY_RATE_SELECT_FPA1@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	add	x9, x20, #4
	tst	w8, w0
	csel	x8, x9, x20, eq
	ldr	w0, [x8]
	bl	_REG_READ
	mov	x20, x0
	cmp	w22, #1
	b.ne	LBB0_5
; %bb.2:
Lloh3:
	adrp	x8, _LVDS@GOTPAGE
Lloh4:
	ldr	x8, [x8, _LVDS@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	bl	_REG_READ
Lloh6:
	adrp	x8, _LVDS_PORT_EN@GOTPAGE
Lloh7:
	ldr	x8, [x8, _LVDS_PORT_EN@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	tst	w8, w0
	cset	w22, ne
	b	LBB0_6
LBB0_3:
	madd	x8, x22, x8, x20
	add	x9, x8, #4
	ldr	w19, [x8], #8
Lloh9:
	adrp	x10, _DISPLAY_RATE_SELECT_FPA1@GOTPAGE
Lloh10:
	ldr	x10, [x10, _DISPLAY_RATE_SELECT_FPA1@GOTPAGEOFF]
Lloh11:
	ldr	w10, [x10]
	tst	w10, w19
	csel	x8, x9, x8, eq
	ldr	w20, [x8]
	cmp	w22, #1
	b.ne	LBB0_7
; %bb.4:
	ldr	w8, [x23]
Lloh12:
	adrp	x9, _LVDS_PORT_EN@GOTPAGE
Lloh13:
	ldr	x9, [x9, _LVDS_PORT_EN@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	tst	w9, w8
	cset	w22, ne
	b	LBB0_8
LBB0_5:
	mov	w22, #0
LBB0_6:
	mov	x0, x21
	bl	_gma_power_end
	b	LBB0_8
LBB0_7:
	mov	w22, #0
LBB0_8:
Lloh15:
	adrp	x8, _FP_M1_DIV_MASK@GOTPAGE
Lloh16:
	ldr	x8, [x8, _FP_M1_DIV_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	and	w8, w8, w20
Lloh18:
	adrp	x9, _FP_M1_DIV_SHIFT@GOTPAGE
Lloh19:
	ldr	x9, [x9, _FP_M1_DIV_SHIFT@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
Lloh21:
	adrp	x10, _FP_M2_DIV_MASK@GOTPAGE
Lloh22:
	ldr	x10, [x10, _FP_M2_DIV_MASK@GOTPAGEOFF]
	asr	w8, w8, w9
Lloh23:
	ldr	w9, [x10]
	and	w9, w9, w20
Lloh24:
	adrp	x10, _FP_M2_DIV_SHIFT@GOTPAGE
Lloh25:
	ldr	x10, [x10, _FP_M2_DIV_SHIFT@GOTPAGEOFF]
Lloh26:
	ldr	w10, [x10]
	asr	w9, w9, w10
	stp	w8, w9, [sp, #8]
Lloh27:
	adrp	x8, _FP_N_DIV_MASK@GOTPAGE
Lloh28:
	ldr	x8, [x8, _FP_N_DIV_MASK@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	and	w8, w8, w20
Lloh30:
	adrp	x9, _FP_N_DIV_SHIFT@GOTPAGE
Lloh31:
	ldr	x9, [x9, _FP_N_DIV_SHIFT@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	asr	w8, w8, w9
	str	w8, [sp, #16]
	cbz	w22, LBB0_10
; %bb.9:
Lloh33:
	adrp	x8, _DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS@GOTPAGE
Lloh34:
	ldr	x8, [x8, _DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
	and	w8, w8, w19
Lloh36:
	adrp	x9, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGE
Lloh37:
	ldr	x9, [x9, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGEOFF]
Lloh38:
	ldr	w9, [x9]
	asr	w8, w8, w9
	rbit	w9, w8
	clz	w9, w9
	cmp	w8, #0
	csinc	w8, wzr, w9, eq
	mov	w9, #14
	stp	w8, w9, [sp, #20]
Lloh39:
	adrp	x8, _PLL_REF_INPUT_MASK@GOTPAGE
Lloh40:
	ldr	x8, [x8, _PLL_REF_INPUT_MASK@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
Lloh42:
	adrp	x9, _PLLB_REF_INPUT_SPREADSPECTRUMIN@GOTPAGE
Lloh43:
	ldr	x9, [x9, _PLLB_REF_INPUT_SPREADSPECTRUMIN@GOTPAGEOFF]
	and	w8, w8, w19
Lloh44:
	ldr	w9, [x9]
	mov	w10, #48000
	mov	w11, #464
	movk	w11, #1, lsl #16
	cmp	w8, w9
	csel	w0, w11, w10, eq
	b	LBB0_13
LBB0_10:
Lloh45:
	adrp	x8, _PLL_P1_DIVIDE_BY_TWO@GOTPAGE
Lloh46:
	ldr	x8, [x8, _PLL_P1_DIVIDE_BY_TWO@GOTPAGEOFF]
Lloh47:
	ldr	w10, [x8]
	mov	w8, #2
	mov	w9, #2
	tst	w10, w19
	b.ne	LBB0_12
; %bb.11:
Lloh48:
	adrp	x9, _DPLL_FPA01_P1_POST_DIV_MASK_I830@GOTPAGE
Lloh49:
	ldr	x9, [x9, _DPLL_FPA01_P1_POST_DIV_MASK_I830@GOTPAGEOFF]
Lloh50:
	ldr	w9, [x9]
	and	w9, w9, w19
Lloh51:
	adrp	x10, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGE
Lloh52:
	ldr	x10, [x10, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGEOFF]
Lloh53:
	ldr	w10, [x10]
	asr	w9, w9, w10
	add	w9, w9, #2
LBB0_12:
Lloh54:
	adrp	x10, _PLL_P2_DIVIDE_BY_4@GOTPAGE
Lloh55:
	ldr	x10, [x10, _PLL_P2_DIVIDE_BY_4@GOTPAGEOFF]
Lloh56:
	ldr	w10, [x10]
	tst	w10, w19
	mov	w10, #4
	csel	w8, w8, w10, eq
	stp	w9, w8, [sp, #20]
	mov	w0, #48000
LBB0_13:
	add	x1, sp, #8
	bl	_psb_intel_clock
	ldr	w0, [sp, #28]
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.cfi_endproc
                                        ; -- End function
	.comm	_DISPLAY_RATE_SELECT_FPA1,4,2   ; @DISPLAY_RATE_SELECT_FPA1
	.comm	_LVDS,4,2                       ; @LVDS
	.comm	_LVDS_PORT_EN,4,2               ; @LVDS_PORT_EN
	.comm	_FP_M1_DIV_MASK,4,2             ; @FP_M1_DIV_MASK
	.comm	_FP_M1_DIV_SHIFT,4,2            ; @FP_M1_DIV_SHIFT
	.comm	_FP_M2_DIV_MASK,4,2             ; @FP_M2_DIV_MASK
	.comm	_FP_M2_DIV_SHIFT,4,2            ; @FP_M2_DIV_SHIFT
	.comm	_FP_N_DIV_MASK,4,2              ; @FP_N_DIV_MASK
	.comm	_FP_N_DIV_SHIFT,4,2             ; @FP_N_DIV_SHIFT
	.comm	_DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS,4,2 ; @DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
	.comm	_DPLL_FPA01_P1_POST_DIV_SHIFT,4,2 ; @DPLL_FPA01_P1_POST_DIV_SHIFT
	.comm	_PLL_REF_INPUT_MASK,4,2         ; @PLL_REF_INPUT_MASK
	.comm	_PLLB_REF_INPUT_SPREADSPECTRUMIN,4,2 ; @PLLB_REF_INPUT_SPREADSPECTRUMIN
	.comm	_PLL_P1_DIVIDE_BY_TWO,4,2       ; @PLL_P1_DIVIDE_BY_TWO
	.comm	_DPLL_FPA01_P1_POST_DIV_MASK_I830,4,2 ; @DPLL_FPA01_P1_POST_DIV_MASK_I830
	.comm	_PLL_P2_DIVIDE_BY_4,4,2         ; @PLL_P2_DIVIDE_BY_4
	.no_dead_strip	_psb_intel_crtc_clock_get
.subsections_via_symbols
