	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_dc_assign_shared_plane
_tegra_dc_assign_shared_plane:          ## @tegra_dc_assign_shared_plane
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r15
	movq	%rdi, %r14
	callq	_tegra_dc_owns_shared_plane
	testl	%eax, %eax
	jne	LBB0_3
## %bb.1:
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_tegra_shared_plane_set_owner
	testl	%eax, %eax
	js	LBB0_2
LBB0_3:
	movq	_DC_WIN_CORE_IHUB_LINEBUF_CONFIG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_tegra_plane_readl
	movq	_MODE_FOUR_LINES@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_tegra_plane_writel
	movq	_DC_WIN_CORE_IHUB_WGRP_FETCH_METER@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_tegra_plane_readl
	movl	$1, %edi
	callq	_SLOTS
	movl	(%rbx), %edx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_tegra_plane_writel
	movq	_DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_tegra_plane_readl
	movq	_LATENCY_CTL_MODE_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edx
	movq	%r15, %rdi
	callq	_tegra_plane_writel
	movq	_DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_tegra_plane_readl
	movq	_WATERMARK_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_tegra_plane_writel
	movq	_DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%r15, %rdi
	callq	_tegra_plane_readl
	xorl	%edi, %edi
	callq	_PIPE_METER_INT
	movl	%eax, %ebx
	xorl	%edi, %edi
	callq	_PIPE_METER_FRAC
	orl	%eax, %ebx
	movl	(%r14), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_tegra_plane_writel
	movq	_DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_tegra_plane_readl
	movl	$817, %edi                      ## imm = 0x331
	callq	_MEMPOOL_ENTRIES
	movl	(%rbx), %edx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_tegra_plane_writel
	movq	_DC_WIN_CORE_IHUB_THREAD_GROUP@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%r15, %rdi
	callq	_tegra_plane_readl
	movq	_THREAD_NUM_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	(%r15), %edi
	callq	_THREAD_NUM
	orl	%eax, %ebx
	movq	_THREAD_GROUP_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	(%r14), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_tegra_plane_writel
	movq	%r15, %rdi
	callq	_tegra_shared_plane_update
	movq	%r15, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_tegra_shared_plane_activate    ## TAILCALL
LBB0_2:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DC_WIN_CORE_IHUB_LINEBUF_CONFIG,4,2 ## @DC_WIN_CORE_IHUB_LINEBUF_CONFIG
	.comm	_MODE_FOUR_LINES,4,2            ## @MODE_FOUR_LINES
	.comm	_DC_WIN_CORE_IHUB_WGRP_FETCH_METER,4,2 ## @DC_WIN_CORE_IHUB_WGRP_FETCH_METER
	.comm	_DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA,4,2 ## @DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA
	.comm	_LATENCY_CTL_MODE_ENABLE,4,2    ## @LATENCY_CTL_MODE_ENABLE
	.comm	_DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB,4,2 ## @DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB
	.comm	_WATERMARK_MASK,4,2             ## @WATERMARK_MASK
	.comm	_DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER,4,2 ## @DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER
	.comm	_DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG,4,2 ## @DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG
	.comm	_DC_WIN_CORE_IHUB_THREAD_GROUP,4,2 ## @DC_WIN_CORE_IHUB_THREAD_GROUP
	.comm	_THREAD_NUM_MASK,4,2            ## @THREAD_NUM_MASK
	.comm	_THREAD_GROUP_ENABLE,4,2        ## @THREAD_GROUP_ENABLE
	.no_dead_strip	_tegra_dc_assign_shared_plane
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_dc_assign_shared_plane
_tegra_dc_assign_shared_plane:          ; @tegra_dc_assign_shared_plane
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x1
	mov	x20, x0
	bl	_tegra_dc_owns_shared_plane
	cbnz	w0, LBB0_2
; %bb.1:
	mov	x0, x19
	mov	x1, x20
	bl	_tegra_shared_plane_set_owner
	tbnz	w0, #31, LBB0_3
LBB0_2:
Lloh0:
	adrp	x20, _DC_WIN_CORE_IHUB_LINEBUF_CONFIG@GOTPAGE
Lloh1:
	ldr	x20, [x20, _DC_WIN_CORE_IHUB_LINEBUF_CONFIG@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_tegra_plane_readl
Lloh2:
	adrp	x8, _MODE_FOUR_LINES@GOTPAGE
Lloh3:
	ldr	x8, [x8, _MODE_FOUR_LINES@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w2, [x20]
	mov	x0, x19
	bl	_tegra_plane_writel
Lloh5:
	adrp	x20, _DC_WIN_CORE_IHUB_WGRP_FETCH_METER@GOTPAGE
Lloh6:
	ldr	x20, [x20, _DC_WIN_CORE_IHUB_WGRP_FETCH_METER@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_tegra_plane_readl
	mov	w0, #1
	bl	_SLOTS
	mov	x1, x0
	ldr	w2, [x20]
	mov	x0, x19
	bl	_tegra_plane_writel
Lloh7:
	adrp	x20, _DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA@GOTPAGE
Lloh8:
	ldr	x20, [x20, _DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_tegra_plane_readl
Lloh9:
	adrp	x8, _LATENCY_CTL_MODE_ENABLE@GOTPAGE
Lloh10:
	ldr	x8, [x8, _LATENCY_CTL_MODE_ENABLE@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w2, [x20]
	mov	x0, x19
	bl	_tegra_plane_writel
Lloh12:
	adrp	x20, _DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB@GOTPAGE
Lloh13:
	ldr	x20, [x20, _DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_tegra_plane_readl
Lloh14:
	adrp	x8, _WATERMARK_MASK@GOTPAGE
Lloh15:
	ldr	x8, [x8, _WATERMARK_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w2, [x20]
	mov	x0, x19
	bl	_tegra_plane_writel
Lloh17:
	adrp	x21, _DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER@GOTPAGE
Lloh18:
	ldr	x21, [x21, _DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_tegra_plane_readl
	mov	w0, #0
	bl	_PIPE_METER_INT
	mov	x20, x0
	mov	w0, #0
	bl	_PIPE_METER_FRAC
	orr	w1, w0, w20
	ldr	w2, [x21]
	mov	x0, x19
	bl	_tegra_plane_writel
Lloh19:
	adrp	x20, _DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG@GOTPAGE
Lloh20:
	ldr	x20, [x20, _DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_tegra_plane_readl
	mov	w0, #817
	bl	_MEMPOOL_ENTRIES
	mov	x1, x0
	ldr	w2, [x20]
	mov	x0, x19
	bl	_tegra_plane_writel
Lloh21:
	adrp	x20, _DC_WIN_CORE_IHUB_THREAD_GROUP@GOTPAGE
Lloh22:
	ldr	x20, [x20, _DC_WIN_CORE_IHUB_THREAD_GROUP@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_tegra_plane_readl
Lloh23:
	adrp	x8, _THREAD_NUM_MASK@GOTPAGE
Lloh24:
	ldr	x8, [x8, _THREAD_NUM_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
	bic	w21, w0, w8
	ldr	w0, [x19]
	bl	_THREAD_NUM
	orr	w8, w0, w21
Lloh26:
	adrp	x9, _THREAD_GROUP_ENABLE@GOTPAGE
Lloh27:
	ldr	x9, [x9, _THREAD_GROUP_ENABLE@GOTPAGEOFF]
Lloh28:
	ldr	w9, [x9]
	orr	w1, w8, w9
	ldr	w2, [x20]
	mov	x0, x19
	bl	_tegra_plane_writel
	mov	x0, x19
	bl	_tegra_shared_plane_update
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_tegra_shared_plane_activate
LBB0_3:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_DC_WIN_CORE_IHUB_LINEBUF_CONFIG,4,2 ; @DC_WIN_CORE_IHUB_LINEBUF_CONFIG
	.comm	_MODE_FOUR_LINES,4,2            ; @MODE_FOUR_LINES
	.comm	_DC_WIN_CORE_IHUB_WGRP_FETCH_METER,4,2 ; @DC_WIN_CORE_IHUB_WGRP_FETCH_METER
	.comm	_DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA,4,2 ; @DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA
	.comm	_LATENCY_CTL_MODE_ENABLE,4,2    ; @LATENCY_CTL_MODE_ENABLE
	.comm	_DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB,4,2 ; @DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB
	.comm	_WATERMARK_MASK,4,2             ; @WATERMARK_MASK
	.comm	_DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER,4,2 ; @DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER
	.comm	_DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG,4,2 ; @DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG
	.comm	_DC_WIN_CORE_IHUB_THREAD_GROUP,4,2 ; @DC_WIN_CORE_IHUB_THREAD_GROUP
	.comm	_THREAD_NUM_MASK,4,2            ; @THREAD_NUM_MASK
	.comm	_THREAD_GROUP_ENABLE,4,2        ; @THREAD_GROUP_ENABLE
	.no_dead_strip	_tegra_dc_assign_shared_plane
.subsections_via_symbols
