	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function a4xx_enable_hwcg
_a4xx_enable_hwcg:                      ## @a4xx_enable_hwcg
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	callq	_to_adreno_gpu
	movq	%rax, %r15
	xorl	%r14d, %r14d
	xorl	%edi, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL_TP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$35791362, %edx                 ## imm = 0x2222202
	callq	_gpu_write
	movl	$1, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL_TP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$35791362, %edx                 ## imm = 0x2222202
	callq	_gpu_write
	movl	$2, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL_TP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$35791362, %edx                 ## imm = 0x2222202
	callq	_gpu_write
	movl	$3, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL_TP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$35791362, %edx                 ## imm = 0x2222202
	callq	_gpu_write
	xorl	%edi, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL2_TP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$8738, %edx                     ## imm = 0x2222
	callq	_gpu_write
	movl	$1, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL2_TP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$8738, %edx                     ## imm = 0x2222
	callq	_gpu_write
	movl	$2, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL2_TP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$8738, %edx                     ## imm = 0x2222
	callq	_gpu_write
	movl	$3, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL2_TP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$8738, %edx                     ## imm = 0x2222
	callq	_gpu_write
	xorl	%edi, %edi
	callq	_REG_A4XX_RBBM_CLOCK_HYST_TP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$242457831, %edx                ## imm = 0xE739CE7
	callq	_gpu_write
	movl	$1, %edi
	callq	_REG_A4XX_RBBM_CLOCK_HYST_TP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$242457831, %edx                ## imm = 0xE739CE7
	callq	_gpu_write
	movl	$2, %edi
	callq	_REG_A4XX_RBBM_CLOCK_HYST_TP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$242457831, %edx                ## imm = 0xE739CE7
	callq	_gpu_write
	movl	$3, %edi
	callq	_REG_A4XX_RBBM_CLOCK_HYST_TP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$242457831, %edx                ## imm = 0xE739CE7
	callq	_gpu_write
	xorl	%edi, %edi
	callq	_REG_A4XX_RBBM_CLOCK_DELAY_TP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$1118481, %edx                  ## imm = 0x111111
	callq	_gpu_write
	movl	$1, %edi
	callq	_REG_A4XX_RBBM_CLOCK_DELAY_TP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$1118481, %edx                  ## imm = 0x111111
	callq	_gpu_write
	movl	$2, %edi
	callq	_REG_A4XX_RBBM_CLOCK_DELAY_TP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$1118481, %edx                  ## imm = 0x111111
	callq	_gpu_write
	movl	$3, %edi
	callq	_REG_A4XX_RBBM_CLOCK_DELAY_TP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$1118481, %edx                  ## imm = 0x111111
	callq	_gpu_write
	xorl	%edi, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL_SP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$572662306, %edx                ## imm = 0x22222222
	callq	_gpu_write
	movl	$1, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL_SP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$572662306, %edx                ## imm = 0x22222222
	callq	_gpu_write
	movl	$2, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL_SP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$572662306, %edx                ## imm = 0x22222222
	callq	_gpu_write
	movl	$3, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL_SP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$572662306, %edx                ## imm = 0x22222222
	callq	_gpu_write
	xorl	%edi, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL2_SP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$2236962, %edx                  ## imm = 0x222222
	callq	_gpu_write
	movl	$1, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL2_SP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$2236962, %edx                  ## imm = 0x222222
	callq	_gpu_write
	movl	$2, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL2_SP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$2236962, %edx                  ## imm = 0x222222
	callq	_gpu_write
	movl	$3, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL2_SP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$2236962, %edx                  ## imm = 0x222222
	callq	_gpu_write
	xorl	%edi, %edi
	callq	_REG_A4XX_RBBM_CLOCK_HYST_SP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$260, %edx                      ## imm = 0x104
	callq	_gpu_write
	movl	$1, %edi
	callq	_REG_A4XX_RBBM_CLOCK_HYST_SP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$260, %edx                      ## imm = 0x104
	callq	_gpu_write
	movl	$2, %edi
	callq	_REG_A4XX_RBBM_CLOCK_HYST_SP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$260, %edx                      ## imm = 0x104
	callq	_gpu_write
	movl	$3, %edi
	callq	_REG_A4XX_RBBM_CLOCK_HYST_SP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$260, %edx                      ## imm = 0x104
	callq	_gpu_write
	xorl	%edi, %edi
	callq	_REG_A4XX_RBBM_CLOCK_DELAY_SP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$129, %edx
	callq	_gpu_write
	movl	$1, %edi
	callq	_REG_A4XX_RBBM_CLOCK_DELAY_SP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$129, %edx
	callq	_gpu_write
	movl	$2, %edi
	callq	_REG_A4XX_RBBM_CLOCK_DELAY_SP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$129, %edx
	callq	_gpu_write
	movl	$3, %edi
	callq	_REG_A4XX_RBBM_CLOCK_DELAY_SP
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$129, %edx
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_CLOCK_CTL_UCHE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$572662306, %edx                ## imm = 0x22222222
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_CLOCK_CTL2_UCHE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$35791394, %edx                 ## imm = 0x2222222
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_CLOCK_CTL3_UCHE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_CLOCK_CTL4_UCHE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_CLOCK_HYST_UCHE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$17476, %edx                    ## imm = 0x4444
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_CLOCK_DELAY_UCHE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$4370, %edx                     ## imm = 0x1112
	callq	_gpu_write
	xorl	%edi, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL_RB
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$572662306, %edx                ## imm = 0x22222222
	callq	_gpu_write
	movl	$1, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL_RB
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$572662306, %edx                ## imm = 0x22222222
	callq	_gpu_write
	movl	$2, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL_RB
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$572662306, %edx                ## imm = 0x22222222
	callq	_gpu_write
	movl	$3, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL_RB
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$572662306, %edx                ## imm = 0x22222222
	callq	_gpu_write
	movq	%r15, %rdi
	callq	_adreno_is_a420
	xorl	%ebx, %ebx
	testq	%rax, %rax
	sete	%bl
	xorl	%edi, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL2_RB
	shll	$17, %ebx
	orl	$8224, %ebx                     ## imm = 0x2020
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	%ebx, %edx
	callq	_gpu_write
	movq	%r15, %rdi
	callq	_adreno_is_a420
	xorl	%ebx, %ebx
	testq	%rax, %rax
	sete	%bl
	shll	$17, %ebx
	orl	$8224, %ebx                     ## imm = 0x2020
	movl	$1, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL2_RB
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	%ebx, %edx
	callq	_gpu_write
	movq	%r15, %rdi
	callq	_adreno_is_a420
	xorl	%ebx, %ebx
	testq	%rax, %rax
	sete	%bl
	shll	$17, %ebx
	orl	$8224, %ebx                     ## imm = 0x2020
	movl	$2, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL2_RB
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	%ebx, %edx
	callq	_gpu_write
	movq	%r15, %rdi
	callq	_adreno_is_a420
	xorl	%ebx, %ebx
	testq	%rax, %rax
	sete	%bl
	shll	$17, %ebx
	orl	$8224, %ebx                     ## imm = 0x2020
	movl	$3, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL2_RB
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	%ebx, %edx
	callq	_gpu_write
	xorl	%edi, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$2338, %edx                     ## imm = 0x922
	callq	_gpu_write
	movl	$1, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$2338, %edx                     ## imm = 0x922
	callq	_gpu_write
	movl	$2, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$2338, %edx                     ## imm = 0x922
	callq	_gpu_write
	movl	$3, %edi
	callq	_REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$2338, %edx                     ## imm = 0x922
	callq	_gpu_write
	xorl	%edi, %edi
	callq	_REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU
	movq	%r12, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_gpu_write
	movl	$1, %edi
	callq	_REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU
	movq	%r12, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_gpu_write
	movl	$2, %edi
	callq	_REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU
	movq	%r12, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_gpu_write
	movl	$3, %edi
	callq	_REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU
	movq	%r12, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_gpu_write
	xorl	%edi, %edi
	callq	_REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$1, %edx
	callq	_gpu_write
	movl	$1, %edi
	callq	_REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$1, %edx
	callq	_gpu_write
	movl	$2, %edi
	callq	_REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$1, %edx
	callq	_gpu_write
	movl	$3, %edi
	callq	_REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	$1, %edx
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_CLOCK_MODE_GPC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$35791394, %edx                 ## imm = 0x2222222
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_CLOCK_HYST_GPC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$68157700, %edx                 ## imm = 0x4100104
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_CLOCK_DELAY_GPC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$139810, %edx                   ## imm = 0x22222
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$34, %edx
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$271, %edx                      ## imm = 0x10F
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$34, %edx
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$2236962, %edx                  ## imm = 0x222222
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$16644, %edx                    ## imm = 0x4104
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$546, %edx                      ## imm = 0x222
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_CLOCK_CTL_HLSQ@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_CLOCK_HYST_HLSQ@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_CLOCK_DELAY_HLSQ@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$2228224, %edx                  ## imm = 0x220000
	callq	_gpu_write
	movq	%r15, %rdi
	callq	_adreno_is_a430
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	cmpl	$2, (%r15)
	jl	LBB0_3
LBB0_2:
	movl	$-1431655766, %r14d             ## imm = 0xAAAAAAAA
LBB0_3:
	movq	_REG_A4XX_RBBM_CLOCK_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	%r14d, %edx
	callq	_gpu_write
	movq	_REG_A4XX_RBBM_CLOCK_CTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_gpu_write                      ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_REG_A4XX_RBBM_CLOCK_CTL_UCHE,4,2 ## @REG_A4XX_RBBM_CLOCK_CTL_UCHE
	.comm	_REG_A4XX_RBBM_CLOCK_CTL2_UCHE,4,2 ## @REG_A4XX_RBBM_CLOCK_CTL2_UCHE
	.comm	_REG_A4XX_RBBM_CLOCK_CTL3_UCHE,4,2 ## @REG_A4XX_RBBM_CLOCK_CTL3_UCHE
	.comm	_REG_A4XX_RBBM_CLOCK_CTL4_UCHE,4,2 ## @REG_A4XX_RBBM_CLOCK_CTL4_UCHE
	.comm	_REG_A4XX_RBBM_CLOCK_HYST_UCHE,4,2 ## @REG_A4XX_RBBM_CLOCK_HYST_UCHE
	.comm	_REG_A4XX_RBBM_CLOCK_DELAY_UCHE,4,2 ## @REG_A4XX_RBBM_CLOCK_DELAY_UCHE
	.comm	_REG_A4XX_RBBM_CLOCK_MODE_GPC,4,2 ## @REG_A4XX_RBBM_CLOCK_MODE_GPC
	.comm	_REG_A4XX_RBBM_CLOCK_HYST_GPC,4,2 ## @REG_A4XX_RBBM_CLOCK_HYST_GPC
	.comm	_REG_A4XX_RBBM_CLOCK_DELAY_GPC,4,2 ## @REG_A4XX_RBBM_CLOCK_DELAY_GPC
	.comm	_REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM,4,2 ## @REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM
	.comm	_REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM,4,2 ## @REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM
	.comm	_REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM,4,2 ## @REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM
	.comm	_REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM,4,2 ## @REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM
	.comm	_REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM,4,2 ## @REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM
	.comm	_REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM,4,2 ## @REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM
	.comm	_REG_A4XX_RBBM_CLOCK_CTL_HLSQ,4,2 ## @REG_A4XX_RBBM_CLOCK_CTL_HLSQ
	.comm	_REG_A4XX_RBBM_CLOCK_HYST_HLSQ,4,2 ## @REG_A4XX_RBBM_CLOCK_HYST_HLSQ
	.comm	_REG_A4XX_RBBM_CLOCK_DELAY_HLSQ,4,2 ## @REG_A4XX_RBBM_CLOCK_DELAY_HLSQ
	.comm	_REG_A4XX_RBBM_CLOCK_CTL,4,2    ## @REG_A4XX_RBBM_CLOCK_CTL
	.comm	_REG_A4XX_RBBM_CLOCK_CTL2,4,2   ## @REG_A4XX_RBBM_CLOCK_CTL2
	.no_dead_strip	_a4xx_enable_hwcg
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function a4xx_enable_hwcg
_a4xx_enable_hwcg:                      ; @a4xx_enable_hwcg
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	bl	_to_adreno_gpu
	mov	x20, x0
	mov	w0, #0
	bl	_REG_A4XX_RBBM_CLOCK_CTL_TP
	mov	x1, x0
	mov	w21, #8706
	movk	w21, #546, lsl #16
	mov	x0, x19
	mov	w2, #8706
	movk	w2, #546, lsl #16
	bl	_gpu_write
	mov	w0, #1
	bl	_REG_A4XX_RBBM_CLOCK_CTL_TP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #8706
	movk	w2, #546, lsl #16
	bl	_gpu_write
	mov	w0, #2
	bl	_REG_A4XX_RBBM_CLOCK_CTL_TP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #8706
	movk	w2, #546, lsl #16
	bl	_gpu_write
	mov	w0, #3
	bl	_REG_A4XX_RBBM_CLOCK_CTL_TP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #8706
	movk	w2, #546, lsl #16
	bl	_gpu_write
	mov	w0, #0
	bl	_REG_A4XX_RBBM_CLOCK_CTL2_TP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #8738
	bl	_gpu_write
	mov	w0, #1
	bl	_REG_A4XX_RBBM_CLOCK_CTL2_TP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #8738
	bl	_gpu_write
	mov	w0, #2
	bl	_REG_A4XX_RBBM_CLOCK_CTL2_TP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #8738
	bl	_gpu_write
	mov	w0, #3
	bl	_REG_A4XX_RBBM_CLOCK_CTL2_TP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #8738
	bl	_gpu_write
	mov	w0, #0
	bl	_REG_A4XX_RBBM_CLOCK_HYST_TP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #40167
	movk	w2, #3699, lsl #16
	bl	_gpu_write
	mov	w0, #1
	bl	_REG_A4XX_RBBM_CLOCK_HYST_TP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #40167
	movk	w2, #3699, lsl #16
	bl	_gpu_write
	mov	w0, #2
	bl	_REG_A4XX_RBBM_CLOCK_HYST_TP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #40167
	movk	w2, #3699, lsl #16
	bl	_gpu_write
	mov	w0, #3
	bl	_REG_A4XX_RBBM_CLOCK_HYST_TP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #40167
	movk	w2, #3699, lsl #16
	bl	_gpu_write
	mov	w0, #0
	bl	_REG_A4XX_RBBM_CLOCK_DELAY_TP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #4369
	movk	w2, #17, lsl #16
	bl	_gpu_write
	mov	w0, #1
	bl	_REG_A4XX_RBBM_CLOCK_DELAY_TP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #4369
	movk	w2, #17, lsl #16
	bl	_gpu_write
	mov	w0, #2
	bl	_REG_A4XX_RBBM_CLOCK_DELAY_TP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #4369
	movk	w2, #17, lsl #16
	bl	_gpu_write
	mov	w0, #3
	bl	_REG_A4XX_RBBM_CLOCK_DELAY_TP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #4369
	movk	w2, #17, lsl #16
	bl	_gpu_write
	mov	w0, #0
	bl	_REG_A4XX_RBBM_CLOCK_CTL_SP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #572662306
	bl	_gpu_write
	mov	w0, #1
	bl	_REG_A4XX_RBBM_CLOCK_CTL_SP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #572662306
	bl	_gpu_write
	mov	w0, #2
	bl	_REG_A4XX_RBBM_CLOCK_CTL_SP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #572662306
	bl	_gpu_write
	mov	w0, #3
	bl	_REG_A4XX_RBBM_CLOCK_CTL_SP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #572662306
	bl	_gpu_write
	mov	w0, #0
	bl	_REG_A4XX_RBBM_CLOCK_CTL2_SP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #8738
	movk	w2, #34, lsl #16
	bl	_gpu_write
	mov	w0, #1
	bl	_REG_A4XX_RBBM_CLOCK_CTL2_SP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #8738
	movk	w2, #34, lsl #16
	bl	_gpu_write
	mov	w0, #2
	bl	_REG_A4XX_RBBM_CLOCK_CTL2_SP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #8738
	movk	w2, #34, lsl #16
	bl	_gpu_write
	mov	w0, #3
	bl	_REG_A4XX_RBBM_CLOCK_CTL2_SP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #8738
	movk	w2, #34, lsl #16
	bl	_gpu_write
	mov	w0, #0
	bl	_REG_A4XX_RBBM_CLOCK_HYST_SP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #260
	bl	_gpu_write
	mov	w0, #1
	bl	_REG_A4XX_RBBM_CLOCK_HYST_SP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #260
	bl	_gpu_write
	mov	w0, #2
	bl	_REG_A4XX_RBBM_CLOCK_HYST_SP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #260
	bl	_gpu_write
	mov	w0, #3
	bl	_REG_A4XX_RBBM_CLOCK_HYST_SP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #260
	bl	_gpu_write
	mov	w0, #0
	bl	_REG_A4XX_RBBM_CLOCK_DELAY_SP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #129
	bl	_gpu_write
	mov	w0, #1
	bl	_REG_A4XX_RBBM_CLOCK_DELAY_SP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #129
	bl	_gpu_write
	mov	w0, #2
	bl	_REG_A4XX_RBBM_CLOCK_DELAY_SP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #129
	bl	_gpu_write
	mov	w0, #3
	bl	_REG_A4XX_RBBM_CLOCK_DELAY_SP
	mov	x1, x0
	mov	x0, x19
	mov	w2, #129
	bl	_gpu_write
Lloh0:
	adrp	x8, _REG_A4XX_RBBM_CLOCK_CTL_UCHE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _REG_A4XX_RBBM_CLOCK_CTL_UCHE@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #572662306
	bl	_gpu_write
Lloh3:
	adrp	x8, _REG_A4XX_RBBM_CLOCK_CTL2_UCHE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _REG_A4XX_RBBM_CLOCK_CTL2_UCHE@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	orr	w21, w21, #0x20
	mov	x0, x19
	mov	x2, x21
	bl	_gpu_write
Lloh6:
	adrp	x8, _REG_A4XX_RBBM_CLOCK_CTL3_UCHE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _REG_A4XX_RBBM_CLOCK_CTL3_UCHE@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
Lloh9:
	adrp	x8, _REG_A4XX_RBBM_CLOCK_CTL4_UCHE@GOTPAGE
Lloh10:
	ldr	x8, [x8, _REG_A4XX_RBBM_CLOCK_CTL4_UCHE@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
Lloh12:
	adrp	x8, _REG_A4XX_RBBM_CLOCK_HYST_UCHE@GOTPAGE
Lloh13:
	ldr	x8, [x8, _REG_A4XX_RBBM_CLOCK_HYST_UCHE@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #17476
	bl	_gpu_write
Lloh15:
	adrp	x8, _REG_A4XX_RBBM_CLOCK_DELAY_UCHE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _REG_A4XX_RBBM_CLOCK_DELAY_UCHE@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #4370
	bl	_gpu_write
	mov	w0, #0
	bl	_REG_A4XX_RBBM_CLOCK_CTL_RB
	mov	x1, x0
	mov	x0, x19
	mov	w2, #572662306
	bl	_gpu_write
	mov	w0, #1
	bl	_REG_A4XX_RBBM_CLOCK_CTL_RB
	mov	x1, x0
	mov	x0, x19
	mov	w2, #572662306
	bl	_gpu_write
	mov	w0, #2
	bl	_REG_A4XX_RBBM_CLOCK_CTL_RB
	mov	x1, x0
	mov	x0, x19
	mov	w2, #572662306
	bl	_gpu_write
	mov	w0, #3
	bl	_REG_A4XX_RBBM_CLOCK_CTL_RB
	mov	x1, x0
	mov	x0, x19
	mov	w2, #572662306
	bl	_gpu_write
	mov	x0, x20
	bl	_adreno_is_a420
	mov	x22, x0
	mov	w0, #0
	bl	_REG_A4XX_RBBM_CLOCK_CTL2_RB
	mov	x1, x0
	cmp	x22, #0
	mov	w24, #8224
	mov	w23, #8224
	movk	w23, #2, lsl #16
	csel	w2, w23, w24, eq
	mov	x0, x19
	bl	_gpu_write
	mov	x0, x20
	bl	_adreno_is_a420
	cmp	x0, #0
	csel	w22, w23, w24, eq
	mov	w0, #1
	bl	_REG_A4XX_RBBM_CLOCK_CTL2_RB
	mov	x1, x0
	mov	x0, x19
	mov	x2, x22
	bl	_gpu_write
	mov	x0, x20
	bl	_adreno_is_a420
	cmp	x0, #0
	csel	w22, w23, w24, eq
	mov	w0, #2
	bl	_REG_A4XX_RBBM_CLOCK_CTL2_RB
	mov	x1, x0
	mov	x0, x19
	mov	x2, x22
	bl	_gpu_write
	mov	x0, x20
	bl	_adreno_is_a420
	cmp	x0, #0
	csel	w22, w23, w24, eq
	mov	w0, #3
	bl	_REG_A4XX_RBBM_CLOCK_CTL2_RB
	mov	x1, x0
	mov	x0, x19
	mov	x2, x22
	bl	_gpu_write
	mov	w0, #0
	bl	_REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU
	mov	x1, x0
	mov	x0, x19
	mov	w2, #2338
	bl	_gpu_write
	mov	w0, #1
	bl	_REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU
	mov	x1, x0
	mov	x0, x19
	mov	w2, #2338
	bl	_gpu_write
	mov	w0, #2
	bl	_REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU
	mov	x1, x0
	mov	x0, x19
	mov	w2, #2338
	bl	_gpu_write
	mov	w0, #3
	bl	_REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU
	mov	x1, x0
	mov	x0, x19
	mov	w2, #2338
	bl	_gpu_write
	mov	w0, #0
	bl	_REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU
	mov	x1, x0
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
	mov	w0, #1
	bl	_REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU
	mov	x1, x0
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
	mov	w0, #2
	bl	_REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU
	mov	x1, x0
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
	mov	w0, #3
	bl	_REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU
	mov	x1, x0
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
	mov	w0, #0
	bl	_REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1
	mov	x1, x0
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
	mov	w0, #1
	bl	_REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1
	mov	x1, x0
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
	mov	w0, #2
	bl	_REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1
	mov	x1, x0
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
	mov	w0, #3
	bl	_REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1
	mov	x1, x0
	mov	x0, x19
	mov	w2, #1
	bl	_gpu_write
Lloh18:
	adrp	x8, _REG_A4XX_RBBM_CLOCK_MODE_GPC@GOTPAGE
Lloh19:
	ldr	x8, [x8, _REG_A4XX_RBBM_CLOCK_MODE_GPC@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_gpu_write
Lloh21:
	adrp	x8, _REG_A4XX_RBBM_CLOCK_HYST_GPC@GOTPAGE
Lloh22:
	ldr	x8, [x8, _REG_A4XX_RBBM_CLOCK_HYST_GPC@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #260
	movk	w2, #1040, lsl #16
	bl	_gpu_write
Lloh24:
	adrp	x8, _REG_A4XX_RBBM_CLOCK_DELAY_GPC@GOTPAGE
Lloh25:
	ldr	x8, [x8, _REG_A4XX_RBBM_CLOCK_DELAY_GPC@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	w8, #514
	orr	w2, w23, w8
	mov	x0, x19
	bl	_gpu_write
Lloh27:
	adrp	x8, _REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM@GOTPAGE
Lloh28:
	ldr	x8, [x8, _REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #34
	bl	_gpu_write
Lloh30:
	adrp	x8, _REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM@GOTPAGE
Lloh31:
	ldr	x8, [x8, _REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #271
	bl	_gpu_write
Lloh33:
	adrp	x8, _REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM@GOTPAGE
Lloh34:
	ldr	x8, [x8, _REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM@GOTPAGEOFF]
Lloh35:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #34
	bl	_gpu_write
Lloh36:
	adrp	x8, _REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM@GOTPAGE
Lloh37:
	ldr	x8, [x8, _REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #8738
	movk	w2, #34, lsl #16
	bl	_gpu_write
Lloh39:
	adrp	x8, _REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM@GOTPAGE
Lloh40:
	ldr	x8, [x8, _REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #16644
	bl	_gpu_write
Lloh42:
	adrp	x8, _REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM@GOTPAGE
Lloh43:
	ldr	x8, [x8, _REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #546
	bl	_gpu_write
Lloh45:
	adrp	x8, _REG_A4XX_RBBM_CLOCK_CTL_HLSQ@GOTPAGE
Lloh46:
	ldr	x8, [x8, _REG_A4XX_RBBM_CLOCK_CTL_HLSQ@GOTPAGEOFF]
Lloh47:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
Lloh48:
	adrp	x8, _REG_A4XX_RBBM_CLOCK_HYST_HLSQ@GOTPAGE
Lloh49:
	ldr	x8, [x8, _REG_A4XX_RBBM_CLOCK_HYST_HLSQ@GOTPAGEOFF]
Lloh50:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
Lloh51:
	adrp	x8, _REG_A4XX_RBBM_CLOCK_DELAY_HLSQ@GOTPAGE
Lloh52:
	ldr	x8, [x8, _REG_A4XX_RBBM_CLOCK_DELAY_HLSQ@GOTPAGEOFF]
Lloh53:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #2228224
	bl	_gpu_write
	mov	x0, x20
	bl	_adreno_is_a430
	cbz	x0, LBB0_3
; %bb.1:
	ldr	w8, [x20]
	cmp	w8, #2
	b.ge	LBB0_3
; %bb.2:
	mov	w2, #0
	b	LBB0_4
LBB0_3:
	mov	w2, #-1431655766
LBB0_4:
Lloh54:
	adrp	x8, _REG_A4XX_RBBM_CLOCK_CTL@GOTPAGE
Lloh55:
	ldr	x8, [x8, _REG_A4XX_RBBM_CLOCK_CTL@GOTPAGEOFF]
Lloh56:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_gpu_write
Lloh57:
	adrp	x8, _REG_A4XX_RBBM_CLOCK_CTL2@GOTPAGE
Lloh58:
	ldr	x8, [x8, _REG_A4XX_RBBM_CLOCK_CTL2@GOTPAGEOFF]
Lloh59:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_gpu_write
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.cfi_endproc
                                        ; -- End function
	.comm	_REG_A4XX_RBBM_CLOCK_CTL_UCHE,4,2 ; @REG_A4XX_RBBM_CLOCK_CTL_UCHE
	.comm	_REG_A4XX_RBBM_CLOCK_CTL2_UCHE,4,2 ; @REG_A4XX_RBBM_CLOCK_CTL2_UCHE
	.comm	_REG_A4XX_RBBM_CLOCK_CTL3_UCHE,4,2 ; @REG_A4XX_RBBM_CLOCK_CTL3_UCHE
	.comm	_REG_A4XX_RBBM_CLOCK_CTL4_UCHE,4,2 ; @REG_A4XX_RBBM_CLOCK_CTL4_UCHE
	.comm	_REG_A4XX_RBBM_CLOCK_HYST_UCHE,4,2 ; @REG_A4XX_RBBM_CLOCK_HYST_UCHE
	.comm	_REG_A4XX_RBBM_CLOCK_DELAY_UCHE,4,2 ; @REG_A4XX_RBBM_CLOCK_DELAY_UCHE
	.comm	_REG_A4XX_RBBM_CLOCK_MODE_GPC,4,2 ; @REG_A4XX_RBBM_CLOCK_MODE_GPC
	.comm	_REG_A4XX_RBBM_CLOCK_HYST_GPC,4,2 ; @REG_A4XX_RBBM_CLOCK_HYST_GPC
	.comm	_REG_A4XX_RBBM_CLOCK_DELAY_GPC,4,2 ; @REG_A4XX_RBBM_CLOCK_DELAY_GPC
	.comm	_REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM,4,2 ; @REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM
	.comm	_REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM,4,2 ; @REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM
	.comm	_REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM,4,2 ; @REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM
	.comm	_REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM,4,2 ; @REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM
	.comm	_REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM,4,2 ; @REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM
	.comm	_REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM,4,2 ; @REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM
	.comm	_REG_A4XX_RBBM_CLOCK_CTL_HLSQ,4,2 ; @REG_A4XX_RBBM_CLOCK_CTL_HLSQ
	.comm	_REG_A4XX_RBBM_CLOCK_HYST_HLSQ,4,2 ; @REG_A4XX_RBBM_CLOCK_HYST_HLSQ
	.comm	_REG_A4XX_RBBM_CLOCK_DELAY_HLSQ,4,2 ; @REG_A4XX_RBBM_CLOCK_DELAY_HLSQ
	.comm	_REG_A4XX_RBBM_CLOCK_CTL,4,2    ; @REG_A4XX_RBBM_CLOCK_CTL
	.comm	_REG_A4XX_RBBM_CLOCK_CTL2,4,2   ; @REG_A4XX_RBBM_CLOCK_CTL2
	.no_dead_strip	_a4xx_enable_hwcg
.subsections_via_symbols
