	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vi_get_rev_id
_vi_get_rev_id:                         ## @vi_get_rev_id
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rdi)
	je	LBB0_2
## %bb.1:
	movq	_ATI_REV_ID_FUSE_MACRO__ADDRESS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_SMC
	movq	_ATI_REV_ID_FUSE_MACRO__SHIFT@GOTPCREL(%rip), %rcx
	movq	_ATI_REV_ID_FUSE_MACRO__MASK@GOTPCREL(%rip), %rdx
	jmp	LBB0_3
LBB0_2:
	movq	_mmPCIE_EFUSE4@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT@GOTPCREL(%rip), %rcx
	movq	_PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK@GOTPCREL(%rip), %rdx
LBB0_3:
	andl	(%rdx), %eax
	movb	(%rcx), %cl
	sarl	%cl, %eax
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_ATI_REV_ID_FUSE_MACRO__ADDRESS,4,2 ## @ATI_REV_ID_FUSE_MACRO__ADDRESS
	.comm	_ATI_REV_ID_FUSE_MACRO__MASK,4,2 ## @ATI_REV_ID_FUSE_MACRO__MASK
	.comm	_ATI_REV_ID_FUSE_MACRO__SHIFT,4,2 ## @ATI_REV_ID_FUSE_MACRO__SHIFT
	.comm	_mmPCIE_EFUSE4,4,2              ## @mmPCIE_EFUSE4
	.comm	_PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK,4,2 ## @PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK
	.comm	_PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT,4,2 ## @PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT
	.no_dead_strip	_vi_get_rev_id
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vi_get_rev_id
_vi_get_rev_id:                         ; @vi_get_rev_id
	.cfi_startproc
; %bb.0:
	stp	x29, x30, [sp, #-16]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 16
	mov	x29, sp
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _AMD_IS_APU@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_IS_APU@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
Lloh3:
	adrp	x8, _ATI_REV_ID_FUSE_MACRO__ADDRESS@GOTPAGE
Lloh4:
	ldr	x8, [x8, _ATI_REV_ID_FUSE_MACRO__ADDRESS@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	bl	_RREG32_SMC
Lloh6:
	adrp	x8, _ATI_REV_ID_FUSE_MACRO__SHIFT@GOTPAGE
Lloh7:
	ldr	x8, [x8, _ATI_REV_ID_FUSE_MACRO__SHIFT@GOTPAGEOFF]
Lloh8:
	adrp	x9, _ATI_REV_ID_FUSE_MACRO__MASK@GOTPAGE
Lloh9:
	ldr	x9, [x9, _ATI_REV_ID_FUSE_MACRO__MASK@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:
Lloh10:
	adrp	x8, _mmPCIE_EFUSE4@GOTPAGE
Lloh11:
	ldr	x8, [x8, _mmPCIE_EFUSE4@GOTPAGEOFF]
Lloh12:
	ldr	w0, [x8]
	bl	_RREG32
Lloh13:
	adrp	x8, _PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT@GOTPAGE
Lloh14:
	ldr	x8, [x8, _PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT@GOTPAGEOFF]
Lloh15:
	adrp	x9, _PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK@GOTPAGE
Lloh16:
	ldr	x9, [x9, _PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK@GOTPAGEOFF]
LBB0_3:
	ldr	w9, [x9]
	and	w9, w9, w0
	ldr	w8, [x8]
	asr	w0, w9, w8
	ldp	x29, x30, [sp], #16             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_ATI_REV_ID_FUSE_MACRO__ADDRESS,4,2 ; @ATI_REV_ID_FUSE_MACRO__ADDRESS
	.comm	_ATI_REV_ID_FUSE_MACRO__MASK,4,2 ; @ATI_REV_ID_FUSE_MACRO__MASK
	.comm	_ATI_REV_ID_FUSE_MACRO__SHIFT,4,2 ; @ATI_REV_ID_FUSE_MACRO__SHIFT
	.comm	_mmPCIE_EFUSE4,4,2              ; @mmPCIE_EFUSE4
	.comm	_PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK,4,2 ; @PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK
	.comm	_PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT,4,2 ; @PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT
	.no_dead_strip	_vi_get_rev_id
.subsections_via_symbols
