	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_uvd_ring_parse_cs       ## -- Begin function amdgpu_uvd_ring_parse_cs
	.p2align	4, 0x90
_amdgpu_uvd_ring_parse_cs:              ## @amdgpu_uvd_ring_parse_cs
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	subq	$64, %rsp
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %r15
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -40(%rbp)
	movq	$0, -80(%rbp)
	movl	l___const.amdgpu_uvd_ring_parse_cs.buf_sizes+16(%rip), %eax
	movl	%eax, -48(%rbp)
	movaps	l___const.amdgpu_uvd_ring_parse_cs.buf_sizes(%rip), %xmm0
	movaps	%xmm0, -64(%rbp)
	movq	8(%rdi), %rax
	movq	8(%rax), %r12
	movq	$0, (%rax)
	leaq	(%rsi,%rsi,2), %rbx
	movl	4(%r12,%rbx,4), %edi
	callq	_amdgpu_sa_bo_gpu_addr
	movl	%eax, 8(%r12,%rbx,4)
	movl	(%r12,%rbx,4), %esi
	testb	$15, %sil
	je	LBB0_2
## %bb.1:
	leaq	L_.str(%rip), %rdi
	xorl	%ebx, %ebx
	xorl	%eax, %eax
	callq	_DRM_ERROR
LBB0_7:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	subl	(%rax), %ebx
	jmp	LBB0_8
LBB0_2:
	movq	%r15, -72(%rbp)
	leaq	-64(%rbp), %rax
	movq	%rax, -96(%rbp)
	movq	%r14, -88(%rbp)
	movq	(%r15), %rax
	cmpl	$0, (%rax)
	je	LBB0_3
LBB0_4:
	movq	_amdgpu_uvd_cs_pass2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-96(%rbp), %rdi
	callq	_amdgpu_uvd_cs_packets
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_8
## %bb.5:
	xorl	%ebx, %ebx
	cmpl	$0, -80(%rbp)
	jne	LBB0_8
## %bb.6:
	leaq	L_.str.1(%rip), %rdi
	xorl	%ebx, %ebx
	xorl	%eax, %eax
	callq	_DRM_ERROR
	jmp	LBB0_7
LBB0_3:
	movq	_amdgpu_uvd_cs_pass1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-96(%rbp), %rdi
	callq	_amdgpu_uvd_cs_packets
	movl	%eax, %ebx
	testl	%eax, %eax
	je	LBB0_4
LBB0_8:
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	cmpq	-40(%rbp), %rax
	jne	LBB0_10
## %bb.9:
	movl	%ebx, %eax
	addq	$64, %rsp
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_10:
	callq	___stack_chk_fail
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__const
	.p2align	4                               ## @__const.amdgpu_uvd_ring_parse_cs.buf_sizes
l___const.amdgpu_uvd_ring_parse_cs.buf_sizes:
	.long	2048                            ## 0x800
	.long	4294967295                      ## 0xffffffff
	.long	4294967295                      ## 0xffffffff
	.long	2048                            ## 0x800
	.long	4294967295                      ## 0xffffffff

	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"UVD IB length (%d) not 16 dwords aligned!\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_amdgpu_uvd_cs_pass1,4,2        ## @amdgpu_uvd_cs_pass1
	.comm	_amdgpu_uvd_cs_pass2,4,2        ## @amdgpu_uvd_cs_pass2
L_.str.1:                               ## @.str.1
	.asciz	"UVD-IBs need a msg command!\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_uvd_ring_parse_cs       ; -- Begin function amdgpu_uvd_ring_parse_cs
	.p2align	2
_amdgpu_uvd_ring_parse_cs:              ; @amdgpu_uvd_ring_parse_cs
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #128
	.cfi_def_cfa_offset 128
	stp	x22, x21, [sp, #80]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #96]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #112]            ; 16-byte Folded Spill
	add	x29, sp, #112
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x8, ___stack_chk_guard@GOTPAGE
Lloh1:
	ldr	x8, [x8, ___stack_chk_guard@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	stur	x8, [x29, #-40]
	str	xzr, [sp, #32]
Lloh3:
	adrp	x8, l___const.amdgpu_uvd_ring_parse_cs.buf_sizes@PAGE
Lloh4:
	add	x8, x8, l___const.amdgpu_uvd_ring_parse_cs.buf_sizes@PAGEOFF
	ldr	q0, [x8]
	str	q0, [sp, #48]
	ldr	w8, [x8, #16]
	str	w8, [sp, #64]
	ldr	x8, [x0, #8]
	ldr	x9, [x8, #8]
	str	xzr, [x8]
	mov	w8, #12
	madd	x21, x1, x8, x9
	ldr	w0, [x21, #4]
	bl	_amdgpu_sa_bo_gpu_addr
	str	w0, [x21, #8]
	ldr	w8, [x21]
	tst	w8, #0xf
	b.eq	LBB0_3
; %bb.1:
	str	x8, [sp]
Lloh5:
	adrp	x0, l_.str@PAGE
Lloh6:
	add	x0, x0, l_.str@PAGEOFF
LBB0_2:
	bl	_DRM_ERROR
Lloh7:
	adrp	x8, _EINVAL@GOTPAGE
Lloh8:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_8
LBB0_3:
	str	x19, [sp, #40]
	add	x8, sp, #48
	stp	x8, x20, [sp, #16]
	ldr	x8, [x19]
	ldr	w8, [x8]
	cbz	w8, LBB0_7
LBB0_4:
Lloh10:
	adrp	x8, _amdgpu_uvd_cs_pass2@GOTPAGE
Lloh11:
	ldr	x8, [x8, _amdgpu_uvd_cs_pass2@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
	add	x0, sp, #16
	bl	_amdgpu_uvd_cs_packets
	cbnz	w0, LBB0_8
; %bb.5:
	ldr	w8, [sp, #32]
	cbz	w8, LBB0_10
; %bb.6:
	mov	w0, #0
	b	LBB0_8
LBB0_7:
Lloh13:
	adrp	x8, _amdgpu_uvd_cs_pass1@GOTPAGE
Lloh14:
	ldr	x8, [x8, _amdgpu_uvd_cs_pass1@GOTPAGEOFF]
Lloh15:
	ldr	w1, [x8]
	add	x0, sp, #16
	bl	_amdgpu_uvd_cs_packets
	cbz	w0, LBB0_4
LBB0_8:
	ldur	x8, [x29, #-40]
Lloh16:
	adrp	x9, ___stack_chk_guard@GOTPAGE
Lloh17:
	ldr	x9, [x9, ___stack_chk_guard@GOTPAGEOFF]
Lloh18:
	ldr	x9, [x9]
	cmp	x9, x8
	b.ne	LBB0_11
; %bb.9:
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	add	sp, sp, #128
	ret
LBB0_10:
Lloh19:
	adrp	x0, l_.str.1@PAGE
Lloh20:
	add	x0, x0, l_.str.1@PAGEOFF
	b	LBB0_2
LBB0_11:
	bl	___stack_chk_fail
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpAdd	Lloh19, Lloh20
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__const
	.p2align	2                               ; @__const.amdgpu_uvd_ring_parse_cs.buf_sizes
l___const.amdgpu_uvd_ring_parse_cs.buf_sizes:
	.long	2048                            ; 0x800
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	2048                            ; 0x800
	.long	4294967295                      ; 0xffffffff

	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"UVD IB length (%d) not 16 dwords aligned!\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_amdgpu_uvd_cs_pass1,4,2        ; @amdgpu_uvd_cs_pass1
	.comm	_amdgpu_uvd_cs_pass2,4,2        ; @amdgpu_uvd_cs_pass2
l_.str.1:                               ; @.str.1
	.asciz	"UVD-IBs need a msg command!\n"

.subsections_via_symbols
