	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v7_0_ring_emit_hdp_flush
_gfx_v7_0_ring_emit_hdp_flush:          ## @gfx_v7_0_ring_emit_hdp_flush
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	8(%rdi), %rax
	movq	(%rax), %rax
	movq	_AMDGPU_RING_TYPE_COMPUTE@GOTPCREL(%rip), %rcx
	xorl	%r15d, %r15d
	cmpq	(%rcx), %rax
	setne	%al
	jne	LBB0_6
## %bb.1:
	movl	(%r12), %ecx
	cmpl	$2, %ecx
	je	LBB0_5
## %bb.2:
	cmpl	$1, %ecx
	jne	LBB0_8
## %bb.3:
	movq	_GPU_HDP_FLUSH_DONE__CP2_MASK@GOTPCREL(%rip), %rcx
	jmp	LBB0_4
LBB0_6:
	movq	_GPU_HDP_FLUSH_DONE__CP0_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r14d
	jmp	LBB0_7
LBB0_5:
	movq	_GPU_HDP_FLUSH_DONE__CP6_MASK@GOTPCREL(%rip), %rcx
LBB0_4:
	movl	(%rcx), %r14d
	movb	4(%r12), %cl
	shll	%cl, %r14d
LBB0_7:
	movb	%al, %r15b
	movq	_PACKET3_WAIT_REG_MEM@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$5, %esi
	callq	_PACKET3
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	$1, %edi
	callq	_WAIT_REG_MEM_OPERATION
	movl	%eax, %ebx
	movl	$3, %edi
	callq	_WAIT_REG_MEM_FUNCTION
	orl	%eax, %ebx
	movl	%r15d, %edi
	callq	_WAIT_REG_MEM_ENGINE
	orl	%eax, %ebx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_amdgpu_ring_write
	movq	_mmGPU_HDP_FLUSH_REQ@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_amdgpu_ring_write
	movq	_mmGPU_HDP_FLUSH_DONE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_amdgpu_ring_write
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_amdgpu_ring_write
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_amdgpu_ring_write
	movq	%r12, %rdi
	movl	$32, %esi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_write              ## TAILCALL
LBB0_8:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_RING_TYPE_COMPUTE,8,3   ## @AMDGPU_RING_TYPE_COMPUTE
	.comm	_GPU_HDP_FLUSH_DONE__CP2_MASK,4,2 ## @GPU_HDP_FLUSH_DONE__CP2_MASK
	.comm	_GPU_HDP_FLUSH_DONE__CP6_MASK,4,2 ## @GPU_HDP_FLUSH_DONE__CP6_MASK
	.comm	_GPU_HDP_FLUSH_DONE__CP0_MASK,4,2 ## @GPU_HDP_FLUSH_DONE__CP0_MASK
	.comm	_PACKET3_WAIT_REG_MEM,4,2       ## @PACKET3_WAIT_REG_MEM
	.comm	_mmGPU_HDP_FLUSH_REQ,4,2        ## @mmGPU_HDP_FLUSH_REQ
	.comm	_mmGPU_HDP_FLUSH_DONE,4,2       ## @mmGPU_HDP_FLUSH_DONE
	.no_dead_strip	_gfx_v7_0_ring_emit_hdp_flush
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v7_0_ring_emit_hdp_flush
_gfx_v7_0_ring_emit_hdp_flush:          ; @gfx_v7_0_ring_emit_hdp_flush
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x8, [x0, #8]
	ldr	x8, [x8]
Lloh0:
	adrp	x9, _AMDGPU_RING_TYPE_COMPUTE@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMDGPU_RING_TYPE_COMPUTE@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	cset	w21, ne
	b.ne	LBB0_4
; %bb.1:
	ldr	w8, [x19]
	cmp	w8, #2
	b.eq	LBB0_5
; %bb.2:
	cmp	w8, #1
	b.ne	LBB0_8
; %bb.3:
Lloh3:
	adrp	x8, _GPU_HDP_FLUSH_DONE__CP2_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _GPU_HDP_FLUSH_DONE__CP2_MASK@GOTPAGEOFF]
	b	LBB0_6
LBB0_4:
Lloh5:
	adrp	x8, _GPU_HDP_FLUSH_DONE__CP0_MASK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _GPU_HDP_FLUSH_DONE__CP0_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w20, [x8]
	b	LBB0_7
LBB0_5:
Lloh8:
	adrp	x8, _GPU_HDP_FLUSH_DONE__CP6_MASK@GOTPAGE
Lloh9:
	ldr	x8, [x8, _GPU_HDP_FLUSH_DONE__CP6_MASK@GOTPAGEOFF]
LBB0_6:
	ldr	w8, [x8]
	ldr	w9, [x19, #4]
	lsl	w20, w8, w9
LBB0_7:
Lloh10:
	adrp	x8, _PACKET3_WAIT_REG_MEM@GOTPAGE
Lloh11:
	ldr	x8, [x8, _PACKET3_WAIT_REG_MEM@GOTPAGEOFF]
Lloh12:
	ldr	w0, [x8]
	mov	w1, #5
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	w0, #1
	bl	_WAIT_REG_MEM_OPERATION
	mov	x22, x0
	mov	w0, #3
	bl	_WAIT_REG_MEM_FUNCTION
	orr	w22, w0, w22
	mov	x0, x21
	bl	_WAIT_REG_MEM_ENGINE
	orr	w1, w22, w0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh13:
	adrp	x8, _mmGPU_HDP_FLUSH_REQ@GOTPAGE
Lloh14:
	ldr	x8, [x8, _mmGPU_HDP_FLUSH_REQ@GOTPAGEOFF]
Lloh15:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh16:
	adrp	x8, _mmGPU_HDP_FLUSH_DONE@GOTPAGE
Lloh17:
	ldr	x8, [x8, _mmGPU_HDP_FLUSH_DONE@GOTPAGEOFF]
Lloh18:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #32
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_amdgpu_ring_write
LBB0_8:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_RING_TYPE_COMPUTE,8,3   ; @AMDGPU_RING_TYPE_COMPUTE
	.comm	_GPU_HDP_FLUSH_DONE__CP2_MASK,4,2 ; @GPU_HDP_FLUSH_DONE__CP2_MASK
	.comm	_GPU_HDP_FLUSH_DONE__CP6_MASK,4,2 ; @GPU_HDP_FLUSH_DONE__CP6_MASK
	.comm	_GPU_HDP_FLUSH_DONE__CP0_MASK,4,2 ; @GPU_HDP_FLUSH_DONE__CP0_MASK
	.comm	_PACKET3_WAIT_REG_MEM,4,2       ; @PACKET3_WAIT_REG_MEM
	.comm	_mmGPU_HDP_FLUSH_REQ,4,2        ; @mmGPU_HDP_FLUSH_REQ
	.comm	_mmGPU_HDP_FLUSH_DONE,4,2       ; @mmGPU_HDP_FLUSH_DONE
	.no_dead_strip	_gfx_v7_0_ring_emit_hdp_flush
.subsections_via_symbols
