	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_get_vtiming_tables_addr
_radeon_get_vtiming_tables_addr:        ## @radeon_get_vtiming_tables_addr
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
                                        ## kill: def $edi killed $edi def $rdi
	movq	_RADEON_VCODE_TABLE_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	andl	%edi, %edx
	movq	_RADEON_VCODE_TABLE_SEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarl	%cl, %edx
	cmpl	$2, %edx
	je	LBB0_5
## %bb.1:
	cmpl	$1, %edx
	je	LBB0_4
## %bb.2:
	xorl	%eax, %eax
	testl	%edx, %edx
	jne	LBB0_7
## %bb.3:
	movq	_RADEON_MAX_UV_ADR_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %edi
	movq	_RADEON_MAX_UV_ADR_SHIFT@GOTPCREL(%rip), %rax
	jmp	LBB0_6
LBB0_5:
	movq	_RADEON_TABLE3_TOP_ADR_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %edi
	movq	_RADEON_TABLE3_TOP_ADR_SHIFT@GOTPCREL(%rip), %rax
	jmp	LBB0_6
LBB0_4:
	movq	_RADEON_TABLE1_BOT_ADR_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %edi
	movq	_RADEON_TABLE1_BOT_ADR_SHIFT@GOTPCREL(%rip), %rax
LBB0_6:
	movb	(%rax), %cl
	sarl	%cl, %edi
	leal	(%rdi,%rdi), %eax
	incl	%eax
LBB0_7:
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_VCODE_TABLE_SEL_MASK,4,2 ## @RADEON_VCODE_TABLE_SEL_MASK
	.comm	_RADEON_VCODE_TABLE_SEL_SHIFT,4,2 ## @RADEON_VCODE_TABLE_SEL_SHIFT
	.comm	_RADEON_MAX_UV_ADR_MASK,4,2     ## @RADEON_MAX_UV_ADR_MASK
	.comm	_RADEON_MAX_UV_ADR_SHIFT,4,2    ## @RADEON_MAX_UV_ADR_SHIFT
	.comm	_RADEON_TABLE1_BOT_ADR_MASK,4,2 ## @RADEON_TABLE1_BOT_ADR_MASK
	.comm	_RADEON_TABLE1_BOT_ADR_SHIFT,4,2 ## @RADEON_TABLE1_BOT_ADR_SHIFT
	.comm	_RADEON_TABLE3_TOP_ADR_MASK,4,2 ## @RADEON_TABLE3_TOP_ADR_MASK
	.comm	_RADEON_TABLE3_TOP_ADR_SHIFT,4,2 ## @RADEON_TABLE3_TOP_ADR_SHIFT
	.no_dead_strip	_radeon_get_vtiming_tables_addr
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_get_vtiming_tables_addr
_radeon_get_vtiming_tables_addr:        ; @radeon_get_vtiming_tables_addr
	.cfi_startproc
; %bb.0:
Lloh0:
	adrp	x8, _RADEON_VCODE_TABLE_SEL_MASK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_VCODE_TABLE_SEL_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh3:
	adrp	x9, _RADEON_VCODE_TABLE_SEL_SHIFT@GOTPAGE
Lloh4:
	ldr	x9, [x9, _RADEON_VCODE_TABLE_SEL_SHIFT@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	asr	w8, w8, w9
	cmp	w8, #2
	b.eq	LBB0_4
; %bb.1:
	cmp	w8, #1
	b.eq	LBB0_5
; %bb.2:
	cbnz	w8, LBB0_7
; %bb.3:
Lloh6:
	adrp	x8, _RADEON_MAX_UV_ADR_MASK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_MAX_UV_ADR_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh9:
	adrp	x9, _RADEON_MAX_UV_ADR_SHIFT@GOTPAGE
Lloh10:
	ldr	x9, [x9, _RADEON_MAX_UV_ADR_SHIFT@GOTPAGEOFF]
	b	LBB0_6
LBB0_4:
Lloh11:
	adrp	x8, _RADEON_TABLE3_TOP_ADR_MASK@GOTPAGE
Lloh12:
	ldr	x8, [x8, _RADEON_TABLE3_TOP_ADR_MASK@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh14:
	adrp	x9, _RADEON_TABLE3_TOP_ADR_SHIFT@GOTPAGE
Lloh15:
	ldr	x9, [x9, _RADEON_TABLE3_TOP_ADR_SHIFT@GOTPAGEOFF]
	b	LBB0_6
LBB0_5:
Lloh16:
	adrp	x8, _RADEON_TABLE1_BOT_ADR_MASK@GOTPAGE
Lloh17:
	ldr	x8, [x8, _RADEON_TABLE1_BOT_ADR_MASK@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh19:
	adrp	x9, _RADEON_TABLE1_BOT_ADR_SHIFT@GOTPAGE
Lloh20:
	ldr	x9, [x9, _RADEON_TABLE1_BOT_ADR_SHIFT@GOTPAGEOFF]
LBB0_6:
	ldr	w9, [x9]
	asr	w8, w8, w9
	mov	w0, #1
	bfi	w0, w8, #1, #31
	ret
LBB0_7:
	mov	w0, #0
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_VCODE_TABLE_SEL_MASK,4,2 ; @RADEON_VCODE_TABLE_SEL_MASK
	.comm	_RADEON_VCODE_TABLE_SEL_SHIFT,4,2 ; @RADEON_VCODE_TABLE_SEL_SHIFT
	.comm	_RADEON_MAX_UV_ADR_MASK,4,2     ; @RADEON_MAX_UV_ADR_MASK
	.comm	_RADEON_MAX_UV_ADR_SHIFT,4,2    ; @RADEON_MAX_UV_ADR_SHIFT
	.comm	_RADEON_TABLE1_BOT_ADR_MASK,4,2 ; @RADEON_TABLE1_BOT_ADR_MASK
	.comm	_RADEON_TABLE1_BOT_ADR_SHIFT,4,2 ; @RADEON_TABLE1_BOT_ADR_SHIFT
	.comm	_RADEON_TABLE3_TOP_ADR_MASK,4,2 ; @RADEON_TABLE3_TOP_ADR_MASK
	.comm	_RADEON_TABLE3_TOP_ADR_SHIFT,4,2 ; @RADEON_TABLE3_TOP_ADR_SHIFT
	.no_dead_strip	_radeon_get_vtiming_tables_addr
.subsections_via_symbols
