	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function smu_v12_0_powergate_vcn
_smu_v12_0_powergate_vcn:               ## @smu_v12_0_powergate_vcn
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	(%rdi), %rax
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, (%rax)
	je	LBB0_5
## %bb.1:
	testl	%esi, %esi
	jne	LBB0_2
## %bb.3:
	movq	_SMU_MSG_PowerUpVcn@GOTPCREL(%rip), %rax
	jmp	LBB0_4
LBB0_5:
	xorl	%eax, %eax
	popq	%rbp
	retq
LBB0_2:
	movq	_SMU_MSG_PowerDownVcn@GOTPCREL(%rip), %rax
LBB0_4:
	movl	(%rax), %esi
	popq	%rbp
	jmp	_smu_send_smc_msg               ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_SMU_MSG_PowerDownVcn,4,2       ## @SMU_MSG_PowerDownVcn
	.comm	_SMU_MSG_PowerUpVcn,4,2         ## @SMU_MSG_PowerUpVcn
	.no_dead_strip	_smu_v12_0_powergate_vcn
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function smu_v12_0_powergate_vcn
_smu_v12_0_powergate_vcn:               ; @smu_v12_0_powergate_vcn
	.cfi_startproc
; %bb.0:
	ldr	x8, [x0]
	ldr	w8, [x8]
Lloh0:
	adrp	x9, _AMD_IS_APU@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_IS_APU@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
Lloh3:
	adrp	x8, _SMU_MSG_PowerUpVcn@GOTPAGE
Lloh4:
	ldr	x8, [x8, _SMU_MSG_PowerUpVcn@GOTPAGEOFF]
Lloh5:
	adrp	x9, _SMU_MSG_PowerDownVcn@GOTPAGE
Lloh6:
	ldr	x9, [x9, _SMU_MSG_PowerDownVcn@GOTPAGEOFF]
	cmp	w1, #0
	csel	x8, x8, x9, eq
	ldr	w1, [x8]
	b	_smu_send_smc_msg
LBB0_2:
	mov	w0, #0
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_SMU_MSG_PowerDownVcn,4,2       ; @SMU_MSG_PowerDownVcn
	.comm	_SMU_MSG_PowerUpVcn,4,2         ; @SMU_MSG_PowerUpVcn
	.no_dead_strip	_smu_v12_0_powergate_vcn
.subsections_via_symbols
