	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function si_pcie_gen3_enable
_si_pcie_gen3_enable:                   ## @si_pcie_gen3_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	8(%rdi), %rax
	movq	(%rax), %rdi
	movq	(%rdi), %r14
	callq	_pci_is_root_bus
	testq	%rax, %rax
	jne	LBB0_31
## %bb.1:
	movq	_amdgpu_pcie_gen2@GOTPCREL(%rip), %rax
	cmpq	$0, (%rax)
	je	LBB0_31
## %bb.2:
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r15)
	je	LBB0_3
LBB0_31:
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_3:
	movq	_CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2@GOTPCREL(%rip), %rcx
	movq	_CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3@GOTPCREL(%rip), %r12
	movl	(%r12), %eax
	orl	(%rcx), %eax
	testl	%eax, 16(%r15)
	je	LBB0_31
## %bb.4:
	movq	_PCIE_LC_SPEED_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PCIE_PORT
	movl	%eax, %r13d
	movq	_LC_CURRENT_DATA_RATE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	andl	%r13d, %ebx
	movq	_LC_CURRENT_DATA_RATE_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarl	%cl, %ebx
	movl	16(%r15), %eax
	testl	%eax, (%r12)
	je	LBB0_7
## %bb.5:
	cmpl	$2, %ebx
	jne	LBB0_6
## %bb.32:
	leaq	L_.str(%rip), %rdi
	jmp	LBB0_33
LBB0_7:
	movq	_CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_11
## %bb.8:
	cmpl	$1, %ebx
	jne	LBB0_9
## %bb.34:
	leaq	L_.str.2(%rip), %rdi
LBB0_33:
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_DRM_INFO                       ## TAILCALL
LBB0_6:
	leaq	L_.str.1(%rip), %rdi
	jmp	LBB0_10
LBB0_9:
	leaq	L_.str.3(%rip), %rdi
LBB0_10:
	callq	_DRM_INFO
LBB0_11:
	movl	%r13d, -76(%rbp)                ## 4-byte Spill
	movq	%r14, %rdi
	callq	_pci_pcie_cap
	testl	%eax, %eax
	je	LBB0_31
## %bb.12:
	movl	%eax, %r13d
	movq	8(%r15), %rdi
	callq	_pci_pcie_cap
	movl	%eax, %r12d
	movq	_CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3@GOTPCREL(%rip), %rax
	testl	%r12d, %r12d
	je	LBB0_31
## %bb.13:
	movl	(%rax), %eax
	testl	%eax, 16(%r15)
	je	LBB0_15
## %bb.14:
	cmpl	$2, %ebx
	je	LBB0_15
## %bb.16:
	movslq	%r13d, %rbx
	movq	_PCI_EXP_LNKCTL@GOTPCREL(%rip), %r13
	movq	(%r13), %rsi
	addq	%rbx, %rsi
	leaq	-52(%rbp), %rdx
	movq	%r14, %rdi
	callq	_pci_read_config_word
	movq	8(%r15), %rdi
	movslq	%r12d, %r12
	movq	(%r13), %rsi
	addq	%r12, %rsi
	leaq	-48(%rbp), %rdx
	callq	_pci_read_config_word
	movq	%r14, %rdi
	movq	_PCI_EXP_LNKCTL_HAWD@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	orl	-52(%rbp), %edx
	movl	%edx, -44(%rbp)
	movq	(%r13), %rsi
	movq	%rbx, -96(%rbp)                 ## 8-byte Spill
	addq	%rbx, %rsi
	movq	%rdi, -72(%rbp)                 ## 8-byte Spill
	callq	_pci_write_config_word
	movl	(%r14), %edx
	orl	-48(%rbp), %edx
	movl	%edx, -44(%rbp)
	movq	8(%r15), %rdi
	movq	(%r13), %rsi
	addq	%r12, %rsi
	callq	_pci_write_config_word
	movq	_PCIE_LC_STATUS1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PCIE
	movq	_LC_DETECTED_LINK_WIDTH_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r13d
	andl	%eax, %r13d
	movq	_LC_DETECTED_LINK_WIDTH_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %r13d
	movq	_LC_OPERATING_LINK_WIDTH_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_LC_OPERATING_LINK_WIDTH_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	cmpl	%r13d, %eax
	jge	LBB0_19
## %bb.17:
	movq	_PCIE_LC_LINK_WIDTH_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_RENEGOTIATION_SUPPORT@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_19
## %bb.18:
	movq	_LC_LINK_WIDTH_MASK@GOTPCREL(%rip), %rcx
	movq	_LC_UPCONFIGURE_DIS@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	notl	%edx
	movq	_LC_LINK_WIDTH_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r13d
	andl	%edx, %eax
	orl	%eax, %r13d
	movq	_LC_UPCONFIGURE_SUPPORT@GOTPCREL(%rip), %rax
	movq	_LC_RENEGOTIATE_EN@GOTPCREL(%rip), %rcx
	orl	(%rax), %r13d
	orl	(%rcx), %r13d
	movq	_LC_RECONFIG_NOW@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	movl	(%rbx), %edi
	movl	%r13d, %esi
	callq	_WREG32_PCIE_PORT
LBB0_19:
	movl	$10, %ebx
	movq	-72(%rbp), %r14                 ## 8-byte Reload
	movq	%r12, -64(%rbp)                 ## 8-byte Spill
	.p2align	4, 0x90
LBB0_20:                                ## =>This Inner Loop Header: Depth=1
	movq	8(%r15), %rdi
	movq	_PCI_EXP_DEVSTA@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	%r12, %rsi
	leaq	-44(%rbp), %rdx
	callq	_pci_read_config_word
	movq	_PCI_EXP_DEVSTA_TRPND@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, -44(%rbp)
	jne	LBB0_22
## %bb.21:                              ##   in Loop: Header=BB0_20 Depth=1
	movl	%ebx, -80(%rbp)                 ## 4-byte Spill
	movq	_PCI_EXP_LNKCTL@GOTPCREL(%rip), %r13
	movq	(%r13), %rsi
	movq	-96(%rbp), %r12                 ## 8-byte Reload
	addq	%r12, %rsi
	movq	%r14, %rdi
	leaq	-52(%rbp), %rdx
	callq	_pci_read_config_word
	movq	8(%r15), %rdi
	movq	(%r13), %rsi
	addq	-64(%rbp), %rsi                 ## 8-byte Folded Reload
	leaq	-48(%rbp), %rdx
	callq	_pci_read_config_word
	movq	_PCI_EXP_LNKCTL2@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rsi
	addq	%r12, %rsi
	movq	%r14, %rdi
	leaq	-88(%rbp), %rdx
	callq	_pci_read_config_word
	movq	8(%r15), %rdi
	movq	(%rbx), %rsi
	addq	-64(%rbp), %rsi                 ## 8-byte Folded Reload
	leaq	-84(%rbp), %rdx
	callq	_pci_read_config_word
	movq	_PCIE_LC_CNTL4@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	%rax, %rbx
	callq	_RREG32_PCIE_PORT
	movq	_LC_SET_QUIESCE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PCIE_PORT
	movl	(%rbx), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_REDO_EQ@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PCIE_PORT
	movl	$100, %edi
	callq	_mdelay
	movq	(%r13), %rsi
	addq	%r12, %rsi
	movq	%r14, %rdi
	leaq	-44(%rbp), %rbx
	movq	%rbx, %rdx
	callq	_pci_read_config_word
	movl	-44(%rbp), %eax
	movl	-52(%rbp), %edx
	xorl	%eax, %edx
	movq	_PCI_EXP_LNKCTL_HAWD@GOTPCREL(%rip), %r14
	andl	(%r14), %edx
	xorl	%eax, %edx
	movl	%edx, -44(%rbp)
	movq	(%r13), %rsi
	addq	%r12, %rsi
	movq	-72(%rbp), %rdi                 ## 8-byte Reload
	callq	_pci_write_config_word
	movq	8(%r15), %rdi
	movq	(%r13), %rsi
	addq	-64(%rbp), %rsi                 ## 8-byte Folded Reload
	movq	%rbx, %rdx
	callq	_pci_read_config_word
	movl	-44(%rbp), %eax
	movl	-48(%rbp), %edx
	xorl	%eax, %edx
	andl	(%r14), %edx
	movq	-72(%rbp), %r14                 ## 8-byte Reload
	xorl	%eax, %edx
	movl	%edx, -44(%rbp)
	movq	8(%r15), %rdi
	movq	(%r13), %rsi
	movl	-80(%rbp), %ebx                 ## 4-byte Reload
	addq	-64(%rbp), %rsi                 ## 8-byte Folded Reload
	callq	_pci_write_config_word
	movq	_PCI_EXP_LNKCTL2@GOTPCREL(%rip), %r13
	movq	(%r13), %rsi
	addq	%r12, %rsi
	movq	%r14, %rdi
	leaq	-44(%rbp), %rdx
	callq	_pci_read_config_word
	movl	-44(%rbp), %eax
	movl	$-3601, %ecx                    ## imm = 0xF1EF
	andl	%ecx, %eax
	movl	-88(%rbp), %edx
	movl	$3600, %ecx                     ## imm = 0xE10
	andl	%ecx, %edx
	orl	%eax, %edx
	movl	%edx, -44(%rbp)
	movq	(%r13), %rsi
	addq	%r12, %rsi
	movq	-64(%rbp), %r12                 ## 8-byte Reload
	movq	%r14, %rdi
	callq	_pci_write_config_word
	movq	8(%r15), %rdi
	movq	(%r13), %rsi
	addq	%r12, %rsi
	leaq	-44(%rbp), %rdx
	callq	_pci_read_config_word
	movl	-44(%rbp), %eax
	movl	$-3601, %ecx                    ## imm = 0xF1EF
	andl	%ecx, %eax
	movl	-84(%rbp), %edx
	movl	$3600, %ecx                     ## imm = 0xE10
	andl	%ecx, %edx
	orl	%eax, %edx
	movl	%edx, -44(%rbp)
	movq	8(%r15), %rdi
	movq	(%r13), %rsi
	addq	%r12, %rsi
	callq	_pci_write_config_word
	movq	_PCIE_LC_CNTL4@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_SET_QUIESCE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r13), %edi
	callq	_WREG32_PCIE_PORT
	decl	%ebx
	jne	LBB0_20
	jmp	LBB0_22
LBB0_15:
	movslq	%r12d, %r12
LBB0_22:
	movq	_LC_FORCE_EN_SW_SPEED_CHANGE@GOTPCREL(%rip), %rax
	movl	-76(%rbp), %ecx                 ## 4-byte Reload
	orl	(%rax), %ecx
	movq	_LC_FORCE_DIS_HW_SPEED_CHANGE@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_LC_FORCE_DIS_SW_SPEED_CHANGE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	%ecx, %esi
	movq	_PCIE_LC_SPEED_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32_PCIE_PORT
	movq	8(%r15), %rdi
	movq	_PCI_EXP_LNKCTL2@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rsi
	addq	%r12, %rsi
	leaq	-44(%rbp), %rdx
	callq	_pci_read_config_word
	movl	-44(%rbp), %edx
	andl	$-16, %edx
	movl	16(%r15), %eax
	movq	_CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_24
## %bb.23:
	orl	$3, %edx
	jmp	LBB0_27
LBB0_24:
	movq	_CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_26
## %bb.25:
	orl	$2, %edx
	jmp	LBB0_27
LBB0_26:
	orl	$1, %edx
LBB0_27:
	movl	%edx, -44(%rbp)
	movq	8(%r15), %rdi
	addq	(%rbx), %r12
	movq	%r12, %rsi
	callq	_pci_write_config_word
	movq	_PCIE_LC_SPEED_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_INITIATE_LINK_SPEED_CHANGE@GOTPCREL(%rip), %r14
	orl	(%r14), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PCIE_PORT
	cmpl	$0, 4(%r15)
	jle	LBB0_31
## %bb.28:
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_29:                                ## =>This Inner Loop Header: Depth=1
	movq	_PCIE_LC_SPEED_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PCIE_PORT
	testl	%eax, (%r14)
	je	LBB0_31
## %bb.30:                              ##   in Loop: Header=BB0_29 Depth=1
	movl	$1, %edi
	callq	_udelay
	incl	%ebx
	cmpl	4(%r15), %ebx
	jl	LBB0_29
	jmp	LBB0_31
	.cfi_endproc
                                        ## -- End function
	.comm	_amdgpu_pcie_gen2,8,3           ## @amdgpu_pcie_gen2
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2,4,2 ## @CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2
	.comm	_CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3,4,2 ## @CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3
	.comm	_PCIE_LC_SPEED_CNTL,4,2         ## @PCIE_LC_SPEED_CNTL
	.comm	_LC_CURRENT_DATA_RATE_MASK,4,2  ## @LC_CURRENT_DATA_RATE_MASK
	.comm	_LC_CURRENT_DATA_RATE_SHIFT,4,2 ## @LC_CURRENT_DATA_RATE_SHIFT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"PCIE gen 3 link speeds already enabled\n"

L_.str.1:                               ## @.str.1
	.asciz	"enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"

L_.str.2:                               ## @.str.2
	.asciz	"PCIE gen 2 link speeds already enabled\n"

L_.str.3:                               ## @.str.3
	.asciz	"enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"

	.comm	_PCI_EXP_LNKCTL,8,3             ## @PCI_EXP_LNKCTL
	.comm	_PCI_EXP_LNKCTL_HAWD,4,2        ## @PCI_EXP_LNKCTL_HAWD
	.comm	_PCIE_LC_STATUS1,4,2            ## @PCIE_LC_STATUS1
	.comm	_LC_DETECTED_LINK_WIDTH_MASK,4,2 ## @LC_DETECTED_LINK_WIDTH_MASK
	.comm	_LC_DETECTED_LINK_WIDTH_SHIFT,4,2 ## @LC_DETECTED_LINK_WIDTH_SHIFT
	.comm	_LC_OPERATING_LINK_WIDTH_MASK,4,2 ## @LC_OPERATING_LINK_WIDTH_MASK
	.comm	_LC_OPERATING_LINK_WIDTH_SHIFT,4,2 ## @LC_OPERATING_LINK_WIDTH_SHIFT
	.comm	_PCIE_LC_LINK_WIDTH_CNTL,4,2    ## @PCIE_LC_LINK_WIDTH_CNTL
	.comm	_LC_RENEGOTIATION_SUPPORT,4,2   ## @LC_RENEGOTIATION_SUPPORT
	.comm	_LC_LINK_WIDTH_MASK,4,2         ## @LC_LINK_WIDTH_MASK
	.comm	_LC_UPCONFIGURE_DIS,4,2         ## @LC_UPCONFIGURE_DIS
	.comm	_LC_LINK_WIDTH_SHIFT,4,2        ## @LC_LINK_WIDTH_SHIFT
	.comm	_LC_UPCONFIGURE_SUPPORT,4,2     ## @LC_UPCONFIGURE_SUPPORT
	.comm	_LC_RENEGOTIATE_EN,4,2          ## @LC_RENEGOTIATE_EN
	.comm	_LC_RECONFIG_NOW,4,2            ## @LC_RECONFIG_NOW
	.comm	_PCI_EXP_DEVSTA,8,3             ## @PCI_EXP_DEVSTA
	.comm	_PCI_EXP_DEVSTA_TRPND,4,2       ## @PCI_EXP_DEVSTA_TRPND
	.comm	_PCI_EXP_LNKCTL2,8,3            ## @PCI_EXP_LNKCTL2
	.comm	_PCIE_LC_CNTL4,4,2              ## @PCIE_LC_CNTL4
	.comm	_LC_SET_QUIESCE,4,2             ## @LC_SET_QUIESCE
	.comm	_LC_REDO_EQ,4,2                 ## @LC_REDO_EQ
	.comm	_LC_FORCE_EN_SW_SPEED_CHANGE,4,2 ## @LC_FORCE_EN_SW_SPEED_CHANGE
	.comm	_LC_FORCE_DIS_HW_SPEED_CHANGE,4,2 ## @LC_FORCE_DIS_HW_SPEED_CHANGE
	.comm	_LC_FORCE_DIS_SW_SPEED_CHANGE,4,2 ## @LC_FORCE_DIS_SW_SPEED_CHANGE
	.comm	_LC_INITIATE_LINK_SPEED_CHANGE,4,2 ## @LC_INITIATE_LINK_SPEED_CHANGE
	.no_dead_strip	_si_pcie_gen3_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function si_pcie_gen3_enable
_si_pcie_gen3_enable:                   ; @si_pcie_gen3_enable
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #128
	.cfi_def_cfa_offset 128
	stp	x28, x27, [sp, #32]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #48]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #64]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #80]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #96]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #112]            ; 16-byte Folded Spill
	add	x29, sp, #112
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	x8, [x0, #8]
	ldr	x0, [x8]
	ldr	x20, [x0]
	bl	_pci_is_root_bus
Lloh0:
	adrp	x8, _amdgpu_pcie_gen2@GOTPAGE
Lloh1:
	ldr	x8, [x8, _amdgpu_pcie_gen2@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	cmp	x0, #0
	ccmp	x8, #0, #4, eq
	b.eq	LBB0_2
; %bb.1:
	ldr	w8, [x19]
Lloh3:
	adrp	x9, _AMD_IS_APU@GOTPAGE
Lloh4:
	ldr	x9, [x9, _AMD_IS_APU@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_3
LBB0_2:
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	ret
LBB0_3:
	ldr	w8, [x19, #16]
Lloh6:
	adrp	x25, _CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2@GOTPAGE
Lloh7:
	ldr	x25, [x25, _CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2@GOTPAGEOFF]
	ldr	w9, [x25]
Lloh8:
	adrp	x26, _CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3@GOTPAGE
Lloh9:
	ldr	x26, [x26, _CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3@GOTPAGEOFF]
	ldr	w10, [x26]
	orr	w9, w10, w9
	tst	w9, w8
	b.eq	LBB0_2
; %bb.4:
Lloh10:
	adrp	x24, _PCIE_LC_SPEED_CNTL@GOTPAGE
Lloh11:
	ldr	x24, [x24, _PCIE_LC_SPEED_CNTL@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_RREG32_PCIE_PORT
	mov	x28, x0
Lloh12:
	adrp	x8, _LC_CURRENT_DATA_RATE_MASK@GOTPAGE
Lloh13:
	ldr	x8, [x8, _LC_CURRENT_DATA_RATE_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
Lloh15:
	adrp	x9, _LC_CURRENT_DATA_RATE_SHIFT@GOTPAGE
Lloh16:
	ldr	x9, [x9, _LC_CURRENT_DATA_RATE_SHIFT@GOTPAGEOFF]
	and	w8, w8, w0
Lloh17:
	ldr	w9, [x9]
	asr	w21, w8, w9
	ldr	w8, [x19, #16]
	ldr	w9, [x26]
	tst	w9, w8
	b.eq	LBB0_7
; %bb.5:
	cmp	w21, #2
	b.ne	LBB0_11
; %bb.6:
Lloh18:
	adrp	x0, l_.str@PAGE
Lloh19:
	add	x0, x0, l_.str@PAGEOFF
	b	LBB0_10
LBB0_7:
	ldr	w9, [x25]
	tst	w9, w8
	b.eq	LBB0_14
; %bb.8:
	cmp	w21, #1
	b.ne	LBB0_12
; %bb.9:
Lloh20:
	adrp	x0, l_.str.2@PAGE
Lloh21:
	add	x0, x0, l_.str.2@PAGEOFF
LBB0_10:
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	b	_DRM_INFO
LBB0_11:
Lloh22:
	adrp	x0, l_.str.1@PAGE
Lloh23:
	add	x0, x0, l_.str.1@PAGEOFF
	b	LBB0_13
LBB0_12:
Lloh24:
	adrp	x0, l_.str.3@PAGE
Lloh25:
	add	x0, x0, l_.str.3@PAGEOFF
LBB0_13:
	bl	_DRM_INFO
LBB0_14:
	mov	x0, x20
	bl	_pci_pcie_cap
	cbz	w0, LBB0_2
; %bb.15:
	mov	x23, x0
	ldr	x0, [x19, #8]
	bl	_pci_pcie_cap
	cbz	w0, LBB0_2
; %bb.16:
	mov	x22, x0
	ldr	w8, [x19, #16]
	ldr	w9, [x26]
	tst	w9, w8
	b.eq	LBB0_25
; %bb.17:
	cmp	w21, #2
	b.eq	LBB0_25
; %bb.18:
	str	w28, [sp, #8]                   ; 4-byte Folded Spill
	sxtw	x23, w23
Lloh26:
	adrp	x24, _PCI_EXP_LNKCTL@GOTPAGE
Lloh27:
	ldr	x24, [x24, _PCI_EXP_LNKCTL@GOTPAGEOFF]
	ldr	x8, [x24]
	add	x1, x8, x23
	add	x2, sp, #24
	mov	x0, x20
	bl	_pci_read_config_word
	ldr	x0, [x19, #8]
                                        ; kill: def $w22 killed $w22 killed $x22 def $x22
	sxtw	x22, w22
	ldr	x8, [x24]
	add	x1, x8, x22
	add	x2, sp, #20
	bl	_pci_read_config_word
Lloh28:
	adrp	x21, _PCI_EXP_LNKCTL_HAWD@GOTPAGE
Lloh29:
	ldr	x21, [x21, _PCI_EXP_LNKCTL_HAWD@GOTPAGEOFF]
	ldr	w8, [sp, #24]
	ldr	w9, [x21]
	orr	w2, w9, w8
	str	w2, [sp, #28]
	ldr	x8, [x24]
	add	x1, x8, x23
	mov	x0, x20
	bl	_pci_write_config_word
	ldr	w8, [sp, #20]
	ldr	w9, [x21]
	orr	w2, w9, w8
	str	w2, [sp, #28]
	ldr	x0, [x19, #8]
	ldr	x8, [x24]
	add	x1, x8, x22
	bl	_pci_write_config_word
Lloh30:
	adrp	x8, _PCIE_LC_STATUS1@GOTPAGE
Lloh31:
	ldr	x8, [x8, _PCIE_LC_STATUS1@GOTPAGEOFF]
Lloh32:
	ldr	w0, [x8]
	bl	_RREG32_PCIE
Lloh33:
	adrp	x8, _LC_DETECTED_LINK_WIDTH_MASK@GOTPAGE
Lloh34:
	ldr	x8, [x8, _LC_DETECTED_LINK_WIDTH_MASK@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
Lloh36:
	adrp	x9, _LC_DETECTED_LINK_WIDTH_SHIFT@GOTPAGE
Lloh37:
	ldr	x9, [x9, _LC_DETECTED_LINK_WIDTH_SHIFT@GOTPAGEOFF]
	and	w8, w8, w0
Lloh38:
	ldr	w9, [x9]
	asr	w21, w8, w9
Lloh39:
	adrp	x8, _LC_OPERATING_LINK_WIDTH_MASK@GOTPAGE
Lloh40:
	ldr	x8, [x8, _LC_OPERATING_LINK_WIDTH_MASK@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh42:
	adrp	x9, _LC_OPERATING_LINK_WIDTH_SHIFT@GOTPAGE
Lloh43:
	ldr	x9, [x9, _LC_OPERATING_LINK_WIDTH_SHIFT@GOTPAGEOFF]
Lloh44:
	ldr	w9, [x9]
	asr	w8, w8, w9
	cmp	w8, w21
	b.ge	LBB0_21
; %bb.19:
Lloh45:
	adrp	x24, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGE
Lloh46:
	ldr	x24, [x24, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_RREG32_PCIE_PORT
Lloh47:
	adrp	x8, _LC_RENEGOTIATION_SUPPORT@GOTPAGE
Lloh48:
	ldr	x8, [x8, _LC_RENEGOTIATION_SUPPORT@GOTPAGEOFF]
Lloh49:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_21
; %bb.20:
Lloh50:
	adrp	x8, _LC_LINK_WIDTH_MASK@GOTPAGE
Lloh51:
	ldr	x8, [x8, _LC_LINK_WIDTH_MASK@GOTPAGEOFF]
Lloh52:
	ldr	w8, [x8]
Lloh53:
	adrp	x9, _LC_UPCONFIGURE_DIS@GOTPAGE
Lloh54:
	ldr	x9, [x9, _LC_UPCONFIGURE_DIS@GOTPAGEOFF]
Lloh55:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
Lloh56:
	adrp	x9, _LC_LINK_WIDTH_SHIFT@GOTPAGE
Lloh57:
	ldr	x9, [x9, _LC_LINK_WIDTH_SHIFT@GOTPAGEOFF]
Lloh58:
	ldr	w9, [x9]
	lsl	w9, w21, w9
Lloh59:
	adrp	x10, _LC_UPCONFIGURE_SUPPORT@GOTPAGE
Lloh60:
	ldr	x10, [x10, _LC_UPCONFIGURE_SUPPORT@GOTPAGEOFF]
Lloh61:
	ldr	w10, [x10]
Lloh62:
	adrp	x11, _LC_RENEGOTIATE_EN@GOTPAGE
Lloh63:
	ldr	x11, [x11, _LC_RENEGOTIATE_EN@GOTPAGEOFF]
Lloh64:
	ldr	w11, [x11]
Lloh65:
	adrp	x12, _LC_RECONFIG_NOW@GOTPAGE
Lloh66:
	ldr	x12, [x12, _LC_RECONFIG_NOW@GOTPAGEOFF]
Lloh67:
	ldr	w12, [x12]
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w1, w8, w12
	ldr	w0, [x24]
	bl	_WREG32_PCIE_PORT
LBB0_21:
	mov	w24, #10
Lloh68:
	adrp	x26, _PCIE_LC_CNTL4@GOTPAGE
Lloh69:
	ldr	x26, [x26, _PCIE_LC_CNTL4@GOTPAGEOFF]
Lloh70:
	adrp	x28, _PCI_EXP_LNKCTL2@GOTPAGE
Lloh71:
	ldr	x28, [x28, _PCI_EXP_LNKCTL2@GOTPAGEOFF]
Lloh72:
	adrp	x21, _LC_SET_QUIESCE@GOTPAGE
Lloh73:
	ldr	x21, [x21, _LC_SET_QUIESCE@GOTPAGEOFF]
LBB0_22:                                ; =>This Inner Loop Header: Depth=1
	ldr	x0, [x19, #8]
Lloh74:
	adrp	x8, _PCI_EXP_DEVSTA@GOTPAGE
Lloh75:
	ldr	x8, [x8, _PCI_EXP_DEVSTA@GOTPAGEOFF]
Lloh76:
	ldr	x8, [x8]
	add	x1, x8, x22
	add	x2, sp, #28
	bl	_pci_read_config_word
	ldr	w8, [sp, #28]
Lloh77:
	adrp	x9, _PCI_EXP_DEVSTA_TRPND@GOTPAGE
Lloh78:
	ldr	x9, [x9, _PCI_EXP_DEVSTA_TRPND@GOTPAGEOFF]
Lloh79:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_24
; %bb.23:                               ;   in Loop: Header=BB0_22 Depth=1
Lloh80:
	adrp	x27, _PCI_EXP_LNKCTL@GOTPAGE
Lloh81:
	ldr	x27, [x27, _PCI_EXP_LNKCTL@GOTPAGEOFF]
	ldr	x8, [x27]
	add	x1, x8, x23
	add	x2, sp, #24
	mov	x0, x20
	bl	_pci_read_config_word
	ldr	x0, [x19, #8]
	ldr	x8, [x27]
	add	x1, x8, x22
	add	x2, sp, #20
	bl	_pci_read_config_word
	ldr	x8, [x28]
	add	x1, x8, x23
	add	x2, sp, #16
	mov	x0, x20
	bl	_pci_read_config_word
	ldr	x0, [x19, #8]
	ldr	x8, [x28]
	add	x1, x8, x22
	add	x2, sp, #12
	bl	_pci_read_config_word
	ldr	w0, [x26]
	bl	_RREG32_PCIE_PORT
	ldr	w8, [x21]
	orr	w1, w8, w0
	ldr	w0, [x26]
	bl	_WREG32_PCIE_PORT
	ldr	w0, [x26]
	bl	_RREG32_PCIE_PORT
Lloh82:
	adrp	x8, _LC_REDO_EQ@GOTPAGE
Lloh83:
	ldr	x8, [x8, _LC_REDO_EQ@GOTPAGEOFF]
Lloh84:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x26]
	bl	_WREG32_PCIE_PORT
	mov	w0, #100
	bl	_mdelay
	ldr	x8, [x27]
	add	x1, x8, x23
	add	x2, sp, #28
	mov	x0, x20
	bl	_pci_read_config_word
Lloh85:
	adrp	x25, _PCI_EXP_LNKCTL_HAWD@GOTPAGE
Lloh86:
	ldr	x25, [x25, _PCI_EXP_LNKCTL_HAWD@GOTPAGEOFF]
	ldr	w8, [x25]
	ldp	w10, w9, [sp, #24]
	bic	w9, w9, w8
	and	w8, w10, w8
	orr	w2, w8, w9
	str	w2, [sp, #28]
	ldr	x8, [x27]
	add	x1, x8, x23
	mov	x0, x20
	bl	_pci_write_config_word
	ldr	x0, [x19, #8]
	ldr	x8, [x27]
	add	x1, x8, x22
	add	x2, sp, #28
	bl	_pci_read_config_word
	ldr	w8, [x25]
	ldr	w9, [sp, #28]
	bic	w9, w9, w8
	ldr	w10, [sp, #20]
	and	w8, w10, w8
	orr	w2, w8, w9
	str	w2, [sp, #28]
	ldr	x0, [x19, #8]
	ldr	x8, [x27]
	add	x1, x8, x22
	bl	_pci_write_config_word
	ldr	x8, [x28]
	add	x1, x8, x23
	add	x2, sp, #28
	mov	x0, x20
	bl	_pci_read_config_word
	ldr	w8, [sp, #28]
	mov	w25, #-3601
	and	w8, w8, w25
	ldr	w9, [sp, #16]
	mov	w27, #3600
	and	w9, w9, w27
	orr	w2, w9, w8
	str	w2, [sp, #28]
	ldr	x8, [x28]
	add	x1, x8, x23
	mov	x0, x20
	bl	_pci_write_config_word
	ldr	x0, [x19, #8]
	ldr	x8, [x28]
	add	x1, x8, x22
	add	x2, sp, #28
	bl	_pci_read_config_word
	ldr	w8, [sp, #28]
	and	w8, w8, w25
	ldr	w9, [sp, #12]
	and	w9, w9, w27
	orr	w2, w9, w8
	str	w2, [sp, #28]
	ldr	x0, [x19, #8]
	ldr	x8, [x28]
	add	x1, x8, x22
	bl	_pci_write_config_word
	ldr	w0, [x26]
	bl	_RREG32_PCIE_PORT
	ldr	w8, [x21]
	bic	w1, w0, w8
	ldr	w0, [x26]
	bl	_WREG32_PCIE_PORT
	subs	w24, w24, #1
	b.ne	LBB0_22
LBB0_24:
Lloh87:
	adrp	x24, _PCIE_LC_SPEED_CNTL@GOTPAGE
Lloh88:
	ldr	x24, [x24, _PCIE_LC_SPEED_CNTL@GOTPAGEOFF]
Lloh89:
	adrp	x25, _CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2@GOTPAGE
Lloh90:
	ldr	x25, [x25, _CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2@GOTPAGEOFF]
Lloh91:
	adrp	x26, _CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3@GOTPAGE
Lloh92:
	ldr	x26, [x26, _CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3@GOTPAGEOFF]
	ldr	w28, [sp, #8]                   ; 4-byte Folded Reload
	b	LBB0_26
LBB0_25:
	sxtw	x22, w22
LBB0_26:
Lloh93:
	adrp	x8, _LC_FORCE_EN_SW_SPEED_CHANGE@GOTPAGE
Lloh94:
	ldr	x8, [x8, _LC_FORCE_EN_SW_SPEED_CHANGE@GOTPAGEOFF]
Lloh95:
	ldr	w8, [x8]
Lloh96:
	adrp	x9, _LC_FORCE_DIS_HW_SPEED_CHANGE@GOTPAGE
Lloh97:
	ldr	x9, [x9, _LC_FORCE_DIS_HW_SPEED_CHANGE@GOTPAGEOFF]
Lloh98:
	ldr	w9, [x9]
	orr	w8, w8, w28
	orr	w8, w8, w9
Lloh99:
	adrp	x9, _LC_FORCE_DIS_SW_SPEED_CHANGE@GOTPAGE
Lloh100:
	ldr	x9, [x9, _LC_FORCE_DIS_SW_SPEED_CHANGE@GOTPAGEOFF]
Lloh101:
	ldr	w9, [x9]
	bic	w1, w8, w9
	ldr	w0, [x24]
	bl	_WREG32_PCIE_PORT
	ldr	x0, [x19, #8]
Lloh102:
	adrp	x8, _PCI_EXP_LNKCTL2@GOTPAGE
Lloh103:
	ldr	x8, [x8, _PCI_EXP_LNKCTL2@GOTPAGEOFF]
Lloh104:
	ldr	x8, [x8]
	add	x1, x8, x22
	add	x2, sp, #28
	bl	_pci_read_config_word
	ldr	w8, [sp, #28]
	and	w8, w8, #0xfffffff0
	ldr	w9, [x19, #16]
	ldr	w10, [x26]
	tst	w10, w9
	b.eq	LBB0_28
; %bb.27:
	orr	w2, w8, #0x3
	b	LBB0_31
LBB0_28:
	ldr	w10, [x25]
	tst	w10, w9
	b.eq	LBB0_30
; %bb.29:
	orr	w2, w8, #0x2
	b	LBB0_31
LBB0_30:
	orr	w2, w8, #0x1
LBB0_31:
	str	w2, [sp, #28]
	ldr	x0, [x19, #8]
Lloh105:
	adrp	x8, _PCI_EXP_LNKCTL2@GOTPAGE
Lloh106:
	ldr	x8, [x8, _PCI_EXP_LNKCTL2@GOTPAGEOFF]
Lloh107:
	ldr	x8, [x8]
	add	x1, x8, x22
	bl	_pci_write_config_word
	ldr	w0, [x24]
	bl	_RREG32_PCIE_PORT
Lloh108:
	adrp	x20, _LC_INITIATE_LINK_SPEED_CHANGE@GOTPAGE
Lloh109:
	ldr	x20, [x20, _LC_INITIATE_LINK_SPEED_CHANGE@GOTPAGEOFF]
	ldr	w8, [x20]
	orr	w1, w8, w0
	ldr	w0, [x24]
	bl	_WREG32_PCIE_PORT
	ldr	w8, [x19, #4]
	cmp	w8, #1
	b.lt	LBB0_2
; %bb.32:
	mov	w21, #0
LBB0_33:                                ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x24]
	bl	_RREG32_PCIE_PORT
	ldr	w8, [x20]
	tst	w8, w0
	b.eq	LBB0_2
; %bb.34:                               ;   in Loop: Header=BB0_33 Depth=1
	mov	w0, #1
	bl	_udelay
	add	w21, w21, #1
	ldr	w8, [x19, #4]
	cmp	w21, w8
	b.lt	LBB0_33
	b	LBB0_2
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpAdd	Lloh18, Lloh19
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpAdd	Lloh22, Lloh23
	.loh AdrpAdd	Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh72, Lloh73
	.loh AdrpLdrGot	Lloh70, Lloh71
	.loh AdrpLdrGot	Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGot	Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGot	Lloh80, Lloh81
	.loh AdrpLdrGot	Lloh91, Lloh92
	.loh AdrpLdrGot	Lloh89, Lloh90
	.loh AdrpLdrGot	Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGot	Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.cfi_endproc
                                        ; -- End function
	.comm	_amdgpu_pcie_gen2,8,3           ; @amdgpu_pcie_gen2
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2,4,2 ; @CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2
	.comm	_CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3,4,2 ; @CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3
	.comm	_PCIE_LC_SPEED_CNTL,4,2         ; @PCIE_LC_SPEED_CNTL
	.comm	_LC_CURRENT_DATA_RATE_MASK,4,2  ; @LC_CURRENT_DATA_RATE_MASK
	.comm	_LC_CURRENT_DATA_RATE_SHIFT,4,2 ; @LC_CURRENT_DATA_RATE_SHIFT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"PCIE gen 3 link speeds already enabled\n"

l_.str.1:                               ; @.str.1
	.asciz	"enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"

l_.str.2:                               ; @.str.2
	.asciz	"PCIE gen 2 link speeds already enabled\n"

l_.str.3:                               ; @.str.3
	.asciz	"enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"

	.comm	_PCI_EXP_LNKCTL,8,3             ; @PCI_EXP_LNKCTL
	.comm	_PCI_EXP_LNKCTL_HAWD,4,2        ; @PCI_EXP_LNKCTL_HAWD
	.comm	_PCIE_LC_STATUS1,4,2            ; @PCIE_LC_STATUS1
	.comm	_LC_DETECTED_LINK_WIDTH_MASK,4,2 ; @LC_DETECTED_LINK_WIDTH_MASK
	.comm	_LC_DETECTED_LINK_WIDTH_SHIFT,4,2 ; @LC_DETECTED_LINK_WIDTH_SHIFT
	.comm	_LC_OPERATING_LINK_WIDTH_MASK,4,2 ; @LC_OPERATING_LINK_WIDTH_MASK
	.comm	_LC_OPERATING_LINK_WIDTH_SHIFT,4,2 ; @LC_OPERATING_LINK_WIDTH_SHIFT
	.comm	_PCIE_LC_LINK_WIDTH_CNTL,4,2    ; @PCIE_LC_LINK_WIDTH_CNTL
	.comm	_LC_RENEGOTIATION_SUPPORT,4,2   ; @LC_RENEGOTIATION_SUPPORT
	.comm	_LC_LINK_WIDTH_MASK,4,2         ; @LC_LINK_WIDTH_MASK
	.comm	_LC_UPCONFIGURE_DIS,4,2         ; @LC_UPCONFIGURE_DIS
	.comm	_LC_LINK_WIDTH_SHIFT,4,2        ; @LC_LINK_WIDTH_SHIFT
	.comm	_LC_UPCONFIGURE_SUPPORT,4,2     ; @LC_UPCONFIGURE_SUPPORT
	.comm	_LC_RENEGOTIATE_EN,4,2          ; @LC_RENEGOTIATE_EN
	.comm	_LC_RECONFIG_NOW,4,2            ; @LC_RECONFIG_NOW
	.comm	_PCI_EXP_DEVSTA,8,3             ; @PCI_EXP_DEVSTA
	.comm	_PCI_EXP_DEVSTA_TRPND,4,2       ; @PCI_EXP_DEVSTA_TRPND
	.comm	_PCI_EXP_LNKCTL2,8,3            ; @PCI_EXP_LNKCTL2
	.comm	_PCIE_LC_CNTL4,4,2              ; @PCIE_LC_CNTL4
	.comm	_LC_SET_QUIESCE,4,2             ; @LC_SET_QUIESCE
	.comm	_LC_REDO_EQ,4,2                 ; @LC_REDO_EQ
	.comm	_LC_FORCE_EN_SW_SPEED_CHANGE,4,2 ; @LC_FORCE_EN_SW_SPEED_CHANGE
	.comm	_LC_FORCE_DIS_HW_SPEED_CHANGE,4,2 ; @LC_FORCE_DIS_HW_SPEED_CHANGE
	.comm	_LC_FORCE_DIS_SW_SPEED_CHANGE,4,2 ; @LC_FORCE_DIS_SW_SPEED_CHANGE
	.comm	_LC_INITIATE_LINK_SPEED_CHANGE,4,2 ; @LC_INITIATE_LINK_SPEED_CHANGE
	.no_dead_strip	_si_pcie_gen3_enable
.subsections_via_symbols
