	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function nv_update_hdp_clock_gating
_nv_update_hdp_clock_gating:            ## @nv_update_hdp_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_AMD_CG_SUPPORT_HDP_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rdi)
	je	LBB0_5
## %bb.1:
	movl	%esi, %ebx
	movq	_HDP@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movq	_mmHDP_CLK_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ebx, %ebx
	je	LBB0_3
## %bb.2:
	orl	%edx, %ecx
	movq	_HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	notl	%ecx
	andl	%ecx, %eax
	jmp	LBB0_4
LBB0_5:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_3:
	movq	_HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK@GOTPCREL(%rip), %rsi
	movq	_HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK@GOTPCREL(%rip), %rdi
	movq	_HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK@GOTPCREL(%rip), %rbx
	movq	_HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK@GOTPCREL(%rip), %r8
	orl	%eax, %edx
	orl	%ecx, %edx
	orl	(%rsi), %edx
	orl	(%rdi), %edx
	orl	(%rbx), %edx
	orl	(%r8), %edx
	movl	%edx, %eax
LBB0_4:
	movl	(%r14), %edi
	movl	(%r15), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_SOC15                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_CG_SUPPORT_HDP_MGCG,4,2    ## @AMD_CG_SUPPORT_HDP_MGCG
	.comm	_HDP,4,2                        ## @HDP
	.comm	_mmHDP_CLK_CNTL,4,2             ## @mmHDP_CLK_CNTL
	.comm	_HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK,4,2 ## @HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK
	.comm	_HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK,4,2 ## @HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK
	.comm	_HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK,4,2 ## @HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK
	.comm	_HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK,4,2 ## @HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK
	.comm	_HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK,4,2 ## @HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK
	.comm	_HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK,4,2 ## @HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK
	.no_dead_strip	_nv_update_hdp_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function nv_update_hdp_clock_gating
_nv_update_hdp_clock_gating:            ; @nv_update_hdp_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _AMD_CG_SUPPORT_HDP_MGCG@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_CG_SUPPORT_HDP_MGCG@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_3
; %bb.1:
	mov	x19, x1
Lloh3:
	adrp	x20, _HDP@GOTPAGE
Lloh4:
	ldr	x20, [x20, _HDP@GOTPAGEOFF]
	ldr	w0, [x20]
Lloh5:
	adrp	x21, _mmHDP_CLK_CNTL@GOTPAGE
Lloh6:
	ldr	x21, [x21, _mmHDP_CLK_CNTL@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh7:
	adrp	x8, _HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK@GOTPAGE
Lloh8:
	ldr	x8, [x8, _HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
Lloh10:
	adrp	x9, _HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK@GOTPAGE
Lloh11:
	ldr	x9, [x9, _HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
	cbz	w19, LBB0_4
; %bb.2:
	orr	w8, w9, w8
Lloh13:
	adrp	x9, _HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK@GOTPAGE
Lloh14:
	ldr	x9, [x9, _HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
Lloh16:
	adrp	x10, _HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK@GOTPAGE
Lloh17:
	ldr	x10, [x10, _HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh18:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh19:
	adrp	x9, _HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK@GOTPAGE
Lloh20:
	ldr	x9, [x9, _HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh22:
	adrp	x9, _HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK@GOTPAGE
Lloh23:
	ldr	x9, [x9, _HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w3, w0, w8
	b	LBB0_5
LBB0_3:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_4:
Lloh25:
	adrp	x10, _HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK@GOTPAGE
Lloh26:
	ldr	x10, [x10, _HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK@GOTPAGEOFF]
Lloh27:
	ldr	w10, [x10]
Lloh28:
	adrp	x11, _HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK@GOTPAGE
Lloh29:
	ldr	x11, [x11, _HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK@GOTPAGEOFF]
Lloh30:
	ldr	w11, [x11]
Lloh31:
	adrp	x12, _HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK@GOTPAGE
Lloh32:
	ldr	x12, [x12, _HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK@GOTPAGEOFF]
Lloh33:
	ldr	w12, [x12]
Lloh34:
	adrp	x13, _HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK@GOTPAGE
Lloh35:
	ldr	x13, [x13, _HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK@GOTPAGEOFF]
Lloh36:
	ldr	w13, [x13]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w3, w8, w13
LBB0_5:
	ldr	w0, [x20]
	ldr	w2, [x21]
	mov	w1, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32_SOC15
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_CG_SUPPORT_HDP_MGCG,4,2    ; @AMD_CG_SUPPORT_HDP_MGCG
	.comm	_HDP,4,2                        ; @HDP
	.comm	_mmHDP_CLK_CNTL,4,2             ; @mmHDP_CLK_CNTL
	.comm	_HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK,4,2 ; @HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK
	.comm	_HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK,4,2 ; @HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK
	.comm	_HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK,4,2 ; @HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK
	.comm	_HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK,4,2 ; @HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK
	.comm	_HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK,4,2 ; @HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK
	.comm	_HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK,4,2 ; @HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK
	.no_dead_strip	_nv_update_hdp_clock_gating
.subsections_via_symbols
