	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v7_0_ring_emit_ib_gfx
_gfx_v7_0_ring_emit_ib_gfx:             ## @gfx_v7_0_ring_emit_ib_gfx
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %r12d
	movq	%rdx, %r15
	movq	%rdi, %rbx
	movq	%rsi, %rdi
	callq	_AMDGPU_JOB_GET_VMID
	movl	%eax, %r14d
	movq	_AMDGPU_HAVE_CTX_SWITCH@GOTPCREL(%rip), %rax
	testl	%r12d, (%rax)
	je	LBB0_2
## %bb.1:
	movq	_PACKET3_SWITCH_BUFFER@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET3
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
LBB0_2:
	movq	_AMDGPU_IB_FLAG_CE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%r15), %eax
	jne	LBB0_3
## %bb.4:
	movq	_PACKET3_INDIRECT_BUFFER@GOTPCREL(%rip), %rax
	jmp	LBB0_5
LBB0_3:
	movq	_PACKET3_INDIRECT_BUFFER_CONST@GOTPCREL(%rip), %rax
LBB0_5:
	movl	(%rax), %edi
	movl	$2, %esi
	callq	_PACKET3
	shll	$24, %r14d
	orl	4(%r15), %r14d
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	8(%r15), %esi
	andl	$-4, %esi
	movq	%rbx, %rdi
	callq	_amdgpu_ring_write
	movl	8(%r15), %edi
	callq	_upper_32_bits
	movzwl	%ax, %esi
	movq	%rbx, %rdi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	%r14d, %esi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_write              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_HAVE_CTX_SWITCH,4,2     ## @AMDGPU_HAVE_CTX_SWITCH
	.comm	_PACKET3_SWITCH_BUFFER,4,2      ## @PACKET3_SWITCH_BUFFER
	.comm	_AMDGPU_IB_FLAG_CE,4,2          ## @AMDGPU_IB_FLAG_CE
	.comm	_PACKET3_INDIRECT_BUFFER_CONST,4,2 ## @PACKET3_INDIRECT_BUFFER_CONST
	.comm	_PACKET3_INDIRECT_BUFFER,4,2    ## @PACKET3_INDIRECT_BUFFER
	.no_dead_strip	_gfx_v7_0_ring_emit_ib_gfx
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v7_0_ring_emit_ib_gfx
_gfx_v7_0_ring_emit_ib_gfx:             ; @gfx_v7_0_ring_emit_ib_gfx
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x22, x3
	mov	x20, x2
	mov	x19, x0
	mov	x0, x1
	bl	_AMDGPU_JOB_GET_VMID
	mov	x21, x0
Lloh0:
	adrp	x8, _AMDGPU_HAVE_CTX_SWITCH@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPU_HAVE_CTX_SWITCH@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_2
; %bb.1:
Lloh3:
	adrp	x8, _PACKET3_SWITCH_BUFFER@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PACKET3_SWITCH_BUFFER@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_ring_write
LBB0_2:
	ldr	w8, [x20]
Lloh6:
	adrp	x9, _AMDGPU_IB_FLAG_CE@GOTPAGE
Lloh7:
	ldr	x9, [x9, _AMDGPU_IB_FLAG_CE@GOTPAGEOFF]
Lloh8:
	adrp	x10, _PACKET3_INDIRECT_BUFFER@GOTPAGE
Lloh9:
	ldr	x10, [x10, _PACKET3_INDIRECT_BUFFER@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
Lloh11:
	adrp	x11, _PACKET3_INDIRECT_BUFFER_CONST@GOTPAGE
Lloh12:
	ldr	x11, [x11, _PACKET3_INDIRECT_BUFFER_CONST@GOTPAGEOFF]
	tst	w9, w8
	csel	x8, x10, x11, eq
	ldr	w0, [x8]
	mov	w1, #2
	bl	_PACKET3
	mov	x1, x0
	ldr	w8, [x20, #4]
	orr	w21, w8, w21, lsl #24
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w8, [x20, #8]
	and	w1, w8, #0xfffffffc
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x20, #8]
	bl	_upper_32_bits
	and	w1, w0, #0xffff
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	x1, x21
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_amdgpu_ring_write
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh10
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_HAVE_CTX_SWITCH,4,2     ; @AMDGPU_HAVE_CTX_SWITCH
	.comm	_PACKET3_SWITCH_BUFFER,4,2      ; @PACKET3_SWITCH_BUFFER
	.comm	_AMDGPU_IB_FLAG_CE,4,2          ; @AMDGPU_IB_FLAG_CE
	.comm	_PACKET3_INDIRECT_BUFFER_CONST,4,2 ; @PACKET3_INDIRECT_BUFFER_CONST
	.comm	_PACKET3_INDIRECT_BUFFER,4,2    ; @PACKET3_INDIRECT_BUFFER
	.no_dead_strip	_gfx_v7_0_ring_emit_ib_gfx
.subsections_via_symbols
