	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function chv_prepare_pll
_chv_prepare_pll:                       ## @chv_prepare_pll
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r12
	movq	%rdi, %rbx
	movq	8(%rdi), %rdi
	callq	_to_i915
	movq	%rax, %r13
	movl	(%rbx), %ebx
	movl	%ebx, %edi
	callq	_vlv_pipe_to_channel
	movl	%eax, %r15d
	movl	%ebx, %edi
	callq	_DPLL
	movq	_DPLL_VCO_ENABLE@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	notl	%esi
	andl	24(%r12), %esi
	movl	%eax, %edi
	callq	_I915_WRITE
	movl	(%r14), %eax
	testl	%eax, 24(%r12)
	je	LBB0_7
## %bb.1:
	movl	4(%r12), %eax
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	movq	%r13, %rcx
	movl	%r15d, %r13d
	movl	12(%r12), %r15d
	movl	%ebx, -52(%rbp)                 ## 4-byte Spill
	movl	%eax, %ebx
	sarl	$22, %ebx
	movq	%rcx, -48(%rbp)                 ## 8-byte Spill
	movl	16(%r12), %r14d
	movl	20(%r12), %eax
	movl	%eax, -60(%rbp)                 ## 4-byte Spill
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_vlv_dpio_get
	movl	%r13d, %edi
	callq	_CHV_CMN_DW13
	movq	_DPIO_CHV_S1_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$5, %edx
	shll	%cl, %edx
	movq	_DPIO_CHV_P1_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r15d
	orl	%edx, %r15d
	movq	_DPIO_CHV_P2_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r14d
	orl	%r15d, %r14d
	movq	_DPIO_CHV_K_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	btsl	%ecx, %r14d
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movl	-52(%rbp), %esi                 ## 4-byte Reload
	movl	%eax, %edx
	movl	%r14d, %ecx
	callq	_vlv_dpio_write
	movl	%r13d, %edi
	callq	_CHV_PLL_DW0
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movl	-52(%rbp), %esi                 ## 4-byte Reload
	movl	%eax, %edx
	movl	%ebx, %ecx
	movl	-52(%rbp), %r12d                ## 4-byte Reload
	callq	_vlv_dpio_write
	movl	%r13d, %edi
	callq	_CHV_PLL_DW1
	movq	_DPIO_CHV_M1_DIV_BY_2@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	_DPIO_CHV_N_DIV_SHIFT@GOTPCREL(%rip), %rdx
	movb	(%rdx), %dl
	btsl	%edx, %ecx
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movl	%r12d, %esi
	movl	%eax, %edx
	callq	_vlv_dpio_write
	movl	%r13d, %edi
	callq	_CHV_PLL_DW2
	movl	-56(%rbp), %ebx                 ## 4-byte Reload
	movl	%ebx, %ecx
	andl	$4194303, %ecx                  ## imm = 0x3FFFFF
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movl	%r12d, %esi
	movl	%eax, %edx
	callq	_vlv_dpio_write
	movl	%r13d, %edi
	callq	_CHV_PLL_DW3
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movl	%r12d, %esi
	movl	%eax, %edx
	callq	_vlv_dpio_read
	xorl	%r14d, %r14d
	movl	%ebx, %ecx
	andl	$4194303, %ecx                  ## imm = 0x3FFFFF
	movq	_DPIO_CHV_FEEDFWD_GAIN_MASK@GOTPCREL(%rip), %rcx
	movq	_DPIO_CHV_FRAC_DIV_EN@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movl	%edx, %esi
	cmovel	%r14d, %esi
	orl	(%rcx), %edx
	movq	_DPIO_CHV_FEEDFWD_GAIN_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %ebx
	shll	%cl, %ebx
	notl	%edx
	andl	%eax, %edx
	orl	%esi, %ebx
	orl	%edx, %ebx
	movl	%r13d, %edi
	callq	_CHV_PLL_DW3
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movl	%r12d, %esi
	movl	%eax, %edx
	movl	%ebx, %ecx
	callq	_vlv_dpio_write
	movl	%r13d, %edi
	callq	_CHV_PLL_DW9
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movl	%r12d, %esi
	movl	%eax, %edx
	callq	_vlv_dpio_read
	andl	$4194303, -56(%rbp)             ## 4-byte Folded Spill
                                        ## imm = 0x3FFFFF
	movq	_DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	cmovel	%edx, %r14d
	movq	_DPIO_CHV_INT_LOCK_THRESHOLD_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	_DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$5, %ebx
	shll	%cl, %ebx
	notl	%edx
	andl	%eax, %edx
	orl	%r14d, %ebx
	movq	-48(%rbp), %r14                 ## 8-byte Reload
	orl	%edx, %ebx
	movl	%r13d, %edi
	callq	_CHV_PLL_DW9
	movq	%r14, %rdi
	movl	%r12d, %esi
	movl	%eax, %edx
	movl	%ebx, %ecx
	callq	_vlv_dpio_write
	movl	-60(%rbp), %eax                 ## 4-byte Reload
	cmpl	$5400000, %eax                  ## imm = 0x5265C0
	jne	LBB0_3
## %bb.2:
	movq	_DPIO_CHV_PROP_COEFF_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$3, %eax
	shll	%cl, %eax
	movq	_DPIO_CHV_INT_COEFF_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$8, %ebx
	shll	%cl, %ebx
	orl	%eax, %ebx
	movq	_DPIO_CHV_GAIN_CTRL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	btsl	%eax, %ebx
	movl	$9, %r12d
	jmp	LBB0_6
LBB0_7:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_3:
	cmpl	$6200000, %eax                  ## imm = 0x5E9AC0
	jg	LBB0_5
## %bb.4:
	movq	_DPIO_CHV_PROP_COEFF_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$5, %eax
	shll	%cl, %eax
	movq	_DPIO_CHV_INT_COEFF_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$11, %edx
	shll	%cl, %edx
	movq	_DPIO_CHV_GAIN_CTRL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$3, %ebx
	shll	%cl, %ebx
	orl	%eax, %edx
	orl	%edx, %ebx
	movl	$9, %r12d
	jmp	LBB0_6
LBB0_5:
	xorl	%r12d, %r12d
	cmpl	$6480001, %eax                  ## imm = 0x62E081
	setb	%r12b
	movq	_DPIO_CHV_PROP_COEFF_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$4, %eax
	shll	%cl, %eax
	movq	_DPIO_CHV_INT_COEFF_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$9, %edx
	shll	%cl, %edx
	movq	_DPIO_CHV_GAIN_CTRL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$3, %ebx
	shll	%cl, %ebx
	orl	%eax, %edx
	orl	%edx, %ebx
	shll	$3, %r12d
LBB0_6:
	movl	%r13d, %edi
	callq	_CHV_PLL_DW6
	movq	%r14, %rdi
	movl	-52(%rbp), %r15d                ## 4-byte Reload
	movl	%r15d, %esi
	movl	%eax, %edx
	movl	%ebx, %ecx
	callq	_vlv_dpio_write
	movl	%r13d, %edi
	callq	_CHV_PLL_DW8
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_vlv_dpio_read
	movq	_DPIO_CHV_TDC_TARGET_CNT_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	_DPIO_CHV_TDC_TARGET_CNT_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r12d
	orl	%edx, %r12d
	movl	%r13d, %edi
	callq	_CHV_PLL_DW8
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	movl	%r12d, %ecx
	callq	_vlv_dpio_write
	movl	%r13d, %edi
	callq	_CHV_CMN_DW14
	movl	%eax, %ebx
	movl	%r13d, %edi
	callq	_CHV_CMN_DW14
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_vlv_dpio_read
	movq	_DPIO_AFC_RECAL@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	movl	%eax, %ecx
	callq	_vlv_dpio_write
	movq	%r14, %rdi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_vlv_dpio_put                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_DPLL_VCO_ENABLE,4,2            ## @DPLL_VCO_ENABLE
	.comm	_DPIO_CHV_S1_DIV_SHIFT,4,2      ## @DPIO_CHV_S1_DIV_SHIFT
	.comm	_DPIO_CHV_P1_DIV_SHIFT,4,2      ## @DPIO_CHV_P1_DIV_SHIFT
	.comm	_DPIO_CHV_P2_DIV_SHIFT,4,2      ## @DPIO_CHV_P2_DIV_SHIFT
	.comm	_DPIO_CHV_K_DIV_SHIFT,4,2       ## @DPIO_CHV_K_DIV_SHIFT
	.comm	_DPIO_CHV_M1_DIV_BY_2,4,2       ## @DPIO_CHV_M1_DIV_BY_2
	.comm	_DPIO_CHV_N_DIV_SHIFT,4,2       ## @DPIO_CHV_N_DIV_SHIFT
	.comm	_DPIO_CHV_FEEDFWD_GAIN_MASK,4,2 ## @DPIO_CHV_FEEDFWD_GAIN_MASK
	.comm	_DPIO_CHV_FRAC_DIV_EN,4,2       ## @DPIO_CHV_FRAC_DIV_EN
	.comm	_DPIO_CHV_FEEDFWD_GAIN_SHIFT,4,2 ## @DPIO_CHV_FEEDFWD_GAIN_SHIFT
	.comm	_DPIO_CHV_INT_LOCK_THRESHOLD_MASK,4,2 ## @DPIO_CHV_INT_LOCK_THRESHOLD_MASK
	.comm	_DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE,4,2 ## @DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
	.comm	_DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT,4,2 ## @DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
	.comm	_DPIO_CHV_PROP_COEFF_SHIFT,4,2  ## @DPIO_CHV_PROP_COEFF_SHIFT
	.comm	_DPIO_CHV_INT_COEFF_SHIFT,4,2   ## @DPIO_CHV_INT_COEFF_SHIFT
	.comm	_DPIO_CHV_GAIN_CTRL_SHIFT,4,2   ## @DPIO_CHV_GAIN_CTRL_SHIFT
	.comm	_DPIO_CHV_TDC_TARGET_CNT_MASK,4,2 ## @DPIO_CHV_TDC_TARGET_CNT_MASK
	.comm	_DPIO_CHV_TDC_TARGET_CNT_SHIFT,4,2 ## @DPIO_CHV_TDC_TARGET_CNT_SHIFT
	.comm	_DPIO_AFC_RECAL,4,2             ## @DPIO_AFC_RECAL
	.no_dead_strip	_chv_prepare_pll
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function chv_prepare_pll
_chv_prepare_pll:                       ; @chv_prepare_pll
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x22, x1
	mov	x20, x0
	ldr	x0, [x0, #8]
	bl	_to_i915
	mov	x19, x0
	ldr	w20, [x20]
	mov	x0, x20
	bl	_vlv_pipe_to_channel
	mov	x21, x0
	mov	x0, x20
	bl	_DPLL
	ldr	w8, [x22, #24]
Lloh0:
	adrp	x23, _DPLL_VCO_ENABLE@GOTPAGE
Lloh1:
	ldr	x23, [x23, _DPLL_VCO_ENABLE@GOTPAGEOFF]
	ldr	w9, [x23]
	bic	w1, w8, w9
	bl	_I915_WRITE
	ldr	w8, [x22, #24]
	ldr	w9, [x23]
	tst	w9, w8
	b.eq	LBB0_3
; %bb.1:
	ldr	w26, [x22, #4]
	asr	w23, w26, #22
	ldp	w25, w28, [x22, #12]
	ldr	w24, [x22, #20]
	mov	x0, x19
	bl	_vlv_dpio_get
	mov	x0, x21
	bl	_CHV_CMN_DW13
	mov	x2, x0
Lloh2:
	adrp	x8, _DPIO_CHV_S1_DIV_SHIFT@GOTPAGE
Lloh3:
	ldr	x8, [x8, _DPIO_CHV_S1_DIV_SHIFT@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	mov	w27, #5
	lsl	w8, w27, w8
Lloh5:
	adrp	x9, _DPIO_CHV_P1_DIV_SHIFT@GOTPAGE
Lloh6:
	ldr	x9, [x9, _DPIO_CHV_P1_DIV_SHIFT@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	lsl	w9, w25, w9
	orr	w8, w9, w8
Lloh8:
	adrp	x9, _DPIO_CHV_P2_DIV_SHIFT@GOTPAGE
Lloh9:
	ldr	x9, [x9, _DPIO_CHV_P2_DIV_SHIFT@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
	lsl	w9, w28, w9
	orr	w8, w8, w9
Lloh11:
	adrp	x9, _DPIO_CHV_K_DIV_SHIFT@GOTPAGE
Lloh12:
	ldr	x9, [x9, _DPIO_CHV_K_DIV_SHIFT@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	mov	w25, #1
	lsl	w9, w25, w9
	orr	w3, w8, w9
	mov	x0, x19
	mov	x1, x20
	bl	_vlv_dpio_write
	mov	x0, x21
	bl	_CHV_PLL_DW0
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	mov	x3, x23
	bl	_vlv_dpio_write
	mov	x0, x21
	bl	_CHV_PLL_DW1
	mov	x2, x0
Lloh14:
	adrp	x8, _DPIO_CHV_M1_DIV_BY_2@GOTPAGE
Lloh15:
	ldr	x8, [x8, _DPIO_CHV_M1_DIV_BY_2@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
Lloh17:
	adrp	x9, _DPIO_CHV_N_DIV_SHIFT@GOTPAGE
Lloh18:
	ldr	x9, [x9, _DPIO_CHV_N_DIV_SHIFT@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	lsl	w9, w25, w9
	orr	w3, w9, w8
	mov	x0, x19
	mov	x1, x20
	bl	_vlv_dpio_write
	mov	x0, x21
	bl	_CHV_PLL_DW2
	mov	x2, x0
	ands	w3, w26, #0x3fffff
	mov	x0, x19
	mov	x1, x20
	bl	_vlv_dpio_write
	mov	x0, x21
	bl	_CHV_PLL_DW3
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_vlv_dpio_read
	tst	w26, #0x3fffff
Lloh20:
	adrp	x8, _DPIO_CHV_FEEDFWD_GAIN_MASK@GOTPAGE
Lloh21:
	ldr	x8, [x8, _DPIO_CHV_FEEDFWD_GAIN_MASK@GOTPAGEOFF]
Lloh22:
	adrp	x9, _DPIO_CHV_FRAC_DIV_EN@GOTPAGE
Lloh23:
	ldr	x9, [x9, _DPIO_CHV_FRAC_DIV_EN@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
Lloh25:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
Lloh26:
	adrp	x10, _DPIO_CHV_FEEDFWD_GAIN_SHIFT@GOTPAGE
Lloh27:
	ldr	x10, [x10, _DPIO_CHV_FEEDFWD_GAIN_SHIFT@GOTPAGEOFF]
Lloh28:
	ldr	w10, [x10]
	mov	w11, #2
	lsl	w10, w11, w10
	csel	w9, wzr, w9, eq
	orr	w9, w10, w9
	orr	w22, w9, w8
	mov	x0, x21
	bl	_CHV_PLL_DW3
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	mov	x3, x22
	bl	_vlv_dpio_write
	mov	x0, x21
	bl	_CHV_PLL_DW9
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_vlv_dpio_read
	tst	w26, #0x3fffff
Lloh29:
	adrp	x8, _DPIO_CHV_INT_LOCK_THRESHOLD_MASK@GOTPAGE
Lloh30:
	ldr	x8, [x8, _DPIO_CHV_INT_LOCK_THRESHOLD_MASK@GOTPAGEOFF]
Lloh31:
	ldr	w8, [x8]
Lloh32:
	adrp	x9, _DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE@GOTPAGE
Lloh33:
	ldr	x9, [x9, _DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh35:
	adrp	x10, _DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT@GOTPAGE
Lloh36:
	ldr	x10, [x10, _DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT@GOTPAGEOFF]
	bic	w8, w0, w8
Lloh37:
	ldr	w10, [x10]
	lsl	w10, w27, w10
	csel	w9, w9, wzr, eq
	orr	w9, w10, w9
	orr	w22, w9, w8
	mov	x0, x21
	bl	_CHV_PLL_DW9
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	mov	x3, x22
	bl	_vlv_dpio_write
	sub	w8, w24, #1318, lsl #12         ; =5398528
	cmp	w8, #1472
	b.ne	LBB0_4
; %bb.2:
Lloh38:
	adrp	x8, _DPIO_CHV_PROP_COEFF_SHIFT@GOTPAGE
Lloh39:
	ldr	x8, [x8, _DPIO_CHV_PROP_COEFF_SHIFT@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
	mov	w9, #3
	lsl	w8, w9, w8
Lloh41:
	adrp	x9, _DPIO_CHV_INT_COEFF_SHIFT@GOTPAGE
Lloh42:
	ldr	x9, [x9, _DPIO_CHV_INT_COEFF_SHIFT@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
	mov	w10, #8
	lsl	w9, w10, w9
	orr	w8, w9, w8
Lloh44:
	adrp	x9, _DPIO_CHV_GAIN_CTRL_SHIFT@GOTPAGE
Lloh45:
	ldr	x9, [x9, _DPIO_CHV_GAIN_CTRL_SHIFT@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
	lsl	w9, w25, w9
	b	LBB0_6
LBB0_3:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
LBB0_4:
	mov	w8, #39616
	movk	w8, #94, lsl #16
	cmp	w24, w8
	b.gt	LBB0_7
; %bb.5:
Lloh47:
	adrp	x8, _DPIO_CHV_PROP_COEFF_SHIFT@GOTPAGE
Lloh48:
	ldr	x8, [x8, _DPIO_CHV_PROP_COEFF_SHIFT@GOTPAGEOFF]
Lloh49:
	ldr	w8, [x8]
	mov	w9, #5
Lloh50:
	adrp	x10, _DPIO_CHV_INT_COEFF_SHIFT@GOTPAGE
Lloh51:
	ldr	x10, [x10, _DPIO_CHV_INT_COEFF_SHIFT@GOTPAGEOFF]
	lsl	w8, w9, w8
Lloh52:
	ldr	w9, [x10]
	mov	w10, #11
	lsl	w9, w10, w9
Lloh53:
	adrp	x10, _DPIO_CHV_GAIN_CTRL_SHIFT@GOTPAGE
Lloh54:
	ldr	x10, [x10, _DPIO_CHV_GAIN_CTRL_SHIFT@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh55:
	ldr	w9, [x10]
	mov	w10, #3
	lsl	w9, w10, w9
LBB0_6:
	orr	w22, w8, w9
	mov	w23, #9
	b	LBB0_8
LBB0_7:
	mov	w8, #57473
	movk	w8, #98, lsl #16
	cmp	w24, w8
	cset	w8, lo
Lloh56:
	adrp	x9, _DPIO_CHV_PROP_COEFF_SHIFT@GOTPAGE
Lloh57:
	ldr	x9, [x9, _DPIO_CHV_PROP_COEFF_SHIFT@GOTPAGEOFF]
Lloh58:
	ldr	w9, [x9]
	mov	w10, #4
Lloh59:
	adrp	x11, _DPIO_CHV_INT_COEFF_SHIFT@GOTPAGE
Lloh60:
	ldr	x11, [x11, _DPIO_CHV_INT_COEFF_SHIFT@GOTPAGEOFF]
	lsl	w9, w10, w9
Lloh61:
	ldr	w10, [x11]
	mov	w11, #9
	lsl	w10, w11, w10
Lloh62:
	adrp	x11, _DPIO_CHV_GAIN_CTRL_SHIFT@GOTPAGE
Lloh63:
	ldr	x11, [x11, _DPIO_CHV_GAIN_CTRL_SHIFT@GOTPAGEOFF]
	orr	w9, w10, w9
Lloh64:
	ldr	w10, [x11]
	mov	w11, #3
	lsl	w10, w11, w10
	orr	w22, w9, w10
	lsl	w23, w8, #3
LBB0_8:
	mov	x0, x21
	bl	_CHV_PLL_DW6
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	mov	x3, x22
	bl	_vlv_dpio_write
	mov	x0, x21
	bl	_CHV_PLL_DW8
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_vlv_dpio_read
Lloh65:
	adrp	x8, _DPIO_CHV_TDC_TARGET_CNT_MASK@GOTPAGE
Lloh66:
	ldr	x8, [x8, _DPIO_CHV_TDC_TARGET_CNT_MASK@GOTPAGEOFF]
Lloh67:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh68:
	adrp	x9, _DPIO_CHV_TDC_TARGET_CNT_SHIFT@GOTPAGE
Lloh69:
	ldr	x9, [x9, _DPIO_CHV_TDC_TARGET_CNT_SHIFT@GOTPAGEOFF]
Lloh70:
	ldr	w9, [x9]
	lsl	w9, w23, w9
	orr	w22, w9, w8
	mov	x0, x21
	bl	_CHV_PLL_DW8
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	mov	x3, x22
	bl	_vlv_dpio_write
	mov	x0, x21
	bl	_CHV_CMN_DW14
	mov	x22, x0
	mov	x0, x21
	bl	_CHV_CMN_DW14
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_vlv_dpio_read
Lloh71:
	adrp	x8, _DPIO_AFC_RECAL@GOTPAGE
Lloh72:
	ldr	x8, [x8, _DPIO_AFC_RECAL@GOTPAGEOFF]
Lloh73:
	ldr	w8, [x8]
	orr	w3, w8, w0
	mov	x0, x19
	mov	x1, x20
	mov	x2, x22
	bl	_vlv_dpio_write
	mov	x0, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_vlv_dpio_put
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh24
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.cfi_endproc
                                        ; -- End function
	.comm	_DPLL_VCO_ENABLE,4,2            ; @DPLL_VCO_ENABLE
	.comm	_DPIO_CHV_S1_DIV_SHIFT,4,2      ; @DPIO_CHV_S1_DIV_SHIFT
	.comm	_DPIO_CHV_P1_DIV_SHIFT,4,2      ; @DPIO_CHV_P1_DIV_SHIFT
	.comm	_DPIO_CHV_P2_DIV_SHIFT,4,2      ; @DPIO_CHV_P2_DIV_SHIFT
	.comm	_DPIO_CHV_K_DIV_SHIFT,4,2       ; @DPIO_CHV_K_DIV_SHIFT
	.comm	_DPIO_CHV_M1_DIV_BY_2,4,2       ; @DPIO_CHV_M1_DIV_BY_2
	.comm	_DPIO_CHV_N_DIV_SHIFT,4,2       ; @DPIO_CHV_N_DIV_SHIFT
	.comm	_DPIO_CHV_FEEDFWD_GAIN_MASK,4,2 ; @DPIO_CHV_FEEDFWD_GAIN_MASK
	.comm	_DPIO_CHV_FRAC_DIV_EN,4,2       ; @DPIO_CHV_FRAC_DIV_EN
	.comm	_DPIO_CHV_FEEDFWD_GAIN_SHIFT,4,2 ; @DPIO_CHV_FEEDFWD_GAIN_SHIFT
	.comm	_DPIO_CHV_INT_LOCK_THRESHOLD_MASK,4,2 ; @DPIO_CHV_INT_LOCK_THRESHOLD_MASK
	.comm	_DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE,4,2 ; @DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
	.comm	_DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT,4,2 ; @DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
	.comm	_DPIO_CHV_PROP_COEFF_SHIFT,4,2  ; @DPIO_CHV_PROP_COEFF_SHIFT
	.comm	_DPIO_CHV_INT_COEFF_SHIFT,4,2   ; @DPIO_CHV_INT_COEFF_SHIFT
	.comm	_DPIO_CHV_GAIN_CTRL_SHIFT,4,2   ; @DPIO_CHV_GAIN_CTRL_SHIFT
	.comm	_DPIO_CHV_TDC_TARGET_CNT_MASK,4,2 ; @DPIO_CHV_TDC_TARGET_CNT_MASK
	.comm	_DPIO_CHV_TDC_TARGET_CNT_SHIFT,4,2 ; @DPIO_CHV_TDC_TARGET_CNT_SHIFT
	.comm	_DPIO_AFC_RECAL,4,2             ; @DPIO_AFC_RECAL
	.no_dead_strip	_chv_prepare_pll
.subsections_via_symbols
