	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_intel_init_cdclk_hooks         ## -- Begin function intel_init_cdclk_hooks
	.p2align	4, 0x90
_intel_init_cdclk_hooks:                ## @intel_init_cdclk_hooks
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	callq	_INTEL_GEN
	cmpl	$10, %eax
	jle	LBB0_2
## %bb.1:
	movq	_icl_modeset_calc_cdclk@GOTPCREL(%rip), %rbx
	movq	_icl_set_cdclk@GOTPCREL(%rip), %rax
	jmp	LBB0_14
LBB0_2:
	movq	%r12, %rdi
	callq	_IS_CANNONLAKE
	testq	%rax, %rax
	je	LBB0_4
## %bb.3:
	movq	_cnl_modeset_calc_cdclk@GOTPCREL(%rip), %rbx
	movq	_cnl_set_cdclk@GOTPCREL(%rip), %rax
	jmp	LBB0_14
LBB0_4:
	movq	%r12, %rdi
	callq	_IS_GEN9_LP
	testq	%rax, %rax
	je	LBB0_6
## %bb.5:
	movq	_bxt_modeset_calc_cdclk@GOTPCREL(%rip), %rbx
	movq	_bxt_set_cdclk@GOTPCREL(%rip), %rax
	jmp	LBB0_14
LBB0_6:
	movq	%r12, %rdi
	callq	_IS_GEN9_BC
	testq	%rax, %rax
	je	LBB0_8
## %bb.7:
	movq	_skl_modeset_calc_cdclk@GOTPCREL(%rip), %rbx
	movq	_skl_set_cdclk@GOTPCREL(%rip), %rax
	jmp	LBB0_14
LBB0_8:
	movq	%r12, %rdi
	callq	_IS_BROADWELL
	testq	%rax, %rax
	je	LBB0_10
## %bb.9:
	movq	_bdw_modeset_calc_cdclk@GOTPCREL(%rip), %rbx
	movq	_bdw_set_cdclk@GOTPCREL(%rip), %rax
	jmp	LBB0_14
LBB0_10:
	movq	%r12, %rdi
	callq	_IS_CHERRYVIEW
	movq	_vlv_modeset_calc_cdclk@GOTPCREL(%rip), %rbx
	testq	%rax, %rax
	je	LBB0_12
## %bb.11:
	movq	_chv_set_cdclk@GOTPCREL(%rip), %rax
	jmp	LBB0_14
LBB0_12:
	movq	%r12, %rdi
	callq	_IS_VALLEYVIEW
	testq	%rax, %rax
	je	LBB0_15
## %bb.13:
	movq	_vlv_set_cdclk@GOTPCREL(%rip), %rax
LBB0_14:
	movl	(%rax), %eax
	movl	%eax, 16(%r12)
	movq	(%rbx), %rax
	movq	%rax, 8(%r12)
LBB0_15:
	movq	%r12, %rdi
	callq	_INTEL_GEN
	cmpl	$10, %eax
	jle	LBB0_17
## %bb.16:
	movq	_icl_get_cdclk@GOTPCREL(%rip), %r14
	jmp	LBB0_59
LBB0_17:
	movq	%r12, %rdi
	callq	_IS_CANNONLAKE
	testq	%rax, %rax
	je	LBB0_19
## %bb.18:
	movq	_cnl_get_cdclk@GOTPCREL(%rip), %r14
	jmp	LBB0_59
LBB0_19:
	movq	%r12, %rdi
	callq	_IS_GEN9_LP
	testq	%rax, %rax
	je	LBB0_21
## %bb.20:
	movq	_bxt_get_cdclk@GOTPCREL(%rip), %r14
	jmp	LBB0_59
LBB0_21:
	movq	%r12, %rdi
	callq	_IS_GEN9_BC
	testq	%rax, %rax
	je	LBB0_23
## %bb.22:
	movq	_skl_get_cdclk@GOTPCREL(%rip), %r14
	jmp	LBB0_59
LBB0_23:
	movq	%r12, %rdi
	callq	_IS_BROADWELL
	testq	%rax, %rax
	je	LBB0_25
## %bb.24:
	movq	_bdw_get_cdclk@GOTPCREL(%rip), %r14
	jmp	LBB0_59
LBB0_25:
	movq	%r12, %rdi
	callq	_IS_HASWELL
	testq	%rax, %rax
	je	LBB0_27
## %bb.26:
	movq	_hsw_get_cdclk@GOTPCREL(%rip), %r14
	jmp	LBB0_59
LBB0_27:
	movq	%r12, %rdi
	callq	_IS_VALLEYVIEW
	movq	_vlv_get_cdclk@GOTPCREL(%rip), %r14
	testq	%rax, %rax
	jne	LBB0_59
## %bb.28:
	movq	%r12, %rdi
	callq	_IS_CHERRYVIEW
	testq	%rax, %rax
	jne	LBB0_59
## %bb.29:
	movq	%r12, %rdi
	movl	$6, %esi
	callq	_IS_GEN
	movq	_fixed_400mhz_get_cdclk@GOTPCREL(%rip), %r15
	testq	%rax, %rax
	jne	LBB0_30
## %bb.31:
	movq	%r12, %rdi
	callq	_IS_IVYBRIDGE
	testq	%rax, %rax
	je	LBB0_33
LBB0_30:
	movq	%r15, %r14
LBB0_59:
	movq	(%r14), %rax
	movq	%rax, (%r12)
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_33:
	movq	%r12, %rdi
	movl	$5, %esi
	callq	_IS_GEN
	testq	%rax, %rax
	je	LBB0_35
## %bb.34:
	movq	_fixed_450mhz_get_cdclk@GOTPCREL(%rip), %r14
	jmp	LBB0_59
LBB0_35:
	movq	%r12, %rdi
	callq	_IS_GM45
	testq	%rax, %rax
	je	LBB0_37
## %bb.36:
	movq	_gm45_get_cdclk@GOTPCREL(%rip), %r14
	jmp	LBB0_59
LBB0_37:
	movq	%r12, %rdi
	callq	_IS_G45
	movq	_g33_get_cdclk@GOTPCREL(%rip), %r14
	testq	%rax, %rax
	jne	LBB0_59
## %bb.38:
	movq	%r12, %rdi
	callq	_IS_I965GM
	testq	%rax, %rax
	je	LBB0_40
## %bb.39:
	movq	_i965gm_get_cdclk@GOTPCREL(%rip), %r14
	jmp	LBB0_59
LBB0_40:
	movq	%r12, %rdi
	callq	_IS_I965G
	testq	%rax, %rax
	jne	LBB0_30
## %bb.42:
	movq	%r12, %rdi
	callq	_IS_PINEVIEW
	testq	%rax, %rax
	je	LBB0_44
## %bb.43:
	movq	_pnv_get_cdclk@GOTPCREL(%rip), %r14
	jmp	LBB0_59
LBB0_44:
	movq	%r12, %rdi
	callq	_IS_G33
	testq	%rax, %rax
	jne	LBB0_59
## %bb.45:
	movq	%r12, %rdi
	callq	_IS_I945GM
	testq	%rax, %rax
	je	LBB0_47
## %bb.46:
	movq	_i945gm_get_cdclk@GOTPCREL(%rip), %r14
	jmp	LBB0_59
LBB0_47:
	movq	%r12, %rdi
	callq	_IS_I945G
	movq	%r15, %r14
	testq	%rax, %rax
	jne	LBB0_59
## %bb.48:
	movq	%r12, %rdi
	callq	_IS_I915GM
	testq	%rax, %rax
	je	LBB0_50
## %bb.49:
	movq	_i915gm_get_cdclk@GOTPCREL(%rip), %r14
	jmp	LBB0_59
LBB0_50:
	movq	%r12, %rdi
	callq	_IS_I915G
	testq	%rax, %rax
	je	LBB0_52
## %bb.51:
	movq	_fixed_333mhz_get_cdclk@GOTPCREL(%rip), %r14
	jmp	LBB0_59
LBB0_52:
	movq	%r12, %rdi
	callq	_IS_I865G
	testq	%rax, %rax
	je	LBB0_54
## %bb.53:
	movq	_fixed_266mhz_get_cdclk@GOTPCREL(%rip), %r14
	jmp	LBB0_59
LBB0_54:
	movq	%r12, %rdi
	callq	_IS_I85X
	testq	%rax, %rax
	je	LBB0_56
## %bb.55:
	movq	_i85x_get_cdclk@GOTPCREL(%rip), %r14
	jmp	LBB0_59
LBB0_56:
	movq	%r12, %rdi
	callq	_IS_I845G
	testq	%rax, %rax
	je	LBB0_58
## %bb.57:
	movq	_fixed_200mhz_get_cdclk@GOTPCREL(%rip), %r14
	jmp	LBB0_59
LBB0_58:
	movq	%r12, %rdi
	callq	_IS_I830
	xorl	%edi, %edi
	testl	%eax, %eax
	sete	%dil
	leaq	L_.str(%rip), %rsi
	callq	_WARN
	movq	_fixed_133mhz_get_cdclk@GOTPCREL(%rip), %r14
	jmp	LBB0_59
	.cfi_endproc
                                        ## -- End function
	.comm	_icl_set_cdclk,4,2              ## @icl_set_cdclk
	.comm	_icl_modeset_calc_cdclk,8,3     ## @icl_modeset_calc_cdclk
	.comm	_cnl_set_cdclk,4,2              ## @cnl_set_cdclk
	.comm	_cnl_modeset_calc_cdclk,8,3     ## @cnl_modeset_calc_cdclk
	.comm	_bxt_set_cdclk,4,2              ## @bxt_set_cdclk
	.comm	_bxt_modeset_calc_cdclk,8,3     ## @bxt_modeset_calc_cdclk
	.comm	_skl_set_cdclk,4,2              ## @skl_set_cdclk
	.comm	_skl_modeset_calc_cdclk,8,3     ## @skl_modeset_calc_cdclk
	.comm	_bdw_set_cdclk,4,2              ## @bdw_set_cdclk
	.comm	_bdw_modeset_calc_cdclk,8,3     ## @bdw_modeset_calc_cdclk
	.comm	_chv_set_cdclk,4,2              ## @chv_set_cdclk
	.comm	_vlv_modeset_calc_cdclk,8,3     ## @vlv_modeset_calc_cdclk
	.comm	_vlv_set_cdclk,4,2              ## @vlv_set_cdclk
	.comm	_icl_get_cdclk,8,3              ## @icl_get_cdclk
	.comm	_cnl_get_cdclk,8,3              ## @cnl_get_cdclk
	.comm	_bxt_get_cdclk,8,3              ## @bxt_get_cdclk
	.comm	_skl_get_cdclk,8,3              ## @skl_get_cdclk
	.comm	_bdw_get_cdclk,8,3              ## @bdw_get_cdclk
	.comm	_hsw_get_cdclk,8,3              ## @hsw_get_cdclk
	.comm	_vlv_get_cdclk,8,3              ## @vlv_get_cdclk
	.comm	_fixed_400mhz_get_cdclk,8,3     ## @fixed_400mhz_get_cdclk
	.comm	_fixed_450mhz_get_cdclk,8,3     ## @fixed_450mhz_get_cdclk
	.comm	_gm45_get_cdclk,8,3             ## @gm45_get_cdclk
	.comm	_g33_get_cdclk,8,3              ## @g33_get_cdclk
	.comm	_i965gm_get_cdclk,8,3           ## @i965gm_get_cdclk
	.comm	_pnv_get_cdclk,8,3              ## @pnv_get_cdclk
	.comm	_i945gm_get_cdclk,8,3           ## @i945gm_get_cdclk
	.comm	_i915gm_get_cdclk,8,3           ## @i915gm_get_cdclk
	.comm	_fixed_333mhz_get_cdclk,8,3     ## @fixed_333mhz_get_cdclk
	.comm	_fixed_266mhz_get_cdclk,8,3     ## @fixed_266mhz_get_cdclk
	.comm	_i85x_get_cdclk,8,3             ## @i85x_get_cdclk
	.comm	_fixed_200mhz_get_cdclk,8,3     ## @fixed_200mhz_get_cdclk
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Unknown platform. Assuming 133 MHz CDCLK\n"

	.comm	_fixed_133mhz_get_cdclk,8,3     ## @fixed_133mhz_get_cdclk
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_intel_init_cdclk_hooks         ; -- Begin function intel_init_cdclk_hooks
	.p2align	2
_intel_init_cdclk_hooks:                ; @intel_init_cdclk_hooks
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_INTEL_GEN
	cmp	w0, #10
	b.le	LBB0_2
; %bb.1:
Lloh0:
	adrp	x8, _icl_modeset_calc_cdclk@GOTPAGE
Lloh1:
	ldr	x8, [x8, _icl_modeset_calc_cdclk@GOTPAGEOFF]
Lloh2:
	adrp	x9, _icl_set_cdclk@GOTPAGE
Lloh3:
	ldr	x9, [x9, _icl_set_cdclk@GOTPAGEOFF]
	b	LBB0_14
LBB0_2:
	mov	x0, x19
	bl	_IS_CANNONLAKE
	cbz	x0, LBB0_4
; %bb.3:
Lloh4:
	adrp	x8, _cnl_modeset_calc_cdclk@GOTPAGE
Lloh5:
	ldr	x8, [x8, _cnl_modeset_calc_cdclk@GOTPAGEOFF]
Lloh6:
	adrp	x9, _cnl_set_cdclk@GOTPAGE
Lloh7:
	ldr	x9, [x9, _cnl_set_cdclk@GOTPAGEOFF]
	b	LBB0_14
LBB0_4:
	mov	x0, x19
	bl	_IS_GEN9_LP
	cbz	x0, LBB0_6
; %bb.5:
Lloh8:
	adrp	x8, _bxt_modeset_calc_cdclk@GOTPAGE
Lloh9:
	ldr	x8, [x8, _bxt_modeset_calc_cdclk@GOTPAGEOFF]
Lloh10:
	adrp	x9, _bxt_set_cdclk@GOTPAGE
Lloh11:
	ldr	x9, [x9, _bxt_set_cdclk@GOTPAGEOFF]
	b	LBB0_14
LBB0_6:
	mov	x0, x19
	bl	_IS_GEN9_BC
	cbz	x0, LBB0_8
; %bb.7:
Lloh12:
	adrp	x8, _skl_modeset_calc_cdclk@GOTPAGE
Lloh13:
	ldr	x8, [x8, _skl_modeset_calc_cdclk@GOTPAGEOFF]
Lloh14:
	adrp	x9, _skl_set_cdclk@GOTPAGE
Lloh15:
	ldr	x9, [x9, _skl_set_cdclk@GOTPAGEOFF]
	b	LBB0_14
LBB0_8:
	mov	x0, x19
	bl	_IS_BROADWELL
	cbz	x0, LBB0_10
; %bb.9:
Lloh16:
	adrp	x8, _bdw_modeset_calc_cdclk@GOTPAGE
Lloh17:
	ldr	x8, [x8, _bdw_modeset_calc_cdclk@GOTPAGEOFF]
Lloh18:
	adrp	x9, _bdw_set_cdclk@GOTPAGE
Lloh19:
	ldr	x9, [x9, _bdw_set_cdclk@GOTPAGEOFF]
	b	LBB0_14
LBB0_10:
	mov	x0, x19
	bl	_IS_CHERRYVIEW
	cbz	x0, LBB0_12
; %bb.11:
Lloh20:
	adrp	x8, _vlv_modeset_calc_cdclk@GOTPAGE
Lloh21:
	ldr	x8, [x8, _vlv_modeset_calc_cdclk@GOTPAGEOFF]
Lloh22:
	adrp	x9, _chv_set_cdclk@GOTPAGE
Lloh23:
	ldr	x9, [x9, _chv_set_cdclk@GOTPAGEOFF]
	b	LBB0_14
LBB0_12:
	mov	x0, x19
	bl	_IS_VALLEYVIEW
	cbz	x0, LBB0_15
; %bb.13:
Lloh24:
	adrp	x8, _vlv_modeset_calc_cdclk@GOTPAGE
Lloh25:
	ldr	x8, [x8, _vlv_modeset_calc_cdclk@GOTPAGEOFF]
Lloh26:
	adrp	x9, _vlv_set_cdclk@GOTPAGE
Lloh27:
	ldr	x9, [x9, _vlv_set_cdclk@GOTPAGEOFF]
LBB0_14:
	ldr	w9, [x9]
	str	w9, [x19, #16]
	ldr	x8, [x8]
	str	x8, [x19, #8]
LBB0_15:
	mov	x0, x19
	bl	_INTEL_GEN
	cmp	w0, #10
	b.le	LBB0_17
; %bb.16:
Lloh28:
	adrp	x8, _icl_get_cdclk@GOTPAGE
Lloh29:
	ldr	x8, [x8, _icl_get_cdclk@GOTPAGEOFF]
	b	LBB0_30
LBB0_17:
	mov	x0, x19
	bl	_IS_CANNONLAKE
	cbz	x0, LBB0_19
; %bb.18:
Lloh30:
	adrp	x8, _cnl_get_cdclk@GOTPAGE
Lloh31:
	ldr	x8, [x8, _cnl_get_cdclk@GOTPAGEOFF]
	b	LBB0_30
LBB0_19:
	mov	x0, x19
	bl	_IS_GEN9_LP
	cbz	x0, LBB0_21
; %bb.20:
Lloh32:
	adrp	x8, _bxt_get_cdclk@GOTPAGE
Lloh33:
	ldr	x8, [x8, _bxt_get_cdclk@GOTPAGEOFF]
	b	LBB0_30
LBB0_21:
	mov	x0, x19
	bl	_IS_GEN9_BC
	cbz	x0, LBB0_23
; %bb.22:
Lloh34:
	adrp	x8, _skl_get_cdclk@GOTPAGE
Lloh35:
	ldr	x8, [x8, _skl_get_cdclk@GOTPAGEOFF]
	b	LBB0_30
LBB0_23:
	mov	x0, x19
	bl	_IS_BROADWELL
	cbz	x0, LBB0_25
; %bb.24:
Lloh36:
	adrp	x8, _bdw_get_cdclk@GOTPAGE
Lloh37:
	ldr	x8, [x8, _bdw_get_cdclk@GOTPAGEOFF]
	b	LBB0_30
LBB0_25:
	mov	x0, x19
	bl	_IS_HASWELL
	cbz	x0, LBB0_27
; %bb.26:
Lloh38:
	adrp	x8, _hsw_get_cdclk@GOTPAGE
Lloh39:
	ldr	x8, [x8, _hsw_get_cdclk@GOTPAGEOFF]
	b	LBB0_30
LBB0_27:
	mov	x0, x19
	bl	_IS_VALLEYVIEW
	cbnz	x0, LBB0_29
; %bb.28:
	mov	x0, x19
	bl	_IS_CHERRYVIEW
	cbz	x0, LBB0_31
LBB0_29:
Lloh40:
	adrp	x8, _vlv_get_cdclk@GOTPAGE
Lloh41:
	ldr	x8, [x8, _vlv_get_cdclk@GOTPAGEOFF]
LBB0_30:
	ldr	x8, [x8]
	str	x8, [x19]
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_31:
	mov	x0, x19
	mov	w1, #6
	bl	_IS_GEN
	cbnz	x0, LBB0_33
; %bb.32:
	mov	x0, x19
	bl	_IS_IVYBRIDGE
	cbz	x0, LBB0_34
LBB0_33:
Lloh42:
	adrp	x8, _fixed_400mhz_get_cdclk@GOTPAGE
Lloh43:
	ldr	x8, [x8, _fixed_400mhz_get_cdclk@GOTPAGEOFF]
	b	LBB0_30
LBB0_34:
	mov	x0, x19
	mov	w1, #5
	bl	_IS_GEN
	cbz	x0, LBB0_36
; %bb.35:
Lloh44:
	adrp	x8, _fixed_450mhz_get_cdclk@GOTPAGE
Lloh45:
	ldr	x8, [x8, _fixed_450mhz_get_cdclk@GOTPAGEOFF]
	b	LBB0_30
LBB0_36:
	mov	x0, x19
	bl	_IS_GM45
	cbz	x0, LBB0_38
; %bb.37:
Lloh46:
	adrp	x8, _gm45_get_cdclk@GOTPAGE
Lloh47:
	ldr	x8, [x8, _gm45_get_cdclk@GOTPAGEOFF]
	b	LBB0_30
LBB0_38:
	mov	x0, x19
	bl	_IS_G45
	cbz	x0, LBB0_40
LBB0_39:
Lloh48:
	adrp	x8, _g33_get_cdclk@GOTPAGE
Lloh49:
	ldr	x8, [x8, _g33_get_cdclk@GOTPAGEOFF]
	b	LBB0_30
LBB0_40:
	mov	x0, x19
	bl	_IS_I965GM
	cbz	x0, LBB0_42
; %bb.41:
Lloh50:
	adrp	x8, _i965gm_get_cdclk@GOTPAGE
Lloh51:
	ldr	x8, [x8, _i965gm_get_cdclk@GOTPAGEOFF]
	b	LBB0_30
LBB0_42:
	mov	x0, x19
	bl	_IS_I965G
	cbnz	x0, LBB0_33
; %bb.43:
	mov	x0, x19
	bl	_IS_PINEVIEW
	cbz	x0, LBB0_45
; %bb.44:
Lloh52:
	adrp	x8, _pnv_get_cdclk@GOTPAGE
Lloh53:
	ldr	x8, [x8, _pnv_get_cdclk@GOTPAGEOFF]
	b	LBB0_30
LBB0_45:
	mov	x0, x19
	bl	_IS_G33
	cbnz	x0, LBB0_39
; %bb.46:
	mov	x0, x19
	bl	_IS_I945GM
	cbz	x0, LBB0_48
; %bb.47:
Lloh54:
	adrp	x8, _i945gm_get_cdclk@GOTPAGE
Lloh55:
	ldr	x8, [x8, _i945gm_get_cdclk@GOTPAGEOFF]
	b	LBB0_30
LBB0_48:
	mov	x0, x19
	bl	_IS_I945G
	cbnz	x0, LBB0_33
; %bb.49:
	mov	x0, x19
	bl	_IS_I915GM
	cbz	x0, LBB0_51
; %bb.50:
Lloh56:
	adrp	x8, _i915gm_get_cdclk@GOTPAGE
Lloh57:
	ldr	x8, [x8, _i915gm_get_cdclk@GOTPAGEOFF]
	b	LBB0_30
LBB0_51:
	mov	x0, x19
	bl	_IS_I915G
	cbz	x0, LBB0_53
; %bb.52:
Lloh58:
	adrp	x8, _fixed_333mhz_get_cdclk@GOTPAGE
Lloh59:
	ldr	x8, [x8, _fixed_333mhz_get_cdclk@GOTPAGEOFF]
	b	LBB0_30
LBB0_53:
	mov	x0, x19
	bl	_IS_I865G
	cbz	x0, LBB0_55
; %bb.54:
Lloh60:
	adrp	x8, _fixed_266mhz_get_cdclk@GOTPAGE
Lloh61:
	ldr	x8, [x8, _fixed_266mhz_get_cdclk@GOTPAGEOFF]
	b	LBB0_30
LBB0_55:
	mov	x0, x19
	bl	_IS_I85X
	cbz	x0, LBB0_57
; %bb.56:
Lloh62:
	adrp	x8, _i85x_get_cdclk@GOTPAGE
Lloh63:
	ldr	x8, [x8, _i85x_get_cdclk@GOTPAGEOFF]
	b	LBB0_30
LBB0_57:
	mov	x0, x19
	bl	_IS_I845G
	cbz	x0, LBB0_59
; %bb.58:
Lloh64:
	adrp	x8, _fixed_200mhz_get_cdclk@GOTPAGE
Lloh65:
	ldr	x8, [x8, _fixed_200mhz_get_cdclk@GOTPAGEOFF]
	b	LBB0_30
LBB0_59:
	mov	x0, x19
	bl	_IS_I830
	cmp	w0, #0
	cset	w0, eq
Lloh66:
	adrp	x1, l_.str@PAGE
Lloh67:
	add	x1, x1, l_.str@PAGEOFF
	bl	_WARN
Lloh68:
	adrp	x8, _fixed_133mhz_get_cdclk@GOTPAGE
Lloh69:
	ldr	x8, [x8, _fixed_133mhz_get_cdclk@GOTPAGEOFF]
	b	LBB0_30
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh54, Lloh55
	.loh AdrpLdrGot	Lloh56, Lloh57
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGot	Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh62, Lloh63
	.loh AdrpLdrGot	Lloh64, Lloh65
	.loh AdrpLdrGot	Lloh68, Lloh69
	.loh AdrpAdd	Lloh66, Lloh67
	.cfi_endproc
                                        ; -- End function
	.comm	_icl_set_cdclk,4,2              ; @icl_set_cdclk
	.comm	_icl_modeset_calc_cdclk,8,3     ; @icl_modeset_calc_cdclk
	.comm	_cnl_set_cdclk,4,2              ; @cnl_set_cdclk
	.comm	_cnl_modeset_calc_cdclk,8,3     ; @cnl_modeset_calc_cdclk
	.comm	_bxt_set_cdclk,4,2              ; @bxt_set_cdclk
	.comm	_bxt_modeset_calc_cdclk,8,3     ; @bxt_modeset_calc_cdclk
	.comm	_skl_set_cdclk,4,2              ; @skl_set_cdclk
	.comm	_skl_modeset_calc_cdclk,8,3     ; @skl_modeset_calc_cdclk
	.comm	_bdw_set_cdclk,4,2              ; @bdw_set_cdclk
	.comm	_bdw_modeset_calc_cdclk,8,3     ; @bdw_modeset_calc_cdclk
	.comm	_chv_set_cdclk,4,2              ; @chv_set_cdclk
	.comm	_vlv_modeset_calc_cdclk,8,3     ; @vlv_modeset_calc_cdclk
	.comm	_vlv_set_cdclk,4,2              ; @vlv_set_cdclk
	.comm	_icl_get_cdclk,8,3              ; @icl_get_cdclk
	.comm	_cnl_get_cdclk,8,3              ; @cnl_get_cdclk
	.comm	_bxt_get_cdclk,8,3              ; @bxt_get_cdclk
	.comm	_skl_get_cdclk,8,3              ; @skl_get_cdclk
	.comm	_bdw_get_cdclk,8,3              ; @bdw_get_cdclk
	.comm	_hsw_get_cdclk,8,3              ; @hsw_get_cdclk
	.comm	_vlv_get_cdclk,8,3              ; @vlv_get_cdclk
	.comm	_fixed_400mhz_get_cdclk,8,3     ; @fixed_400mhz_get_cdclk
	.comm	_fixed_450mhz_get_cdclk,8,3     ; @fixed_450mhz_get_cdclk
	.comm	_gm45_get_cdclk,8,3             ; @gm45_get_cdclk
	.comm	_g33_get_cdclk,8,3              ; @g33_get_cdclk
	.comm	_i965gm_get_cdclk,8,3           ; @i965gm_get_cdclk
	.comm	_pnv_get_cdclk,8,3              ; @pnv_get_cdclk
	.comm	_i945gm_get_cdclk,8,3           ; @i945gm_get_cdclk
	.comm	_i915gm_get_cdclk,8,3           ; @i915gm_get_cdclk
	.comm	_fixed_333mhz_get_cdclk,8,3     ; @fixed_333mhz_get_cdclk
	.comm	_fixed_266mhz_get_cdclk,8,3     ; @fixed_266mhz_get_cdclk
	.comm	_i85x_get_cdclk,8,3             ; @i85x_get_cdclk
	.comm	_fixed_200mhz_get_cdclk,8,3     ; @fixed_200mhz_get_cdclk
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Unknown platform. Assuming 133 MHz CDCLK\n"

	.comm	_fixed_133mhz_get_cdclk,8,3     ; @fixed_133mhz_get_cdclk
.subsections_via_symbols
