	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function anx78xx_tx_initialization
_anx78xx_tx_initialization:             ## @anx78xx_tx_initialization
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r13
	movq	(%rdi), %rax
	movq	_I2C_IDX_TX_P0@GOTPCREL(%rip), %r12
	movq	(%r12), %rcx
	movl	(%rax,%rcx,4), %edi
	movq	_SP_DP_AUX_CH_CTRL2_REG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movl	$48, %edx
	callq	_regmap_write
	testl	%eax, %eax
	jne	LBB0_17
## %bb.1:
	movq	(%r13), %rax
	movq	(%r12), %rcx
	movl	(%rax,%rcx,4), %edi
	movl	(%rbx), %esi
	movl	$8, %edx
	callq	_anx78xx_set_bits
	testl	%eax, %eax
	jne	LBB0_17
## %bb.2:
	movq	(%r13), %rax
	movq	(%r12), %rcx
	movl	(%rax,%rcx,4), %edi
	movq	_SP_DP_HDCP_CTRL_REG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_SP_AUTO_EN@GOTPCREL(%rip), %rax
	movq	_SP_AUTO_START@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	callq	_anx78xx_clear_bits
	testl	%eax, %eax
	jne	LBB0_17
## %bb.3:
	movq	(%r13), %rax
	movq	(%r12), %rcx
	movl	(%rax,%rcx,4), %r14d
	movq	_otp_key_protect@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	%r15d, %edi
	callq	_ARRAY_SIZE
	movl	%r14d, %edi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_regmap_multi_reg_write
	testl	%eax, %eax
	jne	LBB0_17
## %bb.4:
	movq	(%r13), %rax
	movq	(%r12), %rcx
	movl	(%rax,%rcx,4), %edi
	movq	_SP_HDCP_KEY_COMMAND_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SP_DISABLE_SYNC_HDCP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_anx78xx_set_bits
	testl	%eax, %eax
	jne	LBB0_17
## %bb.5:
	movq	(%r13), %rax
	movq	_I2C_IDX_TX_P2@GOTPCREL(%rip), %r14
	movq	(%r14), %rcx
	movl	(%rax,%rcx,4), %edi
	movq	_SP_VID_CTRL8_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SP_VID_VRES_TH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_regmap_write
	testl	%eax, %eax
	jne	LBB0_17
## %bb.6:
	movq	(%r13), %rax
	movq	(%r12), %rcx
	movl	(%rax,%rcx,4), %edi
	movq	_SP_HDCP_AUTO_TIMER_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	testl	%eax, %eax
	jne	LBB0_17
## %bb.7:
	movq	(%r13), %rax
	movq	(%r12), %rcx
	movl	(%rax,%rcx,4), %edi
	movl	(%rbx), %esi
	movq	_SP_LINK_POLLING@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_anx78xx_set_bits
	testl	%eax, %eax
	jne	LBB0_17
## %bb.8:
	movq	(%r13), %rax
	movq	(%r12), %rcx
	movl	(%rax,%rcx,4), %edi
	movq	_SP_DP_LINK_DEBUG_CTRL_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SP_M_VID_DEBUG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_anx78xx_set_bits
	testl	%eax, %eax
	jne	LBB0_17
## %bb.9:
	movq	(%r13), %rax
	movq	(%r14), %rcx
	movl	(%rax,%rcx,4), %edi
	movq	_SP_ANALOG_DEBUG2_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SP_POWERON_TIME_1P5MS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_anx78xx_set_bits
	testl	%eax, %eax
	jne	LBB0_17
## %bb.10:
	movq	%r13, %rdi
	callq	_anx78xx_xtal_clk_sel
	testl	%eax, %eax
	jne	LBB0_17
## %bb.11:
	movq	(%r13), %rax
	movq	(%r12), %rcx
	movl	(%rax,%rcx,4), %edi
	movq	_SP_AUX_DEFER_CTRL_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SP_DEFER_CTRL_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	orl	$12, %edx
	callq	_regmap_write
	testl	%eax, %eax
	jne	LBB0_17
## %bb.12:
	movq	(%r13), %rax
	movq	(%r12), %rcx
	movl	(%rax,%rcx,4), %edi
	movq	_SP_DP_POLLING_CTRL_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SP_AUTO_POLLING_DISABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_anx78xx_set_bits
	testl	%eax, %eax
	jne	LBB0_17
## %bb.13:
	movq	(%r13), %rax
	movq	(%r12), %rcx
	movl	(%rax,%rcx,4), %edi
	movq	_SP_HDCP_LINK_CHECK_TIMER_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$29, %edx
	callq	_regmap_write
	testl	%eax, %eax
	jne	LBB0_17
## %bb.14:
	movq	(%r13), %rax
	movq	(%r12), %rcx
	movl	(%rax,%rcx,4), %edi
	movq	_SP_DP_MISC_CTRL_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SP_EQ_TRAINING_LOOP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_anx78xx_set_bits
	testl	%eax, %eax
	jne	LBB0_17
## %bb.15:
	movq	(%r13), %rax
	movq	(%r12), %rcx
	movl	(%rax,%rcx,4), %edi
	movq	_SP_DP_ANALOG_POWER_DOWN_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SP_CH0_PD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_anx78xx_set_bits
	testl	%eax, %eax
	jne	LBB0_17
## %bb.16:
	movq	%r13, %rdi
	callq	_anx78xx_link_phy_initialization
	testl	%eax, %eax
	je	LBB0_18
LBB0_17:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_18:
	movq	(%r13), %rax
	movq	(%r12), %rcx
	movl	(%rax,%rcx,4), %edi
	movq	_SP_DP_M_CALCULATION_CTRL_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SP_M_GEN_CLK_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_anx78xx_set_bits               ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_I2C_IDX_TX_P0,8,3              ## @I2C_IDX_TX_P0
	.comm	_SP_DP_AUX_CH_CTRL2_REG,4,2     ## @SP_DP_AUX_CH_CTRL2_REG
	.comm	_SP_DP_HDCP_CTRL_REG,4,2        ## @SP_DP_HDCP_CTRL_REG
	.comm	_SP_AUTO_EN,4,2                 ## @SP_AUTO_EN
	.comm	_SP_AUTO_START,4,2              ## @SP_AUTO_START
	.comm	_otp_key_protect,4,2            ## @otp_key_protect
	.comm	_SP_HDCP_KEY_COMMAND_REG,4,2    ## @SP_HDCP_KEY_COMMAND_REG
	.comm	_SP_DISABLE_SYNC_HDCP,4,2       ## @SP_DISABLE_SYNC_HDCP
	.comm	_I2C_IDX_TX_P2,8,3              ## @I2C_IDX_TX_P2
	.comm	_SP_VID_CTRL8_REG,4,2           ## @SP_VID_CTRL8_REG
	.comm	_SP_VID_VRES_TH,4,2             ## @SP_VID_VRES_TH
	.comm	_SP_HDCP_AUTO_TIMER_REG,4,2     ## @SP_HDCP_AUTO_TIMER_REG
	.comm	_SP_LINK_POLLING,4,2            ## @SP_LINK_POLLING
	.comm	_SP_DP_LINK_DEBUG_CTRL_REG,4,2  ## @SP_DP_LINK_DEBUG_CTRL_REG
	.comm	_SP_M_VID_DEBUG,4,2             ## @SP_M_VID_DEBUG
	.comm	_SP_ANALOG_DEBUG2_REG,4,2       ## @SP_ANALOG_DEBUG2_REG
	.comm	_SP_POWERON_TIME_1P5MS,4,2      ## @SP_POWERON_TIME_1P5MS
	.comm	_SP_AUX_DEFER_CTRL_REG,4,2      ## @SP_AUX_DEFER_CTRL_REG
	.comm	_SP_DEFER_CTRL_EN,4,2           ## @SP_DEFER_CTRL_EN
	.comm	_SP_DP_POLLING_CTRL_REG,4,2     ## @SP_DP_POLLING_CTRL_REG
	.comm	_SP_AUTO_POLLING_DISABLE,4,2    ## @SP_AUTO_POLLING_DISABLE
	.comm	_SP_HDCP_LINK_CHECK_TIMER_REG,4,2 ## @SP_HDCP_LINK_CHECK_TIMER_REG
	.comm	_SP_DP_MISC_CTRL_REG,4,2        ## @SP_DP_MISC_CTRL_REG
	.comm	_SP_EQ_TRAINING_LOOP,4,2        ## @SP_EQ_TRAINING_LOOP
	.comm	_SP_DP_ANALOG_POWER_DOWN_REG,4,2 ## @SP_DP_ANALOG_POWER_DOWN_REG
	.comm	_SP_CH0_PD,4,2                  ## @SP_CH0_PD
	.comm	_SP_DP_M_CALCULATION_CTRL_REG,4,2 ## @SP_DP_M_CALCULATION_CTRL_REG
	.comm	_SP_M_GEN_CLK_SEL,4,2           ## @SP_M_GEN_CLK_SEL
	.no_dead_strip	_anx78xx_tx_initialization
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function anx78xx_tx_initialization
_anx78xx_tx_initialization:             ; @anx78xx_tx_initialization
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	x8, [x0]
Lloh0:
	adrp	x22, _I2C_IDX_TX_P0@GOTPAGE
Lloh1:
	ldr	x22, [x22, _I2C_IDX_TX_P0@GOTPAGEOFF]
	ldr	x9, [x22]
	ldr	w0, [x8, x9, lsl #2]
Lloh2:
	adrp	x20, _SP_DP_AUX_CH_CTRL2_REG@GOTPAGE
Lloh3:
	ldr	x20, [x20, _SP_DP_AUX_CH_CTRL2_REG@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	w2, #48
	bl	_regmap_write
	cbnz	w0, LBB0_17
; %bb.1:
	ldr	x8, [x19]
	ldr	x9, [x22]
	ldr	w0, [x8, x9, lsl #2]
	ldr	w1, [x20]
	mov	w2, #8
	bl	_anx78xx_set_bits
	cbnz	w0, LBB0_17
; %bb.2:
	ldr	x8, [x19]
	ldr	x9, [x22]
	ldr	w0, [x8, x9, lsl #2]
Lloh4:
	adrp	x23, _SP_DP_HDCP_CTRL_REG@GOTPAGE
Lloh5:
	ldr	x23, [x23, _SP_DP_HDCP_CTRL_REG@GOTPAGEOFF]
Lloh6:
	adrp	x8, _SP_AUTO_EN@GOTPAGE
Lloh7:
	ldr	x8, [x8, _SP_AUTO_EN@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh8:
	ldr	w8, [x8]
Lloh9:
	adrp	x9, _SP_AUTO_START@GOTPAGE
Lloh10:
	ldr	x9, [x9, _SP_AUTO_START@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	orr	w2, w9, w8
	bl	_anx78xx_clear_bits
	cbnz	w0, LBB0_17
; %bb.3:
	ldr	x8, [x19]
	ldr	x9, [x22]
	ldr	w20, [x8, x9, lsl #2]
Lloh12:
	adrp	x8, _otp_key_protect@GOTPAGE
Lloh13:
	ldr	x8, [x8, _otp_key_protect@GOTPAGEOFF]
Lloh14:
	ldr	w21, [x8]
	mov	x0, x21
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_regmap_multi_reg_write
	cbnz	w0, LBB0_17
; %bb.4:
	ldr	x8, [x19]
	ldr	x9, [x22]
	ldr	w0, [x8, x9, lsl #2]
Lloh15:
	adrp	x8, _SP_HDCP_KEY_COMMAND_REG@GOTPAGE
Lloh16:
	ldr	x8, [x8, _SP_HDCP_KEY_COMMAND_REG@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
Lloh18:
	adrp	x8, _SP_DISABLE_SYNC_HDCP@GOTPAGE
Lloh19:
	ldr	x8, [x8, _SP_DISABLE_SYNC_HDCP@GOTPAGEOFF]
Lloh20:
	ldr	w2, [x8]
	bl	_anx78xx_set_bits
	cbnz	w0, LBB0_17
; %bb.5:
	ldr	x8, [x19]
Lloh21:
	adrp	x20, _I2C_IDX_TX_P2@GOTPAGE
Lloh22:
	ldr	x20, [x20, _I2C_IDX_TX_P2@GOTPAGEOFF]
	ldr	x9, [x20]
	ldr	w0, [x8, x9, lsl #2]
Lloh23:
	adrp	x8, _SP_VID_CTRL8_REG@GOTPAGE
Lloh24:
	ldr	x8, [x8, _SP_VID_CTRL8_REG@GOTPAGEOFF]
Lloh25:
	ldr	w1, [x8]
Lloh26:
	adrp	x8, _SP_VID_VRES_TH@GOTPAGE
Lloh27:
	ldr	x8, [x8, _SP_VID_VRES_TH@GOTPAGEOFF]
Lloh28:
	ldr	w2, [x8]
	bl	_regmap_write
	cbnz	w0, LBB0_17
; %bb.6:
	ldr	x8, [x19]
	ldr	x9, [x22]
	ldr	w0, [x8, x9, lsl #2]
Lloh29:
	adrp	x8, _SP_HDCP_AUTO_TIMER_REG@GOTPAGE
Lloh30:
	ldr	x8, [x8, _SP_HDCP_AUTO_TIMER_REG@GOTPAGEOFF]
Lloh31:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_regmap_write
	cbnz	w0, LBB0_17
; %bb.7:
	ldr	x8, [x19]
	ldr	x9, [x22]
	ldr	w0, [x8, x9, lsl #2]
	ldr	w1, [x23]
Lloh32:
	adrp	x8, _SP_LINK_POLLING@GOTPAGE
Lloh33:
	ldr	x8, [x8, _SP_LINK_POLLING@GOTPAGEOFF]
Lloh34:
	ldr	w2, [x8]
	bl	_anx78xx_set_bits
	cbnz	w0, LBB0_17
; %bb.8:
	ldr	x8, [x19]
	ldr	x9, [x22]
	ldr	w0, [x8, x9, lsl #2]
Lloh35:
	adrp	x8, _SP_DP_LINK_DEBUG_CTRL_REG@GOTPAGE
Lloh36:
	ldr	x8, [x8, _SP_DP_LINK_DEBUG_CTRL_REG@GOTPAGEOFF]
Lloh37:
	ldr	w1, [x8]
Lloh38:
	adrp	x8, _SP_M_VID_DEBUG@GOTPAGE
Lloh39:
	ldr	x8, [x8, _SP_M_VID_DEBUG@GOTPAGEOFF]
Lloh40:
	ldr	w2, [x8]
	bl	_anx78xx_set_bits
	cbnz	w0, LBB0_17
; %bb.9:
	ldr	x8, [x19]
	ldr	x9, [x20]
	ldr	w0, [x8, x9, lsl #2]
Lloh41:
	adrp	x8, _SP_ANALOG_DEBUG2_REG@GOTPAGE
Lloh42:
	ldr	x8, [x8, _SP_ANALOG_DEBUG2_REG@GOTPAGEOFF]
Lloh43:
	ldr	w1, [x8]
Lloh44:
	adrp	x8, _SP_POWERON_TIME_1P5MS@GOTPAGE
Lloh45:
	ldr	x8, [x8, _SP_POWERON_TIME_1P5MS@GOTPAGEOFF]
Lloh46:
	ldr	w2, [x8]
	bl	_anx78xx_set_bits
	cbnz	w0, LBB0_17
; %bb.10:
	mov	x0, x19
	bl	_anx78xx_xtal_clk_sel
	cbnz	w0, LBB0_17
; %bb.11:
	ldr	x8, [x19]
	ldr	x9, [x22]
	ldr	w0, [x8, x9, lsl #2]
Lloh47:
	adrp	x8, _SP_AUX_DEFER_CTRL_REG@GOTPAGE
Lloh48:
	ldr	x8, [x8, _SP_AUX_DEFER_CTRL_REG@GOTPAGEOFF]
Lloh49:
	ldr	w1, [x8]
Lloh50:
	adrp	x8, _SP_DEFER_CTRL_EN@GOTPAGE
Lloh51:
	ldr	x8, [x8, _SP_DEFER_CTRL_EN@GOTPAGEOFF]
Lloh52:
	ldr	w8, [x8]
	orr	w2, w8, #0xc
	bl	_regmap_write
	cbnz	w0, LBB0_17
; %bb.12:
	ldr	x8, [x19]
	ldr	x9, [x22]
	ldr	w0, [x8, x9, lsl #2]
Lloh53:
	adrp	x8, _SP_DP_POLLING_CTRL_REG@GOTPAGE
Lloh54:
	ldr	x8, [x8, _SP_DP_POLLING_CTRL_REG@GOTPAGEOFF]
Lloh55:
	ldr	w1, [x8]
Lloh56:
	adrp	x8, _SP_AUTO_POLLING_DISABLE@GOTPAGE
Lloh57:
	ldr	x8, [x8, _SP_AUTO_POLLING_DISABLE@GOTPAGEOFF]
Lloh58:
	ldr	w2, [x8]
	bl	_anx78xx_set_bits
	cbnz	w0, LBB0_17
; %bb.13:
	ldr	x8, [x19]
	ldr	x9, [x22]
	ldr	w0, [x8, x9, lsl #2]
Lloh59:
	adrp	x8, _SP_HDCP_LINK_CHECK_TIMER_REG@GOTPAGE
Lloh60:
	ldr	x8, [x8, _SP_HDCP_LINK_CHECK_TIMER_REG@GOTPAGEOFF]
Lloh61:
	ldr	w1, [x8]
	mov	w2, #29
	bl	_regmap_write
	cbnz	w0, LBB0_17
; %bb.14:
	ldr	x8, [x19]
	ldr	x9, [x22]
	ldr	w0, [x8, x9, lsl #2]
Lloh62:
	adrp	x8, _SP_DP_MISC_CTRL_REG@GOTPAGE
Lloh63:
	ldr	x8, [x8, _SP_DP_MISC_CTRL_REG@GOTPAGEOFF]
Lloh64:
	ldr	w1, [x8]
Lloh65:
	adrp	x8, _SP_EQ_TRAINING_LOOP@GOTPAGE
Lloh66:
	ldr	x8, [x8, _SP_EQ_TRAINING_LOOP@GOTPAGEOFF]
Lloh67:
	ldr	w2, [x8]
	bl	_anx78xx_set_bits
	cbnz	w0, LBB0_17
; %bb.15:
	ldr	x8, [x19]
	ldr	x9, [x22]
	ldr	w0, [x8, x9, lsl #2]
Lloh68:
	adrp	x8, _SP_DP_ANALOG_POWER_DOWN_REG@GOTPAGE
Lloh69:
	ldr	x8, [x8, _SP_DP_ANALOG_POWER_DOWN_REG@GOTPAGEOFF]
Lloh70:
	ldr	w1, [x8]
Lloh71:
	adrp	x8, _SP_CH0_PD@GOTPAGE
Lloh72:
	ldr	x8, [x8, _SP_CH0_PD@GOTPAGEOFF]
Lloh73:
	ldr	w2, [x8]
	bl	_anx78xx_set_bits
	cbnz	w0, LBB0_17
; %bb.16:
	mov	x0, x19
	bl	_anx78xx_link_phy_initialization
	cbz	w0, LBB0_18
LBB0_17:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_18:
	ldr	x8, [x19]
	ldr	x9, [x22]
	ldr	w0, [x8, x9, lsl #2]
Lloh74:
	adrp	x8, _SP_DP_M_CALCULATION_CTRL_REG@GOTPAGE
Lloh75:
	ldr	x8, [x8, _SP_DP_M_CALCULATION_CTRL_REG@GOTPAGEOFF]
Lloh76:
	ldr	w1, [x8]
Lloh77:
	adrp	x8, _SP_M_GEN_CLK_SEL@GOTPAGE
Lloh78:
	ldr	x8, [x8, _SP_M_GEN_CLK_SEL@GOTPAGEOFF]
Lloh79:
	ldr	w2, [x8]
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_anx78xx_set_bits
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.cfi_endproc
                                        ; -- End function
	.comm	_I2C_IDX_TX_P0,8,3              ; @I2C_IDX_TX_P0
	.comm	_SP_DP_AUX_CH_CTRL2_REG,4,2     ; @SP_DP_AUX_CH_CTRL2_REG
	.comm	_SP_DP_HDCP_CTRL_REG,4,2        ; @SP_DP_HDCP_CTRL_REG
	.comm	_SP_AUTO_EN,4,2                 ; @SP_AUTO_EN
	.comm	_SP_AUTO_START,4,2              ; @SP_AUTO_START
	.comm	_otp_key_protect,4,2            ; @otp_key_protect
	.comm	_SP_HDCP_KEY_COMMAND_REG,4,2    ; @SP_HDCP_KEY_COMMAND_REG
	.comm	_SP_DISABLE_SYNC_HDCP,4,2       ; @SP_DISABLE_SYNC_HDCP
	.comm	_I2C_IDX_TX_P2,8,3              ; @I2C_IDX_TX_P2
	.comm	_SP_VID_CTRL8_REG,4,2           ; @SP_VID_CTRL8_REG
	.comm	_SP_VID_VRES_TH,4,2             ; @SP_VID_VRES_TH
	.comm	_SP_HDCP_AUTO_TIMER_REG,4,2     ; @SP_HDCP_AUTO_TIMER_REG
	.comm	_SP_LINK_POLLING,4,2            ; @SP_LINK_POLLING
	.comm	_SP_DP_LINK_DEBUG_CTRL_REG,4,2  ; @SP_DP_LINK_DEBUG_CTRL_REG
	.comm	_SP_M_VID_DEBUG,4,2             ; @SP_M_VID_DEBUG
	.comm	_SP_ANALOG_DEBUG2_REG,4,2       ; @SP_ANALOG_DEBUG2_REG
	.comm	_SP_POWERON_TIME_1P5MS,4,2      ; @SP_POWERON_TIME_1P5MS
	.comm	_SP_AUX_DEFER_CTRL_REG,4,2      ; @SP_AUX_DEFER_CTRL_REG
	.comm	_SP_DEFER_CTRL_EN,4,2           ; @SP_DEFER_CTRL_EN
	.comm	_SP_DP_POLLING_CTRL_REG,4,2     ; @SP_DP_POLLING_CTRL_REG
	.comm	_SP_AUTO_POLLING_DISABLE,4,2    ; @SP_AUTO_POLLING_DISABLE
	.comm	_SP_HDCP_LINK_CHECK_TIMER_REG,4,2 ; @SP_HDCP_LINK_CHECK_TIMER_REG
	.comm	_SP_DP_MISC_CTRL_REG,4,2        ; @SP_DP_MISC_CTRL_REG
	.comm	_SP_EQ_TRAINING_LOOP,4,2        ; @SP_EQ_TRAINING_LOOP
	.comm	_SP_DP_ANALOG_POWER_DOWN_REG,4,2 ; @SP_DP_ANALOG_POWER_DOWN_REG
	.comm	_SP_CH0_PD,4,2                  ; @SP_CH0_PD
	.comm	_SP_DP_M_CALCULATION_CTRL_REG,4,2 ; @SP_DP_M_CALCULATION_CTRL_REG
	.comm	_SP_M_GEN_CLK_SEL,4,2           ; @SP_M_GEN_CLK_SEL
	.no_dead_strip	_anx78xx_tx_initialization
.subsections_via_symbols
