	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v1_0_start_dpg_mode
_vcn_v1_0_start_dpg_mode:               ## @vcn_v1_0_start_dpg_mode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	(%rdi), %rax
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
	movq	%rdi, %rbx
	movq	%rdi, -48(%rbp)                 ## 8-byte Spill
	callq	_vcn_1_0_enable_static_power_gating
	movq	_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	%rax, %r15
	movq	_mmUVD_POWER_STATUS@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_UVD_POWER_STATUS__UVD_PG_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_POWER_STATUS__UVD_PG_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r15), %edi
	movl	(%r14), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_vcn_v1_0_clock_gating_dpg_mode
	movq	_UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$255, %eax
	shll	%cl, %eax
	movq	_UVD_VCPU_CNTL__CLK_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r15), %edi
	movq	_mmUVD_VCPU_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r15), %edi
	movq	_mmUVD_MASTINT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_UVD_MASTINT_EN__VCPU_EN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r15), %edi
	movq	%r15, %r14
	movq	_mmUVD_LMI_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$8, %eax
	shll	%cl, %eax
	movl	$8, %r12d
	movq	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPCREL(%rip), %rsi
	movq	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPCREL(%rip), %rcx
	movq	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPCREL(%rip), %rbx
	movq	_UVD_LMI_CTRL__REQ_MODE_MASK@GOTPCREL(%rip), %r9
	movq	_UVD_LMI_CTRL__CRC_RESET_MASK@GOTPCREL(%rip), %r8
	orl	(%rsi), %eax
	orl	(%rcx), %eax
	orl	(%rbx), %eax
	orl	(%r9), %eax
	orl	(%r8), %eax
	movq	_UVD_LMI_CTRL__MASK_MC_URGENT_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	orl	$1048576, %eax                  ## imm = 0x100000
	xorl	%esi, %esi
	movl	%eax, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r15), %edi
	movq	_mmUVD_LMI_SWAP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r15), %edi
	movq	_mmUVD_MPC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %r15d
	movl	$2, %eax
	shll	%cl, %eax
	xorl	%esi, %esi
	movl	%eax, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r14), %edi
	movq	_mmUVD_MPC_SET_MUXA0@GOTPCREL(%rip), %rax
	movq	_UVD_MPC_SET_MUXA0__VARA_2__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %esi
	shll	%cl, %esi
	movl	(%rax), %edx
	movq	_UVD_MPC_SET_MUXA0__VARA_1__SHIFT@GOTPCREL(%rip), %rax
	movq	_UVD_MPC_SET_MUXA0__VARA_3__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$3, %ebx
	shll	%cl, %ebx
	movb	(%rax), %al
	btsl	%eax, %esi
	movq	_UVD_MPC_SET_MUXA0__VARA_4__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$4, %eax
	shll	%cl, %eax
	movl	$3, %r14d
	movl	$4, %r13d
	orl	%ebx, %eax
	orl	%esi, %eax
	xorl	%esi, %esi
	movl	%eax, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movq	_UVD@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_UVD_MPC_SET_MUXB0__VARB_2__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %eax
	shll	%cl, %eax
	movq	_UVD_MPC_SET_MUXB0__VARB_3__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r14d
	movq	_mmUVD_MPC_SET_MUXB0@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_UVD_MPC_SET_MUXB0__VARB_4__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movq	_UVD_MPC_SET_MUXB0__VARB_1__SHIFT@GOTPCREL(%rip), %rsi
	shll	%cl, %r13d
	movb	(%rsi), %cl
	btsl	%ecx, %eax
	orl	%r14d, %r13d
	orl	%eax, %r13d
	xorl	%esi, %esi
	movl	%r13d, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movq	%rbx, %r14
	movl	(%rbx), %edi
	movq	_mmUVD_MPC_SET_MUX@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_UVD_MPC_SET_MUX__SET_1__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	movq	_UVD_MPC_SET_MUX__SET_2__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r15d
	btsl	%eax, %r15d
	xorl	%esi, %esi
	movl	%r15d, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	callq	_vcn_v1_0_mc_resume_dpg_mode
	movl	(%r14), %edi
	movq	_mmUVD_REG_XX_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	movl	$16, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r14), %edi
	movq	_mmUVD_RBC_XX_IB_REG_CHECK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	movl	$3, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r14), %edi
	movq	_mmUVD_SOFT_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r14), %edi
	movq	_mmUVD_LMI_CTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$31, %eax
	shll	%cl, %eax
	xorl	%esi, %esi
	movl	%eax, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r14), %edi
	movq	_mmUVD_MASTINT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_UVD_MASTINT_EN__VCPU_EN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%esi, %esi
	movl	%ecx, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movq	%rbx, %rdi
	movl	$1, %esi
	callq	_vcn_v1_0_clock_gating_dpg_mode
	movq	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r12d
	movl	(%r14), %edi
	movq	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
	movq	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
	movq	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
	movq	_UVD_LMI_CTRL__REQ_MODE_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
	movq	_UVD_LMI_CTRL__CRC_RESET_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
	movq	_mmUVD_LMI_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_UVD_LMI_CTRL__MASK_MC_URGENT_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
	orl	$1048576, %r12d                 ## imm = 0x100000
	xorl	%esi, %esi
	movl	%r12d, %ecx
	movl	$-1, %r8d
	movl	$1, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	8(%rbx), %ebx
	movl	(%r14), %edi
	movq	_mmUVD_JPEG_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	movl	%ebx, %ecx
	movl	$-1, %r8d
	movl	$1, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r14), %edi
	movq	_mmUVD_JPEG_UV_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	movl	%ebx, %ecx
	movl	$-1, %r8d
	movl	$1, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r14), %edi
	movq	_mmUVD_SYS_INT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_UVD_SYS_INT_EN__UVD_JRBC_EN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%esi, %esi
	movl	$-1, %r8d
	movl	$1, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movq	-56(%rbp), %r13                 ## 8-byte Reload
	movl	56(%r13), %edi
	callq	_order_base_2
	movq	_UVD_RBC_RB_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_RB_BUFSZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%edi, %edi
	movl	%eax, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_BLKSZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_NO_FETCH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_NO_UPDATE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_RPTR_WR_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r14), %edi
	movq	_mmUVD_RBC_RB_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_RBC_RB_WPTR_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %ebx
	movq	_mmUVD_RBC_RB_RPTR_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	48(%r13), %rdi
	callq	_upper_32_bits
	sarl	$2, %eax
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r15d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %ebx
	movq	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	48(%r13), %rdi
	callq	_lower_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r15d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %ebx
	movq	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	48(%r13), %rdi
	callq	_upper_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r15d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_RBC_RB_RPTR@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_SCRATCH2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	%rax, 40(%r13)
	movl	(%r14), %ebx
	movq	_mmUVD_RBC_RB_WPTR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r15d
	movq	%rax, %rdi
	callq	_lower_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r15d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rbx
	movl	(%r14), %edi
	movq	_mmUVD_JRBC_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	%rax, 8(%rbx)
	movslq	(%rbx), %rcx
	movq	_amdgpu_sched_hw_submission@GOTPCREL(%rip), %rdx
	movslq	(%rdx), %rsi
	imulq	%rcx, %rsi
	addq	%rax, %rsi
	movq	%rbx, %rdi
	callq	_vcn_v1_0_jpeg_ring_set_patch_ring
	xorl	%eax, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_POWER_STATUS,4,2         ## @mmUVD_POWER_STATUS
	.comm	_UVD_POWER_STATUS__UVD_PG_MODE_MASK,4,2 ## @UVD_POWER_STATUS__UVD_PG_MODE_MASK
	.comm	_UVD_POWER_STATUS__UVD_PG_EN_MASK,4,2 ## @UVD_POWER_STATUS__UVD_PG_EN_MASK
	.comm	_UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT,4,2 ## @UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT
	.comm	_UVD_VCPU_CNTL__CLK_EN_MASK,4,2 ## @UVD_VCPU_CNTL__CLK_EN_MASK
	.comm	_UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK,4,2 ## @UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK
	.comm	_mmUVD_VCPU_CNTL,4,2            ## @mmUVD_VCPU_CNTL
	.comm	_mmUVD_MASTINT_EN,4,2           ## @mmUVD_MASTINT_EN
	.comm	_UVD_MASTINT_EN__VCPU_EN_MASK,4,2 ## @UVD_MASTINT_EN__VCPU_EN_MASK
	.comm	_mmUVD_LMI_CTRL,4,2             ## @mmUVD_LMI_CTRL
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT,4,2 ## @UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK,4,2 ## @UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK
	.comm	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK,4,2 ## @UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK,4,2 ## @UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__REQ_MODE_MASK,4,2 ## @UVD_LMI_CTRL__REQ_MODE_MASK
	.comm	_UVD_LMI_CTRL__CRC_RESET_MASK,4,2 ## @UVD_LMI_CTRL__CRC_RESET_MASK
	.comm	_UVD_LMI_CTRL__MASK_MC_URGENT_MASK,4,2 ## @UVD_LMI_CTRL__MASK_MC_URGENT_MASK
	.comm	_mmUVD_LMI_SWAP_CNTL,4,2        ## @mmUVD_LMI_SWAP_CNTL
	.comm	_mmUVD_MPC_CNTL,4,2             ## @mmUVD_MPC_CNTL
	.comm	_UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT,4,2 ## @UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT
	.comm	_mmUVD_MPC_SET_MUXA0,4,2        ## @mmUVD_MPC_SET_MUXA0
	.comm	_UVD_MPC_SET_MUXA0__VARA_1__SHIFT,4,2 ## @UVD_MPC_SET_MUXA0__VARA_1__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_2__SHIFT,4,2 ## @UVD_MPC_SET_MUXA0__VARA_2__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_3__SHIFT,4,2 ## @UVD_MPC_SET_MUXA0__VARA_3__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_4__SHIFT,4,2 ## @UVD_MPC_SET_MUXA0__VARA_4__SHIFT
	.comm	_mmUVD_MPC_SET_MUXB0,4,2        ## @mmUVD_MPC_SET_MUXB0
	.comm	_UVD_MPC_SET_MUXB0__VARB_1__SHIFT,4,2 ## @UVD_MPC_SET_MUXB0__VARB_1__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_2__SHIFT,4,2 ## @UVD_MPC_SET_MUXB0__VARB_2__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_3__SHIFT,4,2 ## @UVD_MPC_SET_MUXB0__VARB_3__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_4__SHIFT,4,2 ## @UVD_MPC_SET_MUXB0__VARB_4__SHIFT
	.comm	_mmUVD_MPC_SET_MUX,4,2          ## @mmUVD_MPC_SET_MUX
	.comm	_UVD_MPC_SET_MUX__SET_0__SHIFT,4,2 ## @UVD_MPC_SET_MUX__SET_0__SHIFT
	.comm	_UVD_MPC_SET_MUX__SET_1__SHIFT,4,2 ## @UVD_MPC_SET_MUX__SET_1__SHIFT
	.comm	_UVD_MPC_SET_MUX__SET_2__SHIFT,4,2 ## @UVD_MPC_SET_MUX__SET_2__SHIFT
	.comm	_mmUVD_REG_XX_MASK,4,2          ## @mmUVD_REG_XX_MASK
	.comm	_mmUVD_RBC_XX_IB_REG_CHECK,4,2  ## @mmUVD_RBC_XX_IB_REG_CHECK
	.comm	_mmUVD_SOFT_RESET,4,2           ## @mmUVD_SOFT_RESET
	.comm	_mmUVD_LMI_CTRL2,4,2            ## @mmUVD_LMI_CTRL2
	.comm	_UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,4,2 ## @UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT
	.comm	_mmUVD_JPEG_ADDR_CONFIG,4,2     ## @mmUVD_JPEG_ADDR_CONFIG
	.comm	_mmUVD_JPEG_UV_ADDR_CONFIG,4,2  ## @mmUVD_JPEG_UV_ADDR_CONFIG
	.comm	_mmUVD_SYS_INT_EN,4,2           ## @mmUVD_SYS_INT_EN
	.comm	_UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,4,2 ## @UVD_SYS_INT_EN__UVD_JRBC_EN_MASK
	.comm	_UVD_RBC_RB_CNTL,4,2            ## @UVD_RBC_RB_CNTL
	.comm	_RB_BUFSZ,4,2                   ## @RB_BUFSZ
	.comm	_RB_BLKSZ,4,2                   ## @RB_BLKSZ
	.comm	_RB_NO_FETCH,4,2                ## @RB_NO_FETCH
	.comm	_RB_NO_UPDATE,4,2               ## @RB_NO_UPDATE
	.comm	_RB_RPTR_WR_EN,4,2              ## @RB_RPTR_WR_EN
	.comm	_mmUVD_RBC_RB_CNTL,4,2          ## @mmUVD_RBC_RB_CNTL
	.comm	_mmUVD_RBC_RB_WPTR_CNTL,4,2     ## @mmUVD_RBC_RB_WPTR_CNTL
	.comm	_mmUVD_RBC_RB_RPTR_ADDR,4,2     ## @mmUVD_RBC_RB_RPTR_ADDR
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
	.comm	_mmUVD_RBC_RB_RPTR,4,2          ## @mmUVD_RBC_RB_RPTR
	.comm	_mmUVD_SCRATCH2,4,2             ## @mmUVD_SCRATCH2
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ## @mmUVD_RBC_RB_WPTR
	.comm	_UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK,4,2 ## @UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK
	.comm	_mmUVD_JRBC_RB_WPTR,4,2         ## @mmUVD_JRBC_RB_WPTR
	.comm	_amdgpu_sched_hw_submission,4,2 ## @amdgpu_sched_hw_submission
	.no_dead_strip	_vcn_v1_0_start_dpg_mode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v1_0_start_dpg_mode
_vcn_v1_0_start_dpg_mode:               ; @vcn_v1_0_start_dpg_mode
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	x23, [x0]
	bl	_vcn_1_0_enable_static_power_gating
Lloh0:
	adrp	x22, _UVD@GOTPAGE
Lloh1:
	ldr	x22, [x22, _UVD@GOTPAGEOFF]
	ldr	w0, [x22]
Lloh2:
	adrp	x20, _mmUVD_POWER_STATUS@GOTPAGE
Lloh3:
	ldr	x20, [x20, _mmUVD_POWER_STATUS@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh4:
	adrp	x8, _UVD_POWER_STATUS__UVD_PG_MODE_MASK@GOTPAGE
Lloh5:
	ldr	x8, [x8, _UVD_POWER_STATUS__UVD_PG_MODE_MASK@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh7:
	adrp	x9, _UVD_POWER_STATUS__UVD_PG_EN_MASK@GOTPAGE
Lloh8:
	ldr	x9, [x9, _UVD_POWER_STATUS__UVD_PG_EN_MASK@GOTPAGEOFF]
Lloh9:
	ldr	w9, [x9]
	orr	w3, w8, w9
	ldr	w0, [x22]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_WREG32_SOC15
	mov	x0, x19
	mov	w1, #0
	bl	_vcn_v1_0_clock_gating_dpg_mode
Lloh10:
	adrp	x8, _UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT@GOTPAGE
Lloh11:
	ldr	x8, [x8, _UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	mov	w9, #255
	lsl	w8, w9, w8
Lloh13:
	adrp	x9, _UVD_VCPU_CNTL__CLK_EN_MASK@GOTPAGE
Lloh14:
	ldr	x9, [x9, _UVD_VCPU_CNTL__CLK_EN_MASK@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh16:
	adrp	x9, _UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK@GOTPAGE
Lloh17:
	ldr	x9, [x9, _UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	orr	w3, w8, w9
	ldr	w0, [x22]
Lloh19:
	adrp	x8, _mmUVD_VCPU_CNTL@GOTPAGE
Lloh20:
	ldr	x8, [x8, _mmUVD_VCPU_CNTL@GOTPAGEOFF]
Lloh21:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x22]
Lloh22:
	adrp	x8, _mmUVD_MASTINT_EN@GOTPAGE
Lloh23:
	ldr	x8, [x8, _mmUVD_MASTINT_EN@GOTPAGEOFF]
Lloh24:
	ldr	w2, [x8]
Lloh25:
	adrp	x8, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGE
Lloh26:
	ldr	x8, [x8, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGEOFF]
Lloh27:
	ldr	w4, [x8]
	mov	w1, #0
	mov	w3, #0
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x22]
Lloh28:
	adrp	x8, _mmUVD_LMI_CTRL@GOTPAGE
Lloh29:
	ldr	x8, [x8, _mmUVD_LMI_CTRL@GOTPAGEOFF]
Lloh30:
	ldr	w2, [x8]
Lloh31:
	adrp	x8, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT@GOTPAGE
Lloh32:
	ldr	x8, [x8, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
	mov	w9, #8
Lloh34:
	adrp	x10, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPAGE
Lloh35:
	ldr	x10, [x10, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPAGEOFF]
	lsl	w8, w9, w8
Lloh36:
	ldr	w9, [x10]
Lloh37:
	adrp	x10, _UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPAGE
Lloh38:
	ldr	x10, [x10, _UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPAGEOFF]
Lloh39:
	adrp	x12, _UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPAGE
Lloh40:
	ldr	x12, [x12, _UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPAGEOFF]
Lloh41:
	ldr	w10, [x10]
Lloh42:
	ldr	w11, [x12]
Lloh43:
	adrp	x21, _UVD_LMI_CTRL__REQ_MODE_MASK@GOTPAGE
Lloh44:
	ldr	x21, [x21, _UVD_LMI_CTRL__REQ_MODE_MASK@GOTPAGEOFF]
Lloh45:
	adrp	x24, _UVD_LMI_CTRL__CRC_RESET_MASK@GOTPAGE
Lloh46:
	ldr	x24, [x24, _UVD_LMI_CTRL__CRC_RESET_MASK@GOTPAGEOFF]
	ldr	w12, [x21]
	ldr	w13, [x24]
Lloh47:
	adrp	x25, _UVD_LMI_CTRL__MASK_MC_URGENT_MASK@GOTPAGE
Lloh48:
	ldr	x25, [x25, _UVD_LMI_CTRL__MASK_MC_URGENT_MASK@GOTPAGEOFF]
	ldr	w14, [x25]
	orr	w8, w9, w8
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w8, w8, w13
	orr	w8, w8, w14
	orr	w3, w8, #0x100000
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x22]
Lloh49:
	adrp	x8, _mmUVD_LMI_SWAP_CNTL@GOTPAGE
Lloh50:
	ldr	x8, [x8, _mmUVD_LMI_SWAP_CNTL@GOTPAGEOFF]
Lloh51:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x22]
Lloh52:
	adrp	x8, _mmUVD_MPC_CNTL@GOTPAGE
Lloh53:
	ldr	x8, [x8, _mmUVD_MPC_CNTL@GOTPAGEOFF]
Lloh54:
	ldr	w2, [x8]
Lloh55:
	adrp	x8, _UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT@GOTPAGE
Lloh56:
	ldr	x8, [x8, _UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT@GOTPAGEOFF]
Lloh57:
	ldr	w8, [x8]
	mov	w26, #2
	lsl	w3, w26, w8
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
Lloh58:
	adrp	x8, _mmUVD_MPC_SET_MUXA0@GOTPAGE
Lloh59:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXA0@GOTPAGEOFF]
	ldr	w0, [x22]
Lloh60:
	ldr	w2, [x8]
Lloh61:
	adrp	x8, _UVD_MPC_SET_MUXA0__VARA_1__SHIFT@GOTPAGE
Lloh62:
	ldr	x8, [x8, _UVD_MPC_SET_MUXA0__VARA_1__SHIFT@GOTPAGEOFF]
Lloh63:
	ldr	w8, [x8]
	mov	w27, #1
	lsl	w8, w27, w8
Lloh64:
	adrp	x9, _UVD_MPC_SET_MUXA0__VARA_2__SHIFT@GOTPAGE
Lloh65:
	ldr	x9, [x9, _UVD_MPC_SET_MUXA0__VARA_2__SHIFT@GOTPAGEOFF]
Lloh66:
	ldr	w9, [x9]
	lsl	w9, w26, w9
	orr	w8, w9, w8
Lloh67:
	adrp	x9, _UVD_MPC_SET_MUXA0__VARA_3__SHIFT@GOTPAGE
Lloh68:
	ldr	x9, [x9, _UVD_MPC_SET_MUXA0__VARA_3__SHIFT@GOTPAGEOFF]
Lloh69:
	ldr	w9, [x9]
	mov	w28, #3
	lsl	w9, w28, w9
	orr	w8, w8, w9
Lloh70:
	adrp	x9, _UVD_MPC_SET_MUXA0__VARA_4__SHIFT@GOTPAGE
Lloh71:
	ldr	x9, [x9, _UVD_MPC_SET_MUXA0__VARA_4__SHIFT@GOTPAGEOFF]
Lloh72:
	ldr	w9, [x9]
	mov	w20, #4
	lsl	w9, w20, w9
	orr	w3, w8, w9
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x22]
Lloh73:
	adrp	x8, _mmUVD_MPC_SET_MUXB0@GOTPAGE
Lloh74:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXB0@GOTPAGEOFF]
Lloh75:
	adrp	x9, _UVD_MPC_SET_MUXB0__VARB_1__SHIFT@GOTPAGE
Lloh76:
	ldr	x9, [x9, _UVD_MPC_SET_MUXB0__VARB_1__SHIFT@GOTPAGEOFF]
Lloh77:
	ldr	w2, [x8]
Lloh78:
	ldr	w8, [x9]
	lsl	w8, w27, w8
Lloh79:
	adrp	x9, _UVD_MPC_SET_MUXB0__VARB_2__SHIFT@GOTPAGE
Lloh80:
	ldr	x9, [x9, _UVD_MPC_SET_MUXB0__VARB_2__SHIFT@GOTPAGEOFF]
Lloh81:
	ldr	w9, [x9]
	lsl	w9, w26, w9
	orr	w8, w9, w8
Lloh82:
	adrp	x9, _UVD_MPC_SET_MUXB0__VARB_3__SHIFT@GOTPAGE
Lloh83:
	ldr	x9, [x9, _UVD_MPC_SET_MUXB0__VARB_3__SHIFT@GOTPAGEOFF]
Lloh84:
	ldr	w9, [x9]
	lsl	w9, w28, w9
	orr	w8, w8, w9
Lloh85:
	adrp	x9, _UVD_MPC_SET_MUXB0__VARB_4__SHIFT@GOTPAGE
Lloh86:
	ldr	x9, [x9, _UVD_MPC_SET_MUXB0__VARB_4__SHIFT@GOTPAGEOFF]
Lloh87:
	ldr	w9, [x9]
	lsl	w9, w20, w9
	orr	w3, w8, w9
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x22]
Lloh88:
	adrp	x8, _mmUVD_MPC_SET_MUX@GOTPAGE
Lloh89:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUX@GOTPAGEOFF]
Lloh90:
	ldr	w2, [x8]
Lloh91:
	adrp	x8, _UVD_MPC_SET_MUX__SET_1__SHIFT@GOTPAGE
Lloh92:
	ldr	x8, [x8, _UVD_MPC_SET_MUX__SET_1__SHIFT@GOTPAGEOFF]
Lloh93:
	ldr	w8, [x8]
	lsl	w8, w27, w8
Lloh94:
	adrp	x9, _UVD_MPC_SET_MUX__SET_2__SHIFT@GOTPAGE
Lloh95:
	ldr	x9, [x9, _UVD_MPC_SET_MUX__SET_2__SHIFT@GOTPAGEOFF]
Lloh96:
	ldr	w9, [x9]
	lsl	w9, w26, w9
	orr	w3, w9, w8
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	mov	x0, x19
	bl	_vcn_v1_0_mc_resume_dpg_mode
	ldr	w0, [x22]
Lloh97:
	adrp	x8, _mmUVD_REG_XX_MASK@GOTPAGE
Lloh98:
	ldr	x8, [x8, _mmUVD_REG_XX_MASK@GOTPAGEOFF]
Lloh99:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #16
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x22]
Lloh100:
	adrp	x8, _mmUVD_RBC_XX_IB_REG_CHECK@GOTPAGE
Lloh101:
	ldr	x8, [x8, _mmUVD_RBC_XX_IB_REG_CHECK@GOTPAGEOFF]
Lloh102:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #3
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x22]
Lloh103:
	adrp	x8, _mmUVD_SOFT_RESET@GOTPAGE
Lloh104:
	ldr	x8, [x8, _mmUVD_SOFT_RESET@GOTPAGEOFF]
Lloh105:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x22]
Lloh106:
	adrp	x8, _mmUVD_LMI_CTRL2@GOTPAGE
Lloh107:
	ldr	x8, [x8, _mmUVD_LMI_CTRL2@GOTPAGEOFF]
Lloh108:
	ldr	w2, [x8]
Lloh109:
	adrp	x8, _UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT@GOTPAGE
Lloh110:
	ldr	x8, [x8, _UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT@GOTPAGEOFF]
Lloh111:
	ldr	w8, [x8]
	mov	w9, #31
	lsl	w3, w9, w8
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x22]
Lloh112:
	adrp	x8, _mmUVD_MASTINT_EN@GOTPAGE
Lloh113:
	ldr	x8, [x8, _mmUVD_MASTINT_EN@GOTPAGEOFF]
Lloh114:
	ldr	w2, [x8]
Lloh115:
	adrp	x8, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGE
Lloh116:
	ldr	x8, [x8, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGEOFF]
Lloh117:
	ldr	w3, [x8]
	mov	w1, #0
	mov	x4, x3
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	mov	x0, x19
	mov	w1, #1
	bl	_vcn_v1_0_clock_gating_dpg_mode
	ldr	w0, [x22]
Lloh118:
	adrp	x8, _mmUVD_LMI_CTRL@GOTPAGE
Lloh119:
	ldr	x8, [x8, _mmUVD_LMI_CTRL@GOTPAGEOFF]
Lloh120:
	ldr	w2, [x8]
Lloh121:
	adrp	x8, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT@GOTPAGE
Lloh122:
	ldr	x8, [x8, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT@GOTPAGEOFF]
Lloh123:
	ldr	w8, [x8]
	mov	w9, #8
	lsl	w8, w9, w8
Lloh124:
	adrp	x9, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPAGE
Lloh125:
	ldr	x9, [x9, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPAGEOFF]
Lloh126:
	ldr	w9, [x9]
Lloh127:
	adrp	x10, _UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPAGE
Lloh128:
	ldr	x10, [x10, _UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPAGEOFF]
Lloh129:
	ldr	w10, [x10]
Lloh130:
	adrp	x11, _UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPAGE
Lloh131:
	ldr	x11, [x11, _UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPAGEOFF]
Lloh132:
	ldr	w11, [x11]
	ldr	w12, [x21]
	ldr	w13, [x24]
	ldr	w14, [x25]
	orr	w8, w9, w8
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w8, w8, w13
	orr	w8, w8, w14
	orr	w3, w8, #0x100000
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #1
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w20, [x19, #8]
	ldr	w0, [x22]
Lloh133:
	adrp	x8, _mmUVD_JPEG_ADDR_CONFIG@GOTPAGE
Lloh134:
	ldr	x8, [x8, _mmUVD_JPEG_ADDR_CONFIG@GOTPAGEOFF]
Lloh135:
	ldr	w2, [x8]
	mov	w1, #0
	mov	x3, x20
	mov	w4, #-1
	mov	w5, #1
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x22]
Lloh136:
	adrp	x8, _mmUVD_JPEG_UV_ADDR_CONFIG@GOTPAGE
Lloh137:
	ldr	x8, [x8, _mmUVD_JPEG_UV_ADDR_CONFIG@GOTPAGEOFF]
Lloh138:
	ldr	w2, [x8]
	mov	w1, #0
	mov	x3, x20
	mov	w4, #-1
	mov	w5, #1
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x22]
Lloh139:
	adrp	x8, _mmUVD_SYS_INT_EN@GOTPAGE
Lloh140:
	ldr	x8, [x8, _mmUVD_SYS_INT_EN@GOTPAGEOFF]
Lloh141:
	ldr	w2, [x8]
Lloh142:
	adrp	x8, _UVD_SYS_INT_EN__UVD_JRBC_EN_MASK@GOTPAGE
Lloh143:
	ldr	x8, [x8, _UVD_SYS_INT_EN__UVD_JRBC_EN_MASK@GOTPAGEOFF]
Lloh144:
	ldr	w3, [x8]
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #1
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x23, #56]
	bl	_order_base_2
	mov	x3, x0
Lloh145:
	adrp	x20, _UVD_RBC_RB_CNTL@GOTPAGE
Lloh146:
	ldr	x20, [x20, _UVD_RBC_RB_CNTL@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh147:
	adrp	x8, _RB_BUFSZ@GOTPAGE
Lloh148:
	ldr	x8, [x8, _RB_BUFSZ@GOTPAGEOFF]
Lloh149:
	ldr	w2, [x8]
	mov	w0, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x20]
Lloh150:
	adrp	x8, _RB_BLKSZ@GOTPAGE
Lloh151:
	ldr	x8, [x8, _RB_BLKSZ@GOTPAGEOFF]
Lloh152:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x20]
Lloh153:
	adrp	x8, _RB_NO_FETCH@GOTPAGE
Lloh154:
	ldr	x8, [x8, _RB_NO_FETCH@GOTPAGEOFF]
Lloh155:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x20]
Lloh156:
	adrp	x8, _RB_NO_UPDATE@GOTPAGE
Lloh157:
	ldr	x8, [x8, _RB_NO_UPDATE@GOTPAGEOFF]
Lloh158:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x20]
Lloh159:
	adrp	x8, _RB_RPTR_WR_EN@GOTPAGE
Lloh160:
	ldr	x8, [x8, _RB_RPTR_WR_EN@GOTPAGEOFF]
Lloh161:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x22]
Lloh162:
	adrp	x24, _mmUVD_RBC_RB_CNTL@GOTPAGE
Lloh163:
	ldr	x24, [x24, _mmUVD_RBC_RB_CNTL@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh164:
	adrp	x8, _mmUVD_RBC_RB_WPTR_CNTL@GOTPAGE
Lloh165:
	ldr	x8, [x8, _mmUVD_RBC_RB_WPTR_CNTL@GOTPAGEOFF]
Lloh166:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh167:
	adrp	x8, _mmUVD_RBC_RB_RPTR_ADDR@GOTPAGE
Lloh168:
	ldr	x8, [x8, _mmUVD_RBC_RB_RPTR_ADDR@GOTPAGEOFF]
Lloh169:
	ldr	w21, [x8]
	ldr	x0, [x23, #48]
	bl	_upper_32_bits
	asr	w3, w0, #2
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh170:
	adrp	x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPAGE
Lloh171:
	ldr	x8, [x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh172:
	ldr	w21, [x8]
	ldr	x0, [x23, #48]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh173:
	adrp	x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPAGE
Lloh174:
	ldr	x8, [x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh175:
	ldr	w21, [x8]
	ldr	x0, [x23, #48]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh176:
	adrp	x20, _mmUVD_RBC_RB_RPTR@GOTPAGE
Lloh177:
	ldr	x20, [x20, _mmUVD_RBC_RB_RPTR@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh178:
	adrp	x8, _mmUVD_SCRATCH2@GOTPAGE
Lloh179:
	ldr	x8, [x8, _mmUVD_SCRATCH2@GOTPAGEOFF]
Lloh180:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_RREG32_SOC15
	str	x0, [x23, #40]
	ldr	w20, [x22]
Lloh181:
	adrp	x8, _mmUVD_RBC_RB_WPTR@GOTPAGE
Lloh182:
	ldr	x8, [x8, _mmUVD_RBC_RB_WPTR@GOTPAGEOFF]
Lloh183:
	ldr	w21, [x8]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w0, [x22]
	ldr	w2, [x24]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh184:
	adrp	x8, _UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK@GOTPAGE
Lloh185:
	ldr	x8, [x8, _UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK@GOTPAGEOFF]
Lloh186:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	x19, [x19]
	ldr	w0, [x22]
Lloh187:
	adrp	x8, _mmUVD_JRBC_RB_WPTR@GOTPAGE
Lloh188:
	ldr	x8, [x8, _mmUVD_JRBC_RB_WPTR@GOTPAGEOFF]
Lloh189:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_RREG32_SOC15
	str	x0, [x19, #8]
	ldrsw	x8, [x19]
Lloh190:
	adrp	x9, _amdgpu_sched_hw_submission@GOTPAGE
Lloh191:
	ldr	x9, [x9, _amdgpu_sched_hw_submission@GOTPAGEOFF]
Lloh192:
	ldrsw	x9, [x9]
	madd	x1, x9, x8, x0
	mov	x0, x19
	bl	_vcn_v1_0_jpeg_ring_set_patch_ring
	mov	w0, #0
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh190, Lloh191, Lloh192
	.loh AdrpLdrGotLdr	Lloh187, Lloh188, Lloh189
	.loh AdrpLdrGotLdr	Lloh184, Lloh185, Lloh186
	.loh AdrpLdrGotLdr	Lloh181, Lloh182, Lloh183
	.loh AdrpLdrGotLdr	Lloh178, Lloh179, Lloh180
	.loh AdrpLdrGot	Lloh176, Lloh177
	.loh AdrpLdrGotLdr	Lloh173, Lloh174, Lloh175
	.loh AdrpLdrGotLdr	Lloh170, Lloh171, Lloh172
	.loh AdrpLdrGotLdr	Lloh167, Lloh168, Lloh169
	.loh AdrpLdrGotLdr	Lloh164, Lloh165, Lloh166
	.loh AdrpLdrGot	Lloh162, Lloh163
	.loh AdrpLdrGotLdr	Lloh159, Lloh160, Lloh161
	.loh AdrpLdrGotLdr	Lloh156, Lloh157, Lloh158
	.loh AdrpLdrGotLdr	Lloh153, Lloh154, Lloh155
	.loh AdrpLdrGotLdr	Lloh150, Lloh151, Lloh152
	.loh AdrpLdrGotLdr	Lloh147, Lloh148, Lloh149
	.loh AdrpLdrGot	Lloh145, Lloh146
	.loh AdrpLdrGotLdr	Lloh142, Lloh143, Lloh144
	.loh AdrpLdrGotLdr	Lloh139, Lloh140, Lloh141
	.loh AdrpLdrGotLdr	Lloh136, Lloh137, Lloh138
	.loh AdrpLdrGotLdr	Lloh133, Lloh134, Lloh135
	.loh AdrpLdrGotLdr	Lloh130, Lloh131, Lloh132
	.loh AdrpLdrGotLdr	Lloh127, Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.loh AdrpLdrGotLdr	Lloh112, Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh77
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh41
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_POWER_STATUS,4,2         ; @mmUVD_POWER_STATUS
	.comm	_UVD_POWER_STATUS__UVD_PG_MODE_MASK,4,2 ; @UVD_POWER_STATUS__UVD_PG_MODE_MASK
	.comm	_UVD_POWER_STATUS__UVD_PG_EN_MASK,4,2 ; @UVD_POWER_STATUS__UVD_PG_EN_MASK
	.comm	_UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT,4,2 ; @UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT
	.comm	_UVD_VCPU_CNTL__CLK_EN_MASK,4,2 ; @UVD_VCPU_CNTL__CLK_EN_MASK
	.comm	_UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK,4,2 ; @UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK
	.comm	_mmUVD_VCPU_CNTL,4,2            ; @mmUVD_VCPU_CNTL
	.comm	_mmUVD_MASTINT_EN,4,2           ; @mmUVD_MASTINT_EN
	.comm	_UVD_MASTINT_EN__VCPU_EN_MASK,4,2 ; @UVD_MASTINT_EN__VCPU_EN_MASK
	.comm	_mmUVD_LMI_CTRL,4,2             ; @mmUVD_LMI_CTRL
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT,4,2 ; @UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK,4,2 ; @UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK
	.comm	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK,4,2 ; @UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK,4,2 ; @UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__REQ_MODE_MASK,4,2 ; @UVD_LMI_CTRL__REQ_MODE_MASK
	.comm	_UVD_LMI_CTRL__CRC_RESET_MASK,4,2 ; @UVD_LMI_CTRL__CRC_RESET_MASK
	.comm	_UVD_LMI_CTRL__MASK_MC_URGENT_MASK,4,2 ; @UVD_LMI_CTRL__MASK_MC_URGENT_MASK
	.comm	_mmUVD_LMI_SWAP_CNTL,4,2        ; @mmUVD_LMI_SWAP_CNTL
	.comm	_mmUVD_MPC_CNTL,4,2             ; @mmUVD_MPC_CNTL
	.comm	_UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT,4,2 ; @UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT
	.comm	_mmUVD_MPC_SET_MUXA0,4,2        ; @mmUVD_MPC_SET_MUXA0
	.comm	_UVD_MPC_SET_MUXA0__VARA_1__SHIFT,4,2 ; @UVD_MPC_SET_MUXA0__VARA_1__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_2__SHIFT,4,2 ; @UVD_MPC_SET_MUXA0__VARA_2__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_3__SHIFT,4,2 ; @UVD_MPC_SET_MUXA0__VARA_3__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_4__SHIFT,4,2 ; @UVD_MPC_SET_MUXA0__VARA_4__SHIFT
	.comm	_mmUVD_MPC_SET_MUXB0,4,2        ; @mmUVD_MPC_SET_MUXB0
	.comm	_UVD_MPC_SET_MUXB0__VARB_1__SHIFT,4,2 ; @UVD_MPC_SET_MUXB0__VARB_1__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_2__SHIFT,4,2 ; @UVD_MPC_SET_MUXB0__VARB_2__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_3__SHIFT,4,2 ; @UVD_MPC_SET_MUXB0__VARB_3__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_4__SHIFT,4,2 ; @UVD_MPC_SET_MUXB0__VARB_4__SHIFT
	.comm	_mmUVD_MPC_SET_MUX,4,2          ; @mmUVD_MPC_SET_MUX
	.comm	_UVD_MPC_SET_MUX__SET_0__SHIFT,4,2 ; @UVD_MPC_SET_MUX__SET_0__SHIFT
	.comm	_UVD_MPC_SET_MUX__SET_1__SHIFT,4,2 ; @UVD_MPC_SET_MUX__SET_1__SHIFT
	.comm	_UVD_MPC_SET_MUX__SET_2__SHIFT,4,2 ; @UVD_MPC_SET_MUX__SET_2__SHIFT
	.comm	_mmUVD_REG_XX_MASK,4,2          ; @mmUVD_REG_XX_MASK
	.comm	_mmUVD_RBC_XX_IB_REG_CHECK,4,2  ; @mmUVD_RBC_XX_IB_REG_CHECK
	.comm	_mmUVD_SOFT_RESET,4,2           ; @mmUVD_SOFT_RESET
	.comm	_mmUVD_LMI_CTRL2,4,2            ; @mmUVD_LMI_CTRL2
	.comm	_UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,4,2 ; @UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT
	.comm	_mmUVD_JPEG_ADDR_CONFIG,4,2     ; @mmUVD_JPEG_ADDR_CONFIG
	.comm	_mmUVD_JPEG_UV_ADDR_CONFIG,4,2  ; @mmUVD_JPEG_UV_ADDR_CONFIG
	.comm	_mmUVD_SYS_INT_EN,4,2           ; @mmUVD_SYS_INT_EN
	.comm	_UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,4,2 ; @UVD_SYS_INT_EN__UVD_JRBC_EN_MASK
	.comm	_UVD_RBC_RB_CNTL,4,2            ; @UVD_RBC_RB_CNTL
	.comm	_RB_BUFSZ,4,2                   ; @RB_BUFSZ
	.comm	_RB_BLKSZ,4,2                   ; @RB_BLKSZ
	.comm	_RB_NO_FETCH,4,2                ; @RB_NO_FETCH
	.comm	_RB_NO_UPDATE,4,2               ; @RB_NO_UPDATE
	.comm	_RB_RPTR_WR_EN,4,2              ; @RB_RPTR_WR_EN
	.comm	_mmUVD_RBC_RB_CNTL,4,2          ; @mmUVD_RBC_RB_CNTL
	.comm	_mmUVD_RBC_RB_WPTR_CNTL,4,2     ; @mmUVD_RBC_RB_WPTR_CNTL
	.comm	_mmUVD_RBC_RB_RPTR_ADDR,4,2     ; @mmUVD_RBC_RB_RPTR_ADDR
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
	.comm	_mmUVD_RBC_RB_RPTR,4,2          ; @mmUVD_RBC_RB_RPTR
	.comm	_mmUVD_SCRATCH2,4,2             ; @mmUVD_SCRATCH2
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ; @mmUVD_RBC_RB_WPTR
	.comm	_UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK,4,2 ; @UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK
	.comm	_mmUVD_JRBC_RB_WPTR,4,2         ; @mmUVD_JRBC_RB_WPTR
	.comm	_amdgpu_sched_hw_submission,4,2 ; @amdgpu_sched_hw_submission
	.no_dead_strip	_vcn_v1_0_start_dpg_mode
.subsections_via_symbols
