	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function load_dmcu_fw
_load_dmcu_fw:                          ## @load_dmcu_fw
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	(%rdi), %esi
	leal	-128(%rsi), %eax
	cmpl	$20, %eax
	ja	LBB0_15
## %bb.1:
	xorl	%r14d, %r14d
	cmpl	$7, %eax
	je	LBB0_2
LBB0_14:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_15:
	leaq	L_.str(%rip), %rdi
                                        ## kill: def $esi killed $esi killed $rsi
	callq	_DRM_ERROR
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r14d, %r14d
	subl	(%rax), %r14d
	jmp	LBB0_14
LBB0_2:
	movq	%rdi, %rbx
	movl	52(%rdi), %edi
	callq	_ASICREV_IS_PICASSO
	testl	%eax, %eax
	jne	LBB0_4
## %bb.3:
	movl	52(%rbx), %edi
	callq	_ASICREV_IS_RAVEN2
	testl	%eax, %eax
	je	LBB0_14
LBB0_4:
	movq	24(%rbx), %rax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_5
## %bb.6:
	movq	_FIRMWARE_RAVEN_DMCU@GOTPCREL(%rip), %rax
	movq	(%rax), %r15
	leaq	16(%rbx), %r12
	movl	48(%rbx), %edx
	movq	%r12, %rdi
	movq	%r15, %rsi
	callq	_request_firmware_direct
	movl	%eax, %r13d
	movq	_ENOENT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	addl	%r13d, %eax
	jne	LBB0_8
## %bb.7:
	leaq	L_.str.2(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	movq	$0, (%r12)
	jmp	LBB0_14
LBB0_5:
	leaq	L_.str.1(%rip), %rdi
LBB0_13:
	callq	_DRM_DEBUG_KMS
	jmp	LBB0_14
LBB0_8:
	testl	%r13d, %r13d
	je	LBB0_10
## %bb.9:
	movl	48(%rbx), %edi
	leaq	L_.str.3(%rip), %rsi
	movq	%r15, %rdx
	callq	_dev_err
	movl	%r13d, %r14d
	jmp	LBB0_14
LBB0_10:
	movq	(%r12), %rdi
	callq	_amdgpu_ucode_validate
	testl	%eax, %eax
	je	LBB0_12
## %bb.11:
	movl	%eax, %r12d
	movl	48(%rbx), %edi
	leaq	L_.str.4(%rip), %rsi
	movq	%r15, %rdx
	callq	_dev_err
	movq	16(%rbx), %rdi
	callq	_release_firmware
	movq	$0, 16(%rbx)
	movl	%r12d, %r14d
	jmp	LBB0_14
LBB0_12:
	movq	16(%rbx), %rax
	movq	40(%rbx), %rcx
	movq	(%rax), %r12
	movq	_AMDGPU_UCODE_ID_DMCU_ERAM@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rsi
	movq	%rsi, %rdi
	shlq	$4, %rdi
	movq	%rsi, (%rcx,%rdi)
	movq	(%rdx), %rdx
	shlq	$4, %rdx
	movq	%rax, 8(%rcx,%rdx)
	movl	4(%r12), %edi
	callq	_le32_to_cpu
	movq	%rax, %r15
	movl	8(%r12), %edi
	callq	_le32_to_cpu
	subq	%rax, %r15
	movq	_PAGE_SIZE@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%r15, %rdi
	callq	_ALIGN
	addl	%eax, 32(%rbx)
	movq	_AMDGPU_UCODE_ID_DMCU_INTV@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	40(%rbx), %rdx
	movq	%rcx, %rsi
	shlq	$4, %rsi
	movq	%rcx, (%rdx,%rsi)
	movq	16(%rbx), %rcx
	movq	(%rax), %rax
	shlq	$4, %rax
	movq	%rcx, 8(%rdx,%rax)
	movl	8(%r12), %edi
	callq	_le32_to_cpu
	movl	(%r13), %esi
	movq	%rax, %rdi
	callq	_ALIGN
	addl	%eax, 32(%rbx)
	movl	(%r12), %edi
	callq	_le32_to_cpu
	movq	%rax, 8(%rbx)
	leaq	L_.str.5(%rip), %rdi
	jmp	LBB0_13
	.cfi_endproc
                                        ## -- End function
	.comm	_FIRMWARE_RAVEN_DMCU,8,3        ## @FIRMWARE_RAVEN_DMCU
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Unsupported ASIC type: 0x%X\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
L_.str.1:                               ## @.str.1
	.asciz	"dm: DMCU firmware not supported on direct or SMU loading\n"

	.comm	_ENOENT,4,2                     ## @ENOENT
L_.str.2:                               ## @.str.2
	.asciz	"dm: DMCU firmware not found\n"

L_.str.3:                               ## @.str.3
	.asciz	"amdgpu_dm: Can't load firmware \"%s\"\n"

L_.str.4:                               ## @.str.4
	.asciz	"amdgpu_dm: Can't validate firmware \"%s\"\n"

	.comm	_AMDGPU_UCODE_ID_DMCU_ERAM,8,3  ## @AMDGPU_UCODE_ID_DMCU_ERAM
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
	.comm	_AMDGPU_UCODE_ID_DMCU_INTV,8,3  ## @AMDGPU_UCODE_ID_DMCU_INTV
L_.str.5:                               ## @.str.5
	.asciz	"PSP loading DMCU firmware\n"

	.no_dead_strip	_load_dmcu_fw
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function load_dmcu_fw
_load_dmcu_fw:                          ; @load_dmcu_fw
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	ldr	w1, [x0]
	sub	w8, w1, #128
	cmp	w8, #20
	b.hi	LBB0_4
; %bb.1:
	cmp	w8, #7
	b.eq	LBB0_5
LBB0_2:
	mov	w20, #0
LBB0_3:
	mov	x0, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_4:
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_ERROR
Lloh2:
	adrp	x8, _EINVAL@GOTPAGE
Lloh3:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	neg	w20, w8
	b	LBB0_3
LBB0_5:
	mov	x19, x0
	ldr	w0, [x0, #52]
	bl	_ASICREV_IS_PICASSO
	cbnz	w0, LBB0_7
; %bb.6:
	ldr	w0, [x19, #52]
	bl	_ASICREV_IS_RAVEN2
	cbz	w0, LBB0_2
LBB0_7:
	ldr	x8, [x19, #24]
Lloh5:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh6:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh7:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_10
; %bb.8:
Lloh8:
	adrp	x8, _FIRMWARE_RAVEN_DMCU@GOTPAGE
Lloh9:
	ldr	x8, [x8, _FIRMWARE_RAVEN_DMCU@GOTPAGEOFF]
Lloh10:
	ldr	x21, [x8]
	add	x22, x19, #16
	ldr	w2, [x19, #48]
	mov	x0, x22
	mov	x1, x21
	bl	_request_firmware_direct
Lloh11:
	adrp	x8, _ENOENT@GOTPAGE
Lloh12:
	ldr	x8, [x8, _ENOENT@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
	cmn	w0, w8
	b.ne	LBB0_12
; %bb.9:
Lloh14:
	adrp	x0, l_.str.2@PAGE
Lloh15:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	_DRM_DEBUG_KMS
	mov	w20, #0
	str	xzr, [x22]
	b	LBB0_3
LBB0_10:
Lloh16:
	adrp	x0, l_.str.1@PAGE
Lloh17:
	add	x0, x0, l_.str.1@PAGEOFF
LBB0_11:
	bl	_DRM_DEBUG_KMS
	b	LBB0_2
LBB0_12:
	mov	x20, x0
	cbz	w0, LBB0_14
; %bb.13:
	ldr	w0, [x19, #48]
Lloh18:
	adrp	x1, l_.str.3@PAGE
Lloh19:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x2, x21
	bl	_dev_err
	b	LBB0_3
LBB0_14:
	ldr	x0, [x22]
	bl	_amdgpu_ucode_validate
	cbz	w0, LBB0_16
; %bb.15:
	mov	x20, x0
	ldr	w0, [x19, #48]
Lloh20:
	adrp	x1, l_.str.4@PAGE
Lloh21:
	add	x1, x1, l_.str.4@PAGEOFF
	mov	x2, x21
	bl	_dev_err
	ldr	x0, [x19, #16]
	bl	_release_firmware
	str	xzr, [x19, #16]
	b	LBB0_3
LBB0_16:
	ldr	x8, [x19, #16]
	ldr	x21, [x8]
Lloh22:
	adrp	x9, _AMDGPU_UCODE_ID_DMCU_ERAM@GOTPAGE
Lloh23:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_DMCU_ERAM@GOTPAGEOFF]
	ldr	x10, [x9]
	ldr	x11, [x19, #40]
	lsl	x12, x10, #4
	str	x10, [x11, x12]
	ldr	x9, [x9]
	add	x9, x11, x9, lsl #4
	str	x8, [x9, #8]
	ldr	w0, [x21, #4]
	bl	_le32_to_cpu
	mov	x20, x0
	ldr	w0, [x21, #8]
	bl	_le32_to_cpu
	sub	x0, x20, x0
Lloh24:
	adrp	x20, _PAGE_SIZE@GOTPAGE
Lloh25:
	ldr	x20, [x20, _PAGE_SIZE@GOTPAGEOFF]
	ldr	w1, [x20]
	bl	_ALIGN
	ldr	w8, [x19, #32]
Lloh26:
	adrp	x9, _AMDGPU_UCODE_ID_DMCU_INTV@GOTPAGE
Lloh27:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_DMCU_INTV@GOTPAGEOFF]
	add	w8, w8, w0
	ldr	x10, [x9]
	ldr	x11, [x19, #40]
	lsl	x12, x10, #4
	str	x10, [x11, x12]
	str	w8, [x19, #32]
	ldr	x8, [x19, #16]
	ldr	x9, [x9]
	add	x9, x11, x9, lsl #4
	str	x8, [x9, #8]
	ldr	w0, [x21, #8]
	bl	_le32_to_cpu
	ldr	w1, [x20]
	bl	_ALIGN
	ldr	w8, [x19, #32]
	add	w8, w8, w0
	str	w8, [x19, #32]
	ldr	w0, [x21]
	bl	_le32_to_cpu
	str	x0, [x19, #8]
Lloh28:
	adrp	x0, l_.str.5@PAGE
Lloh29:
	add	x0, x0, l_.str.5@PAGEOFF
	b	LBB0_11
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpAdd	Lloh14, Lloh15
	.loh AdrpAdd	Lloh16, Lloh17
	.loh AdrpAdd	Lloh18, Lloh19
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpAdd	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh22, Lloh23
	.cfi_endproc
                                        ; -- End function
	.comm	_FIRMWARE_RAVEN_DMCU,8,3        ; @FIRMWARE_RAVEN_DMCU
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Unsupported ASIC type: 0x%X\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
l_.str.1:                               ; @.str.1
	.asciz	"dm: DMCU firmware not supported on direct or SMU loading\n"

	.comm	_ENOENT,4,2                     ; @ENOENT
l_.str.2:                               ; @.str.2
	.asciz	"dm: DMCU firmware not found\n"

l_.str.3:                               ; @.str.3
	.asciz	"amdgpu_dm: Can't load firmware \"%s\"\n"

l_.str.4:                               ; @.str.4
	.asciz	"amdgpu_dm: Can't validate firmware \"%s\"\n"

	.comm	_AMDGPU_UCODE_ID_DMCU_ERAM,8,3  ; @AMDGPU_UCODE_ID_DMCU_ERAM
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
	.comm	_AMDGPU_UCODE_ID_DMCU_INTV,8,3  ; @AMDGPU_UCODE_ID_DMCU_INTV
l_.str.5:                               ; @.str.5
	.asciz	"PSP loading DMCU firmware\n"

	.no_dead_strip	_load_dmcu_fw
.subsections_via_symbols
