	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v6_0_cp_gfx_resume
_gfx_v6_0_cp_gfx_resume:                ## @gfx_v6_0_cp_gfx_resume
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_mmCP_SEM_WAIT_TIMER@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmCP_SEM_INCOMPLETE_TIMER_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmCP_RB_WPTR_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmCP_DEBUG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmSCRATCH_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	8(%r14), %r15
	movl	(%r15), %eax
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	callq	_order_base_2
	movl	%eax, %r12d
	movq	_AMDGPU_GPU_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	callq	_order_base_2
	shll	$8, %eax
	orl	%eax, %r12d
	movq	_mmCP_RB0_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movl	(%rbx), %edi
	movq	_CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	%r12d, %esi
	callq	_WREG32
	movl	$0, 4(%r15)
	movq	_mmCP_RB0_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movslq	8(%r15), %rbx
	shlq	$2, %rbx
	addq	(%r14), %rbx
	movq	_mmCP_RB0_RPTR_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	%rbx, %rdi
	callq	_lower_32_bits
	movl	%r13d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmCP_RB0_RPTR_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	%rbx, %rdi
	callq	_upper_32_bits
	movzbl	%al, %esi
	movl	%r13d, %edi
	callq	_WREG32
	movq	_mmSCRATCH_UMSK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	$1, %edi
	callq	_mdelay
	movq	_mmCP_RB0_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_mmCP_RB0_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	12(%r15), %esi
	sarl	$8, %esi
	callq	_WREG32
	movq	%r14, %rdi
	callq	_gfx_v6_0_cp_gfx_start
	movq	%r15, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_test_helper        ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_mmCP_SEM_WAIT_TIMER,4,2        ## @mmCP_SEM_WAIT_TIMER
	.comm	_mmCP_SEM_INCOMPLETE_TIMER_CNTL,4,2 ## @mmCP_SEM_INCOMPLETE_TIMER_CNTL
	.comm	_mmCP_RB_WPTR_DELAY,4,2         ## @mmCP_RB_WPTR_DELAY
	.comm	_mmCP_DEBUG,4,2                 ## @mmCP_DEBUG
	.comm	_mmSCRATCH_ADDR,4,2             ## @mmSCRATCH_ADDR
	.comm	_AMDGPU_GPU_PAGE_SIZE,4,2       ## @AMDGPU_GPU_PAGE_SIZE
	.comm	_mmCP_RB0_CNTL,4,2              ## @mmCP_RB0_CNTL
	.comm	_CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK,4,2 ## @CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK
	.comm	_mmCP_RB0_WPTR,4,2              ## @mmCP_RB0_WPTR
	.comm	_mmCP_RB0_RPTR_ADDR,4,2         ## @mmCP_RB0_RPTR_ADDR
	.comm	_mmCP_RB0_RPTR_ADDR_HI,4,2      ## @mmCP_RB0_RPTR_ADDR_HI
	.comm	_mmSCRATCH_UMSK,4,2             ## @mmSCRATCH_UMSK
	.comm	_mmCP_RB0_BASE,4,2              ## @mmCP_RB0_BASE
	.comm	_BUF_SWAP_32BIT,4,2             ## @BUF_SWAP_32BIT
	.no_dead_strip	_gfx_v6_0_cp_gfx_resume
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v6_0_cp_gfx_resume
_gfx_v6_0_cp_gfx_resume:                ; @gfx_v6_0_cp_gfx_resume
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x8, _mmCP_SEM_WAIT_TIMER@GOTPAGE
Lloh1:
	ldr	x8, [x8, _mmCP_SEM_WAIT_TIMER@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh3:
	adrp	x8, _mmCP_SEM_INCOMPLETE_TIMER_CNTL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _mmCP_SEM_INCOMPLETE_TIMER_CNTL@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh6:
	adrp	x8, _mmCP_RB_WPTR_DELAY@GOTPAGE
Lloh7:
	ldr	x8, [x8, _mmCP_RB_WPTR_DELAY@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh9:
	adrp	x8, _mmCP_DEBUG@GOTPAGE
Lloh10:
	ldr	x8, [x8, _mmCP_DEBUG@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh12:
	adrp	x8, _mmSCRATCH_ADDR@GOTPAGE
Lloh13:
	ldr	x8, [x8, _mmSCRATCH_ADDR@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	ldr	x20, [x19, #8]
	ldr	w8, [x20]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #3
	bl	_order_base_2
	mov	x21, x0
Lloh15:
	adrp	x8, _AMDGPU_GPU_PAGE_SIZE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _AMDGPU_GPU_PAGE_SIZE@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #3
	bl	_order_base_2
	orr	w21, w21, w0, lsl #8
Lloh18:
	adrp	x24, _mmCP_RB0_CNTL@GOTPAGE
Lloh19:
	ldr	x24, [x24, _mmCP_RB0_CNTL@GOTPAGEOFF]
	ldr	w0, [x24]
	mov	x1, x21
	bl	_WREG32
	ldr	w0, [x24]
Lloh20:
	adrp	x8, _CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK@GOTPAGE
Lloh21:
	ldr	x8, [x8, _CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
	orr	w1, w8, w21
	bl	_WREG32
	str	wzr, [x20, #4]
Lloh23:
	adrp	x8, _mmCP_RB0_WPTR@GOTPAGE
Lloh24:
	ldr	x8, [x8, _mmCP_RB0_WPTR@GOTPAGEOFF]
Lloh25:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x19]
	ldrsw	x9, [x20, #8]
	add	x22, x8, x9, lsl #2
Lloh26:
	adrp	x8, _mmCP_RB0_RPTR_ADDR@GOTPAGE
Lloh27:
	ldr	x8, [x8, _mmCP_RB0_RPTR_ADDR@GOTPAGEOFF]
Lloh28:
	ldr	w23, [x8]
	mov	x0, x22
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x23
	bl	_WREG32
Lloh29:
	adrp	x8, _mmCP_RB0_RPTR_ADDR_HI@GOTPAGE
Lloh30:
	ldr	x8, [x8, _mmCP_RB0_RPTR_ADDR_HI@GOTPAGEOFF]
Lloh31:
	ldr	w23, [x8]
	mov	x0, x22
	bl	_upper_32_bits
	and	w1, w0, #0xff
	mov	x0, x23
	bl	_WREG32
Lloh32:
	adrp	x8, _mmSCRATCH_UMSK@GOTPAGE
Lloh33:
	ldr	x8, [x8, _mmSCRATCH_UMSK@GOTPAGEOFF]
Lloh34:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	mov	w0, #1
	bl	_mdelay
	ldr	w0, [x24]
	mov	x1, x21
	bl	_WREG32
Lloh35:
	adrp	x8, _mmCP_RB0_BASE@GOTPAGE
Lloh36:
	ldr	x8, [x8, _mmCP_RB0_BASE@GOTPAGEOFF]
Lloh37:
	ldr	w0, [x8]
	ldr	w8, [x20, #12]
	asr	w1, w8, #8
	bl	_WREG32
	mov	x0, x19
	bl	_gfx_v6_0_cp_gfx_start
	mov	x0, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_amdgpu_ring_test_helper
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_mmCP_SEM_WAIT_TIMER,4,2        ; @mmCP_SEM_WAIT_TIMER
	.comm	_mmCP_SEM_INCOMPLETE_TIMER_CNTL,4,2 ; @mmCP_SEM_INCOMPLETE_TIMER_CNTL
	.comm	_mmCP_RB_WPTR_DELAY,4,2         ; @mmCP_RB_WPTR_DELAY
	.comm	_mmCP_DEBUG,4,2                 ; @mmCP_DEBUG
	.comm	_mmSCRATCH_ADDR,4,2             ; @mmSCRATCH_ADDR
	.comm	_AMDGPU_GPU_PAGE_SIZE,4,2       ; @AMDGPU_GPU_PAGE_SIZE
	.comm	_mmCP_RB0_CNTL,4,2              ; @mmCP_RB0_CNTL
	.comm	_CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK,4,2 ; @CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK
	.comm	_mmCP_RB0_WPTR,4,2              ; @mmCP_RB0_WPTR
	.comm	_mmCP_RB0_RPTR_ADDR,4,2         ; @mmCP_RB0_RPTR_ADDR
	.comm	_mmCP_RB0_RPTR_ADDR_HI,4,2      ; @mmCP_RB0_RPTR_ADDR_HI
	.comm	_mmSCRATCH_UMSK,4,2             ; @mmSCRATCH_UMSK
	.comm	_mmCP_RB0_BASE,4,2              ; @mmCP_RB0_BASE
	.comm	_BUF_SWAP_32BIT,4,2             ; @BUF_SWAP_32BIT
	.no_dead_strip	_gfx_v6_0_cp_gfx_resume
.subsections_via_symbols
