	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_cik_gpu_check_soft_reset       ## -- Begin function cik_gpu_check_soft_reset
	.p2align	4, 0x90
_cik_gpu_check_soft_reset:              ## @cik_gpu_check_soft_reset
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, -56(%rbp)                 ## 8-byte Spill
	movq	_GRBM_STATUS@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movq	_PA_BUSY@GOTPCREL(%rip), %rcx
	movq	_SC_BUSY@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r14d
	orl	(%rcx), %r14d
	movq	_BCI_BUSY@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r14d
	movq	_SX_BUSY@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r14d
	movq	_TA_BUSY@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r14d
	movq	_VGT_BUSY@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r14d
	movq	_DB_BUSY@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r14d
	movq	_CB_BUSY@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r14d
	movq	_GDS_BUSY@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r14d
	movq	_SPI_BUSY@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r14d
	movq	_IA_BUSY@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r14d
	movq	_IA_BUSY_NO_DMA@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r14d
	andl	%eax, %r14d
	je	LBB0_2
## %bb.1:
	movq	_RADEON_RESET_GFX@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r14d
LBB0_2:
	movq	_CP_BUSY@GOTPCREL(%rip), %rcx
	movq	_CP_COHERENCY_BUSY@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r13d
	orl	(%rcx), %r13d
	andl	%eax, %r13d
	je	LBB0_4
## %bb.3:
	movq	_RADEON_RESET_CP@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
LBB0_4:
	movq	_GRBM_STATUS2@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %ebx
	movq	_RLC_BUSY@GOTPCREL(%rip), %rax
	andl	(%rax), %ebx
	je	LBB0_6
## %bb.5:
	movq	_RADEON_RESET_RLC@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
LBB0_6:
	movq	_SDMA0_STATUS_REG@GOTPCREL(%rip), %r15
	movq	_SDMA0_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r15), %rdi
	callq	_RREG32
	movq	_SDMA_IDLE@GOTPCREL(%rip), %r12
	movq	_RADEON_RESET_DMA@GOTPCREL(%rip), %rdx
	movl	$0, %ecx
	andl	(%r12), %eax
	jne	LBB0_8
## %bb.7:
	movl	(%rdx), %ecx
LBB0_8:
	movl	%ecx, -48(%rbp)                 ## 4-byte Spill
	movq	_SDMA1_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r15), %rdi
	callq	_RREG32
	movq	_RADEON_RESET_DMA1@GOTPCREL(%rip), %rdx
	movl	$0, %ecx
	andl	(%r12), %eax
	jne	LBB0_10
## %bb.9:
	movl	(%rdx), %ecx
LBB0_10:
	movl	%ecx, -44(%rbp)                 ## 4-byte Spill
	movq	_SRBM_STATUS2@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movl	%eax, %r15d
	movq	_SDMA_BUSY@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	andl	%r15d, %r12d
	je	LBB0_12
## %bb.11:
	movq	_RADEON_RESET_DMA@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
LBB0_12:
	movq	_SDMA1_BUSY@GOTPCREL(%rip), %rax
	andl	(%rax), %r15d
	je	LBB0_14
## %bb.13:
	movq	_RADEON_RESET_DMA1@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
LBB0_14:
	orl	%ebx, %r13d
	movq	_SRBM_STATUS@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	movq	_IH_BUSY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	andl	%eax, %ebx
	je	LBB0_16
## %bb.15:
	movq	_RADEON_RESET_IH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
LBB0_16:
	orl	-48(%rbp), %r13d                ## 4-byte Folded Reload
	movq	_SEM_BUSY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%eax, %ecx
	je	LBB0_18
## %bb.17:
	movq	_RADEON_RESET_SEM@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_18:
	orl	%ecx, %ebx
	orl	-44(%rbp), %r13d                ## 4-byte Folded Reload
	movq	_GRBM_RQ_PENDING@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%eax, %ecx
	je	LBB0_20
## %bb.19:
	movq	_RADEON_RESET_GRBM@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_20:
	orl	%ecx, %ebx
	orl	%r12d, %r13d
	movq	_VMC_BUSY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%eax, %ecx
	je	LBB0_22
## %bb.21:
	movq	_RADEON_RESET_VMC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_22:
	orl	%ecx, %ebx
	orl	%r15d, %r13d
	movq	_MCB_BUSY@GOTPCREL(%rip), %rdx
	movq	_MCB_NON_DISPLAY_BUSY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rdx), %ecx
	movq	_MCC_BUSY@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_MCD_BUSY@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_RADEON_RESET_MC@GOTPCREL(%rip), %r15
	andl	%eax, %ecx
	je	LBB0_24
## %bb.23:
	movl	(%r15), %ecx
LBB0_24:
	orl	%ecx, %ebx
	orl	%r13d, %r14d
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_evergreen_is_display_hung
	testq	%rax, %rax
	movl	$0, %eax
	je	LBB0_26
## %bb.25:
	movq	_RADEON_RESET_DISPLAY@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_26:
	orl	%eax, %ebx
	orl	%ebx, %r14d
	testl	%r14d, (%r15)
	je	LBB0_28
## %bb.27:
	leaq	L_.str(%rip), %rdi
	movl	%r14d, %esi
	callq	_DRM_DEBUG
	movl	(%r15), %eax
	notl	%eax
	andl	%eax, %r14d
LBB0_28:
	movl	%r14d, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_GRBM_STATUS,8,3                ## @GRBM_STATUS
	.comm	_PA_BUSY,4,2                    ## @PA_BUSY
	.comm	_SC_BUSY,4,2                    ## @SC_BUSY
	.comm	_BCI_BUSY,4,2                   ## @BCI_BUSY
	.comm	_SX_BUSY,4,2                    ## @SX_BUSY
	.comm	_TA_BUSY,4,2                    ## @TA_BUSY
	.comm	_VGT_BUSY,4,2                   ## @VGT_BUSY
	.comm	_DB_BUSY,4,2                    ## @DB_BUSY
	.comm	_CB_BUSY,4,2                    ## @CB_BUSY
	.comm	_GDS_BUSY,4,2                   ## @GDS_BUSY
	.comm	_SPI_BUSY,4,2                   ## @SPI_BUSY
	.comm	_IA_BUSY,4,2                    ## @IA_BUSY
	.comm	_IA_BUSY_NO_DMA,4,2             ## @IA_BUSY_NO_DMA
	.comm	_RADEON_RESET_GFX,4,2           ## @RADEON_RESET_GFX
	.comm	_CP_BUSY,4,2                    ## @CP_BUSY
	.comm	_CP_COHERENCY_BUSY,4,2          ## @CP_COHERENCY_BUSY
	.comm	_RADEON_RESET_CP,4,2            ## @RADEON_RESET_CP
	.comm	_GRBM_STATUS2,8,3               ## @GRBM_STATUS2
	.comm	_RLC_BUSY,4,2                   ## @RLC_BUSY
	.comm	_RADEON_RESET_RLC,4,2           ## @RADEON_RESET_RLC
	.comm	_SDMA0_STATUS_REG,8,3           ## @SDMA0_STATUS_REG
	.comm	_SDMA0_REGISTER_OFFSET,8,3      ## @SDMA0_REGISTER_OFFSET
	.comm	_SDMA_IDLE,4,2                  ## @SDMA_IDLE
	.comm	_RADEON_RESET_DMA,4,2           ## @RADEON_RESET_DMA
	.comm	_SDMA1_REGISTER_OFFSET,8,3      ## @SDMA1_REGISTER_OFFSET
	.comm	_RADEON_RESET_DMA1,4,2          ## @RADEON_RESET_DMA1
	.comm	_SRBM_STATUS2,8,3               ## @SRBM_STATUS2
	.comm	_SDMA_BUSY,4,2                  ## @SDMA_BUSY
	.comm	_SDMA1_BUSY,4,2                 ## @SDMA1_BUSY
	.comm	_SRBM_STATUS,8,3                ## @SRBM_STATUS
	.comm	_IH_BUSY,4,2                    ## @IH_BUSY
	.comm	_RADEON_RESET_IH,4,2            ## @RADEON_RESET_IH
	.comm	_SEM_BUSY,4,2                   ## @SEM_BUSY
	.comm	_RADEON_RESET_SEM,4,2           ## @RADEON_RESET_SEM
	.comm	_GRBM_RQ_PENDING,4,2            ## @GRBM_RQ_PENDING
	.comm	_RADEON_RESET_GRBM,4,2          ## @RADEON_RESET_GRBM
	.comm	_VMC_BUSY,4,2                   ## @VMC_BUSY
	.comm	_RADEON_RESET_VMC,4,2           ## @RADEON_RESET_VMC
	.comm	_MCB_BUSY,4,2                   ## @MCB_BUSY
	.comm	_MCB_NON_DISPLAY_BUSY,4,2       ## @MCB_NON_DISPLAY_BUSY
	.comm	_MCC_BUSY,4,2                   ## @MCC_BUSY
	.comm	_MCD_BUSY,4,2                   ## @MCD_BUSY
	.comm	_RADEON_RESET_MC,4,2            ## @RADEON_RESET_MC
	.comm	_RADEON_RESET_DISPLAY,4,2       ## @RADEON_RESET_DISPLAY
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"MC busy: 0x%08X, clearing.\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_cik_gpu_check_soft_reset       ; -- Begin function cik_gpu_check_soft_reset
	.p2align	2
_cik_gpu_check_soft_reset:              ; @cik_gpu_check_soft_reset
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x8, _GRBM_STATUS@GOTPAGE
Lloh1:
	ldr	x8, [x8, _GRBM_STATUS@GOTPAGEOFF]
Lloh2:
	ldr	x0, [x8]
	bl	_RREG32
Lloh3:
	adrp	x8, _PA_BUSY@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PA_BUSY@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
Lloh6:
	adrp	x9, _SC_BUSY@GOTPAGE
Lloh7:
	ldr	x9, [x9, _SC_BUSY@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
Lloh9:
	adrp	x10, _BCI_BUSY@GOTPAGE
Lloh10:
	ldr	x10, [x10, _BCI_BUSY@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh11:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh12:
	adrp	x9, _SX_BUSY@GOTPAGE
Lloh13:
	ldr	x9, [x9, _SX_BUSY@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh15:
	adrp	x9, _TA_BUSY@GOTPAGE
Lloh16:
	ldr	x9, [x9, _TA_BUSY@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
Lloh18:
	adrp	x10, _VGT_BUSY@GOTPAGE
Lloh19:
	ldr	x10, [x10, _VGT_BUSY@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh20:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh21:
	adrp	x9, _DB_BUSY@GOTPAGE
Lloh22:
	ldr	x9, [x9, _DB_BUSY@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh24:
	adrp	x9, _CB_BUSY@GOTPAGE
Lloh25:
	ldr	x9, [x9, _CB_BUSY@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
Lloh27:
	adrp	x10, _GDS_BUSY@GOTPAGE
Lloh28:
	ldr	x10, [x10, _GDS_BUSY@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh29:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh30:
	adrp	x9, _SPI_BUSY@GOTPAGE
Lloh31:
	ldr	x9, [x9, _SPI_BUSY@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh33:
	adrp	x9, _IA_BUSY@GOTPAGE
Lloh34:
	ldr	x9, [x9, _IA_BUSY@GOTPAGEOFF]
Lloh35:
	ldr	w9, [x9]
Lloh36:
	adrp	x10, _IA_BUSY_NO_DMA@GOTPAGE
Lloh37:
	ldr	x10, [x10, _IA_BUSY_NO_DMA@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh38:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh39:
	adrp	x9, _RADEON_RESET_GFX@GOTPAGE
Lloh40:
	ldr	x9, [x9, _RADEON_RESET_GFX@GOTPAGEOFF]
Lloh41:
	ldr	w9, [x9]
	tst	w8, w0
	csel	w8, wzr, w9, eq
Lloh42:
	adrp	x9, _CP_BUSY@GOTPAGE
Lloh43:
	ldr	x9, [x9, _CP_BUSY@GOTPAGEOFF]
Lloh44:
	adrp	x10, _CP_COHERENCY_BUSY@GOTPAGE
Lloh45:
	ldr	x10, [x10, _CP_COHERENCY_BUSY@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
Lloh47:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh48:
	adrp	x10, _RADEON_RESET_CP@GOTPAGE
Lloh49:
	ldr	x10, [x10, _RADEON_RESET_CP@GOTPAGEOFF]
Lloh50:
	ldr	w10, [x10]
	tst	w9, w0
	csel	w9, wzr, w10, eq
	orr	w20, w9, w8
Lloh51:
	adrp	x8, _GRBM_STATUS2@GOTPAGE
Lloh52:
	ldr	x8, [x8, _GRBM_STATUS2@GOTPAGEOFF]
Lloh53:
	ldr	x0, [x8]
	bl	_RREG32
Lloh54:
	adrp	x8, _RLC_BUSY@GOTPAGE
Lloh55:
	ldr	x8, [x8, _RLC_BUSY@GOTPAGEOFF]
Lloh56:
	adrp	x9, _RADEON_RESET_RLC@GOTPAGE
Lloh57:
	ldr	x9, [x9, _RADEON_RESET_RLC@GOTPAGEOFF]
Lloh58:
	ldr	w8, [x8]
Lloh59:
	ldr	w9, [x9]
	tst	w8, w0
	csel	w8, wzr, w9, eq
Lloh60:
	adrp	x21, _SDMA0_STATUS_REG@GOTPAGE
Lloh61:
	ldr	x21, [x21, _SDMA0_STATUS_REG@GOTPAGEOFF]
	orr	w20, w20, w8
	ldr	x8, [x21]
Lloh62:
	adrp	x9, _SDMA0_REGISTER_OFFSET@GOTPAGE
Lloh63:
	ldr	x9, [x9, _SDMA0_REGISTER_OFFSET@GOTPAGEOFF]
Lloh64:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_RREG32
Lloh65:
	adrp	x22, _SDMA_IDLE@GOTPAGE
Lloh66:
	ldr	x22, [x22, _SDMA_IDLE@GOTPAGEOFF]
	ldr	w8, [x22]
Lloh67:
	adrp	x23, _RADEON_RESET_DMA@GOTPAGE
Lloh68:
	ldr	x23, [x23, _RADEON_RESET_DMA@GOTPAGEOFF]
	ldr	w9, [x23]
	tst	w8, w0
	csel	w8, w9, wzr, eq
	orr	w20, w20, w8
	ldr	x8, [x21]
Lloh69:
	adrp	x9, _SDMA1_REGISTER_OFFSET@GOTPAGE
Lloh70:
	ldr	x9, [x9, _SDMA1_REGISTER_OFFSET@GOTPAGEOFF]
Lloh71:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_RREG32
	ldr	w8, [x22]
Lloh72:
	adrp	x21, _RADEON_RESET_DMA1@GOTPAGE
Lloh73:
	ldr	x21, [x21, _RADEON_RESET_DMA1@GOTPAGEOFF]
	ldr	w9, [x21]
	tst	w8, w0
	csel	w8, w9, wzr, eq
	orr	w20, w20, w8
Lloh74:
	adrp	x8, _SRBM_STATUS2@GOTPAGE
Lloh75:
	ldr	x8, [x8, _SRBM_STATUS2@GOTPAGEOFF]
Lloh76:
	ldr	x0, [x8]
	bl	_RREG32
Lloh77:
	adrp	x8, _SDMA_BUSY@GOTPAGE
Lloh78:
	ldr	x8, [x8, _SDMA_BUSY@GOTPAGEOFF]
Lloh79:
	ldr	w8, [x8]
	ldr	w9, [x23]
	tst	w8, w0
	csel	w8, wzr, w9, eq
	orr	w8, w20, w8
Lloh80:
	adrp	x9, _SDMA1_BUSY@GOTPAGE
Lloh81:
	ldr	x9, [x9, _SDMA1_BUSY@GOTPAGEOFF]
Lloh82:
	ldr	w9, [x9]
	ldr	w10, [x21]
	tst	w9, w0
	csel	w9, wzr, w10, eq
	orr	w20, w8, w9
Lloh83:
	adrp	x8, _SRBM_STATUS@GOTPAGE
Lloh84:
	ldr	x8, [x8, _SRBM_STATUS@GOTPAGEOFF]
Lloh85:
	ldr	x0, [x8]
	bl	_RREG32
Lloh86:
	adrp	x8, _IH_BUSY@GOTPAGE
Lloh87:
	ldr	x8, [x8, _IH_BUSY@GOTPAGEOFF]
Lloh88:
	ldr	w8, [x8]
Lloh89:
	adrp	x9, _RADEON_RESET_IH@GOTPAGE
Lloh90:
	ldr	x9, [x9, _RADEON_RESET_IH@GOTPAGEOFF]
Lloh91:
	ldr	w9, [x9]
	tst	w8, w0
	csel	w8, wzr, w9, eq
	orr	w8, w20, w8
Lloh92:
	adrp	x9, _SEM_BUSY@GOTPAGE
Lloh93:
	ldr	x9, [x9, _SEM_BUSY@GOTPAGEOFF]
Lloh94:
	ldr	w9, [x9]
Lloh95:
	adrp	x10, _RADEON_RESET_SEM@GOTPAGE
Lloh96:
	ldr	x10, [x10, _RADEON_RESET_SEM@GOTPAGEOFF]
Lloh97:
	ldr	w10, [x10]
	tst	w9, w0
	csel	w9, wzr, w10, eq
	orr	w8, w8, w9
Lloh98:
	adrp	x9, _GRBM_RQ_PENDING@GOTPAGE
Lloh99:
	ldr	x9, [x9, _GRBM_RQ_PENDING@GOTPAGEOFF]
Lloh100:
	ldr	w9, [x9]
Lloh101:
	adrp	x10, _RADEON_RESET_GRBM@GOTPAGE
Lloh102:
	ldr	x10, [x10, _RADEON_RESET_GRBM@GOTPAGEOFF]
Lloh103:
	ldr	w10, [x10]
	tst	w9, w0
	csel	w9, wzr, w10, eq
	orr	w8, w8, w9
Lloh104:
	adrp	x9, _VMC_BUSY@GOTPAGE
Lloh105:
	ldr	x9, [x9, _VMC_BUSY@GOTPAGEOFF]
Lloh106:
	ldr	w9, [x9]
Lloh107:
	adrp	x10, _RADEON_RESET_VMC@GOTPAGE
Lloh108:
	ldr	x10, [x10, _RADEON_RESET_VMC@GOTPAGEOFF]
Lloh109:
	ldr	w10, [x10]
	tst	w9, w0
	csel	w9, wzr, w10, eq
	orr	w8, w8, w9
Lloh110:
	adrp	x9, _MCB_BUSY@GOTPAGE
Lloh111:
	ldr	x9, [x9, _MCB_BUSY@GOTPAGEOFF]
Lloh112:
	ldr	w9, [x9]
Lloh113:
	adrp	x10, _MCB_NON_DISPLAY_BUSY@GOTPAGE
Lloh114:
	ldr	x10, [x10, _MCB_NON_DISPLAY_BUSY@GOTPAGEOFF]
Lloh115:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh116:
	adrp	x10, _MCC_BUSY@GOTPAGE
Lloh117:
	ldr	x10, [x10, _MCC_BUSY@GOTPAGEOFF]
Lloh118:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh119:
	adrp	x10, _MCD_BUSY@GOTPAGE
Lloh120:
	ldr	x10, [x10, _MCD_BUSY@GOTPAGEOFF]
Lloh121:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh122:
	adrp	x20, _RADEON_RESET_MC@GOTPAGE
Lloh123:
	ldr	x20, [x20, _RADEON_RESET_MC@GOTPAGEOFF]
	ldr	w10, [x20]
	tst	w9, w0
	csel	w9, wzr, w10, eq
	orr	w21, w8, w9
	mov	x0, x19
	bl	_evergreen_is_display_hung
Lloh124:
	adrp	x8, _RADEON_RESET_DISPLAY@GOTPAGE
Lloh125:
	ldr	x8, [x8, _RADEON_RESET_DISPLAY@GOTPAGEOFF]
Lloh126:
	ldr	w8, [x8]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w19, w21, w8
	ldr	w8, [x20]
	tst	w19, w8
	b.eq	LBB0_2
; %bb.1:
Lloh127:
	adrp	x0, l_.str@PAGE
Lloh128:
	add	x0, x0, l_.str@PAGEOFF
	mov	x1, x19
	bl	_DRM_DEBUG
	ldr	w8, [x20]
	bic	w19, w19, w8
LBB0_2:
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGot	Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGot	Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGot	Lloh67, Lloh68
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh58
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh46
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh127, Lloh128
	.cfi_endproc
                                        ; -- End function
	.comm	_GRBM_STATUS,8,3                ; @GRBM_STATUS
	.comm	_PA_BUSY,4,2                    ; @PA_BUSY
	.comm	_SC_BUSY,4,2                    ; @SC_BUSY
	.comm	_BCI_BUSY,4,2                   ; @BCI_BUSY
	.comm	_SX_BUSY,4,2                    ; @SX_BUSY
	.comm	_TA_BUSY,4,2                    ; @TA_BUSY
	.comm	_VGT_BUSY,4,2                   ; @VGT_BUSY
	.comm	_DB_BUSY,4,2                    ; @DB_BUSY
	.comm	_CB_BUSY,4,2                    ; @CB_BUSY
	.comm	_GDS_BUSY,4,2                   ; @GDS_BUSY
	.comm	_SPI_BUSY,4,2                   ; @SPI_BUSY
	.comm	_IA_BUSY,4,2                    ; @IA_BUSY
	.comm	_IA_BUSY_NO_DMA,4,2             ; @IA_BUSY_NO_DMA
	.comm	_RADEON_RESET_GFX,4,2           ; @RADEON_RESET_GFX
	.comm	_CP_BUSY,4,2                    ; @CP_BUSY
	.comm	_CP_COHERENCY_BUSY,4,2          ; @CP_COHERENCY_BUSY
	.comm	_RADEON_RESET_CP,4,2            ; @RADEON_RESET_CP
	.comm	_GRBM_STATUS2,8,3               ; @GRBM_STATUS2
	.comm	_RLC_BUSY,4,2                   ; @RLC_BUSY
	.comm	_RADEON_RESET_RLC,4,2           ; @RADEON_RESET_RLC
	.comm	_SDMA0_STATUS_REG,8,3           ; @SDMA0_STATUS_REG
	.comm	_SDMA0_REGISTER_OFFSET,8,3      ; @SDMA0_REGISTER_OFFSET
	.comm	_SDMA_IDLE,4,2                  ; @SDMA_IDLE
	.comm	_RADEON_RESET_DMA,4,2           ; @RADEON_RESET_DMA
	.comm	_SDMA1_REGISTER_OFFSET,8,3      ; @SDMA1_REGISTER_OFFSET
	.comm	_RADEON_RESET_DMA1,4,2          ; @RADEON_RESET_DMA1
	.comm	_SRBM_STATUS2,8,3               ; @SRBM_STATUS2
	.comm	_SDMA_BUSY,4,2                  ; @SDMA_BUSY
	.comm	_SDMA1_BUSY,4,2                 ; @SDMA1_BUSY
	.comm	_SRBM_STATUS,8,3                ; @SRBM_STATUS
	.comm	_IH_BUSY,4,2                    ; @IH_BUSY
	.comm	_RADEON_RESET_IH,4,2            ; @RADEON_RESET_IH
	.comm	_SEM_BUSY,4,2                   ; @SEM_BUSY
	.comm	_RADEON_RESET_SEM,4,2           ; @RADEON_RESET_SEM
	.comm	_GRBM_RQ_PENDING,4,2            ; @GRBM_RQ_PENDING
	.comm	_RADEON_RESET_GRBM,4,2          ; @RADEON_RESET_GRBM
	.comm	_VMC_BUSY,4,2                   ; @VMC_BUSY
	.comm	_RADEON_RESET_VMC,4,2           ; @RADEON_RESET_VMC
	.comm	_MCB_BUSY,4,2                   ; @MCB_BUSY
	.comm	_MCB_NON_DISPLAY_BUSY,4,2       ; @MCB_NON_DISPLAY_BUSY
	.comm	_MCC_BUSY,4,2                   ; @MCC_BUSY
	.comm	_MCD_BUSY,4,2                   ; @MCD_BUSY
	.comm	_RADEON_RESET_MC,4,2            ; @RADEON_RESET_MC
	.comm	_RADEON_RESET_DISPLAY,4,2       ; @RADEON_RESET_DISPLAY
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"MC busy: 0x%08X, clearing.\n"

.subsections_via_symbols
