	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function uvd_v5_0_start
_uvd_v5_0_start:                        ## @uvd_v5_0_start
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	(%rdi), %r15
	movq	_mmUVD_POWER_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%r14d, %r14d
	xorl	%esi, %esi
	movl	$-5, %edx
	callq	_WREG32_P
	movq	%rbx, %rdi
	callq	_uvd_v5_0_mc_resume
	movq	_mmUVD_MASTINT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	movl	$-3, %edx
	callq	_WREG32_P
	movq	_mmUVD_LMI_CTRL2@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movl	$256, %esi                      ## imm = 0x100
	movl	$-257, %edx                     ## imm = 0xFEFF
	callq	_WREG32_P
	movl	$1, %edi
	callq	_mdelay
	movq	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	movq	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	orl	(%rax), %esi
	movq	_UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_UVD_SOFT_RESET__RBC_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_UVD_SOFT_RESET__CSM_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_UVD_SOFT_RESET__CXW_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_mmUVD_SOFT_RESET@GOTPCREL(%rip), %r12
	movq	_UVD_SOFT_RESET__TAP_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	(%r12), %edi
	movq	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	callq	_WREG32
	movl	$5, %edi
	callq	_mdelay
	movq	_mmSRBM_SOFT_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	$5, %edi
	callq	_mdelay
	movq	_mmUVD_LMI_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$3154752, %esi                  ## imm = 0x302340
	callq	_WREG32
	movq	_mmUVD_LMI_SWAP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmUVD_MP_SWAP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmUVD_MPC_SET_MUXA0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$67903552, %esi                 ## imm = 0x40C2040
	callq	_WREG32
	movq	_mmUVD_MPC_SET_MUXA1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmUVD_MPC_SET_MUXB0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$67903552, %esi                 ## imm = 0x40C2040
	callq	_WREG32
	movq	_mmUVD_MPC_SET_MUXB1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmUVD_MPC_SET_ALU@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmUVD_MPC_SET_MUX@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$136, %esi
	callq	_WREG32
	movl	(%r12), %edi
	movl	(%rbx), %esi
	callq	_WREG32
	movl	$5, %edi
	callq	_mdelay
	movq	_mmUVD_VCPU_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$512, %esi                      ## imm = 0x200
	callq	_WREG32
	movl	(%r13), %edi
	xorl	%esi, %esi
	movl	$-257, %edx                     ## imm = 0xFEFF
	callq	_WREG32_P
	movl	(%r12), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	$10, %edi
	callq	_mdelay
	movq	_mmUVD_STATUS@GOTPCREL(%rip), %r13
LBB0_1:                                 ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_2 Depth 2
	movl	$100, %ebx
	.p2align	4, 0x90
LBB0_2:                                 ##   Parent Loop BB0_1 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movl	(%r13), %edi
	callq	_RREG32
	testb	$2, %al
	jne	LBB0_6
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=2
	movl	$10, %edi
	callq	_mdelay
	decl	%ebx
	jne	LBB0_2
## %bb.4:                               ##   in Loop: Header=BB0_1 Depth=1
	leaq	L_.str(%rip), %rdi
	callq	_DRM_ERROR
	movl	(%r12), %edi
	movq	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movl	%esi, %edx
	notl	%edx
	callq	_WREG32_P
	movl	$10, %edi
	callq	_mdelay
	movl	(%r12), %edi
	movl	(%rbx), %edx
	notl	%edx
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	$10, %edi
	callq	_mdelay
	incl	%r14d
	cmpl	$10, %r14d
	jne	LBB0_1
## %bb.5:
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_ERROR
	movl	$-1, %r14d
	jmp	LBB0_7
LBB0_6:
	movq	_mmUVD_MASTINT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$6, %esi
	movl	$-7, %edx
	callq	_WREG32_P
	movl	(%r13), %edi
	xorl	%r14d, %r14d
	xorl	%esi, %esi
	movl	$-5, %edx
	callq	_WREG32_P
	movl	16(%r15), %edi
	callq	_order_base_2
	movq	_UVD_RBC_RB_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_RB_BUFSZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%edi, %edi
	movl	%eax, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_BLKSZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_NO_FETCH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_WPTR_POLL_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_NO_UPDATE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_RPTR_WR_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movq	_mmUVD_RBC_RB_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmUVD_RBC_RB_WPTR_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmUVD_RBC_RB_RPTR_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	8(%r15), %rdi
	callq	_upper_32_bits
	sarl	$2, %eax
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	8(%r15), %rdi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	8(%r15), %rdi
	callq	_upper_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmUVD_RBC_RB_RPTR@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%rbx), %edi
	callq	_RREG32
	movq	%rax, (%r15)
	movq	_mmUVD_RBC_RB_WPTR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	movq	%rax, %rdi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movl	(%r12), %edi
	movq	_UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	xorl	%esi, %esi
	callq	_WREG32_P
LBB0_7:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_mmUVD_POWER_STATUS,4,2         ## @mmUVD_POWER_STATUS
	.comm	_mmUVD_MASTINT_EN,4,2           ## @mmUVD_MASTINT_EN
	.comm	_mmUVD_LMI_CTRL2,4,2            ## @mmUVD_LMI_CTRL2
	.comm	_mmUVD_SOFT_RESET,4,2           ## @mmUVD_SOFT_RESET
	.comm	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__RBC_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__RBC_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__CSM_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__CSM_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__CXW_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__CXW_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__TAP_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__TAP_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
	.comm	_mmSRBM_SOFT_RESET,4,2          ## @mmSRBM_SOFT_RESET
	.comm	_SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,4,2 ## @SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK
	.comm	_mmUVD_LMI_CTRL,4,2             ## @mmUVD_LMI_CTRL
	.comm	_mmUVD_LMI_SWAP_CNTL,4,2        ## @mmUVD_LMI_SWAP_CNTL
	.comm	_mmUVD_MP_SWAP_CNTL,4,2         ## @mmUVD_MP_SWAP_CNTL
	.comm	_mmUVD_MPC_SET_MUXA0,4,2        ## @mmUVD_MPC_SET_MUXA0
	.comm	_mmUVD_MPC_SET_MUXA1,4,2        ## @mmUVD_MPC_SET_MUXA1
	.comm	_mmUVD_MPC_SET_MUXB0,4,2        ## @mmUVD_MPC_SET_MUXB0
	.comm	_mmUVD_MPC_SET_MUXB1,4,2        ## @mmUVD_MPC_SET_MUXB1
	.comm	_mmUVD_MPC_SET_ALU,4,2          ## @mmUVD_MPC_SET_ALU
	.comm	_mmUVD_MPC_SET_MUX,4,2          ## @mmUVD_MPC_SET_MUX
	.comm	_mmUVD_VCPU_CNTL,4,2            ## @mmUVD_VCPU_CNTL
	.comm	_mmUVD_STATUS,4,2               ## @mmUVD_STATUS
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"UVD not responding, trying to reset the VCPU!!!\n"

L_.str.1:                               ## @.str.1
	.asciz	"UVD not responding, giving up!!!\n"

	.comm	_UVD_RBC_RB_CNTL,4,2            ## @UVD_RBC_RB_CNTL
	.comm	_RB_BUFSZ,4,2                   ## @RB_BUFSZ
	.comm	_RB_BLKSZ,4,2                   ## @RB_BLKSZ
	.comm	_RB_NO_FETCH,4,2                ## @RB_NO_FETCH
	.comm	_RB_WPTR_POLL_EN,4,2            ## @RB_WPTR_POLL_EN
	.comm	_RB_NO_UPDATE,4,2               ## @RB_NO_UPDATE
	.comm	_RB_RPTR_WR_EN,4,2              ## @RB_RPTR_WR_EN
	.comm	_mmUVD_RBC_RB_CNTL,4,2          ## @mmUVD_RBC_RB_CNTL
	.comm	_mmUVD_RBC_RB_WPTR_CNTL,4,2     ## @mmUVD_RBC_RB_WPTR_CNTL
	.comm	_mmUVD_RBC_RB_RPTR_ADDR,4,2     ## @mmUVD_RBC_RB_RPTR_ADDR
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
	.comm	_mmUVD_RBC_RB_RPTR,4,2          ## @mmUVD_RBC_RB_RPTR
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ## @mmUVD_RBC_RB_WPTR
	.comm	_UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK,4,2 ## @UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK
	.no_dead_strip	_uvd_v5_0_start
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function uvd_v5_0_start
_uvd_v5_0_start:                        ; @uvd_v5_0_start
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldr	x20, [x0]
Lloh0:
	adrp	x8, _mmUVD_POWER_STATUS@GOTPAGE
Lloh1:
	ldr	x8, [x8, _mmUVD_POWER_STATUS@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	mov	w1, #0
	mov	w2, #-5
	bl	_WREG32_P
	mov	x0, x19
	bl	_uvd_v5_0_mc_resume
Lloh3:
	adrp	x21, _mmUVD_MASTINT_EN@GOTPAGE
Lloh4:
	ldr	x21, [x21, _mmUVD_MASTINT_EN@GOTPAGEOFF]
	ldr	w0, [x21]
	mov	w1, #0
	mov	w2, #-3
	bl	_WREG32_P
Lloh5:
	adrp	x19, _mmUVD_LMI_CTRL2@GOTPAGE
Lloh6:
	ldr	x19, [x19, _mmUVD_LMI_CTRL2@GOTPAGEOFF]
	ldr	w0, [x19]
	mov	w1, #256
	mov	w2, #-257
	bl	_WREG32_P
	mov	w0, #1
	bl	_mdelay
Lloh7:
	adrp	x22, _mmUVD_SOFT_RESET@GOTPAGE
Lloh8:
	ldr	x22, [x22, _mmUVD_SOFT_RESET@GOTPAGEOFF]
Lloh9:
	adrp	x8, _UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPAGEOFF]
	ldr	w0, [x22]
Lloh11:
	ldr	w8, [x8]
Lloh12:
	adrp	x23, _UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPAGE
Lloh13:
	ldr	x23, [x23, _UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPAGEOFF]
	ldr	w9, [x23]
	orr	w8, w9, w8
Lloh14:
	adrp	x9, _UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK@GOTPAGE
Lloh15:
	ldr	x9, [x9, _UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh17:
	adrp	x9, _UVD_SOFT_RESET__RBC_SOFT_RESET_MASK@GOTPAGE
Lloh18:
	ldr	x9, [x9, _UVD_SOFT_RESET__RBC_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh20:
	adrp	x9, _UVD_SOFT_RESET__CSM_SOFT_RESET_MASK@GOTPAGE
Lloh21:
	ldr	x9, [x9, _UVD_SOFT_RESET__CSM_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh23:
	adrp	x9, _UVD_SOFT_RESET__CXW_SOFT_RESET_MASK@GOTPAGE
Lloh24:
	ldr	x9, [x9, _UVD_SOFT_RESET__CXW_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh26:
	adrp	x9, _UVD_SOFT_RESET__TAP_SOFT_RESET_MASK@GOTPAGE
Lloh27:
	ldr	x9, [x9, _UVD_SOFT_RESET__TAP_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh28:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh29:
	adrp	x9, _UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPAGE
Lloh30:
	ldr	x9, [x9, _UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh31:
	ldr	w9, [x9]
	orr	w1, w8, w9
	bl	_WREG32
	mov	w0, #5
	bl	_mdelay
Lloh32:
	adrp	x8, _mmSRBM_SOFT_RESET@GOTPAGE
Lloh33:
	ldr	x8, [x8, _mmSRBM_SOFT_RESET@GOTPAGEOFF]
Lloh34:
	ldr	w0, [x8]
Lloh35:
	adrp	x8, _SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK@GOTPAGE
Lloh36:
	ldr	x8, [x8, _SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK@GOTPAGEOFF]
Lloh37:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	mov	w0, #5
	bl	_mdelay
Lloh38:
	adrp	x8, _mmUVD_LMI_CTRL@GOTPAGE
Lloh39:
	ldr	x8, [x8, _mmUVD_LMI_CTRL@GOTPAGEOFF]
Lloh40:
	ldr	w0, [x8]
	mov	w1, #9024
	movk	w1, #48, lsl #16
	bl	_WREG32
Lloh41:
	adrp	x8, _mmUVD_LMI_SWAP_CNTL@GOTPAGE
Lloh42:
	ldr	x8, [x8, _mmUVD_LMI_SWAP_CNTL@GOTPAGEOFF]
Lloh43:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh44:
	adrp	x8, _mmUVD_MP_SWAP_CNTL@GOTPAGE
Lloh45:
	ldr	x8, [x8, _mmUVD_MP_SWAP_CNTL@GOTPAGEOFF]
Lloh46:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh47:
	adrp	x8, _mmUVD_MPC_SET_MUXA0@GOTPAGE
Lloh48:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXA0@GOTPAGEOFF]
Lloh49:
	ldr	w0, [x8]
	mov	w1, #8256
	movk	w1, #1036, lsl #16
	bl	_WREG32
Lloh50:
	adrp	x8, _mmUVD_MPC_SET_MUXA1@GOTPAGE
Lloh51:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXA1@GOTPAGEOFF]
Lloh52:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh53:
	adrp	x8, _mmUVD_MPC_SET_MUXB0@GOTPAGE
Lloh54:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXB0@GOTPAGEOFF]
Lloh55:
	ldr	w0, [x8]
	mov	w1, #8256
	movk	w1, #1036, lsl #16
	bl	_WREG32
Lloh56:
	adrp	x8, _mmUVD_MPC_SET_MUXB1@GOTPAGE
Lloh57:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXB1@GOTPAGEOFF]
Lloh58:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh59:
	adrp	x8, _mmUVD_MPC_SET_ALU@GOTPAGE
Lloh60:
	ldr	x8, [x8, _mmUVD_MPC_SET_ALU@GOTPAGEOFF]
Lloh61:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh62:
	adrp	x8, _mmUVD_MPC_SET_MUX@GOTPAGE
Lloh63:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUX@GOTPAGEOFF]
Lloh64:
	ldr	w0, [x8]
	mov	w1, #136
	bl	_WREG32
	ldr	w0, [x22]
	ldr	w1, [x23]
	bl	_WREG32
	mov	w0, #5
	bl	_mdelay
Lloh65:
	adrp	x8, _mmUVD_VCPU_CNTL@GOTPAGE
Lloh66:
	ldr	x8, [x8, _mmUVD_VCPU_CNTL@GOTPAGEOFF]
Lloh67:
	ldr	w0, [x8]
	mov	w1, #512
	bl	_WREG32
	ldr	w0, [x19]
	mov	w1, #0
	mov	w2, #-257
	bl	_WREG32_P
	ldr	w0, [x22]
	mov	w1, #0
	bl	_WREG32
	mov	w0, #10
	bl	_mdelay
	mov	w25, #0
Lloh68:
	adrp	x24, _mmUVD_STATUS@GOTPAGE
Lloh69:
	ldr	x24, [x24, _mmUVD_STATUS@GOTPAGEOFF]
Lloh70:
	adrp	x19, l_.str@PAGE
Lloh71:
	add	x19, x19, l_.str@PAGEOFF
LBB0_1:                                 ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
	mov	w26, #100
LBB0_2:                                 ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ldr	w0, [x24]
	bl	_RREG32
	tbnz	w0, #1, LBB0_6
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=2
	mov	w0, #10
	bl	_mdelay
	subs	w26, w26, #1
	b.ne	LBB0_2
; %bb.4:                                ;   in Loop: Header=BB0_1 Depth=1
	mov	x0, x19
	bl	_DRM_ERROR
	ldr	w0, [x22]
	ldr	w1, [x23]
	mvn	w2, w1
	bl	_WREG32_P
	mov	w0, #10
	bl	_mdelay
	ldr	w0, [x22]
	ldr	w8, [x23]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	mov	w0, #10
	bl	_mdelay
	add	w25, w25, #1
	cmp	w25, #10
	b.ne	LBB0_1
; %bb.5:
Lloh72:
	adrp	x0, l_.str.1@PAGE
Lloh73:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_ERROR
	mov	w0, #-1
	b	LBB0_7
LBB0_6:
	ldr	w0, [x21]
	mov	w1, #6
	mov	w2, #-7
	bl	_WREG32_P
	ldr	w0, [x24]
	mov	w1, #0
	mov	w2, #-5
	bl	_WREG32_P
	ldr	w0, [x20, #16]
	bl	_order_base_2
	mov	x3, x0
Lloh74:
	adrp	x19, _UVD_RBC_RB_CNTL@GOTPAGE
Lloh75:
	ldr	x19, [x19, _UVD_RBC_RB_CNTL@GOTPAGEOFF]
	ldr	w1, [x19]
Lloh76:
	adrp	x8, _RB_BUFSZ@GOTPAGE
Lloh77:
	ldr	x8, [x8, _RB_BUFSZ@GOTPAGEOFF]
Lloh78:
	ldr	w2, [x8]
	mov	w0, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh79:
	adrp	x8, _RB_BLKSZ@GOTPAGE
Lloh80:
	ldr	x8, [x8, _RB_BLKSZ@GOTPAGEOFF]
Lloh81:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh82:
	adrp	x8, _RB_NO_FETCH@GOTPAGE
Lloh83:
	ldr	x8, [x8, _RB_NO_FETCH@GOTPAGEOFF]
Lloh84:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh85:
	adrp	x8, _RB_WPTR_POLL_EN@GOTPAGE
Lloh86:
	ldr	x8, [x8, _RB_WPTR_POLL_EN@GOTPAGEOFF]
Lloh87:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh88:
	adrp	x8, _RB_NO_UPDATE@GOTPAGE
Lloh89:
	ldr	x8, [x8, _RB_NO_UPDATE@GOTPAGEOFF]
Lloh90:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh91:
	adrp	x8, _RB_RPTR_WR_EN@GOTPAGE
Lloh92:
	ldr	x8, [x8, _RB_RPTR_WR_EN@GOTPAGEOFF]
Lloh93:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x1, x0
Lloh94:
	adrp	x21, _mmUVD_RBC_RB_CNTL@GOTPAGE
Lloh95:
	ldr	x21, [x21, _mmUVD_RBC_RB_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_WREG32
Lloh96:
	adrp	x8, _mmUVD_RBC_RB_WPTR_CNTL@GOTPAGE
Lloh97:
	ldr	x8, [x8, _mmUVD_RBC_RB_WPTR_CNTL@GOTPAGEOFF]
Lloh98:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh99:
	adrp	x8, _mmUVD_RBC_RB_RPTR_ADDR@GOTPAGE
Lloh100:
	ldr	x8, [x8, _mmUVD_RBC_RB_RPTR_ADDR@GOTPAGEOFF]
Lloh101:
	ldr	w19, [x8]
	ldr	x0, [x20, #8]
	bl	_upper_32_bits
	asr	w1, w0, #2
	mov	x0, x19
	bl	_WREG32
Lloh102:
	adrp	x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPAGE
Lloh103:
	ldr	x8, [x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh104:
	ldr	w19, [x8]
	ldr	x0, [x20, #8]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_WREG32
Lloh105:
	adrp	x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPAGE
Lloh106:
	ldr	x8, [x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh107:
	ldr	w19, [x8]
	ldr	x0, [x20, #8]
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_WREG32
Lloh108:
	adrp	x19, _mmUVD_RBC_RB_RPTR@GOTPAGE
Lloh109:
	ldr	x19, [x19, _mmUVD_RBC_RB_RPTR@GOTPAGEOFF]
	ldr	w0, [x19]
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x19]
	bl	_RREG32
	str	x0, [x20]
Lloh110:
	adrp	x8, _mmUVD_RBC_RB_WPTR@GOTPAGE
Lloh111:
	ldr	x8, [x8, _mmUVD_RBC_RB_WPTR@GOTPAGEOFF]
Lloh112:
	ldr	w19, [x8]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_WREG32
	ldr	w0, [x21]
Lloh113:
	adrp	x8, _UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK@GOTPAGE
Lloh114:
	ldr	x8, [x8, _UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK@GOTPAGEOFF]
Lloh115:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	mov	w0, #0
LBB0_7:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh70, Lloh71
	.loh AdrpLdrGot	Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGot	Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGot	Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGot	Lloh74, Lloh75
	.cfi_endproc
                                        ; -- End function
	.comm	_mmUVD_POWER_STATUS,4,2         ; @mmUVD_POWER_STATUS
	.comm	_mmUVD_MASTINT_EN,4,2           ; @mmUVD_MASTINT_EN
	.comm	_mmUVD_LMI_CTRL2,4,2            ; @mmUVD_LMI_CTRL2
	.comm	_mmUVD_SOFT_RESET,4,2           ; @mmUVD_SOFT_RESET
	.comm	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__RBC_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__RBC_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__CSM_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__CSM_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__CXW_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__CXW_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__TAP_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__TAP_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
	.comm	_mmSRBM_SOFT_RESET,4,2          ; @mmSRBM_SOFT_RESET
	.comm	_SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,4,2 ; @SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK
	.comm	_mmUVD_LMI_CTRL,4,2             ; @mmUVD_LMI_CTRL
	.comm	_mmUVD_LMI_SWAP_CNTL,4,2        ; @mmUVD_LMI_SWAP_CNTL
	.comm	_mmUVD_MP_SWAP_CNTL,4,2         ; @mmUVD_MP_SWAP_CNTL
	.comm	_mmUVD_MPC_SET_MUXA0,4,2        ; @mmUVD_MPC_SET_MUXA0
	.comm	_mmUVD_MPC_SET_MUXA1,4,2        ; @mmUVD_MPC_SET_MUXA1
	.comm	_mmUVD_MPC_SET_MUXB0,4,2        ; @mmUVD_MPC_SET_MUXB0
	.comm	_mmUVD_MPC_SET_MUXB1,4,2        ; @mmUVD_MPC_SET_MUXB1
	.comm	_mmUVD_MPC_SET_ALU,4,2          ; @mmUVD_MPC_SET_ALU
	.comm	_mmUVD_MPC_SET_MUX,4,2          ; @mmUVD_MPC_SET_MUX
	.comm	_mmUVD_VCPU_CNTL,4,2            ; @mmUVD_VCPU_CNTL
	.comm	_mmUVD_STATUS,4,2               ; @mmUVD_STATUS
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"UVD not responding, trying to reset the VCPU!!!\n"

l_.str.1:                               ; @.str.1
	.asciz	"UVD not responding, giving up!!!\n"

	.comm	_UVD_RBC_RB_CNTL,4,2            ; @UVD_RBC_RB_CNTL
	.comm	_RB_BUFSZ,4,2                   ; @RB_BUFSZ
	.comm	_RB_BLKSZ,4,2                   ; @RB_BLKSZ
	.comm	_RB_NO_FETCH,4,2                ; @RB_NO_FETCH
	.comm	_RB_WPTR_POLL_EN,4,2            ; @RB_WPTR_POLL_EN
	.comm	_RB_NO_UPDATE,4,2               ; @RB_NO_UPDATE
	.comm	_RB_RPTR_WR_EN,4,2              ; @RB_RPTR_WR_EN
	.comm	_mmUVD_RBC_RB_CNTL,4,2          ; @mmUVD_RBC_RB_CNTL
	.comm	_mmUVD_RBC_RB_WPTR_CNTL,4,2     ; @mmUVD_RBC_RB_WPTR_CNTL
	.comm	_mmUVD_RBC_RB_RPTR_ADDR,4,2     ; @mmUVD_RBC_RB_RPTR_ADDR
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
	.comm	_mmUVD_RBC_RB_RPTR,4,2          ; @mmUVD_RBC_RB_RPTR
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ; @mmUVD_RBC_RB_WPTR
	.comm	_UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK,4,2 ; @UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK
	.no_dead_strip	_uvd_v5_0_start
.subsections_via_symbols
