	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_ib_schedule             ## -- Begin function amdgpu_ib_schedule
	.p2align	4, 0x90
_amdgpu_ib_schedule:                    ## @amdgpu_ib_schedule
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	testl	%esi, %esi
	je	LBB0_4
## %bb.1:
	movq	%rcx, %r12
	movq	%rdx, %rbx
	movl	%esi, %r15d
	movq	%rdi, %r13
	movq	24(%rdi), %rdx
	testq	%rcx, %rcx
	je	LBB0_5
## %bb.2:
	movq	24(%r12), %rax
	testq	%rax, %rax
	je	LBB0_7
## %bb.3:
	movl	(%rax), %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	cmpl	$0, 20(%r13)
	jne	LBB0_8
	jmp	LBB0_14
LBB0_4:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r14d, %r14d
	subl	(%rax), %r14d
	jmp	LBB0_69
LBB0_5:
	cmpl	$0, 20(%r13)
	je	LBB0_14
## %bb.6:
	movq	%r8, -80(%rbp)                  ## 8-byte Spill
	movl	$0, -44(%rbp)                   ## 4-byte Folded Spill
	jmp	LBB0_11
LBB0_7:
	movl	$0, -44(%rbp)                   ## 4-byte Folded Spill
	cmpl	$0, 20(%r13)
	je	LBB0_14
LBB0_8:
	cmpq	$0, 32(%r12)
	movq	%r8, -80(%rbp)                  ## 8-byte Spill
	je	LBB0_11
## %bb.9:
	xorl	%r14d, %r14d
	cmpl	$0, 8(%r12)
	jne	LBB0_12
## %bb.10:
	movl	4(%rdx), %edi
	leaq	L_.str.1(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_15
LBB0_11:
	movb	$1, %r14b
LBB0_12:
	movq	%rdx, -56(%rbp)                 ## 8-byte Spill
	movl	%r14d, -68(%rbp)                ## 4-byte Spill
	movq	8(%r13), %rax
	movl	4(%rax), %esi
	imull	%r15d, %esi
	addl	(%rax), %esi
	movq	%r13, %rdi
	callq	_amdgpu_ring_alloc
	testl	%eax, %eax
	je	LBB0_16
## %bb.13:
	movl	%eax, %r14d
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	4(%rax), %edi
	leaq	L_.str.2(%rip), %rsi
	movl	%r14d, %edx
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_69
LBB0_14:
	movl	4(%rdx), %edi
	movl	(%r13), %edx
	leaq	L_.str(%rip), %rsi
	xorl	%r14d, %r14d
	xorl	%eax, %eax
	callq	_dev_err
LBB0_15:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	subl	(%rax), %r14d
	jmp	LBB0_69
LBB0_16:
	movl	%r15d, -60(%rbp)                ## 4-byte Spill
	xorl	%r14d, %r14d
	movl	16(%r13), %r15d
	testq	%r12, %r12
	je	LBB0_24
## %bb.17:
	movq	8(%r13), %rax
	cmpq	$0, 80(%rax)
	je	LBB0_24
## %bb.18:
	leaq	20(%r12), %rdi
	xorl	%esi, %esi
	callq	_amdgpu_sync_get_fence
	movq	%rax, %r14
	testq	%rax, %rax
	je	LBB0_20
## %bb.19:
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	_trace_amdgpu_ib_pipe_sync
	jmp	LBB0_23
LBB0_20:
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_22
## %bb.21:
	cmpl	-44(%rbp), %r15d                ## 4-byte Folded Reload
	jne	LBB0_23
LBB0_22:
	movq	%r13, %rdi
	movq	%r12, %rsi
	callq	_amdgpu_vm_need_pipeline_sync
	testq	%rax, %rax
	je	LBB0_70
LBB0_23:
	movq	%r14, %rdi
	callq	_dma_fence_put
	movl	$1, %r14d
LBB0_24:
	movl	%r15d, -48(%rbp)                ## 4-byte Spill
	movq	8(%r13), %rax
	movq	72(%rax), %rax
	testq	%rax, %rax
	je	LBB0_26
## %bb.25:
	movq	%r13, %rdi
	callq	*%rax
LBB0_26:
	movl	$-1, %r15d
	testq	%r12, %r12
	je	LBB0_31
## %bb.27:
	movq	%r13, %rdi
	movq	%r12, %rsi
	movl	%r14d, %edx
	callq	_amdgpu_vm_flush
	testl	%eax, %eax
	je	LBB0_29
## %bb.28:
	movl	%eax, %r14d
	jmp	LBB0_59
LBB0_29:
	movq	8(%r13), %rax
	cmpq	$0, 64(%rax)
	je	LBB0_31
## %bb.30:
	movq	%r13, %rdi
	callq	_amdgpu_ring_init_cond_exec
	movl	%eax, %r15d
LBB0_31:
	movq	8(%r13), %rax
	cmpq	$0, 56(%rax)
	je	LBB0_33
## %bb.32:
	movq	%r13, %rdi
	callq	_amdgpu_ring_emit_hdp_flush
	jmp	LBB0_34
LBB0_33:
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	movq	%r13, %rsi
	callq	_amdgpu_asic_flush_hdp
LBB0_34:
	xorl	%r14d, %r14d
	movl	-48(%rbp), %eax                 ## 4-byte Reload
	cmpl	-44(%rbp), %eax                 ## 4-byte Folded Reload
	movl	-60(%rbp), %ecx                 ## 4-byte Reload
	je	LBB0_36
## %bb.35:
	movq	_AMDGPU_HAVE_CTX_SWITCH@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
LBB0_36:
	movq	%r13, %rdi
	movl	16(%r13), %eax
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	testq	%r12, %r12
	movl	%r15d, -64(%rbp)                ## 4-byte Spill
	je	LBB0_40
## %bb.37:
	movq	8(%rdi), %rax
	cmpq	$0, 48(%rax)
	je	LBB0_40
## %bb.38:
	orl	(%r12), %r14d
	orl	4(%r12), %r14d
	movq	%rdi, %r13
	movl	%r14d, %esi
	callq	_amdgpu_ring_emit_cntxcntl
	movl	-60(%rbp), %ecx                 ## 4-byte Reload
	jmp	LBB0_41
LBB0_40:
	movq	%rdi, %r13
LBB0_41:
	movl	%ecx, %r15d
	jmp	LBB0_44
	.p2align	4, 0x90
LBB0_42:                                ##   in Loop: Header=BB0_44 Depth=1
	movq	%r13, %rdi
	movq	%r12, %rsi
	movq	%rbx, %rdx
	movl	%r14d, %ecx
	callq	_amdgpu_ring_emit_ib
	movq	_AMDGPU_HAVE_CTX_SWITCH@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r14d
LBB0_43:                                ##   in Loop: Header=BB0_44 Depth=1
	addq	$4, %rbx
	decq	%r15
	je	LBB0_48
LBB0_44:                                ## =>This Inner Loop Header: Depth=1
	movq	_AMDGPU_IB_FLAG_PREAMBLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rbx)
	je	LBB0_42
## %bb.45:                              ##   in Loop: Header=BB0_44 Depth=1
	movl	-48(%rbp), %eax                 ## 4-byte Reload
	cmpl	-44(%rbp), %eax                 ## 4-byte Folded Reload
	jne	LBB0_42
## %bb.46:                              ##   in Loop: Header=BB0_44 Depth=1
	movq	_AMDGPU_PREAMBLE_IB_PRESENT_FIRST@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r14d, %eax
	movq	_amdgpu_mcbp@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	jne	LBB0_42
## %bb.47:                              ##   in Loop: Header=BB0_44 Depth=1
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	jne	LBB0_42
	jmp	LBB0_43
LBB0_48:
	movq	8(%r13), %rax
	cmpq	$0, 40(%rax)
	je	LBB0_50
## %bb.49:
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_emit_tmz
LBB0_50:
	movq	-56(%rbp), %r15                 ## 8-byte Reload
	movq	%r15, %rdi
	movq	%r13, %rsi
	callq	_amdgpu_asic_invalidate_hdp
	movq	_AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	andl	-4(%rbx), %r14d
	je	LBB0_52
## %bb.51:
	movq	_AMDGPU_FENCE_FLAG_TC_WB_ONLY@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
LBB0_52:
	testq	%r12, %r12
	je	LBB0_55
## %bb.53:
	movl	16(%r12), %esi
	testl	%esi, %esi
	je	LBB0_55
## %bb.54:
	movl	12(%r12), %edx
	movq	_AMDGPU_FENCE_FLAG_64BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	orl	%r14d, %ecx
	movq	%r13, %rdi
	callq	_amdgpu_ring_emit_fence
LBB0_55:
	movq	%r13, %rdi
	movq	-80(%rbp), %rsi                 ## 8-byte Reload
	movl	%r14d, %edx
	callq	_amdgpu_fence_emit
	testl	%eax, %eax
	je	LBB0_60
## %bb.56:
	movl	%eax, %r14d
	movl	4(%r15), %edi
	leaq	L_.str.3(%rip), %rsi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_dev_err
	testq	%r12, %r12
	je	LBB0_59
## %bb.57:
	movl	8(%r12), %edx
	testl	%edx, %edx
	je	LBB0_59
## %bb.58:
	movq	8(%r13), %rax
	movl	32(%rax), %esi
	movq	%r15, %rdi
	callq	_amdgpu_vmid_reset
LBB0_59:
	movq	%r13, %rdi
	callq	_amdgpu_ring_undo
	jmp	LBB0_69
LBB0_60:
	movq	8(%r13), %rax
	movq	24(%rax), %rax
	testq	%rax, %rax
	je	LBB0_62
## %bb.61:
	movq	%r13, %rdi
	callq	*%rax
LBB0_62:
	movl	-64(%rbp), %esi                 ## 4-byte Reload
	cmpl	$-1, %esi
	movl	-68(%rbp), %ebx                 ## 4-byte Reload
	je	LBB0_65
## %bb.63:
	movq	8(%r13), %rax
	cmpq	$0, 16(%rax)
	je	LBB0_65
## %bb.64:
	movq	%r13, %rdi
	callq	_amdgpu_ring_patch_cond_exec
LBB0_65:
	movl	-44(%rbp), %eax                 ## 4-byte Reload
	movl	%eax, 16(%r13)
	testb	%bl, %bl
	jne	LBB0_68
## %bb.66:
	movq	8(%r13), %rax
	cmpq	$0, 8(%rax)
	je	LBB0_68
## %bb.67:
	movq	%r13, %rdi
	callq	_amdgpu_ring_emit_switch_buffer
LBB0_68:
	movq	%r13, %rdi
	callq	_amdgpu_ring_commit
	xorl	%r14d, %r14d
LBB0_69:
	movl	%r14d, %eax
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_70:
	xorl	%r14d, %r14d
	jmp	LBB0_24
	.cfi_endproc
                                        ## -- End function
	.comm	_EINVAL,4,2                     ## @EINVAL
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"couldn't schedule ib on ring <%s>\n"

L_.str.1:                               ## @.str.1
	.asciz	"VM IB without ID\n"

L_.str.2:                               ## @.str.2
	.asciz	"scheduling IB failed (%d).\n"

	.comm	_AMDGPU_HAVE_CTX_SWITCH,4,2     ## @AMDGPU_HAVE_CTX_SWITCH
	.comm	_AMDGPU_IB_FLAG_PREAMBLE,4,2    ## @AMDGPU_IB_FLAG_PREAMBLE
	.comm	_AMDGPU_PREAMBLE_IB_PRESENT_FIRST,4,2 ## @AMDGPU_PREAMBLE_IB_PRESENT_FIRST
	.comm	_amdgpu_mcbp,4,2                ## @amdgpu_mcbp
	.comm	_AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE,4,2 ## @AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE
	.comm	_AMDGPU_FENCE_FLAG_TC_WB_ONLY,4,2 ## @AMDGPU_FENCE_FLAG_TC_WB_ONLY
	.comm	_AMDGPU_FENCE_FLAG_64BIT,4,2    ## @AMDGPU_FENCE_FLAG_64BIT
L_.str.3:                               ## @.str.3
	.asciz	"failed to emit fence (%d)\n"

	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_ib_schedule             ; -- Begin function amdgpu_ib_schedule
	.p2align	2
_amdgpu_ib_schedule:                    ; @amdgpu_ib_schedule
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #144
	.cfi_def_cfa_offset 144
	stp	x28, x27, [sp, #48]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #64]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #80]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #96]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #112]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #128]            ; 16-byte Folded Spill
	add	x29, sp, #128
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	cbz	w1, LBB0_15
; %bb.1:
	mov	x22, x4
	mov	x21, x3
	mov	x23, x2
	mov	x24, x1
	mov	x19, x0
	ldr	x20, [x0, #24]
	cbz	x3, LBB0_4
; %bb.2:
	ldr	x8, [x21, #24]
	cbz	x8, LBB0_6
; %bb.3:
	ldr	w27, [x8]
	ldr	w8, [x19, #20]
	cbnz	w8, LBB0_7
	b	LBB0_13
LBB0_4:
	ldr	w8, [x19, #20]
	cbz	w8, LBB0_13
; %bb.5:
	mov	w27, #0
	b	LBB0_10
LBB0_6:
	mov	w27, #0
	ldr	w8, [x19, #20]
	cbz	w8, LBB0_13
LBB0_7:
	ldr	x8, [x21, #32]
	cbz	x8, LBB0_10
; %bb.8:
	ldr	w8, [x21, #8]
	cbz	w8, LBB0_21
; %bb.9:
	mov	w25, #0
	b	LBB0_11
LBB0_10:
	mov	w25, #1
LBB0_11:
	ldr	x8, [x19, #8]
	ldp	w9, w8, [x8]
	madd	w1, w8, w24, w9
	mov	x0, x19
	bl	_amdgpu_ring_alloc
	cbz	w0, LBB0_17
; %bb.12:
	mov	x26, x0
	ldr	w0, [x20, #4]
	str	x26, [sp]
Lloh0:
	adrp	x1, l_.str.2@PAGE
Lloh1:
	add	x1, x1, l_.str.2@PAGEOFF
	bl	_dev_err
                                        ; kill: def $w26 killed $w26 killed $x26 def $x26
	b	LBB0_16
LBB0_13:
	ldr	w0, [x20, #4]
	ldr	w8, [x19]
	str	x8, [sp]
Lloh2:
	adrp	x1, l_.str@PAGE
Lloh3:
	add	x1, x1, l_.str@PAGEOFF
LBB0_14:
	bl	_dev_err
LBB0_15:
Lloh4:
	adrp	x8, _EINVAL@GOTPAGE
Lloh5:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
	neg	w26, w8
LBB0_16:
	mov	x0, x26
	ldp	x29, x30, [sp, #128]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #112]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #96]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #80]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #64]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #144
	ret
LBB0_17:
	str	w25, [sp, #36]                  ; 4-byte Folded Spill
	mov	w25, #0
	ldr	w28, [x19, #16]
	cbz	x21, LBB0_26
; %bb.18:
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #80]
	cbz	x8, LBB0_26
; %bb.19:
	add	x0, x21, #20
	mov	x1, #0
	bl	_amdgpu_sync_get_fence
	mov	x25, x0
	cbz	x0, LBB0_22
; %bb.20:
	mov	x0, x21
	mov	x1, x25
	bl	_trace_amdgpu_ib_pipe_sync
	b	LBB0_25
LBB0_21:
	ldr	w0, [x20, #4]
Lloh7:
	adrp	x1, l_.str.1@PAGE
Lloh8:
	add	x1, x1, l_.str.1@PAGEOFF
	b	LBB0_14
LBB0_22:
	mov	x0, x20
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_24
; %bb.23:
	cmp	w28, w27
	b.ne	LBB0_25
LBB0_24:
	mov	x0, x19
	mov	x1, x21
	bl	_amdgpu_vm_need_pipeline_sync
	cbz	x0, LBB0_65
LBB0_25:
	mov	x0, x25
	bl	_dma_fence_put
	mov	w25, #1
LBB0_26:
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #72]
	cbz	x8, LBB0_28
; %bb.27:
	mov	x0, x19
	blr	x8
LBB0_28:
	cbz	x21, LBB0_33
; %bb.29:
	mov	x0, x19
	mov	x1, x21
	mov	x2, x25
	bl	_amdgpu_vm_flush
	cbz	w0, LBB0_31
; %bb.30:
	mov	x26, x0
	b	LBB0_55
LBB0_31:
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #64]
	cbz	x8, LBB0_33
; %bb.32:
	mov	x0, x19
	bl	_amdgpu_ring_init_cond_exec
	b	LBB0_34
LBB0_33:
	mov	w0, #-1
LBB0_34:
	str	w0, [sp, #20]                   ; 4-byte Folded Spill
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #56]
	cbz	x8, LBB0_36
; %bb.35:
	mov	x0, x19
	bl	_amdgpu_ring_emit_hdp_flush
	b	LBB0_37
LBB0_36:
	mov	x0, x20
	mov	x1, x19
	bl	_amdgpu_asic_flush_hdp
LBB0_37:
Lloh9:
	adrp	x25, _AMDGPU_HAVE_CTX_SWITCH@GOTPAGE
Lloh10:
	ldr	x25, [x25, _AMDGPU_HAVE_CTX_SWITCH@GOTPAGEOFF]
	ldr	w8, [x25]
	cmp	w28, w27
	csel	w26, w8, wzr, ne
	ldr	w28, [x19, #16]
	str	x20, [sp, #40]                  ; 8-byte Folded Spill
	str	x22, [sp, #24]                  ; 8-byte Folded Spill
	cbz	x21, LBB0_40
; %bb.38:
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #48]
	cbz	x8, LBB0_40
; %bb.39:
	ldp	w8, w9, [x21]
	orr	w8, w8, w26
	orr	w26, w8, w9
	mov	x0, x19
	mov	x1, x26
	bl	_amdgpu_ring_emit_cntxcntl
LBB0_40:
	mov	w24, w24
Lloh11:
	adrp	x22, _AMDGPU_IB_FLAG_PREAMBLE@GOTPAGE
Lloh12:
	ldr	x22, [x22, _AMDGPU_IB_FLAG_PREAMBLE@GOTPAGEOFF]
Lloh13:
	adrp	x20, _amdgpu_mcbp@GOTPAGE
Lloh14:
	ldr	x20, [x20, _amdgpu_mcbp@GOTPAGEOFF]
	b	LBB0_43
LBB0_41:                                ;   in Loop: Header=BB0_43 Depth=1
	mov	x0, x19
	mov	x1, x21
	mov	x2, x23
	mov	x3, x26
	bl	_amdgpu_ring_emit_ib
	ldr	w8, [x25]
	bic	w26, w26, w8
LBB0_42:                                ;   in Loop: Header=BB0_43 Depth=1
	add	x23, x23, #4
	subs	x24, x24, #1
	b.eq	LBB0_46
LBB0_43:                                ; =>This Inner Loop Header: Depth=1
	ldr	w8, [x23]
	ldr	w9, [x22]
	and	w8, w9, w8
	cmp	w8, #0
	ccmp	w28, w27, #0, ne
	b.ne	LBB0_41
; %bb.44:                               ;   in Loop: Header=BB0_43 Depth=1
Lloh15:
	adrp	x8, _AMDGPU_PREAMBLE_IB_PRESENT_FIRST@GOTPAGE
Lloh16:
	ldr	x8, [x8, _AMDGPU_PREAMBLE_IB_PRESENT_FIRST@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	and	w8, w8, w26
	ldr	w9, [x20]
	orr	w8, w8, w9
	cbnz	w8, LBB0_41
; %bb.45:                               ;   in Loop: Header=BB0_43 Depth=1
	ldr	x0, [sp, #40]                   ; 8-byte Folded Reload
	bl	_amdgpu_sriov_vf
	cbnz	x0, LBB0_41
	b	LBB0_42
LBB0_46:
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #40]
	cbz	x8, LBB0_48
; %bb.47:
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_ring_emit_tmz
LBB0_48:
	ldr	x20, [sp, #40]                  ; 8-byte Folded Reload
	mov	x0, x20
	mov	x1, x19
	bl	_amdgpu_asic_invalidate_hdp
	ldur	w8, [x23, #-4]
Lloh18:
	adrp	x9, _AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE@GOTPAGE
Lloh19:
	ldr	x9, [x9, _AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
Lloh21:
	adrp	x10, _AMDGPU_FENCE_FLAG_TC_WB_ONLY@GOTPAGE
Lloh22:
	ldr	x10, [x10, _AMDGPU_FENCE_FLAG_TC_WB_ONLY@GOTPAGEOFF]
Lloh23:
	ldr	w10, [x10]
	tst	w9, w8
	csel	w23, wzr, w10, eq
	ldr	x22, [sp, #24]                  ; 8-byte Folded Reload
	ldr	w24, [sp, #36]                  ; 4-byte Folded Reload
	cbz	x21, LBB0_51
; %bb.49:
	ldr	w1, [x21, #16]
	cbz	w1, LBB0_51
; %bb.50:
	ldr	w2, [x21, #12]
Lloh24:
	adrp	x8, _AMDGPU_FENCE_FLAG_64BIT@GOTPAGE
Lloh25:
	ldr	x8, [x8, _AMDGPU_FENCE_FLAG_64BIT@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	orr	w3, w8, w23
	mov	x0, x19
	bl	_amdgpu_ring_emit_fence
LBB0_51:
	mov	x0, x19
	mov	x1, x22
	mov	x2, x23
	bl	_amdgpu_fence_emit
	cbz	w0, LBB0_56
; %bb.52:
	mov	x26, x0
	ldr	w0, [x20, #4]
	str	x26, [sp]
Lloh27:
	adrp	x1, l_.str.3@PAGE
Lloh28:
	add	x1, x1, l_.str.3@PAGEOFF
	bl	_dev_err
	cbz	x21, LBB0_55
; %bb.53:
	ldr	w2, [x21, #8]
	cbz	w2, LBB0_55
; %bb.54:
	ldr	x8, [x19, #8]
	ldr	w1, [x8, #32]
	mov	x0, x20
	bl	_amdgpu_vmid_reset
LBB0_55:
	mov	x0, x19
	bl	_amdgpu_ring_undo
	b	LBB0_16
LBB0_56:
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #24]
	cbz	x8, LBB0_58
; %bb.57:
	mov	x0, x19
	blr	x8
LBB0_58:
	ldr	w1, [sp, #20]                   ; 4-byte Folded Reload
	cmn	w1, #1
	b.eq	LBB0_61
; %bb.59:
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #16]
	cbz	x8, LBB0_61
; %bb.60:
	mov	x0, x19
	bl	_amdgpu_ring_patch_cond_exec
LBB0_61:
	str	w27, [x19, #16]
	tbnz	w24, #0, LBB0_64
; %bb.62:
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	cbz	x8, LBB0_64
; %bb.63:
	mov	x0, x19
	bl	_amdgpu_ring_emit_switch_buffer
LBB0_64:
	mov	x0, x19
	bl	_amdgpu_ring_commit
	mov	w26, #0
	b	LBB0_16
LBB0_65:
	mov	w25, #0
	b	LBB0_26
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpAdd	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpAdd	Lloh27, Lloh28
	.cfi_endproc
                                        ; -- End function
	.comm	_EINVAL,4,2                     ; @EINVAL
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"couldn't schedule ib on ring <%s>\n"

l_.str.1:                               ; @.str.1
	.asciz	"VM IB without ID\n"

l_.str.2:                               ; @.str.2
	.asciz	"scheduling IB failed (%d).\n"

	.comm	_AMDGPU_HAVE_CTX_SWITCH,4,2     ; @AMDGPU_HAVE_CTX_SWITCH
	.comm	_AMDGPU_IB_FLAG_PREAMBLE,4,2    ; @AMDGPU_IB_FLAG_PREAMBLE
	.comm	_AMDGPU_PREAMBLE_IB_PRESENT_FIRST,4,2 ; @AMDGPU_PREAMBLE_IB_PRESENT_FIRST
	.comm	_amdgpu_mcbp,4,2                ; @amdgpu_mcbp
	.comm	_AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE,4,2 ; @AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE
	.comm	_AMDGPU_FENCE_FLAG_TC_WB_ONLY,4,2 ; @AMDGPU_FENCE_FLAG_TC_WB_ONLY
	.comm	_AMDGPU_FENCE_FLAG_64BIT,4,2    ; @AMDGPU_FENCE_FLAG_64BIT
l_.str.3:                               ; @.str.3
	.asciz	"failed to emit fence (%d)\n"

	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
.subsections_via_symbols
