	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function amdgpu_set_pp_force_state
_amdgpu_set_pp_force_state:             ## @amdgpu_set_pp_force_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rcx, %r14
	movq	%rdx, %rbx
	callq	_dev_get_drvdata
	movq	(%rax), %r15
	movq	%rbx, %rdi
	callq	_strlen
	cmpl	$1, %eax
	je	LBB0_3
## %bb.2:
	movq	%r15, %rdi
	callq	_is_support_sw_smu
	testq	%rax, %rax
	je	LBB0_5
LBB0_3:
	movl	$0, (%r15)
LBB0_4:
	movq	%r14, %rax
	addq	$24, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_5:
	movq	8(%r15), %rax
	cmpq	$0, 8(%rax)
	je	LBB0_4
## %bb.6:
	cmpq	$0, (%rax)
	je	LBB0_4
## %bb.7:
	leaq	-32(%rbp), %rdx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_kstrtoul
	testl	%eax, %eax
	jne	LBB0_12
## %bb.8:
	movq	-32(%rbp), %rbx
	callq	_ARRAY_SIZE
	cmpq	%rax, %rbx
	jae	LBB0_12
## %bb.9:
	movq	-32(%rbp), %rbx
	callq	_ARRAY_SIZE
	movq	%rbx, %rdi
	movq	%rax, %rsi
	callq	_array_index_nospec
	movq	%rax, -32(%rbp)
	leaq	-48(%rbp), %rsi
	movq	%r15, %rdi
	callq	_amdgpu_dpm_get_pp_num_states
	movq	-48(%rbp), %rax
	movq	-32(%rbp), %rcx
	movl	(%rax,%rcx,4), %eax
	movl	%eax, -36(%rbp)
	movq	_POWER_STATE_TYPE_INTERNAL_BOOT@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_4
## %bb.10:
	movq	_POWER_STATE_TYPE_DEFAULT@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_4
## %bb.11:
	movq	_AMD_PP_TASK_ENABLE_USER_STATE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-36(%rbp), %rdx
	movq	%r15, %rdi
	callq	_amdgpu_dpm_dispatch_task
	movl	$1, (%r15)
	jmp	LBB0_4
LBB0_12:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r14d, %r14d
	subq	(%rax), %r14
	jmp	LBB0_4
	.cfi_endproc
                                        ## -- End function
	.comm	_EINVAL,8,3                     ## @EINVAL
	.comm	_POWER_STATE_TYPE_INTERNAL_BOOT,4,2 ## @POWER_STATE_TYPE_INTERNAL_BOOT
	.comm	_POWER_STATE_TYPE_DEFAULT,4,2   ## @POWER_STATE_TYPE_DEFAULT
	.comm	_AMD_PP_TASK_ENABLE_USER_STATE,4,2 ## @AMD_PP_TASK_ENABLE_USER_STATE
	.no_dead_strip	_amdgpu_set_pp_force_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function amdgpu_set_pp_force_state
_amdgpu_set_pp_force_state:             ; @amdgpu_set_pp_force_state
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x3
	mov	x21, x2
	bl	_dev_get_drvdata
	ldr	x20, [x0]
	mov	x0, x21
	bl	_strlen
	cmp	w0, #1
	b.eq	LBB0_2
; %bb.1:
	mov	x0, x20
	bl	_is_support_sw_smu
	cbz	x0, LBB0_4
LBB0_2:
	str	wzr, [x20]
LBB0_3:
	mov	x0, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
LBB0_4:
	ldr	x8, [x20, #8]
	ldr	x9, [x8, #8]
	cbz	x9, LBB0_3
; %bb.5:
	ldr	x8, [x8]
	cbz	x8, LBB0_3
; %bb.6:
	add	x2, sp, #16
	mov	x0, x21
	mov	w1, #0
	bl	_kstrtoul
	cbnz	w0, LBB0_11
; %bb.7:
	ldr	x21, [sp, #16]
	bl	_ARRAY_SIZE
	cmp	x21, x0
	b.hs	LBB0_11
; %bb.8:
	ldr	x21, [sp, #16]
	bl	_ARRAY_SIZE
	mov	x1, x0
	mov	x0, x21
	bl	_array_index_nospec
	str	x0, [sp, #16]
	add	x1, sp, #8
	mov	x0, x20
	bl	_amdgpu_dpm_get_pp_num_states
	ldp	x8, x9, [sp, #8]
	ldr	w8, [x8, x9, lsl #2]
	str	w8, [sp, #28]
Lloh0:
	adrp	x9, _POWER_STATE_TYPE_INTERNAL_BOOT@GOTPAGE
Lloh1:
	ldr	x9, [x9, _POWER_STATE_TYPE_INTERNAL_BOOT@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	cmp	w8, w9
	b.eq	LBB0_3
; %bb.9:
Lloh3:
	adrp	x9, _POWER_STATE_TYPE_DEFAULT@GOTPAGE
Lloh4:
	ldr	x9, [x9, _POWER_STATE_TYPE_DEFAULT@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	cmp	w8, w9
	b.eq	LBB0_3
; %bb.10:
Lloh6:
	adrp	x8, _AMD_PP_TASK_ENABLE_USER_STATE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _AMD_PP_TASK_ENABLE_USER_STATE@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	add	x2, sp, #28
	mov	x0, x20
	bl	_amdgpu_dpm_dispatch_task
	mov	w8, #1
	str	w8, [x20]
	b	LBB0_3
LBB0_11:
Lloh9:
	adrp	x8, _EINVAL@GOTPAGE
Lloh10:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh11:
	ldr	x8, [x8]
	neg	x19, x8
	b	LBB0_3
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.cfi_endproc
                                        ; -- End function
	.comm	_EINVAL,8,3                     ; @EINVAL
	.comm	_POWER_STATE_TYPE_INTERNAL_BOOT,4,2 ; @POWER_STATE_TYPE_INTERNAL_BOOT
	.comm	_POWER_STATE_TYPE_DEFAULT,4,2   ; @POWER_STATE_TYPE_DEFAULT
	.comm	_AMD_PP_TASK_ENABLE_USER_STATE,4,2 ; @AMD_PP_TASK_ENABLE_USER_STATE
	.no_dead_strip	_amdgpu_set_pp_force_state
.subsections_via_symbols
