	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v10_0_ring_emit_ib_compute
_gfx_v10_0_ring_emit_ib_compute:        ## @gfx_v10_0_ring_emit_ib_compute
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r15
	movq	%rdi, %r14
	movq	%rsi, %rdi
	callq	_AMDGPU_JOB_GET_VMID
	movl	%eax, %ebx
	movq	_INDIRECT_BUFFER_VALID@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	(%r15), %r12d
	movq	_AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 4(%r15)
	je	LBB0_2
## %bb.1:
	movq	_PACKET3_SET_CONFIG_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_PACKET3
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_mmGDS_COMPUTE_MAX_WAVE_ID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_amdgpu_ring_write
	movq	(%r14), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_amdgpu_ring_write
LBB0_2:
	shll	$24, %ebx
	orl	%r13d, %ebx
	orl	%r12d, %ebx
	movq	_PACKET3_INDIRECT_BUFFER@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$2, %esi
	callq	_PACKET3
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	8(%r15), %edi
	andl	$3, %edi
	callq	_BUG_ON
	movl	8(%r15), %edi
	callq	_lower_32_bits
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	8(%r15), %edi
	callq	_upper_32_bits
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r14, %rdi
	movl	%ebx, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_write              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_INDIRECT_BUFFER_VALID,4,2      ## @INDIRECT_BUFFER_VALID
	.comm	_AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID,4,2 ## @AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
	.comm	_PACKET3_SET_CONFIG_REG,4,2     ## @PACKET3_SET_CONFIG_REG
	.comm	_mmGDS_COMPUTE_MAX_WAVE_ID,4,2  ## @mmGDS_COMPUTE_MAX_WAVE_ID
	.comm	_PACKET3_INDIRECT_BUFFER,4,2    ## @PACKET3_INDIRECT_BUFFER
	.no_dead_strip	_gfx_v10_0_ring_emit_ib_compute
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v10_0_ring_emit_ib_compute
_gfx_v10_0_ring_emit_ib_compute:        ; @gfx_v10_0_ring_emit_ib_compute
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x2
	mov	x19, x0
	mov	x0, x1
	bl	_AMDGPU_JOB_GET_VMID
	mov	x21, x0
Lloh0:
	adrp	x8, _INDIRECT_BUFFER_VALID@GOTPAGE
Lloh1:
	ldr	x8, [x8, _INDIRECT_BUFFER_VALID@GOTPAGEOFF]
Lloh2:
	ldr	w22, [x8]
	ldp	w23, w8, [x20]
Lloh3:
	adrp	x9, _AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID@GOTPAGE
Lloh4:
	ldr	x9, [x9, _AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
Lloh6:
	adrp	x8, _PACKET3_SET_CONFIG_REG@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PACKET3_SET_CONFIG_REG@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh9:
	adrp	x8, _mmGDS_COMPUTE_MAX_WAVE_ID@GOTPAGE
Lloh10:
	ldr	x8, [x8, _mmGDS_COMPUTE_MAX_WAVE_ID@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	x8, [x19]
	ldr	w1, [x8]
	mov	x0, x19
	bl	_amdgpu_ring_write
LBB0_2:
	orr	w8, w22, w21, lsl #24
	orr	w21, w8, w23
Lloh12:
	adrp	x8, _PACKET3_INDIRECT_BUFFER@GOTPAGE
Lloh13:
	ldr	x8, [x8, _PACKET3_INDIRECT_BUFFER@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	mov	w1, #2
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w8, [x20, #8]
	and	w0, w8, #0x3
	bl	_BUG_ON
	ldr	w0, [x20, #8]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x20, #8]
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	x1, x21
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_amdgpu_ring_write
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.cfi_endproc
                                        ; -- End function
	.comm	_INDIRECT_BUFFER_VALID,4,2      ; @INDIRECT_BUFFER_VALID
	.comm	_AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID,4,2 ; @AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
	.comm	_PACKET3_SET_CONFIG_REG,4,2     ; @PACKET3_SET_CONFIG_REG
	.comm	_mmGDS_COMPUTE_MAX_WAVE_ID,4,2  ; @mmGDS_COMPUTE_MAX_WAVE_ID
	.comm	_PACKET3_INDIRECT_BUFFER,4,2    ; @PACKET3_INDIRECT_BUFFER
	.no_dead_strip	_gfx_v10_0_ring_emit_ib_compute
.subsections_via_symbols
