	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function intel_pps_init
_intel_pps_init:                        ## @intel_pps_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	callq	_HAS_PCH_SPLIT
	movq	_PCH_PPS_BASE@GOTPCREL(%rip), %r14
	testq	%rax, %rax
	jne	LBB0_7
## %bb.1:
	movq	%rbx, %rdi
	callq	_IS_GEN9_LP
	testq	%rax, %rax
	jne	LBB0_7
## %bb.2:
	movq	%rbx, %rdi
	callq	_IS_VALLEYVIEW
	testq	%rax, %rax
	jne	LBB0_6
## %bb.4:
	movq	%rbx, %rdi
	callq	_IS_CHERRYVIEW
	testq	%rax, %rax
	jne	LBB0_6
## %bb.5:
	movq	_PPS_BASE@GOTPCREL(%rip), %r14
	jmp	LBB0_7
LBB0_6:
	movq	_VLV_PPS_BASE@GOTPCREL(%rip), %r14
LBB0_7:
	movl	(%r14), %eax
	movl	%eax, (%rbx)
	movq	%rbx, %rdi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_intel_pps_unlock_regs_wa       ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PCH_PPS_BASE,4,2               ## @PCH_PPS_BASE
	.comm	_VLV_PPS_BASE,4,2               ## @VLV_PPS_BASE
	.comm	_PPS_BASE,4,2                   ## @PPS_BASE
	.no_dead_strip	_intel_pps_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function intel_pps_init
_intel_pps_init:                        ; @intel_pps_init
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_HAS_PCH_SPLIT
	cbnz	x0, LBB0_2
; %bb.1:
	mov	x0, x19
	bl	_IS_GEN9_LP
	cbz	x0, LBB0_4
LBB0_2:
Lloh0:
	adrp	x20, _PCH_PPS_BASE@GOTPAGE
Lloh1:
	ldr	x20, [x20, _PCH_PPS_BASE@GOTPAGEOFF]
LBB0_3:
	ldr	w8, [x20]
	str	w8, [x19]
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_intel_pps_unlock_regs_wa
LBB0_4:
	mov	x0, x19
	bl	_IS_VALLEYVIEW
Lloh2:
	adrp	x20, _VLV_PPS_BASE@GOTPAGE
Lloh3:
	ldr	x20, [x20, _VLV_PPS_BASE@GOTPAGEOFF]
	cbnz	x0, LBB0_3
; %bb.5:
	mov	x0, x19
	bl	_IS_CHERRYVIEW
Lloh4:
	adrp	x8, _PPS_BASE@GOTPAGE
Lloh5:
	ldr	x8, [x8, _PPS_BASE@GOTPAGEOFF]
	cmp	x0, #0
	csel	x20, x8, x20, eq
	b	LBB0_3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_PCH_PPS_BASE,4,2               ; @PCH_PPS_BASE
	.comm	_VLV_PPS_BASE,4,2               ; @VLV_PPS_BASE
	.comm	_PPS_BASE,4,2                   ; @PPS_BASE
	.no_dead_strip	_intel_pps_init
.subsections_via_symbols
