	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v9_0_sw_fini
_gfx_v9_0_sw_fini:                      ## @gfx_v9_0_sw_fini
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	_AMDGPU_RAS_BLOCK__GFX@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_amdgpu_ras_is_supported
	testq	%rax, %rax
	je	LBB0_3
## %bb.1:
	movq	56(%r15), %r14
	testq	%r14, %r14
	je	LBB0_3
## %bb.2:
	movl	(%r14), %eax
	movl	%eax, -32(%rbp)
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_amdgpu_ras_debugfs_remove
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_amdgpu_ras_sysfs_remove
	leaq	-32(%rbp), %rsi
	movq	%r15, %rdi
	callq	_amdgpu_ras_interrupt_remove_handler
	movq	%r15, %rdi
	movq	%r14, %rsi
	xorl	%edx, %edx
	callq	_amdgpu_ras_feature_enable
	movq	%r14, %rdi
	callq	_kfree
LBB0_3:
	cmpl	$0, 8(%r15)
	jle	LBB0_6
## %bb.4:
	xorl	%r14d, %r14d
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	movq	48(%r15), %rdi
	addq	%r14, %rdi
	callq	_amdgpu_ring_fini
	incq	%rbx
	movslq	8(%r15), %rax
	addq	$4, %r14
	cmpq	%rax, %rbx
	jl	LBB0_5
LBB0_6:
	cmpl	$0, 12(%r15)
	jle	LBB0_9
## %bb.7:
	xorl	%r14d, %r14d
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_8:                                 ## =>This Inner Loop Header: Depth=1
	movq	40(%r15), %rdi
	addq	%r14, %rdi
	callq	_amdgpu_ring_fini
	incq	%rbx
	movslq	12(%r15), %rax
	addq	$4, %r14
	cmpq	%rax, %rbx
	jl	LBB0_8
LBB0_9:
	movq	%r15, %rdi
	callq	_amdgpu_gfx_mqd_sw_fini
	leaq	32(%r15), %rsi
	leaq	36(%r15), %rdi
	callq	_amdgpu_gfx_kiq_free_ring
	movq	%r15, %rdi
	callq	_amdgpu_gfx_kiq_fini
	movq	%r15, %rdi
	callq	_gfx_v9_0_mec_fini
	movq	%r15, %rdi
	callq	_gfx_v9_0_ngg_fini
	leaq	28(%r15), %rdi
	callq	_amdgpu_bo_unref
	movq	(%r15), %rax
	movq	_CHIP_RAVEN@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_11
## %bb.10:
	movq	_CHIP_RENOIR@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_12
LBB0_11:
	leaq	16(%r15), %rdx
	leaq	24(%r15), %rdi
	leaq	20(%r15), %rsi
	callq	_amdgpu_bo_free_kernel
LBB0_12:
	movq	%r15, %rdi
	callq	_gfx_v9_0_free_microcode
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_RAS_BLOCK__GFX,4,2      ## @AMDGPU_RAS_BLOCK__GFX
	.comm	_CHIP_RAVEN,8,3                 ## @CHIP_RAVEN
	.comm	_CHIP_RENOIR,8,3                ## @CHIP_RENOIR
	.no_dead_strip	_gfx_v9_0_sw_fini
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v9_0_sw_fini
_gfx_v9_0_sw_fini:                      ; @gfx_v9_0_sw_fini
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, _AMDGPU_RAS_BLOCK__GFX@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPU_RAS_BLOCK__GFX@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	bl	_amdgpu_ras_is_supported
	cbz	x0, LBB0_3
; %bb.1:
	ldr	x20, [x19, #56]
	cbz	x20, LBB0_3
; %bb.2:
	ldr	w8, [x20]
	str	w8, [sp, #8]
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_ras_debugfs_remove
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_ras_sysfs_remove
	add	x1, sp, #8
	mov	x0, x19
	bl	_amdgpu_ras_interrupt_remove_handler
	mov	x0, x19
	mov	x1, x20
	mov	w2, #0
	bl	_amdgpu_ras_feature_enable
	mov	x0, x20
	bl	_kfree
LBB0_3:
	ldr	w8, [x19, #8]
	cmp	w8, #1
	b.lt	LBB0_6
; %bb.4:
	mov	x20, #0
	mov	x21, #0
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #48]
	add	x0, x8, x20
	bl	_amdgpu_ring_fini
	add	x21, x21, #1
	ldrsw	x8, [x19, #8]
	add	x20, x20, #4
	cmp	x21, x8
	b.lt	LBB0_5
LBB0_6:
	ldr	w8, [x19, #12]
	cmp	w8, #1
	b.lt	LBB0_9
; %bb.7:
	mov	x20, #0
	mov	x21, #0
LBB0_8:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #40]
	add	x0, x8, x20
	bl	_amdgpu_ring_fini
	add	x21, x21, #1
	ldrsw	x8, [x19, #12]
	add	x20, x20, #4
	cmp	x21, x8
	b.lt	LBB0_8
LBB0_9:
	mov	x0, x19
	bl	_amdgpu_gfx_mqd_sw_fini
	add	x1, x19, #32
	add	x0, x19, #36
	bl	_amdgpu_gfx_kiq_free_ring
	mov	x0, x19
	bl	_amdgpu_gfx_kiq_fini
	mov	x0, x19
	bl	_gfx_v9_0_mec_fini
	mov	x0, x19
	bl	_gfx_v9_0_ngg_fini
	add	x0, x19, #28
	bl	_amdgpu_bo_unref
	ldr	x8, [x19]
Lloh3:
	adrp	x9, _CHIP_RAVEN@GOTPAGE
Lloh4:
	ldr	x9, [x9, _CHIP_RAVEN@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
Lloh6:
	adrp	x10, _CHIP_RENOIR@GOTPAGE
Lloh7:
	ldr	x10, [x10, _CHIP_RENOIR@GOTPAGEOFF]
Lloh8:
	ldr	x10, [x10]
	cmp	x8, x9
	ccmp	x8, x10, #4, ne
	b.ne	LBB0_11
; %bb.10:
	add	x2, x19, #16
	add	x0, x19, #24
	add	x1, x19, #20
	bl	_amdgpu_bo_free_kernel
LBB0_11:
	mov	x0, x19
	bl	_gfx_v9_0_free_microcode
	mov	w0, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_RAS_BLOCK__GFX,4,2      ; @AMDGPU_RAS_BLOCK__GFX
	.comm	_CHIP_RAVEN,8,3                 ; @CHIP_RAVEN
	.comm	_CHIP_RENOIR,8,3                ; @CHIP_RENOIR
	.no_dead_strip	_gfx_v9_0_sw_fini
.subsections_via_symbols
