	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function smu7_register_irq_handlers
_smu7_register_irq_handlers:            ## @smu7_register_irq_handlers
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_GFP_KERNEL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$8, %edi
	callq	_kzalloc
	testq	%rax, %rax
	je	LBB0_1
## %bb.2:
	movq	%rax, %rbx
	movq	_smu7_irq_funcs@GOTPCREL(%rip), %rax
	movq	%rax, (%rbx)
	movq	(%r14), %rdi
	movq	_AMDGPU_IRQ_CLIENTID_LEGACY@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rcx
	callq	_amdgpu_irq_add_id
	movq	(%r14), %rdi
	movl	(%r15), %esi
	movq	_VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rcx
	callq	_amdgpu_irq_add_id
	movq	(%r14), %rdi
	movl	(%r15), %esi
	movq	_VISLANDS30_IV_SRCID_GPIO_19@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rcx
	callq	_amdgpu_irq_add_id
	xorl	%eax, %eax
	jmp	LBB0_3
LBB0_1:
	movq	_ENOMEM@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_3:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_GFP_KERNEL,4,2                 ## @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ## @ENOMEM
	.comm	_smu7_irq_funcs,4,2             ## @smu7_irq_funcs
	.comm	_AMDGPU_IRQ_CLIENTID_LEGACY,4,2 ## @AMDGPU_IRQ_CLIENTID_LEGACY
	.comm	_VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH,4,2 ## @VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH
	.comm	_VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW,4,2 ## @VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW
	.comm	_VISLANDS30_IV_SRCID_GPIO_19,4,2 ## @VISLANDS30_IV_SRCID_GPIO_19
	.no_dead_strip	_smu7_register_irq_handlers
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function smu7_register_irq_handlers
_smu7_register_irq_handlers:            ; @smu7_register_irq_handlers
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, _GFP_KERNEL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _GFP_KERNEL@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	w0, #8
	bl	_kzalloc
	cbz	x0, LBB0_2
; %bb.1:
	mov	x20, x0
Lloh3:
	adrp	x8, _smu7_irq_funcs@GOTPAGE
Lloh4:
	ldr	x8, [x8, _smu7_irq_funcs@GOTPAGEOFF]
	str	x8, [x0]
	ldr	x0, [x19]
Lloh5:
	adrp	x21, _AMDGPU_IRQ_CLIENTID_LEGACY@GOTPAGE
Lloh6:
	ldr	x21, [x21, _AMDGPU_IRQ_CLIENTID_LEGACY@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh7:
	adrp	x8, _VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH@GOTPAGE
Lloh8:
	ldr	x8, [x8, _VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH@GOTPAGEOFF]
Lloh9:
	ldr	w2, [x8]
	mov	x3, x20
	bl	_amdgpu_irq_add_id
	ldr	x0, [x19]
	ldr	w1, [x21]
Lloh10:
	adrp	x8, _VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW@GOTPAGE
Lloh11:
	ldr	x8, [x8, _VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW@GOTPAGEOFF]
Lloh12:
	ldr	w2, [x8]
	mov	x3, x20
	bl	_amdgpu_irq_add_id
	ldr	x0, [x19]
	ldr	w1, [x21]
Lloh13:
	adrp	x8, _VISLANDS30_IV_SRCID_GPIO_19@GOTPAGE
Lloh14:
	ldr	x8, [x8, _VISLANDS30_IV_SRCID_GPIO_19@GOTPAGEOFF]
Lloh15:
	ldr	w2, [x8]
	mov	x3, x20
	bl	_amdgpu_irq_add_id
	mov	w0, #0
	b	LBB0_3
LBB0_2:
Lloh16:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh17:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_3:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.cfi_endproc
                                        ; -- End function
	.comm	_GFP_KERNEL,4,2                 ; @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ; @ENOMEM
	.comm	_smu7_irq_funcs,4,2             ; @smu7_irq_funcs
	.comm	_AMDGPU_IRQ_CLIENTID_LEGACY,4,2 ; @AMDGPU_IRQ_CLIENTID_LEGACY
	.comm	_VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH,4,2 ; @VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH
	.comm	_VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW,4,2 ; @VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW
	.comm	_VISLANDS30_IV_SRCID_GPIO_19,4,2 ; @VISLANDS30_IV_SRCID_GPIO_19
	.no_dead_strip	_smu7_register_irq_handlers
.subsections_via_symbols
