	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vlv_initial_power_sequencer_setup
_vlv_initial_power_sequencer_setup:     ## @vlv_initial_power_sequencer_setup
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	callq	_dp_to_i915
	movq	%rax, %r15
	movq	%r12, %rdi
	callq	_dp_to_dig_port
	movl	(%rax), %r14d
	movq	%r15, %rdi
	callq	_lockdep_assert_held
	movq	_vlv_pipe_has_pp_on@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_vlv_initial_pps_pipe
	movq	%rax, %rbx
	movq	%rax, (%r12)
	movq	_INVALID_PIPE@GOTPCREL(%rip), %rax
	movq	(%rax), %r13
	cmpq	%rbx, %r13
	jne	LBB0_2
## %bb.1:
	movq	_vlv_pipe_has_vdd_on@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_vlv_initial_pps_pipe
	movq	%rax, %rbx
	movq	%rax, (%r12)
	movq	_INVALID_PIPE@GOTPCREL(%rip), %rax
	movq	(%rax), %r13
LBB0_2:
	cmpq	%r13, %rbx
	jne	LBB0_4
## %bb.3:
	movq	_vlv_pipe_any@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_vlv_initial_pps_pipe
	movq	%rax, %rbx
	movq	%rax, (%r12)
	movq	_INVALID_PIPE@GOTPCREL(%rip), %rax
	movq	(%rax), %r13
LBB0_4:
	movl	%r14d, %edi
	callq	_port_name
	movl	%eax, %r14d
	cmpq	%r13, %rbx
	jne	LBB0_6
## %bb.5:
	leaq	L_.str(%rip), %rdi
	movl	%r14d, %esi
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_DRM_DEBUG_KMS                  ## TAILCALL
LBB0_6:
	movq	(%r12), %rdi
	callq	_pipe_name
	leaq	L_.str.1(%rip), %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_DRM_DEBUG_KMS
	movq	%r12, %rdi
	callq	_intel_dp_init_panel_power_sequencer
	movq	%r12, %rdi
	xorl	%esi, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_intel_dp_init_panel_power_sequencer_registers ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_vlv_pipe_has_pp_on,4,2         ## @vlv_pipe_has_pp_on
	.comm	_INVALID_PIPE,8,3               ## @INVALID_PIPE
	.comm	_vlv_pipe_has_vdd_on,4,2        ## @vlv_pipe_has_vdd_on
	.comm	_vlv_pipe_any,4,2               ## @vlv_pipe_any
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"no initial power sequencer for port %c\n"

L_.str.1:                               ## @.str.1
	.asciz	"initial power sequencer for port %c: pipe %c\n"

	.no_dead_strip	_vlv_initial_power_sequencer_setup
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vlv_initial_power_sequencer_setup
_vlv_initial_power_sequencer_setup:     ; @vlv_initial_power_sequencer_setup
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	bl	_dp_to_i915
	mov	x21, x0
	mov	x0, x19
	bl	_dp_to_dig_port
	ldr	w20, [x0]
	mov	x0, x21
	bl	_lockdep_assert_held
Lloh0:
	adrp	x8, _vlv_pipe_has_pp_on@GOTPAGE
Lloh1:
	ldr	x8, [x8, _vlv_pipe_has_pp_on@GOTPAGEOFF]
Lloh2:
	ldr	w2, [x8]
	mov	x0, x21
	mov	x1, x20
	bl	_vlv_initial_pps_pipe
	str	x0, [x19]
Lloh3:
	adrp	x23, _INVALID_PIPE@GOTPAGE
Lloh4:
	ldr	x23, [x23, _INVALID_PIPE@GOTPAGEOFF]
	ldr	x24, [x23]
	cmp	x24, x0
	b.ne	LBB0_2
; %bb.1:
Lloh5:
	adrp	x8, _vlv_pipe_has_vdd_on@GOTPAGE
Lloh6:
	ldr	x8, [x8, _vlv_pipe_has_vdd_on@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	x0, x21
	mov	x1, x20
	bl	_vlv_initial_pps_pipe
	mov	x22, x0
	str	x0, [x19]
	ldr	x24, [x23]
	cmp	x22, x24
	b.eq	LBB0_3
	b	LBB0_4
LBB0_2:
	mov	x22, x0
	cmp	x22, x24
	b.ne	LBB0_4
LBB0_3:
Lloh8:
	adrp	x8, _vlv_pipe_any@GOTPAGE
Lloh9:
	ldr	x8, [x8, _vlv_pipe_any@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	x0, x21
	mov	x1, x20
	bl	_vlv_initial_pps_pipe
	mov	x22, x0
	str	x0, [x19]
	ldr	x24, [x23]
LBB0_4:
	mov	x0, x20
	bl	_port_name
	mov	x20, x0
	cmp	x22, x24
	b.ne	LBB0_6
; %bb.5:
Lloh11:
	adrp	x0, l_.str@PAGE
Lloh12:
	add	x0, x0, l_.str@PAGEOFF
	mov	x1, x20
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	b	_DRM_DEBUG_KMS
LBB0_6:
	ldr	x0, [x19]
	bl	_pipe_name
                                        ; kill: def $w0 killed $w0 def $x0
	str	x0, [sp]
Lloh13:
	adrp	x0, l_.str.1@PAGE
Lloh14:
	add	x0, x0, l_.str.1@PAGEOFF
	mov	x1, x20
	bl	_DRM_DEBUG_KMS
	mov	x0, x19
	bl	_intel_dp_init_panel_power_sequencer
	mov	x0, x19
	mov	w1, #0
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	b	_intel_dp_init_panel_power_sequencer_registers
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpAdd	Lloh11, Lloh12
	.loh AdrpAdd	Lloh13, Lloh14
	.cfi_endproc
                                        ; -- End function
	.comm	_vlv_pipe_has_pp_on,4,2         ; @vlv_pipe_has_pp_on
	.comm	_INVALID_PIPE,8,3               ; @INVALID_PIPE
	.comm	_vlv_pipe_has_vdd_on,4,2        ; @vlv_pipe_has_vdd_on
	.comm	_vlv_pipe_any,4,2               ; @vlv_pipe_any
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"no initial power sequencer for port %c\n"

l_.str.1:                               ; @.str.1
	.asciz	"initial power sequencer for port %c: pipe %c\n"

	.no_dead_strip	_vlv_initial_power_sequencer_setup
.subsections_via_symbols
