	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function uvd_v6_0_start
_uvd_v6_0_start:                        ## @uvd_v6_0_start
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	(%rdi), %rax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movq	_mmUVD_POWER_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_UVD_POWER_STATUS__UVD_PG_MODE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	xorl	%r15d, %r15d
	xorl	%esi, %esi
	callq	_WREG32_P
	movq	%rbx, -56(%rbp)                 ## 8-byte Spill
	movq	%rbx, %rdi
	callq	_uvd_v6_0_mc_resume
	movq	_UVD_MASTINT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_VCPU_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_WREG32_FIELD
	movq	_UVD_LMI_CTRL2@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	movq	_STALL_ARB_UMC@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movl	$1, %edx
	callq	_WREG32_FIELD
	movl	$1, %edi
	callq	_mdelay
	movq	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	movq	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	orl	(%rax), %esi
	movq	_UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_UVD_SOFT_RESET__RBC_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_UVD_SOFT_RESET__CSM_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_UVD_SOFT_RESET__CXW_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_mmUVD_SOFT_RESET@GOTPCREL(%rip), %r14
	movq	_UVD_SOFT_RESET__TAP_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	(%r14), %edi
	movq	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	callq	_WREG32
	movl	$5, %edi
	callq	_mdelay
	movq	_SRBM_SOFT_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_SOFT_RESET_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_WREG32_FIELD
	movl	$5, %edi
	callq	_mdelay
	movq	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$64, %esi
	shll	%cl, %esi
	movq	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_mmUVD_LMI_CTRL@GOTPCREL(%rip), %rax
	movq	_UVD_LMI_CTRL__REQ_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movl	(%rax), %edi
	movq	_UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	callq	_WREG32
	movq	_mmUVD_LMI_SWAP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmUVD_MP_SWAP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmUVD_MPC_SET_MUXA0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$67903552, %esi                 ## imm = 0x40C2040
	callq	_WREG32
	movq	_mmUVD_MPC_SET_MUXA1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmUVD_MPC_SET_MUXB0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$67903552, %esi                 ## imm = 0x40C2040
	callq	_WREG32
	movq	_mmUVD_MPC_SET_MUXB1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmUVD_MPC_SET_ALU@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmUVD_MPC_SET_MUX@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$136, %esi
	callq	_WREG32
	movl	(%r14), %edi
	movl	(%r13), %esi
	callq	_WREG32
	movl	$5, %edi
	callq	_mdelay
	movq	_mmUVD_VCPU_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_UVD_VCPU_CNTL__CLK_EN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_WREG32
	movl	(%r12), %edi
	movl	(%rbx), %esi
	xorl	%edx, %edx
	callq	_WREG32_FIELD
	movl	(%r14), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	$10, %edi
	callq	_mdelay
	movq	_mmUVD_STATUS@GOTPCREL(%rip), %rbx
	movq	_UVD_SOFT_RESET@GOTPCREL(%rip), %r13
	movq	_VCPU_SOFT_RESET@GOTPCREL(%rip), %r14
LBB0_1:                                 ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_2 Depth 2
	movl	$100, %r12d
	.p2align	4, 0x90
LBB0_2:                                 ##   Parent Loop BB0_1 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movl	(%rbx), %edi
	callq	_RREG32
	testb	$2, %al
	jne	LBB0_6
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=2
	movl	$10, %edi
	callq	_mdelay
	decl	%r12d
	jne	LBB0_2
## %bb.4:                               ##   in Loop: Header=BB0_1 Depth=1
	leaq	L_.str(%rip), %rdi
	callq	_DRM_ERROR
	movl	(%r13), %edi
	movl	(%r14), %esi
	movl	$1, %edx
	callq	_WREG32_FIELD
	movl	$10, %edi
	callq	_mdelay
	movl	(%r13), %edi
	movl	(%r14), %esi
	xorl	%edx, %edx
	callq	_WREG32_FIELD
	movl	$10, %edi
	callq	_mdelay
	incl	%r15d
	cmpl	$10, %r15d
	jne	LBB0_1
## %bb.5:
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_ERROR
	movl	$-1, %r12d
	jmp	LBB0_8
LBB0_6:
	movq	_mmUVD_MASTINT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_UVD_MASTINT_EN__VCPU_EN_MASK@GOTPCREL(%rip), %rax
	movq	_UVD_MASTINT_EN__SYS_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movl	%esi, %edx
	notl	%edx
	callq	_WREG32_P
	movl	(%rbx), %edi
	movq	_UVD_STATUS__VCPU_REPORT__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %edx
	shll	%cl, %edx
	notl	%edx
	xorl	%r12d, %r12d
	xorl	%esi, %esi
	callq	_WREG32_P
	movq	-48(%rbp), %r15                 ## 8-byte Reload
	movl	8(%r15), %edi
	callq	_order_base_2
	movq	_UVD_RBC_RB_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	_RB_BUFSZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%edi, %edi
	movl	%eax, %ecx
	callq	_REG_SET_FIELD
	movl	(%r13), %esi
	movq	_RB_BLKSZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r13), %esi
	movq	_RB_NO_FETCH@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r13), %esi
	movq	_RB_WPTR_POLL_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%r13), %esi
	movq	_RB_NO_UPDATE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r13), %esi
	movq	_RB_RPTR_WR_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movq	_mmUVD_RBC_RB_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmUVD_RBC_RB_WPTR_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmUVD_RBC_RB_RPTR_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	12(%r15), %edi
	callq	_upper_32_bits
	sarl	$2, %eax
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	12(%r15), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	12(%r15), %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmUVD_RBC_RB_RPTR@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%rbx), %edi
	callq	_RREG32
	movl	%eax, 16(%r15)
	movq	_mmUVD_RBC_RB_WPTR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	movl	%eax, %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movl	(%r13), %edi
	movl	(%r14), %esi
	xorl	%edx, %edx
	callq	_WREG32_FIELD
	movq	-56(%rbp), %r15                 ## 8-byte Reload
	movq	%r15, %rdi
	callq	_uvd_v6_0_enc_support
	testq	%rax, %rax
	je	LBB0_8
## %bb.7:
	movq	(%r15), %rax
	movq	(%rax), %rbx
	movq	_mmUVD_RB_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	8(%rbx), %edi
	callq	_lower_32_bits
	movl	%r14d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmUVD_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	8(%rbx), %edi
	callq	_lower_32_bits
	movl	%r14d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmUVD_RB_BASE_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	4(%rbx), %esi
	callq	_WREG32
	movq	_mmUVD_RB_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	4(%rbx), %edi
	callq	_upper_32_bits
	movl	%r14d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmUVD_RB_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%rbx), %eax
	leal	3(%rax), %esi
	testl	%eax, %eax
	cmovnsl	%eax, %esi
	sarl	$2, %esi
	callq	_WREG32
	movq	(%r15), %rax
	movq	(%rax), %rbx
	movq	_mmUVD_RB_RPTR2@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	20(%rbx), %edi
	callq	_lower_32_bits
	movl	%r14d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmUVD_RB_WPTR2@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	20(%rbx), %edi
	callq	_lower_32_bits
	movl	%r14d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmUVD_RB_BASE_LO2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	16(%rbx), %esi
	callq	_WREG32
	movq	_mmUVD_RB_BASE_HI2@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	16(%rbx), %edi
	callq	_upper_32_bits
	movl	%r14d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmUVD_RB_SIZE2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	12(%rbx), %eax
	leal	3(%rax), %esi
	testl	%eax, %eax
	cmovnsl	%eax, %esi
	sarl	$2, %esi
	callq	_WREG32
LBB0_8:
	movl	%r12d, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_mmUVD_POWER_STATUS,4,2         ## @mmUVD_POWER_STATUS
	.comm	_UVD_POWER_STATUS__UVD_PG_MODE_MASK,4,2 ## @UVD_POWER_STATUS__UVD_PG_MODE_MASK
	.comm	_UVD_MASTINT_EN,4,2             ## @UVD_MASTINT_EN
	.comm	_VCPU_EN,4,2                    ## @VCPU_EN
	.comm	_UVD_LMI_CTRL2,4,2              ## @UVD_LMI_CTRL2
	.comm	_STALL_ARB_UMC,4,2              ## @STALL_ARB_UMC
	.comm	_mmUVD_SOFT_RESET,4,2           ## @mmUVD_SOFT_RESET
	.comm	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__RBC_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__RBC_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__CSM_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__CSM_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__CXW_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__CXW_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__TAP_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__TAP_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
	.comm	_SRBM_SOFT_RESET,4,2            ## @SRBM_SOFT_RESET
	.comm	_SOFT_RESET_UVD,4,2             ## @SOFT_RESET_UVD
	.comm	_mmUVD_LMI_CTRL,4,2             ## @mmUVD_LMI_CTRL
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT,4,2 ## @UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK,4,2 ## @UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK
	.comm	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK,4,2 ## @UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK,4,2 ## @UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__REQ_MODE_MASK,4,2 ## @UVD_LMI_CTRL__REQ_MODE_MASK
	.comm	_UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK,4,2 ## @UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK
	.comm	_mmUVD_LMI_SWAP_CNTL,4,2        ## @mmUVD_LMI_SWAP_CNTL
	.comm	_mmUVD_MP_SWAP_CNTL,4,2         ## @mmUVD_MP_SWAP_CNTL
	.comm	_mmUVD_MPC_SET_MUXA0,4,2        ## @mmUVD_MPC_SET_MUXA0
	.comm	_mmUVD_MPC_SET_MUXA1,4,2        ## @mmUVD_MPC_SET_MUXA1
	.comm	_mmUVD_MPC_SET_MUXB0,4,2        ## @mmUVD_MPC_SET_MUXB0
	.comm	_mmUVD_MPC_SET_MUXB1,4,2        ## @mmUVD_MPC_SET_MUXB1
	.comm	_mmUVD_MPC_SET_ALU,4,2          ## @mmUVD_MPC_SET_ALU
	.comm	_mmUVD_MPC_SET_MUX,4,2          ## @mmUVD_MPC_SET_MUX
	.comm	_mmUVD_VCPU_CNTL,4,2            ## @mmUVD_VCPU_CNTL
	.comm	_UVD_VCPU_CNTL__CLK_EN_MASK,4,2 ## @UVD_VCPU_CNTL__CLK_EN_MASK
	.comm	_mmUVD_STATUS,4,2               ## @mmUVD_STATUS
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"UVD not responding, trying to reset the VCPU!!!\n"

	.comm	_UVD_SOFT_RESET,4,2             ## @UVD_SOFT_RESET
	.comm	_VCPU_SOFT_RESET,4,2            ## @VCPU_SOFT_RESET
L_.str.1:                               ## @.str.1
	.asciz	"UVD not responding, giving up!!!\n"

	.comm	_mmUVD_MASTINT_EN,4,2           ## @mmUVD_MASTINT_EN
	.comm	_UVD_MASTINT_EN__VCPU_EN_MASK,4,2 ## @UVD_MASTINT_EN__VCPU_EN_MASK
	.comm	_UVD_MASTINT_EN__SYS_EN_MASK,4,2 ## @UVD_MASTINT_EN__SYS_EN_MASK
	.comm	_UVD_STATUS__VCPU_REPORT__SHIFT,4,2 ## @UVD_STATUS__VCPU_REPORT__SHIFT
	.comm	_UVD_RBC_RB_CNTL,4,2            ## @UVD_RBC_RB_CNTL
	.comm	_RB_BUFSZ,4,2                   ## @RB_BUFSZ
	.comm	_RB_BLKSZ,4,2                   ## @RB_BLKSZ
	.comm	_RB_NO_FETCH,4,2                ## @RB_NO_FETCH
	.comm	_RB_WPTR_POLL_EN,4,2            ## @RB_WPTR_POLL_EN
	.comm	_RB_NO_UPDATE,4,2               ## @RB_NO_UPDATE
	.comm	_RB_RPTR_WR_EN,4,2              ## @RB_RPTR_WR_EN
	.comm	_mmUVD_RBC_RB_CNTL,4,2          ## @mmUVD_RBC_RB_CNTL
	.comm	_mmUVD_RBC_RB_WPTR_CNTL,4,2     ## @mmUVD_RBC_RB_WPTR_CNTL
	.comm	_mmUVD_RBC_RB_RPTR_ADDR,4,2     ## @mmUVD_RBC_RB_RPTR_ADDR
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
	.comm	_mmUVD_RBC_RB_RPTR,4,2          ## @mmUVD_RBC_RB_RPTR
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ## @mmUVD_RBC_RB_WPTR
	.comm	_mmUVD_RB_RPTR,4,2              ## @mmUVD_RB_RPTR
	.comm	_mmUVD_RB_WPTR,4,2              ## @mmUVD_RB_WPTR
	.comm	_mmUVD_RB_BASE_LO,4,2           ## @mmUVD_RB_BASE_LO
	.comm	_mmUVD_RB_BASE_HI,4,2           ## @mmUVD_RB_BASE_HI
	.comm	_mmUVD_RB_SIZE,4,2              ## @mmUVD_RB_SIZE
	.comm	_mmUVD_RB_RPTR2,4,2             ## @mmUVD_RB_RPTR2
	.comm	_mmUVD_RB_WPTR2,4,2             ## @mmUVD_RB_WPTR2
	.comm	_mmUVD_RB_BASE_LO2,4,2          ## @mmUVD_RB_BASE_LO2
	.comm	_mmUVD_RB_BASE_HI2,4,2          ## @mmUVD_RB_BASE_HI2
	.comm	_mmUVD_RB_SIZE2,4,2             ## @mmUVD_RB_SIZE2
	.no_dead_strip	_uvd_v6_0_start
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function uvd_v6_0_start
_uvd_v6_0_start:                        ; @uvd_v6_0_start
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
Lloh0:
	adrp	x8, _mmUVD_POWER_STATUS@GOTPAGE
Lloh1:
	ldr	x8, [x8, _mmUVD_POWER_STATUS@GOTPAGEOFF]
	ldr	x21, [x0]
Lloh2:
	ldr	w0, [x8]
Lloh3:
	adrp	x8, _UVD_POWER_STATUS__UVD_PG_MODE_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _UVD_POWER_STATUS__UVD_PG_MODE_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	mov	x0, x19
	bl	_uvd_v6_0_mc_resume
Lloh6:
	adrp	x8, _UVD_MASTINT_EN@GOTPAGE
Lloh7:
	ldr	x8, [x8, _UVD_MASTINT_EN@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
Lloh9:
	adrp	x8, _VCPU_EN@GOTPAGE
Lloh10:
	ldr	x8, [x8, _VCPU_EN@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_WREG32_FIELD
Lloh12:
	adrp	x20, _UVD_LMI_CTRL2@GOTPAGE
Lloh13:
	ldr	x20, [x20, _UVD_LMI_CTRL2@GOTPAGEOFF]
	ldr	w0, [x20]
Lloh14:
	adrp	x22, _STALL_ARB_UMC@GOTPAGE
Lloh15:
	ldr	x22, [x22, _STALL_ARB_UMC@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	w2, #1
	bl	_WREG32_FIELD
	mov	w0, #1
	bl	_mdelay
Lloh16:
	adrp	x23, _mmUVD_SOFT_RESET@GOTPAGE
Lloh17:
	ldr	x23, [x23, _mmUVD_SOFT_RESET@GOTPAGEOFF]
Lloh18:
	adrp	x8, _UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPAGE
Lloh19:
	ldr	x8, [x8, _UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPAGEOFF]
	ldr	w0, [x23]
Lloh20:
	ldr	w8, [x8]
Lloh21:
	adrp	x24, _UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPAGE
Lloh22:
	ldr	x24, [x24, _UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPAGEOFF]
	ldr	w9, [x24]
	orr	w8, w9, w8
Lloh23:
	adrp	x9, _UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK@GOTPAGE
Lloh24:
	ldr	x9, [x9, _UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh26:
	adrp	x9, _UVD_SOFT_RESET__RBC_SOFT_RESET_MASK@GOTPAGE
Lloh27:
	ldr	x9, [x9, _UVD_SOFT_RESET__RBC_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh28:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh29:
	adrp	x9, _UVD_SOFT_RESET__CSM_SOFT_RESET_MASK@GOTPAGE
Lloh30:
	ldr	x9, [x9, _UVD_SOFT_RESET__CSM_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh31:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh32:
	adrp	x9, _UVD_SOFT_RESET__CXW_SOFT_RESET_MASK@GOTPAGE
Lloh33:
	ldr	x9, [x9, _UVD_SOFT_RESET__CXW_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh35:
	adrp	x9, _UVD_SOFT_RESET__TAP_SOFT_RESET_MASK@GOTPAGE
Lloh36:
	ldr	x9, [x9, _UVD_SOFT_RESET__TAP_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh37:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh38:
	adrp	x9, _UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPAGE
Lloh39:
	ldr	x9, [x9, _UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
	orr	w1, w8, w9
	bl	_WREG32
	mov	w0, #5
	bl	_mdelay
Lloh41:
	adrp	x8, _SRBM_SOFT_RESET@GOTPAGE
Lloh42:
	ldr	x8, [x8, _SRBM_SOFT_RESET@GOTPAGEOFF]
Lloh43:
	ldr	w0, [x8]
Lloh44:
	adrp	x8, _SOFT_RESET_UVD@GOTPAGE
Lloh45:
	ldr	x8, [x8, _SOFT_RESET_UVD@GOTPAGEOFF]
Lloh46:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_WREG32_FIELD
	mov	w0, #5
	bl	_mdelay
Lloh47:
	adrp	x8, _mmUVD_LMI_CTRL@GOTPAGE
Lloh48:
	ldr	x8, [x8, _mmUVD_LMI_CTRL@GOTPAGEOFF]
Lloh49:
	adrp	x9, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT@GOTPAGE
Lloh50:
	ldr	x9, [x9, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT@GOTPAGEOFF]
Lloh51:
	ldr	w0, [x8]
Lloh52:
	ldr	w8, [x9]
	mov	w9, #64
	lsl	w8, w9, w8
Lloh53:
	adrp	x9, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPAGE
Lloh54:
	ldr	x9, [x9, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPAGEOFF]
Lloh55:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh56:
	adrp	x9, _UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPAGE
Lloh57:
	ldr	x9, [x9, _UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPAGEOFF]
Lloh58:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh59:
	adrp	x9, _UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPAGE
Lloh60:
	ldr	x9, [x9, _UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPAGEOFF]
Lloh61:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh62:
	adrp	x9, _UVD_LMI_CTRL__REQ_MODE_MASK@GOTPAGE
Lloh63:
	ldr	x9, [x9, _UVD_LMI_CTRL__REQ_MODE_MASK@GOTPAGEOFF]
Lloh64:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh65:
	adrp	x9, _UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK@GOTPAGE
Lloh66:
	ldr	x9, [x9, _UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK@GOTPAGEOFF]
Lloh67:
	ldr	w9, [x9]
	orr	w1, w8, w9
	bl	_WREG32
Lloh68:
	adrp	x8, _mmUVD_LMI_SWAP_CNTL@GOTPAGE
Lloh69:
	ldr	x8, [x8, _mmUVD_LMI_SWAP_CNTL@GOTPAGEOFF]
Lloh70:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh71:
	adrp	x8, _mmUVD_MP_SWAP_CNTL@GOTPAGE
Lloh72:
	ldr	x8, [x8, _mmUVD_MP_SWAP_CNTL@GOTPAGEOFF]
Lloh73:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh74:
	adrp	x8, _mmUVD_MPC_SET_MUXA0@GOTPAGE
Lloh75:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXA0@GOTPAGEOFF]
Lloh76:
	ldr	w0, [x8]
	mov	w1, #8256
	movk	w1, #1036, lsl #16
	bl	_WREG32
Lloh77:
	adrp	x8, _mmUVD_MPC_SET_MUXA1@GOTPAGE
Lloh78:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXA1@GOTPAGEOFF]
Lloh79:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh80:
	adrp	x8, _mmUVD_MPC_SET_MUXB0@GOTPAGE
Lloh81:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXB0@GOTPAGEOFF]
Lloh82:
	ldr	w0, [x8]
	mov	w1, #8256
	movk	w1, #1036, lsl #16
	bl	_WREG32
Lloh83:
	adrp	x8, _mmUVD_MPC_SET_MUXB1@GOTPAGE
Lloh84:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXB1@GOTPAGEOFF]
Lloh85:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh86:
	adrp	x8, _mmUVD_MPC_SET_ALU@GOTPAGE
Lloh87:
	ldr	x8, [x8, _mmUVD_MPC_SET_ALU@GOTPAGEOFF]
Lloh88:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh89:
	adrp	x8, _mmUVD_MPC_SET_MUX@GOTPAGE
Lloh90:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUX@GOTPAGEOFF]
Lloh91:
	ldr	w0, [x8]
	mov	w1, #136
	bl	_WREG32
	ldr	w0, [x23]
	ldr	w1, [x24]
	bl	_WREG32
	mov	w0, #5
	bl	_mdelay
Lloh92:
	adrp	x8, _mmUVD_VCPU_CNTL@GOTPAGE
Lloh93:
	ldr	x8, [x8, _mmUVD_VCPU_CNTL@GOTPAGEOFF]
Lloh94:
	ldr	w0, [x8]
Lloh95:
	adrp	x8, _UVD_VCPU_CNTL__CLK_EN_MASK@GOTPAGE
Lloh96:
	ldr	x8, [x8, _UVD_VCPU_CNTL__CLK_EN_MASK@GOTPAGEOFF]
Lloh97:
	ldr	w1, [x8]
	bl	_WREG32
	ldr	w0, [x20]
	ldr	w1, [x22]
	mov	w2, #0
	bl	_WREG32_FIELD
	ldr	w0, [x23]
	mov	w1, #0
	bl	_WREG32
	mov	w0, #10
	bl	_mdelay
	mov	w23, #0
Lloh98:
	adrp	x22, _mmUVD_STATUS@GOTPAGE
Lloh99:
	ldr	x22, [x22, _mmUVD_STATUS@GOTPAGEOFF]
Lloh100:
	adrp	x24, _UVD_SOFT_RESET@GOTPAGE
Lloh101:
	ldr	x24, [x24, _UVD_SOFT_RESET@GOTPAGEOFF]
Lloh102:
	adrp	x20, l_.str@PAGE
Lloh103:
	add	x20, x20, l_.str@PAGEOFF
Lloh104:
	adrp	x25, _VCPU_SOFT_RESET@GOTPAGE
Lloh105:
	ldr	x25, [x25, _VCPU_SOFT_RESET@GOTPAGEOFF]
LBB0_1:                                 ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
	mov	w26, #100
LBB0_2:                                 ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ldr	w0, [x22]
	bl	_RREG32
	tbnz	w0, #1, LBB0_6
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=2
	mov	w0, #10
	bl	_mdelay
	subs	w26, w26, #1
	b.ne	LBB0_2
; %bb.4:                                ;   in Loop: Header=BB0_1 Depth=1
	mov	x0, x20
	bl	_DRM_ERROR
	ldr	w0, [x24]
	ldr	w1, [x25]
	mov	w2, #1
	bl	_WREG32_FIELD
	mov	w0, #10
	bl	_mdelay
	ldr	w0, [x24]
	ldr	w1, [x25]
	mov	w2, #0
	bl	_WREG32_FIELD
	mov	w0, #10
	bl	_mdelay
	add	w23, w23, #1
	cmp	w23, #10
	b.ne	LBB0_1
; %bb.5:
Lloh106:
	adrp	x0, l_.str.1@PAGE
Lloh107:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_ERROR
	mov	w0, #-1
	b	LBB0_8
LBB0_6:
Lloh108:
	adrp	x8, _mmUVD_MASTINT_EN@GOTPAGE
Lloh109:
	ldr	x8, [x8, _mmUVD_MASTINT_EN@GOTPAGEOFF]
Lloh110:
	ldr	w0, [x8]
Lloh111:
	adrp	x8, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGE
Lloh112:
	ldr	x8, [x8, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGEOFF]
Lloh113:
	ldr	w8, [x8]
Lloh114:
	adrp	x9, _UVD_MASTINT_EN__SYS_EN_MASK@GOTPAGE
Lloh115:
	ldr	x9, [x9, _UVD_MASTINT_EN__SYS_EN_MASK@GOTPAGEOFF]
Lloh116:
	ldr	w9, [x9]
	orr	w1, w9, w8
	mvn	w2, w1
	bl	_WREG32_P
	ldr	w0, [x22]
Lloh117:
	adrp	x8, _UVD_STATUS__VCPU_REPORT__SHIFT@GOTPAGE
Lloh118:
	ldr	x8, [x8, _UVD_STATUS__VCPU_REPORT__SHIFT@GOTPAGEOFF]
Lloh119:
	ldr	w8, [x8]
	mov	w9, #2
	lsl	w8, w9, w8
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w0, [x21, #8]
	bl	_order_base_2
	mov	x3, x0
Lloh120:
	adrp	x22, _UVD_RBC_RB_CNTL@GOTPAGE
Lloh121:
	ldr	x22, [x22, _UVD_RBC_RB_CNTL@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh122:
	adrp	x8, _RB_BUFSZ@GOTPAGE
Lloh123:
	ldr	x8, [x8, _RB_BUFSZ@GOTPAGEOFF]
Lloh124:
	ldr	w2, [x8]
	mov	w0, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x22]
Lloh125:
	adrp	x8, _RB_BLKSZ@GOTPAGE
Lloh126:
	ldr	x8, [x8, _RB_BLKSZ@GOTPAGEOFF]
Lloh127:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x22]
Lloh128:
	adrp	x23, _RB_NO_FETCH@GOTPAGE
Lloh129:
	ldr	x23, [x23, _RB_NO_FETCH@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x22]
Lloh130:
	adrp	x8, _RB_WPTR_POLL_EN@GOTPAGE
Lloh131:
	ldr	x8, [x8, _RB_WPTR_POLL_EN@GOTPAGEOFF]
Lloh132:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x22]
Lloh133:
	adrp	x8, _RB_NO_UPDATE@GOTPAGE
Lloh134:
	ldr	x8, [x8, _RB_NO_UPDATE@GOTPAGEOFF]
Lloh135:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x22]
Lloh136:
	adrp	x8, _RB_RPTR_WR_EN@GOTPAGE
Lloh137:
	ldr	x8, [x8, _RB_RPTR_WR_EN@GOTPAGEOFF]
Lloh138:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x1, x0
Lloh139:
	adrp	x8, _mmUVD_RBC_RB_CNTL@GOTPAGE
Lloh140:
	ldr	x8, [x8, _mmUVD_RBC_RB_CNTL@GOTPAGEOFF]
Lloh141:
	ldr	w0, [x8]
	bl	_WREG32
Lloh142:
	adrp	x8, _mmUVD_RBC_RB_WPTR_CNTL@GOTPAGE
Lloh143:
	ldr	x8, [x8, _mmUVD_RBC_RB_WPTR_CNTL@GOTPAGEOFF]
Lloh144:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh145:
	adrp	x8, _mmUVD_RBC_RB_RPTR_ADDR@GOTPAGE
Lloh146:
	ldr	x8, [x8, _mmUVD_RBC_RB_RPTR_ADDR@GOTPAGEOFF]
Lloh147:
	ldr	w20, [x8]
	ldr	w0, [x21, #12]
	bl	_upper_32_bits
	asr	w1, w0, #2
	mov	x0, x20
	bl	_WREG32
Lloh148:
	adrp	x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPAGE
Lloh149:
	ldr	x8, [x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh150:
	ldr	w20, [x8]
	ldr	w0, [x21, #12]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
Lloh151:
	adrp	x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPAGE
Lloh152:
	ldr	x8, [x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh153:
	ldr	w20, [x8]
	ldr	w0, [x21, #12]
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
Lloh154:
	adrp	x20, _mmUVD_RBC_RB_RPTR@GOTPAGE
Lloh155:
	ldr	x20, [x20, _mmUVD_RBC_RB_RPTR@GOTPAGEOFF]
	ldr	w0, [x20]
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x20]
	bl	_RREG32
	str	w0, [x21, #16]
Lloh156:
	adrp	x8, _mmUVD_RBC_RB_WPTR@GOTPAGE
Lloh157:
	ldr	x8, [x8, _mmUVD_RBC_RB_WPTR@GOTPAGEOFF]
Lloh158:
	ldr	w20, [x8]
                                        ; kill: def $w0 killed $w0 killed $x0
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
	ldr	w0, [x22]
	ldr	w1, [x23]
	mov	w2, #0
	bl	_WREG32_FIELD
	mov	x0, x19
	bl	_uvd_v6_0_enc_support
	cbz	x0, LBB0_8
; %bb.7:
	ldr	x8, [x19]
	ldr	x21, [x8]
Lloh159:
	adrp	x8, _mmUVD_RB_RPTR@GOTPAGE
Lloh160:
	ldr	x8, [x8, _mmUVD_RB_RPTR@GOTPAGEOFF]
Lloh161:
	ldr	w20, [x8]
	ldr	w0, [x21, #8]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
Lloh162:
	adrp	x8, _mmUVD_RB_WPTR@GOTPAGE
Lloh163:
	ldr	x8, [x8, _mmUVD_RB_WPTR@GOTPAGEOFF]
Lloh164:
	ldr	w20, [x8]
	ldr	w0, [x21, #8]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
Lloh165:
	adrp	x8, _mmUVD_RB_BASE_LO@GOTPAGE
Lloh166:
	ldr	x8, [x8, _mmUVD_RB_BASE_LO@GOTPAGEOFF]
Lloh167:
	ldr	w0, [x8]
	ldr	w1, [x21, #4]
	bl	_WREG32
Lloh168:
	adrp	x8, _mmUVD_RB_BASE_HI@GOTPAGE
Lloh169:
	ldr	x8, [x8, _mmUVD_RB_BASE_HI@GOTPAGEOFF]
Lloh170:
	ldr	w20, [x8]
	ldr	w0, [x21, #4]
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
Lloh171:
	adrp	x8, _mmUVD_RB_SIZE@GOTPAGE
Lloh172:
	ldr	x8, [x8, _mmUVD_RB_SIZE@GOTPAGEOFF]
Lloh173:
	ldr	w0, [x8]
	ldr	w8, [x21]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w1, w8, #2
	bl	_WREG32
	ldr	x8, [x19]
	ldr	x20, [x8]
Lloh174:
	adrp	x8, _mmUVD_RB_RPTR2@GOTPAGE
Lloh175:
	ldr	x8, [x8, _mmUVD_RB_RPTR2@GOTPAGEOFF]
Lloh176:
	ldr	w19, [x8]
	ldr	w0, [x20, #20]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_WREG32
Lloh177:
	adrp	x8, _mmUVD_RB_WPTR2@GOTPAGE
Lloh178:
	ldr	x8, [x8, _mmUVD_RB_WPTR2@GOTPAGEOFF]
Lloh179:
	ldr	w19, [x8]
	ldr	w0, [x20, #20]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_WREG32
Lloh180:
	adrp	x8, _mmUVD_RB_BASE_LO2@GOTPAGE
Lloh181:
	ldr	x8, [x8, _mmUVD_RB_BASE_LO2@GOTPAGEOFF]
Lloh182:
	ldr	w0, [x8]
	ldr	w1, [x20, #16]
	bl	_WREG32
Lloh183:
	adrp	x8, _mmUVD_RB_BASE_HI2@GOTPAGE
Lloh184:
	ldr	x8, [x8, _mmUVD_RB_BASE_HI2@GOTPAGEOFF]
Lloh185:
	ldr	w19, [x8]
	ldr	w0, [x20, #16]
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_WREG32
Lloh186:
	adrp	x8, _mmUVD_RB_SIZE2@GOTPAGE
Lloh187:
	ldr	x8, [x8, _mmUVD_RB_SIZE2@GOTPAGEOFF]
Lloh188:
	ldr	w0, [x8]
	ldr	w8, [x20, #12]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w1, w8, #2
	bl	_WREG32
	mov	w0, #0
LBB0_8:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh104, Lloh105
	.loh AdrpAdd	Lloh102, Lloh103
	.loh AdrpLdrGot	Lloh100, Lloh101
	.loh AdrpLdrGot	Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh51
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh156, Lloh157, Lloh158
	.loh AdrpLdrGot	Lloh154, Lloh155
	.loh AdrpLdrGotLdr	Lloh151, Lloh152, Lloh153
	.loh AdrpLdrGotLdr	Lloh148, Lloh149, Lloh150
	.loh AdrpLdrGotLdr	Lloh145, Lloh146, Lloh147
	.loh AdrpLdrGotLdr	Lloh142, Lloh143, Lloh144
	.loh AdrpLdrGotLdr	Lloh139, Lloh140, Lloh141
	.loh AdrpLdrGotLdr	Lloh136, Lloh137, Lloh138
	.loh AdrpLdrGotLdr	Lloh133, Lloh134, Lloh135
	.loh AdrpLdrGotLdr	Lloh130, Lloh131, Lloh132
	.loh AdrpLdrGot	Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGot	Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh186, Lloh187, Lloh188
	.loh AdrpLdrGotLdr	Lloh183, Lloh184, Lloh185
	.loh AdrpLdrGotLdr	Lloh180, Lloh181, Lloh182
	.loh AdrpLdrGotLdr	Lloh177, Lloh178, Lloh179
	.loh AdrpLdrGotLdr	Lloh174, Lloh175, Lloh176
	.loh AdrpLdrGotLdr	Lloh171, Lloh172, Lloh173
	.loh AdrpLdrGotLdr	Lloh168, Lloh169, Lloh170
	.loh AdrpLdrGotLdr	Lloh165, Lloh166, Lloh167
	.loh AdrpLdrGotLdr	Lloh162, Lloh163, Lloh164
	.loh AdrpLdrGotLdr	Lloh159, Lloh160, Lloh161
	.cfi_endproc
                                        ; -- End function
	.comm	_mmUVD_POWER_STATUS,4,2         ; @mmUVD_POWER_STATUS
	.comm	_UVD_POWER_STATUS__UVD_PG_MODE_MASK,4,2 ; @UVD_POWER_STATUS__UVD_PG_MODE_MASK
	.comm	_UVD_MASTINT_EN,4,2             ; @UVD_MASTINT_EN
	.comm	_VCPU_EN,4,2                    ; @VCPU_EN
	.comm	_UVD_LMI_CTRL2,4,2              ; @UVD_LMI_CTRL2
	.comm	_STALL_ARB_UMC,4,2              ; @STALL_ARB_UMC
	.comm	_mmUVD_SOFT_RESET,4,2           ; @mmUVD_SOFT_RESET
	.comm	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__RBC_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__RBC_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__CSM_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__CSM_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__CXW_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__CXW_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__TAP_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__TAP_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
	.comm	_SRBM_SOFT_RESET,4,2            ; @SRBM_SOFT_RESET
	.comm	_SOFT_RESET_UVD,4,2             ; @SOFT_RESET_UVD
	.comm	_mmUVD_LMI_CTRL,4,2             ; @mmUVD_LMI_CTRL
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT,4,2 ; @UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK,4,2 ; @UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK
	.comm	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK,4,2 ; @UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK,4,2 ; @UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__REQ_MODE_MASK,4,2 ; @UVD_LMI_CTRL__REQ_MODE_MASK
	.comm	_UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK,4,2 ; @UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK
	.comm	_mmUVD_LMI_SWAP_CNTL,4,2        ; @mmUVD_LMI_SWAP_CNTL
	.comm	_mmUVD_MP_SWAP_CNTL,4,2         ; @mmUVD_MP_SWAP_CNTL
	.comm	_mmUVD_MPC_SET_MUXA0,4,2        ; @mmUVD_MPC_SET_MUXA0
	.comm	_mmUVD_MPC_SET_MUXA1,4,2        ; @mmUVD_MPC_SET_MUXA1
	.comm	_mmUVD_MPC_SET_MUXB0,4,2        ; @mmUVD_MPC_SET_MUXB0
	.comm	_mmUVD_MPC_SET_MUXB1,4,2        ; @mmUVD_MPC_SET_MUXB1
	.comm	_mmUVD_MPC_SET_ALU,4,2          ; @mmUVD_MPC_SET_ALU
	.comm	_mmUVD_MPC_SET_MUX,4,2          ; @mmUVD_MPC_SET_MUX
	.comm	_mmUVD_VCPU_CNTL,4,2            ; @mmUVD_VCPU_CNTL
	.comm	_UVD_VCPU_CNTL__CLK_EN_MASK,4,2 ; @UVD_VCPU_CNTL__CLK_EN_MASK
	.comm	_mmUVD_STATUS,4,2               ; @mmUVD_STATUS
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"UVD not responding, trying to reset the VCPU!!!\n"

	.comm	_UVD_SOFT_RESET,4,2             ; @UVD_SOFT_RESET
	.comm	_VCPU_SOFT_RESET,4,2            ; @VCPU_SOFT_RESET
l_.str.1:                               ; @.str.1
	.asciz	"UVD not responding, giving up!!!\n"

	.comm	_mmUVD_MASTINT_EN,4,2           ; @mmUVD_MASTINT_EN
	.comm	_UVD_MASTINT_EN__VCPU_EN_MASK,4,2 ; @UVD_MASTINT_EN__VCPU_EN_MASK
	.comm	_UVD_MASTINT_EN__SYS_EN_MASK,4,2 ; @UVD_MASTINT_EN__SYS_EN_MASK
	.comm	_UVD_STATUS__VCPU_REPORT__SHIFT,4,2 ; @UVD_STATUS__VCPU_REPORT__SHIFT
	.comm	_UVD_RBC_RB_CNTL,4,2            ; @UVD_RBC_RB_CNTL
	.comm	_RB_BUFSZ,4,2                   ; @RB_BUFSZ
	.comm	_RB_BLKSZ,4,2                   ; @RB_BLKSZ
	.comm	_RB_NO_FETCH,4,2                ; @RB_NO_FETCH
	.comm	_RB_WPTR_POLL_EN,4,2            ; @RB_WPTR_POLL_EN
	.comm	_RB_NO_UPDATE,4,2               ; @RB_NO_UPDATE
	.comm	_RB_RPTR_WR_EN,4,2              ; @RB_RPTR_WR_EN
	.comm	_mmUVD_RBC_RB_CNTL,4,2          ; @mmUVD_RBC_RB_CNTL
	.comm	_mmUVD_RBC_RB_WPTR_CNTL,4,2     ; @mmUVD_RBC_RB_WPTR_CNTL
	.comm	_mmUVD_RBC_RB_RPTR_ADDR,4,2     ; @mmUVD_RBC_RB_RPTR_ADDR
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
	.comm	_mmUVD_RBC_RB_RPTR,4,2          ; @mmUVD_RBC_RB_RPTR
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ; @mmUVD_RBC_RB_WPTR
	.comm	_mmUVD_RB_RPTR,4,2              ; @mmUVD_RB_RPTR
	.comm	_mmUVD_RB_WPTR,4,2              ; @mmUVD_RB_WPTR
	.comm	_mmUVD_RB_BASE_LO,4,2           ; @mmUVD_RB_BASE_LO
	.comm	_mmUVD_RB_BASE_HI,4,2           ; @mmUVD_RB_BASE_HI
	.comm	_mmUVD_RB_SIZE,4,2              ; @mmUVD_RB_SIZE
	.comm	_mmUVD_RB_RPTR2,4,2             ; @mmUVD_RB_RPTR2
	.comm	_mmUVD_RB_WPTR2,4,2             ; @mmUVD_RB_WPTR2
	.comm	_mmUVD_RB_BASE_LO2,4,2          ; @mmUVD_RB_BASE_LO2
	.comm	_mmUVD_RB_BASE_HI2,4,2          ; @mmUVD_RB_BASE_HI2
	.comm	_mmUVD_RB_SIZE2,4,2             ; @mmUVD_RB_SIZE2
	.no_dead_strip	_uvd_v6_0_start
.subsections_via_symbols
