	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v2_0_hw_fini
_vcn_v2_0_hw_fini:                      ## @vcn_v2_0_hw_fini
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	movq	24(%rdi), %r14
	movq	_AMD_PG_SUPPORT_VCN_DPG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rdi)
	je	LBB0_1
LBB0_3:
	movq	_AMD_PG_STATE_GATE@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	callq	_vcn_v2_0_set_powergating_state
	jmp	LBB0_4
LBB0_1:
	movq	8(%rbx), %rax
	movq	_AMD_PG_STATE_GATE@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_4
## %bb.2:
	movq	_VCN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmUVD_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	testq	%rax, %rax
	jne	LBB0_3
LBB0_4:
	movl	$0, 16(%r14)
	movl	16(%rbx), %esi
	movq	24(%rbx), %rbx
	testl	%esi, %esi
	jle	LBB0_6
## %bb.5:
	movq	8(%rbx), %rdi
	shlq	$2, %rsi
	callq	___bzero
LBB0_6:
	movl	$0, (%rbx)
	xorl	%eax, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_PG_SUPPORT_VCN_DPG,4,2     ## @AMD_PG_SUPPORT_VCN_DPG
	.comm	_AMD_PG_STATE_GATE,8,3          ## @AMD_PG_STATE_GATE
	.comm	_VCN,4,2                        ## @VCN
	.comm	_mmUVD_STATUS,4,2               ## @mmUVD_STATUS
	.no_dead_strip	_vcn_v2_0_hw_fini
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v2_0_hw_fini
_vcn_v2_0_hw_fini:                      ; @vcn_v2_0_hw_fini
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x20, [x0, #24]
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _AMD_PG_SUPPORT_VCN_DPG@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_PG_SUPPORT_VCN_DPG@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
Lloh3:
	adrp	x21, _AMD_PG_STATE_GATE@GOTPAGE
Lloh4:
	ldr	x21, [x21, _AMD_PG_STATE_GATE@GOTPAGEOFF]
	tst	w9, w8
	b.eq	LBB0_2
LBB0_1:
	ldr	x1, [x21]
	mov	x0, x19
	bl	_vcn_v2_0_set_powergating_state
	b	LBB0_4
LBB0_2:
	ldr	x8, [x19, #8]
	ldr	x9, [x21]
	cmp	x8, x9
	b.eq	LBB0_4
; %bb.3:
Lloh5:
	adrp	x8, _VCN@GOTPAGE
Lloh6:
	ldr	x8, [x8, _VCN@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
Lloh8:
	adrp	x8, _mmUVD_STATUS@GOTPAGE
Lloh9:
	ldr	x8, [x8, _mmUVD_STATUS@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_RREG32_SOC15
	cbnz	x0, LBB0_1
LBB0_4:
	str	wzr, [x20, #16]
	ldr	w8, [x19, #16]
	ldr	x19, [x19, #24]
	cmp	w8, #1
	b.lt	LBB0_6
; %bb.5:
	ldr	x0, [x19, #8]
	lsl	x1, x8, #2
	bl	_bzero
LBB0_6:
	str	wzr, [x19]
	mov	w0, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_PG_SUPPORT_VCN_DPG,4,2     ; @AMD_PG_SUPPORT_VCN_DPG
	.comm	_AMD_PG_STATE_GATE,8,3          ; @AMD_PG_STATE_GATE
	.comm	_VCN,4,2                        ; @VCN
	.comm	_mmUVD_STATUS,4,2               ; @mmUVD_STATUS
	.no_dead_strip	_vcn_v2_0_hw_fini
.subsections_via_symbols
