	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4                               ## -- Begin function init_bxt_mmio_info
LCPI0_0:
	.space	16
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	4, 0x90
_init_bxt_mmio_info:                    ## @init_bxt_mmio_info
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	$524288, %edi                   ## imm = 0x80000
	callq	__MMIO
	movq	_D_BXT@GOTPCREL(%rip), %r15
	movl	(%r15), %r9d
	xorps	%xmm0, %xmm0
	movups	%xmm0, (%rsp)
	movl	%eax, %edi
	movl	$12288, %esi                    ## imm = 0x3000
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	xorl	%r8d, %r8d
	callq	_MMIO_F
	movq	_GEN7_SAMPLER_INSTDONE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_D
	movq	_GEN7_ROW_INSTDONE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_D
	movq	_GEN8_FAULT_TLB_DATA0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_D
	movq	_GEN8_FAULT_TLB_DATA1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_D
	movq	_ERROR_GEN6@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_D
	movq	_DONE_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_D
	movq	_EIR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_D
	movq	_PGTBL_ER@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_D
	movl	$16788, %edi                    ## imm = 0x4194
	callq	__MMIO
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	$17044, %edi                    ## imm = 0x4294
	callq	__MMIO
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	$17556, %edi                    ## imm = 0x4494
	callq	__MMIO
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movq	_RING_PSMI_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_RING_D
	movq	_RING_DMA_FADD@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_RING_D
	movq	_RING_DMA_FADD_UDW@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_RING_D
	movq	_RING_IPEHR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_RING_D
	movq	_RING_INSTPS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_RING_D
	movq	_RING_BBADDR_UDW@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_RING_D
	movq	_RING_BBSTATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_RING_D
	movq	_RING_IPEIR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_RING_D
	xorl	%edi, %edi
	callq	_SOFT_SCRATCH
	movl	(%r15), %r9d
	xorps	%xmm0, %xmm0
	movups	%xmm0, (%rsp)
	movl	%eax, %edi
	movl	$64, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	xorl	%r8d, %r8d
	callq	_MMIO_F
	movq	_BXT_P_CR_GT_DISP_PWRON@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	movq	_bxt_gt_disp_pwron_write@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	xorl	%edx, %edx
	callq	_MMIO_DH
	movq	_BXT_RP_STATE_CAP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_D
	movq	_DPIO_PHY0@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_BXT_PHY_CTL_FAMILY
	movl	(%r15), %esi
	movq	_bxt_phy_ctl_family_write@GOTPCREL(%rip), %r14
	movq	(%r14), %rcx
	movl	%eax, %edi
	xorl	%edx, %edx
	callq	_MMIO_DH
	movq	_DPIO_PHY1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_BXT_PHY_CTL_FAMILY
	movl	(%r15), %esi
	movq	(%r14), %rcx
	movl	%eax, %edi
	xorl	%edx, %edx
	callq	_MMIO_DH
	movq	_PORT_A@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_BXT_PHY_CTL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movq	_PORT_B@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_BXT_PHY_CTL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movq	_PORT_C@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_BXT_PHY_CTL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	callq	_BXT_PORT_PLL_ENABLE
	movl	(%r15), %esi
	movq	_bxt_port_pll_enable_write@GOTPCREL(%rip), %r14
	movq	(%r14), %rcx
	movl	%eax, %edi
	xorl	%edx, %edx
	callq	_MMIO_DH
	movl	(%r13), %edi
	callq	_BXT_PORT_PLL_ENABLE
	movl	(%r15), %esi
	movq	(%r14), %rcx
	movl	%eax, %edi
	xorl	%edx, %edx
	callq	_MMIO_DH
	movl	(%rbx), %edi
	callq	_BXT_PORT_PLL_ENABLE
	movl	(%r15), %esi
	movq	(%r14), %rcx
	movl	%eax, %edi
	xorl	%edx, %edx
	callq	_MMIO_DH
	movl	(%r12), %edi
	callq	_BXT_PORT_CL1CM_DW0
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	callq	_BXT_PORT_CL1CM_DW9
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	callq	_BXT_PORT_CL1CM_DW10
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	callq	_BXT_PORT_CL1CM_DW28
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	callq	_BXT_PORT_CL1CM_DW30
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	callq	_BXT_PORT_CL2CM_DW6
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	callq	_BXT_PORT_REF_DW3
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	callq	_BXT_PORT_REF_DW6
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	callq	_BXT_PORT_REF_DW8
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movq	_DPIO_PHY1@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_BXT_PORT_CL1CM_DW0
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	callq	_BXT_PORT_CL1CM_DW9
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	callq	_BXT_PORT_CL1CM_DW10
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	callq	_BXT_PORT_CL1CM_DW28
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	callq	_BXT_PORT_CL1CM_DW30
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	callq	_BXT_PORT_CL2CM_DW6
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	callq	_BXT_PORT_REF_DW3
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	callq	_BXT_PORT_REF_DW6
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	callq	_BXT_PORT_REF_DW8
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movq	_DPIO_CH0@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	callq	_BXT_PORT_PLL_EBB_0
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_PLL_EBB_4
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_PCS_DW10_LN01
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_PCS_DW10_GRP
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_PCS_DW12_LN01
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_PCS_DW12_LN23
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_PCS_DW12_GRP
	movl	(%r15), %esi
	movq	_bxt_pcs_dw12_grp_write@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	%eax, %edi
	xorl	%edx, %edx
	callq	_MMIO_DH
	movl	(%r12), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_TX_DW2_LN0
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_TX_DW2_GRP
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_TX_DW3_LN0
	movl	(%r15), %esi
	movq	_bxt_port_tx_dw3_read@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rdx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_MMIO_DH
	movl	(%r12), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_TX_DW3_GRP
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_TX_DW4_LN0
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_TX_DW4_GRP
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	xorl	%edx, %edx
	callq	_BXT_PORT_TX_DW14_LN
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	movl	$1, %edx
	callq	_BXT_PORT_TX_DW14_LN
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	movl	$2, %edx
	callq	_BXT_PORT_TX_DW14_LN
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	movl	$3, %edx
	callq	_BXT_PORT_TX_DW14_LN
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	xorl	%edx, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	movl	$1, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	movl	$2, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	movl	$3, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	movl	$6, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	movl	$8, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	movl	$9, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%rbx), %esi
	movl	$10, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movq	_DPIO_CH1@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	callq	_BXT_PORT_PLL_EBB_0
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	callq	_BXT_PORT_PLL_EBB_4
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	callq	_BXT_PORT_PCS_DW10_LN01
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	callq	_BXT_PORT_PCS_DW10_GRP
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	callq	_BXT_PORT_PCS_DW12_LN01
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	callq	_BXT_PORT_PCS_DW12_LN23
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	callq	_BXT_PORT_PCS_DW12_GRP
	movl	(%r15), %esi
	movq	_bxt_pcs_dw12_grp_write@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	%eax, %edi
	xorl	%edx, %edx
	callq	_MMIO_DH
	movl	(%r12), %edi
	movl	(%r13), %esi
	callq	_BXT_PORT_TX_DW2_LN0
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	callq	_BXT_PORT_TX_DW2_GRP
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	callq	_BXT_PORT_TX_DW3_LN0
	movl	(%r15), %esi
	movq	_bxt_port_tx_dw3_read@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rdx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_MMIO_DH
	movl	(%r12), %edi
	movl	(%r13), %esi
	callq	_BXT_PORT_TX_DW3_GRP
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	callq	_BXT_PORT_TX_DW4_LN0
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	callq	_BXT_PORT_TX_DW4_GRP
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	xorl	%edx, %edx
	callq	_BXT_PORT_TX_DW14_LN
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	movl	$1, %edx
	callq	_BXT_PORT_TX_DW14_LN
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	movl	$2, %edx
	callq	_BXT_PORT_TX_DW14_LN
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	movl	$3, %edx
	callq	_BXT_PORT_TX_DW14_LN
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	xorl	%edx, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	movl	$1, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	movl	$2, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	movl	$3, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	movl	$6, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	movl	$8, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	movl	$9, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r12), %edi
	movl	(%r13), %esi
	movl	$10, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_PLL_EBB_0
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_PLL_EBB_4
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_PCS_DW10_LN01
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_PCS_DW10_GRP
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_PCS_DW12_LN01
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_PCS_DW12_LN23
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_PCS_DW12_GRP
	movl	(%r15), %esi
	movq	_bxt_pcs_dw12_grp_write@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	%eax, %edi
	xorl	%edx, %edx
	callq	_MMIO_DH
	movl	(%r14), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_TX_DW2_LN0
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_TX_DW2_GRP
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_TX_DW3_LN0
	movl	(%r15), %esi
	movq	_bxt_port_tx_dw3_read@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rdx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_MMIO_DH
	movl	(%r14), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_TX_DW3_GRP
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_TX_DW4_LN0
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	callq	_BXT_PORT_TX_DW4_GRP
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	xorl	%edx, %edx
	callq	_BXT_PORT_TX_DW14_LN
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	movl	$1, %edx
	callq	_BXT_PORT_TX_DW14_LN
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	movl	$2, %edx
	callq	_BXT_PORT_TX_DW14_LN
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	movl	$3, %edx
	callq	_BXT_PORT_TX_DW14_LN
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	xorl	%edx, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	movl	$1, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	movl	$2, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	movl	$3, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	movl	$6, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	movl	$8, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	movl	$9, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movl	(%r14), %edi
	movl	(%rbx), %esi
	movl	$10, %edx
	callq	_BXT_PORT_PLL
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movq	_BXT_DE_PLL_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_D
	movq	_BXT_DE_PLL_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	movq	_bxt_de_pll_enable_write@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	xorl	%edx, %edx
	callq	_MMIO_DH
	movq	_BXT_DSI_PLL_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_D
	movq	_BXT_DSI_PLL_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_D
	movq	_GEN9_CLKGATE_DIS_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_D
	movq	_GEN9_CLKGATE_DIS_4@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_D
	movq	_TRANSCODER_A@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_HSW_TVIDEO_DIP_GCP
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movq	_TRANSCODER_B@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_HSW_TVIDEO_DIP_GCP
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movq	_TRANSCODER_C@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_HSW_TVIDEO_DIP_GCP
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_MMIO_D
	movq	_RC6_CTX_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_D
	movq	_GEN8_PUSHBUS_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_D
	movq	_GEN8_PUSHBUS_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_D
	movq	_GEN8_PUSHBUS_SHIFT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_D
	movq	_GEN6_GFXPAUSE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	callq	_MMIO_D
	movq	_GEN8_L3SQCREG1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	movq	_F_CMD_ACCESS@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%ecx, %ecx
	xorl	%r8d, %r8d
	callq	_MMIO_DFH
	movq	_GEN9_CTX_PREEMPT_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	movl	(%rbx), %edx
	xorl	%ecx, %ecx
	xorl	%r8d, %r8d
	callq	_MMIO_DFH
	xorl	%eax, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_D_BXT,4,2                      ## @D_BXT
	.comm	_GEN7_SAMPLER_INSTDONE,4,2      ## @GEN7_SAMPLER_INSTDONE
	.comm	_GEN7_ROW_INSTDONE,4,2          ## @GEN7_ROW_INSTDONE
	.comm	_GEN8_FAULT_TLB_DATA0,4,2       ## @GEN8_FAULT_TLB_DATA0
	.comm	_GEN8_FAULT_TLB_DATA1,4,2       ## @GEN8_FAULT_TLB_DATA1
	.comm	_ERROR_GEN6,4,2                 ## @ERROR_GEN6
	.comm	_DONE_REG,4,2                   ## @DONE_REG
	.comm	_EIR,4,2                        ## @EIR
	.comm	_PGTBL_ER,4,2                   ## @PGTBL_ER
	.comm	_RING_PSMI_CTL,4,2              ## @RING_PSMI_CTL
	.comm	_RING_DMA_FADD,4,2              ## @RING_DMA_FADD
	.comm	_RING_DMA_FADD_UDW,4,2          ## @RING_DMA_FADD_UDW
	.comm	_RING_IPEHR,4,2                 ## @RING_IPEHR
	.comm	_RING_INSTPS,4,2                ## @RING_INSTPS
	.comm	_RING_BBADDR_UDW,4,2            ## @RING_BBADDR_UDW
	.comm	_RING_BBSTATE,4,2               ## @RING_BBSTATE
	.comm	_RING_IPEIR,4,2                 ## @RING_IPEIR
	.comm	_BXT_P_CR_GT_DISP_PWRON,4,2     ## @BXT_P_CR_GT_DISP_PWRON
	.comm	_bxt_gt_disp_pwron_write,8,3    ## @bxt_gt_disp_pwron_write
	.comm	_BXT_RP_STATE_CAP,4,2           ## @BXT_RP_STATE_CAP
	.comm	_DPIO_PHY0,4,2                  ## @DPIO_PHY0
	.comm	_bxt_phy_ctl_family_write,8,3   ## @bxt_phy_ctl_family_write
	.comm	_DPIO_PHY1,4,2                  ## @DPIO_PHY1
	.comm	_PORT_A,4,2                     ## @PORT_A
	.comm	_PORT_B,4,2                     ## @PORT_B
	.comm	_PORT_C,4,2                     ## @PORT_C
	.comm	_bxt_port_pll_enable_write,8,3  ## @bxt_port_pll_enable_write
	.comm	_DPIO_CH0,4,2                   ## @DPIO_CH0
	.comm	_bxt_pcs_dw12_grp_write,8,3     ## @bxt_pcs_dw12_grp_write
	.comm	_bxt_port_tx_dw3_read,8,3       ## @bxt_port_tx_dw3_read
	.comm	_DPIO_CH1,4,2                   ## @DPIO_CH1
	.comm	_BXT_DE_PLL_CTL,4,2             ## @BXT_DE_PLL_CTL
	.comm	_BXT_DE_PLL_ENABLE,4,2          ## @BXT_DE_PLL_ENABLE
	.comm	_bxt_de_pll_enable_write,8,3    ## @bxt_de_pll_enable_write
	.comm	_BXT_DSI_PLL_CTL,4,2            ## @BXT_DSI_PLL_CTL
	.comm	_BXT_DSI_PLL_ENABLE,4,2         ## @BXT_DSI_PLL_ENABLE
	.comm	_GEN9_CLKGATE_DIS_0,4,2         ## @GEN9_CLKGATE_DIS_0
	.comm	_GEN9_CLKGATE_DIS_4,4,2         ## @GEN9_CLKGATE_DIS_4
	.comm	_TRANSCODER_A,4,2               ## @TRANSCODER_A
	.comm	_TRANSCODER_B,4,2               ## @TRANSCODER_B
	.comm	_TRANSCODER_C,4,2               ## @TRANSCODER_C
	.comm	_RC6_CTX_BASE,4,2               ## @RC6_CTX_BASE
	.comm	_GEN8_PUSHBUS_CONTROL,4,2       ## @GEN8_PUSHBUS_CONTROL
	.comm	_GEN8_PUSHBUS_ENABLE,4,2        ## @GEN8_PUSHBUS_ENABLE
	.comm	_GEN8_PUSHBUS_SHIFT,4,2         ## @GEN8_PUSHBUS_SHIFT
	.comm	_GEN6_GFXPAUSE,4,2              ## @GEN6_GFXPAUSE
	.comm	_GEN8_L3SQCREG1,4,2             ## @GEN8_L3SQCREG1
	.comm	_F_CMD_ACCESS,4,2               ## @F_CMD_ACCESS
	.comm	_GEN9_CTX_PREEMPT_REG,4,2       ## @GEN9_CTX_PREEMPT_REG
	.no_dead_strip	_init_bxt_mmio_info
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function init_bxt_mmio_info
_init_bxt_mmio_info:                    ; @init_bxt_mmio_info
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	w0, #524288
	bl	__MMIO
Lloh0:
	adrp	x19, _D_BXT@GOTPAGE
Lloh1:
	ldr	x19, [x19, _D_BXT@GOTPAGEOFF]
	ldr	w5, [x19]
	mov	w1, #12288
	mov	w2, #0
	mov	w3, #0
	mov	w4, #0
	mov	x6, #0
	mov	x7, #0
	bl	_MMIO_F
Lloh2:
	adrp	x8, _GEN7_SAMPLER_INSTDONE@GOTPAGE
Lloh3:
	ldr	x8, [x8, _GEN7_SAMPLER_INSTDONE@GOTPAGEOFF]
Lloh4:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh5:
	adrp	x8, _GEN7_ROW_INSTDONE@GOTPAGE
Lloh6:
	ldr	x8, [x8, _GEN7_ROW_INSTDONE@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh8:
	adrp	x8, _GEN8_FAULT_TLB_DATA0@GOTPAGE
Lloh9:
	ldr	x8, [x8, _GEN8_FAULT_TLB_DATA0@GOTPAGEOFF]
Lloh10:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh11:
	adrp	x8, _GEN8_FAULT_TLB_DATA1@GOTPAGE
Lloh12:
	ldr	x8, [x8, _GEN8_FAULT_TLB_DATA1@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh14:
	adrp	x8, _ERROR_GEN6@GOTPAGE
Lloh15:
	ldr	x8, [x8, _ERROR_GEN6@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh17:
	adrp	x8, _DONE_REG@GOTPAGE
Lloh18:
	ldr	x8, [x8, _DONE_REG@GOTPAGEOFF]
Lloh19:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh20:
	adrp	x8, _EIR@GOTPAGE
Lloh21:
	ldr	x8, [x8, _EIR@GOTPAGEOFF]
Lloh22:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh23:
	adrp	x8, _PGTBL_ER@GOTPAGE
Lloh24:
	ldr	x8, [x8, _PGTBL_ER@GOTPAGEOFF]
Lloh25:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_D
	mov	w0, #16788
	bl	__MMIO
	ldr	w1, [x19]
	bl	_MMIO_D
	mov	w0, #17044
	bl	__MMIO
	ldr	w1, [x19]
	bl	_MMIO_D
	mov	w0, #17556
	bl	__MMIO
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh26:
	adrp	x8, _RING_PSMI_CTL@GOTPAGE
Lloh27:
	ldr	x8, [x8, _RING_PSMI_CTL@GOTPAGEOFF]
Lloh28:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_RING_D
Lloh29:
	adrp	x8, _RING_DMA_FADD@GOTPAGE
Lloh30:
	ldr	x8, [x8, _RING_DMA_FADD@GOTPAGEOFF]
Lloh31:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_RING_D
Lloh32:
	adrp	x8, _RING_DMA_FADD_UDW@GOTPAGE
Lloh33:
	ldr	x8, [x8, _RING_DMA_FADD_UDW@GOTPAGEOFF]
Lloh34:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_RING_D
Lloh35:
	adrp	x8, _RING_IPEHR@GOTPAGE
Lloh36:
	ldr	x8, [x8, _RING_IPEHR@GOTPAGEOFF]
Lloh37:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_RING_D
Lloh38:
	adrp	x8, _RING_INSTPS@GOTPAGE
Lloh39:
	ldr	x8, [x8, _RING_INSTPS@GOTPAGEOFF]
Lloh40:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_RING_D
Lloh41:
	adrp	x8, _RING_BBADDR_UDW@GOTPAGE
Lloh42:
	ldr	x8, [x8, _RING_BBADDR_UDW@GOTPAGEOFF]
Lloh43:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_RING_D
Lloh44:
	adrp	x8, _RING_BBSTATE@GOTPAGE
Lloh45:
	ldr	x8, [x8, _RING_BBSTATE@GOTPAGEOFF]
Lloh46:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_RING_D
Lloh47:
	adrp	x8, _RING_IPEIR@GOTPAGE
Lloh48:
	ldr	x8, [x8, _RING_IPEIR@GOTPAGEOFF]
Lloh49:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_RING_D
	mov	w0, #0
	bl	_SOFT_SCRATCH
	ldr	w5, [x19]
	mov	w1, #64
	mov	w2, #0
	mov	w3, #0
	mov	w4, #0
	mov	x6, #0
	mov	x7, #0
	bl	_MMIO_F
Lloh50:
	adrp	x8, _BXT_P_CR_GT_DISP_PWRON@GOTPAGE
Lloh51:
	ldr	x8, [x8, _BXT_P_CR_GT_DISP_PWRON@GOTPAGEOFF]
Lloh52:
	ldr	w0, [x8]
	ldr	w1, [x19]
Lloh53:
	adrp	x8, _bxt_gt_disp_pwron_write@GOTPAGE
Lloh54:
	ldr	x8, [x8, _bxt_gt_disp_pwron_write@GOTPAGEOFF]
Lloh55:
	ldr	x3, [x8]
	mov	x2, #0
	bl	_MMIO_DH
Lloh56:
	adrp	x8, _BXT_RP_STATE_CAP@GOTPAGE
Lloh57:
	ldr	x8, [x8, _BXT_RP_STATE_CAP@GOTPAGEOFF]
Lloh58:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh59:
	adrp	x22, _DPIO_PHY0@GOTPAGE
Lloh60:
	ldr	x22, [x22, _DPIO_PHY0@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_BXT_PHY_CTL_FAMILY
	ldr	w1, [x19]
Lloh61:
	adrp	x21, _bxt_phy_ctl_family_write@GOTPAGE
Lloh62:
	ldr	x21, [x21, _bxt_phy_ctl_family_write@GOTPAGEOFF]
	ldr	x3, [x21]
	mov	x2, #0
	bl	_MMIO_DH
Lloh63:
	adrp	x20, _DPIO_PHY1@GOTPAGE
Lloh64:
	ldr	x20, [x20, _DPIO_PHY1@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_BXT_PHY_CTL_FAMILY
	ldr	w1, [x19]
	ldr	x3, [x21]
	mov	x2, #0
	bl	_MMIO_DH
Lloh65:
	adrp	x21, _PORT_A@GOTPAGE
Lloh66:
	ldr	x21, [x21, _PORT_A@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_BXT_PHY_CTL
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh67:
	adrp	x23, _PORT_B@GOTPAGE
Lloh68:
	ldr	x23, [x23, _PORT_B@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_BXT_PHY_CTL
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh69:
	adrp	x24, _PORT_C@GOTPAGE
Lloh70:
	ldr	x24, [x24, _PORT_C@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_BXT_PHY_CTL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x21]
	bl	_BXT_PORT_PLL_ENABLE
	ldr	w1, [x19]
Lloh71:
	adrp	x21, _bxt_port_pll_enable_write@GOTPAGE
Lloh72:
	ldr	x21, [x21, _bxt_port_pll_enable_write@GOTPAGEOFF]
	ldr	x3, [x21]
	mov	x2, #0
	bl	_MMIO_DH
	ldr	w0, [x23]
	bl	_BXT_PORT_PLL_ENABLE
	ldr	w1, [x19]
	ldr	x3, [x21]
	mov	x2, #0
	bl	_MMIO_DH
	ldr	w0, [x24]
	bl	_BXT_PORT_PLL_ENABLE
	ldr	w1, [x19]
	ldr	x3, [x21]
	mov	x2, #0
	bl	_MMIO_DH
	ldr	w0, [x22]
	bl	_BXT_PORT_CL1CM_DW0
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	bl	_BXT_PORT_CL1CM_DW9
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	bl	_BXT_PORT_CL1CM_DW10
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	bl	_BXT_PORT_CL1CM_DW28
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	bl	_BXT_PORT_CL1CM_DW30
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	bl	_BXT_PORT_CL2CM_DW6
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	bl	_BXT_PORT_REF_DW3
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	bl	_BXT_PORT_REF_DW6
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	bl	_BXT_PORT_REF_DW8
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	bl	_BXT_PORT_CL1CM_DW0
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	bl	_BXT_PORT_CL1CM_DW9
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	bl	_BXT_PORT_CL1CM_DW10
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	bl	_BXT_PORT_CL1CM_DW28
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	bl	_BXT_PORT_CL1CM_DW30
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	bl	_BXT_PORT_CL2CM_DW6
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	bl	_BXT_PORT_REF_DW3
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	bl	_BXT_PORT_REF_DW6
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	bl	_BXT_PORT_REF_DW8
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
Lloh73:
	adrp	x21, _DPIO_CH0@GOTPAGE
Lloh74:
	ldr	x21, [x21, _DPIO_CH0@GOTPAGEOFF]
	ldr	w1, [x21]
	bl	_BXT_PORT_PLL_EBB_0
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	bl	_BXT_PORT_PLL_EBB_4
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	bl	_BXT_PORT_PCS_DW10_LN01
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	bl	_BXT_PORT_PCS_DW10_GRP
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	bl	_BXT_PORT_PCS_DW12_LN01
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	bl	_BXT_PORT_PCS_DW12_LN23
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	bl	_BXT_PORT_PCS_DW12_GRP
	ldr	w1, [x19]
Lloh75:
	adrp	x23, _bxt_pcs_dw12_grp_write@GOTPAGE
Lloh76:
	ldr	x23, [x23, _bxt_pcs_dw12_grp_write@GOTPAGEOFF]
	ldr	x3, [x23]
	mov	x2, #0
	bl	_MMIO_DH
	ldr	w0, [x22]
	ldr	w1, [x21]
	bl	_BXT_PORT_TX_DW2_LN0
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	bl	_BXT_PORT_TX_DW2_GRP
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	bl	_BXT_PORT_TX_DW3_LN0
	ldr	w1, [x19]
Lloh77:
	adrp	x24, _bxt_port_tx_dw3_read@GOTPAGE
Lloh78:
	ldr	x24, [x24, _bxt_port_tx_dw3_read@GOTPAGEOFF]
	ldr	x2, [x24]
	mov	x3, #0
	bl	_MMIO_DH
	ldr	w0, [x22]
	ldr	w1, [x21]
	bl	_BXT_PORT_TX_DW3_GRP
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	bl	_BXT_PORT_TX_DW4_LN0
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	bl	_BXT_PORT_TX_DW4_GRP
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	mov	w2, #0
	bl	_BXT_PORT_TX_DW14_LN
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	mov	w2, #1
	bl	_BXT_PORT_TX_DW14_LN
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	mov	w2, #2
	bl	_BXT_PORT_TX_DW14_LN
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	mov	w2, #3
	bl	_BXT_PORT_TX_DW14_LN
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	mov	w2, #0
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	mov	w2, #1
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	mov	w2, #2
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	mov	w2, #3
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	mov	w2, #6
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	mov	w2, #8
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	mov	w2, #9
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x21]
	mov	w2, #10
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
Lloh79:
	adrp	x25, _DPIO_CH1@GOTPAGE
Lloh80:
	ldr	x25, [x25, _DPIO_CH1@GOTPAGEOFF]
	ldr	w1, [x25]
	bl	_BXT_PORT_PLL_EBB_0
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	bl	_BXT_PORT_PLL_EBB_4
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	bl	_BXT_PORT_PCS_DW10_LN01
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	bl	_BXT_PORT_PCS_DW10_GRP
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	bl	_BXT_PORT_PCS_DW12_LN01
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	bl	_BXT_PORT_PCS_DW12_LN23
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	bl	_BXT_PORT_PCS_DW12_GRP
	ldr	w1, [x19]
	ldr	x3, [x23]
	mov	x2, #0
	bl	_MMIO_DH
	ldr	w0, [x22]
	ldr	w1, [x25]
	bl	_BXT_PORT_TX_DW2_LN0
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	bl	_BXT_PORT_TX_DW2_GRP
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	bl	_BXT_PORT_TX_DW3_LN0
	ldr	w1, [x19]
	ldr	x2, [x24]
	mov	x3, #0
	bl	_MMIO_DH
	ldr	w0, [x22]
	ldr	w1, [x25]
	bl	_BXT_PORT_TX_DW3_GRP
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	bl	_BXT_PORT_TX_DW4_LN0
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	bl	_BXT_PORT_TX_DW4_GRP
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	mov	w2, #0
	bl	_BXT_PORT_TX_DW14_LN
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	mov	w2, #1
	bl	_BXT_PORT_TX_DW14_LN
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	mov	w2, #2
	bl	_BXT_PORT_TX_DW14_LN
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	mov	w2, #3
	bl	_BXT_PORT_TX_DW14_LN
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	mov	w2, #0
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	mov	w2, #1
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	mov	w2, #2
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	mov	w2, #3
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	mov	w2, #6
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	mov	w2, #8
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	mov	w2, #9
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x22]
	ldr	w1, [x25]
	mov	w2, #10
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	bl	_BXT_PORT_PLL_EBB_0
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	bl	_BXT_PORT_PLL_EBB_4
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	bl	_BXT_PORT_PCS_DW10_LN01
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	bl	_BXT_PORT_PCS_DW10_GRP
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	bl	_BXT_PORT_PCS_DW12_LN01
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	bl	_BXT_PORT_PCS_DW12_LN23
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	bl	_BXT_PORT_PCS_DW12_GRP
	ldr	w1, [x19]
	ldr	x3, [x23]
	mov	x2, #0
	bl	_MMIO_DH
	ldr	w0, [x20]
	ldr	w1, [x21]
	bl	_BXT_PORT_TX_DW2_LN0
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	bl	_BXT_PORT_TX_DW2_GRP
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	bl	_BXT_PORT_TX_DW3_LN0
	ldr	w1, [x19]
	ldr	x2, [x24]
	mov	x3, #0
	bl	_MMIO_DH
	ldr	w0, [x20]
	ldr	w1, [x21]
	bl	_BXT_PORT_TX_DW3_GRP
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	bl	_BXT_PORT_TX_DW4_LN0
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	bl	_BXT_PORT_TX_DW4_GRP
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	mov	w2, #0
	bl	_BXT_PORT_TX_DW14_LN
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	mov	w2, #1
	bl	_BXT_PORT_TX_DW14_LN
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	mov	w2, #2
	bl	_BXT_PORT_TX_DW14_LN
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	mov	w2, #3
	bl	_BXT_PORT_TX_DW14_LN
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	mov	w2, #0
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	mov	w2, #1
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	mov	w2, #2
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	mov	w2, #3
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	mov	w2, #6
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	mov	w2, #8
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	mov	w2, #9
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
	ldr	w0, [x20]
	ldr	w1, [x21]
	mov	w2, #10
	bl	_BXT_PORT_PLL
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh81:
	adrp	x8, _BXT_DE_PLL_CTL@GOTPAGE
Lloh82:
	ldr	x8, [x8, _BXT_DE_PLL_CTL@GOTPAGEOFF]
Lloh83:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh84:
	adrp	x8, _BXT_DE_PLL_ENABLE@GOTPAGE
Lloh85:
	ldr	x8, [x8, _BXT_DE_PLL_ENABLE@GOTPAGEOFF]
Lloh86:
	ldr	w0, [x8]
	ldr	w1, [x19]
Lloh87:
	adrp	x8, _bxt_de_pll_enable_write@GOTPAGE
Lloh88:
	ldr	x8, [x8, _bxt_de_pll_enable_write@GOTPAGEOFF]
Lloh89:
	ldr	x3, [x8]
	mov	x2, #0
	bl	_MMIO_DH
Lloh90:
	adrp	x8, _BXT_DSI_PLL_CTL@GOTPAGE
Lloh91:
	ldr	x8, [x8, _BXT_DSI_PLL_CTL@GOTPAGEOFF]
Lloh92:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh93:
	adrp	x8, _BXT_DSI_PLL_ENABLE@GOTPAGE
Lloh94:
	ldr	x8, [x8, _BXT_DSI_PLL_ENABLE@GOTPAGEOFF]
Lloh95:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh96:
	adrp	x8, _GEN9_CLKGATE_DIS_0@GOTPAGE
Lloh97:
	ldr	x8, [x8, _GEN9_CLKGATE_DIS_0@GOTPAGEOFF]
Lloh98:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh99:
	adrp	x8, _GEN9_CLKGATE_DIS_4@GOTPAGE
Lloh100:
	ldr	x8, [x8, _GEN9_CLKGATE_DIS_4@GOTPAGEOFF]
Lloh101:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh102:
	adrp	x8, _TRANSCODER_A@GOTPAGE
Lloh103:
	ldr	x8, [x8, _TRANSCODER_A@GOTPAGEOFF]
Lloh104:
	ldr	w0, [x8]
	bl	_HSW_TVIDEO_DIP_GCP
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh105:
	adrp	x8, _TRANSCODER_B@GOTPAGE
Lloh106:
	ldr	x8, [x8, _TRANSCODER_B@GOTPAGEOFF]
Lloh107:
	ldr	w0, [x8]
	bl	_HSW_TVIDEO_DIP_GCP
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh108:
	adrp	x8, _TRANSCODER_C@GOTPAGE
Lloh109:
	ldr	x8, [x8, _TRANSCODER_C@GOTPAGEOFF]
Lloh110:
	ldr	w0, [x8]
	bl	_HSW_TVIDEO_DIP_GCP
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh111:
	adrp	x8, _RC6_CTX_BASE@GOTPAGE
Lloh112:
	ldr	x8, [x8, _RC6_CTX_BASE@GOTPAGEOFF]
Lloh113:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh114:
	adrp	x8, _GEN8_PUSHBUS_CONTROL@GOTPAGE
Lloh115:
	ldr	x8, [x8, _GEN8_PUSHBUS_CONTROL@GOTPAGEOFF]
Lloh116:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh117:
	adrp	x8, _GEN8_PUSHBUS_ENABLE@GOTPAGE
Lloh118:
	ldr	x8, [x8, _GEN8_PUSHBUS_ENABLE@GOTPAGEOFF]
Lloh119:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh120:
	adrp	x8, _GEN8_PUSHBUS_SHIFT@GOTPAGE
Lloh121:
	ldr	x8, [x8, _GEN8_PUSHBUS_SHIFT@GOTPAGEOFF]
Lloh122:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh123:
	adrp	x8, _GEN6_GFXPAUSE@GOTPAGE
Lloh124:
	ldr	x8, [x8, _GEN6_GFXPAUSE@GOTPAGEOFF]
Lloh125:
	ldr	w0, [x8]
	ldr	w1, [x19]
	bl	_MMIO_D
Lloh126:
	adrp	x8, _GEN8_L3SQCREG1@GOTPAGE
Lloh127:
	ldr	x8, [x8, _GEN8_L3SQCREG1@GOTPAGEOFF]
Lloh128:
	ldr	w0, [x8]
	ldr	w1, [x19]
Lloh129:
	adrp	x20, _F_CMD_ACCESS@GOTPAGE
Lloh130:
	ldr	x20, [x20, _F_CMD_ACCESS@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	x3, #0
	mov	x4, #0
	bl	_MMIO_DFH
Lloh131:
	adrp	x8, _GEN9_CTX_PREEMPT_REG@GOTPAGE
Lloh132:
	ldr	x8, [x8, _GEN9_CTX_PREEMPT_REG@GOTPAGEOFF]
Lloh133:
	ldr	w0, [x8]
	ldr	w1, [x19]
	ldr	w2, [x20]
	mov	x3, #0
	mov	x4, #0
	bl	_MMIO_DFH
	mov	w0, #0
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh131, Lloh132, Lloh133
	.loh AdrpLdrGot	Lloh129, Lloh130
	.loh AdrpLdrGotLdr	Lloh126, Lloh127, Lloh128
	.loh AdrpLdrGotLdr	Lloh123, Lloh124, Lloh125
	.loh AdrpLdrGotLdr	Lloh120, Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGot	Lloh79, Lloh80
	.loh AdrpLdrGot	Lloh77, Lloh78
	.loh AdrpLdrGot	Lloh75, Lloh76
	.loh AdrpLdrGot	Lloh73, Lloh74
	.loh AdrpLdrGot	Lloh71, Lloh72
	.loh AdrpLdrGot	Lloh69, Lloh70
	.loh AdrpLdrGot	Lloh67, Lloh68
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGot	Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpLdrGot	Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_D_BXT,4,2                      ; @D_BXT
	.comm	_GEN7_SAMPLER_INSTDONE,4,2      ; @GEN7_SAMPLER_INSTDONE
	.comm	_GEN7_ROW_INSTDONE,4,2          ; @GEN7_ROW_INSTDONE
	.comm	_GEN8_FAULT_TLB_DATA0,4,2       ; @GEN8_FAULT_TLB_DATA0
	.comm	_GEN8_FAULT_TLB_DATA1,4,2       ; @GEN8_FAULT_TLB_DATA1
	.comm	_ERROR_GEN6,4,2                 ; @ERROR_GEN6
	.comm	_DONE_REG,4,2                   ; @DONE_REG
	.comm	_EIR,4,2                        ; @EIR
	.comm	_PGTBL_ER,4,2                   ; @PGTBL_ER
	.comm	_RING_PSMI_CTL,4,2              ; @RING_PSMI_CTL
	.comm	_RING_DMA_FADD,4,2              ; @RING_DMA_FADD
	.comm	_RING_DMA_FADD_UDW,4,2          ; @RING_DMA_FADD_UDW
	.comm	_RING_IPEHR,4,2                 ; @RING_IPEHR
	.comm	_RING_INSTPS,4,2                ; @RING_INSTPS
	.comm	_RING_BBADDR_UDW,4,2            ; @RING_BBADDR_UDW
	.comm	_RING_BBSTATE,4,2               ; @RING_BBSTATE
	.comm	_RING_IPEIR,4,2                 ; @RING_IPEIR
	.comm	_BXT_P_CR_GT_DISP_PWRON,4,2     ; @BXT_P_CR_GT_DISP_PWRON
	.comm	_bxt_gt_disp_pwron_write,8,3    ; @bxt_gt_disp_pwron_write
	.comm	_BXT_RP_STATE_CAP,4,2           ; @BXT_RP_STATE_CAP
	.comm	_DPIO_PHY0,4,2                  ; @DPIO_PHY0
	.comm	_bxt_phy_ctl_family_write,8,3   ; @bxt_phy_ctl_family_write
	.comm	_DPIO_PHY1,4,2                  ; @DPIO_PHY1
	.comm	_PORT_A,4,2                     ; @PORT_A
	.comm	_PORT_B,4,2                     ; @PORT_B
	.comm	_PORT_C,4,2                     ; @PORT_C
	.comm	_bxt_port_pll_enable_write,8,3  ; @bxt_port_pll_enable_write
	.comm	_DPIO_CH0,4,2                   ; @DPIO_CH0
	.comm	_bxt_pcs_dw12_grp_write,8,3     ; @bxt_pcs_dw12_grp_write
	.comm	_bxt_port_tx_dw3_read,8,3       ; @bxt_port_tx_dw3_read
	.comm	_DPIO_CH1,4,2                   ; @DPIO_CH1
	.comm	_BXT_DE_PLL_CTL,4,2             ; @BXT_DE_PLL_CTL
	.comm	_BXT_DE_PLL_ENABLE,4,2          ; @BXT_DE_PLL_ENABLE
	.comm	_bxt_de_pll_enable_write,8,3    ; @bxt_de_pll_enable_write
	.comm	_BXT_DSI_PLL_CTL,4,2            ; @BXT_DSI_PLL_CTL
	.comm	_BXT_DSI_PLL_ENABLE,4,2         ; @BXT_DSI_PLL_ENABLE
	.comm	_GEN9_CLKGATE_DIS_0,4,2         ; @GEN9_CLKGATE_DIS_0
	.comm	_GEN9_CLKGATE_DIS_4,4,2         ; @GEN9_CLKGATE_DIS_4
	.comm	_TRANSCODER_A,4,2               ; @TRANSCODER_A
	.comm	_TRANSCODER_B,4,2               ; @TRANSCODER_B
	.comm	_TRANSCODER_C,4,2               ; @TRANSCODER_C
	.comm	_RC6_CTX_BASE,4,2               ; @RC6_CTX_BASE
	.comm	_GEN8_PUSHBUS_CONTROL,4,2       ; @GEN8_PUSHBUS_CONTROL
	.comm	_GEN8_PUSHBUS_ENABLE,4,2        ; @GEN8_PUSHBUS_ENABLE
	.comm	_GEN8_PUSHBUS_SHIFT,4,2         ; @GEN8_PUSHBUS_SHIFT
	.comm	_GEN6_GFXPAUSE,4,2              ; @GEN6_GFXPAUSE
	.comm	_GEN8_L3SQCREG1,4,2             ; @GEN8_L3SQCREG1
	.comm	_F_CMD_ACCESS,4,2               ; @F_CMD_ACCESS
	.comm	_GEN9_CTX_PREEMPT_REG,4,2       ; @GEN9_CTX_PREEMPT_REG
	.no_dead_strip	_init_bxt_mmio_info
.subsections_via_symbols
