	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_intel_init_display_hooks       ## -- Begin function intel_init_display_hooks
	.p2align	4, 0x90
_intel_init_display_hooks:              ## @intel_init_display_hooks
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	callq	_intel_init_cdclk_hooks
	movq	%rbx, %rdi
	callq	_INTEL_GEN
	cmpl	$9, %eax
	jl	LBB0_3
## %bb.1:
	movq	_haswell_get_pipe_config@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 40(%rbx)
	movq	_skylake_get_initial_plane_config@GOTPCREL(%rip), %rax
	jmp	LBB0_2
LBB0_3:
	movq	%rbx, %rdi
	callq	_HAS_DDI
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	movq	_haswell_get_pipe_config@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 40(%rbx)
	movq	_i9xx_get_initial_plane_config@GOTPCREL(%rip), %rax
LBB0_2:
	movq	(%rax), %rax
	movq	%rax, 32(%rbx)
	movq	_haswell_crtc_disable@GOTPCREL(%rip), %rax
	movq	_haswell_crtc_enable@GOTPCREL(%rip), %rcx
	movq	_haswell_crtc_compute_clock@GOTPCREL(%rip), %rdx
LBB0_19:
	movq	(%rdx), %rdx
	movq	%rdx, 24(%rbx)
	movq	(%rcx), %rcx
	movq	%rcx, 16(%rbx)
	movq	(%rax), %rax
	movq	%rax, 8(%rbx)
	movq	%rbx, %rdi
	movl	$5, %esi
	callq	_IS_GEN
	testq	%rax, %rax
	je	LBB0_21
## %bb.20:
	movq	_ironlake_fdi_link_train@GOTPCREL(%rip), %r14
	jmp	LBB0_27
LBB0_21:
	movq	%rbx, %rdi
	movl	$6, %esi
	callq	_IS_GEN
	testq	%rax, %rax
	je	LBB0_23
## %bb.22:
	movq	_gen6_fdi_link_train@GOTPCREL(%rip), %r14
	jmp	LBB0_27
LBB0_5:
	movq	%rbx, %rdi
	callq	_HAS_PCH_SPLIT
	testq	%rax, %rax
	je	LBB0_7
## %bb.6:
	movq	_ironlake_get_pipe_config@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 40(%rbx)
	movq	_i9xx_get_initial_plane_config@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 32(%rbx)
	movq	_ironlake_crtc_disable@GOTPCREL(%rip), %rax
	movq	_ironlake_crtc_enable@GOTPCREL(%rip), %rcx
	movq	_ironlake_crtc_compute_clock@GOTPCREL(%rip), %rdx
	jmp	LBB0_19
LBB0_23:
	movq	%rbx, %rdi
	callq	_IS_IVYBRIDGE
	testq	%rax, %rax
	je	LBB0_25
## %bb.24:
	movq	_ivb_manual_fdi_link_train@GOTPCREL(%rip), %r14
	jmp	LBB0_27
LBB0_7:
	movq	%rbx, %rdi
	callq	_IS_CHERRYVIEW
	testq	%rax, %rax
	je	LBB0_9
## %bb.8:
	movq	_i9xx_get_pipe_config@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 40(%rbx)
	movq	_i9xx_get_initial_plane_config@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 32(%rbx)
	movq	_i9xx_crtc_disable@GOTPCREL(%rip), %rax
	movq	_valleyview_crtc_enable@GOTPCREL(%rip), %rcx
	movq	_chv_crtc_compute_clock@GOTPCREL(%rip), %rdx
	jmp	LBB0_19
LBB0_25:
	movq	%rbx, %rdi
	callq	_IS_HASWELL
	movq	_hsw_fdi_link_train@GOTPCREL(%rip), %r14
	testq	%rax, %rax
	jne	LBB0_27
## %bb.26:
	movq	%rbx, %rdi
	callq	_IS_BROADWELL
	testq	%rax, %rax
	je	LBB0_28
LBB0_27:
	movl	(%r14), %eax
	movl	%eax, 4(%rbx)
LBB0_28:
	movq	%rbx, %rdi
	callq	_INTEL_GEN
	cmpl	$9, %eax
	jl	LBB0_29
## %bb.30:
	movq	_skl_update_crtcs@GOTPCREL(%rip), %rax
	jmp	LBB0_31
LBB0_29:
	movq	_intel_update_crtcs@GOTPCREL(%rip), %rax
LBB0_31:
	movl	(%rax), %eax
	movl	%eax, (%rbx)
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
LBB0_9:
	movq	%rbx, %rdi
	callq	_IS_VALLEYVIEW
	testq	%rax, %rax
	je	LBB0_11
## %bb.10:
	movq	_i9xx_get_pipe_config@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 40(%rbx)
	movq	_i9xx_get_initial_plane_config@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 32(%rbx)
	movq	_i9xx_crtc_disable@GOTPCREL(%rip), %rax
	movq	_valleyview_crtc_enable@GOTPCREL(%rip), %rcx
	movq	_vlv_crtc_compute_clock@GOTPCREL(%rip), %rdx
	jmp	LBB0_19
LBB0_11:
	movq	%rbx, %rdi
	callq	_IS_G4X
	testq	%rax, %rax
	je	LBB0_13
## %bb.12:
	movq	_i9xx_get_pipe_config@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 40(%rbx)
	movq	_i9xx_get_initial_plane_config@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 32(%rbx)
	movq	_i9xx_crtc_disable@GOTPCREL(%rip), %rax
	movq	_i9xx_crtc_enable@GOTPCREL(%rip), %rcx
	movq	_g4x_crtc_compute_clock@GOTPCREL(%rip), %rdx
	jmp	LBB0_19
LBB0_13:
	movq	%rbx, %rdi
	callq	_IS_PINEVIEW
	testq	%rax, %rax
	je	LBB0_15
## %bb.14:
	movq	_i9xx_get_pipe_config@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 40(%rbx)
	movq	_i9xx_get_initial_plane_config@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 32(%rbx)
	movq	_i9xx_crtc_disable@GOTPCREL(%rip), %rax
	movq	_i9xx_crtc_enable@GOTPCREL(%rip), %rcx
	movq	_pnv_crtc_compute_clock@GOTPCREL(%rip), %rdx
	jmp	LBB0_19
LBB0_15:
	movq	%rbx, %rdi
	movl	$2, %esi
	callq	_IS_GEN
	movq	_i9xx_get_pipe_config@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, 40(%rbx)
	movq	_i9xx_get_initial_plane_config@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, 32(%rbx)
	testq	%rax, %rax
	jne	LBB0_16
## %bb.17:
	movq	_i9xx_crtc_compute_clock@GOTPCREL(%rip), %rdx
	jmp	LBB0_18
LBB0_16:
	movq	_i8xx_crtc_compute_clock@GOTPCREL(%rip), %rdx
LBB0_18:
	movq	_i9xx_crtc_disable@GOTPCREL(%rip), %rax
	movq	_i9xx_crtc_enable@GOTPCREL(%rip), %rcx
	jmp	LBB0_19
	.cfi_endproc
                                        ## -- End function
	.comm	_haswell_get_pipe_config,8,3    ## @haswell_get_pipe_config
	.comm	_skylake_get_initial_plane_config,8,3 ## @skylake_get_initial_plane_config
	.comm	_haswell_crtc_compute_clock,8,3 ## @haswell_crtc_compute_clock
	.comm	_haswell_crtc_enable,8,3        ## @haswell_crtc_enable
	.comm	_haswell_crtc_disable,8,3       ## @haswell_crtc_disable
	.comm	_i9xx_get_initial_plane_config,8,3 ## @i9xx_get_initial_plane_config
	.comm	_ironlake_get_pipe_config,8,3   ## @ironlake_get_pipe_config
	.comm	_ironlake_crtc_compute_clock,8,3 ## @ironlake_crtc_compute_clock
	.comm	_ironlake_crtc_enable,8,3       ## @ironlake_crtc_enable
	.comm	_ironlake_crtc_disable,8,3      ## @ironlake_crtc_disable
	.comm	_i9xx_get_pipe_config,8,3       ## @i9xx_get_pipe_config
	.comm	_chv_crtc_compute_clock,8,3     ## @chv_crtc_compute_clock
	.comm	_valleyview_crtc_enable,8,3     ## @valleyview_crtc_enable
	.comm	_i9xx_crtc_disable,8,3          ## @i9xx_crtc_disable
	.comm	_vlv_crtc_compute_clock,8,3     ## @vlv_crtc_compute_clock
	.comm	_g4x_crtc_compute_clock,8,3     ## @g4x_crtc_compute_clock
	.comm	_i9xx_crtc_enable,8,3           ## @i9xx_crtc_enable
	.comm	_pnv_crtc_compute_clock,8,3     ## @pnv_crtc_compute_clock
	.comm	_i9xx_crtc_compute_clock,8,3    ## @i9xx_crtc_compute_clock
	.comm	_i8xx_crtc_compute_clock,8,3    ## @i8xx_crtc_compute_clock
	.comm	_ironlake_fdi_link_train,4,2    ## @ironlake_fdi_link_train
	.comm	_gen6_fdi_link_train,4,2        ## @gen6_fdi_link_train
	.comm	_ivb_manual_fdi_link_train,4,2  ## @ivb_manual_fdi_link_train
	.comm	_hsw_fdi_link_train,4,2         ## @hsw_fdi_link_train
	.comm	_skl_update_crtcs,4,2           ## @skl_update_crtcs
	.comm	_intel_update_crtcs,4,2         ## @intel_update_crtcs
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_intel_init_display_hooks       ; -- Begin function intel_init_display_hooks
	.p2align	2
_intel_init_display_hooks:              ; @intel_init_display_hooks
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_intel_init_cdclk_hooks
	mov	x0, x19
	bl	_INTEL_GEN
	cmp	w0, #9
	b.lt	LBB0_2
; %bb.1:
Lloh0:
	adrp	x8, _haswell_get_pipe_config@GOTPAGE
Lloh1:
	ldr	x8, [x8, _haswell_get_pipe_config@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
Lloh3:
	adrp	x9, _skylake_get_initial_plane_config@GOTPAGE
Lloh4:
	ldr	x9, [x9, _skylake_get_initial_plane_config@GOTPAGEOFF]
	b	LBB0_4
LBB0_2:
	mov	x0, x19
	bl	_HAS_DDI
	cbz	x0, LBB0_9
; %bb.3:
Lloh5:
	adrp	x8, _haswell_get_pipe_config@GOTPAGE
Lloh6:
	ldr	x8, [x8, _haswell_get_pipe_config@GOTPAGEOFF]
Lloh7:
	ldr	x8, [x8]
Lloh8:
	adrp	x9, _i9xx_get_initial_plane_config@GOTPAGE
Lloh9:
	ldr	x9, [x9, _i9xx_get_initial_plane_config@GOTPAGEOFF]
LBB0_4:
	ldr	x9, [x9]
	stp	x9, x8, [x19, #32]
Lloh10:
	adrp	x8, _haswell_crtc_disable@GOTPAGE
Lloh11:
	ldr	x8, [x8, _haswell_crtc_disable@GOTPAGEOFF]
Lloh12:
	adrp	x9, _haswell_crtc_enable@GOTPAGE
Lloh13:
	ldr	x9, [x9, _haswell_crtc_enable@GOTPAGEOFF]
Lloh14:
	adrp	x10, _haswell_crtc_compute_clock@GOTPAGE
Lloh15:
	ldr	x10, [x10, _haswell_crtc_compute_clock@GOTPAGEOFF]
LBB0_5:
	ldr	x10, [x10]
	ldr	x9, [x9]
	ldr	x8, [x8]
	stp	x9, x10, [x19, #16]
	str	x8, [x19, #8]
	mov	x0, x19
	mov	w1, #5
	bl	_IS_GEN
	cbz	x0, LBB0_7
; %bb.6:
Lloh16:
	adrp	x8, _ironlake_fdi_link_train@GOTPAGE
Lloh17:
	ldr	x8, [x8, _ironlake_fdi_link_train@GOTPAGEOFF]
	b	LBB0_18
LBB0_7:
	mov	x0, x19
	mov	w1, #6
	bl	_IS_GEN
	cbz	x0, LBB0_11
; %bb.8:
Lloh18:
	adrp	x8, _gen6_fdi_link_train@GOTPAGE
Lloh19:
	ldr	x8, [x8, _gen6_fdi_link_train@GOTPAGEOFF]
	b	LBB0_18
LBB0_9:
	mov	x0, x19
	bl	_HAS_PCH_SPLIT
	cbz	x0, LBB0_13
; %bb.10:
Lloh20:
	adrp	x8, _ironlake_get_pipe_config@GOTPAGE
Lloh21:
	ldr	x8, [x8, _ironlake_get_pipe_config@GOTPAGEOFF]
Lloh22:
	ldr	x8, [x8]
Lloh23:
	adrp	x9, _i9xx_get_initial_plane_config@GOTPAGE
Lloh24:
	ldr	x9, [x9, _i9xx_get_initial_plane_config@GOTPAGEOFF]
Lloh25:
	ldr	x9, [x9]
	stp	x9, x8, [x19, #32]
Lloh26:
	adrp	x8, _ironlake_crtc_disable@GOTPAGE
Lloh27:
	ldr	x8, [x8, _ironlake_crtc_disable@GOTPAGEOFF]
Lloh28:
	adrp	x9, _ironlake_crtc_enable@GOTPAGE
Lloh29:
	ldr	x9, [x9, _ironlake_crtc_enable@GOTPAGEOFF]
Lloh30:
	adrp	x10, _ironlake_crtc_compute_clock@GOTPAGE
Lloh31:
	ldr	x10, [x10, _ironlake_crtc_compute_clock@GOTPAGEOFF]
	b	LBB0_5
LBB0_11:
	mov	x0, x19
	bl	_IS_IVYBRIDGE
	cbz	x0, LBB0_15
; %bb.12:
Lloh32:
	adrp	x8, _ivb_manual_fdi_link_train@GOTPAGE
Lloh33:
	ldr	x8, [x8, _ivb_manual_fdi_link_train@GOTPAGEOFF]
	b	LBB0_18
LBB0_13:
	mov	x0, x19
	bl	_IS_CHERRYVIEW
	cbz	x0, LBB0_20
; %bb.14:
Lloh34:
	adrp	x8, _i9xx_get_pipe_config@GOTPAGE
Lloh35:
	ldr	x8, [x8, _i9xx_get_pipe_config@GOTPAGEOFF]
Lloh36:
	ldr	x8, [x8]
Lloh37:
	adrp	x9, _i9xx_get_initial_plane_config@GOTPAGE
Lloh38:
	ldr	x9, [x9, _i9xx_get_initial_plane_config@GOTPAGEOFF]
Lloh39:
	ldr	x9, [x9]
	stp	x9, x8, [x19, #32]
Lloh40:
	adrp	x8, _i9xx_crtc_disable@GOTPAGE
Lloh41:
	ldr	x8, [x8, _i9xx_crtc_disable@GOTPAGEOFF]
Lloh42:
	adrp	x9, _valleyview_crtc_enable@GOTPAGE
Lloh43:
	ldr	x9, [x9, _valleyview_crtc_enable@GOTPAGEOFF]
Lloh44:
	adrp	x10, _chv_crtc_compute_clock@GOTPAGE
Lloh45:
	ldr	x10, [x10, _chv_crtc_compute_clock@GOTPAGEOFF]
	b	LBB0_5
LBB0_15:
	mov	x0, x19
	bl	_IS_HASWELL
	cbnz	x0, LBB0_17
; %bb.16:
	mov	x0, x19
	bl	_IS_BROADWELL
	cbz	x0, LBB0_19
LBB0_17:
Lloh46:
	adrp	x8, _hsw_fdi_link_train@GOTPAGE
Lloh47:
	ldr	x8, [x8, _hsw_fdi_link_train@GOTPAGEOFF]
LBB0_18:
	ldr	w8, [x8]
	str	w8, [x19, #4]
LBB0_19:
	mov	x0, x19
	bl	_INTEL_GEN
Lloh48:
	adrp	x8, _skl_update_crtcs@GOTPAGE
Lloh49:
	ldr	x8, [x8, _skl_update_crtcs@GOTPAGEOFF]
Lloh50:
	adrp	x9, _intel_update_crtcs@GOTPAGE
Lloh51:
	ldr	x9, [x9, _intel_update_crtcs@GOTPAGEOFF]
	cmp	w0, #8
	csel	x8, x8, x9, gt
	ldr	w8, [x8]
	str	w8, [x19]
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_20:
	mov	x0, x19
	bl	_IS_VALLEYVIEW
	cbz	x0, LBB0_22
; %bb.21:
Lloh52:
	adrp	x8, _i9xx_get_pipe_config@GOTPAGE
Lloh53:
	ldr	x8, [x8, _i9xx_get_pipe_config@GOTPAGEOFF]
Lloh54:
	ldr	x8, [x8]
Lloh55:
	adrp	x9, _i9xx_get_initial_plane_config@GOTPAGE
Lloh56:
	ldr	x9, [x9, _i9xx_get_initial_plane_config@GOTPAGEOFF]
Lloh57:
	ldr	x9, [x9]
	stp	x9, x8, [x19, #32]
Lloh58:
	adrp	x8, _i9xx_crtc_disable@GOTPAGE
Lloh59:
	ldr	x8, [x8, _i9xx_crtc_disable@GOTPAGEOFF]
Lloh60:
	adrp	x9, _valleyview_crtc_enable@GOTPAGE
Lloh61:
	ldr	x9, [x9, _valleyview_crtc_enable@GOTPAGEOFF]
Lloh62:
	adrp	x10, _vlv_crtc_compute_clock@GOTPAGE
Lloh63:
	ldr	x10, [x10, _vlv_crtc_compute_clock@GOTPAGEOFF]
	b	LBB0_5
LBB0_22:
	mov	x0, x19
	bl	_IS_G4X
	cbz	x0, LBB0_24
; %bb.23:
Lloh64:
	adrp	x8, _i9xx_get_pipe_config@GOTPAGE
Lloh65:
	ldr	x8, [x8, _i9xx_get_pipe_config@GOTPAGEOFF]
Lloh66:
	ldr	x8, [x8]
Lloh67:
	adrp	x9, _i9xx_get_initial_plane_config@GOTPAGE
Lloh68:
	ldr	x9, [x9, _i9xx_get_initial_plane_config@GOTPAGEOFF]
Lloh69:
	ldr	x9, [x9]
	stp	x9, x8, [x19, #32]
Lloh70:
	adrp	x8, _i9xx_crtc_disable@GOTPAGE
Lloh71:
	ldr	x8, [x8, _i9xx_crtc_disable@GOTPAGEOFF]
Lloh72:
	adrp	x9, _i9xx_crtc_enable@GOTPAGE
Lloh73:
	ldr	x9, [x9, _i9xx_crtc_enable@GOTPAGEOFF]
Lloh74:
	adrp	x10, _g4x_crtc_compute_clock@GOTPAGE
Lloh75:
	ldr	x10, [x10, _g4x_crtc_compute_clock@GOTPAGEOFF]
	b	LBB0_5
LBB0_24:
	mov	x0, x19
	bl	_IS_PINEVIEW
	cbz	x0, LBB0_26
; %bb.25:
Lloh76:
	adrp	x8, _i9xx_get_pipe_config@GOTPAGE
Lloh77:
	ldr	x8, [x8, _i9xx_get_pipe_config@GOTPAGEOFF]
Lloh78:
	ldr	x8, [x8]
Lloh79:
	adrp	x9, _i9xx_get_initial_plane_config@GOTPAGE
Lloh80:
	ldr	x9, [x9, _i9xx_get_initial_plane_config@GOTPAGEOFF]
Lloh81:
	ldr	x9, [x9]
	stp	x9, x8, [x19, #32]
Lloh82:
	adrp	x8, _i9xx_crtc_disable@GOTPAGE
Lloh83:
	ldr	x8, [x8, _i9xx_crtc_disable@GOTPAGEOFF]
Lloh84:
	adrp	x9, _i9xx_crtc_enable@GOTPAGE
Lloh85:
	ldr	x9, [x9, _i9xx_crtc_enable@GOTPAGEOFF]
Lloh86:
	adrp	x10, _pnv_crtc_compute_clock@GOTPAGE
Lloh87:
	ldr	x10, [x10, _pnv_crtc_compute_clock@GOTPAGEOFF]
	b	LBB0_5
LBB0_26:
	mov	x0, x19
	mov	w1, #2
	bl	_IS_GEN
Lloh88:
	adrp	x8, _i9xx_get_pipe_config@GOTPAGE
Lloh89:
	ldr	x8, [x8, _i9xx_get_pipe_config@GOTPAGEOFF]
Lloh90:
	ldr	x8, [x8]
Lloh91:
	adrp	x9, _i9xx_get_initial_plane_config@GOTPAGE
Lloh92:
	ldr	x9, [x9, _i9xx_get_initial_plane_config@GOTPAGEOFF]
Lloh93:
	ldr	x9, [x9]
	stp	x9, x8, [x19, #32]
Lloh94:
	adrp	x8, _i8xx_crtc_compute_clock@GOTPAGE
Lloh95:
	ldr	x8, [x8, _i8xx_crtc_compute_clock@GOTPAGEOFF]
Lloh96:
	adrp	x9, _i9xx_crtc_compute_clock@GOTPAGE
Lloh97:
	ldr	x9, [x9, _i9xx_crtc_compute_clock@GOTPAGEOFF]
	cmp	x0, #0
	csel	x10, x9, x8, eq
Lloh98:
	adrp	x8, _i9xx_crtc_disable@GOTPAGE
Lloh99:
	ldr	x8, [x8, _i9xx_crtc_disable@GOTPAGEOFF]
Lloh100:
	adrp	x9, _i9xx_crtc_enable@GOTPAGE
Lloh101:
	ldr	x9, [x9, _i9xx_crtc_enable@GOTPAGEOFF]
	b	LBB0_5
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGot	Lloh62, Lloh63
	.loh AdrpLdrGot	Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh74, Lloh75
	.loh AdrpLdrGot	Lloh72, Lloh73
	.loh AdrpLdrGot	Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGot	Lloh86, Lloh87
	.loh AdrpLdrGot	Lloh84, Lloh85
	.loh AdrpLdrGot	Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGot	Lloh100, Lloh101
	.loh AdrpLdrGot	Lloh98, Lloh99
	.loh AdrpLdrGot	Lloh96, Lloh97
	.loh AdrpLdrGot	Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.cfi_endproc
                                        ; -- End function
	.comm	_haswell_get_pipe_config,8,3    ; @haswell_get_pipe_config
	.comm	_skylake_get_initial_plane_config,8,3 ; @skylake_get_initial_plane_config
	.comm	_haswell_crtc_compute_clock,8,3 ; @haswell_crtc_compute_clock
	.comm	_haswell_crtc_enable,8,3        ; @haswell_crtc_enable
	.comm	_haswell_crtc_disable,8,3       ; @haswell_crtc_disable
	.comm	_i9xx_get_initial_plane_config,8,3 ; @i9xx_get_initial_plane_config
	.comm	_ironlake_get_pipe_config,8,3   ; @ironlake_get_pipe_config
	.comm	_ironlake_crtc_compute_clock,8,3 ; @ironlake_crtc_compute_clock
	.comm	_ironlake_crtc_enable,8,3       ; @ironlake_crtc_enable
	.comm	_ironlake_crtc_disable,8,3      ; @ironlake_crtc_disable
	.comm	_i9xx_get_pipe_config,8,3       ; @i9xx_get_pipe_config
	.comm	_chv_crtc_compute_clock,8,3     ; @chv_crtc_compute_clock
	.comm	_valleyview_crtc_enable,8,3     ; @valleyview_crtc_enable
	.comm	_i9xx_crtc_disable,8,3          ; @i9xx_crtc_disable
	.comm	_vlv_crtc_compute_clock,8,3     ; @vlv_crtc_compute_clock
	.comm	_g4x_crtc_compute_clock,8,3     ; @g4x_crtc_compute_clock
	.comm	_i9xx_crtc_enable,8,3           ; @i9xx_crtc_enable
	.comm	_pnv_crtc_compute_clock,8,3     ; @pnv_crtc_compute_clock
	.comm	_i9xx_crtc_compute_clock,8,3    ; @i9xx_crtc_compute_clock
	.comm	_i8xx_crtc_compute_clock,8,3    ; @i8xx_crtc_compute_clock
	.comm	_ironlake_fdi_link_train,4,2    ; @ironlake_fdi_link_train
	.comm	_gen6_fdi_link_train,4,2        ; @gen6_fdi_link_train
	.comm	_ivb_manual_fdi_link_train,4,2  ; @ivb_manual_fdi_link_train
	.comm	_hsw_fdi_link_train,4,2         ; @hsw_fdi_link_train
	.comm	_skl_update_crtcs,4,2           ; @skl_update_crtcs
	.comm	_intel_update_crtcs,4,2         ; @intel_update_crtcs
.subsections_via_symbols
