	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function max30102_chip_init
_max30102_chip_init:                    ## @max30102_chip_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	callq	_max30102_led_init
	testl	%eax, %eax
	jne	LBB0_3
## %bb.1:
	movl	(%rbx), %edi
	movq	_MAX30102_REG_SPO2_CONFIG@GOTPCREL(%rip), %rdx
	movq	_MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %eax
	movq	_MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	movl	(%rdx), %esi
	movq	_MAX30102_REG_SPO2_CONFIG_SR_400HZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	orl	%eax, %edx
	movq	_MAX30102_REG_SPO2_CONFIG_PULSE_411_US@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	callq	_regmap_write
	testl	%eax, %eax
	jne	LBB0_3
## %bb.2:
	movl	(%rbx), %edi
	movq	_MAX30102_REG_FIFO_CONFIG@GOTPCREL(%rip), %rax
	movq	_MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_MAX30102_REG_FIFO_CONFIG_AVG_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	movl	(%rax), %esi
	movq	_MAX30102_REG_FIFO_CONFIG_AFULL@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	callq	_regmap_write
	testl	%eax, %eax
	je	LBB0_4
LBB0_3:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
LBB0_4:
	movl	(%rbx), %edi
	movq	_MAX30102_REG_INT_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MAX30102_REG_INT_ENABLE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_MAX30102_REG_INT_ENABLE_FIFO_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_regmap_update_bits             ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_MAX30102_REG_SPO2_CONFIG,4,2   ## @MAX30102_REG_SPO2_CONFIG
	.comm	_MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS,4,2 ## @MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS
	.comm	_MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT,4,2 ## @MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT
	.comm	_MAX30102_REG_SPO2_CONFIG_SR_400HZ,4,2 ## @MAX30102_REG_SPO2_CONFIG_SR_400HZ
	.comm	_MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT,4,2 ## @MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT
	.comm	_MAX30102_REG_SPO2_CONFIG_PULSE_411_US,4,2 ## @MAX30102_REG_SPO2_CONFIG_PULSE_411_US
	.comm	_MAX30102_REG_FIFO_CONFIG,4,2   ## @MAX30102_REG_FIFO_CONFIG
	.comm	_MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES,4,2 ## @MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES
	.comm	_MAX30102_REG_FIFO_CONFIG_AVG_SHIFT,4,2 ## @MAX30102_REG_FIFO_CONFIG_AVG_SHIFT
	.comm	_MAX30102_REG_FIFO_CONFIG_AFULL,4,2 ## @MAX30102_REG_FIFO_CONFIG_AFULL
	.comm	_MAX30102_REG_INT_ENABLE,4,2    ## @MAX30102_REG_INT_ENABLE
	.comm	_MAX30102_REG_INT_ENABLE_MASK,4,2 ## @MAX30102_REG_INT_ENABLE_MASK
	.comm	_MAX30102_REG_INT_ENABLE_FIFO_EN,4,2 ## @MAX30102_REG_INT_ENABLE_FIFO_EN
	.no_dead_strip	_max30102_chip_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function max30102_chip_init
_max30102_chip_init:                    ; @max30102_chip_init
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_max30102_led_init
	cbnz	w0, LBB0_3
; %bb.1:
	ldr	w0, [x19]
Lloh0:
	adrp	x8, _MAX30102_REG_SPO2_CONFIG@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MAX30102_REG_SPO2_CONFIG@GOTPAGEOFF]
Lloh2:
	adrp	x9, _MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS@GOTPAGE
Lloh3:
	ldr	x9, [x9, _MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
Lloh5:
	ldr	w8, [x9]
Lloh6:
	adrp	x9, _MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT@GOTPAGE
Lloh7:
	ldr	x9, [x9, _MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	lsl	w8, w8, w9
Lloh9:
	adrp	x9, _MAX30102_REG_SPO2_CONFIG_SR_400HZ@GOTPAGE
Lloh10:
	ldr	x9, [x9, _MAX30102_REG_SPO2_CONFIG_SR_400HZ@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
Lloh12:
	adrp	x10, _MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT@GOTPAGE
Lloh13:
	ldr	x10, [x10, _MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT@GOTPAGEOFF]
Lloh14:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w8, w9, w8
Lloh15:
	adrp	x9, _MAX30102_REG_SPO2_CONFIG_PULSE_411_US@GOTPAGE
Lloh16:
	ldr	x9, [x9, _MAX30102_REG_SPO2_CONFIG_PULSE_411_US@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	orr	w2, w8, w9
	bl	_regmap_write
	cbnz	w0, LBB0_3
; %bb.2:
	ldr	w0, [x19]
Lloh18:
	adrp	x8, _MAX30102_REG_FIFO_CONFIG@GOTPAGE
Lloh19:
	ldr	x8, [x8, _MAX30102_REG_FIFO_CONFIG@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
Lloh21:
	adrp	x8, _MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES@GOTPAGE
Lloh22:
	ldr	x8, [x8, _MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
Lloh24:
	adrp	x9, _MAX30102_REG_FIFO_CONFIG_AVG_SHIFT@GOTPAGE
Lloh25:
	ldr	x9, [x9, _MAX30102_REG_FIFO_CONFIG_AVG_SHIFT@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	lsl	w8, w8, w9
Lloh27:
	adrp	x9, _MAX30102_REG_FIFO_CONFIG_AFULL@GOTPAGE
Lloh28:
	ldr	x9, [x9, _MAX30102_REG_FIFO_CONFIG_AFULL@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	orr	w2, w8, w9
	bl	_regmap_write
	cbz	w0, LBB0_4
LBB0_3:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_4:
Lloh30:
	adrp	x8, _MAX30102_REG_INT_ENABLE@GOTPAGE
Lloh31:
	ldr	x8, [x8, _MAX30102_REG_INT_ENABLE@GOTPAGEOFF]
	ldr	w0, [x19]
Lloh32:
	ldr	w1, [x8]
Lloh33:
	adrp	x8, _MAX30102_REG_INT_ENABLE_MASK@GOTPAGE
Lloh34:
	ldr	x8, [x8, _MAX30102_REG_INT_ENABLE_MASK@GOTPAGEOFF]
Lloh35:
	adrp	x9, _MAX30102_REG_INT_ENABLE_FIFO_EN@GOTPAGE
Lloh36:
	ldr	x9, [x9, _MAX30102_REG_INT_ENABLE_FIFO_EN@GOTPAGEOFF]
Lloh37:
	ldr	w2, [x8]
Lloh38:
	ldr	w3, [x9]
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_regmap_update_bits
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh4
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh37
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.cfi_endproc
                                        ; -- End function
	.comm	_MAX30102_REG_SPO2_CONFIG,4,2   ; @MAX30102_REG_SPO2_CONFIG
	.comm	_MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS,4,2 ; @MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS
	.comm	_MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT,4,2 ; @MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT
	.comm	_MAX30102_REG_SPO2_CONFIG_SR_400HZ,4,2 ; @MAX30102_REG_SPO2_CONFIG_SR_400HZ
	.comm	_MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT,4,2 ; @MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT
	.comm	_MAX30102_REG_SPO2_CONFIG_PULSE_411_US,4,2 ; @MAX30102_REG_SPO2_CONFIG_PULSE_411_US
	.comm	_MAX30102_REG_FIFO_CONFIG,4,2   ; @MAX30102_REG_FIFO_CONFIG
	.comm	_MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES,4,2 ; @MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES
	.comm	_MAX30102_REG_FIFO_CONFIG_AVG_SHIFT,4,2 ; @MAX30102_REG_FIFO_CONFIG_AVG_SHIFT
	.comm	_MAX30102_REG_FIFO_CONFIG_AFULL,4,2 ; @MAX30102_REG_FIFO_CONFIG_AFULL
	.comm	_MAX30102_REG_INT_ENABLE,4,2    ; @MAX30102_REG_INT_ENABLE
	.comm	_MAX30102_REG_INT_ENABLE_MASK,4,2 ; @MAX30102_REG_INT_ENABLE_MASK
	.comm	_MAX30102_REG_INT_ENABLE_FIFO_EN,4,2 ; @MAX30102_REG_INT_ENABLE_FIFO_EN
	.no_dead_strip	_max30102_chip_init
.subsections_via_symbols
