	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function td028ttec1_prepare
_td028ttec1_prepare:                    ## @td028ttec1_prepare
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	callq	_to_td028ttec1_device
	movq	%rax, %rbx
	movl	$0, -28(%rbp)
	leaq	-28(%rbp), %r14
	movq	%rax, %rdi
	xorl	%esi, %esi
	movq	%r14, %rdx
	callq	_jbt_ret_write_0
	movl	$1000, %edi                     ## imm = 0x3E8
	movl	$2000, %esi                     ## imm = 0x7D0
	callq	_usleep_range
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movq	%r14, %rdx
	callq	_jbt_ret_write_0
	movl	$1000, %edi                     ## imm = 0x3E8
	movl	$2000, %esi                     ## imm = 0x7D0
	callq	_usleep_range
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movq	%r14, %rdx
	callq	_jbt_ret_write_0
	movl	$1000, %edi                     ## imm = 0x3E8
	movl	$2000, %esi                     ## imm = 0x7D0
	callq	_usleep_range
	movq	_JBT_REG_POWER_ON_OFF@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	movl	$23, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_DISPLAY_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$128, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_QUAD_RATE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movl	(%r15), %esi
	movq	%rbx, %rdi
	movl	$22, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_OUTPUT_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$65529, %edx                    ## imm = 0xFFF9
	movq	%r14, %rcx
	callq	_jbt_reg_write_2
	movq	_JBT_REG_SLEEP_OUT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	callq	_jbt_ret_write_0
	movq	_JBT_REG_DISPLAY_MODE1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_DISPLAY_MODE2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_RGB_FORMAT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$96, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_DRIVE_SYSTEM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$16, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_BOOSTER_OP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$86, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_BOOSTER_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$51, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_BOOSTER_FREQ@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	movl	$17, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movl	(%r15), %esi
	movq	%rbx, %rdi
	movl	$17, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_OPAMP_SYSCLK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$2, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_VSC_VOLTAGE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$43, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_VCOM_VOLTAGE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$64, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_EXT_DISPL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$3, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_DCCLK_DCEV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$4, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_ASW_SLEW@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$4, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_DUMMY_DISPLAY@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_SLEEP_OUT_FR_A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$17, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_SLEEP_OUT_FR_B@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$17, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_SLEEP_OUT_FR_C@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$17, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_SLEEP_IN_LCCNT_D@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$8256, %edx                     ## imm = 0x2040
	movq	%r14, %rcx
	callq	_jbt_reg_write_2
	movq	_JBT_REG_SLEEP_IN_LCCNT_E@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$24768, %edx                    ## imm = 0x60C0
	movq	%r14, %rcx
	callq	_jbt_reg_write_2
	movq	_JBT_REG_SLEEP_IN_LCCNT_F@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$4128, %edx                     ## imm = 0x1020
	movq	%r14, %rcx
	callq	_jbt_reg_write_2
	movq	_JBT_REG_SLEEP_IN_LCCNT_G@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$24768, %edx                    ## imm = 0x60C0
	movq	%r14, %rcx
	callq	_jbt_reg_write_2
	movq	_JBT_REG_GAMMA1_FINE_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$21811, %edx                    ## imm = 0x5533
	movq	%r14, %rcx
	callq	_jbt_reg_write_2
	movq	_JBT_REG_GAMMA1_FINE_2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_GAMMA1_INCLINATION@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_GAMMA1_BLUE_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_HCLOCK_VGA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$496, %edx                      ## imm = 0x1F0
	movq	%r14, %rcx
	callq	_jbt_reg_write_2
	movq	_JBT_REG_BLANK_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$2, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_BLANK_TH_TV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$2052, %edx                     ## imm = 0x804
	movq	%r14, %rcx
	callq	_jbt_reg_write_2
	movq	_JBT_REG_CKV_ON_OFF@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movq	_JBT_REG_CKV_1_2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_2
	movq	_JBT_REG_OEV_TIMING@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$3342, %edx                     ## imm = 0xD0E
	movq	%r14, %rcx
	callq	_jbt_reg_write_2
	movq	_JBT_REG_ASW_TIMING_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$4516, %edx                     ## imm = 0x11A4
	movq	%r14, %rcx
	callq	_jbt_reg_write_2
	movq	_JBT_REG_ASW_TIMING_2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$14, %edx
	movq	%r14, %rcx
	callq	_jbt_reg_write_1
	movl	-28(%rbp), %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_JBT_REG_POWER_ON_OFF,4,2       ## @JBT_REG_POWER_ON_OFF
	.comm	_JBT_REG_DISPLAY_MODE,4,2       ## @JBT_REG_DISPLAY_MODE
	.comm	_JBT_REG_QUAD_RATE,4,2          ## @JBT_REG_QUAD_RATE
	.comm	_JBT_REG_OUTPUT_CONTROL,4,2     ## @JBT_REG_OUTPUT_CONTROL
	.comm	_JBT_REG_SLEEP_OUT,4,2          ## @JBT_REG_SLEEP_OUT
	.comm	_JBT_REG_DISPLAY_MODE1,4,2      ## @JBT_REG_DISPLAY_MODE1
	.comm	_JBT_REG_DISPLAY_MODE2,4,2      ## @JBT_REG_DISPLAY_MODE2
	.comm	_JBT_REG_RGB_FORMAT,4,2         ## @JBT_REG_RGB_FORMAT
	.comm	_JBT_REG_DRIVE_SYSTEM,4,2       ## @JBT_REG_DRIVE_SYSTEM
	.comm	_JBT_REG_BOOSTER_OP,4,2         ## @JBT_REG_BOOSTER_OP
	.comm	_JBT_REG_BOOSTER_MODE,4,2       ## @JBT_REG_BOOSTER_MODE
	.comm	_JBT_REG_BOOSTER_FREQ,4,2       ## @JBT_REG_BOOSTER_FREQ
	.comm	_JBT_REG_OPAMP_SYSCLK,4,2       ## @JBT_REG_OPAMP_SYSCLK
	.comm	_JBT_REG_VSC_VOLTAGE,4,2        ## @JBT_REG_VSC_VOLTAGE
	.comm	_JBT_REG_VCOM_VOLTAGE,4,2       ## @JBT_REG_VCOM_VOLTAGE
	.comm	_JBT_REG_EXT_DISPL,4,2          ## @JBT_REG_EXT_DISPL
	.comm	_JBT_REG_DCCLK_DCEV,4,2         ## @JBT_REG_DCCLK_DCEV
	.comm	_JBT_REG_ASW_SLEW,4,2           ## @JBT_REG_ASW_SLEW
	.comm	_JBT_REG_DUMMY_DISPLAY,4,2      ## @JBT_REG_DUMMY_DISPLAY
	.comm	_JBT_REG_SLEEP_OUT_FR_A,4,2     ## @JBT_REG_SLEEP_OUT_FR_A
	.comm	_JBT_REG_SLEEP_OUT_FR_B,4,2     ## @JBT_REG_SLEEP_OUT_FR_B
	.comm	_JBT_REG_SLEEP_OUT_FR_C,4,2     ## @JBT_REG_SLEEP_OUT_FR_C
	.comm	_JBT_REG_SLEEP_IN_LCCNT_D,4,2   ## @JBT_REG_SLEEP_IN_LCCNT_D
	.comm	_JBT_REG_SLEEP_IN_LCCNT_E,4,2   ## @JBT_REG_SLEEP_IN_LCCNT_E
	.comm	_JBT_REG_SLEEP_IN_LCCNT_F,4,2   ## @JBT_REG_SLEEP_IN_LCCNT_F
	.comm	_JBT_REG_SLEEP_IN_LCCNT_G,4,2   ## @JBT_REG_SLEEP_IN_LCCNT_G
	.comm	_JBT_REG_GAMMA1_FINE_1,4,2      ## @JBT_REG_GAMMA1_FINE_1
	.comm	_JBT_REG_GAMMA1_FINE_2,4,2      ## @JBT_REG_GAMMA1_FINE_2
	.comm	_JBT_REG_GAMMA1_INCLINATION,4,2 ## @JBT_REG_GAMMA1_INCLINATION
	.comm	_JBT_REG_GAMMA1_BLUE_OFFSET,4,2 ## @JBT_REG_GAMMA1_BLUE_OFFSET
	.comm	_JBT_REG_HCLOCK_VGA,4,2         ## @JBT_REG_HCLOCK_VGA
	.comm	_JBT_REG_BLANK_CONTROL,4,2      ## @JBT_REG_BLANK_CONTROL
	.comm	_JBT_REG_BLANK_TH_TV,4,2        ## @JBT_REG_BLANK_TH_TV
	.comm	_JBT_REG_CKV_ON_OFF,4,2         ## @JBT_REG_CKV_ON_OFF
	.comm	_JBT_REG_CKV_1_2,4,2            ## @JBT_REG_CKV_1_2
	.comm	_JBT_REG_OEV_TIMING,4,2         ## @JBT_REG_OEV_TIMING
	.comm	_JBT_REG_ASW_TIMING_1,4,2       ## @JBT_REG_ASW_TIMING_1
	.comm	_JBT_REG_ASW_TIMING_2,4,2       ## @JBT_REG_ASW_TIMING_2
	.no_dead_strip	_td028ttec1_prepare
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function td028ttec1_prepare
_td028ttec1_prepare:                    ; @td028ttec1_prepare
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #48
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	bl	_to_td028ttec1_device
	mov	x19, x0
	str	wzr, [sp, #12]
	add	x2, sp, #12
	mov	w1, #0
	bl	_jbt_ret_write_0
	mov	w0, #1000
	mov	w1, #2000
	bl	_usleep_range
	add	x2, sp, #12
	mov	x0, x19
	mov	w1, #0
	bl	_jbt_ret_write_0
	mov	w0, #1000
	mov	w1, #2000
	bl	_usleep_range
	add	x2, sp, #12
	mov	x0, x19
	mov	w1, #0
	bl	_jbt_ret_write_0
	mov	w0, #1000
	mov	w1, #2000
	bl	_usleep_range
Lloh0:
	adrp	x20, _JBT_REG_POWER_ON_OFF@GOTPAGE
Lloh1:
	ldr	x20, [x20, _JBT_REG_POWER_ON_OFF@GOTPAGEOFF]
	ldr	w1, [x20]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #23
	bl	_jbt_reg_write_1
Lloh2:
	adrp	x8, _JBT_REG_DISPLAY_MODE@GOTPAGE
Lloh3:
	ldr	x8, [x8, _JBT_REG_DISPLAY_MODE@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #128
	bl	_jbt_reg_write_1
Lloh5:
	adrp	x8, _JBT_REG_QUAD_RATE@GOTPAGE
Lloh6:
	ldr	x8, [x8, _JBT_REG_QUAD_RATE@GOTPAGEOFF]
Lloh7:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #0
	bl	_jbt_reg_write_1
	ldr	w1, [x20]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #22
	bl	_jbt_reg_write_1
Lloh8:
	adrp	x8, _JBT_REG_OUTPUT_CONTROL@GOTPAGE
Lloh9:
	ldr	x8, [x8, _JBT_REG_OUTPUT_CONTROL@GOTPAGEOFF]
Lloh10:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #65529
	bl	_jbt_reg_write_2
Lloh11:
	adrp	x8, _JBT_REG_SLEEP_OUT@GOTPAGE
Lloh12:
	ldr	x8, [x8, _JBT_REG_SLEEP_OUT@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
	add	x2, sp, #12
	mov	x0, x19
	bl	_jbt_ret_write_0
Lloh14:
	adrp	x8, _JBT_REG_DISPLAY_MODE1@GOTPAGE
Lloh15:
	ldr	x8, [x8, _JBT_REG_DISPLAY_MODE1@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #1
	bl	_jbt_reg_write_1
Lloh17:
	adrp	x8, _JBT_REG_DISPLAY_MODE2@GOTPAGE
Lloh18:
	ldr	x8, [x8, _JBT_REG_DISPLAY_MODE2@GOTPAGEOFF]
Lloh19:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #0
	bl	_jbt_reg_write_1
Lloh20:
	adrp	x8, _JBT_REG_RGB_FORMAT@GOTPAGE
Lloh21:
	ldr	x8, [x8, _JBT_REG_RGB_FORMAT@GOTPAGEOFF]
Lloh22:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #96
	bl	_jbt_reg_write_1
Lloh23:
	adrp	x8, _JBT_REG_DRIVE_SYSTEM@GOTPAGE
Lloh24:
	ldr	x8, [x8, _JBT_REG_DRIVE_SYSTEM@GOTPAGEOFF]
Lloh25:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #16
	bl	_jbt_reg_write_1
Lloh26:
	adrp	x8, _JBT_REG_BOOSTER_OP@GOTPAGE
Lloh27:
	ldr	x8, [x8, _JBT_REG_BOOSTER_OP@GOTPAGEOFF]
Lloh28:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #86
	bl	_jbt_reg_write_1
Lloh29:
	adrp	x8, _JBT_REG_BOOSTER_MODE@GOTPAGE
Lloh30:
	ldr	x8, [x8, _JBT_REG_BOOSTER_MODE@GOTPAGEOFF]
Lloh31:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #51
	bl	_jbt_reg_write_1
Lloh32:
	adrp	x20, _JBT_REG_BOOSTER_FREQ@GOTPAGE
Lloh33:
	ldr	x20, [x20, _JBT_REG_BOOSTER_FREQ@GOTPAGEOFF]
	ldr	w1, [x20]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #17
	bl	_jbt_reg_write_1
	ldr	w1, [x20]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #17
	bl	_jbt_reg_write_1
Lloh34:
	adrp	x8, _JBT_REG_OPAMP_SYSCLK@GOTPAGE
Lloh35:
	ldr	x8, [x8, _JBT_REG_OPAMP_SYSCLK@GOTPAGEOFF]
Lloh36:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #2
	bl	_jbt_reg_write_1
Lloh37:
	adrp	x8, _JBT_REG_VSC_VOLTAGE@GOTPAGE
Lloh38:
	ldr	x8, [x8, _JBT_REG_VSC_VOLTAGE@GOTPAGEOFF]
Lloh39:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #43
	bl	_jbt_reg_write_1
Lloh40:
	adrp	x8, _JBT_REG_VCOM_VOLTAGE@GOTPAGE
Lloh41:
	ldr	x8, [x8, _JBT_REG_VCOM_VOLTAGE@GOTPAGEOFF]
Lloh42:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #64
	bl	_jbt_reg_write_1
Lloh43:
	adrp	x8, _JBT_REG_EXT_DISPL@GOTPAGE
Lloh44:
	ldr	x8, [x8, _JBT_REG_EXT_DISPL@GOTPAGEOFF]
Lloh45:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #3
	bl	_jbt_reg_write_1
Lloh46:
	adrp	x8, _JBT_REG_DCCLK_DCEV@GOTPAGE
Lloh47:
	ldr	x8, [x8, _JBT_REG_DCCLK_DCEV@GOTPAGEOFF]
Lloh48:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #4
	bl	_jbt_reg_write_1
Lloh49:
	adrp	x8, _JBT_REG_ASW_SLEW@GOTPAGE
Lloh50:
	ldr	x8, [x8, _JBT_REG_ASW_SLEW@GOTPAGEOFF]
Lloh51:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #4
	bl	_jbt_reg_write_1
Lloh52:
	adrp	x8, _JBT_REG_DUMMY_DISPLAY@GOTPAGE
Lloh53:
	ldr	x8, [x8, _JBT_REG_DUMMY_DISPLAY@GOTPAGEOFF]
Lloh54:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #0
	bl	_jbt_reg_write_1
Lloh55:
	adrp	x8, _JBT_REG_SLEEP_OUT_FR_A@GOTPAGE
Lloh56:
	ldr	x8, [x8, _JBT_REG_SLEEP_OUT_FR_A@GOTPAGEOFF]
Lloh57:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #17
	bl	_jbt_reg_write_1
Lloh58:
	adrp	x8, _JBT_REG_SLEEP_OUT_FR_B@GOTPAGE
Lloh59:
	ldr	x8, [x8, _JBT_REG_SLEEP_OUT_FR_B@GOTPAGEOFF]
Lloh60:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #17
	bl	_jbt_reg_write_1
Lloh61:
	adrp	x8, _JBT_REG_SLEEP_OUT_FR_C@GOTPAGE
Lloh62:
	ldr	x8, [x8, _JBT_REG_SLEEP_OUT_FR_C@GOTPAGEOFF]
Lloh63:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #17
	bl	_jbt_reg_write_1
Lloh64:
	adrp	x8, _JBT_REG_SLEEP_IN_LCCNT_D@GOTPAGE
Lloh65:
	ldr	x8, [x8, _JBT_REG_SLEEP_IN_LCCNT_D@GOTPAGEOFF]
Lloh66:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #8256
	bl	_jbt_reg_write_2
Lloh67:
	adrp	x8, _JBT_REG_SLEEP_IN_LCCNT_E@GOTPAGE
Lloh68:
	ldr	x8, [x8, _JBT_REG_SLEEP_IN_LCCNT_E@GOTPAGEOFF]
Lloh69:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #24768
	bl	_jbt_reg_write_2
Lloh70:
	adrp	x8, _JBT_REG_SLEEP_IN_LCCNT_F@GOTPAGE
Lloh71:
	ldr	x8, [x8, _JBT_REG_SLEEP_IN_LCCNT_F@GOTPAGEOFF]
Lloh72:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #4128
	bl	_jbt_reg_write_2
Lloh73:
	adrp	x8, _JBT_REG_SLEEP_IN_LCCNT_G@GOTPAGE
Lloh74:
	ldr	x8, [x8, _JBT_REG_SLEEP_IN_LCCNT_G@GOTPAGEOFF]
Lloh75:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #24768
	bl	_jbt_reg_write_2
Lloh76:
	adrp	x8, _JBT_REG_GAMMA1_FINE_1@GOTPAGE
Lloh77:
	ldr	x8, [x8, _JBT_REG_GAMMA1_FINE_1@GOTPAGEOFF]
Lloh78:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #21811
	bl	_jbt_reg_write_2
Lloh79:
	adrp	x8, _JBT_REG_GAMMA1_FINE_2@GOTPAGE
Lloh80:
	ldr	x8, [x8, _JBT_REG_GAMMA1_FINE_2@GOTPAGEOFF]
Lloh81:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #0
	bl	_jbt_reg_write_1
Lloh82:
	adrp	x8, _JBT_REG_GAMMA1_INCLINATION@GOTPAGE
Lloh83:
	ldr	x8, [x8, _JBT_REG_GAMMA1_INCLINATION@GOTPAGEOFF]
Lloh84:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #0
	bl	_jbt_reg_write_1
Lloh85:
	adrp	x8, _JBT_REG_GAMMA1_BLUE_OFFSET@GOTPAGE
Lloh86:
	ldr	x8, [x8, _JBT_REG_GAMMA1_BLUE_OFFSET@GOTPAGEOFF]
Lloh87:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #0
	bl	_jbt_reg_write_1
Lloh88:
	adrp	x8, _JBT_REG_HCLOCK_VGA@GOTPAGE
Lloh89:
	ldr	x8, [x8, _JBT_REG_HCLOCK_VGA@GOTPAGEOFF]
Lloh90:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #496
	bl	_jbt_reg_write_2
Lloh91:
	adrp	x8, _JBT_REG_BLANK_CONTROL@GOTPAGE
Lloh92:
	ldr	x8, [x8, _JBT_REG_BLANK_CONTROL@GOTPAGEOFF]
Lloh93:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #2
	bl	_jbt_reg_write_1
Lloh94:
	adrp	x8, _JBT_REG_BLANK_TH_TV@GOTPAGE
Lloh95:
	ldr	x8, [x8, _JBT_REG_BLANK_TH_TV@GOTPAGEOFF]
Lloh96:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #2052
	bl	_jbt_reg_write_2
Lloh97:
	adrp	x8, _JBT_REG_CKV_ON_OFF@GOTPAGE
Lloh98:
	ldr	x8, [x8, _JBT_REG_CKV_ON_OFF@GOTPAGEOFF]
Lloh99:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #1
	bl	_jbt_reg_write_1
Lloh100:
	adrp	x8, _JBT_REG_CKV_1_2@GOTPAGE
Lloh101:
	ldr	x8, [x8, _JBT_REG_CKV_1_2@GOTPAGEOFF]
Lloh102:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #0
	bl	_jbt_reg_write_2
Lloh103:
	adrp	x8, _JBT_REG_OEV_TIMING@GOTPAGE
Lloh104:
	ldr	x8, [x8, _JBT_REG_OEV_TIMING@GOTPAGEOFF]
Lloh105:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #3342
	bl	_jbt_reg_write_2
Lloh106:
	adrp	x8, _JBT_REG_ASW_TIMING_1@GOTPAGE
Lloh107:
	ldr	x8, [x8, _JBT_REG_ASW_TIMING_1@GOTPAGEOFF]
Lloh108:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #4516
	bl	_jbt_reg_write_2
Lloh109:
	adrp	x8, _JBT_REG_ASW_TIMING_2@GOTPAGE
Lloh110:
	ldr	x8, [x8, _JBT_REG_ASW_TIMING_2@GOTPAGEOFF]
Lloh111:
	ldr	w1, [x8]
	add	x3, sp, #12
	mov	x0, x19
	mov	w2, #14
	bl	_jbt_reg_write_1
	ldr	w0, [sp, #12]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	ret
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_JBT_REG_POWER_ON_OFF,4,2       ; @JBT_REG_POWER_ON_OFF
	.comm	_JBT_REG_DISPLAY_MODE,4,2       ; @JBT_REG_DISPLAY_MODE
	.comm	_JBT_REG_QUAD_RATE,4,2          ; @JBT_REG_QUAD_RATE
	.comm	_JBT_REG_OUTPUT_CONTROL,4,2     ; @JBT_REG_OUTPUT_CONTROL
	.comm	_JBT_REG_SLEEP_OUT,4,2          ; @JBT_REG_SLEEP_OUT
	.comm	_JBT_REG_DISPLAY_MODE1,4,2      ; @JBT_REG_DISPLAY_MODE1
	.comm	_JBT_REG_DISPLAY_MODE2,4,2      ; @JBT_REG_DISPLAY_MODE2
	.comm	_JBT_REG_RGB_FORMAT,4,2         ; @JBT_REG_RGB_FORMAT
	.comm	_JBT_REG_DRIVE_SYSTEM,4,2       ; @JBT_REG_DRIVE_SYSTEM
	.comm	_JBT_REG_BOOSTER_OP,4,2         ; @JBT_REG_BOOSTER_OP
	.comm	_JBT_REG_BOOSTER_MODE,4,2       ; @JBT_REG_BOOSTER_MODE
	.comm	_JBT_REG_BOOSTER_FREQ,4,2       ; @JBT_REG_BOOSTER_FREQ
	.comm	_JBT_REG_OPAMP_SYSCLK,4,2       ; @JBT_REG_OPAMP_SYSCLK
	.comm	_JBT_REG_VSC_VOLTAGE,4,2        ; @JBT_REG_VSC_VOLTAGE
	.comm	_JBT_REG_VCOM_VOLTAGE,4,2       ; @JBT_REG_VCOM_VOLTAGE
	.comm	_JBT_REG_EXT_DISPL,4,2          ; @JBT_REG_EXT_DISPL
	.comm	_JBT_REG_DCCLK_DCEV,4,2         ; @JBT_REG_DCCLK_DCEV
	.comm	_JBT_REG_ASW_SLEW,4,2           ; @JBT_REG_ASW_SLEW
	.comm	_JBT_REG_DUMMY_DISPLAY,4,2      ; @JBT_REG_DUMMY_DISPLAY
	.comm	_JBT_REG_SLEEP_OUT_FR_A,4,2     ; @JBT_REG_SLEEP_OUT_FR_A
	.comm	_JBT_REG_SLEEP_OUT_FR_B,4,2     ; @JBT_REG_SLEEP_OUT_FR_B
	.comm	_JBT_REG_SLEEP_OUT_FR_C,4,2     ; @JBT_REG_SLEEP_OUT_FR_C
	.comm	_JBT_REG_SLEEP_IN_LCCNT_D,4,2   ; @JBT_REG_SLEEP_IN_LCCNT_D
	.comm	_JBT_REG_SLEEP_IN_LCCNT_E,4,2   ; @JBT_REG_SLEEP_IN_LCCNT_E
	.comm	_JBT_REG_SLEEP_IN_LCCNT_F,4,2   ; @JBT_REG_SLEEP_IN_LCCNT_F
	.comm	_JBT_REG_SLEEP_IN_LCCNT_G,4,2   ; @JBT_REG_SLEEP_IN_LCCNT_G
	.comm	_JBT_REG_GAMMA1_FINE_1,4,2      ; @JBT_REG_GAMMA1_FINE_1
	.comm	_JBT_REG_GAMMA1_FINE_2,4,2      ; @JBT_REG_GAMMA1_FINE_2
	.comm	_JBT_REG_GAMMA1_INCLINATION,4,2 ; @JBT_REG_GAMMA1_INCLINATION
	.comm	_JBT_REG_GAMMA1_BLUE_OFFSET,4,2 ; @JBT_REG_GAMMA1_BLUE_OFFSET
	.comm	_JBT_REG_HCLOCK_VGA,4,2         ; @JBT_REG_HCLOCK_VGA
	.comm	_JBT_REG_BLANK_CONTROL,4,2      ; @JBT_REG_BLANK_CONTROL
	.comm	_JBT_REG_BLANK_TH_TV,4,2        ; @JBT_REG_BLANK_TH_TV
	.comm	_JBT_REG_CKV_ON_OFF,4,2         ; @JBT_REG_CKV_ON_OFF
	.comm	_JBT_REG_CKV_1_2,4,2            ; @JBT_REG_CKV_1_2
	.comm	_JBT_REG_OEV_TIMING,4,2         ; @JBT_REG_OEV_TIMING
	.comm	_JBT_REG_ASW_TIMING_1,4,2       ; @JBT_REG_ASW_TIMING_1
	.comm	_JBT_REG_ASW_TIMING_2,4,2       ; @JBT_REG_ASW_TIMING_2
	.no_dead_strip	_td028ttec1_prepare
.subsections_via_symbols
