	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v9_0_init_gfx_power_gating
_gfx_v9_0_init_gfx_power_gating:        ## @gfx_v9_0_init_gfx_power_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_AMD_PG_SUPPORT_GFX_PG@GOTPCREL(%rip), %rax
	movq	_AMD_PG_SUPPORT_GFX_SMG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	_AMD_PG_SUPPORT_GFX_DMG@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	testl	%ecx, (%rdi)
	je	LBB0_1
## %bb.2:
	movq	%rdi, %r14
	movq	_GC@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	movq	_mmCP_RB_WPTR_POLL_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	callq	_RREG32
	movq	_CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movq	_CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$96, %ebx
	shll	%cl, %ebx
	andl	%eax, %edx
	orl	%edx, %ebx
	movl	(%r15), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_RLC_PG_DELAY__POWER_UP_DELAY__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$16, %eax
	shll	%cl, %eax
	movq	_RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$16, %edx
	shll	%cl, %edx
	movq	_RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$16, %esi
	shll	%cl, %esi
	orl	%eax, %edx
	movq	_RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$64, %ebx
	shll	%cl, %ebx
	orl	%esi, %ebx
	orl	%edx, %ebx
	movl	(%r15), %edi
	movq	_mmRLC_PG_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r15), %edi
	movq	_mmRLC_PG_DELAY_2@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	callq	_RREG32
	movq	_RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movq	_RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$4, %ebx
	shll	%cl, %ebx
	andl	%eax, %edx
	orl	%edx, %ebx
	movl	(%r15), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r15), %edi
	movq	_mmRLC_PG_DELAY_3@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	callq	_RREG32
	movq	_RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movq	_RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$255, %ebx
	shll	%cl, %ebx
	andl	%eax, %edx
	orl	%edx, %ebx
	movl	(%r15), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r15), %edi
	movq	_mmRLC_AUTO_PG_CTRL@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	callq	_RREG32
	movq	_RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movq	_RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$22000, %ebx                    ## imm = 0x55F0
	shll	%cl, %ebx
	andl	%eax, %edx
	orl	%edx, %ebx
	movl	(%r15), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	%r14, %rdi
	movl	$1, %esi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_pwr_10_0_gfxip_control_over_cgpg ## TAILCALL
LBB0_1:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_PG_SUPPORT_GFX_PG,4,2      ## @AMD_PG_SUPPORT_GFX_PG
	.comm	_AMD_PG_SUPPORT_GFX_SMG,4,2     ## @AMD_PG_SUPPORT_GFX_SMG
	.comm	_AMD_PG_SUPPORT_GFX_DMG,4,2     ## @AMD_PG_SUPPORT_GFX_DMG
	.comm	_GC,4,2                         ## @GC
	.comm	_mmCP_RB_WPTR_POLL_CNTL,4,2     ## @mmCP_RB_WPTR_POLL_CNTL
	.comm	_CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK,4,2 ## @CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK
	.comm	_CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT,4,2 ## @CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT
	.comm	_RLC_PG_DELAY__POWER_UP_DELAY__SHIFT,4,2 ## @RLC_PG_DELAY__POWER_UP_DELAY__SHIFT
	.comm	_RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT,4,2 ## @RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT
	.comm	_RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT,4,2 ## @RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT
	.comm	_RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT,4,2 ## @RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT
	.comm	_mmRLC_PG_DELAY,4,2             ## @mmRLC_PG_DELAY
	.comm	_mmRLC_PG_DELAY_2,4,2           ## @mmRLC_PG_DELAY_2
	.comm	_RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK,4,2 ## @RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK
	.comm	_RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT,4,2 ## @RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT
	.comm	_mmRLC_PG_DELAY_3,4,2           ## @mmRLC_PG_DELAY_3
	.comm	_RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK,4,2 ## @RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK
	.comm	_RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT,4,2 ## @RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT
	.comm	_mmRLC_AUTO_PG_CTRL,4,2         ## @mmRLC_AUTO_PG_CTRL
	.comm	_RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK,4,2 ## @RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK
	.comm	_RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT,4,2 ## @RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT
	.no_dead_strip	_gfx_v9_0_init_gfx_power_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v9_0_init_gfx_power_gating
_gfx_v9_0_init_gfx_power_gating:        ; @gfx_v9_0_init_gfx_power_gating
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _AMD_PG_SUPPORT_GFX_PG@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_PG_SUPPORT_GFX_PG@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
Lloh3:
	adrp	x10, _AMD_PG_SUPPORT_GFX_SMG@GOTPAGE
Lloh4:
	ldr	x10, [x10, _AMD_PG_SUPPORT_GFX_SMG@GOTPAGEOFF]
Lloh5:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh6:
	adrp	x10, _AMD_PG_SUPPORT_GFX_DMG@GOTPAGE
Lloh7:
	ldr	x10, [x10, _AMD_PG_SUPPORT_GFX_DMG@GOTPAGEOFF]
Lloh8:
	ldr	w10, [x10]
	orr	w9, w9, w10
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
	mov	x19, x0
Lloh9:
	adrp	x21, _GC@GOTPAGE
Lloh10:
	ldr	x21, [x21, _GC@GOTPAGEOFF]
	ldr	w0, [x21]
Lloh11:
	adrp	x22, _mmCP_RB_WPTR_POLL_CNTL@GOTPAGE
Lloh12:
	ldr	x22, [x22, _mmCP_RB_WPTR_POLL_CNTL@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	bl	_RREG32
Lloh13:
	adrp	x8, _CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK@GOTPAGE
Lloh14:
	ldr	x8, [x8, _CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh16:
	adrp	x9, _CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT@GOTPAGE
Lloh17:
	ldr	x9, [x9, _CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	mov	w10, #96
	lsl	w9, w10, w9
	orr	w20, w9, w8
	ldr	w0, [x21]
	ldr	w2, [x22]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x1, x20
	bl	_WREG32
Lloh19:
	adrp	x8, _RLC_PG_DELAY__POWER_UP_DELAY__SHIFT@GOTPAGE
Lloh20:
	ldr	x8, [x8, _RLC_PG_DELAY__POWER_UP_DELAY__SHIFT@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
	mov	w9, #16
	lsl	w8, w9, w8
Lloh22:
	adrp	x10, _RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT@GOTPAGE
Lloh23:
	ldr	x10, [x10, _RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT@GOTPAGEOFF]
Lloh24:
	ldr	w10, [x10]
	lsl	w10, w9, w10
	orr	w8, w10, w8
Lloh25:
	adrp	x10, _RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT@GOTPAGE
Lloh26:
	ldr	x10, [x10, _RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT@GOTPAGEOFF]
Lloh27:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w8, w8, w9
Lloh28:
	adrp	x9, _RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT@GOTPAGE
Lloh29:
	ldr	x9, [x9, _RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
	mov	w10, #64
	lsl	w9, w10, w9
	orr	w20, w8, w9
	ldr	w0, [x21]
Lloh31:
	adrp	x8, _mmRLC_PG_DELAY@GOTPAGE
Lloh32:
	ldr	x8, [x8, _mmRLC_PG_DELAY@GOTPAGEOFF]
Lloh33:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x1, x20
	bl	_WREG32
	ldr	w0, [x21]
Lloh34:
	adrp	x22, _mmRLC_PG_DELAY_2@GOTPAGE
Lloh35:
	ldr	x22, [x22, _mmRLC_PG_DELAY_2@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	bl	_RREG32
Lloh36:
	adrp	x8, _RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK@GOTPAGE
Lloh37:
	ldr	x8, [x8, _RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK@GOTPAGEOFF]
Lloh38:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh39:
	adrp	x9, _RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT@GOTPAGE
Lloh40:
	ldr	x9, [x9, _RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT@GOTPAGEOFF]
Lloh41:
	ldr	w9, [x9]
	mov	w10, #4
	lsl	w9, w10, w9
	orr	w20, w9, w8
	ldr	w0, [x21]
	ldr	w2, [x22]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x1, x20
	bl	_WREG32
	ldr	w0, [x21]
Lloh42:
	adrp	x22, _mmRLC_PG_DELAY_3@GOTPAGE
Lloh43:
	ldr	x22, [x22, _mmRLC_PG_DELAY_3@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	bl	_RREG32
Lloh44:
	adrp	x8, _RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK@GOTPAGE
Lloh45:
	ldr	x8, [x8, _RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK@GOTPAGEOFF]
Lloh46:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh47:
	adrp	x9, _RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT@GOTPAGE
Lloh48:
	ldr	x9, [x9, _RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT@GOTPAGEOFF]
Lloh49:
	ldr	w9, [x9]
	mov	w10, #255
	lsl	w9, w10, w9
	orr	w20, w9, w8
	ldr	w0, [x21]
	ldr	w2, [x22]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x1, x20
	bl	_WREG32
	ldr	w0, [x21]
Lloh50:
	adrp	x22, _mmRLC_AUTO_PG_CTRL@GOTPAGE
Lloh51:
	ldr	x22, [x22, _mmRLC_AUTO_PG_CTRL@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	bl	_RREG32
Lloh52:
	adrp	x8, _RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK@GOTPAGE
Lloh53:
	ldr	x8, [x8, _RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK@GOTPAGEOFF]
Lloh54:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh55:
	adrp	x9, _RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT@GOTPAGE
Lloh56:
	ldr	x9, [x9, _RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT@GOTPAGEOFF]
Lloh57:
	ldr	w9, [x9]
	mov	w10, #22000
	lsl	w9, w10, w9
	orr	w20, w9, w8
	ldr	w0, [x21]
	ldr	w2, [x22]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x1, x20
	bl	_WREG32
	mov	x0, x19
	mov	w1, #1
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_pwr_10_0_gfxip_control_over_cgpg
LBB0_2:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_PG_SUPPORT_GFX_PG,4,2      ; @AMD_PG_SUPPORT_GFX_PG
	.comm	_AMD_PG_SUPPORT_GFX_SMG,4,2     ; @AMD_PG_SUPPORT_GFX_SMG
	.comm	_AMD_PG_SUPPORT_GFX_DMG,4,2     ; @AMD_PG_SUPPORT_GFX_DMG
	.comm	_GC,4,2                         ; @GC
	.comm	_mmCP_RB_WPTR_POLL_CNTL,4,2     ; @mmCP_RB_WPTR_POLL_CNTL
	.comm	_CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK,4,2 ; @CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK
	.comm	_CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT,4,2 ; @CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT
	.comm	_RLC_PG_DELAY__POWER_UP_DELAY__SHIFT,4,2 ; @RLC_PG_DELAY__POWER_UP_DELAY__SHIFT
	.comm	_RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT,4,2 ; @RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT
	.comm	_RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT,4,2 ; @RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT
	.comm	_RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT,4,2 ; @RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT
	.comm	_mmRLC_PG_DELAY,4,2             ; @mmRLC_PG_DELAY
	.comm	_mmRLC_PG_DELAY_2,4,2           ; @mmRLC_PG_DELAY_2
	.comm	_RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK,4,2 ; @RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK
	.comm	_RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT,4,2 ; @RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT
	.comm	_mmRLC_PG_DELAY_3,4,2           ; @mmRLC_PG_DELAY_3
	.comm	_RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK,4,2 ; @RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK
	.comm	_RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT,4,2 ; @RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT
	.comm	_mmRLC_AUTO_PG_CTRL,4,2         ; @mmRLC_AUTO_PG_CTRL
	.comm	_RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK,4,2 ; @RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK
	.comm	_RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT,4,2 ; @RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT
	.no_dead_strip	_gfx_v9_0_init_gfx_power_gating
.subsections_via_symbols
