	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rv770_populate_smc_initial_state
_rv770_populate_smc_initial_state:      ## @rv770_populate_smc_initial_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r13
	movq	%rdi, %r12
	movq	%rsi, %rdi
	callq	_rv770_get_ps
	movq	%rax, %r15
	movq	%r12, %rdi
	callq	_rv770_get_pi
	movq	%rax, %r14
	movl	40(%rax), %edi
	callq	_cpu_to_be32
	movq	8(%r13), %rcx
	movq	%rax, 160(%rcx)
	movl	44(%r14), %edi
	callq	_cpu_to_be32
	movq	8(%r13), %rcx
	movq	%rax, 152(%rcx)
	movl	48(%r14), %edi
	callq	_cpu_to_be32
	movq	8(%r13), %rcx
	movq	%rax, 144(%rcx)
	movl	52(%r14), %edi
	callq	_cpu_to_be32
	movq	8(%r13), %rcx
	movq	%rax, 136(%rcx)
	movl	56(%r14), %edi
	callq	_cpu_to_be32
	movq	8(%r13), %rcx
	movq	%rax, 128(%rcx)
	movl	60(%r14), %edi
	callq	_cpu_to_be32
	movq	8(%r13), %rcx
	movq	%rax, 120(%rcx)
	movl	64(%r14), %edi
	callq	_cpu_to_be32
	movq	8(%r13), %rcx
	movq	%rax, 112(%rcx)
	movl	68(%r14), %edi
	callq	_cpu_to_be32
	movq	8(%r13), %rcx
	movq	%rax, 104(%rcx)
	movl	(%r15), %edi
	callq	_cpu_to_be32
	movq	8(%r13), %rcx
	movq	%rax, 96(%rcx)
	movl	72(%r14), %edi
	callq	_cpu_to_be32
	movq	8(%r13), %rcx
	movq	%rax, 88(%rcx)
	movl	76(%r14), %edi
	callq	_cpu_to_be32
	movq	8(%r13), %rcx
	movq	%rax, 80(%rcx)
	movl	80(%r14), %edi
	callq	_cpu_to_be32
	movq	8(%r13), %rcx
	movq	%rax, 72(%rcx)
	movl	84(%r14), %edi
	callq	_cpu_to_be32
	movq	8(%r13), %rcx
	movq	%rax, 64(%rcx)
	movl	88(%r14), %edi
	callq	_cpu_to_be32
	movq	8(%r13), %rcx
	movq	%rax, 56(%rcx)
	movl	4(%r15), %edi
	callq	_cpu_to_be32
	movq	8(%r13), %rcx
	movq	%rax, 48(%rcx)
	movq	_MC_CG_ARB_FREQ_F0@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 44(%rcx)
	movq	%r12, %rdi
	movq	%r15, %rsi
	callq	_rv770_get_seq_value
	movq	8(%r13), %rdx
	movl	%eax, 40(%rdx)
	movl	12(%r15), %esi
	addq	$36, %rdx
	movq	%r12, %rdi
	callq	_rv770_populate_vddc_value
	movq	8(%r13), %rsi
	addq	$32, %rsi
	movq	%r12, %rdi
	callq	_rv770_populate_initial_mvdd_value
	movl	$65535, %edi                    ## imm = 0xFFFF
	callq	_CG_R
	movl	%eax, %ebx
	xorl	%edi, %edi
	callq	_CG_L
	orl	%eax, %ebx
	movl	%ebx, %edi
	callq	_cpu_to_be32
	movq	8(%r13), %rcx
	movq	%rax, 24(%rcx)
	movl	(%r14), %edi
	callq	_cpu_to_be32
	movq	8(%r13), %rcx
	movq	%rax, 16(%rcx)
	xorl	%eax, %eax
	cmpq	$0, 32(%r14)
	setne	%al
	movl	%eax, (%rcx)
	movq	_ATOM_PPLIB_R600_FLAGS_PCIEGEN2@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	xorl	%edx, %edx
	andl	8(%r15), %eax
	setne	%dl
	movl	%edx, 4(%rcx)
	movq	(%r12), %rax
	movq	_CHIP_RV740@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rax
	jne	LBB0_6
## %bb.1:
	cmpq	$0, 24(%r14)
	je	LBB0_6
## %bb.2:
	leaq	8(%r13), %rbx
	movslq	(%r15), %rdi
	cmpq	%rdi, 8(%r14)
	jge	LBB0_3
## %bb.4:
	movl	$0, 8(%rcx)
	jmp	LBB0_5
LBB0_3:
	callq	_rv740_get_mclk_frequency_ratio
	orl	$16, %eax
	movq	(%rbx), %rcx
	movl	%eax, 8(%rcx)
	movslq	(%r15), %rdi
LBB0_5:
	movq	_SMC_MC_EDC_RD_FLAG@GOTPCREL(%rip), %rax
	movq	_SMC_MC_EDC_WR_FLAG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	xorl	%eax, %eax
	cmpq	%rdi, 16(%r14)
	cmovlel	%ecx, %eax
	movq	(%rbx), %rcx
	movl	%eax, 12(%rcx)
LBB0_6:
	movq	8(%r13), %rsi
	leaq	168(%rsi), %rdi
	movl	$168, %edx
	callq	_memcpy
	movq	8(%r13), %rsi
	leaq	336(%rsi), %rdi
	movl	$168, %edx
	callq	_memcpy
	movq	_PPSMC_SWSTATE_FLAG_DC@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r13)
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MC_CG_ARB_FREQ_F0,4,2          ## @MC_CG_ARB_FREQ_F0
	.comm	_ATOM_PPLIB_R600_FLAGS_PCIEGEN2,4,2 ## @ATOM_PPLIB_R600_FLAGS_PCIEGEN2
	.comm	_CHIP_RV740,8,3                 ## @CHIP_RV740
	.comm	_SMC_MC_EDC_RD_FLAG,4,2         ## @SMC_MC_EDC_RD_FLAG
	.comm	_SMC_MC_EDC_WR_FLAG,4,2         ## @SMC_MC_EDC_WR_FLAG
	.comm	_PPSMC_SWSTATE_FLAG_DC,4,2      ## @PPSMC_SWSTATE_FLAG_DC
	.no_dead_strip	_rv770_populate_smc_initial_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rv770_populate_smc_initial_state
_rv770_populate_smc_initial_state:      ; @rv770_populate_smc_initial_state
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x2
	mov	x22, x0
	mov	x0, x1
	bl	_rv770_get_ps
	mov	x21, x0
	mov	x0, x22
	bl	_rv770_get_pi
	mov	x20, x0
	ldr	w0, [x0, #40]
	bl	_cpu_to_be32
	mov	x24, x19
	ldr	x8, [x24, #8]!
	str	x0, [x8, #160]
	ldr	w0, [x20, #44]
	bl	_cpu_to_be32
	ldr	x8, [x24]
	str	x0, [x8, #152]
	ldr	w0, [x20, #48]
	bl	_cpu_to_be32
	ldr	x8, [x24]
	str	x0, [x8, #144]
	ldr	w0, [x20, #52]
	bl	_cpu_to_be32
	ldr	x8, [x24]
	str	x0, [x8, #136]
	ldr	w0, [x20, #56]
	bl	_cpu_to_be32
	ldr	x8, [x24]
	str	x0, [x8, #128]
	ldr	w0, [x20, #60]
	bl	_cpu_to_be32
	ldr	x8, [x24]
	str	x0, [x8, #120]
	ldr	w0, [x20, #64]
	bl	_cpu_to_be32
	ldr	x8, [x24]
	str	x0, [x8, #112]
	ldr	w0, [x20, #68]
	bl	_cpu_to_be32
	ldr	x8, [x24]
	str	x0, [x8, #104]
	ldr	w0, [x21]
	bl	_cpu_to_be32
	ldr	x8, [x24]
	str	x0, [x8, #96]
	ldr	w0, [x20, #72]
	bl	_cpu_to_be32
	ldr	x8, [x24]
	str	x0, [x8, #88]
	ldr	w0, [x20, #76]
	bl	_cpu_to_be32
	ldr	x8, [x24]
	str	x0, [x8, #80]
	ldr	w0, [x20, #80]
	bl	_cpu_to_be32
	ldr	x8, [x24]
	str	x0, [x8, #72]
	ldr	w0, [x20, #84]
	bl	_cpu_to_be32
	ldr	x8, [x24]
	str	x0, [x8, #64]
	ldr	w0, [x20, #88]
	bl	_cpu_to_be32
	ldr	x8, [x24]
	str	x0, [x8, #56]
	ldr	w0, [x21, #4]
	bl	_cpu_to_be32
	ldr	x8, [x24]
	str	x0, [x8, #48]
Lloh0:
	adrp	x9, _MC_CG_ARB_FREQ_F0@GOTPAGE
Lloh1:
	ldr	x9, [x9, _MC_CG_ARB_FREQ_F0@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	str	w9, [x8, #44]
	mov	x0, x22
	mov	x1, x21
	bl	_rv770_get_seq_value
	ldr	x8, [x24]
	str	w0, [x8, #40]
	ldr	w1, [x21, #12]
	add	x2, x8, #36
	mov	x0, x22
	bl	_rv770_populate_vddc_value
	ldr	x8, [x24]
	add	x1, x8, #32
	mov	x0, x22
	bl	_rv770_populate_initial_mvdd_value
	mov	w0, #65535
	bl	_CG_R
	mov	x23, x0
	mov	w0, #0
	bl	_CG_L
	orr	w0, w0, w23
	bl	_cpu_to_be32
	ldr	x8, [x24]
	str	x0, [x8, #24]
	ldr	w0, [x20]
	bl	_cpu_to_be32
	ldr	x8, [x24]
	str	x0, [x8, #16]
	ldr	x9, [x20, #32]
	cmp	x9, #0
	cset	w9, ne
	str	w9, [x8]
	ldr	w9, [x21, #8]
Lloh3:
	adrp	x10, _ATOM_PPLIB_R600_FLAGS_PCIEGEN2@GOTPAGE
Lloh4:
	ldr	x10, [x10, _ATOM_PPLIB_R600_FLAGS_PCIEGEN2@GOTPAGEOFF]
Lloh5:
	ldr	w10, [x10]
	tst	w10, w9
	cset	w9, ne
	str	w9, [x8, #4]
	ldr	x9, [x22]
Lloh6:
	adrp	x10, _CHIP_RV740@GOTPAGE
Lloh7:
	ldr	x10, [x10, _CHIP_RV740@GOTPAGEOFF]
Lloh8:
	ldr	x10, [x10]
	cmp	x9, x10
	b.ne	LBB0_6
; %bb.1:
	ldr	x9, [x20, #24]
	cbz	x9, LBB0_6
; %bb.2:
	ldrsw	x0, [x21]
	ldr	x9, [x20, #8]
	cmp	x9, x0
	b.ge	LBB0_4
; %bb.3:
	str	wzr, [x8, #8]
	b	LBB0_5
LBB0_4:
	bl	_rv740_get_mclk_frequency_ratio
	orr	w8, w0, #0x10
	ldr	x9, [x24]
	str	w8, [x9, #8]
	ldrsw	x0, [x21]
LBB0_5:
	ldr	x8, [x20, #16]
Lloh9:
	adrp	x9, _SMC_MC_EDC_RD_FLAG@GOTPAGE
Lloh10:
	ldr	x9, [x9, _SMC_MC_EDC_RD_FLAG@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
Lloh12:
	adrp	x10, _SMC_MC_EDC_WR_FLAG@GOTPAGE
Lloh13:
	ldr	x10, [x10, _SMC_MC_EDC_WR_FLAG@GOTPAGEOFF]
Lloh14:
	ldr	w10, [x10]
	orr	w9, w10, w9
	cmp	x8, x0
	csel	w8, wzr, w9, gt
	ldr	x9, [x24]
	str	w8, [x9, #12]
LBB0_6:
	ldr	x8, [x19, #8]
	add	x9, x8, #168
	ldp	q0, q1, [x8, #128]
	stp	q0, q1, [x9, #128]
	ldp	q1, q0, [x8, #32]
	stur	q0, [x8, #216]
	ldp	q0, q2, [x8, #64]
	stur	q0, [x8, #232]
	stur	q2, [x8, #248]
	ldp	q2, q0, [x8, #96]
	stp	q2, q0, [x9, #96]
	ldp	q0, q2, [x8]
	stur	q0, [x8, #168]
	ldr	x10, [x8, #160]
	str	x10, [x9, #160]
	stur	q2, [x8, #184]
	stur	q1, [x8, #200]
	ldr	x8, [x19, #8]
	ldp	q0, q1, [x8]
	stp	q0, q1, [x8, #336]
	ldp	q1, q0, [x8, #64]
	stp	q1, q0, [x8, #400]
	ldp	q0, q1, [x8, #32]
	stp	q0, q1, [x8, #368]
	ldr	x9, [x8, #160]
	str	x9, [x8, #496]
	ldp	q1, q0, [x8, #128]
	stp	q1, q0, [x8, #464]
	ldp	q0, q1, [x8, #96]
Lloh15:
	adrp	x9, _PPSMC_SWSTATE_FLAG_DC@GOTPAGE
Lloh16:
	ldr	x9, [x9, _PPSMC_SWSTATE_FLAG_DC@GOTPAGEOFF]
	stp	q0, q1, [x8, #432]
Lloh17:
	ldr	w8, [x9]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
	mov	w0, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.cfi_endproc
                                        ; -- End function
	.comm	_MC_CG_ARB_FREQ_F0,4,2          ; @MC_CG_ARB_FREQ_F0
	.comm	_ATOM_PPLIB_R600_FLAGS_PCIEGEN2,4,2 ; @ATOM_PPLIB_R600_FLAGS_PCIEGEN2
	.comm	_CHIP_RV740,8,3                 ; @CHIP_RV740
	.comm	_SMC_MC_EDC_RD_FLAG,4,2         ; @SMC_MC_EDC_RD_FLAG
	.comm	_SMC_MC_EDC_WR_FLAG,4,2         ; @SMC_MC_EDC_WR_FLAG
	.comm	_PPSMC_SWSTATE_FLAG_DC,4,2      ; @PPSMC_SWSTATE_FLAG_DC
	.no_dead_strip	_rv770_populate_smc_initial_state
.subsections_via_symbols
