	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_vcn_sw_init             ## -- Begin function amdgpu_vcn_sw_init
	.p2align	4, 0x90
_amdgpu_vcn_sw_init:                    ## @amdgpu_vcn_sw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	addq	$64, %rdi
	movq	_amdgpu_vcn_idle_work_handler@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_DELAYED_WORK
	movl	(%r15), %eax
	addl	$-128, %eax
	cmpl	$5, %eax
	ja	LBB0_6
## %bb.1:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_2:
	movq	_FIRMWARE_RENOIR@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_6:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r12d, %r12d
	subl	(%rax), %r12d
	jmp	LBB0_18
LBB0_7:
	cmpl	$8, 4(%r15)
	jl	LBB0_21
## %bb.8:
	movq	_FIRMWARE_RAVEN2@GOTPCREL(%rip), %rax
	jmp	LBB0_13
LBB0_9:
	movq	_FIRMWARE_NAVI14@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_10:
	movq	_FIRMWARE_NAVI12@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_11:
	movq	_FIRMWARE_NAVI10@GOTPCREL(%rip), %rax
LBB0_3:
	movq	(%rax), %r14
	movq	72(%r15), %rax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_14
## %bb.4:
	movq	_AMD_PG_SUPPORT_VCN_DPG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 8(%r15)
	je	LBB0_14
## %bb.5:
	movl	$1, 16(%r15)
	jmp	LBB0_14
LBB0_12:
	movq	_FIRMWARE_ARCTURUS@GOTPCREL(%rip), %rax
LBB0_13:
	movq	(%rax), %r14
LBB0_14:
	leaq	56(%r15), %rbx
	movl	12(%r15), %edx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	_request_firmware
	testl	%eax, %eax
	je	LBB0_16
## %bb.15:
	movl	%eax, %r12d
	movl	12(%r15), %edi
	leaq	L_.str(%rip), %rsi
	movq	%r14, %rdx
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_18
LBB0_16:
	movq	(%rbx), %rdi
	callq	_amdgpu_ucode_validate
	testl	%eax, %eax
	je	LBB0_19
## %bb.17:
	movl	%eax, %r12d
	movl	12(%r15), %edi
	leaq	L_.str.1(%rip), %rsi
	movq	%r14, %rdx
	xorl	%eax, %eax
	callq	_dev_err
	movq	56(%r15), %rdi
	callq	_release_firmware
	movq	$0, 56(%r15)
LBB0_18:
	movl	%r12d, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_19:
	movq	56(%r15), %rax
	movq	(%rax), %r12
	movl	4(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, 20(%r15)
	movl	4(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, %ebx
	shrl	$20, %ebx
	movl	4(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, %r14d
	andb	$15, %bl
	je	LBB0_23
## %bb.20:
	andl	$4095, %r14d                    ## imm = 0xFFF
	movl	4(%r12), %edi
	callq	_le32_to_cpu
	shrl	$12, %eax
	movzbl	%al, %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movzbl	%bl, %r13d
	movl	4(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, %ebx
	shrl	$24, %ebx
	andl	$15, %ebx
	movl	4(%r12), %edi
	callq	_le32_to_cpu
	shrl	$28, %eax
	leaq	L_.str.2(%rip), %rdi
	movl	%r13d, %esi
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	movl	%ebx, %ecx
	movl	%eax, %r8d
	movl	%r14d, %r9d
	xorl	%eax, %eax
	callq	_DRM_INFO
	jmp	LBB0_24
LBB0_21:
	movq	80(%r15), %rax
	cmpl	$5592, (%rax)                   ## imm = 0x15D8
	jne	LBB0_35
## %bb.22:
	movq	_FIRMWARE_PICASSO@GOTPCREL(%rip), %rax
	jmp	LBB0_13
LBB0_23:
	movzbl	%r14b, %r14d
	movl	4(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, %ebx
	shrl	$24, %ebx
	movl	4(%r12), %edi
	callq	_le32_to_cpu
	movzbl	%ah, %edx
	leaq	L_.str.3(%rip), %rdi
	movl	%ebx, %esi
	movl	%r14d, %ecx
	xorl	%eax, %eax
	callq	_DRM_INFO
LBB0_24:
	movq	_AMDGPU_VCN_STACK_SIZE@GOTPCREL(%rip), %rax
	movq	_AMDGPU_VCN_CONTEXT_SIZE@GOTPCREL(%rip), %rcx
	movq	(%rcx), %r14
	addq	(%rax), %r14
	movq	72(%r15), %rax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_26
## %bb.25:
	movl	(%r12), %edi
	callq	_le32_to_cpu
                                        ## kill: def $eax killed $eax def $rax
	leal	8(%rax), %edi
	callq	_AMDGPU_GPU_PAGE_ALIGN
	addq	%rax, %r14
LBB0_26:
	movl	24(%r15), %eax
	testl	%eax, %eax
	jle	LBB0_32
## %bb.27:
	movl	$8, %r13d
	xorl	%ebx, %ebx
	jmp	LBB0_29
	.p2align	4, 0x90
LBB0_28:                                ##   in Loop: Header=BB0_29 Depth=1
	incq	%rbx
	movslq	%eax, %rcx
	addq	$12, %r13
	cmpq	%rcx, %rbx
	jge	LBB0_32
LBB0_29:                                ## =>This Inner Loop Header: Depth=1
	movl	28(%r15), %ecx
	btl	%ebx, %ecx
	jb	LBB0_28
## %bb.30:                              ##   in Loop: Header=BB0_29 Depth=1
	movq	_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_AMDGPU_GEM_DOMAIN_VRAM@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	48(%r15), %rax
	leaq	(%rax,%r13), %r8
	leaq	-4(%rax,%r13), %r9
	leaq	-8(%rax,%r13), %rax
	movq	%rax, (%rsp)
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_amdgpu_bo_create_kernel
	testl	%eax, %eax
	jne	LBB0_36
## %bb.31:                              ##   in Loop: Header=BB0_29 Depth=1
	movl	24(%r15), %eax
	jmp	LBB0_28
LBB0_32:
	xorl	%r12d, %r12d
	cmpl	$0, 16(%r15)
	je	LBB0_18
## %bb.33:
	movq	_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_AMDGPU_GEM_DOMAIN_VRAM@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	leaq	40(%r15), %r8
	leaq	36(%r15), %r9
	leaq	32(%r15), %rax
	movq	%rax, (%rsp)
	movq	%r15, %rdi
	movl	$512, %esi                      ## imm = 0x200
	callq	_amdgpu_bo_create_kernel
	testl	%eax, %eax
	je	LBB0_18
## %bb.34:
	movl	%eax, %r14d
	movl	12(%r15), %edi
	leaq	L_.str.5(%rip), %rsi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_dev_err
	movl	%r14d, %r12d
	jmp	LBB0_18
LBB0_35:
	movq	_FIRMWARE_RAVEN@GOTPCREL(%rip), %rax
	jmp	LBB0_13
LBB0_36:
	movl	%eax, %r12d
	movl	12(%r15), %edi
	leaq	L_.str.4(%rip), %rsi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_18
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_2, LBB0_2-LJTI0_0
.set L0_0_set_7, LBB0_7-LJTI0_0
.set L0_0_set_9, LBB0_9-LJTI0_0
.set L0_0_set_10, LBB0_10-LJTI0_0
.set L0_0_set_11, LBB0_11-LJTI0_0
.set L0_0_set_12, LBB0_12-LJTI0_0
LJTI0_0:
	.long	L0_0_set_2
	.long	L0_0_set_7
	.long	L0_0_set_9
	.long	L0_0_set_10
	.long	L0_0_set_11
	.long	L0_0_set_12
	.end_data_region
                                        ## -- End function
	.comm	_amdgpu_vcn_idle_work_handler,4,2 ## @amdgpu_vcn_idle_work_handler
	.comm	_FIRMWARE_RAVEN2,8,3            ## @FIRMWARE_RAVEN2
	.comm	_FIRMWARE_PICASSO,8,3           ## @FIRMWARE_PICASSO
	.comm	_FIRMWARE_RAVEN,8,3             ## @FIRMWARE_RAVEN
	.comm	_FIRMWARE_ARCTURUS,8,3          ## @FIRMWARE_ARCTURUS
	.comm	_FIRMWARE_RENOIR,8,3            ## @FIRMWARE_RENOIR
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_AMD_PG_SUPPORT_VCN_DPG,4,2     ## @AMD_PG_SUPPORT_VCN_DPG
	.comm	_FIRMWARE_NAVI10,8,3            ## @FIRMWARE_NAVI10
	.comm	_FIRMWARE_NAVI14,8,3            ## @FIRMWARE_NAVI14
	.comm	_FIRMWARE_NAVI12,8,3            ## @FIRMWARE_NAVI12
	.comm	_EINVAL,4,2                     ## @EINVAL
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"amdgpu_vcn: Can't load firmware \"%s\"\n"

L_.str.1:                               ## @.str.1
	.asciz	"amdgpu_vcn: Can't validate firmware \"%s\"\n"

L_.str.2:                               ## @.str.2
	.asciz	"Found VCN firmware Version ENC: %hu.%hu DEC: %hu VEP: %hu Revision: %hu\n"

L_.str.3:                               ## @.str.3
	.asciz	"Found VCN firmware Version: %hu.%hu Family ID: %hu\n"

	.comm	_AMDGPU_VCN_STACK_SIZE,8,3      ## @AMDGPU_VCN_STACK_SIZE
	.comm	_AMDGPU_VCN_CONTEXT_SIZE,8,3    ## @AMDGPU_VCN_CONTEXT_SIZE
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
	.comm	_AMDGPU_GEM_DOMAIN_VRAM,4,2     ## @AMDGPU_GEM_DOMAIN_VRAM
L_.str.4:                               ## @.str.4
	.asciz	"(%d) failed to allocate vcn bo\n"

L_.str.5:                               ## @.str.5
	.asciz	"(%d) failed to allocate DPG bo\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_vcn_sw_init             ; -- Begin function amdgpu_vcn_sw_init
	.p2align	2
_amdgpu_vcn_sw_init:                    ; @amdgpu_vcn_sw_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	add	x0, x0, #64
Lloh0:
	adrp	x8, _amdgpu_vcn_idle_work_handler@GOTPAGE
Lloh1:
	ldr	x8, [x8, _amdgpu_vcn_idle_work_handler@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	bl	_INIT_DELAYED_WORK
	ldr	w8, [x19]
	sub	w8, w8, #128
	cmp	w8, #5
	b.hi	LBB0_3
; %bb.1:
Lloh3:
	adrp	x9, lJTI0_0@PAGE
Lloh4:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_2
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_2:
Lloh5:
	adrp	x8, _FIRMWARE_RENOIR@GOTPAGE
Lloh6:
	ldr	x8, [x8, _FIRMWARE_RENOIR@GOTPAGEOFF]
	b	LBB0_9
LBB0_3:
Lloh7:
	adrp	x8, _EINVAL@GOTPAGE
Lloh8:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	neg	w21, w8
	b	LBB0_18
LBB0_4:
	ldr	w8, [x19, #4]
	cmp	w8, #8
	b.lt	LBB0_21
; %bb.5:
Lloh10:
	adrp	x8, _FIRMWARE_RAVEN2@GOTPAGE
Lloh11:
	ldr	x8, [x8, _FIRMWARE_RAVEN2@GOTPAGEOFF]
	b	LBB0_13
LBB0_6:
Lloh12:
	adrp	x8, _FIRMWARE_NAVI14@GOTPAGE
Lloh13:
	ldr	x8, [x8, _FIRMWARE_NAVI14@GOTPAGEOFF]
	b	LBB0_9
LBB0_7:
Lloh14:
	adrp	x8, _FIRMWARE_NAVI12@GOTPAGE
Lloh15:
	ldr	x8, [x8, _FIRMWARE_NAVI12@GOTPAGEOFF]
	b	LBB0_9
LBB0_8:
Lloh16:
	adrp	x8, _FIRMWARE_NAVI10@GOTPAGE
Lloh17:
	ldr	x8, [x8, _FIRMWARE_NAVI10@GOTPAGEOFF]
LBB0_9:
	ldr	x20, [x8]
	ldr	x8, [x19, #72]
Lloh18:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh19:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh20:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_14
; %bb.10:
	ldr	w8, [x19, #8]
Lloh21:
	adrp	x9, _AMD_PG_SUPPORT_VCN_DPG@GOTPAGE
Lloh22:
	ldr	x9, [x9, _AMD_PG_SUPPORT_VCN_DPG@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_14
; %bb.11:
	mov	w8, #1
	str	w8, [x19, #16]
	b	LBB0_14
LBB0_12:
Lloh24:
	adrp	x8, _FIRMWARE_ARCTURUS@GOTPAGE
Lloh25:
	ldr	x8, [x8, _FIRMWARE_ARCTURUS@GOTPAGEOFF]
LBB0_13:
	ldr	x20, [x8]
LBB0_14:
	add	x22, x19, #56
	ldr	w2, [x19, #12]
	mov	x0, x22
	mov	x1, x20
	bl	_request_firmware
	cbz	w0, LBB0_16
; %bb.15:
	mov	x21, x0
	ldr	w0, [x19, #12]
	str	x20, [sp]
Lloh26:
	adrp	x1, l_.str@PAGE
Lloh27:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
	b	LBB0_18
LBB0_16:
	ldr	x0, [x22]
	bl	_amdgpu_ucode_validate
	cbz	w0, LBB0_19
; %bb.17:
	mov	x21, x0
	ldr	w0, [x19, #12]
	str	x20, [sp]
Lloh28:
	adrp	x1, l_.str.1@PAGE
Lloh29:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_err
	ldr	x0, [x19, #56]
	bl	_release_firmware
	str	xzr, [x19, #56]
LBB0_18:
	mov	x0, x21
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_19:
	ldr	x8, [x19, #56]
	ldr	x23, [x8]
	ldr	w0, [x23, #4]
	bl	_le32_to_cpu
	str	w0, [x19, #20]
	ldr	w0, [x23, #4]
	bl	_le32_to_cpu
	ubfx	w20, w0, #20, #4
	ldr	w0, [x23, #4]
	bl	_le32_to_cpu
	cbz	w20, LBB0_23
; %bb.20:
	and	w24, w0, #0xfff
	ldr	w0, [x23, #4]
	bl	_le32_to_cpu
	ubfx	w21, w0, #12, #8
	ldr	w0, [x23, #4]
	bl	_le32_to_cpu
	ubfx	w22, w0, #24, #4
	ldr	w0, [x23, #4]
	bl	_le32_to_cpu
	lsr	w8, w0, #28
	stp	x8, x24, [sp]
Lloh30:
	adrp	x0, l_.str.2@PAGE
Lloh31:
	add	x0, x0, l_.str.2@PAGEOFF
	mov	x1, x20
	mov	x2, x21
	mov	x3, x22
	b	LBB0_24
LBB0_21:
	ldr	x8, [x19, #80]
	ldr	w8, [x8]
	mov	w9, #5592
	cmp	w8, w9
	b.ne	LBB0_36
; %bb.22:
Lloh32:
	adrp	x8, _FIRMWARE_PICASSO@GOTPAGE
Lloh33:
	ldr	x8, [x8, _FIRMWARE_PICASSO@GOTPAGEOFF]
	b	LBB0_13
LBB0_23:
	and	w20, w0, #0xff
	ldr	w0, [x23, #4]
	bl	_le32_to_cpu
	lsr	w21, w0, #24
	ldr	w0, [x23, #4]
	bl	_le32_to_cpu
	ubfx	w2, w0, #8, #8
Lloh34:
	adrp	x0, l_.str.3@PAGE
Lloh35:
	add	x0, x0, l_.str.3@PAGEOFF
	mov	x1, x21
	mov	x3, x20
LBB0_24:
	bl	_DRM_INFO
Lloh36:
	adrp	x8, _AMDGPU_VCN_STACK_SIZE@GOTPAGE
Lloh37:
	ldr	x8, [x8, _AMDGPU_VCN_STACK_SIZE@GOTPAGEOFF]
Lloh38:
	ldr	x8, [x8]
Lloh39:
	adrp	x9, _AMDGPU_VCN_CONTEXT_SIZE@GOTPAGE
Lloh40:
	ldr	x9, [x9, _AMDGPU_VCN_CONTEXT_SIZE@GOTPAGEOFF]
Lloh41:
	ldr	x9, [x9]
	add	x20, x9, x8
	ldr	x8, [x19, #72]
Lloh42:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh43:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh44:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_26
; %bb.25:
	ldr	w0, [x23]
	bl	_le32_to_cpu
	add	w0, w0, #8
	bl	_AMDGPU_GPU_PAGE_ALIGN
	add	x20, x0, x20
LBB0_26:
	ldr	w8, [x19, #24]
Lloh45:
	adrp	x22, _PAGE_SIZE@GOTPAGE
Lloh46:
	ldr	x22, [x22, _PAGE_SIZE@GOTPAGEOFF]
Lloh47:
	adrp	x23, _AMDGPU_GEM_DOMAIN_VRAM@GOTPAGE
Lloh48:
	ldr	x23, [x23, _AMDGPU_GEM_DOMAIN_VRAM@GOTPAGEOFF]
	cmp	w8, #1
	b.lt	LBB0_32
; %bb.27:
	mov	x24, #0
	mov	w25, #8
	b	LBB0_29
LBB0_28:                                ;   in Loop: Header=BB0_29 Depth=1
	add	x24, x24, #1
	add	x25, x25, #12
	cmp	x24, w8, sxtw
	b.ge	LBB0_32
LBB0_29:                                ; =>This Inner Loop Header: Depth=1
	ldr	w9, [x19, #28]
	lsr	w9, w9, w24
	tbnz	w9, #0, LBB0_28
; %bb.30:                               ;   in Loop: Header=BB0_29 Depth=1
	ldr	w2, [x22]
	ldr	w3, [x23]
	ldr	x8, [x19, #48]
	add	x4, x8, x25
	sub	x5, x4, #4
	sub	x6, x4, #8
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_bo_create_kernel
	cbnz	w0, LBB0_37
; %bb.31:                               ;   in Loop: Header=BB0_29 Depth=1
	ldr	w8, [x19, #24]
	b	LBB0_28
LBB0_32:
	ldr	w8, [x19, #16]
	cbz	w8, LBB0_35
; %bb.33:
	ldr	w2, [x22]
	ldr	w3, [x23]
	add	x4, x19, #40
	add	x5, x19, #36
	add	x6, x19, #32
	mov	x0, x19
	mov	w1, #512
	bl	_amdgpu_bo_create_kernel
	mov	x21, x0
	cbz	w0, LBB0_18
; %bb.34:
	ldr	w0, [x19, #12]
	str	x21, [sp]
Lloh49:
	adrp	x1, l_.str.5@PAGE
Lloh50:
	add	x1, x1, l_.str.5@PAGEOFF
	bl	_dev_err
                                        ; kill: def $w21 killed $w21 killed $x21 def $x21
	b	LBB0_18
LBB0_35:
	mov	w21, #0
	b	LBB0_18
LBB0_36:
Lloh51:
	adrp	x8, _FIRMWARE_RAVEN@GOTPAGE
Lloh52:
	ldr	x8, [x8, _FIRMWARE_RAVEN@GOTPAGEOFF]
	b	LBB0_13
LBB0_37:
	mov	x21, x0
	ldr	w0, [x19, #12]
	str	x21, [sp]
Lloh53:
	adrp	x1, l_.str.4@PAGE
Lloh54:
	add	x1, x1, l_.str.4@PAGEOFF
	bl	_dev_err
	b	LBB0_18
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpAdd	Lloh26, Lloh27
	.loh AdrpAdd	Lloh28, Lloh29
	.loh AdrpAdd	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpAdd	Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpAdd	Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh51, Lloh52
	.loh AdrpAdd	Lloh53, Lloh54
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_6-LBB0_2)>>2
	.byte	(LBB0_7-LBB0_2)>>2
	.byte	(LBB0_8-LBB0_2)>>2
	.byte	(LBB0_12-LBB0_2)>>2
                                        ; -- End function
	.comm	_amdgpu_vcn_idle_work_handler,4,2 ; @amdgpu_vcn_idle_work_handler
	.comm	_FIRMWARE_RAVEN2,8,3            ; @FIRMWARE_RAVEN2
	.comm	_FIRMWARE_PICASSO,8,3           ; @FIRMWARE_PICASSO
	.comm	_FIRMWARE_RAVEN,8,3             ; @FIRMWARE_RAVEN
	.comm	_FIRMWARE_ARCTURUS,8,3          ; @FIRMWARE_ARCTURUS
	.comm	_FIRMWARE_RENOIR,8,3            ; @FIRMWARE_RENOIR
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_AMD_PG_SUPPORT_VCN_DPG,4,2     ; @AMD_PG_SUPPORT_VCN_DPG
	.comm	_FIRMWARE_NAVI10,8,3            ; @FIRMWARE_NAVI10
	.comm	_FIRMWARE_NAVI14,8,3            ; @FIRMWARE_NAVI14
	.comm	_FIRMWARE_NAVI12,8,3            ; @FIRMWARE_NAVI12
	.comm	_EINVAL,4,2                     ; @EINVAL
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"amdgpu_vcn: Can't load firmware \"%s\"\n"

l_.str.1:                               ; @.str.1
	.asciz	"amdgpu_vcn: Can't validate firmware \"%s\"\n"

l_.str.2:                               ; @.str.2
	.asciz	"Found VCN firmware Version ENC: %hu.%hu DEC: %hu VEP: %hu Revision: %hu\n"

l_.str.3:                               ; @.str.3
	.asciz	"Found VCN firmware Version: %hu.%hu Family ID: %hu\n"

	.comm	_AMDGPU_VCN_STACK_SIZE,8,3      ; @AMDGPU_VCN_STACK_SIZE
	.comm	_AMDGPU_VCN_CONTEXT_SIZE,8,3    ; @AMDGPU_VCN_CONTEXT_SIZE
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
	.comm	_AMDGPU_GEM_DOMAIN_VRAM,4,2     ; @AMDGPU_GEM_DOMAIN_VRAM
l_.str.4:                               ; @.str.4
	.asciz	"(%d) failed to allocate vcn bo\n"

l_.str.5:                               ; @.str.5
	.asciz	"(%d) failed to allocate DPG bo\n"

.subsections_via_symbols
