	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_dp_link_train_init
_radeon_dp_link_train_init:             ## @radeon_dp_link_train_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	movl	28(%rdi), %edi
	callq	_to_radeon_encoder
	movq	(%rax), %r14
	movl	36(%rbx), %edi
	movq	_DP_SET_POWER_D0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_radeon_dp_set_rx_power_state
	movq	(%rbx), %rax
	movl	12(%rax), %edx
	andl	$1, %edx
	negl	%edx
	movl	12(%rbx), %edi
	movq	_DP_DOWNSPREAD_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DP_SPREAD_AMP_0_5@GOTPCREL(%rip), %rax
	andl	(%rax), %edx
	callq	_drm_dp_dpcd_writeb
	movq	(%r14), %rax
	movq	_DP_PANEL_MODE_INTERNAL_DP2_MODE@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_2
## %bb.1:
	movl	12(%rbx), %edi
	movq	_DP_EDP_CONFIGURATION_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %edx
	callq	_drm_dp_dpcd_writeb
LBB0_2:
	movl	8(%rbx), %r14d
	movq	(%rbx), %rdi
	callq	_drm_dp_enhanced_frame_cap
	xorl	%edx, %edx
	testq	%rax, %rax
	je	LBB0_4
## %bb.3:
	movq	_DP_LANE_COUNT_ENHANCED_FRAME_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
LBB0_4:
	orl	%r14d, %edx
	movl	12(%rbx), %edi
	movq	_DP_LANE_COUNT_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_drm_dp_dpcd_writeb
	movl	20(%rbx), %edi
	callq	_drm_dp_link_rate_to_bw_code
	movl	12(%rbx), %edi
	movq	_DP_LINK_BW_SET@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edx
	callq	_drm_dp_dpcd_writeb
	movl	24(%rbx), %edi
	callq	_ASIC_IS_DCE4
	testq	%rax, %rax
	je	LBB0_5
LBB0_6:
	movl	28(%rbx), %edi
	movq	_ATOM_ENCODER_CMD_DP_LINK_TRAINING_START@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_atombios_dig_encoder_setup
	jmp	LBB0_8
LBB0_5:
	cmpl	$0, 32(%rbx)
	je	LBB0_6
## %bb.7:
	movl	24(%rbx), %edi
	movq	_ATOM_DP_ACTION_TRAINING_START@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	16(%rbx), %ecx
	movl	20(%rbx), %edx
	xorl	%r8d, %r8d
	callq	_radeon_dp_encoder_service
LBB0_8:
	movl	12(%rbx), %edi
	movq	_DP_TRAINING_PATTERN_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DP_TRAINING_PATTERN_DISABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_drm_dp_dpcd_writeb
	xorl	%eax, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DP_SET_POWER_D0,4,2            ## @DP_SET_POWER_D0
	.comm	_DP_DOWNSPREAD_CTRL,4,2         ## @DP_DOWNSPREAD_CTRL
	.comm	_DP_SPREAD_AMP_0_5,4,2          ## @DP_SPREAD_AMP_0_5
	.comm	_DP_PANEL_MODE_INTERNAL_DP2_MODE,8,3 ## @DP_PANEL_MODE_INTERNAL_DP2_MODE
	.comm	_DP_EDP_CONFIGURATION_SET,4,2   ## @DP_EDP_CONFIGURATION_SET
	.comm	_DP_LANE_COUNT_ENHANCED_FRAME_EN,4,2 ## @DP_LANE_COUNT_ENHANCED_FRAME_EN
	.comm	_DP_LANE_COUNT_SET,4,2          ## @DP_LANE_COUNT_SET
	.comm	_DP_LINK_BW_SET,4,2             ## @DP_LINK_BW_SET
	.comm	_ATOM_ENCODER_CMD_DP_LINK_TRAINING_START,4,2 ## @ATOM_ENCODER_CMD_DP_LINK_TRAINING_START
	.comm	_ATOM_DP_ACTION_TRAINING_START,4,2 ## @ATOM_DP_ACTION_TRAINING_START
	.comm	_DP_TRAINING_PATTERN_SET,4,2    ## @DP_TRAINING_PATTERN_SET
	.comm	_DP_TRAINING_PATTERN_DISABLE,4,2 ## @DP_TRAINING_PATTERN_DISABLE
	.no_dead_strip	_radeon_dp_link_train_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_dp_link_train_init
_radeon_dp_link_train_init:             ; @radeon_dp_link_train_init
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	w0, [x0, #28]
	bl	_to_radeon_encoder
	ldr	x20, [x0]
	ldr	w0, [x19, #36]
Lloh0:
	adrp	x8, _DP_SET_POWER_D0@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DP_SET_POWER_D0@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	bl	_radeon_dp_set_rx_power_state
	ldr	x8, [x19]
	ldr	w8, [x8, #12]
	sbfx	w8, w8, #0, #1
Lloh3:
	adrp	x9, _DP_DOWNSPREAD_CTRL@GOTPAGE
Lloh4:
	ldr	x9, [x9, _DP_DOWNSPREAD_CTRL@GOTPAGEOFF]
	ldr	w0, [x19, #12]
Lloh5:
	ldr	w1, [x9]
Lloh6:
	adrp	x9, _DP_SPREAD_AMP_0_5@GOTPAGE
Lloh7:
	ldr	x9, [x9, _DP_SPREAD_AMP_0_5@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	and	w2, w8, w9
	bl	_drm_dp_dpcd_writeb
	ldr	x8, [x20]
Lloh9:
	adrp	x9, _DP_PANEL_MODE_INTERNAL_DP2_MODE@GOTPAGE
Lloh10:
	ldr	x9, [x9, _DP_PANEL_MODE_INTERNAL_DP2_MODE@GOTPAGEOFF]
Lloh11:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_2
; %bb.1:
	ldr	w0, [x19, #12]
Lloh12:
	adrp	x8, _DP_EDP_CONFIGURATION_SET@GOTPAGE
Lloh13:
	ldr	x8, [x8, _DP_EDP_CONFIGURATION_SET@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mov	w2, #1
	bl	_drm_dp_dpcd_writeb
LBB0_2:
	ldr	w20, [x19, #8]
	ldr	x0, [x19]
	bl	_drm_dp_enhanced_frame_cap
Lloh15:
	adrp	x8, _DP_LANE_COUNT_ENHANCED_FRAME_EN@GOTPAGE
Lloh16:
	ldr	x8, [x8, _DP_LANE_COUNT_ENHANCED_FRAME_EN@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w2, w8, w20
	ldr	w0, [x19, #12]
Lloh18:
	adrp	x8, _DP_LANE_COUNT_SET@GOTPAGE
Lloh19:
	ldr	x8, [x8, _DP_LANE_COUNT_SET@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	bl	_drm_dp_dpcd_writeb
	ldr	w0, [x19, #20]
	bl	_drm_dp_link_rate_to_bw_code
	mov	x2, x0
	ldr	w0, [x19, #12]
Lloh21:
	adrp	x8, _DP_LINK_BW_SET@GOTPAGE
Lloh22:
	ldr	x8, [x8, _DP_LINK_BW_SET@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	bl	_drm_dp_dpcd_writeb
	ldr	w0, [x19, #24]
	bl	_ASIC_IS_DCE4
	cbz	x0, LBB0_4
LBB0_3:
	ldr	w0, [x19, #28]
Lloh24:
	adrp	x8, _ATOM_ENCODER_CMD_DP_LINK_TRAINING_START@GOTPAGE
Lloh25:
	ldr	x8, [x8, _ATOM_ENCODER_CMD_DP_LINK_TRAINING_START@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_atombios_dig_encoder_setup
	b	LBB0_6
LBB0_4:
	ldr	w8, [x19, #32]
	cbz	w8, LBB0_3
; %bb.5:
	ldp	w2, w0, [x19, #20]
Lloh27:
	adrp	x8, _ATOM_DP_ACTION_TRAINING_START@GOTPAGE
Lloh28:
	ldr	x8, [x8, _ATOM_DP_ACTION_TRAINING_START@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	ldr	w3, [x19, #16]
	mov	w4, #0
	bl	_radeon_dp_encoder_service
LBB0_6:
	ldr	w0, [x19, #12]
Lloh30:
	adrp	x8, _DP_TRAINING_PATTERN_SET@GOTPAGE
Lloh31:
	ldr	x8, [x8, _DP_TRAINING_PATTERN_SET@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
Lloh33:
	adrp	x8, _DP_TRAINING_PATTERN_DISABLE@GOTPAGE
Lloh34:
	ldr	x8, [x8, _DP_TRAINING_PATTERN_DISABLE@GOTPAGEOFF]
Lloh35:
	ldr	w2, [x8]
	bl	_drm_dp_dpcd_writeb
	mov	w0, #0
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.cfi_endproc
                                        ; -- End function
	.comm	_DP_SET_POWER_D0,4,2            ; @DP_SET_POWER_D0
	.comm	_DP_DOWNSPREAD_CTRL,4,2         ; @DP_DOWNSPREAD_CTRL
	.comm	_DP_SPREAD_AMP_0_5,4,2          ; @DP_SPREAD_AMP_0_5
	.comm	_DP_PANEL_MODE_INTERNAL_DP2_MODE,8,3 ; @DP_PANEL_MODE_INTERNAL_DP2_MODE
	.comm	_DP_EDP_CONFIGURATION_SET,4,2   ; @DP_EDP_CONFIGURATION_SET
	.comm	_DP_LANE_COUNT_ENHANCED_FRAME_EN,4,2 ; @DP_LANE_COUNT_ENHANCED_FRAME_EN
	.comm	_DP_LANE_COUNT_SET,4,2          ; @DP_LANE_COUNT_SET
	.comm	_DP_LINK_BW_SET,4,2             ; @DP_LINK_BW_SET
	.comm	_ATOM_ENCODER_CMD_DP_LINK_TRAINING_START,4,2 ; @ATOM_ENCODER_CMD_DP_LINK_TRAINING_START
	.comm	_ATOM_DP_ACTION_TRAINING_START,4,2 ; @ATOM_DP_ACTION_TRAINING_START
	.comm	_DP_TRAINING_PATTERN_SET,4,2    ; @DP_TRAINING_PATTERN_SET
	.comm	_DP_TRAINING_PATTERN_DISABLE,4,2 ; @DP_TRAINING_PATTERN_DISABLE
	.no_dead_strip	_radeon_dp_link_train_init
.subsections_via_symbols
