	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v9_0_set_powergating_state
_gfx_v9_0_set_powergating_state:        ## @gfx_v9_0_set_powergating_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %r12
	movq	_AMD_PG_STATE_GATE@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	xorl	%r15d, %r15d
	cmpl	%esi, %r13d
	sete	%bl
	movl	(%rdi), %eax
	leal	-129(%rax), %ecx
	cmpl	$2, %ecx
	jae	LBB0_1
## %bb.4:
	cmpl	%r14d, %r13d
	je	LBB0_6
## %bb.5:
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_gfx_off_ctrl
	leaq	8(%r12), %rdi
	callq	_cancel_delayed_work_sync
LBB0_6:
	movb	%bl, %r15b
	movq	_AMD_PG_SUPPORT_RLC_SMU_HS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	xorl	%ebx, %ebx
	andl	4(%r12), %eax
	setne	%bl
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_gfx_v9_0_enable_sck_slow_down_on_power_up
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_gfx_v9_0_enable_sck_slow_down_on_power_down
	movq	_AMD_PG_SUPPORT_CP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	xorl	%esi, %esi
	andl	4(%r12), %eax
	setne	%sil
	movq	%r12, %rdi
	callq	_gfx_v9_0_enable_cp_power_gating
	movq	%r12, %rdi
	callq	_is_support_sw_smu
	testl	%eax, %eax
	je	LBB0_9
## %bb.7:
	cmpl	%r14d, %r13d
	jne	LBB0_9
## %bb.8:
	leaq	12(%r12), %rdi
	movl	%r15d, %esi
	callq	_smu_set_gfx_cgpg
LBB0_9:
	movq	%r12, %rdi
	movl	%r15d, %esi
	callq	_gfx_v9_0_update_gfx_cg_power_gating
	movq	%r12, %rdi
	movl	%r15d, %esi
	callq	_gfx_v9_0_update_gfx_mg_power_gating
	cmpl	%r14d, %r13d
	je	LBB0_10
	jmp	LBB0_11
LBB0_1:
	cmpl	$128, %eax
	jne	LBB0_11
## %bb.2:
	cmpl	%r14d, %r13d
	jne	LBB0_3
LBB0_10:
	movq	%r12, %rdi
	movl	$1, %esi
	callq	_amdgpu_gfx_off_ctrl
	jmp	LBB0_11
LBB0_3:
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_gfx_off_ctrl
	addq	$8, %r12
	movq	%r12, %rdi
	callq	_cancel_delayed_work_sync
LBB0_11:
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_PG_STATE_GATE,4,2          ## @AMD_PG_STATE_GATE
	.comm	_AMD_PG_SUPPORT_RLC_SMU_HS,4,2  ## @AMD_PG_SUPPORT_RLC_SMU_HS
	.comm	_AMD_PG_SUPPORT_CP,4,2          ## @AMD_PG_SUPPORT_CP
	.no_dead_strip	_gfx_v9_0_set_powergating_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v9_0_set_powergating_state
_gfx_v9_0_set_powergating_state:        ; @gfx_v9_0_set_powergating_state
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x8, _AMD_PG_STATE_GATE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMD_PG_STATE_GATE@GOTPAGEOFF]
Lloh2:
	ldr	w23, [x8]
	cmp	w23, w1
	cset	w21, eq
	ldr	w8, [x0]
	sub	w9, w8, #129
	cmp	w9, #2
	b.hs	LBB0_7
; %bb.1:
	cmp	w23, w20
	b.eq	LBB0_3
; %bb.2:
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_gfx_off_ctrl
	add	x0, x19, #8
	bl	_cancel_delayed_work_sync
LBB0_3:
	ldr	w8, [x19, #4]
Lloh3:
	adrp	x9, _AMD_PG_SUPPORT_RLC_SMU_HS@GOTPAGE
Lloh4:
	ldr	x9, [x9, _AMD_PG_SUPPORT_RLC_SMU_HS@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	tst	w9, w8
	cset	w22, ne
	mov	x0, x19
	mov	x1, x22
	bl	_gfx_v9_0_enable_sck_slow_down_on_power_up
	mov	x0, x19
	mov	x1, x22
	bl	_gfx_v9_0_enable_sck_slow_down_on_power_down
	ldr	w8, [x19, #4]
Lloh6:
	adrp	x9, _AMD_PG_SUPPORT_CP@GOTPAGE
Lloh7:
	ldr	x9, [x9, _AMD_PG_SUPPORT_CP@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	tst	w9, w8
	cset	w1, ne
	mov	x0, x19
	bl	_gfx_v9_0_enable_cp_power_gating
	mov	x0, x19
	bl	_is_support_sw_smu
	cbz	w0, LBB0_6
; %bb.4:
	cmp	w23, w20
	b.ne	LBB0_6
; %bb.5:
	add	x0, x19, #12
	mov	x1, x21
	bl	_smu_set_gfx_cgpg
LBB0_6:
	mov	x0, x19
	mov	x1, x21
	bl	_gfx_v9_0_update_gfx_cg_power_gating
	mov	x0, x19
	mov	x1, x21
	bl	_gfx_v9_0_update_gfx_mg_power_gating
	cmp	w23, w20
	b.eq	LBB0_9
	b	LBB0_11
LBB0_7:
	cmp	w8, #128
	b.ne	LBB0_11
; %bb.8:
	cmp	w23, w20
	b.ne	LBB0_10
LBB0_9:
	mov	x0, x19
	mov	w1, #1
	bl	_amdgpu_gfx_off_ctrl
	b	LBB0_11
LBB0_10:
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_gfx_off_ctrl
	add	x0, x19, #8
	bl	_cancel_delayed_work_sync
LBB0_11:
	mov	w0, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_PG_STATE_GATE,4,2          ; @AMD_PG_STATE_GATE
	.comm	_AMD_PG_SUPPORT_RLC_SMU_HS,4,2  ; @AMD_PG_SUPPORT_RLC_SMU_HS
	.comm	_AMD_PG_SUPPORT_CP,4,2          ; @AMD_PG_SUPPORT_CP
	.no_dead_strip	_gfx_v9_0_set_powergating_state
.subsections_via_symbols
