	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function etnaviv_gpu_update_clock
_etnaviv_gpu_update_clock:              ## @etnaviv_gpu_update_clock
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	_chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 20(%rdi)
	je	LBB0_2
## %bb.1:
	movl	16(%rbx), %edi
	movl	(%rbx), %esi
	movb	4(%rbx), %cl
	sarl	%cl, %esi
	callq	_clk_set_rate
	movl	12(%rbx), %edi
	movl	8(%rbx), %esi
	movb	4(%rbx), %cl
	sarl	%cl, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_clk_set_rate                   ## TAILCALL
LBB0_2:
	movb	$6, %cl
	subb	4(%rbx), %cl
	movl	$1, %r14d
	shll	%cl, %r14d
	movq	_VIVS_HI_CLOCK_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_gpu_read
	movq	_VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r15d
	notl	%r15d
	andl	%eax, %r15d
	movl	%r14d, %edi
	callq	_VIVS_HI_CLOCK_CONTROL_FSCALE_VAL
	orl	%eax, %r15d
	movq	%rbx, %rdi
	movl	%r15d, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_etnaviv_gpu_load_clock         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING,4,2 ## @chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING
	.comm	_VIVS_HI_CLOCK_CONTROL,4,2      ## @VIVS_HI_CLOCK_CONTROL
	.comm	_VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK,4,2 ## @VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK
	.no_dead_strip	_etnaviv_gpu_update_clock
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function etnaviv_gpu_update_clock
_etnaviv_gpu_update_clock:              ; @etnaviv_gpu_update_clock
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	w8, [x0, #20]
Lloh0:
	adrp	x9, _chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING@GOTPAGE
Lloh1:
	ldr	x9, [x9, _chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
	ldr	w0, [x19, #16]
	ldp	w8, w9, [x19]
	asr	w1, w8, w9
	bl	_clk_set_rate
	ldp	w8, w0, [x19, #8]
	ldr	w9, [x19, #4]
	asr	w1, w8, w9
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_clk_set_rate
LBB0_2:
	ldr	w8, [x19, #4]
	mov	w9, #6
	sub	w8, w9, w8
	mov	w9, #1
	lsl	w20, w9, w8
Lloh3:
	adrp	x8, _VIVS_HI_CLOCK_CONTROL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _VIVS_HI_CLOCK_CONTROL@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_gpu_read
Lloh6:
	adrp	x8, _VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	bic	w21, w0, w8
	mov	x0, x20
	bl	_VIVS_HI_CLOCK_CONTROL_FSCALE_VAL
	orr	w1, w21, w0
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_etnaviv_gpu_load_clock
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING,4,2 ; @chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING
	.comm	_VIVS_HI_CLOCK_CONTROL,4,2      ; @VIVS_HI_CLOCK_CONTROL
	.comm	_VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK,4,2 ; @VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK
	.no_dead_strip	_etnaviv_gpu_update_clock
.subsections_via_symbols
