	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rv770_pcie_gen2_enable
_rv770_pcie_gen2_enable:                ## @rv770_pcie_gen2_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_radeon_pcie_gen2@GOTPCREL(%rip), %rax
	cmpq	$0, (%rax)
	je	LBB0_13
## %bb.1:
	movq	%rdi, %rbx
	movl	(%rdi), %eax
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_2
LBB0_13:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	movq	_RADEON_IS_PCIE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_13
## %bb.3:
	movq	%rbx, %rdi
	callq	_ASIC_IS_X2
	testq	%rax, %rax
	jne	LBB0_13
## %bb.4:
	movq	8(%rbx), %rax
	movq	(%rax), %rax
	movq	(%rax), %rax
	movq	_PCIE_SPEED_5_0GT@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_6
## %bb.5:
	movq	_PCIE_SPEED_8_0GT@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_13
LBB0_6:
	leaq	L_.str(%rip), %rdi
	callq	_DRM_INFO
	movq	_PCIE_LC_LINK_WIDTH_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_UPCONFIGURE_DIS@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32_PCIE_PORT
	movl	(%rbx), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_RENEGOTIATION_SUPPORT@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_8
## %bb.7:
	movq	_LC_LINK_WIDTH_RD_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	andl	%eax, %esi
	movq	_LC_LINK_WIDTH_RD_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %esi
	movq	_LC_LINK_WIDTH_MASK@GOTPCREL(%rip), %rcx
	movq	_LC_RECONFIG_ARC_MISSING_ESCAPE@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	notl	%edx
	movq	_LC_RECONFIG_NOW@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	andl	%edx, %eax
	movq	_LC_RENEGOTIATE_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	orl	%eax, %esi
	movq	_LC_UPCONFIGURE_SUPPORT@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	jmp	LBB0_9
LBB0_8:
	movq	_LC_UPCONFIGURE_DIS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	%eax, %esi
LBB0_9:
	movl	(%rbx), %edi
	callq	_WREG32_PCIE_PORT
	movq	_PCIE_LC_SPEED_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_OTHER_SIDE_EVER_SENT_GEN2@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_12
## %bb.10:
	movq	_LC_OTHER_SIDE_SUPPORTS_GEN2@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_12
## %bb.11:
	movl	$21532, %edi                    ## imm = 0x541C
	callq	_RREG32
	orl	$8, %eax
	movl	$21532, %edi                    ## imm = 0x541C
	movl	%eax, %esi
	callq	_WREG32
	movq	_MM_CFGREGS_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_MM_WR_TO_CFG_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_WREG32
	movl	$16520, %edi                    ## imm = 0x4088
	callq	_RREG16
	movq	_TARGET_LINK_SPEED_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	orl	$2, %esi
	movl	$16520, %edi                    ## imm = 0x4088
	callq	_WREG16
	movl	(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r14), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_TARGET_LINK_SPEED_OVERRIDE_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r14), %edi
	callq	_WREG32_PCIE_PORT
	movl	(%r14), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_CLR_FAILED_SPD_CHANGE_CNT@GOTPCREL(%rip), %rbx
	orl	(%rbx), %eax
	movl	(%r14), %edi
	movl	%eax, %esi
	callq	_WREG32_PCIE_PORT
	movl	(%r14), %edi
	callq	_RREG32_PCIE_PORT
	movl	(%rbx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r14), %edi
	callq	_WREG32_PCIE_PORT
	movq	_LC_GEN2_EN_STRAP@GOTPCREL(%rip), %r15
	movq	%r14, %rbx
LBB0_12:
	movl	(%rbx), %edi
	callq	_RREG32_PCIE_PORT
	orl	(%r15), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_PCIE_PORT               ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_radeon_pcie_gen2,8,3           ## @radeon_pcie_gen2
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
	.comm	_RADEON_IS_PCIE,4,2             ## @RADEON_IS_PCIE
	.comm	_PCIE_SPEED_5_0GT,8,3           ## @PCIE_SPEED_5_0GT
	.comm	_PCIE_SPEED_8_0GT,8,3           ## @PCIE_SPEED_8_0GT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"

	.comm	_PCIE_LC_LINK_WIDTH_CNTL,4,2    ## @PCIE_LC_LINK_WIDTH_CNTL
	.comm	_LC_UPCONFIGURE_DIS,4,2         ## @LC_UPCONFIGURE_DIS
	.comm	_LC_RENEGOTIATION_SUPPORT,4,2   ## @LC_RENEGOTIATION_SUPPORT
	.comm	_LC_LINK_WIDTH_RD_MASK,4,2      ## @LC_LINK_WIDTH_RD_MASK
	.comm	_LC_LINK_WIDTH_RD_SHIFT,4,2     ## @LC_LINK_WIDTH_RD_SHIFT
	.comm	_LC_LINK_WIDTH_MASK,4,2         ## @LC_LINK_WIDTH_MASK
	.comm	_LC_RECONFIG_ARC_MISSING_ESCAPE,4,2 ## @LC_RECONFIG_ARC_MISSING_ESCAPE
	.comm	_LC_RECONFIG_NOW,4,2            ## @LC_RECONFIG_NOW
	.comm	_LC_RENEGOTIATE_EN,4,2          ## @LC_RENEGOTIATE_EN
	.comm	_LC_UPCONFIGURE_SUPPORT,4,2     ## @LC_UPCONFIGURE_SUPPORT
	.comm	_PCIE_LC_SPEED_CNTL,4,2         ## @PCIE_LC_SPEED_CNTL
	.comm	_LC_OTHER_SIDE_EVER_SENT_GEN2,4,2 ## @LC_OTHER_SIDE_EVER_SENT_GEN2
	.comm	_LC_OTHER_SIDE_SUPPORTS_GEN2,4,2 ## @LC_OTHER_SIDE_SUPPORTS_GEN2
	.comm	_MM_CFGREGS_CNTL,4,2            ## @MM_CFGREGS_CNTL
	.comm	_MM_WR_TO_CFG_EN,4,2            ## @MM_WR_TO_CFG_EN
	.comm	_TARGET_LINK_SPEED_MASK,4,2     ## @TARGET_LINK_SPEED_MASK
	.comm	_LC_TARGET_LINK_SPEED_OVERRIDE_EN,4,2 ## @LC_TARGET_LINK_SPEED_OVERRIDE_EN
	.comm	_LC_CLR_FAILED_SPD_CHANGE_CNT,4,2 ## @LC_CLR_FAILED_SPD_CHANGE_CNT
	.comm	_LC_GEN2_EN_STRAP,4,2           ## @LC_GEN2_EN_STRAP
	.no_dead_strip	_rv770_pcie_gen2_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rv770_pcie_gen2_enable
_rv770_pcie_gen2_enable:                ; @rv770_pcie_gen2_enable
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
Lloh0:
	adrp	x8, _radeon_pcie_gen2@GOTPAGE
Lloh1:
	ldr	x8, [x8, _radeon_pcie_gen2@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	cbz	x8, LBB0_2
; %bb.1:
	mov	x19, x0
	ldr	w8, [x0]
Lloh3:
	adrp	x9, _RADEON_IS_IGP@GOTPAGE
Lloh4:
	ldr	x9, [x9, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_3
LBB0_2:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_3:
Lloh6:
	adrp	x9, _RADEON_IS_PCIE@GOTPAGE
Lloh7:
	ldr	x9, [x9, _RADEON_IS_PCIE@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.4:
	mov	x0, x19
	bl	_ASIC_IS_X2
	cbnz	x0, LBB0_2
; %bb.5:
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	ldr	x8, [x8]
Lloh9:
	adrp	x9, _PCIE_SPEED_5_0GT@GOTPAGE
Lloh10:
	ldr	x9, [x9, _PCIE_SPEED_5_0GT@GOTPAGEOFF]
Lloh11:
	ldr	x9, [x9]
Lloh12:
	adrp	x10, _PCIE_SPEED_8_0GT@GOTPAGE
Lloh13:
	ldr	x10, [x10, _PCIE_SPEED_8_0GT@GOTPAGEOFF]
Lloh14:
	ldr	x10, [x10]
	cmp	x8, x9
	ccmp	x8, x10, #4, ne
	b.ne	LBB0_2
; %bb.6:
Lloh15:
	adrp	x0, l_.str@PAGE
Lloh16:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_INFO
Lloh17:
	adrp	x20, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGE
Lloh18:
	ldr	x20, [x20, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PCIE_PORT
Lloh19:
	adrp	x19, _LC_UPCONFIGURE_DIS@GOTPAGE
Lloh20:
	ldr	x19, [x19, _LC_UPCONFIGURE_DIS@GOTPAGEOFF]
	ldr	w8, [x19]
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32_PCIE_PORT
	ldr	w0, [x20]
	bl	_RREG32_PCIE_PORT
Lloh21:
	adrp	x8, _LC_RENEGOTIATION_SUPPORT@GOTPAGE
Lloh22:
	ldr	x8, [x8, _LC_RENEGOTIATION_SUPPORT@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_8
; %bb.7:
Lloh24:
	adrp	x8, _LC_LINK_WIDTH_RD_MASK@GOTPAGE
Lloh25:
	ldr	x8, [x8, _LC_LINK_WIDTH_RD_MASK@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
Lloh27:
	adrp	x9, _LC_LINK_WIDTH_RD_SHIFT@GOTPAGE
Lloh28:
	ldr	x9, [x9, _LC_LINK_WIDTH_RD_SHIFT@GOTPAGEOFF]
	and	w8, w8, w0
Lloh29:
	ldr	w9, [x9]
	asr	w8, w8, w9
Lloh30:
	adrp	x9, _LC_LINK_WIDTH_MASK@GOTPAGE
Lloh31:
	ldr	x9, [x9, _LC_LINK_WIDTH_MASK@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
Lloh33:
	adrp	x10, _LC_RECONFIG_ARC_MISSING_ESCAPE@GOTPAGE
Lloh34:
	ldr	x10, [x10, _LC_RECONFIG_ARC_MISSING_ESCAPE@GOTPAGEOFF]
Lloh35:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh36:
	adrp	x10, _LC_RECONFIG_NOW@GOTPAGE
Lloh37:
	ldr	x10, [x10, _LC_RECONFIG_NOW@GOTPAGEOFF]
	bic	w9, w0, w9
Lloh38:
	ldr	w10, [x10]
	orr	w8, w10, w8
Lloh39:
	adrp	x10, _LC_RENEGOTIATE_EN@GOTPAGE
Lloh40:
	ldr	x10, [x10, _LC_RENEGOTIATE_EN@GOTPAGEOFF]
Lloh41:
	ldr	w10, [x10]
	orr	w8, w8, w10
Lloh42:
	adrp	x10, _LC_UPCONFIGURE_SUPPORT@GOTPAGE
Lloh43:
	ldr	x10, [x10, _LC_UPCONFIGURE_SUPPORT@GOTPAGEOFF]
Lloh44:
	ldr	w10, [x10]
	orr	w8, w8, w9
	orr	w1, w8, w10
	b	LBB0_9
LBB0_8:
	ldr	w8, [x19]
	orr	w1, w8, w0
LBB0_9:
	ldr	w0, [x20]
	bl	_WREG32_PCIE_PORT
Lloh45:
	adrp	x19, _PCIE_LC_SPEED_CNTL@GOTPAGE
Lloh46:
	ldr	x19, [x19, _PCIE_LC_SPEED_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PCIE_PORT
Lloh47:
	adrp	x8, _LC_OTHER_SIDE_EVER_SENT_GEN2@GOTPAGE
Lloh48:
	ldr	x8, [x8, _LC_OTHER_SIDE_EVER_SENT_GEN2@GOTPAGEOFF]
Lloh49:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_12
; %bb.10:
Lloh50:
	adrp	x8, _LC_OTHER_SIDE_SUPPORTS_GEN2@GOTPAGE
Lloh51:
	ldr	x8, [x8, _LC_OTHER_SIDE_SUPPORTS_GEN2@GOTPAGEOFF]
Lloh52:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_13
; %bb.11:
	mov	w0, #21532
	bl	_RREG32
	orr	w1, w0, #0x8
	mov	w0, #21532
	bl	_WREG32
Lloh53:
	adrp	x20, _MM_CFGREGS_CNTL@GOTPAGE
Lloh54:
	ldr	x20, [x20, _MM_CFGREGS_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
Lloh55:
	adrp	x8, _MM_WR_TO_CFG_EN@GOTPAGE
Lloh56:
	ldr	x8, [x8, _MM_WR_TO_CFG_EN@GOTPAGEOFF]
Lloh57:
	ldr	w1, [x8]
	bl	_WREG32
	mov	w0, #16520
	bl	_RREG16
Lloh58:
	adrp	x8, _TARGET_LINK_SPEED_MASK@GOTPAGE
Lloh59:
	ldr	x8, [x8, _TARGET_LINK_SPEED_MASK@GOTPAGEOFF]
Lloh60:
	ldr	w8, [x8]
	bic	w8, w0, w8
	orr	w1, w8, #0x2
	mov	w0, #16520
	bl	_WREG16
	ldr	w0, [x20]
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x19]
	bl	_RREG32_PCIE_PORT
Lloh61:
	adrp	x8, _LC_TARGET_LINK_SPEED_OVERRIDE_EN@GOTPAGE
Lloh62:
	ldr	x8, [x8, _LC_TARGET_LINK_SPEED_OVERRIDE_EN@GOTPAGEOFF]
Lloh63:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w0, [x19]
	bl	_WREG32_PCIE_PORT
	ldr	w0, [x19]
	bl	_RREG32_PCIE_PORT
Lloh64:
	adrp	x20, _LC_CLR_FAILED_SPD_CHANGE_CNT@GOTPAGE
Lloh65:
	ldr	x20, [x20, _LC_CLR_FAILED_SPD_CHANGE_CNT@GOTPAGEOFF]
	ldr	w8, [x20]
	orr	w1, w8, w0
	ldr	w0, [x19]
	bl	_WREG32_PCIE_PORT
	ldr	w0, [x19]
	bl	_RREG32_PCIE_PORT
	ldr	w8, [x20]
	bic	w1, w0, w8
	ldr	w0, [x19]
	bl	_WREG32_PCIE_PORT
Lloh66:
	adrp	x21, _LC_GEN2_EN_STRAP@GOTPAGE
Lloh67:
	ldr	x21, [x21, _LC_GEN2_EN_STRAP@GOTPAGEOFF]
	mov	x20, x19
	b	LBB0_14
LBB0_12:
Lloh68:
	adrp	x21, _LC_UPCONFIGURE_DIS@GOTPAGE
Lloh69:
	ldr	x21, [x21, _LC_UPCONFIGURE_DIS@GOTPAGEOFF]
	b	LBB0_14
LBB0_13:
Lloh70:
	adrp	x21, _LC_UPCONFIGURE_DIS@GOTPAGE
Lloh71:
	ldr	x21, [x21, _LC_UPCONFIGURE_DIS@GOTPAGEOFF]
Lloh72:
	adrp	x20, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGE
Lloh73:
	ldr	x20, [x20, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGEOFF]
LBB0_14:
	ldr	w0, [x20]
	bl	_RREG32_PCIE_PORT
	ldr	w8, [x21]
	orr	w1, w8, w0
	ldr	w0, [x20]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32_PCIE_PORT
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh66, Lloh67
	.loh AdrpLdrGot	Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh68, Lloh69
	.loh AdrpLdrGot	Lloh72, Lloh73
	.loh AdrpLdrGot	Lloh70, Lloh71
	.cfi_endproc
                                        ; -- End function
	.comm	_radeon_pcie_gen2,8,3           ; @radeon_pcie_gen2
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
	.comm	_RADEON_IS_PCIE,4,2             ; @RADEON_IS_PCIE
	.comm	_PCIE_SPEED_5_0GT,8,3           ; @PCIE_SPEED_5_0GT
	.comm	_PCIE_SPEED_8_0GT,8,3           ; @PCIE_SPEED_8_0GT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"

	.comm	_PCIE_LC_LINK_WIDTH_CNTL,4,2    ; @PCIE_LC_LINK_WIDTH_CNTL
	.comm	_LC_UPCONFIGURE_DIS,4,2         ; @LC_UPCONFIGURE_DIS
	.comm	_LC_RENEGOTIATION_SUPPORT,4,2   ; @LC_RENEGOTIATION_SUPPORT
	.comm	_LC_LINK_WIDTH_RD_MASK,4,2      ; @LC_LINK_WIDTH_RD_MASK
	.comm	_LC_LINK_WIDTH_RD_SHIFT,4,2     ; @LC_LINK_WIDTH_RD_SHIFT
	.comm	_LC_LINK_WIDTH_MASK,4,2         ; @LC_LINK_WIDTH_MASK
	.comm	_LC_RECONFIG_ARC_MISSING_ESCAPE,4,2 ; @LC_RECONFIG_ARC_MISSING_ESCAPE
	.comm	_LC_RECONFIG_NOW,4,2            ; @LC_RECONFIG_NOW
	.comm	_LC_RENEGOTIATE_EN,4,2          ; @LC_RENEGOTIATE_EN
	.comm	_LC_UPCONFIGURE_SUPPORT,4,2     ; @LC_UPCONFIGURE_SUPPORT
	.comm	_PCIE_LC_SPEED_CNTL,4,2         ; @PCIE_LC_SPEED_CNTL
	.comm	_LC_OTHER_SIDE_EVER_SENT_GEN2,4,2 ; @LC_OTHER_SIDE_EVER_SENT_GEN2
	.comm	_LC_OTHER_SIDE_SUPPORTS_GEN2,4,2 ; @LC_OTHER_SIDE_SUPPORTS_GEN2
	.comm	_MM_CFGREGS_CNTL,4,2            ; @MM_CFGREGS_CNTL
	.comm	_MM_WR_TO_CFG_EN,4,2            ; @MM_WR_TO_CFG_EN
	.comm	_TARGET_LINK_SPEED_MASK,4,2     ; @TARGET_LINK_SPEED_MASK
	.comm	_LC_TARGET_LINK_SPEED_OVERRIDE_EN,4,2 ; @LC_TARGET_LINK_SPEED_OVERRIDE_EN
	.comm	_LC_CLR_FAILED_SPD_CHANGE_CNT,4,2 ; @LC_CLR_FAILED_SPD_CHANGE_CNT
	.comm	_LC_GEN2_EN_STRAP,4,2           ; @LC_GEN2_EN_STRAP
	.no_dead_strip	_rv770_pcie_gen2_enable
.subsections_via_symbols
