	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function program_multi_taps_filter
_program_multi_taps_filter:             ## @program_multi_taps_filter
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, -80(%rbp)                 ## 8-byte Spill
	testq	%rdx, %rdx
	je	LBB0_15
## %bb.1:
	movl	%esi, %r15d
	movl	%ecx, -56(%rbp)                 ## 4-byte Spill
	movq	(%rdi), %rbx
	leal	1(%r15), %eax
	shrl	$31, %eax
	addl	%r15d, %eax
	incl	%eax
	sarl	%eax
	movq	%rax, -64(%rbp)                 ## 8-byte Spill
	movq	_SCLV_PHASES@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %eax
	shrl	$31, %eax
	movl	%ecx, -44(%rbp)                 ## 4-byte Spill
	addl	%ecx, %eax
	sarl	%eax
	movl	%eax, -72(%rbp)                 ## 4-byte Spill
	movq	_mmDCFEV_MEM_PWR_CTRL@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_dm_read_reg
	movl	%eax, %r12d
	movq	_DCFEV_MEM_PWR_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_SCLV_COEFF_MEM_PWR_DIS@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%r12d, %edi
	movl	$1, %esi
	callq	_set_reg_field_value
	movl	(%r14), %esi
	movq	%rbx, %rdi
	movl	%r12d, -68(%rbp)                ## 4-byte Spill
	movl	%r12d, %edx
	callq	_dm_write_reg
	movl	$10, %r13d
	movq	_DCFEV_MEM_PWR_STATUS@GOTPCREL(%rip), %r14
	movq	_SCLV_COEFF_MEM_PWR_STATE@GOTPCREL(%rip), %r12
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	_mmDCFEV_MEM_PWR_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_dm_read_reg
	movl	(%r14), %esi
	movl	(%r12), %edx
	movl	%eax, %edi
	callq	_get_reg_field_value
	testq	%rax, %rax
	je	LBB0_4
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movl	$1, %edi
	callq	_udelay
	decl	%r13d
	jne	LBB0_2
LBB0_4:
	movq	_SCLV_COEF_RAM_SELECT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_SCL_C_RAM_FILTER_TYPE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%r12d, %r12d
	xorl	%edi, %edi
	movl	-56(%rbp), %esi                 ## 4-byte Reload
	callq	_set_reg_field_value
	cmpl	$-1, -44(%rbp)                  ## 4-byte Folded Reload
	jge	LBB0_5
LBB0_14:
	movq	_mmDCFEV_MEM_PWR_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	-68(%rbp), %edx                 ## 4-byte Reload
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_dm_write_reg                   ## TAILCALL
LBB0_15:
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_5:
	movq	-64(%rbp), %rcx                 ## 8-byte Reload
	leal	-1(%rcx), %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	cmpl	$2, %ecx
	movl	$1, %eax
	cmovll	%eax, %ecx
	movq	%rcx, -64(%rbp)                 ## 8-byte Spill
	movq	_SCLV_COEF_RAM_TAP_DATA@GOTPCREL(%rip), %r14
	xorl	%r13d, %r13d
	movq	%r15, -56(%rbp)                 ## 8-byte Spill
	jmp	LBB0_6
	.p2align	4, 0x90
LBB0_13:                                ##   in Loop: Header=BB0_6 Depth=1
	movq	-88(%rbp), %rcx                 ## 8-byte Reload
	leal	1(%rcx), %eax
	cmpl	-72(%rbp), %ecx                 ## 4-byte Folded Reload
	movl	%eax, %r12d
	movq	-56(%rbp), %r15                 ## 8-byte Reload
	je	LBB0_14
LBB0_6:                                 ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_8 Depth 2
	movq	_SCLV_COEF_RAM_SELECT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_SCL_C_RAM_PHASE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%edi, %edi
	movl	%r12d, %esi
	callq	_set_reg_field_value
	testl	%r15d, %r15d
	movq	%r12, -88(%rbp)                 ## 8-byte Spill
	jle	LBB0_13
## %bb.7:                               ##   in Loop: Header=BB0_6 Depth=1
	xorl	%r12d, %r12d
	jmp	LBB0_8
	.p2align	4, 0x90
LBB0_11:                                ##   in Loop: Header=BB0_8 Depth=2
	xorl	%edi, %edi
	movl	$1, %esi
	callq	_set_reg_field_value
	movq	-80(%rbp), %rax                 ## 8-byte Reload
	movl	4(%rax,%r15,4), %esi
	movl	(%r14), %edx
	movq	_SCL_C_RAM_ODD_TAP_COEF@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%edi, %edi
	callq	_set_reg_field_value
	movl	$2, %eax
LBB0_12:                                ##   in Loop: Header=BB0_8 Depth=2
	addl	%eax, %r13d
	movq	_mmSCLV_COEF_RAM_TAP_DATA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_dm_write_reg
	incl	%r12d
	cmpl	%r12d, -64(%rbp)                ## 4-byte Folded Reload
	je	LBB0_13
LBB0_8:                                 ##   Parent Loop BB0_6 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movq	_SCLV_COEF_RAM_SELECT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_SCL_C_RAM_TAP_PAIR_IDX@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%edi, %edi
	movl	%r12d, %esi
	callq	_set_reg_field_value
	movq	_mmSCLV_COEF_RAM_SELECT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_dm_write_reg
	movl	(%r14), %edx
	movq	_SCL_C_RAM_EVEN_TAP_COEF_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%edi, %edi
	movl	$1, %esi
	callq	_set_reg_field_value
	movslq	%r13d, %r15
	movq	-80(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax,%r15,4), %esi
	movl	(%r14), %edx
	movq	_SCL_C_RAM_EVEN_TAP_COEF@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%edi, %edi
	callq	_set_reg_field_value
	movl	(%r14), %edx
	movq	_SCL_C_RAM_ODD_TAP_COEF_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	testb	$1, -56(%rbp)                   ## 1-byte Folded Reload
	je	LBB0_11
## %bb.9:                               ##   in Loop: Header=BB0_8 Depth=2
	cmpl	%r12d, -44(%rbp)                ## 4-byte Folded Reload
	jne	LBB0_11
## %bb.10:                              ##   in Loop: Header=BB0_8 Depth=2
	xorl	%edi, %edi
	xorl	%esi, %esi
	callq	_set_reg_field_value
	movl	$1, %eax
	jmp	LBB0_12
	.cfi_endproc
                                        ## -- End function
	.comm	_SCLV_PHASES,4,2                ## @SCLV_PHASES
	.comm	_mmDCFEV_MEM_PWR_CTRL,4,2       ## @mmDCFEV_MEM_PWR_CTRL
	.comm	_DCFEV_MEM_PWR_CTRL,4,2         ## @DCFEV_MEM_PWR_CTRL
	.comm	_SCLV_COEFF_MEM_PWR_DIS,4,2     ## @SCLV_COEFF_MEM_PWR_DIS
	.comm	_mmDCFEV_MEM_PWR_STATUS,4,2     ## @mmDCFEV_MEM_PWR_STATUS
	.comm	_DCFEV_MEM_PWR_STATUS,4,2       ## @DCFEV_MEM_PWR_STATUS
	.comm	_SCLV_COEFF_MEM_PWR_STATE,4,2   ## @SCLV_COEFF_MEM_PWR_STATE
	.comm	_SCLV_COEF_RAM_SELECT,4,2       ## @SCLV_COEF_RAM_SELECT
	.comm	_SCL_C_RAM_FILTER_TYPE,4,2      ## @SCL_C_RAM_FILTER_TYPE
	.comm	_SCL_C_RAM_PHASE,4,2            ## @SCL_C_RAM_PHASE
	.comm	_SCL_C_RAM_TAP_PAIR_IDX,4,2     ## @SCL_C_RAM_TAP_PAIR_IDX
	.comm	_mmSCLV_COEF_RAM_SELECT,4,2     ## @mmSCLV_COEF_RAM_SELECT
	.comm	_SCLV_COEF_RAM_TAP_DATA,4,2     ## @SCLV_COEF_RAM_TAP_DATA
	.comm	_SCL_C_RAM_EVEN_TAP_COEF_EN,4,2 ## @SCL_C_RAM_EVEN_TAP_COEF_EN
	.comm	_SCL_C_RAM_EVEN_TAP_COEF,4,2    ## @SCL_C_RAM_EVEN_TAP_COEF
	.comm	_SCL_C_RAM_ODD_TAP_COEF_EN,4,2  ## @SCL_C_RAM_ODD_TAP_COEF_EN
	.comm	_SCL_C_RAM_ODD_TAP_COEF,4,2     ## @SCL_C_RAM_ODD_TAP_COEF
	.comm	_mmSCLV_COEF_RAM_TAP_DATA,4,2   ## @mmSCLV_COEF_RAM_TAP_DATA
	.no_dead_strip	_program_multi_taps_filter
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function program_multi_taps_filter
_program_multi_taps_filter:             ; @program_multi_taps_filter
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	add	w8, w1, #1
	add	w9, w1, #2
	cmp	w8, #0
	csinc	w8, w9, w1, lt
Lloh0:
	adrp	x9, _SCLV_PHASES@GOTPAGE
Lloh1:
	ldr	x9, [x9, _SCLV_PHASES@GOTPAGEOFF]
Lloh2:
	ldr	w22, [x9]
	cmp	w22, #0
	cinc	w9, w22, lt
	cbz	x2, LBB0_6
; %bb.1:
	mov	x23, x3
	mov	x19, x2
	mov	x20, x1
	ldr	x21, [x0]
	asr	w24, w8, #1
	asr	w8, w9, #1
	str	w8, [sp, #8]                    ; 4-byte Folded Spill
Lloh3:
	adrp	x25, _mmDCFEV_MEM_PWR_CTRL@GOTPAGE
Lloh4:
	ldr	x25, [x25, _mmDCFEV_MEM_PWR_CTRL@GOTPAGEOFF]
	ldr	w1, [x25]
	mov	x0, x21
	bl	_dm_read_reg
	mov	x26, x0
Lloh5:
	adrp	x8, _DCFEV_MEM_PWR_CTRL@GOTPAGE
Lloh6:
	ldr	x8, [x8, _DCFEV_MEM_PWR_CTRL@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
Lloh8:
	adrp	x8, _SCLV_COEFF_MEM_PWR_DIS@GOTPAGE
Lloh9:
	ldr	x8, [x8, _SCLV_COEFF_MEM_PWR_DIS@GOTPAGEOFF]
Lloh10:
	ldr	w3, [x8]
	mov	w1, #1
	bl	_set_reg_field_value
	ldr	w1, [x25]
	mov	x0, x21
	str	w26, [sp, #4]                   ; 4-byte Folded Spill
	mov	x2, x26
	bl	_dm_write_reg
	mov	w25, #10
Lloh11:
	adrp	x26, _mmDCFEV_MEM_PWR_STATUS@GOTPAGE
Lloh12:
	ldr	x26, [x26, _mmDCFEV_MEM_PWR_STATUS@GOTPAGEOFF]
Lloh13:
	adrp	x27, _DCFEV_MEM_PWR_STATUS@GOTPAGE
Lloh14:
	ldr	x27, [x27, _DCFEV_MEM_PWR_STATUS@GOTPAGEOFF]
Lloh15:
	adrp	x28, _SCLV_COEFF_MEM_PWR_STATE@GOTPAGE
Lloh16:
	ldr	x28, [x28, _SCLV_COEFF_MEM_PWR_STATE@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x26]
	mov	x0, x21
	bl	_dm_read_reg
	ldr	w1, [x27]
	ldr	w2, [x28]
	bl	_get_reg_field_value
	cbz	x0, LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	mov	w0, #1
	bl	_udelay
	subs	w25, w25, #1
	b.ne	LBB0_2
LBB0_4:
Lloh17:
	adrp	x8, _SCLV_COEF_RAM_SELECT@GOTPAGE
Lloh18:
	ldr	x8, [x8, _SCLV_COEF_RAM_SELECT@GOTPAGEOFF]
Lloh19:
	ldr	w2, [x8]
Lloh20:
	adrp	x8, _SCL_C_RAM_FILTER_TYPE@GOTPAGE
Lloh21:
	ldr	x8, [x8, _SCL_C_RAM_FILTER_TYPE@GOTPAGEOFF]
Lloh22:
	ldr	w3, [x8]
	mov	w0, #0
	mov	x1, x23
	bl	_set_reg_field_value
	cmn	w22, #1
	b.ge	LBB0_7
LBB0_5:
Lloh23:
	adrp	x8, _mmDCFEV_MEM_PWR_CTRL@GOTPAGE
Lloh24:
	ldr	x8, [x8, _mmDCFEV_MEM_PWR_CTRL@GOTPAGEOFF]
Lloh25:
	ldr	w1, [x8]
	mov	x0, x21
	ldr	w2, [sp, #4]                    ; 4-byte Folded Reload
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	b	_dm_write_reg
LBB0_6:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
LBB0_7:
	mov	w26, #0
	mov	w22, #0
	subs	w28, w24, #1
	csinc	w25, w24, wzr, gt
Lloh26:
	adrp	x23, _SCLV_COEF_RAM_TAP_DATA@GOTPAGE
Lloh27:
	ldr	x23, [x23, _SCLV_COEF_RAM_TAP_DATA@GOTPAGEOFF]
Lloh28:
	adrp	x27, _mmSCLV_COEF_RAM_TAP_DATA@GOTPAGE
Lloh29:
	ldr	x27, [x27, _mmSCLV_COEF_RAM_TAP_DATA@GOTPAGEOFF]
	b	LBB0_9
LBB0_8:                                 ;   in Loop: Header=BB0_9 Depth=1
	ldp	w9, w10, [sp, #8]               ; 8-byte Folded Reload
	add	w26, w10, #1
	cmp	w10, w9
	b.eq	LBB0_5
LBB0_9:                                 ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_13 Depth 2
Lloh30:
	adrp	x8, _SCLV_COEF_RAM_SELECT@GOTPAGE
Lloh31:
	ldr	x8, [x8, _SCLV_COEF_RAM_SELECT@GOTPAGEOFF]
Lloh32:
	ldr	w2, [x8]
Lloh33:
	adrp	x8, _SCL_C_RAM_PHASE@GOTPAGE
Lloh34:
	ldr	x8, [x8, _SCL_C_RAM_PHASE@GOTPAGEOFF]
Lloh35:
	ldr	w3, [x8]
	mov	w0, #0
	mov	x1, x26
	bl	_set_reg_field_value
	cmp	w20, #1
	str	w26, [sp, #12]                  ; 4-byte Folded Spill
	b.lt	LBB0_8
; %bb.10:                               ;   in Loop: Header=BB0_9 Depth=1
	mov	w24, #0
	b	LBB0_13
LBB0_11:                                ;   in Loop: Header=BB0_13 Depth=2
	mov	w0, #0
	mov	w1, #1
	bl	_set_reg_field_value
	add	x8, x19, x26, lsl #2
	ldr	w1, [x8, #4]
	ldr	w2, [x23]
Lloh36:
	adrp	x8, _SCL_C_RAM_ODD_TAP_COEF@GOTPAGE
Lloh37:
	ldr	x8, [x8, _SCL_C_RAM_ODD_TAP_COEF@GOTPAGEOFF]
Lloh38:
	ldr	w3, [x8]
	mov	w0, #0
	bl	_set_reg_field_value
	mov	w8, #2
LBB0_12:                                ;   in Loop: Header=BB0_13 Depth=2
	add	w22, w26, w8
	ldr	w1, [x27]
	mov	x0, x21
	mov	w2, #0
	bl	_dm_write_reg
	add	w24, w24, #1
	cmp	w25, w24
	b.eq	LBB0_8
LBB0_13:                                ;   Parent Loop BB0_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
Lloh39:
	adrp	x8, _SCLV_COEF_RAM_SELECT@GOTPAGE
Lloh40:
	ldr	x8, [x8, _SCLV_COEF_RAM_SELECT@GOTPAGEOFF]
Lloh41:
	ldr	w2, [x8]
Lloh42:
	adrp	x8, _SCL_C_RAM_TAP_PAIR_IDX@GOTPAGE
Lloh43:
	ldr	x8, [x8, _SCL_C_RAM_TAP_PAIR_IDX@GOTPAGEOFF]
Lloh44:
	ldr	w3, [x8]
	mov	w0, #0
	mov	x1, x24
	bl	_set_reg_field_value
Lloh45:
	adrp	x8, _mmSCLV_COEF_RAM_SELECT@GOTPAGE
Lloh46:
	ldr	x8, [x8, _mmSCLV_COEF_RAM_SELECT@GOTPAGEOFF]
Lloh47:
	ldr	w1, [x8]
	mov	x0, x21
	mov	w2, #0
	bl	_dm_write_reg
	ldr	w2, [x23]
Lloh48:
	adrp	x8, _SCL_C_RAM_EVEN_TAP_COEF_EN@GOTPAGE
Lloh49:
	ldr	x8, [x8, _SCL_C_RAM_EVEN_TAP_COEF_EN@GOTPAGEOFF]
Lloh50:
	ldr	w3, [x8]
	mov	w0, #0
	mov	w1, #1
	bl	_set_reg_field_value
	sxtw	x26, w22
	ldr	w1, [x19, w22, sxtw #2]
	ldr	w2, [x23]
Lloh51:
	adrp	x8, _SCL_C_RAM_EVEN_TAP_COEF@GOTPAGE
Lloh52:
	ldr	x8, [x8, _SCL_C_RAM_EVEN_TAP_COEF@GOTPAGEOFF]
Lloh53:
	ldr	w3, [x8]
	mov	w0, #0
	bl	_set_reg_field_value
	ldr	w2, [x23]
Lloh54:
	adrp	x8, _SCL_C_RAM_ODD_TAP_COEF_EN@GOTPAGE
Lloh55:
	ldr	x8, [x8, _SCL_C_RAM_ODD_TAP_COEF_EN@GOTPAGEOFF]
Lloh56:
	ldr	w3, [x8]
	tbz	w20, #0, LBB0_11
; %bb.14:                               ;   in Loop: Header=BB0_13 Depth=2
	cmp	w28, w24
	b.ne	LBB0_11
; %bb.15:                               ;   in Loop: Header=BB0_13 Depth=2
	mov	w0, #0
	mov	w1, #0
	bl	_set_reg_field_value
	mov	w8, #1
	b	LBB0_12
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.cfi_endproc
                                        ; -- End function
	.comm	_SCLV_PHASES,4,2                ; @SCLV_PHASES
	.comm	_mmDCFEV_MEM_PWR_CTRL,4,2       ; @mmDCFEV_MEM_PWR_CTRL
	.comm	_DCFEV_MEM_PWR_CTRL,4,2         ; @DCFEV_MEM_PWR_CTRL
	.comm	_SCLV_COEFF_MEM_PWR_DIS,4,2     ; @SCLV_COEFF_MEM_PWR_DIS
	.comm	_mmDCFEV_MEM_PWR_STATUS,4,2     ; @mmDCFEV_MEM_PWR_STATUS
	.comm	_DCFEV_MEM_PWR_STATUS,4,2       ; @DCFEV_MEM_PWR_STATUS
	.comm	_SCLV_COEFF_MEM_PWR_STATE,4,2   ; @SCLV_COEFF_MEM_PWR_STATE
	.comm	_SCLV_COEF_RAM_SELECT,4,2       ; @SCLV_COEF_RAM_SELECT
	.comm	_SCL_C_RAM_FILTER_TYPE,4,2      ; @SCL_C_RAM_FILTER_TYPE
	.comm	_SCL_C_RAM_PHASE,4,2            ; @SCL_C_RAM_PHASE
	.comm	_SCL_C_RAM_TAP_PAIR_IDX,4,2     ; @SCL_C_RAM_TAP_PAIR_IDX
	.comm	_mmSCLV_COEF_RAM_SELECT,4,2     ; @mmSCLV_COEF_RAM_SELECT
	.comm	_SCLV_COEF_RAM_TAP_DATA,4,2     ; @SCLV_COEF_RAM_TAP_DATA
	.comm	_SCL_C_RAM_EVEN_TAP_COEF_EN,4,2 ; @SCL_C_RAM_EVEN_TAP_COEF_EN
	.comm	_SCL_C_RAM_EVEN_TAP_COEF,4,2    ; @SCL_C_RAM_EVEN_TAP_COEF
	.comm	_SCL_C_RAM_ODD_TAP_COEF_EN,4,2  ; @SCL_C_RAM_ODD_TAP_COEF_EN
	.comm	_SCL_C_RAM_ODD_TAP_COEF,4,2     ; @SCL_C_RAM_ODD_TAP_COEF
	.comm	_mmSCLV_COEF_RAM_TAP_DATA,4,2   ; @mmSCLV_COEF_RAM_TAP_DATA
	.no_dead_strip	_program_multi_taps_filter
.subsections_via_symbols
