	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v1_0_jpeg_ring_emit_fence
_vcn_v1_0_jpeg_ring_emit_fence:         ## @vcn_v1_0_jpeg_ring_emit_fence
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r15d
	movl	%esi, %r14d
	movq	%rdi, %rbx
	movq	_AMDGPU_FENCE_FLAG_64BIT@GOTPCREL(%rip), %rax
	andl	(%rax), %ecx
	movl	%ecx, %edi
	callq	_WARN_ON
	movq	_UVD@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movq	_mmUVD_JPEG_GPCOM_DATA0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_PACKETJ_TYPE0@GOTPCREL(%rip), %r12
	movl	(%r12), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%r15d, -44(%rbp)                ## 4-byte Spill
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_JPEG_GPCOM_DATA1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r12), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	%r15d, %esi
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r12), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	%r14d, %edi
	callq	_lower_32_bits
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r12), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	%r14d, %edi
	callq	_upper_32_bits
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_JPEG_GPCOM_CMD@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r12), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$8, %esi
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movl	(%r15), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_PACKETJ_CONDITION_CHECK0@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_PACKETJ_TYPE4@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_JRBC_RB_COND_RD_TIMER@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r12), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$20972032, %esi                 ## imm = 0x1400200
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_JRBC_RB_REF_DATA@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r12), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r12), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	%r14d, %edi
	callq	_lower_32_bits
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r12), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	%r14d, %edi
	callq	_upper_32_bits
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_PACKETJ_CONDITION_CHECK3@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_PACKETJ_TYPE2@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%edi, %edi
	xorl	%esi, %esi
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$-1, %esi
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_JRBC_EXTERNAL_REG_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r12), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$16316, %esi                    ## imm = 0x3FBC
	callq	_amdgpu_ring_write
	movl	(%r12), %ecx
	xorl	%edi, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$1, %esi
	callq	_amdgpu_ring_write
	movq	_PACKETJ_TYPE7@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%edi, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	xorl	%esi, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_write              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_FENCE_FLAG_64BIT,4,2    ## @AMDGPU_FENCE_FLAG_64BIT
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_JPEG_GPCOM_DATA0,4,2     ## @mmUVD_JPEG_GPCOM_DATA0
	.comm	_PACKETJ_TYPE0,4,2              ## @PACKETJ_TYPE0
	.comm	_mmUVD_JPEG_GPCOM_DATA1,4,2     ## @mmUVD_JPEG_GPCOM_DATA1
	.comm	_mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH
	.comm	_mmUVD_JPEG_GPCOM_CMD,4,2       ## @mmUVD_JPEG_GPCOM_CMD
	.comm	_PACKETJ_CONDITION_CHECK0,4,2   ## @PACKETJ_CONDITION_CHECK0
	.comm	_PACKETJ_TYPE4,4,2              ## @PACKETJ_TYPE4
	.comm	_mmUVD_JRBC_RB_COND_RD_TIMER,4,2 ## @mmUVD_JRBC_RB_COND_RD_TIMER
	.comm	_mmUVD_JRBC_RB_REF_DATA,4,2     ## @mmUVD_JRBC_RB_REF_DATA
	.comm	_mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
	.comm	_PACKETJ_CONDITION_CHECK3,4,2   ## @PACKETJ_CONDITION_CHECK3
	.comm	_PACKETJ_TYPE2,4,2              ## @PACKETJ_TYPE2
	.comm	_mmUVD_JRBC_EXTERNAL_REG_BASE,4,2 ## @mmUVD_JRBC_EXTERNAL_REG_BASE
	.comm	_PACKETJ_TYPE7,4,2              ## @PACKETJ_TYPE7
	.no_dead_strip	_vcn_v1_0_jpeg_ring_emit_fence
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v1_0_jpeg_ring_emit_fence
_vcn_v1_0_jpeg_ring_emit_fence:         ; @vcn_v1_0_jpeg_ring_emit_fence
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x21, x2
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x8, _AMDGPU_FENCE_FLAG_64BIT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPU_FENCE_FLAG_64BIT@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	and	w0, w8, w3
	bl	_WARN_ON
Lloh3:
	adrp	x23, _UVD@GOTPAGE
Lloh4:
	ldr	x23, [x23, _UVD@GOTPAGEOFF]
	ldr	w0, [x23]
Lloh5:
	adrp	x8, _mmUVD_JPEG_GPCOM_DATA0@GOTPAGE
Lloh6:
	ldr	x8, [x8, _mmUVD_JPEG_GPCOM_DATA0@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh8:
	adrp	x22, _PACKETJ_TYPE0@GOTPAGE
Lloh9:
	ldr	x22, [x22, _PACKETJ_TYPE0@GOTPAGEOFF]
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	x1, x21
	bl	_amdgpu_ring_write
	ldr	w0, [x23]
Lloh10:
	adrp	x8, _mmUVD_JPEG_GPCOM_DATA1@GOTPAGE
Lloh11:
	ldr	x8, [x8, _mmUVD_JPEG_GPCOM_DATA1@GOTPAGEOFF]
Lloh12:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	x1, x21
	bl	_amdgpu_ring_write
	ldr	w0, [x23]
Lloh13:
	adrp	x8, _mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW@GOTPAGE
Lloh14:
	ldr	x8, [x8, _mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh15:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x20
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x23]
Lloh16:
	adrp	x8, _mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH@GOTPAGE
Lloh17:
	ldr	x8, [x8, _mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh18:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x20
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x23]
Lloh19:
	adrp	x24, _mmUVD_JPEG_GPCOM_CMD@GOTPAGE
Lloh20:
	ldr	x24, [x24, _mmUVD_JPEG_GPCOM_CMD@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #8
	bl	_amdgpu_ring_write
	ldr	w0, [x23]
	ldr	w2, [x24]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh21:
	adrp	x8, _PACKETJ_CONDITION_CHECK0@GOTPAGE
Lloh22:
	ldr	x8, [x8, _PACKETJ_CONDITION_CHECK0@GOTPAGEOFF]
Lloh23:
	ldr	w2, [x8]
Lloh24:
	adrp	x8, _PACKETJ_TYPE4@GOTPAGE
Lloh25:
	ldr	x8, [x8, _PACKETJ_TYPE4@GOTPAGEOFF]
Lloh26:
	ldr	w3, [x8]
	mov	w1, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_ring_write
	ldr	w0, [x23]
Lloh27:
	adrp	x8, _mmUVD_JRBC_RB_COND_RD_TIMER@GOTPAGE
Lloh28:
	ldr	x8, [x8, _mmUVD_JRBC_RB_COND_RD_TIMER@GOTPAGEOFF]
Lloh29:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #512
	movk	w1, #320, lsl #16
	bl	_amdgpu_ring_write
	ldr	w0, [x23]
Lloh30:
	adrp	x8, _mmUVD_JRBC_RB_REF_DATA@GOTPAGE
Lloh31:
	ldr	x8, [x8, _mmUVD_JRBC_RB_REF_DATA@GOTPAGEOFF]
Lloh32:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	x1, x21
	bl	_amdgpu_ring_write
	ldr	w0, [x23]
Lloh33:
	adrp	x8, _mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW@GOTPAGE
Lloh34:
	ldr	x8, [x8, _mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh35:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x20
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x23]
Lloh36:
	adrp	x8, _mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH@GOTPAGE
Lloh37:
	ldr	x8, [x8, _mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh38:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x20
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh39:
	adrp	x8, _PACKETJ_CONDITION_CHECK3@GOTPAGE
Lloh40:
	ldr	x8, [x8, _PACKETJ_CONDITION_CHECK3@GOTPAGEOFF]
Lloh41:
	ldr	w2, [x8]
Lloh42:
	adrp	x8, _PACKETJ_TYPE2@GOTPAGE
Lloh43:
	ldr	x8, [x8, _PACKETJ_TYPE2@GOTPAGEOFF]
Lloh44:
	ldr	w3, [x8]
	mov	w0, #0
	mov	w1, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #-1
	bl	_amdgpu_ring_write
	ldr	w0, [x23]
Lloh45:
	adrp	x8, _mmUVD_JRBC_EXTERNAL_REG_BASE@GOTPAGE
Lloh46:
	ldr	x8, [x8, _mmUVD_JRBC_EXTERNAL_REG_BASE@GOTPAGEOFF]
Lloh47:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w3, [x22]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #16316
	bl	_amdgpu_ring_write
	ldr	w3, [x22]
	mov	w0, #0
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #1
	bl	_amdgpu_ring_write
Lloh48:
	adrp	x8, _PACKETJ_TYPE7@GOTPAGE
Lloh49:
	ldr	x8, [x8, _PACKETJ_TYPE7@GOTPAGEOFF]
Lloh50:
	ldr	w3, [x8]
	mov	w0, #0
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_amdgpu_ring_write
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_FENCE_FLAG_64BIT,4,2    ; @AMDGPU_FENCE_FLAG_64BIT
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_JPEG_GPCOM_DATA0,4,2     ; @mmUVD_JPEG_GPCOM_DATA0
	.comm	_PACKETJ_TYPE0,4,2              ; @PACKETJ_TYPE0
	.comm	_mmUVD_JPEG_GPCOM_DATA1,4,2     ; @mmUVD_JPEG_GPCOM_DATA1
	.comm	_mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH
	.comm	_mmUVD_JPEG_GPCOM_CMD,4,2       ; @mmUVD_JPEG_GPCOM_CMD
	.comm	_PACKETJ_CONDITION_CHECK0,4,2   ; @PACKETJ_CONDITION_CHECK0
	.comm	_PACKETJ_TYPE4,4,2              ; @PACKETJ_TYPE4
	.comm	_mmUVD_JRBC_RB_COND_RD_TIMER,4,2 ; @mmUVD_JRBC_RB_COND_RD_TIMER
	.comm	_mmUVD_JRBC_RB_REF_DATA,4,2     ; @mmUVD_JRBC_RB_REF_DATA
	.comm	_mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
	.comm	_PACKETJ_CONDITION_CHECK3,4,2   ; @PACKETJ_CONDITION_CHECK3
	.comm	_PACKETJ_TYPE2,4,2              ; @PACKETJ_TYPE2
	.comm	_mmUVD_JRBC_EXTERNAL_REG_BASE,4,2 ; @mmUVD_JRBC_EXTERNAL_REG_BASE
	.comm	_PACKETJ_TYPE7,4,2              ; @PACKETJ_TYPE7
	.no_dead_strip	_vcn_v1_0_jpeg_ring_emit_fence
.subsections_via_symbols
