	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function uvd_v6_0_hw_init
_uvd_v6_0_hw_init:                      ## @uvd_v6_0_hw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	8(%rdi), %r15
	addq	$8, %r15
	movl	$10000, %esi                    ## imm = 0x2710
	movl	$10000, %edx                    ## imm = 0x2710
	callq	_amdgpu_asic_set_uvd_clocks
	movq	_AMD_CG_STATE_UNGATE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_uvd_v6_0_set_clockgating_state
	movq	%r14, %rdi
	movl	$1, %esi
	callq	_uvd_v6_0_enable_mgcg
	movq	%r15, %rdi
	callq	_amdgpu_ring_test_helper
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_13
## %bb.1:
	movq	%r15, %rdi
	movl	$10, %esi
	callq	_amdgpu_ring_alloc
	testl	%eax, %eax
	je	LBB0_3
## %bb.2:
	movl	%eax, %ebx
	leaq	L_.str(%rip), %rdi
	movl	%eax, %esi
	callq	_DRM_ERROR
	jmp	LBB0_13
LBB0_3:
	movq	_mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r15, %rdi
	movl	$1048575, %esi                  ## imm = 0xFFFFF
	callq	_amdgpu_ring_write
	movq	_mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r15, %rdi
	movl	$1048575, %esi                  ## imm = 0xFFFFF
	callq	_amdgpu_ring_write
	movq	_mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r15, %rdi
	movl	$1048575, %esi                  ## imm = 0xFFFFF
	callq	_amdgpu_ring_write
	movq	_mmUVD_SEMA_TIMEOUT_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r15, %rdi
	movl	$8, %esi
	callq	_amdgpu_ring_write
	movq	_mmUVD_SEMA_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r15, %rdi
	movl	$3, %esi
	callq	_amdgpu_ring_write
	movq	%r15, %rdi
	callq	_amdgpu_ring_commit
	movq	%r14, %rdi
	callq	_uvd_v6_0_enc_support
	testq	%rax, %rax
	je	LBB0_9
## %bb.4:
	cmpl	$0, (%r14)
	jle	LBB0_9
## %bb.5:
	xorl	%r15d, %r15d
	xorl	%r12d, %r12d
	.p2align	4, 0x90
LBB0_7:                                 ## =>This Inner Loop Header: Depth=1
	movq	8(%r14), %rax
	movq	(%rax), %rdi
	addq	%r15, %rdi
	callq	_amdgpu_ring_test_helper
	testl	%eax, %eax
	jne	LBB0_8
## %bb.6:                               ##   in Loop: Header=BB0_7 Depth=1
	incq	%r12
	movslq	(%r14), %rax
	addq	$4, %r15
	cmpq	%rax, %r12
	jl	LBB0_7
LBB0_9:
	movq	%r14, %rdi
	callq	_uvd_v6_0_enc_support
	testq	%rax, %rax
	je	LBB0_11
## %bb.10:
	leaq	L_.str.1(%rip), %rdi
	jmp	LBB0_12
LBB0_11:
	leaq	L_.str.2(%rip), %rdi
LBB0_12:
	callq	_DRM_INFO
	xorl	%ebx, %ebx
	jmp	LBB0_13
LBB0_8:
	movl	%eax, %ebx
LBB0_13:
	movl	%ebx, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_CG_STATE_UNGATE,4,2        ## @AMD_CG_STATE_UNGATE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"amdgpu: ring failed to lock UVD ring (%d).\n"

	.comm	_mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL,4,2 ## @mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
	.comm	_mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL,4,2 ## @mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
	.comm	_mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL,4,2 ## @mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
	.comm	_mmUVD_SEMA_TIMEOUT_STATUS,4,2  ## @mmUVD_SEMA_TIMEOUT_STATUS
	.comm	_mmUVD_SEMA_CNTL,4,2            ## @mmUVD_SEMA_CNTL
L_.str.1:                               ## @.str.1
	.asciz	"UVD and UVD ENC initialized successfully.\n"

L_.str.2:                               ## @.str.2
	.asciz	"UVD initialized successfully.\n"

	.no_dead_strip	_uvd_v6_0_hw_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function uvd_v6_0_hw_init
_uvd_v6_0_hw_init:                      ; @uvd_v6_0_hw_init
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x8, [x0, #8]
	add	x20, x8, #8
	mov	w1, #10000
	mov	w2, #10000
	bl	_amdgpu_asic_set_uvd_clocks
Lloh0:
	adrp	x8, _AMD_CG_STATE_UNGATE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMD_CG_STATE_UNGATE@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_uvd_v6_0_set_clockgating_state
	mov	x0, x19
	mov	w1, #1
	bl	_uvd_v6_0_enable_mgcg
	mov	x0, x20
	bl	_amdgpu_ring_test_helper
	mov	x21, x0
	cbnz	w0, LBB0_13
; %bb.1:
	mov	x0, x20
	mov	w1, #10
	bl	_amdgpu_ring_alloc
	cbz	w0, LBB0_3
; %bb.2:
	mov	x21, x0
Lloh3:
	adrp	x0, l_.str@PAGE
Lloh4:
	add	x0, x0, l_.str@PAGEOFF
	mov	x1, x21
	bl	_DRM_ERROR
	b	LBB0_13
LBB0_3:
Lloh5:
	adrp	x8, _mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL@GOTPAGE
Lloh6:
	ldr	x8, [x8, _mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
	mov	x0, x20
	mov	w1, #1048575
	bl	_amdgpu_ring_write
Lloh8:
	adrp	x8, _mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL@GOTPAGE
Lloh9:
	ldr	x8, [x8, _mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL@GOTPAGEOFF]
Lloh10:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
	mov	x0, x20
	mov	w1, #1048575
	bl	_amdgpu_ring_write
Lloh11:
	adrp	x8, _mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL@GOTPAGE
Lloh12:
	ldr	x8, [x8, _mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
	mov	x0, x20
	mov	w1, #1048575
	bl	_amdgpu_ring_write
Lloh14:
	adrp	x8, _mmUVD_SEMA_TIMEOUT_STATUS@GOTPAGE
Lloh15:
	ldr	x8, [x8, _mmUVD_SEMA_TIMEOUT_STATUS@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
	mov	x0, x20
	mov	w1, #8
	bl	_amdgpu_ring_write
Lloh17:
	adrp	x8, _mmUVD_SEMA_CNTL@GOTPAGE
Lloh18:
	ldr	x8, [x8, _mmUVD_SEMA_CNTL@GOTPAGEOFF]
Lloh19:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
	mov	x0, x20
	mov	w1, #3
	bl	_amdgpu_ring_write
	mov	x0, x20
	bl	_amdgpu_ring_commit
	mov	x0, x19
	bl	_uvd_v6_0_enc_support
	cbz	x0, LBB0_8
; %bb.4:
	ldr	w8, [x19]
	cmp	w8, #1
	b.lt	LBB0_8
; %bb.5:
	mov	x20, #0
	mov	x22, #0
LBB0_6:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	add	x0, x8, x20
	bl	_amdgpu_ring_test_helper
	cbnz	w0, LBB0_12
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=1
	add	x22, x22, #1
	ldrsw	x8, [x19]
	add	x20, x20, #4
	cmp	x22, x8
	b.lt	LBB0_6
LBB0_8:
	mov	x0, x19
	bl	_uvd_v6_0_enc_support
	cbz	x0, LBB0_10
; %bb.9:
Lloh20:
	adrp	x0, l_.str.1@PAGE
Lloh21:
	add	x0, x0, l_.str.1@PAGEOFF
	b	LBB0_11
LBB0_10:
Lloh22:
	adrp	x0, l_.str.2@PAGE
Lloh23:
	add	x0, x0, l_.str.2@PAGEOFF
LBB0_11:
	bl	_DRM_INFO
	mov	w21, #0
	b	LBB0_13
LBB0_12:
	mov	x21, x0
LBB0_13:
	mov	x0, x21
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpAdd	Lloh22, Lloh23
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_CG_STATE_UNGATE,4,2        ; @AMD_CG_STATE_UNGATE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"amdgpu: ring failed to lock UVD ring (%d).\n"

	.comm	_mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL,4,2 ; @mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
	.comm	_mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL,4,2 ; @mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
	.comm	_mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL,4,2 ; @mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
	.comm	_mmUVD_SEMA_TIMEOUT_STATUS,4,2  ; @mmUVD_SEMA_TIMEOUT_STATUS
	.comm	_mmUVD_SEMA_CNTL,4,2            ; @mmUVD_SEMA_CNTL
l_.str.1:                               ; @.str.1
	.asciz	"UVD and UVD ENC initialized successfully.\n"

l_.str.2:                               ; @.str.2
	.asciz	"UVD initialized successfully.\n"

	.no_dead_strip	_uvd_v6_0_hw_init
.subsections_via_symbols
