	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r100_pci_gart_disable          ## -- Begin function r100_pci_gart_disable
	.p2align	4, 0x90
_r100_pci_gart_disable:                 ## @r100_pci_gart_disable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	_RADEON_AIC_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_RADEON_DIS_OUT_OF_PCI_GART_ACCESS@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movq	_RADEON_PCIGART_TRANSLATE_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	callq	_WREG32
	movq	_RADEON_AIC_LO_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_RADEON_AIC_HI_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_AIC_CNTL,4,2            ## @RADEON_AIC_CNTL
	.comm	_RADEON_DIS_OUT_OF_PCI_GART_ACCESS,4,2 ## @RADEON_DIS_OUT_OF_PCI_GART_ACCESS
	.comm	_RADEON_PCIGART_TRANSLATE_EN,4,2 ## @RADEON_PCIGART_TRANSLATE_EN
	.comm	_RADEON_AIC_LO_ADDR,4,2         ## @RADEON_AIC_LO_ADDR
	.comm	_RADEON_AIC_HI_ADDR,4,2         ## @RADEON_AIC_HI_ADDR
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r100_pci_gart_disable          ; -- Begin function r100_pci_gart_disable
	.p2align	2
_r100_pci_gart_disable:                 ; @r100_pci_gart_disable
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
Lloh0:
	adrp	x19, _RADEON_AIC_CNTL@GOTPAGE
Lloh1:
	ldr	x19, [x19, _RADEON_AIC_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32
Lloh2:
	adrp	x8, _RADEON_DIS_OUT_OF_PCI_GART_ACCESS@GOTPAGE
Lloh3:
	ldr	x8, [x8, _RADEON_DIS_OUT_OF_PCI_GART_ACCESS@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	orr	w8, w8, w0
	ldr	w0, [x19]
Lloh5:
	adrp	x9, _RADEON_PCIGART_TRANSLATE_EN@GOTPAGE
Lloh6:
	ldr	x9, [x9, _RADEON_PCIGART_TRANSLATE_EN@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	bic	w1, w8, w9
	bl	_WREG32
Lloh8:
	adrp	x8, _RADEON_AIC_LO_ADDR@GOTPAGE
Lloh9:
	ldr	x8, [x8, _RADEON_AIC_LO_ADDR@GOTPAGEOFF]
Lloh10:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh11:
	adrp	x8, _RADEON_AIC_HI_ADDR@GOTPAGE
Lloh12:
	ldr	x8, [x8, _RADEON_AIC_HI_ADDR@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
	mov	w1, #0
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_WREG32
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_AIC_CNTL,4,2            ; @RADEON_AIC_CNTL
	.comm	_RADEON_DIS_OUT_OF_PCI_GART_ACCESS,4,2 ; @RADEON_DIS_OUT_OF_PCI_GART_ACCESS
	.comm	_RADEON_PCIGART_TRANSLATE_EN,4,2 ; @RADEON_PCIGART_TRANSLATE_EN
	.comm	_RADEON_AIC_LO_ADDR,4,2         ; @RADEON_AIC_LO_ADDR
	.comm	_RADEON_AIC_HI_ADDR,4,2         ; @RADEON_AIC_HI_ADDR
.subsections_via_symbols
