	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_intel_init_clock_gating_hooks  ## -- Begin function intel_init_clock_gating_hooks
	.p2align	4, 0x90
_intel_init_clock_gating_hooks:         ## @intel_init_clock_gating_hooks
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movl	$12, %esi
	callq	_IS_GEN
	movq	_nop_init_clock_gating@GOTPCREL(%rip), %r14
	testq	%rax, %rax
	je	LBB0_1
LBB0_42:
	movq	%r14, %rbx
	jmp	LBB0_43
LBB0_1:
	movq	%r15, %rdi
	movl	$11, %esi
	callq	_IS_GEN
	testq	%rax, %rax
	je	LBB0_3
## %bb.2:
	movq	_icl_init_clock_gating@GOTPCREL(%rip), %rbx
	jmp	LBB0_43
LBB0_3:
	movq	%r15, %rdi
	callq	_IS_CANNONLAKE
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	movq	_cnl_init_clock_gating@GOTPCREL(%rip), %rbx
	jmp	LBB0_43
LBB0_5:
	movq	%r15, %rdi
	callq	_IS_COFFEELAKE
	testq	%rax, %rax
	je	LBB0_7
## %bb.6:
	movq	_cfl_init_clock_gating@GOTPCREL(%rip), %rbx
	jmp	LBB0_43
LBB0_7:
	movq	%r15, %rdi
	callq	_IS_SKYLAKE
	testq	%rax, %rax
	je	LBB0_9
## %bb.8:
	movq	_skl_init_clock_gating@GOTPCREL(%rip), %rbx
	jmp	LBB0_43
LBB0_9:
	movq	%r15, %rdi
	callq	_IS_KABYLAKE
	testq	%rax, %rax
	je	LBB0_11
## %bb.10:
	movq	_kbl_init_clock_gating@GOTPCREL(%rip), %rbx
	jmp	LBB0_43
LBB0_11:
	movq	%r15, %rdi
	callq	_IS_BROXTON
	testq	%rax, %rax
	je	LBB0_13
## %bb.12:
	movq	_bxt_init_clock_gating@GOTPCREL(%rip), %rbx
	jmp	LBB0_43
LBB0_13:
	movq	%r15, %rdi
	callq	_IS_GEMINILAKE
	testq	%rax, %rax
	je	LBB0_15
## %bb.14:
	movq	_glk_init_clock_gating@GOTPCREL(%rip), %rbx
	jmp	LBB0_43
LBB0_15:
	movq	%r15, %rdi
	callq	_IS_BROADWELL
	testq	%rax, %rax
	je	LBB0_17
## %bb.16:
	movq	_bdw_init_clock_gating@GOTPCREL(%rip), %rbx
	jmp	LBB0_43
LBB0_17:
	movq	%r15, %rdi
	callq	_IS_CHERRYVIEW
	testq	%rax, %rax
	je	LBB0_19
## %bb.18:
	movq	_chv_init_clock_gating@GOTPCREL(%rip), %rbx
	jmp	LBB0_43
LBB0_19:
	movq	%r15, %rdi
	callq	_IS_HASWELL
	testq	%rax, %rax
	je	LBB0_21
## %bb.20:
	movq	_hsw_init_clock_gating@GOTPCREL(%rip), %rbx
	jmp	LBB0_43
LBB0_21:
	movq	%r15, %rdi
	callq	_IS_IVYBRIDGE
	testq	%rax, %rax
	je	LBB0_23
## %bb.22:
	movq	_ivb_init_clock_gating@GOTPCREL(%rip), %rbx
	jmp	LBB0_43
LBB0_23:
	movq	%r15, %rdi
	callq	_IS_VALLEYVIEW
	testq	%rax, %rax
	je	LBB0_25
## %bb.24:
	movq	_vlv_init_clock_gating@GOTPCREL(%rip), %rbx
	jmp	LBB0_43
LBB0_25:
	movq	%r15, %rdi
	movl	$6, %esi
	callq	_IS_GEN
	testq	%rax, %rax
	je	LBB0_27
## %bb.26:
	movq	_gen6_init_clock_gating@GOTPCREL(%rip), %rbx
	jmp	LBB0_43
LBB0_27:
	movq	%r15, %rdi
	movl	$5, %esi
	callq	_IS_GEN
	testq	%rax, %rax
	je	LBB0_29
## %bb.28:
	movq	_ilk_init_clock_gating@GOTPCREL(%rip), %rbx
	jmp	LBB0_43
LBB0_29:
	movq	%r15, %rdi
	callq	_IS_G4X
	testq	%rax, %rax
	je	LBB0_31
## %bb.30:
	movq	_g4x_init_clock_gating@GOTPCREL(%rip), %rbx
	jmp	LBB0_43
LBB0_31:
	movq	%r15, %rdi
	callq	_IS_I965GM
	testq	%rax, %rax
	je	LBB0_33
## %bb.32:
	movq	_i965gm_init_clock_gating@GOTPCREL(%rip), %rbx
	jmp	LBB0_43
LBB0_33:
	movq	%r15, %rdi
	callq	_IS_I965G
	testq	%rax, %rax
	je	LBB0_35
## %bb.34:
	movq	_i965g_init_clock_gating@GOTPCREL(%rip), %rbx
	jmp	LBB0_43
LBB0_35:
	movq	%r15, %rdi
	movl	$3, %esi
	callq	_IS_GEN
	testq	%rax, %rax
	je	LBB0_37
## %bb.36:
	movq	_gen3_init_clock_gating@GOTPCREL(%rip), %rbx
	jmp	LBB0_43
LBB0_37:
	movq	%r15, %rdi
	callq	_IS_I85X
	movq	_i85x_init_clock_gating@GOTPCREL(%rip), %rbx
	testq	%rax, %rax
	jne	LBB0_43
## %bb.38:
	movq	%r15, %rdi
	callq	_IS_I865G
	testq	%rax, %rax
	jne	LBB0_43
## %bb.39:
	movq	%r15, %rdi
	movl	$2, %esi
	callq	_IS_GEN
	testq	%rax, %rax
	je	LBB0_41
## %bb.40:
	movq	_i830_init_clock_gating@GOTPCREL(%rip), %rbx
LBB0_43:
	movq	(%rbx), %rax
	movq	%rax, (%r15)
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_41:
	movq	%r15, %rdi
	callq	_INTEL_DEVID
	movl	%eax, %edi
	callq	_MISSING_CASE
	jmp	LBB0_42
	.cfi_endproc
                                        ## -- End function
	.comm	_nop_init_clock_gating,8,3      ## @nop_init_clock_gating
	.comm	_icl_init_clock_gating,8,3      ## @icl_init_clock_gating
	.comm	_cnl_init_clock_gating,8,3      ## @cnl_init_clock_gating
	.comm	_cfl_init_clock_gating,8,3      ## @cfl_init_clock_gating
	.comm	_skl_init_clock_gating,8,3      ## @skl_init_clock_gating
	.comm	_kbl_init_clock_gating,8,3      ## @kbl_init_clock_gating
	.comm	_bxt_init_clock_gating,8,3      ## @bxt_init_clock_gating
	.comm	_glk_init_clock_gating,8,3      ## @glk_init_clock_gating
	.comm	_bdw_init_clock_gating,8,3      ## @bdw_init_clock_gating
	.comm	_chv_init_clock_gating,8,3      ## @chv_init_clock_gating
	.comm	_hsw_init_clock_gating,8,3      ## @hsw_init_clock_gating
	.comm	_ivb_init_clock_gating,8,3      ## @ivb_init_clock_gating
	.comm	_vlv_init_clock_gating,8,3      ## @vlv_init_clock_gating
	.comm	_gen6_init_clock_gating,8,3     ## @gen6_init_clock_gating
	.comm	_ilk_init_clock_gating,8,3      ## @ilk_init_clock_gating
	.comm	_g4x_init_clock_gating,8,3      ## @g4x_init_clock_gating
	.comm	_i965gm_init_clock_gating,8,3   ## @i965gm_init_clock_gating
	.comm	_i965g_init_clock_gating,8,3    ## @i965g_init_clock_gating
	.comm	_gen3_init_clock_gating,8,3     ## @gen3_init_clock_gating
	.comm	_i85x_init_clock_gating,8,3     ## @i85x_init_clock_gating
	.comm	_i830_init_clock_gating,8,3     ## @i830_init_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_intel_init_clock_gating_hooks  ; -- Begin function intel_init_clock_gating_hooks
	.p2align	2
_intel_init_clock_gating_hooks:         ; @intel_init_clock_gating_hooks
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	mov	w1, #12
	bl	_IS_GEN
	cbz	x0, LBB0_2
LBB0_1:
Lloh0:
	adrp	x8, _nop_init_clock_gating@GOTPAGE
Lloh1:
	ldr	x8, [x8, _nop_init_clock_gating@GOTPAGEOFF]
	b	LBB0_41
LBB0_2:
	mov	x0, x19
	mov	w1, #11
	bl	_IS_GEN
	cbz	x0, LBB0_4
; %bb.3:
Lloh2:
	adrp	x8, _icl_init_clock_gating@GOTPAGE
Lloh3:
	ldr	x8, [x8, _icl_init_clock_gating@GOTPAGEOFF]
	b	LBB0_41
LBB0_4:
	mov	x0, x19
	bl	_IS_CANNONLAKE
	cbz	x0, LBB0_6
; %bb.5:
Lloh4:
	adrp	x8, _cnl_init_clock_gating@GOTPAGE
Lloh5:
	ldr	x8, [x8, _cnl_init_clock_gating@GOTPAGEOFF]
	b	LBB0_41
LBB0_6:
	mov	x0, x19
	bl	_IS_COFFEELAKE
	cbz	x0, LBB0_8
; %bb.7:
Lloh6:
	adrp	x8, _cfl_init_clock_gating@GOTPAGE
Lloh7:
	ldr	x8, [x8, _cfl_init_clock_gating@GOTPAGEOFF]
	b	LBB0_41
LBB0_8:
	mov	x0, x19
	bl	_IS_SKYLAKE
	cbz	x0, LBB0_10
; %bb.9:
Lloh8:
	adrp	x8, _skl_init_clock_gating@GOTPAGE
Lloh9:
	ldr	x8, [x8, _skl_init_clock_gating@GOTPAGEOFF]
	b	LBB0_41
LBB0_10:
	mov	x0, x19
	bl	_IS_KABYLAKE
	cbz	x0, LBB0_12
; %bb.11:
Lloh10:
	adrp	x8, _kbl_init_clock_gating@GOTPAGE
Lloh11:
	ldr	x8, [x8, _kbl_init_clock_gating@GOTPAGEOFF]
	b	LBB0_41
LBB0_12:
	mov	x0, x19
	bl	_IS_BROXTON
	cbz	x0, LBB0_14
; %bb.13:
Lloh12:
	adrp	x8, _bxt_init_clock_gating@GOTPAGE
Lloh13:
	ldr	x8, [x8, _bxt_init_clock_gating@GOTPAGEOFF]
	b	LBB0_41
LBB0_14:
	mov	x0, x19
	bl	_IS_GEMINILAKE
	cbz	x0, LBB0_16
; %bb.15:
Lloh14:
	adrp	x8, _glk_init_clock_gating@GOTPAGE
Lloh15:
	ldr	x8, [x8, _glk_init_clock_gating@GOTPAGEOFF]
	b	LBB0_41
LBB0_16:
	mov	x0, x19
	bl	_IS_BROADWELL
	cbz	x0, LBB0_18
; %bb.17:
Lloh16:
	adrp	x8, _bdw_init_clock_gating@GOTPAGE
Lloh17:
	ldr	x8, [x8, _bdw_init_clock_gating@GOTPAGEOFF]
	b	LBB0_41
LBB0_18:
	mov	x0, x19
	bl	_IS_CHERRYVIEW
	cbz	x0, LBB0_20
; %bb.19:
Lloh18:
	adrp	x8, _chv_init_clock_gating@GOTPAGE
Lloh19:
	ldr	x8, [x8, _chv_init_clock_gating@GOTPAGEOFF]
	b	LBB0_41
LBB0_20:
	mov	x0, x19
	bl	_IS_HASWELL
	cbz	x0, LBB0_22
; %bb.21:
Lloh20:
	adrp	x8, _hsw_init_clock_gating@GOTPAGE
Lloh21:
	ldr	x8, [x8, _hsw_init_clock_gating@GOTPAGEOFF]
	b	LBB0_41
LBB0_22:
	mov	x0, x19
	bl	_IS_IVYBRIDGE
	cbz	x0, LBB0_24
; %bb.23:
Lloh22:
	adrp	x8, _ivb_init_clock_gating@GOTPAGE
Lloh23:
	ldr	x8, [x8, _ivb_init_clock_gating@GOTPAGEOFF]
	b	LBB0_41
LBB0_24:
	mov	x0, x19
	bl	_IS_VALLEYVIEW
	cbz	x0, LBB0_26
; %bb.25:
Lloh24:
	adrp	x8, _vlv_init_clock_gating@GOTPAGE
Lloh25:
	ldr	x8, [x8, _vlv_init_clock_gating@GOTPAGEOFF]
	b	LBB0_41
LBB0_26:
	mov	x0, x19
	mov	w1, #6
	bl	_IS_GEN
	cbz	x0, LBB0_28
; %bb.27:
Lloh26:
	adrp	x8, _gen6_init_clock_gating@GOTPAGE
Lloh27:
	ldr	x8, [x8, _gen6_init_clock_gating@GOTPAGEOFF]
	b	LBB0_41
LBB0_28:
	mov	x0, x19
	mov	w1, #5
	bl	_IS_GEN
	cbz	x0, LBB0_30
; %bb.29:
Lloh28:
	adrp	x8, _ilk_init_clock_gating@GOTPAGE
Lloh29:
	ldr	x8, [x8, _ilk_init_clock_gating@GOTPAGEOFF]
	b	LBB0_41
LBB0_30:
	mov	x0, x19
	bl	_IS_G4X
	cbz	x0, LBB0_32
; %bb.31:
Lloh30:
	adrp	x8, _g4x_init_clock_gating@GOTPAGE
Lloh31:
	ldr	x8, [x8, _g4x_init_clock_gating@GOTPAGEOFF]
	b	LBB0_41
LBB0_32:
	mov	x0, x19
	bl	_IS_I965GM
	cbz	x0, LBB0_34
; %bb.33:
Lloh32:
	adrp	x8, _i965gm_init_clock_gating@GOTPAGE
Lloh33:
	ldr	x8, [x8, _i965gm_init_clock_gating@GOTPAGEOFF]
	b	LBB0_41
LBB0_34:
	mov	x0, x19
	bl	_IS_I965G
	cbz	x0, LBB0_36
; %bb.35:
Lloh34:
	adrp	x8, _i965g_init_clock_gating@GOTPAGE
Lloh35:
	ldr	x8, [x8, _i965g_init_clock_gating@GOTPAGEOFF]
	b	LBB0_41
LBB0_36:
	mov	x0, x19
	mov	w1, #3
	bl	_IS_GEN
	cbz	x0, LBB0_38
; %bb.37:
Lloh36:
	adrp	x8, _gen3_init_clock_gating@GOTPAGE
Lloh37:
	ldr	x8, [x8, _gen3_init_clock_gating@GOTPAGEOFF]
	b	LBB0_41
LBB0_38:
	mov	x0, x19
	bl	_IS_I85X
	cbnz	x0, LBB0_40
; %bb.39:
	mov	x0, x19
	bl	_IS_I865G
	cbz	x0, LBB0_42
LBB0_40:
Lloh38:
	adrp	x8, _i85x_init_clock_gating@GOTPAGE
Lloh39:
	ldr	x8, [x8, _i85x_init_clock_gating@GOTPAGEOFF]
LBB0_41:
	ldr	x8, [x8]
	str	x8, [x19]
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_42:
	mov	x0, x19
	mov	w1, #2
	bl	_IS_GEN
	cbz	x0, LBB0_44
; %bb.43:
Lloh40:
	adrp	x8, _i830_init_clock_gating@GOTPAGE
Lloh41:
	ldr	x8, [x8, _i830_init_clock_gating@GOTPAGEOFF]
	b	LBB0_41
LBB0_44:
	mov	x0, x19
	bl	_INTEL_DEVID
	bl	_MISSING_CASE
	b	LBB0_1
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh40, Lloh41
	.cfi_endproc
                                        ; -- End function
	.comm	_nop_init_clock_gating,8,3      ; @nop_init_clock_gating
	.comm	_icl_init_clock_gating,8,3      ; @icl_init_clock_gating
	.comm	_cnl_init_clock_gating,8,3      ; @cnl_init_clock_gating
	.comm	_cfl_init_clock_gating,8,3      ; @cfl_init_clock_gating
	.comm	_skl_init_clock_gating,8,3      ; @skl_init_clock_gating
	.comm	_kbl_init_clock_gating,8,3      ; @kbl_init_clock_gating
	.comm	_bxt_init_clock_gating,8,3      ; @bxt_init_clock_gating
	.comm	_glk_init_clock_gating,8,3      ; @glk_init_clock_gating
	.comm	_bdw_init_clock_gating,8,3      ; @bdw_init_clock_gating
	.comm	_chv_init_clock_gating,8,3      ; @chv_init_clock_gating
	.comm	_hsw_init_clock_gating,8,3      ; @hsw_init_clock_gating
	.comm	_ivb_init_clock_gating,8,3      ; @ivb_init_clock_gating
	.comm	_vlv_init_clock_gating,8,3      ; @vlv_init_clock_gating
	.comm	_gen6_init_clock_gating,8,3     ; @gen6_init_clock_gating
	.comm	_ilk_init_clock_gating,8,3      ; @ilk_init_clock_gating
	.comm	_g4x_init_clock_gating,8,3      ; @g4x_init_clock_gating
	.comm	_i965gm_init_clock_gating,8,3   ; @i965gm_init_clock_gating
	.comm	_i965g_init_clock_gating,8,3    ; @i965g_init_clock_gating
	.comm	_gen3_init_clock_gating,8,3     ; @gen3_init_clock_gating
	.comm	_i85x_init_clock_gating,8,3     ; @i85x_init_clock_gating
	.comm	_i830_init_clock_gating,8,3     ; @i830_init_clock_gating
.subsections_via_symbols
