	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_vm_update_ptes
_radeon_vm_update_ptes:                 ## @radeon_vm_update_ptes
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$72, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, -72(%rbp)                 ## 8-byte Spill
	movq	%rsi, -112(%rbp)                ## 8-byte Spill
	movq	%rdi, -64(%rbp)                 ## 8-byte Spill
	xorl	%r14d, %r14d
	cmpq	%r8, %rcx
	jae	LBB0_12
## %bb.1:
	movq	%r8, %rbx
	movq	%rcx, %r15
	movq	_RADEON_VM_PTE_COUNT@GOTPCREL(%rip), %rax
	movslq	(%rax), %rax
	decq	%rax
	movq	%rax, -96(%rbp)                 ## 8-byte Spill
	notq	%rax
	movq	%rax, -88(%rbp)                 ## 8-byte Spill
	xorl	%r12d, %r12d
	movq	$-1, -48(%rbp)                  ## 8-byte Folded Spill
	movq	$-1, -56(%rbp)                  ## 8-byte Folded Spill
	movq	%r8, -104(%rbp)                 ## 8-byte Spill
	jmp	LBB0_2
	.p2align	4, 0x90
LBB0_8:                                 ##   in Loop: Header=BB0_2 Depth=1
	addl	%ebx, %r12d
	movq	-80(%rbp), %r9                  ## 8-byte Reload
LBB0_9:                                 ##   in Loop: Header=BB0_2 Depth=1
	movl	%ebx, %eax
	addq	%rax, %r15
	movq	_RADEON_GPU_PAGE_SIZE@GOTPCREL(%rip), %rax
	imull	(%rax), %ebx
	addq	%rbx, %r9
	movq	-104(%rbp), %rbx                ## 8-byte Reload
	cmpq	%rbx, %r15
	jae	LBB0_10
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r9, -80(%rbp)                  ## 8-byte Spill
	movq	_radeon_vm_block_size@GOTPCREL(%rip), %rax
	movzbl	(%rax), %ecx
	movq	%r15, %rax
	shrq	%cl, %rax
	movq	-112(%rbp), %rcx                ## 8-byte Reload
	movq	(%rcx), %rcx
	movq	(%rcx,%rax,8), %r13
	movl	(%r13), %edx
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	movq	-72(%rbp), %rsi                 ## 8-byte Reload
	movl	$1, %ecx
	callq	_radeon_sync_resv
	movl	(%r13), %edi
	movl	$1, %esi
	callq	_dma_resv_reserve_shared
	testl	%eax, %eax
	jne	LBB0_3
## %bb.4:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	%r15, %rax
	xorq	%rbx, %rax
	movl	%ebx, %ecx
	subl	%r15d, %ecx
	movq	_RADEON_VM_PTE_COUNT@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	movq	-96(%rbp), %r14                 ## 8-byte Reload
	movl	%r14d, %edx
	andl	%r15d, %edx
	subl	%edx, %ebx
	testq	%rax, -88(%rbp)                 ## 8-byte Folded Reload
	cmovel	%ecx, %ebx
	movq	%r13, %rdi
	callq	_radeon_bo_gpu_offset
	movq	%r15, %rcx
	andq	%r14, %rcx
	leaq	(%rax,%rcx,8), %r14
	leal	(,%r12,8), %ecx
	addq	-48(%rbp), %rcx                 ## 8-byte Folded Reload
	cmpq	%r14, %rcx
	je	LBB0_8
## %bb.5:                               ##   in Loop: Header=BB0_2 Depth=1
	testl	%r12d, %r12d
	je	LBB0_6
## %bb.7:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	movq	-72(%rbp), %rsi                 ## 8-byte Reload
	movq	-48(%rbp), %rdx                 ## 8-byte Reload
	movq	-56(%rbp), %r8                  ## 8-byte Reload
	movl	16(%rbp), %r9d
	callq	_radeon_vm_frag_ptes
LBB0_6:                                 ##   in Loop: Header=BB0_2 Depth=1
	movq	-80(%rbp), %r9                  ## 8-byte Reload
	movq	%r9, -56(%rbp)                  ## 8-byte Spill
	movl	%ebx, %r12d
	movq	%r14, -48(%rbp)                 ## 8-byte Spill
	jmp	LBB0_9
LBB0_3:
	movl	%eax, %r14d
	jmp	LBB0_12
LBB0_10:
	xorl	%r14d, %r14d
	testl	%r12d, %r12d
	je	LBB0_12
## %bb.11:
	shll	$3, %r12d
	movq	-48(%rbp), %rdx                 ## 8-byte Reload
	addq	%rdx, %r12
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	movq	-72(%rbp), %rsi                 ## 8-byte Reload
	movq	%r12, %rcx
	movq	-56(%rbp), %r8                  ## 8-byte Reload
	movl	16(%rbp), %r9d
	callq	_radeon_vm_frag_ptes
LBB0_12:
	movl	%r14d, %eax
	addq	$72, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_VM_PTE_COUNT,4,2        ## @RADEON_VM_PTE_COUNT
	.comm	_radeon_vm_block_size,8,3       ## @radeon_vm_block_size
	.comm	_RADEON_GPU_PAGE_SIZE,4,2       ## @RADEON_GPU_PAGE_SIZE
	.no_dead_strip	_radeon_vm_update_ptes
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_vm_update_ptes
_radeon_vm_update_ptes:                 ; @radeon_vm_update_ptes
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #128
	.cfi_def_cfa_offset 128
	stp	x28, x27, [sp, #32]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #48]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #64]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #80]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #96]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #112]            ; 16-byte Folded Spill
	add	x29, sp, #112
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	str	w6, [sp, #4]                    ; 4-byte Folded Spill
	str	x1, [sp, #24]                   ; 8-byte Folded Spill
	cmp	x3, x4
	b.hs	LBB0_11
; %bb.1:
	mov	x22, x5
	mov	x23, x4
	mov	x24, x3
	mov	x20, x2
	mov	x21, x0
	mov	w25, #0
Lloh0:
	adrp	x8, _RADEON_VM_PTE_COUNT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_VM_PTE_COUNT@GOTPAGEOFF]
Lloh2:
	ldrsw	x8, [x8]
	sub	x19, x8, #1
	mvn	x8, x19
	str	x8, [sp, #16]                   ; 8-byte Folded Spill
	mov	x26, #-1
	mov	x8, #-1
	str	x8, [sp, #8]                    ; 8-byte Folded Spill
	b	LBB0_4
LBB0_2:                                 ;   in Loop: Header=BB0_4 Depth=1
	add	w25, w27, w25
LBB0_3:                                 ;   in Loop: Header=BB0_4 Depth=1
	add	x24, x24, w27, uxtw
Lloh3:
	adrp	x8, _RADEON_GPU_PAGE_SIZE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _RADEON_GPU_PAGE_SIZE@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	mul	w8, w8, w27
	add	x22, x22, x8
	cmp	x24, x23
	b.hs	LBB0_9
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
Lloh6:
	adrp	x8, _radeon_vm_block_size@GOTPAGE
Lloh7:
	ldr	x8, [x8, _radeon_vm_block_size@GOTPAGEOFF]
Lloh8:
	ldr	x8, [x8]
	lsr	x8, x24, x8
	ldr	x9, [sp, #24]                   ; 8-byte Folded Reload
	ldr	x9, [x9]
	ldr	x28, [x9, x8, lsl #3]
	ldr	w2, [x28]
	mov	x0, x21
	mov	x1, x20
	mov	w3, #1
	bl	_radeon_sync_resv
	ldr	w0, [x28]
	mov	w1, #1
	bl	_dma_resv_reserve_shared
	cbnz	w0, LBB0_12
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	eor	x8, x24, x23
	sub	w9, w23, w24
Lloh9:
	adrp	x10, _RADEON_VM_PTE_COUNT@GOTPAGE
Lloh10:
	ldr	x10, [x10, _RADEON_VM_PTE_COUNT@GOTPAGEOFF]
Lloh11:
	ldr	w10, [x10]
	and	w11, w19, w24
	sub	w10, w10, w11
	ldr	x11, [sp, #16]                  ; 8-byte Folded Reload
	tst	x8, x11
	csel	w27, w9, w10, eq
	mov	x0, x28
	bl	_radeon_bo_gpu_offset
	and	x8, x24, x19
	add	x28, x0, x8, lsl #3
	lsl	w8, w25, #3
	add	x3, x26, x8
	cmp	x3, x28
	b.eq	LBB0_2
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=1
	cbz	w25, LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_4 Depth=1
	mov	x0, x21
	mov	x1, x20
	mov	x2, x26
	ldr	x4, [sp, #8]                    ; 8-byte Folded Reload
	ldr	w5, [sp, #4]                    ; 4-byte Folded Reload
	bl	_radeon_vm_frag_ptes
LBB0_8:                                 ;   in Loop: Header=BB0_4 Depth=1
	str	x22, [sp, #8]                   ; 8-byte Folded Spill
	mov	x25, x27
	mov	x26, x28
	b	LBB0_3
LBB0_9:
	cbz	w25, LBB0_11
; %bb.10:
	lsl	w8, w25, #3
	add	x3, x26, x8
	mov	x0, x21
	mov	x1, x20
	mov	x2, x26
	ldr	x4, [sp, #8]                    ; 8-byte Folded Reload
	ldr	w5, [sp, #4]                    ; 4-byte Folded Reload
	bl	_radeon_vm_frag_ptes
LBB0_11:
	mov	w0, #0
LBB0_12:
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_VM_PTE_COUNT,4,2        ; @RADEON_VM_PTE_COUNT
	.comm	_radeon_vm_block_size,8,3       ; @radeon_vm_block_size
	.comm	_RADEON_GPU_PAGE_SIZE,4,2       ; @RADEON_GPU_PAGE_SIZE
	.no_dead_strip	_radeon_vm_update_ptes
.subsections_via_symbols
