	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vce_v3_0_sw_init
_vce_v3_0_sw_init:                      ## @vce_v3_0_sw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	_AMDGPU_IRQ_CLIENTID_LEGACY@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_VISLANDS30_IV_SRCID_VCE_TRAP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	leaq	12(%rdi), %r14
	movq	%r14, %rcx
	callq	_amdgpu_irq_add_id
	testl	%eax, %eax
	jne	LBB0_9
## %bb.1:
	movq	_VCE_V3_0_FW_SIZE@GOTPCREL(%rip), %rax
	movq	_VCE_V3_0_STACK_SIZE@GOTPCREL(%rip), %rcx
	movslq	(%rcx), %rcx
	movq	_VCE_V3_0_DATA_SIZE@GOTPCREL(%rip), %rdx
	movslq	(%rdx), %rsi
	addq	%rcx, %rsi
	addq	%rsi, %rsi
	addq	(%rax), %rsi
	movq	%r12, %rdi
	callq	_amdgpu_vce_sw_init
	testl	%eax, %eax
	jne	LBB0_9
## %bb.2:
	movq	(%r12), %rax
	movq	_FW_52_8_3@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_4
## %bb.3:
	movl	$2, 8(%r12)
LBB0_4:
	movq	%r12, %rdi
	callq	_amdgpu_vce_resume
	testl	%eax, %eax
	je	LBB0_5
LBB0_9:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_5:
	cmpl	$0, 8(%r12)
	jle	LBB0_10
## %bb.6:
	xorl	%r15d, %r15d
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_8:                                 ## =>This Inner Loop Header: Depth=1
	movq	16(%r12), %r13
	movl	(%r13,%rbx,4), %edi
	addq	%r15, %r13
	leaq	L_.str(%rip), %rsi
	movl	%ebx, %edx
	callq	_sprintf
	movq	%r12, %rdi
	movq	%r13, %rsi
	movl	$512, %edx                      ## imm = 0x200
	movq	%r14, %rcx
	xorl	%r8d, %r8d
	callq	_amdgpu_ring_init
	testl	%eax, %eax
	jne	LBB0_9
## %bb.7:                               ##   in Loop: Header=BB0_8 Depth=1
	incq	%rbx
	movslq	8(%r12), %rax
	addq	$4, %r15
	cmpq	%rax, %rbx
	jl	LBB0_8
LBB0_10:
	movq	%r12, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_vce_entity_init         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_IRQ_CLIENTID_LEGACY,4,2 ## @AMDGPU_IRQ_CLIENTID_LEGACY
	.comm	_VISLANDS30_IV_SRCID_VCE_TRAP,4,2 ## @VISLANDS30_IV_SRCID_VCE_TRAP
	.comm	_VCE_V3_0_FW_SIZE,8,3           ## @VCE_V3_0_FW_SIZE
	.comm	_VCE_V3_0_STACK_SIZE,4,2        ## @VCE_V3_0_STACK_SIZE
	.comm	_VCE_V3_0_DATA_SIZE,4,2         ## @VCE_V3_0_DATA_SIZE
	.comm	_FW_52_8_3,8,3                  ## @FW_52_8_3
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"vce%d"

	.no_dead_strip	_vce_v3_0_sw_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vce_v3_0_sw_init
_vce_v3_0_sw_init:                      ; @vce_v3_0_sw_init
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x8, _AMDGPU_IRQ_CLIENTID_LEGACY@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPU_IRQ_CLIENTID_LEGACY@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
Lloh3:
	adrp	x8, _VISLANDS30_IV_SRCID_VCE_TRAP@GOTPAGE
Lloh4:
	ldr	x8, [x8, _VISLANDS30_IV_SRCID_VCE_TRAP@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	add	x20, x0, #12
	mov	x3, x20
	bl	_amdgpu_irq_add_id
	cbnz	w0, LBB0_5
; %bb.1:
Lloh6:
	adrp	x8, _VCE_V3_0_FW_SIZE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _VCE_V3_0_FW_SIZE@GOTPAGEOFF]
Lloh8:
	ldr	x8, [x8]
Lloh9:
	adrp	x9, _VCE_V3_0_STACK_SIZE@GOTPAGE
Lloh10:
	ldr	x9, [x9, _VCE_V3_0_STACK_SIZE@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
Lloh12:
	adrp	x10, _VCE_V3_0_DATA_SIZE@GOTPAGE
Lloh13:
	ldr	x10, [x10, _VCE_V3_0_DATA_SIZE@GOTPAGEOFF]
Lloh14:
	ldr	w10, [x10]
	add	w9, w10, w9
	lsl	w9, w9, #1
	add	x1, x8, w9, sxtw
	mov	x0, x19
	bl	_amdgpu_vce_sw_init
	cbnz	w0, LBB0_5
; %bb.2:
	ldr	x8, [x19]
Lloh15:
	adrp	x9, _FW_52_8_3@GOTPAGE
Lloh16:
	ldr	x9, [x9, _FW_52_8_3@GOTPAGEOFF]
Lloh17:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_4
; %bb.3:
	mov	w8, #2
	str	w8, [x19, #8]
LBB0_4:
	mov	x0, x19
	bl	_amdgpu_vce_resume
	cbz	w0, LBB0_6
LBB0_5:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_6:
	ldr	w8, [x19, #8]
	cmp	w8, #1
	b.lt	LBB0_10
; %bb.7:
	mov	x24, #0
	mov	x21, #0
Lloh18:
	adrp	x22, l_.str@PAGE
Lloh19:
	add	x22, x22, l_.str@PAGEOFF
LBB0_8:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #16]
	add	x23, x8, x24
	ldr	w0, [x8, x21, lsl #2]
	mov	x1, x22
	mov	x2, x21
	bl	_sprintf
	mov	x0, x19
	mov	x1, x23
	mov	w2, #512
	mov	x3, x20
	mov	w4, #0
	bl	_amdgpu_ring_init
	cbnz	w0, LBB0_5
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=1
	add	x21, x21, #1
	ldrsw	x8, [x19, #8]
	add	x24, x24, #4
	cmp	x21, x8
	b.lt	LBB0_8
LBB0_10:
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_amdgpu_vce_entity_init
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpAdd	Lloh18, Lloh19
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_IRQ_CLIENTID_LEGACY,4,2 ; @AMDGPU_IRQ_CLIENTID_LEGACY
	.comm	_VISLANDS30_IV_SRCID_VCE_TRAP,4,2 ; @VISLANDS30_IV_SRCID_VCE_TRAP
	.comm	_VCE_V3_0_FW_SIZE,8,3           ; @VCE_V3_0_FW_SIZE
	.comm	_VCE_V3_0_STACK_SIZE,4,2        ; @VCE_V3_0_STACK_SIZE
	.comm	_VCE_V3_0_DATA_SIZE,4,2         ; @VCE_V3_0_DATA_SIZE
	.comm	_FW_52_8_3,8,3                  ; @FW_52_8_3
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"vce%d"

	.no_dead_strip	_vce_v3_0_sw_init
.subsections_via_symbols
