	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v2_0_disable_clock_gating
_vcn_v2_0_disable_clock_gating:         ## @vcn_v2_0_disable_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	_VCN@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movq	_mmUVD_CGC_CTRL@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_AMD_CG_SUPPORT_VCN_MGCG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, (%rbx)
	je	LBB0_2
## %bb.1:
	movq	_UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	btsl	%ecx, %eax
	jmp	LBB0_3
LBB0_2:
	movq	_UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%ecx, %eax
LBB0_3:
	movq	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %dl
	movq	_UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$4, %ebx
	shll	%cl, %ebx
	btsl	%edx, %eax
	orl	%eax, %ebx
	movl	(%r14), %edi
	movl	(%r15), %edx
	xorl	%esi, %esi
	movl	%ebx, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_CGC_GATE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_UVD_CGC_GATE__SYS_MASK@GOTPCREL(%rip), %rdx
	movq	_UVD_CGC_GATE__UDEC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__MPEG2_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__REGS_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__RBC_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__LMI_MC_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__LMI_UMC_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__IDCT_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__MPRD_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__MPC_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__LBSI_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__LRBBM_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__UDEC_RE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__UDEC_CM_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__UDEC_IT_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__UDEC_DB_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__UDEC_MP_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__WCB_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__VCPU_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_GATE__SCPU_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movl	(%r14), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movl	(%r15), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPCREL(%rip), %rdx
	movq	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__SYS_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__REGS_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__RBC_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__MPC_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__WCB_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_CGC_CTRL__SCPU_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movl	(%r14), %edi
	movl	(%r15), %edx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_SUVD_CGC_GATE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_UVD_SUVD_CGC_GATE__SRE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SIT_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SMP_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SCM_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SDB_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SRE_H264_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SRE_HEVC_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SIT_H264_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SIT_HEVC_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SCM_H264_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SCM_HEVC_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SDB_H264_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SDB_HEVC_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SCLR_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__UVD_SC_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__ENT_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SITE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SRE_VP9_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SCM_VP9_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__SDB_VP9_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_SUVD_CGC_GATE__IME_HEVC_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r14), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_SUVD_CGC_CTRL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_UVD_SUVD_CGC_CTRL__SRE_MODE_MASK@GOTPCREL(%rip), %rdx
	movq	_UVD_SUVD_CGC_CTRL__SIT_MODE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rdx), %ecx
	movq	_UVD_SUVD_CGC_CTRL__SMP_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_SUVD_CGC_CTRL__SCM_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_SUVD_CGC_CTRL__SDB_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_SUVD_CGC_CTRL__ENT_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_SUVD_CGC_CTRL__IME_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_UVD_SUVD_CGC_CTRL__SITE_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movl	(%r14), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_SOC15                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_VCN,4,2                        ## @VCN
	.comm	_mmUVD_CGC_CTRL,4,2             ## @mmUVD_CGC_CTRL
	.comm	_AMD_CG_SUPPORT_VCN_MGCG,4,2    ## @AMD_CG_SUPPORT_VCN_MGCG
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT,4,2 ## @UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK,4,2 ## @UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK
	.comm	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT,4,2 ## @UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
	.comm	_UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT,4,2 ## @UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT
	.comm	_mmUVD_CGC_GATE,4,2             ## @mmUVD_CGC_GATE
	.comm	_UVD_CGC_GATE__SYS_MASK,4,2     ## @UVD_CGC_GATE__SYS_MASK
	.comm	_UVD_CGC_GATE__UDEC_MASK,4,2    ## @UVD_CGC_GATE__UDEC_MASK
	.comm	_UVD_CGC_GATE__MPEG2_MASK,4,2   ## @UVD_CGC_GATE__MPEG2_MASK
	.comm	_UVD_CGC_GATE__REGS_MASK,4,2    ## @UVD_CGC_GATE__REGS_MASK
	.comm	_UVD_CGC_GATE__RBC_MASK,4,2     ## @UVD_CGC_GATE__RBC_MASK
	.comm	_UVD_CGC_GATE__LMI_MC_MASK,4,2  ## @UVD_CGC_GATE__LMI_MC_MASK
	.comm	_UVD_CGC_GATE__LMI_UMC_MASK,4,2 ## @UVD_CGC_GATE__LMI_UMC_MASK
	.comm	_UVD_CGC_GATE__IDCT_MASK,4,2    ## @UVD_CGC_GATE__IDCT_MASK
	.comm	_UVD_CGC_GATE__MPRD_MASK,4,2    ## @UVD_CGC_GATE__MPRD_MASK
	.comm	_UVD_CGC_GATE__MPC_MASK,4,2     ## @UVD_CGC_GATE__MPC_MASK
	.comm	_UVD_CGC_GATE__LBSI_MASK,4,2    ## @UVD_CGC_GATE__LBSI_MASK
	.comm	_UVD_CGC_GATE__LRBBM_MASK,4,2   ## @UVD_CGC_GATE__LRBBM_MASK
	.comm	_UVD_CGC_GATE__UDEC_RE_MASK,4,2 ## @UVD_CGC_GATE__UDEC_RE_MASK
	.comm	_UVD_CGC_GATE__UDEC_CM_MASK,4,2 ## @UVD_CGC_GATE__UDEC_CM_MASK
	.comm	_UVD_CGC_GATE__UDEC_IT_MASK,4,2 ## @UVD_CGC_GATE__UDEC_IT_MASK
	.comm	_UVD_CGC_GATE__UDEC_DB_MASK,4,2 ## @UVD_CGC_GATE__UDEC_DB_MASK
	.comm	_UVD_CGC_GATE__UDEC_MP_MASK,4,2 ## @UVD_CGC_GATE__UDEC_MP_MASK
	.comm	_UVD_CGC_GATE__WCB_MASK,4,2     ## @UVD_CGC_GATE__WCB_MASK
	.comm	_UVD_CGC_GATE__VCPU_MASK,4,2    ## @UVD_CGC_GATE__VCPU_MASK
	.comm	_UVD_CGC_GATE__SCPU_MASK,4,2    ## @UVD_CGC_GATE__SCPU_MASK
	.comm	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_RE_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_CM_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_IT_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_DB_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_MP_MODE_MASK
	.comm	_UVD_CGC_CTRL__SYS_MODE_MASK,4,2 ## @UVD_CGC_CTRL__SYS_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPEG2_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPEG2_MODE_MASK
	.comm	_UVD_CGC_CTRL__REGS_MODE_MASK,4,2 ## @UVD_CGC_CTRL__REGS_MODE_MASK
	.comm	_UVD_CGC_CTRL__RBC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__RBC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_MC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LMI_MC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LMI_UMC_MODE_MASK
	.comm	_UVD_CGC_CTRL__IDCT_MODE_MASK,4,2 ## @UVD_CGC_CTRL__IDCT_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPRD_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPRD_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LBSI_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LBSI_MODE_MASK
	.comm	_UVD_CGC_CTRL__LRBBM_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LRBBM_MODE_MASK
	.comm	_UVD_CGC_CTRL__WCB_MODE_MASK,4,2 ## @UVD_CGC_CTRL__WCB_MODE_MASK
	.comm	_UVD_CGC_CTRL__VCPU_MODE_MASK,4,2 ## @UVD_CGC_CTRL__VCPU_MODE_MASK
	.comm	_UVD_CGC_CTRL__SCPU_MODE_MASK,4,2 ## @UVD_CGC_CTRL__SCPU_MODE_MASK
	.comm	_mmUVD_SUVD_CGC_GATE,4,2        ## @mmUVD_SUVD_CGC_GATE
	.comm	_UVD_SUVD_CGC_GATE__SRE_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SRE_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SIT_MASK
	.comm	_UVD_SUVD_CGC_GATE__SMP_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SMP_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SCM_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SDB_MASK
	.comm	_UVD_SUVD_CGC_GATE__SRE_H264_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SRE_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SRE_HEVC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_H264_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SIT_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_HEVC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_H264_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SCM_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_HEVC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_H264_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SDB_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_HEVC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCLR_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SCLR_MASK
	.comm	_UVD_SUVD_CGC_GATE__UVD_SC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__UVD_SC_MASK
	.comm	_UVD_SUVD_CGC_GATE__ENT_MASK,4,2 ## @UVD_SUVD_CGC_GATE__ENT_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SITE_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SITE_MASK
	.comm	_UVD_SUVD_CGC_GATE__SRE_VP9_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SRE_VP9_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_VP9_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SCM_VP9_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_VP9_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SDB_VP9_MASK
	.comm	_UVD_SUVD_CGC_GATE__IME_HEVC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__IME_HEVC_MASK
	.comm	_mmUVD_SUVD_CGC_CTRL,4,2        ## @mmUVD_SUVD_CGC_CTRL
	.comm	_UVD_SUVD_CGC_CTRL__SRE_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SIT_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SMP_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SCM_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SDB_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__ENT_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__IME_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__IME_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SITE_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
	.no_dead_strip	_vcn_v2_0_disable_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v2_0_disable_clock_gating
_vcn_v2_0_disable_clock_gating:         ; @vcn_v2_0_disable_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
Lloh0:
	adrp	x20, _VCN@GOTPAGE
Lloh1:
	ldr	x20, [x20, _VCN@GOTPAGEOFF]
	ldr	w0, [x20]
Lloh2:
	adrp	x21, _mmUVD_CGC_CTRL@GOTPAGE
Lloh3:
	ldr	x21, [x21, _mmUVD_CGC_CTRL@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_RREG32_SOC15
	ldr	w8, [x19]
Lloh4:
	adrp	x9, _AMD_CG_SUPPORT_VCN_MGCG@GOTPAGE
Lloh5:
	ldr	x9, [x9, _AMD_CG_SUPPORT_VCN_MGCG@GOTPAGEOFF]
Lloh6:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
Lloh7:
	adrp	x8, _UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPAGE
Lloh8:
	ldr	x8, [x8, _UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	mov	w9, #1
	lsl	w8, w9, w8
	orr	w8, w8, w0
	b	LBB0_3
LBB0_2:
Lloh10:
	adrp	x8, _UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPAGE
Lloh11:
	ldr	x8, [x8, _UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	bic	w8, w0, w8
LBB0_3:
Lloh13:
	adrp	x9, _UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPAGE
Lloh14:
	ldr	x9, [x9, _UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	mov	w10, #1
	lsl	w9, w10, w9
	orr	w8, w9, w8
Lloh16:
	adrp	x9, _UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPAGE
Lloh17:
	ldr	x9, [x9, _UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	mov	w10, #4
	lsl	w9, w10, w9
	orr	w3, w8, w9
	ldr	w0, [x20]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x20]
Lloh19:
	adrp	x19, _mmUVD_CGC_GATE@GOTPAGE
Lloh20:
	ldr	x19, [x19, _mmUVD_CGC_GATE@GOTPAGEOFF]
	ldr	w2, [x19]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh21:
	adrp	x8, _UVD_CGC_GATE__SYS_MASK@GOTPAGE
Lloh22:
	ldr	x8, [x8, _UVD_CGC_GATE__SYS_MASK@GOTPAGEOFF]
Lloh23:
	adrp	x9, _UVD_CGC_GATE__UDEC_MASK@GOTPAGE
Lloh24:
	ldr	x9, [x9, _UVD_CGC_GATE__UDEC_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
Lloh26:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh27:
	adrp	x9, _UVD_CGC_GATE__MPEG2_MASK@GOTPAGE
Lloh28:
	ldr	x9, [x9, _UVD_CGC_GATE__MPEG2_MASK@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh30:
	adrp	x9, _UVD_CGC_GATE__REGS_MASK@GOTPAGE
Lloh31:
	ldr	x9, [x9, _UVD_CGC_GATE__REGS_MASK@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
Lloh33:
	adrp	x10, _UVD_CGC_GATE__RBC_MASK@GOTPAGE
Lloh34:
	ldr	x10, [x10, _UVD_CGC_GATE__RBC_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh35:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh36:
	adrp	x9, _UVD_CGC_GATE__LMI_MC_MASK@GOTPAGE
Lloh37:
	ldr	x9, [x9, _UVD_CGC_GATE__LMI_MC_MASK@GOTPAGEOFF]
Lloh38:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh39:
	adrp	x9, _UVD_CGC_GATE__LMI_UMC_MASK@GOTPAGE
Lloh40:
	ldr	x9, [x9, _UVD_CGC_GATE__LMI_UMC_MASK@GOTPAGEOFF]
Lloh41:
	ldr	w9, [x9]
Lloh42:
	adrp	x10, _UVD_CGC_GATE__IDCT_MASK@GOTPAGE
Lloh43:
	ldr	x10, [x10, _UVD_CGC_GATE__IDCT_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh44:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh45:
	adrp	x9, _UVD_CGC_GATE__MPRD_MASK@GOTPAGE
Lloh46:
	ldr	x9, [x9, _UVD_CGC_GATE__MPRD_MASK@GOTPAGEOFF]
Lloh47:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh48:
	adrp	x9, _UVD_CGC_GATE__MPC_MASK@GOTPAGE
Lloh49:
	ldr	x9, [x9, _UVD_CGC_GATE__MPC_MASK@GOTPAGEOFF]
Lloh50:
	ldr	w9, [x9]
Lloh51:
	adrp	x10, _UVD_CGC_GATE__LBSI_MASK@GOTPAGE
Lloh52:
	ldr	x10, [x10, _UVD_CGC_GATE__LBSI_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh53:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh54:
	adrp	x9, _UVD_CGC_GATE__LRBBM_MASK@GOTPAGE
Lloh55:
	ldr	x9, [x9, _UVD_CGC_GATE__LRBBM_MASK@GOTPAGEOFF]
Lloh56:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh57:
	adrp	x9, _UVD_CGC_GATE__UDEC_RE_MASK@GOTPAGE
Lloh58:
	ldr	x9, [x9, _UVD_CGC_GATE__UDEC_RE_MASK@GOTPAGEOFF]
Lloh59:
	ldr	w9, [x9]
Lloh60:
	adrp	x10, _UVD_CGC_GATE__UDEC_CM_MASK@GOTPAGE
Lloh61:
	ldr	x10, [x10, _UVD_CGC_GATE__UDEC_CM_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh62:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh63:
	adrp	x9, _UVD_CGC_GATE__UDEC_IT_MASK@GOTPAGE
Lloh64:
	ldr	x9, [x9, _UVD_CGC_GATE__UDEC_IT_MASK@GOTPAGEOFF]
Lloh65:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh66:
	adrp	x9, _UVD_CGC_GATE__UDEC_DB_MASK@GOTPAGE
Lloh67:
	ldr	x9, [x9, _UVD_CGC_GATE__UDEC_DB_MASK@GOTPAGEOFF]
Lloh68:
	ldr	w9, [x9]
Lloh69:
	adrp	x10, _UVD_CGC_GATE__UDEC_MP_MASK@GOTPAGE
Lloh70:
	ldr	x10, [x10, _UVD_CGC_GATE__UDEC_MP_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh71:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh72:
	adrp	x9, _UVD_CGC_GATE__WCB_MASK@GOTPAGE
Lloh73:
	ldr	x9, [x9, _UVD_CGC_GATE__WCB_MASK@GOTPAGEOFF]
Lloh74:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh75:
	adrp	x9, _UVD_CGC_GATE__VCPU_MASK@GOTPAGE
Lloh76:
	ldr	x9, [x9, _UVD_CGC_GATE__VCPU_MASK@GOTPAGEOFF]
Lloh77:
	ldr	w9, [x9]
Lloh78:
	adrp	x10, _UVD_CGC_GATE__SCPU_MASK@GOTPAGE
Lloh79:
	ldr	x10, [x10, _UVD_CGC_GATE__SCPU_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh80:
	ldr	w9, [x10]
	orr	w8, w8, w9
	bic	w3, w0, w8
	ldr	w0, [x20]
	ldr	w2, [x19]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x20]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh81:
	adrp	x8, _UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPAGE
Lloh82:
	ldr	x8, [x8, _UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPAGEOFF]
Lloh83:
	adrp	x9, _UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPAGE
Lloh84:
	ldr	x9, [x9, _UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPAGEOFF]
Lloh85:
	ldr	w8, [x8]
Lloh86:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh87:
	adrp	x9, _UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPAGE
Lloh88:
	ldr	x9, [x9, _UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPAGEOFF]
Lloh89:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh90:
	adrp	x9, _UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPAGE
Lloh91:
	ldr	x9, [x9, _UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPAGEOFF]
Lloh92:
	ldr	w9, [x9]
Lloh93:
	adrp	x10, _UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPAGE
Lloh94:
	ldr	x10, [x10, _UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh95:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh96:
	adrp	x9, _UVD_CGC_CTRL__SYS_MODE_MASK@GOTPAGE
Lloh97:
	ldr	x9, [x9, _UVD_CGC_CTRL__SYS_MODE_MASK@GOTPAGEOFF]
Lloh98:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh99:
	adrp	x9, _UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPAGE
Lloh100:
	ldr	x9, [x9, _UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPAGEOFF]
Lloh101:
	ldr	w9, [x9]
Lloh102:
	adrp	x10, _UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPAGE
Lloh103:
	ldr	x10, [x10, _UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh104:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh105:
	adrp	x9, _UVD_CGC_CTRL__REGS_MODE_MASK@GOTPAGE
Lloh106:
	ldr	x9, [x9, _UVD_CGC_CTRL__REGS_MODE_MASK@GOTPAGEOFF]
Lloh107:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh108:
	adrp	x9, _UVD_CGC_CTRL__RBC_MODE_MASK@GOTPAGE
Lloh109:
	ldr	x9, [x9, _UVD_CGC_CTRL__RBC_MODE_MASK@GOTPAGEOFF]
Lloh110:
	ldr	w9, [x9]
Lloh111:
	adrp	x10, _UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPAGE
Lloh112:
	ldr	x10, [x10, _UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh113:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh114:
	adrp	x9, _UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPAGE
Lloh115:
	ldr	x9, [x9, _UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPAGEOFF]
Lloh116:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh117:
	adrp	x9, _UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPAGE
Lloh118:
	ldr	x9, [x9, _UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPAGEOFF]
Lloh119:
	ldr	w9, [x9]
Lloh120:
	adrp	x10, _UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPAGE
Lloh121:
	ldr	x10, [x10, _UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh122:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh123:
	adrp	x9, _UVD_CGC_CTRL__MPC_MODE_MASK@GOTPAGE
Lloh124:
	ldr	x9, [x9, _UVD_CGC_CTRL__MPC_MODE_MASK@GOTPAGEOFF]
Lloh125:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh126:
	adrp	x9, _UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPAGE
Lloh127:
	ldr	x9, [x9, _UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPAGEOFF]
Lloh128:
	ldr	w9, [x9]
Lloh129:
	adrp	x10, _UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPAGE
Lloh130:
	ldr	x10, [x10, _UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh131:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh132:
	adrp	x9, _UVD_CGC_CTRL__WCB_MODE_MASK@GOTPAGE
Lloh133:
	ldr	x9, [x9, _UVD_CGC_CTRL__WCB_MODE_MASK@GOTPAGEOFF]
Lloh134:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh135:
	adrp	x9, _UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPAGE
Lloh136:
	ldr	x9, [x9, _UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPAGEOFF]
Lloh137:
	ldr	w9, [x9]
Lloh138:
	adrp	x10, _UVD_CGC_CTRL__SCPU_MODE_MASK@GOTPAGE
Lloh139:
	ldr	x10, [x10, _UVD_CGC_CTRL__SCPU_MODE_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh140:
	ldr	w9, [x10]
	orr	w8, w8, w9
	bic	w3, w0, w8
	ldr	w0, [x20]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x20]
Lloh141:
	adrp	x19, _mmUVD_SUVD_CGC_GATE@GOTPAGE
Lloh142:
	ldr	x19, [x19, _mmUVD_SUVD_CGC_GATE@GOTPAGEOFF]
	ldr	w2, [x19]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh143:
	adrp	x8, _UVD_SUVD_CGC_GATE__SRE_MASK@GOTPAGE
Lloh144:
	ldr	x8, [x8, _UVD_SUVD_CGC_GATE__SRE_MASK@GOTPAGEOFF]
Lloh145:
	ldr	w8, [x8]
Lloh146:
	adrp	x9, _UVD_SUVD_CGC_GATE__SIT_MASK@GOTPAGE
Lloh147:
	ldr	x9, [x9, _UVD_SUVD_CGC_GATE__SIT_MASK@GOTPAGEOFF]
Lloh148:
	ldr	w9, [x9]
Lloh149:
	adrp	x10, _UVD_SUVD_CGC_GATE__SMP_MASK@GOTPAGE
Lloh150:
	ldr	x10, [x10, _UVD_SUVD_CGC_GATE__SMP_MASK@GOTPAGEOFF]
Lloh151:
	ldr	w10, [x10]
Lloh152:
	adrp	x11, _UVD_SUVD_CGC_GATE__SCM_MASK@GOTPAGE
Lloh153:
	ldr	x11, [x11, _UVD_SUVD_CGC_GATE__SCM_MASK@GOTPAGEOFF]
Lloh154:
	ldr	w11, [x11]
Lloh155:
	adrp	x12, _UVD_SUVD_CGC_GATE__SDB_MASK@GOTPAGE
Lloh156:
	ldr	x12, [x12, _UVD_SUVD_CGC_GATE__SDB_MASK@GOTPAGEOFF]
Lloh157:
	ldr	w12, [x12]
Lloh158:
	adrp	x13, _UVD_SUVD_CGC_GATE__SRE_H264_MASK@GOTPAGE
Lloh159:
	ldr	x13, [x13, _UVD_SUVD_CGC_GATE__SRE_H264_MASK@GOTPAGEOFF]
Lloh160:
	ldr	w13, [x13]
Lloh161:
	adrp	x14, _UVD_SUVD_CGC_GATE__SRE_HEVC_MASK@GOTPAGE
Lloh162:
	ldr	x14, [x14, _UVD_SUVD_CGC_GATE__SRE_HEVC_MASK@GOTPAGEOFF]
Lloh163:
	ldr	w14, [x14]
Lloh164:
	adrp	x15, _UVD_SUVD_CGC_GATE__SIT_H264_MASK@GOTPAGE
Lloh165:
	ldr	x15, [x15, _UVD_SUVD_CGC_GATE__SIT_H264_MASK@GOTPAGEOFF]
Lloh166:
	ldr	w15, [x15]
Lloh167:
	adrp	x16, _UVD_SUVD_CGC_GATE__SIT_HEVC_MASK@GOTPAGE
Lloh168:
	ldr	x16, [x16, _UVD_SUVD_CGC_GATE__SIT_HEVC_MASK@GOTPAGEOFF]
Lloh169:
	ldr	w16, [x16]
Lloh170:
	adrp	x17, _UVD_SUVD_CGC_GATE__SCM_H264_MASK@GOTPAGE
Lloh171:
	ldr	x17, [x17, _UVD_SUVD_CGC_GATE__SCM_H264_MASK@GOTPAGEOFF]
Lloh172:
	ldr	w17, [x17]
Lloh173:
	adrp	x1, _UVD_SUVD_CGC_GATE__SCM_HEVC_MASK@GOTPAGE
Lloh174:
	ldr	x1, [x1, _UVD_SUVD_CGC_GATE__SCM_HEVC_MASK@GOTPAGEOFF]
Lloh175:
	ldr	w1, [x1]
Lloh176:
	adrp	x2, _UVD_SUVD_CGC_GATE__SDB_H264_MASK@GOTPAGE
Lloh177:
	ldr	x2, [x2, _UVD_SUVD_CGC_GATE__SDB_H264_MASK@GOTPAGEOFF]
Lloh178:
	ldr	w2, [x2]
Lloh179:
	adrp	x3, _UVD_SUVD_CGC_GATE__SDB_HEVC_MASK@GOTPAGE
Lloh180:
	ldr	x3, [x3, _UVD_SUVD_CGC_GATE__SDB_HEVC_MASK@GOTPAGEOFF]
Lloh181:
	ldr	w3, [x3]
Lloh182:
	adrp	x4, _UVD_SUVD_CGC_GATE__SCLR_MASK@GOTPAGE
Lloh183:
	ldr	x4, [x4, _UVD_SUVD_CGC_GATE__SCLR_MASK@GOTPAGEOFF]
Lloh184:
	ldr	w4, [x4]
Lloh185:
	adrp	x5, _UVD_SUVD_CGC_GATE__UVD_SC_MASK@GOTPAGE
Lloh186:
	ldr	x5, [x5, _UVD_SUVD_CGC_GATE__UVD_SC_MASK@GOTPAGEOFF]
Lloh187:
	ldr	w5, [x5]
Lloh188:
	adrp	x6, _UVD_SUVD_CGC_GATE__ENT_MASK@GOTPAGE
Lloh189:
	ldr	x6, [x6, _UVD_SUVD_CGC_GATE__ENT_MASK@GOTPAGEOFF]
Lloh190:
	ldr	w6, [x6]
Lloh191:
	adrp	x7, _UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK@GOTPAGE
Lloh192:
	ldr	x7, [x7, _UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK@GOTPAGEOFF]
Lloh193:
	ldr	w7, [x7]
Lloh194:
	adrp	x21, _UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK@GOTPAGE
Lloh195:
	ldr	x21, [x21, _UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK@GOTPAGEOFF]
Lloh196:
	ldr	w21, [x21]
Lloh197:
	adrp	x22, _UVD_SUVD_CGC_GATE__SITE_MASK@GOTPAGE
Lloh198:
	ldr	x22, [x22, _UVD_SUVD_CGC_GATE__SITE_MASK@GOTPAGEOFF]
Lloh199:
	ldr	w22, [x22]
Lloh200:
	adrp	x23, _UVD_SUVD_CGC_GATE__SRE_VP9_MASK@GOTPAGE
Lloh201:
	ldr	x23, [x23, _UVD_SUVD_CGC_GATE__SRE_VP9_MASK@GOTPAGEOFF]
Lloh202:
	ldr	w23, [x23]
Lloh203:
	adrp	x24, _UVD_SUVD_CGC_GATE__SCM_VP9_MASK@GOTPAGE
Lloh204:
	ldr	x24, [x24, _UVD_SUVD_CGC_GATE__SCM_VP9_MASK@GOTPAGEOFF]
Lloh205:
	ldr	w24, [x24]
Lloh206:
	adrp	x25, _UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK@GOTPAGE
Lloh207:
	ldr	x25, [x25, _UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK@GOTPAGEOFF]
Lloh208:
	ldr	w25, [x25]
Lloh209:
	adrp	x26, _UVD_SUVD_CGC_GATE__SDB_VP9_MASK@GOTPAGE
Lloh210:
	ldr	x26, [x26, _UVD_SUVD_CGC_GATE__SDB_VP9_MASK@GOTPAGEOFF]
Lloh211:
	ldr	w26, [x26]
Lloh212:
	adrp	x27, _UVD_SUVD_CGC_GATE__IME_HEVC_MASK@GOTPAGE
Lloh213:
	ldr	x27, [x27, _UVD_SUVD_CGC_GATE__IME_HEVC_MASK@GOTPAGEOFF]
Lloh214:
	ldr	w27, [x27]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w8, w8, w13
	orr	w8, w8, w14
	orr	w8, w8, w15
	orr	w8, w8, w16
	orr	w8, w8, w17
	orr	w8, w8, w1
	orr	w8, w8, w2
	orr	w8, w8, w3
	orr	w8, w8, w4
	orr	w8, w8, w5
	orr	w8, w8, w6
	orr	w8, w8, w7
	orr	w8, w8, w21
	orr	w8, w8, w22
	orr	w8, w8, w23
	orr	w8, w8, w24
	orr	w8, w8, w25
	orr	w8, w8, w26
	orr	w3, w8, w27
	ldr	w0, [x20]
	ldr	w2, [x19]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x20]
Lloh215:
	adrp	x19, _mmUVD_SUVD_CGC_CTRL@GOTPAGE
Lloh216:
	ldr	x19, [x19, _mmUVD_SUVD_CGC_CTRL@GOTPAGEOFF]
	ldr	w2, [x19]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh217:
	adrp	x8, _UVD_SUVD_CGC_CTRL__SRE_MODE_MASK@GOTPAGE
Lloh218:
	ldr	x8, [x8, _UVD_SUVD_CGC_CTRL__SRE_MODE_MASK@GOTPAGEOFF]
Lloh219:
	adrp	x9, _UVD_SUVD_CGC_CTRL__SIT_MODE_MASK@GOTPAGE
Lloh220:
	ldr	x9, [x9, _UVD_SUVD_CGC_CTRL__SIT_MODE_MASK@GOTPAGEOFF]
Lloh221:
	ldr	w8, [x8]
Lloh222:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh223:
	adrp	x9, _UVD_SUVD_CGC_CTRL__SMP_MODE_MASK@GOTPAGE
Lloh224:
	ldr	x9, [x9, _UVD_SUVD_CGC_CTRL__SMP_MODE_MASK@GOTPAGEOFF]
Lloh225:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh226:
	adrp	x9, _UVD_SUVD_CGC_CTRL__SCM_MODE_MASK@GOTPAGE
Lloh227:
	ldr	x9, [x9, _UVD_SUVD_CGC_CTRL__SCM_MODE_MASK@GOTPAGEOFF]
Lloh228:
	ldr	w9, [x9]
Lloh229:
	adrp	x10, _UVD_SUVD_CGC_CTRL__SDB_MODE_MASK@GOTPAGE
Lloh230:
	ldr	x10, [x10, _UVD_SUVD_CGC_CTRL__SDB_MODE_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh231:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh232:
	adrp	x9, _UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK@GOTPAGE
Lloh233:
	ldr	x9, [x9, _UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK@GOTPAGEOFF]
Lloh234:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh235:
	adrp	x9, _UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK@GOTPAGE
Lloh236:
	ldr	x9, [x9, _UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK@GOTPAGEOFF]
Lloh237:
	ldr	w9, [x9]
Lloh238:
	adrp	x10, _UVD_SUVD_CGC_CTRL__ENT_MODE_MASK@GOTPAGE
Lloh239:
	ldr	x10, [x10, _UVD_SUVD_CGC_CTRL__ENT_MODE_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh240:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh241:
	adrp	x9, _UVD_SUVD_CGC_CTRL__IME_MODE_MASK@GOTPAGE
Lloh242:
	ldr	x9, [x9, _UVD_SUVD_CGC_CTRL__IME_MODE_MASK@GOTPAGEOFF]
Lloh243:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh244:
	adrp	x9, _UVD_SUVD_CGC_CTRL__SITE_MODE_MASK@GOTPAGE
Lloh245:
	ldr	x9, [x9, _UVD_SUVD_CGC_CTRL__SITE_MODE_MASK@GOTPAGEOFF]
Lloh246:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w3, w0, w8
	ldr	w0, [x20]
	ldr	w2, [x19]
	mov	w1, #0
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_WREG32_SOC15
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh244, Lloh245, Lloh246
	.loh AdrpLdrGotLdr	Lloh241, Lloh242, Lloh243
	.loh AdrpLdrGotLdr	Lloh238, Lloh239, Lloh240
	.loh AdrpLdrGotLdr	Lloh235, Lloh236, Lloh237
	.loh AdrpLdrGotLdr	Lloh232, Lloh233, Lloh234
	.loh AdrpLdrGotLdr	Lloh229, Lloh230, Lloh231
	.loh AdrpLdrGotLdr	Lloh226, Lloh227, Lloh228
	.loh AdrpLdrGotLdr	Lloh223, Lloh224, Lloh225
	.loh AdrpLdrGotLdr	Lloh219, Lloh220, Lloh222
	.loh AdrpLdrGotLdr	Lloh217, Lloh218, Lloh221
	.loh AdrpLdrGot	Lloh215, Lloh216
	.loh AdrpLdrGotLdr	Lloh212, Lloh213, Lloh214
	.loh AdrpLdrGotLdr	Lloh209, Lloh210, Lloh211
	.loh AdrpLdrGotLdr	Lloh206, Lloh207, Lloh208
	.loh AdrpLdrGotLdr	Lloh203, Lloh204, Lloh205
	.loh AdrpLdrGotLdr	Lloh200, Lloh201, Lloh202
	.loh AdrpLdrGotLdr	Lloh197, Lloh198, Lloh199
	.loh AdrpLdrGotLdr	Lloh194, Lloh195, Lloh196
	.loh AdrpLdrGotLdr	Lloh191, Lloh192, Lloh193
	.loh AdrpLdrGotLdr	Lloh188, Lloh189, Lloh190
	.loh AdrpLdrGotLdr	Lloh185, Lloh186, Lloh187
	.loh AdrpLdrGotLdr	Lloh182, Lloh183, Lloh184
	.loh AdrpLdrGotLdr	Lloh179, Lloh180, Lloh181
	.loh AdrpLdrGotLdr	Lloh176, Lloh177, Lloh178
	.loh AdrpLdrGotLdr	Lloh173, Lloh174, Lloh175
	.loh AdrpLdrGotLdr	Lloh170, Lloh171, Lloh172
	.loh AdrpLdrGotLdr	Lloh167, Lloh168, Lloh169
	.loh AdrpLdrGotLdr	Lloh164, Lloh165, Lloh166
	.loh AdrpLdrGotLdr	Lloh161, Lloh162, Lloh163
	.loh AdrpLdrGotLdr	Lloh158, Lloh159, Lloh160
	.loh AdrpLdrGotLdr	Lloh155, Lloh156, Lloh157
	.loh AdrpLdrGotLdr	Lloh152, Lloh153, Lloh154
	.loh AdrpLdrGotLdr	Lloh149, Lloh150, Lloh151
	.loh AdrpLdrGotLdr	Lloh146, Lloh147, Lloh148
	.loh AdrpLdrGotLdr	Lloh143, Lloh144, Lloh145
	.loh AdrpLdrGot	Lloh141, Lloh142
	.loh AdrpLdrGotLdr	Lloh138, Lloh139, Lloh140
	.loh AdrpLdrGotLdr	Lloh135, Lloh136, Lloh137
	.loh AdrpLdrGotLdr	Lloh132, Lloh133, Lloh134
	.loh AdrpLdrGotLdr	Lloh129, Lloh130, Lloh131
	.loh AdrpLdrGotLdr	Lloh126, Lloh127, Lloh128
	.loh AdrpLdrGotLdr	Lloh123, Lloh124, Lloh125
	.loh AdrpLdrGotLdr	Lloh120, Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh85
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh25
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.cfi_endproc
                                        ; -- End function
	.comm	_VCN,4,2                        ; @VCN
	.comm	_mmUVD_CGC_CTRL,4,2             ; @mmUVD_CGC_CTRL
	.comm	_AMD_CG_SUPPORT_VCN_MGCG,4,2    ; @AMD_CG_SUPPORT_VCN_MGCG
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT,4,2 ; @UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK,4,2 ; @UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK
	.comm	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT,4,2 ; @UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
	.comm	_UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT,4,2 ; @UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT
	.comm	_mmUVD_CGC_GATE,4,2             ; @mmUVD_CGC_GATE
	.comm	_UVD_CGC_GATE__SYS_MASK,4,2     ; @UVD_CGC_GATE__SYS_MASK
	.comm	_UVD_CGC_GATE__UDEC_MASK,4,2    ; @UVD_CGC_GATE__UDEC_MASK
	.comm	_UVD_CGC_GATE__MPEG2_MASK,4,2   ; @UVD_CGC_GATE__MPEG2_MASK
	.comm	_UVD_CGC_GATE__REGS_MASK,4,2    ; @UVD_CGC_GATE__REGS_MASK
	.comm	_UVD_CGC_GATE__RBC_MASK,4,2     ; @UVD_CGC_GATE__RBC_MASK
	.comm	_UVD_CGC_GATE__LMI_MC_MASK,4,2  ; @UVD_CGC_GATE__LMI_MC_MASK
	.comm	_UVD_CGC_GATE__LMI_UMC_MASK,4,2 ; @UVD_CGC_GATE__LMI_UMC_MASK
	.comm	_UVD_CGC_GATE__IDCT_MASK,4,2    ; @UVD_CGC_GATE__IDCT_MASK
	.comm	_UVD_CGC_GATE__MPRD_MASK,4,2    ; @UVD_CGC_GATE__MPRD_MASK
	.comm	_UVD_CGC_GATE__MPC_MASK,4,2     ; @UVD_CGC_GATE__MPC_MASK
	.comm	_UVD_CGC_GATE__LBSI_MASK,4,2    ; @UVD_CGC_GATE__LBSI_MASK
	.comm	_UVD_CGC_GATE__LRBBM_MASK,4,2   ; @UVD_CGC_GATE__LRBBM_MASK
	.comm	_UVD_CGC_GATE__UDEC_RE_MASK,4,2 ; @UVD_CGC_GATE__UDEC_RE_MASK
	.comm	_UVD_CGC_GATE__UDEC_CM_MASK,4,2 ; @UVD_CGC_GATE__UDEC_CM_MASK
	.comm	_UVD_CGC_GATE__UDEC_IT_MASK,4,2 ; @UVD_CGC_GATE__UDEC_IT_MASK
	.comm	_UVD_CGC_GATE__UDEC_DB_MASK,4,2 ; @UVD_CGC_GATE__UDEC_DB_MASK
	.comm	_UVD_CGC_GATE__UDEC_MP_MASK,4,2 ; @UVD_CGC_GATE__UDEC_MP_MASK
	.comm	_UVD_CGC_GATE__WCB_MASK,4,2     ; @UVD_CGC_GATE__WCB_MASK
	.comm	_UVD_CGC_GATE__VCPU_MASK,4,2    ; @UVD_CGC_GATE__VCPU_MASK
	.comm	_UVD_CGC_GATE__SCPU_MASK,4,2    ; @UVD_CGC_GATE__SCPU_MASK
	.comm	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_RE_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_CM_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_IT_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_DB_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_MP_MODE_MASK
	.comm	_UVD_CGC_CTRL__SYS_MODE_MASK,4,2 ; @UVD_CGC_CTRL__SYS_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPEG2_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPEG2_MODE_MASK
	.comm	_UVD_CGC_CTRL__REGS_MODE_MASK,4,2 ; @UVD_CGC_CTRL__REGS_MODE_MASK
	.comm	_UVD_CGC_CTRL__RBC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__RBC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_MC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LMI_MC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LMI_UMC_MODE_MASK
	.comm	_UVD_CGC_CTRL__IDCT_MODE_MASK,4,2 ; @UVD_CGC_CTRL__IDCT_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPRD_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPRD_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LBSI_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LBSI_MODE_MASK
	.comm	_UVD_CGC_CTRL__LRBBM_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LRBBM_MODE_MASK
	.comm	_UVD_CGC_CTRL__WCB_MODE_MASK,4,2 ; @UVD_CGC_CTRL__WCB_MODE_MASK
	.comm	_UVD_CGC_CTRL__VCPU_MODE_MASK,4,2 ; @UVD_CGC_CTRL__VCPU_MODE_MASK
	.comm	_UVD_CGC_CTRL__SCPU_MODE_MASK,4,2 ; @UVD_CGC_CTRL__SCPU_MODE_MASK
	.comm	_mmUVD_SUVD_CGC_GATE,4,2        ; @mmUVD_SUVD_CGC_GATE
	.comm	_UVD_SUVD_CGC_GATE__SRE_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SRE_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SIT_MASK
	.comm	_UVD_SUVD_CGC_GATE__SMP_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SMP_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SCM_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SDB_MASK
	.comm	_UVD_SUVD_CGC_GATE__SRE_H264_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SRE_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SRE_HEVC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_H264_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SIT_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_HEVC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_H264_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SCM_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_HEVC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_H264_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SDB_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_HEVC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCLR_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SCLR_MASK
	.comm	_UVD_SUVD_CGC_GATE__UVD_SC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__UVD_SC_MASK
	.comm	_UVD_SUVD_CGC_GATE__ENT_MASK,4,2 ; @UVD_SUVD_CGC_GATE__ENT_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SITE_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SITE_MASK
	.comm	_UVD_SUVD_CGC_GATE__SRE_VP9_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SRE_VP9_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_VP9_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SCM_VP9_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_VP9_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SDB_VP9_MASK
	.comm	_UVD_SUVD_CGC_GATE__IME_HEVC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__IME_HEVC_MASK
	.comm	_mmUVD_SUVD_CGC_CTRL,4,2        ; @mmUVD_SUVD_CGC_CTRL
	.comm	_UVD_SUVD_CGC_CTRL__SRE_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SIT_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SMP_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SCM_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SDB_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__ENT_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__IME_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__IME_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SITE_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
	.no_dead_strip	_vcn_v2_0_disable_clock_gating
.subsections_via_symbols
