	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r600_fence_ring_emit           ## -- Begin function r600_fence_ring_emit
	.p2align	4, 0x90
_r600_fence_ring_emit:                  ## @r600_fence_ring_emit
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %r15
	movq	(%rsi), %rax
	leaq	(,%rax,4), %r13
	movq	_PACKET3_TC_ACTION_ENA@GOTPCREL(%rip), %rcx
	movq	_PACKET3_VC_ACTION_ENA@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	movq	_PACKET3_SH_ACTION_ENA@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	(%rdi), %rdx
	movq	_CHIP_RV770@GOTPCREL(%rip), %rsi
	xorl	%ecx, %ecx
	cmpq	(%rsi), %rdx
	jl	LBB0_2
## %bb.1:
	movq	_PACKET3_FULL_CACHE_ENA@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_2:
	orl	%ecx, %ebx
	addq	24(%r15), %r13
	cmpq	$0, 16(%r15)
	je	LBB0_4
## %bb.3:
	movq	8(%r15), %rcx
	movl	4(%rcx,%rax,8), %r12d
	movq	_PACKET3_SURFACE_SYNC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$3, %esi
	callq	_PACKET3
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_radeon_ring_write
	movq	%r13, %rdi
	movl	$-1, %esi
	callq	_radeon_ring_write
	xorl	%r15d, %r15d
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	_radeon_ring_write
	movq	%r13, %rdi
	movl	$10, %esi
	callq	_radeon_ring_write
	movq	_PACKET3_EVENT_WRITE_EOP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$4, %esi
	callq	_PACKET3
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movq	_CACHE_FLUSH_AND_INV_EVENT_TS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_EVENT_TYPE
	movl	%eax, %ebx
	movl	$5, %edi
	callq	_EVENT_INDEX
	orl	%eax, %ebx
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_radeon_ring_write
	movl	%r12d, %edi
	callq	_lower_32_bits
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movl	%r12d, %edi
	callq	_upper_32_bits
	movzbl	%al, %r12d
	movl	$1, %edi
	callq	_DATA_SEL
	movl	%eax, %ebx
	movl	$2, %edi
	callq	_INT_SEL
	orl	%eax, %ebx
	orl	%r12d, %ebx
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_radeon_ring_write
	movl	8(%r14), %esi
	movq	%r13, %rdi
	callq	_radeon_ring_write
	jmp	LBB0_5
LBB0_4:
	movq	_PACKET3_SURFACE_SYNC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$3, %esi
	callq	_PACKET3
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_radeon_ring_write
	movq	%r13, %rdi
	movl	$-1, %esi
	callq	_radeon_ring_write
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	_radeon_ring_write
	movq	%r13, %rdi
	movl	$10, %esi
	callq	_radeon_ring_write
	movq	_PACKET3_EVENT_WRITE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET3
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movq	_CACHE_FLUSH_AND_INV_EVENT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_EVENT_TYPE
	movl	%eax, %ebx
	xorl	%edi, %edi
	callq	_EVENT_INDEX
	orl	%eax, %ebx
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_radeon_ring_write
	movq	_PACKET3_SET_CONFIG_REG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movl	$1, %esi
	callq	_PACKET3
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movq	_WAIT_UNTIL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PACKET3_SET_CONFIG_REG_OFFSET@GOTPCREL(%rip), %r12
	subl	(%r12), %esi
	sarl	$2, %esi
	movq	%r13, %rdi
	callq	_radeon_ring_write
	movq	_WAIT_3D_IDLE_bit@GOTPCREL(%rip), %rax
	movq	_WAIT_3D_IDLECLEAN_bit@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movq	%r13, %rdi
	callq	_radeon_ring_write
	movl	(%rbx), %edi
	movl	$1, %esi
	callq	_PACKET3
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movq	8(%r15), %rax
	movq	(%r14), %rcx
	movl	(%rax,%rcx,8), %esi
	subl	(%r12), %esi
	sarl	$2, %esi
	movq	%r13, %rdi
	callq	_radeon_ring_write
	movl	8(%r14), %esi
	movq	%r13, %rdi
	callq	_radeon_ring_write
	movq	_CP_INT_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movq	_RB_INT_STAT@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
LBB0_5:
	movq	%r13, %rdi
	movl	%r15d, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_ring_write              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PACKET3_TC_ACTION_ENA,4,2      ## @PACKET3_TC_ACTION_ENA
	.comm	_PACKET3_VC_ACTION_ENA,4,2      ## @PACKET3_VC_ACTION_ENA
	.comm	_PACKET3_SH_ACTION_ENA,4,2      ## @PACKET3_SH_ACTION_ENA
	.comm	_CHIP_RV770,8,3                 ## @CHIP_RV770
	.comm	_PACKET3_FULL_CACHE_ENA,4,2     ## @PACKET3_FULL_CACHE_ENA
	.comm	_PACKET3_SURFACE_SYNC,4,2       ## @PACKET3_SURFACE_SYNC
	.comm	_PACKET3_EVENT_WRITE_EOP,4,2    ## @PACKET3_EVENT_WRITE_EOP
	.comm	_CACHE_FLUSH_AND_INV_EVENT_TS,4,2 ## @CACHE_FLUSH_AND_INV_EVENT_TS
	.comm	_PACKET3_EVENT_WRITE,4,2        ## @PACKET3_EVENT_WRITE
	.comm	_CACHE_FLUSH_AND_INV_EVENT,4,2  ## @CACHE_FLUSH_AND_INV_EVENT
	.comm	_PACKET3_SET_CONFIG_REG,4,2     ## @PACKET3_SET_CONFIG_REG
	.comm	_WAIT_UNTIL,4,2                 ## @WAIT_UNTIL
	.comm	_PACKET3_SET_CONFIG_REG_OFFSET,4,2 ## @PACKET3_SET_CONFIG_REG_OFFSET
	.comm	_WAIT_3D_IDLE_bit,4,2           ## @WAIT_3D_IDLE_bit
	.comm	_WAIT_3D_IDLECLEAN_bit,4,2      ## @WAIT_3D_IDLECLEAN_bit
	.comm	_CP_INT_STATUS,4,2              ## @CP_INT_STATUS
	.comm	_RB_INT_STAT,4,2                ## @RB_INT_STAT
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r600_fence_ring_emit           ; -- Begin function r600_fence_ring_emit
	.p2align	2
_r600_fence_ring_emit:                  ; @r600_fence_ring_emit
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x1
	mov	x21, x0
	ldr	x8, [x1]
	ldp	x10, x9, [x0, #16]
	add	x19, x9, x8, lsl #2
Lloh0:
	adrp	x9, _PACKET3_TC_ACTION_ENA@GOTPAGE
Lloh1:
	ldr	x9, [x9, _PACKET3_TC_ACTION_ENA@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
Lloh3:
	adrp	x11, _PACKET3_VC_ACTION_ENA@GOTPAGE
Lloh4:
	ldr	x11, [x11, _PACKET3_VC_ACTION_ENA@GOTPAGEOFF]
Lloh5:
	ldr	w11, [x11]
	orr	w9, w11, w9
Lloh6:
	adrp	x11, _PACKET3_SH_ACTION_ENA@GOTPAGE
Lloh7:
	ldr	x11, [x11, _PACKET3_SH_ACTION_ENA@GOTPAGEOFF]
Lloh8:
	ldr	w11, [x11]
	orr	w9, w9, w11
	ldr	x11, [x0]
Lloh9:
	adrp	x12, _CHIP_RV770@GOTPAGE
Lloh10:
	ldr	x12, [x12, _CHIP_RV770@GOTPAGEOFF]
Lloh11:
	ldr	x12, [x12]
	cmp	x11, x12
Lloh12:
	adrp	x11, _PACKET3_FULL_CACHE_ENA@GOTPAGE
Lloh13:
	ldr	x11, [x11, _PACKET3_FULL_CACHE_ENA@GOTPAGEOFF]
Lloh14:
	ldr	w11, [x11]
	csel	w11, wzr, w11, lt
	orr	w22, w9, w11
	cbz	x10, LBB0_2
; %bb.1:
	ldr	x9, [x21, #8]
	add	x8, x9, x8, lsl #3
	ldr	w21, [x8, #4]
Lloh15:
	adrp	x8, _PACKET3_SURFACE_SYNC@GOTPAGE
Lloh16:
	ldr	x8, [x8, _PACKET3_SURFACE_SYNC@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	mov	w1, #3
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_radeon_ring_write
	mov	x0, x19
	mov	x1, x22
	bl	_radeon_ring_write
	mov	x0, x19
	mov	w1, #-1
	bl	_radeon_ring_write
	mov	x0, x19
	mov	w1, #0
	bl	_radeon_ring_write
	mov	x0, x19
	mov	w1, #10
	bl	_radeon_ring_write
Lloh18:
	adrp	x8, _PACKET3_EVENT_WRITE_EOP@GOTPAGE
Lloh19:
	ldr	x8, [x8, _PACKET3_EVENT_WRITE_EOP@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
	mov	w1, #4
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_radeon_ring_write
Lloh21:
	adrp	x8, _CACHE_FLUSH_AND_INV_EVENT_TS@GOTPAGE
Lloh22:
	ldr	x8, [x8, _CACHE_FLUSH_AND_INV_EVENT_TS@GOTPAGEOFF]
Lloh23:
	ldr	w0, [x8]
	bl	_EVENT_TYPE
	mov	x22, x0
	mov	w0, #5
	bl	_EVENT_INDEX
	orr	w1, w0, w22
	mov	x0, x19
	bl	_radeon_ring_write
	mov	x0, x21
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_radeon_ring_write
	mov	x0, x21
	bl	_upper_32_bits
	and	w21, w0, #0xff
	mov	w0, #1
	bl	_DATA_SEL
	orr	w21, w21, w0
	mov	w0, #2
	bl	_INT_SEL
	orr	w1, w21, w0
	mov	x0, x19
	bl	_radeon_ring_write
	ldr	w1, [x20, #8]
	mov	x0, x19
	bl	_radeon_ring_write
	mov	w1, #0
	b	LBB0_3
LBB0_2:
Lloh24:
	adrp	x8, _PACKET3_SURFACE_SYNC@GOTPAGE
Lloh25:
	ldr	x8, [x8, _PACKET3_SURFACE_SYNC@GOTPAGEOFF]
Lloh26:
	ldr	w0, [x8]
	mov	w1, #3
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_radeon_ring_write
	mov	x0, x19
	mov	x1, x22
	bl	_radeon_ring_write
	mov	x0, x19
	mov	w1, #-1
	bl	_radeon_ring_write
	mov	x0, x19
	mov	w1, #0
	bl	_radeon_ring_write
	mov	x0, x19
	mov	w1, #10
	bl	_radeon_ring_write
Lloh27:
	adrp	x8, _PACKET3_EVENT_WRITE@GOTPAGE
Lloh28:
	ldr	x8, [x8, _PACKET3_EVENT_WRITE@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_radeon_ring_write
Lloh30:
	adrp	x8, _CACHE_FLUSH_AND_INV_EVENT@GOTPAGE
Lloh31:
	ldr	x8, [x8, _CACHE_FLUSH_AND_INV_EVENT@GOTPAGEOFF]
Lloh32:
	ldr	w0, [x8]
	bl	_EVENT_TYPE
	mov	x22, x0
	mov	w0, #0
	bl	_EVENT_INDEX
	orr	w1, w0, w22
	mov	x0, x19
	bl	_radeon_ring_write
Lloh33:
	adrp	x22, _PACKET3_SET_CONFIG_REG@GOTPAGE
Lloh34:
	ldr	x22, [x22, _PACKET3_SET_CONFIG_REG@GOTPAGEOFF]
	ldr	w0, [x22]
	mov	w1, #1
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_radeon_ring_write
Lloh35:
	adrp	x8, _WAIT_UNTIL@GOTPAGE
Lloh36:
	ldr	x8, [x8, _WAIT_UNTIL@GOTPAGEOFF]
Lloh37:
	ldr	w8, [x8]
Lloh38:
	adrp	x23, _PACKET3_SET_CONFIG_REG_OFFSET@GOTPAGE
Lloh39:
	ldr	x23, [x23, _PACKET3_SET_CONFIG_REG_OFFSET@GOTPAGEOFF]
	ldr	w9, [x23]
	sub	w8, w8, w9
	asr	w1, w8, #2
	mov	x0, x19
	bl	_radeon_ring_write
Lloh40:
	adrp	x8, _WAIT_3D_IDLE_bit@GOTPAGE
Lloh41:
	ldr	x8, [x8, _WAIT_3D_IDLE_bit@GOTPAGEOFF]
Lloh42:
	ldr	w8, [x8]
Lloh43:
	adrp	x9, _WAIT_3D_IDLECLEAN_bit@GOTPAGE
Lloh44:
	ldr	x9, [x9, _WAIT_3D_IDLECLEAN_bit@GOTPAGEOFF]
Lloh45:
	ldr	w9, [x9]
	orr	w1, w9, w8
	mov	x0, x19
	bl	_radeon_ring_write
	ldr	w0, [x22]
	mov	w1, #1
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_radeon_ring_write
	ldr	x8, [x21, #8]
	ldr	x9, [x20]
	lsl	x9, x9, #3
	ldr	w8, [x8, x9]
	ldr	w9, [x23]
	sub	w8, w8, w9
	asr	w1, w8, #2
	mov	x0, x19
	bl	_radeon_ring_write
	ldr	w1, [x20, #8]
	mov	x0, x19
	bl	_radeon_ring_write
Lloh46:
	adrp	x8, _CP_INT_STATUS@GOTPAGE
Lloh47:
	ldr	x8, [x8, _CP_INT_STATUS@GOTPAGEOFF]
Lloh48:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_radeon_ring_write
Lloh49:
	adrp	x8, _RB_INT_STAT@GOTPAGE
Lloh50:
	ldr	x8, [x8, _RB_INT_STAT@GOTPAGEOFF]
Lloh51:
	ldr	w1, [x8]
LBB0_3:
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_radeon_ring_write
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.cfi_endproc
                                        ; -- End function
	.comm	_PACKET3_TC_ACTION_ENA,4,2      ; @PACKET3_TC_ACTION_ENA
	.comm	_PACKET3_VC_ACTION_ENA,4,2      ; @PACKET3_VC_ACTION_ENA
	.comm	_PACKET3_SH_ACTION_ENA,4,2      ; @PACKET3_SH_ACTION_ENA
	.comm	_CHIP_RV770,8,3                 ; @CHIP_RV770
	.comm	_PACKET3_FULL_CACHE_ENA,4,2     ; @PACKET3_FULL_CACHE_ENA
	.comm	_PACKET3_SURFACE_SYNC,4,2       ; @PACKET3_SURFACE_SYNC
	.comm	_PACKET3_EVENT_WRITE_EOP,4,2    ; @PACKET3_EVENT_WRITE_EOP
	.comm	_CACHE_FLUSH_AND_INV_EVENT_TS,4,2 ; @CACHE_FLUSH_AND_INV_EVENT_TS
	.comm	_PACKET3_EVENT_WRITE,4,2        ; @PACKET3_EVENT_WRITE
	.comm	_CACHE_FLUSH_AND_INV_EVENT,4,2  ; @CACHE_FLUSH_AND_INV_EVENT
	.comm	_PACKET3_SET_CONFIG_REG,4,2     ; @PACKET3_SET_CONFIG_REG
	.comm	_WAIT_UNTIL,4,2                 ; @WAIT_UNTIL
	.comm	_PACKET3_SET_CONFIG_REG_OFFSET,4,2 ; @PACKET3_SET_CONFIG_REG_OFFSET
	.comm	_WAIT_3D_IDLE_bit,4,2           ; @WAIT_3D_IDLE_bit
	.comm	_WAIT_3D_IDLECLEAN_bit,4,2      ; @WAIT_3D_IDLECLEAN_bit
	.comm	_CP_INT_STATUS,4,2              ; @CP_INT_STATUS
	.comm	_RB_INT_STAT,4,2                ; @RB_INT_STAT
.subsections_via_symbols
