	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function iceland_check_s0_mc_reg_index
_iceland_check_s0_mc_reg_index:         ## @iceland_check_s0_mc_reg_index
	.cfi_startproc
## %bb.0:
	addl	$-128, %edi
	xorl	%eax, %eax
	cmpl	$19, %edi
	ja	LBB0_2
## %bb.1:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movslq	%edi, %rax
	leaq	l_switch.table.iceland_check_s0_mc_reg_index(%rip), %rcx
	movq	(%rcx,%rax,8), %rax
	movl	(%rax), %eax
	movl	%eax, (%rsi)
	movl	$1, %eax
	popq	%rbp
LBB0_2:
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_mmMC_SEQ_RAS_TIMING_LP,4,2     ## @mmMC_SEQ_RAS_TIMING_LP
	.comm	_mmMC_SEQ_DLL_STBY_LP,4,2       ## @mmMC_SEQ_DLL_STBY_LP
	.comm	_mmMC_SEQ_G5PDX_CMD0_LP,4,2     ## @mmMC_SEQ_G5PDX_CMD0_LP
	.comm	_mmMC_SEQ_G5PDX_CMD1_LP,4,2     ## @mmMC_SEQ_G5PDX_CMD1_LP
	.comm	_mmMC_SEQ_G5PDX_CTRL_LP,4,2     ## @mmMC_SEQ_G5PDX_CTRL_LP
	.comm	_mmMC_SEQ_CAS_TIMING_LP,4,2     ## @mmMC_SEQ_CAS_TIMING_LP
	.comm	_mmMC_SEQ_MISC_TIMING_LP,4,2    ## @mmMC_SEQ_MISC_TIMING_LP
	.comm	_mmMC_SEQ_MISC_TIMING2_LP,4,2   ## @mmMC_SEQ_MISC_TIMING2_LP
	.comm	_mmMC_SEQ_PMG_DVS_CMD_LP,4,2    ## @mmMC_SEQ_PMG_DVS_CMD_LP
	.comm	_mmMC_SEQ_PMG_DVS_CTL_LP,4,2    ## @mmMC_SEQ_PMG_DVS_CTL_LP
	.comm	_mmMC_SEQ_RD_CTL_D0_LP,4,2      ## @mmMC_SEQ_RD_CTL_D0_LP
	.comm	_mmMC_SEQ_RD_CTL_D1_LP,4,2      ## @mmMC_SEQ_RD_CTL_D1_LP
	.comm	_mmMC_SEQ_WR_CTL_D0_LP,4,2      ## @mmMC_SEQ_WR_CTL_D0_LP
	.comm	_mmMC_SEQ_WR_CTL_D1_LP,4,2      ## @mmMC_SEQ_WR_CTL_D1_LP
	.comm	_mmMC_SEQ_PMG_CMD_EMRS_LP,4,2   ## @mmMC_SEQ_PMG_CMD_EMRS_LP
	.comm	_mmMC_SEQ_PMG_CMD_MRS_LP,4,2    ## @mmMC_SEQ_PMG_CMD_MRS_LP
	.comm	_mmMC_SEQ_PMG_CMD_MRS1_LP,4,2   ## @mmMC_SEQ_PMG_CMD_MRS1_LP
	.comm	_mmMC_SEQ_PMG_TIMING_LP,4,2     ## @mmMC_SEQ_PMG_TIMING_LP
	.comm	_mmMC_SEQ_PMG_CMD_MRS2_LP,4,2   ## @mmMC_SEQ_PMG_CMD_MRS2_LP
	.comm	_mmMC_SEQ_WR_CTL_2_LP,4,2       ## @mmMC_SEQ_WR_CTL_2_LP
	.no_dead_strip	_iceland_check_s0_mc_reg_index
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.iceland_check_s0_mc_reg_index
l_switch.table.iceland_check_s0_mc_reg_index:
	.quad	_mmMC_SEQ_WR_CTL_D1_LP
	.quad	_mmMC_SEQ_WR_CTL_D0_LP
	.quad	_mmMC_SEQ_WR_CTL_2_LP
	.quad	_mmMC_SEQ_RD_CTL_D1_LP
	.quad	_mmMC_SEQ_RD_CTL_D0_LP
	.quad	_mmMC_SEQ_RAS_TIMING_LP
	.quad	_mmMC_SEQ_PMG_TIMING_LP
	.quad	_mmMC_SEQ_PMG_DVS_CTL_LP
	.quad	_mmMC_SEQ_PMG_DVS_CMD_LP
	.quad	_mmMC_SEQ_MISC_TIMING2_LP
	.quad	_mmMC_SEQ_MISC_TIMING_LP
	.quad	_mmMC_SEQ_G5PDX_CTRL_LP
	.quad	_mmMC_SEQ_G5PDX_CMD1_LP
	.quad	_mmMC_SEQ_G5PDX_CMD0_LP
	.quad	_mmMC_SEQ_DLL_STBY_LP
	.quad	_mmMC_SEQ_CAS_TIMING_LP
	.quad	_mmMC_SEQ_PMG_CMD_MRS2_LP
	.quad	_mmMC_SEQ_PMG_CMD_MRS1_LP
	.quad	_mmMC_SEQ_PMG_CMD_MRS_LP
	.quad	_mmMC_SEQ_PMG_CMD_EMRS_LP

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function iceland_check_s0_mc_reg_index
_iceland_check_s0_mc_reg_index:         ; @iceland_check_s0_mc_reg_index
	.cfi_startproc
; %bb.0:
	sub	w8, w0, #128
	cmp	w8, #19
	b.hi	LBB0_2
; %bb.1:
Lloh0:
	adrp	x9, l_switch.table.iceland_check_s0_mc_reg_index@PAGE
Lloh1:
	add	x9, x9, l_switch.table.iceland_check_s0_mc_reg_index@PAGEOFF
	ldr	x8, [x9, w8, sxtw #3]
	ldr	w8, [x8]
	str	w8, [x1]
	mov	w0, #1
	ret
LBB0_2:
	mov	w0, #0
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_mmMC_SEQ_RAS_TIMING_LP,4,2     ; @mmMC_SEQ_RAS_TIMING_LP
	.comm	_mmMC_SEQ_DLL_STBY_LP,4,2       ; @mmMC_SEQ_DLL_STBY_LP
	.comm	_mmMC_SEQ_G5PDX_CMD0_LP,4,2     ; @mmMC_SEQ_G5PDX_CMD0_LP
	.comm	_mmMC_SEQ_G5PDX_CMD1_LP,4,2     ; @mmMC_SEQ_G5PDX_CMD1_LP
	.comm	_mmMC_SEQ_G5PDX_CTRL_LP,4,2     ; @mmMC_SEQ_G5PDX_CTRL_LP
	.comm	_mmMC_SEQ_CAS_TIMING_LP,4,2     ; @mmMC_SEQ_CAS_TIMING_LP
	.comm	_mmMC_SEQ_MISC_TIMING_LP,4,2    ; @mmMC_SEQ_MISC_TIMING_LP
	.comm	_mmMC_SEQ_MISC_TIMING2_LP,4,2   ; @mmMC_SEQ_MISC_TIMING2_LP
	.comm	_mmMC_SEQ_PMG_DVS_CMD_LP,4,2    ; @mmMC_SEQ_PMG_DVS_CMD_LP
	.comm	_mmMC_SEQ_PMG_DVS_CTL_LP,4,2    ; @mmMC_SEQ_PMG_DVS_CTL_LP
	.comm	_mmMC_SEQ_RD_CTL_D0_LP,4,2      ; @mmMC_SEQ_RD_CTL_D0_LP
	.comm	_mmMC_SEQ_RD_CTL_D1_LP,4,2      ; @mmMC_SEQ_RD_CTL_D1_LP
	.comm	_mmMC_SEQ_WR_CTL_D0_LP,4,2      ; @mmMC_SEQ_WR_CTL_D0_LP
	.comm	_mmMC_SEQ_WR_CTL_D1_LP,4,2      ; @mmMC_SEQ_WR_CTL_D1_LP
	.comm	_mmMC_SEQ_PMG_CMD_EMRS_LP,4,2   ; @mmMC_SEQ_PMG_CMD_EMRS_LP
	.comm	_mmMC_SEQ_PMG_CMD_MRS_LP,4,2    ; @mmMC_SEQ_PMG_CMD_MRS_LP
	.comm	_mmMC_SEQ_PMG_CMD_MRS1_LP,4,2   ; @mmMC_SEQ_PMG_CMD_MRS1_LP
	.comm	_mmMC_SEQ_PMG_TIMING_LP,4,2     ; @mmMC_SEQ_PMG_TIMING_LP
	.comm	_mmMC_SEQ_PMG_CMD_MRS2_LP,4,2   ; @mmMC_SEQ_PMG_CMD_MRS2_LP
	.comm	_mmMC_SEQ_WR_CTL_2_LP,4,2       ; @mmMC_SEQ_WR_CTL_2_LP
	.no_dead_strip	_iceland_check_s0_mc_reg_index
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.iceland_check_s0_mc_reg_index
l_switch.table.iceland_check_s0_mc_reg_index:
	.quad	_mmMC_SEQ_WR_CTL_D1_LP
	.quad	_mmMC_SEQ_WR_CTL_D0_LP
	.quad	_mmMC_SEQ_WR_CTL_2_LP
	.quad	_mmMC_SEQ_RD_CTL_D1_LP
	.quad	_mmMC_SEQ_RD_CTL_D0_LP
	.quad	_mmMC_SEQ_RAS_TIMING_LP
	.quad	_mmMC_SEQ_PMG_TIMING_LP
	.quad	_mmMC_SEQ_PMG_DVS_CTL_LP
	.quad	_mmMC_SEQ_PMG_DVS_CMD_LP
	.quad	_mmMC_SEQ_MISC_TIMING2_LP
	.quad	_mmMC_SEQ_MISC_TIMING_LP
	.quad	_mmMC_SEQ_G5PDX_CTRL_LP
	.quad	_mmMC_SEQ_G5PDX_CMD1_LP
	.quad	_mmMC_SEQ_G5PDX_CMD0_LP
	.quad	_mmMC_SEQ_DLL_STBY_LP
	.quad	_mmMC_SEQ_CAS_TIMING_LP
	.quad	_mmMC_SEQ_PMG_CMD_MRS2_LP
	.quad	_mmMC_SEQ_PMG_CMD_MRS1_LP
	.quad	_mmMC_SEQ_PMG_CMD_MRS_LP
	.quad	_mmMC_SEQ_PMG_CMD_EMRS_LP

.subsections_via_symbols
