	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function si_pcie_gen3_enable
_si_pcie_gen3_enable:                   ## @si_pcie_gen3_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	8(%rdi), %rax
	movq	(%rax), %rdi
	movq	(%rdi), %r15
	callq	_pci_is_root_bus
	testq	%rax, %rax
	jne	LBB0_35
## %bb.1:
	movq	_radeon_pcie_gen2@GOTPCREL(%rip), %rax
	cmpq	$0, (%rax)
	je	LBB0_35
## %bb.2:
	movl	(%r12), %eax
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_3
LBB0_35:
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_3:
	movq	_RADEON_IS_PCIE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_35
## %bb.4:
	movq	%r15, %rdi
	callq	_pcie_get_speed_cap
	movl	%eax, %ebx
	movq	_PCI_SPEED_UNKNOWN@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	je	LBB0_35
## %bb.5:
	movq	_PCIE_SPEED_8_0GT@GOTPCREL(%rip), %rcx
	movq	_PCIE_SPEED_5_0GT@GOTPCREL(%rip), %rax
	cmpl	(%rcx), %ebx
	je	LBB0_7
## %bb.6:
	cmpl	(%rax), %ebx
	jne	LBB0_35
LBB0_7:
	movq	_PCIE_LC_SPEED_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PCIE_PORT
	movl	%eax, %r13d
	movq	_LC_CURRENT_DATA_RATE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	andl	%r13d, %r14d
	movq	_LC_CURRENT_DATA_RATE_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarl	%cl, %r14d
	movq	_PCIE_SPEED_8_0GT@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	jne	LBB0_10
## %bb.8:
	cmpl	$2, %r14d
	jne	LBB0_9
## %bb.36:
	leaq	L_.str(%rip), %rdi
	jmp	LBB0_37
LBB0_10:
	movq	_PCIE_SPEED_5_0GT@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	jne	LBB0_14
## %bb.11:
	cmpl	$1, %r14d
	jne	LBB0_12
## %bb.38:
	leaq	L_.str.2(%rip), %rdi
LBB0_37:
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_DRM_INFO                       ## TAILCALL
LBB0_9:
	leaq	L_.str.1(%rip), %rdi
	jmp	LBB0_13
LBB0_12:
	leaq	L_.str.3(%rip), %rdi
LBB0_13:
	callq	_DRM_INFO
LBB0_14:
	movl	%r13d, -72(%rbp)                ## 4-byte Spill
	movq	%r15, %rdi
	callq	_pci_pcie_cap
	testl	%eax, %eax
	je	LBB0_35
## %bb.15:
	movl	%eax, %r13d
	movq	8(%r12), %rdi
	callq	_pci_pcie_cap
	testl	%eax, %eax
	je	LBB0_35
## %bb.16:
	movl	%eax, %ecx
	movq	_PCIE_SPEED_8_0GT@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	jne	LBB0_18
## %bb.17:
	cmpl	$2, %r14d
	je	LBB0_18
## %bb.19:
	movl	%ebx, -68(%rbp)                 ## 4-byte Spill
	movslq	%r13d, %rbx
	movq	_PCI_EXP_LNKCTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rax, %r14
	addq	%rbx, %rsi
	leaq	-52(%rbp), %rdx
	movq	%r15, %rdi
	movl	%ecx, %r13d
	callq	_pci_read_config_word
	movq	8(%r12), %rdi
	movslq	%r13d, %r13
	movq	(%r14), %rsi
	addq	%r13, %rsi
	leaq	-48(%rbp), %rdx
	callq	_pci_read_config_word
	movq	_PCI_EXP_LNKCTL_HAWD@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	orl	-52(%rbp), %edx
	movl	%edx, -44(%rbp)
	movq	_PCI_EXP_LNKCTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, -96(%rbp)                 ## 8-byte Spill
	addq	%rbx, %rsi
	movq	%r15, %rdi
	callq	_pci_write_config_word
	movl	(%r14), %edx
	orl	-48(%rbp), %edx
	movl	%edx, -44(%rbp)
	movq	8(%r12), %rdi
	movq	_PCI_EXP_LNKCTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	%r13, %rsi
	callq	_pci_write_config_word
	movq	_PCIE_LC_STATUS1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PCIE
	movq	_LC_DETECTED_LINK_WIDTH_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	andl	%eax, %ebx
	movq	_LC_DETECTED_LINK_WIDTH_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %ebx
	movq	_LC_OPERATING_LINK_WIDTH_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_LC_OPERATING_LINK_WIDTH_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	cmpl	%ebx, %eax
	jge	LBB0_22
## %bb.20:
	movq	_PCIE_LC_LINK_WIDTH_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_RENEGOTIATION_SUPPORT@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_22
## %bb.21:
	movq	_LC_LINK_WIDTH_MASK@GOTPCREL(%rip), %rcx
	movq	_LC_UPCONFIGURE_DIS@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	notl	%edx
	movq	_LC_LINK_WIDTH_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %ebx
	andl	%edx, %eax
	orl	%eax, %ebx
	movq	_LC_UPCONFIGURE_SUPPORT@GOTPCREL(%rip), %rax
	movq	_LC_RENEGOTIATE_EN@GOTPCREL(%rip), %rcx
	orl	(%rax), %ebx
	orl	(%rcx), %ebx
	movq	_LC_RECONFIG_NOW@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	(%r14), %edi
	movl	%ebx, %esi
	callq	_WREG32_PCIE_PORT
LBB0_22:
	movl	$10, %ebx
	movq	%r13, -64(%rbp)                 ## 8-byte Spill
LBB0_23:                                ## =>This Inner Loop Header: Depth=1
	movq	8(%r12), %rdi
	movq	_PCI_EXP_DEVSTA@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	%r13, %rsi
	leaq	-44(%rbp), %rdx
	callq	_pci_read_config_word
	movq	_PCI_EXP_DEVSTA_TRPND@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, -44(%rbp)
	jne	LBB0_25
## %bb.24:                              ##   in Loop: Header=BB0_23 Depth=1
	movl	%ebx, -76(%rbp)                 ## 4-byte Spill
	movq	_PCI_EXP_LNKCTL@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rsi
	movq	-96(%rbp), %r13                 ## 8-byte Reload
	addq	%r13, %rsi
	movq	%r15, %rdi
	leaq	-52(%rbp), %rdx
	callq	_pci_read_config_word
	movq	8(%r12), %rdi
	movq	(%rbx), %rsi
	movq	%rbx, %r14
	addq	-64(%rbp), %rsi                 ## 8-byte Folded Reload
	leaq	-48(%rbp), %rdx
	callq	_pci_read_config_word
	movq	_PCI_EXP_LNKCTL2@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rax, %rbx
	addq	%r13, %rsi
	movq	%r15, %rdi
	leaq	-84(%rbp), %rdx
	callq	_pci_read_config_word
	movq	8(%r12), %rdi
	movq	(%rbx), %rsi
	addq	-64(%rbp), %rsi                 ## 8-byte Folded Reload
	leaq	-80(%rbp), %rdx
	callq	_pci_read_config_word
	movq	_PCIE_LC_CNTL4@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_SET_QUIESCE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PCIE_PORT
	movl	(%rbx), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_REDO_EQ@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PCIE_PORT
	movl	$100, %edi
	callq	_msleep
	movq	(%r14), %rsi
	addq	%r13, %rsi
	movq	%r15, %rdi
	leaq	-44(%rbp), %r14
	movq	%r14, %rdx
	callq	_pci_read_config_word
	movl	-44(%rbp), %eax
	movl	-52(%rbp), %edx
	xorl	%eax, %edx
	movq	_PCI_EXP_LNKCTL_HAWD@GOTPCREL(%rip), %rbx
	andl	(%rbx), %edx
	xorl	%eax, %edx
	movl	%edx, -44(%rbp)
	movq	_PCI_EXP_LNKCTL@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rsi
	addq	%r13, %rsi
	movq	%r15, %rdi
	callq	_pci_write_config_word
	movq	8(%r12), %rdi
	movq	(%rbx), %rsi
	addq	-64(%rbp), %rsi                 ## 8-byte Folded Reload
	movq	%r14, %rdx
	callq	_pci_read_config_word
	movl	-44(%rbp), %eax
	movl	-48(%rbp), %edx
	xorl	%eax, %edx
	movq	_PCI_EXP_LNKCTL_HAWD@GOTPCREL(%rip), %rcx
	andl	(%rcx), %edx
	movl	-76(%rbp), %ebx                 ## 4-byte Reload
	xorl	%eax, %edx
	movl	%edx, -44(%rbp)
	movq	8(%r12), %rdi
	movq	_PCI_EXP_LNKCTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	-64(%rbp), %rsi                 ## 8-byte Folded Reload
	callq	_pci_write_config_word
	movq	_PCI_EXP_LNKCTL2@GOTPCREL(%rip), %r14
	movq	(%r14), %rsi
	addq	%r13, %rsi
	movq	%r15, %rdi
	leaq	-44(%rbp), %rdx
	callq	_pci_read_config_word
	movl	-44(%rbp), %eax
	movl	$-3601, %ecx                    ## imm = 0xF1EF
	andl	%ecx, %eax
	movl	-84(%rbp), %edx
	movl	$3600, %ecx                     ## imm = 0xE10
	andl	%ecx, %edx
	orl	%eax, %edx
	movl	%edx, -44(%rbp)
	movq	(%r14), %rsi
	addq	%r13, %rsi
	movq	-64(%rbp), %r13                 ## 8-byte Reload
	movq	%r15, %rdi
	callq	_pci_write_config_word
	movq	8(%r12), %rdi
	movq	(%r14), %rsi
	addq	%r13, %rsi
	leaq	-44(%rbp), %rdx
	callq	_pci_read_config_word
	movl	-44(%rbp), %eax
	movl	$-3601, %ecx                    ## imm = 0xF1EF
	andl	%ecx, %eax
	movl	-80(%rbp), %edx
	movl	$3600, %ecx                     ## imm = 0xE10
	andl	%ecx, %edx
	orl	%eax, %edx
	movl	%edx, -44(%rbp)
	movq	8(%r12), %rdi
	movq	(%r14), %rsi
	addq	%r13, %rsi
	callq	_pci_write_config_word
	movq	_PCIE_LC_CNTL4@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_SET_QUIESCE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r14), %edi
	callq	_WREG32_PCIE_PORT
	decl	%ebx
	jne	LBB0_23
LBB0_25:
	movl	-68(%rbp), %ebx                 ## 4-byte Reload
	jmp	LBB0_26
LBB0_18:
	movslq	%ecx, %r13
LBB0_26:
	movq	_LC_FORCE_EN_SW_SPEED_CHANGE@GOTPCREL(%rip), %rax
	movl	-72(%rbp), %ecx                 ## 4-byte Reload
	orl	(%rax), %ecx
	movq	_LC_FORCE_DIS_HW_SPEED_CHANGE@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_LC_FORCE_DIS_SW_SPEED_CHANGE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	%ecx, %esi
	movq	_PCIE_LC_SPEED_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32_PCIE_PORT
	movq	8(%r12), %rdi
	movq	_PCI_EXP_LNKCTL2@GOTPCREL(%rip), %r14
	movq	(%r14), %rsi
	addq	%r13, %rsi
	leaq	-44(%rbp), %rdx
	callq	_pci_read_config_word
	movl	-44(%rbp), %edx
	andl	$-16, %edx
	movq	_PCIE_SPEED_8_0GT@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	jne	LBB0_28
## %bb.27:
	orl	$3, %edx
	jmp	LBB0_31
LBB0_28:
	movq	_PCIE_SPEED_5_0GT@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	jne	LBB0_30
## %bb.29:
	orl	$2, %edx
	jmp	LBB0_31
LBB0_30:
	orl	$1, %edx
LBB0_31:
	movl	%edx, -44(%rbp)
	movq	8(%r12), %rdi
	addq	(%r14), %r13
	movq	%r13, %rsi
	callq	_pci_write_config_word
	movq	_PCIE_LC_SPEED_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_INITIATE_LINK_SPEED_CHANGE@GOTPCREL(%rip), %r14
	orl	(%r14), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PCIE_PORT
	cmpl	$0, 4(%r12)
	jle	LBB0_35
## %bb.32:
	xorl	%ebx, %ebx
LBB0_33:                                ## =>This Inner Loop Header: Depth=1
	movq	_PCIE_LC_SPEED_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PCIE_PORT
	testl	%eax, (%r14)
	je	LBB0_35
## %bb.34:                              ##   in Loop: Header=BB0_33 Depth=1
	movl	$1, %edi
	callq	_udelay
	incl	%ebx
	cmpl	4(%r12), %ebx
	jl	LBB0_33
	jmp	LBB0_35
	.cfi_endproc
                                        ## -- End function
	.comm	_radeon_pcie_gen2,8,3           ## @radeon_pcie_gen2
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
	.comm	_RADEON_IS_PCIE,4,2             ## @RADEON_IS_PCIE
	.comm	_PCI_SPEED_UNKNOWN,4,2          ## @PCI_SPEED_UNKNOWN
	.comm	_PCIE_SPEED_8_0GT,4,2           ## @PCIE_SPEED_8_0GT
	.comm	_PCIE_SPEED_5_0GT,4,2           ## @PCIE_SPEED_5_0GT
	.comm	_PCIE_LC_SPEED_CNTL,4,2         ## @PCIE_LC_SPEED_CNTL
	.comm	_LC_CURRENT_DATA_RATE_MASK,4,2  ## @LC_CURRENT_DATA_RATE_MASK
	.comm	_LC_CURRENT_DATA_RATE_SHIFT,4,2 ## @LC_CURRENT_DATA_RATE_SHIFT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"PCIE gen 3 link speeds already enabled\n"

L_.str.1:                               ## @.str.1
	.asciz	"enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n"

L_.str.2:                               ## @.str.2
	.asciz	"PCIE gen 2 link speeds already enabled\n"

L_.str.3:                               ## @.str.3
	.asciz	"enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"

	.comm	_PCI_EXP_LNKCTL,8,3             ## @PCI_EXP_LNKCTL
	.comm	_PCI_EXP_LNKCTL_HAWD,4,2        ## @PCI_EXP_LNKCTL_HAWD
	.comm	_PCIE_LC_STATUS1,4,2            ## @PCIE_LC_STATUS1
	.comm	_LC_DETECTED_LINK_WIDTH_MASK,4,2 ## @LC_DETECTED_LINK_WIDTH_MASK
	.comm	_LC_DETECTED_LINK_WIDTH_SHIFT,4,2 ## @LC_DETECTED_LINK_WIDTH_SHIFT
	.comm	_LC_OPERATING_LINK_WIDTH_MASK,4,2 ## @LC_OPERATING_LINK_WIDTH_MASK
	.comm	_LC_OPERATING_LINK_WIDTH_SHIFT,4,2 ## @LC_OPERATING_LINK_WIDTH_SHIFT
	.comm	_PCIE_LC_LINK_WIDTH_CNTL,4,2    ## @PCIE_LC_LINK_WIDTH_CNTL
	.comm	_LC_RENEGOTIATION_SUPPORT,4,2   ## @LC_RENEGOTIATION_SUPPORT
	.comm	_LC_LINK_WIDTH_MASK,4,2         ## @LC_LINK_WIDTH_MASK
	.comm	_LC_UPCONFIGURE_DIS,4,2         ## @LC_UPCONFIGURE_DIS
	.comm	_LC_LINK_WIDTH_SHIFT,4,2        ## @LC_LINK_WIDTH_SHIFT
	.comm	_LC_UPCONFIGURE_SUPPORT,4,2     ## @LC_UPCONFIGURE_SUPPORT
	.comm	_LC_RENEGOTIATE_EN,4,2          ## @LC_RENEGOTIATE_EN
	.comm	_LC_RECONFIG_NOW,4,2            ## @LC_RECONFIG_NOW
	.comm	_PCI_EXP_DEVSTA,8,3             ## @PCI_EXP_DEVSTA
	.comm	_PCI_EXP_DEVSTA_TRPND,4,2       ## @PCI_EXP_DEVSTA_TRPND
	.comm	_PCI_EXP_LNKCTL2,8,3            ## @PCI_EXP_LNKCTL2
	.comm	_PCIE_LC_CNTL4,4,2              ## @PCIE_LC_CNTL4
	.comm	_LC_SET_QUIESCE,4,2             ## @LC_SET_QUIESCE
	.comm	_LC_REDO_EQ,4,2                 ## @LC_REDO_EQ
	.comm	_LC_FORCE_EN_SW_SPEED_CHANGE,4,2 ## @LC_FORCE_EN_SW_SPEED_CHANGE
	.comm	_LC_FORCE_DIS_HW_SPEED_CHANGE,4,2 ## @LC_FORCE_DIS_HW_SPEED_CHANGE
	.comm	_LC_FORCE_DIS_SW_SPEED_CHANGE,4,2 ## @LC_FORCE_DIS_SW_SPEED_CHANGE
	.comm	_LC_INITIATE_LINK_SPEED_CHANGE,4,2 ## @LC_INITIATE_LINK_SPEED_CHANGE
	.no_dead_strip	_si_pcie_gen3_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function si_pcie_gen3_enable
_si_pcie_gen3_enable:                   ; @si_pcie_gen3_enable
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #128
	.cfi_def_cfa_offset 128
	stp	x28, x27, [sp, #32]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #48]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #64]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #80]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #96]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #112]            ; 16-byte Folded Spill
	add	x29, sp, #112
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	x8, [x0, #8]
	ldr	x0, [x8]
	ldr	x21, [x0]
	bl	_pci_is_root_bus
Lloh0:
	adrp	x8, _radeon_pcie_gen2@GOTPAGE
Lloh1:
	ldr	x8, [x8, _radeon_pcie_gen2@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	cmp	x0, #0
	ccmp	x8, #0, #4, eq
	b.eq	LBB0_2
; %bb.1:
	ldr	w8, [x19]
Lloh3:
	adrp	x9, _RADEON_IS_IGP@GOTPAGE
Lloh4:
	ldr	x9, [x9, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_3
LBB0_2:
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	ret
LBB0_3:
Lloh6:
	adrp	x9, _RADEON_IS_PCIE@GOTPAGE
Lloh7:
	ldr	x9, [x9, _RADEON_IS_PCIE@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.4:
	mov	x0, x21
	bl	_pcie_get_speed_cap
Lloh9:
	adrp	x8, _PCI_SPEED_UNKNOWN@GOTPAGE
Lloh10:
	ldr	x8, [x8, _PCI_SPEED_UNKNOWN@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	cmp	w0, w8
	b.eq	LBB0_2
; %bb.5:
	mov	x20, x0
Lloh12:
	adrp	x27, _PCIE_SPEED_8_0GT@GOTPAGE
Lloh13:
	ldr	x27, [x27, _PCIE_SPEED_8_0GT@GOTPAGEOFF]
	ldr	w8, [x27]
Lloh14:
	adrp	x26, _PCIE_SPEED_5_0GT@GOTPAGE
Lloh15:
	ldr	x26, [x26, _PCIE_SPEED_5_0GT@GOTPAGEOFF]
	ldr	w9, [x26]
	cmp	w0, w8
	ccmp	w0, w9, #4, ne
	b.ne	LBB0_2
; %bb.6:
Lloh16:
	adrp	x25, _PCIE_LC_SPEED_CNTL@GOTPAGE
Lloh17:
	ldr	x25, [x25, _PCIE_LC_SPEED_CNTL@GOTPAGEOFF]
	ldr	w0, [x25]
	bl	_RREG32_PCIE_PORT
	mov	x28, x0
Lloh18:
	adrp	x8, _LC_CURRENT_DATA_RATE_MASK@GOTPAGE
Lloh19:
	ldr	x8, [x8, _LC_CURRENT_DATA_RATE_MASK@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh21:
	adrp	x9, _LC_CURRENT_DATA_RATE_SHIFT@GOTPAGE
Lloh22:
	ldr	x9, [x9, _LC_CURRENT_DATA_RATE_SHIFT@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	asr	w22, w8, w9
	ldr	w8, [x27]
	cmp	w20, w8
	b.ne	LBB0_9
; %bb.7:
	cmp	w22, #2
	b.ne	LBB0_13
; %bb.8:
Lloh24:
	adrp	x0, l_.str@PAGE
Lloh25:
	add	x0, x0, l_.str@PAGEOFF
	b	LBB0_12
LBB0_9:
	ldr	w8, [x26]
	cmp	w20, w8
	b.ne	LBB0_16
; %bb.10:
	cmp	w22, #1
	b.ne	LBB0_14
; %bb.11:
Lloh26:
	adrp	x0, l_.str.2@PAGE
Lloh27:
	add	x0, x0, l_.str.2@PAGEOFF
LBB0_12:
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	b	_DRM_INFO
LBB0_13:
Lloh28:
	adrp	x0, l_.str.1@PAGE
Lloh29:
	add	x0, x0, l_.str.1@PAGEOFF
	b	LBB0_15
LBB0_14:
Lloh30:
	adrp	x0, l_.str.3@PAGE
Lloh31:
	add	x0, x0, l_.str.3@PAGEOFF
LBB0_15:
	bl	_DRM_INFO
LBB0_16:
	mov	x0, x21
	bl	_pci_pcie_cap
	cbz	w0, LBB0_2
; %bb.17:
	mov	x24, x0
	ldr	x0, [x19, #8]
	bl	_pci_pcie_cap
	cbz	w0, LBB0_2
; %bb.18:
	mov	x23, x0
	str	w28, [sp, #8]                   ; 4-byte Folded Spill
	ldr	w8, [x27]
	cmp	w20, w8
	b.ne	LBB0_27
; %bb.19:
	cmp	w22, #2
	b.eq	LBB0_27
; %bb.20:
	str	w20, [sp, #4]                   ; 4-byte Folded Spill
	sxtw	x24, w24
Lloh32:
	adrp	x25, _PCI_EXP_LNKCTL@GOTPAGE
Lloh33:
	ldr	x25, [x25, _PCI_EXP_LNKCTL@GOTPAGEOFF]
	ldr	x8, [x25]
	add	x1, x8, x24
	add	x2, sp, #24
	mov	x0, x21
	bl	_pci_read_config_word
	ldr	x0, [x19, #8]
                                        ; kill: def $w23 killed $w23 killed $x23 def $x23
	sxtw	x23, w23
	ldr	x8, [x25]
	add	x1, x8, x23
	add	x2, sp, #20
	bl	_pci_read_config_word
Lloh34:
	adrp	x22, _PCI_EXP_LNKCTL_HAWD@GOTPAGE
Lloh35:
	ldr	x22, [x22, _PCI_EXP_LNKCTL_HAWD@GOTPAGEOFF]
	ldr	w8, [sp, #24]
	ldr	w9, [x22]
	orr	w2, w9, w8
	str	w2, [sp, #28]
	ldr	x8, [x25]
	add	x1, x8, x24
	mov	x0, x21
	bl	_pci_write_config_word
	ldr	w8, [sp, #20]
	ldr	w9, [x22]
	orr	w2, w9, w8
	str	w2, [sp, #28]
	ldr	x0, [x19, #8]
	ldr	x8, [x25]
	add	x1, x8, x23
	bl	_pci_write_config_word
Lloh36:
	adrp	x8, _PCIE_LC_STATUS1@GOTPAGE
Lloh37:
	ldr	x8, [x8, _PCIE_LC_STATUS1@GOTPAGEOFF]
Lloh38:
	ldr	w0, [x8]
	bl	_RREG32_PCIE
Lloh39:
	adrp	x8, _LC_DETECTED_LINK_WIDTH_MASK@GOTPAGE
Lloh40:
	ldr	x8, [x8, _LC_DETECTED_LINK_WIDTH_MASK@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
Lloh42:
	adrp	x9, _LC_DETECTED_LINK_WIDTH_SHIFT@GOTPAGE
Lloh43:
	ldr	x9, [x9, _LC_DETECTED_LINK_WIDTH_SHIFT@GOTPAGEOFF]
	and	w8, w8, w0
Lloh44:
	ldr	w9, [x9]
	asr	w22, w8, w9
Lloh45:
	adrp	x8, _LC_OPERATING_LINK_WIDTH_MASK@GOTPAGE
Lloh46:
	ldr	x8, [x8, _LC_OPERATING_LINK_WIDTH_MASK@GOTPAGEOFF]
Lloh47:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh48:
	adrp	x9, _LC_OPERATING_LINK_WIDTH_SHIFT@GOTPAGE
Lloh49:
	ldr	x9, [x9, _LC_OPERATING_LINK_WIDTH_SHIFT@GOTPAGEOFF]
Lloh50:
	ldr	w9, [x9]
	asr	w8, w8, w9
	cmp	w8, w22
	b.ge	LBB0_23
; %bb.21:
Lloh51:
	adrp	x26, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGE
Lloh52:
	ldr	x26, [x26, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGEOFF]
	ldr	w0, [x26]
	bl	_RREG32_PCIE_PORT
Lloh53:
	adrp	x8, _LC_RENEGOTIATION_SUPPORT@GOTPAGE
Lloh54:
	ldr	x8, [x8, _LC_RENEGOTIATION_SUPPORT@GOTPAGEOFF]
Lloh55:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_23
; %bb.22:
Lloh56:
	adrp	x8, _LC_LINK_WIDTH_MASK@GOTPAGE
Lloh57:
	ldr	x8, [x8, _LC_LINK_WIDTH_MASK@GOTPAGEOFF]
Lloh58:
	ldr	w8, [x8]
Lloh59:
	adrp	x9, _LC_UPCONFIGURE_DIS@GOTPAGE
Lloh60:
	ldr	x9, [x9, _LC_UPCONFIGURE_DIS@GOTPAGEOFF]
Lloh61:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
Lloh62:
	adrp	x9, _LC_LINK_WIDTH_SHIFT@GOTPAGE
Lloh63:
	ldr	x9, [x9, _LC_LINK_WIDTH_SHIFT@GOTPAGEOFF]
Lloh64:
	ldr	w9, [x9]
	lsl	w9, w22, w9
Lloh65:
	adrp	x10, _LC_UPCONFIGURE_SUPPORT@GOTPAGE
Lloh66:
	ldr	x10, [x10, _LC_UPCONFIGURE_SUPPORT@GOTPAGEOFF]
Lloh67:
	ldr	w10, [x10]
Lloh68:
	adrp	x11, _LC_RENEGOTIATE_EN@GOTPAGE
Lloh69:
	ldr	x11, [x11, _LC_RENEGOTIATE_EN@GOTPAGEOFF]
Lloh70:
	ldr	w11, [x11]
Lloh71:
	adrp	x12, _LC_RECONFIG_NOW@GOTPAGE
Lloh72:
	ldr	x12, [x12, _LC_RECONFIG_NOW@GOTPAGEOFF]
Lloh73:
	ldr	w12, [x12]
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w1, w8, w12
	ldr	w0, [x26]
	bl	_WREG32_PCIE_PORT
LBB0_23:
	mov	w22, #10
Lloh74:
	adrp	x25, _PCI_EXP_LNKCTL2@GOTPAGE
Lloh75:
	ldr	x25, [x25, _PCI_EXP_LNKCTL2@GOTPAGEOFF]
Lloh76:
	adrp	x20, _PCIE_LC_CNTL4@GOTPAGE
Lloh77:
	ldr	x20, [x20, _PCIE_LC_CNTL4@GOTPAGEOFF]
Lloh78:
	adrp	x28, _LC_SET_QUIESCE@GOTPAGE
Lloh79:
	ldr	x28, [x28, _LC_SET_QUIESCE@GOTPAGEOFF]
LBB0_24:                                ; =>This Inner Loop Header: Depth=1
	ldr	x0, [x19, #8]
Lloh80:
	adrp	x8, _PCI_EXP_DEVSTA@GOTPAGE
Lloh81:
	ldr	x8, [x8, _PCI_EXP_DEVSTA@GOTPAGEOFF]
Lloh82:
	ldr	x8, [x8]
	add	x1, x8, x23
	add	x2, sp, #28
	bl	_pci_read_config_word
	ldr	w8, [sp, #28]
Lloh83:
	adrp	x9, _PCI_EXP_DEVSTA_TRPND@GOTPAGE
Lloh84:
	ldr	x9, [x9, _PCI_EXP_DEVSTA_TRPND@GOTPAGEOFF]
Lloh85:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_26
; %bb.25:                               ;   in Loop: Header=BB0_24 Depth=1
Lloh86:
	adrp	x27, _PCI_EXP_LNKCTL@GOTPAGE
Lloh87:
	ldr	x27, [x27, _PCI_EXP_LNKCTL@GOTPAGEOFF]
	ldr	x8, [x27]
	add	x1, x8, x24
	add	x2, sp, #24
	mov	x0, x21
	bl	_pci_read_config_word
	ldr	x0, [x19, #8]
	ldr	x8, [x27]
	add	x1, x8, x23
	add	x2, sp, #20
	bl	_pci_read_config_word
	ldr	x8, [x25]
	add	x1, x8, x24
	add	x2, sp, #16
	mov	x0, x21
	bl	_pci_read_config_word
	ldr	x0, [x19, #8]
	ldr	x8, [x25]
	add	x1, x8, x23
	add	x2, sp, #12
	bl	_pci_read_config_word
	ldr	w0, [x20]
	bl	_RREG32_PCIE_PORT
	ldr	w8, [x28]
	orr	w1, w8, w0
	ldr	w0, [x20]
	bl	_WREG32_PCIE_PORT
	ldr	w0, [x20]
	bl	_RREG32_PCIE_PORT
Lloh88:
	adrp	x8, _LC_REDO_EQ@GOTPAGE
Lloh89:
	ldr	x8, [x8, _LC_REDO_EQ@GOTPAGEOFF]
Lloh90:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x20]
	bl	_WREG32_PCIE_PORT
	mov	w0, #100
	bl	_msleep
	ldr	x8, [x27]
	add	x1, x8, x24
	add	x2, sp, #28
	mov	x0, x21
	bl	_pci_read_config_word
Lloh91:
	adrp	x26, _PCI_EXP_LNKCTL_HAWD@GOTPAGE
Lloh92:
	ldr	x26, [x26, _PCI_EXP_LNKCTL_HAWD@GOTPAGEOFF]
	ldr	w8, [x26]
	ldp	w10, w9, [sp, #24]
	bic	w9, w9, w8
	and	w8, w10, w8
	orr	w2, w8, w9
	str	w2, [sp, #28]
	ldr	x8, [x27]
	add	x1, x8, x24
	mov	x0, x21
	bl	_pci_write_config_word
	ldr	x0, [x19, #8]
	ldr	x8, [x27]
	add	x1, x8, x23
	add	x2, sp, #28
	bl	_pci_read_config_word
	ldr	w8, [x26]
	ldr	w9, [sp, #28]
	bic	w9, w9, w8
	ldr	w10, [sp, #20]
	and	w8, w10, w8
	orr	w2, w8, w9
	str	w2, [sp, #28]
	ldr	x0, [x19, #8]
	ldr	x8, [x27]
	add	x1, x8, x23
	bl	_pci_write_config_word
	ldr	x8, [x25]
	add	x1, x8, x24
	add	x2, sp, #28
	mov	x0, x21
	bl	_pci_read_config_word
	ldr	w8, [sp, #28]
	mov	w26, #-3601
	and	w8, w8, w26
	ldr	w9, [sp, #16]
	mov	w27, #3600
	and	w9, w9, w27
	orr	w2, w9, w8
	str	w2, [sp, #28]
	ldr	x8, [x25]
	add	x1, x8, x24
	mov	x0, x21
	bl	_pci_write_config_word
	ldr	x0, [x19, #8]
	ldr	x8, [x25]
	add	x1, x8, x23
	add	x2, sp, #28
	bl	_pci_read_config_word
	ldr	w8, [sp, #28]
	and	w8, w8, w26
	ldr	w9, [sp, #12]
	and	w9, w9, w27
	orr	w2, w9, w8
	str	w2, [sp, #28]
	ldr	x0, [x19, #8]
	ldr	x8, [x25]
	add	x1, x8, x23
	bl	_pci_write_config_word
	ldr	w0, [x20]
	bl	_RREG32_PCIE_PORT
	ldr	w8, [x28]
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32_PCIE_PORT
	subs	w22, w22, #1
	b.ne	LBB0_24
LBB0_26:
Lloh93:
	adrp	x25, _PCIE_LC_SPEED_CNTL@GOTPAGE
Lloh94:
	ldr	x25, [x25, _PCIE_LC_SPEED_CNTL@GOTPAGEOFF]
Lloh95:
	adrp	x26, _PCIE_SPEED_5_0GT@GOTPAGE
Lloh96:
	ldr	x26, [x26, _PCIE_SPEED_5_0GT@GOTPAGEOFF]
Lloh97:
	adrp	x27, _PCIE_SPEED_8_0GT@GOTPAGE
Lloh98:
	ldr	x27, [x27, _PCIE_SPEED_8_0GT@GOTPAGEOFF]
	ldr	w20, [sp, #4]                   ; 4-byte Folded Reload
	b	LBB0_28
LBB0_27:
	sxtw	x23, w23
LBB0_28:
Lloh99:
	adrp	x8, _LC_FORCE_EN_SW_SPEED_CHANGE@GOTPAGE
Lloh100:
	ldr	x8, [x8, _LC_FORCE_EN_SW_SPEED_CHANGE@GOTPAGEOFF]
Lloh101:
	ldr	w8, [x8]
Lloh102:
	adrp	x9, _LC_FORCE_DIS_HW_SPEED_CHANGE@GOTPAGE
Lloh103:
	ldr	x9, [x9, _LC_FORCE_DIS_HW_SPEED_CHANGE@GOTPAGEOFF]
Lloh104:
	ldr	w9, [x9]
	ldr	w10, [sp, #8]                   ; 4-byte Folded Reload
	orr	w8, w8, w10
	orr	w8, w8, w9
Lloh105:
	adrp	x9, _LC_FORCE_DIS_SW_SPEED_CHANGE@GOTPAGE
Lloh106:
	ldr	x9, [x9, _LC_FORCE_DIS_SW_SPEED_CHANGE@GOTPAGEOFF]
Lloh107:
	ldr	w9, [x9]
	bic	w1, w8, w9
	ldr	w0, [x25]
	bl	_WREG32_PCIE_PORT
	ldr	x0, [x19, #8]
Lloh108:
	adrp	x8, _PCI_EXP_LNKCTL2@GOTPAGE
Lloh109:
	ldr	x8, [x8, _PCI_EXP_LNKCTL2@GOTPAGEOFF]
Lloh110:
	ldr	x8, [x8]
	add	x1, x8, x23
	add	x2, sp, #28
	bl	_pci_read_config_word
	ldr	w8, [sp, #28]
	and	w8, w8, #0xfffffff0
	ldr	w9, [x27]
	cmp	w20, w9
	b.ne	LBB0_30
; %bb.29:
	orr	w2, w8, #0x3
	b	LBB0_33
LBB0_30:
	ldr	w9, [x26]
	cmp	w20, w9
	b.ne	LBB0_32
; %bb.31:
	orr	w2, w8, #0x2
	b	LBB0_33
LBB0_32:
	orr	w2, w8, #0x1
LBB0_33:
	str	w2, [sp, #28]
	ldr	x0, [x19, #8]
Lloh111:
	adrp	x8, _PCI_EXP_LNKCTL2@GOTPAGE
Lloh112:
	ldr	x8, [x8, _PCI_EXP_LNKCTL2@GOTPAGEOFF]
Lloh113:
	ldr	x8, [x8]
	add	x1, x8, x23
	bl	_pci_write_config_word
	ldr	w0, [x25]
	bl	_RREG32_PCIE_PORT
Lloh114:
	adrp	x20, _LC_INITIATE_LINK_SPEED_CHANGE@GOTPAGE
Lloh115:
	ldr	x20, [x20, _LC_INITIATE_LINK_SPEED_CHANGE@GOTPAGEOFF]
	ldr	w8, [x20]
	orr	w1, w8, w0
	ldr	w0, [x25]
	bl	_WREG32_PCIE_PORT
	ldr	w8, [x19, #4]
	cmp	w8, #1
	b.lt	LBB0_2
; %bb.34:
	mov	w21, #0
LBB0_35:                                ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x25]
	bl	_RREG32_PCIE_PORT
	ldr	w8, [x20]
	tst	w8, w0
	b.eq	LBB0_2
; %bb.36:                               ;   in Loop: Header=BB0_35 Depth=1
	mov	w0, #1
	bl	_udelay
	add	w21, w21, #1
	ldr	w8, [x19, #4]
	cmp	w21, w8
	b.lt	LBB0_35
	b	LBB0_2
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpAdd	Lloh24, Lloh25
	.loh AdrpAdd	Lloh26, Lloh27
	.loh AdrpAdd	Lloh28, Lloh29
	.loh AdrpAdd	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGot	Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGot	Lloh78, Lloh79
	.loh AdrpLdrGot	Lloh76, Lloh77
	.loh AdrpLdrGot	Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGot	Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGot	Lloh86, Lloh87
	.loh AdrpLdrGot	Lloh97, Lloh98
	.loh AdrpLdrGot	Lloh95, Lloh96
	.loh AdrpLdrGot	Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGot	Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.cfi_endproc
                                        ; -- End function
	.comm	_radeon_pcie_gen2,8,3           ; @radeon_pcie_gen2
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
	.comm	_RADEON_IS_PCIE,4,2             ; @RADEON_IS_PCIE
	.comm	_PCI_SPEED_UNKNOWN,4,2          ; @PCI_SPEED_UNKNOWN
	.comm	_PCIE_SPEED_8_0GT,4,2           ; @PCIE_SPEED_8_0GT
	.comm	_PCIE_SPEED_5_0GT,4,2           ; @PCIE_SPEED_5_0GT
	.comm	_PCIE_LC_SPEED_CNTL,4,2         ; @PCIE_LC_SPEED_CNTL
	.comm	_LC_CURRENT_DATA_RATE_MASK,4,2  ; @LC_CURRENT_DATA_RATE_MASK
	.comm	_LC_CURRENT_DATA_RATE_SHIFT,4,2 ; @LC_CURRENT_DATA_RATE_SHIFT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"PCIE gen 3 link speeds already enabled\n"

l_.str.1:                               ; @.str.1
	.asciz	"enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n"

l_.str.2:                               ; @.str.2
	.asciz	"PCIE gen 2 link speeds already enabled\n"

l_.str.3:                               ; @.str.3
	.asciz	"enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"

	.comm	_PCI_EXP_LNKCTL,8,3             ; @PCI_EXP_LNKCTL
	.comm	_PCI_EXP_LNKCTL_HAWD,4,2        ; @PCI_EXP_LNKCTL_HAWD
	.comm	_PCIE_LC_STATUS1,4,2            ; @PCIE_LC_STATUS1
	.comm	_LC_DETECTED_LINK_WIDTH_MASK,4,2 ; @LC_DETECTED_LINK_WIDTH_MASK
	.comm	_LC_DETECTED_LINK_WIDTH_SHIFT,4,2 ; @LC_DETECTED_LINK_WIDTH_SHIFT
	.comm	_LC_OPERATING_LINK_WIDTH_MASK,4,2 ; @LC_OPERATING_LINK_WIDTH_MASK
	.comm	_LC_OPERATING_LINK_WIDTH_SHIFT,4,2 ; @LC_OPERATING_LINK_WIDTH_SHIFT
	.comm	_PCIE_LC_LINK_WIDTH_CNTL,4,2    ; @PCIE_LC_LINK_WIDTH_CNTL
	.comm	_LC_RENEGOTIATION_SUPPORT,4,2   ; @LC_RENEGOTIATION_SUPPORT
	.comm	_LC_LINK_WIDTH_MASK,4,2         ; @LC_LINK_WIDTH_MASK
	.comm	_LC_UPCONFIGURE_DIS,4,2         ; @LC_UPCONFIGURE_DIS
	.comm	_LC_LINK_WIDTH_SHIFT,4,2        ; @LC_LINK_WIDTH_SHIFT
	.comm	_LC_UPCONFIGURE_SUPPORT,4,2     ; @LC_UPCONFIGURE_SUPPORT
	.comm	_LC_RENEGOTIATE_EN,4,2          ; @LC_RENEGOTIATE_EN
	.comm	_LC_RECONFIG_NOW,4,2            ; @LC_RECONFIG_NOW
	.comm	_PCI_EXP_DEVSTA,8,3             ; @PCI_EXP_DEVSTA
	.comm	_PCI_EXP_DEVSTA_TRPND,4,2       ; @PCI_EXP_DEVSTA_TRPND
	.comm	_PCI_EXP_LNKCTL2,8,3            ; @PCI_EXP_LNKCTL2
	.comm	_PCIE_LC_CNTL4,4,2              ; @PCIE_LC_CNTL4
	.comm	_LC_SET_QUIESCE,4,2             ; @LC_SET_QUIESCE
	.comm	_LC_REDO_EQ,4,2                 ; @LC_REDO_EQ
	.comm	_LC_FORCE_EN_SW_SPEED_CHANGE,4,2 ; @LC_FORCE_EN_SW_SPEED_CHANGE
	.comm	_LC_FORCE_DIS_HW_SPEED_CHANGE,4,2 ; @LC_FORCE_DIS_HW_SPEED_CHANGE
	.comm	_LC_FORCE_DIS_SW_SPEED_CHANGE,4,2 ; @LC_FORCE_DIS_SW_SPEED_CHANGE
	.comm	_LC_INITIATE_LINK_SPEED_CHANGE,4,2 ; @LC_INITIATE_LINK_SPEED_CHANGE
	.no_dead_strip	_si_pcie_gen3_enable
.subsections_via_symbols
