	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v2_0_pause_dpg_mode
_vcn_v2_0_pause_dpg_mode:               ## @vcn_v2_0_pause_dpg_mode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	(%rdi), %rsi
	movq	(%r14), %rdx
	cmpq	%rdx, %rsi
	je	LBB0_5
## %bb.1:
	movq	%rdi, %r15
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG
	movq	_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmUVD_DPG_PAUSE@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK@GOTPCREL(%rip), %r13
	movl	(%r13), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movq	(%r14), %rax
	movq	_VCN_DPG_STATE__PAUSE@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_3
## %bb.2:
	movq	_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmUVD_POWER_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_UVD_POWER_STATUS__UVD_POWER_STATUS_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	xorl	%esi, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	_SOC15_WAIT_ON_RREG
	movq	_UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	movl	%ebx, %ecx
	callq	_WREG32_SOC15
	movq	_UVD@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movl	(%r12), %edx
	movl	(%r13), %ecx
	xorl	%esi, %esi
	movl	%ecx, %r8d
	xorl	%r9d, %r9d
	callq	_SOC15_WAIT_ON_RREG
	movq	8(%r15), %rax
	movq	(%rax), %r13
	movl	(%rbx), %edi
	movq	_mmUVD_RB_BASE_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r13), %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%rbx), %ebx
	movq	_mmUVD_RB_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	(%r13), %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	_UVD@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	movq	%r12, %rbx
	movq	_mmUVD_RB_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	4(%r13), %eax
	leal	3(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$2, %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r12), %ebx
	movq	_mmUVD_RB_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	8(%r13), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_mmUVD_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	8(%r13), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	8(%r15), %rax
	movq	(%rax), %rbx
	movq	_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmUVD_RB_BASE_LO2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	12(%rbx), %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movq	_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	_mmUVD_RB_BASE_HI2@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	12(%rbx), %edi
	callq	_upper_32_bits
	movl	%r13d, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	_UVD@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	movq	_mmUVD_RB_SIZE2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	16(%rbx), %eax
	leal	3(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$2, %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r12), %r13d
	movq	_mmUVD_RB_RPTR2@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	20(%rbx), %edi
	callq	_lower_32_bits
	movl	%r13d, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	_mmUVD_RB_WPTR2@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	20(%rbx), %edi
	callq	_lower_32_bits
	movl	%r13d, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_mmUVD_RBC_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	_mmUVD_SCRATCH2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%ebx, %edi
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	andl	$2147483647, %eax               ## imm = 0x7FFFFFFF
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmUVD_POWER_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	_UVD_POWER_STATUS__UVD_POWER_STATUS_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	xorl	%esi, %esi
	xorl	%r9d, %r9d
	callq	_SOC15_WAIT_ON_RREG
	jmp	LBB0_4
LBB0_3:
	movq	_UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %ebx
	movq	_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	movl	%ebx, %ecx
	callq	_WREG32_SOC15
LBB0_4:
	movq	(%r14), %rax
	movq	%rax, (%r15)
LBB0_5:
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"dpg pause state changed %d -> %d"

	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_DPG_PAUSE,4,2            ## @mmUVD_DPG_PAUSE
	.comm	_UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,4,2 ## @UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK
	.comm	_VCN_DPG_STATE__PAUSE,8,3       ## @VCN_DPG_STATE__PAUSE
	.comm	_mmUVD_POWER_STATUS,4,2         ## @mmUVD_POWER_STATUS
	.comm	_UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,4,2 ## @UVD_POWER_STATUS__UVD_POWER_STATUS_MASK
	.comm	_UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK,4,2 ## @UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK
	.comm	_mmUVD_RB_BASE_LO,4,2           ## @mmUVD_RB_BASE_LO
	.comm	_mmUVD_RB_BASE_HI,4,2           ## @mmUVD_RB_BASE_HI
	.comm	_mmUVD_RB_SIZE,4,2              ## @mmUVD_RB_SIZE
	.comm	_mmUVD_RB_RPTR,4,2              ## @mmUVD_RB_RPTR
	.comm	_mmUVD_RB_WPTR,4,2              ## @mmUVD_RB_WPTR
	.comm	_mmUVD_RB_BASE_LO2,4,2          ## @mmUVD_RB_BASE_LO2
	.comm	_mmUVD_RB_BASE_HI2,4,2          ## @mmUVD_RB_BASE_HI2
	.comm	_mmUVD_RB_SIZE2,4,2             ## @mmUVD_RB_SIZE2
	.comm	_mmUVD_RB_RPTR2,4,2             ## @mmUVD_RB_RPTR2
	.comm	_mmUVD_RB_WPTR2,4,2             ## @mmUVD_RB_WPTR2
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ## @mmUVD_RBC_RB_WPTR
	.comm	_mmUVD_SCRATCH2,4,2             ## @mmUVD_SCRATCH2
	.comm	_UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,4,2 ## @UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON
	.no_dead_strip	_vcn_v2_0_pause_dpg_mode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v2_0_pause_dpg_mode
_vcn_v2_0_pause_dpg_mode:               ; @vcn_v2_0_pause_dpg_mode
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x1
	ldr	x1, [x0]
	ldr	x2, [x20]
	cmp	x1, x2
	b.eq	LBB0_5
; %bb.1:
	mov	x19, x0
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG
Lloh2:
	adrp	x23, _UVD@GOTPAGE
Lloh3:
	ldr	x23, [x23, _UVD@GOTPAGEOFF]
	ldr	w0, [x23]
Lloh4:
	adrp	x21, _mmUVD_DPG_PAUSE@GOTPAGE
Lloh5:
	ldr	x21, [x21, _mmUVD_DPG_PAUSE@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh6:
	adrp	x22, _UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK@GOTPAGE
Lloh7:
	ldr	x22, [x22, _UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK@GOTPAGEOFF]
	ldr	w8, [x22]
	bic	w26, w0, w8
	ldr	x8, [x20]
Lloh8:
	adrp	x9, _VCN_DPG_STATE__PAUSE@GOTPAGE
Lloh9:
	ldr	x9, [x9, _VCN_DPG_STATE__PAUSE@GOTPAGEOFF]
Lloh10:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_3
; %bb.2:
	ldr	w0, [x23]
Lloh11:
	adrp	x25, _mmUVD_POWER_STATUS@GOTPAGE
Lloh12:
	ldr	x25, [x25, _mmUVD_POWER_STATUS@GOTPAGEOFF]
	ldr	w2, [x25]
Lloh13:
	adrp	x24, _UVD_POWER_STATUS__UVD_POWER_STATUS_MASK@GOTPAGE
Lloh14:
	ldr	x24, [x24, _UVD_POWER_STATUS__UVD_POWER_STATUS_MASK@GOTPAGEOFF]
	ldr	w4, [x24]
	mov	w1, #0
	mov	w3, #1
	mov	w5, #0
	bl	_SOC15_WAIT_ON_RREG
Lloh15:
	adrp	x8, _UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK@GOTPAGE
Lloh16:
	ldr	x8, [x8, _UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	orr	w3, w8, w26
	ldr	w0, [x23]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x23]
	ldr	w2, [x21]
	ldr	w3, [x22]
	mov	w1, #0
	mov	x4, x3
	mov	w5, #0
	bl	_SOC15_WAIT_ON_RREG
	ldr	x8, [x19, #8]
	ldr	x26, [x8]
	ldr	w0, [x23]
Lloh18:
	adrp	x8, _mmUVD_RB_BASE_LO@GOTPAGE
Lloh19:
	ldr	x8, [x8, _mmUVD_RB_BASE_LO@GOTPAGEOFF]
Lloh20:
	ldr	w2, [x8]
	ldr	w3, [x26]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w21, [x23]
Lloh21:
	adrp	x8, _mmUVD_RB_BASE_HI@GOTPAGE
Lloh22:
	ldr	x8, [x8, _mmUVD_RB_BASE_HI@GOTPAGEOFF]
Lloh23:
	ldr	w22, [x8]
	ldr	w0, [x26]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x21
	mov	w1, #0
	mov	x2, x22
	bl	_WREG32_SOC15
	ldr	w0, [x23]
Lloh24:
	adrp	x8, _mmUVD_RB_SIZE@GOTPAGE
Lloh25:
	ldr	x8, [x8, _mmUVD_RB_SIZE@GOTPAGEOFF]
Lloh26:
	ldr	w2, [x8]
	ldr	w8, [x26, #4]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w3, w8, #2
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w21, [x23]
Lloh27:
	adrp	x8, _mmUVD_RB_RPTR@GOTPAGE
Lloh28:
	ldr	x8, [x8, _mmUVD_RB_RPTR@GOTPAGEOFF]
Lloh29:
	ldr	w22, [x8]
	ldr	w0, [x26, #8]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x21
	mov	w1, #0
	mov	x2, x22
	bl	_WREG32_SOC15
	ldr	w21, [x23]
Lloh30:
	adrp	x8, _mmUVD_RB_WPTR@GOTPAGE
Lloh31:
	ldr	x8, [x8, _mmUVD_RB_WPTR@GOTPAGEOFF]
Lloh32:
	ldr	w22, [x8]
	ldr	w0, [x26, #8]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x21
	mov	w1, #0
	mov	x2, x22
	bl	_WREG32_SOC15
	ldr	x8, [x19, #8]
	ldr	x26, [x8]
	ldr	w0, [x23]
Lloh33:
	adrp	x8, _mmUVD_RB_BASE_LO2@GOTPAGE
Lloh34:
	ldr	x8, [x8, _mmUVD_RB_BASE_LO2@GOTPAGEOFF]
Lloh35:
	ldr	w2, [x8]
	ldr	w3, [x26, #12]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w21, [x23]
Lloh36:
	adrp	x8, _mmUVD_RB_BASE_HI2@GOTPAGE
Lloh37:
	ldr	x8, [x8, _mmUVD_RB_BASE_HI2@GOTPAGEOFF]
Lloh38:
	ldr	w22, [x8]
	ldr	w0, [x26, #12]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x21
	mov	w1, #0
	mov	x2, x22
	bl	_WREG32_SOC15
	ldr	w0, [x23]
Lloh39:
	adrp	x8, _mmUVD_RB_SIZE2@GOTPAGE
Lloh40:
	ldr	x8, [x8, _mmUVD_RB_SIZE2@GOTPAGEOFF]
Lloh41:
	ldr	w2, [x8]
	ldr	w8, [x26, #16]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w3, w8, #2
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w21, [x23]
Lloh42:
	adrp	x8, _mmUVD_RB_RPTR2@GOTPAGE
Lloh43:
	ldr	x8, [x8, _mmUVD_RB_RPTR2@GOTPAGEOFF]
Lloh44:
	ldr	w22, [x8]
	ldr	w0, [x26, #20]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x21
	mov	w1, #0
	mov	x2, x22
	bl	_WREG32_SOC15
	ldr	w21, [x23]
Lloh45:
	adrp	x8, _mmUVD_RB_WPTR2@GOTPAGE
Lloh46:
	ldr	x8, [x8, _mmUVD_RB_WPTR2@GOTPAGEOFF]
Lloh47:
	ldr	w22, [x8]
	ldr	w0, [x26, #20]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x21
	mov	w1, #0
	mov	x2, x22
	bl	_WREG32_SOC15
	ldr	w21, [x23]
Lloh48:
	adrp	x8, _mmUVD_RBC_RB_WPTR@GOTPAGE
Lloh49:
	ldr	x8, [x8, _mmUVD_RBC_RB_WPTR@GOTPAGEOFF]
Lloh50:
	ldr	w22, [x8]
Lloh51:
	adrp	x8, _mmUVD_SCRATCH2@GOTPAGE
Lloh52:
	ldr	x8, [x8, _mmUVD_SCRATCH2@GOTPAGEOFF]
Lloh53:
	ldr	w2, [x8]
	mov	x0, x21
	mov	w1, #0
	bl	_RREG32_SOC15
	and	w3, w0, #0x7fffffff
	mov	x0, x21
	mov	w1, #0
	mov	x2, x22
	bl	_WREG32_SOC15
	ldr	w0, [x23]
	ldr	w2, [x25]
Lloh54:
	adrp	x8, _UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON@GOTPAGE
Lloh55:
	ldr	x8, [x8, _UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON@GOTPAGEOFF]
Lloh56:
	ldr	w3, [x8]
	ldr	w4, [x24]
	mov	w1, #0
	mov	w5, #0
	bl	_SOC15_WAIT_ON_RREG
	b	LBB0_4
LBB0_3:
Lloh57:
	adrp	x8, _UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK@GOTPAGE
Lloh58:
	ldr	x8, [x8, _UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK@GOTPAGEOFF]
Lloh59:
	ldr	w8, [x8]
	bic	w3, w26, w8
	ldr	w0, [x23]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_WREG32_SOC15
LBB0_4:
	ldr	x8, [x20]
	str	x8, [x19]
LBB0_5:
	mov	w0, #0
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"dpg pause state changed %d -> %d"

	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_DPG_PAUSE,4,2            ; @mmUVD_DPG_PAUSE
	.comm	_UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,4,2 ; @UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK
	.comm	_VCN_DPG_STATE__PAUSE,8,3       ; @VCN_DPG_STATE__PAUSE
	.comm	_mmUVD_POWER_STATUS,4,2         ; @mmUVD_POWER_STATUS
	.comm	_UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,4,2 ; @UVD_POWER_STATUS__UVD_POWER_STATUS_MASK
	.comm	_UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK,4,2 ; @UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK
	.comm	_mmUVD_RB_BASE_LO,4,2           ; @mmUVD_RB_BASE_LO
	.comm	_mmUVD_RB_BASE_HI,4,2           ; @mmUVD_RB_BASE_HI
	.comm	_mmUVD_RB_SIZE,4,2              ; @mmUVD_RB_SIZE
	.comm	_mmUVD_RB_RPTR,4,2              ; @mmUVD_RB_RPTR
	.comm	_mmUVD_RB_WPTR,4,2              ; @mmUVD_RB_WPTR
	.comm	_mmUVD_RB_BASE_LO2,4,2          ; @mmUVD_RB_BASE_LO2
	.comm	_mmUVD_RB_BASE_HI2,4,2          ; @mmUVD_RB_BASE_HI2
	.comm	_mmUVD_RB_SIZE2,4,2             ; @mmUVD_RB_SIZE2
	.comm	_mmUVD_RB_RPTR2,4,2             ; @mmUVD_RB_RPTR2
	.comm	_mmUVD_RB_WPTR2,4,2             ; @mmUVD_RB_WPTR2
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ; @mmUVD_RBC_RB_WPTR
	.comm	_mmUVD_SCRATCH2,4,2             ; @mmUVD_SCRATCH2
	.comm	_UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,4,2 ; @UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON
	.no_dead_strip	_vcn_v2_0_pause_dpg_mode
.subsections_via_symbols
