	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function uvd_v6_0_enable_clock_gating
_uvd_v6_0_enable_clock_gating:          ## @uvd_v6_0_enable_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %ebx
	movq	%rdi, %r15
	movq	_mmUVD_SUVD_CGC_GATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -60(%rbp)                 ## 4-byte Spill
	movq	_mmUVD_CGC_GATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_UVD_SUVD_CGC_GATE__SRE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_UVD_SUVD_CGC_GATE__SIT_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, -56(%rbp)                 ## 4-byte Spill
	movq	_UVD_SUVD_CGC_GATE__SMP_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movq	_UVD_SUVD_CGC_GATE__SCM_MASK@GOTPCREL(%rip), %rdi
	movl	(%rdi), %edi
	movq	_UVD_SUVD_CGC_GATE__SDB_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r8d
	movq	_UVD_SUVD_CGC_GATE__SRE_H264_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r9d
	movq	_UVD_SUVD_CGC_GATE__SRE_HEVC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r10d
	movq	_UVD_SUVD_CGC_GATE__SIT_H264_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r11d
	movq	_UVD_SUVD_CGC_GATE__SIT_HEVC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r12d
	movq	_UVD_SUVD_CGC_GATE__SCM_H264_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r13d
	movq	_UVD_SUVD_CGC_GATE__SCM_HEVC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r14d
	movq	_UVD_SUVD_CGC_GATE__SDB_H264_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, -52(%rbp)                 ## 4-byte Spill
	movq	_UVD_SUVD_CGC_GATE__SDB_HEVC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ebx, %ebx
	je	LBB0_1
## %bb.2:
	movl	%edx, -44(%rbp)                 ## 4-byte Spill
	movl	%ecx, -48(%rbp)                 ## 4-byte Spill
	movq	_UVD_CGC_GATE__SYS_MASK@GOTPCREL(%rip), %rdx
	movq	_AMD_PG_SUPPORT_UVD@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	movq	_UVD_CGC_GATE__JPEG2_MASK@GOTPCREL(%rip), %rcx
	andl	(%r15), %ebx
	je	LBB0_4
## %bb.3:
	movq	%rcx, %r15
	movq	_UVD_CGC_GATE__VCPU_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	movq	%r15, %rcx
LBB0_4:
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__UDEC_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__MPEG2_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__RBC_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__LMI_MC_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__LMI_UMC_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__IDCT_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__MPRD_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__MPC_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__LBSI_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__LRBBM_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__UDEC_RE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__UDEC_CM_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__UDEC_IT_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__UDEC_DB_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__UDEC_MP_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__WCB_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__JPEG_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_GATE__SCPU_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	orl	(%rcx), %eax
	orl	%ebx, %eax
	movq	_UVD_CGC_GATE__REGS_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	-48(%rbp), %ecx                 ## 4-byte Reload
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	jmp	LBB0_5
LBB0_1:
	xorl	%ebx, %ebx
LBB0_5:
	orl	-60(%rbp), %esi                 ## 4-byte Folded Reload
	orl	-56(%rbp), %esi                 ## 4-byte Folded Reload
	orl	%edx, %esi
	orl	%edi, %esi
	orl	%r8d, %esi
	orl	%r9d, %esi
	orl	%r10d, %esi
	orl	%r11d, %esi
	orl	%r12d, %esi
	orl	%r13d, %esi
	orl	%r14d, %esi
	orl	-52(%rbp), %esi                 ## 4-byte Folded Reload
	orl	%ecx, %esi
	movq	_mmUVD_SUVD_CGC_GATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32
	movq	_mmUVD_CGC_GATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_mmUVD_SUVD_CGC_GATE,4,2        ## @mmUVD_SUVD_CGC_GATE
	.comm	_mmUVD_CGC_GATE,4,2             ## @mmUVD_CGC_GATE
	.comm	_UVD_SUVD_CGC_GATE__SRE_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SRE_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SIT_MASK
	.comm	_UVD_SUVD_CGC_GATE__SMP_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SMP_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SCM_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SDB_MASK
	.comm	_UVD_SUVD_CGC_GATE__SRE_H264_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SRE_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SRE_HEVC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_H264_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SIT_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_HEVC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_H264_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SCM_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_HEVC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_H264_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SDB_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_HEVC_MASK,4,2 ## @UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
	.comm	_UVD_CGC_GATE__SYS_MASK,4,2     ## @UVD_CGC_GATE__SYS_MASK
	.comm	_UVD_CGC_GATE__UDEC_MASK,4,2    ## @UVD_CGC_GATE__UDEC_MASK
	.comm	_UVD_CGC_GATE__MPEG2_MASK,4,2   ## @UVD_CGC_GATE__MPEG2_MASK
	.comm	_UVD_CGC_GATE__RBC_MASK,4,2     ## @UVD_CGC_GATE__RBC_MASK
	.comm	_UVD_CGC_GATE__LMI_MC_MASK,4,2  ## @UVD_CGC_GATE__LMI_MC_MASK
	.comm	_UVD_CGC_GATE__LMI_UMC_MASK,4,2 ## @UVD_CGC_GATE__LMI_UMC_MASK
	.comm	_UVD_CGC_GATE__IDCT_MASK,4,2    ## @UVD_CGC_GATE__IDCT_MASK
	.comm	_UVD_CGC_GATE__MPRD_MASK,4,2    ## @UVD_CGC_GATE__MPRD_MASK
	.comm	_UVD_CGC_GATE__MPC_MASK,4,2     ## @UVD_CGC_GATE__MPC_MASK
	.comm	_UVD_CGC_GATE__LBSI_MASK,4,2    ## @UVD_CGC_GATE__LBSI_MASK
	.comm	_UVD_CGC_GATE__LRBBM_MASK,4,2   ## @UVD_CGC_GATE__LRBBM_MASK
	.comm	_UVD_CGC_GATE__UDEC_RE_MASK,4,2 ## @UVD_CGC_GATE__UDEC_RE_MASK
	.comm	_UVD_CGC_GATE__UDEC_CM_MASK,4,2 ## @UVD_CGC_GATE__UDEC_CM_MASK
	.comm	_UVD_CGC_GATE__UDEC_IT_MASK,4,2 ## @UVD_CGC_GATE__UDEC_IT_MASK
	.comm	_UVD_CGC_GATE__UDEC_DB_MASK,4,2 ## @UVD_CGC_GATE__UDEC_DB_MASK
	.comm	_UVD_CGC_GATE__UDEC_MP_MASK,4,2 ## @UVD_CGC_GATE__UDEC_MP_MASK
	.comm	_UVD_CGC_GATE__WCB_MASK,4,2     ## @UVD_CGC_GATE__WCB_MASK
	.comm	_UVD_CGC_GATE__JPEG_MASK,4,2    ## @UVD_CGC_GATE__JPEG_MASK
	.comm	_UVD_CGC_GATE__SCPU_MASK,4,2    ## @UVD_CGC_GATE__SCPU_MASK
	.comm	_UVD_CGC_GATE__JPEG2_MASK,4,2   ## @UVD_CGC_GATE__JPEG2_MASK
	.comm	_AMD_PG_SUPPORT_UVD,4,2         ## @AMD_PG_SUPPORT_UVD
	.comm	_UVD_CGC_GATE__VCPU_MASK,4,2    ## @UVD_CGC_GATE__VCPU_MASK
	.comm	_UVD_CGC_GATE__REGS_MASK,4,2    ## @UVD_CGC_GATE__REGS_MASK
	.no_dead_strip	_uvd_v6_0_enable_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function uvd_v6_0_enable_clock_gating
_uvd_v6_0_enable_clock_gating:          ; @uvd_v6_0_enable_clock_gating
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #144
	.cfi_def_cfa_offset 144
	stp	x28, x27, [sp, #48]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #64]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #80]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #96]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #112]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #128]            ; 16-byte Folded Spill
	add	x29, sp, #128
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x1
	mov	x20, x0
Lloh0:
	adrp	x19, _mmUVD_SUVD_CGC_GATE@GOTPAGE
Lloh1:
	ldr	x19, [x19, _mmUVD_SUVD_CGC_GATE@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32
	mov	x23, x0
Lloh2:
	adrp	x22, _mmUVD_CGC_GATE@GOTPAGE
Lloh3:
	ldr	x22, [x22, _mmUVD_CGC_GATE@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_RREG32
Lloh4:
	adrp	x8, _UVD_SUVD_CGC_GATE__SRE_MASK@GOTPAGE
Lloh5:
	ldr	x8, [x8, _UVD_SUVD_CGC_GATE__SRE_MASK@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
Lloh7:
	adrp	x9, _UVD_SUVD_CGC_GATE__SIT_MASK@GOTPAGE
Lloh8:
	ldr	x9, [x9, _UVD_SUVD_CGC_GATE__SIT_MASK@GOTPAGEOFF]
Lloh9:
	ldr	w9, [x9]
Lloh10:
	adrp	x10, _UVD_SUVD_CGC_GATE__SMP_MASK@GOTPAGE
Lloh11:
	ldr	x10, [x10, _UVD_SUVD_CGC_GATE__SMP_MASK@GOTPAGEOFF]
Lloh12:
	ldr	w10, [x10]
Lloh13:
	adrp	x11, _UVD_SUVD_CGC_GATE__SCM_MASK@GOTPAGE
Lloh14:
	ldr	x11, [x11, _UVD_SUVD_CGC_GATE__SCM_MASK@GOTPAGEOFF]
Lloh15:
	ldr	w11, [x11]
Lloh16:
	adrp	x12, _UVD_SUVD_CGC_GATE__SDB_MASK@GOTPAGE
Lloh17:
	ldr	x12, [x12, _UVD_SUVD_CGC_GATE__SDB_MASK@GOTPAGEOFF]
Lloh18:
	ldr	w12, [x12]
Lloh19:
	adrp	x13, _UVD_SUVD_CGC_GATE__SRE_H264_MASK@GOTPAGE
Lloh20:
	ldr	x13, [x13, _UVD_SUVD_CGC_GATE__SRE_H264_MASK@GOTPAGEOFF]
Lloh21:
	ldr	w13, [x13]
Lloh22:
	adrp	x14, _UVD_SUVD_CGC_GATE__SRE_HEVC_MASK@GOTPAGE
Lloh23:
	ldr	x14, [x14, _UVD_SUVD_CGC_GATE__SRE_HEVC_MASK@GOTPAGEOFF]
Lloh24:
	ldr	w14, [x14]
Lloh25:
	adrp	x15, _UVD_SUVD_CGC_GATE__SIT_H264_MASK@GOTPAGE
Lloh26:
	ldr	x15, [x15, _UVD_SUVD_CGC_GATE__SIT_H264_MASK@GOTPAGEOFF]
Lloh27:
	ldr	w15, [x15]
Lloh28:
	adrp	x16, _UVD_SUVD_CGC_GATE__SIT_HEVC_MASK@GOTPAGE
Lloh29:
	ldr	x16, [x16, _UVD_SUVD_CGC_GATE__SIT_HEVC_MASK@GOTPAGEOFF]
Lloh30:
	ldr	w16, [x16]
Lloh31:
	adrp	x17, _UVD_SUVD_CGC_GATE__SCM_H264_MASK@GOTPAGE
Lloh32:
	ldr	x17, [x17, _UVD_SUVD_CGC_GATE__SCM_H264_MASK@GOTPAGEOFF]
Lloh33:
	ldr	w17, [x17]
Lloh34:
	adrp	x1, _UVD_SUVD_CGC_GATE__SCM_HEVC_MASK@GOTPAGE
Lloh35:
	ldr	x1, [x1, _UVD_SUVD_CGC_GATE__SCM_HEVC_MASK@GOTPAGEOFF]
Lloh36:
	ldr	w6, [x1]
Lloh37:
	adrp	x2, _UVD_SUVD_CGC_GATE__SDB_H264_MASK@GOTPAGE
Lloh38:
	ldr	x2, [x2, _UVD_SUVD_CGC_GATE__SDB_H264_MASK@GOTPAGEOFF]
Lloh39:
	ldr	w1, [x2]
Lloh40:
	adrp	x3, _UVD_SUVD_CGC_GATE__SDB_HEVC_MASK@GOTPAGE
Lloh41:
	ldr	x3, [x3, _UVD_SUVD_CGC_GATE__SDB_HEVC_MASK@GOTPAGEOFF]
Lloh42:
	ldr	w2, [x3]
	cbz	w21, LBB0_2
; %bb.1:
	str	w0, [sp, #36]                   ; 4-byte Folded Spill
Lloh43:
	adrp	x4, _UVD_CGC_GATE__SYS_MASK@GOTPAGE
Lloh44:
	ldr	x4, [x4, _UVD_CGC_GATE__SYS_MASK@GOTPAGEOFF]
Lloh45:
	adrp	x5, _UVD_CGC_GATE__UDEC_MASK@GOTPAGE
Lloh46:
	ldr	x5, [x5, _UVD_CGC_GATE__UDEC_MASK@GOTPAGEOFF]
Lloh47:
	ldr	w3, [x4]
Lloh48:
	ldr	w0, [x5]
	stp	w3, w0, [sp, #28]               ; 8-byte Folded Spill
Lloh49:
	adrp	x0, _UVD_CGC_GATE__MPEG2_MASK@GOTPAGE
Lloh50:
	ldr	x0, [x0, _UVD_CGC_GATE__MPEG2_MASK@GOTPAGEOFF]
Lloh51:
	adrp	x7, _UVD_CGC_GATE__RBC_MASK@GOTPAGE
Lloh52:
	ldr	x7, [x7, _UVD_CGC_GATE__RBC_MASK@GOTPAGEOFF]
Lloh53:
	ldr	w3, [x0]
Lloh54:
	ldr	w0, [x7]
	stp	w3, w0, [sp, #20]               ; 8-byte Folded Spill
Lloh55:
	adrp	x21, _UVD_CGC_GATE__LMI_MC_MASK@GOTPAGE
Lloh56:
	ldr	x21, [x21, _UVD_CGC_GATE__LMI_MC_MASK@GOTPAGEOFF]
Lloh57:
	adrp	x24, _UVD_CGC_GATE__LMI_UMC_MASK@GOTPAGE
Lloh58:
	ldr	x24, [x24, _UVD_CGC_GATE__LMI_UMC_MASK@GOTPAGEOFF]
Lloh59:
	ldr	w3, [x21]
Lloh60:
	ldr	w0, [x24]
	stp	w3, w0, [sp, #12]               ; 8-byte Folded Spill
Lloh61:
	adrp	x25, _UVD_CGC_GATE__IDCT_MASK@GOTPAGE
Lloh62:
	ldr	x25, [x25, _UVD_CGC_GATE__IDCT_MASK@GOTPAGEOFF]
Lloh63:
	adrp	x26, _UVD_CGC_GATE__MPRD_MASK@GOTPAGE
Lloh64:
	ldr	x26, [x26, _UVD_CGC_GATE__MPRD_MASK@GOTPAGEOFF]
Lloh65:
	ldr	w3, [x25]
Lloh66:
	ldr	w0, [x26]
	stp	w3, w0, [sp, #4]                ; 8-byte Folded Spill
Lloh67:
	adrp	x27, _UVD_CGC_GATE__MPC_MASK@GOTPAGE
Lloh68:
	ldr	x27, [x27, _UVD_CGC_GATE__MPC_MASK@GOTPAGEOFF]
Lloh69:
	adrp	x28, _UVD_CGC_GATE__LBSI_MASK@GOTPAGE
Lloh70:
	ldr	x28, [x28, _UVD_CGC_GATE__LBSI_MASK@GOTPAGEOFF]
Lloh71:
	ldr	w27, [x27]
Lloh72:
	ldr	w28, [x28]
Lloh73:
	adrp	x30, _UVD_CGC_GATE__LRBBM_MASK@GOTPAGE
Lloh74:
	ldr	x30, [x30, _UVD_CGC_GATE__LRBBM_MASK@GOTPAGEOFF]
Lloh75:
	adrp	x22, _UVD_CGC_GATE__UDEC_RE_MASK@GOTPAGE
Lloh76:
	ldr	x22, [x22, _UVD_CGC_GATE__UDEC_RE_MASK@GOTPAGEOFF]
Lloh77:
	ldr	w30, [x30]
Lloh78:
	ldr	w22, [x22]
	mov	x26, x23
Lloh79:
	adrp	x23, _UVD_CGC_GATE__UDEC_CM_MASK@GOTPAGE
Lloh80:
	ldr	x23, [x23, _UVD_CGC_GATE__UDEC_CM_MASK@GOTPAGEOFF]
Lloh81:
	adrp	x19, _UVD_CGC_GATE__UDEC_IT_MASK@GOTPAGE
Lloh82:
	ldr	x19, [x19, _UVD_CGC_GATE__UDEC_IT_MASK@GOTPAGEOFF]
Lloh83:
	ldr	w23, [x23]
Lloh84:
	ldr	w19, [x19]
	str	w8, [sp, #44]                   ; 4-byte Folded Spill
Lloh85:
	adrp	x8, _UVD_CGC_GATE__UDEC_DB_MASK@GOTPAGE
Lloh86:
	ldr	x8, [x8, _UVD_CGC_GATE__UDEC_DB_MASK@GOTPAGEOFF]
Lloh87:
	adrp	x3, _UVD_CGC_GATE__UDEC_MP_MASK@GOTPAGE
Lloh88:
	ldr	x3, [x3, _UVD_CGC_GATE__UDEC_MP_MASK@GOTPAGEOFF]
Lloh89:
	ldr	w21, [x8]
Lloh90:
	ldr	w24, [x3]
	str	w9, [sp, #40]                   ; 4-byte Folded Spill
Lloh91:
	adrp	x9, _UVD_CGC_GATE__WCB_MASK@GOTPAGE
Lloh92:
	ldr	x9, [x9, _UVD_CGC_GATE__WCB_MASK@GOTPAGEOFF]
	mov	x25, x10
Lloh93:
	adrp	x10, _UVD_CGC_GATE__JPEG_MASK@GOTPAGE
Lloh94:
	ldr	x10, [x10, _UVD_CGC_GATE__JPEG_MASK@GOTPAGEOFF]
	mov	x3, x1
Lloh95:
	ldr	w1, [x9]
Lloh96:
	ldr	w10, [x10]
	mov	x7, x11
Lloh97:
	adrp	x11, _UVD_CGC_GATE__SCPU_MASK@GOTPAGE
Lloh98:
	ldr	x11, [x11, _UVD_CGC_GATE__SCPU_MASK@GOTPAGEOFF]
	mov	x5, x12
Lloh99:
	adrp	x12, _UVD_CGC_GATE__JPEG2_MASK@GOTPAGE
Lloh100:
	ldr	x12, [x12, _UVD_CGC_GATE__JPEG2_MASK@GOTPAGEOFF]
Lloh101:
	ldr	w11, [x11]
Lloh102:
	ldr	w12, [x12]
	mov	x4, x2
	mov	x0, x17
	mov	x17, x16
	mov	x16, x13
	ldr	w13, [x20]
	mov	x9, x14
Lloh103:
	adrp	x14, _AMD_PG_SUPPORT_UVD@GOTPAGE
Lloh104:
	ldr	x14, [x14, _AMD_PG_SUPPORT_UVD@GOTPAGEOFF]
Lloh105:
	ldr	w14, [x14]
	mov	x8, x15
Lloh106:
	adrp	x15, _UVD_CGC_GATE__VCPU_MASK@GOTPAGE
Lloh107:
	ldr	x15, [x15, _UVD_CGC_GATE__VCPU_MASK@GOTPAGEOFF]
Lloh108:
	ldr	w15, [x15]
	tst	w14, w13
	csel	w13, wzr, w15, eq
	mov	x15, x8
	ldr	w8, [sp, #36]                   ; 4-byte Folded Reload
	ldr	w14, [sp, #28]                  ; 4-byte Folded Reload
	orr	w14, w14, w8
	ldr	w8, [sp, #32]                   ; 4-byte Folded Reload
	orr	w14, w14, w8
	ldr	w8, [sp, #20]                   ; 4-byte Folded Reload
	orr	w14, w14, w8
	ldr	w8, [sp, #24]                   ; 4-byte Folded Reload
	orr	w14, w14, w8
	ldr	w8, [sp, #12]                   ; 4-byte Folded Reload
	orr	w14, w14, w8
	ldr	w8, [sp, #16]                   ; 4-byte Folded Reload
	orr	w14, w14, w8
	ldr	w8, [sp, #4]                    ; 4-byte Folded Reload
	orr	w14, w14, w8
	ldr	w8, [sp, #8]                    ; 4-byte Folded Reload
	orr	w14, w14, w8
	orr	w14, w14, w27
	orr	w14, w14, w28
	orr	w14, w14, w30
	orr	w14, w14, w22
Lloh109:
	adrp	x22, _mmUVD_CGC_GATE@GOTPAGE
Lloh110:
	ldr	x22, [x22, _mmUVD_CGC_GATE@GOTPAGEOFF]
	orr	w14, w14, w23
	mov	x23, x26
	orr	w14, w14, w19
Lloh111:
	adrp	x19, _mmUVD_SUVD_CGC_GATE@GOTPAGE
Lloh112:
	ldr	x19, [x19, _mmUVD_SUVD_CGC_GATE@GOTPAGEOFF]
	orr	w8, w14, w21
	mov	x14, x9
	orr	w8, w8, w24
	orr	w8, w8, w1
	mov	x1, x3
	orr	w8, w8, w10
	mov	x10, x25
	orr	w8, w8, w11
	mov	x11, x7
	orr	w8, w8, w12
	mov	x12, x5
	orr	w8, w8, w13
	mov	x13, x16
	mov	x16, x17
	mov	x17, x0
Lloh113:
	adrp	x9, _UVD_CGC_GATE__REGS_MASK@GOTPAGE
Lloh114:
	ldr	x9, [x9, _UVD_CGC_GATE__REGS_MASK@GOTPAGEOFF]
Lloh115:
	ldr	w9, [x9]
	bic	w20, w8, w9
	ldp	w9, w8, [sp, #40]               ; 8-byte Folded Reload
	b	LBB0_3
LBB0_2:
	mov	w20, #0
LBB0_3:
	orr	w8, w8, w23
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w8, w8, w13
	orr	w8, w8, w14
	orr	w8, w8, w15
	orr	w8, w8, w16
	orr	w8, w8, w17
	orr	w8, w8, w6
	orr	w8, w8, w1
	orr	w1, w8, w2
	ldr	w0, [x19]
	bl	_WREG32
	ldr	w0, [x22]
	mov	x1, x20
	ldp	x29, x30, [sp, #128]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #112]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #96]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #80]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #64]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #144
	b	_WREG32
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGot	Lloh111, Lloh112
	.loh AdrpLdrGot	Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh101
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh95
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh89
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh83
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh77
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh71
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh65
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh59
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh53
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh47
	.cfi_endproc
                                        ; -- End function
	.comm	_mmUVD_SUVD_CGC_GATE,4,2        ; @mmUVD_SUVD_CGC_GATE
	.comm	_mmUVD_CGC_GATE,4,2             ; @mmUVD_CGC_GATE
	.comm	_UVD_SUVD_CGC_GATE__SRE_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SRE_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SIT_MASK
	.comm	_UVD_SUVD_CGC_GATE__SMP_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SMP_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SCM_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SDB_MASK
	.comm	_UVD_SUVD_CGC_GATE__SRE_H264_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SRE_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SRE_HEVC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_H264_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SIT_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SIT_HEVC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_H264_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SCM_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SCM_HEVC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_H264_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SDB_H264_MASK
	.comm	_UVD_SUVD_CGC_GATE__SDB_HEVC_MASK,4,2 ; @UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
	.comm	_UVD_CGC_GATE__SYS_MASK,4,2     ; @UVD_CGC_GATE__SYS_MASK
	.comm	_UVD_CGC_GATE__UDEC_MASK,4,2    ; @UVD_CGC_GATE__UDEC_MASK
	.comm	_UVD_CGC_GATE__MPEG2_MASK,4,2   ; @UVD_CGC_GATE__MPEG2_MASK
	.comm	_UVD_CGC_GATE__RBC_MASK,4,2     ; @UVD_CGC_GATE__RBC_MASK
	.comm	_UVD_CGC_GATE__LMI_MC_MASK,4,2  ; @UVD_CGC_GATE__LMI_MC_MASK
	.comm	_UVD_CGC_GATE__LMI_UMC_MASK,4,2 ; @UVD_CGC_GATE__LMI_UMC_MASK
	.comm	_UVD_CGC_GATE__IDCT_MASK,4,2    ; @UVD_CGC_GATE__IDCT_MASK
	.comm	_UVD_CGC_GATE__MPRD_MASK,4,2    ; @UVD_CGC_GATE__MPRD_MASK
	.comm	_UVD_CGC_GATE__MPC_MASK,4,2     ; @UVD_CGC_GATE__MPC_MASK
	.comm	_UVD_CGC_GATE__LBSI_MASK,4,2    ; @UVD_CGC_GATE__LBSI_MASK
	.comm	_UVD_CGC_GATE__LRBBM_MASK,4,2   ; @UVD_CGC_GATE__LRBBM_MASK
	.comm	_UVD_CGC_GATE__UDEC_RE_MASK,4,2 ; @UVD_CGC_GATE__UDEC_RE_MASK
	.comm	_UVD_CGC_GATE__UDEC_CM_MASK,4,2 ; @UVD_CGC_GATE__UDEC_CM_MASK
	.comm	_UVD_CGC_GATE__UDEC_IT_MASK,4,2 ; @UVD_CGC_GATE__UDEC_IT_MASK
	.comm	_UVD_CGC_GATE__UDEC_DB_MASK,4,2 ; @UVD_CGC_GATE__UDEC_DB_MASK
	.comm	_UVD_CGC_GATE__UDEC_MP_MASK,4,2 ; @UVD_CGC_GATE__UDEC_MP_MASK
	.comm	_UVD_CGC_GATE__WCB_MASK,4,2     ; @UVD_CGC_GATE__WCB_MASK
	.comm	_UVD_CGC_GATE__JPEG_MASK,4,2    ; @UVD_CGC_GATE__JPEG_MASK
	.comm	_UVD_CGC_GATE__SCPU_MASK,4,2    ; @UVD_CGC_GATE__SCPU_MASK
	.comm	_UVD_CGC_GATE__JPEG2_MASK,4,2   ; @UVD_CGC_GATE__JPEG2_MASK
	.comm	_AMD_PG_SUPPORT_UVD,4,2         ; @AMD_PG_SUPPORT_UVD
	.comm	_UVD_CGC_GATE__VCPU_MASK,4,2    ; @UVD_CGC_GATE__VCPU_MASK
	.comm	_UVD_CGC_GATE__REGS_MASK,4,2    ; @UVD_CGC_GATE__REGS_MASK
	.no_dead_strip	_uvd_v6_0_enable_clock_gating
.subsections_via_symbols
