	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_agp_disable             ## -- Begin function radeon_agp_disable
	.p2align	4, 0x90
_radeon_agp_disable:                    ## @radeon_agp_disable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	movq	_RADEON_IS_AGP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, 24(%rdi)
	movq	(%rdi), %rax
	movq	_CHIP_R600@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_1
## %bb.2:
	movq	_CHIP_RV515@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_6
## %bb.3:
	movq	_CHIP_RV380@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_6
## %bb.4:
	movq	_CHIP_RV410@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_6
## %bb.5:
	movq	_CHIP_R423@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_6
## %bb.7:
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_INFO
	movq	_RADEON_IS_PCI@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, 24(%rbx)
	movq	16(%rbx), %rax
	movq	_r100_pci_gart_tlb_flush@GOTPCREL(%rip), %rcx
	movq	%rcx, 16(%rax)
	movq	_r100_pci_gart_get_page_entry@GOTPCREL(%rip), %rcx
	movq	%rcx, 8(%rax)
	movq	_r100_pci_gart_set_page@GOTPCREL(%rip), %rcx
	jmp	LBB0_8
LBB0_1:
	leaq	L_.str(%rip), %rdi
	callq	_DRM_INFO
	movq	_RADEON_IS_PCIE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, 24(%rbx)
	jmp	LBB0_9
LBB0_6:
	leaq	L_.str(%rip), %rdi
	callq	_DRM_INFO
	movq	_RADEON_IS_PCIE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, 24(%rbx)
	movq	16(%rbx), %rax
	movq	_rv370_pcie_gart_tlb_flush@GOTPCREL(%rip), %rcx
	movq	%rcx, 16(%rax)
	movq	_rv370_pcie_gart_get_page_entry@GOTPCREL(%rip), %rcx
	movq	%rcx, 8(%rax)
	movq	_rv370_pcie_gart_set_page@GOTPCREL(%rip), %rcx
LBB0_8:
	movq	%rcx, (%rax)
LBB0_9:
	movq	_radeon_gart_size@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	shll	$20, %eax
	movl	%eax, 8(%rbx)
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_IS_AGP,4,2              ## @RADEON_IS_AGP
	.comm	_CHIP_R600,8,3                  ## @CHIP_R600
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Forcing AGP to PCIE mode\n"

	.comm	_RADEON_IS_PCIE,4,2             ## @RADEON_IS_PCIE
	.comm	_CHIP_RV515,8,3                 ## @CHIP_RV515
	.comm	_CHIP_RV380,8,3                 ## @CHIP_RV380
	.comm	_CHIP_RV410,8,3                 ## @CHIP_RV410
	.comm	_CHIP_R423,8,3                  ## @CHIP_R423
	.comm	_rv370_pcie_gart_tlb_flush,4,2  ## @rv370_pcie_gart_tlb_flush
	.comm	_rv370_pcie_gart_get_page_entry,4,2 ## @rv370_pcie_gart_get_page_entry
	.comm	_rv370_pcie_gart_set_page,4,2   ## @rv370_pcie_gart_set_page
L_.str.1:                               ## @.str.1
	.asciz	"Forcing AGP to PCI mode\n"

	.comm	_RADEON_IS_PCI,4,2              ## @RADEON_IS_PCI
	.comm	_r100_pci_gart_tlb_flush,4,2    ## @r100_pci_gart_tlb_flush
	.comm	_r100_pci_gart_get_page_entry,4,2 ## @r100_pci_gart_get_page_entry
	.comm	_r100_pci_gart_set_page,4,2     ## @r100_pci_gart_set_page
	.comm	_radeon_gart_size,4,2           ## @radeon_gart_size
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_agp_disable             ; -- Begin function radeon_agp_disable
	.p2align	2
_radeon_agp_disable:                    ; @radeon_agp_disable
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
Lloh0:
	adrp	x8, _RADEON_IS_AGP@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_IS_AGP@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	ldr	w9, [x0, #24]
	bic	w8, w9, w8
	str	w8, [x0, #24]
	ldr	x8, [x0]
Lloh3:
	adrp	x9, _CHIP_R600@GOTPAGE
Lloh4:
	ldr	x9, [x9, _CHIP_R600@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_3
; %bb.1:
Lloh6:
	adrp	x9, _CHIP_RV515@GOTPAGE
Lloh7:
	ldr	x9, [x9, _CHIP_RV515@GOTPAGEOFF]
Lloh8:
	adrp	x10, _CHIP_RV380@GOTPAGE
Lloh9:
	ldr	x10, [x10, _CHIP_RV380@GOTPAGEOFF]
Lloh10:
	ldr	x9, [x9]
Lloh11:
	ldr	x10, [x10]
Lloh12:
	adrp	x11, _CHIP_RV410@GOTPAGE
Lloh13:
	ldr	x11, [x11, _CHIP_RV410@GOTPAGEOFF]
Lloh14:
	adrp	x12, _CHIP_R423@GOTPAGE
Lloh15:
	ldr	x12, [x12, _CHIP_R423@GOTPAGEOFF]
Lloh16:
	ldr	x11, [x11]
Lloh17:
	ldr	x12, [x12]
	cmp	x8, x9
	ccmp	x8, x10, #4, lt
	ccmp	x8, x11, #4, ne
	ccmp	x8, x12, #4, ne
	b.ne	LBB0_4
; %bb.2:
Lloh18:
	adrp	x0, l_.str@PAGE
Lloh19:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_INFO
Lloh20:
	adrp	x8, _RADEON_IS_PCIE@GOTPAGE
Lloh21:
	ldr	x8, [x8, _RADEON_IS_PCIE@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
	ldr	w9, [x19, #24]
	orr	w8, w9, w8
	str	w8, [x19, #24]
	ldr	x8, [x19, #16]
Lloh23:
	adrp	x9, _rv370_pcie_gart_tlb_flush@GOTPAGE
Lloh24:
	ldr	x9, [x9, _rv370_pcie_gart_tlb_flush@GOTPAGEOFF]
	str	x9, [x8, #16]
Lloh25:
	adrp	x9, _rv370_pcie_gart_get_page_entry@GOTPAGE
Lloh26:
	ldr	x9, [x9, _rv370_pcie_gart_get_page_entry@GOTPAGEOFF]
Lloh27:
	adrp	x10, _rv370_pcie_gart_set_page@GOTPAGE
Lloh28:
	ldr	x10, [x10, _rv370_pcie_gart_set_page@GOTPAGEOFF]
	b	LBB0_5
LBB0_3:
Lloh29:
	adrp	x0, l_.str@PAGE
Lloh30:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_INFO
Lloh31:
	adrp	x8, _RADEON_IS_PCIE@GOTPAGE
Lloh32:
	ldr	x8, [x8, _RADEON_IS_PCIE@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
	ldr	w9, [x19, #24]
	orr	w8, w9, w8
	str	w8, [x19, #24]
	b	LBB0_6
LBB0_4:
Lloh34:
	adrp	x0, l_.str.1@PAGE
Lloh35:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_INFO
Lloh36:
	adrp	x8, _RADEON_IS_PCI@GOTPAGE
Lloh37:
	ldr	x8, [x8, _RADEON_IS_PCI@GOTPAGEOFF]
Lloh38:
	ldr	w8, [x8]
	ldr	w9, [x19, #24]
	orr	w8, w9, w8
	str	w8, [x19, #24]
	ldr	x8, [x19, #16]
Lloh39:
	adrp	x9, _r100_pci_gart_tlb_flush@GOTPAGE
Lloh40:
	ldr	x9, [x9, _r100_pci_gart_tlb_flush@GOTPAGEOFF]
	str	x9, [x8, #16]
Lloh41:
	adrp	x9, _r100_pci_gart_get_page_entry@GOTPAGE
Lloh42:
	ldr	x9, [x9, _r100_pci_gart_get_page_entry@GOTPAGEOFF]
Lloh43:
	adrp	x10, _r100_pci_gart_set_page@GOTPAGE
Lloh44:
	ldr	x10, [x10, _r100_pci_gart_set_page@GOTPAGEOFF]
LBB0_5:
	stp	x10, x9, [x8]
LBB0_6:
Lloh45:
	adrp	x8, _radeon_gart_size@GOTPAGE
Lloh46:
	ldr	x8, [x8, _radeon_gart_size@GOTPAGEOFF]
Lloh47:
	ldr	w8, [x8]
	lsl	w8, w8, #20
	str	w8, [x19, #8]
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh16
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh10
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpAdd	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpAdd	Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpAdd	Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_IS_AGP,4,2              ; @RADEON_IS_AGP
	.comm	_CHIP_R600,8,3                  ; @CHIP_R600
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Forcing AGP to PCIE mode\n"

	.comm	_RADEON_IS_PCIE,4,2             ; @RADEON_IS_PCIE
	.comm	_CHIP_RV515,8,3                 ; @CHIP_RV515
	.comm	_CHIP_RV380,8,3                 ; @CHIP_RV380
	.comm	_CHIP_RV410,8,3                 ; @CHIP_RV410
	.comm	_CHIP_R423,8,3                  ; @CHIP_R423
	.comm	_rv370_pcie_gart_tlb_flush,4,2  ; @rv370_pcie_gart_tlb_flush
	.comm	_rv370_pcie_gart_get_page_entry,4,2 ; @rv370_pcie_gart_get_page_entry
	.comm	_rv370_pcie_gart_set_page,4,2   ; @rv370_pcie_gart_set_page
l_.str.1:                               ; @.str.1
	.asciz	"Forcing AGP to PCI mode\n"

	.comm	_RADEON_IS_PCI,4,2              ; @RADEON_IS_PCI
	.comm	_r100_pci_gart_tlb_flush,4,2    ; @r100_pci_gart_tlb_flush
	.comm	_r100_pci_gart_get_page_entry,4,2 ; @r100_pci_gart_get_page_entry
	.comm	_r100_pci_gart_set_page,4,2     ; @r100_pci_gart_set_page
	.comm	_radeon_gart_size,4,2           ; @radeon_gart_size
.subsections_via_symbols
