	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vlv_pipe_crc_ctl_reg
_vlv_pipe_crc_ctl_reg:                  ## @vlv_pipe_crc_ctl_reg
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rcx, %r14
	movl	%esi, %r15d
	movq	%rdi, %r12
	movl	(%rdx), %eax
	movq	_INTEL_PIPE_CRC_SOURCE_AUTO@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_3
## %bb.1:
	movq	%rdx, %rbx
	movq	%r12, %rdi
	movl	%r15d, %esi
	callq	_i9xx_pipe_crc_auto_source
	testl	%eax, %eax
	jne	LBB0_13
## %bb.2:
	movl	(%rbx), %eax
LBB0_3:
	addl	$-131, %eax
	cmpl	$4, %eax
	ja	LBB0_12
## %bb.4:
	movq	_PIPE_CRC_SOURCE_DP_B_VLV@GOTPCREL(%rip), %rcx
	leaq	LJTI0_0(%rip), %rdx
	movslq	(%rdx,%rax,4), %rax
	addq	%rdx, %rax
	jmpq	*%rax
LBB0_5:
	movq	_PIPE_CRC_ENABLE@GOTPCREL(%rip), %rax
	movq	_PIPE_CRC_SOURCE_PIPE_VLV@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movl	%ecx, (%r14)
	xorl	%eax, %eax
	jmp	LBB0_13
LBB0_8:
	movl	$0, (%r14)
	xorl	%eax, %eax
	jmp	LBB0_13
LBB0_6:
	movq	%r12, %rdi
	callq	_IS_CHERRYVIEW
	testl	%eax, %eax
	je	LBB0_12
## %bb.7:
	movq	_PIPE_CRC_SOURCE_DP_D_VLV@GOTPCREL(%rip), %rcx
	jmp	LBB0_10
LBB0_9:
	movq	_PIPE_CRC_SOURCE_DP_C_VLV@GOTPCREL(%rip), %rcx
LBB0_10:
	movq	_PIPE_CRC_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movl	%ecx, (%r14)
	movq	_PORT_DFT2_G4X@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_I915_READ
	addl	$-128, %r15d
	cmpl	$2, %r15d
	ja	LBB0_12
## %bb.11:
	movq	_DC_BALANCE_RESET_VLV@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movslq	%r15d, %rcx
	leaq	l_switch.table.vlv_pipe_crc_ctl_reg(%rip), %rdx
	movq	(%rdx,%rcx,8), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_I915_WRITE
	xorl	%eax, %eax
	jmp	LBB0_13
LBB0_12:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_13:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_8, LBB0_8-LJTI0_0
.set L0_0_set_6, LBB0_6-LJTI0_0
.set L0_0_set_9, LBB0_9-LJTI0_0
.set L0_0_set_10, LBB0_10-LJTI0_0
LJTI0_0:
	.long	L0_0_set_5
	.long	L0_0_set_8
	.long	L0_0_set_6
	.long	L0_0_set_9
	.long	L0_0_set_10
	.end_data_region
                                        ## -- End function
	.comm	_INTEL_PIPE_CRC_SOURCE_AUTO,4,2 ## @INTEL_PIPE_CRC_SOURCE_AUTO
	.comm	_PIPE_CRC_ENABLE,4,2            ## @PIPE_CRC_ENABLE
	.comm	_PIPE_CRC_SOURCE_PIPE_VLV,4,2   ## @PIPE_CRC_SOURCE_PIPE_VLV
	.comm	_PIPE_CRC_SOURCE_DP_B_VLV,4,2   ## @PIPE_CRC_SOURCE_DP_B_VLV
	.comm	_PIPE_CRC_SOURCE_DP_C_VLV,4,2   ## @PIPE_CRC_SOURCE_DP_C_VLV
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_PIPE_CRC_SOURCE_DP_D_VLV,4,2   ## @PIPE_CRC_SOURCE_DP_D_VLV
	.comm	_PORT_DFT2_G4X,4,2              ## @PORT_DFT2_G4X
	.comm	_DC_BALANCE_RESET_VLV,4,2       ## @DC_BALANCE_RESET_VLV
	.comm	_PIPE_A_SCRAMBLE_RESET,4,2      ## @PIPE_A_SCRAMBLE_RESET
	.comm	_PIPE_B_SCRAMBLE_RESET,4,2      ## @PIPE_B_SCRAMBLE_RESET
	.comm	_PIPE_C_SCRAMBLE_RESET,4,2      ## @PIPE_C_SCRAMBLE_RESET
	.no_dead_strip	_vlv_pipe_crc_ctl_reg
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.vlv_pipe_crc_ctl_reg
l_switch.table.vlv_pipe_crc_ctl_reg:
	.quad	_PIPE_C_SCRAMBLE_RESET
	.quad	_PIPE_B_SCRAMBLE_RESET
	.quad	_PIPE_A_SCRAMBLE_RESET

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vlv_pipe_crc_ctl_reg
_vlv_pipe_crc_ctl_reg:                  ; @vlv_pipe_crc_ctl_reg
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x3
	mov	x20, x1
	mov	x21, x0
	ldr	w8, [x2]
Lloh0:
	adrp	x9, _INTEL_PIPE_CRC_SOURCE_AUTO@GOTPAGE
Lloh1:
	ldr	x9, [x9, _INTEL_PIPE_CRC_SOURCE_AUTO@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_3
; %bb.1:
	mov	x22, x2
	mov	x0, x21
	mov	x1, x20
	bl	_i9xx_pipe_crc_auto_source
	cbnz	w0, LBB0_13
; %bb.2:
	ldr	w8, [x22]
LBB0_3:
	sub	w9, w8, #131
	cmp	w9, #4
	b.hi	LBB0_12
; %bb.4:
Lloh3:
	adrp	x8, _PIPE_CRC_SOURCE_DP_B_VLV@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PIPE_CRC_SOURCE_DP_B_VLV@GOTPAGEOFF]
Lloh5:
	adrp	x10, lJTI0_0@PAGE
Lloh6:
	add	x10, x10, lJTI0_0@PAGEOFF
	adr	x11, LBB0_5
	ldrb	w12, [x10, x9]
	add	x11, x11, x12, lsl #2
	br	x11
LBB0_5:
	mov	w0, #0
Lloh7:
	adrp	x8, _PIPE_CRC_ENABLE@GOTPAGE
Lloh8:
	ldr	x8, [x8, _PIPE_CRC_ENABLE@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
Lloh10:
	adrp	x9, _PIPE_CRC_SOURCE_PIPE_VLV@GOTPAGE
Lloh11:
	ldr	x9, [x9, _PIPE_CRC_SOURCE_PIPE_VLV@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
	orr	w8, w9, w8
	str	w8, [x19]
	b	LBB0_13
LBB0_6:
	mov	w0, #0
	str	wzr, [x19]
	b	LBB0_13
LBB0_7:
	mov	x0, x21
	bl	_IS_CHERRYVIEW
	cbz	w0, LBB0_12
; %bb.8:
Lloh13:
	adrp	x8, _PIPE_CRC_SOURCE_DP_D_VLV@GOTPAGE
Lloh14:
	ldr	x8, [x8, _PIPE_CRC_SOURCE_DP_D_VLV@GOTPAGEOFF]
	b	LBB0_10
LBB0_9:
Lloh15:
	adrp	x8, _PIPE_CRC_SOURCE_DP_C_VLV@GOTPAGE
Lloh16:
	ldr	x8, [x8, _PIPE_CRC_SOURCE_DP_C_VLV@GOTPAGEOFF]
LBB0_10:
Lloh17:
	adrp	x9, _PIPE_CRC_ENABLE@GOTPAGE
Lloh18:
	ldr	x9, [x9, _PIPE_CRC_ENABLE@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	ldr	w8, [x8]
	orr	w8, w8, w9
	str	w8, [x19]
Lloh20:
	adrp	x19, _PORT_DFT2_G4X@GOTPAGE
Lloh21:
	ldr	x19, [x19, _PORT_DFT2_G4X@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_I915_READ
	sub	w8, w20, #128
	cmp	w8, #2
	b.hi	LBB0_12
; %bb.11:
Lloh22:
	adrp	x9, _DC_BALANCE_RESET_VLV@GOTPAGE
Lloh23:
	ldr	x9, [x9, _DC_BALANCE_RESET_VLV@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
Lloh25:
	adrp	x10, l_switch.table.vlv_pipe_crc_ctl_reg@PAGE
Lloh26:
	add	x10, x10, l_switch.table.vlv_pipe_crc_ctl_reg@PAGEOFF
	orr	w9, w9, w0
	ldr	x8, [x10, w8, sxtw #3]
	ldr	w8, [x8]
	orr	w1, w9, w8
	ldr	w0, [x19]
	bl	_I915_WRITE
	mov	w0, #0
	b	LBB0_13
LBB0_12:
Lloh27:
	adrp	x8, _EINVAL@GOTPAGE
Lloh28:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_13:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpAdd	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_5-LBB0_5)>>2
	.byte	(LBB0_6-LBB0_5)>>2
	.byte	(LBB0_7-LBB0_5)>>2
	.byte	(LBB0_9-LBB0_5)>>2
	.byte	(LBB0_10-LBB0_5)>>2
                                        ; -- End function
	.comm	_INTEL_PIPE_CRC_SOURCE_AUTO,4,2 ; @INTEL_PIPE_CRC_SOURCE_AUTO
	.comm	_PIPE_CRC_ENABLE,4,2            ; @PIPE_CRC_ENABLE
	.comm	_PIPE_CRC_SOURCE_PIPE_VLV,4,2   ; @PIPE_CRC_SOURCE_PIPE_VLV
	.comm	_PIPE_CRC_SOURCE_DP_B_VLV,4,2   ; @PIPE_CRC_SOURCE_DP_B_VLV
	.comm	_PIPE_CRC_SOURCE_DP_C_VLV,4,2   ; @PIPE_CRC_SOURCE_DP_C_VLV
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_PIPE_CRC_SOURCE_DP_D_VLV,4,2   ; @PIPE_CRC_SOURCE_DP_D_VLV
	.comm	_PORT_DFT2_G4X,4,2              ; @PORT_DFT2_G4X
	.comm	_DC_BALANCE_RESET_VLV,4,2       ; @DC_BALANCE_RESET_VLV
	.comm	_PIPE_A_SCRAMBLE_RESET,4,2      ; @PIPE_A_SCRAMBLE_RESET
	.comm	_PIPE_B_SCRAMBLE_RESET,4,2      ; @PIPE_B_SCRAMBLE_RESET
	.comm	_PIPE_C_SCRAMBLE_RESET,4,2      ; @PIPE_C_SCRAMBLE_RESET
	.no_dead_strip	_vlv_pipe_crc_ctl_reg
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.vlv_pipe_crc_ctl_reg
l_switch.table.vlv_pipe_crc_ctl_reg:
	.quad	_PIPE_C_SCRAMBLE_RESET
	.quad	_PIPE_B_SCRAMBLE_RESET
	.quad	_PIPE_A_SCRAMBLE_RESET

.subsections_via_symbols
