	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function uvd_v6_0_set_sw_clock_gating
_uvd_v6_0_set_sw_clock_gating:          ## @uvd_v6_0_set_sw_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_mmUVD_CGC_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %ebx
	movq	_mmUVD_SUVD_CGC_CTRL@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_RREG32
	movl	%eax, %r14d
	movq	_UVD_CGC_CTRL__CLK_OFF_DELAY_MASK@GOTPCREL(%rip), %rax
	movq	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r12d
	orl	(%rax), %r12d
	notl	%r12d
	andl	%ebx, %r12d
	movq	_UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPCREL(%rip), %rax
	movq	_UVD_CGC_CTRL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_CLK_GATE_DLY_TIMER@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %r12d
	callq	_REG_FIELD_SHIFT
	movl	%eax, %r15d
	movl	(%rbx), %edi
	movq	_CLK_OFF_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_REG_FIELD_SHIFT
	movq	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPCREL(%rip), %rcx
	movq	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	movq	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_CGC_CTRL__SYS_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_CGC_CTRL__REGS_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_CGC_CTRL__RBC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_CGC_CTRL__MPC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_CGC_CTRL__WCB_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_CGC_CTRL__JPEG_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_CGC_CTRL__SCPU_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_CGC_CTRL__JPEG2_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_UVD_SUVD_CGC_CTRL__SRE_MODE_MASK@GOTPCREL(%rip), %rcx
	movq	_UVD_SUVD_CGC_CTRL__SIT_MODE_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	btsl	%r15d, %r12d
	movq	_UVD_SUVD_CGC_CTRL__SMP_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movl	$4, %edx
	movl	%eax, %ecx
	shll	%cl, %edx
	orl	%edx, %r12d
	movq	_UVD_SUVD_CGC_CTRL__SCM_MODE_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	notl	%esi
	movq	_UVD_SUVD_CGC_CTRL__SDB_MODE_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	andl	%r12d, %esi
	notl	%ebx
	andl	%r14d, %ebx
	movq	_mmUVD_CGC_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32
	movl	(%r13), %edi
	movl	%ebx, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_mmUVD_CGC_CTRL,4,2             ## @mmUVD_CGC_CTRL
	.comm	_mmUVD_SUVD_CGC_CTRL,4,2        ## @mmUVD_SUVD_CGC_CTRL
	.comm	_UVD_CGC_CTRL__CLK_OFF_DELAY_MASK,4,2 ## @UVD_CGC_CTRL__CLK_OFF_DELAY_MASK
	.comm	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK,4,2 ## @UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK,4,2 ## @UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK
	.comm	_UVD_CGC_CTRL,4,2               ## @UVD_CGC_CTRL
	.comm	_CLK_GATE_DLY_TIMER,4,2         ## @CLK_GATE_DLY_TIMER
	.comm	_CLK_OFF_DELAY,4,2              ## @CLK_OFF_DELAY
	.comm	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_RE_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_CM_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_IT_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_DB_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_MP_MODE_MASK
	.comm	_UVD_CGC_CTRL__SYS_MODE_MASK,4,2 ## @UVD_CGC_CTRL__SYS_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPEG2_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPEG2_MODE_MASK
	.comm	_UVD_CGC_CTRL__REGS_MODE_MASK,4,2 ## @UVD_CGC_CTRL__REGS_MODE_MASK
	.comm	_UVD_CGC_CTRL__RBC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__RBC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_MC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LMI_MC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LMI_UMC_MODE_MASK
	.comm	_UVD_CGC_CTRL__IDCT_MODE_MASK,4,2 ## @UVD_CGC_CTRL__IDCT_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPRD_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPRD_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LBSI_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LBSI_MODE_MASK
	.comm	_UVD_CGC_CTRL__LRBBM_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LRBBM_MODE_MASK
	.comm	_UVD_CGC_CTRL__WCB_MODE_MASK,4,2 ## @UVD_CGC_CTRL__WCB_MODE_MASK
	.comm	_UVD_CGC_CTRL__VCPU_MODE_MASK,4,2 ## @UVD_CGC_CTRL__VCPU_MODE_MASK
	.comm	_UVD_CGC_CTRL__JPEG_MODE_MASK,4,2 ## @UVD_CGC_CTRL__JPEG_MODE_MASK
	.comm	_UVD_CGC_CTRL__SCPU_MODE_MASK,4,2 ## @UVD_CGC_CTRL__SCPU_MODE_MASK
	.comm	_UVD_CGC_CTRL__JPEG2_MODE_MASK,4,2 ## @UVD_CGC_CTRL__JPEG2_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SRE_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SIT_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SMP_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SCM_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SDB_MODE_MASK,4,2 ## @UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
	.no_dead_strip	_uvd_v6_0_set_sw_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function uvd_v6_0_set_sw_clock_gating
_uvd_v6_0_set_sw_clock_gating:          ; @uvd_v6_0_set_sw_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
Lloh0:
	adrp	x21, _mmUVD_CGC_CTRL@GOTPAGE
Lloh1:
	ldr	x21, [x21, _mmUVD_CGC_CTRL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
	mov	x20, x0
Lloh2:
	adrp	x22, _mmUVD_SUVD_CGC_CTRL@GOTPAGE
Lloh3:
	ldr	x22, [x22, _mmUVD_SUVD_CGC_CTRL@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_RREG32
	mov	x19, x0
Lloh4:
	adrp	x8, _UVD_CGC_CTRL__CLK_OFF_DELAY_MASK@GOTPAGE
Lloh5:
	ldr	x8, [x8, _UVD_CGC_CTRL__CLK_OFF_DELAY_MASK@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
Lloh7:
	adrp	x9, _UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK@GOTPAGE
Lloh8:
	ldr	x9, [x9, _UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK@GOTPAGEOFF]
Lloh9:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w20, w20, w8
Lloh10:
	adrp	x8, _UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPAGE
Lloh11:
	ldr	x8, [x8, _UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPAGEOFF]
Lloh12:
	ldr	w23, [x8]
Lloh13:
	adrp	x24, _UVD_CGC_CTRL@GOTPAGE
Lloh14:
	ldr	x24, [x24, _UVD_CGC_CTRL@GOTPAGEOFF]
	ldr	w0, [x24]
Lloh15:
	adrp	x8, _CLK_GATE_DLY_TIMER@GOTPAGE
Lloh16:
	ldr	x8, [x8, _CLK_GATE_DLY_TIMER@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	bl	_REG_FIELD_SHIFT
	mov	w8, #1
	lsl	w25, w8, w0
	ldr	w0, [x24]
Lloh18:
	adrp	x8, _CLK_OFF_DELAY@GOTPAGE
Lloh19:
	ldr	x8, [x8, _CLK_OFF_DELAY@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	bl	_REG_FIELD_SHIFT
	mov	w8, #4
	lsl	w8, w8, w0
	orr	w9, w20, w23
	orr	w9, w9, w25
Lloh21:
	adrp	x10, _UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPAGE
Lloh22:
	ldr	x10, [x10, _UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh23:
	ldr	w9, [x10]
Lloh24:
	adrp	x10, _UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPAGE
Lloh25:
	ldr	x10, [x10, _UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPAGEOFF]
Lloh26:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh27:
	adrp	x10, _UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPAGE
Lloh28:
	ldr	x10, [x10, _UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPAGEOFF]
Lloh29:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh30:
	adrp	x10, _UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPAGE
Lloh31:
	ldr	x10, [x10, _UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPAGEOFF]
Lloh32:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh33:
	adrp	x10, _UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPAGE
Lloh34:
	ldr	x10, [x10, _UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPAGEOFF]
Lloh35:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh36:
	adrp	x10, _UVD_CGC_CTRL__SYS_MODE_MASK@GOTPAGE
Lloh37:
	ldr	x10, [x10, _UVD_CGC_CTRL__SYS_MODE_MASK@GOTPAGEOFF]
Lloh38:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh39:
	adrp	x10, _UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPAGE
Lloh40:
	ldr	x10, [x10, _UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPAGEOFF]
Lloh41:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh42:
	adrp	x10, _UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPAGE
Lloh43:
	ldr	x10, [x10, _UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPAGEOFF]
Lloh44:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh45:
	adrp	x10, _UVD_CGC_CTRL__REGS_MODE_MASK@GOTPAGE
Lloh46:
	ldr	x10, [x10, _UVD_CGC_CTRL__REGS_MODE_MASK@GOTPAGEOFF]
Lloh47:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh48:
	adrp	x10, _UVD_CGC_CTRL__RBC_MODE_MASK@GOTPAGE
Lloh49:
	ldr	x10, [x10, _UVD_CGC_CTRL__RBC_MODE_MASK@GOTPAGEOFF]
Lloh50:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh51:
	adrp	x10, _UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPAGE
Lloh52:
	ldr	x10, [x10, _UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPAGEOFF]
Lloh53:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh54:
	adrp	x10, _UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPAGE
Lloh55:
	ldr	x10, [x10, _UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPAGEOFF]
Lloh56:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh57:
	adrp	x10, _UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPAGE
Lloh58:
	ldr	x10, [x10, _UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPAGEOFF]
Lloh59:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh60:
	adrp	x10, _UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPAGE
Lloh61:
	ldr	x10, [x10, _UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPAGEOFF]
Lloh62:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh63:
	adrp	x10, _UVD_CGC_CTRL__MPC_MODE_MASK@GOTPAGE
Lloh64:
	ldr	x10, [x10, _UVD_CGC_CTRL__MPC_MODE_MASK@GOTPAGEOFF]
Lloh65:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh66:
	adrp	x10, _UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPAGE
Lloh67:
	ldr	x10, [x10, _UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPAGEOFF]
Lloh68:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh69:
	adrp	x10, _UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPAGE
Lloh70:
	ldr	x10, [x10, _UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPAGEOFF]
Lloh71:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh72:
	adrp	x10, _UVD_CGC_CTRL__WCB_MODE_MASK@GOTPAGE
Lloh73:
	ldr	x10, [x10, _UVD_CGC_CTRL__WCB_MODE_MASK@GOTPAGEOFF]
Lloh74:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh75:
	adrp	x10, _UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPAGE
Lloh76:
	ldr	x10, [x10, _UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPAGEOFF]
Lloh77:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh78:
	adrp	x10, _UVD_CGC_CTRL__JPEG_MODE_MASK@GOTPAGE
Lloh79:
	ldr	x10, [x10, _UVD_CGC_CTRL__JPEG_MODE_MASK@GOTPAGEOFF]
Lloh80:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh81:
	adrp	x10, _UVD_CGC_CTRL__SCPU_MODE_MASK@GOTPAGE
Lloh82:
	ldr	x10, [x10, _UVD_CGC_CTRL__SCPU_MODE_MASK@GOTPAGEOFF]
Lloh83:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh84:
	adrp	x10, _UVD_CGC_CTRL__JPEG2_MODE_MASK@GOTPAGE
Lloh85:
	ldr	x10, [x10, _UVD_CGC_CTRL__JPEG2_MODE_MASK@GOTPAGEOFF]
Lloh86:
	ldr	w10, [x10]
	orr	w9, w9, w10
	bic	w1, w8, w9
Lloh87:
	adrp	x8, _UVD_SUVD_CGC_CTRL__SRE_MODE_MASK@GOTPAGE
Lloh88:
	ldr	x8, [x8, _UVD_SUVD_CGC_CTRL__SRE_MODE_MASK@GOTPAGEOFF]
Lloh89:
	ldr	w8, [x8]
Lloh90:
	adrp	x9, _UVD_SUVD_CGC_CTRL__SIT_MODE_MASK@GOTPAGE
Lloh91:
	ldr	x9, [x9, _UVD_SUVD_CGC_CTRL__SIT_MODE_MASK@GOTPAGEOFF]
Lloh92:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh93:
	adrp	x9, _UVD_SUVD_CGC_CTRL__SMP_MODE_MASK@GOTPAGE
Lloh94:
	ldr	x9, [x9, _UVD_SUVD_CGC_CTRL__SMP_MODE_MASK@GOTPAGEOFF]
Lloh95:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh96:
	adrp	x9, _UVD_SUVD_CGC_CTRL__SCM_MODE_MASK@GOTPAGE
Lloh97:
	ldr	x9, [x9, _UVD_SUVD_CGC_CTRL__SCM_MODE_MASK@GOTPAGEOFF]
Lloh98:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh99:
	adrp	x9, _UVD_SUVD_CGC_CTRL__SDB_MODE_MASK@GOTPAGE
Lloh100:
	ldr	x9, [x9, _UVD_SUVD_CGC_CTRL__SDB_MODE_MASK@GOTPAGEOFF]
Lloh101:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w19, w19, w8
	ldr	w0, [x21]
	bl	_WREG32
	ldr	w0, [x22]
	mov	x1, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_WREG32
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_mmUVD_CGC_CTRL,4,2             ; @mmUVD_CGC_CTRL
	.comm	_mmUVD_SUVD_CGC_CTRL,4,2        ; @mmUVD_SUVD_CGC_CTRL
	.comm	_UVD_CGC_CTRL__CLK_OFF_DELAY_MASK,4,2 ; @UVD_CGC_CTRL__CLK_OFF_DELAY_MASK
	.comm	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK,4,2 ; @UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK,4,2 ; @UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK
	.comm	_UVD_CGC_CTRL,4,2               ; @UVD_CGC_CTRL
	.comm	_CLK_GATE_DLY_TIMER,4,2         ; @CLK_GATE_DLY_TIMER
	.comm	_CLK_OFF_DELAY,4,2              ; @CLK_OFF_DELAY
	.comm	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_RE_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_CM_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_IT_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_DB_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_MP_MODE_MASK
	.comm	_UVD_CGC_CTRL__SYS_MODE_MASK,4,2 ; @UVD_CGC_CTRL__SYS_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPEG2_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPEG2_MODE_MASK
	.comm	_UVD_CGC_CTRL__REGS_MODE_MASK,4,2 ; @UVD_CGC_CTRL__REGS_MODE_MASK
	.comm	_UVD_CGC_CTRL__RBC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__RBC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_MC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LMI_MC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LMI_UMC_MODE_MASK
	.comm	_UVD_CGC_CTRL__IDCT_MODE_MASK,4,2 ; @UVD_CGC_CTRL__IDCT_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPRD_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPRD_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LBSI_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LBSI_MODE_MASK
	.comm	_UVD_CGC_CTRL__LRBBM_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LRBBM_MODE_MASK
	.comm	_UVD_CGC_CTRL__WCB_MODE_MASK,4,2 ; @UVD_CGC_CTRL__WCB_MODE_MASK
	.comm	_UVD_CGC_CTRL__VCPU_MODE_MASK,4,2 ; @UVD_CGC_CTRL__VCPU_MODE_MASK
	.comm	_UVD_CGC_CTRL__JPEG_MODE_MASK,4,2 ; @UVD_CGC_CTRL__JPEG_MODE_MASK
	.comm	_UVD_CGC_CTRL__SCPU_MODE_MASK,4,2 ; @UVD_CGC_CTRL__SCPU_MODE_MASK
	.comm	_UVD_CGC_CTRL__JPEG2_MODE_MASK,4,2 ; @UVD_CGC_CTRL__JPEG2_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SRE_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SIT_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SMP_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SCM_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
	.comm	_UVD_SUVD_CGC_CTRL__SDB_MODE_MASK,4,2 ; @UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
	.no_dead_strip	_uvd_v6_0_set_sw_clock_gating
.subsections_via_symbols
