	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function cdv_intel_dp_max_lane_count
_cdv_intel_dp_max_lane_count:           ## @cdv_intel_dp_max_lane_count
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	(%rdi), %rax
	movq	(%rax), %rcx
	movq	_DP_DPCD_REV@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movl	$4, %eax
	cmpl	$17, (%rcx,%rdx,4)
	jl	LBB0_3
## %bb.1:
	movq	_DP_MAX_LANE_COUNT@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdx
	movl	(%rcx,%rdx,4), %ecx
	andl	$31, %ecx
	leal	-1(%rcx), %edx
	cmpl	$3, %edx
	ja	LBB0_3
## %bb.2:
	leaq	L_switch.table.cdv_intel_dp_max_lane_count(%rip), %rax
	movl	-4(%rax,%rcx,4), %eax
LBB0_3:
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DP_DPCD_REV,8,3                ## @DP_DPCD_REV
	.comm	_DP_MAX_LANE_COUNT,8,3          ## @DP_MAX_LANE_COUNT
	.no_dead_strip	_cdv_intel_dp_max_lane_count
	.section	__TEXT,__literal16,16byte_literals
	.p2align	2                               ## @switch.table.cdv_intel_dp_max_lane_count
L_switch.table.cdv_intel_dp_max_lane_count:
	.long	1                               ## 0x1
	.long	2                               ## 0x2
	.long	4                               ## 0x4
	.long	4                               ## 0x4

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cdv_intel_dp_max_lane_count
_cdv_intel_dp_max_lane_count:           ; @cdv_intel_dp_max_lane_count
	.cfi_startproc
; %bb.0:
	ldr	x8, [x0]
	ldr	x8, [x8]
Lloh0:
	adrp	x9, _DP_DPCD_REV@GOTPAGE
Lloh1:
	ldr	x9, [x9, _DP_DPCD_REV@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	ldr	w9, [x8, x9, lsl #2]
	cmp	w9, #17
	b.lt	LBB0_3
; %bb.1:
Lloh3:
	adrp	x9, _DP_MAX_LANE_COUNT@GOTPAGE
Lloh4:
	ldr	x9, [x9, _DP_MAX_LANE_COUNT@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
	ldr	w8, [x8, x9, lsl #2]
	and	x8, x8, #0x1f
	sub	x8, x8, #1
	cmp	w8, #3
	b.hi	LBB0_3
; %bb.2:
Lloh6:
	adrp	x9, l_switch.table.cdv_intel_dp_max_lane_count@PAGE
Lloh7:
	add	x9, x9, l_switch.table.cdv_intel_dp_max_lane_count@PAGEOFF
	ldr	w0, [x9, x8, lsl #2]
	ret
LBB0_3:
	mov	w0, #4
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpAdd	Lloh6, Lloh7
	.cfi_endproc
                                        ; -- End function
	.comm	_DP_DPCD_REV,8,3                ; @DP_DPCD_REV
	.comm	_DP_MAX_LANE_COUNT,8,3          ; @DP_MAX_LANE_COUNT
	.no_dead_strip	_cdv_intel_dp_max_lane_count
	.section	__TEXT,__literal16,16byte_literals
	.p2align	2                               ; @switch.table.cdv_intel_dp_max_lane_count
l_switch.table.cdv_intel_dp_max_lane_count:
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	4                               ; 0x4

.subsections_via_symbols
