	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_legacy_set_engine_clock ## -- Begin function radeon_legacy_set_engine_clock
	.p2align	4, 0x90
_radeon_legacy_set_engine_clock:        ## @radeon_legacy_set_engine_clock
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	leaq	-48(%rbp), %rdx
	leaq	-44(%rbp), %rcx
	callq	_calc_eng_mem_clock
	movl	%eax, %r13d
	movq	_RADEON_CLK_PIN_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_DONT_USE_XTALIN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32_PLL
	movq	_RADEON_SCLK_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	%rax, %rbx
	callq	_RREG32_PLL
	movq	_RADEON_SCLK_SRC_SEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32_PLL
	movl	$10, %edi
	callq	_udelay
	movq	_RADEON_SPLL_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32_PLL
	movq	_RADEON_SPLL_SLEEP@GOTPCREL(%rip), %r14
	orl	(%r14), %eax
	movl	(%r15), %edi
	movl	%eax, %esi
	callq	_WREG32_PLL
	movl	$2, %edi
	callq	_udelay
	movl	(%r15), %edi
	callq	_RREG32_PLL
	movq	_RADEON_SPLL_RESET@GOTPCREL(%rip), %rbx
	orl	(%rbx), %eax
	movl	(%r15), %edi
	movl	%eax, %esi
	callq	_WREG32_PLL
	movl	$200, %edi
	callq	_udelay
	movq	_RADEON_M_SPLL_REF_FB_DIV@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_RREG32_PLL
	movq	_RADEON_SPLL_FB_DIV_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_RADEON_SPLL_FB_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	%esi, %edx
	shll	%cl, %edx
	andl	-48(%rbp), %esi
	shll	%cl, %esi
	notl	%edx
	andl	%eax, %edx
	orl	%edx, %esi
	movl	(%r12), %edi
	callq	_WREG32_PLL
	movl	(%r15), %edi
	callq	_RREG32_PLL
	movq	_RADEON_SPLL_PVG_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	imull	-44(%rbp), %r13d
	xorl	%eax, %eax
	cmpl	$90000, %r13d                   ## imm = 0x15F90
	setge	%al
	movq	_RADEON_SPLL_PVG_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	leal	(%rax,%rax,2), %esi
	orl	$4, %esi
	shll	%cl, %esi
	orl	%edx, %esi
	movl	(%r15), %edi
	callq	_WREG32_PLL
	movl	(%r15), %edi
	callq	_RREG32_PLL
	movl	(%r14), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r15), %edi
	callq	_WREG32_PLL
	movl	$2, %edi
	callq	_udelay
	movl	(%r15), %edi
	callq	_RREG32_PLL
	movl	(%rbx), %esi
	movq	_RADEON_SCLK_CNTL@GOTPCREL(%rip), %rbx
	notl	%esi
	andl	%eax, %esi
	movl	(%r15), %edi
	callq	_WREG32_PLL
	movl	$200, %edi
	callq	_udelay
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_SCLK_SRC_SEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	-44(%rbp), %esi
	addl	$-2, %esi
	movl	$1, %edx
	cmpl	$6, %esi
	ja	LBB0_2
## %bb.1:
	movslq	%esi, %rdx
	leaq	l_switch.table.radeon_legacy_set_engine_clock(%rip), %rsi
	movl	(%rsi,%rdx,4), %edx
LBB0_2:
	notl	%ecx
	andl	%ecx, %eax
	orl	%edx, %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PLL
	movl	$20, %edi
	callq	_udelay
	movq	_RADEON_CLK_PIN_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_DONT_USE_XTALIN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PLL
	movl	$10, %edi
	callq	_udelay
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_CLK_PIN_CNTL,4,2        ## @RADEON_CLK_PIN_CNTL
	.comm	_RADEON_DONT_USE_XTALIN,4,2     ## @RADEON_DONT_USE_XTALIN
	.comm	_RADEON_SCLK_CNTL,4,2           ## @RADEON_SCLK_CNTL
	.comm	_RADEON_SCLK_SRC_SEL_MASK,4,2   ## @RADEON_SCLK_SRC_SEL_MASK
	.comm	_RADEON_SPLL_CNTL,4,2           ## @RADEON_SPLL_CNTL
	.comm	_RADEON_SPLL_SLEEP,4,2          ## @RADEON_SPLL_SLEEP
	.comm	_RADEON_SPLL_RESET,4,2          ## @RADEON_SPLL_RESET
	.comm	_RADEON_M_SPLL_REF_FB_DIV,4,2   ## @RADEON_M_SPLL_REF_FB_DIV
	.comm	_RADEON_SPLL_FB_DIV_MASK,4,2    ## @RADEON_SPLL_FB_DIV_MASK
	.comm	_RADEON_SPLL_FB_DIV_SHIFT,4,2   ## @RADEON_SPLL_FB_DIV_SHIFT
	.comm	_RADEON_SPLL_PVG_MASK,4,2       ## @RADEON_SPLL_PVG_MASK
	.comm	_RADEON_SPLL_PVG_SHIFT,4,2      ## @RADEON_SPLL_PVG_SHIFT
	.section	__TEXT,__const
	.p2align	2                               ## @switch.table.radeon_legacy_set_engine_clock
l_switch.table.radeon_legacy_set_engine_clock:
	.long	2                               ## 0x2
	.long	1                               ## 0x1
	.long	3                               ## 0x3
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	4                               ## 0x4

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_legacy_set_engine_clock ; -- Begin function radeon_legacy_set_engine_clock
	.p2align	2
_radeon_legacy_set_engine_clock:        ; @radeon_legacy_set_engine_clock
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	add	x2, sp, #12
	add	x3, sp, #8
	bl	_calc_eng_mem_clock
	mov	x19, x0
Lloh0:
	adrp	x20, _RADEON_CLK_PIN_CNTL@GOTPAGE
Lloh1:
	ldr	x20, [x20, _RADEON_CLK_PIN_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PLL
Lloh2:
	adrp	x21, _RADEON_DONT_USE_XTALIN@GOTPAGE
Lloh3:
	ldr	x21, [x21, _RADEON_DONT_USE_XTALIN@GOTPAGEOFF]
	ldr	w8, [x21]
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32_PLL
Lloh4:
	adrp	x22, _RADEON_SCLK_CNTL@GOTPAGE
Lloh5:
	ldr	x22, [x22, _RADEON_SCLK_CNTL@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_RREG32_PLL
Lloh6:
	adrp	x23, _RADEON_SCLK_SRC_SEL_MASK@GOTPAGE
Lloh7:
	ldr	x23, [x23, _RADEON_SCLK_SRC_SEL_MASK@GOTPAGEOFF]
	ldr	w8, [x23]
	bic	w1, w0, w8
	ldr	w0, [x22]
	bl	_WREG32_PLL
	mov	w0, #10
	bl	_udelay
Lloh8:
	adrp	x24, _RADEON_SPLL_CNTL@GOTPAGE
Lloh9:
	ldr	x24, [x24, _RADEON_SPLL_CNTL@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_RREG32_PLL
Lloh10:
	adrp	x25, _RADEON_SPLL_SLEEP@GOTPAGE
Lloh11:
	ldr	x25, [x25, _RADEON_SPLL_SLEEP@GOTPAGEOFF]
	ldr	w8, [x25]
	orr	w1, w8, w0
	ldr	w0, [x24]
	bl	_WREG32_PLL
	mov	w0, #2
	bl	_udelay
	ldr	w0, [x24]
	bl	_RREG32_PLL
Lloh12:
	adrp	x26, _RADEON_SPLL_RESET@GOTPAGE
Lloh13:
	ldr	x26, [x26, _RADEON_SPLL_RESET@GOTPAGEOFF]
	ldr	w8, [x26]
	orr	w1, w8, w0
	ldr	w0, [x24]
	bl	_WREG32_PLL
	mov	w0, #200
	bl	_udelay
Lloh14:
	adrp	x27, _RADEON_M_SPLL_REF_FB_DIV@GOTPAGE
Lloh15:
	ldr	x27, [x27, _RADEON_M_SPLL_REF_FB_DIV@GOTPAGEOFF]
	ldr	w0, [x27]
	bl	_RREG32_PLL
Lloh16:
	adrp	x8, _RADEON_SPLL_FB_DIV_MASK@GOTPAGE
Lloh17:
	ldr	x8, [x8, _RADEON_SPLL_FB_DIV_MASK@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
Lloh19:
	adrp	x9, _RADEON_SPLL_FB_DIV_SHIFT@GOTPAGE
Lloh20:
	ldr	x9, [x9, _RADEON_SPLL_FB_DIV_SHIFT@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	lsl	w10, w8, w9
	bic	w10, w0, w10
	ldr	w11, [sp, #12]
	and	w8, w11, w8
	lsl	w8, w8, w9
	orr	w1, w8, w10
	ldr	w0, [x27]
	bl	_WREG32_PLL
	ldr	w0, [x24]
	bl	_RREG32_PLL
Lloh22:
	adrp	x8, _RADEON_SPLL_PVG_MASK@GOTPAGE
Lloh23:
	ldr	x8, [x8, _RADEON_SPLL_PVG_MASK@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	bic	w8, w0, w8
	ldr	w9, [sp, #8]
	mul	w9, w9, w19
Lloh25:
	adrp	x10, _RADEON_SPLL_PVG_SHIFT@GOTPAGE
Lloh26:
	ldr	x10, [x10, _RADEON_SPLL_PVG_SHIFT@GOTPAGEOFF]
Lloh27:
	ldr	w10, [x10]
	mov	w11, #24463
	movk	w11, #1, lsl #16
	mov	w12, #4
	mov	w13, #7
	cmp	w9, w11
	csel	w9, w13, w12, gt
	lsl	w9, w9, w10
	orr	w1, w9, w8
	ldr	w0, [x24]
	bl	_WREG32_PLL
	ldr	w0, [x24]
	bl	_RREG32_PLL
	ldr	w8, [x25]
	bic	w1, w0, w8
	ldr	w0, [x24]
	bl	_WREG32_PLL
	mov	w0, #2
	bl	_udelay
	ldr	w0, [x24]
	bl	_RREG32_PLL
	ldr	w8, [x26]
	bic	w1, w0, w8
	ldr	w0, [x24]
	bl	_WREG32_PLL
	mov	w0, #200
	bl	_udelay
	ldr	w0, [x22]
	bl	_RREG32_PLL
	ldr	w8, [x23]
	ldr	w9, [sp, #8]
	sub	w9, w9, #2
	cmp	w9, #6
	b.hi	LBB0_2
; %bb.1:
Lloh28:
	adrp	x10, l_switch.table.radeon_legacy_set_engine_clock@PAGE
Lloh29:
	add	x10, x10, l_switch.table.radeon_legacy_set_engine_clock@PAGEOFF
	ldr	w9, [x10, w9, sxtw #2]
	b	LBB0_3
LBB0_2:
	mov	w9, #1
LBB0_3:
	bic	w8, w0, w8
	orr	w1, w8, w9
	ldr	w0, [x22]
	bl	_WREG32_PLL
	mov	w0, #20
	bl	_udelay
	ldr	w0, [x20]
	bl	_RREG32_PLL
	ldr	w8, [x21]
	orr	w1, w8, w0
	ldr	w0, [x20]
	bl	_WREG32_PLL
	mov	w0, #10
	bl	_udelay
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh28, Lloh29
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_CLK_PIN_CNTL,4,2        ; @RADEON_CLK_PIN_CNTL
	.comm	_RADEON_DONT_USE_XTALIN,4,2     ; @RADEON_DONT_USE_XTALIN
	.comm	_RADEON_SCLK_CNTL,4,2           ; @RADEON_SCLK_CNTL
	.comm	_RADEON_SCLK_SRC_SEL_MASK,4,2   ; @RADEON_SCLK_SRC_SEL_MASK
	.comm	_RADEON_SPLL_CNTL,4,2           ; @RADEON_SPLL_CNTL
	.comm	_RADEON_SPLL_SLEEP,4,2          ; @RADEON_SPLL_SLEEP
	.comm	_RADEON_SPLL_RESET,4,2          ; @RADEON_SPLL_RESET
	.comm	_RADEON_M_SPLL_REF_FB_DIV,4,2   ; @RADEON_M_SPLL_REF_FB_DIV
	.comm	_RADEON_SPLL_FB_DIV_MASK,4,2    ; @RADEON_SPLL_FB_DIV_MASK
	.comm	_RADEON_SPLL_FB_DIV_SHIFT,4,2   ; @RADEON_SPLL_FB_DIV_SHIFT
	.comm	_RADEON_SPLL_PVG_MASK,4,2       ; @RADEON_SPLL_PVG_MASK
	.comm	_RADEON_SPLL_PVG_SHIFT,4,2      ; @RADEON_SPLL_PVG_SHIFT
	.section	__TEXT,__const
	.p2align	2                               ; @switch.table.radeon_legacy_set_engine_clock
l_switch.table.radeon_legacy_set_engine_clock:
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	3                               ; 0x3
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	4                               ; 0x4

.subsections_via_symbols
