	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function sdma_v5_0_start
_sdma_v5_0_start:                       ## @sdma_v5_0_start
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_1
## %bb.8:
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_sdma_v5_0_ctx_switch_enable
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_sdma_v5_0_enable
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_sdma_v5_0_gfx_resume           ## TAILCALL
LBB0_1:
	movq	8(%rbx), %rax
	movq	_AMDGPU_FW_LOAD_DIRECT@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_6
## %bb.2:
	movq	%rbx, %rdi
	callq	_sdma_v5_0_load_microcode
	testl	%eax, %eax
	jne	LBB0_7
## %bb.3:
	movq	_amdgpu_emu_mode@GOTPCREL(%rip), %rax
	cmpl	$1, (%rax)
	jne	LBB0_6
## %bb.4:
	movq	(%rbx), %rax
	cmpl	$77, (%rax)
	jne	LBB0_6
## %bb.5:
	movl	$1000, %edi                     ## imm = 0x3E8
	callq	_msleep
LBB0_6:
	movq	%rbx, %rdi
	movl	$1, %esi
	callq	_sdma_v5_0_enable
	movq	%rbx, %rdi
	movl	$1, %esi
	callq	_sdma_v5_0_ctx_switch_enable
	movq	%rbx, %rdi
	callq	_sdma_v5_0_gfx_resume
	testl	%eax, %eax
	je	LBB0_9
LBB0_7:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
LBB0_9:
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_sdma_v5_0_rlc_resume           ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_FW_LOAD_DIRECT,8,3      ## @AMDGPU_FW_LOAD_DIRECT
	.comm	_amdgpu_emu_mode,4,2            ## @amdgpu_emu_mode
	.no_dead_strip	_sdma_v5_0_start
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function sdma_v5_0_start
_sdma_v5_0_start:                       ; @sdma_v5_0_start
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_2
; %bb.1:
	mov	x0, x19
	mov	w1, #0
	bl	_sdma_v5_0_ctx_switch_enable
	mov	x0, x19
	mov	w1, #0
	bl	_sdma_v5_0_enable
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_sdma_v5_0_gfx_resume
LBB0_2:
	ldr	x8, [x19, #8]
Lloh0:
	adrp	x9, _AMDGPU_FW_LOAD_DIRECT@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_DIRECT@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_7
; %bb.3:
	mov	x0, x19
	bl	_sdma_v5_0_load_microcode
	cbnz	w0, LBB0_8
; %bb.4:
Lloh3:
	adrp	x8, _amdgpu_emu_mode@GOTPAGE
Lloh4:
	ldr	x8, [x8, _amdgpu_emu_mode@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	cmp	w8, #1
	b.ne	LBB0_7
; %bb.5:
	ldr	x8, [x19]
	ldr	w8, [x8]
	cmp	w8, #77
	b.ne	LBB0_7
; %bb.6:
	mov	w0, #1000
	bl	_msleep
LBB0_7:
	mov	x0, x19
	mov	w1, #1
	bl	_sdma_v5_0_enable
	mov	x0, x19
	mov	w1, #1
	bl	_sdma_v5_0_ctx_switch_enable
	mov	x0, x19
	bl	_sdma_v5_0_gfx_resume
	cbz	w0, LBB0_9
LBB0_8:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_9:
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_sdma_v5_0_rlc_resume
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_FW_LOAD_DIRECT,8,3      ; @AMDGPU_FW_LOAD_DIRECT
	.comm	_amdgpu_emu_mode,4,2            ; @amdgpu_emu_mode
	.no_dead_strip	_sdma_v5_0_start
.subsections_via_symbols
