	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function icl_disable_phy_clock_gating
_icl_disable_phy_clock_gating:          ## @icl_disable_phy_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movl	4(%rdi), %edi
	callq	_to_i915
	movl	(%rbx), %r15d
	movq	%rax, %rdi
	movl	%r15d, %esi
	callq	_intel_port_to_tc
	movl	%eax, %r14d
	movq	_PORT_TC_NONE@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r14d
	jne	LBB0_2
## %bb.1:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	xorl	%edi, %edi
	movl	%r15d, %esi
	callq	_MG_DP_MODE
	movl	%eax, %edi
	callq	_I915_READ
	movq	_MG_DP_MODE_CFG_TR2PWR_GATING@GOTPCREL(%rip), %rcx
	movq	_MG_DP_MODE_CFG_TRPWR_GATING@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	movq	_MG_DP_MODE_CFG_CLNPWR_GATING@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_MG_DP_MODE_CFG_DIGPWR_GATING@GOTPCREL(%rip), %r12
	orl	(%r12), %ebx
	movq	_MG_DP_MODE_CFG_GAONPWR_GATING@GOTPCREL(%rip), %r13
	orl	(%r13), %ebx
	notl	%ebx
	andl	%eax, %ebx
	xorl	%edi, %edi
	movl	%r15d, %esi
	callq	_MG_DP_MODE
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movl	$1, %edi
	movl	%r15d, %esi
	callq	_MG_DP_MODE
	movl	%eax, %edi
	callq	_I915_READ
	movq	_MG_DP_MODE_CFG_TRPWR_GATING@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	movq	_MG_DP_MODE_CFG_TR2PWR_GATING@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_MG_DP_MODE_CFG_CLNPWR_GATING@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	orl	(%r12), %ebx
	orl	(%r13), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	$1, %edi
	movl	%r15d, %esi
	callq	_MG_DP_MODE
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movl	%r14d, %edi
	callq	_MG_MISC_SUS0
	movl	%eax, %edi
	callq	_I915_READ
	movq	_MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK@GOTPCREL(%rip), %rcx
	movq	_MG_MISC_SUS0_CFG_TR2PWR_GATING@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	movq	_MG_MISC_SUS0_CFG_CL2PWR_GATING@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_MG_MISC_SUS0_CFG_GAONPWR_GATING@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_MG_MISC_SUS0_CFG_TRPWR_GATING@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_MG_MISC_SUS0_CFG_CL1PWR_GATING@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_MG_MISC_SUS0_CFG_DGPWR_GATING@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	%r14d, %edi
	callq	_MG_MISC_SUS0
	movl	%eax, %edi
	movl	%ebx, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_I915_WRITE                     ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PORT_TC_NONE,4,2               ## @PORT_TC_NONE
	.comm	_MG_DP_MODE_CFG_TR2PWR_GATING,4,2 ## @MG_DP_MODE_CFG_TR2PWR_GATING
	.comm	_MG_DP_MODE_CFG_TRPWR_GATING,4,2 ## @MG_DP_MODE_CFG_TRPWR_GATING
	.comm	_MG_DP_MODE_CFG_CLNPWR_GATING,4,2 ## @MG_DP_MODE_CFG_CLNPWR_GATING
	.comm	_MG_DP_MODE_CFG_DIGPWR_GATING,4,2 ## @MG_DP_MODE_CFG_DIGPWR_GATING
	.comm	_MG_DP_MODE_CFG_GAONPWR_GATING,4,2 ## @MG_DP_MODE_CFG_GAONPWR_GATING
	.comm	_MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK,4,2 ## @MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK
	.comm	_MG_MISC_SUS0_CFG_TR2PWR_GATING,4,2 ## @MG_MISC_SUS0_CFG_TR2PWR_GATING
	.comm	_MG_MISC_SUS0_CFG_CL2PWR_GATING,4,2 ## @MG_MISC_SUS0_CFG_CL2PWR_GATING
	.comm	_MG_MISC_SUS0_CFG_GAONPWR_GATING,4,2 ## @MG_MISC_SUS0_CFG_GAONPWR_GATING
	.comm	_MG_MISC_SUS0_CFG_TRPWR_GATING,4,2 ## @MG_MISC_SUS0_CFG_TRPWR_GATING
	.comm	_MG_MISC_SUS0_CFG_CL1PWR_GATING,4,2 ## @MG_MISC_SUS0_CFG_CL1PWR_GATING
	.comm	_MG_MISC_SUS0_CFG_DGPWR_GATING,4,2 ## @MG_MISC_SUS0_CFG_DGPWR_GATING
	.no_dead_strip	_icl_disable_phy_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function icl_disable_phy_clock_gating
_icl_disable_phy_clock_gating:          ; @icl_disable_phy_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldr	w0, [x0, #4]
	bl	_to_i915
	ldr	w20, [x19]
	mov	x1, x20
	bl	_intel_port_to_tc
Lloh0:
	adrp	x8, _PORT_TC_NONE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PORT_TC_NONE@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cmp	w0, w8
	b.ne	LBB0_2
; %bb.1:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_2:
	mov	x19, x0
	mov	w0, #0
	mov	x1, x20
	bl	_MG_DP_MODE
	bl	_I915_READ
Lloh3:
	adrp	x22, _MG_DP_MODE_CFG_TR2PWR_GATING@GOTPAGE
Lloh4:
	ldr	x22, [x22, _MG_DP_MODE_CFG_TR2PWR_GATING@GOTPAGEOFF]
	ldr	w8, [x22]
Lloh5:
	adrp	x23, _MG_DP_MODE_CFG_TRPWR_GATING@GOTPAGE
Lloh6:
	ldr	x23, [x23, _MG_DP_MODE_CFG_TRPWR_GATING@GOTPAGEOFF]
	ldr	w9, [x23]
Lloh7:
	adrp	x24, _MG_DP_MODE_CFG_CLNPWR_GATING@GOTPAGE
Lloh8:
	ldr	x24, [x24, _MG_DP_MODE_CFG_CLNPWR_GATING@GOTPAGEOFF]
	orr	w8, w9, w8
	ldr	w9, [x24]
	orr	w8, w8, w9
Lloh9:
	adrp	x25, _MG_DP_MODE_CFG_DIGPWR_GATING@GOTPAGE
Lloh10:
	ldr	x25, [x25, _MG_DP_MODE_CFG_DIGPWR_GATING@GOTPAGEOFF]
	ldr	w9, [x25]
	orr	w8, w8, w9
Lloh11:
	adrp	x26, _MG_DP_MODE_CFG_GAONPWR_GATING@GOTPAGE
Lloh12:
	ldr	x26, [x26, _MG_DP_MODE_CFG_GAONPWR_GATING@GOTPAGEOFF]
	ldr	w9, [x26]
	orr	w8, w8, w9
	bic	w21, w0, w8
	mov	w0, #0
	mov	x1, x20
	bl	_MG_DP_MODE
	mov	x1, x21
	bl	_I915_WRITE
	mov	w0, #1
	mov	x1, x20
	bl	_MG_DP_MODE
	bl	_I915_READ
	ldr	w8, [x22]
	ldr	w9, [x23]
	orr	w8, w9, w8
	ldr	w9, [x24]
	orr	w8, w8, w9
	ldr	w9, [x25]
	orr	w8, w8, w9
	ldr	w9, [x26]
	orr	w8, w8, w9
	bic	w21, w0, w8
	mov	w0, #1
	mov	x1, x20
	bl	_MG_DP_MODE
	mov	x1, x21
	bl	_I915_WRITE
	mov	x0, x19
	bl	_MG_MISC_SUS0
	bl	_I915_READ
Lloh13:
	adrp	x8, _MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK@GOTPAGE
Lloh14:
	ldr	x8, [x8, _MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK@GOTPAGEOFF]
Lloh15:
	adrp	x9, _MG_MISC_SUS0_CFG_TR2PWR_GATING@GOTPAGE
Lloh16:
	ldr	x9, [x9, _MG_MISC_SUS0_CFG_TR2PWR_GATING@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
Lloh18:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh19:
	adrp	x9, _MG_MISC_SUS0_CFG_CL2PWR_GATING@GOTPAGE
Lloh20:
	ldr	x9, [x9, _MG_MISC_SUS0_CFG_CL2PWR_GATING@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh22:
	adrp	x9, _MG_MISC_SUS0_CFG_GAONPWR_GATING@GOTPAGE
Lloh23:
	ldr	x9, [x9, _MG_MISC_SUS0_CFG_GAONPWR_GATING@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
Lloh25:
	adrp	x10, _MG_MISC_SUS0_CFG_TRPWR_GATING@GOTPAGE
Lloh26:
	ldr	x10, [x10, _MG_MISC_SUS0_CFG_TRPWR_GATING@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh27:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh28:
	adrp	x9, _MG_MISC_SUS0_CFG_CL1PWR_GATING@GOTPAGE
Lloh29:
	ldr	x9, [x9, _MG_MISC_SUS0_CFG_CL1PWR_GATING@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh31:
	adrp	x9, _MG_MISC_SUS0_CFG_DGPWR_GATING@GOTPAGE
Lloh32:
	ldr	x9, [x9, _MG_MISC_SUS0_CFG_DGPWR_GATING@GOTPAGEOFF]
Lloh33:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w20, w0, w8
	mov	x0, x19
	bl	_MG_MISC_SUS0
	mov	x1, x20
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_I915_WRITE
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh17
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_PORT_TC_NONE,4,2               ; @PORT_TC_NONE
	.comm	_MG_DP_MODE_CFG_TR2PWR_GATING,4,2 ; @MG_DP_MODE_CFG_TR2PWR_GATING
	.comm	_MG_DP_MODE_CFG_TRPWR_GATING,4,2 ; @MG_DP_MODE_CFG_TRPWR_GATING
	.comm	_MG_DP_MODE_CFG_CLNPWR_GATING,4,2 ; @MG_DP_MODE_CFG_CLNPWR_GATING
	.comm	_MG_DP_MODE_CFG_DIGPWR_GATING,4,2 ; @MG_DP_MODE_CFG_DIGPWR_GATING
	.comm	_MG_DP_MODE_CFG_GAONPWR_GATING,4,2 ; @MG_DP_MODE_CFG_GAONPWR_GATING
	.comm	_MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK,4,2 ; @MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK
	.comm	_MG_MISC_SUS0_CFG_TR2PWR_GATING,4,2 ; @MG_MISC_SUS0_CFG_TR2PWR_GATING
	.comm	_MG_MISC_SUS0_CFG_CL2PWR_GATING,4,2 ; @MG_MISC_SUS0_CFG_CL2PWR_GATING
	.comm	_MG_MISC_SUS0_CFG_GAONPWR_GATING,4,2 ; @MG_MISC_SUS0_CFG_GAONPWR_GATING
	.comm	_MG_MISC_SUS0_CFG_TRPWR_GATING,4,2 ; @MG_MISC_SUS0_CFG_TRPWR_GATING
	.comm	_MG_MISC_SUS0_CFG_CL1PWR_GATING,4,2 ; @MG_MISC_SUS0_CFG_CL1PWR_GATING
	.comm	_MG_MISC_SUS0_CFG_DGPWR_GATING,4,2 ; @MG_MISC_SUS0_CFG_DGPWR_GATING
	.no_dead_strip	_icl_disable_phy_clock_gating
.subsections_via_symbols
