	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function soc15_common_get_clockgating_state
_soc15_common_get_clockgating_state:    ## @soc15_common_get_clockgating_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %rbx
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movl	$0, (%r14)
LBB0_2:
	movq	8(%rbx), %rax
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	*(%rax)
	movq	_HDP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmHDP_MEM_POWER_LS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	callq	_RREG32
	movq	_HDP_MEM_POWER_LS__LS_ENABLE_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_4
## %bb.3:
	movq	_AMD_CG_SUPPORT_HDP_LS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r14)
LBB0_4:
	movq	_MP0@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	movq	_mmMP0_MISC_CGTT_CTRL0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	callq	_RREG32
	testl	$16777216, %eax                 ## imm = 0x1000000
	jne	LBB0_6
## %bb.5:
	movq	_AMD_CG_SUPPORT_DRM_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r14)
LBB0_6:
	movl	(%r15), %edi
	movq	_mmMP0_MISC_LIGHT_SLEEP_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	callq	_RREG32
	testb	$1, %al
	je	LBB0_8
## %bb.7:
	movq	_AMD_CG_SUPPORT_DRM_LS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r14)
LBB0_8:
	movq	_SMUIO@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmCGTT_ROM_CLK_CTRL0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	callq	_RREG32
	movq	_CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	jne	LBB0_10
## %bb.9:
	movq	_AMD_CG_SUPPORT_ROM_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r14)
LBB0_10:
	movq	(%rbx), %rax
	movq	(%rax), %rax
	movq	%rbx, %rdi
	movq	%r14, %rsi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmpq	*%rax                           ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_HDP,4,2                        ## @HDP
	.comm	_mmHDP_MEM_POWER_LS,4,2         ## @mmHDP_MEM_POWER_LS
	.comm	_HDP_MEM_POWER_LS__LS_ENABLE_MASK,4,2 ## @HDP_MEM_POWER_LS__LS_ENABLE_MASK
	.comm	_AMD_CG_SUPPORT_HDP_LS,4,2      ## @AMD_CG_SUPPORT_HDP_LS
	.comm	_MP0,4,2                        ## @MP0
	.comm	_mmMP0_MISC_CGTT_CTRL0,4,2      ## @mmMP0_MISC_CGTT_CTRL0
	.comm	_AMD_CG_SUPPORT_DRM_MGCG,4,2    ## @AMD_CG_SUPPORT_DRM_MGCG
	.comm	_mmMP0_MISC_LIGHT_SLEEP_CTRL,4,2 ## @mmMP0_MISC_LIGHT_SLEEP_CTRL
	.comm	_AMD_CG_SUPPORT_DRM_LS,4,2      ## @AMD_CG_SUPPORT_DRM_LS
	.comm	_SMUIO,4,2                      ## @SMUIO
	.comm	_mmCGTT_ROM_CLK_CTRL0,4,2       ## @mmCGTT_ROM_CLK_CTRL0
	.comm	_CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK,4,2 ## @CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK
	.comm	_AMD_CG_SUPPORT_ROM_MGCG,4,2    ## @AMD_CG_SUPPORT_ROM_MGCG
	.no_dead_strip	_soc15_common_get_clockgating_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function soc15_common_get_clockgating_state
_soc15_common_get_clockgating_state:    ; @soc15_common_get_clockgating_state
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x1
	mov	x20, x0
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_2
; %bb.1:
	str	wzr, [x19]
LBB0_2:
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	mov	x0, x20
	mov	x1, x19
	blr	x8
Lloh0:
	adrp	x8, _HDP@GOTPAGE
Lloh1:
	ldr	x8, [x8, _HDP@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
Lloh3:
	adrp	x8, _mmHDP_MEM_POWER_LS@GOTPAGE
Lloh4:
	ldr	x8, [x8, _mmHDP_MEM_POWER_LS@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	bl	_RREG32
Lloh6:
	adrp	x8, _HDP_MEM_POWER_LS__LS_ENABLE_MASK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _HDP_MEM_POWER_LS__LS_ENABLE_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_4
; %bb.3:
Lloh9:
	adrp	x8, _AMD_CG_SUPPORT_HDP_LS@GOTPAGE
Lloh10:
	ldr	x8, [x8, _AMD_CG_SUPPORT_HDP_LS@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_4:
Lloh12:
	adrp	x21, _MP0@GOTPAGE
Lloh13:
	ldr	x21, [x21, _MP0@GOTPAGEOFF]
	ldr	w0, [x21]
Lloh14:
	adrp	x8, _mmMP0_MISC_CGTT_CTRL0@GOTPAGE
Lloh15:
	ldr	x8, [x8, _mmMP0_MISC_CGTT_CTRL0@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	bl	_RREG32
	tbnz	w0, #24, LBB0_6
; %bb.5:
Lloh17:
	adrp	x8, _AMD_CG_SUPPORT_DRM_MGCG@GOTPAGE
Lloh18:
	ldr	x8, [x8, _AMD_CG_SUPPORT_DRM_MGCG@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_6:
	ldr	w0, [x21]
Lloh20:
	adrp	x8, _mmMP0_MISC_LIGHT_SLEEP_CTRL@GOTPAGE
Lloh21:
	ldr	x8, [x8, _mmMP0_MISC_LIGHT_SLEEP_CTRL@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	bl	_RREG32
	tbz	w0, #0, LBB0_8
; %bb.7:
Lloh23:
	adrp	x8, _AMD_CG_SUPPORT_DRM_LS@GOTPAGE
Lloh24:
	ldr	x8, [x8, _AMD_CG_SUPPORT_DRM_LS@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_8:
Lloh26:
	adrp	x8, _SMUIO@GOTPAGE
Lloh27:
	ldr	x8, [x8, _SMUIO@GOTPAGEOFF]
Lloh28:
	ldr	w0, [x8]
Lloh29:
	adrp	x8, _mmCGTT_ROM_CLK_CTRL0@GOTPAGE
Lloh30:
	ldr	x8, [x8, _mmCGTT_ROM_CLK_CTRL0@GOTPAGEOFF]
Lloh31:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	bl	_RREG32
Lloh32:
	adrp	x8, _CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK@GOTPAGE
Lloh33:
	ldr	x8, [x8, _CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK@GOTPAGEOFF]
Lloh34:
	ldr	w8, [x8]
	tst	w8, w0
	b.ne	LBB0_10
; %bb.9:
Lloh35:
	adrp	x8, _AMD_CG_SUPPORT_ROM_MGCG@GOTPAGE
Lloh36:
	ldr	x8, [x8, _AMD_CG_SUPPORT_ROM_MGCG@GOTPAGEOFF]
Lloh37:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_10:
	ldr	x8, [x20]
	ldr	x2, [x8]
	mov	x0, x20
	mov	x1, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	br	x2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.cfi_endproc
                                        ; -- End function
	.comm	_HDP,4,2                        ; @HDP
	.comm	_mmHDP_MEM_POWER_LS,4,2         ; @mmHDP_MEM_POWER_LS
	.comm	_HDP_MEM_POWER_LS__LS_ENABLE_MASK,4,2 ; @HDP_MEM_POWER_LS__LS_ENABLE_MASK
	.comm	_AMD_CG_SUPPORT_HDP_LS,4,2      ; @AMD_CG_SUPPORT_HDP_LS
	.comm	_MP0,4,2                        ; @MP0
	.comm	_mmMP0_MISC_CGTT_CTRL0,4,2      ; @mmMP0_MISC_CGTT_CTRL0
	.comm	_AMD_CG_SUPPORT_DRM_MGCG,4,2    ; @AMD_CG_SUPPORT_DRM_MGCG
	.comm	_mmMP0_MISC_LIGHT_SLEEP_CTRL,4,2 ; @mmMP0_MISC_LIGHT_SLEEP_CTRL
	.comm	_AMD_CG_SUPPORT_DRM_LS,4,2      ; @AMD_CG_SUPPORT_DRM_LS
	.comm	_SMUIO,4,2                      ; @SMUIO
	.comm	_mmCGTT_ROM_CLK_CTRL0,4,2       ; @mmCGTT_ROM_CLK_CTRL0
	.comm	_CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK,4,2 ; @CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK
	.comm	_AMD_CG_SUPPORT_ROM_MGCG,4,2    ; @AMD_CG_SUPPORT_ROM_MGCG
	.no_dead_strip	_soc15_common_get_clockgating_state
.subsections_via_symbols
