	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function r100_packet0_check
_r100_packet0_check:                    ## @r100_packet0_check
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %ebx
	movl	%edx, %r14d
	movq	%rsi, -56(%rbp)                 ## 8-byte Spill
	movq	%rdi, %r13
	movq	8(%rdi), %r12
	movq	16(%rdi), %rax
	movq	%rax, -72(%rbp)                 ## 8-byte Spill
	movl	%edx, %esi
	callq	_radeon_get_ib_value
	movl	%eax, %r15d
	leal	-147(%rbx), %eax
	cmpl	$46, %eax
	ja	LBB0_31
## %bb.1:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_2:
	movq	%r12, -64(%rbp)                 ## 8-byte Spill
	leaq	-48(%rbp), %rsi
	movq	%r13, %rdi
	xorl	%edx, %edx
	callq	_radeon_cs_packet_next_reloc
	testl	%eax, %eax
	jne	LBB0_10
## %bb.3:
	addl	$-177, %ebx
	shrl	$2, %ebx
	movq	-64(%rbp), %r8                  ## 8-byte Reload
	movq	32(%r8), %rax
	movq	168(%rax), %rax
	jmp	LBB0_8
LBB0_4:
	movq	%r12, -64(%rbp)                 ## 8-byte Spill
	leaq	-48(%rbp), %rsi
	movq	%r13, %rdi
	xorl	%edx, %edx
	callq	_radeon_cs_packet_next_reloc
	testl	%eax, %eax
	jne	LBB0_10
## %bb.5:
	addl	$-182, %ebx
	shrl	$2, %ebx
	movq	-64(%rbp), %r8                  ## 8-byte Reload
	movq	32(%r8), %rax
	movq	104(%rax), %rax
	jmp	LBB0_8
LBB0_6:
	movq	%r12, -64(%rbp)                 ## 8-byte Spill
	leaq	-48(%rbp), %rsi
	movq	%r13, %rdi
	xorl	%edx, %edx
	callq	_radeon_cs_packet_next_reloc
	testl	%eax, %eax
	jne	LBB0_10
## %bb.7:
	addl	$-187, %ebx
	shrl	$2, %ebx
	movq	-64(%rbp), %r8                  ## 8-byte Reload
	movq	32(%r8), %rax
	movq	40(%rax), %rax
LBB0_8:
	shlq	$4, %rbx
	movl	%r15d, (%rax,%rbx)
	movq	-48(%rbp), %rcx
	movl	4(%rcx), %edx
	addl	%r15d, %edx
	movl	%r14d, %esi
	movq	-72(%rbp), %rdi                 ## 8-byte Reload
	movl	%edx, (%rdi,%rsi,4)
	movl	8(%rcx), %ecx
	movl	%ecx, 12(%rax,%rbx)
	movl	$1, 8(%r8)
	jmp	LBB0_81
LBB0_9:
	movq	%r12, -64(%rbp)                 ## 8-byte Spill
	leaq	-48(%rbp), %rsi
	movq	%r13, %rdi
	xorl	%edx, %edx
	callq	_radeon_cs_packet_next_reloc
	testl	%eax, %eax
	je	LBB0_23
LBB0_10:
	movl	%eax, %r12d
	leaq	L_.str(%rip), %rdi
	movl	%r14d, %esi
	movl	%ebx, %edx
LBB0_11:
	xorl	%eax, %eax
	callq	_DRM_ERROR
	movq	%r13, %rdi
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
	callq	_radeon_cs_dump_packet
	jmp	LBB0_82
LBB0_12:
	addl	$-163, %ebx
	movl	$2863311531, %edx               ## imm = 0xAAAAAAAB
	imulq	%rbx, %rdx
	shrq	$36, %rdx
	movq	_RADEON_TXFORMAT_NON_POWER2@GOTPCREL(%rip), %rcx
	shlq	$6, %rdx
	movq	32(%r12), %rsi
	leaq	(%rsi,%rdx), %rax
	addq	$24, %rax
	testl	%r15d, (%rcx)
	je	LBB0_25
## %bb.13:
	movl	$1, (%rax)
	jmp	LBB0_26
LBB0_14:
	addl	$-166, %ebx
	movl	$2863311531, %eax               ## imm = 0xAAAAAAAB
	imulq	%rbx, %rax
	shrq	$36, %rax
	movq	_RADEON_MAX_MIP_LEVEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	andl	%r15d, %edx
	movq	_RADEON_MAX_MIP_LEVEL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %edx
	movq	32(%r12), %rcx
	shlq	$6, %rax
	movl	%edx, 12(%rcx,%rax)
	movl	%r15d, %edx
	andl	$25165824, %edx                 ## imm = 0x1800000
	cmpl	$16777216, %edx                 ## imm = 0x1000000
	jne	LBB0_16
## %bb.15:
	movl	$0, 16(%rcx,%rax)
LBB0_16:
	andl	$402653184, %r15d               ## imm = 0x18000000
	cmpl	$268435456, %r15d               ## imm = 0x10000000
	jne	LBB0_78
## %bb.17:
	movl	$0, 20(%rcx,%rax)
	jmp	LBB0_78
LBB0_19:
	addl	$-169, %ebx
	shrl	$3, %ebx
	movq	_RADEON_TEX_USIZE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r15d, %eax
	incl	%eax
	movq	32(%r12), %rdx
	shlq	$6, %rbx
	movl	%eax, 4(%rdx,%rbx)
	movq	_RADEON_TEX_VSIZE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r15d, %eax
	movq	_RADEON_TEX_VSIZE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	incl	%eax
	movl	%eax, 8(%rdx,%rbx)
	movl	$1, 8(%r12)
	jmp	LBB0_81
LBB0_20:
	addl	$-172, %ebx
	shrl	$3, %ebx
	addl	$32, %r15d
	movq	32(%r12), %rax
	shlq	$6, %rbx
	movl	%r15d, 56(%rax,%rbx)
	movl	$1, 8(%r12)
	jmp	LBB0_81
LBB0_21:
	addl	$-190, %ebx
	movl	%r15d, %ecx
	andb	$15, %cl
	movl	$1, %esi
	shll	%cl, %esi
	movl	%r15d, %ecx
	shrb	$4, %cl
	movl	$1, %edi
	shll	%cl, %edi
	shrl	$2, %ebx
	movq	32(%r12), %rax
	movl	%r15d, %ecx
	shrl	$8, %ecx
	andb	$15, %cl
	movl	$1, %edx
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %edx
	shlq	$6, %rbx
	movq	40(%rax,%rbx), %rax
	movl	%r15d, %ecx
	shrl	$12, %ecx
	andb	$15, %cl
	movl	$1, %ebx
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %ebx
	movl	$1, %r8d
	movl	%esi, 4(%rax)
	movl	%r15d, %ecx
	shrl	$16, %ecx
	andb	$15, %cl
	movl	$1, %esi
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %esi
	movl	%edi, 8(%rax)
	movl	%edx, 20(%rax)
	movl	%r15d, %ecx
	shrl	$20, %ecx
	andb	$15, %cl
	movl	$1, %edx
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %edx
	movl	%ebx, 24(%rax)
	movl	%esi, 36(%rax)
	movl	%r15d, %ecx
	shrl	$24, %ecx
	andb	$15, %cl
	movl	$1, %esi
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %esi
	shrl	$28, %r15d
	movl	%r15d, %ecx
	shll	%cl, %r8d
	movl	%edx, 40(%rax)
	movl	%esi, 52(%rax)
	movl	%r8d, 56(%rax)
	movl	$1, 8(%r12)
	jmp	LBB0_81
LBB0_22:
	movq	%r13, %rdi
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
	movl	%r14d, %edx
	movl	%ebx, %ecx
	callq	_r100_reloc_pitch_offset
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	LBB0_82
	jmp	LBB0_81
LBB0_23:
	addl	$-160, %ebx
	movl	$2863311531, %eax               ## imm = 0xAAAAAAAB
	imulq	%rbx, %rax
	shrq	$36, %rax
	movq	_RADEON_CS_KEEP_TILING_FLAGS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	-48(%rbp), %rcx
	testl	%edx, (%r13)
	je	LBB0_56
## %bb.24:
	movl	4(%rcx), %edx
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	jmp	LBB0_61
LBB0_25:
	movl	$0, (%rax)
	movq	_RADEON_TXFORMAT_WIDTH_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	%r15d, %eax
	sarl	%cl, %eax
	movq	_RADEON_TXFORMAT_WIDTH_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movl	$1, %edi
	movl	%eax, %ecx
	shll	%cl, %edi
	movl	%edi, 4(%rsi,%rdx)
	movq	_RADEON_TXFORMAT_HEIGHT_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	%r15d, %eax
	sarl	%cl, %eax
	movl	$1, %edi
	movq	_RADEON_TXFORMAT_HEIGHT_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movl	%eax, %ecx
	shll	%cl, %edi
	movl	%edi, 8(%rsi,%rdx)
LBB0_26:
	movq	_RADEON_TXFORMAT_CUBIC_MAP_ENABLE@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_28
## %bb.27:
	movl	$2, 28(%rsi,%rdx)
LBB0_28:
	movq	_RADEON_TXFORMAT_FORMAT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r15d, %eax
	addl	$-128, %eax
	cmpl	$18, %eax
	ja	LBB0_30
## %bb.29:
	cltq
	leaq	l_switch.table.r100_packet0_check.4(%rip), %rcx
	movl	(%rcx,%rax,4), %ecx
	leaq	l_switch.table.r100_packet0_check.5(%rip), %rdi
	movq	(%rdi,%rax,8), %rax
	movl	%ecx, 32(%rsi,%rdx)
	movq	(%rax), %rax
	movq	%rax, 48(%rsi,%rdx)
LBB0_30:
	movl	%r15d, %ecx
	shrl	$16, %ecx
	andb	$15, %cl
	movl	$1, %eax
	movl	$1, %edi
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %edi
	shrl	$20, %r15d
	andb	$15, %r15b
	movl	%r15d, %ecx
	shll	%cl, %eax
	movq	40(%rsi,%rdx), %rcx
	movl	%edi, 68(%rcx)
	movl	%eax, 72(%rcx)
	movl	$1, 8(%r12)
	jmp	LBB0_81
LBB0_31:
	leaq	L_.str.2(%rip), %rdi
	movl	%ebx, %esi
	movl	%r14d, %edx
	callq	_pr_err
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r12d, %r12d
	subl	(%rax), %r12d
	jmp	LBB0_82
LBB0_32:
	movl	%r15d, %edi
	callq	_r100_get_vtx_size
	movl	%eax, 40(%r12)
	jmp	LBB0_81
LBB0_33:
	movl	%r15d, 24(%r12)
	jmp	LBB0_81
LBB0_34:
	shrl	$16, %r15d
	andl	$2047, %r15d                    ## imm = 0x7FF
	movl	%r15d, 12(%r12)
	jmp	LBB0_80
LBB0_35:
	andl	$15, %r15d
	cmpl	$11, %r15d
	ja	LBB0_38
## %bb.36:
	movl	$2621, %eax                     ## imm = 0xA3D
	btl	%r15d, %eax
	jae	LBB0_38
## %bb.37:
	movl	%r15d, %eax
	leaq	l_switch.table.r100_packet0_check.3(%rip), %rcx
	movl	(%rcx,%rax,4), %eax
	movl	%eax, 52(%r12)
LBB0_38:
	movl	$1, (%r12)
	jmp	LBB0_81
LBB0_39:
	leaq	-48(%rbp), %rsi
	movq	%r13, %rdi
	xorl	%edx, %edx
	callq	_radeon_cs_packet_next_reloc
	testl	%eax, %eax
	je	LBB0_62
## %bb.40:
	movl	%eax, %r12d
	leaq	L_.str(%rip), %rdi
	movl	%r14d, %esi
	movl	$152, %edx
	jmp	LBB0_11
LBB0_41:
	movq	_RADEON_DEPTHPITCH_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r15d, %eax
	movl	%eax, 48(%r12)
	movl	$1, (%r12)
	jmp	LBB0_81
LBB0_42:
	movq	%r12, %rbx
	leaq	-48(%rbp), %rsi
	movq	%r13, %rdi
	xorl	%edx, %edx
	callq	_radeon_cs_packet_next_reloc
	testl	%eax, %eax
	je	LBB0_63
## %bb.43:
	movl	%eax, %r12d
	leaq	L_.str(%rip), %rdi
	movl	%r14d, %esi
	movl	$154, %edx
	jmp	LBB0_11
LBB0_44:
	movq	%r12, %rbx
	leaq	-48(%rbp), %rsi
	movq	%r13, %rdi
	xorl	%edx, %edx
	callq	_radeon_cs_packet_next_reloc
	testl	%eax, %eax
	je	LBB0_64
## %bb.45:
	movl	%eax, %r12d
	leaq	L_.str(%rip), %rdi
	movl	%r14d, %esi
	movl	$155, %edx
	jmp	LBB0_11
LBB0_46:
	movq	%r12, %rbx
	leaq	-48(%rbp), %rsi
	movq	%r13, %rdi
	xorl	%edx, %edx
	callq	_radeon_cs_packet_next_reloc
	testl	%eax, %eax
	je	LBB0_71
## %bb.47:
	movl	%eax, %r12d
	leaq	L_.str(%rip), %rdi
	movl	%r14d, %esi
	movl	$156, %edx
	jmp	LBB0_11
LBB0_48:
	movq	_RADEON_RB3D_COLOR_FORMAT_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	%r15d, %esi
	sarl	%cl, %esi
	andl	$31, %esi
	leal	-3(%rsi), %eax
	cmpl	$13, %eax
	jae	LBB0_50
## %bb.49:
	movl	$4987, %ecx                     ## imm = 0x137B
	btl	%eax, %ecx
	jb	LBB0_79
LBB0_50:
	leaq	L_.str.1(%rip), %rdi
	xorl	%r12d, %r12d
                                        ## kill: def $esi killed $esi killed $rsi
	xorl	%eax, %eax
	callq	_DRM_ERROR
	movq	_EINVAL@GOTPCREL(%rip), %rax
	subl	(%rax), %r12d
	jmp	LBB0_82
LBB0_51:
	movl	20(%r12), %esi
	testl	%esi, %esi
	jle	LBB0_78
## %bb.52:
	sarl	$4, %r15d
	movq	32(%r12), %r8
	leaq	-1(%rsi), %rdx
	movl	%esi, %ecx
	andl	$3, %ecx
	cmpq	$3, %rdx
	jae	LBB0_73
## %bb.53:
	xorl	%edx, %edx
	jmp	LBB0_75
LBB0_54:
	movq	%r13, %rdi
	callq	_r100_cs_packet_parse_vline
	testl	%eax, %eax
	je	LBB0_81
## %bb.55:
	movl	%eax, %r12d
	leaq	L_.str(%rip), %rdi
	movl	%r14d, %esi
	movl	$193, %edx
	jmp	LBB0_11
LBB0_56:
	movq	_RADEON_TILING_MACRO@GOTPCREL(%rip), %rdx
	movl	(%rcx), %esi
	movl	(%rdx), %edx
	andl	%esi, %edx
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	je	LBB0_58
## %bb.57:
	movq	_RADEON_TXO_MACRO_TILE@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
LBB0_58:
	movq	_RADEON_TILING_MICRO@GOTPCREL(%rip), %rdi
	andl	(%rdi), %esi
	je	LBB0_60
## %bb.59:
	movq	_RADEON_TXO_MICRO_TILE_X2@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
LBB0_60:
	movl	4(%rcx), %edi
	andl	$-29, %r15d
	orl	%r15d, %edx
	orl	%esi, %edx
	movl	%edi, %r15d
LBB0_61:
	addl	%edx, %r15d
	movl	%r14d, %edx
	movq	-72(%rbp), %rsi                 ## 8-byte Reload
	movl	%r15d, (%rsi,%rdx,4)
	movl	8(%rcx), %ecx
	movq	32(%rbx), %rdx
	movl	%eax, %eax
	shlq	$6, %rax
	movl	%ecx, 60(%rdx,%rax)
	movl	$1, 8(%rbx)
	jmp	LBB0_81
LBB0_62:
	movq	-48(%rbp), %rax
	jmp	LBB0_72
LBB0_63:
	movq	-48(%rbp), %rax
	movl	8(%rax), %ecx
	movl	%ecx, 56(%rbx)
	movl	%r15d, 44(%rbx)
	movl	$1, (%rbx)
	jmp	LBB0_72
LBB0_64:
	movq	_RADEON_CS_KEEP_TILING_FLAGS@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%r15d, %eax
	testl	%ecx, (%r13)
	movq	%rbx, %rsi
	jne	LBB0_70
## %bb.65:
	movq	-48(%rbp), %rax
	movl	(%rax), %ecx
	movq	_RADEON_TILING_MACRO@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%ecx, %eax
	je	LBB0_67
## %bb.66:
	movq	_RADEON_COLOR_TILE_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_67:
	movq	_RADEON_TILING_MICRO@GOTPCREL(%rip), %rdx
	andl	(%rdx), %ecx
	je	LBB0_69
## %bb.68:
	movq	_RADEON_COLOR_MICROTILE_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_69:
	movl	%r15d, %edx
	andl	$-458753, %edx                  ## imm = 0xFFF8FFFF
	orl	%edx, %eax
	orl	%ecx, %eax
LBB0_70:
	movl	%r14d, %ecx
	movq	-72(%rbp), %rdx                 ## 8-byte Reload
	movl	%eax, (%rdx,%rcx,4)
	movq	_RADEON_COLORPITCH_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r15d, %eax
	movq	64(%rsi), %rcx
	movl	%eax, 4(%rcx)
	movl	$1, 4(%rsi)
	jmp	LBB0_81
LBB0_71:
	movq	-48(%rbp), %rax
	movl	8(%rax), %ecx
	movq	64(%rbx), %rdx
	movl	%ecx, 12(%rdx)
	movl	%r15d, (%rdx)
	movl	$1, 4(%rbx)
LBB0_72:
	movl	4(%rax), %eax
	addl	%r15d, %eax
	movl	%r14d, %ecx
	movq	-72(%rbp), %rdx                 ## 8-byte Reload
	movl	%eax, (%rdx,%rcx,4)
	jmp	LBB0_81
LBB0_73:
	andl	$-4, %esi
	leaq	192(%r8), %rdi
	xorl	%edx, %edx
	.p2align	4, 0x90
LBB0_74:                                ## =>This Inner Loop Header: Depth=1
	xorl	%ebx, %ebx
	btl	%edx, %r15d
	setb	%bl
	movl	%ebx, -192(%rdi)
	leal	1(%rdx), %ebx
	movzbl	%bl, %ebx
	xorl	%eax, %eax
	btl	%ebx, %r15d
	setb	%al
	movl	%eax, -128(%rdi)
	leal	2(%rdx), %eax
	movzbl	%al, %eax
	xorl	%ebx, %ebx
	btl	%eax, %r15d
	setb	%bl
	movl	%ebx, -64(%rdi)
	leal	3(%rdx), %eax
	movzbl	%al, %eax
	xorl	%ebx, %ebx
	btl	%eax, %r15d
	setb	%bl
	movl	%ebx, (%rdi)
	addq	$4, %rdx
	addq	$256, %rdi                      ## imm = 0x100
	cmpq	%rsi, %rdx
	jne	LBB0_74
LBB0_75:
	testq	%rcx, %rcx
	je	LBB0_78
## %bb.76:
	movq	%rdx, %rax
	shlq	$6, %rax
	addq	%rax, %r8
	shlq	$6, %rcx
	xorl	%esi, %esi
	.p2align	4, 0x90
LBB0_77:                                ## =>This Inner Loop Header: Depth=1
	xorl	%eax, %eax
	btl	%edx, %r15d
	setb	%al
	movl	%eax, (%r8,%rsi)
	addq	$64, %rsi
	incl	%edx
	cmpq	%rsi, %rcx
	jne	LBB0_77
LBB0_78:
	movl	$1, 8(%r12)
	jmp	LBB0_81
LBB0_79:
	cltq
	leaq	l_switch.table.r100_packet0_check(%rip), %rcx
	movl	(%rcx,%rax,4), %eax
	movq	64(%r12), %rcx
	movl	%eax, 8(%rcx)
	movq	_RADEON_Z_ENABLE@GOTPCREL(%rip), %rax
	xorl	%ecx, %ecx
	movl	(%rax), %eax
	andl	%r15d, %eax
	setne	%cl
	movl	%ecx, 16(%r12)
LBB0_80:
	movabsq	$4294967297, %rax               ## imm = 0x100000001
	movq	%rax, (%r12)
LBB0_81:
	xorl	%r12d, %r12d
LBB0_82:
	movl	%r12d, %eax
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_22, LBB0_22-LJTI0_0
.set L0_0_set_32, LBB0_32-LJTI0_0
.set L0_0_set_33, LBB0_33-LJTI0_0
.set L0_0_set_34, LBB0_34-LJTI0_0
.set L0_0_set_35, LBB0_35-LJTI0_0
.set L0_0_set_39, LBB0_39-LJTI0_0
.set L0_0_set_41, LBB0_41-LJTI0_0
.set L0_0_set_42, LBB0_42-LJTI0_0
.set L0_0_set_44, LBB0_44-LJTI0_0
.set L0_0_set_46, LBB0_46-LJTI0_0
.set L0_0_set_48, LBB0_48-LJTI0_0
.set L0_0_set_9, LBB0_9-LJTI0_0
.set L0_0_set_12, LBB0_12-LJTI0_0
.set L0_0_set_14, LBB0_14-LJTI0_0
.set L0_0_set_19, LBB0_19-LJTI0_0
.set L0_0_set_20, LBB0_20-LJTI0_0
.set L0_0_set_2, LBB0_2-LJTI0_0
.set L0_0_set_4, LBB0_4-LJTI0_0
.set L0_0_set_6, LBB0_6-LJTI0_0
.set L0_0_set_21, LBB0_21-LJTI0_0
.set L0_0_set_51, LBB0_51-LJTI0_0
.set L0_0_set_54, LBB0_54-LJTI0_0
LJTI0_0:
	.long	L0_0_set_22
	.long	L0_0_set_32
	.long	L0_0_set_33
	.long	L0_0_set_34
	.long	L0_0_set_35
	.long	L0_0_set_39
	.long	L0_0_set_41
	.long	L0_0_set_42
	.long	L0_0_set_44
	.long	L0_0_set_46
	.long	L0_0_set_48
	.long	L0_0_set_9
	.long	L0_0_set_9
	.long	L0_0_set_9
	.long	L0_0_set_12
	.long	L0_0_set_12
	.long	L0_0_set_12
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_19
	.long	L0_0_set_19
	.long	L0_0_set_19
	.long	L0_0_set_20
	.long	L0_0_set_20
	.long	L0_0_set_20
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_4
	.long	L0_0_set_4
	.long	L0_0_set_4
	.long	L0_0_set_4
	.long	L0_0_set_4
	.long	L0_0_set_6
	.long	L0_0_set_6
	.long	L0_0_set_6
	.long	L0_0_set_6
	.long	L0_0_set_6
	.long	L0_0_set_21
	.long	L0_0_set_21
	.long	L0_0_set_21
	.long	L0_0_set_51
	.long	L0_0_set_22
	.long	L0_0_set_54
	.end_data_region
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"No reloc for ib[%d]=0x%04X\n"

	.comm	_RADEON_CS_KEEP_TILING_FLAGS,4,2 ## @RADEON_CS_KEEP_TILING_FLAGS
	.comm	_RADEON_TILING_MACRO,4,2        ## @RADEON_TILING_MACRO
	.comm	_RADEON_TXO_MACRO_TILE,4,2      ## @RADEON_TXO_MACRO_TILE
	.comm	_RADEON_TILING_MICRO,4,2        ## @RADEON_TILING_MICRO
	.comm	_RADEON_TXO_MICRO_TILE_X2,4,2   ## @RADEON_TXO_MICRO_TILE_X2
	.comm	_RADEON_COLOR_TILE_ENABLE,4,2   ## @RADEON_COLOR_TILE_ENABLE
	.comm	_RADEON_COLOR_MICROTILE_ENABLE,4,2 ## @RADEON_COLOR_MICROTILE_ENABLE
	.comm	_RADEON_COLORPITCH_MASK,4,2     ## @RADEON_COLORPITCH_MASK
	.comm	_RADEON_DEPTHPITCH_MASK,4,2     ## @RADEON_DEPTHPITCH_MASK
	.comm	_RADEON_RB3D_COLOR_FORMAT_SHIFT,4,2 ## @RADEON_RB3D_COLOR_FORMAT_SHIFT
L_.str.1:                               ## @.str.1
	.asciz	"Invalid color buffer format (%d) !\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_RADEON_Z_ENABLE,4,2            ## @RADEON_Z_ENABLE
	.comm	_RADEON_TEX_USIZE_MASK,4,2      ## @RADEON_TEX_USIZE_MASK
	.comm	_RADEON_TEX_VSIZE_MASK,4,2      ## @RADEON_TEX_VSIZE_MASK
	.comm	_RADEON_TEX_VSIZE_SHIFT,4,2     ## @RADEON_TEX_VSIZE_SHIFT
	.comm	_RADEON_MAX_MIP_LEVEL_MASK,4,2  ## @RADEON_MAX_MIP_LEVEL_MASK
	.comm	_RADEON_MAX_MIP_LEVEL_SHIFT,4,2 ## @RADEON_MAX_MIP_LEVEL_SHIFT
	.comm	_RADEON_TXFORMAT_NON_POWER2,4,2 ## @RADEON_TXFORMAT_NON_POWER2
	.comm	_RADEON_TXFORMAT_WIDTH_SHIFT,4,2 ## @RADEON_TXFORMAT_WIDTH_SHIFT
	.comm	_RADEON_TXFORMAT_WIDTH_MASK,4,2 ## @RADEON_TXFORMAT_WIDTH_MASK
	.comm	_RADEON_TXFORMAT_HEIGHT_SHIFT,4,2 ## @RADEON_TXFORMAT_HEIGHT_SHIFT
	.comm	_RADEON_TXFORMAT_HEIGHT_MASK,4,2 ## @RADEON_TXFORMAT_HEIGHT_MASK
	.comm	_RADEON_TXFORMAT_CUBIC_MAP_ENABLE,4,2 ## @RADEON_TXFORMAT_CUBIC_MAP_ENABLE
	.comm	_RADEON_TXFORMAT_FORMAT_MASK,4,2 ## @RADEON_TXFORMAT_FORMAT_MASK
	.comm	_R100_TRACK_COMP_NONE,8,3       ## @R100_TRACK_COMP_NONE
	.comm	_R100_TRACK_COMP_DXT1,8,3       ## @R100_TRACK_COMP_DXT1
	.comm	_R100_TRACK_COMP_DXT35,8,3      ## @R100_TRACK_COMP_DXT35
L_.str.2:                               ## @.str.2
	.asciz	"Forbidden register 0x%04X in cs at %d\n"

	.no_dead_strip	_r100_packet0_check
	.section	__TEXT,__const
	.p2align	2                               ## @switch.table.r100_packet0_check
l_switch.table.r100_packet0_check:
	.long	2                               ## 0x2
	.long	2                               ## 0x2
	.long	1                               ## 0x1
	.long	4                               ## 0x4
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	2                               ## 0x2

	.p2align	2                               ## @switch.table.r100_packet0_check.3
l_switch.table.r100_packet0_check.3:
	.long	2                               ## 0x2
	.long	2                               ## 0x2
	.long	4                               ## 0x4
	.long	4                               ## 0x4
	.long	4                               ## 0x4
	.long	4                               ## 0x4
	.long	2                               ## 0x2
	.long	2                               ## 0x2
	.long	2                               ## 0x2
	.long	4                               ## 0x4
	.long	2                               ## 0x2
	.long	4                               ## 0x4

	.p2align	2                               ## @switch.table.r100_packet0_check.4
l_switch.table.r100_packet0_check.4:
	.long	2                               ## 0x2
	.long	1                               ## 0x1
	.long	2                               ## 0x2
	.long	4                               ## 0x4
	.long	2                               ## 0x2
	.long	4                               ## 0x4
	.long	2                               ## 0x2
	.long	1                               ## 0x1
	.long	2                               ## 0x2
	.long	4                               ## 0x4
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	2                               ## 0x2
	.long	4                               ## 0x4
	.long	2                               ## 0x2
	.long	2                               ## 0x2
	.long	2                               ## 0x2

	.section	__DATA,__const
	.p2align	3                               ## @switch.table.r100_packet0_check.5
l_switch.table.r100_packet0_check.5:
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_DXT35
	.quad	_R100_TRACK_COMP_DXT35
	.quad	_R100_TRACK_COMP_DXT1
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3                               ; -- Begin function r100_packet0_check
lCPI0_0:
	.long	4294967288                      ; 0xfffffff8
	.long	4294967284                      ; 0xfffffff4
lCPI0_1:
	.long	4294967280                      ; 0xfffffff0
	.long	4294967276                      ; 0xffffffec
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	2
_r100_packet0_check:                    ; @r100_packet0_check
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x24, x3
	mov	x20, x2
	mov	x21, x1
	mov	x22, x0
	ldp	x25, x26, [x0, #8]
	mov	x1, x2
	bl	_radeon_get_ib_value
	sub	w8, w24, #147
	cmp	w8, #46
	b.hi	LBB0_30
; %bb.1:
	mov	x19, x0
Lloh0:
	adrp	x9, lJTI0_0@PAGE
Lloh1:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_2
	ldrh	w11, [x9, x8, lsl #1]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_2:
	add	x1, sp, #8
	mov	x0, x22
	mov	w2, #0
	bl	_radeon_cs_packet_next_reloc
	cbnz	w0, LBB0_7
; %bb.3:
	sub	w8, w24, #177
	lsr	w8, w8, #2
	ldr	x9, [x25, #32]
	ldr	x9, [x9, #168]
	b	LBB0_21
LBB0_4:
	add	x1, sp, #8
	mov	x0, x22
	mov	w2, #0
	bl	_radeon_cs_packet_next_reloc
	cbnz	w0, LBB0_7
; %bb.5:
	sub	w8, w24, #182
	lsr	w8, w8, #2
	ldr	x9, [x25, #32]
	ldr	x9, [x9, #104]
	b	LBB0_21
LBB0_6:
	add	x1, sp, #8
	mov	x0, x22
	mov	w2, #0
	bl	_radeon_cs_packet_next_reloc
	cbz	w0, LBB0_20
LBB0_7:
	mov	x23, x0
                                        ; kill: def $w24 killed $w24 killed $x24 def $x24
	str	x24, [sp]
	b	LBB0_57
LBB0_8:
	add	x1, sp, #8
	mov	x0, x22
	mov	w2, #0
	bl	_radeon_cs_packet_next_reloc
	cbz	w0, LBB0_22
; %bb.9:
	mov	x23, x0
	str	x24, [sp]
	b	LBB0_57
LBB0_10:
	sub	w8, w24, #163
	mov	w9, #43691
	movk	w9, #43690, lsl #16
	umull	x8, w8, w9
Lloh2:
	adrp	x9, _RADEON_TXFORMAT_NON_POWER2@GOTPAGE
Lloh3:
	ldr	x9, [x9, _RADEON_TXFORMAT_NON_POWER2@GOTPAGEOFF]
	lsr	x8, x8, #36
Lloh4:
	ldr	w12, [x9]
	ldr	x9, [x25, #32]
	add	x10, x9, x8, lsl #6
	add	x11, x10, #24
	tst	w12, w19
	b.eq	LBB0_24
; %bb.11:
	mov	w10, #1
	str	w10, [x11]
	b	LBB0_25
LBB0_12:
	sub	w8, w24, #166
	mov	w9, #43691
	movk	w9, #43690, lsl #16
	umull	x8, w8, w9
	lsr	x8, x8, #36
Lloh5:
	adrp	x9, _RADEON_MAX_MIP_LEVEL_MASK@GOTPAGE
Lloh6:
	ldr	x9, [x9, _RADEON_MAX_MIP_LEVEL_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	and	w9, w9, w19
Lloh8:
	adrp	x10, _RADEON_MAX_MIP_LEVEL_SHIFT@GOTPAGE
Lloh9:
	ldr	x10, [x10, _RADEON_MAX_MIP_LEVEL_SHIFT@GOTPAGEOFF]
Lloh10:
	ldr	w10, [x10]
	asr	w11, w9, w10
	ldr	x9, [x25, #32]
	add	x10, x9, x8, lsl #6
	str	w11, [x10, #12]
	and	w11, w19, #0x1800000
	mov	w12, #16777216
	cmp	w11, w12
	b.ne	LBB0_14
; %bb.13:
	str	wzr, [x10, #16]
LBB0_14:
	and	w10, w19, #0x18000000
	mov	w11, #268435456
	cmp	w10, w11
	b.ne	LBB0_72
; %bb.15:
	add	x8, x9, x8, lsl #6
	str	wzr, [x8, #20]
	b	LBB0_72
LBB0_16:
	sub	w8, w24, #169
	lsr	w8, w8, #3
Lloh11:
	adrp	x9, _RADEON_TEX_USIZE_MASK@GOTPAGE
Lloh12:
	ldr	x9, [x9, _RADEON_TEX_USIZE_MASK@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	and	w9, w9, w19
	add	w9, w9, #1
	ldr	x10, [x25, #32]
	add	x8, x10, x8, lsl #6
	str	w9, [x8, #4]
Lloh14:
	adrp	x9, _RADEON_TEX_VSIZE_MASK@GOTPAGE
Lloh15:
	ldr	x9, [x9, _RADEON_TEX_VSIZE_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
	and	w9, w9, w19
Lloh17:
	adrp	x10, _RADEON_TEX_VSIZE_SHIFT@GOTPAGE
Lloh18:
	ldr	x10, [x10, _RADEON_TEX_VSIZE_SHIFT@GOTPAGEOFF]
Lloh19:
	ldr	w10, [x10]
	asr	w9, w9, w10
	add	w9, w9, #1
	str	w9, [x8, #8]
	b	LBB0_72
LBB0_17:
	sub	w8, w24, #172
	lsr	w8, w8, #3
	add	w9, w19, #32
	ldr	x10, [x25, #32]
	add	x8, x10, x8, lsl #6
	str	w9, [x8, #56]
	b	LBB0_72
LBB0_18:
	sub	w8, w24, #190
	lsr	w8, w8, #2
	ldr	x9, [x25, #32]
	add	x8, x9, x8, lsl #6
	ldr	x8, [x8, #40]
	and	w9, w19, #0xf
	mov	w10, #1
	lsl	w9, w10, w9
	ubfx	w11, w19, #4, #4
	lsl	w11, w10, w11
	stp	w9, w11, [x8, #4]
	dup.2s	v0, w19
Lloh20:
	adrp	x9, lCPI0_0@PAGE
Lloh21:
	ldr	d1, [x9, lCPI0_0@PAGEOFF]
	ushl.2s	v1, v0, v1
	movi.2s	v2, #15
	and.8b	v1, v1, v2
	movi.2s	v3, #1
	ushl.2s	v1, v3, v1
	stur	d1, [x8, #20]
Lloh22:
	adrp	x9, lCPI0_1@PAGE
Lloh23:
	ldr	d1, [x9, lCPI0_1@PAGEOFF]
	ushl.2s	v0, v0, v1
	and.8b	v0, v0, v2
	ushl.2s	v0, v3, v0
	stur	d0, [x8, #36]
	ubfx	w9, w19, #24, #4
	lsl	w9, w10, w9
	lsr	w11, w19, #28
	lsl	w11, w10, w11
	stp	w9, w11, [x8, #52]
	str	w10, [x25, #8]
	b	LBB0_73
LBB0_19:
	mov	x0, x22
	mov	x1, x21
	mov	x2, x20
	mov	x3, x24
	bl	_r100_reloc_pitch_offset
	mov	x23, x0
	cbnz	w0, LBB0_74
	b	LBB0_73
LBB0_20:
	sub	w8, w24, #187
	lsr	w8, w8, #2
	ldr	x9, [x25, #32]
	ldr	x9, [x9, #40]
LBB0_21:
	add	x8, x9, w8, uxtw #4
	str	w19, [x8]
	ldr	x9, [sp, #8]
	ldr	w10, [x9, #4]
	add	w10, w10, w19
	str	w10, [x26, w20, uxtw #2]
	ldr	w9, [x9, #8]
	str	w9, [x8, #12]
	b	LBB0_72
LBB0_22:
	sub	w8, w24, #160
	mov	w9, #43691
	movk	w9, #43690, lsl #16
	umull	x8, w8, w9
	lsr	x8, x8, #36
	ldr	w10, [x22]
Lloh24:
	adrp	x9, _RADEON_CS_KEEP_TILING_FLAGS@GOTPAGE
Lloh25:
	ldr	x9, [x9, _RADEON_CS_KEEP_TILING_FLAGS@GOTPAGEOFF]
Lloh26:
	ldr	w11, [x9]
	ldr	x9, [sp, #8]
	tst	w11, w10
	b.eq	LBB0_58
; %bb.23:
	ldr	w10, [x9, #4]
	b	LBB0_59
LBB0_24:
	str	wzr, [x11]
Lloh27:
	adrp	x11, _RADEON_TXFORMAT_WIDTH_SHIFT@GOTPAGE
Lloh28:
	ldr	x11, [x11, _RADEON_TXFORMAT_WIDTH_SHIFT@GOTPAGEOFF]
Lloh29:
	ldr	w11, [x11]
	asr	w11, w19, w11
Lloh30:
	adrp	x12, _RADEON_TXFORMAT_WIDTH_MASK@GOTPAGE
Lloh31:
	ldr	x12, [x12, _RADEON_TXFORMAT_WIDTH_MASK@GOTPAGEOFF]
Lloh32:
	ldr	w12, [x12]
	and	w11, w11, w12
	mov	w12, #1
	lsl	w11, w12, w11
	str	w11, [x10, #4]
Lloh33:
	adrp	x11, _RADEON_TXFORMAT_HEIGHT_SHIFT@GOTPAGE
Lloh34:
	ldr	x11, [x11, _RADEON_TXFORMAT_HEIGHT_SHIFT@GOTPAGEOFF]
Lloh35:
	ldr	w11, [x11]
	asr	w11, w19, w11
Lloh36:
	adrp	x13, _RADEON_TXFORMAT_HEIGHT_MASK@GOTPAGE
Lloh37:
	ldr	x13, [x13, _RADEON_TXFORMAT_HEIGHT_MASK@GOTPAGEOFF]
Lloh38:
	ldr	w13, [x13]
	and	w11, w11, w13
	lsl	w11, w12, w11
	str	w11, [x10, #8]
LBB0_25:
Lloh39:
	adrp	x10, _RADEON_TXFORMAT_CUBIC_MAP_ENABLE@GOTPAGE
Lloh40:
	ldr	x10, [x10, _RADEON_TXFORMAT_CUBIC_MAP_ENABLE@GOTPAGEOFF]
Lloh41:
	ldr	w10, [x10]
	tst	w10, w19
	b.eq	LBB0_27
; %bb.26:
	add	x10, x9, x8, lsl #6
	mov	w11, #2
	str	w11, [x10, #28]
LBB0_27:
Lloh42:
	adrp	x10, _RADEON_TXFORMAT_FORMAT_MASK@GOTPAGE
Lloh43:
	ldr	x10, [x10, _RADEON_TXFORMAT_FORMAT_MASK@GOTPAGEOFF]
Lloh44:
	ldr	w10, [x10]
	and	w10, w10, w19
	sub	w10, w10, #128
	cmp	w10, #18
	b.hi	LBB0_29
; %bb.28:
Lloh45:
	adrp	x11, l_switch.table.r100_packet0_check.4@PAGE
Lloh46:
	add	x11, x11, l_switch.table.r100_packet0_check.4@PAGEOFF
	ldr	w11, [x11, w10, sxtw #2]
Lloh47:
	adrp	x12, l_switch.table.r100_packet0_check.5@PAGE
Lloh48:
	add	x12, x12, l_switch.table.r100_packet0_check.5@PAGEOFF
	ldr	x10, [x12, w10, sxtw #3]
	add	x12, x9, x8, lsl #6
	str	w11, [x12, #32]
	ldr	x10, [x10]
	str	x10, [x12, #48]
LBB0_29:
	dup.2s	v0, w19
Lloh49:
	adrp	x10, lCPI0_1@PAGE
Lloh50:
	ldr	d1, [x10, lCPI0_1@PAGEOFF]
	ushl.2s	v0, v0, v1
	add	x8, x9, x8, lsl #6
	ldr	x8, [x8, #40]
	movi.2s	v1, #15
	and.8b	v0, v0, v1
	movi.2s	v1, #1
	ushl.2s	v0, v1, v0
	stur	d0, [x8, #68]
	b	LBB0_72
LBB0_30:
Lloh51:
	adrp	x0, l_.str.2@PAGE
Lloh52:
	add	x0, x0, l_.str.2@PAGEOFF
	mov	x1, x24
	mov	x2, x20
	bl	_pr_err
	b	LBB0_50
LBB0_31:
	mov	x0, x19
	bl	_r100_get_vtx_size
	str	w0, [x25, #40]
	b	LBB0_73
LBB0_32:
	str	w19, [x25, #24]
	b	LBB0_73
LBB0_33:
	ubfx	w8, w19, #16, #11
	str	w8, [x25, #12]
	b	LBB0_76
LBB0_34:
	and	w8, w19, #0xf
	cmp	w8, #11
	b.hi	LBB0_40
; %bb.35:
	mov	w9, #2621
	lsr	w9, w9, w8
	tbz	w9, #0, LBB0_40
; %bb.36:
Lloh53:
	adrp	x9, l_switch.table.r100_packet0_check.3@PAGE
Lloh54:
	add	x9, x9, l_switch.table.r100_packet0_check.3@PAGEOFF
	ldr	w8, [x9, w8, uxtw #2]
	str	w8, [x25, #52]
	b	LBB0_40
LBB0_37:
	add	x1, sp, #8
	mov	x0, x22
	mov	w2, #0
	bl	_radeon_cs_packet_next_reloc
	cbz	w0, LBB0_60
; %bb.38:
	mov	x23, x0
	mov	w8, #152
	b	LBB0_56
LBB0_39:
Lloh55:
	adrp	x8, _RADEON_DEPTHPITCH_MASK@GOTPAGE
Lloh56:
	ldr	x8, [x8, _RADEON_DEPTHPITCH_MASK@GOTPAGEOFF]
Lloh57:
	ldr	w8, [x8]
	and	w8, w8, w19
	str	w8, [x25, #48]
LBB0_40:
	mov	w8, #1
	str	w8, [x25]
	b	LBB0_73
LBB0_41:
	add	x1, sp, #8
	mov	x0, x22
	mov	w2, #0
	bl	_radeon_cs_packet_next_reloc
	cbz	w0, LBB0_61
; %bb.42:
	mov	x23, x0
	mov	w8, #154
	b	LBB0_56
LBB0_43:
	add	x1, sp, #8
	mov	x0, x22
	mov	w2, #0
	bl	_radeon_cs_packet_next_reloc
	cbz	w0, LBB0_62
; %bb.44:
	mov	x23, x0
	mov	w8, #155
	b	LBB0_56
LBB0_45:
	add	x1, sp, #8
	mov	x0, x22
	mov	w2, #0
	bl	_radeon_cs_packet_next_reloc
	cbz	w0, LBB0_65
; %bb.46:
	mov	x23, x0
	mov	w8, #156
	b	LBB0_56
LBB0_47:
Lloh58:
	adrp	x8, _RADEON_RB3D_COLOR_FORMAT_SHIFT@GOTPAGE
Lloh59:
	ldr	x8, [x8, _RADEON_RB3D_COLOR_FORMAT_SHIFT@GOTPAGEOFF]
Lloh60:
	ldr	w8, [x8]
	asr	w8, w19, w8
	and	x1, x8, #0x1f
	sub	x8, x1, #3
	cmp	w8, #13
	b.hs	LBB0_49
; %bb.48:
	mov	w9, #4987
	lsr	w9, w9, w8
	tbnz	w9, #0, LBB0_75
LBB0_49:
Lloh61:
	adrp	x0, l_.str.1@PAGE
Lloh62:
	add	x0, x0, l_.str.1@PAGEOFF
                                        ; kill: def $w1 killed $w1 killed $x1
	bl	_DRM_ERROR
LBB0_50:
Lloh63:
	adrp	x8, _EINVAL@GOTPAGE
Lloh64:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh65:
	ldr	w8, [x8]
	neg	w23, w8
	b	LBB0_74
LBB0_51:
	ldr	w8, [x25, #20]
	cmp	w8, #1
	b.lt	LBB0_72
; %bb.52:
	asr	w9, w19, #4
	ldr	x11, [x25, #32]
	cmp	w8, #4
	b.hs	LBB0_67
; %bb.53:
	mov	x10, #0
	b	LBB0_70
LBB0_54:
	mov	x0, x22
	bl	_r100_cs_packet_parse_vline
	cbz	w0, LBB0_73
; %bb.55:
	mov	x23, x0
	mov	w8, #193
LBB0_56:
	str	x8, [sp]
LBB0_57:
Lloh66:
	adrp	x0, l_.str@PAGE
Lloh67:
	add	x0, x0, l_.str@PAGEOFF
	mov	x1, x20
	bl	_DRM_ERROR
	mov	x0, x22
	mov	x1, x21
	bl	_radeon_cs_dump_packet
	b	LBB0_74
LBB0_58:
Lloh68:
	adrp	x10, _RADEON_TILING_MACRO@GOTPAGE
Lloh69:
	ldr	x10, [x10, _RADEON_TILING_MACRO@GOTPAGEOFF]
Lloh70:
	ldr	w10, [x10]
Lloh71:
	adrp	x11, _RADEON_TXO_MACRO_TILE@GOTPAGE
Lloh72:
	ldr	x11, [x11, _RADEON_TXO_MACRO_TILE@GOTPAGEOFF]
Lloh73:
	ldr	w11, [x11]
	and	w12, w19, #0xffffffe3
	ldp	w13, w19, [x9]
	tst	w10, w13
	csel	w10, wzr, w11, eq
Lloh74:
	adrp	x11, _RADEON_TILING_MICRO@GOTPAGE
Lloh75:
	ldr	x11, [x11, _RADEON_TILING_MICRO@GOTPAGEOFF]
Lloh76:
	ldr	w11, [x11]
	tst	w11, w13
Lloh77:
	adrp	x11, _RADEON_TXO_MICRO_TILE_X2@GOTPAGE
Lloh78:
	ldr	x11, [x11, _RADEON_TXO_MICRO_TILE_X2@GOTPAGEOFF]
Lloh79:
	ldr	w11, [x11]
	csel	w11, wzr, w11, eq
	orr	w10, w10, w12
	orr	w10, w10, w11
LBB0_59:
	add	w10, w10, w19
	str	w10, [x26, w20, uxtw #2]
	ldr	w9, [x9, #8]
	ldr	x10, [x25, #32]
	mov	w8, w8
	add	x8, x10, x8, lsl #6
	str	w9, [x8, #60]
	b	LBB0_72
LBB0_60:
	ldr	x8, [sp, #8]
	ldr	w8, [x8, #4]
	b	LBB0_66
LBB0_61:
	ldr	x8, [sp, #8]
	ldp	w8, w9, [x8, #4]
	str	w9, [x25, #56]
	str	w19, [x25, #44]
	mov	w9, #1
	str	w9, [x25]
	b	LBB0_66
LBB0_62:
	ldr	w9, [x22]
Lloh80:
	adrp	x8, _RADEON_CS_KEEP_TILING_FLAGS@GOTPAGE
Lloh81:
	ldr	x8, [x8, _RADEON_CS_KEEP_TILING_FLAGS@GOTPAGEOFF]
Lloh82:
	ldr	w10, [x8]
	mov	x8, x19
	tst	w10, w9
	b.ne	LBB0_64
; %bb.63:
	ldr	x8, [sp, #8]
Lloh83:
	adrp	x9, _RADEON_TILING_MACRO@GOTPAGE
Lloh84:
	ldr	x9, [x9, _RADEON_TILING_MACRO@GOTPAGEOFF]
	ldr	w8, [x8]
Lloh85:
	ldr	w9, [x9]
Lloh86:
	adrp	x10, _RADEON_COLOR_TILE_ENABLE@GOTPAGE
Lloh87:
	ldr	x10, [x10, _RADEON_COLOR_TILE_ENABLE@GOTPAGEOFF]
Lloh88:
	ldr	w10, [x10]
	tst	w9, w8
	csel	w9, wzr, w10, eq
Lloh89:
	adrp	x10, _RADEON_TILING_MICRO@GOTPAGE
Lloh90:
	ldr	x10, [x10, _RADEON_TILING_MICRO@GOTPAGEOFF]
Lloh91:
	ldr	w10, [x10]
Lloh92:
	adrp	x11, _RADEON_COLOR_MICROTILE_ENABLE@GOTPAGE
Lloh93:
	ldr	x11, [x11, _RADEON_COLOR_MICROTILE_ENABLE@GOTPAGEOFF]
Lloh94:
	ldr	w11, [x11]
	tst	w10, w8
	csel	w8, wzr, w11, eq
	and	w10, w19, #0xfff8ffff
	orr	w9, w9, w10
	orr	w8, w9, w8
LBB0_64:
	str	w8, [x26, w20, uxtw #2]
Lloh95:
	adrp	x8, _RADEON_COLORPITCH_MASK@GOTPAGE
Lloh96:
	ldr	x8, [x8, _RADEON_COLORPITCH_MASK@GOTPAGEOFF]
Lloh97:
	ldr	w8, [x8]
	and	w8, w8, w19
	ldr	x9, [x25, #64]
	str	w8, [x9, #4]
	mov	w8, #1
	str	w8, [x25, #4]
	b	LBB0_73
LBB0_65:
	ldr	x8, [sp, #8]
	ldr	x9, [x25, #64]
	ldp	w8, w10, [x8, #4]
	str	w10, [x9, #12]
	str	w19, [x9]
	mov	w9, #1
	str	w9, [x25, #4]
LBB0_66:
	add	w8, w8, w19
	str	w8, [x26, w20, uxtw #2]
	b	LBB0_73
LBB0_67:
	mov	x12, #0
	and	x10, x8, #0xfffffffc
	add	x13, x11, #128
LBB0_68:                                ; =>This Inner Loop Header: Depth=1
	add	w14, w12, #1
	add	w15, w12, #2
	add	w16, w12, #3
	lsr	w17, w9, w12
	lsr	w14, w9, w14
	lsr	w15, w9, w15
	lsr	w16, w9, w16
	and	w17, w17, #0x1
	and	w14, w14, #0x1
	and	w15, w15, #0x1
	and	w16, w16, #0x1
	stur	w17, [x13, #-128]
	stur	w14, [x13, #-64]
	str	w15, [x13]
	str	w16, [x13, #64]
	add	x12, x12, #4
	add	x13, x13, #256
	cmp	x10, x12
	b.ne	LBB0_68
; %bb.69:
	cmp	x10, x8
	b.eq	LBB0_72
LBB0_70:
	add	x11, x11, x10, lsl #6
LBB0_71:                                ; =>This Inner Loop Header: Depth=1
	lsr	w12, w9, w10
	and	w12, w12, #0x1
	str	w12, [x11], #64
	add	x10, x10, #1
	cmp	x8, x10
	b.ne	LBB0_71
LBB0_72:
	mov	w8, #1
	str	w8, [x25, #8]
LBB0_73:
	mov	w23, #0
LBB0_74:
	mov	x0, x23
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_75:
Lloh98:
	adrp	x9, l_switch.table.r100_packet0_check@PAGE
Lloh99:
	add	x9, x9, l_switch.table.r100_packet0_check@PAGEOFF
	ldr	w8, [x9, x8, lsl #2]
	ldr	x9, [x25, #64]
	str	w8, [x9, #8]
Lloh100:
	adrp	x8, _RADEON_Z_ENABLE@GOTPAGE
Lloh101:
	ldr	x8, [x8, _RADEON_Z_ENABLE@GOTPAGEOFF]
Lloh102:
	ldr	w8, [x8]
	tst	w8, w19
	cset	w8, ne
	str	w8, [x25, #16]
LBB0_76:
	movi.2s	v0, #1
	str	d0, [x25]
	b	LBB0_73
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdr	Lloh22, Lloh23
	.loh AdrpAdrp	Lloh20, Lloh22
	.loh AdrpLdr	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpAdd	Lloh47, Lloh48
	.loh AdrpAdd	Lloh45, Lloh46
	.loh AdrpLdr	Lloh49, Lloh50
	.loh AdrpAdd	Lloh51, Lloh52
	.loh AdrpAdd	Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpAdd	Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpAdd	Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpAdd	Lloh98, Lloh99
	.cfi_endproc
	.section	__TEXT,__const
	.p2align	1
lJTI0_0:
	.short	(LBB0_19-LBB0_2)>>2
	.short	(LBB0_31-LBB0_2)>>2
	.short	(LBB0_32-LBB0_2)>>2
	.short	(LBB0_33-LBB0_2)>>2
	.short	(LBB0_34-LBB0_2)>>2
	.short	(LBB0_37-LBB0_2)>>2
	.short	(LBB0_39-LBB0_2)>>2
	.short	(LBB0_41-LBB0_2)>>2
	.short	(LBB0_43-LBB0_2)>>2
	.short	(LBB0_45-LBB0_2)>>2
	.short	(LBB0_47-LBB0_2)>>2
	.short	(LBB0_8-LBB0_2)>>2
	.short	(LBB0_8-LBB0_2)>>2
	.short	(LBB0_8-LBB0_2)>>2
	.short	(LBB0_10-LBB0_2)>>2
	.short	(LBB0_10-LBB0_2)>>2
	.short	(LBB0_10-LBB0_2)>>2
	.short	(LBB0_12-LBB0_2)>>2
	.short	(LBB0_12-LBB0_2)>>2
	.short	(LBB0_12-LBB0_2)>>2
	.short	(LBB0_16-LBB0_2)>>2
	.short	(LBB0_16-LBB0_2)>>2
	.short	(LBB0_16-LBB0_2)>>2
	.short	(LBB0_17-LBB0_2)>>2
	.short	(LBB0_17-LBB0_2)>>2
	.short	(LBB0_17-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_4-LBB0_2)>>2
	.short	(LBB0_4-LBB0_2)>>2
	.short	(LBB0_4-LBB0_2)>>2
	.short	(LBB0_4-LBB0_2)>>2
	.short	(LBB0_4-LBB0_2)>>2
	.short	(LBB0_6-LBB0_2)>>2
	.short	(LBB0_6-LBB0_2)>>2
	.short	(LBB0_6-LBB0_2)>>2
	.short	(LBB0_6-LBB0_2)>>2
	.short	(LBB0_6-LBB0_2)>>2
	.short	(LBB0_18-LBB0_2)>>2
	.short	(LBB0_18-LBB0_2)>>2
	.short	(LBB0_18-LBB0_2)>>2
	.short	(LBB0_51-LBB0_2)>>2
	.short	(LBB0_19-LBB0_2)>>2
	.short	(LBB0_54-LBB0_2)>>2
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"No reloc for ib[%d]=0x%04X\n"

	.comm	_RADEON_CS_KEEP_TILING_FLAGS,4,2 ; @RADEON_CS_KEEP_TILING_FLAGS
	.comm	_RADEON_TILING_MACRO,4,2        ; @RADEON_TILING_MACRO
	.comm	_RADEON_TXO_MACRO_TILE,4,2      ; @RADEON_TXO_MACRO_TILE
	.comm	_RADEON_TILING_MICRO,4,2        ; @RADEON_TILING_MICRO
	.comm	_RADEON_TXO_MICRO_TILE_X2,4,2   ; @RADEON_TXO_MICRO_TILE_X2
	.comm	_RADEON_COLOR_TILE_ENABLE,4,2   ; @RADEON_COLOR_TILE_ENABLE
	.comm	_RADEON_COLOR_MICROTILE_ENABLE,4,2 ; @RADEON_COLOR_MICROTILE_ENABLE
	.comm	_RADEON_COLORPITCH_MASK,4,2     ; @RADEON_COLORPITCH_MASK
	.comm	_RADEON_DEPTHPITCH_MASK,4,2     ; @RADEON_DEPTHPITCH_MASK
	.comm	_RADEON_RB3D_COLOR_FORMAT_SHIFT,4,2 ; @RADEON_RB3D_COLOR_FORMAT_SHIFT
l_.str.1:                               ; @.str.1
	.asciz	"Invalid color buffer format (%d) !\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_RADEON_Z_ENABLE,4,2            ; @RADEON_Z_ENABLE
	.comm	_RADEON_TEX_USIZE_MASK,4,2      ; @RADEON_TEX_USIZE_MASK
	.comm	_RADEON_TEX_VSIZE_MASK,4,2      ; @RADEON_TEX_VSIZE_MASK
	.comm	_RADEON_TEX_VSIZE_SHIFT,4,2     ; @RADEON_TEX_VSIZE_SHIFT
	.comm	_RADEON_MAX_MIP_LEVEL_MASK,4,2  ; @RADEON_MAX_MIP_LEVEL_MASK
	.comm	_RADEON_MAX_MIP_LEVEL_SHIFT,4,2 ; @RADEON_MAX_MIP_LEVEL_SHIFT
	.comm	_RADEON_TXFORMAT_NON_POWER2,4,2 ; @RADEON_TXFORMAT_NON_POWER2
	.comm	_RADEON_TXFORMAT_WIDTH_SHIFT,4,2 ; @RADEON_TXFORMAT_WIDTH_SHIFT
	.comm	_RADEON_TXFORMAT_WIDTH_MASK,4,2 ; @RADEON_TXFORMAT_WIDTH_MASK
	.comm	_RADEON_TXFORMAT_HEIGHT_SHIFT,4,2 ; @RADEON_TXFORMAT_HEIGHT_SHIFT
	.comm	_RADEON_TXFORMAT_HEIGHT_MASK,4,2 ; @RADEON_TXFORMAT_HEIGHT_MASK
	.comm	_RADEON_TXFORMAT_CUBIC_MAP_ENABLE,4,2 ; @RADEON_TXFORMAT_CUBIC_MAP_ENABLE
	.comm	_RADEON_TXFORMAT_FORMAT_MASK,4,2 ; @RADEON_TXFORMAT_FORMAT_MASK
	.comm	_R100_TRACK_COMP_NONE,8,3       ; @R100_TRACK_COMP_NONE
	.comm	_R100_TRACK_COMP_DXT1,8,3       ; @R100_TRACK_COMP_DXT1
	.comm	_R100_TRACK_COMP_DXT35,8,3      ; @R100_TRACK_COMP_DXT35
l_.str.2:                               ; @.str.2
	.asciz	"Forbidden register 0x%04X in cs at %d\n"

	.no_dead_strip	_r100_packet0_check
	.section	__TEXT,__const
	.p2align	2                               ; @switch.table.r100_packet0_check
l_switch.table.r100_packet0_check:
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	4                               ; 0x4
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	2                               ; 0x2

	.p2align	2                               ; @switch.table.r100_packet0_check.3
l_switch.table.r100_packet0_check.3:
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	4                               ; 0x4
	.long	4                               ; 0x4
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	4                               ; 0x4

	.p2align	2                               ; @switch.table.r100_packet0_check.4
l_switch.table.r100_packet0_check.4:
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	2                               ; 0x2

	.section	__DATA,__const
	.p2align	3                               ; @switch.table.r100_packet0_check.5
l_switch.table.r100_packet0_check.5:
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_DXT35
	.quad	_R100_TRACK_COMP_DXT35
	.quad	_R100_TRACK_COMP_DXT1
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE

.subsections_via_symbols
