	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function stm32_adc_core_switches_supply_dis
_stm32_adc_core_switches_supply_dis:    ## @stm32_adc_core_switches_supply_dis
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	cmpl	$2699999, (%rdi)                ## imm = 0x2932DF
	jg	LBB0_6
## %bb.1:
	movq	%rdi, %rbx
	movq	24(%rdi), %rdi
	testq	%rdi, %rdi
	je	LBB0_5
## %bb.2:
	cmpl	$2700001, 4(%rbx)               ## imm = 0x2932E1
	jl	LBB0_5
## %bb.3:
	movq	_STM32MP1_SYSCFG_PMCCLRR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_STM32MP1_SYSCFG_ANASWVDD_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_regmap_write
	movq	16(%rbx), %rdi
	jmp	LBB0_4
LBB0_5:
	movq	8(%rbx), %rdi
	testq	%rdi, %rdi
	je	LBB0_6
LBB0_4:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_regulator_disable              ## TAILCALL
LBB0_6:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_STM32MP1_SYSCFG_PMCCLRR,4,2    ## @STM32MP1_SYSCFG_PMCCLRR
	.comm	_STM32MP1_SYSCFG_ANASWVDD_MASK,4,2 ## @STM32MP1_SYSCFG_ANASWVDD_MASK
	.no_dead_strip	_stm32_adc_core_switches_supply_dis
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function stm32_adc_core_switches_supply_dis
_stm32_adc_core_switches_supply_dis:    ; @stm32_adc_core_switches_supply_dis
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	w8, #13024
	movk	w8, #41, lsl #16
	ldr	w9, [x0]
	cmp	w9, w8
	b.ge	LBB0_6
; %bb.1:
	mov	x19, x0
	ldr	x0, [x0, #24]
	cbz	x0, LBB0_4
; %bb.2:
	ldr	w9, [x19, #4]
	cmp	w9, w8
	b.le	LBB0_4
; %bb.3:
Lloh0:
	adrp	x8, _STM32MP1_SYSCFG_PMCCLRR@GOTPAGE
Lloh1:
	ldr	x8, [x8, _STM32MP1_SYSCFG_PMCCLRR@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
Lloh3:
	adrp	x8, _STM32MP1_SYSCFG_ANASWVDD_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _STM32MP1_SYSCFG_ANASWVDD_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	bl	_regmap_write
	ldr	x0, [x19, #16]
	b	LBB0_5
LBB0_4:
	ldr	x0, [x19, #8]
	cbz	x0, LBB0_6
LBB0_5:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_regulator_disable
LBB0_6:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_STM32MP1_SYSCFG_PMCCLRR,4,2    ; @STM32MP1_SYSCFG_PMCCLRR
	.comm	_STM32MP1_SYSCFG_ANASWVDD_MASK,4,2 ; @STM32MP1_SYSCFG_ANASWVDD_MASK
	.no_dead_strip	_stm32_adc_core_switches_supply_dis
.subsections_via_symbols
