	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_legacy_set_clock_gating ## -- Begin function radeon_legacy_set_clock_gating
	.p2align	4, 0x90
_radeon_legacy_set_clock_gating:        ## @radeon_legacy_set_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_RADEON_SINGLE_CRTC@GOTPCREL(%rip), %rbx
	movl	(%rbx), %eax
	andl	(%rdi), %eax
	testl	%esi, %esi
	je	LBB0_41
## %bb.1:
	testl	%eax, %eax
	je	LBB0_5
## %bb.2:
	movq	_RADEON_SCLK_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32_PLL
	movl	%eax, %ebx
	movq	_RADEON_CONFIG_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_RADEON_CFG_ATI_REV_ID_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_RADEON_CFG_ATI_REV_A13@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jle	LBB0_4
## %bb.3:
	movq	_RADEON_SCLK_FORCE_CP@GOTPCREL(%rip), %rax
	movq	_RADEON_SCLK_FORCE_RB@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	notl	%ecx
	andl	%ecx, %ebx
LBB0_4:
	movq	_RADEON_SCLK_FORCE_HDP@GOTPCREL(%rip), %rax
	movq	_RADEON_SCLK_FORCE_DISP1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movq	_RADEON_SCLK_FORCE_TOP@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_RADEON_SCLK_FORCE_SE@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_RADEON_SCLK_FORCE_IDCT@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_RADEON_SCLK_FORCE_RE@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_RADEON_SCLK_FORCE_PB@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_RADEON_SCLK_FORCE_TAM@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_RADEON_SCLK_FORCE_TDM@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	notl	%esi
	andl	%ebx, %esi
	movl	(%r14), %edi
	jmp	LBB0_19
LBB0_41:
	testl	%eax, %eax
	je	LBB0_44
## %bb.42:
	movq	_RADEON_SCLK_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_SCLK_FORCE_CP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_HDP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_DISP1@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_TOP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_E2@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_SE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_IDCT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_VIP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_RE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_PB@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_TAM@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_TDM@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_RB@GOTPCREL(%rip), %rcx
	jmp	LBB0_43
LBB0_5:
	movq	%r14, %rdi
	callq	_ASIC_IS_R300
	testq	%rax, %rax
	je	LBB0_22
## %bb.6:
	movq	8(%r14), %rax
	movq	_CHIP_RS400@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_8
## %bb.7:
	movq	_CHIP_RS480@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_8
## %bb.9:
	movq	_CHIP_RV350@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_10
## %bb.20:
	movq	_RADEON_SCLK_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_R300_SCLK_FORCE_VAP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_RADEON_SCLK_FORCE_CP@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	(%rbx), %edi
	callq	_WREG32_PLL
	movl	$15, %edi
	callq	_mdelay
	movq	_R300_SCLK_CNTL2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_R300_SCLK_FORCE_TCL@GOTPCREL(%rip), %rcx
	movq	_R300_SCLK_FORCE_GA@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	movq	_R300_SCLK_FORCE_CBA@GOTPCREL(%rip), %rcx
	jmp	LBB0_21
LBB0_44:
	movq	8(%r14), %rax
	movq	_CHIP_RS400@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_46
## %bb.45:
	movq	_CHIP_RS480@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_46
## %bb.48:
	movq	_CHIP_RV350@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_49
## %bb.50:
	movq	_RADEON_SCLK_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32_PLL
	movq	_RADEON_SCLK_FORCE_CP@GOTPCREL(%rip), %rcx
	movq	_RADEON_SCLK_FORCE_E2@GOTPCREL(%rip), %rdx
	movq	_RADEON_SCLK_FORCE_SE@GOTPCREL(%rip), %rsi
	orl	(%rcx), %eax
	orl	(%rdx), %eax
	orl	(%rsi), %eax
	movl	(%rbx), %ecx
	testl	%ecx, (%r14)
	je	LBB0_52
## %bb.51:
	movq	_RADEON_SCLK_FORCE_RB@GOTPCREL(%rip), %rcx
	movq	_RADEON_SCLK_FORCE_TDM@GOTPCREL(%rip), %rdx
	movq	_RADEON_SCLK_FORCE_TAM@GOTPCREL(%rip), %rsi
	movq	_RADEON_SCLK_FORCE_PB@GOTPCREL(%rip), %rdi
	movq	_RADEON_SCLK_FORCE_RE@GOTPCREL(%rip), %rbx
	movq	_RADEON_SCLK_FORCE_VIP@GOTPCREL(%rip), %r8
	movq	_RADEON_SCLK_FORCE_IDCT@GOTPCREL(%rip), %r9
	movq	_RADEON_SCLK_FORCE_TOP@GOTPCREL(%rip), %r10
	movq	_RADEON_SCLK_FORCE_DISP1@GOTPCREL(%rip), %r11
	movq	_RADEON_SCLK_FORCE_DISP2@GOTPCREL(%rip), %r12
	movq	_RADEON_SCLK_FORCE_HDP@GOTPCREL(%rip), %r13
	orl	(%rcx), %eax
	orl	(%rdx), %eax
	orl	(%rsi), %eax
	orl	(%rdi), %eax
	orl	(%rbx), %eax
	orl	(%r8), %eax
	orl	(%r9), %eax
	orl	(%r10), %eax
	orl	(%r11), %eax
	orl	(%r12), %eax
	orl	(%r13), %eax
	jmp	LBB0_55
LBB0_22:
	movq	_RADEON_CLK_PWRMGT_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_ACTIVE_HILO_LAT_MASK@GOTPCREL(%rip), %rcx
	movq	_RADEON_DISP_DYN_STOP_LAT_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	movq	_RADEON_DYN_STOP_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_RADEON_ENGIN_DYNCLK_MODE@GOTPCREL(%rip), %rax
	movq	_RADEON_ACTIVE_HILO_LAT_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	orl	(%rax), %esi
	btsl	%ecx, %esi
	movl	(%rbx), %edi
	callq	_WREG32_PLL
	movl	$15, %edi
	callq	_mdelay
	movq	_RADEON_CLK_PIN_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_SCLK_DYN_START_CNTL@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PLL
	movl	$15, %edi
	callq	_mdelay
	movq	_RADEON_SCLK_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_RREG32_PLL
	movq	_RADEON_SCLK_FORCEON_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movq	8(%r14), %rax
	movq	_CHIP_RV250@GOTPCREL(%rip), %r15
	cmpq	(%r15), %rax
	jne	LBB0_25
## %bb.23:
	movq	_RADEON_CONFIG_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_RADEON_CFG_ATI_REV_ID_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_RADEON_CFG_ATI_REV_A13@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jl	LBB0_27
## %bb.24:
	movq	8(%r14), %rax
LBB0_25:
	movq	_CHIP_RV100@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_28
## %bb.26:
	movq	_RADEON_CONFIG_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_RADEON_CFG_ATI_REV_ID_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_RADEON_CFG_ATI_REV_A13@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jg	LBB0_28
LBB0_27:
	movq	_RADEON_SCLK_FORCE_CP@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_RADEON_SCLK_FORCE_VIP@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
LBB0_28:
	movl	(%r12), %edi
	movl	%ebx, %esi
	callq	_WREG32_PLL
	movq	8(%r14), %rax
	movq	_CHIP_RV200@GOTPCREL(%rip), %r12
	movq	(%r12), %rcx
	cmpq	%rcx, %rax
	je	LBB0_31
## %bb.29:
	movq	(%r15), %rdx
	cmpq	%rdx, %rax
	je	LBB0_31
## %bb.30:
	movq	_CHIP_RV280@GOTPCREL(%rip), %rsi
	cmpq	(%rsi), %rax
	jne	LBB0_36
LBB0_31:
	movq	_RADEON_SCLK_MORE_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_RREG32_PLL
	movq	_RADEON_SCLK_MORE_FORCEON@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movq	8(%r14), %rax
	cmpq	(%r12), %rax
	je	LBB0_33
## %bb.32:
	cmpq	(%r15), %rax
	jne	LBB0_35
LBB0_33:
	movq	_RADEON_CONFIG_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_RADEON_CFG_ATI_REV_ID_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_RADEON_CFG_ATI_REV_A13@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jge	LBB0_35
## %bb.34:
	movq	_RADEON_SCLK_MORE_FORCEON@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
LBB0_35:
	movl	(%r13), %edi
	movl	%ebx, %esi
	callq	_WREG32_PLL
	movl	$15, %edi
	callq	_mdelay
	movq	8(%r14), %rax
	movq	(%r12), %rcx
	movq	(%r15), %rdx
LBB0_36:
	cmpq	%rcx, %rax
	je	LBB0_38
## %bb.37:
	cmpq	%rdx, %rax
	jne	LBB0_40
LBB0_38:
	movq	_RADEON_CONFIG_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_RADEON_CFG_ATI_REV_ID_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_RADEON_CFG_ATI_REV_A13@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jge	LBB0_40
## %bb.39:
	movq	_RADEON_PLL_PWRMGT_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_TCL_BYPASS_DISABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PLL
LBB0_40:
	movl	$15, %edi
	callq	_mdelay
	movq	_RADEON_PIXCLKS_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_PIX2CLK_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	movq	_RADEON_PIX2CLK_DAC_ALWAYS_ONb@GOTPCREL(%rip), %rdx
	movq	_RADEON_PIXCLK_BLEND_ALWAYS_ONb@GOTPCREL(%rip), %rsi
	movq	_RADEON_PIXCLK_GV_ALWAYS_ONb@GOTPCREL(%rip), %rdi
	movq	_RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb@GOTPCREL(%rip), %r8
	movq	_RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPCREL(%rip), %r9
	orl	(%rcx), %eax
	orl	(%rdx), %eax
	orl	(%rsi), %eax
	orl	(%rdi), %eax
	orl	(%r8), %eax
	orl	(%r9), %eax
	movq	_RADEON_PIXCLK_TMDS_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PLL
	movl	$15, %edi
	callq	_mdelay
	movq	_RADEON_VCLK_ECP_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_PIXCLK_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_PIXCLK_DAC_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PLL
	movl	$15, %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_mdelay                         ## TAILCALL
LBB0_8:
	movq	_RADEON_SCLK_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_SCLK_FORCE_DISP2@GOTPCREL(%rip), %rdx
	movq	_RADEON_SCLK_FORCE_CP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rdx), %ecx
	movq	_RADEON_SCLK_FORCE_HDP@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_RADEON_SCLK_FORCE_DISP1@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_RADEON_SCLK_FORCE_TOP@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	%edx, %ecx
	movq	_RADEON_SCLK_FORCE_E2@GOTPCREL(%rip), %rsi
	orl	(%rsi), %ecx
	movq	_R300_SCLK_FORCE_VAP@GOTPCREL(%rip), %rsi
	orl	(%rsi), %ecx
	movq	_RADEON_SCLK_FORCE_IDCT@GOTPCREL(%rip), %rsi
	orl	(%rsi), %ecx
	movq	_RADEON_SCLK_FORCE_VIP@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	orl	%esi, %ecx
	movq	_R300_SCLK_FORCE_SR@GOTPCREL(%rip), %rdi
	orl	(%rdi), %ecx
	movq	_R300_SCLK_FORCE_PX@GOTPCREL(%rip), %rdi
	orl	(%rdi), %ecx
	movq	_R300_SCLK_FORCE_TX@GOTPCREL(%rip), %rdi
	orl	(%rdi), %ecx
	movq	_R300_SCLK_FORCE_US@GOTPCREL(%rip), %rdi
	orl	(%rdi), %ecx
	movq	_RADEON_SCLK_FORCE_TV_SCLK@GOTPCREL(%rip), %rdi
	orl	(%rdi), %ecx
	movq	_R300_SCLK_FORCE_SU@GOTPCREL(%rip), %rdi
	orl	(%rdi), %ecx
	movq	_RADEON_SCLK_FORCE_OV0@GOTPCREL(%rip), %rdi
	orl	(%rdi), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movq	_RADEON_DYN_STOP_LAT_MASK@GOTPCREL(%rip), %rax
	orl	%edx, %esi
	orl	(%rax), %esi
	orl	%ecx, %esi
	movl	(%rbx), %edi
	callq	_WREG32_PLL
	movq	_RADEON_SCLK_MORE_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_SCLK_MORE_FORCEON@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_RADEON_SCLK_MORE_MAX_DYN_STOP_LAT@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	(%rbx), %edi
	callq	_WREG32_PLL
	movq	_RADEON_VCLK_ECP_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_PIXCLK_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_PIXCLK_DAC_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PLL
	movq	_RADEON_PIXCLKS_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_PIX2CLK_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_PIX2CLK_DAC_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_DVOCLK_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_PIXCLK_BLEND_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_PIXCLK_GV_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_PIXCLK_DVO_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_PIXCLK_TMDS_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_PIXCLK_TRANS_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_PIXCLK_TVO_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_P2G2CLK_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_P2G2CLK_DAC_ALWAYS_ONb@GOTPCREL(%rip), %rcx
LBB0_43:
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	jmp	LBB0_19
LBB0_46:
	movq	_RADEON_SCLK_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_SCLK_FORCE_DISP2@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_CP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_HDP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_DISP1@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_TOP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_E2@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_SCLK_FORCE_VAP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_IDCT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_VIP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_SCLK_FORCE_SR@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_SCLK_FORCE_PX@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_SCLK_FORCE_TX@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_SCLK_FORCE_US@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_TV_SCLK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_SCLK_FORCE_SU@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_OV0@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PLL
	movq	_RADEON_SCLK_MORE_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_SCLK_MORE_FORCEON@GOTPCREL(%rip), %rcx
	jmp	LBB0_47
LBB0_10:
	movq	_R300_SCLK_CNTL2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_R300_SCLK_FORCE_TCL@GOTPCREL(%rip), %rcx
	movq	_R300_SCLK_FORCE_GA@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	movq	_R300_SCLK_FORCE_CBA@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	_R300_SCLK_TCL_MAX_DYN_STOP_LAT@GOTPCREL(%rip), %rax
	movq	_R300_SCLK_GA_MAX_DYN_STOP_LAT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	orl	%edx, %esi
	movq	_R300_SCLK_CBA_MAX_DYN_STOP_LAT@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	(%rbx), %edi
	callq	_WREG32_PLL
	movq	_RADEON_SCLK_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_SCLK_FORCE_DISP2@GOTPCREL(%rip), %rcx
	movq	_RADEON_SCLK_FORCE_CP@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	movq	_RADEON_SCLK_FORCE_HDP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_RADEON_SCLK_FORCE_DISP1@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_RADEON_SCLK_FORCE_TOP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_RADEON_SCLK_FORCE_E2@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_R300_SCLK_FORCE_VAP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_RADEON_SCLK_FORCE_IDCT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_RADEON_SCLK_FORCE_VIP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_R300_SCLK_FORCE_SR@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_R300_SCLK_FORCE_PX@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_R300_SCLK_FORCE_TX@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_R300_SCLK_FORCE_US@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_RADEON_SCLK_FORCE_TV_SCLK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_R300_SCLK_FORCE_SU@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_RADEON_SCLK_FORCE_OV0@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_RADEON_DYN_STOP_LAT_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	(%rbx), %edi
	callq	_WREG32_PLL
	movq	_RADEON_SCLK_MORE_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_SCLK_MORE_FORCEON@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_RADEON_SCLK_MORE_MAX_DYN_STOP_LAT@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	(%rbx), %edi
	callq	_WREG32_PLL
	movq	_RADEON_VCLK_ECP_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_PIXCLK_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_PIXCLK_DAC_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PLL
	movq	_RADEON_PIXCLKS_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_PIX2CLK_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_PIX2CLK_DAC_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_DVOCLK_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_PIXCLK_BLEND_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_PIXCLK_GV_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_PIXCLK_DVO_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_PIXCLK_TMDS_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_PIXCLK_TRANS_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_PIXCLK_TVO_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_P2G2CLK_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_P2G2CLK_DAC_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PLL
	movq	_RADEON_MCLK_MISC@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_MC_MCLK_DYN_ENABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_IO_MCLK_DYN_ENABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PLL
	movq	_RADEON_MCLK_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32_PLL
	movq	_RADEON_FORCEON_MCLKA@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_FORCEON_MCLKB@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_FORCEON_YCLKA@GOTPCREL(%rip), %rcx
	movq	_RADEON_FORCEON_YCLKB@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	movq	_RADEON_FORCEON_MC@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movq	_R300_DISABLE_MC_MCLKA@GOTPCREL(%rip), %r12
	testl	%ebx, (%r12)
	je	LBB0_18
## %bb.11:
	movq	_R300_DISABLE_MC_MCLKB@GOTPCREL(%rip), %r13
	testl	%ebx, (%r13)
	je	LBB0_18
## %bb.12:
	movl	(%r15), %edi
	callq	_RREG32_PLL
	movl	%eax, %ebx
	cmpl	$64, 16(%r14)
	jne	LBB0_16
## %bb.13:
	movq	_RADEON_MEM_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_R300_MEM_USE_CD_CH_ONLY@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_15
## %bb.14:
	movl	(%r13), %eax
	jmp	LBB0_17
LBB0_49:
	movq	_R300_SCLK_CNTL2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_R300_SCLK_FORCE_TCL@GOTPCREL(%rip), %rcx
	movq	_R300_SCLK_FORCE_GA@GOTPCREL(%rip), %rdx
	orl	(%rcx), %eax
	orl	(%rdx), %eax
	movq	_R300_SCLK_FORCE_CBA@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PLL
	movq	_RADEON_SCLK_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_SCLK_FORCE_DISP2@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_CP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_HDP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_DISP1@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_TOP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_E2@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_SCLK_FORCE_VAP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_IDCT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_VIP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_SCLK_FORCE_SR@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_SCLK_FORCE_PX@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_SCLK_FORCE_TX@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_SCLK_FORCE_US@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_TV_SCLK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_R300_SCLK_FORCE_SU@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_SCLK_FORCE_OV0@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PLL
	movq	_RADEON_SCLK_MORE_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_SCLK_MORE_FORCEON@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PLL
	movq	_RADEON_MCLK_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_FORCEON_MCLKA@GOTPCREL(%rip), %rcx
	movq	_RADEON_FORCEON_MCLKB@GOTPCREL(%rip), %rdx
	movq	_RADEON_FORCEON_YCLKA@GOTPCREL(%rip), %rsi
	movq	_RADEON_FORCEON_YCLKB@GOTPCREL(%rip), %rdi
	orl	(%rcx), %eax
	orl	(%rdx), %eax
	orl	(%rsi), %eax
	orl	(%rdi), %eax
	movq	_RADEON_FORCEON_MC@GOTPCREL(%rip), %rcx
LBB0_47:
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PLL
	movq	_RADEON_VCLK_ECP_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_PIXCLK_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	movq	_RADEON_PIXCLK_DAC_ALWAYS_ONb@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	movq	_R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32_PLL
	movq	_RADEON_PIXCLKS_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_PIX2CLK_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	movq	_RADEON_PIX2CLK_DAC_ALWAYS_ONb@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	movq	_RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_R300_DVOCLK_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_RADEON_PIXCLK_BLEND_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_RADEON_PIXCLK_GV_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_R300_PIXCLK_DVO_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_RADEON_PIXCLK_TMDS_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_R300_PIXCLK_TRANS_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_R300_PIXCLK_TVO_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_R300_P2G2CLK_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_R300_P2G2CLK_DAC_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF@GOTPCREL(%rip), %rcx
	jmp	LBB0_21
LBB0_52:
	movq	8(%r14), %rcx
	movq	_CHIP_R300@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	je	LBB0_54
## %bb.53:
	movq	_CHIP_R350@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_55
LBB0_54:
	movq	_RADEON_SCLK_FORCE_HDP@GOTPCREL(%rip), %rcx
	movq	_RADEON_SCLK_FORCE_DISP1@GOTPCREL(%rip), %rdx
	movq	_RADEON_SCLK_FORCE_DISP2@GOTPCREL(%rip), %rsi
	movq	_RADEON_SCLK_FORCE_TOP@GOTPCREL(%rip), %rdi
	movq	_RADEON_SCLK_FORCE_IDCT@GOTPCREL(%rip), %rbx
	movq	_RADEON_SCLK_FORCE_VIP@GOTPCREL(%rip), %r8
	orl	(%rcx), %eax
	orl	(%rdx), %eax
	orl	(%rsi), %eax
	orl	(%rdi), %eax
	orl	(%rbx), %eax
	orl	(%r8), %eax
LBB0_55:
	movl	(%r15), %edi
	movl	%eax, %esi
	callq	_WREG32_PLL
	movl	$16, %edi
	callq	_mdelay
	movq	8(%r14), %rax
	movq	_CHIP_R300@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_57
## %bb.56:
	movq	_CHIP_R350@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_58
LBB0_57:
	movq	_R300_SCLK_CNTL2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_R300_SCLK_FORCE_TCL@GOTPCREL(%rip), %rcx
	movq	_R300_SCLK_FORCE_GA@GOTPCREL(%rip), %rdx
	orl	(%rcx), %eax
	orl	(%rdx), %eax
	movq	_R300_SCLK_FORCE_CBA@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PLL
	movl	$16, %edi
	callq	_mdelay
LBB0_58:
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r14)
	je	LBB0_60
## %bb.59:
	movq	_RADEON_MCLK_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_FORCEON_MCLKA@GOTPCREL(%rip), %rcx
	movq	_RADEON_FORCEON_YCLKA@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32_PLL
	movl	$16, %edi
	callq	_mdelay
LBB0_60:
	movq	8(%r14), %rax
	movq	_CHIP_RV200@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_63
## %bb.61:
	movq	_CHIP_RV250@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_63
## %bb.62:
	movq	_CHIP_RV280@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_64
LBB0_63:
	movq	_RADEON_SCLK_MORE_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_SCLK_MORE_FORCEON@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32_PLL
	movl	$16, %edi
	callq	_mdelay
LBB0_64:
	movq	_RADEON_PIXCLKS_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_PIX2CLK_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	movq	_RADEON_PIX2CLK_DAC_ALWAYS_ONb@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	movq	_RADEON_PIXCLK_BLEND_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_RADEON_PIXCLK_GV_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_RADEON_PIXCLK_TMDS_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32_PLL
	movl	$16, %edi
	callq	_mdelay
	movq	_RADEON_VCLK_ECP_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32_PLL
	movq	_RADEON_PIXCLK_ALWAYS_ONb@GOTPCREL(%rip), %rcx
	movq	_RADEON_PIXCLK_DAC_ALWAYS_ONb@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
LBB0_21:
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
LBB0_19:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_PLL                     ## TAILCALL
LBB0_16:
	movl	(%r13), %eax
	orl	(%r12), %eax
	jmp	LBB0_17
LBB0_15:
	movl	(%r12), %eax
LBB0_17:
	notl	%eax
	andl	%eax, %ebx
LBB0_18:
	movl	(%r15), %edi
	movl	%ebx, %esi
	jmp	LBB0_19
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_SINGLE_CRTC,4,2         ## @RADEON_SINGLE_CRTC
	.comm	_RADEON_SCLK_CNTL,4,2           ## @RADEON_SCLK_CNTL
	.comm	_RADEON_CONFIG_CNTL,4,2         ## @RADEON_CONFIG_CNTL
	.comm	_RADEON_CFG_ATI_REV_ID_MASK,4,2 ## @RADEON_CFG_ATI_REV_ID_MASK
	.comm	_RADEON_CFG_ATI_REV_A13,4,2     ## @RADEON_CFG_ATI_REV_A13
	.comm	_RADEON_SCLK_FORCE_CP,4,2       ## @RADEON_SCLK_FORCE_CP
	.comm	_RADEON_SCLK_FORCE_RB,4,2       ## @RADEON_SCLK_FORCE_RB
	.comm	_RADEON_SCLK_FORCE_HDP,4,2      ## @RADEON_SCLK_FORCE_HDP
	.comm	_RADEON_SCLK_FORCE_DISP1,4,2    ## @RADEON_SCLK_FORCE_DISP1
	.comm	_RADEON_SCLK_FORCE_TOP,4,2      ## @RADEON_SCLK_FORCE_TOP
	.comm	_RADEON_SCLK_FORCE_SE,4,2       ## @RADEON_SCLK_FORCE_SE
	.comm	_RADEON_SCLK_FORCE_IDCT,4,2     ## @RADEON_SCLK_FORCE_IDCT
	.comm	_RADEON_SCLK_FORCE_RE,4,2       ## @RADEON_SCLK_FORCE_RE
	.comm	_RADEON_SCLK_FORCE_PB,4,2       ## @RADEON_SCLK_FORCE_PB
	.comm	_RADEON_SCLK_FORCE_TAM,4,2      ## @RADEON_SCLK_FORCE_TAM
	.comm	_RADEON_SCLK_FORCE_TDM,4,2      ## @RADEON_SCLK_FORCE_TDM
	.comm	_CHIP_RS400,8,3                 ## @CHIP_RS400
	.comm	_CHIP_RS480,8,3                 ## @CHIP_RS480
	.comm	_RADEON_SCLK_FORCE_DISP2,4,2    ## @RADEON_SCLK_FORCE_DISP2
	.comm	_RADEON_SCLK_FORCE_E2,4,2       ## @RADEON_SCLK_FORCE_E2
	.comm	_R300_SCLK_FORCE_VAP,4,2        ## @R300_SCLK_FORCE_VAP
	.comm	_RADEON_SCLK_FORCE_VIP,4,2      ## @RADEON_SCLK_FORCE_VIP
	.comm	_R300_SCLK_FORCE_SR,4,2         ## @R300_SCLK_FORCE_SR
	.comm	_R300_SCLK_FORCE_PX,4,2         ## @R300_SCLK_FORCE_PX
	.comm	_R300_SCLK_FORCE_TX,4,2         ## @R300_SCLK_FORCE_TX
	.comm	_R300_SCLK_FORCE_US,4,2         ## @R300_SCLK_FORCE_US
	.comm	_RADEON_SCLK_FORCE_TV_SCLK,4,2  ## @RADEON_SCLK_FORCE_TV_SCLK
	.comm	_R300_SCLK_FORCE_SU,4,2         ## @R300_SCLK_FORCE_SU
	.comm	_RADEON_SCLK_FORCE_OV0,4,2      ## @RADEON_SCLK_FORCE_OV0
	.comm	_RADEON_DYN_STOP_LAT_MASK,4,2   ## @RADEON_DYN_STOP_LAT_MASK
	.comm	_RADEON_SCLK_MORE_CNTL,4,2      ## @RADEON_SCLK_MORE_CNTL
	.comm	_RADEON_SCLK_MORE_FORCEON,4,2   ## @RADEON_SCLK_MORE_FORCEON
	.comm	_RADEON_SCLK_MORE_MAX_DYN_STOP_LAT,4,2 ## @RADEON_SCLK_MORE_MAX_DYN_STOP_LAT
	.comm	_RADEON_VCLK_ECP_CNTL,4,2       ## @RADEON_VCLK_ECP_CNTL
	.comm	_RADEON_PIXCLK_ALWAYS_ONb,4,2   ## @RADEON_PIXCLK_ALWAYS_ONb
	.comm	_RADEON_PIXCLK_DAC_ALWAYS_ONb,4,2 ## @RADEON_PIXCLK_DAC_ALWAYS_ONb
	.comm	_RADEON_PIXCLKS_CNTL,4,2        ## @RADEON_PIXCLKS_CNTL
	.comm	_RADEON_PIX2CLK_ALWAYS_ONb,4,2  ## @RADEON_PIX2CLK_ALWAYS_ONb
	.comm	_RADEON_PIX2CLK_DAC_ALWAYS_ONb,4,2 ## @RADEON_PIX2CLK_DAC_ALWAYS_ONb
	.comm	_RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb,4,2 ## @RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb
	.comm	_R300_DVOCLK_ALWAYS_ONb,4,2     ## @R300_DVOCLK_ALWAYS_ONb
	.comm	_RADEON_PIXCLK_BLEND_ALWAYS_ONb,4,2 ## @RADEON_PIXCLK_BLEND_ALWAYS_ONb
	.comm	_RADEON_PIXCLK_GV_ALWAYS_ONb,4,2 ## @RADEON_PIXCLK_GV_ALWAYS_ONb
	.comm	_R300_PIXCLK_DVO_ALWAYS_ONb,4,2 ## @R300_PIXCLK_DVO_ALWAYS_ONb
	.comm	_RADEON_PIXCLK_LVDS_ALWAYS_ONb,4,2 ## @RADEON_PIXCLK_LVDS_ALWAYS_ONb
	.comm	_RADEON_PIXCLK_TMDS_ALWAYS_ONb,4,2 ## @RADEON_PIXCLK_TMDS_ALWAYS_ONb
	.comm	_R300_PIXCLK_TRANS_ALWAYS_ONb,4,2 ## @R300_PIXCLK_TRANS_ALWAYS_ONb
	.comm	_R300_PIXCLK_TVO_ALWAYS_ONb,4,2 ## @R300_PIXCLK_TVO_ALWAYS_ONb
	.comm	_R300_P2G2CLK_ALWAYS_ONb,4,2    ## @R300_P2G2CLK_ALWAYS_ONb
	.comm	_R300_P2G2CLK_DAC_ALWAYS_ONb,4,2 ## @R300_P2G2CLK_DAC_ALWAYS_ONb
	.comm	_CHIP_RV350,8,3                 ## @CHIP_RV350
	.comm	_R300_SCLK_CNTL2,4,2            ## @R300_SCLK_CNTL2
	.comm	_R300_SCLK_FORCE_TCL,4,2        ## @R300_SCLK_FORCE_TCL
	.comm	_R300_SCLK_FORCE_GA,4,2         ## @R300_SCLK_FORCE_GA
	.comm	_R300_SCLK_FORCE_CBA,4,2        ## @R300_SCLK_FORCE_CBA
	.comm	_R300_SCLK_TCL_MAX_DYN_STOP_LAT,4,2 ## @R300_SCLK_TCL_MAX_DYN_STOP_LAT
	.comm	_R300_SCLK_GA_MAX_DYN_STOP_LAT,4,2 ## @R300_SCLK_GA_MAX_DYN_STOP_LAT
	.comm	_R300_SCLK_CBA_MAX_DYN_STOP_LAT,4,2 ## @R300_SCLK_CBA_MAX_DYN_STOP_LAT
	.comm	_RADEON_MCLK_MISC,4,2           ## @RADEON_MCLK_MISC
	.comm	_RADEON_MC_MCLK_DYN_ENABLE,4,2  ## @RADEON_MC_MCLK_DYN_ENABLE
	.comm	_RADEON_IO_MCLK_DYN_ENABLE,4,2  ## @RADEON_IO_MCLK_DYN_ENABLE
	.comm	_RADEON_MCLK_CNTL,4,2           ## @RADEON_MCLK_CNTL
	.comm	_RADEON_FORCEON_MCLKA,4,2       ## @RADEON_FORCEON_MCLKA
	.comm	_RADEON_FORCEON_MCLKB,4,2       ## @RADEON_FORCEON_MCLKB
	.comm	_RADEON_FORCEON_YCLKA,4,2       ## @RADEON_FORCEON_YCLKA
	.comm	_RADEON_FORCEON_YCLKB,4,2       ## @RADEON_FORCEON_YCLKB
	.comm	_RADEON_FORCEON_MC,4,2          ## @RADEON_FORCEON_MC
	.comm	_R300_DISABLE_MC_MCLKA,4,2      ## @R300_DISABLE_MC_MCLKA
	.comm	_R300_DISABLE_MC_MCLKB,4,2      ## @R300_DISABLE_MC_MCLKB
	.comm	_RADEON_MEM_CNTL,4,2            ## @RADEON_MEM_CNTL
	.comm	_R300_MEM_USE_CD_CH_ONLY,4,2    ## @R300_MEM_USE_CD_CH_ONLY
	.comm	_RADEON_CLK_PWRMGT_CNTL,4,2     ## @RADEON_CLK_PWRMGT_CNTL
	.comm	_RADEON_ACTIVE_HILO_LAT_MASK,4,2 ## @RADEON_ACTIVE_HILO_LAT_MASK
	.comm	_RADEON_DISP_DYN_STOP_LAT_MASK,4,2 ## @RADEON_DISP_DYN_STOP_LAT_MASK
	.comm	_RADEON_DYN_STOP_MODE_MASK,4,2  ## @RADEON_DYN_STOP_MODE_MASK
	.comm	_RADEON_ENGIN_DYNCLK_MODE,4,2   ## @RADEON_ENGIN_DYNCLK_MODE
	.comm	_RADEON_ACTIVE_HILO_LAT_SHIFT,4,2 ## @RADEON_ACTIVE_HILO_LAT_SHIFT
	.comm	_RADEON_CLK_PIN_CNTL,4,2        ## @RADEON_CLK_PIN_CNTL
	.comm	_RADEON_SCLK_DYN_START_CNTL,4,2 ## @RADEON_SCLK_DYN_START_CNTL
	.comm	_RADEON_SCLK_FORCEON_MASK,4,2   ## @RADEON_SCLK_FORCEON_MASK
	.comm	_CHIP_RV250,8,3                 ## @CHIP_RV250
	.comm	_CHIP_RV100,8,3                 ## @CHIP_RV100
	.comm	_CHIP_RV200,8,3                 ## @CHIP_RV200
	.comm	_CHIP_RV280,8,3                 ## @CHIP_RV280
	.comm	_RADEON_PLL_PWRMGT_CNTL,4,2     ## @RADEON_PLL_PWRMGT_CNTL
	.comm	_RADEON_TCL_BYPASS_DISABLE,4,2  ## @RADEON_TCL_BYPASS_DISABLE
	.comm	_RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb,4,2 ## @RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb
	.comm	_R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF,4,2 ## @R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF
	.comm	_R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF,4,2 ## @R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF
	.comm	_CHIP_R300,8,3                  ## @CHIP_R300
	.comm	_CHIP_R350,8,3                  ## @CHIP_R350
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_legacy_set_clock_gating ; -- Begin function radeon_legacy_set_clock_gating
	.p2align	2
_radeon_legacy_set_clock_gating:        ; @radeon_legacy_set_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	w8, [x0]
Lloh0:
	adrp	x21, _RADEON_SINGLE_CRTC@GOTPAGE
Lloh1:
	ldr	x21, [x21, _RADEON_SINGLE_CRTC@GOTPAGEOFF]
	ldr	w9, [x21]
	and	w8, w9, w8
	cbz	w1, LBB0_5
; %bb.1:
	cbz	w8, LBB0_7
; %bb.2:
Lloh2:
	adrp	x20, _RADEON_SCLK_CNTL@GOTPAGE
Lloh3:
	ldr	x20, [x20, _RADEON_SCLK_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PLL
	mov	x19, x0
Lloh4:
	adrp	x8, _RADEON_CONFIG_CNTL@GOTPAGE
Lloh5:
	ldr	x8, [x8, _RADEON_CONFIG_CNTL@GOTPAGEOFF]
Lloh6:
	ldr	w0, [x8]
	bl	_RREG32
Lloh7:
	adrp	x8, _RADEON_CFG_ATI_REV_ID_MASK@GOTPAGE
Lloh8:
	ldr	x8, [x8, _RADEON_CFG_ATI_REV_ID_MASK@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh10:
	adrp	x9, _RADEON_CFG_ATI_REV_A13@GOTPAGE
Lloh11:
	ldr	x9, [x9, _RADEON_CFG_ATI_REV_A13@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
	cmp	w8, w9
	b.le	LBB0_4
; %bb.3:
Lloh13:
	adrp	x8, _RADEON_SCLK_FORCE_CP@GOTPAGE
Lloh14:
	ldr	x8, [x8, _RADEON_SCLK_FORCE_CP@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
Lloh16:
	adrp	x9, _RADEON_SCLK_FORCE_RB@GOTPAGE
Lloh17:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_RB@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w19, w19, w8
LBB0_4:
Lloh19:
	adrp	x8, _RADEON_SCLK_FORCE_HDP@GOTPAGE
Lloh20:
	ldr	x8, [x8, _RADEON_SCLK_FORCE_HDP@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
Lloh22:
	adrp	x9, _RADEON_SCLK_FORCE_DISP1@GOTPAGE
Lloh23:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_DISP1@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh25:
	adrp	x9, _RADEON_SCLK_FORCE_TOP@GOTPAGE
Lloh26:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_TOP@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh28:
	adrp	x9, _RADEON_SCLK_FORCE_SE@GOTPAGE
Lloh29:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_SE@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh31:
	adrp	x9, _RADEON_SCLK_FORCE_IDCT@GOTPAGE
Lloh32:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_IDCT@GOTPAGEOFF]
Lloh33:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh34:
	adrp	x9, _RADEON_SCLK_FORCE_RE@GOTPAGE
Lloh35:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_RE@GOTPAGEOFF]
Lloh36:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh37:
	adrp	x9, _RADEON_SCLK_FORCE_PB@GOTPAGE
Lloh38:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_PB@GOTPAGEOFF]
Lloh39:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh40:
	adrp	x9, _RADEON_SCLK_FORCE_TAM@GOTPAGE
Lloh41:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_TAM@GOTPAGEOFF]
Lloh42:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh43:
	adrp	x9, _RADEON_SCLK_FORCE_TDM@GOTPAGE
Lloh44:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_TDM@GOTPAGEOFF]
Lloh45:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w1, w19, w8
	ldr	w0, [x20]
	b	LBB0_47
LBB0_5:
	cbz	w8, LBB0_11
; %bb.6:
Lloh46:
	adrp	x19, _RADEON_SCLK_CNTL@GOTPAGE
Lloh47:
	ldr	x19, [x19, _RADEON_SCLK_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh48:
	adrp	x8, _RADEON_SCLK_FORCE_CP@GOTPAGE
Lloh49:
	ldr	x8, [x8, _RADEON_SCLK_FORCE_CP@GOTPAGEOFF]
Lloh50:
	ldr	w8, [x8]
Lloh51:
	adrp	x9, _RADEON_SCLK_FORCE_HDP@GOTPAGE
Lloh52:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_HDP@GOTPAGEOFF]
Lloh53:
	adrp	x10, _RADEON_SCLK_FORCE_DISP1@GOTPAGE
Lloh54:
	ldr	x10, [x10, _RADEON_SCLK_FORCE_DISP1@GOTPAGEOFF]
Lloh55:
	ldr	w9, [x9]
Lloh56:
	ldr	w10, [x10]
Lloh57:
	adrp	x11, _RADEON_SCLK_FORCE_TOP@GOTPAGE
Lloh58:
	ldr	x11, [x11, _RADEON_SCLK_FORCE_TOP@GOTPAGEOFF]
Lloh59:
	adrp	x12, _RADEON_SCLK_FORCE_E2@GOTPAGE
Lloh60:
	ldr	x12, [x12, _RADEON_SCLK_FORCE_E2@GOTPAGEOFF]
Lloh61:
	ldr	w11, [x11]
Lloh62:
	ldr	w12, [x12]
Lloh63:
	adrp	x13, _RADEON_SCLK_FORCE_SE@GOTPAGE
Lloh64:
	ldr	x13, [x13, _RADEON_SCLK_FORCE_SE@GOTPAGEOFF]
Lloh65:
	adrp	x14, _RADEON_SCLK_FORCE_IDCT@GOTPAGE
Lloh66:
	ldr	x14, [x14, _RADEON_SCLK_FORCE_IDCT@GOTPAGEOFF]
Lloh67:
	ldr	w13, [x13]
Lloh68:
	ldr	w14, [x14]
Lloh69:
	adrp	x15, _RADEON_SCLK_FORCE_VIP@GOTPAGE
Lloh70:
	ldr	x15, [x15, _RADEON_SCLK_FORCE_VIP@GOTPAGEOFF]
Lloh71:
	adrp	x16, _RADEON_SCLK_FORCE_RE@GOTPAGE
Lloh72:
	ldr	x16, [x16, _RADEON_SCLK_FORCE_RE@GOTPAGEOFF]
Lloh73:
	ldr	w15, [x15]
Lloh74:
	ldr	w16, [x16]
Lloh75:
	adrp	x17, _RADEON_SCLK_FORCE_PB@GOTPAGE
Lloh76:
	ldr	x17, [x17, _RADEON_SCLK_FORCE_PB@GOTPAGEOFF]
Lloh77:
	adrp	x1, _RADEON_SCLK_FORCE_TAM@GOTPAGE
Lloh78:
	ldr	x1, [x1, _RADEON_SCLK_FORCE_TAM@GOTPAGEOFF]
Lloh79:
	ldr	w17, [x17]
Lloh80:
	ldr	w1, [x1]
Lloh81:
	adrp	x2, _RADEON_SCLK_FORCE_TDM@GOTPAGE
Lloh82:
	ldr	x2, [x2, _RADEON_SCLK_FORCE_TDM@GOTPAGEOFF]
Lloh83:
	adrp	x3, _RADEON_SCLK_FORCE_RB@GOTPAGE
Lloh84:
	ldr	x3, [x3, _RADEON_SCLK_FORCE_RB@GOTPAGEOFF]
	b	LBB0_10
LBB0_7:
	mov	x0, x19
	bl	_ASIC_IS_R300
	cbz	x0, LBB0_13
; %bb.8:
	ldr	x8, [x19, #8]
Lloh85:
	adrp	x9, _CHIP_RS400@GOTPAGE
Lloh86:
	ldr	x9, [x9, _CHIP_RS400@GOTPAGEOFF]
Lloh87:
	ldr	x9, [x9]
Lloh88:
	adrp	x10, _CHIP_RS480@GOTPAGE
Lloh89:
	ldr	x10, [x10, _CHIP_RS480@GOTPAGEOFF]
Lloh90:
	ldr	x10, [x10]
	cmp	x8, x9
	ccmp	x8, x10, #4, ne
	b.ne	LBB0_32
; %bb.9:
Lloh91:
	adrp	x19, _RADEON_SCLK_CNTL@GOTPAGE
Lloh92:
	ldr	x19, [x19, _RADEON_SCLK_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh93:
	adrp	x8, _RADEON_SCLK_FORCE_DISP2@GOTPAGE
Lloh94:
	ldr	x8, [x8, _RADEON_SCLK_FORCE_DISP2@GOTPAGEOFF]
Lloh95:
	ldr	w8, [x8]
Lloh96:
	adrp	x9, _RADEON_SCLK_FORCE_CP@GOTPAGE
Lloh97:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_CP@GOTPAGEOFF]
Lloh98:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh99:
	adrp	x9, _RADEON_SCLK_FORCE_HDP@GOTPAGE
Lloh100:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_HDP@GOTPAGEOFF]
Lloh101:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh102:
	adrp	x9, _RADEON_SCLK_FORCE_DISP1@GOTPAGE
Lloh103:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_DISP1@GOTPAGEOFF]
Lloh104:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh105:
	adrp	x9, _RADEON_SCLK_FORCE_TOP@GOTPAGE
Lloh106:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_TOP@GOTPAGEOFF]
Lloh107:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh108:
	adrp	x10, _RADEON_SCLK_FORCE_E2@GOTPAGE
Lloh109:
	ldr	x10, [x10, _RADEON_SCLK_FORCE_E2@GOTPAGEOFF]
Lloh110:
	ldr	w10, [x10]
	orr	w8, w8, w10
Lloh111:
	adrp	x10, _R300_SCLK_FORCE_VAP@GOTPAGE
Lloh112:
	ldr	x10, [x10, _R300_SCLK_FORCE_VAP@GOTPAGEOFF]
Lloh113:
	ldr	w10, [x10]
	orr	w8, w8, w10
Lloh114:
	adrp	x10, _RADEON_SCLK_FORCE_IDCT@GOTPAGE
Lloh115:
	ldr	x10, [x10, _RADEON_SCLK_FORCE_IDCT@GOTPAGEOFF]
Lloh116:
	ldr	w10, [x10]
	orr	w8, w8, w10
Lloh117:
	adrp	x10, _RADEON_SCLK_FORCE_VIP@GOTPAGE
Lloh118:
	ldr	x10, [x10, _RADEON_SCLK_FORCE_VIP@GOTPAGEOFF]
Lloh119:
	ldr	w10, [x10]
	orr	w8, w8, w10
Lloh120:
	adrp	x11, _R300_SCLK_FORCE_SR@GOTPAGE
Lloh121:
	ldr	x11, [x11, _R300_SCLK_FORCE_SR@GOTPAGEOFF]
Lloh122:
	ldr	w11, [x11]
	orr	w8, w8, w11
Lloh123:
	adrp	x11, _R300_SCLK_FORCE_PX@GOTPAGE
Lloh124:
	ldr	x11, [x11, _R300_SCLK_FORCE_PX@GOTPAGEOFF]
Lloh125:
	ldr	w11, [x11]
	orr	w8, w8, w11
Lloh126:
	adrp	x11, _R300_SCLK_FORCE_TX@GOTPAGE
Lloh127:
	ldr	x11, [x11, _R300_SCLK_FORCE_TX@GOTPAGEOFF]
Lloh128:
	ldr	w11, [x11]
	orr	w8, w8, w11
Lloh129:
	adrp	x11, _R300_SCLK_FORCE_US@GOTPAGE
Lloh130:
	ldr	x11, [x11, _R300_SCLK_FORCE_US@GOTPAGEOFF]
Lloh131:
	ldr	w11, [x11]
	orr	w8, w8, w11
Lloh132:
	adrp	x11, _RADEON_SCLK_FORCE_TV_SCLK@GOTPAGE
Lloh133:
	ldr	x11, [x11, _RADEON_SCLK_FORCE_TV_SCLK@GOTPAGEOFF]
Lloh134:
	ldr	w11, [x11]
	orr	w8, w8, w11
Lloh135:
	adrp	x11, _R300_SCLK_FORCE_SU@GOTPAGE
Lloh136:
	ldr	x11, [x11, _R300_SCLK_FORCE_SU@GOTPAGEOFF]
Lloh137:
	ldr	w11, [x11]
	orr	w8, w8, w11
Lloh138:
	adrp	x11, _RADEON_SCLK_FORCE_OV0@GOTPAGE
Lloh139:
	ldr	x11, [x11, _RADEON_SCLK_FORCE_OV0@GOTPAGEOFF]
Lloh140:
	ldr	w11, [x11]
	orr	w8, w8, w11
Lloh141:
	adrp	x11, _RADEON_DYN_STOP_LAT_MASK@GOTPAGE
Lloh142:
	ldr	x11, [x11, _RADEON_DYN_STOP_LAT_MASK@GOTPAGEOFF]
	bic	w8, w0, w8
Lloh143:
	ldr	w11, [x11]
	orr	w9, w10, w9
	orr	w9, w9, w11
	orr	w1, w9, w8
	ldr	w0, [x19]
	bl	_WREG32_PLL
Lloh144:
	adrp	x19, _RADEON_SCLK_MORE_CNTL@GOTPAGE
Lloh145:
	ldr	x19, [x19, _RADEON_SCLK_MORE_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh146:
	adrp	x8, _RADEON_SCLK_MORE_FORCEON@GOTPAGE
Lloh147:
	ldr	x8, [x8, _RADEON_SCLK_MORE_FORCEON@GOTPAGEOFF]
Lloh148:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh149:
	adrp	x9, _RADEON_SCLK_MORE_MAX_DYN_STOP_LAT@GOTPAGE
Lloh150:
	ldr	x9, [x9, _RADEON_SCLK_MORE_MAX_DYN_STOP_LAT@GOTPAGEOFF]
Lloh151:
	ldr	w9, [x9]
	orr	w1, w8, w9
	ldr	w0, [x19]
	bl	_WREG32_PLL
Lloh152:
	adrp	x19, _RADEON_VCLK_ECP_CNTL@GOTPAGE
Lloh153:
	ldr	x19, [x19, _RADEON_VCLK_ECP_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh154:
	adrp	x8, _RADEON_PIXCLK_ALWAYS_ONb@GOTPAGE
Lloh155:
	ldr	x8, [x8, _RADEON_PIXCLK_ALWAYS_ONb@GOTPAGEOFF]
Lloh156:
	ldr	w8, [x8]
Lloh157:
	adrp	x9, _RADEON_PIXCLK_DAC_ALWAYS_ONb@GOTPAGE
Lloh158:
	ldr	x9, [x9, _RADEON_PIXCLK_DAC_ALWAYS_ONb@GOTPAGEOFF]
Lloh159:
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w1, w8, w9
	ldr	w0, [x19]
	bl	_WREG32_PLL
Lloh160:
	adrp	x19, _RADEON_PIXCLKS_CNTL@GOTPAGE
Lloh161:
	ldr	x19, [x19, _RADEON_PIXCLKS_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh162:
	adrp	x8, _RADEON_PIX2CLK_ALWAYS_ONb@GOTPAGE
Lloh163:
	ldr	x8, [x8, _RADEON_PIX2CLK_ALWAYS_ONb@GOTPAGEOFF]
Lloh164:
	ldr	w8, [x8]
Lloh165:
	adrp	x9, _RADEON_PIX2CLK_DAC_ALWAYS_ONb@GOTPAGE
Lloh166:
	ldr	x9, [x9, _RADEON_PIX2CLK_DAC_ALWAYS_ONb@GOTPAGEOFF]
Lloh167:
	adrp	x10, _RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb@GOTPAGE
Lloh168:
	ldr	x10, [x10, _RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb@GOTPAGEOFF]
Lloh169:
	ldr	w9, [x9]
Lloh170:
	ldr	w10, [x10]
Lloh171:
	adrp	x11, _R300_DVOCLK_ALWAYS_ONb@GOTPAGE
Lloh172:
	ldr	x11, [x11, _R300_DVOCLK_ALWAYS_ONb@GOTPAGEOFF]
Lloh173:
	adrp	x12, _RADEON_PIXCLK_BLEND_ALWAYS_ONb@GOTPAGE
Lloh174:
	ldr	x12, [x12, _RADEON_PIXCLK_BLEND_ALWAYS_ONb@GOTPAGEOFF]
Lloh175:
	ldr	w11, [x11]
Lloh176:
	ldr	w12, [x12]
Lloh177:
	adrp	x13, _RADEON_PIXCLK_GV_ALWAYS_ONb@GOTPAGE
Lloh178:
	ldr	x13, [x13, _RADEON_PIXCLK_GV_ALWAYS_ONb@GOTPAGEOFF]
Lloh179:
	adrp	x14, _R300_PIXCLK_DVO_ALWAYS_ONb@GOTPAGE
Lloh180:
	ldr	x14, [x14, _R300_PIXCLK_DVO_ALWAYS_ONb@GOTPAGEOFF]
Lloh181:
	ldr	w13, [x13]
Lloh182:
	ldr	w14, [x14]
Lloh183:
	adrp	x15, _RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPAGE
Lloh184:
	ldr	x15, [x15, _RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPAGEOFF]
Lloh185:
	adrp	x16, _RADEON_PIXCLK_TMDS_ALWAYS_ONb@GOTPAGE
Lloh186:
	ldr	x16, [x16, _RADEON_PIXCLK_TMDS_ALWAYS_ONb@GOTPAGEOFF]
Lloh187:
	ldr	w15, [x15]
Lloh188:
	ldr	w16, [x16]
Lloh189:
	adrp	x17, _R300_PIXCLK_TRANS_ALWAYS_ONb@GOTPAGE
Lloh190:
	ldr	x17, [x17, _R300_PIXCLK_TRANS_ALWAYS_ONb@GOTPAGEOFF]
Lloh191:
	adrp	x1, _R300_PIXCLK_TVO_ALWAYS_ONb@GOTPAGE
Lloh192:
	ldr	x1, [x1, _R300_PIXCLK_TVO_ALWAYS_ONb@GOTPAGEOFF]
Lloh193:
	ldr	w17, [x17]
Lloh194:
	ldr	w1, [x1]
Lloh195:
	adrp	x2, _R300_P2G2CLK_ALWAYS_ONb@GOTPAGE
Lloh196:
	ldr	x2, [x2, _R300_P2G2CLK_ALWAYS_ONb@GOTPAGEOFF]
Lloh197:
	adrp	x3, _R300_P2G2CLK_DAC_ALWAYS_ONb@GOTPAGE
Lloh198:
	ldr	x3, [x3, _R300_P2G2CLK_DAC_ALWAYS_ONb@GOTPAGEOFF]
LBB0_10:
	ldr	w2, [x2]
	ldr	w3, [x3]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w8, w8, w13
	orr	w8, w8, w14
	orr	w8, w8, w15
	orr	w8, w8, w16
	orr	w8, w8, w17
	orr	w8, w8, w1
	orr	w8, w8, w2
	orr	w1, w8, w3
	b	LBB0_46
LBB0_11:
	ldr	x8, [x19, #8]
Lloh199:
	adrp	x9, _CHIP_RS400@GOTPAGE
Lloh200:
	ldr	x9, [x9, _CHIP_RS400@GOTPAGEOFF]
Lloh201:
	ldr	x9, [x9]
Lloh202:
	adrp	x10, _CHIP_RS480@GOTPAGE
Lloh203:
	ldr	x10, [x10, _CHIP_RS480@GOTPAGEOFF]
Lloh204:
	ldr	x10, [x10]
	cmp	x8, x9
	ccmp	x8, x10, #4, ne
	b.ne	LBB0_34
; %bb.12:
Lloh205:
	adrp	x19, _RADEON_SCLK_CNTL@GOTPAGE
Lloh206:
	ldr	x19, [x19, _RADEON_SCLK_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh207:
	adrp	x8, _RADEON_SCLK_FORCE_DISP2@GOTPAGE
Lloh208:
	ldr	x8, [x8, _RADEON_SCLK_FORCE_DISP2@GOTPAGEOFF]
Lloh209:
	ldr	w8, [x8]
Lloh210:
	adrp	x9, _RADEON_SCLK_FORCE_CP@GOTPAGE
Lloh211:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_CP@GOTPAGEOFF]
Lloh212:
	ldr	w9, [x9]
Lloh213:
	adrp	x10, _RADEON_SCLK_FORCE_HDP@GOTPAGE
Lloh214:
	ldr	x10, [x10, _RADEON_SCLK_FORCE_HDP@GOTPAGEOFF]
Lloh215:
	ldr	w10, [x10]
Lloh216:
	adrp	x11, _RADEON_SCLK_FORCE_DISP1@GOTPAGE
Lloh217:
	ldr	x11, [x11, _RADEON_SCLK_FORCE_DISP1@GOTPAGEOFF]
Lloh218:
	ldr	w11, [x11]
Lloh219:
	adrp	x12, _RADEON_SCLK_FORCE_TOP@GOTPAGE
Lloh220:
	ldr	x12, [x12, _RADEON_SCLK_FORCE_TOP@GOTPAGEOFF]
Lloh221:
	ldr	w12, [x12]
Lloh222:
	adrp	x13, _RADEON_SCLK_FORCE_E2@GOTPAGE
Lloh223:
	ldr	x13, [x13, _RADEON_SCLK_FORCE_E2@GOTPAGEOFF]
Lloh224:
	ldr	w13, [x13]
Lloh225:
	adrp	x14, _R300_SCLK_FORCE_VAP@GOTPAGE
Lloh226:
	ldr	x14, [x14, _R300_SCLK_FORCE_VAP@GOTPAGEOFF]
Lloh227:
	ldr	w14, [x14]
Lloh228:
	adrp	x15, _RADEON_SCLK_FORCE_IDCT@GOTPAGE
Lloh229:
	ldr	x15, [x15, _RADEON_SCLK_FORCE_IDCT@GOTPAGEOFF]
Lloh230:
	ldr	w15, [x15]
Lloh231:
	adrp	x16, _RADEON_SCLK_FORCE_VIP@GOTPAGE
Lloh232:
	ldr	x16, [x16, _RADEON_SCLK_FORCE_VIP@GOTPAGEOFF]
Lloh233:
	ldr	w16, [x16]
Lloh234:
	adrp	x17, _R300_SCLK_FORCE_SR@GOTPAGE
Lloh235:
	ldr	x17, [x17, _R300_SCLK_FORCE_SR@GOTPAGEOFF]
Lloh236:
	ldr	w17, [x17]
Lloh237:
	adrp	x1, _R300_SCLK_FORCE_PX@GOTPAGE
Lloh238:
	ldr	x1, [x1, _R300_SCLK_FORCE_PX@GOTPAGEOFF]
Lloh239:
	ldr	w1, [x1]
Lloh240:
	adrp	x2, _R300_SCLK_FORCE_TX@GOTPAGE
Lloh241:
	ldr	x2, [x2, _R300_SCLK_FORCE_TX@GOTPAGEOFF]
Lloh242:
	ldr	w2, [x2]
Lloh243:
	adrp	x3, _R300_SCLK_FORCE_US@GOTPAGE
Lloh244:
	ldr	x3, [x3, _R300_SCLK_FORCE_US@GOTPAGEOFF]
Lloh245:
	ldr	w3, [x3]
Lloh246:
	adrp	x4, _RADEON_SCLK_FORCE_TV_SCLK@GOTPAGE
Lloh247:
	ldr	x4, [x4, _RADEON_SCLK_FORCE_TV_SCLK@GOTPAGEOFF]
Lloh248:
	ldr	w4, [x4]
Lloh249:
	adrp	x5, _R300_SCLK_FORCE_SU@GOTPAGE
Lloh250:
	ldr	x5, [x5, _R300_SCLK_FORCE_SU@GOTPAGEOFF]
Lloh251:
	ldr	w5, [x5]
Lloh252:
	adrp	x6, _RADEON_SCLK_FORCE_OV0@GOTPAGE
Lloh253:
	ldr	x6, [x6, _RADEON_SCLK_FORCE_OV0@GOTPAGEOFF]
Lloh254:
	ldr	w6, [x6]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w8, w8, w13
	orr	w8, w8, w14
	orr	w8, w8, w15
	orr	w8, w8, w16
	orr	w8, w8, w17
	orr	w8, w8, w1
	orr	w8, w8, w2
	orr	w8, w8, w3
	orr	w8, w8, w4
	orr	w8, w8, w5
	orr	w1, w8, w6
	ldr	w0, [x19]
	bl	_WREG32_PLL
Lloh255:
	adrp	x19, _RADEON_SCLK_MORE_CNTL@GOTPAGE
Lloh256:
	ldr	x19, [x19, _RADEON_SCLK_MORE_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh257:
	adrp	x8, _RADEON_SCLK_MORE_FORCEON@GOTPAGE
Lloh258:
	ldr	x8, [x8, _RADEON_SCLK_MORE_FORCEON@GOTPAGEOFF]
Lloh259:
	ldr	w8, [x8]
	orr	w1, w8, w0
	b	LBB0_43
LBB0_13:
Lloh260:
	adrp	x20, _RADEON_CLK_PWRMGT_CNTL@GOTPAGE
Lloh261:
	ldr	x20, [x20, _RADEON_CLK_PWRMGT_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PLL
Lloh262:
	adrp	x8, _RADEON_ACTIVE_HILO_LAT_MASK@GOTPAGE
Lloh263:
	ldr	x8, [x8, _RADEON_ACTIVE_HILO_LAT_MASK@GOTPAGEOFF]
Lloh264:
	ldr	w8, [x8]
Lloh265:
	adrp	x9, _RADEON_DISP_DYN_STOP_LAT_MASK@GOTPAGE
Lloh266:
	ldr	x9, [x9, _RADEON_DISP_DYN_STOP_LAT_MASK@GOTPAGEOFF]
Lloh267:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh268:
	adrp	x9, _RADEON_DYN_STOP_MODE_MASK@GOTPAGE
Lloh269:
	ldr	x9, [x9, _RADEON_DYN_STOP_MODE_MASK@GOTPAGEOFF]
Lloh270:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w8, w0, w8
Lloh271:
	adrp	x9, _RADEON_ENGIN_DYNCLK_MODE@GOTPAGE
Lloh272:
	ldr	x9, [x9, _RADEON_ENGIN_DYNCLK_MODE@GOTPAGEOFF]
Lloh273:
	ldr	w9, [x9]
Lloh274:
	adrp	x10, _RADEON_ACTIVE_HILO_LAT_SHIFT@GOTPAGE
Lloh275:
	ldr	x10, [x10, _RADEON_ACTIVE_HILO_LAT_SHIFT@GOTPAGEOFF]
Lloh276:
	ldr	w10, [x10]
	mov	w11, #1
	lsl	w10, w11, w10
	orr	w8, w8, w9
	orr	w1, w8, w10
	ldr	w0, [x20]
	bl	_WREG32_PLL
	mov	w0, #15
	bl	_mdelay
Lloh277:
	adrp	x20, _RADEON_CLK_PIN_CNTL@GOTPAGE
Lloh278:
	ldr	x20, [x20, _RADEON_CLK_PIN_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PLL
Lloh279:
	adrp	x8, _RADEON_SCLK_DYN_START_CNTL@GOTPAGE
Lloh280:
	ldr	x8, [x8, _RADEON_SCLK_DYN_START_CNTL@GOTPAGEOFF]
Lloh281:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x20]
	bl	_WREG32_PLL
	mov	w0, #15
	bl	_mdelay
Lloh282:
	adrp	x22, _RADEON_SCLK_CNTL@GOTPAGE
Lloh283:
	ldr	x22, [x22, _RADEON_SCLK_CNTL@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_RREG32_PLL
Lloh284:
	adrp	x8, _RADEON_SCLK_FORCEON_MASK@GOTPAGE
Lloh285:
	ldr	x8, [x8, _RADEON_SCLK_FORCEON_MASK@GOTPAGEOFF]
Lloh286:
	ldr	w8, [x8]
	bic	w20, w0, w8
	ldr	x8, [x19, #8]
Lloh287:
	adrp	x21, _CHIP_RV250@GOTPAGE
Lloh288:
	ldr	x21, [x21, _CHIP_RV250@GOTPAGEOFF]
	ldr	x9, [x21]
	cmp	x8, x9
	b.ne	LBB0_16
; %bb.14:
Lloh289:
	adrp	x8, _RADEON_CONFIG_CNTL@GOTPAGE
Lloh290:
	ldr	x8, [x8, _RADEON_CONFIG_CNTL@GOTPAGEOFF]
Lloh291:
	ldr	w0, [x8]
	bl	_RREG32
Lloh292:
	adrp	x8, _RADEON_CFG_ATI_REV_ID_MASK@GOTPAGE
Lloh293:
	ldr	x8, [x8, _RADEON_CFG_ATI_REV_ID_MASK@GOTPAGEOFF]
Lloh294:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh295:
	adrp	x9, _RADEON_CFG_ATI_REV_A13@GOTPAGE
Lloh296:
	ldr	x9, [x9, _RADEON_CFG_ATI_REV_A13@GOTPAGEOFF]
Lloh297:
	ldr	w9, [x9]
	cmp	w8, w9
	b.lt	LBB0_18
; %bb.15:
	ldr	x8, [x19, #8]
LBB0_16:
Lloh298:
	adrp	x9, _CHIP_RV100@GOTPAGE
Lloh299:
	ldr	x9, [x9, _CHIP_RV100@GOTPAGEOFF]
Lloh300:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_19
; %bb.17:
Lloh301:
	adrp	x8, _RADEON_CONFIG_CNTL@GOTPAGE
Lloh302:
	ldr	x8, [x8, _RADEON_CONFIG_CNTL@GOTPAGEOFF]
Lloh303:
	ldr	w0, [x8]
	bl	_RREG32
Lloh304:
	adrp	x8, _RADEON_CFG_ATI_REV_ID_MASK@GOTPAGE
Lloh305:
	ldr	x8, [x8, _RADEON_CFG_ATI_REV_ID_MASK@GOTPAGEOFF]
Lloh306:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh307:
	adrp	x9, _RADEON_CFG_ATI_REV_A13@GOTPAGE
Lloh308:
	ldr	x9, [x9, _RADEON_CFG_ATI_REV_A13@GOTPAGEOFF]
Lloh309:
	ldr	w9, [x9]
	cmp	w8, w9
	b.gt	LBB0_19
LBB0_18:
Lloh310:
	adrp	x8, _RADEON_SCLK_FORCE_CP@GOTPAGE
Lloh311:
	ldr	x8, [x8, _RADEON_SCLK_FORCE_CP@GOTPAGEOFF]
Lloh312:
	ldr	w8, [x8]
	orr	w8, w8, w20
Lloh313:
	adrp	x9, _RADEON_SCLK_FORCE_VIP@GOTPAGE
Lloh314:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_VIP@GOTPAGEOFF]
Lloh315:
	ldr	w9, [x9]
	orr	w20, w8, w9
LBB0_19:
	ldr	w0, [x22]
	mov	x1, x20
	bl	_WREG32_PLL
	ldr	x8, [x19, #8]
Lloh316:
	adrp	x22, _CHIP_RV200@GOTPAGE
Lloh317:
	ldr	x22, [x22, _CHIP_RV200@GOTPAGEOFF]
	ldr	x9, [x22]
	cmp	x8, x9
	b.eq	LBB0_22
; %bb.20:
	ldr	x10, [x21]
	cmp	x8, x10
	b.eq	LBB0_22
; %bb.21:
Lloh318:
	adrp	x11, _CHIP_RV280@GOTPAGE
Lloh319:
	ldr	x11, [x11, _CHIP_RV280@GOTPAGEOFF]
Lloh320:
	ldr	x11, [x11]
	cmp	x8, x11
	b.ne	LBB0_27
LBB0_22:
Lloh321:
	adrp	x23, _RADEON_SCLK_MORE_CNTL@GOTPAGE
Lloh322:
	ldr	x23, [x23, _RADEON_SCLK_MORE_CNTL@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32_PLL
Lloh323:
	adrp	x24, _RADEON_SCLK_MORE_FORCEON@GOTPAGE
Lloh324:
	ldr	x24, [x24, _RADEON_SCLK_MORE_FORCEON@GOTPAGEOFF]
	ldr	w8, [x24]
	bic	w20, w0, w8
	ldr	x8, [x19, #8]
	ldr	x9, [x22]
	cmp	x8, x9
	b.eq	LBB0_24
; %bb.23:
	ldr	x9, [x21]
	cmp	x8, x9
	b.ne	LBB0_26
LBB0_24:
Lloh325:
	adrp	x8, _RADEON_CONFIG_CNTL@GOTPAGE
Lloh326:
	ldr	x8, [x8, _RADEON_CONFIG_CNTL@GOTPAGEOFF]
Lloh327:
	ldr	w0, [x8]
	bl	_RREG32
Lloh328:
	adrp	x8, _RADEON_CFG_ATI_REV_ID_MASK@GOTPAGE
Lloh329:
	ldr	x8, [x8, _RADEON_CFG_ATI_REV_ID_MASK@GOTPAGEOFF]
Lloh330:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh331:
	adrp	x9, _RADEON_CFG_ATI_REV_A13@GOTPAGE
Lloh332:
	ldr	x9, [x9, _RADEON_CFG_ATI_REV_A13@GOTPAGEOFF]
Lloh333:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ge	LBB0_26
; %bb.25:
	ldr	w8, [x24]
	orr	w20, w8, w20
LBB0_26:
	ldr	w0, [x23]
	mov	x1, x20
	bl	_WREG32_PLL
	mov	w0, #15
	bl	_mdelay
	ldr	x8, [x19, #8]
	ldr	x9, [x22]
	ldr	x10, [x21]
LBB0_27:
	cmp	x8, x9
	b.eq	LBB0_29
; %bb.28:
	cmp	x8, x10
	b.ne	LBB0_31
LBB0_29:
Lloh334:
	adrp	x8, _RADEON_CONFIG_CNTL@GOTPAGE
Lloh335:
	ldr	x8, [x8, _RADEON_CONFIG_CNTL@GOTPAGEOFF]
Lloh336:
	ldr	w0, [x8]
	bl	_RREG32
Lloh337:
	adrp	x8, _RADEON_CFG_ATI_REV_ID_MASK@GOTPAGE
Lloh338:
	ldr	x8, [x8, _RADEON_CFG_ATI_REV_ID_MASK@GOTPAGEOFF]
Lloh339:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh340:
	adrp	x9, _RADEON_CFG_ATI_REV_A13@GOTPAGE
Lloh341:
	ldr	x9, [x9, _RADEON_CFG_ATI_REV_A13@GOTPAGEOFF]
Lloh342:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ge	LBB0_31
; %bb.30:
Lloh343:
	adrp	x19, _RADEON_PLL_PWRMGT_CNTL@GOTPAGE
Lloh344:
	ldr	x19, [x19, _RADEON_PLL_PWRMGT_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh345:
	adrp	x8, _RADEON_TCL_BYPASS_DISABLE@GOTPAGE
Lloh346:
	ldr	x8, [x8, _RADEON_TCL_BYPASS_DISABLE@GOTPAGEOFF]
Lloh347:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x19]
	bl	_WREG32_PLL
LBB0_31:
	mov	w0, #15
	bl	_mdelay
Lloh348:
	adrp	x19, _RADEON_PIXCLKS_CNTL@GOTPAGE
Lloh349:
	ldr	x19, [x19, _RADEON_PIXCLKS_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh350:
	adrp	x8, _RADEON_PIX2CLK_ALWAYS_ONb@GOTPAGE
Lloh351:
	ldr	x8, [x8, _RADEON_PIX2CLK_ALWAYS_ONb@GOTPAGEOFF]
Lloh352:
	ldr	w8, [x8]
Lloh353:
	adrp	x9, _RADEON_PIX2CLK_DAC_ALWAYS_ONb@GOTPAGE
Lloh354:
	ldr	x9, [x9, _RADEON_PIX2CLK_DAC_ALWAYS_ONb@GOTPAGEOFF]
Lloh355:
	ldr	w9, [x9]
Lloh356:
	adrp	x10, _RADEON_PIXCLK_BLEND_ALWAYS_ONb@GOTPAGE
Lloh357:
	ldr	x10, [x10, _RADEON_PIXCLK_BLEND_ALWAYS_ONb@GOTPAGEOFF]
Lloh358:
	ldr	w10, [x10]
Lloh359:
	adrp	x11, _RADEON_PIXCLK_GV_ALWAYS_ONb@GOTPAGE
Lloh360:
	ldr	x11, [x11, _RADEON_PIXCLK_GV_ALWAYS_ONb@GOTPAGEOFF]
Lloh361:
	ldr	w11, [x11]
Lloh362:
	adrp	x12, _RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb@GOTPAGE
Lloh363:
	ldr	x12, [x12, _RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb@GOTPAGEOFF]
Lloh364:
	ldr	w12, [x12]
Lloh365:
	adrp	x13, _RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPAGE
Lloh366:
	ldr	x13, [x13, _RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPAGEOFF]
Lloh367:
	ldr	w13, [x13]
Lloh368:
	adrp	x14, _RADEON_PIXCLK_TMDS_ALWAYS_ONb@GOTPAGE
Lloh369:
	ldr	x14, [x14, _RADEON_PIXCLK_TMDS_ALWAYS_ONb@GOTPAGEOFF]
Lloh370:
	ldr	w14, [x14]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w8, w8, w13
	orr	w1, w8, w14
	ldr	w0, [x19]
	bl	_WREG32_PLL
	mov	w0, #15
	bl	_mdelay
Lloh371:
	adrp	x19, _RADEON_VCLK_ECP_CNTL@GOTPAGE
Lloh372:
	ldr	x19, [x19, _RADEON_VCLK_ECP_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh373:
	adrp	x8, _RADEON_PIXCLK_ALWAYS_ONb@GOTPAGE
Lloh374:
	ldr	x8, [x8, _RADEON_PIXCLK_ALWAYS_ONb@GOTPAGEOFF]
Lloh375:
	ldr	w8, [x8]
Lloh376:
	adrp	x9, _RADEON_PIXCLK_DAC_ALWAYS_ONb@GOTPAGE
Lloh377:
	ldr	x9, [x9, _RADEON_PIXCLK_DAC_ALWAYS_ONb@GOTPAGEOFF]
Lloh378:
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w1, w8, w9
	ldr	w0, [x19]
	bl	_WREG32_PLL
	mov	w0, #15
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_mdelay
LBB0_32:
Lloh379:
	adrp	x9, _CHIP_RV350@GOTPAGE
Lloh380:
	ldr	x9, [x9, _CHIP_RV350@GOTPAGEOFF]
Lloh381:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_37
; %bb.33:
Lloh382:
	adrp	x19, _RADEON_SCLK_CNTL@GOTPAGE
Lloh383:
	ldr	x19, [x19, _RADEON_SCLK_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh384:
	adrp	x8, _R300_SCLK_FORCE_VAP@GOTPAGE
Lloh385:
	ldr	x8, [x8, _R300_SCLK_FORCE_VAP@GOTPAGEOFF]
Lloh386:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh387:
	adrp	x9, _RADEON_SCLK_FORCE_CP@GOTPAGE
Lloh388:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_CP@GOTPAGEOFF]
Lloh389:
	ldr	w9, [x9]
	orr	w1, w8, w9
	ldr	w0, [x19]
	bl	_WREG32_PLL
	mov	w0, #15
	bl	_mdelay
Lloh390:
	adrp	x19, _R300_SCLK_CNTL2@GOTPAGE
Lloh391:
	ldr	x19, [x19, _R300_SCLK_CNTL2@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh392:
	adrp	x8, _R300_SCLK_FORCE_TCL@GOTPAGE
Lloh393:
	ldr	x8, [x8, _R300_SCLK_FORCE_TCL@GOTPAGEOFF]
Lloh394:
	ldr	w8, [x8]
Lloh395:
	adrp	x9, _R300_SCLK_FORCE_GA@GOTPAGE
Lloh396:
	ldr	x9, [x9, _R300_SCLK_FORCE_GA@GOTPAGEOFF]
Lloh397:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh398:
	adrp	x9, _R300_SCLK_FORCE_CBA@GOTPAGE
Lloh399:
	ldr	x9, [x9, _R300_SCLK_FORCE_CBA@GOTPAGEOFF]
	b	LBB0_44
LBB0_34:
Lloh400:
	adrp	x9, _CHIP_RV350@GOTPAGE
Lloh401:
	ldr	x9, [x9, _CHIP_RV350@GOTPAGEOFF]
Lloh402:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_42
; %bb.35:
Lloh403:
	adrp	x20, _RADEON_SCLK_CNTL@GOTPAGE
Lloh404:
	ldr	x20, [x20, _RADEON_SCLK_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PLL
Lloh405:
	adrp	x8, _RADEON_SCLK_FORCE_CP@GOTPAGE
Lloh406:
	ldr	x8, [x8, _RADEON_SCLK_FORCE_CP@GOTPAGEOFF]
Lloh407:
	ldr	w8, [x8]
Lloh408:
	adrp	x9, _RADEON_SCLK_FORCE_E2@GOTPAGE
Lloh409:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_E2@GOTPAGEOFF]
Lloh410:
	adrp	x10, _RADEON_SCLK_FORCE_SE@GOTPAGE
Lloh411:
	ldr	x10, [x10, _RADEON_SCLK_FORCE_SE@GOTPAGEOFF]
Lloh412:
	ldr	w9, [x9]
Lloh413:
	ldr	w10, [x10]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w1, w8, w10
	ldr	w8, [x19]
	ldr	w9, [x21]
Lloh414:
	adrp	x22, _CHIP_R300@GOTPAGE
Lloh415:
	ldr	x22, [x22, _CHIP_R300@GOTPAGEOFF]
Lloh416:
	adrp	x21, _CHIP_R350@GOTPAGE
Lloh417:
	ldr	x21, [x21, _CHIP_R350@GOTPAGEOFF]
	tst	w9, w8
	b.eq	LBB0_48
; %bb.36:
Lloh418:
	adrp	x8, _RADEON_SCLK_FORCE_RB@GOTPAGE
Lloh419:
	ldr	x8, [x8, _RADEON_SCLK_FORCE_RB@GOTPAGEOFF]
Lloh420:
	ldr	w8, [x8]
Lloh421:
	adrp	x9, _RADEON_SCLK_FORCE_TDM@GOTPAGE
Lloh422:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_TDM@GOTPAGEOFF]
Lloh423:
	ldr	w9, [x9]
Lloh424:
	adrp	x10, _RADEON_SCLK_FORCE_TAM@GOTPAGE
Lloh425:
	ldr	x10, [x10, _RADEON_SCLK_FORCE_TAM@GOTPAGEOFF]
Lloh426:
	ldr	w10, [x10]
Lloh427:
	adrp	x11, _RADEON_SCLK_FORCE_PB@GOTPAGE
Lloh428:
	ldr	x11, [x11, _RADEON_SCLK_FORCE_PB@GOTPAGEOFF]
Lloh429:
	ldr	w11, [x11]
Lloh430:
	adrp	x12, _RADEON_SCLK_FORCE_RE@GOTPAGE
Lloh431:
	ldr	x12, [x12, _RADEON_SCLK_FORCE_RE@GOTPAGEOFF]
Lloh432:
	ldr	w12, [x12]
Lloh433:
	adrp	x13, _RADEON_SCLK_FORCE_VIP@GOTPAGE
Lloh434:
	ldr	x13, [x13, _RADEON_SCLK_FORCE_VIP@GOTPAGEOFF]
Lloh435:
	ldr	w13, [x13]
Lloh436:
	adrp	x14, _RADEON_SCLK_FORCE_IDCT@GOTPAGE
Lloh437:
	ldr	x14, [x14, _RADEON_SCLK_FORCE_IDCT@GOTPAGEOFF]
Lloh438:
	ldr	w14, [x14]
Lloh439:
	adrp	x15, _RADEON_SCLK_FORCE_TOP@GOTPAGE
Lloh440:
	ldr	x15, [x15, _RADEON_SCLK_FORCE_TOP@GOTPAGEOFF]
Lloh441:
	ldr	w15, [x15]
Lloh442:
	adrp	x16, _RADEON_SCLK_FORCE_DISP1@GOTPAGE
Lloh443:
	ldr	x16, [x16, _RADEON_SCLK_FORCE_DISP1@GOTPAGEOFF]
Lloh444:
	ldr	w16, [x16]
Lloh445:
	adrp	x17, _RADEON_SCLK_FORCE_DISP2@GOTPAGE
Lloh446:
	ldr	x17, [x17, _RADEON_SCLK_FORCE_DISP2@GOTPAGEOFF]
Lloh447:
	ldr	w17, [x17]
Lloh448:
	adrp	x0, _RADEON_SCLK_FORCE_HDP@GOTPAGE
Lloh449:
	ldr	x0, [x0, _RADEON_SCLK_FORCE_HDP@GOTPAGEOFF]
Lloh450:
	ldr	w0, [x0]
	orr	w8, w8, w1
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w8, w8, w13
	orr	w8, w8, w14
	orr	w8, w8, w15
	orr	w8, w8, w16
	orr	w8, w8, w17
	orr	w1, w8, w0
	b	LBB0_51
LBB0_37:
Lloh451:
	adrp	x20, _R300_SCLK_CNTL2@GOTPAGE
Lloh452:
	ldr	x20, [x20, _R300_SCLK_CNTL2@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PLL
Lloh453:
	adrp	x8, _R300_SCLK_FORCE_TCL@GOTPAGE
Lloh454:
	ldr	x8, [x8, _R300_SCLK_FORCE_TCL@GOTPAGEOFF]
Lloh455:
	ldr	w8, [x8]
Lloh456:
	adrp	x9, _R300_SCLK_FORCE_GA@GOTPAGE
Lloh457:
	ldr	x9, [x9, _R300_SCLK_FORCE_GA@GOTPAGEOFF]
Lloh458:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh459:
	adrp	x9, _R300_SCLK_FORCE_CBA@GOTPAGE
Lloh460:
	ldr	x9, [x9, _R300_SCLK_FORCE_CBA@GOTPAGEOFF]
Lloh461:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh462:
	adrp	x9, _R300_SCLK_TCL_MAX_DYN_STOP_LAT@GOTPAGE
Lloh463:
	ldr	x9, [x9, _R300_SCLK_TCL_MAX_DYN_STOP_LAT@GOTPAGEOFF]
	bic	w8, w0, w8
Lloh464:
	ldr	w9, [x9]
Lloh465:
	adrp	x10, _R300_SCLK_GA_MAX_DYN_STOP_LAT@GOTPAGE
Lloh466:
	ldr	x10, [x10, _R300_SCLK_GA_MAX_DYN_STOP_LAT@GOTPAGEOFF]
Lloh467:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh468:
	adrp	x10, _R300_SCLK_CBA_MAX_DYN_STOP_LAT@GOTPAGE
Lloh469:
	ldr	x10, [x10, _R300_SCLK_CBA_MAX_DYN_STOP_LAT@GOTPAGEOFF]
Lloh470:
	ldr	w10, [x10]
	orr	w8, w9, w8
	orr	w1, w8, w10
	ldr	w0, [x20]
	bl	_WREG32_PLL
Lloh471:
	adrp	x20, _RADEON_SCLK_CNTL@GOTPAGE
Lloh472:
	ldr	x20, [x20, _RADEON_SCLK_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PLL
Lloh473:
	adrp	x8, _RADEON_SCLK_FORCE_DISP2@GOTPAGE
Lloh474:
	ldr	x8, [x8, _RADEON_SCLK_FORCE_DISP2@GOTPAGEOFF]
Lloh475:
	ldr	w8, [x8]
Lloh476:
	adrp	x9, _RADEON_SCLK_FORCE_CP@GOTPAGE
Lloh477:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_CP@GOTPAGEOFF]
Lloh478:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh479:
	adrp	x9, _RADEON_SCLK_FORCE_HDP@GOTPAGE
Lloh480:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_HDP@GOTPAGEOFF]
Lloh481:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh482:
	adrp	x9, _RADEON_SCLK_FORCE_DISP1@GOTPAGE
Lloh483:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_DISP1@GOTPAGEOFF]
Lloh484:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh485:
	adrp	x9, _RADEON_SCLK_FORCE_TOP@GOTPAGE
Lloh486:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_TOP@GOTPAGEOFF]
Lloh487:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh488:
	adrp	x9, _RADEON_SCLK_FORCE_E2@GOTPAGE
Lloh489:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_E2@GOTPAGEOFF]
Lloh490:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh491:
	adrp	x9, _R300_SCLK_FORCE_VAP@GOTPAGE
Lloh492:
	ldr	x9, [x9, _R300_SCLK_FORCE_VAP@GOTPAGEOFF]
Lloh493:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh494:
	adrp	x9, _RADEON_SCLK_FORCE_IDCT@GOTPAGE
Lloh495:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_IDCT@GOTPAGEOFF]
Lloh496:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh497:
	adrp	x9, _RADEON_SCLK_FORCE_VIP@GOTPAGE
Lloh498:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_VIP@GOTPAGEOFF]
Lloh499:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh500:
	adrp	x9, _R300_SCLK_FORCE_SR@GOTPAGE
Lloh501:
	ldr	x9, [x9, _R300_SCLK_FORCE_SR@GOTPAGEOFF]
Lloh502:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh503:
	adrp	x9, _R300_SCLK_FORCE_PX@GOTPAGE
Lloh504:
	ldr	x9, [x9, _R300_SCLK_FORCE_PX@GOTPAGEOFF]
Lloh505:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh506:
	adrp	x9, _R300_SCLK_FORCE_TX@GOTPAGE
Lloh507:
	ldr	x9, [x9, _R300_SCLK_FORCE_TX@GOTPAGEOFF]
Lloh508:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh509:
	adrp	x9, _R300_SCLK_FORCE_US@GOTPAGE
Lloh510:
	ldr	x9, [x9, _R300_SCLK_FORCE_US@GOTPAGEOFF]
Lloh511:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh512:
	adrp	x9, _RADEON_SCLK_FORCE_TV_SCLK@GOTPAGE
Lloh513:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_TV_SCLK@GOTPAGEOFF]
Lloh514:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh515:
	adrp	x9, _R300_SCLK_FORCE_SU@GOTPAGE
Lloh516:
	ldr	x9, [x9, _R300_SCLK_FORCE_SU@GOTPAGEOFF]
Lloh517:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh518:
	adrp	x9, _RADEON_SCLK_FORCE_OV0@GOTPAGE
Lloh519:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_OV0@GOTPAGEOFF]
Lloh520:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w8, w0, w8
Lloh521:
	adrp	x9, _RADEON_DYN_STOP_LAT_MASK@GOTPAGE
Lloh522:
	ldr	x9, [x9, _RADEON_DYN_STOP_LAT_MASK@GOTPAGEOFF]
Lloh523:
	ldr	w9, [x9]
	orr	w1, w8, w9
	ldr	w0, [x20]
	bl	_WREG32_PLL
Lloh524:
	adrp	x20, _RADEON_SCLK_MORE_CNTL@GOTPAGE
Lloh525:
	ldr	x20, [x20, _RADEON_SCLK_MORE_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PLL
Lloh526:
	adrp	x8, _RADEON_SCLK_MORE_FORCEON@GOTPAGE
Lloh527:
	ldr	x8, [x8, _RADEON_SCLK_MORE_FORCEON@GOTPAGEOFF]
Lloh528:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh529:
	adrp	x9, _RADEON_SCLK_MORE_MAX_DYN_STOP_LAT@GOTPAGE
Lloh530:
	ldr	x9, [x9, _RADEON_SCLK_MORE_MAX_DYN_STOP_LAT@GOTPAGEOFF]
Lloh531:
	ldr	w9, [x9]
	orr	w1, w8, w9
	ldr	w0, [x20]
	bl	_WREG32_PLL
Lloh532:
	adrp	x20, _RADEON_VCLK_ECP_CNTL@GOTPAGE
Lloh533:
	ldr	x20, [x20, _RADEON_VCLK_ECP_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PLL
Lloh534:
	adrp	x8, _RADEON_PIXCLK_ALWAYS_ONb@GOTPAGE
Lloh535:
	ldr	x8, [x8, _RADEON_PIXCLK_ALWAYS_ONb@GOTPAGEOFF]
Lloh536:
	ldr	w8, [x8]
Lloh537:
	adrp	x9, _RADEON_PIXCLK_DAC_ALWAYS_ONb@GOTPAGE
Lloh538:
	ldr	x9, [x9, _RADEON_PIXCLK_DAC_ALWAYS_ONb@GOTPAGEOFF]
Lloh539:
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w1, w8, w9
	ldr	w0, [x20]
	bl	_WREG32_PLL
Lloh540:
	adrp	x20, _RADEON_PIXCLKS_CNTL@GOTPAGE
Lloh541:
	ldr	x20, [x20, _RADEON_PIXCLKS_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PLL
Lloh542:
	adrp	x8, _RADEON_PIX2CLK_ALWAYS_ONb@GOTPAGE
Lloh543:
	ldr	x8, [x8, _RADEON_PIX2CLK_ALWAYS_ONb@GOTPAGEOFF]
Lloh544:
	ldr	w8, [x8]
Lloh545:
	adrp	x9, _RADEON_PIX2CLK_DAC_ALWAYS_ONb@GOTPAGE
Lloh546:
	ldr	x9, [x9, _RADEON_PIX2CLK_DAC_ALWAYS_ONb@GOTPAGEOFF]
Lloh547:
	ldr	w9, [x9]
Lloh548:
	adrp	x10, _RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb@GOTPAGE
Lloh549:
	ldr	x10, [x10, _RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb@GOTPAGEOFF]
Lloh550:
	ldr	w10, [x10]
Lloh551:
	adrp	x11, _R300_DVOCLK_ALWAYS_ONb@GOTPAGE
Lloh552:
	ldr	x11, [x11, _R300_DVOCLK_ALWAYS_ONb@GOTPAGEOFF]
Lloh553:
	ldr	w11, [x11]
Lloh554:
	adrp	x12, _RADEON_PIXCLK_BLEND_ALWAYS_ONb@GOTPAGE
Lloh555:
	ldr	x12, [x12, _RADEON_PIXCLK_BLEND_ALWAYS_ONb@GOTPAGEOFF]
Lloh556:
	ldr	w12, [x12]
Lloh557:
	adrp	x13, _RADEON_PIXCLK_GV_ALWAYS_ONb@GOTPAGE
Lloh558:
	ldr	x13, [x13, _RADEON_PIXCLK_GV_ALWAYS_ONb@GOTPAGEOFF]
Lloh559:
	ldr	w13, [x13]
Lloh560:
	adrp	x14, _R300_PIXCLK_DVO_ALWAYS_ONb@GOTPAGE
Lloh561:
	ldr	x14, [x14, _R300_PIXCLK_DVO_ALWAYS_ONb@GOTPAGEOFF]
Lloh562:
	ldr	w14, [x14]
Lloh563:
	adrp	x15, _RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPAGE
Lloh564:
	ldr	x15, [x15, _RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPAGEOFF]
Lloh565:
	ldr	w15, [x15]
Lloh566:
	adrp	x16, _RADEON_PIXCLK_TMDS_ALWAYS_ONb@GOTPAGE
Lloh567:
	ldr	x16, [x16, _RADEON_PIXCLK_TMDS_ALWAYS_ONb@GOTPAGEOFF]
Lloh568:
	ldr	w16, [x16]
Lloh569:
	adrp	x17, _R300_PIXCLK_TRANS_ALWAYS_ONb@GOTPAGE
Lloh570:
	ldr	x17, [x17, _R300_PIXCLK_TRANS_ALWAYS_ONb@GOTPAGEOFF]
Lloh571:
	ldr	w17, [x17]
Lloh572:
	adrp	x1, _R300_PIXCLK_TVO_ALWAYS_ONb@GOTPAGE
Lloh573:
	ldr	x1, [x1, _R300_PIXCLK_TVO_ALWAYS_ONb@GOTPAGEOFF]
Lloh574:
	ldr	w1, [x1]
Lloh575:
	adrp	x2, _R300_P2G2CLK_ALWAYS_ONb@GOTPAGE
Lloh576:
	ldr	x2, [x2, _R300_P2G2CLK_ALWAYS_ONb@GOTPAGEOFF]
Lloh577:
	ldr	w2, [x2]
Lloh578:
	adrp	x3, _R300_P2G2CLK_DAC_ALWAYS_ONb@GOTPAGE
Lloh579:
	ldr	x3, [x3, _R300_P2G2CLK_DAC_ALWAYS_ONb@GOTPAGEOFF]
Lloh580:
	ldr	w3, [x3]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w8, w8, w13
	orr	w8, w8, w14
	orr	w8, w8, w15
	orr	w8, w8, w16
	orr	w8, w8, w17
	orr	w8, w8, w1
	orr	w8, w8, w2
	orr	w1, w8, w3
	ldr	w0, [x20]
	bl	_WREG32_PLL
Lloh581:
	adrp	x20, _RADEON_MCLK_MISC@GOTPAGE
Lloh582:
	ldr	x20, [x20, _RADEON_MCLK_MISC@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PLL
Lloh583:
	adrp	x8, _RADEON_MC_MCLK_DYN_ENABLE@GOTPAGE
Lloh584:
	ldr	x8, [x8, _RADEON_MC_MCLK_DYN_ENABLE@GOTPAGEOFF]
Lloh585:
	ldr	w8, [x8]
Lloh586:
	adrp	x9, _RADEON_IO_MCLK_DYN_ENABLE@GOTPAGE
Lloh587:
	ldr	x9, [x9, _RADEON_IO_MCLK_DYN_ENABLE@GOTPAGEOFF]
Lloh588:
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w1, w8, w9
	ldr	w0, [x20]
	bl	_WREG32_PLL
Lloh589:
	adrp	x21, _RADEON_MCLK_CNTL@GOTPAGE
Lloh590:
	ldr	x21, [x21, _RADEON_MCLK_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32_PLL
Lloh591:
	adrp	x8, _RADEON_FORCEON_MCLKA@GOTPAGE
Lloh592:
	ldr	x8, [x8, _RADEON_FORCEON_MCLKA@GOTPAGEOFF]
Lloh593:
	ldr	w8, [x8]
Lloh594:
	adrp	x9, _RADEON_FORCEON_MCLKB@GOTPAGE
Lloh595:
	ldr	x9, [x9, _RADEON_FORCEON_MCLKB@GOTPAGEOFF]
Lloh596:
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w8, w8, w9
Lloh597:
	adrp	x9, _RADEON_FORCEON_YCLKA@GOTPAGE
Lloh598:
	ldr	x9, [x9, _RADEON_FORCEON_YCLKA@GOTPAGEOFF]
Lloh599:
	adrp	x10, _RADEON_FORCEON_YCLKB@GOTPAGE
Lloh600:
	ldr	x10, [x10, _RADEON_FORCEON_YCLKB@GOTPAGEOFF]
Lloh601:
	ldr	w9, [x9]
Lloh602:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh603:
	adrp	x10, _RADEON_FORCEON_MC@GOTPAGE
Lloh604:
	ldr	x10, [x10, _RADEON_FORCEON_MC@GOTPAGEOFF]
Lloh605:
	ldr	w10, [x10]
	orr	w9, w9, w10
	bic	w1, w8, w9
Lloh606:
	adrp	x22, _R300_DISABLE_MC_MCLKA@GOTPAGE
Lloh607:
	ldr	x22, [x22, _R300_DISABLE_MC_MCLKA@GOTPAGEOFF]
	ldr	w8, [x22]
	tst	w1, w8
	b.eq	LBB0_64
; %bb.38:
Lloh608:
	adrp	x23, _R300_DISABLE_MC_MCLKB@GOTPAGE
Lloh609:
	ldr	x23, [x23, _R300_DISABLE_MC_MCLKB@GOTPAGEOFF]
	ldr	w8, [x23]
	tst	w8, w1
	b.eq	LBB0_64
; %bb.39:
	ldr	w0, [x21]
	bl	_RREG32_PLL
	mov	x20, x0
	ldr	w8, [x19, #16]
	cmp	w8, #64
	b.ne	LBB0_61
; %bb.40:
Lloh610:
	adrp	x8, _RADEON_MEM_CNTL@GOTPAGE
Lloh611:
	ldr	x8, [x8, _RADEON_MEM_CNTL@GOTPAGEOFF]
Lloh612:
	ldr	w0, [x8]
	bl	_RREG32
Lloh613:
	adrp	x8, _R300_MEM_USE_CD_CH_ONLY@GOTPAGE
Lloh614:
	ldr	x8, [x8, _R300_MEM_USE_CD_CH_ONLY@GOTPAGEOFF]
Lloh615:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_62
; %bb.41:
	ldr	w8, [x23]
	b	LBB0_63
LBB0_42:
Lloh616:
	adrp	x19, _R300_SCLK_CNTL2@GOTPAGE
Lloh617:
	ldr	x19, [x19, _R300_SCLK_CNTL2@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh618:
	adrp	x8, _R300_SCLK_FORCE_TCL@GOTPAGE
Lloh619:
	ldr	x8, [x8, _R300_SCLK_FORCE_TCL@GOTPAGEOFF]
Lloh620:
	ldr	w8, [x8]
Lloh621:
	adrp	x9, _R300_SCLK_FORCE_GA@GOTPAGE
Lloh622:
	ldr	x9, [x9, _R300_SCLK_FORCE_GA@GOTPAGEOFF]
Lloh623:
	adrp	x10, _R300_SCLK_FORCE_CBA@GOTPAGE
Lloh624:
	ldr	x10, [x10, _R300_SCLK_FORCE_CBA@GOTPAGEOFF]
Lloh625:
	ldr	w9, [x9]
Lloh626:
	ldr	w10, [x10]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w1, w8, w10
	ldr	w0, [x19]
	bl	_WREG32_PLL
Lloh627:
	adrp	x19, _RADEON_SCLK_CNTL@GOTPAGE
Lloh628:
	ldr	x19, [x19, _RADEON_SCLK_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh629:
	adrp	x8, _RADEON_SCLK_FORCE_DISP2@GOTPAGE
Lloh630:
	ldr	x8, [x8, _RADEON_SCLK_FORCE_DISP2@GOTPAGEOFF]
Lloh631:
	ldr	w8, [x8]
Lloh632:
	adrp	x9, _RADEON_SCLK_FORCE_CP@GOTPAGE
Lloh633:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_CP@GOTPAGEOFF]
Lloh634:
	ldr	w9, [x9]
Lloh635:
	adrp	x10, _RADEON_SCLK_FORCE_HDP@GOTPAGE
Lloh636:
	ldr	x10, [x10, _RADEON_SCLK_FORCE_HDP@GOTPAGEOFF]
Lloh637:
	ldr	w10, [x10]
Lloh638:
	adrp	x11, _RADEON_SCLK_FORCE_DISP1@GOTPAGE
Lloh639:
	ldr	x11, [x11, _RADEON_SCLK_FORCE_DISP1@GOTPAGEOFF]
Lloh640:
	ldr	w11, [x11]
Lloh641:
	adrp	x12, _RADEON_SCLK_FORCE_TOP@GOTPAGE
Lloh642:
	ldr	x12, [x12, _RADEON_SCLK_FORCE_TOP@GOTPAGEOFF]
Lloh643:
	ldr	w12, [x12]
Lloh644:
	adrp	x13, _RADEON_SCLK_FORCE_E2@GOTPAGE
Lloh645:
	ldr	x13, [x13, _RADEON_SCLK_FORCE_E2@GOTPAGEOFF]
Lloh646:
	ldr	w13, [x13]
Lloh647:
	adrp	x14, _R300_SCLK_FORCE_VAP@GOTPAGE
Lloh648:
	ldr	x14, [x14, _R300_SCLK_FORCE_VAP@GOTPAGEOFF]
Lloh649:
	ldr	w14, [x14]
Lloh650:
	adrp	x15, _RADEON_SCLK_FORCE_IDCT@GOTPAGE
Lloh651:
	ldr	x15, [x15, _RADEON_SCLK_FORCE_IDCT@GOTPAGEOFF]
Lloh652:
	ldr	w15, [x15]
Lloh653:
	adrp	x16, _RADEON_SCLK_FORCE_VIP@GOTPAGE
Lloh654:
	ldr	x16, [x16, _RADEON_SCLK_FORCE_VIP@GOTPAGEOFF]
Lloh655:
	ldr	w16, [x16]
Lloh656:
	adrp	x17, _R300_SCLK_FORCE_SR@GOTPAGE
Lloh657:
	ldr	x17, [x17, _R300_SCLK_FORCE_SR@GOTPAGEOFF]
Lloh658:
	ldr	w17, [x17]
Lloh659:
	adrp	x1, _R300_SCLK_FORCE_PX@GOTPAGE
Lloh660:
	ldr	x1, [x1, _R300_SCLK_FORCE_PX@GOTPAGEOFF]
Lloh661:
	ldr	w1, [x1]
Lloh662:
	adrp	x2, _R300_SCLK_FORCE_TX@GOTPAGE
Lloh663:
	ldr	x2, [x2, _R300_SCLK_FORCE_TX@GOTPAGEOFF]
Lloh664:
	ldr	w2, [x2]
Lloh665:
	adrp	x3, _R300_SCLK_FORCE_US@GOTPAGE
Lloh666:
	ldr	x3, [x3, _R300_SCLK_FORCE_US@GOTPAGEOFF]
Lloh667:
	ldr	w3, [x3]
Lloh668:
	adrp	x4, _RADEON_SCLK_FORCE_TV_SCLK@GOTPAGE
Lloh669:
	ldr	x4, [x4, _RADEON_SCLK_FORCE_TV_SCLK@GOTPAGEOFF]
Lloh670:
	ldr	w4, [x4]
Lloh671:
	adrp	x5, _R300_SCLK_FORCE_SU@GOTPAGE
Lloh672:
	ldr	x5, [x5, _R300_SCLK_FORCE_SU@GOTPAGEOFF]
Lloh673:
	ldr	w5, [x5]
Lloh674:
	adrp	x6, _RADEON_SCLK_FORCE_OV0@GOTPAGE
Lloh675:
	ldr	x6, [x6, _RADEON_SCLK_FORCE_OV0@GOTPAGEOFF]
Lloh676:
	ldr	w6, [x6]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w8, w8, w13
	orr	w8, w8, w14
	orr	w8, w8, w15
	orr	w8, w8, w16
	orr	w8, w8, w17
	orr	w8, w8, w1
	orr	w8, w8, w2
	orr	w8, w8, w3
	orr	w8, w8, w4
	orr	w8, w8, w5
	orr	w1, w8, w6
	ldr	w0, [x19]
	bl	_WREG32_PLL
Lloh677:
	adrp	x19, _RADEON_SCLK_MORE_CNTL@GOTPAGE
Lloh678:
	ldr	x19, [x19, _RADEON_SCLK_MORE_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh679:
	adrp	x8, _RADEON_SCLK_MORE_FORCEON@GOTPAGE
Lloh680:
	ldr	x8, [x8, _RADEON_SCLK_MORE_FORCEON@GOTPAGEOFF]
Lloh681:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x19]
	bl	_WREG32_PLL
Lloh682:
	adrp	x19, _RADEON_MCLK_CNTL@GOTPAGE
Lloh683:
	ldr	x19, [x19, _RADEON_MCLK_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh684:
	adrp	x8, _RADEON_FORCEON_MCLKA@GOTPAGE
Lloh685:
	ldr	x8, [x8, _RADEON_FORCEON_MCLKA@GOTPAGEOFF]
Lloh686:
	ldr	w8, [x8]
Lloh687:
	adrp	x9, _RADEON_FORCEON_MCLKB@GOTPAGE
Lloh688:
	ldr	x9, [x9, _RADEON_FORCEON_MCLKB@GOTPAGEOFF]
Lloh689:
	ldr	w9, [x9]
Lloh690:
	adrp	x10, _RADEON_FORCEON_YCLKA@GOTPAGE
Lloh691:
	ldr	x10, [x10, _RADEON_FORCEON_YCLKA@GOTPAGEOFF]
Lloh692:
	ldr	w10, [x10]
Lloh693:
	adrp	x11, _RADEON_FORCEON_YCLKB@GOTPAGE
Lloh694:
	ldr	x11, [x11, _RADEON_FORCEON_YCLKB@GOTPAGEOFF]
Lloh695:
	ldr	w11, [x11]
Lloh696:
	adrp	x12, _RADEON_FORCEON_MC@GOTPAGE
Lloh697:
	ldr	x12, [x12, _RADEON_FORCEON_MC@GOTPAGEOFF]
Lloh698:
	ldr	w12, [x12]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w1, w8, w12
LBB0_43:
	ldr	w0, [x19]
	bl	_WREG32_PLL
Lloh699:
	adrp	x19, _RADEON_VCLK_ECP_CNTL@GOTPAGE
Lloh700:
	ldr	x19, [x19, _RADEON_VCLK_ECP_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh701:
	adrp	x8, _RADEON_PIXCLK_ALWAYS_ONb@GOTPAGE
Lloh702:
	ldr	x8, [x8, _RADEON_PIXCLK_ALWAYS_ONb@GOTPAGEOFF]
Lloh703:
	ldr	w8, [x8]
Lloh704:
	adrp	x9, _RADEON_PIXCLK_DAC_ALWAYS_ONb@GOTPAGE
Lloh705:
	ldr	x9, [x9, _RADEON_PIXCLK_DAC_ALWAYS_ONb@GOTPAGEOFF]
Lloh706:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh707:
	adrp	x9, _R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF@GOTPAGE
Lloh708:
	ldr	x9, [x9, _R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF@GOTPAGEOFF]
Lloh709:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w1, w0, w8
	ldr	w0, [x19]
	bl	_WREG32_PLL
Lloh710:
	adrp	x19, _RADEON_PIXCLKS_CNTL@GOTPAGE
Lloh711:
	ldr	x19, [x19, _RADEON_PIXCLKS_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh712:
	adrp	x8, _RADEON_PIX2CLK_ALWAYS_ONb@GOTPAGE
Lloh713:
	ldr	x8, [x8, _RADEON_PIX2CLK_ALWAYS_ONb@GOTPAGEOFF]
Lloh714:
	ldr	w8, [x8]
Lloh715:
	adrp	x9, _RADEON_PIX2CLK_DAC_ALWAYS_ONb@GOTPAGE
Lloh716:
	ldr	x9, [x9, _RADEON_PIX2CLK_DAC_ALWAYS_ONb@GOTPAGEOFF]
Lloh717:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh718:
	adrp	x9, _RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb@GOTPAGE
Lloh719:
	ldr	x9, [x9, _RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb@GOTPAGEOFF]
Lloh720:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh721:
	adrp	x9, _R300_DVOCLK_ALWAYS_ONb@GOTPAGE
Lloh722:
	ldr	x9, [x9, _R300_DVOCLK_ALWAYS_ONb@GOTPAGEOFF]
Lloh723:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh724:
	adrp	x9, _RADEON_PIXCLK_BLEND_ALWAYS_ONb@GOTPAGE
Lloh725:
	ldr	x9, [x9, _RADEON_PIXCLK_BLEND_ALWAYS_ONb@GOTPAGEOFF]
Lloh726:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh727:
	adrp	x9, _RADEON_PIXCLK_GV_ALWAYS_ONb@GOTPAGE
Lloh728:
	ldr	x9, [x9, _RADEON_PIXCLK_GV_ALWAYS_ONb@GOTPAGEOFF]
Lloh729:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh730:
	adrp	x9, _R300_PIXCLK_DVO_ALWAYS_ONb@GOTPAGE
Lloh731:
	ldr	x9, [x9, _R300_PIXCLK_DVO_ALWAYS_ONb@GOTPAGEOFF]
Lloh732:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh733:
	adrp	x9, _RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPAGE
Lloh734:
	ldr	x9, [x9, _RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPAGEOFF]
Lloh735:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh736:
	adrp	x9, _RADEON_PIXCLK_TMDS_ALWAYS_ONb@GOTPAGE
Lloh737:
	ldr	x9, [x9, _RADEON_PIXCLK_TMDS_ALWAYS_ONb@GOTPAGEOFF]
Lloh738:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh739:
	adrp	x9, _R300_PIXCLK_TRANS_ALWAYS_ONb@GOTPAGE
Lloh740:
	ldr	x9, [x9, _R300_PIXCLK_TRANS_ALWAYS_ONb@GOTPAGEOFF]
Lloh741:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh742:
	adrp	x9, _R300_PIXCLK_TVO_ALWAYS_ONb@GOTPAGE
Lloh743:
	ldr	x9, [x9, _R300_PIXCLK_TVO_ALWAYS_ONb@GOTPAGEOFF]
Lloh744:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh745:
	adrp	x9, _R300_P2G2CLK_ALWAYS_ONb@GOTPAGE
Lloh746:
	ldr	x9, [x9, _R300_P2G2CLK_ALWAYS_ONb@GOTPAGEOFF]
Lloh747:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh748:
	adrp	x9, _R300_P2G2CLK_DAC_ALWAYS_ONb@GOTPAGE
Lloh749:
	ldr	x9, [x9, _R300_P2G2CLK_DAC_ALWAYS_ONb@GOTPAGEOFF]
Lloh750:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh751:
	adrp	x9, _R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF@GOTPAGE
Lloh752:
	ldr	x9, [x9, _R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF@GOTPAGEOFF]
LBB0_44:
	ldr	w9, [x9]
	orr	w8, w8, w9
LBB0_45:
	bic	w1, w0, w8
LBB0_46:
	ldr	w0, [x19]
LBB0_47:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_WREG32_PLL
LBB0_48:
	ldr	x8, [x19, #8]
	ldr	x9, [x22]
	cmp	x8, x9
	b.eq	LBB0_50
; %bb.49:
	ldr	x9, [x21]
	cmp	x8, x9
	b.ne	LBB0_51
LBB0_50:
Lloh753:
	adrp	x8, _RADEON_SCLK_FORCE_HDP@GOTPAGE
Lloh754:
	ldr	x8, [x8, _RADEON_SCLK_FORCE_HDP@GOTPAGEOFF]
Lloh755:
	ldr	w8, [x8]
Lloh756:
	adrp	x9, _RADEON_SCLK_FORCE_DISP1@GOTPAGE
Lloh757:
	ldr	x9, [x9, _RADEON_SCLK_FORCE_DISP1@GOTPAGEOFF]
Lloh758:
	ldr	w9, [x9]
Lloh759:
	adrp	x10, _RADEON_SCLK_FORCE_DISP2@GOTPAGE
Lloh760:
	ldr	x10, [x10, _RADEON_SCLK_FORCE_DISP2@GOTPAGEOFF]
Lloh761:
	ldr	w10, [x10]
Lloh762:
	adrp	x11, _RADEON_SCLK_FORCE_TOP@GOTPAGE
Lloh763:
	ldr	x11, [x11, _RADEON_SCLK_FORCE_TOP@GOTPAGEOFF]
Lloh764:
	ldr	w11, [x11]
Lloh765:
	adrp	x12, _RADEON_SCLK_FORCE_IDCT@GOTPAGE
Lloh766:
	ldr	x12, [x12, _RADEON_SCLK_FORCE_IDCT@GOTPAGEOFF]
Lloh767:
	ldr	w12, [x12]
Lloh768:
	adrp	x13, _RADEON_SCLK_FORCE_VIP@GOTPAGE
Lloh769:
	ldr	x13, [x13, _RADEON_SCLK_FORCE_VIP@GOTPAGEOFF]
Lloh770:
	ldr	w13, [x13]
	orr	w8, w8, w1
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w1, w8, w13
LBB0_51:
	ldr	w0, [x20]
	bl	_WREG32_PLL
	mov	w0, #16
	bl	_mdelay
	ldr	x8, [x19, #8]
	ldr	x9, [x22]
	cmp	x8, x9
	b.eq	LBB0_53
; %bb.52:
	ldr	x9, [x21]
	cmp	x8, x9
	b.ne	LBB0_54
LBB0_53:
Lloh771:
	adrp	x20, _R300_SCLK_CNTL2@GOTPAGE
Lloh772:
	ldr	x20, [x20, _R300_SCLK_CNTL2@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PLL
Lloh773:
	adrp	x8, _R300_SCLK_FORCE_TCL@GOTPAGE
Lloh774:
	ldr	x8, [x8, _R300_SCLK_FORCE_TCL@GOTPAGEOFF]
Lloh775:
	ldr	w8, [x8]
Lloh776:
	adrp	x9, _R300_SCLK_FORCE_GA@GOTPAGE
Lloh777:
	ldr	x9, [x9, _R300_SCLK_FORCE_GA@GOTPAGEOFF]
Lloh778:
	adrp	x10, _R300_SCLK_FORCE_CBA@GOTPAGE
Lloh779:
	ldr	x10, [x10, _R300_SCLK_FORCE_CBA@GOTPAGEOFF]
Lloh780:
	ldr	w9, [x9]
Lloh781:
	ldr	w10, [x10]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w1, w8, w10
	ldr	w0, [x20]
	bl	_WREG32_PLL
	mov	w0, #16
	bl	_mdelay
LBB0_54:
	ldr	w8, [x19]
Lloh782:
	adrp	x9, _RADEON_IS_IGP@GOTPAGE
Lloh783:
	ldr	x9, [x9, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh784:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_56
; %bb.55:
Lloh785:
	adrp	x20, _RADEON_MCLK_CNTL@GOTPAGE
Lloh786:
	ldr	x20, [x20, _RADEON_MCLK_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PLL
Lloh787:
	adrp	x8, _RADEON_FORCEON_MCLKA@GOTPAGE
Lloh788:
	ldr	x8, [x8, _RADEON_FORCEON_MCLKA@GOTPAGEOFF]
Lloh789:
	ldr	w8, [x8]
Lloh790:
	adrp	x9, _RADEON_FORCEON_YCLKA@GOTPAGE
Lloh791:
	ldr	x9, [x9, _RADEON_FORCEON_YCLKA@GOTPAGEOFF]
Lloh792:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32_PLL
	mov	w0, #16
	bl	_mdelay
LBB0_56:
	ldr	x8, [x19, #8]
Lloh793:
	adrp	x9, _CHIP_RV200@GOTPAGE
Lloh794:
	ldr	x9, [x9, _CHIP_RV200@GOTPAGEOFF]
Lloh795:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_59
; %bb.57:
Lloh796:
	adrp	x9, _CHIP_RV250@GOTPAGE
Lloh797:
	ldr	x9, [x9, _CHIP_RV250@GOTPAGEOFF]
Lloh798:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_59
; %bb.58:
Lloh799:
	adrp	x9, _CHIP_RV280@GOTPAGE
Lloh800:
	ldr	x9, [x9, _CHIP_RV280@GOTPAGEOFF]
Lloh801:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_60
LBB0_59:
Lloh802:
	adrp	x19, _RADEON_SCLK_MORE_CNTL@GOTPAGE
Lloh803:
	ldr	x19, [x19, _RADEON_SCLK_MORE_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh804:
	adrp	x8, _RADEON_SCLK_MORE_FORCEON@GOTPAGE
Lloh805:
	ldr	x8, [x8, _RADEON_SCLK_MORE_FORCEON@GOTPAGEOFF]
Lloh806:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x19]
	bl	_WREG32_PLL
	mov	w0, #16
	bl	_mdelay
LBB0_60:
Lloh807:
	adrp	x19, _RADEON_PIXCLKS_CNTL@GOTPAGE
Lloh808:
	ldr	x19, [x19, _RADEON_PIXCLKS_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh809:
	adrp	x8, _RADEON_PIX2CLK_ALWAYS_ONb@GOTPAGE
Lloh810:
	ldr	x8, [x8, _RADEON_PIX2CLK_ALWAYS_ONb@GOTPAGEOFF]
Lloh811:
	ldr	w8, [x8]
Lloh812:
	adrp	x9, _RADEON_PIX2CLK_DAC_ALWAYS_ONb@GOTPAGE
Lloh813:
	ldr	x9, [x9, _RADEON_PIX2CLK_DAC_ALWAYS_ONb@GOTPAGEOFF]
Lloh814:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh815:
	adrp	x9, _RADEON_PIXCLK_BLEND_ALWAYS_ONb@GOTPAGE
Lloh816:
	ldr	x9, [x9, _RADEON_PIXCLK_BLEND_ALWAYS_ONb@GOTPAGEOFF]
Lloh817:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh818:
	adrp	x9, _RADEON_PIXCLK_GV_ALWAYS_ONb@GOTPAGE
Lloh819:
	ldr	x9, [x9, _RADEON_PIXCLK_GV_ALWAYS_ONb@GOTPAGEOFF]
Lloh820:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh821:
	adrp	x9, _RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb@GOTPAGE
Lloh822:
	ldr	x9, [x9, _RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb@GOTPAGEOFF]
Lloh823:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh824:
	adrp	x9, _RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPAGE
Lloh825:
	ldr	x9, [x9, _RADEON_PIXCLK_LVDS_ALWAYS_ONb@GOTPAGEOFF]
Lloh826:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh827:
	adrp	x9, _RADEON_PIXCLK_TMDS_ALWAYS_ONb@GOTPAGE
Lloh828:
	ldr	x9, [x9, _RADEON_PIXCLK_TMDS_ALWAYS_ONb@GOTPAGEOFF]
Lloh829:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w1, w0, w8
	ldr	w0, [x19]
	bl	_WREG32_PLL
	mov	w0, #16
	bl	_mdelay
Lloh830:
	adrp	x19, _RADEON_VCLK_ECP_CNTL@GOTPAGE
Lloh831:
	ldr	x19, [x19, _RADEON_VCLK_ECP_CNTL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_PLL
Lloh832:
	adrp	x8, _RADEON_PIXCLK_ALWAYS_ONb@GOTPAGE
Lloh833:
	ldr	x8, [x8, _RADEON_PIXCLK_ALWAYS_ONb@GOTPAGEOFF]
Lloh834:
	ldr	w8, [x8]
Lloh835:
	adrp	x9, _RADEON_PIXCLK_DAC_ALWAYS_ONb@GOTPAGE
Lloh836:
	ldr	x9, [x9, _RADEON_PIXCLK_DAC_ALWAYS_ONb@GOTPAGEOFF]
Lloh837:
	ldr	w9, [x9]
	orr	w8, w9, w8
	b	LBB0_45
LBB0_61:
	ldr	w8, [x22]
	ldr	w9, [x23]
	orr	w8, w9, w8
	b	LBB0_63
LBB0_62:
	ldr	w8, [x22]
LBB0_63:
	bic	w1, w20, w8
LBB0_64:
	ldr	w0, [x21]
	b	LBB0_47
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh83, Lloh84
	.loh AdrpLdrGot	Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh79
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh73
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh67
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh61
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh55
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGot	Lloh197, Lloh198
	.loh AdrpLdrGot	Lloh195, Lloh196
	.loh AdrpLdrGotLdr	Lloh191, Lloh192, Lloh194
	.loh AdrpLdrGotLdr	Lloh189, Lloh190, Lloh193
	.loh AdrpLdrGotLdr	Lloh185, Lloh186, Lloh188
	.loh AdrpLdrGotLdr	Lloh183, Lloh184, Lloh187
	.loh AdrpLdrGotLdr	Lloh179, Lloh180, Lloh182
	.loh AdrpLdrGotLdr	Lloh177, Lloh178, Lloh181
	.loh AdrpLdrGotLdr	Lloh173, Lloh174, Lloh176
	.loh AdrpLdrGotLdr	Lloh171, Lloh172, Lloh175
	.loh AdrpLdrGotLdr	Lloh167, Lloh168, Lloh170
	.loh AdrpLdrGotLdr	Lloh165, Lloh166, Lloh169
	.loh AdrpLdrGotLdr	Lloh162, Lloh163, Lloh164
	.loh AdrpLdrGot	Lloh160, Lloh161
	.loh AdrpLdrGotLdr	Lloh157, Lloh158, Lloh159
	.loh AdrpLdrGotLdr	Lloh154, Lloh155, Lloh156
	.loh AdrpLdrGot	Lloh152, Lloh153
	.loh AdrpLdrGotLdr	Lloh149, Lloh150, Lloh151
	.loh AdrpLdrGotLdr	Lloh146, Lloh147, Lloh148
	.loh AdrpLdrGot	Lloh144, Lloh145
	.loh AdrpLdrGotLdr	Lloh141, Lloh142, Lloh143
	.loh AdrpLdrGotLdr	Lloh138, Lloh139, Lloh140
	.loh AdrpLdrGotLdr	Lloh135, Lloh136, Lloh137
	.loh AdrpLdrGotLdr	Lloh132, Lloh133, Lloh134
	.loh AdrpLdrGotLdr	Lloh129, Lloh130, Lloh131
	.loh AdrpLdrGotLdr	Lloh126, Lloh127, Lloh128
	.loh AdrpLdrGotLdr	Lloh123, Lloh124, Lloh125
	.loh AdrpLdrGotLdr	Lloh120, Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGot	Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh202, Lloh203, Lloh204
	.loh AdrpLdrGotLdr	Lloh199, Lloh200, Lloh201
	.loh AdrpLdrGotLdr	Lloh257, Lloh258, Lloh259
	.loh AdrpLdrGot	Lloh255, Lloh256
	.loh AdrpLdrGotLdr	Lloh252, Lloh253, Lloh254
	.loh AdrpLdrGotLdr	Lloh249, Lloh250, Lloh251
	.loh AdrpLdrGotLdr	Lloh246, Lloh247, Lloh248
	.loh AdrpLdrGotLdr	Lloh243, Lloh244, Lloh245
	.loh AdrpLdrGotLdr	Lloh240, Lloh241, Lloh242
	.loh AdrpLdrGotLdr	Lloh237, Lloh238, Lloh239
	.loh AdrpLdrGotLdr	Lloh234, Lloh235, Lloh236
	.loh AdrpLdrGotLdr	Lloh231, Lloh232, Lloh233
	.loh AdrpLdrGotLdr	Lloh228, Lloh229, Lloh230
	.loh AdrpLdrGotLdr	Lloh225, Lloh226, Lloh227
	.loh AdrpLdrGotLdr	Lloh222, Lloh223, Lloh224
	.loh AdrpLdrGotLdr	Lloh219, Lloh220, Lloh221
	.loh AdrpLdrGotLdr	Lloh216, Lloh217, Lloh218
	.loh AdrpLdrGotLdr	Lloh213, Lloh214, Lloh215
	.loh AdrpLdrGotLdr	Lloh210, Lloh211, Lloh212
	.loh AdrpLdrGotLdr	Lloh207, Lloh208, Lloh209
	.loh AdrpLdrGot	Lloh205, Lloh206
	.loh AdrpLdrGot	Lloh287, Lloh288
	.loh AdrpLdrGotLdr	Lloh284, Lloh285, Lloh286
	.loh AdrpLdrGot	Lloh282, Lloh283
	.loh AdrpLdrGotLdr	Lloh279, Lloh280, Lloh281
	.loh AdrpLdrGot	Lloh277, Lloh278
	.loh AdrpLdrGotLdr	Lloh274, Lloh275, Lloh276
	.loh AdrpLdrGotLdr	Lloh271, Lloh272, Lloh273
	.loh AdrpLdrGotLdr	Lloh268, Lloh269, Lloh270
	.loh AdrpLdrGotLdr	Lloh265, Lloh266, Lloh267
	.loh AdrpLdrGotLdr	Lloh262, Lloh263, Lloh264
	.loh AdrpLdrGot	Lloh260, Lloh261
	.loh AdrpLdrGotLdr	Lloh295, Lloh296, Lloh297
	.loh AdrpLdrGotLdr	Lloh292, Lloh293, Lloh294
	.loh AdrpLdrGotLdr	Lloh289, Lloh290, Lloh291
	.loh AdrpLdrGotLdr	Lloh298, Lloh299, Lloh300
	.loh AdrpLdrGotLdr	Lloh307, Lloh308, Lloh309
	.loh AdrpLdrGotLdr	Lloh304, Lloh305, Lloh306
	.loh AdrpLdrGotLdr	Lloh301, Lloh302, Lloh303
	.loh AdrpLdrGotLdr	Lloh313, Lloh314, Lloh315
	.loh AdrpLdrGotLdr	Lloh310, Lloh311, Lloh312
	.loh AdrpLdrGot	Lloh316, Lloh317
	.loh AdrpLdrGotLdr	Lloh318, Lloh319, Lloh320
	.loh AdrpLdrGot	Lloh323, Lloh324
	.loh AdrpLdrGot	Lloh321, Lloh322
	.loh AdrpLdrGotLdr	Lloh331, Lloh332, Lloh333
	.loh AdrpLdrGotLdr	Lloh328, Lloh329, Lloh330
	.loh AdrpLdrGotLdr	Lloh325, Lloh326, Lloh327
	.loh AdrpLdrGotLdr	Lloh340, Lloh341, Lloh342
	.loh AdrpLdrGotLdr	Lloh337, Lloh338, Lloh339
	.loh AdrpLdrGotLdr	Lloh334, Lloh335, Lloh336
	.loh AdrpLdrGotLdr	Lloh345, Lloh346, Lloh347
	.loh AdrpLdrGot	Lloh343, Lloh344
	.loh AdrpLdrGotLdr	Lloh376, Lloh377, Lloh378
	.loh AdrpLdrGotLdr	Lloh373, Lloh374, Lloh375
	.loh AdrpLdrGot	Lloh371, Lloh372
	.loh AdrpLdrGotLdr	Lloh368, Lloh369, Lloh370
	.loh AdrpLdrGotLdr	Lloh365, Lloh366, Lloh367
	.loh AdrpLdrGotLdr	Lloh362, Lloh363, Lloh364
	.loh AdrpLdrGotLdr	Lloh359, Lloh360, Lloh361
	.loh AdrpLdrGotLdr	Lloh356, Lloh357, Lloh358
	.loh AdrpLdrGotLdr	Lloh353, Lloh354, Lloh355
	.loh AdrpLdrGotLdr	Lloh350, Lloh351, Lloh352
	.loh AdrpLdrGot	Lloh348, Lloh349
	.loh AdrpLdrGotLdr	Lloh379, Lloh380, Lloh381
	.loh AdrpLdrGot	Lloh398, Lloh399
	.loh AdrpLdrGotLdr	Lloh395, Lloh396, Lloh397
	.loh AdrpLdrGotLdr	Lloh392, Lloh393, Lloh394
	.loh AdrpLdrGot	Lloh390, Lloh391
	.loh AdrpLdrGotLdr	Lloh387, Lloh388, Lloh389
	.loh AdrpLdrGotLdr	Lloh384, Lloh385, Lloh386
	.loh AdrpLdrGot	Lloh382, Lloh383
	.loh AdrpLdrGotLdr	Lloh400, Lloh401, Lloh402
	.loh AdrpLdrGot	Lloh416, Lloh417
	.loh AdrpLdrGot	Lloh414, Lloh415
	.loh AdrpLdrGotLdr	Lloh410, Lloh411, Lloh413
	.loh AdrpLdrGotLdr	Lloh408, Lloh409, Lloh412
	.loh AdrpLdrGotLdr	Lloh405, Lloh406, Lloh407
	.loh AdrpLdrGot	Lloh403, Lloh404
	.loh AdrpLdrGotLdr	Lloh448, Lloh449, Lloh450
	.loh AdrpLdrGotLdr	Lloh445, Lloh446, Lloh447
	.loh AdrpLdrGotLdr	Lloh442, Lloh443, Lloh444
	.loh AdrpLdrGotLdr	Lloh439, Lloh440, Lloh441
	.loh AdrpLdrGotLdr	Lloh436, Lloh437, Lloh438
	.loh AdrpLdrGotLdr	Lloh433, Lloh434, Lloh435
	.loh AdrpLdrGotLdr	Lloh430, Lloh431, Lloh432
	.loh AdrpLdrGotLdr	Lloh427, Lloh428, Lloh429
	.loh AdrpLdrGotLdr	Lloh424, Lloh425, Lloh426
	.loh AdrpLdrGotLdr	Lloh421, Lloh422, Lloh423
	.loh AdrpLdrGotLdr	Lloh418, Lloh419, Lloh420
	.loh AdrpLdrGot	Lloh606, Lloh607
	.loh AdrpLdrGotLdr	Lloh603, Lloh604, Lloh605
	.loh AdrpLdrGotLdr	Lloh599, Lloh600, Lloh602
	.loh AdrpLdrGotLdr	Lloh597, Lloh598, Lloh601
	.loh AdrpLdrGotLdr	Lloh594, Lloh595, Lloh596
	.loh AdrpLdrGotLdr	Lloh591, Lloh592, Lloh593
	.loh AdrpLdrGot	Lloh589, Lloh590
	.loh AdrpLdrGotLdr	Lloh586, Lloh587, Lloh588
	.loh AdrpLdrGotLdr	Lloh583, Lloh584, Lloh585
	.loh AdrpLdrGot	Lloh581, Lloh582
	.loh AdrpLdrGotLdr	Lloh578, Lloh579, Lloh580
	.loh AdrpLdrGotLdr	Lloh575, Lloh576, Lloh577
	.loh AdrpLdrGotLdr	Lloh572, Lloh573, Lloh574
	.loh AdrpLdrGotLdr	Lloh569, Lloh570, Lloh571
	.loh AdrpLdrGotLdr	Lloh566, Lloh567, Lloh568
	.loh AdrpLdrGotLdr	Lloh563, Lloh564, Lloh565
	.loh AdrpLdrGotLdr	Lloh560, Lloh561, Lloh562
	.loh AdrpLdrGotLdr	Lloh557, Lloh558, Lloh559
	.loh AdrpLdrGotLdr	Lloh554, Lloh555, Lloh556
	.loh AdrpLdrGotLdr	Lloh551, Lloh552, Lloh553
	.loh AdrpLdrGotLdr	Lloh548, Lloh549, Lloh550
	.loh AdrpLdrGotLdr	Lloh545, Lloh546, Lloh547
	.loh AdrpLdrGotLdr	Lloh542, Lloh543, Lloh544
	.loh AdrpLdrGot	Lloh540, Lloh541
	.loh AdrpLdrGotLdr	Lloh537, Lloh538, Lloh539
	.loh AdrpLdrGotLdr	Lloh534, Lloh535, Lloh536
	.loh AdrpLdrGot	Lloh532, Lloh533
	.loh AdrpLdrGotLdr	Lloh529, Lloh530, Lloh531
	.loh AdrpLdrGotLdr	Lloh526, Lloh527, Lloh528
	.loh AdrpLdrGot	Lloh524, Lloh525
	.loh AdrpLdrGotLdr	Lloh521, Lloh522, Lloh523
	.loh AdrpLdrGotLdr	Lloh518, Lloh519, Lloh520
	.loh AdrpLdrGotLdr	Lloh515, Lloh516, Lloh517
	.loh AdrpLdrGotLdr	Lloh512, Lloh513, Lloh514
	.loh AdrpLdrGotLdr	Lloh509, Lloh510, Lloh511
	.loh AdrpLdrGotLdr	Lloh506, Lloh507, Lloh508
	.loh AdrpLdrGotLdr	Lloh503, Lloh504, Lloh505
	.loh AdrpLdrGotLdr	Lloh500, Lloh501, Lloh502
	.loh AdrpLdrGotLdr	Lloh497, Lloh498, Lloh499
	.loh AdrpLdrGotLdr	Lloh494, Lloh495, Lloh496
	.loh AdrpLdrGotLdr	Lloh491, Lloh492, Lloh493
	.loh AdrpLdrGotLdr	Lloh488, Lloh489, Lloh490
	.loh AdrpLdrGotLdr	Lloh485, Lloh486, Lloh487
	.loh AdrpLdrGotLdr	Lloh482, Lloh483, Lloh484
	.loh AdrpLdrGotLdr	Lloh479, Lloh480, Lloh481
	.loh AdrpLdrGotLdr	Lloh476, Lloh477, Lloh478
	.loh AdrpLdrGotLdr	Lloh473, Lloh474, Lloh475
	.loh AdrpLdrGot	Lloh471, Lloh472
	.loh AdrpLdrGotLdr	Lloh468, Lloh469, Lloh470
	.loh AdrpLdrGotLdr	Lloh465, Lloh466, Lloh467
	.loh AdrpLdrGotLdr	Lloh462, Lloh463, Lloh464
	.loh AdrpLdrGotLdr	Lloh459, Lloh460, Lloh461
	.loh AdrpLdrGotLdr	Lloh456, Lloh457, Lloh458
	.loh AdrpLdrGotLdr	Lloh453, Lloh454, Lloh455
	.loh AdrpLdrGot	Lloh451, Lloh452
	.loh AdrpLdrGot	Lloh608, Lloh609
	.loh AdrpLdrGotLdr	Lloh613, Lloh614, Lloh615
	.loh AdrpLdrGotLdr	Lloh610, Lloh611, Lloh612
	.loh AdrpLdrGotLdr	Lloh696, Lloh697, Lloh698
	.loh AdrpLdrGotLdr	Lloh693, Lloh694, Lloh695
	.loh AdrpLdrGotLdr	Lloh690, Lloh691, Lloh692
	.loh AdrpLdrGotLdr	Lloh687, Lloh688, Lloh689
	.loh AdrpLdrGotLdr	Lloh684, Lloh685, Lloh686
	.loh AdrpLdrGot	Lloh682, Lloh683
	.loh AdrpLdrGotLdr	Lloh679, Lloh680, Lloh681
	.loh AdrpLdrGot	Lloh677, Lloh678
	.loh AdrpLdrGotLdr	Lloh674, Lloh675, Lloh676
	.loh AdrpLdrGotLdr	Lloh671, Lloh672, Lloh673
	.loh AdrpLdrGotLdr	Lloh668, Lloh669, Lloh670
	.loh AdrpLdrGotLdr	Lloh665, Lloh666, Lloh667
	.loh AdrpLdrGotLdr	Lloh662, Lloh663, Lloh664
	.loh AdrpLdrGotLdr	Lloh659, Lloh660, Lloh661
	.loh AdrpLdrGotLdr	Lloh656, Lloh657, Lloh658
	.loh AdrpLdrGotLdr	Lloh653, Lloh654, Lloh655
	.loh AdrpLdrGotLdr	Lloh650, Lloh651, Lloh652
	.loh AdrpLdrGotLdr	Lloh647, Lloh648, Lloh649
	.loh AdrpLdrGotLdr	Lloh644, Lloh645, Lloh646
	.loh AdrpLdrGotLdr	Lloh641, Lloh642, Lloh643
	.loh AdrpLdrGotLdr	Lloh638, Lloh639, Lloh640
	.loh AdrpLdrGotLdr	Lloh635, Lloh636, Lloh637
	.loh AdrpLdrGotLdr	Lloh632, Lloh633, Lloh634
	.loh AdrpLdrGotLdr	Lloh629, Lloh630, Lloh631
	.loh AdrpLdrGot	Lloh627, Lloh628
	.loh AdrpLdrGotLdr	Lloh623, Lloh624, Lloh626
	.loh AdrpLdrGotLdr	Lloh621, Lloh622, Lloh625
	.loh AdrpLdrGotLdr	Lloh618, Lloh619, Lloh620
	.loh AdrpLdrGot	Lloh616, Lloh617
	.loh AdrpLdrGot	Lloh751, Lloh752
	.loh AdrpLdrGotLdr	Lloh748, Lloh749, Lloh750
	.loh AdrpLdrGotLdr	Lloh745, Lloh746, Lloh747
	.loh AdrpLdrGotLdr	Lloh742, Lloh743, Lloh744
	.loh AdrpLdrGotLdr	Lloh739, Lloh740, Lloh741
	.loh AdrpLdrGotLdr	Lloh736, Lloh737, Lloh738
	.loh AdrpLdrGotLdr	Lloh733, Lloh734, Lloh735
	.loh AdrpLdrGotLdr	Lloh730, Lloh731, Lloh732
	.loh AdrpLdrGotLdr	Lloh727, Lloh728, Lloh729
	.loh AdrpLdrGotLdr	Lloh724, Lloh725, Lloh726
	.loh AdrpLdrGotLdr	Lloh721, Lloh722, Lloh723
	.loh AdrpLdrGotLdr	Lloh718, Lloh719, Lloh720
	.loh AdrpLdrGotLdr	Lloh715, Lloh716, Lloh717
	.loh AdrpLdrGotLdr	Lloh712, Lloh713, Lloh714
	.loh AdrpLdrGot	Lloh710, Lloh711
	.loh AdrpLdrGotLdr	Lloh707, Lloh708, Lloh709
	.loh AdrpLdrGotLdr	Lloh704, Lloh705, Lloh706
	.loh AdrpLdrGotLdr	Lloh701, Lloh702, Lloh703
	.loh AdrpLdrGot	Lloh699, Lloh700
	.loh AdrpLdrGotLdr	Lloh768, Lloh769, Lloh770
	.loh AdrpLdrGotLdr	Lloh765, Lloh766, Lloh767
	.loh AdrpLdrGotLdr	Lloh762, Lloh763, Lloh764
	.loh AdrpLdrGotLdr	Lloh759, Lloh760, Lloh761
	.loh AdrpLdrGotLdr	Lloh756, Lloh757, Lloh758
	.loh AdrpLdrGotLdr	Lloh753, Lloh754, Lloh755
	.loh AdrpLdrGotLdr	Lloh778, Lloh779, Lloh781
	.loh AdrpLdrGotLdr	Lloh776, Lloh777, Lloh780
	.loh AdrpLdrGotLdr	Lloh773, Lloh774, Lloh775
	.loh AdrpLdrGot	Lloh771, Lloh772
	.loh AdrpLdrGotLdr	Lloh782, Lloh783, Lloh784
	.loh AdrpLdrGotLdr	Lloh790, Lloh791, Lloh792
	.loh AdrpLdrGotLdr	Lloh787, Lloh788, Lloh789
	.loh AdrpLdrGot	Lloh785, Lloh786
	.loh AdrpLdrGotLdr	Lloh793, Lloh794, Lloh795
	.loh AdrpLdrGotLdr	Lloh796, Lloh797, Lloh798
	.loh AdrpLdrGotLdr	Lloh799, Lloh800, Lloh801
	.loh AdrpLdrGotLdr	Lloh804, Lloh805, Lloh806
	.loh AdrpLdrGot	Lloh802, Lloh803
	.loh AdrpLdrGotLdr	Lloh835, Lloh836, Lloh837
	.loh AdrpLdrGotLdr	Lloh832, Lloh833, Lloh834
	.loh AdrpLdrGot	Lloh830, Lloh831
	.loh AdrpLdrGotLdr	Lloh827, Lloh828, Lloh829
	.loh AdrpLdrGotLdr	Lloh824, Lloh825, Lloh826
	.loh AdrpLdrGotLdr	Lloh821, Lloh822, Lloh823
	.loh AdrpLdrGotLdr	Lloh818, Lloh819, Lloh820
	.loh AdrpLdrGotLdr	Lloh815, Lloh816, Lloh817
	.loh AdrpLdrGotLdr	Lloh812, Lloh813, Lloh814
	.loh AdrpLdrGotLdr	Lloh809, Lloh810, Lloh811
	.loh AdrpLdrGot	Lloh807, Lloh808
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_SINGLE_CRTC,4,2         ; @RADEON_SINGLE_CRTC
	.comm	_RADEON_SCLK_CNTL,4,2           ; @RADEON_SCLK_CNTL
	.comm	_RADEON_CONFIG_CNTL,4,2         ; @RADEON_CONFIG_CNTL
	.comm	_RADEON_CFG_ATI_REV_ID_MASK,4,2 ; @RADEON_CFG_ATI_REV_ID_MASK
	.comm	_RADEON_CFG_ATI_REV_A13,4,2     ; @RADEON_CFG_ATI_REV_A13
	.comm	_RADEON_SCLK_FORCE_CP,4,2       ; @RADEON_SCLK_FORCE_CP
	.comm	_RADEON_SCLK_FORCE_RB,4,2       ; @RADEON_SCLK_FORCE_RB
	.comm	_RADEON_SCLK_FORCE_HDP,4,2      ; @RADEON_SCLK_FORCE_HDP
	.comm	_RADEON_SCLK_FORCE_DISP1,4,2    ; @RADEON_SCLK_FORCE_DISP1
	.comm	_RADEON_SCLK_FORCE_TOP,4,2      ; @RADEON_SCLK_FORCE_TOP
	.comm	_RADEON_SCLK_FORCE_SE,4,2       ; @RADEON_SCLK_FORCE_SE
	.comm	_RADEON_SCLK_FORCE_IDCT,4,2     ; @RADEON_SCLK_FORCE_IDCT
	.comm	_RADEON_SCLK_FORCE_RE,4,2       ; @RADEON_SCLK_FORCE_RE
	.comm	_RADEON_SCLK_FORCE_PB,4,2       ; @RADEON_SCLK_FORCE_PB
	.comm	_RADEON_SCLK_FORCE_TAM,4,2      ; @RADEON_SCLK_FORCE_TAM
	.comm	_RADEON_SCLK_FORCE_TDM,4,2      ; @RADEON_SCLK_FORCE_TDM
	.comm	_CHIP_RS400,8,3                 ; @CHIP_RS400
	.comm	_CHIP_RS480,8,3                 ; @CHIP_RS480
	.comm	_RADEON_SCLK_FORCE_DISP2,4,2    ; @RADEON_SCLK_FORCE_DISP2
	.comm	_RADEON_SCLK_FORCE_E2,4,2       ; @RADEON_SCLK_FORCE_E2
	.comm	_R300_SCLK_FORCE_VAP,4,2        ; @R300_SCLK_FORCE_VAP
	.comm	_RADEON_SCLK_FORCE_VIP,4,2      ; @RADEON_SCLK_FORCE_VIP
	.comm	_R300_SCLK_FORCE_SR,4,2         ; @R300_SCLK_FORCE_SR
	.comm	_R300_SCLK_FORCE_PX,4,2         ; @R300_SCLK_FORCE_PX
	.comm	_R300_SCLK_FORCE_TX,4,2         ; @R300_SCLK_FORCE_TX
	.comm	_R300_SCLK_FORCE_US,4,2         ; @R300_SCLK_FORCE_US
	.comm	_RADEON_SCLK_FORCE_TV_SCLK,4,2  ; @RADEON_SCLK_FORCE_TV_SCLK
	.comm	_R300_SCLK_FORCE_SU,4,2         ; @R300_SCLK_FORCE_SU
	.comm	_RADEON_SCLK_FORCE_OV0,4,2      ; @RADEON_SCLK_FORCE_OV0
	.comm	_RADEON_DYN_STOP_LAT_MASK,4,2   ; @RADEON_DYN_STOP_LAT_MASK
	.comm	_RADEON_SCLK_MORE_CNTL,4,2      ; @RADEON_SCLK_MORE_CNTL
	.comm	_RADEON_SCLK_MORE_FORCEON,4,2   ; @RADEON_SCLK_MORE_FORCEON
	.comm	_RADEON_SCLK_MORE_MAX_DYN_STOP_LAT,4,2 ; @RADEON_SCLK_MORE_MAX_DYN_STOP_LAT
	.comm	_RADEON_VCLK_ECP_CNTL,4,2       ; @RADEON_VCLK_ECP_CNTL
	.comm	_RADEON_PIXCLK_ALWAYS_ONb,4,2   ; @RADEON_PIXCLK_ALWAYS_ONb
	.comm	_RADEON_PIXCLK_DAC_ALWAYS_ONb,4,2 ; @RADEON_PIXCLK_DAC_ALWAYS_ONb
	.comm	_RADEON_PIXCLKS_CNTL,4,2        ; @RADEON_PIXCLKS_CNTL
	.comm	_RADEON_PIX2CLK_ALWAYS_ONb,4,2  ; @RADEON_PIX2CLK_ALWAYS_ONb
	.comm	_RADEON_PIX2CLK_DAC_ALWAYS_ONb,4,2 ; @RADEON_PIX2CLK_DAC_ALWAYS_ONb
	.comm	_RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb,4,2 ; @RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb
	.comm	_R300_DVOCLK_ALWAYS_ONb,4,2     ; @R300_DVOCLK_ALWAYS_ONb
	.comm	_RADEON_PIXCLK_BLEND_ALWAYS_ONb,4,2 ; @RADEON_PIXCLK_BLEND_ALWAYS_ONb
	.comm	_RADEON_PIXCLK_GV_ALWAYS_ONb,4,2 ; @RADEON_PIXCLK_GV_ALWAYS_ONb
	.comm	_R300_PIXCLK_DVO_ALWAYS_ONb,4,2 ; @R300_PIXCLK_DVO_ALWAYS_ONb
	.comm	_RADEON_PIXCLK_LVDS_ALWAYS_ONb,4,2 ; @RADEON_PIXCLK_LVDS_ALWAYS_ONb
	.comm	_RADEON_PIXCLK_TMDS_ALWAYS_ONb,4,2 ; @RADEON_PIXCLK_TMDS_ALWAYS_ONb
	.comm	_R300_PIXCLK_TRANS_ALWAYS_ONb,4,2 ; @R300_PIXCLK_TRANS_ALWAYS_ONb
	.comm	_R300_PIXCLK_TVO_ALWAYS_ONb,4,2 ; @R300_PIXCLK_TVO_ALWAYS_ONb
	.comm	_R300_P2G2CLK_ALWAYS_ONb,4,2    ; @R300_P2G2CLK_ALWAYS_ONb
	.comm	_R300_P2G2CLK_DAC_ALWAYS_ONb,4,2 ; @R300_P2G2CLK_DAC_ALWAYS_ONb
	.comm	_CHIP_RV350,8,3                 ; @CHIP_RV350
	.comm	_R300_SCLK_CNTL2,4,2            ; @R300_SCLK_CNTL2
	.comm	_R300_SCLK_FORCE_TCL,4,2        ; @R300_SCLK_FORCE_TCL
	.comm	_R300_SCLK_FORCE_GA,4,2         ; @R300_SCLK_FORCE_GA
	.comm	_R300_SCLK_FORCE_CBA,4,2        ; @R300_SCLK_FORCE_CBA
	.comm	_R300_SCLK_TCL_MAX_DYN_STOP_LAT,4,2 ; @R300_SCLK_TCL_MAX_DYN_STOP_LAT
	.comm	_R300_SCLK_GA_MAX_DYN_STOP_LAT,4,2 ; @R300_SCLK_GA_MAX_DYN_STOP_LAT
	.comm	_R300_SCLK_CBA_MAX_DYN_STOP_LAT,4,2 ; @R300_SCLK_CBA_MAX_DYN_STOP_LAT
	.comm	_RADEON_MCLK_MISC,4,2           ; @RADEON_MCLK_MISC
	.comm	_RADEON_MC_MCLK_DYN_ENABLE,4,2  ; @RADEON_MC_MCLK_DYN_ENABLE
	.comm	_RADEON_IO_MCLK_DYN_ENABLE,4,2  ; @RADEON_IO_MCLK_DYN_ENABLE
	.comm	_RADEON_MCLK_CNTL,4,2           ; @RADEON_MCLK_CNTL
	.comm	_RADEON_FORCEON_MCLKA,4,2       ; @RADEON_FORCEON_MCLKA
	.comm	_RADEON_FORCEON_MCLKB,4,2       ; @RADEON_FORCEON_MCLKB
	.comm	_RADEON_FORCEON_YCLKA,4,2       ; @RADEON_FORCEON_YCLKA
	.comm	_RADEON_FORCEON_YCLKB,4,2       ; @RADEON_FORCEON_YCLKB
	.comm	_RADEON_FORCEON_MC,4,2          ; @RADEON_FORCEON_MC
	.comm	_R300_DISABLE_MC_MCLKA,4,2      ; @R300_DISABLE_MC_MCLKA
	.comm	_R300_DISABLE_MC_MCLKB,4,2      ; @R300_DISABLE_MC_MCLKB
	.comm	_RADEON_MEM_CNTL,4,2            ; @RADEON_MEM_CNTL
	.comm	_R300_MEM_USE_CD_CH_ONLY,4,2    ; @R300_MEM_USE_CD_CH_ONLY
	.comm	_RADEON_CLK_PWRMGT_CNTL,4,2     ; @RADEON_CLK_PWRMGT_CNTL
	.comm	_RADEON_ACTIVE_HILO_LAT_MASK,4,2 ; @RADEON_ACTIVE_HILO_LAT_MASK
	.comm	_RADEON_DISP_DYN_STOP_LAT_MASK,4,2 ; @RADEON_DISP_DYN_STOP_LAT_MASK
	.comm	_RADEON_DYN_STOP_MODE_MASK,4,2  ; @RADEON_DYN_STOP_MODE_MASK
	.comm	_RADEON_ENGIN_DYNCLK_MODE,4,2   ; @RADEON_ENGIN_DYNCLK_MODE
	.comm	_RADEON_ACTIVE_HILO_LAT_SHIFT,4,2 ; @RADEON_ACTIVE_HILO_LAT_SHIFT
	.comm	_RADEON_CLK_PIN_CNTL,4,2        ; @RADEON_CLK_PIN_CNTL
	.comm	_RADEON_SCLK_DYN_START_CNTL,4,2 ; @RADEON_SCLK_DYN_START_CNTL
	.comm	_RADEON_SCLK_FORCEON_MASK,4,2   ; @RADEON_SCLK_FORCEON_MASK
	.comm	_CHIP_RV250,8,3                 ; @CHIP_RV250
	.comm	_CHIP_RV100,8,3                 ; @CHIP_RV100
	.comm	_CHIP_RV200,8,3                 ; @CHIP_RV200
	.comm	_CHIP_RV280,8,3                 ; @CHIP_RV280
	.comm	_RADEON_PLL_PWRMGT_CNTL,4,2     ; @RADEON_PLL_PWRMGT_CNTL
	.comm	_RADEON_TCL_BYPASS_DISABLE,4,2  ; @RADEON_TCL_BYPASS_DISABLE
	.comm	_RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb,4,2 ; @RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb
	.comm	_R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF,4,2 ; @R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF
	.comm	_R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF,4,2 ; @R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF
	.comm	_CHIP_R300,8,3                  ; @CHIP_R300
	.comm	_CHIP_R350,8,3                  ; @CHIP_R350
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
.subsections_via_symbols
