	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ironlake_crtc_enable
_ironlake_crtc_enable:                  ## @ironlake_crtc_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, -72(%rbp)                 ## 8-byte Spill
	movq	%rdi, %r15
	movq	16(%rdi), %r13
	movq	(%r13), %r14
	movq	%r14, %rdi
	callq	_to_i915
	movq	%rax, -64(%rbp)                 ## 8-byte Spill
	movq	%r13, %rdi
	callq	_to_intel_crtc
	movq	%rax, %r12
	movl	(%rax), %ebx
	movl	4(%rax), %edi
	callq	_WARN_ON
	testq	%rax, %rax
	je	LBB0_1
## %bb.19:
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_1:
	movq	%r13, -56(%rbp)                 ## 8-byte Spill
	movq	%r14, -48(%rbp)                 ## 8-byte Spill
	movl	%ebx, %r13d
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	movl	%r13d, %esi
	xorl	%edx, %edx
	callq	_intel_set_cpu_fifo_underrun_reporting
	movq	%rbx, %r14
	movq	%rbx, %rdi
	movl	%r13d, %esi
	xorl	%edx, %edx
	callq	_intel_set_pch_fifo_underrun_reporting
	cmpq	$0, (%r15)
	je	LBB0_3
## %bb.2:
	movq	%r15, %rdi
	callq	_intel_prepare_shared_dpll
LBB0_3:
	movq	%r15, %rdi
	callq	_intel_crtc_has_dp_encoder
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	movq	_M1_N1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_intel_dp_set_m_n
LBB0_5:
	movq	%r15, %rdi
	callq	_intel_set_pipe_timings
	movq	%r15, %rdi
	callq	_intel_set_pipe_src_size
	cmpq	$0, (%r15)
	movq	%r14, %rbx
	je	LBB0_7
## %bb.6:
	leaq	8(%r15), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_intel_cpu_transcoder_set_m_n
LBB0_7:
	movq	%r15, %rdi
	callq	_ironlake_set_pipeconf
	movq	%r12, %rdi
	movl	$1, 4(%r12)
	movq	%r15, %rsi
	movq	-72(%rbp), %r14                 ## 8-byte Reload
	movq	%r14, %rdx
	callq	_intel_encoders_pre_enable
	cmpq	$0, (%r15)
	je	LBB0_9
## %bb.8:
	movq	%r15, %rdi
	callq	_ironlake_fdi_pll_enable
	jmp	LBB0_10
LBB0_9:
	movq	%rbx, %rdi
	movl	%r13d, %esi
	callq	_assert_fdi_tx_disabled
	movq	%rbx, %rdi
	movl	%r13d, %esi
	callq	_assert_fdi_rx_disabled
LBB0_10:
	movq	%r15, %rdi
	callq	_ironlake_pfit_enable
	movq	%r15, %rdi
	callq	_intel_color_load_luts
	movq	%r15, %rdi
	callq	_intel_color_commit
	movq	%r15, %rdi
	callq	_intel_disable_primary_plane
	movq	(%rbx), %rax
	testq	%rax, %rax
	je	LBB0_12
## %bb.11:
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	*%rax
LBB0_12:
	movq	%r15, %rdi
	callq	_intel_enable_pipe
	cmpq	$0, (%r15)
	je	LBB0_14
## %bb.13:
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	_ironlake_pch_enable
LBB0_14:
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_assert_vblank_disabled
	movq	%r15, %rdi
	callq	_intel_crtc_vblank_on
	movq	%r12, %rdi
	movq	%r15, %rsi
	movq	%r14, %rdx
	callq	_intel_encoders_enable
	movq	%rbx, %rdi
	callq	_HAS_PCH_CPT
	testq	%rax, %rax
	je	LBB0_16
## %bb.15:
	movl	(%r12), %esi
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_cpt_verify_modeset
LBB0_16:
	cmpq	$0, (%r15)
	je	LBB0_18
## %bb.17:
	movq	%rbx, %rdi
	movl	%r13d, %esi
	callq	_intel_wait_for_vblank
	movq	%rbx, %rdi
	movl	%r13d, %esi
	callq	_intel_wait_for_vblank
LBB0_18:
	movq	%rbx, %rdi
	movl	%r13d, %esi
	movl	$1, %edx
	callq	_intel_set_cpu_fifo_underrun_reporting
	movq	%rbx, %rdi
	movl	%r13d, %esi
	movl	$1, %edx
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_intel_set_pch_fifo_underrun_reporting ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_M1_N1,4,2                      ## @M1_N1
	.no_dead_strip	_ironlake_crtc_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ironlake_crtc_enable
_ironlake_crtc_enable:                  ; @ironlake_crtc_enable
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x23, x1
	mov	x21, x0
	ldr	x25, [x0, #16]
	ldr	x22, [x25]
	mov	x0, x22
	bl	_to_i915
	mov	x19, x0
	mov	x0, x25
	bl	_to_intel_crtc
	mov	x24, x0
	ldp	w20, w0, [x0]
	bl	_WARN_ON
	cbz	x0, LBB0_2
; %bb.1:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_2:
	mov	x0, x19
	mov	x1, x20
	mov	w2, #0
	bl	_intel_set_cpu_fifo_underrun_reporting
	mov	x0, x19
	mov	x1, x20
	mov	w2, #0
	bl	_intel_set_pch_fifo_underrun_reporting
	ldr	x8, [x21]
	cbz	x8, LBB0_4
; %bb.3:
	mov	x0, x21
	bl	_intel_prepare_shared_dpll
LBB0_4:
	mov	x0, x21
	bl	_intel_crtc_has_dp_encoder
	cbz	x0, LBB0_6
; %bb.5:
Lloh0:
	adrp	x8, _M1_N1@GOTPAGE
Lloh1:
	ldr	x8, [x8, _M1_N1@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x21
	bl	_intel_dp_set_m_n
LBB0_6:
	mov	x0, x21
	bl	_intel_set_pipe_timings
	mov	x0, x21
	bl	_intel_set_pipe_src_size
	ldr	x8, [x21]
	cbz	x8, LBB0_8
; %bb.7:
	add	x1, x21, #8
	mov	x0, x21
	mov	x2, #0
	bl	_intel_cpu_transcoder_set_m_n
LBB0_8:
	mov	x0, x21
	bl	_ironlake_set_pipeconf
	mov	w8, #1
	str	w8, [x24, #4]
	mov	x0, x24
	mov	x1, x21
	mov	x2, x23
	bl	_intel_encoders_pre_enable
	ldr	x8, [x21]
	cbz	x8, LBB0_10
; %bb.9:
	mov	x0, x21
	bl	_ironlake_fdi_pll_enable
	b	LBB0_11
LBB0_10:
	mov	x0, x19
	mov	x1, x20
	bl	_assert_fdi_tx_disabled
	mov	x0, x19
	mov	x1, x20
	bl	_assert_fdi_rx_disabled
LBB0_11:
	mov	x0, x21
	bl	_ironlake_pfit_enable
	mov	x0, x21
	bl	_intel_color_load_luts
	mov	x0, x21
	bl	_intel_color_commit
	mov	x0, x21
	bl	_intel_disable_primary_plane
	ldr	x8, [x19]
	cbz	x8, LBB0_13
; %bb.12:
	mov	x0, x23
	mov	x1, x21
	blr	x8
LBB0_13:
	mov	x0, x21
	bl	_intel_enable_pipe
	ldr	x8, [x21]
	cbz	x8, LBB0_15
; %bb.14:
	mov	x0, x23
	mov	x1, x21
	bl	_ironlake_pch_enable
LBB0_15:
	mov	x0, x25
	bl	_assert_vblank_disabled
	mov	x0, x21
	bl	_intel_crtc_vblank_on
	mov	x0, x24
	mov	x1, x21
	mov	x2, x23
	bl	_intel_encoders_enable
	mov	x0, x19
	bl	_HAS_PCH_CPT
	cbz	x0, LBB0_17
; %bb.16:
	ldr	w1, [x24]
	mov	x0, x22
	bl	_cpt_verify_modeset
LBB0_17:
	ldr	x8, [x21]
	cbz	x8, LBB0_19
; %bb.18:
	mov	x0, x19
	mov	x1, x20
	bl	_intel_wait_for_vblank
	mov	x0, x19
	mov	x1, x20
	bl	_intel_wait_for_vblank
LBB0_19:
	mov	x0, x19
	mov	x1, x20
	mov	w2, #1
	bl	_intel_set_cpu_fifo_underrun_reporting
	mov	x0, x19
	mov	x1, x20
	mov	w2, #1
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_intel_set_pch_fifo_underrun_reporting
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_M1_N1,4,2                      ; @M1_N1
	.no_dead_strip	_ironlake_crtc_enable
.subsections_via_symbols
