	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function icl_enable_phy_clock_gating
_icl_enable_phy_clock_gating:           ## @icl_enable_phy_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movl	4(%rdi), %edi
	callq	_to_i915
	movl	(%rbx), %r15d
	movq	%rax, %rdi
	movl	%r15d, %esi
	callq	_intel_port_to_tc
	movl	%eax, %r14d
	movq	_PORT_TC_NONE@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r14d
	jne	LBB0_2
## %bb.1:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	xorl	%edi, %edi
	movl	%r15d, %esi
	callq	_MG_DP_MODE
	movl	%eax, %edi
	callq	_I915_READ
	movl	%eax, %ebx
	movq	_MG_DP_MODE_CFG_TR2PWR_GATING@GOTPCREL(%rip), %r12
	movq	_MG_DP_MODE_CFG_TRPWR_GATING@GOTPCREL(%rip), %r13
	movq	_MG_DP_MODE_CFG_CLNPWR_GATING@GOTPCREL(%rip), %rdx
	movq	_MG_DP_MODE_CFG_DIGPWR_GATING@GOTPCREL(%rip), %rcx
	movq	_MG_DP_MODE_CFG_GAONPWR_GATING@GOTPCREL(%rip), %rax
	orl	(%r12), %ebx
	orl	(%r13), %ebx
	orl	(%rdx), %ebx
	orl	(%rcx), %ebx
	orl	(%rax), %ebx
	xorl	%edi, %edi
	movl	%r15d, %esi
	callq	_MG_DP_MODE
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movl	$1, %edi
	movl	%r15d, %esi
	callq	_MG_DP_MODE
	movl	%eax, %edi
	callq	_I915_READ
	movl	%eax, %ebx
	orl	(%r12), %ebx
	orl	(%r13), %ebx
	movq	_MG_DP_MODE_CFG_CLNPWR_GATING@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_MG_DP_MODE_CFG_DIGPWR_GATING@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_MG_DP_MODE_CFG_GAONPWR_GATING@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	$1, %edi
	movl	%r15d, %esi
	callq	_MG_DP_MODE
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
	movl	%r14d, %edi
	callq	_MG_MISC_SUS0
	movl	%eax, %edi
	callq	_I915_READ
	movl	%eax, %ebx
	movl	$3, %edi
	callq	_MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE
	movq	_MG_MISC_SUS0_CFG_TR2PWR_GATING@GOTPCREL(%rip), %rcx
	movq	_MG_MISC_SUS0_CFG_CL2PWR_GATING@GOTPCREL(%rip), %rdx
	movq	_MG_MISC_SUS0_CFG_GAONPWR_GATING@GOTPCREL(%rip), %rsi
	movq	_MG_MISC_SUS0_CFG_TRPWR_GATING@GOTPCREL(%rip), %rdi
	movq	_MG_MISC_SUS0_CFG_CL1PWR_GATING@GOTPCREL(%rip), %r8
	movq	_MG_MISC_SUS0_CFG_DGPWR_GATING@GOTPCREL(%rip), %r9
	orl	%eax, %ebx
	orl	(%rcx), %ebx
	orl	(%rdx), %ebx
	orl	(%rsi), %ebx
	orl	(%rdi), %ebx
	orl	(%r8), %ebx
	orl	(%r9), %ebx
	movl	%r14d, %edi
	callq	_MG_MISC_SUS0
	movl	%eax, %edi
	movl	%ebx, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_I915_WRITE                     ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PORT_TC_NONE,4,2               ## @PORT_TC_NONE
	.comm	_MG_DP_MODE_CFG_TR2PWR_GATING,4,2 ## @MG_DP_MODE_CFG_TR2PWR_GATING
	.comm	_MG_DP_MODE_CFG_TRPWR_GATING,4,2 ## @MG_DP_MODE_CFG_TRPWR_GATING
	.comm	_MG_DP_MODE_CFG_CLNPWR_GATING,4,2 ## @MG_DP_MODE_CFG_CLNPWR_GATING
	.comm	_MG_DP_MODE_CFG_DIGPWR_GATING,4,2 ## @MG_DP_MODE_CFG_DIGPWR_GATING
	.comm	_MG_DP_MODE_CFG_GAONPWR_GATING,4,2 ## @MG_DP_MODE_CFG_GAONPWR_GATING
	.comm	_MG_MISC_SUS0_CFG_TR2PWR_GATING,4,2 ## @MG_MISC_SUS0_CFG_TR2PWR_GATING
	.comm	_MG_MISC_SUS0_CFG_CL2PWR_GATING,4,2 ## @MG_MISC_SUS0_CFG_CL2PWR_GATING
	.comm	_MG_MISC_SUS0_CFG_GAONPWR_GATING,4,2 ## @MG_MISC_SUS0_CFG_GAONPWR_GATING
	.comm	_MG_MISC_SUS0_CFG_TRPWR_GATING,4,2 ## @MG_MISC_SUS0_CFG_TRPWR_GATING
	.comm	_MG_MISC_SUS0_CFG_CL1PWR_GATING,4,2 ## @MG_MISC_SUS0_CFG_CL1PWR_GATING
	.comm	_MG_MISC_SUS0_CFG_DGPWR_GATING,4,2 ## @MG_MISC_SUS0_CFG_DGPWR_GATING
	.no_dead_strip	_icl_enable_phy_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function icl_enable_phy_clock_gating
_icl_enable_phy_clock_gating:           ; @icl_enable_phy_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldr	w0, [x0, #4]
	bl	_to_i915
	ldr	w20, [x19]
	mov	x1, x20
	bl	_intel_port_to_tc
Lloh0:
	adrp	x8, _PORT_TC_NONE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PORT_TC_NONE@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cmp	w0, w8
	b.ne	LBB0_2
; %bb.1:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_2:
	mov	x19, x0
	mov	w0, #0
	mov	x1, x20
	bl	_MG_DP_MODE
	bl	_I915_READ
Lloh3:
	adrp	x22, _MG_DP_MODE_CFG_TR2PWR_GATING@GOTPAGE
Lloh4:
	ldr	x22, [x22, _MG_DP_MODE_CFG_TR2PWR_GATING@GOTPAGEOFF]
	ldr	w8, [x22]
Lloh5:
	adrp	x23, _MG_DP_MODE_CFG_TRPWR_GATING@GOTPAGE
Lloh6:
	ldr	x23, [x23, _MG_DP_MODE_CFG_TRPWR_GATING@GOTPAGEOFF]
	ldr	w9, [x23]
Lloh7:
	adrp	x24, _MG_DP_MODE_CFG_CLNPWR_GATING@GOTPAGE
Lloh8:
	ldr	x24, [x24, _MG_DP_MODE_CFG_CLNPWR_GATING@GOTPAGEOFF]
	ldr	w10, [x24]
Lloh9:
	adrp	x25, _MG_DP_MODE_CFG_DIGPWR_GATING@GOTPAGE
Lloh10:
	ldr	x25, [x25, _MG_DP_MODE_CFG_DIGPWR_GATING@GOTPAGEOFF]
	ldr	w11, [x25]
Lloh11:
	adrp	x26, _MG_DP_MODE_CFG_GAONPWR_GATING@GOTPAGE
Lloh12:
	ldr	x26, [x26, _MG_DP_MODE_CFG_GAONPWR_GATING@GOTPAGEOFF]
	ldr	w12, [x26]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w21, w8, w12
	mov	w0, #0
	mov	x1, x20
	bl	_MG_DP_MODE
	mov	x1, x21
	bl	_I915_WRITE
	mov	w0, #1
	mov	x1, x20
	bl	_MG_DP_MODE
	bl	_I915_READ
	ldr	w8, [x22]
	ldr	w9, [x23]
	ldr	w10, [x24]
	ldr	w11, [x25]
	ldr	w12, [x26]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w21, w8, w12
	mov	w0, #1
	mov	x1, x20
	bl	_MG_DP_MODE
	mov	x1, x21
	bl	_I915_WRITE
	mov	x0, x19
	bl	_MG_MISC_SUS0
	bl	_I915_READ
	mov	x20, x0
	mov	w0, #3
	bl	_MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE
Lloh13:
	adrp	x8, _MG_MISC_SUS0_CFG_TR2PWR_GATING@GOTPAGE
Lloh14:
	ldr	x8, [x8, _MG_MISC_SUS0_CFG_TR2PWR_GATING@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
Lloh16:
	adrp	x9, _MG_MISC_SUS0_CFG_CL2PWR_GATING@GOTPAGE
Lloh17:
	ldr	x9, [x9, _MG_MISC_SUS0_CFG_CL2PWR_GATING@GOTPAGEOFF]
Lloh18:
	adrp	x10, _MG_MISC_SUS0_CFG_GAONPWR_GATING@GOTPAGE
Lloh19:
	ldr	x10, [x10, _MG_MISC_SUS0_CFG_GAONPWR_GATING@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
Lloh21:
	ldr	w10, [x10]
Lloh22:
	adrp	x11, _MG_MISC_SUS0_CFG_TRPWR_GATING@GOTPAGE
Lloh23:
	ldr	x11, [x11, _MG_MISC_SUS0_CFG_TRPWR_GATING@GOTPAGEOFF]
Lloh24:
	adrp	x12, _MG_MISC_SUS0_CFG_CL1PWR_GATING@GOTPAGE
Lloh25:
	ldr	x12, [x12, _MG_MISC_SUS0_CFG_CL1PWR_GATING@GOTPAGEOFF]
Lloh26:
	ldr	w11, [x11]
Lloh27:
	ldr	w12, [x12]
Lloh28:
	adrp	x13, _MG_MISC_SUS0_CFG_DGPWR_GATING@GOTPAGE
Lloh29:
	ldr	x13, [x13, _MG_MISC_SUS0_CFG_DGPWR_GATING@GOTPAGEOFF]
Lloh30:
	ldr	w13, [x13]
	orr	w14, w0, w20
	orr	w8, w14, w8
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w20, w8, w13
	mov	x0, x19
	bl	_MG_MISC_SUS0
	mov	x1, x20
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_I915_WRITE
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh26
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh20
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_PORT_TC_NONE,4,2               ; @PORT_TC_NONE
	.comm	_MG_DP_MODE_CFG_TR2PWR_GATING,4,2 ; @MG_DP_MODE_CFG_TR2PWR_GATING
	.comm	_MG_DP_MODE_CFG_TRPWR_GATING,4,2 ; @MG_DP_MODE_CFG_TRPWR_GATING
	.comm	_MG_DP_MODE_CFG_CLNPWR_GATING,4,2 ; @MG_DP_MODE_CFG_CLNPWR_GATING
	.comm	_MG_DP_MODE_CFG_DIGPWR_GATING,4,2 ; @MG_DP_MODE_CFG_DIGPWR_GATING
	.comm	_MG_DP_MODE_CFG_GAONPWR_GATING,4,2 ; @MG_DP_MODE_CFG_GAONPWR_GATING
	.comm	_MG_MISC_SUS0_CFG_TR2PWR_GATING,4,2 ; @MG_MISC_SUS0_CFG_TR2PWR_GATING
	.comm	_MG_MISC_SUS0_CFG_CL2PWR_GATING,4,2 ; @MG_MISC_SUS0_CFG_CL2PWR_GATING
	.comm	_MG_MISC_SUS0_CFG_GAONPWR_GATING,4,2 ; @MG_MISC_SUS0_CFG_GAONPWR_GATING
	.comm	_MG_MISC_SUS0_CFG_TRPWR_GATING,4,2 ; @MG_MISC_SUS0_CFG_TRPWR_GATING
	.comm	_MG_MISC_SUS0_CFG_CL1PWR_GATING,4,2 ; @MG_MISC_SUS0_CFG_CL1PWR_GATING
	.comm	_MG_MISC_SUS0_CFG_DGPWR_GATING,4,2 ; @MG_MISC_SUS0_CFG_DGPWR_GATING
	.no_dead_strip	_icl_enable_phy_clock_gating
.subsections_via_symbols
