	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v2_0_clock_gating_dpg_mode
_vcn_v2_0_clock_gating_dpg_mode:        ## @vcn_v2_0_clock_gating_dpg_mode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$1, %eax
	shll	%cl, %eax
	movq	_AMD_CG_SUPPORT_VCN_MGCG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	(%rdi), %ecx
	testl	%ecx, %ecx
	cmovel	%ecx, %eax
	movq	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPCREL(%rip), %rcx
	movq	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPCREL(%rip), %rdi
	movl	(%rdi), %ebx
	orl	(%rcx), %ebx
	movq	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_UVD_CGC_CTRL__SYS_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_UVD_CGC_CTRL__REGS_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_UVD_CGC_CTRL__RBC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movl	%edx, %r14d
	movl	%esi, %r15d
	movq	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPCREL(%rip), %rcx
	movq	_UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ebx
	movb	(%rcx), %dl
	movq	_UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_UVD_CGC_CTRL__MPC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movq	_UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movq	_UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPCREL(%rip), %rsi
	orl	(%rsi), %ebx
	movl	$4, %esi
	shll	%cl, %esi
	btsl	%edx, %eax
	movq	_UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	orl	%eax, %esi
	movq	_UVD_CGC_CTRL__WCB_MODE_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_UVD_CGC_CTRL__SCPU_MODE_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	notl	%ebx
	andl	%esi, %ebx
	movq	_UVD@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	movq	_mmUVD_CGC_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	movl	%ebx, %esi
	movl	%r15d, %edx
	movl	%r14d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%r12), %edi
	movq	_mmUVD_CGC_GATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	xorl	%esi, %esi
	movl	%r15d, %edx
	movl	%r14d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%r12), %edi
	movq	_mmUVD_SUVD_CGC_GATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	movl	$1, %esi
	movl	%r15d, %edx
	movl	%r14d, %ecx
	callq	_WREG32_SOC15_DPG_MODE_2_0
	movl	(%r12), %edi
	movq	_mmUVD_SUVD_CGC_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_DPG_MODE_OFFSET_2_0
	movl	%eax, %edi
	xorl	%esi, %esi
	movl	%r15d, %edx
	movl	%r14d, %ecx
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_SOC15_DPG_MODE_2_0      ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_CG_SUPPORT_VCN_MGCG,4,2    ## @AMD_CG_SUPPORT_VCN_MGCG
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT,4,2 ## @UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT
	.comm	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT,4,2 ## @UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
	.comm	_UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT,4,2 ## @UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT
	.comm	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_RE_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_CM_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_IT_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_DB_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_MP_MODE_MASK
	.comm	_UVD_CGC_CTRL__SYS_MODE_MASK,4,2 ## @UVD_CGC_CTRL__SYS_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPEG2_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPEG2_MODE_MASK
	.comm	_UVD_CGC_CTRL__REGS_MODE_MASK,4,2 ## @UVD_CGC_CTRL__REGS_MODE_MASK
	.comm	_UVD_CGC_CTRL__RBC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__RBC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_MC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LMI_MC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LMI_UMC_MODE_MASK
	.comm	_UVD_CGC_CTRL__IDCT_MODE_MASK,4,2 ## @UVD_CGC_CTRL__IDCT_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPRD_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPRD_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LBSI_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LBSI_MODE_MASK
	.comm	_UVD_CGC_CTRL__LRBBM_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LRBBM_MODE_MASK
	.comm	_UVD_CGC_CTRL__WCB_MODE_MASK,4,2 ## @UVD_CGC_CTRL__WCB_MODE_MASK
	.comm	_UVD_CGC_CTRL__VCPU_MODE_MASK,4,2 ## @UVD_CGC_CTRL__VCPU_MODE_MASK
	.comm	_UVD_CGC_CTRL__SCPU_MODE_MASK,4,2 ## @UVD_CGC_CTRL__SCPU_MODE_MASK
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_CGC_CTRL,4,2             ## @mmUVD_CGC_CTRL
	.comm	_mmUVD_CGC_GATE,4,2             ## @mmUVD_CGC_GATE
	.comm	_mmUVD_SUVD_CGC_GATE,4,2        ## @mmUVD_SUVD_CGC_GATE
	.comm	_mmUVD_SUVD_CGC_CTRL,4,2        ## @mmUVD_SUVD_CGC_CTRL
	.no_dead_strip	_vcn_v2_0_clock_gating_dpg_mode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v2_0_clock_gating_dpg_mode
_vcn_v2_0_clock_gating_dpg_mode:        ; @vcn_v2_0_clock_gating_dpg_mode
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x2
	mov	x20, x1
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _AMD_CG_SUPPORT_VCN_MGCG@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_CG_SUPPORT_VCN_MGCG@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
Lloh3:
	adrp	x10, _UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPAGE
Lloh4:
	ldr	x10, [x10, _UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPAGEOFF]
Lloh5:
	ldr	w10, [x10]
	mov	w11, #1
	lsl	w10, w11, w10
	tst	w9, w8
Lloh6:
	adrp	x8, _UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPAGE
Lloh7:
	ldr	x8, [x8, _UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPAGEOFF]
	csel	w9, wzr, w10, eq
Lloh8:
	ldr	w8, [x8]
	lsl	w8, w11, w8
	orr	w8, w9, w8
Lloh9:
	adrp	x9, _UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPAGE
Lloh10:
	ldr	x9, [x9, _UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	mov	w10, #4
	lsl	w9, w10, w9
	orr	w8, w8, w9
Lloh12:
	adrp	x9, _UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPAGE
Lloh13:
	ldr	x9, [x9, _UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
Lloh15:
	adrp	x10, _UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPAGE
Lloh16:
	ldr	x10, [x10, _UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w10, [x10]
Lloh18:
	adrp	x11, _UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPAGE
Lloh19:
	ldr	x11, [x11, _UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPAGEOFF]
	orr	w9, w10, w9
Lloh20:
	ldr	w10, [x11]
	orr	w9, w9, w10
Lloh21:
	adrp	x10, _UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPAGE
Lloh22:
	ldr	x10, [x10, _UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPAGEOFF]
Lloh23:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh24:
	adrp	x10, _UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPAGE
Lloh25:
	ldr	x10, [x10, _UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPAGEOFF]
Lloh26:
	ldr	w10, [x10]
Lloh27:
	adrp	x11, _UVD_CGC_CTRL__SYS_MODE_MASK@GOTPAGE
Lloh28:
	ldr	x11, [x11, _UVD_CGC_CTRL__SYS_MODE_MASK@GOTPAGEOFF]
	orr	w9, w9, w10
Lloh29:
	ldr	w10, [x11]
	orr	w9, w9, w10
Lloh30:
	adrp	x10, _UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPAGE
Lloh31:
	ldr	x10, [x10, _UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPAGEOFF]
Lloh32:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh33:
	adrp	x10, _UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPAGE
Lloh34:
	ldr	x10, [x10, _UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPAGEOFF]
Lloh35:
	ldr	w10, [x10]
Lloh36:
	adrp	x11, _UVD_CGC_CTRL__REGS_MODE_MASK@GOTPAGE
Lloh37:
	ldr	x11, [x11, _UVD_CGC_CTRL__REGS_MODE_MASK@GOTPAGEOFF]
	orr	w9, w9, w10
Lloh38:
	ldr	w10, [x11]
	orr	w9, w9, w10
Lloh39:
	adrp	x10, _UVD_CGC_CTRL__RBC_MODE_MASK@GOTPAGE
Lloh40:
	ldr	x10, [x10, _UVD_CGC_CTRL__RBC_MODE_MASK@GOTPAGEOFF]
Lloh41:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh42:
	adrp	x10, _UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPAGE
Lloh43:
	ldr	x10, [x10, _UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPAGEOFF]
Lloh44:
	ldr	w10, [x10]
Lloh45:
	adrp	x11, _UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPAGE
Lloh46:
	ldr	x11, [x11, _UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPAGEOFF]
	orr	w9, w9, w10
Lloh47:
	ldr	w10, [x11]
	orr	w9, w9, w10
Lloh48:
	adrp	x10, _UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPAGE
Lloh49:
	ldr	x10, [x10, _UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPAGEOFF]
Lloh50:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh51:
	adrp	x10, _UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPAGE
Lloh52:
	ldr	x10, [x10, _UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPAGEOFF]
Lloh53:
	ldr	w10, [x10]
Lloh54:
	adrp	x11, _UVD_CGC_CTRL__MPC_MODE_MASK@GOTPAGE
Lloh55:
	ldr	x11, [x11, _UVD_CGC_CTRL__MPC_MODE_MASK@GOTPAGEOFF]
	orr	w9, w9, w10
Lloh56:
	ldr	w10, [x11]
	orr	w9, w9, w10
Lloh57:
	adrp	x10, _UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPAGE
Lloh58:
	ldr	x10, [x10, _UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPAGEOFF]
Lloh59:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh60:
	adrp	x10, _UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPAGE
Lloh61:
	ldr	x10, [x10, _UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPAGEOFF]
Lloh62:
	ldr	w10, [x10]
Lloh63:
	adrp	x11, _UVD_CGC_CTRL__WCB_MODE_MASK@GOTPAGE
Lloh64:
	ldr	x11, [x11, _UVD_CGC_CTRL__WCB_MODE_MASK@GOTPAGEOFF]
	orr	w9, w9, w10
Lloh65:
	ldr	w10, [x11]
	orr	w9, w9, w10
Lloh66:
	adrp	x10, _UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPAGE
Lloh67:
	ldr	x10, [x10, _UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPAGEOFF]
Lloh68:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh69:
	adrp	x10, _UVD_CGC_CTRL__SCPU_MODE_MASK@GOTPAGE
Lloh70:
	ldr	x10, [x10, _UVD_CGC_CTRL__SCPU_MODE_MASK@GOTPAGEOFF]
Lloh71:
	ldr	w10, [x10]
	orr	w9, w9, w10
	bic	w21, w8, w9
Lloh72:
	adrp	x22, _UVD@GOTPAGE
Lloh73:
	ldr	x22, [x22, _UVD@GOTPAGEOFF]
	ldr	w0, [x22]
Lloh74:
	adrp	x8, _mmUVD_CGC_CTRL@GOTPAGE
Lloh75:
	ldr	x8, [x8, _mmUVD_CGC_CTRL@GOTPAGEOFF]
Lloh76:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	x1, x21
	mov	x2, x20
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x22]
Lloh77:
	adrp	x8, _mmUVD_CGC_GATE@GOTPAGE
Lloh78:
	ldr	x8, [x8, _mmUVD_CGC_GATE@GOTPAGEOFF]
Lloh79:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	w1, #0
	mov	x2, x20
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x22]
Lloh80:
	adrp	x8, _mmUVD_SUVD_CGC_GATE@GOTPAGE
Lloh81:
	ldr	x8, [x8, _mmUVD_SUVD_CGC_GATE@GOTPAGEOFF]
Lloh82:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	w1, #1
	mov	x2, x20
	mov	x3, x19
	bl	_WREG32_SOC15_DPG_MODE_2_0
	ldr	w0, [x22]
Lloh83:
	adrp	x8, _mmUVD_SUVD_CGC_CTRL@GOTPAGE
Lloh84:
	ldr	x8, [x8, _mmUVD_SUVD_CGC_CTRL@GOTPAGEOFF]
Lloh85:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_DPG_MODE_OFFSET_2_0
	mov	w1, #0
	mov	x2, x20
	mov	x3, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32_SOC15_DPG_MODE_2_0
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGot	Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_CG_SUPPORT_VCN_MGCG,4,2    ; @AMD_CG_SUPPORT_VCN_MGCG
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT,4,2 ; @UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT
	.comm	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT,4,2 ; @UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
	.comm	_UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT,4,2 ; @UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT
	.comm	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_RE_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_CM_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_IT_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_DB_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_MP_MODE_MASK
	.comm	_UVD_CGC_CTRL__SYS_MODE_MASK,4,2 ; @UVD_CGC_CTRL__SYS_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPEG2_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPEG2_MODE_MASK
	.comm	_UVD_CGC_CTRL__REGS_MODE_MASK,4,2 ; @UVD_CGC_CTRL__REGS_MODE_MASK
	.comm	_UVD_CGC_CTRL__RBC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__RBC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_MC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LMI_MC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LMI_UMC_MODE_MASK
	.comm	_UVD_CGC_CTRL__IDCT_MODE_MASK,4,2 ; @UVD_CGC_CTRL__IDCT_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPRD_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPRD_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LBSI_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LBSI_MODE_MASK
	.comm	_UVD_CGC_CTRL__LRBBM_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LRBBM_MODE_MASK
	.comm	_UVD_CGC_CTRL__WCB_MODE_MASK,4,2 ; @UVD_CGC_CTRL__WCB_MODE_MASK
	.comm	_UVD_CGC_CTRL__VCPU_MODE_MASK,4,2 ; @UVD_CGC_CTRL__VCPU_MODE_MASK
	.comm	_UVD_CGC_CTRL__SCPU_MODE_MASK,4,2 ; @UVD_CGC_CTRL__SCPU_MODE_MASK
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_CGC_CTRL,4,2             ; @mmUVD_CGC_CTRL
	.comm	_mmUVD_CGC_GATE,4,2             ; @mmUVD_CGC_GATE
	.comm	_mmUVD_SUVD_CGC_GATE,4,2        ; @mmUVD_SUVD_CGC_GATE
	.comm	_mmUVD_SUVD_CGC_CTRL,4,2        ; @mmUVD_SUVD_CGC_CTRL
	.no_dead_strip	_vcn_v2_0_clock_gating_dpg_mode
.subsections_via_symbols
