	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_intel_gvt_create_idle_vgpu     ## -- Begin function intel_gvt_create_idle_vgpu
	.p2align	4, 0x90
_intel_gvt_create_idle_vgpu:            ## @intel_gvt_create_idle_vgpu
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movl	$40, %edi
	callq	_vzalloc
	testq	%rax, %rax
	je	LBB0_1
## %bb.3:
	movq	%rax, %r15
	movq	_IDLE_VGPU_IDR@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 32(%r15)
	movq	%r14, 24(%r15)
	movq	%r15, %rdi
	addq	$16, %rdi
	callq	_mutex_init
	movq	_I915_NUM_ENGINES@GOTPCREL(%rip), %r14
	cmpl	$0, (%r14)
	je	LBB0_6
## %bb.4:
	xorl	%r12d, %r12d
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	movq	8(%r15), %rdi
	addq	%r12, %rdi
	callq	_INIT_LIST_HEAD
	incq	%rbx
	movl	(%r14), %eax
	addq	$4, %r12
	cmpq	%rax, %rbx
	jb	LBB0_5
LBB0_6:
	movq	%r15, %rdi
	callq	_intel_vgpu_init_sched_policy
	testl	%eax, %eax
	je	LBB0_7
## %bb.8:
	movl	%eax, %r14d
	movq	%r15, %rdi
	callq	_vfree
	movl	%r14d, %edi
	jmp	LBB0_2
LBB0_1:
	movq	_ENOMEM@GOTPCREL(%rip), %rax
	xorl	%edi, %edi
	subl	(%rax), %edi
LBB0_2:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_ERR_PTR                        ## TAILCALL
LBB0_7:
	movl	$0, (%r15)
	movq	%r15, %rax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_ENOMEM,4,2                     ## @ENOMEM
	.comm	_IDLE_VGPU_IDR,4,2              ## @IDLE_VGPU_IDR
	.comm	_I915_NUM_ENGINES,4,2           ## @I915_NUM_ENGINES
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_intel_gvt_create_idle_vgpu     ; -- Begin function intel_gvt_create_idle_vgpu
	.p2align	2
_intel_gvt_create_idle_vgpu:            ; @intel_gvt_create_idle_vgpu
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x0
	mov	w0, #40
	bl	_vzalloc
	cbz	x0, LBB0_6
; %bb.1:
	mov	x19, x0
Lloh0:
	adrp	x8, _IDLE_VGPU_IDR@GOTPAGE
Lloh1:
	ldr	x8, [x8, _IDLE_VGPU_IDR@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	str	w8, [x0, #32]
	str	x20, [x0, #24]
	add	x0, x0, #16
	bl	_mutex_init
Lloh3:
	adrp	x20, _I915_NUM_ENGINES@GOTPAGE
Lloh4:
	ldr	x20, [x20, _I915_NUM_ENGINES@GOTPAGEOFF]
	ldr	w8, [x20]
	cbz	w8, LBB0_4
; %bb.2:
	mov	x21, #0
	mov	x22, #0
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #8]
	add	x0, x8, x21
	bl	_INIT_LIST_HEAD
	add	x22, x22, #1
	ldr	w8, [x20]
	add	x21, x21, #4
	cmp	x22, x8
	b.lo	LBB0_3
LBB0_4:
	mov	x0, x19
	bl	_intel_vgpu_init_sched_policy
	cbz	w0, LBB0_8
; %bb.5:
	mov	x20, x0
	mov	x0, x19
	bl	_vfree
	mov	x0, x20
	b	LBB0_7
LBB0_6:
Lloh5:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh6:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_7:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_ERR_PTR
LBB0_8:
	str	wzr, [x19]
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.cfi_endproc
                                        ; -- End function
	.comm	_ENOMEM,4,2                     ; @ENOMEM
	.comm	_IDLE_VGPU_IDR,4,2              ; @IDLE_VGPU_IDR
	.comm	_I915_NUM_ENGINES,4,2           ; @I915_NUM_ENGINES
.subsections_via_symbols
