	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function analogix_dp_link_start
_analogix_dp_link_start:                ## @analogix_dp_link_start
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -48(%rbp)
	movl	8(%rdi), %r14d
	movq	_CLOCK_RECOVERY@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 32(%rdi)
	movq	$0, 24(%rdi)
	testl	%r14d, %r14d
	jle	LBB0_2
## %bb.1:
	movq	16(%r15), %rdi
	leaq	(,%r14,8), %rsi
	callq	___bzero
LBB0_2:
	movl	12(%r15), %esi
	movq	%r15, %rdi
	callq	_analogix_dp_set_link_bandwidth
	movl	8(%r15), %esi
	movq	%r15, %rdi
	callq	_analogix_dp_set_lane_count
	movl	12(%r15), %eax
	movl	%eax, -64(%rbp)
	movl	8(%r15), %eax
	movl	%eax, -60(%rbp)
	movq	_DP_LINK_BW_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-64(%rbp), %rdx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	_drm_dp_dpcd_write
	testl	%eax, %eax
	js	LBB0_15
## %bb.3:
	movq	%r15, %rdi
	callq	_analogix_dp_set_enhanced_mode
	testl	%eax, %eax
	js	LBB0_16
## %bb.4:
	testl	%r14d, %r14d
	jle	LBB0_7
## %bb.5:
	xorl	%ebx, %ebx
	movq	_PRE_EMPHASIS_LEVEL_0@GOTPCREL(%rip), %r12
	.p2align	4, 0x90
LBB0_6:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r12), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_analogix_dp_set_lane_lane_pre_emphasis
	incl	%ebx
	cmpl	%ebx, %r14d
	jne	LBB0_6
LBB0_7:
	movq	%r15, %rdi
	callq	_analogix_dp_get_pll_lock_status
	movq	_PLL_UNLOCKED@GOTPCREL(%rip), %r12
	cmpq	(%r12), %rax
	jne	LBB0_11
## %bb.8:
	movl	$-1, %ebx
	movq	_DP_TIMEOUT_LOOP_COUNT@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_9:                                 ## =>This Inner Loop Header: Depth=1
	incl	%ebx
	cmpl	(%r13), %ebx
	je	LBB0_18
## %bb.10:                              ##   in Loop: Header=BB0_9 Depth=1
	movl	$90, %edi
	movl	$120, %esi
	callq	_usleep_range
	movq	%r15, %rdi
	callq	_analogix_dp_get_pll_lock_status
	cmpq	(%r12), %rax
	je	LBB0_9
LBB0_11:
	movq	_TRAINING_PTN1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_analogix_dp_set_training_pattern
	movq	_DP_TRAINING_PATTERN_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DP_LINK_SCRAMBLING_DISABLE@GOTPCREL(%rip), %rax
	movq	_DP_TRAINING_PATTERN_1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	%r15, %rdi
	callq	_drm_dp_dpcd_writeb
	testl	%eax, %eax
	js	LBB0_15
## %bb.12:
	testl	%r14d, %r14d
	jle	LBB0_28
## %bb.13:
	movq	_DP_TRAIN_PRE_EMPH_LEVEL_0@GOTPCREL(%rip), %rcx
	movq	_DP_TRAIN_VOLTAGE_SWING_LEVEL_0@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	(%rcx), %eax
	cmpl	$8, %r14d
	jae	LBB0_19
## %bb.14:
	xorl	%ecx, %ecx
	jmp	LBB0_27
LBB0_15:
	movl	%eax, %ebx
	jmp	LBB0_29
LBB0_16:
	movl	%eax, %ebx
	movl	4(%r15), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
	jmp	LBB0_29
LBB0_18:
	movl	4(%r15), %edi
	leaq	L_.str.1(%rip), %rsi
	callq	_dev_err
	movq	_ETIMEDOUT@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
	jmp	LBB0_29
LBB0_19:
	movl	%r14d, %ecx
	andl	$-8, %ecx
	movd	%eax, %xmm0
	pshufd	$0, %xmm0, %xmm0                ## xmm0 = xmm0[0,0,0,0]
	leaq	-8(%rcx), %rdi
	movq	%rdi, %rsi
	shrq	$3, %rsi
	incq	%rsi
	movl	%esi, %edx
	andl	$7, %edx
	cmpq	$56, %rdi
	jae	LBB0_21
## %bb.20:
	xorl	%edi, %edi
	jmp	LBB0_23
LBB0_21:
	andq	$-8, %rsi
	xorl	%edi, %edi
	.p2align	4, 0x90
LBB0_22:                                ## =>This Inner Loop Header: Depth=1
	movdqa	%xmm0, -64(%rbp,%rdi,4)
	movdqa	%xmm0, -48(%rbp,%rdi,4)
	movdqa	%xmm0, -32(%rbp,%rdi,4)
	movdqa	%xmm0, -16(%rbp,%rdi,4)
	movdqa	%xmm0, (%rbp,%rdi,4)
	movdqa	%xmm0, 16(%rbp,%rdi,4)
	movdqa	%xmm0, 32(%rbp,%rdi,4)
	movdqa	%xmm0, 48(%rbp,%rdi,4)
	movdqa	%xmm0, 64(%rbp,%rdi,4)
	movdqa	%xmm0, 80(%rbp,%rdi,4)
	movdqa	%xmm0, 96(%rbp,%rdi,4)
	movdqa	%xmm0, 112(%rbp,%rdi,4)
	movdqa	%xmm0, 128(%rbp,%rdi,4)
	movdqa	%xmm0, 144(%rbp,%rdi,4)
	movdqa	%xmm0, 160(%rbp,%rdi,4)
	movdqa	%xmm0, 176(%rbp,%rdi,4)
	addq	$64, %rdi
	addq	$-8, %rsi
	jne	LBB0_22
LBB0_23:
	testq	%rdx, %rdx
	je	LBB0_26
## %bb.24:
	leaq	-48(,%rdi,4), %rsi
	addq	%rbp, %rsi
	shlq	$5, %rdx
	xorl	%edi, %edi
	.p2align	4, 0x90
LBB0_25:                                ## =>This Inner Loop Header: Depth=1
	movdqa	%xmm0, -16(%rsi,%rdi)
	movdqa	%xmm0, (%rsi,%rdi)
	addq	$32, %rdi
	cmpq	%rdi, %rdx
	jne	LBB0_25
LBB0_26:
	cmpq	%r14, %rcx
	je	LBB0_28
	.p2align	4, 0x90
LBB0_27:                                ## =>This Inner Loop Header: Depth=1
	movl	%eax, -64(%rbp,%rcx,4)
	incq	%rcx
	cmpq	%rcx, %r14
	jne	LBB0_27
LBB0_28:
	movq	_DP_TRAINING_LANE0_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-64(%rbp), %rdx
	movq	%r15, %rdi
	movl	%r14d, %ecx
	callq	_drm_dp_dpcd_write
	movl	%eax, %ebx
	sarl	$31, %ebx
	andl	%eax, %ebx
LBB0_29:
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	cmpq	-48(%rbp), %rax
	jne	LBB0_31
## %bb.30:
	movl	%ebx, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_31:
	callq	___stack_chk_fail
	.cfi_endproc
                                        ## -- End function
	.comm	_CLOCK_RECOVERY,4,2             ## @CLOCK_RECOVERY
	.comm	_DP_LINK_BW_SET,4,2             ## @DP_LINK_BW_SET
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"failed to set enhance mode\n"

	.comm	_PRE_EMPHASIS_LEVEL_0,4,2       ## @PRE_EMPHASIS_LEVEL_0
	.comm	_PLL_UNLOCKED,8,3               ## @PLL_UNLOCKED
	.comm	_DP_TIMEOUT_LOOP_COUNT,4,2      ## @DP_TIMEOUT_LOOP_COUNT
L_.str.1:                               ## @.str.1
	.asciz	"Wait for PLL lock timed out\n"

	.comm	_ETIMEDOUT,4,2                  ## @ETIMEDOUT
	.comm	_TRAINING_PTN1,4,2              ## @TRAINING_PTN1
	.comm	_DP_TRAINING_PATTERN_SET,4,2    ## @DP_TRAINING_PATTERN_SET
	.comm	_DP_LINK_SCRAMBLING_DISABLE,4,2 ## @DP_LINK_SCRAMBLING_DISABLE
	.comm	_DP_TRAINING_PATTERN_1,4,2      ## @DP_TRAINING_PATTERN_1
	.comm	_DP_TRAIN_PRE_EMPH_LEVEL_0,4,2  ## @DP_TRAIN_PRE_EMPH_LEVEL_0
	.comm	_DP_TRAIN_VOLTAGE_SWING_LEVEL_0,4,2 ## @DP_TRAIN_VOLTAGE_SWING_LEVEL_0
	.comm	_DP_TRAINING_LANE0_SET,4,2      ## @DP_TRAINING_LANE0_SET
	.no_dead_strip	_analogix_dp_link_start
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function analogix_dp_link_start
_analogix_dp_link_start:                ; @analogix_dp_link_start
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x8, ___stack_chk_guard@GOTPAGE
Lloh1:
	ldr	x8, [x8, ___stack_chk_guard@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	str	x8, [sp, #24]
	ldr	w20, [x0, #8]
Lloh3:
	adrp	x8, _CLOCK_RECOVERY@GOTPAGE
Lloh4:
	ldr	x8, [x8, _CLOCK_RECOVERY@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	str	w8, [x0, #32]
	str	xzr, [x0, #24]
	cmp	w20, #1
	b.lt	LBB0_2
; %bb.1:
	ldr	x0, [x19, #16]
	lsl	x1, x20, #3
	bl	_bzero
LBB0_2:
	ldr	w1, [x19, #12]
	mov	x0, x19
	bl	_analogix_dp_set_link_bandwidth
	ldr	w1, [x19, #8]
	mov	x0, x19
	bl	_analogix_dp_set_lane_count
	ldr	d0, [x19, #8]
	rev64.2s	v0, v0
	str	d0, [sp, #8]
Lloh6:
	adrp	x8, _DP_LINK_BW_SET@GOTPAGE
Lloh7:
	ldr	x8, [x8, _DP_LINK_BW_SET@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	add	x2, sp, #8
	mov	x0, x19
	mov	w3, #2
	bl	_drm_dp_dpcd_write
	tbnz	w0, #31, LBB0_15
; %bb.3:
	mov	x0, x19
	bl	_analogix_dp_set_enhanced_mode
	tbnz	w0, #31, LBB0_16
; %bb.4:
	cmp	w20, #1
	b.lt	LBB0_7
; %bb.5:
	mov	w21, #0
Lloh9:
	adrp	x22, _PRE_EMPHASIS_LEVEL_0@GOTPAGE
Lloh10:
	ldr	x22, [x22, _PRE_EMPHASIS_LEVEL_0@GOTPAGEOFF]
LBB0_6:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x22]
	mov	x0, x19
	mov	x2, x21
	bl	_analogix_dp_set_lane_lane_pre_emphasis
	add	w21, w21, #1
	cmp	w20, w21
	b.ne	LBB0_6
LBB0_7:
	mov	x0, x19
	bl	_analogix_dp_get_pll_lock_status
Lloh11:
	adrp	x21, _PLL_UNLOCKED@GOTPAGE
Lloh12:
	ldr	x21, [x21, _PLL_UNLOCKED@GOTPAGEOFF]
	ldr	x8, [x21]
	cmp	x0, x8
	b.ne	LBB0_11
; %bb.8:
	mov	w22, #-1
Lloh13:
	adrp	x23, _DP_TIMEOUT_LOOP_COUNT@GOTPAGE
Lloh14:
	ldr	x23, [x23, _DP_TIMEOUT_LOOP_COUNT@GOTPAGEOFF]
LBB0_9:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w8, [x23]
	add	w22, w22, #1
	cmp	w22, w8
	b.eq	LBB0_17
; %bb.10:                               ;   in Loop: Header=BB0_9 Depth=1
	mov	w0, #90
	mov	w1, #120
	bl	_usleep_range
	mov	x0, x19
	bl	_analogix_dp_get_pll_lock_status
	ldr	x8, [x21]
	cmp	x0, x8
	b.eq	LBB0_9
LBB0_11:
Lloh15:
	adrp	x8, _TRAINING_PTN1@GOTPAGE
Lloh16:
	ldr	x8, [x8, _TRAINING_PTN1@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_analogix_dp_set_training_pattern
Lloh18:
	adrp	x8, _DP_TRAINING_PATTERN_SET@GOTPAGE
Lloh19:
	ldr	x8, [x8, _DP_TRAINING_PATTERN_SET@GOTPAGEOFF]
Lloh20:
	adrp	x9, _DP_LINK_SCRAMBLING_DISABLE@GOTPAGE
Lloh21:
	ldr	x9, [x9, _DP_LINK_SCRAMBLING_DISABLE@GOTPAGEOFF]
Lloh22:
	ldr	w1, [x8]
Lloh23:
	ldr	w8, [x9]
Lloh24:
	adrp	x9, _DP_TRAINING_PATTERN_1@GOTPAGE
Lloh25:
	ldr	x9, [x9, _DP_TRAINING_PATTERN_1@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_drm_dp_dpcd_writeb
	tbnz	w0, #31, LBB0_15
; %bb.12:
	cmp	w20, #1
	b.lt	LBB0_23
; %bb.13:
Lloh27:
	adrp	x8, _DP_TRAIN_PRE_EMPH_LEVEL_0@GOTPAGE
Lloh28:
	ldr	x8, [x8, _DP_TRAIN_PRE_EMPH_LEVEL_0@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
Lloh30:
	adrp	x9, _DP_TRAIN_VOLTAGE_SWING_LEVEL_0@GOTPAGE
Lloh31:
	ldr	x9, [x9, _DP_TRAIN_VOLTAGE_SWING_LEVEL_0@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	orr	w8, w9, w8
	cmp	w20, #16
	b.hs	LBB0_18
; %bb.14:
	mov	x9, #0
	b	LBB0_21
LBB0_15:
	mov	x21, x0
	b	LBB0_24
LBB0_16:
	mov	x21, x0
	ldr	w0, [x19, #4]
Lloh33:
	adrp	x1, l_.str@PAGE
Lloh34:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
	b	LBB0_24
LBB0_17:
	ldr	w0, [x19, #4]
Lloh35:
	adrp	x1, l_.str.1@PAGE
Lloh36:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_err
Lloh37:
	adrp	x8, _ETIMEDOUT@GOTPAGE
Lloh38:
	ldr	x8, [x8, _ETIMEDOUT@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
	neg	w21, w8
	b	LBB0_24
LBB0_18:
	and	x9, x20, #0xfffffff0
	dup.4s	v0, w8
	add	x10, sp, #8
	add	x10, x10, #32
	mov	x11, x9
LBB0_19:                                ; =>This Inner Loop Header: Depth=1
	stp	q0, q0, [x10, #-32]
	stp	q0, q0, [x10], #64
	subs	x11, x11, #16
	b.ne	LBB0_19
; %bb.20:
	cmp	x9, x20
	b.eq	LBB0_23
LBB0_21:
	add	x10, sp, #8
	add	x10, x10, x9, lsl #2
	sub	x9, x20, x9
LBB0_22:                                ; =>This Inner Loop Header: Depth=1
	str	w8, [x10], #4
	subs	x9, x9, #1
	b.ne	LBB0_22
LBB0_23:
Lloh40:
	adrp	x8, _DP_TRAINING_LANE0_SET@GOTPAGE
Lloh41:
	ldr	x8, [x8, _DP_TRAINING_LANE0_SET@GOTPAGEOFF]
Lloh42:
	ldr	w1, [x8]
	add	x2, sp, #8
	mov	x0, x19
	mov	x3, x20
	bl	_drm_dp_dpcd_write
	cmp	w0, #0
	csel	w21, w0, wzr, lt
LBB0_24:
	ldr	x8, [sp, #24]
Lloh43:
	adrp	x9, ___stack_chk_guard@GOTPAGE
Lloh44:
	ldr	x9, [x9, ___stack_chk_guard@GOTPAGEOFF]
Lloh45:
	ldr	x9, [x9]
	cmp	x9, x8
	b.ne	LBB0_26
; %bb.25:
	mov	x0, x21
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_26:
	bl	___stack_chk_fail
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh22
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpAdd	Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpAdd	Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.cfi_endproc
                                        ; -- End function
	.comm	_CLOCK_RECOVERY,4,2             ; @CLOCK_RECOVERY
	.comm	_DP_LINK_BW_SET,4,2             ; @DP_LINK_BW_SET
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"failed to set enhance mode\n"

	.comm	_PRE_EMPHASIS_LEVEL_0,4,2       ; @PRE_EMPHASIS_LEVEL_0
	.comm	_PLL_UNLOCKED,8,3               ; @PLL_UNLOCKED
	.comm	_DP_TIMEOUT_LOOP_COUNT,4,2      ; @DP_TIMEOUT_LOOP_COUNT
l_.str.1:                               ; @.str.1
	.asciz	"Wait for PLL lock timed out\n"

	.comm	_ETIMEDOUT,4,2                  ; @ETIMEDOUT
	.comm	_TRAINING_PTN1,4,2              ; @TRAINING_PTN1
	.comm	_DP_TRAINING_PATTERN_SET,4,2    ; @DP_TRAINING_PATTERN_SET
	.comm	_DP_LINK_SCRAMBLING_DISABLE,4,2 ; @DP_LINK_SCRAMBLING_DISABLE
	.comm	_DP_TRAINING_PATTERN_1,4,2      ; @DP_TRAINING_PATTERN_1
	.comm	_DP_TRAIN_PRE_EMPH_LEVEL_0,4,2  ; @DP_TRAIN_PRE_EMPH_LEVEL_0
	.comm	_DP_TRAIN_VOLTAGE_SWING_LEVEL_0,4,2 ; @DP_TRAIN_VOLTAGE_SWING_LEVEL_0
	.comm	_DP_TRAINING_LANE0_SET,4,2      ; @DP_TRAINING_LANE0_SET
	.no_dead_strip	_analogix_dp_link_start
.subsections_via_symbols
