	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dpu_hw_sspp_setup_format
_dpu_hw_sspp_setup_format:              ## @dpu_hw_sspp_setup_format
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %ebx
	movl	%edx, -44(%rbp)                 ## 4-byte Spill
	movq	%rsi, %r15
	movq	%rdi, %r14
	movq	_DPU_SSPP_SRC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-48(%rbp), %rdx
	callq	__sspp_subblk_offset
	testq	%r15, %r15
	je	LBB0_32
## %bb.1:
	testq	%rax, %rax
	jne	LBB0_32
## %bb.2:
	movq	_DPU_SSPP_RECT_SOLO@GOTPCREL(%rip), %rax
	cmpl	%ebx, (%rax)
	sete	%al
	movq	_DPU_SSPP_RECT_0@GOTPCREL(%rip), %rcx
	cmpl	%ebx, (%rcx)
	sete	%cl
	orb	%al, %cl
	movq	_SSPP_SRC_FORMAT_REC1@GOTPCREL(%rip), %rax
	cmovneq	_SSPP_SRC_FORMAT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -72(%rbp)                 ## 4-byte Spill
	movq	_SSPP_SRC_UNPACK_PATTERN_REC1@GOTPCREL(%rip), %rax
	cmovneq	_SSPP_SRC_UNPACK_PATTERN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -76(%rbp)                 ## 4-byte Spill
	movq	_SSPP_SRC_OP_MODE_REC1@GOTPCREL(%rip), %rax
	cmovneq	_SSPP_SRC_OP_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	leaq	24(%r14), %rdi
	movl	-48(%rbp), %esi
	movl	%eax, -80(%rbp)                 ## 4-byte Spill
	addl	%eax, %esi
	movq	%rdi, -64(%rbp)                 ## 8-byte Spill
	callq	_DPU_REG_READ
	movq	_MDSS_MDP_OP_FLIP_LR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	_MDSS_MDP_OP_FLIP_UD@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movl	%edx, %ebx
	orl	%ecx, %ebx
	movq	_MDSS_MDP_OP_BWC_EN@GOTPCREL(%rip), %rsi
	orl	(%rsi), %ebx
	movl	%eax, -68(%rbp)                 ## 4-byte Spill
	movq	_MDSS_MDP_OP_PE_OVERRIDE@GOTPCREL(%rip), %rsi
	movq	_DPU_SSPP_FLIP_LR@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	andl	%edi, %r13d
	cmovnel	%ecx, %r13d
	movq	_DPU_SSPP_FLIP_UD@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	andl	%edi, %r12d
	cmovnel	%edx, %r12d
	movl	(%r15), %eax
	movq	_DPU_SSPP_SOURCE_ROTATED_90@GOTPCREL(%rip), %rcx
	testl	%edi, (%rcx)
	movq	%r14, -56(%rbp)                 ## 8-byte Spill
	je	LBB0_6
## %bb.3:
	movq	_DPU_CHROMA_H2V1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	_DPU_CHROMA_H1V2@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	cmpl	%ecx, %eax
	jne	LBB0_5
## %bb.4:
	movl	%edx, %eax
	jmp	LBB0_6
LBB0_5:
	cmpl	%edx, %eax
	cmovel	%ecx, %eax
LBB0_6:
	orl	(%rsi), %ebx
	shll	$23, %eax
	movl	4(%r15), %ecx
	shll	$19, %ecx
	orl	%eax, %ecx
	movq	8(%r15), %rax
	movq	_C3_ALPHA@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdx
	movl	(%rax,%rdx,4), %edx
	shll	$6, %edx
	orl	%ecx, %edx
	movq	_C2_R_Cr@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	(%rax,%rcx,4), %ecx
	shll	$4, %ecx
	movq	_C1_B_Cb@GOTPCREL(%rip), %rsi
	movq	(%rsi), %rsi
	movl	(%rax,%rsi,4), %r14d
	shll	$2, %r14d
	orl	%ecx, %r14d
	orl	%edx, %r14d
	movq	_C0_G_Y@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	orl	(%rax,%rcx,4), %r14d
	movq	_DPU_SSPP_ROT_90@GOTPCREL(%rip), %rax
	testl	%edi, (%rax)
	je	LBB0_8
## %bb.7:
	movl	$11, %edi
	callq	_BIT
	orl	%eax, %r14d
LBB0_8:
	notl	%ebx
	cmpq	$0, 48(%r15)
	je	LBB0_11
## %bb.9:
	movl	4(%r15), %eax
	movq	_DPU_PLANE_INTERLEAVED@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_11
## %bb.10:
	movl	$8, %edi
	callq	_BIT
	orl	%eax, %r14d
LBB0_11:
	movl	-44(%rbp), %ecx                 ## 4-byte Reload
	movl	-68(%rbp), %eax                 ## 4-byte Reload
	andl	%ebx, %eax
	movl	%eax, %ebx
	orl	%r12d, %r13d
	movq	_DPU_SSPP_SOLID_FILL@GOTPCREL(%rip), %rax
	testl	%ecx, (%rax)
	je	LBB0_13
## %bb.12:
	movl	$22, %edi
	callq	_BIT
	orl	%eax, %r14d
LBB0_13:
	movq	_MDSS_MDP_OP_PE_OVERRIDE@GOTPCREL(%rip), %rsi
	orl	%r13d, %ebx
	movq	16(%r15), %rax
	movl	12(%rax), %ecx
	shll	$24, %ecx
	movl	4(%rax), %r13d
	movl	8(%rax), %edx
	shll	$16, %edx
	orl	%ecx, %edx
	shll	$8, %r13d
	orl	%edx, %r13d
	orl	(%rax), %r13d
	movl	24(%r15), %eax
	shll	$12, %eax
	addl	$-4096, %eax                    ## imm = 0xF000
	orl	%r14d, %eax
	movl	28(%r15), %ecx
	shll	$17, %ecx
	movl	32(%r15), %edx
	shll	$18, %edx
	orl	%ecx, %edx
	movl	%ebx, %r14d
	movl	36(%r15), %ebx
	shll	$9, %ebx
	addl	$-512, %ebx                     ## imm = 0xFE00
	orl	%edx, %ebx
	orl	%eax, %ebx
	movl	40(%r15), %eax
	movq	_DPU_FETCH_LINEAR@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_15
## %bb.14:
	movl	%ebx, %r12d
	jmp	LBB0_23
LBB0_15:
	movl	%r14d, %r12d
	movq	%r15, %rdi
	callq	_DPU_FORMAT_IS_UBWC
	xorl	%r14d, %r14d
	testq	%rax, %rax
	je	LBB0_17
## %bb.16:
	movq	_MDSS_MDP_OP_BWC_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
LBB0_17:
	orl	%r12d, %r14d
	movl	40(%r15), %r12d
	shll	$30, %r12d
	orl	%ebx, %r12d
	movq	_SSPP_FETCH_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DPU_FETCH_CONFIG_RESET_VALUE@GOTPCREL(%rip), %rax
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movq	8(%rbx), %rcx
	movl	(%rcx), %edx
	shll	$18, %edx
	orl	(%rax), %edx
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	callq	_DPU_REG_WRITE
	movq	16(%rbx), %rax
	movq	(%rax), %rax
	movl	(%rax), %edi
	callq	_IS_UBWC_20_SUPPORTED
	testq	%rax, %rax
	je	LBB0_22
## %bb.18:
	cmpq	$0, 48(%r15)
	je	LBB0_19
## %bb.20:
	movl	$31, %edi
	callq	_BIT
	jmp	LBB0_21
LBB0_19:
	xorl	%eax, %eax
LBB0_21:
	movq	_SSPP_UBWC_STATIC_CTRL@GOTPCREL(%rip), %rcx
	movq	-56(%rbp), %rdx                 ## 8-byte Reload
	movq	8(%rdx), %rdx
	orl	4(%rdx), %eax
	movl	(%rcx), %esi
	movl	(%rdx), %edx
	shll	$4, %edx
	orl	%eax, %edx
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	callq	_DPU_REG_WRITE
LBB0_22:
	movq	_MDSS_MDP_OP_PE_OVERRIDE@GOTPCREL(%rip), %rsi
LBB0_23:
	orl	(%rsi), %r14d
	movl	%r14d, -44(%rbp)                ## 4-byte Spill
	movq	%r15, %rdi
	callq	_DPU_FORMAT_IS_YUV
	testq	%rax, %rax
	je	LBB0_25
## %bb.24:
	movl	$15, %edi
	callq	_BIT
	orl	%eax, %r12d
LBB0_25:
	movq	%r15, %rdi
	callq	_DPU_FORMAT_IS_DX
	testq	%rax, %rax
	je	LBB0_27
## %bb.26:
	movl	$14, %edi
	callq	_BIT
	orl	%eax, %r12d
LBB0_27:
	movq	_DPU_SSPP_CSC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	-56(%rbp), %r14                 ## 8-byte Reload
	movq	(%r14), %rsi
	callq	_test_bit
	testq	%rax, %rax
	je	LBB0_29
## %bb.28:
	movq	_VIG_OP_CSC_EN@GOTPCREL(%rip), %rax
	movq	_VIG_OP_CSC_SRC_DATAFMT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	%r15, %rdi
	callq	_DPU_FORMAT_IS_YUV
	movq	%r14, %rdi
	movl	%ebx, %esi
	movq	%rax, %rdx
	callq	__sspp_setup_opmode
	jmp	LBB0_31
LBB0_29:
	movq	_DPU_SSPP_CSC_10BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	(%r14), %rsi
	callq	_test_bit
	testq	%rax, %rax
	je	LBB0_31
## %bb.30:
	movq	_VIG_CSC_10_EN@GOTPCREL(%rip), %rax
	movq	_VIG_CSC_10_SRC_DATAFMT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	%r15, %rdi
	callq	_DPU_FORMAT_IS_YUV
	movq	%r14, %rdi
	movl	%ebx, %esi
	movq	%rax, %rdx
	callq	__sspp_setup_csc10_opmode
LBB0_31:
	movl	-72(%rbp), %esi                 ## 4-byte Reload
	addl	-48(%rbp), %esi
	movq	-64(%rbp), %r15                 ## 8-byte Reload
	movq	%r15, %rdi
	movl	%r12d, %edx
	callq	_DPU_REG_WRITE
	movl	-76(%rbp), %esi                 ## 4-byte Reload
	addl	-48(%rbp), %esi
	movq	%r15, %rdi
	movl	%r13d, %edx
	callq	_DPU_REG_WRITE
	movl	-80(%rbp), %esi                 ## 4-byte Reload
	addl	-48(%rbp), %esi
	movq	%r15, %rdi
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	callq	_DPU_REG_WRITE
	movq	_SSPP_UBWC_ERROR_STATUS@GOTPCREL(%rip), %rax
	movl	-48(%rbp), %ebx
	addl	(%rax), %ebx
	movl	$31, %edi
	callq	_BIT
	movq	%r15, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_DPU_REG_WRITE
LBB0_32:
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DPU_SSPP_SRC,4,2               ## @DPU_SSPP_SRC
	.comm	_DPU_SSPP_RECT_SOLO,4,2         ## @DPU_SSPP_RECT_SOLO
	.comm	_DPU_SSPP_RECT_0,4,2            ## @DPU_SSPP_RECT_0
	.comm	_SSPP_SRC_OP_MODE,4,2           ## @SSPP_SRC_OP_MODE
	.comm	_SSPP_SRC_UNPACK_PATTERN,4,2    ## @SSPP_SRC_UNPACK_PATTERN
	.comm	_SSPP_SRC_FORMAT,4,2            ## @SSPP_SRC_FORMAT
	.comm	_SSPP_SRC_OP_MODE_REC1,4,2      ## @SSPP_SRC_OP_MODE_REC1
	.comm	_SSPP_SRC_UNPACK_PATTERN_REC1,4,2 ## @SSPP_SRC_UNPACK_PATTERN_REC1
	.comm	_SSPP_SRC_FORMAT_REC1,4,2       ## @SSPP_SRC_FORMAT_REC1
	.comm	_MDSS_MDP_OP_FLIP_LR,4,2        ## @MDSS_MDP_OP_FLIP_LR
	.comm	_MDSS_MDP_OP_FLIP_UD,4,2        ## @MDSS_MDP_OP_FLIP_UD
	.comm	_MDSS_MDP_OP_BWC_EN,4,2         ## @MDSS_MDP_OP_BWC_EN
	.comm	_MDSS_MDP_OP_PE_OVERRIDE,4,2    ## @MDSS_MDP_OP_PE_OVERRIDE
	.comm	_DPU_SSPP_FLIP_LR,4,2           ## @DPU_SSPP_FLIP_LR
	.comm	_DPU_SSPP_FLIP_UD,4,2           ## @DPU_SSPP_FLIP_UD
	.comm	_DPU_SSPP_SOURCE_ROTATED_90,4,2 ## @DPU_SSPP_SOURCE_ROTATED_90
	.comm	_DPU_CHROMA_H2V1,4,2            ## @DPU_CHROMA_H2V1
	.comm	_DPU_CHROMA_H1V2,4,2            ## @DPU_CHROMA_H1V2
	.comm	_C3_ALPHA,8,3                   ## @C3_ALPHA
	.comm	_C2_R_Cr,8,3                    ## @C2_R_Cr
	.comm	_C1_B_Cb,8,3                    ## @C1_B_Cb
	.comm	_C0_G_Y,8,3                     ## @C0_G_Y
	.comm	_DPU_SSPP_ROT_90,4,2            ## @DPU_SSPP_ROT_90
	.comm	_DPU_PLANE_INTERLEAVED,4,2      ## @DPU_PLANE_INTERLEAVED
	.comm	_DPU_SSPP_SOLID_FILL,4,2        ## @DPU_SSPP_SOLID_FILL
	.comm	_DPU_FETCH_LINEAR,4,2           ## @DPU_FETCH_LINEAR
	.comm	_SSPP_FETCH_CONFIG,4,2          ## @SSPP_FETCH_CONFIG
	.comm	_DPU_FETCH_CONFIG_RESET_VALUE,4,2 ## @DPU_FETCH_CONFIG_RESET_VALUE
	.comm	_SSPP_UBWC_STATIC_CTRL,4,2      ## @SSPP_UBWC_STATIC_CTRL
	.comm	_DPU_SSPP_CSC,4,2               ## @DPU_SSPP_CSC
	.comm	_VIG_OP_CSC_EN,4,2              ## @VIG_OP_CSC_EN
	.comm	_VIG_OP_CSC_SRC_DATAFMT,4,2     ## @VIG_OP_CSC_SRC_DATAFMT
	.comm	_DPU_SSPP_CSC_10BIT,4,2         ## @DPU_SSPP_CSC_10BIT
	.comm	_VIG_CSC_10_EN,4,2              ## @VIG_CSC_10_EN
	.comm	_VIG_CSC_10_SRC_DATAFMT,4,2     ## @VIG_CSC_10_SRC_DATAFMT
	.comm	_SSPP_UBWC_ERROR_STATUS,4,2     ## @SSPP_UBWC_ERROR_STATUS
	.no_dead_strip	_dpu_hw_sspp_setup_format
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dpu_hw_sspp_setup_format
_dpu_hw_sspp_setup_format:              ; @dpu_hw_sspp_setup_format
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x3
	mov	x22, x2
	mov	x21, x1
	mov	x20, x0
Lloh0:
	adrp	x8, _DPU_SSPP_SRC@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DPU_SSPP_SRC@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	add	x2, sp, #12
	bl	__sspp_subblk_offset
	cbz	x21, LBB0_26
; %bb.1:
	cbnz	x0, LBB0_26
; %bb.2:
Lloh3:
	adrp	x8, _DPU_SSPP_RECT_SOLO@GOTPAGE
Lloh4:
	ldr	x8, [x8, _DPU_SSPP_RECT_SOLO@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
Lloh6:
	adrp	x9, _DPU_SSPP_RECT_0@GOTPAGE
Lloh7:
	ldr	x9, [x9, _DPU_SSPP_RECT_0@GOTPAGEOFF]
	cmp	w8, w19
Lloh8:
	ldr	w8, [x9]
Lloh9:
	adrp	x9, _SSPP_SRC_FORMAT@GOTPAGE
Lloh10:
	ldr	x9, [x9, _SSPP_SRC_FORMAT@GOTPAGEOFF]
Lloh11:
	adrp	x10, _SSPP_SRC_FORMAT_REC1@GOTPAGE
Lloh12:
	ldr	x10, [x10, _SSPP_SRC_FORMAT_REC1@GOTPAGEOFF]
	ccmp	w8, w19, #4, ne
	csel	x8, x9, x10, eq
Lloh13:
	adrp	x9, _SSPP_SRC_UNPACK_PATTERN@GOTPAGE
Lloh14:
	ldr	x9, [x9, _SSPP_SRC_UNPACK_PATTERN@GOTPAGEOFF]
Lloh15:
	adrp	x10, _SSPP_SRC_UNPACK_PATTERN_REC1@GOTPAGE
Lloh16:
	ldr	x10, [x10, _SSPP_SRC_UNPACK_PATTERN_REC1@GOTPAGEOFF]
	ldr	w8, [x8]
	str	w8, [sp, #4]                    ; 4-byte Folded Spill
	csel	x8, x9, x10, eq
Lloh17:
	adrp	x9, _SSPP_SRC_OP_MODE@GOTPAGE
Lloh18:
	ldr	x9, [x9, _SSPP_SRC_OP_MODE@GOTPAGEOFF]
Lloh19:
	adrp	x10, _SSPP_SRC_OP_MODE_REC1@GOTPAGE
Lloh20:
	ldr	x10, [x10, _SSPP_SRC_OP_MODE_REC1@GOTPAGEOFF]
	ldr	w26, [x8]
	csel	x8, x9, x10, eq
	ldr	w25, [x8]
	add	x19, x20, #24
	ldr	w8, [sp, #12]
	add	w1, w25, w8
	mov	x0, x19
	bl	_DPU_REG_READ
	mov	x23, x0
Lloh21:
	adrp	x8, _MDSS_MDP_OP_FLIP_LR@GOTPAGE
Lloh22:
	ldr	x8, [x8, _MDSS_MDP_OP_FLIP_LR@GOTPAGEOFF]
Lloh23:
	ldr	w10, [x8]
Lloh24:
	adrp	x8, _MDSS_MDP_OP_FLIP_UD@GOTPAGE
Lloh25:
	ldr	x8, [x8, _MDSS_MDP_OP_FLIP_UD@GOTPAGEOFF]
Lloh26:
	ldr	w11, [x8]
	orr	w8, w11, w10
Lloh27:
	adrp	x9, _MDSS_MDP_OP_BWC_EN@GOTPAGE
Lloh28:
	ldr	x9, [x9, _MDSS_MDP_OP_BWC_EN@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh30:
	adrp	x9, _MDSS_MDP_OP_PE_OVERRIDE@GOTPAGE
Lloh31:
	ldr	x9, [x9, _MDSS_MDP_OP_PE_OVERRIDE@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
Lloh33:
	adrp	x12, _DPU_SSPP_FLIP_LR@GOTPAGE
Lloh34:
	ldr	x12, [x12, _DPU_SSPP_FLIP_LR@GOTPAGEOFF]
Lloh35:
	ldr	w12, [x12]
	tst	w12, w22
	csel	w24, wzr, w10, eq
Lloh36:
	adrp	x10, _DPU_SSPP_FLIP_UD@GOTPAGE
Lloh37:
	ldr	x10, [x10, _DPU_SSPP_FLIP_UD@GOTPAGEOFF]
Lloh38:
	ldr	w10, [x10]
	tst	w10, w22
	csel	w27, wzr, w11, eq
	ldr	w10, [x21]
Lloh39:
	adrp	x11, _DPU_SSPP_SOURCE_ROTATED_90@GOTPAGE
Lloh40:
	ldr	x11, [x11, _DPU_SSPP_SOURCE_ROTATED_90@GOTPAGEOFF]
Lloh41:
	ldr	w11, [x11]
	tst	w11, w22
	str	w25, [sp, #8]                   ; 4-byte Folded Spill
	b.eq	LBB0_4
; %bb.3:
Lloh42:
	adrp	x11, _DPU_CHROMA_H2V1@GOTPAGE
Lloh43:
	ldr	x11, [x11, _DPU_CHROMA_H2V1@GOTPAGEOFF]
Lloh44:
	adrp	x12, _DPU_CHROMA_H1V2@GOTPAGE
Lloh45:
	ldr	x12, [x12, _DPU_CHROMA_H1V2@GOTPAGEOFF]
Lloh46:
	ldr	w11, [x11]
Lloh47:
	ldr	w12, [x12]
	cmp	w10, w12
	csel	w13, w11, w10, eq
	cmp	w10, w11
	csel	w10, w12, w13, eq
LBB0_4:
	orr	w28, w8, w9
	ldr	w8, [x21, #4]
	lsl	w8, w8, #19
	ldr	x9, [x21, #8]
Lloh48:
	adrp	x11, _C3_ALPHA@GOTPAGE
Lloh49:
	ldr	x11, [x11, _C3_ALPHA@GOTPAGEOFF]
Lloh50:
	ldr	x11, [x11]
	ldr	w11, [x9, x11, lsl #2]
	orr	w8, w8, w10, lsl #23
Lloh51:
	adrp	x10, _C2_R_Cr@GOTPAGE
Lloh52:
	ldr	x10, [x10, _C2_R_Cr@GOTPAGEOFF]
Lloh53:
	ldr	x10, [x10]
	ldr	w10, [x9, x10, lsl #2]
	orr	w8, w8, w11, lsl #6
Lloh54:
	adrp	x11, _C1_B_Cb@GOTPAGE
Lloh55:
	ldr	x11, [x11, _C1_B_Cb@GOTPAGEOFF]
Lloh56:
	ldr	x11, [x11]
	ldr	w11, [x9, x11, lsl #2]
	orr	w8, w8, w10, lsl #4
Lloh57:
	adrp	x10, _C0_G_Y@GOTPAGE
Lloh58:
	ldr	x10, [x10, _C0_G_Y@GOTPAGEOFF]
Lloh59:
	ldr	x10, [x10]
	ldr	w9, [x9, x10, lsl #2]
	orr	w8, w8, w11, lsl #2
	orr	w25, w8, w9
Lloh60:
	adrp	x8, _DPU_SSPP_ROT_90@GOTPAGE
Lloh61:
	ldr	x8, [x8, _DPU_SSPP_ROT_90@GOTPAGEOFF]
Lloh62:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_6
; %bb.5:
	mov	w0, #11
	bl	_BIT
	orr	w25, w0, w25
LBB0_6:
	bic	w23, w23, w28
	ldr	x8, [x21, #48]
	cbz	x8, LBB0_9
; %bb.7:
	ldr	w8, [x21, #4]
Lloh63:
	adrp	x9, _DPU_PLANE_INTERLEAVED@GOTPAGE
Lloh64:
	ldr	x9, [x9, _DPU_PLANE_INTERLEAVED@GOTPAGEOFF]
Lloh65:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_9
; %bb.8:
	mov	w0, #8
	bl	_BIT
	orr	w25, w0, w25
LBB0_9:
	orr	w23, w24, w23
Lloh66:
	adrp	x8, _DPU_SSPP_SOLID_FILL@GOTPAGE
Lloh67:
	ldr	x8, [x8, _DPU_SSPP_SOLID_FILL@GOTPAGEOFF]
Lloh68:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_11
; %bb.10:
	mov	w0, #22
	bl	_BIT
	orr	w25, w0, w25
LBB0_11:
	orr	w23, w23, w27
	ldr	x8, [x21, #16]
	ldp	w10, w9, [x8, #8]
	lsl	w10, w10, #16
	orr	w28, w10, w9, lsl #24
	ldp	w27, w24, [x8]
	ldp	w8, w9, [x21, #24]
	lsl	w8, w8, #12
	sub	w8, w8, #1, lsl #12             ; =4096
	ldp	w10, w11, [x21, #32]
	lsl	w11, w11, #9
	sub	w11, w11, #512
	orr	w9, w25, w9, lsl #17
	orr	w8, w9, w8
	orr	w8, w8, w10, lsl #18
	orr	w22, w8, w11
	ldr	w8, [x21, #40]
Lloh69:
	adrp	x9, _DPU_FETCH_LINEAR@GOTPAGE
Lloh70:
	ldr	x9, [x9, _DPU_FETCH_LINEAR@GOTPAGEOFF]
Lloh71:
	ldr	w9, [x9]
	cmp	w8, w9
	b.eq	LBB0_17
; %bb.12:
	mov	x0, x21
	bl	_DPU_FORMAT_IS_UBWC
Lloh72:
	adrp	x8, _MDSS_MDP_OP_BWC_EN@GOTPAGE
Lloh73:
	ldr	x8, [x8, _MDSS_MDP_OP_BWC_EN@GOTPAGEOFF]
Lloh74:
	ldr	w8, [x8]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w23, w8, w23
	ldr	w8, [x21, #40]
	orr	w22, w22, w8, lsl #30
Lloh75:
	adrp	x8, _SSPP_FETCH_CONFIG@GOTPAGE
Lloh76:
	ldr	x8, [x8, _SSPP_FETCH_CONFIG@GOTPAGEOFF]
Lloh77:
	ldr	w1, [x8]
Lloh78:
	adrp	x8, _DPU_FETCH_CONFIG_RESET_VALUE@GOTPAGE
Lloh79:
	ldr	x8, [x8, _DPU_FETCH_CONFIG_RESET_VALUE@GOTPAGEOFF]
Lloh80:
	ldr	w8, [x8]
	ldr	x9, [x20, #8]
	ldr	w9, [x9]
	orr	w2, w8, w9, lsl #18
	mov	x0, x19
	bl	_DPU_REG_WRITE
	ldr	x8, [x20, #16]
	ldr	x8, [x8]
	ldr	w0, [x8]
	bl	_IS_UBWC_20_SUPPORTED
	cbz	x0, LBB0_17
; %bb.13:
	ldr	x8, [x21, #48]
	cbz	x8, LBB0_15
; %bb.14:
	mov	w0, #31
	bl	_BIT
	b	LBB0_16
LBB0_15:
	mov	w0, #0
LBB0_16:
Lloh81:
	adrp	x8, _SSPP_UBWC_STATIC_CTRL@GOTPAGE
Lloh82:
	ldr	x8, [x8, _SSPP_UBWC_STATIC_CTRL@GOTPAGEOFF]
Lloh83:
	ldr	w1, [x8]
	ldr	x8, [x20, #8]
	ldp	w8, w9, [x8]
	orr	w9, w9, w0
	orr	w2, w9, w8, lsl #4
	mov	x0, x19
	bl	_DPU_REG_WRITE
LBB0_17:
Lloh84:
	adrp	x8, _MDSS_MDP_OP_PE_OVERRIDE@GOTPAGE
Lloh85:
	ldr	x8, [x8, _MDSS_MDP_OP_PE_OVERRIDE@GOTPAGEOFF]
	orr	w24, w28, w24, lsl #8
Lloh86:
	ldr	w25, [x8]
	mov	x0, x21
	bl	_DPU_FORMAT_IS_YUV
	cbz	x0, LBB0_19
; %bb.18:
	mov	w0, #15
	bl	_BIT
	orr	w22, w0, w22
LBB0_19:
	ldr	w28, [sp, #8]                   ; 4-byte Folded Reload
	orr	w24, w24, w27
	orr	w23, w25, w23
	mov	x0, x21
	bl	_DPU_FORMAT_IS_DX
	cbz	x0, LBB0_21
; %bb.20:
	mov	w0, #14
	bl	_BIT
	orr	w22, w0, w22
LBB0_21:
	ldr	w27, [sp, #4]                   ; 4-byte Folded Reload
Lloh87:
	adrp	x8, _DPU_SSPP_CSC@GOTPAGE
Lloh88:
	ldr	x8, [x8, _DPU_SSPP_CSC@GOTPAGEOFF]
Lloh89:
	ldr	w0, [x8]
	ldr	x1, [x20]
	bl	_test_bit
	cbz	x0, LBB0_23
; %bb.22:
Lloh90:
	adrp	x8, _VIG_OP_CSC_EN@GOTPAGE
Lloh91:
	ldr	x8, [x8, _VIG_OP_CSC_EN@GOTPAGEOFF]
Lloh92:
	ldr	w8, [x8]
Lloh93:
	adrp	x9, _VIG_OP_CSC_SRC_DATAFMT@GOTPAGE
Lloh94:
	ldr	x9, [x9, _VIG_OP_CSC_SRC_DATAFMT@GOTPAGEOFF]
Lloh95:
	ldr	w9, [x9]
	orr	w25, w9, w8
	mov	x0, x21
	bl	_DPU_FORMAT_IS_YUV
	mov	x2, x0
	mov	x0, x20
	mov	x1, x25
	bl	__sspp_setup_opmode
	b	LBB0_25
LBB0_23:
Lloh96:
	adrp	x8, _DPU_SSPP_CSC_10BIT@GOTPAGE
Lloh97:
	ldr	x8, [x8, _DPU_SSPP_CSC_10BIT@GOTPAGEOFF]
Lloh98:
	ldr	w0, [x8]
	ldr	x1, [x20]
	bl	_test_bit
	cbz	x0, LBB0_25
; %bb.24:
Lloh99:
	adrp	x8, _VIG_CSC_10_EN@GOTPAGE
Lloh100:
	ldr	x8, [x8, _VIG_CSC_10_EN@GOTPAGEOFF]
Lloh101:
	ldr	w8, [x8]
Lloh102:
	adrp	x9, _VIG_CSC_10_SRC_DATAFMT@GOTPAGE
Lloh103:
	ldr	x9, [x9, _VIG_CSC_10_SRC_DATAFMT@GOTPAGEOFF]
Lloh104:
	ldr	w9, [x9]
	orr	w25, w9, w8
	mov	x0, x21
	bl	_DPU_FORMAT_IS_YUV
	mov	x2, x0
	mov	x0, x20
	mov	x1, x25
	bl	__sspp_setup_csc10_opmode
LBB0_25:
	ldr	w8, [sp, #12]
	add	w1, w8, w27
	mov	x0, x19
	mov	x2, x22
	bl	_DPU_REG_WRITE
	ldr	w8, [sp, #12]
	add	w1, w8, w26
	mov	x0, x19
	mov	x2, x24
	bl	_DPU_REG_WRITE
	ldr	w8, [sp, #12]
	add	w1, w8, w28
	mov	x0, x19
	mov	x2, x23
	bl	_DPU_REG_WRITE
Lloh105:
	adrp	x8, _SSPP_UBWC_ERROR_STATUS@GOTPAGE
Lloh106:
	ldr	x8, [x8, _SSPP_UBWC_ERROR_STATUS@GOTPAGEOFF]
Lloh107:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	add	w20, w9, w8
	mov	w0, #31
	bl	_BIT
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_DPU_REG_WRITE
LBB0_26:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh46
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.cfi_endproc
                                        ; -- End function
	.comm	_DPU_SSPP_SRC,4,2               ; @DPU_SSPP_SRC
	.comm	_DPU_SSPP_RECT_SOLO,4,2         ; @DPU_SSPP_RECT_SOLO
	.comm	_DPU_SSPP_RECT_0,4,2            ; @DPU_SSPP_RECT_0
	.comm	_SSPP_SRC_OP_MODE,4,2           ; @SSPP_SRC_OP_MODE
	.comm	_SSPP_SRC_UNPACK_PATTERN,4,2    ; @SSPP_SRC_UNPACK_PATTERN
	.comm	_SSPP_SRC_FORMAT,4,2            ; @SSPP_SRC_FORMAT
	.comm	_SSPP_SRC_OP_MODE_REC1,4,2      ; @SSPP_SRC_OP_MODE_REC1
	.comm	_SSPP_SRC_UNPACK_PATTERN_REC1,4,2 ; @SSPP_SRC_UNPACK_PATTERN_REC1
	.comm	_SSPP_SRC_FORMAT_REC1,4,2       ; @SSPP_SRC_FORMAT_REC1
	.comm	_MDSS_MDP_OP_FLIP_LR,4,2        ; @MDSS_MDP_OP_FLIP_LR
	.comm	_MDSS_MDP_OP_FLIP_UD,4,2        ; @MDSS_MDP_OP_FLIP_UD
	.comm	_MDSS_MDP_OP_BWC_EN,4,2         ; @MDSS_MDP_OP_BWC_EN
	.comm	_MDSS_MDP_OP_PE_OVERRIDE,4,2    ; @MDSS_MDP_OP_PE_OVERRIDE
	.comm	_DPU_SSPP_FLIP_LR,4,2           ; @DPU_SSPP_FLIP_LR
	.comm	_DPU_SSPP_FLIP_UD,4,2           ; @DPU_SSPP_FLIP_UD
	.comm	_DPU_SSPP_SOURCE_ROTATED_90,4,2 ; @DPU_SSPP_SOURCE_ROTATED_90
	.comm	_DPU_CHROMA_H2V1,4,2            ; @DPU_CHROMA_H2V1
	.comm	_DPU_CHROMA_H1V2,4,2            ; @DPU_CHROMA_H1V2
	.comm	_C3_ALPHA,8,3                   ; @C3_ALPHA
	.comm	_C2_R_Cr,8,3                    ; @C2_R_Cr
	.comm	_C1_B_Cb,8,3                    ; @C1_B_Cb
	.comm	_C0_G_Y,8,3                     ; @C0_G_Y
	.comm	_DPU_SSPP_ROT_90,4,2            ; @DPU_SSPP_ROT_90
	.comm	_DPU_PLANE_INTERLEAVED,4,2      ; @DPU_PLANE_INTERLEAVED
	.comm	_DPU_SSPP_SOLID_FILL,4,2        ; @DPU_SSPP_SOLID_FILL
	.comm	_DPU_FETCH_LINEAR,4,2           ; @DPU_FETCH_LINEAR
	.comm	_SSPP_FETCH_CONFIG,4,2          ; @SSPP_FETCH_CONFIG
	.comm	_DPU_FETCH_CONFIG_RESET_VALUE,4,2 ; @DPU_FETCH_CONFIG_RESET_VALUE
	.comm	_SSPP_UBWC_STATIC_CTRL,4,2      ; @SSPP_UBWC_STATIC_CTRL
	.comm	_DPU_SSPP_CSC,4,2               ; @DPU_SSPP_CSC
	.comm	_VIG_OP_CSC_EN,4,2              ; @VIG_OP_CSC_EN
	.comm	_VIG_OP_CSC_SRC_DATAFMT,4,2     ; @VIG_OP_CSC_SRC_DATAFMT
	.comm	_DPU_SSPP_CSC_10BIT,4,2         ; @DPU_SSPP_CSC_10BIT
	.comm	_VIG_CSC_10_EN,4,2              ; @VIG_CSC_10_EN
	.comm	_VIG_CSC_10_SRC_DATAFMT,4,2     ; @VIG_CSC_10_SRC_DATAFMT
	.comm	_SSPP_UBWC_ERROR_STATUS,4,2     ; @SSPP_UBWC_ERROR_STATUS
	.no_dead_strip	_dpu_hw_sspp_setup_format
.subsections_via_symbols
