	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v1_0_sw_init
_vcn_v1_0_sw_init:                      ## @vcn_v1_0_sw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	_SOC15_IH_CLIENTID_VCN@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	_VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	8(%rdi), %rcx
	addq	$48, %rcx
	callq	_amdgpu_irq_add_id
	testl	%eax, %eax
	jne	LBB0_17
## %bb.1:
	cmpl	$0, (%r15)
	jle	LBB0_5
## %bb.2:
	xorl	%ebx, %ebx
	movq	_VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE@GOTPCREL(%rip), %r12
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %esi
	movl	(%r12), %edx
	addl	%ebx, %edx
	movq	8(%r15), %rcx
	addq	$48, %rcx
	movq	%r15, %rdi
	callq	_amdgpu_irq_add_id
	testl	%eax, %eax
	jne	LBB0_17
## %bb.3:                               ##   in Loop: Header=BB0_4 Depth=1
	incl	%ebx
	cmpl	(%r15), %ebx
	jl	LBB0_4
LBB0_5:
	movl	(%r14), %esi
	movq	8(%r15), %rcx
	addq	$48, %rcx
	movq	%r15, %rdi
	movl	$126, %edx
	callq	_amdgpu_irq_add_id
	testl	%eax, %eax
	jne	LBB0_17
## %bb.6:
	movq	%r15, %rdi
	callq	_amdgpu_vcn_sw_init
	testl	%eax, %eax
	jne	LBB0_17
## %bb.7:
	movq	80(%r15), %rax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_9
## %bb.8:
	movq	72(%r15), %rax
	movq	96(%r15), %rcx
	movq	(%rax), %rdx
	movq	_AMDGPU_UCODE_ID_VCN@GOTPCREL(%rip), %rsi
	movq	(%rsi), %rbx
	movq	%rbx, %rdi
	shlq	$4, %rdi
	movq	%rbx, (%rcx,%rdi)
	movq	(%rsi), %rsi
	shlq	$4, %rsi
	movq	%rax, 8(%rcx,%rsi)
	movl	(%rdx), %edi
	callq	_le32_to_cpu
	movq	_PAGE_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_ALIGN
	addl	%eax, 88(%r15)
	leaq	L_.str(%rip), %rdi
	callq	_DRM_INFO
LBB0_9:
	movq	%r15, %rdi
	callq	_amdgpu_vcn_resume
	testl	%eax, %eax
	jne	LBB0_17
## %bb.10:
	movq	8(%r15), %r14
	movl	64(%r14), %edi
	addq	$64, %r14
	leaq	L_.str.1(%rip), %rsi
	xorl	%eax, %eax
	callq	_sprintf
	movq	8(%r15), %rcx
	addq	$48, %rcx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	$512, %edx                      ## imm = 0x200
	xorl	%r8d, %r8d
	callq	_amdgpu_ring_init
	testl	%eax, %eax
	jne	LBB0_17
## %bb.11:
	movq	_UVD@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_mmUVD_SCRATCH9@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	8(%r15), %rcx
	movq	%rax, 40(%rcx)
	movq	%rax, 56(%r15)
	movl	(%rbx), %edi
	movq	_mmUVD_GPCOM_VCPU_DATA0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	8(%r15), %rcx
	movq	%rax, 32(%rcx)
	movq	%rax, 48(%r15)
	movl	(%rbx), %edi
	movq	_mmUVD_GPCOM_VCPU_DATA1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	8(%r15), %rcx
	movq	%rax, 24(%rcx)
	movq	%rax, 40(%r15)
	movl	(%rbx), %edi
	movq	_mmUVD_GPCOM_VCPU_CMD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	8(%r15), %rcx
	movq	%rax, 16(%rcx)
	movq	%rax, 32(%r15)
	movl	(%rbx), %edi
	movq	_mmUVD_NO_OP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	8(%r15), %r14
	movq	%rax, 8(%r14)
	movq	%rax, 24(%r15)
	cmpl	$0, (%r15)
	jle	LBB0_15
## %bb.12:
	leaq	L_.str.2(%rip), %rbx
	xorl	%r13d, %r13d
	xorl	%r12d, %r12d
LBB0_14:                                ## =>This Inner Loop Header: Depth=1
	movq	56(%r14), %r14
	movl	(%r14,%r13), %edi
	addq	%r13, %r14
	movq	%rbx, %rsi
	movl	%r12d, %edx
	xorl	%eax, %eax
	callq	_sprintf
	movq	8(%r15), %rcx
	addq	$48, %rcx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	$512, %edx                      ## imm = 0x200
	xorl	%r8d, %r8d
	callq	_amdgpu_ring_init
	testl	%eax, %eax
	jne	LBB0_17
## %bb.13:                              ##   in Loop: Header=BB0_14 Depth=1
	incq	%r12
	movslq	(%r15), %rax
	movq	8(%r15), %r14
	addq	$4, %r13
	cmpq	%rax, %r12
	jl	LBB0_14
LBB0_15:
	movl	52(%r14), %edi
	addq	$52, %r14
	leaq	L_.str.3(%rip), %rsi
	xorl	%eax, %eax
	callq	_sprintf
	movq	8(%r15), %rcx
	addq	$48, %rcx
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	$512, %edx                      ## imm = 0x200
	xorl	%r8d, %r8d
	callq	_amdgpu_ring_init
	testl	%eax, %eax
	jne	LBB0_17
## %bb.16:
	movq	_vcn_v1_0_pause_dpg_mode@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 64(%r15)
	movq	_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmUVD_JPEG_PITCH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	8(%r15), %rcx
	movq	%rax, (%rcx)
	movq	%rax, 16(%r15)
	xorl	%eax, %eax
LBB0_17:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_SOC15_IH_CLIENTID_VCN,4,2      ## @SOC15_IH_CLIENTID_VCN
	.comm	_VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,4,2 ## @VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT
	.comm	_VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,4,2 ## @VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_VCN,8,3        ## @AMDGPU_UCODE_ID_VCN
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"PSP loading VCN firmware\n"

L_.str.1:                               ## @.str.1
	.asciz	"vcn_dec"

	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_SCRATCH9,4,2             ## @mmUVD_SCRATCH9
	.comm	_mmUVD_GPCOM_VCPU_DATA0,4,2     ## @mmUVD_GPCOM_VCPU_DATA0
	.comm	_mmUVD_GPCOM_VCPU_DATA1,4,2     ## @mmUVD_GPCOM_VCPU_DATA1
	.comm	_mmUVD_GPCOM_VCPU_CMD,4,2       ## @mmUVD_GPCOM_VCPU_CMD
	.comm	_mmUVD_NO_OP,4,2                ## @mmUVD_NO_OP
L_.str.2:                               ## @.str.2
	.asciz	"vcn_enc%d"

L_.str.3:                               ## @.str.3
	.asciz	"vcn_jpeg"

	.comm	_vcn_v1_0_pause_dpg_mode,4,2    ## @vcn_v1_0_pause_dpg_mode
	.comm	_mmUVD_JPEG_PITCH,4,2           ## @mmUVD_JPEG_PITCH
	.no_dead_strip	_vcn_v1_0_sw_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v1_0_sw_init
_vcn_v1_0_sw_init:                      ; @vcn_v1_0_sw_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x20, _SOC15_IH_CLIENTID_VCN@GOTPAGE
Lloh1:
	ldr	x20, [x20, _SOC15_IH_CLIENTID_VCN@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh2:
	adrp	x8, _VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT@GOTPAGE
Lloh3:
	ldr	x8, [x8, _VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	ldr	x8, [x0, #8]
	add	x3, x8, #48
	bl	_amdgpu_irq_add_id
	cbnz	w0, LBB0_17
; %bb.1:
	ldr	w8, [x19]
	cmp	w8, #1
	b.lt	LBB0_5
; %bb.2:
	mov	w21, #0
Lloh5:
	adrp	x22, _VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE@GOTPAGE
Lloh6:
	ldr	x22, [x22, _VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE@GOTPAGEOFF]
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x20]
	ldr	w8, [x22]
	add	w2, w21, w8
	ldr	x8, [x19, #8]
	add	x3, x8, #48
	mov	x0, x19
	bl	_amdgpu_irq_add_id
	cbnz	w0, LBB0_17
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	add	w21, w21, #1
	ldr	w8, [x19]
	cmp	w21, w8
	b.lt	LBB0_3
LBB0_5:
	ldr	w1, [x20]
	ldr	x8, [x19, #8]
	add	x3, x8, #48
	mov	x0, x19
	mov	w2, #126
	bl	_amdgpu_irq_add_id
	cbnz	w0, LBB0_17
; %bb.6:
	mov	x0, x19
	bl	_amdgpu_vcn_sw_init
	cbnz	w0, LBB0_17
; %bb.7:
	ldr	x8, [x19, #80]
Lloh7:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh8:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh9:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_9
; %bb.8:
	ldr	x8, [x19, #72]
	ldr	x9, [x8]
Lloh10:
	adrp	x10, _AMDGPU_UCODE_ID_VCN@GOTPAGE
Lloh11:
	ldr	x10, [x10, _AMDGPU_UCODE_ID_VCN@GOTPAGEOFF]
	ldr	x11, [x10]
	ldr	x12, [x19, #96]
	lsl	x13, x11, #4
	str	x11, [x12, x13]
	ldr	x10, [x10]
	add	x10, x12, x10, lsl #4
	str	x8, [x10, #8]
	ldr	w0, [x9]
	bl	_le32_to_cpu
Lloh12:
	adrp	x8, _PAGE_SIZE@GOTPAGE
Lloh13:
	ldr	x8, [x8, _PAGE_SIZE@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	bl	_ALIGN
	ldr	w8, [x19, #88]
	add	w8, w8, w0
	str	w8, [x19, #88]
Lloh15:
	adrp	x0, l_.str@PAGE
Lloh16:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_INFO
LBB0_9:
	mov	x0, x19
	bl	_amdgpu_vcn_resume
	cbnz	w0, LBB0_17
; %bb.10:
	ldr	x20, [x19, #8]
	ldr	w0, [x20, #64]!
Lloh17:
	adrp	x1, l_.str.1@PAGE
Lloh18:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_sprintf
	ldr	x8, [x19, #8]
	add	x3, x8, #48
	mov	x0, x19
	mov	x1, x20
	mov	w2, #512
	mov	w4, #0
	bl	_amdgpu_ring_init
	cbnz	w0, LBB0_17
; %bb.11:
Lloh19:
	adrp	x22, _UVD@GOTPAGE
Lloh20:
	ldr	x22, [x22, _UVD@GOTPAGEOFF]
	ldr	w0, [x22]
Lloh21:
	adrp	x8, _mmUVD_SCRATCH9@GOTPAGE
Lloh22:
	ldr	x8, [x8, _mmUVD_SCRATCH9@GOTPAGEOFF]
Lloh23:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	x8, [x19, #8]
	str	x0, [x8, #40]
	str	x0, [x19, #56]
	ldr	w0, [x22]
Lloh24:
	adrp	x8, _mmUVD_GPCOM_VCPU_DATA0@GOTPAGE
Lloh25:
	ldr	x8, [x8, _mmUVD_GPCOM_VCPU_DATA0@GOTPAGEOFF]
Lloh26:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	x8, [x19, #8]
	str	x0, [x8, #32]
	str	x0, [x19, #48]
	ldr	w0, [x22]
Lloh27:
	adrp	x8, _mmUVD_GPCOM_VCPU_DATA1@GOTPAGE
Lloh28:
	ldr	x8, [x8, _mmUVD_GPCOM_VCPU_DATA1@GOTPAGEOFF]
Lloh29:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	x8, [x19, #8]
	str	x0, [x8, #24]
	str	x0, [x19, #40]
	ldr	w0, [x22]
Lloh30:
	adrp	x8, _mmUVD_GPCOM_VCPU_CMD@GOTPAGE
Lloh31:
	ldr	x8, [x8, _mmUVD_GPCOM_VCPU_CMD@GOTPAGEOFF]
Lloh32:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	x8, [x19, #8]
	str	x0, [x8, #16]
	str	x0, [x19, #32]
	ldr	w0, [x22]
Lloh33:
	adrp	x8, _mmUVD_NO_OP@GOTPAGE
Lloh34:
	ldr	x8, [x8, _mmUVD_NO_OP@GOTPAGEOFF]
Lloh35:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	x20, [x19, #8]
	str	x0, [x20, #8]
	str	x0, [x19, #24]
	ldr	w8, [x19]
	cmp	w8, #1
	b.lt	LBB0_15
; %bb.12:
	mov	x23, #0
	mov	x24, #0
Lloh36:
	adrp	x21, l_.str.2@PAGE
Lloh37:
	add	x21, x21, l_.str.2@PAGEOFF
LBB0_13:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x20, #56]
	add	x20, x8, x23
	ldr	w0, [x20]
	str	x24, [sp]
	mov	x1, x21
	bl	_sprintf
	ldr	x8, [x19, #8]
	add	x3, x8, #48
	mov	x0, x19
	mov	x1, x20
	mov	w2, #512
	mov	w4, #0
	bl	_amdgpu_ring_init
	cbnz	w0, LBB0_17
; %bb.14:                               ;   in Loop: Header=BB0_13 Depth=1
	add	x24, x24, #1
	ldrsw	x8, [x19]
	ldr	x20, [x19, #8]
	add	x23, x23, #4
	cmp	x24, x8
	b.lt	LBB0_13
LBB0_15:
	ldr	w0, [x20, #52]!
Lloh38:
	adrp	x1, l_.str.3@PAGE
Lloh39:
	add	x1, x1, l_.str.3@PAGEOFF
	bl	_sprintf
	ldr	x8, [x19, #8]
	add	x3, x8, #48
	mov	x0, x19
	mov	x1, x20
	mov	w2, #512
	mov	w4, #0
	bl	_amdgpu_ring_init
	cbnz	w0, LBB0_17
; %bb.16:
Lloh40:
	adrp	x8, _vcn_v1_0_pause_dpg_mode@GOTPAGE
Lloh41:
	ldr	x8, [x8, _vcn_v1_0_pause_dpg_mode@GOTPAGEOFF]
Lloh42:
	ldr	w8, [x8]
	str	w8, [x19, #64]
	ldr	w0, [x22]
Lloh43:
	adrp	x8, _mmUVD_JPEG_PITCH@GOTPAGE
Lloh44:
	ldr	x8, [x8, _mmUVD_JPEG_PITCH@GOTPAGEOFF]
Lloh45:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x8, x0
	mov	w0, #0
	ldr	x9, [x19, #8]
	str	x8, [x9]
	str	x8, [x19, #16]
LBB0_17:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpAdd	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpAdd	Lloh36, Lloh37
	.loh AdrpAdd	Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.cfi_endproc
                                        ; -- End function
	.comm	_SOC15_IH_CLIENTID_VCN,4,2      ; @SOC15_IH_CLIENTID_VCN
	.comm	_VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,4,2 ; @VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT
	.comm	_VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,4,2 ; @VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_VCN,8,3        ; @AMDGPU_UCODE_ID_VCN
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"PSP loading VCN firmware\n"

l_.str.1:                               ; @.str.1
	.asciz	"vcn_dec"

	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_SCRATCH9,4,2             ; @mmUVD_SCRATCH9
	.comm	_mmUVD_GPCOM_VCPU_DATA0,4,2     ; @mmUVD_GPCOM_VCPU_DATA0
	.comm	_mmUVD_GPCOM_VCPU_DATA1,4,2     ; @mmUVD_GPCOM_VCPU_DATA1
	.comm	_mmUVD_GPCOM_VCPU_CMD,4,2       ; @mmUVD_GPCOM_VCPU_CMD
	.comm	_mmUVD_NO_OP,4,2                ; @mmUVD_NO_OP
l_.str.2:                               ; @.str.2
	.asciz	"vcn_enc%d"

l_.str.3:                               ; @.str.3
	.asciz	"vcn_jpeg"

	.comm	_vcn_v1_0_pause_dpg_mode,4,2    ; @vcn_v1_0_pause_dpg_mode
	.comm	_mmUVD_JPEG_PITCH,4,2           ; @mmUVD_JPEG_PITCH
	.no_dead_strip	_vcn_v1_0_sw_init
.subsections_via_symbols
