	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function intel_update_pipe_config
_intel_update_pipe_config:              ## @intel_update_pipe_config
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %rbx
	movq	%rdi, %r12
	movl	20(%rsi), %edi
	callq	_to_intel_crtc
	movq	%rax, %r15
	movl	8(%rax), %edi
	callq	_to_i915
	movq	%rax, %r14
	movl	16(%rbx), %eax
	movl	%eax, 4(%r15)
	movl	(%r15), %edi
	callq	_PIPESRC
	movl	(%rbx), %ecx
	movl	4(%rbx), %esi
	shll	$16, %ecx
	addl	$-65536, %ecx                   ## imm = 0xFFFF0000
	decl	%esi
	orl	%ecx, %esi
	movl	%eax, %edi
	callq	_I915_WRITE
	movq	%r14, %rdi
	callq	_INTEL_GEN
	cmpl	$9, %eax
	jl	LBB0_3
## %bb.1:
	movq	%rbx, %rdi
	callq	_skl_detach_scalers
	cmpq	$0, 8(%rbx)
	je	LBB0_8
## %bb.2:
	movq	%rbx, %rdi
	callq	_skylake_pfit_enable
	jmp	LBB0_8
LBB0_3:
	movq	%r14, %rdi
	callq	_HAS_PCH_SPLIT
	testq	%rax, %rax
	je	LBB0_8
## %bb.4:
	cmpq	$0, 8(%rbx)
	je	LBB0_6
## %bb.5:
	movq	%rbx, %rdi
	callq	_ironlake_pfit_enable
	jmp	LBB0_8
LBB0_6:
	cmpq	$0, 8(%r12)
	je	LBB0_8
## %bb.7:
	movq	%r12, %rdi
	callq	_ironlake_pfit_disable
LBB0_8:
	movq	%r14, %rdi
	callq	_INTEL_GEN
	cmpl	$11, %eax
	jl	LBB0_9
## %bb.10:
	movq	%r15, %rdi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_icl_set_pipe_chicken           ## TAILCALL
LBB0_9:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.no_dead_strip	_intel_update_pipe_config
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function intel_update_pipe_config
_intel_update_pipe_config:              ; @intel_update_pipe_config
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x21, x1
	mov	x22, x0
	ldr	w0, [x1, #20]
	bl	_to_intel_crtc
	mov	x19, x0
	ldr	w0, [x0, #8]
	bl	_to_i915
	mov	x20, x0
	ldr	w8, [x21, #16]
	str	w8, [x19, #4]
	ldr	w0, [x19]
	bl	_PIPESRC
	ldp	w8, w9, [x21]
	lsl	w8, w8, #16
	sub	w8, w8, #16, lsl #12            ; =65536
	sub	w9, w9, #1
	orr	w1, w8, w9
	bl	_I915_WRITE
	mov	x0, x20
	bl	_INTEL_GEN
	cmp	w0, #9
	b.lt	LBB0_3
; %bb.1:
	mov	x0, x21
	bl	_skl_detach_scalers
	ldr	x8, [x21, #8]
	cbz	x8, LBB0_8
; %bb.2:
	mov	x0, x21
	bl	_skylake_pfit_enable
	b	LBB0_8
LBB0_3:
	mov	x0, x20
	bl	_HAS_PCH_SPLIT
	cbz	x0, LBB0_8
; %bb.4:
	ldr	x8, [x21, #8]
	cbz	x8, LBB0_6
; %bb.5:
	mov	x0, x21
	bl	_ironlake_pfit_enable
	b	LBB0_8
LBB0_6:
	ldr	x8, [x22, #8]
	cbz	x8, LBB0_8
; %bb.7:
	mov	x0, x22
	bl	_ironlake_pfit_disable
LBB0_8:
	mov	x0, x20
	bl	_INTEL_GEN
	cmp	w0, #11
	b.lt	LBB0_10
; %bb.9:
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_icl_set_pipe_chicken
LBB0_10:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.cfi_endproc
                                        ; -- End function
	.no_dead_strip	_intel_update_pipe_config
.subsections_via_symbols
