	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mmhub_v9_4_update_medium_grain_clock_gating
_mmhub_v9_4_update_medium_grain_clock_gating: ## @mmhub_v9_4_update_medium_grain_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, -48(%rbp)                 ## 8-byte Spill
	movq	_MMHUB_NUM_INSTANCES@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	jle	LBB0_18
## %bb.1:
	movl	%esi, %ebx
	movq	_mmDAGB1_CNTL_MISC2@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	_mmDAGB0_CNTL_MISC2@GOTPCREL(%rip), %rax
	subl	(%rax), %r12d
	xorl	%r15d, %r15d
	jmp	LBB0_2
	.p2align	4, 0x90
LBB0_17:                                ##   in Loop: Header=BB0_2 Depth=1
	incl	%r15d
	movq	_MMHUB_NUM_INSTANCES@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r15d
	jge	LBB0_18
LBB0_2:                                 ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_9 Depth 2
	movq	_MMHUB@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmATCL2_0_ATC_L2_MISC_CG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_MMHUB_INSTANCE_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	imull	%r15d, %ecx
	xorl	%esi, %esi
	callq	_RREG32_SOC15_OFFSET
	testl	%ebx, %ebx
	je	LBB0_5
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	_AMD_CG_SUPPORT_MC_MGCG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	-48(%rbp), %rdx                 ## 8-byte Reload
	testl	%ecx, (%rdx)
	je	LBB0_5
## %bb.4:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	_ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r8d
	orl	%eax, %r8d
	cmpl	%r8d, %eax
	jne	LBB0_7
	jmp	LBB0_8
	.p2align	4, 0x90
LBB0_5:                                 ##   in Loop: Header=BB0_2 Depth=1
	movq	_ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r8d
	notl	%r8d
	andl	%eax, %r8d
	cmpl	%r8d, %eax
	je	LBB0_8
LBB0_7:                                 ##   in Loop: Header=BB0_2 Depth=1
	movq	_MMHUB@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmATCL2_0_ATC_L2_MISC_CG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_MMHUB_INSTANCE_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	imull	%r15d, %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15_OFFSET
LBB0_8:                                 ##   in Loop: Header=BB0_2 Depth=1
	xorl	%r14d, %r14d
	xorl	%r13d, %r13d
	.p2align	4, 0x90
LBB0_9:                                 ##   Parent Loop BB0_2 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movq	_MMHUB@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmDAGB0_CNTL_MISC2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_MMHUB_INSTANCE_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	imull	%r15d, %ecx
	addl	%r14d, %ecx
	xorl	%esi, %esi
	callq	_RREG32_SOC15_OFFSET
	testl	%ebx, %ebx
	je	LBB0_12
## %bb.10:                              ##   in Loop: Header=BB0_9 Depth=2
	movq	_AMD_CG_SUPPORT_MC_MGCG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	-48(%rbp), %rdx                 ## 8-byte Reload
	testl	%ecx, (%rdx)
	je	LBB0_12
## %bb.11:                              ##   in Loop: Header=BB0_9 Depth=2
	movq	_DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r8d
	movq	_DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r8d
	movq	_DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r8d
	movq	_DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r8d
	movq	_DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r8d
	movq	_DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r8d
	notl	%r8d
	andl	%eax, %r8d
	cmpl	%r8d, %eax
	jne	LBB0_14
	jmp	LBB0_15
	.p2align	4, 0x90
LBB0_12:                                ##   in Loop: Header=BB0_9 Depth=2
	movq	_DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r8d
	orl	%eax, %r8d
	movq	_DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r8d
	movq	_DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r8d
	movq	_DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r8d
	movq	_DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r8d
	movq	_DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r8d
	cmpl	%r8d, %eax
	je	LBB0_15
LBB0_14:                                ##   in Loop: Header=BB0_9 Depth=2
	movq	_MMHUB@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmDAGB0_CNTL_MISC2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_MMHUB_INSTANCE_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	imull	%r15d, %ecx
	addl	%r14d, %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15_OFFSET
LBB0_15:                                ##   in Loop: Header=BB0_9 Depth=2
	movl	%r15d, %eax
	xorl	$1, %eax
	movl	%r13d, %ecx
	xorl	$3, %ecx
	orl	%eax, %ecx
	je	LBB0_17
## %bb.16:                              ##   in Loop: Header=BB0_9 Depth=2
	leal	1(%r13), %eax
	addl	%r12d, %r14d
	cmpl	$4, %r13d
	movl	%eax, %r13d
	jb	LBB0_9
	jmp	LBB0_17
LBB0_18:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_mmDAGB1_CNTL_MISC2,4,2         ## @mmDAGB1_CNTL_MISC2
	.comm	_mmDAGB0_CNTL_MISC2,4,2         ## @mmDAGB0_CNTL_MISC2
	.comm	_MMHUB_NUM_INSTANCES,4,2        ## @MMHUB_NUM_INSTANCES
	.comm	_MMHUB,4,2                      ## @MMHUB
	.comm	_mmATCL2_0_ATC_L2_MISC_CG,4,2   ## @mmATCL2_0_ATC_L2_MISC_CG
	.comm	_MMHUB_INSTANCE_REGISTER_OFFSET,4,2 ## @MMHUB_INSTANCE_REGISTER_OFFSET
	.comm	_AMD_CG_SUPPORT_MC_MGCG,4,2     ## @AMD_CG_SUPPORT_MC_MGCG
	.comm	_ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK,4,2 ## @ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK
	.no_dead_strip	_mmhub_v9_4_update_medium_grain_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mmhub_v9_4_update_medium_grain_clock_gating
_mmhub_v9_4_update_medium_grain_clock_gating: ; @mmhub_v9_4_update_medium_grain_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
Lloh0:
	adrp	x8, _MMHUB_NUM_INSTANCES@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MMHUB_NUM_INSTANCES@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cmp	w8, #1
	b.lt	LBB0_16
; %bb.1:
	mov	x19, x1
	mov	x20, x0
	mov	w22, #0
Lloh3:
	adrp	x8, _mmDAGB1_CNTL_MISC2@GOTPAGE
Lloh4:
	ldr	x8, [x8, _mmDAGB1_CNTL_MISC2@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
Lloh6:
	adrp	x23, _mmDAGB0_CNTL_MISC2@GOTPAGE
Lloh7:
	ldr	x23, [x23, _mmDAGB0_CNTL_MISC2@GOTPAGEOFF]
	ldr	w9, [x23]
	sub	w24, w8, w9
Lloh8:
	adrp	x25, _MMHUB@GOTPAGE
Lloh9:
	ldr	x25, [x25, _MMHUB@GOTPAGEOFF]
Lloh10:
	adrp	x27, _MMHUB_INSTANCE_REGISTER_OFFSET@GOTPAGE
Lloh11:
	ldr	x27, [x27, _MMHUB_INSTANCE_REGISTER_OFFSET@GOTPAGEOFF]
Lloh12:
	adrp	x26, _DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPAGE
Lloh13:
	ldr	x26, [x26, _DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:                                 ;   in Loop: Header=BB0_3 Depth=1
	add	w22, w22, #1
Lloh14:
	adrp	x8, _MMHUB_NUM_INSTANCES@GOTPAGE
Lloh15:
	ldr	x8, [x8, _MMHUB_NUM_INSTANCES@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
	cmp	w22, w8
	b.ge	LBB0_16
LBB0_3:                                 ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_9 Depth 2
	ldr	w0, [x25]
Lloh17:
	adrp	x8, _mmATCL2_0_ATC_L2_MISC_CG@GOTPAGE
Lloh18:
	ldr	x8, [x8, _mmATCL2_0_ATC_L2_MISC_CG@GOTPAGEOFF]
Lloh19:
	ldr	w2, [x8]
	ldr	w8, [x27]
	mul	w3, w8, w22
	mov	w1, #0
	bl	_RREG32_SOC15_OFFSET
	cbz	w19, LBB0_6
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	ldr	w8, [x20]
Lloh20:
	adrp	x9, _AMD_CG_SUPPORT_MC_MGCG@GOTPAGE
Lloh21:
	ldr	x9, [x9, _AMD_CG_SUPPORT_MC_MGCG@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_3 Depth=1
Lloh23:
	adrp	x8, _ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK@GOTPAGE
Lloh24:
	ldr	x8, [x8, _ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
	orr	w4, w8, w0
	cmp	w0, w4
	b.ne	LBB0_7
	b	LBB0_8
LBB0_6:                                 ;   in Loop: Header=BB0_3 Depth=1
Lloh26:
	adrp	x8, _ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK@GOTPAGE
Lloh27:
	ldr	x8, [x8, _ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
	bic	w4, w0, w8
	cmp	w0, w4
	b.eq	LBB0_8
LBB0_7:                                 ;   in Loop: Header=BB0_3 Depth=1
	ldr	w0, [x25]
Lloh29:
	adrp	x8, _mmATCL2_0_ATC_L2_MISC_CG@GOTPAGE
Lloh30:
	ldr	x8, [x8, _mmATCL2_0_ATC_L2_MISC_CG@GOTPAGEOFF]
Lloh31:
	ldr	w2, [x8]
	ldr	w8, [x27]
	mul	w3, w8, w22
	mov	w1, #0
	bl	_WREG32_SOC15_OFFSET
LBB0_8:                                 ;   in Loop: Header=BB0_3 Depth=1
	mov	w21, #0
	mov	w28, #0
LBB0_9:                                 ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ldr	w0, [x25]
	ldr	w2, [x23]
	ldr	w8, [x27]
	madd	w3, w22, w8, w21
	mov	w1, #0
	bl	_RREG32_SOC15_OFFSET
	cbz	w19, LBB0_12
; %bb.10:                               ;   in Loop: Header=BB0_9 Depth=2
	ldr	w8, [x20]
Lloh32:
	adrp	x9, _AMD_CG_SUPPORT_MC_MGCG@GOTPAGE
Lloh33:
	ldr	x9, [x9, _AMD_CG_SUPPORT_MC_MGCG@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_9 Depth=2
Lloh35:
	adrp	x8, _DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPAGE
Lloh36:
	ldr	x8, [x8, _DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPAGEOFF]
Lloh37:
	ldr	w8, [x8]
Lloh38:
	adrp	x9, _DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPAGE
Lloh39:
	ldr	x9, [x9, _DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh41:
	adrp	x9, _DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPAGE
Lloh42:
	ldr	x9, [x9, _DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh44:
	adrp	x9, _DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPAGE
Lloh45:
	ldr	x9, [x9, _DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh47:
	adrp	x9, _DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPAGE
Lloh48:
	ldr	x9, [x9, _DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPAGEOFF]
Lloh49:
	ldr	w9, [x9]
	orr	w8, w8, w9
	ldr	w9, [x26]
	orr	w8, w8, w9
	bic	w4, w0, w8
	cmp	w0, w4
	b.ne	LBB0_13
	b	LBB0_14
LBB0_12:                                ;   in Loop: Header=BB0_9 Depth=2
Lloh50:
	adrp	x8, _DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPAGE
Lloh51:
	ldr	x8, [x8, _DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPAGEOFF]
Lloh52:
	ldr	w8, [x8]
Lloh53:
	adrp	x9, _DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPAGE
Lloh54:
	ldr	x9, [x9, _DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPAGEOFF]
Lloh55:
	ldr	w9, [x9]
Lloh56:
	adrp	x10, _DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPAGE
Lloh57:
	ldr	x10, [x10, _DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPAGEOFF]
Lloh58:
	ldr	w10, [x10]
Lloh59:
	adrp	x11, _DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPAGE
Lloh60:
	ldr	x11, [x11, _DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPAGEOFF]
Lloh61:
	ldr	w11, [x11]
Lloh62:
	adrp	x12, _DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPAGE
Lloh63:
	ldr	x12, [x12, _DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPAGEOFF]
Lloh64:
	ldr	w12, [x12]
	ldr	w13, [x26]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w4, w8, w13
	cmp	w0, w4
	b.eq	LBB0_14
LBB0_13:                                ;   in Loop: Header=BB0_9 Depth=2
	ldr	w0, [x25]
	ldr	w2, [x23]
	ldr	w8, [x27]
	madd	w3, w22, w8, w21
	mov	w1, #0
	bl	_WREG32_SOC15_OFFSET
LBB0_14:                                ;   in Loop: Header=BB0_9 Depth=2
	cmp	w28, #3
	ccmp	w22, #1, #0, eq
	b.eq	LBB0_2
; %bb.15:                               ;   in Loop: Header=BB0_9 Depth=2
	add	w8, w28, #1
	add	w21, w21, w24
	cmp	w28, #4
	mov	x28, x8
	b.lo	LBB0_9
	b	LBB0_2
LBB0_16:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.cfi_endproc
                                        ; -- End function
	.comm	_mmDAGB1_CNTL_MISC2,4,2         ; @mmDAGB1_CNTL_MISC2
	.comm	_mmDAGB0_CNTL_MISC2,4,2         ; @mmDAGB0_CNTL_MISC2
	.comm	_MMHUB_NUM_INSTANCES,4,2        ; @MMHUB_NUM_INSTANCES
	.comm	_MMHUB,4,2                      ; @MMHUB
	.comm	_mmATCL2_0_ATC_L2_MISC_CG,4,2   ; @mmATCL2_0_ATC_L2_MISC_CG
	.comm	_MMHUB_INSTANCE_REGISTER_OFFSET,4,2 ; @MMHUB_INSTANCE_REGISTER_OFFSET
	.comm	_AMD_CG_SUPPORT_MC_MGCG,4,2     ; @AMD_CG_SUPPORT_MC_MGCG
	.comm	_ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK,4,2 ; @ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK
	.no_dead_strip	_mmhub_v9_4_update_medium_grain_clock_gating
.subsections_via_symbols
