	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function i8xx_compute_dpll
_i8xx_compute_dpll:                     ## @i8xx_compute_dpll
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r12
	movq	%rsi, %r15
	movq	%rdi, %rbx
	movq	(%rdi), %rdi
	callq	_to_i915
	movq	%rax, %r14
	movq	%rbx, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	callq	_i9xx_update_pll_dividers
	movq	_DPLL_VGA_MODE_DIS@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	_INTEL_OUTPUT_LVDS@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_intel_crtc_has_type
	movl	4(%r15), %edx
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	decb	%dl
	movl	$1, %ebx
	movl	%edx, %ecx
	shll	%cl, %ebx
	movq	_DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %ebx
	orl	%r13d, %ebx
	jmp	LBB0_6
LBB0_2:
	leal	-2(%rdx), %ebx
	movq	_DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %ebx
	cmpl	$2, %edx
	jne	LBB0_4
## %bb.3:
	movq	_PLL_P1_DIVIDE_BY_TWO@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
LBB0_4:
	orl	%r13d, %ebx
	cmpl	$4, 8(%r15)
	jne	LBB0_6
## %bb.5:
	movq	_PLL_P2_DIVIDE_BY_4@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
LBB0_6:
	movq	%r14, %rdi
	callq	_IS_I830
	testq	%rax, %rax
	jne	LBB0_8
## %bb.7:
	movq	_INTEL_OUTPUT_DVO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_intel_crtc_has_type
	testq	%rax, %rax
	je	LBB0_9
LBB0_8:
	movq	_DPLL_DVO_2X_MODE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
LBB0_9:
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_intel_crtc_has_type
	testq	%rax, %rax
	je	LBB0_12
## %bb.10:
	movq	%r14, %rdi
	callq	_intel_panel_use_ssc
	testq	%rax, %rax
	je	LBB0_12
## %bb.11:
	movq	_PLLB_REF_INPUT_SPREADSPECTRUMIN@GOTPCREL(%rip), %rax
	jmp	LBB0_13
LBB0_12:
	movq	_PLL_REF_INPUT_DREFCLK@GOTPCREL(%rip), %rax
LBB0_13:
	orl	(%rax), %ebx
	movq	_DPLL_VCO_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	%ebx, (%r15)
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DPLL_VGA_MODE_DIS,4,2          ## @DPLL_VGA_MODE_DIS
	.comm	_INTEL_OUTPUT_LVDS,4,2          ## @INTEL_OUTPUT_LVDS
	.comm	_DPLL_FPA01_P1_POST_DIV_SHIFT,4,2 ## @DPLL_FPA01_P1_POST_DIV_SHIFT
	.comm	_PLL_P1_DIVIDE_BY_TWO,4,2       ## @PLL_P1_DIVIDE_BY_TWO
	.comm	_PLL_P2_DIVIDE_BY_4,4,2         ## @PLL_P2_DIVIDE_BY_4
	.comm	_INTEL_OUTPUT_DVO,4,2           ## @INTEL_OUTPUT_DVO
	.comm	_DPLL_DVO_2X_MODE,4,2           ## @DPLL_DVO_2X_MODE
	.comm	_PLLB_REF_INPUT_SPREADSPECTRUMIN,4,2 ## @PLLB_REF_INPUT_SPREADSPECTRUMIN
	.comm	_PLL_REF_INPUT_DREFCLK,4,2      ## @PLL_REF_INPUT_DREFCLK
	.comm	_DPLL_VCO_ENABLE,4,2            ## @DPLL_VCO_ENABLE
	.no_dead_strip	_i8xx_compute_dpll
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function i8xx_compute_dpll
_i8xx_compute_dpll:                     ; @i8xx_compute_dpll
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x21, x2
	mov	x19, x1
	mov	x22, x0
	ldr	x0, [x0]
	bl	_to_i915
	mov	x20, x0
	mov	x0, x22
	mov	x1, x19
	mov	x2, x21
	bl	_i9xx_update_pll_dividers
Lloh0:
	adrp	x8, _DPLL_VGA_MODE_DIS@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DPLL_VGA_MODE_DIS@GOTPAGEOFF]
Lloh2:
	ldr	w22, [x8]
Lloh3:
	adrp	x21, _INTEL_OUTPUT_LVDS@GOTPAGE
Lloh4:
	ldr	x21, [x21, _INTEL_OUTPUT_LVDS@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_intel_crtc_has_type
	ldr	w8, [x19, #4]
	cbz	x0, LBB0_2
; %bb.1:
	sub	w8, w8, #1
	mov	w9, #1
	lsl	w8, w9, w8
Lloh5:
	adrp	x9, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGE
Lloh6:
	ldr	x9, [x9, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	b	LBB0_4
LBB0_2:
Lloh8:
	adrp	x9, _PLL_P1_DIVIDE_BY_TWO@GOTPAGE
Lloh9:
	ldr	x9, [x9, _PLL_P1_DIVIDE_BY_TWO@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
	subs	w8, w8, #2
Lloh11:
	adrp	x10, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGE
Lloh12:
	ldr	x10, [x10, _DPLL_FPA01_P1_POST_DIV_SHIFT@GOTPAGEOFF]
Lloh13:
	ldr	w10, [x10]
	lsl	w8, w8, w10
	csel	w8, w9, w8, eq
	orr	w22, w8, w22
	ldr	w8, [x19, #8]
	cmp	w8, #4
	b.ne	LBB0_5
; %bb.3:
Lloh14:
	adrp	x8, _PLL_P2_DIVIDE_BY_4@GOTPAGE
Lloh15:
	ldr	x8, [x8, _PLL_P2_DIVIDE_BY_4@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
LBB0_4:
	orr	w22, w8, w22
LBB0_5:
	mov	x0, x20
	bl	_IS_I830
	cbnz	x0, LBB0_7
; %bb.6:
Lloh17:
	adrp	x8, _INTEL_OUTPUT_DVO@GOTPAGE
Lloh18:
	ldr	x8, [x8, _INTEL_OUTPUT_DVO@GOTPAGEOFF]
Lloh19:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_intel_crtc_has_type
	cbz	x0, LBB0_8
LBB0_7:
Lloh20:
	adrp	x8, _DPLL_DVO_2X_MODE@GOTPAGE
Lloh21:
	ldr	x8, [x8, _DPLL_DVO_2X_MODE@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
	orr	w22, w8, w22
LBB0_8:
	ldr	w1, [x21]
	mov	x0, x19
	bl	_intel_crtc_has_type
	cbz	x0, LBB0_11
; %bb.9:
	mov	x0, x20
	bl	_intel_panel_use_ssc
	cbz	x0, LBB0_11
; %bb.10:
Lloh23:
	adrp	x8, _PLLB_REF_INPUT_SPREADSPECTRUMIN@GOTPAGE
Lloh24:
	ldr	x8, [x8, _PLLB_REF_INPUT_SPREADSPECTRUMIN@GOTPAGEOFF]
	b	LBB0_12
LBB0_11:
Lloh25:
	adrp	x8, _PLL_REF_INPUT_DREFCLK@GOTPAGE
Lloh26:
	ldr	x8, [x8, _PLL_REF_INPUT_DREFCLK@GOTPAGEOFF]
LBB0_12:
	ldr	w8, [x8]
	orr	w8, w8, w22
Lloh27:
	adrp	x9, _DPLL_VCO_ENABLE@GOTPAGE
Lloh28:
	ldr	x9, [x9, _DPLL_VCO_ENABLE@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x19]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.cfi_endproc
                                        ; -- End function
	.comm	_DPLL_VGA_MODE_DIS,4,2          ; @DPLL_VGA_MODE_DIS
	.comm	_INTEL_OUTPUT_LVDS,4,2          ; @INTEL_OUTPUT_LVDS
	.comm	_DPLL_FPA01_P1_POST_DIV_SHIFT,4,2 ; @DPLL_FPA01_P1_POST_DIV_SHIFT
	.comm	_PLL_P1_DIVIDE_BY_TWO,4,2       ; @PLL_P1_DIVIDE_BY_TWO
	.comm	_PLL_P2_DIVIDE_BY_4,4,2         ; @PLL_P2_DIVIDE_BY_4
	.comm	_INTEL_OUTPUT_DVO,4,2           ; @INTEL_OUTPUT_DVO
	.comm	_DPLL_DVO_2X_MODE,4,2           ; @DPLL_DVO_2X_MODE
	.comm	_PLLB_REF_INPUT_SPREADSPECTRUMIN,4,2 ; @PLLB_REF_INPUT_SPREADSPECTRUMIN
	.comm	_PLL_REF_INPUT_DREFCLK,4,2      ; @PLL_REF_INPUT_DREFCLK
	.comm	_DPLL_VCO_ENABLE,4,2            ; @DPLL_VCO_ENABLE
	.no_dead_strip	_i8xx_compute_dpll
.subsections_via_symbols
