	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v10_0_rlc_resume
_gfx_v10_0_rlc_resume:                  ## @gfx_v10_0_rlc_resume
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	callq	_amdgpu_sriov_vf
	movq	%rax, %rcx
	xorl	%eax, %eax
	testq	%rcx, %rcx
	je	LBB0_1
LBB0_12:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
LBB0_1:
	movq	(%rbx), %rax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_4
## %bb.2:
	movq	%rbx, %rdi
	callq	_gfx_v10_0_wait_for_rlc_autoload_complete
	testl	%eax, %eax
	jne	LBB0_12
## %bb.3:
	movq	%rbx, %rdi
	callq	_gfx_v10_0_init_pg
	movq	%rbx, %rdi
	callq	_gfx_v10_0_rlc_enable_srm
	jmp	LBB0_11
LBB0_4:
	movq	8(%rbx), %rax
	movq	%rbx, %rdi
	callq	*8(%rax)
	movq	_GC@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movq	_mmRLC_CGCG_CGLS_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmRLC_PG_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movq	(%rbx), %rax
	movq	_AMDGPU_FW_LOAD_DIRECT@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_6
## %bb.5:
	movq	%rbx, %rdi
	callq	_gfx_v10_0_rlc_load_microcode
	testl	%eax, %eax
	jne	LBB0_12
	jmp	LBB0_9
LBB0_6:
	movq	_AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_9
## %bb.7:
	movq	%rbx, %rdi
	callq	_gfx_v10_0_rlc_backdoor_autoload_enable
	testl	%eax, %eax
	jne	LBB0_12
LBB0_9:
	movq	%rbx, %rdi
	callq	_gfx_v10_0_init_pg
	movq	8(%rbx), %rax
	movq	%rbx, %rdi
	callq	*(%rax)
	movq	(%rbx), %rax
	movq	_AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_11
## %bb.10:
	movq	%rbx, %rdi
	callq	_gfx_v10_0_wait_for_rlc_autoload_complete
	testl	%eax, %eax
	jne	LBB0_12
LBB0_11:
	xorl	%eax, %eax
	jmp	LBB0_12
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_GC,4,2                         ## @GC
	.comm	_mmRLC_CGCG_CGLS_CTRL,4,2       ## @mmRLC_CGCG_CGLS_CTRL
	.comm	_mmRLC_PG_CNTL,4,2              ## @mmRLC_PG_CNTL
	.comm	_AMDGPU_FW_LOAD_DIRECT,8,3      ## @AMDGPU_FW_LOAD_DIRECT
	.comm	_AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,8,3 ## @AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO
	.no_dead_strip	_gfx_v10_0_rlc_resume
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v10_0_rlc_resume
_gfx_v10_0_rlc_resume:                  ; @gfx_v10_0_rlc_resume
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_3
LBB0_1:
	mov	w0, #0
LBB0_2:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_3:
	ldr	x8, [x19]
Lloh0:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_6
; %bb.4:
	mov	x0, x19
	bl	_gfx_v10_0_wait_for_rlc_autoload_complete
	cbnz	w0, LBB0_2
; %bb.5:
	mov	x0, x19
	bl	_gfx_v10_0_init_pg
	mov	x0, x19
	bl	_gfx_v10_0_rlc_enable_srm
	b	LBB0_1
LBB0_6:
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	mov	x0, x19
	blr	x8
Lloh3:
	adrp	x20, _GC@GOTPAGE
Lloh4:
	ldr	x20, [x20, _GC@GOTPAGEOFF]
	ldr	w0, [x20]
Lloh5:
	adrp	x8, _mmRLC_CGCG_CGLS_CTRL@GOTPAGE
Lloh6:
	ldr	x8, [x8, _mmRLC_CGCG_CGLS_CTRL@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x20]
Lloh8:
	adrp	x8, _mmRLC_PG_CNTL@GOTPAGE
Lloh9:
	ldr	x8, [x8, _mmRLC_PG_CNTL@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	x8, [x19]
Lloh11:
	adrp	x9, _AMDGPU_FW_LOAD_DIRECT@GOTPAGE
Lloh12:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_DIRECT@GOTPAGEOFF]
Lloh13:
	ldr	x9, [x9]
Lloh14:
	adrp	x20, _AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO@GOTPAGE
Lloh15:
	ldr	x20, [x20, _AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO@GOTPAGEOFF]
	cmp	x8, x9
	b.ne	LBB0_8
; %bb.7:
	mov	x0, x19
	bl	_gfx_v10_0_rlc_load_microcode
	cbnz	w0, LBB0_2
	b	LBB0_10
LBB0_8:
	ldr	x9, [x20]
	cmp	x8, x9
	b.ne	LBB0_10
; %bb.9:
	mov	x0, x19
	bl	_gfx_v10_0_rlc_backdoor_autoload_enable
	cbnz	w0, LBB0_2
LBB0_10:
	mov	x0, x19
	bl	_gfx_v10_0_init_pg
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	mov	x0, x19
	blr	x8
	ldr	x8, [x19]
	ldr	x9, [x20]
	cmp	x8, x9
	b.ne	LBB0_1
; %bb.11:
	mov	x0, x19
	bl	_gfx_v10_0_wait_for_rlc_autoload_complete
	cbnz	w0, LBB0_2
	b	LBB0_1
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_GC,4,2                         ; @GC
	.comm	_mmRLC_CGCG_CGLS_CTRL,4,2       ; @mmRLC_CGCG_CGLS_CTRL
	.comm	_mmRLC_PG_CNTL,4,2              ; @mmRLC_PG_CNTL
	.comm	_AMDGPU_FW_LOAD_DIRECT,8,3      ; @AMDGPU_FW_LOAD_DIRECT
	.comm	_AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,8,3 ; @AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO
	.no_dead_strip	_gfx_v10_0_rlc_resume
.subsections_via_symbols
