	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_xgpu_vi_init_golden_registers  ## -- Begin function xgpu_vi_init_golden_registers
	.p2align	4, 0x90
_xgpu_vi_init_golden_registers:         ## @xgpu_vi_init_golden_registers
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	movl	(%rdi), %eax
	cmpl	$128, %eax
	je	LBB0_4
## %bb.1:
	cmpl	$129, %eax
	jne	LBB0_5
## %bb.2:
	movq	_xgpu_fiji_mgcg_cgcg_init@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%r14d, %edi
	callq	_ARRAY_SIZE
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_amdgpu_device_program_register_sequence
	movq	_xgpu_fiji_golden_settings_a10@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%r14d, %edi
	callq	_ARRAY_SIZE
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_amdgpu_device_program_register_sequence
	movq	_xgpu_fiji_golden_common_all@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_4:
	movq	_xgpu_tonga_mgcg_cgcg_init@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%r14d, %edi
	callq	_ARRAY_SIZE
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_amdgpu_device_program_register_sequence
	movq	_xgpu_tonga_golden_settings_a11@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%r14d, %edi
	callq	_ARRAY_SIZE
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_amdgpu_device_program_register_sequence
	movq	_xgpu_tonga_golden_common_all@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %r14d
	movl	%r14d, %edi
	callq	_ARRAY_SIZE
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_amdgpu_device_program_register_sequence ## TAILCALL
LBB0_5:
	leaq	L_.str(%rip), %rdi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_BUG_ON                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_xgpu_fiji_mgcg_cgcg_init,4,2   ## @xgpu_fiji_mgcg_cgcg_init
	.comm	_xgpu_fiji_golden_settings_a10,4,2 ## @xgpu_fiji_golden_settings_a10
	.comm	_xgpu_fiji_golden_common_all,4,2 ## @xgpu_fiji_golden_common_all
	.comm	_xgpu_tonga_mgcg_cgcg_init,4,2  ## @xgpu_tonga_mgcg_cgcg_init
	.comm	_xgpu_tonga_golden_settings_a11,4,2 ## @xgpu_tonga_golden_settings_a11
	.comm	_xgpu_tonga_golden_common_all,4,2 ## @xgpu_tonga_golden_common_all
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Doesn't support chip type.\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_xgpu_vi_init_golden_registers  ; -- Begin function xgpu_vi_init_golden_registers
	.p2align	2
_xgpu_vi_init_golden_registers:         ; @xgpu_vi_init_golden_registers
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	w8, [x0]
	cmp	w8, #128
	b.eq	LBB0_3
; %bb.1:
	cmp	w8, #129
	b.ne	LBB0_5
; %bb.2:
Lloh0:
	adrp	x8, _xgpu_fiji_mgcg_cgcg_init@GOTPAGE
Lloh1:
	ldr	x8, [x8, _xgpu_fiji_mgcg_cgcg_init@GOTPAGEOFF]
Lloh2:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_device_program_register_sequence
Lloh3:
	adrp	x8, _xgpu_fiji_golden_settings_a10@GOTPAGE
Lloh4:
	ldr	x8, [x8, _xgpu_fiji_golden_settings_a10@GOTPAGEOFF]
Lloh5:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_device_program_register_sequence
Lloh6:
	adrp	x8, _xgpu_fiji_golden_common_all@GOTPAGE
Lloh7:
	ldr	x8, [x8, _xgpu_fiji_golden_common_all@GOTPAGEOFF]
	b	LBB0_4
LBB0_3:
Lloh8:
	adrp	x8, _xgpu_tonga_mgcg_cgcg_init@GOTPAGE
Lloh9:
	ldr	x8, [x8, _xgpu_tonga_mgcg_cgcg_init@GOTPAGEOFF]
Lloh10:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_device_program_register_sequence
Lloh11:
	adrp	x8, _xgpu_tonga_golden_settings_a11@GOTPAGE
Lloh12:
	ldr	x8, [x8, _xgpu_tonga_golden_settings_a11@GOTPAGEOFF]
Lloh13:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_device_program_register_sequence
Lloh14:
	adrp	x8, _xgpu_tonga_golden_common_all@GOTPAGE
Lloh15:
	ldr	x8, [x8, _xgpu_tonga_golden_common_all@GOTPAGEOFF]
LBB0_4:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_amdgpu_device_program_register_sequence
LBB0_5:
Lloh16:
	adrp	x0, l_.str@PAGE
Lloh17:
	add	x0, x0, l_.str@PAGEOFF
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_BUG_ON
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpAdd	Lloh16, Lloh17
	.cfi_endproc
                                        ; -- End function
	.comm	_xgpu_fiji_mgcg_cgcg_init,4,2   ; @xgpu_fiji_mgcg_cgcg_init
	.comm	_xgpu_fiji_golden_settings_a10,4,2 ; @xgpu_fiji_golden_settings_a10
	.comm	_xgpu_fiji_golden_common_all,4,2 ; @xgpu_fiji_golden_common_all
	.comm	_xgpu_tonga_mgcg_cgcg_init,4,2  ; @xgpu_tonga_mgcg_cgcg_init
	.comm	_xgpu_tonga_golden_settings_a11,4,2 ; @xgpu_tonga_golden_settings_a11
	.comm	_xgpu_tonga_golden_common_all,4,2 ; @xgpu_tonga_golden_common_all
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Doesn't support chip type.\n"

.subsections_via_symbols
