	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function intel_vgpu_set_irqs
_intel_vgpu_set_irqs:                   ## @intel_vgpu_set_irqs
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movl	%esi, %eax
	cmpl	$128, %edx
	je	LBB0_4
## %bb.1:
	cmpl	$129, %edx
	jne	LBB0_3
## %bb.2:
	movq	_VFIO_IRQ_SET_ACTION_TYPE_MASK@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	andl	%eax, %esi
	addl	$-130, %esi
	cmpl	$3, %esi
	jae	LBB0_3
## %bb.6:
	movslq	%esi, %r10
	leaq	l_switch.table.intel_vgpu_set_irqs(%rip), %rsi
	movq	(%rsi,%r10,8), %r11
	jmp	LBB0_7
LBB0_4:
	movq	_VFIO_IRQ_SET_ACTION_TYPE_MASK@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	andl	%eax, %esi
	cmpl	$131, %esi
	jne	LBB0_3
## %bb.5:
	movq	_intel_vgpu_set_msi_trigger@GOTPCREL(%rip), %r11
LBB0_7:
	movl	%edx, %esi
	movl	%ecx, %edx
	movl	%r8d, %ecx
	movl	%eax, %r8d
	popq	%rbp
	jmpq	*%r11                           ## TAILCALL
LBB0_3:
	movq	_ENOTTY@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_VFIO_IRQ_SET_ACTION_TYPE_MASK,4,2 ## @VFIO_IRQ_SET_ACTION_TYPE_MASK
	.comm	_ENOTTY,4,2                     ## @ENOTTY
	.no_dead_strip	_intel_vgpu_set_irqs
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.intel_vgpu_set_irqs
l_switch.table.intel_vgpu_set_irqs:
	.quad	_intel_vgpu_set_intx_unmask
	.quad	_intel_vgpu_set_intx_trigger
	.quad	_intel_vgpu_set_intx_mask

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function intel_vgpu_set_irqs
_intel_vgpu_set_irqs:                   ; @intel_vgpu_set_irqs
	.cfi_startproc
; %bb.0:
	mov	x8, x1
	cmp	w2, #128
	b.eq	LBB0_4
; %bb.1:
	cmp	w2, #129
	b.ne	LBB0_7
; %bb.2:
Lloh0:
	adrp	x9, _VFIO_IRQ_SET_ACTION_TYPE_MASK@GOTPAGE
Lloh1:
	ldr	x9, [x9, _VFIO_IRQ_SET_ACTION_TYPE_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	and	w9, w9, w8
	sub	w9, w9, #130
	cmp	w9, #3
	b.hs	LBB0_7
; %bb.3:
Lloh3:
	adrp	x10, l_switch.table.intel_vgpu_set_irqs@PAGE
Lloh4:
	add	x10, x10, l_switch.table.intel_vgpu_set_irqs@PAGEOFF
	ldr	x6, [x10, w9, sxtw #3]
	b	LBB0_6
LBB0_4:
Lloh5:
	adrp	x9, _VFIO_IRQ_SET_ACTION_TYPE_MASK@GOTPAGE
Lloh6:
	ldr	x9, [x9, _VFIO_IRQ_SET_ACTION_TYPE_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	and	w9, w9, w8
	cmp	w9, #131
	b.ne	LBB0_7
; %bb.5:
Lloh8:
	adrp	x6, _intel_vgpu_set_msi_trigger@GOTPAGE
Lloh9:
	ldr	x6, [x6, _intel_vgpu_set_msi_trigger@GOTPAGEOFF]
LBB0_6:
	mov	x1, x2
	mov	x2, x3
	mov	x3, x4
	mov	x4, x8
	br	x6
LBB0_7:
Lloh10:
	adrp	x8, _ENOTTY@GOTPAGE
Lloh11:
	ldr	x8, [x8, _ENOTTY@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	neg	w0, w8
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.cfi_endproc
                                        ; -- End function
	.comm	_VFIO_IRQ_SET_ACTION_TYPE_MASK,4,2 ; @VFIO_IRQ_SET_ACTION_TYPE_MASK
	.comm	_ENOTTY,4,2                     ; @ENOTTY
	.no_dead_strip	_intel_vgpu_set_irqs
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.intel_vgpu_set_irqs
l_switch.table.intel_vgpu_set_irqs:
	.quad	_intel_vgpu_set_intx_unmask
	.quad	_intel_vgpu_set_intx_trigger
	.quad	_intel_vgpu_set_intx_mask

.subsections_via_symbols
