	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function si_is_special_1gb_platform
_si_is_special_1gb_platform:            ## @si_is_special_1gb_platform
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_MC_SEQ_MISC0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r12d
	movq	_MC_SEQ_MISC0_GDDR5_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	andl	%r12d, %r15d
	movq	_MC_SEQ_MISC0_GDDR5_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarl	%cl, %r15d
	movq	_MC_SEQ_MISC0_GDDR5_VALUE@GOTPCREL(%rip), %rax
	xorl	(%rax), %r15d
	movq	_MC_SEQ_MISC0_REV_ID_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r12d, %eax
	movq	_MC_SEQ_MISC0_REV_ID_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	movq	_MC_SEQ_MISC0_REV_ID_VALUE@GOTPCREL(%rip), %rcx
	xorl	(%rcx), %eax
	movq	_MC_SEQ_MISC0_VEN_ID_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %r12d
	movq	_MC_SEQ_MISC0_VEN_ID_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %r12d
	movq	_MC_SEQ_MISC0_VEN_ID_VALUE@GOTPCREL(%rip), %rcx
	xorl	(%rcx), %r12d
	orl	%eax, %r12d
	movq	_MC_SEQ_IO_DEBUG_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$11, %esi
	callq	_WREG32
	movq	_MC_SEQ_IO_DEBUG_DATA@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	xorl	%ebx, %ebx
	testb	$2, %al
	sete	%bl
	shll	$4, %ebx
	addl	$16, %ebx
	movq	_MC_ARB_RAMCFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_NOOFROWS_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	andl	%eax, %esi
	movq	_NOOFROWS_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %esi
	movq	_NOOFCOLS_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	andl	%eax, %edx
	movq	_NOOFCOLS_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %edx
	addl	%esi, %edx
	movq	_NOOFBANK_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_NOOFBANK_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	addl	%eax, %edx
	movl	%edx, %ecx
	shll	%cl, %ebx
	movq	(%r14), %rax
	movl	$26649, %ecx                    ## imm = 0x6819
	xorl	(%rax), %ecx
	orl	%r15d, %ecx
	orl	%r12d, %ecx
	xorl	$1024, %ebx                     ## imm = 0x400
	xorl	%eax, %eax
	orl	%ecx, %ebx
	sete	%al
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MC_SEQ_MISC0,4,2               ## @MC_SEQ_MISC0
	.comm	_MC_SEQ_MISC0_GDDR5_VALUE,4,2   ## @MC_SEQ_MISC0_GDDR5_VALUE
	.comm	_MC_SEQ_MISC0_GDDR5_MASK,4,2    ## @MC_SEQ_MISC0_GDDR5_MASK
	.comm	_MC_SEQ_MISC0_GDDR5_SHIFT,4,2   ## @MC_SEQ_MISC0_GDDR5_SHIFT
	.comm	_MC_SEQ_MISC0_REV_ID_VALUE,4,2  ## @MC_SEQ_MISC0_REV_ID_VALUE
	.comm	_MC_SEQ_MISC0_REV_ID_MASK,4,2   ## @MC_SEQ_MISC0_REV_ID_MASK
	.comm	_MC_SEQ_MISC0_REV_ID_SHIFT,4,2  ## @MC_SEQ_MISC0_REV_ID_SHIFT
	.comm	_MC_SEQ_MISC0_VEN_ID_VALUE,4,2  ## @MC_SEQ_MISC0_VEN_ID_VALUE
	.comm	_MC_SEQ_MISC0_VEN_ID_MASK,4,2   ## @MC_SEQ_MISC0_VEN_ID_MASK
	.comm	_MC_SEQ_MISC0_VEN_ID_SHIFT,4,2  ## @MC_SEQ_MISC0_VEN_ID_SHIFT
	.comm	_MC_SEQ_IO_DEBUG_INDEX,4,2      ## @MC_SEQ_IO_DEBUG_INDEX
	.comm	_MC_SEQ_IO_DEBUG_DATA,4,2       ## @MC_SEQ_IO_DEBUG_DATA
	.comm	_MC_ARB_RAMCFG,4,2              ## @MC_ARB_RAMCFG
	.comm	_NOOFROWS_MASK,4,2              ## @NOOFROWS_MASK
	.comm	_NOOFROWS_SHIFT,4,2             ## @NOOFROWS_SHIFT
	.comm	_NOOFCOLS_MASK,4,2              ## @NOOFCOLS_MASK
	.comm	_NOOFCOLS_SHIFT,4,2             ## @NOOFCOLS_SHIFT
	.comm	_NOOFBANK_MASK,4,2              ## @NOOFBANK_MASK
	.comm	_NOOFBANK_SHIFT,4,2             ## @NOOFBANK_SHIFT
	.no_dead_strip	_si_is_special_1gb_platform
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function si_is_special_1gb_platform
_si_is_special_1gb_platform:            ; @si_is_special_1gb_platform
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x8, _MC_SEQ_MISC0@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MC_SEQ_MISC0@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_RREG32
Lloh3:
	adrp	x8, _MC_SEQ_MISC0_GDDR5_VALUE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _MC_SEQ_MISC0_GDDR5_VALUE@GOTPAGEOFF]
Lloh5:
	ldr	w20, [x8]
Lloh6:
	adrp	x8, _MC_SEQ_MISC0_GDDR5_MASK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _MC_SEQ_MISC0_GDDR5_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh9:
	adrp	x9, _MC_SEQ_MISC0_GDDR5_SHIFT@GOTPAGE
Lloh10:
	ldr	x9, [x9, _MC_SEQ_MISC0_GDDR5_SHIFT@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	asr	w21, w8, w9
Lloh12:
	adrp	x8, _MC_SEQ_MISC0_REV_ID_VALUE@GOTPAGE
Lloh13:
	ldr	x8, [x8, _MC_SEQ_MISC0_REV_ID_VALUE@GOTPAGEOFF]
Lloh14:
	adrp	x9, _MC_SEQ_MISC0_REV_ID_MASK@GOTPAGE
Lloh15:
	ldr	x9, [x9, _MC_SEQ_MISC0_REV_ID_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
Lloh17:
	ldr	w9, [x9]
	and	w9, w9, w0
Lloh18:
	adrp	x10, _MC_SEQ_MISC0_REV_ID_SHIFT@GOTPAGE
Lloh19:
	ldr	x10, [x10, _MC_SEQ_MISC0_REV_ID_SHIFT@GOTPAGEOFF]
Lloh20:
	ldr	w10, [x10]
	asr	w9, w9, w10
	cmp	w8, w9
Lloh21:
	adrp	x8, _MC_SEQ_MISC0_VEN_ID_VALUE@GOTPAGE
Lloh22:
	ldr	x8, [x8, _MC_SEQ_MISC0_VEN_ID_VALUE@GOTPAGEOFF]
Lloh23:
	adrp	x9, _MC_SEQ_MISC0_VEN_ID_MASK@GOTPAGE
Lloh24:
	ldr	x9, [x9, _MC_SEQ_MISC0_VEN_ID_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
Lloh26:
	ldr	w9, [x9]
	and	w9, w9, w0
Lloh27:
	adrp	x10, _MC_SEQ_MISC0_VEN_ID_SHIFT@GOTPAGE
Lloh28:
	ldr	x10, [x10, _MC_SEQ_MISC0_VEN_ID_SHIFT@GOTPAGEOFF]
Lloh29:
	ldr	w10, [x10]
	asr	w9, w9, w10
	ccmp	w8, w9, #0, eq
	cset	w22, eq
Lloh30:
	adrp	x8, _MC_SEQ_IO_DEBUG_INDEX@GOTPAGE
Lloh31:
	ldr	x8, [x8, _MC_SEQ_IO_DEBUG_INDEX@GOTPAGEOFF]
Lloh32:
	ldr	w0, [x8]
	mov	w1, #11
	bl	_WREG32
Lloh33:
	adrp	x8, _MC_SEQ_IO_DEBUG_DATA@GOTPAGE
Lloh34:
	ldr	x8, [x8, _MC_SEQ_IO_DEBUG_DATA@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	bl	_RREG32
	tst	w0, #0x2
	mov	w8, #16
	mov	w9, #32
	csel	w23, w9, w8, eq
Lloh36:
	adrp	x8, _MC_ARB_RAMCFG@GOTPAGE
Lloh37:
	ldr	x8, [x8, _MC_ARB_RAMCFG@GOTPAGEOFF]
Lloh38:
	ldr	w0, [x8]
	bl	_RREG32
Lloh39:
	adrp	x8, _NOOFROWS_MASK@GOTPAGE
Lloh40:
	ldr	x8, [x8, _NOOFROWS_MASK@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh42:
	adrp	x9, _NOOFROWS_SHIFT@GOTPAGE
Lloh43:
	ldr	x9, [x9, _NOOFROWS_SHIFT@GOTPAGEOFF]
Lloh44:
	ldr	w9, [x9]
	asr	w8, w8, w9
Lloh45:
	adrp	x9, _NOOFCOLS_MASK@GOTPAGE
Lloh46:
	ldr	x9, [x9, _NOOFCOLS_MASK@GOTPAGEOFF]
Lloh47:
	ldr	w9, [x9]
	and	w9, w9, w0
Lloh48:
	adrp	x10, _NOOFCOLS_SHIFT@GOTPAGE
Lloh49:
	ldr	x10, [x10, _NOOFCOLS_SHIFT@GOTPAGEOFF]
Lloh50:
	ldr	w10, [x10]
	asr	w9, w9, w10
Lloh51:
	adrp	x10, _NOOFBANK_MASK@GOTPAGE
Lloh52:
	ldr	x10, [x10, _NOOFBANK_MASK@GOTPAGEOFF]
Lloh53:
	ldr	w10, [x10]
	and	w10, w10, w0
Lloh54:
	adrp	x11, _NOOFBANK_SHIFT@GOTPAGE
Lloh55:
	ldr	x11, [x11, _NOOFBANK_SHIFT@GOTPAGEOFF]
Lloh56:
	ldr	w11, [x11]
	asr	w10, w10, w11
	add	w8, w9, w8
	add	w8, w8, w10
	lsl	w8, w23, w8
	ldr	x9, [x19]
	ldr	w9, [x9]
	mov	w10, #26649
	cmp	w9, w10
	ccmp	w20, w21, #0, eq
	cset	w9, eq
	and	w9, w9, w22
	cmp	w8, #1024
	cset	w8, eq
	and	w0, w9, w8
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh25
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh16
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_MC_SEQ_MISC0,4,2               ; @MC_SEQ_MISC0
	.comm	_MC_SEQ_MISC0_GDDR5_VALUE,4,2   ; @MC_SEQ_MISC0_GDDR5_VALUE
	.comm	_MC_SEQ_MISC0_GDDR5_MASK,4,2    ; @MC_SEQ_MISC0_GDDR5_MASK
	.comm	_MC_SEQ_MISC0_GDDR5_SHIFT,4,2   ; @MC_SEQ_MISC0_GDDR5_SHIFT
	.comm	_MC_SEQ_MISC0_REV_ID_VALUE,4,2  ; @MC_SEQ_MISC0_REV_ID_VALUE
	.comm	_MC_SEQ_MISC0_REV_ID_MASK,4,2   ; @MC_SEQ_MISC0_REV_ID_MASK
	.comm	_MC_SEQ_MISC0_REV_ID_SHIFT,4,2  ; @MC_SEQ_MISC0_REV_ID_SHIFT
	.comm	_MC_SEQ_MISC0_VEN_ID_VALUE,4,2  ; @MC_SEQ_MISC0_VEN_ID_VALUE
	.comm	_MC_SEQ_MISC0_VEN_ID_MASK,4,2   ; @MC_SEQ_MISC0_VEN_ID_MASK
	.comm	_MC_SEQ_MISC0_VEN_ID_SHIFT,4,2  ; @MC_SEQ_MISC0_VEN_ID_SHIFT
	.comm	_MC_SEQ_IO_DEBUG_INDEX,4,2      ; @MC_SEQ_IO_DEBUG_INDEX
	.comm	_MC_SEQ_IO_DEBUG_DATA,4,2       ; @MC_SEQ_IO_DEBUG_DATA
	.comm	_MC_ARB_RAMCFG,4,2              ; @MC_ARB_RAMCFG
	.comm	_NOOFROWS_MASK,4,2              ; @NOOFROWS_MASK
	.comm	_NOOFROWS_SHIFT,4,2             ; @NOOFROWS_SHIFT
	.comm	_NOOFCOLS_MASK,4,2              ; @NOOFCOLS_MASK
	.comm	_NOOFCOLS_SHIFT,4,2             ; @NOOFCOLS_SHIFT
	.comm	_NOOFBANK_MASK,4,2              ; @NOOFBANK_MASK
	.comm	_NOOFBANK_SHIFT,4,2             ; @NOOFBANK_SHIFT
	.no_dead_strip	_si_is_special_1gb_platform
.subsections_via_symbols
