	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function fiji_update_mc_medium_grain_clock_gating
_fiji_update_mc_medium_grain_clock_gating: ## @fiji_update_mc_medium_grain_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	testl	%esi, %esi
	je	LBB0_3
## %bb.1:
	movq	_AMD_CG_SUPPORT_MC_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rdi)
	je	LBB0_3
## %bb.2:
	movq	_mmMC_HUB_MISC_HUB_CG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_MC_HUB_MISC_HUB_CG__ENABLE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmMC_HUB_MISC_SIP_CG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_MC_HUB_MISC_SIP_CG__ENABLE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmMC_HUB_MISC_VM_CG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_MC_HUB_MISC_VM_CG__ENABLE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmMC_XPB_CLK_GAT@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_MC_XPB_CLK_GAT__ENABLE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmATC_MISC_CG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_ATC_MISC_CG__ENABLE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmMC_CITF_MISC_WR_CG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_MC_CITF_MISC_WR_CG__ENABLE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmMC_CITF_MISC_RD_CG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_MC_CITF_MISC_RD_CG__ENABLE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmMC_CITF_MISC_VM_CG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_MC_CITF_MISC_VM_CG__ENABLE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmVM_L2_CG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %esi
	movq	_VM_L2_CG__ENABLE_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	jmp	LBB0_4
LBB0_3:
	movq	_mmMC_HUB_MISC_HUB_CG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_MC_HUB_MISC_HUB_CG__ENABLE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32
	movq	_mmMC_HUB_MISC_SIP_CG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_MC_HUB_MISC_SIP_CG__ENABLE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32
	movq	_mmMC_HUB_MISC_VM_CG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_MC_HUB_MISC_VM_CG__ENABLE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32
	movq	_mmMC_XPB_CLK_GAT@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_MC_XPB_CLK_GAT__ENABLE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32
	movq	_mmATC_MISC_CG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_ATC_MISC_CG__ENABLE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32
	movq	_mmMC_CITF_MISC_WR_CG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_MC_CITF_MISC_WR_CG__ENABLE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32
	movq	_mmMC_CITF_MISC_RD_CG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_MC_CITF_MISC_RD_CG__ENABLE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32
	movq	_mmMC_CITF_MISC_VM_CG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_MC_CITF_MISC_VM_CG__ENABLE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32
	movq	_mmVM_L2_CG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_VM_L2_CG__ENABLE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
LBB0_4:
	movq	_mmVM_L2_CG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_CG_SUPPORT_MC_MGCG,4,2     ## @AMD_CG_SUPPORT_MC_MGCG
	.comm	_mmMC_HUB_MISC_HUB_CG,4,2       ## @mmMC_HUB_MISC_HUB_CG
	.comm	_MC_HUB_MISC_HUB_CG__ENABLE_MASK,4,2 ## @MC_HUB_MISC_HUB_CG__ENABLE_MASK
	.comm	_mmMC_HUB_MISC_SIP_CG,4,2       ## @mmMC_HUB_MISC_SIP_CG
	.comm	_MC_HUB_MISC_SIP_CG__ENABLE_MASK,4,2 ## @MC_HUB_MISC_SIP_CG__ENABLE_MASK
	.comm	_mmMC_HUB_MISC_VM_CG,4,2        ## @mmMC_HUB_MISC_VM_CG
	.comm	_MC_HUB_MISC_VM_CG__ENABLE_MASK,4,2 ## @MC_HUB_MISC_VM_CG__ENABLE_MASK
	.comm	_mmMC_XPB_CLK_GAT,4,2           ## @mmMC_XPB_CLK_GAT
	.comm	_MC_XPB_CLK_GAT__ENABLE_MASK,4,2 ## @MC_XPB_CLK_GAT__ENABLE_MASK
	.comm	_mmATC_MISC_CG,4,2              ## @mmATC_MISC_CG
	.comm	_ATC_MISC_CG__ENABLE_MASK,4,2   ## @ATC_MISC_CG__ENABLE_MASK
	.comm	_mmMC_CITF_MISC_WR_CG,4,2       ## @mmMC_CITF_MISC_WR_CG
	.comm	_MC_CITF_MISC_WR_CG__ENABLE_MASK,4,2 ## @MC_CITF_MISC_WR_CG__ENABLE_MASK
	.comm	_mmMC_CITF_MISC_RD_CG,4,2       ## @mmMC_CITF_MISC_RD_CG
	.comm	_MC_CITF_MISC_RD_CG__ENABLE_MASK,4,2 ## @MC_CITF_MISC_RD_CG__ENABLE_MASK
	.comm	_mmMC_CITF_MISC_VM_CG,4,2       ## @mmMC_CITF_MISC_VM_CG
	.comm	_MC_CITF_MISC_VM_CG__ENABLE_MASK,4,2 ## @MC_CITF_MISC_VM_CG__ENABLE_MASK
	.comm	_mmVM_L2_CG,4,2                 ## @mmVM_L2_CG
	.comm	_VM_L2_CG__ENABLE_MASK,4,2      ## @VM_L2_CG__ENABLE_MASK
	.no_dead_strip	_fiji_update_mc_medium_grain_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function fiji_update_mc_medium_grain_clock_gating
_fiji_update_mc_medium_grain_clock_gating: ; @fiji_update_mc_medium_grain_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
Lloh0:
	adrp	x19, _mmVM_L2_CG@GOTPAGE
Lloh1:
	ldr	x19, [x19, _mmVM_L2_CG@GOTPAGEOFF]
	cbz	w1, LBB0_3
; %bb.1:
	ldr	w8, [x0]
Lloh2:
	adrp	x9, _AMD_CG_SUPPORT_MC_MGCG@GOTPAGE
Lloh3:
	ldr	x9, [x9, _AMD_CG_SUPPORT_MC_MGCG@GOTPAGEOFF]
Lloh4:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_3
; %bb.2:
Lloh5:
	adrp	x20, _mmMC_HUB_MISC_HUB_CG@GOTPAGE
Lloh6:
	ldr	x20, [x20, _mmMC_HUB_MISC_HUB_CG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh7:
	adrp	x8, _MC_HUB_MISC_HUB_CG__ENABLE_MASK@GOTPAGE
Lloh8:
	ldr	x8, [x8, _MC_HUB_MISC_HUB_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x20]
	bl	_WREG32
Lloh10:
	adrp	x20, _mmMC_HUB_MISC_SIP_CG@GOTPAGE
Lloh11:
	ldr	x20, [x20, _mmMC_HUB_MISC_SIP_CG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh12:
	adrp	x8, _MC_HUB_MISC_SIP_CG__ENABLE_MASK@GOTPAGE
Lloh13:
	ldr	x8, [x8, _MC_HUB_MISC_SIP_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x20]
	bl	_WREG32
Lloh15:
	adrp	x20, _mmMC_HUB_MISC_VM_CG@GOTPAGE
Lloh16:
	ldr	x20, [x20, _mmMC_HUB_MISC_VM_CG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh17:
	adrp	x8, _MC_HUB_MISC_VM_CG__ENABLE_MASK@GOTPAGE
Lloh18:
	ldr	x8, [x8, _MC_HUB_MISC_VM_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x20]
	bl	_WREG32
Lloh20:
	adrp	x20, _mmMC_XPB_CLK_GAT@GOTPAGE
Lloh21:
	ldr	x20, [x20, _mmMC_XPB_CLK_GAT@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh22:
	adrp	x8, _MC_XPB_CLK_GAT__ENABLE_MASK@GOTPAGE
Lloh23:
	ldr	x8, [x8, _MC_XPB_CLK_GAT__ENABLE_MASK@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x20]
	bl	_WREG32
Lloh25:
	adrp	x20, _mmATC_MISC_CG@GOTPAGE
Lloh26:
	ldr	x20, [x20, _mmATC_MISC_CG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh27:
	adrp	x8, _ATC_MISC_CG__ENABLE_MASK@GOTPAGE
Lloh28:
	ldr	x8, [x8, _ATC_MISC_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x20]
	bl	_WREG32
Lloh30:
	adrp	x20, _mmMC_CITF_MISC_WR_CG@GOTPAGE
Lloh31:
	ldr	x20, [x20, _mmMC_CITF_MISC_WR_CG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh32:
	adrp	x8, _MC_CITF_MISC_WR_CG__ENABLE_MASK@GOTPAGE
Lloh33:
	ldr	x8, [x8, _MC_CITF_MISC_WR_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh34:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x20]
	bl	_WREG32
Lloh35:
	adrp	x20, _mmMC_CITF_MISC_RD_CG@GOTPAGE
Lloh36:
	ldr	x20, [x20, _mmMC_CITF_MISC_RD_CG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh37:
	adrp	x8, _MC_CITF_MISC_RD_CG__ENABLE_MASK@GOTPAGE
Lloh38:
	ldr	x8, [x8, _MC_CITF_MISC_RD_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x20]
	bl	_WREG32
Lloh40:
	adrp	x20, _mmMC_CITF_MISC_VM_CG@GOTPAGE
Lloh41:
	ldr	x20, [x20, _mmMC_CITF_MISC_VM_CG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh42:
	adrp	x8, _MC_CITF_MISC_VM_CG__ENABLE_MASK@GOTPAGE
Lloh43:
	ldr	x8, [x8, _MC_CITF_MISC_VM_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh44:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w0, [x20]
	bl	_WREG32
	ldr	w0, [x19]
	bl	_RREG32
Lloh45:
	adrp	x8, _VM_L2_CG__ENABLE_MASK@GOTPAGE
Lloh46:
	ldr	x8, [x8, _VM_L2_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh47:
	ldr	w8, [x8]
	orr	w1, w8, w0
	b	LBB0_4
LBB0_3:
Lloh48:
	adrp	x20, _mmMC_HUB_MISC_HUB_CG@GOTPAGE
Lloh49:
	ldr	x20, [x20, _mmMC_HUB_MISC_HUB_CG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh50:
	adrp	x8, _MC_HUB_MISC_HUB_CG__ENABLE_MASK@GOTPAGE
Lloh51:
	ldr	x8, [x8, _MC_HUB_MISC_HUB_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh52:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32
Lloh53:
	adrp	x20, _mmMC_HUB_MISC_SIP_CG@GOTPAGE
Lloh54:
	ldr	x20, [x20, _mmMC_HUB_MISC_SIP_CG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh55:
	adrp	x8, _MC_HUB_MISC_SIP_CG__ENABLE_MASK@GOTPAGE
Lloh56:
	ldr	x8, [x8, _MC_HUB_MISC_SIP_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh57:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32
Lloh58:
	adrp	x20, _mmMC_HUB_MISC_VM_CG@GOTPAGE
Lloh59:
	ldr	x20, [x20, _mmMC_HUB_MISC_VM_CG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh60:
	adrp	x8, _MC_HUB_MISC_VM_CG__ENABLE_MASK@GOTPAGE
Lloh61:
	ldr	x8, [x8, _MC_HUB_MISC_VM_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh62:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32
Lloh63:
	adrp	x20, _mmMC_XPB_CLK_GAT@GOTPAGE
Lloh64:
	ldr	x20, [x20, _mmMC_XPB_CLK_GAT@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh65:
	adrp	x8, _MC_XPB_CLK_GAT__ENABLE_MASK@GOTPAGE
Lloh66:
	ldr	x8, [x8, _MC_XPB_CLK_GAT__ENABLE_MASK@GOTPAGEOFF]
Lloh67:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32
Lloh68:
	adrp	x20, _mmATC_MISC_CG@GOTPAGE
Lloh69:
	ldr	x20, [x20, _mmATC_MISC_CG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh70:
	adrp	x8, _ATC_MISC_CG__ENABLE_MASK@GOTPAGE
Lloh71:
	ldr	x8, [x8, _ATC_MISC_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh72:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32
Lloh73:
	adrp	x20, _mmMC_CITF_MISC_WR_CG@GOTPAGE
Lloh74:
	ldr	x20, [x20, _mmMC_CITF_MISC_WR_CG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh75:
	adrp	x8, _MC_CITF_MISC_WR_CG__ENABLE_MASK@GOTPAGE
Lloh76:
	ldr	x8, [x8, _MC_CITF_MISC_WR_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh77:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32
Lloh78:
	adrp	x20, _mmMC_CITF_MISC_RD_CG@GOTPAGE
Lloh79:
	ldr	x20, [x20, _mmMC_CITF_MISC_RD_CG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh80:
	adrp	x8, _MC_CITF_MISC_RD_CG__ENABLE_MASK@GOTPAGE
Lloh81:
	ldr	x8, [x8, _MC_CITF_MISC_RD_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh82:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32
Lloh83:
	adrp	x20, _mmMC_CITF_MISC_VM_CG@GOTPAGE
Lloh84:
	ldr	x20, [x20, _mmMC_CITF_MISC_VM_CG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh85:
	adrp	x8, _MC_CITF_MISC_VM_CG__ENABLE_MASK@GOTPAGE
Lloh86:
	ldr	x8, [x8, _MC_CITF_MISC_VM_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh87:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32
	ldr	w0, [x19]
	bl	_RREG32
Lloh88:
	adrp	x8, _VM_L2_CG__ENABLE_MASK@GOTPAGE
Lloh89:
	ldr	x8, [x8, _VM_L2_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh90:
	ldr	w8, [x8]
	bic	w1, w0, w8
LBB0_4:
	ldr	w0, [x19]
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_WREG32
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGot	Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGot	Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGot	Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGot	Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGot	Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh48, Lloh49
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_CG_SUPPORT_MC_MGCG,4,2     ; @AMD_CG_SUPPORT_MC_MGCG
	.comm	_mmMC_HUB_MISC_HUB_CG,4,2       ; @mmMC_HUB_MISC_HUB_CG
	.comm	_MC_HUB_MISC_HUB_CG__ENABLE_MASK,4,2 ; @MC_HUB_MISC_HUB_CG__ENABLE_MASK
	.comm	_mmMC_HUB_MISC_SIP_CG,4,2       ; @mmMC_HUB_MISC_SIP_CG
	.comm	_MC_HUB_MISC_SIP_CG__ENABLE_MASK,4,2 ; @MC_HUB_MISC_SIP_CG__ENABLE_MASK
	.comm	_mmMC_HUB_MISC_VM_CG,4,2        ; @mmMC_HUB_MISC_VM_CG
	.comm	_MC_HUB_MISC_VM_CG__ENABLE_MASK,4,2 ; @MC_HUB_MISC_VM_CG__ENABLE_MASK
	.comm	_mmMC_XPB_CLK_GAT,4,2           ; @mmMC_XPB_CLK_GAT
	.comm	_MC_XPB_CLK_GAT__ENABLE_MASK,4,2 ; @MC_XPB_CLK_GAT__ENABLE_MASK
	.comm	_mmATC_MISC_CG,4,2              ; @mmATC_MISC_CG
	.comm	_ATC_MISC_CG__ENABLE_MASK,4,2   ; @ATC_MISC_CG__ENABLE_MASK
	.comm	_mmMC_CITF_MISC_WR_CG,4,2       ; @mmMC_CITF_MISC_WR_CG
	.comm	_MC_CITF_MISC_WR_CG__ENABLE_MASK,4,2 ; @MC_CITF_MISC_WR_CG__ENABLE_MASK
	.comm	_mmMC_CITF_MISC_RD_CG,4,2       ; @mmMC_CITF_MISC_RD_CG
	.comm	_MC_CITF_MISC_RD_CG__ENABLE_MASK,4,2 ; @MC_CITF_MISC_RD_CG__ENABLE_MASK
	.comm	_mmMC_CITF_MISC_VM_CG,4,2       ; @mmMC_CITF_MISC_VM_CG
	.comm	_MC_CITF_MISC_VM_CG__ENABLE_MASK,4,2 ; @MC_CITF_MISC_VM_CG__ENABLE_MASK
	.comm	_mmVM_L2_CG,4,2                 ; @mmVM_L2_CG
	.comm	_VM_L2_CG__ENABLE_MASK,4,2      ; @VM_L2_CG__ENABLE_MASK
	.no_dead_strip	_fiji_update_mc_medium_grain_clock_gating
.subsections_via_symbols
