	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function uvd_v5_0_hw_init
_uvd_v5_0_hw_init:                      ## @uvd_v5_0_hw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	movq	(%rdi), %r14
	movl	$10000, %esi                    ## imm = 0x2710
	movl	$10000, %edx                    ## imm = 0x2710
	callq	_amdgpu_asic_set_uvd_clocks
	movq	_AMD_CG_STATE_UNGATE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_uvd_v5_0_set_clockgating_state
	movq	%rbx, %rdi
	movl	$1, %esi
	callq	_uvd_v5_0_enable_mgcg
	movq	%r14, %rdi
	callq	_amdgpu_ring_test_helper
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_4
## %bb.1:
	movq	%r14, %rdi
	movl	$10, %esi
	callq	_amdgpu_ring_alloc
	testl	%eax, %eax
	je	LBB0_3
## %bb.2:
	movl	%eax, %ebx
	leaq	L_.str(%rip), %rdi
	movl	%eax, %esi
	callq	_DRM_ERROR
	jmp	LBB0_4
LBB0_3:
	movq	_mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%ebx, %ebx
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r14, %rdi
	movl	$1048575, %esi                  ## imm = 0xFFFFF
	callq	_amdgpu_ring_write
	movq	_mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r14, %rdi
	movl	$1048575, %esi                  ## imm = 0xFFFFF
	callq	_amdgpu_ring_write
	movq	_mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r14, %rdi
	movl	$1048575, %esi                  ## imm = 0xFFFFF
	callq	_amdgpu_ring_write
	movq	_mmUVD_SEMA_TIMEOUT_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r14, %rdi
	movl	$8, %esi
	callq	_amdgpu_ring_write
	movq	_mmUVD_SEMA_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r14, %rdi
	movl	$3, %esi
	callq	_amdgpu_ring_write
	movq	%r14, %rdi
	callq	_amdgpu_ring_commit
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_INFO
LBB0_4:
	movl	%ebx, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_CG_STATE_UNGATE,4,2        ## @AMD_CG_STATE_UNGATE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"amdgpu: ring failed to lock UVD ring (%d).\n"

	.comm	_mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL,4,2 ## @mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
	.comm	_mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL,4,2 ## @mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
	.comm	_mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL,4,2 ## @mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
	.comm	_mmUVD_SEMA_TIMEOUT_STATUS,4,2  ## @mmUVD_SEMA_TIMEOUT_STATUS
	.comm	_mmUVD_SEMA_CNTL,4,2            ## @mmUVD_SEMA_CNTL
L_.str.1:                               ## @.str.1
	.asciz	"UVD initialized successfully.\n"

	.no_dead_strip	_uvd_v5_0_hw_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function uvd_v5_0_hw_init
_uvd_v5_0_hw_init:                      ; @uvd_v5_0_hw_init
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x20, x0
	ldr	x19, [x0]
	mov	w1, #10000
	mov	w2, #10000
	bl	_amdgpu_asic_set_uvd_clocks
Lloh0:
	adrp	x8, _AMD_CG_STATE_UNGATE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMD_CG_STATE_UNGATE@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_uvd_v5_0_set_clockgating_state
	mov	x0, x20
	mov	w1, #1
	bl	_uvd_v5_0_enable_mgcg
	mov	x0, x19
	bl	_amdgpu_ring_test_helper
	mov	x20, x0
	cbnz	w0, LBB0_4
; %bb.1:
	mov	x0, x19
	mov	w1, #10
	bl	_amdgpu_ring_alloc
	mov	x20, x0
	cbz	w0, LBB0_3
; %bb.2:
Lloh3:
	adrp	x0, l_.str@PAGE
Lloh4:
	add	x0, x0, l_.str@PAGEOFF
	mov	x1, x20
	bl	_DRM_ERROR
	b	LBB0_4
LBB0_3:
Lloh5:
	adrp	x8, _mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL@GOTPAGE
Lloh6:
	ldr	x8, [x8, _mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #1048575
	bl	_amdgpu_ring_write
Lloh8:
	adrp	x8, _mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL@GOTPAGE
Lloh9:
	ldr	x8, [x8, _mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL@GOTPAGEOFF]
Lloh10:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #1048575
	bl	_amdgpu_ring_write
Lloh11:
	adrp	x8, _mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL@GOTPAGE
Lloh12:
	ldr	x8, [x8, _mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #1048575
	bl	_amdgpu_ring_write
Lloh14:
	adrp	x8, _mmUVD_SEMA_TIMEOUT_STATUS@GOTPAGE
Lloh15:
	ldr	x8, [x8, _mmUVD_SEMA_TIMEOUT_STATUS@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #8
	bl	_amdgpu_ring_write
Lloh17:
	adrp	x8, _mmUVD_SEMA_CNTL@GOTPAGE
Lloh18:
	ldr	x8, [x8, _mmUVD_SEMA_CNTL@GOTPAGEOFF]
Lloh19:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #3
	bl	_amdgpu_ring_write
	mov	x0, x19
	bl	_amdgpu_ring_commit
Lloh20:
	adrp	x0, l_.str.1@PAGE
Lloh21:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_INFO
LBB0_4:
	mov	x0, x20
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_CG_STATE_UNGATE,4,2        ; @AMD_CG_STATE_UNGATE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"amdgpu: ring failed to lock UVD ring (%d).\n"

	.comm	_mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL,4,2 ; @mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
	.comm	_mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL,4,2 ; @mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
	.comm	_mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL,4,2 ; @mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
	.comm	_mmUVD_SEMA_TIMEOUT_STATUS,4,2  ; @mmUVD_SEMA_TIMEOUT_STATUS
	.comm	_mmUVD_SEMA_CNTL,4,2            ; @mmUVD_SEMA_CNTL
l_.str.1:                               ; @.str.1
	.asciz	"UVD initialized successfully.\n"

	.no_dead_strip	_uvd_v5_0_hw_init
.subsections_via_symbols
