	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vce_v3_0_is_idle
_vce_v3_0_is_idle:                      ## @vce_v3_0_is_idle
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movl	(%rdi), %ecx
	movq	_AMDGPU_VCE_HARVEST_VCE0@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	movl	(%rax), %edx
	movl	$0, %eax
	andl	%ecx, %edx
	jne	LBB0_2
## %bb.1:
	movq	_SRBM_STATUS2__VCE0_BUSY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_2:
	movq	_AMDGPU_VCE_HARVEST_VCE1@GOTPCREL(%rip), %rdx
	andl	(%rdx), %ecx
	jne	LBB0_4
## %bb.3:
	movq	_SRBM_STATUS2__VCE1_BUSY_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
LBB0_4:
	orl	%eax, %ebx
	movq	_mmSRBM_STATUS2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	xorl	%ecx, %ecx
	testl	%eax, %ebx
	sete	%cl
	movl	%ecx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_VCE_HARVEST_VCE0,4,2    ## @AMDGPU_VCE_HARVEST_VCE0
	.comm	_SRBM_STATUS2__VCE0_BUSY_MASK,4,2 ## @SRBM_STATUS2__VCE0_BUSY_MASK
	.comm	_AMDGPU_VCE_HARVEST_VCE1,4,2    ## @AMDGPU_VCE_HARVEST_VCE1
	.comm	_SRBM_STATUS2__VCE1_BUSY_MASK,4,2 ## @SRBM_STATUS2__VCE1_BUSY_MASK
	.comm	_mmSRBM_STATUS2,4,2             ## @mmSRBM_STATUS2
	.no_dead_strip	_vce_v3_0_is_idle
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vce_v3_0_is_idle
_vce_v3_0_is_idle:                      ; @vce_v3_0_is_idle
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _AMDGPU_VCE_HARVEST_VCE0@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMDGPU_VCE_HARVEST_VCE0@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
Lloh3:
	adrp	x10, _SRBM_STATUS2__VCE0_BUSY_MASK@GOTPAGE
Lloh4:
	ldr	x10, [x10, _SRBM_STATUS2__VCE0_BUSY_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w10, [x10]
	tst	w9, w8
	csel	w9, w10, wzr, eq
Lloh6:
	adrp	x10, _AMDGPU_VCE_HARVEST_VCE1@GOTPAGE
Lloh7:
	ldr	x10, [x10, _AMDGPU_VCE_HARVEST_VCE1@GOTPAGEOFF]
Lloh8:
	ldr	w10, [x10]
Lloh9:
	adrp	x11, _SRBM_STATUS2__VCE1_BUSY_MASK@GOTPAGE
Lloh10:
	ldr	x11, [x11, _SRBM_STATUS2__VCE1_BUSY_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w11, [x11]
	tst	w10, w8
	csel	w8, w11, wzr, eq
	orr	w19, w8, w9
Lloh12:
	adrp	x8, _mmSRBM_STATUS2@GOTPAGE
Lloh13:
	ldr	x8, [x8, _mmSRBM_STATUS2@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	bl	_RREG32
	tst	w19, w0
	cset	w0, eq
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_VCE_HARVEST_VCE0,4,2    ; @AMDGPU_VCE_HARVEST_VCE0
	.comm	_SRBM_STATUS2__VCE0_BUSY_MASK,4,2 ; @SRBM_STATUS2__VCE0_BUSY_MASK
	.comm	_AMDGPU_VCE_HARVEST_VCE1,4,2    ; @AMDGPU_VCE_HARVEST_VCE1
	.comm	_SRBM_STATUS2__VCE1_BUSY_MASK,4,2 ; @SRBM_STATUS2__VCE1_BUSY_MASK
	.comm	_mmSRBM_STATUS2,4,2             ; @mmSRBM_STATUS2
	.no_dead_strip	_vce_v3_0_is_idle
.subsections_via_symbols
