	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function nbio_v6_1_hdp_flush
_nbio_v6_1_hdp_flush:                   ## @nbio_v6_1_hdp_flush
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	testq	%rsi, %rsi
	je	LBB0_2
## %bb.1:
	movq	%rsi, %rbx
	movq	(%rsi), %rax
	cmpl	$0, (%rax)
	je	LBB0_2
## %bb.3:
	movq	_NBIO@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	%rbx, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_amdgpu_ring_emit_wreg          ## TAILCALL
LBB0_2:
	movq	_NBIO@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_WREG32_SOC15_NO_KIQ            ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_NBIO,4,2                       ## @NBIO
	.comm	_mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL,4,2 ## @mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL
	.no_dead_strip	_nbio_v6_1_hdp_flush
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function nbio_v6_1_hdp_flush
_nbio_v6_1_hdp_flush:                   ; @nbio_v6_1_hdp_flush
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	cbz	x1, LBB0_3
; %bb.1:
	mov	x19, x1
	ldr	x8, [x1]
	ldr	w8, [x8]
	cbz	w8, LBB0_3
; %bb.2:
Lloh0:
	adrp	x8, _NBIO@GOTPAGE
Lloh1:
	ldr	x8, [x8, _NBIO@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
Lloh3:
	adrp	x8, _mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x1, x0
	mov	x0, x19
	mov	w2, #0
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_amdgpu_ring_emit_wreg
LBB0_3:
Lloh6:
	adrp	x8, _NBIO@GOTPAGE
Lloh7:
	ldr	x8, [x8, _NBIO@GOTPAGEOFF]
Lloh8:
	adrp	x9, _mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL@GOTPAGE
Lloh9:
	ldr	x9, [x9, _mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL@GOTPAGEOFF]
Lloh10:
	ldr	w0, [x8]
Lloh11:
	ldr	w2, [x9]
	mov	w1, #0
	mov	w3, #0
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_WREG32_SOC15_NO_KIQ
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh10
	.cfi_endproc
                                        ; -- End function
	.comm	_NBIO,4,2                       ; @NBIO
	.comm	_mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL,4,2 ; @mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL
	.no_dead_strip	_nbio_v6_1_hdp_flush
.subsections_via_symbols
