	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_1_0_disable_static_power_gating
_vcn_1_0_disable_static_power_gating:   ## @vcn_1_0_disable_static_power_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	_AMD_PG_SUPPORT_VCN@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	movq	_UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %sil
	movq	_UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$1, %eax
	shll	%cl, %eax
	btsl	%esi, %eax
	movq	_UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%edx, (%rdi)
	je	LBB0_2
## %bb.1:
	movl	$2, %esi
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %esi
	movq	_UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %edi
	shll	%cl, %edi
	movq	_UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %ebx
	shll	%cl, %ebx
	movq	_UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %edx
	shll	%cl, %edx
	orl	%esi, %eax
	movq	_UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %esi
	shll	%cl, %esi
	orl	%edi, %ebx
	orl	%ebx, %edx
	movq	_UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %edi
	shll	%cl, %edi
	orl	%eax, %edx
	orl	%esi, %edi
	movq	_UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %esi
	shll	%cl, %esi
	movl	$2, %eax
	orl	%edi, %esi
	movq	_UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %edi
	shll	%cl, %edi
	orl	%esi, %edi
	orl	%edx, %edi
	movq	_UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	orl	%edi, %eax
	movq	_VCN@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_mmUVD_PGFSM_CONFIG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%rbx), %edi
	movq	_mmUVD_PGFSM_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%esi, %esi
	movl	$16777215, %r8d                 ## imm = 0xFFFFFF
	jmp	LBB0_3
LBB0_2:
	btsl	%ecx, %eax
	movq	_UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	btsl	%ecx, %eax
	movq	_UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	btsl	%ecx, %eax
	movq	_UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	btsl	%ecx, %eax
	movq	_UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	btsl	%ecx, %eax
	movq	_UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	btsl	%ecx, %eax
	movq	_UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	btsl	%ecx, %eax
	movq	_UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	btsl	%ecx, %eax
	movq	_UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	btsl	%ecx, %eax
	movq	_VCN@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_mmUVD_PGFSM_CONFIG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%rbx), %edi
	movq	_mmUVD_PGFSM_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	movl	$-1, %r8d
LBB0_3:
	callq	_SOC15_WAIT_ON_RREG
	movq	_VCN@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	movq	_mmUVD_POWER_STATUS@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	(%r14), %edx
	andl	(%r15), %edx
	movq	_UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON@GOTPCREL(%rip), %rsi
	movq	_UVD_POWER_STATUS__UVD_PG_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rsi), %ecx
	andl	$-260, %eax                     ## imm = 0xFEFC
	testl	%edx, %edx
	cmovel	%edx, %ecx
	orl	%eax, %ecx
	movl	(%r12), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_SOC15                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_PG_SUPPORT_VCN,4,2         ## @AMD_PG_SUPPORT_VCN
	.comm	_UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT,4,2 ## @UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT
	.comm	_VCN,4,2                        ## @VCN
	.comm	_mmUVD_PGFSM_CONFIG,4,2         ## @mmUVD_PGFSM_CONFIG
	.comm	_mmUVD_PGFSM_STATUS,4,2         ## @mmUVD_PGFSM_STATUS
	.comm	_UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON,4,2 ## @UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON
	.comm	_mmUVD_POWER_STATUS,4,2         ## @mmUVD_POWER_STATUS
	.comm	_UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,4,2 ## @UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON
	.comm	_UVD_POWER_STATUS__UVD_PG_EN_MASK,4,2 ## @UVD_POWER_STATUS__UVD_PG_EN_MASK
	.no_dead_strip	_vcn_1_0_disable_static_power_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_1_0_disable_static_power_gating
_vcn_1_0_disable_static_power_gating:   ; @vcn_1_0_disable_static_power_gating
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x20, _AMD_PG_SUPPORT_VCN@GOTPAGE
Lloh1:
	ldr	x20, [x20, _AMD_PG_SUPPORT_VCN@GOTPAGEOFF]
	ldr	w11, [x0]
	ldr	w12, [x20]
Lloh2:
	adrp	x8, _UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT@GOTPAGE
Lloh3:
	ldr	x8, [x8, _UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh4:
	ldr	w9, [x8]
	mov	w8, #1
	lsl	w9, w8, w9
Lloh5:
	adrp	x10, _UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT@GOTPAGE
Lloh6:
	ldr	x10, [x10, _UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh7:
	ldr	w10, [x10]
	lsl	w10, w8, w10
	orr	w9, w10, w9
Lloh8:
	adrp	x10, _UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT@GOTPAGE
Lloh9:
	ldr	x10, [x10, _UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh10:
	ldr	w10, [x10]
Lloh11:
	adrp	x21, _VCN@GOTPAGE
Lloh12:
	ldr	x21, [x21, _VCN@GOTPAGEOFF]
	tst	w12, w11
	b.eq	LBB0_2
; %bb.1:
	mov	w8, #2
	lsl	w10, w8, w10
	orr	w9, w9, w10
Lloh13:
	adrp	x10, _UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT@GOTPAGE
Lloh14:
	ldr	x10, [x10, _UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh15:
	ldr	w10, [x10]
	lsl	w10, w8, w10
	orr	w9, w9, w10
Lloh16:
	adrp	x10, _UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT@GOTPAGE
Lloh17:
	ldr	x10, [x10, _UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh18:
	ldr	w10, [x10]
	lsl	w10, w8, w10
	orr	w9, w9, w10
Lloh19:
	adrp	x10, _UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT@GOTPAGE
Lloh20:
	ldr	x10, [x10, _UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh21:
	ldr	w10, [x10]
	lsl	w10, w8, w10
	orr	w9, w9, w10
Lloh22:
	adrp	x10, _UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT@GOTPAGE
Lloh23:
	ldr	x10, [x10, _UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh24:
	ldr	w10, [x10]
	lsl	w10, w8, w10
	orr	w9, w9, w10
Lloh25:
	adrp	x10, _UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT@GOTPAGE
Lloh26:
	ldr	x10, [x10, _UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh27:
	ldr	w10, [x10]
	lsl	w10, w8, w10
Lloh28:
	adrp	x11, _UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT@GOTPAGE
Lloh29:
	ldr	x11, [x11, _UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT@GOTPAGEOFF]
	orr	w9, w9, w10
Lloh30:
	ldr	w10, [x11]
	lsl	w10, w8, w10
	orr	w9, w9, w10
Lloh31:
	adrp	x10, _UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT@GOTPAGE
Lloh32:
	ldr	x10, [x10, _UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh33:
	ldr	w10, [x10]
	lsl	w10, w8, w10
	orr	w9, w9, w10
Lloh34:
	adrp	x10, _UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT@GOTPAGE
Lloh35:
	ldr	x10, [x10, _UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh36:
	ldr	w10, [x10]
	lsl	w8, w8, w10
	orr	w3, w9, w8
	ldr	w0, [x21]
Lloh37:
	adrp	x8, _mmUVD_PGFSM_CONFIG@GOTPAGE
Lloh38:
	ldr	x8, [x8, _mmUVD_PGFSM_CONFIG@GOTPAGEOFF]
Lloh39:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x21]
Lloh40:
	adrp	x8, _mmUVD_PGFSM_STATUS@GOTPAGE
Lloh41:
	ldr	x8, [x8, _mmUVD_PGFSM_STATUS@GOTPAGEOFF]
Lloh42:
	ldr	w2, [x8]
Lloh43:
	adrp	x8, _UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON@GOTPAGE
Lloh44:
	ldr	x8, [x8, _UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON@GOTPAGEOFF]
Lloh45:
	ldr	w3, [x8]
	mov	w1, #0
	mov	w4, #16777215
	b	LBB0_3
LBB0_2:
	lsl	w10, w8, w10
	orr	w9, w9, w10
Lloh46:
	adrp	x10, _UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT@GOTPAGE
Lloh47:
	ldr	x10, [x10, _UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh48:
	ldr	w10, [x10]
	lsl	w10, w8, w10
	orr	w9, w9, w10
Lloh49:
	adrp	x10, _UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT@GOTPAGE
Lloh50:
	ldr	x10, [x10, _UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh51:
	ldr	w10, [x10]
	lsl	w10, w8, w10
	orr	w9, w9, w10
Lloh52:
	adrp	x10, _UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT@GOTPAGE
Lloh53:
	ldr	x10, [x10, _UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh54:
	ldr	w10, [x10]
	lsl	w10, w8, w10
	orr	w9, w9, w10
Lloh55:
	adrp	x10, _UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT@GOTPAGE
Lloh56:
	ldr	x10, [x10, _UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh57:
	ldr	w10, [x10]
	lsl	w10, w8, w10
	orr	w9, w9, w10
Lloh58:
	adrp	x10, _UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT@GOTPAGE
Lloh59:
	ldr	x10, [x10, _UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh60:
	ldr	w10, [x10]
	lsl	w10, w8, w10
Lloh61:
	adrp	x11, _UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT@GOTPAGE
Lloh62:
	ldr	x11, [x11, _UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT@GOTPAGEOFF]
	orr	w9, w9, w10
Lloh63:
	ldr	w10, [x11]
	lsl	w10, w8, w10
	orr	w9, w9, w10
Lloh64:
	adrp	x10, _UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT@GOTPAGE
Lloh65:
	ldr	x10, [x10, _UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh66:
	ldr	w10, [x10]
	lsl	w10, w8, w10
	orr	w9, w9, w10
Lloh67:
	adrp	x10, _UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT@GOTPAGE
Lloh68:
	ldr	x10, [x10, _UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT@GOTPAGEOFF]
Lloh69:
	ldr	w10, [x10]
	lsl	w8, w8, w10
	orr	w3, w9, w8
	ldr	w0, [x21]
Lloh70:
	adrp	x8, _mmUVD_PGFSM_CONFIG@GOTPAGE
Lloh71:
	ldr	x8, [x8, _mmUVD_PGFSM_CONFIG@GOTPAGEOFF]
Lloh72:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x21]
Lloh73:
	adrp	x8, _mmUVD_PGFSM_STATUS@GOTPAGE
Lloh74:
	ldr	x8, [x8, _mmUVD_PGFSM_STATUS@GOTPAGEOFF]
Lloh75:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	mov	w4, #-1
LBB0_3:
	bl	_SOC15_WAIT_ON_RREG
	ldr	w0, [x21]
Lloh76:
	adrp	x22, _mmUVD_POWER_STATUS@GOTPAGE
Lloh77:
	ldr	x22, [x22, _mmUVD_POWER_STATUS@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	w1, #0
	bl	_RREG32_SOC15
	mov	w8, #-260
	and	w8, w0, w8
	ldr	w9, [x19]
	ldr	w10, [x20]
Lloh78:
	adrp	x11, _UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON@GOTPAGE
Lloh79:
	ldr	x11, [x11, _UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON@GOTPAGEOFF]
Lloh80:
	adrp	x12, _UVD_POWER_STATUS__UVD_PG_EN_MASK@GOTPAGE
Lloh81:
	ldr	x12, [x12, _UVD_POWER_STATUS__UVD_PG_EN_MASK@GOTPAGEOFF]
Lloh82:
	ldr	w11, [x11]
Lloh83:
	ldr	w12, [x12]
	orr	w11, w12, w11
	tst	w10, w9
	csel	w9, wzr, w11, eq
	orr	w3, w9, w8
	ldr	w0, [x21]
	ldr	w2, [x22]
	mov	w1, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32_SOC15
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh82
	.loh AdrpLdrGot	Lloh76, Lloh77
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_PG_SUPPORT_VCN,4,2         ; @AMD_PG_SUPPORT_VCN
	.comm	_UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
	.comm	_UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT,4,2 ; @UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT
	.comm	_VCN,4,2                        ; @VCN
	.comm	_mmUVD_PGFSM_CONFIG,4,2         ; @mmUVD_PGFSM_CONFIG
	.comm	_mmUVD_PGFSM_STATUS,4,2         ; @mmUVD_PGFSM_STATUS
	.comm	_UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON,4,2 ; @UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON
	.comm	_mmUVD_POWER_STATUS,4,2         ; @mmUVD_POWER_STATUS
	.comm	_UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,4,2 ; @UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON
	.comm	_UVD_POWER_STATUS__UVD_PG_EN_MASK,4,2 ; @UVD_POWER_STATUS__UVD_PG_EN_MASK
	.no_dead_strip	_vcn_1_0_disable_static_power_gating
.subsections_via_symbols
