	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_intel_init_pm                  ## -- Begin function intel_init_pm
	.p2align	4, 0x90
_intel_init_pm:                         ## @intel_init_pm
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	callq	_IS_PINEVIEW
	movq	%rbx, %rdi
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	callq	_i915_pineview_get_mem_freq
	jmp	LBB0_4
LBB0_2:
	movl	$5, %esi
	callq	_IS_GEN
	testq	%rax, %rax
	je	LBB0_4
## %bb.3:
	movq	%rbx, %rdi
	callq	_i915_ironlake_get_mem_freq
LBB0_4:
	movq	%rbx, %rdi
	callq	_INTEL_GEN
	movq	%rbx, %rdi
	cmpl	$9, %eax
	jl	LBB0_6
## %bb.5:
	callq	_skl_setup_wm_latency
	movq	_skl_initial_wm@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 28(%rbx)
	movq	_skl_atomic_update_crtc_wm@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 40(%rbx)
	movq	_skl_compute_wm@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 44(%rbx)
	jmp	LBB0_21
LBB0_6:
	callq	_HAS_PCH_SPLIT
	movq	%rbx, %rdi
	testq	%rax, %rax
	je	LBB0_18
## %bb.7:
	callq	_ilk_setup_wm_latency
	movq	%rbx, %rdi
	movl	$5, %esi
	callq	_IS_GEN
	testq	%rax, %rax
	je	LBB0_11
## %bb.8:
	movq	72(%rbx), %rax
	cmpq	$0, 8(%rax)
	je	LBB0_11
## %bb.9:
	movq	64(%rbx), %rax
	cmpq	$0, 8(%rax)
	je	LBB0_11
## %bb.10:
	movq	56(%rbx), %rax
	cmpq	$0, 8(%rax)
	jne	LBB0_15
LBB0_11:
	movq	%rbx, %rdi
	movl	$5, %esi
	callq	_IS_GEN
	testq	%rax, %rax
	je	LBB0_12
LBB0_17:
	leaq	L_.str(%rip), %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_DRM_DEBUG_KMS                  ## TAILCALL
LBB0_18:
	callq	_IS_VALLEYVIEW
	testq	%rax, %rax
	jne	LBB0_20
## %bb.19:
	movq	%rbx, %rdi
	callq	_IS_CHERRYVIEW
	testq	%rax, %rax
	je	LBB0_22
LBB0_20:
	movq	%rbx, %rdi
	callq	_vlv_setup_wm_latency
	movq	_vlv_compute_pipe_wm@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 36(%rbx)
	movq	_vlv_compute_intermediate_wm@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 32(%rbx)
	movq	_vlv_initial_watermarks@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 28(%rbx)
	movq	_vlv_optimize_watermarks@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 24(%rbx)
	movq	_vlv_atomic_update_fifo@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 40(%rbx)
	jmp	LBB0_21
LBB0_12:
	movq	72(%rbx), %rax
	cmpq	$0, (%rax)
	je	LBB0_17
## %bb.13:
	movq	64(%rbx), %rax
	cmpq	$0, (%rax)
	je	LBB0_17
## %bb.14:
	movq	56(%rbx), %rax
	cmpq	$0, (%rax)
	je	LBB0_17
LBB0_15:
	movq	_ilk_compute_pipe_wm@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 36(%rbx)
	movq	_ilk_compute_intermediate_wm@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 32(%rbx)
	movq	_ilk_initial_watermarks@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 28(%rbx)
	movq	_ilk_optimize_watermarks@GOTPCREL(%rip), %rax
LBB0_16:
	movl	(%rax), %eax
	movl	%eax, 24(%rbx)
LBB0_21:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
LBB0_22:
	movq	%rbx, %rdi
	callq	_IS_G4X
	movq	%rbx, %rdi
	testq	%rax, %rax
	je	LBB0_24
## %bb.23:
	callq	_g4x_setup_wm_latency
	movq	_g4x_compute_pipe_wm@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 36(%rbx)
	movq	_g4x_compute_intermediate_wm@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 32(%rbx)
	movq	_g4x_initial_watermarks@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 28(%rbx)
	movq	_g4x_optimize_watermarks@GOTPCREL(%rip), %rax
	jmp	LBB0_16
LBB0_24:
	callq	_IS_PINEVIEW
	movq	%rbx, %rdi
	testq	%rax, %rax
	je	LBB0_29
## %bb.25:
	callq	_IS_MOBILE
	xorl	%edi, %edi
	testl	%eax, %eax
	sete	%dil
	movl	52(%rbx), %edx
	movl	(%rbx), %esi
	movl	48(%rbx), %ecx
	callq	_intel_get_cxsr_latency
	testl	%eax, %eax
	je	LBB0_26
## %bb.27:
	movq	_pineview_update_wm@GOTPCREL(%rip), %rax
	jmp	LBB0_28
LBB0_29:
	movl	$4, %esi
	callq	_IS_GEN
	testq	%rax, %rax
	je	LBB0_31
## %bb.30:
	movq	_i965_update_wm@GOTPCREL(%rip), %rax
LBB0_28:
	movq	(%rax), %rax
	movq	%rax, 16(%rbx)
	jmp	LBB0_21
LBB0_26:
	movl	48(%rbx), %ecx
	cmpl	$1, (%rbx)
	leaq	L_.str.2(%rip), %rax
	leaq	L_.str.3(%rip), %rsi
	cmoveq	%rax, %rsi
	movl	52(%rbx), %edx
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_INFO
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_intel_set_memory_cxsr
	movq	$0, 16(%rbx)
	jmp	LBB0_21
LBB0_31:
	movq	%rbx, %rdi
	movl	$3, %esi
	callq	_IS_GEN
	testq	%rax, %rax
	je	LBB0_34
## %bb.32:
	movq	_i9xx_update_wm@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 16(%rbx)
	movq	_i9xx_get_fifo_size@GOTPCREL(%rip), %rax
LBB0_33:
	movl	(%rax), %eax
	movl	%eax, 8(%rbx)
	jmp	LBB0_21
LBB0_34:
	movq	%rbx, %rdi
	movl	$2, %esi
	callq	_IS_GEN
	testq	%rax, %rax
	je	LBB0_38
## %bb.35:
	movq	%rbx, %rdi
	callq	_INTEL_INFO
	cmpl	$1, (%rax)
	jne	LBB0_37
## %bb.36:
	movq	_i845_update_wm@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 16(%rbx)
	movq	_i845_get_fifo_size@GOTPCREL(%rip), %rax
	jmp	LBB0_33
LBB0_38:
	leaq	L_.str.4(%rip), %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_DRM_ERROR                      ## TAILCALL
LBB0_37:
	movq	_i9xx_update_wm@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 16(%rbx)
	movq	_i830_get_fifo_size@GOTPCREL(%rip), %rax
	jmp	LBB0_33
	.cfi_endproc
                                        ## -- End function
	.comm	_skl_initial_wm,4,2             ## @skl_initial_wm
	.comm	_skl_atomic_update_crtc_wm,4,2  ## @skl_atomic_update_crtc_wm
	.comm	_skl_compute_wm,4,2             ## @skl_compute_wm
	.comm	_ilk_compute_pipe_wm,4,2        ## @ilk_compute_pipe_wm
	.comm	_ilk_compute_intermediate_wm,4,2 ## @ilk_compute_intermediate_wm
	.comm	_ilk_initial_watermarks,4,2     ## @ilk_initial_watermarks
	.comm	_ilk_optimize_watermarks,4,2    ## @ilk_optimize_watermarks
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Failed to read display plane latency. Disable CxSR\n"

	.comm	_vlv_compute_pipe_wm,4,2        ## @vlv_compute_pipe_wm
	.comm	_vlv_compute_intermediate_wm,4,2 ## @vlv_compute_intermediate_wm
	.comm	_vlv_initial_watermarks,4,2     ## @vlv_initial_watermarks
	.comm	_vlv_optimize_watermarks,4,2    ## @vlv_optimize_watermarks
	.comm	_vlv_atomic_update_fifo,4,2     ## @vlv_atomic_update_fifo
	.comm	_g4x_compute_pipe_wm,4,2        ## @g4x_compute_pipe_wm
	.comm	_g4x_compute_intermediate_wm,4,2 ## @g4x_compute_intermediate_wm
	.comm	_g4x_initial_watermarks,4,2     ## @g4x_initial_watermarks
	.comm	_g4x_optimize_watermarks,4,2    ## @g4x_optimize_watermarks
L_.str.1:                               ## @.str.1
	.asciz	"failed to find known CxSR latency (found ddr%s fsb freq %d, mem freq %d), disabling CxSR\n"

L_.str.2:                               ## @.str.2
	.asciz	"3"

L_.str.3:                               ## @.str.3
	.asciz	"2"

	.comm	_pineview_update_wm,8,3         ## @pineview_update_wm
	.comm	_i965_update_wm,8,3             ## @i965_update_wm
	.comm	_i9xx_update_wm,8,3             ## @i9xx_update_wm
	.comm	_i9xx_get_fifo_size,4,2         ## @i9xx_get_fifo_size
	.comm	_i845_update_wm,8,3             ## @i845_update_wm
	.comm	_i845_get_fifo_size,4,2         ## @i845_get_fifo_size
	.comm	_i830_get_fifo_size,4,2         ## @i830_get_fifo_size
L_.str.4:                               ## @.str.4
	.asciz	"unexpected fall-through in intel_init_pm\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_intel_init_pm                  ; -- Begin function intel_init_pm
	.p2align	2
_intel_init_pm:                         ; @intel_init_pm
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_IS_PINEVIEW
	cbz	x0, LBB0_2
; %bb.1:
	mov	x0, x19
	bl	_i915_pineview_get_mem_freq
	b	LBB0_4
LBB0_2:
	mov	x0, x19
	mov	w1, #5
	bl	_IS_GEN
	cbz	x0, LBB0_4
; %bb.3:
	mov	x0, x19
	bl	_i915_ironlake_get_mem_freq
LBB0_4:
	mov	x0, x19
	bl	_INTEL_GEN
	cmp	w0, #9
	b.lt	LBB0_6
; %bb.5:
	mov	x0, x19
	bl	_skl_setup_wm_latency
Lloh0:
	adrp	x8, _skl_initial_wm@GOTPAGE
Lloh1:
	ldr	x8, [x8, _skl_initial_wm@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	str	w8, [x19, #28]
Lloh3:
	adrp	x8, _skl_atomic_update_crtc_wm@GOTPAGE
Lloh4:
	ldr	x8, [x8, _skl_atomic_update_crtc_wm@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
Lloh6:
	adrp	x9, _skl_compute_wm@GOTPAGE
Lloh7:
	ldr	x9, [x9, _skl_compute_wm@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	stp	w8, w9, [x19, #40]
	b	LBB0_21
LBB0_6:
	mov	x0, x19
	bl	_HAS_PCH_SPLIT
	cbz	x0, LBB0_13
; %bb.7:
	mov	x0, x19
	bl	_ilk_setup_wm_latency
	mov	x0, x19
	mov	w1, #5
	bl	_IS_GEN
	cbz	x0, LBB0_11
; %bb.8:
	ldr	x8, [x19, #72]
	ldr	x8, [x8, #8]
	cbz	x8, LBB0_11
; %bb.9:
	ldr	x8, [x19, #64]
	ldr	x8, [x8, #8]
	cbz	x8, LBB0_11
; %bb.10:
	ldr	x8, [x19, #56]
	ldr	x8, [x8, #8]
	cbnz	x8, LBB0_19
LBB0_11:
	mov	x0, x19
	mov	w1, #5
	bl	_IS_GEN
	cbz	x0, LBB0_16
LBB0_12:
Lloh9:
	adrp	x0, l_.str@PAGE
Lloh10:
	add	x0, x0, l_.str@PAGEOFF
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_DRM_DEBUG_KMS
LBB0_13:
	mov	x0, x19
	bl	_IS_VALLEYVIEW
	cbnz	x0, LBB0_15
; %bb.14:
	mov	x0, x19
	bl	_IS_CHERRYVIEW
	cbz	x0, LBB0_22
LBB0_15:
	mov	x0, x19
	bl	_vlv_setup_wm_latency
Lloh11:
	adrp	x8, _vlv_compute_pipe_wm@GOTPAGE
Lloh12:
	ldr	x8, [x8, _vlv_compute_pipe_wm@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
Lloh14:
	adrp	x9, _vlv_compute_intermediate_wm@GOTPAGE
Lloh15:
	ldr	x9, [x9, _vlv_compute_intermediate_wm@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #32]
Lloh17:
	adrp	x8, _vlv_initial_watermarks@GOTPAGE
Lloh18:
	ldr	x8, [x8, _vlv_initial_watermarks@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
Lloh20:
	adrp	x9, _vlv_optimize_watermarks@GOTPAGE
Lloh21:
	ldr	x9, [x9, _vlv_optimize_watermarks@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #24]
Lloh23:
	adrp	x8, _vlv_atomic_update_fifo@GOTPAGE
Lloh24:
	ldr	x8, [x8, _vlv_atomic_update_fifo@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
	str	w8, [x19, #40]
	b	LBB0_21
LBB0_16:
	ldr	x8, [x19, #72]
	ldr	x8, [x8]
	cbz	x8, LBB0_12
; %bb.17:
	ldr	x8, [x19, #64]
	ldr	x8, [x8]
	cbz	x8, LBB0_12
; %bb.18:
	ldr	x8, [x19, #56]
	ldr	x8, [x8]
	cbz	x8, LBB0_12
LBB0_19:
Lloh26:
	adrp	x8, _ilk_compute_pipe_wm@GOTPAGE
Lloh27:
	ldr	x8, [x8, _ilk_compute_pipe_wm@GOTPAGEOFF]
Lloh28:
	adrp	x9, _ilk_compute_intermediate_wm@GOTPAGE
Lloh29:
	ldr	x9, [x9, _ilk_compute_intermediate_wm@GOTPAGEOFF]
Lloh30:
	ldr	w8, [x8]
Lloh31:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #32]
Lloh32:
	adrp	x8, _ilk_initial_watermarks@GOTPAGE
Lloh33:
	ldr	x8, [x8, _ilk_initial_watermarks@GOTPAGEOFF]
Lloh34:
	ldr	w8, [x8]
Lloh35:
	adrp	x9, _ilk_optimize_watermarks@GOTPAGE
Lloh36:
	ldr	x9, [x9, _ilk_optimize_watermarks@GOTPAGEOFF]
LBB0_20:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #24]
LBB0_21:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_22:
	mov	x0, x19
	bl	_IS_G4X
	cbz	x0, LBB0_24
; %bb.23:
	mov	x0, x19
	bl	_g4x_setup_wm_latency
Lloh37:
	adrp	x8, _g4x_compute_pipe_wm@GOTPAGE
Lloh38:
	ldr	x8, [x8, _g4x_compute_pipe_wm@GOTPAGEOFF]
Lloh39:
	adrp	x9, _g4x_compute_intermediate_wm@GOTPAGE
Lloh40:
	ldr	x9, [x9, _g4x_compute_intermediate_wm@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
Lloh42:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #32]
Lloh43:
	adrp	x8, _g4x_initial_watermarks@GOTPAGE
Lloh44:
	ldr	x8, [x8, _g4x_initial_watermarks@GOTPAGEOFF]
Lloh45:
	ldr	w8, [x8]
Lloh46:
	adrp	x9, _g4x_optimize_watermarks@GOTPAGE
Lloh47:
	ldr	x9, [x9, _g4x_optimize_watermarks@GOTPAGEOFF]
	b	LBB0_20
LBB0_24:
	mov	x0, x19
	bl	_IS_PINEVIEW
	cbz	x0, LBB0_27
; %bb.25:
	mov	x0, x19
	bl	_IS_MOBILE
	cmp	w0, #0
	cset	w0, eq
	ldr	w1, [x19]
	ldp	w3, w2, [x19, #48]
	bl	_intel_get_cxsr_latency
	cbz	w0, LBB0_30
; %bb.26:
Lloh48:
	adrp	x8, _pineview_update_wm@GOTPAGE
Lloh49:
	ldr	x8, [x8, _pineview_update_wm@GOTPAGEOFF]
	b	LBB0_29
LBB0_27:
	mov	x0, x19
	mov	w1, #4
	bl	_IS_GEN
	cbz	x0, LBB0_31
; %bb.28:
Lloh50:
	adrp	x8, _i965_update_wm@GOTPAGE
Lloh51:
	ldr	x8, [x8, _i965_update_wm@GOTPAGEOFF]
LBB0_29:
	ldr	x8, [x8]
	str	x8, [x19, #16]
	b	LBB0_21
LBB0_30:
	ldr	w8, [x19]
Lloh52:
	adrp	x9, l_.str.3@PAGE
Lloh53:
	add	x9, x9, l_.str.3@PAGEOFF
Lloh54:
	adrp	x10, l_.str.2@PAGE
Lloh55:
	add	x10, x10, l_.str.2@PAGEOFF
	cmp	w8, #1
	csel	x1, x10, x9, eq
	ldp	w3, w2, [x19, #48]
Lloh56:
	adrp	x0, l_.str.1@PAGE
Lloh57:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_INFO
	mov	x0, x19
	mov	w1, #0
	bl	_intel_set_memory_cxsr
	str	xzr, [x19, #16]
	b	LBB0_21
LBB0_31:
	mov	x0, x19
	mov	w1, #3
	bl	_IS_GEN
	cbz	x0, LBB0_34
; %bb.32:
Lloh58:
	adrp	x8, _i9xx_update_wm@GOTPAGE
Lloh59:
	ldr	x8, [x8, _i9xx_update_wm@GOTPAGEOFF]
Lloh60:
	ldr	x8, [x8]
	str	x8, [x19, #16]
Lloh61:
	adrp	x8, _i9xx_get_fifo_size@GOTPAGE
Lloh62:
	ldr	x8, [x8, _i9xx_get_fifo_size@GOTPAGEOFF]
LBB0_33:
	ldr	w8, [x8]
	str	w8, [x19, #8]
	b	LBB0_21
LBB0_34:
	mov	x0, x19
	mov	w1, #2
	bl	_IS_GEN
	cbz	x0, LBB0_37
; %bb.35:
	mov	x0, x19
	bl	_INTEL_INFO
	ldr	w8, [x0]
	cmp	w8, #1
	b.ne	LBB0_38
; %bb.36:
Lloh63:
	adrp	x8, _i845_update_wm@GOTPAGE
Lloh64:
	ldr	x8, [x8, _i845_update_wm@GOTPAGEOFF]
Lloh65:
	ldr	x8, [x8]
	str	x8, [x19, #16]
Lloh66:
	adrp	x8, _i845_get_fifo_size@GOTPAGE
Lloh67:
	ldr	x8, [x8, _i845_get_fifo_size@GOTPAGEOFF]
	b	LBB0_33
LBB0_37:
Lloh68:
	adrp	x0, l_.str.4@PAGE
Lloh69:
	add	x0, x0, l_.str.4@PAGEOFF
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_DRM_ERROR
LBB0_38:
Lloh70:
	adrp	x8, _i9xx_update_wm@GOTPAGE
Lloh71:
	ldr	x8, [x8, _i9xx_update_wm@GOTPAGEOFF]
Lloh72:
	ldr	x8, [x8]
	str	x8, [x19, #16]
Lloh73:
	adrp	x8, _i830_get_fifo_size@GOTPAGE
Lloh74:
	ldr	x8, [x8, _i830_get_fifo_size@GOTPAGEOFF]
	b	LBB0_33
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh30
	.loh AdrpLdrGot	Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh41
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpAdd	Lloh56, Lloh57
	.loh AdrpAdd	Lloh54, Lloh55
	.loh AdrpAdd	Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGot	Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpAdd	Lloh68, Lloh69
	.loh AdrpLdrGot	Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.cfi_endproc
                                        ; -- End function
	.comm	_skl_initial_wm,4,2             ; @skl_initial_wm
	.comm	_skl_atomic_update_crtc_wm,4,2  ; @skl_atomic_update_crtc_wm
	.comm	_skl_compute_wm,4,2             ; @skl_compute_wm
	.comm	_ilk_compute_pipe_wm,4,2        ; @ilk_compute_pipe_wm
	.comm	_ilk_compute_intermediate_wm,4,2 ; @ilk_compute_intermediate_wm
	.comm	_ilk_initial_watermarks,4,2     ; @ilk_initial_watermarks
	.comm	_ilk_optimize_watermarks,4,2    ; @ilk_optimize_watermarks
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Failed to read display plane latency. Disable CxSR\n"

	.comm	_vlv_compute_pipe_wm,4,2        ; @vlv_compute_pipe_wm
	.comm	_vlv_compute_intermediate_wm,4,2 ; @vlv_compute_intermediate_wm
	.comm	_vlv_initial_watermarks,4,2     ; @vlv_initial_watermarks
	.comm	_vlv_optimize_watermarks,4,2    ; @vlv_optimize_watermarks
	.comm	_vlv_atomic_update_fifo,4,2     ; @vlv_atomic_update_fifo
	.comm	_g4x_compute_pipe_wm,4,2        ; @g4x_compute_pipe_wm
	.comm	_g4x_compute_intermediate_wm,4,2 ; @g4x_compute_intermediate_wm
	.comm	_g4x_initial_watermarks,4,2     ; @g4x_initial_watermarks
	.comm	_g4x_optimize_watermarks,4,2    ; @g4x_optimize_watermarks
l_.str.1:                               ; @.str.1
	.asciz	"failed to find known CxSR latency (found ddr%s fsb freq %d, mem freq %d), disabling CxSR\n"

l_.str.2:                               ; @.str.2
	.asciz	"3"

l_.str.3:                               ; @.str.3
	.asciz	"2"

	.comm	_pineview_update_wm,8,3         ; @pineview_update_wm
	.comm	_i965_update_wm,8,3             ; @i965_update_wm
	.comm	_i9xx_update_wm,8,3             ; @i9xx_update_wm
	.comm	_i9xx_get_fifo_size,4,2         ; @i9xx_get_fifo_size
	.comm	_i845_update_wm,8,3             ; @i845_update_wm
	.comm	_i845_get_fifo_size,4,2         ; @i845_get_fifo_size
	.comm	_i830_get_fifo_size,4,2         ; @i830_get_fifo_size
l_.str.4:                               ; @.str.4
	.asciz	"unexpected fall-through in intel_init_pm\n"

.subsections_via_symbols
