	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vi_common_get_clockgating_state
_vi_common_get_clockgating_state:       ## @vi_common_get_clockgating_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rsi, %rbx
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movl	$0, (%rbx)
LBB0_2:
	movq	_ixPCIE_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_PCIE
	movq	_PCIE_CNTL2__SLV_MEM_LS_EN_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_4
## %bb.3:
	movq	_AMD_CG_SUPPORT_BIF_LS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%rbx)
LBB0_4:
	movq	_mmHDP_MEM_POWER_LS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_HDP_MEM_POWER_LS__LS_ENABLE_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_6
## %bb.5:
	movq	_AMD_CG_SUPPORT_HDP_LS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%rbx)
LBB0_6:
	movq	_mmHDP_HOST_PATH_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	jne	LBB0_8
## %bb.7:
	movq	_AMD_CG_SUPPORT_HDP_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%rbx)
LBB0_8:
	movq	_ixCGTT_ROM_CLK_CTRL0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_SMC
	movq	_CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	jne	LBB0_10
## %bb.9:
	movq	_AMD_CG_SUPPORT_ROM_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%rbx)
LBB0_10:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_ixPCIE_CNTL2,4,2               ## @ixPCIE_CNTL2
	.comm	_PCIE_CNTL2__SLV_MEM_LS_EN_MASK,4,2 ## @PCIE_CNTL2__SLV_MEM_LS_EN_MASK
	.comm	_AMD_CG_SUPPORT_BIF_LS,4,2      ## @AMD_CG_SUPPORT_BIF_LS
	.comm	_mmHDP_MEM_POWER_LS,4,2         ## @mmHDP_MEM_POWER_LS
	.comm	_HDP_MEM_POWER_LS__LS_ENABLE_MASK,4,2 ## @HDP_MEM_POWER_LS__LS_ENABLE_MASK
	.comm	_AMD_CG_SUPPORT_HDP_LS,4,2      ## @AMD_CG_SUPPORT_HDP_LS
	.comm	_mmHDP_HOST_PATH_CNTL,4,2       ## @mmHDP_HOST_PATH_CNTL
	.comm	_HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK,4,2 ## @HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK
	.comm	_AMD_CG_SUPPORT_HDP_MGCG,4,2    ## @AMD_CG_SUPPORT_HDP_MGCG
	.comm	_ixCGTT_ROM_CLK_CTRL0,4,2       ## @ixCGTT_ROM_CLK_CTRL0
	.comm	_CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK,4,2 ## @CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK
	.comm	_AMD_CG_SUPPORT_ROM_MGCG,4,2    ## @AMD_CG_SUPPORT_ROM_MGCG
	.no_dead_strip	_vi_common_get_clockgating_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vi_common_get_clockgating_state
_vi_common_get_clockgating_state:       ; @vi_common_get_clockgating_state
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x1
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_2
; %bb.1:
	str	wzr, [x19]
LBB0_2:
Lloh0:
	adrp	x8, _ixPCIE_CNTL2@GOTPAGE
Lloh1:
	ldr	x8, [x8, _ixPCIE_CNTL2@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_RREG32_PCIE
Lloh3:
	adrp	x8, _PCIE_CNTL2__SLV_MEM_LS_EN_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCIE_CNTL2__SLV_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_4
; %bb.3:
Lloh6:
	adrp	x8, _AMD_CG_SUPPORT_BIF_LS@GOTPAGE
Lloh7:
	ldr	x8, [x8, _AMD_CG_SUPPORT_BIF_LS@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_4:
Lloh9:
	adrp	x8, _mmHDP_MEM_POWER_LS@GOTPAGE
Lloh10:
	ldr	x8, [x8, _mmHDP_MEM_POWER_LS@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	bl	_RREG32
Lloh12:
	adrp	x8, _HDP_MEM_POWER_LS__LS_ENABLE_MASK@GOTPAGE
Lloh13:
	ldr	x8, [x8, _HDP_MEM_POWER_LS__LS_ENABLE_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_6
; %bb.5:
Lloh15:
	adrp	x8, _AMD_CG_SUPPORT_HDP_LS@GOTPAGE
Lloh16:
	ldr	x8, [x8, _AMD_CG_SUPPORT_HDP_LS@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_6:
Lloh18:
	adrp	x8, _mmHDP_HOST_PATH_CNTL@GOTPAGE
Lloh19:
	ldr	x8, [x8, _mmHDP_HOST_PATH_CNTL@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
	bl	_RREG32
Lloh21:
	adrp	x8, _HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK@GOTPAGE
Lloh22:
	ldr	x8, [x8, _HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	tst	w8, w0
	b.ne	LBB0_8
; %bb.7:
Lloh24:
	adrp	x8, _AMD_CG_SUPPORT_HDP_MGCG@GOTPAGE
Lloh25:
	ldr	x8, [x8, _AMD_CG_SUPPORT_HDP_MGCG@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_8:
Lloh27:
	adrp	x8, _ixCGTT_ROM_CLK_CTRL0@GOTPAGE
Lloh28:
	ldr	x8, [x8, _ixCGTT_ROM_CLK_CTRL0@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	bl	_RREG32_SMC
Lloh30:
	adrp	x8, _CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK@GOTPAGE
Lloh31:
	ldr	x8, [x8, _CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
	tst	w8, w0
	b.ne	LBB0_10
; %bb.9:
Lloh33:
	adrp	x8, _AMD_CG_SUPPORT_ROM_MGCG@GOTPAGE
Lloh34:
	ldr	x8, [x8, _AMD_CG_SUPPORT_ROM_MGCG@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_10:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.cfi_endproc
                                        ; -- End function
	.comm	_ixPCIE_CNTL2,4,2               ; @ixPCIE_CNTL2
	.comm	_PCIE_CNTL2__SLV_MEM_LS_EN_MASK,4,2 ; @PCIE_CNTL2__SLV_MEM_LS_EN_MASK
	.comm	_AMD_CG_SUPPORT_BIF_LS,4,2      ; @AMD_CG_SUPPORT_BIF_LS
	.comm	_mmHDP_MEM_POWER_LS,4,2         ; @mmHDP_MEM_POWER_LS
	.comm	_HDP_MEM_POWER_LS__LS_ENABLE_MASK,4,2 ; @HDP_MEM_POWER_LS__LS_ENABLE_MASK
	.comm	_AMD_CG_SUPPORT_HDP_LS,4,2      ; @AMD_CG_SUPPORT_HDP_LS
	.comm	_mmHDP_HOST_PATH_CNTL,4,2       ; @mmHDP_HOST_PATH_CNTL
	.comm	_HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK,4,2 ; @HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK
	.comm	_AMD_CG_SUPPORT_HDP_MGCG,4,2    ; @AMD_CG_SUPPORT_HDP_MGCG
	.comm	_ixCGTT_ROM_CLK_CTRL0,4,2       ; @ixCGTT_ROM_CLK_CTRL0
	.comm	_CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK,4,2 ; @CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK
	.comm	_AMD_CG_SUPPORT_ROM_MGCG,4,2    ; @AMD_CG_SUPPORT_ROM_MGCG
	.no_dead_strip	_vi_common_get_clockgating_state
.subsections_via_symbols
