	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_dpm_get_sclk            ## -- Begin function amdgpu_dpm_get_sclk
	.p2align	4, 0x90
_amdgpu_dpm_get_sclk:                   ## @amdgpu_dpm_get_sclk
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r15d
	movq	%rdi, %rbx
	callq	_is_support_sw_smu
	testq	%rax, %rax
	je	LBB0_4
## %bb.1:
	addq	$16, %rbx
	movq	_SMU_GFXCLK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%r14d, %r14d
	testl	%r15d, %r15d
	leaq	-28(%rbp), %rcx
	movq	%rcx, %rdx
	cmoveq	%r14, %rdx
	cmovneq	%r14, %rcx
	movq	%rbx, %rdi
	callq	_smu_get_dpm_freq_range
	testl	%eax, %eax
	jne	LBB0_3
## %bb.2:
	imull	$100, -28(%rbp), %r14d
LBB0_3:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_4:
	movq	8(%rbx), %rax
	movq	(%rax), %rax
	movl	(%rbx), %edi
	movl	%r15d, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmpq	*%rax                           ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_SMU_GFXCLK,4,2                 ## @SMU_GFXCLK
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_dpm_get_sclk            ; -- Begin function amdgpu_dpm_get_sclk
	.p2align	2
_amdgpu_dpm_get_sclk:                   ; @amdgpu_dpm_get_sclk
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #48
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x1
	mov	x20, x0
	bl	_is_support_sw_smu
	cbz	x0, LBB0_3
; %bb.1:
Lloh0:
	adrp	x8, _SMU_GFXCLK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _SMU_GFXCLK@GOTPAGEOFF]
	add	x0, x20, #16
Lloh2:
	ldr	w1, [x8]
	cmp	w19, #0
	add	x8, sp, #12
	csel	x2, xzr, x8, eq
	csel	x3, x8, xzr, eq
	bl	_smu_get_dpm_freq_range
	cbz	w0, LBB0_4
; %bb.2:
	mov	w0, #0
	b	LBB0_5
LBB0_3:
	ldr	x8, [x20, #8]
	ldr	x2, [x8]
	ldr	w0, [x20]
	mov	x1, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	br	x2
LBB0_4:
	ldr	w8, [sp, #12]
	mov	w9, #100
	mul	w0, w8, w9
LBB0_5:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_SMU_GFXCLK,4,2                 ; @SMU_GFXCLK
.subsections_via_symbols
