	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_surface_init            ## -- Begin function radeon_surface_init
	.p2align	4, 0x90
_radeon_surface_init:                   ## @radeon_surface_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	(%rdi), %rax
	movq	_CHIP_R600@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_8
## %bb.1:
	movq	_RADEON_GEM_MAX_SURFACES@GOTPCREL(%rip), %r15
	cmpl	$0, (%r15)
	jle	LBB0_7
## %bb.2:
	movq	%rdi, %r14
	xorl	%ebx, %ebx
	jmp	LBB0_3
	.p2align	4, 0x90
LBB0_5:                                 ##   in Loop: Header=BB0_3 Depth=1
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_radeon_clear_surface_reg
LBB0_6:                                 ##   in Loop: Header=BB0_3 Depth=1
	incq	%rbx
	movslq	(%r15), %rax
	cmpq	%rax, %rbx
	jge	LBB0_7
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movq	8(%r14), %rax
	movq	(%rax,%rbx,8), %rdi
	testq	%rdi, %rdi
	je	LBB0_5
## %bb.4:                               ##   in Loop: Header=BB0_3 Depth=1
	callq	_radeon_bo_get_surface_reg
	jmp	LBB0_6
LBB0_8:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_7:
	movq	_RADEON_SURFACE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_CHIP_R600,8,3                  ## @CHIP_R600
	.comm	_RADEON_GEM_MAX_SURFACES,4,2    ## @RADEON_GEM_MAX_SURFACES
	.comm	_RADEON_SURFACE_CNTL,4,2        ## @RADEON_SURFACE_CNTL
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_surface_init            ; -- Begin function radeon_surface_init
	.p2align	2
_radeon_surface_init:                   ; @radeon_surface_init
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	ldr	x8, [x0]
Lloh0:
	adrp	x9, _CHIP_R600@GOTPAGE
Lloh1:
	ldr	x9, [x9, _CHIP_R600@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_7
; %bb.1:
Lloh3:
	adrp	x21, _RADEON_GEM_MAX_SURFACES@GOTPAGE
Lloh4:
	ldr	x21, [x21, _RADEON_GEM_MAX_SURFACES@GOTPAGEOFF]
	ldr	w8, [x21]
	cmp	w8, #1
	b.lt	LBB0_8
; %bb.2:
	mov	x19, x0
	mov	x20, #0
	b	LBB0_5
LBB0_3:                                 ;   in Loop: Header=BB0_5 Depth=1
	mov	x0, x19
	mov	x1, x20
	bl	_radeon_clear_surface_reg
LBB0_4:                                 ;   in Loop: Header=BB0_5 Depth=1
	add	x20, x20, #1
	ldrsw	x8, [x21]
	cmp	x20, x8
	b.ge	LBB0_8
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #8]
	ldr	x0, [x8, x20, lsl #3]
	cbz	x0, LBB0_3
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	bl	_radeon_bo_get_surface_reg
	b	LBB0_4
LBB0_7:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_8:
Lloh5:
	adrp	x8, _RADEON_SURFACE_CNTL@GOTPAGE
Lloh6:
	ldr	x8, [x8, _RADEON_SURFACE_CNTL@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
	mov	w1, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.cfi_endproc
                                        ; -- End function
	.comm	_CHIP_R600,8,3                  ; @CHIP_R600
	.comm	_RADEON_GEM_MAX_SURFACES,4,2    ; @RADEON_GEM_MAX_SURFACES
	.comm	_RADEON_SURFACE_CNTL,4,2        ; @RADEON_SURFACE_CNTL
.subsections_via_symbols
