	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function analogix_dp_process_equalizer_training
_analogix_dp_process_equalizer_training: ## @analogix_dp_process_equalizer_training
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	subq	$48, %rsp
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -40(%rbp)
	movl	$400, %edi                      ## imm = 0x190
	movl	$401, %esi                      ## imm = 0x191
	callq	_usleep_range
	movl	(%r12), %r14d
	leaq	32(%r12), %r15
	movq	_DP_LANE0_1_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-48(%rbp), %rdx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	_drm_dp_dpcd_read
	testl	%eax, %eax
	js	LBB0_3
## %bb.1:
	leaq	-48(%rbp), %rdi
	movl	%r14d, %esi
	callq	_analogix_dp_clock_recovery_ok
	testq	%rax, %rax
	je	LBB0_6
LBB0_2:
	movq	%r12, %rdi
	callq	_analogix_dp_reduce_link_rate
	movq	_EIO@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
	jmp	LBB0_4
LBB0_6:
	movq	_DP_ADJUST_REQUEST_LANE0_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-56(%rbp), %rdx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	_drm_dp_dpcd_read
	testl	%eax, %eax
	js	LBB0_3
## %bb.7:
	movq	_DP_LANE_ALIGN_STATUS_UPDATED@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-60(%rbp), %rdx
	movq	%r15, %rdi
	callq	_drm_dp_dpcd_readb
	testl	%eax, %eax
	js	LBB0_3
## %bb.8:
	leaq	-56(%rbp), %rsi
	movq	%r12, %rdi
	callq	_analogix_dp_get_adjust_training_lane
	movl	-60(%rbp), %esi
	leaq	-48(%rbp), %rdi
	movl	%r14d, %edx
	callq	_analogix_dp_channel_eq_ok
	testl	%eax, %eax
	je	LBB0_16
## %bb.9:
	movq	8(%r12), %rax
	leaq	1(%rax), %rcx
	movq	%rcx, 8(%r12)
	movq	_MAX_EQ_LOOP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_18
## %bb.10:
	testl	%r14d, %r14d
	jle	LBB0_13
## %bb.11:
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_12:                                ## =>This Inner Loop Header: Depth=1
	movq	16(%r12), %rax
	movl	(%rax,%rbx,4), %esi
	movq	%r12, %rdi
	movl	%ebx, %edx
	callq	_analogix_dp_set_lane_link_training
	incq	%rbx
	cmpq	%rbx, %r14
	jne	LBB0_12
LBB0_13:
	movq	_DP_TRAINING_LANE0_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	16(%r12), %rdx
	movq	%r15, %rdi
	movl	%r14d, %ecx
	callq	_drm_dp_dpcd_write
	movl	%eax, %ebx
	sarl	$31, %ebx
	andl	%eax, %ebx
	jmp	LBB0_4
LBB0_16:
	movq	%r12, %rdi
	callq	_analogix_dp_training_pattern_dis
	testl	%eax, %eax
	js	LBB0_3
## %bb.17:
	movl	36(%r12), %edi
	leaq	L_.str(%rip), %rsi
	xorl	%ebx, %ebx
	xorl	%eax, %eax
	callq	_dev_dbg
	leaq	-72(%rbp), %r14
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	_analogix_dp_get_link_bandwidth
	movl	-72(%rbp), %edx
	movl	%edx, 4(%r12)
	movl	36(%r12), %edi
	leaq	L_.str.1(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_dbg
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	_analogix_dp_get_lane_count
	movl	-72(%rbp), %edx
	movl	%edx, (%r12)
	movl	36(%r12), %edi
	leaq	L_.str.2(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_dbg
	movq	_FINISHED@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 24(%r12)
	jmp	LBB0_4
LBB0_3:
	movl	%eax, %ebx
LBB0_4:
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	cmpq	-40(%rbp), %rax
	jne	LBB0_20
## %bb.5:
	movl	%ebx, %eax
	addq	$48, %rsp
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_18:
	movl	36(%r12), %edi
	leaq	L_.str.3(%rip), %rsi
	callq	_dev_err
	jmp	LBB0_2
LBB0_20:
	callq	___stack_chk_fail
	.cfi_endproc
                                        ## -- End function
	.comm	_DP_LANE0_1_STATUS,4,2          ## @DP_LANE0_1_STATUS
	.comm	_EIO,4,2                        ## @EIO
	.comm	_DP_ADJUST_REQUEST_LANE0_1,4,2  ## @DP_ADJUST_REQUEST_LANE0_1
	.comm	_DP_LANE_ALIGN_STATUS_UPDATED,4,2 ## @DP_LANE_ALIGN_STATUS_UPDATED
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Link Training success!\n"

L_.str.1:                               ## @.str.1
	.asciz	"final bandwidth = %.2x\n"

L_.str.2:                               ## @.str.2
	.asciz	"final lane count = %.2x\n"

	.comm	_FINISHED,4,2                   ## @FINISHED
	.comm	_MAX_EQ_LOOP,8,3                ## @MAX_EQ_LOOP
L_.str.3:                               ## @.str.3
	.asciz	"EQ Max loop\n"

	.comm	_DP_TRAINING_LANE0_SET,4,2      ## @DP_TRAINING_LANE0_SET
	.no_dead_strip	_analogix_dp_process_equalizer_training
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function analogix_dp_process_equalizer_training
_analogix_dp_process_equalizer_training: ; @analogix_dp_process_equalizer_training
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, ___stack_chk_guard@GOTPAGE
Lloh1:
	ldr	x8, [x8, ___stack_chk_guard@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	str	x8, [sp, #40]
	mov	w0, #400
	mov	w1, #401
	bl	_usleep_range
	mov	x21, x19
	ldr	w20, [x21], #32
Lloh3:
	adrp	x8, _DP_LANE0_1_STATUS@GOTPAGE
Lloh4:
	ldr	x8, [x8, _DP_LANE0_1_STATUS@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	add	x2, sp, #32
	mov	x0, x21
	mov	w3, #2
	bl	_drm_dp_dpcd_read
	tbnz	w0, #31, LBB0_3
; %bb.1:
	add	x0, sp, #32
	mov	x1, x20
	bl	_analogix_dp_clock_recovery_ok
	cbz	x0, LBB0_5
LBB0_2:
	mov	x0, x19
	bl	_analogix_dp_reduce_link_rate
Lloh6:
	adrp	x8, _EIO@GOTPAGE
Lloh7:
	ldr	x8, [x8, _EIO@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_3:
	ldr	x8, [sp, #40]
Lloh9:
	adrp	x9, ___stack_chk_guard@GOTPAGE
Lloh10:
	ldr	x9, [x9, ___stack_chk_guard@GOTPAGEOFF]
Lloh11:
	ldr	x9, [x9]
	cmp	x9, x8
	b.ne	LBB0_16
; %bb.4:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_5:
Lloh12:
	adrp	x8, _DP_ADJUST_REQUEST_LANE0_1@GOTPAGE
Lloh13:
	ldr	x8, [x8, _DP_ADJUST_REQUEST_LANE0_1@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	add	x2, sp, #24
	mov	x0, x21
	mov	w3, #2
	bl	_drm_dp_dpcd_read
	tbnz	w0, #31, LBB0_3
; %bb.6:
Lloh15:
	adrp	x8, _DP_LANE_ALIGN_STATUS_UPDATED@GOTPAGE
Lloh16:
	ldr	x8, [x8, _DP_LANE_ALIGN_STATUS_UPDATED@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	add	x2, sp, #12
	mov	x0, x21
	bl	_drm_dp_dpcd_readb
	tbnz	w0, #31, LBB0_3
; %bb.7:
	add	x1, sp, #24
	mov	x0, x19
	bl	_analogix_dp_get_adjust_training_lane
	ldr	w1, [sp, #12]
	add	x0, sp, #32
	mov	x2, x20
	bl	_analogix_dp_channel_eq_ok
	cbz	w0, LBB0_13
; %bb.8:
	ldr	x8, [x19, #8]
	add	x9, x8, #1
	str	x9, [x19, #8]
Lloh18:
	adrp	x9, _MAX_EQ_LOOP@GOTPAGE
Lloh19:
	ldr	x9, [x9, _MAX_EQ_LOOP@GOTPAGEOFF]
Lloh20:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_15
; %bb.9:
	cmp	w20, #1
	b.lt	LBB0_12
; %bb.10:
	mov	x22, #0
LBB0_11:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #16]
	ldr	w1, [x8, x22, lsl #2]
	mov	x0, x19
	mov	x2, x22
	bl	_analogix_dp_set_lane_link_training
	add	x22, x22, #1
	cmp	x20, x22
	b.ne	LBB0_11
LBB0_12:
Lloh21:
	adrp	x8, _DP_TRAINING_LANE0_SET@GOTPAGE
Lloh22:
	ldr	x8, [x8, _DP_TRAINING_LANE0_SET@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	ldr	x2, [x19, #16]
	mov	x0, x21
	mov	x3, x20
	bl	_drm_dp_dpcd_write
	cmp	w0, #0
	csel	w0, w0, wzr, lt
	b	LBB0_3
LBB0_13:
	mov	x0, x19
	bl	_analogix_dp_training_pattern_dis
	tbnz	w0, #31, LBB0_3
; %bb.14:
	ldr	w0, [x19, #36]
Lloh24:
	adrp	x1, l_.str@PAGE
Lloh25:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_dbg
	add	x1, sp, #16
	mov	x0, x19
	bl	_analogix_dp_get_link_bandwidth
	ldr	x8, [sp, #16]
	str	w8, [x19, #4]
	ldr	w0, [x19, #36]
	str	x8, [sp]
Lloh26:
	adrp	x1, l_.str.1@PAGE
Lloh27:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_dbg
	add	x1, sp, #16
	mov	x0, x19
	bl	_analogix_dp_get_lane_count
	ldr	x8, [sp, #16]
	str	w8, [x19]
	ldr	w0, [x19, #36]
	str	x8, [sp]
Lloh28:
	adrp	x1, l_.str.2@PAGE
Lloh29:
	add	x1, x1, l_.str.2@PAGEOFF
	bl	_dev_dbg
	mov	w0, #0
Lloh30:
	adrp	x8, _FINISHED@GOTPAGE
Lloh31:
	ldr	x8, [x8, _FINISHED@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
	str	w8, [x19, #24]
	b	LBB0_3
LBB0_15:
	ldr	w0, [x19, #36]
Lloh33:
	adrp	x1, l_.str.3@PAGE
Lloh34:
	add	x1, x1, l_.str.3@PAGEOFF
	bl	_dev_err
	b	LBB0_2
LBB0_16:
	bl	___stack_chk_fail
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpAdd	Lloh28, Lloh29
	.loh AdrpAdd	Lloh26, Lloh27
	.loh AdrpAdd	Lloh24, Lloh25
	.loh AdrpAdd	Lloh33, Lloh34
	.cfi_endproc
                                        ; -- End function
	.comm	_DP_LANE0_1_STATUS,4,2          ; @DP_LANE0_1_STATUS
	.comm	_EIO,4,2                        ; @EIO
	.comm	_DP_ADJUST_REQUEST_LANE0_1,4,2  ; @DP_ADJUST_REQUEST_LANE0_1
	.comm	_DP_LANE_ALIGN_STATUS_UPDATED,4,2 ; @DP_LANE_ALIGN_STATUS_UPDATED
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Link Training success!\n"

l_.str.1:                               ; @.str.1
	.asciz	"final bandwidth = %.2x\n"

l_.str.2:                               ; @.str.2
	.asciz	"final lane count = %.2x\n"

	.comm	_FINISHED,4,2                   ; @FINISHED
	.comm	_MAX_EQ_LOOP,8,3                ; @MAX_EQ_LOOP
l_.str.3:                               ; @.str.3
	.asciz	"EQ Max loop\n"

	.comm	_DP_TRAINING_LANE0_SET,4,2      ; @DP_TRAINING_LANE0_SET
	.no_dead_strip	_analogix_dp_process_equalizer_training
.subsections_via_symbols
