	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function etnaviv_gpu_hw_init
_etnaviv_gpu_hw_init:                   ## @etnaviv_gpu_hw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	_GC320@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movl	$20487, %edx                    ## imm = 0x5007
	callq	_etnaviv_is_model_rev
	testq	%rax, %rax
	jne	LBB0_2
## %bb.1:
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	$21024, %edx                    ## imm = 0x5220
	callq	_etnaviv_is_model_rev
	testq	%rax, %rax
	je	LBB0_4
LBB0_2:
	movq	_VIVS_HI_CHIP_TIME@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_gpu_read
	cmpl	$33956864, %eax                 ## imm = 0x2062400
	je	LBB0_4
## %bb.3:
	movq	_VIVS_MC_DEBUG_MEMORY@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_gpu_read
                                        ## kill: def $eax killed $eax def $rax
	andl	$-256, %eax
	xorl	%ecx, %ecx
	cmpl	$20487, 8(%r15)                 ## imm = 0x5007
	sete	%cl
	leal	(%rax,%rcx,4), %edx
	addl	$8, %edx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_gpu_write
LBB0_4:
	movq	%r15, %rdi
	callq	_etnaviv_gpu_enable_mlcg
	movq	_VIVS_HI_AXI_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	$2, %edi
	callq	_VIVS_HI_AXI_CONFIG_AWCACHE
	movl	%eax, %ebx
	movl	$2, %edi
	callq	_VIVS_HI_AXI_CONFIG_ARCACHE
	orl	%eax, %ebx
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%ebx, %edx
	callq	_gpu_write
	movq	_GC2000@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$20744, %edx                    ## imm = 0x5108
	callq	_etnaviv_is_model_rev
	testq	%rax, %rax
	je	LBB0_6
## %bb.5:
	movq	_VIVS_MC_BUS_CONFIG@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%r15, %rdi
	callq	_gpu_read
	movq	_VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK@GOTPCREL(%rip), %rcx
	movq	_VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	$1, %edi
	callq	_VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG
	movl	%eax, %r12d
	xorl	%edi, %edi
	callq	_VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG
	orl	%eax, %r12d
	orl	%ebx, %r12d
	movl	(%r14), %esi
	movq	%r15, %rdi
	movl	%r12d, %edx
	callq	_gpu_write
LBB0_6:
	movq	(%r15), %rax
	movq	_ETNA_SEC_KERNEL@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_8
## %bb.7:
	movq	_VIVS_MMUv2_AHB_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_gpu_read
	movq	_VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	%eax, %edx
	callq	_gpu_write
LBB0_8:
	movq	%r15, %rdi
	callq	_etnaviv_gpu_setup_pulse_eater
	movq	_VIVS_HI_INTR_ENBL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$-1, %edx
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_gpu_write                      ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_GC320,4,2                      ## @GC320
	.comm	_VIVS_HI_CHIP_TIME,4,2          ## @VIVS_HI_CHIP_TIME
	.comm	_VIVS_MC_DEBUG_MEMORY,4,2       ## @VIVS_MC_DEBUG_MEMORY
	.comm	_VIVS_HI_AXI_CONFIG,4,2         ## @VIVS_HI_AXI_CONFIG
	.comm	_GC2000,4,2                     ## @GC2000
	.comm	_VIVS_MC_BUS_CONFIG,4,2         ## @VIVS_MC_BUS_CONFIG
	.comm	_VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK,4,2 ## @VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK
	.comm	_VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK,4,2 ## @VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK
	.comm	_ETNA_SEC_KERNEL,8,3            ## @ETNA_SEC_KERNEL
	.comm	_VIVS_MMUv2_AHB_CONTROL,4,2     ## @VIVS_MMUv2_AHB_CONTROL
	.comm	_VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS,4,2 ## @VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS
	.comm	_VIVS_HI_INTR_ENBL,4,2          ## @VIVS_HI_INTR_ENBL
	.no_dead_strip	_etnaviv_gpu_hw_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function etnaviv_gpu_hw_init
_etnaviv_gpu_hw_init:                   ; @etnaviv_gpu_hw_init
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x20, _GC320@GOTPAGE
Lloh1:
	ldr	x20, [x20, _GC320@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	w2, #20487
	bl	_etnaviv_is_model_rev
	cbnz	x0, LBB0_2
; %bb.1:
	ldr	w1, [x20]
	mov	x0, x19
	mov	w2, #21024
	bl	_etnaviv_is_model_rev
	cbz	x0, LBB0_4
LBB0_2:
Lloh2:
	adrp	x8, _VIVS_HI_CHIP_TIME@GOTPAGE
Lloh3:
	ldr	x8, [x8, _VIVS_HI_CHIP_TIME@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_gpu_read
	mov	w8, #9216
	movk	w8, #518, lsl #16
	cmp	w0, w8
	b.eq	LBB0_4
; %bb.3:
Lloh5:
	adrp	x20, _VIVS_MC_DEBUG_MEMORY@GOTPAGE
Lloh6:
	ldr	x20, [x20, _VIVS_MC_DEBUG_MEMORY@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_gpu_read
	and	w8, w0, #0xffffff00
	ldr	w9, [x19, #8]
	mov	w10, #20487
	mov	w11, #8
	mov	w12, #12
	cmp	w9, w10
	csel	w9, w12, w11, eq
	orr	w2, w9, w8
	ldr	w1, [x20]
	mov	x0, x19
	bl	_gpu_write
LBB0_4:
	mov	x0, x19
	bl	_etnaviv_gpu_enable_mlcg
Lloh7:
	adrp	x8, _VIVS_HI_AXI_CONFIG@GOTPAGE
Lloh8:
	ldr	x8, [x8, _VIVS_HI_AXI_CONFIG@GOTPAGEOFF]
Lloh9:
	ldr	w20, [x8]
	mov	w0, #2
	bl	_VIVS_HI_AXI_CONFIG_AWCACHE
	mov	x21, x0
	mov	w0, #2
	bl	_VIVS_HI_AXI_CONFIG_ARCACHE
	orr	w2, w0, w21
	mov	x0, x19
	mov	x1, x20
	bl	_gpu_write
Lloh10:
	adrp	x8, _GC2000@GOTPAGE
Lloh11:
	ldr	x8, [x8, _GC2000@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #20744
	bl	_etnaviv_is_model_rev
	cbz	x0, LBB0_6
; %bb.5:
Lloh13:
	adrp	x21, _VIVS_MC_BUS_CONFIG@GOTPAGE
Lloh14:
	ldr	x21, [x21, _VIVS_MC_BUS_CONFIG@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_gpu_read
Lloh15:
	adrp	x8, _VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK@GOTPAGE
Lloh16:
	ldr	x8, [x8, _VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
Lloh18:
	adrp	x9, _VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK@GOTPAGE
Lloh19:
	ldr	x9, [x9, _VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w22, w0, w8
	mov	w0, #1
	bl	_VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG
	mov	x20, x0
	mov	w0, #0
	bl	_VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG
	orr	w8, w0, w20
	orr	w2, w8, w22
	ldr	w1, [x21]
	mov	x0, x19
	bl	_gpu_write
LBB0_6:
	ldr	x8, [x19]
Lloh21:
	adrp	x9, _ETNA_SEC_KERNEL@GOTPAGE
Lloh22:
	ldr	x9, [x9, _ETNA_SEC_KERNEL@GOTPAGEOFF]
Lloh23:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_8
; %bb.7:
Lloh24:
	adrp	x20, _VIVS_MMUv2_AHB_CONTROL@GOTPAGE
Lloh25:
	ldr	x20, [x20, _VIVS_MMUv2_AHB_CONTROL@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_gpu_read
Lloh26:
	adrp	x8, _VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS@GOTPAGE
Lloh27:
	ldr	x8, [x8, _VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
	orr	w2, w8, w0
	ldr	w1, [x20]
	mov	x0, x19
	bl	_gpu_write
LBB0_8:
	mov	x0, x19
	bl	_etnaviv_gpu_setup_pulse_eater
Lloh29:
	adrp	x8, _VIVS_HI_INTR_ENBL@GOTPAGE
Lloh30:
	ldr	x8, [x8, _VIVS_HI_INTR_ENBL@GOTPAGEOFF]
Lloh31:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_gpu_write
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.cfi_endproc
                                        ; -- End function
	.comm	_GC320,4,2                      ; @GC320
	.comm	_VIVS_HI_CHIP_TIME,4,2          ; @VIVS_HI_CHIP_TIME
	.comm	_VIVS_MC_DEBUG_MEMORY,4,2       ; @VIVS_MC_DEBUG_MEMORY
	.comm	_VIVS_HI_AXI_CONFIG,4,2         ; @VIVS_HI_AXI_CONFIG
	.comm	_GC2000,4,2                     ; @GC2000
	.comm	_VIVS_MC_BUS_CONFIG,4,2         ; @VIVS_MC_BUS_CONFIG
	.comm	_VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK,4,2 ; @VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK
	.comm	_VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK,4,2 ; @VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK
	.comm	_ETNA_SEC_KERNEL,8,3            ; @ETNA_SEC_KERNEL
	.comm	_VIVS_MMUv2_AHB_CONTROL,4,2     ; @VIVS_MMUv2_AHB_CONTROL
	.comm	_VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS,4,2 ; @VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS
	.comm	_VIVS_HI_INTR_ENBL,4,2          ; @VIVS_HI_INTR_ENBL
	.no_dead_strip	_etnaviv_gpu_hw_init
.subsections_via_symbols
