	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vce_v3_0_mc_resume
_vce_v3_0_mc_resume:                    ## @vce_v3_0_mc_resume
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %rbx
	movq	_mmVCE_CLOCK_GATING_A@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	movl	$-65537, %edx                   ## imm = 0xFFFEFFFF
	callq	_WREG32_P
	movq	_mmVCE_UENC_CLOCK_GATING@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$2093056, %esi                  ## imm = 0x1FF000
	movl	$6295551, %edx                  ## imm = 0x600FFF
	callq	_WREG32_P
	movq	_mmVCE_UENC_REG_CLOCK_GATING@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$63, %esi
	movl	$-64, %edx
	callq	_WREG32_P
	movq	_mmVCE_CLOCK_GATING_B@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$511, %esi                      ## imm = 0x1FF
	callq	_WREG32
	movq	_mmVCE_LMI_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$3768320, %esi                  ## imm = 0x398000
	callq	_WREG32
	movq	_mmVCE_LMI_CACHE_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	movl	$-2, %edx
	callq	_WREG32_P
	movq	_mmVCE_LMI_SWAP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmVCE_LMI_SWAP_CNTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmVCE_LMI_VM_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmVCE_VCPU_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1048576, %esi                  ## imm = 0x100000
	callq	_WREG32_OR
	movq	(%rbx), %rax
	movq	_CHIP_STONEY@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_1
## %bb.2:
	addq	$8, %rbx
	movq	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR@GOTPCREL(%rip), %rax
	movq	%rbx, %r15
	jmp	LBB0_3
LBB0_1:
	movq	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	leaq	8(%rbx), %r15
	movl	8(%rbx), %esi
	sarl	$8, %esi
	callq	_WREG32
	movq	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	8(%rbx), %esi
	sarl	$8, %esi
	callq	_WREG32
	movq	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR2@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %edi
	movl	(%r15), %esi
	sarl	$8, %esi
	callq	_WREG32
	movq	_AMDGPU_VCE_FIRMWARE_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_VCE_V3_0_FW_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_mmVCE_VCPU_CACHE_OFFSET0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r15d, %esi
	andl	$2147483647, %esi               ## imm = 0x7FFFFFFF
	callq	_WREG32
	movq	_mmVCE_VCPU_CACHE_SIZE0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	testl	%r14d, %r14d
	je	LBB0_4
## %bb.5:
	movq	_VCE_V3_0_STACK_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_VCE_V3_0_DATA_SIZE@GOTPCREL(%rip), %r12
	addl	%r15d, %ebx
	addl	%r14d, %ebx
	addl	(%r12), %ebx
	movq	_mmVCE_VCPU_CACHE_OFFSET1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	andl	$268435455, %esi                ## imm = 0xFFFFFFF
	callq	_WREG32
	movq	_mmVCE_VCPU_CACHE_SIZE1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	addl	%r14d, %ebx
	movl	(%r12), %r14d
	movq	_mmVCE_VCPU_CACHE_OFFSET2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	andl	$268435455, %ebx                ## imm = 0xFFFFFFF
	jmp	LBB0_6
LBB0_4:
	addl	%r15d, %ebx
	movq	_VCE_V3_0_STACK_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_mmVCE_VCPU_CACHE_OFFSET1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	andl	$2147483647, %esi               ## imm = 0x7FFFFFFF
	callq	_WREG32
	movq	_mmVCE_VCPU_CACHE_SIZE1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	addl	%r14d, %ebx
	movq	_VCE_V3_0_DATA_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_mmVCE_VCPU_CACHE_OFFSET2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	andl	$2147483647, %ebx               ## imm = 0x7FFFFFFF
LBB0_6:
	movl	%ebx, %esi
	callq	_WREG32
	movq	_mmVCE_VCPU_CACHE_SIZE2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_mmVCE_LMI_CTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	movl	$-257, %edx                     ## imm = 0xFEFF
	callq	_WREG32_P
	movq	_VCE_SYS_INT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_VCE_SYS_INT_TRAP_INTERRUPT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %edx
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_FIELD                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_mmVCE_CLOCK_GATING_A,4,2       ## @mmVCE_CLOCK_GATING_A
	.comm	_mmVCE_UENC_CLOCK_GATING,4,2    ## @mmVCE_UENC_CLOCK_GATING
	.comm	_mmVCE_UENC_REG_CLOCK_GATING,4,2 ## @mmVCE_UENC_REG_CLOCK_GATING
	.comm	_mmVCE_CLOCK_GATING_B,4,2       ## @mmVCE_CLOCK_GATING_B
	.comm	_mmVCE_LMI_CTRL,4,2             ## @mmVCE_LMI_CTRL
	.comm	_mmVCE_LMI_CACHE_CTRL,4,2       ## @mmVCE_LMI_CACHE_CTRL
	.comm	_mmVCE_LMI_SWAP_CNTL,4,2        ## @mmVCE_LMI_SWAP_CNTL
	.comm	_mmVCE_LMI_SWAP_CNTL1,4,2       ## @mmVCE_LMI_SWAP_CNTL1
	.comm	_mmVCE_LMI_VM_CTRL,4,2          ## @mmVCE_LMI_VM_CTRL
	.comm	_mmVCE_VCPU_CNTL,4,2            ## @mmVCE_VCPU_CNTL
	.comm	_CHIP_STONEY,8,3                ## @CHIP_STONEY
	.comm	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR0,4,2 ## @mmVCE_LMI_VCPU_CACHE_40BIT_BAR0
	.comm	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR1,4,2 ## @mmVCE_LMI_VCPU_CACHE_40BIT_BAR1
	.comm	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR2,4,2 ## @mmVCE_LMI_VCPU_CACHE_40BIT_BAR2
	.comm	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR,4,2 ## @mmVCE_LMI_VCPU_CACHE_40BIT_BAR
	.comm	_AMDGPU_VCE_FIRMWARE_OFFSET,4,2 ## @AMDGPU_VCE_FIRMWARE_OFFSET
	.comm	_VCE_V3_0_FW_SIZE,4,2           ## @VCE_V3_0_FW_SIZE
	.comm	_mmVCE_VCPU_CACHE_OFFSET0,4,2   ## @mmVCE_VCPU_CACHE_OFFSET0
	.comm	_mmVCE_VCPU_CACHE_SIZE0,4,2     ## @mmVCE_VCPU_CACHE_SIZE0
	.comm	_VCE_V3_0_STACK_SIZE,4,2        ## @VCE_V3_0_STACK_SIZE
	.comm	_mmVCE_VCPU_CACHE_OFFSET1,4,2   ## @mmVCE_VCPU_CACHE_OFFSET1
	.comm	_mmVCE_VCPU_CACHE_SIZE1,4,2     ## @mmVCE_VCPU_CACHE_SIZE1
	.comm	_VCE_V3_0_DATA_SIZE,4,2         ## @VCE_V3_0_DATA_SIZE
	.comm	_mmVCE_VCPU_CACHE_OFFSET2,4,2   ## @mmVCE_VCPU_CACHE_OFFSET2
	.comm	_mmVCE_VCPU_CACHE_SIZE2,4,2     ## @mmVCE_VCPU_CACHE_SIZE2
	.comm	_mmVCE_LMI_CTRL2,4,2            ## @mmVCE_LMI_CTRL2
	.comm	_VCE_SYS_INT_EN,4,2             ## @VCE_SYS_INT_EN
	.comm	_VCE_SYS_INT_TRAP_INTERRUPT_EN,4,2 ## @VCE_SYS_INT_TRAP_INTERRUPT_EN
	.no_dead_strip	_vce_v3_0_mc_resume
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vce_v3_0_mc_resume
_vce_v3_0_mc_resume:                    ; @vce_v3_0_mc_resume
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x1
	mov	x20, x0
Lloh0:
	adrp	x8, _mmVCE_CLOCK_GATING_A@GOTPAGE
Lloh1:
	ldr	x8, [x8, _mmVCE_CLOCK_GATING_A@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	mov	w1, #0
	mov	w2, #-65537
	bl	_WREG32_P
Lloh3:
	adrp	x8, _mmVCE_UENC_CLOCK_GATING@GOTPAGE
Lloh4:
	ldr	x8, [x8, _mmVCE_UENC_CLOCK_GATING@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	mov	w1, #2093056
	mov	w2, #4095
	movk	w2, #96, lsl #16
	bl	_WREG32_P
Lloh6:
	adrp	x8, _mmVCE_UENC_REG_CLOCK_GATING@GOTPAGE
Lloh7:
	ldr	x8, [x8, _mmVCE_UENC_REG_CLOCK_GATING@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	mov	w1, #63
	mov	w2, #-64
	bl	_WREG32_P
Lloh9:
	adrp	x8, _mmVCE_CLOCK_GATING_B@GOTPAGE
Lloh10:
	ldr	x8, [x8, _mmVCE_CLOCK_GATING_B@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	mov	w1, #511
	bl	_WREG32
Lloh12:
	adrp	x8, _mmVCE_LMI_CTRL@GOTPAGE
Lloh13:
	ldr	x8, [x8, _mmVCE_LMI_CTRL@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	mov	w1, #32768
	movk	w1, #57, lsl #16
	bl	_WREG32
Lloh15:
	adrp	x8, _mmVCE_LMI_CACHE_CTRL@GOTPAGE
Lloh16:
	ldr	x8, [x8, _mmVCE_LMI_CACHE_CTRL@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	mov	w1, #0
	mov	w2, #-2
	bl	_WREG32_P
Lloh18:
	adrp	x8, _mmVCE_LMI_SWAP_CNTL@GOTPAGE
Lloh19:
	ldr	x8, [x8, _mmVCE_LMI_SWAP_CNTL@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh21:
	adrp	x8, _mmVCE_LMI_SWAP_CNTL1@GOTPAGE
Lloh22:
	ldr	x8, [x8, _mmVCE_LMI_SWAP_CNTL1@GOTPAGEOFF]
Lloh23:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh24:
	adrp	x8, _mmVCE_LMI_VM_CTRL@GOTPAGE
Lloh25:
	ldr	x8, [x8, _mmVCE_LMI_VM_CTRL@GOTPAGEOFF]
Lloh26:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh27:
	adrp	x8, _mmVCE_VCPU_CNTL@GOTPAGE
Lloh28:
	ldr	x8, [x8, _mmVCE_VCPU_CNTL@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	mov	w1, #1048576
	bl	_WREG32_OR
	ldr	x8, [x20]
Lloh30:
	adrp	x9, _CHIP_STONEY@GOTPAGE
Lloh31:
	ldr	x9, [x9, _CHIP_STONEY@GOTPAGEOFF]
Lloh32:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_2
; %bb.1:
	add	x20, x20, #8
Lloh33:
	adrp	x8, _mmVCE_LMI_VCPU_CACHE_40BIT_BAR@GOTPAGE
Lloh34:
	ldr	x8, [x8, _mmVCE_LMI_VCPU_CACHE_40BIT_BAR@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:
Lloh35:
	adrp	x8, _mmVCE_LMI_VCPU_CACHE_40BIT_BAR0@GOTPAGE
Lloh36:
	ldr	x8, [x8, _mmVCE_LMI_VCPU_CACHE_40BIT_BAR0@GOTPAGEOFF]
Lloh37:
	ldr	w0, [x8]
	ldr	w8, [x20, #8]!
	asr	w1, w8, #8
	bl	_WREG32
Lloh38:
	adrp	x8, _mmVCE_LMI_VCPU_CACHE_40BIT_BAR1@GOTPAGE
Lloh39:
	ldr	x8, [x8, _mmVCE_LMI_VCPU_CACHE_40BIT_BAR1@GOTPAGEOFF]
Lloh40:
	ldr	w0, [x8]
	ldr	w8, [x20]
	asr	w1, w8, #8
	bl	_WREG32
Lloh41:
	adrp	x8, _mmVCE_LMI_VCPU_CACHE_40BIT_BAR2@GOTPAGE
Lloh42:
	ldr	x8, [x8, _mmVCE_LMI_VCPU_CACHE_40BIT_BAR2@GOTPAGEOFF]
LBB0_3:
	ldr	w0, [x8]
	ldr	w8, [x20]
	asr	w1, w8, #8
	bl	_WREG32
Lloh43:
	adrp	x8, _AMDGPU_VCE_FIRMWARE_OFFSET@GOTPAGE
Lloh44:
	ldr	x8, [x8, _AMDGPU_VCE_FIRMWARE_OFFSET@GOTPAGEOFF]
Lloh45:
	adrp	x9, _VCE_V3_0_FW_SIZE@GOTPAGE
Lloh46:
	ldr	x9, [x9, _VCE_V3_0_FW_SIZE@GOTPAGEOFF]
Lloh47:
	ldr	w21, [x8]
Lloh48:
	ldr	w20, [x9]
Lloh49:
	adrp	x8, _mmVCE_VCPU_CACHE_OFFSET0@GOTPAGE
Lloh50:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_OFFSET0@GOTPAGEOFF]
Lloh51:
	ldr	w0, [x8]
	and	w1, w21, #0x7fffffff
	bl	_WREG32
Lloh52:
	adrp	x8, _mmVCE_VCPU_CACHE_SIZE0@GOTPAGE
Lloh53:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_SIZE0@GOTPAGEOFF]
Lloh54:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh55:
	adrp	x8, _VCE_V3_0_STACK_SIZE@GOTPAGE
Lloh56:
	ldr	x8, [x8, _VCE_V3_0_STACK_SIZE@GOTPAGEOFF]
	cbz	w19, LBB0_5
; %bb.4:
	ldr	w19, [x8]
Lloh57:
	adrp	x22, _VCE_V3_0_DATA_SIZE@GOTPAGE
Lloh58:
	ldr	x22, [x22, _VCE_V3_0_DATA_SIZE@GOTPAGEOFF]
	ldr	w8, [x22]
	add	w9, w20, w21
	add	w9, w9, w19
	add	w20, w9, w8
Lloh59:
	adrp	x8, _mmVCE_VCPU_CACHE_OFFSET1@GOTPAGE
Lloh60:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_OFFSET1@GOTPAGEOFF]
Lloh61:
	ldr	w0, [x8]
	and	w1, w20, #0xfffffff
	bl	_WREG32
Lloh62:
	adrp	x8, _mmVCE_VCPU_CACHE_SIZE1@GOTPAGE
Lloh63:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_SIZE1@GOTPAGEOFF]
Lloh64:
	ldr	w0, [x8]
	mov	x1, x19
	bl	_WREG32
	add	w8, w20, w19
	ldr	w19, [x22]
Lloh65:
	adrp	x9, _mmVCE_VCPU_CACHE_OFFSET2@GOTPAGE
Lloh66:
	ldr	x9, [x9, _mmVCE_VCPU_CACHE_OFFSET2@GOTPAGEOFF]
Lloh67:
	ldr	w0, [x9]
	and	w1, w8, #0xfffffff
	b	LBB0_6
LBB0_5:
	add	w20, w20, w21
	ldr	w19, [x8]
Lloh68:
	adrp	x8, _mmVCE_VCPU_CACHE_OFFSET1@GOTPAGE
Lloh69:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_OFFSET1@GOTPAGEOFF]
Lloh70:
	ldr	w0, [x8]
	and	w1, w20, #0x7fffffff
	bl	_WREG32
Lloh71:
	adrp	x8, _mmVCE_VCPU_CACHE_SIZE1@GOTPAGE
Lloh72:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_SIZE1@GOTPAGEOFF]
Lloh73:
	ldr	w0, [x8]
	mov	x1, x19
	bl	_WREG32
Lloh74:
	adrp	x8, _VCE_V3_0_DATA_SIZE@GOTPAGE
Lloh75:
	ldr	x8, [x8, _VCE_V3_0_DATA_SIZE@GOTPAGEOFF]
	add	w9, w19, w20
Lloh76:
	ldr	w19, [x8]
Lloh77:
	adrp	x8, _mmVCE_VCPU_CACHE_OFFSET2@GOTPAGE
Lloh78:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_OFFSET2@GOTPAGEOFF]
Lloh79:
	ldr	w0, [x8]
	and	w1, w9, #0x7fffffff
LBB0_6:
	bl	_WREG32
Lloh80:
	adrp	x8, _mmVCE_VCPU_CACHE_SIZE2@GOTPAGE
Lloh81:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_SIZE2@GOTPAGEOFF]
Lloh82:
	ldr	w0, [x8]
	mov	x1, x19
	bl	_WREG32
Lloh83:
	adrp	x8, _mmVCE_LMI_CTRL2@GOTPAGE
Lloh84:
	ldr	x8, [x8, _mmVCE_LMI_CTRL2@GOTPAGEOFF]
Lloh85:
	ldr	w0, [x8]
	mov	w1, #0
	mov	w2, #-257
	bl	_WREG32_P
Lloh86:
	adrp	x8, _VCE_SYS_INT_EN@GOTPAGE
Lloh87:
	ldr	x8, [x8, _VCE_SYS_INT_EN@GOTPAGEOFF]
Lloh88:
	ldr	w0, [x8]
Lloh89:
	adrp	x8, _VCE_SYS_INT_TRAP_INTERRUPT_EN@GOTPAGE
Lloh90:
	ldr	x8, [x8, _VCE_SYS_INT_TRAP_INTERRUPT_EN@GOTPAGEOFF]
Lloh91:
	ldr	w1, [x8]
	mov	w2, #1
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32_FIELD
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh47
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.cfi_endproc
                                        ; -- End function
	.comm	_mmVCE_CLOCK_GATING_A,4,2       ; @mmVCE_CLOCK_GATING_A
	.comm	_mmVCE_UENC_CLOCK_GATING,4,2    ; @mmVCE_UENC_CLOCK_GATING
	.comm	_mmVCE_UENC_REG_CLOCK_GATING,4,2 ; @mmVCE_UENC_REG_CLOCK_GATING
	.comm	_mmVCE_CLOCK_GATING_B,4,2       ; @mmVCE_CLOCK_GATING_B
	.comm	_mmVCE_LMI_CTRL,4,2             ; @mmVCE_LMI_CTRL
	.comm	_mmVCE_LMI_CACHE_CTRL,4,2       ; @mmVCE_LMI_CACHE_CTRL
	.comm	_mmVCE_LMI_SWAP_CNTL,4,2        ; @mmVCE_LMI_SWAP_CNTL
	.comm	_mmVCE_LMI_SWAP_CNTL1,4,2       ; @mmVCE_LMI_SWAP_CNTL1
	.comm	_mmVCE_LMI_VM_CTRL,4,2          ; @mmVCE_LMI_VM_CTRL
	.comm	_mmVCE_VCPU_CNTL,4,2            ; @mmVCE_VCPU_CNTL
	.comm	_CHIP_STONEY,8,3                ; @CHIP_STONEY
	.comm	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR0,4,2 ; @mmVCE_LMI_VCPU_CACHE_40BIT_BAR0
	.comm	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR1,4,2 ; @mmVCE_LMI_VCPU_CACHE_40BIT_BAR1
	.comm	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR2,4,2 ; @mmVCE_LMI_VCPU_CACHE_40BIT_BAR2
	.comm	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR,4,2 ; @mmVCE_LMI_VCPU_CACHE_40BIT_BAR
	.comm	_AMDGPU_VCE_FIRMWARE_OFFSET,4,2 ; @AMDGPU_VCE_FIRMWARE_OFFSET
	.comm	_VCE_V3_0_FW_SIZE,4,2           ; @VCE_V3_0_FW_SIZE
	.comm	_mmVCE_VCPU_CACHE_OFFSET0,4,2   ; @mmVCE_VCPU_CACHE_OFFSET0
	.comm	_mmVCE_VCPU_CACHE_SIZE0,4,2     ; @mmVCE_VCPU_CACHE_SIZE0
	.comm	_VCE_V3_0_STACK_SIZE,4,2        ; @VCE_V3_0_STACK_SIZE
	.comm	_mmVCE_VCPU_CACHE_OFFSET1,4,2   ; @mmVCE_VCPU_CACHE_OFFSET1
	.comm	_mmVCE_VCPU_CACHE_SIZE1,4,2     ; @mmVCE_VCPU_CACHE_SIZE1
	.comm	_VCE_V3_0_DATA_SIZE,4,2         ; @VCE_V3_0_DATA_SIZE
	.comm	_mmVCE_VCPU_CACHE_OFFSET2,4,2   ; @mmVCE_VCPU_CACHE_OFFSET2
	.comm	_mmVCE_VCPU_CACHE_SIZE2,4,2     ; @mmVCE_VCPU_CACHE_SIZE2
	.comm	_mmVCE_LMI_CTRL2,4,2            ; @mmVCE_LMI_CTRL2
	.comm	_VCE_SYS_INT_EN,4,2             ; @VCE_SYS_INT_EN
	.comm	_VCE_SYS_INT_TRAP_INTERRUPT_EN,4,2 ; @VCE_SYS_INT_TRAP_INTERRUPT_EN
	.no_dead_strip	_vce_v3_0_mc_resume
.subsections_via_symbols
