	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_vm_frag_ptes
_radeon_vm_frag_ptes:                   ## @radeon_vm_frag_ptes
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, -64(%rbp)                 ## 8-byte Spill
	movq	(%rdi), %rax
	movq	_CHIP_CAYMAN@GOTPCREL(%rip), %rdi
	cmpq	(%rdi), %rax
	sete	%bl
	movq	_CHIP_ARUBA@GOTPCREL(%rip), %rdi
	cmpq	(%rdi), %rax
	movl	%r9d, %r13d
	movl	%r8d, -44(%rbp)                 ## 4-byte Spill
	movl	%ecx, %r15d
	movl	%edx, %r12d
	movq	%rsi, -56(%rbp)                 ## 8-byte Spill
	sete	%al
	orb	%bl, %al
	movq	_R600_PTE_FRAG_64KB@GOTPCREL(%rip), %rax
	cmovneq	_R600_PTE_FRAG_256KB@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$-512, %eax                     ## imm = 0xFE00
	movl	$-128, %r14d
	cmovnel	%eax, %r14d
	movl	$512, %eax                      ## imm = 0x200
	movl	$128, %esi
	cmovnel	%eax, %esi
	movl	%edx, %edi
	callq	_ALIGN
	movq	_R600_PTE_SYSTEM@GOTPCREL(%rip), %rcx
	testl	%r13d, (%rcx)
	je	LBB0_1
LBB0_3:
	subl	%r12d, %r15d
	leal	7(%r15), %r8d
	testl	%r15d, %r15d
	cmovnsl	%r15d, %r8d
	sarl	$3, %r8d
	movq	_RADEON_GPU_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %r9d
	movl	%r13d, (%rsp)
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
	movl	%r12d, %edx
	movl	-44(%rbp), %ecx                 ## 4-byte Reload
LBB0_4:
	callq	_radeon_vm_set_pages
LBB0_5:
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_1:
	movq	_R600_PTE_VALID@GOTPCREL(%rip), %rcx
	testl	%r13d, (%rcx)
	je	LBB0_3
## %bb.2:
	andl	%r15d, %r14d
	movl	%r14d, %esi
	subl	%eax, %esi
	jle	LBB0_3
## %bb.6:
	movl	%eax, %ecx
	subl	%r12d, %ecx
	movq	-56(%rbp), %rdx                 ## 8-byte Reload
	jne	LBB0_8
## %bb.7:
	movq	_RADEON_GPU_PAGE_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r9d
	movl	-44(%rbp), %ecx                 ## 4-byte Reload
	jmp	LBB0_9
LBB0_8:
	leal	7(%rcx), %edx
	testl	%ecx, %ecx
	cmovnsl	%ecx, %edx
	sarl	$3, %edx
	movl	%edx, %r8d
	movl	%edx, -68(%rbp)                 ## 4-byte Spill
	movq	_RADEON_GPU_PAGE_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r9d
	movl	%r13d, (%rsp)
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	movq	%rsi, -80(%rbp)                 ## 8-byte Spill
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
	movl	%r12d, %edx
	movl	%ebx, -72(%rbp)                 ## 4-byte Spill
	movl	-44(%rbp), %ebx                 ## 4-byte Reload
	movl	%ebx, %ecx
	movl	%eax, %r12d
	callq	_radeon_vm_set_pages
	movq	-80(%rbp), %rsi                 ## 8-byte Reload
	movl	%r12d, %eax
	movl	%ebx, %ecx
	movl	-72(%rbp), %ebx                 ## 4-byte Reload
	movq	-56(%rbp), %rdx                 ## 8-byte Reload
	movq	_RADEON_GPU_PAGE_SIZE@GOTPCREL(%rip), %rdi
	movl	(%rdi), %r9d
	movl	-68(%rbp), %edi                 ## 4-byte Reload
	imull	%r9d, %edi
	addl	%edi, %ecx
LBB0_9:
	movl	%ecx, -44(%rbp)                 ## 4-byte Spill
	leal	7(%rsi), %r12d
	testl	%esi, %esi
	cmovnsl	%esi, %r12d
	sarl	$3, %r12d
	orl	%r13d, %ebx
	movl	%ebx, (%rsp)
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	movq	%rdx, %rsi
	movl	%eax, %edx
	movl	%r12d, %r8d
	callq	_radeon_vm_set_pages
	cmpl	%r15d, %r14d
	je	LBB0_5
## %bb.10:
	movq	_RADEON_GPU_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %r9d
	imull	%r9d, %r12d
	addl	-44(%rbp), %r12d                ## 4-byte Folded Reload
	subl	%r14d, %r15d
	leal	7(%r15), %r8d
	testl	%r15d, %r15d
	cmovnsl	%r15d, %r8d
	sarl	$3, %r8d
	movl	%r13d, (%rsp)
	movq	%rbx, %rdi
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
	movl	%r14d, %edx
	movl	%r12d, %ecx
	jmp	LBB0_4
	.cfi_endproc
                                        ## -- End function
	.comm	_CHIP_CAYMAN,8,3                ## @CHIP_CAYMAN
	.comm	_CHIP_ARUBA,8,3                 ## @CHIP_ARUBA
	.comm	_R600_PTE_FRAG_256KB,4,2        ## @R600_PTE_FRAG_256KB
	.comm	_R600_PTE_FRAG_64KB,4,2         ## @R600_PTE_FRAG_64KB
	.comm	_R600_PTE_SYSTEM,4,2            ## @R600_PTE_SYSTEM
	.comm	_R600_PTE_VALID,4,2             ## @R600_PTE_VALID
	.comm	_RADEON_GPU_PAGE_SIZE,4,2       ## @RADEON_GPU_PAGE_SIZE
	.no_dead_strip	_radeon_vm_frag_ptes
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_vm_frag_ptes
_radeon_vm_frag_ptes:                   ; @radeon_vm_frag_ptes
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x5
	mov	x21, x4
	mov	x23, x3
	mov	x25, x2
	mov	x20, x1
	mov	x22, x0
	ldr	x8, [x0]
Lloh0:
	adrp	x9, _CHIP_CAYMAN@GOTPAGE
Lloh1:
	ldr	x9, [x9, _CHIP_CAYMAN@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
Lloh3:
	adrp	x9, _CHIP_ARUBA@GOTPAGE
Lloh4:
	ldr	x9, [x9, _CHIP_ARUBA@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
	ccmp	x8, x9, #4, ne
Lloh6:
	adrp	x8, _R600_PTE_FRAG_256KB@GOTPAGE
Lloh7:
	ldr	x8, [x8, _R600_PTE_FRAG_256KB@GOTPAGEOFF]
Lloh8:
	adrp	x9, _R600_PTE_FRAG_64KB@GOTPAGE
Lloh9:
	ldr	x9, [x9, _R600_PTE_FRAG_64KB@GOTPAGEOFF]
	csel	x8, x8, x9, eq
	ldr	w28, [x8]
	mov	w8, #-128
	mov	w9, #-512
	csel	w24, w9, w8, eq
	mov	w8, #128
	mov	w9, #512
	csel	w1, w9, w8, eq
	mov	x0, x2
	bl	_ALIGN
Lloh10:
	adrp	x8, _R600_PTE_SYSTEM@GOTPAGE
Lloh11:
	ldr	x8, [x8, _R600_PTE_SYSTEM@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	tst	w8, w19
	b.ne	LBB0_2
; %bb.1:
	mov	x26, x0
	and	w24, w24, w23
Lloh13:
	adrp	x8, _R600_PTE_VALID@GOTPAGE
Lloh14:
	ldr	x8, [x8, _R600_PTE_VALID@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
	and	w8, w8, w19
	cmp	w8, #0
	ccmp	w24, w0, #4, ne
	b.gt	LBB0_4
LBB0_2:
	sub	w8, w23, w25
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w4, w8, #3
Lloh16:
	adrp	x8, _RADEON_GPU_PAGE_SIZE@GOTPAGE
Lloh17:
	ldr	x8, [x8, _RADEON_GPU_PAGE_SIZE@GOTPAGEOFF]
Lloh18:
	ldr	w5, [x8]
	mov	x0, x22
	mov	x1, x20
	mov	x2, x25
	mov	x3, x21
LBB0_3:
	mov	x6, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_radeon_vm_set_pages
LBB0_4:
	subs	w8, w26, w25
	b.ne	LBB0_6
; %bb.5:
Lloh19:
	adrp	x8, _RADEON_GPU_PAGE_SIZE@GOTPAGE
Lloh20:
	ldr	x8, [x8, _RADEON_GPU_PAGE_SIZE@GOTPAGEOFF]
Lloh21:
	ldr	w5, [x8]
	b	LBB0_7
LBB0_6:
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w27, w8, #3
Lloh22:
	adrp	x8, _RADEON_GPU_PAGE_SIZE@GOTPAGE
Lloh23:
	ldr	x8, [x8, _RADEON_GPU_PAGE_SIZE@GOTPAGEOFF]
Lloh24:
	ldr	w5, [x8]
	mov	x0, x22
	mov	x1, x20
	mov	x2, x25
	mov	x3, x21
	mov	x4, x27
	mov	x6, x19
	bl	_radeon_vm_set_pages
Lloh25:
	adrp	x8, _RADEON_GPU_PAGE_SIZE@GOTPAGE
Lloh26:
	ldr	x8, [x8, _RADEON_GPU_PAGE_SIZE@GOTPAGEOFF]
Lloh27:
	ldr	w5, [x8]
	madd	w21, w5, w27, w21
LBB0_7:
	sub	w8, w24, w26
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w25, w8, #3
	orr	w6, w28, w19
	mov	x0, x22
	mov	x1, x20
	mov	x2, x26
	mov	x3, x21
	mov	x4, x25
	bl	_radeon_vm_set_pages
	cmp	w24, w23
	b.ne	LBB0_9
; %bb.8:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
LBB0_9:
Lloh28:
	adrp	x8, _RADEON_GPU_PAGE_SIZE@GOTPAGE
Lloh29:
	ldr	x8, [x8, _RADEON_GPU_PAGE_SIZE@GOTPAGEOFF]
Lloh30:
	ldr	w5, [x8]
	madd	w3, w5, w25, w21
	sub	w8, w23, w24
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w4, w8, #3
	mov	x0, x22
	mov	x1, x20
	mov	x2, x24
	b	LBB0_3
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.cfi_endproc
                                        ; -- End function
	.comm	_CHIP_CAYMAN,8,3                ; @CHIP_CAYMAN
	.comm	_CHIP_ARUBA,8,3                 ; @CHIP_ARUBA
	.comm	_R600_PTE_FRAG_256KB,4,2        ; @R600_PTE_FRAG_256KB
	.comm	_R600_PTE_FRAG_64KB,4,2         ; @R600_PTE_FRAG_64KB
	.comm	_R600_PTE_SYSTEM,4,2            ; @R600_PTE_SYSTEM
	.comm	_R600_PTE_VALID,4,2             ; @R600_PTE_VALID
	.comm	_RADEON_GPU_PAGE_SIZE,4,2       ; @RADEON_GPU_PAGE_SIZE
	.no_dead_strip	_radeon_vm_frag_ptes
.subsections_via_symbols
