	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function altera_cvp_state
_altera_cvp_state:                      ## @altera_cvp_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	subq	$16, %rsp
	movq	(%rdi), %rdi
	movq	_VSE_CVP_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-4(%rbp), %rdx
	callq	_altera_read_config_dword
	movl	-4(%rbp), %ecx
	movq	_VSE_CVP_STATUS_CFG_DONE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%ecx, %eax
	movq	_VSE_CVP_STATUS_CVP_EN@GOTPCREL(%rip), %rdx
	andl	(%rdx), %ecx
	jne	LBB0_1
## %bb.2:
	movq	_FPGA_MGR_STATE_UNKNOWN@GOTPCREL(%rip), %rcx
	testl	%eax, %eax
	jne	LBB0_4
	jmp	LBB0_5
LBB0_1:
	movq	_FPGA_MGR_STATE_POWER_UP@GOTPCREL(%rip), %rcx
	testl	%eax, %eax
	je	LBB0_5
LBB0_4:
	movq	_FPGA_MGR_STATE_OPERATING@GOTPCREL(%rip), %rcx
LBB0_5:
	movl	(%rcx), %eax
	addq	$16, %rsp
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_VSE_CVP_STATUS,4,2             ## @VSE_CVP_STATUS
	.comm	_VSE_CVP_STATUS_CFG_DONE,4,2    ## @VSE_CVP_STATUS_CFG_DONE
	.comm	_FPGA_MGR_STATE_OPERATING,4,2   ## @FPGA_MGR_STATE_OPERATING
	.comm	_VSE_CVP_STATUS_CVP_EN,4,2      ## @VSE_CVP_STATUS_CVP_EN
	.comm	_FPGA_MGR_STATE_POWER_UP,4,2    ## @FPGA_MGR_STATE_POWER_UP
	.comm	_FPGA_MGR_STATE_UNKNOWN,4,2     ## @FPGA_MGR_STATE_UNKNOWN
	.no_dead_strip	_altera_cvp_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function altera_cvp_state
_altera_cvp_state:                      ; @altera_cvp_state
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #32
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	ldr	x0, [x0]
Lloh0:
	adrp	x8, _VSE_CVP_STATUS@GOTPAGE
Lloh1:
	ldr	x8, [x8, _VSE_CVP_STATUS@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	sub	x2, x29, #4
	bl	_altera_read_config_dword
	ldur	w8, [x29, #-4]
Lloh3:
	adrp	x9, _VSE_CVP_STATUS_CFG_DONE@GOTPAGE
Lloh4:
	ldr	x9, [x9, _VSE_CVP_STATUS_CFG_DONE@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
Lloh6:
	adrp	x10, _VSE_CVP_STATUS_CVP_EN@GOTPAGE
Lloh7:
	ldr	x10, [x10, _VSE_CVP_STATUS_CVP_EN@GOTPAGEOFF]
Lloh8:
	ldr	w10, [x10]
Lloh9:
	adrp	x11, _FPGA_MGR_STATE_UNKNOWN@GOTPAGE
Lloh10:
	ldr	x11, [x11, _FPGA_MGR_STATE_UNKNOWN@GOTPAGEOFF]
Lloh11:
	adrp	x12, _FPGA_MGR_STATE_POWER_UP@GOTPAGE
Lloh12:
	ldr	x12, [x12, _FPGA_MGR_STATE_POWER_UP@GOTPAGEOFF]
	tst	w10, w8
	csel	x10, x11, x12, eq
Lloh13:
	adrp	x11, _FPGA_MGR_STATE_OPERATING@GOTPAGE
Lloh14:
	ldr	x11, [x11, _FPGA_MGR_STATE_OPERATING@GOTPAGEOFF]
	tst	w9, w8
	csel	x8, x10, x11, eq
	ldr	w0, [x8]
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #32
	ret
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_VSE_CVP_STATUS,4,2             ; @VSE_CVP_STATUS
	.comm	_VSE_CVP_STATUS_CFG_DONE,4,2    ; @VSE_CVP_STATUS_CFG_DONE
	.comm	_FPGA_MGR_STATE_OPERATING,4,2   ; @FPGA_MGR_STATE_OPERATING
	.comm	_VSE_CVP_STATUS_CVP_EN,4,2      ; @VSE_CVP_STATUS_CVP_EN
	.comm	_FPGA_MGR_STATE_POWER_UP,4,2    ; @FPGA_MGR_STATE_POWER_UP
	.comm	_FPGA_MGR_STATE_UNKNOWN,4,2     ; @FPGA_MGR_STATE_UNKNOWN
	.no_dead_strip	_altera_cvp_state
.subsections_via_symbols
