	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function haswell_crtc_enable
_haswell_crtc_enable:                   ## @haswell_crtc_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, -56(%rbp)                 ## 8-byte Spill
	movq	%rdi, %rbx
	movq	48(%rdi), %r14
	movl	(%r14), %edi
	callq	_to_i915
	movq	%rax, -64(%rbp)                 ## 8-byte Spill
	movq	%r14, %rdi
	callq	_to_intel_crtc
	movq	%rax, %r13
	movl	(%rax), %r12d
	movl	4(%rax), %edi
	movl	(%rbx), %r15d
	callq	_WARN_ON
	testq	%rax, %rax
	je	LBB0_2
LBB0_1:
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	movq	%r14, -72(%rbp)                 ## 8-byte Spill
	movl	%r12d, -48(%rbp)                ## 4-byte Spill
	movq	%r13, %r14
	movq	%r13, %rdi
	movq	%rbx, %rsi
	movq	-56(%rbp), %r12                 ## 8-byte Reload
	movq	%r12, %rdx
	callq	_intel_encoders_pre_pll_enable
	cmpq	$0, 40(%rbx)
	je	LBB0_4
## %bb.3:
	movq	%rbx, %rdi
	callq	_intel_enable_shared_dpll
LBB0_4:
	movq	%r14, %rdi
	movq	%rbx, %rsi
	movq	%r12, %rdx
	callq	_intel_encoders_pre_enable
	movq	%rbx, %rdi
	callq	_intel_crtc_has_dp_encoder
	testq	%rax, %rax
	movq	-64(%rbp), %r13                 ## 8-byte Reload
	je	LBB0_6
## %bb.5:
	movq	_M1_N1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_intel_dp_set_m_n
LBB0_6:
	movl	%r15d, %edi
	callq	_transcoder_is_dsi
	testl	%eax, %eax
	jne	LBB0_8
## %bb.7:
	movq	%rbx, %rdi
	callq	_intel_set_pipe_timings
LBB0_8:
	movq	%rbx, %rdi
	callq	_intel_set_pipe_src_size
	movq	_TRANSCODER_EDP@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r15d
	je	LBB0_11
## %bb.9:
	movl	%r15d, %edi
	callq	_transcoder_is_dsi
	testl	%eax, %eax
	jne	LBB0_11
## %bb.10:
	movl	%r15d, %edi
	callq	_PIPE_MULT
	movq	32(%rbx), %rsi
	decq	%rsi
	movl	%eax, %edi
	callq	_I915_WRITE
LBB0_11:
	cmpq	$0, 8(%rbx)
	je	LBB0_13
## %bb.12:
	leaq	24(%rbx), %rsi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_intel_cpu_transcoder_set_m_n
LBB0_13:
	movl	%r15d, %edi
	callq	_transcoder_is_dsi
	testl	%eax, %eax
	jne	LBB0_15
## %bb.14:
	movq	%rbx, %rdi
	callq	_haswell_set_pipeconf
LBB0_15:
	movq	%r13, %rdi
	callq	_INTEL_GEN
	cmpl	$8, %eax
	jg	LBB0_17
## %bb.16:
	movq	%r13, %rdi
	callq	_IS_BROADWELL
	testq	%rax, %rax
	je	LBB0_18
LBB0_17:
	movq	%rbx, %rdi
	callq	_bdw_set_pipemisc
LBB0_18:
	movl	$1, 4(%r14)
	movq	%r13, %rdi
	callq	_IS_GEMINILAKE
	testq	%rax, %rax
	jne	LBB0_20
## %bb.19:
	movq	%r13, %rdi
	callq	_IS_CANNONLAKE
	testq	%rax, %rax
	je	LBB0_23
LBB0_20:
	cmpq	$0, 16(%rbx)
	je	LBB0_23
## %bb.21:
	movq	%r13, %rdi
	movl	-48(%rbp), %esi                 ## 4-byte Reload
	movl	$1, %edx
	callq	_glk_pipe_scaler_clock_gating_wa
	movb	$1, %al
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	jmp	LBB0_24
LBB0_23:
	movl	$0, -44(%rbp)                   ## 4-byte Folded Spill
LBB0_24:
	movq	%r13, %rdi
	callq	_INTEL_GEN
	movq	%rbx, %rdi
	cmpl	$9, %eax
	jl	LBB0_26
## %bb.25:
	callq	_skylake_pfit_enable
	jmp	LBB0_27
LBB0_26:
	callq	_ironlake_pfit_enable
LBB0_27:
	movq	%rbx, %rdi
	callq	_intel_color_load_luts
	movq	%rbx, %rdi
	callq	_intel_color_commit
	movq	%r13, %rdi
	callq	_INTEL_GEN
	cmpl	$8, %eax
	jg	LBB0_29
## %bb.28:
	movq	%rbx, %rdi
	callq	_intel_disable_primary_plane
LBB0_29:
	movq	%r13, %rdi
	callq	_INTEL_GEN
	cmpl	$11, %eax
	jl	LBB0_31
## %bb.30:
	movq	%r14, %rdi
	callq	_icl_set_pipe_chicken
LBB0_31:
	movq	%rbx, %rdi
	callq	_intel_ddi_set_pipe_settings
	movl	%r15d, %edi
	callq	_transcoder_is_dsi
	testl	%eax, %eax
	jne	LBB0_33
## %bb.32:
	movq	%rbx, %rdi
	callq	_intel_ddi_enable_transcoder_func
LBB0_33:
	movq	(%r13), %rax
	testq	%rax, %rax
	je	LBB0_35
## %bb.34:
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	movq	%rbx, %rsi
	callq	*%rax
LBB0_35:
	movq	%r13, %rdi
	callq	_INTEL_GEN
	cmpl	$11, %eax
	jl	LBB0_37
## %bb.36:
	movq	%r14, %rdi
	callq	_icl_pipe_mbus_enable
LBB0_37:
	movl	%r15d, %edi
	callq	_transcoder_is_dsi
	testl	%eax, %eax
	jne	LBB0_39
## %bb.38:
	movq	%rbx, %rdi
	callq	_intel_enable_pipe
LBB0_39:
	cmpq	$0, 8(%rbx)
	movl	-48(%rbp), %r12d                ## 4-byte Reload
	je	LBB0_41
## %bb.40:
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	movq	%rbx, %rsi
	callq	_lpt_pch_enable
LBB0_41:
	movq	_INTEL_OUTPUT_DP_MST@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_intel_crtc_has_type
	testq	%rax, %rax
	je	LBB0_43
## %bb.42:
	movq	%rbx, %rdi
	movl	$1, %esi
	callq	_intel_ddi_set_vc_payload_alloc
LBB0_43:
	movq	-72(%rbp), %rdi                 ## 8-byte Reload
	callq	_assert_vblank_disabled
	movq	%rbx, %rdi
	callq	_intel_crtc_vblank_on
	movq	%r14, %rdi
	movq	%rbx, %rsi
	movq	-56(%rbp), %rdx                 ## 8-byte Reload
	callq	_intel_encoders_enable
	cmpb	$0, -44(%rbp)                   ## 1-byte Folded Reload
	je	LBB0_45
## %bb.44:
	movq	%r13, %rdi
	movl	%r12d, %esi
	callq	_intel_wait_for_vblank
	movq	%r13, %rdi
	movl	%r12d, %esi
	xorl	%edx, %edx
	callq	_glk_pipe_scaler_clock_gating_wa
LBB0_45:
	movl	4(%rbx), %ebx
	movq	%r13, %rdi
	callq	_IS_HASWELL
	testq	%rax, %rax
	je	LBB0_1
## %bb.46:
	movq	_INVALID_PIPE@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	je	LBB0_1
## %bb.47:
	movq	-64(%rbp), %r14                 ## 8-byte Reload
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_intel_wait_for_vblank
	movq	%r14, %rdi
	movl	%ebx, %esi
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_intel_wait_for_vblank          ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_M1_N1,4,2                      ## @M1_N1
	.comm	_TRANSCODER_EDP,4,2             ## @TRANSCODER_EDP
	.comm	_INTEL_OUTPUT_DP_MST,4,2        ## @INTEL_OUTPUT_DP_MST
	.comm	_INVALID_PIPE,4,2               ## @INVALID_PIPE
	.no_dead_strip	_haswell_crtc_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function haswell_crtc_enable
_haswell_crtc_enable:                   ; @haswell_crtc_enable
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x21, x1
	mov	x20, x0
	ldr	x23, [x0, #48]
	ldr	w0, [x23]
	bl	_to_i915
	mov	x19, x0
	mov	x0, x23
	bl	_to_intel_crtc
	mov	x24, x0
	ldr	w25, [x20]
	ldp	w22, w0, [x0]
	bl	_WARN_ON
	cbz	x0, LBB0_2
LBB0_1:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_2:
	mov	x0, x24
	mov	x1, x20
	mov	x2, x21
	bl	_intel_encoders_pre_pll_enable
	ldr	x8, [x20, #40]
	cbz	x8, LBB0_4
; %bb.3:
	mov	x0, x20
	bl	_intel_enable_shared_dpll
LBB0_4:
	mov	x0, x24
	mov	x1, x20
	mov	x2, x21
	bl	_intel_encoders_pre_enable
	mov	x0, x20
	bl	_intel_crtc_has_dp_encoder
	cbz	x0, LBB0_6
; %bb.5:
Lloh0:
	adrp	x8, _M1_N1@GOTPAGE
Lloh1:
	ldr	x8, [x8, _M1_N1@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_intel_dp_set_m_n
LBB0_6:
	mov	x0, x25
	bl	_transcoder_is_dsi
	cbnz	w0, LBB0_8
; %bb.7:
	mov	x0, x20
	bl	_intel_set_pipe_timings
LBB0_8:
	mov	x0, x20
	bl	_intel_set_pipe_src_size
Lloh3:
	adrp	x8, _TRANSCODER_EDP@GOTPAGE
Lloh4:
	ldr	x8, [x8, _TRANSCODER_EDP@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	cmp	w25, w8
	b.eq	LBB0_11
; %bb.9:
	mov	x0, x25
	bl	_transcoder_is_dsi
	cbnz	w0, LBB0_11
; %bb.10:
	mov	x0, x25
	bl	_PIPE_MULT
	ldr	x8, [x20, #32]
	sub	x1, x8, #1
	bl	_I915_WRITE
LBB0_11:
	ldr	x8, [x20, #8]
	cbz	x8, LBB0_13
; %bb.12:
	add	x1, x20, #24
	mov	x0, x20
	mov	x2, #0
	bl	_intel_cpu_transcoder_set_m_n
LBB0_13:
	mov	x0, x25
	bl	_transcoder_is_dsi
	cbnz	w0, LBB0_15
; %bb.14:
	mov	x0, x20
	bl	_haswell_set_pipeconf
LBB0_15:
	mov	x0, x19
	bl	_INTEL_GEN
	cmp	w0, #8
	b.gt	LBB0_17
; %bb.16:
	mov	x0, x19
	bl	_IS_BROADWELL
	cbz	x0, LBB0_18
LBB0_17:
	mov	x0, x20
	bl	_bdw_set_pipemisc
LBB0_18:
	mov	w8, #1
	str	w8, [x24, #4]
	mov	x0, x19
	bl	_IS_GEMINILAKE
	cbnz	x0, LBB0_20
; %bb.19:
	mov	x0, x19
	bl	_IS_CANNONLAKE
	cbz	x0, LBB0_22
LBB0_20:
	ldr	x8, [x20, #16]
	cbz	x8, LBB0_22
; %bb.21:
	mov	w26, #1
	mov	x0, x19
	mov	x1, x22
	mov	w2, #1
	bl	_glk_pipe_scaler_clock_gating_wa
	b	LBB0_23
LBB0_22:
	mov	w26, #0
LBB0_23:
	mov	x0, x19
	bl	_INTEL_GEN
	cmp	w0, #9
	b.lt	LBB0_25
; %bb.24:
	mov	x0, x20
	bl	_skylake_pfit_enable
	b	LBB0_26
LBB0_25:
	mov	x0, x20
	bl	_ironlake_pfit_enable
LBB0_26:
	mov	x0, x20
	bl	_intel_color_load_luts
	mov	x0, x20
	bl	_intel_color_commit
	mov	x0, x19
	bl	_INTEL_GEN
	cmp	w0, #8
	b.gt	LBB0_28
; %bb.27:
	mov	x0, x20
	bl	_intel_disable_primary_plane
LBB0_28:
	mov	x0, x19
	bl	_INTEL_GEN
	cmp	w0, #11
	b.lt	LBB0_30
; %bb.29:
	mov	x0, x24
	bl	_icl_set_pipe_chicken
LBB0_30:
	mov	x0, x20
	bl	_intel_ddi_set_pipe_settings
	mov	x0, x25
	bl	_transcoder_is_dsi
	cbnz	w0, LBB0_32
; %bb.31:
	mov	x0, x20
	bl	_intel_ddi_enable_transcoder_func
LBB0_32:
	ldr	x8, [x19]
	cbz	x8, LBB0_34
; %bb.33:
	mov	x0, x21
	mov	x1, x20
	blr	x8
LBB0_34:
	mov	x0, x19
	bl	_INTEL_GEN
	cmp	w0, #11
	b.lt	LBB0_36
; %bb.35:
	mov	x0, x24
	bl	_icl_pipe_mbus_enable
LBB0_36:
	mov	x0, x25
	bl	_transcoder_is_dsi
	cbnz	w0, LBB0_38
; %bb.37:
	mov	x0, x20
	bl	_intel_enable_pipe
LBB0_38:
	ldr	x8, [x20, #8]
	cbz	x8, LBB0_40
; %bb.39:
	mov	x0, x21
	mov	x1, x20
	bl	_lpt_pch_enable
LBB0_40:
Lloh6:
	adrp	x8, _INTEL_OUTPUT_DP_MST@GOTPAGE
Lloh7:
	ldr	x8, [x8, _INTEL_OUTPUT_DP_MST@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_intel_crtc_has_type
	cbz	x0, LBB0_42
; %bb.41:
	mov	x0, x20
	mov	w1, #1
	bl	_intel_ddi_set_vc_payload_alloc
LBB0_42:
	mov	x0, x23
	bl	_assert_vblank_disabled
	mov	x0, x20
	bl	_intel_crtc_vblank_on
	mov	x0, x24
	mov	x1, x20
	mov	x2, x21
	bl	_intel_encoders_enable
	cbz	w26, LBB0_44
; %bb.43:
	mov	x0, x19
	mov	x1, x22
	bl	_intel_wait_for_vblank
	mov	x0, x19
	mov	x1, x22
	mov	w2, #0
	bl	_glk_pipe_scaler_clock_gating_wa
LBB0_44:
	ldr	w20, [x20, #4]
	mov	x0, x19
	bl	_IS_HASWELL
	cbz	x0, LBB0_1
; %bb.45:
Lloh9:
	adrp	x8, _INVALID_PIPE@GOTPAGE
Lloh10:
	ldr	x8, [x8, _INVALID_PIPE@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	cmp	w20, w8
	b.eq	LBB0_1
; %bb.46:
	mov	x0, x19
	mov	x1, x20
	bl	_intel_wait_for_vblank
	mov	x0, x19
	mov	x1, x20
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_intel_wait_for_vblank
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.cfi_endproc
                                        ; -- End function
	.comm	_M1_N1,4,2                      ; @M1_N1
	.comm	_TRANSCODER_EDP,4,2             ; @TRANSCODER_EDP
	.comm	_INTEL_OUTPUT_DP_MST,4,2        ; @INTEL_OUTPUT_DP_MST
	.comm	_INVALID_PIPE,4,2               ; @INVALID_PIPE
	.no_dead_strip	_haswell_crtc_enable
.subsections_via_symbols
