	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v2_5_sw_init
_vcn_v2_5_sw_init:                      ## @vcn_v2_5_sw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movl	(%rdi), %eax
	testl	%eax, %eax
	jle	LBB0_11
## %bb.1:
	xorl	%ebx, %ebx
	movq	_amdgpu_ih_clientid_vcns@GOTPCREL(%rip), %r12
	jmp	LBB0_2
	.p2align	4, 0x90
LBB0_10:                                ##   in Loop: Header=BB0_2 Depth=1
	incq	%rbx
	movslq	%eax, %rcx
	cmpq	%rcx, %rbx
	jge	LBB0_11
LBB0_2:                                 ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_7 Depth 2
	movl	4(%r14), %ecx
	btl	%ebx, %ecx
	jb	LBB0_10
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	(%r12), %rax
	movl	(%rax,%rbx,4), %esi
	movq	_VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	imulq	$88, %rbx, %r15
	movq	16(%r14), %rcx
	addq	%r15, %rcx
	movq	%r14, %rdi
	callq	_amdgpu_irq_add_id
	testl	%eax, %eax
	jne	LBB0_29
## %bb.4:                               ##   in Loop: Header=BB0_2 Depth=1
	cmpl	$0, 8(%r14)
	jle	LBB0_8
## %bb.5:                               ##   in Loop: Header=BB0_2 Depth=1
	xorl	%r13d, %r13d
	.p2align	4, 0x90
LBB0_7:                                 ##   Parent Loop BB0_2 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movq	(%r12), %rax
	movl	(%rax,%rbx,4), %esi
	movq	_VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	addq	%r13, %rdx
	movq	16(%r14), %rcx
	addq	%r15, %rcx
	movq	%r14, %rdi
	callq	_amdgpu_irq_add_id
	testl	%eax, %eax
	jne	LBB0_29
## %bb.6:                               ##   in Loop: Header=BB0_7 Depth=2
	incq	%r13
	movslq	8(%r14), %rax
	cmpq	%rax, %r13
	jl	LBB0_7
LBB0_8:                                 ##   in Loop: Header=BB0_2 Depth=1
	movq	(%r12), %rax
	movl	(%rax,%rbx,4), %esi
	movq	_VCN_2_0__SRCID__JPEG_DECODE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	addq	16(%r14), %r15
	movq	%r14, %rdi
	movq	%r15, %rcx
	callq	_amdgpu_irq_add_id
	testl	%eax, %eax
	jne	LBB0_29
## %bb.9:                               ##   in Loop: Header=BB0_2 Depth=1
	movl	(%r14), %eax
	jmp	LBB0_10
LBB0_11:
	movq	%r14, %rdi
	callq	_amdgpu_vcn_sw_init
	testl	%eax, %eax
	jne	LBB0_29
## %bb.12:
	movq	88(%r14), %rax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_16
## %bb.13:
	movq	72(%r14), %rax
	movq	104(%r14), %rcx
	movq	(%rax), %rbx
	movq	_AMDGPU_UCODE_ID_VCN@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rsi
	movq	%rsi, %rdi
	shlq	$4, %rdi
	movq	%rsi, (%rcx,%rdi)
	movq	(%rdx), %rdx
	shlq	$4, %rdx
	movq	%rax, 8(%rcx,%rdx)
	movl	(%rbx), %edi
	callq	_le32_to_cpu
	movq	_PAGE_SIZE@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_ALIGN
	addl	%eax, 96(%r14)
	movl	(%r14), %eax
	movq	_VCN25_MAX_HW_INSTANCES_ARCTURUS@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_15
## %bb.14:
	movq	_AMDGPU_UCODE_ID_VCN1@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	104(%r14), %rdx
	movq	%rcx, %rsi
	shlq	$4, %rsi
	movq	%rcx, (%rdx,%rsi)
	movq	72(%r14), %rcx
	movq	(%rax), %rax
	shlq	$4, %rax
	movq	%rcx, 8(%rdx,%rax)
	movl	(%rbx), %edi
	callq	_le32_to_cpu
	movl	(%r15), %esi
	movl	%eax, %edi
	callq	_ALIGN
	addl	%eax, 96(%r14)
LBB0_15:
	leaq	L_.str(%rip), %rdi
	callq	_DRM_INFO
LBB0_16:
	movq	%r14, %rdi
	callq	_amdgpu_vcn_resume
	testl	%eax, %eax
	je	LBB0_17
LBB0_29:
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_17:
	movl	(%r14), %ecx
	testl	%ecx, %ecx
	jle	LBB0_18
## %bb.19:
	xorl	%r15d, %r15d
	xorl	%r13d, %r13d
	jmp	LBB0_20
	.p2align	4, 0x90
LBB0_28:                                ##   in Loop: Header=BB0_20 Depth=1
	incq	%r13
	movslq	%ecx, %rdx
	addl	$8, %r15d
	xorl	%eax, %eax
	cmpq	%rdx, %r13
	jge	LBB0_29
LBB0_20:                                ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_25 Depth 2
	movl	4(%r14), %eax
	btl	%r13d, %eax
	jb	LBB0_28
## %bb.21:                              ##   in Loop: Header=BB0_20 Depth=1
	movq	_mmUVD_CONTEXT_ID_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 68(%r14)
	movq	_mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 64(%r14)
	movq	_mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 60(%r14)
	movq	_mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 56(%r14)
	movq	_mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 52(%r14)
	movq	_mmUVD_GP_SCRATCH8_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 48(%r14)
	movq	_mmUVD_SCRATCH9_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 44(%r14)
	movq	_UVD@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_mmUVD_SCRATCH9@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r13d, %esi
	callq	_SOC15_REG_OFFSET
	movq	16(%r14), %rcx
	imulq	$88, %r13, %r12
	movq	%rax, 80(%rcx,%r12)
	movq	_mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 40(%r14)
	movl	(%rbx), %edi
	movq	_mmUVD_GPCOM_VCPU_DATA0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r13d, %esi
	callq	_SOC15_REG_OFFSET
	movq	16(%r14), %rcx
	movq	%rax, 72(%rcx,%r12)
	movq	_mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 36(%r14)
	movl	(%rbx), %edi
	movq	_mmUVD_GPCOM_VCPU_DATA1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r13d, %esi
	callq	_SOC15_REG_OFFSET
	movq	16(%r14), %rcx
	movq	%rax, 64(%rcx,%r12)
	movq	_mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 32(%r14)
	movl	(%rbx), %edi
	movq	_mmUVD_GPCOM_VCPU_CMD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r13d, %esi
	callq	_SOC15_REG_OFFSET
	movq	16(%r14), %rcx
	movq	%rax, 56(%rcx,%r12)
	movq	_mmUVD_NO_OP_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 28(%r14)
	movl	(%rbx), %edi
	movq	_mmUVD_NO_OP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r13d, %esi
	callq	_SOC15_REG_OFFSET
	movq	16(%r14), %rcx
	movq	%rax, 48(%rcx,%r12)
	movq	_mmUVD_JPEG_PITCH_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 24(%r14)
	movl	(%rbx), %edi
	movq	_mmUVD_JPEG_PITCH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r13d, %esi
	callq	_SOC15_REG_OFFSET
	movq	16(%r14), %rcx
	movq	%rax, 40(%rcx,%r12)
	leaq	(%rcx,%r12), %rbx
	addq	$24, %rbx
	movl	$1, 24(%rcx,%r12)
	movl	80(%r14), %eax
	leal	(,%r13,8), %edx
	movq	%rdx, -64(%rbp)                 ## 8-byte Spill
	leal	(%rdx,%rax,2), %eax
	movl	%eax, 28(%rcx,%r12)
	movl	32(%rcx,%r12), %edi
	leaq	L_.str.1(%rip), %rsi
	movl	%r13d, %edx
	xorl	%eax, %eax
	callq	_sprintf
	movq	16(%r14), %rcx
	addq	%r12, %rcx
	movq	%r14, %rdi
	movq	%rbx, %rsi
	movl	$512, %edx                      ## imm = 0x200
	xorl	%r8d, %r8d
	callq	_amdgpu_ring_init
	testl	%eax, %eax
	jne	LBB0_29
## %bb.22:                              ##   in Loop: Header=BB0_20 Depth=1
	movq	%r13, -56(%rbp)                 ## 8-byte Spill
	movl	%r15d, -44(%rbp)                ## 4-byte Spill
	cmpl	$0, 8(%r14)
	jle	LBB0_26
## %bb.23:                              ##   in Loop: Header=BB0_20 Depth=1
	movl	-44(%rbp), %eax                 ## 4-byte Reload
	addq	$2, %rax
	movq	%rax, -72(%rbp)                 ## 8-byte Spill
	xorl	%r13d, %r13d
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_25:                                ##   Parent Loop BB0_20 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movq	16(%r14), %rax
	movq	16(%rax,%r12), %rax
	leaq	(%rax,%r13), %r15
	movl	$1, (%rax,%r13)
	movl	80(%r14), %ecx
	movq	-72(%rbp), %rdx                 ## 8-byte Reload
	addl	%ebx, %edx
	leal	(%rdx,%rcx,2), %ecx
	movl	%ecx, 4(%rax,%r13)
	movl	8(%rax,%r13), %edi
	leaq	L_.str.2(%rip), %rsi
	movq	-56(%rbp), %rdx                 ## 8-byte Reload
                                        ## kill: def $edx killed $edx killed $rdx
	movl	%ebx, %ecx
	xorl	%eax, %eax
	callq	_sprintf
	movq	16(%r14), %rcx
	addq	%r12, %rcx
	movq	%r14, %rdi
	movq	%r15, %rsi
	movl	$512, %edx                      ## imm = 0x200
	xorl	%r8d, %r8d
	callq	_amdgpu_ring_init
	testl	%eax, %eax
	jne	LBB0_29
## %bb.24:                              ##   in Loop: Header=BB0_25 Depth=2
	incq	%rbx
	movslq	8(%r14), %rax
	addq	$12, %r13
	cmpq	%rax, %rbx
	jl	LBB0_25
LBB0_26:                                ##   in Loop: Header=BB0_20 Depth=1
	movq	16(%r14), %rax
	leaq	(%rax,%r12), %rbx
	addq	$4, %rbx
	movl	$1, 4(%rax,%r12)
	movl	80(%r14), %ecx
	movq	-64(%rbp), %rdx                 ## 8-byte Reload
	orl	$1, %edx
	leal	(%rdx,%rcx,2), %ecx
	movl	%ecx, 8(%rax,%r12)
	movl	12(%rax,%r12), %edi
	leaq	L_.str.3(%rip), %rsi
	movq	-56(%rbp), %r13                 ## 8-byte Reload
	movl	%r13d, %edx
	xorl	%eax, %eax
	callq	_sprintf
	addq	16(%r14), %r12
	movq	%r14, %rdi
	movq	%rbx, %rsi
	movl	$512, %edx                      ## imm = 0x200
	movq	%r12, %rcx
	xorl	%r8d, %r8d
	callq	_amdgpu_ring_init
	testl	%eax, %eax
	jne	LBB0_29
## %bb.27:                              ##   in Loop: Header=BB0_20 Depth=1
	movl	(%r14), %ecx
	movl	-44(%rbp), %r15d                ## 4-byte Reload
	jmp	LBB0_28
LBB0_18:
	xorl	%eax, %eax
	jmp	LBB0_29
	.cfi_endproc
                                        ## -- End function
	.comm	_amdgpu_ih_clientid_vcns,8,3    ## @amdgpu_ih_clientid_vcns
	.comm	_VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,8,3 ## @VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT
	.comm	_VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE,8,3 ## @VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE
	.comm	_VCN_2_0__SRCID__JPEG_DECODE,8,3 ## @VCN_2_0__SRCID__JPEG_DECODE
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_VCN,8,3        ## @AMDGPU_UCODE_ID_VCN
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
	.comm	_VCN25_MAX_HW_INSTANCES_ARCTURUS,4,2 ## @VCN25_MAX_HW_INSTANCES_ARCTURUS
	.comm	_AMDGPU_UCODE_ID_VCN1,8,3       ## @AMDGPU_UCODE_ID_VCN1
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"PSP loading VCN firmware\n"

	.comm	_mmUVD_CONTEXT_ID_INTERNAL_OFFSET,4,2 ## @mmUVD_CONTEXT_ID_INTERNAL_OFFSET
	.comm	_mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET,4,2 ## @mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET
	.comm	_mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,4,2 ## @mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET
	.comm	_mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,4,2 ## @mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET
	.comm	_mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET,4,2 ## @mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET
	.comm	_mmUVD_GP_SCRATCH8_INTERNAL_OFFSET,4,2 ## @mmUVD_GP_SCRATCH8_INTERNAL_OFFSET
	.comm	_mmUVD_SCRATCH9_INTERNAL_OFFSET,4,2 ## @mmUVD_SCRATCH9_INTERNAL_OFFSET
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_SCRATCH9,4,2             ## @mmUVD_SCRATCH9
	.comm	_mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET,4,2 ## @mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET
	.comm	_mmUVD_GPCOM_VCPU_DATA0,4,2     ## @mmUVD_GPCOM_VCPU_DATA0
	.comm	_mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET,4,2 ## @mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET
	.comm	_mmUVD_GPCOM_VCPU_DATA1,4,2     ## @mmUVD_GPCOM_VCPU_DATA1
	.comm	_mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET,4,2 ## @mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET
	.comm	_mmUVD_GPCOM_VCPU_CMD,4,2       ## @mmUVD_GPCOM_VCPU_CMD
	.comm	_mmUVD_NO_OP_INTERNAL_OFFSET,4,2 ## @mmUVD_NO_OP_INTERNAL_OFFSET
	.comm	_mmUVD_NO_OP,4,2                ## @mmUVD_NO_OP
	.comm	_mmUVD_JPEG_PITCH_INTERNAL_OFFSET,4,2 ## @mmUVD_JPEG_PITCH_INTERNAL_OFFSET
	.comm	_mmUVD_JPEG_PITCH,4,2           ## @mmUVD_JPEG_PITCH
L_.str.1:                               ## @.str.1
	.asciz	"vcn_dec_%d"

L_.str.2:                               ## @.str.2
	.asciz	"vcn_enc_%d.%d"

L_.str.3:                               ## @.str.3
	.asciz	"vcn_jpeg_%d"

	.no_dead_strip	_vcn_v2_5_sw_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v2_5_sw_init
_vcn_v2_5_sw_init:                      ; @vcn_v2_5_sw_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	w8, [x0]
	cmp	w8, #1
	b.lt	LBB0_11
; %bb.1:
	mov	x20, #0
Lloh0:
	adrp	x21, _amdgpu_ih_clientid_vcns@GOTPAGE
Lloh1:
	ldr	x21, [x21, _amdgpu_ih_clientid_vcns@GOTPAGEOFF]
Lloh2:
	adrp	x22, _VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT@GOTPAGE
Lloh3:
	ldr	x22, [x22, _VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT@GOTPAGEOFF]
	mov	w23, #88
Lloh4:
	adrp	x24, _VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE@GOTPAGE
Lloh5:
	ldr	x24, [x24, _VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE@GOTPAGEOFF]
Lloh6:
	adrp	x25, _VCN_2_0__SRCID__JPEG_DECODE@GOTPAGE
Lloh7:
	ldr	x25, [x25, _VCN_2_0__SRCID__JPEG_DECODE@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:                                 ;   in Loop: Header=BB0_3 Depth=1
	add	x20, x20, #1
	cmp	x20, w8, sxtw
	b.ge	LBB0_11
LBB0_3:                                 ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
	ldr	w9, [x19, #4]
	lsr	w9, w9, w20
	tbnz	w9, #0, LBB0_2
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	ldr	x8, [x21]
	ldr	w1, [x8, x20, lsl #2]
	ldr	x2, [x22]
	ldr	x8, [x19, #16]
	madd	x3, x20, x23, x8
	mov	x0, x19
	bl	_amdgpu_irq_add_id
	cbnz	w0, LBB0_17
; %bb.5:                                ;   in Loop: Header=BB0_3 Depth=1
	ldr	w8, [x19, #8]
	cmp	w8, #1
	b.lt	LBB0_9
; %bb.6:                                ;   in Loop: Header=BB0_3 Depth=1
	mov	x26, #0
LBB0_7:                                 ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ldr	x8, [x21]
	ldr	w1, [x8, x20, lsl #2]
	ldr	x8, [x24]
	add	x2, x26, x8
	ldr	x8, [x19, #16]
	madd	x3, x20, x23, x8
	mov	x0, x19
	bl	_amdgpu_irq_add_id
	cbnz	w0, LBB0_17
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=2
	add	x26, x26, #1
	ldrsw	x8, [x19, #8]
	cmp	x26, x8
	b.lt	LBB0_7
LBB0_9:                                 ;   in Loop: Header=BB0_3 Depth=1
	ldr	x8, [x21]
	ldr	w1, [x8, x20, lsl #2]
	ldr	x2, [x25]
	ldr	x8, [x19, #16]
	madd	x3, x20, x23, x8
	mov	x0, x19
	bl	_amdgpu_irq_add_id
	cbnz	w0, LBB0_17
; %bb.10:                               ;   in Loop: Header=BB0_3 Depth=1
	ldr	w8, [x19]
	b	LBB0_2
LBB0_11:
	mov	x0, x19
	bl	_amdgpu_vcn_sw_init
	cbnz	w0, LBB0_17
; %bb.12:
	ldr	x8, [x19, #88]
Lloh8:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh9:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh10:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_16
; %bb.13:
	ldr	x8, [x19, #72]
	ldr	x20, [x8]
Lloh11:
	adrp	x9, _AMDGPU_UCODE_ID_VCN@GOTPAGE
Lloh12:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_VCN@GOTPAGEOFF]
	ldr	x10, [x9]
	ldr	x11, [x19, #104]
	lsl	x12, x10, #4
	str	x10, [x11, x12]
	ldr	x9, [x9]
	add	x9, x11, x9, lsl #4
	str	x8, [x9, #8]
	ldr	w0, [x20]
	bl	_le32_to_cpu
Lloh13:
	adrp	x21, _PAGE_SIZE@GOTPAGE
Lloh14:
	ldr	x21, [x21, _PAGE_SIZE@GOTPAGEOFF]
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #96]
	add	w8, w8, w0
	str	w8, [x19, #96]
	ldr	w8, [x19]
Lloh15:
	adrp	x9, _VCN25_MAX_HW_INSTANCES_ARCTURUS@GOTPAGE
Lloh16:
	ldr	x9, [x9, _VCN25_MAX_HW_INSTANCES_ARCTURUS@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_15
; %bb.14:
Lloh18:
	adrp	x8, _AMDGPU_UCODE_ID_VCN1@GOTPAGE
Lloh19:
	ldr	x8, [x8, _AMDGPU_UCODE_ID_VCN1@GOTPAGEOFF]
	ldr	x9, [x8]
	ldr	x10, [x19, #104]
	lsl	x11, x9, #4
	str	x9, [x10, x11]
	ldr	x9, [x19, #72]
	ldr	x8, [x8]
	add	x8, x10, x8, lsl #4
	str	x9, [x8, #8]
	ldr	w0, [x20]
	bl	_le32_to_cpu
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #96]
	add	w8, w8, w0
	str	w8, [x19, #96]
LBB0_15:
Lloh20:
	adrp	x0, l_.str@PAGE
Lloh21:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_INFO
LBB0_16:
	mov	x0, x19
	bl	_amdgpu_vcn_resume
	cbz	w0, LBB0_18
LBB0_17:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
LBB0_18:
	ldr	w8, [x19]
	cmp	w8, #1
	b.lt	LBB0_29
; %bb.19:
	mov	w25, #0
	mov	x20, #0
	mov	w28, #1
	b	LBB0_21
LBB0_20:                                ;   in Loop: Header=BB0_21 Depth=1
	mov	w0, #0
	add	x20, x20, #1
	add	w25, w25, #8
	cmp	x20, w8, sxtw
	b.ge	LBB0_17
LBB0_21:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_25 Depth 2
	ldr	w9, [x19, #4]
	lsr	w9, w9, w20
	tbnz	w9, #0, LBB0_20
; %bb.22:                               ;   in Loop: Header=BB0_21 Depth=1
Lloh22:
	adrp	x8, _mmUVD_CONTEXT_ID_INTERNAL_OFFSET@GOTPAGE
Lloh23:
	ldr	x8, [x8, _mmUVD_CONTEXT_ID_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	str	w8, [x19, #68]
Lloh25:
	adrp	x8, _mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET@GOTPAGE
Lloh26:
	ldr	x8, [x8, _mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
Lloh28:
	adrp	x9, _mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET@GOTPAGE
Lloh29:
	ldr	x9, [x9, _mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #60]
Lloh31:
	adrp	x8, _mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET@GOTPAGE
Lloh32:
	ldr	x8, [x8, _mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
Lloh34:
	adrp	x9, _mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET@GOTPAGE
Lloh35:
	ldr	x9, [x9, _mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh36:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #52]
Lloh37:
	adrp	x8, _mmUVD_GP_SCRATCH8_INTERNAL_OFFSET@GOTPAGE
Lloh38:
	ldr	x8, [x8, _mmUVD_GP_SCRATCH8_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
Lloh40:
	adrp	x9, _mmUVD_SCRATCH9_INTERNAL_OFFSET@GOTPAGE
Lloh41:
	ldr	x9, [x9, _mmUVD_SCRATCH9_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh42:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #44]
Lloh43:
	adrp	x21, _UVD@GOTPAGE
Lloh44:
	ldr	x21, [x21, _UVD@GOTPAGEOFF]
	ldr	w0, [x21]
Lloh45:
	adrp	x8, _mmUVD_SCRATCH9@GOTPAGE
Lloh46:
	ldr	x8, [x8, _mmUVD_SCRATCH9@GOTPAGEOFF]
Lloh47:
	ldr	w2, [x8]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	ldr	x8, [x19, #16]
	mov	w9, #88
	mul	x27, x20, x9
	add	x8, x8, x27
	str	x0, [x8, #80]
Lloh48:
	adrp	x8, _mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET@GOTPAGE
Lloh49:
	ldr	x8, [x8, _mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh50:
	ldr	w8, [x8]
	str	w8, [x19, #40]
	ldr	w0, [x21]
Lloh51:
	adrp	x8, _mmUVD_GPCOM_VCPU_DATA0@GOTPAGE
Lloh52:
	ldr	x8, [x8, _mmUVD_GPCOM_VCPU_DATA0@GOTPAGEOFF]
Lloh53:
	ldr	w2, [x8]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	ldr	x8, [x19, #16]
	add	x8, x8, x27
	str	x0, [x8, #72]
Lloh54:
	adrp	x8, _mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET@GOTPAGE
Lloh55:
	ldr	x8, [x8, _mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh56:
	ldr	w8, [x8]
	str	w8, [x19, #36]
	ldr	w0, [x21]
Lloh57:
	adrp	x8, _mmUVD_GPCOM_VCPU_DATA1@GOTPAGE
Lloh58:
	ldr	x8, [x8, _mmUVD_GPCOM_VCPU_DATA1@GOTPAGEOFF]
Lloh59:
	ldr	w2, [x8]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	ldr	x8, [x19, #16]
	add	x8, x8, x27
	str	x0, [x8, #64]
Lloh60:
	adrp	x8, _mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET@GOTPAGE
Lloh61:
	ldr	x8, [x8, _mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh62:
	ldr	w8, [x8]
	str	w8, [x19, #32]
	ldr	w0, [x21]
Lloh63:
	adrp	x8, _mmUVD_GPCOM_VCPU_CMD@GOTPAGE
Lloh64:
	ldr	x8, [x8, _mmUVD_GPCOM_VCPU_CMD@GOTPAGEOFF]
Lloh65:
	ldr	w2, [x8]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	ldr	x8, [x19, #16]
	add	x8, x8, x27
	str	x0, [x8, #56]
Lloh66:
	adrp	x8, _mmUVD_NO_OP_INTERNAL_OFFSET@GOTPAGE
Lloh67:
	ldr	x8, [x8, _mmUVD_NO_OP_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh68:
	ldr	w8, [x8]
	str	w8, [x19, #28]
	ldr	w0, [x21]
Lloh69:
	adrp	x8, _mmUVD_NO_OP@GOTPAGE
Lloh70:
	ldr	x8, [x8, _mmUVD_NO_OP@GOTPAGEOFF]
Lloh71:
	ldr	w2, [x8]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	ldr	x8, [x19, #16]
	add	x8, x8, x27
	str	x0, [x8, #48]
Lloh72:
	adrp	x8, _mmUVD_JPEG_PITCH_INTERNAL_OFFSET@GOTPAGE
Lloh73:
	ldr	x8, [x8, _mmUVD_JPEG_PITCH_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh74:
	ldr	w8, [x8]
	str	w8, [x19, #24]
	ldr	w0, [x21]
Lloh75:
	adrp	x8, _mmUVD_JPEG_PITCH@GOTPAGE
Lloh76:
	ldr	x8, [x8, _mmUVD_JPEG_PITCH@GOTPAGEOFF]
Lloh77:
	ldr	w2, [x8]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	ldr	x8, [x19, #16]
	add	x24, x8, x27
	str	w28, [x24, #24]!
	str	x0, [x24, #16]
	ldr	w8, [x19, #80]
	lsl	w21, w20, #3
	add	w8, w21, w8, lsl #1
	str	w8, [x24, #4]
	ldr	w0, [x24, #8]
Lloh78:
	adrp	x1, l_.str.1@PAGE
Lloh79:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x2, x20
	bl	_sprintf
	ldr	x8, [x19, #16]
	add	x3, x8, x27
	mov	x0, x19
	mov	x1, x24
	mov	w2, #512
	mov	w4, #0
	bl	_amdgpu_ring_init
	cbnz	w0, LBB0_17
; %bb.23:                               ;   in Loop: Header=BB0_21 Depth=1
	ldr	w8, [x19, #8]
	cmp	w8, #1
	b.lt	LBB0_27
; %bb.24:                               ;   in Loop: Header=BB0_21 Depth=1
	mov	x27, #0
	mov	x23, #0
	mov	w8, w25
	add	x22, x8, #2
LBB0_25:                                ;   Parent Loop BB0_21 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ldr	x8, [x19, #16]
	mov	w9, #88
	mul	x26, x20, x9
	add	x8, x8, x26
	ldr	x8, [x8, #16]
	add	x24, x8, x27
	ldr	w8, [x19, #80]
	add	w9, w22, w23
	add	w8, w9, w8, lsl #1
	stp	w28, w8, [x24]
	ldr	w0, [x24, #8]
	str	x23, [sp]
Lloh80:
	adrp	x1, l_.str.2@PAGE
Lloh81:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x2, x20
	bl	_sprintf
	ldr	x8, [x19, #16]
	add	x3, x8, x26
	mov	x0, x19
	mov	x1, x24
	mov	w2, #512
	mov	w4, #0
	bl	_amdgpu_ring_init
	cbnz	w0, LBB0_17
; %bb.26:                               ;   in Loop: Header=BB0_25 Depth=2
	add	x23, x23, #1
	ldrsw	x8, [x19, #8]
	add	x27, x27, #12
	cmp	x23, x8
	b.lt	LBB0_25
LBB0_27:                                ;   in Loop: Header=BB0_21 Depth=1
	ldr	x8, [x19, #16]
	mov	w9, #88
	mul	x22, x20, x9
	add	x24, x8, x22
	str	w28, [x24, #4]!
	ldr	w8, [x19, #80]
	orr	w9, w21, #0x1
	add	w8, w9, w8, lsl #1
	str	w8, [x24, #4]
	ldr	w0, [x24, #8]
Lloh82:
	adrp	x1, l_.str.3@PAGE
Lloh83:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x2, x20
	bl	_sprintf
	ldr	x8, [x19, #16]
	add	x3, x8, x22
	mov	x0, x19
	mov	x1, x24
	mov	w2, #512
	mov	w4, #0
	bl	_amdgpu_ring_init
	cbnz	w0, LBB0_17
; %bb.28:                               ;   in Loop: Header=BB0_21 Depth=1
	ldr	w8, [x19]
	b	LBB0_20
LBB0_29:
	mov	w0, #0
	b	LBB0_17
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpAdd	Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpAdd	Lloh80, Lloh81
	.loh AdrpAdd	Lloh82, Lloh83
	.cfi_endproc
                                        ; -- End function
	.comm	_amdgpu_ih_clientid_vcns,8,3    ; @amdgpu_ih_clientid_vcns
	.comm	_VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,8,3 ; @VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT
	.comm	_VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE,8,3 ; @VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE
	.comm	_VCN_2_0__SRCID__JPEG_DECODE,8,3 ; @VCN_2_0__SRCID__JPEG_DECODE
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_VCN,8,3        ; @AMDGPU_UCODE_ID_VCN
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
	.comm	_VCN25_MAX_HW_INSTANCES_ARCTURUS,4,2 ; @VCN25_MAX_HW_INSTANCES_ARCTURUS
	.comm	_AMDGPU_UCODE_ID_VCN1,8,3       ; @AMDGPU_UCODE_ID_VCN1
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"PSP loading VCN firmware\n"

	.comm	_mmUVD_CONTEXT_ID_INTERNAL_OFFSET,4,2 ; @mmUVD_CONTEXT_ID_INTERNAL_OFFSET
	.comm	_mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET,4,2 ; @mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET
	.comm	_mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,4,2 ; @mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET
	.comm	_mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,4,2 ; @mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET
	.comm	_mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET,4,2 ; @mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET
	.comm	_mmUVD_GP_SCRATCH8_INTERNAL_OFFSET,4,2 ; @mmUVD_GP_SCRATCH8_INTERNAL_OFFSET
	.comm	_mmUVD_SCRATCH9_INTERNAL_OFFSET,4,2 ; @mmUVD_SCRATCH9_INTERNAL_OFFSET
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_SCRATCH9,4,2             ; @mmUVD_SCRATCH9
	.comm	_mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET,4,2 ; @mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET
	.comm	_mmUVD_GPCOM_VCPU_DATA0,4,2     ; @mmUVD_GPCOM_VCPU_DATA0
	.comm	_mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET,4,2 ; @mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET
	.comm	_mmUVD_GPCOM_VCPU_DATA1,4,2     ; @mmUVD_GPCOM_VCPU_DATA1
	.comm	_mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET,4,2 ; @mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET
	.comm	_mmUVD_GPCOM_VCPU_CMD,4,2       ; @mmUVD_GPCOM_VCPU_CMD
	.comm	_mmUVD_NO_OP_INTERNAL_OFFSET,4,2 ; @mmUVD_NO_OP_INTERNAL_OFFSET
	.comm	_mmUVD_NO_OP,4,2                ; @mmUVD_NO_OP
	.comm	_mmUVD_JPEG_PITCH_INTERNAL_OFFSET,4,2 ; @mmUVD_JPEG_PITCH_INTERNAL_OFFSET
	.comm	_mmUVD_JPEG_PITCH,4,2           ; @mmUVD_JPEG_PITCH
l_.str.1:                               ; @.str.1
	.asciz	"vcn_dec_%d"

l_.str.2:                               ; @.str.2
	.asciz	"vcn_enc_%d.%d"

l_.str.3:                               ; @.str.3
	.asciz	"vcn_jpeg_%d"

	.no_dead_strip	_vcn_v2_5_sw_init
.subsections_via_symbols
