	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function intel_dp_update_link_train
_intel_dp_update_link_train:            ## @intel_dp_update_link_train
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	callq	_intel_dp_set_signal_levels
	leaq	8(%rbx), %rdi
	movq	_DP_TRAINING_LANE0_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%rbx), %ecx
	movl	4(%rbx), %edx
	callq	_drm_dp_dpcd_write
	xorl	%ecx, %ecx
	cmpl	(%rbx), %eax
	sete	%cl
	movl	%ecx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DP_TRAINING_LANE0_SET,4,2      ## @DP_TRAINING_LANE0_SET
	.no_dead_strip	_intel_dp_update_link_train
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function intel_dp_update_link_train
_intel_dp_update_link_train:            ; @intel_dp_update_link_train
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_intel_dp_set_signal_levels
	add	x0, x19, #8
Lloh0:
	adrp	x8, _DP_TRAINING_LANE0_SET@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DP_TRAINING_LANE0_SET@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	ldp	w3, w2, [x19]
	bl	_drm_dp_dpcd_write
	ldr	w8, [x19]
	cmp	w0, w8
	cset	w0, eq
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_DP_TRAINING_LANE0_SET,4,2      ; @DP_TRAINING_LANE0_SET
	.no_dead_strip	_intel_dp_update_link_train
.subsections_via_symbols
