	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dce_v10_0_crtc_do_set_base
_dce_v10_0_crtc_do_set_base:            ## @dce_v10_0_crtc_do_set_base
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$104, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%r8d, %r13d
	movl	%ecx, -88(%rbp)                 ## 4-byte Spill
	movl	%edx, -92(%rbp)                 ## 4-byte Spill
	movq	%rsi, %r15
	movq	%rdi, %rbx
	callq	_to_amdgpu_crtc
	movq	%rax, %r12
	movq	16(%rbx), %rax
	movq	(%rax), %rax
	movq	%rax, -128(%rbp)                ## 8-byte Spill
	movq	_GRPH_SWAP_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	_GRPH_ENDIAN_SWAP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_ENDIAN_NONE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%edi, %edi
	callq	_REG_SET_FIELD
	movq	%r15, %rcx
	movl	%r13d, -76(%rbp)                ## 4-byte Spill
	testl	%r13d, %r13d
	jne	LBB0_3
## %bb.1:
	movq	(%rbx), %rcx
	movq	(%rcx), %rcx
	testq	%rcx, %rcx
	je	LBB0_2
LBB0_3:
	movl	%eax, -72(%rbp)                 ## 4-byte Spill
	movq	%rbx, -56(%rbp)                 ## 8-byte Spill
	movq	%r15, -120(%rbp)                ## 8-byte Spill
	movq	16(%rcx), %rax
	movq	(%rax), %rdi
	movq	%rcx, %r13
	callq	_gem_to_amdgpu_bo
	movq	%rax, %r15
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_bo_reserve
	movl	%eax, %ebx
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	callq	_unlikely
	testq	%rax, %rax
	jne	LBB0_38
## %bb.4:
	movq	%r13, -104(%rbp)                ## 8-byte Spill
	cmpl	$0, -76(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_5
LBB0_8:
	movq	%r15, %rdi
	callq	_amdgpu_bo_gpu_offset
	movq	%rax, %rbx
	leaq	-64(%rbp), %rsi
	movq	%r15, %rdi
	callq	_amdgpu_bo_get_tiling_flags
	movq	%r15, %rdi
	callq	_amdgpu_bo_unreserve
	movq	-64(%rbp), %rdi
	movq	_PIPE_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AMDGPU_TILING_GET
	movl	%eax, %ecx
	movq	-104(%rbp), %rax                ## 8-byte Reload
	movq	24(%rax), %rax
	movl	(%rax), %edi
	leal	-128(%rdi), %eax
	cmpl	$15, %eax
	ja	LBB0_25
## %bb.9:
	movl	%ecx, -68(%rbp)                 ## 4-byte Spill
	movq	%rbx, -112(%rbp)                ## 8-byte Spill
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_20:
	movq	_GRPH_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_GRPH_DEPTH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%edi, %edi
	movl	$2, %ecx
	jmp	LBB0_11
LBB0_2:
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	jmp	LBB0_37
LBB0_5:
	movq	_AMDGPU_GEM_DOMAIN_VRAM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_amdgpu_bo_pin
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	callq	_unlikely
	testq	%rax, %rax
	je	LBB0_8
## %bb.6:
	movq	%r15, %rdi
	callq	_amdgpu_bo_unreserve
LBB0_7:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
	jmp	LBB0_38
LBB0_16:
	movq	_GRPH_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_GRPH_DEPTH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%edi, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_GRPH_FORMAT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$2, %ecx
	jmp	LBB0_12
LBB0_21:
	movq	_GRPH_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_GRPH_DEPTH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	$0, -44(%rbp)                   ## 4-byte Folded Spill
	xorl	%edi, %edi
	movl	$2, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_GRPH_FORMAT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	jmp	LBB0_22
LBB0_17:
	movq	_GRPH_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_GRPH_DEPTH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%edi, %edi
	movl	$1, %ecx
	jmp	LBB0_11
LBB0_24:
	movq	_GRPH_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_GRPH_DEPTH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%edi, %edi
	movl	$2, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_GRPH_FORMAT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	%eax, %r15d
	movl	(%r14), %esi
	movq	_GRPH_RED_CROSSBAR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	-72(%rbp), %edi                 ## 4-byte Reload
	movl	$2, %ecx
	callq	_REG_SET_FIELD
	movl	(%r14), %esi
	movq	_GRPH_BLUE_CROSSBAR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$2, %ecx
	callq	_REG_SET_FIELD
	movl	%eax, -72(%rbp)                 ## 4-byte Spill
	jmp	LBB0_13
LBB0_18:
	movq	_GRPH_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_GRPH_DEPTH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%edi, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_GRPH_FORMAT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$5, %ecx
	jmp	LBB0_12
LBB0_23:
	movq	_GRPH_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_GRPH_DEPTH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	$0, -44(%rbp)                   ## 4-byte Folded Spill
	xorl	%edi, %edi
	movl	$2, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_GRPH_FORMAT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$4, %ecx
LBB0_22:
	callq	_REG_SET_FIELD
	movl	%eax, %r15d
	jmp	LBB0_14
LBB0_25:
	leaq	-136(%rbp), %rsi
                                        ## kill: def $edi killed $edi killed $rdi
	callq	_drm_get_format_name
	leaq	L_.str.1(%rip), %rdi
	movl	%eax, %esi
	callq	_DRM_ERROR
	jmp	LBB0_7
LBB0_19:
	movq	_GRPH_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_GRPH_DEPTH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%edi, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_GRPH_FORMAT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	jmp	LBB0_12
LBB0_10:
	movq	_GRPH_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_GRPH_DEPTH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%edi, %edi
	xorl	%ecx, %ecx
LBB0_11:
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_GRPH_FORMAT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
LBB0_12:
	callq	_REG_SET_FIELD
	movl	%eax, %r15d
LBB0_13:
	movb	$1, %al
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
LBB0_14:
	movq	-56(%rbp), %r13                 ## 8-byte Reload
	movq	-64(%rbp), %rdi
	movq	_ARRAY_MODE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	callq	_AMDGPU_TILING_GET
	movq	_ARRAY_2D_TILED_THIN1@GOTPCREL(%rip), %rcx
	movq	-64(%rbp), %rdi
	cmpl	(%rcx), %eax
	jne	LBB0_26
## %bb.15:
	movq	_BANK_WIDTH@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AMDGPU_TILING_GET
	movl	%eax, -80(%rbp)                 ## 4-byte Spill
	movq	-64(%rbp), %rdi
	movq	_BANK_HEIGHT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AMDGPU_TILING_GET
	movl	%eax, -84(%rbp)                 ## 4-byte Spill
	movq	-64(%rbp), %rdi
	movq	_MACRO_TILE_ASPECT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AMDGPU_TILING_GET
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	movq	-64(%rbp), %rdi
	movq	_TILE_SPLIT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AMDGPU_TILING_GET
	movl	%eax, %r14d
	movq	-64(%rbp), %rdi
	movq	_NUM_BANKS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AMDGPU_TILING_GET
	movq	_GRPH_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_GRPH_NUM_BANKS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%r15d, %edi
	movl	%eax, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_GRPH_ARRAY_MODE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_ARRAY_2D_TILED_THIN1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%eax, %edi
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_GRPH_TILE_SPLIT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	%r14d, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_GRPH_BANK_WIDTH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	-80(%rbp), %ecx                 ## 4-byte Reload
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_GRPH_BANK_HEIGHT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	-84(%rbp), %ecx                 ## 4-byte Reload
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_GRPH_MACRO_TILE_ASPECT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	-56(%rbp), %ecx                 ## 4-byte Reload
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_GRPH_MICRO_TILE_MODE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_ADDR_SURF_MICRO_TILING_DISPLAY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%eax, %edi
	jmp	LBB0_28
LBB0_26:
	movl	(%rbx), %esi
	callq	_AMDGPU_TILING_GET
	movq	_ARRAY_1D_TILED_THIN1@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_29
## %bb.27:
	movq	_GRPH_CONTROL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_GRPH_ARRAY_MODE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%r15d, %edi
	movl	%eax, %ecx
LBB0_28:
	callq	_REG_SET_FIELD
	movl	%eax, %r15d
LBB0_29:
	movl	-68(%rbp), %ecx                 ## 4-byte Reload
	movq	_GRPH_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_GRPH_PIPE_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %edi
	callq	_REG_SET_FIELD
	movl	%eax, %r15d
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	_dce_v10_0_vga_enable
	movq	_mmGRPH_FLIP_CONTROL@GOTPCREL(%rip), %rbx
	movq	(%r12), %rdi
	addq	(%rbx), %rdi
	callq	_RREG32
	movq	_GRPH_FLIP_CONTROL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_GRPH_SURFACE_UPDATE_H_RETRACE_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movq	(%r12), %rdi
	addq	(%rbx), %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH@GOTPCREL(%rip), %rax
	movq	(%r12), %rbx
	addq	(%rax), %rbx
	movq	-112(%rbp), %r14                ## 8-byte Reload
	movq	%r14, %rdi
	callq	_upper_32_bits
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH@GOTPCREL(%rip), %rax
	movq	(%r12), %rbx
	addq	(%rax), %rbx
	movq	%r14, %rdi
	callq	_upper_32_bits
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmGRPH_PRIMARY_SURFACE_ADDRESS@GOTPCREL(%rip), %rax
	movq	(%r12), %rdi
	addq	(%rax), %rdi
	movq	_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	andl	%r14d, %esi
	callq	_WREG32
	movq	_mmGRPH_SECONDARY_SURFACE_ADDRESS@GOTPCREL(%rip), %rax
	movq	(%r12), %rdi
	addq	(%rax), %rdi
	movq	_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %r14d
	movl	%r14d, %esi
	callq	_WREG32
	movq	_mmGRPH_CONTROL@GOTPCREL(%rip), %rax
	movq	(%r12), %rdi
	addq	(%rax), %rdi
	movl	%r15d, %esi
	callq	_WREG32
	movq	_mmGRPH_SWAP_CNTL@GOTPCREL(%rip), %rax
	movq	(%r12), %rdi
	addq	(%rax), %rdi
	movl	-72(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_mmGRPH_LUT_10BIT_BYPASS@GOTPCREL(%rip), %r14
	movq	(%r12), %rdi
	addq	(%r14), %rdi
	callq	_RREG32
	movq	_GRPH_LUT_10BIT_BYPASS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_GRPH_LUT_10BIT_BYPASS_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	-44(%rbp), %ebx                 ## 4-byte Reload
	movl	%ebx, %ecx
	xorb	$1, %cl
	movzbl	%cl, %ecx
	movl	%eax, %edi
	callq	_REG_SET_FIELD
	movq	(%r12), %rdi
	addq	(%r14), %rdi
	movl	%eax, %esi
	callq	_WREG32
	testb	%bl, %bl
	jne	LBB0_31
## %bb.30:
	leaq	L_.str.2(%rip), %rdi
	callq	_DRM_DEBUG_KMS
LBB0_31:
	movq	_mmGRPH_SURFACE_OFFSET_X@GOTPCREL(%rip), %rax
	movq	(%r12), %rdi
	addq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmGRPH_SURFACE_OFFSET_Y@GOTPCREL(%rip), %rax
	movq	(%r12), %rdi
	addq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmGRPH_X_START@GOTPCREL(%rip), %rax
	movq	(%r12), %rdi
	addq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmGRPH_Y_START@GOTPCREL(%rip), %rax
	movq	(%r12), %rdi
	addq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmGRPH_X_END@GOTPCREL(%rip), %rax
	movq	(%r12), %rdi
	addq	(%rax), %rdi
	movq	-104(%rbp), %rbx                ## 8-byte Reload
	movl	(%rbx), %esi
	callq	_WREG32
	movq	_mmGRPH_Y_END@GOTPCREL(%rip), %rax
	movq	(%r12), %rdi
	addq	(%rax), %rdi
	movl	4(%rbx), %esi
	callq	_WREG32
	movq	8(%rbx), %rax
	movq	24(%rbx), %rcx
	movl	(%rax), %eax
	movq	8(%rcx), %rcx
	cltd
	idivl	(%rcx)
	movq	_mmGRPH_PITCH@GOTPCREL(%rip), %rcx
	movq	(%r12), %rdi
	addq	(%rcx), %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	%r13, %rdi
	movl	$1, %esi
	callq	_dce_v10_0_grph_enable
	movq	_mmLB_DESKTOP_HEIGHT@GOTPCREL(%rip), %rax
	movq	(%r12), %rdi
	addq	(%rax), %rdi
	movl	4(%rbx), %esi
	callq	_WREG32
	movq	_mmVIEWPORT_START@GOTPCREL(%rip), %rax
	movq	(%r12), %rdi
	addq	(%rax), %rdi
	movl	-88(%rbp), %eax                 ## 4-byte Reload
	andl	$-2, %eax
	movl	-92(%rbp), %esi                 ## 4-byte Reload
	andl	$-4, %esi
	shll	$16, %esi
	orl	%eax, %esi
	callq	_WREG32
	movl	8(%r13), %esi
	movl	12(%r13), %eax
	incl	%eax
	andl	$-2, %eax
	movq	_mmVIEWPORT_SIZE@GOTPCREL(%rip), %rcx
	movq	(%r12), %rdi
	addq	(%rcx), %rdi
	shll	$16, %esi
	orl	%eax, %esi
	callq	_WREG32
	movq	_mmMASTER_UPDATE_MODE@GOTPCREL(%rip), %rax
	movq	(%r12), %rdi
	addq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	-120(%rbp), %rcx                ## 8-byte Reload
	testq	%rcx, %rcx
	je	LBB0_36
## %bb.32:
	cmpl	$0, -76(%rbp)                   ## 4-byte Folded Reload
	jne	LBB0_36
## %bb.33:
	movq	(%r13), %rax
	cmpq	%rcx, (%rax)
	je	LBB0_36
## %bb.34:
	movq	16(%rcx), %rax
	movq	(%rax), %rdi
	callq	_gem_to_amdgpu_bo
	movq	%rax, %r14
	movq	%rax, %rdi
	movl	$1, %esi
	callq	_amdgpu_bo_reserve
	movl	%eax, %ebx
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	callq	_unlikely
	testq	%rax, %rax
	jne	LBB0_38
## %bb.35:
	movq	%r14, %rdi
	callq	_amdgpu_bo_unpin
	movq	%r14, %rdi
	callq	_amdgpu_bo_unreserve
LBB0_36:
	movq	-128(%rbp), %rdi                ## 8-byte Reload
	callq	_dce_v10_0_bandwidth_update
LBB0_37:
	xorl	%ebx, %ebx
LBB0_38:
	movl	%ebx, %eax
	addq	$104, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_20, LBB0_20-LJTI0_0
.set L0_0_set_16, LBB0_16-LJTI0_0
.set L0_0_set_21, LBB0_21-LJTI0_0
.set L0_0_set_17, LBB0_17-LJTI0_0
.set L0_0_set_24, LBB0_24-LJTI0_0
.set L0_0_set_19, LBB0_19-LJTI0_0
.set L0_0_set_10, LBB0_10-LJTI0_0
.set L0_0_set_18, LBB0_18-LJTI0_0
.set L0_0_set_23, LBB0_23-LJTI0_0
LJTI0_0:
	.long	L0_0_set_20
	.long	L0_0_set_16
	.long	L0_0_set_21
	.long	L0_0_set_17
	.long	L0_0_set_24
	.long	L0_0_set_19
	.long	L0_0_set_10
	.long	L0_0_set_18
	.long	L0_0_set_23
	.long	L0_0_set_18
	.long	L0_0_set_23
	.long	L0_0_set_20
	.long	L0_0_set_16
	.long	L0_0_set_21
	.long	L0_0_set_17
	.long	L0_0_set_24
	.end_data_region
                                        ## -- End function
	.comm	_GRPH_SWAP_CNTL,4,2             ## @GRPH_SWAP_CNTL
	.comm	_GRPH_ENDIAN_SWAP,4,2           ## @GRPH_ENDIAN_SWAP
	.comm	_ENDIAN_NONE,4,2                ## @ENDIAN_NONE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"No FB bound\n"

	.comm	_AMDGPU_GEM_DOMAIN_VRAM,4,2     ## @AMDGPU_GEM_DOMAIN_VRAM
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_PIPE_CONFIG,4,2                ## @PIPE_CONFIG
	.comm	_GRPH_CONTROL,4,2               ## @GRPH_CONTROL
	.comm	_GRPH_DEPTH,4,2                 ## @GRPH_DEPTH
	.comm	_GRPH_FORMAT,4,2                ## @GRPH_FORMAT
	.comm	_GRPH_RED_CROSSBAR,4,2          ## @GRPH_RED_CROSSBAR
	.comm	_GRPH_BLUE_CROSSBAR,4,2         ## @GRPH_BLUE_CROSSBAR
L_.str.1:                               ## @.str.1
	.asciz	"Unsupported screen format %s\n"

	.comm	_ARRAY_MODE,4,2                 ## @ARRAY_MODE
	.comm	_ARRAY_2D_TILED_THIN1,4,2       ## @ARRAY_2D_TILED_THIN1
	.comm	_BANK_WIDTH,4,2                 ## @BANK_WIDTH
	.comm	_BANK_HEIGHT,4,2                ## @BANK_HEIGHT
	.comm	_MACRO_TILE_ASPECT,4,2          ## @MACRO_TILE_ASPECT
	.comm	_TILE_SPLIT,4,2                 ## @TILE_SPLIT
	.comm	_NUM_BANKS,4,2                  ## @NUM_BANKS
	.comm	_GRPH_NUM_BANKS,4,2             ## @GRPH_NUM_BANKS
	.comm	_GRPH_ARRAY_MODE,4,2            ## @GRPH_ARRAY_MODE
	.comm	_GRPH_TILE_SPLIT,4,2            ## @GRPH_TILE_SPLIT
	.comm	_GRPH_BANK_WIDTH,4,2            ## @GRPH_BANK_WIDTH
	.comm	_GRPH_BANK_HEIGHT,4,2           ## @GRPH_BANK_HEIGHT
	.comm	_GRPH_MACRO_TILE_ASPECT,4,2     ## @GRPH_MACRO_TILE_ASPECT
	.comm	_GRPH_MICRO_TILE_MODE,4,2       ## @GRPH_MICRO_TILE_MODE
	.comm	_ADDR_SURF_MICRO_TILING_DISPLAY,4,2 ## @ADDR_SURF_MICRO_TILING_DISPLAY
	.comm	_ARRAY_1D_TILED_THIN1,4,2       ## @ARRAY_1D_TILED_THIN1
	.comm	_GRPH_PIPE_CONFIG,4,2           ## @GRPH_PIPE_CONFIG
	.comm	_mmGRPH_FLIP_CONTROL,8,3        ## @mmGRPH_FLIP_CONTROL
	.comm	_GRPH_FLIP_CONTROL,4,2          ## @GRPH_FLIP_CONTROL
	.comm	_GRPH_SURFACE_UPDATE_H_RETRACE_EN,4,2 ## @GRPH_SURFACE_UPDATE_H_RETRACE_EN
	.comm	_mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH,8,3 ## @mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
	.comm	_mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH,8,3 ## @mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH
	.comm	_mmGRPH_PRIMARY_SURFACE_ADDRESS,8,3 ## @mmGRPH_PRIMARY_SURFACE_ADDRESS
	.comm	_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK,4,2 ## @GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK
	.comm	_mmGRPH_SECONDARY_SURFACE_ADDRESS,8,3 ## @mmGRPH_SECONDARY_SURFACE_ADDRESS
	.comm	_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK,4,2 ## @GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK
	.comm	_mmGRPH_CONTROL,8,3             ## @mmGRPH_CONTROL
	.comm	_mmGRPH_SWAP_CNTL,8,3           ## @mmGRPH_SWAP_CNTL
	.comm	_mmGRPH_LUT_10BIT_BYPASS,8,3    ## @mmGRPH_LUT_10BIT_BYPASS
	.comm	_GRPH_LUT_10BIT_BYPASS,4,2      ## @GRPH_LUT_10BIT_BYPASS
	.comm	_GRPH_LUT_10BIT_BYPASS_EN,4,2   ## @GRPH_LUT_10BIT_BYPASS_EN
L_.str.2:                               ## @.str.2
	.asciz	"Bypassing hardware LUT due to 10 bit fb scanout.\n"

	.comm	_mmGRPH_SURFACE_OFFSET_X,8,3    ## @mmGRPH_SURFACE_OFFSET_X
	.comm	_mmGRPH_SURFACE_OFFSET_Y,8,3    ## @mmGRPH_SURFACE_OFFSET_Y
	.comm	_mmGRPH_X_START,8,3             ## @mmGRPH_X_START
	.comm	_mmGRPH_Y_START,8,3             ## @mmGRPH_Y_START
	.comm	_mmGRPH_X_END,8,3               ## @mmGRPH_X_END
	.comm	_mmGRPH_Y_END,8,3               ## @mmGRPH_Y_END
	.comm	_mmGRPH_PITCH,8,3               ## @mmGRPH_PITCH
	.comm	_mmLB_DESKTOP_HEIGHT,8,3        ## @mmLB_DESKTOP_HEIGHT
	.comm	_mmVIEWPORT_START,8,3           ## @mmVIEWPORT_START
	.comm	_mmVIEWPORT_SIZE,8,3            ## @mmVIEWPORT_SIZE
	.comm	_mmMASTER_UPDATE_MODE,8,3       ## @mmMASTER_UPDATE_MODE
	.comm	_ENDIAN_8IN16,4,2               ## @ENDIAN_8IN16
	.comm	_ENDIAN_8IN32,4,2               ## @ENDIAN_8IN32
	.no_dead_strip	_dce_v10_0_crtc_do_set_base
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dce_v10_0_crtc_do_set_base
_dce_v10_0_crtc_do_set_base:            ; @dce_v10_0_crtc_do_set_base
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #160
	.cfi_def_cfa_offset 160
	stp	x28, x27, [sp, #64]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #80]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #96]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #112]            ; 16-byte Folded Spill
	stp	x20, x19, [sp, #128]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #144]            ; 16-byte Folded Spill
	add	x29, sp, #144
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x4
	mov	x19, x3
	mov	x28, x2
	mov	x27, x1
	mov	x22, x0
	bl	_to_amdgpu_crtc
	mov	x23, x0
	ldr	x8, [x22, #16]
	ldr	x26, [x8]
Lloh0:
	adrp	x25, _GRPH_SWAP_CNTL@GOTPAGE
Lloh1:
	ldr	x25, [x25, _GRPH_SWAP_CNTL@GOTPAGEOFF]
	ldr	w1, [x25]
Lloh2:
	adrp	x8, _GRPH_ENDIAN_SWAP@GOTPAGE
Lloh3:
	ldr	x8, [x8, _GRPH_ENDIAN_SWAP@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
Lloh5:
	adrp	x8, _ENDIAN_NONE@GOTPAGE
Lloh6:
	ldr	x8, [x8, _ENDIAN_NONE@GOTPAGEOFF]
Lloh7:
	ldr	w3, [x8]
	mov	w0, #0
	bl	_REG_SET_FIELD
	mov	x20, x27
	cbnz	w21, LBB0_2
; %bb.1:
	ldr	x8, [x22]
	ldr	x20, [x8]
	cbz	x20, LBB0_7
LBB0_2:
	stp	w19, w0, [sp, #40]              ; 8-byte Folded Spill
	ldr	x8, [x20, #16]
	ldr	x0, [x8]
	bl	_gem_to_amdgpu_bo
	mov	x19, x0
	mov	w1, #0
	bl	_amdgpu_bo_reserve
	mov	x24, x0
	cmp	w0, #0
	cset	w0, ne
	bl	_unlikely
	cbnz	x0, LBB0_39
; %bb.3:
	cbz	w21, LBB0_8
LBB0_4:
	mov	x0, x19
	bl	_amdgpu_bo_gpu_offset
	mov	x24, x0
	add	x1, sp, #56
	mov	x0, x19
	bl	_amdgpu_bo_get_tiling_flags
	mov	x0, x19
	bl	_amdgpu_bo_unreserve
	ldr	x0, [sp, #56]
Lloh8:
	adrp	x8, _PIPE_CONFIG@GOTPAGE
Lloh9:
	ldr	x8, [x8, _PIPE_CONFIG@GOTPAGEOFF]
Lloh10:
	ldr	w1, [x8]
	bl	_AMDGPU_TILING_GET
	mov	x9, x0
	ldr	x8, [x20, #24]
	ldr	w0, [x8]
	sub	w8, w0, #128
	cmp	w8, #15
	b.hi	LBB0_18
; %bb.5:
	str	w9, [sp, #20]                   ; 4-byte Folded Spill
	str	w28, [sp, #36]                  ; 4-byte Folded Spill
Lloh11:
	adrp	x9, lJTI0_0@PAGE
Lloh12:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_6
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
Lloh13:
	adrp	x19, _GRPH_CONTROL@GOTPAGE
Lloh14:
	ldr	x19, [x19, _GRPH_CONTROL@GOTPAGEOFF]
	str	x24, [sp, #24]                  ; 8-byte Folded Spill
	br	x10
LBB0_6:
	ldr	w1, [x19]
Lloh15:
	adrp	x8, _GRPH_DEPTH@GOTPAGE
Lloh16:
	ldr	x8, [x8, _GRPH_DEPTH@GOTPAGEOFF]
Lloh17:
	ldr	w2, [x8]
	mov	w0, #0
	mov	w3, #2
	b	LBB0_22
LBB0_7:
Lloh18:
	adrp	x0, l_.str@PAGE
Lloh19:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_KMS
	b	LBB0_38
LBB0_8:
Lloh20:
	adrp	x8, _AMDGPU_GEM_DOMAIN_VRAM@GOTPAGE
Lloh21:
	ldr	x8, [x8, _AMDGPU_GEM_DOMAIN_VRAM@GOTPAGEOFF]
Lloh22:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_amdgpu_bo_pin
	cmp	w0, #0
	cset	w0, ne
	bl	_unlikely
	cbz	x0, LBB0_4
; %bb.9:
	mov	x0, x19
	bl	_amdgpu_bo_unreserve
LBB0_10:
Lloh23:
	adrp	x8, _EINVAL@GOTPAGE
Lloh24:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
	neg	w24, w8
	b	LBB0_39
LBB0_11:
	ldr	w1, [x19]
Lloh26:
	adrp	x8, _GRPH_DEPTH@GOTPAGE
Lloh27:
	ldr	x8, [x8, _GRPH_DEPTH@GOTPAGEOFF]
Lloh28:
	ldr	w2, [x8]
	mov	w8, #1
	str	w8, [sp, #16]                   ; 4-byte Folded Spill
	mov	w0, #0
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh29:
	adrp	x8, _GRPH_FORMAT@GOTPAGE
Lloh30:
	ldr	x8, [x8, _GRPH_FORMAT@GOTPAGEOFF]
Lloh31:
	ldr	w2, [x8]
	mov	w3, #2
	b	LBB0_20
LBB0_12:
	ldr	w1, [x19]
Lloh32:
	adrp	x8, _GRPH_DEPTH@GOTPAGE
Lloh33:
	ldr	x8, [x8, _GRPH_DEPTH@GOTPAGEOFF]
Lloh34:
	ldr	w2, [x8]
	mov	w0, #0
	mov	w3, #2
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh35:
	adrp	x8, _GRPH_FORMAT@GOTPAGE
Lloh36:
	ldr	x8, [x8, _GRPH_FORMAT@GOTPAGEOFF]
Lloh37:
	ldr	w2, [x8]
	mov	w3, #1
	b	LBB0_17
LBB0_13:
	ldr	w1, [x19]
Lloh38:
	adrp	x8, _GRPH_DEPTH@GOTPAGE
Lloh39:
	ldr	x8, [x8, _GRPH_DEPTH@GOTPAGEOFF]
Lloh40:
	ldr	w2, [x8]
	mov	w8, #1
	str	w8, [sp, #16]                   ; 4-byte Folded Spill
	mov	w0, #0
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh41:
	adrp	x8, _GRPH_FORMAT@GOTPAGE
Lloh42:
	ldr	x8, [x8, _GRPH_FORMAT@GOTPAGEOFF]
Lloh43:
	ldr	w2, [x8]
	mov	w3, #0
	b	LBB0_20
LBB0_14:
	ldr	w1, [x19]
Lloh44:
	adrp	x8, _GRPH_DEPTH@GOTPAGE
Lloh45:
	ldr	x8, [x8, _GRPH_DEPTH@GOTPAGEOFF]
Lloh46:
	ldr	w2, [x8]
	mov	w0, #0
	mov	w3, #2
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh47:
	adrp	x8, _GRPH_FORMAT@GOTPAGE
Lloh48:
	ldr	x8, [x8, _GRPH_FORMAT@GOTPAGEOFF]
Lloh49:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	mov	x28, x0
	ldr	w1, [x25]
Lloh50:
	adrp	x8, _GRPH_RED_CROSSBAR@GOTPAGE
Lloh51:
	ldr	x8, [x8, _GRPH_RED_CROSSBAR@GOTPAGEOFF]
Lloh52:
	ldr	w2, [x8]
	ldr	w0, [sp, #44]                   ; 4-byte Folded Reload
	mov	w3, #2
	bl	_REG_SET_FIELD
	ldr	w1, [x25]
Lloh53:
	adrp	x8, _GRPH_BLUE_CROSSBAR@GOTPAGE
Lloh54:
	ldr	x8, [x8, _GRPH_BLUE_CROSSBAR@GOTPAGEOFF]
Lloh55:
	ldr	w2, [x8]
	mov	w3, #2
	bl	_REG_SET_FIELD
	str	w0, [sp, #44]                   ; 4-byte Folded Spill
	b	LBB0_23
LBB0_15:
	ldr	w1, [x19]
Lloh56:
	adrp	x8, _GRPH_DEPTH@GOTPAGE
Lloh57:
	ldr	x8, [x8, _GRPH_DEPTH@GOTPAGEOFF]
Lloh58:
	ldr	w2, [x8]
	mov	w8, #1
	str	w8, [sp, #16]                   ; 4-byte Folded Spill
	mov	w0, #0
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh59:
	adrp	x8, _GRPH_FORMAT@GOTPAGE
Lloh60:
	ldr	x8, [x8, _GRPH_FORMAT@GOTPAGEOFF]
Lloh61:
	ldr	w2, [x8]
	mov	w3, #5
	b	LBB0_20
LBB0_16:
	ldr	w1, [x19]
Lloh62:
	adrp	x8, _GRPH_DEPTH@GOTPAGE
Lloh63:
	ldr	x8, [x8, _GRPH_DEPTH@GOTPAGEOFF]
Lloh64:
	ldr	w2, [x8]
	mov	w0, #0
	mov	w3, #2
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh65:
	adrp	x8, _GRPH_FORMAT@GOTPAGE
Lloh66:
	ldr	x8, [x8, _GRPH_FORMAT@GOTPAGEOFF]
Lloh67:
	ldr	w2, [x8]
	mov	w3, #4
LBB0_17:
	bl	_REG_SET_FIELD
	mov	x28, x0
	str	wzr, [sp, #16]                  ; 4-byte Folded Spill
	b	LBB0_24
LBB0_18:
	add	x1, sp, #48
	bl	_drm_get_format_name
	mov	x1, x0
Lloh68:
	adrp	x0, l_.str.1@PAGE
Lloh69:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_ERROR
	b	LBB0_10
LBB0_19:
	ldr	w1, [x19]
Lloh70:
	adrp	x8, _GRPH_DEPTH@GOTPAGE
Lloh71:
	ldr	x8, [x8, _GRPH_DEPTH@GOTPAGEOFF]
Lloh72:
	ldr	w2, [x8]
	mov	w8, #1
	str	w8, [sp, #16]                   ; 4-byte Folded Spill
	mov	w0, #0
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh73:
	adrp	x8, _GRPH_FORMAT@GOTPAGE
Lloh74:
	ldr	x8, [x8, _GRPH_FORMAT@GOTPAGEOFF]
Lloh75:
	ldr	w2, [x8]
	mov	w3, #1
LBB0_20:
	bl	_REG_SET_FIELD
	mov	x28, x0
	b	LBB0_24
LBB0_21:
	ldr	w1, [x19]
Lloh76:
	adrp	x8, _GRPH_DEPTH@GOTPAGE
Lloh77:
	ldr	x8, [x8, _GRPH_DEPTH@GOTPAGEOFF]
Lloh78:
	ldr	w2, [x8]
	mov	w0, #0
	mov	w3, #0
LBB0_22:
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh79:
	adrp	x8, _GRPH_FORMAT@GOTPAGE
Lloh80:
	ldr	x8, [x8, _GRPH_FORMAT@GOTPAGEOFF]
Lloh81:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	mov	x28, x0
LBB0_23:
	mov	w8, #1
	str	w8, [sp, #16]                   ; 4-byte Folded Spill
LBB0_24:
	ldr	x0, [sp, #56]
Lloh82:
	adrp	x24, _ARRAY_MODE@GOTPAGE
Lloh83:
	ldr	x24, [x24, _ARRAY_MODE@GOTPAGEOFF]
	ldr	w1, [x24]
	bl	_AMDGPU_TILING_GET
	mov	x8, x0
Lloh84:
	adrp	x25, _ARRAY_2D_TILED_THIN1@GOTPAGE
Lloh85:
	ldr	x25, [x25, _ARRAY_2D_TILED_THIN1@GOTPAGEOFF]
	ldr	w9, [x25]
	ldr	x0, [sp, #56]
	cmp	w8, w9
	b.ne	LBB0_26
; %bb.25:
Lloh86:
	adrp	x8, _BANK_WIDTH@GOTPAGE
Lloh87:
	ldr	x8, [x8, _BANK_WIDTH@GOTPAGEOFF]
Lloh88:
	ldr	w1, [x8]
	bl	_AMDGPU_TILING_GET
	str	w0, [sp, #4]                    ; 4-byte Folded Spill
	ldr	x0, [sp, #56]
Lloh89:
	adrp	x8, _BANK_HEIGHT@GOTPAGE
Lloh90:
	ldr	x8, [x8, _BANK_HEIGHT@GOTPAGEOFF]
Lloh91:
	ldr	w1, [x8]
	bl	_AMDGPU_TILING_GET
	str	w0, [sp, #8]                    ; 4-byte Folded Spill
	ldr	x0, [sp, #56]
Lloh92:
	adrp	x8, _MACRO_TILE_ASPECT@GOTPAGE
Lloh93:
	ldr	x8, [x8, _MACRO_TILE_ASPECT@GOTPAGEOFF]
Lloh94:
	ldr	w1, [x8]
	bl	_AMDGPU_TILING_GET
	str	w0, [sp, #12]                   ; 4-byte Folded Spill
	ldr	x0, [sp, #56]
Lloh95:
	adrp	x8, _TILE_SPLIT@GOTPAGE
Lloh96:
	ldr	x8, [x8, _TILE_SPLIT@GOTPAGEOFF]
Lloh97:
	ldr	w1, [x8]
	bl	_AMDGPU_TILING_GET
	mov	x24, x26
	mov	x26, x0
	ldr	x0, [sp, #56]
Lloh98:
	adrp	x8, _NUM_BANKS@GOTPAGE
Lloh99:
	ldr	x8, [x8, _NUM_BANKS@GOTPAGEOFF]
Lloh100:
	ldr	w1, [x8]
	bl	_AMDGPU_TILING_GET
	mov	x3, x0
Lloh101:
	adrp	x19, _GRPH_CONTROL@GOTPAGE
Lloh102:
	ldr	x19, [x19, _GRPH_CONTROL@GOTPAGEOFF]
	ldr	w1, [x19]
Lloh103:
	adrp	x8, _GRPH_NUM_BANKS@GOTPAGE
Lloh104:
	ldr	x8, [x8, _GRPH_NUM_BANKS@GOTPAGEOFF]
Lloh105:
	ldr	w2, [x8]
	mov	x0, x28
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh106:
	adrp	x8, _GRPH_ARRAY_MODE@GOTPAGE
Lloh107:
	ldr	x8, [x8, _GRPH_ARRAY_MODE@GOTPAGEOFF]
Lloh108:
	ldr	w2, [x8]
	ldr	w3, [x25]
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh109:
	adrp	x8, _GRPH_TILE_SPLIT@GOTPAGE
Lloh110:
	ldr	x8, [x8, _GRPH_TILE_SPLIT@GOTPAGEOFF]
Lloh111:
	ldr	w2, [x8]
	mov	x3, x26
	mov	x26, x24
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh112:
	adrp	x8, _GRPH_BANK_WIDTH@GOTPAGE
Lloh113:
	ldr	x8, [x8, _GRPH_BANK_WIDTH@GOTPAGEOFF]
Lloh114:
	ldr	w2, [x8]
	ldr	w3, [sp, #4]                    ; 4-byte Folded Reload
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh115:
	adrp	x8, _GRPH_BANK_HEIGHT@GOTPAGE
Lloh116:
	ldr	x8, [x8, _GRPH_BANK_HEIGHT@GOTPAGEOFF]
Lloh117:
	ldr	w2, [x8]
	ldr	w3, [sp, #8]                    ; 4-byte Folded Reload
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh118:
	adrp	x8, _GRPH_MACRO_TILE_ASPECT@GOTPAGE
Lloh119:
	ldr	x8, [x8, _GRPH_MACRO_TILE_ASPECT@GOTPAGEOFF]
Lloh120:
	ldr	w2, [x8]
	ldr	w3, [sp, #12]                   ; 4-byte Folded Reload
	bl	_REG_SET_FIELD
	ldr	w1, [x19]
Lloh121:
	adrp	x8, _GRPH_MICRO_TILE_MODE@GOTPAGE
Lloh122:
	ldr	x8, [x8, _GRPH_MICRO_TILE_MODE@GOTPAGEOFF]
Lloh123:
	ldr	w2, [x8]
Lloh124:
	adrp	x8, _ADDR_SURF_MICRO_TILING_DISPLAY@GOTPAGE
Lloh125:
	ldr	x8, [x8, _ADDR_SURF_MICRO_TILING_DISPLAY@GOTPAGEOFF]
Lloh126:
	ldr	w3, [x8]
	b	LBB0_28
LBB0_26:
	ldr	w1, [x24]
	bl	_AMDGPU_TILING_GET
Lloh127:
	adrp	x8, _ARRAY_1D_TILED_THIN1@GOTPAGE
Lloh128:
	ldr	x8, [x8, _ARRAY_1D_TILED_THIN1@GOTPAGEOFF]
Lloh129:
	ldr	w8, [x8]
	cmp	w0, w8
	b.ne	LBB0_29
; %bb.27:
	mov	x3, x0
Lloh130:
	adrp	x19, _GRPH_CONTROL@GOTPAGE
Lloh131:
	ldr	x19, [x19, _GRPH_CONTROL@GOTPAGEOFF]
	ldr	w1, [x19]
Lloh132:
	adrp	x8, _GRPH_ARRAY_MODE@GOTPAGE
Lloh133:
	ldr	x8, [x8, _GRPH_ARRAY_MODE@GOTPAGEOFF]
Lloh134:
	ldr	w2, [x8]
	mov	x0, x28
LBB0_28:
	bl	_REG_SET_FIELD
	mov	x28, x0
	ldr	x24, [sp, #24]                  ; 8-byte Folded Reload
	b	LBB0_30
LBB0_29:
	ldr	x24, [sp, #24]                  ; 8-byte Folded Reload
Lloh135:
	adrp	x19, _GRPH_CONTROL@GOTPAGE
Lloh136:
	ldr	x19, [x19, _GRPH_CONTROL@GOTPAGEOFF]
LBB0_30:
	ldr	w1, [x19]
Lloh137:
	adrp	x8, _GRPH_PIPE_CONFIG@GOTPAGE
Lloh138:
	ldr	x8, [x8, _GRPH_PIPE_CONFIG@GOTPAGEOFF]
Lloh139:
	ldr	w2, [x8]
	mov	x0, x28
	ldr	w3, [sp, #20]                   ; 4-byte Folded Reload
	bl	_REG_SET_FIELD
	mov	x28, x0
	mov	x0, x22
	mov	w1, #0
	bl	_dce_v10_0_vga_enable
Lloh140:
	adrp	x19, _mmGRPH_FLIP_CONTROL@GOTPAGE
Lloh141:
	ldr	x19, [x19, _mmGRPH_FLIP_CONTROL@GOTPAGEOFF]
	ldr	x8, [x19]
	ldr	x9, [x23]
	add	x0, x9, x8
	bl	_RREG32
Lloh142:
	adrp	x8, _GRPH_FLIP_CONTROL@GOTPAGE
Lloh143:
	ldr	x8, [x8, _GRPH_FLIP_CONTROL@GOTPAGEOFF]
Lloh144:
	ldr	w1, [x8]
Lloh145:
	adrp	x8, _GRPH_SURFACE_UPDATE_H_RETRACE_EN@GOTPAGE
Lloh146:
	ldr	x8, [x8, _GRPH_SURFACE_UPDATE_H_RETRACE_EN@GOTPAGEOFF]
Lloh147:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	mov	x1, x0
	ldr	x8, [x19]
	ldr	x9, [x23]
	add	x0, x9, x8
	bl	_WREG32
Lloh148:
	adrp	x8, _mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH@GOTPAGE
Lloh149:
	ldr	x8, [x8, _mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH@GOTPAGEOFF]
Lloh150:
	ldr	x8, [x8]
	ldr	x9, [x23]
	add	x19, x9, x8
	mov	x0, x24
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_WREG32
Lloh151:
	adrp	x8, _mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH@GOTPAGE
Lloh152:
	ldr	x8, [x8, _mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH@GOTPAGEOFF]
Lloh153:
	ldr	x8, [x8]
	ldr	x9, [x23]
	add	x19, x9, x8
	mov	x0, x24
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_WREG32
Lloh154:
	adrp	x8, _mmGRPH_PRIMARY_SURFACE_ADDRESS@GOTPAGE
Lloh155:
	ldr	x8, [x8, _mmGRPH_PRIMARY_SURFACE_ADDRESS@GOTPAGEOFF]
Lloh156:
	ldr	x8, [x8]
	ldr	x9, [x23]
	add	x0, x9, x8
Lloh157:
	adrp	x8, _GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK@GOTPAGE
Lloh158:
	ldr	x8, [x8, _GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK@GOTPAGEOFF]
Lloh159:
	ldr	w8, [x8]
	and	w1, w8, w24
	bl	_WREG32
Lloh160:
	adrp	x8, _mmGRPH_SECONDARY_SURFACE_ADDRESS@GOTPAGE
Lloh161:
	ldr	x8, [x8, _mmGRPH_SECONDARY_SURFACE_ADDRESS@GOTPAGEOFF]
Lloh162:
	ldr	x8, [x8]
	ldr	x9, [x23]
	add	x0, x9, x8
Lloh163:
	adrp	x8, _GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK@GOTPAGE
Lloh164:
	ldr	x8, [x8, _GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK@GOTPAGEOFF]
Lloh165:
	ldr	w8, [x8]
	and	w1, w8, w24
	bl	_WREG32
Lloh166:
	adrp	x8, _mmGRPH_CONTROL@GOTPAGE
Lloh167:
	ldr	x8, [x8, _mmGRPH_CONTROL@GOTPAGEOFF]
Lloh168:
	ldr	x8, [x8]
	ldr	x9, [x23]
	add	x0, x9, x8
	mov	x1, x28
	bl	_WREG32
Lloh169:
	adrp	x8, _mmGRPH_SWAP_CNTL@GOTPAGE
Lloh170:
	ldr	x8, [x8, _mmGRPH_SWAP_CNTL@GOTPAGEOFF]
Lloh171:
	ldr	x8, [x8]
	ldr	x9, [x23]
	add	x0, x9, x8
	ldr	w1, [sp, #44]                   ; 4-byte Folded Reload
	bl	_WREG32
Lloh172:
	adrp	x19, _mmGRPH_LUT_10BIT_BYPASS@GOTPAGE
Lloh173:
	ldr	x19, [x19, _mmGRPH_LUT_10BIT_BYPASS@GOTPAGEOFF]
	ldr	x8, [x19]
	ldr	x9, [x23]
	add	x0, x9, x8
	bl	_RREG32
Lloh174:
	adrp	x8, _GRPH_LUT_10BIT_BYPASS@GOTPAGE
Lloh175:
	ldr	x8, [x8, _GRPH_LUT_10BIT_BYPASS@GOTPAGEOFF]
Lloh176:
	ldr	w1, [x8]
Lloh177:
	adrp	x8, _GRPH_LUT_10BIT_BYPASS_EN@GOTPAGE
Lloh178:
	ldr	x8, [x8, _GRPH_LUT_10BIT_BYPASS_EN@GOTPAGEOFF]
Lloh179:
	ldr	w2, [x8]
	ldr	w24, [sp, #16]                  ; 4-byte Folded Reload
	eor	w3, w24, #0x1
	bl	_REG_SET_FIELD
	mov	x1, x0
	ldr	x8, [x19]
	ldr	x9, [x23]
	add	x0, x9, x8
	bl	_WREG32
	tbnz	w24, #0, LBB0_32
; %bb.31:
Lloh180:
	adrp	x0, l_.str.2@PAGE
Lloh181:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	_DRM_DEBUG_KMS
LBB0_32:
Lloh182:
	adrp	x8, _mmGRPH_SURFACE_OFFSET_X@GOTPAGE
Lloh183:
	ldr	x8, [x8, _mmGRPH_SURFACE_OFFSET_X@GOTPAGEOFF]
Lloh184:
	ldr	x8, [x8]
	ldr	x9, [x23]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
Lloh185:
	adrp	x8, _mmGRPH_SURFACE_OFFSET_Y@GOTPAGE
Lloh186:
	ldr	x8, [x8, _mmGRPH_SURFACE_OFFSET_Y@GOTPAGEOFF]
Lloh187:
	ldr	x8, [x8]
	ldr	x9, [x23]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
Lloh188:
	adrp	x8, _mmGRPH_X_START@GOTPAGE
Lloh189:
	ldr	x8, [x8, _mmGRPH_X_START@GOTPAGEOFF]
Lloh190:
	ldr	x8, [x8]
	ldr	x9, [x23]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
Lloh191:
	adrp	x8, _mmGRPH_Y_START@GOTPAGE
Lloh192:
	ldr	x8, [x8, _mmGRPH_Y_START@GOTPAGEOFF]
Lloh193:
	ldr	x8, [x8]
	ldr	x9, [x23]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
Lloh194:
	adrp	x8, _mmGRPH_X_END@GOTPAGE
Lloh195:
	ldr	x8, [x8, _mmGRPH_X_END@GOTPAGEOFF]
Lloh196:
	ldr	x8, [x8]
	ldr	x9, [x23]
	add	x0, x9, x8
	ldr	w1, [x20]
	bl	_WREG32
Lloh197:
	adrp	x8, _mmGRPH_Y_END@GOTPAGE
Lloh198:
	ldr	x8, [x8, _mmGRPH_Y_END@GOTPAGEOFF]
Lloh199:
	ldr	x8, [x8]
	ldr	x9, [x23]
	add	x0, x9, x8
	ldr	w1, [x20, #4]
	bl	_WREG32
	ldr	x8, [x20, #8]
	ldr	w8, [x8]
	ldr	x9, [x20, #24]
	ldr	x9, [x9, #8]
	ldr	w9, [x9]
	sdiv	w1, w8, w9
Lloh200:
	adrp	x8, _mmGRPH_PITCH@GOTPAGE
Lloh201:
	ldr	x8, [x8, _mmGRPH_PITCH@GOTPAGEOFF]
Lloh202:
	ldr	x8, [x8]
	ldr	x9, [x23]
	add	x0, x9, x8
	bl	_WREG32
	mov	x0, x22
	mov	w1, #1
	bl	_dce_v10_0_grph_enable
Lloh203:
	adrp	x8, _mmLB_DESKTOP_HEIGHT@GOTPAGE
Lloh204:
	ldr	x8, [x8, _mmLB_DESKTOP_HEIGHT@GOTPAGEOFF]
Lloh205:
	ldr	x8, [x8]
	ldr	x9, [x23]
	add	x0, x9, x8
	ldr	w1, [x20, #4]
	bl	_WREG32
	ldr	w8, [sp, #40]                   ; 4-byte Folded Reload
	and	w8, w8, #0xfffffffe
Lloh206:
	adrp	x9, _mmVIEWPORT_START@GOTPAGE
Lloh207:
	ldr	x9, [x9, _mmVIEWPORT_START@GOTPAGEOFF]
Lloh208:
	ldr	x9, [x9]
	ldr	x10, [x23]
	add	x0, x10, x9
	ldr	w9, [sp, #36]                   ; 4-byte Folded Reload
	lsl	w9, w9, #16
	and	w9, w9, #0xfffc0000
	orr	w1, w9, w8
	bl	_WREG32
	ldp	w8, w9, [x22, #8]
	add	w9, w9, #1
	and	w9, w9, #0xfffffffe
Lloh209:
	adrp	x10, _mmVIEWPORT_SIZE@GOTPAGE
Lloh210:
	ldr	x10, [x10, _mmVIEWPORT_SIZE@GOTPAGEOFF]
Lloh211:
	ldr	x10, [x10]
	ldr	x11, [x23]
	add	x0, x11, x10
	orr	w1, w9, w8, lsl #16
	bl	_WREG32
Lloh212:
	adrp	x8, _mmMASTER_UPDATE_MODE@GOTPAGE
Lloh213:
	ldr	x8, [x8, _mmMASTER_UPDATE_MODE@GOTPAGEOFF]
Lloh214:
	ldr	x8, [x8]
	ldr	x9, [x23]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
	cbz	x27, LBB0_37
; %bb.33:
	cbnz	w21, LBB0_37
; %bb.34:
	ldr	x8, [x22]
	ldr	x8, [x8]
	cmp	x8, x27
	b.eq	LBB0_37
; %bb.35:
	ldr	x8, [x27, #16]
	ldr	x0, [x8]
	bl	_gem_to_amdgpu_bo
	mov	x19, x0
	mov	w1, #1
	bl	_amdgpu_bo_reserve
	mov	x24, x0
	cmp	w0, #0
	cset	w0, ne
	bl	_unlikely
	cbnz	x0, LBB0_39
; %bb.36:
	mov	x0, x19
	bl	_amdgpu_bo_unpin
	mov	x0, x19
	bl	_amdgpu_bo_unreserve
LBB0_37:
	mov	x0, x26
	bl	_dce_v10_0_bandwidth_update
LBB0_38:
	mov	w24, #0
LBB0_39:
	mov	x0, x24
	ldp	x29, x30, [sp, #144]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #128]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #112]            ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #96]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #80]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #64]             ; 16-byte Folded Reload
	add	sp, sp, #160
	ret
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpAdd	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpAdd	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpAdd	Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGot	Lloh84, Lloh85
	.loh AdrpLdrGot	Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.loh AdrpLdrGotLdr	Lloh112, Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGot	Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh127, Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh132, Lloh133, Lloh134
	.loh AdrpLdrGot	Lloh130, Lloh131
	.loh AdrpLdrGot	Lloh135, Lloh136
	.loh AdrpLdrGotLdr	Lloh177, Lloh178, Lloh179
	.loh AdrpLdrGotLdr	Lloh174, Lloh175, Lloh176
	.loh AdrpLdrGot	Lloh172, Lloh173
	.loh AdrpLdrGotLdr	Lloh169, Lloh170, Lloh171
	.loh AdrpLdrGotLdr	Lloh166, Lloh167, Lloh168
	.loh AdrpLdrGotLdr	Lloh163, Lloh164, Lloh165
	.loh AdrpLdrGotLdr	Lloh160, Lloh161, Lloh162
	.loh AdrpLdrGotLdr	Lloh157, Lloh158, Lloh159
	.loh AdrpLdrGotLdr	Lloh154, Lloh155, Lloh156
	.loh AdrpLdrGotLdr	Lloh151, Lloh152, Lloh153
	.loh AdrpLdrGotLdr	Lloh148, Lloh149, Lloh150
	.loh AdrpLdrGotLdr	Lloh145, Lloh146, Lloh147
	.loh AdrpLdrGotLdr	Lloh142, Lloh143, Lloh144
	.loh AdrpLdrGot	Lloh140, Lloh141
	.loh AdrpLdrGotLdr	Lloh137, Lloh138, Lloh139
	.loh AdrpAdd	Lloh180, Lloh181
	.loh AdrpLdrGotLdr	Lloh212, Lloh213, Lloh214
	.loh AdrpLdrGotLdr	Lloh209, Lloh210, Lloh211
	.loh AdrpLdrGotLdr	Lloh206, Lloh207, Lloh208
	.loh AdrpLdrGotLdr	Lloh203, Lloh204, Lloh205
	.loh AdrpLdrGotLdr	Lloh200, Lloh201, Lloh202
	.loh AdrpLdrGotLdr	Lloh197, Lloh198, Lloh199
	.loh AdrpLdrGotLdr	Lloh194, Lloh195, Lloh196
	.loh AdrpLdrGotLdr	Lloh191, Lloh192, Lloh193
	.loh AdrpLdrGotLdr	Lloh188, Lloh189, Lloh190
	.loh AdrpLdrGotLdr	Lloh185, Lloh186, Lloh187
	.loh AdrpLdrGotLdr	Lloh182, Lloh183, Lloh184
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_6-LBB0_6)>>2
	.byte	(LBB0_11-LBB0_6)>>2
	.byte	(LBB0_12-LBB0_6)>>2
	.byte	(LBB0_13-LBB0_6)>>2
	.byte	(LBB0_14-LBB0_6)>>2
	.byte	(LBB0_19-LBB0_6)>>2
	.byte	(LBB0_21-LBB0_6)>>2
	.byte	(LBB0_15-LBB0_6)>>2
	.byte	(LBB0_16-LBB0_6)>>2
	.byte	(LBB0_15-LBB0_6)>>2
	.byte	(LBB0_16-LBB0_6)>>2
	.byte	(LBB0_6-LBB0_6)>>2
	.byte	(LBB0_11-LBB0_6)>>2
	.byte	(LBB0_12-LBB0_6)>>2
	.byte	(LBB0_13-LBB0_6)>>2
	.byte	(LBB0_14-LBB0_6)>>2
                                        ; -- End function
	.comm	_GRPH_SWAP_CNTL,4,2             ; @GRPH_SWAP_CNTL
	.comm	_GRPH_ENDIAN_SWAP,4,2           ; @GRPH_ENDIAN_SWAP
	.comm	_ENDIAN_NONE,4,2                ; @ENDIAN_NONE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"No FB bound\n"

	.comm	_AMDGPU_GEM_DOMAIN_VRAM,4,2     ; @AMDGPU_GEM_DOMAIN_VRAM
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_PIPE_CONFIG,4,2                ; @PIPE_CONFIG
	.comm	_GRPH_CONTROL,4,2               ; @GRPH_CONTROL
	.comm	_GRPH_DEPTH,4,2                 ; @GRPH_DEPTH
	.comm	_GRPH_FORMAT,4,2                ; @GRPH_FORMAT
	.comm	_GRPH_RED_CROSSBAR,4,2          ; @GRPH_RED_CROSSBAR
	.comm	_GRPH_BLUE_CROSSBAR,4,2         ; @GRPH_BLUE_CROSSBAR
l_.str.1:                               ; @.str.1
	.asciz	"Unsupported screen format %s\n"

	.comm	_ARRAY_MODE,4,2                 ; @ARRAY_MODE
	.comm	_ARRAY_2D_TILED_THIN1,4,2       ; @ARRAY_2D_TILED_THIN1
	.comm	_BANK_WIDTH,4,2                 ; @BANK_WIDTH
	.comm	_BANK_HEIGHT,4,2                ; @BANK_HEIGHT
	.comm	_MACRO_TILE_ASPECT,4,2          ; @MACRO_TILE_ASPECT
	.comm	_TILE_SPLIT,4,2                 ; @TILE_SPLIT
	.comm	_NUM_BANKS,4,2                  ; @NUM_BANKS
	.comm	_GRPH_NUM_BANKS,4,2             ; @GRPH_NUM_BANKS
	.comm	_GRPH_ARRAY_MODE,4,2            ; @GRPH_ARRAY_MODE
	.comm	_GRPH_TILE_SPLIT,4,2            ; @GRPH_TILE_SPLIT
	.comm	_GRPH_BANK_WIDTH,4,2            ; @GRPH_BANK_WIDTH
	.comm	_GRPH_BANK_HEIGHT,4,2           ; @GRPH_BANK_HEIGHT
	.comm	_GRPH_MACRO_TILE_ASPECT,4,2     ; @GRPH_MACRO_TILE_ASPECT
	.comm	_GRPH_MICRO_TILE_MODE,4,2       ; @GRPH_MICRO_TILE_MODE
	.comm	_ADDR_SURF_MICRO_TILING_DISPLAY,4,2 ; @ADDR_SURF_MICRO_TILING_DISPLAY
	.comm	_ARRAY_1D_TILED_THIN1,4,2       ; @ARRAY_1D_TILED_THIN1
	.comm	_GRPH_PIPE_CONFIG,4,2           ; @GRPH_PIPE_CONFIG
	.comm	_mmGRPH_FLIP_CONTROL,8,3        ; @mmGRPH_FLIP_CONTROL
	.comm	_GRPH_FLIP_CONTROL,4,2          ; @GRPH_FLIP_CONTROL
	.comm	_GRPH_SURFACE_UPDATE_H_RETRACE_EN,4,2 ; @GRPH_SURFACE_UPDATE_H_RETRACE_EN
	.comm	_mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH,8,3 ; @mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
	.comm	_mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH,8,3 ; @mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH
	.comm	_mmGRPH_PRIMARY_SURFACE_ADDRESS,8,3 ; @mmGRPH_PRIMARY_SURFACE_ADDRESS
	.comm	_GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK,4,2 ; @GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK
	.comm	_mmGRPH_SECONDARY_SURFACE_ADDRESS,8,3 ; @mmGRPH_SECONDARY_SURFACE_ADDRESS
	.comm	_GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK,4,2 ; @GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK
	.comm	_mmGRPH_CONTROL,8,3             ; @mmGRPH_CONTROL
	.comm	_mmGRPH_SWAP_CNTL,8,3           ; @mmGRPH_SWAP_CNTL
	.comm	_mmGRPH_LUT_10BIT_BYPASS,8,3    ; @mmGRPH_LUT_10BIT_BYPASS
	.comm	_GRPH_LUT_10BIT_BYPASS,4,2      ; @GRPH_LUT_10BIT_BYPASS
	.comm	_GRPH_LUT_10BIT_BYPASS_EN,4,2   ; @GRPH_LUT_10BIT_BYPASS_EN
l_.str.2:                               ; @.str.2
	.asciz	"Bypassing hardware LUT due to 10 bit fb scanout.\n"

	.comm	_mmGRPH_SURFACE_OFFSET_X,8,3    ; @mmGRPH_SURFACE_OFFSET_X
	.comm	_mmGRPH_SURFACE_OFFSET_Y,8,3    ; @mmGRPH_SURFACE_OFFSET_Y
	.comm	_mmGRPH_X_START,8,3             ; @mmGRPH_X_START
	.comm	_mmGRPH_Y_START,8,3             ; @mmGRPH_Y_START
	.comm	_mmGRPH_X_END,8,3               ; @mmGRPH_X_END
	.comm	_mmGRPH_Y_END,8,3               ; @mmGRPH_Y_END
	.comm	_mmGRPH_PITCH,8,3               ; @mmGRPH_PITCH
	.comm	_mmLB_DESKTOP_HEIGHT,8,3        ; @mmLB_DESKTOP_HEIGHT
	.comm	_mmVIEWPORT_START,8,3           ; @mmVIEWPORT_START
	.comm	_mmVIEWPORT_SIZE,8,3            ; @mmVIEWPORT_SIZE
	.comm	_mmMASTER_UPDATE_MODE,8,3       ; @mmMASTER_UPDATE_MODE
	.comm	_ENDIAN_8IN16,4,2               ; @ENDIAN_8IN16
	.comm	_ENDIAN_8IN32,4,2               ; @ENDIAN_8IN32
	.no_dead_strip	_dce_v10_0_crtc_do_set_base
.subsections_via_symbols
