	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function smu7_init_dpm_defaults
_smu7_init_dpm_defaults:                ## @smu7_init_dpm_defaults
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	88(%rdi), %rbx
	movq	72(%rdi), %rax
	movq	%rax, -64(%rbp)                 ## 8-byte Spill
	movq	80(%rdi), %rax
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
	movabsq	$42949672960, %rax              ## imm = 0xA00000000
	movq	%rax, (%rbx)
	movl	$300, 8(%rbx)                   ## imm = 0x12C
	movq	_SMU7_STATICSCREENTHRESHOLD_DFLT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 228(%rbx)
	movq	_SMU7_STATICSCREENTHRESHOLDUNIT_DFLT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 224(%rbx)
	movq	_SMU7_VOTINGRIGHTSCLIENTS_DFLT0@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	216(%rbx), %rcx
	movl	%eax, (%rcx)
	movq	_SMU7_VOTINGRIGHTSCLIENTS_DFLT1@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 4(%rcx)
	movq	_SMU7_VOTINGRIGHTSCLIENTS_DFLT2@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 8(%rcx)
	movq	_SMU7_VOTINGRIGHTSCLIENTS_DFLT3@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 12(%rcx)
	movq	_SMU7_VOTINGRIGHTSCLIENTS_DFLT4@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 16(%rcx)
	movq	_SMU7_VOTINGRIGHTSCLIENTS_DFLT5@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 20(%rcx)
	movq	_SMU7_VOTINGRIGHTSCLIENTS_DFLT6@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 24(%rcx)
	movq	_SMU7_VOTINGRIGHTSCLIENTS_DFLT7@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 28(%rcx)
	movl	(%rdi), %eax
	movq	_PP_MCLK_DPM_MASK@GOTPCREL(%rip), %rcx
	xorl	%edx, %edx
	movl	(%rcx), %ecx
	andl	%eax, %ecx
	sete	%dl
	movl	%edx, 12(%rbx)
	movq	_PP_SCLK_DPM_MASK@GOTPCREL(%rip), %rcx
	xorl	%edx, %edx
	movl	(%rcx), %ecx
	andl	%eax, %ecx
	sete	%dl
	movl	%edx, 16(%rbx)
	movq	_PP_PCIE_DPM_MASK@GOTPCREL(%rip), %rcx
	xorl	%edx, %edx
	movl	(%rcx), %ecx
	andl	%eax, %ecx
	sete	%dl
	movl	%edx, 20(%rbx)
	movq	_SMU7_VOLTAGE_CONTROL_NONE@GOTPCREL(%rip), %r12
	movq	(%r12), %rcx
	movq	%rcx, 136(%rbx)
	movq	%rcx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movabsq	$4294967297, %rcx               ## imm = 0x100000001
	movq	%rcx, 40(%rbx)
	movq	_PP_PCIEGenInvalid@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, 208(%rbx)
	movq	_PP_ULV_MASK@GOTPCREL(%rip), %rcx
	xorl	%edx, %edx
	andl	(%rcx), %eax
	setne	%dl
	movl	%edx, 48(%rbx)
	movabsq	$429496729601, %rax             ## imm = 0x6400000001
	movq	%rax, 160(%rbx)
	movq	$0, 200(%rbx)
	movq	_SMU7_SCLK_TARGETACTIVITY_DFLT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, 192(%rbx)
	movq	%rax, 168(%rbx)
	movq	$0, 184(%rbx)
	movq	_SMU7_MCLK_TARGETACTIVITY_DFLT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 176(%rbx)
	movq	_PP_SMC_POWER_PROFILE_FULLSCREEN3D@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	8(%rdi), %rax
	movb	(%rax,%rdx,4), %cl
	movl	$1, %esi
	shll	%cl, %esi
	movq	32(%rdi), %rax
	movl	%esi, 4(%rdi)
	movq	%rdx, 16(%rdi)
	movq	%rdx, 24(%rdi)
	movq	_CHIP_POLARIS12@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_2
## %bb.1:
	cmpq	$0, 64(%r15)
	je	LBB0_3
LBB0_2:
	movl	$0, -44(%rbp)
	movq	_VOLTAGE_TYPE_VDDC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-72(%rbp), %rdx
	leaq	-68(%rbp), %rcx
	leaq	-44(%rbp), %r8
	movq	%r15, %rdi
	callq	_atomctrl_get_svi2_info
	movl	-44(%rbp), %eax
	movl	%eax, %ecx
	shrl	$4, %ecx
	shrl	$6, %eax
	andl	$1, %eax
	andl	$2, %ecx
	orl	%eax, %ecx
	movl	%ecx, 52(%rbx)
	movq	32(%r15), %rax
LBB0_6:
	movq	_CHIP_HAWAII@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	movl	$94500, %eax                    ## imm = 0x17124
	movl	$99500, %ecx                    ## imm = 0x184AC
	cmovel	%eax, %ecx
	movl	$95000, %eax                    ## imm = 0x17318
	movl	$100000, %edx                   ## imm = 0x186A0
	cmovel	%eax, %edx
	movl	%ecx, 144(%rbx)
	movl	%edx, 148(%rbx)
	movl	$104000, 152(%rbx)              ## imm = 0x19640
	movl	$100, 56(%rbx)
	movq	_VOLTAGE_TYPE_VDDC@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	_VOLTAGE_OBJ_SVID2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_atomctrl_is_voltage_controlled_by_gpio_v3
	testq	%rax, %rax
	je	LBB0_8
## %bb.7:
	movq	_SMU7_VOLTAGE_CONTROL_BY_SVID2@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_8:
	movl	(%r14), %esi
	movq	_VOLTAGE_OBJ_GPIO_LUT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_atomctrl_is_voltage_controlled_by_gpio_v3
	testq	%rax, %rax
	je	LBB0_11
## %bb.9:
	movq	_SMU7_VOLTAGE_CONTROL_BY_GPIO@GOTPCREL(%rip), %rax
LBB0_10:
	movq	(%rax), %rax
	movq	%rax, 136(%rbx)
LBB0_11:
	movl	56(%r15), %edi
	movq	_PHM_PlatformCaps_ControlVDDGFX@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	callq	_phm_cap_enabled
	testq	%rax, %rax
	je	LBB0_14
## %bb.12:
	movq	_VOLTAGE_TYPE_VDDGFX@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_VOLTAGE_OBJ_SVID2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_atomctrl_is_voltage_controlled_by_gpio_v3
	testq	%rax, %rax
	je	LBB0_14
## %bb.13:
	movq	_SMU7_VOLTAGE_CONTROL_BY_SVID2@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 64(%rbx)
LBB0_14:
	movl	56(%r15), %edi
	movq	_PHM_PlatformCaps_EnableMVDDControl@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_phm_cap_enabled
	testq	%rax, %rax
	je	LBB0_20
## %bb.15:
	movq	%r12, %r14
	movq	_VOLTAGE_TYPE_MVDDC@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	_VOLTAGE_OBJ_GPIO_LUT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_atomctrl_is_voltage_controlled_by_gpio_v3
	testq	%rax, %rax
	je	LBB0_17
## %bb.16:
	movq	_SMU7_VOLTAGE_CONTROL_BY_GPIO@GOTPCREL(%rip), %rax
	movq	%r14, %r12
	jmp	LBB0_19
LBB0_17:
	movl	(%r12), %esi
	movq	_VOLTAGE_OBJ_SVID2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_atomctrl_is_voltage_controlled_by_gpio_v3
	testq	%rax, %rax
	movq	%r14, %r12
	je	LBB0_20
## %bb.18:
	movq	_SMU7_VOLTAGE_CONTROL_BY_SVID2@GOTPCREL(%rip), %rax
LBB0_19:
	movq	(%rax), %rax
	movq	%rax, 32(%rbx)
LBB0_20:
	movq	(%r12), %rax
	cmpq	64(%rbx), %rax
	jne	LBB0_22
## %bb.21:
	movl	56(%r15), %edi
	movl	(%r13), %esi
	callq	_phm_cap_unset
LBB0_22:
	movl	56(%r15), %edi
	movq	_PHM_PlatformCaps_ControlVDDCI@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	callq	_phm_cap_enabled
	testq	%rax, %rax
	je	LBB0_28
## %bb.23:
	movq	%r12, %r14
	movq	_VOLTAGE_TYPE_VDDCI@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	_VOLTAGE_OBJ_GPIO_LUT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_atomctrl_is_voltage_controlled_by_gpio_v3
	testq	%rax, %rax
	je	LBB0_25
## %bb.24:
	movq	_SMU7_VOLTAGE_CONTROL_BY_GPIO@GOTPCREL(%rip), %rax
	movq	%r14, %r12
	jmp	LBB0_27
LBB0_25:
	movl	(%r12), %esi
	movq	_VOLTAGE_OBJ_SVID2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_atomctrl_is_voltage_controlled_by_gpio_v3
	testq	%rax, %rax
	movq	%r14, %r12
	je	LBB0_28
## %bb.26:
	movq	_SMU7_VOLTAGE_CONTROL_BY_SVID2@GOTPCREL(%rip), %rax
LBB0_27:
	movq	(%rax), %rax
	movq	%rax, 24(%rbx)
LBB0_28:
	movq	(%r12), %rax
	cmpq	%rax, 32(%rbx)
	jne	LBB0_30
## %bb.29:
	movl	56(%r15), %edi
	movq	_PHM_PlatformCaps_EnableMVDDControl@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_phm_cap_unset
	movq	(%r12), %rax
LBB0_30:
	cmpq	%rax, 24(%rbx)
	jne	LBB0_32
## %bb.31:
	movl	56(%r15), %edi
	movl	(%r13), %esi
	callq	_phm_cap_unset
LBB0_32:
	movq	48(%r15), %rax
	movq	_PP_TABLE_V0@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_36
## %bb.33:
	movq	_PP_CLOCK_STRETCH_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r15)
	je	LBB0_36
## %bb.34:
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rax
	cmpq	$0, (%rax)
	je	LBB0_36
## %bb.35:
	movl	56(%r15), %edi
	movq	_PHM_PlatformCaps_ClockStretcher@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_phm_cap_set
LBB0_36:
	movq	_PP_PCIEGen1@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 128(%rbx)
	movq	_PP_PCIEGen3@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, 120(%rbx)
	movq	%rax, 112(%rbx)
	movq	%rcx, 104(%rbx)
	movq	$0, 96(%rbx)
	movl	$16, 88(%rbx)
	movq	$0, 80(%rbx)
	movl	$16, 72(%rbx)
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	movl	(%rbx), %eax
	movq	_AMD_PG_SUPPORT_UVD@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_38
## %bb.37:
	movl	56(%r15), %edi
	movq	_PHM_PlatformCaps_UVDPowerGating@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_phm_cap_set
	movl	(%rbx), %eax
LBB0_38:
	movq	_AMD_PG_SUPPORT_VCE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_40
## %bb.39:
	movl	56(%r15), %edi
	movq	_PHM_PlatformCaps_VCEPowerGating@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_phm_cap_set
LBB0_40:
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_3:
	movq	40(%r15), %rcx
	movq	_AMDGPU_FAMILY_CI@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_5
## %bb.4:
	movl	$1, 52(%rbx)
	jmp	LBB0_6
LBB0_5:
	movl	$0, 52(%rbx)
	jmp	LBB0_6
	.cfi_endproc
                                        ## -- End function
	.comm	_SMU7_STATICSCREENTHRESHOLD_DFLT,4,2 ## @SMU7_STATICSCREENTHRESHOLD_DFLT
	.comm	_SMU7_STATICSCREENTHRESHOLDUNIT_DFLT,4,2 ## @SMU7_STATICSCREENTHRESHOLDUNIT_DFLT
	.comm	_SMU7_VOTINGRIGHTSCLIENTS_DFLT0,4,2 ## @SMU7_VOTINGRIGHTSCLIENTS_DFLT0
	.comm	_SMU7_VOTINGRIGHTSCLIENTS_DFLT1,4,2 ## @SMU7_VOTINGRIGHTSCLIENTS_DFLT1
	.comm	_SMU7_VOTINGRIGHTSCLIENTS_DFLT2,4,2 ## @SMU7_VOTINGRIGHTSCLIENTS_DFLT2
	.comm	_SMU7_VOTINGRIGHTSCLIENTS_DFLT3,4,2 ## @SMU7_VOTINGRIGHTSCLIENTS_DFLT3
	.comm	_SMU7_VOTINGRIGHTSCLIENTS_DFLT4,4,2 ## @SMU7_VOTINGRIGHTSCLIENTS_DFLT4
	.comm	_SMU7_VOTINGRIGHTSCLIENTS_DFLT5,4,2 ## @SMU7_VOTINGRIGHTSCLIENTS_DFLT5
	.comm	_SMU7_VOTINGRIGHTSCLIENTS_DFLT6,4,2 ## @SMU7_VOTINGRIGHTSCLIENTS_DFLT6
	.comm	_SMU7_VOTINGRIGHTSCLIENTS_DFLT7,4,2 ## @SMU7_VOTINGRIGHTSCLIENTS_DFLT7
	.comm	_PP_MCLK_DPM_MASK,4,2           ## @PP_MCLK_DPM_MASK
	.comm	_PP_SCLK_DPM_MASK,4,2           ## @PP_SCLK_DPM_MASK
	.comm	_PP_PCIE_DPM_MASK,4,2           ## @PP_PCIE_DPM_MASK
	.comm	_SMU7_VOLTAGE_CONTROL_NONE,8,3  ## @SMU7_VOLTAGE_CONTROL_NONE
	.comm	_PP_PCIEGenInvalid,4,2          ## @PP_PCIEGenInvalid
	.comm	_PP_ULV_MASK,4,2                ## @PP_ULV_MASK
	.comm	_SMU7_SCLK_TARGETACTIVITY_DFLT,4,2 ## @SMU7_SCLK_TARGETACTIVITY_DFLT
	.comm	_SMU7_MCLK_TARGETACTIVITY_DFLT,4,2 ## @SMU7_MCLK_TARGETACTIVITY_DFLT
	.comm	_PP_SMC_POWER_PROFILE_FULLSCREEN3D,8,3 ## @PP_SMC_POWER_PROFILE_FULLSCREEN3D
	.comm	_CHIP_POLARIS12,8,3             ## @CHIP_POLARIS12
	.comm	_VOLTAGE_TYPE_VDDC,4,2          ## @VOLTAGE_TYPE_VDDC
	.comm	_AMDGPU_FAMILY_CI,8,3           ## @AMDGPU_FAMILY_CI
	.comm	_CHIP_HAWAII,8,3                ## @CHIP_HAWAII
	.comm	_VOLTAGE_OBJ_SVID2,4,2          ## @VOLTAGE_OBJ_SVID2
	.comm	_SMU7_VOLTAGE_CONTROL_BY_SVID2,8,3 ## @SMU7_VOLTAGE_CONTROL_BY_SVID2
	.comm	_VOLTAGE_OBJ_GPIO_LUT,4,2       ## @VOLTAGE_OBJ_GPIO_LUT
	.comm	_SMU7_VOLTAGE_CONTROL_BY_GPIO,8,3 ## @SMU7_VOLTAGE_CONTROL_BY_GPIO
	.comm	_PHM_PlatformCaps_ControlVDDGFX,4,2 ## @PHM_PlatformCaps_ControlVDDGFX
	.comm	_VOLTAGE_TYPE_VDDGFX,4,2        ## @VOLTAGE_TYPE_VDDGFX
	.comm	_PHM_PlatformCaps_EnableMVDDControl,4,2 ## @PHM_PlatformCaps_EnableMVDDControl
	.comm	_VOLTAGE_TYPE_MVDDC,4,2         ## @VOLTAGE_TYPE_MVDDC
	.comm	_PHM_PlatformCaps_ControlVDDCI,4,2 ## @PHM_PlatformCaps_ControlVDDCI
	.comm	_VOLTAGE_TYPE_VDDCI,4,2         ## @VOLTAGE_TYPE_VDDCI
	.comm	_PP_TABLE_V0,8,3                ## @PP_TABLE_V0
	.comm	_PP_CLOCK_STRETCH_MASK,4,2      ## @PP_CLOCK_STRETCH_MASK
	.comm	_PHM_PlatformCaps_ClockStretcher,4,2 ## @PHM_PlatformCaps_ClockStretcher
	.comm	_PP_PCIEGen1,8,3                ## @PP_PCIEGen1
	.comm	_PP_PCIEGen3,8,3                ## @PP_PCIEGen3
	.comm	_AMD_PG_SUPPORT_UVD,4,2         ## @AMD_PG_SUPPORT_UVD
	.comm	_PHM_PlatformCaps_UVDPowerGating,4,2 ## @PHM_PlatformCaps_UVDPowerGating
	.comm	_AMD_PG_SUPPORT_VCE,4,2         ## @AMD_PG_SUPPORT_VCE
	.comm	_PHM_PlatformCaps_VCEPowerGating,4,2 ## @PHM_PlatformCaps_VCEPowerGating
	.no_dead_strip	_smu7_init_dpm_defaults
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3                               ; -- Begin function smu7_init_dpm_defaults
lCPI0_0:
	.long	0                               ; 0x0
	.long	10                              ; 0xa
lCPI0_1:
	.long	100                             ; 0x64
	.long	1                               ; 0x1
lCPI0_2:
	.long	99500                           ; 0x184ac
	.long	100000                          ; 0x186a0
lCPI0_3:
	.long	94500                           ; 0x17124
	.long	95000                           ; 0x17318
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	2
_smu7_init_dpm_defaults:                ; @smu7_init_dpm_defaults
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldp	x22, x21, [x0, #80]
	ldr	x20, [x0, #72]
Lloh0:
	adrp	x8, lCPI0_0@PAGE
Lloh1:
	ldr	d0, [x8, lCPI0_0@PAGEOFF]
	str	d0, [x21]
	mov	w8, #300
	str	w8, [x21, #8]
Lloh2:
	adrp	x8, _SMU7_STATICSCREENTHRESHOLD_DFLT@GOTPAGE
Lloh3:
	ldr	x8, [x8, _SMU7_STATICSCREENTHRESHOLD_DFLT@GOTPAGEOFF]
Lloh4:
	adrp	x9, _SMU7_STATICSCREENTHRESHOLDUNIT_DFLT@GOTPAGE
Lloh5:
	ldr	x9, [x9, _SMU7_STATICSCREENTHRESHOLDUNIT_DFLT@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
Lloh7:
	ldr	w9, [x9]
	stp	w9, w8, [x21, #224]
Lloh8:
	adrp	x8, _SMU7_VOTINGRIGHTSCLIENTS_DFLT0@GOTPAGE
Lloh9:
	ldr	x8, [x8, _SMU7_VOTINGRIGHTSCLIENTS_DFLT0@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	ldr	x9, [x21, #216]
	str	w8, [x9]
Lloh11:
	adrp	x8, _SMU7_VOTINGRIGHTSCLIENTS_DFLT1@GOTPAGE
Lloh12:
	ldr	x8, [x8, _SMU7_VOTINGRIGHTSCLIENTS_DFLT1@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
Lloh14:
	adrp	x10, _SMU7_VOTINGRIGHTSCLIENTS_DFLT2@GOTPAGE
Lloh15:
	ldr	x10, [x10, _SMU7_VOTINGRIGHTSCLIENTS_DFLT2@GOTPAGEOFF]
Lloh16:
	ldr	w10, [x10]
Lloh17:
	adrp	x11, _SMU7_VOTINGRIGHTSCLIENTS_DFLT3@GOTPAGE
Lloh18:
	ldr	x11, [x11, _SMU7_VOTINGRIGHTSCLIENTS_DFLT3@GOTPAGEOFF]
	stp	w8, w10, [x9, #4]
Lloh19:
	ldr	w8, [x11]
Lloh20:
	adrp	x10, _SMU7_VOTINGRIGHTSCLIENTS_DFLT4@GOTPAGE
Lloh21:
	ldr	x10, [x10, _SMU7_VOTINGRIGHTSCLIENTS_DFLT4@GOTPAGEOFF]
Lloh22:
	ldr	w10, [x10]
	stp	w8, w10, [x9, #12]
Lloh23:
	adrp	x8, _SMU7_VOTINGRIGHTSCLIENTS_DFLT5@GOTPAGE
Lloh24:
	ldr	x8, [x8, _SMU7_VOTINGRIGHTSCLIENTS_DFLT5@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
Lloh26:
	adrp	x10, _SMU7_VOTINGRIGHTSCLIENTS_DFLT6@GOTPAGE
Lloh27:
	ldr	x10, [x10, _SMU7_VOTINGRIGHTSCLIENTS_DFLT6@GOTPAGEOFF]
Lloh28:
	ldr	w10, [x10]
	stp	w8, w10, [x9, #20]
Lloh29:
	adrp	x8, _SMU7_VOTINGRIGHTSCLIENTS_DFLT7@GOTPAGE
Lloh30:
	ldr	x8, [x8, _SMU7_VOTINGRIGHTSCLIENTS_DFLT7@GOTPAGEOFF]
Lloh31:
	ldr	w8, [x8]
	str	w8, [x9, #28]
	ldr	w8, [x0]
Lloh32:
	adrp	x9, _PP_MCLK_DPM_MASK@GOTPAGE
Lloh33:
	ldr	x9, [x9, _PP_MCLK_DPM_MASK@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	tst	w9, w8
	cset	w9, eq
Lloh35:
	adrp	x10, _PP_SCLK_DPM_MASK@GOTPAGE
Lloh36:
	ldr	x10, [x10, _PP_SCLK_DPM_MASK@GOTPAGEOFF]
Lloh37:
	ldr	w10, [x10]
	tst	w10, w8
	cset	w10, eq
	stp	w9, w10, [x21, #12]
Lloh38:
	adrp	x9, _PP_PCIE_DPM_MASK@GOTPAGE
Lloh39:
	ldr	x9, [x9, _PP_PCIE_DPM_MASK@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
	tst	w9, w8
	cset	w9, eq
	str	w9, [x21, #20]
Lloh41:
	adrp	x23, _SMU7_VOLTAGE_CONTROL_NONE@GOTPAGE
Lloh42:
	ldr	x23, [x23, _SMU7_VOLTAGE_CONTROL_NONE@GOTPAGEOFF]
	ldr	x9, [x23]
	str	x9, [x21, #136]
	stp	x9, x9, [x21, #24]
	movi.2s	v0, #1
	str	d0, [x21, #40]
Lloh43:
	adrp	x9, _PP_PCIEGenInvalid@GOTPAGE
Lloh44:
	ldr	x9, [x9, _PP_PCIEGenInvalid@GOTPAGEOFF]
Lloh45:
	ldr	w9, [x9]
	str	w9, [x21, #208]
Lloh46:
	adrp	x9, _PP_ULV_MASK@GOTPAGE
Lloh47:
	ldr	x9, [x9, _PP_ULV_MASK@GOTPAGEOFF]
Lloh48:
	ldr	w9, [x9]
	tst	w9, w8
	cset	w8, ne
	str	w8, [x21, #48]
	mov	w8, #1
	str	w8, [x21, #160]
Lloh49:
	adrp	x9, _SMU7_SCLK_TARGETACTIVITY_DFLT@GOTPAGE
Lloh50:
	ldr	x9, [x9, _SMU7_SCLK_TARGETACTIVITY_DFLT@GOTPAGEOFF]
	str	xzr, [x21, #200]
Lloh51:
	ldr	w9, [x9]
	str	w9, [x21, #192]
Lloh52:
	adrp	x9, lCPI0_1@PAGE
Lloh53:
	ldr	d0, [x9, lCPI0_1@PAGEOFF]
	stur	d0, [x21, #164]
	mov	w9, #100
Lloh54:
	adrp	x10, _SMU7_MCLK_TARGETACTIVITY_DFLT@GOTPAGE
Lloh55:
	ldr	x10, [x10, _SMU7_MCLK_TARGETACTIVITY_DFLT@GOTPAGEOFF]
Lloh56:
	ldr	w10, [x10]
	stp	w9, w10, [x21, #172]
	ldr	x9, [x0, #8]
Lloh57:
	adrp	x10, _PP_SMC_POWER_PROFILE_FULLSCREEN3D@GOTPAGE
Lloh58:
	ldr	x10, [x10, _PP_SMC_POWER_PROFILE_FULLSCREEN3D@GOTPAGEOFF]
Lloh59:
	ldr	x10, [x10]
	ldr	w9, [x9, x10, lsl #2]
	str	xzr, [x21, #184]
	lsl	w8, w8, w9
	str	w8, [x0, #4]
	stp	x10, x10, [x0, #16]
	ldr	x8, [x0, #32]
Lloh60:
	adrp	x9, _CHIP_POLARIS12@GOTPAGE
Lloh61:
	ldr	x9, [x9, _CHIP_POLARIS12@GOTPAGEOFF]
Lloh62:
	ldr	x9, [x9]
Lloh63:
	adrp	x26, _VOLTAGE_TYPE_VDDC@GOTPAGE
Lloh64:
	ldr	x26, [x26, _VOLTAGE_TYPE_VDDC@GOTPAGEOFF]
	cmp	x8, x9
	b.eq	LBB0_2
; %bb.1:
	ldr	x9, [x19, #64]
	cbz	x9, LBB0_37
LBB0_2:
	str	wzr, [sp, #4]
	ldr	w1, [x26]
	add	x2, sp, #12
	add	x3, sp, #8
	add	x4, sp, #4
	mov	x0, x19
	bl	_atomctrl_get_svi2_info
	ldr	w8, [sp, #4]
	lsr	w9, w8, #4
	and	w9, w9, #0x2
	bfxil	w9, w8, #6, #1
	str	w9, [x21, #52]
	ldr	x8, [x19, #32]
LBB0_3:
Lloh65:
	adrp	x9, _CHIP_HAWAII@GOTPAGE
Lloh66:
	ldr	x9, [x9, _CHIP_HAWAII@GOTPAGEOFF]
Lloh67:
	ldr	x9, [x9]
	cmp	x8, x9
	cset	w8, eq
	dup.2s	v0, w8
	shl.2s	v0, v0, #31
	cmlt.2s	v0, v0, #0
Lloh68:
	adrp	x8, lCPI0_2@PAGE
Lloh69:
	ldr	d1, [x8, lCPI0_2@PAGEOFF]
Lloh70:
	adrp	x8, lCPI0_3@PAGE
Lloh71:
	ldr	d2, [x8, lCPI0_3@PAGEOFF]
	bsl.8b	v0, v2, v1
	str	d0, [x21, #144]
	mov	w8, #38464
	movk	w8, #1, lsl #16
	str	w8, [x21, #152]
	mov	w8, #100
	str	w8, [x21, #56]
	ldr	w1, [x26]
Lloh72:
	adrp	x24, _VOLTAGE_OBJ_SVID2@GOTPAGE
Lloh73:
	ldr	x24, [x24, _VOLTAGE_OBJ_SVID2@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	x0, x19
	bl	_atomctrl_is_voltage_controlled_by_gpio_v3
Lloh74:
	adrp	x28, _SMU7_VOLTAGE_CONTROL_BY_SVID2@GOTPAGE
Lloh75:
	ldr	x28, [x28, _SMU7_VOLTAGE_CONTROL_BY_SVID2@GOTPAGEOFF]
Lloh76:
	adrp	x25, _VOLTAGE_OBJ_GPIO_LUT@GOTPAGE
Lloh77:
	ldr	x25, [x25, _VOLTAGE_OBJ_GPIO_LUT@GOTPAGEOFF]
	mov	x8, x28
	cbnz	x0, LBB0_6
; %bb.4:
	ldr	w1, [x26]
	ldr	w2, [x25]
	mov	x0, x19
	bl	_atomctrl_is_voltage_controlled_by_gpio_v3
	cbz	x0, LBB0_7
; %bb.5:
Lloh78:
	adrp	x8, _SMU7_VOLTAGE_CONTROL_BY_GPIO@GOTPAGE
Lloh79:
	ldr	x8, [x8, _SMU7_VOLTAGE_CONTROL_BY_GPIO@GOTPAGEOFF]
LBB0_6:
	ldr	x8, [x8]
	str	x8, [x21, #136]
LBB0_7:
	ldr	w0, [x19, #56]
Lloh80:
	adrp	x27, _PHM_PlatformCaps_ControlVDDGFX@GOTPAGE
Lloh81:
	ldr	x27, [x27, _PHM_PlatformCaps_ControlVDDGFX@GOTPAGEOFF]
	ldr	w1, [x27]
	bl	_phm_cap_enabled
	cbz	x0, LBB0_10
; %bb.8:
Lloh82:
	adrp	x8, _VOLTAGE_TYPE_VDDGFX@GOTPAGE
Lloh83:
	ldr	x8, [x8, _VOLTAGE_TYPE_VDDGFX@GOTPAGEOFF]
Lloh84:
	ldr	w1, [x8]
	ldr	w2, [x24]
	mov	x0, x19
	bl	_atomctrl_is_voltage_controlled_by_gpio_v3
	cbz	x0, LBB0_10
; %bb.9:
	ldr	x8, [x28]
	str	x8, [x21, #64]
LBB0_10:
	ldr	w0, [x19, #56]
Lloh85:
	adrp	x26, _PHM_PlatformCaps_EnableMVDDControl@GOTPAGE
Lloh86:
	ldr	x26, [x26, _PHM_PlatformCaps_EnableMVDDControl@GOTPAGEOFF]
	ldr	w1, [x26]
	bl	_phm_cap_enabled
	cbz	x0, LBB0_16
; %bb.11:
Lloh87:
	adrp	x28, _VOLTAGE_TYPE_MVDDC@GOTPAGE
Lloh88:
	ldr	x28, [x28, _VOLTAGE_TYPE_MVDDC@GOTPAGEOFF]
	ldr	w1, [x28]
	ldr	w2, [x25]
	mov	x0, x19
	bl	_atomctrl_is_voltage_controlled_by_gpio_v3
	cbz	x0, LBB0_13
; %bb.12:
Lloh89:
	adrp	x8, _SMU7_VOLTAGE_CONTROL_BY_GPIO@GOTPAGE
Lloh90:
	ldr	x8, [x8, _SMU7_VOLTAGE_CONTROL_BY_GPIO@GOTPAGEOFF]
	b	LBB0_15
LBB0_13:
	ldr	w1, [x28]
	ldr	w2, [x24]
	mov	x0, x19
	bl	_atomctrl_is_voltage_controlled_by_gpio_v3
	cbz	x0, LBB0_16
; %bb.14:
Lloh91:
	adrp	x8, _SMU7_VOLTAGE_CONTROL_BY_SVID2@GOTPAGE
Lloh92:
	ldr	x8, [x8, _SMU7_VOLTAGE_CONTROL_BY_SVID2@GOTPAGEOFF]
LBB0_15:
	ldr	x8, [x8]
	str	x8, [x21, #32]
LBB0_16:
	ldr	x8, [x23]
	ldr	x9, [x21, #64]
	cmp	x8, x9
	b.ne	LBB0_18
; %bb.17:
	ldr	w0, [x19, #56]
	ldr	w1, [x27]
	bl	_phm_cap_unset
LBB0_18:
	ldr	w0, [x19, #56]
Lloh93:
	adrp	x27, _PHM_PlatformCaps_ControlVDDCI@GOTPAGE
Lloh94:
	ldr	x27, [x27, _PHM_PlatformCaps_ControlVDDCI@GOTPAGEOFF]
	ldr	w1, [x27]
	bl	_phm_cap_enabled
	cbz	x0, LBB0_24
; %bb.19:
Lloh95:
	adrp	x28, _VOLTAGE_TYPE_VDDCI@GOTPAGE
Lloh96:
	ldr	x28, [x28, _VOLTAGE_TYPE_VDDCI@GOTPAGEOFF]
	ldr	w1, [x28]
	ldr	w2, [x25]
	mov	x0, x19
	bl	_atomctrl_is_voltage_controlled_by_gpio_v3
	cbz	x0, LBB0_21
; %bb.20:
Lloh97:
	adrp	x8, _SMU7_VOLTAGE_CONTROL_BY_GPIO@GOTPAGE
Lloh98:
	ldr	x8, [x8, _SMU7_VOLTAGE_CONTROL_BY_GPIO@GOTPAGEOFF]
	b	LBB0_23
LBB0_21:
	ldr	w1, [x28]
	ldr	w2, [x24]
	mov	x0, x19
	bl	_atomctrl_is_voltage_controlled_by_gpio_v3
	cbz	x0, LBB0_24
; %bb.22:
Lloh99:
	adrp	x8, _SMU7_VOLTAGE_CONTROL_BY_SVID2@GOTPAGE
Lloh100:
	ldr	x8, [x8, _SMU7_VOLTAGE_CONTROL_BY_SVID2@GOTPAGEOFF]
LBB0_23:
	ldr	x8, [x8]
	str	x8, [x21, #24]
LBB0_24:
	ldr	x9, [x21, #32]
	ldr	x8, [x23]
	cmp	x9, x8
	b.ne	LBB0_26
; %bb.25:
	ldr	w0, [x19, #56]
	ldr	w1, [x26]
	bl	_phm_cap_unset
	ldr	x8, [x23]
LBB0_26:
	ldr	x9, [x21, #24]
	cmp	x9, x8
	b.ne	LBB0_28
; %bb.27:
	ldr	w0, [x19, #56]
	ldr	w1, [x27]
	bl	_phm_cap_unset
LBB0_28:
	ldr	x8, [x19, #48]
Lloh101:
	adrp	x9, _PP_TABLE_V0@GOTPAGE
Lloh102:
	ldr	x9, [x9, _PP_TABLE_V0@GOTPAGEOFF]
Lloh103:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_32
; %bb.29:
	ldr	w8, [x19]
Lloh104:
	adrp	x9, _PP_CLOCK_STRETCH_MASK@GOTPAGE
Lloh105:
	ldr	x9, [x9, _PP_CLOCK_STRETCH_MASK@GOTPAGEOFF]
Lloh106:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_32
; %bb.30:
	ldr	x8, [x22]
	ldr	x8, [x8]
	cbz	x8, LBB0_32
; %bb.31:
	ldr	w0, [x19, #56]
Lloh107:
	adrp	x8, _PHM_PlatformCaps_ClockStretcher@GOTPAGE
Lloh108:
	ldr	x8, [x8, _PHM_PlatformCaps_ClockStretcher@GOTPAGEOFF]
Lloh109:
	ldr	w1, [x8]
	bl	_phm_cap_set
LBB0_32:
Lloh110:
	adrp	x8, _PP_PCIEGen1@GOTPAGE
Lloh111:
	ldr	x8, [x8, _PP_PCIEGen1@GOTPAGEOFF]
Lloh112:
	ldr	x8, [x8]
	str	x8, [x21, #128]
Lloh113:
	adrp	x9, _PP_PCIEGen3@GOTPAGE
Lloh114:
	ldr	x9, [x9, _PP_PCIEGen3@GOTPAGEOFF]
Lloh115:
	ldr	x9, [x9]
	stp	x8, x9, [x21, #112]
	stp	xzr, x9, [x21, #96]
	mov	w8, #16
	str	w8, [x21, #88]
	str	xzr, [x21, #80]
	str	w8, [x21, #72]
	ldr	w8, [x20]
Lloh116:
	adrp	x9, _AMD_PG_SUPPORT_UVD@GOTPAGE
Lloh117:
	ldr	x9, [x9, _AMD_PG_SUPPORT_UVD@GOTPAGEOFF]
Lloh118:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_34
; %bb.33:
	ldr	w0, [x19, #56]
Lloh119:
	adrp	x8, _PHM_PlatformCaps_UVDPowerGating@GOTPAGE
Lloh120:
	ldr	x8, [x8, _PHM_PlatformCaps_UVDPowerGating@GOTPAGEOFF]
Lloh121:
	ldr	w1, [x8]
	bl	_phm_cap_set
	ldr	w8, [x20]
LBB0_34:
Lloh122:
	adrp	x9, _AMD_PG_SUPPORT_VCE@GOTPAGE
Lloh123:
	ldr	x9, [x9, _AMD_PG_SUPPORT_VCE@GOTPAGEOFF]
Lloh124:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_36
; %bb.35:
	ldr	w0, [x19, #56]
Lloh125:
	adrp	x8, _PHM_PlatformCaps_VCEPowerGating@GOTPAGE
Lloh126:
	ldr	x8, [x8, _PHM_PlatformCaps_VCEPowerGating@GOTPAGEOFF]
Lloh127:
	ldr	w1, [x8]
	bl	_phm_cap_set
LBB0_36:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
LBB0_37:
	ldr	x9, [x19, #40]
Lloh128:
	adrp	x10, _AMDGPU_FAMILY_CI@GOTPAGE
Lloh129:
	ldr	x10, [x10, _AMDGPU_FAMILY_CI@GOTPAGEOFF]
Lloh130:
	ldr	x10, [x10]
	cmp	x9, x10
	b.ne	LBB0_39
; %bb.38:
	mov	w9, #1
	str	w9, [x21, #52]
	b	LBB0_3
LBB0_39:
	str	wzr, [x21, #52]
	b	LBB0_3
	.loh AdrpLdrGot	Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdr	Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh6
	.loh AdrpLdr	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh76, Lloh77
	.loh AdrpLdrGot	Lloh74, Lloh75
	.loh AdrpLdrGot	Lloh72, Lloh73
	.loh AdrpLdr	Lloh70, Lloh71
	.loh AdrpAdrp	Lloh68, Lloh70
	.loh AdrpLdr	Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGot	Lloh78, Lloh79
	.loh AdrpLdrGot	Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGot	Lloh85, Lloh86
	.loh AdrpLdrGot	Lloh87, Lloh88
	.loh AdrpLdrGot	Lloh89, Lloh90
	.loh AdrpLdrGot	Lloh91, Lloh92
	.loh AdrpLdrGot	Lloh93, Lloh94
	.loh AdrpLdrGot	Lloh95, Lloh96
	.loh AdrpLdrGot	Lloh97, Lloh98
	.loh AdrpLdrGot	Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh128, Lloh129, Lloh130
	.cfi_endproc
                                        ; -- End function
	.comm	_SMU7_STATICSCREENTHRESHOLD_DFLT,4,2 ; @SMU7_STATICSCREENTHRESHOLD_DFLT
	.comm	_SMU7_STATICSCREENTHRESHOLDUNIT_DFLT,4,2 ; @SMU7_STATICSCREENTHRESHOLDUNIT_DFLT
	.comm	_SMU7_VOTINGRIGHTSCLIENTS_DFLT0,4,2 ; @SMU7_VOTINGRIGHTSCLIENTS_DFLT0
	.comm	_SMU7_VOTINGRIGHTSCLIENTS_DFLT1,4,2 ; @SMU7_VOTINGRIGHTSCLIENTS_DFLT1
	.comm	_SMU7_VOTINGRIGHTSCLIENTS_DFLT2,4,2 ; @SMU7_VOTINGRIGHTSCLIENTS_DFLT2
	.comm	_SMU7_VOTINGRIGHTSCLIENTS_DFLT3,4,2 ; @SMU7_VOTINGRIGHTSCLIENTS_DFLT3
	.comm	_SMU7_VOTINGRIGHTSCLIENTS_DFLT4,4,2 ; @SMU7_VOTINGRIGHTSCLIENTS_DFLT4
	.comm	_SMU7_VOTINGRIGHTSCLIENTS_DFLT5,4,2 ; @SMU7_VOTINGRIGHTSCLIENTS_DFLT5
	.comm	_SMU7_VOTINGRIGHTSCLIENTS_DFLT6,4,2 ; @SMU7_VOTINGRIGHTSCLIENTS_DFLT6
	.comm	_SMU7_VOTINGRIGHTSCLIENTS_DFLT7,4,2 ; @SMU7_VOTINGRIGHTSCLIENTS_DFLT7
	.comm	_PP_MCLK_DPM_MASK,4,2           ; @PP_MCLK_DPM_MASK
	.comm	_PP_SCLK_DPM_MASK,4,2           ; @PP_SCLK_DPM_MASK
	.comm	_PP_PCIE_DPM_MASK,4,2           ; @PP_PCIE_DPM_MASK
	.comm	_SMU7_VOLTAGE_CONTROL_NONE,8,3  ; @SMU7_VOLTAGE_CONTROL_NONE
	.comm	_PP_PCIEGenInvalid,4,2          ; @PP_PCIEGenInvalid
	.comm	_PP_ULV_MASK,4,2                ; @PP_ULV_MASK
	.comm	_SMU7_SCLK_TARGETACTIVITY_DFLT,4,2 ; @SMU7_SCLK_TARGETACTIVITY_DFLT
	.comm	_SMU7_MCLK_TARGETACTIVITY_DFLT,4,2 ; @SMU7_MCLK_TARGETACTIVITY_DFLT
	.comm	_PP_SMC_POWER_PROFILE_FULLSCREEN3D,8,3 ; @PP_SMC_POWER_PROFILE_FULLSCREEN3D
	.comm	_CHIP_POLARIS12,8,3             ; @CHIP_POLARIS12
	.comm	_VOLTAGE_TYPE_VDDC,4,2          ; @VOLTAGE_TYPE_VDDC
	.comm	_AMDGPU_FAMILY_CI,8,3           ; @AMDGPU_FAMILY_CI
	.comm	_CHIP_HAWAII,8,3                ; @CHIP_HAWAII
	.comm	_VOLTAGE_OBJ_SVID2,4,2          ; @VOLTAGE_OBJ_SVID2
	.comm	_SMU7_VOLTAGE_CONTROL_BY_SVID2,8,3 ; @SMU7_VOLTAGE_CONTROL_BY_SVID2
	.comm	_VOLTAGE_OBJ_GPIO_LUT,4,2       ; @VOLTAGE_OBJ_GPIO_LUT
	.comm	_SMU7_VOLTAGE_CONTROL_BY_GPIO,8,3 ; @SMU7_VOLTAGE_CONTROL_BY_GPIO
	.comm	_PHM_PlatformCaps_ControlVDDGFX,4,2 ; @PHM_PlatformCaps_ControlVDDGFX
	.comm	_VOLTAGE_TYPE_VDDGFX,4,2        ; @VOLTAGE_TYPE_VDDGFX
	.comm	_PHM_PlatformCaps_EnableMVDDControl,4,2 ; @PHM_PlatformCaps_EnableMVDDControl
	.comm	_VOLTAGE_TYPE_MVDDC,4,2         ; @VOLTAGE_TYPE_MVDDC
	.comm	_PHM_PlatformCaps_ControlVDDCI,4,2 ; @PHM_PlatformCaps_ControlVDDCI
	.comm	_VOLTAGE_TYPE_VDDCI,4,2         ; @VOLTAGE_TYPE_VDDCI
	.comm	_PP_TABLE_V0,8,3                ; @PP_TABLE_V0
	.comm	_PP_CLOCK_STRETCH_MASK,4,2      ; @PP_CLOCK_STRETCH_MASK
	.comm	_PHM_PlatformCaps_ClockStretcher,4,2 ; @PHM_PlatformCaps_ClockStretcher
	.comm	_PP_PCIEGen1,8,3                ; @PP_PCIEGen1
	.comm	_PP_PCIEGen3,8,3                ; @PP_PCIEGen3
	.comm	_AMD_PG_SUPPORT_UVD,4,2         ; @AMD_PG_SUPPORT_UVD
	.comm	_PHM_PlatformCaps_UVDPowerGating,4,2 ; @PHM_PlatformCaps_UVDPowerGating
	.comm	_AMD_PG_SUPPORT_VCE,4,2         ; @AMD_PG_SUPPORT_VCE
	.comm	_PHM_PlatformCaps_VCEPowerGating,4,2 ; @PHM_PlatformCaps_VCEPowerGating
	.no_dead_strip	_smu7_init_dpm_defaults
.subsections_via_symbols
