	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_sor_hdmi_enable
_tegra_sor_hdmi_enable:                 ## @tegra_sor_hdmi_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	callq	_encoder_to_output
	movq	%rax, %r12
	movq	(%rbx), %rdi
	callq	_to_tegra_dc
	movq	%rax, %r14
	movq	%r12, %rdi
	callq	_to_sor
	movq	%rax, %r15
	movl	(%r12), %edi
	callq	_to_sor_state
	movq	%rax, %r12
	movq	(%rbx), %rax
	movq	(%rax), %rbx
	movslq	(%rbx), %r13
	movl	4(%r15), %edi
	callq	_pm_runtime_get_sync
	movl	44(%r15), %esi
	movq	%r15, %rdi
	callq	_tegra_sor_set_parent_clock
	testl	%eax, %eax
	js	LBB0_1
## %bb.4:
	movq	%r13, -80(%rbp)                 ## 8-byte Spill
	movq	%rbx, -56(%rbp)                 ## 8-byte Spill
	movq	%r14, -72(%rbp)                 ## 8-byte Spill
	movl	16(%r15), %edi
	callq	_clk_get_rate
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movl	40(%r15), %edi
	callq	_tegra_io_pad_power_enable
	testl	%eax, %eax
	jns	LBB0_6
## %bb.5:
	movl	4(%r15), %edi
	leaq	L_.str.1(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
LBB0_6:
	movq	%r12, -64(%rbp)                 ## 8-byte Spill
	movl	$20, %edi
	movl	$100, %esi
	callq	_usleep_range
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	48(%rax), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_PLL2_BANDGAP_POWERDOWN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	48(%rax), %rdx
	movq	%r15, %rdi
	callq	_tegra_sor_writel
	movl	$20, %edi
	movl	$100, %esi
	callq	_usleep_range
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	24(%rax), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_PLL3_PLL_VDD_MODE_3V3@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	24(%rax), %rdx
	movq	%r15, %rdi
	callq	_tegra_sor_writel
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	40(%rax), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_PLL0_VCOPD@GOTPCREL(%rip), %rcx
	movq	_SOR_PLL0_PWR@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	40(%rax), %rdx
	movq	%r15, %rdi
	callq	_tegra_sor_writel
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	48(%rax), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_PLL2_SEQ_PLLCAPPD_ENFORCE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	48(%rax), %rdx
	movq	%r15, %rdi
	callq	_tegra_sor_writel
	movl	$200, %edi
	movl	$400, %esi                      ## imm = 0x190
	callq	_usleep_range
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	48(%rax), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_PLL2_POWERDOWN_OVERRIDE@GOTPCREL(%rip), %rcx
	movq	_SOR_PLL2_PORT_POWERDOWN@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	48(%rax), %rdx
	movq	%r15, %rdi
	callq	_tegra_sor_writel
	movl	$20, %edi
	movl	$100, %esi
	callq	_usleep_range
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	8(%rax), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_DP_PADCTL_PD_TXD_3@GOTPCREL(%rip), %rcx
	movq	_SOR_DP_PADCTL_PD_TXD_0@GOTPCREL(%rip), %rdx
	movq	_SOR_DP_PADCTL_PD_TXD_1@GOTPCREL(%rip), %rsi
	movq	_SOR_DP_PADCTL_PD_TXD_2@GOTPCREL(%rip), %rdi
	orl	(%rcx), %eax
	orl	(%rdx), %eax
	orl	(%rsi), %eax
	orl	(%rdi), %eax
	movq	8(%r15), %rcx
	movq	8(%rcx), %rcx
	movq	8(%rcx), %rdx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_tegra_sor_writel
	movq	_SOR_LANE_SEQ_CTL@GOTPCREL(%rip), %r13
	movq	(%r13), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_LANE_SEQ_CTL_STATE_BUSY@GOTPCREL(%rip), %rbx
	testl	%eax, (%rbx)
	je	LBB0_9
	.p2align	4, 0x90
LBB0_7:                                 ## =>This Inner Loop Header: Depth=1
	movl	$250, %edi
	movl	$1000, %esi                     ## imm = 0x3E8
	callq	_usleep_range
	movq	(%r13), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	testl	%eax, (%rbx)
	jne	LBB0_7
LBB0_9:
	movq	_SOR_LANE_SEQ_CTL_TRIGGER@GOTPCREL(%rip), %r12
	movq	_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	orl	(%r12), %r14d
	movq	_SOR_LANE_SEQ_CTL_POWER_STATE_UP@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
	movl	$5, %edi
	callq	_SOR_LANE_SEQ_CTL_DELAY
	orl	%eax, %r14d
	movq	(%r13), %rdx
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_tegra_sor_writel
	.p2align	4, 0x90
LBB0_11:                                ## =>This Inner Loop Header: Depth=1
	movq	(%r13), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	testl	%eax, (%r12)
	je	LBB0_12
## %bb.10:                              ##   in Loop: Header=BB0_11 Depth=1
	movl	$250, %edi
	movl	$1000, %esi                     ## imm = 0x3E8
	callq	_usleep_range
	jmp	LBB0_11
LBB0_12:
	movq	_SOR_CLK_CNTRL@GOTPCREL(%rip), %r14
	movq	(%r14), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK@GOTPCREL(%rip), %rcx
	movq	_SOR_CLK_CNTRL_DP_CLK_SEL_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	cmpl	$340000, (%rax)                 ## imm = 0x53020
	leaq	L_.str.2(%rip), %rax
	leaq	L_.str.3(%rip), %rdi
	cmovlq	%rax, %rdi
	movq	_SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40@GOTPCREL(%rip), %r12
	cmovlq	_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70@GOTPCREL(%rip), %r12
	xorl	%eax, %eax
	callq	_DRM_DEBUG_KMS
	orl	(%r12), %ebx
	movq	_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	(%r14), %rdx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_tegra_sor_writel
	movl	$250, %edi
	movl	$1000, %esi                     ## imm = 0x3E8
	callq	_usleep_range
	movq	_SOR_DP_LINKCTL0@GOTPCREL(%rip), %r14
	movq	(%r14), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_DP_LINKCTL_LANE_COUNT_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	$4, %edi
	callq	_SOR_DP_LINKCTL_LANE_COUNT
	orl	%eax, %ebx
	movq	(%r14), %rdx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_tegra_sor_writel
	movq	_SOR_DP_SPARE0@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_DP_SPARE_DISP_VIDEO_PREAMBLE@GOTPCREL(%rip), %rdx
	movq	_SOR_DP_SPARE_PANEL_INTERNAL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rdx), %esi
	movq	_SOR_DP_SPARE_SEQ_ENABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_SOR_DP_SPARE_MACRO_SOR_CLK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	(%rbx), %rdx
	movq	%r15, %rdi
	callq	_tegra_sor_writel
	xorl	%edi, %edi
	callq	_SOR_SEQ_CTL_PU_PC
	movl	%eax, %ebx
	xorl	%edi, %edi
	callq	_SOR_SEQ_CTL_PU_PC_ALT
	orl	%eax, %ebx
	movl	$8, %edi
	callq	_SOR_SEQ_CTL_PD_PC
	movl	%eax, %r13d
	movl	$8, %edi
	callq	_SOR_SEQ_CTL_PD_PC_ALT
	orl	%eax, %r13d
	orl	%ebx, %r13d
	movq	_SOR_SEQ_CTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r15, %rdi
	movl	%r13d, %esi
	callq	_tegra_sor_writel
	movq	_SOR_SEQ_INST_DRIVE_PWM_OUT_LO@GOTPCREL(%rip), %rax
	movq	_SOR_SEQ_INST_HALT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	_SOR_SEQ_INST_WAIT_VSYNC@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	$1, %edi
	callq	_SOR_SEQ_INST_WAIT
	orl	%eax, %ebx
	xorl	%edi, %edi
	callq	_SOR_SEQ_INST
	movq	%r15, %rdi
	movl	%ebx, %esi
	movq	%rax, %rdx
	callq	_tegra_sor_writel
	movl	$8, %edi
	callq	_SOR_SEQ_INST
	movq	%r15, %rdi
	movl	%ebx, %esi
	movq	%rax, %rdx
	callq	_tegra_sor_writel
	movq	8(%r15), %rax
	cmpl	$0, (%rax)
	jne	LBB0_14
## %bb.13:
	movslq	-44(%rbp), %rax                 ## 4-byte Folded Reload
	imulq	$1125899907, %rax, %rbx         ## imm = 0x431BDE83
	movq	%rbx, %rax
	shrq	$63, %rax
	sarq	$50, %rbx
	addl	%eax, %ebx
	shll	$2, %ebx
	movl	%ebx, %edi
	callq	_SOR_REFCLK_DIV_INT
	movl	%eax, %r13d
	movl	%ebx, %edi
	callq	_SOR_REFCLK_DIV_FRAC
	orl	%eax, %r13d
	movq	_SOR_REFCLK@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r15, %rdi
	movl	%r13d, %esi
	callq	_tegra_sor_writel
LBB0_14:
	movq	32(%r15), %rax
	movl	(%rax), %esi
	xorl	%edi, %edi
	callq	_SOR_XBAR_CTRL_LINK0_XSEL
	movl	%eax, %ebx
	xorl	%edi, %edi
	xorl	%esi, %esi
	callq	_SOR_XBAR_CTRL_LINK1_XSEL
	orl	%eax, %ebx
	movq	32(%r15), %rax
	movl	4(%rax), %esi
	movl	$1, %edi
	callq	_SOR_XBAR_CTRL_LINK0_XSEL
	movl	%eax, %r13d
	movl	$1, %edi
	movl	$1, %esi
	callq	_SOR_XBAR_CTRL_LINK1_XSEL
	orl	%eax, %r13d
	orl	%ebx, %r13d
	movq	32(%r15), %rax
	movl	8(%rax), %esi
	movl	$2, %edi
	callq	_SOR_XBAR_CTRL_LINK0_XSEL
	movl	%eax, %r14d
	movl	$2, %edi
	movl	$2, %esi
	callq	_SOR_XBAR_CTRL_LINK1_XSEL
	orl	%eax, %r14d
	movq	32(%r15), %rax
	movl	12(%rax), %esi
	movl	$3, %edi
	callq	_SOR_XBAR_CTRL_LINK0_XSEL
	movl	%eax, %r12d
	movl	$3, %edi
	movl	$3, %esi
	callq	_SOR_XBAR_CTRL_LINK1_XSEL
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	orl	%r14d, %r12d
	orl	%r13d, %r12d
	movq	32(%r15), %rax
	movl	16(%rax), %esi
	movl	$4, %edi
	callq	_SOR_XBAR_CTRL_LINK0_XSEL
	movl	%eax, %ebx
	movl	$4, %edi
	movl	$4, %esi
	callq	_SOR_XBAR_CTRL_LINK1_XSEL
	orl	-44(%rbp), %ebx                 ## 4-byte Folded Reload
	orl	%eax, %ebx
	orl	%r12d, %ebx
	movq	_SOR_XBAR_POL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_tegra_sor_writel
	movq	_SOR_XBAR_CTRL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_tegra_sor_writel
	movl	16(%r15), %edi
	movl	20(%r15), %esi
	callq	_clk_set_parent
	testl	%eax, %eax
	js	LBB0_15
## %bb.16:
	movl	24(%r15), %esi
	movq	%r15, %rdi
	callq	_tegra_sor_set_parent_clock
	testl	%eax, %eax
	js	LBB0_17
## %bb.18:
	imulq	$1000, -80(%rbp), %r12          ## 8-byte Folded Reload
                                        ## imm = 0x3E8
	movl	20(%r15), %edi
	callq	_clk_get_rate
	movslq	%eax, %rbx
	movq	-56(%rbp), %r13                 ## 8-byte Reload
	cmpl	$340000, (%r13)                 ## imm = 0x53020
	setge	%cl
	shrq	%cl, %rbx
	leaq	L_.str.6(%rip), %rdi
	xorl	%r14d, %r14d
	movq	%rbx, %rsi
	movq	%r12, %rdx
	xorl	%eax, %eax
	callq	_DRM_DEBUG_KMS
	movl	16(%r15), %edi
	movq	%rbx, %rsi
	callq	_clk_set_rate
	movq	8(%r15), %rax
	cmpl	$0, (%rax)
	movq	-72(%rbp), %r12                 ## 8-byte Reload
	jne	LBB0_22
## %bb.19:
	movq	8(%r12), %rdi
	callq	_SOR_INPUT_CONTROL_HDMI_SRC_SELECT
	cmpl	$75000, (%r13)                  ## imm = 0x124F8
	jge	LBB0_21
## %bb.20:
	movq	_SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r14d
LBB0_21:
	orl	%eax, %r14d
	movq	_SOR_INPUT_CONTROL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_tegra_sor_writel
LBB0_22:
	movl	8(%r13), %eax
	movq	_SOR_REKEY@GOTPCREL(%rip), %r14
	addl	(%r14), %eax
	movl	4(%r13), %ecx
	movl	%ecx, %edi
	subl	%eax, %edi
	negl	%eax
	addl	%ecx, %eax
	addl	$-18, %eax
	addl	$13, %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$5, %edi
	movq	_SOR_HDMI_CTRL_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	callq	_SOR_HDMI_CTRL_MAX_AC_PACKET
	orl	%eax, %ebx
	movq	_SOR_HDMI_CTRL_AUDIO_LAYOUT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	(%r14), %edi
	callq	_SOR_HDMI_CTRL_REKEY
	orl	%eax, %ebx
	movq	_SOR_HDMI_CTRL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_tegra_sor_writel
	movq	(%r12), %rax
	cmpq	$0, (%rax)
	jne	LBB0_24
## %bb.23:
	movl	4(%r13), %ebx
	subl	16(%r13), %ebx
	leal	-9(%rbx), %r14d
	movq	_PULSE_LAST_END_A@GOTPCREL(%rip), %rax
	movq	_PULSE_QUAL_VACTIVE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movq	_PULSE_POLARITY_HIGH@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_PULSE_MODE_NORMAL@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_DC_DISP_H_PULSE2_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_tegra_dc_writel
	decl	%ebx
	movl	%ebx, %edi
	callq	_PULSE_END
	movl	%eax, %ebx
	movl	%r14d, %edi
	callq	_PULSE_START
	orl	%eax, %ebx
	movq	_DC_DISP_H_PULSE2_POSITION_A@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_tegra_dc_writel
	movq	_DC_DISP_DISP_SIGNAL_OPTIONS0@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_tegra_dc_readl
	movq	_H_PULSE2_ENABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edx
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_tegra_dc_writel
LBB0_24:
	movq	%r15, %rdi
	movq	%r13, %rsi
	callq	_tegra_sor_hdmi_setup_avi_infoframe
	testl	%eax, %eax
	jns	LBB0_26
## %bb.25:
	movl	4(%r15), %edi
	leaq	L_.str.7(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
LBB0_26:
	movq	%r15, %rdi
	callq	_tegra_sor_hdmi_disable_audio_infoframe
	movq	_SOR_STATE1@GOTPCREL(%rip), %r14
	movq	(%r14), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_STATE_ASY_PROTOCOL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	(%r14), %rdx
	movq	%r15, %rdi
	callq	_tegra_sor_writel
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	8(%rax), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_DP_PADCTL_PAD_CAL_PD@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	8(%rax), %rdx
	movq	%r15, %rdi
	callq	_tegra_sor_writel
	imull	$1000, (%r13), %esi             ## imm = 0x3E8
	movq	%r15, %rdi
	callq	_tegra_sor_hdmi_find_settings
	testq	%rax, %rax
	je	LBB0_27
## %bb.28:
	movq	%rax, %r13
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	40(%rax), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_PLL0_ICHPMP_MASK@GOTPCREL(%rip), %rcx
	movq	_SOR_PLL0_FILTER_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	movq	_SOR_PLL0_VCOCAP_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	56(%r13), %edi
	callq	_SOR_PLL0_ICHPMP
	movl	%eax, %r12d
	movl	52(%r13), %edi
	callq	_SOR_PLL0_FILTER
	orl	%eax, %r12d
	movl	48(%r13), %edi
	callq	_SOR_PLL0_VCOCAP
	orl	%eax, %r12d
	orl	%ebx, %r12d
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	40(%rax), %rdx
	movq	%r15, %rdi
	movl	%r12d, %esi
	callq	_tegra_sor_writel
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	32(%rax), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_PLL1_LOADADJ_MASK@GOTPCREL(%rip), %rcx
	movq	_SOR_PLL1_TMDS_TERMADJ_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r12d
	orl	(%rcx), %r12d
	notl	%r12d
	andl	%eax, %r12d
	movl	44(%r13), %edi
	callq	_SOR_PLL1_LOADADJ
	movl	%eax, %ebx
	movl	40(%r13), %edi
	callq	_SOR_PLL1_TMDS_TERMADJ
	orl	%eax, %ebx
	orl	%r12d, %ebx
	movq	_SOR_PLL1_TMDS_TERM@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	32(%rax), %rdx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_tegra_sor_writel
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	24(%rax), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_PLL3_BG_TEMP_COEF_MASK@GOTPCREL(%rip), %rcx
	movq	_SOR_PLL3_BG_VREF_LEVEL_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r12d
	orl	(%rcx), %r12d
	movq	_SOR_PLL3_AVDD10_LEVEL_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r12d
	movq	_SOR_PLL3_AVDD14_LEVEL_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r12d
	notl	%r12d
	andl	%eax, %r12d
	movl	36(%r13), %edi
	callq	_SOR_PLL3_BG_TEMP_COEF
	movl	%eax, %ebx
	movl	32(%r13), %edi
	callq	_SOR_PLL3_BG_VREF_LEVEL
	orl	%eax, %ebx
	movl	28(%r13), %edi
	callq	_SOR_PLL3_AVDD10_LEVEL
	orl	%eax, %ebx
	orl	%r12d, %ebx
	movl	24(%r13), %edi
	callq	_SOR_PLL3_AVDD14_LEVEL
	orl	%eax, %ebx
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	24(%rax), %rdx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_tegra_sor_writel
	movq	(%r13), %rax
	movl	12(%rax), %ecx
	shll	$24, %ecx
	movl	4(%rax), %esi
	movl	8(%rax), %edx
	shll	$16, %edx
	orl	%ecx, %edx
	shll	$8, %esi
	orl	%edx, %esi
	orl	(%rax), %esi
	movq	_SOR_LANE_DRIVE_CURRENT0@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r15, %rdi
	callq	_tegra_sor_writel
	movq	8(%r13), %rax
	movl	12(%rax), %ecx
	shll	$24, %ecx
	movl	4(%rax), %esi
	movl	8(%rax), %edx
	shll	$16, %edx
	orl	%ecx, %edx
	shll	$8, %esi
	orl	%edx, %esi
	orl	(%rax), %esi
	movq	_SOR_LANE_PREEMPHASIS0@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r15, %rdi
	callq	_tegra_sor_writel
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	8(%rax), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_DP_PADCTL_TX_PU_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movq	_SOR_DP_PADCTL_TX_PU_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	20(%r13), %edi
	callq	_SOR_DP_PADCTL_TX_PU
	orl	%eax, %ebx
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	8(%rax), %rdx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_tegra_sor_writel
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	16(%rax), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_DP_PADCTL_SPAREPLL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	16(%r13), %edi
	callq	_SOR_DP_PADCTL_SPAREPLL
	orl	%eax, %ebx
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	16(%rax), %rdx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_tegra_sor_writel
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	8(%rax), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_DP_PADCTL_PAD_CAL_PD@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	8(%r15), %rcx
	movq	8(%rcx), %rcx
	movq	8(%rcx), %rdx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_tegra_sor_writel
	movq	-72(%rbp), %r13                 ## 8-byte Reload
	movq	(%r13), %rax
	cmpq	$0, (%rax)
	jne	LBB0_30
## %bb.29:
	movl	$1, %edi
	callq	_VSYNC_H_POSITION
	movq	_DC_DISP_DISP_TIMING_OPTIONS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_tegra_dc_writel
LBB0_30:
	movq	_DC_DISP_DISP_COLOR_CONTROL@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r13, %rdi
	callq	_tegra_dc_readl
	movq	_DITHER_CONTROL_MASK@GOTPCREL(%rip), %rcx
	movq	_BASE_COLOR_SIZE_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movq	-64(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %edx
	leal	-6(%rdx), %eax
	cmpl	$7, %eax
	jae	LBB0_31
## %bb.32:
	movl	$85, %ecx
	btl	%eax, %ecx
	jb	LBB0_33
LBB0_31:
	leaq	L_.str.9(%rip), %rsi
	movl	$1, %edi
                                        ## kill: def $edx killed $edx killed $rdx
	callq	_WARN
	movq	_BASE_COLOR_SIZE_888@GOTPCREL(%rip), %rax
	jmp	LBB0_34
LBB0_1:
	movl	4(%r15), %edi
	leaq	L_.str(%rip), %rsi
	jmp	LBB0_2
LBB0_15:
	movl	4(%r15), %edi
	leaq	L_.str.4(%rip), %rsi
	jmp	LBB0_2
LBB0_17:
	movl	4(%r15), %edi
	leaq	L_.str.5(%rip), %rsi
LBB0_2:
	movl	%eax, %edx
LBB0_3:
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_dev_err                        ## TAILCALL
LBB0_27:
	movq	%r13, %rcx
	movl	4(%r15), %edi
	imull	$1000, (%r13), %edx             ## imm = 0x3E8
	leaq	L_.str.8(%rip), %rsi
	jmp	LBB0_3
LBB0_33:
	cltq
	leaq	l_switch.table.tegra_sor_hdmi_enable(%rip), %rcx
	movq	(%rcx,%rax,8), %rax
LBB0_34:
	orl	(%rax), %ebx
	movl	(%r12), %edx
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_tegra_dc_writel
	movq	(%r14), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_STATE_ASY_OWNER_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movq	8(%r13), %rdi
	incq	%rdi
	callq	_SOR_STATE_ASY_OWNER
	orl	%eax, %ebx
	movq	(%r14), %rdx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_tegra_sor_writel
	movq	%r15, %rdi
	movl	$250, %esi
	callq	_tegra_sor_power_up
	testl	%eax, %eax
	jns	LBB0_36
## %bb.35:
	movl	4(%r15), %edi
	leaq	L_.str.10(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
LBB0_36:
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	8(%r13), %rsi
	addq	(%rax), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_HEAD_STATE_RANGECOMPRESS_MASK@GOTPCREL(%rip), %rcx
	movq	_SOR_HEAD_STATE_DYNRANGE_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	8(%r13), %rdx
	addq	(%rax), %rdx
	movq	%r15, %rdi
	callq	_tegra_sor_writel
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	8(%r13), %rsi
	addq	(%rax), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_HEAD_STATE_COLORSPACE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_SOR_HEAD_STATE_COLORSPACE_RGB@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	8(%r15), %rax
	movq	8(%rax), %rax
	movq	8(%r13), %rdx
	addq	(%rax), %rdx
	movq	%r15, %rdi
	callq	_tegra_sor_writel
	movq	%r15, %rdi
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
	movq	-64(%rbp), %rdx                 ## 8-byte Reload
	callq	_tegra_sor_mode_set
	movq	%r15, %rdi
	callq	_tegra_sor_update
	movq	_SOR_DP_SPARE0@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_DP_SPARE_DISP_VIDEO_PREAMBLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	(%rbx), %rdx
	movq	%r15, %rdi
	callq	_tegra_sor_writel
	movq	%r15, %rdi
	callq	_tegra_sor_attach
	testl	%eax, %eax
	jns	LBB0_38
## %bb.37:
	movl	4(%r15), %edi
	leaq	L_.str.11(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
LBB0_38:
	movq	_DC_DISP_DISP_WIN_OPTIONS@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%r13, %rdi
	callq	_tegra_dc_readl
	movl	%eax, %ebx
	movq	8(%r15), %rax
	cmpl	$0, (%rax)
	je	LBB0_39
## %bb.40:
	movl	(%r15), %edi
	callq	_SOR_ENABLE
	jmp	LBB0_41
LBB0_39:
	movl	$1, %edi
	callq	_SOR_ENABLE
	movq	_SOR1_TIMING_CYA@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
LBB0_41:
	orl	%ebx, %eax
	movl	(%r14), %edx
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_tegra_dc_writel
	movq	(%r13), %rax
	cmpq	$0, (%rax)
	je	LBB0_43
## %bb.42:
	movl	(%r15), %edi
	callq	_DC_DISP_CORE_SOR_SET_CONTROL
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_tegra_dc_readl
	movq	_PROTOCOL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movq	_PROTOCOL_SINGLE_TMDS_A@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	(%r15), %edi
	callq	_DC_DISP_CORE_SOR_SET_CONTROL
	movq	%r13, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_tegra_dc_writel
LBB0_43:
	movq	%r13, %rdi
	callq	_tegra_dc_commit
	movq	%r15, %rdi
	callq	_tegra_sor_wakeup
	testl	%eax, %eax
	jns	LBB0_45
## %bb.44:
	movl	4(%r15), %edi
	leaq	L_.str.12(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
LBB0_45:
	movq	%r15, %rdi
	callq	_tegra_sor_hdmi_scdc_start
	movq	%r15, %rdi
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_tegra_sor_audio_prepare        ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"failed to set safe parent clock: %d\n"

L_.str.1:                               ## @.str.1
	.asciz	"failed to power on I/O pad: %d\n"

	.comm	_SOR_PLL2_BANDGAP_POWERDOWN,4,2 ## @SOR_PLL2_BANDGAP_POWERDOWN
	.comm	_SOR_PLL3_PLL_VDD_MODE_3V3,4,2  ## @SOR_PLL3_PLL_VDD_MODE_3V3
	.comm	_SOR_PLL0_VCOPD,4,2             ## @SOR_PLL0_VCOPD
	.comm	_SOR_PLL0_PWR,4,2               ## @SOR_PLL0_PWR
	.comm	_SOR_PLL2_SEQ_PLLCAPPD_ENFORCE,4,2 ## @SOR_PLL2_SEQ_PLLCAPPD_ENFORCE
	.comm	_SOR_PLL2_POWERDOWN_OVERRIDE,4,2 ## @SOR_PLL2_POWERDOWN_OVERRIDE
	.comm	_SOR_PLL2_PORT_POWERDOWN,4,2    ## @SOR_PLL2_PORT_POWERDOWN
	.comm	_SOR_DP_PADCTL_PD_TXD_3,4,2     ## @SOR_DP_PADCTL_PD_TXD_3
	.comm	_SOR_DP_PADCTL_PD_TXD_0,4,2     ## @SOR_DP_PADCTL_PD_TXD_0
	.comm	_SOR_DP_PADCTL_PD_TXD_1,4,2     ## @SOR_DP_PADCTL_PD_TXD_1
	.comm	_SOR_DP_PADCTL_PD_TXD_2,4,2     ## @SOR_DP_PADCTL_PD_TXD_2
	.comm	_SOR_LANE_SEQ_CTL,8,3           ## @SOR_LANE_SEQ_CTL
	.comm	_SOR_LANE_SEQ_CTL_STATE_BUSY,4,2 ## @SOR_LANE_SEQ_CTL_STATE_BUSY
	.comm	_SOR_LANE_SEQ_CTL_TRIGGER,4,2   ## @SOR_LANE_SEQ_CTL_TRIGGER
	.comm	_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN,4,2 ## @SOR_LANE_SEQ_CTL_SEQUENCE_DOWN
	.comm	_SOR_LANE_SEQ_CTL_POWER_STATE_UP,4,2 ## @SOR_LANE_SEQ_CTL_POWER_STATE_UP
	.comm	_SOR_CLK_CNTRL,8,3              ## @SOR_CLK_CNTRL
	.comm	_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK,4,2 ## @SOR_CLK_CNTRL_DP_LINK_SPEED_MASK
	.comm	_SOR_CLK_CNTRL_DP_CLK_SEL_MASK,4,2 ## @SOR_CLK_CNTRL_DP_CLK_SEL_MASK
L_.str.2:                               ## @.str.2
	.asciz	"setting 2.7 GHz link speed\n"

	.comm	_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70,4,2 ## @SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70
L_.str.3:                               ## @.str.3
	.asciz	"setting 5.4 GHz link speed\n"

	.comm	_SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40,4,2 ## @SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40
	.comm	_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK,4,2 ## @SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK
	.comm	_SOR_DP_LINKCTL0,8,3            ## @SOR_DP_LINKCTL0
	.comm	_SOR_DP_LINKCTL_LANE_COUNT_MASK,4,2 ## @SOR_DP_LINKCTL_LANE_COUNT_MASK
	.comm	_SOR_DP_SPARE0,8,3              ## @SOR_DP_SPARE0
	.comm	_SOR_DP_SPARE_DISP_VIDEO_PREAMBLE,4,2 ## @SOR_DP_SPARE_DISP_VIDEO_PREAMBLE
	.comm	_SOR_DP_SPARE_PANEL_INTERNAL,4,2 ## @SOR_DP_SPARE_PANEL_INTERNAL
	.comm	_SOR_DP_SPARE_SEQ_ENABLE,4,2    ## @SOR_DP_SPARE_SEQ_ENABLE
	.comm	_SOR_DP_SPARE_MACRO_SOR_CLK,4,2 ## @SOR_DP_SPARE_MACRO_SOR_CLK
	.comm	_SOR_SEQ_CTL,8,3                ## @SOR_SEQ_CTL
	.comm	_SOR_SEQ_INST_DRIVE_PWM_OUT_LO,4,2 ## @SOR_SEQ_INST_DRIVE_PWM_OUT_LO
	.comm	_SOR_SEQ_INST_HALT,4,2          ## @SOR_SEQ_INST_HALT
	.comm	_SOR_SEQ_INST_WAIT_VSYNC,4,2    ## @SOR_SEQ_INST_WAIT_VSYNC
	.comm	_SOR_REFCLK,8,3                 ## @SOR_REFCLK
	.comm	_SOR_XBAR_POL,8,3               ## @SOR_XBAR_POL
	.comm	_SOR_XBAR_CTRL,8,3              ## @SOR_XBAR_CTRL
L_.str.4:                               ## @.str.4
	.asciz	"failed to set parent clock: %d\n"

L_.str.5:                               ## @.str.5
	.asciz	"failed to set pad clock: %d\n"

L_.str.6:                               ## @.str.6
	.asciz	"setting clock to %lu Hz, mode: %lu Hz\n"

	.comm	_SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED,4,2 ## @SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED
	.comm	_SOR_INPUT_CONTROL,8,3          ## @SOR_INPUT_CONTROL
	.comm	_SOR_REKEY,4,2                  ## @SOR_REKEY
	.comm	_SOR_HDMI_CTRL_ENABLE,4,2       ## @SOR_HDMI_CTRL_ENABLE
	.comm	_SOR_HDMI_CTRL_AUDIO_LAYOUT,4,2 ## @SOR_HDMI_CTRL_AUDIO_LAYOUT
	.comm	_SOR_HDMI_CTRL,8,3              ## @SOR_HDMI_CTRL
	.comm	_PULSE_LAST_END_A,4,2           ## @PULSE_LAST_END_A
	.comm	_PULSE_QUAL_VACTIVE,4,2         ## @PULSE_QUAL_VACTIVE
	.comm	_PULSE_POLARITY_HIGH,4,2        ## @PULSE_POLARITY_HIGH
	.comm	_PULSE_MODE_NORMAL,4,2          ## @PULSE_MODE_NORMAL
	.comm	_DC_DISP_H_PULSE2_CONTROL,4,2   ## @DC_DISP_H_PULSE2_CONTROL
	.comm	_DC_DISP_H_PULSE2_POSITION_A,4,2 ## @DC_DISP_H_PULSE2_POSITION_A
	.comm	_DC_DISP_DISP_SIGNAL_OPTIONS0,4,2 ## @DC_DISP_DISP_SIGNAL_OPTIONS0
	.comm	_H_PULSE2_ENABLE,4,2            ## @H_PULSE2_ENABLE
L_.str.7:                               ## @.str.7
	.asciz	"failed to setup AVI infoframe: %d\n"

	.comm	_SOR_STATE1,8,3                 ## @SOR_STATE1
	.comm	_SOR_STATE_ASY_PROTOCOL_MASK,4,2 ## @SOR_STATE_ASY_PROTOCOL_MASK
	.comm	_SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A,4,2 ## @SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A
	.comm	_SOR_DP_PADCTL_PAD_CAL_PD,4,2   ## @SOR_DP_PADCTL_PAD_CAL_PD
L_.str.8:                               ## @.str.8
	.asciz	"no settings for pixel clock %d Hz\n"

	.comm	_SOR_PLL0_ICHPMP_MASK,4,2       ## @SOR_PLL0_ICHPMP_MASK
	.comm	_SOR_PLL0_FILTER_MASK,4,2       ## @SOR_PLL0_FILTER_MASK
	.comm	_SOR_PLL0_VCOCAP_MASK,4,2       ## @SOR_PLL0_VCOCAP_MASK
	.comm	_SOR_PLL1_LOADADJ_MASK,4,2      ## @SOR_PLL1_LOADADJ_MASK
	.comm	_SOR_PLL1_TMDS_TERMADJ_MASK,4,2 ## @SOR_PLL1_TMDS_TERMADJ_MASK
	.comm	_SOR_PLL1_TMDS_TERM,4,2         ## @SOR_PLL1_TMDS_TERM
	.comm	_SOR_PLL3_BG_TEMP_COEF_MASK,4,2 ## @SOR_PLL3_BG_TEMP_COEF_MASK
	.comm	_SOR_PLL3_BG_VREF_LEVEL_MASK,4,2 ## @SOR_PLL3_BG_VREF_LEVEL_MASK
	.comm	_SOR_PLL3_AVDD10_LEVEL_MASK,4,2 ## @SOR_PLL3_AVDD10_LEVEL_MASK
	.comm	_SOR_PLL3_AVDD14_LEVEL_MASK,4,2 ## @SOR_PLL3_AVDD14_LEVEL_MASK
	.comm	_SOR_LANE_DRIVE_CURRENT0,8,3    ## @SOR_LANE_DRIVE_CURRENT0
	.comm	_SOR_LANE_PREEMPHASIS0,8,3      ## @SOR_LANE_PREEMPHASIS0
	.comm	_SOR_DP_PADCTL_TX_PU_MASK,4,2   ## @SOR_DP_PADCTL_TX_PU_MASK
	.comm	_SOR_DP_PADCTL_TX_PU_ENABLE,4,2 ## @SOR_DP_PADCTL_TX_PU_ENABLE
	.comm	_SOR_DP_PADCTL_SPAREPLL_MASK,4,2 ## @SOR_DP_PADCTL_SPAREPLL_MASK
	.comm	_DC_DISP_DISP_TIMING_OPTIONS,4,2 ## @DC_DISP_DISP_TIMING_OPTIONS
	.comm	_DC_DISP_DISP_COLOR_CONTROL,4,2 ## @DC_DISP_DISP_COLOR_CONTROL
	.comm	_DITHER_CONTROL_MASK,4,2        ## @DITHER_CONTROL_MASK
	.comm	_BASE_COLOR_SIZE_MASK,4,2       ## @BASE_COLOR_SIZE_MASK
	.comm	_BASE_COLOR_SIZE_666,4,2        ## @BASE_COLOR_SIZE_666
	.comm	_BASE_COLOR_SIZE_888,4,2        ## @BASE_COLOR_SIZE_888
	.comm	_BASE_COLOR_SIZE_101010,4,2     ## @BASE_COLOR_SIZE_101010
	.comm	_BASE_COLOR_SIZE_121212,4,2     ## @BASE_COLOR_SIZE_121212
L_.str.9:                               ## @.str.9
	.asciz	"%u bits-per-color not supported\n"

	.comm	_SOR_STATE_ASY_OWNER_MASK,4,2   ## @SOR_STATE_ASY_OWNER_MASK
L_.str.10:                              ## @.str.10
	.asciz	"failed to power up SOR: %d\n"

	.comm	_SOR_HEAD_STATE_RANGECOMPRESS_MASK,4,2 ## @SOR_HEAD_STATE_RANGECOMPRESS_MASK
	.comm	_SOR_HEAD_STATE_DYNRANGE_MASK,4,2 ## @SOR_HEAD_STATE_DYNRANGE_MASK
	.comm	_SOR_HEAD_STATE_COLORSPACE_MASK,4,2 ## @SOR_HEAD_STATE_COLORSPACE_MASK
	.comm	_SOR_HEAD_STATE_COLORSPACE_RGB,4,2 ## @SOR_HEAD_STATE_COLORSPACE_RGB
L_.str.11:                              ## @.str.11
	.asciz	"failed to attach SOR: %d\n"

	.comm	_DC_DISP_DISP_WIN_OPTIONS,4,2   ## @DC_DISP_DISP_WIN_OPTIONS
	.comm	_SOR1_TIMING_CYA,4,2            ## @SOR1_TIMING_CYA
	.comm	_PROTOCOL_MASK,4,2              ## @PROTOCOL_MASK
	.comm	_PROTOCOL_SINGLE_TMDS_A,4,2     ## @PROTOCOL_SINGLE_TMDS_A
L_.str.12:                              ## @.str.12
	.asciz	"failed to wakeup SOR: %d\n"

	.no_dead_strip	_tegra_sor_hdmi_enable
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.tegra_sor_hdmi_enable
l_switch.table.tegra_sor_hdmi_enable:
	.quad	_BASE_COLOR_SIZE_666
	.quad	_BASE_COLOR_SIZE_666
	.quad	_BASE_COLOR_SIZE_888
	.quad	_BASE_COLOR_SIZE_666
	.quad	_BASE_COLOR_SIZE_101010
	.quad	_BASE_COLOR_SIZE_666
	.quad	_BASE_COLOR_SIZE_121212

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_sor_hdmi_enable
_tegra_sor_hdmi_enable:                 ; @tegra_sor_hdmi_enable
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x22, x0
	bl	_encoder_to_output
	mov	x21, x0
	ldr	x0, [x22]
	bl	_to_tegra_dc
	mov	x20, x0
	mov	x0, x21
	bl	_to_sor
	mov	x19, x0
	ldr	w0, [x21]
	bl	_to_sor_state
	mov	x21, x0
	ldr	x8, [x22]
	ldr	x22, [x8]
	ldrsw	x27, [x22]
	ldr	w0, [x19, #4]
	bl	_pm_runtime_get_sync
	ldr	w1, [x19, #44]
	mov	x0, x19
	bl	_tegra_sor_set_parent_clock
	tbnz	w0, #31, LBB0_25
; %bb.1:
	ldr	w0, [x19, #16]
	bl	_clk_get_rate
	mov	x23, x0
	ldr	w0, [x19, #40]
	bl	_tegra_io_pad_power_enable
	tbz	w0, #31, LBB0_3
; %bb.2:
	mov	x2, x0
	ldr	w0, [x19, #4]
Lloh0:
	adrp	x1, l_.str.1@PAGE
Lloh1:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_err
LBB0_3:
	mov	w0, #20
	mov	w1, #100
	bl	_usleep_range
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x1, [x8, #48]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh2:
	adrp	x8, _SOR_PLL2_BANDGAP_POWERDOWN@GOTPAGE
Lloh3:
	ldr	x8, [x8, _SOR_PLL2_BANDGAP_POWERDOWN@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x2, [x8, #48]
	mov	x0, x19
	bl	_tegra_sor_writel
	mov	w0, #20
	mov	w1, #100
	bl	_usleep_range
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x1, [x8, #24]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh5:
	adrp	x8, _SOR_PLL3_PLL_VDD_MODE_3V3@GOTPAGE
Lloh6:
	ldr	x8, [x8, _SOR_PLL3_PLL_VDD_MODE_3V3@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x2, [x8, #24]
	mov	x0, x19
	bl	_tegra_sor_writel
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x1, [x8, #40]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh8:
	adrp	x8, _SOR_PLL0_VCOPD@GOTPAGE
Lloh9:
	ldr	x8, [x8, _SOR_PLL0_VCOPD@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
Lloh11:
	adrp	x9, _SOR_PLL0_PWR@GOTPAGE
Lloh12:
	ldr	x9, [x9, _SOR_PLL0_PWR@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w1, w0, w8
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x2, [x8, #40]
	mov	x0, x19
	bl	_tegra_sor_writel
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x1, [x8, #48]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh14:
	adrp	x8, _SOR_PLL2_SEQ_PLLCAPPD_ENFORCE@GOTPAGE
Lloh15:
	ldr	x8, [x8, _SOR_PLL2_SEQ_PLLCAPPD_ENFORCE@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x2, [x8, #48]
	mov	x0, x19
	bl	_tegra_sor_writel
	mov	w0, #200
	mov	w1, #400
	bl	_usleep_range
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x1, [x8, #48]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh17:
	adrp	x8, _SOR_PLL2_POWERDOWN_OVERRIDE@GOTPAGE
Lloh18:
	ldr	x8, [x8, _SOR_PLL2_POWERDOWN_OVERRIDE@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
Lloh20:
	adrp	x9, _SOR_PLL2_PORT_POWERDOWN@GOTPAGE
Lloh21:
	ldr	x9, [x9, _SOR_PLL2_PORT_POWERDOWN@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w1, w0, w8
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x2, [x8, #48]
	mov	x0, x19
	bl	_tegra_sor_writel
	mov	w0, #20
	mov	w1, #100
	bl	_usleep_range
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x1, [x8, #8]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh23:
	adrp	x8, _SOR_DP_PADCTL_PD_TXD_3@GOTPAGE
Lloh24:
	ldr	x8, [x8, _SOR_DP_PADCTL_PD_TXD_3@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
Lloh26:
	adrp	x9, _SOR_DP_PADCTL_PD_TXD_0@GOTPAGE
Lloh27:
	ldr	x9, [x9, _SOR_DP_PADCTL_PD_TXD_0@GOTPAGEOFF]
Lloh28:
	adrp	x10, _SOR_DP_PADCTL_PD_TXD_1@GOTPAGE
Lloh29:
	ldr	x10, [x10, _SOR_DP_PADCTL_PD_TXD_1@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
Lloh31:
	ldr	w10, [x10]
Lloh32:
	adrp	x11, _SOR_DP_PADCTL_PD_TXD_2@GOTPAGE
Lloh33:
	ldr	x11, [x11, _SOR_DP_PADCTL_PD_TXD_2@GOTPAGEOFF]
Lloh34:
	ldr	w11, [x11]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w1, w8, w11
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x2, [x8, #8]
	mov	x0, x19
	bl	_tegra_sor_writel
Lloh35:
	adrp	x24, _SOR_LANE_SEQ_CTL@GOTPAGE
Lloh36:
	ldr	x24, [x24, _SOR_LANE_SEQ_CTL@GOTPAGEOFF]
	ldr	x1, [x24]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh37:
	adrp	x25, _SOR_LANE_SEQ_CTL_STATE_BUSY@GOTPAGE
Lloh38:
	ldr	x25, [x25, _SOR_LANE_SEQ_CTL_STATE_BUSY@GOTPAGEOFF]
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w8, [x25]
	tst	w8, w0
	b.eq	LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	mov	w0, #250
	mov	w1, #1000
	bl	_usleep_range
	ldr	x1, [x24]
	mov	x0, x19
	bl	_tegra_sor_readl
	b	LBB0_4
LBB0_6:
Lloh39:
	adrp	x25, _SOR_LANE_SEQ_CTL_TRIGGER@GOTPAGE
Lloh40:
	ldr	x25, [x25, _SOR_LANE_SEQ_CTL_TRIGGER@GOTPAGEOFF]
	ldr	w8, [x25]
Lloh41:
	adrp	x9, _SOR_LANE_SEQ_CTL_SEQUENCE_DOWN@GOTPAGE
Lloh42:
	ldr	x9, [x9, _SOR_LANE_SEQ_CTL_SEQUENCE_DOWN@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh44:
	adrp	x9, _SOR_LANE_SEQ_CTL_POWER_STATE_UP@GOTPAGE
Lloh45:
	ldr	x9, [x9, _SOR_LANE_SEQ_CTL_POWER_STATE_UP@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
	orr	w26, w8, w9
	mov	w0, #5
	bl	_SOR_LANE_SEQ_CTL_DELAY
	orr	w1, w26, w0
	ldr	x2, [x24]
	mov	x0, x19
	bl	_tegra_sor_writel
LBB0_7:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x1, [x24]
	mov	x0, x19
	bl	_tegra_sor_readl
	ldr	w8, [x25]
	tst	w8, w0
	b.eq	LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=1
	mov	w0, #250
	mov	w1, #1000
	bl	_usleep_range
	b	LBB0_7
LBB0_9:
	mov	w28, #12319
	movk	w28, #5, lsl #16
Lloh47:
	adrp	x24, _SOR_CLK_CNTRL@GOTPAGE
Lloh48:
	ldr	x24, [x24, _SOR_CLK_CNTRL@GOTPAGEOFF]
	ldr	x1, [x24]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh49:
	adrp	x8, _SOR_CLK_CNTRL_DP_LINK_SPEED_MASK@GOTPAGE
Lloh50:
	ldr	x8, [x8, _SOR_CLK_CNTRL_DP_LINK_SPEED_MASK@GOTPAGEOFF]
Lloh51:
	adrp	x9, _SOR_CLK_CNTRL_DP_CLK_SEL_MASK@GOTPAGE
Lloh52:
	ldr	x9, [x9, _SOR_CLK_CNTRL_DP_CLK_SEL_MASK@GOTPAGEOFF]
Lloh53:
	ldr	w8, [x8]
Lloh54:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w25, w0, w8
	ldr	w8, [x22]
	add	w9, w28, #1
Lloh55:
	adrp	x10, l_.str.3@PAGE
Lloh56:
	add	x10, x10, l_.str.3@PAGEOFF
Lloh57:
	adrp	x11, l_.str.2@PAGE
Lloh58:
	add	x11, x11, l_.str.2@PAGEOFF
	cmp	w8, w9
	csel	x0, x11, x10, lt
Lloh59:
	adrp	x8, _SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70@GOTPAGE
Lloh60:
	ldr	x8, [x8, _SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70@GOTPAGEOFF]
Lloh61:
	adrp	x9, _SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40@GOTPAGE
Lloh62:
	ldr	x9, [x9, _SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40@GOTPAGEOFF]
	csel	x26, x8, x9, lt
	bl	_DRM_DEBUG_KMS
	ldr	w8, [x26]
	orr	w8, w8, w25
Lloh63:
	adrp	x9, _SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK@GOTPAGE
Lloh64:
	ldr	x9, [x9, _SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK@GOTPAGEOFF]
Lloh65:
	ldr	w9, [x9]
	orr	w1, w8, w9
	ldr	x2, [x24]
	mov	x0, x19
	bl	_tegra_sor_writel
	mov	w0, #250
	mov	w1, #1000
	bl	_usleep_range
Lloh66:
	adrp	x24, _SOR_DP_LINKCTL0@GOTPAGE
Lloh67:
	ldr	x24, [x24, _SOR_DP_LINKCTL0@GOTPAGEOFF]
	ldr	x1, [x24]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh68:
	adrp	x8, _SOR_DP_LINKCTL_LANE_COUNT_MASK@GOTPAGE
Lloh69:
	ldr	x8, [x8, _SOR_DP_LINKCTL_LANE_COUNT_MASK@GOTPAGEOFF]
Lloh70:
	ldr	w8, [x8]
	bic	w25, w0, w8
	mov	w0, #4
	bl	_SOR_DP_LINKCTL_LANE_COUNT
	orr	w1, w25, w0
	ldr	x2, [x24]
	mov	x0, x19
	bl	_tegra_sor_writel
Lloh71:
	adrp	x25, _SOR_DP_SPARE0@GOTPAGE
Lloh72:
	ldr	x25, [x25, _SOR_DP_SPARE0@GOTPAGEOFF]
	ldr	x1, [x25]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh73:
	adrp	x26, _SOR_DP_SPARE_DISP_VIDEO_PREAMBLE@GOTPAGE
Lloh74:
	ldr	x26, [x26, _SOR_DP_SPARE_DISP_VIDEO_PREAMBLE@GOTPAGEOFF]
	ldr	w8, [x26]
Lloh75:
	adrp	x9, _SOR_DP_SPARE_PANEL_INTERNAL@GOTPAGE
Lloh76:
	ldr	x9, [x9, _SOR_DP_SPARE_PANEL_INTERNAL@GOTPAGEOFF]
Lloh77:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh78:
	adrp	x9, _SOR_DP_SPARE_SEQ_ENABLE@GOTPAGE
Lloh79:
	ldr	x9, [x9, _SOR_DP_SPARE_SEQ_ENABLE@GOTPAGEOFF]
Lloh80:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh81:
	adrp	x9, _SOR_DP_SPARE_MACRO_SOR_CLK@GOTPAGE
Lloh82:
	ldr	x9, [x9, _SOR_DP_SPARE_MACRO_SOR_CLK@GOTPAGEOFF]
Lloh83:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w1, w0, w8
	ldr	x2, [x25]
	mov	x0, x19
	bl	_tegra_sor_writel
	mov	w0, #0
	bl	_SOR_SEQ_CTL_PU_PC
	mov	x24, x0
	mov	w0, #0
	bl	_SOR_SEQ_CTL_PU_PC_ALT
	orr	w24, w0, w24
	mov	w0, #8
	bl	_SOR_SEQ_CTL_PD_PC
	orr	w24, w24, w0
	mov	w0, #8
	bl	_SOR_SEQ_CTL_PD_PC_ALT
	orr	w1, w24, w0
Lloh84:
	adrp	x8, _SOR_SEQ_CTL@GOTPAGE
Lloh85:
	ldr	x8, [x8, _SOR_SEQ_CTL@GOTPAGEOFF]
Lloh86:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_tegra_sor_writel
Lloh87:
	adrp	x8, _SOR_SEQ_INST_DRIVE_PWM_OUT_LO@GOTPAGE
Lloh88:
	ldr	x8, [x8, _SOR_SEQ_INST_DRIVE_PWM_OUT_LO@GOTPAGEOFF]
Lloh89:
	ldr	w8, [x8]
Lloh90:
	adrp	x9, _SOR_SEQ_INST_HALT@GOTPAGE
Lloh91:
	ldr	x9, [x9, _SOR_SEQ_INST_HALT@GOTPAGEOFF]
Lloh92:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh93:
	adrp	x9, _SOR_SEQ_INST_WAIT_VSYNC@GOTPAGE
Lloh94:
	ldr	x9, [x9, _SOR_SEQ_INST_WAIT_VSYNC@GOTPAGEOFF]
Lloh95:
	ldr	w9, [x9]
	orr	w24, w8, w9
	mov	w0, #1
	bl	_SOR_SEQ_INST_WAIT
	orr	w24, w24, w0
	mov	w0, #0
	bl	_SOR_SEQ_INST
	mov	x2, x0
	mov	x0, x19
	mov	x1, x24
	bl	_tegra_sor_writel
	mov	w0, #8
	bl	_SOR_SEQ_INST
	mov	x2, x0
	mov	x0, x19
	mov	x1, x24
	bl	_tegra_sor_writel
	ldr	x8, [x19, #8]
	ldr	w8, [x8]
	cbnz	w8, LBB0_11
; %bb.10:
	mov	w8, #56963
	movk	w8, #17179, lsl #16
	smull	x8, w23, w8
	lsr	x9, x8, #63
	asr	x8, x8, #50
	add	w8, w8, w9
	lsl	w23, w8, #2
	mov	x0, x23
	bl	_SOR_REFCLK_DIV_INT
	mov	x24, x0
	mov	x0, x23
	bl	_SOR_REFCLK_DIV_FRAC
	orr	w1, w0, w24
Lloh96:
	adrp	x8, _SOR_REFCLK@GOTPAGE
Lloh97:
	ldr	x8, [x8, _SOR_REFCLK@GOTPAGEOFF]
Lloh98:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_tegra_sor_writel
LBB0_11:
	ldr	x8, [x19, #32]
	ldr	w1, [x8]
	mov	w0, #0
	bl	_SOR_XBAR_CTRL_LINK0_XSEL
	mov	x23, x0
	mov	w0, #0
	mov	w1, #0
	bl	_SOR_XBAR_CTRL_LINK1_XSEL
	orr	w24, w23, w0
	ldr	x8, [x19, #32]
	ldr	w1, [x8, #4]
	mov	w0, #1
	bl	_SOR_XBAR_CTRL_LINK0_XSEL
	mov	x23, x0
	mov	w0, #1
	mov	w1, #1
	bl	_SOR_XBAR_CTRL_LINK1_XSEL
	orr	w8, w23, w24
	orr	w24, w8, w0
	ldr	x8, [x19, #32]
	ldr	w1, [x8, #8]
	mov	w0, #2
	bl	_SOR_XBAR_CTRL_LINK0_XSEL
	mov	x23, x0
	mov	w0, #2
	mov	w1, #2
	bl	_SOR_XBAR_CTRL_LINK1_XSEL
	orr	w8, w23, w24
	orr	w24, w8, w0
	ldr	x8, [x19, #32]
	ldr	w1, [x8, #12]
	mov	w0, #3
	bl	_SOR_XBAR_CTRL_LINK0_XSEL
	mov	x23, x0
	mov	w0, #3
	mov	w1, #3
	bl	_SOR_XBAR_CTRL_LINK1_XSEL
	orr	w8, w23, w24
	orr	w24, w8, w0
	ldr	x8, [x19, #32]
	ldr	w1, [x8, #16]
	mov	w0, #4
	bl	_SOR_XBAR_CTRL_LINK0_XSEL
	mov	x23, x0
	mov	w0, #4
	mov	w1, #4
	bl	_SOR_XBAR_CTRL_LINK1_XSEL
	orr	w8, w23, w24
	orr	w23, w8, w0
Lloh99:
	adrp	x8, _SOR_XBAR_POL@GOTPAGE
Lloh100:
	ldr	x8, [x8, _SOR_XBAR_POL@GOTPAGEOFF]
Lloh101:
	ldr	x2, [x8]
	mov	x0, x19
	mov	w1, #0
	bl	_tegra_sor_writel
Lloh102:
	adrp	x8, _SOR_XBAR_CTRL@GOTPAGE
Lloh103:
	ldr	x8, [x8, _SOR_XBAR_CTRL@GOTPAGEOFF]
Lloh104:
	ldr	x2, [x8]
	mov	x0, x19
	mov	x1, x23
	bl	_tegra_sor_writel
	ldp	w0, w1, [x19, #16]
	bl	_clk_set_parent
	tbnz	w0, #31, LBB0_26
; %bb.12:
	ldr	w1, [x19, #24]
	mov	x0, x19
	bl	_tegra_sor_set_parent_clock
	tbnz	w0, #31, LBB0_27
; %bb.13:
	mov	w8, #1000
	mul	x24, x27, x8
	ldr	w0, [x19, #20]
	bl	_clk_get_rate
                                        ; kill: def $w0 killed $w0 def $x0
	sxtw	x8, w0
	ldr	w9, [x22]
	cmp	w9, w28
	cset	w9, gt
	lsr	x23, x8, x9
	stp	x23, x24, [sp]
Lloh105:
	adrp	x0, l_.str.6@PAGE
Lloh106:
	add	x0, x0, l_.str.6@PAGEOFF
	bl	_DRM_DEBUG_KMS
	ldr	w0, [x19, #16]
	mov	x1, x23
	bl	_clk_set_rate
	ldr	x8, [x19, #8]
	ldr	w8, [x8]
	cbnz	w8, LBB0_15
; %bb.14:
	ldr	x0, [x20, #8]
	bl	_SOR_INPUT_CONTROL_HDMI_SRC_SELECT
	ldr	w8, [x22]
Lloh107:
	adrp	x9, _SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED@GOTPAGE
Lloh108:
	ldr	x9, [x9, _SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED@GOTPAGEOFF]
Lloh109:
	ldr	w9, [x9]
	mov	w10, #9464
	movk	w10, #1, lsl #16
	cmp	w8, w10
	csel	w8, w9, wzr, lt
	orr	w1, w8, w0
Lloh110:
	adrp	x8, _SOR_INPUT_CONTROL@GOTPAGE
Lloh111:
	ldr	x8, [x8, _SOR_INPUT_CONTROL@GOTPAGEOFF]
Lloh112:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_tegra_sor_writel
LBB0_15:
Lloh113:
	adrp	x23, _SOR_REKEY@GOTPAGE
Lloh114:
	ldr	x23, [x23, _SOR_REKEY@GOTPAGEOFF]
	ldp	w8, w9, [x22, #4]
	ldr	w10, [x23]
	add	w9, w9, w10
	sub	w8, w8, w9
	sub	w9, w8, #18
	add	w8, w8, #13
	cmp	w9, #0
	csel	w8, w8, w9, lt
	asr	w0, w8, #5
Lloh115:
	adrp	x8, _SOR_HDMI_CTRL_ENABLE@GOTPAGE
Lloh116:
	ldr	x8, [x8, _SOR_HDMI_CTRL_ENABLE@GOTPAGEOFF]
Lloh117:
	ldr	w24, [x8]
	bl	_SOR_HDMI_CTRL_MAX_AC_PACKET
	orr	w8, w0, w24
Lloh118:
	adrp	x9, _SOR_HDMI_CTRL_AUDIO_LAYOUT@GOTPAGE
Lloh119:
	ldr	x9, [x9, _SOR_HDMI_CTRL_AUDIO_LAYOUT@GOTPAGEOFF]
Lloh120:
	ldr	w9, [x9]
	orr	w24, w8, w9
	ldr	w0, [x23]
	bl	_SOR_HDMI_CTRL_REKEY
	orr	w1, w24, w0
Lloh121:
	adrp	x8, _SOR_HDMI_CTRL@GOTPAGE
Lloh122:
	ldr	x8, [x8, _SOR_HDMI_CTRL@GOTPAGEOFF]
Lloh123:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_tegra_sor_writel
	ldr	x8, [x20]
	ldr	x8, [x8]
	cbnz	x8, LBB0_17
; %bb.16:
	ldr	w8, [x22, #16]
	ldr	w9, [x22, #4]
Lloh124:
	adrp	x10, _PULSE_LAST_END_A@GOTPAGE
Lloh125:
	ldr	x10, [x10, _PULSE_LAST_END_A@GOTPAGEOFF]
	sub	w24, w9, w8
Lloh126:
	ldr	w8, [x10]
Lloh127:
	adrp	x9, _PULSE_QUAL_VACTIVE@GOTPAGE
Lloh128:
	ldr	x9, [x9, _PULSE_QUAL_VACTIVE@GOTPAGEOFF]
Lloh129:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh130:
	adrp	x9, _PULSE_POLARITY_HIGH@GOTPAGE
Lloh131:
	ldr	x9, [x9, _PULSE_POLARITY_HIGH@GOTPAGEOFF]
Lloh132:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh133:
	adrp	x9, _PULSE_MODE_NORMAL@GOTPAGE
Lloh134:
	ldr	x9, [x9, _PULSE_MODE_NORMAL@GOTPAGEOFF]
	sub	w23, w24, #9
Lloh135:
	ldr	w9, [x9]
	orr	w1, w8, w9
Lloh136:
	adrp	x8, _DC_DISP_H_PULSE2_CONTROL@GOTPAGE
Lloh137:
	ldr	x8, [x8, _DC_DISP_H_PULSE2_CONTROL@GOTPAGEOFF]
Lloh138:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_tegra_dc_writel
	sub	w0, w24, #1
	bl	_PULSE_END
	mov	x24, x0
	mov	x0, x23
	bl	_PULSE_START
	orr	w1, w0, w24
Lloh139:
	adrp	x8, _DC_DISP_H_PULSE2_POSITION_A@GOTPAGE
Lloh140:
	ldr	x8, [x8, _DC_DISP_H_PULSE2_POSITION_A@GOTPAGEOFF]
Lloh141:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_tegra_dc_writel
Lloh142:
	adrp	x23, _DC_DISP_DISP_SIGNAL_OPTIONS0@GOTPAGE
Lloh143:
	ldr	x23, [x23, _DC_DISP_DISP_SIGNAL_OPTIONS0@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x20
	bl	_tegra_dc_readl
Lloh144:
	adrp	x8, _H_PULSE2_ENABLE@GOTPAGE
Lloh145:
	ldr	x8, [x8, _H_PULSE2_ENABLE@GOTPAGEOFF]
Lloh146:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w2, [x23]
	mov	x0, x20
	bl	_tegra_dc_writel
LBB0_17:
	mov	x0, x19
	mov	x1, x22
	bl	_tegra_sor_hdmi_setup_avi_infoframe
	tbz	w0, #31, LBB0_19
; %bb.18:
	mov	x2, x0
	ldr	w0, [x19, #4]
Lloh147:
	adrp	x1, l_.str.7@PAGE
Lloh148:
	add	x1, x1, l_.str.7@PAGEOFF
	bl	_dev_err
LBB0_19:
	mov	x0, x19
	bl	_tegra_sor_hdmi_disable_audio_infoframe
Lloh149:
	adrp	x24, _SOR_STATE1@GOTPAGE
Lloh150:
	ldr	x24, [x24, _SOR_STATE1@GOTPAGEOFF]
	ldr	x1, [x24]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh151:
	adrp	x8, _SOR_STATE_ASY_PROTOCOL_MASK@GOTPAGE
Lloh152:
	ldr	x8, [x8, _SOR_STATE_ASY_PROTOCOL_MASK@GOTPAGEOFF]
Lloh153:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh154:
	adrp	x9, _SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A@GOTPAGE
Lloh155:
	ldr	x9, [x9, _SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A@GOTPAGEOFF]
Lloh156:
	ldr	w9, [x9]
	orr	w1, w8, w9
	ldr	x2, [x24]
	mov	x0, x19
	bl	_tegra_sor_writel
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x1, [x8, #8]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh157:
	adrp	x27, _SOR_DP_PADCTL_PAD_CAL_PD@GOTPAGE
Lloh158:
	ldr	x27, [x27, _SOR_DP_PADCTL_PAD_CAL_PD@GOTPAGEOFF]
	ldr	w8, [x27]
	bic	w1, w0, w8
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x2, [x8, #8]
	mov	x0, x19
	bl	_tegra_sor_writel
	ldr	w8, [x22]
	mov	w28, #1000
	mul	w1, w8, w28
	mov	x0, x19
	bl	_tegra_sor_hdmi_find_settings
	cbz	x0, LBB0_28
; %bb.20:
	mov	x23, x0
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x1, [x8, #40]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh159:
	adrp	x8, _SOR_PLL0_ICHPMP_MASK@GOTPAGE
Lloh160:
	ldr	x8, [x8, _SOR_PLL0_ICHPMP_MASK@GOTPAGEOFF]
Lloh161:
	ldr	w8, [x8]
Lloh162:
	adrp	x9, _SOR_PLL0_FILTER_MASK@GOTPAGE
Lloh163:
	ldr	x9, [x9, _SOR_PLL0_FILTER_MASK@GOTPAGEOFF]
Lloh164:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh165:
	adrp	x9, _SOR_PLL0_VCOCAP_MASK@GOTPAGE
Lloh166:
	ldr	x9, [x9, _SOR_PLL0_VCOCAP_MASK@GOTPAGEOFF]
Lloh167:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w28, w0, w8
	ldr	w0, [x23, #56]
	bl	_SOR_PLL0_ICHPMP
	orr	w28, w28, w0
	ldr	w0, [x23, #52]
	bl	_SOR_PLL0_FILTER
	orr	w28, w28, w0
	ldr	w0, [x23, #48]
	bl	_SOR_PLL0_VCOCAP
	orr	w1, w28, w0
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x2, [x8, #40]
	mov	x0, x19
	bl	_tegra_sor_writel
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x1, [x8, #32]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh168:
	adrp	x8, _SOR_PLL1_LOADADJ_MASK@GOTPAGE
Lloh169:
	ldr	x8, [x8, _SOR_PLL1_LOADADJ_MASK@GOTPAGEOFF]
Lloh170:
	ldr	w8, [x8]
Lloh171:
	adrp	x9, _SOR_PLL1_TMDS_TERMADJ_MASK@GOTPAGE
Lloh172:
	ldr	x9, [x9, _SOR_PLL1_TMDS_TERMADJ_MASK@GOTPAGEOFF]
Lloh173:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w28, w0, w8
	ldr	w0, [x23, #44]
	bl	_SOR_PLL1_LOADADJ
	orr	w28, w28, w0
	ldr	w0, [x23, #40]
	bl	_SOR_PLL1_TMDS_TERMADJ
Lloh174:
	adrp	x8, _SOR_PLL1_TMDS_TERM@GOTPAGE
Lloh175:
	ldr	x8, [x8, _SOR_PLL1_TMDS_TERM@GOTPAGEOFF]
	orr	w9, w28, w0
Lloh176:
	ldr	w8, [x8]
	orr	w1, w9, w8
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x2, [x8, #32]
	mov	x0, x19
	bl	_tegra_sor_writel
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x1, [x8, #24]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh177:
	adrp	x8, _SOR_PLL3_BG_TEMP_COEF_MASK@GOTPAGE
Lloh178:
	ldr	x8, [x8, _SOR_PLL3_BG_TEMP_COEF_MASK@GOTPAGEOFF]
Lloh179:
	ldr	w8, [x8]
Lloh180:
	adrp	x9, _SOR_PLL3_BG_VREF_LEVEL_MASK@GOTPAGE
Lloh181:
	ldr	x9, [x9, _SOR_PLL3_BG_VREF_LEVEL_MASK@GOTPAGEOFF]
Lloh182:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh183:
	adrp	x9, _SOR_PLL3_AVDD10_LEVEL_MASK@GOTPAGE
Lloh184:
	ldr	x9, [x9, _SOR_PLL3_AVDD10_LEVEL_MASK@GOTPAGEOFF]
Lloh185:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh186:
	adrp	x9, _SOR_PLL3_AVDD14_LEVEL_MASK@GOTPAGE
Lloh187:
	ldr	x9, [x9, _SOR_PLL3_AVDD14_LEVEL_MASK@GOTPAGEOFF]
Lloh188:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w28, w0, w8
	ldr	w0, [x23, #36]
	bl	_SOR_PLL3_BG_TEMP_COEF
	orr	w28, w28, w0
	ldr	w0, [x23, #32]
	bl	_SOR_PLL3_BG_VREF_LEVEL
	orr	w28, w28, w0
	ldr	w0, [x23, #28]
	bl	_SOR_PLL3_AVDD10_LEVEL
	orr	w28, w28, w0
	ldr	w0, [x23, #24]
	bl	_SOR_PLL3_AVDD14_LEVEL
	orr	w1, w28, w0
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x2, [x8, #24]
	mov	x0, x19
	bl	_tegra_sor_writel
	ldr	x8, [x23]
	ldp	w10, w9, [x8, #8]
	lsl	w10, w10, #16
	orr	w9, w10, w9, lsl #24
	ldp	w8, w10, [x8]
	orr	w9, w9, w10, lsl #8
	orr	w1, w9, w8
Lloh189:
	adrp	x8, _SOR_LANE_DRIVE_CURRENT0@GOTPAGE
Lloh190:
	ldr	x8, [x8, _SOR_LANE_DRIVE_CURRENT0@GOTPAGEOFF]
Lloh191:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_tegra_sor_writel
	ldr	x8, [x23, #8]
	ldp	w10, w9, [x8, #8]
	lsl	w10, w10, #16
	orr	w9, w10, w9, lsl #24
	ldp	w8, w10, [x8]
	orr	w9, w9, w10, lsl #8
	orr	w1, w9, w8
Lloh192:
	adrp	x8, _SOR_LANE_PREEMPHASIS0@GOTPAGE
Lloh193:
	ldr	x8, [x8, _SOR_LANE_PREEMPHASIS0@GOTPAGEOFF]
Lloh194:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_tegra_sor_writel
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x1, [x8, #8]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh195:
	adrp	x8, _SOR_DP_PADCTL_TX_PU_MASK@GOTPAGE
Lloh196:
	ldr	x8, [x8, _SOR_DP_PADCTL_TX_PU_MASK@GOTPAGEOFF]
Lloh197:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh198:
	adrp	x9, _SOR_DP_PADCTL_TX_PU_ENABLE@GOTPAGE
Lloh199:
	ldr	x9, [x9, _SOR_DP_PADCTL_TX_PU_ENABLE@GOTPAGEOFF]
Lloh200:
	ldr	w9, [x9]
	orr	w28, w8, w9
	ldr	w0, [x23, #20]
	bl	_SOR_DP_PADCTL_TX_PU
	orr	w1, w28, w0
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x2, [x8, #8]
	mov	x0, x19
	bl	_tegra_sor_writel
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x1, [x8, #16]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh201:
	adrp	x8, _SOR_DP_PADCTL_SPAREPLL_MASK@GOTPAGE
Lloh202:
	ldr	x8, [x8, _SOR_DP_PADCTL_SPAREPLL_MASK@GOTPAGEOFF]
Lloh203:
	ldr	w8, [x8]
	bic	w28, w0, w8
	ldr	w0, [x23, #16]
	bl	_SOR_DP_PADCTL_SPAREPLL
	orr	w1, w0, w28
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x2, [x8, #16]
	mov	x0, x19
	bl	_tegra_sor_writel
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x1, [x8, #8]
	mov	x0, x19
	bl	_tegra_sor_readl
	ldr	w8, [x27]
	orr	w1, w8, w0
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x2, [x8, #8]
	mov	x0, x19
	bl	_tegra_sor_writel
	ldr	x8, [x20]
	ldr	x8, [x8]
	cbnz	x8, LBB0_22
; %bb.21:
	mov	w0, #1
	bl	_VSYNC_H_POSITION
	mov	x1, x0
Lloh204:
	adrp	x8, _DC_DISP_DISP_TIMING_OPTIONS@GOTPAGE
Lloh205:
	ldr	x8, [x8, _DC_DISP_DISP_TIMING_OPTIONS@GOTPAGEOFF]
Lloh206:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_tegra_dc_writel
LBB0_22:
Lloh207:
	adrp	x23, _DC_DISP_DISP_COLOR_CONTROL@GOTPAGE
Lloh208:
	ldr	x23, [x23, _DC_DISP_DISP_COLOR_CONTROL@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x20
	bl	_tegra_dc_readl
Lloh209:
	adrp	x8, _DITHER_CONTROL_MASK@GOTPAGE
Lloh210:
	ldr	x8, [x8, _DITHER_CONTROL_MASK@GOTPAGEOFF]
Lloh211:
	ldr	w8, [x8]
Lloh212:
	adrp	x9, _BASE_COLOR_SIZE_MASK@GOTPAGE
Lloh213:
	ldr	x9, [x9, _BASE_COLOR_SIZE_MASK@GOTPAGEOFF]
Lloh214:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w27, w0, w8
	ldr	w2, [x21]
	sub	w8, w2, #6
	cmp	w8, #7
	b.hs	LBB0_24
; %bb.23:
	mov	w9, #85
	lsr	w9, w9, w8
	tbnz	w9, #0, LBB0_30
LBB0_24:
Lloh215:
	adrp	x1, l_.str.9@PAGE
Lloh216:
	add	x1, x1, l_.str.9@PAGEOFF
	mov	w0, #1
	bl	_WARN
Lloh217:
	adrp	x8, _BASE_COLOR_SIZE_888@GOTPAGE
Lloh218:
	ldr	x8, [x8, _BASE_COLOR_SIZE_888@GOTPAGEOFF]
	b	LBB0_31
LBB0_25:
	mov	x2, x0
	ldr	w0, [x19, #4]
Lloh219:
	adrp	x1, l_.str@PAGE
Lloh220:
	add	x1, x1, l_.str@PAGEOFF
	b	LBB0_29
LBB0_26:
	mov	x2, x0
	ldr	w0, [x19, #4]
Lloh221:
	adrp	x1, l_.str.4@PAGE
Lloh222:
	add	x1, x1, l_.str.4@PAGEOFF
	b	LBB0_29
LBB0_27:
	mov	x2, x0
	ldr	w0, [x19, #4]
Lloh223:
	adrp	x1, l_.str.5@PAGE
Lloh224:
	add	x1, x1, l_.str.5@PAGEOFF
	b	LBB0_29
LBB0_28:
	ldr	w0, [x19, #4]
	ldr	w8, [x22]
	mul	w2, w8, w28
Lloh225:
	adrp	x1, l_.str.8@PAGE
Lloh226:
	add	x1, x1, l_.str.8@PAGEOFF
LBB0_29:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	b	_dev_err
LBB0_30:
Lloh227:
	adrp	x9, l_switch.table.tegra_sor_hdmi_enable@PAGE
Lloh228:
	add	x9, x9, l_switch.table.tegra_sor_hdmi_enable@PAGEOFF
	ldr	x8, [x9, w8, sxtw #3]
LBB0_31:
	ldr	w8, [x8]
	orr	w1, w8, w27
	ldr	w2, [x23]
	mov	x0, x20
	bl	_tegra_dc_writel
	ldr	x1, [x24]
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh229:
	adrp	x8, _SOR_STATE_ASY_OWNER_MASK@GOTPAGE
Lloh230:
	ldr	x8, [x8, _SOR_STATE_ASY_OWNER_MASK@GOTPAGEOFF]
Lloh231:
	ldr	w8, [x8]
	bic	w23, w0, w8
	ldr	x8, [x20, #8]
	add	x0, x8, #1
	bl	_SOR_STATE_ASY_OWNER
	orr	w1, w0, w23
	ldr	x2, [x24]
	mov	x0, x19
	bl	_tegra_sor_writel
	mov	x0, x19
	mov	w1, #250
	bl	_tegra_sor_power_up
	tbz	w0, #31, LBB0_33
; %bb.32:
	mov	x2, x0
	ldr	w0, [x19, #4]
Lloh232:
	adrp	x1, l_.str.10@PAGE
Lloh233:
	add	x1, x1, l_.str.10@PAGEOFF
	bl	_dev_err
LBB0_33:
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x8, [x8]
	ldr	x9, [x20, #8]
	add	x1, x9, x8
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh234:
	adrp	x8, _SOR_HEAD_STATE_RANGECOMPRESS_MASK@GOTPAGE
Lloh235:
	ldr	x8, [x8, _SOR_HEAD_STATE_RANGECOMPRESS_MASK@GOTPAGEOFF]
Lloh236:
	ldr	w8, [x8]
Lloh237:
	adrp	x9, _SOR_HEAD_STATE_DYNRANGE_MASK@GOTPAGE
Lloh238:
	ldr	x9, [x9, _SOR_HEAD_STATE_DYNRANGE_MASK@GOTPAGEOFF]
Lloh239:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w1, w0, w8
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x8, [x8]
	ldr	x9, [x20, #8]
	add	x2, x9, x8
	mov	x0, x19
	bl	_tegra_sor_writel
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x8, [x8]
	ldr	x9, [x20, #8]
	add	x1, x9, x8
	mov	x0, x19
	bl	_tegra_sor_readl
Lloh240:
	adrp	x8, _SOR_HEAD_STATE_COLORSPACE_MASK@GOTPAGE
Lloh241:
	ldr	x8, [x8, _SOR_HEAD_STATE_COLORSPACE_MASK@GOTPAGEOFF]
Lloh242:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh243:
	adrp	x9, _SOR_HEAD_STATE_COLORSPACE_RGB@GOTPAGE
Lloh244:
	ldr	x9, [x9, _SOR_HEAD_STATE_COLORSPACE_RGB@GOTPAGEOFF]
Lloh245:
	ldr	w9, [x9]
	orr	w1, w8, w9
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x8, [x8]
	ldr	x9, [x20, #8]
	add	x2, x9, x8
	mov	x0, x19
	bl	_tegra_sor_writel
	mov	x0, x19
	mov	x1, x22
	mov	x2, x21
	bl	_tegra_sor_mode_set
	mov	x0, x19
	bl	_tegra_sor_update
	ldr	x1, [x25]
	mov	x0, x19
	bl	_tegra_sor_readl
	ldr	w8, [x26]
	bic	w1, w0, w8
	ldr	x2, [x25]
	mov	x0, x19
	bl	_tegra_sor_writel
	mov	x0, x19
	bl	_tegra_sor_attach
	tbz	w0, #31, LBB0_35
; %bb.34:
	mov	x2, x0
	ldr	w0, [x19, #4]
Lloh246:
	adrp	x1, l_.str.11@PAGE
Lloh247:
	add	x1, x1, l_.str.11@PAGEOFF
	bl	_dev_err
LBB0_35:
Lloh248:
	adrp	x22, _DC_DISP_DISP_WIN_OPTIONS@GOTPAGE
Lloh249:
	ldr	x22, [x22, _DC_DISP_DISP_WIN_OPTIONS@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x20
	bl	_tegra_dc_readl
	mov	x21, x0
	ldr	x8, [x19, #8]
	ldr	w8, [x8]
	cbz	w8, LBB0_37
; %bb.36:
	ldr	w0, [x19]
	bl	_SOR_ENABLE
	b	LBB0_38
LBB0_37:
	mov	w0, #1
	bl	_SOR_ENABLE
Lloh250:
	adrp	x8, _SOR1_TIMING_CYA@GOTPAGE
Lloh251:
	ldr	x8, [x8, _SOR1_TIMING_CYA@GOTPAGEOFF]
Lloh252:
	ldr	w8, [x8]
	orr	w0, w8, w0
LBB0_38:
	orr	w1, w0, w21
	ldr	w2, [x22]
	mov	x0, x20
	bl	_tegra_dc_writel
	ldr	x8, [x20]
	ldr	x8, [x8]
	cbz	x8, LBB0_40
; %bb.39:
	ldr	w0, [x19]
	bl	_DC_DISP_CORE_SOR_SET_CONTROL
	mov	x1, x0
	mov	x0, x20
	bl	_tegra_dc_readl
Lloh253:
	adrp	x8, _PROTOCOL_MASK@GOTPAGE
Lloh254:
	ldr	x8, [x8, _PROTOCOL_MASK@GOTPAGEOFF]
Lloh255:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh256:
	adrp	x9, _PROTOCOL_SINGLE_TMDS_A@GOTPAGE
Lloh257:
	ldr	x9, [x9, _PROTOCOL_SINGLE_TMDS_A@GOTPAGEOFF]
Lloh258:
	ldr	w9, [x9]
	orr	w21, w8, w9
	ldr	w0, [x19]
	bl	_DC_DISP_CORE_SOR_SET_CONTROL
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_tegra_dc_writel
LBB0_40:
	mov	x0, x20
	bl	_tegra_dc_commit
	mov	x0, x19
	bl	_tegra_sor_wakeup
	tbz	w0, #31, LBB0_42
; %bb.41:
	mov	x2, x0
	ldr	w0, [x19, #4]
Lloh259:
	adrp	x1, l_.str.12@PAGE
Lloh260:
	add	x1, x1, l_.str.12@PAGEOFF
	bl	_dev_err
LBB0_42:
	mov	x0, x19
	bl	_tegra_sor_hdmi_scdc_start
	mov	x0, x19
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	b	_tegra_sor_audio_prepare
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh30
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGot	Lloh73, Lloh74
	.loh AdrpLdrGot	Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGot	Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpLdrGot	Lloh59, Lloh60
	.loh AdrpAdd	Lloh57, Lloh58
	.loh AdrpAdd	Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh53
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpAdd	Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.loh AdrpLdrGot	Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh144, Lloh145, Lloh146
	.loh AdrpLdrGot	Lloh142, Lloh143
	.loh AdrpLdrGotLdr	Lloh139, Lloh140, Lloh141
	.loh AdrpLdrGotLdr	Lloh136, Lloh137, Lloh138
	.loh AdrpLdrGotLdr	Lloh133, Lloh134, Lloh135
	.loh AdrpLdrGotLdr	Lloh130, Lloh131, Lloh132
	.loh AdrpLdrGotLdr	Lloh127, Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpAdd	Lloh147, Lloh148
	.loh AdrpLdrGot	Lloh157, Lloh158
	.loh AdrpLdrGotLdr	Lloh154, Lloh155, Lloh156
	.loh AdrpLdrGotLdr	Lloh151, Lloh152, Lloh153
	.loh AdrpLdrGot	Lloh149, Lloh150
	.loh AdrpLdrGotLdr	Lloh201, Lloh202, Lloh203
	.loh AdrpLdrGotLdr	Lloh198, Lloh199, Lloh200
	.loh AdrpLdrGotLdr	Lloh195, Lloh196, Lloh197
	.loh AdrpLdrGotLdr	Lloh192, Lloh193, Lloh194
	.loh AdrpLdrGotLdr	Lloh189, Lloh190, Lloh191
	.loh AdrpLdrGotLdr	Lloh186, Lloh187, Lloh188
	.loh AdrpLdrGotLdr	Lloh183, Lloh184, Lloh185
	.loh AdrpLdrGotLdr	Lloh180, Lloh181, Lloh182
	.loh AdrpLdrGotLdr	Lloh177, Lloh178, Lloh179
	.loh AdrpLdrGotLdr	Lloh174, Lloh175, Lloh176
	.loh AdrpLdrGotLdr	Lloh171, Lloh172, Lloh173
	.loh AdrpLdrGotLdr	Lloh168, Lloh169, Lloh170
	.loh AdrpLdrGotLdr	Lloh165, Lloh166, Lloh167
	.loh AdrpLdrGotLdr	Lloh162, Lloh163, Lloh164
	.loh AdrpLdrGotLdr	Lloh159, Lloh160, Lloh161
	.loh AdrpLdrGotLdr	Lloh204, Lloh205, Lloh206
	.loh AdrpLdrGotLdr	Lloh212, Lloh213, Lloh214
	.loh AdrpLdrGotLdr	Lloh209, Lloh210, Lloh211
	.loh AdrpLdrGot	Lloh207, Lloh208
	.loh AdrpLdrGot	Lloh217, Lloh218
	.loh AdrpAdd	Lloh215, Lloh216
	.loh AdrpAdd	Lloh219, Lloh220
	.loh AdrpAdd	Lloh221, Lloh222
	.loh AdrpAdd	Lloh223, Lloh224
	.loh AdrpAdd	Lloh225, Lloh226
	.loh AdrpAdd	Lloh227, Lloh228
	.loh AdrpLdrGotLdr	Lloh229, Lloh230, Lloh231
	.loh AdrpAdd	Lloh232, Lloh233
	.loh AdrpLdrGotLdr	Lloh243, Lloh244, Lloh245
	.loh AdrpLdrGotLdr	Lloh240, Lloh241, Lloh242
	.loh AdrpLdrGotLdr	Lloh237, Lloh238, Lloh239
	.loh AdrpLdrGotLdr	Lloh234, Lloh235, Lloh236
	.loh AdrpAdd	Lloh246, Lloh247
	.loh AdrpLdrGot	Lloh248, Lloh249
	.loh AdrpLdrGotLdr	Lloh250, Lloh251, Lloh252
	.loh AdrpLdrGotLdr	Lloh256, Lloh257, Lloh258
	.loh AdrpLdrGotLdr	Lloh253, Lloh254, Lloh255
	.loh AdrpAdd	Lloh259, Lloh260
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"failed to set safe parent clock: %d\n"

l_.str.1:                               ; @.str.1
	.asciz	"failed to power on I/O pad: %d\n"

	.comm	_SOR_PLL2_BANDGAP_POWERDOWN,4,2 ; @SOR_PLL2_BANDGAP_POWERDOWN
	.comm	_SOR_PLL3_PLL_VDD_MODE_3V3,4,2  ; @SOR_PLL3_PLL_VDD_MODE_3V3
	.comm	_SOR_PLL0_VCOPD,4,2             ; @SOR_PLL0_VCOPD
	.comm	_SOR_PLL0_PWR,4,2               ; @SOR_PLL0_PWR
	.comm	_SOR_PLL2_SEQ_PLLCAPPD_ENFORCE,4,2 ; @SOR_PLL2_SEQ_PLLCAPPD_ENFORCE
	.comm	_SOR_PLL2_POWERDOWN_OVERRIDE,4,2 ; @SOR_PLL2_POWERDOWN_OVERRIDE
	.comm	_SOR_PLL2_PORT_POWERDOWN,4,2    ; @SOR_PLL2_PORT_POWERDOWN
	.comm	_SOR_DP_PADCTL_PD_TXD_3,4,2     ; @SOR_DP_PADCTL_PD_TXD_3
	.comm	_SOR_DP_PADCTL_PD_TXD_0,4,2     ; @SOR_DP_PADCTL_PD_TXD_0
	.comm	_SOR_DP_PADCTL_PD_TXD_1,4,2     ; @SOR_DP_PADCTL_PD_TXD_1
	.comm	_SOR_DP_PADCTL_PD_TXD_2,4,2     ; @SOR_DP_PADCTL_PD_TXD_2
	.comm	_SOR_LANE_SEQ_CTL,8,3           ; @SOR_LANE_SEQ_CTL
	.comm	_SOR_LANE_SEQ_CTL_STATE_BUSY,4,2 ; @SOR_LANE_SEQ_CTL_STATE_BUSY
	.comm	_SOR_LANE_SEQ_CTL_TRIGGER,4,2   ; @SOR_LANE_SEQ_CTL_TRIGGER
	.comm	_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN,4,2 ; @SOR_LANE_SEQ_CTL_SEQUENCE_DOWN
	.comm	_SOR_LANE_SEQ_CTL_POWER_STATE_UP,4,2 ; @SOR_LANE_SEQ_CTL_POWER_STATE_UP
	.comm	_SOR_CLK_CNTRL,8,3              ; @SOR_CLK_CNTRL
	.comm	_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK,4,2 ; @SOR_CLK_CNTRL_DP_LINK_SPEED_MASK
	.comm	_SOR_CLK_CNTRL_DP_CLK_SEL_MASK,4,2 ; @SOR_CLK_CNTRL_DP_CLK_SEL_MASK
l_.str.2:                               ; @.str.2
	.asciz	"setting 2.7 GHz link speed\n"

	.comm	_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70,4,2 ; @SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70
l_.str.3:                               ; @.str.3
	.asciz	"setting 5.4 GHz link speed\n"

	.comm	_SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40,4,2 ; @SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40
	.comm	_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK,4,2 ; @SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK
	.comm	_SOR_DP_LINKCTL0,8,3            ; @SOR_DP_LINKCTL0
	.comm	_SOR_DP_LINKCTL_LANE_COUNT_MASK,4,2 ; @SOR_DP_LINKCTL_LANE_COUNT_MASK
	.comm	_SOR_DP_SPARE0,8,3              ; @SOR_DP_SPARE0
	.comm	_SOR_DP_SPARE_DISP_VIDEO_PREAMBLE,4,2 ; @SOR_DP_SPARE_DISP_VIDEO_PREAMBLE
	.comm	_SOR_DP_SPARE_PANEL_INTERNAL,4,2 ; @SOR_DP_SPARE_PANEL_INTERNAL
	.comm	_SOR_DP_SPARE_SEQ_ENABLE,4,2    ; @SOR_DP_SPARE_SEQ_ENABLE
	.comm	_SOR_DP_SPARE_MACRO_SOR_CLK,4,2 ; @SOR_DP_SPARE_MACRO_SOR_CLK
	.comm	_SOR_SEQ_CTL,8,3                ; @SOR_SEQ_CTL
	.comm	_SOR_SEQ_INST_DRIVE_PWM_OUT_LO,4,2 ; @SOR_SEQ_INST_DRIVE_PWM_OUT_LO
	.comm	_SOR_SEQ_INST_HALT,4,2          ; @SOR_SEQ_INST_HALT
	.comm	_SOR_SEQ_INST_WAIT_VSYNC,4,2    ; @SOR_SEQ_INST_WAIT_VSYNC
	.comm	_SOR_REFCLK,8,3                 ; @SOR_REFCLK
	.comm	_SOR_XBAR_POL,8,3               ; @SOR_XBAR_POL
	.comm	_SOR_XBAR_CTRL,8,3              ; @SOR_XBAR_CTRL
l_.str.4:                               ; @.str.4
	.asciz	"failed to set parent clock: %d\n"

l_.str.5:                               ; @.str.5
	.asciz	"failed to set pad clock: %d\n"

l_.str.6:                               ; @.str.6
	.asciz	"setting clock to %lu Hz, mode: %lu Hz\n"

	.comm	_SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED,4,2 ; @SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED
	.comm	_SOR_INPUT_CONTROL,8,3          ; @SOR_INPUT_CONTROL
	.comm	_SOR_REKEY,4,2                  ; @SOR_REKEY
	.comm	_SOR_HDMI_CTRL_ENABLE,4,2       ; @SOR_HDMI_CTRL_ENABLE
	.comm	_SOR_HDMI_CTRL_AUDIO_LAYOUT,4,2 ; @SOR_HDMI_CTRL_AUDIO_LAYOUT
	.comm	_SOR_HDMI_CTRL,8,3              ; @SOR_HDMI_CTRL
	.comm	_PULSE_LAST_END_A,4,2           ; @PULSE_LAST_END_A
	.comm	_PULSE_QUAL_VACTIVE,4,2         ; @PULSE_QUAL_VACTIVE
	.comm	_PULSE_POLARITY_HIGH,4,2        ; @PULSE_POLARITY_HIGH
	.comm	_PULSE_MODE_NORMAL,4,2          ; @PULSE_MODE_NORMAL
	.comm	_DC_DISP_H_PULSE2_CONTROL,4,2   ; @DC_DISP_H_PULSE2_CONTROL
	.comm	_DC_DISP_H_PULSE2_POSITION_A,4,2 ; @DC_DISP_H_PULSE2_POSITION_A
	.comm	_DC_DISP_DISP_SIGNAL_OPTIONS0,4,2 ; @DC_DISP_DISP_SIGNAL_OPTIONS0
	.comm	_H_PULSE2_ENABLE,4,2            ; @H_PULSE2_ENABLE
l_.str.7:                               ; @.str.7
	.asciz	"failed to setup AVI infoframe: %d\n"

	.comm	_SOR_STATE1,8,3                 ; @SOR_STATE1
	.comm	_SOR_STATE_ASY_PROTOCOL_MASK,4,2 ; @SOR_STATE_ASY_PROTOCOL_MASK
	.comm	_SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A,4,2 ; @SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A
	.comm	_SOR_DP_PADCTL_PAD_CAL_PD,4,2   ; @SOR_DP_PADCTL_PAD_CAL_PD
l_.str.8:                               ; @.str.8
	.asciz	"no settings for pixel clock %d Hz\n"

	.comm	_SOR_PLL0_ICHPMP_MASK,4,2       ; @SOR_PLL0_ICHPMP_MASK
	.comm	_SOR_PLL0_FILTER_MASK,4,2       ; @SOR_PLL0_FILTER_MASK
	.comm	_SOR_PLL0_VCOCAP_MASK,4,2       ; @SOR_PLL0_VCOCAP_MASK
	.comm	_SOR_PLL1_LOADADJ_MASK,4,2      ; @SOR_PLL1_LOADADJ_MASK
	.comm	_SOR_PLL1_TMDS_TERMADJ_MASK,4,2 ; @SOR_PLL1_TMDS_TERMADJ_MASK
	.comm	_SOR_PLL1_TMDS_TERM,4,2         ; @SOR_PLL1_TMDS_TERM
	.comm	_SOR_PLL3_BG_TEMP_COEF_MASK,4,2 ; @SOR_PLL3_BG_TEMP_COEF_MASK
	.comm	_SOR_PLL3_BG_VREF_LEVEL_MASK,4,2 ; @SOR_PLL3_BG_VREF_LEVEL_MASK
	.comm	_SOR_PLL3_AVDD10_LEVEL_MASK,4,2 ; @SOR_PLL3_AVDD10_LEVEL_MASK
	.comm	_SOR_PLL3_AVDD14_LEVEL_MASK,4,2 ; @SOR_PLL3_AVDD14_LEVEL_MASK
	.comm	_SOR_LANE_DRIVE_CURRENT0,8,3    ; @SOR_LANE_DRIVE_CURRENT0
	.comm	_SOR_LANE_PREEMPHASIS0,8,3      ; @SOR_LANE_PREEMPHASIS0
	.comm	_SOR_DP_PADCTL_TX_PU_MASK,4,2   ; @SOR_DP_PADCTL_TX_PU_MASK
	.comm	_SOR_DP_PADCTL_TX_PU_ENABLE,4,2 ; @SOR_DP_PADCTL_TX_PU_ENABLE
	.comm	_SOR_DP_PADCTL_SPAREPLL_MASK,4,2 ; @SOR_DP_PADCTL_SPAREPLL_MASK
	.comm	_DC_DISP_DISP_TIMING_OPTIONS,4,2 ; @DC_DISP_DISP_TIMING_OPTIONS
	.comm	_DC_DISP_DISP_COLOR_CONTROL,4,2 ; @DC_DISP_DISP_COLOR_CONTROL
	.comm	_DITHER_CONTROL_MASK,4,2        ; @DITHER_CONTROL_MASK
	.comm	_BASE_COLOR_SIZE_MASK,4,2       ; @BASE_COLOR_SIZE_MASK
	.comm	_BASE_COLOR_SIZE_666,4,2        ; @BASE_COLOR_SIZE_666
	.comm	_BASE_COLOR_SIZE_888,4,2        ; @BASE_COLOR_SIZE_888
	.comm	_BASE_COLOR_SIZE_101010,4,2     ; @BASE_COLOR_SIZE_101010
	.comm	_BASE_COLOR_SIZE_121212,4,2     ; @BASE_COLOR_SIZE_121212
l_.str.9:                               ; @.str.9
	.asciz	"%u bits-per-color not supported\n"

	.comm	_SOR_STATE_ASY_OWNER_MASK,4,2   ; @SOR_STATE_ASY_OWNER_MASK
l_.str.10:                              ; @.str.10
	.asciz	"failed to power up SOR: %d\n"

	.comm	_SOR_HEAD_STATE_RANGECOMPRESS_MASK,4,2 ; @SOR_HEAD_STATE_RANGECOMPRESS_MASK
	.comm	_SOR_HEAD_STATE_DYNRANGE_MASK,4,2 ; @SOR_HEAD_STATE_DYNRANGE_MASK
	.comm	_SOR_HEAD_STATE_COLORSPACE_MASK,4,2 ; @SOR_HEAD_STATE_COLORSPACE_MASK
	.comm	_SOR_HEAD_STATE_COLORSPACE_RGB,4,2 ; @SOR_HEAD_STATE_COLORSPACE_RGB
l_.str.11:                              ; @.str.11
	.asciz	"failed to attach SOR: %d\n"

	.comm	_DC_DISP_DISP_WIN_OPTIONS,4,2   ; @DC_DISP_DISP_WIN_OPTIONS
	.comm	_SOR1_TIMING_CYA,4,2            ; @SOR1_TIMING_CYA
	.comm	_PROTOCOL_MASK,4,2              ; @PROTOCOL_MASK
	.comm	_PROTOCOL_SINGLE_TMDS_A,4,2     ; @PROTOCOL_SINGLE_TMDS_A
l_.str.12:                              ; @.str.12
	.asciz	"failed to wakeup SOR: %d\n"

	.no_dead_strip	_tegra_sor_hdmi_enable
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.tegra_sor_hdmi_enable
l_switch.table.tegra_sor_hdmi_enable:
	.quad	_BASE_COLOR_SIZE_666
	.quad	_BASE_COLOR_SIZE_666
	.quad	_BASE_COLOR_SIZE_888
	.quad	_BASE_COLOR_SIZE_666
	.quad	_BASE_COLOR_SIZE_101010
	.quad	_BASE_COLOR_SIZE_666
	.quad	_BASE_COLOR_SIZE_121212

.subsections_via_symbols
