	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function si_init_golden_registers
_si_init_golden_registers:              ## @si_init_golden_registers
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movl	(%rdi), %eax
	addl	$-128, %eax
	cmpl	$4, %eax
	ja	LBB0_8
## %bb.1:
	movq	%rdi, %rbx
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_5:
	movq	_verde_golden_registers@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%r14d, %edi
	callq	_ARRAY_SIZE
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_amdgpu_device_program_register_sequence
	movq	_verde_golden_rlc_registers@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%r14d, %edi
	callq	_ARRAY_SIZE
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_amdgpu_device_program_register_sequence
	movq	_verde_mgcg_cgcg_init@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%r14d, %edi
	callq	_ARRAY_SIZE
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_amdgpu_device_program_register_sequence
	movq	_verde_pg_init@GOTPCREL(%rip), %rax
	jmp	LBB0_4
LBB0_8:
	xorl	%eax, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_BUG                            ## TAILCALL
LBB0_2:
	movq	_tahiti_golden_registers@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%r14d, %edi
	callq	_ARRAY_SIZE
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_amdgpu_device_program_register_sequence
	movq	_tahiti_golden_rlc_registers@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%r14d, %edi
	callq	_ARRAY_SIZE
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_amdgpu_device_program_register_sequence
	movq	_tahiti_mgcg_cgcg_init@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%r14d, %edi
	callq	_ARRAY_SIZE
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_amdgpu_device_program_register_sequence
	movq	_tahiti_golden_registers2@GOTPCREL(%rip), %rax
	jmp	LBB0_4
LBB0_3:
	movq	_pitcairn_golden_registers@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%r14d, %edi
	callq	_ARRAY_SIZE
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_amdgpu_device_program_register_sequence
	movq	_pitcairn_golden_rlc_registers@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%r14d, %edi
	callq	_ARRAY_SIZE
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_amdgpu_device_program_register_sequence
	movq	_pitcairn_mgcg_cgcg_init@GOTPCREL(%rip), %rax
	jmp	LBB0_4
LBB0_6:
	movq	_oland_golden_registers@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%r14d, %edi
	callq	_ARRAY_SIZE
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_amdgpu_device_program_register_sequence
	movq	_oland_golden_rlc_registers@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%r14d, %edi
	callq	_ARRAY_SIZE
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_amdgpu_device_program_register_sequence
	movq	_oland_mgcg_cgcg_init@GOTPCREL(%rip), %rax
	jmp	LBB0_4
LBB0_7:
	movq	_hainan_golden_registers@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%r14d, %edi
	callq	_ARRAY_SIZE
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_amdgpu_device_program_register_sequence
	movq	_hainan_golden_registers2@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%r14d, %edi
	callq	_ARRAY_SIZE
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_amdgpu_device_program_register_sequence
	movq	_hainan_mgcg_cgcg_init@GOTPCREL(%rip), %rax
LBB0_4:
	movl	(%rax), %r14d
	movl	%r14d, %edi
	callq	_ARRAY_SIZE
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_amdgpu_device_program_register_sequence ## TAILCALL
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_2, LBB0_2-LJTI0_0
.set L0_0_set_3, LBB0_3-LJTI0_0
.set L0_0_set_6, LBB0_6-LJTI0_0
.set L0_0_set_7, LBB0_7-LJTI0_0
LJTI0_0:
	.long	L0_0_set_5
	.long	L0_0_set_2
	.long	L0_0_set_3
	.long	L0_0_set_6
	.long	L0_0_set_7
	.end_data_region
                                        ## -- End function
	.comm	_tahiti_golden_registers,4,2    ## @tahiti_golden_registers
	.comm	_tahiti_golden_rlc_registers,4,2 ## @tahiti_golden_rlc_registers
	.comm	_tahiti_mgcg_cgcg_init,4,2      ## @tahiti_mgcg_cgcg_init
	.comm	_tahiti_golden_registers2,4,2   ## @tahiti_golden_registers2
	.comm	_pitcairn_golden_registers,4,2  ## @pitcairn_golden_registers
	.comm	_pitcairn_golden_rlc_registers,4,2 ## @pitcairn_golden_rlc_registers
	.comm	_pitcairn_mgcg_cgcg_init,4,2    ## @pitcairn_mgcg_cgcg_init
	.comm	_verde_golden_registers,4,2     ## @verde_golden_registers
	.comm	_verde_golden_rlc_registers,4,2 ## @verde_golden_rlc_registers
	.comm	_verde_mgcg_cgcg_init,4,2       ## @verde_mgcg_cgcg_init
	.comm	_verde_pg_init,4,2              ## @verde_pg_init
	.comm	_oland_golden_registers,4,2     ## @oland_golden_registers
	.comm	_oland_golden_rlc_registers,4,2 ## @oland_golden_rlc_registers
	.comm	_oland_mgcg_cgcg_init,4,2       ## @oland_mgcg_cgcg_init
	.comm	_hainan_golden_registers,4,2    ## @hainan_golden_registers
	.comm	_hainan_golden_registers2,4,2   ## @hainan_golden_registers2
	.comm	_hainan_mgcg_cgcg_init,4,2      ## @hainan_mgcg_cgcg_init
	.no_dead_strip	_si_init_golden_registers
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function si_init_golden_registers
_si_init_golden_registers:              ; @si_init_golden_registers
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	w8, [x0]
	sub	w8, w8, #128
	cmp	w8, #4
	b.hi	LBB0_3
; %bb.1:
	mov	x19, x0
Lloh0:
	adrp	x9, lJTI0_0@PAGE
Lloh1:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_2
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_2:
Lloh2:
	adrp	x8, _verde_golden_registers@GOTPAGE
Lloh3:
	ldr	x8, [x8, _verde_golden_registers@GOTPAGEOFF]
Lloh4:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_device_program_register_sequence
Lloh5:
	adrp	x8, _verde_golden_rlc_registers@GOTPAGE
Lloh6:
	ldr	x8, [x8, _verde_golden_rlc_registers@GOTPAGEOFF]
Lloh7:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_device_program_register_sequence
Lloh8:
	adrp	x8, _verde_mgcg_cgcg_init@GOTPAGE
Lloh9:
	ldr	x8, [x8, _verde_mgcg_cgcg_init@GOTPAGEOFF]
Lloh10:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_device_program_register_sequence
Lloh11:
	adrp	x8, _verde_pg_init@GOTPAGE
Lloh12:
	ldr	x8, [x8, _verde_pg_init@GOTPAGEOFF]
	b	LBB0_8
LBB0_3:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_BUG
LBB0_4:
Lloh13:
	adrp	x8, _tahiti_golden_registers@GOTPAGE
Lloh14:
	ldr	x8, [x8, _tahiti_golden_registers@GOTPAGEOFF]
Lloh15:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_device_program_register_sequence
Lloh16:
	adrp	x8, _tahiti_golden_rlc_registers@GOTPAGE
Lloh17:
	ldr	x8, [x8, _tahiti_golden_rlc_registers@GOTPAGEOFF]
Lloh18:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_device_program_register_sequence
Lloh19:
	adrp	x8, _tahiti_mgcg_cgcg_init@GOTPAGE
Lloh20:
	ldr	x8, [x8, _tahiti_mgcg_cgcg_init@GOTPAGEOFF]
Lloh21:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_device_program_register_sequence
Lloh22:
	adrp	x8, _tahiti_golden_registers2@GOTPAGE
Lloh23:
	ldr	x8, [x8, _tahiti_golden_registers2@GOTPAGEOFF]
	b	LBB0_8
LBB0_5:
Lloh24:
	adrp	x8, _pitcairn_golden_registers@GOTPAGE
Lloh25:
	ldr	x8, [x8, _pitcairn_golden_registers@GOTPAGEOFF]
Lloh26:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_device_program_register_sequence
Lloh27:
	adrp	x8, _pitcairn_golden_rlc_registers@GOTPAGE
Lloh28:
	ldr	x8, [x8, _pitcairn_golden_rlc_registers@GOTPAGEOFF]
Lloh29:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_device_program_register_sequence
Lloh30:
	adrp	x8, _pitcairn_mgcg_cgcg_init@GOTPAGE
Lloh31:
	ldr	x8, [x8, _pitcairn_mgcg_cgcg_init@GOTPAGEOFF]
	b	LBB0_8
LBB0_6:
Lloh32:
	adrp	x8, _oland_golden_registers@GOTPAGE
Lloh33:
	ldr	x8, [x8, _oland_golden_registers@GOTPAGEOFF]
Lloh34:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_device_program_register_sequence
Lloh35:
	adrp	x8, _oland_golden_rlc_registers@GOTPAGE
Lloh36:
	ldr	x8, [x8, _oland_golden_rlc_registers@GOTPAGEOFF]
Lloh37:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_device_program_register_sequence
Lloh38:
	adrp	x8, _oland_mgcg_cgcg_init@GOTPAGE
Lloh39:
	ldr	x8, [x8, _oland_mgcg_cgcg_init@GOTPAGEOFF]
	b	LBB0_8
LBB0_7:
Lloh40:
	adrp	x8, _hainan_golden_registers@GOTPAGE
Lloh41:
	ldr	x8, [x8, _hainan_golden_registers@GOTPAGEOFF]
Lloh42:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_device_program_register_sequence
Lloh43:
	adrp	x8, _hainan_golden_registers2@GOTPAGE
Lloh44:
	ldr	x8, [x8, _hainan_golden_registers2@GOTPAGEOFF]
Lloh45:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_device_program_register_sequence
Lloh46:
	adrp	x8, _hainan_mgcg_cgcg_init@GOTPAGE
Lloh47:
	ldr	x8, [x8, _hainan_mgcg_cgcg_init@GOTPAGEOFF]
LBB0_8:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_ARRAY_SIZE
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_amdgpu_device_program_register_sequence
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_6-LBB0_2)>>2
	.byte	(LBB0_7-LBB0_2)>>2
                                        ; -- End function
	.comm	_tahiti_golden_registers,4,2    ; @tahiti_golden_registers
	.comm	_tahiti_golden_rlc_registers,4,2 ; @tahiti_golden_rlc_registers
	.comm	_tahiti_mgcg_cgcg_init,4,2      ; @tahiti_mgcg_cgcg_init
	.comm	_tahiti_golden_registers2,4,2   ; @tahiti_golden_registers2
	.comm	_pitcairn_golden_registers,4,2  ; @pitcairn_golden_registers
	.comm	_pitcairn_golden_rlc_registers,4,2 ; @pitcairn_golden_rlc_registers
	.comm	_pitcairn_mgcg_cgcg_init,4,2    ; @pitcairn_mgcg_cgcg_init
	.comm	_verde_golden_registers,4,2     ; @verde_golden_registers
	.comm	_verde_golden_rlc_registers,4,2 ; @verde_golden_rlc_registers
	.comm	_verde_mgcg_cgcg_init,4,2       ; @verde_mgcg_cgcg_init
	.comm	_verde_pg_init,4,2              ; @verde_pg_init
	.comm	_oland_golden_registers,4,2     ; @oland_golden_registers
	.comm	_oland_golden_rlc_registers,4,2 ; @oland_golden_rlc_registers
	.comm	_oland_mgcg_cgcg_init,4,2       ; @oland_mgcg_cgcg_init
	.comm	_hainan_golden_registers,4,2    ; @hainan_golden_registers
	.comm	_hainan_golden_registers2,4,2   ; @hainan_golden_registers2
	.comm	_hainan_mgcg_cgcg_init,4,2      ; @hainan_mgcg_cgcg_init
	.no_dead_strip	_si_init_golden_registers
.subsections_via_symbols
