	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v9_0_ngg_en
_gfx_v9_0_ngg_en:                       ## @gfx_v9_0_ngg_en
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_amdgpu_ngg@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	je	LBB0_4
## %bb.1:
	movq	%rdi, %r12
	movq	16(%rdi), %rax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movq	_WD_BUF_RESOURCE_1@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_INDEX_BUF_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	8(%rdi), %rax
	movq	_NGG_PRIM@GOTPCREL(%rip), %rdi
	movq	(%rdi), %rcx
	movq	%rdi, %r13
	movl	(%rax,%rcx,8), %ecx
	sarl	$8, %ecx
	xorl	%edi, %edi
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_POS_BUF_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	8(%r12), %rcx
	movq	_NGG_POS@GOTPCREL(%rip), %rdi
	movq	(%rdi), %rdi
	movl	(%rcx,%rdi,8), %ecx
	sarl	$8, %ecx
	movl	%eax, %edi
	callq	_REG_SET_FIELD
	movq	_GC@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movq	_mmWD_BUF_RESOURCE_1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	_WD_BUF_RESOURCE_2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_CNTL_SB_BUF_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	8(%r12), %rax
	movq	_NGG_CNTL@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	(%rax,%rcx,8), %ecx
	sarl	$8, %ecx
	xorl	%edi, %edi
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_PARAM_BUF_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	8(%r12), %rcx
	movq	_NGG_PARAM@GOTPCREL(%rip), %rdi
	movq	(%rdi), %rdi
	movl	(%rcx,%rdi,8), %ecx
	sarl	$10, %ecx
	movl	%eax, %edi
	callq	_REG_SET_FIELD
	movl	(%r14), %edi
	movq	_mmWD_BUF_RESOURCE_2@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	8(%r12), %rax
	movq	%r13, %rbx
	movq	(%r13), %rcx
	movl	4(%rax,%rcx,8), %edi
	callq	_lower_32_bits
	movq	_WD_INDEX_BUF_BASE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_BASE@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	xorl	%edi, %edi
	movl	%eax, %ecx
	callq	_REG_SET_FIELD
	movl	(%r14), %edi
	movq	_mmWD_INDEX_BUF_BASE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	8(%r12), %rax
	movq	(%rbx), %rcx
	movl	4(%rax,%rcx,8), %edi
	callq	_upper_32_bits
	movq	_WD_INDEX_BUF_BASE_HI@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_BASE_HI@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	xorl	%edi, %edi
	movl	%eax, %ecx
	callq	_REG_SET_FIELD
	movl	(%r14), %edi
	movq	_mmWD_INDEX_BUF_BASE_HI@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	8(%r12), %rax
	movq	_NGG_POS@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rcx
	movl	4(%rax,%rcx,8), %edi
	callq	_lower_32_bits
	movq	_WD_POS_BUF_BASE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	(%r13), %edx
	xorl	%edi, %edi
	movl	%eax, %ecx
	callq	_REG_SET_FIELD
	movl	(%r14), %edi
	movq	_mmWD_POS_BUF_BASE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	8(%r12), %rax
	movq	(%rbx), %rcx
	movl	4(%rax,%rcx,8), %edi
	callq	_upper_32_bits
	movq	_WD_POS_BUF_BASE_HI@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	(%r15), %edx
	xorl	%edi, %edi
	movl	%eax, %ecx
	callq	_REG_SET_FIELD
	movl	(%r14), %edi
	movq	_mmWD_POS_BUF_BASE_HI@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	8(%r12), %rax
	movq	_NGG_CNTL@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rcx
	movl	4(%rax,%rcx,8), %edi
	callq	_lower_32_bits
	movq	_WD_CNTL_SB_BUF_BASE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	(%r13), %edx
	xorl	%edi, %edi
	movl	%eax, %ecx
	callq	_REG_SET_FIELD
	movl	(%r14), %edi
	movq	_mmWD_CNTL_SB_BUF_BASE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	8(%r12), %rax
	movq	(%rbx), %rcx
	movl	4(%rax,%rcx,8), %edi
	callq	_upper_32_bits
	movq	_WD_CNTL_SB_BUF_BASE_HI@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	(%r15), %edx
	movq	-48(%rbp), %r15                 ## 8-byte Reload
	xorl	%edi, %edi
	movl	%eax, %ecx
	callq	_REG_SET_FIELD
	movq	%r14, %r13
	movl	(%r14), %edi
	movq	_mmWD_CNTL_SB_BUF_BASE_HI@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	%r15, %rdi
	movl	$17, %esi
	callq	_amdgpu_ring_alloc
	testl	%eax, %eax
	je	LBB0_3
## %bb.2:
	movl	%eax, %ebx
	movl	(%r15), %esi
	leaq	L_.str(%rip), %rdi
	movl	%eax, %edx
	callq	_DRM_ERROR
	movl	%ebx, %eax
	jmp	LBB0_5
LBB0_3:
	movq	%r13, %r14
	movl	(%r13), %edi
	movq	_mmGDS_VMID0_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movslq	(%r12), %r8
	addq	24(%r12), %r8
	movq	%r15, %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	movl	%eax, %ecx
	callq	_gfx_v9_0_write_data_to_reg
	movq	_PACKET3_DMA_DATA@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$5, %esi
	callq	_PACKET3
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_PACKET3_DMA_DATA_CP_SYNC@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	$1, %edi
	callq	_PACKET3_DMA_DATA_DST_SEL
	movl	%eax, %ebx
	movl	$2, %edi
	callq	_PACKET3_DMA_DATA_SRC_SEL
	orl	%eax, %ebx
	orl	%r13d, %ebx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_amdgpu_ring_write
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
	movl	4(%r12), %esi
	movq	%r15, %rdi
	callq	_amdgpu_ring_write
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
	movq	_PACKET3_DMA_DATA_CMD_RAW_WAIT@GOTPCREL(%rip), %rax
	movl	(%r12), %esi
	orl	(%rax), %esi
	movq	%r15, %rdi
	callq	_amdgpu_ring_write
	movl	(%r14), %edi
	movq	_mmGDS_VMID0_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	%r15, %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	movl	%eax, %ecx
	xorl	%r8d, %r8d
	callq	_gfx_v9_0_write_data_to_reg
	movq	%r15, %rdi
	callq	_amdgpu_ring_commit
LBB0_4:
	xorl	%eax, %eax
LBB0_5:
                                        ## kill: def $eax killed $eax killed $rax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_amdgpu_ngg,4,2                 ## @amdgpu_ngg
	.comm	_WD_BUF_RESOURCE_1,4,2          ## @WD_BUF_RESOURCE_1
	.comm	_INDEX_BUF_SIZE,4,2             ## @INDEX_BUF_SIZE
	.comm	_NGG_PRIM,8,3                   ## @NGG_PRIM
	.comm	_POS_BUF_SIZE,4,2               ## @POS_BUF_SIZE
	.comm	_NGG_POS,8,3                    ## @NGG_POS
	.comm	_GC,4,2                         ## @GC
	.comm	_mmWD_BUF_RESOURCE_1,4,2        ## @mmWD_BUF_RESOURCE_1
	.comm	_WD_BUF_RESOURCE_2,4,2          ## @WD_BUF_RESOURCE_2
	.comm	_CNTL_SB_BUF_SIZE,4,2           ## @CNTL_SB_BUF_SIZE
	.comm	_NGG_CNTL,8,3                   ## @NGG_CNTL
	.comm	_PARAM_BUF_SIZE,4,2             ## @PARAM_BUF_SIZE
	.comm	_NGG_PARAM,8,3                  ## @NGG_PARAM
	.comm	_mmWD_BUF_RESOURCE_2,4,2        ## @mmWD_BUF_RESOURCE_2
	.comm	_WD_INDEX_BUF_BASE,4,2          ## @WD_INDEX_BUF_BASE
	.comm	_BASE,4,2                       ## @BASE
	.comm	_mmWD_INDEX_BUF_BASE,4,2        ## @mmWD_INDEX_BUF_BASE
	.comm	_WD_INDEX_BUF_BASE_HI,4,2       ## @WD_INDEX_BUF_BASE_HI
	.comm	_BASE_HI,4,2                    ## @BASE_HI
	.comm	_mmWD_INDEX_BUF_BASE_HI,4,2     ## @mmWD_INDEX_BUF_BASE_HI
	.comm	_WD_POS_BUF_BASE,4,2            ## @WD_POS_BUF_BASE
	.comm	_mmWD_POS_BUF_BASE,4,2          ## @mmWD_POS_BUF_BASE
	.comm	_WD_POS_BUF_BASE_HI,4,2         ## @WD_POS_BUF_BASE_HI
	.comm	_mmWD_POS_BUF_BASE_HI,4,2       ## @mmWD_POS_BUF_BASE_HI
	.comm	_WD_CNTL_SB_BUF_BASE,4,2        ## @WD_CNTL_SB_BUF_BASE
	.comm	_mmWD_CNTL_SB_BUF_BASE,4,2      ## @mmWD_CNTL_SB_BUF_BASE
	.comm	_WD_CNTL_SB_BUF_BASE_HI,4,2     ## @WD_CNTL_SB_BUF_BASE_HI
	.comm	_mmWD_CNTL_SB_BUF_BASE_HI,4,2   ## @mmWD_CNTL_SB_BUF_BASE_HI
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"amdgpu: NGG failed to lock ring %s (%d).\n"

	.comm	_mmGDS_VMID0_SIZE,4,2           ## @mmGDS_VMID0_SIZE
	.comm	_PACKET3_DMA_DATA,4,2           ## @PACKET3_DMA_DATA
	.comm	_PACKET3_DMA_DATA_CP_SYNC,4,2   ## @PACKET3_DMA_DATA_CP_SYNC
	.comm	_PACKET3_DMA_DATA_CMD_RAW_WAIT,4,2 ## @PACKET3_DMA_DATA_CMD_RAW_WAIT
	.no_dead_strip	_gfx_v9_0_ngg_en
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v9_0_ngg_en
_gfx_v9_0_ngg_en:                       ; @gfx_v9_0_ngg_en
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
Lloh0:
	adrp	x8, _amdgpu_ngg@GOTPAGE
Lloh1:
	ldr	x8, [x8, _amdgpu_ngg@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cbz	w8, LBB0_4
; %bb.1:
	mov	x20, x0
Lloh3:
	adrp	x21, _WD_BUF_RESOURCE_1@GOTPAGE
Lloh4:
	ldr	x21, [x21, _WD_BUF_RESOURCE_1@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh5:
	adrp	x8, _INDEX_BUF_SIZE@GOTPAGE
Lloh6:
	ldr	x8, [x8, _INDEX_BUF_SIZE@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
Lloh8:
	adrp	x25, _NGG_PRIM@GOTPAGE
Lloh9:
	ldr	x25, [x25, _NGG_PRIM@GOTPAGEOFF]
	ldp	x8, x19, [x0, #8]
	ldr	x9, [x25]
	lsl	x9, x9, #3
	ldr	w8, [x8, x9]
	asr	w3, w8, #8
	mov	w0, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x21]
Lloh10:
	adrp	x8, _POS_BUF_SIZE@GOTPAGE
Lloh11:
	ldr	x8, [x8, _POS_BUF_SIZE@GOTPAGEOFF]
Lloh12:
	ldr	w2, [x8]
Lloh13:
	adrp	x23, _NGG_POS@GOTPAGE
Lloh14:
	ldr	x23, [x23, _NGG_POS@GOTPAGEOFF]
	ldr	x8, [x20, #8]
	ldr	x9, [x23]
	lsl	x9, x9, #3
	ldr	w8, [x8, x9]
	asr	w3, w8, #8
	bl	_REG_SET_FIELD
	mov	x3, x0
Lloh15:
	adrp	x22, _GC@GOTPAGE
Lloh16:
	ldr	x22, [x22, _GC@GOTPAGEOFF]
	ldr	w0, [x22]
Lloh17:
	adrp	x8, _mmWD_BUF_RESOURCE_1@GOTPAGE
Lloh18:
	ldr	x8, [x8, _mmWD_BUF_RESOURCE_1@GOTPAGEOFF]
Lloh19:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
Lloh20:
	adrp	x24, _WD_BUF_RESOURCE_2@GOTPAGE
Lloh21:
	ldr	x24, [x24, _WD_BUF_RESOURCE_2@GOTPAGEOFF]
	ldr	w1, [x24]
Lloh22:
	adrp	x8, _CNTL_SB_BUF_SIZE@GOTPAGE
Lloh23:
	ldr	x8, [x8, _CNTL_SB_BUF_SIZE@GOTPAGEOFF]
Lloh24:
	ldr	w2, [x8]
Lloh25:
	adrp	x21, _NGG_CNTL@GOTPAGE
Lloh26:
	ldr	x21, [x21, _NGG_CNTL@GOTPAGEOFF]
	ldr	x8, [x20, #8]
	ldr	x9, [x21]
	lsl	x9, x9, #3
	ldr	w8, [x8, x9]
	asr	w3, w8, #8
	mov	w0, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x24]
Lloh27:
	adrp	x8, _PARAM_BUF_SIZE@GOTPAGE
Lloh28:
	ldr	x8, [x8, _PARAM_BUF_SIZE@GOTPAGEOFF]
Lloh29:
	ldr	w2, [x8]
Lloh30:
	adrp	x8, _NGG_PARAM@GOTPAGE
Lloh31:
	ldr	x8, [x8, _NGG_PARAM@GOTPAGEOFF]
	ldr	x9, [x20, #8]
Lloh32:
	ldr	x8, [x8]
	lsl	x8, x8, #3
	ldr	w8, [x9, x8]
	asr	w3, w8, #10
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x22]
Lloh33:
	adrp	x8, _mmWD_BUF_RESOURCE_2@GOTPAGE
Lloh34:
	ldr	x8, [x8, _mmWD_BUF_RESOURCE_2@GOTPAGEOFF]
Lloh35:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	x8, [x20, #8]
	ldr	x9, [x25]
	add	x8, x8, x9, lsl #3
	ldr	w0, [x8, #4]
	bl	_lower_32_bits
	mov	x3, x0
Lloh36:
	adrp	x8, _WD_INDEX_BUF_BASE@GOTPAGE
Lloh37:
	ldr	x8, [x8, _WD_INDEX_BUF_BASE@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
Lloh39:
	adrp	x24, _BASE@GOTPAGE
Lloh40:
	ldr	x24, [x24, _BASE@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	w0, #0
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x22]
Lloh41:
	adrp	x8, _mmWD_INDEX_BUF_BASE@GOTPAGE
Lloh42:
	ldr	x8, [x8, _mmWD_INDEX_BUF_BASE@GOTPAGEOFF]
Lloh43:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	x8, [x20, #8]
	ldr	x9, [x25]
	add	x8, x8, x9, lsl #3
	ldr	w0, [x8, #4]
	bl	_upper_32_bits
	mov	x3, x0
Lloh44:
	adrp	x8, _WD_INDEX_BUF_BASE_HI@GOTPAGE
Lloh45:
	ldr	x8, [x8, _WD_INDEX_BUF_BASE_HI@GOTPAGEOFF]
Lloh46:
	ldr	w1, [x8]
Lloh47:
	adrp	x25, _BASE_HI@GOTPAGE
Lloh48:
	ldr	x25, [x25, _BASE_HI@GOTPAGEOFF]
	ldr	w2, [x25]
	mov	w0, #0
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x22]
Lloh49:
	adrp	x8, _mmWD_INDEX_BUF_BASE_HI@GOTPAGE
Lloh50:
	ldr	x8, [x8, _mmWD_INDEX_BUF_BASE_HI@GOTPAGEOFF]
Lloh51:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	x8, [x20, #8]
	ldr	x9, [x23]
	add	x8, x8, x9, lsl #3
	ldr	w0, [x8, #4]
	bl	_lower_32_bits
	mov	x3, x0
Lloh52:
	adrp	x8, _WD_POS_BUF_BASE@GOTPAGE
Lloh53:
	ldr	x8, [x8, _WD_POS_BUF_BASE@GOTPAGEOFF]
Lloh54:
	ldr	w1, [x8]
	ldr	w2, [x24]
	mov	w0, #0
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x22]
Lloh55:
	adrp	x8, _mmWD_POS_BUF_BASE@GOTPAGE
Lloh56:
	ldr	x8, [x8, _mmWD_POS_BUF_BASE@GOTPAGEOFF]
Lloh57:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	x8, [x20, #8]
	ldr	x9, [x23]
	add	x8, x8, x9, lsl #3
	ldr	w0, [x8, #4]
	bl	_upper_32_bits
	mov	x3, x0
Lloh58:
	adrp	x8, _WD_POS_BUF_BASE_HI@GOTPAGE
Lloh59:
	ldr	x8, [x8, _WD_POS_BUF_BASE_HI@GOTPAGEOFF]
Lloh60:
	ldr	w1, [x8]
	ldr	w2, [x25]
	mov	w0, #0
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x22]
Lloh61:
	adrp	x8, _mmWD_POS_BUF_BASE_HI@GOTPAGE
Lloh62:
	ldr	x8, [x8, _mmWD_POS_BUF_BASE_HI@GOTPAGEOFF]
Lloh63:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	x8, [x20, #8]
	ldr	x9, [x21]
	add	x8, x8, x9, lsl #3
	ldr	w0, [x8, #4]
	bl	_lower_32_bits
	mov	x3, x0
Lloh64:
	adrp	x8, _WD_CNTL_SB_BUF_BASE@GOTPAGE
Lloh65:
	ldr	x8, [x8, _WD_CNTL_SB_BUF_BASE@GOTPAGEOFF]
Lloh66:
	ldr	w1, [x8]
	ldr	w2, [x24]
	mov	w0, #0
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x22]
Lloh67:
	adrp	x8, _mmWD_CNTL_SB_BUF_BASE@GOTPAGE
Lloh68:
	ldr	x8, [x8, _mmWD_CNTL_SB_BUF_BASE@GOTPAGEOFF]
Lloh69:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	x8, [x20, #8]
	ldr	x9, [x21]
	add	x8, x8, x9, lsl #3
	ldr	w0, [x8, #4]
	bl	_upper_32_bits
	mov	x3, x0
Lloh70:
	adrp	x8, _WD_CNTL_SB_BUF_BASE_HI@GOTPAGE
Lloh71:
	ldr	x8, [x8, _WD_CNTL_SB_BUF_BASE_HI@GOTPAGEOFF]
Lloh72:
	ldr	w1, [x8]
	ldr	w2, [x25]
	mov	w0, #0
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x22]
Lloh73:
	adrp	x8, _mmWD_CNTL_SB_BUF_BASE_HI@GOTPAGE
Lloh74:
	ldr	x8, [x8, _mmWD_CNTL_SB_BUF_BASE_HI@GOTPAGEOFF]
Lloh75:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
	mov	x0, x19
	mov	w1, #17
	bl	_amdgpu_ring_alloc
	cbz	w0, LBB0_3
; %bb.2:
	mov	x21, x0
	ldr	w1, [x19]
Lloh76:
	adrp	x0, l_.str@PAGE
Lloh77:
	add	x0, x0, l_.str@PAGEOFF
	mov	x2, x21
	bl	_DRM_ERROR
	b	LBB0_5
LBB0_3:
	ldr	w0, [x22]
Lloh78:
	adrp	x21, _mmGDS_VMID0_SIZE@GOTPAGE
Lloh79:
	ldr	x21, [x21, _mmGDS_VMID0_SIZE@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x3, x0
	ldr	x8, [x20, #24]
	ldrsw	x9, [x20]
	add	x4, x8, x9
	mov	x0, x19
	mov	w1, #0
	mov	w2, #0
	bl	_gfx_v9_0_write_data_to_reg
Lloh80:
	adrp	x8, _PACKET3_DMA_DATA@GOTPAGE
Lloh81:
	ldr	x8, [x8, _PACKET3_DMA_DATA@GOTPAGEOFF]
Lloh82:
	ldr	w0, [x8]
	mov	w1, #5
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh83:
	adrp	x8, _PACKET3_DMA_DATA_CP_SYNC@GOTPAGE
Lloh84:
	ldr	x8, [x8, _PACKET3_DMA_DATA_CP_SYNC@GOTPAGEOFF]
Lloh85:
	ldr	w23, [x8]
	mov	w0, #1
	bl	_PACKET3_DMA_DATA_DST_SEL
	orr	w23, w0, w23
	mov	w0, #2
	bl	_PACKET3_DMA_DATA_SRC_SEL
	orr	w1, w23, w0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_ring_write
	ldr	w1, [x20, #4]
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_ring_write
Lloh86:
	adrp	x8, _PACKET3_DMA_DATA_CMD_RAW_WAIT@GOTPAGE
Lloh87:
	ldr	x8, [x8, _PACKET3_DMA_DATA_CMD_RAW_WAIT@GOTPAGEOFF]
Lloh88:
	ldr	w8, [x8]
	ldr	w9, [x20]
	orr	w1, w9, w8
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x22]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x3, x0
	mov	x0, x19
	mov	w1, #0
	mov	w2, #0
	mov	x4, #0
	bl	_gfx_v9_0_write_data_to_reg
	mov	x0, x19
	bl	_amdgpu_ring_commit
LBB0_4:
	mov	w21, #0
LBB0_5:
	mov	x0, x21
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpAdd	Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGot	Lloh78, Lloh79
	.cfi_endproc
                                        ; -- End function
	.comm	_amdgpu_ngg,4,2                 ; @amdgpu_ngg
	.comm	_WD_BUF_RESOURCE_1,4,2          ; @WD_BUF_RESOURCE_1
	.comm	_INDEX_BUF_SIZE,4,2             ; @INDEX_BUF_SIZE
	.comm	_NGG_PRIM,8,3                   ; @NGG_PRIM
	.comm	_POS_BUF_SIZE,4,2               ; @POS_BUF_SIZE
	.comm	_NGG_POS,8,3                    ; @NGG_POS
	.comm	_GC,4,2                         ; @GC
	.comm	_mmWD_BUF_RESOURCE_1,4,2        ; @mmWD_BUF_RESOURCE_1
	.comm	_WD_BUF_RESOURCE_2,4,2          ; @WD_BUF_RESOURCE_2
	.comm	_CNTL_SB_BUF_SIZE,4,2           ; @CNTL_SB_BUF_SIZE
	.comm	_NGG_CNTL,8,3                   ; @NGG_CNTL
	.comm	_PARAM_BUF_SIZE,4,2             ; @PARAM_BUF_SIZE
	.comm	_NGG_PARAM,8,3                  ; @NGG_PARAM
	.comm	_mmWD_BUF_RESOURCE_2,4,2        ; @mmWD_BUF_RESOURCE_2
	.comm	_WD_INDEX_BUF_BASE,4,2          ; @WD_INDEX_BUF_BASE
	.comm	_BASE,4,2                       ; @BASE
	.comm	_mmWD_INDEX_BUF_BASE,4,2        ; @mmWD_INDEX_BUF_BASE
	.comm	_WD_INDEX_BUF_BASE_HI,4,2       ; @WD_INDEX_BUF_BASE_HI
	.comm	_BASE_HI,4,2                    ; @BASE_HI
	.comm	_mmWD_INDEX_BUF_BASE_HI,4,2     ; @mmWD_INDEX_BUF_BASE_HI
	.comm	_WD_POS_BUF_BASE,4,2            ; @WD_POS_BUF_BASE
	.comm	_mmWD_POS_BUF_BASE,4,2          ; @mmWD_POS_BUF_BASE
	.comm	_WD_POS_BUF_BASE_HI,4,2         ; @WD_POS_BUF_BASE_HI
	.comm	_mmWD_POS_BUF_BASE_HI,4,2       ; @mmWD_POS_BUF_BASE_HI
	.comm	_WD_CNTL_SB_BUF_BASE,4,2        ; @WD_CNTL_SB_BUF_BASE
	.comm	_mmWD_CNTL_SB_BUF_BASE,4,2      ; @mmWD_CNTL_SB_BUF_BASE
	.comm	_WD_CNTL_SB_BUF_BASE_HI,4,2     ; @WD_CNTL_SB_BUF_BASE_HI
	.comm	_mmWD_CNTL_SB_BUF_BASE_HI,4,2   ; @mmWD_CNTL_SB_BUF_BASE_HI
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"amdgpu: NGG failed to lock ring %s (%d).\n"

	.comm	_mmGDS_VMID0_SIZE,4,2           ; @mmGDS_VMID0_SIZE
	.comm	_PACKET3_DMA_DATA,4,2           ; @PACKET3_DMA_DATA
	.comm	_PACKET3_DMA_DATA_CP_SYNC,4,2   ; @PACKET3_DMA_DATA_CP_SYNC
	.comm	_PACKET3_DMA_DATA_CMD_RAW_WAIT,4,2 ; @PACKET3_DMA_DATA_CMD_RAW_WAIT
	.no_dead_strip	_gfx_v9_0_ngg_en
.subsections_via_symbols
