	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function si_cp_resume
_si_cp_resume:                          ## @si_cp_resume
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	xorl	%esi, %esi
	callq	_si_enable_gui_idle_interrupt
	movq	_CP_SEM_WAIT_TIMER@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CP_SEM_INCOMPLETE_TIMER_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CP_RB_WPTR_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CP_DEBUG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_SCRATCH_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_WB_SCRATCH_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	24(%r14), %esi
	sarl	$8, %esi
	callq	_WREG32
	movq	16(%r14), %r13
	movq	_RADEON_RING_TYPE_GFX_INDEX@GOTPCREL(%rip), %rax
	movq	(%rax), %r12
	shlq	$4, %r12
	movl	(%r13,%r12), %eax
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	callq	_order_base_2
	movl	%eax, %r15d
	movq	_RADEON_GPU_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	callq	_order_base_2
	movl	%eax, %ebx
	shll	$8, %ebx
	orl	%r15d, %ebx
	movq	_CP_RB0_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r15), %edi
	movq	_RB_RPTR_WR_ENA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	%ebx, %esi
	callq	_WREG32
	movq	%r13, -48(%rbp)                 ## 8-byte Spill
	movl	$0, 4(%r13,%r12)
	movq	_CP_RB0_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CP_RB0_RPTR_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_WB_CP_RPTR_OFFSET@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	addl	24(%r14), %esi
	andl	$-4, %esi
	callq	_WREG32
	movq	_CP_RB0_RPTR_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	(%r13), %edi
	addl	24(%r14), %edi
	callq	_upper_32_bits
	movzbl	%al, %esi
	movl	%r15d, %edi
	callq	_WREG32
	xorl	%eax, %eax
	cmpq	$0, 32(%r14)
	movl	$255, %esi
	jne	LBB0_2
## %bb.1:
	movq	_RB_NO_UPDATE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	xorl	%esi, %esi
LBB0_2:
	orl	%eax, %ebx
	movq	_SCRATCH_UMSK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32
	movl	$1, %edi
	callq	_mdelay
	movq	_CP_RB0_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_CP_RB0_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movl	8(%rax,%r12), %esi
	sarl	$8, %esi
	callq	_WREG32
	movq	16(%r14), %rcx
	movq	_CAYMAN_RING_TYPE_CP1_INDEX@GOTPCREL(%rip), %rax
	movq	(%rax), %r13
	shlq	$4, %r13
	movl	(%rcx,%r13), %eax
	movq	%rcx, %r15
	movq	%rcx, -56(%rbp)                 ## 8-byte Spill
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	callq	_order_base_2
	movq	%r14, -48(%rbp)                 ## 8-byte Spill
	movl	%eax, %r14d
	movq	_RADEON_GPU_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	callq	_order_base_2
	shll	$8, %eax
	orl	%eax, %r14d
	movq	_CP_RB1_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movl	(%rbx), %edi
	movq	_RB_RPTR_WR_ENA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	%r14d, %esi
	callq	_WREG32
	movl	$0, 4(%r15,%r13)
	movq	_CP_RB1_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CP_RB1_RPTR_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_WB_CP1_RPTR_OFFSET@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	addl	24(%rax), %esi
	andl	$-4, %esi
	callq	_WREG32
	movq	_CP_RB1_RPTR_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	(%r12), %edi
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	addl	24(%rax), %edi
	callq	_upper_32_bits
	movzbl	%al, %esi
	movl	%r15d, %edi
	callq	_WREG32
	movl	$1, %edi
	callq	_mdelay
	movl	(%rbx), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_CP_RB1_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	8(%rax,%r13), %esi
	sarl	$8, %esi
	callq	_WREG32
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movq	16(%rax), %rcx
	movq	_CAYMAN_RING_TYPE_CP2_INDEX@GOTPCREL(%rip), %rax
	movq	(%rax), %r12
	shlq	$4, %r12
	movl	(%rcx,%r12), %eax
	movq	%rcx, %r15
	movq	%rcx, -56(%rbp)                 ## 8-byte Spill
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	callq	_order_base_2
	movl	%eax, %r14d
	movq	_RADEON_GPU_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	callq	_order_base_2
	shll	$8, %eax
	orl	%eax, %r14d
	movq	_CP_RB2_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movl	(%rbx), %edi
	movq	_RB_RPTR_WR_ENA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	%r14d, %esi
	callq	_WREG32
	movl	$0, 4(%r15,%r12)
	movq	_CP_RB2_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CP_RB2_RPTR_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_WB_CP2_RPTR_OFFSET@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	addl	24(%rbx), %esi
	andl	$-4, %esi
	callq	_WREG32
	movq	_CP_RB2_RPTR_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	(%r13), %edi
	movq	_CAYMAN_RING_TYPE_CP2_INDEX@GOTPCREL(%rip), %r13
	addl	24(%rbx), %edi
	callq	_upper_32_bits
	movzbl	%al, %esi
	movl	%r15d, %edi
	callq	_WREG32
	movl	$1, %edi
	callq	_mdelay
	movq	_CP_RB2_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_CP_RB2_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	8(%rax,%r12), %esi
	movq	_CAYMAN_RING_TYPE_CP1_INDEX@GOTPCREL(%rip), %r12
	sarl	$8, %esi
	callq	_WREG32
	movq	%rbx, %rdi
	callq	_si_cp_start
	movq	16(%rbx), %rax
	movq	_RADEON_RING_TYPE_GFX_INDEX@GOTPCREL(%rip), %r15
	movq	(%r15), %rsi
	movq	%rsi, %rcx
	shlq	$4, %rcx
	leaq	(%rax,%rcx), %rdx
	movl	$1, 12(%rax,%rcx)
	movq	(%r12), %rcx
	shlq	$4, %rcx
	movl	$1, 12(%rax,%rcx)
	movq	(%r13), %rcx
	shlq	$4, %rcx
	movl	$1, 12(%rax,%rcx)
	movq	%rbx, %rdi
	callq	_radeon_ring_test
	movl	%eax, %r14d
	testl	%eax, %eax
	je	LBB0_4
## %bb.3:
	movq	16(%rbx), %rax
	movq	(%r15), %rcx
	shlq	$4, %rcx
	movl	$0, 12(%rax,%rcx)
	movq	(%r12), %rcx
	shlq	$4, %rcx
	movl	$0, 12(%rax,%rcx)
	movq	(%r13), %rcx
	shlq	$4, %rcx
	movl	$0, 12(%rax,%rcx)
	jmp	LBB0_10
LBB0_4:
	movq	(%r12), %rsi
	movq	%rsi, %rdx
	shlq	$4, %rdx
	addq	16(%rbx), %rdx
	movq	%rbx, %rdi
	callq	_radeon_ring_test
	movq	16(%rbx), %rdx
	testl	%eax, %eax
	je	LBB0_6
## %bb.5:
	movq	(%r12), %rax
	shlq	$4, %rax
	movl	$0, 12(%rdx,%rax)
LBB0_6:
	movq	(%r13), %rsi
	movq	%rsi, %rax
	shlq	$4, %rax
	addq	%rax, %rdx
	movq	%rbx, %rdi
	callq	_radeon_ring_test
	testl	%eax, %eax
	je	LBB0_8
## %bb.7:
	movq	16(%rbx), %rax
	movq	(%r13), %rcx
	shlq	$4, %rcx
	movl	$0, 12(%rax,%rcx)
LBB0_8:
	movq	%rbx, %rdi
	movl	$1, %esi
	callq	_si_enable_gui_idle_interrupt
	movq	8(%rbx), %rax
	movq	(%rax), %rax
	cmpq	(%r15), %rax
	jne	LBB0_10
## %bb.9:
	movl	(%rbx), %esi
	movq	%rbx, %rdi
	callq	_radeon_ttm_set_active_vram_size
LBB0_10:
	movl	%r14d, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CP_SEM_WAIT_TIMER,4,2          ## @CP_SEM_WAIT_TIMER
	.comm	_CP_SEM_INCOMPLETE_TIMER_CNTL,4,2 ## @CP_SEM_INCOMPLETE_TIMER_CNTL
	.comm	_CP_RB_WPTR_DELAY,4,2           ## @CP_RB_WPTR_DELAY
	.comm	_CP_DEBUG,4,2                   ## @CP_DEBUG
	.comm	_SCRATCH_ADDR,4,2               ## @SCRATCH_ADDR
	.comm	_RADEON_WB_SCRATCH_OFFSET,4,2   ## @RADEON_WB_SCRATCH_OFFSET
	.comm	_RADEON_RING_TYPE_GFX_INDEX,8,3 ## @RADEON_RING_TYPE_GFX_INDEX
	.comm	_RADEON_GPU_PAGE_SIZE,4,2       ## @RADEON_GPU_PAGE_SIZE
	.comm	_CP_RB0_CNTL,4,2                ## @CP_RB0_CNTL
	.comm	_RB_RPTR_WR_ENA,4,2             ## @RB_RPTR_WR_ENA
	.comm	_CP_RB0_WPTR,4,2                ## @CP_RB0_WPTR
	.comm	_CP_RB0_RPTR_ADDR,4,2           ## @CP_RB0_RPTR_ADDR
	.comm	_RADEON_WB_CP_RPTR_OFFSET,4,2   ## @RADEON_WB_CP_RPTR_OFFSET
	.comm	_CP_RB0_RPTR_ADDR_HI,4,2        ## @CP_RB0_RPTR_ADDR_HI
	.comm	_SCRATCH_UMSK,4,2               ## @SCRATCH_UMSK
	.comm	_RB_NO_UPDATE,4,2               ## @RB_NO_UPDATE
	.comm	_CP_RB0_BASE,4,2                ## @CP_RB0_BASE
	.comm	_CAYMAN_RING_TYPE_CP1_INDEX,8,3 ## @CAYMAN_RING_TYPE_CP1_INDEX
	.comm	_CP_RB1_CNTL,4,2                ## @CP_RB1_CNTL
	.comm	_CP_RB1_WPTR,4,2                ## @CP_RB1_WPTR
	.comm	_CP_RB1_RPTR_ADDR,4,2           ## @CP_RB1_RPTR_ADDR
	.comm	_RADEON_WB_CP1_RPTR_OFFSET,4,2  ## @RADEON_WB_CP1_RPTR_OFFSET
	.comm	_CP_RB1_RPTR_ADDR_HI,4,2        ## @CP_RB1_RPTR_ADDR_HI
	.comm	_CP_RB1_BASE,4,2                ## @CP_RB1_BASE
	.comm	_CAYMAN_RING_TYPE_CP2_INDEX,8,3 ## @CAYMAN_RING_TYPE_CP2_INDEX
	.comm	_CP_RB2_CNTL,4,2                ## @CP_RB2_CNTL
	.comm	_CP_RB2_WPTR,4,2                ## @CP_RB2_WPTR
	.comm	_CP_RB2_RPTR_ADDR,4,2           ## @CP_RB2_RPTR_ADDR
	.comm	_RADEON_WB_CP2_RPTR_OFFSET,4,2  ## @RADEON_WB_CP2_RPTR_OFFSET
	.comm	_CP_RB2_RPTR_ADDR_HI,4,2        ## @CP_RB2_RPTR_ADDR_HI
	.comm	_CP_RB2_BASE,4,2                ## @CP_RB2_BASE
	.comm	_BUF_SWAP_32BIT,4,2             ## @BUF_SWAP_32BIT
	.no_dead_strip	_si_cp_resume
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function si_cp_resume
_si_cp_resume:                          ; @si_cp_resume
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	mov	w1, #0
	bl	_si_enable_gui_idle_interrupt
Lloh0:
	adrp	x8, _CP_SEM_WAIT_TIMER@GOTPAGE
Lloh1:
	ldr	x8, [x8, _CP_SEM_WAIT_TIMER@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh3:
	adrp	x8, _CP_SEM_INCOMPLETE_TIMER_CNTL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _CP_SEM_INCOMPLETE_TIMER_CNTL@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh6:
	adrp	x8, _CP_RB_WPTR_DELAY@GOTPAGE
Lloh7:
	ldr	x8, [x8, _CP_RB_WPTR_DELAY@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh9:
	adrp	x8, _CP_DEBUG@GOTPAGE
Lloh10:
	ldr	x8, [x8, _CP_DEBUG@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh12:
	adrp	x8, _SCRATCH_ADDR@GOTPAGE
Lloh13:
	ldr	x8, [x8, _SCRATCH_ADDR@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	ldr	w8, [x19, #24]
Lloh15:
	adrp	x9, _RADEON_WB_SCRATCH_OFFSET@GOTPAGE
Lloh16:
	ldr	x9, [x9, _RADEON_WB_SCRATCH_OFFSET@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	add	w8, w9, w8
	asr	w1, w8, #8
	bl	_WREG32
	ldr	x8, [x19, #16]
Lloh18:
	adrp	x9, _RADEON_RING_TYPE_GFX_INDEX@GOTPAGE
Lloh19:
	ldr	x9, [x9, _RADEON_RING_TYPE_GFX_INDEX@GOTPAGEOFF]
Lloh20:
	ldr	x9, [x9]
	add	x23, x8, x9, lsl #4
	ldr	w8, [x23]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #3
	bl	_order_base_2
	mov	x20, x0
Lloh21:
	adrp	x25, _RADEON_GPU_PAGE_SIZE@GOTPAGE
Lloh22:
	ldr	x25, [x25, _RADEON_GPU_PAGE_SIZE@GOTPAGEOFF]
	ldr	w8, [x25]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #3
	bl	_order_base_2
	orr	w20, w20, w0, lsl #8
Lloh23:
	adrp	x27, _CP_RB0_CNTL@GOTPAGE
Lloh24:
	ldr	x27, [x27, _CP_RB0_CNTL@GOTPAGEOFF]
	ldr	w0, [x27]
	mov	x1, x20
	bl	_WREG32
	ldr	w0, [x27]
Lloh25:
	adrp	x26, _RB_RPTR_WR_ENA@GOTPAGE
Lloh26:
	ldr	x26, [x26, _RB_RPTR_WR_ENA@GOTPAGEOFF]
	ldr	w8, [x26]
	orr	w1, w8, w20
	bl	_WREG32
	str	wzr, [x23, #4]
Lloh27:
	adrp	x8, _CP_RB0_WPTR@GOTPAGE
Lloh28:
	ldr	x8, [x8, _CP_RB0_WPTR@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh30:
	adrp	x8, _CP_RB0_RPTR_ADDR@GOTPAGE
Lloh31:
	ldr	x8, [x8, _CP_RB0_RPTR_ADDR@GOTPAGEOFF]
Lloh32:
	ldr	w0, [x8]
	ldr	w8, [x19, #24]
Lloh33:
	adrp	x24, _RADEON_WB_CP_RPTR_OFFSET@GOTPAGE
Lloh34:
	ldr	x24, [x24, _RADEON_WB_CP_RPTR_OFFSET@GOTPAGEOFF]
	ldr	w9, [x24]
	add	w8, w9, w8
	and	w1, w8, #0xfffffffc
	bl	_WREG32
Lloh35:
	adrp	x8, _CP_RB0_RPTR_ADDR_HI@GOTPAGE
Lloh36:
	ldr	x8, [x8, _CP_RB0_RPTR_ADDR_HI@GOTPAGEOFF]
Lloh37:
	ldr	w21, [x8]
	ldr	w8, [x19, #24]
	ldr	w9, [x24]
	add	w0, w9, w8
	bl	_upper_32_bits
	and	w1, w0, #0xff
	mov	x0, x21
	bl	_WREG32
	ldr	x8, [x19, #32]
Lloh38:
	adrp	x9, _RB_NO_UPDATE@GOTPAGE
Lloh39:
	ldr	x9, [x9, _RB_NO_UPDATE@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
	cmp	x8, #0
	mov	w8, #255
	csel	w1, wzr, w8, eq
	csel	w8, w9, wzr, eq
	orr	w20, w20, w8
Lloh41:
	adrp	x8, _SCRATCH_UMSK@GOTPAGE
Lloh42:
	ldr	x8, [x8, _SCRATCH_UMSK@GOTPAGEOFF]
Lloh43:
	ldr	w0, [x8]
	bl	_WREG32
	mov	w24, #1
	mov	w0, #1
	bl	_mdelay
	ldr	w0, [x27]
	mov	x1, x20
	bl	_WREG32
Lloh44:
	adrp	x8, _CP_RB0_BASE@GOTPAGE
Lloh45:
	ldr	x8, [x8, _CP_RB0_BASE@GOTPAGEOFF]
Lloh46:
	ldr	w0, [x8]
	ldr	w8, [x23, #8]
	asr	w1, w8, #8
	bl	_WREG32
	ldr	x8, [x19, #16]
Lloh47:
	adrp	x23, _CAYMAN_RING_TYPE_CP1_INDEX@GOTPAGE
Lloh48:
	ldr	x23, [x23, _CAYMAN_RING_TYPE_CP1_INDEX@GOTPAGEOFF]
	ldr	x9, [x23]
	add	x27, x8, x9, lsl #4
	ldr	w8, [x27]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #3
	bl	_order_base_2
	mov	x20, x0
	ldr	w8, [x25]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #3
	bl	_order_base_2
	orr	w20, w20, w0, lsl #8
Lloh49:
	adrp	x28, _CP_RB1_CNTL@GOTPAGE
Lloh50:
	ldr	x28, [x28, _CP_RB1_CNTL@GOTPAGEOFF]
	ldr	w0, [x28]
	mov	x1, x20
	bl	_WREG32
	ldr	w0, [x28]
	ldr	w8, [x26]
	orr	w1, w8, w20
	bl	_WREG32
	str	wzr, [x27, #4]
Lloh51:
	adrp	x8, _CP_RB1_WPTR@GOTPAGE
Lloh52:
	ldr	x8, [x8, _CP_RB1_WPTR@GOTPAGEOFF]
Lloh53:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh54:
	adrp	x8, _CP_RB1_RPTR_ADDR@GOTPAGE
Lloh55:
	ldr	x8, [x8, _CP_RB1_RPTR_ADDR@GOTPAGEOFF]
Lloh56:
	ldr	w0, [x8]
	ldr	w8, [x19, #24]
Lloh57:
	adrp	x22, _RADEON_WB_CP1_RPTR_OFFSET@GOTPAGE
Lloh58:
	ldr	x22, [x22, _RADEON_WB_CP1_RPTR_OFFSET@GOTPAGEOFF]
	ldr	w9, [x22]
	add	w8, w9, w8
	and	w1, w8, #0xfffffffc
	bl	_WREG32
Lloh59:
	adrp	x8, _CP_RB1_RPTR_ADDR_HI@GOTPAGE
Lloh60:
	ldr	x8, [x8, _CP_RB1_RPTR_ADDR_HI@GOTPAGEOFF]
Lloh61:
	ldr	w21, [x8]
	ldr	w8, [x19, #24]
	ldr	w9, [x22]
	add	w0, w9, w8
	bl	_upper_32_bits
	and	w1, w0, #0xff
	mov	x0, x21
	bl	_WREG32
	mov	w0, #1
	bl	_mdelay
	ldr	w0, [x28]
	mov	x1, x20
	bl	_WREG32
Lloh62:
	adrp	x8, _CP_RB1_BASE@GOTPAGE
Lloh63:
	ldr	x8, [x8, _CP_RB1_BASE@GOTPAGEOFF]
Lloh64:
	ldr	w0, [x8]
	ldr	w8, [x27, #8]
	asr	w1, w8, #8
	bl	_WREG32
	ldr	x8, [x19, #16]
Lloh65:
	adrp	x27, _CAYMAN_RING_TYPE_CP2_INDEX@GOTPAGE
Lloh66:
	ldr	x27, [x27, _CAYMAN_RING_TYPE_CP2_INDEX@GOTPAGEOFF]
	ldr	x9, [x27]
	add	x28, x8, x9, lsl #4
	ldr	w8, [x28]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #3
	bl	_order_base_2
	mov	x20, x0
	ldr	w8, [x25]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #3
	bl	_order_base_2
	orr	w20, w20, w0, lsl #8
Lloh67:
	adrp	x22, _CP_RB2_CNTL@GOTPAGE
Lloh68:
	ldr	x22, [x22, _CP_RB2_CNTL@GOTPAGEOFF]
	ldr	w0, [x22]
	mov	x1, x20
	bl	_WREG32
	ldr	w0, [x22]
	ldr	w8, [x26]
	orr	w1, w8, w20
	bl	_WREG32
	str	wzr, [x28, #4]
Lloh69:
	adrp	x8, _CP_RB2_WPTR@GOTPAGE
Lloh70:
	ldr	x8, [x8, _CP_RB2_WPTR@GOTPAGEOFF]
Lloh71:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh72:
	adrp	x8, _CP_RB2_RPTR_ADDR@GOTPAGE
Lloh73:
	ldr	x8, [x8, _CP_RB2_RPTR_ADDR@GOTPAGEOFF]
Lloh74:
	ldr	w0, [x8]
	ldr	w8, [x19, #24]
Lloh75:
	adrp	x25, _RADEON_WB_CP2_RPTR_OFFSET@GOTPAGE
Lloh76:
	ldr	x25, [x25, _RADEON_WB_CP2_RPTR_OFFSET@GOTPAGEOFF]
	ldr	w9, [x25]
	add	w8, w9, w8
	and	w1, w8, #0xfffffffc
	bl	_WREG32
Lloh77:
	adrp	x8, _CP_RB2_RPTR_ADDR_HI@GOTPAGE
Lloh78:
	ldr	x8, [x8, _CP_RB2_RPTR_ADDR_HI@GOTPAGEOFF]
Lloh79:
	ldr	w21, [x8]
	ldr	w8, [x19, #24]
	ldr	w9, [x25]
	add	w0, w9, w8
	bl	_upper_32_bits
	and	w1, w0, #0xff
	mov	x0, x21
Lloh80:
	adrp	x21, _RADEON_RING_TYPE_GFX_INDEX@GOTPAGE
Lloh81:
	ldr	x21, [x21, _RADEON_RING_TYPE_GFX_INDEX@GOTPAGEOFF]
	bl	_WREG32
	mov	w0, #1
	bl	_mdelay
	ldr	w0, [x22]
	mov	x1, x20
	bl	_WREG32
Lloh82:
	adrp	x8, _CP_RB2_BASE@GOTPAGE
Lloh83:
	ldr	x8, [x8, _CP_RB2_BASE@GOTPAGEOFF]
Lloh84:
	ldr	w0, [x8]
	ldr	w8, [x28, #8]
	asr	w1, w8, #8
	bl	_WREG32
	mov	x0, x19
	bl	_si_cp_start
	ldr	x8, [x19, #16]
	ldr	x1, [x21]
	add	x2, x8, x1, lsl #4
	str	w24, [x2, #12]
	ldr	x9, [x23]
	add	x9, x8, x9, lsl #4
	str	w24, [x9, #12]
	ldr	x9, [x27]
	add	x8, x8, x9, lsl #4
	str	w24, [x8, #12]
	mov	x0, x19
	bl	_radeon_ring_test
	mov	x20, x0
	cbz	w0, LBB0_2
; %bb.1:
	ldr	x8, [x19, #16]
	ldr	x9, [x21]
	add	x9, x8, x9, lsl #4
	str	wzr, [x9, #12]
	ldr	x9, [x23]
	add	x9, x8, x9, lsl #4
	str	wzr, [x9, #12]
	ldr	x9, [x27]
	add	x8, x8, x9, lsl #4
	str	wzr, [x8, #12]
	b	LBB0_8
LBB0_2:
	ldr	x1, [x23]
	ldr	x8, [x19, #16]
	add	x2, x8, x1, lsl #4
	mov	x0, x19
	bl	_radeon_ring_test
	ldr	x8, [x19, #16]
	cbz	w0, LBB0_4
; %bb.3:
	ldr	x9, [x23]
	add	x9, x8, x9, lsl #4
	str	wzr, [x9, #12]
LBB0_4:
	ldr	x1, [x27]
	add	x2, x8, x1, lsl #4
	mov	x0, x19
	bl	_radeon_ring_test
	cbz	w0, LBB0_6
; %bb.5:
	ldr	x8, [x19, #16]
	ldr	x9, [x27]
	add	x8, x8, x9, lsl #4
	str	wzr, [x8, #12]
LBB0_6:
	mov	x0, x19
	mov	w1, #1
	bl	_si_enable_gui_idle_interrupt
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	ldr	x9, [x21]
	cmp	x8, x9
	b.ne	LBB0_8
; %bb.7:
	ldr	w1, [x19]
	mov	x0, x19
	bl	_radeon_ttm_set_active_vram_size
LBB0_8:
	mov	x0, x20
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGot	Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGot	Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGot	Lloh67, Lloh68
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_CP_SEM_WAIT_TIMER,4,2          ; @CP_SEM_WAIT_TIMER
	.comm	_CP_SEM_INCOMPLETE_TIMER_CNTL,4,2 ; @CP_SEM_INCOMPLETE_TIMER_CNTL
	.comm	_CP_RB_WPTR_DELAY,4,2           ; @CP_RB_WPTR_DELAY
	.comm	_CP_DEBUG,4,2                   ; @CP_DEBUG
	.comm	_SCRATCH_ADDR,4,2               ; @SCRATCH_ADDR
	.comm	_RADEON_WB_SCRATCH_OFFSET,4,2   ; @RADEON_WB_SCRATCH_OFFSET
	.comm	_RADEON_RING_TYPE_GFX_INDEX,8,3 ; @RADEON_RING_TYPE_GFX_INDEX
	.comm	_RADEON_GPU_PAGE_SIZE,4,2       ; @RADEON_GPU_PAGE_SIZE
	.comm	_CP_RB0_CNTL,4,2                ; @CP_RB0_CNTL
	.comm	_RB_RPTR_WR_ENA,4,2             ; @RB_RPTR_WR_ENA
	.comm	_CP_RB0_WPTR,4,2                ; @CP_RB0_WPTR
	.comm	_CP_RB0_RPTR_ADDR,4,2           ; @CP_RB0_RPTR_ADDR
	.comm	_RADEON_WB_CP_RPTR_OFFSET,4,2   ; @RADEON_WB_CP_RPTR_OFFSET
	.comm	_CP_RB0_RPTR_ADDR_HI,4,2        ; @CP_RB0_RPTR_ADDR_HI
	.comm	_SCRATCH_UMSK,4,2               ; @SCRATCH_UMSK
	.comm	_RB_NO_UPDATE,4,2               ; @RB_NO_UPDATE
	.comm	_CP_RB0_BASE,4,2                ; @CP_RB0_BASE
	.comm	_CAYMAN_RING_TYPE_CP1_INDEX,8,3 ; @CAYMAN_RING_TYPE_CP1_INDEX
	.comm	_CP_RB1_CNTL,4,2                ; @CP_RB1_CNTL
	.comm	_CP_RB1_WPTR,4,2                ; @CP_RB1_WPTR
	.comm	_CP_RB1_RPTR_ADDR,4,2           ; @CP_RB1_RPTR_ADDR
	.comm	_RADEON_WB_CP1_RPTR_OFFSET,4,2  ; @RADEON_WB_CP1_RPTR_OFFSET
	.comm	_CP_RB1_RPTR_ADDR_HI,4,2        ; @CP_RB1_RPTR_ADDR_HI
	.comm	_CP_RB1_BASE,4,2                ; @CP_RB1_BASE
	.comm	_CAYMAN_RING_TYPE_CP2_INDEX,8,3 ; @CAYMAN_RING_TYPE_CP2_INDEX
	.comm	_CP_RB2_CNTL,4,2                ; @CP_RB2_CNTL
	.comm	_CP_RB2_WPTR,4,2                ; @CP_RB2_WPTR
	.comm	_CP_RB2_RPTR_ADDR,4,2           ; @CP_RB2_RPTR_ADDR
	.comm	_RADEON_WB_CP2_RPTR_OFFSET,4,2  ; @RADEON_WB_CP2_RPTR_OFFSET
	.comm	_CP_RB2_RPTR_ADDR_HI,4,2        ; @CP_RB2_RPTR_ADDR_HI
	.comm	_CP_RB2_BASE,4,2                ; @CP_RB2_BASE
	.comm	_BUF_SWAP_32BIT,4,2             ; @BUF_SWAP_32BIT
	.no_dead_strip	_si_cp_resume
.subsections_via_symbols
