	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function zynq_fpga_ops_write_complete
_zynq_fpga_ops_write_complete:          ## @zynq_fpga_ops_write_complete
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	(%rdi), %r15
	movl	4(%r15), %edi
	callq	_clk_enable
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_5
## %bb.1:
	movq	_CTRL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_zynq_fpga_read
	movq	_CTRL_PCAP_PR_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_zynq_fpga_write
	movq	_INT_STS_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_INIT_POLL_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	movq	_INIT_POLL_TIMEOUT@GOTPCREL(%rip), %rax
	movl	(%rax), %r9d
	movq	%r15, %rdi
	xorl	%ecx, %ecx
	callq	_zynq_fpga_poll_timeout
	movl	%eax, %ebx
	movl	4(%r15), %edi
	callq	_clk_disable
	testl	%ebx, %ebx
	jne	LBB0_5
## %bb.2:
	movq	_FPGA_MGR_PARTIAL_RECONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r14)
	jne	LBB0_4
## %bb.3:
	movl	(%r15), %edi
	movq	_SLCR_LVL_SHFTR_EN_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_LVL_SHFTR_ENABLE_PL_TO_PS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_regmap_write
	movl	(%r15), %edi
	movq	_SLCR_FPGA_RST_CTRL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_FPGA_RST_NONE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_regmap_write
LBB0_4:
	xorl	%ebx, %ebx
LBB0_5:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CTRL_OFFSET,4,2                ## @CTRL_OFFSET
	.comm	_CTRL_PCAP_PR_MASK,4,2          ## @CTRL_PCAP_PR_MASK
	.comm	_INT_STS_OFFSET,4,2             ## @INT_STS_OFFSET
	.comm	_IXR_PCFG_DONE_MASK,4,2         ## @IXR_PCFG_DONE_MASK
	.comm	_INIT_POLL_DELAY,4,2            ## @INIT_POLL_DELAY
	.comm	_INIT_POLL_TIMEOUT,4,2          ## @INIT_POLL_TIMEOUT
	.comm	_FPGA_MGR_PARTIAL_RECONFIG,4,2  ## @FPGA_MGR_PARTIAL_RECONFIG
	.comm	_SLCR_LVL_SHFTR_EN_OFFSET,4,2   ## @SLCR_LVL_SHFTR_EN_OFFSET
	.comm	_LVL_SHFTR_ENABLE_PL_TO_PS,4,2  ## @LVL_SHFTR_ENABLE_PL_TO_PS
	.comm	_SLCR_FPGA_RST_CTRL_OFFSET,4,2  ## @SLCR_FPGA_RST_CTRL_OFFSET
	.comm	_FPGA_RST_NONE_MASK,4,2         ## @FPGA_RST_NONE_MASK
	.no_dead_strip	_zynq_fpga_ops_write_complete
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function zynq_fpga_ops_write_complete
_zynq_fpga_ops_write_complete:          ; @zynq_fpga_ops_write_complete
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	ldr	x19, [x0]
	ldr	w0, [x19, #4]
	bl	_clk_enable
	mov	x21, x0
	cbnz	w0, LBB0_5
; %bb.1:
Lloh0:
	adrp	x8, _CTRL_OFFSET@GOTPAGE
Lloh1:
	ldr	x8, [x8, _CTRL_OFFSET@GOTPAGEOFF]
Lloh2:
	ldr	w21, [x8]
	mov	x0, x19
	mov	x1, x21
	bl	_zynq_fpga_read
Lloh3:
	adrp	x8, _CTRL_PCAP_PR_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _CTRL_PCAP_PR_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	bic	w2, w0, w8
	mov	x0, x19
	mov	x1, x21
	bl	_zynq_fpga_write
Lloh6:
	adrp	x8, _INT_STS_OFFSET@GOTPAGE
Lloh7:
	ldr	x8, [x8, _INT_STS_OFFSET@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
Lloh9:
	adrp	x8, _INIT_POLL_DELAY@GOTPAGE
Lloh10:
	ldr	x8, [x8, _INIT_POLL_DELAY@GOTPAGEOFF]
Lloh11:
	ldr	w4, [x8]
Lloh12:
	adrp	x8, _INIT_POLL_TIMEOUT@GOTPAGE
Lloh13:
	ldr	x8, [x8, _INIT_POLL_TIMEOUT@GOTPAGEOFF]
Lloh14:
	ldr	w5, [x8]
	mov	x0, x19
	mov	w3, #0
	bl	_zynq_fpga_poll_timeout
	mov	x21, x0
	ldr	w0, [x19, #4]
	bl	_clk_disable
	cbnz	w21, LBB0_5
; %bb.2:
	ldr	w8, [x20]
Lloh15:
	adrp	x9, _FPGA_MGR_PARTIAL_RECONFIG@GOTPAGE
Lloh16:
	ldr	x9, [x9, _FPGA_MGR_PARTIAL_RECONFIG@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_4
; %bb.3:
	ldr	w0, [x19]
Lloh18:
	adrp	x8, _SLCR_LVL_SHFTR_EN_OFFSET@GOTPAGE
Lloh19:
	ldr	x8, [x8, _SLCR_LVL_SHFTR_EN_OFFSET@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
Lloh21:
	adrp	x8, _LVL_SHFTR_ENABLE_PL_TO_PS@GOTPAGE
Lloh22:
	ldr	x8, [x8, _LVL_SHFTR_ENABLE_PL_TO_PS@GOTPAGEOFF]
Lloh23:
	ldr	w2, [x8]
	bl	_regmap_write
	ldr	w0, [x19]
Lloh24:
	adrp	x8, _SLCR_FPGA_RST_CTRL_OFFSET@GOTPAGE
Lloh25:
	ldr	x8, [x8, _SLCR_FPGA_RST_CTRL_OFFSET@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
Lloh27:
	adrp	x8, _FPGA_RST_NONE_MASK@GOTPAGE
Lloh28:
	ldr	x8, [x8, _FPGA_RST_NONE_MASK@GOTPAGEOFF]
Lloh29:
	ldr	w2, [x8]
	bl	_regmap_write
LBB0_4:
	mov	w21, #0
LBB0_5:
	mov	x0, x21
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.cfi_endproc
                                        ; -- End function
	.comm	_CTRL_OFFSET,4,2                ; @CTRL_OFFSET
	.comm	_CTRL_PCAP_PR_MASK,4,2          ; @CTRL_PCAP_PR_MASK
	.comm	_INT_STS_OFFSET,4,2             ; @INT_STS_OFFSET
	.comm	_IXR_PCFG_DONE_MASK,4,2         ; @IXR_PCFG_DONE_MASK
	.comm	_INIT_POLL_DELAY,4,2            ; @INIT_POLL_DELAY
	.comm	_INIT_POLL_TIMEOUT,4,2          ; @INIT_POLL_TIMEOUT
	.comm	_FPGA_MGR_PARTIAL_RECONFIG,4,2  ; @FPGA_MGR_PARTIAL_RECONFIG
	.comm	_SLCR_LVL_SHFTR_EN_OFFSET,4,2   ; @SLCR_LVL_SHFTR_EN_OFFSET
	.comm	_LVL_SHFTR_ENABLE_PL_TO_PS,4,2  ; @LVL_SHFTR_ENABLE_PL_TO_PS
	.comm	_SLCR_FPGA_RST_CTRL_OFFSET,4,2  ; @SLCR_FPGA_RST_CTRL_OFFSET
	.comm	_FPGA_RST_NONE_MASK,4,2         ; @FPGA_RST_NONE_MASK
	.no_dead_strip	_zynq_fpga_ops_write_complete
.subsections_via_symbols
