	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_vmw_fifo_release               ## -- Begin function vmw_fifo_release
	.p2align	4, 0x90
_vmw_fifo_release:                      ## @vmw_fifo_release
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %rbx
	movq	16(%rdi), %r15
	movq	_SVGA_REG_SYNC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SVGA_SYNC_GENERIC@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_vmw_write
	movq	_SVGA_REG_BUSY@GOTPCREL(%rip), %r12
	.p2align	4, 0x90
LBB0_1:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r12), %esi
	movq	%rbx, %rdi
	callq	_vmw_read
	testq	%rax, %rax
	jne	LBB0_1
## %bb.2:
	movq	_SVGA_FIFO_FENCE@GOTPCREL(%rip), %rax
	movslq	(%rax), %rax
	leaq	(%r15,%rax,4), %rdi
	callq	_vmw_mmio_read
	movl	%eax, 12(%rbx)
	movq	_SVGA_REG_CONFIG_DONE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	8(%rbx), %edx
	movq	%rbx, %rdi
	callq	_vmw_write
	movq	_SVGA_REG_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	4(%rbx), %edx
	movq	%rbx, %rdi
	callq	_vmw_write
	movq	_SVGA_REG_TRACES@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%rbx), %edx
	movq	%rbx, %rdi
	callq	_vmw_write
	leaq	16(%r14), %rdi
	callq	_vmw_marker_queue_takedown
	xorl	%edi, %edi
	cmpq	$0, 8(%r14)
	setne	%dil
	callq	_likely
	testq	%rax, %rax
	je	LBB0_4
## %bb.3:
	movq	8(%r14), %rdi
	callq	_vfree
	movq	$0, 8(%r14)
LBB0_4:
	xorl	%edi, %edi
	cmpq	$0, (%r14)
	setne	%dil
	callq	_likely
	testq	%rax, %rax
	je	LBB0_6
## %bb.5:
	movq	(%r14), %rdi
	callq	_vfree
	movq	$0, (%r14)
LBB0_6:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_SVGA_REG_SYNC,4,2              ## @SVGA_REG_SYNC
	.comm	_SVGA_SYNC_GENERIC,4,2          ## @SVGA_SYNC_GENERIC
	.comm	_SVGA_REG_BUSY,4,2              ## @SVGA_REG_BUSY
	.comm	_SVGA_FIFO_FENCE,4,2            ## @SVGA_FIFO_FENCE
	.comm	_SVGA_REG_CONFIG_DONE,4,2       ## @SVGA_REG_CONFIG_DONE
	.comm	_SVGA_REG_ENABLE,4,2            ## @SVGA_REG_ENABLE
	.comm	_SVGA_REG_TRACES,4,2            ## @SVGA_REG_TRACES
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_vmw_fifo_release               ; -- Begin function vmw_fifo_release
	.p2align	2
_vmw_fifo_release:                      ; @vmw_fifo_release
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x1
	mov	x20, x0
	ldr	x21, [x0, #16]
Lloh0:
	adrp	x8, _SVGA_REG_SYNC@GOTPAGE
Lloh1:
	ldr	x8, [x8, _SVGA_REG_SYNC@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
Lloh3:
	adrp	x8, _SVGA_SYNC_GENERIC@GOTPAGE
Lloh4:
	ldr	x8, [x8, _SVGA_SYNC_GENERIC@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	bl	_vmw_write
Lloh6:
	adrp	x22, _SVGA_REG_BUSY@GOTPAGE
Lloh7:
	ldr	x22, [x22, _SVGA_REG_BUSY@GOTPAGEOFF]
LBB0_1:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x22]
	mov	x0, x20
	bl	_vmw_read
	cbnz	x0, LBB0_1
; %bb.2:
Lloh8:
	adrp	x8, _SVGA_FIFO_FENCE@GOTPAGE
Lloh9:
	ldr	x8, [x8, _SVGA_FIFO_FENCE@GOTPAGEOFF]
Lloh10:
	ldrsw	x8, [x8]
	add	x0, x21, x8, lsl #2
	bl	_vmw_mmio_read
	str	w0, [x20, #12]
Lloh11:
	adrp	x8, _SVGA_REG_CONFIG_DONE@GOTPAGE
Lloh12:
	ldr	x8, [x8, _SVGA_REG_CONFIG_DONE@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
	ldr	w2, [x20, #8]
	mov	x0, x20
	bl	_vmw_write
Lloh14:
	adrp	x8, _SVGA_REG_ENABLE@GOTPAGE
Lloh15:
	ldr	x8, [x8, _SVGA_REG_ENABLE@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
	ldr	w2, [x20, #4]
	mov	x0, x20
	bl	_vmw_write
Lloh17:
	adrp	x8, _SVGA_REG_TRACES@GOTPAGE
Lloh18:
	ldr	x8, [x8, _SVGA_REG_TRACES@GOTPAGEOFF]
Lloh19:
	ldr	w1, [x8]
	ldr	w2, [x20]
	mov	x0, x20
	bl	_vmw_write
	add	x0, x19, #16
	bl	_vmw_marker_queue_takedown
	ldr	x8, [x19, #8]
	cmp	x8, #0
	cset	w0, ne
	bl	_likely
	cbz	x0, LBB0_4
; %bb.3:
	ldr	x0, [x19, #8]
	bl	_vfree
	str	xzr, [x19, #8]
LBB0_4:
	ldr	x8, [x19]
	cmp	x8, #0
	cset	w0, ne
	bl	_likely
	cbz	x0, LBB0_6
; %bb.5:
	ldr	x0, [x19]
	bl	_vfree
	str	xzr, [x19]
LBB0_6:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.cfi_endproc
                                        ; -- End function
	.comm	_SVGA_REG_SYNC,4,2              ; @SVGA_REG_SYNC
	.comm	_SVGA_SYNC_GENERIC,4,2          ; @SVGA_SYNC_GENERIC
	.comm	_SVGA_REG_BUSY,4,2              ; @SVGA_REG_BUSY
	.comm	_SVGA_FIFO_FENCE,4,2            ; @SVGA_FIFO_FENCE
	.comm	_SVGA_REG_CONFIG_DONE,4,2       ; @SVGA_REG_CONFIG_DONE
	.comm	_SVGA_REG_ENABLE,4,2            ; @SVGA_REG_ENABLE
	.comm	_SVGA_REG_TRACES,4,2            ; @SVGA_REG_TRACES
.subsections_via_symbols
