	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function uvd_v4_2_start
_uvd_v4_2_start:                        ## @uvd_v4_2_start
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	(%rdi), %rax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movq	_mmUVD_STATUS@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movl	$4, %esi
	movl	$-5, %edx
	callq	_WREG32_P
	movq	%r14, %rdi
	movl	$1, %esi
	callq	_uvd_v4_2_set_dcm
	movq	_mmUVD_CGC_GATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%r12d, %r12d
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmSRBM_SOFT_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	$5, %edi
	callq	_mdelay
	movq	_mmUVD_VCPU_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$512, %esi                      ## imm = 0x200
	callq	_WREG32
	movq	_mmUVD_MASTINT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	movl	$-3, %edx
	callq	_WREG32_P
	movq	_mmUVD_LMI_SWAP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmUVD_MP_SWAP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmUVD_LMI_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$2109704, %esi                  ## imm = 0x203108
	callq	_WREG32
	movq	_mmUVD_MPC_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32
	movl	(%r15), %edi
	orl	$16, %eax
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmUVD_MPC_SET_MUXA0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$67903552, %esi                 ## imm = 0x40C2040
	callq	_WREG32
	movq	_mmUVD_MPC_SET_MUXA1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmUVD_MPC_SET_MUXB0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$67903552, %esi                 ## imm = 0x40C2040
	callq	_WREG32
	movq	_mmUVD_MPC_SET_MUXB1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmUVD_MPC_SET_ALU@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmUVD_MPC_SET_MUX@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$136, %esi
	callq	_WREG32
	movq	%r14, %rdi
	callq	_uvd_v4_2_mc_resume
	movq	_ixUVD_LMI_CACHE_CTRL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32_UVD_CTX
	movl	(%r14), %edi
	andl	$-17, %eax
	movl	%eax, %esi
	callq	_WREG32_UVD_CTX
	movq	_mmUVD_LMI_CTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	movl	$-257, %edx                     ## imm = 0xFEFF
	callq	_WREG32_P
	movq	_mmUVD_SOFT_RESET@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movq	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	(%r13), %edi
	movq	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	(%r13), %edi
	movq	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	notl	%edx
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	$10, %edi
	callq	_mdelay
LBB0_1:                                 ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_2 Depth 2
	movl	$100, %r15d
	.p2align	4, 0x90
LBB0_2:                                 ##   Parent Loop BB0_1 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movl	(%rbx), %edi
	callq	_RREG32
	testb	$2, %al
	jne	LBB0_6
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=2
	movl	$10, %edi
	callq	_mdelay
	decl	%r15d
	jne	LBB0_2
## %bb.4:                               ##   in Loop: Header=BB0_1 Depth=1
	leaq	L_.str(%rip), %rdi
	callq	_DRM_ERROR
	movl	(%r13), %edi
	movl	(%r14), %esi
	movl	%esi, %edx
	notl	%edx
	callq	_WREG32_P
	movl	$10, %edi
	callq	_mdelay
	movl	(%r13), %edi
	movl	(%r14), %edx
	notl	%edx
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	$10, %edi
	callq	_mdelay
	incl	%r12d
	cmpl	$10, %r12d
	jne	LBB0_1
## %bb.5:
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_ERROR
	movl	$-1, %r14d
	jmp	LBB0_7
LBB0_6:
	movq	_mmUVD_MASTINT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$6, %esi
	movl	$-7, %edx
	callq	_WREG32_P
	movl	(%rbx), %edi
	xorl	%r14d, %r14d
	xorl	%esi, %esi
	movl	$-5, %edx
	callq	_WREG32_P
	movq	_mmUVD_RBC_RB_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	movl	$285278465, %esi                ## imm = 0x11010101
	callq	_WREG32
	movq	_mmUVD_RBC_RB_WPTR_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmUVD_LMI_EXT40_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	movl	(%rbx), %edi
	callq	_upper_32_bits
	orl	$-2147024896, %eax              ## imm = 0x80070000
	movl	%r15d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmUVD_RBC_RB_RPTR@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r15), %edi
	callq	_RREG32
	movq	%rax, 8(%rbx)
	movq	_mmUVD_RBC_RB_WPTR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r15d
	movq	%rax, %rdi
	callq	_lower_32_bits
	movl	%r15d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmUVD_RBC_RB_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%rbx), %esi
	callq	_WREG32
	movl	4(%rbx), %edi
	callq	_order_base_2
	orl	$256, %eax                      ## imm = 0x100
	movl	(%r12), %edi
	movl	%eax, %esi
	movl	$-73504, %edx                   ## imm = 0xFFFEE0E0
	callq	_WREG32_P
LBB0_7:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_mmUVD_STATUS,4,2               ## @mmUVD_STATUS
	.comm	_mmUVD_CGC_GATE,4,2             ## @mmUVD_CGC_GATE
	.comm	_mmSRBM_SOFT_RESET,4,2          ## @mmSRBM_SOFT_RESET
	.comm	_SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,4,2 ## @SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK
	.comm	_mmUVD_VCPU_CNTL,4,2            ## @mmUVD_VCPU_CNTL
	.comm	_mmUVD_MASTINT_EN,4,2           ## @mmUVD_MASTINT_EN
	.comm	_mmUVD_LMI_SWAP_CNTL,4,2        ## @mmUVD_LMI_SWAP_CNTL
	.comm	_mmUVD_MP_SWAP_CNTL,4,2         ## @mmUVD_MP_SWAP_CNTL
	.comm	_mmUVD_LMI_CTRL,4,2             ## @mmUVD_LMI_CTRL
	.comm	_mmUVD_MPC_CNTL,4,2             ## @mmUVD_MPC_CNTL
	.comm	_mmUVD_MPC_SET_MUXA0,4,2        ## @mmUVD_MPC_SET_MUXA0
	.comm	_mmUVD_MPC_SET_MUXA1,4,2        ## @mmUVD_MPC_SET_MUXA1
	.comm	_mmUVD_MPC_SET_MUXB0,4,2        ## @mmUVD_MPC_SET_MUXB0
	.comm	_mmUVD_MPC_SET_MUXB1,4,2        ## @mmUVD_MPC_SET_MUXB1
	.comm	_mmUVD_MPC_SET_ALU,4,2          ## @mmUVD_MPC_SET_ALU
	.comm	_mmUVD_MPC_SET_MUX,4,2          ## @mmUVD_MPC_SET_MUX
	.comm	_ixUVD_LMI_CACHE_CTRL,4,2       ## @ixUVD_LMI_CACHE_CTRL
	.comm	_mmUVD_LMI_CTRL2,4,2            ## @mmUVD_LMI_CTRL2
	.comm	_mmUVD_SOFT_RESET,4,2           ## @mmUVD_SOFT_RESET
	.comm	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"UVD not responding, trying to reset the VCPU!!!\n"

L_.str.1:                               ## @.str.1
	.asciz	"UVD not responding, giving up!!!\n"

	.comm	_mmUVD_RBC_RB_CNTL,4,2          ## @mmUVD_RBC_RB_CNTL
	.comm	_mmUVD_RBC_RB_WPTR_CNTL,4,2     ## @mmUVD_RBC_RB_WPTR_CNTL
	.comm	_mmUVD_LMI_EXT40_ADDR,4,2       ## @mmUVD_LMI_EXT40_ADDR
	.comm	_mmUVD_RBC_RB_RPTR,4,2          ## @mmUVD_RBC_RB_RPTR
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ## @mmUVD_RBC_RB_WPTR
	.comm	_mmUVD_RBC_RB_BASE,4,2          ## @mmUVD_RBC_RB_BASE
	.no_dead_strip	_uvd_v4_2_start
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function uvd_v4_2_start
_uvd_v4_2_start:                        ; @uvd_v4_2_start
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldr	x20, [x0]
Lloh0:
	adrp	x21, _mmUVD_STATUS@GOTPAGE
Lloh1:
	ldr	x21, [x21, _mmUVD_STATUS@GOTPAGEOFF]
	ldr	w0, [x21]
	mov	w1, #4
	mov	w2, #-5
	bl	_WREG32_P
	mov	x0, x19
	mov	w1, #1
	bl	_uvd_v4_2_set_dcm
Lloh2:
	adrp	x8, _mmUVD_CGC_GATE@GOTPAGE
Lloh3:
	ldr	x8, [x8, _mmUVD_CGC_GATE@GOTPAGEOFF]
Lloh4:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh5:
	adrp	x8, _mmSRBM_SOFT_RESET@GOTPAGE
Lloh6:
	ldr	x8, [x8, _mmSRBM_SOFT_RESET@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
Lloh8:
	adrp	x8, _SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK@GOTPAGE
Lloh9:
	ldr	x8, [x8, _SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	mov	w0, #5
	bl	_mdelay
Lloh11:
	adrp	x8, _mmUVD_VCPU_CNTL@GOTPAGE
Lloh12:
	ldr	x8, [x8, _mmUVD_VCPU_CNTL@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
	mov	w1, #512
	bl	_WREG32
Lloh14:
	adrp	x22, _mmUVD_MASTINT_EN@GOTPAGE
Lloh15:
	ldr	x22, [x22, _mmUVD_MASTINT_EN@GOTPAGEOFF]
	ldr	w0, [x22]
	mov	w1, #0
	mov	w2, #-3
	bl	_WREG32_P
Lloh16:
	adrp	x8, _mmUVD_LMI_SWAP_CNTL@GOTPAGE
Lloh17:
	ldr	x8, [x8, _mmUVD_LMI_SWAP_CNTL@GOTPAGEOFF]
Lloh18:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh19:
	adrp	x8, _mmUVD_MP_SWAP_CNTL@GOTPAGE
Lloh20:
	ldr	x8, [x8, _mmUVD_MP_SWAP_CNTL@GOTPAGEOFF]
Lloh21:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh22:
	adrp	x8, _mmUVD_LMI_CTRL@GOTPAGE
Lloh23:
	ldr	x8, [x8, _mmUVD_LMI_CTRL@GOTPAGEOFF]
Lloh24:
	ldr	w0, [x8]
	mov	w1, #12552
	movk	w1, #32, lsl #16
	bl	_WREG32
Lloh25:
	adrp	x23, _mmUVD_MPC_CNTL@GOTPAGE
Lloh26:
	ldr	x23, [x23, _mmUVD_MPC_CNTL@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32
	ldr	w8, [x23]
	orr	w1, w0, #0x10
	mov	x0, x8
	bl	_WREG32
Lloh27:
	adrp	x8, _mmUVD_MPC_SET_MUXA0@GOTPAGE
Lloh28:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXA0@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	mov	w1, #8256
	movk	w1, #1036, lsl #16
	bl	_WREG32
Lloh30:
	adrp	x8, _mmUVD_MPC_SET_MUXA1@GOTPAGE
Lloh31:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXA1@GOTPAGEOFF]
Lloh32:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh33:
	adrp	x8, _mmUVD_MPC_SET_MUXB0@GOTPAGE
Lloh34:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXB0@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	mov	w1, #8256
	movk	w1, #1036, lsl #16
	bl	_WREG32
Lloh36:
	adrp	x8, _mmUVD_MPC_SET_MUXB1@GOTPAGE
Lloh37:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXB1@GOTPAGEOFF]
Lloh38:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh39:
	adrp	x8, _mmUVD_MPC_SET_ALU@GOTPAGE
Lloh40:
	ldr	x8, [x8, _mmUVD_MPC_SET_ALU@GOTPAGEOFF]
Lloh41:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh42:
	adrp	x8, _mmUVD_MPC_SET_MUX@GOTPAGE
Lloh43:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUX@GOTPAGEOFF]
Lloh44:
	ldr	w0, [x8]
	mov	w1, #136
	bl	_WREG32
	mov	x0, x19
	bl	_uvd_v4_2_mc_resume
Lloh45:
	adrp	x19, _ixUVD_LMI_CACHE_CTRL@GOTPAGE
Lloh46:
	ldr	x19, [x19, _ixUVD_LMI_CACHE_CTRL@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_RREG32_UVD_CTX
	ldr	w8, [x19]
	and	w1, w0, #0xffffffef
	mov	x0, x8
	bl	_WREG32_UVD_CTX
Lloh47:
	adrp	x8, _mmUVD_LMI_CTRL2@GOTPAGE
Lloh48:
	ldr	x8, [x8, _mmUVD_LMI_CTRL2@GOTPAGEOFF]
Lloh49:
	ldr	w0, [x8]
	mov	w1, #0
	mov	w2, #-257
	bl	_WREG32_P
Lloh50:
	adrp	x23, _mmUVD_SOFT_RESET@GOTPAGE
Lloh51:
	ldr	x23, [x23, _mmUVD_SOFT_RESET@GOTPAGEOFF]
	ldr	w0, [x23]
Lloh52:
	adrp	x8, _UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPAGE
Lloh53:
	ldr	x8, [x8, _UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh54:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w0, [x23]
Lloh55:
	adrp	x8, _UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPAGE
Lloh56:
	ldr	x8, [x8, _UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh57:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w0, [x23]
Lloh58:
	adrp	x24, _UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPAGE
Lloh59:
	ldr	x24, [x24, _UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPAGEOFF]
	ldr	w8, [x24]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	mov	w0, #10
	bl	_mdelay
	mov	w25, #0
Lloh60:
	adrp	x19, l_.str@PAGE
Lloh61:
	add	x19, x19, l_.str@PAGEOFF
LBB0_1:                                 ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
	mov	w26, #100
LBB0_2:                                 ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ldr	w0, [x21]
	bl	_RREG32
	tbnz	w0, #1, LBB0_6
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=2
	mov	w0, #10
	bl	_mdelay
	subs	w26, w26, #1
	b.ne	LBB0_2
; %bb.4:                                ;   in Loop: Header=BB0_1 Depth=1
	mov	x0, x19
	bl	_DRM_ERROR
	ldr	w0, [x23]
	ldr	w1, [x24]
	mvn	w2, w1
	bl	_WREG32_P
	mov	w0, #10
	bl	_mdelay
	ldr	w0, [x23]
	ldr	w8, [x24]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	mov	w0, #10
	bl	_mdelay
	add	w25, w25, #1
	cmp	w25, #10
	b.ne	LBB0_1
; %bb.5:
Lloh62:
	adrp	x0, l_.str.1@PAGE
Lloh63:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_ERROR
	mov	w0, #-1
	b	LBB0_7
LBB0_6:
	ldr	w0, [x22]
	mov	w1, #6
	mov	w2, #-7
	bl	_WREG32_P
	ldr	w0, [x21]
	mov	w1, #0
	mov	w2, #-5
	bl	_WREG32_P
Lloh64:
	adrp	x21, _mmUVD_RBC_RB_CNTL@GOTPAGE
Lloh65:
	ldr	x21, [x21, _mmUVD_RBC_RB_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	mov	w1, #257
	movk	w1, #4353, lsl #16
	bl	_WREG32
Lloh66:
	adrp	x8, _mmUVD_RBC_RB_WPTR_CNTL@GOTPAGE
Lloh67:
	ldr	x8, [x8, _mmUVD_RBC_RB_WPTR_CNTL@GOTPAGEOFF]
Lloh68:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh69:
	adrp	x8, _mmUVD_LMI_EXT40_ADDR@GOTPAGE
Lloh70:
	ldr	x8, [x8, _mmUVD_LMI_EXT40_ADDR@GOTPAGEOFF]
Lloh71:
	ldr	w19, [x8]
	ldr	w0, [x20]
	bl	_upper_32_bits
	mov	w8, #-2147024896
	orr	w1, w0, w8
	mov	x0, x19
	bl	_WREG32
Lloh72:
	adrp	x19, _mmUVD_RBC_RB_RPTR@GOTPAGE
Lloh73:
	ldr	x19, [x19, _mmUVD_RBC_RB_RPTR@GOTPAGEOFF]
	ldr	w0, [x19]
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x19]
	bl	_RREG32
	str	x0, [x20, #8]
Lloh74:
	adrp	x8, _mmUVD_RBC_RB_WPTR@GOTPAGE
Lloh75:
	ldr	x8, [x8, _mmUVD_RBC_RB_WPTR@GOTPAGEOFF]
Lloh76:
	ldr	w19, [x8]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_WREG32
Lloh77:
	adrp	x8, _mmUVD_RBC_RB_BASE@GOTPAGE
Lloh78:
	ldr	x8, [x8, _mmUVD_RBC_RB_BASE@GOTPAGEOFF]
Lloh79:
	ldr	w0, [x8]
	ldr	w1, [x20]
	bl	_WREG32
	ldr	w0, [x20, #4]
	bl	_order_base_2
	orr	w1, w0, #0x100
	ldr	w0, [x21]
	mov	w2, #57568
	movk	w2, #65534, lsl #16
	bl	_WREG32_P
	mov	w0, #0
LBB0_7:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGot	Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGot	Lloh64, Lloh65
	.cfi_endproc
                                        ; -- End function
	.comm	_mmUVD_STATUS,4,2               ; @mmUVD_STATUS
	.comm	_mmUVD_CGC_GATE,4,2             ; @mmUVD_CGC_GATE
	.comm	_mmSRBM_SOFT_RESET,4,2          ; @mmSRBM_SOFT_RESET
	.comm	_SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,4,2 ; @SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK
	.comm	_mmUVD_VCPU_CNTL,4,2            ; @mmUVD_VCPU_CNTL
	.comm	_mmUVD_MASTINT_EN,4,2           ; @mmUVD_MASTINT_EN
	.comm	_mmUVD_LMI_SWAP_CNTL,4,2        ; @mmUVD_LMI_SWAP_CNTL
	.comm	_mmUVD_MP_SWAP_CNTL,4,2         ; @mmUVD_MP_SWAP_CNTL
	.comm	_mmUVD_LMI_CTRL,4,2             ; @mmUVD_LMI_CTRL
	.comm	_mmUVD_MPC_CNTL,4,2             ; @mmUVD_MPC_CNTL
	.comm	_mmUVD_MPC_SET_MUXA0,4,2        ; @mmUVD_MPC_SET_MUXA0
	.comm	_mmUVD_MPC_SET_MUXA1,4,2        ; @mmUVD_MPC_SET_MUXA1
	.comm	_mmUVD_MPC_SET_MUXB0,4,2        ; @mmUVD_MPC_SET_MUXB0
	.comm	_mmUVD_MPC_SET_MUXB1,4,2        ; @mmUVD_MPC_SET_MUXB1
	.comm	_mmUVD_MPC_SET_ALU,4,2          ; @mmUVD_MPC_SET_ALU
	.comm	_mmUVD_MPC_SET_MUX,4,2          ; @mmUVD_MPC_SET_MUX
	.comm	_ixUVD_LMI_CACHE_CTRL,4,2       ; @ixUVD_LMI_CACHE_CTRL
	.comm	_mmUVD_LMI_CTRL2,4,2            ; @mmUVD_LMI_CTRL2
	.comm	_mmUVD_SOFT_RESET,4,2           ; @mmUVD_SOFT_RESET
	.comm	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"UVD not responding, trying to reset the VCPU!!!\n"

l_.str.1:                               ; @.str.1
	.asciz	"UVD not responding, giving up!!!\n"

	.comm	_mmUVD_RBC_RB_CNTL,4,2          ; @mmUVD_RBC_RB_CNTL
	.comm	_mmUVD_RBC_RB_WPTR_CNTL,4,2     ; @mmUVD_RBC_RB_WPTR_CNTL
	.comm	_mmUVD_LMI_EXT40_ADDR,4,2       ; @mmUVD_LMI_EXT40_ADDR
	.comm	_mmUVD_RBC_RB_RPTR,4,2          ; @mmUVD_RBC_RB_RPTR
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ; @mmUVD_RBC_RB_WPTR
	.comm	_mmUVD_RBC_RB_BASE,4,2          ; @mmUVD_RBC_RB_BASE
	.no_dead_strip	_uvd_v4_2_start
.subsections_via_symbols
