	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_intel_ddi_enable_pipe_clock    ## -- Begin function intel_ddi_enable_pipe_clock
	.p2align	4, 0x90
_intel_ddi_enable_pipe_clock:           ## @intel_ddi_enable_pipe_clock
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movl	4(%rdi), %edi
	callq	_to_intel_crtc
	movq	%rax, %rbx
	movl	(%rax), %edi
	callq	_to_i915
	movq	%rax, %r14
	movq	%rbx, %rdi
	callq	_intel_ddi_get_crtc_encoder
	movl	(%r15), %ebx
	movq	_TRANSCODER_EDP@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %ebx
	jne	LBB0_1
## %bb.5:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_1:
	movl	(%rax), %r15d
	movq	%r14, %rdi
	callq	_INTEL_GEN
	movl	%eax, %r12d
	movl	%ebx, %edi
	callq	_TRANS_CLK_SEL
	movl	%eax, %r14d
	movl	%r15d, %edi
	cmpl	$12, %r12d
	jl	LBB0_3
## %bb.2:
	callq	_TGL_TRANS_CLK_SEL_PORT
	jmp	LBB0_4
LBB0_3:
	callq	_TRANS_CLK_SEL_PORT
LBB0_4:
	movl	%r14d, %edi
	movl	%eax, %esi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_I915_WRITE                     ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_TRANSCODER_EDP,4,2             ## @TRANSCODER_EDP
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_intel_ddi_enable_pipe_clock    ; -- Begin function intel_ddi_enable_pipe_clock
	.p2align	2
_intel_ddi_enable_pipe_clock:           ; @intel_ddi_enable_pipe_clock
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x0
	ldr	w0, [x0, #4]
	bl	_to_intel_crtc
	mov	x21, x0
	ldr	w0, [x0]
	bl	_to_i915
	mov	x19, x0
	mov	x0, x21
	bl	_intel_ddi_get_crtc_encoder
	ldr	w21, [x20]
Lloh0:
	adrp	x8, _TRANSCODER_EDP@GOTPAGE
Lloh1:
	ldr	x8, [x8, _TRANSCODER_EDP@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cmp	w21, w8
	b.ne	LBB0_2
; %bb.1:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_2:
	ldr	w20, [x0]
	mov	x0, x19
	bl	_INTEL_GEN
	mov	x22, x0
	mov	x0, x21
	bl	_TRANS_CLK_SEL
	mov	x19, x0
	mov	x0, x20
	cmp	w22, #12
	b.lt	LBB0_4
; %bb.3:
	bl	_TGL_TRANS_CLK_SEL_PORT
	b	LBB0_5
LBB0_4:
	bl	_TRANS_CLK_SEL_PORT
LBB0_5:
	mov	x1, x0
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_I915_WRITE
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_TRANSCODER_EDP,4,2             ; @TRANSCODER_EDP
.subsections_via_symbols
