	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ni_copy_and_switch_arb_sets
_ni_copy_and_switch_arb_sets:           ## @ni_copy_and_switch_arb_sets
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	addl	$-128, %esi
	cmpl	$4, %esi
	jae	LBB0_1
## %bb.3:
	movl	%edx, %r15d
	movslq	%esi, %rax
	leaq	l_switch.table.ni_copy_and_switch_arb_sets(%rip), %rcx
	movq	(%rcx,%rax,8), %rcx
	leaq	l_switch.table.ni_copy_and_switch_arb_sets.1(%rip), %rsi
	movq	(%rsi,%rax,8), %rbx
	leaq	l_switch.table.ni_copy_and_switch_arb_sets.2(%rip), %rsi
	movq	(%rsi,%rax,8), %r13
	leaq	l_switch.table.ni_copy_and_switch_arb_sets.3(%rip), %rsi
	movq	(%rsi,%rax,8), %r14
	movl	(%rcx), %edi
	callq	_RREG32
	movl	%eax, %r12d
	movl	(%rbx), %edi
	callq	_RREG32
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	_MC_ARB_BURST_TIME@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %ebx
	andl	(%r13), %ebx
	movb	(%r14), %cl
	sarl	%cl, %ebx
	leal	-128(%r15), %eax
	cmpl	$3, %eax
	ja	LBB0_1
## %bb.4:
	movq	%r15, %r14
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_9:
	movq	_MC_ARB_DRAM_TIMING_3@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_MC_ARB_DRAM_TIMING2_3@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_MC_ARB_BURST_TIME@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	%ebx, %edi
	callq	_STATE3
	movq	_STATE3_MASK@GOTPCREL(%rip), %rcx
	jmp	LBB0_6
LBB0_1:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_2
LBB0_8:
	movq	_MC_ARB_DRAM_TIMING_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_MC_ARB_DRAM_TIMING2_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_MC_ARB_BURST_TIME@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	%ebx, %edi
	callq	_STATE2
	movq	_STATE2_MASK@GOTPCREL(%rip), %rcx
	jmp	LBB0_6
LBB0_7:
	movq	_MC_ARB_DRAM_TIMING_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_MC_ARB_DRAM_TIMING2_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_MC_ARB_BURST_TIME@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	%ebx, %edi
	callq	_STATE1
	movq	_STATE1_MASK@GOTPCREL(%rip), %rcx
	jmp	LBB0_6
LBB0_5:
	movq	_MC_ARB_DRAM_TIMING@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_MC_ARB_DRAM_TIMING2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
	movq	_MC_ARB_BURST_TIME@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	%ebx, %edi
	callq	_STATE0
	movq	_STATE0_MASK@GOTPCREL(%rip), %rcx
LBB0_6:
	movl	(%rcx), %edx
	notl	%edx
	movl	%r15d, %edi
	movl	%eax, %esi
	callq	_WREG32_P
	movq	_MC_CG_CONFIG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	orl	$15, %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_MC_ARB_CG@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%r14d, %edi
	callq	_CG_ARB_REQ
	movq	_CG_ARB_REQ_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32_P
	xorl	%eax, %eax
LBB0_2:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_9, LBB0_9-LJTI0_0
.set L0_0_set_8, LBB0_8-LJTI0_0
.set L0_0_set_7, LBB0_7-LJTI0_0
.set L0_0_set_5, LBB0_5-LJTI0_0
LJTI0_0:
	.long	L0_0_set_9
	.long	L0_0_set_8
	.long	L0_0_set_7
	.long	L0_0_set_5
	.end_data_region
                                        ## -- End function
	.comm	_MC_ARB_DRAM_TIMING,4,2         ## @MC_ARB_DRAM_TIMING
	.comm	_MC_ARB_DRAM_TIMING2,4,2        ## @MC_ARB_DRAM_TIMING2
	.comm	_MC_ARB_BURST_TIME,4,2          ## @MC_ARB_BURST_TIME
	.comm	_STATE0_MASK,4,2                ## @STATE0_MASK
	.comm	_STATE0_SHIFT,4,2               ## @STATE0_SHIFT
	.comm	_MC_ARB_DRAM_TIMING_1,4,2       ## @MC_ARB_DRAM_TIMING_1
	.comm	_MC_ARB_DRAM_TIMING2_1,4,2      ## @MC_ARB_DRAM_TIMING2_1
	.comm	_STATE1_MASK,4,2                ## @STATE1_MASK
	.comm	_STATE1_SHIFT,4,2               ## @STATE1_SHIFT
	.comm	_MC_ARB_DRAM_TIMING_2,4,2       ## @MC_ARB_DRAM_TIMING_2
	.comm	_MC_ARB_DRAM_TIMING2_2,4,2      ## @MC_ARB_DRAM_TIMING2_2
	.comm	_STATE2_MASK,4,2                ## @STATE2_MASK
	.comm	_STATE2_SHIFT,4,2               ## @STATE2_SHIFT
	.comm	_MC_ARB_DRAM_TIMING_3,4,2       ## @MC_ARB_DRAM_TIMING_3
	.comm	_MC_ARB_DRAM_TIMING2_3,4,2      ## @MC_ARB_DRAM_TIMING2_3
	.comm	_STATE3_MASK,4,2                ## @STATE3_MASK
	.comm	_STATE3_SHIFT,4,2               ## @STATE3_SHIFT
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_MC_CG_CONFIG,4,2               ## @MC_CG_CONFIG
	.comm	_MC_ARB_CG,4,2                  ## @MC_ARB_CG
	.comm	_CG_ARB_REQ_MASK,4,2            ## @CG_ARB_REQ_MASK
	.no_dead_strip	_ni_copy_and_switch_arb_sets
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.ni_copy_and_switch_arb_sets
l_switch.table.ni_copy_and_switch_arb_sets:
	.quad	_MC_ARB_DRAM_TIMING_3
	.quad	_MC_ARB_DRAM_TIMING_2
	.quad	_MC_ARB_DRAM_TIMING_1
	.quad	_MC_ARB_DRAM_TIMING

	.p2align	3                               ## @switch.table.ni_copy_and_switch_arb_sets.1
l_switch.table.ni_copy_and_switch_arb_sets.1:
	.quad	_MC_ARB_DRAM_TIMING2_3
	.quad	_MC_ARB_DRAM_TIMING2_2
	.quad	_MC_ARB_DRAM_TIMING2_1
	.quad	_MC_ARB_DRAM_TIMING2

	.p2align	3                               ## @switch.table.ni_copy_and_switch_arb_sets.2
l_switch.table.ni_copy_and_switch_arb_sets.2:
	.quad	_STATE3_MASK
	.quad	_STATE2_MASK
	.quad	_STATE1_MASK
	.quad	_STATE0_MASK

	.p2align	3                               ## @switch.table.ni_copy_and_switch_arb_sets.3
l_switch.table.ni_copy_and_switch_arb_sets.3:
	.quad	_STATE3_SHIFT
	.quad	_STATE2_SHIFT
	.quad	_STATE1_SHIFT
	.quad	_STATE0_SHIFT

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ni_copy_and_switch_arb_sets
_ni_copy_and_switch_arb_sets:           ; @ni_copy_and_switch_arb_sets
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	sub	w8, w1, #128
	cmp	w8, #4
	b.hs	LBB0_4
; %bb.1:
	mov	x19, x2
	sbfiz	x21, x8, #3, #32
Lloh0:
	adrp	x8, l_switch.table.ni_copy_and_switch_arb_sets@PAGE
Lloh1:
	add	x8, x8, l_switch.table.ni_copy_and_switch_arb_sets@PAGEOFF
	ldr	x8, [x8, x21]
Lloh2:
	adrp	x9, l_switch.table.ni_copy_and_switch_arb_sets.1@PAGE
Lloh3:
	add	x9, x9, l_switch.table.ni_copy_and_switch_arb_sets.1@PAGEOFF
	ldr	x20, [x9, x21]
	ldr	w0, [x8]
	bl	_RREG32
	mov	x22, x0
	ldr	w0, [x20]
	bl	_RREG32
	mov	x20, x0
Lloh4:
	adrp	x23, _MC_ARB_BURST_TIME@GOTPAGE
Lloh5:
	ldr	x23, [x23, _MC_ARB_BURST_TIME@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32
	sub	w8, w19, #128
	cmp	w8, #3
	b.hi	LBB0_4
; %bb.2:
Lloh6:
	adrp	x9, l_switch.table.ni_copy_and_switch_arb_sets.2@PAGE
Lloh7:
	add	x9, x9, l_switch.table.ni_copy_and_switch_arb_sets.2@PAGEOFF
	ldr	x9, [x9, x21]
Lloh8:
	adrp	x10, l_switch.table.ni_copy_and_switch_arb_sets.3@PAGE
Lloh9:
	add	x10, x10, l_switch.table.ni_copy_and_switch_arb_sets.3@PAGEOFF
	ldr	x10, [x10, x21]
	ldr	w9, [x9]
	and	w9, w9, w0
	ldr	w10, [x10]
	asr	w21, w9, w10
Lloh10:
	adrp	x9, lJTI0_0@PAGE
Lloh11:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_3
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_3:
Lloh12:
	adrp	x8, _MC_ARB_DRAM_TIMING_3@GOTPAGE
Lloh13:
	ldr	x8, [x8, _MC_ARB_DRAM_TIMING_3@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	mov	x1, x22
	bl	_WREG32
Lloh15:
	adrp	x8, _MC_ARB_DRAM_TIMING2_3@GOTPAGE
Lloh16:
	ldr	x8, [x8, _MC_ARB_DRAM_TIMING2_3@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
	ldr	w20, [x23]
	mov	x0, x21
	bl	_STATE3
	mov	x1, x0
Lloh18:
	adrp	x8, _STATE3_MASK@GOTPAGE
Lloh19:
	ldr	x8, [x8, _STATE3_MASK@GOTPAGEOFF]
	b	LBB0_8
LBB0_4:
Lloh20:
	adrp	x8, _EINVAL@GOTPAGE
Lloh21:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_9
LBB0_5:
Lloh23:
	adrp	x8, _MC_ARB_DRAM_TIMING_2@GOTPAGE
Lloh24:
	ldr	x8, [x8, _MC_ARB_DRAM_TIMING_2@GOTPAGEOFF]
Lloh25:
	ldr	w0, [x8]
	mov	x1, x22
	bl	_WREG32
Lloh26:
	adrp	x8, _MC_ARB_DRAM_TIMING2_2@GOTPAGE
Lloh27:
	ldr	x8, [x8, _MC_ARB_DRAM_TIMING2_2@GOTPAGEOFF]
Lloh28:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
	ldr	w20, [x23]
	mov	x0, x21
	bl	_STATE2
	mov	x1, x0
Lloh29:
	adrp	x8, _STATE2_MASK@GOTPAGE
Lloh30:
	ldr	x8, [x8, _STATE2_MASK@GOTPAGEOFF]
	b	LBB0_8
LBB0_6:
Lloh31:
	adrp	x8, _MC_ARB_DRAM_TIMING_1@GOTPAGE
Lloh32:
	ldr	x8, [x8, _MC_ARB_DRAM_TIMING_1@GOTPAGEOFF]
Lloh33:
	ldr	w0, [x8]
	mov	x1, x22
	bl	_WREG32
Lloh34:
	adrp	x8, _MC_ARB_DRAM_TIMING2_1@GOTPAGE
Lloh35:
	ldr	x8, [x8, _MC_ARB_DRAM_TIMING2_1@GOTPAGEOFF]
Lloh36:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
	ldr	w20, [x23]
	mov	x0, x21
	bl	_STATE1
	mov	x1, x0
Lloh37:
	adrp	x8, _STATE1_MASK@GOTPAGE
Lloh38:
	ldr	x8, [x8, _STATE1_MASK@GOTPAGEOFF]
	b	LBB0_8
LBB0_7:
Lloh39:
	adrp	x8, _MC_ARB_DRAM_TIMING@GOTPAGE
Lloh40:
	ldr	x8, [x8, _MC_ARB_DRAM_TIMING@GOTPAGEOFF]
Lloh41:
	ldr	w0, [x8]
	mov	x1, x22
	bl	_WREG32
Lloh42:
	adrp	x8, _MC_ARB_DRAM_TIMING2@GOTPAGE
Lloh43:
	ldr	x8, [x8, _MC_ARB_DRAM_TIMING2@GOTPAGEOFF]
Lloh44:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
	ldr	w20, [x23]
	mov	x0, x21
	bl	_STATE0
	mov	x1, x0
Lloh45:
	adrp	x8, _STATE0_MASK@GOTPAGE
Lloh46:
	ldr	x8, [x8, _STATE0_MASK@GOTPAGEOFF]
LBB0_8:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	x0, x20
	bl	_WREG32_P
Lloh47:
	adrp	x20, _MC_CG_CONFIG@GOTPAGE
Lloh48:
	ldr	x20, [x20, _MC_CG_CONFIG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	orr	w1, w0, #0xf
	ldr	w0, [x20]
	bl	_WREG32
Lloh49:
	adrp	x8, _MC_ARB_CG@GOTPAGE
Lloh50:
	ldr	x8, [x8, _MC_ARB_CG@GOTPAGEOFF]
Lloh51:
	ldr	w20, [x8]
	mov	x0, x19
	bl	_CG_ARB_REQ
	mov	x1, x0
Lloh52:
	adrp	x8, _CG_ARB_REQ_MASK@GOTPAGE
Lloh53:
	ldr	x8, [x8, _CG_ARB_REQ_MASK@GOTPAGEOFF]
Lloh54:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	x0, x20
	bl	_WREG32_P
	mov	w0, #0
LBB0_9:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh47, Lloh48
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_3-LBB0_3)>>2
	.byte	(LBB0_5-LBB0_3)>>2
	.byte	(LBB0_6-LBB0_3)>>2
	.byte	(LBB0_7-LBB0_3)>>2
                                        ; -- End function
	.comm	_MC_ARB_DRAM_TIMING,4,2         ; @MC_ARB_DRAM_TIMING
	.comm	_MC_ARB_DRAM_TIMING2,4,2        ; @MC_ARB_DRAM_TIMING2
	.comm	_MC_ARB_BURST_TIME,4,2          ; @MC_ARB_BURST_TIME
	.comm	_STATE0_MASK,4,2                ; @STATE0_MASK
	.comm	_STATE0_SHIFT,4,2               ; @STATE0_SHIFT
	.comm	_MC_ARB_DRAM_TIMING_1,4,2       ; @MC_ARB_DRAM_TIMING_1
	.comm	_MC_ARB_DRAM_TIMING2_1,4,2      ; @MC_ARB_DRAM_TIMING2_1
	.comm	_STATE1_MASK,4,2                ; @STATE1_MASK
	.comm	_STATE1_SHIFT,4,2               ; @STATE1_SHIFT
	.comm	_MC_ARB_DRAM_TIMING_2,4,2       ; @MC_ARB_DRAM_TIMING_2
	.comm	_MC_ARB_DRAM_TIMING2_2,4,2      ; @MC_ARB_DRAM_TIMING2_2
	.comm	_STATE2_MASK,4,2                ; @STATE2_MASK
	.comm	_STATE2_SHIFT,4,2               ; @STATE2_SHIFT
	.comm	_MC_ARB_DRAM_TIMING_3,4,2       ; @MC_ARB_DRAM_TIMING_3
	.comm	_MC_ARB_DRAM_TIMING2_3,4,2      ; @MC_ARB_DRAM_TIMING2_3
	.comm	_STATE3_MASK,4,2                ; @STATE3_MASK
	.comm	_STATE3_SHIFT,4,2               ; @STATE3_SHIFT
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_MC_CG_CONFIG,4,2               ; @MC_CG_CONFIG
	.comm	_MC_ARB_CG,4,2                  ; @MC_ARB_CG
	.comm	_CG_ARB_REQ_MASK,4,2            ; @CG_ARB_REQ_MASK
	.no_dead_strip	_ni_copy_and_switch_arb_sets
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.ni_copy_and_switch_arb_sets
l_switch.table.ni_copy_and_switch_arb_sets:
	.quad	_MC_ARB_DRAM_TIMING_3
	.quad	_MC_ARB_DRAM_TIMING_2
	.quad	_MC_ARB_DRAM_TIMING_1
	.quad	_MC_ARB_DRAM_TIMING

	.p2align	3                               ; @switch.table.ni_copy_and_switch_arb_sets.1
l_switch.table.ni_copy_and_switch_arb_sets.1:
	.quad	_MC_ARB_DRAM_TIMING2_3
	.quad	_MC_ARB_DRAM_TIMING2_2
	.quad	_MC_ARB_DRAM_TIMING2_1
	.quad	_MC_ARB_DRAM_TIMING2

	.p2align	3                               ; @switch.table.ni_copy_and_switch_arb_sets.2
l_switch.table.ni_copy_and_switch_arb_sets.2:
	.quad	_STATE3_MASK
	.quad	_STATE2_MASK
	.quad	_STATE1_MASK
	.quad	_STATE0_MASK

	.p2align	3                               ; @switch.table.ni_copy_and_switch_arb_sets.3
l_switch.table.ni_copy_and_switch_arb_sets.3:
	.quad	_STATE3_SHIFT
	.quad	_STATE2_SHIFT
	.quad	_STATE1_SHIFT
	.quad	_STATE0_SHIFT

.subsections_via_symbols
