	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gmc_v10_0_emit_pasid_mapping
_gmc_v10_0_emit_pasid_mapping:          ## @gmc_v10_0_emit_pasid_mapping
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r14d
	movl	%esi, %ebx
	movq	%rdi, %r15
	movq	(%rdi), %rax
	movq	(%rax), %rax
	movq	_AMDGPU_GFXHUB_0@GOTPCREL(%rip), %rcx
	movq	_OSSSYS@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edi
	cmpq	(%rcx), %rax
	jne	LBB0_1
## %bb.2:
	movq	_mmIH_VMID_0_LUT@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_1:
	movq	_mmIH_VMID_0_LUT_MM@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	addl	%eax, %ebx
	movq	%r15, %rdi
	movl	%ebx, %esi
	movl	%r14d, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_emit_wreg          ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_GFXHUB_0,8,3            ## @AMDGPU_GFXHUB_0
	.comm	_OSSSYS,4,2                     ## @OSSSYS
	.comm	_mmIH_VMID_0_LUT,4,2            ## @mmIH_VMID_0_LUT
	.comm	_mmIH_VMID_0_LUT_MM,4,2         ## @mmIH_VMID_0_LUT_MM
	.no_dead_strip	_gmc_v10_0_emit_pasid_mapping
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gmc_v10_0_emit_pasid_mapping
_gmc_v10_0_emit_pasid_mapping:          ; @gmc_v10_0_emit_pasid_mapping
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x2
	mov	x20, x1
	mov	x21, x0
	ldr	x8, [x0]
Lloh0:
	adrp	x9, _AMDGPU_GFXHUB_0@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMDGPU_GFXHUB_0@GOTPAGEOFF]
	ldr	x8, [x8]
Lloh2:
	ldr	x9, [x9]
Lloh3:
	adrp	x10, _OSSSYS@GOTPAGE
Lloh4:
	ldr	x10, [x10, _OSSSYS@GOTPAGEOFF]
Lloh5:
	adrp	x11, _mmIH_VMID_0_LUT@GOTPAGE
Lloh6:
	ldr	x11, [x11, _mmIH_VMID_0_LUT@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x10]
Lloh8:
	adrp	x10, _mmIH_VMID_0_LUT_MM@GOTPAGE
Lloh9:
	ldr	x10, [x10, _mmIH_VMID_0_LUT_MM@GOTPAGEOFF]
	cmp	x8, x9
	csel	x8, x11, x10, eq
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	add	w1, w0, w20
	mov	x0, x21
	mov	x2, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_amdgpu_ring_emit_wreg
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh7
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_GFXHUB_0,8,3            ; @AMDGPU_GFXHUB_0
	.comm	_OSSSYS,4,2                     ; @OSSSYS
	.comm	_mmIH_VMID_0_LUT,4,2            ; @mmIH_VMID_0_LUT
	.comm	_mmIH_VMID_0_LUT_MM,4,2         ; @mmIH_VMID_0_LUT_MM
	.no_dead_strip	_gmc_v10_0_emit_pasid_mapping
.subsections_via_symbols
