	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function trinity_set_divider_value
_trinity_set_divider_value:             ## @trinity_set_divider_value
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r15d
	movl	%esi, %r12d
	movq	%rdi, %r14
	movq	_TRINITY_SIZEOF_DPM_STATE_TABLE@GOTPCREL(%rip), %rax
	imull	(%rax), %r12d
	movq	_COMPUTE_ENGINE_PLL_PARAM@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	leaq	-48(%rbp), %r8
	xorl	%ecx, %ecx
	callq	_radeon_atom_get_clock_dividers
	testl	%eax, %eax
	jne	LBB0_3
## %bb.1:
	movq	_SMU_SCLK_DPM_STATE_0_CNTL_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	addl	%r12d, %edi
	callq	_RREG32_SMC
	movq	_CLK_DIVIDER_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	-48(%rbp), %edi
	callq	_CLK_DIVIDER
	orl	%eax, %ebx
	movq	_SMU_SCLK_DPM_STATE_0_CNTL_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	addl	%r12d, %edi
	movl	%ebx, %esi
	callq	_WREG32_SMC
	movl	(%r13), %esi
	movl	%r15d, %edx
	shrl	$31, %edx
	addl	%r15d, %edx
	sarl	%edx
	leaq	-48(%rbp), %r8
	movq	%r14, %rdi
	xorl	%ecx, %ecx
	callq	_radeon_atom_get_clock_dividers
	testl	%eax, %eax
	jne	LBB0_3
## %bb.2:
	movq	_SMU_SCLK_DPM_STATE_0_PG_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	addl	%r12d, %edi
	callq	_RREG32_SMC
	movq	_PD_SCLK_DIVIDER_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	-48(%rbp), %edi
	callq	_PD_SCLK_DIVIDER
	orl	%eax, %ebx
	addl	(%r14), %r12d
	movl	%r12d, %edi
	movl	%ebx, %esi
	callq	_WREG32_SMC
LBB0_3:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_TRINITY_SIZEOF_DPM_STATE_TABLE,4,2 ## @TRINITY_SIZEOF_DPM_STATE_TABLE
	.comm	_COMPUTE_ENGINE_PLL_PARAM,4,2   ## @COMPUTE_ENGINE_PLL_PARAM
	.comm	_SMU_SCLK_DPM_STATE_0_CNTL_0,4,2 ## @SMU_SCLK_DPM_STATE_0_CNTL_0
	.comm	_CLK_DIVIDER_MASK,4,2           ## @CLK_DIVIDER_MASK
	.comm	_SMU_SCLK_DPM_STATE_0_PG_CNTL,4,2 ## @SMU_SCLK_DPM_STATE_0_PG_CNTL
	.comm	_PD_SCLK_DIVIDER_MASK,4,2       ## @PD_SCLK_DIVIDER_MASK
	.no_dead_strip	_trinity_set_divider_value
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function trinity_set_divider_value
_trinity_set_divider_value:             ; @trinity_set_divider_value
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x2
	mov	x21, x1
	mov	x19, x0
Lloh0:
	adrp	x8, _TRINITY_SIZEOF_DPM_STATE_TABLE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _TRINITY_SIZEOF_DPM_STATE_TABLE@GOTPAGEOFF]
Lloh2:
	ldr	w23, [x8]
Lloh3:
	adrp	x22, _COMPUTE_ENGINE_PLL_PARAM@GOTPAGE
Lloh4:
	ldr	x22, [x22, _COMPUTE_ENGINE_PLL_PARAM@GOTPAGEOFF]
	ldr	w1, [x22]
	add	x4, sp, #8
	mov	w3, #0
	bl	_radeon_atom_get_clock_dividers
	cbnz	w0, LBB0_3
; %bb.1:
	mul	w21, w23, w21
Lloh5:
	adrp	x23, _SMU_SCLK_DPM_STATE_0_CNTL_0@GOTPAGE
Lloh6:
	ldr	x23, [x23, _SMU_SCLK_DPM_STATE_0_CNTL_0@GOTPAGEOFF]
	ldr	w8, [x23]
	add	w0, w8, w21
	bl	_RREG32_SMC
Lloh7:
	adrp	x8, _CLK_DIVIDER_MASK@GOTPAGE
Lloh8:
	ldr	x8, [x8, _CLK_DIVIDER_MASK@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	bic	w24, w0, w8
	ldr	w0, [sp, #8]
	bl	_CLK_DIVIDER
	orr	w1, w0, w24
	ldr	w8, [x23]
	add	w0, w8, w21
	bl	_WREG32_SMC
	ldr	w1, [x22]
	cmp	w20, #0
	cinc	w8, w20, lt
	asr	w2, w8, #1
	add	x4, sp, #8
	mov	x0, x19
	mov	w3, #0
	bl	_radeon_atom_get_clock_dividers
	cbnz	w0, LBB0_3
; %bb.2:
Lloh10:
	adrp	x19, _SMU_SCLK_DPM_STATE_0_PG_CNTL@GOTPAGE
Lloh11:
	ldr	x19, [x19, _SMU_SCLK_DPM_STATE_0_PG_CNTL@GOTPAGEOFF]
	ldr	w8, [x19]
	add	w0, w8, w21
	bl	_RREG32_SMC
Lloh12:
	adrp	x8, _PD_SCLK_DIVIDER_MASK@GOTPAGE
Lloh13:
	ldr	x8, [x8, _PD_SCLK_DIVIDER_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	bic	w20, w0, w8
	ldr	w0, [sp, #8]
	bl	_PD_SCLK_DIVIDER
	orr	w1, w0, w20
	ldr	w8, [x19]
	add	w0, w8, w21
	bl	_WREG32_SMC
LBB0_3:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh10, Lloh11
	.cfi_endproc
                                        ; -- End function
	.comm	_TRINITY_SIZEOF_DPM_STATE_TABLE,4,2 ; @TRINITY_SIZEOF_DPM_STATE_TABLE
	.comm	_COMPUTE_ENGINE_PLL_PARAM,4,2   ; @COMPUTE_ENGINE_PLL_PARAM
	.comm	_SMU_SCLK_DPM_STATE_0_CNTL_0,4,2 ; @SMU_SCLK_DPM_STATE_0_CNTL_0
	.comm	_CLK_DIVIDER_MASK,4,2           ; @CLK_DIVIDER_MASK
	.comm	_SMU_SCLK_DPM_STATE_0_PG_CNTL,4,2 ; @SMU_SCLK_DPM_STATE_0_PG_CNTL
	.comm	_PD_SCLK_DIVIDER_MASK,4,2       ; @PD_SCLK_DIVIDER_MASK
	.no_dead_strip	_trinity_set_divider_value
.subsections_via_symbols
