	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function combios_write_ram_size
_combios_write_ram_size:                ## @combios_write_ram_size
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	(%rdi), %r12
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r12)
	je	LBB0_2
## %bb.1:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	movq	%rdi, %r15
	movq	_COMBIOS_DETECTED_MEM_TABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_combios_get_table_offset
	testq	%rax, %rax
	je	LBB0_8
## %bb.3:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	_RBIOS8
	cmpl	$2, %eax
	jg	LBB0_8
## %bb.4:
	leaq	1(%rbx), %rdi
	callq	_RBIOS32
	movl	%eax, %r13d
	addq	$5, %rbx
	movq	%rbx, %rdi
	callq	_RBIOS16
	movl	%eax, %r14d
	movq	8(%r12), %rax
	movq	_CHIP_R200@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_7
## %bb.5:
	movq	%r12, %rdi
	callq	_ASIC_IS_RN50
	testl	%eax, %eax
	jne	LBB0_7
## %bb.6:
	movq	_RADEON_MEM_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r13d, %esi
	callq	_WREG32
LBB0_7:
	testl	%r14d, %r14d
	jne	LBB0_15
LBB0_8:
	movq	_COMBIOS_MEM_CONFIG_TABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_combios_get_table_offset
	xorl	%r14d, %r14d
	testq	%rax, %rax
	je	LBB0_15
## %bb.9:
	movq	%rax, %rbx
	movq	%rax, %rdi
	decq	%rdi
	callq	_RBIOS8
	testl	%eax, %eax
	jle	LBB0_11
## %bb.10:
	movq	%rbx, %rdi
	callq	_RBIOS8
	movl	%eax, %r14d
	addl	%eax, %r14d
	jmp	LBB0_15
LBB0_11:
	movq	8(%r12), %rax
	movq	_CHIP_R200@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_13
## %bb.12:
	movq	%r12, %rdi
	callq	_ASIC_IS_RN50
	testl	%eax, %eax
	je	LBB0_18
LBB0_13:
	movq	%rbx, %rdi
	callq	_RBIOS8
LBB0_14:
	movl	%eax, %r14d
LBB0_15:
	shll	$20, %r14d
	movq	_RADEON_CONFIG_MEMSIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
LBB0_16:                                ##   in Loop: Header=BB0_18 Depth=1
	movq	%rbx, %rdi
	callq	_RBIOS8
	movl	%eax, %r12d
	incq	%rbx
	movq	%rbx, %rdi
	callq	_RBIOS8
	cmpl	$37, %eax
	setne	%cl
	shll	%cl, %r12d
	movq	%r15, %rdi
	movl	%r12d, %esi
	movl	%eax, %edx
	callq	_combios_detect_ram
	testl	%eax, %eax
	jne	LBB0_14
## %bb.17:                              ##   in Loop: Header=BB0_18 Depth=1
	incq	%rbx
LBB0_18:                                ## =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	callq	_RBIOS8
	testl	%eax, %eax
	jne	LBB0_16
	jmp	LBB0_15
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
	.comm	_COMBIOS_DETECTED_MEM_TABLE,4,2 ## @COMBIOS_DETECTED_MEM_TABLE
	.comm	_CHIP_R200,8,3                  ## @CHIP_R200
	.comm	_RADEON_MEM_CNTL,4,2            ## @RADEON_MEM_CNTL
	.comm	_COMBIOS_MEM_CONFIG_TABLE,4,2   ## @COMBIOS_MEM_CONFIG_TABLE
	.comm	_RADEON_CONFIG_MEMSIZE,4,2      ## @RADEON_CONFIG_MEMSIZE
	.no_dead_strip	_combios_write_ram_size
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function combios_write_ram_size
_combios_write_ram_size:                ; @combios_write_ram_size
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	ldr	x20, [x0]
	ldr	w8, [x20]
Lloh0:
	adrp	x9, _RADEON_IS_IGP@GOTPAGE
Lloh1:
	ldr	x9, [x9, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_2:
	mov	x19, x0
Lloh3:
	adrp	x8, _COMBIOS_DETECTED_MEM_TABLE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _COMBIOS_DETECTED_MEM_TABLE@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	bl	_combios_get_table_offset
	cbz	x0, LBB0_8
; %bb.3:
	mov	x22, x0
	bl	_RBIOS8
	cmp	w0, #2
	b.gt	LBB0_8
; %bb.4:
	add	x0, x22, #1
	bl	_RBIOS32
	mov	x21, x0
	add	x0, x22, #5
	bl	_RBIOS16
	mov	x22, x0
	ldr	x8, [x20, #8]
Lloh6:
	adrp	x9, _CHIP_R200@GOTPAGE
Lloh7:
	ldr	x9, [x9, _CHIP_R200@GOTPAGEOFF]
Lloh8:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_7
; %bb.5:
	mov	x0, x20
	bl	_ASIC_IS_RN50
	cbnz	w0, LBB0_7
; %bb.6:
Lloh9:
	adrp	x8, _RADEON_MEM_CNTL@GOTPAGE
Lloh10:
	ldr	x8, [x8, _RADEON_MEM_CNTL@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	mov	x1, x21
	bl	_WREG32
LBB0_7:
	cbnz	w22, LBB0_18
LBB0_8:
Lloh12:
	adrp	x8, _COMBIOS_MEM_CONFIG_TABLE@GOTPAGE
Lloh13:
	ldr	x8, [x8, _COMBIOS_MEM_CONFIG_TABLE@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_combios_get_table_offset
	cbz	x0, LBB0_17
; %bb.9:
	mov	x21, x0
	sub	x0, x0, #1
	bl	_RBIOS8
	cmp	w0, #0
	b.le	LBB0_11
; %bb.10:
	mov	x0, x21
	bl	_RBIOS8
	lsl	w22, w0, #1
	b	LBB0_18
LBB0_11:
	ldr	x8, [x20, #8]
Lloh15:
	adrp	x9, _CHIP_R200@GOTPAGE
Lloh16:
	ldr	x9, [x9, _CHIP_R200@GOTPAGEOFF]
Lloh17:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_13
; %bb.12:
	mov	x0, x20
	bl	_ASIC_IS_RN50
	cbz	w0, LBB0_14
LBB0_13:
	mov	x0, x21
	bl	_RBIOS8
	mov	x22, x0
	b	LBB0_18
LBB0_14:
	mov	x0, x21
	bl	_RBIOS8
	cbz	w0, LBB0_17
LBB0_15:                                ; =>This Inner Loop Header: Depth=1
	mov	x0, x21
	bl	_RBIOS8
	mov	x22, x0
	add	x20, x21, #1
	mov	x0, x20
	bl	_RBIOS8
	mov	x2, x0
	cmp	w0, #37
	cset	w8, ne
	lsl	w1, w22, w8
	mov	x0, x19
	bl	_combios_detect_ram
	mov	x22, x0
	cbnz	w0, LBB0_18
; %bb.16:                               ;   in Loop: Header=BB0_15 Depth=1
	add	x21, x20, #1
	mov	x0, x21
	bl	_RBIOS8
	cbnz	w0, LBB0_15
	b	LBB0_18
LBB0_17:
	mov	w22, #0
LBB0_18:
	lsl	w1, w22, #20
Lloh18:
	adrp	x8, _RADEON_CONFIG_MEMSIZE@GOTPAGE
Lloh19:
	ldr	x8, [x8, _RADEON_CONFIG_MEMSIZE@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
	.comm	_COMBIOS_DETECTED_MEM_TABLE,4,2 ; @COMBIOS_DETECTED_MEM_TABLE
	.comm	_CHIP_R200,8,3                  ; @CHIP_R200
	.comm	_RADEON_MEM_CNTL,4,2            ; @RADEON_MEM_CNTL
	.comm	_COMBIOS_MEM_CONFIG_TABLE,4,2   ; @COMBIOS_MEM_CONFIG_TABLE
	.comm	_RADEON_CONFIG_MEMSIZE,4,2      ; @RADEON_CONFIG_MEMSIZE
	.no_dead_strip	_combios_write_ram_size
.subsections_via_symbols
