	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_evergreen_rlc_resume           ## -- Begin function evergreen_rlc_resume
	.p2align	4, 0x90
_evergreen_rlc_resume:                  ## @evergreen_rlc_resume
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	cmpq	$0, 16(%rdi)
	je	LBB0_1
## %bb.2:
	movq	%rdi, %rbx
	callq	_r600_rlc_stop
	movq	_RLC_HB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%r15d, %r15d
	xorl	%esi, %esi
	callq	_WREG32
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rbx)
	je	LBB0_9
## %bb.3:
	movq	8(%rbx), %rax
	movq	_CHIP_ARUBA@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_4
## %bb.5:
	movl	32(%rbx), %r14d
	movq	_CC_GC_SHADER_PIPE_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movb	36(%rbx), %cl
	movl	$-1, %edi
	shll	%cl, %edi
	shrl	$16, %eax
	orl	%eax, %edi
	notl	%edi
	callq	_hweight32
	cmpl	36(%rbx), %eax
	jne	LBB0_8
## %bb.6:
	shll	$4, %r14d
	movl	$3, %esi
	movl	%r14d, %ecx
	shll	%cl, %esi
	orl	$3, %esi
	movq	_TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32
	movq	_TN_RLC_LB_PARAMS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$6295556, %esi                  ## imm = 0x601004
	callq	_WREG32
	movq	_TN_RLC_LB_INIT_SIMD_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$-1, %esi
	callq	_WREG32
	movl	$8192, %r15d                    ## imm = 0x2000
	movq	_TN_RLC_LB_CNTR_MAX@GOTPCREL(%rip), %r14
	movq	_TN_RLC_LB_CNTR_INIT@GOTPCREL(%rip), %rax
	jmp	LBB0_7
LBB0_1:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
	jmp	LBB0_22
LBB0_9:
	movq	_RLC_HB_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_RLC_HB_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_RLC_HB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_RLC_HB_WPTR_LSB_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_RLC_HB_WPTR_MSB_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	jmp	LBB0_10
LBB0_4:
	movq	_RLC_HB_WPTR_MSB_ADDR@GOTPCREL(%rip), %r14
	movq	_RLC_HB_WPTR_LSB_ADDR@GOTPCREL(%rip), %rax
LBB0_7:
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r14), %edi
	movl	%r15d, %esi
	callq	_WREG32
LBB0_8:
	movq	_TN_RLC_SAVE_AND_RESTORE_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	24(%rbx), %esi
	sarl	$8, %esi
	callq	_WREG32
	movq	_TN_RLC_CLEAR_STATE_RESTORE_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	28(%rbx), %esi
	sarl	$8, %esi
LBB0_10:
	callq	_WREG32
	movq	_RLC_MC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_RLC_UCODE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	8(%rbx), %rax
	movq	16(%rbx), %rcx
	movq	(%rcx), %r12
	movq	_CHIP_ARUBA@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	movq	%rbx, -48(%rbp)                 ## 8-byte Spill
	jge	LBB0_11
## %bb.14:
	movq	_CHIP_CAYMAN@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_15
## %bb.18:
	movq	_EVERGREEN_RLC_UCODE_SIZE@GOTPCREL(%rip), %r14
	cmpl	$0, (%r14)
	jle	LBB0_21
## %bb.19:
	xorl	%r15d, %r15d
	movq	_RLC_UCODE_DATA@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_20:                                ## =>This Inner Loop Header: Depth=1
	movq	_RLC_UCODE_ADDR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movl	(%r13), %ebx
	movl	%r12d, %edi
	callq	_be32_to_cpup
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	incl	%r15d
	addl	$4, %r12d
	cmpl	(%r14), %r15d
	jl	LBB0_20
	jmp	LBB0_21
LBB0_11:
	movq	_ARUBA_RLC_UCODE_SIZE@GOTPCREL(%rip), %r14
	cmpl	$0, (%r14)
	jle	LBB0_21
## %bb.12:
	xorl	%ebx, %ebx
	movq	_RLC_UCODE_DATA@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_13:                                ## =>This Inner Loop Header: Depth=1
	movq	_RLC_UCODE_ADDR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r13), %r15d
	movl	%r12d, %edi
	callq	_be32_to_cpup
	movl	%r15d, %edi
	movl	%eax, %esi
	callq	_WREG32
	incl	%ebx
	addl	$4, %r12d
	cmpl	(%r14), %ebx
	jl	LBB0_13
	jmp	LBB0_21
LBB0_15:
	movq	_CAYMAN_RLC_UCODE_SIZE@GOTPCREL(%rip), %r14
	cmpl	$0, (%r14)
	jle	LBB0_21
## %bb.16:
	xorl	%r15d, %r15d
	movq	_RLC_UCODE_DATA@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_17:                                ## =>This Inner Loop Header: Depth=1
	movq	_RLC_UCODE_ADDR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movl	(%r13), %ebx
	movl	%r12d, %edi
	callq	_be32_to_cpup
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	incl	%r15d
	addl	$4, %r12d
	cmpl	(%r14), %r15d
	jl	LBB0_17
LBB0_21:
	movq	_RLC_UCODE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%ebx, %ebx
	xorl	%esi, %esi
	callq	_WREG32
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_evergreen_rlc_start
LBB0_22:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_RLC_HB_CNTL,4,2                ## @RLC_HB_CNTL
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
	.comm	_CHIP_ARUBA,8,3                 ## @CHIP_ARUBA
	.comm	_CC_GC_SHADER_PIPE_CONFIG,4,2   ## @CC_GC_SHADER_PIPE_CONFIG
	.comm	_TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK,4,2 ## @TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK
	.comm	_TN_RLC_LB_PARAMS,4,2           ## @TN_RLC_LB_PARAMS
	.comm	_TN_RLC_LB_INIT_SIMD_MASK,4,2   ## @TN_RLC_LB_INIT_SIMD_MASK
	.comm	_TN_RLC_LB_CNTR_INIT,4,2        ## @TN_RLC_LB_CNTR_INIT
	.comm	_TN_RLC_LB_CNTR_MAX,4,2         ## @TN_RLC_LB_CNTR_MAX
	.comm	_RLC_HB_WPTR_LSB_ADDR,4,2       ## @RLC_HB_WPTR_LSB_ADDR
	.comm	_RLC_HB_WPTR_MSB_ADDR,4,2       ## @RLC_HB_WPTR_MSB_ADDR
	.comm	_TN_RLC_SAVE_AND_RESTORE_BASE,4,2 ## @TN_RLC_SAVE_AND_RESTORE_BASE
	.comm	_TN_RLC_CLEAR_STATE_RESTORE_BASE,4,2 ## @TN_RLC_CLEAR_STATE_RESTORE_BASE
	.comm	_RLC_HB_BASE,4,2                ## @RLC_HB_BASE
	.comm	_RLC_HB_RPTR,4,2                ## @RLC_HB_RPTR
	.comm	_RLC_HB_WPTR,4,2                ## @RLC_HB_WPTR
	.comm	_RLC_MC_CNTL,4,2                ## @RLC_MC_CNTL
	.comm	_RLC_UCODE_CNTL,4,2             ## @RLC_UCODE_CNTL
	.comm	_ARUBA_RLC_UCODE_SIZE,4,2       ## @ARUBA_RLC_UCODE_SIZE
	.comm	_RLC_UCODE_ADDR,4,2             ## @RLC_UCODE_ADDR
	.comm	_RLC_UCODE_DATA,4,2             ## @RLC_UCODE_DATA
	.comm	_CHIP_CAYMAN,8,3                ## @CHIP_CAYMAN
	.comm	_CAYMAN_RLC_UCODE_SIZE,4,2      ## @CAYMAN_RLC_UCODE_SIZE
	.comm	_EVERGREEN_RLC_UCODE_SIZE,4,2   ## @EVERGREEN_RLC_UCODE_SIZE
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_evergreen_rlc_resume           ; -- Begin function evergreen_rlc_resume
	.p2align	2
_evergreen_rlc_resume:                  ; @evergreen_rlc_resume
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	ldr	x8, [x0, #16]
	cbz	x8, LBB0_5
; %bb.1:
	mov	x19, x0
	bl	_r600_rlc_stop
Lloh0:
	adrp	x8, _RLC_HB_CNTL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RLC_HB_CNTL@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	ldr	w8, [x19]
Lloh3:
	adrp	x9, _RADEON_IS_IGP@GOTPAGE
Lloh4:
	ldr	x9, [x9, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
Lloh6:
	adrp	x21, _CHIP_ARUBA@GOTPAGE
Lloh7:
	ldr	x21, [x21, _CHIP_ARUBA@GOTPAGEOFF]
	tst	w9, w8
	b.eq	LBB0_6
; %bb.2:
	ldr	x8, [x19, #8]
	ldr	x9, [x21]
	cmp	x8, x9
	b.ne	LBB0_7
; %bb.3:
	ldr	w20, [x19, #32]
Lloh8:
	adrp	x8, _CC_GC_SHADER_PIPE_CONFIG@GOTPAGE
Lloh9:
	ldr	x8, [x8, _CC_GC_SHADER_PIPE_CONFIG@GOTPAGEOFF]
Lloh10:
	ldr	w0, [x8]
	bl	_RREG32
	ldr	w8, [x19, #36]
	mov	w9, #-1
	lsl	w8, w9, w8
	orr	w8, w8, w0, lsr #16
	mvn	w0, w8
	bl	_hweight32
	ldr	w8, [x19, #36]
	cmp	w0, w8
	b.ne	LBB0_9
; %bb.4:
	lsl	w8, w20, #4
	mov	w9, #3
	lsl	w8, w9, w8
	orr	w1, w8, #0x3
Lloh11:
	adrp	x8, _TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK@GOTPAGE
Lloh12:
	ldr	x8, [x8, _TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
	bl	_WREG32
Lloh14:
	adrp	x8, _TN_RLC_LB_PARAMS@GOTPAGE
Lloh15:
	ldr	x8, [x8, _TN_RLC_LB_PARAMS@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
	mov	w1, #4100
	movk	w1, #96, lsl #16
	bl	_WREG32
Lloh17:
	adrp	x8, _TN_RLC_LB_INIT_SIMD_MASK@GOTPAGE
Lloh18:
	ldr	x8, [x8, _TN_RLC_LB_INIT_SIMD_MASK@GOTPAGEOFF]
Lloh19:
	ldr	w0, [x8]
	mov	w1, #-1
	bl	_WREG32
	mov	w20, #8192
Lloh20:
	adrp	x22, _TN_RLC_LB_CNTR_MAX@GOTPAGE
Lloh21:
	ldr	x22, [x22, _TN_RLC_LB_CNTR_MAX@GOTPAGEOFF]
Lloh22:
	adrp	x8, _TN_RLC_LB_CNTR_INIT@GOTPAGE
Lloh23:
	ldr	x8, [x8, _TN_RLC_LB_CNTR_INIT@GOTPAGEOFF]
	b	LBB0_8
LBB0_5:
Lloh24:
	adrp	x8, _EINVAL@GOTPAGE
Lloh25:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_22
LBB0_6:
Lloh27:
	adrp	x8, _RLC_HB_BASE@GOTPAGE
Lloh28:
	ldr	x8, [x8, _RLC_HB_BASE@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh30:
	adrp	x8, _RLC_HB_RPTR@GOTPAGE
Lloh31:
	ldr	x8, [x8, _RLC_HB_RPTR@GOTPAGEOFF]
Lloh32:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh33:
	adrp	x8, _RLC_HB_WPTR@GOTPAGE
Lloh34:
	ldr	x8, [x8, _RLC_HB_WPTR@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh36:
	adrp	x8, _RLC_HB_WPTR_LSB_ADDR@GOTPAGE
Lloh37:
	ldr	x8, [x8, _RLC_HB_WPTR_LSB_ADDR@GOTPAGEOFF]
Lloh38:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh39:
	adrp	x8, _RLC_HB_WPTR_MSB_ADDR@GOTPAGE
Lloh40:
	ldr	x8, [x8, _RLC_HB_WPTR_MSB_ADDR@GOTPAGEOFF]
Lloh41:
	ldr	w0, [x8]
	mov	w1, #0
	b	LBB0_10
LBB0_7:
	mov	w20, #0
Lloh42:
	adrp	x22, _RLC_HB_WPTR_MSB_ADDR@GOTPAGE
Lloh43:
	ldr	x22, [x22, _RLC_HB_WPTR_MSB_ADDR@GOTPAGEOFF]
Lloh44:
	adrp	x8, _RLC_HB_WPTR_LSB_ADDR@GOTPAGE
Lloh45:
	ldr	x8, [x8, _RLC_HB_WPTR_LSB_ADDR@GOTPAGEOFF]
LBB0_8:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x22]
	mov	x1, x20
	bl	_WREG32
LBB0_9:
Lloh46:
	adrp	x8, _TN_RLC_SAVE_AND_RESTORE_BASE@GOTPAGE
Lloh47:
	ldr	x8, [x8, _TN_RLC_SAVE_AND_RESTORE_BASE@GOTPAGEOFF]
Lloh48:
	ldr	w0, [x8]
	ldr	w8, [x19, #24]
	asr	w1, w8, #8
	bl	_WREG32
Lloh49:
	adrp	x8, _TN_RLC_CLEAR_STATE_RESTORE_BASE@GOTPAGE
Lloh50:
	ldr	x8, [x8, _TN_RLC_CLEAR_STATE_RESTORE_BASE@GOTPAGEOFF]
Lloh51:
	ldr	w0, [x8]
	ldr	w8, [x19, #28]
	asr	w1, w8, #8
LBB0_10:
	bl	_WREG32
Lloh52:
	adrp	x8, _RLC_MC_CNTL@GOTPAGE
Lloh53:
	ldr	x8, [x8, _RLC_MC_CNTL@GOTPAGEOFF]
Lloh54:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh55:
	adrp	x8, _RLC_UCODE_CNTL@GOTPAGE
Lloh56:
	ldr	x8, [x8, _RLC_UCODE_CNTL@GOTPAGEOFF]
Lloh57:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	ldp	x8, x9, [x19, #8]
	ldr	x20, [x9]
	ldr	x9, [x21]
Lloh58:
	adrp	x23, _RLC_UCODE_ADDR@GOTPAGE
Lloh59:
	ldr	x23, [x23, _RLC_UCODE_ADDR@GOTPAGEOFF]
	cmp	x8, x9
	b.ge	LBB0_15
; %bb.11:
Lloh60:
	adrp	x9, _CHIP_CAYMAN@GOTPAGE
Lloh61:
	ldr	x9, [x9, _CHIP_CAYMAN@GOTPAGEOFF]
Lloh62:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_18
; %bb.12:
Lloh63:
	adrp	x24, _EVERGREEN_RLC_UCODE_SIZE@GOTPAGE
Lloh64:
	ldr	x24, [x24, _EVERGREEN_RLC_UCODE_SIZE@GOTPAGEOFF]
	ldr	w8, [x24]
	cmp	w8, #1
	b.lt	LBB0_21
; %bb.13:
	mov	w21, #0
Lloh65:
	adrp	x25, _RLC_UCODE_DATA@GOTPAGE
Lloh66:
	ldr	x25, [x25, _RLC_UCODE_DATA@GOTPAGEOFF]
LBB0_14:                                ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x23]
	mov	x1, x21
	bl	_WREG32
	ldr	w22, [x25]
	mov	x0, x20
	bl	_be32_to_cpup
	mov	x1, x0
	mov	x0, x22
	bl	_WREG32
	add	w21, w21, #1
	ldr	w8, [x24]
	add	w20, w20, #4
	cmp	w21, w8
	b.lt	LBB0_14
	b	LBB0_21
LBB0_15:
Lloh67:
	adrp	x24, _ARUBA_RLC_UCODE_SIZE@GOTPAGE
Lloh68:
	ldr	x24, [x24, _ARUBA_RLC_UCODE_SIZE@GOTPAGEOFF]
	ldr	w8, [x24]
	cmp	w8, #1
	b.lt	LBB0_21
; %bb.16:
	mov	w21, #0
Lloh69:
	adrp	x25, _RLC_UCODE_DATA@GOTPAGE
Lloh70:
	ldr	x25, [x25, _RLC_UCODE_DATA@GOTPAGEOFF]
LBB0_17:                                ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x23]
	mov	x1, x21
	bl	_WREG32
	ldr	w22, [x25]
	mov	x0, x20
	bl	_be32_to_cpup
	mov	x1, x0
	mov	x0, x22
	bl	_WREG32
	add	w21, w21, #1
	ldr	w8, [x24]
	add	w20, w20, #4
	cmp	w21, w8
	b.lt	LBB0_17
	b	LBB0_21
LBB0_18:
Lloh71:
	adrp	x24, _CAYMAN_RLC_UCODE_SIZE@GOTPAGE
Lloh72:
	ldr	x24, [x24, _CAYMAN_RLC_UCODE_SIZE@GOTPAGEOFF]
	ldr	w8, [x24]
	cmp	w8, #1
	b.lt	LBB0_21
; %bb.19:
	mov	w21, #0
Lloh73:
	adrp	x25, _RLC_UCODE_DATA@GOTPAGE
Lloh74:
	ldr	x25, [x25, _RLC_UCODE_DATA@GOTPAGEOFF]
LBB0_20:                                ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x23]
	mov	x1, x21
	bl	_WREG32
	ldr	w22, [x25]
	mov	x0, x20
	bl	_be32_to_cpup
	mov	x1, x0
	mov	x0, x22
	bl	_WREG32
	add	w21, w21, #1
	ldr	w8, [x24]
	add	w20, w20, #4
	cmp	w21, w8
	b.lt	LBB0_20
LBB0_21:
	ldr	w0, [x23]
	mov	w1, #0
	bl	_WREG32
	mov	x0, x19
	bl	_evergreen_rlc_start
	mov	w0, #0
LBB0_22:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGot	Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGot	Lloh67, Lloh68
	.loh AdrpLdrGot	Lloh69, Lloh70
	.loh AdrpLdrGot	Lloh71, Lloh72
	.loh AdrpLdrGot	Lloh73, Lloh74
	.cfi_endproc
                                        ; -- End function
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_RLC_HB_CNTL,4,2                ; @RLC_HB_CNTL
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
	.comm	_CHIP_ARUBA,8,3                 ; @CHIP_ARUBA
	.comm	_CC_GC_SHADER_PIPE_CONFIG,4,2   ; @CC_GC_SHADER_PIPE_CONFIG
	.comm	_TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK,4,2 ; @TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK
	.comm	_TN_RLC_LB_PARAMS,4,2           ; @TN_RLC_LB_PARAMS
	.comm	_TN_RLC_LB_INIT_SIMD_MASK,4,2   ; @TN_RLC_LB_INIT_SIMD_MASK
	.comm	_TN_RLC_LB_CNTR_INIT,4,2        ; @TN_RLC_LB_CNTR_INIT
	.comm	_TN_RLC_LB_CNTR_MAX,4,2         ; @TN_RLC_LB_CNTR_MAX
	.comm	_RLC_HB_WPTR_LSB_ADDR,4,2       ; @RLC_HB_WPTR_LSB_ADDR
	.comm	_RLC_HB_WPTR_MSB_ADDR,4,2       ; @RLC_HB_WPTR_MSB_ADDR
	.comm	_TN_RLC_SAVE_AND_RESTORE_BASE,4,2 ; @TN_RLC_SAVE_AND_RESTORE_BASE
	.comm	_TN_RLC_CLEAR_STATE_RESTORE_BASE,4,2 ; @TN_RLC_CLEAR_STATE_RESTORE_BASE
	.comm	_RLC_HB_BASE,4,2                ; @RLC_HB_BASE
	.comm	_RLC_HB_RPTR,4,2                ; @RLC_HB_RPTR
	.comm	_RLC_HB_WPTR,4,2                ; @RLC_HB_WPTR
	.comm	_RLC_MC_CNTL,4,2                ; @RLC_MC_CNTL
	.comm	_RLC_UCODE_CNTL,4,2             ; @RLC_UCODE_CNTL
	.comm	_ARUBA_RLC_UCODE_SIZE,4,2       ; @ARUBA_RLC_UCODE_SIZE
	.comm	_RLC_UCODE_ADDR,4,2             ; @RLC_UCODE_ADDR
	.comm	_RLC_UCODE_DATA,4,2             ; @RLC_UCODE_DATA
	.comm	_CHIP_CAYMAN,8,3                ; @CHIP_CAYMAN
	.comm	_CAYMAN_RLC_UCODE_SIZE,4,2      ; @CAYMAN_RLC_UCODE_SIZE
	.comm	_EVERGREEN_RLC_UCODE_SIZE,4,2   ; @EVERGREEN_RLC_UCODE_SIZE
.subsections_via_symbols
