	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function si_ih_irq_init
_si_ih_irq_init:                        ## @si_ih_irq_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	callq	_si_ih_disable_interrupts
	movq	_INTERRUPT_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	16(%r14), %esi
	sarl	$8, %esi
	callq	_WREG32
	movq	_INTERRUPT_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_IH_DUMMY_RD_OVERRIDE@GOTPCREL(%rip), %rcx
	movq	_IH_REQ_NONSNOOP_EN@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32
	movq	_IH_RB_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	16(%r14), %esi
	sarl	$8, %esi
	callq	_WREG32
	movl	20(%r14), %eax
	leal	3(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$2, %edi
	callq	_order_base_2
                                        ## kill: def $eax killed $eax def $rax
	movq	_IH_WPTR_OVERFLOW_ENABLE@GOTPCREL(%rip), %rcx
	movq	_IH_WPTR_OVERFLOW_CLEAR@GOTPCREL(%rip), %rdx
	leal	(%rax,%rax), %ebx
	movq	_IH_WPTR_WRITEBACK_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rcx), %ebx
	orl	(%rdx), %ebx
	orl	(%rax), %ebx
	movq	_IH_RB_WPTR_ADDR_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	24(%r14), %edi
	callq	_lower_32_bits
	movl	%r15d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_IH_RB_WPTR_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	24(%r14), %edi
	callq	_upper_32_bits
	movzbl	%al, %esi
	movl	%r15d, %edi
	callq	_WREG32
	movq	_IH_RB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_IH_RB_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_IH_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	$16, %edi
	callq	_MC_WRREQ_CREDIT
	movl	%eax, %r15d
	movl	$16, %edi
	callq	_MC_WR_CLEAN_CNT
	movl	%eax, %ebx
	orl	%r15d, %ebx
	xorl	%edi, %edi
	callq	_MC_VMID
	orl	%ebx, %eax
	cmpq	$0, 8(%r14)
	movl	$0, %ecx
	je	LBB0_2
## %bb.1:
	movq	_RPTR_REARM@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_2:
	orl	%ecx, %eax
	movq	_IH_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movl	(%r14), %edi
	callq	_pci_set_master
	movq	%r14, %rdi
	callq	_si_ih_enable_interrupts
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_INTERRUPT_CNTL2,4,2            ## @INTERRUPT_CNTL2
	.comm	_INTERRUPT_CNTL,4,2             ## @INTERRUPT_CNTL
	.comm	_IH_DUMMY_RD_OVERRIDE,4,2       ## @IH_DUMMY_RD_OVERRIDE
	.comm	_IH_REQ_NONSNOOP_EN,4,2         ## @IH_REQ_NONSNOOP_EN
	.comm	_IH_RB_BASE,4,2                 ## @IH_RB_BASE
	.comm	_IH_WPTR_OVERFLOW_ENABLE,4,2    ## @IH_WPTR_OVERFLOW_ENABLE
	.comm	_IH_WPTR_OVERFLOW_CLEAR,4,2     ## @IH_WPTR_OVERFLOW_CLEAR
	.comm	_IH_WPTR_WRITEBACK_ENABLE,4,2   ## @IH_WPTR_WRITEBACK_ENABLE
	.comm	_IH_RB_WPTR_ADDR_LO,4,2         ## @IH_RB_WPTR_ADDR_LO
	.comm	_IH_RB_WPTR_ADDR_HI,4,2         ## @IH_RB_WPTR_ADDR_HI
	.comm	_IH_RB_CNTL,4,2                 ## @IH_RB_CNTL
	.comm	_IH_RB_RPTR,4,2                 ## @IH_RB_RPTR
	.comm	_IH_RB_WPTR,4,2                 ## @IH_RB_WPTR
	.comm	_RPTR_REARM,4,2                 ## @RPTR_REARM
	.comm	_IH_CNTL,4,2                    ## @IH_CNTL
	.no_dead_strip	_si_ih_irq_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function si_ih_irq_init
_si_ih_irq_init:                        ; @si_ih_irq_init
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	bl	_si_ih_disable_interrupts
Lloh0:
	adrp	x8, _INTERRUPT_CNTL2@GOTPAGE
Lloh1:
	ldr	x8, [x8, _INTERRUPT_CNTL2@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	ldr	w8, [x19, #16]
	asr	w1, w8, #8
	bl	_WREG32
Lloh3:
	adrp	x20, _INTERRUPT_CNTL@GOTPAGE
Lloh4:
	ldr	x20, [x20, _INTERRUPT_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh5:
	adrp	x8, _IH_DUMMY_RD_OVERRIDE@GOTPAGE
Lloh6:
	ldr	x8, [x8, _IH_DUMMY_RD_OVERRIDE@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
Lloh8:
	adrp	x9, _IH_REQ_NONSNOOP_EN@GOTPAGE
Lloh9:
	ldr	x9, [x9, _IH_REQ_NONSNOOP_EN@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32
Lloh11:
	adrp	x8, _IH_RB_BASE@GOTPAGE
Lloh12:
	ldr	x8, [x8, _IH_RB_BASE@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
	ldr	w8, [x19, #16]
	asr	w1, w8, #8
	bl	_WREG32
	ldr	w8, [x19, #20]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #2
	bl	_order_base_2
Lloh14:
	adrp	x8, _IH_WPTR_OVERFLOW_ENABLE@GOTPAGE
Lloh15:
	ldr	x8, [x8, _IH_WPTR_OVERFLOW_ENABLE@GOTPAGEOFF]
Lloh16:
	adrp	x9, _IH_WPTR_OVERFLOW_CLEAR@GOTPAGE
Lloh17:
	ldr	x9, [x9, _IH_WPTR_OVERFLOW_CLEAR@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
Lloh19:
	ldr	w9, [x9]
Lloh20:
	adrp	x10, _IH_WPTR_WRITEBACK_ENABLE@GOTPAGE
Lloh21:
	ldr	x10, [x10, _IH_WPTR_WRITEBACK_ENABLE@GOTPAGEOFF]
Lloh22:
	ldr	w10, [x10]
	orr	w8, w8, w0, lsl #1
	orr	w8, w8, w9
	orr	w20, w8, w10
Lloh23:
	adrp	x8, _IH_RB_WPTR_ADDR_LO@GOTPAGE
Lloh24:
	ldr	x8, [x8, _IH_RB_WPTR_ADDR_LO@GOTPAGEOFF]
Lloh25:
	ldr	w21, [x8]
	ldr	w0, [x19, #24]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x21
	bl	_WREG32
Lloh26:
	adrp	x8, _IH_RB_WPTR_ADDR_HI@GOTPAGE
Lloh27:
	ldr	x8, [x8, _IH_RB_WPTR_ADDR_HI@GOTPAGEOFF]
Lloh28:
	ldr	w21, [x8]
	ldr	w0, [x19, #24]
	bl	_upper_32_bits
	and	w1, w0, #0xff
	mov	x0, x21
	bl	_WREG32
Lloh29:
	adrp	x8, _IH_RB_CNTL@GOTPAGE
Lloh30:
	ldr	x8, [x8, _IH_RB_CNTL@GOTPAGEOFF]
Lloh31:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh32:
	adrp	x8, _IH_RB_RPTR@GOTPAGE
Lloh33:
	ldr	x8, [x8, _IH_RB_RPTR@GOTPAGEOFF]
Lloh34:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh35:
	adrp	x8, _IH_RB_WPTR@GOTPAGE
Lloh36:
	ldr	x8, [x8, _IH_RB_WPTR@GOTPAGEOFF]
Lloh37:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	mov	w0, #16
	bl	_MC_WRREQ_CREDIT
	mov	x20, x0
	mov	w0, #16
	bl	_MC_WR_CLEAN_CNT
	orr	w20, w0, w20
	mov	w0, #0
	bl	_MC_VMID
	orr	w8, w20, w0
	ldr	x9, [x19, #8]
Lloh38:
	adrp	x10, _RPTR_REARM@GOTPAGE
Lloh39:
	ldr	x10, [x10, _RPTR_REARM@GOTPAGEOFF]
Lloh40:
	ldr	w10, [x10]
	cmp	x9, #0
	csel	w9, wzr, w10, eq
	orr	w1, w8, w9
Lloh41:
	adrp	x8, _IH_CNTL@GOTPAGE
Lloh42:
	ldr	x8, [x8, _IH_CNTL@GOTPAGEOFF]
Lloh43:
	ldr	w0, [x8]
	bl	_WREG32
	ldr	w0, [x19]
	bl	_pci_set_master
	mov	x0, x19
	bl	_si_ih_enable_interrupts
	mov	w0, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh18
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_INTERRUPT_CNTL2,4,2            ; @INTERRUPT_CNTL2
	.comm	_INTERRUPT_CNTL,4,2             ; @INTERRUPT_CNTL
	.comm	_IH_DUMMY_RD_OVERRIDE,4,2       ; @IH_DUMMY_RD_OVERRIDE
	.comm	_IH_REQ_NONSNOOP_EN,4,2         ; @IH_REQ_NONSNOOP_EN
	.comm	_IH_RB_BASE,4,2                 ; @IH_RB_BASE
	.comm	_IH_WPTR_OVERFLOW_ENABLE,4,2    ; @IH_WPTR_OVERFLOW_ENABLE
	.comm	_IH_WPTR_OVERFLOW_CLEAR,4,2     ; @IH_WPTR_OVERFLOW_CLEAR
	.comm	_IH_WPTR_WRITEBACK_ENABLE,4,2   ; @IH_WPTR_WRITEBACK_ENABLE
	.comm	_IH_RB_WPTR_ADDR_LO,4,2         ; @IH_RB_WPTR_ADDR_LO
	.comm	_IH_RB_WPTR_ADDR_HI,4,2         ; @IH_RB_WPTR_ADDR_HI
	.comm	_IH_RB_CNTL,4,2                 ; @IH_RB_CNTL
	.comm	_IH_RB_RPTR,4,2                 ; @IH_RB_RPTR
	.comm	_IH_RB_WPTR,4,2                 ; @IH_RB_WPTR
	.comm	_RPTR_REARM,4,2                 ; @RPTR_REARM
	.comm	_IH_CNTL,4,2                    ; @IH_CNTL
	.no_dead_strip	_si_ih_irq_init
.subsections_via_symbols
