	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vc4_dsi_encoder_enable
_vc4_dsi_encoder_enable:                ## @vc4_dsi_encoder_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	(%rdi), %rax
	movq	(%rax), %r15
	callq	_to_vc4_dsi_encoder
	movq	(%rax), %r12
	movq	32(%r12), %rbx
	movl	$60, %edi
	callq	_dsi_esc_timing
	movl	%eax, %r14d
	movslq	(%r15), %r15
	movq	%rbx, %rdi
	callq	_pm_runtime_get_sync
	testl	%eax, %eax
	je	LBB0_2
## %bb.1:
	movl	(%r12), %esi
	leaq	L_.str(%rip), %rdi
	jmp	LBB0_20
LBB0_2:
	movq	%rbx, -48(%rbp)                 ## 8-byte Spill
	movq	%r14, -56(%rbp)                 ## 8-byte Spill
	imulq	$1000, %r15, %r13               ## imm = 0x3E8
	addq	$1000, %r13                     ## imm = 0x3E8
	imulq	8(%r12), %r13
	movl	48(%r12), %edi
	movq	%r13, %rsi
	callq	_clk_set_rate
	testl	%eax, %eax
	je	LBB0_4
## %bb.3:
	movq	32(%r12), %rdi
	leaq	L_.str.2(%rip), %rsi
	movq	%r13, %rdx
	movl	%eax, %ecx
	callq	_dev_err
LBB0_4:
	movq	_CTRL@GOTPCREL(%rip), %r15
	movl	(%r15), %r14d
	movq	_DSI_CTRL_SOFT_RESET_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_CTRL_RESET_FIFOS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_DSI_PORT_BIT
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_DSI_PORT_WRITE
	movl	(%r15), %edi
	movq	_DSI_CTRL_HSDT_EOT_DISABLE@GOTPCREL(%rip), %rax
	movq	_DSI_CTRL_RX_LPDT_EOT_DISABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	callq	_DSI_PORT_WRITE
	movq	_STAT@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%ebx, %edi
	callq	_DSI_PORT_READ
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_DSI_PORT_WRITE
	movq	%r12, %r15
	movl	(%r12), %r12d
	movq	_DSI_PHY_AFEC0_PTATADJ@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$7, %edi
	callq	_VC4_SET_FIELD
	movl	%eax, %r14d
	movq	_DSI_PHY_AFEC0_CTATADJ@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$7, %edi
	callq	_VC4_SET_FIELD
	movl	%eax, %ebx
	orl	%r14d, %ebx
	testl	%r12d, %r12d
	je	LBB0_5
## %bb.10:
	movq	_DSI1_PHY_AFEC0_IDR_CLANE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$6, %edi
	callq	_VC4_SET_FIELD
	orl	%eax, %ebx
	movq	_DSI1_PHY_AFEC0_IDR_DLANE0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$6, %edi
	callq	_VC4_SET_FIELD
	movl	%eax, %r14d
	movq	_DSI1_PHY_AFEC0_IDR_DLANE1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$6, %edi
	callq	_VC4_SET_FIELD
	movl	%eax, %r12d
	orl	%r14d, %r12d
	movq	_DSI1_PHY_AFEC0_IDR_DLANE2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$6, %edi
	callq	_VC4_SET_FIELD
	movl	%eax, %r14d
	orl	%r12d, %r14d
	orl	%ebx, %r14d
	movq	_DSI1_PHY_AFEC0_IDR_DLANE3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$6, %edi
	callq	_VC4_SET_FIELD
	movl	16(%r15), %ecx
	movl	$0, %edx
	cmpl	$4, %ecx
	movq	%r15, %r12
	jge	LBB0_12
## %bb.11:
	movq	_DSI1_PHY_AFEC0_PD_DLANE3@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
LBB0_12:
	orl	%eax, %r14d
	movl	$0, %eax
	cmpl	$3, %ecx
	jge	LBB0_14
## %bb.13:
	movq	_DSI1_PHY_AFEC0_PD_DLANE2@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_14:
	orl	%edx, %r14d
	movl	$0, %edx
	cmpl	$2, %ecx
	jge	LBB0_16
## %bb.15:
	movq	_DSI1_PHY_AFEC0_PD_DLANE1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
LBB0_16:
	orl	%edx, %eax
	orl	%eax, %r14d
	movq	_DSI1_PHY_AFEC0_RESET@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
	movq	_PHY_AFEC0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_DSI_PORT_WRITE
	movq	_PHY_AFEC1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_DSI_PORT_WRITE
	movl	$1, %edi
	callq	_mdelay
	jmp	LBB0_17
LBB0_5:
	xorl	%eax, %eax
	cmpl	$2, 16(%r15)
	movl	$0, %ecx
	movq	%r15, %r12
	jge	LBB0_7
## %bb.6:
	movq	_DSI0_PHY_AFEC0_PD_DLANE1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_7:
	orl	%ecx, %ebx
	movq	_MIPI_DSI_MODE_VIDEO@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	20(%r12), %ecx
	jne	LBB0_9
## %bb.8:
	movq	_DSI0_PHY_AFEC0_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_9:
	orl	%eax, %ebx
	movq	_PHY_AFEC0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_DSI_PORT_WRITE
	movq	_PHY_AFEC1@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_DSI0_PHY_AFEC1_IDR_DLANE1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$6, %edi
	callq	_VC4_SET_FIELD
	movl	%eax, %ebx
	movq	_DSI0_PHY_AFEC1_IDR_DLANE0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$6, %edi
	callq	_VC4_SET_FIELD
	orl	%eax, %ebx
	movq	_DSI0_PHY_AFEC1_IDR_CLANE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$6, %edi
	callq	_VC4_SET_FIELD
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_DSI_PORT_WRITE
LBB0_17:
	movl	52(%r12), %edi
	callq	_clk_prepare_enable
	testl	%eax, %eax
	je	LBB0_21
## %bb.18:
	leaq	L_.str.3(%rip), %rdi
	jmp	LBB0_19
LBB0_21:
	movl	48(%r12), %edi
	callq	_clk_prepare_enable
	testl	%eax, %eax
	je	LBB0_23
## %bb.22:
	leaq	L_.str.4(%rip), %rdi
	jmp	LBB0_19
LBB0_23:
	movl	48(%r12), %edi
	callq	_clk_get_rate
	movq	%rax, %rbx
	shrq	$3, %r13
	movl	44(%r12), %edi
	movq	%r13, %rsi
	callq	_clk_set_rate
	testl	%eax, %eax
	je	LBB0_25
## %bb.24:
	leaq	L_.str.5(%rip), %rsi
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movq	%r13, %rdx
	movl	%eax, %ecx
	callq	_dev_err
LBB0_25:
	movl	44(%r12), %edi
	callq	_clk_prepare_enable
	testl	%eax, %eax
	je	LBB0_27
## %bb.26:
	leaq	L_.str.6(%rip), %rdi
LBB0_19:
	movl	%eax, %esi
LBB0_20:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_DRM_ERROR                      ## TAILCALL
LBB0_27:
	movl	$500000000, %edi                ## imm = 0x1DCD6500
	movq	%rbx, %rsi
	callq	_DIV_ROUND_UP
	movl	%eax, %r15d
	movq	_HS_CLT0@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%r15d, %edi
	movl	$262, %esi                      ## imm = 0x106
	xorl	%edx, %edx
	callq	_dsi_hs_timing
	movq	_DSI_HS_CLT0_CZERO@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_VC4_SET_FIELD
	movl	%eax, %ebx
	movl	%r15d, %edi
	xorl	%esi, %esi
	movl	$8, %edx
	callq	_dsi_hs_timing
	movq	_DSI_HS_CLT0_CPRE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_VC4_SET_FIELD
	orl	%eax, %ebx
	movl	%r15d, %edi
	movl	$38, %esi
	xorl	%edx, %edx
	callq	_dsi_hs_timing
	movq	_DSI_HS_CLT0_CPREP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_VC4_SET_FIELD
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_DSI_PORT_WRITE
	movq	_HS_CLT1@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%r15d, %edi
	movl	$60, %esi
	xorl	%edx, %edx
	callq	_dsi_hs_timing
	movq	_DSI_HS_CLT1_CTRAIL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_VC4_SET_FIELD
	movl	%eax, %ebx
	movl	%r15d, %edi
	movl	$60, %esi
	movl	$52, %edx
	callq	_dsi_hs_timing
	movq	_DSI_HS_CLT1_CPOST@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_VC4_SET_FIELD
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_DSI_PORT_WRITE
	movq	_HS_CLT2@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%r15d, %edi
	movl	$1000000, %esi                  ## imm = 0xF4240
	xorl	%edx, %edx
	callq	_dsi_hs_timing
	movq	_DSI_HS_CLT2_WUP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_VC4_SET_FIELD
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_DSI_PORT_WRITE
	movq	_HS_DLT3@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%r15d, %edi
	movl	$100, %esi
	xorl	%edx, %edx
	callq	_dsi_hs_timing
	movq	_DSI_HS_DLT3_EXIT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_VC4_SET_FIELD
	movl	%eax, %ebx
	movl	%r15d, %edi
	movl	$105, %esi
	movl	$6, %edx
	callq	_dsi_hs_timing
	movq	_DSI_HS_DLT3_ZERO@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_VC4_SET_FIELD
	orl	%eax, %ebx
	movl	%r15d, %edi
	movl	$40, %esi
	movl	$4, %edx
	callq	_dsi_hs_timing
	movq	_DSI_HS_DLT3_PRE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_VC4_SET_FIELD
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_DSI_PORT_WRITE
	movq	_HS_DLT4@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_ESC_TIME_NS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	-56(%rbp), %r13                 ## 8-byte Reload
	imull	%r13d, %esi
	movl	%r15d, %edi
	xorl	%edx, %edx
	callq	_dsi_hs_timing
	movq	_DSI_HS_DLT4_LPX@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_VC4_SET_FIELD
	movl	%eax, %ebx
	movl	%r15d, %edi
	xorl	%esi, %esi
	movl	$8, %edx
	callq	_dsi_hs_timing
	movl	%eax, %r14d
	movl	%r15d, %edi
	movl	$60, %esi
	movl	$4, %edx
	callq	_dsi_hs_timing
	movl	%r14d, %edi
	movl	%eax, %esi
	callq	_max
	movq	_DSI_HS_DLT4_TRAIL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_VC4_SET_FIELD
	movl	%eax, %r14d
	movq	_DSI_HS_DLT4_ANLAT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edi, %edi
	callq	_VC4_SET_FIELD
	orl	%eax, %ebx
	orl	%r14d, %ebx
	movl	-48(%rbp), %edi                 ## 4-byte Reload
	movl	%ebx, %esi
	callq	_DSI_PORT_WRITE
	movq	_HS_DLT5@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%r15d, %edi
	movl	$5000000, %esi                  ## imm = 0x4C4B40
	xorl	%edx, %edx
	callq	_dsi_hs_timing
	movq	_DSI_HS_DLT5_INIT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_VC4_SET_FIELD
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_DSI_PORT_WRITE
	movq	_HS_DLT6@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	leal	(%r13,%r13,4), %edi
	movq	_DSI_HS_DLT6_TA_GET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_VC4_SET_FIELD
	movl	%eax, %r15d
	movq	_DSI_HS_DLT6_TA_SURE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r13d, %edi
	callq	_VC4_SET_FIELD
	orl	%eax, %r15d
	leal	(,%r13,4), %edi
	movq	_DSI_HS_DLT6_TA_GO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_VC4_SET_FIELD
	movl	%eax, %ebx
	movq	_DSI_HS_DLT6_LP_LPX@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r13d, %edi
	callq	_VC4_SET_FIELD
	orl	%eax, %ebx
	orl	%r15d, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_DSI_PORT_WRITE
	movq	_HS_DLT7@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$1000000, %edi                  ## imm = 0xF4240
	callq	_dsi_esc_timing
	movq	_DSI_HS_DLT7_LP_WUP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_VC4_SET_FIELD
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_DSI_PORT_WRITE
	movl	16(%r12), %eax
	movl	$0, %r15d
	cmpl	$2, %eax
	jl	LBB0_29
## %bb.28:
	movq	_DSI_PHYC_DLANE1_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r15d
LBB0_29:
	movq	_DSI_PHYC_DLANE0_ENABLE@GOTPCREL(%rip), %rsi
	movl	$0, %ecx
	cmpl	$3, %eax
	jl	LBB0_31
## %bb.30:
	movq	_DSI_PHYC_DLANE2_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_31:
	movq	_PHYC@GOTPCREL(%rip), %rdx
	orl	(%rsi), %r15d
	movl	$0, %esi
	cmpl	$4, %eax
	jl	LBB0_33
## %bb.32:
	movq	_DSI_PHYC_DLANE3_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
LBB0_33:
	orl	%esi, %ecx
	orl	%ecx, %r15d
	movl	(%rdx), %r14d
	movq	_PHYC_CLANE_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_DSI_PORT_BIT
	movl	%eax, %ebx
	orl	%r15d, %ebx
	movq	_MIPI_DSI_CLOCK_NON_CONTINUOUS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 20(%r12)
	movl	$0, %eax
	jne	LBB0_35
## %bb.34:
	movq	_PHYC_HS_CLK_CONTINUOUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_DSI_PORT_BIT
LBB0_35:
	orl	%eax, %ebx
	decl	%r13d
	cmpl	$0, (%r12)
	jne	LBB0_36
## %bb.37:
	movq	_DSI0_PHYC_ESC_CLK_LPDT@GOTPCREL(%rip), %rax
	jmp	LBB0_38
LBB0_36:
	movq	_DSI1_PHYC_ESC_CLK_LPDT@GOTPCREL(%rip), %rax
LBB0_38:
	movl	(%rax), %esi
	movl	%r13d, %edi
	callq	_VC4_SET_FIELD
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_DSI_PORT_WRITE
	movq	_CTRL@GOTPCREL(%rip), %r14
	movl	(%r14), %ebx
	movl	%ebx, %edi
	callq	_DSI_PORT_READ
	movq	_DSI_CTRL_CAL_BYTE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_DSI_PORT_WRITE
	movq	_HSTX_TO_CNT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_DSI_PORT_WRITE
	movq	_LPRX_TO_CNT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$16777215, %esi                 ## imm = 0xFFFFFF
	callq	_DSI_PORT_WRITE
	movq	_TA_TO_CNT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$100000, %esi                   ## imm = 0x186A0
	callq	_DSI_PORT_WRITE
	movq	_PR_TO_CNT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$100000, %esi                   ## imm = 0x186A0
	callq	_DSI_PORT_WRITE
	movq	_DISP1_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_DSI_DISP1_PFORMAT_32BIT_LE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_DSI_DISP1_PFORMAT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_VC4_SET_FIELD
	movq	_DSI_DISP1_ENABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_DSI_PORT_WRITE
	cmpl	$0, (%r12)
	movl	(%r14), %ebx
	jne	LBB0_39
## %bb.40:
	movq	_DSI0_CTRL_CTRL0@GOTPCREL(%rip), %r14
	jmp	LBB0_41
LBB0_39:
	movq	_DSI1_CTRL_EN@GOTPCREL(%rip), %r14
LBB0_41:
	movl	%ebx, %edi
	callq	_DSI_PORT_READ
	orl	(%r14), %eax
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_DSI_PORT_WRITE
	cmpl	$0, (%r12)
	je	LBB0_43
## %bb.42:
	movq	_PHY_AFEC0@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%ebx, %edi
	callq	_DSI_PORT_READ
	movq	_DSI1_PHY_AFEC0_RESET@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	%ebx, %edi
	callq	_DSI_PORT_WRITE
LBB0_43:
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	_vc4_dsi_ulps
	movl	40(%r12), %edi
	callq	_drm_bridge_pre_enable
	movq	_MIPI_DSI_MODE_VIDEO@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_DISP0_CTRL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r14d
	testl	%eax, 20(%r12)
	je	LBB0_45
## %bb.44:
	movl	8(%r12), %edi
	movq	_DSI_DISP0_PIX_CLK_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_VC4_SET_FIELD
	movl	%eax, %r15d
	movl	24(%r12), %edi
	movq	_DSI_DISP0_PFORMAT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_VC4_SET_FIELD
	movl	%eax, %ebx
	orl	%r15d, %ebx
	movq	_DSI_DISP0_LP_STOP_PERFRAME@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_DSI_DISP0_LP_STOP_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_VC4_SET_FIELD
	movl	%eax, %esi
	orl	%ebx, %esi
	movq	_DSI_DISP0_ST_END@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_DSI_DISP0_ENABLE@GOTPCREL(%rip), %rax
	jmp	LBB0_46
LBB0_45:
	movq	_DSI_DISP0_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DSI_DISP0_COMMAND_MODE@GOTPCREL(%rip), %rax
LBB0_46:
	orl	(%rax), %esi
	movl	%r14d, %edi
	callq	_DSI_PORT_WRITE
	movl	40(%r12), %edi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_drm_bridge_enable              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Failed to runtime PM enable on DSI%d\n"

L_.str.2:                               ## @.str.2
	.asciz	"Failed to set phy clock to %ld: %d\n"

	.comm	_CTRL,4,2                       ## @CTRL
	.comm	_DSI_CTRL_SOFT_RESET_CFG,4,2    ## @DSI_CTRL_SOFT_RESET_CFG
	.comm	_CTRL_RESET_FIFOS,4,2           ## @CTRL_RESET_FIFOS
	.comm	_DSI_CTRL_HSDT_EOT_DISABLE,4,2  ## @DSI_CTRL_HSDT_EOT_DISABLE
	.comm	_DSI_CTRL_RX_LPDT_EOT_DISABLE,4,2 ## @DSI_CTRL_RX_LPDT_EOT_DISABLE
	.comm	_STAT,4,2                       ## @STAT
	.comm	_DSI_PHY_AFEC0_PTATADJ,4,2      ## @DSI_PHY_AFEC0_PTATADJ
	.comm	_DSI_PHY_AFEC0_CTATADJ,4,2      ## @DSI_PHY_AFEC0_CTATADJ
	.comm	_DSI0_PHY_AFEC0_PD_DLANE1,4,2   ## @DSI0_PHY_AFEC0_PD_DLANE1
	.comm	_MIPI_DSI_MODE_VIDEO,4,2        ## @MIPI_DSI_MODE_VIDEO
	.comm	_DSI0_PHY_AFEC0_RESET,4,2       ## @DSI0_PHY_AFEC0_RESET
	.comm	_PHY_AFEC0,4,2                  ## @PHY_AFEC0
	.comm	_PHY_AFEC1,4,2                  ## @PHY_AFEC1
	.comm	_DSI0_PHY_AFEC1_IDR_DLANE1,4,2  ## @DSI0_PHY_AFEC1_IDR_DLANE1
	.comm	_DSI0_PHY_AFEC1_IDR_DLANE0,4,2  ## @DSI0_PHY_AFEC1_IDR_DLANE0
	.comm	_DSI0_PHY_AFEC1_IDR_CLANE,4,2   ## @DSI0_PHY_AFEC1_IDR_CLANE
	.comm	_DSI1_PHY_AFEC0_IDR_CLANE,4,2   ## @DSI1_PHY_AFEC0_IDR_CLANE
	.comm	_DSI1_PHY_AFEC0_IDR_DLANE0,4,2  ## @DSI1_PHY_AFEC0_IDR_DLANE0
	.comm	_DSI1_PHY_AFEC0_IDR_DLANE1,4,2  ## @DSI1_PHY_AFEC0_IDR_DLANE1
	.comm	_DSI1_PHY_AFEC0_IDR_DLANE2,4,2  ## @DSI1_PHY_AFEC0_IDR_DLANE2
	.comm	_DSI1_PHY_AFEC0_IDR_DLANE3,4,2  ## @DSI1_PHY_AFEC0_IDR_DLANE3
	.comm	_DSI1_PHY_AFEC0_PD_DLANE3,4,2   ## @DSI1_PHY_AFEC0_PD_DLANE3
	.comm	_DSI1_PHY_AFEC0_PD_DLANE2,4,2   ## @DSI1_PHY_AFEC0_PD_DLANE2
	.comm	_DSI1_PHY_AFEC0_PD_DLANE1,4,2   ## @DSI1_PHY_AFEC0_PD_DLANE1
	.comm	_DSI1_PHY_AFEC0_RESET,4,2       ## @DSI1_PHY_AFEC0_RESET
L_.str.3:                               ## @.str.3
	.asciz	"Failed to turn on DSI escape clock: %d\n"

L_.str.4:                               ## @.str.4
	.asciz	"Failed to turn on DSI PLL: %d\n"

L_.str.5:                               ## @.str.5
	.asciz	"Failed to set pixel clock to %ldHz: %d\n"

L_.str.6:                               ## @.str.6
	.asciz	"Failed to turn on DSI pixel clock: %d\n"

	.comm	_HS_CLT0,4,2                    ## @HS_CLT0
	.comm	_DSI_HS_CLT0_CZERO,4,2          ## @DSI_HS_CLT0_CZERO
	.comm	_DSI_HS_CLT0_CPRE,4,2           ## @DSI_HS_CLT0_CPRE
	.comm	_DSI_HS_CLT0_CPREP,4,2          ## @DSI_HS_CLT0_CPREP
	.comm	_HS_CLT1,4,2                    ## @HS_CLT1
	.comm	_DSI_HS_CLT1_CTRAIL,4,2         ## @DSI_HS_CLT1_CTRAIL
	.comm	_DSI_HS_CLT1_CPOST,4,2          ## @DSI_HS_CLT1_CPOST
	.comm	_HS_CLT2,4,2                    ## @HS_CLT2
	.comm	_DSI_HS_CLT2_WUP,4,2            ## @DSI_HS_CLT2_WUP
	.comm	_HS_DLT3,4,2                    ## @HS_DLT3
	.comm	_DSI_HS_DLT3_EXIT,4,2           ## @DSI_HS_DLT3_EXIT
	.comm	_DSI_HS_DLT3_ZERO,4,2           ## @DSI_HS_DLT3_ZERO
	.comm	_DSI_HS_DLT3_PRE,4,2            ## @DSI_HS_DLT3_PRE
	.comm	_HS_DLT4,4,2                    ## @HS_DLT4
	.comm	_ESC_TIME_NS,4,2                ## @ESC_TIME_NS
	.comm	_DSI_HS_DLT4_LPX,4,2            ## @DSI_HS_DLT4_LPX
	.comm	_DSI_HS_DLT4_TRAIL,4,2          ## @DSI_HS_DLT4_TRAIL
	.comm	_DSI_HS_DLT4_ANLAT,4,2          ## @DSI_HS_DLT4_ANLAT
	.comm	_HS_DLT5,4,2                    ## @HS_DLT5
	.comm	_DSI_HS_DLT5_INIT,4,2           ## @DSI_HS_DLT5_INIT
	.comm	_HS_DLT6,4,2                    ## @HS_DLT6
	.comm	_DSI_HS_DLT6_TA_GET,4,2         ## @DSI_HS_DLT6_TA_GET
	.comm	_DSI_HS_DLT6_TA_SURE,4,2        ## @DSI_HS_DLT6_TA_SURE
	.comm	_DSI_HS_DLT6_TA_GO,4,2          ## @DSI_HS_DLT6_TA_GO
	.comm	_DSI_HS_DLT6_LP_LPX,4,2         ## @DSI_HS_DLT6_LP_LPX
	.comm	_HS_DLT7,4,2                    ## @HS_DLT7
	.comm	_DSI_HS_DLT7_LP_WUP,4,2         ## @DSI_HS_DLT7_LP_WUP
	.comm	_PHYC,4,2                       ## @PHYC
	.comm	_DSI_PHYC_DLANE0_ENABLE,4,2     ## @DSI_PHYC_DLANE0_ENABLE
	.comm	_DSI_PHYC_DLANE1_ENABLE,4,2     ## @DSI_PHYC_DLANE1_ENABLE
	.comm	_DSI_PHYC_DLANE2_ENABLE,4,2     ## @DSI_PHYC_DLANE2_ENABLE
	.comm	_DSI_PHYC_DLANE3_ENABLE,4,2     ## @DSI_PHYC_DLANE3_ENABLE
	.comm	_PHYC_CLANE_ENABLE,4,2          ## @PHYC_CLANE_ENABLE
	.comm	_MIPI_DSI_CLOCK_NON_CONTINUOUS,4,2 ## @MIPI_DSI_CLOCK_NON_CONTINUOUS
	.comm	_PHYC_HS_CLK_CONTINUOUS,4,2     ## @PHYC_HS_CLK_CONTINUOUS
	.comm	_DSI0_PHYC_ESC_CLK_LPDT,4,2     ## @DSI0_PHYC_ESC_CLK_LPDT
	.comm	_DSI1_PHYC_ESC_CLK_LPDT,4,2     ## @DSI1_PHYC_ESC_CLK_LPDT
	.comm	_DSI_CTRL_CAL_BYTE,4,2          ## @DSI_CTRL_CAL_BYTE
	.comm	_HSTX_TO_CNT,4,2                ## @HSTX_TO_CNT
	.comm	_LPRX_TO_CNT,4,2                ## @LPRX_TO_CNT
	.comm	_TA_TO_CNT,4,2                  ## @TA_TO_CNT
	.comm	_PR_TO_CNT,4,2                  ## @PR_TO_CNT
	.comm	_DISP1_CTRL,4,2                 ## @DISP1_CTRL
	.comm	_DSI_DISP1_PFORMAT_32BIT_LE,4,2 ## @DSI_DISP1_PFORMAT_32BIT_LE
	.comm	_DSI_DISP1_PFORMAT,4,2          ## @DSI_DISP1_PFORMAT
	.comm	_DSI_DISP1_ENABLE,4,2           ## @DSI_DISP1_ENABLE
	.comm	_DSI0_CTRL_CTRL0,4,2            ## @DSI0_CTRL_CTRL0
	.comm	_DSI1_CTRL_EN,4,2               ## @DSI1_CTRL_EN
	.comm	_DISP0_CTRL,4,2                 ## @DISP0_CTRL
	.comm	_DSI_DISP0_PIX_CLK_DIV,4,2      ## @DSI_DISP0_PIX_CLK_DIV
	.comm	_DSI_DISP0_PFORMAT,4,2          ## @DSI_DISP0_PFORMAT
	.comm	_DSI_DISP0_LP_STOP_PERFRAME,4,2 ## @DSI_DISP0_LP_STOP_PERFRAME
	.comm	_DSI_DISP0_LP_STOP_CTRL,4,2     ## @DSI_DISP0_LP_STOP_CTRL
	.comm	_DSI_DISP0_ST_END,4,2           ## @DSI_DISP0_ST_END
	.comm	_DSI_DISP0_ENABLE,4,2           ## @DSI_DISP0_ENABLE
	.comm	_DSI_DISP0_COMMAND_MODE,4,2     ## @DSI_DISP0_COMMAND_MODE
	.no_dead_strip	_vc4_dsi_encoder_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vc4_dsi_encoder_enable
_vc4_dsi_encoder_enable:                ; @vc4_dsi_encoder_enable
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	ldr	x8, [x0]
	ldr	x22, [x8]
	bl	_to_vc4_dsi_encoder
	ldr	x19, [x0]
	ldr	x21, [x19, #32]
	mov	w0, #60
	bl	_dsi_esc_timing
	mov	x20, x0
	ldrsw	x22, [x22]
	mov	x0, x21
	bl	_pm_runtime_get_sync
	cbz	w0, LBB0_2
; %bb.1:
	ldr	w1, [x19]
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	b	LBB0_15
LBB0_2:
	mov	w8, #1000
	mul	x8, x22, x8
	add	x8, x8, #1000
	ldr	x9, [x19, #8]
	mul	x22, x9, x8
	ldr	w0, [x19, #48]
	mov	x1, x22
	bl	_clk_set_rate
	cbz	w0, LBB0_4
; %bb.3:
	mov	x3, x0
	ldr	x0, [x19, #32]
Lloh2:
	adrp	x1, l_.str.2@PAGE
Lloh3:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x2, x22
	bl	_dev_err
LBB0_4:
Lloh4:
	adrp	x25, _CTRL@GOTPAGE
Lloh5:
	ldr	x25, [x25, _CTRL@GOTPAGEOFF]
	ldr	w23, [x25]
Lloh6:
	adrp	x8, _DSI_CTRL_SOFT_RESET_CFG@GOTPAGE
Lloh7:
	ldr	x8, [x8, _DSI_CTRL_SOFT_RESET_CFG@GOTPAGEOFF]
Lloh8:
	ldr	w24, [x8]
Lloh9:
	adrp	x8, _CTRL_RESET_FIFOS@GOTPAGE
Lloh10:
	ldr	x8, [x8, _CTRL_RESET_FIFOS@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	bl	_DSI_PORT_BIT
	orr	w1, w0, w24
	mov	x0, x23
	bl	_DSI_PORT_WRITE
Lloh12:
	adrp	x8, _DSI_CTRL_HSDT_EOT_DISABLE@GOTPAGE
Lloh13:
	ldr	x8, [x8, _DSI_CTRL_HSDT_EOT_DISABLE@GOTPAGEOFF]
	ldr	w0, [x25]
Lloh14:
	ldr	w8, [x8]
Lloh15:
	adrp	x9, _DSI_CTRL_RX_LPDT_EOT_DISABLE@GOTPAGE
Lloh16:
	ldr	x9, [x9, _DSI_CTRL_RX_LPDT_EOT_DISABLE@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	orr	w1, w9, w8
	bl	_DSI_PORT_WRITE
Lloh18:
	adrp	x8, _STAT@GOTPAGE
Lloh19:
	ldr	x8, [x8, _STAT@GOTPAGEOFF]
Lloh20:
	ldr	w23, [x8]
	mov	x0, x23
	bl	_DSI_PORT_READ
	mov	x1, x0
	mov	x0, x23
	bl	_DSI_PORT_WRITE
	ldr	w24, [x19]
Lloh21:
	adrp	x8, _DSI_PHY_AFEC0_PTATADJ@GOTPAGE
Lloh22:
	ldr	x8, [x8, _DSI_PHY_AFEC0_PTATADJ@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	mov	w0, #7
	bl	_VC4_SET_FIELD
	mov	x23, x0
Lloh24:
	adrp	x8, _DSI_PHY_AFEC0_CTATADJ@GOTPAGE
Lloh25:
	ldr	x8, [x8, _DSI_PHY_AFEC0_CTATADJ@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	w0, #7
	bl	_VC4_SET_FIELD
	orr	w23, w0, w23
	cbz	w24, LBB0_6
; %bb.5:
Lloh27:
	adrp	x8, _DSI1_PHY_AFEC0_IDR_CLANE@GOTPAGE
Lloh28:
	ldr	x8, [x8, _DSI1_PHY_AFEC0_IDR_CLANE@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	mov	w0, #6
	bl	_VC4_SET_FIELD
	orr	w23, w23, w0
Lloh30:
	adrp	x8, _DSI1_PHY_AFEC0_IDR_DLANE0@GOTPAGE
Lloh31:
	ldr	x8, [x8, _DSI1_PHY_AFEC0_IDR_DLANE0@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
	mov	w0, #6
	bl	_VC4_SET_FIELD
	orr	w23, w23, w0
Lloh33:
	adrp	x8, _DSI1_PHY_AFEC0_IDR_DLANE1@GOTPAGE
Lloh34:
	ldr	x8, [x8, _DSI1_PHY_AFEC0_IDR_DLANE1@GOTPAGEOFF]
Lloh35:
	ldr	w1, [x8]
	mov	w0, #6
	bl	_VC4_SET_FIELD
	orr	w23, w23, w0
Lloh36:
	adrp	x8, _DSI1_PHY_AFEC0_IDR_DLANE2@GOTPAGE
Lloh37:
	ldr	x8, [x8, _DSI1_PHY_AFEC0_IDR_DLANE2@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
	mov	w0, #6
	bl	_VC4_SET_FIELD
	orr	w23, w23, w0
Lloh39:
	adrp	x8, _DSI1_PHY_AFEC0_IDR_DLANE3@GOTPAGE
Lloh40:
	ldr	x8, [x8, _DSI1_PHY_AFEC0_IDR_DLANE3@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	mov	w0, #6
	bl	_VC4_SET_FIELD
	orr	w8, w23, w0
Lloh42:
	adrp	x9, _DSI1_PHY_AFEC0_PD_DLANE3@GOTPAGE
Lloh43:
	ldr	x9, [x9, _DSI1_PHY_AFEC0_PD_DLANE3@GOTPAGEOFF]
	ldr	w10, [x19, #16]
Lloh44:
	ldr	w9, [x9]
	cmp	w10, #4
	csel	w9, w9, wzr, lt
Lloh45:
	adrp	x11, _DSI1_PHY_AFEC0_PD_DLANE2@GOTPAGE
Lloh46:
	ldr	x11, [x11, _DSI1_PHY_AFEC0_PD_DLANE2@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh47:
	ldr	w9, [x11]
	cmp	w10, #3
	csel	w9, w9, wzr, lt
Lloh48:
	adrp	x11, _DSI1_PHY_AFEC0_PD_DLANE1@GOTPAGE
Lloh49:
	ldr	x11, [x11, _DSI1_PHY_AFEC0_PD_DLANE1@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh50:
	ldr	w9, [x11]
	cmp	w10, #2
	csel	w9, w9, wzr, lt
Lloh51:
	adrp	x10, _DSI1_PHY_AFEC0_RESET@GOTPAGE
Lloh52:
	ldr	x10, [x10, _DSI1_PHY_AFEC0_RESET@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh53:
	ldr	w9, [x10]
	orr	w1, w8, w9
Lloh54:
	adrp	x8, _PHY_AFEC0@GOTPAGE
Lloh55:
	ldr	x8, [x8, _PHY_AFEC0@GOTPAGEOFF]
Lloh56:
	ldr	w0, [x8]
	bl	_DSI_PORT_WRITE
Lloh57:
	adrp	x8, _PHY_AFEC1@GOTPAGE
Lloh58:
	ldr	x8, [x8, _PHY_AFEC1@GOTPAGEOFF]
Lloh59:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_DSI_PORT_WRITE
	mov	w0, #1
	bl	_mdelay
	b	LBB0_7
LBB0_6:
Lloh60:
	adrp	x8, _DSI0_PHY_AFEC0_PD_DLANE1@GOTPAGE
Lloh61:
	ldr	x8, [x8, _DSI0_PHY_AFEC0_PD_DLANE1@GOTPAGEOFF]
Lloh62:
	ldr	w8, [x8]
	ldp	w9, w10, [x19, #16]
	cmp	w9, #2
	csel	w8, w8, wzr, lt
	orr	w8, w23, w8
Lloh63:
	adrp	x9, _MIPI_DSI_MODE_VIDEO@GOTPAGE
Lloh64:
	ldr	x9, [x9, _MIPI_DSI_MODE_VIDEO@GOTPAGEOFF]
Lloh65:
	ldr	w9, [x9]
Lloh66:
	adrp	x11, _DSI0_PHY_AFEC0_RESET@GOTPAGE
Lloh67:
	ldr	x11, [x11, _DSI0_PHY_AFEC0_RESET@GOTPAGEOFF]
Lloh68:
	ldr	w11, [x11]
	tst	w9, w10
	csel	w9, w11, wzr, eq
	orr	w1, w8, w9
Lloh69:
	adrp	x8, _PHY_AFEC0@GOTPAGE
Lloh70:
	ldr	x8, [x8, _PHY_AFEC0@GOTPAGEOFF]
Lloh71:
	ldr	w0, [x8]
	bl	_DSI_PORT_WRITE
Lloh72:
	adrp	x8, _PHY_AFEC1@GOTPAGE
Lloh73:
	ldr	x8, [x8, _PHY_AFEC1@GOTPAGEOFF]
Lloh74:
	ldr	w23, [x8]
Lloh75:
	adrp	x8, _DSI0_PHY_AFEC1_IDR_DLANE1@GOTPAGE
Lloh76:
	ldr	x8, [x8, _DSI0_PHY_AFEC1_IDR_DLANE1@GOTPAGEOFF]
Lloh77:
	ldr	w1, [x8]
	mov	w0, #6
	bl	_VC4_SET_FIELD
	mov	x24, x0
Lloh78:
	adrp	x8, _DSI0_PHY_AFEC1_IDR_DLANE0@GOTPAGE
Lloh79:
	ldr	x8, [x8, _DSI0_PHY_AFEC1_IDR_DLANE0@GOTPAGEOFF]
Lloh80:
	ldr	w1, [x8]
	mov	w0, #6
	bl	_VC4_SET_FIELD
	orr	w24, w0, w24
Lloh81:
	adrp	x8, _DSI0_PHY_AFEC1_IDR_CLANE@GOTPAGE
Lloh82:
	ldr	x8, [x8, _DSI0_PHY_AFEC1_IDR_CLANE@GOTPAGEOFF]
Lloh83:
	ldr	w1, [x8]
	mov	w0, #6
	bl	_VC4_SET_FIELD
	orr	w1, w24, w0
	mov	x0, x23
	bl	_DSI_PORT_WRITE
LBB0_7:
	ldr	w0, [x19, #52]
	bl	_clk_prepare_enable
	cbz	w0, LBB0_9
; %bb.8:
	mov	x1, x0
Lloh84:
	adrp	x0, l_.str.3@PAGE
Lloh85:
	add	x0, x0, l_.str.3@PAGEOFF
	b	LBB0_15
LBB0_9:
	ldr	w0, [x19, #48]
	bl	_clk_prepare_enable
	cbz	w0, LBB0_11
; %bb.10:
	mov	x1, x0
Lloh86:
	adrp	x0, l_.str.4@PAGE
Lloh87:
	add	x0, x0, l_.str.4@PAGEOFF
	b	LBB0_15
LBB0_11:
	ldr	w0, [x19, #48]
	bl	_clk_get_rate
	mov	x23, x0
	lsr	x22, x22, #3
	ldr	w0, [x19, #44]
	mov	x1, x22
	bl	_clk_set_rate
	cbz	w0, LBB0_13
; %bb.12:
	mov	x3, x0
Lloh88:
	adrp	x1, l_.str.5@PAGE
Lloh89:
	add	x1, x1, l_.str.5@PAGEOFF
	mov	x0, x21
	mov	x2, x22
	bl	_dev_err
LBB0_13:
	ldr	w0, [x19, #44]
	bl	_clk_prepare_enable
	cbz	w0, LBB0_16
; %bb.14:
	mov	x1, x0
Lloh90:
	adrp	x0, l_.str.6@PAGE
Lloh91:
	add	x0, x0, l_.str.6@PAGEOFF
LBB0_15:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_DRM_ERROR
LBB0_16:
	mov	w0, #25856
	movk	w0, #7629, lsl #16
	mov	x1, x23
	bl	_DIV_ROUND_UP
	mov	x21, x0
Lloh92:
	adrp	x8, _HS_CLT0@GOTPAGE
Lloh93:
	ldr	x8, [x8, _HS_CLT0@GOTPAGEOFF]
Lloh94:
	ldr	w22, [x8]
	mov	w1, #262
	mov	w2, #0
	bl	_dsi_hs_timing
Lloh95:
	adrp	x8, _DSI_HS_CLT0_CZERO@GOTPAGE
Lloh96:
	ldr	x8, [x8, _DSI_HS_CLT0_CZERO@GOTPAGEOFF]
Lloh97:
	ldr	w1, [x8]
	bl	_VC4_SET_FIELD
	mov	x23, x0
	mov	x0, x21
	mov	w1, #0
	mov	w2, #8
	bl	_dsi_hs_timing
Lloh98:
	adrp	x8, _DSI_HS_CLT0_CPRE@GOTPAGE
Lloh99:
	ldr	x8, [x8, _DSI_HS_CLT0_CPRE@GOTPAGEOFF]
Lloh100:
	ldr	w1, [x8]
	bl	_VC4_SET_FIELD
	orr	w23, w0, w23
	mov	x0, x21
	mov	w1, #38
	mov	w2, #0
	bl	_dsi_hs_timing
Lloh101:
	adrp	x8, _DSI_HS_CLT0_CPREP@GOTPAGE
Lloh102:
	ldr	x8, [x8, _DSI_HS_CLT0_CPREP@GOTPAGEOFF]
Lloh103:
	ldr	w1, [x8]
	bl	_VC4_SET_FIELD
	orr	w1, w23, w0
	mov	x0, x22
	bl	_DSI_PORT_WRITE
Lloh104:
	adrp	x8, _HS_CLT1@GOTPAGE
Lloh105:
	ldr	x8, [x8, _HS_CLT1@GOTPAGEOFF]
Lloh106:
	ldr	w22, [x8]
	mov	x0, x21
	mov	w1, #60
	mov	w2, #0
	bl	_dsi_hs_timing
Lloh107:
	adrp	x8, _DSI_HS_CLT1_CTRAIL@GOTPAGE
Lloh108:
	ldr	x8, [x8, _DSI_HS_CLT1_CTRAIL@GOTPAGEOFF]
Lloh109:
	ldr	w1, [x8]
	bl	_VC4_SET_FIELD
	mov	x23, x0
	mov	x0, x21
	mov	w1, #60
	mov	w2, #52
	bl	_dsi_hs_timing
Lloh110:
	adrp	x8, _DSI_HS_CLT1_CPOST@GOTPAGE
Lloh111:
	ldr	x8, [x8, _DSI_HS_CLT1_CPOST@GOTPAGEOFF]
Lloh112:
	ldr	w1, [x8]
	bl	_VC4_SET_FIELD
	orr	w1, w0, w23
	mov	x0, x22
	bl	_DSI_PORT_WRITE
Lloh113:
	adrp	x8, _HS_CLT2@GOTPAGE
Lloh114:
	ldr	x8, [x8, _HS_CLT2@GOTPAGEOFF]
Lloh115:
	ldr	w22, [x8]
	mov	x0, x21
	mov	w1, #16960
	movk	w1, #15, lsl #16
	mov	w2, #0
	bl	_dsi_hs_timing
Lloh116:
	adrp	x8, _DSI_HS_CLT2_WUP@GOTPAGE
Lloh117:
	ldr	x8, [x8, _DSI_HS_CLT2_WUP@GOTPAGEOFF]
Lloh118:
	ldr	w1, [x8]
	bl	_VC4_SET_FIELD
	mov	x1, x0
	mov	x0, x22
	bl	_DSI_PORT_WRITE
Lloh119:
	adrp	x8, _HS_DLT3@GOTPAGE
Lloh120:
	ldr	x8, [x8, _HS_DLT3@GOTPAGEOFF]
Lloh121:
	ldr	w22, [x8]
	mov	x0, x21
	mov	w1, #100
	mov	w2, #0
	bl	_dsi_hs_timing
Lloh122:
	adrp	x8, _DSI_HS_DLT3_EXIT@GOTPAGE
Lloh123:
	ldr	x8, [x8, _DSI_HS_DLT3_EXIT@GOTPAGEOFF]
Lloh124:
	ldr	w1, [x8]
	bl	_VC4_SET_FIELD
	mov	x23, x0
	mov	x0, x21
	mov	w1, #105
	mov	w2, #6
	bl	_dsi_hs_timing
Lloh125:
	adrp	x8, _DSI_HS_DLT3_ZERO@GOTPAGE
Lloh126:
	ldr	x8, [x8, _DSI_HS_DLT3_ZERO@GOTPAGEOFF]
Lloh127:
	ldr	w1, [x8]
	bl	_VC4_SET_FIELD
	orr	w23, w0, w23
	mov	x0, x21
	mov	w1, #40
	mov	w2, #4
	bl	_dsi_hs_timing
Lloh128:
	adrp	x8, _DSI_HS_DLT3_PRE@GOTPAGE
Lloh129:
	ldr	x8, [x8, _DSI_HS_DLT3_PRE@GOTPAGEOFF]
Lloh130:
	ldr	w1, [x8]
	bl	_VC4_SET_FIELD
	orr	w1, w23, w0
	mov	x0, x22
	bl	_DSI_PORT_WRITE
Lloh131:
	adrp	x8, _HS_DLT4@GOTPAGE
Lloh132:
	ldr	x8, [x8, _HS_DLT4@GOTPAGEOFF]
Lloh133:
	ldr	w22, [x8]
Lloh134:
	adrp	x8, _ESC_TIME_NS@GOTPAGE
Lloh135:
	ldr	x8, [x8, _ESC_TIME_NS@GOTPAGEOFF]
Lloh136:
	ldr	w8, [x8]
	mul	w1, w8, w20
	mov	x0, x21
	mov	w2, #0
	bl	_dsi_hs_timing
Lloh137:
	adrp	x8, _DSI_HS_DLT4_LPX@GOTPAGE
Lloh138:
	ldr	x8, [x8, _DSI_HS_DLT4_LPX@GOTPAGEOFF]
Lloh139:
	ldr	w1, [x8]
	bl	_VC4_SET_FIELD
	mov	x23, x0
	mov	x0, x21
	mov	w1, #0
	mov	w2, #8
	bl	_dsi_hs_timing
	mov	x24, x0
	mov	x0, x21
	mov	w1, #60
	mov	w2, #4
	bl	_dsi_hs_timing
	mov	x1, x0
	mov	x0, x24
	bl	_max
Lloh140:
	adrp	x8, _DSI_HS_DLT4_TRAIL@GOTPAGE
Lloh141:
	ldr	x8, [x8, _DSI_HS_DLT4_TRAIL@GOTPAGEOFF]
Lloh142:
	ldr	w1, [x8]
	bl	_VC4_SET_FIELD
	orr	w23, w0, w23
Lloh143:
	adrp	x8, _DSI_HS_DLT4_ANLAT@GOTPAGE
Lloh144:
	ldr	x8, [x8, _DSI_HS_DLT4_ANLAT@GOTPAGEOFF]
Lloh145:
	ldr	w1, [x8]
	mov	w0, #0
	bl	_VC4_SET_FIELD
	orr	w1, w23, w0
	mov	x0, x22
	bl	_DSI_PORT_WRITE
Lloh146:
	adrp	x8, _HS_DLT5@GOTPAGE
Lloh147:
	ldr	x8, [x8, _HS_DLT5@GOTPAGEOFF]
Lloh148:
	ldr	w22, [x8]
	mov	x0, x21
	mov	w1, #19264
	movk	w1, #76, lsl #16
	mov	w2, #0
	bl	_dsi_hs_timing
Lloh149:
	adrp	x8, _DSI_HS_DLT5_INIT@GOTPAGE
Lloh150:
	ldr	x8, [x8, _DSI_HS_DLT5_INIT@GOTPAGEOFF]
Lloh151:
	ldr	w1, [x8]
	bl	_VC4_SET_FIELD
	mov	x1, x0
	mov	x0, x22
	bl	_DSI_PORT_WRITE
Lloh152:
	adrp	x8, _HS_DLT6@GOTPAGE
Lloh153:
	ldr	x8, [x8, _HS_DLT6@GOTPAGEOFF]
Lloh154:
	ldr	w21, [x8]
	lsl	w22, w20, #2
	add	w0, w22, w20
Lloh155:
	adrp	x8, _DSI_HS_DLT6_TA_GET@GOTPAGE
Lloh156:
	ldr	x8, [x8, _DSI_HS_DLT6_TA_GET@GOTPAGEOFF]
Lloh157:
	ldr	w1, [x8]
	bl	_VC4_SET_FIELD
	mov	x23, x0
Lloh158:
	adrp	x8, _DSI_HS_DLT6_TA_SURE@GOTPAGE
Lloh159:
	ldr	x8, [x8, _DSI_HS_DLT6_TA_SURE@GOTPAGEOFF]
Lloh160:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_VC4_SET_FIELD
	orr	w23, w0, w23
Lloh161:
	adrp	x8, _DSI_HS_DLT6_TA_GO@GOTPAGE
Lloh162:
	ldr	x8, [x8, _DSI_HS_DLT6_TA_GO@GOTPAGEOFF]
Lloh163:
	ldr	w1, [x8]
	mov	x0, x22
	bl	_VC4_SET_FIELD
	orr	w22, w23, w0
Lloh164:
	adrp	x8, _DSI_HS_DLT6_LP_LPX@GOTPAGE
Lloh165:
	ldr	x8, [x8, _DSI_HS_DLT6_LP_LPX@GOTPAGEOFF]
Lloh166:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_VC4_SET_FIELD
	orr	w1, w22, w0
	mov	x0, x21
	bl	_DSI_PORT_WRITE
Lloh167:
	adrp	x8, _HS_DLT7@GOTPAGE
Lloh168:
	ldr	x8, [x8, _HS_DLT7@GOTPAGEOFF]
Lloh169:
	ldr	w21, [x8]
	mov	w0, #16960
	movk	w0, #15, lsl #16
	bl	_dsi_esc_timing
Lloh170:
	adrp	x8, _DSI_HS_DLT7_LP_WUP@GOTPAGE
Lloh171:
	ldr	x8, [x8, _DSI_HS_DLT7_LP_WUP@GOTPAGEOFF]
Lloh172:
	ldr	w1, [x8]
	bl	_VC4_SET_FIELD
	mov	x1, x0
	mov	x0, x21
	bl	_DSI_PORT_WRITE
Lloh173:
	adrp	x8, _PHYC@GOTPAGE
Lloh174:
	ldr	x8, [x8, _PHYC@GOTPAGEOFF]
Lloh175:
	adrp	x9, _DSI_PHYC_DLANE0_ENABLE@GOTPAGE
Lloh176:
	ldr	x9, [x9, _DSI_PHYC_DLANE0_ENABLE@GOTPAGEOFF]
Lloh177:
	ldr	w21, [x8]
Lloh178:
	ldr	w8, [x9]
	ldr	w9, [x19, #16]
Lloh179:
	adrp	x10, _DSI_PHYC_DLANE1_ENABLE@GOTPAGE
Lloh180:
	ldr	x10, [x10, _DSI_PHYC_DLANE1_ENABLE@GOTPAGEOFF]
Lloh181:
	ldr	w10, [x10]
	cmp	w9, #1
	csel	w10, w10, wzr, gt
	orr	w8, w10, w8
Lloh182:
	adrp	x10, _DSI_PHYC_DLANE2_ENABLE@GOTPAGE
Lloh183:
	ldr	x10, [x10, _DSI_PHYC_DLANE2_ENABLE@GOTPAGEOFF]
Lloh184:
	ldr	w10, [x10]
	cmp	w9, #2
	csel	w10, w10, wzr, gt
	orr	w8, w8, w10
Lloh185:
	adrp	x10, _DSI_PHYC_DLANE3_ENABLE@GOTPAGE
Lloh186:
	ldr	x10, [x10, _DSI_PHYC_DLANE3_ENABLE@GOTPAGEOFF]
Lloh187:
	ldr	w10, [x10]
	cmp	w9, #3
	csel	w9, w10, wzr, gt
	orr	w22, w8, w9
Lloh188:
	adrp	x8, _PHYC_CLANE_ENABLE@GOTPAGE
Lloh189:
	ldr	x8, [x8, _PHYC_CLANE_ENABLE@GOTPAGEOFF]
Lloh190:
	ldr	w0, [x8]
	bl	_DSI_PORT_BIT
	mov	x8, x0
	mov	w0, #0
	orr	w22, w22, w8
	ldr	w8, [x19, #20]
Lloh191:
	adrp	x9, _MIPI_DSI_CLOCK_NON_CONTINUOUS@GOTPAGE
Lloh192:
	ldr	x9, [x9, _MIPI_DSI_CLOCK_NON_CONTINUOUS@GOTPAGEOFF]
Lloh193:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_18
; %bb.17:
Lloh194:
	adrp	x8, _PHYC_HS_CLK_CONTINUOUS@GOTPAGE
Lloh195:
	ldr	x8, [x8, _PHYC_HS_CLK_CONTINUOUS@GOTPAGEOFF]
Lloh196:
	ldr	w0, [x8]
	bl	_DSI_PORT_BIT
LBB0_18:
	orr	w22, w22, w0
	ldr	w8, [x19]
Lloh197:
	adrp	x9, _DSI0_PHYC_ESC_CLK_LPDT@GOTPAGE
Lloh198:
	ldr	x9, [x9, _DSI0_PHYC_ESC_CLK_LPDT@GOTPAGEOFF]
	sub	w0, w20, #1
Lloh199:
	adrp	x10, _DSI1_PHYC_ESC_CLK_LPDT@GOTPAGE
Lloh200:
	ldr	x10, [x10, _DSI1_PHYC_ESC_CLK_LPDT@GOTPAGEOFF]
	cmp	w8, #0
	csel	x8, x9, x10, eq
	ldr	w1, [x8]
	bl	_VC4_SET_FIELD
	orr	w1, w22, w0
	mov	x0, x21
	bl	_DSI_PORT_WRITE
	ldr	w20, [x25]
	mov	x0, x20
	bl	_DSI_PORT_READ
Lloh201:
	adrp	x8, _DSI_CTRL_CAL_BYTE@GOTPAGE
Lloh202:
	ldr	x8, [x8, _DSI_CTRL_CAL_BYTE@GOTPAGEOFF]
Lloh203:
	ldr	w8, [x8]
	orr	w1, w8, w0
	mov	x0, x20
	bl	_DSI_PORT_WRITE
Lloh204:
	adrp	x8, _HSTX_TO_CNT@GOTPAGE
Lloh205:
	ldr	x8, [x8, _HSTX_TO_CNT@GOTPAGEOFF]
Lloh206:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_DSI_PORT_WRITE
Lloh207:
	adrp	x8, _LPRX_TO_CNT@GOTPAGE
Lloh208:
	ldr	x8, [x8, _LPRX_TO_CNT@GOTPAGEOFF]
Lloh209:
	ldr	w0, [x8]
	mov	w1, #16777215
	bl	_DSI_PORT_WRITE
Lloh210:
	adrp	x8, _TA_TO_CNT@GOTPAGE
Lloh211:
	ldr	x8, [x8, _TA_TO_CNT@GOTPAGEOFF]
Lloh212:
	ldr	w0, [x8]
	mov	w1, #34464
	movk	w1, #1, lsl #16
	bl	_DSI_PORT_WRITE
Lloh213:
	adrp	x8, _PR_TO_CNT@GOTPAGE
Lloh214:
	ldr	x8, [x8, _PR_TO_CNT@GOTPAGEOFF]
Lloh215:
	ldr	w0, [x8]
	mov	w1, #34464
	movk	w1, #1, lsl #16
	bl	_DSI_PORT_WRITE
Lloh216:
	adrp	x8, _DISP1_CTRL@GOTPAGE
Lloh217:
	ldr	x8, [x8, _DISP1_CTRL@GOTPAGEOFF]
Lloh218:
	ldr	w20, [x8]
Lloh219:
	adrp	x8, _DSI_DISP1_PFORMAT_32BIT_LE@GOTPAGE
Lloh220:
	ldr	x8, [x8, _DSI_DISP1_PFORMAT_32BIT_LE@GOTPAGEOFF]
Lloh221:
	ldr	w0, [x8]
Lloh222:
	adrp	x8, _DSI_DISP1_PFORMAT@GOTPAGE
Lloh223:
	ldr	x8, [x8, _DSI_DISP1_PFORMAT@GOTPAGEOFF]
Lloh224:
	ldr	w1, [x8]
	bl	_VC4_SET_FIELD
Lloh225:
	adrp	x8, _DSI_DISP1_ENABLE@GOTPAGE
Lloh226:
	ldr	x8, [x8, _DSI_DISP1_ENABLE@GOTPAGEOFF]
Lloh227:
	ldr	w8, [x8]
	orr	w1, w8, w0
	mov	x0, x20
	bl	_DSI_PORT_WRITE
	ldr	w21, [x19]
	ldr	w20, [x25]
	mov	x0, x20
	bl	_DSI_PORT_READ
Lloh228:
	adrp	x8, _DSI0_CTRL_CTRL0@GOTPAGE
Lloh229:
	ldr	x8, [x8, _DSI0_CTRL_CTRL0@GOTPAGEOFF]
Lloh230:
	adrp	x9, _DSI1_CTRL_EN@GOTPAGE
Lloh231:
	ldr	x9, [x9, _DSI1_CTRL_EN@GOTPAGEOFF]
	cmp	w21, #0
	csel	x8, x8, x9, eq
	ldr	w8, [x8]
	orr	w1, w8, w0
	mov	x0, x20
	bl	_DSI_PORT_WRITE
	ldr	w8, [x19]
	cbz	w8, LBB0_20
; %bb.19:
Lloh232:
	adrp	x8, _PHY_AFEC0@GOTPAGE
Lloh233:
	ldr	x8, [x8, _PHY_AFEC0@GOTPAGEOFF]
Lloh234:
	ldr	w20, [x8]
	mov	x0, x20
	bl	_DSI_PORT_READ
Lloh235:
	adrp	x8, _DSI1_PHY_AFEC0_RESET@GOTPAGE
Lloh236:
	ldr	x8, [x8, _DSI1_PHY_AFEC0_RESET@GOTPAGEOFF]
Lloh237:
	ldr	w8, [x8]
	bic	w1, w0, w8
	mov	x0, x20
	bl	_DSI_PORT_WRITE
LBB0_20:
	mov	x0, x19
	mov	w1, #0
	bl	_vc4_dsi_ulps
	ldr	w0, [x19, #40]
	bl	_drm_bridge_pre_enable
Lloh238:
	adrp	x8, _MIPI_DSI_MODE_VIDEO@GOTPAGE
Lloh239:
	ldr	x8, [x8, _MIPI_DSI_MODE_VIDEO@GOTPAGEOFF]
	ldr	w9, [x19, #20]
Lloh240:
	ldr	w8, [x8]
Lloh241:
	adrp	x10, _DISP0_CTRL@GOTPAGE
Lloh242:
	ldr	x10, [x10, _DISP0_CTRL@GOTPAGEOFF]
Lloh243:
	ldr	w20, [x10]
	tst	w8, w9
	b.eq	LBB0_22
; %bb.21:
	ldr	w0, [x19, #8]
Lloh244:
	adrp	x8, _DSI_DISP0_PIX_CLK_DIV@GOTPAGE
Lloh245:
	ldr	x8, [x8, _DSI_DISP0_PIX_CLK_DIV@GOTPAGEOFF]
Lloh246:
	ldr	w1, [x8]
	bl	_VC4_SET_FIELD
	mov	x21, x0
	ldr	w0, [x19, #24]
Lloh247:
	adrp	x8, _DSI_DISP0_PFORMAT@GOTPAGE
Lloh248:
	ldr	x8, [x8, _DSI_DISP0_PFORMAT@GOTPAGEOFF]
Lloh249:
	ldr	w1, [x8]
	bl	_VC4_SET_FIELD
	orr	w21, w0, w21
Lloh250:
	adrp	x8, _DSI_DISP0_LP_STOP_PERFRAME@GOTPAGE
Lloh251:
	ldr	x8, [x8, _DSI_DISP0_LP_STOP_PERFRAME@GOTPAGEOFF]
Lloh252:
	ldr	w0, [x8]
Lloh253:
	adrp	x8, _DSI_DISP0_LP_STOP_CTRL@GOTPAGE
Lloh254:
	ldr	x8, [x8, _DSI_DISP0_LP_STOP_CTRL@GOTPAGEOFF]
Lloh255:
	ldr	w1, [x8]
	bl	_VC4_SET_FIELD
	orr	w8, w21, w0
Lloh256:
	adrp	x9, _DSI_DISP0_ST_END@GOTPAGE
Lloh257:
	ldr	x9, [x9, _DSI_DISP0_ST_END@GOTPAGEOFF]
Lloh258:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh259:
	adrp	x9, _DSI_DISP0_ENABLE@GOTPAGE
Lloh260:
	ldr	x9, [x9, _DSI_DISP0_ENABLE@GOTPAGEOFF]
	b	LBB0_23
LBB0_22:
Lloh261:
	adrp	x8, _DSI_DISP0_ENABLE@GOTPAGE
Lloh262:
	ldr	x8, [x8, _DSI_DISP0_ENABLE@GOTPAGEOFF]
Lloh263:
	ldr	w8, [x8]
Lloh264:
	adrp	x9, _DSI_DISP0_COMMAND_MODE@GOTPAGE
Lloh265:
	ldr	x9, [x9, _DSI_DISP0_COMMAND_MODE@GOTPAGEOFF]
LBB0_23:
	ldr	w9, [x9]
	orr	w1, w8, w9
	mov	x0, x20
	bl	_DSI_PORT_WRITE
	ldr	w0, [x19, #40]
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_drm_bridge_enable
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpAdd	Lloh84, Lloh85
	.loh AdrpAdd	Lloh86, Lloh87
	.loh AdrpAdd	Lloh88, Lloh89
	.loh AdrpAdd	Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh191, Lloh192, Lloh193
	.loh AdrpLdrGotLdr	Lloh188, Lloh189, Lloh190
	.loh AdrpLdrGotLdr	Lloh185, Lloh186, Lloh187
	.loh AdrpLdrGotLdr	Lloh182, Lloh183, Lloh184
	.loh AdrpLdrGotLdr	Lloh179, Lloh180, Lloh181
	.loh AdrpLdrGotLdr	Lloh175, Lloh176, Lloh178
	.loh AdrpLdrGotLdr	Lloh173, Lloh174, Lloh177
	.loh AdrpLdrGotLdr	Lloh170, Lloh171, Lloh172
	.loh AdrpLdrGotLdr	Lloh167, Lloh168, Lloh169
	.loh AdrpLdrGotLdr	Lloh164, Lloh165, Lloh166
	.loh AdrpLdrGotLdr	Lloh161, Lloh162, Lloh163
	.loh AdrpLdrGotLdr	Lloh158, Lloh159, Lloh160
	.loh AdrpLdrGotLdr	Lloh155, Lloh156, Lloh157
	.loh AdrpLdrGotLdr	Lloh152, Lloh153, Lloh154
	.loh AdrpLdrGotLdr	Lloh149, Lloh150, Lloh151
	.loh AdrpLdrGotLdr	Lloh146, Lloh147, Lloh148
	.loh AdrpLdrGotLdr	Lloh143, Lloh144, Lloh145
	.loh AdrpLdrGotLdr	Lloh140, Lloh141, Lloh142
	.loh AdrpLdrGotLdr	Lloh137, Lloh138, Lloh139
	.loh AdrpLdrGotLdr	Lloh134, Lloh135, Lloh136
	.loh AdrpLdrGotLdr	Lloh131, Lloh132, Lloh133
	.loh AdrpLdrGotLdr	Lloh128, Lloh129, Lloh130
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh194, Lloh195, Lloh196
	.loh AdrpLdrGot	Lloh230, Lloh231
	.loh AdrpLdrGot	Lloh228, Lloh229
	.loh AdrpLdrGotLdr	Lloh225, Lloh226, Lloh227
	.loh AdrpLdrGotLdr	Lloh222, Lloh223, Lloh224
	.loh AdrpLdrGotLdr	Lloh219, Lloh220, Lloh221
	.loh AdrpLdrGotLdr	Lloh216, Lloh217, Lloh218
	.loh AdrpLdrGotLdr	Lloh213, Lloh214, Lloh215
	.loh AdrpLdrGotLdr	Lloh210, Lloh211, Lloh212
	.loh AdrpLdrGotLdr	Lloh207, Lloh208, Lloh209
	.loh AdrpLdrGotLdr	Lloh204, Lloh205, Lloh206
	.loh AdrpLdrGotLdr	Lloh201, Lloh202, Lloh203
	.loh AdrpLdrGot	Lloh199, Lloh200
	.loh AdrpLdrGot	Lloh197, Lloh198
	.loh AdrpLdrGotLdr	Lloh235, Lloh236, Lloh237
	.loh AdrpLdrGotLdr	Lloh232, Lloh233, Lloh234
	.loh AdrpLdrGotLdr	Lloh241, Lloh242, Lloh243
	.loh AdrpLdrGotLdr	Lloh238, Lloh239, Lloh240
	.loh AdrpLdrGot	Lloh259, Lloh260
	.loh AdrpLdrGotLdr	Lloh256, Lloh257, Lloh258
	.loh AdrpLdrGotLdr	Lloh253, Lloh254, Lloh255
	.loh AdrpLdrGotLdr	Lloh250, Lloh251, Lloh252
	.loh AdrpLdrGotLdr	Lloh247, Lloh248, Lloh249
	.loh AdrpLdrGotLdr	Lloh244, Lloh245, Lloh246
	.loh AdrpLdrGot	Lloh264, Lloh265
	.loh AdrpLdrGotLdr	Lloh261, Lloh262, Lloh263
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Failed to runtime PM enable on DSI%d\n"

l_.str.2:                               ; @.str.2
	.asciz	"Failed to set phy clock to %ld: %d\n"

	.comm	_CTRL,4,2                       ; @CTRL
	.comm	_DSI_CTRL_SOFT_RESET_CFG,4,2    ; @DSI_CTRL_SOFT_RESET_CFG
	.comm	_CTRL_RESET_FIFOS,4,2           ; @CTRL_RESET_FIFOS
	.comm	_DSI_CTRL_HSDT_EOT_DISABLE,4,2  ; @DSI_CTRL_HSDT_EOT_DISABLE
	.comm	_DSI_CTRL_RX_LPDT_EOT_DISABLE,4,2 ; @DSI_CTRL_RX_LPDT_EOT_DISABLE
	.comm	_STAT,4,2                       ; @STAT
	.comm	_DSI_PHY_AFEC0_PTATADJ,4,2      ; @DSI_PHY_AFEC0_PTATADJ
	.comm	_DSI_PHY_AFEC0_CTATADJ,4,2      ; @DSI_PHY_AFEC0_CTATADJ
	.comm	_DSI0_PHY_AFEC0_PD_DLANE1,4,2   ; @DSI0_PHY_AFEC0_PD_DLANE1
	.comm	_MIPI_DSI_MODE_VIDEO,4,2        ; @MIPI_DSI_MODE_VIDEO
	.comm	_DSI0_PHY_AFEC0_RESET,4,2       ; @DSI0_PHY_AFEC0_RESET
	.comm	_PHY_AFEC0,4,2                  ; @PHY_AFEC0
	.comm	_PHY_AFEC1,4,2                  ; @PHY_AFEC1
	.comm	_DSI0_PHY_AFEC1_IDR_DLANE1,4,2  ; @DSI0_PHY_AFEC1_IDR_DLANE1
	.comm	_DSI0_PHY_AFEC1_IDR_DLANE0,4,2  ; @DSI0_PHY_AFEC1_IDR_DLANE0
	.comm	_DSI0_PHY_AFEC1_IDR_CLANE,4,2   ; @DSI0_PHY_AFEC1_IDR_CLANE
	.comm	_DSI1_PHY_AFEC0_IDR_CLANE,4,2   ; @DSI1_PHY_AFEC0_IDR_CLANE
	.comm	_DSI1_PHY_AFEC0_IDR_DLANE0,4,2  ; @DSI1_PHY_AFEC0_IDR_DLANE0
	.comm	_DSI1_PHY_AFEC0_IDR_DLANE1,4,2  ; @DSI1_PHY_AFEC0_IDR_DLANE1
	.comm	_DSI1_PHY_AFEC0_IDR_DLANE2,4,2  ; @DSI1_PHY_AFEC0_IDR_DLANE2
	.comm	_DSI1_PHY_AFEC0_IDR_DLANE3,4,2  ; @DSI1_PHY_AFEC0_IDR_DLANE3
	.comm	_DSI1_PHY_AFEC0_PD_DLANE3,4,2   ; @DSI1_PHY_AFEC0_PD_DLANE3
	.comm	_DSI1_PHY_AFEC0_PD_DLANE2,4,2   ; @DSI1_PHY_AFEC0_PD_DLANE2
	.comm	_DSI1_PHY_AFEC0_PD_DLANE1,4,2   ; @DSI1_PHY_AFEC0_PD_DLANE1
	.comm	_DSI1_PHY_AFEC0_RESET,4,2       ; @DSI1_PHY_AFEC0_RESET
l_.str.3:                               ; @.str.3
	.asciz	"Failed to turn on DSI escape clock: %d\n"

l_.str.4:                               ; @.str.4
	.asciz	"Failed to turn on DSI PLL: %d\n"

l_.str.5:                               ; @.str.5
	.asciz	"Failed to set pixel clock to %ldHz: %d\n"

l_.str.6:                               ; @.str.6
	.asciz	"Failed to turn on DSI pixel clock: %d\n"

	.comm	_HS_CLT0,4,2                    ; @HS_CLT0
	.comm	_DSI_HS_CLT0_CZERO,4,2          ; @DSI_HS_CLT0_CZERO
	.comm	_DSI_HS_CLT0_CPRE,4,2           ; @DSI_HS_CLT0_CPRE
	.comm	_DSI_HS_CLT0_CPREP,4,2          ; @DSI_HS_CLT0_CPREP
	.comm	_HS_CLT1,4,2                    ; @HS_CLT1
	.comm	_DSI_HS_CLT1_CTRAIL,4,2         ; @DSI_HS_CLT1_CTRAIL
	.comm	_DSI_HS_CLT1_CPOST,4,2          ; @DSI_HS_CLT1_CPOST
	.comm	_HS_CLT2,4,2                    ; @HS_CLT2
	.comm	_DSI_HS_CLT2_WUP,4,2            ; @DSI_HS_CLT2_WUP
	.comm	_HS_DLT3,4,2                    ; @HS_DLT3
	.comm	_DSI_HS_DLT3_EXIT,4,2           ; @DSI_HS_DLT3_EXIT
	.comm	_DSI_HS_DLT3_ZERO,4,2           ; @DSI_HS_DLT3_ZERO
	.comm	_DSI_HS_DLT3_PRE,4,2            ; @DSI_HS_DLT3_PRE
	.comm	_HS_DLT4,4,2                    ; @HS_DLT4
	.comm	_ESC_TIME_NS,4,2                ; @ESC_TIME_NS
	.comm	_DSI_HS_DLT4_LPX,4,2            ; @DSI_HS_DLT4_LPX
	.comm	_DSI_HS_DLT4_TRAIL,4,2          ; @DSI_HS_DLT4_TRAIL
	.comm	_DSI_HS_DLT4_ANLAT,4,2          ; @DSI_HS_DLT4_ANLAT
	.comm	_HS_DLT5,4,2                    ; @HS_DLT5
	.comm	_DSI_HS_DLT5_INIT,4,2           ; @DSI_HS_DLT5_INIT
	.comm	_HS_DLT6,4,2                    ; @HS_DLT6
	.comm	_DSI_HS_DLT6_TA_GET,4,2         ; @DSI_HS_DLT6_TA_GET
	.comm	_DSI_HS_DLT6_TA_SURE,4,2        ; @DSI_HS_DLT6_TA_SURE
	.comm	_DSI_HS_DLT6_TA_GO,4,2          ; @DSI_HS_DLT6_TA_GO
	.comm	_DSI_HS_DLT6_LP_LPX,4,2         ; @DSI_HS_DLT6_LP_LPX
	.comm	_HS_DLT7,4,2                    ; @HS_DLT7
	.comm	_DSI_HS_DLT7_LP_WUP,4,2         ; @DSI_HS_DLT7_LP_WUP
	.comm	_PHYC,4,2                       ; @PHYC
	.comm	_DSI_PHYC_DLANE0_ENABLE,4,2     ; @DSI_PHYC_DLANE0_ENABLE
	.comm	_DSI_PHYC_DLANE1_ENABLE,4,2     ; @DSI_PHYC_DLANE1_ENABLE
	.comm	_DSI_PHYC_DLANE2_ENABLE,4,2     ; @DSI_PHYC_DLANE2_ENABLE
	.comm	_DSI_PHYC_DLANE3_ENABLE,4,2     ; @DSI_PHYC_DLANE3_ENABLE
	.comm	_PHYC_CLANE_ENABLE,4,2          ; @PHYC_CLANE_ENABLE
	.comm	_MIPI_DSI_CLOCK_NON_CONTINUOUS,4,2 ; @MIPI_DSI_CLOCK_NON_CONTINUOUS
	.comm	_PHYC_HS_CLK_CONTINUOUS,4,2     ; @PHYC_HS_CLK_CONTINUOUS
	.comm	_DSI0_PHYC_ESC_CLK_LPDT,4,2     ; @DSI0_PHYC_ESC_CLK_LPDT
	.comm	_DSI1_PHYC_ESC_CLK_LPDT,4,2     ; @DSI1_PHYC_ESC_CLK_LPDT
	.comm	_DSI_CTRL_CAL_BYTE,4,2          ; @DSI_CTRL_CAL_BYTE
	.comm	_HSTX_TO_CNT,4,2                ; @HSTX_TO_CNT
	.comm	_LPRX_TO_CNT,4,2                ; @LPRX_TO_CNT
	.comm	_TA_TO_CNT,4,2                  ; @TA_TO_CNT
	.comm	_PR_TO_CNT,4,2                  ; @PR_TO_CNT
	.comm	_DISP1_CTRL,4,2                 ; @DISP1_CTRL
	.comm	_DSI_DISP1_PFORMAT_32BIT_LE,4,2 ; @DSI_DISP1_PFORMAT_32BIT_LE
	.comm	_DSI_DISP1_PFORMAT,4,2          ; @DSI_DISP1_PFORMAT
	.comm	_DSI_DISP1_ENABLE,4,2           ; @DSI_DISP1_ENABLE
	.comm	_DSI0_CTRL_CTRL0,4,2            ; @DSI0_CTRL_CTRL0
	.comm	_DSI1_CTRL_EN,4,2               ; @DSI1_CTRL_EN
	.comm	_DISP0_CTRL,4,2                 ; @DISP0_CTRL
	.comm	_DSI_DISP0_PIX_CLK_DIV,4,2      ; @DSI_DISP0_PIX_CLK_DIV
	.comm	_DSI_DISP0_PFORMAT,4,2          ; @DSI_DISP0_PFORMAT
	.comm	_DSI_DISP0_LP_STOP_PERFRAME,4,2 ; @DSI_DISP0_LP_STOP_PERFRAME
	.comm	_DSI_DISP0_LP_STOP_CTRL,4,2     ; @DSI_DISP0_LP_STOP_CTRL
	.comm	_DSI_DISP0_ST_END,4,2           ; @DSI_DISP0_ST_END
	.comm	_DSI_DISP0_ENABLE,4,2           ; @DSI_DISP0_ENABLE
	.comm	_DSI_DISP0_COMMAND_MODE,4,2     ; @DSI_DISP0_COMMAND_MODE
	.no_dead_strip	_vc4_dsi_encoder_enable
.subsections_via_symbols
