	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function xgpu_ai_set_mailbox_rcv_irq
_xgpu_ai_set_mailbox_rcv_irq:           ## @xgpu_ai_set_mailbox_rcv_irq
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %ebx
	movq	_NBIO@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movq	_mmBIF_BX_PF0_MAILBOX_INT_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	callq	_RREG32_NO_KIQ
	movq	_BIF_BX_PF0_MAILBOX_INT_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_VALID_INT_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_AMDGPU_IRQ_STATE_ENABLE@GOTPCREL(%rip), %rdi
	xorl	%ecx, %ecx
	cmpl	%ebx, (%rdi)
	sete	%cl
	movl	%eax, %edi
	callq	_REG_SET_FIELD
	movl	%eax, %ebx
	movl	(%r14), %edi
	movl	(%r15), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_WREG32_NO_KIQ
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_NBIO,4,2                       ## @NBIO
	.comm	_mmBIF_BX_PF0_MAILBOX_INT_CNTL,4,2 ## @mmBIF_BX_PF0_MAILBOX_INT_CNTL
	.comm	_BIF_BX_PF0_MAILBOX_INT_CNTL,4,2 ## @BIF_BX_PF0_MAILBOX_INT_CNTL
	.comm	_VALID_INT_EN,4,2               ## @VALID_INT_EN
	.comm	_AMDGPU_IRQ_STATE_ENABLE,4,2    ## @AMDGPU_IRQ_STATE_ENABLE
	.no_dead_strip	_xgpu_ai_set_mailbox_rcv_irq
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function xgpu_ai_set_mailbox_rcv_irq
_xgpu_ai_set_mailbox_rcv_irq:           ; @xgpu_ai_set_mailbox_rcv_irq
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x3
Lloh0:
	adrp	x20, _NBIO@GOTPAGE
Lloh1:
	ldr	x20, [x20, _NBIO@GOTPAGEOFF]
	ldr	w0, [x20]
Lloh2:
	adrp	x21, _mmBIF_BX_PF0_MAILBOX_INT_CNTL@GOTPAGE
Lloh3:
	ldr	x21, [x21, _mmBIF_BX_PF0_MAILBOX_INT_CNTL@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	bl	_RREG32_NO_KIQ
Lloh4:
	adrp	x8, _BIF_BX_PF0_MAILBOX_INT_CNTL@GOTPAGE
Lloh5:
	ldr	x8, [x8, _BIF_BX_PF0_MAILBOX_INT_CNTL@GOTPAGEOFF]
Lloh6:
	ldr	w1, [x8]
Lloh7:
	adrp	x8, _VALID_INT_EN@GOTPAGE
Lloh8:
	ldr	x8, [x8, _VALID_INT_EN@GOTPAGEOFF]
Lloh9:
	ldr	w2, [x8]
Lloh10:
	adrp	x8, _AMDGPU_IRQ_STATE_ENABLE@GOTPAGE
Lloh11:
	ldr	x8, [x8, _AMDGPU_IRQ_STATE_ENABLE@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	cmp	w8, w19
	cset	w3, eq
	bl	_REG_SET_FIELD
	mov	x19, x0
	ldr	w0, [x20]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x1, x19
	bl	_WREG32_NO_KIQ
	mov	w0, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_NBIO,4,2                       ; @NBIO
	.comm	_mmBIF_BX_PF0_MAILBOX_INT_CNTL,4,2 ; @mmBIF_BX_PF0_MAILBOX_INT_CNTL
	.comm	_BIF_BX_PF0_MAILBOX_INT_CNTL,4,2 ; @BIF_BX_PF0_MAILBOX_INT_CNTL
	.comm	_VALID_INT_EN,4,2               ; @VALID_INT_EN
	.comm	_AMDGPU_IRQ_STATE_ENABLE,4,2    ; @AMDGPU_IRQ_STATE_ENABLE
	.no_dead_strip	_xgpu_ai_set_mailbox_rcv_irq
.subsections_via_symbols
