	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_legacy_tv_write_fifo
_radeon_legacy_tv_write_fifo:           ## @radeon_legacy_tv_write_fifo
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	_RADEON_TV_HOST_WRITE_DATA@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%edx, %esi
	callq	_WREG32
	movq	_RADEON_TV_HOST_RD_WT_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movl	(%r15), %edi
	movq	_RADEON_HOST_FIFO_WT@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
	movl	%r14d, %esi
	callq	_WREG32
	xorl	%ebx, %ebx
	movq	_RADEON_HOST_FIFO_WT_ACK@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_1:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r15), %edi
	callq	_RREG32
	testl	%eax, (%r14)
	je	LBB0_3
## %bb.2:                               ##   in Loop: Header=BB0_1 Depth=1
	leal	1(%rbx), %eax
	cmpl	$9999, %ebx                     ## imm = 0x270F
	movl	%eax, %ebx
	jb	LBB0_1
LBB0_3:
	movl	(%r15), %edi
	xorl	%esi, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_TV_HOST_WRITE_DATA,4,2  ## @RADEON_TV_HOST_WRITE_DATA
	.comm	_RADEON_TV_HOST_RD_WT_CNTL,4,2  ## @RADEON_TV_HOST_RD_WT_CNTL
	.comm	_RADEON_HOST_FIFO_WT,4,2        ## @RADEON_HOST_FIFO_WT
	.comm	_RADEON_HOST_FIFO_WT_ACK,4,2    ## @RADEON_HOST_FIFO_WT_ACK
	.no_dead_strip	_radeon_legacy_tv_write_fifo
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_legacy_tv_write_fifo
_radeon_legacy_tv_write_fifo:           ; @radeon_legacy_tv_write_fifo
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x1
Lloh0:
	adrp	x8, _RADEON_TV_HOST_WRITE_DATA@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_TV_HOST_WRITE_DATA@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	mov	x1, x2
	bl	_WREG32
Lloh3:
	adrp	x20, _RADEON_TV_HOST_RD_WT_CNTL@GOTPAGE
Lloh4:
	ldr	x20, [x20, _RADEON_TV_HOST_RD_WT_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	mov	x1, x19
	bl	_WREG32
	ldr	w0, [x20]
Lloh5:
	adrp	x8, _RADEON_HOST_FIFO_WT@GOTPAGE
Lloh6:
	ldr	x8, [x8, _RADEON_HOST_FIFO_WT@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	orr	w1, w8, w19
	bl	_WREG32
	mov	w19, #0
Lloh8:
	adrp	x21, _RADEON_HOST_FIFO_WT_ACK@GOTPAGE
Lloh9:
	ldr	x21, [x21, _RADEON_HOST_FIFO_WT_ACK@GOTPAGEOFF]
	mov	w22, #9999
LBB0_1:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x20]
	bl	_RREG32
	ldr	w8, [x21]
	and	w8, w8, w0
	cmp	w8, #0
	ccmp	w19, w22, #2, ne
	add	w19, w19, #1
	b.lo	LBB0_1
; %bb.2:
	ldr	w0, [x20]
	mov	w1, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_TV_HOST_WRITE_DATA,4,2  ; @RADEON_TV_HOST_WRITE_DATA
	.comm	_RADEON_TV_HOST_RD_WT_CNTL,4,2  ; @RADEON_TV_HOST_RD_WT_CNTL
	.comm	_RADEON_HOST_FIFO_WT,4,2        ; @RADEON_HOST_FIFO_WT
	.comm	_RADEON_HOST_FIFO_WT_ACK,4,2    ; @RADEON_HOST_FIFO_WT_ACK
	.no_dead_strip	_radeon_legacy_tv_write_fifo
.subsections_via_symbols
