	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v7_0_enable_mgcg
_gfx_v7_0_enable_mgcg:                  ## @gfx_v7_0_enable_mgcg
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	testl	%esi, %esi
	je	LBB0_14
## %bb.1:
	movl	(%r12), %eax
	movq	_AMD_CG_SUPPORT_GFX_MGCG@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_14
## %bb.2:
	movq	_AMD_CG_SUPPORT_GFX_MGLS@GOTPCREL(%rip), %r13
	testl	%eax, (%r13)
	je	LBB0_6
## %bb.3:
	movq	_AMD_CG_SUPPORT_GFX_CP_LS@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_6
## %bb.4:
	movq	_mmCP_MEM_SLP_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	%eax, %esi
	cmpl	%esi, %eax
	je	LBB0_6
## %bb.5:
	movl	(%rbx), %edi
	callq	_WREG32
LBB0_6:
	movq	_mmRLC_CGTT_MGCG_OVERRIDE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movl	%eax, %esi
	andl	$-4, %esi
	orl	$1, %esi
	cmpl	%esi, %eax
	je	LBB0_8
## %bb.7:
	movl	(%rbx), %edi
	callq	_WREG32
LBB0_8:
	movq	%r12, %rdi
	callq	_gfx_v7_0_halt_rlc
	movl	%eax, %r14d
	leaq	4(%r12), %r15
	movq	%r15, %rdi
	callq	_mutex_lock
	movq	%r12, %rdi
	movl	$-1, %esi
	movl	$-1, %edx
	movl	$-1, %ecx
	callq	_gfx_v7_0_select_se_sh
	movq	_mmRLC_SERDES_WR_CU_MASTER_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$-1, %esi
	callq	_WREG32
	movq	_mmRLC_SERDES_WR_NONCU_MASTER_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$-1, %esi
	callq	_WREG32
	movq	_RLC_SERDES_WR_CTRL__BPM_ADDR_MASK@GOTPCREL(%rip), %rax
	movq	_RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movq	_mmRLC_SERDES_WR_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32
	movq	%r15, %rdi
	callq	_mutex_unlock
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_gfx_v7_0_update_rlc
	movq	_AMD_CG_SUPPORT_GFX_CGTS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r12)
	je	LBB0_23
## %bb.9:
	movq	_mmCGTS_SM_CTRL_REG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_CGTS_SM_CTRL_REG__SM_MODE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	_CGTS_SM_CTRL_REG__SM_MODE__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %esi
	shll	%cl, %esi
	orl	%edx, %esi
	movq	_CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_CGTS_SM_CTRL_REG__OVERRIDE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%esi, %ecx
	movl	(%r12), %edx
	testl	%edx, (%r13)
	je	LBB0_12
## %bb.10:
	movq	_AMD_CG_SUPPORT_GFX_CGTS_LS@GOTPCREL(%rip), %rsi
	testl	%edx, (%rsi)
	je	LBB0_12
## %bb.11:
	movq	_CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	notl	%edx
	andl	%edx, %ecx
LBB0_12:
	movq	_CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	notl	%edx
	andl	%ecx, %edx
	movq	_CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK@GOTPCREL(%rip), %rdi
	movq	_CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$150, %esi
	shll	%cl, %esi
	orl	(%rdi), %edx
	orl	%edx, %esi
	cmpl	%esi, %eax
	jne	LBB0_13
LBB0_23:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_14:
	movq	_mmRLC_CGTT_MGCG_OVERRIDE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movl	%eax, %esi
	orl	$3, %esi
	cmpl	%esi, %eax
	je	LBB0_16
## %bb.15:
	movl	(%rbx), %edi
	callq	_WREG32
LBB0_16:
	movq	_mmRLC_MEM_SLP_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%eax, %ecx
	je	LBB0_18
## %bb.17:
	notl	%ecx
	andl	%ecx, %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
LBB0_18:
	movq	_mmCP_MEM_SLP_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%eax, %ecx
	je	LBB0_20
## %bb.19:
	notl	%ecx
	andl	%ecx, %eax
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
LBB0_20:
	movq	_mmCGTS_SM_CTRL_REG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_CGTS_SM_CTRL_REG__OVERRIDE_MASK@GOTPCREL(%rip), %rcx
	movq	_CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK@GOTPCREL(%rip), %rdx
	movl	(%rcx), %esi
	orl	%eax, %esi
	orl	(%rdx), %esi
	cmpl	%esi, %eax
	je	LBB0_22
## %bb.21:
	movl	(%rbx), %edi
	callq	_WREG32
LBB0_22:
	movq	%r12, %rdi
	callq	_gfx_v7_0_halt_rlc
	movl	%eax, %r14d
	leaq	4(%r12), %rbx
	movq	%rbx, %rdi
	callq	_mutex_lock
	movq	%r12, %rdi
	movl	$-1, %esi
	movl	$-1, %edx
	movl	$-1, %ecx
	callq	_gfx_v7_0_select_se_sh
	movq	_mmRLC_SERDES_WR_CU_MASTER_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$-1, %esi
	callq	_WREG32
	movq	_mmRLC_SERDES_WR_NONCU_MASTER_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$-1, %esi
	callq	_WREG32
	movq	_RLC_SERDES_WR_CTRL__BPM_ADDR_MASK@GOTPCREL(%rip), %rax
	movq	_RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movq	_mmRLC_SERDES_WR_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32
	movq	%rbx, %rdi
	callq	_mutex_unlock
	movq	%r12, %rdi
	movl	%r14d, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_gfx_v7_0_update_rlc            ## TAILCALL
LBB0_13:
	movl	(%rbx), %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_CG_SUPPORT_GFX_MGCG,4,2    ## @AMD_CG_SUPPORT_GFX_MGCG
	.comm	_AMD_CG_SUPPORT_GFX_MGLS,4,2    ## @AMD_CG_SUPPORT_GFX_MGLS
	.comm	_AMD_CG_SUPPORT_GFX_CP_LS,4,2   ## @AMD_CG_SUPPORT_GFX_CP_LS
	.comm	_mmCP_MEM_SLP_CNTL,4,2          ## @mmCP_MEM_SLP_CNTL
	.comm	_CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK,4,2 ## @CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK
	.comm	_mmRLC_CGTT_MGCG_OVERRIDE,4,2   ## @mmRLC_CGTT_MGCG_OVERRIDE
	.comm	_mmRLC_SERDES_WR_CU_MASTER_MASK,4,2 ## @mmRLC_SERDES_WR_CU_MASTER_MASK
	.comm	_mmRLC_SERDES_WR_NONCU_MASTER_MASK,4,2 ## @mmRLC_SERDES_WR_NONCU_MASTER_MASK
	.comm	_RLC_SERDES_WR_CTRL__BPM_ADDR_MASK,4,2 ## @RLC_SERDES_WR_CTRL__BPM_ADDR_MASK
	.comm	_RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK,4,2 ## @RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK
	.comm	_mmRLC_SERDES_WR_CTRL,4,2       ## @mmRLC_SERDES_WR_CTRL
	.comm	_AMD_CG_SUPPORT_GFX_CGTS,4,2    ## @AMD_CG_SUPPORT_GFX_CGTS
	.comm	_mmCGTS_SM_CTRL_REG,4,2         ## @mmCGTS_SM_CTRL_REG
	.comm	_CGTS_SM_CTRL_REG__SM_MODE_MASK,4,2 ## @CGTS_SM_CTRL_REG__SM_MODE_MASK
	.comm	_CGTS_SM_CTRL_REG__SM_MODE__SHIFT,4,2 ## @CGTS_SM_CTRL_REG__SM_MODE__SHIFT
	.comm	_CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK,4,2 ## @CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK
	.comm	_CGTS_SM_CTRL_REG__OVERRIDE_MASK,4,2 ## @CGTS_SM_CTRL_REG__OVERRIDE_MASK
	.comm	_AMD_CG_SUPPORT_GFX_CGTS_LS,4,2 ## @AMD_CG_SUPPORT_GFX_CGTS_LS
	.comm	_CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK,4,2 ## @CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK
	.comm	_CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK,4,2 ## @CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK
	.comm	_CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK,4,2 ## @CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK
	.comm	_CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT,4,2 ## @CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT
	.comm	_mmRLC_MEM_SLP_CNTL,4,2         ## @mmRLC_MEM_SLP_CNTL
	.comm	_RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK,4,2 ## @RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK
	.comm	_RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK,4,2 ## @RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK
	.no_dead_strip	_gfx_v7_0_enable_mgcg
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v7_0_enable_mgcg
_gfx_v7_0_enable_mgcg:                  ; @gfx_v7_0_enable_mgcg
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	cbz	w1, LBB0_14
; %bb.1:
	ldr	w8, [x19]
Lloh0:
	adrp	x9, _AMD_CG_SUPPORT_GFX_MGCG@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_CG_SUPPORT_GFX_MGCG@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_14
; %bb.2:
Lloh3:
	adrp	x22, _AMD_CG_SUPPORT_GFX_MGLS@GOTPAGE
Lloh4:
	ldr	x22, [x22, _AMD_CG_SUPPORT_GFX_MGLS@GOTPAGEOFF]
	ldr	w9, [x22]
	tst	w9, w8
	b.eq	LBB0_6
; %bb.3:
Lloh5:
	adrp	x9, _AMD_CG_SUPPORT_GFX_CP_LS@GOTPAGE
Lloh6:
	ldr	x9, [x9, _AMD_CG_SUPPORT_GFX_CP_LS@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_6
; %bb.4:
Lloh8:
	adrp	x20, _mmCP_MEM_SLP_CNTL@GOTPAGE
Lloh9:
	ldr	x20, [x20, _mmCP_MEM_SLP_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh10:
	adrp	x8, _CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPAGE
Lloh11:
	ldr	x8, [x8, _CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	orr	w1, w8, w0
	cmp	w0, w1
	b.eq	LBB0_6
; %bb.5:
	ldr	w0, [x20]
	bl	_WREG32
LBB0_6:
Lloh13:
	adrp	x20, _mmRLC_CGTT_MGCG_OVERRIDE@GOTPAGE
Lloh14:
	ldr	x20, [x20, _mmRLC_CGTT_MGCG_OVERRIDE@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	and	w8, w0, #0xfffffffc
	orr	w1, w8, #0x1
	cmp	w0, w1
	b.eq	LBB0_8
; %bb.7:
	ldr	w0, [x20]
	bl	_WREG32
LBB0_8:
	mov	x0, x19
	bl	_gfx_v7_0_halt_rlc
	mov	x20, x0
	add	x21, x19, #4
	mov	x0, x21
	bl	_mutex_lock
	mov	x0, x19
	mov	w1, #-1
	mov	w2, #-1
	mov	w3, #-1
	bl	_gfx_v7_0_select_se_sh
Lloh15:
	adrp	x8, _mmRLC_SERDES_WR_CU_MASTER_MASK@GOTPAGE
Lloh16:
	ldr	x8, [x8, _mmRLC_SERDES_WR_CU_MASTER_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	mov	w1, #-1
	bl	_WREG32
Lloh18:
	adrp	x8, _mmRLC_SERDES_WR_NONCU_MASTER_MASK@GOTPAGE
Lloh19:
	ldr	x8, [x8, _mmRLC_SERDES_WR_NONCU_MASTER_MASK@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
	mov	w1, #-1
	bl	_WREG32
Lloh21:
	adrp	x8, _RLC_SERDES_WR_CTRL__BPM_ADDR_MASK@GOTPAGE
Lloh22:
	ldr	x8, [x8, _RLC_SERDES_WR_CTRL__BPM_ADDR_MASK@GOTPAGEOFF]
Lloh23:
	adrp	x9, _RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK@GOTPAGE
Lloh24:
	ldr	x9, [x9, _RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
Lloh26:
	ldr	w9, [x9]
	orr	w1, w9, w8
Lloh27:
	adrp	x8, _mmRLC_SERDES_WR_CTRL@GOTPAGE
Lloh28:
	ldr	x8, [x8, _mmRLC_SERDES_WR_CTRL@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	bl	_WREG32
	mov	x0, x21
	bl	_mutex_unlock
	mov	x0, x19
	mov	x1, x20
	bl	_gfx_v7_0_update_rlc
	ldr	w8, [x19]
Lloh30:
	adrp	x9, _AMD_CG_SUPPORT_GFX_CGTS@GOTPAGE
Lloh31:
	ldr	x9, [x9, _AMD_CG_SUPPORT_GFX_CGTS@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_13
; %bb.9:
Lloh33:
	adrp	x20, _mmCGTS_SM_CTRL_REG@GOTPAGE
Lloh34:
	ldr	x20, [x20, _mmCGTS_SM_CTRL_REG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh35:
	adrp	x8, _CGTS_SM_CTRL_REG__SM_MODE_MASK@GOTPAGE
Lloh36:
	ldr	x8, [x8, _CGTS_SM_CTRL_REG__SM_MODE_MASK@GOTPAGEOFF]
Lloh37:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh38:
	adrp	x9, _CGTS_SM_CTRL_REG__SM_MODE__SHIFT@GOTPAGE
Lloh39:
	ldr	x9, [x9, _CGTS_SM_CTRL_REG__SM_MODE__SHIFT@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
	mov	w10, #2
	lsl	w9, w10, w9
	orr	w8, w9, w8
Lloh41:
	adrp	x9, _CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK@GOTPAGE
Lloh42:
	ldr	x9, [x9, _CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
Lloh44:
	adrp	x10, _CGTS_SM_CTRL_REG__OVERRIDE_MASK@GOTPAGE
Lloh45:
	ldr	x10, [x10, _CGTS_SM_CTRL_REG__OVERRIDE_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh46:
	ldr	w9, [x10]
	bic	w8, w8, w9
	ldr	w9, [x19]
	ldr	w10, [x22]
	tst	w10, w9
	b.eq	LBB0_12
; %bb.10:
Lloh47:
	adrp	x10, _AMD_CG_SUPPORT_GFX_CGTS_LS@GOTPAGE
Lloh48:
	ldr	x10, [x10, _AMD_CG_SUPPORT_GFX_CGTS_LS@GOTPAGEOFF]
Lloh49:
	ldr	w10, [x10]
	tst	w10, w9
	b.eq	LBB0_12
; %bb.11:
Lloh50:
	adrp	x9, _CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK@GOTPAGE
Lloh51:
	ldr	x9, [x9, _CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK@GOTPAGEOFF]
Lloh52:
	ldr	w9, [x9]
	bic	w8, w8, w9
LBB0_12:
Lloh53:
	adrp	x9, _CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK@GOTPAGE
Lloh54:
	ldr	x9, [x9, _CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK@GOTPAGEOFF]
Lloh55:
	ldr	w9, [x9]
	bic	w8, w8, w9
Lloh56:
	adrp	x9, _CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK@GOTPAGE
Lloh57:
	ldr	x9, [x9, _CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK@GOTPAGEOFF]
Lloh58:
	ldr	w9, [x9]
Lloh59:
	adrp	x10, _CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT@GOTPAGE
Lloh60:
	ldr	x10, [x10, _CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh61:
	ldr	w9, [x10]
	mov	w10, #150
	lsl	w9, w10, w9
	orr	w1, w8, w9
	cmp	w0, w1
	b.ne	LBB0_23
LBB0_13:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_14:
Lloh62:
	adrp	x20, _mmRLC_CGTT_MGCG_OVERRIDE@GOTPAGE
Lloh63:
	ldr	x20, [x20, _mmRLC_CGTT_MGCG_OVERRIDE@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	orr	w1, w0, #0x3
	cmp	w0, w1
	b.eq	LBB0_16
; %bb.15:
	ldr	w0, [x20]
	bl	_WREG32
LBB0_16:
Lloh64:
	adrp	x20, _mmRLC_MEM_SLP_CNTL@GOTPAGE
Lloh65:
	ldr	x20, [x20, _mmRLC_MEM_SLP_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh66:
	adrp	x8, _RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK@GOTPAGE
Lloh67:
	ldr	x8, [x8, _RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh68:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_18
; %bb.17:
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32
LBB0_18:
Lloh69:
	adrp	x20, _mmCP_MEM_SLP_CNTL@GOTPAGE
Lloh70:
	ldr	x20, [x20, _mmCP_MEM_SLP_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh71:
	adrp	x8, _CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPAGE
Lloh72:
	ldr	x8, [x8, _CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK@GOTPAGEOFF]
Lloh73:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_20
; %bb.19:
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32
LBB0_20:
Lloh74:
	adrp	x20, _mmCGTS_SM_CTRL_REG@GOTPAGE
Lloh75:
	ldr	x20, [x20, _mmCGTS_SM_CTRL_REG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh76:
	adrp	x8, _CGTS_SM_CTRL_REG__OVERRIDE_MASK@GOTPAGE
Lloh77:
	ldr	x8, [x8, _CGTS_SM_CTRL_REG__OVERRIDE_MASK@GOTPAGEOFF]
Lloh78:
	ldr	w8, [x8]
Lloh79:
	adrp	x9, _CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK@GOTPAGE
Lloh80:
	ldr	x9, [x9, _CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK@GOTPAGEOFF]
Lloh81:
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w1, w8, w9
	cmp	w0, w1
	b.eq	LBB0_22
; %bb.21:
	ldr	w0, [x20]
	bl	_WREG32
LBB0_22:
	mov	x0, x19
	bl	_gfx_v7_0_halt_rlc
	mov	x20, x0
	add	x21, x19, #4
	mov	x0, x21
	bl	_mutex_lock
	mov	x0, x19
	mov	w1, #-1
	mov	w2, #-1
	mov	w3, #-1
	bl	_gfx_v7_0_select_se_sh
Lloh82:
	adrp	x8, _mmRLC_SERDES_WR_CU_MASTER_MASK@GOTPAGE
Lloh83:
	ldr	x8, [x8, _mmRLC_SERDES_WR_CU_MASTER_MASK@GOTPAGEOFF]
Lloh84:
	ldr	w0, [x8]
	mov	w1, #-1
	bl	_WREG32
Lloh85:
	adrp	x8, _mmRLC_SERDES_WR_NONCU_MASTER_MASK@GOTPAGE
Lloh86:
	ldr	x8, [x8, _mmRLC_SERDES_WR_NONCU_MASTER_MASK@GOTPAGEOFF]
Lloh87:
	ldr	w0, [x8]
	mov	w1, #-1
	bl	_WREG32
Lloh88:
	adrp	x8, _RLC_SERDES_WR_CTRL__BPM_ADDR_MASK@GOTPAGE
Lloh89:
	ldr	x8, [x8, _RLC_SERDES_WR_CTRL__BPM_ADDR_MASK@GOTPAGEOFF]
Lloh90:
	adrp	x9, _RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK@GOTPAGE
Lloh91:
	ldr	x9, [x9, _RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK@GOTPAGEOFF]
Lloh92:
	ldr	w8, [x8]
Lloh93:
	ldr	w9, [x9]
	orr	w1, w9, w8
Lloh94:
	adrp	x8, _mmRLC_SERDES_WR_CTRL@GOTPAGE
Lloh95:
	ldr	x8, [x8, _mmRLC_SERDES_WR_CTRL@GOTPAGEOFF]
Lloh96:
	ldr	w0, [x8]
	bl	_WREG32
	mov	x0, x21
	bl	_mutex_unlock
	mov	x0, x19
	mov	x1, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_gfx_v7_0_update_rlc
LBB0_23:
	ldr	w0, [x20]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh25
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGot	Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGot	Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGot	Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGot	Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh92
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_CG_SUPPORT_GFX_MGCG,4,2    ; @AMD_CG_SUPPORT_GFX_MGCG
	.comm	_AMD_CG_SUPPORT_GFX_MGLS,4,2    ; @AMD_CG_SUPPORT_GFX_MGLS
	.comm	_AMD_CG_SUPPORT_GFX_CP_LS,4,2   ; @AMD_CG_SUPPORT_GFX_CP_LS
	.comm	_mmCP_MEM_SLP_CNTL,4,2          ; @mmCP_MEM_SLP_CNTL
	.comm	_CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK,4,2 ; @CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK
	.comm	_mmRLC_CGTT_MGCG_OVERRIDE,4,2   ; @mmRLC_CGTT_MGCG_OVERRIDE
	.comm	_mmRLC_SERDES_WR_CU_MASTER_MASK,4,2 ; @mmRLC_SERDES_WR_CU_MASTER_MASK
	.comm	_mmRLC_SERDES_WR_NONCU_MASTER_MASK,4,2 ; @mmRLC_SERDES_WR_NONCU_MASTER_MASK
	.comm	_RLC_SERDES_WR_CTRL__BPM_ADDR_MASK,4,2 ; @RLC_SERDES_WR_CTRL__BPM_ADDR_MASK
	.comm	_RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK,4,2 ; @RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK
	.comm	_mmRLC_SERDES_WR_CTRL,4,2       ; @mmRLC_SERDES_WR_CTRL
	.comm	_AMD_CG_SUPPORT_GFX_CGTS,4,2    ; @AMD_CG_SUPPORT_GFX_CGTS
	.comm	_mmCGTS_SM_CTRL_REG,4,2         ; @mmCGTS_SM_CTRL_REG
	.comm	_CGTS_SM_CTRL_REG__SM_MODE_MASK,4,2 ; @CGTS_SM_CTRL_REG__SM_MODE_MASK
	.comm	_CGTS_SM_CTRL_REG__SM_MODE__SHIFT,4,2 ; @CGTS_SM_CTRL_REG__SM_MODE__SHIFT
	.comm	_CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK,4,2 ; @CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK
	.comm	_CGTS_SM_CTRL_REG__OVERRIDE_MASK,4,2 ; @CGTS_SM_CTRL_REG__OVERRIDE_MASK
	.comm	_AMD_CG_SUPPORT_GFX_CGTS_LS,4,2 ; @AMD_CG_SUPPORT_GFX_CGTS_LS
	.comm	_CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK,4,2 ; @CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK
	.comm	_CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK,4,2 ; @CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK
	.comm	_CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK,4,2 ; @CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK
	.comm	_CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT,4,2 ; @CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT
	.comm	_mmRLC_MEM_SLP_CNTL,4,2         ; @mmRLC_MEM_SLP_CNTL
	.comm	_RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK,4,2 ; @RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK
	.comm	_RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK,4,2 ; @RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK
	.no_dead_strip	_gfx_v7_0_enable_mgcg
.subsections_via_symbols
