	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vce_v4_0_sw_init
_vce_v4_0_sw_init:                      ## @vce_v4_0_sw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	_SOC15_IH_CLIENTID_VCE0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	4(%rdi), %r14
	movl	$167, %edx
	movq	%r14, %rcx
	callq	_amdgpu_irq_add_id
	testl	%eax, %eax
	jne	LBB0_19
## %bb.1:
	movq	_VCE_V4_0_STACK_SIZE@GOTPCREL(%rip), %rax
	movq	_VCE_V4_0_DATA_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	addl	(%rax), %esi
	movq	40(%r12), %rcx
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rbx
	xorl	%eax, %eax
	cmpq	(%rbx), %rcx
	je	LBB0_3
## %bb.2:
	movq	_VCE_V4_0_FW_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_3:
	addl	%eax, %esi
	movq	%r12, %rdi
	callq	_amdgpu_vce_sw_init
	testl	%eax, %eax
	je	LBB0_4
LBB0_19:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_4:
	movq	40(%r12), %rax
	cmpq	(%rbx), %rax
	jne	LBB0_8
## %bb.5:
	movl	28(%r12), %edi
	callq	_amdgpu_bo_size
	movq	_GFP_KERNEL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_kvmalloc
	movl	%eax, 24(%r12)
	testl	%eax, %eax
	je	LBB0_6
## %bb.7:
	movq	16(%r12), %rax
	movq	56(%r12), %rcx
	movq	(%rax), %rdx
	movq	_AMDGPU_UCODE_ID_VCE@GOTPCREL(%rip), %rsi
	movq	(%rsi), %rbx
	movq	%rbx, %rdi
	shlq	$4, %rdi
	movq	%rbx, (%rcx,%rdi)
	movq	(%rsi), %rsi
	shlq	$4, %rsi
	movq	%rax, 8(%rcx,%rsi)
	movl	(%rdx), %edi
	callq	_le32_to_cpu
	movq	_PAGE_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_ALIGN
	addl	%eax, 48(%r12)
	leaq	L_.str(%rip), %rdi
	callq	_DRM_INFO
	jmp	LBB0_9
LBB0_8:
	movq	%r12, %rdi
	callq	_amdgpu_vce_resume
	testl	%eax, %eax
	jne	LBB0_19
LBB0_9:
	cmpl	$0, (%r12)
	jle	LBB0_18
## %bb.10:
	xorl	%r15d, %r15d
	xorl	%ebx, %ebx
	movq	%r14, -48(%rbp)                 ## 8-byte Spill
	.p2align	4, 0x90
LBB0_12:                                ## =>This Inner Loop Header: Depth=1
	movq	8(%r12), %r14
	leaq	(%r14,%r15), %r13
	movl	8(%r14,%r15), %edi
	leaq	L_.str.1(%rip), %rsi
	movl	%ebx, %edx
	callq	_sprintf
	movq	%r12, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_17
## %bb.13:                              ##   in Loop: Header=BB0_12 Depth=1
	movl	$1, (%r14,%r15)
	testq	%r15, %r15
	je	LBB0_14
## %bb.15:                              ##   in Loop: Header=BB0_12 Depth=1
	movl	36(%r12), %eax
	addl	%eax, %eax
	incl	%eax
	jmp	LBB0_16
LBB0_14:                                ##   in Loop: Header=BB0_12 Depth=1
	movl	32(%r12), %eax
	addl	%eax, %eax
LBB0_16:                                ##   in Loop: Header=BB0_12 Depth=1
	movl	%eax, 4(%r14,%r15)
LBB0_17:                                ##   in Loop: Header=BB0_12 Depth=1
	movq	%r12, %rdi
	movq	%r13, %rsi
	movl	$512, %edx                      ## imm = 0x200
	movq	-48(%rbp), %rcx                 ## 8-byte Reload
	xorl	%r8d, %r8d
	callq	_amdgpu_ring_init
	testl	%eax, %eax
	jne	LBB0_19
## %bb.11:                              ##   in Loop: Header=BB0_12 Depth=1
	incq	%rbx
	movslq	(%r12), %rax
	addq	$12, %r15
	cmpq	%rax, %rbx
	jl	LBB0_12
LBB0_18:
	movq	%r12, %rdi
	callq	_amdgpu_vce_entity_init
	testl	%eax, %eax
	jne	LBB0_19
## %bb.20:
	movq	%r12, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_virt_alloc_mm_table     ## TAILCALL
LBB0_6:
	movq	_ENOMEM@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_19
	.cfi_endproc
                                        ## -- End function
	.comm	_SOC15_IH_CLIENTID_VCE0,4,2     ## @SOC15_IH_CLIENTID_VCE0
	.comm	_VCE_V4_0_STACK_SIZE,4,2        ## @VCE_V4_0_STACK_SIZE
	.comm	_VCE_V4_0_DATA_SIZE,4,2         ## @VCE_V4_0_DATA_SIZE
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_VCE_V4_0_FW_SIZE,8,3           ## @VCE_V4_0_FW_SIZE
	.comm	_GFP_KERNEL,4,2                 ## @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ## @ENOMEM
	.comm	_AMDGPU_UCODE_ID_VCE,8,3        ## @AMDGPU_UCODE_ID_VCE
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"PSP loading VCE firmware\n"

L_.str.1:                               ## @.str.1
	.asciz	"vce%d"

	.no_dead_strip	_vce_v4_0_sw_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vce_v4_0_sw_init
_vce_v4_0_sw_init:                      ; @vce_v4_0_sw_init
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
Lloh0:
	adrp	x8, _SOC15_IH_CLIENTID_VCE0@GOTPAGE
Lloh1:
	ldr	x8, [x8, _SOC15_IH_CLIENTID_VCE0@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	add	x20, x0, #4
	mov	w2, #167
	mov	x3, x20
	bl	_amdgpu_irq_add_id
	cbnz	w0, LBB0_2
; %bb.1:
Lloh3:
	adrp	x8, _VCE_V4_0_STACK_SIZE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _VCE_V4_0_STACK_SIZE@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
Lloh6:
	adrp	x9, _VCE_V4_0_DATA_SIZE@GOTPAGE
Lloh7:
	ldr	x9, [x9, _VCE_V4_0_DATA_SIZE@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	ldr	x10, [x19, #40]
Lloh9:
	adrp	x21, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh10:
	ldr	x21, [x21, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh11:
	adrp	x11, _VCE_V4_0_FW_SIZE@GOTPAGE
Lloh12:
	ldr	x11, [x11, _VCE_V4_0_FW_SIZE@GOTPAGEOFF]
	ldr	x12, [x21]
Lloh13:
	ldr	w11, [x11]
	cmp	x10, x12
	csel	w10, wzr, w11, eq
	add	w8, w9, w8
	add	w1, w8, w10
	mov	x0, x19
	bl	_amdgpu_vce_sw_init
	cbz	w0, LBB0_3
LBB0_2:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_3:
	ldr	x8, [x19, #40]
	ldr	x9, [x21]
	cmp	x8, x9
	b.ne	LBB0_6
; %bb.4:
	ldr	w0, [x19, #28]
	bl	_amdgpu_bo_size
Lloh14:
	adrp	x8, _GFP_KERNEL@GOTPAGE
Lloh15:
	ldr	x8, [x8, _GFP_KERNEL@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
	bl	_kvmalloc
	str	w0, [x19, #24]
	cbz	w0, LBB0_18
; %bb.5:
	ldr	x8, [x19, #16]
	ldr	x9, [x8]
Lloh17:
	adrp	x10, _AMDGPU_UCODE_ID_VCE@GOTPAGE
Lloh18:
	ldr	x10, [x10, _AMDGPU_UCODE_ID_VCE@GOTPAGEOFF]
	ldr	x11, [x10]
	ldr	x12, [x19, #56]
	lsl	x13, x11, #4
	str	x11, [x12, x13]
	ldr	x10, [x10]
	add	x10, x12, x10, lsl #4
	str	x8, [x10, #8]
	ldr	w0, [x9]
	bl	_le32_to_cpu
Lloh19:
	adrp	x8, _PAGE_SIZE@GOTPAGE
Lloh20:
	ldr	x8, [x8, _PAGE_SIZE@GOTPAGEOFF]
Lloh21:
	ldr	w1, [x8]
	bl	_ALIGN
	ldr	w8, [x19, #48]
	add	w8, w8, w0
	str	w8, [x19, #48]
Lloh22:
	adrp	x0, l_.str@PAGE
Lloh23:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_INFO
	b	LBB0_7
LBB0_6:
	mov	x0, x19
	bl	_amdgpu_vce_resume
	cbnz	w0, LBB0_2
LBB0_7:
	ldr	w8, [x19]
	cmp	w8, #1
	b.lt	LBB0_16
; %bb.8:
	mov	x24, #0
	mov	x21, #0
	mov	w25, #1
Lloh24:
	adrp	x22, l_.str.1@PAGE
Lloh25:
	add	x22, x22, l_.str.1@PAGEOFF
LBB0_9:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x26, [x19, #8]
	add	x23, x26, x24
	ldr	w0, [x23, #8]
	mov	x1, x22
	mov	x2, x21
	bl	_sprintf
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_14
; %bb.10:                               ;   in Loop: Header=BB0_9 Depth=1
	str	w25, [x26, x24]
	cbz	x24, LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_9 Depth=1
	ldr	w9, [x19, #36]
	mov	w8, #1
	bfi	w8, w9, #1, #31
	b	LBB0_13
LBB0_12:                                ;   in Loop: Header=BB0_9 Depth=1
	ldr	w8, [x19, #32]
	lsl	w8, w8, #1
LBB0_13:                                ;   in Loop: Header=BB0_9 Depth=1
	add	x9, x26, x24
	str	w8, [x9, #4]
LBB0_14:                                ;   in Loop: Header=BB0_9 Depth=1
	mov	x0, x19
	mov	x1, x23
	mov	w2, #512
	mov	x3, x20
	mov	w4, #0
	bl	_amdgpu_ring_init
	cbnz	w0, LBB0_2
; %bb.15:                               ;   in Loop: Header=BB0_9 Depth=1
	add	x21, x21, #1
	ldrsw	x8, [x19]
	add	x24, x24, #12
	cmp	x21, x8
	b.lt	LBB0_9
LBB0_16:
	mov	x0, x19
	bl	_amdgpu_vce_entity_init
	cbnz	w0, LBB0_2
; %bb.17:
	mov	x0, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_amdgpu_virt_alloc_mm_table
LBB0_18:
Lloh26:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh27:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_2
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpAdd	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpAdd	Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.cfi_endproc
                                        ; -- End function
	.comm	_SOC15_IH_CLIENTID_VCE0,4,2     ; @SOC15_IH_CLIENTID_VCE0
	.comm	_VCE_V4_0_STACK_SIZE,4,2        ; @VCE_V4_0_STACK_SIZE
	.comm	_VCE_V4_0_DATA_SIZE,4,2         ; @VCE_V4_0_DATA_SIZE
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_VCE_V4_0_FW_SIZE,8,3           ; @VCE_V4_0_FW_SIZE
	.comm	_GFP_KERNEL,4,2                 ; @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ; @ENOMEM
	.comm	_AMDGPU_UCODE_ID_VCE,8,3        ; @AMDGPU_UCODE_ID_VCE
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"PSP loading VCE firmware\n"

l_.str.1:                               ; @.str.1
	.asciz	"vce%d"

	.no_dead_strip	_vce_v4_0_sw_init
.subsections_via_symbols
