	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function socfpga_fpga_ops_configure_init
_socfpga_fpga_ops_configure_init:       ## @socfpga_fpga_ops_configure_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	_FPGA_MGR_PARTIAL_RECONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rsi)
	je	LBB0_2
## %bb.1:
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
	movq	_EINVAL@GOTPCREL(%rip), %rcx
LBB0_5:
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_7
LBB0_2:
	movq	8(%rdi), %rbx
	callq	_socfpga_fpga_reset
	testl	%eax, %eax
	je	LBB0_3
LBB0_7:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
LBB0_3:
	movq	_SOCFPGA_FPGMGR_STAT_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_socfpga_fpga_wait_for_state
	testq	%rax, %rax
	je	LBB0_6
## %bb.4:
	movq	_ETIMEDOUT@GOTPCREL(%rip), %rcx
	jmp	LBB0_5
LBB0_6:
	movq	_SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SOCFPGA_FPGMGR_MON_NSTATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_socfpga_fpga_writel
	movq	_SOCFPGA_FPGMGR_CTL_OFST@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SOCFPGA_FPGMGR_CTL_AXICFGEN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_socfpga_fpga_set_bitsl
	xorl	%eax, %eax
	jmp	LBB0_7
	.cfi_endproc
                                        ## -- End function
	.comm	_FPGA_MGR_PARTIAL_RECONFIG,4,2  ## @FPGA_MGR_PARTIAL_RECONFIG
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Partial reconfiguration not supported.\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_SOCFPGA_FPGMGR_STAT_CFG,4,2    ## @SOCFPGA_FPGMGR_STAT_CFG
	.comm	_ETIMEDOUT,4,2                  ## @ETIMEDOUT
	.comm	_SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST,4,2 ## @SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST
	.comm	_SOCFPGA_FPGMGR_MON_NSTATUS,4,2 ## @SOCFPGA_FPGMGR_MON_NSTATUS
	.comm	_SOCFPGA_FPGMGR_CTL_OFST,4,2    ## @SOCFPGA_FPGMGR_CTL_OFST
	.comm	_SOCFPGA_FPGMGR_CTL_AXICFGEN,4,2 ## @SOCFPGA_FPGMGR_CTL_AXICFGEN
	.no_dead_strip	_socfpga_fpga_ops_configure_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function socfpga_fpga_ops_configure_init
_socfpga_fpga_ops_configure_init:       ; @socfpga_fpga_ops_configure_init
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	w8, [x1]
Lloh0:
	adrp	x9, _FPGA_MGR_PARTIAL_RECONFIG@GOTPAGE
Lloh1:
	ldr	x9, [x9, _FPGA_MGR_PARTIAL_RECONFIG@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_3
; %bb.1:
Lloh3:
	adrp	x1, l_.str@PAGE
Lloh4:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
Lloh5:
	adrp	x8, _EINVAL@GOTPAGE
Lloh6:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
LBB0_2:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_4
LBB0_3:
	ldr	x19, [x0, #8]
	bl	_socfpga_fpga_reset
	cbz	w0, LBB0_5
LBB0_4:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_5:
Lloh7:
	adrp	x8, _SOCFPGA_FPGMGR_STAT_CFG@GOTPAGE
Lloh8:
	ldr	x8, [x8, _SOCFPGA_FPGMGR_STAT_CFG@GOTPAGEOFF]
Lloh9:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_socfpga_fpga_wait_for_state
	cbz	x0, LBB0_7
; %bb.6:
Lloh10:
	adrp	x8, _ETIMEDOUT@GOTPAGE
Lloh11:
	ldr	x8, [x8, _ETIMEDOUT@GOTPAGEOFF]
	b	LBB0_2
LBB0_7:
Lloh12:
	adrp	x8, _SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST@GOTPAGE
Lloh13:
	ldr	x8, [x8, _SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
Lloh15:
	adrp	x8, _SOCFPGA_FPGMGR_MON_NSTATUS@GOTPAGE
Lloh16:
	ldr	x8, [x8, _SOCFPGA_FPGMGR_MON_NSTATUS@GOTPAGEOFF]
Lloh17:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_socfpga_fpga_writel
Lloh18:
	adrp	x8, _SOCFPGA_FPGMGR_CTL_OFST@GOTPAGE
Lloh19:
	ldr	x8, [x8, _SOCFPGA_FPGMGR_CTL_OFST@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
Lloh21:
	adrp	x8, _SOCFPGA_FPGMGR_CTL_AXICFGEN@GOTPAGE
Lloh22:
	ldr	x8, [x8, _SOCFPGA_FPGMGR_CTL_AXICFGEN@GOTPAGEOFF]
Lloh23:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_socfpga_fpga_set_bitsl
	mov	w0, #0
	b	LBB0_4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.cfi_endproc
                                        ; -- End function
	.comm	_FPGA_MGR_PARTIAL_RECONFIG,4,2  ; @FPGA_MGR_PARTIAL_RECONFIG
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Partial reconfiguration not supported.\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_SOCFPGA_FPGMGR_STAT_CFG,4,2    ; @SOCFPGA_FPGMGR_STAT_CFG
	.comm	_ETIMEDOUT,4,2                  ; @ETIMEDOUT
	.comm	_SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST,4,2 ; @SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST
	.comm	_SOCFPGA_FPGMGR_MON_NSTATUS,4,2 ; @SOCFPGA_FPGMGR_MON_NSTATUS
	.comm	_SOCFPGA_FPGMGR_CTL_OFST,4,2    ; @SOCFPGA_FPGMGR_CTL_OFST
	.comm	_SOCFPGA_FPGMGR_CTL_AXICFGEN,4,2 ; @SOCFPGA_FPGMGR_CTL_AXICFGEN
	.no_dead_strip	_socfpga_fpga_ops_configure_init
.subsections_via_symbols
