	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_bo_pin_restricted       ## -- Begin function amdgpu_bo_pin_restricted
	.p2align	4, 0x90
_amdgpu_bo_pin_restricted:              ## @amdgpu_bo_pin_restricted
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rcx, %r13
	movq	%rdx, %r12
	movl	%esi, %r14d
	movq	%rdi, %r15
	movq	16(%rdi), %rdi
	callq	_amdgpu_ttm_adev
	movq	%rax, %rbx
	movq	$0, -56(%rbp)
	movl	24(%r15), %edi
	callq	_amdgpu_ttm_tt_get_usermm
	testq	%rax, %rax
	je	LBB0_3
## %bb.1:
	movq	_EPERM@GOTPCREL(%rip), %rax
	jmp	LBB0_2
LBB0_3:
	xorl	%edi, %edi
	cmpq	%r13, %r12
	setg	%dil
	callq	_WARN_ON_ONCE
	testq	%rax, %rax
	je	LBB0_5
LBB0_4:
	movq	_EINVAL@GOTPCREL(%rip), %rax
LBB0_2:
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
LBB0_28:
	movl	%ebx, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_5:
	cmpq	$0, 48(%r15)
	je	LBB0_7
## %bb.6:
	movq	_AMDGPU_GEM_DOMAIN_GTT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%r14d, %eax
	movl	%eax, %r14d
	je	LBB0_4
LBB0_7:
	leaq	8(%r15), %rax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_amdgpu_bo_get_preferred_pin_domain
	movl	%eax, %r14d
	cmpl	$0, (%r15)
	je	LBB0_11
## %bb.8:
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %r12
	movq	%r12, %rdi
	callq	_amdgpu_mem_type_to_domain
	testl	%r14d, %eax
	je	LBB0_4
## %bb.9:
	incl	(%r15)
	xorl	%ebx, %ebx
	testq	%r13, %r13
	je	LBB0_28
## %bb.10:
	movq	16(%r15), %rax
	movq	(%rax), %rax
	movq	(%rax,%r12,8), %r14
	movq	%r15, %rdi
	callq	_amdgpu_bo_gpu_offset
	subq	%r14, %rax
	xorl	%edi, %edi
	cmpq	%r13, %rax
	setg	%dil
	callq	_WARN_ON_ONCE
	jmp	LBB0_28
LBB0_11:
	movq	_AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS@GOTPCREL(%rip), %rcx
	movl	4(%r15), %eax
	orl	(%rcx), %eax
	movl	%eax, 4(%r15)
	movq	_AMDGPU_GEM_CREATE_NO_CPU_ACCESS@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	jne	LBB0_13
## %bb.12:
	movq	_AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, 4(%r15)
LBB0_13:
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_amdgpu_bo_placement_from_domain
	leaq	32(%r15), %rsi
	movl	32(%r15), %edx
	testl	%edx, %edx
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movq	%rbx, %r14
	jle	LBB0_21
## %bb.14:
	movq	_PAGE_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarq	%cl, %r12
	sarq	%cl, %r13
	movq	40(%r15), %rax
	shlq	$2, %rdx
	leaq	(%rdx,%rdx,2), %r9
	xorl	%edx, %edx
	movq	_TTM_PL_FLAG_NO_EVICT@GOTPCREL(%rip), %r8
	jmp	LBB0_15
	.p2align	4, 0x90
LBB0_19:                                ##   in Loop: Header=BB0_15 Depth=1
	movl	%r13d, 4(%rax,%rdx)
LBB0_20:                                ##   in Loop: Header=BB0_15 Depth=1
	movl	(%r8), %ecx
	orl	%ecx, 8(%rax,%rdx)
	addq	$12, %rdx
	cmpq	%rdx, %r9
	je	LBB0_21
LBB0_15:                                ## =>This Inner Loop Header: Depth=1
	cmpl	%r12d, (%rax,%rdx)
	jae	LBB0_17
## %bb.16:                              ##   in Loop: Header=BB0_15 Depth=1
	movl	%r12d, (%rax,%rdx)
LBB0_17:                                ##   in Loop: Header=BB0_15 Depth=1
	testl	%r13d, %r13d
	setne	%bl
	movl	4(%rax,%rdx), %ecx
	cmpl	%r13d, %ecx
	seta	%r10b
	testl	%ecx, %ecx
	je	LBB0_19
## %bb.18:                              ##   in Loop: Header=BB0_15 Depth=1
	andb	%r10b, %bl
	je	LBB0_20
	jmp	LBB0_19
LBB0_21:
	leaq	-56(%rbp), %rdx
	callq	_ttm_bo_validate
	movl	%eax, %ebx
	movl	%eax, %edi
	callq	_unlikely
	testq	%rax, %rax
	je	LBB0_23
## %bb.22:
	movl	12(%r14), %edi
	leaq	L_.str(%rip), %rsi
	movq	%r15, %rdx
	callq	_dev_err
	jmp	LBB0_28
LBB0_23:
	movl	$1, (%r15)
	movq	8(%r15), %rdi
	callq	_amdgpu_mem_type_to_domain
	movq	_AMDGPU_GEM_DOMAIN_VRAM@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_25
## %bb.24:
	movq	%r15, %rdi
	callq	_amdgpu_bo_size
	leaq	8(%r14), %rsi
	movl	%eax, %edi
	callq	_atomic64_add
	movq	%r15, %rdi
	callq	_amdgpu_vram_mgr_bo_visible_size
	addq	$4, %r14
	jmp	LBB0_27
LBB0_25:
	movq	_AMDGPU_GEM_DOMAIN_GTT@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_28
## %bb.26:
	movq	%r15, %rdi
	callq	_amdgpu_bo_size
LBB0_27:
	movl	%eax, %edi
	movq	%r14, %rsi
	callq	_atomic64_add
	jmp	LBB0_28
	.cfi_endproc
                                        ## -- End function
	.comm	_EPERM,4,2                      ## @EPERM
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_AMDGPU_GEM_DOMAIN_GTT,4,2      ## @AMDGPU_GEM_DOMAIN_GTT
	.comm	_AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,4,2 ## @AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
	.comm	_AMDGPU_GEM_CREATE_NO_CPU_ACCESS,4,2 ## @AMDGPU_GEM_CREATE_NO_CPU_ACCESS
	.comm	_AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,4,2 ## @AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
	.comm	_PAGE_SHIFT,8,3                 ## @PAGE_SHIFT
	.comm	_TTM_PL_FLAG_NO_EVICT,4,2       ## @TTM_PL_FLAG_NO_EVICT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"%p pin failed\n"

	.comm	_AMDGPU_GEM_DOMAIN_VRAM,4,2     ## @AMDGPU_GEM_DOMAIN_VRAM
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_bo_pin_restricted       ; -- Begin function amdgpu_bo_pin_restricted
	.p2align	2
_amdgpu_bo_pin_restricted:              ; @amdgpu_bo_pin_restricted
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x21, x3
	mov	x23, x2
	mov	x24, x1
	mov	x19, x0
	ldr	x0, [x0, #16]
	bl	_amdgpu_ttm_adev
	mov	x20, x0
	str	xzr, [sp, #8]
	ldr	w0, [x19, #24]
	bl	_amdgpu_ttm_tt_get_usermm
	cbz	x0, LBB0_2
; %bb.1:
Lloh0:
	adrp	x8, _EPERM@GOTPAGE
Lloh1:
	ldr	x8, [x8, _EPERM@GOTPAGEOFF]
	b	LBB0_4
LBB0_2:
	cmp	x23, x21
	cset	w0, gt
	bl	_WARN_ON_ONCE
	cbz	x0, LBB0_6
LBB0_3:
Lloh2:
	adrp	x8, _EINVAL@GOTPAGE
Lloh3:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
LBB0_4:
	ldr	w8, [x8]
	neg	w21, w8
LBB0_5:
	mov	x0, x21
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
LBB0_6:
	ldr	x8, [x19, #48]
	cbz	x8, LBB0_8
; %bb.7:
Lloh4:
	adrp	x8, _AMDGPU_GEM_DOMAIN_GTT@GOTPAGE
Lloh5:
	ldr	x8, [x8, _AMDGPU_GEM_DOMAIN_GTT@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
	tst	w8, w24
	mov	x24, x8
	b.eq	LBB0_3
LBB0_8:
	add	x22, x19, #8
	mov	x0, x20
	mov	x1, x24
	bl	_amdgpu_bo_get_preferred_pin_domain
	mov	x24, x0
	ldr	w8, [x19]
	cbz	w8, LBB0_12
; %bb.9:
	ldr	x20, [x22]
	mov	x0, x20
	bl	_amdgpu_mem_type_to_domain
	tst	w0, w24
	b.eq	LBB0_3
; %bb.10:
	ldr	w8, [x19]
	add	w8, w8, #1
	str	w8, [x19]
	cbz	x21, LBB0_5
; %bb.11:
	ldr	x8, [x19, #16]
	ldr	x8, [x8]
	ldr	x20, [x8, x20, lsl #3]
	mov	x0, x19
	bl	_amdgpu_bo_gpu_offset
	sub	x8, x0, x20
	cmp	x8, x21
	cset	w0, gt
	bl	_WARN_ON_ONCE
	mov	w21, #0
	b	LBB0_5
LBB0_12:
Lloh7:
	adrp	x8, _AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS@GOTPAGE
Lloh8:
	ldr	x8, [x8, _AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	ldr	w9, [x19, #4]
	orr	w8, w9, w8
	str	w8, [x19, #4]
Lloh10:
	adrp	x9, _AMDGPU_GEM_CREATE_NO_CPU_ACCESS@GOTPAGE
Lloh11:
	ldr	x9, [x9, _AMDGPU_GEM_CREATE_NO_CPU_ACCESS@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_14
; %bb.13:
Lloh13:
	adrp	x9, _AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED@GOTPAGE
Lloh14:
	ldr	x9, [x9, _AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	orr	w8, w9, w8
	str	w8, [x19, #4]
LBB0_14:
	mov	x0, x19
	mov	x1, x24
	bl	_amdgpu_bo_placement_from_domain
	mov	x1, x19
	ldr	w8, [x1, #32]!
	cmp	w8, #1
	b.lt	LBB0_21
; %bb.15:
Lloh16:
	adrp	x9, _PAGE_SHIFT@GOTPAGE
Lloh17:
	ldr	x9, [x9, _PAGE_SHIFT@GOTPAGEOFF]
Lloh18:
	ldr	x10, [x9]
	asr	x9, x23, x10
	asr	x10, x21, x10
	ldr	x11, [x19, #40]
	add	x11, x11, #8
Lloh19:
	adrp	x12, _TTM_PL_FLAG_NO_EVICT@GOTPAGE
Lloh20:
	ldr	x12, [x12, _TTM_PL_FLAG_NO_EVICT@GOTPAGEOFF]
	b	LBB0_17
LBB0_16:                                ;   in Loop: Header=BB0_17 Depth=1
	ldr	w13, [x12]
	ldr	w14, [x11]
	orr	w13, w14, w13
	str	w13, [x11], #12
	subs	x8, x8, #1
	b.eq	LBB0_21
LBB0_17:                                ; =>This Inner Loop Header: Depth=1
	ldur	w13, [x11, #-8]
	cmp	w13, w9
	b.hs	LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_17 Depth=1
	stur	w9, [x11, #-8]
LBB0_19:                                ;   in Loop: Header=BB0_17 Depth=1
	cmp	w10, #0
	ldur	w13, [x11, #-4]
	ccmp	w13, w10, #0, ne
	cset	w14, hi
	cmp	w13, #0
	ccmp	w14, #0, #0, ne
	b.eq	LBB0_16
; %bb.20:                               ;   in Loop: Header=BB0_17 Depth=1
	stur	w10, [x11, #-4]
	b	LBB0_16
LBB0_21:
	add	x2, sp, #8
	mov	x0, x22
	bl	_ttm_bo_validate
	mov	x21, x0
	bl	_unlikely
	cbz	x0, LBB0_23
; %bb.22:
	ldr	w0, [x20, #12]
Lloh21:
	adrp	x1, l_.str@PAGE
Lloh22:
	add	x1, x1, l_.str@PAGEOFF
	mov	x2, x19
	bl	_dev_err
	b	LBB0_5
LBB0_23:
	mov	w8, #1
	str	w8, [x19]
	ldr	x0, [x19, #8]
	bl	_amdgpu_mem_type_to_domain
Lloh23:
	adrp	x8, _AMDGPU_GEM_DOMAIN_VRAM@GOTPAGE
Lloh24:
	ldr	x8, [x8, _AMDGPU_GEM_DOMAIN_VRAM@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
	cmp	w0, w8
	b.ne	LBB0_25
; %bb.24:
	mov	x0, x19
	bl	_amdgpu_bo_size
	add	x1, x20, #8
	bl	_atomic64_add
	mov	x0, x19
	bl	_amdgpu_vram_mgr_bo_visible_size
	add	x1, x20, #4
	b	LBB0_27
LBB0_25:
Lloh26:
	adrp	x8, _AMDGPU_GEM_DOMAIN_GTT@GOTPAGE
Lloh27:
	ldr	x8, [x8, _AMDGPU_GEM_DOMAIN_GTT@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
	cmp	w0, w8
	b.ne	LBB0_5
; %bb.26:
	mov	x0, x19
	bl	_amdgpu_bo_size
	mov	x1, x20
LBB0_27:
	bl	_atomic64_add
	b	LBB0_5
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpAdd	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.cfi_endproc
                                        ; -- End function
	.comm	_EPERM,4,2                      ; @EPERM
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_AMDGPU_GEM_DOMAIN_GTT,4,2      ; @AMDGPU_GEM_DOMAIN_GTT
	.comm	_AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,4,2 ; @AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
	.comm	_AMDGPU_GEM_CREATE_NO_CPU_ACCESS,4,2 ; @AMDGPU_GEM_CREATE_NO_CPU_ACCESS
	.comm	_AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,4,2 ; @AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
	.comm	_PAGE_SHIFT,8,3                 ; @PAGE_SHIFT
	.comm	_TTM_PL_FLAG_NO_EVICT,4,2       ; @TTM_PL_FLAG_NO_EVICT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"%p pin failed\n"

	.comm	_AMDGPU_GEM_DOMAIN_VRAM,4,2     ; @AMDGPU_GEM_DOMAIN_VRAM
.subsections_via_symbols
