	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_uvd_v1_0_init                  ## -- Begin function uvd_v1_0_init
	.p2align	4, 0x90
_uvd_v1_0_init:                         ## @uvd_v1_0_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_R600_RING_TYPE_UVD_INDEX@GOTPCREL(%rip), %r12
	movq	(%r12), %r15
	shlq	$2, %r15
	addq	8(%rdi), %r15
	movl	(%rdi), %eax
	movq	_CHIP_RV740@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jge	LBB0_2
## %bb.1:
	movq	%r14, %rdi
	movl	$10000, %esi                    ## imm = 0x2710
	movl	$10000, %edx                    ## imm = 0x2710
	jmp	LBB0_3
LBB0_2:
	movq	%r14, %rdi
	movl	$53300, %esi                    ## imm = 0xD034
	movl	$40000, %edx                    ## imm = 0x9C40
LBB0_3:
	callq	_radeon_set_uvd_clocks
	movq	%r14, %rdi
	callq	_uvd_v1_0_start
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_8
## %bb.4:
	movl	$1, (%r15)
	movq	(%r12), %rsi
	movq	%r14, %rdi
	movq	%r15, %rdx
	callq	_radeon_ring_test
	testl	%eax, %eax
	je	LBB0_6
## %bb.5:
	movl	%eax, %ebx
	movl	$0, (%r15)
	jmp	LBB0_8
LBB0_6:
	movq	%r14, %rdi
	movq	%r15, %rsi
	movl	$10, %edx
	callq	_radeon_ring_lock
	testl	%eax, %eax
	je	LBB0_9
## %bb.7:
	movl	%eax, %ebx
	leaq	L_.str(%rip), %rdi
	movl	%eax, %esi
	callq	_DRM_ERROR
LBB0_8:
	movq	%r14, %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_radeon_set_uvd_clocks
LBB0_14:
	movl	%ebx, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_9:
	movq	_UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movq	%r15, %rdi
	movl	$1048575, %esi                  ## imm = 0xFFFFF
	callq	_radeon_ring_write
	movq	_UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movq	%r15, %rdi
	movl	$1048575, %esi                  ## imm = 0xFFFFF
	callq	_radeon_ring_write
	movq	_UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movq	%r15, %rdi
	movl	$1048575, %esi                  ## imm = 0xFFFFF
	callq	_radeon_ring_write
	movq	_UVD_SEMA_TIMEOUT_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movq	%r15, %rdi
	movl	$8, %esi
	callq	_radeon_ring_write
	movq	_UVD_SEMA_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_radeon_ring_write
	movq	%r15, %rdi
	movl	$3, %esi
	callq	_radeon_ring_write
	movq	%r14, %rdi
	movq	%r15, %rsi
	xorl	%edx, %edx
	callq	_radeon_ring_unlock_commit
	movq	%r14, %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_radeon_set_uvd_clocks
	movl	(%r14), %eax
	leal	-130(%rax), %ecx
	cmpl	$3, %ecx
	jae	LBB0_10
## %bb.11:
	movq	_MC_CONFIG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%rbx), %edi
	movl	$16, %esi
	callq	_WREG32
	movq	_RS_DQ_RD_RET_CONF@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$63, %esi
	callq	_WREG32
	movl	(%rbx), %edi
	movl	$31, %esi
	callq	_WREG32
	jmp	LBB0_12
LBB0_10:
	addl	$-128, %eax
	cmpl	$2, %eax
	jae	LBB0_13
LBB0_12:
	movq	_UVD_VCPU_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$16, %esi
	movl	$-17, %edx
	callq	_WREG32_P
LBB0_13:
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_INFO
	xorl	%ebx, %ebx
	jmp	LBB0_14
	.cfi_endproc
                                        ## -- End function
	.comm	_R600_RING_TYPE_UVD_INDEX,8,3   ## @R600_RING_TYPE_UVD_INDEX
	.comm	_CHIP_RV740,4,2                 ## @CHIP_RV740
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"radeon: ring failed to lock UVD ring (%d).\n"

	.comm	_UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL,4,2 ## @UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
	.comm	_UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL,4,2 ## @UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
	.comm	_UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL,4,2 ## @UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
	.comm	_UVD_SEMA_TIMEOUT_STATUS,4,2    ## @UVD_SEMA_TIMEOUT_STATUS
	.comm	_UVD_SEMA_CNTL,4,2              ## @UVD_SEMA_CNTL
	.comm	_MC_CONFIG,4,2                  ## @MC_CONFIG
	.comm	_RS_DQ_RD_RET_CONF,4,2          ## @RS_DQ_RD_RET_CONF
	.comm	_UVD_VCPU_CNTL,4,2              ## @UVD_VCPU_CNTL
L_.str.1:                               ## @.str.1
	.asciz	"UVD initialized successfully.\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_uvd_v1_0_init                  ; -- Begin function uvd_v1_0_init
	.p2align	2
_uvd_v1_0_init:                         ; @uvd_v1_0_init
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	x20, [x0, #8]
Lloh0:
	adrp	x22, _R600_RING_TYPE_UVD_INDEX@GOTPAGE
Lloh1:
	ldr	x22, [x22, _R600_RING_TYPE_UVD_INDEX@GOTPAGEOFF]
	ldr	x23, [x22]
	ldr	w8, [x0]
Lloh2:
	adrp	x9, _CHIP_RV740@GOTPAGE
Lloh3:
	ldr	x9, [x9, _CHIP_RV740@GOTPAGEOFF]
Lloh4:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ge	LBB0_2
; %bb.1:
	mov	w1, #10000
	mov	w2, #10000
	b	LBB0_3
LBB0_2:
	mov	w1, #53300
	mov	w2, #40000
LBB0_3:
	bl	_radeon_set_uvd_clocks
	mov	x0, x19
	bl	_uvd_v1_0_start
	mov	x21, x0
	cbnz	w0, LBB0_8
; %bb.4:
	add	x20, x20, x23, lsl #2
	mov	w8, #1
	str	w8, [x20]
	ldr	x1, [x22]
	mov	x0, x19
	mov	x2, x20
	bl	_radeon_ring_test
	cbz	w0, LBB0_6
; %bb.5:
	mov	x21, x0
	str	wzr, [x20]
	b	LBB0_8
LBB0_6:
	mov	x0, x19
	mov	x1, x20
	mov	w2, #10
	bl	_radeon_ring_lock
	cbz	w0, LBB0_10
; %bb.7:
	mov	x21, x0
Lloh5:
	adrp	x0, l_.str@PAGE
Lloh6:
	add	x0, x0, l_.str@PAGEOFF
	mov	x1, x21
	bl	_DRM_ERROR
LBB0_8:
	mov	x0, x19
	mov	w1, #0
	mov	w2, #0
	bl	_radeon_set_uvd_clocks
LBB0_9:
	mov	x0, x21
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_10:
Lloh7:
	adrp	x8, _UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL@GOTPAGE
Lloh8:
	ldr	x8, [x8, _UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL@GOTPAGEOFF]
Lloh9:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x20
	bl	_radeon_ring_write
	mov	x0, x20
	mov	w1, #1048575
	bl	_radeon_ring_write
Lloh10:
	adrp	x8, _UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL@GOTPAGE
Lloh11:
	ldr	x8, [x8, _UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL@GOTPAGEOFF]
Lloh12:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x20
	bl	_radeon_ring_write
	mov	x0, x20
	mov	w1, #1048575
	bl	_radeon_ring_write
Lloh13:
	adrp	x8, _UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL@GOTPAGE
Lloh14:
	ldr	x8, [x8, _UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL@GOTPAGEOFF]
Lloh15:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x20
	bl	_radeon_ring_write
	mov	x0, x20
	mov	w1, #1048575
	bl	_radeon_ring_write
Lloh16:
	adrp	x8, _UVD_SEMA_TIMEOUT_STATUS@GOTPAGE
Lloh17:
	ldr	x8, [x8, _UVD_SEMA_TIMEOUT_STATUS@GOTPAGEOFF]
Lloh18:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x20
	bl	_radeon_ring_write
	mov	x0, x20
	mov	w1, #8
	bl	_radeon_ring_write
Lloh19:
	adrp	x8, _UVD_SEMA_CNTL@GOTPAGE
Lloh20:
	ldr	x8, [x8, _UVD_SEMA_CNTL@GOTPAGEOFF]
Lloh21:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x20
	bl	_radeon_ring_write
	mov	x0, x20
	mov	w1, #3
	bl	_radeon_ring_write
	mov	x0, x19
	mov	x1, x20
	mov	w2, #0
	bl	_radeon_ring_unlock_commit
	mov	x0, x19
	mov	w1, #0
	mov	w2, #0
	bl	_radeon_set_uvd_clocks
	ldr	w8, [x19]
	sub	w9, w8, #130
	cmp	w9, #3
	b.hs	LBB0_12
; %bb.11:
Lloh22:
	adrp	x19, _MC_CONFIG@GOTPAGE
Lloh23:
	ldr	x19, [x19, _MC_CONFIG@GOTPAGEOFF]
	ldr	w0, [x19]
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x19]
	mov	w1, #16
	bl	_WREG32
Lloh24:
	adrp	x8, _RS_DQ_RD_RET_CONF@GOTPAGE
Lloh25:
	ldr	x8, [x8, _RS_DQ_RD_RET_CONF@GOTPAGEOFF]
Lloh26:
	ldr	w0, [x8]
	mov	w1, #63
	bl	_WREG32
	ldr	w0, [x19]
	mov	w1, #31
	bl	_WREG32
	b	LBB0_13
LBB0_12:
	sub	w8, w8, #128
	cmp	w8, #2
	b.hs	LBB0_14
LBB0_13:
Lloh27:
	adrp	x8, _UVD_VCPU_CNTL@GOTPAGE
Lloh28:
	ldr	x8, [x8, _UVD_VCPU_CNTL@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	mov	w1, #16
	mov	w2, #-17
	bl	_WREG32_P
LBB0_14:
Lloh30:
	adrp	x0, l_.str.1@PAGE
Lloh31:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_INFO
	mov	w21, #0
	b	LBB0_9
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpAdd	Lloh30, Lloh31
	.cfi_endproc
                                        ; -- End function
	.comm	_R600_RING_TYPE_UVD_INDEX,8,3   ; @R600_RING_TYPE_UVD_INDEX
	.comm	_CHIP_RV740,4,2                 ; @CHIP_RV740
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"radeon: ring failed to lock UVD ring (%d).\n"

	.comm	_UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL,4,2 ; @UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
	.comm	_UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL,4,2 ; @UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
	.comm	_UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL,4,2 ; @UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
	.comm	_UVD_SEMA_TIMEOUT_STATUS,4,2    ; @UVD_SEMA_TIMEOUT_STATUS
	.comm	_UVD_SEMA_CNTL,4,2              ; @UVD_SEMA_CNTL
	.comm	_MC_CONFIG,4,2                  ; @MC_CONFIG
	.comm	_RS_DQ_RD_RET_CONF,4,2          ; @RS_DQ_RD_RET_CONF
	.comm	_UVD_VCPU_CNTL,4,2              ; @UVD_VCPU_CNTL
l_.str.1:                               ; @.str.1
	.asciz	"UVD initialized successfully.\n"

.subsections_via_symbols
