	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function meson_viu_set_osd_matrix
_meson_viu_set_osd_matrix:              ## @meson_viu_set_osd_matrix
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r13
	movq	%rdi, %r15
	movq	_VIU_MATRIX_OSD@GOTPCREL(%rip), %rax
	cmpl	%esi, (%rax)
	jne	LBB0_7
## %bb.1:
	movl	%ecx, -44(%rbp)                 ## 4-byte Spill
	movl	(%r13), %eax
	shll	$16, %eax
	andl	$268369920, %eax                ## imm = 0xFFF0000
	movl	$4095, %r12d                    ## imm = 0xFFF
	movl	4(%r13), %ebx
	andl	%r12d, %ebx
	orl	%eax, %ebx
	movq	(%r15), %r14
	movq	_VIU_OSD1_MATRIX_PRE_OFFSET0_1@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	__REG
	addq	%rax, %r14
	movl	%ebx, %edi
	movq	%r14, %rsi
	callq	_writel
	movl	8(%r13), %r14d
	andl	%r12d, %r14d
	movq	(%r15), %rbx
	movq	_VIU_OSD1_MATRIX_PRE_OFFSET2@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	__REG
	addq	%rax, %rbx
	movl	%r14d, %edi
	movq	%rbx, %rsi
	callq	_writel
	movl	12(%r13), %eax
	shll	$16, %eax
	andl	$536805376, %eax                ## imm = 0x1FFF0000
	movl	$8191, %r12d                    ## imm = 0x1FFF
	movl	16(%r13), %ebx
	andl	%r12d, %ebx
	orl	%eax, %ebx
	movq	(%r15), %r14
	movq	_VIU_OSD1_MATRIX_COEF00_01@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	__REG
	addq	%rax, %r14
	movl	%ebx, %edi
	movq	%r14, %rsi
	callq	_writel
	movl	20(%r13), %eax
	shll	$16, %eax
	andl	$536805376, %eax                ## imm = 0x1FFF0000
	movl	24(%r13), %ebx
	andl	%r12d, %ebx
	orl	%eax, %ebx
	movq	(%r15), %r14
	movq	_VIU_OSD1_MATRIX_COEF02_10@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	__REG
	addq	%rax, %r14
	movl	%ebx, %edi
	movq	%r14, %rsi
	callq	_writel
	movl	28(%r13), %eax
	shll	$16, %eax
	andl	$536805376, %eax                ## imm = 0x1FFF0000
	movl	32(%r13), %ebx
	andl	%r12d, %ebx
	orl	%eax, %ebx
	movq	(%r15), %r14
	movq	_VIU_OSD1_MATRIX_COEF11_12@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	__REG
	addq	%rax, %r14
	movl	%ebx, %edi
	movq	%r14, %rsi
	callq	_writel
	movl	36(%r13), %eax
	shll	$16, %eax
	andl	$536805376, %eax                ## imm = 0x1FFF0000
	movl	40(%r13), %ebx
	andl	%r12d, %ebx
	orl	%eax, %ebx
	movq	(%r15), %r14
	movq	_VIU_OSD1_MATRIX_COEF20_21@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	__REG
	addq	%rax, %r14
	movl	%ebx, %edi
	movq	%r14, %rsi
	callq	_writel
	movl	44(%r13), %ebx
	shll	$16, %ebx
	andl	$536805376, %ebx                ## imm = 0x1FFF0000
	cmpl	$0, 84(%r13)
	je	LBB0_2
## %bb.3:
	movl	48(%r13), %eax
	andl	%r12d, %eax
	orl	%eax, %ebx
	movq	(%r15), %r14
	movq	_VIU_OSD1_MATRIX_COEF22_30@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	__REG
	addq	%rax, %r14
	movl	%ebx, %edi
	movq	%r14, %rsi
	callq	_writel
	movl	52(%r13), %eax
	shll	$16, %eax
	andl	$536805376, %eax                ## imm = 0x1FFF0000
	movl	56(%r13), %ebx
	andl	%r12d, %ebx
	orl	%eax, %ebx
	movq	(%r15), %r14
	movq	_VIU_OSD1_MATRIX_COEF31_32@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	__REG
	addq	%rax, %r14
	movl	%ebx, %edi
	movq	%r14, %rsi
	callq	_writel
	movl	60(%r13), %eax
	shll	$16, %eax
	andl	$536805376, %eax                ## imm = 0x1FFF0000
	movl	64(%r13), %ebx
	andl	%r12d, %ebx
	orl	%eax, %ebx
	movq	(%r15), %r14
	movq	_VIU_OSD1_MATRIX_COEF40_41@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	__REG
	addq	%rax, %r14
	movl	%ebx, %edi
	movq	%r14, %rsi
	callq	_writel
	andl	68(%r13), %r12d
	movq	_VIU_OSD1_MATRIX_COLMOD_COEF42@GOTPCREL(%rip), %rax
	movl	%r12d, %ebx
	jmp	LBB0_4
LBB0_7:
	movq	_VIU_MATRIX_OSD_EOTF@GOTPCREL(%rip), %rax
	cmpl	%esi, (%rax)
	jne	LBB0_14
## %bb.8:
	movl	(%r13), %eax
	shll	$16, %eax
	andl	$536805376, %eax                ## imm = 0x1FFF0000
	movl	$8191, %r12d                    ## imm = 0x1FFF
	movl	4(%r13), %ebx
	andl	%r12d, %ebx
	orl	%eax, %ebx
	movq	(%r15), %r14
	movq	_VIU_OSD1_EOTF_CTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	incq	%rdi
	movl	%ecx, -44(%rbp)                 ## 4-byte Spill
	callq	__REG
	addq	%rax, %r14
	movl	%ebx, %edi
	movq	%r14, %rsi
	callq	_writel
	movl	8(%r13), %eax
	shll	$16, %eax
	andl	$536805376, %eax                ## imm = 0x1FFF0000
	movl	12(%r13), %ebx
	andl	%r12d, %ebx
	orl	%eax, %ebx
	movq	(%r15), %r14
	movq	_VIU_OSD1_EOTF_CTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	$2, %rdi
	callq	__REG
	addq	%rax, %r14
	movl	%ebx, %edi
	movq	%r14, %rsi
	callq	_writel
	movl	16(%r13), %eax
	shll	$16, %eax
	andl	$536805376, %eax                ## imm = 0x1FFF0000
	movl	20(%r13), %ebx
	andl	%r12d, %ebx
	orl	%eax, %ebx
	movq	(%r15), %r14
	movq	_VIU_OSD1_EOTF_CTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	$3, %rdi
	callq	__REG
	addq	%rax, %r14
	movl	%ebx, %edi
	movq	%r14, %rsi
	callq	_writel
	movl	24(%r13), %eax
	shll	$16, %eax
	andl	$536805376, %eax                ## imm = 0x1FFF0000
	movl	28(%r13), %ebx
	andl	%r12d, %ebx
	orl	%eax, %ebx
	movq	(%r15), %r14
	movq	_VIU_OSD1_EOTF_CTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	$4, %rdi
	callq	__REG
	addq	%rax, %r14
	movl	%ebx, %edi
	movq	%r14, %rsi
	callq	_writel
	movl	32(%r13), %eax
	shll	$16, %eax
	andl	$536805376, %eax                ## imm = 0x1FFF0000
	andl	36(%r13), %r12d
	orl	%eax, %r12d
	movq	(%r15), %rbx
	movq	_VIU_OSD1_EOTF_CTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	$5, %rdi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel
	movl	$30, %edi
	callq	_BIT
	movl	%eax, %r13d
	movl	$0, %r14d
	movl	-44(%rbp), %eax                 ## 4-byte Reload
	movl	%eax, %r12d
	testl	%eax, %eax
	je	LBB0_10
## %bb.9:
	movl	$30, %edi
	callq	_BIT
	movl	%eax, %r14d
LBB0_10:
	movq	(%r15), %rbx
	movq	_VIU_OSD1_EOTF_CTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	__REG
	addq	%rax, %rbx
	movl	%r13d, %edi
	movl	%r14d, %esi
	movq	%rbx, %rdx
	callq	_writel_bits_relaxed
	movl	$31, %edi
	callq	_BIT
	movl	%eax, %r14d
	testl	%r12d, %r12d
	movl	$0, %r12d
	je	LBB0_12
## %bb.11:
	movl	$31, %edi
	callq	_BIT
	movl	%eax, %r12d
LBB0_12:
	movq	(%r15), %rbx
	movq	_VIU_OSD1_EOTF_CTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	__REG
	addq	%rax, %rbx
	movl	%r14d, %edi
	movl	%r12d, %esi
	jmp	LBB0_13
LBB0_14:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	movq	_VIU_OSD1_MATRIX_COEF22_30@GOTPCREL(%rip), %rax
LBB0_4:
	movl	$4095, %r12d                    ## imm = 0xFFF
	movq	(%r15), %r14
	movq	(%rax), %rdi
	callq	__REG
	addq	%rax, %r14
	movl	%ebx, %edi
	movq	%r14, %rsi
	callq	_writel
	movl	72(%r13), %eax
	shll	$16, %eax
	andl	$268369920, %eax                ## imm = 0xFFF0000
	movl	76(%r13), %ebx
	andl	%r12d, %ebx
	orl	%eax, %ebx
	movq	(%r15), %r14
	movq	_VIU_OSD1_MATRIX_OFFSET0_1@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	__REG
	addq	%rax, %r14
	movl	%ebx, %edi
	movq	%r14, %rsi
	callq	_writel
	andl	80(%r13), %r12d
	movq	(%r15), %rbx
	movq	_VIU_OSD1_MATRIX_OFFSET2@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel
	movl	84(%r13), %r14d
	shll	$30, %r14d
	movq	(%r15), %rbx
	movq	_VIU_OSD1_MATRIX_COLMOD_COEF42@GOTPCREL(%rip), %r12
	movq	(%r12), %rdi
	callq	__REG
	addq	%rax, %rbx
	movl	$-1073741824, %edi              ## imm = 0xC0000000
	movl	%r14d, %esi
	movq	%rbx, %rdx
	callq	_writel_bits_relaxed
	movl	88(%r13), %r14d
	shll	$16, %r14d
	movq	(%r15), %rbx
	movq	(%r12), %rdi
	callq	__REG
	addq	%rax, %rbx
	movl	$458752, %edi                   ## imm = 0x70000
	movl	%r14d, %esi
	movq	%rbx, %rdx
	callq	_writel_bits_relaxed
	xorl	%r14d, %r14d
	xorl	%edi, %edi
	callq	_BIT
	movl	%eax, %r12d
	cmpl	$0, -44(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_6
## %bb.5:
	xorl	%edi, %edi
	callq	_BIT
	movl	%eax, %r14d
LBB0_6:
	movq	(%r15), %rbx
	movq	_VIU_OSD1_MATRIX_CTRL@GOTPCREL(%rip), %r13
	movq	(%r13), %rdi
	callq	__REG
	addq	%rax, %rbx
	movl	%r12d, %edi
	movl	%r14d, %esi
	movq	%rbx, %rdx
	callq	_writel_bits_relaxed
	movl	$1, %edi
	callq	_BIT
	movl	%eax, %r14d
	movq	(%r15), %rbx
	movq	(%r13), %rdi
	callq	__REG
	addq	%rax, %rbx
	movl	%r14d, %edi
	xorl	%esi, %esi
LBB0_13:
	movq	%rbx, %rdx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_writel_bits_relaxed            ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_VIU_MATRIX_OSD,4,2             ## @VIU_MATRIX_OSD
	.comm	_VIU_OSD1_MATRIX_PRE_OFFSET0_1,8,3 ## @VIU_OSD1_MATRIX_PRE_OFFSET0_1
	.comm	_VIU_OSD1_MATRIX_PRE_OFFSET2,8,3 ## @VIU_OSD1_MATRIX_PRE_OFFSET2
	.comm	_VIU_OSD1_MATRIX_COEF00_01,8,3  ## @VIU_OSD1_MATRIX_COEF00_01
	.comm	_VIU_OSD1_MATRIX_COEF02_10,8,3  ## @VIU_OSD1_MATRIX_COEF02_10
	.comm	_VIU_OSD1_MATRIX_COEF11_12,8,3  ## @VIU_OSD1_MATRIX_COEF11_12
	.comm	_VIU_OSD1_MATRIX_COEF20_21,8,3  ## @VIU_OSD1_MATRIX_COEF20_21
	.comm	_VIU_OSD1_MATRIX_COEF22_30,8,3  ## @VIU_OSD1_MATRIX_COEF22_30
	.comm	_VIU_OSD1_MATRIX_COEF31_32,8,3  ## @VIU_OSD1_MATRIX_COEF31_32
	.comm	_VIU_OSD1_MATRIX_COEF40_41,8,3  ## @VIU_OSD1_MATRIX_COEF40_41
	.comm	_VIU_OSD1_MATRIX_COLMOD_COEF42,8,3 ## @VIU_OSD1_MATRIX_COLMOD_COEF42
	.comm	_VIU_OSD1_MATRIX_OFFSET0_1,8,3  ## @VIU_OSD1_MATRIX_OFFSET0_1
	.comm	_VIU_OSD1_MATRIX_OFFSET2,8,3    ## @VIU_OSD1_MATRIX_OFFSET2
	.comm	_VIU_OSD1_MATRIX_CTRL,8,3       ## @VIU_OSD1_MATRIX_CTRL
	.comm	_VIU_MATRIX_OSD_EOTF,4,2        ## @VIU_MATRIX_OSD_EOTF
	.comm	_VIU_OSD1_EOTF_CTL,8,3          ## @VIU_OSD1_EOTF_CTL
	.no_dead_strip	_meson_viu_set_osd_matrix
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function meson_viu_set_osd_matrix
_meson_viu_set_osd_matrix:              ; @meson_viu_set_osd_matrix
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x3
	mov	x21, x2
	mov	x19, x0
Lloh0:
	adrp	x8, _VIU_MATRIX_OSD@GOTPAGE
Lloh1:
	ldr	x8, [x8, _VIU_MATRIX_OSD@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cmp	w8, w1
	b.ne	LBB0_6
; %bb.1:
	ldp	w8, w9, [x21]
	and	w22, w9, #0xfff
	bfi	w22, w8, #16, #12
	ldr	x23, [x19]
Lloh3:
	adrp	x8, _VIU_OSD1_MATRIX_PRE_OFFSET0_1@GOTPAGE
Lloh4:
	ldr	x8, [x8, _VIU_OSD1_MATRIX_PRE_OFFSET0_1@GOTPAGEOFF]
Lloh5:
	ldr	x0, [x8]
	bl	__REG
	add	x1, x0, x23
	mov	x0, x22
	bl	_writel
	ldr	w8, [x21, #8]
	and	w22, w8, #0xfff
	ldr	x23, [x19]
Lloh6:
	adrp	x8, _VIU_OSD1_MATRIX_PRE_OFFSET2@GOTPAGE
Lloh7:
	ldr	x8, [x8, _VIU_OSD1_MATRIX_PRE_OFFSET2@GOTPAGEOFF]
Lloh8:
	ldr	x0, [x8]
	bl	__REG
	add	x1, x0, x23
	mov	x0, x22
	bl	_writel
	ldp	w8, w9, [x21, #12]
	and	w22, w9, #0x1fff
	bfi	w22, w8, #16, #13
	ldr	x23, [x19]
Lloh9:
	adrp	x8, _VIU_OSD1_MATRIX_COEF00_01@GOTPAGE
Lloh10:
	ldr	x8, [x8, _VIU_OSD1_MATRIX_COEF00_01@GOTPAGEOFF]
Lloh11:
	ldr	x0, [x8]
	bl	__REG
	add	x1, x0, x23
	mov	x0, x22
	bl	_writel
	ldp	w8, w9, [x21, #20]
	and	w22, w9, #0x1fff
	bfi	w22, w8, #16, #13
	ldr	x23, [x19]
Lloh12:
	adrp	x8, _VIU_OSD1_MATRIX_COEF02_10@GOTPAGE
Lloh13:
	ldr	x8, [x8, _VIU_OSD1_MATRIX_COEF02_10@GOTPAGEOFF]
Lloh14:
	ldr	x0, [x8]
	bl	__REG
	add	x1, x0, x23
	mov	x0, x22
	bl	_writel
	ldp	w8, w9, [x21, #28]
	and	w22, w9, #0x1fff
	bfi	w22, w8, #16, #13
	ldr	x23, [x19]
Lloh15:
	adrp	x8, _VIU_OSD1_MATRIX_COEF11_12@GOTPAGE
Lloh16:
	ldr	x8, [x8, _VIU_OSD1_MATRIX_COEF11_12@GOTPAGEOFF]
Lloh17:
	ldr	x0, [x8]
	bl	__REG
	add	x1, x0, x23
	mov	x0, x22
	bl	_writel
	ldp	w8, w9, [x21, #36]
	and	w22, w9, #0x1fff
	bfi	w22, w8, #16, #13
	ldr	x23, [x19]
Lloh18:
	adrp	x8, _VIU_OSD1_MATRIX_COEF20_21@GOTPAGE
Lloh19:
	ldr	x8, [x8, _VIU_OSD1_MATRIX_COEF20_21@GOTPAGEOFF]
Lloh20:
	ldr	x0, [x8]
	bl	__REG
	add	x1, x0, x23
	mov	x0, x22
	bl	_writel
	ldr	w9, [x21, #84]
	ldr	w8, [x21, #44]
	ubfiz	w22, w8, #16, #13
Lloh21:
	adrp	x8, _VIU_OSD1_MATRIX_COEF22_30@GOTPAGE
Lloh22:
	ldr	x8, [x8, _VIU_OSD1_MATRIX_COEF22_30@GOTPAGEOFF]
Lloh23:
	adrp	x23, _VIU_OSD1_MATRIX_COLMOD_COEF42@GOTPAGE
Lloh24:
	ldr	x23, [x23, _VIU_OSD1_MATRIX_COLMOD_COEF42@GOTPAGEOFF]
	cbz	w9, LBB0_3
; %bb.2:
	ldr	w9, [x21, #48]
	and	w9, w9, #0x1fff
	orr	w22, w22, w9
	ldr	x24, [x19]
	ldr	x0, [x8]
	bl	__REG
	add	x1, x0, x24
	mov	x0, x22
	bl	_writel
	ldp	w8, w9, [x21, #52]
	and	w22, w9, #0x1fff
	bfi	w22, w8, #16, #13
	ldr	x24, [x19]
Lloh25:
	adrp	x8, _VIU_OSD1_MATRIX_COEF31_32@GOTPAGE
Lloh26:
	ldr	x8, [x8, _VIU_OSD1_MATRIX_COEF31_32@GOTPAGEOFF]
Lloh27:
	ldr	x0, [x8]
	bl	__REG
	add	x1, x0, x24
	mov	x0, x22
	bl	_writel
	ldp	w8, w9, [x21, #60]
	and	w22, w9, #0x1fff
	bfi	w22, w8, #16, #13
	ldr	x24, [x19]
Lloh28:
	adrp	x8, _VIU_OSD1_MATRIX_COEF40_41@GOTPAGE
Lloh29:
	ldr	x8, [x8, _VIU_OSD1_MATRIX_COEF40_41@GOTPAGEOFF]
Lloh30:
	ldr	x0, [x8]
	bl	__REG
	add	x1, x0, x24
	mov	x0, x22
	bl	_writel
	ldr	w8, [x21, #68]
	and	w22, w8, #0x1fff
Lloh31:
	adrp	x8, _VIU_OSD1_MATRIX_COLMOD_COEF42@GOTPAGE
Lloh32:
	ldr	x8, [x8, _VIU_OSD1_MATRIX_COLMOD_COEF42@GOTPAGEOFF]
LBB0_3:
	ldr	x24, [x19]
	ldr	x0, [x8]
	bl	__REG
	add	x1, x0, x24
	mov	x0, x22
	bl	_writel
	ldp	w8, w9, [x21, #72]
	and	w22, w9, #0xfff
	bfi	w22, w8, #16, #12
	ldr	x24, [x19]
Lloh33:
	adrp	x8, _VIU_OSD1_MATRIX_OFFSET0_1@GOTPAGE
Lloh34:
	ldr	x8, [x8, _VIU_OSD1_MATRIX_OFFSET0_1@GOTPAGEOFF]
Lloh35:
	ldr	x0, [x8]
	bl	__REG
	add	x1, x0, x24
	mov	x0, x22
	bl	_writel
	ldr	w8, [x21, #80]
	and	w22, w8, #0xfff
	ldr	x24, [x19]
Lloh36:
	adrp	x8, _VIU_OSD1_MATRIX_OFFSET2@GOTPAGE
Lloh37:
	ldr	x8, [x8, _VIU_OSD1_MATRIX_OFFSET2@GOTPAGEOFF]
Lloh38:
	ldr	x0, [x8]
	bl	__REG
	add	x1, x0, x24
	mov	x0, x22
	bl	_writel
	ldr	w8, [x21, #84]
	lsl	w22, w8, #30
	ldr	x24, [x19]
	ldr	x0, [x23]
	bl	__REG
	add	x2, x0, x24
	mov	w0, #-1073741824
	mov	x1, x22
	bl	_writel_bits_relaxed
	ldr	w8, [x21, #88]
	lsl	w21, w8, #16
	ldr	x22, [x19]
	ldr	x0, [x23]
	bl	__REG
	add	x2, x0, x22
	mov	w0, #458752
	mov	x1, x21
	bl	_writel_bits_relaxed
	mov	w0, #0
	bl	_BIT
	mov	x21, x0
	cbz	w20, LBB0_5
; %bb.4:
	mov	w0, #0
	bl	_BIT
	mov	x20, x0
LBB0_5:
	ldr	x22, [x19]
Lloh39:
	adrp	x23, _VIU_OSD1_MATRIX_CTRL@GOTPAGE
Lloh40:
	ldr	x23, [x23, _VIU_OSD1_MATRIX_CTRL@GOTPAGEOFF]
	ldr	x0, [x23]
	bl	__REG
	add	x2, x0, x22
	mov	x0, x21
	mov	x1, x20
	bl	_writel_bits_relaxed
	mov	w0, #1
	bl	_BIT
	mov	x20, x0
	ldr	x19, [x19]
	ldr	x0, [x23]
	bl	__REG
	add	x2, x0, x19
	mov	x0, x20
	mov	w1, #0
	b	LBB0_14
LBB0_6:
Lloh41:
	adrp	x8, _VIU_MATRIX_OSD_EOTF@GOTPAGE
Lloh42:
	ldr	x8, [x8, _VIU_MATRIX_OSD_EOTF@GOTPAGEOFF]
Lloh43:
	ldr	w8, [x8]
	cmp	w8, w1
	b.ne	LBB0_9
; %bb.7:
	ldp	w8, w9, [x21]
	and	w22, w9, #0x1fff
	bfi	w22, w8, #16, #13
	ldr	x24, [x19]
Lloh44:
	adrp	x23, _VIU_OSD1_EOTF_CTL@GOTPAGE
Lloh45:
	ldr	x23, [x23, _VIU_OSD1_EOTF_CTL@GOTPAGEOFF]
	ldr	x8, [x23]
	add	x0, x8, #1
	bl	__REG
	add	x1, x0, x24
	mov	x0, x22
	bl	_writel
	ldp	w8, w9, [x21, #8]
	and	w22, w9, #0x1fff
	bfi	w22, w8, #16, #13
	ldr	x24, [x19]
	ldr	x8, [x23]
	add	x0, x8, #2
	bl	__REG
	add	x1, x0, x24
	mov	x0, x22
	bl	_writel
	ldp	w8, w9, [x21, #16]
	and	w22, w9, #0x1fff
	bfi	w22, w8, #16, #13
	ldr	x24, [x19]
	ldr	x8, [x23]
	add	x0, x8, #3
	bl	__REG
	add	x1, x0, x24
	mov	x0, x22
	bl	_writel
	ldp	w8, w9, [x21, #24]
	and	w22, w9, #0x1fff
	bfi	w22, w8, #16, #13
	ldr	x24, [x19]
	ldr	x8, [x23]
	add	x0, x8, #4
	bl	__REG
	add	x1, x0, x24
	mov	x0, x22
	bl	_writel
	ldp	w8, w9, [x21, #32]
	and	w21, w9, #0x1fff
	bfi	w21, w8, #16, #13
	ldr	x22, [x19]
	ldr	x8, [x23]
	add	x0, x8, #5
	bl	__REG
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel
	mov	w0, #30
	bl	_BIT
	mov	x21, x0
	cbz	w20, LBB0_10
; %bb.8:
	mov	w0, #30
	bl	_BIT
	mov	x22, x0
	b	LBB0_11
LBB0_9:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_10:
	mov	w22, #0
LBB0_11:
	ldr	x24, [x19]
	ldr	x0, [x23]
	bl	__REG
	add	x2, x0, x24
	mov	x0, x21
	mov	x1, x22
	bl	_writel_bits_relaxed
	mov	w0, #31
	bl	_BIT
	mov	x21, x0
	cbz	w20, LBB0_13
; %bb.12:
	mov	w0, #31
	bl	_BIT
	mov	x20, x0
LBB0_13:
	ldr	x19, [x19]
	ldr	x0, [x23]
	bl	__REG
	add	x2, x0, x19
	mov	x0, x21
	mov	x1, x20
LBB0_14:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_writel_bits_relaxed
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh44, Lloh45
	.cfi_endproc
                                        ; -- End function
	.comm	_VIU_MATRIX_OSD,4,2             ; @VIU_MATRIX_OSD
	.comm	_VIU_OSD1_MATRIX_PRE_OFFSET0_1,8,3 ; @VIU_OSD1_MATRIX_PRE_OFFSET0_1
	.comm	_VIU_OSD1_MATRIX_PRE_OFFSET2,8,3 ; @VIU_OSD1_MATRIX_PRE_OFFSET2
	.comm	_VIU_OSD1_MATRIX_COEF00_01,8,3  ; @VIU_OSD1_MATRIX_COEF00_01
	.comm	_VIU_OSD1_MATRIX_COEF02_10,8,3  ; @VIU_OSD1_MATRIX_COEF02_10
	.comm	_VIU_OSD1_MATRIX_COEF11_12,8,3  ; @VIU_OSD1_MATRIX_COEF11_12
	.comm	_VIU_OSD1_MATRIX_COEF20_21,8,3  ; @VIU_OSD1_MATRIX_COEF20_21
	.comm	_VIU_OSD1_MATRIX_COEF22_30,8,3  ; @VIU_OSD1_MATRIX_COEF22_30
	.comm	_VIU_OSD1_MATRIX_COEF31_32,8,3  ; @VIU_OSD1_MATRIX_COEF31_32
	.comm	_VIU_OSD1_MATRIX_COEF40_41,8,3  ; @VIU_OSD1_MATRIX_COEF40_41
	.comm	_VIU_OSD1_MATRIX_COLMOD_COEF42,8,3 ; @VIU_OSD1_MATRIX_COLMOD_COEF42
	.comm	_VIU_OSD1_MATRIX_OFFSET0_1,8,3  ; @VIU_OSD1_MATRIX_OFFSET0_1
	.comm	_VIU_OSD1_MATRIX_OFFSET2,8,3    ; @VIU_OSD1_MATRIX_OFFSET2
	.comm	_VIU_OSD1_MATRIX_CTRL,8,3       ; @VIU_OSD1_MATRIX_CTRL
	.comm	_VIU_MATRIX_OSD_EOTF,4,2        ; @VIU_MATRIX_OSD_EOTF
	.comm	_VIU_OSD1_EOTF_CTL,8,3          ; @VIU_OSD1_EOTF_CTL
	.no_dead_strip	_meson_viu_set_osd_matrix
.subsections_via_symbols
