	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vega20_apply_clocks_adjust_rules
_vega20_apply_clocks_adjust_rules:      ## @vega20_apply_clocks_adjust_rules
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	(%rdi), %r10
	movq	24(%rdi), %rax
	cmpl	$2, (%r10)
	jl	LBB0_3
## %bb.1:
	cmpl	$0, 24(%r10)
	je	LBB0_2
LBB0_3:
	xorl	%r9d, %r9d
LBB0_4:
	movl	4(%r10), %r14d
	movq	168(%rax), %rsi
	movl	(%rsi), %edx
	movl	%edx, 176(%rax)
	movslq	160(%rax), %rcx
	movl	-4(%rsi,%rcx,4), %r15d
	movl	%r15d, 180(%rax)
	movl	%edx, 184(%rax)
	movl	%r15d, 188(%rax)
	movq	_VEGA20_UMD_PSTATE_GFXCLK_LEVEL@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rbx
	cmpq	%rcx, %rbx
	jae	LBB0_6
## %bb.5:
	movl	(%rsi,%rbx,4), %ecx
	movl	%ecx, 176(%rax)
	movl	%ecx, 180(%rax)
LBB0_6:
	movq	8(%rdi), %r11
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %r11
	jne	LBB0_8
## %bb.7:
	movl	%edx, 176(%rax)
	movl	%edx, 180(%rax)
LBB0_8:
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPCREL(%rip), %rcx
	movq	(%rcx), %r8
	cmpq	%r8, %r11
	jne	LBB0_10
## %bb.9:
	movl	%r15d, 176(%rax)
	movl	%r15d, 180(%rax)
LBB0_10:
	movq	136(%rax), %r12
	movl	(%r12), %edx
	movl	%edx, 144(%rax)
	movslq	128(%rax), %rcx
	movl	-4(%r12,%rcx,4), %r15d
	movl	%r15d, 148(%rax)
	movl	%edx, 152(%rax)
	movl	%r15d, 156(%rax)
	movq	_VEGA20_UMD_PSTATE_MCLK_LEVEL@GOTPCREL(%rip), %rsi
	movq	(%rsi), %rsi
	cmpq	%rcx, %rsi
	jae	LBB0_12
## %bb.11:
	movl	(%r12,%rsi,4), %ecx
	movl	%ecx, 144(%rax)
	movl	%ecx, 148(%rax)
LBB0_12:
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %r11
	jne	LBB0_14
## %bb.13:
	movl	%edx, 144(%rax)
	movl	%edx, 148(%rax)
LBB0_14:
	cmpq	%r8, %r11
	jne	LBB0_16
## %bb.15:
	movl	%r15d, 144(%rax)
	movl	%r15d, 148(%rax)
LBB0_16:
	movslq	8(%r10), %rcx
	imulq	$1374389535, %rcx, %rbx         ## imm = 0x51EB851F
	movq	%rbx, %rcx
	shrq	$63, %rcx
	sarq	$37, %rbx
	addl	%ecx, %ebx
	cmpl	%ebx, %edx
	jge	LBB0_18
## %bb.17:
	movl	%ebx, 152(%rax)
LBB0_18:
	testb	%r9b, %r9b
	je	LBB0_25
## %bb.19:
	movl	%r15d, 152(%rax)
	movq	16(%rdi), %rsi
	movl	(%rsi), %edx
	cmpl	$2, %edx
	jl	LBB0_25
## %bb.20:
	decl	%edx
	movq	8(%rsi), %rdi
	xorl	%esi, %esi
	jmp	LBB0_21
	.p2align	4, 0x90
LBB0_24:                                ##   in Loop: Header=BB0_21 Depth=1
	incq	%rsi
	cmpq	%rsi, %rdx
	je	LBB0_25
LBB0_21:                                ## =>This Inner Loop Header: Depth=1
	cmpl	%r14d, (%rdi,%rsi,4)
	jg	LBB0_24
## %bb.22:                              ##   in Loop: Header=BB0_21 Depth=1
	movl	(%r12,%rsi,4), %ecx
	cmpl	%ebx, %ecx
	jl	LBB0_24
## %bb.23:
	movl	%ecx, 152(%rax)
LBB0_25:
	cmpq	$0, 16(%r10)
	je	LBB0_27
## %bb.26:
	movl	%r15d, 152(%rax)
LBB0_27:
	movq	104(%rax), %rsi
	movl	(%rsi), %ecx
	movl	%ecx, 112(%rax)
	movslq	96(%rax), %rdi
	movl	-4(%rsi,%rdi,4), %edx
	movl	%edx, 116(%rax)
	movl	%ecx, 120(%rax)
	movl	%edx, 124(%rax)
	movq	_VEGA20_UMD_PSTATE_UVDCLK_LEVEL@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	cmpq	%rdi, %rcx
	jae	LBB0_29
## %bb.28:
	movl	(%rsi,%rcx,4), %esi
	movl	%esi, 112(%rax)
	movl	%esi, 116(%rax)
LBB0_29:
	cmpq	%r8, %r11
	jne	LBB0_31
## %bb.30:
	movl	%edx, 112(%rax)
	movl	%edx, 116(%rax)
LBB0_31:
	movq	72(%rax), %rsi
	movl	(%rsi), %edi
	movl	%edi, 80(%rax)
	movslq	64(%rax), %rbx
	movl	-4(%rsi,%rbx,4), %edx
	movl	%edx, 84(%rax)
	movl	%edi, 88(%rax)
	movl	%edx, 92(%rax)
	cmpq	%rbx, %rcx
	jae	LBB0_33
## %bb.32:
	movl	(%rsi,%rcx,4), %ecx
	movl	%ecx, 80(%rax)
	movl	%ecx, 84(%rax)
LBB0_33:
	cmpq	%r8, %r11
	jne	LBB0_35
## %bb.34:
	movl	%edx, 80(%rax)
	movl	%edx, 84(%rax)
LBB0_35:
	movq	40(%rax), %rdx
	movl	(%rdx), %esi
	movl	%esi, 48(%rax)
	movslq	32(%rax), %rdi
	movl	-4(%rdx,%rdi,4), %ecx
	movl	%ecx, 52(%rax)
	movl	%esi, 56(%rax)
	movl	%ecx, 60(%rax)
	movq	_VEGA20_UMD_PSTATE_SOCCLK_LEVEL@GOTPCREL(%rip), %rsi
	movq	(%rsi), %rsi
	cmpq	%rdi, %rsi
	jae	LBB0_37
## %bb.36:
	movl	(%rdx,%rsi,4), %edx
	movl	%edx, 48(%rax)
	movl	%edx, 52(%rax)
LBB0_37:
	cmpq	%r8, %r11
	jne	LBB0_39
## %bb.38:
	movl	%ecx, 48(%rax)
	movl	%ecx, 52(%rax)
LBB0_39:
	movq	8(%rax), %rdx
	movl	(%rdx), %esi
	movl	%esi, 16(%rax)
	movslq	(%rax), %rdi
	movl	-4(%rdx,%rdi,4), %ecx
	movl	%ecx, 20(%rax)
	movl	%esi, 24(%rax)
	movl	%ecx, 28(%rax)
	movq	_VEGA20_UMD_PSTATE_VCEMCLK_LEVEL@GOTPCREL(%rip), %rsi
	movq	(%rsi), %rsi
	cmpq	%rdi, %rsi
	jae	LBB0_41
## %bb.40:
	movl	(%rdx,%rsi,4), %edx
	movl	%edx, 16(%rax)
	movl	%edx, 20(%rax)
LBB0_41:
	cmpq	%r8, %r11
	jne	LBB0_43
## %bb.42:
	movl	%ecx, 16(%rax)
	movl	%ecx, 20(%rax)
LBB0_43:
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	movb	$1, %r9b
	jmp	LBB0_4
	.cfi_endproc
                                        ## -- End function
	.comm	_VEGA20_UMD_PSTATE_GFXCLK_LEVEL,8,3 ## @VEGA20_UMD_PSTATE_GFXCLK_LEVEL
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK,8,3 ## @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,8,3 ## @AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
	.comm	_VEGA20_UMD_PSTATE_MCLK_LEVEL,8,3 ## @VEGA20_UMD_PSTATE_MCLK_LEVEL
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK,8,3 ## @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
	.comm	_VEGA20_UMD_PSTATE_UVDCLK_LEVEL,8,3 ## @VEGA20_UMD_PSTATE_UVDCLK_LEVEL
	.comm	_VEGA20_UMD_PSTATE_SOCCLK_LEVEL,8,3 ## @VEGA20_UMD_PSTATE_SOCCLK_LEVEL
	.comm	_VEGA20_UMD_PSTATE_VCEMCLK_LEVEL,8,3 ## @VEGA20_UMD_PSTATE_VCEMCLK_LEVEL
	.no_dead_strip	_vega20_apply_clocks_adjust_rules
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vega20_apply_clocks_adjust_rules
_vega20_apply_clocks_adjust_rules:      ; @vega20_apply_clocks_adjust_rules
	.cfi_startproc
; %bb.0:
	ldr	x8, [x0, #24]
	ldr	x11, [x0]
	ldr	w9, [x11]
	cmp	w9, #2
	b.lt	LBB0_2
; %bb.1:
	ldr	w9, [x11, #24]
	cbz	w9, LBB0_43
LBB0_2:
	mov	w13, #0
LBB0_3:
	ldr	w12, [x11, #4]
	ldr	x9, [x8, #168]
	ldr	w10, [x9]
	ldrsw	x16, [x8, #160]
	add	x14, x9, x16, lsl #2
	ldur	w14, [x14, #-4]
	stp	w10, w14, [x8, #176]
	stp	w10, w14, [x8, #184]
Lloh0:
	adrp	x15, _VEGA20_UMD_PSTATE_GFXCLK_LEVEL@GOTPAGE
Lloh1:
	ldr	x15, [x15, _VEGA20_UMD_PSTATE_GFXCLK_LEVEL@GOTPAGEOFF]
Lloh2:
	ldr	x15, [x15]
	cmp	x15, x16
	b.hs	LBB0_5
; %bb.4:
	ldr	w9, [x9, x15, lsl #2]
	stp	w9, w9, [x8, #176]
LBB0_5:
	ldr	x9, [x0, #8]
Lloh3:
	adrp	x15, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK@GOTPAGE
Lloh4:
	ldr	x15, [x15, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK@GOTPAGEOFF]
Lloh5:
	ldr	x15, [x15]
	cmp	x9, x15
	b.ne	LBB0_7
; %bb.6:
	stp	w10, w10, [x8, #176]
LBB0_7:
Lloh6:
	adrp	x10, _AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPAGE
Lloh7:
	ldr	x10, [x10, _AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPAGEOFF]
Lloh8:
	ldr	x10, [x10]
	cmp	x9, x10
	b.ne	LBB0_9
; %bb.8:
	stp	w14, w14, [x8, #176]
LBB0_9:
	ldr	x15, [x8, #136]
	ldr	w17, [x15]
	ldrsw	x1, [x8, #128]
	add	x14, x15, x1, lsl #2
	ldur	w14, [x14, #-4]
	stp	w17, w14, [x8, #144]
	stp	w17, w14, [x8, #152]
Lloh9:
	adrp	x16, _VEGA20_UMD_PSTATE_MCLK_LEVEL@GOTPAGE
Lloh10:
	ldr	x16, [x16, _VEGA20_UMD_PSTATE_MCLK_LEVEL@GOTPAGEOFF]
Lloh11:
	ldr	x16, [x16]
	cmp	x16, x1
	b.hs	LBB0_11
; %bb.10:
	ldr	w16, [x15, x16, lsl #2]
	stp	w16, w16, [x8, #144]
LBB0_11:
Lloh12:
	adrp	x16, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK@GOTPAGE
Lloh13:
	ldr	x16, [x16, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK@GOTPAGEOFF]
Lloh14:
	ldr	x16, [x16]
	cmp	x9, x16
	b.ne	LBB0_13
; %bb.12:
	stp	w17, w17, [x8, #144]
LBB0_13:
	cmp	x9, x10
	b.ne	LBB0_15
; %bb.14:
	stp	w14, w14, [x8, #144]
LBB0_15:
	ldrsw	x16, [x11, #8]
	mov	w1, #34079
	movk	w1, #20971, lsl #16
	mul	x16, x16, x1
	lsr	x1, x16, #63
	asr	x16, x16, #37
	add	w16, w16, w1
	cmp	w17, w16
	b.ge	LBB0_17
; %bb.16:
	str	w16, [x8, #152]
LBB0_17:
	cbz	w13, LBB0_24
; %bb.18:
	str	w14, [x8, #152]
	ldr	x17, [x0, #16]
	ldr	w13, [x17]
	cmp	w13, #2
	b.lt	LBB0_24
; %bb.19:
	sub	w13, w13, #1
	ldr	x17, [x17, #8]
	b	LBB0_21
LBB0_20:                                ;   in Loop: Header=BB0_21 Depth=1
	add	x17, x17, #4
	add	x15, x15, #4
	subs	x13, x13, #1
	b.eq	LBB0_24
LBB0_21:                                ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x17]
	cmp	w0, w12
	b.gt	LBB0_20
; %bb.22:                               ;   in Loop: Header=BB0_21 Depth=1
	ldr	w0, [x15]
	cmp	w0, w16
	b.lt	LBB0_20
; %bb.23:
	str	w0, [x8, #152]
LBB0_24:
	ldr	x11, [x11, #16]
	cbz	x11, LBB0_26
; %bb.25:
	str	w14, [x8, #152]
LBB0_26:
	ldr	x13, [x8, #104]
	ldr	w11, [x13]
	ldrsw	x14, [x8, #96]
	add	x12, x13, x14, lsl #2
	ldur	w12, [x12, #-4]
	stp	w11, w12, [x8, #112]
	stp	w11, w12, [x8, #120]
Lloh15:
	adrp	x11, _VEGA20_UMD_PSTATE_UVDCLK_LEVEL@GOTPAGE
Lloh16:
	ldr	x11, [x11, _VEGA20_UMD_PSTATE_UVDCLK_LEVEL@GOTPAGEOFF]
Lloh17:
	ldr	x11, [x11]
	cmp	x11, x14
	b.hs	LBB0_28
; %bb.27:
	ldr	w13, [x13, x11, lsl #2]
	stp	w13, w13, [x8, #112]
LBB0_28:
	cmp	x9, x10
	b.ne	LBB0_30
; %bb.29:
	stp	w12, w12, [x8, #112]
LBB0_30:
	ldr	x13, [x8, #72]
	ldr	w14, [x13]
	ldrsw	x15, [x8, #64]
	add	x12, x13, x15, lsl #2
	ldur	w12, [x12, #-4]
	stp	w14, w12, [x8, #80]
	stp	w14, w12, [x8, #88]
	cmp	x11, x15
	b.hs	LBB0_32
; %bb.31:
	ldr	w11, [x13, x11, lsl #2]
	stp	w11, w11, [x8, #80]
LBB0_32:
	cmp	x9, x10
	b.ne	LBB0_34
; %bb.33:
	stp	w12, w12, [x8, #80]
LBB0_34:
	ldr	x12, [x8, #40]
	ldr	w13, [x12]
	ldrsw	x14, [x8, #32]
	add	x11, x12, x14, lsl #2
	ldur	w11, [x11, #-4]
	stp	w13, w11, [x8, #48]
	stp	w13, w11, [x8, #56]
Lloh18:
	adrp	x13, _VEGA20_UMD_PSTATE_SOCCLK_LEVEL@GOTPAGE
Lloh19:
	ldr	x13, [x13, _VEGA20_UMD_PSTATE_SOCCLK_LEVEL@GOTPAGEOFF]
Lloh20:
	ldr	x13, [x13]
	cmp	x13, x14
	b.hs	LBB0_36
; %bb.35:
	ldr	w12, [x12, x13, lsl #2]
	stp	w12, w12, [x8, #48]
LBB0_36:
	cmp	x9, x10
	b.ne	LBB0_38
; %bb.37:
	stp	w11, w11, [x8, #48]
LBB0_38:
	ldr	x12, [x8, #8]
	ldr	w13, [x12]
	ldrsw	x14, [x8]
	add	x11, x12, x14, lsl #2
	ldur	w11, [x11, #-4]
	stp	w13, w11, [x8, #16]
	stp	w13, w11, [x8, #24]
Lloh21:
	adrp	x13, _VEGA20_UMD_PSTATE_VCEMCLK_LEVEL@GOTPAGE
Lloh22:
	ldr	x13, [x13, _VEGA20_UMD_PSTATE_VCEMCLK_LEVEL@GOTPAGEOFF]
Lloh23:
	ldr	x13, [x13]
	cmp	x13, x14
	b.lo	LBB0_41
; %bb.39:
	cmp	x9, x10
	b.eq	LBB0_42
LBB0_40:
	mov	w0, #0
	ret
LBB0_41:
	ldr	w12, [x12, x13, lsl #2]
	stp	w12, w12, [x8, #16]
	cmp	x9, x10
	b.ne	LBB0_40
LBB0_42:
	stp	w11, w11, [x8, #16]
	mov	w0, #0
	ret
LBB0_43:
	mov	w13, #1
	b	LBB0_3
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.cfi_endproc
                                        ; -- End function
	.comm	_VEGA20_UMD_PSTATE_GFXCLK_LEVEL,8,3 ; @VEGA20_UMD_PSTATE_GFXCLK_LEVEL
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK,8,3 ; @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,8,3 ; @AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
	.comm	_VEGA20_UMD_PSTATE_MCLK_LEVEL,8,3 ; @VEGA20_UMD_PSTATE_MCLK_LEVEL
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK,8,3 ; @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
	.comm	_VEGA20_UMD_PSTATE_UVDCLK_LEVEL,8,3 ; @VEGA20_UMD_PSTATE_UVDCLK_LEVEL
	.comm	_VEGA20_UMD_PSTATE_SOCCLK_LEVEL,8,3 ; @VEGA20_UMD_PSTATE_SOCCLK_LEVEL
	.comm	_VEGA20_UMD_PSTATE_VCEMCLK_LEVEL,8,3 ; @VEGA20_UMD_PSTATE_VCEMCLK_LEVEL
	.no_dead_strip	_vega20_apply_clocks_adjust_rules
.subsections_via_symbols
