	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v8_0_cp_gfx_start
_gfx_v8_0_cp_gfx_start:                 ## @gfx_v8_0_cp_gfx_start
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	16(%rdi), %rbx
	movq	_mmCP_MAX_CONTEXT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r15), %esi
	decl	%esi
	callq	_WREG32
	movq	_mmCP_ENDIAN_SWAP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmCP_DEVICE_ID@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_WREG32
	movq	%r15, %rdi
	movl	$1, %esi
	callq	_gfx_v8_0_cp_gfx_enable
	movq	%r15, %rdi
	callq	_gfx_v8_0_get_csb_size
	leaq	4(%rax), %rsi
	movq	%rbx, %rdi
	callq	_amdgpu_ring_alloc
	testl	%eax, %eax
	je	LBB0_2
## %bb.1:
	movl	%eax, %r14d
	leaq	L_.str(%rip), %rdi
	movl	%eax, %esi
	callq	_DRM_ERROR
	jmp	LBB0_12
LBB0_2:
	movq	%r15, -48(%rbp)                 ## 8-byte Spill
	movq	_PACKET3_PREAMBLE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET3
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_PACKET3_PREAMBLE_BEGIN_CLEAR_STATE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_amdgpu_ring_write
	movq	_PACKET3_CONTEXT_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_PACKET3
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$-2147483648, %esi              ## imm = 0x80000000
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$-2147483648, %esi              ## imm = 0x80000000
	callq	_amdgpu_ring_write
	movq	_vi_cs_data@GOTPCREL(%rip), %rax
	movq	(%rax), %r13
	movq	8(%r13), %r12
	testq	%r12, %r12
	je	LBB0_11
## %bb.3:
	movq	_SECT_CONTEXT@GOTPCREL(%rip), %r14
	jmp	LBB0_4
	.p2align	4, 0x90
LBB0_10:                                ##   in Loop: Header=BB0_4 Depth=1
	movq	24(%r13), %r12
	addq	$16, %r13
	testq	%r12, %r12
	je	LBB0_11
LBB0_4:                                 ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_5 Depth 2
                                        ##       Child Loop BB0_8 Depth 3
	cmpq	$0, (%r12)
	jne	LBB0_5
	jmp	LBB0_10
	.p2align	4, 0x90
LBB0_9:                                 ##   in Loop: Header=BB0_5 Depth=2
	cmpq	$0, 16(%r12)
	leaq	16(%r12), %r12
	je	LBB0_10
LBB0_5:                                 ##   Parent Loop BB0_4 Depth=1
                                        ## =>  This Loop Header: Depth=2
                                        ##       Child Loop BB0_8 Depth 3
	movq	(%r13), %rax
	cmpq	(%r14), %rax
	jne	LBB0_9
## %bb.6:                               ##   in Loop: Header=BB0_5 Depth=2
	movq	_PACKET3_SET_CONTEXT_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	8(%r12), %esi
	callq	_PACKET3
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	12(%r12), %esi
	movq	_PACKET3_SET_CONTEXT_REG_START@GOTPCREL(%rip), %rax
	subl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_amdgpu_ring_write
	cmpl	$0, 8(%r12)
	jle	LBB0_9
## %bb.7:                               ##   in Loop: Header=BB0_5 Depth=2
	xorl	%r15d, %r15d
	.p2align	4, 0x90
LBB0_8:                                 ##   Parent Loop BB0_4 Depth=1
                                        ##     Parent Loop BB0_5 Depth=2
                                        ## =>    This Inner Loop Header: Depth=3
	movq	(%r12), %rax
	movl	(%rax,%r15,4), %esi
	movq	%rbx, %rdi
	callq	_amdgpu_ring_write
	incq	%r15
	movslq	8(%r12), %rax
	cmpq	%rax, %r15
	jl	LBB0_8
	jmp	LBB0_9
LBB0_11:
	movq	_PACKET3_SET_CONTEXT_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$2, %esi
	callq	_PACKET3
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_mmPA_SC_RASTER_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PACKET3_SET_CONTEXT_REG_START@GOTPCREL(%rip), %rax
	subl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_amdgpu_ring_write
	movq	-48(%rbp), %r14                 ## 8-byte Reload
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_amdgpu_ring_write
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	4(%rax), %esi
	movq	%rbx, %rdi
	callq	_amdgpu_ring_write
	movq	_PACKET3_PREAMBLE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET3
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_PACKET3_PREAMBLE_END_CLEAR_STATE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_amdgpu_ring_write
	movq	_PACKET3_CLEAR_STATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET3
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
	movq	_PACKET3_SET_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$2, %esi
	callq	_PACKET3
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_CE_PARTITION_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_PACKET3_BASE_INDEX
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$32768, %esi                    ## imm = 0x8000
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$32768, %esi                    ## imm = 0x8000
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	callq	_amdgpu_ring_commit
	xorl	%r14d, %r14d
LBB0_12:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_mmCP_MAX_CONTEXT,4,2           ## @mmCP_MAX_CONTEXT
	.comm	_mmCP_ENDIAN_SWAP,4,2           ## @mmCP_ENDIAN_SWAP
	.comm	_mmCP_DEVICE_ID,4,2             ## @mmCP_DEVICE_ID
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"amdgpu: cp failed to lock ring (%d).\n"

	.comm	_PACKET3_PREAMBLE_CNTL,4,2      ## @PACKET3_PREAMBLE_CNTL
	.comm	_PACKET3_PREAMBLE_BEGIN_CLEAR_STATE,4,2 ## @PACKET3_PREAMBLE_BEGIN_CLEAR_STATE
	.comm	_PACKET3_CONTEXT_CONTROL,4,2    ## @PACKET3_CONTEXT_CONTROL
	.comm	_vi_cs_data,8,3                 ## @vi_cs_data
	.comm	_SECT_CONTEXT,8,3               ## @SECT_CONTEXT
	.comm	_PACKET3_SET_CONTEXT_REG,4,2    ## @PACKET3_SET_CONTEXT_REG
	.comm	_PACKET3_SET_CONTEXT_REG_START,4,2 ## @PACKET3_SET_CONTEXT_REG_START
	.comm	_mmPA_SC_RASTER_CONFIG,4,2      ## @mmPA_SC_RASTER_CONFIG
	.comm	_PACKET3_PREAMBLE_END_CLEAR_STATE,4,2 ## @PACKET3_PREAMBLE_END_CLEAR_STATE
	.comm	_PACKET3_CLEAR_STATE,4,2        ## @PACKET3_CLEAR_STATE
	.comm	_PACKET3_SET_BASE,4,2           ## @PACKET3_SET_BASE
	.comm	_CE_PARTITION_BASE,4,2          ## @CE_PARTITION_BASE
	.no_dead_strip	_gfx_v8_0_cp_gfx_start
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v8_0_cp_gfx_start
_gfx_v8_0_cp_gfx_start:                 ; @gfx_v8_0_cp_gfx_start
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x20, x0
	ldr	x19, [x0, #16]
Lloh0:
	adrp	x8, _mmCP_MAX_CONTEXT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _mmCP_MAX_CONTEXT@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	ldr	w8, [x20]
	sub	w1, w8, #1
	bl	_WREG32
Lloh3:
	adrp	x8, _mmCP_ENDIAN_SWAP@GOTPAGE
Lloh4:
	ldr	x8, [x8, _mmCP_ENDIAN_SWAP@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh6:
	adrp	x8, _mmCP_DEVICE_ID@GOTPAGE
Lloh7:
	ldr	x8, [x8, _mmCP_DEVICE_ID@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_WREG32
	mov	x0, x20
	mov	w1, #1
	bl	_gfx_v8_0_cp_gfx_enable
	mov	x0, x20
	bl	_gfx_v8_0_get_csb_size
	add	x1, x0, #4
	mov	x0, x19
	bl	_amdgpu_ring_alloc
	cbz	w0, LBB0_2
; %bb.1:
	mov	x21, x0
Lloh9:
	adrp	x0, l_.str@PAGE
Lloh10:
	add	x0, x0, l_.str@PAGEOFF
	mov	x1, x21
	bl	_DRM_ERROR
	b	LBB0_12
LBB0_2:
Lloh11:
	adrp	x21, _PACKET3_PREAMBLE_CNTL@GOTPAGE
Lloh12:
	ldr	x21, [x21, _PACKET3_PREAMBLE_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	mov	w1, #0
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh13:
	adrp	x8, _PACKET3_PREAMBLE_BEGIN_CLEAR_STATE@GOTPAGE
Lloh14:
	ldr	x8, [x8, _PACKET3_PREAMBLE_BEGIN_CLEAR_STATE@GOTPAGEOFF]
Lloh15:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh16:
	adrp	x8, _PACKET3_CONTEXT_CONTROL@GOTPAGE
Lloh17:
	ldr	x8, [x8, _PACKET3_CONTEXT_CONTROL@GOTPAGEOFF]
Lloh18:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #-2147483648
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #-2147483648
	bl	_amdgpu_ring_write
Lloh19:
	adrp	x8, _vi_cs_data@GOTPAGE
Lloh20:
	ldr	x8, [x8, _vi_cs_data@GOTPAGEOFF]
Lloh21:
	ldr	x24, [x8]
	ldr	x25, [x24, #8]
Lloh22:
	adrp	x23, _PACKET3_SET_CONTEXT_REG@GOTPAGE
Lloh23:
	ldr	x23, [x23, _PACKET3_SET_CONTEXT_REG@GOTPAGEOFF]
Lloh24:
	adrp	x22, _PACKET3_SET_CONTEXT_REG_START@GOTPAGE
Lloh25:
	ldr	x22, [x22, _PACKET3_SET_CONTEXT_REG_START@GOTPAGEOFF]
	cbz	x25, LBB0_11
; %bb.3:
Lloh26:
	adrp	x26, _SECT_CONTEXT@GOTPAGE
Lloh27:
	ldr	x26, [x26, _SECT_CONTEXT@GOTPAGEOFF]
	b	LBB0_5
LBB0_4:                                 ;   in Loop: Header=BB0_5 Depth=1
	ldr	x25, [x24, #24]
	add	x24, x24, #16
	cbz	x25, LBB0_11
LBB0_5:                                 ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
                                        ;       Child Loop BB0_10 Depth 3
	ldr	x8, [x25]
	cbnz	x8, LBB0_7
	b	LBB0_4
LBB0_6:                                 ;   in Loop: Header=BB0_7 Depth=2
	ldr	x8, [x25, #16]!
	cbz	x8, LBB0_4
LBB0_7:                                 ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_10 Depth 3
	ldr	x8, [x24]
	ldr	x9, [x26]
	cmp	x8, x9
	b.ne	LBB0_6
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=2
	ldr	w0, [x23]
	ldr	w1, [x25, #8]
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w8, [x25, #12]
	ldr	w9, [x22]
	sub	w1, w8, w9
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w8, [x25, #8]
	cmp	w8, #1
	b.lt	LBB0_6
; %bb.9:                                ;   in Loop: Header=BB0_7 Depth=2
	mov	x27, #0
LBB0_10:                                ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_7 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	ldr	x8, [x25]
	ldr	w1, [x8, x27, lsl #2]
	mov	x0, x19
	bl	_amdgpu_ring_write
	add	x27, x27, #1
	ldrsw	x8, [x25, #8]
	cmp	x27, x8
	b.lt	LBB0_10
	b	LBB0_6
LBB0_11:
	ldr	w0, [x23]
	mov	w1, #2
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh28:
	adrp	x8, _mmPA_SC_RASTER_CONFIG@GOTPAGE
Lloh29:
	ldr	x8, [x8, _mmPA_SC_RASTER_CONFIG@GOTPAGEOFF]
Lloh30:
	ldr	w8, [x8]
	ldr	w9, [x22]
	sub	w1, w8, w9
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w1, [x8]
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w1, [x8, #4]
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x21]
	mov	w1, #0
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh31:
	adrp	x8, _PACKET3_PREAMBLE_END_CLEAR_STATE@GOTPAGE
Lloh32:
	ldr	x8, [x8, _PACKET3_PREAMBLE_END_CLEAR_STATE@GOTPAGEOFF]
Lloh33:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh34:
	adrp	x8, _PACKET3_CLEAR_STATE@GOTPAGE
Lloh35:
	ldr	x8, [x8, _PACKET3_CLEAR_STATE@GOTPAGEOFF]
Lloh36:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_ring_write
Lloh37:
	adrp	x8, _PACKET3_SET_BASE@GOTPAGE
Lloh38:
	ldr	x8, [x8, _PACKET3_SET_BASE@GOTPAGEOFF]
Lloh39:
	ldr	w0, [x8]
	mov	w1, #2
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh40:
	adrp	x8, _CE_PARTITION_BASE@GOTPAGE
Lloh41:
	ldr	x8, [x8, _CE_PARTITION_BASE@GOTPAGEOFF]
Lloh42:
	ldr	w0, [x8]
	bl	_PACKET3_BASE_INDEX
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #32768
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #32768
	bl	_amdgpu_ring_write
	mov	x0, x19
	bl	_amdgpu_ring_commit
	mov	w21, #0
LBB0_12:
	mov	x0, x21
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.cfi_endproc
                                        ; -- End function
	.comm	_mmCP_MAX_CONTEXT,4,2           ; @mmCP_MAX_CONTEXT
	.comm	_mmCP_ENDIAN_SWAP,4,2           ; @mmCP_ENDIAN_SWAP
	.comm	_mmCP_DEVICE_ID,4,2             ; @mmCP_DEVICE_ID
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"amdgpu: cp failed to lock ring (%d).\n"

	.comm	_PACKET3_PREAMBLE_CNTL,4,2      ; @PACKET3_PREAMBLE_CNTL
	.comm	_PACKET3_PREAMBLE_BEGIN_CLEAR_STATE,4,2 ; @PACKET3_PREAMBLE_BEGIN_CLEAR_STATE
	.comm	_PACKET3_CONTEXT_CONTROL,4,2    ; @PACKET3_CONTEXT_CONTROL
	.comm	_vi_cs_data,8,3                 ; @vi_cs_data
	.comm	_SECT_CONTEXT,8,3               ; @SECT_CONTEXT
	.comm	_PACKET3_SET_CONTEXT_REG,4,2    ; @PACKET3_SET_CONTEXT_REG
	.comm	_PACKET3_SET_CONTEXT_REG_START,4,2 ; @PACKET3_SET_CONTEXT_REG_START
	.comm	_mmPA_SC_RASTER_CONFIG,4,2      ; @mmPA_SC_RASTER_CONFIG
	.comm	_PACKET3_PREAMBLE_END_CLEAR_STATE,4,2 ; @PACKET3_PREAMBLE_END_CLEAR_STATE
	.comm	_PACKET3_CLEAR_STATE,4,2        ; @PACKET3_CLEAR_STATE
	.comm	_PACKET3_SET_BASE,4,2           ; @PACKET3_SET_BASE
	.comm	_CE_PARTITION_BASE,4,2          ; @CE_PARTITION_BASE
	.no_dead_strip	_gfx_v8_0_cp_gfx_start
.subsections_via_symbols
