	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vce_v3_0_set_vce_sw_clock_gating
_vce_v3_0_set_vce_sw_clock_gating:      ## @vce_v3_0_set_vce_sw_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %ebx
	movq	%rdi, %r14
	movl	$1, %esi
	callq	_vce_v3_0_override_vce_clock_gating
	movq	_mmVCE_CLOCK_GATING_B@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32
	testl	%ebx, %ebx
	je	LBB0_1
## %bb.2:
	andl	$-15663129, %eax                ## imm = 0xFF10FFE7
	orl	$15138824, %eax                 ## imm = 0xE70008
	movl	(%r15), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmVCE_UENC_CLOCK_GATING@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	orl	$-4194304, %eax                 ## imm = 0xFFC00000
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmVCE_UENC_CLOCK_GATING_2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	orl	$65536, %eax                    ## imm = 0x10000
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmVCE_UENC_REG_CLOCK_GATING@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	andl	$-1024, %eax                    ## imm = 0xFC00
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmVCE_UENC_DMA_DCLK_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK@GOTPCREL(%rip), %rcx
	movq	_VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	movq	_VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	andl	$-9, %esi
	jmp	LBB0_3
LBB0_1:
	andl	$-15663616, %eax                ## imm = 0xFF10FE00
	orl	$511, %eax                      ## imm = 0x1FF
	movl	(%r15), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmVCE_UENC_CLOCK_GATING@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	orl	$4190208, %eax                  ## imm = 0x3FF000
	andl	$4194303, %eax                  ## imm = 0x3FFFFF
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmVCE_UENC_CLOCK_GATING_2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
                                        ## kill: def $eax killed $eax def $rax
	andl	$-65539, %eax                   ## imm = 0xFFFEFFFD
	leal	2(%rax), %esi
	movl	(%rbx), %edi
	callq	_WREG32
	movq	_mmVCE_UENC_REG_CLOCK_GATING@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	orl	$895, %eax                      ## imm = 0x37F
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmVCE_UENC_DMA_DCLK_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %esi
	movq	_VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK@GOTPCREL(%rip), %rax
	movq	_VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK@GOTPCREL(%rip), %rcx
	orl	(%rax), %esi
	orl	(%rcx), %esi
	movq	_VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	orl	$8, %esi
LBB0_3:
	movq	_mmVCE_UENC_DMA_DCLK_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32
	movq	%r14, %rdi
	xorl	%esi, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_vce_v3_0_override_vce_clock_gating ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_mmVCE_CLOCK_GATING_B,4,2       ## @mmVCE_CLOCK_GATING_B
	.comm	_mmVCE_UENC_CLOCK_GATING,4,2    ## @mmVCE_UENC_CLOCK_GATING
	.comm	_mmVCE_UENC_CLOCK_GATING_2,4,2  ## @mmVCE_UENC_CLOCK_GATING_2
	.comm	_mmVCE_UENC_REG_CLOCK_GATING,4,2 ## @mmVCE_UENC_REG_CLOCK_GATING
	.comm	_mmVCE_UENC_DMA_DCLK_CTRL,4,2   ## @mmVCE_UENC_DMA_DCLK_CTRL
	.comm	_VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK,4,2 ## @VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK
	.comm	_VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK,4,2 ## @VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK
	.comm	_VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK,4,2 ## @VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK
	.no_dead_strip	_vce_v3_0_set_vce_sw_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vce_v3_0_set_vce_sw_clock_gating
_vce_v3_0_set_vce_sw_clock_gating:      ; @vce_v3_0_set_vce_sw_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x1
	mov	x19, x0
	mov	w22, #65024
	movk	w22, #65296, lsl #16
	mov	w1, #1
	bl	_vce_v3_0_override_vce_clock_gating
Lloh0:
	adrp	x23, _mmVCE_CLOCK_GATING_B@GOTPAGE
Lloh1:
	ldr	x23, [x23, _mmVCE_CLOCK_GATING_B@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_RREG32
Lloh2:
	adrp	x21, _mmVCE_UENC_DMA_DCLK_CTRL@GOTPAGE
Lloh3:
	ldr	x21, [x21, _mmVCE_UENC_DMA_DCLK_CTRL@GOTPAGEOFF]
	cbz	w20, LBB0_2
; %bb.1:
	add	w8, w22, #487
	and	w8, w0, w8
	mov	w9, #8
	movk	w9, #231, lsl #16
	orr	w1, w8, w9
	ldr	w0, [x23]
	bl	_WREG32
Lloh4:
	adrp	x20, _mmVCE_UENC_CLOCK_GATING@GOTPAGE
Lloh5:
	ldr	x20, [x20, _mmVCE_UENC_CLOCK_GATING@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	orr	w1, w0, #0xffc00000
	ldr	w0, [x20]
	bl	_WREG32
Lloh6:
	adrp	x20, _mmVCE_UENC_CLOCK_GATING_2@GOTPAGE
Lloh7:
	ldr	x20, [x20, _mmVCE_UENC_CLOCK_GATING_2@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	orr	w1, w0, #0x10000
	ldr	w0, [x20]
	bl	_WREG32
Lloh8:
	adrp	x20, _mmVCE_UENC_REG_CLOCK_GATING@GOTPAGE
Lloh9:
	ldr	x20, [x20, _mmVCE_UENC_REG_CLOCK_GATING@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	and	w1, w0, #0xfffffc00
	ldr	w0, [x20]
	bl	_WREG32
	ldr	w0, [x21]
	bl	_RREG32
Lloh10:
	adrp	x8, _VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK@GOTPAGE
Lloh11:
	ldr	x8, [x8, _VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
Lloh13:
	adrp	x9, _VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK@GOTPAGE
Lloh14:
	ldr	x9, [x9, _VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh16:
	adrp	x9, _VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK@GOTPAGE
Lloh17:
	ldr	x9, [x9, _VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w8, w0, w8
	and	w1, w8, #0xfffffff7
	b	LBB0_3
LBB0_2:
	and	w8, w0, w22
	orr	w1, w8, #0x1ff
	ldr	w0, [x23]
	bl	_WREG32
Lloh19:
	adrp	x20, _mmVCE_UENC_CLOCK_GATING@GOTPAGE
Lloh20:
	ldr	x20, [x20, _mmVCE_UENC_CLOCK_GATING@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	mov	w1, #4190208
	bfxil	w1, w0, #0, #12
	ldr	w0, [x20]
	bl	_WREG32
Lloh21:
	adrp	x20, _mmVCE_UENC_CLOCK_GATING_2@GOTPAGE
Lloh22:
	ldr	x20, [x20, _mmVCE_UENC_CLOCK_GATING_2@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	and	w8, w0, #0xfffeffff
	orr	w1, w8, #0x2
	ldr	w0, [x20]
	bl	_WREG32
Lloh23:
	adrp	x20, _mmVCE_UENC_REG_CLOCK_GATING@GOTPAGE
Lloh24:
	ldr	x20, [x20, _mmVCE_UENC_REG_CLOCK_GATING@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	mov	w8, #895
	orr	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32
	ldr	w0, [x21]
	bl	_RREG32
Lloh25:
	adrp	x8, _VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK@GOTPAGE
Lloh26:
	ldr	x8, [x8, _VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
Lloh28:
	adrp	x9, _VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK@GOTPAGE
Lloh29:
	ldr	x9, [x9, _VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK@GOTPAGEOFF]
Lloh30:
	adrp	x10, _VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK@GOTPAGE
Lloh31:
	ldr	x10, [x10, _VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
Lloh33:
	ldr	w10, [x10]
	orr	w8, w0, w8
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w1, w8, #0x8
LBB0_3:
	ldr	w0, [x21]
	bl	_WREG32
	mov	x0, x19
	mov	w1, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_vce_v3_0_override_vce_clock_gating
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh32
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.cfi_endproc
                                        ; -- End function
	.comm	_mmVCE_CLOCK_GATING_B,4,2       ; @mmVCE_CLOCK_GATING_B
	.comm	_mmVCE_UENC_CLOCK_GATING,4,2    ; @mmVCE_UENC_CLOCK_GATING
	.comm	_mmVCE_UENC_CLOCK_GATING_2,4,2  ; @mmVCE_UENC_CLOCK_GATING_2
	.comm	_mmVCE_UENC_REG_CLOCK_GATING,4,2 ; @mmVCE_UENC_REG_CLOCK_GATING
	.comm	_mmVCE_UENC_DMA_DCLK_CTRL,4,2   ; @mmVCE_UENC_DMA_DCLK_CTRL
	.comm	_VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK,4,2 ; @VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK
	.comm	_VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK,4,2 ; @VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK
	.comm	_VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK,4,2 ; @VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK
	.no_dead_strip	_vce_v3_0_set_vce_sw_clock_gating
.subsections_via_symbols
