	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v9_0_cp_resume
_gfx_v9_0_cp_resume:                    ## @gfx_v9_0_cp_resume
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rdi)
	jne	LBB0_2
## %bb.1:
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_gfx_v9_0_enable_gui_idle_interrupt
LBB0_2:
	movq	40(%r15), %rax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_6
## %bb.3:
	movq	8(%r15), %rax
	movq	_CHIP_ARCTURUS@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_5
## %bb.4:
	movq	%r15, %rdi
	callq	_gfx_v9_0_cp_gfx_load_microcode
	testl	%eax, %eax
	jne	LBB0_16
LBB0_5:
	movq	%r15, %rdi
	callq	_gfx_v9_0_cp_compute_load_microcode
	testl	%eax, %eax
	jne	LBB0_16
LBB0_6:
	movq	%r15, %rdi
	callq	_gfx_v9_0_kiq_resume
	testl	%eax, %eax
	je	LBB0_7
LBB0_16:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_7:
	movq	8(%r15), %rax
	movq	_CHIP_ARCTURUS@GOTPCREL(%rip), %r14
	cmpq	(%r14), %rax
	je	LBB0_9
## %bb.8:
	movq	%r15, %rdi
	callq	_gfx_v9_0_cp_gfx_resume
	testl	%eax, %eax
	jne	LBB0_16
LBB0_9:
	movq	%r15, %rdi
	callq	_gfx_v9_0_kcq_resume
	testl	%eax, %eax
	jne	LBB0_16
## %bb.10:
	movq	8(%r15), %rax
	cmpq	(%r14), %rax
	je	LBB0_12
## %bb.11:
	movq	32(%r15), %rdi
	callq	_amdgpu_ring_test_helper
	testl	%eax, %eax
	jne	LBB0_16
LBB0_12:
	cmpl	$0, 16(%r15)
	jle	LBB0_15
## %bb.13:
	xorl	%r14d, %r14d
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_14:                                ## =>This Inner Loop Header: Depth=1
	movq	24(%r15), %rdi
	addq	%r14, %rdi
	callq	_amdgpu_ring_test_helper
	incq	%rbx
	movslq	16(%r15), %rax
	addq	$4, %r14
	cmpq	%rax, %rbx
	jl	LBB0_14
LBB0_15:
	movq	%r15, %rdi
	movl	$1, %esi
	callq	_gfx_v9_0_enable_gui_idle_interrupt
	xorl	%eax, %eax
	jmp	LBB0_16
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_CHIP_ARCTURUS,8,3              ## @CHIP_ARCTURUS
	.no_dead_strip	_gfx_v9_0_cp_resume
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v9_0_cp_resume
_gfx_v9_0_cp_resume:                    ; @gfx_v9_0_cp_resume
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _AMD_IS_APU@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_IS_APU@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_2
; %bb.1:
	mov	x0, x19
	mov	w1, #0
	bl	_gfx_v9_0_enable_gui_idle_interrupt
LBB0_2:
	ldr	x8, [x19, #40]
Lloh3:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh4:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_6
; %bb.3:
	ldr	x8, [x19, #8]
Lloh6:
	adrp	x9, _CHIP_ARCTURUS@GOTPAGE
Lloh7:
	ldr	x9, [x9, _CHIP_ARCTURUS@GOTPAGEOFF]
Lloh8:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_5
; %bb.4:
	mov	x0, x19
	bl	_gfx_v9_0_cp_gfx_load_microcode
	cbnz	w0, LBB0_7
LBB0_5:
	mov	x0, x19
	bl	_gfx_v9_0_cp_compute_load_microcode
	cbnz	w0, LBB0_7
LBB0_6:
	mov	x0, x19
	bl	_gfx_v9_0_kiq_resume
	cbz	w0, LBB0_8
LBB0_7:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_8:
	ldr	x8, [x19, #8]
Lloh9:
	adrp	x20, _CHIP_ARCTURUS@GOTPAGE
Lloh10:
	ldr	x20, [x20, _CHIP_ARCTURUS@GOTPAGEOFF]
	ldr	x9, [x20]
	cmp	x8, x9
	b.eq	LBB0_10
; %bb.9:
	mov	x0, x19
	bl	_gfx_v9_0_cp_gfx_resume
	cbnz	w0, LBB0_7
LBB0_10:
	mov	x0, x19
	bl	_gfx_v9_0_kcq_resume
	cbnz	w0, LBB0_7
; %bb.11:
	ldr	x8, [x19, #8]
	ldr	x9, [x20]
	cmp	x8, x9
	b.eq	LBB0_13
; %bb.12:
	ldr	x0, [x19, #32]
	bl	_amdgpu_ring_test_helper
	cbnz	w0, LBB0_7
LBB0_13:
	ldr	w8, [x19, #16]
	cmp	w8, #1
	b.lt	LBB0_16
; %bb.14:
	mov	x20, #0
	mov	x21, #0
LBB0_15:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #24]
	add	x0, x8, x20
	bl	_amdgpu_ring_test_helper
	add	x21, x21, #1
	ldrsw	x8, [x19, #16]
	add	x20, x20, #4
	cmp	x21, x8
	b.lt	LBB0_15
LBB0_16:
	mov	x0, x19
	mov	w1, #1
	bl	_gfx_v9_0_enable_gui_idle_interrupt
	mov	w0, #0
	b	LBB0_7
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh9, Lloh10
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_CHIP_ARCTURUS,8,3              ; @CHIP_ARCTURUS
	.no_dead_strip	_gfx_v9_0_cp_resume
.subsections_via_symbols
