	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function validate_uniform_address_write
_validate_uniform_address_write:        ## @validate_uniform_address_write
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r12d
	movq	%rsi, %rbx
	movq	%rdi, %r14
	movq	(%rsi), %rax
	movq	8(%rsi), %rcx
	movl	(%rax,%rcx,4), %r15d
	movq	_QPU_ADD_B@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r15d, %edi
	callq	_QPU_GET_FIELD
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movq	_QPU_RADDR_A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r15d, %edi
	callq	_QPU_GET_FIELD
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_QPU_RADDR_B@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r15d, %edi
	callq	_QPU_GET_FIELD
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movl	%r15d, %edi
	callq	_raddr_add_a_to_live_reg_index
	movl	%eax, %r13d
	movl	(%r14), %eax
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	movq	_QPU_SIG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r15d, %edi
	callq	_QPU_GET_FIELD
	addl	$-128, %eax
	cmpl	$5, %eax
	jae	LBB0_1
## %bb.3:
	testl	%r12d, %r12d
	jne	LBB0_5
## %bb.4:
	movq	_QPU_OP_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r15d, %edi
	callq	_QPU_GET_FIELD
	movq	_QPU_A_ADD@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_5
## %bb.6:
	movq	_QPU_COND_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r15d, %edi
	callq	_QPU_GET_FIELD
	movq	_QPU_COND_ALWAYS@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_7
## %bb.8:
	movq	_QPU_PACK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r15d, %edi
	callq	_QPU_GET_FIELD
	movq	_QPU_PACK_A_NOP@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_11
## %bb.9:
	movq	_QPU_PM@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_10
LBB0_11:
	cmpl	$-1, %r13d
	je	LBB0_12
## %bb.13:
	movl	-56(%rbp), %edx                 ## 4-byte Reload
	addl	$4, %edx
	movq	16(%rbx), %rax
	movslq	%r13d, %rcx
	movl	(%rax,%rcx,4), %esi
	cmpl	%edx, %esi
	jne	LBB0_14
## %bb.16:
	movq	_QPU_MUX_A@GOTPCREL(%rip), %rcx
	movq	_QPU_R_UNIF@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	-52(%rbp), %edx                 ## 4-byte Reload
	cmpl	(%rcx), %edx
	jne	LBB0_18
## %bb.17:
	cmpl	%eax, -48(%rbp)                 ## 4-byte Folded Reload
	je	LBB0_21
LBB0_18:
	movq	_QPU_MUX_B@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %edx
	jne	LBB0_20
## %bb.19:
	cmpl	%eax, -44(%rbp)                 ## 4-byte Folded Reload
	jne	LBB0_20
LBB0_21:
	movq	$0, 24(%rbx)
	movq	%r14, %rdi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_require_uniform_address_uniform ## TAILCALL
LBB0_1:
	leaq	L_.str(%rip), %rdi
	jmp	LBB0_2
LBB0_5:
	leaq	L_.str.1(%rip), %rdi
LBB0_2:
	xorl	%eax, %eax
	callq	_DRM_DEBUG
LBB0_15:
	xorl	%eax, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_7:
	leaq	L_.str.2(%rip), %rdi
	jmp	LBB0_2
LBB0_12:
	leaq	L_.str.4(%rip), %rdi
	jmp	LBB0_2
LBB0_14:
	leaq	L_.str.5(%rip), %rdi
	xorl	%eax, %eax
	callq	_DRM_DEBUG
	jmp	LBB0_15
LBB0_10:
	leaq	L_.str.3(%rip), %rdi
	jmp	LBB0_2
LBB0_20:
	leaq	L_.str.6(%rip), %rdi
	jmp	LBB0_2
	.cfi_endproc
                                        ## -- End function
	.comm	_QPU_ADD_B,4,2                  ## @QPU_ADD_B
	.comm	_QPU_RADDR_A,4,2                ## @QPU_RADDR_A
	.comm	_QPU_RADDR_B,4,2                ## @QPU_RADDR_B
	.comm	_QPU_SIG,4,2                    ## @QPU_SIG
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"uniforms address change must be normal math\n"

	.comm	_QPU_OP_ADD,4,2                 ## @QPU_OP_ADD
	.comm	_QPU_A_ADD,4,2                  ## @QPU_A_ADD
L_.str.1:                               ## @.str.1
	.asciz	"Uniform address reset must be an ADD.\n"

	.comm	_QPU_COND_ADD,4,2               ## @QPU_COND_ADD
	.comm	_QPU_COND_ALWAYS,4,2            ## @QPU_COND_ALWAYS
L_.str.2:                               ## @.str.2
	.asciz	"Uniform address reset must be unconditional.\n"

	.comm	_QPU_PACK,4,2                   ## @QPU_PACK
	.comm	_QPU_PACK_A_NOP,4,2             ## @QPU_PACK_A_NOP
	.comm	_QPU_PM,4,2                     ## @QPU_PM
L_.str.3:                               ## @.str.3
	.asciz	"No packing allowed on uniforms reset\n"

L_.str.4:                               ## @.str.4
	.asciz	"First argument of uniform address write must be an immediate value.\n"

L_.str.5:                               ## @.str.5
	.asciz	"Resetting uniforms with offset %db instead of %db\n"

	.comm	_QPU_MUX_A,4,2                  ## @QPU_MUX_A
	.comm	_QPU_R_UNIF,4,2                 ## @QPU_R_UNIF
	.comm	_QPU_MUX_B,4,2                  ## @QPU_MUX_B
L_.str.6:                               ## @.str.6
	.asciz	"Second argument of uniform address write must be a uniform.\n"

	.no_dead_strip	_validate_uniform_address_write
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function validate_uniform_address_write
_validate_uniform_address_write:        ; @validate_uniform_address_write
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x26, x2
	mov	x20, x1
	mov	x19, x0
	ldp	x8, x9, [x1]
	ldr	w24, [x8, x9, lsl #2]
Lloh0:
	adrp	x8, _QPU_ADD_B@GOTPAGE
Lloh1:
	ldr	x8, [x8, _QPU_ADD_B@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x24
	bl	_QPU_GET_FIELD
	mov	x21, x0
Lloh3:
	adrp	x8, _QPU_RADDR_A@GOTPAGE
Lloh4:
	ldr	x8, [x8, _QPU_RADDR_A@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x24
	bl	_QPU_GET_FIELD
	mov	x23, x0
Lloh6:
	adrp	x8, _QPU_RADDR_B@GOTPAGE
Lloh7:
	ldr	x8, [x8, _QPU_RADDR_B@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	x0, x24
	bl	_QPU_GET_FIELD
	mov	x22, x0
	mov	x0, x24
	bl	_raddr_add_a_to_live_reg_index
	mov	x25, x0
	ldr	w27, [x19]
Lloh9:
	adrp	x8, _QPU_SIG@GOTPAGE
Lloh10:
	ldr	x8, [x8, _QPU_SIG@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x0, x24
	bl	_QPU_GET_FIELD
	sub	w8, w0, #128
	cmp	w8, #5
	b.hs	LBB0_13
; %bb.1:
	cbnz	w26, LBB0_14
; %bb.2:
Lloh12:
	adrp	x8, _QPU_OP_ADD@GOTPAGE
Lloh13:
	ldr	x8, [x8, _QPU_OP_ADD@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mov	x0, x24
	bl	_QPU_GET_FIELD
Lloh15:
	adrp	x8, _QPU_A_ADD@GOTPAGE
Lloh16:
	ldr	x8, [x8, _QPU_A_ADD@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	cmp	w0, w8
	b.ne	LBB0_14
; %bb.3:
Lloh18:
	adrp	x8, _QPU_COND_ADD@GOTPAGE
Lloh19:
	ldr	x8, [x8, _QPU_COND_ADD@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	mov	x0, x24
	bl	_QPU_GET_FIELD
Lloh21:
	adrp	x8, _QPU_COND_ALWAYS@GOTPAGE
Lloh22:
	ldr	x8, [x8, _QPU_COND_ALWAYS@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	cmp	w0, w8
	b.ne	LBB0_16
; %bb.4:
Lloh24:
	adrp	x8, _QPU_PACK@GOTPAGE
Lloh25:
	ldr	x8, [x8, _QPU_PACK@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	x0, x24
	bl	_QPU_GET_FIELD
Lloh27:
	adrp	x8, _QPU_PACK_A_NOP@GOTPAGE
Lloh28:
	ldr	x8, [x8, _QPU_PACK_A_NOP@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	cmp	w0, w8
	b.eq	LBB0_6
; %bb.5:
Lloh30:
	adrp	x8, _QPU_PM@GOTPAGE
Lloh31:
	ldr	x8, [x8, _QPU_PM@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
	tst	w8, w24
	b.eq	LBB0_19
LBB0_6:
	cmn	w25, #1
	b.eq	LBB0_17
; %bb.7:
	add	w8, w27, #4
	ldr	x9, [x20, #16]
	ldr	w9, [x9, w25, sxtw #2]
	cmp	w9, w8
	b.ne	LBB0_18
; %bb.8:
Lloh33:
	adrp	x8, _QPU_MUX_A@GOTPAGE
Lloh34:
	ldr	x8, [x8, _QPU_MUX_A@GOTPAGEOFF]
Lloh35:
	ldr	w9, [x8]
Lloh36:
	adrp	x8, _QPU_R_UNIF@GOTPAGE
Lloh37:
	ldr	x8, [x8, _QPU_R_UNIF@GOTPAGEOFF]
Lloh38:
	ldr	w8, [x8]
	cmp	w21, w9
	b.ne	LBB0_10
; %bb.9:
	cmp	w23, w8
	b.eq	LBB0_12
LBB0_10:
Lloh39:
	adrp	x9, _QPU_MUX_B@GOTPAGE
Lloh40:
	ldr	x9, [x9, _QPU_MUX_B@GOTPAGEOFF]
Lloh41:
	ldr	w9, [x9]
	cmp	w21, w9
	b.ne	LBB0_20
; %bb.11:
	cmp	w22, w8
	b.ne	LBB0_20
LBB0_12:
	str	xzr, [x20, #24]
	mov	x0, x19
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	b	_require_uniform_address_uniform
LBB0_13:
Lloh42:
	adrp	x0, l_.str@PAGE
Lloh43:
	add	x0, x0, l_.str@PAGEOFF
	b	LBB0_15
LBB0_14:
Lloh44:
	adrp	x0, l_.str.1@PAGE
Lloh45:
	add	x0, x0, l_.str.1@PAGEOFF
LBB0_15:
	bl	_DRM_DEBUG
	mov	w0, #0
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
LBB0_16:
Lloh46:
	adrp	x0, l_.str.2@PAGE
Lloh47:
	add	x0, x0, l_.str.2@PAGEOFF
	b	LBB0_15
LBB0_17:
Lloh48:
	adrp	x0, l_.str.4@PAGE
Lloh49:
	add	x0, x0, l_.str.4@PAGEOFF
	b	LBB0_15
LBB0_18:
	stp	x9, x8, [sp]
Lloh50:
	adrp	x0, l_.str.5@PAGE
Lloh51:
	add	x0, x0, l_.str.5@PAGEOFF
	b	LBB0_15
LBB0_19:
Lloh52:
	adrp	x0, l_.str.3@PAGE
Lloh53:
	add	x0, x0, l_.str.3@PAGEOFF
	b	LBB0_15
LBB0_20:
Lloh54:
	adrp	x0, l_.str.6@PAGE
Lloh55:
	add	x0, x0, l_.str.6@PAGEOFF
	b	LBB0_15
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpAdd	Lloh42, Lloh43
	.loh AdrpAdd	Lloh44, Lloh45
	.loh AdrpAdd	Lloh46, Lloh47
	.loh AdrpAdd	Lloh48, Lloh49
	.loh AdrpAdd	Lloh50, Lloh51
	.loh AdrpAdd	Lloh52, Lloh53
	.loh AdrpAdd	Lloh54, Lloh55
	.cfi_endproc
                                        ; -- End function
	.comm	_QPU_ADD_B,4,2                  ; @QPU_ADD_B
	.comm	_QPU_RADDR_A,4,2                ; @QPU_RADDR_A
	.comm	_QPU_RADDR_B,4,2                ; @QPU_RADDR_B
	.comm	_QPU_SIG,4,2                    ; @QPU_SIG
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"uniforms address change must be normal math\n"

	.comm	_QPU_OP_ADD,4,2                 ; @QPU_OP_ADD
	.comm	_QPU_A_ADD,4,2                  ; @QPU_A_ADD
l_.str.1:                               ; @.str.1
	.asciz	"Uniform address reset must be an ADD.\n"

	.comm	_QPU_COND_ADD,4,2               ; @QPU_COND_ADD
	.comm	_QPU_COND_ALWAYS,4,2            ; @QPU_COND_ALWAYS
l_.str.2:                               ; @.str.2
	.asciz	"Uniform address reset must be unconditional.\n"

	.comm	_QPU_PACK,4,2                   ; @QPU_PACK
	.comm	_QPU_PACK_A_NOP,4,2             ; @QPU_PACK_A_NOP
	.comm	_QPU_PM,4,2                     ; @QPU_PM
l_.str.3:                               ; @.str.3
	.asciz	"No packing allowed on uniforms reset\n"

l_.str.4:                               ; @.str.4
	.asciz	"First argument of uniform address write must be an immediate value.\n"

l_.str.5:                               ; @.str.5
	.asciz	"Resetting uniforms with offset %db instead of %db\n"

	.comm	_QPU_MUX_A,4,2                  ; @QPU_MUX_A
	.comm	_QPU_R_UNIF,4,2                 ; @QPU_R_UNIF
	.comm	_QPU_MUX_B,4,2                  ; @QPU_MUX_B
l_.str.6:                               ; @.str.6
	.asciz	"Second argument of uniform address write must be a uniform.\n"

	.no_dead_strip	_validate_uniform_address_write
.subsections_via_symbols
