	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v10_0_compute_ring_init
_gfx_v10_0_compute_ring_init:           ## @gfx_v10_0_compute_ring_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	24(%rdi), %r12
	movslq	%esi, %rax
	leaq	(%rax,%rax,4), %rbx
	leaq	(%r12,%rbx,8), %r14
	incl	%edx
	movl	%edx, (%r12,%rbx,8)
	movl	%ecx, 4(%r12,%rbx,8)
	movl	%r8d, 8(%r12,%rbx,8)
	movq	$0, 32(%r12,%rbx,8)
	movl	$1, 12(%r12,%rbx,8)
	movl	32(%rdi), %esi
	addl	%eax, %esi
	addl	%esi, %esi
	movl	%esi, 16(%r12,%rbx,8)
	movq	_GFX10_MEC_HPD_SIZE@GOTPCREL(%rip), %rsi
	movslq	(%rsi), %rsi
	imulq	%rax, %rsi
	addq	16(%rdi), %rsi
	movq	%rsi, 24(%r12,%rbx,8)
	movl	20(%r12,%rbx,8), %edi
	leaq	L_.str(%rip), %rsi
	callq	_sprintf
	movq	_AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP@GOTPCREL(%rip), %rax
	movl	(%r12,%rbx,8), %r8d
	decl	%r8d
	imull	8(%r15), %r8d
	addl	(%rax), %r8d
	addl	4(%r12,%rbx,8), %r8d
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	$1024, %edx                     ## imm = 0x400
	movq	%r15, %rcx
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_init               ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_GFX10_MEC_HPD_SIZE,4,2         ## @GFX10_MEC_HPD_SIZE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"comp_%d.%d.%d"

	.comm	_AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,4,2 ## @AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
	.no_dead_strip	_gfx_v10_0_compute_ring_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v10_0_compute_ring_init
_gfx_v10_0_compute_ring_init:           ; @gfx_v10_0_compute_ring_init
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
                                        ; kill: def $w1 killed $w1 def $x1
	mov	x19, x0
	mov	w8, #40
	ldp	x10, x9, [x0, #16]
	smaddl	x20, w1, w8, x9
	mov	w8, #1
	stp	w4, w8, [x20, #8]
	ldr	w8, [x0, #32]
	add	w8, w8, w1
	sxtw	x9, w1
	add	w2, w2, #1
	lsl	w8, w8, #1
	str	w8, [x20, #16]
Lloh0:
	adrp	x8, _GFX10_MEC_HPD_SIZE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _GFX10_MEC_HPD_SIZE@GOTPAGEOFF]
	stp	w2, w3, [x20]
Lloh2:
	ldrsw	x8, [x8]
	madd	x8, x8, x9, x10
	stp	x8, xzr, [x20, #24]
	ldr	w0, [x20, #20]
Lloh3:
	adrp	x1, l_.str@PAGE
Lloh4:
	add	x1, x1, l_.str@PAGEOFF
	bl	_sprintf
Lloh5:
	adrp	x8, _AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP@GOTPAGE
Lloh6:
	ldr	x8, [x8, _AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	ldp	w9, w10, [x20]
	sub	w9, w9, #1
	ldr	w11, [x19, #8]
	madd	w8, w9, w11, w8
	add	w4, w8, w10
	mov	x0, x19
	mov	x1, x20
	mov	w2, #1024
	mov	x3, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_amdgpu_ring_init
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_GFX10_MEC_HPD_SIZE,4,2         ; @GFX10_MEC_HPD_SIZE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"comp_%d.%d.%d"

	.comm	_AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,4,2 ; @AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
	.no_dead_strip	_gfx_v10_0_compute_ring_init
.subsections_via_symbols
