	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vce_v3_0_get_harvest_config
_vce_v3_0_get_harvest_config:           ## @vce_v3_0_get_harvest_config
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	(%rdi), %rax
	movq	_CHIP_FIJI@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_6
## %bb.1:
	movq	_CHIP_STONEY@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_6
## %bb.2:
	movq	%rdi, %r14
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	8(%rdi), %eax
	movq	_ixVCE_HARVEST_FUSE_MACRO__ADDRESS@GOTPCREL(%rip), %rax
	cmoveq	_ixCC_HARVEST_FUSES@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_VCE_HARVEST_FUSE_MACRO__MASK@GOTPCREL(%rip), %r15
	cmoveq	_CC_HARVEST_FUSES__VCE_DISABLE_MASK@GOTPCREL(%rip), %r15
	movq	_VCE_HARVEST_FUSE_MACRO__SHIFT@GOTPCREL(%rip), %rbx
	cmoveq	_CC_HARVEST_FUSES__VCE_DISABLE__SHIFT@GOTPCREL(%rip), %rbx
	callq	_RREG32_SMC
	andl	(%r15), %eax
	movb	(%rbx), %cl
	sarl	%cl, %eax
	cmpl	$3, %eax
	je	LBB0_9
## %bb.3:
	cmpl	$2, %eax
	je	LBB0_6
## %bb.4:
	cmpl	$1, %eax
	jne	LBB0_10
## %bb.5:
	movq	_AMDGPU_VCE_HARVEST_VCE0@GOTPCREL(%rip), %rax
	jmp	LBB0_7
LBB0_6:
	movq	_AMDGPU_VCE_HARVEST_VCE1@GOTPCREL(%rip), %rax
LBB0_7:
	movl	(%rax), %eax
LBB0_8:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_9:
	movq	_AMDGPU_VCE_HARVEST_VCE0@GOTPCREL(%rip), %rcx
	movq	_AMDGPU_VCE_HARVEST_VCE1@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	(%rcx), %eax
	jmp	LBB0_8
LBB0_10:
	movq	(%r14), %rcx
	movq	_CHIP_POLARIS10@GOTPCREL(%rip), %rdx
	movq	_CHIP_POLARIS11@GOTPCREL(%rip), %rsi
	movq	_CHIP_POLARIS12@GOTPCREL(%rip), %rdi
	movq	_CHIP_VEGAM@GOTPCREL(%rip), %rbx
	xorl	%eax, %eax
	cmpq	(%rbx), %rcx
	movq	_AMDGPU_VCE_HARVEST_VCE1@GOTPCREL(%rip), %rbx
	movl	(%rbx), %ebx
	cmovel	%ebx, %eax
	cmpq	(%rdi), %rcx
	cmovel	%ebx, %eax
	cmpq	(%rsi), %rcx
	cmovel	%ebx, %eax
	cmpq	(%rdx), %rcx
	cmovel	%ebx, %eax
	jmp	LBB0_8
	.cfi_endproc
                                        ## -- End function
	.comm	_CHIP_FIJI,8,3                  ## @CHIP_FIJI
	.comm	_CHIP_STONEY,8,3                ## @CHIP_STONEY
	.comm	_AMDGPU_VCE_HARVEST_VCE1,4,2    ## @AMDGPU_VCE_HARVEST_VCE1
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_ixVCE_HARVEST_FUSE_MACRO__ADDRESS,4,2 ## @ixVCE_HARVEST_FUSE_MACRO__ADDRESS
	.comm	_VCE_HARVEST_FUSE_MACRO__MASK,4,2 ## @VCE_HARVEST_FUSE_MACRO__MASK
	.comm	_VCE_HARVEST_FUSE_MACRO__SHIFT,4,2 ## @VCE_HARVEST_FUSE_MACRO__SHIFT
	.comm	_ixCC_HARVEST_FUSES,4,2         ## @ixCC_HARVEST_FUSES
	.comm	_CC_HARVEST_FUSES__VCE_DISABLE_MASK,4,2 ## @CC_HARVEST_FUSES__VCE_DISABLE_MASK
	.comm	_CC_HARVEST_FUSES__VCE_DISABLE__SHIFT,4,2 ## @CC_HARVEST_FUSES__VCE_DISABLE__SHIFT
	.comm	_AMDGPU_VCE_HARVEST_VCE0,4,2    ## @AMDGPU_VCE_HARVEST_VCE0
	.comm	_CHIP_POLARIS10,8,3             ## @CHIP_POLARIS10
	.comm	_CHIP_POLARIS11,8,3             ## @CHIP_POLARIS11
	.comm	_CHIP_POLARIS12,8,3             ## @CHIP_POLARIS12
	.comm	_CHIP_VEGAM,8,3                 ## @CHIP_VEGAM
	.no_dead_strip	_vce_v3_0_get_harvest_config
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vce_v3_0_get_harvest_config
_vce_v3_0_get_harvest_config:           ; @vce_v3_0_get_harvest_config
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	ldr	x8, [x0]
Lloh0:
	adrp	x9, _CHIP_FIJI@GOTPAGE
Lloh1:
	ldr	x9, [x9, _CHIP_FIJI@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
Lloh3:
	adrp	x10, _CHIP_STONEY@GOTPAGE
Lloh4:
	ldr	x10, [x10, _CHIP_STONEY@GOTPAGEOFF]
Lloh5:
	ldr	x10, [x10]
	cmp	x8, x9
	ccmp	x8, x10, #4, ne
	b.eq	LBB0_5
; %bb.1:
	mov	x19, x0
	ldr	w8, [x0, #8]
Lloh6:
	adrp	x9, _AMD_IS_APU@GOTPAGE
Lloh7:
	ldr	x9, [x9, _AMD_IS_APU@GOTPAGEOFF]
Lloh8:
	adrp	x10, _ixCC_HARVEST_FUSES@GOTPAGE
Lloh9:
	ldr	x10, [x10, _ixCC_HARVEST_FUSES@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
Lloh11:
	adrp	x11, _ixVCE_HARVEST_FUSE_MACRO__ADDRESS@GOTPAGE
Lloh12:
	ldr	x11, [x11, _ixVCE_HARVEST_FUSE_MACRO__ADDRESS@GOTPAGEOFF]
	tst	w9, w8
	csel	x8, x10, x11, eq
	ldr	w0, [x8]
Lloh13:
	adrp	x8, _CC_HARVEST_FUSES__VCE_DISABLE_MASK@GOTPAGE
Lloh14:
	ldr	x8, [x8, _CC_HARVEST_FUSES__VCE_DISABLE_MASK@GOTPAGEOFF]
Lloh15:
	adrp	x9, _VCE_HARVEST_FUSE_MACRO__MASK@GOTPAGE
Lloh16:
	ldr	x9, [x9, _VCE_HARVEST_FUSE_MACRO__MASK@GOTPAGEOFF]
	csel	x20, x8, x9, eq
Lloh17:
	adrp	x8, _CC_HARVEST_FUSES__VCE_DISABLE__SHIFT@GOTPAGE
Lloh18:
	ldr	x8, [x8, _CC_HARVEST_FUSES__VCE_DISABLE__SHIFT@GOTPAGEOFF]
Lloh19:
	adrp	x9, _VCE_HARVEST_FUSE_MACRO__SHIFT@GOTPAGE
Lloh20:
	ldr	x9, [x9, _VCE_HARVEST_FUSE_MACRO__SHIFT@GOTPAGEOFF]
	csel	x21, x8, x9, eq
	bl	_RREG32_SMC
	ldr	w8, [x20]
	and	w8, w8, w0
	ldr	w9, [x21]
	asr	w8, w8, w9
	cmp	w8, #3
	b.eq	LBB0_8
; %bb.2:
	cmp	w8, #2
	b.eq	LBB0_5
; %bb.3:
	cmp	w8, #1
	b.ne	LBB0_9
; %bb.4:
Lloh21:
	adrp	x8, _AMDGPU_VCE_HARVEST_VCE0@GOTPAGE
Lloh22:
	ldr	x8, [x8, _AMDGPU_VCE_HARVEST_VCE0@GOTPAGEOFF]
	b	LBB0_6
LBB0_5:
Lloh23:
	adrp	x8, _AMDGPU_VCE_HARVEST_VCE1@GOTPAGE
Lloh24:
	ldr	x8, [x8, _AMDGPU_VCE_HARVEST_VCE1@GOTPAGEOFF]
LBB0_6:
	ldr	w0, [x8]
LBB0_7:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_8:
Lloh25:
	adrp	x8, _AMDGPU_VCE_HARVEST_VCE0@GOTPAGE
Lloh26:
	ldr	x8, [x8, _AMDGPU_VCE_HARVEST_VCE0@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
Lloh28:
	adrp	x9, _AMDGPU_VCE_HARVEST_VCE1@GOTPAGE
Lloh29:
	ldr	x9, [x9, _AMDGPU_VCE_HARVEST_VCE1@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
	orr	w0, w9, w8
	b	LBB0_7
LBB0_9:
	ldr	x8, [x19]
Lloh31:
	adrp	x9, _CHIP_POLARIS10@GOTPAGE
Lloh32:
	ldr	x9, [x9, _CHIP_POLARIS10@GOTPAGEOFF]
Lloh33:
	ldr	x9, [x9]
Lloh34:
	adrp	x10, _CHIP_POLARIS11@GOTPAGE
Lloh35:
	ldr	x10, [x10, _CHIP_POLARIS11@GOTPAGEOFF]
Lloh36:
	ldr	x10, [x10]
Lloh37:
	adrp	x11, _CHIP_POLARIS12@GOTPAGE
Lloh38:
	ldr	x11, [x11, _CHIP_POLARIS12@GOTPAGEOFF]
Lloh39:
	ldr	x11, [x11]
Lloh40:
	adrp	x12, _CHIP_VEGAM@GOTPAGE
Lloh41:
	ldr	x12, [x12, _CHIP_VEGAM@GOTPAGEOFF]
Lloh42:
	ldr	x12, [x12]
	cmp	x8, x12
	ccmp	x8, x11, #4, ne
	ccmp	x8, x10, #4, ne
	ccmp	x8, x9, #4, ne
Lloh43:
	adrp	x8, _AMDGPU_VCE_HARVEST_VCE1@GOTPAGE
Lloh44:
	ldr	x8, [x8, _AMDGPU_VCE_HARVEST_VCE1@GOTPAGEOFF]
Lloh45:
	ldr	w8, [x8]
	csel	w0, w8, wzr, eq
	b	LBB0_7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh10
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.cfi_endproc
                                        ; -- End function
	.comm	_CHIP_FIJI,8,3                  ; @CHIP_FIJI
	.comm	_CHIP_STONEY,8,3                ; @CHIP_STONEY
	.comm	_AMDGPU_VCE_HARVEST_VCE1,4,2    ; @AMDGPU_VCE_HARVEST_VCE1
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_ixVCE_HARVEST_FUSE_MACRO__ADDRESS,4,2 ; @ixVCE_HARVEST_FUSE_MACRO__ADDRESS
	.comm	_VCE_HARVEST_FUSE_MACRO__MASK,4,2 ; @VCE_HARVEST_FUSE_MACRO__MASK
	.comm	_VCE_HARVEST_FUSE_MACRO__SHIFT,4,2 ; @VCE_HARVEST_FUSE_MACRO__SHIFT
	.comm	_ixCC_HARVEST_FUSES,4,2         ; @ixCC_HARVEST_FUSES
	.comm	_CC_HARVEST_FUSES__VCE_DISABLE_MASK,4,2 ; @CC_HARVEST_FUSES__VCE_DISABLE_MASK
	.comm	_CC_HARVEST_FUSES__VCE_DISABLE__SHIFT,4,2 ; @CC_HARVEST_FUSES__VCE_DISABLE__SHIFT
	.comm	_AMDGPU_VCE_HARVEST_VCE0,4,2    ; @AMDGPU_VCE_HARVEST_VCE0
	.comm	_CHIP_POLARIS10,8,3             ; @CHIP_POLARIS10
	.comm	_CHIP_POLARIS11,8,3             ; @CHIP_POLARIS11
	.comm	_CHIP_POLARIS12,8,3             ; @CHIP_POLARIS12
	.comm	_CHIP_VEGAM,8,3                 ; @CHIP_VEGAM
	.no_dead_strip	_vce_v3_0_get_harvest_config
.subsections_via_symbols
