	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function uvd_v6_0_ring_emit_pipeline_sync
_uvd_v6_0_ring_emit_pipeline_sync:      ## @uvd_v6_0_ring_emit_pipeline_sync
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movl	(%rdi), %r14d
	movl	4(%rdi), %r15d
	movq	_mmUVD_GPCOM_VCPU_DATA0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	%r15d, %edi
	callq	_lower_32_bits
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_mmUVD_GPCOM_VCPU_DATA1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	%r15d, %edi
	callq	_upper_32_bits
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_mmUVD_GP_SCRATCH8@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$-1, %esi
	callq	_amdgpu_ring_write
	movq	_mmUVD_GP_SCRATCH9@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_amdgpu_ring_write
	movq	_mmUVD_GPCOM_VCPU_CMD@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_PACKET0
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$14, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_write              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_mmUVD_GPCOM_VCPU_DATA0,4,2     ## @mmUVD_GPCOM_VCPU_DATA0
	.comm	_mmUVD_GPCOM_VCPU_DATA1,4,2     ## @mmUVD_GPCOM_VCPU_DATA1
	.comm	_mmUVD_GP_SCRATCH8,4,2          ## @mmUVD_GP_SCRATCH8
	.comm	_mmUVD_GP_SCRATCH9,4,2          ## @mmUVD_GP_SCRATCH9
	.comm	_mmUVD_GPCOM_VCPU_CMD,4,2       ## @mmUVD_GPCOM_VCPU_CMD
	.no_dead_strip	_uvd_v6_0_ring_emit_pipeline_sync
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function uvd_v6_0_ring_emit_pipeline_sync
_uvd_v6_0_ring_emit_pipeline_sync:      ; @uvd_v6_0_ring_emit_pipeline_sync
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldp	w20, w21, [x0]
Lloh0:
	adrp	x8, _mmUVD_GPCOM_VCPU_DATA0@GOTPAGE
Lloh1:
	ldr	x8, [x8, _mmUVD_GPCOM_VCPU_DATA0@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x21
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh3:
	adrp	x8, _mmUVD_GPCOM_VCPU_DATA1@GOTPAGE
Lloh4:
	ldr	x8, [x8, _mmUVD_GPCOM_VCPU_DATA1@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x21
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh6:
	adrp	x8, _mmUVD_GP_SCRATCH8@GOTPAGE
Lloh7:
	ldr	x8, [x8, _mmUVD_GP_SCRATCH8@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #-1
	bl	_amdgpu_ring_write
Lloh9:
	adrp	x8, _mmUVD_GP_SCRATCH9@GOTPAGE
Lloh10:
	ldr	x8, [x8, _mmUVD_GP_SCRATCH9@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_ring_write
Lloh12:
	adrp	x8, _mmUVD_GPCOM_VCPU_CMD@GOTPAGE
Lloh13:
	ldr	x8, [x8, _mmUVD_GPCOM_VCPU_CMD@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_PACKET0
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #14
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_amdgpu_ring_write
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_mmUVD_GPCOM_VCPU_DATA0,4,2     ; @mmUVD_GPCOM_VCPU_DATA0
	.comm	_mmUVD_GPCOM_VCPU_DATA1,4,2     ; @mmUVD_GPCOM_VCPU_DATA1
	.comm	_mmUVD_GP_SCRATCH8,4,2          ; @mmUVD_GP_SCRATCH8
	.comm	_mmUVD_GP_SCRATCH9,4,2          ; @mmUVD_GP_SCRATCH9
	.comm	_mmUVD_GPCOM_VCPU_CMD,4,2       ; @mmUVD_GPCOM_VCPU_CMD
	.no_dead_strip	_uvd_v6_0_ring_emit_pipeline_sync
.subsections_via_symbols
