	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function intel_dp_get_config
_intel_dp_get_config:                   ## @intel_dp_get_config
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r15
	movq	%rdi, %rbx
	leaq	16(%rdi), %r12
	movl	16(%rdi), %edi
	callq	_to_i915
	movq	%rax, %r14
	movq	%r12, %rdi
	callq	_enc_to_intel_dp
	movq	%rax, %r13
	movl	(%rbx), %r12d
	movl	36(%r15), %edi
	callq	_to_intel_crtc
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
	movq	8(%rbx), %rdi
	movq	_INTEL_OUTPUT_EDP@GOTPCREL(%rip), %rax
	cmpq	(%rax), %rdi
	je	LBB0_2
## %bb.1:
	movq	_INTEL_OUTPUT_DP@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
LBB0_2:
	callq	_BIT
	orl	%eax, 40(%r15)
	movq	%r13, -48(%rbp)                 ## 8-byte Spill
	movl	(%r13), %edi
	callq	_I915_READ
	movl	%eax, %r13d
	movq	_DP_AUDIO_OUTPUT_ENABLE@GOTPCREL(%rip), %rax
	movl	%r13d, %ecx
	andl	(%rax), %ecx
	setne	%al
	movq	_PORT_A@GOTPCREL(%rip), %rbx
	cmpl	(%rbx), %r12d
	setne	%cl
	andb	%al, %cl
	movzbl	%cl, %eax
	movl	%eax, (%r15)
	movq	%r14, %rdi
	callq	_HAS_PCH_CPT
	testq	%rax, %rax
	je	LBB0_11
## %bb.3:
	cmpl	(%rbx), %r12d
	je	LBB0_11
## %bb.4:
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %edi
	callq	_TRANS_DP_CTL
	movl	%eax, %edi
	callq	_I915_READ
	movq	_TRANS_DP_HSYNC_ACTIVE_HIGH@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	jne	LBB0_5
## %bb.6:
	movq	_DRM_MODE_FLAG_NHSYNC@GOTPCREL(%rip), %rcx
	jmp	LBB0_7
LBB0_11:
	movq	_DP_SYNC_HS_HIGH@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	jne	LBB0_12
## %bb.13:
	movq	_DRM_MODE_FLAG_NHSYNC@GOTPCREL(%rip), %rax
	jmp	LBB0_14
LBB0_5:
	movq	_DRM_MODE_FLAG_PHSYNC@GOTPCREL(%rip), %rcx
LBB0_7:
	movq	_TRANS_DP_VSYNC_ACTIVE_HIGH@GOTPCREL(%rip), %rdx
	testl	%eax, (%rdx)
	jne	LBB0_8
## %bb.9:
	movq	_DRM_MODE_FLAG_NVSYNC@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	jmp	LBB0_17
LBB0_12:
	movq	_DRM_MODE_FLAG_PHSYNC@GOTPCREL(%rip), %rax
LBB0_14:
	movl	(%rax), %eax
	movq	_DP_SYNC_VS_HIGH@GOTPCREL(%rip), %rcx
	testl	%r13d, (%rcx)
	je	LBB0_16
## %bb.15:
	movq	_DRM_MODE_FLAG_PVSYNC@GOTPCREL(%rip), %rcx
	jmp	LBB0_17
LBB0_8:
	movq	_DRM_MODE_FLAG_PVSYNC@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	jmp	LBB0_17
LBB0_16:
	movq	_DRM_MODE_FLAG_NVSYNC@GOTPCREL(%rip), %rcx
LBB0_17:
	orl	(%rcx), %eax
	orl	%eax, 28(%r15)
	movq	%r14, %rdi
	callq	_IS_G4X
	testq	%rax, %rax
	je	LBB0_20
## %bb.18:
	movq	_DP_COLOR_RANGE_16_235@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_20
## %bb.19:
	movl	$1, 4(%r15)
LBB0_20:
	movq	_DP_PORT_WIDTH_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r13d, %eax
	movq	_DP_PORT_WIDTH_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	incl	%eax
	movl	%eax, 8(%r15)
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	movq	%r15, %rsi
	callq	_intel_dp_get_m_n
	cmpl	(%rbx), %r12d
	jne	LBB0_21
## %bb.22:
	movq	_DP_A@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	_DP_PLL_FREQ_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_DP_PLL_FREQ_162MHZ@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	jne	LBB0_24
## %bb.23:
	movl	$162000, 12(%r15)               ## imm = 0x278D0
	movl	$162000, %edi                   ## imm = 0x278D0
	jmp	LBB0_25
LBB0_21:
	movl	12(%r15), %edi
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	jmp	LBB0_25
LBB0_24:
	movl	$270000, 12(%r15)               ## imm = 0x41EB0
	movl	$270000, %edi                   ## imm = 0x41EB0
LBB0_25:
	leaq	24(%r15), %rsi
	callq	_intel_dotclock_calculate
	movl	%eax, 32(%r15)
	movq	%rbx, %rdi
	callq	_intel_dp_is_edp
	testq	%rax, %rax
	je	LBB0_29
## %bb.26:
	movq	(%r14), %rdx
	testq	%rdx, %rdx
	je	LBB0_29
## %bb.27:
	movq	16(%r15), %rsi
	cmpq	%rdx, %rsi
	jle	LBB0_29
## %bb.28:
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	movq	16(%r15), %rax
	movq	%rax, (%r14)
LBB0_29:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_INTEL_OUTPUT_EDP,8,3           ## @INTEL_OUTPUT_EDP
	.comm	_INTEL_OUTPUT_DP,8,3            ## @INTEL_OUTPUT_DP
	.comm	_DP_AUDIO_OUTPUT_ENABLE,4,2     ## @DP_AUDIO_OUTPUT_ENABLE
	.comm	_PORT_A,4,2                     ## @PORT_A
	.comm	_TRANS_DP_HSYNC_ACTIVE_HIGH,4,2 ## @TRANS_DP_HSYNC_ACTIVE_HIGH
	.comm	_DRM_MODE_FLAG_PHSYNC,4,2       ## @DRM_MODE_FLAG_PHSYNC
	.comm	_DRM_MODE_FLAG_NHSYNC,4,2       ## @DRM_MODE_FLAG_NHSYNC
	.comm	_TRANS_DP_VSYNC_ACTIVE_HIGH,4,2 ## @TRANS_DP_VSYNC_ACTIVE_HIGH
	.comm	_DRM_MODE_FLAG_PVSYNC,4,2       ## @DRM_MODE_FLAG_PVSYNC
	.comm	_DRM_MODE_FLAG_NVSYNC,4,2       ## @DRM_MODE_FLAG_NVSYNC
	.comm	_DP_SYNC_HS_HIGH,4,2            ## @DP_SYNC_HS_HIGH
	.comm	_DP_SYNC_VS_HIGH,4,2            ## @DP_SYNC_VS_HIGH
	.comm	_DP_COLOR_RANGE_16_235,4,2      ## @DP_COLOR_RANGE_16_235
	.comm	_DP_PORT_WIDTH_MASK,4,2         ## @DP_PORT_WIDTH_MASK
	.comm	_DP_PORT_WIDTH_SHIFT,4,2        ## @DP_PORT_WIDTH_SHIFT
	.comm	_DP_A,4,2                       ## @DP_A
	.comm	_DP_PLL_FREQ_MASK,4,2           ## @DP_PLL_FREQ_MASK
	.comm	_DP_PLL_FREQ_162MHZ,4,2         ## @DP_PLL_FREQ_162MHZ
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n"

	.no_dead_strip	_intel_dp_get_config
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function intel_dp_get_config
_intel_dp_get_config:                   ; @intel_dp_get_config
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x1
	mov	x23, x0
	mov	x21, x0
	ldr	w0, [x21, #16]!
	bl	_to_i915
	mov	x20, x0
	mov	x0, x21
	bl	_enc_to_intel_dp
	mov	x21, x0
	ldr	w24, [x23]
	ldr	w0, [x19, #36]
	bl	_to_intel_crtc
	mov	x22, x0
	ldr	x8, [x23, #8]
Lloh0:
	adrp	x9, _INTEL_OUTPUT_EDP@GOTPAGE
Lloh1:
	ldr	x9, [x9, _INTEL_OUTPUT_EDP@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
Lloh3:
	adrp	x10, _INTEL_OUTPUT_DP@GOTPAGE
Lloh4:
	ldr	x10, [x10, _INTEL_OUTPUT_DP@GOTPAGEOFF]
Lloh5:
	ldr	x10, [x10]
	cmp	x8, x9
	csel	x0, x8, x10, eq
	bl	_BIT
	ldr	w8, [x19, #40]
	orr	w8, w8, w0
	str	w8, [x19, #40]
	ldr	w0, [x21]
	bl	_I915_READ
	mov	x23, x0
Lloh6:
	adrp	x8, _DP_AUDIO_OUTPUT_ENABLE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _DP_AUDIO_OUTPUT_ENABLE@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	tst	w8, w0
Lloh9:
	adrp	x25, _PORT_A@GOTPAGE
Lloh10:
	ldr	x25, [x25, _PORT_A@GOTPAGEOFF]
	ldr	w8, [x25]
	ccmp	w24, w8, #4, ne
	cset	w8, ne
	str	w8, [x19]
	mov	x0, x20
	bl	_HAS_PCH_CPT
	cbz	x0, LBB0_3
; %bb.1:
	ldr	w8, [x25]
	cmp	w24, w8
	b.eq	LBB0_3
; %bb.2:
	ldr	w0, [x22]
	bl	_TRANS_DP_CTL
	bl	_I915_READ
Lloh11:
	adrp	x8, _TRANS_DP_HSYNC_ACTIVE_HIGH@GOTPAGE
Lloh12:
	ldr	x8, [x8, _TRANS_DP_HSYNC_ACTIVE_HIGH@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
Lloh14:
	adrp	x9, _DRM_MODE_FLAG_NHSYNC@GOTPAGE
Lloh15:
	ldr	x9, [x9, _DRM_MODE_FLAG_NHSYNC@GOTPAGEOFF]
Lloh16:
	adrp	x10, _DRM_MODE_FLAG_PHSYNC@GOTPAGE
Lloh17:
	ldr	x10, [x10, _DRM_MODE_FLAG_PHSYNC@GOTPAGEOFF]
	tst	w8, w0
	csel	x8, x9, x10, eq
	ldr	w8, [x8]
Lloh18:
	adrp	x9, _TRANS_DP_VSYNC_ACTIVE_HIGH@GOTPAGE
Lloh19:
	ldr	x9, [x9, _TRANS_DP_VSYNC_ACTIVE_HIGH@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
Lloh21:
	adrp	x10, _DRM_MODE_FLAG_NVSYNC@GOTPAGE
Lloh22:
	ldr	x10, [x10, _DRM_MODE_FLAG_NVSYNC@GOTPAGEOFF]
Lloh23:
	adrp	x11, _DRM_MODE_FLAG_PVSYNC@GOTPAGE
Lloh24:
	ldr	x11, [x11, _DRM_MODE_FLAG_PVSYNC@GOTPAGEOFF]
	tst	w9, w0
	csel	x9, x10, x11, eq
	b	LBB0_6
LBB0_3:
Lloh25:
	adrp	x8, _DP_SYNC_HS_HIGH@GOTPAGE
Lloh26:
	ldr	x8, [x8, _DP_SYNC_HS_HIGH@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
Lloh28:
	adrp	x9, _DRM_MODE_FLAG_NHSYNC@GOTPAGE
Lloh29:
	ldr	x9, [x9, _DRM_MODE_FLAG_NHSYNC@GOTPAGEOFF]
Lloh30:
	adrp	x10, _DRM_MODE_FLAG_PHSYNC@GOTPAGE
Lloh31:
	ldr	x10, [x10, _DRM_MODE_FLAG_PHSYNC@GOTPAGEOFF]
	tst	w8, w23
	csel	x8, x9, x10, eq
	ldr	w8, [x8]
Lloh32:
	adrp	x9, _DP_SYNC_VS_HIGH@GOTPAGE
Lloh33:
	ldr	x9, [x9, _DP_SYNC_VS_HIGH@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	tst	w9, w23
	b.eq	LBB0_5
; %bb.4:
Lloh35:
	adrp	x9, _DRM_MODE_FLAG_PVSYNC@GOTPAGE
Lloh36:
	ldr	x9, [x9, _DRM_MODE_FLAG_PVSYNC@GOTPAGEOFF]
	b	LBB0_6
LBB0_5:
Lloh37:
	adrp	x9, _DRM_MODE_FLAG_NVSYNC@GOTPAGE
Lloh38:
	ldr	x9, [x9, _DRM_MODE_FLAG_NVSYNC@GOTPAGEOFF]
LBB0_6:
	ldr	w9, [x9]
	orr	w8, w9, w8
	ldr	w9, [x19, #28]
	orr	w8, w9, w8
	str	w8, [x19, #28]
	mov	x0, x20
	bl	_IS_G4X
	cbz	x0, LBB0_9
; %bb.7:
Lloh39:
	adrp	x8, _DP_COLOR_RANGE_16_235@GOTPAGE
Lloh40:
	ldr	x8, [x8, _DP_COLOR_RANGE_16_235@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
	tst	w8, w23
	b.eq	LBB0_9
; %bb.8:
	mov	w8, #1
	str	w8, [x19, #4]
LBB0_9:
Lloh42:
	adrp	x8, _DP_PORT_WIDTH_MASK@GOTPAGE
Lloh43:
	ldr	x8, [x8, _DP_PORT_WIDTH_MASK@GOTPAGEOFF]
Lloh44:
	ldr	w8, [x8]
	and	w8, w8, w23
Lloh45:
	adrp	x9, _DP_PORT_WIDTH_SHIFT@GOTPAGE
Lloh46:
	ldr	x9, [x9, _DP_PORT_WIDTH_SHIFT@GOTPAGEOFF]
Lloh47:
	ldr	w9, [x9]
	asr	w8, w8, w9
	add	w8, w8, #1
	str	w8, [x19, #8]
	mov	x0, x22
	mov	x1, x19
	bl	_intel_dp_get_m_n
	ldr	w8, [x25]
	cmp	w24, w8
	b.ne	LBB0_12
; %bb.10:
Lloh48:
	adrp	x8, _DP_A@GOTPAGE
Lloh49:
	ldr	x8, [x8, _DP_A@GOTPAGEOFF]
Lloh50:
	ldr	w0, [x8]
	bl	_I915_READ
Lloh51:
	adrp	x8, _DP_PLL_FREQ_MASK@GOTPAGE
Lloh52:
	ldr	x8, [x8, _DP_PLL_FREQ_MASK@GOTPAGEOFF]
Lloh53:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh54:
	adrp	x9, _DP_PLL_FREQ_162MHZ@GOTPAGE
Lloh55:
	ldr	x9, [x9, _DP_PLL_FREQ_162MHZ@GOTPAGEOFF]
Lloh56:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_13
; %bb.11:
	mov	w0, #30928
	movk	w0, #2, lsl #16
	b	LBB0_14
LBB0_12:
	ldr	w0, [x19, #12]
	b	LBB0_15
LBB0_13:
	mov	w0, #7856
	movk	w0, #4, lsl #16
LBB0_14:
	str	w0, [x19, #12]
LBB0_15:
	add	x1, x19, #24
	bl	_intel_dotclock_calculate
	str	w0, [x19, #32]
	mov	x0, x21
	bl	_intel_dp_is_edp
	cbz	x0, LBB0_19
; %bb.16:
	ldr	x2, [x20]
	cbz	x2, LBB0_19
; %bb.17:
	ldr	x1, [x19, #16]
	cmp	x1, x2
	b.le	LBB0_19
; %bb.18:
Lloh57:
	adrp	x0, l_.str@PAGE
Lloh58:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_KMS
	ldr	x8, [x19, #16]
	str	x8, [x20]
LBB0_19:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpAdd	Lloh57, Lloh58
	.cfi_endproc
                                        ; -- End function
	.comm	_INTEL_OUTPUT_EDP,8,3           ; @INTEL_OUTPUT_EDP
	.comm	_INTEL_OUTPUT_DP,8,3            ; @INTEL_OUTPUT_DP
	.comm	_DP_AUDIO_OUTPUT_ENABLE,4,2     ; @DP_AUDIO_OUTPUT_ENABLE
	.comm	_PORT_A,4,2                     ; @PORT_A
	.comm	_TRANS_DP_HSYNC_ACTIVE_HIGH,4,2 ; @TRANS_DP_HSYNC_ACTIVE_HIGH
	.comm	_DRM_MODE_FLAG_PHSYNC,4,2       ; @DRM_MODE_FLAG_PHSYNC
	.comm	_DRM_MODE_FLAG_NHSYNC,4,2       ; @DRM_MODE_FLAG_NHSYNC
	.comm	_TRANS_DP_VSYNC_ACTIVE_HIGH,4,2 ; @TRANS_DP_VSYNC_ACTIVE_HIGH
	.comm	_DRM_MODE_FLAG_PVSYNC,4,2       ; @DRM_MODE_FLAG_PVSYNC
	.comm	_DRM_MODE_FLAG_NVSYNC,4,2       ; @DRM_MODE_FLAG_NVSYNC
	.comm	_DP_SYNC_HS_HIGH,4,2            ; @DP_SYNC_HS_HIGH
	.comm	_DP_SYNC_VS_HIGH,4,2            ; @DP_SYNC_VS_HIGH
	.comm	_DP_COLOR_RANGE_16_235,4,2      ; @DP_COLOR_RANGE_16_235
	.comm	_DP_PORT_WIDTH_MASK,4,2         ; @DP_PORT_WIDTH_MASK
	.comm	_DP_PORT_WIDTH_SHIFT,4,2        ; @DP_PORT_WIDTH_SHIFT
	.comm	_DP_A,4,2                       ; @DP_A
	.comm	_DP_PLL_FREQ_MASK,4,2           ; @DP_PLL_FREQ_MASK
	.comm	_DP_PLL_FREQ_162MHZ,4,2         ; @DP_PLL_FREQ_162MHZ
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n"

	.no_dead_strip	_intel_dp_get_config
.subsections_via_symbols
