	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_sor_mode_set
_tegra_sor_mode_set:                    ## @tegra_sor_mode_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, -80(%rbp)                 ## 8-byte Spill
	movq	%rsi, %r14
	movq	%rdi, %r15
	movl	8(%rdi), %edi
	callq	_to_tegra_dc
	movq	%rax, %r12
	movq	_SOR_STATE1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	callq	_tegra_sor_readl
	movl	%eax, %ebx
	movq	_SOR_STATE_ASY_PIXELDEPTH_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_SOR_STATE_ASY_CRC_MODE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	_SOR_STATE_ASY_OWNER_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	_SOR_STATE_ASY_CRC_MODE_COMPLETE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movq	%r12, -64(%rbp)                 ## 8-byte Spill
	movq	(%r12), %rdi
	incq	%rdi
	callq	_SOR_STATE_ASY_OWNER
	movq	%r14, -88(%rbp)                 ## 8-byte Spill
	movl	(%r14), %ecx
	movq	_DRM_MODE_FLAG_PHSYNC@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movq	_SOR_STATE_ASY_HSYNCPOL@GOTPCREL(%rip), %rsi
	movl	(%rsi), %r14d
	movq	_DRM_MODE_FLAG_NHSYNC@GOTPCREL(%rip), %rsi
	movl	(%rsi), %r10d
	movq	_DRM_MODE_FLAG_PVSYNC@GOTPCREL(%rip), %rsi
	movl	(%rsi), %edi
	movq	_SOR_STATE_ASY_VSYNCPOL@GOTPCREL(%rip), %rsi
	movl	(%rsi), %r11d
	movq	_DRM_MODE_FLAG_NVSYNC@GOTPCREL(%rip), %rsi
	movl	(%rsi), %r8d
	movq	-80(%rbp), %rsi                 ## 8-byte Reload
	movl	(%rsi), %esi
	addl	$-6, %esi
	cmpl	$10, %esi
	ja	LBB0_1
## %bb.2:
	movslq	%esi, %r9
	leaq	l_switch.table.tegra_sor_mode_set(%rip), %rsi
	movq	(%rsi,%r9,8), %r9
	jmp	LBB0_3
LBB0_1:
	movq	_SOR_STATE_ASY_PIXELDEPTH_BPP_24_444@GOTPCREL(%rip), %r9
LBB0_3:
	orl	-48(%rbp), %r13d                ## 4-byte Folded Reload
	orl	-44(%rbp), %r13d                ## 4-byte Folded Reload
	notl	%r13d
	andl	%r13d, %ebx
	orl	-52(%rbp), %ebx                 ## 4-byte Folded Reload
	orl	%eax, %ebx
	andl	%ecx, %edx
	movl	%r14d, %eax
	notl	%eax
	xorl	%esi, %esi
	cmpl	$1, %edx
	movl	$0, %edx
	sbbl	%edx, %edx
	orl	%eax, %edx
	andl	%ebx, %edx
	orl	%r14d, %ebx
	testl	%ecx, %r10d
	cmovel	%edx, %ebx
	andl	%ecx, %edi
	cmpl	$1, %edi
	movl	%r11d, %eax
	notl	%eax
	sbbl	%esi, %esi
	orl	%eax, %esi
	andl	%ebx, %esi
	orl	%r11d, %ebx
	testl	%ecx, %r8d
	cmovel	%esi, %ebx
	orl	(%r9), %ebx
	movq	_SOR_STATE1@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_tegra_sor_writel
	movq	-88(%rbp), %r12                 ## 8-byte Reload
	movl	4(%r12), %eax
	shll	$16, %eax
	andl	$2147418112, %eax               ## imm = 0x7FFF0000
	movl	$32767, %esi                    ## imm = 0x7FFF
	andl	8(%r12), %esi
	orl	%eax, %esi
	movq	(%r15), %rax
	movq	(%rax), %rax
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	movq	(%rbx), %rdx
	addq	32(%rax), %rdx
	movq	%r15, %rdi
	callq	_tegra_sor_writel
	movq	%r15, %rdi
	movq	%r15, -72(%rbp)                 ## 8-byte Spill
	movl	16(%r12), %r15d
	movl	24(%r12), %r14d
	notl	%r15d
	addl	12(%r12), %r15d
	notl	%r14d
	addl	20(%r12), %r14d
	movl	%r15d, %eax
	shll	$16, %eax
	andl	$2147418112, %eax               ## imm = 0x7FFF0000
	movl	%r14d, %esi
	andl	$32767, %esi                    ## imm = 0x7FFF
	orl	%eax, %esi
	movq	(%rdi), %rax
	movq	(%rax), %rax
	movq	(%rbx), %rdx
	addq	24(%rax), %rdx
	callq	_tegra_sor_writel
	movl	4(%r12), %ebx
	movl	8(%r12), %r13d
	subl	12(%r12), %ebx
	addl	%r15d, %ebx
	subl	20(%r12), %r13d
	addl	%r14d, %r13d
	movl	%ebx, %eax
	shll	$16, %eax
	andl	$2147418112, %eax               ## imm = 0x7FFF0000
	movl	%r13d, %esi
	andl	$32767, %esi                    ## imm = 0x7FFF
	orl	%eax, %esi
	movq	-72(%rbp), %rdi                 ## 8-byte Reload
	movq	(%rdi), %rax
	movq	(%rax), %rax
	movq	-64(%rbp), %r15                 ## 8-byte Reload
	movq	(%r15), %rdx
	addq	16(%rax), %rdx
	movq	%rdi, %r14
	callq	_tegra_sor_writel
	addl	28(%r12), %ebx
	addl	32(%r12), %r13d
	shll	$16, %ebx
	andl	$2147418112, %ebx               ## imm = 0x7FFF0000
	andl	$32767, %r13d                   ## imm = 0x7FFF
	orl	%ebx, %r13d
	movq	%r14, %rbx
	movq	(%r14), %rax
	movq	(%rax), %rax
	movq	%r15, %r14
	movq	(%r15), %rdx
	addq	8(%rax), %rdx
	movq	%rbx, %rdi
	movl	%r13d, %esi
	callq	_tegra_sor_writel
	movq	(%rbx), %rax
	movq	(%rax), %rax
	movq	(%r14), %rdx
	addq	(%rax), %rdx
	movq	%rbx, %rdi
	movl	$1, %esi
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_tegra_sor_writel               ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_SOR_STATE1,8,3                 ## @SOR_STATE1
	.comm	_SOR_STATE_ASY_PIXELDEPTH_MASK,4,2 ## @SOR_STATE_ASY_PIXELDEPTH_MASK
	.comm	_SOR_STATE_ASY_CRC_MODE_MASK,4,2 ## @SOR_STATE_ASY_CRC_MODE_MASK
	.comm	_SOR_STATE_ASY_OWNER_MASK,4,2   ## @SOR_STATE_ASY_OWNER_MASK
	.comm	_SOR_STATE_ASY_CRC_MODE_COMPLETE,4,2 ## @SOR_STATE_ASY_CRC_MODE_COMPLETE
	.comm	_DRM_MODE_FLAG_PHSYNC,4,2       ## @DRM_MODE_FLAG_PHSYNC
	.comm	_SOR_STATE_ASY_HSYNCPOL,4,2     ## @SOR_STATE_ASY_HSYNCPOL
	.comm	_DRM_MODE_FLAG_NHSYNC,4,2       ## @DRM_MODE_FLAG_NHSYNC
	.comm	_DRM_MODE_FLAG_PVSYNC,4,2       ## @DRM_MODE_FLAG_PVSYNC
	.comm	_SOR_STATE_ASY_VSYNCPOL,4,2     ## @SOR_STATE_ASY_VSYNCPOL
	.comm	_DRM_MODE_FLAG_NVSYNC,4,2       ## @DRM_MODE_FLAG_NVSYNC
	.comm	_SOR_STATE_ASY_PIXELDEPTH_BPP_48_444,4,2 ## @SOR_STATE_ASY_PIXELDEPTH_BPP_48_444
	.comm	_SOR_STATE_ASY_PIXELDEPTH_BPP_36_444,4,2 ## @SOR_STATE_ASY_PIXELDEPTH_BPP_36_444
	.comm	_SOR_STATE_ASY_PIXELDEPTH_BPP_30_444,4,2 ## @SOR_STATE_ASY_PIXELDEPTH_BPP_30_444
	.comm	_SOR_STATE_ASY_PIXELDEPTH_BPP_24_444,4,2 ## @SOR_STATE_ASY_PIXELDEPTH_BPP_24_444
	.comm	_SOR_STATE_ASY_PIXELDEPTH_BPP_18_444,4,2 ## @SOR_STATE_ASY_PIXELDEPTH_BPP_18_444
	.no_dead_strip	_tegra_sor_mode_set
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.tegra_sor_mode_set
l_switch.table.tegra_sor_mode_set:
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_18_444
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_24_444
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_24_444
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_24_444
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_30_444
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_24_444
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_36_444
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_24_444
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_24_444
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_24_444
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_48_444

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_sor_mode_set
_tegra_sor_mode_set:                    ; @tegra_sor_mode_set
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x23, x2
	mov	x21, x1
	mov	x19, x0
	ldr	w0, [x0, #8]
	bl	_to_tegra_dc
	mov	x20, x0
Lloh0:
	adrp	x24, _SOR_STATE1@GOTPAGE
Lloh1:
	ldr	x24, [x24, _SOR_STATE1@GOTPAGEOFF]
	ldr	x1, [x24]
	mov	x0, x19
	bl	_tegra_sor_readl
	mov	x22, x0
Lloh2:
	adrp	x8, _SOR_STATE_ASY_PIXELDEPTH_MASK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _SOR_STATE_ASY_PIXELDEPTH_MASK@GOTPAGEOFF]
Lloh4:
	ldr	w25, [x8]
Lloh5:
	adrp	x8, _SOR_STATE_ASY_CRC_MODE_MASK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _SOR_STATE_ASY_CRC_MODE_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w26, [x8]
Lloh8:
	adrp	x8, _SOR_STATE_ASY_OWNER_MASK@GOTPAGE
Lloh9:
	ldr	x8, [x8, _SOR_STATE_ASY_OWNER_MASK@GOTPAGEOFF]
Lloh10:
	ldr	w27, [x8]
Lloh11:
	adrp	x8, _SOR_STATE_ASY_CRC_MODE_COMPLETE@GOTPAGE
Lloh12:
	ldr	x8, [x8, _SOR_STATE_ASY_CRC_MODE_COMPLETE@GOTPAGEOFF]
Lloh13:
	ldr	w28, [x8]
	ldr	x8, [x20]
	add	x0, x8, #1
	bl	_SOR_STATE_ASY_OWNER
	ldr	w8, [x21]
Lloh14:
	adrp	x9, _DRM_MODE_FLAG_PHSYNC@GOTPAGE
Lloh15:
	ldr	x9, [x9, _DRM_MODE_FLAG_PHSYNC@GOTPAGEOFF]
Lloh16:
	ldr	w13, [x9]
Lloh17:
	adrp	x9, _SOR_STATE_ASY_HSYNCPOL@GOTPAGE
Lloh18:
	ldr	x9, [x9, _SOR_STATE_ASY_HSYNCPOL@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
Lloh20:
	adrp	x10, _DRM_MODE_FLAG_NHSYNC@GOTPAGE
Lloh21:
	ldr	x10, [x10, _DRM_MODE_FLAG_NHSYNC@GOTPAGEOFF]
Lloh22:
	ldr	w11, [x10]
Lloh23:
	adrp	x10, _DRM_MODE_FLAG_PVSYNC@GOTPAGE
Lloh24:
	ldr	x10, [x10, _DRM_MODE_FLAG_PVSYNC@GOTPAGEOFF]
Lloh25:
	ldr	w12, [x10]
Lloh26:
	adrp	x10, _SOR_STATE_ASY_VSYNCPOL@GOTPAGE
Lloh27:
	ldr	x10, [x10, _SOR_STATE_ASY_VSYNCPOL@GOTPAGEOFF]
Lloh28:
	ldr	w10, [x10]
Lloh29:
	adrp	x14, _DRM_MODE_FLAG_NVSYNC@GOTPAGE
Lloh30:
	ldr	x14, [x14, _DRM_MODE_FLAG_NVSYNC@GOTPAGEOFF]
	ldr	w15, [x23]
	sub	w15, w15, #6
Lloh31:
	ldr	w14, [x14]
	cmp	w15, #10
	b.hi	LBB0_2
; %bb.1:
Lloh32:
	adrp	x16, l_switch.table.tegra_sor_mode_set@PAGE
Lloh33:
	add	x16, x16, l_switch.table.tegra_sor_mode_set@PAGEOFF
	ldr	x15, [x16, w15, sxtw #3]
	b	LBB0_3
LBB0_2:
Lloh34:
	adrp	x15, _SOR_STATE_ASY_PIXELDEPTH_BPP_24_444@GOTPAGE
Lloh35:
	ldr	x15, [x15, _SOR_STATE_ASY_PIXELDEPTH_BPP_24_444@GOTPAGEOFF]
LBB0_3:
	orr	w16, w26, w25
	orr	w16, w16, w27
	bic	w16, w22, w16
	orr	w16, w16, w28
	orr	w16, w16, w0
	tst	w13, w8
	mov	w13, #-1
	csinv	w17, w13, w9, eq
	and	w17, w17, w16
	orr	w9, w9, w16
	tst	w11, w8
	csel	w9, w17, w9, eq
	tst	w12, w8
	csinv	w11, w13, w10, eq
	and	w11, w11, w9
	orr	w9, w9, w10
	tst	w14, w8
	csel	w8, w11, w9, eq
	ldr	w9, [x15]
	orr	w1, w9, w8
	ldr	x2, [x24]
	mov	x0, x19
	bl	_tegra_sor_writel
	ldp	w8, w9, [x21, #4]
	and	w1, w9, #0x7fff
	bfi	w1, w8, #16, #15
	ldr	x8, [x19]
	ldr	x8, [x8]
	ldr	x8, [x8, #32]
	ldr	x9, [x20]
	add	x2, x9, x8
	mov	x0, x19
	bl	_tegra_sor_writel
	ldp	w8, w9, [x21, #12]
	mvn	w9, w9
	add	w22, w8, w9
	ldp	w8, w9, [x21, #20]
	mvn	w9, w9
	add	w23, w8, w9
	and	w1, w23, #0x7fff
	bfi	w1, w22, #16, #15
	ldr	x8, [x19]
	ldr	x8, [x8]
	ldr	x8, [x8, #24]
	ldr	x9, [x20]
	add	x2, x9, x8
	mov	x0, x19
	bl	_tegra_sor_writel
	ldp	w10, w8, [x21, #8]
	ldr	w9, [x21, #4]
	sub	w8, w9, w8
	add	w22, w8, w22
	ldr	w8, [x21, #20]
	sub	w8, w10, w8
	add	w23, w8, w23
	and	w1, w23, #0x7fff
	bfi	w1, w22, #16, #15
	ldr	x8, [x19]
	ldr	x8, [x8]
	ldr	x8, [x8, #16]
	ldr	x9, [x20]
	add	x2, x9, x8
	mov	x0, x19
	bl	_tegra_sor_writel
	ldp	w8, w9, [x21, #28]
	add	w8, w8, w22
	add	w9, w9, w23
	and	w1, w9, #0x7fff
	bfi	w1, w8, #16, #15
	ldr	x8, [x19]
	ldr	x8, [x8]
	ldr	x8, [x8, #8]
	ldr	x9, [x20]
	add	x2, x9, x8
	mov	x0, x19
	bl	_tegra_sor_writel
	ldr	x8, [x19]
	ldr	x8, [x8]
	ldr	x8, [x8]
	ldr	x9, [x20]
	add	x2, x9, x8
	mov	x0, x19
	mov	w1, #1
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_tegra_sor_writel
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh34, Lloh35
	.cfi_endproc
                                        ; -- End function
	.comm	_SOR_STATE1,8,3                 ; @SOR_STATE1
	.comm	_SOR_STATE_ASY_PIXELDEPTH_MASK,4,2 ; @SOR_STATE_ASY_PIXELDEPTH_MASK
	.comm	_SOR_STATE_ASY_CRC_MODE_MASK,4,2 ; @SOR_STATE_ASY_CRC_MODE_MASK
	.comm	_SOR_STATE_ASY_OWNER_MASK,4,2   ; @SOR_STATE_ASY_OWNER_MASK
	.comm	_SOR_STATE_ASY_CRC_MODE_COMPLETE,4,2 ; @SOR_STATE_ASY_CRC_MODE_COMPLETE
	.comm	_DRM_MODE_FLAG_PHSYNC,4,2       ; @DRM_MODE_FLAG_PHSYNC
	.comm	_SOR_STATE_ASY_HSYNCPOL,4,2     ; @SOR_STATE_ASY_HSYNCPOL
	.comm	_DRM_MODE_FLAG_NHSYNC,4,2       ; @DRM_MODE_FLAG_NHSYNC
	.comm	_DRM_MODE_FLAG_PVSYNC,4,2       ; @DRM_MODE_FLAG_PVSYNC
	.comm	_SOR_STATE_ASY_VSYNCPOL,4,2     ; @SOR_STATE_ASY_VSYNCPOL
	.comm	_DRM_MODE_FLAG_NVSYNC,4,2       ; @DRM_MODE_FLAG_NVSYNC
	.comm	_SOR_STATE_ASY_PIXELDEPTH_BPP_48_444,4,2 ; @SOR_STATE_ASY_PIXELDEPTH_BPP_48_444
	.comm	_SOR_STATE_ASY_PIXELDEPTH_BPP_36_444,4,2 ; @SOR_STATE_ASY_PIXELDEPTH_BPP_36_444
	.comm	_SOR_STATE_ASY_PIXELDEPTH_BPP_30_444,4,2 ; @SOR_STATE_ASY_PIXELDEPTH_BPP_30_444
	.comm	_SOR_STATE_ASY_PIXELDEPTH_BPP_24_444,4,2 ; @SOR_STATE_ASY_PIXELDEPTH_BPP_24_444
	.comm	_SOR_STATE_ASY_PIXELDEPTH_BPP_18_444,4,2 ; @SOR_STATE_ASY_PIXELDEPTH_BPP_18_444
	.no_dead_strip	_tegra_sor_mode_set
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.tegra_sor_mode_set
l_switch.table.tegra_sor_mode_set:
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_18_444
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_24_444
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_24_444
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_24_444
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_30_444
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_24_444
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_36_444
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_24_444
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_24_444
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_24_444
	.quad	_SOR_STATE_ASY_PIXELDEPTH_BPP_48_444

.subsections_via_symbols
