	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_uvd_v4_2_resume                ## -- Begin function uvd_v4_2_resume
	.p2align	4, 0x90
_uvd_v4_2_resume:                       ## @uvd_v4_2_resume
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movl	(%rdi), %eax
	leal	512(%rax), %ebx
	cmpq	$0, 8(%rdi)
	cmovel	%eax, %ebx
	sarl	$3, %ebx
	movq	16(%rdi), %rax
	movq	(%rax), %rdi
	addq	$4, %rdi
	callq	_RADEON_GPU_PAGE_ALIGN
	movl	%eax, %r15d
	sarl	$3, %r15d
	movq	_UVD_VCPU_CACHE_OFFSET0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_UVD_VCPU_CACHE_SIZE0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r15d, %esi
	callq	_WREG32
	addl	%ebx, %r15d
	movq	_RADEON_UVD_HEAP_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	sarl	$3, %r12d
	movq	_UVD_VCPU_CACHE_OFFSET1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movq	_UVD_VCPU_CACHE_SIZE1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_RADEON_UVD_SESSION_SIZE@GOTPCREL(%rip), %rax
	movl	4(%r14), %ebx
	imull	(%rax), %ebx
	movq	_RADEON_UVD_STACK_SIZE@GOTPCREL(%rip), %rax
	addl	(%rax), %ebx
	addl	%r15d, %r12d
	sarl	$3, %ebx
	movq	_UVD_VCPU_CACHE_OFFSET2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	_UVD_VCPU_CACHE_SIZE2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	(%r14), %eax
	shrl	$28, %eax
	movq	_UVD_LMI_ADDR_EXT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%eax, %esi
	shll	$12, %esi
	orl	%eax, %esi
	callq	_WREG32
	movq	_UVD_LMI_EXT40_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32
	cmpq	$0, 8(%r14)
	je	LBB0_2
## %bb.1:
	movq	_UVD_GP_SCRATCH4@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	4(%r14), %esi
	callq	_WREG32
LBB0_2:
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_UVD_VCPU_CACHE_OFFSET0,4,2     ## @UVD_VCPU_CACHE_OFFSET0
	.comm	_UVD_VCPU_CACHE_SIZE0,4,2       ## @UVD_VCPU_CACHE_SIZE0
	.comm	_RADEON_UVD_HEAP_SIZE,4,2       ## @RADEON_UVD_HEAP_SIZE
	.comm	_UVD_VCPU_CACHE_OFFSET1,4,2     ## @UVD_VCPU_CACHE_OFFSET1
	.comm	_UVD_VCPU_CACHE_SIZE1,4,2       ## @UVD_VCPU_CACHE_SIZE1
	.comm	_RADEON_UVD_STACK_SIZE,4,2      ## @RADEON_UVD_STACK_SIZE
	.comm	_RADEON_UVD_SESSION_SIZE,4,2    ## @RADEON_UVD_SESSION_SIZE
	.comm	_UVD_VCPU_CACHE_OFFSET2,4,2     ## @UVD_VCPU_CACHE_OFFSET2
	.comm	_UVD_VCPU_CACHE_SIZE2,4,2       ## @UVD_VCPU_CACHE_SIZE2
	.comm	_UVD_LMI_ADDR_EXT,4,2           ## @UVD_LMI_ADDR_EXT
	.comm	_UVD_LMI_EXT40_ADDR,4,2         ## @UVD_LMI_EXT40_ADDR
	.comm	_UVD_GP_SCRATCH4,4,2            ## @UVD_GP_SCRATCH4
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_uvd_v4_2_resume                ; -- Begin function uvd_v4_2_resume
	.p2align	2
_uvd_v4_2_resume:                       ; @uvd_v4_2_resume
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	w8, [x0]
	add	w9, w8, #512
	ldp	x10, x11, [x0, #8]
	cmp	x10, #0
	csel	w8, w8, w9, eq
	asr	w20, w8, #3
	ldr	x8, [x11]
	add	x0, x8, #4
	bl	_RADEON_GPU_PAGE_ALIGN
	asr	w21, w0, #3
Lloh0:
	adrp	x8, _UVD_VCPU_CACHE_OFFSET0@GOTPAGE
Lloh1:
	ldr	x8, [x8, _UVD_VCPU_CACHE_OFFSET0@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh3:
	adrp	x8, _UVD_VCPU_CACHE_SIZE0@GOTPAGE
Lloh4:
	ldr	x8, [x8, _UVD_VCPU_CACHE_SIZE0@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	mov	x1, x21
	bl	_WREG32
Lloh6:
	adrp	x8, _RADEON_UVD_HEAP_SIZE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RADEON_UVD_HEAP_SIZE@GOTPAGEOFF]
	add	w20, w21, w20
Lloh8:
	ldr	w8, [x8]
	asr	w21, w8, #3
Lloh9:
	adrp	x8, _UVD_VCPU_CACHE_OFFSET1@GOTPAGE
Lloh10:
	ldr	x8, [x8, _UVD_VCPU_CACHE_OFFSET1@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh12:
	adrp	x8, _UVD_VCPU_CACHE_SIZE1@GOTPAGE
Lloh13:
	ldr	x8, [x8, _UVD_VCPU_CACHE_SIZE1@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	mov	x1, x21
	bl	_WREG32
	add	w1, w21, w20
Lloh15:
	adrp	x8, _RADEON_UVD_STACK_SIZE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _RADEON_UVD_STACK_SIZE@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
Lloh18:
	adrp	x9, _RADEON_UVD_SESSION_SIZE@GOTPAGE
Lloh19:
	ldr	x9, [x9, _RADEON_UVD_SESSION_SIZE@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	ldr	w10, [x19, #4]
	madd	w8, w10, w9, w8
	asr	w20, w8, #3
Lloh21:
	adrp	x8, _UVD_VCPU_CACHE_OFFSET2@GOTPAGE
Lloh22:
	ldr	x8, [x8, _UVD_VCPU_CACHE_OFFSET2@GOTPAGEOFF]
Lloh23:
	ldr	w0, [x8]
	bl	_WREG32
Lloh24:
	adrp	x8, _UVD_VCPU_CACHE_SIZE2@GOTPAGE
Lloh25:
	ldr	x8, [x8, _UVD_VCPU_CACHE_SIZE2@GOTPAGEOFF]
Lloh26:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
	ldr	w8, [x19]
	lsr	w1, w8, #28
Lloh27:
	adrp	x8, _UVD_LMI_ADDR_EXT@GOTPAGE
Lloh28:
	ldr	x8, [x8, _UVD_LMI_ADDR_EXT@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	bfi	w1, w1, #12, #4
	bl	_WREG32
Lloh30:
	adrp	x8, _UVD_LMI_EXT40_ADDR@GOTPAGE
Lloh31:
	ldr	x8, [x8, _UVD_LMI_EXT40_ADDR@GOTPAGEOFF]
Lloh32:
	ldr	w0, [x8]
	bl	_WREG32
	ldr	x8, [x19, #8]
	cbz	x8, LBB0_2
; %bb.1:
Lloh33:
	adrp	x8, _UVD_GP_SCRATCH4@GOTPAGE
Lloh34:
	ldr	x8, [x8, _UVD_GP_SCRATCH4@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	ldr	w1, [x19, #4]
	bl	_WREG32
LBB0_2:
	mov	w0, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.cfi_endproc
                                        ; -- End function
	.comm	_UVD_VCPU_CACHE_OFFSET0,4,2     ; @UVD_VCPU_CACHE_OFFSET0
	.comm	_UVD_VCPU_CACHE_SIZE0,4,2       ; @UVD_VCPU_CACHE_SIZE0
	.comm	_RADEON_UVD_HEAP_SIZE,4,2       ; @RADEON_UVD_HEAP_SIZE
	.comm	_UVD_VCPU_CACHE_OFFSET1,4,2     ; @UVD_VCPU_CACHE_OFFSET1
	.comm	_UVD_VCPU_CACHE_SIZE1,4,2       ; @UVD_VCPU_CACHE_SIZE1
	.comm	_RADEON_UVD_STACK_SIZE,4,2      ; @RADEON_UVD_STACK_SIZE
	.comm	_RADEON_UVD_SESSION_SIZE,4,2    ; @RADEON_UVD_SESSION_SIZE
	.comm	_UVD_VCPU_CACHE_OFFSET2,4,2     ; @UVD_VCPU_CACHE_OFFSET2
	.comm	_UVD_VCPU_CACHE_SIZE2,4,2       ; @UVD_VCPU_CACHE_SIZE2
	.comm	_UVD_LMI_ADDR_EXT,4,2           ; @UVD_LMI_ADDR_EXT
	.comm	_UVD_LMI_EXT40_ADDR,4,2         ; @UVD_LMI_EXT40_ADDR
	.comm	_UVD_GP_SCRATCH4,4,2            ; @UVD_GP_SCRATCH4
.subsections_via_symbols
