	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_meson_hdmi_pll_set_params      ## -- Begin function meson_hdmi_pll_set_params
	.p2align	4, 0x90
_meson_hdmi_pll_set_params:             ## @meson_hdmi_pll_set_params
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%r9d, %r15d
	movl	%r8d, %ebx
	movl	%ecx, -44(%rbp)                 ## 4-byte Spill
	movl	%edx, %r13d
	movl	%esi, %r12d
	movq	%rdi, %r14
	movq	_VPU_COMPATIBLE_GXBB@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	movl	%r15d, -52(%rbp)                ## 4-byte Spill
	movl	%ebx, -48(%rbp)                 ## 4-byte Spill
	je	LBB0_3
## %bb.1:
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	$1476395520, %r12d              ## imm = 0x58000200
	movl	%r12d, %edx
	callq	_regmap_write
	movl	%r13d, %edx
	orl	$16384, %edx                    ## imm = 0x4000
	testl	%r13d, %r13d
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	cmovel	%r13d, %edx
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$224153745, %edx                ## imm = 0xD5C5091
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL4@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$-2145540308, %edx              ## imm = 0x801DA72C
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL5@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1900571008, %edx               ## imm = 0x71486980
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL6@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$3669, %edx                     ## imm = 0xE55
	callq	_regmap_write
	movq	_HHI_HDMI_PLL_CNTL_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	$1879048192, %edx               ## imm = 0x70000000
	jmp	LBB0_2
LBB0_3:
	movq	_VPU_COMPATIBLE_GXM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	jne	LBB0_5
## %bb.4:
	movq	_VPU_COMPATIBLE_GXL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_6
LBB0_5:
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	orl	$1073742336, %r12d              ## imm = 0x40000200
	movl	%r12d, %edx
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	$-2146652160, %r13d             ## imm = 0x800CB000
	movl	%r13d, %edx
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$-2045824828, %edx              ## imm = 0x860F30C4
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL4@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$210632704, %edx                ## imm = 0xC8E0000
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL5@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$2074409, %edx                  ## imm = 0x1FA729
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL6@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$27464960, %edx                 ## imm = 0x1A31500
	callq	_regmap_write
	movl	(%r14), %edi
	movl	(%r15), %esi
	movq	_HDMI_PLL_RESET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%rbx), %edx
	xorl	%ecx, %ecx
LBB0_2:
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	callq	_regmap_update_bits
	movl	(%r14), %edi
	movl	(%rbx), %esi
	xorl	%ecx, %ecx
	movl	$10, %r8d
	xorl	%r9d, %r9d
	callq	_regmap_read_poll_timeout
LBB0_12:
	movq	_VPU_COMPATIBLE_GXBB@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_14
## %bb.13:
	movq	_HHI_HDMI_PLL_CNTL2@GOTPCREL(%rip), %r12
LBB0_18:
	movl	$16, %ebx
	movl	$196608, %r13d                  ## imm = 0x30000
	jmp	LBB0_19
LBB0_14:
	movq	_VPU_COMPATIBLE_GXM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	movl	$6291456, %r13d                 ## imm = 0x600000
	movl	$21, %ebx
	movq	_HHI_HDMI_PLL_CNTL3@GOTPCREL(%rip), %r12
	testq	%rax, %rax
	jne	LBB0_19
## %bb.15:
	movq	_VPU_COMPATIBLE_GXL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_16
LBB0_19:
	movl	(%r14), %r15d
	movl	(%r12), %r12d
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	callq	_pll_od_to_reg
	movl	%ebx, %ecx
	shll	%cl, %eax
	movl	%r15d, %edi
	movl	%r12d, %esi
	movl	%r13d, %edx
	movl	%eax, %ecx
	callq	_regmap_update_bits
LBB0_20:
	movq	_VPU_COMPATIBLE_GXBB@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_22
## %bb.21:
	movl	$12582912, %r15d                ## imm = 0xC00000
	movl	$22, %r12d
	movq	_HHI_HDMI_PLL_CNTL2@GOTPCREL(%rip), %r13
	jmp	LBB0_26
LBB0_22:
	movq	_VPU_COMPATIBLE_GXM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	movl	$25165824, %r15d                ## imm = 0x1800000
	movl	$23, %r12d
	movq	_HHI_HDMI_PLL_CNTL3@GOTPCREL(%rip), %r13
	testq	%rax, %rax
	jne	LBB0_26
## %bb.23:
	movq	_VPU_COMPATIBLE_GXL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	jne	LBB0_26
## %bb.24:
	movq	_VPU_COMPATIBLE_G12A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_27
## %bb.25:
	movl	$786432, %r15d                  ## imm = 0xC0000
	movl	$18, %r12d
	movq	_HHI_HDMI_PLL_CNTL@GOTPCREL(%rip), %r13
LBB0_26:
	movl	(%r14), %ebx
	movl	(%r13), %r13d
	movl	-48(%rbp), %edi                 ## 4-byte Reload
	callq	_pll_od_to_reg
	movl	%r12d, %ecx
	shll	%cl, %eax
	movl	%ebx, %edi
	movl	%r13d, %esi
	movl	%r15d, %edx
	movl	%eax, %ecx
	callq	_regmap_update_bits
LBB0_27:
	movq	_VPU_COMPATIBLE_GXBB@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_29
## %bb.28:
	movl	$786432, %r12d                  ## imm = 0xC0000
	movl	$18, %r15d
	movq	_HHI_HDMI_PLL_CNTL2@GOTPCREL(%rip), %r13
	jmp	LBB0_33
LBB0_29:
	movq	_VPU_COMPATIBLE_GXM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	movl	$1572864, %r12d                 ## imm = 0x180000
	movl	$19, %r15d
	movq	_HHI_HDMI_PLL_CNTL3@GOTPCREL(%rip), %r13
	testq	%rax, %rax
	jne	LBB0_33
## %bb.30:
	movq	_VPU_COMPATIBLE_GXL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	jne	LBB0_33
## %bb.31:
	movq	_VPU_COMPATIBLE_G12A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_34
## %bb.32:
	movl	$3145728, %r12d                 ## imm = 0x300000
	movl	$20, %r15d
	movq	_HHI_HDMI_PLL_CNTL@GOTPCREL(%rip), %r13
LBB0_33:
	movl	(%r14), %ebx
	movl	(%r13), %r14d
	movl	-52(%rbp), %edi                 ## 4-byte Reload
	callq	_pll_od_to_reg
	movl	%r15d, %ecx
	shll	%cl, %eax
	movl	%ebx, %edi
	movl	%r14d, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_regmap_update_bits             ## TAILCALL
LBB0_6:
	movq	_VPU_COMPATIBLE_G12A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_12
## %bb.7:
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movl	%r12d, %edx
	orl	$188351488, %edx                ## imm = 0xB3A0400
	callq	_regmap_write
	movl	(%r14), %edi
	movl	(%r15), %esi
	movl	$805306368, %edx                ## imm = 0x30000000
	movl	$805306368, %ecx                ## imm = 0x30000000
	callq	_regmap_update_bits
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r13d, %edx
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	cmpl	$247, %r12d
	jb	LBB0_9
## %bb.8:
	cmpl	$65536, %r13d                   ## imm = 0x10000
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL4@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1785224192, %eax               ## imm = 0x6A685C00
	movl	$-362226688, %edx               ## imm = 0xEA68DC00
	cmovbl	%eax, %edx
	movl	$290787987, %eax                ## imm = 0x11551293
	movl	$1702302352, %r13d              ## imm = 0x65771290
	cmovbl	%eax, %r13d
	callq	_regmap_write
	movl	$1431568384, %r12d              ## imm = 0x55540000
	movl	$958865408, %ebx                ## imm = 0x39272000
	jmp	LBB0_10
LBB0_16:
	movq	_VPU_COMPATIBLE_G12A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_20
## %bb.17:
	movq	_HHI_HDMI_PLL_CNTL@GOTPCREL(%rip), %r12
	jmp	LBB0_18
LBB0_34:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_9:
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL4@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$174660608, %edx                ## imm = 0xA691C00
	callq	_regmap_write
	movl	$1347682304, %r12d              ## imm = 0x50540000
	movl	$958857216, %ebx                ## imm = 0x39270000
	movl	$863441552, %r13d               ## imm = 0x33771290
LBB0_10:
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL5@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r13d, %edx
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL6@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%ebx, %edx
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL7@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r12d, %edx
	callq	_regmap_write
	movq	_HDMI_PLL_RESET_G12A@GOTPCREL(%rip), %rbx
	movq	_HDMI_PLL_LOCK_G12A@GOTPCREL(%rip), %r12
	.p2align	4, 0x90
LBB0_11:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %edi
	movl	(%r15), %esi
	movl	(%rbx), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r14), %edi
	movl	(%r15), %esi
	movl	(%rbx), %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	(%r14), %edi
	movl	(%r15), %esi
	xorl	%ecx, %ecx
	cmpl	$0, (%r12)
	sete	%cl
	movl	$10, %r8d
	movl	$100, %r9d
	callq	_regmap_read_poll_timeout
	testl	%eax, %eax
	jne	LBB0_11
	jmp	LBB0_12
	.cfi_endproc
                                        ## -- End function
	.comm	_VPU_COMPATIBLE_GXBB,4,2        ## @VPU_COMPATIBLE_GXBB
	.comm	_HHI_HDMI_PLL_CNTL,4,2          ## @HHI_HDMI_PLL_CNTL
	.comm	_HHI_HDMI_PLL_CNTL2,4,2         ## @HHI_HDMI_PLL_CNTL2
	.comm	_HHI_HDMI_PLL_CNTL3,4,2         ## @HHI_HDMI_PLL_CNTL3
	.comm	_HHI_HDMI_PLL_CNTL4,4,2         ## @HHI_HDMI_PLL_CNTL4
	.comm	_HHI_HDMI_PLL_CNTL5,4,2         ## @HHI_HDMI_PLL_CNTL5
	.comm	_HHI_HDMI_PLL_CNTL6,4,2         ## @HHI_HDMI_PLL_CNTL6
	.comm	_HHI_HDMI_PLL_CNTL_EN,4,2       ## @HHI_HDMI_PLL_CNTL_EN
	.comm	_HDMI_PLL_LOCK,4,2              ## @HDMI_PLL_LOCK
	.comm	_VPU_COMPATIBLE_GXM,4,2         ## @VPU_COMPATIBLE_GXM
	.comm	_VPU_COMPATIBLE_GXL,4,2         ## @VPU_COMPATIBLE_GXL
	.comm	_HDMI_PLL_RESET,4,2             ## @HDMI_PLL_RESET
	.comm	_VPU_COMPATIBLE_G12A,4,2        ## @VPU_COMPATIBLE_G12A
	.comm	_HHI_HDMI_PLL_CNTL7,4,2         ## @HHI_HDMI_PLL_CNTL7
	.comm	_HDMI_PLL_RESET_G12A,4,2        ## @HDMI_PLL_RESET_G12A
	.comm	_HDMI_PLL_LOCK_G12A,4,2         ## @HDMI_PLL_LOCK_G12A
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_meson_hdmi_pll_set_params      ; -- Begin function meson_hdmi_pll_set_params
	.p2align	2
_meson_hdmi_pll_set_params:             ; @meson_hdmi_pll_set_params
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x5
	mov	x21, x4
	mov	x22, x3
	mov	x23, x2
	mov	x24, x1
	mov	x20, x0
Lloh0:
	adrp	x26, _VPU_COMPATIBLE_GXBB@GOTPAGE
Lloh1:
	ldr	x26, [x26, _VPU_COMPATIBLE_GXBB@GOTPAGEOFF]
	ldr	w1, [x26]
	bl	_meson_vpu_is_compatible
Lloh2:
	adrp	x27, _HHI_HDMI_PLL_CNTL@GOTPAGE
Lloh3:
	ldr	x27, [x27, _HHI_HDMI_PLL_CNTL@GOTPAGEOFF]
	cbz	x0, LBB0_2
; %bb.1:
	ldr	w0, [x20]
	ldr	w1, [x27]
	mov	w8, #512
	movk	w8, #22528, lsl #16
	orr	w2, w24, w8
	bl	_regmap_write
	ldr	w0, [x20]
Lloh4:
	adrp	x8, _HHI_HDMI_PLL_CNTL2@GOTPAGE
Lloh5:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL2@GOTPAGEOFF]
Lloh6:
	ldr	w1, [x8]
	orr	w8, w23, #0x4000
	cmp	w23, #0
	csel	w2, wzr, w8, eq
	bl	_regmap_write
	ldr	w0, [x20]
Lloh7:
	adrp	x8, _HHI_HDMI_PLL_CNTL3@GOTPAGE
Lloh8:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL3@GOTPAGEOFF]
Lloh9:
	ldr	w1, [x8]
	mov	w2, #20625
	movk	w2, #3420, lsl #16
	bl	_regmap_write
	ldr	w0, [x20]
Lloh10:
	adrp	x8, _HHI_HDMI_PLL_CNTL4@GOTPAGE
Lloh11:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL4@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
	mov	w2, #42796
	movk	w2, #32797, lsl #16
	bl	_regmap_write
	ldr	w0, [x20]
Lloh13:
	adrp	x8, _HHI_HDMI_PLL_CNTL5@GOTPAGE
Lloh14:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL5@GOTPAGEOFF]
Lloh15:
	ldr	w1, [x8]
	mov	w2, #27008
	movk	w2, #29000, lsl #16
	bl	_regmap_write
	ldr	w0, [x20]
Lloh16:
	adrp	x8, _HHI_HDMI_PLL_CNTL6@GOTPAGE
Lloh17:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL6@GOTPAGEOFF]
Lloh18:
	ldr	w1, [x8]
	mov	w2, #3669
	bl	_regmap_write
Lloh19:
	adrp	x8, _HHI_HDMI_PLL_CNTL_EN@GOTPAGE
Lloh20:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL_EN@GOTPAGEOFF]
Lloh21:
	ldr	w3, [x8]
	mov	w2, #1879048192
	b	LBB0_5
LBB0_2:
Lloh22:
	adrp	x8, _VPU_COMPATIBLE_GXM@GOTPAGE
Lloh23:
	ldr	x8, [x8, _VPU_COMPATIBLE_GXM@GOTPAGEOFF]
Lloh24:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_meson_vpu_is_compatible
	cbnz	x0, LBB0_4
; %bb.3:
Lloh25:
	adrp	x8, _VPU_COMPATIBLE_GXL@GOTPAGE
Lloh26:
	ldr	x8, [x8, _VPU_COMPATIBLE_GXL@GOTPAGEOFF]
Lloh27:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_24
LBB0_4:
	ldr	w0, [x20]
	ldr	w1, [x27]
	mov	w8, #512
	movk	w8, #16384, lsl #16
	orr	w2, w24, w8
	bl	_regmap_write
	ldr	w0, [x20]
Lloh28:
	adrp	x8, _HHI_HDMI_PLL_CNTL2@GOTPAGE
Lloh29:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL2@GOTPAGEOFF]
Lloh30:
	ldr	w1, [x8]
	mov	w8, #45056
	movk	w8, #32780, lsl #16
	orr	w2, w23, w8
	bl	_regmap_write
	ldr	w0, [x20]
Lloh31:
	adrp	x8, _HHI_HDMI_PLL_CNTL3@GOTPAGE
Lloh32:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL3@GOTPAGEOFF]
Lloh33:
	ldr	w1, [x8]
	mov	w2, #12484
	movk	w2, #34319, lsl #16
	bl	_regmap_write
	ldr	w0, [x20]
Lloh34:
	adrp	x8, _HHI_HDMI_PLL_CNTL4@GOTPAGE
Lloh35:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL4@GOTPAGEOFF]
Lloh36:
	ldr	w1, [x8]
	mov	w2, #210632704
	bl	_regmap_write
	ldr	w0, [x20]
Lloh37:
	adrp	x8, _HHI_HDMI_PLL_CNTL5@GOTPAGE
Lloh38:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL5@GOTPAGEOFF]
Lloh39:
	ldr	w1, [x8]
	mov	w2, #42793
	movk	w2, #31, lsl #16
	bl	_regmap_write
	ldr	w0, [x20]
Lloh40:
	adrp	x8, _HHI_HDMI_PLL_CNTL6@GOTPAGE
Lloh41:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL6@GOTPAGEOFF]
Lloh42:
	ldr	w1, [x8]
	mov	w2, #5376
	movk	w2, #419, lsl #16
	bl	_regmap_write
	ldr	w0, [x20]
	ldr	w1, [x27]
Lloh43:
	adrp	x23, _HDMI_PLL_RESET@GOTPAGE
Lloh44:
	ldr	x23, [x23, _HDMI_PLL_RESET@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	x3, x2
	bl	_regmap_update_bits
	mov	w3, #0
	ldr	w2, [x23]
LBB0_5:
	ldr	w0, [x20]
	ldr	w1, [x27]
	bl	_regmap_update_bits
	ldr	w0, [x20]
	ldr	w1, [x27]
	mov	w3, #0
	mov	w4, #10
	mov	w5, #0
	bl	_regmap_read_poll_timeout
LBB0_6:
	ldr	w1, [x26]
	mov	x0, x20
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_8
; %bb.7:
	mov	w23, #196608
	mov	w27, #16
Lloh45:
	adrp	x8, _HHI_HDMI_PLL_CNTL2@GOTPAGE
Lloh46:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL2@GOTPAGEOFF]
	b	LBB0_11
LBB0_8:
Lloh47:
	adrp	x8, _VPU_COMPATIBLE_GXM@GOTPAGE
Lloh48:
	ldr	x8, [x8, _VPU_COMPATIBLE_GXM@GOTPAGEOFF]
Lloh49:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_meson_vpu_is_compatible
	cbnz	x0, LBB0_10
; %bb.9:
Lloh50:
	adrp	x8, _VPU_COMPATIBLE_GXL@GOTPAGE
Lloh51:
	ldr	x8, [x8, _VPU_COMPATIBLE_GXL@GOTPAGEOFF]
Lloh52:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_27
LBB0_10:
	mov	w23, #6291456
	mov	w27, #21
Lloh53:
	adrp	x8, _HHI_HDMI_PLL_CNTL3@GOTPAGE
Lloh54:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL3@GOTPAGEOFF]
LBB0_11:
	ldr	w24, [x20]
	ldr	w25, [x8]
	mov	x0, x22
	bl	_pll_od_to_reg
	lsl	w3, w0, w27
	mov	x0, x24
	mov	x1, x25
	mov	x2, x23
	bl	_regmap_update_bits
LBB0_12:
	ldr	w1, [x26]
	mov	x0, x20
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_14
; %bb.13:
	mov	w22, #12582912
	mov	w25, #22
Lloh55:
	adrp	x8, _HHI_HDMI_PLL_CNTL2@GOTPAGE
Lloh56:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL2@GOTPAGEOFF]
	b	LBB0_17
LBB0_14:
Lloh57:
	adrp	x8, _VPU_COMPATIBLE_GXM@GOTPAGE
Lloh58:
	ldr	x8, [x8, _VPU_COMPATIBLE_GXM@GOTPAGEOFF]
Lloh59:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_meson_vpu_is_compatible
	cbnz	x0, LBB0_16
; %bb.15:
Lloh60:
	adrp	x8, _VPU_COMPATIBLE_GXL@GOTPAGE
Lloh61:
	ldr	x8, [x8, _VPU_COMPATIBLE_GXL@GOTPAGEOFF]
Lloh62:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_29
LBB0_16:
	mov	w22, #25165824
	mov	w25, #23
Lloh63:
	adrp	x8, _HHI_HDMI_PLL_CNTL3@GOTPAGE
Lloh64:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL3@GOTPAGEOFF]
LBB0_17:
	ldr	w23, [x20]
	ldr	w24, [x8]
	mov	x0, x21
	bl	_pll_od_to_reg
	lsl	w3, w0, w25
	mov	x0, x23
	mov	x1, x24
	mov	x2, x22
	bl	_regmap_update_bits
LBB0_18:
	ldr	w1, [x26]
	mov	x0, x20
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_20
; %bb.19:
	mov	w21, #786432
	mov	w23, #18
Lloh65:
	adrp	x8, _HHI_HDMI_PLL_CNTL2@GOTPAGE
Lloh66:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL2@GOTPAGEOFF]
	b	LBB0_23
LBB0_20:
Lloh67:
	adrp	x8, _VPU_COMPATIBLE_GXM@GOTPAGE
Lloh68:
	ldr	x8, [x8, _VPU_COMPATIBLE_GXM@GOTPAGEOFF]
Lloh69:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_meson_vpu_is_compatible
	cbnz	x0, LBB0_22
; %bb.21:
Lloh70:
	adrp	x8, _VPU_COMPATIBLE_GXL@GOTPAGE
Lloh71:
	ldr	x8, [x8, _VPU_COMPATIBLE_GXL@GOTPAGEOFF]
Lloh72:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_31
LBB0_22:
	mov	w21, #1572864
	mov	w23, #19
Lloh73:
	adrp	x8, _HHI_HDMI_PLL_CNTL3@GOTPAGE
Lloh74:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL3@GOTPAGEOFF]
LBB0_23:
	ldr	w20, [x20]
	ldr	w22, [x8]
	mov	x0, x19
	bl	_pll_od_to_reg
	lsl	w3, w0, w23
	mov	x0, x20
	mov	x1, x22
	mov	x2, x21
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_regmap_update_bits
LBB0_24:
Lloh75:
	adrp	x8, _VPU_COMPATIBLE_G12A@GOTPAGE
Lloh76:
	ldr	x8, [x8, _VPU_COMPATIBLE_G12A@GOTPAGEOFF]
Lloh77:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_6
; %bb.25:
	ldr	w0, [x20]
	ldr	w1, [x27]
	mov	w8, #1024
	movk	w8, #2874, lsl #16
	orr	w2, w24, w8
	bl	_regmap_write
	ldr	w0, [x20]
	ldr	w1, [x27]
	mov	w2, #805306368
	mov	w3, #805306368
	bl	_regmap_update_bits
	ldr	w0, [x20]
Lloh78:
	adrp	x8, _HHI_HDMI_PLL_CNTL2@GOTPAGE
Lloh79:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL2@GOTPAGEOFF]
Lloh80:
	ldr	w1, [x8]
	mov	x2, x23
	bl	_regmap_write
	ldr	w0, [x20]
Lloh81:
	adrp	x8, _HHI_HDMI_PLL_CNTL3@GOTPAGE
Lloh82:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL3@GOTPAGEOFF]
Lloh83:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_regmap_write
	cmp	w24, #247
	b.lo	LBB0_34
; %bb.26:
	ldr	w0, [x20]
Lloh84:
	adrp	x8, _HHI_HDMI_PLL_CNTL4@GOTPAGE
Lloh85:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL4@GOTPAGEOFF]
Lloh86:
	ldr	w1, [x8]
	mov	w8, #56320
	movk	w8, #60008, lsl #16
	mov	w9, #23552
	movk	w9, #27240, lsl #16
	cmp	w23, #16, lsl #12               ; =65536
	csel	w2, w9, w8, lo
	mov	w8, #4752
	movk	w8, #25975, lsl #16
	mov	w9, #4755
	movk	w9, #4437, lsl #16
	csel	w25, w9, w8, lo
	bl	_regmap_write
	mov	w23, #1431568384
	mov	w24, #8192
	movk	w24, #14631, lsl #16
	b	LBB0_35
LBB0_27:
Lloh87:
	adrp	x8, _VPU_COMPATIBLE_G12A@GOTPAGE
Lloh88:
	ldr	x8, [x8, _VPU_COMPATIBLE_G12A@GOTPAGEOFF]
Lloh89:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_12
; %bb.28:
	mov	w23, #196608
	mov	w27, #16
Lloh90:
	adrp	x8, _HHI_HDMI_PLL_CNTL@GOTPAGE
Lloh91:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL@GOTPAGEOFF]
	b	LBB0_11
LBB0_29:
Lloh92:
	adrp	x8, _VPU_COMPATIBLE_G12A@GOTPAGE
Lloh93:
	ldr	x8, [x8, _VPU_COMPATIBLE_G12A@GOTPAGEOFF]
Lloh94:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_18
; %bb.30:
	mov	w22, #786432
	mov	w25, #18
Lloh95:
	adrp	x8, _HHI_HDMI_PLL_CNTL@GOTPAGE
Lloh96:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL@GOTPAGEOFF]
	b	LBB0_17
LBB0_31:
Lloh97:
	adrp	x8, _VPU_COMPATIBLE_G12A@GOTPAGE
Lloh98:
	ldr	x8, [x8, _VPU_COMPATIBLE_G12A@GOTPAGEOFF]
Lloh99:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_33
; %bb.32:
	mov	w21, #3145728
	mov	w23, #20
Lloh100:
	adrp	x8, _HHI_HDMI_PLL_CNTL@GOTPAGE
Lloh101:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL@GOTPAGEOFF]
	b	LBB0_23
LBB0_33:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
LBB0_34:
	ldr	w0, [x20]
Lloh102:
	adrp	x8, _HHI_HDMI_PLL_CNTL4@GOTPAGE
Lloh103:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL4@GOTPAGEOFF]
Lloh104:
	ldr	w1, [x8]
	mov	w2, #7168
	movk	w2, #2665, lsl #16
	bl	_regmap_write
	mov	w23, #1347682304
	mov	w24, #958857216
	mov	w25, #4752
	movk	w25, #13175, lsl #16
LBB0_35:
	ldr	w0, [x20]
Lloh105:
	adrp	x8, _HHI_HDMI_PLL_CNTL5@GOTPAGE
Lloh106:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL5@GOTPAGEOFF]
Lloh107:
	ldr	w1, [x8]
	mov	x2, x25
	bl	_regmap_write
	ldr	w0, [x20]
Lloh108:
	adrp	x8, _HHI_HDMI_PLL_CNTL6@GOTPAGE
Lloh109:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL6@GOTPAGEOFF]
Lloh110:
	ldr	w1, [x8]
	mov	x2, x24
	bl	_regmap_write
	ldr	w0, [x20]
Lloh111:
	adrp	x8, _HHI_HDMI_PLL_CNTL7@GOTPAGE
Lloh112:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL7@GOTPAGEOFF]
Lloh113:
	ldr	w1, [x8]
	mov	x2, x23
	bl	_regmap_write
Lloh114:
	adrp	x23, _HDMI_PLL_RESET_G12A@GOTPAGE
Lloh115:
	ldr	x23, [x23, _HDMI_PLL_RESET_G12A@GOTPAGEOFF]
Lloh116:
	adrp	x24, _HDMI_PLL_LOCK_G12A@GOTPAGE
Lloh117:
	ldr	x24, [x24, _HDMI_PLL_LOCK_G12A@GOTPAGEOFF]
LBB0_36:                                ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x20]
	ldr	w1, [x27]
	ldr	w2, [x23]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x20]
	ldr	w1, [x27]
	ldr	w2, [x23]
	mov	w3, #0
	bl	_regmap_update_bits
	ldr	w0, [x20]
	ldr	w1, [x27]
	ldr	w8, [x24]
	cmp	w8, #0
	cset	w3, eq
	mov	w4, #10
	mov	w5, #100
	bl	_regmap_read_poll_timeout
	cbnz	w0, LBB0_36
	b	LBB0_6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGot	Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGot	Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGot	Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGot	Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGot	Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGot	Lloh116, Lloh117
	.loh AdrpLdrGot	Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.cfi_endproc
                                        ; -- End function
	.comm	_VPU_COMPATIBLE_GXBB,4,2        ; @VPU_COMPATIBLE_GXBB
	.comm	_HHI_HDMI_PLL_CNTL,4,2          ; @HHI_HDMI_PLL_CNTL
	.comm	_HHI_HDMI_PLL_CNTL2,4,2         ; @HHI_HDMI_PLL_CNTL2
	.comm	_HHI_HDMI_PLL_CNTL3,4,2         ; @HHI_HDMI_PLL_CNTL3
	.comm	_HHI_HDMI_PLL_CNTL4,4,2         ; @HHI_HDMI_PLL_CNTL4
	.comm	_HHI_HDMI_PLL_CNTL5,4,2         ; @HHI_HDMI_PLL_CNTL5
	.comm	_HHI_HDMI_PLL_CNTL6,4,2         ; @HHI_HDMI_PLL_CNTL6
	.comm	_HHI_HDMI_PLL_CNTL_EN,4,2       ; @HHI_HDMI_PLL_CNTL_EN
	.comm	_HDMI_PLL_LOCK,4,2              ; @HDMI_PLL_LOCK
	.comm	_VPU_COMPATIBLE_GXM,4,2         ; @VPU_COMPATIBLE_GXM
	.comm	_VPU_COMPATIBLE_GXL,4,2         ; @VPU_COMPATIBLE_GXL
	.comm	_HDMI_PLL_RESET,4,2             ; @HDMI_PLL_RESET
	.comm	_VPU_COMPATIBLE_G12A,4,2        ; @VPU_COMPATIBLE_G12A
	.comm	_HHI_HDMI_PLL_CNTL7,4,2         ; @HHI_HDMI_PLL_CNTL7
	.comm	_HDMI_PLL_RESET_G12A,4,2        ; @HDMI_PLL_RESET_G12A
	.comm	_HDMI_PLL_LOCK_G12A,4,2         ; @HDMI_PLL_LOCK_G12A
.subsections_via_symbols
