	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v8_0_constants_init
_gfx_v8_0_constants_init:               ## @gfx_v8_0_constants_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_GRBM_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_READ_TIMEOUT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$255, %edx
	callq	_WREG32_FIELD
	movq	_mmGB_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	4(%r14), %esi
	callq	_WREG32
	movq	_mmHDP_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	4(%r14), %esi
	callq	_WREG32
	movq	_mmDMIF_ADDR_CALC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	4(%r14), %esi
	callq	_WREG32
	movq	%r14, %rdi
	callq	_gfx_v8_0_tiling_mode_table_init
	movq	%r14, %rdi
	callq	_gfx_v8_0_setup_rb
	movq	%r14, %rdi
	callq	_gfx_v8_0_get_cu_info
	movq	%r14, %rdi
	callq	_gfx_v8_0_config_init
	movq	_SH_STATIC_MEM_CONFIG@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_SWIZZLE_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r15), %esi
	movq	_ELEMENT_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r15), %esi
	movq	_INDEX_STRIDE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$3, %ecx
	callq	_REG_SET_FIELD
	movq	_mmSH_STATIC_MEM_CONFIG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%eax, %esi
	callq	_WREG32
	leaq	24(%r14), %rdi
	movq	%rdi, -48(%rbp)                 ## 8-byte Spill
	callq	_mutex_lock
	movq	32(%r14), %rax
	cmpl	$0, (%rax)
	jle	LBB0_5
## %bb.1:
	movq	_SH_MEM_CONFIG@GOTPCREL(%rip), %r12
	movq	_MTYPE_UC@GOTPCREL(%rip), %r15
	movq	_mmSH_MEM_APE1_LIMIT@GOTPCREL(%rip), %r13
	jmp	LBB0_2
	.p2align	4, 0x90
LBB0_4:                                 ##   in Loop: Header=BB0_2 Depth=1
	movl	(%r12), %esi
	movq	_DEFAULT_MTYPE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	(%rax), %ecx
	xorl	%edi, %edi
	callq	_REG_SET_FIELD
	movl	(%r12), %esi
	movq	_APE1_MTYPE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	(%r15), %ecx
	movl	%eax, %edi
	callq	_REG_SET_FIELD
	movl	(%r12), %esi
	movq	_ALIGNMENT_MODE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_SH_MEM_ALIGNMENT_MODE_UNALIGNED@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%eax, %edi
	callq	_REG_SET_FIELD
	movq	_mmSH_MEM_CONFIG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmSH_MEM_BASES@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmSH_MEM_APE1_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_WREG32
	movl	(%r13), %edi
	xorl	%esi, %esi
	callq	_WREG32
	incl	%ebx
	movq	32(%r14), %rax
	cmpl	(%rax), %ebx
	jge	LBB0_5
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	movl	%ebx, %r8d
	callq	_vi_srbm_select
	movq	%r15, %rax
	testl	%ebx, %ebx
	je	LBB0_4
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	_MTYPE_NC@GOTPCREL(%rip), %rax
	jmp	LBB0_4
LBB0_5:
	movq	%r14, %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	xorl	%r8d, %r8d
	callq	_vi_srbm_select
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_mutex_unlock
	movq	%r14, %rdi
	callq	_gfx_v8_0_init_compute_vmid
	movq	%r14, %rdi
	callq	_gfx_v8_0_init_gds_vmid
	movq	%r14, %rdi
	callq	_mutex_lock
	movq	%r14, %rdi
	movl	$-1, %esi
	movl	$-1, %edx
	movl	$-1, %ecx
	callq	_gfx_v8_0_select_se_sh
	movq	_PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	8(%r14), %eax
	movl	12(%r14), %edx
	shll	%cl, %eax
	movq	_PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	movl	16(%r14), %ebx
	movq	_PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %ebx
	movq	_mmPA_SC_FIFO_SIZE@GOTPCREL(%rip), %rdi
	movq	_PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	20(%r14), %esi
	shll	%cl, %esi
	movl	(%rdi), %edi
	orl	%eax, %edx
	orl	%ebx, %esi
	orl	%edx, %esi
	callq	_WREG32
	movq	_mmSPI_ARB_PRIORITY@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32
	movq	_SPI_ARB_PRIORITY@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_PIPE_ORDER_TS0@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$2, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_PIPE_ORDER_TS1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$2, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_PIPE_ORDER_TS2@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$2, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_PIPE_ORDER_TS3@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$2, %ecx
	callq	_REG_SET_FIELD
	movl	(%r15), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	%r14, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_mutex_unlock                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_GRBM_CNTL,4,2                  ## @GRBM_CNTL
	.comm	_READ_TIMEOUT,4,2               ## @READ_TIMEOUT
	.comm	_mmGB_ADDR_CONFIG,4,2           ## @mmGB_ADDR_CONFIG
	.comm	_mmHDP_ADDR_CONFIG,4,2          ## @mmHDP_ADDR_CONFIG
	.comm	_mmDMIF_ADDR_CALC,4,2           ## @mmDMIF_ADDR_CALC
	.comm	_SH_STATIC_MEM_CONFIG,4,2       ## @SH_STATIC_MEM_CONFIG
	.comm	_SWIZZLE_ENABLE,4,2             ## @SWIZZLE_ENABLE
	.comm	_ELEMENT_SIZE,4,2               ## @ELEMENT_SIZE
	.comm	_INDEX_STRIDE,4,2               ## @INDEX_STRIDE
	.comm	_mmSH_STATIC_MEM_CONFIG,4,2     ## @mmSH_STATIC_MEM_CONFIG
	.comm	_SH_MEM_CONFIG,4,2              ## @SH_MEM_CONFIG
	.comm	_DEFAULT_MTYPE,4,2              ## @DEFAULT_MTYPE
	.comm	_MTYPE_UC,4,2                   ## @MTYPE_UC
	.comm	_APE1_MTYPE,4,2                 ## @APE1_MTYPE
	.comm	_ALIGNMENT_MODE,4,2             ## @ALIGNMENT_MODE
	.comm	_SH_MEM_ALIGNMENT_MODE_UNALIGNED,4,2 ## @SH_MEM_ALIGNMENT_MODE_UNALIGNED
	.comm	_mmSH_MEM_CONFIG,4,2            ## @mmSH_MEM_CONFIG
	.comm	_mmSH_MEM_BASES,4,2             ## @mmSH_MEM_BASES
	.comm	_MTYPE_NC,4,2                   ## @MTYPE_NC
	.comm	_mmSH_MEM_APE1_BASE,4,2         ## @mmSH_MEM_APE1_BASE
	.comm	_mmSH_MEM_APE1_LIMIT,4,2        ## @mmSH_MEM_APE1_LIMIT
	.comm	_mmPA_SC_FIFO_SIZE,4,2          ## @mmPA_SC_FIFO_SIZE
	.comm	_PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT,4,2 ## @PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT
	.comm	_PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT,4,2 ## @PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT
	.comm	_PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT,4,2 ## @PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT
	.comm	_PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT,4,2 ## @PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT
	.comm	_mmSPI_ARB_PRIORITY,4,2         ## @mmSPI_ARB_PRIORITY
	.comm	_SPI_ARB_PRIORITY,4,2           ## @SPI_ARB_PRIORITY
	.comm	_PIPE_ORDER_TS0,4,2             ## @PIPE_ORDER_TS0
	.comm	_PIPE_ORDER_TS1,4,2             ## @PIPE_ORDER_TS1
	.comm	_PIPE_ORDER_TS2,4,2             ## @PIPE_ORDER_TS2
	.comm	_PIPE_ORDER_TS3,4,2             ## @PIPE_ORDER_TS3
	.no_dead_strip	_gfx_v8_0_constants_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v8_0_constants_init
_gfx_v8_0_constants_init:               ; @gfx_v8_0_constants_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
Lloh0:
	adrp	x8, _GRBM_CNTL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _GRBM_CNTL@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
Lloh3:
	adrp	x8, _READ_TIMEOUT@GOTPAGE
Lloh4:
	ldr	x8, [x8, _READ_TIMEOUT@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	w2, #255
	bl	_WREG32_FIELD
Lloh6:
	adrp	x8, _mmGB_ADDR_CONFIG@GOTPAGE
Lloh7:
	ldr	x8, [x8, _mmGB_ADDR_CONFIG@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	ldr	w1, [x19, #4]
	bl	_WREG32
Lloh9:
	adrp	x8, _mmHDP_ADDR_CONFIG@GOTPAGE
Lloh10:
	ldr	x8, [x8, _mmHDP_ADDR_CONFIG@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	ldr	w1, [x19, #4]
	bl	_WREG32
Lloh12:
	adrp	x8, _mmDMIF_ADDR_CALC@GOTPAGE
Lloh13:
	ldr	x8, [x8, _mmDMIF_ADDR_CALC@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	ldr	w1, [x19, #4]
	bl	_WREG32
	mov	x0, x19
	bl	_gfx_v8_0_tiling_mode_table_init
	mov	x0, x19
	bl	_gfx_v8_0_setup_rb
	mov	x0, x19
	bl	_gfx_v8_0_get_cu_info
	mov	x0, x19
	bl	_gfx_v8_0_config_init
Lloh15:
	adrp	x20, _SH_STATIC_MEM_CONFIG@GOTPAGE
Lloh16:
	ldr	x20, [x20, _SH_STATIC_MEM_CONFIG@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh17:
	adrp	x8, _SWIZZLE_ENABLE@GOTPAGE
Lloh18:
	ldr	x8, [x8, _SWIZZLE_ENABLE@GOTPAGEOFF]
Lloh19:
	ldr	w2, [x8]
	mov	w0, #0
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x20]
Lloh20:
	adrp	x8, _ELEMENT_SIZE@GOTPAGE
Lloh21:
	ldr	x8, [x8, _ELEMENT_SIZE@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x20]
Lloh23:
	adrp	x8, _INDEX_STRIDE@GOTPAGE
Lloh24:
	ldr	x8, [x8, _INDEX_STRIDE@GOTPAGEOFF]
Lloh25:
	ldr	w2, [x8]
	mov	w3, #3
	bl	_REG_SET_FIELD
	mov	x1, x0
Lloh26:
	adrp	x8, _mmSH_STATIC_MEM_CONFIG@GOTPAGE
Lloh27:
	ldr	x8, [x8, _mmSH_STATIC_MEM_CONFIG@GOTPAGEOFF]
Lloh28:
	ldr	w0, [x8]
	bl	_WREG32
	add	x0, x19, #24
	str	x0, [sp, #8]                    ; 8-byte Folded Spill
	bl	_mutex_lock
	ldr	x8, [x19, #32]
	ldr	w8, [x8]
	cmp	w8, #1
	b.lt	LBB0_3
; %bb.1:
	mov	w21, #0
Lloh29:
	adrp	x22, _SH_MEM_CONFIG@GOTPAGE
Lloh30:
	ldr	x22, [x22, _SH_MEM_CONFIG@GOTPAGEOFF]
Lloh31:
	adrp	x24, _MTYPE_UC@GOTPAGE
Lloh32:
	ldr	x24, [x24, _MTYPE_UC@GOTPAGEOFF]
Lloh33:
	adrp	x27, _ALIGNMENT_MODE@GOTPAGE
Lloh34:
	ldr	x27, [x27, _ALIGNMENT_MODE@GOTPAGEOFF]
Lloh35:
	adrp	x28, _SH_MEM_ALIGNMENT_MODE_UNALIGNED@GOTPAGE
Lloh36:
	ldr	x28, [x28, _SH_MEM_ALIGNMENT_MODE_UNALIGNED@GOTPAGEOFF]
Lloh37:
	adrp	x20, _mmSH_MEM_CONFIG@GOTPAGE
Lloh38:
	ldr	x20, [x20, _mmSH_MEM_CONFIG@GOTPAGEOFF]
Lloh39:
	adrp	x23, _mmSH_MEM_BASES@GOTPAGE
Lloh40:
	ldr	x23, [x23, _mmSH_MEM_BASES@GOTPAGEOFF]
Lloh41:
	adrp	x25, _mmSH_MEM_APE1_BASE@GOTPAGE
Lloh42:
	ldr	x25, [x25, _mmSH_MEM_APE1_BASE@GOTPAGEOFF]
Lloh43:
	adrp	x26, _mmSH_MEM_APE1_LIMIT@GOTPAGE
Lloh44:
	ldr	x26, [x26, _mmSH_MEM_APE1_LIMIT@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x19
	mov	w1, #0
	mov	w2, #0
	mov	w3, #0
	mov	x4, x21
	bl	_vi_srbm_select
	ldr	w1, [x22]
Lloh45:
	adrp	x8, _DEFAULT_MTYPE@GOTPAGE
Lloh46:
	ldr	x8, [x8, _DEFAULT_MTYPE@GOTPAGEOFF]
Lloh47:
	ldr	w2, [x8]
	cmp	w21, #0
Lloh48:
	adrp	x8, _MTYPE_NC@GOTPAGE
Lloh49:
	ldr	x8, [x8, _MTYPE_NC@GOTPAGEOFF]
	csel	x8, x24, x8, eq
	ldr	w3, [x8]
	mov	w0, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x22]
Lloh50:
	adrp	x8, _APE1_MTYPE@GOTPAGE
Lloh51:
	ldr	x8, [x8, _APE1_MTYPE@GOTPAGEOFF]
Lloh52:
	ldr	w2, [x8]
	ldr	w3, [x24]
	bl	_REG_SET_FIELD
	ldr	w1, [x22]
	ldr	w2, [x27]
	ldr	w3, [x28]
	bl	_REG_SET_FIELD
	mov	x1, x0
	ldr	w0, [x20]
	bl	_WREG32
	ldr	w0, [x23]
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x25]
	mov	w1, #1
	bl	_WREG32
	ldr	w0, [x26]
	mov	w1, #0
	bl	_WREG32
	add	w21, w21, #1
	ldr	x8, [x19, #32]
	ldr	w8, [x8]
	cmp	w21, w8
	b.lt	LBB0_2
LBB0_3:
	mov	x0, x19
	mov	w1, #0
	mov	w2, #0
	mov	w3, #0
	mov	w4, #0
	bl	_vi_srbm_select
	ldr	x0, [sp, #8]                    ; 8-byte Folded Reload
	bl	_mutex_unlock
	mov	x0, x19
	bl	_gfx_v8_0_init_compute_vmid
	mov	x0, x19
	bl	_gfx_v8_0_init_gds_vmid
	mov	x0, x19
	bl	_mutex_lock
	mov	x0, x19
	mov	w1, #-1
	mov	w2, #-1
	mov	w3, #-1
	bl	_gfx_v8_0_select_se_sh
Lloh53:
	adrp	x8, _PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT@GOTPAGE
Lloh54:
	ldr	x8, [x8, _PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT@GOTPAGEOFF]
Lloh55:
	ldr	w8, [x8]
	ldp	w9, w10, [x19, #8]
	lsl	w8, w9, w8
Lloh56:
	adrp	x9, _PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT@GOTPAGE
Lloh57:
	ldr	x9, [x9, _PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT@GOTPAGEOFF]
Lloh58:
	ldr	w9, [x9]
	lsl	w9, w10, w9
	orr	w8, w9, w8
Lloh59:
	adrp	x9, _PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT@GOTPAGE
Lloh60:
	ldr	x9, [x9, _PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT@GOTPAGEOFF]
Lloh61:
	ldr	w9, [x9]
	ldp	w10, w11, [x19, #16]
	lsl	w9, w10, w9
Lloh62:
	adrp	x10, _mmPA_SC_FIFO_SIZE@GOTPAGE
Lloh63:
	ldr	x10, [x10, _mmPA_SC_FIFO_SIZE@GOTPAGEOFF]
Lloh64:
	ldr	w0, [x10]
	orr	w8, w8, w9
Lloh65:
	adrp	x9, _PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT@GOTPAGE
Lloh66:
	ldr	x9, [x9, _PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT@GOTPAGEOFF]
Lloh67:
	ldr	w9, [x9]
	lsl	w9, w11, w9
	orr	w1, w8, w9
	bl	_WREG32
Lloh68:
	adrp	x20, _mmSPI_ARB_PRIORITY@GOTPAGE
Lloh69:
	ldr	x20, [x20, _mmSPI_ARB_PRIORITY@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh70:
	adrp	x21, _SPI_ARB_PRIORITY@GOTPAGE
Lloh71:
	ldr	x21, [x21, _SPI_ARB_PRIORITY@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh72:
	adrp	x8, _PIPE_ORDER_TS0@GOTPAGE
Lloh73:
	ldr	x8, [x8, _PIPE_ORDER_TS0@GOTPAGEOFF]
Lloh74:
	ldr	w2, [x8]
	mov	w3, #2
	bl	_REG_SET_FIELD
	ldr	w1, [x21]
Lloh75:
	adrp	x8, _PIPE_ORDER_TS1@GOTPAGE
Lloh76:
	ldr	x8, [x8, _PIPE_ORDER_TS1@GOTPAGEOFF]
Lloh77:
	ldr	w2, [x8]
	mov	w3, #2
	bl	_REG_SET_FIELD
	ldr	w1, [x21]
Lloh78:
	adrp	x8, _PIPE_ORDER_TS2@GOTPAGE
Lloh79:
	ldr	x8, [x8, _PIPE_ORDER_TS2@GOTPAGEOFF]
Lloh80:
	ldr	w2, [x8]
	mov	w3, #2
	bl	_REG_SET_FIELD
	ldr	w1, [x21]
Lloh81:
	adrp	x8, _PIPE_ORDER_TS3@GOTPAGE
Lloh82:
	ldr	x8, [x8, _PIPE_ORDER_TS3@GOTPAGEOFF]
Lloh83:
	ldr	w2, [x8]
	mov	w3, #2
	bl	_REG_SET_FIELD
	mov	x1, x0
	ldr	w0, [x20]
	bl	_WREG32
	mov	x0, x19
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	b	_mutex_unlock
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGot	Lloh70, Lloh71
	.loh AdrpLdrGot	Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.cfi_endproc
                                        ; -- End function
	.comm	_GRBM_CNTL,4,2                  ; @GRBM_CNTL
	.comm	_READ_TIMEOUT,4,2               ; @READ_TIMEOUT
	.comm	_mmGB_ADDR_CONFIG,4,2           ; @mmGB_ADDR_CONFIG
	.comm	_mmHDP_ADDR_CONFIG,4,2          ; @mmHDP_ADDR_CONFIG
	.comm	_mmDMIF_ADDR_CALC,4,2           ; @mmDMIF_ADDR_CALC
	.comm	_SH_STATIC_MEM_CONFIG,4,2       ; @SH_STATIC_MEM_CONFIG
	.comm	_SWIZZLE_ENABLE,4,2             ; @SWIZZLE_ENABLE
	.comm	_ELEMENT_SIZE,4,2               ; @ELEMENT_SIZE
	.comm	_INDEX_STRIDE,4,2               ; @INDEX_STRIDE
	.comm	_mmSH_STATIC_MEM_CONFIG,4,2     ; @mmSH_STATIC_MEM_CONFIG
	.comm	_SH_MEM_CONFIG,4,2              ; @SH_MEM_CONFIG
	.comm	_DEFAULT_MTYPE,4,2              ; @DEFAULT_MTYPE
	.comm	_MTYPE_UC,4,2                   ; @MTYPE_UC
	.comm	_APE1_MTYPE,4,2                 ; @APE1_MTYPE
	.comm	_ALIGNMENT_MODE,4,2             ; @ALIGNMENT_MODE
	.comm	_SH_MEM_ALIGNMENT_MODE_UNALIGNED,4,2 ; @SH_MEM_ALIGNMENT_MODE_UNALIGNED
	.comm	_mmSH_MEM_CONFIG,4,2            ; @mmSH_MEM_CONFIG
	.comm	_mmSH_MEM_BASES,4,2             ; @mmSH_MEM_BASES
	.comm	_MTYPE_NC,4,2                   ; @MTYPE_NC
	.comm	_mmSH_MEM_APE1_BASE,4,2         ; @mmSH_MEM_APE1_BASE
	.comm	_mmSH_MEM_APE1_LIMIT,4,2        ; @mmSH_MEM_APE1_LIMIT
	.comm	_mmPA_SC_FIFO_SIZE,4,2          ; @mmPA_SC_FIFO_SIZE
	.comm	_PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT,4,2 ; @PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT
	.comm	_PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT,4,2 ; @PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT
	.comm	_PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT,4,2 ; @PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT
	.comm	_PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT,4,2 ; @PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT
	.comm	_mmSPI_ARB_PRIORITY,4,2         ; @mmSPI_ARB_PRIORITY
	.comm	_SPI_ARB_PRIORITY,4,2           ; @SPI_ARB_PRIORITY
	.comm	_PIPE_ORDER_TS0,4,2             ; @PIPE_ORDER_TS0
	.comm	_PIPE_ORDER_TS1,4,2             ; @PIPE_ORDER_TS1
	.comm	_PIPE_ORDER_TS2,4,2             ; @PIPE_ORDER_TS2
	.comm	_PIPE_ORDER_TS3,4,2             ; @PIPE_ORDER_TS3
	.no_dead_strip	_gfx_v8_0_constants_init
.subsections_via_symbols
