	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function pp_dpm_en_umd_pstate
_pp_dpm_en_umd_pstate:                  ## @pp_dpm_en_umd_pstate
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD@GOTPCREL(%rip), %rcx
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	(%rcx), %eax
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	%rdi, %rbx
	movl	(%rdi), %ecx
	movl	(%rsi), %edx
	testl	%eax, %ecx
	je	LBB0_1
## %bb.3:
	testl	%eax, %edx
	jne	LBB0_7
## %bb.4:
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_EXIT@GOTPCREL(%rip), %rdi
	movq	_AMD_PG_STATE_GATE@GOTPCREL(%rip), %r14
	movq	_AMD_CG_STATE_GATE@GOTPCREL(%rip), %rax
	xorl	%ecx, %ecx
	cmpl	(%rdi), %edx
	jne	LBB0_6
## %bb.5:
	movl	4(%rbx), %edx
	movl	%edx, (%rsi)
	jmp	LBB0_6
LBB0_1:
	testl	%eax, %edx
	je	LBB0_7
## %bb.2:
	movl	%ecx, 4(%rbx)
	movq	_AMD_PG_STATE_UNGATE@GOTPCREL(%rip), %r14
	movq	_AMD_CG_STATE_UNGATE@GOTPCREL(%rip), %rax
	movl	$1, %ecx
LBB0_6:
	movl	%ecx, 8(%rbx)
	movl	12(%rbx), %edi
	movq	_AMD_IP_BLOCK_TYPE_GFX@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movl	(%rax), %edx
	callq	_amdgpu_device_ip_set_clockgating_state
	movl	12(%rbx), %edi
	movl	(%r15), %esi
	movl	(%r14), %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_device_ip_set_powergating_state ## TAILCALL
LBB0_7:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD,4,2 ## @AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK,4,2 ## @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK,4,2 ## @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,4,2 ## @AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
	.comm	_AMD_IP_BLOCK_TYPE_GFX,4,2      ## @AMD_IP_BLOCK_TYPE_GFX
	.comm	_AMD_CG_STATE_UNGATE,4,2        ## @AMD_CG_STATE_UNGATE
	.comm	_AMD_PG_STATE_UNGATE,4,2        ## @AMD_PG_STATE_UNGATE
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_EXIT,4,2 ## @AMD_DPM_FORCED_LEVEL_PROFILE_EXIT
	.comm	_AMD_CG_STATE_GATE,4,2          ## @AMD_CG_STATE_GATE
	.comm	_AMD_PG_STATE_GATE,4,2          ## @AMD_PG_STATE_GATE
	.no_dead_strip	_pp_dpm_en_umd_pstate
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function pp_dpm_en_umd_pstate
_pp_dpm_en_umd_pstate:                  ; @pp_dpm_en_umd_pstate
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, _AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK@GOTPAGE
Lloh4:
	ldr	x9, [x9, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh6:
	adrp	x9, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK@GOTPAGE
Lloh7:
	ldr	x9, [x9, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh9:
	adrp	x9, _AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPAGE
Lloh10:
	ldr	x9, [x9, _AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	orr	w11, w8, w9
	ldr	w8, [x0]
	ldr	w9, [x1]
	and	w10, w9, w11
	tst	w8, w11
	b.eq	LBB0_4
; %bb.1:
	cbnz	w10, LBB0_6
; %bb.2:
Lloh12:
	adrp	x8, _AMD_DPM_FORCED_LEVEL_PROFILE_EXIT@GOTPAGE
Lloh13:
	ldr	x8, [x8, _AMD_DPM_FORCED_LEVEL_PROFILE_EXIT@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	cmp	w9, w8
	b.ne	LBB0_7
; %bb.3:
	mov	w8, #0
	ldr	w9, [x19, #4]
	str	w9, [x1]
	b	LBB0_8
LBB0_4:
	cbz	w10, LBB0_6
; %bb.5:
	str	w8, [x19, #4]
Lloh15:
	adrp	x20, _AMD_PG_STATE_UNGATE@GOTPAGE
Lloh16:
	ldr	x20, [x20, _AMD_PG_STATE_UNGATE@GOTPAGEOFF]
	mov	w8, #1
Lloh17:
	adrp	x9, _AMD_CG_STATE_UNGATE@GOTPAGE
Lloh18:
	ldr	x9, [x9, _AMD_CG_STATE_UNGATE@GOTPAGEOFF]
	b	LBB0_9
LBB0_6:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_7:
	mov	w8, #0
LBB0_8:
Lloh19:
	adrp	x20, _AMD_PG_STATE_GATE@GOTPAGE
Lloh20:
	ldr	x20, [x20, _AMD_PG_STATE_GATE@GOTPAGEOFF]
Lloh21:
	adrp	x9, _AMD_CG_STATE_GATE@GOTPAGE
Lloh22:
	ldr	x9, [x9, _AMD_CG_STATE_GATE@GOTPAGEOFF]
LBB0_9:
	str	w8, [x19, #8]
	ldr	w0, [x19, #12]
Lloh23:
	adrp	x21, _AMD_IP_BLOCK_TYPE_GFX@GOTPAGE
Lloh24:
	ldr	x21, [x21, _AMD_IP_BLOCK_TYPE_GFX@GOTPAGEOFF]
	ldr	w1, [x21]
	ldr	w2, [x9]
	bl	_amdgpu_device_ip_set_clockgating_state
	ldr	w0, [x19, #12]
	ldr	w1, [x21]
	ldr	w2, [x20]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_amdgpu_device_ip_set_powergating_state
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh23, Lloh24
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD,4,2 ; @AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK,4,2 ; @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK,4,2 ; @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,4,2 ; @AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
	.comm	_AMD_IP_BLOCK_TYPE_GFX,4,2      ; @AMD_IP_BLOCK_TYPE_GFX
	.comm	_AMD_CG_STATE_UNGATE,4,2        ; @AMD_CG_STATE_UNGATE
	.comm	_AMD_PG_STATE_UNGATE,4,2        ; @AMD_PG_STATE_UNGATE
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_EXIT,4,2 ; @AMD_DPM_FORCED_LEVEL_PROFILE_EXIT
	.comm	_AMD_CG_STATE_GATE,4,2          ; @AMD_CG_STATE_GATE
	.comm	_AMD_PG_STATE_GATE,4,2          ; @AMD_PG_STATE_GATE
	.no_dead_strip	_pp_dpm_en_umd_pstate
.subsections_via_symbols
