	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vega10_enable_psm_gc_didt_config
_vega10_enable_psm_gc_didt_config:      ## @vega10_enable_psm_gc_didt_config
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	(%rdi), %rbx
	movl	4(%rbx), %r14d
	movq	%rbx, %rdi
	callq	_amdgpu_gfx_rlc_enter_safe_mode
	movq	%rbx, -56(%rbp)                 ## 8-byte Spill
	movq	%rbx, %rdi
	callq	_mutex_lock
	movl	%r14d, -44(%rbp)                ## 4-byte Spill
	testl	%r14d, %r14d
	jle	LBB0_4
## %bb.1:
	decl	-44(%rbp)                       ## 4-byte Folded Spill
	xorl	%r14d, %r14d
	movq	_VEGA10_CONFIGREG_DIDT@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	_GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_GRBM_GFX_INDEX__SE_INDEX__SHIFT@GOTPCREL(%rip), %rax
	movzbl	(%rax), %ecx
	movl	%r14d, %eax
	shll	%cl, %eax
	orl	%edx, %eax
	movq	_GC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movq	_mmGRBM_GFX_INDEX@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	_SEDiDtStallCtrlConfig_vega10@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r13), %edx
	movq	%r15, %rdi
	callq	_vega10_program_didt_config_registers
	movl	%eax, %r12d
	movq	_SEDiDtStallPatternConfig_vega10@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r13), %edx
	movq	%r15, %rdi
	callq	_vega10_program_didt_config_registers
	movl	%eax, %ebx
	orl	%r12d, %ebx
	movq	_SEDiDtCtrl3Config_vega10@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r13), %edx
	movq	%r15, %rdi
	callq	_vega10_program_didt_config_registers
	movl	%eax, %r12d
	orl	%ebx, %r12d
	movq	_SEDiDtCtrl0Config_Vega10@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r13), %edx
	movq	%r15, %rdi
	callq	_vega10_program_didt_config_registers
	orl	%r12d, %eax
	jne	LBB0_4
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	leal	1(%r14), %eax
	cmpl	%r14d, -44(%rbp)                ## 4-byte Folded Reload
	movl	%eax, %r14d
	jne	LBB0_2
LBB0_4:
	movq	_GC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmGRBM_GFX_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	movl	$-536870912, %ecx               ## imm = 0xE0000000
	callq	_WREG32_SOC15
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	callq	_mutex_unlock
	movq	%r15, %rdi
	movl	$1, %esi
	callq	_vega10_didt_set_mask
	movq	%rbx, %rdi
	callq	_amdgpu_gfx_rlc_exit_safe_mode
	movq	_GCDiDtDroopCtrlConfig_vega10@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_vega10_program_gc_didt_config_registers
	movq	_PHM_PlatformCaps_GCEDC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_PP_CAP
	testq	%rax, %rax
	je	LBB0_6
## %bb.5:
	movq	_GCDiDtCtrl0Config_vega10@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_vega10_program_gc_didt_config_registers
LBB0_6:
	movq	_PHM_PlatformCaps_PSM@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_PP_CAP
	testq	%rax, %rax
	je	LBB0_8
## %bb.7:
	movq	_AvfsPSMInitConfig_vega10@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_vega10_program_gc_didt_config_registers
LBB0_8:
	xorl	%eax, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK,4,2 ## @GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK
	.comm	_GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK,4,2 ## @GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK
	.comm	_GRBM_GFX_INDEX__SE_INDEX__SHIFT,4,2 ## @GRBM_GFX_INDEX__SE_INDEX__SHIFT
	.comm	_GC,4,2                         ## @GC
	.comm	_mmGRBM_GFX_INDEX,4,2           ## @mmGRBM_GFX_INDEX
	.comm	_SEDiDtStallCtrlConfig_vega10,4,2 ## @SEDiDtStallCtrlConfig_vega10
	.comm	_VEGA10_CONFIGREG_DIDT,4,2      ## @VEGA10_CONFIGREG_DIDT
	.comm	_SEDiDtStallPatternConfig_vega10,4,2 ## @SEDiDtStallPatternConfig_vega10
	.comm	_SEDiDtCtrl3Config_vega10,4,2   ## @SEDiDtCtrl3Config_vega10
	.comm	_SEDiDtCtrl0Config_Vega10,4,2   ## @SEDiDtCtrl0Config_Vega10
	.comm	_GCDiDtDroopCtrlConfig_vega10,4,2 ## @GCDiDtDroopCtrlConfig_vega10
	.comm	_PHM_PlatformCaps_GCEDC,4,2     ## @PHM_PlatformCaps_GCEDC
	.comm	_GCDiDtCtrl0Config_vega10,4,2   ## @GCDiDtCtrl0Config_vega10
	.comm	_PHM_PlatformCaps_PSM,4,2       ## @PHM_PlatformCaps_PSM
	.comm	_AvfsPSMInitConfig_vega10,4,2   ## @AvfsPSMInitConfig_vega10
	.no_dead_strip	_vega10_enable_psm_gc_didt_config
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vega10_enable_psm_gc_didt_config
_vega10_enable_psm_gc_didt_config:      ; @vega10_enable_psm_gc_didt_config
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	x21, [x0]
	ldr	w20, [x21, #4]
	mov	x0, x21
	bl	_amdgpu_gfx_rlc_enter_safe_mode
	str	x21, [sp, #8]                   ; 8-byte Folded Spill
	mov	x0, x21
	bl	_mutex_lock
Lloh0:
	adrp	x28, _GC@GOTPAGE
Lloh1:
	ldr	x28, [x28, _GC@GOTPAGEOFF]
Lloh2:
	adrp	x11, _mmGRBM_GFX_INDEX@GOTPAGE
Lloh3:
	ldr	x11, [x11, _mmGRBM_GFX_INDEX@GOTPAGEOFF]
	subs	w24, w20, #1
	b.lt	LBB0_3
; %bb.1:
	mov	w25, #0
Lloh4:
	adrp	x22, _VEGA10_CONFIGREG_DIDT@GOTPAGE
Lloh5:
	ldr	x22, [x22, _VEGA10_CONFIGREG_DIDT@GOTPAGEOFF]
Lloh6:
	adrp	x23, _SEDiDtStallPatternConfig_vega10@GOTPAGE
Lloh7:
	ldr	x23, [x23, _SEDiDtStallPatternConfig_vega10@GOTPAGEOFF]
Lloh8:
	adrp	x26, _SEDiDtCtrl3Config_vega10@GOTPAGE
Lloh9:
	ldr	x26, [x26, _SEDiDtCtrl3Config_vega10@GOTPAGEOFF]
Lloh10:
	adrp	x27, _SEDiDtCtrl0Config_Vega10@GOTPAGE
Lloh11:
	ldr	x27, [x27, _SEDiDtCtrl0Config_Vega10@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
Lloh12:
	adrp	x8, _GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK@GOTPAGE
Lloh13:
	ldr	x8, [x8, _GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
Lloh15:
	adrp	x9, _GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK@GOTPAGE
Lloh16:
	ldr	x9, [x9, _GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh18:
	adrp	x9, _GRBM_GFX_INDEX__SE_INDEX__SHIFT@GOTPAGE
Lloh19:
	ldr	x9, [x9, _GRBM_GFX_INDEX__SE_INDEX__SHIFT@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	lsl	w9, w25, w9
	orr	w3, w8, w9
	ldr	w0, [x28]
	ldr	w2, [x11]
	mov	w1, #0
	mov	x20, x11
	bl	_WREG32_SOC15
Lloh21:
	adrp	x8, _SEDiDtStallCtrlConfig_vega10@GOTPAGE
Lloh22:
	ldr	x8, [x8, _SEDiDtStallCtrlConfig_vega10@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	ldr	w2, [x22]
	mov	x0, x19
	bl	_vega10_program_didt_config_registers
	mov	x21, x0
	ldr	w1, [x23]
	ldr	w2, [x22]
	mov	x0, x19
	bl	_vega10_program_didt_config_registers
	orr	w21, w0, w21
	ldr	w1, [x26]
	ldr	w2, [x22]
	mov	x0, x19
	bl	_vega10_program_didt_config_registers
	orr	w21, w21, w0
	ldr	w1, [x27]
	ldr	w2, [x22]
	mov	x0, x19
	bl	_vega10_program_didt_config_registers
	mov	x11, x20
	orr	w8, w21, w0
	cmp	w8, #0
	ccmp	w24, w25, #4, eq
	add	w25, w25, #1
	b.ne	LBB0_2
LBB0_3:
	ldr	w0, [x28]
	ldr	w2, [x11]
	mov	w1, #0
	mov	w3, #-536870912
	bl	_WREG32_SOC15
	ldr	x20, [sp, #8]                   ; 8-byte Folded Reload
	mov	x0, x20
	bl	_mutex_unlock
	mov	x0, x19
	mov	w1, #1
	bl	_vega10_didt_set_mask
	mov	x0, x20
	bl	_amdgpu_gfx_rlc_exit_safe_mode
Lloh24:
	adrp	x8, _GCDiDtDroopCtrlConfig_vega10@GOTPAGE
Lloh25:
	ldr	x8, [x8, _GCDiDtDroopCtrlConfig_vega10@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_vega10_program_gc_didt_config_registers
Lloh27:
	adrp	x8, _PHM_PlatformCaps_GCEDC@GOTPAGE
Lloh28:
	ldr	x8, [x8, _PHM_PlatformCaps_GCEDC@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	bl	_PP_CAP
	cbz	x0, LBB0_5
; %bb.4:
Lloh30:
	adrp	x8, _GCDiDtCtrl0Config_vega10@GOTPAGE
Lloh31:
	ldr	x8, [x8, _GCDiDtCtrl0Config_vega10@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_vega10_program_gc_didt_config_registers
LBB0_5:
Lloh33:
	adrp	x8, _PHM_PlatformCaps_PSM@GOTPAGE
Lloh34:
	ldr	x8, [x8, _PHM_PlatformCaps_PSM@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	bl	_PP_CAP
	cbz	x0, LBB0_7
; %bb.6:
Lloh36:
	adrp	x8, _AvfsPSMInitConfig_vega10@GOTPAGE
Lloh37:
	ldr	x8, [x8, _AvfsPSMInitConfig_vega10@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_vega10_program_gc_didt_config_registers
LBB0_7:
	mov	w0, #0
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.cfi_endproc
                                        ; -- End function
	.comm	_GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK,4,2 ; @GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK
	.comm	_GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK,4,2 ; @GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK
	.comm	_GRBM_GFX_INDEX__SE_INDEX__SHIFT,4,2 ; @GRBM_GFX_INDEX__SE_INDEX__SHIFT
	.comm	_GC,4,2                         ; @GC
	.comm	_mmGRBM_GFX_INDEX,4,2           ; @mmGRBM_GFX_INDEX
	.comm	_SEDiDtStallCtrlConfig_vega10,4,2 ; @SEDiDtStallCtrlConfig_vega10
	.comm	_VEGA10_CONFIGREG_DIDT,4,2      ; @VEGA10_CONFIGREG_DIDT
	.comm	_SEDiDtStallPatternConfig_vega10,4,2 ; @SEDiDtStallPatternConfig_vega10
	.comm	_SEDiDtCtrl3Config_vega10,4,2   ; @SEDiDtCtrl3Config_vega10
	.comm	_SEDiDtCtrl0Config_Vega10,4,2   ; @SEDiDtCtrl0Config_Vega10
	.comm	_GCDiDtDroopCtrlConfig_vega10,4,2 ; @GCDiDtDroopCtrlConfig_vega10
	.comm	_PHM_PlatformCaps_GCEDC,4,2     ; @PHM_PlatformCaps_GCEDC
	.comm	_GCDiDtCtrl0Config_vega10,4,2   ; @GCDiDtCtrl0Config_vega10
	.comm	_PHM_PlatformCaps_PSM,4,2       ; @PHM_PlatformCaps_PSM
	.comm	_AvfsPSMInitConfig_vega10,4,2   ; @AvfsPSMInitConfig_vega10
	.no_dead_strip	_vega10_enable_psm_gc_didt_config
.subsections_via_symbols
