	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v6_0_enable_cp_pg
_gfx_v6_0_enable_cp_pg:                 ## @gfx_v6_0_enable_cp_pg
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %ebx
	movq	%rdi, %r14
	movq	_mmRLC_PG_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_RREG32
	testl	%ebx, %ebx
	je	LBB0_3
## %bb.1:
	movq	_AMD_PG_SUPPORT_CP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, (%r14)
	je	LBB0_3
## %bb.2:
	movl	%eax, %esi
	andl	$-32769, %esi                   ## imm = 0xFFFF7FFF
	cmpl	%esi, %eax
	je	LBB0_5
LBB0_6:
	movl	(%r15), %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
LBB0_3:
	movl	%eax, %esi
	orl	$32768, %esi                    ## imm = 0x8000
	cmpl	%esi, %eax
	jne	LBB0_6
LBB0_5:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_mmRLC_PG_CNTL,4,2              ## @mmRLC_PG_CNTL
	.comm	_AMD_PG_SUPPORT_CP,4,2          ## @AMD_PG_SUPPORT_CP
	.no_dead_strip	_gfx_v6_0_enable_cp_pg
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v6_0_enable_cp_pg
_gfx_v6_0_enable_cp_pg:                 ; @gfx_v6_0_enable_cp_pg
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x21, _mmRLC_PG_CNTL@GOTPAGE
Lloh1:
	ldr	x21, [x21, _mmRLC_PG_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
	cbz	w20, LBB0_4
; %bb.1:
	ldr	w8, [x19]
Lloh2:
	adrp	x9, _AMD_PG_SUPPORT_CP@GOTPAGE
Lloh3:
	ldr	x9, [x9, _AMD_PG_SUPPORT_CP@GOTPAGEOFF]
Lloh4:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_4
; %bb.2:
	and	w1, w0, #0xffff7fff
	cmp	w0, w1
	b.eq	LBB0_5
LBB0_3:
	ldr	w0, [x21]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32
LBB0_4:
	orr	w1, w0, #0x8000
	cmp	w0, w1
	b.ne	LBB0_3
LBB0_5:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_mmRLC_PG_CNTL,4,2              ; @mmRLC_PG_CNTL
	.comm	_AMD_PG_SUPPORT_CP,4,2          ; @AMD_PG_SUPPORT_CP
	.no_dead_strip	_gfx_v6_0_enable_cp_pg
.subsections_via_symbols
