	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function hsw_ddi_clock_get
_hsw_ddi_clock_get:                     ## @hsw_ddi_clock_get
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movl	(%rdi), %edi
	callq	_to_i915
	movq	%rax, %r15
	movl	4(%r14), %edi
	callq	_hsw_pll_to_ddi_pll_sel
                                        ## kill: def $eax killed $eax def $rax
	movq	_PORT_CLK_SEL_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	addl	$-128, %eax
	cmpl	$5, %eax
	ja	LBB0_11
## %bb.1:
	movl	$81000, %ebx                    ## imm = 0x13C68
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_5:
	movl	$1, %edi
	jmp	LBB0_4
LBB0_3:
	xorl	%edi, %edi
LBB0_4:
	callq	_WRPLL_CTL
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_hsw_ddi_calc_wrpll_link
	movl	%eax, %ebx
	jmp	LBB0_13
LBB0_2:
	movl	$270000, %ebx                   ## imm = 0x41EB0
	jmp	LBB0_13
LBB0_11:
	leaq	L_.str.1(%rip), %rsi
LBB0_10:
	movl	$1, %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WARN                           ## TAILCALL
LBB0_6:
	movq	_SPLL_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	_SPLL_FREQ_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_SPLL_FREQ_810MHz@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_13
## %bb.7:
	movq	_SPLL_FREQ_1350MHz@GOTPCREL(%rip), %rcx
	movl	$135000, %ebx                   ## imm = 0x20F58
	cmpl	(%rcx), %eax
	je	LBB0_13
## %bb.8:
	movq	_SPLL_FREQ_2700MHz@GOTPCREL(%rip), %rcx
	movl	$270000, %ebx                   ## imm = 0x41EB0
	cmpl	(%rcx), %eax
	je	LBB0_13
## %bb.9:
	leaq	L_.str(%rip), %rsi
	jmp	LBB0_10
LBB0_12:
	movl	$135000, %ebx                   ## imm = 0x20F58
LBB0_13:
	addl	%ebx, %ebx
	movl	%ebx, (%r14)
	movq	%r14, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_ddi_dotclock_get               ## TAILCALL
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_3, LBB0_3-LJTI0_0
.set L0_0_set_6, LBB0_6-LJTI0_0
.set L0_0_set_13, LBB0_13-LJTI0_0
.set L0_0_set_2, LBB0_2-LJTI0_0
.set L0_0_set_12, LBB0_12-LJTI0_0
LJTI0_0:
	.long	L0_0_set_5
	.long	L0_0_set_3
	.long	L0_0_set_6
	.long	L0_0_set_13
	.long	L0_0_set_2
	.long	L0_0_set_12
	.end_data_region
                                        ## -- End function
	.comm	_PORT_CLK_SEL_MASK,4,2          ## @PORT_CLK_SEL_MASK
	.comm	_SPLL_CTL,4,2                   ## @SPLL_CTL
	.comm	_SPLL_FREQ_MASK,4,2             ## @SPLL_FREQ_MASK
	.comm	_SPLL_FREQ_810MHz,4,2           ## @SPLL_FREQ_810MHz
	.comm	_SPLL_FREQ_1350MHz,4,2          ## @SPLL_FREQ_1350MHz
	.comm	_SPLL_FREQ_2700MHz,4,2          ## @SPLL_FREQ_2700MHz
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"bad spll freq\n"

L_.str.1:                               ## @.str.1
	.asciz	"bad port clock sel\n"

	.no_dead_strip	_hsw_ddi_clock_get
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function hsw_ddi_clock_get
_hsw_ddi_clock_get:                     ; @hsw_ddi_clock_get
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x1
	ldr	w0, [x0]
	bl	_to_i915
	mov	x21, x0
	ldr	w0, [x19, #4]
	bl	_hsw_pll_to_ddi_pll_sel
Lloh0:
	adrp	x8, _PORT_CLK_SEL_MASK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PORT_CLK_SEL_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	and	w8, w8, w0
	sub	w8, w8, #128
	cmp	w8, #5
	b.hi	LBB0_3
; %bb.1:
	mov	w20, #15464
	movk	w20, #1, lsl #16
Lloh3:
	adrp	x9, lJTI0_0@PAGE
Lloh4:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_2
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_2:
	mov	w0, #1
	b	LBB0_6
LBB0_3:
Lloh5:
	adrp	x1, l_.str.1@PAGE
Lloh6:
	add	x1, x1, l_.str.1@PAGEOFF
LBB0_4:
	mov	w0, #1
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WARN
LBB0_5:
	mov	w0, #0
LBB0_6:
	bl	_WRPLL_CTL
	mov	x1, x0
	mov	x0, x21
	bl	_hsw_ddi_calc_wrpll_link
	mov	x20, x0
	b	LBB0_12
LBB0_7:
Lloh7:
	adrp	x8, _SPLL_CTL@GOTPAGE
Lloh8:
	ldr	x8, [x8, _SPLL_CTL@GOTPAGEOFF]
Lloh9:
	ldr	w0, [x8]
	bl	_I915_READ
Lloh10:
	adrp	x8, _SPLL_FREQ_MASK@GOTPAGE
Lloh11:
	ldr	x8, [x8, _SPLL_FREQ_MASK@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh13:
	adrp	x9, _SPLL_FREQ_810MHz@GOTPAGE
Lloh14:
	ldr	x9, [x9, _SPLL_FREQ_810MHz@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	cmp	w8, w9
	b.eq	LBB0_12
; %bb.8:
Lloh16:
	adrp	x9, _SPLL_FREQ_1350MHz@GOTPAGE
Lloh17:
	ldr	x9, [x9, _SPLL_FREQ_1350MHz@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_10
LBB0_9:
	mov	w20, #3928
	movk	w20, #2, lsl #16
	b	LBB0_12
LBB0_10:
Lloh19:
	adrp	x9, _SPLL_FREQ_2700MHz@GOTPAGE
Lloh20:
	ldr	x9, [x9, _SPLL_FREQ_2700MHz@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_13
LBB0_11:
	mov	w20, #7856
	movk	w20, #4, lsl #16
LBB0_12:
	lsl	w8, w20, #1
	str	w8, [x19]
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_ddi_dotclock_get
LBB0_13:
Lloh22:
	adrp	x1, l_.str@PAGE
Lloh23:
	add	x1, x1, l_.str@PAGEOFF
	b	LBB0_4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpAdd	Lloh22, Lloh23
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_7-LBB0_2)>>2
	.byte	(LBB0_12-LBB0_2)>>2
	.byte	(LBB0_11-LBB0_2)>>2
	.byte	(LBB0_9-LBB0_2)>>2
                                        ; -- End function
	.comm	_PORT_CLK_SEL_MASK,4,2          ; @PORT_CLK_SEL_MASK
	.comm	_SPLL_CTL,4,2                   ; @SPLL_CTL
	.comm	_SPLL_FREQ_MASK,4,2             ; @SPLL_FREQ_MASK
	.comm	_SPLL_FREQ_810MHz,4,2           ; @SPLL_FREQ_810MHz
	.comm	_SPLL_FREQ_1350MHz,4,2          ; @SPLL_FREQ_1350MHz
	.comm	_SPLL_FREQ_2700MHz,4,2          ; @SPLL_FREQ_2700MHz
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"bad spll freq\n"

l_.str.1:                               ; @.str.1
	.asciz	"bad port clock sel\n"

	.no_dead_strip	_hsw_ddi_clock_get
.subsections_via_symbols
