	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_vram_mgr_bo_visible_size ## -- Begin function amdgpu_vram_mgr_bo_visible_size
	.p2align	4, 0x90
_amdgpu_vram_mgr_bo_visible_size:       ## @amdgpu_vram_mgr_bo_visible_size
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movl	24(%rdi), %edi
	callq	_amdgpu_ttm_adev
	movq	%rax, %r14
	movq	16(%rbx), %r15
	movl	(%rbx), %r12d
	movq	%rax, %rdi
	callq	_amdgpu_gmc_vram_full_visible
	testq	%rax, %rax
	je	LBB0_1
## %bb.8:
	movq	%rbx, %rdi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_bo_size                 ## TAILCALL
LBB0_1:
	movq	(%r14), %rax
	movq	_PAGE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarq	%cl, %rax
	cmpq	%rax, 8(%rbx)
	jge	LBB0_2
## %bb.3:
	xorl	%ebx, %ebx
	testq	%r15, %r15
	je	LBB0_7
## %bb.4:
	testl	%r12d, %r12d
	je	LBB0_7
## %bb.5:
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_6:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	_amdgpu_vram_mgr_vis_size
	addq	%rax, %rbx
	leaq	8(%r15), %rax
	subl	(%r15), %r12d
	movq	%rax, %r15
	jne	LBB0_6
	jmp	LBB0_7
LBB0_2:
	xorl	%ebx, %ebx
LBB0_7:
	movq	%rbx, %rax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PAGE_SHIFT,4,2                 ## @PAGE_SHIFT
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_vram_mgr_bo_visible_size ; -- Begin function amdgpu_vram_mgr_bo_visible_size
	.p2align	2
_amdgpu_vram_mgr_bo_visible_size:       ; @amdgpu_vram_mgr_bo_visible_size
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x21, x0
	ldr	w0, [x0, #24]
	bl	_amdgpu_ttm_adev
	mov	x19, x0
	ldr	x20, [x21, #16]
	ldr	w22, [x21]
	bl	_amdgpu_gmc_vram_full_visible
	cbz	x0, LBB0_2
; %bb.1:
	mov	x0, x21
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_amdgpu_bo_size
LBB0_2:
	ldr	x8, [x21, #8]
	ldr	x9, [x19]
Lloh0:
	adrp	x10, _PAGE_SHIFT@GOTPAGE
Lloh1:
	ldr	x10, [x10, _PAGE_SHIFT@GOTPAGEOFF]
Lloh2:
	ldr	w10, [x10]
	asr	x9, x9, x10
	cmp	x8, x9
	b.ge	LBB0_7
; %bb.3:
	mov	x21, #0
	cbz	x20, LBB0_8
; %bb.4:
	cbz	w22, LBB0_8
; %bb.5:
	mov	x21, #0
LBB0_6:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_vram_mgr_vis_size
	add	x21, x0, x21
	ldr	w8, [x20], #8
	subs	w22, w22, w8
	b.ne	LBB0_6
	b	LBB0_8
LBB0_7:
	mov	x21, #0
LBB0_8:
	mov	x0, x21
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_PAGE_SHIFT,4,2                 ; @PAGE_SHIFT
.subsections_via_symbols
