	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_cypress_notify_link_speed_change_after_state_change ## -- Begin function cypress_notify_link_speed_change_after_state_change
	.p2align	4, 0x90
_cypress_notify_link_speed_change_after_state_change: ## @cypress_notify_link_speed_change_after_state_change
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r15
	movq	%rdi, %r14
	movq	%rsi, %rdi
	callq	_cypress_get_maximum_link_speed
	movl	%eax, %ebx
	movq	%r15, %rdi
	callq	_cypress_get_maximum_link_speed
	cmpl	%eax, %ebx
	jae	LBB0_7
## %bb.1:
	movq	_RADEON_PCIE_GEN1@GOTPCREL(%rip), %rcx
	movq	_RADEON_PCIE_GEN2@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	jne	LBB0_2
## %bb.3:
	movq	_PCIE_PERF_REQ_PECI_GEN2@GOTPCREL(%rip), %rax
	cmpl	(%rcx), %ebx
	je	LBB0_5
	jmp	LBB0_6
LBB0_7:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	movq	_PCIE_PERF_REQ_PECI_GEN3@GOTPCREL(%rip), %rax
	cmpl	(%rcx), %ebx
	jne	LBB0_6
LBB0_5:
	movq	_PCIE_PERF_REQ_PECI_GEN1@GOTPCREL(%rip), %rax
LBB0_6:
	movl	(%rax), %esi
	movq	%r14, %rdi
	xorl	%edx, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_cypress_pcie_performance_request ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_PCIE_GEN1,4,2           ## @RADEON_PCIE_GEN1
	.comm	_PCIE_PERF_REQ_PECI_GEN1,4,2    ## @PCIE_PERF_REQ_PECI_GEN1
	.comm	_RADEON_PCIE_GEN2,4,2           ## @RADEON_PCIE_GEN2
	.comm	_PCIE_PERF_REQ_PECI_GEN2,4,2    ## @PCIE_PERF_REQ_PECI_GEN2
	.comm	_PCIE_PERF_REQ_PECI_GEN3,4,2    ## @PCIE_PERF_REQ_PECI_GEN3
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_cypress_notify_link_speed_change_after_state_change ; -- Begin function cypress_notify_link_speed_change_after_state_change
	.p2align	2
_cypress_notify_link_speed_change_after_state_change: ; @cypress_notify_link_speed_change_after_state_change
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x21, x2
	mov	x19, x0
	mov	x0, x1
	bl	_cypress_get_maximum_link_speed
	mov	x20, x0
	mov	x0, x21
	bl	_cypress_get_maximum_link_speed
	cmp	w20, w0
	b.hs	LBB0_2
; %bb.1:
Lloh0:
	adrp	x8, _RADEON_PCIE_GEN1@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_PCIE_GEN1@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _RADEON_PCIE_GEN2@GOTPAGE
Lloh4:
	ldr	x9, [x9, _RADEON_PCIE_GEN2@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
Lloh6:
	adrp	x10, _PCIE_PERF_REQ_PECI_GEN1@GOTPAGE
Lloh7:
	ldr	x10, [x10, _PCIE_PERF_REQ_PECI_GEN1@GOTPAGEOFF]
Lloh8:
	adrp	x11, _PCIE_PERF_REQ_PECI_GEN2@GOTPAGE
Lloh9:
	ldr	x11, [x11, _PCIE_PERF_REQ_PECI_GEN2@GOTPAGEOFF]
Lloh10:
	adrp	x12, _PCIE_PERF_REQ_PECI_GEN3@GOTPAGE
Lloh11:
	ldr	x12, [x12, _PCIE_PERF_REQ_PECI_GEN3@GOTPAGEOFF]
	cmp	w20, w9
	csel	x9, x11, x12, eq
	cmp	w20, w8
	csel	x8, x10, x9, eq
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_cypress_pcie_performance_request
LBB0_2:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_PCIE_GEN1,4,2           ; @RADEON_PCIE_GEN1
	.comm	_PCIE_PERF_REQ_PECI_GEN1,4,2    ; @PCIE_PERF_REQ_PECI_GEN1
	.comm	_RADEON_PCIE_GEN2,4,2           ; @RADEON_PCIE_GEN2
	.comm	_PCIE_PERF_REQ_PECI_GEN2,4,2    ; @PCIE_PERF_REQ_PECI_GEN2
	.comm	_PCIE_PERF_REQ_PECI_GEN3,4,2    ; @PCIE_PERF_REQ_PECI_GEN3
.subsections_via_symbols
