	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function amdgpu_device_ip_hw_init_phase1
_amdgpu_device_ip_hw_init_phase1:       ## @amdgpu_device_ip_hw_init_phase1
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	cmpl	$0, (%rdi)
	jle	LBB0_11
## %bb.1:
	movq	%rdi, %r14
	movq	8(%rdi), %rax
	xorl	%ebx, %ebx
	movq	_AMD_IP_BLOCK_TYPE_COMMON@GOTPCREL(%rip), %r12
	xorl	%r13d, %r13d
	jmp	LBB0_2
	.p2align	4, 0x90
LBB0_10:                                ##   in Loop: Header=BB0_2 Depth=1
	incq	%r13
	movslq	(%r14), %rcx
	addq	$16, %rbx
	cmpq	%rcx, %r13
	jge	LBB0_11
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	cmpl	$0, 4(%rax,%rbx)
	je	LBB0_10
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	cmpl	$0, (%rax,%rbx)
	jne	LBB0_10
## %bb.4:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	8(%rax,%rbx), %rcx
	movq	(%rcx), %rax
	cmpq	(%r12), %rax
	jne	LBB0_5
LBB0_7:                                 ##   in Loop: Header=BB0_2 Depth=1
	movq	8(%rcx), %rax
	movq	%r14, %rdi
	callq	*(%rax)
	testl	%eax, %eax
	jne	LBB0_8
## %bb.9:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	8(%r14), %rax
	movl	$1, (%rax,%rbx)
	jmp	LBB0_10
LBB0_5:                                 ##   in Loop: Header=BB0_2 Depth=1
	movq	%r14, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	setne	%sil
	movq	8(%r14), %rax
	movq	8(%rax,%rbx), %rcx
	movq	(%rcx), %rdi
	movq	_AMD_IP_BLOCK_TYPE_PSP@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rdi
	sete	%dl
	testb	%dl, %sil
	jne	LBB0_7
## %bb.6:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	_AMD_IP_BLOCK_TYPE_IH@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rdi
	jne	LBB0_10
	jmp	LBB0_7
LBB0_11:
	xorl	%r15d, %r15d
LBB0_12:
	movl	%r15d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_8:
	movl	%eax, %r15d
	movq	8(%r14), %rax
	movq	8(%rax,%rbx), %rax
	movq	8(%rax), %rax
	movl	8(%rax), %esi
	leaq	L_.str(%rip), %rdi
	movl	%r15d, %edx
	callq	_DRM_ERROR
	jmp	LBB0_12
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_IP_BLOCK_TYPE_COMMON,8,3   ## @AMD_IP_BLOCK_TYPE_COMMON
	.comm	_AMD_IP_BLOCK_TYPE_PSP,8,3      ## @AMD_IP_BLOCK_TYPE_PSP
	.comm	_AMD_IP_BLOCK_TYPE_IH,8,3       ## @AMD_IP_BLOCK_TYPE_IH
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"hw_init of IP block <%s> failed %d\n"

	.no_dead_strip	_amdgpu_device_ip_hw_init_phase1
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function amdgpu_device_ip_hw_init_phase1
_amdgpu_device_ip_hw_init_phase1:       ; @amdgpu_device_ip_hw_init_phase1
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	ldr	w8, [x0]
	cmp	w8, #1
	b.lt	LBB0_9
; %bb.1:
	mov	x19, x0
	mov	x21, #0
	mov	x22, #0
Lloh0:
	adrp	x23, _AMD_IP_BLOCK_TYPE_COMMON@GOTPAGE
Lloh1:
	ldr	x23, [x23, _AMD_IP_BLOCK_TYPE_COMMON@GOTPAGEOFF]
	ldr	x8, [x0, #8]
	mov	w24, #1
Lloh2:
	adrp	x25, _AMD_IP_BLOCK_TYPE_PSP@GOTPAGE
Lloh3:
	ldr	x25, [x25, _AMD_IP_BLOCK_TYPE_PSP@GOTPAGEOFF]
Lloh4:
	adrp	x26, _AMD_IP_BLOCK_TYPE_IH@GOTPAGE
Lloh5:
	ldr	x26, [x26, _AMD_IP_BLOCK_TYPE_IH@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:                                 ;   in Loop: Header=BB0_3 Depth=1
	add	x22, x22, #1
	ldrsw	x9, [x19]
	add	x21, x21, #16
	cmp	x22, x9
	b.ge	LBB0_9
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	add	x9, x8, x21
	ldr	w9, [x9, #4]
	cbz	w9, LBB0_2
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	ldr	w9, [x8, x21]
	cbnz	w9, LBB0_2
; %bb.5:                                ;   in Loop: Header=BB0_3 Depth=1
	add	x8, x8, x21
	ldr	x9, [x8, #8]
	ldr	x8, [x9]
	ldr	x10, [x23]
	cmp	x8, x10
	b.eq	LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_3 Depth=1
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	ldr	x8, [x19, #8]
	add	x9, x8, x21
	ldr	x9, [x9, #8]
	ldr	x10, [x9]
	ldr	x11, [x25]
	cmp	x10, x11
	ccmp	x0, #0, #4, eq
	ldr	x11, [x26]
	ccmp	x10, x11, #4, eq
	b.ne	LBB0_2
LBB0_7:                                 ;   in Loop: Header=BB0_3 Depth=1
	ldr	x8, [x9, #8]
	ldr	x8, [x8]
	mov	x0, x19
	blr	x8
	cbnz	w0, LBB0_11
; %bb.8:                                ;   in Loop: Header=BB0_3 Depth=1
	ldr	x8, [x19, #8]
	str	w24, [x8, x21]
	b	LBB0_2
LBB0_9:
	mov	w20, #0
LBB0_10:
	mov	x0, x20
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_11:
	mov	x20, x0
	ldr	x8, [x19, #8]
	add	x8, x8, x21
	ldr	x8, [x8, #8]
	ldr	x8, [x8, #8]
	ldr	w1, [x8, #8]
Lloh6:
	adrp	x0, l_.str@PAGE
Lloh7:
	add	x0, x0, l_.str@PAGEOFF
	mov	x2, x20
	bl	_DRM_ERROR
	b	LBB0_10
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh6, Lloh7
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_IP_BLOCK_TYPE_COMMON,8,3   ; @AMD_IP_BLOCK_TYPE_COMMON
	.comm	_AMD_IP_BLOCK_TYPE_PSP,8,3      ; @AMD_IP_BLOCK_TYPE_PSP
	.comm	_AMD_IP_BLOCK_TYPE_IH,8,3       ; @AMD_IP_BLOCK_TYPE_IH
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"hw_init of IP block <%s> failed %d\n"

	.no_dead_strip	_amdgpu_device_ip_hw_init_phase1
.subsections_via_symbols
