	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3                               ## -- Begin function dcn_bw_update_from_pplib
LCPI0_0:
	.quad	0x408f400000000000              ## double 1000
LCPI0_1:
	.quad	0x4040000000000000              ## double 32
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4
LCPI0_2:
	.quad	0x408f400000000000              ## double 1000
	.quad	0x408f400000000000              ## double 1000
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_dcn_bw_update_from_pplib
	.p2align	4, 0x90
_dcn_bw_update_from_pplib:              ## @dcn_bw_update_from_pplib
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	8(%rdi), %r15
	xorpd	%xmm0, %xmm0
	movapd	%xmm0, -48(%rbp)
	movq	$0, -32(%rbp)
	movapd	%xmm0, -80(%rbp)
	movq	$0, -64(%rbp)
	movq	_DM_PP_CLOCK_TYPE_FCLK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-48(%rbp), %rdx
	movq	%r15, %rdi
	callq	_dm_pp_get_clock_levels_by_type_with_voltage
	movl	%eax, %ebx
	xorl	%eax, %eax
	callq	_kernel_fpu_begin
	testl	%ebx, %ebx
	je	LBB0_3
## %bb.1:
	leaq	-48(%rbp), %rdi
	callq	_verify_clock_values
	testl	%eax, %eax
	je	LBB0_3
## %bb.2:
	xorl	%edi, %edi
	cmpl	$3, -48(%rbp)
	setge	%dil
	callq	_ASSERT
	movq	-40(%rbp), %rcx
	movsd	(%rcx), %xmm1                   ## xmm1 = mem[0],zero
	movsd	LCPI0_0(%rip), %xmm0            ## xmm0 = mem[0],zero
	divsd	%xmm0, %xmm1
	mulsd	LCPI0_1(%rip), %xmm1
	divsd	%xmm0, %xmm1
	cvttsd2si	%xmm1, %edx
	movq	(%r14), %rax
	movl	%edx, (%rax)
	movsd	16(%rax), %xmm1                 ## xmm1 = mem[0],zero
	movslq	-48(%rbp), %rdx
	xorl	%esi, %esi
	cmpq	$3, %rdx
	setge	%sil
	movl	%edx, %edi
	subl	%esi, %edi
	addl	$-2, %edi
	movslq	%edi, %rsi
	movsd	(%rcx,%rsi,8), %xmm2            ## xmm2 = mem[0],zero
	divsd	%xmm0, %xmm2
	mulsd	%xmm1, %xmm2
	movq	_ddr4_dram_factor_single_Channel@GOTPCREL(%rip), %rsi
	movsd	(%rsi), %xmm3                   ## xmm3 = mem[0],zero
	mulsd	%xmm3, %xmm2
	divsd	%xmm0, %xmm2
	movsd	%xmm2, 8(%rax)
	movupd	-16(%rcx,%rdx,8), %xmm0
	movapd	LCPI0_2(%rip), %xmm2            ## xmm2 = [1.0E+3,1.0E+3]
	divpd	%xmm2, %xmm0
	movddup	%xmm1, %xmm1                    ## xmm1 = xmm1[0,0]
	mulpd	%xmm0, %xmm1
	movddup	%xmm3, %xmm0                    ## xmm0 = xmm3[0,0]
	mulpd	%xmm1, %xmm0
	divpd	%xmm2, %xmm0
	movupd	%xmm0, 24(%rax)
	jmp	LBB0_4
LBB0_3:
	xorl	%eax, %eax
	callq	_BREAK_TO_DEBUGGER
LBB0_4:
	xorl	%eax, %eax
	callq	_kernel_fpu_end
	movq	_DM_PP_CLOCK_TYPE_DCFCLK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-80(%rbp), %rdx
	movq	%r15, %rdi
	callq	_dm_pp_get_clock_levels_by_type_with_voltage
	movl	%eax, %ebx
	xorl	%eax, %eax
	callq	_kernel_fpu_begin
	testl	%ebx, %ebx
	je	LBB0_8
## %bb.5:
	leaq	-80(%rbp), %rdi
	callq	_verify_clock_values
	testl	%eax, %eax
	je	LBB0_8
## %bb.6:
	movl	-80(%rbp), %eax
	cmpl	$3, %eax
	jl	LBB0_8
## %bb.7:
	movq	-72(%rbp), %rcx
	movq	(%r14), %rdx
	leal	-3(%rax), %esi
	movsd	(%rcx), %xmm0                   ## xmm0 = mem[0],zero
	movhpd	(%rcx,%rsi,8), %xmm0            ## xmm0 = xmm0[0],mem[0]
	movapd	LCPI0_2(%rip), %xmm1            ## xmm1 = [1.0E+3,1.0E+3]
	divpd	%xmm1, %xmm0
	movupd	%xmm0, 40(%rdx)
	leal	-2(%rax), %esi
	decl	%eax
	movsd	(%rcx,%rsi,8), %xmm0            ## xmm0 = mem[0],zero
	movhpd	(%rcx,%rax,8), %xmm0            ## xmm0 = xmm0[0],mem[0]
	divpd	%xmm1, %xmm0
	movupd	%xmm0, 56(%rdx)
	jmp	LBB0_9
LBB0_8:
	xorl	%eax, %eax
	callq	_BREAK_TO_DEBUGGER
LBB0_9:
	xorl	%eax, %eax
	callq	_kernel_fpu_end
	addq	$56, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DM_PP_CLOCK_TYPE_FCLK,4,2      ## @DM_PP_CLOCK_TYPE_FCLK
	.comm	_ddr4_dram_factor_single_Channel,8,3 ## @ddr4_dram_factor_single_Channel
	.comm	_DM_PP_CLOCK_TYPE_DCFCLK,4,2    ## @DM_PP_CLOCK_TYPE_DCFCLK
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_dcn_bw_update_from_pplib       ; -- Begin function dcn_bw_update_from_pplib
	.p2align	2
_dcn_bw_update_from_pplib:              ; @dcn_bw_update_from_pplib
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x20, [x0, #8]
	stp	xzr, xzr, [sp, #24]
	str	xzr, [sp, #40]
	stp	xzr, xzr, [sp]
	str	xzr, [sp, #16]
Lloh0:
	adrp	x8, _DM_PP_CLOCK_TYPE_FCLK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DM_PP_CLOCK_TYPE_FCLK@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	add	x2, sp, #24
	mov	x0, x20
	bl	_dm_pp_get_clock_levels_by_type_with_voltage
	mov	x21, x0
	bl	_kernel_fpu_begin
	cbz	w21, LBB0_3
; %bb.1:
	add	x0, sp, #24
	bl	_verify_clock_values
	cbz	w0, LBB0_3
; %bb.2:
	ldr	w8, [sp, #24]
	cmp	w8, #2
	cset	w0, gt
	bl	_ASSERT
	ldr	x8, [sp, #32]
	mov	x9, #70368744177664
	movk	x9, #16527, lsl #48
	dup.2d	v0, x9
	ldr	d1, [x8]
	fmov	d2, x9
	fdiv	d1, d1, d2
	mov	x9, #4629700416936869888
	fmov	d3, x9
	fmul	d1, d1, d3
	fdiv	d1, d1, d2
	fcvtzs	w9, d1
	ldr	x10, [x19]
	str	w9, [x10]
	ldr	w9, [sp, #24]
	subs	w11, w9, #2
	mov	w12, #-3
	cinc	w12, w12, le
	add	w9, w12, w9
	ldr	d1, [x8, w9, sxtw #3]
	ldr	d3, [x10, #16]
	fdiv	d1, d1, d2
	fmul	d1, d3, d1
Lloh3:
	adrp	x9, _ddr4_dram_factor_single_Channel@GOTPAGE
Lloh4:
	ldr	x9, [x9, _ddr4_dram_factor_single_Channel@GOTPAGEOFF]
Lloh5:
	ldr	d4, [x9]
	fmul	d1, d4, d1
	fdiv	d1, d1, d2
	str	d1, [x10, #8]
	sbfiz	x9, x11, #3, #32
	ldr	q1, [x8, x9]
	fdiv.2d	v1, v1, v0
	fmul.2d	v1, v1, v3[0]
	fmul.2d	v1, v1, v4[0]
	fdiv.2d	v0, v1, v0
	stur	q0, [x10, #24]
	b	LBB0_4
LBB0_3:
	bl	_BREAK_TO_DEBUGGER
LBB0_4:
	bl	_kernel_fpu_end
Lloh6:
	adrp	x8, _DM_PP_CLOCK_TYPE_DCFCLK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _DM_PP_CLOCK_TYPE_DCFCLK@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	x2, sp
	mov	x0, x20
	bl	_dm_pp_get_clock_levels_by_type_with_voltage
	mov	x20, x0
	bl	_kernel_fpu_begin
	cbz	w20, LBB0_8
; %bb.5:
	mov	x0, sp
	bl	_verify_clock_values
	cbz	w0, LBB0_8
; %bb.6:
	ldr	w8, [sp]
	subs	w9, w8, #3
	b.lt	LBB0_8
; %bb.7:
	ldr	x10, [sp, #8]
	ldr	d0, [x10]
	mov	x11, #70368744177664
	movk	x11, #16527, lsl #48
	fmov	d1, x11
	fdiv	d0, d0, d1
	ldr	x11, [x19]
	str	d0, [x11, #40]
	ldr	d0, [x10, w9, uxtw #3]
	fdiv	d0, d0, d1
	str	d0, [x11, #48]
	sub	w9, w8, #2
	ldr	d0, [x10, w9, uxtw #3]
	fdiv	d0, d0, d1
	str	d0, [x11, #56]
	sub	w8, w8, #1
	ldr	d0, [x10, w8, uxtw #3]
	fdiv	d0, d0, d1
	str	d0, [x11, #64]
	b	LBB0_9
LBB0_8:
	bl	_BREAK_TO_DEBUGGER
LBB0_9:
	bl	_kernel_fpu_end
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_DM_PP_CLOCK_TYPE_FCLK,4,2      ; @DM_PP_CLOCK_TYPE_FCLK
	.comm	_ddr4_dram_factor_single_Channel,8,3 ; @ddr4_dram_factor_single_Channel
	.comm	_DM_PP_CLOCK_TYPE_DCFCLK,4,2    ; @DM_PP_CLOCK_TYPE_DCFCLK
.subsections_via_symbols
