	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_gem_userptr_ioctl       ## -- Begin function radeon_gem_userptr_ioctl
	.p2align	4, 0x90
_radeon_gem_userptr_ioctl:              ## @radeon_gem_userptr_ioctl
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r15
	movq	%rsi, %rbx
	movq	$1, -72(%rbp)
	movq	(%rdi), %r14
	movl	(%rsi), %edi
	callq	_untagged_addr
	movl	%eax, (%rbx)
	orl	4(%rbx), %eax
	movl	%eax, %edi
	callq	_offset_in_page
	testq	%rax, %rax
	jne	LBB0_1
## %bb.3:
	movl	8(%rbx), %eax
	movq	_RADEON_GEM_USERPTR_READONLY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_RADEON_GEM_USERPTR_ANONONLY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, %edi
	orl	%esi, %edi
	movq	_RADEON_GEM_USERPTR_VALIDATE@GOTPCREL(%rip), %rdx
	orl	(%rdx), %edi
	movq	_RADEON_GEM_USERPTR_REGISTER@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	%edx, %edi
	notl	%edi
	testl	%edi, %eax
	je	LBB0_4
LBB0_1:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
LBB0_2:
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_22:
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_4:
	testl	%eax, %esi
	je	LBB0_16
## %bb.5:
	movq	(%r14), %rax
	movq	_CHIP_R600@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_1
	jmp	LBB0_6
LBB0_16:
	testl	%eax, %ecx
	je	LBB0_18
## %bb.17:
	andl	%eax, %edx
	je	LBB0_18
LBB0_6:
	leaq	8(%r14), %r13
	movq	%r13, %rdi
	callq	_down_read
	movl	4(%rbx), %esi
	movq	_RADEON_GEM_DOMAIN_CPU@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	leaq	-48(%rbp), %rax
	movq	%rax, (%rsp)
	movq	%r14, %rdi
	xorl	%edx, %edx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	_radeon_gem_object_create
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	LBB0_15
## %bb.7:
	movq	%r13, -64(%rbp)                 ## 8-byte Spill
	movq	-48(%rbp), %rdi
	callq	_gem_to_radeon_bo
	movq	%rax, %r13
	movl	4(%rax), %edi
	movl	(%rbx), %esi
	movl	8(%rbx), %edx
	callq	_radeon_ttm_tt_set_userptr
	testl	%eax, %eax
	je	LBB0_8
LBB0_14:
	movq	-48(%rbp), %rdi
	movl	%eax, %r12d
	callq	_drm_gem_object_put_unlocked
	movq	-64(%rbp), %r13                 ## 8-byte Reload
LBB0_15:
	movq	%r13, %rdi
	callq	_up_read
	movq	%r14, %rdi
	movl	%r12d, %esi
	callq	_radeon_gem_handle_lockup
	jmp	LBB0_22
LBB0_18:
	movq	_EACCES@GOTPCREL(%rip), %rcx
	jmp	LBB0_2
LBB0_8:
	movl	8(%rbx), %eax
	movq	_RADEON_GEM_USERPTR_REGISTER@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_11
## %bb.9:
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_radeon_mn_register
	testl	%eax, %eax
	jne	LBB0_14
## %bb.10:
	movl	8(%rbx), %eax
LBB0_11:
	movq	_RADEON_GEM_USERPTR_VALIDATE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_20
## %bb.12:
	movq	_current@GOTPCREL(%rip), %r12
	movq	(%r12), %rax
	movq	(%rax), %rdi
	callq	_down_read
	movq	%r13, %rdi
	movl	$1, %esi
	callq	_radeon_bo_reserve
	testl	%eax, %eax
	je	LBB0_19
## %bb.13:
	movl	%eax, %ebx
	movq	(%r12), %rax
	movq	(%rax), %rdi
	callq	_up_read
	movl	%ebx, %eax
	jmp	LBB0_14
LBB0_19:
	movq	%r13, %r12
	addq	$4, %r12
	movq	_RADEON_GEM_DOMAIN_GTT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_radeon_ttm_placement_from_domain
	leaq	-72(%rbp), %rdx
	movq	%r12, %rdi
	movq	%r13, %rsi
	callq	_ttm_bo_validate
	movl	%eax, %r12d
	movq	%r13, %rdi
	callq	_radeon_bo_unreserve
	movq	_current@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	(%rax), %rdi
	callq	_up_read
	movl	%r12d, %eax
	testl	%r12d, %r12d
	jne	LBB0_14
LBB0_20:
	movq	-48(%rbp), %rsi
	leaq	-52(%rbp), %rdx
	movq	%r15, %rdi
	callq	_drm_gem_handle_create
	movl	%eax, %r12d
	movq	-48(%rbp), %rdi
	callq	_drm_gem_object_put_unlocked
	testl	%r12d, %r12d
	movq	-64(%rbp), %r13                 ## 8-byte Reload
	jne	LBB0_15
## %bb.21:
	movl	-52(%rbp), %eax
	movl	%eax, 12(%rbx)
	movq	%r13, %rdi
	callq	_up_read
	xorl	%eax, %eax
	jmp	LBB0_22
	.cfi_endproc
                                        ## -- End function
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_RADEON_GEM_USERPTR_READONLY,4,2 ## @RADEON_GEM_USERPTR_READONLY
	.comm	_RADEON_GEM_USERPTR_ANONONLY,4,2 ## @RADEON_GEM_USERPTR_ANONONLY
	.comm	_RADEON_GEM_USERPTR_VALIDATE,4,2 ## @RADEON_GEM_USERPTR_VALIDATE
	.comm	_RADEON_GEM_USERPTR_REGISTER,4,2 ## @RADEON_GEM_USERPTR_REGISTER
	.comm	_CHIP_R600,8,3                  ## @CHIP_R600
	.comm	_EACCES,4,2                     ## @EACCES
	.comm	_RADEON_GEM_DOMAIN_CPU,4,2      ## @RADEON_GEM_DOMAIN_CPU
	.comm	_current,8,3                    ## @current
	.comm	_RADEON_GEM_DOMAIN_GTT,4,2      ## @RADEON_GEM_DOMAIN_GTT
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_gem_userptr_ioctl       ; -- Begin function radeon_gem_userptr_ioctl
	.p2align	2
_radeon_gem_userptr_ioctl:              ; @radeon_gem_userptr_ioctl
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #128
	.cfi_def_cfa_offset 128
	stp	x28, x27, [sp, #32]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #48]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #64]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #80]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #96]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #112]            ; 16-byte Folded Spill
	add	x29, sp, #112
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x2
	mov	x20, x1
	mov	w8, #1
	str	x8, [sp, #24]
	ldr	x19, [x0]
	ldr	w0, [x1]
	bl	_untagged_addr
	str	w0, [x20]
	ldr	w8, [x20, #4]
	orr	w0, w8, w0
	bl	_offset_in_page
	cbnz	x0, LBB0_2
; %bb.1:
	ldr	w8, [x20, #8]
Lloh0:
	adrp	x9, _RADEON_GEM_USERPTR_READONLY@GOTPAGE
Lloh1:
	ldr	x9, [x9, _RADEON_GEM_USERPTR_READONLY@GOTPAGEOFF]
Lloh2:
	adrp	x11, _RADEON_GEM_USERPTR_ANONONLY@GOTPAGE
Lloh3:
	ldr	x11, [x11, _RADEON_GEM_USERPTR_ANONONLY@GOTPAGEOFF]
Lloh4:
	ldr	w10, [x9]
Lloh5:
	ldr	w9, [x11]
	orr	w11, w9, w10
Lloh6:
	adrp	x26, _RADEON_GEM_USERPTR_VALIDATE@GOTPAGE
Lloh7:
	ldr	x26, [x26, _RADEON_GEM_USERPTR_VALIDATE@GOTPAGEOFF]
	ldr	w12, [x26]
	orr	w12, w11, w12
Lloh8:
	adrp	x27, _RADEON_GEM_USERPTR_REGISTER@GOTPAGE
Lloh9:
	ldr	x27, [x27, _RADEON_GEM_USERPTR_REGISTER@GOTPAGEOFF]
	ldr	w11, [x27]
	orr	w12, w12, w11
	bics	wzr, w8, w12
	b.eq	LBB0_5
LBB0_2:
Lloh10:
	adrp	x8, _EINVAL@GOTPAGE
Lloh11:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
LBB0_3:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_4:
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	ret
LBB0_5:
	tst	w10, w8
	b.eq	LBB0_7
; %bb.6:
	ldr	x8, [x19]
Lloh12:
	adrp	x9, _CHIP_R600@GOTPAGE
Lloh13:
	ldr	x9, [x9, _CHIP_R600@GOTPAGEOFF]
Lloh14:
	ldr	x9, [x9]
	cmp	x8, x9
	b.lt	LBB0_2
	b	LBB0_9
LBB0_7:
	and	w9, w9, w8
	and	w8, w11, w8
	cmp	w9, #0
	ccmp	w8, #0, #4, ne
	b.ne	LBB0_9
; %bb.8:
Lloh15:
	adrp	x8, _EACCES@GOTPAGE
Lloh16:
	ldr	x8, [x8, _EACCES@GOTPAGEOFF]
	b	LBB0_3
LBB0_9:
	add	x22, x19, #8
	mov	x0, x22
	bl	_down_read
	ldr	w1, [x20, #4]
Lloh17:
	adrp	x8, _RADEON_GEM_DOMAIN_CPU@GOTPAGE
Lloh18:
	ldr	x8, [x8, _RADEON_GEM_DOMAIN_CPU@GOTPAGEOFF]
Lloh19:
	ldr	w3, [x8]
	add	x6, sp, #16
	mov	x0, x19
	mov	w2, #0
	mov	w4, #0
	mov	w5, #0
	bl	_radeon_gem_object_create
	mov	x25, x0
	cbnz	w0, LBB0_12
; %bb.10:
	ldr	x0, [sp, #16]
	bl	_gem_to_radeon_bo
	mov	x23, x0
	mov	x24, x0
	ldr	w0, [x24, #4]!
	ldr	w1, [x20]
	ldr	w2, [x20, #8]
	bl	_radeon_ttm_tt_set_userptr
	mov	x25, x0
	cbz	w0, LBB0_13
LBB0_11:
	ldr	x0, [sp, #16]
	bl	_drm_gem_object_put_unlocked
LBB0_12:
	mov	x0, x22
	bl	_up_read
	mov	x0, x19
	mov	x1, x25
	bl	_radeon_gem_handle_lockup
	b	LBB0_4
LBB0_13:
	ldr	w8, [x20, #8]
	ldr	w9, [x27]
	tst	w9, w8
	b.eq	LBB0_16
; %bb.14:
	ldr	w1, [x20]
	mov	x0, x23
	bl	_radeon_mn_register
	mov	x25, x0
	cbnz	w0, LBB0_11
; %bb.15:
	ldr	w8, [x20, #8]
LBB0_16:
	ldr	w9, [x26]
	tst	w9, w8
	b.eq	LBB0_20
; %bb.17:
Lloh20:
	adrp	x26, _current@GOTPAGE
Lloh21:
	ldr	x26, [x26, _current@GOTPAGEOFF]
	ldr	x8, [x26]
	ldr	x0, [x8]
	bl	_down_read
	mov	x0, x23
	mov	w1, #1
	bl	_radeon_bo_reserve
	cbz	w0, LBB0_19
; %bb.18:
	mov	x25, x0
	ldr	x8, [x26]
	ldr	x0, [x8]
	bl	_up_read
	b	LBB0_11
LBB0_19:
Lloh22:
	adrp	x8, _RADEON_GEM_DOMAIN_GTT@GOTPAGE
Lloh23:
	ldr	x8, [x8, _RADEON_GEM_DOMAIN_GTT@GOTPAGEOFF]
Lloh24:
	ldr	w1, [x8]
	mov	x0, x23
	bl	_radeon_ttm_placement_from_domain
	add	x2, sp, #24
	mov	x0, x24
	mov	x1, x23
	bl	_ttm_bo_validate
	mov	x25, x0
	mov	x0, x23
	bl	_radeon_bo_unreserve
	ldr	x8, [x26]
	ldr	x0, [x8]
	bl	_up_read
	cbnz	w25, LBB0_11
LBB0_20:
	ldr	x1, [sp, #16]
	add	x2, sp, #12
	mov	x0, x21
	bl	_drm_gem_handle_create
	mov	x25, x0
	ldr	x0, [sp, #16]
	bl	_drm_gem_object_put_unlocked
	cbnz	w25, LBB0_12
; %bb.21:
	ldr	w8, [sp, #12]
	str	w8, [x20, #12]
	mov	x0, x22
	bl	_up_read
	mov	w0, #0
	b	LBB0_4
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh4
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.cfi_endproc
                                        ; -- End function
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_RADEON_GEM_USERPTR_READONLY,4,2 ; @RADEON_GEM_USERPTR_READONLY
	.comm	_RADEON_GEM_USERPTR_ANONONLY,4,2 ; @RADEON_GEM_USERPTR_ANONONLY
	.comm	_RADEON_GEM_USERPTR_VALIDATE,4,2 ; @RADEON_GEM_USERPTR_VALIDATE
	.comm	_RADEON_GEM_USERPTR_REGISTER,4,2 ; @RADEON_GEM_USERPTR_REGISTER
	.comm	_CHIP_R600,8,3                  ; @CHIP_R600
	.comm	_EACCES,4,2                     ; @EACCES
	.comm	_RADEON_GEM_DOMAIN_CPU,4,2      ; @RADEON_GEM_DOMAIN_CPU
	.comm	_current,8,3                    ; @current
	.comm	_RADEON_GEM_DOMAIN_GTT,4,2      ; @RADEON_GEM_DOMAIN_GTT
.subsections_via_symbols
