	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function uvd_v4_2_set_powergating_state
_uvd_v4_2_set_powergating_state:        ## @uvd_v4_2_set_powergating_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	movq	_AMD_PG_STATE_GATE@GOTPCREL(%rip), %rax
	cmpl	%esi, (%rax)
	jne	LBB0_6
## %bb.1:
	movq	%rbx, %rdi
	callq	_uvd_v4_2_stop
	movq	_AMD_PG_SUPPORT_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rbx)
	je	LBB0_5
## %bb.2:
	cmpl	$0, 4(%rbx)
	jne	LBB0_5
## %bb.3:
	movq	_ixCURRENT_PG_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_SMC
	movq	_CURRENT_PG_STATUS__UVD_PG_STATUS_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	jne	LBB0_5
## %bb.4:
	movq	_mmUVD_PGFSM_CONFIG@GOTPCREL(%rip), %rax
	movq	_UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK@GOTPCREL(%rip), %rcx
	movq	_UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	movl	(%rax), %edi
	movq	_UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	callq	_WREG32
	movl	$20, %edi
	callq	_mdelay
LBB0_5:
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
LBB0_6:
	movq	_AMD_PG_SUPPORT_UVD@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rbx)
	je	LBB0_10
## %bb.7:
	cmpl	$0, 4(%rbx)
	jne	LBB0_10
## %bb.8:
	movq	_ixCURRENT_PG_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_SMC
	movq	_CURRENT_PG_STATUS__UVD_PG_STATUS_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_10
## %bb.9:
	movq	_mmUVD_PGFSM_CONFIG@GOTPCREL(%rip), %rax
	movq	_UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK@GOTPCREL(%rip), %rcx
	movq	_UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	movl	(%rax), %edi
	movq	_UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	callq	_WREG32
	movl	$30, %edi
	callq	_mdelay
LBB0_10:
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_uvd_v4_2_start                 ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_PG_STATE_GATE,4,2          ## @AMD_PG_STATE_GATE
	.comm	_AMD_PG_SUPPORT_UVD,4,2         ## @AMD_PG_SUPPORT_UVD
	.comm	_ixCURRENT_PG_STATUS,4,2        ## @ixCURRENT_PG_STATUS
	.comm	_CURRENT_PG_STATUS__UVD_PG_STATUS_MASK,4,2 ## @CURRENT_PG_STATUS__UVD_PG_STATUS_MASK
	.comm	_mmUVD_PGFSM_CONFIG,4,2         ## @mmUVD_PGFSM_CONFIG
	.comm	_UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK,4,2 ## @UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK
	.comm	_UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK,4,2 ## @UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK
	.comm	_UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK,4,2 ## @UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK
	.comm	_UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK,4,2 ## @UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK
	.no_dead_strip	_uvd_v4_2_set_powergating_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function uvd_v4_2_set_powergating_state
_uvd_v4_2_set_powergating_state:        ; @uvd_v4_2_set_powergating_state
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
Lloh0:
	adrp	x8, _AMD_PG_STATE_GATE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMD_PG_STATE_GATE@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cmp	w8, w1
	b.ne	LBB0_6
; %bb.1:
	mov	x0, x19
	bl	_uvd_v4_2_stop
	ldr	w8, [x19]
Lloh3:
	adrp	x9, _AMD_PG_SUPPORT_UVD@GOTPAGE
Lloh4:
	ldr	x9, [x9, _AMD_PG_SUPPORT_UVD@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_5
; %bb.2:
	ldr	w8, [x19, #4]
	cbnz	w8, LBB0_5
; %bb.3:
Lloh6:
	adrp	x8, _ixCURRENT_PG_STATUS@GOTPAGE
Lloh7:
	ldr	x8, [x8, _ixCURRENT_PG_STATUS@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	bl	_RREG32_SMC
Lloh9:
	adrp	x8, _CURRENT_PG_STATUS__UVD_PG_STATUS_MASK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _CURRENT_PG_STATUS__UVD_PG_STATUS_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	tst	w8, w0
	b.ne	LBB0_5
; %bb.4:
Lloh12:
	adrp	x8, _mmUVD_PGFSM_CONFIG@GOTPAGE
Lloh13:
	ldr	x8, [x8, _mmUVD_PGFSM_CONFIG@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
Lloh15:
	adrp	x8, _UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK@GOTPAGE
Lloh16:
	ldr	x8, [x8, _UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
Lloh18:
	adrp	x9, _UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK@GOTPAGE
Lloh19:
	ldr	x9, [x9, _UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh21:
	adrp	x9, _UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK@GOTPAGE
Lloh22:
	ldr	x9, [x9, _UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	orr	w1, w8, w9
	bl	_WREG32
	mov	w0, #20
	bl	_mdelay
LBB0_5:
	mov	w0, #0
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_6:
	ldr	w8, [x19]
Lloh24:
	adrp	x9, _AMD_PG_SUPPORT_UVD@GOTPAGE
Lloh25:
	ldr	x9, [x9, _AMD_PG_SUPPORT_UVD@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_10
; %bb.7:
	ldr	w8, [x19, #4]
	cbnz	w8, LBB0_10
; %bb.8:
Lloh27:
	adrp	x8, _ixCURRENT_PG_STATUS@GOTPAGE
Lloh28:
	ldr	x8, [x8, _ixCURRENT_PG_STATUS@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	bl	_RREG32_SMC
Lloh30:
	adrp	x8, _CURRENT_PG_STATUS__UVD_PG_STATUS_MASK@GOTPAGE
Lloh31:
	ldr	x8, [x8, _CURRENT_PG_STATUS__UVD_PG_STATUS_MASK@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_10
; %bb.9:
Lloh33:
	adrp	x8, _mmUVD_PGFSM_CONFIG@GOTPAGE
Lloh34:
	ldr	x8, [x8, _mmUVD_PGFSM_CONFIG@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
Lloh36:
	adrp	x8, _UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK@GOTPAGE
Lloh37:
	ldr	x8, [x8, _UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK@GOTPAGEOFF]
Lloh38:
	ldr	w8, [x8]
Lloh39:
	adrp	x9, _UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK@GOTPAGE
Lloh40:
	ldr	x9, [x9, _UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK@GOTPAGEOFF]
Lloh41:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh42:
	adrp	x9, _UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK@GOTPAGE
Lloh43:
	ldr	x9, [x9, _UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK@GOTPAGEOFF]
Lloh44:
	ldr	w9, [x9]
	orr	w1, w8, w9
	bl	_WREG32
	mov	w0, #30
	bl	_mdelay
LBB0_10:
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_uvd_v4_2_start
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_PG_STATE_GATE,4,2          ; @AMD_PG_STATE_GATE
	.comm	_AMD_PG_SUPPORT_UVD,4,2         ; @AMD_PG_SUPPORT_UVD
	.comm	_ixCURRENT_PG_STATUS,4,2        ; @ixCURRENT_PG_STATUS
	.comm	_CURRENT_PG_STATUS__UVD_PG_STATUS_MASK,4,2 ; @CURRENT_PG_STATUS__UVD_PG_STATUS_MASK
	.comm	_mmUVD_PGFSM_CONFIG,4,2         ; @mmUVD_PGFSM_CONFIG
	.comm	_UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK,4,2 ; @UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK
	.comm	_UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK,4,2 ; @UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK
	.comm	_UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK,4,2 ; @UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK
	.comm	_UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK,4,2 ; @UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK
	.no_dead_strip	_uvd_v4_2_set_powergating_state
.subsections_via_symbols
