	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r200_packet0_check             ## -- Begin function r200_packet0_check
	.p2align	4, 0x90
_r200_packet0_check:                    ## @r200_packet0_check
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %r12d
	movl	%edx, %r15d
	movq	%rsi, -56(%rbp)                 ## 8-byte Spill
	movq	%rdi, %rbx
	movq	8(%rdi), %r13
	movq	16(%rdi), %rax
	movq	%rax, -64(%rbp)                 ## 8-byte Spill
	movl	%edx, %esi
	callq	_radeon_get_ib_value
	movl	%eax, %r14d
	leal	-128(%r12), %eax
	cmpl	$112, %eax
	ja	LBB0_27
## %bb.1:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_2:
	movq	%r14, -72(%rbp)                 ## 8-byte Spill
	movq	%r13, %r14
	leaq	-48(%rbp), %rsi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_radeon_cs_packet_next_reloc
	testl	%eax, %eax
	je	LBB0_5
LBB0_3:
	movl	%eax, %r13d
	leaq	L_.str(%rip), %rdi
	movl	%r15d, %esi
	movl	%r12d, %edx
LBB0_4:
	xorl	%eax, %eax
	callq	_DRM_ERROR
	movq	%rbx, %rdi
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
	callq	_radeon_cs_dump_packet
	jmp	LBB0_82
LBB0_5:
	leal	76(%r12), %eax
	movzbl	%al, %eax
	imull	$171, %eax, %eax
	shrl	$12, %eax
	leal	(,%rax,8), %ecx
	leal	(%rcx,%rcx,2), %ecx
	negl	%ecx
	addl	%r12d, %ecx
	addl	$-180, %ecx
	shrl	$2, %ecx
	movq	32(%r14), %rdx
	leaq	(%rax,%rax,8), %rax
	movq	48(%rdx,%rax,8), %rax
	shlq	$4, %rcx
	movq	-72(%rbp), %rdi                 ## 8-byte Reload
	movl	%edi, -16(%rcx,%rax)
	movq	-48(%rbp), %rdx
	movl	4(%rdx), %esi
	addl	%edi, %esi
	movl	%r15d, %edi
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	movl	%esi, (%rbx,%rdi,4)
	movl	8(%rdx), %edx
	movl	%edx, -4(%rcx,%rax)
	movl	$1, 8(%r14)
	jmp	LBB0_81
LBB0_6:
	addl	$-168, %r12d
	shrl	$5, %r12d
	movq	_RADEON_TEX_USIZE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r14d, %eax
	incl	%eax
	movq	32(%r13), %rdx
	leaq	(%r12,%r12,8), %rsi
	movl	%eax, 4(%rdx,%rsi,8)
	movq	_RADEON_TEX_VSIZE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r14d, %eax
	movq	_RADEON_TEX_VSIZE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	incl	%eax
	movl	%eax, 8(%rdx,%rsi,8)
	jmp	LBB0_80
LBB0_7:
	addl	$-174, %r12d
	shrl	$5, %r12d
	addl	$32, %r14d
	movq	32(%r13), %rax
	leaq	(%r12,%r12,8), %rcx
	movl	%r14d, 64(%rax,%rcx,8)
	jmp	LBB0_80
LBB0_8:
	movq	%r13, -72(%rbp)                 ## 8-byte Spill
	leaq	-48(%rbp), %rsi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_radeon_cs_packet_next_reloc
	testl	%eax, %eax
	jne	LBB0_3
## %bb.9:
	addl	$-180, %r12d
	movl	$2863311531, %eax               ## imm = 0xAAAAAAAB
	imulq	%r12, %rax
	shrq	$36, %rax
	movq	_RADEON_CS_KEEP_TILING_FLAGS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	-48(%rbp), %rcx
	testl	%edx, (%rbx)
	je	LBB0_57
## %bb.10:
	movl	4(%rcx), %edx
	movq	-72(%rbp), %rbx                 ## 8-byte Reload
	jmp	LBB0_62
LBB0_11:
	addl	$-192, %r12d
	shrl	$5, %r12d
	movl	%r14d, %eax
	andl	$7, %eax
	movq	32(%r13), %rcx
	leaq	(%r12,%r12,8), %rdx
	movl	%eax, 24(%rcx,%rdx,8)
	shrl	$16, %r14d
	andl	$3, %r14d
	leaq	L_switch.table.r200_packet0_check.5(%rip), %rax
	movl	(%rax,%r14,4), %eax
	movl	%eax, 28(%rcx,%rdx,8)
	jmp	LBB0_80
LBB0_12:
	addl	$-198, %r12d
	shrl	$5, %r12d
	movq	_R200_TXFORMAT_NON_POWER2@GOTPCREL(%rip), %rcx
	movq	32(%r13), %rdx
	leaq	(%r12,%r12,8), %rsi
	leaq	(%rdx,%rsi,8), %rax
	addq	$32, %rax
	testl	%r14d, (%rcx)
	je	LBB0_20
## %bb.13:
	movl	$1, (%rax)
	jmp	LBB0_21
LBB0_14:
	addl	$-204, %r12d
	shrl	$5, %r12d
	movq	_R200_MAX_MIP_LEVEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	andl	%r14d, %edx
	movq	_R200_MAX_MIP_LEVEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarl	%cl, %edx
	movq	32(%r13), %rax
	leaq	(%r12,%r12,8), %rcx
	movl	%edx, 12(%rax,%rcx,8)
	movl	%r14d, %edx
	andl	$25165824, %edx                 ## imm = 0x1800000
	cmpl	$16777216, %edx                 ## imm = 0x1000000
	jne	LBB0_16
## %bb.15:
	movl	$0, 16(%rax,%rcx,8)
LBB0_16:
	andl	$402653184, %r14d               ## imm = 0x18000000
	cmpl	$268435456, %r14d               ## imm = 0x10000000
	jne	LBB0_80
## %bb.17:
	movl	$0, 20(%rax,%rcx,8)
	jmp	LBB0_80
LBB0_19:
	addl	$-240, %r12d
	movl	%r14d, %ecx
	andb	$15, %cl
	movl	$1, %esi
	shll	%cl, %esi
	movl	%r14d, %ecx
	shrb	$4, %cl
	movl	$1, %edi
	shll	%cl, %edi
	shrl	$5, %r12d
	movq	32(%r13), %rax
	movl	%r14d, %ecx
	shrl	$8, %ecx
	andb	$15, %cl
	movl	$1, %ebx
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %ebx
	leaq	(%r12,%r12,8), %rcx
	movq	48(%rax,%rcx,8), %rax
	movl	%r14d, %ecx
	shrl	$12, %ecx
	andb	$15, %cl
	movl	$1, %edx
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %edx
	movl	$1, %r8d
	movl	%esi, 4(%rax)
	movl	%r14d, %ecx
	shrl	$16, %ecx
	andb	$15, %cl
	movl	$1, %esi
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %esi
	movl	%edi, 8(%rax)
	movl	%ebx, 20(%rax)
	movl	%r14d, %ecx
	shrl	$20, %ecx
	andb	$15, %cl
	movl	$1, %edi
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %edi
	movl	%edx, 24(%rax)
	movl	%esi, 36(%rax)
	movl	%r14d, %ecx
	shrl	$24, %ecx
	andb	$15, %cl
	movl	$1, %edx
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %edx
	shrl	$28, %r14d
	movl	%r14d, %ecx
	shll	%cl, %r8d
	movl	%edi, 40(%rax)
	movl	%edx, 52(%rax)
	movl	%r8d, 56(%rax)
	jmp	LBB0_80
LBB0_20:
	movl	$0, (%rax)
	movq	_RADEON_TXFORMAT_WIDTH_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	%r14d, %eax
	sarl	%cl, %eax
	movq	_RADEON_TXFORMAT_WIDTH_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movl	$1, %edi
	movl	%eax, %ecx
	shll	%cl, %edi
	movl	%edi, 4(%rdx,%rsi,8)
	movq	_RADEON_TXFORMAT_HEIGHT_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	%r14d, %eax
	sarl	%cl, %eax
	movl	$1, %edi
	movq	_RADEON_TXFORMAT_HEIGHT_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movl	%eax, %ecx
	shll	%cl, %edi
	movl	%edi, 8(%rdx,%rsi,8)
LBB0_21:
	movq	_R200_TXFORMAT_LOOKUP_DISABLE@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_23
## %bb.22:
	movl	$1, 36(%rdx,%rsi,8)
LBB0_23:
	movq	_RADEON_TXFORMAT_FORMAT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r14d, %eax
	addl	$-141, %eax
	cmpl	$19, %eax
	ja	LBB0_25
## %bb.24:
	cltq
	leaq	l_switch.table.r200_packet0_check.6(%rip), %rcx
	movl	(%rcx,%rax,4), %ecx
	leaq	l_switch.table.r200_packet0_check.7(%rip), %rdi
	movq	(%rdi,%rax,8), %rax
	movl	%ecx, 40(%rdx,%rsi,8)
	movq	(%rax), %rax
	movq	%rax, 56(%rdx,%rsi,8)
LBB0_25:
	movl	%r14d, %ecx
	shrl	$16, %ecx
	andb	$15, %cl
	movl	$1, %eax
	movl	$1, %edi
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %edi
	shrl	$20, %r14d
	andb	$15, %r14b
	movl	%r14d, %ecx
	shll	%cl, %eax
	movq	48(%rdx,%rsi,8), %rcx
	movl	%edi, 68(%rcx)
	movl	%eax, 72(%rcx)
LBB0_80:
	movl	$1, 8(%r13)
LBB0_81:
	xorl	%r13d, %r13d
LBB0_82:
	movl	%r13d, %eax
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_26:
	movq	%rbx, %rdi
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
	movl	%r15d, %edx
	movl	%r12d, %ecx
	callq	_r100_reloc_pitch_offset
	movl	%eax, %r13d
	testl	%eax, %eax
	jne	LBB0_82
	jmp	LBB0_81
LBB0_27:
	cmpl	$8460, %r12d                    ## imm = 0x210C
	jne	LBB0_29
## %bb.28:
	andl	$16777215, %r14d                ## imm = 0xFFFFFF
	movl	%r14d, 28(%r13)
	jmp	LBB0_81
LBB0_29:
	leaq	L_.str.3(%rip), %rdi
	movl	%r12d, %esi
	movl	%r15d, %edx
	callq	_pr_err
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r13d, %r13d
	subl	(%rax), %r13d
	jmp	LBB0_82
LBB0_30:
	movl	%r14d, 24(%r13)
	jmp	LBB0_81
LBB0_31:
	shrl	$16, %r14d
	andl	$2047, %r14d                    ## imm = 0x7FF
	movl	%r14d, 12(%r13)
LBB0_32:
	movabsq	$4294967297, %rax               ## imm = 0x100000001
	movq	%rax, (%r13)
	jmp	LBB0_81
LBB0_33:
	andl	$15, %r14d
	cmpl	$11, %r14d
	ja	LBB0_36
## %bb.34:
	movl	$2621, %eax                     ## imm = 0xA3D
	btl	%r14d, %eax
	jae	LBB0_36
## %bb.35:
	movl	%r14d, %eax
	leaq	l_switch.table.r200_packet0_check.4(%rip), %rcx
	movl	(%rcx,%rax,4), %eax
	movl	%eax, 52(%r13)
LBB0_36:
	movl	$1, (%r13)
	jmp	LBB0_81
LBB0_37:
	leaq	-48(%rbp), %rsi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_radeon_cs_packet_next_reloc
	testl	%eax, %eax
	je	LBB0_63
## %bb.38:
	movl	%eax, %r13d
	leaq	L_.str(%rip), %rdi
	movl	%r15d, %esi
	movl	$132, %edx
	jmp	LBB0_4
LBB0_39:
	movq	_RADEON_DEPTHPITCH_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r14d, %eax
	movl	%eax, 48(%r13)
	movl	$1, (%r13)
	jmp	LBB0_81
LBB0_40:
	movq	%r14, %r12
	movq	%r13, %r14
	leaq	-48(%rbp), %rsi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_radeon_cs_packet_next_reloc
	testl	%eax, %eax
	je	LBB0_64
## %bb.41:
	movl	%eax, %r13d
	leaq	L_.str(%rip), %rdi
	movl	%r15d, %esi
	movl	$134, %edx
	jmp	LBB0_4
LBB0_42:
	movq	%r14, %r12
	movq	%r13, %r14
	leaq	-48(%rbp), %rsi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_radeon_cs_packet_next_reloc
	testl	%eax, %eax
	je	LBB0_65
## %bb.43:
	movl	%eax, %r13d
	leaq	L_.str(%rip), %rdi
	movl	%r15d, %esi
	movl	$135, %edx
	jmp	LBB0_4
LBB0_44:
	movq	%r14, %r12
	movq	%r13, %r14
	leaq	-48(%rbp), %rsi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_radeon_cs_packet_next_reloc
	testl	%eax, %eax
	je	LBB0_72
## %bb.45:
	movl	%eax, %r13d
	leaq	L_.str(%rip), %rdi
	movl	%r15d, %esi
	movl	$136, %edx
	jmp	LBB0_4
LBB0_46:
	movq	_RADEON_RB3D_COLOR_FORMAT_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	%r14d, %esi
	sarl	%cl, %esi
	andl	$31, %esi
	leal	-3(%rsi), %eax
	cmpl	$13, %eax
	jae	LBB0_48
## %bb.47:
	movl	$4987, %ecx                     ## imm = 0x137B
	btl	%eax, %ecx
	jb	LBB0_83
LBB0_48:
	leaq	L_.str.1(%rip), %rdi
	xorl	%r13d, %r13d
                                        ## kill: def $esi killed $esi killed $rsi
	xorl	%eax, %eax
	callq	_DRM_ERROR
LBB0_49:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	subl	(%rax), %r13d
	jmp	LBB0_82
LBB0_50:
	movl	20(%r13), %esi
	testl	%esi, %esi
	jle	LBB0_80
## %bb.51:
	sarl	$4, %r14d
	movq	32(%r13), %r8
	leaq	-1(%rsi), %rax
	movl	%esi, %ecx
	andl	$3, %ecx
	cmpq	$3, %rax
	jae	LBB0_75
## %bb.52:
	xorl	%eax, %eax
	jmp	LBB0_77
LBB0_53:
	movq	%rbx, %rdi
	callq	_r100_cs_packet_parse_vline
	testl	%eax, %eax
	je	LBB0_81
## %bb.54:
	movl	%eax, %r13d
	leaq	L_.str(%rip), %rdi
	movl	%r15d, %esi
	movl	$140, %edx
	jmp	LBB0_4
LBB0_55:
	movl	%r14d, %edi
	callq	_r200_get_vtx_size_1
	addl	%eax, 40(%r13)
	jmp	LBB0_81
LBB0_56:
	movl	%r14d, %edi
	callq	_r200_get_vtx_size_0
	movl	%eax, 40(%r13)
	jmp	LBB0_81
LBB0_57:
	movq	_RADEON_TILING_MACRO@GOTPCREL(%rip), %rdx
	movl	(%rcx), %esi
	movl	(%rdx), %edx
	andl	%esi, %edx
	je	LBB0_59
## %bb.58:
	movq	_R200_TXO_MACRO_TILE@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
LBB0_59:
	movq	_RADEON_TILING_MICRO@GOTPCREL(%rip), %rdi
	andl	(%rdi), %esi
	movq	-72(%rbp), %rbx                 ## 8-byte Reload
	je	LBB0_61
## %bb.60:
	movq	_R200_TXO_MICRO_TILE@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
LBB0_61:
	movl	4(%rcx), %edi
	andl	$-29, %r14d
	orl	%r14d, %edx
	orl	%esi, %edx
	movl	%edi, %r14d
LBB0_62:
	movq	-64(%rbp), %rsi                 ## 8-byte Reload
	addl	%edx, %r14d
	movl	%r15d, %edx
	movl	%r14d, (%rsi,%rdx,4)
	movl	8(%rcx), %ecx
	movq	32(%rbx), %rdx
	movl	%eax, %eax
	leaq	(%rax,%rax,8), %rax
	movl	%ecx, 68(%rdx,%rax,8)
	movl	$1, 8(%rbx)
	jmp	LBB0_81
LBB0_63:
	movq	-48(%rbp), %rax
	movl	4(%rax), %eax
	addl	%r14d, %eax
	jmp	LBB0_74
LBB0_64:
	movq	-48(%rbp), %rax
	movl	8(%rax), %ecx
	movl	%ecx, 56(%r14)
	movl	%r12d, 44(%r14)
	movl	$1, (%r14)
	jmp	LBB0_73
LBB0_65:
	movq	_RADEON_CS_KEEP_TILING_FLAGS@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%r12d, %eax
	testl	%ecx, (%rbx)
	movq	%r14, %rsi
	movq	%r12, %rdi
	jne	LBB0_71
## %bb.66:
	movq	-48(%rbp), %rax
	movl	(%rax), %ecx
	movq	_RADEON_TILING_MACRO@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%ecx, %eax
	je	LBB0_68
## %bb.67:
	movq	_RADEON_COLOR_TILE_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_68:
	movq	_RADEON_TILING_MICRO@GOTPCREL(%rip), %rdx
	andl	(%rdx), %ecx
	je	LBB0_70
## %bb.69:
	movq	_RADEON_COLOR_MICROTILE_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_70:
	movl	%edi, %edx
	andl	$-458753, %edx                  ## imm = 0xFFF8FFFF
	orl	%edx, %eax
	orl	%ecx, %eax
LBB0_71:
	movl	%r15d, %ecx
	movq	-64(%rbp), %rdx                 ## 8-byte Reload
	movl	%eax, (%rdx,%rcx,4)
	movq	_RADEON_COLORPITCH_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%edi, %eax
	movq	64(%rsi), %rcx
	movl	%eax, 4(%rcx)
	movl	$1, 4(%rsi)
	jmp	LBB0_81
LBB0_72:
	movq	-48(%rbp), %rax
	movl	8(%rax), %ecx
	movq	64(%r14), %rdx
	movl	%ecx, 12(%rdx)
	movl	%r12d, (%rdx)
	movl	$1, 4(%r14)
LBB0_73:
	movl	4(%rax), %eax
	addl	%r12d, %eax
LBB0_74:
	movl	%r15d, %ecx
	movq	-64(%rbp), %rdx                 ## 8-byte Reload
	movl	%eax, (%rdx,%rcx,4)
	jmp	LBB0_81
LBB0_75:
	andl	$-4, %esi
	xorl	%eax, %eax
	movq	%r8, %rdi
LBB0_76:                                ## =>This Inner Loop Header: Depth=1
	xorl	%ebx, %ebx
	btl	%eax, %r14d
	setb	%bl
	movl	%ebx, (%rdi)
	leal	1(%rax), %ebx
	movzbl	%bl, %ebx
	xorl	%edx, %edx
	btl	%ebx, %r14d
	setb	%dl
	movl	%edx, 72(%rdi)
	leal	2(%rax), %edx
	movzbl	%dl, %edx
	xorl	%ebx, %ebx
	btl	%edx, %r14d
	setb	%bl
	movl	%ebx, 144(%rdi)
	leal	3(%rax), %edx
	movzbl	%dl, %edx
	xorl	%ebx, %ebx
	btl	%edx, %r14d
	setb	%bl
	movl	%ebx, 216(%rdi)
	addq	$4, %rax
	addq	$288, %rdi                      ## imm = 0x120
	cmpq	%rsi, %rax
	jne	LBB0_76
LBB0_77:
	testq	%rcx, %rcx
	je	LBB0_80
## %bb.78:
	leaq	(%rax,%rax,8), %rdx
	leaq	(%r8,%rdx,8), %rdx
	shlq	$3, %rcx
	leaq	(%rcx,%rcx,8), %rcx
	xorl	%esi, %esi
LBB0_79:                                ## =>This Inner Loop Header: Depth=1
	xorl	%edi, %edi
	btl	%eax, %r14d
	setb	%dil
	movl	%edi, (%rdx,%rsi)
	addq	$72, %rsi
	incl	%eax
	cmpq	%rsi, %rcx
	jne	LBB0_79
	jmp	LBB0_80
LBB0_83:
	cltq
	leaq	l_switch.table.r200_packet0_check(%rip), %rcx
	movl	(%rcx,%rax,4), %eax
	movq	64(%r13), %rcx
	movl	%eax, 8(%rcx)
	movq	_RADEON_DEPTHXY_OFFSET_ENABLE@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_85
## %bb.84:
	leaq	L_.str.2(%rip), %rdi
	xorl	%r13d, %r13d
	xorl	%eax, %eax
	callq	_DRM_ERROR
	jmp	LBB0_49
LBB0_85:
	movq	_RADEON_Z_ENABLE@GOTPCREL(%rip), %rax
	xorl	%ecx, %ecx
	movl	(%rax), %eax
	andl	%r14d, %eax
	setne	%cl
	movl	%ecx, 16(%r13)
	jmp	LBB0_32
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_26, LBB0_26-LJTI0_0
.set L0_0_set_30, LBB0_30-LJTI0_0
.set L0_0_set_31, LBB0_31-LJTI0_0
.set L0_0_set_33, LBB0_33-LJTI0_0
.set L0_0_set_37, LBB0_37-LJTI0_0
.set L0_0_set_39, LBB0_39-LJTI0_0
.set L0_0_set_40, LBB0_40-LJTI0_0
.set L0_0_set_42, LBB0_42-LJTI0_0
.set L0_0_set_44, LBB0_44-LJTI0_0
.set L0_0_set_46, LBB0_46-LJTI0_0
.set L0_0_set_50, LBB0_50-LJTI0_0
.set L0_0_set_53, LBB0_53-LJTI0_0
.set L0_0_set_29, LBB0_29-LJTI0_0
.set L0_0_set_55, LBB0_55-LJTI0_0
.set L0_0_set_56, LBB0_56-LJTI0_0
.set L0_0_set_6, LBB0_6-LJTI0_0
.set L0_0_set_7, LBB0_7-LJTI0_0
.set L0_0_set_8, LBB0_8-LJTI0_0
.set L0_0_set_81, LBB0_81-LJTI0_0
.set L0_0_set_11, LBB0_11-LJTI0_0
.set L0_0_set_12, LBB0_12-LJTI0_0
.set L0_0_set_14, LBB0_14-LJTI0_0
.set L0_0_set_2, LBB0_2-LJTI0_0
.set L0_0_set_19, LBB0_19-LJTI0_0
LJTI0_0:
	.long	L0_0_set_26
	.long	L0_0_set_30
	.long	L0_0_set_31
	.long	L0_0_set_33
	.long	L0_0_set_37
	.long	L0_0_set_39
	.long	L0_0_set_40
	.long	L0_0_set_42
	.long	L0_0_set_44
	.long	L0_0_set_46
	.long	L0_0_set_50
	.long	L0_0_set_26
	.long	L0_0_set_53
	.long	L0_0_set_29
	.long	L0_0_set_29
	.long	L0_0_set_29
	.long	L0_0_set_29
	.long	L0_0_set_29
	.long	L0_0_set_29
	.long	L0_0_set_29
	.long	L0_0_set_29
	.long	L0_0_set_29
	.long	L0_0_set_29
	.long	L0_0_set_29
	.long	L0_0_set_29
	.long	L0_0_set_29
	.long	L0_0_set_29
	.long	L0_0_set_29
	.long	L0_0_set_29
	.long	L0_0_set_29
	.long	L0_0_set_29
	.long	L0_0_set_29
	.long	L0_0_set_29
	.long	L0_0_set_55
	.long	L0_0_set_56
	.long	L0_0_set_6
	.long	L0_0_set_6
	.long	L0_0_set_6
	.long	L0_0_set_6
	.long	L0_0_set_6
	.long	L0_0_set_6
	.long	L0_0_set_7
	.long	L0_0_set_7
	.long	L0_0_set_7
	.long	L0_0_set_7
	.long	L0_0_set_7
	.long	L0_0_set_7
	.long	L0_0_set_8
	.long	L0_0_set_8
	.long	L0_0_set_8
	.long	L0_0_set_8
	.long	L0_0_set_8
	.long	L0_0_set_8
	.long	L0_0_set_81
	.long	L0_0_set_81
	.long	L0_0_set_81
	.long	L0_0_set_81
	.long	L0_0_set_81
	.long	L0_0_set_81
	.long	L0_0_set_11
	.long	L0_0_set_11
	.long	L0_0_set_11
	.long	L0_0_set_11
	.long	L0_0_set_11
	.long	L0_0_set_11
	.long	L0_0_set_12
	.long	L0_0_set_12
	.long	L0_0_set_12
	.long	L0_0_set_12
	.long	L0_0_set_12
	.long	L0_0_set_12
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_14
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_19
	.long	L0_0_set_19
	.long	L0_0_set_19
	.long	L0_0_set_19
	.long	L0_0_set_19
	.long	L0_0_set_19
	.end_data_region
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"No reloc for ib[%d]=0x%04X\n"

	.comm	_RADEON_CS_KEEP_TILING_FLAGS,4,2 ## @RADEON_CS_KEEP_TILING_FLAGS
	.comm	_RADEON_TILING_MACRO,4,2        ## @RADEON_TILING_MACRO
	.comm	_R200_TXO_MACRO_TILE,4,2        ## @R200_TXO_MACRO_TILE
	.comm	_RADEON_TILING_MICRO,4,2        ## @RADEON_TILING_MICRO
	.comm	_R200_TXO_MICRO_TILE,4,2        ## @R200_TXO_MICRO_TILE
	.comm	_RADEON_COLOR_TILE_ENABLE,4,2   ## @RADEON_COLOR_TILE_ENABLE
	.comm	_RADEON_COLOR_MICROTILE_ENABLE,4,2 ## @RADEON_COLOR_MICROTILE_ENABLE
	.comm	_RADEON_COLORPITCH_MASK,4,2     ## @RADEON_COLORPITCH_MASK
	.comm	_RADEON_DEPTHPITCH_MASK,4,2     ## @RADEON_DEPTHPITCH_MASK
	.comm	_RADEON_RB3D_COLOR_FORMAT_SHIFT,4,2 ## @RADEON_RB3D_COLOR_FORMAT_SHIFT
L_.str.1:                               ## @.str.1
	.asciz	"Invalid color buffer format (%d) !\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_RADEON_DEPTHXY_OFFSET_ENABLE,4,2 ## @RADEON_DEPTHXY_OFFSET_ENABLE
L_.str.2:                               ## @.str.2
	.asciz	"No support for depth xy offset in kms\n"

	.comm	_RADEON_Z_ENABLE,4,2            ## @RADEON_Z_ENABLE
	.comm	_RADEON_TEX_USIZE_MASK,4,2      ## @RADEON_TEX_USIZE_MASK
	.comm	_RADEON_TEX_VSIZE_MASK,4,2      ## @RADEON_TEX_VSIZE_MASK
	.comm	_RADEON_TEX_VSIZE_SHIFT,4,2     ## @RADEON_TEX_VSIZE_SHIFT
	.comm	_R200_MAX_MIP_LEVEL_MASK,4,2    ## @R200_MAX_MIP_LEVEL_MASK
	.comm	_R200_MAX_MIP_LEVEL_SHIFT,4,2   ## @R200_MAX_MIP_LEVEL_SHIFT
	.comm	_R200_TXFORMAT_NON_POWER2,4,2   ## @R200_TXFORMAT_NON_POWER2
	.comm	_RADEON_TXFORMAT_WIDTH_SHIFT,4,2 ## @RADEON_TXFORMAT_WIDTH_SHIFT
	.comm	_RADEON_TXFORMAT_WIDTH_MASK,4,2 ## @RADEON_TXFORMAT_WIDTH_MASK
	.comm	_RADEON_TXFORMAT_HEIGHT_SHIFT,4,2 ## @RADEON_TXFORMAT_HEIGHT_SHIFT
	.comm	_RADEON_TXFORMAT_HEIGHT_MASK,4,2 ## @RADEON_TXFORMAT_HEIGHT_MASK
	.comm	_R200_TXFORMAT_LOOKUP_DISABLE,4,2 ## @R200_TXFORMAT_LOOKUP_DISABLE
	.comm	_RADEON_TXFORMAT_FORMAT_MASK,4,2 ## @RADEON_TXFORMAT_FORMAT_MASK
	.comm	_R100_TRACK_COMP_NONE,8,3       ## @R100_TRACK_COMP_NONE
	.comm	_R100_TRACK_COMP_DXT1,8,3       ## @R100_TRACK_COMP_DXT1
L_.str.3:                               ## @.str.3
	.asciz	"Forbidden register 0x%04X in cs at %d\n"

	.section	__TEXT,__const
	.p2align	2                               ## @switch.table.r200_packet0_check
l_switch.table.r200_packet0_check:
	.long	2                               ## 0x2
	.long	2                               ## 0x2
	.long	1                               ## 0x1
	.long	4                               ## 0x4
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	2                               ## 0x2

	.p2align	2                               ## @switch.table.r200_packet0_check.4
l_switch.table.r200_packet0_check.4:
	.long	2                               ## 0x2
	.long	2                               ## 0x2
	.long	4                               ## 0x4
	.long	4                               ## 0x4
	.long	4                               ## 0x4
	.long	4                               ## 0x4
	.long	2                               ## 0x2
	.long	2                               ## 0x2
	.long	2                               ## 0x2
	.long	4                               ## 0x4
	.long	2                               ## 0x2
	.long	4                               ## 0x4

	.section	__TEXT,__literal16,16byte_literals
	.p2align	2                               ## @switch.table.r200_packet0_check.5
L_switch.table.r200_packet0_check.5:
	.long	0                               ## 0x0
	.long	2                               ## 0x2
	.long	1                               ## 0x1
	.long	0                               ## 0x0

	.section	__TEXT,__const
	.p2align	2                               ## @switch.table.r200_packet0_check.6
l_switch.table.r200_packet0_check.6:
	.long	2                               ## 0x2
	.long	1                               ## 0x1
	.long	2                               ## 0x2
	.long	4                               ## 0x4
	.long	2                               ## 0x2
	.long	1                               ## 0x1
	.long	4                               ## 0x4
	.long	2                               ## 0x2
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	2                               ## 0x2
	.long	4                               ## 0x4
	.long	2                               ## 0x2
	.long	4                               ## 0x4
	.long	2                               ## 0x2
	.long	2                               ## 0x2
	.long	2                               ## 0x2
	.long	4                               ## 0x4

	.section	__DATA,__const
	.p2align	3                               ## @switch.table.r200_packet0_check.7
l_switch.table.r200_packet0_check.7:
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_DXT1
	.quad	_R100_TRACK_COMP_DXT1
	.quad	_R100_TRACK_COMP_DXT1
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3                               ; -- Begin function r200_packet0_check
lCPI0_0:
	.long	4294967288                      ; 0xfffffff8
	.long	4294967284                      ; 0xfffffff4
lCPI0_1:
	.long	4294967280                      ; 0xfffffff0
	.long	4294967276                      ; 0xffffffec
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_r200_packet0_check
	.p2align	2
_r200_packet0_check:                    ; @r200_packet0_check
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x24, x3
	mov	x20, x2
	mov	x21, x1
	mov	x22, x0
	ldp	x25, x26, [x0, #8]
	mov	x1, x2
	bl	_radeon_get_ib_value
	mov	x19, x0
	sub	w8, w24, #128
	cmp	w8, #112
	b.hi	LBB0_28
; %bb.1:
Lloh0:
	adrp	x9, lJTI0_0@PAGE
Lloh1:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_2
	ldrh	w11, [x9, x8, lsl #1]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_2:
	add	x1, sp, #24
	mov	x0, x22
	mov	w2, #0
	bl	_radeon_cs_packet_next_reloc
	cbz	w0, LBB0_6
; %bb.3:
	mov	x23, x0
                                        ; kill: def $w24 killed $w24 killed $x24 def $x24
LBB0_4:
                                        ; kill: def $w20 killed $w20 killed $x20 def $x20
	str	x24, [sp, #8]
LBB0_5:
	str	x20, [sp]
Lloh2:
	adrp	x0, l_.str@PAGE
Lloh3:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_ERROR
	mov	x0, x22
	mov	x1, x21
	bl	_radeon_cs_dump_packet
	b	LBB0_65
LBB0_6:
	add	w8, w24, #76
	and	w8, w8, #0xff
	mov	w9, #171
	mul	w8, w8, w9
	lsr	w8, w8, #12
	mov	w9, #-24
	madd	w9, w8, w9, w24
	sub	w9, w9, #180
	lsr	w9, w9, #2
	ldr	x10, [x25, #32]
	mov	w11, #72
	umaddl	x8, w8, w11, x10
	ldr	x8, [x8, #48]
	add	x8, x8, w9, uxtw #4
	stur	w19, [x8, #-16]
	ldr	x9, [sp, #24]
	ldr	w10, [x9, #4]
	add	w10, w10, w19
	str	w10, [x26, w20, uxtw #2]
	ldr	w9, [x9, #8]
	stur	w9, [x8, #-4]
	b	LBB0_63
LBB0_7:
	sub	w8, w24, #168
	lsr	w8, w8, #5
Lloh4:
	adrp	x9, _RADEON_TEX_USIZE_MASK@GOTPAGE
Lloh5:
	ldr	x9, [x9, _RADEON_TEX_USIZE_MASK@GOTPAGEOFF]
Lloh6:
	ldr	w9, [x9]
	and	w9, w9, w19
	add	w9, w9, #1
	ldr	x10, [x25, #32]
	mov	w11, #72
	umaddl	x8, w8, w11, x10
	str	w9, [x8, #4]
Lloh7:
	adrp	x9, _RADEON_TEX_VSIZE_MASK@GOTPAGE
Lloh8:
	ldr	x9, [x9, _RADEON_TEX_VSIZE_MASK@GOTPAGEOFF]
Lloh9:
	ldr	w9, [x9]
	and	w9, w9, w19
Lloh10:
	adrp	x10, _RADEON_TEX_VSIZE_SHIFT@GOTPAGE
Lloh11:
	ldr	x10, [x10, _RADEON_TEX_VSIZE_SHIFT@GOTPAGEOFF]
Lloh12:
	ldr	w10, [x10]
	asr	w9, w9, w10
	add	w9, w9, #1
	str	w9, [x8, #8]
	b	LBB0_63
LBB0_8:
	sub	w8, w24, #174
	lsr	w8, w8, #5
	add	w9, w19, #32
	ldr	x10, [x25, #32]
	mov	w11, #72
	umaddl	x8, w8, w11, x10
	str	w9, [x8, #64]
	b	LBB0_63
LBB0_9:
	add	x1, sp, #24
	mov	x0, x22
	mov	w2, #0
	bl	_radeon_cs_packet_next_reloc
	cbz	w0, LBB0_19
; %bb.10:
	mov	x23, x0
	b	LBB0_4
LBB0_11:
	sub	w8, w24, #192
	lsr	w8, w8, #5
	and	w9, w19, #0x7
	ldr	x10, [x25, #32]
	mov	w11, #72
	umaddl	x8, w8, w11, x10
	ubfx	w10, w19, #16, #2
Lloh13:
	adrp	x11, l_switch.table.r200_packet0_check.5@PAGE
Lloh14:
	add	x11, x11, l_switch.table.r200_packet0_check.5@PAGEOFF
	ldr	w10, [x11, w10, uxtw #2]
	stp	w9, w10, [x8, #24]
	b	LBB0_63
LBB0_12:
	sub	w8, w24, #198
	lsr	w8, w8, #5
Lloh15:
	adrp	x9, _R200_TXFORMAT_NON_POWER2@GOTPAGE
Lloh16:
	ldr	x9, [x9, _R200_TXFORMAT_NON_POWER2@GOTPAGEOFF]
Lloh17:
	ldr	w11, [x9]
	ldr	x9, [x25, #32]
	mov	w10, #72
	umaddl	x10, w8, w10, x9
	add	x10, x10, #32
	tst	w11, w19
	b.eq	LBB0_21
; %bb.13:
	mov	w11, #1
	str	w11, [x10]
	b	LBB0_22
LBB0_14:
	sub	w8, w24, #204
	lsr	w8, w8, #5
Lloh18:
	adrp	x9, _R200_MAX_MIP_LEVEL_MASK@GOTPAGE
Lloh19:
	ldr	x9, [x9, _R200_MAX_MIP_LEVEL_MASK@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	and	w9, w9, w19
Lloh21:
	adrp	x10, _R200_MAX_MIP_LEVEL_SHIFT@GOTPAGE
Lloh22:
	ldr	x10, [x10, _R200_MAX_MIP_LEVEL_SHIFT@GOTPAGEOFF]
Lloh23:
	ldr	w10, [x10]
	asr	w10, w9, w10
	ldr	x9, [x25, #32]
	mov	w11, #72
	umaddl	x11, w8, w11, x9
	str	w10, [x11, #12]
	and	w10, w19, #0x1800000
	mov	w11, #16777216
	cmp	w10, w11
	b.ne	LBB0_16
; %bb.15:
	mov	w10, #72
	madd	x10, x8, x10, x9
	str	wzr, [x10, #16]
LBB0_16:
	and	w10, w19, #0x18000000
	mov	w11, #268435456
	cmp	w10, w11
	b.ne	LBB0_63
; %bb.17:
	mov	w10, #72
	madd	x8, x8, x10, x9
	str	wzr, [x8, #20]
	b	LBB0_63
LBB0_18:
	sub	w8, w24, #240
	lsr	w8, w8, #5
	ldr	x9, [x25, #32]
	mov	w10, #72
	umaddl	x8, w8, w10, x9
	ldr	x8, [x8, #48]
	and	w9, w19, #0xf
	mov	w10, #1
	lsl	w9, w10, w9
	ubfx	w11, w19, #4, #4
	lsl	w11, w10, w11
	stp	w9, w11, [x8, #4]
	dup.2s	v0, w19
Lloh24:
	adrp	x9, lCPI0_0@PAGE
Lloh25:
	ldr	d1, [x9, lCPI0_0@PAGEOFF]
	ushl.2s	v1, v0, v1
	movi.2s	v2, #15
	and.8b	v1, v1, v2
	movi.2s	v3, #1
	ushl.2s	v1, v3, v1
	stur	d1, [x8, #20]
Lloh26:
	adrp	x9, lCPI0_1@PAGE
Lloh27:
	ldr	d1, [x9, lCPI0_1@PAGEOFF]
	ushl.2s	v0, v0, v1
	and.8b	v0, v0, v2
	ushl.2s	v0, v3, v0
	stur	d0, [x8, #36]
	ubfx	w9, w19, #24, #4
	lsl	w9, w10, w9
	lsr	w11, w19, #28
	lsl	w11, w10, w11
	stp	w9, w11, [x8, #52]
	str	w10, [x25, #8]
	b	LBB0_64
LBB0_19:
	sub	w8, w24, #180
	mov	w9, #43691
	movk	w9, #43690, lsl #16
	umull	x8, w8, w9
	lsr	x8, x8, #36
	ldr	w10, [x22]
Lloh28:
	adrp	x9, _RADEON_CS_KEEP_TILING_FLAGS@GOTPAGE
Lloh29:
	ldr	x9, [x9, _RADEON_CS_KEEP_TILING_FLAGS@GOTPAGEOFF]
Lloh30:
	ldr	w11, [x9]
	ldr	x9, [sp, #24]
	tst	w11, w10
	b.eq	LBB0_61
; %bb.20:
	ldr	w10, [x9, #4]
	b	LBB0_62
LBB0_21:
	str	wzr, [x10]
Lloh31:
	adrp	x10, _RADEON_TXFORMAT_WIDTH_SHIFT@GOTPAGE
Lloh32:
	ldr	x10, [x10, _RADEON_TXFORMAT_WIDTH_SHIFT@GOTPAGEOFF]
Lloh33:
	ldr	w10, [x10]
Lloh34:
	adrp	x11, _RADEON_TXFORMAT_WIDTH_MASK@GOTPAGE
Lloh35:
	ldr	x11, [x11, _RADEON_TXFORMAT_WIDTH_MASK@GOTPAGEOFF]
	asr	w10, w19, w10
Lloh36:
	ldr	w11, [x11]
	and	w10, w10, w11
	mov	w11, #1
	lsl	w10, w11, w10
	mov	w12, #72
	madd	x12, x8, x12, x9
	str	w10, [x12, #4]
Lloh37:
	adrp	x10, _RADEON_TXFORMAT_HEIGHT_SHIFT@GOTPAGE
Lloh38:
	ldr	x10, [x10, _RADEON_TXFORMAT_HEIGHT_SHIFT@GOTPAGEOFF]
Lloh39:
	ldr	w10, [x10]
	asr	w10, w19, w10
Lloh40:
	adrp	x13, _RADEON_TXFORMAT_HEIGHT_MASK@GOTPAGE
Lloh41:
	ldr	x13, [x13, _RADEON_TXFORMAT_HEIGHT_MASK@GOTPAGEOFF]
Lloh42:
	ldr	w13, [x13]
	and	w10, w10, w13
	lsl	w10, w11, w10
	str	w10, [x12, #8]
LBB0_22:
Lloh43:
	adrp	x10, _R200_TXFORMAT_LOOKUP_DISABLE@GOTPAGE
Lloh44:
	ldr	x10, [x10, _R200_TXFORMAT_LOOKUP_DISABLE@GOTPAGEOFF]
Lloh45:
	ldr	w10, [x10]
	tst	w10, w19
	b.eq	LBB0_24
; %bb.23:
	mov	w10, #72
	madd	x10, x8, x10, x9
	mov	w11, #1
	str	w11, [x10, #36]
LBB0_24:
Lloh46:
	adrp	x10, _RADEON_TXFORMAT_FORMAT_MASK@GOTPAGE
Lloh47:
	ldr	x10, [x10, _RADEON_TXFORMAT_FORMAT_MASK@GOTPAGEOFF]
Lloh48:
	ldr	w10, [x10]
	and	w10, w10, w19
	sub	w10, w10, #141
	cmp	w10, #19
	b.hi	LBB0_26
; %bb.25:
Lloh49:
	adrp	x11, l_switch.table.r200_packet0_check.6@PAGE
Lloh50:
	add	x11, x11, l_switch.table.r200_packet0_check.6@PAGEOFF
	ldr	w11, [x11, w10, sxtw #2]
Lloh51:
	adrp	x12, l_switch.table.r200_packet0_check.7@PAGE
Lloh52:
	add	x12, x12, l_switch.table.r200_packet0_check.7@PAGEOFF
	ldr	x10, [x12, w10, sxtw #3]
	mov	w12, #72
	madd	x12, x8, x12, x9
	str	w11, [x12, #40]
	ldr	x10, [x10]
	str	x10, [x12, #56]
LBB0_26:
	dup.2s	v0, w19
Lloh53:
	adrp	x10, lCPI0_1@PAGE
Lloh54:
	ldr	d1, [x10, lCPI0_1@PAGEOFF]
	ushl.2s	v0, v0, v1
	mov	w10, #72
	madd	x8, x8, x10, x9
	ldr	x8, [x8, #48]
	movi.2s	v1, #15
	and.8b	v0, v0, v1
	movi.2s	v1, #1
	ushl.2s	v0, v1, v0
	stur	d0, [x8, #68]
	b	LBB0_63
LBB0_27:
	mov	x0, x22
	mov	x1, x21
	mov	x2, x20
	mov	x3, x24
	bl	_r100_reloc_pitch_offset
	mov	x23, x0
	cbnz	w0, LBB0_65
	b	LBB0_64
LBB0_28:
	mov	w8, #8460
	cmp	w24, w8
	b.ne	LBB0_30
; %bb.29:
	and	w8, w19, #0xffffff
	str	w8, [x25, #28]
	b	LBB0_64
LBB0_30:
Lloh55:
	adrp	x0, l_.str.3@PAGE
Lloh56:
	add	x0, x0, l_.str.3@PAGEOFF
	mov	x1, x24
	mov	x2, x20
	bl	_pr_err
	b	LBB0_52
LBB0_31:
	str	w19, [x25, #24]
	b	LBB0_64
LBB0_32:
	ubfx	w8, w19, #16, #11
	str	w8, [x25, #12]
LBB0_33:
	movi.2s	v0, #1
	str	d0, [x25]
	b	LBB0_64
LBB0_34:
	and	w8, w19, #0xf
	cmp	w8, #11
	b.hi	LBB0_40
; %bb.35:
	mov	w9, #2621
	lsr	w9, w9, w8
	tbz	w9, #0, LBB0_40
; %bb.36:
Lloh57:
	adrp	x9, l_switch.table.r200_packet0_check.4@PAGE
Lloh58:
	add	x9, x9, l_switch.table.r200_packet0_check.4@PAGEOFF
	ldr	w8, [x9, w8, uxtw #2]
	str	w8, [x25, #52]
	b	LBB0_40
LBB0_37:
	add	x1, sp, #24
	mov	x0, x22
	mov	w2, #0
	bl	_radeon_cs_packet_next_reloc
	cbz	w0, LBB0_66
; %bb.38:
	mov	x23, x0
	mov	w8, #132
	b	LBB0_47
LBB0_39:
Lloh59:
	adrp	x8, _RADEON_DEPTHPITCH_MASK@GOTPAGE
Lloh60:
	ldr	x8, [x8, _RADEON_DEPTHPITCH_MASK@GOTPAGEOFF]
Lloh61:
	ldr	w8, [x8]
	and	w8, w8, w19
	str	w8, [x25, #48]
LBB0_40:
	mov	w8, #1
	str	w8, [x25]
	b	LBB0_64
LBB0_41:
	add	x1, sp, #24
	mov	x0, x22
	mov	w2, #0
	bl	_radeon_cs_packet_next_reloc
	cbz	w0, LBB0_67
; %bb.42:
	mov	x23, x0
	mov	w8, #134
	b	LBB0_47
LBB0_43:
	add	x1, sp, #24
	mov	x0, x22
	mov	w2, #0
	bl	_radeon_cs_packet_next_reloc
	cbz	w0, LBB0_68
; %bb.44:
	mov	x23, x0
	mov	w8, #135
	b	LBB0_47
LBB0_45:
	add	x1, sp, #24
	mov	x0, x22
	mov	w2, #0
	bl	_radeon_cs_packet_next_reloc
	cbz	w0, LBB0_71
; %bb.46:
	mov	x23, x0
	mov	w8, #136
LBB0_47:
                                        ; kill: def $w20 killed $w20 killed $x20 def $x20
	b	LBB0_58
LBB0_48:
Lloh62:
	adrp	x8, _RADEON_RB3D_COLOR_FORMAT_SHIFT@GOTPAGE
Lloh63:
	ldr	x8, [x8, _RADEON_RB3D_COLOR_FORMAT_SHIFT@GOTPAGEOFF]
Lloh64:
	ldr	w8, [x8]
	asr	w8, w19, w8
	and	x8, x8, #0x1f
	sub	x9, x8, #3
	cmp	w9, #13
	b.hs	LBB0_50
; %bb.49:
	mov	w10, #4987
	lsr	w10, w10, w9
	tbnz	w10, #0, LBB0_78
LBB0_50:
                                        ; kill: def $w8 killed $w8 killed $x8 def $x8
	str	x8, [sp]
Lloh65:
	adrp	x0, l_.str.1@PAGE
Lloh66:
	add	x0, x0, l_.str.1@PAGEOFF
LBB0_51:
	bl	_DRM_ERROR
LBB0_52:
Lloh67:
	adrp	x8, _EINVAL@GOTPAGE
Lloh68:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh69:
	ldr	w8, [x8]
	neg	w23, w8
	b	LBB0_65
LBB0_53:
	ldr	w8, [x25, #20]
	cmp	w8, #1
	b.lt	LBB0_63
; %bb.54:
	asr	w9, w19, #4
	ldr	x11, [x25, #32]
	cmp	w8, #4
	b.hs	LBB0_73
; %bb.55:
	mov	x10, #0
	b	LBB0_76
LBB0_56:
	mov	x0, x22
	bl	_r100_cs_packet_parse_vline
	cbz	w0, LBB0_64
; %bb.57:
	mov	x23, x0
	mov	w8, #140
LBB0_58:
	str	x8, [sp, #8]
	b	LBB0_5
LBB0_59:
	mov	x0, x19
	bl	_r200_get_vtx_size_1
	ldr	w8, [x25, #40]
	add	w8, w8, w0
	str	w8, [x25, #40]
	b	LBB0_64
LBB0_60:
	mov	x0, x19
	bl	_r200_get_vtx_size_0
	str	w0, [x25, #40]
	b	LBB0_64
LBB0_61:
Lloh70:
	adrp	x10, _RADEON_TILING_MACRO@GOTPAGE
Lloh71:
	ldr	x10, [x10, _RADEON_TILING_MACRO@GOTPAGEOFF]
Lloh72:
	ldr	w10, [x10]
Lloh73:
	adrp	x11, _R200_TXO_MACRO_TILE@GOTPAGE
Lloh74:
	ldr	x11, [x11, _R200_TXO_MACRO_TILE@GOTPAGEOFF]
Lloh75:
	ldr	w11, [x11]
	and	w12, w19, #0xffffffe3
	ldp	w13, w19, [x9]
	tst	w10, w13
	csel	w10, wzr, w11, eq
Lloh76:
	adrp	x11, _RADEON_TILING_MICRO@GOTPAGE
Lloh77:
	ldr	x11, [x11, _RADEON_TILING_MICRO@GOTPAGEOFF]
Lloh78:
	ldr	w11, [x11]
	tst	w11, w13
Lloh79:
	adrp	x11, _R200_TXO_MICRO_TILE@GOTPAGE
Lloh80:
	ldr	x11, [x11, _R200_TXO_MICRO_TILE@GOTPAGEOFF]
Lloh81:
	ldr	w11, [x11]
	csel	w11, wzr, w11, eq
	orr	w10, w10, w12
	orr	w10, w10, w11
LBB0_62:
	add	w10, w10, w19
	str	w10, [x26, w20, uxtw #2]
	ldr	w9, [x9, #8]
	ldr	x10, [x25, #32]
	mov	w11, #72
	umaddl	x8, w8, w11, x10
	str	w9, [x8, #68]
LBB0_63:
	mov	w8, #1
	str	w8, [x25, #8]
LBB0_64:
	mov	w23, #0
LBB0_65:
	mov	x0, x23
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
LBB0_66:
	ldr	x8, [sp, #24]
	ldr	w8, [x8, #4]
	b	LBB0_72
LBB0_67:
	ldr	x8, [sp, #24]
	ldp	w8, w9, [x8, #4]
	str	w9, [x25, #56]
	str	w19, [x25, #44]
	mov	w9, #1
	str	w9, [x25]
	b	LBB0_72
LBB0_68:
	ldr	w9, [x22]
Lloh82:
	adrp	x8, _RADEON_CS_KEEP_TILING_FLAGS@GOTPAGE
Lloh83:
	ldr	x8, [x8, _RADEON_CS_KEEP_TILING_FLAGS@GOTPAGEOFF]
Lloh84:
	ldr	w10, [x8]
	mov	x8, x19
	tst	w10, w9
	b.ne	LBB0_70
; %bb.69:
	ldr	x8, [sp, #24]
Lloh85:
	adrp	x9, _RADEON_TILING_MACRO@GOTPAGE
Lloh86:
	ldr	x9, [x9, _RADEON_TILING_MACRO@GOTPAGEOFF]
	ldr	w8, [x8]
Lloh87:
	ldr	w9, [x9]
Lloh88:
	adrp	x10, _RADEON_COLOR_TILE_ENABLE@GOTPAGE
Lloh89:
	ldr	x10, [x10, _RADEON_COLOR_TILE_ENABLE@GOTPAGEOFF]
Lloh90:
	ldr	w10, [x10]
	tst	w9, w8
	csel	w9, wzr, w10, eq
Lloh91:
	adrp	x10, _RADEON_TILING_MICRO@GOTPAGE
Lloh92:
	ldr	x10, [x10, _RADEON_TILING_MICRO@GOTPAGEOFF]
Lloh93:
	ldr	w10, [x10]
Lloh94:
	adrp	x11, _RADEON_COLOR_MICROTILE_ENABLE@GOTPAGE
Lloh95:
	ldr	x11, [x11, _RADEON_COLOR_MICROTILE_ENABLE@GOTPAGEOFF]
Lloh96:
	ldr	w11, [x11]
	tst	w10, w8
	csel	w8, wzr, w11, eq
	and	w10, w19, #0xfff8ffff
	orr	w9, w9, w10
	orr	w8, w9, w8
LBB0_70:
	str	w8, [x26, w20, uxtw #2]
Lloh97:
	adrp	x8, _RADEON_COLORPITCH_MASK@GOTPAGE
Lloh98:
	ldr	x8, [x8, _RADEON_COLORPITCH_MASK@GOTPAGEOFF]
Lloh99:
	ldr	w8, [x8]
	and	w8, w8, w19
	ldr	x9, [x25, #64]
	str	w8, [x9, #4]
	mov	w8, #1
	str	w8, [x25, #4]
	b	LBB0_64
LBB0_71:
	ldr	x8, [sp, #24]
	ldr	x9, [x25, #64]
	ldp	w8, w10, [x8, #4]
	str	w10, [x9, #12]
	str	w19, [x9]
	mov	w9, #1
	str	w9, [x25, #4]
LBB0_72:
	add	w8, w8, w19
	str	w8, [x26, w20, uxtw #2]
	b	LBB0_64
LBB0_73:
	mov	x12, #0
	and	x10, x8, #0xfffffffc
	add	x13, x11, #144
LBB0_74:                                ; =>This Inner Loop Header: Depth=1
	add	w14, w12, #1
	add	w15, w12, #2
	add	w16, w12, #3
	lsr	w17, w9, w12
	lsr	w14, w9, w14
	lsr	w15, w9, w15
	lsr	w16, w9, w16
	and	w17, w17, #0x1
	and	w14, w14, #0x1
	and	w15, w15, #0x1
	and	w16, w16, #0x1
	stur	w17, [x13, #-144]
	stur	w14, [x13, #-72]
	str	w15, [x13]
	str	w16, [x13, #72]
	add	x12, x12, #4
	add	x13, x13, #288
	cmp	x10, x12
	b.ne	LBB0_74
; %bb.75:
	cmp	x10, x8
	b.eq	LBB0_63
LBB0_76:
	mov	w12, #72
	madd	x11, x10, x12, x11
LBB0_77:                                ; =>This Inner Loop Header: Depth=1
	lsr	w12, w9, w10
	and	w12, w12, #0x1
	str	w12, [x11], #72
	add	x10, x10, #1
	cmp	x8, x10
	b.ne	LBB0_77
	b	LBB0_63
LBB0_78:
Lloh100:
	adrp	x8, l_switch.table.r200_packet0_check@PAGE
Lloh101:
	add	x8, x8, l_switch.table.r200_packet0_check@PAGEOFF
	ldr	w8, [x8, x9, lsl #2]
	ldr	x9, [x25, #64]
	str	w8, [x9, #8]
Lloh102:
	adrp	x8, _RADEON_DEPTHXY_OFFSET_ENABLE@GOTPAGE
Lloh103:
	ldr	x8, [x8, _RADEON_DEPTHXY_OFFSET_ENABLE@GOTPAGEOFF]
Lloh104:
	ldr	w8, [x8]
	tst	w8, w19
	b.eq	LBB0_80
; %bb.79:
Lloh105:
	adrp	x0, l_.str.2@PAGE
Lloh106:
	add	x0, x0, l_.str.2@PAGEOFF
	b	LBB0_51
LBB0_80:
Lloh107:
	adrp	x8, _RADEON_Z_ENABLE@GOTPAGE
Lloh108:
	ldr	x8, [x8, _RADEON_Z_ENABLE@GOTPAGEOFF]
Lloh109:
	ldr	w8, [x8]
	tst	w8, w19
	cset	w8, ne
	str	w8, [x25, #16]
	b	LBB0_33
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpAdd	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdr	Lloh26, Lloh27
	.loh AdrpAdrp	Lloh24, Lloh26
	.loh AdrpLdr	Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpAdd	Lloh51, Lloh52
	.loh AdrpAdd	Lloh49, Lloh50
	.loh AdrpLdr	Lloh53, Lloh54
	.loh AdrpAdd	Lloh55, Lloh56
	.loh AdrpAdd	Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpAdd	Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpAdd	Lloh100, Lloh101
	.loh AdrpAdd	Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.cfi_endproc
	.section	__TEXT,__const
	.p2align	1
lJTI0_0:
	.short	(LBB0_27-LBB0_2)>>2
	.short	(LBB0_31-LBB0_2)>>2
	.short	(LBB0_32-LBB0_2)>>2
	.short	(LBB0_34-LBB0_2)>>2
	.short	(LBB0_37-LBB0_2)>>2
	.short	(LBB0_39-LBB0_2)>>2
	.short	(LBB0_41-LBB0_2)>>2
	.short	(LBB0_43-LBB0_2)>>2
	.short	(LBB0_45-LBB0_2)>>2
	.short	(LBB0_48-LBB0_2)>>2
	.short	(LBB0_53-LBB0_2)>>2
	.short	(LBB0_27-LBB0_2)>>2
	.short	(LBB0_56-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_59-LBB0_2)>>2
	.short	(LBB0_60-LBB0_2)>>2
	.short	(LBB0_7-LBB0_2)>>2
	.short	(LBB0_7-LBB0_2)>>2
	.short	(LBB0_7-LBB0_2)>>2
	.short	(LBB0_7-LBB0_2)>>2
	.short	(LBB0_7-LBB0_2)>>2
	.short	(LBB0_7-LBB0_2)>>2
	.short	(LBB0_8-LBB0_2)>>2
	.short	(LBB0_8-LBB0_2)>>2
	.short	(LBB0_8-LBB0_2)>>2
	.short	(LBB0_8-LBB0_2)>>2
	.short	(LBB0_8-LBB0_2)>>2
	.short	(LBB0_8-LBB0_2)>>2
	.short	(LBB0_9-LBB0_2)>>2
	.short	(LBB0_9-LBB0_2)>>2
	.short	(LBB0_9-LBB0_2)>>2
	.short	(LBB0_9-LBB0_2)>>2
	.short	(LBB0_9-LBB0_2)>>2
	.short	(LBB0_9-LBB0_2)>>2
	.short	(LBB0_64-LBB0_2)>>2
	.short	(LBB0_64-LBB0_2)>>2
	.short	(LBB0_64-LBB0_2)>>2
	.short	(LBB0_64-LBB0_2)>>2
	.short	(LBB0_64-LBB0_2)>>2
	.short	(LBB0_64-LBB0_2)>>2
	.short	(LBB0_11-LBB0_2)>>2
	.short	(LBB0_11-LBB0_2)>>2
	.short	(LBB0_11-LBB0_2)>>2
	.short	(LBB0_11-LBB0_2)>>2
	.short	(LBB0_11-LBB0_2)>>2
	.short	(LBB0_11-LBB0_2)>>2
	.short	(LBB0_12-LBB0_2)>>2
	.short	(LBB0_12-LBB0_2)>>2
	.short	(LBB0_12-LBB0_2)>>2
	.short	(LBB0_12-LBB0_2)>>2
	.short	(LBB0_12-LBB0_2)>>2
	.short	(LBB0_12-LBB0_2)>>2
	.short	(LBB0_14-LBB0_2)>>2
	.short	(LBB0_14-LBB0_2)>>2
	.short	(LBB0_14-LBB0_2)>>2
	.short	(LBB0_14-LBB0_2)>>2
	.short	(LBB0_14-LBB0_2)>>2
	.short	(LBB0_14-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_18-LBB0_2)>>2
	.short	(LBB0_18-LBB0_2)>>2
	.short	(LBB0_18-LBB0_2)>>2
	.short	(LBB0_18-LBB0_2)>>2
	.short	(LBB0_18-LBB0_2)>>2
	.short	(LBB0_18-LBB0_2)>>2
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"No reloc for ib[%d]=0x%04X\n"

	.comm	_RADEON_CS_KEEP_TILING_FLAGS,4,2 ; @RADEON_CS_KEEP_TILING_FLAGS
	.comm	_RADEON_TILING_MACRO,4,2        ; @RADEON_TILING_MACRO
	.comm	_R200_TXO_MACRO_TILE,4,2        ; @R200_TXO_MACRO_TILE
	.comm	_RADEON_TILING_MICRO,4,2        ; @RADEON_TILING_MICRO
	.comm	_R200_TXO_MICRO_TILE,4,2        ; @R200_TXO_MICRO_TILE
	.comm	_RADEON_COLOR_TILE_ENABLE,4,2   ; @RADEON_COLOR_TILE_ENABLE
	.comm	_RADEON_COLOR_MICROTILE_ENABLE,4,2 ; @RADEON_COLOR_MICROTILE_ENABLE
	.comm	_RADEON_COLORPITCH_MASK,4,2     ; @RADEON_COLORPITCH_MASK
	.comm	_RADEON_DEPTHPITCH_MASK,4,2     ; @RADEON_DEPTHPITCH_MASK
	.comm	_RADEON_RB3D_COLOR_FORMAT_SHIFT,4,2 ; @RADEON_RB3D_COLOR_FORMAT_SHIFT
l_.str.1:                               ; @.str.1
	.asciz	"Invalid color buffer format (%d) !\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_RADEON_DEPTHXY_OFFSET_ENABLE,4,2 ; @RADEON_DEPTHXY_OFFSET_ENABLE
l_.str.2:                               ; @.str.2
	.asciz	"No support for depth xy offset in kms\n"

	.comm	_RADEON_Z_ENABLE,4,2            ; @RADEON_Z_ENABLE
	.comm	_RADEON_TEX_USIZE_MASK,4,2      ; @RADEON_TEX_USIZE_MASK
	.comm	_RADEON_TEX_VSIZE_MASK,4,2      ; @RADEON_TEX_VSIZE_MASK
	.comm	_RADEON_TEX_VSIZE_SHIFT,4,2     ; @RADEON_TEX_VSIZE_SHIFT
	.comm	_R200_MAX_MIP_LEVEL_MASK,4,2    ; @R200_MAX_MIP_LEVEL_MASK
	.comm	_R200_MAX_MIP_LEVEL_SHIFT,4,2   ; @R200_MAX_MIP_LEVEL_SHIFT
	.comm	_R200_TXFORMAT_NON_POWER2,4,2   ; @R200_TXFORMAT_NON_POWER2
	.comm	_RADEON_TXFORMAT_WIDTH_SHIFT,4,2 ; @RADEON_TXFORMAT_WIDTH_SHIFT
	.comm	_RADEON_TXFORMAT_WIDTH_MASK,4,2 ; @RADEON_TXFORMAT_WIDTH_MASK
	.comm	_RADEON_TXFORMAT_HEIGHT_SHIFT,4,2 ; @RADEON_TXFORMAT_HEIGHT_SHIFT
	.comm	_RADEON_TXFORMAT_HEIGHT_MASK,4,2 ; @RADEON_TXFORMAT_HEIGHT_MASK
	.comm	_R200_TXFORMAT_LOOKUP_DISABLE,4,2 ; @R200_TXFORMAT_LOOKUP_DISABLE
	.comm	_RADEON_TXFORMAT_FORMAT_MASK,4,2 ; @RADEON_TXFORMAT_FORMAT_MASK
	.comm	_R100_TRACK_COMP_NONE,8,3       ; @R100_TRACK_COMP_NONE
	.comm	_R100_TRACK_COMP_DXT1,8,3       ; @R100_TRACK_COMP_DXT1
l_.str.3:                               ; @.str.3
	.asciz	"Forbidden register 0x%04X in cs at %d\n"

	.section	__TEXT,__const
	.p2align	2                               ; @switch.table.r200_packet0_check
l_switch.table.r200_packet0_check:
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	4                               ; 0x4
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	2                               ; 0x2

	.p2align	2                               ; @switch.table.r200_packet0_check.4
l_switch.table.r200_packet0_check.4:
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	4                               ; 0x4
	.long	4                               ; 0x4
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	4                               ; 0x4

	.section	__TEXT,__literal16,16byte_literals
	.p2align	2                               ; @switch.table.r200_packet0_check.5
l_switch.table.r200_packet0_check.5:
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	0                               ; 0x0

	.section	__TEXT,__const
	.p2align	2                               ; @switch.table.r200_packet0_check.6
l_switch.table.r200_packet0_check.6:
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	4                               ; 0x4

	.section	__DATA,__const
	.p2align	3                               ; @switch.table.r200_packet0_check.7
l_switch.table.r200_packet0_check.7:
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_DXT1
	.quad	_R100_TRACK_COMP_DXT1
	.quad	_R100_TRACK_COMP_DXT1
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE
	.quad	_R100_TRACK_COMP_NONE

.subsections_via_symbols
