	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vi_set_vce_clocks
_vi_set_vce_clocks:                     ## @vi_set_vce_clocks
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rdi)
	je	LBB0_2
## %bb.1:
	movq	_CG_ECLK_CNTL__ECLK_DIVIDER_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	$65536, %r12d                   ## imm = 0x10000
	movq	_ixGNB_CLK3_STATUS@GOTPCREL(%rip), %rax
	movq	_ixGNB_CLK3_DFS_CNTL@GOTPCREL(%rip), %rcx
	jmp	LBB0_3
LBB0_2:
	movq	_CG_ECLK_STATUS__ECLK_STATUS_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	_CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK@GOTPCREL(%rip), %rax
	movq	_CG_ECLK_CNTL__ECLK_DIVIDER_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r14d
	orl	(%rax), %r14d
	movq	_ixCG_ECLK_STATUS@GOTPCREL(%rip), %rax
	movq	_ixCG_ECLK_CNTL@GOTPCREL(%rip), %rcx
LBB0_3:
	movl	(%rax), %r13d
	movl	(%rcx), %r15d
	movq	_COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-48(%rbp), %r8
	xorl	%ecx, %ecx
	callq	_amdgpu_atombios_get_clock_dividers
	testl	%eax, %eax
	jne	LBB0_12
## %bb.4:
	movl	$100, %ebx
	.p2align	4, 0x90
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	movl	%r13d, %edi
	callq	_RREG32_SMC
	testl	%r12d, %eax
	jne	LBB0_7
## %bb.6:                               ##   in Loop: Header=BB0_5 Depth=1
	movl	$10, %edi
	callq	_mdelay
	decl	%ebx
	jne	LBB0_5
	jmp	LBB0_11
LBB0_7:
	movl	%r15d, %edi
	callq	_RREG32_SMC
	notl	%r14d
	andl	%eax, %r14d
	orl	-48(%rbp), %r14d
	movl	%r15d, %edi
	movl	%r14d, %esi
	callq	_WREG32_SMC
	movl	$100, %ebx
	.p2align	4, 0x90
LBB0_8:                                 ## =>This Inner Loop Header: Depth=1
	movl	%r13d, %edi
	callq	_RREG32_SMC
	testl	%r12d, %eax
	jne	LBB0_9
## %bb.10:                              ##   in Loop: Header=BB0_8 Depth=1
	movl	$10, %edi
	callq	_mdelay
	decl	%ebx
	jne	LBB0_8
LBB0_11:
	movq	_ETIMEDOUT@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_12
LBB0_9:
	xorl	%eax, %eax
LBB0_12:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_ixGNB_CLK3_DFS_CNTL,4,2        ## @ixGNB_CLK3_DFS_CNTL
	.comm	_ixGNB_CLK3_STATUS,4,2          ## @ixGNB_CLK3_STATUS
	.comm	_CG_ECLK_CNTL__ECLK_DIVIDER_MASK,4,2 ## @CG_ECLK_CNTL__ECLK_DIVIDER_MASK
	.comm	_ixCG_ECLK_CNTL,4,2             ## @ixCG_ECLK_CNTL
	.comm	_ixCG_ECLK_STATUS,4,2           ## @ixCG_ECLK_STATUS
	.comm	_CG_ECLK_STATUS__ECLK_STATUS_MASK,4,2 ## @CG_ECLK_STATUS__ECLK_STATUS_MASK
	.comm	_CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK,4,2 ## @CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK
	.comm	_COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,4,2 ## @COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK
	.comm	_ETIMEDOUT,4,2                  ## @ETIMEDOUT
	.no_dead_strip	_vi_set_vce_clocks
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vi_set_vce_clocks
_vi_set_vce_clocks:                     ; @vi_set_vce_clocks
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _AMD_IS_APU@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_IS_APU@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
Lloh3:
	adrp	x8, _CG_ECLK_CNTL__ECLK_DIVIDER_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _CG_ECLK_CNTL__ECLK_DIVIDER_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w22, [x8]
	mov	w21, #65536
Lloh6:
	adrp	x8, _ixGNB_CLK3_STATUS@GOTPAGE
Lloh7:
	ldr	x8, [x8, _ixGNB_CLK3_STATUS@GOTPAGEOFF]
Lloh8:
	adrp	x9, _ixGNB_CLK3_DFS_CNTL@GOTPAGE
Lloh9:
	ldr	x9, [x9, _ixGNB_CLK3_DFS_CNTL@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:
Lloh10:
	adrp	x8, _CG_ECLK_STATUS__ECLK_STATUS_MASK@GOTPAGE
Lloh11:
	ldr	x8, [x8, _CG_ECLK_STATUS__ECLK_STATUS_MASK@GOTPAGEOFF]
Lloh12:
	ldr	w21, [x8]
Lloh13:
	adrp	x8, _CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK@GOTPAGE
Lloh14:
	ldr	x8, [x8, _CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
Lloh16:
	adrp	x9, _CG_ECLK_CNTL__ECLK_DIVIDER_MASK@GOTPAGE
Lloh17:
	ldr	x9, [x9, _CG_ECLK_CNTL__ECLK_DIVIDER_MASK@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	orr	w22, w9, w8
Lloh19:
	adrp	x8, _ixCG_ECLK_STATUS@GOTPAGE
Lloh20:
	ldr	x8, [x8, _ixCG_ECLK_STATUS@GOTPAGEOFF]
Lloh21:
	adrp	x9, _ixCG_ECLK_CNTL@GOTPAGE
Lloh22:
	ldr	x9, [x9, _ixCG_ECLK_CNTL@GOTPAGEOFF]
LBB0_3:
	ldr	w19, [x8]
	ldr	w20, [x9]
Lloh23:
	adrp	x8, _COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK@GOTPAGE
Lloh24:
	ldr	x8, [x8, _COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK@GOTPAGEOFF]
Lloh25:
	ldr	w1, [x8]
	add	x4, sp, #8
	mov	w3, #0
	bl	_amdgpu_atombios_get_clock_dividers
	cbnz	w0, LBB0_12
; %bb.4:
	mov	w23, #100
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x19
	bl	_RREG32_SMC
	tst	w0, w21
	b.ne	LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	mov	w0, #10
	bl	_mdelay
	subs	w23, w23, #1
	b.ne	LBB0_5
	b	LBB0_10
LBB0_7:
	mov	x0, x20
	bl	_RREG32_SMC
	bic	w8, w0, w22
	ldr	w9, [sp, #8]
	orr	w1, w8, w9
	mov	x0, x20
	bl	_WREG32_SMC
	mov	w20, #100
LBB0_8:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x19
	bl	_RREG32_SMC
	tst	w0, w21
	b.ne	LBB0_11
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=1
	mov	w0, #10
	bl	_mdelay
	subs	w20, w20, #1
	b.ne	LBB0_8
LBB0_10:
Lloh26:
	adrp	x8, _ETIMEDOUT@GOTPAGE
Lloh27:
	ldr	x8, [x8, _ETIMEDOUT@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_12
LBB0_11:
	mov	w0, #0
LBB0_12:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_ixGNB_CLK3_DFS_CNTL,4,2        ; @ixGNB_CLK3_DFS_CNTL
	.comm	_ixGNB_CLK3_STATUS,4,2          ; @ixGNB_CLK3_STATUS
	.comm	_CG_ECLK_CNTL__ECLK_DIVIDER_MASK,4,2 ; @CG_ECLK_CNTL__ECLK_DIVIDER_MASK
	.comm	_ixCG_ECLK_CNTL,4,2             ; @ixCG_ECLK_CNTL
	.comm	_ixCG_ECLK_STATUS,4,2           ; @ixCG_ECLK_STATUS
	.comm	_CG_ECLK_STATUS__ECLK_STATUS_MASK,4,2 ; @CG_ECLK_STATUS__ECLK_STATUS_MASK
	.comm	_CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK,4,2 ; @CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK
	.comm	_COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,4,2 ; @COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK
	.comm	_ETIMEDOUT,4,2                  ; @ETIMEDOUT
	.no_dead_strip	_vi_set_vce_clocks
.subsections_via_symbols
