	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v1_0_clock_gating_dpg_mode
_vcn_v1_0_clock_gating_dpg_mode:        ## @vcn_v1_0_clock_gating_dpg_mode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	_JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$1, %edx
	shll	%cl, %edx
	movq	_AMD_CG_SUPPORT_VCN_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%rdi), %eax
	movl	%esi, %r14d
	testl	%eax, %eax
	cmovel	%eax, %edx
	movl	$1, %ebx
	movq	_JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	btsl	%eax, %edx
	movq	_JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$4, %r13d
	movl	$4, %eax
	shll	%cl, %eax
	orl	%edx, %eax
	movq	_UVD@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	movq	_mmJPEG_CGC_CTRL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	movl	$-1, %r8d
	movl	%r14d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r15), %edi
	movq	_mmJPEG_CGC_GATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	movl	$-1, %r8d
	movl	%r14d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movq	_AMD_CG_SUPPORT_VCN_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%r12), %eax
	movq	_UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %ebx
	testl	%eax, %eax
	cmovel	%eax, %ebx
	movq	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPCREL(%rip), %rcx
	movq	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__SYS_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__REGS_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__RBC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__MPC_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movq	_UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movq	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPCREL(%rip), %rdx
	movb	(%rdx), %dl
	shll	%cl, %r13d
	btsl	%edx, %ebx
	movq	_UVD_CGC_CTRL__WCB_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	orl	%ebx, %r13d
	movq	_UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_CGC_CTRL__SCPU_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	notl	%eax
	andl	%r13d, %eax
	movl	(%r15), %edi
	movq	_mmUVD_CGC_CTRL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	movl	$-1, %r8d
	movl	%r14d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r15), %edi
	movq	_mmUVD_CGC_GATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	movl	$-1, %r8d
	movl	%r14d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r15), %edi
	movq	_mmUVD_SUVD_CGC_GATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	movl	$1, %ecx
	movl	$-1, %r8d
	movl	%r14d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r15), %edi
	movq	_mmUVD_SUVD_CGC_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	movl	$-1, %r8d
	movl	%r14d, %r9d
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_SOC15_DPG_MODE          ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_CG_SUPPORT_VCN_MGCG,4,2    ## @AMD_CG_SUPPORT_VCN_MGCG
	.comm	_JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT,4,2 ## @JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT
	.comm	_JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT,4,2 ## @JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
	.comm	_JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT,4,2 ## @JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmJPEG_CGC_CTRL,4,2            ## @mmJPEG_CGC_CTRL
	.comm	_mmJPEG_CGC_GATE,4,2            ## @mmJPEG_CGC_GATE
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT,4,2 ## @UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT
	.comm	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT,4,2 ## @UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
	.comm	_UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT,4,2 ## @UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT
	.comm	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_RE_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_CM_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_IT_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_DB_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_MP_MODE_MASK
	.comm	_UVD_CGC_CTRL__SYS_MODE_MASK,4,2 ## @UVD_CGC_CTRL__SYS_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__UDEC_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPEG2_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPEG2_MODE_MASK
	.comm	_UVD_CGC_CTRL__REGS_MODE_MASK,4,2 ## @UVD_CGC_CTRL__REGS_MODE_MASK
	.comm	_UVD_CGC_CTRL__RBC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__RBC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_MC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LMI_MC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LMI_UMC_MODE_MASK
	.comm	_UVD_CGC_CTRL__IDCT_MODE_MASK,4,2 ## @UVD_CGC_CTRL__IDCT_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPRD_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPRD_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPC_MODE_MASK,4,2 ## @UVD_CGC_CTRL__MPC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LBSI_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LBSI_MODE_MASK
	.comm	_UVD_CGC_CTRL__LRBBM_MODE_MASK,4,2 ## @UVD_CGC_CTRL__LRBBM_MODE_MASK
	.comm	_UVD_CGC_CTRL__WCB_MODE_MASK,4,2 ## @UVD_CGC_CTRL__WCB_MODE_MASK
	.comm	_UVD_CGC_CTRL__VCPU_MODE_MASK,4,2 ## @UVD_CGC_CTRL__VCPU_MODE_MASK
	.comm	_UVD_CGC_CTRL__SCPU_MODE_MASK,4,2 ## @UVD_CGC_CTRL__SCPU_MODE_MASK
	.comm	_mmUVD_CGC_CTRL,4,2             ## @mmUVD_CGC_CTRL
	.comm	_mmUVD_CGC_GATE,4,2             ## @mmUVD_CGC_GATE
	.comm	_mmUVD_SUVD_CGC_GATE,4,2        ## @mmUVD_SUVD_CGC_GATE
	.comm	_mmUVD_SUVD_CGC_CTRL,4,2        ## @mmUVD_SUVD_CGC_CTRL
	.no_dead_strip	_vcn_v1_0_clock_gating_dpg_mode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v1_0_clock_gating_dpg_mode
_vcn_v1_0_clock_gating_dpg_mode:        ; @vcn_v1_0_clock_gating_dpg_mode
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x1
	mov	x20, x0
	ldr	w8, [x0]
Lloh0:
	adrp	x22, _AMD_CG_SUPPORT_VCN_MGCG@GOTPAGE
Lloh1:
	ldr	x22, [x22, _AMD_CG_SUPPORT_VCN_MGCG@GOTPAGEOFF]
	ldr	w9, [x22]
Lloh2:
	adrp	x10, _JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPAGE
Lloh3:
	ldr	x10, [x10, _JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPAGEOFF]
Lloh4:
	ldr	w10, [x10]
	mov	w23, #1
	lsl	w10, w23, w10
	tst	w9, w8
	csel	w8, wzr, w10, eq
Lloh5:
	adrp	x9, _JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPAGE
Lloh6:
	ldr	x9, [x9, _JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	lsl	w9, w23, w9
	orr	w8, w8, w9
Lloh8:
	adrp	x9, _JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPAGE
Lloh9:
	ldr	x9, [x9, _JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
	mov	w24, #4
	lsl	w9, w24, w9
	orr	w3, w8, w9
Lloh11:
	adrp	x21, _UVD@GOTPAGE
Lloh12:
	ldr	x21, [x21, _UVD@GOTPAGEOFF]
	ldr	w0, [x21]
Lloh13:
	adrp	x8, _mmJPEG_CGC_CTRL@GOTPAGE
Lloh14:
	ldr	x8, [x8, _mmJPEG_CGC_CTRL@GOTPAGEOFF]
Lloh15:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w4, #-1
	mov	x5, x19
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x21]
Lloh16:
	adrp	x8, _mmJPEG_CGC_GATE@GOTPAGE
Lloh17:
	ldr	x8, [x8, _mmJPEG_CGC_GATE@GOTPAGEOFF]
Lloh18:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	mov	w4, #-1
	mov	x5, x19
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w8, [x20]
	ldr	w9, [x22]
Lloh19:
	adrp	x10, _UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPAGE
Lloh20:
	ldr	x10, [x10, _UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT@GOTPAGEOFF]
Lloh21:
	ldr	w10, [x10]
	lsl	w10, w23, w10
	tst	w9, w8
	csel	w8, wzr, w10, eq
Lloh22:
	adrp	x9, _UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPAGE
Lloh23:
	ldr	x9, [x9, _UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	lsl	w9, w23, w9
	orr	w8, w8, w9
Lloh25:
	adrp	x9, _UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPAGE
Lloh26:
	ldr	x9, [x9, _UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
	lsl	w9, w24, w9
	orr	w8, w8, w9
Lloh28:
	adrp	x9, _UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPAGE
Lloh29:
	ldr	x9, [x9, _UVD_CGC_CTRL__UDEC_RE_MODE_MASK@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
Lloh31:
	adrp	x10, _UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPAGE
Lloh32:
	ldr	x10, [x10, _UVD_CGC_CTRL__UDEC_CM_MODE_MASK@GOTPAGEOFF]
Lloh33:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh34:
	adrp	x10, _UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPAGE
Lloh35:
	ldr	x10, [x10, _UVD_CGC_CTRL__UDEC_IT_MODE_MASK@GOTPAGEOFF]
Lloh36:
	ldr	w10, [x10]
Lloh37:
	adrp	x11, _UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPAGE
Lloh38:
	ldr	x11, [x11, _UVD_CGC_CTRL__UDEC_DB_MODE_MASK@GOTPAGEOFF]
	orr	w9, w9, w10
Lloh39:
	ldr	w10, [x11]
	orr	w9, w9, w10
Lloh40:
	adrp	x10, _UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPAGE
Lloh41:
	ldr	x10, [x10, _UVD_CGC_CTRL__UDEC_MP_MODE_MASK@GOTPAGEOFF]
Lloh42:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh43:
	adrp	x10, _UVD_CGC_CTRL__SYS_MODE_MASK@GOTPAGE
Lloh44:
	ldr	x10, [x10, _UVD_CGC_CTRL__SYS_MODE_MASK@GOTPAGEOFF]
Lloh45:
	ldr	w10, [x10]
Lloh46:
	adrp	x11, _UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPAGE
Lloh47:
	ldr	x11, [x11, _UVD_CGC_CTRL__UDEC_MODE_MASK@GOTPAGEOFF]
	orr	w9, w9, w10
Lloh48:
	ldr	w10, [x11]
	orr	w9, w9, w10
Lloh49:
	adrp	x10, _UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPAGE
Lloh50:
	ldr	x10, [x10, _UVD_CGC_CTRL__MPEG2_MODE_MASK@GOTPAGEOFF]
Lloh51:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh52:
	adrp	x10, _UVD_CGC_CTRL__REGS_MODE_MASK@GOTPAGE
Lloh53:
	ldr	x10, [x10, _UVD_CGC_CTRL__REGS_MODE_MASK@GOTPAGEOFF]
Lloh54:
	ldr	w10, [x10]
Lloh55:
	adrp	x11, _UVD_CGC_CTRL__RBC_MODE_MASK@GOTPAGE
Lloh56:
	ldr	x11, [x11, _UVD_CGC_CTRL__RBC_MODE_MASK@GOTPAGEOFF]
	orr	w9, w9, w10
Lloh57:
	ldr	w10, [x11]
	orr	w9, w9, w10
Lloh58:
	adrp	x10, _UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPAGE
Lloh59:
	ldr	x10, [x10, _UVD_CGC_CTRL__LMI_MC_MODE_MASK@GOTPAGEOFF]
Lloh60:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh61:
	adrp	x10, _UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPAGE
Lloh62:
	ldr	x10, [x10, _UVD_CGC_CTRL__LMI_UMC_MODE_MASK@GOTPAGEOFF]
Lloh63:
	ldr	w10, [x10]
Lloh64:
	adrp	x11, _UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPAGE
Lloh65:
	ldr	x11, [x11, _UVD_CGC_CTRL__IDCT_MODE_MASK@GOTPAGEOFF]
	orr	w9, w9, w10
Lloh66:
	ldr	w10, [x11]
	orr	w9, w9, w10
Lloh67:
	adrp	x10, _UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPAGE
Lloh68:
	ldr	x10, [x10, _UVD_CGC_CTRL__MPRD_MODE_MASK@GOTPAGEOFF]
Lloh69:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh70:
	adrp	x10, _UVD_CGC_CTRL__MPC_MODE_MASK@GOTPAGE
Lloh71:
	ldr	x10, [x10, _UVD_CGC_CTRL__MPC_MODE_MASK@GOTPAGEOFF]
Lloh72:
	ldr	w10, [x10]
Lloh73:
	adrp	x11, _UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPAGE
Lloh74:
	ldr	x11, [x11, _UVD_CGC_CTRL__LBSI_MODE_MASK@GOTPAGEOFF]
	orr	w9, w9, w10
Lloh75:
	ldr	w10, [x11]
	orr	w9, w9, w10
Lloh76:
	adrp	x10, _UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPAGE
Lloh77:
	ldr	x10, [x10, _UVD_CGC_CTRL__LRBBM_MODE_MASK@GOTPAGEOFF]
Lloh78:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh79:
	adrp	x10, _UVD_CGC_CTRL__WCB_MODE_MASK@GOTPAGE
Lloh80:
	ldr	x10, [x10, _UVD_CGC_CTRL__WCB_MODE_MASK@GOTPAGEOFF]
Lloh81:
	ldr	w10, [x10]
Lloh82:
	adrp	x11, _UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPAGE
Lloh83:
	ldr	x11, [x11, _UVD_CGC_CTRL__VCPU_MODE_MASK@GOTPAGEOFF]
	orr	w9, w9, w10
Lloh84:
	ldr	w10, [x11]
	orr	w9, w9, w10
Lloh85:
	adrp	x10, _UVD_CGC_CTRL__SCPU_MODE_MASK@GOTPAGE
Lloh86:
	ldr	x10, [x10, _UVD_CGC_CTRL__SCPU_MODE_MASK@GOTPAGEOFF]
Lloh87:
	ldr	w10, [x10]
	orr	w9, w9, w10
	bic	w3, w8, w9
	ldr	w0, [x21]
Lloh88:
	adrp	x8, _mmUVD_CGC_CTRL@GOTPAGE
Lloh89:
	ldr	x8, [x8, _mmUVD_CGC_CTRL@GOTPAGEOFF]
Lloh90:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w4, #-1
	mov	x5, x19
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x21]
Lloh91:
	adrp	x8, _mmUVD_CGC_GATE@GOTPAGE
Lloh92:
	ldr	x8, [x8, _mmUVD_CGC_GATE@GOTPAGEOFF]
Lloh93:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	mov	w4, #-1
	mov	x5, x19
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x21]
Lloh94:
	adrp	x8, _mmUVD_SUVD_CGC_GATE@GOTPAGE
Lloh95:
	ldr	x8, [x8, _mmUVD_SUVD_CGC_GATE@GOTPAGEOFF]
Lloh96:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #1
	mov	w4, #-1
	mov	x5, x19
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x21]
Lloh97:
	adrp	x8, _mmUVD_SUVD_CGC_CTRL@GOTPAGE
Lloh98:
	ldr	x8, [x8, _mmUVD_SUVD_CGC_CTRL@GOTPAGEOFF]
Lloh99:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	mov	w4, #-1
	mov	x5, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_WREG32_SOC15_DPG_MODE
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_CG_SUPPORT_VCN_MGCG,4,2    ; @AMD_CG_SUPPORT_VCN_MGCG
	.comm	_JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT,4,2 ; @JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT
	.comm	_JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT,4,2 ; @JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
	.comm	_JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT,4,2 ; @JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmJPEG_CGC_CTRL,4,2            ; @mmJPEG_CGC_CTRL
	.comm	_mmJPEG_CGC_GATE,4,2            ; @mmJPEG_CGC_GATE
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT,4,2 ; @UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT
	.comm	_UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT,4,2 ; @UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
	.comm	_UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT,4,2 ; @UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT
	.comm	_UVD_CGC_CTRL__UDEC_RE_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_RE_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_CM_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_CM_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_IT_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_IT_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_DB_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_DB_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MP_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_MP_MODE_MASK
	.comm	_UVD_CGC_CTRL__SYS_MODE_MASK,4,2 ; @UVD_CGC_CTRL__SYS_MODE_MASK
	.comm	_UVD_CGC_CTRL__UDEC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__UDEC_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPEG2_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPEG2_MODE_MASK
	.comm	_UVD_CGC_CTRL__REGS_MODE_MASK,4,2 ; @UVD_CGC_CTRL__REGS_MODE_MASK
	.comm	_UVD_CGC_CTRL__RBC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__RBC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_MC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LMI_MC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LMI_UMC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LMI_UMC_MODE_MASK
	.comm	_UVD_CGC_CTRL__IDCT_MODE_MASK,4,2 ; @UVD_CGC_CTRL__IDCT_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPRD_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPRD_MODE_MASK
	.comm	_UVD_CGC_CTRL__MPC_MODE_MASK,4,2 ; @UVD_CGC_CTRL__MPC_MODE_MASK
	.comm	_UVD_CGC_CTRL__LBSI_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LBSI_MODE_MASK
	.comm	_UVD_CGC_CTRL__LRBBM_MODE_MASK,4,2 ; @UVD_CGC_CTRL__LRBBM_MODE_MASK
	.comm	_UVD_CGC_CTRL__WCB_MODE_MASK,4,2 ; @UVD_CGC_CTRL__WCB_MODE_MASK
	.comm	_UVD_CGC_CTRL__VCPU_MODE_MASK,4,2 ; @UVD_CGC_CTRL__VCPU_MODE_MASK
	.comm	_UVD_CGC_CTRL__SCPU_MODE_MASK,4,2 ; @UVD_CGC_CTRL__SCPU_MODE_MASK
	.comm	_mmUVD_CGC_CTRL,4,2             ; @mmUVD_CGC_CTRL
	.comm	_mmUVD_CGC_GATE,4,2             ; @mmUVD_CGC_GATE
	.comm	_mmUVD_SUVD_CGC_GATE,4,2        ; @mmUVD_SUVD_CGC_GATE
	.comm	_mmUVD_SUVD_CGC_CTRL,4,2        ; @mmUVD_SUVD_CGC_CTRL
	.no_dead_strip	_vcn_v1_0_clock_gating_dpg_mode
.subsections_via_symbols
