	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r600_voltage_control_program_voltages ## -- Begin function r600_voltage_control_program_voltages
	.p2align	4, 0x90
_r600_voltage_control_program_voltages: ## @r600_voltage_control_program_voltages
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r14d
	movl	%esi, %ebx
	notl	%ebx
	andl	$3, %ebx
	movq	_CTXSW_VID_LOWER_GPIO_CNTL@GOTPCREL(%rip), %rax
	leal	(,%rbx,4), %edi
	addq	(%rax), %rdi
	movl	%edx, %esi
	callq	_WREG32
	leal	(%rbx,%rbx,2), %ebx
	movl	$7, %r15d
	movl	%ebx, %ecx
	shll	%cl, %r15d
	movq	_VID_UPPER_GPIO_CNTL@GOTPCREL(%rip), %r12
	movq	(%r12), %rdi
	callq	_RREG32
	negb	%bl
	movl	%ebx, %ecx
	sarl	%cl, %r14d
	xorl	%eax, %r14d
	andl	%r15d, %r14d
	xorl	%eax, %r14d
	movq	(%r12), %rdi
	movl	%r14d, %esi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_CTXSW_VID_LOWER_GPIO_CNTL,8,3  ## @CTXSW_VID_LOWER_GPIO_CNTL
	.comm	_VID_UPPER_GPIO_CNTL,8,3        ## @VID_UPPER_GPIO_CNTL
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r600_voltage_control_program_voltages ; -- Begin function r600_voltage_control_program_voltages
	.p2align	2
_r600_voltage_control_program_voltages: ; @r600_voltage_control_program_voltages
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x2
	mvn	w8, w1
	and	w20, w8, #0x3
Lloh0:
	adrp	x8, _CTXSW_VID_LOWER_GPIO_CNTL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _CTXSW_VID_LOWER_GPIO_CNTL@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	lsl	w9, w20, #2
	add	x0, x8, x9
	mov	x1, x2
	bl	_WREG32
	add	w20, w20, w20, lsl #1
	mov	w8, #7
	lsl	w21, w8, w20
Lloh3:
	adrp	x22, _VID_UPPER_GPIO_CNTL@GOTPAGE
Lloh4:
	ldr	x22, [x22, _VID_UPPER_GPIO_CNTL@GOTPAGEOFF]
	ldr	x0, [x22]
	bl	_RREG32
	bic	w8, w0, w21
	neg	w9, w20
	asr	w9, w19, w9
	and	w9, w9, w21
	orr	w1, w8, w9
	ldr	x0, [x22]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_CTXSW_VID_LOWER_GPIO_CNTL,8,3  ; @CTXSW_VID_LOWER_GPIO_CNTL
	.comm	_VID_UPPER_GPIO_CNTL,8,3        ; @VID_UPPER_GPIO_CNTL
.subsections_via_symbols
