	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function meson_sar_adc_init
_meson_sar_adc_init:                    ## @meson_sar_adc_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	callq	_iio_priv
	movq	%rax, %r15
	movq	_CHAN7_MUX_CH7_INPUT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_meson_sar_adc_set_chan7_mux
	movq	8(%r15), %rax
	cmpq	$0, 8(%rax)
	je	LBB0_2
## %bb.1:
	movl	28(%r15), %edi
	movq	_MESON_SAR_ADC_REG3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-44(%rbp), %rdx
	callq	_regmap_read
	movq	_MESON_SAR_ADC_REG3_BL30_INITIALIZED@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	xorl	%r14d, %r14d
	testl	%eax, -44(%rbp)
	jne	LBB0_12
LBB0_2:
	movq	%rbx, -56(%rbp)                 ## 8-byte Spill
	movq	%rbx, %rdi
	callq	_meson_sar_adc_stop_sample_engine
	movl	28(%r15), %edi
	movq	_MESON_SAR_ADC_REG0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	28(%r15), %edi
	movq	_MESON_SAR_ADC_CHAN_LIST@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	movl	28(%r15), %edi
	movq	_MESON_SAR_ADC_REG3@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	28(%r15), %edi
	movl	(%rbx), %esi
	movq	_MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	28(%r15), %r12d
	movq	_MESON_SAR_ADC_DELAY@GOTPCREL(%rip), %r14
	movl	(%r14), %r13d
	movq	_MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$10, %esi
	callq	_FIELD_PREP
	movl	%r12d, %edi
	movl	%r13d, %esi
	movl	%ebx, %edx
	movl	%eax, %ecx
	callq	_regmap_update_bits
	movl	28(%r15), %r13d
	movl	(%r14), %r12d
	movq	_MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%ebx, %edi
	xorl	%esi, %esi
	callq	_FIELD_PREP
	movl	%r13d, %edi
	movl	%r12d, %esi
	movl	%ebx, %edx
	movl	%eax, %ecx
	callq	_regmap_update_bits
	movl	28(%r15), %r13d
	movl	(%r14), %r12d
	movq	_MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%ebx, %edi
	movl	$10, %esi
	callq	_FIELD_PREP
	movl	%r13d, %edi
	movl	%r12d, %esi
	movl	%ebx, %edx
	movl	%eax, %ecx
	callq	_regmap_update_bits
	movl	28(%r15), %r13d
	movl	(%r14), %r12d
	movq	_MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%ebx, %edi
	movl	$1, %esi
	callq	_FIELD_PREP
	movl	%r13d, %edi
	movl	%r12d, %esi
	movl	%ebx, %edx
	movl	%eax, %ecx
	callq	_regmap_update_bits
	movq	_MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	xorl	%esi, %esi
	callq	_FIELD_PREP
	movl	%eax, -44(%rbp)
	movl	28(%r15), %edi
	movq	_MESON_SAR_ADC_CHAN_10_SW@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movl	(%rbx), %edx
	movl	%eax, %ecx
	callq	_regmap_update_bits
	movq	_MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movl	$1, %esi
	callq	_FIELD_PREP
	movl	%eax, -44(%rbp)
	movl	28(%r15), %edi
	movl	(%r14), %esi
	movl	(%rbx), %edx
	movl	%eax, %ecx
	callq	_regmap_update_bits
	movl	$0, -44(%rbp)
	movl	$2, %ebx
	movl	$2, %edi
	callq	_MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT
	movl	%eax, %ecx
	shll	%cl, %ebx
	orl	%ebx, -44(%rbp)
	movl	$3, %ebx
	movl	$3, %edi
	callq	_MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT
	movl	%eax, %ecx
	shll	%cl, %ebx
	orl	%ebx, -44(%rbp)
	movl	$4, %ebx
	movl	$4, %edi
	callq	_MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT
	movl	%eax, %ecx
	shll	%cl, %ebx
	orl	%ebx, -44(%rbp)
	movl	$5, %ebx
	movl	$5, %edi
	callq	_MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT
	movl	%eax, %ecx
	shll	%cl, %ebx
	orl	%ebx, -44(%rbp)
	movl	$6, %ebx
	movl	$6, %edi
	callq	_MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT
	movl	%eax, %ecx
	shll	%cl, %ebx
	orl	%ebx, -44(%rbp)
	movl	$7, %ebx
	movl	$7, %edi
	callq	_MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT
	movl	%eax, %ecx
	shll	%cl, %ebx
	orl	-44(%rbp), %ebx
	movq	_MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	%ebx, -44(%rbp)
	movl	28(%r15), %edi
	movq	_MESON_SAR_ADC_AUX_SW@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%ebx, %edx
	callq	_regmap_write
	cmpq	$0, 40(%r15)
	movl	28(%r15), %edi
	movq	_MESON_SAR_ADC_DELTA_10@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_MESON_SAR_ADC_DELTA_10_TS_REVE1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	je	LBB0_5
## %bb.3:
	movl	%edx, %ecx
	callq	_regmap_update_bits
	movl	28(%r15), %edi
	movl	(%rbx), %esi
	movq	_MESON_SAR_ADC_DELTA_10_TS_REVE0@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movq	_MESON_SAR_ADC_DELTA_10_TS_C_MASK@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movl	(%r15), %esi
	callq	_FIELD_PREP
	movl	%eax, -44(%rbp)
	movl	28(%r15), %edi
	movl	(%rbx), %esi
	movl	(%r14), %edx
	movl	%eax, %ecx
	callq	_regmap_update_bits
	movq	8(%r15), %rax
	cmpl	$5, (%rax)
	jne	LBB0_7
## %bb.4:
	movl	(%r15), %ebx
	movl	$4, %edi
	callq	_BIT
	andl	%eax, %ebx
	movq	_MESON_HHI_DPLL_TOP_0_TSC_BIT4@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	cmovnel	%edx, %ebx
	movl	%ebx, -44(%rbp)
	movl	32(%r15), %edi
	movq	_MESON_HHI_DPLL_TOP_0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%ebx, %ecx
	jmp	LBB0_6
LBB0_5:
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	28(%r15), %edi
	movl	(%rbx), %esi
	movq	_MESON_SAR_ADC_DELTA_10_TS_REVE0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
LBB0_6:
	callq	_regmap_update_bits
LBB0_7:
	movl	20(%r15), %esi
	movl	24(%r15), %edi
	callq	_clk_set_parent
	testl	%eax, %eax
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	je	LBB0_9
## %bb.8:
	movl	%eax, %r14d
	leaq	L_.str(%rip), %rsi
	jmp	LBB0_11
LBB0_9:
	movl	16(%r15), %edi
	movq	8(%r15), %rax
	movl	4(%rax), %esi
	callq	_clk_set_rate
	testl	%eax, %eax
	je	LBB0_13
## %bb.10:
	movl	%eax, %r14d
	leaq	L_.str.1(%rip), %rsi
LBB0_11:
	movl	(%rbx), %edi
	callq	_dev_err
LBB0_12:
	movl	%r14d, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_13:
	xorl	%r14d, %r14d
	jmp	LBB0_12
	.cfi_endproc
                                        ## -- End function
	.comm	_CHAN7_MUX_CH7_INPUT,4,2        ## @CHAN7_MUX_CH7_INPUT
	.comm	_MESON_SAR_ADC_REG3,4,2         ## @MESON_SAR_ADC_REG3
	.comm	_MESON_SAR_ADC_REG3_BL30_INITIALIZED,4,2 ## @MESON_SAR_ADC_REG3_BL30_INITIALIZED
	.comm	_MESON_SAR_ADC_REG0,4,2         ## @MESON_SAR_ADC_REG0
	.comm	_MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL,4,2 ## @MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL
	.comm	_MESON_SAR_ADC_CHAN_LIST,4,2    ## @MESON_SAR_ADC_CHAN_LIST
	.comm	_MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE,4,2 ## @MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE
	.comm	_MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,4,2 ## @MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY
	.comm	_MESON_SAR_ADC_DELAY,4,2        ## @MESON_SAR_ADC_DELAY
	.comm	_MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,4,2 ## @MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK
	.comm	_MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,4,2 ## @MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK
	.comm	_MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,4,2 ## @MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK
	.comm	_MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,4,2 ## @MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK
	.comm	_MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK,4,2 ## @MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK
	.comm	_MESON_SAR_ADC_CHAN_10_SW,4,2   ## @MESON_SAR_ADC_CHAN_10_SW
	.comm	_MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,4,2 ## @MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK
	.comm	_MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW,4,2 ## @MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW
	.comm	_MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW,4,2 ## @MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW
	.comm	_MESON_SAR_ADC_AUX_SW,4,2       ## @MESON_SAR_ADC_AUX_SW
	.comm	_MESON_SAR_ADC_DELTA_10,4,2     ## @MESON_SAR_ADC_DELTA_10
	.comm	_MESON_SAR_ADC_DELTA_10_TS_REVE1,4,2 ## @MESON_SAR_ADC_DELTA_10_TS_REVE1
	.comm	_MESON_SAR_ADC_DELTA_10_TS_REVE0,4,2 ## @MESON_SAR_ADC_DELTA_10_TS_REVE0
	.comm	_MESON_SAR_ADC_DELTA_10_TS_C_MASK,4,2 ## @MESON_SAR_ADC_DELTA_10_TS_C_MASK
	.comm	_MESON_HHI_DPLL_TOP_0_TSC_BIT4,4,2 ## @MESON_HHI_DPLL_TOP_0_TSC_BIT4
	.comm	_MESON_HHI_DPLL_TOP_0,4,2       ## @MESON_HHI_DPLL_TOP_0
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"failed to set adc parent to clkin\n"

L_.str.1:                               ## @.str.1
	.asciz	"failed to set adc clock rate\n"

	.no_dead_strip	_meson_sar_adc_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function meson_sar_adc_init
_meson_sar_adc_init:                    ; @meson_sar_adc_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	bl	_iio_priv
	mov	x20, x0
Lloh0:
	adrp	x8, _CHAN7_MUX_CH7_INPUT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _CHAN7_MUX_CH7_INPUT@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_meson_sar_adc_set_chan7_mux
	ldr	x8, [x20, #8]
	ldr	x8, [x8, #8]
Lloh3:
	adrp	x21, _MESON_SAR_ADC_REG3@GOTPAGE
Lloh4:
	ldr	x21, [x21, _MESON_SAR_ADC_REG3@GOTPAGEOFF]
	cbz	x8, LBB0_3
; %bb.1:
	ldr	w0, [x20, #28]
	ldr	w1, [x21]
	add	x2, sp, #12
	bl	_regmap_read
	ldr	w8, [sp, #12]
Lloh5:
	adrp	x9, _MESON_SAR_ADC_REG3_BL30_INITIALIZED@GOTPAGE
Lloh6:
	ldr	x9, [x9, _MESON_SAR_ADC_REG3_BL30_INITIALIZED@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_3
; %bb.2:
	mov	w21, #0
	b	LBB0_13
LBB0_3:
	mov	x0, x19
	bl	_meson_sar_adc_stop_sample_engine
	ldr	w0, [x20, #28]
Lloh8:
	adrp	x8, _MESON_SAR_ADC_REG0@GOTPAGE
Lloh9:
	ldr	x8, [x8, _MESON_SAR_ADC_REG0@GOTPAGEOFF]
Lloh10:
	ldr	w1, [x8]
Lloh11:
	adrp	x8, _MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL@GOTPAGE
Lloh12:
	ldr	x8, [x8, _MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_regmap_update_bits
	ldr	w0, [x20, #28]
Lloh14:
	adrp	x8, _MESON_SAR_ADC_CHAN_LIST@GOTPAGE
Lloh15:
	ldr	x8, [x8, _MESON_SAR_ADC_CHAN_LIST@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_regmap_write
	ldr	w0, [x20, #28]
	ldr	w1, [x21]
Lloh17:
	adrp	x8, _MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE@GOTPAGE
Lloh18:
	ldr	x8, [x8, _MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE@GOTPAGEOFF]
Lloh19:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_regmap_update_bits
	ldr	w0, [x20, #28]
	ldr	w1, [x21]
Lloh20:
	adrp	x8, _MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY@GOTPAGE
Lloh21:
	ldr	x8, [x8, _MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w21, [x20, #28]
Lloh23:
	adrp	x24, _MESON_SAR_ADC_DELAY@GOTPAGE
Lloh24:
	ldr	x24, [x24, _MESON_SAR_ADC_DELAY@GOTPAGEOFF]
	ldr	w22, [x24]
Lloh25:
	adrp	x25, _MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK@GOTPAGE
Lloh26:
	ldr	x25, [x25, _MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK@GOTPAGEOFF]
	ldr	w23, [x25]
Lloh27:
	adrp	x8, _MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK@GOTPAGE
Lloh28:
	ldr	x8, [x8, _MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	mov	w1, #10
	bl	_FIELD_PREP
	mov	x3, x0
	mov	x0, x21
	mov	x1, x22
	mov	x2, x23
	bl	_regmap_update_bits
	ldr	w21, [x20, #28]
	ldr	w22, [x24]
Lloh30:
	adrp	x8, _MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK@GOTPAGE
Lloh31:
	ldr	x8, [x8, _MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK@GOTPAGEOFF]
Lloh32:
	ldr	w23, [x8]
	mov	x0, x23
	mov	w1, #0
	bl	_FIELD_PREP
	mov	x3, x0
	mov	x0, x21
	mov	x1, x22
	mov	x2, x23
	bl	_regmap_update_bits
	ldr	w21, [x20, #28]
	ldr	w22, [x24]
	ldr	w23, [x25]
	mov	x0, x23
	mov	w1, #10
	bl	_FIELD_PREP
	mov	x3, x0
	mov	x0, x21
	mov	x1, x22
	mov	x2, x23
	bl	_regmap_update_bits
	ldr	w21, [x20, #28]
	ldr	w22, [x24]
Lloh33:
	adrp	x8, _MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK@GOTPAGE
Lloh34:
	ldr	x8, [x8, _MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK@GOTPAGEOFF]
Lloh35:
	ldr	w23, [x8]
	mov	x0, x23
	mov	w1, #1
	bl	_FIELD_PREP
	mov	x3, x0
	mov	x0, x21
	mov	x1, x22
	mov	x2, x23
	bl	_regmap_update_bits
Lloh36:
	adrp	x21, _MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK@GOTPAGE
Lloh37:
	ldr	x21, [x21, _MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK@GOTPAGEOFF]
	ldr	w0, [x21]
	mov	w1, #0
	bl	_FIELD_PREP
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w0, [x20, #28]
Lloh38:
	adrp	x22, _MESON_SAR_ADC_CHAN_10_SW@GOTPAGE
Lloh39:
	ldr	x22, [x22, _MESON_SAR_ADC_CHAN_10_SW@GOTPAGEOFF]
	ldr	w1, [x22]
	ldr	w2, [x21]
	bl	_regmap_update_bits
Lloh40:
	adrp	x21, _MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK@GOTPAGE
Lloh41:
	ldr	x21, [x21, _MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK@GOTPAGEOFF]
	ldr	w0, [x21]
	mov	w1, #1
	bl	_FIELD_PREP
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w0, [x20, #28]
	ldr	w1, [x22]
	ldr	w2, [x21]
	bl	_regmap_update_bits
	str	wzr, [sp, #12]
	mov	w21, #2
	mov	w0, #2
	bl	_MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT
	lsl	w8, w21, w0
	ldr	w9, [sp, #12]
	orr	w8, w9, w8
	str	w8, [sp, #12]
	mov	w21, #3
	mov	w0, #3
	bl	_MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT
	lsl	w8, w21, w0
	ldr	w9, [sp, #12]
	orr	w8, w9, w8
	str	w8, [sp, #12]
	mov	w21, #4
	mov	w0, #4
	bl	_MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT
	lsl	w8, w21, w0
	ldr	w9, [sp, #12]
	orr	w8, w9, w8
	str	w8, [sp, #12]
	mov	w21, #5
	mov	w0, #5
	bl	_MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT
	lsl	w8, w21, w0
	ldr	w9, [sp, #12]
	orr	w8, w9, w8
	str	w8, [sp, #12]
	mov	w21, #6
	mov	w0, #6
	bl	_MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT
	lsl	w8, w21, w0
	ldr	w9, [sp, #12]
	orr	w8, w9, w8
	str	w8, [sp, #12]
	mov	w21, #7
	mov	w0, #7
	bl	_MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT
	lsl	w8, w21, w0
	ldr	w9, [sp, #12]
Lloh42:
	adrp	x10, _MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW@GOTPAGE
Lloh43:
	ldr	x10, [x10, _MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh44:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh45:
	adrp	x9, _MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW@GOTPAGE
Lloh46:
	ldr	x9, [x9, _MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW@GOTPAGEOFF]
Lloh47:
	ldr	w9, [x9]
	orr	w2, w9, w8
	str	w2, [sp, #12]
	ldr	w0, [x20, #28]
Lloh48:
	adrp	x8, _MESON_SAR_ADC_AUX_SW@GOTPAGE
Lloh49:
	ldr	x8, [x8, _MESON_SAR_ADC_AUX_SW@GOTPAGEOFF]
Lloh50:
	ldr	w1, [x8]
	bl	_regmap_write
	ldr	x8, [x20, #40]
	ldr	w0, [x20, #28]
Lloh51:
	adrp	x21, _MESON_SAR_ADC_DELTA_10@GOTPAGE
Lloh52:
	ldr	x21, [x21, _MESON_SAR_ADC_DELTA_10@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh53:
	adrp	x9, _MESON_SAR_ADC_DELTA_10_TS_REVE1@GOTPAGE
Lloh54:
	ldr	x9, [x9, _MESON_SAR_ADC_DELTA_10_TS_REVE1@GOTPAGEOFF]
Lloh55:
	ldr	w2, [x9]
	cbz	x8, LBB0_6
; %bb.4:
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x20, #28]
	ldr	w1, [x21]
Lloh56:
	adrp	x8, _MESON_SAR_ADC_DELTA_10_TS_REVE0@GOTPAGE
Lloh57:
	ldr	x8, [x8, _MESON_SAR_ADC_DELTA_10_TS_REVE0@GOTPAGEOFF]
Lloh58:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
Lloh59:
	adrp	x22, _MESON_SAR_ADC_DELTA_10_TS_C_MASK@GOTPAGE
Lloh60:
	ldr	x22, [x22, _MESON_SAR_ADC_DELTA_10_TS_C_MASK@GOTPAGEOFF]
	ldr	w0, [x22]
	ldr	w1, [x20]
	bl	_FIELD_PREP
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w0, [x20, #28]
	ldr	w1, [x21]
	ldr	w2, [x22]
	bl	_regmap_update_bits
	ldr	x8, [x20, #8]
	ldr	w8, [x8]
	cmp	w8, #5
	b.ne	LBB0_8
; %bb.5:
	ldr	w21, [x20]
	mov	w0, #4
	bl	_BIT
Lloh61:
	adrp	x8, _MESON_HHI_DPLL_TOP_0_TSC_BIT4@GOTPAGE
Lloh62:
	ldr	x8, [x8, _MESON_HHI_DPLL_TOP_0_TSC_BIT4@GOTPAGEOFF]
Lloh63:
	ldr	w2, [x8]
	tst	w0, w21
	csel	w3, wzr, w2, eq
	str	w3, [sp, #12]
	ldr	w0, [x20, #32]
Lloh64:
	adrp	x8, _MESON_HHI_DPLL_TOP_0@GOTPAGE
Lloh65:
	ldr	x8, [x8, _MESON_HHI_DPLL_TOP_0@GOTPAGEOFF]
Lloh66:
	ldr	w1, [x8]
	b	LBB0_7
LBB0_6:
	mov	w3, #0
	bl	_regmap_update_bits
	ldr	w0, [x20, #28]
	ldr	w1, [x21]
Lloh67:
	adrp	x8, _MESON_SAR_ADC_DELTA_10_TS_REVE0@GOTPAGE
Lloh68:
	ldr	x8, [x8, _MESON_SAR_ADC_DELTA_10_TS_REVE0@GOTPAGEOFF]
Lloh69:
	ldr	w2, [x8]
	mov	w3, #0
LBB0_7:
	bl	_regmap_update_bits
LBB0_8:
	ldp	w1, w0, [x20, #20]
	bl	_clk_set_parent
	cbz	w0, LBB0_10
; %bb.9:
	mov	x21, x0
Lloh70:
	adrp	x1, l_.str@PAGE
Lloh71:
	add	x1, x1, l_.str@PAGEOFF
	b	LBB0_12
LBB0_10:
	ldr	w0, [x20, #16]
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #4]
	bl	_clk_set_rate
	mov	x21, x0
	cbz	w0, LBB0_13
; %bb.11:
Lloh72:
	adrp	x1, l_.str.1@PAGE
Lloh73:
	add	x1, x1, l_.str.1@PAGEOFF
LBB0_12:
	ldr	w0, [x19]
	bl	_dev_err
LBB0_13:
	mov	x0, x21
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGot	Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpAdd	Lloh70, Lloh71
	.loh AdrpAdd	Lloh72, Lloh73
	.cfi_endproc
                                        ; -- End function
	.comm	_CHAN7_MUX_CH7_INPUT,4,2        ; @CHAN7_MUX_CH7_INPUT
	.comm	_MESON_SAR_ADC_REG3,4,2         ; @MESON_SAR_ADC_REG3
	.comm	_MESON_SAR_ADC_REG3_BL30_INITIALIZED,4,2 ; @MESON_SAR_ADC_REG3_BL30_INITIALIZED
	.comm	_MESON_SAR_ADC_REG0,4,2         ; @MESON_SAR_ADC_REG0
	.comm	_MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL,4,2 ; @MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL
	.comm	_MESON_SAR_ADC_CHAN_LIST,4,2    ; @MESON_SAR_ADC_CHAN_LIST
	.comm	_MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE,4,2 ; @MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE
	.comm	_MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,4,2 ; @MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY
	.comm	_MESON_SAR_ADC_DELAY,4,2        ; @MESON_SAR_ADC_DELAY
	.comm	_MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,4,2 ; @MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK
	.comm	_MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,4,2 ; @MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK
	.comm	_MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,4,2 ; @MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK
	.comm	_MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,4,2 ; @MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK
	.comm	_MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK,4,2 ; @MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK
	.comm	_MESON_SAR_ADC_CHAN_10_SW,4,2   ; @MESON_SAR_ADC_CHAN_10_SW
	.comm	_MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,4,2 ; @MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK
	.comm	_MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW,4,2 ; @MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW
	.comm	_MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW,4,2 ; @MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW
	.comm	_MESON_SAR_ADC_AUX_SW,4,2       ; @MESON_SAR_ADC_AUX_SW
	.comm	_MESON_SAR_ADC_DELTA_10,4,2     ; @MESON_SAR_ADC_DELTA_10
	.comm	_MESON_SAR_ADC_DELTA_10_TS_REVE1,4,2 ; @MESON_SAR_ADC_DELTA_10_TS_REVE1
	.comm	_MESON_SAR_ADC_DELTA_10_TS_REVE0,4,2 ; @MESON_SAR_ADC_DELTA_10_TS_REVE0
	.comm	_MESON_SAR_ADC_DELTA_10_TS_C_MASK,4,2 ; @MESON_SAR_ADC_DELTA_10_TS_C_MASK
	.comm	_MESON_HHI_DPLL_TOP_0_TSC_BIT4,4,2 ; @MESON_HHI_DPLL_TOP_0_TSC_BIT4
	.comm	_MESON_HHI_DPLL_TOP_0,4,2       ; @MESON_HHI_DPLL_TOP_0
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"failed to set adc parent to clkin\n"

l_.str.1:                               ; @.str.1
	.asciz	"failed to set adc clock rate\n"

	.no_dead_strip	_meson_sar_adc_init
.subsections_via_symbols
