	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function psp_v3_1_init_microcode
_psp_v3_1_init_microcode:               ## @psp_v3_1_init_microcode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	subq	$48, %rsp
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -40(%rbp)
	movq	(%rdi), %r12
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG
	movl	(%r12), %eax
	cmpl	$129, %eax
	je	LBB0_1
## %bb.2:
	cmpl	$128, %eax
	jne	LBB0_4
## %bb.3:
	leaq	L_.str.2(%rip), %r14
	jmp	LBB0_5
LBB0_1:
	leaq	L_.str.1(%rip), %r14
	jmp	LBB0_5
LBB0_4:
	xorl	%eax, %eax
	callq	_BUG
                                        ## implicit-def: $r14
LBB0_5:
	leaq	L_.str.3(%rip), %rdx
	leaq	-80(%rbp), %r15
	movq	%r15, %rdi
	movl	$30, %esi
	movq	%r14, %rcx
	callq	_snprintf
	leaq	48(%r12), %rbx
	movl	80(%r12), %edx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	_request_firmware
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	LBB0_10
## %bb.6:
	movq	(%rbx), %rdi
	callq	_amdgpu_ucode_validate
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	LBB0_10
## %bb.7:
	movq	48(%r12), %rax
	movq	(%rax), %rbx
	movl	8(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 8(%r12)
	movl	12(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 12(%r12)
	movl	20(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 16(%r12)
	movl	4(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, %r15d
	movl	20(%rbx), %edi
	callq	_le32_to_cpu
	subl	%eax, %r15d
	movl	%r15d, 20(%r12)
	movl	(%rbx), %edi
	callq	_le32_to_cpu
	cltq
	leaq	(%rbx,%rax,4), %r15
	movq	%r15, 64(%r12)
	movl	16(%rbx), %edi
	callq	_le32_to_cpu
	cltq
	leaq	(%r15,%rax,4), %rax
	movq	%rax, 72(%r12)
	leaq	L_.str.4(%rip), %rdx
	leaq	-80(%rbp), %r15
	movq	%r15, %rdi
	movl	$30, %esi
	movq	%r14, %rcx
	callq	_snprintf
	leaq	40(%r12), %rbx
	movl	80(%r12), %edx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	_request_firmware
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	LBB0_10
## %bb.8:
	movq	(%rbx), %rdi
	callq	_amdgpu_ucode_validate
	movl	%eax, %r15d
	testl	%eax, %eax
	je	LBB0_9
LBB0_10:
	movl	80(%r12), %edi
	leaq	L_.str.5(%rip), %rsi
	leaq	-80(%rbp), %rdx
	callq	_dev_err
	movq	48(%r12), %rdi
	callq	_release_firmware
	movq	$0, 48(%r12)
	movq	40(%r12), %rdi
	callq	_release_firmware
	movq	$0, 40(%r12)
LBB0_11:
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	cmpq	-40(%rbp), %rax
	jne	LBB0_13
## %bb.12:
	movl	%r15d, %eax
	addq	$48, %rsp
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_9:
	movq	40(%r12), %rax
	movq	(%rax), %rbx
	movl	8(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 24(%r12)
	movl	12(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 28(%r12)
	movl	4(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, 32(%r12)
	movl	(%rbx), %edi
	callq	_le32_to_cpu
	cltq
	leaq	(%rbx,%rax,4), %rax
	movq	%rax, 56(%r12)
	xorl	%r15d, %r15d
	jmp	LBB0_11
LBB0_13:
	callq	___stack_chk_fail
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"\n"

L_.str.1:                               ## @.str.1
	.asciz	"vega10"

L_.str.2:                               ## @.str.2
	.asciz	"vega12"

L_.str.3:                               ## @.str.3
	.asciz	"amdgpu/%s_sos.bin"

L_.str.4:                               ## @.str.4
	.asciz	"amdgpu/%s_asd.bin"

L_.str.5:                               ## @.str.5
	.asciz	"psp v3.1: Failed to load firmware \"%s\"\n"

	.no_dead_strip	_psp_v3_1_init_microcode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function psp_v3_1_init_microcode
_psp_v3_1_init_microcode:               ; @psp_v3_1_init_microcode
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
Lloh0:
	adrp	x8, ___stack_chk_guard@GOTPAGE
Lloh1:
	ldr	x8, [x8, ___stack_chk_guard@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	str	x8, [sp, #40]
	ldr	x22, [x0]
Lloh3:
	adrp	x0, l_.str@PAGE
Lloh4:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG
	ldr	w8, [x22]
	cmp	w8, #129
	b.eq	LBB0_3
; %bb.1:
	cmp	w8, #128
	b.ne	LBB0_4
; %bb.2:
Lloh5:
	adrp	x19, l_.str.2@PAGE
Lloh6:
	add	x19, x19, l_.str.2@PAGEOFF
	b	LBB0_5
LBB0_3:
Lloh7:
	adrp	x19, l_.str.1@PAGE
Lloh8:
	add	x19, x19, l_.str.1@PAGEOFF
	b	LBB0_5
LBB0_4:
	bl	_BUG
                                        ; implicit-def: $x19
LBB0_5:
Lloh9:
	adrp	x2, l_.str.3@PAGE
Lloh10:
	add	x2, x2, l_.str.3@PAGEOFF
	add	x0, sp, #10
	mov	w1, #30
	mov	x3, x19
	bl	_snprintf
	add	x21, x22, #48
	ldr	w2, [x22, #80]
	add	x1, sp, #10
	mov	x0, x21
	bl	_request_firmware
	mov	x20, x0
	cbnz	w0, LBB0_9
; %bb.6:
	ldr	x0, [x21]
	bl	_amdgpu_ucode_validate
	mov	x20, x0
	cbnz	w0, LBB0_9
; %bb.7:
	ldr	x8, [x22, #48]
	ldr	x21, [x8]
	ldr	w0, [x21, #8]
	bl	_le32_to_cpu
	str	w0, [x22, #8]
	ldr	w0, [x21, #12]
	bl	_le32_to_cpu
	str	w0, [x22, #12]
	ldr	w0, [x21, #20]
	bl	_le32_to_cpu
	str	w0, [x22, #16]
	ldr	w0, [x21, #4]
	bl	_le32_to_cpu
	mov	x20, x0
	ldr	w0, [x21, #20]
	bl	_le32_to_cpu
	sub	w8, w20, w0
	str	w8, [x22, #20]
	ldr	w0, [x21]
	bl	_le32_to_cpu
	add	x20, x21, w0, sxtw #2
	str	x20, [x22, #64]
	ldr	w0, [x21, #16]
	bl	_le32_to_cpu
	add	x8, x20, w0, sxtw #2
	str	x8, [x22, #72]
Lloh11:
	adrp	x2, l_.str.4@PAGE
Lloh12:
	add	x2, x2, l_.str.4@PAGEOFF
	add	x0, sp, #10
	mov	w1, #30
	mov	x3, x19
	bl	_snprintf
	add	x19, x22, #40
	ldr	w2, [x22, #80]
	add	x1, sp, #10
	mov	x0, x19
	bl	_request_firmware
	mov	x20, x0
	cbnz	w0, LBB0_9
; %bb.8:
	ldr	x0, [x19]
	bl	_amdgpu_ucode_validate
	mov	x20, x0
	cbz	w0, LBB0_12
LBB0_9:
	ldr	w0, [x22, #80]
Lloh13:
	adrp	x1, l_.str.5@PAGE
Lloh14:
	add	x1, x1, l_.str.5@PAGEOFF
	add	x2, sp, #10
	bl	_dev_err
	ldr	x0, [x22, #48]
	bl	_release_firmware
	str	xzr, [x22, #48]
	ldr	x0, [x22, #40]
	bl	_release_firmware
	str	xzr, [x22, #40]
LBB0_10:
	ldr	x8, [sp, #40]
Lloh15:
	adrp	x9, ___stack_chk_guard@GOTPAGE
Lloh16:
	ldr	x9, [x9, ___stack_chk_guard@GOTPAGEOFF]
Lloh17:
	ldr	x9, [x9]
	cmp	x9, x8
	b.ne	LBB0_13
; %bb.11:
	mov	x0, x20
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_12:
	ldr	x8, [x22, #40]
	ldr	x19, [x8]
	ldr	w0, [x19, #8]
	bl	_le32_to_cpu
	str	w0, [x22, #24]
	ldr	w0, [x19, #12]
	bl	_le32_to_cpu
	str	w0, [x22, #28]
	ldr	w0, [x19, #4]
	bl	_le32_to_cpu
	str	w0, [x22, #32]
	ldr	w0, [x19]
	bl	_le32_to_cpu
	add	x8, x19, w0, sxtw #2
	str	x8, [x22, #56]
	b	LBB0_10
LBB0_13:
	bl	___stack_chk_fail
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpAdd	Lloh7, Lloh8
	.loh AdrpAdd	Lloh9, Lloh10
	.loh AdrpAdd	Lloh11, Lloh12
	.loh AdrpAdd	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"\n"

l_.str.1:                               ; @.str.1
	.asciz	"vega10"

l_.str.2:                               ; @.str.2
	.asciz	"vega12"

l_.str.3:                               ; @.str.3
	.asciz	"amdgpu/%s_sos.bin"

l_.str.4:                               ; @.str.4
	.asciz	"amdgpu/%s_asd.bin"

l_.str.5:                               ; @.str.5
	.asciz	"psp v3.1: Failed to load firmware \"%s\"\n"

	.no_dead_strip	_psp_v3_1_init_microcode
.subsections_via_symbols
