	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function npcm7xx_pwm_config_set
_npcm7xx_pwm_config_set:                ## @npcm7xx_pwm_config_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r12
	movl	%esi, %eax
	movq	%rdi, %r13
	movq	_NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE@GOTPCREL(%rip), %rcx
	cltd
	idivl	(%rcx)
	movslq	%edx, %rbx
	movslq	%eax, %r15
	leaq	(,%r15,4), %r14
	movq	(%rdi), %rdi
	addq	%r14, %rdi
	callq	_mutex_lock
	movl	8(%r13), %edi
	movq	%r15, %rsi
	movq	%rbx, %rdx
	callq	_NPCM7XX_PWM_REG_CMRx
	movq	%r12, -48(%rbp)                 ## 8-byte Spill
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_iowrite32
	movl	8(%r13), %edi
	movq	%r15, %rsi
	callq	_NPCM7XX_PWM_REG_CR
	movl	%eax, %edi
	callq	_ioread32
	cmpl	$4, %ebx
	jae	LBB0_1
## %bb.2:
	movq	%rax, %r12
	leaq	l_switch.table.npcm7xx_pwm_config_set(%rip), %rax
	movq	(%rax,%rbx,8), %rcx
	leaq	l_switch.table.npcm7xx_pwm_config_set.1(%rip), %rax
	movq	(%rax,%rbx,8), %rax
	movq	(%rax), %rax
	movq	(%rcx), %rcx
	cmpq	$0, -48(%rbp)                   ## 8-byte Folded Reload
	je	LBB0_3
## %bb.4:
	orq	%r12, %rcx
	notq	%rax
	andq	%rcx, %rax
	movq	%rax, %r12
	jmp	LBB0_5
LBB0_1:
	addq	(%r13), %r14
	movq	%r14, %rdi
	callq	_mutex_unlock
	movq	_ENODEV@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_6
LBB0_3:
	notq	%rcx
	andq	%rcx, %r12
	orq	%rax, %r12
LBB0_5:
	movl	8(%r13), %edi
	movq	%r15, %rsi
	callq	_NPCM7XX_PWM_REG_CR
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_iowrite32
	addq	(%r13), %r14
	movq	%r14, %rdi
	callq	_mutex_unlock
	xorl	%eax, %eax
LBB0_6:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE,4,2 ## @NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE
	.comm	_NPCM7XX_PWM_CTRL_CH0_EN_BIT,8,3 ## @NPCM7XX_PWM_CTRL_CH0_EN_BIT
	.comm	_NPCM7XX_PWM_CTRL_CH0_INV_BIT,8,3 ## @NPCM7XX_PWM_CTRL_CH0_INV_BIT
	.comm	_NPCM7XX_PWM_CTRL_CH1_EN_BIT,8,3 ## @NPCM7XX_PWM_CTRL_CH1_EN_BIT
	.comm	_NPCM7XX_PWM_CTRL_CH1_INV_BIT,8,3 ## @NPCM7XX_PWM_CTRL_CH1_INV_BIT
	.comm	_NPCM7XX_PWM_CTRL_CH2_EN_BIT,8,3 ## @NPCM7XX_PWM_CTRL_CH2_EN_BIT
	.comm	_NPCM7XX_PWM_CTRL_CH2_INV_BIT,8,3 ## @NPCM7XX_PWM_CTRL_CH2_INV_BIT
	.comm	_NPCM7XX_PWM_CTRL_CH3_EN_BIT,8,3 ## @NPCM7XX_PWM_CTRL_CH3_EN_BIT
	.comm	_NPCM7XX_PWM_CTRL_CH3_INV_BIT,8,3 ## @NPCM7XX_PWM_CTRL_CH3_INV_BIT
	.comm	_ENODEV,4,2                     ## @ENODEV
	.no_dead_strip	_npcm7xx_pwm_config_set
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.npcm7xx_pwm_config_set
l_switch.table.npcm7xx_pwm_config_set:
	.quad	_NPCM7XX_PWM_CTRL_CH0_EN_BIT
	.quad	_NPCM7XX_PWM_CTRL_CH1_EN_BIT
	.quad	_NPCM7XX_PWM_CTRL_CH2_EN_BIT
	.quad	_NPCM7XX_PWM_CTRL_CH3_EN_BIT

	.p2align	3                               ## @switch.table.npcm7xx_pwm_config_set.1
l_switch.table.npcm7xx_pwm_config_set.1:
	.quad	_NPCM7XX_PWM_CTRL_CH0_INV_BIT
	.quad	_NPCM7XX_PWM_CTRL_CH1_INV_BIT
	.quad	_NPCM7XX_PWM_CTRL_CH2_INV_BIT
	.quad	_NPCM7XX_PWM_CTRL_CH3_INV_BIT

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function npcm7xx_pwm_config_set
_npcm7xx_pwm_config_set:                ; @npcm7xx_pwm_config_set
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x21, x2
	mov	x19, x0
Lloh0:
	adrp	x8, _NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	sdiv	w9, w1, w8
	msub	w23, w9, w8, w1
	sxtw	x22, w23
	sxtw	x20, w9
	ldr	x8, [x0]
	add	x0, x8, w9, sxtw #2
	bl	_mutex_lock
	ldr	w0, [x19, #8]
	mov	x1, x20
	mov	x2, x22
	bl	_NPCM7XX_PWM_REG_CMRx
	mov	x1, x0
	mov	x0, x21
	bl	_iowrite32
	ldr	w0, [x19, #8]
	mov	x1, x20
	bl	_NPCM7XX_PWM_REG_CR
	bl	_ioread32
	cmp	w23, #4
	b.hs	LBB0_2
; %bb.1:
	lsl	x8, x22, #3
Lloh3:
	adrp	x9, l_switch.table.npcm7xx_pwm_config_set@PAGE
Lloh4:
	add	x9, x9, l_switch.table.npcm7xx_pwm_config_set@PAGEOFF
	ldr	x9, [x9, x8]
Lloh5:
	adrp	x10, l_switch.table.npcm7xx_pwm_config_set.1@PAGE
Lloh6:
	add	x10, x10, l_switch.table.npcm7xx_pwm_config_set.1@PAGEOFF
	ldr	x8, [x10, x8]
	ldr	x8, [x8]
	ldr	x9, [x9]
	orr	x10, x9, x0
	bic	x10, x10, x8
	bic	x9, x0, x9
	orr	x8, x9, x8
	cmp	x21, #0
	csel	x21, x10, x8, ne
	ldr	w0, [x19, #8]
	mov	x1, x20
	bl	_NPCM7XX_PWM_REG_CR
	mov	x1, x0
	mov	x0, x21
	bl	_iowrite32
	ldr	x8, [x19]
	add	x0, x8, x20, lsl #2
	bl	_mutex_unlock
	mov	w0, #0
	b	LBB0_3
LBB0_2:
	ldr	x8, [x19]
	add	x0, x8, x20, lsl #2
	bl	_mutex_unlock
Lloh7:
	adrp	x8, _ENODEV@GOTPAGE
Lloh8:
	ldr	x8, [x8, _ENODEV@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_3:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.cfi_endproc
                                        ; -- End function
	.comm	_NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE,4,2 ; @NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE
	.comm	_NPCM7XX_PWM_CTRL_CH0_EN_BIT,8,3 ; @NPCM7XX_PWM_CTRL_CH0_EN_BIT
	.comm	_NPCM7XX_PWM_CTRL_CH0_INV_BIT,8,3 ; @NPCM7XX_PWM_CTRL_CH0_INV_BIT
	.comm	_NPCM7XX_PWM_CTRL_CH1_EN_BIT,8,3 ; @NPCM7XX_PWM_CTRL_CH1_EN_BIT
	.comm	_NPCM7XX_PWM_CTRL_CH1_INV_BIT,8,3 ; @NPCM7XX_PWM_CTRL_CH1_INV_BIT
	.comm	_NPCM7XX_PWM_CTRL_CH2_EN_BIT,8,3 ; @NPCM7XX_PWM_CTRL_CH2_EN_BIT
	.comm	_NPCM7XX_PWM_CTRL_CH2_INV_BIT,8,3 ; @NPCM7XX_PWM_CTRL_CH2_INV_BIT
	.comm	_NPCM7XX_PWM_CTRL_CH3_EN_BIT,8,3 ; @NPCM7XX_PWM_CTRL_CH3_EN_BIT
	.comm	_NPCM7XX_PWM_CTRL_CH3_INV_BIT,8,3 ; @NPCM7XX_PWM_CTRL_CH3_INV_BIT
	.comm	_ENODEV,4,2                     ; @ENODEV
	.no_dead_strip	_npcm7xx_pwm_config_set
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.npcm7xx_pwm_config_set
l_switch.table.npcm7xx_pwm_config_set:
	.quad	_NPCM7XX_PWM_CTRL_CH0_EN_BIT
	.quad	_NPCM7XX_PWM_CTRL_CH1_EN_BIT
	.quad	_NPCM7XX_PWM_CTRL_CH2_EN_BIT
	.quad	_NPCM7XX_PWM_CTRL_CH3_EN_BIT

	.p2align	3                               ; @switch.table.npcm7xx_pwm_config_set.1
l_switch.table.npcm7xx_pwm_config_set.1:
	.quad	_NPCM7XX_PWM_CTRL_CH0_INV_BIT
	.quad	_NPCM7XX_PWM_CTRL_CH1_INV_BIT
	.quad	_NPCM7XX_PWM_CTRL_CH2_INV_BIT
	.quad	_NPCM7XX_PWM_CTRL_CH3_INV_BIT

.subsections_via_symbols
