	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r600_irq_init                  ## -- Begin function r600_irq_init
	.p2align	4, 0x90
_r600_irq_init:                         ## @r600_irq_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	callq	_r600_ih_ring_alloc
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_14
## %bb.1:
	movq	%r15, %rdi
	callq	_r600_disable_interrupts
	movq	(%r15), %rax
	movq	_CHIP_CEDAR@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_2
## %bb.3:
	movq	%r15, %rdi
	callq	_r600_rlc_resume
	jmp	LBB0_4
LBB0_2:
	movq	%r15, %rdi
	callq	_evergreen_rlc_resume
LBB0_4:
	movl	%eax, %ebx
	testl	%eax, %eax
	je	LBB0_6
## %bb.5:
	movq	%r15, %rdi
	callq	_r600_ih_ring_fini
	jmp	LBB0_14
LBB0_6:
	movq	_INTERRUPT_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	40(%r15), %esi
	sarl	$8, %esi
	callq	_WREG32
	movq	_INTERRUPT_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_IH_DUMMY_RD_OVERRIDE@GOTPCREL(%rip), %rcx
	movq	_IH_REQ_NONSNOOP_EN@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32
	movq	_IH_RB_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	40(%r15), %esi
	sarl	$8, %esi
	callq	_WREG32
	movl	44(%r15), %eax
	leal	3(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$2, %edi
	callq	_order_base_2
	movl	%eax, %r14d
	movq	_IH_WPTR_OVERFLOW_ENABLE@GOTPCREL(%rip), %rcx
	movq	_IH_WPTR_OVERFLOW_CLEAR@GOTPCREL(%rip), %rax
	addl	%r14d, %r14d
	xorl	%r13d, %r13d
	cmpq	$0, 32(%r15)
	movl	$0, %edx
	je	LBB0_8
## %bb.7:
	movq	_IH_WPTR_WRITEBACK_ENABLE@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
LBB0_8:
	orl	(%rcx), %r14d
	orl	(%rax), %r14d
	orl	%edx, %r14d
	movq	_IH_RB_WPTR_ADDR_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_R600_WB_IH_WPTR_OFFSET@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	addl	24(%r15), %esi
	andl	$-4, %esi
	callq	_WREG32
	movq	_IH_RB_WPTR_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	(%r12), %edi
	addl	24(%r15), %edi
	callq	_upper_32_bits
	movzbl	%al, %esi
	movl	%ebx, %edi
	callq	_WREG32
	movq	_IH_RB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_WREG32
	movq	_IH_RB_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_IH_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	$16, %edi
	callq	_MC_WRREQ_CREDIT
	movl	%eax, %ebx
	movl	$16, %edi
	callq	_MC_WR_CLEAN_CNT
	orl	%ebx, %eax
	cmpq	$0, 16(%r15)
	je	LBB0_10
## %bb.9:
	movq	_RPTR_REARM@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r13d
LBB0_10:
	orl	%r13d, %eax
	movq	_IH_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	(%r15), %rax
	movq	_CHIP_CEDAR@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_11
## %bb.12:
	movq	%r15, %rdi
	callq	_r600_disable_interrupt_state
	jmp	LBB0_13
LBB0_11:
	movq	%r15, %rdi
	callq	_evergreen_disable_interrupt_state
LBB0_13:
	movl	8(%r15), %edi
	callq	_pci_set_master
	movq	%r15, %rdi
	callq	_r600_enable_interrupts
	xorl	%ebx, %ebx
LBB0_14:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CHIP_CEDAR,8,3                 ## @CHIP_CEDAR
	.comm	_INTERRUPT_CNTL2,4,2            ## @INTERRUPT_CNTL2
	.comm	_INTERRUPT_CNTL,4,2             ## @INTERRUPT_CNTL
	.comm	_IH_DUMMY_RD_OVERRIDE,4,2       ## @IH_DUMMY_RD_OVERRIDE
	.comm	_IH_REQ_NONSNOOP_EN,4,2         ## @IH_REQ_NONSNOOP_EN
	.comm	_IH_RB_BASE,4,2                 ## @IH_RB_BASE
	.comm	_IH_WPTR_OVERFLOW_ENABLE,4,2    ## @IH_WPTR_OVERFLOW_ENABLE
	.comm	_IH_WPTR_OVERFLOW_CLEAR,4,2     ## @IH_WPTR_OVERFLOW_CLEAR
	.comm	_IH_WPTR_WRITEBACK_ENABLE,4,2   ## @IH_WPTR_WRITEBACK_ENABLE
	.comm	_IH_RB_WPTR_ADDR_LO,4,2         ## @IH_RB_WPTR_ADDR_LO
	.comm	_R600_WB_IH_WPTR_OFFSET,4,2     ## @R600_WB_IH_WPTR_OFFSET
	.comm	_IH_RB_WPTR_ADDR_HI,4,2         ## @IH_RB_WPTR_ADDR_HI
	.comm	_IH_RB_CNTL,4,2                 ## @IH_RB_CNTL
	.comm	_IH_RB_RPTR,4,2                 ## @IH_RB_RPTR
	.comm	_IH_RB_WPTR,4,2                 ## @IH_RB_WPTR
	.comm	_RPTR_REARM,4,2                 ## @RPTR_REARM
	.comm	_IH_CNTL,4,2                    ## @IH_CNTL
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_r600_irq_init                  ; -- Begin function r600_irq_init
	.p2align	2
_r600_irq_init:                         ; @r600_irq_init
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	bl	_r600_ih_ring_alloc
	mov	x20, x0
	cbnz	w0, LBB0_9
; %bb.1:
	mov	x0, x19
	bl	_r600_disable_interrupts
	ldr	x8, [x19]
Lloh0:
	adrp	x22, _CHIP_CEDAR@GOTPAGE
Lloh1:
	ldr	x22, [x22, _CHIP_CEDAR@GOTPAGEOFF]
	ldr	x9, [x22]
	mov	x0, x19
	cmp	x8, x9
	b.ge	LBB0_4
; %bb.2:
	bl	_r600_rlc_resume
	mov	x20, x0
	cbz	w0, LBB0_5
LBB0_3:
	mov	x0, x19
	bl	_r600_ih_ring_fini
	b	LBB0_9
LBB0_4:
	bl	_evergreen_rlc_resume
	mov	x20, x0
	cbnz	w0, LBB0_3
LBB0_5:
Lloh2:
	adrp	x8, _INTERRUPT_CNTL2@GOTPAGE
Lloh3:
	ldr	x8, [x8, _INTERRUPT_CNTL2@GOTPAGEOFF]
Lloh4:
	ldr	w0, [x8]
	ldr	w8, [x19, #40]
	asr	w1, w8, #8
	bl	_WREG32
Lloh5:
	adrp	x20, _INTERRUPT_CNTL@GOTPAGE
Lloh6:
	ldr	x20, [x20, _INTERRUPT_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh7:
	adrp	x8, _IH_DUMMY_RD_OVERRIDE@GOTPAGE
Lloh8:
	ldr	x8, [x8, _IH_DUMMY_RD_OVERRIDE@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
Lloh10:
	adrp	x9, _IH_REQ_NONSNOOP_EN@GOTPAGE
Lloh11:
	ldr	x9, [x9, _IH_REQ_NONSNOOP_EN@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32
Lloh13:
	adrp	x8, _IH_RB_BASE@GOTPAGE
Lloh14:
	ldr	x8, [x8, _IH_RB_BASE@GOTPAGEOFF]
Lloh15:
	ldr	w0, [x8]
	ldr	w8, [x19, #40]
	asr	w1, w8, #8
	bl	_WREG32
	ldr	w8, [x19, #44]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #2
	bl	_order_base_2
Lloh16:
	adrp	x8, _IH_WPTR_OVERFLOW_ENABLE@GOTPAGE
Lloh17:
	ldr	x8, [x8, _IH_WPTR_OVERFLOW_ENABLE@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
Lloh19:
	adrp	x9, _IH_WPTR_OVERFLOW_CLEAR@GOTPAGE
Lloh20:
	ldr	x9, [x9, _IH_WPTR_OVERFLOW_CLEAR@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	ldr	x10, [x19, #32]
Lloh22:
	adrp	x11, _IH_WPTR_WRITEBACK_ENABLE@GOTPAGE
Lloh23:
	ldr	x11, [x11, _IH_WPTR_WRITEBACK_ENABLE@GOTPAGEOFF]
Lloh24:
	ldr	w11, [x11]
	cmp	x10, #0
	csel	w10, wzr, w11, eq
	orr	w8, w8, w0, lsl #1
	orr	w8, w8, w9
	orr	w20, w8, w10
Lloh25:
	adrp	x8, _IH_RB_WPTR_ADDR_LO@GOTPAGE
Lloh26:
	ldr	x8, [x8, _IH_RB_WPTR_ADDR_LO@GOTPAGEOFF]
Lloh27:
	ldr	w0, [x8]
	ldr	w8, [x19, #24]
Lloh28:
	adrp	x23, _R600_WB_IH_WPTR_OFFSET@GOTPAGE
Lloh29:
	ldr	x23, [x23, _R600_WB_IH_WPTR_OFFSET@GOTPAGEOFF]
	ldr	w9, [x23]
	add	w8, w9, w8
	and	w1, w8, #0xfffffffc
	bl	_WREG32
Lloh30:
	adrp	x8, _IH_RB_WPTR_ADDR_HI@GOTPAGE
Lloh31:
	ldr	x8, [x8, _IH_RB_WPTR_ADDR_HI@GOTPAGEOFF]
Lloh32:
	ldr	w21, [x8]
	ldr	w8, [x19, #24]
	ldr	w9, [x23]
	add	w0, w9, w8
	bl	_upper_32_bits
	and	w1, w0, #0xff
	mov	x0, x21
	bl	_WREG32
Lloh33:
	adrp	x8, _IH_RB_CNTL@GOTPAGE
Lloh34:
	ldr	x8, [x8, _IH_RB_CNTL@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh36:
	adrp	x8, _IH_RB_RPTR@GOTPAGE
Lloh37:
	ldr	x8, [x8, _IH_RB_RPTR@GOTPAGEOFF]
Lloh38:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh39:
	adrp	x8, _IH_RB_WPTR@GOTPAGE
Lloh40:
	ldr	x8, [x8, _IH_RB_WPTR@GOTPAGEOFF]
Lloh41:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	mov	w0, #16
	bl	_MC_WRREQ_CREDIT
	mov	x20, x0
	mov	w0, #16
	bl	_MC_WR_CLEAN_CNT
	orr	w8, w0, w20
	ldr	x9, [x19, #16]
Lloh42:
	adrp	x10, _RPTR_REARM@GOTPAGE
Lloh43:
	ldr	x10, [x10, _RPTR_REARM@GOTPAGEOFF]
Lloh44:
	ldr	w10, [x10]
	cmp	x9, #0
	csel	w9, wzr, w10, eq
	orr	w1, w8, w9
Lloh45:
	adrp	x8, _IH_CNTL@GOTPAGE
Lloh46:
	ldr	x8, [x8, _IH_CNTL@GOTPAGEOFF]
Lloh47:
	ldr	w0, [x8]
	bl	_WREG32
	ldr	x8, [x19]
	ldr	x9, [x22]
	mov	x0, x19
	cmp	x8, x9
	b.ge	LBB0_7
; %bb.6:
	bl	_r600_disable_interrupt_state
	b	LBB0_8
LBB0_7:
	bl	_evergreen_disable_interrupt_state
LBB0_8:
	ldr	w0, [x19, #8]
	bl	_pci_set_master
	mov	x0, x19
	bl	_r600_enable_interrupts
	mov	w20, #0
LBB0_9:
	mov	x0, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_CHIP_CEDAR,8,3                 ; @CHIP_CEDAR
	.comm	_INTERRUPT_CNTL2,4,2            ; @INTERRUPT_CNTL2
	.comm	_INTERRUPT_CNTL,4,2             ; @INTERRUPT_CNTL
	.comm	_IH_DUMMY_RD_OVERRIDE,4,2       ; @IH_DUMMY_RD_OVERRIDE
	.comm	_IH_REQ_NONSNOOP_EN,4,2         ; @IH_REQ_NONSNOOP_EN
	.comm	_IH_RB_BASE,4,2                 ; @IH_RB_BASE
	.comm	_IH_WPTR_OVERFLOW_ENABLE,4,2    ; @IH_WPTR_OVERFLOW_ENABLE
	.comm	_IH_WPTR_OVERFLOW_CLEAR,4,2     ; @IH_WPTR_OVERFLOW_CLEAR
	.comm	_IH_WPTR_WRITEBACK_ENABLE,4,2   ; @IH_WPTR_WRITEBACK_ENABLE
	.comm	_IH_RB_WPTR_ADDR_LO,4,2         ; @IH_RB_WPTR_ADDR_LO
	.comm	_R600_WB_IH_WPTR_OFFSET,4,2     ; @R600_WB_IH_WPTR_OFFSET
	.comm	_IH_RB_WPTR_ADDR_HI,4,2         ; @IH_RB_WPTR_ADDR_HI
	.comm	_IH_RB_CNTL,4,2                 ; @IH_RB_CNTL
	.comm	_IH_RB_RPTR,4,2                 ; @IH_RB_RPTR
	.comm	_IH_RB_WPTR,4,2                 ; @IH_RB_WPTR
	.comm	_RPTR_REARM,4,2                 ; @RPTR_REARM
	.comm	_IH_CNTL,4,2                    ; @IH_CNTL
.subsections_via_symbols
