	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mtk_mipi_tx_pll_prepare
_mtk_mipi_tx_pll_prepare:               ## @mtk_mipi_tx_pll_prepare
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	callq	_mtk_mipi_tx_from_clk_hw
	movq	%rax, %rbx
	movl	(%rax), %edx
	movl	24(%rax), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_dbg
	movl	(%rbx), %ecx
	movl	$33554432, %r12d                ## imm = 0x2000000
	movl	$0, %r15d
	movl	$0, %eax
	cmpl	$499999999, %ecx                ## imm = 0x1DCD64FF
	jg	LBB0_9
## %bb.1:
	cmpl	$249999999, %ecx                ## imm = 0xEE6B27F
	jle	LBB0_3
## %bb.2:
	movl	$8, %r15d
	movl	$67108864, %r12d                ## imm = 0x4000000
	xorl	%eax, %eax
	jmp	LBB0_9
LBB0_3:
	movl	$16, %r15d
	movl	$134217728, %r12d               ## imm = 0x8000000
	cmpl	$124999999, %ecx                ## imm = 0x773593F
	jle	LBB0_5
## %bb.4:
	xorl	%eax, %eax
	jmp	LBB0_9
LBB0_5:
	cmpl	$62000000, %ecx                 ## imm = 0x3B20B80
	jle	LBB0_7
## %bb.6:
	movl	$32, %eax
	movl	$268435456, %r12d               ## imm = 0x10000000
	jmp	LBB0_9
LBB0_7:
	cmpl	$49999999, %ecx                 ## imm = 0x2FAF07F
	jle	LBB0_11
## %bb.8:
	movl	$64, %eax
	movl	$536870912, %r12d               ## imm = 0x20000000
LBB0_9:
	orl	%eax, %r15d
	movq	_MIPITX_DSI_BG_CON@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_RG_DSI_BG_CKEN@GOTPCREL(%rip), %rax
	movq	_RG_DSI_BG_CORE_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	_RG_DSI_VOUT_MSK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	orl	%ecx, %edx
	orl	$4793472, %ecx                  ## imm = 0x492480
	movq	%rbx, %rdi
	callq	_mtk_mipi_tx_update_bits
	movl	$30, %edi
	movl	$100, %esi
	callq	_usleep_range
	movq	_MIPITX_DSI_TOP_CON@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_RG_DSI_LNT_IMP_CAL_CODE@GOTPCREL(%rip), %rax
	movq	_RG_DSI_LNT_HS_BIAS_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	(%rax), %edx
	orl	%ecx, %edx
	orl	$128, %ecx
	movq	%rbx, %rdi
	callq	_mtk_mipi_tx_update_bits
	movq	_MIPITX_DSI_CON@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_RG_DSI_CKG_LDOOUT_EN@GOTPCREL(%rip), %rax
	movq	_RG_DSI_LDOCORE_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_mtk_mipi_tx_set_bits
	movq	_MIPITX_DSI_PLL_PWR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_RG_DSI_MPPLL_SDM_PWR_ON@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	_RG_DSI_MPPLL_SDM_ISO_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	orl	%ecx, %edx
	movq	%rbx, %rdi
	callq	_mtk_mipi_tx_update_bits
	movq	_MIPITX_DSI_PLL_CON0@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	_RG_DSI_MPPLL_PLL_EN@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	movq	%rbx, %rdi
	callq	_mtk_mipi_tx_clear_bits
	movq	_RG_DSI_MPPLL_TXDIV0@GOTPCREL(%rip), %rax
	movq	_RG_DSI_MPPLL_TXDIV1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movl	(%r13), %esi
	movq	_RG_DSI_MPPLL_PREDIV@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	%rbx, %rdi
	movl	%r15d, %ecx
	callq	_mtk_mipi_tx_update_bits
	imull	(%rbx), %r12d
	movl	%r12d, %edi
	movl	$26000000, %esi                 ## imm = 0x18CBA80
	callq	_div_u64
	movq	_MIPITX_DSI_PLL_CON2@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rsi
	addq	16(%rbx), %rsi
	movl	%eax, %edi
	callq	_writel
	movq	_MIPITX_DSI_PLL_CON1@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_RG_DSI_MPPLL_SDM_FRA_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_mtk_mipi_tx_set_bits
	movl	(%r13), %esi
	movl	(%r14), %edx
	movq	%rbx, %rdi
	callq	_mtk_mipi_tx_set_bits
	movl	$20, %edi
	movl	$100, %esi
	callq	_usleep_range
	movl	(%r15), %esi
	movq	_RG_DSI_MPPLL_SDM_SSC_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_mtk_mipi_tx_clear_bits
	movq	_MIPITX_DSI_PLL_TOP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_RG_DSI_MPPLL_PRESERVE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	8(%rbx), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	callq	_mtk_mipi_tx_update_bits
	xorl	%eax, %eax
LBB0_10:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_11:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_10
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"prepare: %u Hz\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_MIPITX_DSI_BG_CON,4,2          ## @MIPITX_DSI_BG_CON
	.comm	_RG_DSI_VOUT_MSK,4,2            ## @RG_DSI_VOUT_MSK
	.comm	_RG_DSI_BG_CKEN,4,2             ## @RG_DSI_BG_CKEN
	.comm	_RG_DSI_BG_CORE_EN,4,2          ## @RG_DSI_BG_CORE_EN
	.comm	_MIPITX_DSI_TOP_CON,4,2         ## @MIPITX_DSI_TOP_CON
	.comm	_RG_DSI_LNT_IMP_CAL_CODE,4,2    ## @RG_DSI_LNT_IMP_CAL_CODE
	.comm	_RG_DSI_LNT_HS_BIAS_EN,4,2      ## @RG_DSI_LNT_HS_BIAS_EN
	.comm	_MIPITX_DSI_CON,4,2             ## @MIPITX_DSI_CON
	.comm	_RG_DSI_CKG_LDOOUT_EN,4,2       ## @RG_DSI_CKG_LDOOUT_EN
	.comm	_RG_DSI_LDOCORE_EN,4,2          ## @RG_DSI_LDOCORE_EN
	.comm	_MIPITX_DSI_PLL_PWR,4,2         ## @MIPITX_DSI_PLL_PWR
	.comm	_RG_DSI_MPPLL_SDM_PWR_ON,4,2    ## @RG_DSI_MPPLL_SDM_PWR_ON
	.comm	_RG_DSI_MPPLL_SDM_ISO_EN,4,2    ## @RG_DSI_MPPLL_SDM_ISO_EN
	.comm	_MIPITX_DSI_PLL_CON0,4,2        ## @MIPITX_DSI_PLL_CON0
	.comm	_RG_DSI_MPPLL_PLL_EN,4,2        ## @RG_DSI_MPPLL_PLL_EN
	.comm	_RG_DSI_MPPLL_TXDIV0,4,2        ## @RG_DSI_MPPLL_TXDIV0
	.comm	_RG_DSI_MPPLL_TXDIV1,4,2        ## @RG_DSI_MPPLL_TXDIV1
	.comm	_RG_DSI_MPPLL_PREDIV,4,2        ## @RG_DSI_MPPLL_PREDIV
	.comm	_MIPITX_DSI_PLL_CON2,8,3        ## @MIPITX_DSI_PLL_CON2
	.comm	_MIPITX_DSI_PLL_CON1,4,2        ## @MIPITX_DSI_PLL_CON1
	.comm	_RG_DSI_MPPLL_SDM_FRA_EN,4,2    ## @RG_DSI_MPPLL_SDM_FRA_EN
	.comm	_RG_DSI_MPPLL_SDM_SSC_EN,4,2    ## @RG_DSI_MPPLL_SDM_SSC_EN
	.comm	_MIPITX_DSI_PLL_TOP,4,2         ## @MIPITX_DSI_PLL_TOP
	.comm	_RG_DSI_MPPLL_PRESERVE,4,2      ## @RG_DSI_MPPLL_PRESERVE
	.no_dead_strip	_mtk_mipi_tx_pll_prepare
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mtk_mipi_tx_pll_prepare
_mtk_mipi_tx_pll_prepare:               ; @mtk_mipi_tx_pll_prepare
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	bl	_mtk_mipi_tx_from_clk_hw
	mov	x19, x0
	ldr	w0, [x0, #24]
	ldr	w2, [x19]
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_dbg
	ldr	w8, [x19]
	mov	w9, #25855
	movk	w9, #7629, lsl #16
	cmp	w8, w9
	b.le	LBB0_2
; %bb.1:
	mov	w21, #0
	mov	w20, #0
	mov	w22, #33554432
	b	LBB0_10
LBB0_2:
	mov	w9, #45695
	movk	w9, #3814, lsl #16
	cmp	w8, w9
	b.le	LBB0_4
; %bb.3:
	mov	w20, #0
	mov	w21, #8
	mov	w22, #67108864
	b	LBB0_10
LBB0_4:
	mov	w9, #22847
	movk	w9, #1907, lsl #16
	cmp	w8, w9
	b.le	LBB0_6
; %bb.5:
	mov	w20, #0
	mov	w21, #16
	mov	w22, #134217728
	b	LBB0_10
LBB0_6:
	mov	w9, #2944
	movk	w9, #946, lsl #16
	cmp	w8, w9
	b.le	LBB0_8
; %bb.7:
	mov	w20, #32
	mov	w21, #16
	mov	w22, #268435456
	b	LBB0_10
LBB0_8:
	mov	w9, #61567
	movk	w9, #762, lsl #16
	cmp	w8, w9
	b.le	LBB0_12
; %bb.9:
	mov	w20, #64
	mov	w21, #16
	mov	w22, #536870912
LBB0_10:
Lloh2:
	adrp	x8, _MIPITX_DSI_BG_CON@GOTPAGE
Lloh3:
	ldr	x8, [x8, _MIPITX_DSI_BG_CON@GOTPAGEOFF]
Lloh4:
	adrp	x9, _RG_DSI_VOUT_MSK@GOTPAGE
Lloh5:
	ldr	x9, [x9, _RG_DSI_VOUT_MSK@GOTPAGEOFF]
Lloh6:
	ldr	w1, [x8]
Lloh7:
	ldr	w8, [x9]
Lloh8:
	adrp	x9, _RG_DSI_BG_CKEN@GOTPAGE
Lloh9:
	ldr	x9, [x9, _RG_DSI_BG_CKEN@GOTPAGEOFF]
Lloh10:
	adrp	x10, _RG_DSI_BG_CORE_EN@GOTPAGE
Lloh11:
	ldr	x10, [x10, _RG_DSI_BG_CORE_EN@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
Lloh13:
	ldr	w10, [x10]
	orr	w9, w10, w9
	orr	w2, w9, w8
	mov	w8, #9344
	movk	w8, #73, lsl #16
	orr	w3, w9, w8
	mov	x0, x19
	bl	_mtk_mipi_tx_update_bits
	mov	w0, #30
	mov	w1, #100
	bl	_usleep_range
Lloh14:
	adrp	x8, _MIPITX_DSI_TOP_CON@GOTPAGE
Lloh15:
	ldr	x8, [x8, _MIPITX_DSI_TOP_CON@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
Lloh17:
	adrp	x8, _RG_DSI_LNT_IMP_CAL_CODE@GOTPAGE
Lloh18:
	ldr	x8, [x8, _RG_DSI_LNT_IMP_CAL_CODE@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
Lloh20:
	adrp	x9, _RG_DSI_LNT_HS_BIAS_EN@GOTPAGE
Lloh21:
	ldr	x9, [x9, _RG_DSI_LNT_HS_BIAS_EN@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	orr	w2, w9, w8
	orr	w3, w9, #0x80
	mov	x0, x19
	bl	_mtk_mipi_tx_update_bits
Lloh23:
	adrp	x8, _MIPITX_DSI_CON@GOTPAGE
Lloh24:
	ldr	x8, [x8, _MIPITX_DSI_CON@GOTPAGEOFF]
Lloh25:
	adrp	x9, _RG_DSI_CKG_LDOOUT_EN@GOTPAGE
Lloh26:
	ldr	x9, [x9, _RG_DSI_CKG_LDOOUT_EN@GOTPAGEOFF]
Lloh27:
	ldr	w1, [x8]
Lloh28:
	ldr	w8, [x9]
Lloh29:
	adrp	x9, _RG_DSI_LDOCORE_EN@GOTPAGE
Lloh30:
	ldr	x9, [x9, _RG_DSI_LDOCORE_EN@GOTPAGEOFF]
Lloh31:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_mtk_mipi_tx_set_bits
Lloh32:
	adrp	x8, _MIPITX_DSI_PLL_PWR@GOTPAGE
Lloh33:
	ldr	x8, [x8, _MIPITX_DSI_PLL_PWR@GOTPAGEOFF]
Lloh34:
	adrp	x9, _RG_DSI_MPPLL_SDM_PWR_ON@GOTPAGE
Lloh35:
	ldr	x9, [x9, _RG_DSI_MPPLL_SDM_PWR_ON@GOTPAGEOFF]
Lloh36:
	ldr	w1, [x8]
Lloh37:
	ldr	w3, [x9]
Lloh38:
	adrp	x8, _RG_DSI_MPPLL_SDM_ISO_EN@GOTPAGE
Lloh39:
	ldr	x8, [x8, _RG_DSI_MPPLL_SDM_ISO_EN@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
	orr	w2, w8, w3
	mov	x0, x19
	bl	_mtk_mipi_tx_update_bits
Lloh41:
	adrp	x23, _MIPITX_DSI_PLL_CON0@GOTPAGE
Lloh42:
	ldr	x23, [x23, _MIPITX_DSI_PLL_CON0@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh43:
	adrp	x24, _RG_DSI_MPPLL_PLL_EN@GOTPAGE
Lloh44:
	ldr	x24, [x24, _RG_DSI_MPPLL_PLL_EN@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	x0, x19
	bl	_mtk_mipi_tx_clear_bits
	ldr	w1, [x23]
Lloh45:
	adrp	x8, _RG_DSI_MPPLL_TXDIV0@GOTPAGE
Lloh46:
	ldr	x8, [x8, _RG_DSI_MPPLL_TXDIV0@GOTPAGEOFF]
Lloh47:
	ldr	w8, [x8]
Lloh48:
	adrp	x9, _RG_DSI_MPPLL_TXDIV1@GOTPAGE
Lloh49:
	ldr	x9, [x9, _RG_DSI_MPPLL_TXDIV1@GOTPAGEOFF]
Lloh50:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh51:
	adrp	x9, _RG_DSI_MPPLL_PREDIV@GOTPAGE
Lloh52:
	ldr	x9, [x9, _RG_DSI_MPPLL_PREDIV@GOTPAGEOFF]
Lloh53:
	ldr	w9, [x9]
	orr	w2, w8, w9
	orr	w3, w20, w21
	mov	x0, x19
	bl	_mtk_mipi_tx_update_bits
	ldr	w8, [x19]
	mul	w0, w22, w8
	mov	w1, #47744
	movk	w1, #396, lsl #16
	bl	_div_u64
	ldr	x8, [x19, #16]
Lloh54:
	adrp	x9, _MIPITX_DSI_PLL_CON2@GOTPAGE
Lloh55:
	ldr	x9, [x9, _MIPITX_DSI_PLL_CON2@GOTPAGEOFF]
Lloh56:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
Lloh57:
	adrp	x20, _MIPITX_DSI_PLL_CON1@GOTPAGE
Lloh58:
	ldr	x20, [x20, _MIPITX_DSI_PLL_CON1@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh59:
	adrp	x8, _RG_DSI_MPPLL_SDM_FRA_EN@GOTPAGE
Lloh60:
	ldr	x8, [x8, _RG_DSI_MPPLL_SDM_FRA_EN@GOTPAGEOFF]
Lloh61:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mtk_mipi_tx_set_bits
	ldr	w1, [x23]
	ldr	w2, [x24]
	mov	x0, x19
	bl	_mtk_mipi_tx_set_bits
	mov	w0, #20
	mov	w1, #100
	bl	_usleep_range
	ldr	w1, [x20]
Lloh62:
	adrp	x8, _RG_DSI_MPPLL_SDM_SSC_EN@GOTPAGE
Lloh63:
	ldr	x8, [x8, _RG_DSI_MPPLL_SDM_SSC_EN@GOTPAGEOFF]
Lloh64:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mtk_mipi_tx_clear_bits
Lloh65:
	adrp	x8, _MIPITX_DSI_PLL_TOP@GOTPAGE
Lloh66:
	ldr	x8, [x8, _MIPITX_DSI_PLL_TOP@GOTPAGEOFF]
Lloh67:
	ldr	w1, [x8]
Lloh68:
	adrp	x8, _RG_DSI_MPPLL_PRESERVE@GOTPAGE
Lloh69:
	ldr	x8, [x8, _RG_DSI_MPPLL_PRESERVE@GOTPAGEOFF]
Lloh70:
	ldr	w2, [x8]
	ldr	x8, [x19, #8]
	ldr	w3, [x8]
	mov	x0, x19
	bl	_mtk_mipi_tx_update_bits
	mov	w0, #0
LBB0_11:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_12:
Lloh71:
	adrp	x8, _EINVAL@GOTPAGE
Lloh72:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh73:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_11
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh36
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh27
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh12
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh6
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"prepare: %u Hz\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_MIPITX_DSI_BG_CON,4,2          ; @MIPITX_DSI_BG_CON
	.comm	_RG_DSI_VOUT_MSK,4,2            ; @RG_DSI_VOUT_MSK
	.comm	_RG_DSI_BG_CKEN,4,2             ; @RG_DSI_BG_CKEN
	.comm	_RG_DSI_BG_CORE_EN,4,2          ; @RG_DSI_BG_CORE_EN
	.comm	_MIPITX_DSI_TOP_CON,4,2         ; @MIPITX_DSI_TOP_CON
	.comm	_RG_DSI_LNT_IMP_CAL_CODE,4,2    ; @RG_DSI_LNT_IMP_CAL_CODE
	.comm	_RG_DSI_LNT_HS_BIAS_EN,4,2      ; @RG_DSI_LNT_HS_BIAS_EN
	.comm	_MIPITX_DSI_CON,4,2             ; @MIPITX_DSI_CON
	.comm	_RG_DSI_CKG_LDOOUT_EN,4,2       ; @RG_DSI_CKG_LDOOUT_EN
	.comm	_RG_DSI_LDOCORE_EN,4,2          ; @RG_DSI_LDOCORE_EN
	.comm	_MIPITX_DSI_PLL_PWR,4,2         ; @MIPITX_DSI_PLL_PWR
	.comm	_RG_DSI_MPPLL_SDM_PWR_ON,4,2    ; @RG_DSI_MPPLL_SDM_PWR_ON
	.comm	_RG_DSI_MPPLL_SDM_ISO_EN,4,2    ; @RG_DSI_MPPLL_SDM_ISO_EN
	.comm	_MIPITX_DSI_PLL_CON0,4,2        ; @MIPITX_DSI_PLL_CON0
	.comm	_RG_DSI_MPPLL_PLL_EN,4,2        ; @RG_DSI_MPPLL_PLL_EN
	.comm	_RG_DSI_MPPLL_TXDIV0,4,2        ; @RG_DSI_MPPLL_TXDIV0
	.comm	_RG_DSI_MPPLL_TXDIV1,4,2        ; @RG_DSI_MPPLL_TXDIV1
	.comm	_RG_DSI_MPPLL_PREDIV,4,2        ; @RG_DSI_MPPLL_PREDIV
	.comm	_MIPITX_DSI_PLL_CON2,8,3        ; @MIPITX_DSI_PLL_CON2
	.comm	_MIPITX_DSI_PLL_CON1,4,2        ; @MIPITX_DSI_PLL_CON1
	.comm	_RG_DSI_MPPLL_SDM_FRA_EN,4,2    ; @RG_DSI_MPPLL_SDM_FRA_EN
	.comm	_RG_DSI_MPPLL_SDM_SSC_EN,4,2    ; @RG_DSI_MPPLL_SDM_SSC_EN
	.comm	_MIPITX_DSI_PLL_TOP,4,2         ; @MIPITX_DSI_PLL_TOP
	.comm	_RG_DSI_MPPLL_PRESERVE,4,2      ; @RG_DSI_MPPLL_PRESERVE
	.no_dead_strip	_mtk_mipi_tx_pll_prepare
.subsections_via_symbols
