	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function smu_alloc_memory_pool
_smu_alloc_memory_pool:                 ## @smu_alloc_memory_pool
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	subq	$16, %rsp
	movl	(%rdi), %esi
	movq	_SMU_MEMORY_POOL_SIZE_ZERO@GOTPCREL(%rip), %rax
	cmpl	(%rax), %esi
	je	LBB0_3
## %bb.1:
	movq	32(%rdi), %r10
	movl	%esi, 4(%rdi)
	movq	_PAGE_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%edx, 24(%rdi)
	movq	_AMDGPU_GEM_DOMAIN_GTT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, 20(%rdi)
	movl	%esi, %eax
	andl	$-4, %eax
	cmpl	$128, %eax
	jne	LBB0_3
## %bb.2:
	leaq	16(%rdi), %r8
	leaq	12(%rdi), %r9
	addq	$8, %rdi
	movq	%rdi, (%rsp)
	movq	%r10, %rdi
	callq	_amdgpu_bo_create_kernel
	jmp	LBB0_4
LBB0_3:
	xorl	%eax, %eax
LBB0_4:
	addq	$16, %rsp
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_SMU_MEMORY_POOL_SIZE_ZERO,4,2  ## @SMU_MEMORY_POOL_SIZE_ZERO
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
	.comm	_AMDGPU_GEM_DOMAIN_GTT,4,2      ## @AMDGPU_GEM_DOMAIN_GTT
	.no_dead_strip	_smu_alloc_memory_pool
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function smu_alloc_memory_pool
_smu_alloc_memory_pool:                 ; @smu_alloc_memory_pool
	.cfi_startproc
; %bb.0:
	ldr	w1, [x0]
Lloh0:
	adrp	x8, _SMU_MEMORY_POOL_SIZE_ZERO@GOTPAGE
Lloh1:
	ldr	x8, [x8, _SMU_MEMORY_POOL_SIZE_ZERO@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cmp	w1, w8
	b.eq	LBB0_3
; %bb.1:
	ldr	x8, [x0, #32]
	str	w1, [x0, #4]
Lloh3:
	adrp	x9, _PAGE_SIZE@GOTPAGE
Lloh4:
	ldr	x9, [x9, _PAGE_SIZE@GOTPAGEOFF]
Lloh5:
	adrp	x10, _AMDGPU_GEM_DOMAIN_GTT@GOTPAGE
Lloh6:
	ldr	x10, [x10, _AMDGPU_GEM_DOMAIN_GTT@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x9]
Lloh8:
	ldr	w3, [x10]
	stp	w3, w2, [x0, #20]
	and	w9, w1, #0xfffffffc
	cmp	w9, #128
	b.ne	LBB0_3
; %bb.2:
	add	x4, x0, #16
	add	x5, x0, #12
	add	x6, x0, #8
	mov	x0, x8
	b	_amdgpu_bo_create_kernel
LBB0_3:
	mov	w0, #0
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh7
	.cfi_endproc
                                        ; -- End function
	.comm	_SMU_MEMORY_POOL_SIZE_ZERO,4,2  ; @SMU_MEMORY_POOL_SIZE_ZERO
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
	.comm	_AMDGPU_GEM_DOMAIN_GTT,4,2      ; @AMDGPU_GEM_DOMAIN_GTT
	.no_dead_strip	_smu_alloc_memory_pool
.subsections_via_symbols
