	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function hdmi_8996_pll_set_clk_rate
_hdmi_8996_pll_set_clk_rate:            ## @hdmi_8996_pll_set_clk_rate
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$152, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r15
	movq	%rsi, %rbx
	callq	_hw_clk_to_pll
	movq	%rax, %r12
	movq	%rax, %rdi
	callq	_pll_get_phy
	movq	%rax, %r14
	leaq	-184(%rbp), %r13
	movq	%r13, %rdi
	xorl	%esi, %esi
	movl	$136, %edx
	callq	_memset
	movq	%rbx, %rdi
	movq	%r15, %rsi
	movq	%r13, %rdx
	callq	_pll_calculate
	testl	%eax, %eax
	je	LBB0_2
## %bb.1:
	movl	%eax, %ebx
	leaq	L_.str(%rip), %rdi
	callq	_DRM_ERROR
	jmp	LBB0_9
LBB0_2:
	leaq	L_.str.1(%rip), %rdi
	callq	_DBG
	movq	_REG_HDMI_8996_PHY_PD_CTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	_hdmi_phy_write
	movl	$500, %edi                      ## imm = 0x1F4
	callq	_udelay
	movq	_REG_HDMI_PHY_QSERDES_COM_BG_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$4, %edx
	callq	_hdmi_pll_write
	movl	(%rbx), %esi
	movq	%r14, %rdi
	movl	$1, %edx
	callq	_hdmi_phy_write
	movq	_REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$32, %edx
	callq	_hdmi_pll_write
	movq	_REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$15, %edx
	callq	_hdmi_phy_write
	movq	_REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, -48(%rbp)                 ## 8-byte Spill
	movq	%r14, %rdi
	movl	$15, %edx
	callq	_hdmi_phy_write
	movq	_HDMI_NUM_TX_CHANNEL@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	jle	LBB0_5
## %bb.3:
	xorl	%ebx, %ebx
	movq	_REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE@GOTPCREL(%rip), %r14
	movq	_REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND@GOTPCREL(%rip), %r15
	movq	_REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %edx
	movq	%r12, %rdi
	movl	%ebx, %esi
	movl	$3, %ecx
	callq	_hdmi_tx_chan_write
	movl	(%r15), %edx
	movq	-184(%rbp), %rax
	movl	(%rax,%rbx,4), %ecx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_hdmi_tx_chan_write
	movl	(%r13), %edx
	movq	%r12, %rdi
	movl	%ebx, %esi
	movl	$3, %ecx
	callq	_hdmi_tx_chan_write
	incq	%rbx
	movq	_HDMI_NUM_TX_CHANNEL@GOTPCREL(%rip), %rax
	movslq	(%rax), %rax
	cmpq	%rax, %rbx
	jl	LBB0_4
LBB0_5:
	movq	_REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	-176(%rbp), %rax
	movl	(%rax), %ecx
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	_hdmi_tx_chan_write
	movl	(%rbx), %edx
	movq	-176(%rbp), %rax
	movl	8(%rax), %ecx
	movq	%r12, %rdi
	movl	$2, %esi
	callq	_hdmi_tx_chan_write
	movq	_REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$30, %edx
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$7, %edx
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$55, %edx
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$2, %edx
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$14, %edx
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-168(%rbp), %edx
	movq	%r12, %rdi
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_BG_TRIM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$15, %edx
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_PLL_IVCO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$15, %edx
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-164(%rbp), %edx
	movq	%r12, %rdi
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_BG_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$6, %edx
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_CLK_SELECT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$48, %edx
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-160(%rbp), %edx
	movq	%r12, %rdi
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-156(%rbp), %edx
	movq	%r12, %rdi
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-152(%rbp), %edx
	movq	%r12, %rdi
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-148(%rbp), %edx
	movq	%r12, %rdi
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-144(%rbp), %edx
	movq	%r12, %rdi
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-140(%rbp), %edx
	movq	%r12, %rdi
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-136(%rbp), %edx
	movq	%r12, %rdi
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-132(%rbp), %edx
	movq	%r12, %rdi
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-128(%rbp), %edx
	movq	%r12, %rdi
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-124(%rbp), %edx
	movq	%r12, %rdi
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-120(%rbp), %edx
	movq	%r12, %rdi
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-116(%rbp), %edx
	movq	%r12, %rdi
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-112(%rbp), %edx
	movq	%r12, %rdi
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-108(%rbp), %edx
	movq	%r12, %rdi
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-104(%rbp), %edx
	movq	%r12, %rdi
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-100(%rbp), %edx
	movq	%r12, %rdi
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$2, %edx
	callq	_hdmi_pll_write
	movq	_REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$21, %edx
	callq	_hdmi_pll_write
	movq	_HDMI_NUM_TX_CHANNEL@GOTPCREL(%rip), %r14
	cmpl	$0, (%r14)
	jle	LBB0_8
## %bb.6:
	xorl	%ebx, %ebx
	movq	_REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN@GOTPCREL(%rip), %r15
	movq	_REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_7:                                 ## =>This Inner Loop Header: Depth=1
	movq	_REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	-96(%rbp), %rax
	movl	(%rax,%rbx,4), %ecx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_hdmi_tx_chan_write
	movq	_REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	-88(%rbp), %rax
	movl	(%rax,%rbx,4), %ecx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_hdmi_tx_chan_write
	movq	_REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	-80(%rbp), %rax
	movl	(%rax,%rbx,4), %ecx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_hdmi_tx_chan_write
	movq	_REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	-72(%rbp), %rax
	movl	(%rax,%rbx,4), %ecx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_hdmi_tx_chan_write
	movq	_REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%ebx, %esi
	xorl	%ecx, %ecx
	callq	_hdmi_tx_chan_write
	movq	_REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%ebx, %esi
	xorl	%ecx, %ecx
	callq	_hdmi_tx_chan_write
	movq	_REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%ebx, %esi
	movl	$3, %ecx
	callq	_hdmi_tx_chan_write
	movl	(%r15), %edx
	movq	%r12, %rdi
	movl	%ebx, %esi
	movl	$64, %ecx
	callq	_hdmi_tx_chan_write
	movl	(%r13), %edx
	movq	-64(%rbp), %rax
	movl	(%rax,%rbx,4), %ecx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_hdmi_tx_chan_write
	incq	%rbx
	movslq	(%r14), %rax
	cmpq	%rax, %rbx
	jl	LBB0_7
LBB0_8:
	movq	_REG_HDMI_8996_PHY_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-56(%rbp), %edx
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	callq	_hdmi_phy_write
	movq	_REG_HDMI_8996_PHY_PD_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$31, %edx
	callq	_hdmi_phy_write
	xorl	%eax, %eax
	callq	_wmb
	xorl	%ebx, %ebx
LBB0_9:
	movl	%ebx, %eax
	addq	$152, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"PLL calculation failed\n"

L_.str.1:                               ## @.str.1
	.asciz	"Disabling PHY"

	.comm	_REG_HDMI_8996_PHY_PD_CTL,4,2   ## @REG_HDMI_8996_PHY_PD_CTL
	.comm	_REG_HDMI_PHY_QSERDES_COM_BG_CTRL,4,2 ## @REG_HDMI_PHY_QSERDES_COM_BG_CTRL
	.comm	_REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL,4,2 ## @REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL
	.comm	_REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL,4,2 ## @REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL
	.comm	_REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL,4,2 ## @REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL
	.comm	_HDMI_NUM_TX_CHANNEL,4,2        ## @HDMI_NUM_TX_CHANNEL
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE,4,2 ## @REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND,4,2 ## @REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN,4,2 ## @REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE,4,2 ## @REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE
	.comm	_REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE,4,2 ## @REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE
	.comm	_REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN,4,2 ## @REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN
	.comm	_REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL,4,2 ## @REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL
	.comm	_REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL,4,2 ## @REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL
	.comm	_REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1,4,2 ## @REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1
	.comm	_REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL,4,2 ## @REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL
	.comm	_REG_HDMI_PHY_QSERDES_COM_BG_TRIM,4,2 ## @REG_HDMI_PHY_QSERDES_COM_BG_TRIM
	.comm	_REG_HDMI_PHY_QSERDES_COM_PLL_IVCO,4,2 ## @REG_HDMI_PHY_QSERDES_COM_PLL_IVCO
	.comm	_REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL,4,2 ## @REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL
	.comm	_REG_HDMI_PHY_QSERDES_COM_CLK_SELECT,4,2 ## @REG_HDMI_PHY_QSERDES_COM_CLK_SELECT
	.comm	_REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL,4,2 ## @REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL
	.comm	_REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN,4,2 ## @REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN
	.comm	_REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0,4,2 ## @REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0,4,2 ## @REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0,4,2 ## @REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0,4,2 ## @REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0,4,2 ## @REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0,4,2 ## @REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0,4,2 ## @REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0,4,2 ## @REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0,4,2 ## @REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0,4,2 ## @REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0,4,2 ## @REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0,4,2 ## @REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP,4,2 ## @REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP
	.comm	_REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN,4,2 ## @REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN
	.comm	_REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV,4,2 ## @REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV
	.comm	_REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG,4,2 ## @REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG
	.comm	_REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM,4,2 ## @REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL,4,2 ## @REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL,4,2 ## @REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1,4,2 ## @REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2,4,2 ## @REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET,4,2 ## @REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET,4,2 ## @REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN,4,2 ## @REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN,4,2 ## @REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES,4,2 ## @REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES
	.comm	_REG_HDMI_8996_PHY_MODE,4,2     ## @REG_HDMI_8996_PHY_MODE
	.no_dead_strip	_hdmi_8996_pll_set_clk_rate
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function hdmi_8996_pll_set_clk_rate
_hdmi_8996_pll_set_clk_rate:            ; @hdmi_8996_pll_set_clk_rate
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #240
	.cfi_def_cfa_offset 240
	stp	x28, x27, [sp, #144]            ; 16-byte Folded Spill
	stp	x26, x25, [sp, #160]            ; 16-byte Folded Spill
	stp	x24, x23, [sp, #176]            ; 16-byte Folded Spill
	stp	x22, x21, [sp, #192]            ; 16-byte Folded Spill
	stp	x20, x19, [sp, #208]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #224]            ; 16-byte Folded Spill
	add	x29, sp, #224
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x2
	mov	x22, x1
	bl	_hw_clk_to_pll
	mov	x20, x0
	bl	_pll_get_phy
	mov	x19, x0
	add	x0, sp, #8
	mov	w1, #0
	mov	w2, #136
	bl	_memset
	add	x2, sp, #8
	mov	x0, x22
	mov	x1, x21
	bl	_pll_calculate
	cbz	w0, LBB0_2
; %bb.1:
	mov	x21, x0
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_ERROR
	b	LBB0_9
LBB0_2:
Lloh2:
	adrp	x0, l_.str.1@PAGE
Lloh3:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DBG
Lloh4:
	adrp	x21, _REG_HDMI_8996_PHY_PD_CTL@GOTPAGE
Lloh5:
	ldr	x21, [x21, _REG_HDMI_8996_PHY_PD_CTL@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	mov	w2, #0
	bl	_hdmi_phy_write
	mov	w0, #500
	bl	_udelay
Lloh6:
	adrp	x24, _REG_HDMI_PHY_QSERDES_COM_BG_CTRL@GOTPAGE
Lloh7:
	ldr	x24, [x24, _REG_HDMI_PHY_QSERDES_COM_BG_CTRL@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	x0, x20
	mov	w2, #4
	bl	_hdmi_pll_write
	ldr	w1, [x21]
	mov	x0, x19
	mov	w2, #1
	bl	_hdmi_phy_write
Lloh8:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL@GOTPAGE
Lloh9:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL@GOTPAGEOFF]
Lloh10:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #32
	bl	_hdmi_pll_write
Lloh11:
	adrp	x8, _REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL@GOTPAGE
Lloh12:
	ldr	x8, [x8, _REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #15
	bl	_hdmi_phy_write
Lloh14:
	adrp	x8, _REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL@GOTPAGE
Lloh15:
	ldr	x8, [x8, _REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
	str	x19, [sp]                       ; 8-byte Folded Spill
	mov	x0, x19
	mov	w2, #15
	bl	_hdmi_phy_write
Lloh17:
	adrp	x26, _HDMI_NUM_TX_CHANNEL@GOTPAGE
Lloh18:
	ldr	x26, [x26, _HDMI_NUM_TX_CHANNEL@GOTPAGEOFF]
	ldr	w8, [x26]
	cmp	w8, #1
	b.lt	LBB0_5
; %bb.3:
	mov	x21, #0
Lloh19:
	adrp	x19, _REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE@GOTPAGE
Lloh20:
	ldr	x19, [x19, _REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE@GOTPAGEOFF]
Lloh21:
	adrp	x22, _REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND@GOTPAGE
Lloh22:
	ldr	x22, [x22, _REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND@GOTPAGEOFF]
Lloh23:
	adrp	x23, _REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN@GOTPAGE
Lloh24:
	ldr	x23, [x23, _REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN@GOTPAGEOFF]
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w2, [x19]
	mov	x0, x20
	mov	x1, x21
	mov	w3, #3
	bl	_hdmi_tx_chan_write
	ldr	w2, [x22]
	ldr	x8, [sp, #8]
	ldr	w3, [x8, x21, lsl #2]
	mov	x0, x20
	mov	x1, x21
	bl	_hdmi_tx_chan_write
	ldr	w2, [x23]
	mov	x0, x20
	mov	x1, x21
	mov	w3, #3
	bl	_hdmi_tx_chan_write
	add	x21, x21, #1
	ldrsw	x8, [x26]
	cmp	x21, x8
	b.lt	LBB0_4
LBB0_5:
Lloh25:
	adrp	x19, _REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE@GOTPAGE
Lloh26:
	ldr	x19, [x19, _REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE@GOTPAGEOFF]
	ldr	w2, [x19]
	ldr	x8, [sp, #16]
	ldr	w3, [x8]
	mov	x0, x20
	mov	w1, #0
	bl	_hdmi_tx_chan_write
	ldr	w2, [x19]
	ldr	x8, [sp, #16]
	ldr	w3, [x8, #8]
	mov	x0, x20
	mov	w1, #2
	bl	_hdmi_tx_chan_write
Lloh27:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE@GOTPAGE
Lloh28:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #30
	bl	_hdmi_pll_write
Lloh30:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN@GOTPAGE
Lloh31:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #7
	bl	_hdmi_pll_write
Lloh33:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL@GOTPAGE
Lloh34:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL@GOTPAGEOFF]
Lloh35:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #55
	bl	_hdmi_pll_write
Lloh36:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL@GOTPAGE
Lloh37:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #2
	bl	_hdmi_pll_write
Lloh39:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1@GOTPAGE
Lloh40:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #14
	bl	_hdmi_pll_write
Lloh42:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL@GOTPAGE
Lloh43:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x8]
	ldr	w2, [sp, #24]
	mov	x0, x20
	bl	_hdmi_pll_write
Lloh45:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_BG_TRIM@GOTPAGE
Lloh46:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_BG_TRIM@GOTPAGEOFF]
Lloh47:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #15
	bl	_hdmi_pll_write
Lloh48:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_PLL_IVCO@GOTPAGE
Lloh49:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_PLL_IVCO@GOTPAGEOFF]
Lloh50:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #15
	bl	_hdmi_pll_write
Lloh51:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL@GOTPAGE
Lloh52:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL@GOTPAGEOFF]
Lloh53:
	ldr	w1, [x8]
	ldr	w2, [sp, #28]
	mov	x0, x20
	bl	_hdmi_pll_write
	ldr	w1, [x24]
	mov	x0, x20
	mov	w2, #6
	bl	_hdmi_pll_write
Lloh54:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_CLK_SELECT@GOTPAGE
Lloh55:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_CLK_SELECT@GOTPAGEOFF]
Lloh56:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #48
	bl	_hdmi_pll_write
Lloh57:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL@GOTPAGE
Lloh58:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL@GOTPAGEOFF]
Lloh59:
	ldr	w1, [x8]
	ldr	w2, [sp, #32]
	mov	x0, x20
	bl	_hdmi_pll_write
Lloh60:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN@GOTPAGE
Lloh61:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN@GOTPAGEOFF]
Lloh62:
	ldr	w1, [x8]
	ldr	w2, [sp, #36]
	mov	x0, x20
	bl	_hdmi_pll_write
Lloh63:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0@GOTPAGE
Lloh64:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0@GOTPAGEOFF]
Lloh65:
	ldr	w1, [x8]
	ldr	w2, [sp, #40]
	mov	x0, x20
	bl	_hdmi_pll_write
Lloh66:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0@GOTPAGE
Lloh67:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0@GOTPAGEOFF]
Lloh68:
	ldr	w1, [x8]
	ldr	w2, [sp, #44]
	mov	x0, x20
	bl	_hdmi_pll_write
Lloh69:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0@GOTPAGE
Lloh70:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0@GOTPAGEOFF]
Lloh71:
	ldr	w1, [x8]
	ldr	w2, [sp, #48]
	mov	x0, x20
	bl	_hdmi_pll_write
Lloh72:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0@GOTPAGE
Lloh73:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0@GOTPAGEOFF]
Lloh74:
	ldr	w1, [x8]
	ldr	w2, [sp, #52]
	mov	x0, x20
	bl	_hdmi_pll_write
Lloh75:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0@GOTPAGE
Lloh76:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0@GOTPAGEOFF]
Lloh77:
	ldr	w1, [x8]
	ldr	w2, [sp, #56]
	mov	x0, x20
	bl	_hdmi_pll_write
Lloh78:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0@GOTPAGE
Lloh79:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0@GOTPAGEOFF]
Lloh80:
	ldr	w1, [x8]
	ldr	w2, [sp, #60]
	mov	x0, x20
	bl	_hdmi_pll_write
Lloh81:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0@GOTPAGE
Lloh82:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0@GOTPAGEOFF]
Lloh83:
	ldr	w1, [x8]
	ldr	w2, [sp, #64]
	mov	x0, x20
	bl	_hdmi_pll_write
Lloh84:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0@GOTPAGE
Lloh85:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0@GOTPAGEOFF]
Lloh86:
	ldr	w1, [x8]
	ldr	w2, [sp, #68]
	mov	x0, x20
	bl	_hdmi_pll_write
Lloh87:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0@GOTPAGE
Lloh88:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0@GOTPAGEOFF]
Lloh89:
	ldr	w1, [x8]
	ldr	w2, [sp, #72]
	mov	x0, x20
	bl	_hdmi_pll_write
Lloh90:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0@GOTPAGE
Lloh91:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0@GOTPAGEOFF]
Lloh92:
	ldr	w1, [x8]
	ldr	w2, [sp, #76]
	mov	x0, x20
	bl	_hdmi_pll_write
Lloh93:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0@GOTPAGE
Lloh94:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0@GOTPAGEOFF]
Lloh95:
	ldr	w1, [x8]
	ldr	w2, [sp, #80]
	mov	x0, x20
	bl	_hdmi_pll_write
Lloh96:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0@GOTPAGE
Lloh97:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0@GOTPAGEOFF]
Lloh98:
	ldr	w1, [x8]
	ldr	w2, [sp, #84]
	mov	x0, x20
	bl	_hdmi_pll_write
Lloh99:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP@GOTPAGE
Lloh100:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP@GOTPAGEOFF]
Lloh101:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #0
	bl	_hdmi_pll_write
Lloh102:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN@GOTPAGE
Lloh103:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN@GOTPAGEOFF]
Lloh104:
	ldr	w1, [x8]
	ldr	w2, [sp, #88]
	mov	x0, x20
	bl	_hdmi_pll_write
Lloh105:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV@GOTPAGE
Lloh106:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV@GOTPAGEOFF]
Lloh107:
	ldr	w1, [x8]
	ldr	w2, [sp, #92]
	mov	x0, x20
	bl	_hdmi_pll_write
Lloh108:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG@GOTPAGE
Lloh109:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG@GOTPAGEOFF]
Lloh110:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #2
	bl	_hdmi_pll_write
Lloh111:
	adrp	x8, _REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM@GOTPAGE
Lloh112:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM@GOTPAGEOFF]
Lloh113:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #21
	bl	_hdmi_pll_write
	ldr	w8, [x26]
	cmp	w8, #1
	b.lt	LBB0_8
; %bb.6:
	mov	x21, #0
Lloh114:
	adrp	x27, _REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2@GOTPAGE
Lloh115:
	ldr	x27, [x27, _REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2@GOTPAGEOFF]
Lloh116:
	adrp	x28, _REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET@GOTPAGE
Lloh117:
	ldr	x28, [x28, _REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET@GOTPAGEOFF]
Lloh118:
	adrp	x22, _REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET@GOTPAGE
Lloh119:
	ldr	x22, [x22, _REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET@GOTPAGEOFF]
Lloh120:
	adrp	x19, _REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN@GOTPAGE
Lloh121:
	ldr	x19, [x19, _REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN@GOTPAGEOFF]
Lloh122:
	adrp	x23, _REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN@GOTPAGE
Lloh123:
	ldr	x23, [x23, _REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN@GOTPAGEOFF]
Lloh124:
	adrp	x24, _REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES@GOTPAGE
Lloh125:
	ldr	x24, [x24, _REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES@GOTPAGEOFF]
LBB0_7:                                 ; =>This Inner Loop Header: Depth=1
Lloh126:
	adrp	x8, _REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL@GOTPAGE
Lloh127:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL@GOTPAGEOFF]
Lloh128:
	ldr	w2, [x8]
	ldr	x8, [sp, #96]
	lsl	x25, x21, #2
	ldr	w3, [x8, x25]
	mov	x0, x20
	mov	x1, x21
	bl	_hdmi_tx_chan_write
Lloh129:
	adrp	x8, _REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL@GOTPAGE
Lloh130:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL@GOTPAGEOFF]
Lloh131:
	ldr	w2, [x8]
	ldr	x8, [sp, #104]
	ldr	w3, [x8, x25]
	mov	x0, x20
	mov	x1, x21
	bl	_hdmi_tx_chan_write
Lloh132:
	adrp	x8, _REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1@GOTPAGE
Lloh133:
	ldr	x8, [x8, _REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1@GOTPAGEOFF]
Lloh134:
	ldr	w2, [x8]
	ldr	x8, [sp, #112]
	ldr	w3, [x8, x25]
	mov	x0, x20
	mov	x1, x21
	bl	_hdmi_tx_chan_write
	ldr	w2, [x27]
	ldr	x8, [sp, #120]
	ldr	w3, [x8, x25]
	mov	x0, x20
	mov	x1, x21
	bl	_hdmi_tx_chan_write
	ldr	w2, [x28]
	mov	x0, x20
	mov	x1, x21
	mov	w3, #0
	bl	_hdmi_tx_chan_write
	ldr	w2, [x22]
	mov	x0, x20
	mov	x1, x21
	mov	w3, #0
	bl	_hdmi_tx_chan_write
	ldr	w2, [x19]
	mov	x0, x20
	mov	x1, x21
	mov	w3, #3
	bl	_hdmi_tx_chan_write
	ldr	w2, [x23]
	mov	x0, x20
	mov	x1, x21
	mov	w3, #64
	bl	_hdmi_tx_chan_write
	ldr	w2, [x24]
	ldr	x8, [sp, #128]
	ldr	w3, [x8, x25]
	mov	x0, x20
	mov	x1, x21
	bl	_hdmi_tx_chan_write
	add	x21, x21, #1
	ldrsw	x8, [x26]
	cmp	x21, x8
	b.lt	LBB0_7
LBB0_8:
Lloh135:
	adrp	x8, _REG_HDMI_8996_PHY_MODE@GOTPAGE
Lloh136:
	ldr	x8, [x8, _REG_HDMI_8996_PHY_MODE@GOTPAGEOFF]
Lloh137:
	ldr	w1, [x8]
	ldr	w2, [sp, #136]
	ldr	x19, [sp]                       ; 8-byte Folded Reload
	mov	x0, x19
	bl	_hdmi_phy_write
Lloh138:
	adrp	x8, _REG_HDMI_8996_PHY_PD_CTL@GOTPAGE
Lloh139:
	ldr	x8, [x8, _REG_HDMI_8996_PHY_PD_CTL@GOTPAGEOFF]
Lloh140:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #31
	bl	_hdmi_phy_write
	bl	_wmb
	mov	w21, #0
LBB0_9:
	mov	x0, x21
	ldp	x29, x30, [sp, #224]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #208]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #192]            ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #176]            ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #160]            ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #144]            ; 16-byte Folded Reload
	add	sp, sp, #240
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh124, Lloh125
	.loh AdrpLdrGot	Lloh122, Lloh123
	.loh AdrpLdrGot	Lloh120, Lloh121
	.loh AdrpLdrGot	Lloh118, Lloh119
	.loh AdrpLdrGot	Lloh116, Lloh117
	.loh AdrpLdrGot	Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh132, Lloh133, Lloh134
	.loh AdrpLdrGotLdr	Lloh129, Lloh130, Lloh131
	.loh AdrpLdrGotLdr	Lloh126, Lloh127, Lloh128
	.loh AdrpLdrGotLdr	Lloh138, Lloh139, Lloh140
	.loh AdrpLdrGotLdr	Lloh135, Lloh136, Lloh137
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"PLL calculation failed\n"

l_.str.1:                               ; @.str.1
	.asciz	"Disabling PHY"

	.comm	_REG_HDMI_8996_PHY_PD_CTL,4,2   ; @REG_HDMI_8996_PHY_PD_CTL
	.comm	_REG_HDMI_PHY_QSERDES_COM_BG_CTRL,4,2 ; @REG_HDMI_PHY_QSERDES_COM_BG_CTRL
	.comm	_REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL,4,2 ; @REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL
	.comm	_REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL,4,2 ; @REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL
	.comm	_REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL,4,2 ; @REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL
	.comm	_HDMI_NUM_TX_CHANNEL,4,2        ; @HDMI_NUM_TX_CHANNEL
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE,4,2 ; @REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND,4,2 ; @REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN,4,2 ; @REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE,4,2 ; @REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE
	.comm	_REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE,4,2 ; @REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE
	.comm	_REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN,4,2 ; @REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN
	.comm	_REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL,4,2 ; @REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL
	.comm	_REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL,4,2 ; @REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL
	.comm	_REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1,4,2 ; @REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1
	.comm	_REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL,4,2 ; @REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL
	.comm	_REG_HDMI_PHY_QSERDES_COM_BG_TRIM,4,2 ; @REG_HDMI_PHY_QSERDES_COM_BG_TRIM
	.comm	_REG_HDMI_PHY_QSERDES_COM_PLL_IVCO,4,2 ; @REG_HDMI_PHY_QSERDES_COM_PLL_IVCO
	.comm	_REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL,4,2 ; @REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL
	.comm	_REG_HDMI_PHY_QSERDES_COM_CLK_SELECT,4,2 ; @REG_HDMI_PHY_QSERDES_COM_CLK_SELECT
	.comm	_REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL,4,2 ; @REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL
	.comm	_REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN,4,2 ; @REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN
	.comm	_REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0,4,2 ; @REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0,4,2 ; @REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0,4,2 ; @REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0,4,2 ; @REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0,4,2 ; @REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0,4,2 ; @REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0,4,2 ; @REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0,4,2 ; @REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0,4,2 ; @REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0,4,2 ; @REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0,4,2 ; @REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0,4,2 ; @REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0
	.comm	_REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP,4,2 ; @REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP
	.comm	_REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN,4,2 ; @REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN
	.comm	_REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV,4,2 ; @REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV
	.comm	_REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG,4,2 ; @REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG
	.comm	_REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM,4,2 ; @REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL,4,2 ; @REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL,4,2 ; @REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1,4,2 ; @REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2,4,2 ; @REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET,4,2 ; @REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET,4,2 ; @REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN,4,2 ; @REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN,4,2 ; @REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN
	.comm	_REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES,4,2 ; @REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES
	.comm	_REG_HDMI_8996_PHY_MODE,4,2     ; @REG_HDMI_8996_PHY_MODE
	.no_dead_strip	_hdmi_8996_pll_set_clk_rate
.subsections_via_symbols
