	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function cayman_pcie_gart_enable
_cayman_pcie_gart_enable:               ## @cayman_pcie_gart_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	cmpq	$0, 8(%rdi)
	je	LBB0_1
## %bb.2:
	movq	%r12, %rdi
	callq	_radeon_gart_table_vram_pin
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	LBB0_4
## %bb.3:
	movq	_MC_VM_MX_L1_TLB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_ENABLE_L1_TLB@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_ENABLE_L1_FRAGMENT_PROCESSING@GOTPCREL(%rip), %rax
	movq	_SYSTEM_ACCESS_MODE_NOT_IN_SYS@GOTPCREL(%rip), %rcx
	movq	_ENABLE_ADVANCED_DRIVER_MODEL@GOTPCREL(%rip), %rdx
	orl	(%rax), %esi
	orl	(%rcx), %esi
	orl	(%rdx), %esi
	movq	_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	orl	$1280, %esi                     ## imm = 0x500
	callq	_WREG32
	movq	_ENABLE_L2_CACHE@GOTPCREL(%rip), %rax
	movq	_ENABLE_L2_FRAGMENT_PROCESSING@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	_VM_L2_CNTL@GOTPCREL(%rip), %rax
	movq	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movl	(%rax), %r14d
	movq	_ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	$7, %edi
	callq	_EFFECTIVE_L2_QUEUE_SIZE
	movl	%eax, %r15d
	movl	$1, %edi
	callq	_CONTEXT1_IDENTITY_ACCESS_MODE
	orl	%eax, %r15d
	orl	%ebx, %r15d
	movl	%r14d, %edi
	movl	%r15d, %esi
	callq	_WREG32
	movq	_VM_L2_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_INVALIDATE_ALL_L1_TLBS@GOTPCREL(%rip), %rax
	movq	_INVALIDATE_L2_CACHE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	callq	_WREG32
	movq	_VM_L2_CNTL3@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_L2_CACHE_BIGK_ASSOCIATIVITY@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	$6, %edi
	callq	_BANK_SELECT
	movl	%eax, %ebx
	movl	$6, %edi
	callq	_L2_CACHE_BIGK_FRAGMENT_SIZE
	orl	%eax, %ebx
	orl	%r15d, %ebx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_VM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	16(%r12), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_VM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movl	20(%r12), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r12), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	28(%r12), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_VM_CONTEXT0_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%r14d, %r14d
	xorl	%esi, %esi
	callq	_WREG32
	movq	_VM_CONTEXT0_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_ENABLE_CONTEXT@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	xorl	%edi, %edi
	callq	_PAGE_TABLE_DEPTH
	orl	%eax, %ebx
	movq	_RANGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	%r15d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	$5588, %edi                     ## imm = 0x15D4
	xorl	%esi, %esi
	callq	_WREG32
	movl	$5592, %edi                     ## imm = 0x15D8
	xorl	%esi, %esi
	callq	_WREG32
	movl	$5596, %edi                     ## imm = 0x15DC
	xorl	%esi, %esi
	callq	_WREG32
	movq	_VM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	addl	$4, %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$4, %edi
	movl	32(%r12), %esi
	decl	%esi
	callq	_WREG32
	movq	_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	addl	$4, %edi
	movq	40(%r12), %rax
	movl	4(%rax), %esi
	callq	_WREG32
	movl	(%rbx), %edi
	addl	$8, %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$8, %edi
	movl	32(%r12), %esi
	decl	%esi
	callq	_WREG32
	movl	(%r15), %edi
	addl	$8, %edi
	movq	40(%r12), %rax
	movl	8(%rax), %esi
	callq	_WREG32
	movl	(%rbx), %edi
	addl	$12, %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$12, %edi
	movl	32(%r12), %esi
	decl	%esi
	callq	_WREG32
	movl	(%r15), %edi
	addl	$12, %edi
	movq	40(%r12), %rax
	movl	12(%rax), %esi
	callq	_WREG32
	movl	(%rbx), %edi
	addl	$16, %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$16, %edi
	movl	32(%r12), %esi
	decl	%esi
	callq	_WREG32
	movl	(%r15), %edi
	addl	$16, %edi
	movq	40(%r12), %rax
	movl	16(%rax), %esi
	callq	_WREG32
	movl	(%rbx), %edi
	addl	$20, %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$20, %edi
	movl	32(%r12), %esi
	decl	%esi
	callq	_WREG32
	movl	(%r15), %edi
	addl	$20, %edi
	movq	40(%r12), %rax
	movl	20(%rax), %esi
	callq	_WREG32
	movl	(%rbx), %edi
	addl	$24, %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$24, %edi
	movl	32(%r12), %esi
	decl	%esi
	callq	_WREG32
	movl	(%r15), %edi
	addl	$24, %edi
	movq	40(%r12), %rax
	movl	24(%rax), %esi
	callq	_WREG32
	movl	(%rbx), %edi
	addl	$28, %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	(%r13), %edi
	addl	$28, %edi
	movl	32(%r12), %esi
	decl	%esi
	callq	_WREG32
	movl	(%r15), %edi
	addl	$28, %edi
	movq	40(%r12), %rax
	movl	28(%rax), %esi
	callq	_WREG32
	movq	_VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	28(%r12), %esi
	sarl	$12, %esi
	callq	_WREG32
	movq	_VM_CONTEXT1_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$4, %esi
	callq	_WREG32
	movq	_VM_CONTEXT1_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_ENABLE_CONTEXT@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$1, %edi
	callq	_PAGE_TABLE_DEPTH
	orl	%eax, %ebx
	movq	_radeon_vm_block_size@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	$-9, %rdi
	callq	_PAGE_TABLE_BLOCK_SIZE
	orl	%eax, %ebx
	movq	_RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_RANGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_PDE0_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_VALID_PROTECTION_FAULT_ENABLE_INTERRUPT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_VALID_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_READ_PROTECTION_FAULT_ENABLE_INTERRUPT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_READ_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_WRITE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	%r15d, %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	%r12, %rdi
	callq	_cayman_pcie_gart_tlb_flush
	movl	24(%r12), %esi
	sarl	$20, %esi
	movslq	(%r12), %rdx
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_INFO
	movl	$1, 4(%r12)
	jmp	LBB0_4
LBB0_1:
	movl	48(%r12), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r14d, %r14d
	subl	(%rax), %r14d
LBB0_4:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"No VRAM object for PCIE GART.\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_MC_VM_MX_L1_TLB_CNTL,4,2       ## @MC_VM_MX_L1_TLB_CNTL
	.comm	_ENABLE_L1_TLB,4,2              ## @ENABLE_L1_TLB
	.comm	_ENABLE_L1_FRAGMENT_PROCESSING,4,2 ## @ENABLE_L1_FRAGMENT_PROCESSING
	.comm	_SYSTEM_ACCESS_MODE_NOT_IN_SYS,4,2 ## @SYSTEM_ACCESS_MODE_NOT_IN_SYS
	.comm	_ENABLE_ADVANCED_DRIVER_MODEL,4,2 ## @ENABLE_ADVANCED_DRIVER_MODEL
	.comm	_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU,4,2 ## @SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
	.comm	_VM_L2_CNTL,4,2                 ## @VM_L2_CNTL
	.comm	_ENABLE_L2_CACHE,4,2            ## @ENABLE_L2_CACHE
	.comm	_ENABLE_L2_FRAGMENT_PROCESSING,4,2 ## @ENABLE_L2_FRAGMENT_PROCESSING
	.comm	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE,4,2 ## @ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE,4,2 ## @ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_VM_L2_CNTL2,4,2                ## @VM_L2_CNTL2
	.comm	_INVALIDATE_ALL_L1_TLBS,4,2     ## @INVALIDATE_ALL_L1_TLBS
	.comm	_INVALIDATE_L2_CACHE,4,2        ## @INVALIDATE_L2_CACHE
	.comm	_VM_L2_CNTL3,4,2                ## @VM_L2_CNTL3
	.comm	_L2_CACHE_BIGK_ASSOCIATIVITY,4,2 ## @L2_CACHE_BIGK_ASSOCIATIVITY
	.comm	_VM_CONTEXT0_PAGE_TABLE_START_ADDR,4,2 ## @VM_CONTEXT0_PAGE_TABLE_START_ADDR
	.comm	_VM_CONTEXT0_PAGE_TABLE_END_ADDR,4,2 ## @VM_CONTEXT0_PAGE_TABLE_END_ADDR
	.comm	_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR,4,2 ## @VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
	.comm	_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,4,2 ## @VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
	.comm	_VM_CONTEXT0_CNTL2,4,2          ## @VM_CONTEXT0_CNTL2
	.comm	_VM_CONTEXT0_CNTL,4,2           ## @VM_CONTEXT0_CNTL
	.comm	_ENABLE_CONTEXT,4,2             ## @ENABLE_CONTEXT
	.comm	_RANGE_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ## @RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,4,2 ## @VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR
	.comm	_VM_CONTEXT1_CNTL2,4,2          ## @VM_CONTEXT1_CNTL2
	.comm	_VM_CONTEXT1_CNTL,4,2           ## @VM_CONTEXT1_CNTL
	.comm	_radeon_vm_block_size,8,3       ## @radeon_vm_block_size
	.comm	_RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT,4,2 ## @RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT
	.comm	_DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT,4,2 ## @DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT
	.comm	_DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ## @DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT,4,2 ## @PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT
	.comm	_PDE0_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ## @PDE0_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_VALID_PROTECTION_FAULT_ENABLE_INTERRUPT,4,2 ## @VALID_PROTECTION_FAULT_ENABLE_INTERRUPT
	.comm	_VALID_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ## @VALID_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_READ_PROTECTION_FAULT_ENABLE_INTERRUPT,4,2 ## @READ_PROTECTION_FAULT_ENABLE_INTERRUPT
	.comm	_READ_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ## @READ_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT,4,2 ## @WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT
	.comm	_WRITE_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ## @WRITE_PROTECTION_FAULT_ENABLE_DEFAULT
L_.str.1:                               ## @.str.1
	.asciz	"PCIE GART of %uM enabled (table at 0x%016llX).\n"

	.no_dead_strip	_cayman_pcie_gart_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cayman_pcie_gart_enable
_cayman_pcie_gart_enable:               ; @cayman_pcie_gart_enable
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldr	x8, [x0, #8]
	cbz	x8, LBB0_3
; %bb.1:
	mov	x0, x19
	bl	_radeon_gart_table_vram_pin
	cbnz	w0, LBB0_4
; %bb.2:
Lloh0:
	adrp	x8, _MC_VM_MX_L1_TLB_CNTL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MC_VM_MX_L1_TLB_CNTL@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
Lloh3:
	adrp	x8, _ENABLE_L1_TLB@GOTPAGE
Lloh4:
	ldr	x8, [x8, _ENABLE_L1_TLB@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
Lloh6:
	adrp	x9, _ENABLE_L1_FRAGMENT_PROCESSING@GOTPAGE
Lloh7:
	ldr	x9, [x9, _ENABLE_L1_FRAGMENT_PROCESSING@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
Lloh9:
	adrp	x10, _SYSTEM_ACCESS_MODE_NOT_IN_SYS@GOTPAGE
Lloh10:
	ldr	x10, [x10, _SYSTEM_ACCESS_MODE_NOT_IN_SYS@GOTPAGEOFF]
Lloh11:
	ldr	w10, [x10]
Lloh12:
	adrp	x11, _ENABLE_ADVANCED_DRIVER_MODEL@GOTPAGE
Lloh13:
	ldr	x11, [x11, _ENABLE_ADVANCED_DRIVER_MODEL@GOTPAGEOFF]
Lloh14:
	ldr	w11, [x11]
Lloh15:
	adrp	x12, _SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU@GOTPAGE
Lloh16:
	ldr	x12, [x12, _SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU@GOTPAGEOFF]
Lloh17:
	ldr	w12, [x12]
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	mov	w9, #1280
	orr	w1, w8, w9
	bl	_WREG32
Lloh18:
	adrp	x8, _VM_L2_CNTL@GOTPAGE
Lloh19:
	ldr	x8, [x8, _VM_L2_CNTL@GOTPAGEOFF]
Lloh20:
	ldr	w20, [x8]
Lloh21:
	adrp	x8, _ENABLE_L2_CACHE@GOTPAGE
Lloh22:
	ldr	x8, [x8, _ENABLE_L2_CACHE@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
Lloh24:
	adrp	x9, _ENABLE_L2_FRAGMENT_PROCESSING@GOTPAGE
Lloh25:
	ldr	x9, [x9, _ENABLE_L2_FRAGMENT_PROCESSING@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh27:
	adrp	x9, _ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGE
Lloh28:
	ldr	x9, [x9, _ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh30:
	adrp	x9, _ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGE
Lloh31:
	ldr	x9, [x9, _ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	orr	w21, w8, w9
	mov	w0, #7
	bl	_EFFECTIVE_L2_QUEUE_SIZE
	orr	w22, w21, w0
	mov	w21, #1
	mov	w0, #1
	bl	_CONTEXT1_IDENTITY_ACCESS_MODE
	orr	w1, w22, w0
	mov	x0, x20
	bl	_WREG32
Lloh33:
	adrp	x8, _VM_L2_CNTL2@GOTPAGE
Lloh34:
	ldr	x8, [x8, _VM_L2_CNTL2@GOTPAGEOFF]
Lloh35:
	adrp	x9, _INVALIDATE_ALL_L1_TLBS@GOTPAGE
Lloh36:
	ldr	x9, [x9, _INVALIDATE_ALL_L1_TLBS@GOTPAGEOFF]
Lloh37:
	ldr	w0, [x8]
Lloh38:
	ldr	w8, [x9]
Lloh39:
	adrp	x9, _INVALIDATE_L2_CACHE@GOTPAGE
Lloh40:
	ldr	x9, [x9, _INVALIDATE_L2_CACHE@GOTPAGEOFF]
Lloh41:
	ldr	w9, [x9]
	orr	w1, w9, w8
	bl	_WREG32
Lloh42:
	adrp	x8, _VM_L2_CNTL3@GOTPAGE
Lloh43:
	ldr	x8, [x8, _VM_L2_CNTL3@GOTPAGEOFF]
Lloh44:
	ldr	w20, [x8]
Lloh45:
	adrp	x8, _L2_CACHE_BIGK_ASSOCIATIVITY@GOTPAGE
Lloh46:
	ldr	x8, [x8, _L2_CACHE_BIGK_ASSOCIATIVITY@GOTPAGEOFF]
Lloh47:
	ldr	w22, [x8]
	mov	w0, #6
	bl	_BANK_SELECT
	orr	w22, w0, w22
	mov	w0, #6
	bl	_L2_CACHE_BIGK_FRAGMENT_SIZE
	orr	w1, w22, w0
	mov	x0, x20
	bl	_WREG32
Lloh48:
	adrp	x23, _VM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPAGE
Lloh49:
	ldr	x23, [x23, _VM_CONTEXT0_PAGE_TABLE_START_ADDR@GOTPAGEOFF]
	ldr	w0, [x23]
	ldr	w8, [x19, #16]
	asr	w1, w8, #12
	bl	_WREG32
Lloh50:
	adrp	x24, _VM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPAGE
Lloh51:
	ldr	x24, [x24, _VM_CONTEXT0_PAGE_TABLE_END_ADDR@GOTPAGEOFF]
	ldr	w0, [x24]
	ldr	w8, [x19, #20]
	asr	w1, w8, #12
	bl	_WREG32
Lloh52:
	adrp	x25, _VM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPAGE
Lloh53:
	ldr	x25, [x25, _VM_CONTEXT0_PAGE_TABLE_BASE_ADDR@GOTPAGEOFF]
	ldr	w0, [x25]
	ldr	w8, [x19]
	asr	w1, w8, #12
	bl	_WREG32
Lloh54:
	adrp	x8, _VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR@GOTPAGE
Lloh55:
	ldr	x8, [x8, _VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR@GOTPAGEOFF]
Lloh56:
	ldr	w0, [x8]
	ldr	w8, [x19, #28]
	asr	w1, w8, #12
	bl	_WREG32
Lloh57:
	adrp	x8, _VM_CONTEXT0_CNTL2@GOTPAGE
Lloh58:
	ldr	x8, [x8, _VM_CONTEXT0_CNTL2@GOTPAGEOFF]
Lloh59:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh60:
	adrp	x8, _VM_CONTEXT0_CNTL@GOTPAGE
Lloh61:
	ldr	x8, [x8, _VM_CONTEXT0_CNTL@GOTPAGEOFF]
Lloh62:
	ldr	w20, [x8]
Lloh63:
	adrp	x26, _ENABLE_CONTEXT@GOTPAGE
Lloh64:
	ldr	x26, [x26, _ENABLE_CONTEXT@GOTPAGEOFF]
	ldr	w22, [x26]
	mov	w0, #0
	bl	_PAGE_TABLE_DEPTH
	orr	w8, w0, w22
Lloh65:
	adrp	x22, _RANGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGE
Lloh66:
	ldr	x22, [x22, _RANGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGEOFF]
	ldr	w9, [x22]
	orr	w1, w8, w9
	mov	x0, x20
	bl	_WREG32
	mov	w0, #5588
	mov	w1, #0
	bl	_WREG32
	mov	w0, #5592
	mov	w1, #0
	bl	_WREG32
	mov	w0, #5596
	mov	w1, #0
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #4
	mov	w1, #0
	bl	_WREG32
	ldr	w8, [x24]
	add	w0, w8, #4
	ldr	w8, [x19, #32]
	sub	w1, w8, #1
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #4
	ldr	x8, [x19, #40]
	ldr	w1, [x8, #4]
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #8
	mov	w1, #0
	bl	_WREG32
	ldr	w8, [x24]
	add	w0, w8, #8
	ldr	w8, [x19, #32]
	sub	w1, w8, #1
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #8
	ldr	x8, [x19, #40]
	ldr	w1, [x8, #8]
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #12
	mov	w1, #0
	bl	_WREG32
	ldr	w8, [x24]
	add	w0, w8, #12
	ldr	w8, [x19, #32]
	sub	w1, w8, #1
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #12
	ldr	x8, [x19, #40]
	ldr	w1, [x8, #12]
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #16
	mov	w1, #0
	bl	_WREG32
	ldr	w8, [x24]
	add	w0, w8, #16
	ldr	w8, [x19, #32]
	sub	w1, w8, #1
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #16
	ldr	x8, [x19, #40]
	ldr	w1, [x8, #16]
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #20
	mov	w1, #0
	bl	_WREG32
	ldr	w8, [x24]
	add	w0, w8, #20
	ldr	w8, [x19, #32]
	sub	w1, w8, #1
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #20
	ldr	x8, [x19, #40]
	ldr	w1, [x8, #20]
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #24
	mov	w1, #0
	bl	_WREG32
	ldr	w8, [x24]
	add	w0, w8, #24
	ldr	w8, [x19, #32]
	sub	w1, w8, #1
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #24
	ldr	x8, [x19, #40]
	ldr	w1, [x8, #24]
	bl	_WREG32
	ldr	w8, [x23]
	add	w0, w8, #28
	mov	w1, #0
	bl	_WREG32
	ldr	w8, [x24]
	add	w0, w8, #28
	ldr	w8, [x19, #32]
	sub	w1, w8, #1
	bl	_WREG32
	ldr	w8, [x25]
	add	w0, w8, #28
	ldr	x8, [x19, #40]
	ldr	w1, [x8, #28]
	bl	_WREG32
Lloh67:
	adrp	x8, _VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR@GOTPAGE
Lloh68:
	ldr	x8, [x8, _VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR@GOTPAGEOFF]
Lloh69:
	ldr	w0, [x8]
	ldr	w8, [x19, #28]
	asr	w1, w8, #12
	bl	_WREG32
Lloh70:
	adrp	x8, _VM_CONTEXT1_CNTL2@GOTPAGE
Lloh71:
	ldr	x8, [x8, _VM_CONTEXT1_CNTL2@GOTPAGEOFF]
Lloh72:
	ldr	w0, [x8]
	mov	w1, #4
	bl	_WREG32
Lloh73:
	adrp	x8, _VM_CONTEXT1_CNTL@GOTPAGE
Lloh74:
	ldr	x8, [x8, _VM_CONTEXT1_CNTL@GOTPAGEOFF]
Lloh75:
	ldr	w20, [x8]
	ldr	w23, [x26]
	mov	w0, #1
	bl	_PAGE_TABLE_DEPTH
	orr	w23, w0, w23
Lloh76:
	adrp	x8, _radeon_vm_block_size@GOTPAGE
Lloh77:
	ldr	x8, [x8, _radeon_vm_block_size@GOTPAGEOFF]
Lloh78:
	ldr	x8, [x8]
	sub	x0, x8, #9
	bl	_PAGE_TABLE_BLOCK_SIZE
	orr	w8, w23, w0
Lloh79:
	adrp	x9, _RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT@GOTPAGE
Lloh80:
	ldr	x9, [x9, _RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT@GOTPAGEOFF]
Lloh81:
	ldr	w9, [x9]
	orr	w8, w8, w9
	ldr	w9, [x22]
	orr	w8, w8, w9
Lloh82:
	adrp	x9, _DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT@GOTPAGE
Lloh83:
	ldr	x9, [x9, _DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT@GOTPAGEOFF]
Lloh84:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh85:
	adrp	x9, _DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGE
Lloh86:
	ldr	x9, [x9, _DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGEOFF]
Lloh87:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh88:
	adrp	x9, _PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT@GOTPAGE
Lloh89:
	ldr	x9, [x9, _PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT@GOTPAGEOFF]
Lloh90:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh91:
	adrp	x9, _PDE0_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGE
Lloh92:
	ldr	x9, [x9, _PDE0_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGEOFF]
Lloh93:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh94:
	adrp	x9, _VALID_PROTECTION_FAULT_ENABLE_INTERRUPT@GOTPAGE
Lloh95:
	ldr	x9, [x9, _VALID_PROTECTION_FAULT_ENABLE_INTERRUPT@GOTPAGEOFF]
Lloh96:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh97:
	adrp	x9, _VALID_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGE
Lloh98:
	ldr	x9, [x9, _VALID_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGEOFF]
Lloh99:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh100:
	adrp	x9, _READ_PROTECTION_FAULT_ENABLE_INTERRUPT@GOTPAGE
Lloh101:
	ldr	x9, [x9, _READ_PROTECTION_FAULT_ENABLE_INTERRUPT@GOTPAGEOFF]
Lloh102:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh103:
	adrp	x9, _READ_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGE
Lloh104:
	ldr	x9, [x9, _READ_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGEOFF]
Lloh105:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh106:
	adrp	x9, _WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT@GOTPAGE
Lloh107:
	ldr	x9, [x9, _WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT@GOTPAGEOFF]
Lloh108:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh109:
	adrp	x9, _WRITE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGE
Lloh110:
	ldr	x9, [x9, _WRITE_PROTECTION_FAULT_ENABLE_DEFAULT@GOTPAGEOFF]
Lloh111:
	ldr	w9, [x9]
	orr	w1, w8, w9
	mov	x0, x20
	bl	_WREG32
	mov	x0, x19
	bl	_cayman_pcie_gart_tlb_flush
	ldr	w8, [x19, #24]
	asr	w1, w8, #20
	ldrsw	x2, [x19]
Lloh112:
	adrp	x0, l_.str.1@PAGE
Lloh113:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_INFO
	mov	w0, #0
	str	w21, [x19, #4]
	b	LBB0_4
LBB0_3:
	ldr	w0, [x19, #48]
Lloh114:
	adrp	x1, l_.str@PAGE
Lloh115:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
Lloh116:
	adrp	x8, _EINVAL@GOTPAGE
Lloh117:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh118:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_4:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGot	Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh37
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpAdd	Lloh114, Lloh115
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"No VRAM object for PCIE GART.\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_MC_VM_MX_L1_TLB_CNTL,4,2       ; @MC_VM_MX_L1_TLB_CNTL
	.comm	_ENABLE_L1_TLB,4,2              ; @ENABLE_L1_TLB
	.comm	_ENABLE_L1_FRAGMENT_PROCESSING,4,2 ; @ENABLE_L1_FRAGMENT_PROCESSING
	.comm	_SYSTEM_ACCESS_MODE_NOT_IN_SYS,4,2 ; @SYSTEM_ACCESS_MODE_NOT_IN_SYS
	.comm	_ENABLE_ADVANCED_DRIVER_MODEL,4,2 ; @ENABLE_ADVANCED_DRIVER_MODEL
	.comm	_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU,4,2 ; @SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
	.comm	_VM_L2_CNTL,4,2                 ; @VM_L2_CNTL
	.comm	_ENABLE_L2_CACHE,4,2            ; @ENABLE_L2_CACHE
	.comm	_ENABLE_L2_FRAGMENT_PROCESSING,4,2 ; @ENABLE_L2_FRAGMENT_PROCESSING
	.comm	_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE,4,2 ; @ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE,4,2 ; @ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE
	.comm	_VM_L2_CNTL2,4,2                ; @VM_L2_CNTL2
	.comm	_INVALIDATE_ALL_L1_TLBS,4,2     ; @INVALIDATE_ALL_L1_TLBS
	.comm	_INVALIDATE_L2_CACHE,4,2        ; @INVALIDATE_L2_CACHE
	.comm	_VM_L2_CNTL3,4,2                ; @VM_L2_CNTL3
	.comm	_L2_CACHE_BIGK_ASSOCIATIVITY,4,2 ; @L2_CACHE_BIGK_ASSOCIATIVITY
	.comm	_VM_CONTEXT0_PAGE_TABLE_START_ADDR,4,2 ; @VM_CONTEXT0_PAGE_TABLE_START_ADDR
	.comm	_VM_CONTEXT0_PAGE_TABLE_END_ADDR,4,2 ; @VM_CONTEXT0_PAGE_TABLE_END_ADDR
	.comm	_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR,4,2 ; @VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
	.comm	_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,4,2 ; @VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
	.comm	_VM_CONTEXT0_CNTL2,4,2          ; @VM_CONTEXT0_CNTL2
	.comm	_VM_CONTEXT0_CNTL,4,2           ; @VM_CONTEXT0_CNTL
	.comm	_ENABLE_CONTEXT,4,2             ; @ENABLE_CONTEXT
	.comm	_RANGE_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ; @RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,4,2 ; @VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR
	.comm	_VM_CONTEXT1_CNTL2,4,2          ; @VM_CONTEXT1_CNTL2
	.comm	_VM_CONTEXT1_CNTL,4,2           ; @VM_CONTEXT1_CNTL
	.comm	_radeon_vm_block_size,8,3       ; @radeon_vm_block_size
	.comm	_RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT,4,2 ; @RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT
	.comm	_DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT,4,2 ; @DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT
	.comm	_DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ; @DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT,4,2 ; @PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT
	.comm	_PDE0_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ; @PDE0_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_VALID_PROTECTION_FAULT_ENABLE_INTERRUPT,4,2 ; @VALID_PROTECTION_FAULT_ENABLE_INTERRUPT
	.comm	_VALID_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ; @VALID_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_READ_PROTECTION_FAULT_ENABLE_INTERRUPT,4,2 ; @READ_PROTECTION_FAULT_ENABLE_INTERRUPT
	.comm	_READ_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ; @READ_PROTECTION_FAULT_ENABLE_DEFAULT
	.comm	_WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT,4,2 ; @WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT
	.comm	_WRITE_PROTECTION_FAULT_ENABLE_DEFAULT,4,2 ; @WRITE_PROTECTION_FAULT_ENABLE_DEFAULT
l_.str.1:                               ; @.str.1
	.asciz	"PCIE GART of %uM enabled (table at 0x%016llX).\n"

	.no_dead_strip	_cayman_pcie_gart_enable
.subsections_via_symbols
