	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_legacy_tv_dac_dpms
_radeon_legacy_tv_dac_dpms:             ## @radeon_legacy_tv_dac_dpms
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
                                        ## kill: def $esi killed $esi def $rsi
	movq	%rsi, -64(%rbp)                 ## 8-byte Spill
	movq	%rdi, %rbx
	movq	(%rdi), %rax
	movq	(%rax), %r12
	callq	_to_radeon_encoder
	movq	%rax, %r14
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	movq	_ATOM_DEVICE_TV_SUPPORT@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	andl	(%r14), %r15d
	movq	%r12, -56(%rbp)                 ## 8-byte Spill
	movq	(%r12), %rax
	movq	_CHIP_R200@GOTPCREL(%rip), %r14
	cmpq	(%r14), %rax
	movq	%rbx, -48(%rbp)                 ## 8-byte Spill
	jne	LBB0_2
## %bb.1:
	movq	_RADEON_FP2_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	xorl	%r13d, %r13d
	xorl	%ebx, %ebx
	xorl	%r12d, %r12d
	jmp	LBB0_6
LBB0_2:
	testl	%r15d, %r15d
	je	LBB0_4
## %bb.3:
	movq	_RADEON_TV_MASTER_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r12d
	xorl	%r13d, %r13d
	jmp	LBB0_5
LBB0_4:
	movq	_RADEON_CRTC2_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r13d
	xorl	%r12d, %r12d
LBB0_5:
	movq	_RADEON_TV_DAC_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %ebx
	xorl	%eax, %eax
LBB0_6:
	movq	-64(%rbp), %rdx                 ## 8-byte Reload
	leal	-128(%rdx), %ecx
	cmpl	$2, %ecx
	jb	LBB0_9
## %bb.7:
	cmpl	$130, %edx
	je	LBB0_13
## %bb.8:
	cmpl	$131, %edx
	jne	LBB0_16
LBB0_9:
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	movq	(%rcx), %rcx
	movq	(%r14), %r10
	cmpq	%r10, %rcx
	jne	LBB0_11
## %bb.10:
	movq	_RADEON_FP2_ON@GOTPCREL(%rip), %rcx
	movq	_RADEON_FP2_DVO_EN@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	notl	%edx
	andl	%edx, %eax
	jmp	LBB0_15
LBB0_11:
	testl	%r15d, %r15d
	je	LBB0_18
## %bb.12:
	movq	_RADEON_TV_ON@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	notl	%edx
	andl	%edx, %r12d
	jmp	LBB0_19
LBB0_13:
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	movq	(%rcx), %rcx
	movq	(%r14), %r10
	cmpq	%r10, %rcx
	jne	LBB0_26
## %bb.14:
	movq	_RADEON_FP2_ON@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_FP2_DVO_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
LBB0_15:
	movq	_RADEON_FP2_GEN_CNTL@GOTPCREL(%rip), %rcx
	movl	%eax, %ebx
	movq	-48(%rbp), %r14                 ## 8-byte Reload
	jmp	LBB0_37
LBB0_16:
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	movq	(%rcx), %rcx
	movq	(%r14), %r10
	movl	%r13d, %r9d
	movl	%r12d, %esi
	jmp	LBB0_17
LBB0_18:
	movq	_RADEON_CRTC2_CRT2_ON@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	notl	%edx
	andl	%edx, %r13d
LBB0_19:
	movl	%r13d, %r9d
	movl	%r12d, %esi
	movq	_CHIP_R420@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	movq	-48(%rbp), %r14                 ## 8-byte Reload
	je	LBB0_23
## %bb.20:
	movq	_CHIP_R423@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	je	LBB0_23
## %bb.21:
	movq	_CHIP_RV410@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	je	LBB0_23
## %bb.22:
	movq	_RADEON_TV_DAC_RDACPD@GOTPCREL(%rip), %rdx
	movq	_RADEON_TV_DAC_GDACPD@GOTPCREL(%rip), %rdi
	movq	_RADEON_TV_DAC_BDACPD@GOTPCREL(%rip), %r8
	jmp	LBB0_24
LBB0_23:
	movq	_R420_TV_DAC_RDACPD@GOTPCREL(%rip), %rdx
	movq	_R420_TV_DAC_GDACPD@GOTPCREL(%rip), %rdi
	movq	_R420_TV_DAC_BDACPD@GOTPCREL(%rip), %r8
LBB0_24:
	movq	_RADEON_TV_DAC_BGSLEEP@GOTPCREL(%rip), %r11
	orl	(%rdx), %ebx
	orl	(%rdi), %ebx
	orl	(%r8), %ebx
	orl	(%r11), %ebx
	cmpq	%r10, %rcx
	jne	LBB0_32
LBB0_25:
	movq	_RADEON_FP2_GEN_CNTL@GOTPCREL(%rip), %rcx
	movl	%eax, %ebx
	jmp	LBB0_37
LBB0_26:
	xorl	%r9d, %r9d
	testl	%r15d, %r15d
	movq	_RADEON_TV_ON@GOTPCREL(%rip), %r8
	movq	_RADEON_CRTC2_CRT2_ON@GOTPCREL(%rip), %rsi
	cmovel	(%rsi), %r9d
	movl	(%r8), %esi
	cmovel	%r15d, %esi
	orl	%r13d, %r9d
	orl	%r12d, %esi
	movq	_CHIP_R420@GOTPCREL(%rip), %rdi
	cmpq	(%rdi), %rcx
	je	LBB0_30
## %bb.27:
	movq	_CHIP_R423@GOTPCREL(%rip), %rdi
	cmpq	(%rdi), %rcx
	je	LBB0_30
## %bb.28:
	movq	_CHIP_RV410@GOTPCREL(%rip), %rdi
	cmpq	(%rdi), %rcx
	je	LBB0_30
## %bb.29:
	movq	_RADEON_TV_DAC_RDACPD@GOTPCREL(%rip), %rdx
	movq	_RADEON_TV_DAC_GDACPD@GOTPCREL(%rip), %rdi
	movl	(%rdi), %edi
	orl	(%rdx), %edi
	movq	_RADEON_TV_DAC_BDACPD@GOTPCREL(%rip), %rdx
	jmp	LBB0_31
LBB0_30:
	movq	_R420_TV_DAC_RDACPD@GOTPCREL(%rip), %r8
	movq	_R420_TV_DAC_GDACPD@GOTPCREL(%rip), %rdi
	movl	(%rdi), %edi
	orl	(%r8), %edi
	movq	_R420_TV_DAC_BDACPD@GOTPCREL(%rip), %rdx
LBB0_31:
	orl	(%rdx), %edi
	movq	_RADEON_TV_DAC_BGSLEEP@GOTPCREL(%rip), %rdx
	orl	(%rdx), %edi
	notl	%edi
	andl	%edi, %ebx
LBB0_17:
	movq	-48(%rbp), %r14                 ## 8-byte Reload
	cmpq	%r10, %rcx
	je	LBB0_25
LBB0_32:
	testl	%r15d, %r15d
	je	LBB0_35
## %bb.33:
	movq	_RADEON_TV_MASTER_CNTL@GOTPCREL(%rip), %rax
LBB0_34:
	movl	(%rax), %edi
	callq	_WREG32
	jmp	LBB0_36
LBB0_35:
	movq	_RADEON_SINGLE_CRTC@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	testl	%eax, 8(%rcx)
	je	LBB0_40
LBB0_36:
	movq	_RADEON_TV_DAC_CNTL@GOTPCREL(%rip), %rcx
LBB0_37:
	movl	(%rcx), %edi
	movl	%ebx, %esi
	callq	_WREG32
	xorl	%esi, %esi
	cmpl	$130, -64(%rbp)                 ## 4-byte Folded Reload
	sete	%sil
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	cmpq	$0, 16(%rax)
	je	LBB0_39
## %bb.38:
	movq	%r14, %rdi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_atombios_encoder_dpms_scratch_regs ## TAILCALL
LBB0_39:
	movq	%r14, %rdi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_combios_encoder_dpms_scratch_regs ## TAILCALL
LBB0_40:
	movq	_RADEON_CRTC2_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	%r9d, %esi
	jmp	LBB0_34
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"\n"

	.comm	_ATOM_DEVICE_TV_SUPPORT,4,2     ## @ATOM_DEVICE_TV_SUPPORT
	.comm	_CHIP_R200,8,3                  ## @CHIP_R200
	.comm	_RADEON_FP2_GEN_CNTL,4,2        ## @RADEON_FP2_GEN_CNTL
	.comm	_RADEON_TV_MASTER_CNTL,4,2      ## @RADEON_TV_MASTER_CNTL
	.comm	_RADEON_CRTC2_GEN_CNTL,4,2      ## @RADEON_CRTC2_GEN_CNTL
	.comm	_RADEON_TV_DAC_CNTL,4,2         ## @RADEON_TV_DAC_CNTL
	.comm	_RADEON_FP2_ON,4,2              ## @RADEON_FP2_ON
	.comm	_RADEON_FP2_DVO_EN,4,2          ## @RADEON_FP2_DVO_EN
	.comm	_RADEON_TV_ON,4,2               ## @RADEON_TV_ON
	.comm	_RADEON_CRTC2_CRT2_ON,4,2       ## @RADEON_CRTC2_CRT2_ON
	.comm	_CHIP_R420,8,3                  ## @CHIP_R420
	.comm	_CHIP_R423,8,3                  ## @CHIP_R423
	.comm	_CHIP_RV410,8,3                 ## @CHIP_RV410
	.comm	_R420_TV_DAC_RDACPD,4,2         ## @R420_TV_DAC_RDACPD
	.comm	_R420_TV_DAC_GDACPD,4,2         ## @R420_TV_DAC_GDACPD
	.comm	_R420_TV_DAC_BDACPD,4,2         ## @R420_TV_DAC_BDACPD
	.comm	_RADEON_TV_DAC_BGSLEEP,4,2      ## @RADEON_TV_DAC_BGSLEEP
	.comm	_RADEON_TV_DAC_RDACPD,4,2       ## @RADEON_TV_DAC_RDACPD
	.comm	_RADEON_TV_DAC_GDACPD,4,2       ## @RADEON_TV_DAC_GDACPD
	.comm	_RADEON_TV_DAC_BDACPD,4,2       ## @RADEON_TV_DAC_BDACPD
	.comm	_RADEON_SINGLE_CRTC,4,2         ## @RADEON_SINGLE_CRTC
	.no_dead_strip	_radeon_legacy_tv_dac_dpms
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_legacy_tv_dac_dpms
_radeon_legacy_tv_dac_dpms:             ; @radeon_legacy_tv_dac_dpms
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x1
	mov	x19, x0
	ldr	x8, [x0]
	ldr	x24, [x8]
	bl	_to_radeon_encoder
	mov	x21, x0
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_KMS
	ldr	w8, [x21]
Lloh2:
	adrp	x9, _ATOM_DEVICE_TV_SUPPORT@GOTPAGE
Lloh3:
	ldr	x9, [x9, _ATOM_DEVICE_TV_SUPPORT@GOTPAGEOFF]
Lloh4:
	ldr	w9, [x9]
	and	w25, w9, w8
	ldr	x8, [x24]
Lloh5:
	adrp	x26, _CHIP_R200@GOTPAGE
Lloh6:
	ldr	x26, [x26, _CHIP_R200@GOTPAGEOFF]
	ldr	x9, [x26]
	cmp	x8, x9
	b.ne	LBB0_2
; %bb.1:
Lloh7:
	adrp	x8, _RADEON_FP2_GEN_CNTL@GOTPAGE
Lloh8:
	ldr	x8, [x8, _RADEON_FP2_GEN_CNTL@GOTPAGEOFF]
Lloh9:
	ldr	w0, [x8]
	bl	_RREG32
	mov	w22, #0
	mov	w21, #0
	mov	w23, #0
	b	LBB0_6
LBB0_2:
	cbz	w25, LBB0_4
; %bb.3:
Lloh10:
	adrp	x8, _RADEON_TV_MASTER_CNTL@GOTPAGE
Lloh11:
	ldr	x8, [x8, _RADEON_TV_MASTER_CNTL@GOTPAGEOFF]
Lloh12:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x23, x0
	mov	w22, #0
	b	LBB0_5
LBB0_4:
Lloh13:
	adrp	x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGE
Lloh14:
	ldr	x8, [x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGEOFF]
Lloh15:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x22, x0
	mov	w23, #0
LBB0_5:
Lloh16:
	adrp	x8, _RADEON_TV_DAC_CNTL@GOTPAGE
Lloh17:
	ldr	x8, [x8, _RADEON_TV_DAC_CNTL@GOTPAGEOFF]
Lloh18:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x21, x0
	mov	w0, #0
LBB0_6:
	sub	w8, w20, #128
	cmp	w8, #2
	b.lo	LBB0_9
; %bb.7:
	cmp	w20, #130
	b.eq	LBB0_13
; %bb.8:
	cmp	w20, #131
	b.ne	LBB0_16
LBB0_9:
	ldr	x8, [x24]
	ldr	x9, [x26]
	cmp	x8, x9
	b.ne	LBB0_11
; %bb.10:
Lloh19:
	adrp	x8, _RADEON_FP2_ON@GOTPAGE
Lloh20:
	ldr	x8, [x8, _RADEON_FP2_ON@GOTPAGEOFF]
Lloh21:
	adrp	x9, _RADEON_FP2_DVO_EN@GOTPAGE
Lloh22:
	ldr	x9, [x9, _RADEON_FP2_DVO_EN@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
Lloh24:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w21, w0, w8
	b	LBB0_15
LBB0_11:
	cbz	w25, LBB0_20
; %bb.12:
Lloh25:
	adrp	x10, _RADEON_TV_ON@GOTPAGE
Lloh26:
	ldr	x10, [x10, _RADEON_TV_ON@GOTPAGEOFF]
Lloh27:
	ldr	w10, [x10]
	bic	w23, w23, w10
	b	LBB0_21
LBB0_13:
	ldr	x8, [x24]
	ldr	x9, [x26]
	cmp	x8, x9
	b.ne	LBB0_31
; %bb.14:
Lloh28:
	adrp	x8, _RADEON_FP2_ON@GOTPAGE
Lloh29:
	ldr	x8, [x8, _RADEON_FP2_ON@GOTPAGEOFF]
Lloh30:
	adrp	x9, _RADEON_FP2_DVO_EN@GOTPAGE
Lloh31:
	ldr	x9, [x9, _RADEON_FP2_DVO_EN@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
Lloh33:
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w21, w8, w9
LBB0_15:
Lloh34:
	adrp	x8, _RADEON_FP2_GEN_CNTL@GOTPAGE
Lloh35:
	ldr	x8, [x8, _RADEON_FP2_GEN_CNTL@GOTPAGEOFF]
	b	LBB0_28
LBB0_16:
	ldr	x8, [x24]
	ldr	x9, [x26]
	cmp	x8, x9
	b.eq	LBB0_25
LBB0_17:
	cbz	w25, LBB0_26
; %bb.18:
Lloh36:
	adrp	x8, _RADEON_TV_MASTER_CNTL@GOTPAGE
Lloh37:
	ldr	x8, [x8, _RADEON_TV_MASTER_CNTL@GOTPAGEOFF]
LBB0_19:
	ldr	w0, [x8]
	mov	x1, x23
	bl	_WREG32
	b	LBB0_27
LBB0_20:
Lloh38:
	adrp	x10, _RADEON_CRTC2_CRT2_ON@GOTPAGE
Lloh39:
	ldr	x10, [x10, _RADEON_CRTC2_CRT2_ON@GOTPAGEOFF]
Lloh40:
	ldr	w10, [x10]
	bic	w22, w22, w10
LBB0_21:
Lloh41:
	adrp	x10, _CHIP_R420@GOTPAGE
Lloh42:
	ldr	x10, [x10, _CHIP_R420@GOTPAGEOFF]
Lloh43:
	ldr	x10, [x10]
Lloh44:
	adrp	x11, _CHIP_R423@GOTPAGE
Lloh45:
	ldr	x11, [x11, _CHIP_R423@GOTPAGEOFF]
Lloh46:
	ldr	x11, [x11]
Lloh47:
	adrp	x12, _CHIP_RV410@GOTPAGE
Lloh48:
	ldr	x12, [x12, _CHIP_RV410@GOTPAGEOFF]
Lloh49:
	ldr	x12, [x12]
	cmp	x8, x10
	ccmp	x8, x11, #4, ne
	ccmp	x8, x12, #4, ne
	b.ne	LBB0_23
; %bb.22:
Lloh50:
	adrp	x10, _R420_TV_DAC_RDACPD@GOTPAGE
Lloh51:
	ldr	x10, [x10, _R420_TV_DAC_RDACPD@GOTPAGEOFF]
Lloh52:
	adrp	x11, _R420_TV_DAC_GDACPD@GOTPAGE
Lloh53:
	ldr	x11, [x11, _R420_TV_DAC_GDACPD@GOTPAGEOFF]
Lloh54:
	ldr	w10, [x10]
Lloh55:
	ldr	w11, [x11]
Lloh56:
	adrp	x12, _R420_TV_DAC_BDACPD@GOTPAGE
Lloh57:
	ldr	x12, [x12, _R420_TV_DAC_BDACPD@GOTPAGEOFF]
	b	LBB0_24
LBB0_23:
Lloh58:
	adrp	x10, _RADEON_TV_DAC_RDACPD@GOTPAGE
Lloh59:
	ldr	x10, [x10, _RADEON_TV_DAC_RDACPD@GOTPAGEOFF]
Lloh60:
	adrp	x11, _RADEON_TV_DAC_GDACPD@GOTPAGE
Lloh61:
	ldr	x11, [x11, _RADEON_TV_DAC_GDACPD@GOTPAGEOFF]
Lloh62:
	ldr	w10, [x10]
Lloh63:
	ldr	w11, [x11]
Lloh64:
	adrp	x12, _RADEON_TV_DAC_BDACPD@GOTPAGE
Lloh65:
	ldr	x12, [x12, _RADEON_TV_DAC_BDACPD@GOTPAGEOFF]
LBB0_24:
Lloh66:
	adrp	x13, _RADEON_TV_DAC_BGSLEEP@GOTPAGE
Lloh67:
	ldr	x13, [x13, _RADEON_TV_DAC_BGSLEEP@GOTPAGEOFF]
	ldr	w12, [x12]
Lloh68:
	ldr	w13, [x13]
	orr	w10, w10, w21
	orr	w10, w10, w11
	orr	w10, w10, w12
	orr	w21, w10, w13
	cmp	x8, x9
	b.ne	LBB0_17
LBB0_25:
Lloh69:
	adrp	x8, _RADEON_FP2_GEN_CNTL@GOTPAGE
Lloh70:
	ldr	x8, [x8, _RADEON_FP2_GEN_CNTL@GOTPAGEOFF]
	mov	x21, x0
	b	LBB0_28
LBB0_26:
	ldr	w8, [x24, #8]
Lloh71:
	adrp	x9, _RADEON_SINGLE_CRTC@GOTPAGE
Lloh72:
	ldr	x9, [x9, _RADEON_SINGLE_CRTC@GOTPAGEOFF]
Lloh73:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_35
LBB0_27:
Lloh74:
	adrp	x8, _RADEON_TV_DAC_CNTL@GOTPAGE
Lloh75:
	ldr	x8, [x8, _RADEON_TV_DAC_CNTL@GOTPAGEOFF]
LBB0_28:
	ldr	w0, [x8]
	mov	x1, x21
	bl	_WREG32
	ldr	x8, [x24, #16]
	cmp	w20, #130
	cset	w1, eq
	mov	x0, x19
	cbz	x8, LBB0_30
; %bb.29:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_radeon_atombios_encoder_dpms_scratch_regs
LBB0_30:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_radeon_combios_encoder_dpms_scratch_regs
LBB0_31:
Lloh76:
	adrp	x10, _RADEON_TV_ON@GOTPAGE
Lloh77:
	ldr	x10, [x10, _RADEON_TV_ON@GOTPAGEOFF]
Lloh78:
	ldr	w10, [x10]
Lloh79:
	adrp	x11, _RADEON_CRTC2_CRT2_ON@GOTPAGE
Lloh80:
	ldr	x11, [x11, _RADEON_CRTC2_CRT2_ON@GOTPAGEOFF]
Lloh81:
	ldr	w11, [x11]
	cmp	w25, #0
	csel	w11, w11, wzr, eq
	orr	w22, w11, w22
	csel	w10, wzr, w10, eq
	orr	w23, w10, w23
Lloh82:
	adrp	x10, _CHIP_R420@GOTPAGE
Lloh83:
	ldr	x10, [x10, _CHIP_R420@GOTPAGEOFF]
Lloh84:
	ldr	x10, [x10]
Lloh85:
	adrp	x11, _CHIP_R423@GOTPAGE
Lloh86:
	ldr	x11, [x11, _CHIP_R423@GOTPAGEOFF]
Lloh87:
	ldr	x11, [x11]
Lloh88:
	adrp	x12, _CHIP_RV410@GOTPAGE
Lloh89:
	ldr	x12, [x12, _CHIP_RV410@GOTPAGEOFF]
Lloh90:
	ldr	x12, [x12]
	cmp	x8, x10
	ccmp	x8, x11, #4, ne
	ccmp	x8, x12, #4, ne
	b.ne	LBB0_33
; %bb.32:
Lloh91:
	adrp	x10, _R420_TV_DAC_RDACPD@GOTPAGE
Lloh92:
	ldr	x10, [x10, _R420_TV_DAC_RDACPD@GOTPAGEOFF]
Lloh93:
	adrp	x11, _R420_TV_DAC_GDACPD@GOTPAGE
Lloh94:
	ldr	x11, [x11, _R420_TV_DAC_GDACPD@GOTPAGEOFF]
Lloh95:
	ldr	w10, [x10]
Lloh96:
	ldr	w11, [x11]
	orr	w10, w11, w10
Lloh97:
	adrp	x11, _R420_TV_DAC_BDACPD@GOTPAGE
Lloh98:
	ldr	x11, [x11, _R420_TV_DAC_BDACPD@GOTPAGEOFF]
	b	LBB0_34
LBB0_33:
Lloh99:
	adrp	x10, _RADEON_TV_DAC_RDACPD@GOTPAGE
Lloh100:
	ldr	x10, [x10, _RADEON_TV_DAC_RDACPD@GOTPAGEOFF]
Lloh101:
	adrp	x11, _RADEON_TV_DAC_GDACPD@GOTPAGE
Lloh102:
	ldr	x11, [x11, _RADEON_TV_DAC_GDACPD@GOTPAGEOFF]
Lloh103:
	ldr	w10, [x10]
Lloh104:
	ldr	w11, [x11]
	orr	w10, w11, w10
Lloh105:
	adrp	x11, _RADEON_TV_DAC_BDACPD@GOTPAGE
Lloh106:
	ldr	x11, [x11, _RADEON_TV_DAC_BDACPD@GOTPAGEOFF]
LBB0_34:
	ldr	w11, [x11]
	orr	w10, w10, w11
Lloh107:
	adrp	x11, _RADEON_TV_DAC_BGSLEEP@GOTPAGE
Lloh108:
	ldr	x11, [x11, _RADEON_TV_DAC_BGSLEEP@GOTPAGEOFF]
Lloh109:
	ldr	w11, [x11]
	orr	w10, w10, w11
	bic	w21, w21, w10
	cmp	x8, x9
	b.eq	LBB0_25
	b	LBB0_17
LBB0_35:
Lloh110:
	adrp	x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGE
Lloh111:
	ldr	x8, [x8, _RADEON_CRTC2_GEN_CNTL@GOTPAGEOFF]
	mov	x23, x22
	b	LBB0_19
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh23
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh32
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh54
	.loh AdrpLdrGot	Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh62
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGot	Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGot	Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGot	Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh95
	.loh AdrpLdrGot	Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh103
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGot	Lloh110, Lloh111
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"\n"

	.comm	_ATOM_DEVICE_TV_SUPPORT,4,2     ; @ATOM_DEVICE_TV_SUPPORT
	.comm	_CHIP_R200,8,3                  ; @CHIP_R200
	.comm	_RADEON_FP2_GEN_CNTL,4,2        ; @RADEON_FP2_GEN_CNTL
	.comm	_RADEON_TV_MASTER_CNTL,4,2      ; @RADEON_TV_MASTER_CNTL
	.comm	_RADEON_CRTC2_GEN_CNTL,4,2      ; @RADEON_CRTC2_GEN_CNTL
	.comm	_RADEON_TV_DAC_CNTL,4,2         ; @RADEON_TV_DAC_CNTL
	.comm	_RADEON_FP2_ON,4,2              ; @RADEON_FP2_ON
	.comm	_RADEON_FP2_DVO_EN,4,2          ; @RADEON_FP2_DVO_EN
	.comm	_RADEON_TV_ON,4,2               ; @RADEON_TV_ON
	.comm	_RADEON_CRTC2_CRT2_ON,4,2       ; @RADEON_CRTC2_CRT2_ON
	.comm	_CHIP_R420,8,3                  ; @CHIP_R420
	.comm	_CHIP_R423,8,3                  ; @CHIP_R423
	.comm	_CHIP_RV410,8,3                 ; @CHIP_RV410
	.comm	_R420_TV_DAC_RDACPD,4,2         ; @R420_TV_DAC_RDACPD
	.comm	_R420_TV_DAC_GDACPD,4,2         ; @R420_TV_DAC_GDACPD
	.comm	_R420_TV_DAC_BDACPD,4,2         ; @R420_TV_DAC_BDACPD
	.comm	_RADEON_TV_DAC_BGSLEEP,4,2      ; @RADEON_TV_DAC_BGSLEEP
	.comm	_RADEON_TV_DAC_RDACPD,4,2       ; @RADEON_TV_DAC_RDACPD
	.comm	_RADEON_TV_DAC_GDACPD,4,2       ; @RADEON_TV_DAC_GDACPD
	.comm	_RADEON_TV_DAC_BDACPD,4,2       ; @RADEON_TV_DAC_BDACPD
	.comm	_RADEON_SINGLE_CRTC,4,2         ; @RADEON_SINGLE_CRTC
	.no_dead_strip	_radeon_legacy_tv_dac_dpms
.subsections_via_symbols
