	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4                               ## -- Begin function si_dpm_init
LCPI0_0:
	.long	0                               ## 0x0
	.long	0                               ## 0x0
	.long	36000                           ## 0x8ca0
	.long	720                             ## 0x2d0
LCPI0_1:
	.long	54000                           ## 0xd2f0
	.long	810                             ## 0x32a
	.long	72000                           ## 0x11940
	.long	900                             ## 0x384
LCPI0_2:
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	0                               ## 0x0
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	4, 0x90
_si_dpm_init:                           ## @si_dpm_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_GFP_KERNEL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movl	$184, %edi
	callq	_kzalloc
	testq	%rax, %rax
	je	LBB0_1
## %bb.2:
	movq	%rax, %rbx
	movq	%rax, 128(%r14)
	movq	_CAIL_PCIE_LINK_SPEED_SUPPORT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%r14), %eax
	movl	%eax, (%rbx)
	movq	_AMDGPU_PCIE_GEN_INVALID@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 52(%rbx)
	movq	%r14, %rdi
	callq	_si_get_current_pcie_speed
	movl	%eax, 48(%rbx)
	movq	%r14, %rdi
	callq	_si_set_max_cu_value
	movq	%r14, %rdi
	callq	_rv770_get_max_vddc
	movq	%r14, %rdi
	callq	_si_get_leakage_vddc
	movq	%r14, %rdi
	callq	_si_patch_dependency_tables_based_on_leakage
	movq	$0, 96(%rbx)
	xorps	%xmm0, %xmm0
	movups	%xmm0, 160(%rbx)
	movq	$0, 176(%rbx)
	movq	%r14, %rdi
	callq	_amdgpu_get_platform_caps
	testl	%eax, %eax
	jne	LBB0_25
## %bb.3:
	movq	%r14, %rdi
	callq	_amdgpu_parse_extended_power_table
	testl	%eax, %eax
	jne	LBB0_25
## %bb.4:
	movq	%r14, %rdi
	callq	_si_parse_power_table
	testl	%eax, %eax
	jne	LBB0_25
## %bb.5:
	movl	(%r15), %edx
	movl	$4, %edi
	movl	$4, %esi
	callq	_kcalloc
	movq	%rax, 120(%r14)
	testq	%rax, %rax
	je	LBB0_6
## %bb.7:
	movl	$4, 112(%r14)
	movaps	LCPI0_0(%rip), %xmm0            ## xmm0 = [0,0,36000,720]
	movups	%xmm0, (%rax)
	movaps	LCPI0_1(%rip), %xmm0            ## xmm0 = [54000,810,72000,900]
	movups	%xmm0, 16(%rax)
	cmpq	$0, 16(%r14)
	jne	LBB0_9
## %bb.8:
	movq	_R600_VOLTAGERESPONSETIME_DFLT@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 16(%r14)
LBB0_9:
	cmpq	$0, 24(%r14)
	jne	LBB0_11
## %bb.10:
	movq	_R600_BACKBIASRESPONSETIME_DFLT@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 24(%r14)
LBB0_11:
	movq	_COMPUTE_ENGINE_PLL_PARAM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%r15d, %r15d
	leaq	-48(%rbp), %r8
	movq	%r14, %rdi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	callq	_amdgpu_atombios_get_clock_dividers
	testl	%eax, %eax
	jne	LBB0_12
## %bb.13:
	movq	_R600_REFERENCEDIVIDER_DFLT@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	jmp	LBB0_14
LBB0_6:
	movq	%r14, %rdi
	callq	_amdgpu_free_extended_power_table
LBB0_1:
	movq	_ENOMEM@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_25:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_12:
	movq	-48(%rbp), %rax
	incq	%rax
LBB0_14:
	movq	%rax, 152(%rbx)
	movl	$0, 64(%rbx)
	movl	$40000, 104(%rbx)               ## imm = 0x9C40
	movq	%r14, %rdi
	callq	_si_is_special_1gb_platform
	testq	%rax, %rax
	jne	LBB0_16
## %bb.15:
	movl	104(%rbx), %r15d
LBB0_16:
	movl	%r15d, 108(%rbx)
	movl	$40000, 112(%rbx)               ## imm = 0x9C40
	movl	$40000, 68(%rbx)                ## imm = 0x9C40
	movl	$40000, 56(%rbx)                ## imm = 0x9C40
	movq	_SET_VOLTAGE_TYPE_ASIC_VDDC@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_VOLTAGE_OBJ_GPIO_LUT@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movq	%r14, %rdi
	callq	_amdgpu_atombios_is_voltage_gpio
	movq	%rax, 144(%rbx)
	testq	%rax, %rax
	jne	LBB0_19
## %bb.17:
	movl	(%r15), %esi
	movq	_VOLTAGE_OBJ_SVID2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_amdgpu_atombios_is_voltage_gpio
	movq	%rax, 40(%rbx)
	testq	%rax, %rax
	je	LBB0_19
## %bb.18:
	movl	(%r15), %esi
	leaq	36(%rbx), %rdx
	movq	%rbx, %rcx
	addq	$32, %rcx
	movq	%r14, %rdi
	callq	_amdgpu_atombios_get_svi2_info
LBB0_19:
	movq	_SET_VOLTAGE_TYPE_ASIC_MVDDC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r12), %edx
	movq	%r14, %rdi
	callq	_amdgpu_atombios_is_voltage_gpio
	movq	%rax, 136(%rbx)
	movq	_SET_VOLTAGE_TYPE_ASIC_VDDCI@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movl	(%r12), %edx
	movq	%r14, %rdi
	callq	_amdgpu_atombios_is_voltage_gpio
	movq	%rax, 88(%rbx)
	testq	%rax, %rax
	jne	LBB0_21
## %bb.20:
	movl	(%r13), %esi
	movq	_VOLTAGE_OBJ_SVID2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_amdgpu_atombios_is_voltage_gpio
	movq	%rax, 24(%rbx)
LBB0_21:
	movl	(%r15), %esi
	movq	_VOLTAGE_OBJ_PHASE_LUT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_amdgpu_atombios_is_voltage_gpio
	movq	%rax, 16(%rbx)
	movq	%r14, %rdi
	callq	_rv770_get_engine_memory_ss
	movq	_RV770_ASI_DFLT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 132(%rbx)
	movq	_CYPRESS_HASI_DFLT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 128(%rbx)
	movq	_SISLANDS_VRC_DFLT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 124(%rbx)
	movl	$1, 116(%rbx)
	movl	$0, 4(%rbx)
	movq	8(%r14), %rax
	movq	_THERMAL_TYPE_NONE@GOTPCREL(%rip), %rcx
	xorl	%edx, %edx
	cmpq	(%rcx), %rax
	setne	%dl
	movl	%edx, 120(%rbx)
	movaps	LCPI0_2(%rip), %xmm0            ## xmm0 = [1,1,1,0]
	movups	%xmm0, 72(%rbx)
	movq	_SMC_RAM_END@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 12(%rbx)
	movabsq	$64424509440004, %rax           ## imm = 0x3A9800000004
	movq	%rax, 32(%r14)
	movl	$200, 40(%r14)
	xorps	%xmm0, %xmm0
	movups	%xmm0, 80(%r14)
	movups	%xmm0, 96(%r14)
	movq	%r14, %rdi
	callq	_si_initialize_powertune_defaults
	cmpq	$0, 64(%r14)
	je	LBB0_23
## %bb.22:
	cmpq	$0, 72(%r14)
	jne	LBB0_24
LBB0_23:
	movups	48(%r14), %xmm0
	addq	$64, %r14
	movups	%xmm0, (%r14)
LBB0_24:
	movl	$1, 8(%rbx)
	xorl	%eax, %eax
	jmp	LBB0_25
	.cfi_endproc
                                        ## -- End function
	.comm	_GFP_KERNEL,4,2                 ## @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ## @ENOMEM
	.comm	_CAIL_PCIE_LINK_SPEED_SUPPORT_MASK,4,2 ## @CAIL_PCIE_LINK_SPEED_SUPPORT_MASK
	.comm	_AMDGPU_PCIE_GEN_INVALID,4,2    ## @AMDGPU_PCIE_GEN_INVALID
	.comm	_R600_VOLTAGERESPONSETIME_DFLT,8,3 ## @R600_VOLTAGERESPONSETIME_DFLT
	.comm	_R600_BACKBIASRESPONSETIME_DFLT,8,3 ## @R600_BACKBIASRESPONSETIME_DFLT
	.comm	_COMPUTE_ENGINE_PLL_PARAM,4,2   ## @COMPUTE_ENGINE_PLL_PARAM
	.comm	_R600_REFERENCEDIVIDER_DFLT,8,3 ## @R600_REFERENCEDIVIDER_DFLT
	.comm	_SET_VOLTAGE_TYPE_ASIC_VDDC,4,2 ## @SET_VOLTAGE_TYPE_ASIC_VDDC
	.comm	_VOLTAGE_OBJ_GPIO_LUT,4,2       ## @VOLTAGE_OBJ_GPIO_LUT
	.comm	_VOLTAGE_OBJ_SVID2,4,2          ## @VOLTAGE_OBJ_SVID2
	.comm	_SET_VOLTAGE_TYPE_ASIC_MVDDC,4,2 ## @SET_VOLTAGE_TYPE_ASIC_MVDDC
	.comm	_SET_VOLTAGE_TYPE_ASIC_VDDCI,4,2 ## @SET_VOLTAGE_TYPE_ASIC_VDDCI
	.comm	_VOLTAGE_OBJ_PHASE_LUT,4,2      ## @VOLTAGE_OBJ_PHASE_LUT
	.comm	_RV770_ASI_DFLT,4,2             ## @RV770_ASI_DFLT
	.comm	_CYPRESS_HASI_DFLT,4,2          ## @CYPRESS_HASI_DFLT
	.comm	_SISLANDS_VRC_DFLT,4,2          ## @SISLANDS_VRC_DFLT
	.comm	_THERMAL_TYPE_NONE,8,3          ## @THERMAL_TYPE_NONE
	.comm	_SMC_RAM_END,4,2                ## @SMC_RAM_END
	.no_dead_strip	_si_dpm_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4                               ; -- Begin function si_dpm_init
lCPI0_0:
	.long	0                               ; 0x0
	.long	0                               ; 0x0
	.long	36000                           ; 0x8ca0
	.long	720                             ; 0x2d0
lCPI0_1:
	.long	54000                           ; 0xd2f0
	.long	810                             ; 0x32a
	.long	72000                           ; 0x11940
	.long	900                             ; 0x384
lCPI0_2:
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3
lCPI0_3:
	.long	4                               ; 0x4
	.long	15000                           ; 0x3a98
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	2
_si_dpm_init:                           ; @si_dpm_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x21, _GFP_KERNEL@GOTPAGE
Lloh1:
	ldr	x21, [x21, _GFP_KERNEL@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	w0, #184
	bl	_kzalloc
	cbz	x0, LBB0_21
; %bb.1:
	mov	x20, x0
	str	x0, [x19, #128]
	ldr	w8, [x19]
Lloh2:
	adrp	x9, _CAIL_PCIE_LINK_SPEED_SUPPORT_MASK@GOTPAGE
Lloh3:
	ldr	x9, [x9, _CAIL_PCIE_LINK_SPEED_SUPPORT_MASK@GOTPAGEOFF]
Lloh4:
	ldr	w9, [x9]
	and	w8, w9, w8
	str	w8, [x0]
Lloh5:
	adrp	x8, _AMDGPU_PCIE_GEN_INVALID@GOTPAGE
Lloh6:
	ldr	x8, [x8, _AMDGPU_PCIE_GEN_INVALID@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	str	w8, [x0, #52]
	mov	x0, x19
	bl	_si_get_current_pcie_speed
	str	w0, [x20, #48]
	mov	x0, x19
	bl	_si_set_max_cu_value
	mov	x0, x19
	bl	_rv770_get_max_vddc
	mov	x0, x19
	bl	_si_get_leakage_vddc
	mov	x0, x19
	bl	_si_patch_dependency_tables_based_on_leakage
	str	xzr, [x20, #96]
	stp	xzr, xzr, [x20, #168]
	str	xzr, [x20, #160]
	mov	x0, x19
	bl	_amdgpu_get_platform_caps
	cbnz	w0, LBB0_22
; %bb.2:
	mov	x0, x19
	bl	_amdgpu_parse_extended_power_table
	cbnz	w0, LBB0_22
; %bb.3:
	mov	x0, x19
	bl	_si_parse_power_table
	cbnz	w0, LBB0_22
; %bb.4:
	ldr	w2, [x21]
	mov	w21, #4
	mov	w0, #4
	mov	w1, #4
	bl	_kcalloc
	str	x0, [x19, #120]
	cbz	x0, LBB0_20
; %bb.5:
	str	w21, [x19, #112]
Lloh8:
	adrp	x8, lCPI0_0@PAGE
Lloh9:
	ldr	q0, [x8, lCPI0_0@PAGEOFF]
Lloh10:
	adrp	x8, lCPI0_1@PAGE
Lloh11:
	ldr	q1, [x8, lCPI0_1@PAGEOFF]
	stp	q0, q1, [x0]
	ldr	x8, [x19, #16]
	cbnz	x8, LBB0_7
; %bb.6:
Lloh12:
	adrp	x8, _R600_VOLTAGERESPONSETIME_DFLT@GOTPAGE
Lloh13:
	ldr	x8, [x8, _R600_VOLTAGERESPONSETIME_DFLT@GOTPAGEOFF]
Lloh14:
	ldr	x8, [x8]
	str	x8, [x19, #16]
LBB0_7:
	ldr	x8, [x19, #24]
	cbnz	x8, LBB0_9
; %bb.8:
Lloh15:
	adrp	x8, _R600_BACKBIASRESPONSETIME_DFLT@GOTPAGE
Lloh16:
	ldr	x8, [x8, _R600_BACKBIASRESPONSETIME_DFLT@GOTPAGEOFF]
Lloh17:
	ldr	x8, [x8]
	str	x8, [x19, #24]
LBB0_9:
Lloh18:
	adrp	x8, _COMPUTE_ENGINE_PLL_PARAM@GOTPAGE
Lloh19:
	ldr	x8, [x8, _COMPUTE_ENGINE_PLL_PARAM@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	add	x4, sp, #8
	mov	x0, x19
	mov	w2, #0
	mov	w3, #0
	bl	_amdgpu_atombios_get_clock_dividers
Lloh21:
	adrp	x8, _R600_REFERENCEDIVIDER_DFLT@GOTPAGE
Lloh22:
	ldr	x8, [x8, _R600_REFERENCEDIVIDER_DFLT@GOTPAGEOFF]
Lloh23:
	ldr	x8, [x8]
	ldr	x9, [sp, #8]
	cmp	w0, #0
	csinc	x8, x8, x9, eq
	str	x8, [x20, #152]
	str	wzr, [x20, #64]
	mov	w21, #40000
	str	w21, [x20, #104]
	mov	x0, x19
	bl	_si_is_special_1gb_platform
	mov	w8, #0
	cbnz	x0, LBB0_11
; %bb.10:
	ldr	w8, [x20, #104]
LBB0_11:
	stp	w8, w21, [x20, #108]
	str	w21, [x20, #68]
	str	w21, [x20, #56]
Lloh24:
	adrp	x21, _SET_VOLTAGE_TYPE_ASIC_VDDC@GOTPAGE
Lloh25:
	ldr	x21, [x21, _SET_VOLTAGE_TYPE_ASIC_VDDC@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh26:
	adrp	x22, _VOLTAGE_OBJ_GPIO_LUT@GOTPAGE
Lloh27:
	ldr	x22, [x22, _VOLTAGE_OBJ_GPIO_LUT@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	x0, x19
	bl	_amdgpu_atombios_is_voltage_gpio
	str	x0, [x20, #144]
	cbnz	x0, LBB0_14
; %bb.12:
	ldr	w1, [x21]
Lloh28:
	adrp	x8, _VOLTAGE_OBJ_SVID2@GOTPAGE
Lloh29:
	ldr	x8, [x8, _VOLTAGE_OBJ_SVID2@GOTPAGEOFF]
Lloh30:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_amdgpu_atombios_is_voltage_gpio
	str	x0, [x20, #40]
	cbz	x0, LBB0_14
; %bb.13:
	ldr	w1, [x21]
	add	x2, x20, #36
	add	x3, x20, #32
	mov	x0, x19
	bl	_amdgpu_atombios_get_svi2_info
LBB0_14:
Lloh31:
	adrp	x8, _SET_VOLTAGE_TYPE_ASIC_MVDDC@GOTPAGE
Lloh32:
	ldr	x8, [x8, _SET_VOLTAGE_TYPE_ASIC_MVDDC@GOTPAGEOFF]
Lloh33:
	ldr	w1, [x8]
	ldr	w2, [x22]
	mov	x0, x19
	bl	_amdgpu_atombios_is_voltage_gpio
	str	x0, [x20, #136]
Lloh34:
	adrp	x23, _SET_VOLTAGE_TYPE_ASIC_VDDCI@GOTPAGE
Lloh35:
	ldr	x23, [x23, _SET_VOLTAGE_TYPE_ASIC_VDDCI@GOTPAGEOFF]
	ldr	w1, [x23]
	ldr	w2, [x22]
	mov	x0, x19
	bl	_amdgpu_atombios_is_voltage_gpio
	str	x0, [x20, #88]
	cbnz	x0, LBB0_16
; %bb.15:
	ldr	w1, [x23]
Lloh36:
	adrp	x8, _VOLTAGE_OBJ_SVID2@GOTPAGE
Lloh37:
	ldr	x8, [x8, _VOLTAGE_OBJ_SVID2@GOTPAGEOFF]
Lloh38:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_amdgpu_atombios_is_voltage_gpio
	str	x0, [x20, #24]
LBB0_16:
	ldr	w1, [x21]
Lloh39:
	adrp	x8, _VOLTAGE_OBJ_PHASE_LUT@GOTPAGE
Lloh40:
	ldr	x8, [x8, _VOLTAGE_OBJ_PHASE_LUT@GOTPAGEOFF]
Lloh41:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_amdgpu_atombios_is_voltage_gpio
	str	x0, [x20, #16]
	mov	x0, x19
	bl	_rv770_get_engine_memory_ss
Lloh42:
	adrp	x8, _RV770_ASI_DFLT@GOTPAGE
Lloh43:
	ldr	x8, [x8, _RV770_ASI_DFLT@GOTPAGEOFF]
Lloh44:
	ldr	w8, [x8]
	str	w8, [x20, #132]
Lloh45:
	adrp	x8, _CYPRESS_HASI_DFLT@GOTPAGE
Lloh46:
	ldr	x8, [x8, _CYPRESS_HASI_DFLT@GOTPAGEOFF]
Lloh47:
	ldr	w8, [x8]
Lloh48:
	adrp	x9, _SISLANDS_VRC_DFLT@GOTPAGE
Lloh49:
	ldr	x9, [x9, _SISLANDS_VRC_DFLT@GOTPAGEOFF]
Lloh50:
	ldr	w9, [x9]
	stp	w9, w8, [x20, #124]
	ldr	x8, [x19, #8]
Lloh51:
	adrp	x9, _THERMAL_TYPE_NONE@GOTPAGE
Lloh52:
	ldr	x9, [x9, _THERMAL_TYPE_NONE@GOTPAGEOFF]
Lloh53:
	ldr	x9, [x9]
	cmp	x8, x9
	mov	w8, #1
	str	wzr, [x20, #4]
	cset	w9, ne
	stp	w8, w9, [x20, #116]
Lloh54:
	adrp	x8, lCPI0_2@PAGE
Lloh55:
	ldr	q0, [x8, lCPI0_2@PAGEOFF]
	stur	q0, [x20, #72]
Lloh56:
	adrp	x8, _SMC_RAM_END@GOTPAGE
Lloh57:
	ldr	x8, [x8, _SMC_RAM_END@GOTPAGEOFF]
Lloh58:
	ldr	w8, [x8]
	str	w8, [x20, #12]
Lloh59:
	adrp	x8, lCPI0_3@PAGE
Lloh60:
	ldr	d0, [x8, lCPI0_3@PAGEOFF]
	str	d0, [x19, #32]
	mov	w8, #200
	str	w8, [x19, #40]
	movi.2d	v0, #0000000000000000
	stp	q0, q0, [x19, #80]
	mov	x0, x19
	bl	_si_initialize_powertune_defaults
	mov	x8, x19
	ldr	x9, [x8, #64]!
	cbz	x9, LBB0_18
; %bb.17:
	ldr	x9, [x19, #72]
	cbnz	x9, LBB0_19
LBB0_18:
	ldr	q0, [x19, #48]
	str	q0, [x8]
LBB0_19:
	mov	w0, #0
	mov	w8, #1
	str	w8, [x20, #8]
	b	LBB0_22
LBB0_20:
	mov	x0, x19
	bl	_amdgpu_free_extended_power_table
LBB0_21:
Lloh61:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh62:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
Lloh63:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_22:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdr	Lloh10, Lloh11
	.loh AdrpAdrp	Lloh8, Lloh10
	.loh AdrpLdr	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdr	Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpAdrp	Lloh54, Lloh56
	.loh AdrpLdr	Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.cfi_endproc
                                        ; -- End function
	.comm	_GFP_KERNEL,4,2                 ; @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ; @ENOMEM
	.comm	_CAIL_PCIE_LINK_SPEED_SUPPORT_MASK,4,2 ; @CAIL_PCIE_LINK_SPEED_SUPPORT_MASK
	.comm	_AMDGPU_PCIE_GEN_INVALID,4,2    ; @AMDGPU_PCIE_GEN_INVALID
	.comm	_R600_VOLTAGERESPONSETIME_DFLT,8,3 ; @R600_VOLTAGERESPONSETIME_DFLT
	.comm	_R600_BACKBIASRESPONSETIME_DFLT,8,3 ; @R600_BACKBIASRESPONSETIME_DFLT
	.comm	_COMPUTE_ENGINE_PLL_PARAM,4,2   ; @COMPUTE_ENGINE_PLL_PARAM
	.comm	_R600_REFERENCEDIVIDER_DFLT,8,3 ; @R600_REFERENCEDIVIDER_DFLT
	.comm	_SET_VOLTAGE_TYPE_ASIC_VDDC,4,2 ; @SET_VOLTAGE_TYPE_ASIC_VDDC
	.comm	_VOLTAGE_OBJ_GPIO_LUT,4,2       ; @VOLTAGE_OBJ_GPIO_LUT
	.comm	_VOLTAGE_OBJ_SVID2,4,2          ; @VOLTAGE_OBJ_SVID2
	.comm	_SET_VOLTAGE_TYPE_ASIC_MVDDC,4,2 ; @SET_VOLTAGE_TYPE_ASIC_MVDDC
	.comm	_SET_VOLTAGE_TYPE_ASIC_VDDCI,4,2 ; @SET_VOLTAGE_TYPE_ASIC_VDDCI
	.comm	_VOLTAGE_OBJ_PHASE_LUT,4,2      ; @VOLTAGE_OBJ_PHASE_LUT
	.comm	_RV770_ASI_DFLT,4,2             ; @RV770_ASI_DFLT
	.comm	_CYPRESS_HASI_DFLT,4,2          ; @CYPRESS_HASI_DFLT
	.comm	_SISLANDS_VRC_DFLT,4,2          ; @SISLANDS_VRC_DFLT
	.comm	_THERMAL_TYPE_NONE,8,3          ; @THERMAL_TYPE_NONE
	.comm	_SMC_RAM_END,4,2                ; @SMC_RAM_END
	.no_dead_strip	_si_dpm_init
.subsections_via_symbols
