	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4                               ## -- Begin function cik_cp_compute_resume
LCPI0_0:
	.space	16
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	4, 0x90
_cik_cp_compute_resume:                 ## @cik_cp_compute_resume
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$88, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	callq	_cik_cp_compute_start
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	LBB0_26
## %bb.1:
	movq	_CP_CPF_DEBUG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	orl	$8388608, %eax                  ## imm = 0x800000
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	leaq	16(%r15), %rdi
	movq	%rdi, -56(%rbp)                 ## 8-byte Spill
	callq	_mutex_lock
	movl	32(%r15), %eax
	imull	28(%r15), %eax
	testl	%eax, %eax
	jle	LBB0_4
## %bb.2:
	xorl	%r14d, %r14d
	xorl	%edx, %edx
	movq	%r15, -88(%rbp)                 ## 8-byte Spill
	.p2align	4, 0x90
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	cmpl	$4, %edx
	movl	$2, %esi
	sbbl	$0, %esi
	movl	%edx, %r13d
	subl	$4, %r13d
	cmovael	%r13d, %edx
	movq	%r15, %rdi
	xorl	%ecx, %ecx
	xorl	%r8d, %r8d
	callq	_cik_srbm_select
	movq	_MEC_HPD_SIZE@GOTPCREL(%rip), %r15
	movl	(%r15), %ebx
	imull	%r14d, %ebx
	movq	-88(%rbp), %rax                 ## 8-byte Reload
	addl	36(%rax), %ebx
	movq	_CP_HPD_EOP_BASE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	sarl	$8, %esi
	callq	_WREG32
	movq	_CP_HPD_EOP_BASE_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	%ebx, %edi
	callq	_upper_32_bits
	sarl	$8, %eax
	movl	%r12d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_CP_HPD_EOP_VMID@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CP_HPD_EOP_CONTROL@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_RREG32
	movq	_EOP_SIZE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	(%r15), %eax
	movq	-88(%rbp), %r15                 ## 8-byte Reload
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	callq	_order_base_2
	orl	%eax, %ebx
	movl	(%r12), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movl	32(%r15), %eax
	imull	28(%r15), %eax
	addl	$2, %r14d
	leal	5(%r13), %edx
	cmpl	%eax, %edx
	jl	LBB0_3
LBB0_4:
	movq	%r15, %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	xorl	%r8d, %r8d
	callq	_cik_srbm_select
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_mutex_unlock
	movb	$1, %r13b
	movq	_DOORBELL_EN@GOTPCREL(%rip), %r14
	jmp	LBB0_5
	.p2align	4, 0x90
LBB0_25:                                ##   in Loop: Header=BB0_5 Depth=1
	xorl	%r12d, %r12d
	testb	$1, -44(%rbp)                   ## 1-byte Folded Reload
	movl	$0, %r13d
	movq	_DOORBELL_EN@GOTPCREL(%rip), %r14
	je	LBB0_26
LBB0_5:                                 ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_20 Depth 2
	movq	_CAYMAN_RING_TYPE_CP2_INDEX@GOTPCREL(%rip), %rcx
	testb	$1, %r13b
	je	LBB0_7
## %bb.6:                               ##   in Loop: Header=BB0_5 Depth=1
	movq	_CAYMAN_RING_TYPE_CP1_INDEX@GOTPCREL(%rip), %rcx
LBB0_7:                                 ##   in Loop: Header=BB0_5 Depth=1
	movq	8(%r15), %rax
	movslq	(%rcx), %rcx
	movq	%rcx, -80(%rbp)                 ## 8-byte Spill
	leaq	(%rcx,%rcx,4), %rbx
	movq	24(%rax,%rbx,8), %rdi
	testq	%rdi, %rdi
	jne	LBB0_10
## %bb.8:                               ##   in Loop: Header=BB0_5 Depth=1
	leaq	(%rax,%rbx,8), %rax
	addq	$24, %rax
	movq	_PAGE_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_RADEON_GEM_DOMAIN_GTT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r8d
	movq	%rax, 16(%rsp)
	xorps	%xmm0, %xmm0
	movups	%xmm0, (%rsp)
	movq	%r15, %rdi
	movl	$88, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	_radeon_bo_create
	testl	%eax, %eax
	jne	LBB0_27
## %bb.9:                               ##   in Loop: Header=BB0_5 Depth=1
	movq	8(%r15), %rax
	movq	24(%rax,%rbx,8), %rdi
LBB0_10:                                ##   in Loop: Header=BB0_5 Depth=1
	movq	%rbx, -72(%rbp)                 ## 8-byte Spill
	xorl	%esi, %esi
	callq	_radeon_bo_reserve
	movl	%eax, %r12d
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	callq	_unlikely
	testq	%rax, %rax
	jne	LBB0_11
## %bb.12:                              ##   in Loop: Header=BB0_5 Depth=1
	movl	%r13d, -44(%rbp)                ## 4-byte Spill
	movq	8(%r15), %rax
	movq	-72(%rbp), %r13                 ## 8-byte Reload
	movq	24(%rax,%r13,8), %rdi
	movq	_RADEON_GEM_DOMAIN_GTT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-60(%rbp), %rdx
	callq	_radeon_bo_pin
	testl	%eax, %eax
	jne	LBB0_13
## %bb.15:                              ##   in Loop: Header=BB0_5 Depth=1
	movq	8(%r15), %rax
	movq	24(%rax,%r13,8), %rdi
	leaq	-96(%rbp), %rsi
	callq	_radeon_bo_kmap
	testl	%eax, %eax
	jne	LBB0_16
## %bb.17:                              ##   in Loop: Header=BB0_5 Depth=1
	movq	-96(%rbp), %rdi
	xorl	%esi, %esi
	movl	$88, %edx
	callq	_memset
	movq	%r14, %r12
	movq	-96(%rbp), %r14
	movl	$-1070528512, (%r14)            ## imm = 0xC0310800
	movq	8(%r14), %rax
	movq	$-1, (%rax)
	movq	16(%r14), %rax
	movq	$-1, (%rax)
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_mutex_lock
	movq	8(%r15), %rax
	movl	(%rax,%r13,8), %esi
	movl	4(%rax,%r13,8), %edx
	movl	36(%rax,%r13,8), %ecx
	movq	%r15, %rdi
	xorl	%r8d, %r8d
	callq	_cik_srbm_select
	movq	_CP_PQ_WPTR_POLL_CNTL@GOTPCREL(%rip), %r13
	movq	_CP_HQD_PQ_DOORBELL_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%r13), %edi
	callq	_RREG32
	movq	_WPTR_POLL_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r13), %edi
	callq	_WREG32
	movl	(%rbx), %edi
	callq	_RREG32
	orl	(%r12), %eax
	movl	%eax, 24(%r14)
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	$0, 28(%r14)
	movl	$0, 36(%r14)
	movq	_CP_HQD_ACTIVE@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_RREG32
	testb	$1, %al
	movl	-44(%rbp), %r13d                ## 4-byte Reload
	je	LBB0_23
## %bb.18:                              ##   in Loop: Header=BB0_5 Depth=1
	movq	_CP_HQD_DEQUEUE_REQUEST@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_WREG32
	cmpl	$0, (%r15)
	jle	LBB0_22
## %bb.19:                              ##   in Loop: Header=BB0_5 Depth=1
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_20:                                ##   Parent Loop BB0_5 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movl	(%r12), %edi
	callq	_RREG32
	testb	$1, %al
	je	LBB0_22
## %bb.21:                              ##   in Loop: Header=BB0_20 Depth=2
	movl	$1, %edi
	callq	_udelay
	incl	%ebx
	cmpl	(%r15), %ebx
	jl	LBB0_20
LBB0_22:                                ##   in Loop: Header=BB0_5 Depth=1
	movq	_CP_HQD_DEQUEUE_REQUEST@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	28(%r14), %esi
	callq	_WREG32
	movq	_CP_HQD_PQ_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	32(%r14), %esi
	callq	_WREG32
	movq	_CP_HQD_PQ_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	36(%r14), %esi
	callq	_WREG32
LBB0_23:                                ##   in Loop: Header=BB0_5 Depth=1
	movl	-60(%rbp), %edi
	movl	%edi, %eax
	andl	$-4, %eax
	movl	%eax, 40(%r14)
	callq	_upper_32_bits
	movl	%eax, 44(%r14)
	movq	_CP_MQD_BASE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	40(%r14), %esi
	callq	_WREG32
	movq	_CP_MQD_BASE_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	44(%r14), %esi
	callq	_WREG32
	movq	_CP_MQD_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_MQD_VMID_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	%esi, 48(%r14)
	movl	(%rbx), %edi
	callq	_WREG32
	movq	8(%r15), %rax
	movq	-80(%rbp), %rcx                 ## 8-byte Reload
	shlq	$3, %rcx
	leaq	(%rcx,%rcx,4), %r12
	movl	8(%rax,%r12), %edi
	sarl	$8, %edi
	movl	%edi, 52(%r14)
	callq	_upper_32_bits
	movl	%eax, 56(%r14)
	movq	_CP_HQD_PQ_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	52(%r14), %esi
	callq	_WREG32
	movq	_CP_HQD_PQ_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	56(%r14), %esi
	callq	_WREG32
	movq	_CP_HQD_PQ_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_RPTR_BLOCK_SIZE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	_QUEUE_SIZE_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movl	%ecx, 60(%r14)
	movq	8(%r15), %rax
	movl	12(%rax,%r12), %eax
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	callq	_order_base_2
	orl	%eax, 60(%r14)
	movq	_RADEON_GPU_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	callq	_order_base_2
	shll	$8, %eax
	orl	60(%r14), %eax
	movq	_ROQ_PQ_IB_FLIP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_UNORD_DISPATCH@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movq	_PQ_VOLATILE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_PRIV_STATE@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_KMD_QUEUE@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	%esi, 60(%r14)
	movl	(%rbx), %edi
	callq	_WREG32
	testb	$1, %r13b
	movq	_CIK_WB_CP2_WPTR_OFFSET@GOTPCREL(%rip), %rax
	cmovneq	_CIK_WB_CP1_WPTR_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_WB_CP2_RPTR_OFFSET@GOTPCREL(%rip), %r13
	cmovneq	_RADEON_WB_CP1_RPTR_OFFSET@GOTPCREL(%rip), %r13
	addl	20(%r15), %edi
	movl	%edi, %eax
	andl	$-4, %eax
	movl	%eax, 64(%r14)
	callq	_upper_32_bits
	movzwl	%ax, %eax
	movl	%eax, 68(%r14)
	movq	_CP_HQD_PQ_WPTR_POLL_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	64(%r14), %esi
	callq	_WREG32
	movq	_CP_HQD_PQ_WPTR_POLL_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	68(%r14), %esi
	callq	_WREG32
	movl	(%r13), %edi
	addl	20(%r15), %edi
	movl	%edi, %eax
	andl	$-4, %eax
	movl	%eax, 72(%r14)
	callq	_upper_32_bits
	movzwl	%ax, %eax
	movl	%eax, 76(%r14)
	movq	_CP_HQD_PQ_RPTR_REPORT_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	72(%r14), %esi
	callq	_WREG32
	movq	_CP_HQD_PQ_RPTR_REPORT_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	76(%r14), %esi
	callq	_WREG32
	movq	_CP_HQD_PQ_DOORBELL_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_DOORBELL_OFFSET_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movl	%ecx, 24(%r14)
	movq	8(%r15), %rax
	movl	32(%rax,%r12), %edi
	callq	_DOORBELL_OFFSET
	orl	24(%r14), %eax
	movq	_DOORBELL_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_DOORBELL_HIT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_DOORBELL_SOURCE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	%esi, 24(%r14)
	movl	(%rbx), %edi
	callq	_WREG32
	movq	8(%r15), %rax
	movl	$0, 16(%rax,%r12)
	movl	$0, 36(%r14)
	movq	_CP_HQD_PQ_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CP_HQD_PQ_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, 32(%r14)
	movl	$0, 80(%r14)
	movq	_CP_HQD_VMID@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movl	$1, 84(%r14)
	movq	_CP_HQD_ACTIVE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_WREG32
	movq	%r15, %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	xorl	%r8d, %r8d
	callq	_cik_srbm_select
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_mutex_unlock
	movq	8(%r15), %rax
	movq	24(%rax,%r12), %rdi
	callq	_radeon_bo_kunmap
	movq	8(%r15), %rax
	movq	24(%rax,%r12), %rdi
	callq	_radeon_bo_unreserve
	movq	8(%r15), %rax
	leaq	(%rax,%r12), %rdx
	movl	$1, 20(%rax,%r12)
	movq	%r15, %rdi
	movq	-80(%rbp), %rsi                 ## 8-byte Reload
                                        ## kill: def $esi killed $esi killed $rsi
	callq	_radeon_ring_test
	testl	%eax, %eax
	je	LBB0_25
## %bb.24:                              ##   in Loop: Header=BB0_5 Depth=1
	movq	8(%r15), %rax
	movq	-72(%rbp), %rcx                 ## 8-byte Reload
	movl	$0, 20(%rax,%rcx,8)
	jmp	LBB0_25
LBB0_13:
	movl	%eax, %r12d
	movl	24(%r15), %edi
	leaq	L_.str.1(%rip), %rsi
	jmp	LBB0_14
LBB0_16:
	movl	%eax, %r12d
	movl	24(%r15), %edi
	leaq	L_.str.2(%rip), %rsi
LBB0_14:
	movl	%r12d, %edx
	callq	_dev_warn
LBB0_11:
	movq	%r15, %rdi
	callq	_cik_cp_compute_fini
LBB0_26:
	movl	%r12d, %eax
	addq	$88, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_27:
	movl	%eax, %r12d
	movl	24(%r15), %edi
	leaq	L_.str(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_warn
	jmp	LBB0_26
	.cfi_endproc
                                        ## -- End function
	.comm	_CP_CPF_DEBUG,4,2               ## @CP_CPF_DEBUG
	.comm	_MEC_HPD_SIZE,4,2               ## @MEC_HPD_SIZE
	.comm	_CP_HPD_EOP_BASE_ADDR,4,2       ## @CP_HPD_EOP_BASE_ADDR
	.comm	_CP_HPD_EOP_BASE_ADDR_HI,4,2    ## @CP_HPD_EOP_BASE_ADDR_HI
	.comm	_CP_HPD_EOP_VMID,4,2            ## @CP_HPD_EOP_VMID
	.comm	_CP_HPD_EOP_CONTROL,4,2         ## @CP_HPD_EOP_CONTROL
	.comm	_EOP_SIZE_MASK,4,2              ## @EOP_SIZE_MASK
	.comm	_CAYMAN_RING_TYPE_CP1_INDEX,4,2 ## @CAYMAN_RING_TYPE_CP1_INDEX
	.comm	_CAYMAN_RING_TYPE_CP2_INDEX,4,2 ## @CAYMAN_RING_TYPE_CP2_INDEX
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
	.comm	_RADEON_GEM_DOMAIN_GTT,4,2      ## @RADEON_GEM_DOMAIN_GTT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"(%d) create MQD bo failed\n"

L_.str.1:                               ## @.str.1
	.asciz	"(%d) pin MQD bo failed\n"

L_.str.2:                               ## @.str.2
	.asciz	"(%d) map MQD bo failed\n"

	.comm	_CP_PQ_WPTR_POLL_CNTL,4,2       ## @CP_PQ_WPTR_POLL_CNTL
	.comm	_WPTR_POLL_EN,4,2               ## @WPTR_POLL_EN
	.comm	_CP_HQD_PQ_DOORBELL_CONTROL,4,2 ## @CP_HQD_PQ_DOORBELL_CONTROL
	.comm	_DOORBELL_EN,4,2                ## @DOORBELL_EN
	.comm	_CP_HQD_ACTIVE,4,2              ## @CP_HQD_ACTIVE
	.comm	_CP_HQD_DEQUEUE_REQUEST,4,2     ## @CP_HQD_DEQUEUE_REQUEST
	.comm	_CP_HQD_PQ_RPTR,4,2             ## @CP_HQD_PQ_RPTR
	.comm	_CP_HQD_PQ_WPTR,4,2             ## @CP_HQD_PQ_WPTR
	.comm	_CP_MQD_BASE_ADDR,4,2           ## @CP_MQD_BASE_ADDR
	.comm	_CP_MQD_BASE_ADDR_HI,4,2        ## @CP_MQD_BASE_ADDR_HI
	.comm	_CP_MQD_CONTROL,4,2             ## @CP_MQD_CONTROL
	.comm	_MQD_VMID_MASK,4,2              ## @MQD_VMID_MASK
	.comm	_CP_HQD_PQ_BASE,4,2             ## @CP_HQD_PQ_BASE
	.comm	_CP_HQD_PQ_BASE_HI,4,2          ## @CP_HQD_PQ_BASE_HI
	.comm	_CP_HQD_PQ_CONTROL,4,2          ## @CP_HQD_PQ_CONTROL
	.comm	_QUEUE_SIZE_MASK,4,2            ## @QUEUE_SIZE_MASK
	.comm	_RPTR_BLOCK_SIZE_MASK,4,2       ## @RPTR_BLOCK_SIZE_MASK
	.comm	_RADEON_GPU_PAGE_SIZE,4,2       ## @RADEON_GPU_PAGE_SIZE
	.comm	_UNORD_DISPATCH,4,2             ## @UNORD_DISPATCH
	.comm	_ROQ_PQ_IB_FLIP,4,2             ## @ROQ_PQ_IB_FLIP
	.comm	_PQ_VOLATILE,4,2                ## @PQ_VOLATILE
	.comm	_PRIV_STATE,4,2                 ## @PRIV_STATE
	.comm	_KMD_QUEUE,4,2                  ## @KMD_QUEUE
	.comm	_CIK_WB_CP1_WPTR_OFFSET,4,2     ## @CIK_WB_CP1_WPTR_OFFSET
	.comm	_CIK_WB_CP2_WPTR_OFFSET,4,2     ## @CIK_WB_CP2_WPTR_OFFSET
	.comm	_CP_HQD_PQ_WPTR_POLL_ADDR,4,2   ## @CP_HQD_PQ_WPTR_POLL_ADDR
	.comm	_CP_HQD_PQ_WPTR_POLL_ADDR_HI,4,2 ## @CP_HQD_PQ_WPTR_POLL_ADDR_HI
	.comm	_RADEON_WB_CP1_RPTR_OFFSET,4,2  ## @RADEON_WB_CP1_RPTR_OFFSET
	.comm	_RADEON_WB_CP2_RPTR_OFFSET,4,2  ## @RADEON_WB_CP2_RPTR_OFFSET
	.comm	_CP_HQD_PQ_RPTR_REPORT_ADDR,4,2 ## @CP_HQD_PQ_RPTR_REPORT_ADDR
	.comm	_CP_HQD_PQ_RPTR_REPORT_ADDR_HI,4,2 ## @CP_HQD_PQ_RPTR_REPORT_ADDR_HI
	.comm	_DOORBELL_OFFSET_MASK,4,2       ## @DOORBELL_OFFSET_MASK
	.comm	_DOORBELL_SOURCE,4,2            ## @DOORBELL_SOURCE
	.comm	_DOORBELL_HIT,4,2               ## @DOORBELL_HIT
	.comm	_CP_HQD_VMID,4,2                ## @CP_HQD_VMID
	.comm	_BUF_SWAP_32BIT,4,2             ## @BUF_SWAP_32BIT
	.no_dead_strip	_cik_cp_compute_resume
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cik_cp_compute_resume
_cik_cp_compute_resume:                 ; @cik_cp_compute_resume
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #128
	.cfi_def_cfa_offset 128
	stp	x28, x27, [sp, #32]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #48]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #64]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #80]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #96]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #112]            ; 16-byte Folded Spill
	add	x29, sp, #112
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	bl	_cik_cp_compute_start
	mov	x22, x0
	cbnz	w0, LBB0_25
; %bb.1:
Lloh0:
	adrp	x20, _CP_CPF_DEBUG@GOTPAGE
Lloh1:
	ldr	x20, [x20, _CP_CPF_DEBUG@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
	orr	w1, w0, #0x800000
	ldr	w0, [x20]
	bl	_WREG32
	add	x0, x19, #16
	str	x0, [sp, #8]                    ; 8-byte Folded Spill
	bl	_mutex_lock
	ldp	w8, w9, [x19, #28]
	mul	w8, w9, w8
	cmp	w8, #1
	b.lt	LBB0_4
; %bb.2:
	mov	w23, #0
	mov	w24, #0
Lloh2:
	adrp	x26, _MEC_HPD_SIZE@GOTPAGE
Lloh3:
	ldr	x26, [x26, _MEC_HPD_SIZE@GOTPAGEOFF]
Lloh4:
	adrp	x28, _CP_HPD_EOP_BASE_ADDR_HI@GOTPAGE
Lloh5:
	ldr	x28, [x28, _CP_HPD_EOP_BASE_ADDR_HI@GOTPAGEOFF]
Lloh6:
	adrp	x20, _CP_HPD_EOP_VMID@GOTPAGE
Lloh7:
	ldr	x20, [x20, _CP_HPD_EOP_VMID@GOTPAGEOFF]
Lloh8:
	adrp	x25, _CP_HPD_EOP_CONTROL@GOTPAGE
Lloh9:
	ldr	x25, [x25, _CP_HPD_EOP_CONTROL@GOTPAGEOFF]
Lloh10:
	adrp	x27, _EOP_SIZE_MASK@GOTPAGE
Lloh11:
	ldr	x27, [x27, _EOP_SIZE_MASK@GOTPAGEOFF]
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	subs	w8, w24, #4
	mov	w9, #1
	cinc	w1, w9, hs
	csel	w2, w24, w8, lo
	mov	x0, x19
	mov	w3, #0
	mov	w4, #0
	bl	_cik_srbm_select
	ldr	w8, [x19, #36]
	ldr	w9, [x26]
	madd	w21, w23, w9, w8
Lloh12:
	adrp	x8, _CP_HPD_EOP_BASE_ADDR@GOTPAGE
Lloh13:
	ldr	x8, [x8, _CP_HPD_EOP_BASE_ADDR@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	asr	w1, w21, #8
	bl	_WREG32
	ldr	w22, [x28]
	mov	x0, x21
	bl	_upper_32_bits
	asr	w1, w0, #8
	mov	x0, x22
	bl	_WREG32
	ldr	w0, [x20]
	mov	w1, #0
	bl	_WREG32
	ldr	w0, [x25]
	bl	_RREG32
	ldr	w8, [x27]
	bic	w21, w0, w8
	ldr	w8, [x26]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #3
	bl	_order_base_2
	orr	w1, w0, w21
	ldr	w0, [x25]
	bl	_WREG32
	ldp	w8, w9, [x19, #28]
	mul	w8, w9, w8
	add	w23, w23, #2
	add	w24, w24, #1
	cmp	w24, w8
	b.lt	LBB0_3
LBB0_4:
	mov	x0, x19
	mov	w1, #0
	mov	w2, #0
	mov	w3, #0
	mov	w4, #0
	bl	_cik_srbm_select
	ldr	x27, [sp, #8]                   ; 8-byte Folded Reload
	mov	x0, x27
	bl	_mutex_unlock
	mov	w20, #40
Lloh15:
	adrp	x26, _CP_HQD_PQ_DOORBELL_CONTROL@GOTPAGE
Lloh16:
	ldr	x26, [x26, _CP_HQD_PQ_DOORBELL_CONTROL@GOTPAGEOFF]
Lloh17:
	adrp	x23, _DOORBELL_EN@GOTPAGE
Lloh18:
	ldr	x23, [x23, _DOORBELL_EN@GOTPAGEOFF]
Lloh19:
	adrp	x28, _CP_HQD_ACTIVE@GOTPAGE
Lloh20:
	ldr	x28, [x28, _CP_HQD_ACTIVE@GOTPAGEOFF]
	mov	w8, #1
	b	LBB0_6
LBB0_5:                                 ;   in Loop: Header=BB0_6 Depth=1
	mov	w8, #0
Lloh21:
	adrp	x23, _DOORBELL_EN@GOTPAGE
Lloh22:
	ldr	x23, [x23, _DOORBELL_EN@GOTPAGEOFF]
Lloh23:
	adrp	x26, _CP_HQD_PQ_DOORBELL_CONTROL@GOTPAGE
Lloh24:
	ldr	x26, [x26, _CP_HQD_PQ_DOORBELL_CONTROL@GOTPAGEOFF]
	tbz	w25, #0, LBB0_21
LBB0_6:                                 ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_15 Depth 2
	mov	x25, x8
	ldr	x8, [x19, #8]
	tst	w25, #0x1
Lloh25:
	adrp	x9, _CAYMAN_RING_TYPE_CP1_INDEX@GOTPAGE
Lloh26:
	ldr	x9, [x9, _CAYMAN_RING_TYPE_CP1_INDEX@GOTPAGEOFF]
Lloh27:
	adrp	x10, _CAYMAN_RING_TYPE_CP2_INDEX@GOTPAGE
Lloh28:
	ldr	x10, [x10, _CAYMAN_RING_TYPE_CP2_INDEX@GOTPAGEOFF]
	csel	x9, x9, x10, ne
	ldrsw	x21, [x9]
	madd	x8, x21, x20, x8
	ldr	x0, [x8, #24]!
	cbnz	x0, LBB0_9
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=1
Lloh29:
	adrp	x9, _PAGE_SIZE@GOTPAGE
Lloh30:
	ldr	x9, [x9, _PAGE_SIZE@GOTPAGEOFF]
Lloh31:
	ldr	w2, [x9]
Lloh32:
	adrp	x9, _RADEON_GEM_DOMAIN_GTT@GOTPAGE
Lloh33:
	ldr	x9, [x9, _RADEON_GEM_DOMAIN_GTT@GOTPAGEOFF]
Lloh34:
	ldr	w4, [x9]
	str	x8, [sp]
	mov	x0, x19
	mov	w1, #88
	mov	w3, #1
	mov	w5, #0
	mov	x6, #0
	mov	x7, #0
	bl	_radeon_bo_create
	cbnz	w0, LBB0_26
; %bb.8:                                ;   in Loop: Header=BB0_6 Depth=1
	ldr	x8, [x19, #8]
	madd	x8, x21, x20, x8
	ldr	x0, [x8, #24]
LBB0_9:                                 ;   in Loop: Header=BB0_6 Depth=1
	mov	w1, #0
	bl	_radeon_bo_reserve
	mov	x22, x0
	cmp	w0, #0
	cset	w0, ne
	bl	_unlikely
	cbnz	x0, LBB0_24
; %bb.10:                               ;   in Loop: Header=BB0_6 Depth=1
	ldr	x8, [x19, #8]
	madd	x8, x21, x20, x8
	ldr	x0, [x8, #24]
Lloh35:
	adrp	x8, _RADEON_GEM_DOMAIN_GTT@GOTPAGE
Lloh36:
	ldr	x8, [x8, _RADEON_GEM_DOMAIN_GTT@GOTPAGEOFF]
Lloh37:
	ldr	w1, [x8]
	add	x2, sp, #28
	bl	_radeon_bo_pin
	cbnz	w0, LBB0_20
; %bb.11:                               ;   in Loop: Header=BB0_6 Depth=1
	ldr	x8, [x19, #8]
	madd	x8, x21, x20, x8
	ldr	x0, [x8, #24]
	add	x1, sp, #16
	bl	_radeon_bo_kmap
	cbnz	w0, LBB0_22
; %bb.12:                               ;   in Loop: Header=BB0_6 Depth=1
	ldr	x0, [sp, #16]
	mov	w1, #0
	mov	w2, #88
	bl	_memset
	ldr	x22, [sp, #16]
	mov	w8, #2048
	movk	w8, #49201, lsl #16
	str	w8, [x22]
	ldp	x8, x9, [x22, #8]
	movi.2d	v0, #0xffffffffffffffff
	str	d0, [x8]
	str	d0, [x9]
	mov	x0, x27
	bl	_mutex_lock
	ldr	x8, [x19, #8]
	madd	x8, x21, x20, x8
	ldp	w1, w2, [x8]
	ldr	w3, [x8, #36]
	mov	x0, x19
	mov	w4, #0
	bl	_cik_srbm_select
Lloh38:
	adrp	x20, _CP_PQ_WPTR_POLL_CNTL@GOTPAGE
Lloh39:
	ldr	x20, [x20, _CP_PQ_WPTR_POLL_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh40:
	adrp	x8, _WPTR_POLL_EN@GOTPAGE
Lloh41:
	ldr	x8, [x8, _WPTR_POLL_EN@GOTPAGEOFF]
Lloh42:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w0, [x20]
	bl	_WREG32
	ldr	w0, [x26]
	bl	_RREG32
	ldr	w8, [x23]
	orr	w1, w8, w0
	str	w1, [x22, #24]
	ldr	w0, [x26]
	bl	_WREG32
	str	xzr, [x22, #32]
	str	wzr, [x22, #28]
	ldr	w0, [x28]
	bl	_RREG32
	tbz	w0, #0, LBB0_18
; %bb.13:                               ;   in Loop: Header=BB0_6 Depth=1
Lloh43:
	adrp	x8, _CP_HQD_DEQUEUE_REQUEST@GOTPAGE
Lloh44:
	ldr	x8, [x8, _CP_HQD_DEQUEUE_REQUEST@GOTPAGEOFF]
Lloh45:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_WREG32
	ldr	w8, [x19]
	cmp	w8, #1
	b.lt	LBB0_17
; %bb.14:                               ;   in Loop: Header=BB0_6 Depth=1
	mov	w20, #0
LBB0_15:                                ;   Parent Loop BB0_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ldr	w0, [x28]
	bl	_RREG32
	tbz	w0, #0, LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_15 Depth=2
	mov	w0, #1
	bl	_udelay
	add	w20, w20, #1
	ldr	w8, [x19]
	cmp	w20, w8
	b.lt	LBB0_15
LBB0_17:                                ;   in Loop: Header=BB0_6 Depth=1
Lloh46:
	adrp	x8, _CP_HQD_DEQUEUE_REQUEST@GOTPAGE
Lloh47:
	ldr	x8, [x8, _CP_HQD_DEQUEUE_REQUEST@GOTPAGEOFF]
Lloh48:
	ldr	w0, [x8]
	ldr	w1, [x22, #28]
	bl	_WREG32
Lloh49:
	adrp	x8, _CP_HQD_PQ_RPTR@GOTPAGE
Lloh50:
	ldr	x8, [x8, _CP_HQD_PQ_RPTR@GOTPAGEOFF]
Lloh51:
	ldr	w0, [x8]
	ldr	w1, [x22, #32]
	bl	_WREG32
Lloh52:
	adrp	x8, _CP_HQD_PQ_WPTR@GOTPAGE
Lloh53:
	ldr	x8, [x8, _CP_HQD_PQ_WPTR@GOTPAGEOFF]
Lloh54:
	ldr	w0, [x8]
	ldr	w1, [x22, #36]
	bl	_WREG32
	ldr	x27, [sp, #8]                   ; 8-byte Folded Reload
Lloh55:
	adrp	x23, _DOORBELL_EN@GOTPAGE
Lloh56:
	ldr	x23, [x23, _DOORBELL_EN@GOTPAGEOFF]
Lloh57:
	adrp	x26, _CP_HQD_PQ_DOORBELL_CONTROL@GOTPAGE
Lloh58:
	ldr	x26, [x26, _CP_HQD_PQ_DOORBELL_CONTROL@GOTPAGEOFF]
LBB0_18:                                ;   in Loop: Header=BB0_6 Depth=1
	ldr	w0, [sp, #28]
	and	w8, w0, #0xfffffffc
	str	w8, [x22, #40]
	bl	_upper_32_bits
	str	w0, [x22, #44]
Lloh59:
	adrp	x8, _CP_MQD_BASE_ADDR@GOTPAGE
Lloh60:
	ldr	x8, [x8, _CP_MQD_BASE_ADDR@GOTPAGEOFF]
Lloh61:
	ldr	w0, [x8]
	ldr	w1, [x22, #40]
	bl	_WREG32
Lloh62:
	adrp	x8, _CP_MQD_BASE_ADDR_HI@GOTPAGE
Lloh63:
	ldr	x8, [x8, _CP_MQD_BASE_ADDR_HI@GOTPAGEOFF]
Lloh64:
	ldr	w0, [x8]
	ldr	w1, [x22, #44]
	bl	_WREG32
Lloh65:
	adrp	x20, _CP_MQD_CONTROL@GOTPAGE
Lloh66:
	ldr	x20, [x20, _CP_MQD_CONTROL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh67:
	adrp	x8, _MQD_VMID_MASK@GOTPAGE
Lloh68:
	ldr	x8, [x8, _MQD_VMID_MASK@GOTPAGEOFF]
Lloh69:
	ldr	w8, [x8]
	bic	w1, w0, w8
	str	w1, [x22, #48]
	ldr	w0, [x20]
	bl	_WREG32
	ldr	x8, [x19, #8]
	add	x9, x21, x21, lsl #2
	lsl	x24, x9, #3
	add	x8, x8, x24
	ldr	w8, [x8, #8]
	asr	w0, w8, #8
	str	w0, [x22, #52]
	bl	_upper_32_bits
	str	w0, [x22, #56]
Lloh70:
	adrp	x8, _CP_HQD_PQ_BASE@GOTPAGE
Lloh71:
	ldr	x8, [x8, _CP_HQD_PQ_BASE@GOTPAGEOFF]
Lloh72:
	ldr	w0, [x8]
	ldr	w1, [x22, #52]
	bl	_WREG32
Lloh73:
	adrp	x8, _CP_HQD_PQ_BASE_HI@GOTPAGE
Lloh74:
	ldr	x8, [x8, _CP_HQD_PQ_BASE_HI@GOTPAGEOFF]
Lloh75:
	ldr	w0, [x8]
	ldr	w1, [x22, #56]
	bl	_WREG32
Lloh76:
	adrp	x20, _CP_HQD_PQ_CONTROL@GOTPAGE
Lloh77:
	ldr	x20, [x20, _CP_HQD_PQ_CONTROL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32
Lloh78:
	adrp	x8, _QUEUE_SIZE_MASK@GOTPAGE
Lloh79:
	ldr	x8, [x8, _QUEUE_SIZE_MASK@GOTPAGEOFF]
Lloh80:
	ldr	w8, [x8]
Lloh81:
	adrp	x9, _RPTR_BLOCK_SIZE_MASK@GOTPAGE
Lloh82:
	ldr	x9, [x9, _RPTR_BLOCK_SIZE_MASK@GOTPAGEOFF]
Lloh83:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
	str	w8, [x22, #60]
	ldr	x8, [x19, #8]
	add	x8, x8, x24
	ldr	w8, [x8, #12]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #3
	bl	_order_base_2
	ldr	w8, [x22, #60]
	orr	w8, w8, w0
	str	w8, [x22, #60]
Lloh84:
	adrp	x8, _RADEON_GPU_PAGE_SIZE@GOTPAGE
Lloh85:
	ldr	x8, [x8, _RADEON_GPU_PAGE_SIZE@GOTPAGEOFF]
Lloh86:
	ldr	w8, [x8]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #3
	bl	_order_base_2
	ldr	w8, [x22, #60]
	orr	w8, w8, w0, lsl #8
Lloh87:
	adrp	x9, _UNORD_DISPATCH@GOTPAGE
Lloh88:
	ldr	x9, [x9, _UNORD_DISPATCH@GOTPAGEOFF]
Lloh89:
	ldr	w9, [x9]
Lloh90:
	adrp	x10, _ROQ_PQ_IB_FLIP@GOTPAGE
Lloh91:
	ldr	x10, [x10, _ROQ_PQ_IB_FLIP@GOTPAGEOFF]
Lloh92:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh93:
	adrp	x10, _PQ_VOLATILE@GOTPAGE
Lloh94:
	ldr	x10, [x10, _PQ_VOLATILE@GOTPAGEOFF]
Lloh95:
	ldr	w10, [x10]
	orr	w9, w9, w10
	bic	w8, w8, w9
Lloh96:
	adrp	x9, _PRIV_STATE@GOTPAGE
Lloh97:
	ldr	x9, [x9, _PRIV_STATE@GOTPAGEOFF]
Lloh98:
	ldr	w9, [x9]
Lloh99:
	adrp	x10, _KMD_QUEUE@GOTPAGE
Lloh100:
	ldr	x10, [x10, _KMD_QUEUE@GOTPAGEOFF]
Lloh101:
	ldr	w10, [x10]
	orr	w8, w8, w9
	orr	w1, w8, w10
	str	w1, [x22, #60]
	ldr	w0, [x20]
	bl	_WREG32
	ldr	w8, [x19, #20]
	tst	w25, #0x1
Lloh102:
	adrp	x9, _CIK_WB_CP1_WPTR_OFFSET@GOTPAGE
Lloh103:
	ldr	x9, [x9, _CIK_WB_CP1_WPTR_OFFSET@GOTPAGEOFF]
Lloh104:
	adrp	x10, _CIK_WB_CP2_WPTR_OFFSET@GOTPAGE
Lloh105:
	ldr	x10, [x10, _CIK_WB_CP2_WPTR_OFFSET@GOTPAGEOFF]
	csel	x9, x9, x10, ne
	ldr	w9, [x9]
	add	w0, w9, w8
	and	w8, w0, #0xfffffffc
	str	w8, [x22, #64]
Lloh106:
	adrp	x8, _RADEON_WB_CP1_RPTR_OFFSET@GOTPAGE
Lloh107:
	ldr	x8, [x8, _RADEON_WB_CP1_RPTR_OFFSET@GOTPAGEOFF]
Lloh108:
	adrp	x9, _RADEON_WB_CP2_RPTR_OFFSET@GOTPAGE
Lloh109:
	ldr	x9, [x9, _RADEON_WB_CP2_RPTR_OFFSET@GOTPAGEOFF]
	csel	x20, x8, x9, ne
	bl	_upper_32_bits
	and	w8, w0, #0xffff
	str	w8, [x22, #68]
Lloh110:
	adrp	x8, _CP_HQD_PQ_WPTR_POLL_ADDR@GOTPAGE
Lloh111:
	ldr	x8, [x8, _CP_HQD_PQ_WPTR_POLL_ADDR@GOTPAGEOFF]
Lloh112:
	ldr	w0, [x8]
	ldr	w1, [x22, #64]
	bl	_WREG32
Lloh113:
	adrp	x8, _CP_HQD_PQ_WPTR_POLL_ADDR_HI@GOTPAGE
Lloh114:
	ldr	x8, [x8, _CP_HQD_PQ_WPTR_POLL_ADDR_HI@GOTPAGEOFF]
Lloh115:
	ldr	w0, [x8]
	ldr	w1, [x22, #68]
	bl	_WREG32
	ldr	w8, [x19, #20]
	ldr	w9, [x20]
	add	w0, w9, w8
	and	w8, w0, #0xfffffffc
	str	w8, [x22, #72]
	bl	_upper_32_bits
	and	w8, w0, #0xffff
	str	w8, [x22, #76]
Lloh116:
	adrp	x8, _CP_HQD_PQ_RPTR_REPORT_ADDR@GOTPAGE
Lloh117:
	ldr	x8, [x8, _CP_HQD_PQ_RPTR_REPORT_ADDR@GOTPAGEOFF]
Lloh118:
	ldr	w0, [x8]
	ldr	w1, [x22, #72]
	bl	_WREG32
Lloh119:
	adrp	x8, _CP_HQD_PQ_RPTR_REPORT_ADDR_HI@GOTPAGE
Lloh120:
	ldr	x8, [x8, _CP_HQD_PQ_RPTR_REPORT_ADDR_HI@GOTPAGEOFF]
Lloh121:
	ldr	w0, [x8]
	ldr	w1, [x22, #76]
	bl	_WREG32
	ldr	w0, [x26]
	bl	_RREG32
Lloh122:
	adrp	x8, _DOORBELL_OFFSET_MASK@GOTPAGE
Lloh123:
	ldr	x8, [x8, _DOORBELL_OFFSET_MASK@GOTPAGEOFF]
Lloh124:
	ldr	w8, [x8]
	bic	w8, w0, w8
	str	w8, [x22, #24]
	ldr	x8, [x19, #8]
	add	x8, x8, x24
	ldr	w0, [x8, #32]
	bl	_DOORBELL_OFFSET
	ldr	w8, [x22, #24]
	orr	w8, w8, w0
	ldr	w9, [x23]
	orr	w8, w9, w8
Lloh125:
	adrp	x9, _DOORBELL_SOURCE@GOTPAGE
Lloh126:
	ldr	x9, [x9, _DOORBELL_SOURCE@GOTPAGEOFF]
Lloh127:
	ldr	w9, [x9]
Lloh128:
	adrp	x10, _DOORBELL_HIT@GOTPAGE
Lloh129:
	ldr	x10, [x10, _DOORBELL_HIT@GOTPAGEOFF]
Lloh130:
	ldr	w10, [x10]
	orr	w9, w10, w9
	bic	w1, w8, w9
	str	w1, [x22, #24]
	ldr	w0, [x26]
	bl	_WREG32
	ldr	x8, [x19, #8]
	add	x8, x8, x24
	str	wzr, [x8, #16]
	str	wzr, [x22, #36]
Lloh131:
	adrp	x8, _CP_HQD_PQ_WPTR@GOTPAGE
Lloh132:
	ldr	x8, [x8, _CP_HQD_PQ_WPTR@GOTPAGEOFF]
Lloh133:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh134:
	adrp	x8, _CP_HQD_PQ_RPTR@GOTPAGE
Lloh135:
	ldr	x8, [x8, _CP_HQD_PQ_RPTR@GOTPAGEOFF]
Lloh136:
	ldr	w0, [x8]
	bl	_RREG32
	str	w0, [x22, #32]
	str	wzr, [x22, #80]
Lloh137:
	adrp	x8, _CP_HQD_VMID@GOTPAGE
Lloh138:
	ldr	x8, [x8, _CP_HQD_VMID@GOTPAGEOFF]
Lloh139:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	mov	w20, #1
	str	w20, [x22, #84]
	ldr	w0, [x28]
	mov	w1, #1
	bl	_WREG32
	mov	x0, x19
	mov	w1, #0
	mov	w2, #0
	mov	w3, #0
	mov	w4, #0
	bl	_cik_srbm_select
	mov	x0, x27
	bl	_mutex_unlock
	ldr	x8, [x19, #8]
	add	x8, x8, x24
	ldr	x0, [x8, #24]
	bl	_radeon_bo_kunmap
	ldr	x8, [x19, #8]
	add	x8, x8, x24
	ldr	x0, [x8, #24]
	bl	_radeon_bo_unreserve
	ldr	x8, [x19, #8]
	add	x2, x8, x24
	str	w20, [x2, #20]
	mov	x0, x19
	mov	x1, x21
	bl	_radeon_ring_test
	mov	w20, #40
	cbz	w0, LBB0_5
; %bb.19:                               ;   in Loop: Header=BB0_6 Depth=1
	ldr	x8, [x19, #8]
	mul	x9, x21, x20
	add	x8, x8, x9
	str	wzr, [x8, #20]
	b	LBB0_5
LBB0_20:
	mov	x22, x0
	ldr	w0, [x19, #24]
Lloh140:
	adrp	x1, l_.str.1@PAGE
Lloh141:
	add	x1, x1, l_.str.1@PAGEOFF
	b	LBB0_23
LBB0_21:
	mov	w22, #0
	b	LBB0_25
LBB0_22:
	mov	x22, x0
	ldr	w0, [x19, #24]
Lloh142:
	adrp	x1, l_.str.2@PAGE
Lloh143:
	add	x1, x1, l_.str.2@PAGEOFF
LBB0_23:
	mov	x2, x22
	bl	_dev_warn
LBB0_24:
	mov	x0, x19
	bl	_cik_cp_compute_fini
LBB0_25:
	mov	x0, x22
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	ret
LBB0_26:
	mov	x22, x0
	ldr	w0, [x19, #24]
Lloh144:
	adrp	x1, l_.str@PAGE
Lloh145:
	add	x1, x1, l_.str@PAGEOFF
	mov	x2, x22
	bl	_dev_warn
	b	LBB0_25
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh137, Lloh138, Lloh139
	.loh AdrpLdrGotLdr	Lloh134, Lloh135, Lloh136
	.loh AdrpLdrGotLdr	Lloh131, Lloh132, Lloh133
	.loh AdrpLdrGotLdr	Lloh128, Lloh129, Lloh130
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGot	Lloh108, Lloh109
	.loh AdrpLdrGot	Lloh106, Lloh107
	.loh AdrpLdrGot	Lloh104, Lloh105
	.loh AdrpLdrGot	Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGot	Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpAdd	Lloh140, Lloh141
	.loh AdrpAdd	Lloh142, Lloh143
	.loh AdrpAdd	Lloh144, Lloh145
	.cfi_endproc
                                        ; -- End function
	.comm	_CP_CPF_DEBUG,4,2               ; @CP_CPF_DEBUG
	.comm	_MEC_HPD_SIZE,4,2               ; @MEC_HPD_SIZE
	.comm	_CP_HPD_EOP_BASE_ADDR,4,2       ; @CP_HPD_EOP_BASE_ADDR
	.comm	_CP_HPD_EOP_BASE_ADDR_HI,4,2    ; @CP_HPD_EOP_BASE_ADDR_HI
	.comm	_CP_HPD_EOP_VMID,4,2            ; @CP_HPD_EOP_VMID
	.comm	_CP_HPD_EOP_CONTROL,4,2         ; @CP_HPD_EOP_CONTROL
	.comm	_EOP_SIZE_MASK,4,2              ; @EOP_SIZE_MASK
	.comm	_CAYMAN_RING_TYPE_CP1_INDEX,4,2 ; @CAYMAN_RING_TYPE_CP1_INDEX
	.comm	_CAYMAN_RING_TYPE_CP2_INDEX,4,2 ; @CAYMAN_RING_TYPE_CP2_INDEX
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
	.comm	_RADEON_GEM_DOMAIN_GTT,4,2      ; @RADEON_GEM_DOMAIN_GTT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"(%d) create MQD bo failed\n"

l_.str.1:                               ; @.str.1
	.asciz	"(%d) pin MQD bo failed\n"

l_.str.2:                               ; @.str.2
	.asciz	"(%d) map MQD bo failed\n"

	.comm	_CP_PQ_WPTR_POLL_CNTL,4,2       ; @CP_PQ_WPTR_POLL_CNTL
	.comm	_WPTR_POLL_EN,4,2               ; @WPTR_POLL_EN
	.comm	_CP_HQD_PQ_DOORBELL_CONTROL,4,2 ; @CP_HQD_PQ_DOORBELL_CONTROL
	.comm	_DOORBELL_EN,4,2                ; @DOORBELL_EN
	.comm	_CP_HQD_ACTIVE,4,2              ; @CP_HQD_ACTIVE
	.comm	_CP_HQD_DEQUEUE_REQUEST,4,2     ; @CP_HQD_DEQUEUE_REQUEST
	.comm	_CP_HQD_PQ_RPTR,4,2             ; @CP_HQD_PQ_RPTR
	.comm	_CP_HQD_PQ_WPTR,4,2             ; @CP_HQD_PQ_WPTR
	.comm	_CP_MQD_BASE_ADDR,4,2           ; @CP_MQD_BASE_ADDR
	.comm	_CP_MQD_BASE_ADDR_HI,4,2        ; @CP_MQD_BASE_ADDR_HI
	.comm	_CP_MQD_CONTROL,4,2             ; @CP_MQD_CONTROL
	.comm	_MQD_VMID_MASK,4,2              ; @MQD_VMID_MASK
	.comm	_CP_HQD_PQ_BASE,4,2             ; @CP_HQD_PQ_BASE
	.comm	_CP_HQD_PQ_BASE_HI,4,2          ; @CP_HQD_PQ_BASE_HI
	.comm	_CP_HQD_PQ_CONTROL,4,2          ; @CP_HQD_PQ_CONTROL
	.comm	_QUEUE_SIZE_MASK,4,2            ; @QUEUE_SIZE_MASK
	.comm	_RPTR_BLOCK_SIZE_MASK,4,2       ; @RPTR_BLOCK_SIZE_MASK
	.comm	_RADEON_GPU_PAGE_SIZE,4,2       ; @RADEON_GPU_PAGE_SIZE
	.comm	_UNORD_DISPATCH,4,2             ; @UNORD_DISPATCH
	.comm	_ROQ_PQ_IB_FLIP,4,2             ; @ROQ_PQ_IB_FLIP
	.comm	_PQ_VOLATILE,4,2                ; @PQ_VOLATILE
	.comm	_PRIV_STATE,4,2                 ; @PRIV_STATE
	.comm	_KMD_QUEUE,4,2                  ; @KMD_QUEUE
	.comm	_CIK_WB_CP1_WPTR_OFFSET,4,2     ; @CIK_WB_CP1_WPTR_OFFSET
	.comm	_CIK_WB_CP2_WPTR_OFFSET,4,2     ; @CIK_WB_CP2_WPTR_OFFSET
	.comm	_CP_HQD_PQ_WPTR_POLL_ADDR,4,2   ; @CP_HQD_PQ_WPTR_POLL_ADDR
	.comm	_CP_HQD_PQ_WPTR_POLL_ADDR_HI,4,2 ; @CP_HQD_PQ_WPTR_POLL_ADDR_HI
	.comm	_RADEON_WB_CP1_RPTR_OFFSET,4,2  ; @RADEON_WB_CP1_RPTR_OFFSET
	.comm	_RADEON_WB_CP2_RPTR_OFFSET,4,2  ; @RADEON_WB_CP2_RPTR_OFFSET
	.comm	_CP_HQD_PQ_RPTR_REPORT_ADDR,4,2 ; @CP_HQD_PQ_RPTR_REPORT_ADDR
	.comm	_CP_HQD_PQ_RPTR_REPORT_ADDR_HI,4,2 ; @CP_HQD_PQ_RPTR_REPORT_ADDR_HI
	.comm	_DOORBELL_OFFSET_MASK,4,2       ; @DOORBELL_OFFSET_MASK
	.comm	_DOORBELL_SOURCE,4,2            ; @DOORBELL_SOURCE
	.comm	_DOORBELL_HIT,4,2               ; @DOORBELL_HIT
	.comm	_CP_HQD_VMID,4,2                ; @CP_HQD_VMID
	.comm	_BUF_SWAP_32BIT,4,2             ; @BUF_SWAP_32BIT
	.no_dead_strip	_cik_cp_compute_resume
.subsections_via_symbols
