	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ironlake_crtc_disable
_ironlake_crtc_disable:                 ## @ironlake_crtc_disable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, -56(%rbp)                 ## 8-byte Spill
	movq	%rdi, %rbx
	movq	8(%rdi), %r15
	movq	(%r15), %rdi
	callq	_to_i915
	movq	%rax, %r14
	movq	%r15, %rdi
	callq	_to_intel_crtc
	movq	%rax, %r13
	movl	(%rax), %r12d
	movq	%r14, %rdi
	movl	%r12d, %esi
	xorl	%edx, %edx
	callq	_intel_set_cpu_fifo_underrun_reporting
	movq	%r14, %rdi
	movl	%r12d, %esi
	xorl	%edx, %edx
	callq	_intel_set_pch_fifo_underrun_reporting
	movq	%r13, -48(%rbp)                 ## 8-byte Spill
	movq	%r13, %rdi
	movq	-56(%rbp), %r13                 ## 8-byte Reload
	movq	%rbx, %rsi
	movq	%r13, %rdx
	callq	_intel_encoders_disable
	movq	%r15, %rdi
	callq	_drm_crtc_vblank_off
	movq	%r15, %rdi
	callq	_assert_vblank_disabled
	movq	%rbx, %rdi
	callq	_intel_disable_pipe
	movq	%rbx, %rdi
	callq	_ironlake_pfit_disable
	cmpq	$0, (%rbx)
	je	LBB0_2
## %bb.1:
	movq	%r15, %rdi
	callq	_ironlake_fdi_disable
LBB0_2:
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movq	%rbx, %rsi
	movq	%r13, %rdx
	callq	_intel_encoders_post_disable
	cmpq	$0, (%rbx)
	je	LBB0_6
## %bb.3:
	movq	%r14, %rdi
	movl	%r12d, %esi
	callq	_ironlake_disable_pch_transcoder
	movq	%r14, %rdi
	callq	_HAS_PCH_CPT
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	movl	%r12d, %edi
	callq	_TRANS_DP_CTL
	movl	%eax, %ebx
	movl	%eax, %edi
	callq	_I915_READ
	movq	_TRANS_DP_OUTPUT_ENABLE@GOTPCREL(%rip), %rcx
	movq	_TRANS_DP_PORT_SEL_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_TRANS_DP_PORT_SEL_NONE@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	%ebx, %edi
	callq	_I915_WRITE
	movq	_PCH_DPLL_SEL@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_I915_READ
	movl	%eax, %r15d
	movl	%r12d, %edi
	callq	_TRANS_DPLL_ENABLE
	movl	%eax, %ebx
	movl	%r12d, %edi
	callq	_TRANS_DPLLB_SEL
	orl	%eax, %ebx
	notl	%ebx
	andl	%r15d, %ebx
	movl	(%r13), %edi
	movl	%ebx, %esi
	callq	_I915_WRITE
LBB0_5:
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_ironlake_fdi_pll_disable
LBB0_6:
	movq	%r14, %rdi
	movl	%r12d, %esi
	movl	$1, %edx
	callq	_intel_set_cpu_fifo_underrun_reporting
	movq	%r14, %rdi
	movl	%r12d, %esi
	movl	$1, %edx
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_intel_set_pch_fifo_underrun_reporting ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_TRANS_DP_OUTPUT_ENABLE,4,2     ## @TRANS_DP_OUTPUT_ENABLE
	.comm	_TRANS_DP_PORT_SEL_MASK,4,2     ## @TRANS_DP_PORT_SEL_MASK
	.comm	_TRANS_DP_PORT_SEL_NONE,4,2     ## @TRANS_DP_PORT_SEL_NONE
	.comm	_PCH_DPLL_SEL,4,2               ## @PCH_DPLL_SEL
	.no_dead_strip	_ironlake_crtc_disable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ironlake_crtc_disable
_ironlake_crtc_disable:                 ; @ironlake_crtc_disable
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x23, x1
	mov	x22, x0
	ldr	x24, [x0, #8]
	ldr	x0, [x24]
	bl	_to_i915
	mov	x19, x0
	mov	x0, x24
	bl	_to_intel_crtc
	mov	x21, x0
	ldr	w20, [x0]
	mov	x0, x19
	mov	x1, x20
	mov	w2, #0
	bl	_intel_set_cpu_fifo_underrun_reporting
	mov	x0, x19
	mov	x1, x20
	mov	w2, #0
	bl	_intel_set_pch_fifo_underrun_reporting
	mov	x0, x21
	mov	x1, x22
	mov	x2, x23
	bl	_intel_encoders_disable
	mov	x0, x24
	bl	_drm_crtc_vblank_off
	mov	x0, x24
	bl	_assert_vblank_disabled
	mov	x0, x22
	bl	_intel_disable_pipe
	mov	x0, x22
	bl	_ironlake_pfit_disable
	ldr	x8, [x22]
	cbz	x8, LBB0_2
; %bb.1:
	mov	x0, x24
	bl	_ironlake_fdi_disable
LBB0_2:
	mov	x0, x21
	mov	x1, x22
	mov	x2, x23
	bl	_intel_encoders_post_disable
	ldr	x8, [x22]
	cbz	x8, LBB0_6
; %bb.3:
	mov	x0, x19
	mov	x1, x20
	bl	_ironlake_disable_pch_transcoder
	mov	x0, x19
	bl	_HAS_PCH_CPT
	cbz	x0, LBB0_5
; %bb.4:
	mov	x0, x20
	bl	_TRANS_DP_CTL
	mov	x22, x0
	bl	_I915_READ
Lloh0:
	adrp	x8, _TRANS_DP_OUTPUT_ENABLE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _TRANS_DP_OUTPUT_ENABLE@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _TRANS_DP_PORT_SEL_MASK@GOTPAGE
Lloh4:
	ldr	x9, [x9, _TRANS_DP_PORT_SEL_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
Lloh6:
	adrp	x9, _TRANS_DP_PORT_SEL_NONE@GOTPAGE
Lloh7:
	ldr	x9, [x9, _TRANS_DP_PORT_SEL_NONE@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	orr	w1, w8, w9
	mov	x0, x22
	bl	_I915_WRITE
Lloh9:
	adrp	x24, _PCH_DPLL_SEL@GOTPAGE
Lloh10:
	ldr	x24, [x24, _PCH_DPLL_SEL@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_I915_READ
	mov	x22, x0
	mov	x0, x20
	bl	_TRANS_DPLL_ENABLE
	mov	x23, x0
	mov	x0, x20
	bl	_TRANS_DPLLB_SEL
	orr	w8, w0, w23
	bic	w1, w22, w8
	ldr	w0, [x24]
	bl	_I915_WRITE
LBB0_5:
	mov	x0, x21
	bl	_ironlake_fdi_pll_disable
LBB0_6:
	mov	x0, x19
	mov	x1, x20
	mov	w2, #1
	bl	_intel_set_cpu_fifo_underrun_reporting
	mov	x0, x19
	mov	x1, x20
	mov	w2, #1
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_intel_set_pch_fifo_underrun_reporting
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_TRANS_DP_OUTPUT_ENABLE,4,2     ; @TRANS_DP_OUTPUT_ENABLE
	.comm	_TRANS_DP_PORT_SEL_MASK,4,2     ; @TRANS_DP_PORT_SEL_MASK
	.comm	_TRANS_DP_PORT_SEL_NONE,4,2     ; @TRANS_DP_PORT_SEL_NONE
	.comm	_PCH_DPLL_SEL,4,2               ; @PCH_DPLL_SEL
	.no_dead_strip	_ironlake_crtc_disable
.subsections_via_symbols
