	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_sor_edp_enable
_tegra_sor_edp_enable:                  ## @tegra_sor_edp_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$72, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	(%rdi), %rax
	movq	(%rax), %r13
	callq	_encoder_to_output
	movq	%rax, %r15
	movq	(%rbx), %rdi
	callq	_to_tegra_dc
	movq	%rax, %rbx
	movq	%r15, %rdi
	callq	_to_sor
	movq	%rax, %r14
	movl	8(%r15), %edi
	callq	_to_sor_state
	movq	%rax, -88(%rbp)                 ## 8-byte Spill
	movl	(%r14), %edi
	callq	_pm_runtime_get_sync
	movq	(%r15), %rdi
	testq	%rdi, %rdi
	je	LBB0_2
## %bb.1:
	callq	_drm_panel_prepare
LBB0_2:
	movl	4(%r14), %edi
	callq	_drm_dp_aux_enable
	testl	%eax, %eax
	jns	LBB0_4
## %bb.3:
	movl	(%r14), %edi
	leaq	L_.str(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
LBB0_4:
	movl	4(%r14), %edi
	leaq	-56(%rbp), %rsi
	callq	_drm_dp_link_probe
	testl	%eax, %eax
	js	LBB0_5
## %bb.6:
	movq	%rbx, -104(%rbp)                ## 8-byte Spill
	movl	36(%r14), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_set_parent_clock
	testl	%eax, %eax
	jns	LBB0_8
## %bb.7:
	movl	(%r14), %edi
	leaq	L_.str.2(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
LBB0_8:
	leaq	-64(%rbp), %r12
	movq	%r12, %rdi
	xorl	%esi, %esi
	movl	$4, %edx
	callq	_memset
	movq	-88(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %eax
	leal	(%rax,%rax,2), %eax
	movl	%eax, -64(%rbp)
	leaq	-56(%rbp), %rcx
	movq	%r14, %rdi
	movq	%r13, %rsi
	movq	%r12, %rdx
	callq	_tegra_sor_compute_config
	testl	%eax, %eax
	jns	LBB0_10
## %bb.9:
	movl	(%r14), %edi
	leaq	L_.str.3(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
LBB0_10:
	movq	%r13, -96(%rbp)                 ## 8-byte Spill
	movq	%r15, -80(%rbp)                 ## 8-byte Spill
	movq	_SOR_CLK_CNTRL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_CLK_CNTRL_DP_CLK_SEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	(%rbx), %edx
	movq	%r14, %rdi
	callq	_tegra_sor_writel
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	4(%rax), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_PLL2_BANDGAP_POWERDOWN@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	notl	%esi
	andl	%eax, %esi
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	4(%rax), %edx
	movq	%r14, %rdi
	callq	_tegra_sor_writel
	movl	$20, %edi
	movl	$100, %esi
	callq	_usleep_range
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	16(%rax), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_PLL3_PLL_VDD_MODE_3V3@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	8(%r14), %rcx
	movq	(%rcx), %rcx
	movl	16(%rcx), %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_tegra_sor_writel
	movl	$15, %edi
	callq	_SOR_PLL0_ICHPMP
	movq	_SOR_PLL0_VCOCAP_RST@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_SOR_PLL0_PLLREG_LEVEL_V45@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_SOR_PLL0_RESISTOR_EXT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	8(%r14), %rcx
	movq	(%rcx), %rcx
	movl	8(%rcx), %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_tegra_sor_writel
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	4(%rax), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_PLL2_SEQ_PLLCAPPD@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_SOR_PLL2_SEQ_PLLCAPPD_ENFORCE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_SOR_PLL2_LVDS_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	4(%rax), %edx
	movq	%r14, %rdi
	callq	_tegra_sor_writel
	movq	_SOR_PLL1_TERM_COMPOUT@GOTPCREL(%rip), %rax
	movq	_SOR_PLL1_TMDS_TERM@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	12(%rax), %edx
	movq	%r14, %rdi
	callq	_tegra_sor_writel
	.p2align	4, 0x90
LBB0_12:                                ## =>This Inner Loop Header: Depth=1
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	4(%rax), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	testl	%eax, (%rbx)
	je	LBB0_13
## %bb.11:                              ##   in Loop: Header=BB0_12 Depth=1
	movl	$250, %edi
	movl	$1000, %esi                     ## imm = 0x3E8
	callq	_usleep_range
	jmp	LBB0_12
LBB0_13:
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	4(%rax), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_PLL2_POWERDOWN_OVERRIDE@GOTPCREL(%rip), %rcx
	movq	_SOR_PLL2_PORT_POWERDOWN@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	orl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	4(%rax), %edx
	movq	%r14, %rdi
	callq	_tegra_sor_writel
	movq	_SOR_CLK_CNTRL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	(%r15), %edx
	movq	%r14, %rdi
	callq	_tegra_sor_writel
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	4(%rax), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	orl	(%rbx), %eax
	orl	(%r12), %eax
	orl	(%r13), %eax
	movq	8(%r14), %rcx
	movq	(%rcx), %rcx
	movl	4(%rcx), %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_tegra_sor_writel
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	8(%rax), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	%r13, %r12
	movq	_SOR_PLL0_VCOPD@GOTPCREL(%rip), %r13
	movq	_SOR_PLL0_PWR@GOTPCREL(%rip), %r15
	orl	(%r13), %eax
	orl	(%r15), %eax
	movq	8(%r14), %rcx
	movq	(%rcx), %rcx
	movl	8(%rcx), %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_tegra_sor_writel
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_DP_PADCTL_PAD_CAL_PD@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_tegra_sor_writel
	movl	32(%r14), %edi
	callq	_tegra_io_pad_power_enable
	testl	%eax, %eax
	jns	LBB0_15
## %bb.14:
	movl	(%r14), %edi
	leaq	L_.str.4(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
LBB0_15:
	movl	$5, %edi
	movl	$100, %esi
	callq	_usleep_range
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	4(%rax), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movl	(%r12), %esi
	notl	%esi
	andl	%eax, %esi
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	4(%rax), %edx
	movq	%r14, %rdi
	callq	_tegra_sor_writel
	movl	$20, %edi
	movl	$100, %esi
	callq	_usleep_range
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	8(%rax), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movl	(%r15), %esi
	orl	(%r13), %esi
	notl	%esi
	andl	%eax, %esi
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	8(%rax), %edx
	movq	%r14, %rdi
	callq	_tegra_sor_writel
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	4(%rax), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movl	(%rbx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	4(%rax), %edx
	movq	%r14, %rdi
	callq	_tegra_sor_writel
	movl	$200, %edi
	movl	$1000, %esi                     ## imm = 0x3E8
	callq	_usleep_range
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	4(%rax), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_PLL2_PORT_POWERDOWN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	4(%rax), %edx
	movq	%r14, %rdi
	callq	_tegra_sor_writel
	movq	24(%r14), %rax
	movl	(%rax), %esi
	xorl	%edi, %edi
	callq	_SOR_XBAR_CTRL_LINK0_XSEL
	movl	%eax, %r13d
	xorl	%edi, %edi
	xorl	%esi, %esi
	callq	_SOR_XBAR_CTRL_LINK1_XSEL
	orl	%eax, %r13d
	movq	24(%r14), %rax
	movl	4(%rax), %esi
	movl	$1, %edi
	callq	_SOR_XBAR_CTRL_LINK0_XSEL
	movl	%eax, %r12d
	movl	$1, %edi
	movl	$1, %esi
	callq	_SOR_XBAR_CTRL_LINK1_XSEL
	orl	%eax, %r12d
	orl	%r13d, %r12d
	movq	24(%r14), %rax
	movl	8(%rax), %esi
	movl	$2, %edi
	callq	_SOR_XBAR_CTRL_LINK0_XSEL
	movl	%eax, %r15d
	movl	$2, %edi
	movl	$2, %esi
	callq	_SOR_XBAR_CTRL_LINK1_XSEL
	orl	%eax, %r15d
	movq	24(%r14), %rax
	movl	12(%rax), %esi
	movl	$3, %edi
	callq	_SOR_XBAR_CTRL_LINK0_XSEL
	movl	%eax, %r13d
	movl	$3, %edi
	movl	$3, %esi
	callq	_SOR_XBAR_CTRL_LINK1_XSEL
	movl	%eax, -68(%rbp)                 ## 4-byte Spill
	orl	%r15d, %r13d
	orl	%r12d, %r13d
	movq	24(%r14), %rax
	movl	16(%rax), %esi
	movl	$4, %edi
	callq	_SOR_XBAR_CTRL_LINK0_XSEL
	movl	%eax, %ebx
	movl	$4, %edi
	movl	$4, %esi
	callq	_SOR_XBAR_CTRL_LINK1_XSEL
	orl	-68(%rbp), %ebx                 ## 4-byte Folded Reload
	orl	%eax, %ebx
	orl	%r13d, %ebx
	movq	_SOR_XBAR_POL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_tegra_sor_writel
	movq	_SOR_XBAR_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_tegra_sor_writel
	movl	16(%r14), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_set_parent_clock
	testl	%eax, %eax
	jns	LBB0_17
## %bb.16:
	movl	(%r14), %edi
	leaq	L_.str.5(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
LBB0_17:
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movl	-56(%rbp), %ecx
	movq	_SOR_DP_PADCTL_PD_TXD_3@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	movq	_SOR_DP_PADCTL_PD_TXD_2@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	cmpl	$3, %ecx
	jge	LBB0_18
## %bb.19:
	orl	%esi, %edx
	notl	%edx
	andl	%edx, %eax
	cmpl	$2, %ecx
	je	LBB0_20
## %bb.22:
	movq	_SOR_DP_PADCTL_PD_TXD_1@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	notl	%edx
	andl	%edx, %eax
	testl	%ecx, %ecx
	jne	LBB0_21
## %bb.23:
	movq	_SOR_DP_PADCTL_PD_TXD_0@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%ecx, %eax
	jmp	LBB0_24
LBB0_5:
	movl	(%r14), %edi
	leaq	L_.str.1(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
	jmp	LBB0_55
LBB0_18:
	orl	%eax, %esi
	orl	%edx, %esi
	movl	%esi, %eax
LBB0_20:
	movq	_SOR_DP_PADCTL_PD_TXD_1@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
LBB0_21:
	movq	_SOR_DP_PADCTL_PD_TXD_0@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
LBB0_24:
	movq	8(%r14), %rcx
	movq	(%rcx), %rcx
	movl	(%rcx), %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_tegra_sor_writel
	movq	_SOR_DP_LINKCTL0@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_DP_LINKCTL_LANE_COUNT_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	-56(%rbp), %edi
	callq	_SOR_DP_LINKCTL_LANE_COUNT
	orl	%eax, %ebx
	movl	(%r12), %edx
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_tegra_sor_writel
	movq	_SOR_LANE_SEQ_CTL_TRIGGER@GOTPCREL(%rip), %r15
	movq	_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	(%r15), %esi
	movq	_SOR_LANE_SEQ_CTL_POWER_STATE_UP@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_SOR_LANE_SEQ_CTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r14, %rdi
	callq	_tegra_sor_writel
	.p2align	4, 0x90
LBB0_26:                                ## =>This Inner Loop Header: Depth=1
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	testl	%eax, (%r15)
	je	LBB0_27
## %bb.25:                              ##   in Loop: Header=BB0_26 Depth=1
	movl	$250, %edi
	movl	$1000, %esi                     ## imm = 0x3E8
	callq	_usleep_range
	jmp	LBB0_26
LBB0_27:
	movq	_SOR_CLK_CNTRL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	-48(%rbp), %edi
	callq	_drm_dp_link_rate_to_bw_code
                                        ## kill: def $eax killed $eax def $rax
	leal	(,%rax,4), %esi
	orl	%ebx, %esi
	movl	(%r15), %edx
	movq	%r14, %rdi
	callq	_tegra_sor_writel
	leaq	-64(%rbp), %rsi
	movq	%r14, %rdi
	callq	_tegra_sor_apply_config
	movl	(%r12), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_DP_LINKCTL_ENABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_SOR_DP_LINKCTL_ENHANCED_FRAME@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r12), %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_tegra_sor_writel
	movq	_SOR_DP_TPG_CHANNEL_CODING@GOTPCREL(%rip), %rcx
	movq	_SOR_DP_TPG_SCRAMBLER_GALIOS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	(%rcx), %eax
	movq	_SOR_DP_TPG_PATTERN_NONE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, %ecx
	shll	$16, %ecx
	movl	%eax, %esi
	shll	$8, %esi
	orl	%ecx, %esi
	orl	%eax, %esi
	shll	$8, %esi
	orl	%eax, %esi
	movq	_SOR_DP_TPG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_tegra_sor_writel
	movq	8(%r14), %rax
	movq	(%rax), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_DP_PADCTL_PAD_CAL_PD@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	8(%r14), %rcx
	movq	(%rcx), %rcx
	movl	(%rcx), %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_tegra_sor_writel
	movl	4(%r14), %edi
	leaq	-56(%rbp), %rsi
	callq	_drm_dp_link_probe
	testl	%eax, %eax
	jns	LBB0_29
## %bb.28:
	movl	(%r14), %edi
	leaq	L_.str.1(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
LBB0_29:
	movl	4(%r14), %edi
	leaq	-56(%rbp), %rsi
	callq	_drm_dp_link_power_up
	testl	%eax, %eax
	jns	LBB0_31
## %bb.30:
	movl	(%r14), %edi
	leaq	L_.str.6(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
LBB0_31:
	movl	4(%r14), %edi
	leaq	-56(%rbp), %rsi
	callq	_drm_dp_link_configure
	testl	%eax, %eax
	jns	LBB0_33
## %bb.32:
	movl	(%r14), %edi
	leaq	L_.str.7(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
LBB0_33:
	movl	-48(%rbp), %edi
	callq	_drm_dp_link_rate_to_bw_code
	movl	%eax, %r15d
	movl	-56(%rbp), %r12d
	movq	_SOR_CLK_CNTRL@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	%r15d, %edi
	callq	_SOR_CLK_CNTRL_DP_LINK_SPEED
	orl	%eax, %ebx
	movl	(%r13), %edx
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_tegra_sor_writel
	movq	_SOR_DP_LINKCTL0@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_DP_LINKCTL_LANE_COUNT_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	%r12d, %edi
	callq	_SOR_DP_LINKCTL_LANE_COUNT
	movl	%eax, %r12d
	orl	%ebx, %r12d
	movq	_DP_LINK_CAP_ENHANCED_FRAMING@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	-52(%rbp), %eax
	je	LBB0_35
## %bb.34:
	movq	_SOR_DP_LINKCTL_ENHANCED_FRAME@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_35:
	orl	%eax, %r12d
	movl	(%r15), %edx
	movq	%r14, %rdi
	movl	%r12d, %esi
	callq	_tegra_sor_writel
	movl	-56(%rbp), %edx
	testl	%edx, %edx
	je	LBB0_36
## %bb.37:
	movq	_SOR_DP_TPG_SCRAMBLER_GALIOS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_SOR_DP_TPG_CHANNEL_CODING@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_SOR_DP_TPG_PATTERN_NONE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	leal	-1(%rdx), %esi
	movl	%edx, %ecx
	andl	$7, %ecx
	cmpl	$7, %esi
	movq	-80(%rbp), %r13                 ## 8-byte Reload
	jb	LBB0_41
## %bb.38:
	andl	$-8, %edx
	.p2align	4, 0x90
LBB0_39:                                ## =>This Inner Loop Header: Depth=1
	addl	$-8, %edx
	jne	LBB0_39
## %bb.40:
	movl	%eax, %edx
	shll	$16, %edx
	movl	%eax, %r12d
	shll	$8, %r12d
	orl	%edx, %r12d
	orl	%eax, %r12d
	shll	$8, %r12d
	orl	%eax, %r12d
LBB0_41:
	testl	%ecx, %ecx
	movq	_SOR_DP_TPG@GOTPCREL(%rip), %rdx
	je	LBB0_43
	.p2align	4, 0x90
LBB0_42:                                ## =>This Inner Loop Header: Depth=1
	shll	$8, %r12d
	orl	%eax, %r12d
	decl	%ecx
	jne	LBB0_42
	jmp	LBB0_43
LBB0_36:
	movq	-80(%rbp), %r13                 ## 8-byte Reload
	movq	_SOR_DP_TPG@GOTPCREL(%rip), %rdx
LBB0_43:
	movl	(%rdx), %edx
	movq	%r14, %rdi
	movl	%r12d, %esi
	callq	_tegra_sor_writel
	leaq	-56(%rbp), %rsi
	movq	%r14, %rdi
	callq	_tegra_sor_dp_train_fast
	testl	%eax, %eax
	jns	LBB0_45
## %bb.44:
	movl	(%r14), %edi
	leaq	L_.str.8(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
LBB0_45:
	movl	(%r14), %edi
	leaq	L_.str.9(%rip), %rsi
	callq	_dev_dbg
	movq	%r14, %rdi
	movl	$250, %esi
	callq	_tegra_sor_power_up
	testl	%eax, %eax
	movq	-104(%rbp), %r12                ## 8-byte Reload
	jns	LBB0_47
## %bb.46:
	movl	(%r14), %edi
	leaq	L_.str.10(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
LBB0_47:
	movq	_SOR_CSTM_LVDS@GOTPCREL(%rip), %rax
	movq	_SOR_CSTM_LINK_ACT_A@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movq	_SOR_CSTM_LINK_ACT_B@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_SOR_CSTM_UPPER@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_SOR_CSTM@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_tegra_sor_writel
	movq	_SOR_STATE1@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_tegra_sor_readl
	movq	_SOR_STATE_ASY_PROTOCOL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_SOR_STATE_ASY_PROTOCOL_DP_A@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	(%rbx), %edx
	movq	%r14, %rdi
	callq	_tegra_sor_writel
	movq	%r14, %rdi
	movq	-96(%rbp), %rsi                 ## 8-byte Reload
	movq	-88(%rbp), %rdx                 ## 8-byte Reload
	callq	_tegra_sor_mode_set
	movq	%r14, %rdi
	movl	$250, %esi
	callq	_tegra_sor_setup_pwm
	testl	%eax, %eax
	jns	LBB0_49
## %bb.48:
	movl	(%r14), %edi
	leaq	L_.str.11(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
LBB0_49:
	movq	%r14, %rdi
	callq	_tegra_sor_update
	movq	_DC_DISP_DISP_WIN_OPTIONS@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r12, %rdi
	callq	_tegra_dc_readl
	movl	%eax, %ebx
	xorl	%edi, %edi
	callq	_SOR_ENABLE
	orl	%eax, %ebx
	movl	(%r15), %edx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_tegra_dc_writel
	movq	%r12, %rdi
	callq	_tegra_dc_commit
	movq	%r14, %rdi
	callq	_tegra_sor_attach
	testl	%eax, %eax
	jns	LBB0_51
## %bb.50:
	movl	(%r14), %edi
	leaq	L_.str.12(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
LBB0_51:
	movq	%r14, %rdi
	callq	_tegra_sor_wakeup
	testl	%eax, %eax
	jns	LBB0_53
## %bb.52:
	movl	(%r14), %edi
	leaq	L_.str.13(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
LBB0_53:
	movq	(%r13), %rdi
	testq	%rdi, %rdi
	je	LBB0_55
## %bb.54:
	callq	_drm_panel_enable
LBB0_55:
	addq	$72, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"failed to enable DP: %d\n"

L_.str.1:                               ## @.str.1
	.asciz	"failed to probe eDP link: %d\n"

L_.str.2:                               ## @.str.2
	.asciz	"failed to set safe parent clock: %d\n"

L_.str.3:                               ## @.str.3
	.asciz	"failed to compute configuration: %d\n"

	.comm	_SOR_CLK_CNTRL,4,2              ## @SOR_CLK_CNTRL
	.comm	_SOR_CLK_CNTRL_DP_CLK_SEL_MASK,4,2 ## @SOR_CLK_CNTRL_DP_CLK_SEL_MASK
	.comm	_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK,4,2 ## @SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK
	.comm	_SOR_PLL2_BANDGAP_POWERDOWN,4,2 ## @SOR_PLL2_BANDGAP_POWERDOWN
	.comm	_SOR_PLL3_PLL_VDD_MODE_3V3,4,2  ## @SOR_PLL3_PLL_VDD_MODE_3V3
	.comm	_SOR_PLL0_VCOCAP_RST,4,2        ## @SOR_PLL0_VCOCAP_RST
	.comm	_SOR_PLL0_PLLREG_LEVEL_V45,4,2  ## @SOR_PLL0_PLLREG_LEVEL_V45
	.comm	_SOR_PLL0_RESISTOR_EXT,4,2      ## @SOR_PLL0_RESISTOR_EXT
	.comm	_SOR_PLL2_SEQ_PLLCAPPD,4,2      ## @SOR_PLL2_SEQ_PLLCAPPD
	.comm	_SOR_PLL2_SEQ_PLLCAPPD_ENFORCE,4,2 ## @SOR_PLL2_SEQ_PLLCAPPD_ENFORCE
	.comm	_SOR_PLL2_LVDS_ENABLE,4,2       ## @SOR_PLL2_LVDS_ENABLE
	.comm	_SOR_PLL1_TERM_COMPOUT,4,2      ## @SOR_PLL1_TERM_COMPOUT
	.comm	_SOR_PLL1_TMDS_TERM,4,2         ## @SOR_PLL1_TMDS_TERM
	.comm	_SOR_PLL2_POWERDOWN_OVERRIDE,4,2 ## @SOR_PLL2_POWERDOWN_OVERRIDE
	.comm	_SOR_PLL2_PORT_POWERDOWN,4,2    ## @SOR_PLL2_PORT_POWERDOWN
	.comm	_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK,4,2 ## @SOR_CLK_CNTRL_DP_LINK_SPEED_MASK
	.comm	_SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62,4,2 ## @SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62
	.comm	_SOR_PLL0_VCOPD,4,2             ## @SOR_PLL0_VCOPD
	.comm	_SOR_PLL0_PWR,4,2               ## @SOR_PLL0_PWR
	.comm	_SOR_DP_PADCTL_PAD_CAL_PD,4,2   ## @SOR_DP_PADCTL_PAD_CAL_PD
L_.str.4:                               ## @.str.4
	.asciz	"failed to power on I/O pad: %d\n"

	.comm	_SOR_XBAR_POL,4,2               ## @SOR_XBAR_POL
	.comm	_SOR_XBAR_CTRL,4,2              ## @SOR_XBAR_CTRL
L_.str.5:                               ## @.str.5
	.asciz	"failed to set parent clock: %d\n"

	.comm	_SOR_DP_PADCTL_PD_TXD_3,4,2     ## @SOR_DP_PADCTL_PD_TXD_3
	.comm	_SOR_DP_PADCTL_PD_TXD_2,4,2     ## @SOR_DP_PADCTL_PD_TXD_2
	.comm	_SOR_DP_PADCTL_PD_TXD_1,4,2     ## @SOR_DP_PADCTL_PD_TXD_1
	.comm	_SOR_DP_PADCTL_PD_TXD_0,4,2     ## @SOR_DP_PADCTL_PD_TXD_0
	.comm	_SOR_DP_LINKCTL0,4,2            ## @SOR_DP_LINKCTL0
	.comm	_SOR_DP_LINKCTL_LANE_COUNT_MASK,4,2 ## @SOR_DP_LINKCTL_LANE_COUNT_MASK
	.comm	_SOR_LANE_SEQ_CTL_TRIGGER,4,2   ## @SOR_LANE_SEQ_CTL_TRIGGER
	.comm	_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN,4,2 ## @SOR_LANE_SEQ_CTL_SEQUENCE_DOWN
	.comm	_SOR_LANE_SEQ_CTL_POWER_STATE_UP,4,2 ## @SOR_LANE_SEQ_CTL_POWER_STATE_UP
	.comm	_SOR_LANE_SEQ_CTL,4,2           ## @SOR_LANE_SEQ_CTL
	.comm	_SOR_DP_LINKCTL_ENABLE,4,2      ## @SOR_DP_LINKCTL_ENABLE
	.comm	_SOR_DP_LINKCTL_ENHANCED_FRAME,4,2 ## @SOR_DP_LINKCTL_ENHANCED_FRAME
	.comm	_SOR_DP_TPG_CHANNEL_CODING,8,3  ## @SOR_DP_TPG_CHANNEL_CODING
	.comm	_SOR_DP_TPG_SCRAMBLER_GALIOS,8,3 ## @SOR_DP_TPG_SCRAMBLER_GALIOS
	.comm	_SOR_DP_TPG_PATTERN_NONE,8,3    ## @SOR_DP_TPG_PATTERN_NONE
	.comm	_SOR_DP_TPG,4,2                 ## @SOR_DP_TPG
L_.str.6:                               ## @.str.6
	.asciz	"failed to power up eDP link: %d\n"

L_.str.7:                               ## @.str.7
	.asciz	"failed to configure eDP link: %d\n"

	.comm	_DP_LINK_CAP_ENHANCED_FRAMING,4,2 ## @DP_LINK_CAP_ENHANCED_FRAMING
L_.str.8:                               ## @.str.8
	.asciz	"DP fast link training failed: %d\n"

L_.str.9:                               ## @.str.9
	.asciz	"fast link training succeeded\n"

L_.str.10:                              ## @.str.10
	.asciz	"failed to power up SOR: %d\n"

	.comm	_SOR_CSTM_LVDS,4,2              ## @SOR_CSTM_LVDS
	.comm	_SOR_CSTM_LINK_ACT_A,4,2        ## @SOR_CSTM_LINK_ACT_A
	.comm	_SOR_CSTM_LINK_ACT_B,4,2        ## @SOR_CSTM_LINK_ACT_B
	.comm	_SOR_CSTM_UPPER,4,2             ## @SOR_CSTM_UPPER
	.comm	_SOR_CSTM,4,2                   ## @SOR_CSTM
	.comm	_SOR_STATE1,4,2                 ## @SOR_STATE1
	.comm	_SOR_STATE_ASY_PROTOCOL_MASK,4,2 ## @SOR_STATE_ASY_PROTOCOL_MASK
	.comm	_SOR_STATE_ASY_PROTOCOL_DP_A,4,2 ## @SOR_STATE_ASY_PROTOCOL_DP_A
L_.str.11:                              ## @.str.11
	.asciz	"failed to setup PWM: %d\n"

	.comm	_DC_DISP_DISP_WIN_OPTIONS,4,2   ## @DC_DISP_DISP_WIN_OPTIONS
L_.str.12:                              ## @.str.12
	.asciz	"failed to attach SOR: %d\n"

L_.str.13:                              ## @.str.13
	.asciz	"failed to enable DC: %d\n"

	.no_dead_strip	_tegra_sor_edp_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_sor_edp_enable
_tegra_sor_edp_enable:                  ; @tegra_sor_edp_enable
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #160
	.cfi_def_cfa_offset 160
	stp	x28, x27, [sp, #64]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #80]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #96]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #112]            ; 16-byte Folded Spill
	stp	x20, x19, [sp, #128]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #144]            ; 16-byte Folded Spill
	add	x29, sp, #144
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x20, x0
	ldr	x8, [x0]
	ldr	x21, [x8]
	bl	_encoder_to_output
	mov	x19, x0
	ldr	x0, [x20]
	bl	_to_tegra_dc
	mov	x23, x0
	mov	x0, x19
	bl	_to_sor
	mov	x20, x0
	ldr	w0, [x19, #8]
	bl	_to_sor_state
	mov	x26, x0
	ldr	w0, [x20]
	bl	_pm_runtime_get_sync
	ldr	x0, [x19]
	cbz	x0, LBB0_2
; %bb.1:
	bl	_drm_panel_prepare
LBB0_2:
	ldr	w0, [x20, #4]
	bl	_drm_dp_aux_enable
	tbz	w0, #31, LBB0_4
; %bb.3:
	mov	x2, x0
	ldr	w0, [x20]
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
LBB0_4:
	ldr	w0, [x20, #4]
	add	x1, sp, #40
	bl	_drm_dp_link_probe
	tbnz	w0, #31, LBB0_20
; %bb.5:
	ldr	w1, [x20, #36]
	mov	x0, x20
	bl	_tegra_sor_set_parent_clock
	tbz	w0, #31, LBB0_7
; %bb.6:
	mov	x2, x0
	ldr	w0, [x20]
Lloh2:
	adrp	x1, l_.str.2@PAGE
Lloh3:
	add	x1, x1, l_.str.2@PAGEOFF
	bl	_dev_err
LBB0_7:
	add	x0, sp, #56
	mov	w1, #0
	mov	w2, #4
	bl	_memset
	ldr	w8, [x26]
	add	w8, w8, w8, lsl #1
	str	w8, [sp, #56]
	add	x2, sp, #56
	add	x3, sp, #40
	mov	x0, x20
	mov	x1, x21
	bl	_tegra_sor_compute_config
	tbz	w0, #31, LBB0_9
; %bb.8:
	mov	x2, x0
	ldr	w0, [x20]
Lloh4:
	adrp	x1, l_.str.3@PAGE
Lloh5:
	add	x1, x1, l_.str.3@PAGEOFF
	bl	_dev_err
LBB0_9:
	str	x21, [sp, #16]                  ; 8-byte Folded Spill
	str	x19, [sp, #32]                  ; 8-byte Folded Spill
Lloh6:
	adrp	x19, _SOR_CLK_CNTRL@GOTPAGE
Lloh7:
	ldr	x19, [x19, _SOR_CLK_CNTRL@GOTPAGEOFF]
	ldr	w1, [x19]
	mov	x0, x20
	bl	_tegra_sor_readl
Lloh8:
	adrp	x8, _SOR_CLK_CNTRL_DP_CLK_SEL_MASK@GOTPAGE
Lloh9:
	ldr	x8, [x8, _SOR_CLK_CNTRL_DP_CLK_SEL_MASK@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh11:
	adrp	x9, _SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK@GOTPAGE
Lloh12:
	ldr	x9, [x9, _SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	orr	w1, w8, w9
	ldr	w2, [x19]
	mov	x0, x20
	bl	_tegra_sor_writel
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w1, [x8, #4]
	mov	x0, x20
	bl	_tegra_sor_readl
Lloh14:
	adrp	x24, _SOR_PLL2_BANDGAP_POWERDOWN@GOTPAGE
Lloh15:
	ldr	x24, [x24, _SOR_PLL2_BANDGAP_POWERDOWN@GOTPAGEOFF]
	ldr	w8, [x24]
	bic	w1, w0, w8
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w2, [x8, #4]
	mov	x0, x20
	bl	_tegra_sor_writel
	mov	w0, #20
	mov	w1, #100
	bl	_usleep_range
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w1, [x8, #16]
	mov	x0, x20
	bl	_tegra_sor_readl
Lloh16:
	adrp	x8, _SOR_PLL3_PLL_VDD_MODE_3V3@GOTPAGE
Lloh17:
	ldr	x8, [x8, _SOR_PLL3_PLL_VDD_MODE_3V3@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w2, [x8, #16]
	mov	x0, x20
	bl	_tegra_sor_writel
	mov	w0, #15
	bl	_SOR_PLL0_ICHPMP
Lloh19:
	adrp	x8, _SOR_PLL0_VCOCAP_RST@GOTPAGE
Lloh20:
	ldr	x8, [x8, _SOR_PLL0_VCOCAP_RST@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh22:
	adrp	x9, _SOR_PLL0_PLLREG_LEVEL_V45@GOTPAGE
Lloh23:
	ldr	x9, [x9, _SOR_PLL0_PLLREG_LEVEL_V45@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
Lloh25:
	adrp	x10, _SOR_PLL0_RESISTOR_EXT@GOTPAGE
Lloh26:
	ldr	x10, [x10, _SOR_PLL0_RESISTOR_EXT@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh27:
	ldr	w9, [x10]
	orr	w1, w8, w9
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w2, [x8, #8]
	mov	x0, x20
	bl	_tegra_sor_writel
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w1, [x8, #4]
	mov	x0, x20
	bl	_tegra_sor_readl
Lloh28:
	adrp	x8, _SOR_PLL2_SEQ_PLLCAPPD@GOTPAGE
Lloh29:
	ldr	x8, [x8, _SOR_PLL2_SEQ_PLLCAPPD@GOTPAGEOFF]
Lloh30:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh31:
	adrp	x28, _SOR_PLL2_SEQ_PLLCAPPD_ENFORCE@GOTPAGE
Lloh32:
	ldr	x28, [x28, _SOR_PLL2_SEQ_PLLCAPPD_ENFORCE@GOTPAGEOFF]
	ldr	w9, [x28]
Lloh33:
	adrp	x10, _SOR_PLL2_LVDS_ENABLE@GOTPAGE
Lloh34:
	ldr	x10, [x10, _SOR_PLL2_LVDS_ENABLE@GOTPAGEOFF]
	bic	w8, w8, w9
Lloh35:
	ldr	w9, [x10]
	orr	w1, w8, w9
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w2, [x8, #4]
	mov	x0, x20
	bl	_tegra_sor_writel
Lloh36:
	adrp	x8, _SOR_PLL1_TERM_COMPOUT@GOTPAGE
Lloh37:
	ldr	x8, [x8, _SOR_PLL1_TERM_COMPOUT@GOTPAGEOFF]
Lloh38:
	adrp	x9, _SOR_PLL1_TMDS_TERM@GOTPAGE
Lloh39:
	ldr	x9, [x9, _SOR_PLL1_TMDS_TERM@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
Lloh41:
	ldr	w9, [x9]
	orr	w1, w9, w8
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w2, [x8, #12]
	mov	x0, x20
	bl	_tegra_sor_writel
LBB0_10:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w1, [x8, #4]
	mov	x0, x20
	bl	_tegra_sor_readl
	ldr	w8, [x28]
	tst	w8, w0
	b.eq	LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_10 Depth=1
	mov	w0, #250
	mov	w1, #1000
	bl	_usleep_range
	b	LBB0_10
LBB0_12:
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w1, [x8, #4]
	mov	x0, x20
	bl	_tegra_sor_readl
Lloh42:
	adrp	x8, _SOR_PLL2_POWERDOWN_OVERRIDE@GOTPAGE
Lloh43:
	ldr	x8, [x8, _SOR_PLL2_POWERDOWN_OVERRIDE@GOTPAGEOFF]
Lloh44:
	ldr	w8, [x8]
Lloh45:
	adrp	x27, _SOR_PLL2_PORT_POWERDOWN@GOTPAGE
Lloh46:
	ldr	x27, [x27, _SOR_PLL2_PORT_POWERDOWN@GOTPAGEOFF]
	ldr	w9, [x27]
	orr	w8, w9, w8
	bic	w1, w0, w8
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w2, [x8, #4]
	mov	x0, x20
	bl	_tegra_sor_writel
	ldr	w1, [x19]
	mov	x0, x20
	bl	_tegra_sor_readl
Lloh47:
	adrp	x8, _SOR_CLK_CNTRL_DP_LINK_SPEED_MASK@GOTPAGE
Lloh48:
	ldr	x8, [x8, _SOR_CLK_CNTRL_DP_LINK_SPEED_MASK@GOTPAGEOFF]
Lloh49:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh50:
	adrp	x9, _SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62@GOTPAGE
Lloh51:
	ldr	x9, [x9, _SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62@GOTPAGEOFF]
Lloh52:
	ldr	w9, [x9]
	orr	w1, w8, w9
	ldr	w2, [x19]
	mov	x0, x20
	bl	_tegra_sor_writel
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w1, [x8, #4]
	mov	x0, x20
	bl	_tegra_sor_readl
	ldr	w8, [x28]
	ldr	w9, [x27]
	ldr	w10, [x24]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w1, w8, w10
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w2, [x8, #4]
	mov	x0, x20
	bl	_tegra_sor_writel
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w1, [x8, #8]
	mov	x0, x20
	bl	_tegra_sor_readl
Lloh53:
	adrp	x21, _SOR_PLL0_VCOPD@GOTPAGE
Lloh54:
	ldr	x21, [x21, _SOR_PLL0_VCOPD@GOTPAGEOFF]
	ldr	w8, [x21]
Lloh55:
	adrp	x22, _SOR_PLL0_PWR@GOTPAGE
Lloh56:
	ldr	x22, [x22, _SOR_PLL0_PWR@GOTPAGEOFF]
	ldr	w9, [x22]
	orr	w8, w8, w0
	orr	w1, w8, w9
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w2, [x8, #8]
	mov	x0, x20
	bl	_tegra_sor_writel
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w1, [x8]
	mov	x0, x20
	bl	_tegra_sor_readl
Lloh57:
	adrp	x25, _SOR_DP_PADCTL_PAD_CAL_PD@GOTPAGE
Lloh58:
	ldr	x25, [x25, _SOR_DP_PADCTL_PAD_CAL_PD@GOTPAGEOFF]
	ldr	w8, [x25]
	bic	w1, w0, w8
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w2, [x8]
	mov	x0, x20
	bl	_tegra_sor_writel
	ldr	w0, [x20, #32]
	bl	_tegra_io_pad_power_enable
	tbz	w0, #31, LBB0_14
; %bb.13:
	mov	x2, x0
	ldr	w0, [x20]
Lloh59:
	adrp	x1, l_.str.4@PAGE
Lloh60:
	add	x1, x1, l_.str.4@PAGEOFF
	bl	_dev_err
LBB0_14:
	mov	w0, #5
	mov	w1, #100
	bl	_usleep_range
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w1, [x8, #4]
	mov	x0, x20
	bl	_tegra_sor_readl
	ldr	w8, [x24]
	bic	w1, w0, w8
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w2, [x8, #4]
	mov	x0, x20
	bl	_tegra_sor_writel
	mov	w0, #20
	mov	w1, #100
	bl	_usleep_range
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w1, [x8, #8]
	mov	x0, x20
	bl	_tegra_sor_readl
	ldr	w8, [x21]
	ldr	w9, [x22]
	orr	w8, w9, w8
	bic	w1, w0, w8
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w2, [x8, #8]
	mov	x0, x20
	bl	_tegra_sor_writel
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w1, [x8, #4]
	mov	x0, x20
	bl	_tegra_sor_readl
	ldr	w8, [x28]
	bic	w1, w0, w8
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w2, [x8, #4]
	mov	x0, x20
	bl	_tegra_sor_writel
	mov	w0, #200
	mov	w1, #1000
	bl	_usleep_range
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w1, [x8, #4]
	mov	x0, x20
	bl	_tegra_sor_readl
	ldr	w8, [x27]
	bic	w1, w0, w8
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w2, [x8, #4]
	mov	x0, x20
	bl	_tegra_sor_writel
	ldr	x8, [x20, #24]
	ldr	w1, [x8]
	mov	w0, #0
	bl	_SOR_XBAR_CTRL_LINK0_XSEL
	mov	x24, x0
	mov	w0, #0
	mov	w1, #0
	bl	_SOR_XBAR_CTRL_LINK1_XSEL
	orr	w21, w24, w0
	ldr	x8, [x20, #24]
	ldr	w1, [x8, #4]
	mov	w0, #1
	bl	_SOR_XBAR_CTRL_LINK0_XSEL
	mov	x24, x0
	mov	w0, #1
	mov	w1, #1
	bl	_SOR_XBAR_CTRL_LINK1_XSEL
	orr	w8, w24, w21
	orr	w21, w8, w0
	ldr	x8, [x20, #24]
	ldr	w1, [x8, #8]
	mov	w0, #2
	bl	_SOR_XBAR_CTRL_LINK0_XSEL
	mov	x24, x0
	mov	w0, #2
	mov	w1, #2
	bl	_SOR_XBAR_CTRL_LINK1_XSEL
	orr	w8, w24, w21
	orr	w21, w8, w0
	ldr	x8, [x20, #24]
	ldr	w1, [x8, #12]
	mov	w0, #3
	bl	_SOR_XBAR_CTRL_LINK0_XSEL
	mov	x24, x0
	mov	w0, #3
	mov	w1, #3
	bl	_SOR_XBAR_CTRL_LINK1_XSEL
	orr	w8, w24, w21
	orr	w21, w8, w0
	ldr	x8, [x20, #24]
	ldr	w1, [x8, #16]
	mov	w0, #4
	bl	_SOR_XBAR_CTRL_LINK0_XSEL
	mov	x24, x0
	mov	w0, #4
	mov	w1, #4
	bl	_SOR_XBAR_CTRL_LINK1_XSEL
	orr	w8, w24, w21
	orr	w24, w8, w0
Lloh61:
	adrp	x8, _SOR_XBAR_POL@GOTPAGE
Lloh62:
	ldr	x8, [x8, _SOR_XBAR_POL@GOTPAGEOFF]
Lloh63:
	ldr	w2, [x8]
	mov	x0, x20
	mov	w1, #0
	bl	_tegra_sor_writel
Lloh64:
	adrp	x8, _SOR_XBAR_CTRL@GOTPAGE
Lloh65:
	ldr	x8, [x8, _SOR_XBAR_CTRL@GOTPAGEOFF]
Lloh66:
	ldr	w2, [x8]
	mov	x0, x20
	mov	x1, x24
	bl	_tegra_sor_writel
	ldr	w1, [x20, #16]
	mov	x0, x20
	bl	_tegra_sor_set_parent_clock
	tbz	w0, #31, LBB0_16
; %bb.15:
	mov	x2, x0
	ldr	w0, [x20]
Lloh67:
	adrp	x1, l_.str.5@PAGE
Lloh68:
	add	x1, x1, l_.str.5@PAGEOFF
	bl	_dev_err
LBB0_16:
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w1, [x8]
	mov	x0, x20
	bl	_tegra_sor_readl
Lloh69:
	adrp	x9, _SOR_DP_PADCTL_PD_TXD_3@GOTPAGE
Lloh70:
	ldr	x9, [x9, _SOR_DP_PADCTL_PD_TXD_3@GOTPAGEOFF]
	ldr	w8, [sp, #40]
Lloh71:
	ldr	w9, [x9]
Lloh72:
	adrp	x10, _SOR_DP_PADCTL_PD_TXD_2@GOTPAGE
Lloh73:
	ldr	x10, [x10, _SOR_DP_PADCTL_PD_TXD_2@GOTPAGEOFF]
Lloh74:
	ldr	w10, [x10]
	cmp	w8, #3
	b.ge	LBB0_21
; %bb.17:
	orr	w9, w10, w9
	bic	w9, w0, w9
	cmp	w8, #2
	b.eq	LBB0_22
; %bb.18:
Lloh75:
	adrp	x10, _SOR_DP_PADCTL_PD_TXD_1@GOTPAGE
Lloh76:
	ldr	x10, [x10, _SOR_DP_PADCTL_PD_TXD_1@GOTPAGEOFF]
Lloh77:
	ldr	w10, [x10]
	bic	w9, w9, w10
	cbnz	w8, LBB0_23
; %bb.19:
Lloh78:
	adrp	x8, _SOR_DP_PADCTL_PD_TXD_0@GOTPAGE
Lloh79:
	ldr	x8, [x8, _SOR_DP_PADCTL_PD_TXD_0@GOTPAGEOFF]
Lloh80:
	ldr	w8, [x8]
	bic	w1, w9, w8
	b	LBB0_24
LBB0_20:
	mov	x2, x0
	ldr	w0, [x20]
Lloh81:
	adrp	x1, l_.str.1@PAGE
Lloh82:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_err
	b	LBB0_49
LBB0_21:
	orr	w8, w9, w0
	orr	w9, w8, w10
LBB0_22:
Lloh83:
	adrp	x8, _SOR_DP_PADCTL_PD_TXD_1@GOTPAGE
Lloh84:
	ldr	x8, [x8, _SOR_DP_PADCTL_PD_TXD_1@GOTPAGEOFF]
Lloh85:
	ldr	w8, [x8]
	orr	w9, w8, w9
LBB0_23:
Lloh86:
	adrp	x8, _SOR_DP_PADCTL_PD_TXD_0@GOTPAGE
Lloh87:
	ldr	x8, [x8, _SOR_DP_PADCTL_PD_TXD_0@GOTPAGEOFF]
Lloh88:
	ldr	w8, [x8]
	orr	w1, w8, w9
LBB0_24:
	str	x26, [sp, #8]                   ; 8-byte Folded Spill
	str	x23, [sp, #24]                  ; 8-byte Folded Spill
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w2, [x8]
	mov	x0, x20
	bl	_tegra_sor_writel
Lloh89:
	adrp	x28, _SOR_DP_LINKCTL0@GOTPAGE
Lloh90:
	ldr	x28, [x28, _SOR_DP_LINKCTL0@GOTPAGEOFF]
	ldr	w1, [x28]
	mov	x0, x20
	bl	_tegra_sor_readl
Lloh91:
	adrp	x8, _SOR_DP_LINKCTL_LANE_COUNT_MASK@GOTPAGE
Lloh92:
	ldr	x8, [x8, _SOR_DP_LINKCTL_LANE_COUNT_MASK@GOTPAGEOFF]
Lloh93:
	ldr	w8, [x8]
	bic	w21, w0, w8
	ldr	w0, [sp, #40]
	bl	_SOR_DP_LINKCTL_LANE_COUNT
	orr	w1, w0, w21
	ldr	w2, [x28]
	mov	x0, x20
	bl	_tegra_sor_writel
Lloh94:
	adrp	x21, _SOR_LANE_SEQ_CTL_TRIGGER@GOTPAGE
Lloh95:
	ldr	x21, [x21, _SOR_LANE_SEQ_CTL_TRIGGER@GOTPAGEOFF]
	ldr	w8, [x21]
Lloh96:
	adrp	x9, _SOR_LANE_SEQ_CTL_SEQUENCE_DOWN@GOTPAGE
Lloh97:
	ldr	x9, [x9, _SOR_LANE_SEQ_CTL_SEQUENCE_DOWN@GOTPAGEOFF]
Lloh98:
	ldr	w9, [x9]
Lloh99:
	adrp	x10, _SOR_LANE_SEQ_CTL_POWER_STATE_UP@GOTPAGE
Lloh100:
	ldr	x10, [x10, _SOR_LANE_SEQ_CTL_POWER_STATE_UP@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh101:
	ldr	w9, [x10]
	orr	w1, w8, w9
Lloh102:
	adrp	x22, _SOR_LANE_SEQ_CTL@GOTPAGE
Lloh103:
	ldr	x22, [x22, _SOR_LANE_SEQ_CTL@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	x0, x20
	bl	_tegra_sor_writel
LBB0_25:                                ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x22]
	mov	x0, x20
	bl	_tegra_sor_readl
	ldr	w8, [x21]
	tst	w8, w0
	b.eq	LBB0_27
; %bb.26:                               ;   in Loop: Header=BB0_25 Depth=1
	mov	w0, #250
	mov	w1, #1000
	bl	_usleep_range
	b	LBB0_25
LBB0_27:
	ldr	w1, [x19]
	mov	x0, x20
	bl	_tegra_sor_readl
Lloh104:
	adrp	x23, _SOR_CLK_CNTRL_DP_LINK_SPEED_MASK@GOTPAGE
Lloh105:
	ldr	x23, [x23, _SOR_CLK_CNTRL_DP_LINK_SPEED_MASK@GOTPAGEOFF]
	ldr	w8, [x23]
	bic	w21, w0, w8
	ldr	w0, [sp, #48]
	bl	_drm_dp_link_rate_to_bw_code
	orr	w1, w21, w0, lsl #2
	ldr	w2, [x19]
	mov	x0, x20
	bl	_tegra_sor_writel
	add	x1, sp, #56
	mov	x0, x20
	bl	_tegra_sor_apply_config
	ldr	w1, [x28]
	mov	x0, x20
	bl	_tegra_sor_readl
Lloh106:
	adrp	x8, _SOR_DP_LINKCTL_ENABLE@GOTPAGE
Lloh107:
	ldr	x8, [x8, _SOR_DP_LINKCTL_ENABLE@GOTPAGEOFF]
Lloh108:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh109:
	adrp	x27, _SOR_DP_LINKCTL_ENHANCED_FRAME@GOTPAGE
Lloh110:
	ldr	x27, [x27, _SOR_DP_LINKCTL_ENHANCED_FRAME@GOTPAGEOFF]
	ldr	w9, [x27]
	orr	w1, w8, w9
	ldr	w2, [x28]
	mov	x0, x20
	bl	_tegra_sor_writel
Lloh111:
	adrp	x8, _SOR_DP_TPG_CHANNEL_CODING@GOTPAGE
Lloh112:
	ldr	x8, [x8, _SOR_DP_TPG_CHANNEL_CODING@GOTPAGEOFF]
Lloh113:
	ldr	w8, [x8]
Lloh114:
	adrp	x21, _SOR_DP_TPG_SCRAMBLER_GALIOS@GOTPAGE
Lloh115:
	ldr	x21, [x21, _SOR_DP_TPG_SCRAMBLER_GALIOS@GOTPAGEOFF]
	ldr	w9, [x21]
	orr	w8, w9, w8
Lloh116:
	adrp	x26, _SOR_DP_TPG_PATTERN_NONE@GOTPAGE
Lloh117:
	ldr	x26, [x26, _SOR_DP_TPG_PATTERN_NONE@GOTPAGEOFF]
	ldr	w9, [x26]
	orr	w8, w8, w9
	lsl	w9, w8, #16
	orr	w9, w9, w8, lsl #8
	orr	w9, w9, w8
	orr	w1, w8, w9, lsl #8
Lloh118:
	adrp	x22, _SOR_DP_TPG@GOTPAGE
Lloh119:
	ldr	x22, [x22, _SOR_DP_TPG@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	x0, x20
	bl	_tegra_sor_writel
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w1, [x8]
	mov	x0, x20
	bl	_tegra_sor_readl
	ldr	w8, [x25]
	orr	w1, w8, w0
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	ldr	w2, [x8]
	mov	x0, x20
	bl	_tegra_sor_writel
	ldr	w0, [x20, #4]
	add	x1, sp, #40
	bl	_drm_dp_link_probe
	tbz	w0, #31, LBB0_29
; %bb.28:
	mov	x2, x0
	ldr	w0, [x20]
Lloh120:
	adrp	x1, l_.str.1@PAGE
Lloh121:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_err
LBB0_29:
	ldr	w0, [x20, #4]
	add	x1, sp, #40
	bl	_drm_dp_link_power_up
	tbz	w0, #31, LBB0_31
; %bb.30:
	mov	x2, x0
	ldr	w0, [x20]
Lloh122:
	adrp	x1, l_.str.6@PAGE
Lloh123:
	add	x1, x1, l_.str.6@PAGEOFF
	bl	_dev_err
LBB0_31:
	ldr	w0, [x20, #4]
	add	x1, sp, #40
	bl	_drm_dp_link_configure
	tbz	w0, #31, LBB0_33
; %bb.32:
	mov	x2, x0
	ldr	w0, [x20]
Lloh124:
	adrp	x1, l_.str.7@PAGE
Lloh125:
	add	x1, x1, l_.str.7@PAGEOFF
	bl	_dev_err
LBB0_33:
	ldr	w0, [sp, #48]
	bl	_drm_dp_link_rate_to_bw_code
	mov	x24, x0
	ldr	w25, [sp, #40]
	ldr	w1, [x19]
	mov	x0, x20
	bl	_tegra_sor_readl
	ldr	w8, [x23]
	mov	x23, x19
	bic	w19, w0, w8
	mov	x0, x24
	bl	_SOR_CLK_CNTRL_DP_LINK_SPEED
	orr	w1, w19, w0
	ldr	w2, [x23]
	mov	x0, x20
	bl	_tegra_sor_writel
	ldr	w1, [x28]
	mov	x0, x20
	bl	_tegra_sor_readl
Lloh126:
	adrp	x8, _SOR_DP_LINKCTL_LANE_COUNT_MASK@GOTPAGE
Lloh127:
	ldr	x8, [x8, _SOR_DP_LINKCTL_LANE_COUNT_MASK@GOTPAGEOFF]
Lloh128:
	ldr	w8, [x8]
	bic	w19, w0, w8
	mov	x0, x25
	bl	_SOR_DP_LINKCTL_LANE_COUNT
	orr	w8, w19, w0
	ldr	w9, [sp, #44]
Lloh129:
	adrp	x10, _DP_LINK_CAP_ENHANCED_FRAMING@GOTPAGE
Lloh130:
	ldr	x10, [x10, _DP_LINK_CAP_ENHANCED_FRAMING@GOTPAGEOFF]
Lloh131:
	ldr	w10, [x10]
	ldr	w11, [x27]
	tst	w10, w9
	csel	w9, wzr, w11, eq
	orr	w24, w8, w9
	ldr	w2, [x28]
	mov	x0, x20
	mov	x1, x24
	bl	_tegra_sor_writel
	ldr	w8, [sp, #40]
	cbz	w8, LBB0_36
; %bb.34:
Lloh132:
	adrp	x9, _SOR_DP_TPG_CHANNEL_CODING@GOTPAGE
Lloh133:
	ldr	x9, [x9, _SOR_DP_TPG_CHANNEL_CODING@GOTPAGEOFF]
Lloh134:
	ldr	w9, [x9]
	ldr	w10, [x21]
	orr	w9, w10, w9
	ldr	w10, [x26]
	orr	w9, w9, w10
	ldp	x23, x21, [sp, #24]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #8]              ; 16-byte Folded Reload
LBB0_35:                                ; =>This Inner Loop Header: Depth=1
	orr	w24, w9, w24, lsl #8
	subs	w8, w8, #1
	b.ne	LBB0_35
	b	LBB0_37
LBB0_36:
	ldp	x23, x21, [sp, #24]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #8]              ; 16-byte Folded Reload
LBB0_37:
	ldr	w2, [x22]
	mov	x0, x20
	mov	x1, x24
	bl	_tegra_sor_writel
	add	x1, sp, #40
	mov	x0, x20
	bl	_tegra_sor_dp_train_fast
	tbz	w0, #31, LBB0_39
; %bb.38:
	mov	x2, x0
	ldr	w0, [x20]
Lloh135:
	adrp	x1, l_.str.8@PAGE
Lloh136:
	add	x1, x1, l_.str.8@PAGEOFF
	bl	_dev_err
LBB0_39:
	ldr	w0, [x20]
Lloh137:
	adrp	x1, l_.str.9@PAGE
Lloh138:
	add	x1, x1, l_.str.9@PAGEOFF
	bl	_dev_dbg
	mov	x0, x20
	mov	w1, #250
	bl	_tegra_sor_power_up
	tbz	w0, #31, LBB0_41
; %bb.40:
	mov	x2, x0
	ldr	w0, [x20]
Lloh139:
	adrp	x1, l_.str.10@PAGE
Lloh140:
	add	x1, x1, l_.str.10@PAGEOFF
	bl	_dev_err
LBB0_41:
Lloh141:
	adrp	x8, _SOR_CSTM_LVDS@GOTPAGE
Lloh142:
	ldr	x8, [x8, _SOR_CSTM_LVDS@GOTPAGEOFF]
Lloh143:
	ldr	w8, [x8]
Lloh144:
	adrp	x9, _SOR_CSTM_LINK_ACT_A@GOTPAGE
Lloh145:
	ldr	x9, [x9, _SOR_CSTM_LINK_ACT_A@GOTPAGEOFF]
Lloh146:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh147:
	adrp	x9, _SOR_CSTM_LINK_ACT_B@GOTPAGE
Lloh148:
	ldr	x9, [x9, _SOR_CSTM_LINK_ACT_B@GOTPAGEOFF]
Lloh149:
	ldr	w9, [x9]
Lloh150:
	adrp	x10, _SOR_CSTM_UPPER@GOTPAGE
Lloh151:
	ldr	x10, [x10, _SOR_CSTM_UPPER@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh152:
	ldr	w9, [x10]
	orr	w1, w8, w9
Lloh153:
	adrp	x8, _SOR_CSTM@GOTPAGE
Lloh154:
	ldr	x8, [x8, _SOR_CSTM@GOTPAGEOFF]
Lloh155:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_tegra_sor_writel
Lloh156:
	adrp	x19, _SOR_STATE1@GOTPAGE
Lloh157:
	ldr	x19, [x19, _SOR_STATE1@GOTPAGEOFF]
	ldr	w1, [x19]
	mov	x0, x20
	bl	_tegra_sor_readl
Lloh158:
	adrp	x8, _SOR_STATE_ASY_PROTOCOL_MASK@GOTPAGE
Lloh159:
	ldr	x8, [x8, _SOR_STATE_ASY_PROTOCOL_MASK@GOTPAGEOFF]
Lloh160:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh161:
	adrp	x9, _SOR_STATE_ASY_PROTOCOL_DP_A@GOTPAGE
Lloh162:
	ldr	x9, [x9, _SOR_STATE_ASY_PROTOCOL_DP_A@GOTPAGEOFF]
Lloh163:
	ldr	w9, [x9]
	orr	w1, w8, w9
	ldr	w2, [x19]
	mov	x0, x20
	bl	_tegra_sor_writel
	mov	x0, x20
	mov	x1, x25
	mov	x2, x26
	bl	_tegra_sor_mode_set
	mov	x0, x20
	mov	w1, #250
	bl	_tegra_sor_setup_pwm
	tbz	w0, #31, LBB0_43
; %bb.42:
	mov	x2, x0
	ldr	w0, [x20]
Lloh164:
	adrp	x1, l_.str.11@PAGE
Lloh165:
	add	x1, x1, l_.str.11@PAGEOFF
	bl	_dev_err
LBB0_43:
	mov	x0, x20
	bl	_tegra_sor_update
Lloh166:
	adrp	x19, _DC_DISP_DISP_WIN_OPTIONS@GOTPAGE
Lloh167:
	ldr	x19, [x19, _DC_DISP_DISP_WIN_OPTIONS@GOTPAGEOFF]
	ldr	w1, [x19]
	mov	x0, x23
	bl	_tegra_dc_readl
	mov	x22, x0
	mov	w0, #0
	bl	_SOR_ENABLE
	orr	w1, w0, w22
	ldr	w2, [x19]
	mov	x0, x23
	bl	_tegra_dc_writel
	mov	x0, x23
	bl	_tegra_dc_commit
	mov	x0, x20
	bl	_tegra_sor_attach
	tbz	w0, #31, LBB0_45
; %bb.44:
	mov	x2, x0
	ldr	w0, [x20]
Lloh168:
	adrp	x1, l_.str.12@PAGE
Lloh169:
	add	x1, x1, l_.str.12@PAGEOFF
	bl	_dev_err
LBB0_45:
	mov	x0, x20
	bl	_tegra_sor_wakeup
	tbz	w0, #31, LBB0_47
; %bb.46:
	mov	x2, x0
	ldr	w0, [x20]
Lloh170:
	adrp	x1, l_.str.13@PAGE
Lloh171:
	add	x1, x1, l_.str.13@PAGEOFF
	bl	_dev_err
LBB0_47:
	ldr	x0, [x21]
	cbz	x0, LBB0_49
; %bb.48:
	bl	_drm_panel_enable
LBB0_49:
	ldp	x29, x30, [sp, #144]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #128]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #112]            ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #96]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #80]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #64]             ; 16-byte Folded Reload
	add	sp, sp, #160
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh40
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpAdd	Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpAdd	Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpAdd	Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGot	Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGot	Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGot	Lloh89, Lloh90
	.loh AdrpLdrGot	Lloh118, Lloh119
	.loh AdrpLdrGot	Lloh116, Lloh117
	.loh AdrpLdrGot	Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGot	Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGot	Lloh104, Lloh105
	.loh AdrpAdd	Lloh120, Lloh121
	.loh AdrpAdd	Lloh122, Lloh123
	.loh AdrpAdd	Lloh124, Lloh125
	.loh AdrpLdrGotLdr	Lloh129, Lloh130, Lloh131
	.loh AdrpLdrGotLdr	Lloh126, Lloh127, Lloh128
	.loh AdrpLdrGotLdr	Lloh132, Lloh133, Lloh134
	.loh AdrpAdd	Lloh135, Lloh136
	.loh AdrpAdd	Lloh137, Lloh138
	.loh AdrpAdd	Lloh139, Lloh140
	.loh AdrpLdrGotLdr	Lloh161, Lloh162, Lloh163
	.loh AdrpLdrGotLdr	Lloh158, Lloh159, Lloh160
	.loh AdrpLdrGot	Lloh156, Lloh157
	.loh AdrpLdrGotLdr	Lloh153, Lloh154, Lloh155
	.loh AdrpLdrGotLdr	Lloh150, Lloh151, Lloh152
	.loh AdrpLdrGotLdr	Lloh147, Lloh148, Lloh149
	.loh AdrpLdrGotLdr	Lloh144, Lloh145, Lloh146
	.loh AdrpLdrGotLdr	Lloh141, Lloh142, Lloh143
	.loh AdrpAdd	Lloh164, Lloh165
	.loh AdrpLdrGot	Lloh166, Lloh167
	.loh AdrpAdd	Lloh168, Lloh169
	.loh AdrpAdd	Lloh170, Lloh171
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"failed to enable DP: %d\n"

l_.str.1:                               ; @.str.1
	.asciz	"failed to probe eDP link: %d\n"

l_.str.2:                               ; @.str.2
	.asciz	"failed to set safe parent clock: %d\n"

l_.str.3:                               ; @.str.3
	.asciz	"failed to compute configuration: %d\n"

	.comm	_SOR_CLK_CNTRL,4,2              ; @SOR_CLK_CNTRL
	.comm	_SOR_CLK_CNTRL_DP_CLK_SEL_MASK,4,2 ; @SOR_CLK_CNTRL_DP_CLK_SEL_MASK
	.comm	_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK,4,2 ; @SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK
	.comm	_SOR_PLL2_BANDGAP_POWERDOWN,4,2 ; @SOR_PLL2_BANDGAP_POWERDOWN
	.comm	_SOR_PLL3_PLL_VDD_MODE_3V3,4,2  ; @SOR_PLL3_PLL_VDD_MODE_3V3
	.comm	_SOR_PLL0_VCOCAP_RST,4,2        ; @SOR_PLL0_VCOCAP_RST
	.comm	_SOR_PLL0_PLLREG_LEVEL_V45,4,2  ; @SOR_PLL0_PLLREG_LEVEL_V45
	.comm	_SOR_PLL0_RESISTOR_EXT,4,2      ; @SOR_PLL0_RESISTOR_EXT
	.comm	_SOR_PLL2_SEQ_PLLCAPPD,4,2      ; @SOR_PLL2_SEQ_PLLCAPPD
	.comm	_SOR_PLL2_SEQ_PLLCAPPD_ENFORCE,4,2 ; @SOR_PLL2_SEQ_PLLCAPPD_ENFORCE
	.comm	_SOR_PLL2_LVDS_ENABLE,4,2       ; @SOR_PLL2_LVDS_ENABLE
	.comm	_SOR_PLL1_TERM_COMPOUT,4,2      ; @SOR_PLL1_TERM_COMPOUT
	.comm	_SOR_PLL1_TMDS_TERM,4,2         ; @SOR_PLL1_TMDS_TERM
	.comm	_SOR_PLL2_POWERDOWN_OVERRIDE,4,2 ; @SOR_PLL2_POWERDOWN_OVERRIDE
	.comm	_SOR_PLL2_PORT_POWERDOWN,4,2    ; @SOR_PLL2_PORT_POWERDOWN
	.comm	_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK,4,2 ; @SOR_CLK_CNTRL_DP_LINK_SPEED_MASK
	.comm	_SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62,4,2 ; @SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62
	.comm	_SOR_PLL0_VCOPD,4,2             ; @SOR_PLL0_VCOPD
	.comm	_SOR_PLL0_PWR,4,2               ; @SOR_PLL0_PWR
	.comm	_SOR_DP_PADCTL_PAD_CAL_PD,4,2   ; @SOR_DP_PADCTL_PAD_CAL_PD
l_.str.4:                               ; @.str.4
	.asciz	"failed to power on I/O pad: %d\n"

	.comm	_SOR_XBAR_POL,4,2               ; @SOR_XBAR_POL
	.comm	_SOR_XBAR_CTRL,4,2              ; @SOR_XBAR_CTRL
l_.str.5:                               ; @.str.5
	.asciz	"failed to set parent clock: %d\n"

	.comm	_SOR_DP_PADCTL_PD_TXD_3,4,2     ; @SOR_DP_PADCTL_PD_TXD_3
	.comm	_SOR_DP_PADCTL_PD_TXD_2,4,2     ; @SOR_DP_PADCTL_PD_TXD_2
	.comm	_SOR_DP_PADCTL_PD_TXD_1,4,2     ; @SOR_DP_PADCTL_PD_TXD_1
	.comm	_SOR_DP_PADCTL_PD_TXD_0,4,2     ; @SOR_DP_PADCTL_PD_TXD_0
	.comm	_SOR_DP_LINKCTL0,4,2            ; @SOR_DP_LINKCTL0
	.comm	_SOR_DP_LINKCTL_LANE_COUNT_MASK,4,2 ; @SOR_DP_LINKCTL_LANE_COUNT_MASK
	.comm	_SOR_LANE_SEQ_CTL_TRIGGER,4,2   ; @SOR_LANE_SEQ_CTL_TRIGGER
	.comm	_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN,4,2 ; @SOR_LANE_SEQ_CTL_SEQUENCE_DOWN
	.comm	_SOR_LANE_SEQ_CTL_POWER_STATE_UP,4,2 ; @SOR_LANE_SEQ_CTL_POWER_STATE_UP
	.comm	_SOR_LANE_SEQ_CTL,4,2           ; @SOR_LANE_SEQ_CTL
	.comm	_SOR_DP_LINKCTL_ENABLE,4,2      ; @SOR_DP_LINKCTL_ENABLE
	.comm	_SOR_DP_LINKCTL_ENHANCED_FRAME,4,2 ; @SOR_DP_LINKCTL_ENHANCED_FRAME
	.comm	_SOR_DP_TPG_CHANNEL_CODING,8,3  ; @SOR_DP_TPG_CHANNEL_CODING
	.comm	_SOR_DP_TPG_SCRAMBLER_GALIOS,8,3 ; @SOR_DP_TPG_SCRAMBLER_GALIOS
	.comm	_SOR_DP_TPG_PATTERN_NONE,8,3    ; @SOR_DP_TPG_PATTERN_NONE
	.comm	_SOR_DP_TPG,4,2                 ; @SOR_DP_TPG
l_.str.6:                               ; @.str.6
	.asciz	"failed to power up eDP link: %d\n"

l_.str.7:                               ; @.str.7
	.asciz	"failed to configure eDP link: %d\n"

	.comm	_DP_LINK_CAP_ENHANCED_FRAMING,4,2 ; @DP_LINK_CAP_ENHANCED_FRAMING
l_.str.8:                               ; @.str.8
	.asciz	"DP fast link training failed: %d\n"

l_.str.9:                               ; @.str.9
	.asciz	"fast link training succeeded\n"

l_.str.10:                              ; @.str.10
	.asciz	"failed to power up SOR: %d\n"

	.comm	_SOR_CSTM_LVDS,4,2              ; @SOR_CSTM_LVDS
	.comm	_SOR_CSTM_LINK_ACT_A,4,2        ; @SOR_CSTM_LINK_ACT_A
	.comm	_SOR_CSTM_LINK_ACT_B,4,2        ; @SOR_CSTM_LINK_ACT_B
	.comm	_SOR_CSTM_UPPER,4,2             ; @SOR_CSTM_UPPER
	.comm	_SOR_CSTM,4,2                   ; @SOR_CSTM
	.comm	_SOR_STATE1,4,2                 ; @SOR_STATE1
	.comm	_SOR_STATE_ASY_PROTOCOL_MASK,4,2 ; @SOR_STATE_ASY_PROTOCOL_MASK
	.comm	_SOR_STATE_ASY_PROTOCOL_DP_A,4,2 ; @SOR_STATE_ASY_PROTOCOL_DP_A
l_.str.11:                              ; @.str.11
	.asciz	"failed to setup PWM: %d\n"

	.comm	_DC_DISP_DISP_WIN_OPTIONS,4,2   ; @DC_DISP_DISP_WIN_OPTIONS
l_.str.12:                              ; @.str.12
	.asciz	"failed to attach SOR: %d\n"

l_.str.13:                              ; @.str.13
	.asciz	"failed to enable DC: %d\n"

	.no_dead_strip	_tegra_sor_edp_enable
.subsections_via_symbols
