	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function sdma_v5_0_set_trap_irq_state
_sdma_v5_0_set_trap_irq_state:          ## @sdma_v5_0_set_trap_irq_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	_AMDGPU_SDMA_IRQ_INSTANCE0@GOTPCREL(%rip), %rax
	xorl	%esi, %esi
	cmpl	%edx, (%rax)
	movl	%ecx, %r14d
	setne	%sil
	movq	_mmSDMA0_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_sdma_v5_0_get_reg_offset
	movl	%eax, %ebx
	movl	%eax, %edi
	callq	_RREG32
	movq	_SDMA0_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_TRAP_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_AMDGPU_IRQ_STATE_ENABLE@GOTPCREL(%rip), %rdi
	xorl	%ecx, %ecx
	cmpl	%r14d, (%rdi)
	sete	%cl
	movl	%eax, %edi
	callq	_REG_SET_FIELD
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	xorl	%eax, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_SDMA_IRQ_INSTANCE0,4,2  ## @AMDGPU_SDMA_IRQ_INSTANCE0
	.comm	_mmSDMA0_CNTL,4,2               ## @mmSDMA0_CNTL
	.comm	_SDMA0_CNTL,4,2                 ## @SDMA0_CNTL
	.comm	_TRAP_ENABLE,4,2                ## @TRAP_ENABLE
	.comm	_AMDGPU_IRQ_STATE_ENABLE,4,2    ## @AMDGPU_IRQ_STATE_ENABLE
	.no_dead_strip	_sdma_v5_0_set_trap_irq_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function sdma_v5_0_set_trap_irq_state
_sdma_v5_0_set_trap_irq_state:          ; @sdma_v5_0_set_trap_irq_state
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x3
Lloh0:
	adrp	x8, _AMDGPU_SDMA_IRQ_INSTANCE0@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPU_SDMA_IRQ_INSTANCE0@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cmp	w8, w2
	cset	w1, ne
Lloh3:
	adrp	x8, _mmSDMA0_CNTL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _mmSDMA0_CNTL@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	bl	_sdma_v5_0_get_reg_offset
	mov	x20, x0
	bl	_RREG32
Lloh6:
	adrp	x8, _SDMA0_CNTL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _SDMA0_CNTL@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
Lloh9:
	adrp	x8, _TRAP_ENABLE@GOTPAGE
Lloh10:
	ldr	x8, [x8, _TRAP_ENABLE@GOTPAGEOFF]
Lloh11:
	ldr	w2, [x8]
Lloh12:
	adrp	x8, _AMDGPU_IRQ_STATE_ENABLE@GOTPAGE
Lloh13:
	ldr	x8, [x8, _AMDGPU_IRQ_STATE_ENABLE@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	cmp	w8, w19
	cset	w3, eq
	bl	_REG_SET_FIELD
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
	mov	w0, #0
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_SDMA_IRQ_INSTANCE0,4,2  ; @AMDGPU_SDMA_IRQ_INSTANCE0
	.comm	_mmSDMA0_CNTL,4,2               ; @mmSDMA0_CNTL
	.comm	_SDMA0_CNTL,4,2                 ; @SDMA0_CNTL
	.comm	_TRAP_ENABLE,4,2                ; @TRAP_ENABLE
	.comm	_AMDGPU_IRQ_STATE_ENABLE,4,2    ; @AMDGPU_IRQ_STATE_ENABLE
	.no_dead_strip	_sdma_v5_0_set_trap_irq_state
.subsections_via_symbols
