	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v9_0_ring_emit_fence_kiq
_gfx_v9_0_ring_emit_fence_kiq:          ## @gfx_v9_0_ring_emit_fence_kiq
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %r14d
	movl	%edx, %r15d
	movl	%esi, %r12d
	movq	%rdi, %r13
	movq	_AMDGPU_FENCE_FLAG_64BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	andl	%ecx, %edi
	callq	_BUG_ON
	movq	_PACKET3_WRITE_DATA@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$3, %esi
	callq	_PACKET3
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	xorl	%edi, %edi
	callq	_WRITE_DATA_ENGINE_SEL
	movl	%eax, %ebx
	movl	$5, %edi
	callq	_WRITE_DATA_DST_SEL
	orl	%eax, %ebx
	movq	_WR_CONFIRM@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_amdgpu_ring_write
	movl	%r12d, %edi
	callq	_lower_32_bits
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	%r12d, %edi
	callq	_upper_32_bits
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	%r15d, %edi
	callq	_lower_32_bits
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_AMDGPU_FENCE_FLAG_INT@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_1
## %bb.2:
	movq	_PACKET3_WRITE_DATA@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$3, %esi
	callq	_PACKET3
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	xorl	%edi, %edi
	callq	_WRITE_DATA_ENGINE_SEL
	movl	%eax, %ebx
	xorl	%edi, %edi
	callq	_WRITE_DATA_DST_SEL
	orl	%eax, %ebx
	movq	_WR_CONFIRM@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_amdgpu_ring_write
	movq	_GC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmCPC_INT_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
	movq	%r13, %rdi
	movl	$536870912, %esi                ## imm = 0x20000000
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_write              ## TAILCALL
LBB0_1:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_FENCE_FLAG_64BIT,4,2    ## @AMDGPU_FENCE_FLAG_64BIT
	.comm	_PACKET3_WRITE_DATA,4,2         ## @PACKET3_WRITE_DATA
	.comm	_WR_CONFIRM,4,2                 ## @WR_CONFIRM
	.comm	_AMDGPU_FENCE_FLAG_INT,4,2      ## @AMDGPU_FENCE_FLAG_INT
	.comm	_GC,4,2                         ## @GC
	.comm	_mmCPC_INT_STATUS,4,2           ## @mmCPC_INT_STATUS
	.no_dead_strip	_gfx_v9_0_ring_emit_fence_kiq
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v9_0_ring_emit_fence_kiq
_gfx_v9_0_ring_emit_fence_kiq:          ; @gfx_v9_0_ring_emit_fence_kiq
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x3
	mov	x21, x2
	mov	x22, x1
	mov	x19, x0
Lloh0:
	adrp	x8, _AMDGPU_FENCE_FLAG_64BIT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPU_FENCE_FLAG_64BIT@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	and	w0, w8, w3
	bl	_BUG_ON
Lloh3:
	adrp	x24, _PACKET3_WRITE_DATA@GOTPAGE
Lloh4:
	ldr	x24, [x24, _PACKET3_WRITE_DATA@GOTPAGEOFF]
	ldr	w0, [x24]
	mov	w1, #3
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	w0, #0
	bl	_WRITE_DATA_ENGINE_SEL
	mov	x23, x0
	mov	w0, #5
	bl	_WRITE_DATA_DST_SEL
	orr	w8, w0, w23
Lloh5:
	adrp	x23, _WR_CONFIRM@GOTPAGE
Lloh6:
	ldr	x23, [x23, _WR_CONFIRM@GOTPAGEOFF]
	ldr	w9, [x23]
	orr	w1, w8, w9
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x22
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x22
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x21
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh7:
	adrp	x8, _AMDGPU_FENCE_FLAG_INT@GOTPAGE
Lloh8:
	ldr	x8, [x8, _AMDGPU_FENCE_FLAG_INT@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_2
; %bb.1:
	ldr	w0, [x24]
	mov	w1, #3
	bl	_PACKET3
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	w0, #0
	bl	_WRITE_DATA_ENGINE_SEL
	mov	x20, x0
	mov	w0, #0
	bl	_WRITE_DATA_DST_SEL
	orr	w8, w0, w20
	ldr	w9, [x23]
	orr	w1, w8, w9
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh10:
	adrp	x8, _GC@GOTPAGE
Lloh11:
	ldr	x8, [x8, _GC@GOTPAGEOFF]
Lloh12:
	ldr	w0, [x8]
Lloh13:
	adrp	x8, _mmCPC_INT_STATUS@GOTPAGE
Lloh14:
	ldr	x8, [x8, _mmCPC_INT_STATUS@GOTPAGEOFF]
Lloh15:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #536870912
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_amdgpu_ring_write
LBB0_2:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_FENCE_FLAG_64BIT,4,2    ; @AMDGPU_FENCE_FLAG_64BIT
	.comm	_PACKET3_WRITE_DATA,4,2         ; @PACKET3_WRITE_DATA
	.comm	_WR_CONFIRM,4,2                 ; @WR_CONFIRM
	.comm	_AMDGPU_FENCE_FLAG_INT,4,2      ; @AMDGPU_FENCE_FLAG_INT
	.comm	_GC,4,2                         ; @GC
	.comm	_mmCPC_INT_STATUS,4,2           ; @mmCPC_INT_STATUS
	.no_dead_strip	_gfx_v9_0_ring_emit_fence_kiq
.subsections_via_symbols
