	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v6_0_cp_compute_resume
_gfx_v6_0_cp_compute_resume:            ## @gfx_v6_0_cp_compute_resume
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	(%rdi), %r13
	movl	(%r13), %eax
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	callq	_order_base_2
	movl	%eax, %r15d
	movq	_AMDGPU_GPU_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	callq	_order_base_2
	shll	$8, %eax
	orl	%eax, %r15d
	movq	_mmCP_RB1_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movl	(%rbx), %edi
	movq	_CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	%r15d, %esi
	callq	_WREG32
	movl	$0, 4(%r13)
	movq	_mmCP_RB1_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movslq	8(%r13), %rbx
	shlq	$2, %rbx
	addq	8(%r14), %rbx
	movq	_mmCP_RB1_RPTR_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	%rbx, %rdi
	callq	_lower_32_bits
	movl	%r12d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmCP_RB1_RPTR_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	%rbx, %rdi
	callq	_upper_32_bits
	movzbl	%al, %esi
	movl	%r12d, %edi
	callq	_WREG32
	movl	$1, %edi
	callq	_mdelay
	movq	_mmCP_RB1_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movq	_mmCP_RB1_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	12(%r13), %esi
	sarl	$8, %esi
	callq	_WREG32
	movq	(%r14), %r13
	movl	16(%r13), %eax
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	callq	_order_base_2
	movl	%eax, %r15d
	movq	_AMDGPU_GPU_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	callq	_order_base_2
	shll	$8, %eax
	orl	%eax, %r15d
	movq	_mmCP_RB2_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movl	(%rbx), %edi
	movq	_CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	%r15d, %esi
	callq	_WREG32
	movl	$0, 20(%r13)
	movq	_mmCP_RB2_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movslq	24(%r13), %rbx
	shlq	$2, %rbx
	addq	8(%r14), %rbx
	movq	_mmCP_RB2_RPTR_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	%rbx, %rdi
	callq	_lower_32_bits
	movl	%r12d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmCP_RB2_RPTR_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	%rbx, %rdi
	callq	_upper_32_bits
	movzbl	%al, %esi
	movl	%r12d, %edi
	callq	_WREG32
	movl	$1, %edi
	callq	_mdelay
	movq	_mmCP_RB2_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movq	_mmCP_RB2_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	28(%r13), %esi
	sarl	$8, %esi
	callq	_WREG32
	movq	(%r14), %rdi
	callq	_amdgpu_ring_test_helper
	testl	%eax, %eax
	je	LBB0_2
## %bb.1:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	movq	(%r14), %rdi
	addq	$16, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_test_helper        ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_GPU_PAGE_SIZE,4,2       ## @AMDGPU_GPU_PAGE_SIZE
	.comm	_mmCP_RB1_CNTL,4,2              ## @mmCP_RB1_CNTL
	.comm	_CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK,4,2 ## @CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK
	.comm	_mmCP_RB1_WPTR,4,2              ## @mmCP_RB1_WPTR
	.comm	_mmCP_RB1_RPTR_ADDR,4,2         ## @mmCP_RB1_RPTR_ADDR
	.comm	_mmCP_RB1_RPTR_ADDR_HI,4,2      ## @mmCP_RB1_RPTR_ADDR_HI
	.comm	_mmCP_RB1_BASE,4,2              ## @mmCP_RB1_BASE
	.comm	_mmCP_RB2_CNTL,4,2              ## @mmCP_RB2_CNTL
	.comm	_CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK,4,2 ## @CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK
	.comm	_mmCP_RB2_WPTR,4,2              ## @mmCP_RB2_WPTR
	.comm	_mmCP_RB2_RPTR_ADDR,4,2         ## @mmCP_RB2_RPTR_ADDR
	.comm	_mmCP_RB2_RPTR_ADDR_HI,4,2      ## @mmCP_RB2_RPTR_ADDR_HI
	.comm	_mmCP_RB2_BASE,4,2              ## @mmCP_RB2_BASE
	.comm	_BUF_SWAP_32BIT,4,2             ## @BUF_SWAP_32BIT
	.no_dead_strip	_gfx_v6_0_cp_compute_resume
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v6_0_cp_compute_resume
_gfx_v6_0_cp_compute_resume:            ; @gfx_v6_0_cp_compute_resume
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldr	x24, [x0]
	ldr	w8, [x24]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #3
	bl	_order_base_2
	mov	x20, x0
Lloh0:
	adrp	x23, _AMDGPU_GPU_PAGE_SIZE@GOTPAGE
Lloh1:
	ldr	x23, [x23, _AMDGPU_GPU_PAGE_SIZE@GOTPAGEOFF]
	ldr	w8, [x23]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #3
	bl	_order_base_2
	orr	w20, w20, w0, lsl #8
Lloh2:
	adrp	x25, _mmCP_RB1_CNTL@GOTPAGE
Lloh3:
	ldr	x25, [x25, _mmCP_RB1_CNTL@GOTPAGEOFF]
	ldr	w0, [x25]
	mov	x1, x20
	bl	_WREG32
	ldr	w0, [x25]
Lloh4:
	adrp	x8, _CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK@GOTPAGE
Lloh5:
	ldr	x8, [x8, _CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
	orr	w1, w8, w20
	bl	_WREG32
	str	wzr, [x24, #4]
Lloh7:
	adrp	x8, _mmCP_RB1_WPTR@GOTPAGE
Lloh8:
	ldr	x8, [x8, _mmCP_RB1_WPTR@GOTPAGEOFF]
Lloh9:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x19, #8]
	ldrsw	x9, [x24, #8]
	add	x21, x8, x9, lsl #2
Lloh10:
	adrp	x8, _mmCP_RB1_RPTR_ADDR@GOTPAGE
Lloh11:
	ldr	x8, [x8, _mmCP_RB1_RPTR_ADDR@GOTPAGEOFF]
Lloh12:
	ldr	w22, [x8]
	mov	x0, x21
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x22
	bl	_WREG32
Lloh13:
	adrp	x8, _mmCP_RB1_RPTR_ADDR_HI@GOTPAGE
Lloh14:
	ldr	x8, [x8, _mmCP_RB1_RPTR_ADDR_HI@GOTPAGEOFF]
Lloh15:
	ldr	w22, [x8]
	mov	x0, x21
	bl	_upper_32_bits
	and	w1, w0, #0xff
	mov	x0, x22
	bl	_WREG32
	mov	w0, #1
	bl	_mdelay
	ldr	w0, [x25]
	mov	x1, x20
	bl	_WREG32
Lloh16:
	adrp	x8, _mmCP_RB1_BASE@GOTPAGE
Lloh17:
	ldr	x8, [x8, _mmCP_RB1_BASE@GOTPAGEOFF]
Lloh18:
	ldr	w0, [x8]
	ldr	w8, [x24, #12]
	asr	w1, w8, #8
	bl	_WREG32
	ldr	x24, [x19]
	ldr	w8, [x24, #16]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #3
	bl	_order_base_2
	mov	x20, x0
	ldr	w8, [x23]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #3
	bl	_order_base_2
	orr	w20, w20, w0, lsl #8
Lloh19:
	adrp	x23, _mmCP_RB2_CNTL@GOTPAGE
Lloh20:
	ldr	x23, [x23, _mmCP_RB2_CNTL@GOTPAGEOFF]
	ldr	w0, [x23]
	mov	x1, x20
	bl	_WREG32
	ldr	w0, [x23]
Lloh21:
	adrp	x8, _CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK@GOTPAGE
Lloh22:
	ldr	x8, [x8, _CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	orr	w1, w8, w20
	bl	_WREG32
	str	wzr, [x24, #20]
Lloh24:
	adrp	x8, _mmCP_RB2_WPTR@GOTPAGE
Lloh25:
	ldr	x8, [x8, _mmCP_RB2_WPTR@GOTPAGEOFF]
Lloh26:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x19, #8]
	ldrsw	x9, [x24, #24]
	add	x21, x8, x9, lsl #2
Lloh27:
	adrp	x8, _mmCP_RB2_RPTR_ADDR@GOTPAGE
Lloh28:
	ldr	x8, [x8, _mmCP_RB2_RPTR_ADDR@GOTPAGEOFF]
Lloh29:
	ldr	w22, [x8]
	mov	x0, x21
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x22
	bl	_WREG32
Lloh30:
	adrp	x8, _mmCP_RB2_RPTR_ADDR_HI@GOTPAGE
Lloh31:
	ldr	x8, [x8, _mmCP_RB2_RPTR_ADDR_HI@GOTPAGEOFF]
Lloh32:
	ldr	w22, [x8]
	mov	x0, x21
	bl	_upper_32_bits
	and	w1, w0, #0xff
	mov	x0, x22
	bl	_WREG32
	mov	w0, #1
	bl	_mdelay
	ldr	w0, [x23]
	mov	x1, x20
	bl	_WREG32
Lloh33:
	adrp	x8, _mmCP_RB2_BASE@GOTPAGE
Lloh34:
	ldr	x8, [x8, _mmCP_RB2_BASE@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	ldr	w8, [x24, #28]
	asr	w1, w8, #8
	bl	_WREG32
	ldr	x0, [x19]
	bl	_amdgpu_ring_test_helper
	cbz	w0, LBB0_2
; %bb.1:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_2:
	ldr	x8, [x19]
	add	x0, x8, #16
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_amdgpu_ring_test_helper
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_GPU_PAGE_SIZE,4,2       ; @AMDGPU_GPU_PAGE_SIZE
	.comm	_mmCP_RB1_CNTL,4,2              ; @mmCP_RB1_CNTL
	.comm	_CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK,4,2 ; @CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK
	.comm	_mmCP_RB1_WPTR,4,2              ; @mmCP_RB1_WPTR
	.comm	_mmCP_RB1_RPTR_ADDR,4,2         ; @mmCP_RB1_RPTR_ADDR
	.comm	_mmCP_RB1_RPTR_ADDR_HI,4,2      ; @mmCP_RB1_RPTR_ADDR_HI
	.comm	_mmCP_RB1_BASE,4,2              ; @mmCP_RB1_BASE
	.comm	_mmCP_RB2_CNTL,4,2              ; @mmCP_RB2_CNTL
	.comm	_CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK,4,2 ; @CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK
	.comm	_mmCP_RB2_WPTR,4,2              ; @mmCP_RB2_WPTR
	.comm	_mmCP_RB2_RPTR_ADDR,4,2         ; @mmCP_RB2_RPTR_ADDR
	.comm	_mmCP_RB2_RPTR_ADDR_HI,4,2      ; @mmCP_RB2_RPTR_ADDR_HI
	.comm	_mmCP_RB2_BASE,4,2              ; @mmCP_RB2_BASE
	.comm	_BUF_SWAP_32BIT,4,2             ; @BUF_SWAP_32BIT
	.no_dead_strip	_gfx_v6_0_cp_compute_resume
.subsections_via_symbols
