	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_legacy_tmds_ext_mode_set
_radeon_legacy_tmds_ext_mode_set:       ## @radeon_legacy_tmds_ext_mode_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %rbx
	movq	%rdi, %r12
	movq	8(%rdi), %r13
	movq	8(%r13), %r14
	movl	(%rdi), %edi
	callq	_to_radeon_crtc
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movq	%r12, %rdi
	callq	_to_radeon_encoder
	movq	%rax, %r15
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	cmpq	$0, 8(%r14)
	je	LBB0_2
## %bb.1:
	movl	(%rbx), %eax
	movl	%eax, 8(%r15)
	movq	_ATOM_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_atombios_dvo_setup
	movq	_RADEON_FP2_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %ebx
	movq	-48(%rbp), %r13                 ## 8-byte Reload
	jmp	LBB0_10
LBB0_2:
	movq	_RADEON_FP2_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_RADEON_FP2_PANEL_FORMAT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_FP2_ON@GOTPCREL(%rip), %rcx
	movq	_RADEON_FP2_DVO_EN@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rcx), %ebx
	movq	_RADEON_FP2_DVO_RATE_SEL_SDR@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movq	%r14, %rdi
	callq	_ASIC_IS_R300
	testq	%rax, %rax
	je	LBB0_8
## %bb.3:
	movq	(%r13), %rax
	cmpl	$18512, (%rax)                  ## imm = 0x4850
	jne	LBB0_7
## %bb.4:
	cmpl	$4136, 4(%rax)                  ## imm = 0x1028
	jne	LBB0_7
## %bb.5:
	cmpl	$8193, 8(%rax)                  ## imm = 0x2001
	jne	LBB0_7
## %bb.6:
	movq	_R300_FP2_DVO_CLOCK_MODE_SINGLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	jmp	LBB0_8
LBB0_7:
	movq	_RADEON_FP2_PAD_FLOP_EN@GOTPCREL(%rip), %rax
	movq	_R300_FP2_DVO_CLOCK_MODE_SINGLE@GOTPCREL(%rip), %rcx
	orl	(%rax), %ebx
	orl	(%rcx), %ebx
LBB0_8:
	movq	-48(%rbp), %r13                 ## 8-byte Reload
	movq	%r12, %rdi
	callq	_radeon_combios_external_tmds_setup
	testl	%eax, %eax
	jne	LBB0_10
## %bb.9:
	movq	%r12, %rdi
	callq	_radeon_external_tmds_setup
LBB0_10:
	cmpq	$0, (%r13)
	movq	(%r14), %rax
	movq	_CHIP_R200@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	je	LBB0_11
## %bb.17:
	cmpq	%rcx, %rax
	je	LBB0_19
## %bb.18:
	movq	%r14, %rdi
	callq	_ASIC_IS_R300
	testq	%rax, %rax
	je	LBB0_20
LBB0_19:
	movq	_R200_FP2_SOURCE_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %ebx
	movq	_R200_FP2_SOURCE_SEL_CRTC2@GOTPCREL(%rip), %rax
	jmp	LBB0_21
LBB0_11:
	cmpq	%rcx, %rax
	je	LBB0_13
## %bb.12:
	movq	%r14, %rdi
	callq	_ASIC_IS_R300
	testq	%rax, %rax
	je	LBB0_16
LBB0_13:
	movq	_R200_FP2_SOURCE_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %ebx
	movq	(%r15), %rax
	movq	_RMX_OFF@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_14
## %bb.15:
	movq	_R200_FP2_SOURCE_SEL_CRTC1@GOTPCREL(%rip), %rax
	jmp	LBB0_21
LBB0_14:
	movq	_R200_FP2_SOURCE_SEL_RMX@GOTPCREL(%rip), %rax
	jmp	LBB0_21
LBB0_20:
	movq	_RADEON_FP2_SRC_SEL_CRTC2@GOTPCREL(%rip), %rax
LBB0_21:
	orl	(%rax), %ebx
LBB0_22:
	movq	_RADEON_FP2_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	cmpq	$0, 8(%r14)
	movq	(%r13), %rsi
	movq	%r12, %rdi
	je	LBB0_24
## %bb.23:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_atombios_encoder_crtc_scratch_regs ## TAILCALL
LBB0_24:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_combios_encoder_crtc_scratch_regs ## TAILCALL
LBB0_16:
	movq	_RADEON_FP2_SRC_SEL_CRTC2@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %ebx
	jmp	LBB0_22
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"\n"

	.comm	_ATOM_ENABLE,4,2                ## @ATOM_ENABLE
	.comm	_RADEON_FP2_GEN_CNTL,4,2        ## @RADEON_FP2_GEN_CNTL
	.comm	_RADEON_FP2_PANEL_FORMAT,4,2    ## @RADEON_FP2_PANEL_FORMAT
	.comm	_RADEON_FP2_ON,4,2              ## @RADEON_FP2_ON
	.comm	_RADEON_FP2_DVO_EN,4,2          ## @RADEON_FP2_DVO_EN
	.comm	_RADEON_FP2_DVO_RATE_SEL_SDR,4,2 ## @RADEON_FP2_DVO_RATE_SEL_SDR
	.comm	_R300_FP2_DVO_CLOCK_MODE_SINGLE,4,2 ## @R300_FP2_DVO_CLOCK_MODE_SINGLE
	.comm	_RADEON_FP2_PAD_FLOP_EN,4,2     ## @RADEON_FP2_PAD_FLOP_EN
	.comm	_CHIP_R200,8,3                  ## @CHIP_R200
	.comm	_R200_FP2_SOURCE_SEL_MASK,4,2   ## @R200_FP2_SOURCE_SEL_MASK
	.comm	_RMX_OFF,8,3                    ## @RMX_OFF
	.comm	_R200_FP2_SOURCE_SEL_RMX,4,2    ## @R200_FP2_SOURCE_SEL_RMX
	.comm	_R200_FP2_SOURCE_SEL_CRTC1,4,2  ## @R200_FP2_SOURCE_SEL_CRTC1
	.comm	_RADEON_FP2_SRC_SEL_CRTC2,4,2   ## @RADEON_FP2_SRC_SEL_CRTC2
	.comm	_R200_FP2_SOURCE_SEL_CRTC2,4,2  ## @R200_FP2_SOURCE_SEL_CRTC2
	.no_dead_strip	_radeon_legacy_tmds_ext_mode_set
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_legacy_tmds_ext_mode_set
_radeon_legacy_tmds_ext_mode_set:       ; @radeon_legacy_tmds_ext_mode_set
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x23, x2
	mov	x19, x0
	ldr	x25, [x0, #8]
	ldr	x20, [x25, #8]
	ldr	w0, [x0]
	bl	_to_radeon_crtc
	mov	x21, x0
	mov	x0, x19
	bl	_to_radeon_encoder
	mov	x22, x0
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_KMS
	ldr	x8, [x20, #8]
Lloh2:
	adrp	x24, _RADEON_FP2_GEN_CNTL@GOTPAGE
Lloh3:
	ldr	x24, [x24, _RADEON_FP2_GEN_CNTL@GOTPAGEOFF]
	cbz	x8, LBB0_2
; %bb.1:
	ldr	w8, [x23]
	str	w8, [x22, #8]
Lloh4:
	adrp	x8, _ATOM_ENABLE@GOTPAGE
Lloh5:
	ldr	x8, [x8, _ATOM_ENABLE@GOTPAGEOFF]
Lloh6:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_atombios_dvo_setup
	ldr	w0, [x24]
	bl	_RREG32
	mov	x23, x0
	b	LBB0_10
LBB0_2:
	ldr	w0, [x24]
	bl	_RREG32
Lloh7:
	adrp	x8, _RADEON_FP2_PANEL_FORMAT@GOTPAGE
Lloh8:
	ldr	x8, [x8, _RADEON_FP2_PANEL_FORMAT@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh10:
	adrp	x9, _RADEON_FP2_ON@GOTPAGE
Lloh11:
	ldr	x9, [x9, _RADEON_FP2_ON@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
Lloh13:
	adrp	x10, _RADEON_FP2_DVO_EN@GOTPAGE
Lloh14:
	ldr	x10, [x10, _RADEON_FP2_DVO_EN@GOTPAGEOFF]
Lloh15:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh16:
	adrp	x10, _RADEON_FP2_DVO_RATE_SEL_SDR@GOTPAGE
Lloh17:
	ldr	x10, [x10, _RADEON_FP2_DVO_RATE_SEL_SDR@GOTPAGEOFF]
Lloh18:
	ldr	w10, [x10]
	orr	w9, w9, w10
	bic	w23, w8, w9
	mov	x0, x20
	bl	_ASIC_IS_R300
	cbz	x0, LBB0_8
; %bb.3:
	ldr	x8, [x25]
	ldr	w9, [x8]
	mov	w10, #18512
	cmp	w9, w10
	b.ne	LBB0_7
; %bb.4:
	ldr	w9, [x8, #4]
	mov	w10, #4136
	cmp	w9, w10
	b.ne	LBB0_7
; %bb.5:
	ldr	w8, [x8, #8]
	mov	w9, #8193
	cmp	w8, w9
	b.ne	LBB0_7
; %bb.6:
Lloh19:
	adrp	x8, _R300_FP2_DVO_CLOCK_MODE_SINGLE@GOTPAGE
Lloh20:
	ldr	x8, [x8, _R300_FP2_DVO_CLOCK_MODE_SINGLE@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
	orr	w23, w8, w23
	b	LBB0_8
LBB0_7:
Lloh22:
	adrp	x8, _RADEON_FP2_PAD_FLOP_EN@GOTPAGE
Lloh23:
	ldr	x8, [x8, _RADEON_FP2_PAD_FLOP_EN@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
Lloh25:
	adrp	x9, _R300_FP2_DVO_CLOCK_MODE_SINGLE@GOTPAGE
Lloh26:
	ldr	x9, [x9, _R300_FP2_DVO_CLOCK_MODE_SINGLE@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
	orr	w8, w8, w23
	orr	w23, w8, w9
LBB0_8:
	mov	x0, x19
	bl	_radeon_combios_external_tmds_setup
	cbnz	w0, LBB0_10
; %bb.9:
	mov	x0, x19
	bl	_radeon_external_tmds_setup
LBB0_10:
	ldr	x10, [x21]
	ldr	x8, [x20]
Lloh28:
	adrp	x9, _CHIP_R200@GOTPAGE
Lloh29:
	ldr	x9, [x9, _CHIP_R200@GOTPAGEOFF]
Lloh30:
	ldr	x9, [x9]
	cmp	x8, x9
	cbz	x10, LBB0_14
; %bb.11:
	b.eq	LBB0_13
; %bb.12:
	mov	x0, x20
	bl	_ASIC_IS_R300
	cbz	x0, LBB0_20
LBB0_13:
Lloh31:
	adrp	x8, _R200_FP2_SOURCE_SEL_MASK@GOTPAGE
Lloh32:
	ldr	x8, [x8, _R200_FP2_SOURCE_SEL_MASK@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
	bic	w8, w23, w8
Lloh34:
	adrp	x9, _R200_FP2_SOURCE_SEL_CRTC2@GOTPAGE
Lloh35:
	ldr	x9, [x9, _R200_FP2_SOURCE_SEL_CRTC2@GOTPAGEOFF]
Lloh36:
	ldr	w9, [x9]
	orr	w1, w8, w9
	b	LBB0_22
LBB0_14:
	b.eq	LBB0_16
; %bb.15:
	mov	x0, x20
	bl	_ASIC_IS_R300
	cbz	x0, LBB0_21
LBB0_16:
Lloh37:
	adrp	x8, _R200_FP2_SOURCE_SEL_MASK@GOTPAGE
Lloh38:
	ldr	x8, [x8, _R200_FP2_SOURCE_SEL_MASK@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
	bic	w8, w23, w8
	ldr	x9, [x22]
Lloh40:
	adrp	x10, _RMX_OFF@GOTPAGE
Lloh41:
	ldr	x10, [x10, _RMX_OFF@GOTPAGEOFF]
Lloh42:
	ldr	x10, [x10]
	cmp	x9, x10
	b.ne	LBB0_18
; %bb.17:
Lloh43:
	adrp	x9, _R200_FP2_SOURCE_SEL_CRTC1@GOTPAGE
Lloh44:
	ldr	x9, [x9, _R200_FP2_SOURCE_SEL_CRTC1@GOTPAGEOFF]
	b	LBB0_19
LBB0_18:
Lloh45:
	adrp	x9, _R200_FP2_SOURCE_SEL_RMX@GOTPAGE
Lloh46:
	ldr	x9, [x9, _R200_FP2_SOURCE_SEL_RMX@GOTPAGEOFF]
LBB0_19:
	ldr	w9, [x9]
	orr	w1, w9, w8
	b	LBB0_22
LBB0_20:
Lloh47:
	adrp	x8, _RADEON_FP2_SRC_SEL_CRTC2@GOTPAGE
Lloh48:
	ldr	x8, [x8, _RADEON_FP2_SRC_SEL_CRTC2@GOTPAGEOFF]
Lloh49:
	ldr	w8, [x8]
	orr	w1, w8, w23
	b	LBB0_22
LBB0_21:
Lloh50:
	adrp	x8, _RADEON_FP2_SRC_SEL_CRTC2@GOTPAGE
Lloh51:
	ldr	x8, [x8, _RADEON_FP2_SRC_SEL_CRTC2@GOTPAGEOFF]
Lloh52:
	ldr	w8, [x8]
	bic	w1, w23, w8
LBB0_22:
	ldr	w0, [x24]
	bl	_WREG32
	ldr	x8, [x20, #8]
	ldr	x1, [x21]
	mov	x0, x19
	cbz	x8, LBB0_24
; %bb.23:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_radeon_atombios_encoder_crtc_scratch_regs
LBB0_24:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_radeon_combios_encoder_crtc_scratch_regs
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"\n"

	.comm	_ATOM_ENABLE,4,2                ; @ATOM_ENABLE
	.comm	_RADEON_FP2_GEN_CNTL,4,2        ; @RADEON_FP2_GEN_CNTL
	.comm	_RADEON_FP2_PANEL_FORMAT,4,2    ; @RADEON_FP2_PANEL_FORMAT
	.comm	_RADEON_FP2_ON,4,2              ; @RADEON_FP2_ON
	.comm	_RADEON_FP2_DVO_EN,4,2          ; @RADEON_FP2_DVO_EN
	.comm	_RADEON_FP2_DVO_RATE_SEL_SDR,4,2 ; @RADEON_FP2_DVO_RATE_SEL_SDR
	.comm	_R300_FP2_DVO_CLOCK_MODE_SINGLE,4,2 ; @R300_FP2_DVO_CLOCK_MODE_SINGLE
	.comm	_RADEON_FP2_PAD_FLOP_EN,4,2     ; @RADEON_FP2_PAD_FLOP_EN
	.comm	_CHIP_R200,8,3                  ; @CHIP_R200
	.comm	_R200_FP2_SOURCE_SEL_MASK,4,2   ; @R200_FP2_SOURCE_SEL_MASK
	.comm	_RMX_OFF,8,3                    ; @RMX_OFF
	.comm	_R200_FP2_SOURCE_SEL_RMX,4,2    ; @R200_FP2_SOURCE_SEL_RMX
	.comm	_R200_FP2_SOURCE_SEL_CRTC1,4,2  ; @R200_FP2_SOURCE_SEL_CRTC1
	.comm	_RADEON_FP2_SRC_SEL_CRTC2,4,2   ; @RADEON_FP2_SRC_SEL_CRTC2
	.comm	_R200_FP2_SOURCE_SEL_CRTC2,4,2  ; @R200_FP2_SOURCE_SEL_CRTC2
	.no_dead_strip	_radeon_legacy_tmds_ext_mode_set
.subsections_via_symbols
