	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vega10_ih_irq_init
_vega10_ih_irq_init:                    ## @vega10_ih_irq_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	callq	_vega10_ih_disable_interrupts
	movq	128(%r15), %rax
	movq	%r15, %rdi
	callq	*(%rax)
	leaq	88(%r15), %r13
	movq	_OSSSYS@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	movq	_mmIH_RB_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	88(%r15), %ecx
	sarl	$8, %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmIH_RB_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmIH_RB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	%eax, %ebx
	movl	(%r14), %edi
	movq	_mmIH_CHICKEN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	%eax, %r12d
	movq	%r13, %r14
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_vega10_ih_rb_cntl
	movl	%eax, %r13d
	cmpq	$0, 112(%r15)
	movq	_IH_CHICKEN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	jne	LBB0_1
## %bb.2:
	movq	_MC_SPACE_FBPA_ENABLE@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_1:
	movq	_MC_SPACE_GPA_ENABLE@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %edx
	movl	%r12d, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	%eax, %r12d
	movq	_IH_RB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_RPTR_REARM@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
	cmpl	$0, 80(%r15)
	setne	%cl
	movl	%r13d, %edi
	callq	_REG_SET_FIELD
	movl	%eax, %ebx
	movq	%r15, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_7
## %bb.4:
	leaq	12(%r15), %rdi
	movq	_PSP_REG_IH_RB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%ebx, %edx
	callq	_psp_reg_program
	testq	%rax, %rax
	je	LBB0_8
## %bb.5:
	leaq	L_.str(%rip), %rdi
	jmp	LBB0_6
LBB0_7:
	movq	_OSSSYS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmIH_RB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	movl	%ebx, %ecx
	callq	_WREG32_SOC15
LBB0_8:
	movq	(%r15), %rax
	movq	_CHIP_ARCTURUS@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_11
## %bb.9:
	movq	120(%r15), %rcx
	movq	_AMDGPU_FW_LOAD_DIRECT@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	movq	%r14, %r13
	movq	_OSSSYS@GOTPCREL(%rip), %r14
	je	LBB0_12
## %bb.10:
	movq	_CHIP_RENOIR@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_13
	jmp	LBB0_12
LBB0_11:
	movq	_CHIP_RENOIR@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	movq	%r14, %r13
	movq	_OSSSYS@GOTPCREL(%rip), %r14
	jne	LBB0_13
LBB0_12:
	movl	(%r14), %edi
	movq	_mmIH_CHICKEN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	movl	%r12d, %ecx
	callq	_WREG32_SOC15
LBB0_13:
	movl	(%r14), %ebx
	movq	_mmIH_RB_WPTR_ADDR_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	104(%r15), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %ebx
	movq	_mmIH_RB_WPTR_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	104(%r15), %edi
	callq	_upper_32_bits
	movzwl	%ax, %ecx
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmIH_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmIH_RB_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %ebx
	movq	_mmIH_DOORBELL_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	%r13, %rdi
	callq	_vega10_ih_doorbell_rptr
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	cmpq	$0, 56(%r15)
	je	LBB0_19
## %bb.14:
	leaq	48(%r15), %r13
	movl	(%r14), %edi
	movq	_mmIH_RB_BASE_RING1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	48(%r15), %ecx
	sarl	$8, %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmIH_RB_BASE_HI_RING1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmIH_RB_CNTL_RING1@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_vega10_ih_rb_cntl
	movq	_IH_RB_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_WPTR_OVERFLOW_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_FULL_DRAIN_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	%eax, %ebx
	movq	%r15, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_17
## %bb.15:
	leaq	12(%r15), %rdi
	movq	_PSP_REG_IH_RB_CNTL_RING1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%ebx, %edx
	callq	_psp_reg_program
	testq	%rax, %rax
	je	LBB0_18
## %bb.16:
	leaq	L_.str.1(%rip), %rdi
	jmp	LBB0_6
LBB0_17:
	movl	(%r14), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	movl	%ebx, %ecx
	callq	_WREG32_SOC15
LBB0_18:
	movl	(%r14), %edi
	movq	_mmIH_RB_WPTR_RING1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmIH_RB_RPTR_RING1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %ebx
	movq	_mmIH_DOORBELL_RPTR_RING1@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	%r13, %rdi
	callq	_vega10_ih_doorbell_rptr
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
LBB0_19:
	cmpq	$0, 24(%r15)
	je	LBB0_25
## %bb.20:
	leaq	16(%r15), %r13
	movl	(%r14), %edi
	movq	_mmIH_RB_BASE_RING2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	16(%r15), %ecx
	sarl	$8, %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmIH_RB_BASE_HI_RING2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmIH_RB_CNTL_RING2@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_vega10_ih_rb_cntl
	movl	%eax, %ebx
	movq	%r15, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_23
## %bb.21:
	leaq	12(%r15), %rdi
	movq	_PSP_REG_IH_RB_CNTL_RING2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%ebx, %edx
	callq	_psp_reg_program
	testq	%rax, %rax
	je	LBB0_24
## %bb.22:
	leaq	L_.str.2(%rip), %rdi
LBB0_6:
	callq	_DRM_ERROR
	movq	_ETIMEDOUT@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
	jmp	LBB0_26
LBB0_23:
	movl	(%r14), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	movl	%ebx, %ecx
	callq	_WREG32_SOC15
LBB0_24:
	movl	(%r14), %edi
	movq	_mmIH_RB_WPTR_RING2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmIH_RB_RPTR_RING2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %ebx
	movq	_mmIH_DOORBELL_RPTR_RING2@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	%r13, %rdi
	callq	_vega10_ih_doorbell_rptr
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
LBB0_25:
	movl	(%r14), %edi
	movq	_mmIH_STORM_CLIENT_LIST_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%ebx, %ebx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_IH_STORM_CLIENT_LIST_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_CLIENT18_IS_STORM_CLIENT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r14), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmIH_INT_FLOOD_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_IH_INT_FLOOD_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_FLOOD_CNTL_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r14), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	8(%r15), %edi
	callq	_pci_set_master
	movq	%r15, %rdi
	callq	_vega10_ih_enable_interrupts
LBB0_26:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_OSSSYS,4,2                     ## @OSSSYS
	.comm	_mmIH_RB_BASE,4,2               ## @mmIH_RB_BASE
	.comm	_mmIH_RB_BASE_HI,4,2            ## @mmIH_RB_BASE_HI
	.comm	_mmIH_RB_CNTL,4,2               ## @mmIH_RB_CNTL
	.comm	_mmIH_CHICKEN,4,2               ## @mmIH_CHICKEN
	.comm	_IH_CHICKEN,4,2                 ## @IH_CHICKEN
	.comm	_MC_SPACE_GPA_ENABLE,4,2        ## @MC_SPACE_GPA_ENABLE
	.comm	_MC_SPACE_FBPA_ENABLE,4,2       ## @MC_SPACE_FBPA_ENABLE
	.comm	_IH_RB_CNTL,4,2                 ## @IH_RB_CNTL
	.comm	_RPTR_REARM,4,2                 ## @RPTR_REARM
	.comm	_PSP_REG_IH_RB_CNTL,4,2         ## @PSP_REG_IH_RB_CNTL
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"PSP program IH_RB_CNTL failed!\n"

	.comm	_ETIMEDOUT,4,2                  ## @ETIMEDOUT
	.comm	_CHIP_ARCTURUS,8,3              ## @CHIP_ARCTURUS
	.comm	_AMDGPU_FW_LOAD_DIRECT,8,3      ## @AMDGPU_FW_LOAD_DIRECT
	.comm	_CHIP_RENOIR,8,3                ## @CHIP_RENOIR
	.comm	_mmIH_RB_WPTR_ADDR_LO,4,2       ## @mmIH_RB_WPTR_ADDR_LO
	.comm	_mmIH_RB_WPTR_ADDR_HI,4,2       ## @mmIH_RB_WPTR_ADDR_HI
	.comm	_mmIH_RB_WPTR,4,2               ## @mmIH_RB_WPTR
	.comm	_mmIH_RB_RPTR,4,2               ## @mmIH_RB_RPTR
	.comm	_mmIH_DOORBELL_RPTR,4,2         ## @mmIH_DOORBELL_RPTR
	.comm	_mmIH_RB_BASE_RING1,4,2         ## @mmIH_RB_BASE_RING1
	.comm	_mmIH_RB_BASE_HI_RING1,4,2      ## @mmIH_RB_BASE_HI_RING1
	.comm	_mmIH_RB_CNTL_RING1,4,2         ## @mmIH_RB_CNTL_RING1
	.comm	_WPTR_OVERFLOW_ENABLE,4,2       ## @WPTR_OVERFLOW_ENABLE
	.comm	_RB_FULL_DRAIN_ENABLE,4,2       ## @RB_FULL_DRAIN_ENABLE
	.comm	_PSP_REG_IH_RB_CNTL_RING1,4,2   ## @PSP_REG_IH_RB_CNTL_RING1
L_.str.1:                               ## @.str.1
	.asciz	"program IH_RB_CNTL_RING1 failed!\n"

	.comm	_mmIH_RB_WPTR_RING1,4,2         ## @mmIH_RB_WPTR_RING1
	.comm	_mmIH_RB_RPTR_RING1,4,2         ## @mmIH_RB_RPTR_RING1
	.comm	_mmIH_DOORBELL_RPTR_RING1,4,2   ## @mmIH_DOORBELL_RPTR_RING1
	.comm	_mmIH_RB_BASE_RING2,4,2         ## @mmIH_RB_BASE_RING2
	.comm	_mmIH_RB_BASE_HI_RING2,4,2      ## @mmIH_RB_BASE_HI_RING2
	.comm	_mmIH_RB_CNTL_RING2,4,2         ## @mmIH_RB_CNTL_RING2
	.comm	_PSP_REG_IH_RB_CNTL_RING2,4,2   ## @PSP_REG_IH_RB_CNTL_RING2
L_.str.2:                               ## @.str.2
	.asciz	"program IH_RB_CNTL_RING2 failed!\n"

	.comm	_mmIH_RB_WPTR_RING2,4,2         ## @mmIH_RB_WPTR_RING2
	.comm	_mmIH_RB_RPTR_RING2,4,2         ## @mmIH_RB_RPTR_RING2
	.comm	_mmIH_DOORBELL_RPTR_RING2,4,2   ## @mmIH_DOORBELL_RPTR_RING2
	.comm	_mmIH_STORM_CLIENT_LIST_CNTL,4,2 ## @mmIH_STORM_CLIENT_LIST_CNTL
	.comm	_IH_STORM_CLIENT_LIST_CNTL,4,2  ## @IH_STORM_CLIENT_LIST_CNTL
	.comm	_CLIENT18_IS_STORM_CLIENT,4,2   ## @CLIENT18_IS_STORM_CLIENT
	.comm	_mmIH_INT_FLOOD_CNTL,4,2        ## @mmIH_INT_FLOOD_CNTL
	.comm	_IH_INT_FLOOD_CNTL,4,2          ## @IH_INT_FLOOD_CNTL
	.comm	_FLOOD_CNTL_ENABLE,4,2          ## @FLOOD_CNTL_ENABLE
	.no_dead_strip	_vega10_ih_irq_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vega10_ih_irq_init
_vega10_ih_irq_init:                    ; @vega10_ih_irq_init
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	bl	_vega10_ih_disable_interrupts
	ldr	x8, [x19, #128]
	ldr	x8, [x8]
	mov	x0, x19
	blr	x8
	mov	x20, x19
	ldr	w8, [x20, #88]!
Lloh0:
	adrp	x24, _OSSSYS@GOTPAGE
Lloh1:
	ldr	x24, [x24, _OSSSYS@GOTPAGEOFF]
	ldr	w0, [x24]
Lloh2:
	adrp	x9, _mmIH_RB_BASE@GOTPAGE
Lloh3:
	ldr	x9, [x9, _mmIH_RB_BASE@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x9]
	asr	w3, w8, #8
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh5:
	adrp	x8, _mmIH_RB_BASE_HI@GOTPAGE
Lloh6:
	ldr	x8, [x8, _mmIH_RB_BASE_HI@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh8:
	adrp	x27, _mmIH_RB_CNTL@GOTPAGE
Lloh9:
	ldr	x27, [x27, _mmIH_RB_CNTL@GOTPAGEOFF]
	ldr	w2, [x27]
	mov	w1, #0
	bl	_RREG32_SOC15
	mov	x21, x0
	ldr	w0, [x24]
Lloh10:
	adrp	x26, _mmIH_CHICKEN@GOTPAGE
Lloh11:
	ldr	x26, [x26, _mmIH_CHICKEN@GOTPAGEOFF]
	ldr	w2, [x26]
	mov	w1, #0
	bl	_RREG32_SOC15
	mov	x22, x0
	mov	x0, x20
	mov	x1, x21
	bl	_vega10_ih_rb_cntl
	mov	x23, x0
	ldr	x8, [x19, #112]
Lloh12:
	adrp	x9, _IH_CHICKEN@GOTPAGE
Lloh13:
	ldr	x9, [x9, _IH_CHICKEN@GOTPAGEOFF]
Lloh14:
	adrp	x10, _MC_SPACE_FBPA_ENABLE@GOTPAGE
Lloh15:
	ldr	x10, [x10, _MC_SPACE_FBPA_ENABLE@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x9]
Lloh17:
	adrp	x9, _MC_SPACE_GPA_ENABLE@GOTPAGE
Lloh18:
	ldr	x9, [x9, _MC_SPACE_GPA_ENABLE@GOTPAGEOFF]
	cmp	x8, #0
	csel	x8, x10, x9, eq
	ldr	w2, [x8]
	mov	x0, x22
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x21, x0
Lloh19:
	adrp	x25, _IH_RB_CNTL@GOTPAGE
Lloh20:
	ldr	x25, [x25, _IH_RB_CNTL@GOTPAGEOFF]
	ldr	w1, [x25]
Lloh21:
	adrp	x8, _RPTR_REARM@GOTPAGE
Lloh22:
	ldr	x8, [x8, _RPTR_REARM@GOTPAGEOFF]
Lloh23:
	ldr	w2, [x8]
	ldr	w8, [x19, #80]
	cmp	w8, #0
	cset	w3, ne
	mov	x0, x23
	bl	_REG_SET_FIELD
	mov	x22, x0
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_3
; %bb.1:
	add	x0, x19, #12
Lloh24:
	adrp	x8, _PSP_REG_IH_RB_CNTL@GOTPAGE
Lloh25:
	ldr	x8, [x8, _PSP_REG_IH_RB_CNTL@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	x2, x22
	bl	_psp_reg_program
	cbz	x0, LBB0_4
; %bb.2:
Lloh27:
	adrp	x0, l_.str@PAGE
Lloh28:
	add	x0, x0, l_.str@PAGEOFF
	b	LBB0_18
LBB0_3:
	ldr	w0, [x24]
	ldr	w2, [x27]
	mov	w1, #0
	mov	x3, x22
	bl	_WREG32_SOC15
LBB0_4:
	ldr	x8, [x19]
Lloh29:
	adrp	x9, _CHIP_ARCTURUS@GOTPAGE
Lloh30:
	ldr	x9, [x9, _CHIP_ARCTURUS@GOTPAGEOFF]
Lloh31:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_6
; %bb.5:
	ldr	x9, [x19, #120]
Lloh32:
	adrp	x10, _AMDGPU_FW_LOAD_DIRECT@GOTPAGE
Lloh33:
	ldr	x10, [x10, _AMDGPU_FW_LOAD_DIRECT@GOTPAGEOFF]
Lloh34:
	ldr	x10, [x10]
	cmp	x9, x10
	b.eq	LBB0_7
LBB0_6:
Lloh35:
	adrp	x9, _CHIP_RENOIR@GOTPAGE
Lloh36:
	ldr	x9, [x9, _CHIP_RENOIR@GOTPAGEOFF]
Lloh37:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_8
LBB0_7:
	ldr	w0, [x24]
	ldr	w2, [x26]
	mov	w1, #0
	mov	x3, x21
	bl	_WREG32_SOC15
LBB0_8:
	ldr	w21, [x24]
Lloh38:
	adrp	x8, _mmIH_RB_WPTR_ADDR_LO@GOTPAGE
Lloh39:
	ldr	x8, [x8, _mmIH_RB_WPTR_ADDR_LO@GOTPAGEOFF]
Lloh40:
	ldr	w22, [x8]
	ldr	w0, [x19, #104]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x21
	mov	w1, #0
	mov	x2, x22
	bl	_WREG32_SOC15
	ldr	w21, [x24]
Lloh41:
	adrp	x8, _mmIH_RB_WPTR_ADDR_HI@GOTPAGE
Lloh42:
	ldr	x8, [x8, _mmIH_RB_WPTR_ADDR_HI@GOTPAGEOFF]
Lloh43:
	ldr	w22, [x8]
	ldr	w0, [x19, #104]
	bl	_upper_32_bits
	and	w3, w0, #0xffff
	mov	x0, x21
	mov	w1, #0
	mov	x2, x22
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh44:
	adrp	x8, _mmIH_RB_WPTR@GOTPAGE
Lloh45:
	ldr	x8, [x8, _mmIH_RB_WPTR@GOTPAGEOFF]
Lloh46:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh47:
	adrp	x8, _mmIH_RB_RPTR@GOTPAGE
Lloh48:
	ldr	x8, [x8, _mmIH_RB_RPTR@GOTPAGEOFF]
Lloh49:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w21, [x24]
Lloh50:
	adrp	x8, _mmIH_DOORBELL_RPTR@GOTPAGE
Lloh51:
	ldr	x8, [x8, _mmIH_DOORBELL_RPTR@GOTPAGEOFF]
Lloh52:
	ldr	w22, [x8]
	mov	x0, x20
	bl	_vega10_ih_doorbell_rptr
	mov	x3, x0
	mov	x0, x21
	mov	w1, #0
	mov	x2, x22
	bl	_WREG32_SOC15
	ldr	x8, [x19, #56]
	cbz	x8, LBB0_14
; %bb.9:
	add	x20, x19, #48
	ldr	w0, [x24]
Lloh53:
	adrp	x8, _mmIH_RB_BASE_RING1@GOTPAGE
Lloh54:
	ldr	x8, [x8, _mmIH_RB_BASE_RING1@GOTPAGEOFF]
Lloh55:
	ldr	w2, [x8]
	ldr	w8, [x19, #48]
	asr	w3, w8, #8
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh56:
	adrp	x8, _mmIH_RB_BASE_HI_RING1@GOTPAGE
Lloh57:
	ldr	x8, [x8, _mmIH_RB_BASE_HI_RING1@GOTPAGEOFF]
Lloh58:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh59:
	adrp	x22, _mmIH_RB_CNTL_RING1@GOTPAGE
Lloh60:
	ldr	x22, [x22, _mmIH_RB_CNTL_RING1@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	w1, #0
	bl	_RREG32_SOC15
	mov	x1, x0
	mov	x0, x20
	bl	_vega10_ih_rb_cntl
	ldr	w1, [x25]
Lloh61:
	adrp	x8, _WPTR_OVERFLOW_ENABLE@GOTPAGE
Lloh62:
	ldr	x8, [x8, _WPTR_OVERFLOW_ENABLE@GOTPAGEOFF]
Lloh63:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x25]
Lloh64:
	adrp	x8, _RB_FULL_DRAIN_ENABLE@GOTPAGE
Lloh65:
	ldr	x8, [x8, _RB_FULL_DRAIN_ENABLE@GOTPAGEOFF]
Lloh66:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x21, x0
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_12
; %bb.10:
	add	x0, x19, #12
Lloh67:
	adrp	x8, _PSP_REG_IH_RB_CNTL_RING1@GOTPAGE
Lloh68:
	ldr	x8, [x8, _PSP_REG_IH_RB_CNTL_RING1@GOTPAGEOFF]
Lloh69:
	ldr	w1, [x8]
	mov	x2, x21
	bl	_psp_reg_program
	cbz	x0, LBB0_13
; %bb.11:
Lloh70:
	adrp	x0, l_.str.1@PAGE
Lloh71:
	add	x0, x0, l_.str.1@PAGEOFF
	b	LBB0_18
LBB0_12:
	ldr	w0, [x24]
	ldr	w2, [x22]
	mov	w1, #0
	mov	x3, x21
	bl	_WREG32_SOC15
LBB0_13:
	ldr	w0, [x24]
Lloh72:
	adrp	x8, _mmIH_RB_WPTR_RING1@GOTPAGE
Lloh73:
	ldr	x8, [x8, _mmIH_RB_WPTR_RING1@GOTPAGEOFF]
Lloh74:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh75:
	adrp	x8, _mmIH_RB_RPTR_RING1@GOTPAGE
Lloh76:
	ldr	x8, [x8, _mmIH_RB_RPTR_RING1@GOTPAGEOFF]
Lloh77:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w21, [x24]
Lloh78:
	adrp	x8, _mmIH_DOORBELL_RPTR_RING1@GOTPAGE
Lloh79:
	ldr	x8, [x8, _mmIH_DOORBELL_RPTR_RING1@GOTPAGEOFF]
Lloh80:
	ldr	w22, [x8]
	mov	x0, x20
	bl	_vega10_ih_doorbell_rptr
	mov	x3, x0
	mov	x0, x21
	mov	w1, #0
	mov	x2, x22
	bl	_WREG32_SOC15
LBB0_14:
	ldr	x8, [x19, #24]
	cbz	x8, LBB0_21
; %bb.15:
	add	x20, x19, #16
	ldr	w0, [x24]
Lloh81:
	adrp	x8, _mmIH_RB_BASE_RING2@GOTPAGE
Lloh82:
	ldr	x8, [x8, _mmIH_RB_BASE_RING2@GOTPAGEOFF]
Lloh83:
	ldr	w2, [x8]
	ldr	w8, [x19, #16]
	asr	w3, w8, #8
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh84:
	adrp	x8, _mmIH_RB_BASE_HI_RING2@GOTPAGE
Lloh85:
	ldr	x8, [x8, _mmIH_RB_BASE_HI_RING2@GOTPAGEOFF]
Lloh86:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh87:
	adrp	x22, _mmIH_RB_CNTL_RING2@GOTPAGE
Lloh88:
	ldr	x22, [x22, _mmIH_RB_CNTL_RING2@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	w1, #0
	bl	_RREG32_SOC15
	mov	x1, x0
	mov	x0, x20
	bl	_vega10_ih_rb_cntl
	mov	x21, x0
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_19
; %bb.16:
	add	x0, x19, #12
Lloh89:
	adrp	x8, _PSP_REG_IH_RB_CNTL_RING2@GOTPAGE
Lloh90:
	ldr	x8, [x8, _PSP_REG_IH_RB_CNTL_RING2@GOTPAGEOFF]
Lloh91:
	ldr	w1, [x8]
	mov	x2, x21
	bl	_psp_reg_program
	cbz	x0, LBB0_20
; %bb.17:
Lloh92:
	adrp	x0, l_.str.2@PAGE
Lloh93:
	add	x0, x0, l_.str.2@PAGEOFF
LBB0_18:
	bl	_DRM_ERROR
Lloh94:
	adrp	x8, _ETIMEDOUT@GOTPAGE
Lloh95:
	ldr	x8, [x8, _ETIMEDOUT@GOTPAGEOFF]
Lloh96:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_22
LBB0_19:
	ldr	w0, [x24]
	ldr	w2, [x22]
	mov	w1, #0
	mov	x3, x21
	bl	_WREG32_SOC15
LBB0_20:
	ldr	w0, [x24]
Lloh97:
	adrp	x8, _mmIH_RB_WPTR_RING2@GOTPAGE
Lloh98:
	ldr	x8, [x8, _mmIH_RB_WPTR_RING2@GOTPAGEOFF]
Lloh99:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh100:
	adrp	x8, _mmIH_RB_RPTR_RING2@GOTPAGE
Lloh101:
	ldr	x8, [x8, _mmIH_RB_RPTR_RING2@GOTPAGEOFF]
Lloh102:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w21, [x24]
Lloh103:
	adrp	x8, _mmIH_DOORBELL_RPTR_RING2@GOTPAGE
Lloh104:
	ldr	x8, [x8, _mmIH_DOORBELL_RPTR_RING2@GOTPAGEOFF]
Lloh105:
	ldr	w22, [x8]
	mov	x0, x20
	bl	_vega10_ih_doorbell_rptr
	mov	x3, x0
	mov	x0, x21
	mov	w1, #0
	mov	x2, x22
	bl	_WREG32_SOC15
LBB0_21:
	ldr	w0, [x24]
Lloh106:
	adrp	x20, _mmIH_STORM_CLIENT_LIST_CNTL@GOTPAGE
Lloh107:
	ldr	x20, [x20, _mmIH_STORM_CLIENT_LIST_CNTL@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh108:
	adrp	x8, _IH_STORM_CLIENT_LIST_CNTL@GOTPAGE
Lloh109:
	ldr	x8, [x8, _IH_STORM_CLIENT_LIST_CNTL@GOTPAGEOFF]
Lloh110:
	ldr	w1, [x8]
Lloh111:
	adrp	x8, _CLIENT18_IS_STORM_CLIENT@GOTPAGE
Lloh112:
	ldr	x8, [x8, _CLIENT18_IS_STORM_CLIENT@GOTPAGEOFF]
Lloh113:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x24]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh114:
	adrp	x20, _mmIH_INT_FLOOD_CNTL@GOTPAGE
Lloh115:
	ldr	x20, [x20, _mmIH_INT_FLOOD_CNTL@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh116:
	adrp	x8, _IH_INT_FLOOD_CNTL@GOTPAGE
Lloh117:
	ldr	x8, [x8, _IH_INT_FLOOD_CNTL@GOTPAGEOFF]
Lloh118:
	ldr	w1, [x8]
Lloh119:
	adrp	x8, _FLOOD_CNTL_ENABLE@GOTPAGE
Lloh120:
	ldr	x8, [x8, _FLOOD_CNTL_ENABLE@GOTPAGEOFF]
Lloh121:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x24]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x19, #8]
	bl	_pci_set_master
	mov	x0, x19
	bl	_vega10_ih_enable_interrupts
	mov	w0, #0
LBB0_22:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh16
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpAdd	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGot	Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpAdd	Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGot	Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpAdd	Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGot	Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGot	Lloh106, Lloh107
	.cfi_endproc
                                        ; -- End function
	.comm	_OSSSYS,4,2                     ; @OSSSYS
	.comm	_mmIH_RB_BASE,4,2               ; @mmIH_RB_BASE
	.comm	_mmIH_RB_BASE_HI,4,2            ; @mmIH_RB_BASE_HI
	.comm	_mmIH_RB_CNTL,4,2               ; @mmIH_RB_CNTL
	.comm	_mmIH_CHICKEN,4,2               ; @mmIH_CHICKEN
	.comm	_IH_CHICKEN,4,2                 ; @IH_CHICKEN
	.comm	_MC_SPACE_GPA_ENABLE,4,2        ; @MC_SPACE_GPA_ENABLE
	.comm	_MC_SPACE_FBPA_ENABLE,4,2       ; @MC_SPACE_FBPA_ENABLE
	.comm	_IH_RB_CNTL,4,2                 ; @IH_RB_CNTL
	.comm	_RPTR_REARM,4,2                 ; @RPTR_REARM
	.comm	_PSP_REG_IH_RB_CNTL,4,2         ; @PSP_REG_IH_RB_CNTL
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"PSP program IH_RB_CNTL failed!\n"

	.comm	_ETIMEDOUT,4,2                  ; @ETIMEDOUT
	.comm	_CHIP_ARCTURUS,8,3              ; @CHIP_ARCTURUS
	.comm	_AMDGPU_FW_LOAD_DIRECT,8,3      ; @AMDGPU_FW_LOAD_DIRECT
	.comm	_CHIP_RENOIR,8,3                ; @CHIP_RENOIR
	.comm	_mmIH_RB_WPTR_ADDR_LO,4,2       ; @mmIH_RB_WPTR_ADDR_LO
	.comm	_mmIH_RB_WPTR_ADDR_HI,4,2       ; @mmIH_RB_WPTR_ADDR_HI
	.comm	_mmIH_RB_WPTR,4,2               ; @mmIH_RB_WPTR
	.comm	_mmIH_RB_RPTR,4,2               ; @mmIH_RB_RPTR
	.comm	_mmIH_DOORBELL_RPTR,4,2         ; @mmIH_DOORBELL_RPTR
	.comm	_mmIH_RB_BASE_RING1,4,2         ; @mmIH_RB_BASE_RING1
	.comm	_mmIH_RB_BASE_HI_RING1,4,2      ; @mmIH_RB_BASE_HI_RING1
	.comm	_mmIH_RB_CNTL_RING1,4,2         ; @mmIH_RB_CNTL_RING1
	.comm	_WPTR_OVERFLOW_ENABLE,4,2       ; @WPTR_OVERFLOW_ENABLE
	.comm	_RB_FULL_DRAIN_ENABLE,4,2       ; @RB_FULL_DRAIN_ENABLE
	.comm	_PSP_REG_IH_RB_CNTL_RING1,4,2   ; @PSP_REG_IH_RB_CNTL_RING1
l_.str.1:                               ; @.str.1
	.asciz	"program IH_RB_CNTL_RING1 failed!\n"

	.comm	_mmIH_RB_WPTR_RING1,4,2         ; @mmIH_RB_WPTR_RING1
	.comm	_mmIH_RB_RPTR_RING1,4,2         ; @mmIH_RB_RPTR_RING1
	.comm	_mmIH_DOORBELL_RPTR_RING1,4,2   ; @mmIH_DOORBELL_RPTR_RING1
	.comm	_mmIH_RB_BASE_RING2,4,2         ; @mmIH_RB_BASE_RING2
	.comm	_mmIH_RB_BASE_HI_RING2,4,2      ; @mmIH_RB_BASE_HI_RING2
	.comm	_mmIH_RB_CNTL_RING2,4,2         ; @mmIH_RB_CNTL_RING2
	.comm	_PSP_REG_IH_RB_CNTL_RING2,4,2   ; @PSP_REG_IH_RB_CNTL_RING2
l_.str.2:                               ; @.str.2
	.asciz	"program IH_RB_CNTL_RING2 failed!\n"

	.comm	_mmIH_RB_WPTR_RING2,4,2         ; @mmIH_RB_WPTR_RING2
	.comm	_mmIH_RB_RPTR_RING2,4,2         ; @mmIH_RB_RPTR_RING2
	.comm	_mmIH_DOORBELL_RPTR_RING2,4,2   ; @mmIH_DOORBELL_RPTR_RING2
	.comm	_mmIH_STORM_CLIENT_LIST_CNTL,4,2 ; @mmIH_STORM_CLIENT_LIST_CNTL
	.comm	_IH_STORM_CLIENT_LIST_CNTL,4,2  ; @IH_STORM_CLIENT_LIST_CNTL
	.comm	_CLIENT18_IS_STORM_CLIENT,4,2   ; @CLIENT18_IS_STORM_CLIENT
	.comm	_mmIH_INT_FLOOD_CNTL,4,2        ; @mmIH_INT_FLOOD_CNTL
	.comm	_IH_INT_FLOOD_CNTL,4,2          ; @IH_INT_FLOOD_CNTL
	.comm	_FLOOD_CNTL_ENABLE,4,2          ; @FLOOD_CNTL_ENABLE
	.no_dead_strip	_vega10_ih_irq_init
.subsections_via_symbols
