	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function nbio_v2_3_init_registers
_nbio_v2_3_init_registers:              ## @nbio_v2_3_init_registers
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_smnPCIE_CONFIG_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32_PCIE
	movq	%rax, %rbx
	movq	_PCIE_CONFIG_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_CI_SWUS_MAX_READ_REQUEST_SIZE_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r15), %esi
	movq	_CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%rax, %rdi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	cmpq	%rax, %rbx
	jne	LBB0_2
## %bb.1:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	movl	(%r14), %edi
	movq	%rax, %rsi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_PCIE                    ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_smnPCIE_CONFIG_CNTL,4,2        ## @smnPCIE_CONFIG_CNTL
	.comm	_PCIE_CONFIG_CNTL,4,2           ## @PCIE_CONFIG_CNTL
	.comm	_CI_SWUS_MAX_READ_REQUEST_SIZE_MODE,4,2 ## @CI_SWUS_MAX_READ_REQUEST_SIZE_MODE
	.comm	_CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV,4,2 ## @CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV
	.no_dead_strip	_nbio_v2_3_init_registers
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function nbio_v2_3_init_registers
_nbio_v2_3_init_registers:              ; @nbio_v2_3_init_registers
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
Lloh0:
	adrp	x20, _smnPCIE_CONFIG_CNTL@GOTPAGE
Lloh1:
	ldr	x20, [x20, _smnPCIE_CONFIG_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PCIE
	mov	x19, x0
Lloh2:
	adrp	x21, _PCIE_CONFIG_CNTL@GOTPAGE
Lloh3:
	ldr	x21, [x21, _PCIE_CONFIG_CNTL@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh4:
	adrp	x8, _CI_SWUS_MAX_READ_REQUEST_SIZE_MODE@GOTPAGE
Lloh5:
	ldr	x8, [x8, _CI_SWUS_MAX_READ_REQUEST_SIZE_MODE@GOTPAGEOFF]
Lloh6:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x21]
Lloh7:
	adrp	x8, _CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV@GOTPAGE
Lloh8:
	ldr	x8, [x8, _CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV@GOTPAGEOFF]
Lloh9:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	cmp	x19, x0
	b.ne	LBB0_2
; %bb.1:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_2:
	mov	x1, x0
	ldr	w0, [x20]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_WREG32_PCIE
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_smnPCIE_CONFIG_CNTL,4,2        ; @smnPCIE_CONFIG_CNTL
	.comm	_PCIE_CONFIG_CNTL,4,2           ; @PCIE_CONFIG_CNTL
	.comm	_CI_SWUS_MAX_READ_REQUEST_SIZE_MODE,4,2 ; @CI_SWUS_MAX_READ_REQUEST_SIZE_MODE
	.comm	_CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV,4,2 ; @CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV
	.no_dead_strip	_nbio_v2_3_init_registers
.subsections_via_symbols
