	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function sdma_v2_4_ring_emit_vm_flush
_sdma_v2_4_ring_emit_vm_flush:          ## @sdma_v2_4_ring_emit_vm_flush
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	callq	_amdgpu_gmc_emit_flush_gpu_tlb
	movq	_SDMA_OP_POLL_REGMEM@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_SDMA_PKT_HEADER_OP
	movl	%eax, %r14d
	xorl	%edi, %edi
	callq	_SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH
	movl	%eax, %ebx
	xorl	%edi, %edi
	callq	_SDMA_PKT_POLL_REGMEM_HEADER_FUNC
	orl	%eax, %ebx
	orl	%r14d, %ebx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_amdgpu_ring_write
	movq	_mmVM_INVALIDATE_REQUEST@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	shll	$2, %esi
	movq	%r15, %rdi
	callq	_amdgpu_ring_write
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
	movl	$4095, %edi                     ## imm = 0xFFF
	callq	_SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT
	movl	%eax, %ebx
	movl	$10, %edi
	callq	_SDMA_PKT_POLL_REGMEM_DW5_INTERVAL
	orl	%eax, %ebx
	movq	%r15, %rdi
	movl	%ebx, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_write              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_SDMA_OP_POLL_REGMEM,4,2        ## @SDMA_OP_POLL_REGMEM
	.comm	_mmVM_INVALIDATE_REQUEST,4,2    ## @mmVM_INVALIDATE_REQUEST
	.no_dead_strip	_sdma_v2_4_ring_emit_vm_flush
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function sdma_v2_4_ring_emit_vm_flush
_sdma_v2_4_ring_emit_vm_flush:          ; @sdma_v2_4_ring_emit_vm_flush
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_amdgpu_gmc_emit_flush_gpu_tlb
Lloh0:
	adrp	x8, _SDMA_OP_POLL_REGMEM@GOTPAGE
Lloh1:
	ldr	x8, [x8, _SDMA_OP_POLL_REGMEM@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_SDMA_PKT_HEADER_OP
	mov	x20, x0
	mov	w0, #0
	bl	_SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH
	orr	w20, w0, w20
	mov	w0, #0
	bl	_SDMA_PKT_POLL_REGMEM_HEADER_FUNC
	orr	w1, w20, w0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh3:
	adrp	x8, _mmVM_INVALIDATE_REQUEST@GOTPAGE
Lloh4:
	ldr	x8, [x8, _mmVM_INVALIDATE_REQUEST@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	lsl	w1, w8, #2
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_ring_write
	mov	w0, #4095
	bl	_SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT
	mov	x20, x0
	mov	w0, #10
	bl	_SDMA_PKT_POLL_REGMEM_DW5_INTERVAL
	orr	w1, w0, w20
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_amdgpu_ring_write
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_SDMA_OP_POLL_REGMEM,4,2        ; @SDMA_OP_POLL_REGMEM
	.comm	_mmVM_INVALIDATE_REQUEST,4,2    ; @mmVM_INVALIDATE_REQUEST
	.no_dead_strip	_sdma_v2_4_ring_emit_vm_flush
.subsections_via_symbols
