	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function sdma_v3_0_ring_emit_hdp_flush
_sdma_v3_0_ring_emit_hdp_flush:         ## @sdma_v3_0_ring_emit_hdp_flush
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	cmpq	$0, (%rdi)
	movq	_GPU_HDP_FLUSH_DONE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	jne	LBB0_1
## %bb.2:
	movq	_SDMA0@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_1:
	movq	_SDMA1@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %edx
	xorl	%edi, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	%eax, %r14d
	movq	_SDMA_OP_POLL_REGMEM@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_SDMA_PKT_HEADER_OP
	movl	%eax, %r15d
	movl	$1, %edi
	callq	_SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH
	movl	%eax, %ebx
	movl	$3, %edi
	callq	_SDMA_PKT_POLL_REGMEM_HEADER_FUNC
	orl	%eax, %ebx
	orl	%r15d, %ebx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_amdgpu_ring_write
	movq	_mmGPU_HDP_FLUSH_DONE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	shll	$2, %esi
	movq	%r12, %rdi
	callq	_amdgpu_ring_write
	movq	_mmGPU_HDP_FLUSH_REQ@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	shll	$2, %esi
	movq	%r12, %rdi
	callq	_amdgpu_ring_write
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_amdgpu_ring_write
	movq	%r12, %rdi
	movl	%r14d, %esi
	callq	_amdgpu_ring_write
	movl	$4095, %edi                     ## imm = 0xFFF
	callq	_SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT
	movl	%eax, %ebx
	movl	$10, %edi
	callq	_SDMA_PKT_POLL_REGMEM_DW5_INTERVAL
	orl	%eax, %ebx
	movq	%r12, %rdi
	movl	%ebx, %esi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_write              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_GPU_HDP_FLUSH_DONE,4,2         ## @GPU_HDP_FLUSH_DONE
	.comm	_SDMA0,4,2                      ## @SDMA0
	.comm	_SDMA1,4,2                      ## @SDMA1
	.comm	_SDMA_OP_POLL_REGMEM,4,2        ## @SDMA_OP_POLL_REGMEM
	.comm	_mmGPU_HDP_FLUSH_DONE,4,2       ## @mmGPU_HDP_FLUSH_DONE
	.comm	_mmGPU_HDP_FLUSH_REQ,4,2        ## @mmGPU_HDP_FLUSH_REQ
	.no_dead_strip	_sdma_v3_0_ring_emit_hdp_flush
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function sdma_v3_0_ring_emit_hdp_flush
_sdma_v3_0_ring_emit_hdp_flush:         ; @sdma_v3_0_ring_emit_hdp_flush
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x8, [x0]
Lloh0:
	adrp	x9, _GPU_HDP_FLUSH_DONE@GOTPAGE
Lloh1:
	ldr	x9, [x9, _GPU_HDP_FLUSH_DONE@GOTPAGEOFF]
Lloh2:
	adrp	x10, _SDMA0@GOTPAGE
Lloh3:
	ldr	x10, [x10, _SDMA0@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x9]
Lloh5:
	adrp	x9, _SDMA1@GOTPAGE
Lloh6:
	ldr	x9, [x9, _SDMA1@GOTPAGEOFF]
	cmp	x8, #0
	csel	x8, x10, x9, eq
	ldr	w2, [x8]
	mov	w0, #0
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x20, x0
Lloh7:
	adrp	x8, _SDMA_OP_POLL_REGMEM@GOTPAGE
Lloh8:
	ldr	x8, [x8, _SDMA_OP_POLL_REGMEM@GOTPAGEOFF]
Lloh9:
	ldr	w0, [x8]
	bl	_SDMA_PKT_HEADER_OP
	mov	x21, x0
	mov	w0, #1
	bl	_SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH
	orr	w21, w0, w21
	mov	w0, #3
	bl	_SDMA_PKT_POLL_REGMEM_HEADER_FUNC
	orr	w1, w21, w0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh10:
	adrp	x8, _mmGPU_HDP_FLUSH_DONE@GOTPAGE
Lloh11:
	ldr	x8, [x8, _mmGPU_HDP_FLUSH_DONE@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	lsl	w1, w8, #2
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh13:
	adrp	x8, _mmGPU_HDP_FLUSH_REQ@GOTPAGE
Lloh14:
	ldr	x8, [x8, _mmGPU_HDP_FLUSH_REQ@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
	lsl	w1, w8, #2
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	x1, x20
	bl	_amdgpu_ring_write
	mov	w0, #4095
	bl	_SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT
	mov	x20, x0
	mov	w0, #10
	bl	_SDMA_PKT_POLL_REGMEM_DW5_INTERVAL
	orr	w1, w0, w20
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_amdgpu_ring_write
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_GPU_HDP_FLUSH_DONE,4,2         ; @GPU_HDP_FLUSH_DONE
	.comm	_SDMA0,4,2                      ; @SDMA0
	.comm	_SDMA1,4,2                      ; @SDMA1
	.comm	_SDMA_OP_POLL_REGMEM,4,2        ; @SDMA_OP_POLL_REGMEM
	.comm	_mmGPU_HDP_FLUSH_DONE,4,2       ; @mmGPU_HDP_FLUSH_DONE
	.comm	_mmGPU_HDP_FLUSH_REQ,4,2        ; @mmGPU_HDP_FLUSH_REQ
	.no_dead_strip	_sdma_v3_0_ring_emit_hdp_flush
.subsections_via_symbols
