	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function cik_gpu_soft_reset
_cik_gpu_soft_reset:                    ## @cik_gpu_soft_reset
	.cfi_startproc
## %bb.0:
	testl	%esi, %esi
	je	LBB0_29
## %bb.1:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r15d
	movq	%rdi, %r14
	movl	4(%rdi), %edi
	leaq	L_.str(%rip), %rsi
	movl	%r15d, %edx
	callq	_dev_info
	movq	%r14, %rdi
	callq	_cik_print_gpu_status_regs
	movl	4(%r14), %ebx
	movq	_VM_CONTEXT1_PROTECTION_FAULT_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	leaq	L_.str.1(%rip), %rsi
	movl	%ebx, %edi
	movl	%eax, %edx
	callq	_dev_info
	movl	4(%r14), %ebx
	movq	_VM_CONTEXT1_PROTECTION_FAULT_STATUS@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_RREG32
	leaq	L_.str.2(%rip), %rsi
	movl	%ebx, %edi
	movl	%eax, %edx
	callq	_dev_info
	movq	%r14, %rdi
	callq	_cik_fini_pg
	movq	%r14, %rdi
	callq	_cik_fini_cg
	movq	%r14, %rdi
	callq	_cik_rlc_stop
	movq	_CP_ME_CNTL@GOTPCREL(%rip), %rax
	movq	_CP_ME_HALT@GOTPCREL(%rip), %rcx
	movq	_CP_PFP_HALT@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	orl	(%rcx), %esi
	movq	(%rax), %rdi
	movq	_CP_CE_HALT@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	callq	_WREG32
	movq	_CP_MEC_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movq	_MEC_ME1_HALT@GOTPCREL(%rip), %rax
	movq	_MEC_ME2_HALT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	callq	_WREG32
	movq	_RADEON_RESET_DMA@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_3
## %bb.2:
	movq	_SDMA0_ME_CNTL@GOTPCREL(%rip), %r13
	movq	_SDMA0_REGISTER_OFFSET@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	addq	(%r13), %rdi
	callq	_RREG32
	movq	_SDMA_HALT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	(%rbx), %rdi
	addq	(%r13), %rdi
	movl	%eax, %esi
	callq	_WREG32
LBB0_3:
	movq	_RADEON_RESET_DMA1@GOTPCREL(%rip), %r12
	testl	%r15d, (%r12)
	je	LBB0_5
## %bb.4:
	movq	_SDMA0_ME_CNTL@GOTPCREL(%rip), %r13
	movq	_SDMA1_REGISTER_OFFSET@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	addq	(%r13), %rdi
	callq	_RREG32
	movq	_SDMA_HALT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	(%rbx), %rdi
	addq	(%r13), %rdi
	movl	%eax, %esi
	callq	_WREG32
LBB0_5:
	leaq	-48(%rbp), %rsi
	movq	%r14, %rdi
	callq	_evergreen_mc_stop
	movq	%r14, %rdi
	callq	_evergreen_mc_wait_for_idle
	testq	%rax, %rax
	je	LBB0_7
## %bb.6:
	movl	4(%r14), %edi
	leaq	L_.str.3(%rip), %rsi
	callq	_dev_warn
LBB0_7:
	movq	_RADEON_RESET_GFX@GOTPCREL(%rip), %rax
	movq	_RADEON_RESET_COMPUTE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movq	_RADEON_RESET_CP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	orl	%edx, %esi
	movq	_SOFT_RESET_CP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_SOFT_RESET_GFX@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	orl	%eax, %edi
	andl	%r15d, %edx
	movq	_SOFT_RESET_GRBM@GOTPCREL(%rip), %rcx
	cmovel	%edx, %eax
	movl	(%rcx), %ecx
	cmovnel	%ecx, %edx
	testl	%r15d, %esi
	cmovnel	%edi, %eax
	movq	_RADEON_RESET_DMA@GOTPCREL(%rip), %rsi
	movl	(%rsi), %r13d
	andl	%r15d, %r13d
	je	LBB0_9
## %bb.8:
	movq	_SOFT_RESET_SDMA@GOTPCREL(%rip), %rsi
	movl	(%rsi), %r13d
LBB0_9:
	movl	(%r12), %esi
	andl	%r15d, %esi
	je	LBB0_11
## %bb.10:
	movq	_SOFT_RESET_SDMA1@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
LBB0_11:
	movq	_RADEON_RESET_DISPLAY@GOTPCREL(%rip), %rdi
	movl	(%rdi), %edi
	andl	%r15d, %edi
	je	LBB0_13
## %bb.12:
	movq	_SOFT_RESET_DC@GOTPCREL(%rip), %rdi
	movl	(%rdi), %edi
LBB0_13:
	movq	_RADEON_RESET_RLC@GOTPCREL(%rip), %rbx
	movl	(%rbx), %r12d
	andl	%r15d, %r12d
	je	LBB0_15
## %bb.14:
	movq	_SOFT_RESET_RLC@GOTPCREL(%rip), %rbx
	movl	(%rbx), %r12d
LBB0_15:
	orl	%edx, %r13d
	orl	%edi, %esi
	movq	_RADEON_RESET_SEM@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	andl	%r15d, %edx
	je	LBB0_17
## %bb.16:
	movq	_SOFT_RESET_SEM@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
LBB0_17:
	orl	%esi, %r13d
	movq	_RADEON_RESET_IH@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	andl	%r15d, %esi
	je	LBB0_19
## %bb.18:
	movq	_SOFT_RESET_IH@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
LBB0_19:
	orl	%esi, %edx
	movq	_RADEON_RESET_GRBM@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	andl	%r15d, %esi
	cmovel	%esi, %ecx
	orl	%edx, %ecx
	orl	%ecx, %r13d
	movq	_RADEON_RESET_VMC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%r15d, %ecx
	je	LBB0_21
## %bb.20:
	movq	_SOFT_RESET_VMC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_21:
	orl	%ecx, %r13d
	orl	%eax, %r12d
	movq	_RADEON_IS_IGP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r14)
	jne	LBB0_24
## %bb.22:
	movq	_RADEON_RESET_MC@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_24
## %bb.23:
	movq	_SOFT_RESET_MC@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
LBB0_24:
	testl	%r12d, %r12d
	je	LBB0_26
## %bb.25:
	movq	_GRBM_SOFT_RESET@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	callq	_RREG32
	movl	%eax, %ebx
	orl	%r12d, %ebx
	movl	4(%r14), %edi
	leaq	L_.str.4(%rip), %rsi
	movl	%ebx, %edx
	callq	_dev_info
	movq	(%r15), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	(%r15), %rdi
	callq	_RREG32
	movl	%eax, %ebx
	movl	$50, %edi
	callq	_udelay
	notl	%r12d
	andl	%ebx, %r12d
	movq	(%r15), %rdi
	movl	%r12d, %esi
	callq	_WREG32
	movq	(%r15), %rdi
	callq	_RREG32
LBB0_26:
	testl	%r13d, %r13d
	je	LBB0_28
## %bb.27:
	movq	_SRBM_SOFT_RESET@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	callq	_RREG32
	movl	%eax, %ebx
	orl	%r13d, %ebx
	movl	4(%r14), %edi
	leaq	L_.str.5(%rip), %rsi
	movl	%ebx, %edx
	callq	_dev_info
	movq	(%r15), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	(%r15), %rdi
	callq	_RREG32
	movl	%eax, %ebx
	movl	$50, %edi
	callq	_udelay
	notl	%r13d
	andl	%ebx, %r13d
	movq	(%r15), %rdi
	movl	%r13d, %esi
	callq	_WREG32
	movq	(%r15), %rdi
	callq	_RREG32
LBB0_28:
	movl	$50, %edi
	callq	_udelay
	leaq	-48(%rbp), %rsi
	movq	%r14, %rdi
	callq	_evergreen_mc_resume
	movl	$50, %edi
	callq	_udelay
	movq	%r14, %rdi
	callq	_cik_print_gpu_status_regs
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
LBB0_29:
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"GPU softreset: 0x%08X\n"

L_.str.1:                               ## @.str.1
	.asciz	"  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n"

	.comm	_VM_CONTEXT1_PROTECTION_FAULT_ADDR,8,3 ## @VM_CONTEXT1_PROTECTION_FAULT_ADDR
L_.str.2:                               ## @.str.2
	.asciz	"  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n"

	.comm	_VM_CONTEXT1_PROTECTION_FAULT_STATUS,8,3 ## @VM_CONTEXT1_PROTECTION_FAULT_STATUS
	.comm	_CP_ME_CNTL,8,3                 ## @CP_ME_CNTL
	.comm	_CP_ME_HALT,4,2                 ## @CP_ME_HALT
	.comm	_CP_PFP_HALT,4,2                ## @CP_PFP_HALT
	.comm	_CP_CE_HALT,4,2                 ## @CP_CE_HALT
	.comm	_CP_MEC_CNTL,8,3                ## @CP_MEC_CNTL
	.comm	_MEC_ME1_HALT,4,2               ## @MEC_ME1_HALT
	.comm	_MEC_ME2_HALT,4,2               ## @MEC_ME2_HALT
	.comm	_RADEON_RESET_DMA,4,2           ## @RADEON_RESET_DMA
	.comm	_SDMA0_ME_CNTL,8,3              ## @SDMA0_ME_CNTL
	.comm	_SDMA0_REGISTER_OFFSET,8,3      ## @SDMA0_REGISTER_OFFSET
	.comm	_SDMA_HALT,4,2                  ## @SDMA_HALT
	.comm	_RADEON_RESET_DMA1,4,2          ## @RADEON_RESET_DMA1
	.comm	_SDMA1_REGISTER_OFFSET,8,3      ## @SDMA1_REGISTER_OFFSET
L_.str.3:                               ## @.str.3
	.asciz	"Wait for MC idle timedout !\n"

	.comm	_RADEON_RESET_GFX,4,2           ## @RADEON_RESET_GFX
	.comm	_RADEON_RESET_COMPUTE,4,2       ## @RADEON_RESET_COMPUTE
	.comm	_RADEON_RESET_CP,4,2            ## @RADEON_RESET_CP
	.comm	_SOFT_RESET_CP,4,2              ## @SOFT_RESET_CP
	.comm	_SOFT_RESET_GFX,4,2             ## @SOFT_RESET_GFX
	.comm	_SOFT_RESET_GRBM,4,2            ## @SOFT_RESET_GRBM
	.comm	_SOFT_RESET_SDMA,4,2            ## @SOFT_RESET_SDMA
	.comm	_SOFT_RESET_SDMA1,4,2           ## @SOFT_RESET_SDMA1
	.comm	_RADEON_RESET_DISPLAY,4,2       ## @RADEON_RESET_DISPLAY
	.comm	_SOFT_RESET_DC,4,2              ## @SOFT_RESET_DC
	.comm	_RADEON_RESET_RLC,4,2           ## @RADEON_RESET_RLC
	.comm	_SOFT_RESET_RLC,4,2             ## @SOFT_RESET_RLC
	.comm	_RADEON_RESET_SEM,4,2           ## @RADEON_RESET_SEM
	.comm	_SOFT_RESET_SEM,4,2             ## @SOFT_RESET_SEM
	.comm	_RADEON_RESET_IH,4,2            ## @RADEON_RESET_IH
	.comm	_SOFT_RESET_IH,4,2              ## @SOFT_RESET_IH
	.comm	_RADEON_RESET_GRBM,4,2          ## @RADEON_RESET_GRBM
	.comm	_RADEON_RESET_VMC,4,2           ## @RADEON_RESET_VMC
	.comm	_SOFT_RESET_VMC,4,2             ## @SOFT_RESET_VMC
	.comm	_RADEON_IS_IGP,4,2              ## @RADEON_IS_IGP
	.comm	_RADEON_RESET_MC,4,2            ## @RADEON_RESET_MC
	.comm	_SOFT_RESET_MC,4,2              ## @SOFT_RESET_MC
	.comm	_GRBM_SOFT_RESET,8,3            ## @GRBM_SOFT_RESET
L_.str.4:                               ## @.str.4
	.asciz	"GRBM_SOFT_RESET=0x%08X\n"

	.comm	_SRBM_SOFT_RESET,8,3            ## @SRBM_SOFT_RESET
L_.str.5:                               ## @.str.5
	.asciz	"SRBM_SOFT_RESET=0x%08X\n"

	.no_dead_strip	_cik_gpu_soft_reset
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cik_gpu_soft_reset
_cik_gpu_soft_reset:                    ; @cik_gpu_soft_reset
	.cfi_startproc
; %bb.0:
	cbz	w1, LBB0_15
; %bb.1:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x1
	mov	x19, x0
	ldr	w0, [x0, #4]
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	mov	x2, x20
	bl	_dev_info
	mov	x0, x19
	bl	_cik_print_gpu_status_regs
	ldr	w21, [x19, #4]
Lloh2:
	adrp	x8, _VM_CONTEXT1_PROTECTION_FAULT_ADDR@GOTPAGE
Lloh3:
	ldr	x8, [x8, _VM_CONTEXT1_PROTECTION_FAULT_ADDR@GOTPAGEOFF]
Lloh4:
	ldr	x0, [x8]
	bl	_RREG32
	mov	x2, x0
Lloh5:
	adrp	x1, l_.str.1@PAGE
Lloh6:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x21
	bl	_dev_info
	ldr	w21, [x19, #4]
Lloh7:
	adrp	x8, _VM_CONTEXT1_PROTECTION_FAULT_STATUS@GOTPAGE
Lloh8:
	ldr	x8, [x8, _VM_CONTEXT1_PROTECTION_FAULT_STATUS@GOTPAGEOFF]
Lloh9:
	ldr	x0, [x8]
	bl	_RREG32
	mov	x2, x0
Lloh10:
	adrp	x1, l_.str.2@PAGE
Lloh11:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x0, x21
	bl	_dev_info
	mov	x0, x19
	bl	_cik_fini_pg
	mov	x0, x19
	bl	_cik_fini_cg
	mov	x0, x19
	bl	_cik_rlc_stop
Lloh12:
	adrp	x8, _CP_ME_CNTL@GOTPAGE
Lloh13:
	ldr	x8, [x8, _CP_ME_CNTL@GOTPAGEOFF]
Lloh14:
	ldr	x0, [x8]
Lloh15:
	adrp	x8, _CP_ME_HALT@GOTPAGE
Lloh16:
	ldr	x8, [x8, _CP_ME_HALT@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
Lloh18:
	adrp	x9, _CP_PFP_HALT@GOTPAGE
Lloh19:
	ldr	x9, [x9, _CP_PFP_HALT@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh21:
	adrp	x9, _CP_CE_HALT@GOTPAGE
Lloh22:
	ldr	x9, [x9, _CP_CE_HALT@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	orr	w1, w8, w9
	bl	_WREG32
Lloh24:
	adrp	x8, _CP_MEC_CNTL@GOTPAGE
Lloh25:
	ldr	x8, [x8, _CP_MEC_CNTL@GOTPAGEOFF]
Lloh26:
	adrp	x9, _MEC_ME1_HALT@GOTPAGE
Lloh27:
	ldr	x9, [x9, _MEC_ME1_HALT@GOTPAGEOFF]
Lloh28:
	ldr	x0, [x8]
Lloh29:
	ldr	w8, [x9]
Lloh30:
	adrp	x9, _MEC_ME2_HALT@GOTPAGE
Lloh31:
	ldr	x9, [x9, _MEC_ME2_HALT@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	orr	w1, w9, w8
	bl	_WREG32
Lloh33:
	adrp	x21, _RADEON_RESET_DMA@GOTPAGE
Lloh34:
	ldr	x21, [x21, _RADEON_RESET_DMA@GOTPAGEOFF]
	ldr	w8, [x21]
Lloh35:
	adrp	x23, _SDMA0_ME_CNTL@GOTPAGE
Lloh36:
	ldr	x23, [x23, _SDMA0_ME_CNTL@GOTPAGEOFF]
Lloh37:
	adrp	x24, _SDMA_HALT@GOTPAGE
Lloh38:
	ldr	x24, [x24, _SDMA_HALT@GOTPAGEOFF]
	tst	w8, w20
	b.eq	LBB0_3
; %bb.2:
	ldr	x8, [x23]
Lloh39:
	adrp	x22, _SDMA0_REGISTER_OFFSET@GOTPAGE
Lloh40:
	ldr	x22, [x22, _SDMA0_REGISTER_OFFSET@GOTPAGEOFF]
	ldr	x9, [x22]
	add	x0, x9, x8
	bl	_RREG32
	ldr	w8, [x24]
	orr	w1, w8, w0
	ldr	x8, [x23]
	ldr	x9, [x22]
	add	x0, x9, x8
	bl	_WREG32
LBB0_3:
Lloh41:
	adrp	x22, _RADEON_RESET_DMA1@GOTPAGE
Lloh42:
	ldr	x22, [x22, _RADEON_RESET_DMA1@GOTPAGEOFF]
	ldr	w8, [x22]
	tst	w8, w20
	b.eq	LBB0_5
; %bb.4:
	ldr	x8, [x23]
Lloh43:
	adrp	x25, _SDMA1_REGISTER_OFFSET@GOTPAGE
Lloh44:
	ldr	x25, [x25, _SDMA1_REGISTER_OFFSET@GOTPAGEOFF]
	ldr	x9, [x25]
	add	x0, x9, x8
	bl	_RREG32
	ldr	w8, [x24]
	orr	w1, w8, w0
	ldr	x8, [x23]
	ldr	x9, [x25]
	add	x0, x9, x8
	bl	_WREG32
LBB0_5:
	add	x1, sp, #8
	mov	x0, x19
	bl	_evergreen_mc_stop
	mov	x0, x19
	bl	_evergreen_mc_wait_for_idle
	cbz	x0, LBB0_7
; %bb.6:
	ldr	w0, [x19, #4]
Lloh45:
	adrp	x1, l_.str.3@PAGE
Lloh46:
	add	x1, x1, l_.str.3@PAGEOFF
	bl	_dev_warn
LBB0_7:
Lloh47:
	adrp	x8, _RADEON_RESET_GFX@GOTPAGE
Lloh48:
	ldr	x8, [x8, _RADEON_RESET_GFX@GOTPAGEOFF]
Lloh49:
	ldr	w8, [x8]
Lloh50:
	adrp	x9, _RADEON_RESET_COMPUTE@GOTPAGE
Lloh51:
	ldr	x9, [x9, _RADEON_RESET_COMPUTE@GOTPAGEOFF]
Lloh52:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh53:
	adrp	x9, _RADEON_RESET_CP@GOTPAGE
Lloh54:
	ldr	x9, [x9, _RADEON_RESET_CP@GOTPAGEOFF]
Lloh55:
	ldr	w9, [x9]
Lloh56:
	adrp	x10, _SOFT_RESET_CP@GOTPAGE
Lloh57:
	ldr	x10, [x10, _SOFT_RESET_CP@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh58:
	ldr	w10, [x10]
Lloh59:
	adrp	x11, _SOFT_RESET_GFX@GOTPAGE
Lloh60:
	ldr	x11, [x11, _SOFT_RESET_GFX@GOTPAGEOFF]
Lloh61:
	ldr	w11, [x11]
	orr	w11, w11, w10
Lloh62:
	adrp	x12, _SOFT_RESET_GRBM@GOTPAGE
Lloh63:
	ldr	x12, [x12, _SOFT_RESET_GRBM@GOTPAGEOFF]
Lloh64:
	ldr	w12, [x12]
	tst	w9, w20
	csel	w9, wzr, w10, eq
	csel	w10, wzr, w12, eq
	tst	w8, w20
	csel	w8, w9, w11, eq
	ldr	w9, [x21]
Lloh65:
	adrp	x11, _SOFT_RESET_SDMA@GOTPAGE
Lloh66:
	ldr	x11, [x11, _SOFT_RESET_SDMA@GOTPAGEOFF]
Lloh67:
	ldr	w11, [x11]
	tst	w9, w20
	csel	w9, wzr, w11, eq
	orr	w9, w9, w10
	ldr	w10, [x22]
Lloh68:
	adrp	x11, _SOFT_RESET_SDMA1@GOTPAGE
Lloh69:
	ldr	x11, [x11, _SOFT_RESET_SDMA1@GOTPAGEOFF]
Lloh70:
	ldr	w11, [x11]
	tst	w10, w20
	csel	w10, wzr, w11, eq
	orr	w9, w9, w10
Lloh71:
	adrp	x10, _RADEON_RESET_DISPLAY@GOTPAGE
Lloh72:
	ldr	x10, [x10, _RADEON_RESET_DISPLAY@GOTPAGEOFF]
Lloh73:
	ldr	w10, [x10]
Lloh74:
	adrp	x11, _SOFT_RESET_DC@GOTPAGE
Lloh75:
	ldr	x11, [x11, _SOFT_RESET_DC@GOTPAGEOFF]
Lloh76:
	ldr	w11, [x11]
	tst	w10, w20
	csel	w10, wzr, w11, eq
	orr	w9, w9, w10
Lloh77:
	adrp	x10, _RADEON_RESET_RLC@GOTPAGE
Lloh78:
	ldr	x10, [x10, _RADEON_RESET_RLC@GOTPAGEOFF]
Lloh79:
	ldr	w10, [x10]
Lloh80:
	adrp	x11, _SOFT_RESET_RLC@GOTPAGE
Lloh81:
	ldr	x11, [x11, _SOFT_RESET_RLC@GOTPAGEOFF]
Lloh82:
	ldr	w11, [x11]
	tst	w10, w20
	csel	w10, wzr, w11, eq
	orr	w22, w10, w8
Lloh83:
	adrp	x8, _RADEON_RESET_SEM@GOTPAGE
Lloh84:
	ldr	x8, [x8, _RADEON_RESET_SEM@GOTPAGEOFF]
Lloh85:
	ldr	w8, [x8]
Lloh86:
	adrp	x10, _SOFT_RESET_SEM@GOTPAGE
Lloh87:
	ldr	x10, [x10, _SOFT_RESET_SEM@GOTPAGEOFF]
Lloh88:
	ldr	w10, [x10]
	tst	w8, w20
	csel	w8, wzr, w10, eq
	orr	w8, w9, w8
Lloh89:
	adrp	x9, _RADEON_RESET_IH@GOTPAGE
Lloh90:
	ldr	x9, [x9, _RADEON_RESET_IH@GOTPAGEOFF]
Lloh91:
	ldr	w9, [x9]
Lloh92:
	adrp	x10, _SOFT_RESET_IH@GOTPAGE
Lloh93:
	ldr	x10, [x10, _SOFT_RESET_IH@GOTPAGEOFF]
Lloh94:
	ldr	w10, [x10]
	tst	w9, w20
	csel	w9, wzr, w10, eq
	orr	w8, w8, w9
Lloh95:
	adrp	x9, _RADEON_RESET_GRBM@GOTPAGE
Lloh96:
	ldr	x9, [x9, _RADEON_RESET_GRBM@GOTPAGEOFF]
Lloh97:
	ldr	w9, [x9]
	tst	w9, w20
	csel	w9, wzr, w12, eq
	orr	w8, w8, w9
Lloh98:
	adrp	x9, _RADEON_RESET_VMC@GOTPAGE
Lloh99:
	ldr	x9, [x9, _RADEON_RESET_VMC@GOTPAGEOFF]
Lloh100:
	ldr	w9, [x9]
Lloh101:
	adrp	x10, _SOFT_RESET_VMC@GOTPAGE
Lloh102:
	ldr	x10, [x10, _SOFT_RESET_VMC@GOTPAGEOFF]
Lloh103:
	ldr	w10, [x10]
	tst	w9, w20
	csel	w9, wzr, w10, eq
	orr	w21, w8, w9
	ldr	w8, [x19]
Lloh104:
	adrp	x9, _RADEON_IS_IGP@GOTPAGE
Lloh105:
	ldr	x9, [x9, _RADEON_IS_IGP@GOTPAGEOFF]
Lloh106:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_10
; %bb.8:
Lloh107:
	adrp	x8, _RADEON_RESET_MC@GOTPAGE
Lloh108:
	ldr	x8, [x8, _RADEON_RESET_MC@GOTPAGEOFF]
Lloh109:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_10
; %bb.9:
Lloh110:
	adrp	x8, _SOFT_RESET_MC@GOTPAGE
Lloh111:
	ldr	x8, [x8, _SOFT_RESET_MC@GOTPAGEOFF]
Lloh112:
	ldr	w8, [x8]
	orr	w21, w8, w21
LBB0_10:
	cbz	w22, LBB0_12
; %bb.11:
Lloh113:
	adrp	x23, _GRBM_SOFT_RESET@GOTPAGE
Lloh114:
	ldr	x23, [x23, _GRBM_SOFT_RESET@GOTPAGEOFF]
	ldr	x0, [x23]
	bl	_RREG32
	orr	w20, w0, w22
	ldr	w0, [x19, #4]
Lloh115:
	adrp	x1, l_.str.4@PAGE
Lloh116:
	add	x1, x1, l_.str.4@PAGEOFF
	mov	x2, x20
	bl	_dev_info
	ldr	x0, [x23]
	mov	x1, x20
	bl	_WREG32
	ldr	x0, [x23]
	bl	_RREG32
	mov	x20, x0
	mov	w0, #50
	bl	_udelay
	bic	w1, w20, w22
	ldr	x0, [x23]
	bl	_WREG32
	ldr	x0, [x23]
	bl	_RREG32
LBB0_12:
	cbz	w21, LBB0_14
; %bb.13:
Lloh117:
	adrp	x22, _SRBM_SOFT_RESET@GOTPAGE
Lloh118:
	ldr	x22, [x22, _SRBM_SOFT_RESET@GOTPAGEOFF]
	ldr	x0, [x22]
	bl	_RREG32
	orr	w20, w0, w21
	ldr	w0, [x19, #4]
Lloh119:
	adrp	x1, l_.str.5@PAGE
Lloh120:
	add	x1, x1, l_.str.5@PAGEOFF
	mov	x2, x20
	bl	_dev_info
	ldr	x0, [x22]
	mov	x1, x20
	bl	_WREG32
	ldr	x0, [x22]
	bl	_RREG32
	mov	x20, x0
	mov	w0, #50
	bl	_udelay
	bic	w1, w20, w21
	ldr	x0, [x22]
	bl	_WREG32
	ldr	x0, [x22]
	bl	_RREG32
LBB0_14:
	mov	w0, #50
	bl	_udelay
	add	x1, sp, #8
	mov	x0, x19
	bl	_evergreen_mc_resume
	mov	w0, #50
	bl	_udelay
	mov	x0, x19
	bl	_cik_print_gpu_status_regs
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
LBB0_15:
	.cfi_def_cfa wsp, 0
	.cfi_same_value w30
	.cfi_same_value w29
	.cfi_same_value w19
	.cfi_same_value w20
	.cfi_same_value w21
	.cfi_same_value w22
	.cfi_same_value w23
	.cfi_same_value w24
	.cfi_same_value w25
	.cfi_same_value w26
	ret
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh28
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpAdd	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpAdd	Lloh115, Lloh116
	.loh AdrpLdrGot	Lloh113, Lloh114
	.loh AdrpAdd	Lloh119, Lloh120
	.loh AdrpLdrGot	Lloh117, Lloh118
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"GPU softreset: 0x%08X\n"

l_.str.1:                               ; @.str.1
	.asciz	"  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n"

	.comm	_VM_CONTEXT1_PROTECTION_FAULT_ADDR,8,3 ; @VM_CONTEXT1_PROTECTION_FAULT_ADDR
l_.str.2:                               ; @.str.2
	.asciz	"  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n"

	.comm	_VM_CONTEXT1_PROTECTION_FAULT_STATUS,8,3 ; @VM_CONTEXT1_PROTECTION_FAULT_STATUS
	.comm	_CP_ME_CNTL,8,3                 ; @CP_ME_CNTL
	.comm	_CP_ME_HALT,4,2                 ; @CP_ME_HALT
	.comm	_CP_PFP_HALT,4,2                ; @CP_PFP_HALT
	.comm	_CP_CE_HALT,4,2                 ; @CP_CE_HALT
	.comm	_CP_MEC_CNTL,8,3                ; @CP_MEC_CNTL
	.comm	_MEC_ME1_HALT,4,2               ; @MEC_ME1_HALT
	.comm	_MEC_ME2_HALT,4,2               ; @MEC_ME2_HALT
	.comm	_RADEON_RESET_DMA,4,2           ; @RADEON_RESET_DMA
	.comm	_SDMA0_ME_CNTL,8,3              ; @SDMA0_ME_CNTL
	.comm	_SDMA0_REGISTER_OFFSET,8,3      ; @SDMA0_REGISTER_OFFSET
	.comm	_SDMA_HALT,4,2                  ; @SDMA_HALT
	.comm	_RADEON_RESET_DMA1,4,2          ; @RADEON_RESET_DMA1
	.comm	_SDMA1_REGISTER_OFFSET,8,3      ; @SDMA1_REGISTER_OFFSET
l_.str.3:                               ; @.str.3
	.asciz	"Wait for MC idle timedout !\n"

	.comm	_RADEON_RESET_GFX,4,2           ; @RADEON_RESET_GFX
	.comm	_RADEON_RESET_COMPUTE,4,2       ; @RADEON_RESET_COMPUTE
	.comm	_RADEON_RESET_CP,4,2            ; @RADEON_RESET_CP
	.comm	_SOFT_RESET_CP,4,2              ; @SOFT_RESET_CP
	.comm	_SOFT_RESET_GFX,4,2             ; @SOFT_RESET_GFX
	.comm	_SOFT_RESET_GRBM,4,2            ; @SOFT_RESET_GRBM
	.comm	_SOFT_RESET_SDMA,4,2            ; @SOFT_RESET_SDMA
	.comm	_SOFT_RESET_SDMA1,4,2           ; @SOFT_RESET_SDMA1
	.comm	_RADEON_RESET_DISPLAY,4,2       ; @RADEON_RESET_DISPLAY
	.comm	_SOFT_RESET_DC,4,2              ; @SOFT_RESET_DC
	.comm	_RADEON_RESET_RLC,4,2           ; @RADEON_RESET_RLC
	.comm	_SOFT_RESET_RLC,4,2             ; @SOFT_RESET_RLC
	.comm	_RADEON_RESET_SEM,4,2           ; @RADEON_RESET_SEM
	.comm	_SOFT_RESET_SEM,4,2             ; @SOFT_RESET_SEM
	.comm	_RADEON_RESET_IH,4,2            ; @RADEON_RESET_IH
	.comm	_SOFT_RESET_IH,4,2              ; @SOFT_RESET_IH
	.comm	_RADEON_RESET_GRBM,4,2          ; @RADEON_RESET_GRBM
	.comm	_RADEON_RESET_VMC,4,2           ; @RADEON_RESET_VMC
	.comm	_SOFT_RESET_VMC,4,2             ; @SOFT_RESET_VMC
	.comm	_RADEON_IS_IGP,4,2              ; @RADEON_IS_IGP
	.comm	_RADEON_RESET_MC,4,2            ; @RADEON_RESET_MC
	.comm	_SOFT_RESET_MC,4,2              ; @SOFT_RESET_MC
	.comm	_GRBM_SOFT_RESET,8,3            ; @GRBM_SOFT_RESET
l_.str.4:                               ; @.str.4
	.asciz	"GRBM_SOFT_RESET=0x%08X\n"

	.comm	_SRBM_SOFT_RESET,8,3            ; @SRBM_SOFT_RESET
l_.str.5:                               ; @.str.5
	.asciz	"SRBM_SOFT_RESET=0x%08X\n"

	.no_dead_strip	_cik_gpu_soft_reset
.subsections_via_symbols
