	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dbgdev_diq_submit_ib
_dbgdev_diq_submit_ib:                  ## @dbgdev_diq_submit_ib
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%r8, %rbx
	movl	%edx, %r13d
	movl	%esi, %r14d
	movq	%rdi, %r15
	xorl	%edi, %edi
	testq	%r8, %r8
	sete	%dil
	callq	_WARN_ON
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r14d, %r14d
	subl	(%rax), %r14d
	jmp	LBB0_7
LBB0_2:
	movl	%r14d, -44(%rbp)                ## 4-byte Spill
	movq	8(%r15), %r12
	leaq	-56(%rbp), %rdx
	movl	$30, %esi
	movq	%r12, %rdi
	callq	*(%r12)
	testl	%eax, %eax
	je	LBB0_4
## %bb.3:
	movl	%eax, %r14d
	leaq	L_.str(%rip), %rdi
	callq	_pr_err
	jmp	LBB0_7
LBB0_4:
	movq	-56(%rbp), %rdi
	movl	$120, %edx
	xorl	%esi, %esi
	callq	_memset
	movq	%r15, %rcx
	movq	-56(%rbp), %r15
	movl	$3, 16(%r15)
	movq	_IT_INDIRECT_BUFFER_PASID@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 32(%r15)
	movq	_PM4_TYPE_3@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 24(%r15)
	sarl	$2, %r13d
	movl	%r13d, 12(%r15)
	shrl	$2, %ebx
	andl	$1048575, %ebx                  ## imm = 0xFFFFF
	orl	$-2139095040, %ebx              ## imm = 0x80800000
	movl	%ebx, (%r15)
	movl	-44(%rbp), %eax                 ## 4-byte Reload
	movl	%eax, 4(%r15)
	movq	%rcx, %r13
	movl	(%rcx), %edi
	leaq	-64(%rbp), %rdx
	movl	$4, %esi
	callq	_kfd_gtt_sa_allocate
	testl	%eax, %eax
	je	LBB0_6
## %bb.5:
	movl	%eax, %r14d
	leaq	L_.str.1(%rip), %rdi
	callq	_pr_err
	movq	%r12, %rdi
	callq	*16(%r12)
	jmp	LBB0_7
LBB0_6:
	movq	-64(%rbp), %rax
	movq	8(%rax), %r14
	movq	_QUEUESTATE__ACTIVE_COMPLETION_PENDING@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, (%r14)
	movq	_IT_RELEASE_MEM@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, 112(%r15)
	movq	_PM4_TYPE_3@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, 104(%r15)
	movl	$18, 96(%r15)
	movq	_CACHE_FLUSH_AND_INV_TS_EVENT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, 88(%r15)
	movq	_event_index___release_mem__end_of_pipe@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, 84(%r15)
	movq	_cache_policy___release_mem__lru@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, 80(%r15)
	movq	$0, 72(%r15)
	movl	$1, 64(%r15)
	movl	(%rax), %eax
	sarl	$2, %eax
	movl	%eax, 60(%r15)
	movq	_data_sel___release_mem__send_64_bit_data@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 52(%r15)
	movq	_int_sel___release_mem__send_data_after_write_confirm@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 48(%r15)
	movq	_dst_sel___release_mem__memory_controller@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 44(%r15)
	movq	_QUEUESTATE__ACTIVE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %eax
	movl	%eax, 40(%r15)
	movq	%r12, %rdi
	callq	*8(%r12)
	movl	(%rbx), %esi
	movq	%r14, %rdi
	movl	$1500, %edx                     ## imm = 0x5DC
	callq	_amdkfd_fence_wait_timeout
	movl	%eax, %r14d
	movl	(%r13), %edi
	movq	-64(%rbp), %rsi
	callq	_kfd_gtt_sa_free
LBB0_7:
	movl	%r14d, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_EINVAL,4,2                     ## @EINVAL
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"acquire_packet_buffer failed\n"

	.comm	_IT_INDIRECT_BUFFER_PASID,4,2   ## @IT_INDIRECT_BUFFER_PASID
	.comm	_PM4_TYPE_3,8,3                 ## @PM4_TYPE_3
L_.str.1:                               ## @.str.1
	.asciz	"Failed to allocate GART memory\n"

	.comm	_QUEUESTATE__ACTIVE_COMPLETION_PENDING,4,2 ## @QUEUESTATE__ACTIVE_COMPLETION_PENDING
	.comm	_IT_RELEASE_MEM,4,2             ## @IT_RELEASE_MEM
	.comm	_CACHE_FLUSH_AND_INV_TS_EVENT,4,2 ## @CACHE_FLUSH_AND_INV_TS_EVENT
	.comm	_event_index___release_mem__end_of_pipe,4,2 ## @event_index___release_mem__end_of_pipe
	.comm	_cache_policy___release_mem__lru,4,2 ## @cache_policy___release_mem__lru
	.comm	_data_sel___release_mem__send_64_bit_data,4,2 ## @data_sel___release_mem__send_64_bit_data
	.comm	_int_sel___release_mem__send_data_after_write_confirm,4,2 ## @int_sel___release_mem__send_data_after_write_confirm
	.comm	_dst_sel___release_mem__memory_controller,4,2 ## @dst_sel___release_mem__memory_controller
	.comm	_QUEUESTATE__ACTIVE,4,2         ## @QUEUESTATE__ACTIVE
	.no_dead_strip	_dbgdev_diq_submit_ib
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dbgdev_diq_submit_ib
_dbgdev_diq_submit_ib:                  ; @dbgdev_diq_submit_ib
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x22, x4
	mov	x23, x2
	mov	x21, x1
	mov	x19, x0
	cmp	x4, #0
	cset	w0, eq
	bl	_WARN_ON
	cbz	x0, LBB0_2
; %bb.1:
Lloh0:
	adrp	x8, _EINVAL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	neg	w24, w8
	b	LBB0_7
LBB0_2:
	ldr	x20, [x19, #8]
	ldr	x8, [x20]
	mov	x2, sp
	mov	x0, x20
	mov	w1, #30
	blr	x8
	cbz	w0, LBB0_4
; %bb.3:
	mov	x24, x0
Lloh3:
	adrp	x0, l_.str@PAGE
Lloh4:
	add	x0, x0, l_.str@PAGEOFF
	bl	_pr_err
	b	LBB0_7
LBB0_4:
	ldr	x0, [sp]
	mov	w1, #0
	mov	w2, #120
	bl	_memset
	ldr	x25, [sp]
Lloh5:
	adrp	x8, _IT_INDIRECT_BUFFER_PASID@GOTPAGE
Lloh6:
	ldr	x8, [x8, _IT_INDIRECT_BUFFER_PASID@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
Lloh8:
	adrp	x26, _PM4_TYPE_3@GOTPAGE
Lloh9:
	ldr	x26, [x26, _PM4_TYPE_3@GOTPAGEOFF]
	str	w8, [x25, #32]
	ldr	x8, [x26]
	str	x8, [x25, #24]
	mov	w8, #3
	asr	w9, w23, #2
	stp	w9, w8, [x25, #12]
	mov	w8, #-2139095040
	bfxil	w8, w22, #2, #20
	stp	w8, w21, [x25]
	ldr	w0, [x19]
	add	x2, sp, #8
	mov	w1, #4
	bl	_kfd_gtt_sa_allocate
	cbz	w0, LBB0_6
; %bb.5:
	mov	x24, x0
Lloh10:
	adrp	x0, l_.str.1@PAGE
Lloh11:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_pr_err
	ldr	x8, [x20, #16]
	mov	x0, x20
	blr	x8
	b	LBB0_7
LBB0_6:
	ldr	x8, [sp, #8]
	ldr	x21, [x8, #8]
Lloh12:
	adrp	x9, _QUEUESTATE__ACTIVE_COMPLETION_PENDING@GOTPAGE
Lloh13:
	ldr	x9, [x9, _QUEUESTATE__ACTIVE_COMPLETION_PENDING@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
Lloh15:
	adrp	x10, _IT_RELEASE_MEM@GOTPAGE
Lloh16:
	ldr	x10, [x10, _IT_RELEASE_MEM@GOTPAGEOFF]
	str	w9, [x21]
Lloh17:
	ldr	w9, [x10]
	str	w9, [x25, #112]
	ldr	x9, [x26]
	str	x9, [x25, #104]
	mov	w9, #18
	str	w9, [x25, #96]
Lloh18:
	adrp	x9, _CACHE_FLUSH_AND_INV_TS_EVENT@GOTPAGE
Lloh19:
	ldr	x9, [x9, _CACHE_FLUSH_AND_INV_TS_EVENT@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
Lloh21:
	adrp	x10, _event_index___release_mem__end_of_pipe@GOTPAGE
Lloh22:
	ldr	x10, [x10, _event_index___release_mem__end_of_pipe@GOTPAGEOFF]
	str	w9, [x25, #88]
Lloh23:
	ldr	w9, [x10]
Lloh24:
	adrp	x10, _cache_policy___release_mem__lru@GOTPAGE
Lloh25:
	ldr	x10, [x10, _cache_policy___release_mem__lru@GOTPAGEOFF]
Lloh26:
	ldr	w10, [x10]
	stp	w10, w9, [x25, #80]
	str	xzr, [x25, #72]
	mov	w9, #1
	str	w9, [x25, #64]
	ldr	w8, [x8]
	asr	w8, w8, #2
	str	w8, [x25, #60]
Lloh27:
	adrp	x8, _data_sel___release_mem__send_64_bit_data@GOTPAGE
Lloh28:
	ldr	x8, [x8, _data_sel___release_mem__send_64_bit_data@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
Lloh30:
	adrp	x9, _int_sel___release_mem__send_data_after_write_confirm@GOTPAGE
Lloh31:
	ldr	x9, [x9, _int_sel___release_mem__send_data_after_write_confirm@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	stp	w9, w8, [x25, #48]
Lloh33:
	adrp	x8, _dst_sel___release_mem__memory_controller@GOTPAGE
Lloh34:
	ldr	x8, [x8, _dst_sel___release_mem__memory_controller@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
Lloh36:
	adrp	x22, _QUEUESTATE__ACTIVE@GOTPAGE
Lloh37:
	ldr	x22, [x22, _QUEUESTATE__ACTIVE@GOTPAGEOFF]
	ldr	w9, [x22]
	stp	w9, w8, [x25, #40]
	ldr	x8, [x20, #8]
	mov	x0, x20
	blr	x8
	ldr	w1, [x22]
	mov	x0, x21
	mov	w2, #1500
	bl	_amdkfd_fence_wait_timeout
	mov	x24, x0
	ldr	w0, [x19]
	ldr	x1, [sp, #8]
	bl	_kfd_gtt_sa_free
LBB0_7:
	mov	x0, x24
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.cfi_endproc
                                        ; -- End function
	.comm	_EINVAL,4,2                     ; @EINVAL
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"acquire_packet_buffer failed\n"

	.comm	_IT_INDIRECT_BUFFER_PASID,4,2   ; @IT_INDIRECT_BUFFER_PASID
	.comm	_PM4_TYPE_3,8,3                 ; @PM4_TYPE_3
l_.str.1:                               ; @.str.1
	.asciz	"Failed to allocate GART memory\n"

	.comm	_QUEUESTATE__ACTIVE_COMPLETION_PENDING,4,2 ; @QUEUESTATE__ACTIVE_COMPLETION_PENDING
	.comm	_IT_RELEASE_MEM,4,2             ; @IT_RELEASE_MEM
	.comm	_CACHE_FLUSH_AND_INV_TS_EVENT,4,2 ; @CACHE_FLUSH_AND_INV_TS_EVENT
	.comm	_event_index___release_mem__end_of_pipe,4,2 ; @event_index___release_mem__end_of_pipe
	.comm	_cache_policy___release_mem__lru,4,2 ; @cache_policy___release_mem__lru
	.comm	_data_sel___release_mem__send_64_bit_data,4,2 ; @data_sel___release_mem__send_64_bit_data
	.comm	_int_sel___release_mem__send_data_after_write_confirm,4,2 ; @int_sel___release_mem__send_data_after_write_confirm
	.comm	_dst_sel___release_mem__memory_controller,4,2 ; @dst_sel___release_mem__memory_controller
	.comm	_QUEUESTATE__ACTIVE,4,2         ; @QUEUESTATE__ACTIVE
	.no_dead_strip	_dbgdev_diq_submit_ib
.subsections_via_symbols
