	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function intel_ddi_pre_enable_dp
_intel_ddi_pre_enable_dp:               ## @intel_ddi_pre_enable_dp
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r12
	movq	%rdi, %r14
	leaq	8(%rdi), %rbx
	movq	%rbx, %rdi
	callq	_enc_to_intel_dp
	movq	%rax, %r15
	movl	8(%r14), %edi
	callq	_to_i915
	movl	(%r14), %r13d
	movq	%rax, -80(%rbp)                 ## 8-byte Spill
	movq	%rax, %rdi
	movl	%r13d, %esi
	callq	_intel_port_to_phy
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	%rbx, %rdi
	callq	_enc_to_dig_port
	movq	%rax, -64(%rbp)                 ## 8-byte Spill
	movq	_INTEL_OUTPUT_DP_MST@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_intel_crtc_has_type
	movl	%eax, %ebx
	movq	%r15, %rdi
	callq	_intel_ddi_dp_level
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movl	%ebx, -52(%rbp)                 ## 4-byte Spill
	testl	%ebx, %ebx
	movl	%r13d, -68(%rbp)                ## 4-byte Spill
	je	LBB0_1
## %bb.2:
	movq	_PORT_A@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r13d
	sete	%al
	movq	_PORT_E@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %r13d
	sete	%cl
	orb	%al, %cl
	movzbl	%cl, %edi
	jmp	LBB0_3
LBB0_1:
	xorl	%edi, %edi
LBB0_3:
	callq	_WARN_ON
	movl	(%r12), %edx
	movl	4(%r12), %esi
	movq	%r15, %rdi
	movl	-52(%rbp), %ecx                 ## 4-byte Reload
	callq	_intel_dp_set_link_params
	movq	%r15, %rdi
	callq	_intel_edp_panel_on
	movq	%r14, %rdi
	movq	%r12, %rsi
	callq	_intel_ddi_clk_select
	movq	-80(%rbp), %r13                 ## 8-byte Reload
	movq	%r13, %rdi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_intel_phy_is_tc
	testl	%eax, %eax
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	je	LBB0_5
## %bb.4:
	movq	(%rbx), %rax
	movq	_TC_PORT_TBT_ALT@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_6
LBB0_5:
	movl	12(%rbx), %esi
	movq	%r13, %rdi
	callq	_intel_display_power_get
LBB0_6:
	movq	%rbx, %rdi
	callq	_icl_program_mg_dp_mode
	movq	%rbx, %rdi
	callq	_icl_disable_phy_clock_gating
	movq	%r13, %rdi
	callq	_INTEL_GEN
	cmpl	$11, %eax
	jl	LBB0_8
## %bb.7:
	movq	%r15, %rbx
	movl	4(%r12), %esi
	movl	4(%r14), %ecx
	movq	%r14, %rdi
	movl	-48(%rbp), %edx                 ## 4-byte Reload
	callq	_icl_ddi_vswing_sequence
	jmp	LBB0_13
LBB0_8:
	movq	%r13, %rdi
	callq	_IS_CANNONLAKE
	movq	%r15, %rbx
	testq	%rax, %rax
	je	LBB0_10
## %bb.9:
	movl	4(%r14), %edx
	movq	%r14, %rdi
	movl	-48(%rbp), %esi                 ## 4-byte Reload
	callq	_cnl_ddi_vswing_sequence
	jmp	LBB0_13
LBB0_10:
	movq	%r13, %rdi
	callq	_IS_GEN9_LP
	testq	%rax, %rax
	je	LBB0_12
## %bb.11:
	movl	4(%r14), %edx
	movq	%r14, %rdi
	movl	-48(%rbp), %esi                 ## 4-byte Reload
	callq	_bxt_ddi_vswing_sequence
	jmp	LBB0_13
LBB0_12:
	movq	%r14, %rdi
	movq	%r12, %rsi
	callq	_intel_prepare_dp_ddi_buffers
LBB0_13:
	movl	-44(%rbp), %r15d                ## 4-byte Reload
	movq	%r13, %rdi
	movl	%r15d, %esi
	callq	_intel_phy_is_combo
	testq	%rax, %rax
	je	LBB0_15
## %bb.14:
	movq	_DDI_BUF_PORT_REVERSAL@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	movq	-64(%rbp), %rax                 ## 8-byte Reload
	andl	8(%rax), %r8d
	movl	(%r12), %ecx
	movq	%r13, %rdi
	movl	%r15d, %esi
	xorl	%edx, %edx
	callq	_intel_combo_phy_power_up_lanes
LBB0_15:
	movq	%r14, %rdi
	callq	_intel_ddi_init_dp_buf_reg
	cmpl	$0, -52(%rbp)                   ## 4-byte Folded Reload
	jne	LBB0_17
## %bb.16:
	movq	_DRM_MODE_DPMS_ON@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_intel_dp_sink_dpms
LBB0_17:
	movq	%rbx, %rdi
	movq	%r12, %rsi
	movl	$1, %edx
	callq	_intel_dp_sink_set_decompression_state
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	_intel_dp_sink_set_fec_ready
	movq	%rbx, %rdi
	callq	_intel_dp_start_link_train
	movq	_PORT_A@GOTPCREL(%rip), %rax
	movl	-68(%rbp), %ecx                 ## 4-byte Reload
	cmpl	(%rax), %ecx
	jne	LBB0_19
## %bb.18:
	movq	%r13, %rdi
	callq	_INTEL_GEN
	cmpl	$9, %eax
	jl	LBB0_20
LBB0_19:
	movq	%rbx, %rdi
	callq	_intel_dp_stop_link_train
LBB0_20:
	movq	%r14, %rdi
	movq	%r12, %rsi
	callq	_intel_ddi_enable_fec
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	callq	_icl_enable_phy_clock_gating
	cmpl	$0, -52(%rbp)                   ## 4-byte Folded Reload
	jne	LBB0_22
## %bb.21:
	movq	%r12, %rdi
	callq	_intel_ddi_enable_pipe_clock
LBB0_22:
	movq	%r14, %rdi
	movq	%r12, %rsi
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_intel_dsc_enable               ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_INTEL_OUTPUT_DP_MST,4,2        ## @INTEL_OUTPUT_DP_MST
	.comm	_PORT_A,4,2                     ## @PORT_A
	.comm	_PORT_E,4,2                     ## @PORT_E
	.comm	_TC_PORT_TBT_ALT,8,3            ## @TC_PORT_TBT_ALT
	.comm	_DDI_BUF_PORT_REVERSAL,4,2      ## @DDI_BUF_PORT_REVERSAL
	.comm	_DRM_MODE_DPMS_ON,4,2           ## @DRM_MODE_DPMS_ON
	.no_dead_strip	_intel_ddi_pre_enable_dp
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function intel_ddi_pre_enable_dp
_intel_ddi_pre_enable_dp:               ; @intel_ddi_pre_enable_dp
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x1
	mov	x20, x0
	add	x22, x0, #8
	mov	x0, x22
	bl	_enc_to_intel_dp
	mov	x21, x0
	ldr	w0, [x20, #8]
	bl	_to_i915
	mov	x23, x0
	ldr	w25, [x20]
	mov	x1, x25
	bl	_intel_port_to_phy
	mov	x26, x0
	mov	x0, x22
	bl	_enc_to_dig_port
	mov	x22, x0
Lloh0:
	adrp	x8, _INTEL_OUTPUT_DP_MST@GOTPAGE
Lloh1:
	ldr	x8, [x8, _INTEL_OUTPUT_DP_MST@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_intel_crtc_has_type
	mov	x24, x0
	mov	x0, x21
	bl	_intel_ddi_dp_level
	mov	x27, x0
Lloh3:
	adrp	x28, _PORT_A@GOTPAGE
Lloh4:
	ldr	x28, [x28, _PORT_A@GOTPAGEOFF]
	cbz	w24, LBB0_2
; %bb.1:
	ldr	w8, [x28]
	cmp	w25, w8
Lloh5:
	adrp	x8, _PORT_E@GOTPAGE
Lloh6:
	ldr	x8, [x8, _PORT_E@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	ccmp	w25, w8, #4, ne
	cset	w0, eq
	b	LBB0_3
LBB0_2:
	mov	w0, #0
LBB0_3:
	bl	_WARN_ON
	ldp	w2, w1, [x19]
	mov	x0, x21
	mov	x3, x24
	bl	_intel_dp_set_link_params
	mov	x0, x21
	bl	_intel_edp_panel_on
	mov	x0, x20
	mov	x1, x19
	bl	_intel_ddi_clk_select
	mov	x0, x23
	mov	x1, x26
	bl	_intel_phy_is_tc
	cbz	w0, LBB0_5
; %bb.4:
	ldr	x8, [x22]
Lloh8:
	adrp	x9, _TC_PORT_TBT_ALT@GOTPAGE
Lloh9:
	ldr	x9, [x9, _TC_PORT_TBT_ALT@GOTPAGEOFF]
Lloh10:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_6
LBB0_5:
	ldr	w1, [x22, #12]
	mov	x0, x23
	bl	_intel_display_power_get
LBB0_6:
	mov	x0, x22
	bl	_icl_program_mg_dp_mode
	mov	x0, x22
	bl	_icl_disable_phy_clock_gating
	mov	x0, x23
	bl	_INTEL_GEN
	cmp	w0, #11
	b.lt	LBB0_8
; %bb.7:
	ldr	w1, [x19, #4]
	ldr	w3, [x20, #4]
	mov	x0, x20
	mov	x2, x27
	bl	_icl_ddi_vswing_sequence
	b	LBB0_13
LBB0_8:
	mov	x0, x23
	bl	_IS_CANNONLAKE
	cbz	x0, LBB0_10
; %bb.9:
	ldr	w2, [x20, #4]
	mov	x0, x20
	mov	x1, x27
	bl	_cnl_ddi_vswing_sequence
	b	LBB0_13
LBB0_10:
	mov	x0, x23
	bl	_IS_GEN9_LP
	cbz	x0, LBB0_12
; %bb.11:
	ldr	w2, [x20, #4]
	mov	x0, x20
	mov	x1, x27
	bl	_bxt_ddi_vswing_sequence
	b	LBB0_13
LBB0_12:
	mov	x0, x20
	mov	x1, x19
	bl	_intel_prepare_dp_ddi_buffers
LBB0_13:
	mov	x0, x23
	mov	x1, x26
	bl	_intel_phy_is_combo
	cbz	x0, LBB0_15
; %bb.14:
	ldr	w8, [x22, #8]
Lloh11:
	adrp	x9, _DDI_BUF_PORT_REVERSAL@GOTPAGE
Lloh12:
	ldr	x9, [x9, _DDI_BUF_PORT_REVERSAL@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	and	w4, w9, w8
	ldr	w3, [x19]
	mov	x0, x23
	mov	x1, x26
	mov	w2, #0
	bl	_intel_combo_phy_power_up_lanes
LBB0_15:
	mov	x0, x20
	bl	_intel_ddi_init_dp_buf_reg
	cbnz	w24, LBB0_17
; %bb.16:
Lloh14:
	adrp	x8, _DRM_MODE_DPMS_ON@GOTPAGE
Lloh15:
	ldr	x8, [x8, _DRM_MODE_DPMS_ON@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
	mov	x0, x21
	bl	_intel_dp_sink_dpms
LBB0_17:
	mov	x0, x21
	mov	x1, x19
	mov	w2, #1
	bl	_intel_dp_sink_set_decompression_state
	mov	x0, x21
	mov	x1, x19
	bl	_intel_dp_sink_set_fec_ready
	mov	x0, x21
	bl	_intel_dp_start_link_train
	ldr	w8, [x28]
	cmp	w25, w8
	b.ne	LBB0_19
; %bb.18:
	mov	x0, x23
	bl	_INTEL_GEN
	cmp	w0, #9
	b.lt	LBB0_20
LBB0_19:
	mov	x0, x21
	bl	_intel_dp_stop_link_train
LBB0_20:
	mov	x0, x20
	mov	x1, x19
	bl	_intel_ddi_enable_fec
	mov	x0, x22
	bl	_icl_enable_phy_clock_gating
	cbnz	w24, LBB0_22
; %bb.21:
	mov	x0, x19
	bl	_intel_ddi_enable_pipe_clock
LBB0_22:
	mov	x0, x20
	mov	x1, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_intel_dsc_enable
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.cfi_endproc
                                        ; -- End function
	.comm	_INTEL_OUTPUT_DP_MST,4,2        ; @INTEL_OUTPUT_DP_MST
	.comm	_PORT_A,4,2                     ; @PORT_A
	.comm	_PORT_E,4,2                     ; @PORT_E
	.comm	_TC_PORT_TBT_ALT,8,3            ; @TC_PORT_TBT_ALT
	.comm	_DDI_BUF_PORT_REVERSAL,4,2      ; @DDI_BUF_PORT_REVERSAL
	.comm	_DRM_MODE_DPMS_ON,4,2           ; @DRM_MODE_DPMS_ON
	.no_dead_strip	_intel_ddi_pre_enable_dp
.subsections_via_symbols
