	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v8_0_cp_gfx_resume
_gfx_v8_0_cp_gfx_resume:                ## @gfx_v8_0_cp_gfx_resume
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_mmCP_RB_WPTR_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmCP_RB_VMID@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	8(%r14), %r12
	movl	(%r12), %eax
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	callq	_order_base_2
	movl	%eax, %ebx
	movq	_CP_RB0_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_RB_BUFSZ@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%edi, %edi
	movl	%ebx, %ecx
	callq	_REG_SET_FIELD
	movl	(%r15), %esi
	movq	_RB_BLKSZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	addl	$-2, %ebx
	movl	%eax, %edi
	movl	%ebx, %ecx
	callq	_REG_SET_FIELD
	movl	(%r15), %esi
	movq	_MTYPE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$3, %ecx
	callq	_REG_SET_FIELD
	movl	(%r15), %esi
	movq	_MIN_IB_AVAILSZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	%eax, %r15d
	movq	_mmCP_RB0_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movl	%eax, %esi
	callq	_WREG32
	movl	(%rbx), %edi
	movq	_CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	%r15d, %esi
	callq	_WREG32
	movl	$0, 4(%r12)
	movq	_mmCP_RB0_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	xorl	%edi, %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movl	8(%r12), %ebx
	shll	$2, %ebx
	addl	(%r14), %ebx
	movq	_mmCP_RB0_RPTR_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	%ebx, %edi
	callq	_lower_32_bits
	movl	%r13d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmCP_RB0_RPTR_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	%ebx, %edi
	callq	_upper_32_bits
	movzbl	%al, %esi
	movl	%r13d, %edi
	callq	_WREG32
	movl	12(%r12), %ebx
	shll	$2, %ebx
	addl	(%r14), %ebx
	movq	_mmCP_RB_WPTR_POLL_ADDR_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	%ebx, %edi
	callq	_lower_32_bits
	movl	%r13d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmCP_RB_WPTR_POLL_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	%ebx, %edi
	callq	_upper_32_bits
	movl	%r13d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movl	$1, %edi
	callq	_mdelay
	movq	_mmCP_RB0_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movl	16(%r12), %ebx
	sarl	$8, %ebx
	movq	_mmCP_RB0_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_mmCP_RB0_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	%ebx, %edi
	callq	_upper_32_bits
	movl	%r15d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	%r14, %rdi
	movq	%r12, %rsi
	callq	_gfx_v8_0_set_cpg_door_bell
	movq	%r12, %rdi
	callq	_amdgpu_ring_clear_ring
	movq	%r14, %rdi
	callq	_gfx_v8_0_cp_gfx_start
	movl	$1, 20(%r12)
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_mmCP_RB_WPTR_DELAY,4,2         ## @mmCP_RB_WPTR_DELAY
	.comm	_mmCP_RB_VMID,4,2               ## @mmCP_RB_VMID
	.comm	_CP_RB0_CNTL,4,2                ## @CP_RB0_CNTL
	.comm	_RB_BUFSZ,4,2                   ## @RB_BUFSZ
	.comm	_RB_BLKSZ,4,2                   ## @RB_BLKSZ
	.comm	_MTYPE,4,2                      ## @MTYPE
	.comm	_MIN_IB_AVAILSZ,4,2             ## @MIN_IB_AVAILSZ
	.comm	_mmCP_RB0_CNTL,4,2              ## @mmCP_RB0_CNTL
	.comm	_CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK,4,2 ## @CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK
	.comm	_mmCP_RB0_WPTR,4,2              ## @mmCP_RB0_WPTR
	.comm	_mmCP_RB0_RPTR_ADDR,4,2         ## @mmCP_RB0_RPTR_ADDR
	.comm	_mmCP_RB0_RPTR_ADDR_HI,4,2      ## @mmCP_RB0_RPTR_ADDR_HI
	.comm	_mmCP_RB_WPTR_POLL_ADDR_LO,4,2  ## @mmCP_RB_WPTR_POLL_ADDR_LO
	.comm	_mmCP_RB_WPTR_POLL_ADDR_HI,4,2  ## @mmCP_RB_WPTR_POLL_ADDR_HI
	.comm	_mmCP_RB0_BASE,4,2              ## @mmCP_RB0_BASE
	.comm	_mmCP_RB0_BASE_HI,4,2           ## @mmCP_RB0_BASE_HI
	.comm	_BUF_SWAP,4,2                   ## @BUF_SWAP
	.no_dead_strip	_gfx_v8_0_cp_gfx_resume
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v8_0_cp_gfx_resume
_gfx_v8_0_cp_gfx_resume:                ; @gfx_v8_0_cp_gfx_resume
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
Lloh0:
	adrp	x8, _mmCP_RB_WPTR_DELAY@GOTPAGE
Lloh1:
	ldr	x8, [x8, _mmCP_RB_WPTR_DELAY@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh3:
	adrp	x8, _mmCP_RB_VMID@GOTPAGE
Lloh4:
	ldr	x8, [x8, _mmCP_RB_VMID@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	ldr	x20, [x19, #8]
	ldr	w8, [x20]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #3
	bl	_order_base_2
	mov	x21, x0
Lloh6:
	adrp	x22, _CP_RB0_CNTL@GOTPAGE
Lloh7:
	ldr	x22, [x22, _CP_RB0_CNTL@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh8:
	adrp	x8, _RB_BUFSZ@GOTPAGE
Lloh9:
	ldr	x8, [x8, _RB_BUFSZ@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	w0, #0
	mov	x3, x21
	bl	_REG_SET_FIELD
	ldr	w1, [x22]
Lloh11:
	adrp	x8, _RB_BLKSZ@GOTPAGE
Lloh12:
	ldr	x8, [x8, _RB_BLKSZ@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	sub	w3, w21, #2
	bl	_REG_SET_FIELD
	ldr	w1, [x22]
Lloh14:
	adrp	x8, _MTYPE@GOTPAGE
Lloh15:
	ldr	x8, [x8, _MTYPE@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	mov	w3, #3
	bl	_REG_SET_FIELD
	ldr	w1, [x22]
Lloh17:
	adrp	x8, _MIN_IB_AVAILSZ@GOTPAGE
Lloh18:
	ldr	x8, [x8, _MIN_IB_AVAILSZ@GOTPAGEOFF]
Lloh19:
	ldr	w2, [x8]
	mov	w24, #1
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x21, x0
Lloh20:
	adrp	x25, _mmCP_RB0_CNTL@GOTPAGE
Lloh21:
	ldr	x25, [x25, _mmCP_RB0_CNTL@GOTPAGEOFF]
	ldr	w0, [x25]
	mov	x1, x21
	bl	_WREG32
	ldr	w0, [x25]
Lloh22:
	adrp	x8, _CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK@GOTPAGE
Lloh23:
	ldr	x8, [x8, _CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	orr	w1, w8, w21
	bl	_WREG32
	str	wzr, [x20, #4]
Lloh25:
	adrp	x8, _mmCP_RB0_WPTR@GOTPAGE
Lloh26:
	ldr	x8, [x8, _mmCP_RB0_WPTR@GOTPAGEOFF]
Lloh27:
	ldr	w22, [x8]
	mov	w0, #0
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x22
	bl	_WREG32
	ldr	w8, [x19]
	ldr	w9, [x20, #8]
	add	w22, w8, w9, lsl #2
Lloh28:
	adrp	x8, _mmCP_RB0_RPTR_ADDR@GOTPAGE
Lloh29:
	ldr	x8, [x8, _mmCP_RB0_RPTR_ADDR@GOTPAGEOFF]
Lloh30:
	ldr	w23, [x8]
	mov	x0, x22
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x23
	bl	_WREG32
Lloh31:
	adrp	x8, _mmCP_RB0_RPTR_ADDR_HI@GOTPAGE
Lloh32:
	ldr	x8, [x8, _mmCP_RB0_RPTR_ADDR_HI@GOTPAGEOFF]
Lloh33:
	ldr	w23, [x8]
	mov	x0, x22
	bl	_upper_32_bits
	and	w1, w0, #0xff
	mov	x0, x23
	bl	_WREG32
	ldr	w8, [x19]
	ldr	w9, [x20, #12]
	add	w22, w8, w9, lsl #2
Lloh34:
	adrp	x8, _mmCP_RB_WPTR_POLL_ADDR_LO@GOTPAGE
Lloh35:
	ldr	x8, [x8, _mmCP_RB_WPTR_POLL_ADDR_LO@GOTPAGEOFF]
Lloh36:
	ldr	w23, [x8]
	mov	x0, x22
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x23
	bl	_WREG32
Lloh37:
	adrp	x8, _mmCP_RB_WPTR_POLL_ADDR_HI@GOTPAGE
Lloh38:
	ldr	x8, [x8, _mmCP_RB_WPTR_POLL_ADDR_HI@GOTPAGEOFF]
Lloh39:
	ldr	w23, [x8]
	mov	x0, x22
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x23
	bl	_WREG32
	mov	w0, #1
	bl	_mdelay
	ldr	w0, [x25]
	mov	x1, x21
	bl	_WREG32
	ldr	w8, [x20, #16]
	asr	w21, w8, #8
Lloh40:
	adrp	x8, _mmCP_RB0_BASE@GOTPAGE
Lloh41:
	ldr	x8, [x8, _mmCP_RB0_BASE@GOTPAGEOFF]
Lloh42:
	ldr	w0, [x8]
	mov	x1, x21
	bl	_WREG32
Lloh43:
	adrp	x8, _mmCP_RB0_BASE_HI@GOTPAGE
Lloh44:
	ldr	x8, [x8, _mmCP_RB0_BASE_HI@GOTPAGEOFF]
Lloh45:
	ldr	w22, [x8]
	mov	x0, x21
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x22
	bl	_WREG32
	mov	x0, x19
	mov	x1, x20
	bl	_gfx_v8_0_set_cpg_door_bell
	mov	x0, x20
	bl	_amdgpu_ring_clear_ring
	mov	x0, x19
	bl	_gfx_v8_0_cp_gfx_start
	str	w24, [x20, #20]
	mov	w0, #0
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_mmCP_RB_WPTR_DELAY,4,2         ; @mmCP_RB_WPTR_DELAY
	.comm	_mmCP_RB_VMID,4,2               ; @mmCP_RB_VMID
	.comm	_CP_RB0_CNTL,4,2                ; @CP_RB0_CNTL
	.comm	_RB_BUFSZ,4,2                   ; @RB_BUFSZ
	.comm	_RB_BLKSZ,4,2                   ; @RB_BLKSZ
	.comm	_MTYPE,4,2                      ; @MTYPE
	.comm	_MIN_IB_AVAILSZ,4,2             ; @MIN_IB_AVAILSZ
	.comm	_mmCP_RB0_CNTL,4,2              ; @mmCP_RB0_CNTL
	.comm	_CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK,4,2 ; @CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK
	.comm	_mmCP_RB0_WPTR,4,2              ; @mmCP_RB0_WPTR
	.comm	_mmCP_RB0_RPTR_ADDR,4,2         ; @mmCP_RB0_RPTR_ADDR
	.comm	_mmCP_RB0_RPTR_ADDR_HI,4,2      ; @mmCP_RB0_RPTR_ADDR_HI
	.comm	_mmCP_RB_WPTR_POLL_ADDR_LO,4,2  ; @mmCP_RB_WPTR_POLL_ADDR_LO
	.comm	_mmCP_RB_WPTR_POLL_ADDR_HI,4,2  ; @mmCP_RB_WPTR_POLL_ADDR_HI
	.comm	_mmCP_RB0_BASE,4,2              ; @mmCP_RB0_BASE
	.comm	_mmCP_RB0_BASE_HI,4,2           ; @mmCP_RB0_BASE_HI
	.comm	_BUF_SWAP,4,2                   ; @BUF_SWAP
	.no_dead_strip	_gfx_v8_0_cp_gfx_resume
.subsections_via_symbols
