	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_ctx_get_fence           ## -- Begin function amdgpu_ctx_get_fence
	.p2align	4, 0x90
_amdgpu_ctx_get_fence:                  ## @amdgpu_ctx_get_fence
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %rbx
	movq	%rdi, %r14
	movq	%rsi, %rdi
	callq	_to_amdgpu_ctx_entity
	movq	%rax, %r15
	movq	%r14, %rdi
	callq	_spin_lock
	movq	(%r15), %rcx
	leaq	-1(%rcx), %rax
	cmpq	$-1, %rbx
	cmovneq	%rbx, %rax
	cmpq	%rcx, %rax
	jae	LBB0_5
## %bb.1:
	movq	_amdgpu_sched_jobs@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdx
	leaq	(%rdx,%rax), %rsi
	cmpq	%rcx, %rsi
	jae	LBB0_4
## %bb.2:
	movq	%r14, %rdi
	callq	_spin_unlock
	xorl	%eax, %eax
	jmp	LBB0_3
LBB0_5:
	movq	%r14, %rdi
	callq	_spin_unlock
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%edi, %edi
	subl	(%rax), %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_ERR_PTR                        ## TAILCALL
LBB0_4:
	movq	8(%r15), %rcx
	decq	%rdx
	andq	%rax, %rdx
	movl	(%rcx,%rdx,4), %edi
	callq	_dma_fence_get
	movq	%rax, %rbx
	movq	%r14, %rdi
	callq	_spin_unlock
	movq	%rbx, %rax
LBB0_3:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_amdgpu_sched_jobs,8,3          ## @amdgpu_sched_jobs
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_ctx_get_fence           ; -- Begin function amdgpu_ctx_get_fence
	.p2align	2
_amdgpu_ctx_get_fence:                  ; @amdgpu_ctx_get_fence
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x21, x2
	mov	x19, x0
	mov	x0, x1
	bl	_to_amdgpu_ctx_entity
	mov	x20, x0
	mov	x0, x19
	bl	_spin_lock
	ldr	x9, [x20]
	sub	x8, x9, #1
	cmn	x21, #1
	csel	x8, x8, x21, eq
	cmp	x8, x9
	b.hs	LBB0_3
; %bb.1:
Lloh0:
	adrp	x10, _amdgpu_sched_jobs@GOTPAGE
Lloh1:
	ldr	x10, [x10, _amdgpu_sched_jobs@GOTPAGEOFF]
Lloh2:
	ldr	x10, [x10]
	add	x11, x10, x8
	cmp	x11, x9
	b.hs	LBB0_4
; %bb.2:
	mov	x0, x19
	bl	_spin_unlock
	mov	x0, #0
	b	LBB0_5
LBB0_3:
	mov	x0, x19
	bl	_spin_unlock
Lloh3:
	adrp	x8, _EINVAL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	neg	w0, w8
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_ERR_PTR
LBB0_4:
	ldr	x9, [x20, #8]
	sub	x10, x10, #1
	and	x8, x10, x8
	ldr	w0, [x9, x8, lsl #2]
	bl	_dma_fence_get
	mov	x20, x0
	mov	x0, x19
	bl	_spin_unlock
	mov	x0, x20
LBB0_5:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_amdgpu_sched_jobs,8,3          ; @amdgpu_sched_jobs
.subsections_via_symbols
