	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_ttm_tt_pte_flags        ## -- Begin function amdgpu_ttm_tt_pte_flags
	.p2align	4, 0x90
_amdgpu_ttm_tt_pte_flags:               ## @amdgpu_ttm_tt_pte_flags
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %r15
	movq	%rsi, %rdi
	movq	%rdx, %rsi
	callq	_amdgpu_ttm_tt_pde_flags
	movl	%eax, %ebx
	orl	(%r15), %ebx
	movq	_AMDGPU_PTE_READABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	%r14, %rdi
	callq	_amdgpu_ttm_tt_is_readonly
	xorl	%ecx, %ecx
	testl	%eax, %eax
	jne	LBB0_2
## %bb.1:
	movq	_AMDGPU_PTE_WRITEABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
LBB0_2:
	orl	%ecx, %ebx
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_PTE_READABLE,4,2        ## @AMDGPU_PTE_READABLE
	.comm	_AMDGPU_PTE_WRITEABLE,4,2       ## @AMDGPU_PTE_WRITEABLE
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_ttm_tt_pte_flags        ; -- Begin function amdgpu_ttm_tt_pte_flags
	.p2align	2
_amdgpu_ttm_tt_pte_flags:               ; @amdgpu_ttm_tt_pte_flags
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x1
	mov	x20, x0
	mov	x0, x1
	mov	x1, x2
	bl	_amdgpu_ttm_tt_pde_flags
	ldr	w8, [x20]
	orr	w8, w8, w0
Lloh0:
	adrp	x9, _AMDGPU_PTE_READABLE@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMDGPU_PTE_READABLE@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	orr	w20, w8, w9
	mov	x0, x19
	bl	_amdgpu_ttm_tt_is_readonly
Lloh3:
	adrp	x8, _AMDGPU_PTE_WRITEABLE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _AMDGPU_PTE_WRITEABLE@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	cmp	w0, #0
	csel	w8, w8, wzr, eq
	orr	w0, w20, w8
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_PTE_READABLE,4,2        ; @AMDGPU_PTE_READABLE
	.comm	_AMDGPU_PTE_WRITEABLE,4,2       ; @AMDGPU_PTE_WRITEABLE
.subsections_via_symbols
