	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function meson_venci_cvbs_clock_config
_meson_venci_cvbs_clock_config:         ## @meson_venci_cvbs_clock_config
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_VPU_COMPATIBLE_GXBB@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movl	$1476395581, %edx               ## imm = 0x5800023D
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$4214272, %edx                  ## imm = 0x404E00
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$224153745, %edx                ## imm = 0xD5C5091
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL4@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$-2145540308, %edx              ## imm = 0x801DA72C
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL5@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1900571008, %edx               ## imm = 0x71486980
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL6@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$3669, %edx                     ## imm = 0xE55
	callq	_regmap_write
	movl	(%r14), %edi
	movl	(%rbx), %esi
	movl	$1207960125, %edx               ## imm = 0x4800023D
	callq	_regmap_write
	movl	(%r14), %edi
	movl	(%rbx), %esi
	jmp	LBB0_5
LBB0_2:
	movq	_VPU_COMPATIBLE_GXM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	jne	LBB0_4
## %bb.3:
	movq	_VPU_COMPATIBLE_GXL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_8
LBB0_4:
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movl	$1073742459, %edx               ## imm = 0x4000027B
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$-2146651392, %edx              ## imm = 0x800CB300
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$-1507776444, %edx              ## imm = 0xA6212844
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL4@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$206372876, %edx                ## imm = 0xC4D000C
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL5@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$2074409, %edx                  ## imm = 0x1FA729
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL6@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$27464960, %edx                 ## imm = 0x1A31500
	callq	_regmap_write
	movl	(%r14), %edi
	movl	(%r15), %esi
	movq	_HDMI_PLL_RESET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r14), %edi
	movl	(%r15), %esi
	movl	(%rbx), %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	(%r14), %edi
	movl	(%r15), %esi
LBB0_5:
	xorl	%ecx, %ecx
LBB0_6:
	movl	$10, %r8d
	xorl	%r9d, %r9d
	callq	_regmap_read_poll_timeout
LBB0_7:
	movl	(%r14), %edi
	movq	_HHI_VIID_CLK_CNTL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_VCLK2_EN@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movq	_VID_PLL_DIV_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vid_pll_set
	movl	(%r14), %edi
	movq	_HHI_VIID_CLK_DIV@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	_VCLK2_DIV_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	$54, %ecx
	callq	_regmap_update_bits
	movq	_VPU_COMPATIBLE_G12A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	movq	_VCLK2_SEL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$4, %ebx
	shll	%cl, %ebx
	testq	%rax, %rax
	movl	(%r14), %edi
	movl	(%r15), %esi
	movq	_VCLK2_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	$0, %eax
	cmovnel	%eax, %ebx
	movl	%ebx, %ecx
	callq	_regmap_update_bits
	movl	(%r14), %edi
	movl	(%r15), %esi
	movl	(%r13), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r14), %edi
	movq	_HHI_VID_CLK_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_CTS_ENCI_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_CTS_ENCI_SEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$8, %ebx
	movl	$8, %eax
	shll	%cl, %eax
	movl	%eax, %ecx
	callq	_regmap_update_bits
	movl	(%r14), %edi
	movl	(%r12), %esi
	movq	_CTS_VDAC_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_CTS_VDAC_SEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %ebx
	movl	%ebx, %ecx
	callq	_regmap_update_bits
	movl	(%r14), %edi
	movl	(%r12), %esi
	movq	_VCLK2_DIV_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	_VCLK2_DIV_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	orl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r14), %edi
	movl	(%r15), %esi
	movq	_VCLK2_DIV1_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r14), %edi
	movl	(%r15), %esi
	movq	_VCLK2_SOFT_RESET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r14), %edi
	movl	(%r15), %esi
	movl	(%rbx), %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	(%r14), %edi
	movq	_HHI_VID_CLK_CNTL2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_CTS_ENCI_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r14), %edi
	movl	(%rbx), %esi
	movq	_CTS_VDAC_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_regmap_update_bits             ## TAILCALL
LBB0_8:
	movq	_VPU_COMPATIBLE_G12A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_7
## %bb.9:
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movl	$436536567, %edx                ## imm = 0x1A0504F7
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$65536, %edx                    ## imm = 0x10000
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL4@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1781062656, %edx               ## imm = 0x6A28DC00
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL5@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1702302352, %edx               ## imm = 0x65771290
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL6@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$958865408, %edx                ## imm = 0x39272000
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_HHI_HDMI_PLL_CNTL7@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1448345600, %edx               ## imm = 0x56540000
	callq	_regmap_write
	movl	(%r14), %edi
	movl	(%rbx), %esi
	movl	$973407479, %edx                ## imm = 0x3A0504F7
	callq	_regmap_write
	movl	(%r14), %edi
	movl	(%rbx), %esi
	movl	$436536567, %edx                ## imm = 0x1A0504F7
	callq	_regmap_write
	movl	(%r14), %edi
	movl	(%rbx), %esi
	movq	_HDMI_PLL_LOCK_G12A@GOTPCREL(%rip), %rax
	xorl	%ecx, %ecx
	cmpl	$0, (%rax)
	sete	%cl
	jmp	LBB0_6
	.cfi_endproc
                                        ## -- End function
	.comm	_VPU_COMPATIBLE_GXBB,4,2        ## @VPU_COMPATIBLE_GXBB
	.comm	_HHI_HDMI_PLL_CNTL,4,2          ## @HHI_HDMI_PLL_CNTL
	.comm	_HHI_HDMI_PLL_CNTL2,4,2         ## @HHI_HDMI_PLL_CNTL2
	.comm	_HHI_HDMI_PLL_CNTL3,4,2         ## @HHI_HDMI_PLL_CNTL3
	.comm	_HHI_HDMI_PLL_CNTL4,4,2         ## @HHI_HDMI_PLL_CNTL4
	.comm	_HHI_HDMI_PLL_CNTL5,4,2         ## @HHI_HDMI_PLL_CNTL5
	.comm	_HHI_HDMI_PLL_CNTL6,4,2         ## @HHI_HDMI_PLL_CNTL6
	.comm	_HDMI_PLL_LOCK,4,2              ## @HDMI_PLL_LOCK
	.comm	_VPU_COMPATIBLE_GXM,4,2         ## @VPU_COMPATIBLE_GXM
	.comm	_VPU_COMPATIBLE_GXL,4,2         ## @VPU_COMPATIBLE_GXL
	.comm	_HDMI_PLL_RESET,4,2             ## @HDMI_PLL_RESET
	.comm	_VPU_COMPATIBLE_G12A,4,2        ## @VPU_COMPATIBLE_G12A
	.comm	_HHI_HDMI_PLL_CNTL7,4,2         ## @HHI_HDMI_PLL_CNTL7
	.comm	_HDMI_PLL_LOCK_G12A,4,2         ## @HDMI_PLL_LOCK_G12A
	.comm	_HHI_VIID_CLK_CNTL,4,2          ## @HHI_VIID_CLK_CNTL
	.comm	_VCLK2_EN,4,2                   ## @VCLK2_EN
	.comm	_VID_PLL_DIV_1,4,2              ## @VID_PLL_DIV_1
	.comm	_HHI_VIID_CLK_DIV,4,2           ## @HHI_VIID_CLK_DIV
	.comm	_VCLK2_DIV_MASK,4,2             ## @VCLK2_DIV_MASK
	.comm	_VCLK2_SEL_MASK,4,2             ## @VCLK2_SEL_MASK
	.comm	_VCLK2_SEL_SHIFT,4,2            ## @VCLK2_SEL_SHIFT
	.comm	_HHI_VID_CLK_DIV,4,2            ## @HHI_VID_CLK_DIV
	.comm	_CTS_ENCI_SEL_MASK,4,2          ## @CTS_ENCI_SEL_MASK
	.comm	_CTS_ENCI_SEL_SHIFT,4,2         ## @CTS_ENCI_SEL_SHIFT
	.comm	_CTS_VDAC_SEL_MASK,4,2          ## @CTS_VDAC_SEL_MASK
	.comm	_CTS_VDAC_SEL_SHIFT,4,2         ## @CTS_VDAC_SEL_SHIFT
	.comm	_VCLK2_DIV_EN,4,2               ## @VCLK2_DIV_EN
	.comm	_VCLK2_DIV_RESET,4,2            ## @VCLK2_DIV_RESET
	.comm	_VCLK2_DIV1_EN,4,2              ## @VCLK2_DIV1_EN
	.comm	_VCLK2_SOFT_RESET,4,2           ## @VCLK2_SOFT_RESET
	.comm	_HHI_VID_CLK_CNTL2,4,2          ## @HHI_VID_CLK_CNTL2
	.comm	_CTS_ENCI_EN,4,2                ## @CTS_ENCI_EN
	.comm	_CTS_VDAC_EN,4,2                ## @CTS_VDAC_EN
	.no_dead_strip	_meson_venci_cvbs_clock_config
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function meson_venci_cvbs_clock_config
_meson_venci_cvbs_clock_config:         ; @meson_venci_cvbs_clock_config
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x8, _VPU_COMPATIBLE_GXBB@GOTPAGE
Lloh1:
	ldr	x8, [x8, _VPU_COMPATIBLE_GXBB@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	bl	_meson_vpu_is_compatible
Lloh3:
	adrp	x20, _VPU_COMPATIBLE_G12A@GOTPAGE
Lloh4:
	ldr	x20, [x20, _VPU_COMPATIBLE_G12A@GOTPAGEOFF]
	cbz	x0, LBB0_2
; %bb.1:
	ldr	w0, [x19]
Lloh5:
	adrp	x21, _HHI_HDMI_PLL_CNTL@GOTPAGE
Lloh6:
	ldr	x21, [x21, _HHI_HDMI_PLL_CNTL@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	w2, #573
	movk	w2, #22528, lsl #16
	bl	_regmap_write
	ldr	w0, [x19]
Lloh7:
	adrp	x8, _HHI_HDMI_PLL_CNTL2@GOTPAGE
Lloh8:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL2@GOTPAGEOFF]
Lloh9:
	ldr	w1, [x8]
	mov	w2, #19968
	movk	w2, #64, lsl #16
	bl	_regmap_write
	ldr	w0, [x19]
Lloh10:
	adrp	x8, _HHI_HDMI_PLL_CNTL3@GOTPAGE
Lloh11:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL3@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
	mov	w2, #20625
	movk	w2, #3420, lsl #16
	bl	_regmap_write
	ldr	w0, [x19]
Lloh13:
	adrp	x8, _HHI_HDMI_PLL_CNTL4@GOTPAGE
Lloh14:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL4@GOTPAGEOFF]
Lloh15:
	ldr	w1, [x8]
	mov	w2, #42796
	movk	w2, #32797, lsl #16
	bl	_regmap_write
	ldr	w0, [x19]
Lloh16:
	adrp	x8, _HHI_HDMI_PLL_CNTL5@GOTPAGE
Lloh17:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL5@GOTPAGEOFF]
Lloh18:
	ldr	w1, [x8]
	mov	w2, #27008
	movk	w2, #29000, lsl #16
	bl	_regmap_write
	ldr	w0, [x19]
Lloh19:
	adrp	x8, _HHI_HDMI_PLL_CNTL6@GOTPAGE
Lloh20:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL6@GOTPAGEOFF]
Lloh21:
	ldr	w1, [x8]
	mov	w2, #3669
	bl	_regmap_write
	ldr	w0, [x19]
	ldr	w1, [x21]
	mov	w2, #573
	movk	w2, #18432, lsl #16
	bl	_regmap_write
	b	LBB0_5
LBB0_2:
Lloh22:
	adrp	x8, _VPU_COMPATIBLE_GXM@GOTPAGE
Lloh23:
	ldr	x8, [x8, _VPU_COMPATIBLE_GXM@GOTPAGEOFF]
Lloh24:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_meson_vpu_is_compatible
	cbnz	x0, LBB0_4
; %bb.3:
Lloh25:
	adrp	x8, _VPU_COMPATIBLE_GXL@GOTPAGE
Lloh26:
	ldr	x8, [x8, _VPU_COMPATIBLE_GXL@GOTPAGEOFF]
Lloh27:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_8
LBB0_4:
	ldr	w0, [x19]
Lloh28:
	adrp	x21, _HHI_HDMI_PLL_CNTL@GOTPAGE
Lloh29:
	ldr	x21, [x21, _HHI_HDMI_PLL_CNTL@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	w2, #635
	movk	w2, #16384, lsl #16
	bl	_regmap_write
	ldr	w0, [x19]
Lloh30:
	adrp	x8, _HHI_HDMI_PLL_CNTL2@GOTPAGE
Lloh31:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL2@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
	mov	w2, #45824
	movk	w2, #32780, lsl #16
	bl	_regmap_write
	ldr	w0, [x19]
Lloh33:
	adrp	x8, _HHI_HDMI_PLL_CNTL3@GOTPAGE
Lloh34:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL3@GOTPAGEOFF]
Lloh35:
	ldr	w1, [x8]
	mov	w2, #10308
	movk	w2, #42529, lsl #16
	bl	_regmap_write
	ldr	w0, [x19]
Lloh36:
	adrp	x8, _HHI_HDMI_PLL_CNTL4@GOTPAGE
Lloh37:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL4@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
	mov	w2, #12
	movk	w2, #3149, lsl #16
	bl	_regmap_write
	ldr	w0, [x19]
Lloh39:
	adrp	x8, _HHI_HDMI_PLL_CNTL5@GOTPAGE
Lloh40:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL5@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	mov	w2, #42793
	movk	w2, #31, lsl #16
	bl	_regmap_write
	ldr	w0, [x19]
Lloh42:
	adrp	x8, _HHI_HDMI_PLL_CNTL6@GOTPAGE
Lloh43:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL6@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x8]
	mov	w2, #5376
	movk	w2, #419, lsl #16
	bl	_regmap_write
	ldr	w0, [x19]
	ldr	w1, [x21]
Lloh45:
	adrp	x22, _HDMI_PLL_RESET@GOTPAGE
Lloh46:
	ldr	x22, [x22, _HDMI_PLL_RESET@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x21]
	ldr	w2, [x22]
	mov	w3, #0
	bl	_regmap_update_bits
LBB0_5:
	ldr	w0, [x19]
	ldr	w1, [x21]
	mov	w3, #0
LBB0_6:
	mov	w4, #10
	mov	w5, #0
	bl	_regmap_read_poll_timeout
LBB0_7:
	ldr	w0, [x19]
Lloh47:
	adrp	x21, _HHI_VIID_CLK_CNTL@GOTPAGE
Lloh48:
	ldr	x21, [x21, _HHI_VIID_CLK_CNTL@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh49:
	adrp	x23, _VCLK2_EN@GOTPAGE
Lloh50:
	ldr	x23, [x23, _VCLK2_EN@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	w3, #0
	bl	_regmap_update_bits
Lloh51:
	adrp	x8, _VID_PLL_DIV_1@GOTPAGE
Lloh52:
	ldr	x8, [x8, _VID_PLL_DIV_1@GOTPAGEOFF]
Lloh53:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_meson_vid_pll_set
	ldr	w0, [x19]
Lloh54:
	adrp	x22, _HHI_VIID_CLK_DIV@GOTPAGE
Lloh55:
	ldr	x22, [x22, _HHI_VIID_CLK_DIV@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh56:
	adrp	x8, _VCLK2_DIV_MASK@GOTPAGE
Lloh57:
	ldr	x8, [x8, _VCLK2_DIV_MASK@GOTPAGEOFF]
Lloh58:
	ldr	w2, [x8]
	mov	w3, #54
	bl	_regmap_update_bits
	ldr	w1, [x20]
	mov	x0, x19
	bl	_meson_vpu_is_compatible
	ldr	w8, [x19]
	ldr	w1, [x21]
Lloh59:
	adrp	x9, _VCLK2_SEL_MASK@GOTPAGE
Lloh60:
	ldr	x9, [x9, _VCLK2_SEL_MASK@GOTPAGEOFF]
Lloh61:
	adrp	x10, _VCLK2_SEL_SHIFT@GOTPAGE
Lloh62:
	ldr	x10, [x10, _VCLK2_SEL_SHIFT@GOTPAGEOFF]
Lloh63:
	ldr	w2, [x9]
Lloh64:
	ldr	w9, [x10]
	mov	w10, #4
	lsl	w9, w10, w9
	cmp	x0, #0
	csel	w3, w9, wzr, eq
	mov	x0, x8
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x21]
	ldr	w2, [x23]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
Lloh65:
	adrp	x8, _HHI_VID_CLK_DIV@GOTPAGE
Lloh66:
	ldr	x8, [x8, _HHI_VID_CLK_DIV@GOTPAGEOFF]
Lloh67:
	ldr	w1, [x8]
Lloh68:
	adrp	x8, _CTS_ENCI_SEL_MASK@GOTPAGE
Lloh69:
	ldr	x8, [x8, _CTS_ENCI_SEL_MASK@GOTPAGEOFF]
Lloh70:
	ldr	w2, [x8]
Lloh71:
	adrp	x8, _CTS_ENCI_SEL_SHIFT@GOTPAGE
Lloh72:
	ldr	x8, [x8, _CTS_ENCI_SEL_SHIFT@GOTPAGEOFF]
Lloh73:
	ldr	w8, [x8]
	mov	w20, #8
	lsl	w3, w20, w8
	bl	_regmap_update_bits
	ldr	w0, [x19]
Lloh74:
	adrp	x8, _CTS_VDAC_SEL_MASK@GOTPAGE
Lloh75:
	ldr	x8, [x8, _CTS_VDAC_SEL_MASK@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh76:
	ldr	w2, [x8]
Lloh77:
	adrp	x8, _CTS_VDAC_SEL_SHIFT@GOTPAGE
Lloh78:
	ldr	x8, [x8, _CTS_VDAC_SEL_SHIFT@GOTPAGEOFF]
Lloh79:
	ldr	w8, [x8]
	lsl	w3, w20, w8
	bl	_regmap_update_bits
	ldr	w0, [x19]
Lloh80:
	adrp	x8, _VCLK2_DIV_EN@GOTPAGE
Lloh81:
	ldr	x8, [x8, _VCLK2_DIV_EN@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh82:
	ldr	w3, [x8]
Lloh83:
	adrp	x8, _VCLK2_DIV_RESET@GOTPAGE
Lloh84:
	ldr	x8, [x8, _VCLK2_DIV_RESET@GOTPAGEOFF]
Lloh85:
	ldr	w8, [x8]
	orr	w2, w8, w3
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x21]
Lloh86:
	adrp	x8, _VCLK2_DIV1_EN@GOTPAGE
Lloh87:
	ldr	x8, [x8, _VCLK2_DIV1_EN@GOTPAGEOFF]
Lloh88:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x21]
Lloh89:
	adrp	x20, _VCLK2_SOFT_RESET@GOTPAGE
Lloh90:
	ldr	x20, [x20, _VCLK2_SOFT_RESET@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x21]
	ldr	w2, [x20]
	mov	w3, #0
	bl	_regmap_update_bits
	ldr	w0, [x19]
Lloh91:
	adrp	x20, _HHI_VID_CLK_CNTL2@GOTPAGE
Lloh92:
	ldr	x20, [x20, _HHI_VID_CLK_CNTL2@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh93:
	adrp	x8, _CTS_ENCI_EN@GOTPAGE
Lloh94:
	ldr	x8, [x8, _CTS_ENCI_EN@GOTPAGEOFF]
Lloh95:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
Lloh96:
	adrp	x8, _CTS_VDAC_EN@GOTPAGE
Lloh97:
	ldr	x8, [x8, _CTS_VDAC_EN@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh98:
	ldr	w2, [x8]
	mov	x3, x2
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_regmap_update_bits
LBB0_8:
	ldr	w1, [x20]
	mov	x0, x19
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_7
; %bb.9:
	ldr	w0, [x19]
Lloh99:
	adrp	x21, _HHI_HDMI_PLL_CNTL@GOTPAGE
Lloh100:
	ldr	x21, [x21, _HHI_HDMI_PLL_CNTL@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	w2, #1271
	movk	w2, #6661, lsl #16
	bl	_regmap_write
	ldr	w0, [x19]
Lloh101:
	adrp	x8, _HHI_HDMI_PLL_CNTL2@GOTPAGE
Lloh102:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL2@GOTPAGEOFF]
Lloh103:
	ldr	w1, [x8]
	mov	w2, #65536
	bl	_regmap_write
	ldr	w0, [x19]
Lloh104:
	adrp	x8, _HHI_HDMI_PLL_CNTL3@GOTPAGE
Lloh105:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL3@GOTPAGEOFF]
Lloh106:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_regmap_write
	ldr	w0, [x19]
Lloh107:
	adrp	x8, _HHI_HDMI_PLL_CNTL4@GOTPAGE
Lloh108:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL4@GOTPAGEOFF]
Lloh109:
	ldr	w1, [x8]
	mov	w2, #56320
	movk	w2, #27176, lsl #16
	bl	_regmap_write
	ldr	w0, [x19]
Lloh110:
	adrp	x8, _HHI_HDMI_PLL_CNTL5@GOTPAGE
Lloh111:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL5@GOTPAGEOFF]
Lloh112:
	ldr	w1, [x8]
	mov	w2, #4752
	movk	w2, #25975, lsl #16
	bl	_regmap_write
	ldr	w0, [x19]
Lloh113:
	adrp	x8, _HHI_HDMI_PLL_CNTL6@GOTPAGE
Lloh114:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL6@GOTPAGEOFF]
Lloh115:
	ldr	w1, [x8]
	mov	w2, #8192
	movk	w2, #14631, lsl #16
	bl	_regmap_write
	ldr	w0, [x19]
Lloh116:
	adrp	x8, _HHI_HDMI_PLL_CNTL7@GOTPAGE
Lloh117:
	ldr	x8, [x8, _HHI_HDMI_PLL_CNTL7@GOTPAGEOFF]
Lloh118:
	ldr	w1, [x8]
	mov	w2, #1448345600
	bl	_regmap_write
	ldr	w0, [x19]
	ldr	w1, [x21]
	mov	w2, #1271
	movk	w2, #14853, lsl #16
	bl	_regmap_write
	ldr	w0, [x19]
	ldr	w1, [x21]
	mov	w2, #1271
	movk	w2, #6661, lsl #16
	bl	_regmap_write
	ldr	w0, [x19]
	ldr	w1, [x21]
Lloh119:
	adrp	x8, _HDMI_PLL_LOCK_G12A@GOTPAGE
Lloh120:
	ldr	x8, [x8, _HDMI_PLL_LOCK_G12A@GOTPAGEOFF]
Lloh121:
	ldr	w8, [x8]
	cmp	w8, #0
	cset	w3, eq
	b	LBB0_6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGot	Lloh91, Lloh92
	.loh AdrpLdrGot	Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh63
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGot	Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGot	Lloh99, Lloh100
	.cfi_endproc
                                        ; -- End function
	.comm	_VPU_COMPATIBLE_GXBB,4,2        ; @VPU_COMPATIBLE_GXBB
	.comm	_HHI_HDMI_PLL_CNTL,4,2          ; @HHI_HDMI_PLL_CNTL
	.comm	_HHI_HDMI_PLL_CNTL2,4,2         ; @HHI_HDMI_PLL_CNTL2
	.comm	_HHI_HDMI_PLL_CNTL3,4,2         ; @HHI_HDMI_PLL_CNTL3
	.comm	_HHI_HDMI_PLL_CNTL4,4,2         ; @HHI_HDMI_PLL_CNTL4
	.comm	_HHI_HDMI_PLL_CNTL5,4,2         ; @HHI_HDMI_PLL_CNTL5
	.comm	_HHI_HDMI_PLL_CNTL6,4,2         ; @HHI_HDMI_PLL_CNTL6
	.comm	_HDMI_PLL_LOCK,4,2              ; @HDMI_PLL_LOCK
	.comm	_VPU_COMPATIBLE_GXM,4,2         ; @VPU_COMPATIBLE_GXM
	.comm	_VPU_COMPATIBLE_GXL,4,2         ; @VPU_COMPATIBLE_GXL
	.comm	_HDMI_PLL_RESET,4,2             ; @HDMI_PLL_RESET
	.comm	_VPU_COMPATIBLE_G12A,4,2        ; @VPU_COMPATIBLE_G12A
	.comm	_HHI_HDMI_PLL_CNTL7,4,2         ; @HHI_HDMI_PLL_CNTL7
	.comm	_HDMI_PLL_LOCK_G12A,4,2         ; @HDMI_PLL_LOCK_G12A
	.comm	_HHI_VIID_CLK_CNTL,4,2          ; @HHI_VIID_CLK_CNTL
	.comm	_VCLK2_EN,4,2                   ; @VCLK2_EN
	.comm	_VID_PLL_DIV_1,4,2              ; @VID_PLL_DIV_1
	.comm	_HHI_VIID_CLK_DIV,4,2           ; @HHI_VIID_CLK_DIV
	.comm	_VCLK2_DIV_MASK,4,2             ; @VCLK2_DIV_MASK
	.comm	_VCLK2_SEL_MASK,4,2             ; @VCLK2_SEL_MASK
	.comm	_VCLK2_SEL_SHIFT,4,2            ; @VCLK2_SEL_SHIFT
	.comm	_HHI_VID_CLK_DIV,4,2            ; @HHI_VID_CLK_DIV
	.comm	_CTS_ENCI_SEL_MASK,4,2          ; @CTS_ENCI_SEL_MASK
	.comm	_CTS_ENCI_SEL_SHIFT,4,2         ; @CTS_ENCI_SEL_SHIFT
	.comm	_CTS_VDAC_SEL_MASK,4,2          ; @CTS_VDAC_SEL_MASK
	.comm	_CTS_VDAC_SEL_SHIFT,4,2         ; @CTS_VDAC_SEL_SHIFT
	.comm	_VCLK2_DIV_EN,4,2               ; @VCLK2_DIV_EN
	.comm	_VCLK2_DIV_RESET,4,2            ; @VCLK2_DIV_RESET
	.comm	_VCLK2_DIV1_EN,4,2              ; @VCLK2_DIV1_EN
	.comm	_VCLK2_SOFT_RESET,4,2           ; @VCLK2_SOFT_RESET
	.comm	_HHI_VID_CLK_CNTL2,4,2          ; @HHI_VID_CLK_CNTL2
	.comm	_CTS_ENCI_EN,4,2                ; @CTS_ENCI_EN
	.comm	_CTS_VDAC_EN,4,2                ; @CTS_VDAC_EN
	.no_dead_strip	_meson_venci_cvbs_clock_config
.subsections_via_symbols
