	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gmc_v10_0_gart_enable
_gmc_v10_0_gart_enable:                 ## @gmc_v10_0_gart_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	cmpq	$0, 8(%rdi)
	je	LBB0_1
## %bb.2:
	movq	%r14, %rdi
	callq	_amdgpu_gart_table_vram_pin
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_6
## %bb.3:
	movq	%r14, %rdi
	callq	_gfxhub_v2_0_gart_enable
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_6
## %bb.4:
	movq	%r14, %rdi
	callq	_mmhub_v2_0_gart_enable
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_6
## %bb.5:
	movq	_HDP@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	movq	_mmHDP_MISC_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%ebx, %ebx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r15), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r15), %edi
	movq	_mmHDP_HOST_PATH_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	(%r15), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	24(%r14), %rax
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	*(%rax)
	movq	_amdgpu_vm_fault_stop@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_AMDGPU_VM_FAULT_STOP_ALWAYS@GOTPCREL(%rip), %rcx
	xorl	%r15d, %r15d
	cmpq	(%rcx), %rax
	setne	%r15b
	movq	%r14, %rdi
	movl	%r15d, %esi
	callq	_gfxhub_v2_0_set_fault_enable_default
	movq	%r14, %rdi
	movl	%r15d, %esi
	callq	_mmhub_v2_0_set_fault_enable_default
	movq	_AMDGPU_MMHUB_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_gmc_v10_0_flush_gpu_tlb
	movq	_AMDGPU_GFXHUB_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_gmc_v10_0_flush_gpu_tlb
	movl	16(%r14), %r15d
	sarl	$20, %r15d
	movq	8(%r14), %rdi
	callq	_amdgpu_bo_gpu_offset
	leaq	L_.str.1(%rip), %rdi
	movl	%r15d, %esi
	movq	%rax, %rdx
	callq	_DRM_INFO
	movl	$1, (%r14)
	jmp	LBB0_6
LBB0_1:
	movl	32(%r14), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
LBB0_6:
	movl	%ebx, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"No VRAM object for PCIE GART.\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_HDP,4,2                        ## @HDP
	.comm	_mmHDP_MISC_CNTL,4,2            ## @mmHDP_MISC_CNTL
	.comm	_HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK,4,2 ## @HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK
	.comm	_mmHDP_HOST_PATH_CNTL,4,2       ## @mmHDP_HOST_PATH_CNTL
	.comm	_amdgpu_vm_fault_stop,8,3       ## @amdgpu_vm_fault_stop
	.comm	_AMDGPU_VM_FAULT_STOP_ALWAYS,8,3 ## @AMDGPU_VM_FAULT_STOP_ALWAYS
	.comm	_AMDGPU_MMHUB_0,4,2             ## @AMDGPU_MMHUB_0
	.comm	_AMDGPU_GFXHUB_0,4,2            ## @AMDGPU_GFXHUB_0
L_.str.1:                               ## @.str.1
	.asciz	"PCIE GART of %uM enabled (table at 0x%016llX).\n"

	.no_dead_strip	_gmc_v10_0_gart_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gmc_v10_0_gart_enable
_gmc_v10_0_gart_enable:                 ; @gmc_v10_0_gart_enable
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x8, [x0, #8]
	cbz	x8, LBB0_5
; %bb.1:
	mov	x0, x19
	bl	_amdgpu_gart_table_vram_pin
	cbnz	w0, LBB0_6
; %bb.2:
	mov	x0, x19
	bl	_gfxhub_v2_0_gart_enable
	cbnz	w0, LBB0_6
; %bb.3:
	mov	x0, x19
	bl	_mmhub_v2_0_gart_enable
	cbnz	w0, LBB0_6
; %bb.4:
Lloh0:
	adrp	x20, _HDP@GOTPAGE
Lloh1:
	ldr	x20, [x20, _HDP@GOTPAGEOFF]
	ldr	w0, [x20]
Lloh2:
	adrp	x21, _mmHDP_MISC_CNTL@GOTPAGE
Lloh3:
	ldr	x21, [x21, _mmHDP_MISC_CNTL@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh4:
	adrp	x8, _HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK@GOTPAGE
Lloh5:
	ldr	x8, [x8, _HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
	orr	w3, w8, w0
	ldr	w0, [x20]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x20]
Lloh7:
	adrp	x21, _mmHDP_HOST_PATH_CNTL@GOTPAGE
Lloh8:
	ldr	x21, [x21, _mmHDP_HOST_PATH_CNTL@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_RREG32_SOC15
	mov	x3, x0
	ldr	w0, [x20]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	x8, [x19, #24]
	ldr	x8, [x8]
	mov	x0, x19
	mov	x1, #0
	blr	x8
Lloh9:
	adrp	x8, _amdgpu_vm_fault_stop@GOTPAGE
Lloh10:
	ldr	x8, [x8, _amdgpu_vm_fault_stop@GOTPAGEOFF]
Lloh11:
	ldr	x8, [x8]
Lloh12:
	adrp	x9, _AMDGPU_VM_FAULT_STOP_ALWAYS@GOTPAGE
Lloh13:
	ldr	x9, [x9, _AMDGPU_VM_FAULT_STOP_ALWAYS@GOTPAGEOFF]
Lloh14:
	ldr	x9, [x9]
	cmp	x8, x9
	cset	w20, ne
	mov	x0, x19
	mov	x1, x20
	bl	_gfxhub_v2_0_set_fault_enable_default
	mov	x0, x19
	mov	x1, x20
	bl	_mmhub_v2_0_set_fault_enable_default
Lloh15:
	adrp	x8, _AMDGPU_MMHUB_0@GOTPAGE
Lloh16:
	ldr	x8, [x8, _AMDGPU_MMHUB_0@GOTPAGEOFF]
Lloh17:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w1, #0
	mov	w3, #0
	bl	_gmc_v10_0_flush_gpu_tlb
Lloh18:
	adrp	x8, _AMDGPU_GFXHUB_0@GOTPAGE
Lloh19:
	ldr	x8, [x8, _AMDGPU_GFXHUB_0@GOTPAGEOFF]
Lloh20:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w1, #0
	mov	w3, #0
	bl	_gmc_v10_0_flush_gpu_tlb
	ldr	w8, [x19, #16]
	asr	w20, w8, #20
	ldr	x0, [x19, #8]
	bl	_amdgpu_bo_gpu_offset
	mov	x2, x0
Lloh21:
	adrp	x0, l_.str.1@PAGE
Lloh22:
	add	x0, x0, l_.str.1@PAGEOFF
	mov	x1, x20
	bl	_DRM_INFO
	mov	w0, #0
	mov	w8, #1
	str	w8, [x19]
	b	LBB0_6
LBB0_5:
	ldr	w0, [x19, #32]
Lloh23:
	adrp	x1, l_.str@PAGE
Lloh24:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
Lloh25:
	adrp	x8, _EINVAL@GOTPAGE
Lloh26:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_6:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpAdd	Lloh23, Lloh24
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"No VRAM object for PCIE GART.\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_HDP,4,2                        ; @HDP
	.comm	_mmHDP_MISC_CNTL,4,2            ; @mmHDP_MISC_CNTL
	.comm	_HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK,4,2 ; @HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK
	.comm	_mmHDP_HOST_PATH_CNTL,4,2       ; @mmHDP_HOST_PATH_CNTL
	.comm	_amdgpu_vm_fault_stop,8,3       ; @amdgpu_vm_fault_stop
	.comm	_AMDGPU_VM_FAULT_STOP_ALWAYS,8,3 ; @AMDGPU_VM_FAULT_STOP_ALWAYS
	.comm	_AMDGPU_MMHUB_0,4,2             ; @AMDGPU_MMHUB_0
	.comm	_AMDGPU_GFXHUB_0,4,2            ; @AMDGPU_GFXHUB_0
l_.str.1:                               ; @.str.1
	.asciz	"PCIE GART of %uM enabled (table at 0x%016llX).\n"

	.no_dead_strip	_gmc_v10_0_gart_enable
.subsections_via_symbols
