	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vce_v4_0_sriov_start
_vce_v4_0_sriov_start:                  ## @vce_v4_0_sriov_start
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r13
	movq	$0, -56(%rbp)
	movq	(%rdi), %r14
	movq	_MMSCH_COMMAND__END@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -56(%rbp)
	cmpl	$0, (%r14)
	jne	LBB0_6
## %bb.1:
	cmpq	$0, 8(%r14)
	jne	LBB0_6
## %bb.2:
	movq	_MMSCH_VERSION@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 28(%r14)
	movl	$8, 16(%r14)
	movl	20(%r14), %eax
	movl	24(%r14), %ecx
	leal	(%rcx,%rax), %edx
	orl	%ecx, %eax
	movl	$8, %eax
	cmovnel	%edx, %eax
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movl	%eax, (%r14)
	movq	32(%r13), %r15
	movq	_VCE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	%rax, %r12
	movq	_mmVCE_RB_BASE_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %ebx
	movl	4(%r15), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r12), %edi
	movq	_mmVCE_RB_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %ebx
	movl	4(%r15), %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r12), %edi
	movq	_mmVCE_RB_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r15), %ecx
	leal	3(%rcx), %esi
	testl	%ecx, %ecx
	cmovnsl	%ecx, %esi
	sarl	$2, %esi
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r12), %edi
	movq	_mmVCE_LMI_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	$3768320, %esi                  ## imm = 0x398000
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r12), %edi
	movq	_mmVCE_LMI_CACHE_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	$-2, %esi
	xorl	%edx, %edx
	callq	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	movl	(%r12), %edi
	movq	_mmVCE_LMI_SWAP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r12), %edi
	movq	_mmVCE_LMI_SWAP_CNTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r12), %edi
	movq	_mmVCE_LMI_VM_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movq	_AMDGPU_VCE_FIRMWARE_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	8(%r13), %rbx
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rax
	movq	(%rax), %r12
	movq	_VCE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movslq	-48(%rbp), %rcx                 ## 4-byte Folded Reload
	leaq	(%r14,%rcx,4), %rcx
	movq	%rcx, -48(%rbp)                 ## 8-byte Spill
	cmpq	%r12, %rbx
	jne	LBB0_4
## %bb.3:
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movq	_VCE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_mmVCE_LMI_VCPU_CACHE_64BIT_BAR0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%rbx), %edi
	movq	_mmVCE_VCPU_CACHE_OFFSET0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	xorl	%esi, %esi
	jmp	LBB0_5
LBB0_4:
	movl	24(%r13), %esi
	sarl	$8, %esi
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movq	_VCE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_mmVCE_LMI_VCPU_CACHE_64BIT_BAR0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%rbx), %edi
	movq	_mmVCE_VCPU_CACHE_OFFSET0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%r15d, %esi
	andl	$-251658241, %esi               ## imm = 0xF0FFFFFF
	movl	%eax, %edi
LBB0_5:
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movq	_VCE@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	movq	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	24(%r13), %esi
	sarl	$8, %esi
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r12), %edi
	movq	_mmVCE_LMI_VCPU_CACHE_64BIT_BAR1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r12), %edi
	movq	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	24(%r13), %esi
	sarl	$8, %esi
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%r12), %edi
	movq	_mmVCE_LMI_VCPU_CACHE_64BIT_BAR2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movq	_VCE_V4_0_FW_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	(%r12), %edi
	movq	_mmVCE_VCPU_CACHE_SIZE0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	%ebx, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movq	8(%r13), %rax
	addl	%ebx, %r15d
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	movl	$0, %eax
	cmovel	%eax, %r15d
	movq	_VCE_V4_0_STACK_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	_VCE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_mmVCE_VCPU_CACHE_OFFSET1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%r15d, %esi
	andl	$-251658241, %esi               ## imm = 0xF0FFFFFF
	orl	$16777216, %esi                 ## imm = 0x1000000
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%rbx), %edi
	movq	_mmVCE_VCPU_CACHE_SIZE1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	%r12d, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	addl	%r12d, %r15d
	movq	_VCE_V4_0_DATA_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	(%rbx), %edi
	movq	_mmVCE_VCPU_CACHE_OFFSET2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	andl	$-251658241, %r15d              ## imm = 0xF0FFFFFF
	orl	$33554432, %r15d                ## imm = 0x2000000
	movl	%eax, %edi
	movl	%r15d, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%rbx), %edi
	movq	_mmVCE_VCPU_CACHE_SIZE2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	%r12d, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_WT
	movl	(%rbx), %edi
	movq	_mmVCE_LMI_CTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	$-257, %esi                     ## imm = 0xFEFF
	xorl	%edx, %edx
	callq	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	movl	(%rbx), %edi
	movq	_mmVCE_SYS_INT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	%edx, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	movl	(%rbx), %edi
	movq	_mmVCE_STATUS@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_VCE_STATUS__JOB_BUSY_MASK@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	callq	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	movl	(%rbx), %edi
	movq	_mmVCE_VCPU_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_VCE_VCPU_CNTL__CLK_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$-2097154, %esi                 ## imm = 0xFFDFFFFE
	callq	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	movl	(%rbx), %edi
	movq	_mmVCE_SOFT_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	movl	%eax, %edi
	xorl	%edx, %edx
	callq	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	movl	(%rbx), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	%edx, %esi
	callq	_MMSCH_V1_0_INSERT_DIRECT_POLL
	movl	(%rbx), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r15), %esi
	notl	%esi
	movl	%eax, %edi
	xorl	%edx, %edx
	callq	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	leaq	-56(%rbp), %rsi
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movl	$8, %edx
	callq	_memcpy
	movq	$2, 8(%r14)
LBB0_6:
	movq	%r13, %rdi
	movq	%r13, %rsi
	callq	_vce_v4_0_mmsch_start
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MMSCH_COMMAND__DIRECT_REG_WRITE,4,2 ## @MMSCH_COMMAND__DIRECT_REG_WRITE
	.comm	_MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE,4,2 ## @MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE
	.comm	_MMSCH_COMMAND__DIRECT_REG_POLLING,4,2 ## @MMSCH_COMMAND__DIRECT_REG_POLLING
	.comm	_MMSCH_COMMAND__END,4,2         ## @MMSCH_COMMAND__END
	.comm	_MMSCH_VERSION,4,2              ## @MMSCH_VERSION
	.comm	_VCE,4,2                        ## @VCE
	.comm	_mmVCE_RB_BASE_LO,4,2           ## @mmVCE_RB_BASE_LO
	.comm	_mmVCE_RB_BASE_HI,4,2           ## @mmVCE_RB_BASE_HI
	.comm	_mmVCE_RB_SIZE,4,2              ## @mmVCE_RB_SIZE
	.comm	_mmVCE_LMI_CTRL,4,2             ## @mmVCE_LMI_CTRL
	.comm	_mmVCE_LMI_CACHE_CTRL,4,2       ## @mmVCE_LMI_CACHE_CTRL
	.comm	_mmVCE_LMI_SWAP_CNTL,4,2        ## @mmVCE_LMI_SWAP_CNTL
	.comm	_mmVCE_LMI_SWAP_CNTL1,4,2       ## @mmVCE_LMI_SWAP_CNTL1
	.comm	_mmVCE_LMI_VM_CTRL,4,2          ## @mmVCE_LMI_VM_CTRL
	.comm	_AMDGPU_VCE_FIRMWARE_OFFSET,4,2 ## @AMDGPU_VCE_FIRMWARE_OFFSET
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_VCE,8,3        ## @AMDGPU_UCODE_ID_VCE
	.comm	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR0,4,2 ## @mmVCE_LMI_VCPU_CACHE_40BIT_BAR0
	.comm	_mmVCE_LMI_VCPU_CACHE_64BIT_BAR0,4,2 ## @mmVCE_LMI_VCPU_CACHE_64BIT_BAR0
	.comm	_mmVCE_VCPU_CACHE_OFFSET0,4,2   ## @mmVCE_VCPU_CACHE_OFFSET0
	.comm	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR1,4,2 ## @mmVCE_LMI_VCPU_CACHE_40BIT_BAR1
	.comm	_mmVCE_LMI_VCPU_CACHE_64BIT_BAR1,4,2 ## @mmVCE_LMI_VCPU_CACHE_64BIT_BAR1
	.comm	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR2,4,2 ## @mmVCE_LMI_VCPU_CACHE_40BIT_BAR2
	.comm	_mmVCE_LMI_VCPU_CACHE_64BIT_BAR2,4,2 ## @mmVCE_LMI_VCPU_CACHE_64BIT_BAR2
	.comm	_VCE_V4_0_FW_SIZE,4,2           ## @VCE_V4_0_FW_SIZE
	.comm	_mmVCE_VCPU_CACHE_SIZE0,4,2     ## @mmVCE_VCPU_CACHE_SIZE0
	.comm	_VCE_V4_0_STACK_SIZE,4,2        ## @VCE_V4_0_STACK_SIZE
	.comm	_mmVCE_VCPU_CACHE_OFFSET1,4,2   ## @mmVCE_VCPU_CACHE_OFFSET1
	.comm	_mmVCE_VCPU_CACHE_SIZE1,4,2     ## @mmVCE_VCPU_CACHE_SIZE1
	.comm	_VCE_V4_0_DATA_SIZE,4,2         ## @VCE_V4_0_DATA_SIZE
	.comm	_mmVCE_VCPU_CACHE_OFFSET2,4,2   ## @mmVCE_VCPU_CACHE_OFFSET2
	.comm	_mmVCE_VCPU_CACHE_SIZE2,4,2     ## @mmVCE_VCPU_CACHE_SIZE2
	.comm	_mmVCE_LMI_CTRL2,4,2            ## @mmVCE_LMI_CTRL2
	.comm	_mmVCE_SYS_INT_EN,4,2           ## @mmVCE_SYS_INT_EN
	.comm	_VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK,4,2 ## @VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK
	.comm	_mmVCE_STATUS,4,2               ## @mmVCE_STATUS
	.comm	_VCE_STATUS__JOB_BUSY_MASK,4,2  ## @VCE_STATUS__JOB_BUSY_MASK
	.comm	_mmVCE_VCPU_CNTL,4,2            ## @mmVCE_VCPU_CNTL
	.comm	_VCE_VCPU_CNTL__CLK_EN_MASK,4,2 ## @VCE_VCPU_CNTL__CLK_EN_MASK
	.comm	_mmVCE_SOFT_RESET,4,2           ## @mmVCE_SOFT_RESET
	.comm	_VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,4,2 ## @VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
	.comm	_VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK,4,2 ## @VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK
	.no_dead_strip	_vce_v4_0_sriov_start
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vce_v4_0_sriov_start
_vce_v4_0_sriov_start:                  ; @vce_v4_0_sriov_start
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	str	xzr, [sp, #8]
	ldr	x22, [x0]
Lloh0:
	adrp	x8, _MMSCH_COMMAND__END@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MMSCH_COMMAND__END@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	str	w8, [sp, #8]
	ldr	w8, [x22]
	cbnz	w8, LBB0_6
; %bb.1:
	ldr	x8, [x22, #8]
	cbnz	x8, LBB0_6
; %bb.2:
Lloh3:
	adrp	x8, _MMSCH_VERSION@GOTPAGE
Lloh4:
	ldr	x8, [x8, _MMSCH_VERSION@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	str	w8, [x22, #28]
	mov	w8, #8
	str	w8, [x22, #16]
	ldp	w9, w10, [x22, #20]
	orr	w11, w9, w10
	add	w9, w10, w9
	cmp	w11, #0
	csel	w8, w8, w9, eq
	str	w8, [x22]
	add	x20, x22, w8, sxtw #2
	ldr	x24, [x19, #32]
Lloh6:
	adrp	x23, _VCE@GOTPAGE
Lloh7:
	ldr	x23, [x23, _VCE@GOTPAGEOFF]
	ldr	w0, [x23]
Lloh8:
	adrp	x8, _mmVCE_RB_BASE_LO@GOTPAGE
Lloh9:
	ldr	x8, [x8, _mmVCE_RB_BASE_LO@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x21, x0
	ldr	w0, [x24, #4]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x21
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x23]
Lloh11:
	adrp	x8, _mmVCE_RB_BASE_HI@GOTPAGE
Lloh12:
	ldr	x8, [x8, _mmVCE_RB_BASE_HI@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x21, x0
	ldr	w0, [x24, #4]
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x21
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x23]
Lloh14:
	adrp	x8, _mmVCE_RB_SIZE@GOTPAGE
Lloh15:
	ldr	x8, [x8, _mmVCE_RB_SIZE@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x24]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w1, w8, #2
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x23]
Lloh17:
	adrp	x8, _mmVCE_LMI_CTRL@GOTPAGE
Lloh18:
	ldr	x8, [x8, _mmVCE_LMI_CTRL@GOTPAGEOFF]
Lloh19:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #32768
	movk	w1, #57, lsl #16
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x23]
Lloh20:
	adrp	x8, _mmVCE_LMI_CACHE_CTRL@GOTPAGE
Lloh21:
	ldr	x8, [x8, _mmVCE_LMI_CACHE_CTRL@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #-2
	mov	w2, #0
	bl	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	ldr	w0, [x23]
Lloh23:
	adrp	x8, _mmVCE_LMI_SWAP_CNTL@GOTPAGE
Lloh24:
	ldr	x8, [x8, _mmVCE_LMI_SWAP_CNTL@GOTPAGEOFF]
Lloh25:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x23]
Lloh26:
	adrp	x8, _mmVCE_LMI_SWAP_CNTL1@GOTPAGE
Lloh27:
	ldr	x8, [x8, _mmVCE_LMI_SWAP_CNTL1@GOTPAGEOFF]
Lloh28:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x23]
Lloh29:
	adrp	x8, _mmVCE_LMI_VM_CTRL@GOTPAGE
Lloh30:
	ldr	x8, [x8, _mmVCE_LMI_VM_CTRL@GOTPAGEOFF]
Lloh31:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
Lloh32:
	adrp	x8, _AMDGPU_VCE_FIRMWARE_OFFSET@GOTPAGE
Lloh33:
	ldr	x8, [x8, _AMDGPU_VCE_FIRMWARE_OFFSET@GOTPAGEOFF]
Lloh34:
	ldr	w24, [x8]
Lloh35:
	adrp	x25, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh36:
	ldr	x25, [x25, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
	ldr	x21, [x19, #8]
	ldr	x26, [x25]
	ldr	w0, [x23]
Lloh37:
	adrp	x8, _mmVCE_LMI_VCPU_CACHE_40BIT_BAR0@GOTPAGE
Lloh38:
	ldr	x8, [x8, _mmVCE_LMI_VCPU_CACHE_40BIT_BAR0@GOTPAGEOFF]
Lloh39:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	cmp	x21, x26
	b.ne	LBB0_4
; %bb.3:
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x23]
Lloh40:
	adrp	x8, _mmVCE_LMI_VCPU_CACHE_64BIT_BAR0@GOTPAGE
Lloh41:
	ldr	x8, [x8, _mmVCE_LMI_VCPU_CACHE_64BIT_BAR0@GOTPAGEOFF]
Lloh42:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x23]
Lloh43:
	adrp	x8, _mmVCE_VCPU_CACHE_OFFSET0@GOTPAGE
Lloh44:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_OFFSET0@GOTPAGEOFF]
Lloh45:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #0
	b	LBB0_5
LBB0_4:
	ldr	w8, [x19, #24]
	asr	w1, w8, #8
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x23]
Lloh46:
	adrp	x8, _mmVCE_LMI_VCPU_CACHE_64BIT_BAR0@GOTPAGE
Lloh47:
	ldr	x8, [x8, _mmVCE_LMI_VCPU_CACHE_64BIT_BAR0@GOTPAGEOFF]
Lloh48:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x23]
Lloh49:
	adrp	x8, _mmVCE_VCPU_CACHE_OFFSET0@GOTPAGE
Lloh50:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_OFFSET0@GOTPAGEOFF]
Lloh51:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	and	w1, w24, #0xf0ffffff
LBB0_5:
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x23]
Lloh52:
	adrp	x8, _mmVCE_LMI_VCPU_CACHE_40BIT_BAR1@GOTPAGE
Lloh53:
	ldr	x8, [x8, _mmVCE_LMI_VCPU_CACHE_40BIT_BAR1@GOTPAGEOFF]
Lloh54:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x19, #24]
	asr	w1, w8, #8
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x23]
Lloh55:
	adrp	x8, _mmVCE_LMI_VCPU_CACHE_64BIT_BAR1@GOTPAGE
Lloh56:
	ldr	x8, [x8, _mmVCE_LMI_VCPU_CACHE_64BIT_BAR1@GOTPAGEOFF]
Lloh57:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x23]
Lloh58:
	adrp	x8, _mmVCE_LMI_VCPU_CACHE_40BIT_BAR2@GOTPAGE
Lloh59:
	ldr	x8, [x8, _mmVCE_LMI_VCPU_CACHE_40BIT_BAR2@GOTPAGEOFF]
Lloh60:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x19, #24]
	asr	w1, w8, #8
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x23]
Lloh61:
	adrp	x8, _mmVCE_LMI_VCPU_CACHE_64BIT_BAR2@GOTPAGE
Lloh62:
	ldr	x8, [x8, _mmVCE_LMI_VCPU_CACHE_64BIT_BAR2@GOTPAGEOFF]
Lloh63:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
Lloh64:
	adrp	x8, _VCE_V4_0_FW_SIZE@GOTPAGE
Lloh65:
	ldr	x8, [x8, _VCE_V4_0_FW_SIZE@GOTPAGEOFF]
Lloh66:
	ldr	w21, [x8]
	ldr	w0, [x23]
Lloh67:
	adrp	x8, _mmVCE_VCPU_CACHE_SIZE0@GOTPAGE
Lloh68:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_SIZE0@GOTPAGEOFF]
Lloh69:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x1, x21
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	x8, [x19, #8]
	ldr	x9, [x25]
	add	w10, w21, w24
	cmp	x8, x9
Lloh70:
	adrp	x8, _VCE_V4_0_STACK_SIZE@GOTPAGE
Lloh71:
	ldr	x8, [x8, _VCE_V4_0_STACK_SIZE@GOTPAGEOFF]
	csel	w24, wzr, w10, eq
Lloh72:
	ldr	w21, [x8]
	ldr	w0, [x23]
Lloh73:
	adrp	x8, _mmVCE_VCPU_CACHE_OFFSET1@GOTPAGE
Lloh74:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_OFFSET1@GOTPAGEOFF]
Lloh75:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	and	w8, w24, #0xf0ffffff
	orr	w1, w8, #0x1000000
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x23]
Lloh76:
	adrp	x8, _mmVCE_VCPU_CACHE_SIZE1@GOTPAGE
Lloh77:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_SIZE1@GOTPAGEOFF]
Lloh78:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x1, x21
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
Lloh79:
	adrp	x8, _VCE_V4_0_DATA_SIZE@GOTPAGE
Lloh80:
	ldr	x8, [x8, _VCE_V4_0_DATA_SIZE@GOTPAGEOFF]
	add	w24, w24, w21
Lloh81:
	ldr	w21, [x8]
	ldr	w0, [x23]
Lloh82:
	adrp	x8, _mmVCE_VCPU_CACHE_OFFSET2@GOTPAGE
Lloh83:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_OFFSET2@GOTPAGEOFF]
Lloh84:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	and	w8, w24, #0xf0ffffff
	orr	w1, w8, #0x2000000
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x23]
Lloh85:
	adrp	x8, _mmVCE_VCPU_CACHE_SIZE2@GOTPAGE
Lloh86:
	ldr	x8, [x8, _mmVCE_VCPU_CACHE_SIZE2@GOTPAGEOFF]
Lloh87:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x1, x21
	bl	_MMSCH_V1_0_INSERT_DIRECT_WT
	ldr	w0, [x23]
Lloh88:
	adrp	x8, _mmVCE_LMI_CTRL2@GOTPAGE
Lloh89:
	ldr	x8, [x8, _mmVCE_LMI_CTRL2@GOTPAGEOFF]
Lloh90:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #-257
	mov	w2, #0
	bl	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	ldr	w0, [x23]
Lloh91:
	adrp	x8, _mmVCE_SYS_INT_EN@GOTPAGE
Lloh92:
	ldr	x8, [x8, _mmVCE_SYS_INT_EN@GOTPAGEOFF]
Lloh93:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh94:
	adrp	x8, _VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK@GOTPAGE
Lloh95:
	ldr	x8, [x8, _VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK@GOTPAGEOFF]
Lloh96:
	ldr	w1, [x8]
	mov	x2, x1
	bl	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	ldr	w0, [x23]
Lloh97:
	adrp	x21, _mmVCE_STATUS@GOTPAGE
Lloh98:
	ldr	x21, [x21, _mmVCE_STATUS@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh99:
	adrp	x24, _VCE_STATUS__JOB_BUSY_MASK@GOTPAGE
Lloh100:
	ldr	x24, [x24, _VCE_STATUS__JOB_BUSY_MASK@GOTPAGEOFF]
	ldr	w1, [x24]
	mvn	w2, w1
	bl	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	ldr	w0, [x23]
Lloh101:
	adrp	x8, _mmVCE_VCPU_CNTL@GOTPAGE
Lloh102:
	ldr	x8, [x8, _mmVCE_VCPU_CNTL@GOTPAGEOFF]
Lloh103:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh104:
	adrp	x8, _VCE_VCPU_CNTL__CLK_EN_MASK@GOTPAGE
Lloh105:
	ldr	x8, [x8, _VCE_VCPU_CNTL__CLK_EN_MASK@GOTPAGEOFF]
Lloh106:
	ldr	w2, [x8]
	mov	w1, #65534
	movk	w1, #65503, lsl #16
	bl	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	ldr	w0, [x23]
Lloh107:
	adrp	x8, _mmVCE_SOFT_RESET@GOTPAGE
Lloh108:
	ldr	x8, [x8, _mmVCE_SOFT_RESET@GOTPAGEOFF]
Lloh109:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh110:
	adrp	x8, _VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK@GOTPAGE
Lloh111:
	ldr	x8, [x8, _VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh112:
	ldr	w8, [x8]
	mvn	w1, w8
	mov	w2, #0
	bl	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	ldr	w0, [x23]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh113:
	adrp	x8, _VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK@GOTPAGE
Lloh114:
	ldr	x8, [x8, _VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK@GOTPAGEOFF]
Lloh115:
	ldr	w1, [x8]
	mov	x2, x1
	bl	_MMSCH_V1_0_INSERT_DIRECT_POLL
	ldr	w0, [x23]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x24]
	mvn	w1, w8
	mov	w2, #0
	bl	_MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT
	add	x1, sp, #8
	mov	x0, x20
	mov	w2, #8
	bl	_memcpy
	mov	w8, #2
	str	x8, [x22, #8]
LBB0_6:
	mov	x0, x19
	mov	x1, x19
	bl	_vce_v4_0_mmsch_start
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGot	Lloh99, Lloh100
	.loh AdrpLdrGot	Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.cfi_endproc
                                        ; -- End function
	.comm	_MMSCH_COMMAND__DIRECT_REG_WRITE,4,2 ; @MMSCH_COMMAND__DIRECT_REG_WRITE
	.comm	_MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE,4,2 ; @MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE
	.comm	_MMSCH_COMMAND__DIRECT_REG_POLLING,4,2 ; @MMSCH_COMMAND__DIRECT_REG_POLLING
	.comm	_MMSCH_COMMAND__END,4,2         ; @MMSCH_COMMAND__END
	.comm	_MMSCH_VERSION,4,2              ; @MMSCH_VERSION
	.comm	_VCE,4,2                        ; @VCE
	.comm	_mmVCE_RB_BASE_LO,4,2           ; @mmVCE_RB_BASE_LO
	.comm	_mmVCE_RB_BASE_HI,4,2           ; @mmVCE_RB_BASE_HI
	.comm	_mmVCE_RB_SIZE,4,2              ; @mmVCE_RB_SIZE
	.comm	_mmVCE_LMI_CTRL,4,2             ; @mmVCE_LMI_CTRL
	.comm	_mmVCE_LMI_CACHE_CTRL,4,2       ; @mmVCE_LMI_CACHE_CTRL
	.comm	_mmVCE_LMI_SWAP_CNTL,4,2        ; @mmVCE_LMI_SWAP_CNTL
	.comm	_mmVCE_LMI_SWAP_CNTL1,4,2       ; @mmVCE_LMI_SWAP_CNTL1
	.comm	_mmVCE_LMI_VM_CTRL,4,2          ; @mmVCE_LMI_VM_CTRL
	.comm	_AMDGPU_VCE_FIRMWARE_OFFSET,4,2 ; @AMDGPU_VCE_FIRMWARE_OFFSET
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_VCE,8,3        ; @AMDGPU_UCODE_ID_VCE
	.comm	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR0,4,2 ; @mmVCE_LMI_VCPU_CACHE_40BIT_BAR0
	.comm	_mmVCE_LMI_VCPU_CACHE_64BIT_BAR0,4,2 ; @mmVCE_LMI_VCPU_CACHE_64BIT_BAR0
	.comm	_mmVCE_VCPU_CACHE_OFFSET0,4,2   ; @mmVCE_VCPU_CACHE_OFFSET0
	.comm	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR1,4,2 ; @mmVCE_LMI_VCPU_CACHE_40BIT_BAR1
	.comm	_mmVCE_LMI_VCPU_CACHE_64BIT_BAR1,4,2 ; @mmVCE_LMI_VCPU_CACHE_64BIT_BAR1
	.comm	_mmVCE_LMI_VCPU_CACHE_40BIT_BAR2,4,2 ; @mmVCE_LMI_VCPU_CACHE_40BIT_BAR2
	.comm	_mmVCE_LMI_VCPU_CACHE_64BIT_BAR2,4,2 ; @mmVCE_LMI_VCPU_CACHE_64BIT_BAR2
	.comm	_VCE_V4_0_FW_SIZE,4,2           ; @VCE_V4_0_FW_SIZE
	.comm	_mmVCE_VCPU_CACHE_SIZE0,4,2     ; @mmVCE_VCPU_CACHE_SIZE0
	.comm	_VCE_V4_0_STACK_SIZE,4,2        ; @VCE_V4_0_STACK_SIZE
	.comm	_mmVCE_VCPU_CACHE_OFFSET1,4,2   ; @mmVCE_VCPU_CACHE_OFFSET1
	.comm	_mmVCE_VCPU_CACHE_SIZE1,4,2     ; @mmVCE_VCPU_CACHE_SIZE1
	.comm	_VCE_V4_0_DATA_SIZE,4,2         ; @VCE_V4_0_DATA_SIZE
	.comm	_mmVCE_VCPU_CACHE_OFFSET2,4,2   ; @mmVCE_VCPU_CACHE_OFFSET2
	.comm	_mmVCE_VCPU_CACHE_SIZE2,4,2     ; @mmVCE_VCPU_CACHE_SIZE2
	.comm	_mmVCE_LMI_CTRL2,4,2            ; @mmVCE_LMI_CTRL2
	.comm	_mmVCE_SYS_INT_EN,4,2           ; @mmVCE_SYS_INT_EN
	.comm	_VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK,4,2 ; @VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK
	.comm	_mmVCE_STATUS,4,2               ; @mmVCE_STATUS
	.comm	_VCE_STATUS__JOB_BUSY_MASK,4,2  ; @VCE_STATUS__JOB_BUSY_MASK
	.comm	_mmVCE_VCPU_CNTL,4,2            ; @mmVCE_VCPU_CNTL
	.comm	_VCE_VCPU_CNTL__CLK_EN_MASK,4,2 ; @VCE_VCPU_CNTL__CLK_EN_MASK
	.comm	_mmVCE_SOFT_RESET,4,2           ; @mmVCE_SOFT_RESET
	.comm	_VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,4,2 ; @VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
	.comm	_VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK,4,2 ; @VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK
	.no_dead_strip	_vce_v4_0_sriov_start
.subsections_via_symbols
