	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function si_set_pcie_lanes
_si_set_pcie_lanes:                     ## @si_set_pcie_lanes
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rdi)
	je	LBB0_1
## %bb.10:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
LBB0_1:
	cmpl	$16, %esi
	ja	LBB0_7
## %bb.2:
	movq	_LC_LINK_WIDTH_X0@GOTPCREL(%rip), %rax
	movl	%esi, %ecx
	leaq	LJTI0_0(%rip), %rdx
	movslq	(%rdx,%rcx,4), %rcx
	addq	%rdx, %rcx
	jmpq	*%rcx
LBB0_8:
	movq	_LC_LINK_WIDTH_X1@GOTPCREL(%rip), %rax
	jmp	LBB0_9
LBB0_3:
	movq	_LC_LINK_WIDTH_X2@GOTPCREL(%rip), %rax
	jmp	LBB0_9
LBB0_7:
	leaq	L_.str(%rip), %rdi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_DRM_ERROR                      ## TAILCALL
LBB0_4:
	movq	_LC_LINK_WIDTH_X4@GOTPCREL(%rip), %rax
	jmp	LBB0_9
LBB0_5:
	movq	_LC_LINK_WIDTH_X8@GOTPCREL(%rip), %rax
	jmp	LBB0_9
LBB0_6:
	movq	_LC_LINK_WIDTH_X16@GOTPCREL(%rip), %rax
LBB0_9:
	movl	(%rax), %ebx
	movq	_PCIE_LC_LINK_WIDTH_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_RREG32_PCIE_PORT
	movq	_LC_LINK_WIDTH_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	_LC_LINK_WIDTH_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %ebx
	orl	%edx, %ebx
	movq	_LC_RECONFIG_NOW@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_LC_RECONFIG_ARC_MISSING_ESCAPE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	(%r14), %edi
	movl	%ebx, %esi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_WREG32_PCIE_PORT               ## TAILCALL
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_9, LBB0_9-LJTI0_0
.set L0_0_set_8, LBB0_8-LJTI0_0
.set L0_0_set_3, LBB0_3-LJTI0_0
.set L0_0_set_7, LBB0_7-LJTI0_0
.set L0_0_set_4, LBB0_4-LJTI0_0
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_6, LBB0_6-LJTI0_0
LJTI0_0:
	.long	L0_0_set_9
	.long	L0_0_set_8
	.long	L0_0_set_3
	.long	L0_0_set_7
	.long	L0_0_set_4
	.long	L0_0_set_7
	.long	L0_0_set_7
	.long	L0_0_set_7
	.long	L0_0_set_5
	.long	L0_0_set_7
	.long	L0_0_set_7
	.long	L0_0_set_7
	.long	L0_0_set_7
	.long	L0_0_set_7
	.long	L0_0_set_7
	.long	L0_0_set_7
	.long	L0_0_set_6
	.end_data_region
                                        ## -- End function
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_LC_LINK_WIDTH_X0,4,2           ## @LC_LINK_WIDTH_X0
	.comm	_LC_LINK_WIDTH_X1,4,2           ## @LC_LINK_WIDTH_X1
	.comm	_LC_LINK_WIDTH_X2,4,2           ## @LC_LINK_WIDTH_X2
	.comm	_LC_LINK_WIDTH_X4,4,2           ## @LC_LINK_WIDTH_X4
	.comm	_LC_LINK_WIDTH_X8,4,2           ## @LC_LINK_WIDTH_X8
	.comm	_LC_LINK_WIDTH_X16,4,2          ## @LC_LINK_WIDTH_X16
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"invalid pcie lane request: %d\n"

	.comm	_PCIE_LC_LINK_WIDTH_CNTL,4,2    ## @PCIE_LC_LINK_WIDTH_CNTL
	.comm	_LC_LINK_WIDTH_MASK,4,2         ## @LC_LINK_WIDTH_MASK
	.comm	_LC_LINK_WIDTH_SHIFT,4,2        ## @LC_LINK_WIDTH_SHIFT
	.comm	_LC_RECONFIG_NOW,4,2            ## @LC_RECONFIG_NOW
	.comm	_LC_RECONFIG_ARC_MISSING_ESCAPE,4,2 ## @LC_RECONFIG_ARC_MISSING_ESCAPE
	.no_dead_strip	_si_set_pcie_lanes
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function si_set_pcie_lanes
_si_set_pcie_lanes:                     ; @si_set_pcie_lanes
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _AMD_IS_APU@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_IS_APU@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_2:
	cmp	w1, #16
	b.hi	LBB0_6
; %bb.3:
Lloh3:
	adrp	x8, _LC_LINK_WIDTH_X0@GOTPAGE
Lloh4:
	ldr	x8, [x8, _LC_LINK_WIDTH_X0@GOTPAGEOFF]
	mov	w9, w1
Lloh5:
	adrp	x10, lJTI0_0@PAGE
Lloh6:
	add	x10, x10, lJTI0_0@PAGEOFF
	adr	x11, LBB0_4
	ldrb	w12, [x10, x9]
	add	x11, x11, x12, lsl #2
	br	x11
LBB0_4:
Lloh7:
	adrp	x8, _LC_LINK_WIDTH_X1@GOTPAGE
Lloh8:
	ldr	x8, [x8, _LC_LINK_WIDTH_X1@GOTPAGEOFF]
	b	LBB0_10
LBB0_5:
Lloh9:
	adrp	x8, _LC_LINK_WIDTH_X2@GOTPAGE
Lloh10:
	ldr	x8, [x8, _LC_LINK_WIDTH_X2@GOTPAGEOFF]
	b	LBB0_10
LBB0_6:
Lloh11:
	adrp	x0, l_.str@PAGE
Lloh12:
	add	x0, x0, l_.str@PAGEOFF
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_DRM_ERROR
LBB0_7:
Lloh13:
	adrp	x8, _LC_LINK_WIDTH_X4@GOTPAGE
Lloh14:
	ldr	x8, [x8, _LC_LINK_WIDTH_X4@GOTPAGEOFF]
	b	LBB0_10
LBB0_8:
Lloh15:
	adrp	x8, _LC_LINK_WIDTH_X8@GOTPAGE
Lloh16:
	ldr	x8, [x8, _LC_LINK_WIDTH_X8@GOTPAGEOFF]
	b	LBB0_10
LBB0_9:
Lloh17:
	adrp	x8, _LC_LINK_WIDTH_X16@GOTPAGE
Lloh18:
	ldr	x8, [x8, _LC_LINK_WIDTH_X16@GOTPAGEOFF]
LBB0_10:
	ldr	w19, [x8]
Lloh19:
	adrp	x20, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGE
Lloh20:
	ldr	x20, [x20, _PCIE_LC_LINK_WIDTH_CNTL@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_RREG32_PCIE_PORT
Lloh21:
	adrp	x8, _LC_LINK_WIDTH_MASK@GOTPAGE
Lloh22:
	ldr	x8, [x8, _LC_LINK_WIDTH_MASK@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh24:
	adrp	x9, _LC_LINK_WIDTH_SHIFT@GOTPAGE
Lloh25:
	ldr	x9, [x9, _LC_LINK_WIDTH_SHIFT@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	lsl	w9, w19, w9
Lloh27:
	adrp	x10, _LC_RECONFIG_NOW@GOTPAGE
Lloh28:
	ldr	x10, [x10, _LC_RECONFIG_NOW@GOTPAGEOFF]
Lloh29:
	ldr	w10, [x10]
Lloh30:
	adrp	x11, _LC_RECONFIG_ARC_MISSING_ESCAPE@GOTPAGE
Lloh31:
	ldr	x11, [x11, _LC_RECONFIG_ARC_MISSING_ESCAPE@GOTPAGEOFF]
Lloh32:
	ldr	w11, [x11]
	orr	w8, w9, w8
	orr	w8, w8, w10
	orr	w1, w8, w11
	ldr	w0, [x20]
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_WREG32_PCIE_PORT
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpAdd	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh19, Lloh20
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_10-LBB0_4)>>2
	.byte	(LBB0_4-LBB0_4)>>2
	.byte	(LBB0_5-LBB0_4)>>2
	.byte	(LBB0_6-LBB0_4)>>2
	.byte	(LBB0_7-LBB0_4)>>2
	.byte	(LBB0_6-LBB0_4)>>2
	.byte	(LBB0_6-LBB0_4)>>2
	.byte	(LBB0_6-LBB0_4)>>2
	.byte	(LBB0_8-LBB0_4)>>2
	.byte	(LBB0_6-LBB0_4)>>2
	.byte	(LBB0_6-LBB0_4)>>2
	.byte	(LBB0_6-LBB0_4)>>2
	.byte	(LBB0_6-LBB0_4)>>2
	.byte	(LBB0_6-LBB0_4)>>2
	.byte	(LBB0_6-LBB0_4)>>2
	.byte	(LBB0_6-LBB0_4)>>2
	.byte	(LBB0_9-LBB0_4)>>2
                                        ; -- End function
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_LC_LINK_WIDTH_X0,4,2           ; @LC_LINK_WIDTH_X0
	.comm	_LC_LINK_WIDTH_X1,4,2           ; @LC_LINK_WIDTH_X1
	.comm	_LC_LINK_WIDTH_X2,4,2           ; @LC_LINK_WIDTH_X2
	.comm	_LC_LINK_WIDTH_X4,4,2           ; @LC_LINK_WIDTH_X4
	.comm	_LC_LINK_WIDTH_X8,4,2           ; @LC_LINK_WIDTH_X8
	.comm	_LC_LINK_WIDTH_X16,4,2          ; @LC_LINK_WIDTH_X16
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"invalid pcie lane request: %d\n"

	.comm	_PCIE_LC_LINK_WIDTH_CNTL,4,2    ; @PCIE_LC_LINK_WIDTH_CNTL
	.comm	_LC_LINK_WIDTH_MASK,4,2         ; @LC_LINK_WIDTH_MASK
	.comm	_LC_LINK_WIDTH_SHIFT,4,2        ; @LC_LINK_WIDTH_SHIFT
	.comm	_LC_RECONFIG_NOW,4,2            ; @LC_RECONFIG_NOW
	.comm	_LC_RECONFIG_ARC_MISSING_ESCAPE,4,2 ; @LC_RECONFIG_ARC_MISSING_ESCAPE
	.no_dead_strip	_si_set_pcie_lanes
.subsections_via_symbols
