	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function chv_compute_dpll
_chv_compute_dpll:                      ## @chv_compute_dpll
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rsi, %rbx
	movq	_DPLL_SSC_REF_CLK_CHV@GOTPCREL(%rip), %rcx
	movq	_DPLL_REF_CLK_ENABLE_VLV@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	(%rcx), %eax
	movq	_DPLL_VGA_MODE_DIS@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, 4(%rsi)
	movq	(%rdi), %rcx
	movq	_PIPE_A@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	je	LBB0_2
## %bb.1:
	movq	_DPLL_INTEGRATED_CRI_CLK_VLV@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, 4(%rbx)
LBB0_2:
	movq	_INTEL_OUTPUT_DSI@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_intel_crtc_has_type
	testl	%eax, %eax
	jne	LBB0_4
## %bb.3:
	movq	_DPLL_VCO_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, 4(%rbx)
LBB0_4:
	movl	(%rbx), %eax
	decl	%eax
	movq	_DPLL_MD_UDI_MULTIPLIER_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	movl	%eax, 8(%rbx)
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DPLL_SSC_REF_CLK_CHV,4,2       ## @DPLL_SSC_REF_CLK_CHV
	.comm	_DPLL_REF_CLK_ENABLE_VLV,4,2    ## @DPLL_REF_CLK_ENABLE_VLV
	.comm	_DPLL_VGA_MODE_DIS,4,2          ## @DPLL_VGA_MODE_DIS
	.comm	_PIPE_A,8,3                     ## @PIPE_A
	.comm	_DPLL_INTEGRATED_CRI_CLK_VLV,4,2 ## @DPLL_INTEGRATED_CRI_CLK_VLV
	.comm	_INTEL_OUTPUT_DSI,4,2           ## @INTEL_OUTPUT_DSI
	.comm	_DPLL_VCO_ENABLE,4,2            ## @DPLL_VCO_ENABLE
	.comm	_DPLL_MD_UDI_MULTIPLIER_SHIFT,4,2 ## @DPLL_MD_UDI_MULTIPLIER_SHIFT
	.no_dead_strip	_chv_compute_dpll
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function chv_compute_dpll
_chv_compute_dpll:                      ; @chv_compute_dpll
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x1
Lloh0:
	adrp	x8, _DPLL_SSC_REF_CLK_CHV@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DPLL_SSC_REF_CLK_CHV@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _DPLL_REF_CLK_ENABLE_VLV@GOTPAGE
Lloh4:
	ldr	x9, [x9, _DPLL_REF_CLK_ENABLE_VLV@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh6:
	adrp	x9, _DPLL_VGA_MODE_DIS@GOTPAGE
Lloh7:
	ldr	x9, [x9, _DPLL_VGA_MODE_DIS@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x1, #4]
	ldr	x9, [x0]
Lloh9:
	adrp	x10, _PIPE_A@GOTPAGE
Lloh10:
	ldr	x10, [x10, _PIPE_A@GOTPAGEOFF]
Lloh11:
	ldr	x10, [x10]
	cmp	x9, x10
	b.eq	LBB0_2
; %bb.1:
Lloh12:
	adrp	x9, _DPLL_INTEGRATED_CRI_CLK_VLV@GOTPAGE
Lloh13:
	ldr	x9, [x9, _DPLL_INTEGRATED_CRI_CLK_VLV@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	orr	w8, w9, w8
	str	w8, [x19, #4]
LBB0_2:
Lloh15:
	adrp	x8, _INTEL_OUTPUT_DSI@GOTPAGE
Lloh16:
	ldr	x8, [x8, _INTEL_OUTPUT_DSI@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_intel_crtc_has_type
	cbnz	w0, LBB0_4
; %bb.3:
Lloh18:
	adrp	x8, _DPLL_VCO_ENABLE@GOTPAGE
Lloh19:
	ldr	x8, [x8, _DPLL_VCO_ENABLE@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	ldr	w9, [x19, #4]
	orr	w8, w9, w8
	str	w8, [x19, #4]
LBB0_4:
	ldr	w8, [x19]
	sub	w8, w8, #1
Lloh21:
	adrp	x9, _DPLL_MD_UDI_MULTIPLIER_SHIFT@GOTPAGE
Lloh22:
	ldr	x9, [x9, _DPLL_MD_UDI_MULTIPLIER_SHIFT@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	str	w8, [x19, #8]
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.cfi_endproc
                                        ; -- End function
	.comm	_DPLL_SSC_REF_CLK_CHV,4,2       ; @DPLL_SSC_REF_CLK_CHV
	.comm	_DPLL_REF_CLK_ENABLE_VLV,4,2    ; @DPLL_REF_CLK_ENABLE_VLV
	.comm	_DPLL_VGA_MODE_DIS,4,2          ; @DPLL_VGA_MODE_DIS
	.comm	_PIPE_A,8,3                     ; @PIPE_A
	.comm	_DPLL_INTEGRATED_CRI_CLK_VLV,4,2 ; @DPLL_INTEGRATED_CRI_CLK_VLV
	.comm	_INTEL_OUTPUT_DSI,4,2           ; @INTEL_OUTPUT_DSI
	.comm	_DPLL_VCO_ENABLE,4,2            ; @DPLL_VCO_ENABLE
	.comm	_DPLL_MD_UDI_MULTIPLIER_SHIFT,4,2 ; @DPLL_MD_UDI_MULTIPLIER_SHIFT
	.no_dead_strip	_chv_compute_dpll
.subsections_via_symbols
