	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v2_0_start
_vcn_v2_0_start:                        ## @vcn_v2_0_start
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	8(%rdi), %rbx
	cmpq	$0, 24(%rdi)
	je	LBB0_2
## %bb.1:
	movq	%r14, %rdi
	movl	$1, %esi
	callq	_amdgpu_dpm_enable_uvd
LBB0_2:
	movq	_AMD_PG_SUPPORT_VCN_DPG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r14)
	je	LBB0_5
## %bb.3:
	movl	16(%r14), %esi
	movq	%r14, %rdi
	callq	_vcn_v2_0_start_dpg_mode
	testl	%eax, %eax
	je	LBB0_12
LBB0_4:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_5:
	movq	%rbx, -64(%rbp)                 ## 8-byte Spill
	movq	%r14, %rdi
	callq	_vcn_v2_0_disable_static_power_gating
	movq	_UVD@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	movq	_mmUVD_STATUS@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	movl	$0, -44(%rbp)                   ## 4-byte Folded Spill
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_UVD_STATUS__UVD_BUSY@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r12), %edi
	movl	(%r13), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	%r14, %rdi
	callq	_vcn_v2_0_disable_clock_gating
	movl	(%r12), %edi
	movq	_mmUVD_VCPU_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_VCPU_CNTL__CLK_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	callq	_WREG32_P
	movl	(%r12), %edi
	movq	_mmUVD_MASTINT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_MASTINT_EN__VCPU_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	(%r12), %edi
	movq	_mmUVD_LMI_CTRL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_LMI_CTRL__MASK_MC_URGENT_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r12), %edi
	movq	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edx
	movq	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmUVD_MPC_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_UVD_MPC_CNTL__REPLACEMENT_MODE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	_UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %r15d
	movl	$2, %eax
	shll	%cl, %eax
	orl	%edx, %eax
	movq	_VCN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmUVD_MPC_SET_MUXA0@GOTPCREL(%rip), %rax
	movq	_UVD_MPC_SET_MUXA0__VARA_2__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %esi
	shll	%cl, %esi
	movl	(%rax), %edx
	movq	_UVD_MPC_SET_MUXA0__VARA_1__SHIFT@GOTPCREL(%rip), %rax
	movq	_UVD_MPC_SET_MUXA0__VARA_3__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$3, %r8d
	shll	%cl, %r8d
	movb	(%rax), %al
	btsl	%eax, %esi
	movq	_UVD_MPC_SET_MUXA0__VARA_4__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$4, %eax
	shll	%cl, %eax
	movq	%r14, -56(%rbp)                 ## 8-byte Spill
	movl	$3, %r14d
	movl	$4, %ebx
	orl	%r8d, %eax
	orl	%esi, %eax
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_UVD_MPC_SET_MUXB0__VARB_2__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %eax
	shll	%cl, %eax
	movq	_UVD_MPC_SET_MUXB0__VARB_3__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r14d
	movq	_mmUVD_MPC_SET_MUXB0@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_UVD_MPC_SET_MUXB0__VARB_4__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movq	_UVD_MPC_SET_MUXB0__VARB_1__SHIFT@GOTPCREL(%rip), %rsi
	shll	%cl, %ebx
	movb	(%rsi), %cl
	btsl	%ecx, %eax
	orl	%r14d, %ebx
	orl	%eax, %ebx
	xorl	%esi, %esi
	movl	%ebx, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmUVD_MPC_SET_MUX@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_UVD_MPC_SET_MUX__SET_1__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	movq	_UVD_MPC_SET_MUX__SET_2__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r15d
	btsl	%eax, %r15d
	xorl	%esi, %esi
	movl	%r15d, %ecx
	callq	_WREG32_SOC15
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_vcn_v2_0_mc_resume
	movl	(%r12), %edi
	movq	_mmUVD_SOFT_RESET@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	(%r12), %edi
	movq	_mmUVD_LMI_CTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movq	_VCN@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movl	(%r14), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPCREL(%rip), %rdx
	movq	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rdx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movl	(%rbx), %edi
	movl	(%r14), %edx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmUVD_LMI_SWAP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
LBB0_6:                                 ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_7 Depth 2
	movl	$100, %ebx
	.p2align	4, 0x90
LBB0_7:                                 ##   Parent Loop BB0_6 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movl	(%r12), %edi
	movl	(%r13), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	testb	$2, %al
	jne	LBB0_11
## %bb.8:                               ##   in Loop: Header=BB0_7 Depth=2
	movl	$10, %edi
	callq	_mdelay
	decl	%ebx
	jne	LBB0_7
## %bb.9:                               ##   in Loop: Header=BB0_6 Depth=1
	leaq	L_.str(%rip), %rdi
	callq	_DRM_ERROR
	movl	(%r12), %edi
	movl	(%r14), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r15), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	callq	_WREG32_P
	movl	$10, %edi
	callq	_mdelay
	movl	(%r12), %edi
	movl	(%r14), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r15), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	$10, %edi
	callq	_mdelay
	movl	-44(%rbp), %eax                 ## 4-byte Reload
	incl	%eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	cmpl	$10, %eax
	jne	LBB0_6
## %bb.10:
	leaq	L_.str.1(%rip), %rdi
	callq	_DRM_ERROR
	movl	$-1, %eax
	jmp	LBB0_4
LBB0_11:
	movl	(%r12), %edi
	movq	_mmUVD_MASTINT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_MASTINT_EN__VCPU_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	callq	_WREG32_P
	movl	(%r12), %edi
	movl	(%r13), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_STATUS__VCPU_REPORT__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %edx
	shll	%cl, %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	(%r12), %edi
	movq	_mmUVD_LMI_RBC_RB_VMID@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movq	-64(%rbp), %r14                 ## 8-byte Reload
	movl	8(%r14), %edi
	callq	_order_base_2
	movq	_UVD_RBC_RB_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_RB_BUFSZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%edi, %edi
	movl	%eax, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_BLKSZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_NO_FETCH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_NO_UPDATE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_RPTR_WR_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r12), %edi
	movq	_mmUVD_RBC_RB_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %ebx
	movq	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	12(%r14), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r15d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %ebx
	movq	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	12(%r14), %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r15d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmUVD_RBC_RB_RPTR@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movl	(%rbx), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	%eax, 16(%r14)
	movl	(%r12), %ebx
	movq	_mmUVD_RBC_RB_WPTR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r15d
	movl	%eax, %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r15d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movq	-56(%rbp), %r14                 ## 8-byte Reload
	movq	8(%r14), %rax
	movq	(%rax), %rbx
	movl	(%r12), %r13d
	movq	_mmUVD_RB_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	8(%rbx), %edi
	callq	_lower_32_bits
	movl	%r13d, %edi
	xorl	%esi, %esi
	movl	%r15d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %r13d
	movq	_mmUVD_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	8(%rbx), %edi
	callq	_lower_32_bits
	movl	%r13d, %edi
	xorl	%esi, %esi
	movl	%r15d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmUVD_RB_BASE_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	4(%rbx), %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r12), %r13d
	movq	_mmUVD_RB_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	4(%rbx), %edi
	callq	_upper_32_bits
	movl	%r13d, %edi
	xorl	%esi, %esi
	movl	%r15d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmUVD_RB_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%rbx), %eax
	leal	3(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$2, %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movq	8(%r14), %rax
	movq	(%rax), %rbx
	movl	(%r12), %r13d
	movq	_mmUVD_RB_RPTR2@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	20(%rbx), %edi
	callq	_lower_32_bits
	movl	%r13d, %edi
	xorl	%esi, %esi
	movl	%r15d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %r13d
	movq	_mmUVD_RB_WPTR2@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	20(%rbx), %edi
	callq	_lower_32_bits
	movl	%r13d, %edi
	xorl	%esi, %esi
	movl	%r15d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmUVD_RB_BASE_LO2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	16(%rbx), %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r12), %r13d
	movq	_mmUVD_RB_BASE_HI2@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	16(%rbx), %edi
	callq	_upper_32_bits
	movl	%r13d, %edi
	xorl	%esi, %esi
	movl	%r15d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r12), %edi
	movq	_mmUVD_RB_SIZE2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	12(%rbx), %eax
	leal	3(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$2, %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
LBB0_12:
	movq	%r14, %rdi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_jpeg_v2_0_start                ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_PG_SUPPORT_VCN_DPG,4,2     ## @AMD_PG_SUPPORT_VCN_DPG
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_STATUS,4,2               ## @mmUVD_STATUS
	.comm	_UVD_STATUS__UVD_BUSY,4,2       ## @UVD_STATUS__UVD_BUSY
	.comm	_mmUVD_VCPU_CNTL,4,2            ## @mmUVD_VCPU_CNTL
	.comm	_UVD_VCPU_CNTL__CLK_EN_MASK,4,2 ## @UVD_VCPU_CNTL__CLK_EN_MASK
	.comm	_mmUVD_MASTINT_EN,4,2           ## @mmUVD_MASTINT_EN
	.comm	_UVD_MASTINT_EN__VCPU_EN_MASK,4,2 ## @UVD_MASTINT_EN__VCPU_EN_MASK
	.comm	_mmUVD_LMI_CTRL,4,2             ## @mmUVD_LMI_CTRL
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK,4,2 ## @UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK
	.comm	_UVD_LMI_CTRL__MASK_MC_URGENT_MASK,4,2 ## @UVD_LMI_CTRL__MASK_MC_URGENT_MASK
	.comm	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK,4,2 ## @UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK,4,2 ## @UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
	.comm	_mmUVD_MPC_CNTL,4,2             ## @mmUVD_MPC_CNTL
	.comm	_UVD_MPC_CNTL__REPLACEMENT_MODE_MASK,4,2 ## @UVD_MPC_CNTL__REPLACEMENT_MODE_MASK
	.comm	_UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT,4,2 ## @UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT
	.comm	_VCN,4,2                        ## @VCN
	.comm	_mmUVD_MPC_SET_MUXA0,4,2        ## @mmUVD_MPC_SET_MUXA0
	.comm	_UVD_MPC_SET_MUXA0__VARA_1__SHIFT,4,2 ## @UVD_MPC_SET_MUXA0__VARA_1__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_2__SHIFT,4,2 ## @UVD_MPC_SET_MUXA0__VARA_2__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_3__SHIFT,4,2 ## @UVD_MPC_SET_MUXA0__VARA_3__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_4__SHIFT,4,2 ## @UVD_MPC_SET_MUXA0__VARA_4__SHIFT
	.comm	_mmUVD_MPC_SET_MUXB0,4,2        ## @mmUVD_MPC_SET_MUXB0
	.comm	_UVD_MPC_SET_MUXB0__VARB_1__SHIFT,4,2 ## @UVD_MPC_SET_MUXB0__VARB_1__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_2__SHIFT,4,2 ## @UVD_MPC_SET_MUXB0__VARB_2__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_3__SHIFT,4,2 ## @UVD_MPC_SET_MUXB0__VARB_3__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_4__SHIFT,4,2 ## @UVD_MPC_SET_MUXB0__VARB_4__SHIFT
	.comm	_mmUVD_MPC_SET_MUX,4,2          ## @mmUVD_MPC_SET_MUX
	.comm	_UVD_MPC_SET_MUX__SET_0__SHIFT,4,2 ## @UVD_MPC_SET_MUX__SET_0__SHIFT
	.comm	_UVD_MPC_SET_MUX__SET_1__SHIFT,4,2 ## @UVD_MPC_SET_MUX__SET_1__SHIFT
	.comm	_UVD_MPC_SET_MUX__SET_2__SHIFT,4,2 ## @UVD_MPC_SET_MUX__SET_2__SHIFT
	.comm	_mmUVD_SOFT_RESET,4,2           ## @mmUVD_SOFT_RESET
	.comm	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
	.comm	_mmUVD_LMI_CTRL2,4,2            ## @mmUVD_LMI_CTRL2
	.comm	_UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,4,2 ## @UVD_LMI_CTRL2__STALL_ARB_UMC_MASK
	.comm	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
	.comm	_mmUVD_LMI_SWAP_CNTL,4,2        ## @mmUVD_LMI_SWAP_CNTL
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"VCN decode not responding, trying to reset the VCPU!!!\n"

L_.str.1:                               ## @.str.1
	.asciz	"VCN decode not responding, giving up!!!\n"

	.comm	_UVD_STATUS__VCPU_REPORT__SHIFT,4,2 ## @UVD_STATUS__VCPU_REPORT__SHIFT
	.comm	_mmUVD_LMI_RBC_RB_VMID,4,2      ## @mmUVD_LMI_RBC_RB_VMID
	.comm	_UVD_RBC_RB_CNTL,4,2            ## @UVD_RBC_RB_CNTL
	.comm	_RB_BUFSZ,4,2                   ## @RB_BUFSZ
	.comm	_RB_BLKSZ,4,2                   ## @RB_BLKSZ
	.comm	_RB_NO_FETCH,4,2                ## @RB_NO_FETCH
	.comm	_RB_NO_UPDATE,4,2               ## @RB_NO_UPDATE
	.comm	_RB_RPTR_WR_EN,4,2              ## @RB_RPTR_WR_EN
	.comm	_mmUVD_RBC_RB_CNTL,4,2          ## @mmUVD_RBC_RB_CNTL
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
	.comm	_mmUVD_RBC_RB_RPTR,4,2          ## @mmUVD_RBC_RB_RPTR
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ## @mmUVD_RBC_RB_WPTR
	.comm	_mmUVD_RB_RPTR,4,2              ## @mmUVD_RB_RPTR
	.comm	_mmUVD_RB_WPTR,4,2              ## @mmUVD_RB_WPTR
	.comm	_mmUVD_RB_BASE_LO,4,2           ## @mmUVD_RB_BASE_LO
	.comm	_mmUVD_RB_BASE_HI,4,2           ## @mmUVD_RB_BASE_HI
	.comm	_mmUVD_RB_SIZE,4,2              ## @mmUVD_RB_SIZE
	.comm	_mmUVD_RB_RPTR2,4,2             ## @mmUVD_RB_RPTR2
	.comm	_mmUVD_RB_WPTR2,4,2             ## @mmUVD_RB_WPTR2
	.comm	_mmUVD_RB_BASE_LO2,4,2          ## @mmUVD_RB_BASE_LO2
	.comm	_mmUVD_RB_BASE_HI2,4,2          ## @mmUVD_RB_BASE_HI2
	.comm	_mmUVD_RB_SIZE2,4,2             ## @mmUVD_RB_SIZE2
	.no_dead_strip	_vcn_v2_0_start
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v2_0_start
_vcn_v2_0_start:                        ; @vcn_v2_0_start
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	x23, [x0, #8]
	ldr	x8, [x0, #24]
	cbz	x8, LBB0_2
; %bb.1:
	mov	x0, x19
	mov	w1, #1
	bl	_amdgpu_dpm_enable_uvd
LBB0_2:
	ldr	w8, [x19]
Lloh0:
	adrp	x9, _AMD_PG_SUPPORT_VCN_DPG@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_PG_SUPPORT_VCN_DPG@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_5
; %bb.3:
	ldr	w1, [x19, #16]
	mov	x0, x19
	bl	_vcn_v2_0_start_dpg_mode
	cbz	w0, LBB0_12
LBB0_4:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
LBB0_5:
	mov	x0, x19
	bl	_vcn_v2_0_disable_static_power_gating
Lloh3:
	adrp	x22, _UVD@GOTPAGE
Lloh4:
	ldr	x22, [x22, _UVD@GOTPAGEOFF]
	ldr	w0, [x22]
Lloh5:
	adrp	x21, _mmUVD_STATUS@GOTPAGE
Lloh6:
	ldr	x21, [x21, _mmUVD_STATUS@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh7:
	adrp	x8, _UVD_STATUS__UVD_BUSY@GOTPAGE
Lloh8:
	ldr	x8, [x8, _UVD_STATUS__UVD_BUSY@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	orr	w3, w8, w0
	ldr	w0, [x22]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_WREG32_SOC15
	mov	x0, x19
	bl	_vcn_v2_0_disable_clock_gating
	ldr	w0, [x22]
Lloh10:
	adrp	x8, _mmUVD_VCPU_CNTL@GOTPAGE
Lloh11:
	ldr	x8, [x8, _mmUVD_VCPU_CNTL@GOTPAGEOFF]
Lloh12:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh13:
	adrp	x8, _UVD_VCPU_CNTL__CLK_EN_MASK@GOTPAGE
Lloh14:
	ldr	x8, [x8, _UVD_VCPU_CNTL__CLK_EN_MASK@GOTPAGEOFF]
Lloh15:
	ldr	w1, [x8]
	mvn	w2, w1
	bl	_WREG32_P
	ldr	w0, [x22]
Lloh16:
	adrp	x8, _mmUVD_MASTINT_EN@GOTPAGE
Lloh17:
	ldr	x8, [x8, _mmUVD_MASTINT_EN@GOTPAGEOFF]
Lloh18:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh19:
	adrp	x25, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGE
Lloh20:
	ldr	x25, [x25, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGEOFF]
	ldr	w8, [x25]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w0, [x22]
Lloh21:
	adrp	x20, _mmUVD_LMI_CTRL@GOTPAGE
Lloh22:
	ldr	x20, [x20, _mmUVD_LMI_CTRL@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_RREG32_SOC15
	ldr	w8, [x22]
	ldr	w2, [x20]
Lloh23:
	adrp	x9, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPAGE
Lloh24:
	ldr	x9, [x9, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w9, [x9]
	orr	w9, w9, w0
Lloh26:
	adrp	x10, _UVD_LMI_CTRL__MASK_MC_URGENT_MASK@GOTPAGE
Lloh27:
	ldr	x10, [x10, _UVD_LMI_CTRL__MASK_MC_URGENT_MASK@GOTPAGEOFF]
Lloh28:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh29:
	adrp	x10, _UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPAGE
Lloh30:
	ldr	x10, [x10, _UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPAGEOFF]
Lloh31:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh32:
	adrp	x10, _UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPAGE
Lloh33:
	ldr	x10, [x10, _UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPAGEOFF]
Lloh34:
	ldr	w10, [x10]
	orr	w3, w9, w10
	mov	x0, x8
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh35:
	adrp	x24, _mmUVD_MPC_CNTL@GOTPAGE
Lloh36:
	ldr	x24, [x24, _mmUVD_MPC_CNTL@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh37:
	adrp	x8, _UVD_MPC_CNTL__REPLACEMENT_MODE_MASK@GOTPAGE
Lloh38:
	ldr	x8, [x8, _UVD_MPC_CNTL__REPLACEMENT_MODE_MASK@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh40:
	adrp	x9, _UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT@GOTPAGE
Lloh41:
	ldr	x9, [x9, _UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT@GOTPAGEOFF]
Lloh42:
	ldr	w9, [x9]
	mov	w26, #2
	lsl	w9, w26, w9
	orr	w3, w9, w8
Lloh43:
	adrp	x20, _VCN@GOTPAGE
Lloh44:
	ldr	x20, [x20, _VCN@GOTPAGEOFF]
	ldr	w0, [x20]
	ldr	w2, [x24]
	mov	w1, #0
	bl	_WREG32_SOC15
Lloh45:
	adrp	x8, _mmUVD_MPC_SET_MUXA0@GOTPAGE
Lloh46:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXA0@GOTPAGEOFF]
	ldr	w0, [x22]
Lloh47:
	ldr	w2, [x8]
Lloh48:
	adrp	x8, _UVD_MPC_SET_MUXA0__VARA_1__SHIFT@GOTPAGE
Lloh49:
	ldr	x8, [x8, _UVD_MPC_SET_MUXA0__VARA_1__SHIFT@GOTPAGEOFF]
Lloh50:
	ldr	w8, [x8]
	mov	w27, #1
	lsl	w8, w27, w8
Lloh51:
	adrp	x9, _UVD_MPC_SET_MUXA0__VARA_2__SHIFT@GOTPAGE
Lloh52:
	ldr	x9, [x9, _UVD_MPC_SET_MUXA0__VARA_2__SHIFT@GOTPAGEOFF]
Lloh53:
	ldr	w9, [x9]
	lsl	w9, w26, w9
	orr	w8, w9, w8
Lloh54:
	adrp	x9, _UVD_MPC_SET_MUXA0__VARA_3__SHIFT@GOTPAGE
Lloh55:
	ldr	x9, [x9, _UVD_MPC_SET_MUXA0__VARA_3__SHIFT@GOTPAGEOFF]
Lloh56:
	ldr	w9, [x9]
	mov	w24, #3
	lsl	w9, w24, w9
	orr	w8, w8, w9
Lloh57:
	adrp	x9, _UVD_MPC_SET_MUXA0__VARA_4__SHIFT@GOTPAGE
Lloh58:
	ldr	x9, [x9, _UVD_MPC_SET_MUXA0__VARA_4__SHIFT@GOTPAGEOFF]
Lloh59:
	ldr	w9, [x9]
	mov	w28, #4
	lsl	w9, w28, w9
	orr	w3, w8, w9
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh60:
	adrp	x8, _mmUVD_MPC_SET_MUXB0@GOTPAGE
Lloh61:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXB0@GOTPAGEOFF]
Lloh62:
	adrp	x9, _UVD_MPC_SET_MUXB0__VARB_1__SHIFT@GOTPAGE
Lloh63:
	ldr	x9, [x9, _UVD_MPC_SET_MUXB0__VARB_1__SHIFT@GOTPAGEOFF]
Lloh64:
	ldr	w2, [x8]
Lloh65:
	ldr	w8, [x9]
	lsl	w8, w27, w8
Lloh66:
	adrp	x9, _UVD_MPC_SET_MUXB0__VARB_2__SHIFT@GOTPAGE
Lloh67:
	ldr	x9, [x9, _UVD_MPC_SET_MUXB0__VARB_2__SHIFT@GOTPAGEOFF]
Lloh68:
	ldr	w9, [x9]
	lsl	w9, w26, w9
	orr	w8, w9, w8
Lloh69:
	adrp	x9, _UVD_MPC_SET_MUXB0__VARB_3__SHIFT@GOTPAGE
Lloh70:
	ldr	x9, [x9, _UVD_MPC_SET_MUXB0__VARB_3__SHIFT@GOTPAGEOFF]
Lloh71:
	ldr	w9, [x9]
	lsl	w9, w24, w9
	orr	w8, w8, w9
Lloh72:
	adrp	x9, _UVD_MPC_SET_MUXB0__VARB_4__SHIFT@GOTPAGE
Lloh73:
	ldr	x9, [x9, _UVD_MPC_SET_MUXB0__VARB_4__SHIFT@GOTPAGEOFF]
Lloh74:
	ldr	w9, [x9]
	lsl	w9, w28, w9
	orr	w3, w8, w9
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh75:
	adrp	x8, _mmUVD_MPC_SET_MUX@GOTPAGE
Lloh76:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUX@GOTPAGEOFF]
Lloh77:
	ldr	w2, [x8]
Lloh78:
	adrp	x8, _UVD_MPC_SET_MUX__SET_1__SHIFT@GOTPAGE
Lloh79:
	ldr	x8, [x8, _UVD_MPC_SET_MUX__SET_1__SHIFT@GOTPAGEOFF]
Lloh80:
	ldr	w8, [x8]
	lsl	w8, w27, w8
Lloh81:
	adrp	x9, _UVD_MPC_SET_MUX__SET_2__SHIFT@GOTPAGE
Lloh82:
	ldr	x9, [x9, _UVD_MPC_SET_MUX__SET_2__SHIFT@GOTPAGEOFF]
Lloh83:
	ldr	w9, [x9]
	lsl	w9, w26, w9
	orr	w3, w9, w8
	mov	w1, #0
	bl	_WREG32_SOC15
	mov	x0, x19
	bl	_vcn_v2_0_mc_resume
	ldr	w0, [x22]
Lloh84:
	adrp	x26, _mmUVD_SOFT_RESET@GOTPAGE
Lloh85:
	ldr	x26, [x26, _mmUVD_SOFT_RESET@GOTPAGEOFF]
	ldr	w2, [x26]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh86:
	adrp	x27, _UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPAGE
Lloh87:
	ldr	x27, [x27, _UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPAGEOFF]
	ldr	w8, [x27]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w0, [x22]
Lloh88:
	adrp	x8, _mmUVD_LMI_CTRL2@GOTPAGE
Lloh89:
	ldr	x8, [x8, _mmUVD_LMI_CTRL2@GOTPAGEOFF]
Lloh90:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh91:
	adrp	x8, _UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPAGE
Lloh92:
	ldr	x8, [x8, _UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPAGEOFF]
Lloh93:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w0, [x20]
	ldr	w2, [x26]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh94:
	adrp	x8, _UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPAGE
Lloh95:
	ldr	x8, [x8, _UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh96:
	adrp	x9, _UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPAGE
Lloh97:
	ldr	x9, [x9, _UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh98:
	ldr	w8, [x8]
Lloh99:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w3, w0, w8
	ldr	w0, [x20]
	ldr	w2, [x26]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh100:
	adrp	x8, _mmUVD_LMI_SWAP_CNTL@GOTPAGE
Lloh101:
	ldr	x8, [x8, _mmUVD_LMI_SWAP_CNTL@GOTPAGEOFF]
Lloh102:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	mov	w28, #0
Lloh103:
	adrp	x20, l_.str@PAGE
Lloh104:
	add	x20, x20, l_.str@PAGEOFF
LBB0_6:                                 ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
	mov	w24, #100
LBB0_7:                                 ;   Parent Loop BB0_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ldr	w0, [x22]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_RREG32_SOC15
	tbnz	w0, #1, LBB0_11
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=2
	mov	w0, #10
	bl	_mdelay
	subs	w24, w24, #1
	b.ne	LBB0_7
; %bb.9:                                ;   in Loop: Header=BB0_6 Depth=1
	mov	x0, x20
	bl	_DRM_ERROR
	ldr	w0, [x22]
	ldr	w2, [x26]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w1, [x27]
	mvn	w2, w1
	bl	_WREG32_P
	mov	w0, #10
	bl	_mdelay
	ldr	w0, [x22]
	ldr	w2, [x26]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x27]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	mov	w0, #10
	bl	_mdelay
	add	w28, w28, #1
	cmp	w28, #10
	b.ne	LBB0_6
; %bb.10:
Lloh105:
	adrp	x0, l_.str.1@PAGE
Lloh106:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_ERROR
	mov	w0, #-1
	b	LBB0_4
LBB0_11:
	ldr	w0, [x22]
Lloh107:
	adrp	x8, _mmUVD_MASTINT_EN@GOTPAGE
Lloh108:
	ldr	x8, [x8, _mmUVD_MASTINT_EN@GOTPAGEOFF]
Lloh109:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w1, [x25]
	mvn	w2, w1
	bl	_WREG32_P
	ldr	w0, [x22]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh110:
	adrp	x8, _UVD_STATUS__VCPU_REPORT__SHIFT@GOTPAGE
Lloh111:
	ldr	x8, [x8, _UVD_STATUS__VCPU_REPORT__SHIFT@GOTPAGEOFF]
Lloh112:
	ldr	w8, [x8]
	mov	w9, #2
	lsl	w8, w9, w8
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w0, [x22]
Lloh113:
	adrp	x8, _mmUVD_LMI_RBC_RB_VMID@GOTPAGE
Lloh114:
	ldr	x8, [x8, _mmUVD_LMI_RBC_RB_VMID@GOTPAGEOFF]
Lloh115:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x23, #8]
	bl	_order_base_2
	mov	x3, x0
Lloh116:
	adrp	x20, _UVD_RBC_RB_CNTL@GOTPAGE
Lloh117:
	ldr	x20, [x20, _UVD_RBC_RB_CNTL@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh118:
	adrp	x8, _RB_BUFSZ@GOTPAGE
Lloh119:
	ldr	x8, [x8, _RB_BUFSZ@GOTPAGEOFF]
Lloh120:
	ldr	w2, [x8]
	mov	w0, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x20]
Lloh121:
	adrp	x8, _RB_BLKSZ@GOTPAGE
Lloh122:
	ldr	x8, [x8, _RB_BLKSZ@GOTPAGEOFF]
Lloh123:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x20]
Lloh124:
	adrp	x8, _RB_NO_FETCH@GOTPAGE
Lloh125:
	ldr	x8, [x8, _RB_NO_FETCH@GOTPAGEOFF]
Lloh126:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x20]
Lloh127:
	adrp	x8, _RB_NO_UPDATE@GOTPAGE
Lloh128:
	ldr	x8, [x8, _RB_NO_UPDATE@GOTPAGEOFF]
Lloh129:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x20]
Lloh130:
	adrp	x8, _RB_RPTR_WR_EN@GOTPAGE
Lloh131:
	ldr	x8, [x8, _RB_RPTR_WR_EN@GOTPAGEOFF]
Lloh132:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x22]
Lloh133:
	adrp	x8, _mmUVD_RBC_RB_CNTL@GOTPAGE
Lloh134:
	ldr	x8, [x8, _mmUVD_RBC_RB_CNTL@GOTPAGEOFF]
Lloh135:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh136:
	adrp	x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPAGE
Lloh137:
	ldr	x8, [x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh138:
	ldr	w21, [x8]
	ldr	w0, [x23, #12]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh139:
	adrp	x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPAGE
Lloh140:
	ldr	x8, [x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh141:
	ldr	w21, [x8]
	ldr	w0, [x23, #12]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh142:
	adrp	x20, _mmUVD_RBC_RB_RPTR@GOTPAGE
Lloh143:
	ldr	x20, [x20, _mmUVD_RBC_RB_RPTR@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	w1, #0
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x22]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_RREG32_SOC15
	str	w0, [x23, #16]
	ldr	w20, [x22]
Lloh144:
	adrp	x8, _mmUVD_RBC_RB_WPTR@GOTPAGE
Lloh145:
	ldr	x8, [x8, _mmUVD_RBC_RB_WPTR@GOTPAGEOFF]
Lloh146:
	ldr	w21, [x8]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	x8, [x19, #8]
	ldr	x23, [x8]
	ldr	w20, [x22]
Lloh147:
	adrp	x8, _mmUVD_RB_RPTR@GOTPAGE
Lloh148:
	ldr	x8, [x8, _mmUVD_RB_RPTR@GOTPAGEOFF]
Lloh149:
	ldr	w21, [x8]
	ldr	w0, [x23, #8]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh150:
	adrp	x8, _mmUVD_RB_WPTR@GOTPAGE
Lloh151:
	ldr	x8, [x8, _mmUVD_RB_WPTR@GOTPAGEOFF]
Lloh152:
	ldr	w21, [x8]
	ldr	w0, [x23, #8]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh153:
	adrp	x8, _mmUVD_RB_BASE_LO@GOTPAGE
Lloh154:
	ldr	x8, [x8, _mmUVD_RB_BASE_LO@GOTPAGEOFF]
Lloh155:
	ldr	w2, [x8]
	ldr	w3, [x23, #4]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh156:
	adrp	x8, _mmUVD_RB_BASE_HI@GOTPAGE
Lloh157:
	ldr	x8, [x8, _mmUVD_RB_BASE_HI@GOTPAGEOFF]
Lloh158:
	ldr	w21, [x8]
	ldr	w0, [x23, #4]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh159:
	adrp	x8, _mmUVD_RB_SIZE@GOTPAGE
Lloh160:
	ldr	x8, [x8, _mmUVD_RB_SIZE@GOTPAGEOFF]
Lloh161:
	ldr	w2, [x8]
	ldr	w8, [x23]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w3, w8, #2
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	x8, [x19, #8]
	ldr	x23, [x8]
	ldr	w20, [x22]
Lloh162:
	adrp	x8, _mmUVD_RB_RPTR2@GOTPAGE
Lloh163:
	ldr	x8, [x8, _mmUVD_RB_RPTR2@GOTPAGEOFF]
Lloh164:
	ldr	w21, [x8]
	ldr	w0, [x23, #20]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh165:
	adrp	x8, _mmUVD_RB_WPTR2@GOTPAGE
Lloh166:
	ldr	x8, [x8, _mmUVD_RB_WPTR2@GOTPAGEOFF]
Lloh167:
	ldr	w21, [x8]
	ldr	w0, [x23, #20]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh168:
	adrp	x8, _mmUVD_RB_BASE_LO2@GOTPAGE
Lloh169:
	ldr	x8, [x8, _mmUVD_RB_BASE_LO2@GOTPAGEOFF]
Lloh170:
	ldr	w2, [x8]
	ldr	w3, [x23, #16]
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w20, [x22]
Lloh171:
	adrp	x8, _mmUVD_RB_BASE_HI2@GOTPAGE
Lloh172:
	ldr	x8, [x8, _mmUVD_RB_BASE_HI2@GOTPAGEOFF]
Lloh173:
	ldr	w21, [x8]
	ldr	w0, [x23, #16]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	ldr	w0, [x22]
Lloh174:
	adrp	x8, _mmUVD_RB_SIZE2@GOTPAGE
Lloh175:
	ldr	x8, [x8, _mmUVD_RB_SIZE2@GOTPAGEOFF]
Lloh176:
	ldr	w2, [x8]
	ldr	w8, [x23, #12]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w3, w8, #2
	mov	w1, #0
	bl	_WREG32_SOC15
LBB0_12:
	mov	x0, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_jpeg_v2_0_start
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh98
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGot	Lloh86, Lloh87
	.loh AdrpLdrGot	Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh64
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpAdd	Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh174, Lloh175, Lloh176
	.loh AdrpLdrGotLdr	Lloh171, Lloh172, Lloh173
	.loh AdrpLdrGotLdr	Lloh168, Lloh169, Lloh170
	.loh AdrpLdrGotLdr	Lloh165, Lloh166, Lloh167
	.loh AdrpLdrGotLdr	Lloh162, Lloh163, Lloh164
	.loh AdrpLdrGotLdr	Lloh159, Lloh160, Lloh161
	.loh AdrpLdrGotLdr	Lloh156, Lloh157, Lloh158
	.loh AdrpLdrGotLdr	Lloh153, Lloh154, Lloh155
	.loh AdrpLdrGotLdr	Lloh150, Lloh151, Lloh152
	.loh AdrpLdrGotLdr	Lloh147, Lloh148, Lloh149
	.loh AdrpLdrGotLdr	Lloh144, Lloh145, Lloh146
	.loh AdrpLdrGot	Lloh142, Lloh143
	.loh AdrpLdrGotLdr	Lloh139, Lloh140, Lloh141
	.loh AdrpLdrGotLdr	Lloh136, Lloh137, Lloh138
	.loh AdrpLdrGotLdr	Lloh133, Lloh134, Lloh135
	.loh AdrpLdrGotLdr	Lloh130, Lloh131, Lloh132
	.loh AdrpLdrGotLdr	Lloh127, Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGot	Lloh116, Lloh117
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_PG_SUPPORT_VCN_DPG,4,2     ; @AMD_PG_SUPPORT_VCN_DPG
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_STATUS,4,2               ; @mmUVD_STATUS
	.comm	_UVD_STATUS__UVD_BUSY,4,2       ; @UVD_STATUS__UVD_BUSY
	.comm	_mmUVD_VCPU_CNTL,4,2            ; @mmUVD_VCPU_CNTL
	.comm	_UVD_VCPU_CNTL__CLK_EN_MASK,4,2 ; @UVD_VCPU_CNTL__CLK_EN_MASK
	.comm	_mmUVD_MASTINT_EN,4,2           ; @mmUVD_MASTINT_EN
	.comm	_UVD_MASTINT_EN__VCPU_EN_MASK,4,2 ; @UVD_MASTINT_EN__VCPU_EN_MASK
	.comm	_mmUVD_LMI_CTRL,4,2             ; @mmUVD_LMI_CTRL
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK,4,2 ; @UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK
	.comm	_UVD_LMI_CTRL__MASK_MC_URGENT_MASK,4,2 ; @UVD_LMI_CTRL__MASK_MC_URGENT_MASK
	.comm	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK,4,2 ; @UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK,4,2 ; @UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
	.comm	_mmUVD_MPC_CNTL,4,2             ; @mmUVD_MPC_CNTL
	.comm	_UVD_MPC_CNTL__REPLACEMENT_MODE_MASK,4,2 ; @UVD_MPC_CNTL__REPLACEMENT_MODE_MASK
	.comm	_UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT,4,2 ; @UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT
	.comm	_VCN,4,2                        ; @VCN
	.comm	_mmUVD_MPC_SET_MUXA0,4,2        ; @mmUVD_MPC_SET_MUXA0
	.comm	_UVD_MPC_SET_MUXA0__VARA_1__SHIFT,4,2 ; @UVD_MPC_SET_MUXA0__VARA_1__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_2__SHIFT,4,2 ; @UVD_MPC_SET_MUXA0__VARA_2__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_3__SHIFT,4,2 ; @UVD_MPC_SET_MUXA0__VARA_3__SHIFT
	.comm	_UVD_MPC_SET_MUXA0__VARA_4__SHIFT,4,2 ; @UVD_MPC_SET_MUXA0__VARA_4__SHIFT
	.comm	_mmUVD_MPC_SET_MUXB0,4,2        ; @mmUVD_MPC_SET_MUXB0
	.comm	_UVD_MPC_SET_MUXB0__VARB_1__SHIFT,4,2 ; @UVD_MPC_SET_MUXB0__VARB_1__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_2__SHIFT,4,2 ; @UVD_MPC_SET_MUXB0__VARB_2__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_3__SHIFT,4,2 ; @UVD_MPC_SET_MUXB0__VARB_3__SHIFT
	.comm	_UVD_MPC_SET_MUXB0__VARB_4__SHIFT,4,2 ; @UVD_MPC_SET_MUXB0__VARB_4__SHIFT
	.comm	_mmUVD_MPC_SET_MUX,4,2          ; @mmUVD_MPC_SET_MUX
	.comm	_UVD_MPC_SET_MUX__SET_0__SHIFT,4,2 ; @UVD_MPC_SET_MUX__SET_0__SHIFT
	.comm	_UVD_MPC_SET_MUX__SET_1__SHIFT,4,2 ; @UVD_MPC_SET_MUX__SET_1__SHIFT
	.comm	_UVD_MPC_SET_MUX__SET_2__SHIFT,4,2 ; @UVD_MPC_SET_MUX__SET_2__SHIFT
	.comm	_mmUVD_SOFT_RESET,4,2           ; @mmUVD_SOFT_RESET
	.comm	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
	.comm	_mmUVD_LMI_CTRL2,4,2            ; @mmUVD_LMI_CTRL2
	.comm	_UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,4,2 ; @UVD_LMI_CTRL2__STALL_ARB_UMC_MASK
	.comm	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
	.comm	_mmUVD_LMI_SWAP_CNTL,4,2        ; @mmUVD_LMI_SWAP_CNTL
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"VCN decode not responding, trying to reset the VCPU!!!\n"

l_.str.1:                               ; @.str.1
	.asciz	"VCN decode not responding, giving up!!!\n"

	.comm	_UVD_STATUS__VCPU_REPORT__SHIFT,4,2 ; @UVD_STATUS__VCPU_REPORT__SHIFT
	.comm	_mmUVD_LMI_RBC_RB_VMID,4,2      ; @mmUVD_LMI_RBC_RB_VMID
	.comm	_UVD_RBC_RB_CNTL,4,2            ; @UVD_RBC_RB_CNTL
	.comm	_RB_BUFSZ,4,2                   ; @RB_BUFSZ
	.comm	_RB_BLKSZ,4,2                   ; @RB_BLKSZ
	.comm	_RB_NO_FETCH,4,2                ; @RB_NO_FETCH
	.comm	_RB_NO_UPDATE,4,2               ; @RB_NO_UPDATE
	.comm	_RB_RPTR_WR_EN,4,2              ; @RB_RPTR_WR_EN
	.comm	_mmUVD_RBC_RB_CNTL,4,2          ; @mmUVD_RBC_RB_CNTL
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
	.comm	_mmUVD_RBC_RB_RPTR,4,2          ; @mmUVD_RBC_RB_RPTR
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ; @mmUVD_RBC_RB_WPTR
	.comm	_mmUVD_RB_RPTR,4,2              ; @mmUVD_RB_RPTR
	.comm	_mmUVD_RB_WPTR,4,2              ; @mmUVD_RB_WPTR
	.comm	_mmUVD_RB_BASE_LO,4,2           ; @mmUVD_RB_BASE_LO
	.comm	_mmUVD_RB_BASE_HI,4,2           ; @mmUVD_RB_BASE_HI
	.comm	_mmUVD_RB_SIZE,4,2              ; @mmUVD_RB_SIZE
	.comm	_mmUVD_RB_RPTR2,4,2             ; @mmUVD_RB_RPTR2
	.comm	_mmUVD_RB_WPTR2,4,2             ; @mmUVD_RB_WPTR2
	.comm	_mmUVD_RB_BASE_LO2,4,2          ; @mmUVD_RB_BASE_LO2
	.comm	_mmUVD_RB_BASE_HI2,4,2          ; @mmUVD_RB_BASE_HI2
	.comm	_mmUVD_RB_SIZE2,4,2             ; @mmUVD_RB_SIZE2
	.no_dead_strip	_vcn_v2_0_start
.subsections_via_symbols
