	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function etm4_enable_hw
_etm4_enable_hw:                        ## @etm4_enable_hw
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	40(%rdi), %rdi
	movq	48(%r12), %rbx
	callq	_CS_UNLOCK
	movq	%r12, %rdi
	callq	_etm4_os_unlock
	movq	40(%r12), %rdi
	callq	_coresight_claim_device_unlocked
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	LBB0_27
## %bb.1:
	movq	_TRCPRGCTLR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	xorl	%edi, %edi
	callq	_writel_relaxed
	movq	40(%r12), %rdi
	movq	_TRCSTATR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_TRCSTATR_IDLE_BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	$1, %ecx
	callq	_coresight_timeout
	testq	%rax, %rax
	je	LBB0_3
## %bb.2:
	leaq	L_.str(%rip), %rsi
	movq	%rbx, %rdi
	callq	_dev_err
LBB0_3:
	movq	%rbx, -48(%rbp)                 ## 8-byte Spill
	movl	56(%r12), %edi
	movq	_TRCPROCSELR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	movl	60(%r12), %edi
	movq	_TRCCONFIGR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	movq	_TRCAUXCTLR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	xorl	%edi, %edi
	callq	_writel_relaxed
	movl	64(%r12), %edi
	movq	_TRCEVENTCTL0R@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	movl	68(%r12), %edi
	movq	_TRCEVENTCTL1R@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	movl	72(%r12), %edi
	movq	_TRCSTALLCTLR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	movl	76(%r12), %edi
	movq	_TRCTSCTLR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	movl	80(%r12), %edi
	movq	_TRCSYNCPR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	movl	84(%r12), %edi
	movq	_TRCCCCTLR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	movl	88(%r12), %edi
	movq	_TRCBBCTLR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	movl	(%r12), %edi
	movq	_TRCTRACEIDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	movl	92(%r12), %edi
	movq	_TRCVICTLR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	movl	96(%r12), %edi
	movq	_TRCVIIECTLR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	movl	100(%r12), %edi
	movq	_TRCVISSCTLR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	movl	104(%r12), %edi
	movq	_TRCVIPCSSCTLR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	cmpl	$2, 4(%r12)
	jl	LBB0_6
## %bb.4:
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	movq	40(%r12), %r13
	movq	112(%r12), %rax
	movl	(%rax,%rbx,4), %r14d
	movl	%ebx, %edi
	callq	_TRCSEQEVRn
	addq	%rax, %r13
	movl	%r14d, %edi
	movq	%r13, %rsi
	callq	_writel_relaxed
	incq	%rbx
	movslq	4(%r12), %rax
	decq	%rax
	cmpq	%rax, %rbx
	jl	LBB0_5
LBB0_6:
	movl	120(%r12), %edi
	movq	_TRCSEQRSTEVR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	movl	124(%r12), %edi
	movq	_TRCSEQSTR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	movl	128(%r12), %edi
	movq	_TRCEXTINSELR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	cmpl	$0, 8(%r12)
	jle	LBB0_9
## %bb.7:
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_8:                                 ## =>This Inner Loop Header: Depth=1
	movq	40(%r12), %r14
	movq	136(%r12), %rax
	movl	(%rax,%rbx,4), %r13d
	movl	%ebx, %edi
	callq	_TRCCNTRLDVRn
	addq	%rax, %r14
	movl	%r13d, %edi
	movq	%r14, %rsi
	callq	_writel_relaxed
	movq	40(%r12), %r14
	movq	144(%r12), %rax
	movl	(%rax,%rbx,4), %r13d
	movl	%ebx, %edi
	callq	_TRCCNTCTLRn
	addq	%rax, %r14
	movl	%r13d, %edi
	movq	%r14, %rsi
	callq	_writel_relaxed
	movq	40(%r12), %r14
	movq	152(%r12), %rax
	movl	(%rax,%rbx,4), %r13d
	movl	%ebx, %edi
	callq	_TRCCNTVRn
	addq	%rax, %r14
	movl	%r13d, %edi
	movq	%r14, %rsi
	callq	_writel_relaxed
	incq	%rbx
	movslq	8(%r12), %rax
	cmpq	%rax, %rbx
	jl	LBB0_8
LBB0_9:
	cmpl	$2, 12(%r12)
	jl	LBB0_12
## %bb.10:
	movl	$2, %ebx
	.p2align	4, 0x90
LBB0_11:                                ## =>This Inner Loop Header: Depth=1
	movq	40(%r12), %r14
	movq	160(%r12), %rax
	movl	(%rax,%rbx,4), %r13d
	movl	%ebx, %edi
	callq	_TRCRSCTLRn
	addq	%rax, %r14
	movl	%r13d, %edi
	movq	%r14, %rsi
	callq	_writel_relaxed
	incq	%rbx
	movslq	12(%r12), %rax
	addq	%rax, %rax
	cmpq	%rax, %rbx
	jl	LBB0_11
LBB0_12:
	cmpl	$0, 16(%r12)
	jle	LBB0_15
## %bb.13:
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_14:                                ## =>This Inner Loop Header: Depth=1
	movq	40(%r12), %r14
	movq	168(%r12), %rax
	movl	(%rax,%rbx,4), %r13d
	movl	%ebx, %edi
	callq	_TRCSSCCRn
	addq	%rax, %r14
	movl	%r13d, %edi
	movq	%r14, %rsi
	callq	_writel_relaxed
	movq	40(%r12), %r14
	movq	176(%r12), %rax
	movl	(%rax,%rbx,4), %r13d
	movl	%ebx, %edi
	callq	_TRCSSCSRn
	addq	%rax, %r14
	movl	%r13d, %edi
	movq	%r14, %rsi
	callq	_writel_relaxed
	movq	40(%r12), %r14
	movq	184(%r12), %rax
	movl	(%rax,%rbx,4), %r13d
	movl	%ebx, %edi
	callq	_TRCSSPCICRn
	addq	%rax, %r14
	movl	%r13d, %edi
	movq	%r14, %rsi
	callq	_writel_relaxed
	incq	%rbx
	movslq	16(%r12), %rax
	cmpq	%rax, %rbx
	jl	LBB0_14
LBB0_15:
	cmpl	$0, 20(%r12)
	jle	LBB0_18
## %bb.16:
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_17:                                ## =>This Inner Loop Header: Depth=1
	movq	40(%r12), %r14
	movq	232(%r12), %rax
	movl	(%rax,%rbx,4), %r13d
	movl	%ebx, %edi
	callq	_TRCACVRn
	addq	%rax, %r14
	movl	%r13d, %edi
	movq	%r14, %rsi
	callq	_writeq_relaxed
	movq	40(%r12), %r14
	movq	224(%r12), %rax
	movl	(%rax,%rbx,4), %r13d
	movl	%ebx, %edi
	callq	_TRCACATRn
	addq	%rax, %r14
	movl	%r13d, %edi
	movq	%r14, %rsi
	callq	_writeq_relaxed
	incq	%rbx
	movslq	20(%r12), %rax
	cmpq	%rax, %rbx
	jl	LBB0_17
LBB0_18:
	cmpl	$0, 24(%r12)
	jle	LBB0_21
## %bb.19:
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_20:                                ## =>This Inner Loop Header: Depth=1
	movq	40(%r12), %r14
	movq	216(%r12), %rax
	movl	(%rax,%rbx,4), %r13d
	movl	%ebx, %edi
	callq	_TRCCIDCVRn
	addq	%rax, %r14
	movl	%r13d, %edi
	movq	%r14, %rsi
	callq	_writeq_relaxed
	incq	%rbx
	movslq	24(%r12), %rax
	cmpq	%rax, %rbx
	jl	LBB0_20
LBB0_21:
	movl	192(%r12), %edi
	movq	_TRCCIDCCTLR0@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	movl	196(%r12), %edi
	movq	_TRCCIDCCTLR1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	cmpl	$0, 28(%r12)
	jle	LBB0_24
## %bb.22:
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_23:                                ## =>This Inner Loop Header: Depth=1
	movq	40(%r12), %r14
	movq	208(%r12), %rax
	movl	(%rax,%rbx,4), %r13d
	movl	%ebx, %edi
	callq	_TRCVMIDCVRn
	addq	%rax, %r14
	movl	%r13d, %edi
	movq	%r14, %rsi
	callq	_writeq_relaxed
	incq	%rbx
	movslq	28(%r12), %rax
	cmpq	%rax, %rbx
	jl	LBB0_23
LBB0_24:
	movl	200(%r12), %edi
	movq	_TRCVMIDCCTLR0@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	movl	204(%r12), %edi
	movq	_TRCVMIDCCTLR1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	callq	_writel_relaxed
	movq	_TRCPDCR@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	addq	40(%r12), %rdi
	callq	_readl_relaxed
	movq	_TRCPDCR_PU@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	(%rbx), %rsi
	addq	40(%r12), %rsi
	movl	%eax, %edi
	callq	_writel_relaxed
	movq	_TRCPRGCTLR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%r12), %rsi
	movl	$1, %edi
	callq	_writel_relaxed
	movq	40(%r12), %rdi
	movq	_TRCSTATR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_TRCSTATR_IDLE_BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
	callq	_coresight_timeout
	testq	%rax, %rax
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	je	LBB0_26
## %bb.25:
	leaq	L_.str(%rip), %rsi
	movq	%rbx, %rdi
	callq	_dev_err
LBB0_26:
	movq	_sy@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_dsb
	xorl	%eax, %eax
	callq	_isb
LBB0_27:
	movq	40(%r12), %rdi
	callq	_CS_LOCK
	movl	32(%r12), %edx
	leaq	L_.str.1(%rip), %rsi
	movq	%rbx, %rdi
	movl	%r15d, %ecx
	callq	_dev_dbg
	movl	%r15d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_TRCPRGCTLR,8,3                 ## @TRCPRGCTLR
	.comm	_TRCSTATR,4,2                   ## @TRCSTATR
	.comm	_TRCSTATR_IDLE_BIT,4,2          ## @TRCSTATR_IDLE_BIT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"timeout while waiting for Idle Trace Status\n"

	.comm	_TRCPROCSELR,8,3                ## @TRCPROCSELR
	.comm	_TRCCONFIGR,8,3                 ## @TRCCONFIGR
	.comm	_TRCAUXCTLR,8,3                 ## @TRCAUXCTLR
	.comm	_TRCEVENTCTL0R,8,3              ## @TRCEVENTCTL0R
	.comm	_TRCEVENTCTL1R,8,3              ## @TRCEVENTCTL1R
	.comm	_TRCSTALLCTLR,8,3               ## @TRCSTALLCTLR
	.comm	_TRCTSCTLR,8,3                  ## @TRCTSCTLR
	.comm	_TRCSYNCPR,8,3                  ## @TRCSYNCPR
	.comm	_TRCCCCTLR,8,3                  ## @TRCCCCTLR
	.comm	_TRCBBCTLR,8,3                  ## @TRCBBCTLR
	.comm	_TRCTRACEIDR,8,3                ## @TRCTRACEIDR
	.comm	_TRCVICTLR,8,3                  ## @TRCVICTLR
	.comm	_TRCVIIECTLR,8,3                ## @TRCVIIECTLR
	.comm	_TRCVISSCTLR,8,3                ## @TRCVISSCTLR
	.comm	_TRCVIPCSSCTLR,8,3              ## @TRCVIPCSSCTLR
	.comm	_TRCSEQRSTEVR,8,3               ## @TRCSEQRSTEVR
	.comm	_TRCSEQSTR,8,3                  ## @TRCSEQSTR
	.comm	_TRCEXTINSELR,8,3               ## @TRCEXTINSELR
	.comm	_TRCCIDCCTLR0,8,3               ## @TRCCIDCCTLR0
	.comm	_TRCCIDCCTLR1,8,3               ## @TRCCIDCCTLR1
	.comm	_TRCVMIDCCTLR0,8,3              ## @TRCVMIDCCTLR0
	.comm	_TRCVMIDCCTLR1,8,3              ## @TRCVMIDCCTLR1
	.comm	_TRCPDCR,8,3                    ## @TRCPDCR
	.comm	_TRCPDCR_PU,4,2                 ## @TRCPDCR_PU
	.comm	_sy,4,2                         ## @sy
L_.str.1:                               ## @.str.1
	.asciz	"cpu: %d enable smp call done: %d\n"

	.no_dead_strip	_etm4_enable_hw
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function etm4_enable_hw
_etm4_enable_hw:                        ; @etm4_enable_hw
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x20, x0
	ldp	x0, x19, [x0, #40]
	bl	_CS_UNLOCK
	mov	x0, x20
	bl	_etm4_os_unlock
	ldr	x0, [x20, #40]
	bl	_coresight_claim_device_unlocked
	mov	x21, x0
	cbnz	w0, LBB0_27
; %bb.1:
	ldr	x8, [x20, #40]
Lloh0:
	adrp	x24, _TRCPRGCTLR@GOTPAGE
Lloh1:
	ldr	x24, [x24, _TRCPRGCTLR@GOTPAGEOFF]
	ldr	x9, [x24]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	x0, [x20, #40]
Lloh2:
	adrp	x25, _TRCSTATR@GOTPAGE
Lloh3:
	ldr	x25, [x25, _TRCSTATR@GOTPAGEOFF]
	ldr	w1, [x25]
Lloh4:
	adrp	x26, _TRCSTATR_IDLE_BIT@GOTPAGE
Lloh5:
	ldr	x26, [x26, _TRCSTATR_IDLE_BIT@GOTPAGEOFF]
	ldr	w2, [x26]
	mov	w3, #1
	bl	_coresight_timeout
	cbz	x0, LBB0_3
; %bb.2:
Lloh6:
	adrp	x1, l_.str@PAGE
Lloh7:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x19
	bl	_dev_err
LBB0_3:
	ldr	w0, [x20, #56]
	ldr	x8, [x20, #40]
Lloh8:
	adrp	x9, _TRCPROCSELR@GOTPAGE
Lloh9:
	ldr	x9, [x9, _TRCPROCSELR@GOTPAGEOFF]
Lloh10:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w0, [x20, #60]
	ldr	x8, [x20, #40]
Lloh11:
	adrp	x9, _TRCCONFIGR@GOTPAGE
Lloh12:
	ldr	x9, [x9, _TRCCONFIGR@GOTPAGEOFF]
Lloh13:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	x8, [x20, #40]
Lloh14:
	adrp	x9, _TRCAUXCTLR@GOTPAGE
Lloh15:
	ldr	x9, [x9, _TRCAUXCTLR@GOTPAGEOFF]
Lloh16:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #0
	bl	_writel_relaxed
	ldr	w0, [x20, #64]
	ldr	x8, [x20, #40]
Lloh17:
	adrp	x9, _TRCEVENTCTL0R@GOTPAGE
Lloh18:
	ldr	x9, [x9, _TRCEVENTCTL0R@GOTPAGEOFF]
Lloh19:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w0, [x20, #68]
	ldr	x8, [x20, #40]
Lloh20:
	adrp	x9, _TRCEVENTCTL1R@GOTPAGE
Lloh21:
	ldr	x9, [x9, _TRCEVENTCTL1R@GOTPAGEOFF]
Lloh22:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w0, [x20, #72]
	ldr	x8, [x20, #40]
Lloh23:
	adrp	x9, _TRCSTALLCTLR@GOTPAGE
Lloh24:
	ldr	x9, [x9, _TRCSTALLCTLR@GOTPAGEOFF]
Lloh25:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w0, [x20, #76]
	ldr	x8, [x20, #40]
Lloh26:
	adrp	x9, _TRCTSCTLR@GOTPAGE
Lloh27:
	ldr	x9, [x9, _TRCTSCTLR@GOTPAGEOFF]
Lloh28:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w0, [x20, #80]
	ldr	x8, [x20, #40]
Lloh29:
	adrp	x9, _TRCSYNCPR@GOTPAGE
Lloh30:
	ldr	x9, [x9, _TRCSYNCPR@GOTPAGEOFF]
Lloh31:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w0, [x20, #84]
	ldr	x8, [x20, #40]
Lloh32:
	adrp	x9, _TRCCCCTLR@GOTPAGE
Lloh33:
	ldr	x9, [x9, _TRCCCCTLR@GOTPAGEOFF]
Lloh34:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w0, [x20, #88]
	ldr	x8, [x20, #40]
Lloh35:
	adrp	x9, _TRCBBCTLR@GOTPAGE
Lloh36:
	ldr	x9, [x9, _TRCBBCTLR@GOTPAGEOFF]
Lloh37:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w0, [x20]
	ldr	x8, [x20, #40]
Lloh38:
	adrp	x9, _TRCTRACEIDR@GOTPAGE
Lloh39:
	ldr	x9, [x9, _TRCTRACEIDR@GOTPAGEOFF]
Lloh40:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w0, [x20, #92]
	ldr	x8, [x20, #40]
Lloh41:
	adrp	x9, _TRCVICTLR@GOTPAGE
Lloh42:
	ldr	x9, [x9, _TRCVICTLR@GOTPAGEOFF]
Lloh43:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w0, [x20, #96]
	ldr	x8, [x20, #40]
Lloh44:
	adrp	x9, _TRCVIIECTLR@GOTPAGE
Lloh45:
	ldr	x9, [x9, _TRCVIIECTLR@GOTPAGEOFF]
Lloh46:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w0, [x20, #100]
	ldr	x8, [x20, #40]
Lloh47:
	adrp	x9, _TRCVISSCTLR@GOTPAGE
Lloh48:
	ldr	x9, [x9, _TRCVISSCTLR@GOTPAGEOFF]
Lloh49:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w0, [x20, #104]
	ldr	x8, [x20, #40]
Lloh50:
	adrp	x9, _TRCVIPCSSCTLR@GOTPAGE
Lloh51:
	ldr	x9, [x9, _TRCVIPCSSCTLR@GOTPAGEOFF]
Lloh52:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w8, [x20, #4]
	cmp	w8, #1
	b.le	LBB0_6
; %bb.4:
	mov	x22, #0
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x20, #112]
	ldr	w23, [x8, x22, lsl #2]
	ldr	x27, [x20, #40]
	mov	x0, x22
	bl	_TRCSEQEVRn
	add	x1, x0, x27
	mov	x0, x23
	bl	_writel_relaxed
	add	x22, x22, #1
	ldrsw	x8, [x20, #4]
	sub	x8, x8, #1
	cmp	x22, x8
	b.lt	LBB0_5
LBB0_6:
	ldr	w0, [x20, #120]
	ldr	x8, [x20, #40]
Lloh53:
	adrp	x9, _TRCSEQRSTEVR@GOTPAGE
Lloh54:
	ldr	x9, [x9, _TRCSEQRSTEVR@GOTPAGEOFF]
Lloh55:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w0, [x20, #124]
	ldr	x8, [x20, #40]
Lloh56:
	adrp	x9, _TRCSEQSTR@GOTPAGE
Lloh57:
	ldr	x9, [x9, _TRCSEQSTR@GOTPAGEOFF]
Lloh58:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w0, [x20, #128]
	ldr	x8, [x20, #40]
Lloh59:
	adrp	x9, _TRCEXTINSELR@GOTPAGE
Lloh60:
	ldr	x9, [x9, _TRCEXTINSELR@GOTPAGEOFF]
Lloh61:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w8, [x20, #8]
	cmp	w8, #1
	b.lt	LBB0_9
; %bb.7:
	mov	x22, #0
LBB0_8:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x20, #136]
	lsl	x27, x22, #2
	ldr	w23, [x8, x27]
	ldr	x28, [x20, #40]
	mov	x0, x22
	bl	_TRCCNTRLDVRn
	add	x1, x0, x28
	mov	x0, x23
	bl	_writel_relaxed
	ldr	x8, [x20, #144]
	ldr	w23, [x8, x27]
	ldr	x28, [x20, #40]
	mov	x0, x22
	bl	_TRCCNTCTLRn
	add	x1, x0, x28
	mov	x0, x23
	bl	_writel_relaxed
	ldr	x8, [x20, #152]
	ldr	w23, [x8, x27]
	ldr	x27, [x20, #40]
	mov	x0, x22
	bl	_TRCCNTVRn
	add	x1, x0, x27
	mov	x0, x23
	bl	_writel_relaxed
	add	x22, x22, #1
	ldrsw	x8, [x20, #8]
	cmp	x22, x8
	b.lt	LBB0_8
LBB0_9:
	ldr	w8, [x20, #12]
	cmp	w8, #1
	b.le	LBB0_12
; %bb.10:
	mov	w22, #2
LBB0_11:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x20, #160]
	ldr	w23, [x8, x22, lsl #2]
	ldr	x27, [x20, #40]
	mov	x0, x22
	bl	_TRCRSCTLRn
	add	x1, x0, x27
	mov	x0, x23
	bl	_writel_relaxed
	add	x22, x22, #1
	ldrsw	x8, [x20, #12]
	cmp	x22, x8, lsl #1
	b.lt	LBB0_11
LBB0_12:
	ldr	w8, [x20, #16]
	cmp	w8, #1
	b.lt	LBB0_15
; %bb.13:
	mov	x22, #0
LBB0_14:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x20, #168]
	lsl	x27, x22, #2
	ldr	w23, [x8, x27]
	ldr	x28, [x20, #40]
	mov	x0, x22
	bl	_TRCSSCCRn
	add	x1, x0, x28
	mov	x0, x23
	bl	_writel_relaxed
	ldr	x8, [x20, #176]
	ldr	w23, [x8, x27]
	ldr	x28, [x20, #40]
	mov	x0, x22
	bl	_TRCSSCSRn
	add	x1, x0, x28
	mov	x0, x23
	bl	_writel_relaxed
	ldr	x8, [x20, #184]
	ldr	w23, [x8, x27]
	ldr	x27, [x20, #40]
	mov	x0, x22
	bl	_TRCSSPCICRn
	add	x1, x0, x27
	mov	x0, x23
	bl	_writel_relaxed
	add	x22, x22, #1
	ldrsw	x8, [x20, #16]
	cmp	x22, x8
	b.lt	LBB0_14
LBB0_15:
	ldr	w8, [x20, #20]
	cmp	w8, #1
	b.lt	LBB0_18
; %bb.16:
	mov	x22, #0
LBB0_17:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x20, #232]
	lsl	x27, x22, #2
	ldr	w23, [x8, x27]
	ldr	x28, [x20, #40]
	mov	x0, x22
	bl	_TRCACVRn
	add	x1, x0, x28
	mov	x0, x23
	bl	_writeq_relaxed
	ldr	x8, [x20, #224]
	ldr	w23, [x8, x27]
	ldr	x27, [x20, #40]
	mov	x0, x22
	bl	_TRCACATRn
	add	x1, x0, x27
	mov	x0, x23
	bl	_writeq_relaxed
	add	x22, x22, #1
	ldrsw	x8, [x20, #20]
	cmp	x22, x8
	b.lt	LBB0_17
LBB0_18:
	ldr	w8, [x20, #24]
	cmp	w8, #1
	b.lt	LBB0_21
; %bb.19:
	mov	x22, #0
LBB0_20:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x20, #216]
	ldr	w23, [x8, x22, lsl #2]
	ldr	x27, [x20, #40]
	mov	x0, x22
	bl	_TRCCIDCVRn
	add	x1, x0, x27
	mov	x0, x23
	bl	_writeq_relaxed
	add	x22, x22, #1
	ldrsw	x8, [x20, #24]
	cmp	x22, x8
	b.lt	LBB0_20
LBB0_21:
	ldr	w0, [x20, #192]
	ldr	x8, [x20, #40]
Lloh62:
	adrp	x9, _TRCCIDCCTLR0@GOTPAGE
Lloh63:
	ldr	x9, [x9, _TRCCIDCCTLR0@GOTPAGEOFF]
Lloh64:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w0, [x20, #196]
	ldr	x8, [x20, #40]
Lloh65:
	adrp	x9, _TRCCIDCCTLR1@GOTPAGE
Lloh66:
	ldr	x9, [x9, _TRCCIDCCTLR1@GOTPAGEOFF]
Lloh67:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w8, [x20, #28]
	cmp	w8, #1
	b.lt	LBB0_24
; %bb.22:
	mov	x22, #0
LBB0_23:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x20, #208]
	ldr	w23, [x8, x22, lsl #2]
	ldr	x27, [x20, #40]
	mov	x0, x22
	bl	_TRCVMIDCVRn
	add	x1, x0, x27
	mov	x0, x23
	bl	_writeq_relaxed
	add	x22, x22, #1
	ldrsw	x8, [x20, #28]
	cmp	x22, x8
	b.lt	LBB0_23
LBB0_24:
	ldr	w0, [x20, #200]
	ldr	x8, [x20, #40]
Lloh68:
	adrp	x9, _TRCVMIDCCTLR0@GOTPAGE
Lloh69:
	ldr	x9, [x9, _TRCVMIDCCTLR0@GOTPAGEOFF]
Lloh70:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w0, [x20, #204]
	ldr	x8, [x20, #40]
Lloh71:
	adrp	x9, _TRCVMIDCCTLR1@GOTPAGE
Lloh72:
	ldr	x9, [x9, _TRCVMIDCCTLR1@GOTPAGEOFF]
Lloh73:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	x8, [x20, #40]
Lloh74:
	adrp	x22, _TRCPDCR@GOTPAGE
Lloh75:
	ldr	x22, [x22, _TRCPDCR@GOTPAGEOFF]
	ldr	x9, [x22]
	add	x0, x9, x8
	bl	_readl_relaxed
Lloh76:
	adrp	x8, _TRCPDCR_PU@GOTPAGE
Lloh77:
	ldr	x8, [x8, _TRCPDCR_PU@GOTPAGEOFF]
Lloh78:
	ldr	w8, [x8]
	orr	w0, w8, w0
	ldr	x8, [x20, #40]
	ldr	x9, [x22]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	x8, [x20, #40]
	ldr	x9, [x24]
	add	x1, x9, x8
	mov	w0, #1
	bl	_writel_relaxed
	ldr	x0, [x20, #40]
	ldr	w1, [x25]
	ldr	w2, [x26]
	mov	w3, #0
	bl	_coresight_timeout
	cbz	x0, LBB0_26
; %bb.25:
Lloh79:
	adrp	x1, l_.str@PAGE
Lloh80:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x19
	bl	_dev_err
LBB0_26:
Lloh81:
	adrp	x8, _sy@GOTPAGE
Lloh82:
	ldr	x8, [x8, _sy@GOTPAGEOFF]
Lloh83:
	ldr	w0, [x8]
	bl	_dsb
	bl	_isb
LBB0_27:
	ldr	x0, [x20, #40]
	bl	_CS_LOCK
	ldr	w2, [x20, #32]
Lloh84:
	adrp	x1, l_.str.1@PAGE
Lloh85:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x19
	mov	x3, x21
	bl	_dev_dbg
	mov	x0, x21
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGot	Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpAdd	Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpAdd	Lloh84, Lloh85
	.cfi_endproc
                                        ; -- End function
	.comm	_TRCPRGCTLR,8,3                 ; @TRCPRGCTLR
	.comm	_TRCSTATR,4,2                   ; @TRCSTATR
	.comm	_TRCSTATR_IDLE_BIT,4,2          ; @TRCSTATR_IDLE_BIT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"timeout while waiting for Idle Trace Status\n"

	.comm	_TRCPROCSELR,8,3                ; @TRCPROCSELR
	.comm	_TRCCONFIGR,8,3                 ; @TRCCONFIGR
	.comm	_TRCAUXCTLR,8,3                 ; @TRCAUXCTLR
	.comm	_TRCEVENTCTL0R,8,3              ; @TRCEVENTCTL0R
	.comm	_TRCEVENTCTL1R,8,3              ; @TRCEVENTCTL1R
	.comm	_TRCSTALLCTLR,8,3               ; @TRCSTALLCTLR
	.comm	_TRCTSCTLR,8,3                  ; @TRCTSCTLR
	.comm	_TRCSYNCPR,8,3                  ; @TRCSYNCPR
	.comm	_TRCCCCTLR,8,3                  ; @TRCCCCTLR
	.comm	_TRCBBCTLR,8,3                  ; @TRCBBCTLR
	.comm	_TRCTRACEIDR,8,3                ; @TRCTRACEIDR
	.comm	_TRCVICTLR,8,3                  ; @TRCVICTLR
	.comm	_TRCVIIECTLR,8,3                ; @TRCVIIECTLR
	.comm	_TRCVISSCTLR,8,3                ; @TRCVISSCTLR
	.comm	_TRCVIPCSSCTLR,8,3              ; @TRCVIPCSSCTLR
	.comm	_TRCSEQRSTEVR,8,3               ; @TRCSEQRSTEVR
	.comm	_TRCSEQSTR,8,3                  ; @TRCSEQSTR
	.comm	_TRCEXTINSELR,8,3               ; @TRCEXTINSELR
	.comm	_TRCCIDCCTLR0,8,3               ; @TRCCIDCCTLR0
	.comm	_TRCCIDCCTLR1,8,3               ; @TRCCIDCCTLR1
	.comm	_TRCVMIDCCTLR0,8,3              ; @TRCVMIDCCTLR0
	.comm	_TRCVMIDCCTLR1,8,3              ; @TRCVMIDCCTLR1
	.comm	_TRCPDCR,8,3                    ; @TRCPDCR
	.comm	_TRCPDCR_PU,4,2                 ; @TRCPDCR_PU
	.comm	_sy,4,2                         ; @sy
l_.str.1:                               ; @.str.1
	.asciz	"cpu: %d enable smp call done: %d\n"

	.no_dead_strip	_etm4_enable_hw
.subsections_via_symbols
