	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vega10_apply_state_adjust_rules
_vega10_apply_state_adjust_rules:       ## @vega10_apply_state_adjust_rules
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %rbx
	movq	%rdi, %r13
	movq	56(%rdi), %r12
	leaq	8(%rsi), %rdi
	callq	_cast_phw_vega10_power_state
	movq	40(%r13), %r14
	movq	48(%r13), %rsi
	movq	_PP_StateUILabel_Battery@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rdx
	xorl	%ecx, %ecx
	cmpq	(%rbx), %rdx
	sete	%cl
	movq	%rsi, -80(%rbp)                 ## 8-byte Spill
	movl	%ecx, (%rsi)
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
	cmpl	$2, (%rax)
	je	LBB0_2
## %bb.1:
	leaq	L_.str(%rip), %rdi
	callq	_pr_info
LBB0_2:
	leaq	8(%r13), %r15
	leaq	24(%r13), %rdi
	cmpq	$0, (%r12)
	cmovneq	%r15, %rdi
	je	LBB0_3
LBB0_10:
	movq	%rdi, -72(%rbp)                 ## 8-byte Spill
	movq	(%r13), %rax
	movq	(%rax), %rbx
	movq	8(%rax), %r12
	movq	_PHM_PlatformCaps_StablePState@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_PP_CAP
	testl	%eax, %eax
	je	LBB0_11
## %bb.12:
	movq	-80(%rbp), %rax                 ## 8-byte Reload
	movq	24(%rax), %rax
	decq	%rax
	xorl	%edi, %edi
	cmpq	$100, %rax
	setb	%dil
	leaq	L_.str.1(%rip), %rsi
	movl	$75, %edx
	callq	_PP_ASSERT_WITH_CODE
	imulq	$75, 16(%r13), %rax
	shrq	$2, %rax
	movabsq	$2951479051793528259, %rcx      ## imm = 0x28F5C28F5C28F5C3
	mulq	%rcx
	shrq	$2, %rdx
	movq	(%r14), %rax
	movq	(%rax), %rcx
	movq	8(%rax), %rax
	leaq	(%rax,%rcx,8), %rax
	addq	$-8, %rax
	.p2align	4, 0x90
LBB0_13:                                ## =>This Inner Loop Header: Depth=1
	movq	(%rax), %rbx
	addq	$-8, %rax
	cmpq	%rbx, %rdx
	jb	LBB0_13
## %bb.14:
	movq	(%r15), %r14
	movq	%r15, -72(%rbp)                 ## 8-byte Spill
	movq	%rbx, %r12
	movq	%r14, -64(%rbp)                 ## 8-byte Spill
	jmp	LBB0_15
LBB0_3:
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movslq	(%rax), %rax
	testq	%rax, %rax
	je	LBB0_10
## %bb.4:
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	movq	8(%rcx), %rcx
	movq	(%rdi), %rdx
	movq	8(%rdi), %rsi
	addq	$8, %rcx
	jmp	LBB0_5
	.p2align	4, 0x90
LBB0_9:                                 ##   in Loop: Header=BB0_5 Depth=1
	addq	$16, %rcx
	decq	%rax
	je	LBB0_10
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	cmpq	%rdx, -8(%rcx)
	jle	LBB0_7
## %bb.6:                               ##   in Loop: Header=BB0_5 Depth=1
	movq	%rdx, -8(%rcx)
LBB0_7:                                 ##   in Loop: Header=BB0_5 Depth=1
	cmpq	%rsi, (%rcx)
	jbe	LBB0_9
## %bb.8:                               ##   in Loop: Header=BB0_5 Depth=1
	movq	%rsi, (%rcx)
	jmp	LBB0_9
LBB0_11:
	movq	%r12, -64(%rbp)                 ## 8-byte Spill
	xorl	%r12d, %r12d
	xorl	%r14d, %r14d
LBB0_15:
	movq	_PHM_PlatformCaps_DisableMclkSwitchingForFrameLock@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_PP_CAP
	movl	%eax, %r15d
	movq	_PHM_PlatformCaps_DisableMclkSwitchForVR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_PP_CAP
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	_PHM_PlatformCaps_ForceMclkHigh@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_PP_CAP
	movq	(%r13), %r9
	movl	16(%r9), %ecx
	testl	%ecx, %ecx
	movq	-56(%rbp), %r13                 ## 8-byte Reload
	movl	$0, %esi
	je	LBB0_22
## %bb.16:
	cmpl	$2, %ecx
	jl	LBB0_20
## %bb.17:
	cmpl	$0, 32(%r9)
	movl	$1, %esi
	je	LBB0_22
## %bb.18:
	testl	%r15d, %r15d
	jne	LBB0_22
## %bb.19:
	cmpl	$0, -44(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_21
	jmp	LBB0_22
LBB0_20:
	movl	$1, %esi
	orl	-44(%rbp), %r15d                ## 4-byte Folded Reload
	jne	LBB0_22
LBB0_21:
	xorl	%esi, %esi
	testl	%eax, %eax
	setne	%sil
LBB0_22:
	movq	8(%r13), %r10
	movq	(%r10), %rcx
	movq	8(%r10), %rax
	cmpq	%rbx, %rax
	movq	-72(%rbp), %rdx                 ## 8-byte Reload
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	jae	LBB0_24
## %bb.23:
	movq	8(%rdx), %rax
	cmpq	%rax, %rbx
	cmovbq	%rbx, %rax
LBB0_24:
	cmpq	%rdi, %rcx
	jae	LBB0_26
## %bb.25:
	movq	(%rdx), %rcx
	cmpq	%rcx, %rdi
	cmovbq	%rdi, %rcx
LBB0_26:
	movq	%rax, 8(%r10)
	movq	%rcx, (%r10)
	movq	24(%r10), %rdx
	cmpq	%rax, %rdx
	jae	LBB0_28
## %bb.27:
	movq	%rdx, 8(%r10)
LBB0_28:
	movq	16(%r10), %r11
	testl	%esi, %esi
	movq	-80(%rbp), %rax                 ## 8-byte Reload
	je	LBB0_54
## %bb.29:
	cmpq	%r11, %rcx
	movq	%r11, %r15
	cmovaq	%rcx, %r15
	movq	8(%rax), %r8
	testq	%r8, %r8
	je	LBB0_44
## %bb.30:
	movq	24(%r9), %rbx
	movq	16(%rax), %r9
	cmpq	$1, %r8
	jne	LBB0_32
## %bb.31:
	xorl	%edi, %edi
LBB0_40:
	testb	$1, %r8b
	je	LBB0_44
## %bb.41:
	shlq	$4, %rdi
	cmpq	%rbx, (%r9,%rdi)
	ja	LBB0_44
## %bb.42:
	movq	8(%r9,%rdi), %rax
	cmpq	%rcx, %rax
	jl	LBB0_44
## %bb.43:
	cmpq	%r11, %rax
	cmovleq	%rax, %r15
	jmp	LBB0_44
LBB0_54:
	movq	%r11, %r15
	cmpq	%rcx, %r11
	jge	LBB0_45
LBB0_44:
	movq	%r15, (%r10)
LBB0_45:
	movq	_PHM_PlatformCaps_StablePState@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_PP_CAP
	testl	%eax, %eax
	je	LBB0_53
## %bb.46:
	movslq	(%r13), %rcx
	testq	%rcx, %rcx
	je	LBB0_53
## %bb.47:
	movq	8(%r13), %rax
	cmpl	$1, %ecx
	jne	LBB0_49
## %bb.48:
	xorl	%edx, %edx
	jmp	LBB0_51
LBB0_32:
	movq	%r8, %rax
	andq	$-2, %rax
	leaq	24(%r9), %rsi
	xorl	%edi, %edi
	jmp	LBB0_33
	.p2align	4, 0x90
LBB0_39:                                ##   in Loop: Header=BB0_33 Depth=1
	addq	$2, %rdi
	addq	$32, %rsi
	cmpq	%rdi, %rax
	je	LBB0_40
LBB0_33:                                ## =>This Inner Loop Header: Depth=1
	cmpq	%rbx, -24(%rsi)
	ja	LBB0_36
## %bb.34:                              ##   in Loop: Header=BB0_33 Depth=1
	movq	-16(%rsi), %rdx
	cmpq	%rcx, %rdx
	jl	LBB0_36
## %bb.35:                              ##   in Loop: Header=BB0_33 Depth=1
	cmpq	%r11, %rdx
	cmovleq	%rdx, %r15
LBB0_36:                                ##   in Loop: Header=BB0_33 Depth=1
	cmpq	%rbx, -8(%rsi)
	ja	LBB0_39
## %bb.37:                              ##   in Loop: Header=BB0_33 Depth=1
	movq	(%rsi), %rdx
	cmpq	%rcx, %rdx
	jl	LBB0_39
## %bb.38:                              ##   in Loop: Header=BB0_33 Depth=1
	cmpq	%r11, %rdx
	cmovleq	%rdx, %r15
	jmp	LBB0_39
LBB0_49:
	movq	%rcx, %rsi
	andq	$-2, %rsi
	leaq	24(%rax), %rdi
	xorl	%edx, %edx
	.p2align	4, 0x90
LBB0_50:                                ## =>This Inner Loop Header: Depth=1
	movq	%r12, -16(%rdi)
	movq	%r14, -24(%rdi)
	movq	%r12, (%rdi)
	movq	%r14, -8(%rdi)
	addq	$2, %rdx
	addq	$32, %rdi
	cmpq	%rdx, %rsi
	jne	LBB0_50
LBB0_51:
	testb	$1, %cl
	je	LBB0_53
## %bb.52:
	shlq	$4, %rdx
	movq	%r12, 8(%rax,%rdx)
	movq	%r14, (%rax,%rdx)
LBB0_53:
	xorl	%eax, %eax
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PP_StateUILabel_Battery,8,3    ## @PP_StateUILabel_Battery
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"VI should always have 2 performance levels"

	.comm	_PHM_PlatformCaps_StablePState,4,2 ## @PHM_PlatformCaps_StablePState
L_.str.1:                               ## @.str.1
	.asciz	"percent sclk value must range from 1% to 100%, setting default value"

	.comm	_PHM_PlatformCaps_DisableMclkSwitchingForFrameLock,4,2 ## @PHM_PlatformCaps_DisableMclkSwitchingForFrameLock
	.comm	_PHM_PlatformCaps_DisableMclkSwitchForVR,4,2 ## @PHM_PlatformCaps_DisableMclkSwitchForVR
	.comm	_PHM_PlatformCaps_ForceMclkHigh,4,2 ## @PHM_PlatformCaps_ForceMclkHigh
	.no_dead_strip	_vega10_apply_state_adjust_rules
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vega10_apply_state_adjust_rules
_vega10_apply_state_adjust_rules:       ; @vega10_apply_state_adjust_rules
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x1
	mov	x20, x0
	ldr	x24, [x0, #56]
	add	x0, x1, #8
	bl	_cast_phw_vega10_power_state
	mov	x19, x0
	ldp	x22, x23, [x20, #40]
Lloh0:
	adrp	x8, _PP_StateUILabel_Battery@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PP_StateUILabel_Battery@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	ldr	x9, [x21]
	cmp	x8, x9
	cset	w8, eq
	str	w8, [x23]
	ldr	w8, [x0]
	cmp	w8, #2
	b.eq	LBB0_2
; %bb.1:
Lloh3:
	adrp	x0, l_.str@PAGE
Lloh4:
	add	x0, x0, l_.str@PAGEOFF
	bl	_pr_info
LBB0_2:
	ldr	x8, [x24]
	add	x21, x20, #8
	add	x9, x20, #24
	cmp	x8, #0
	csel	x27, x9, x21, eq
	cbz	x8, LBB0_7
LBB0_3:
	ldr	x8, [x20]
	ldp	x24, x28, [x8]
Lloh5:
	adrp	x8, _PHM_PlatformCaps_StablePState@GOTPAGE
Lloh6:
	ldr	x8, [x8, _PHM_PlatformCaps_StablePState@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
	bl	_PP_CAP
	cbz	w0, LBB0_14
; %bb.4:
	ldr	x8, [x23, #24]
	sub	x8, x8, #1
	cmp	x8, #100
	cset	w0, lo
Lloh8:
	adrp	x1, l_.str.1@PAGE
Lloh9:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	w24, #75
	mov	w2, #75
	bl	_PP_ASSERT_WITH_CODE
	ldr	x8, [x20, #16]
	mul	x8, x8, x24
	lsr	x8, x8, #2
	mov	x9, #62915
	movk	x9, #23592, lsl #16
	movk	x9, #49807, lsl #32
	movk	x9, #10485, lsl #48
	umulh	x8, x8, x9
	lsr	x8, x8, #2
	ldr	x9, [x22]
	ldp	x10, x9, [x9]
	add	x9, x9, x10, lsl #3
	sub	x9, x9, #8
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x24, [x9], #-8
	cmp	x8, x24
	b.lo	LBB0_5
; %bb.6:
	ldr	x28, [x21]
	mov	x27, x21
	mov	x26, x24
	mov	x25, x28
	b	LBB0_15
LBB0_7:
	ldrsw	x8, [x19]
	cbz	w8, LBB0_3
; %bb.8:
	ldr	x11, [x19, #8]
	ldp	x9, x10, [x27]
	add	x11, x11, #8
	b	LBB0_10
LBB0_9:                                 ;   in Loop: Header=BB0_10 Depth=1
	add	x11, x11, #16
	subs	x8, x8, #1
	b.eq	LBB0_3
LBB0_10:                                ; =>This Inner Loop Header: Depth=1
	ldur	x12, [x11, #-8]
	cmp	x12, x9
	b.le	LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_10 Depth=1
	stur	x9, [x11, #-8]
LBB0_12:                                ;   in Loop: Header=BB0_10 Depth=1
	ldr	x12, [x11]
	cmp	x12, x10
	b.ls	LBB0_9
; %bb.13:                               ;   in Loop: Header=BB0_10 Depth=1
	str	x10, [x11]
	b	LBB0_9
LBB0_14:
	mov	x26, #0
	mov	x25, #0
LBB0_15:
Lloh10:
	adrp	x8, _PHM_PlatformCaps_DisableMclkSwitchingForFrameLock@GOTPAGE
Lloh11:
	ldr	x8, [x8, _PHM_PlatformCaps_DisableMclkSwitchingForFrameLock@GOTPAGEOFF]
Lloh12:
	ldr	w0, [x8]
	bl	_PP_CAP
	mov	x21, x0
Lloh13:
	adrp	x8, _PHM_PlatformCaps_DisableMclkSwitchForVR@GOTPAGE
Lloh14:
	ldr	x8, [x8, _PHM_PlatformCaps_DisableMclkSwitchForVR@GOTPAGEOFF]
Lloh15:
	ldr	w0, [x8]
	bl	_PP_CAP
	mov	x22, x0
Lloh16:
	adrp	x8, _PHM_PlatformCaps_ForceMclkHigh@GOTPAGE
Lloh17:
	ldr	x8, [x8, _PHM_PlatformCaps_ForceMclkHigh@GOTPAGEOFF]
Lloh18:
	ldr	w0, [x8]
	bl	_PP_CAP
	ldr	x9, [x20]
	ldr	w8, [x9, #16]
	cbz	w8, LBB0_19
; %bb.16:
	cmp	w8, #2
	b.lt	LBB0_20
; %bb.17:
	ldr	w8, [x9, #32]
	cmp	w8, #0
	ccmp	w21, #0, #0, ne
	ccmp	w22, #0, #0, eq
	b.ne	LBB0_21
LBB0_18:
	cmp	w0, #0
	cset	w11, ne
	b	LBB0_22
LBB0_19:
	mov	w11, #0
	b	LBB0_22
LBB0_20:
	orr	w8, w21, w22
	cbz	w8, LBB0_18
LBB0_21:
	mov	w11, #1
LBB0_22:
	ldr	x8, [x19, #8]
	ldp	x10, x12, [x8]
	cmp	x12, x24
	b.hs	LBB0_24
; %bb.23:
	ldr	x12, [x27, #8]
	cmp	x24, x12
	csel	x12, x24, x12, lo
LBB0_24:
	cmp	x10, x28
	b.hs	LBB0_26
; %bb.25:
	ldr	x10, [x27]
	cmp	x28, x10
	csel	x10, x28, x10, lo
LBB0_26:
	stp	x10, x12, [x8]
	ldr	x13, [x8, #24]
	cmp	x13, x12
	b.hs	LBB0_28
; %bb.27:
	str	x13, [x8, #8]
LBB0_28:
	ldr	x12, [x8, #16]
	cbz	w11, LBB0_34
; %bb.29:
	cmp	x10, x12
	csel	x11, x10, x12, hi
	ldr	x13, [x23, #8]
	cbz	x13, LBB0_35
; %bb.30:
	ldr	x9, [x9, #24]
	ldr	x14, [x23, #16]
	add	x14, x14, #8
	b	LBB0_32
LBB0_31:                                ;   in Loop: Header=BB0_32 Depth=1
	add	x14, x14, #16
	subs	x13, x13, #1
	b.eq	LBB0_35
LBB0_32:                                ; =>This Inner Loop Header: Depth=1
	ldur	x15, [x14, #-8]
	cmp	x15, x9
	b.hi	LBB0_31
; %bb.33:                               ;   in Loop: Header=BB0_32 Depth=1
	ldr	x15, [x14]
	cmp	x15, x12
	csel	x16, x11, x15, gt
	cmp	x15, x10
	csel	x11, x11, x16, lt
	b	LBB0_31
LBB0_34:
	mov	x11, x12
	cmp	x12, x10
	b.ge	LBB0_36
LBB0_35:
	str	x11, [x8]
LBB0_36:
Lloh19:
	adrp	x8, _PHM_PlatformCaps_StablePState@GOTPAGE
Lloh20:
	ldr	x8, [x8, _PHM_PlatformCaps_StablePState@GOTPAGEOFF]
Lloh21:
	ldr	w0, [x8]
	bl	_PP_CAP
	cbz	w0, LBB0_45
; %bb.37:
	ldrsw	x8, [x19]
	cbz	w8, LBB0_45
; %bb.38:
	ldr	x9, [x19, #8]
	cmp	w8, #8
	b.hs	LBB0_40
; %bb.39:
	mov	x10, #0
	b	LBB0_43
LBB0_40:
	and	x10, x8, #0xfffffffffffffff8
	dup.2d	v0, x25
	dup.2d	v1, x26
	add	x12, x9, #64
	mov	x11, x10
LBB0_41:                                ; =>This Inner Loop Header: Depth=1
	sub	x13, x12, #64
	st2.2d	{ v0, v1 }, [x13]
	sub	x13, x12, #32
	st2.2d	{ v0, v1 }, [x13]
	add	x13, x12, #128
	st2.2d	{ v0, v1 }, [x12], #32
	st2.2d	{ v0, v1 }, [x12]
	mov	x12, x13
	subs	x11, x11, #8
	b.ne	LBB0_41
; %bb.42:
	cmp	x10, x8
	b.eq	LBB0_45
LBB0_43:
	sub	x8, x8, x10
	add	x9, x9, x10, lsl #4
	add	x9, x9, #8
LBB0_44:                                ; =>This Inner Loop Header: Depth=1
	stp	x25, x26, [x9, #-8]
	add	x9, x9, #16
	subs	x8, x8, #1
	b.ne	LBB0_44
LBB0_45:
	mov	w0, #0
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.cfi_endproc
                                        ; -- End function
	.comm	_PP_StateUILabel_Battery,8,3    ; @PP_StateUILabel_Battery
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"VI should always have 2 performance levels"

	.comm	_PHM_PlatformCaps_StablePState,4,2 ; @PHM_PlatformCaps_StablePState
l_.str.1:                               ; @.str.1
	.asciz	"percent sclk value must range from 1% to 100%, setting default value"

	.comm	_PHM_PlatformCaps_DisableMclkSwitchingForFrameLock,4,2 ; @PHM_PlatformCaps_DisableMclkSwitchingForFrameLock
	.comm	_PHM_PlatformCaps_DisableMclkSwitchForVR,4,2 ; @PHM_PlatformCaps_DisableMclkSwitchForVR
	.comm	_PHM_PlatformCaps_ForceMclkHigh,4,2 ; @PHM_PlatformCaps_ForceMclkHigh
	.no_dead_strip	_vega10_apply_state_adjust_rules
.subsections_via_symbols
