	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function meson_sar_adc_hw_enable
_meson_sar_adc_hw_enable:               ## @meson_sar_adc_hw_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	callq	_iio_priv
	movq	%rax, %r14
	movq	%r15, %rdi
	callq	_meson_sar_adc_lock
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_9
## %bb.1:
	movl	(%r14), %edi
	callq	_regulator_enable
	testl	%eax, %eax
	js	LBB0_2
## %bb.3:
	movl	4(%r14), %edi
	callq	_clk_prepare_enable
	testl	%eax, %eax
	je	LBB0_5
## %bb.4:
	movl	%eax, %ebx
	movl	(%r15), %edi
	leaq	L_.str.1(%rip), %rsi
	callq	_dev_err
	jmp	LBB0_7
LBB0_2:
	movl	%eax, %ebx
	movl	(%r15), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
	jmp	LBB0_8
LBB0_5:
	movq	_MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movl	$1, %esi
	callq	_FIELD_PREP
	movl	8(%r14), %edi
	movq	_MESON_SAR_ADC_REG0@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	(%rbx), %edx
	movl	%eax, %ecx
	callq	_regmap_update_bits
	movq	%r15, %rdi
	movl	$1, %esi
	callq	_meson_sar_adc_set_bandgap
	movl	8(%r14), %edi
	movq	_MESON_SAR_ADC_REG3@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	_MESON_SAR_ADC_REG3_ADC_EN@GOTPCREL(%rip), %r13
	movl	(%r13), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	$5, %edi
	callq	_udelay
	movl	12(%r14), %edi
	callq	_clk_prepare_enable
	testl	%eax, %eax
	je	LBB0_10
## %bb.6:
	movl	%eax, %ebx
	movl	(%r15), %edi
	leaq	L_.str.2(%rip), %rsi
	callq	_dev_err
	movl	8(%r14), %edi
	movl	(%r12), %esi
	movl	(%r13), %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_meson_sar_adc_set_bandgap
	movl	4(%r14), %edi
	callq	_clk_disable_unprepare
LBB0_7:
	movl	(%r14), %edi
	callq	_regulator_disable
LBB0_8:
	movq	%r15, %rdi
	callq	_meson_sar_adc_unlock
LBB0_9:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_10:
	movq	%r15, %rdi
	callq	_meson_sar_adc_unlock
	xorl	%ebx, %ebx
	jmp	LBB0_9
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"failed to enable vref regulator\n"

L_.str.1:                               ## @.str.1
	.asciz	"failed to enable core clk\n"

	.comm	_MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK,4,2 ## @MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK
	.comm	_MESON_SAR_ADC_REG0,4,2         ## @MESON_SAR_ADC_REG0
	.comm	_MESON_SAR_ADC_REG3,4,2         ## @MESON_SAR_ADC_REG3
	.comm	_MESON_SAR_ADC_REG3_ADC_EN,4,2  ## @MESON_SAR_ADC_REG3_ADC_EN
L_.str.2:                               ## @.str.2
	.asciz	"failed to enable adc clk\n"

	.no_dead_strip	_meson_sar_adc_hw_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function meson_sar_adc_hw_enable
_meson_sar_adc_hw_enable:               ; @meson_sar_adc_hw_enable
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	bl	_iio_priv
	mov	x20, x0
	mov	x0, x19
	bl	_meson_sar_adc_lock
	mov	x21, x0
	cbnz	w0, LBB0_9
; %bb.1:
	ldr	w0, [x20]
	bl	_regulator_enable
	tbnz	w0, #31, LBB0_4
; %bb.2:
	ldr	w0, [x20, #4]
	bl	_clk_prepare_enable
	cbz	w0, LBB0_5
; %bb.3:
	mov	x21, x0
	ldr	w0, [x19]
Lloh0:
	adrp	x1, l_.str.1@PAGE
Lloh1:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_err
	b	LBB0_7
LBB0_4:
	mov	x21, x0
	ldr	w0, [x19]
Lloh2:
	adrp	x1, l_.str@PAGE
Lloh3:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
	b	LBB0_8
LBB0_5:
Lloh4:
	adrp	x21, _MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK@GOTPAGE
Lloh5:
	ldr	x21, [x21, _MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK@GOTPAGEOFF]
	ldr	w0, [x21]
	mov	w1, #1
	bl	_FIELD_PREP
	mov	x3, x0
	ldr	w0, [x20, #8]
Lloh6:
	adrp	x8, _MESON_SAR_ADC_REG0@GOTPAGE
Lloh7:
	ldr	x8, [x8, _MESON_SAR_ADC_REG0@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	ldr	w2, [x21]
	bl	_regmap_update_bits
	mov	x0, x19
	mov	w1, #1
	bl	_meson_sar_adc_set_bandgap
	ldr	w0, [x20, #8]
Lloh9:
	adrp	x22, _MESON_SAR_ADC_REG3@GOTPAGE
Lloh10:
	ldr	x22, [x22, _MESON_SAR_ADC_REG3@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh11:
	adrp	x23, _MESON_SAR_ADC_REG3_ADC_EN@GOTPAGE
Lloh12:
	ldr	x23, [x23, _MESON_SAR_ADC_REG3_ADC_EN@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	x3, x2
	bl	_regmap_update_bits
	mov	w0, #5
	bl	_udelay
	ldr	w0, [x20, #12]
	bl	_clk_prepare_enable
	mov	x21, x0
	cbz	w0, LBB0_8
; %bb.6:
	ldr	w0, [x19]
Lloh13:
	adrp	x1, l_.str.2@PAGE
Lloh14:
	add	x1, x1, l_.str.2@PAGEOFF
	bl	_dev_err
	ldr	w0, [x20, #8]
	ldr	w1, [x22]
	ldr	w2, [x23]
	mov	w3, #0
	bl	_regmap_update_bits
	mov	x0, x19
	mov	w1, #0
	bl	_meson_sar_adc_set_bandgap
	ldr	w0, [x20, #4]
	bl	_clk_disable_unprepare
LBB0_7:
	ldr	w0, [x20]
	bl	_regulator_disable
LBB0_8:
	mov	x0, x19
	bl	_meson_sar_adc_unlock
LBB0_9:
	mov	x0, x21
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpAdd	Lloh13, Lloh14
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"failed to enable vref regulator\n"

l_.str.1:                               ; @.str.1
	.asciz	"failed to enable core clk\n"

	.comm	_MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK,4,2 ; @MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK
	.comm	_MESON_SAR_ADC_REG0,4,2         ; @MESON_SAR_ADC_REG0
	.comm	_MESON_SAR_ADC_REG3,4,2         ; @MESON_SAR_ADC_REG3
	.comm	_MESON_SAR_ADC_REG3_ADC_EN,4,2  ; @MESON_SAR_ADC_REG3_ADC_EN
l_.str.2:                               ; @.str.2
	.asciz	"failed to enable adc clk\n"

	.no_dead_strip	_meson_sar_adc_hw_enable
.subsections_via_symbols
