	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mmhub_v1_0_update_medium_grain_clock_gating
_mmhub_v1_0_update_medium_grain_clock_gating: ## @mmhub_v1_0_update_medium_grain_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %r13
	movq	_MMHUB@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_mmATC_L2_MISC_CG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	$0, -44(%rbp)                   ## 4-byte Folded Spill
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	%eax, %r15d
	movq	(%r13), %rax
	movq	_CHIP_RAVEN@GOTPCREL(%rip), %rcx
	movl	(%rbx), %edi
	cmpq	(%rcx), %rax
	jne	LBB0_2
## %bb.1:
	movq	_mmDAGB0_CNTL_MISC2_RV@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	%eax, %r12d
	testl	%r14d, %r14d
	jne	LBB0_3
	jmp	LBB0_6
LBB0_2:
	movq	_mmDAGB0_CNTL_MISC2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	%eax, %r12d
	movl	(%rbx), %edi
	movq	_mmDAGB1_CNTL_MISC2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	testl	%r14d, %r14d
	je	LBB0_6
LBB0_3:
	movq	_AMD_CG_SUPPORT_MC_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 8(%r13)
	je	LBB0_6
## %bb.4:
	movq	_DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPCREL(%rip), %rax
	movq	_DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	_ATC_L2_MISC_CG__ENABLE_MASK@GOTPCREL(%rip), %rax
	movq	_DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movl	(%rax), %ecx
	movq	_DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	orl	%r15d, %ecx
	movq	_DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	notl	%ebx
	andl	%r12d, %ebx
	movq	(%r13), %rax
	movq	_CHIP_RAVEN@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rax
	je	LBB0_5
## %bb.9:
	movq	_DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPCREL(%rip), %rax
	movq	_DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r14d
	orl	(%rax), %r14d
	movq	_DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
	movq	_DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
	movq	_DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
	movq	_DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
	notl	%r14d
	andl	-44(%rbp), %r14d                ## 4-byte Folded Reload
	jmp	LBB0_10
LBB0_6:
	movq	_ATC_L2_MISC_CG__ENABLE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	notl	%ecx
	movq	_DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPCREL(%rip), %rax
	movq	_DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPCREL(%rip), %rdx
	movq	_DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPCREL(%rip), %rsi
	movq	_DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPCREL(%rip), %rdi
	movq	_DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPCREL(%rip), %r8
	movq	_DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPCREL(%rip), %r9
	movl	(%rax), %ebx
	orl	%r12d, %ebx
	orl	(%rdx), %ebx
	orl	(%rsi), %ebx
	orl	(%rdi), %ebx
	orl	(%r8), %ebx
	orl	(%r9), %ebx
	andl	%r15d, %ecx
	movq	(%r13), %rax
	movq	_CHIP_RAVEN@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rax
	jne	LBB0_8
LBB0_5:
	movl	-44(%rbp), %r14d                ## 4-byte Reload
	jmp	LBB0_10
LBB0_8:
	movq	_DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPCREL(%rip), %rax
	movq	_DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPCREL(%rip), %rdx
	movq	_DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPCREL(%rip), %rsi
	movq	_DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPCREL(%rip), %rdi
	movq	_DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPCREL(%rip), %r8
	movq	_DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPCREL(%rip), %r9
	movl	(%rax), %r14d
	orl	-44(%rbp), %r14d                ## 4-byte Folded Reload
	orl	(%rdx), %r14d
	orl	(%rsi), %r14d
	orl	(%rdi), %r14d
	orl	(%r8), %r14d
	orl	(%r9), %r14d
LBB0_10:
	cmpl	%ecx, %r15d
	movq	_MMHUB@GOTPCREL(%rip), %r15
	je	LBB0_12
## %bb.11:
	movl	(%r15), %edi
	movq	_mmATC_L2_MISC_CG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
LBB0_12:
	cmpl	%ebx, %r12d
	je	LBB0_17
## %bb.13:
	movq	(%r13), %rax
	movl	(%r15), %edi
	movq	_CHIP_RAVEN@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_15
## %bb.14:
	movq	_mmDAGB0_CNTL_MISC2_RV@GOTPCREL(%rip), %rax
	jmp	LBB0_16
LBB0_15:
	movq	_mmDAGB0_CNTL_MISC2@GOTPCREL(%rip), %rax
LBB0_16:
	movl	(%rax), %edx
	xorl	%esi, %esi
	movl	%ebx, %ecx
	callq	_WREG32_SOC15
LBB0_17:
	movq	(%r13), %rax
	movq	_CHIP_RAVEN@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_20
## %bb.18:
	cmpl	%r14d, -44(%rbp)                ## 4-byte Folded Reload
	je	LBB0_20
## %bb.19:
	movl	(%r15), %edi
	movq	_mmDAGB1_CNTL_MISC2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	movl	%r14d, %ecx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_SOC15                   ## TAILCALL
LBB0_20:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MMHUB,4,2                      ## @MMHUB
	.comm	_mmATC_L2_MISC_CG,4,2           ## @mmATC_L2_MISC_CG
	.comm	_CHIP_RAVEN,8,3                 ## @CHIP_RAVEN
	.comm	_mmDAGB0_CNTL_MISC2,4,2         ## @mmDAGB0_CNTL_MISC2
	.comm	_mmDAGB1_CNTL_MISC2,4,2         ## @mmDAGB1_CNTL_MISC2
	.comm	_mmDAGB0_CNTL_MISC2_RV,4,2      ## @mmDAGB0_CNTL_MISC2_RV
	.comm	_AMD_CG_SUPPORT_MC_MGCG,4,2     ## @AMD_CG_SUPPORT_MC_MGCG
	.comm	_ATC_L2_MISC_CG__ENABLE_MASK,4,2 ## @ATC_L2_MISC_CG__ENABLE_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK,4,2 ## @DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK
	.comm	_DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK,4,2 ## @DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK
	.comm	_DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK,4,2 ## @DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK
	.comm	_DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK,4,2 ## @DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK
	.comm	_DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK,4,2 ## @DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK
	.comm	_DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK,4,2 ## @DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK
	.comm	_DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK,4,2 ## @DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK
	.no_dead_strip	_mmhub_v1_0_update_medium_grain_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mmhub_v1_0_update_medium_grain_clock_gating
_mmhub_v1_0_update_medium_grain_clock_gating: ; @mmhub_v1_0_update_medium_grain_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x23, x1
	mov	x19, x0
Lloh0:
	adrp	x25, _MMHUB@GOTPAGE
Lloh1:
	ldr	x25, [x25, _MMHUB@GOTPAGEOFF]
	ldr	w0, [x25]
Lloh2:
	adrp	x8, _mmATC_L2_MISC_CG@GOTPAGE
Lloh3:
	ldr	x8, [x8, _mmATC_L2_MISC_CG@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_RREG32_SOC15
	mov	x20, x0
	ldr	x8, [x19]
Lloh5:
	adrp	x27, _CHIP_RAVEN@GOTPAGE
Lloh6:
	ldr	x27, [x27, _CHIP_RAVEN@GOTPAGEOFF]
	ldr	x9, [x27]
Lloh7:
	adrp	x10, _mmDAGB0_CNTL_MISC2@GOTPAGE
Lloh8:
	ldr	x10, [x10, _mmDAGB0_CNTL_MISC2@GOTPAGEOFF]
	ldr	w0, [x25]
Lloh9:
	adrp	x21, _mmDAGB1_CNTL_MISC2@GOTPAGE
Lloh10:
	ldr	x21, [x21, _mmDAGB1_CNTL_MISC2@GOTPAGEOFF]
Lloh11:
	adrp	x11, _mmDAGB0_CNTL_MISC2_RV@GOTPAGE
Lloh12:
	ldr	x11, [x11, _mmDAGB0_CNTL_MISC2_RV@GOTPAGEOFF]
	cmp	x8, x9
	b.ne	LBB0_2
; %bb.1:
	mov	x26, x10
	mov	x28, x11
	ldr	w2, [x11]
	mov	w1, #0
	bl	_RREG32_SOC15
	mov	x22, x0
	mov	w21, #0
	cbnz	w23, LBB0_3
	b	LBB0_6
LBB0_2:
	mov	x28, x11
	mov	x26, x10
	ldr	w2, [x10]
	mov	w1, #0
	bl	_RREG32_SOC15
	mov	x22, x0
	ldr	w0, [x25]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_RREG32_SOC15
	mov	x21, x0
	cbz	w23, LBB0_6
LBB0_3:
	ldr	w8, [x19, #8]
Lloh13:
	adrp	x9, _AMD_CG_SUPPORT_MC_MGCG@GOTPAGE
Lloh14:
	ldr	x9, [x9, _AMD_CG_SUPPORT_MC_MGCG@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_6
; %bb.4:
Lloh16:
	adrp	x8, _ATC_L2_MISC_CG__ENABLE_MASK@GOTPAGE
Lloh17:
	ldr	x8, [x8, _ATC_L2_MISC_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	orr	w3, w8, w20
Lloh19:
	adrp	x8, _DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPAGE
Lloh20:
	ldr	x8, [x8, _DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
Lloh22:
	adrp	x9, _DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPAGE
Lloh23:
	ldr	x9, [x9, _DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh25:
	adrp	x9, _DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPAGE
Lloh26:
	ldr	x9, [x9, _DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh28:
	adrp	x9, _DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPAGE
Lloh29:
	ldr	x9, [x9, _DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh31:
	adrp	x9, _DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPAGE
Lloh32:
	ldr	x9, [x9, _DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPAGEOFF]
Lloh33:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh34:
	adrp	x9, _DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPAGE
Lloh35:
	ldr	x9, [x9, _DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPAGEOFF]
Lloh36:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w23, w22, w8
	ldr	x8, [x19]
	ldr	x9, [x27]
	cmp	x8, x9
	b.eq	LBB0_7
; %bb.5:
Lloh37:
	adrp	x8, _DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPAGE
Lloh38:
	ldr	x8, [x8, _DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
Lloh40:
	adrp	x9, _DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPAGE
Lloh41:
	ldr	x9, [x9, _DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPAGEOFF]
Lloh42:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh43:
	adrp	x9, _DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPAGE
Lloh44:
	ldr	x9, [x9, _DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPAGEOFF]
Lloh45:
	ldr	w9, [x9]
Lloh46:
	adrp	x10, _DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPAGE
Lloh47:
	ldr	x10, [x10, _DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh48:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh49:
	adrp	x9, _DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPAGE
Lloh50:
	ldr	x9, [x9, _DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPAGEOFF]
Lloh51:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh52:
	adrp	x9, _DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPAGE
Lloh53:
	ldr	x9, [x9, _DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPAGEOFF]
Lloh54:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w24, w21, w8
	cmp	w20, w3
	b.ne	LBB0_8
	b	LBB0_9
LBB0_6:
Lloh55:
	adrp	x8, _ATC_L2_MISC_CG__ENABLE_MASK@GOTPAGE
Lloh56:
	ldr	x8, [x8, _ATC_L2_MISC_CG__ENABLE_MASK@GOTPAGEOFF]
Lloh57:
	ldr	w8, [x8]
	bic	w3, w20, w8
Lloh58:
	adrp	x8, _DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPAGE
Lloh59:
	ldr	x8, [x8, _DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPAGEOFF]
Lloh60:
	ldr	w8, [x8]
Lloh61:
	adrp	x9, _DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPAGE
Lloh62:
	ldr	x9, [x9, _DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPAGEOFF]
Lloh63:
	ldr	w9, [x9]
Lloh64:
	adrp	x10, _DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPAGE
Lloh65:
	ldr	x10, [x10, _DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPAGEOFF]
Lloh66:
	ldr	w10, [x10]
Lloh67:
	adrp	x11, _DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPAGE
Lloh68:
	ldr	x11, [x11, _DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPAGEOFF]
Lloh69:
	ldr	w11, [x11]
Lloh70:
	adrp	x12, _DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPAGE
Lloh71:
	ldr	x12, [x12, _DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPAGEOFF]
Lloh72:
	ldr	w12, [x12]
Lloh73:
	adrp	x13, _DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPAGE
Lloh74:
	ldr	x13, [x13, _DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPAGEOFF]
Lloh75:
	ldr	w13, [x13]
	orr	w8, w8, w22
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w23, w8, w13
	ldr	x8, [x19]
	ldr	x9, [x27]
	cmp	x8, x9
	b.ne	LBB0_15
LBB0_7:
	mov	x24, x21
	cmp	w20, w3
	b.eq	LBB0_9
LBB0_8:
	ldr	w0, [x25]
Lloh76:
	adrp	x8, _mmATC_L2_MISC_CG@GOTPAGE
Lloh77:
	ldr	x8, [x8, _mmATC_L2_MISC_CG@GOTPAGEOFF]
Lloh78:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_WREG32_SOC15
LBB0_9:
	cmp	w22, w23
	b.eq	LBB0_11
; %bb.10:
	ldr	x8, [x19]
	ldr	x9, [x27]
	ldr	w0, [x25]
	cmp	x8, x9
	csel	x8, x28, x26, eq
	ldr	w2, [x8]
	mov	w1, #0
	mov	x3, x23
	bl	_WREG32_SOC15
LBB0_11:
	ldr	x8, [x19]
	ldr	x9, [x27]
	cmp	x8, x9
	b.eq	LBB0_14
; %bb.12:
	cmp	w21, w24
	b.eq	LBB0_14
; %bb.13:
	ldr	w0, [x25]
Lloh79:
	adrp	x8, _mmDAGB1_CNTL_MISC2@GOTPAGE
Lloh80:
	ldr	x8, [x8, _mmDAGB1_CNTL_MISC2@GOTPAGEOFF]
Lloh81:
	ldr	w2, [x8]
	mov	w1, #0
	mov	x3, x24
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_WREG32_SOC15
LBB0_14:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
LBB0_15:
Lloh82:
	adrp	x8, _DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPAGE
Lloh83:
	ldr	x8, [x8, _DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK@GOTPAGEOFF]
Lloh84:
	ldr	w8, [x8]
Lloh85:
	adrp	x9, _DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPAGE
Lloh86:
	ldr	x9, [x9, _DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK@GOTPAGEOFF]
Lloh87:
	ldr	w9, [x9]
Lloh88:
	adrp	x10, _DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPAGE
Lloh89:
	ldr	x10, [x10, _DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK@GOTPAGEOFF]
Lloh90:
	ldr	w10, [x10]
Lloh91:
	adrp	x11, _DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPAGE
Lloh92:
	ldr	x11, [x11, _DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK@GOTPAGEOFF]
Lloh93:
	ldr	w11, [x11]
Lloh94:
	adrp	x12, _DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPAGE
Lloh95:
	ldr	x12, [x12, _DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK@GOTPAGEOFF]
Lloh96:
	ldr	w12, [x12]
Lloh97:
	adrp	x13, _DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPAGE
Lloh98:
	ldr	x13, [x13, _DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK@GOTPAGEOFF]
Lloh99:
	ldr	w13, [x13]
	orr	w8, w8, w21
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w24, w8, w13
	cmp	w20, w3
	b.ne	LBB0_8
	b	LBB0_9
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.cfi_endproc
                                        ; -- End function
	.comm	_MMHUB,4,2                      ; @MMHUB
	.comm	_mmATC_L2_MISC_CG,4,2           ; @mmATC_L2_MISC_CG
	.comm	_CHIP_RAVEN,8,3                 ; @CHIP_RAVEN
	.comm	_mmDAGB0_CNTL_MISC2,4,2         ; @mmDAGB0_CNTL_MISC2
	.comm	_mmDAGB1_CNTL_MISC2,4,2         ; @mmDAGB1_CNTL_MISC2
	.comm	_mmDAGB0_CNTL_MISC2_RV,4,2      ; @mmDAGB0_CNTL_MISC2_RV
	.comm	_AMD_CG_SUPPORT_MC_MGCG,4,2     ; @AMD_CG_SUPPORT_MC_MGCG
	.comm	_ATC_L2_MISC_CG__ENABLE_MASK,4,2 ; @ATC_L2_MISC_CG__ENABLE_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK
	.comm	_DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK,4,2 ; @DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK
	.comm	_DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK,4,2 ; @DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK
	.comm	_DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK,4,2 ; @DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK
	.comm	_DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK,4,2 ; @DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK
	.comm	_DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK,4,2 ; @DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK
	.comm	_DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK,4,2 ; @DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK
	.comm	_DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK,4,2 ; @DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK
	.no_dead_strip	_mmhub_v1_0_update_medium_grain_clock_gating
.subsections_via_symbols
