	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function intel_pre_enable_lvds
_intel_pre_enable_lvds:                 ## @intel_pre_enable_lvds
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %rbx
	callq	_to_lvds_encoder
	movq	%rax, %r15
	movl	(%rbx), %edi
	callq	_to_i915
	movq	%rax, %r13
	movl	28(%r14), %edi
	callq	_to_intel_crtc
	movl	(%rax), %r12d
	movq	%r13, %rdi
	callq	_HAS_PCH_SPLIT
	movq	%r13, %rdi
	movl	%r12d, %esi
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	callq	_assert_fdi_rx_pll_disabled
	movl	20(%r14), %esi
	movq	%r13, %rdi
	callq	_assert_shared_dpll_disabled
	jmp	LBB0_3
LBB0_2:
	callq	_assert_pll_disabled
LBB0_3:
	movq	%r15, %rsi
	addq	$24, %rsi
	movq	%r13, %rdi
	callq	_intel_lvds_pps_init_hw
	movq	_LVDS_PORT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_LVDS_A0A2_CLKA_POWER_UP@GOTPCREL(%rip), %rax
	orl	(%r15), %ebx
	orl	(%rax), %ebx
	movq	%r13, %rdi
	callq	_HAS_PCH_CPT
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	movq	_LVDS_PIPE_SEL_MASK_CPT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %ebx
	movl	%r12d, %edi
	callq	_LVDS_PIPE_SEL_CPT
	jmp	LBB0_6
LBB0_5:
	movq	_LVDS_PIPE_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %ebx
	movl	%r12d, %edi
	callq	_LVDS_PIPE_SEL
LBB0_6:
	orl	%ebx, %eax
	movq	_LVDS_BORDER_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	orl	16(%r14), %ecx
	cmpq	$0, 16(%r15)
	movq	_LVDS_B0B3_POWER_UP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_LVDS_CLKB_POWER_UP@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	je	LBB0_8
## %bb.7:
	orl	%ecx, %eax
	orl	%edx, %eax
	jmp	LBB0_9
LBB0_8:
	orl	%eax, %edx
	notl	%edx
	andl	%edx, %ecx
	movl	%ecx, %eax
LBB0_9:
	movq	_LVDS_A3_POWER_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	orl	4(%r15), %ebx
	movq	%r13, %rdi
	movl	$4, %esi
	callq	_IS_GEN
	testq	%rax, %rax
	je	LBB0_14
## %bb.10:
	cmpq	$0, 8(%r14)
	je	LBB0_13
## %bb.11:
	cmpl	$18, (%r14)
	jne	LBB0_13
## %bb.12:
	movq	_LVDS_ENABLE_DITHER@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	jmp	LBB0_14
LBB0_13:
	movq	_LVDS_ENABLE_DITHER@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %ebx
LBB0_14:
	movq	_LVDS_HSYNC_POLARITY@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_LVDS_VSYNC_POLARITY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, %edx
	orl	%eax, %edx
	notl	%edx
	andl	%ebx, %edx
	movl	24(%r14), %esi
	movq	_DRM_MODE_FLAG_NHSYNC@GOTPCREL(%rip), %rdi
	movl	(%rdi), %edi
	andl	%esi, %edi
	cmovnel	%eax, %edi
	movq	_DRM_MODE_FLAG_NVSYNC@GOTPCREL(%rip), %rax
	andl	(%rax), %esi
	cmovnel	%ecx, %esi
	orl	%edi, %esi
	orl	%edx, %esi
	movl	8(%r15), %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_I915_WRITE                     ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_LVDS_PORT_EN,4,2               ## @LVDS_PORT_EN
	.comm	_LVDS_A0A2_CLKA_POWER_UP,4,2    ## @LVDS_A0A2_CLKA_POWER_UP
	.comm	_LVDS_PIPE_SEL_MASK_CPT,4,2     ## @LVDS_PIPE_SEL_MASK_CPT
	.comm	_LVDS_PIPE_SEL_MASK,4,2         ## @LVDS_PIPE_SEL_MASK
	.comm	_LVDS_BORDER_ENABLE,4,2         ## @LVDS_BORDER_ENABLE
	.comm	_LVDS_B0B3_POWER_UP,4,2         ## @LVDS_B0B3_POWER_UP
	.comm	_LVDS_CLKB_POWER_UP,4,2         ## @LVDS_CLKB_POWER_UP
	.comm	_LVDS_A3_POWER_MASK,4,2         ## @LVDS_A3_POWER_MASK
	.comm	_LVDS_ENABLE_DITHER,4,2         ## @LVDS_ENABLE_DITHER
	.comm	_LVDS_HSYNC_POLARITY,4,2        ## @LVDS_HSYNC_POLARITY
	.comm	_LVDS_VSYNC_POLARITY,4,2        ## @LVDS_VSYNC_POLARITY
	.comm	_DRM_MODE_FLAG_NHSYNC,4,2       ## @DRM_MODE_FLAG_NHSYNC
	.comm	_DRM_MODE_FLAG_NVSYNC,4,2       ## @DRM_MODE_FLAG_NVSYNC
	.no_dead_strip	_intel_pre_enable_lvds
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function intel_pre_enable_lvds
_intel_pre_enable_lvds:                 ; @intel_pre_enable_lvds
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x1
	mov	x21, x0
	bl	_to_lvds_encoder
	mov	x19, x0
	ldr	w0, [x21]
	bl	_to_i915
	mov	x21, x0
	ldr	w0, [x20, #28]
	bl	_to_intel_crtc
	ldr	w22, [x0]
	mov	x0, x21
	bl	_HAS_PCH_SPLIT
	cbz	x0, LBB0_2
; %bb.1:
	mov	x0, x21
	mov	x1, x22
	bl	_assert_fdi_rx_pll_disabled
	ldr	w1, [x20, #20]
	mov	x0, x21
	bl	_assert_shared_dpll_disabled
	b	LBB0_3
LBB0_2:
	mov	x0, x21
	mov	x1, x22
	bl	_assert_pll_disabled
LBB0_3:
	add	x1, x19, #24
	mov	x0, x21
	bl	_intel_lvds_pps_init_hw
	ldr	w8, [x19]
Lloh0:
	adrp	x9, _LVDS_PORT_EN@GOTPAGE
Lloh1:
	ldr	x9, [x9, _LVDS_PORT_EN@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
Lloh3:
	adrp	x10, _LVDS_A0A2_CLKA_POWER_UP@GOTPAGE
Lloh4:
	ldr	x10, [x10, _LVDS_A0A2_CLKA_POWER_UP@GOTPAGEOFF]
Lloh5:
	ldr	w10, [x10]
	orr	w8, w9, w8
	orr	w23, w8, w10
	mov	x0, x21
	bl	_HAS_PCH_CPT
	cbz	x0, LBB0_5
; %bb.4:
Lloh6:
	adrp	x8, _LVDS_PIPE_SEL_MASK_CPT@GOTPAGE
Lloh7:
	ldr	x8, [x8, _LVDS_PIPE_SEL_MASK_CPT@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	bic	w23, w23, w8
	mov	x0, x22
	bl	_LVDS_PIPE_SEL_CPT
	b	LBB0_6
LBB0_5:
Lloh9:
	adrp	x8, _LVDS_PIPE_SEL_MASK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _LVDS_PIPE_SEL_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	bic	w23, w23, w8
	mov	x0, x22
	bl	_LVDS_PIPE_SEL
LBB0_6:
	orr	w8, w23, w0
Lloh12:
	adrp	x9, _LVDS_BORDER_ENABLE@GOTPAGE
Lloh13:
	ldr	x9, [x9, _LVDS_BORDER_ENABLE@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	bic	w8, w8, w9
	ldr	w9, [x20, #16]
	orr	w8, w8, w9
	ldr	x9, [x19, #16]
Lloh15:
	adrp	x10, _LVDS_B0B3_POWER_UP@GOTPAGE
Lloh16:
	ldr	x10, [x10, _LVDS_B0B3_POWER_UP@GOTPAGEOFF]
Lloh17:
	ldr	w10, [x10]
Lloh18:
	adrp	x11, _LVDS_CLKB_POWER_UP@GOTPAGE
Lloh19:
	ldr	x11, [x11, _LVDS_CLKB_POWER_UP@GOTPAGEOFF]
Lloh20:
	ldr	w11, [x11]
	orr	w12, w11, w10
	bic	w12, w8, w12
	orr	w8, w10, w8
	orr	w8, w8, w11
	cmp	x9, #0
	csel	w8, w12, w8, eq
Lloh21:
	adrp	x9, _LVDS_A3_POWER_MASK@GOTPAGE
Lloh22:
	ldr	x9, [x9, _LVDS_A3_POWER_MASK@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	bic	w8, w8, w9
	ldr	w9, [x19, #4]
	orr	w22, w8, w9
	mov	x0, x21
	mov	w1, #4
	bl	_IS_GEN
	cbz	x0, LBB0_11
; %bb.7:
	ldr	x8, [x20, #8]
	cbz	x8, LBB0_10
; %bb.8:
	ldr	w8, [x20]
	cmp	w8, #18
	b.ne	LBB0_10
; %bb.9:
Lloh24:
	adrp	x8, _LVDS_ENABLE_DITHER@GOTPAGE
Lloh25:
	ldr	x8, [x8, _LVDS_ENABLE_DITHER@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	orr	w22, w8, w22
	b	LBB0_11
LBB0_10:
Lloh27:
	adrp	x8, _LVDS_ENABLE_DITHER@GOTPAGE
Lloh28:
	ldr	x8, [x8, _LVDS_ENABLE_DITHER@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	bic	w22, w22, w8
LBB0_11:
Lloh30:
	adrp	x8, _LVDS_HSYNC_POLARITY@GOTPAGE
Lloh31:
	ldr	x8, [x8, _LVDS_HSYNC_POLARITY@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
Lloh33:
	adrp	x9, _LVDS_VSYNC_POLARITY@GOTPAGE
Lloh34:
	ldr	x9, [x9, _LVDS_VSYNC_POLARITY@GOTPAGEOFF]
Lloh35:
	ldr	w9, [x9]
	orr	w10, w9, w8
	bic	w10, w22, w10
	ldr	w11, [x20, #24]
Lloh36:
	adrp	x12, _DRM_MODE_FLAG_NHSYNC@GOTPAGE
Lloh37:
	ldr	x12, [x12, _DRM_MODE_FLAG_NHSYNC@GOTPAGEOFF]
Lloh38:
	ldr	w12, [x12]
	tst	w12, w11
	csel	w8, wzr, w8, eq
	orr	w8, w8, w10
Lloh39:
	adrp	x10, _DRM_MODE_FLAG_NVSYNC@GOTPAGE
Lloh40:
	ldr	x10, [x10, _DRM_MODE_FLAG_NVSYNC@GOTPAGEOFF]
Lloh41:
	ldr	w10, [x10]
	tst	w10, w11
	csel	w9, wzr, w9, eq
	orr	w1, w8, w9
	ldr	w0, [x19, #8]
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_I915_WRITE
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.cfi_endproc
                                        ; -- End function
	.comm	_LVDS_PORT_EN,4,2               ; @LVDS_PORT_EN
	.comm	_LVDS_A0A2_CLKA_POWER_UP,4,2    ; @LVDS_A0A2_CLKA_POWER_UP
	.comm	_LVDS_PIPE_SEL_MASK_CPT,4,2     ; @LVDS_PIPE_SEL_MASK_CPT
	.comm	_LVDS_PIPE_SEL_MASK,4,2         ; @LVDS_PIPE_SEL_MASK
	.comm	_LVDS_BORDER_ENABLE,4,2         ; @LVDS_BORDER_ENABLE
	.comm	_LVDS_B0B3_POWER_UP,4,2         ; @LVDS_B0B3_POWER_UP
	.comm	_LVDS_CLKB_POWER_UP,4,2         ; @LVDS_CLKB_POWER_UP
	.comm	_LVDS_A3_POWER_MASK,4,2         ; @LVDS_A3_POWER_MASK
	.comm	_LVDS_ENABLE_DITHER,4,2         ; @LVDS_ENABLE_DITHER
	.comm	_LVDS_HSYNC_POLARITY,4,2        ; @LVDS_HSYNC_POLARITY
	.comm	_LVDS_VSYNC_POLARITY,4,2        ; @LVDS_VSYNC_POLARITY
	.comm	_DRM_MODE_FLAG_NHSYNC,4,2       ; @DRM_MODE_FLAG_NHSYNC
	.comm	_DRM_MODE_FLAG_NVSYNC,4,2       ; @DRM_MODE_FLAG_NVSYNC
	.no_dead_strip	_intel_pre_enable_lvds
.subsections_via_symbols
