	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dcn10_init_hw
_dcn10_init_hw:                         ## @dcn10_init_hw
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	88(%rdi), %r15
	movq	64(%r15), %rax
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
	movq	72(%r15), %rbx
	movq	8(%rdi), %r13
	movq	80(%rdi), %rax
	movq	(%rax), %r12
	movq	96(%rdi), %rdi
	movq	%r15, %rax
	testq	%rdi, %rdi
	je	LBB0_3
## %bb.1:
	movq	(%rdi), %rax
	movq	(%rax), %rcx
	movq	%r15, %rax
	testq	%rcx, %rcx
	je	LBB0_3
## %bb.2:
	callq	*%rcx
	movq	88(%r14), %rax
LBB0_3:
	movq	56(%rax), %rax
	testq	%rax, %rax
	je	LBB0_6
## %bb.4:
	movq	(%rax), %rax
	movq	8(%rax), %rax
	testq	%rax, %rax
	je	LBB0_6
## %bb.5:
	movq	56(%r15), %rdi
	callq	*%rax
LBB0_6:
	movq	80(%r14), %rax
	movl	8(%rax), %edi
	callq	_IS_FPGA_MAXIMUS_DC
	testq	%rax, %rax
	je	LBB0_11
## %bb.7:
	movq	_REFCLK_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_REG_WRITE
	movq	_DCHUBBUB_GLOBAL_TIMER_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_DCHUBBUB_GLOBAL_TIMER_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %edx
	callq	_REG_UPDATE
	movq	_DIO_MEM_PWR_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_REG_WRITE
	cmpl	$0, 56(%r14)
	jne	LBB0_9
## %bb.8:
	movq	_DCCG_GATE_DISABLE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_REG_WRITE
	movq	_DCCG_GATE_DISABLE_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_REG_WRITE
	movq	_DCFCLK_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_DCFCLK_GATE_DIS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_REG_UPDATE
LBB0_9:
	movq	16(%r14), %rax
	movq	%r13, %rdi
	jmp	LBB0_10
LBB0_11:
	movq	(%r12), %rax
	movq	%r12, %rdi
	callq	*(%rax)
	testq	%rax, %rax
	jne	LBB0_13
## %bb.12:
	movq	8(%r14), %rdi
	callq	*48(%r14)
LBB0_13:
	movq	%r14, %rdi
	callq	*40(%r14)
	movq	80(%r14), %rax
	movq	(%rax), %rcx
	cmpq	$0, 16(%rcx)
	je	LBB0_19
## %bb.14:
	movl	8(%rcx), %ecx
	movl	%ecx, 32(%r15)
	movl	8(%rax), %edi
	callq	_IS_FPGA_MAXIMUS_DC
	testq	%rax, %rax
	jne	LBB0_20
## %bb.15:
	movq	56(%r15), %rdi
	testq	%rdi, %rdi
	je	LBB0_18
## %bb.16:
	cmpq	$0, 48(%r15)
	je	LBB0_18
## %bb.17:
	movq	(%rdi), %rax
	movq	80(%r14), %rcx
	movq	(%rcx), %rcx
	movl	8(%rcx), %esi
	leaq	40(%r15), %rdx
	callq	*(%rax)
	movq	48(%r15), %rdi
	movq	(%rdi), %rax
	movl	40(%r15), %esi
	leaq	36(%r15), %rdx
	callq	*(%rax)
	jmp	LBB0_20
LBB0_19:
	xorl	%edi, %edi
	callq	_ASSERT_CRITICAL
	jmp	LBB0_20
LBB0_18:
	movl	32(%r15), %eax
	movl	%eax, 40(%r15)
	movl	%eax, 36(%r15)
LBB0_20:
	movq	%rbx, -48(%rbp)                 ## 8-byte Spill
	cmpl	$0, (%r14)
	jle	LBB0_26
## %bb.21:
	xorl	%ebx, %ebx
	jmp	LBB0_22
	.p2align	4, 0x90
LBB0_25:                                ##   in Loop: Header=BB0_22 Depth=1
	incq	%rbx
	movslq	(%r14), %rax
	cmpq	%rax, %rbx
	jge	LBB0_26
LBB0_22:                                ## =>This Inner Loop Header: Depth=1
	movq	72(%r14), %rax
	movq	(%rax,%rbx,8), %r13
	movq	8(%r13), %rdi
	movq	(%rdi), %rax
	callq	*8(%rax)
	movq	8(%r13), %rdi
	movq	(%rdi), %rax
	movq	(%rax), %rax
	testq	%rax, %rax
	je	LBB0_25
## %bb.23:                              ##   in Loop: Header=BB0_22 Depth=1
	callq	*%rax
	testq	%rax, %rax
	je	LBB0_25
## %bb.24:                              ##   in Loop: Header=BB0_22 Depth=1
	movl	$1, (%r13)
	jmp	LBB0_25
LBB0_26:
	movq	(%r12), %rax
	movq	%r12, %rdi
	callq	*(%rax)
	testq	%rax, %rax
	jne	LBB0_28
## %bb.27:
	cmpq	$0, 64(%r14)
	je	LBB0_29
LBB0_28:
	movl	60(%r14), %esi
	movq	%r14, %rdi
	callq	*24(%r14)
LBB0_29:
	cmpl	$0, (%r15)
	jle	LBB0_32
## %bb.30:
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_31:                                ## =>This Inner Loop Header: Depth=1
	movq	8(%r15), %rax
	movq	(%rax,%rbx,8), %rdi
	movq	(%rdi), %rax
	callq	*(%rax)
	incq	%rbx
	movslq	(%r15), %rax
	cmpq	%rax, %rbx
	jl	LBB0_31
LBB0_32:
	movq	-48(%rbp), %r15                 ## 8-byte Reload
	testq	%r15, %r15
	je	LBB0_34
## %bb.33:
	movq	8(%r15), %rax
	movq	%r15, %rdi
	callq	*8(%rax)
	movq	8(%r15), %rax
	movq	%r15, %rdi
	callq	*(%rax)
LBB0_34:
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	testq	%rbx, %rbx
	je	LBB0_37
## %bb.35:
	movq	(%rbx), %rax
	movq	%rbx, %rdi
	callq	*8(%rax)
	testq	%r15, %r15
	je	LBB0_37
## %bb.36:
	movq	(%rbx), %rax
	movq	%rbx, %rdi
	callq	*(%rax)
	movl	%eax, (%r15)
LBB0_37:
	movq	_DIO_MEM_PWR_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_REG_WRITE
	cmpl	$0, 56(%r14)
	jne	LBB0_39
## %bb.38:
	movq	_DCCG_GATE_DISABLE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_REG_WRITE
	movq	_DCCG_GATE_DISABLE_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_REG_WRITE
	movq	_DCFCLK_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_DCFCLK_GATE_DIS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_REG_UPDATE
LBB0_39:
	movq	8(%r14), %rdi
	movq	16(%r14), %rax
LBB0_10:
	movl	$1, %esi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmpq	*%rax                           ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_REFCLK_CNTL,4,2                ## @REFCLK_CNTL
	.comm	_DCHUBBUB_GLOBAL_TIMER_CNTL,4,2 ## @DCHUBBUB_GLOBAL_TIMER_CNTL
	.comm	_DCHUBBUB_GLOBAL_TIMER_ENABLE,4,2 ## @DCHUBBUB_GLOBAL_TIMER_ENABLE
	.comm	_DIO_MEM_PWR_CTRL,4,2           ## @DIO_MEM_PWR_CTRL
	.comm	_DCCG_GATE_DISABLE_CNTL,4,2     ## @DCCG_GATE_DISABLE_CNTL
	.comm	_DCCG_GATE_DISABLE_CNTL2,4,2    ## @DCCG_GATE_DISABLE_CNTL2
	.comm	_DCFCLK_CNTL,4,2                ## @DCFCLK_CNTL
	.comm	_DCFCLK_GATE_DIS,4,2            ## @DCFCLK_GATE_DIS
	.no_dead_strip	_dcn10_init_hw
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dcn10_init_hw
_dcn10_init_hw:                         ; @dcn10_init_hw
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldp	x8, x24, [x0, #80]
	ldp	x21, x20, [x24, #64]
	ldr	x23, [x0, #8]
	ldr	x22, [x8]
	ldr	x0, [x0, #96]
	mov	x8, x24
	cbz	x0, LBB0_3
; %bb.1:
	ldr	x8, [x0]
	ldr	x9, [x8]
	mov	x8, x24
	cbz	x9, LBB0_3
; %bb.2:
	blr	x9
	ldr	x8, [x19, #88]
LBB0_3:
	ldr	x8, [x8, #56]
	cbz	x8, LBB0_6
; %bb.4:
	ldr	x8, [x8]
	ldr	x8, [x8, #8]
	cbz	x8, LBB0_6
; %bb.5:
	ldr	x0, [x24, #56]
	blr	x8
LBB0_6:
	ldr	x8, [x19, #80]
	ldr	w0, [x8, #8]
	bl	_IS_FPGA_MAXIMUS_DC
	cbz	x0, LBB0_10
; %bb.7:
Lloh0:
	adrp	x8, _REFCLK_CNTL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _REFCLK_CNTL@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_REG_WRITE
Lloh3:
	adrp	x8, _DCHUBBUB_GLOBAL_TIMER_CNTL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _DCHUBBUB_GLOBAL_TIMER_CNTL@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
Lloh6:
	adrp	x8, _DCHUBBUB_GLOBAL_TIMER_ENABLE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _DCHUBBUB_GLOBAL_TIMER_ENABLE@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	w2, #1
	bl	_REG_UPDATE
Lloh9:
	adrp	x8, _DIO_MEM_PWR_CTRL@GOTPAGE
Lloh10:
	ldr	x8, [x8, _DIO_MEM_PWR_CTRL@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_REG_WRITE
	ldr	w8, [x19, #56]
	cbnz	w8, LBB0_9
; %bb.8:
Lloh12:
	adrp	x8, _DCCG_GATE_DISABLE_CNTL@GOTPAGE
Lloh13:
	ldr	x8, [x8, _DCCG_GATE_DISABLE_CNTL@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_REG_WRITE
Lloh15:
	adrp	x8, _DCCG_GATE_DISABLE_CNTL2@GOTPAGE
Lloh16:
	ldr	x8, [x8, _DCCG_GATE_DISABLE_CNTL2@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_REG_WRITE
Lloh18:
	adrp	x8, _DCFCLK_CNTL@GOTPAGE
Lloh19:
	ldr	x8, [x8, _DCFCLK_CNTL@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
Lloh21:
	adrp	x8, _DCFCLK_GATE_DIS@GOTPAGE
Lloh22:
	ldr	x8, [x8, _DCFCLK_GATE_DIS@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_REG_UPDATE
LBB0_9:
	ldr	x2, [x19, #16]
	mov	x0, x23
	b	LBB0_39
LBB0_10:
	ldr	x8, [x22]
	ldr	x8, [x8]
	mov	x0, x22
	blr	x8
	cbnz	x0, LBB0_12
; %bb.11:
	ldr	x8, [x19, #48]
	ldr	x0, [x19, #8]
	blr	x8
LBB0_12:
	ldr	x8, [x19, #40]
	mov	x0, x19
	blr	x8
	ldr	x8, [x19, #80]
	ldr	x9, [x8]
	ldr	x10, [x9, #16]
	cbz	x10, LBB0_17
; %bb.13:
	ldr	w9, [x9, #8]
	str	w9, [x24, #32]
	ldr	w0, [x8, #8]
	bl	_IS_FPGA_MAXIMUS_DC
	cbnz	x0, LBB0_19
; %bb.14:
	ldr	x0, [x24, #56]
	cbz	x0, LBB0_18
; %bb.15:
	ldr	x8, [x24, #48]
	cbz	x8, LBB0_18
; %bb.16:
	ldr	x8, [x0]
	ldr	x8, [x8]
	ldr	x9, [x19, #80]
	ldr	x9, [x9]
	ldr	w1, [x9, #8]
	add	x2, x24, #40
	blr	x8
	ldr	x0, [x24, #48]
	ldr	x8, [x0]
	ldr	x8, [x8]
	ldr	w1, [x24, #40]
	add	x2, x24, #36
	blr	x8
	b	LBB0_19
LBB0_17:
	mov	w0, #0
	bl	_ASSERT_CRITICAL
	b	LBB0_19
LBB0_18:
	ldr	w8, [x24, #32]
	stp	w8, w8, [x24, #36]
LBB0_19:
	ldr	w8, [x19]
	cmp	w8, #1
	b.lt	LBB0_25
; %bb.20:
	mov	x23, #0
	mov	w25, #1
	b	LBB0_22
LBB0_21:                                ;   in Loop: Header=BB0_22 Depth=1
	add	x23, x23, #1
	ldrsw	x8, [x19]
	cmp	x23, x8
	b.ge	LBB0_25
LBB0_22:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #72]
	ldr	x26, [x8, x23, lsl #3]
	ldr	x0, [x26, #8]
	ldr	x8, [x0]
	ldr	x8, [x8, #8]
	blr	x8
	ldr	x0, [x26, #8]
	ldr	x8, [x0]
	ldr	x8, [x8]
	cbz	x8, LBB0_21
; %bb.23:                               ;   in Loop: Header=BB0_22 Depth=1
	blr	x8
	cbz	x0, LBB0_21
; %bb.24:                               ;   in Loop: Header=BB0_22 Depth=1
	str	w25, [x26]
	b	LBB0_21
LBB0_25:
	ldr	x8, [x22]
	ldr	x8, [x8]
	mov	x0, x22
	blr	x8
	cbnz	x0, LBB0_27
; %bb.26:
	ldr	x8, [x19, #64]
	cbz	x8, LBB0_28
LBB0_27:
	ldr	x8, [x19, #24]
	ldr	w1, [x19, #60]
	mov	x0, x19
	blr	x8
LBB0_28:
	ldr	w8, [x24]
	cmp	w8, #1
	b.lt	LBB0_31
; %bb.29:
	mov	x22, #0
LBB0_30:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x24, #8]
	ldr	x0, [x8, x22, lsl #3]
	ldr	x8, [x0]
	ldr	x8, [x8]
	blr	x8
	add	x22, x22, #1
	ldrsw	x8, [x24]
	cmp	x22, x8
	b.lt	LBB0_30
LBB0_31:
	cbz	x20, LBB0_33
; %bb.32:
	ldr	x8, [x20, #8]
	ldr	x8, [x8, #8]
	mov	x0, x20
	blr	x8
	ldr	x8, [x20, #8]
	ldr	x8, [x8]
	mov	x0, x20
	blr	x8
LBB0_33:
	cbz	x21, LBB0_36
; %bb.34:
	ldr	x8, [x21]
	ldr	x8, [x8, #8]
	mov	x0, x21
	blr	x8
	cbz	x20, LBB0_36
; %bb.35:
	ldr	x8, [x21]
	ldr	x8, [x8]
	mov	x0, x21
	blr	x8
	str	w0, [x20]
LBB0_36:
Lloh24:
	adrp	x8, _DIO_MEM_PWR_CTRL@GOTPAGE
Lloh25:
	ldr	x8, [x8, _DIO_MEM_PWR_CTRL@GOTPAGEOFF]
Lloh26:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_REG_WRITE
	ldr	w8, [x19, #56]
	cbnz	w8, LBB0_38
; %bb.37:
Lloh27:
	adrp	x8, _DCCG_GATE_DISABLE_CNTL@GOTPAGE
Lloh28:
	ldr	x8, [x8, _DCCG_GATE_DISABLE_CNTL@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_REG_WRITE
Lloh30:
	adrp	x8, _DCCG_GATE_DISABLE_CNTL2@GOTPAGE
Lloh31:
	ldr	x8, [x8, _DCCG_GATE_DISABLE_CNTL2@GOTPAGEOFF]
Lloh32:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_REG_WRITE
Lloh33:
	adrp	x8, _DCFCLK_CNTL@GOTPAGE
Lloh34:
	ldr	x8, [x8, _DCFCLK_CNTL@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
Lloh36:
	adrp	x8, _DCFCLK_GATE_DIS@GOTPAGE
Lloh37:
	ldr	x8, [x8, _DCFCLK_GATE_DIS@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_REG_UPDATE
LBB0_38:
	ldp	x0, x2, [x19, #8]
LBB0_39:
	mov	w1, #1
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	br	x2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.cfi_endproc
                                        ; -- End function
	.comm	_REFCLK_CNTL,4,2                ; @REFCLK_CNTL
	.comm	_DCHUBBUB_GLOBAL_TIMER_CNTL,4,2 ; @DCHUBBUB_GLOBAL_TIMER_CNTL
	.comm	_DCHUBBUB_GLOBAL_TIMER_ENABLE,4,2 ; @DCHUBBUB_GLOBAL_TIMER_ENABLE
	.comm	_DIO_MEM_PWR_CTRL,4,2           ; @DIO_MEM_PWR_CTRL
	.comm	_DCCG_GATE_DISABLE_CNTL,4,2     ; @DCCG_GATE_DISABLE_CNTL
	.comm	_DCCG_GATE_DISABLE_CNTL2,4,2    ; @DCCG_GATE_DISABLE_CNTL2
	.comm	_DCFCLK_CNTL,4,2                ; @DCFCLK_CNTL
	.comm	_DCFCLK_GATE_DIS,4,2            ; @DCFCLK_GATE_DIS
	.no_dead_strip	_dcn10_init_hw
.subsections_via_symbols
