	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function max30100_chip_init
_max30100_chip_init:                    ## @max30100_chip_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	callq	_max30100_led_init
	testl	%eax, %eax
	jne	LBB0_3
## %bb.1:
	movl	(%rbx), %edi
	movq	_MAX30100_REG_SPO2_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MAX30100_REG_SPO2_CONFIG_HI_RES_EN@GOTPCREL(%rip), %rax
	movq	_MAX30100_REG_SPO2_CONFIG_100HZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	callq	_regmap_write
	testl	%eax, %eax
	jne	LBB0_3
## %bb.2:
	movl	(%rbx), %edi
	movq	_MAX30100_REG_MODE_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MAX30100_REG_MODE_CONFIG_MODE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_MAX30100_REG_MODE_CONFIG_MODE_HR_EN@GOTPCREL(%rip), %rax
	movq	_MAX30100_REG_MODE_CONFIG_MODE_SPO2_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	callq	_regmap_update_bits
	testl	%eax, %eax
	je	LBB0_4
LBB0_3:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
LBB0_4:
	movl	(%rbx), %edi
	movq	_MAX30100_REG_INT_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MAX30100_REG_INT_ENABLE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_MAX30100_REG_INT_ENABLE_FIFO_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_MAX30100_REG_INT_ENABLE_MASK_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	movl	%eax, %ecx
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_regmap_update_bits             ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_MAX30100_REG_SPO2_CONFIG,4,2   ## @MAX30100_REG_SPO2_CONFIG
	.comm	_MAX30100_REG_SPO2_CONFIG_HI_RES_EN,4,2 ## @MAX30100_REG_SPO2_CONFIG_HI_RES_EN
	.comm	_MAX30100_REG_SPO2_CONFIG_100HZ,4,2 ## @MAX30100_REG_SPO2_CONFIG_100HZ
	.comm	_MAX30100_REG_MODE_CONFIG,4,2   ## @MAX30100_REG_MODE_CONFIG
	.comm	_MAX30100_REG_MODE_CONFIG_MODE_MASK,4,2 ## @MAX30100_REG_MODE_CONFIG_MODE_MASK
	.comm	_MAX30100_REG_MODE_CONFIG_MODE_HR_EN,4,2 ## @MAX30100_REG_MODE_CONFIG_MODE_HR_EN
	.comm	_MAX30100_REG_MODE_CONFIG_MODE_SPO2_EN,4,2 ## @MAX30100_REG_MODE_CONFIG_MODE_SPO2_EN
	.comm	_MAX30100_REG_INT_ENABLE,4,2    ## @MAX30100_REG_INT_ENABLE
	.comm	_MAX30100_REG_INT_ENABLE_MASK,4,2 ## @MAX30100_REG_INT_ENABLE_MASK
	.comm	_MAX30100_REG_INT_ENABLE_FIFO_EN,4,2 ## @MAX30100_REG_INT_ENABLE_FIFO_EN
	.comm	_MAX30100_REG_INT_ENABLE_MASK_SHIFT,4,2 ## @MAX30100_REG_INT_ENABLE_MASK_SHIFT
	.no_dead_strip	_max30100_chip_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function max30100_chip_init
_max30100_chip_init:                    ; @max30100_chip_init
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_max30100_led_init
	cbnz	w0, LBB0_3
; %bb.1:
	ldr	w0, [x19]
Lloh0:
	adrp	x8, _MAX30100_REG_SPO2_CONFIG@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MAX30100_REG_SPO2_CONFIG@GOTPAGEOFF]
Lloh2:
	adrp	x9, _MAX30100_REG_SPO2_CONFIG_HI_RES_EN@GOTPAGE
Lloh3:
	ldr	x9, [x9, _MAX30100_REG_SPO2_CONFIG_HI_RES_EN@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
Lloh5:
	ldr	w8, [x9]
Lloh6:
	adrp	x9, _MAX30100_REG_SPO2_CONFIG_100HZ@GOTPAGE
Lloh7:
	ldr	x9, [x9, _MAX30100_REG_SPO2_CONFIG_100HZ@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	orr	w2, w9, w8
	bl	_regmap_write
	cbnz	w0, LBB0_3
; %bb.2:
Lloh9:
	adrp	x8, _MAX30100_REG_MODE_CONFIG@GOTPAGE
Lloh10:
	ldr	x8, [x8, _MAX30100_REG_MODE_CONFIG@GOTPAGEOFF]
	ldr	w0, [x19]
Lloh11:
	ldr	w1, [x8]
Lloh12:
	adrp	x8, _MAX30100_REG_MODE_CONFIG_MODE_MASK@GOTPAGE
Lloh13:
	ldr	x8, [x8, _MAX30100_REG_MODE_CONFIG_MODE_MASK@GOTPAGEOFF]
Lloh14:
	adrp	x9, _MAX30100_REG_MODE_CONFIG_MODE_HR_EN@GOTPAGE
Lloh15:
	ldr	x9, [x9, _MAX30100_REG_MODE_CONFIG_MODE_HR_EN@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
Lloh17:
	ldr	w8, [x9]
Lloh18:
	adrp	x9, _MAX30100_REG_MODE_CONFIG_MODE_SPO2_EN@GOTPAGE
Lloh19:
	ldr	x9, [x9, _MAX30100_REG_MODE_CONFIG_MODE_SPO2_EN@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	orr	w3, w9, w8
	bl	_regmap_update_bits
	cbz	w0, LBB0_4
LBB0_3:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_4:
	ldr	w0, [x19]
Lloh21:
	adrp	x8, _MAX30100_REG_INT_ENABLE@GOTPAGE
Lloh22:
	ldr	x8, [x8, _MAX30100_REG_INT_ENABLE@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
Lloh24:
	adrp	x8, _MAX30100_REG_INT_ENABLE_MASK@GOTPAGE
Lloh25:
	ldr	x8, [x8, _MAX30100_REG_INT_ENABLE_MASK@GOTPAGEOFF]
Lloh26:
	ldr	w2, [x8]
Lloh27:
	adrp	x8, _MAX30100_REG_INT_ENABLE_FIFO_EN@GOTPAGE
Lloh28:
	ldr	x8, [x8, _MAX30100_REG_INT_ENABLE_FIFO_EN@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
Lloh30:
	adrp	x9, _MAX30100_REG_INT_ENABLE_MASK_SHIFT@GOTPAGE
Lloh31:
	ldr	x9, [x9, _MAX30100_REG_INT_ENABLE_MASK_SHIFT@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	lsl	w3, w8, w9
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_regmap_update_bits
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh4
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh16
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.cfi_endproc
                                        ; -- End function
	.comm	_MAX30100_REG_SPO2_CONFIG,4,2   ; @MAX30100_REG_SPO2_CONFIG
	.comm	_MAX30100_REG_SPO2_CONFIG_HI_RES_EN,4,2 ; @MAX30100_REG_SPO2_CONFIG_HI_RES_EN
	.comm	_MAX30100_REG_SPO2_CONFIG_100HZ,4,2 ; @MAX30100_REG_SPO2_CONFIG_100HZ
	.comm	_MAX30100_REG_MODE_CONFIG,4,2   ; @MAX30100_REG_MODE_CONFIG
	.comm	_MAX30100_REG_MODE_CONFIG_MODE_MASK,4,2 ; @MAX30100_REG_MODE_CONFIG_MODE_MASK
	.comm	_MAX30100_REG_MODE_CONFIG_MODE_HR_EN,4,2 ; @MAX30100_REG_MODE_CONFIG_MODE_HR_EN
	.comm	_MAX30100_REG_MODE_CONFIG_MODE_SPO2_EN,4,2 ; @MAX30100_REG_MODE_CONFIG_MODE_SPO2_EN
	.comm	_MAX30100_REG_INT_ENABLE,4,2    ; @MAX30100_REG_INT_ENABLE
	.comm	_MAX30100_REG_INT_ENABLE_MASK,4,2 ; @MAX30100_REG_INT_ENABLE_MASK
	.comm	_MAX30100_REG_INT_ENABLE_FIFO_EN,4,2 ; @MAX30100_REG_INT_ENABLE_FIFO_EN
	.comm	_MAX30100_REG_INT_ENABLE_MASK_SHIFT,4,2 ; @MAX30100_REG_INT_ENABLE_MASK_SHIFT
	.no_dead_strip	_max30100_chip_init
.subsections_via_symbols
