	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function icl_get_cdclk
_icl_get_cdclk:                         ## @icl_get_cdclk
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rsi, %rbx
	movq	%rdi, %r14
	movl	$50000, (%rsi)                  ## imm = 0xC350
	movq	_SKL_DSSM@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	_ICL_DSSM_CDCLK_PLL_REFCLK_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%eax, %ecx
	addl	$-128, %ecx
	cmpl	$3, %ecx
	jae	LBB0_1
## %bb.2:
	movslq	%ecx, %rax
	leaq	l_switch.table.icl_get_cdclk(%rip), %rcx
	movl	(%rcx,%rax,4), %eax
	jmp	LBB0_3
LBB0_1:
	movl	%eax, %edi
	callq	_MISSING_CASE
	movl	$24000, %eax                    ## imm = 0x5DC0
LBB0_3:
	movl	%eax, 4(%rbx)
	movq	_BXT_DE_PLL_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	_BXT_DE_PLL_PLL_ENABLE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_5
## %bb.4:
	movq	_BXT_DE_PLL_LOCK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_5
## %bb.6:
	movq	_BXT_DE_PLL_RATIO_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	imull	4(%rbx), %eax
	movl	%eax, 8(%rbx)
	movq	_CDCLK_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_I915_READ
	movq	_BXT_CDCLK_CD2X_DIV_SEL_MASK@GOTPCREL(%rip), %rcx
	xorl	%edi, %edi
	andl	(%rcx), %eax
	setne	%dil
	callq	_WARN_ON
	movl	8(%rbx), %eax
	movl	%eax, %esi
	shrl	$31, %esi
	addl	%eax, %esi
	sarl	%esi
	jmp	LBB0_7
LBB0_5:
	movl	$0, 8(%rbx)
	movl	(%rbx), %esi
LBB0_7:
	movl	%esi, 12(%rbx)
	movq	%r14, %rdi
	callq	_icl_calc_voltage_level
	movl	%eax, 16(%rbx)
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_SKL_DSSM,4,2                   ## @SKL_DSSM
	.comm	_ICL_DSSM_CDCLK_PLL_REFCLK_MASK,4,2 ## @ICL_DSSM_CDCLK_PLL_REFCLK_MASK
	.comm	_BXT_DE_PLL_ENABLE,4,2          ## @BXT_DE_PLL_ENABLE
	.comm	_BXT_DE_PLL_PLL_ENABLE,4,2      ## @BXT_DE_PLL_PLL_ENABLE
	.comm	_BXT_DE_PLL_LOCK,4,2            ## @BXT_DE_PLL_LOCK
	.comm	_BXT_DE_PLL_RATIO_MASK,4,2      ## @BXT_DE_PLL_RATIO_MASK
	.comm	_CDCLK_CTL,4,2                  ## @CDCLK_CTL
	.comm	_BXT_CDCLK_CD2X_DIV_SEL_MASK,4,2 ## @BXT_CDCLK_CD2X_DIV_SEL_MASK
	.no_dead_strip	_icl_get_cdclk
	.section	__TEXT,__const
	.p2align	2                               ## @switch.table.icl_get_cdclk
l_switch.table.icl_get_cdclk:
	.long	38400                           ## 0x9600
	.long	24000                           ## 0x5dc0
	.long	19200                           ## 0x4b00

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function icl_get_cdclk
_icl_get_cdclk:                         ; @icl_get_cdclk
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x1
	mov	x20, x0
	mov	w8, #50000
	str	w8, [x1]
Lloh0:
	adrp	x8, _SKL_DSSM@GOTPAGE
Lloh1:
	ldr	x8, [x8, _SKL_DSSM@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_I915_READ
Lloh3:
	adrp	x8, _ICL_DSSM_CDCLK_PLL_REFCLK_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _ICL_DSSM_CDCLK_PLL_REFCLK_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	and	w8, w8, w0
	sub	w8, w8, #128
	cmp	w8, #3
	b.hs	LBB0_2
; %bb.1:
Lloh6:
	adrp	x9, l_switch.table.icl_get_cdclk@PAGE
Lloh7:
	add	x9, x9, l_switch.table.icl_get_cdclk@PAGEOFF
	ldr	w8, [x9, w8, sxtw #2]
	b	LBB0_3
LBB0_2:
	bl	_MISSING_CASE
	mov	w8, #24000
LBB0_3:
	str	w8, [x19, #4]
Lloh8:
	adrp	x8, _BXT_DE_PLL_ENABLE@GOTPAGE
Lloh9:
	ldr	x8, [x8, _BXT_DE_PLL_ENABLE@GOTPAGEOFF]
Lloh10:
	ldr	w0, [x8]
	bl	_I915_READ
Lloh11:
	adrp	x8, _BXT_DE_PLL_PLL_ENABLE@GOTPAGE
Lloh12:
	ldr	x8, [x8, _BXT_DE_PLL_PLL_ENABLE@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_6
; %bb.4:
Lloh14:
	adrp	x8, _BXT_DE_PLL_LOCK@GOTPAGE
Lloh15:
	ldr	x8, [x8, _BXT_DE_PLL_LOCK@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_6
; %bb.5:
Lloh17:
	adrp	x8, _BXT_DE_PLL_RATIO_MASK@GOTPAGE
Lloh18:
	ldr	x8, [x8, _BXT_DE_PLL_RATIO_MASK@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
	and	w8, w8, w0
	ldr	w9, [x19, #4]
	mul	w8, w8, w9
	str	w8, [x19, #8]
Lloh20:
	adrp	x8, _CDCLK_CTL@GOTPAGE
Lloh21:
	ldr	x8, [x8, _CDCLK_CTL@GOTPAGEOFF]
Lloh22:
	ldr	w0, [x8]
	bl	_I915_READ
Lloh23:
	adrp	x8, _BXT_CDCLK_CD2X_DIV_SEL_MASK@GOTPAGE
Lloh24:
	ldr	x8, [x8, _BXT_CDCLK_CD2X_DIV_SEL_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
	tst	w8, w0
	cset	w0, ne
	bl	_WARN_ON
	ldr	w8, [x19, #8]
	cmp	w8, #0
	cinc	w8, w8, lt
	asr	w1, w8, #1
	b	LBB0_7
LBB0_6:
	str	wzr, [x19, #8]
	ldr	w1, [x19]
LBB0_7:
	str	w1, [x19, #12]
	mov	x0, x20
	bl	_icl_calc_voltage_level
	str	w0, [x19, #16]
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.cfi_endproc
                                        ; -- End function
	.comm	_SKL_DSSM,4,2                   ; @SKL_DSSM
	.comm	_ICL_DSSM_CDCLK_PLL_REFCLK_MASK,4,2 ; @ICL_DSSM_CDCLK_PLL_REFCLK_MASK
	.comm	_BXT_DE_PLL_ENABLE,4,2          ; @BXT_DE_PLL_ENABLE
	.comm	_BXT_DE_PLL_PLL_ENABLE,4,2      ; @BXT_DE_PLL_PLL_ENABLE
	.comm	_BXT_DE_PLL_LOCK,4,2            ; @BXT_DE_PLL_LOCK
	.comm	_BXT_DE_PLL_RATIO_MASK,4,2      ; @BXT_DE_PLL_RATIO_MASK
	.comm	_CDCLK_CTL,4,2                  ; @CDCLK_CTL
	.comm	_BXT_CDCLK_CD2X_DIV_SEL_MASK,4,2 ; @BXT_CDCLK_CD2X_DIV_SEL_MASK
	.no_dead_strip	_icl_get_cdclk
	.section	__TEXT,__const
	.p2align	2                               ; @switch.table.icl_get_cdclk
l_switch.table.icl_get_cdclk:
	.long	38400                           ; 0x9600
	.long	24000                           ; 0x5dc0
	.long	19200                           ; 0x4b00

.subsections_via_symbols
