	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function a2xx_hw_init
_a2xx_hw_init:                          ## @a2xx_hw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	callq	_to_adreno_gpu
	movq	%rax, %r14
	movq	8(%r12), %rax
	movl	(%rax), %edi
	leaq	-48(%rbp), %rsi
	leaq	-44(%rbp), %rdx
	callq	_msm_gpummu_params
	movl	(%r12), %esi
	leaq	L_.str(%rip), %rdi
	callq	_DBG
	movq	_REG_AXXX_CP_ME_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AXXX_CP_ME_CNTL_HALT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_gpu_write
	movq	_REG_A2XX_RBBM_PM_OVERRIDE1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$-2, %edx
	callq	_gpu_write
	movq	_REG_A2XX_RBBM_PM_OVERRIDE2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$-1, %edx
	callq	_gpu_write
	movq	_REG_A2XX_RBBM_SOFT_RESET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	movl	$-1, %edx
	callq	_gpu_write
	movl	$30, %edi
	callq	_msleep
	movl	(%rbx), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movq	%r14, -56(%rbp)                 ## 8-byte Spill
	movq	%r14, %rdi
	callq	_adreno_is_a225
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	_REG_A2XX_SQ_FLOW_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$402653184, %edx                ## imm = 0x18000000
	callq	_gpu_write
LBB0_2:
	movq	_REG_A2XX_RBBM_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$17474, %edx                    ## imm = 0x4442
	callq	_gpu_write
	movq	_REG_A2XX_MH_MMU_MPU_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movq	_REG_A2XX_MH_MMU_MPU_END@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$-4096, %edx                    ## imm = 0xF000
	callq	_gpu_write
	movq	_REG_A2XX_MH_MMU_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_A2XX_MH_MMU_CONFIG_MMU_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	_BEH_TRAN_RNG@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	callq	_A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR
	orl	%eax, %r13d
	movl	(%r14), %edi
	callq	_A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR
	movl	%eax, %ebx
	movl	(%r14), %edi
	callq	_A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR
	orl	%eax, %ebx
	orl	%r13d, %ebx
	movl	(%r14), %edi
	callq	_A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR
	movl	%eax, %r13d
	movl	(%r14), %edi
	callq	_A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR
	orl	%eax, %r13d
	movl	(%r14), %edi
	callq	_A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR
	orl	%eax, %r13d
	orl	%ebx, %r13d
	movl	(%r14), %edi
	callq	_A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR
	movl	%eax, %ebx
	movl	(%r14), %edi
	callq	_A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR
	orl	%eax, %ebx
	movl	(%r14), %edi
	callq	_A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR
	orl	%eax, %ebx
	movl	(%r14), %edi
	callq	_A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR
	orl	%eax, %ebx
	orl	%r13d, %ebx
	movl	(%r14), %edi
	callq	_A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR
	orl	%eax, %ebx
	movq	%r12, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_gpu_write
	movq	_REG_A2XX_MH_MMU_VA_RANGE@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_SZ_16M@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$4095, %edi                     ## imm = 0xFFF
	callq	_A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS
	orl	%eax, %ebx
	movq	%r12, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_gpu_write
	movq	_REG_A2XX_MH_MMU_PT_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-48(%rbp), %edx
	movq	%r12, %rdi
	callq	_gpu_write
	movq	_REG_A2XX_MH_MMU_TRAN_ERROR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-44(%rbp), %edx
	movq	%r12, %rdi
	callq	_gpu_write
	movq	_REG_A2XX_MH_MMU_INVALIDATE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL@GOTPCREL(%rip), %rax
	movq	_A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	%r12, %rdi
	callq	_gpu_write
	movq	_REG_A2XX_MH_ARBITER_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	$16, %edi
	callq	_A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT
	movl	%eax, %ebx
	movq	_A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	$1, %edi
	callq	_A2XX_MH_ARBITER_CONFIG_PAGE_SIZE
	orl	%eax, %ebx
	movq	_A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	$8, %edi
	callq	_A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT
	orl	%eax, %ebx
	movq	_A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	%r12, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_gpu_write
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	callq	_adreno_is_a20x
	testl	%eax, %eax
	jne	LBB0_4
## %bb.3:
	movq	_REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$208647, %edx                   ## imm = 0x32F07
	callq	_gpu_write
LBB0_4:
	movq	_REG_A2XX_SQ_VS_PROGRAM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movq	_REG_A2XX_SQ_PS_PROGRAM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movq	_REG_A2XX_RBBM_PM_OVERRIDE1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movq	_REG_A2XX_RBBM_PM_OVERRIDE2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movq	_REG_A2XX_RBBM_DEBUG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$524288, %edx                   ## imm = 0x80000
	callq	_gpu_write
	movq	_REG_A2XX_RBBM_INT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_A2XX_RBBM_INT_CNTL_RDERR_INT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_gpu_write
	movq	_AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK@GOTPCREL(%rip), %rax
	movq	_AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	_AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_AXXX_CP_INT_CNTL_IB_ERROR_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_REG_AXXX_CP_INT_CNTL@GOTPCREL(%rip), %rax
	movq	_AXXX_CP_INT_CNTL_IB1_INT_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movl	(%rax), %esi
	movq	_AXXX_CP_INT_CNTL_RB_INT_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	%r12, %rdi
	callq	_gpu_write
	movq	_REG_A2XX_SQ_INT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movq	_REG_A2XX_MH_INTERRUPT_MASK@GOTPCREL(%rip), %rax
	movq	_A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR@GOTPCREL(%rip), %rcx
	movq	_A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	movl	(%rax), %esi
	movq	_A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	%r12, %rdi
	callq	_gpu_write
	movq	_SZ_16K@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	(%rbx), %ecx
	leal	(,%rax,8), %esi
	movl	$3, %edx
	cmpl	%ecx, %esi
	je	LBB0_7
## %bb.5:
	movl	%eax, %esi
	shll	$4, %esi
	movl	$4, %edx
	cmpl	%ecx, %esi
	je	LBB0_7
## %bb.6:
	shll	$5, %eax
	xorl	%esi, %esi
	cmpl	%ecx, %eax
	sete	%sil
	movl	$6, %edx
	subl	%esi, %edx
LBB0_7:
	movq	_REG_A2XX_RB_EDRAM_INFO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_gpu_write
	movq	%r12, %rdi
	callq	_adreno_hw_init
	movl	%eax, %ecx
	testl	%eax, %eax
	jne	LBB0_15
## %bb.8:
	movq	8(%rbx), %rax
	movq	_ADRENO_FW_PM4@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	(%rax,%rcx,8), %rax
	movq	8(%rax), %r14
	movl	(%rax), %r15d
	movl	4(%r14), %esi
	leaq	L_.str.1(%rip), %rdi
	callq	_DBG
	movq	_REG_AXXX_CP_DEBUG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_gpu_write
	movq	_REG_AXXX_CP_ME_RAM_WADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	cmpl	$8, %r15d
	jl	LBB0_11
## %bb.9:
	shrq	$2, %r15
	movl	$1, %ebx
	movq	_REG_AXXX_CP_ME_RAM_DATA@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_10:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r13), %esi
	movl	(%r14,%rbx,4), %edx
	movq	%r12, %rdi
	callq	_gpu_write
	incq	%rbx
	cmpq	%rbx, %r15
	jne	LBB0_10
LBB0_11:
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movq	8(%rax), %rax
	movq	_ADRENO_FW_PFP@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	(%rax,%rcx,8), %rax
	movq	8(%rax), %r15
	movl	(%rax), %r13d
	movl	20(%r15), %esi
	leaq	L_.str.2(%rip), %rdi
	callq	_DBG
	movq	_REG_A2XX_CP_PFP_UCODE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	cmpl	$8, %r13d
	jl	LBB0_14
## %bb.12:
	shrq	$2, %r13
	movl	$1, %ebx
	movq	_REG_A2XX_CP_PFP_UCODE_DATA@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_13:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %esi
	movl	(%r15,%rbx,4), %edx
	movq	%r12, %rdi
	callq	_gpu_write
	incq	%rbx
	cmpq	%rbx, %r13
	jne	LBB0_13
LBB0_14:
	movq	_REG_AXXX_CP_QUEUE_THRESHOLDS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$788484, %edx                   ## imm = 0xC0804
	callq	_gpu_write
	movq	_REG_AXXX_CP_ME_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_gpu_write
	movq	%r12, %rdi
	callq	_a2xx_me_init
	movq	_EINVAL@GOTPCREL(%rip), %rdx
	xorl	%ecx, %ecx
	subl	(%rdx), %ecx
	testq	%rax, %rax
	movl	$0, %eax
	cmovnel	%eax, %ecx
LBB0_15:
	movl	%ecx, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"%s"

	.comm	_REG_AXXX_CP_ME_CNTL,4,2        ## @REG_AXXX_CP_ME_CNTL
	.comm	_AXXX_CP_ME_CNTL_HALT,4,2       ## @AXXX_CP_ME_CNTL_HALT
	.comm	_REG_A2XX_RBBM_PM_OVERRIDE1,4,2 ## @REG_A2XX_RBBM_PM_OVERRIDE1
	.comm	_REG_A2XX_RBBM_PM_OVERRIDE2,4,2 ## @REG_A2XX_RBBM_PM_OVERRIDE2
	.comm	_REG_A2XX_RBBM_SOFT_RESET,4,2   ## @REG_A2XX_RBBM_SOFT_RESET
	.comm	_REG_A2XX_SQ_FLOW_CONTROL,4,2   ## @REG_A2XX_SQ_FLOW_CONTROL
	.comm	_REG_A2XX_RBBM_CNTL,4,2         ## @REG_A2XX_RBBM_CNTL
	.comm	_REG_A2XX_MH_MMU_MPU_BASE,4,2   ## @REG_A2XX_MH_MMU_MPU_BASE
	.comm	_REG_A2XX_MH_MMU_MPU_END,4,2    ## @REG_A2XX_MH_MMU_MPU_END
	.comm	_REG_A2XX_MH_MMU_CONFIG,4,2     ## @REG_A2XX_MH_MMU_CONFIG
	.comm	_A2XX_MH_MMU_CONFIG_MMU_ENABLE,4,2 ## @A2XX_MH_MMU_CONFIG_MMU_ENABLE
	.comm	_BEH_TRAN_RNG,4,2               ## @BEH_TRAN_RNG
	.comm	_REG_A2XX_MH_MMU_VA_RANGE,4,2   ## @REG_A2XX_MH_MMU_VA_RANGE
	.comm	_SZ_16M,4,2                     ## @SZ_16M
	.comm	_REG_A2XX_MH_MMU_PT_BASE,4,2    ## @REG_A2XX_MH_MMU_PT_BASE
	.comm	_REG_A2XX_MH_MMU_TRAN_ERROR,4,2 ## @REG_A2XX_MH_MMU_TRAN_ERROR
	.comm	_REG_A2XX_MH_MMU_INVALIDATE,4,2 ## @REG_A2XX_MH_MMU_INVALIDATE
	.comm	_A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL,4,2 ## @A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL
	.comm	_A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC,4,2 ## @A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC
	.comm	_REG_A2XX_MH_ARBITER_CONFIG,4,2 ## @REG_A2XX_MH_ARBITER_CONFIG
	.comm	_A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE,4,2 ## @A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE
	.comm	_A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE,4,2 ## @A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE
	.comm	_A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE,4,2 ## @A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE
	.comm	_A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE,4,2 ## @A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE
	.comm	_A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE,4,2 ## @A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE
	.comm	_A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE,4,2 ## @A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE
	.comm	_A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE,4,2 ## @A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE
	.comm	_A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE,4,2 ## @A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE
	.comm	_A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE,4,2 ## @A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE
	.comm	_A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE,4,2 ## @A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE
	.comm	_REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1,4,2 ## @REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1
	.comm	_REG_A2XX_SQ_VS_PROGRAM,4,2     ## @REG_A2XX_SQ_VS_PROGRAM
	.comm	_REG_A2XX_SQ_PS_PROGRAM,4,2     ## @REG_A2XX_SQ_PS_PROGRAM
	.comm	_REG_A2XX_RBBM_DEBUG,4,2        ## @REG_A2XX_RBBM_DEBUG
	.comm	_REG_A2XX_RBBM_INT_CNTL,4,2     ## @REG_A2XX_RBBM_INT_CNTL
	.comm	_A2XX_RBBM_INT_CNTL_RDERR_INT_MASK,4,2 ## @A2XX_RBBM_INT_CNTL_RDERR_INT_MASK
	.comm	_REG_AXXX_CP_INT_CNTL,4,2       ## @REG_AXXX_CP_INT_CNTL
	.comm	_AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK,4,2 ## @AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK
	.comm	_AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK,4,2 ## @AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK
	.comm	_AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK,4,2 ## @AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK
	.comm	_AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK,4,2 ## @AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK
	.comm	_AXXX_CP_INT_CNTL_IB_ERROR_MASK,4,2 ## @AXXX_CP_INT_CNTL_IB_ERROR_MASK
	.comm	_AXXX_CP_INT_CNTL_IB1_INT_MASK,4,2 ## @AXXX_CP_INT_CNTL_IB1_INT_MASK
	.comm	_AXXX_CP_INT_CNTL_RB_INT_MASK,4,2 ## @AXXX_CP_INT_CNTL_RB_INT_MASK
	.comm	_REG_A2XX_SQ_INT_CNTL,4,2       ## @REG_A2XX_SQ_INT_CNTL
	.comm	_REG_A2XX_MH_INTERRUPT_MASK,4,2 ## @REG_A2XX_MH_INTERRUPT_MASK
	.comm	_A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR,4,2 ## @A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR
	.comm	_A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR,4,2 ## @A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR
	.comm	_A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT,4,2 ## @A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT
	.comm	_SZ_16K,4,2                     ## @SZ_16K
	.comm	_REG_A2XX_RB_EDRAM_INFO,4,2     ## @REG_A2XX_RB_EDRAM_INFO
	.comm	_ADRENO_FW_PM4,8,3              ## @ADRENO_FW_PM4
L_.str.1:                               ## @.str.1
	.asciz	"loading PM4 ucode version: %x"

	.comm	_REG_AXXX_CP_DEBUG,4,2          ## @REG_AXXX_CP_DEBUG
	.comm	_AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE,4,2 ## @AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE
	.comm	_REG_AXXX_CP_ME_RAM_WADDR,4,2   ## @REG_AXXX_CP_ME_RAM_WADDR
	.comm	_REG_AXXX_CP_ME_RAM_DATA,4,2    ## @REG_AXXX_CP_ME_RAM_DATA
	.comm	_ADRENO_FW_PFP,8,3              ## @ADRENO_FW_PFP
L_.str.2:                               ## @.str.2
	.asciz	"loading PFP ucode version: %x"

	.comm	_REG_A2XX_CP_PFP_UCODE_ADDR,4,2 ## @REG_A2XX_CP_PFP_UCODE_ADDR
	.comm	_REG_A2XX_CP_PFP_UCODE_DATA,4,2 ## @REG_A2XX_CP_PFP_UCODE_DATA
	.comm	_REG_AXXX_CP_QUEUE_THRESHOLDS,4,2 ## @REG_AXXX_CP_QUEUE_THRESHOLDS
	.comm	_EINVAL,4,2                     ## @EINVAL
	.no_dead_strip	_a2xx_hw_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function a2xx_hw_init
_a2xx_hw_init:                          ; @a2xx_hw_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	bl	_to_adreno_gpu
	mov	x20, x0
	ldr	x8, [x19, #8]
	ldr	w0, [x8]
	add	x1, sp, #12
	add	x2, sp, #8
	bl	_msm_gpummu_params
	ldr	w1, [x19]
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DBG
Lloh2:
	adrp	x22, _REG_AXXX_CP_ME_CNTL@GOTPAGE
Lloh3:
	ldr	x22, [x22, _REG_AXXX_CP_ME_CNTL@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh4:
	adrp	x8, _AXXX_CP_ME_CNTL_HALT@GOTPAGE
Lloh5:
	ldr	x8, [x8, _AXXX_CP_ME_CNTL_HALT@GOTPAGEOFF]
Lloh6:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_gpu_write
Lloh7:
	adrp	x23, _REG_A2XX_RBBM_PM_OVERRIDE1@GOTPAGE
Lloh8:
	ldr	x23, [x23, _REG_A2XX_RBBM_PM_OVERRIDE1@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x19
	mov	w2, #-2
	bl	_gpu_write
Lloh9:
	adrp	x24, _REG_A2XX_RBBM_PM_OVERRIDE2@GOTPAGE
Lloh10:
	ldr	x24, [x24, _REG_A2XX_RBBM_PM_OVERRIDE2@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	x0, x19
	mov	w2, #-1
	bl	_gpu_write
Lloh11:
	adrp	x21, _REG_A2XX_RBBM_SOFT_RESET@GOTPAGE
Lloh12:
	ldr	x21, [x21, _REG_A2XX_RBBM_SOFT_RESET@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	mov	w2, #-1
	bl	_gpu_write
	mov	w0, #30
	bl	_msleep
	ldr	w1, [x21]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
	mov	x0, x20
	bl	_adreno_is_a225
	cbz	x0, LBB0_2
; %bb.1:
Lloh13:
	adrp	x8, _REG_A2XX_SQ_FLOW_CONTROL@GOTPAGE
Lloh14:
	ldr	x8, [x8, _REG_A2XX_SQ_FLOW_CONTROL@GOTPAGEOFF]
Lloh15:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #402653184
	bl	_gpu_write
LBB0_2:
Lloh16:
	adrp	x8, _REG_A2XX_RBBM_CNTL@GOTPAGE
Lloh17:
	ldr	x8, [x8, _REG_A2XX_RBBM_CNTL@GOTPAGEOFF]
Lloh18:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #17474
	bl	_gpu_write
Lloh19:
	adrp	x8, _REG_A2XX_MH_MMU_MPU_BASE@GOTPAGE
Lloh20:
	ldr	x8, [x8, _REG_A2XX_MH_MMU_MPU_BASE@GOTPAGEOFF]
Lloh21:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
Lloh22:
	adrp	x8, _REG_A2XX_MH_MMU_MPU_END@GOTPAGE
Lloh23:
	ldr	x8, [x8, _REG_A2XX_MH_MMU_MPU_END@GOTPAGEOFF]
Lloh24:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-4096
	bl	_gpu_write
Lloh25:
	adrp	x8, _REG_A2XX_MH_MMU_CONFIG@GOTPAGE
Lloh26:
	ldr	x8, [x8, _REG_A2XX_MH_MMU_CONFIG@GOTPAGEOFF]
Lloh27:
	ldr	w21, [x8]
Lloh28:
	adrp	x8, _A2XX_MH_MMU_CONFIG_MMU_ENABLE@GOTPAGE
Lloh29:
	ldr	x8, [x8, _A2XX_MH_MMU_CONFIG_MMU_ENABLE@GOTPAGEOFF]
Lloh30:
	ldr	w26, [x8]
Lloh31:
	adrp	x25, _BEH_TRAN_RNG@GOTPAGE
Lloh32:
	ldr	x25, [x25, _BEH_TRAN_RNG@GOTPAGEOFF]
	ldr	w0, [x25]
	bl	_A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR
	orr	w26, w0, w26
	ldr	w0, [x25]
	bl	_A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR
	orr	w26, w26, w0
	ldr	w0, [x25]
	bl	_A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR
	orr	w26, w26, w0
	ldr	w0, [x25]
	bl	_A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR
	orr	w26, w26, w0
	ldr	w0, [x25]
	bl	_A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR
	orr	w26, w26, w0
	ldr	w0, [x25]
	bl	_A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR
	orr	w26, w26, w0
	ldr	w0, [x25]
	bl	_A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR
	orr	w26, w26, w0
	ldr	w0, [x25]
	bl	_A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR
	orr	w26, w26, w0
	ldr	w0, [x25]
	bl	_A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR
	orr	w26, w26, w0
	ldr	w0, [x25]
	bl	_A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR
	orr	w26, w26, w0
	ldr	w0, [x25]
	bl	_A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR
	orr	w2, w26, w0
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
Lloh33:
	adrp	x8, _REG_A2XX_MH_MMU_VA_RANGE@GOTPAGE
Lloh34:
	ldr	x8, [x8, _REG_A2XX_MH_MMU_VA_RANGE@GOTPAGEOFF]
Lloh35:
	ldr	w21, [x8]
Lloh36:
	adrp	x8, _SZ_16M@GOTPAGE
Lloh37:
	ldr	x8, [x8, _SZ_16M@GOTPAGEOFF]
Lloh38:
	ldr	w25, [x8]
	mov	w0, #4095
	bl	_A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS
	orr	w2, w0, w25
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
Lloh39:
	adrp	x8, _REG_A2XX_MH_MMU_PT_BASE@GOTPAGE
Lloh40:
	ldr	x8, [x8, _REG_A2XX_MH_MMU_PT_BASE@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_gpu_write
Lloh42:
	adrp	x8, _REG_A2XX_MH_MMU_TRAN_ERROR@GOTPAGE
Lloh43:
	ldr	x8, [x8, _REG_A2XX_MH_MMU_TRAN_ERROR@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x8]
	ldr	w2, [sp, #8]
	mov	x0, x19
	bl	_gpu_write
Lloh45:
	adrp	x8, _REG_A2XX_MH_MMU_INVALIDATE@GOTPAGE
Lloh46:
	ldr	x8, [x8, _REG_A2XX_MH_MMU_INVALIDATE@GOTPAGEOFF]
Lloh47:
	adrp	x9, _A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL@GOTPAGE
Lloh48:
	ldr	x9, [x9, _A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL@GOTPAGEOFF]
Lloh49:
	ldr	w1, [x8]
Lloh50:
	ldr	w8, [x9]
Lloh51:
	adrp	x9, _A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC@GOTPAGE
Lloh52:
	ldr	x9, [x9, _A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC@GOTPAGEOFF]
Lloh53:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_gpu_write
Lloh54:
	adrp	x8, _REG_A2XX_MH_ARBITER_CONFIG@GOTPAGE
Lloh55:
	ldr	x8, [x8, _REG_A2XX_MH_ARBITER_CONFIG@GOTPAGEOFF]
Lloh56:
	ldr	w21, [x8]
	mov	w0, #16
	bl	_A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT
Lloh57:
	adrp	x8, _A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE@GOTPAGE
Lloh58:
	ldr	x8, [x8, _A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE@GOTPAGEOFF]
Lloh59:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh60:
	adrp	x9, _A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE@GOTPAGE
Lloh61:
	ldr	x9, [x9, _A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE@GOTPAGEOFF]
Lloh62:
	ldr	w9, [x9]
	orr	w25, w8, w9
	mov	w0, #1
	bl	_A2XX_MH_ARBITER_CONFIG_PAGE_SIZE
	orr	w8, w25, w0
Lloh63:
	adrp	x9, _A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE@GOTPAGE
Lloh64:
	ldr	x9, [x9, _A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE@GOTPAGEOFF]
Lloh65:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh66:
	adrp	x9, _A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE@GOTPAGE
Lloh67:
	ldr	x9, [x9, _A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE@GOTPAGEOFF]
Lloh68:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh69:
	adrp	x9, _A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE@GOTPAGE
Lloh70:
	ldr	x9, [x9, _A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE@GOTPAGEOFF]
Lloh71:
	ldr	w9, [x9]
	orr	w25, w8, w9
	mov	w0, #8
	bl	_A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT
	orr	w8, w25, w0
Lloh72:
	adrp	x9, _A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE@GOTPAGE
Lloh73:
	ldr	x9, [x9, _A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE@GOTPAGEOFF]
Lloh74:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh75:
	adrp	x9, _A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE@GOTPAGE
Lloh76:
	ldr	x9, [x9, _A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE@GOTPAGEOFF]
Lloh77:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh78:
	adrp	x9, _A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE@GOTPAGE
Lloh79:
	ldr	x9, [x9, _A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE@GOTPAGEOFF]
Lloh80:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh81:
	adrp	x9, _A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE@GOTPAGE
Lloh82:
	ldr	x9, [x9, _A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE@GOTPAGEOFF]
Lloh83:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh84:
	adrp	x9, _A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE@GOTPAGE
Lloh85:
	ldr	x9, [x9, _A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE@GOTPAGEOFF]
Lloh86:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x19
	mov	x1, x21
	bl	_gpu_write
	mov	x0, x20
	bl	_adreno_is_a20x
	cbnz	w0, LBB0_4
; %bb.3:
Lloh87:
	adrp	x8, _REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1@GOTPAGE
Lloh88:
	ldr	x8, [x8, _REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1@GOTPAGEOFF]
Lloh89:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #12039
	movk	w2, #3, lsl #16
	bl	_gpu_write
LBB0_4:
Lloh90:
	adrp	x8, _REG_A2XX_SQ_VS_PROGRAM@GOTPAGE
Lloh91:
	ldr	x8, [x8, _REG_A2XX_SQ_VS_PROGRAM@GOTPAGEOFF]
Lloh92:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
Lloh93:
	adrp	x8, _REG_A2XX_SQ_PS_PROGRAM@GOTPAGE
Lloh94:
	ldr	x8, [x8, _REG_A2XX_SQ_PS_PROGRAM@GOTPAGEOFF]
Lloh95:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
	ldr	w1, [x23]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
	ldr	w1, [x24]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
Lloh96:
	adrp	x8, _REG_A2XX_RBBM_DEBUG@GOTPAGE
Lloh97:
	ldr	x8, [x8, _REG_A2XX_RBBM_DEBUG@GOTPAGEOFF]
Lloh98:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #524288
	bl	_gpu_write
Lloh99:
	adrp	x8, _REG_A2XX_RBBM_INT_CNTL@GOTPAGE
Lloh100:
	ldr	x8, [x8, _REG_A2XX_RBBM_INT_CNTL@GOTPAGEOFF]
Lloh101:
	ldr	w1, [x8]
Lloh102:
	adrp	x8, _A2XX_RBBM_INT_CNTL_RDERR_INT_MASK@GOTPAGE
Lloh103:
	ldr	x8, [x8, _A2XX_RBBM_INT_CNTL_RDERR_INT_MASK@GOTPAGEOFF]
Lloh104:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_gpu_write
Lloh105:
	adrp	x8, _REG_AXXX_CP_INT_CNTL@GOTPAGE
Lloh106:
	ldr	x8, [x8, _REG_AXXX_CP_INT_CNTL@GOTPAGEOFF]
Lloh107:
	ldr	w1, [x8]
Lloh108:
	adrp	x8, _AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK@GOTPAGE
Lloh109:
	ldr	x8, [x8, _AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK@GOTPAGEOFF]
Lloh110:
	ldr	w8, [x8]
Lloh111:
	adrp	x9, _AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK@GOTPAGE
Lloh112:
	ldr	x9, [x9, _AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK@GOTPAGEOFF]
Lloh113:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh114:
	adrp	x9, _AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK@GOTPAGE
Lloh115:
	ldr	x9, [x9, _AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK@GOTPAGEOFF]
Lloh116:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh117:
	adrp	x9, _AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK@GOTPAGE
Lloh118:
	ldr	x9, [x9, _AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK@GOTPAGEOFF]
Lloh119:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh120:
	adrp	x9, _AXXX_CP_INT_CNTL_IB_ERROR_MASK@GOTPAGE
Lloh121:
	ldr	x9, [x9, _AXXX_CP_INT_CNTL_IB_ERROR_MASK@GOTPAGEOFF]
Lloh122:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh123:
	adrp	x9, _AXXX_CP_INT_CNTL_IB1_INT_MASK@GOTPAGE
Lloh124:
	ldr	x9, [x9, _AXXX_CP_INT_CNTL_IB1_INT_MASK@GOTPAGEOFF]
Lloh125:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh126:
	adrp	x9, _AXXX_CP_INT_CNTL_RB_INT_MASK@GOTPAGE
Lloh127:
	ldr	x9, [x9, _AXXX_CP_INT_CNTL_RB_INT_MASK@GOTPAGEOFF]
Lloh128:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x19
	bl	_gpu_write
Lloh129:
	adrp	x8, _REG_A2XX_SQ_INT_CNTL@GOTPAGE
Lloh130:
	ldr	x8, [x8, _REG_A2XX_SQ_INT_CNTL@GOTPAGEOFF]
Lloh131:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
Lloh132:
	adrp	x8, _REG_A2XX_MH_INTERRUPT_MASK@GOTPAGE
Lloh133:
	ldr	x8, [x8, _REG_A2XX_MH_INTERRUPT_MASK@GOTPAGEOFF]
Lloh134:
	ldr	w1, [x8]
Lloh135:
	adrp	x8, _A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR@GOTPAGE
Lloh136:
	ldr	x8, [x8, _A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR@GOTPAGEOFF]
Lloh137:
	ldr	w8, [x8]
Lloh138:
	adrp	x9, _A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR@GOTPAGE
Lloh139:
	ldr	x9, [x9, _A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR@GOTPAGEOFF]
Lloh140:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh141:
	adrp	x9, _A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT@GOTPAGE
Lloh142:
	ldr	x9, [x9, _A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT@GOTPAGEOFF]
Lloh143:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x19
	bl	_gpu_write
Lloh144:
	adrp	x8, _SZ_16K@GOTPAGE
Lloh145:
	ldr	x8, [x8, _SZ_16K@GOTPAGEOFF]
Lloh146:
	ldr	w8, [x8]
	ldr	w9, [x20]
	cmp	w9, w8, lsl #3
	b.ne	LBB0_6
; %bb.5:
	mov	w2, #3
	b	LBB0_9
LBB0_6:
	cmp	w9, w8, lsl #4
	b.ne	LBB0_8
; %bb.7:
	mov	w2, #4
	b	LBB0_9
LBB0_8:
	cmp	w9, w8, lsl #5
	mov	w8, #5
	cinc	w2, w8, ne
LBB0_9:
Lloh147:
	adrp	x8, _REG_A2XX_RB_EDRAM_INFO@GOTPAGE
Lloh148:
	ldr	x8, [x8, _REG_A2XX_RB_EDRAM_INFO@GOTPAGEOFF]
Lloh149:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_gpu_write
	mov	x0, x19
	bl	_adreno_hw_init
	cbnz	w0, LBB0_17
; %bb.10:
	ldr	x8, [x20, #8]
Lloh150:
	adrp	x9, _ADRENO_FW_PM4@GOTPAGE
Lloh151:
	ldr	x9, [x9, _ADRENO_FW_PM4@GOTPAGEOFF]
Lloh152:
	ldr	x9, [x9]
	ldr	x8, [x8, x9, lsl #3]
	ldr	x21, [x8, #8]
	ldr	w23, [x8]
	ldr	w1, [x21, #4]
Lloh153:
	adrp	x0, l_.str.1@PAGE
Lloh154:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DBG
Lloh155:
	adrp	x8, _REG_AXXX_CP_DEBUG@GOTPAGE
Lloh156:
	ldr	x8, [x8, _REG_AXXX_CP_DEBUG@GOTPAGEOFF]
Lloh157:
	ldr	w1, [x8]
Lloh158:
	adrp	x8, _AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE@GOTPAGE
Lloh159:
	ldr	x8, [x8, _AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE@GOTPAGEOFF]
Lloh160:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_gpu_write
Lloh161:
	adrp	x8, _REG_AXXX_CP_ME_RAM_WADDR@GOTPAGE
Lloh162:
	ldr	x8, [x8, _REG_AXXX_CP_ME_RAM_WADDR@GOTPAGEOFF]
Lloh163:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
	cmp	w23, #8
	b.lt	LBB0_13
; %bb.11:
	lsr	x8, x23, #2
	add	x21, x21, #4
	sub	x23, x8, #1
Lloh164:
	adrp	x24, _REG_AXXX_CP_ME_RAM_DATA@GOTPAGE
Lloh165:
	ldr	x24, [x24, _REG_AXXX_CP_ME_RAM_DATA@GOTPAGEOFF]
LBB0_12:                                ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x24]
	ldr	w2, [x21], #4
	mov	x0, x19
	bl	_gpu_write
	subs	x23, x23, #1
	b.ne	LBB0_12
LBB0_13:
	ldr	x8, [x20, #8]
Lloh166:
	adrp	x9, _ADRENO_FW_PFP@GOTPAGE
Lloh167:
	ldr	x9, [x9, _ADRENO_FW_PFP@GOTPAGEOFF]
Lloh168:
	ldr	x9, [x9]
	ldr	x8, [x8, x9, lsl #3]
	ldr	x20, [x8, #8]
	ldr	w21, [x8]
	ldr	w1, [x20, #20]
Lloh169:
	adrp	x0, l_.str.2@PAGE
Lloh170:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	_DBG
Lloh171:
	adrp	x8, _REG_A2XX_CP_PFP_UCODE_ADDR@GOTPAGE
Lloh172:
	ldr	x8, [x8, _REG_A2XX_CP_PFP_UCODE_ADDR@GOTPAGEOFF]
Lloh173:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
	cmp	w21, #8
	b.lt	LBB0_16
; %bb.14:
	lsr	x8, x21, #2
	add	x20, x20, #4
	sub	x21, x8, #1
Lloh174:
	adrp	x23, _REG_A2XX_CP_PFP_UCODE_DATA@GOTPAGE
Lloh175:
	ldr	x23, [x23, _REG_A2XX_CP_PFP_UCODE_DATA@GOTPAGEOFF]
LBB0_15:                                ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x23]
	ldr	w2, [x20], #4
	mov	x0, x19
	bl	_gpu_write
	subs	x21, x21, #1
	b.ne	LBB0_15
LBB0_16:
Lloh176:
	adrp	x8, _REG_AXXX_CP_QUEUE_THRESHOLDS@GOTPAGE
Lloh177:
	ldr	x8, [x8, _REG_AXXX_CP_QUEUE_THRESHOLDS@GOTPAGEOFF]
Lloh178:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #2052
	movk	w2, #12, lsl #16
	bl	_gpu_write
	ldr	w1, [x22]
	mov	x0, x19
	mov	w2, #0
	bl	_gpu_write
	mov	x0, x19
	bl	_a2xx_me_init
Lloh179:
	adrp	x8, _EINVAL@GOTPAGE
Lloh180:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh181:
	ldr	w8, [x8]
	cmp	x0, #0
	csneg	w0, wzr, w8, ne
LBB0_17:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh49
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh144, Lloh145, Lloh146
	.loh AdrpLdrGotLdr	Lloh141, Lloh142, Lloh143
	.loh AdrpLdrGotLdr	Lloh138, Lloh139, Lloh140
	.loh AdrpLdrGotLdr	Lloh135, Lloh136, Lloh137
	.loh AdrpLdrGotLdr	Lloh132, Lloh133, Lloh134
	.loh AdrpLdrGotLdr	Lloh129, Lloh130, Lloh131
	.loh AdrpLdrGotLdr	Lloh126, Lloh127, Lloh128
	.loh AdrpLdrGotLdr	Lloh123, Lloh124, Lloh125
	.loh AdrpLdrGotLdr	Lloh120, Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh147, Lloh148, Lloh149
	.loh AdrpLdrGotLdr	Lloh161, Lloh162, Lloh163
	.loh AdrpLdrGotLdr	Lloh158, Lloh159, Lloh160
	.loh AdrpLdrGotLdr	Lloh155, Lloh156, Lloh157
	.loh AdrpAdd	Lloh153, Lloh154
	.loh AdrpLdrGotLdr	Lloh150, Lloh151, Lloh152
	.loh AdrpLdrGot	Lloh164, Lloh165
	.loh AdrpLdrGotLdr	Lloh171, Lloh172, Lloh173
	.loh AdrpAdd	Lloh169, Lloh170
	.loh AdrpLdrGotLdr	Lloh166, Lloh167, Lloh168
	.loh AdrpLdrGot	Lloh174, Lloh175
	.loh AdrpLdrGotLdr	Lloh179, Lloh180, Lloh181
	.loh AdrpLdrGotLdr	Lloh176, Lloh177, Lloh178
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"%s"

	.comm	_REG_AXXX_CP_ME_CNTL,4,2        ; @REG_AXXX_CP_ME_CNTL
	.comm	_AXXX_CP_ME_CNTL_HALT,4,2       ; @AXXX_CP_ME_CNTL_HALT
	.comm	_REG_A2XX_RBBM_PM_OVERRIDE1,4,2 ; @REG_A2XX_RBBM_PM_OVERRIDE1
	.comm	_REG_A2XX_RBBM_PM_OVERRIDE2,4,2 ; @REG_A2XX_RBBM_PM_OVERRIDE2
	.comm	_REG_A2XX_RBBM_SOFT_RESET,4,2   ; @REG_A2XX_RBBM_SOFT_RESET
	.comm	_REG_A2XX_SQ_FLOW_CONTROL,4,2   ; @REG_A2XX_SQ_FLOW_CONTROL
	.comm	_REG_A2XX_RBBM_CNTL,4,2         ; @REG_A2XX_RBBM_CNTL
	.comm	_REG_A2XX_MH_MMU_MPU_BASE,4,2   ; @REG_A2XX_MH_MMU_MPU_BASE
	.comm	_REG_A2XX_MH_MMU_MPU_END,4,2    ; @REG_A2XX_MH_MMU_MPU_END
	.comm	_REG_A2XX_MH_MMU_CONFIG,4,2     ; @REG_A2XX_MH_MMU_CONFIG
	.comm	_A2XX_MH_MMU_CONFIG_MMU_ENABLE,4,2 ; @A2XX_MH_MMU_CONFIG_MMU_ENABLE
	.comm	_BEH_TRAN_RNG,4,2               ; @BEH_TRAN_RNG
	.comm	_REG_A2XX_MH_MMU_VA_RANGE,4,2   ; @REG_A2XX_MH_MMU_VA_RANGE
	.comm	_SZ_16M,4,2                     ; @SZ_16M
	.comm	_REG_A2XX_MH_MMU_PT_BASE,4,2    ; @REG_A2XX_MH_MMU_PT_BASE
	.comm	_REG_A2XX_MH_MMU_TRAN_ERROR,4,2 ; @REG_A2XX_MH_MMU_TRAN_ERROR
	.comm	_REG_A2XX_MH_MMU_INVALIDATE,4,2 ; @REG_A2XX_MH_MMU_INVALIDATE
	.comm	_A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL,4,2 ; @A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL
	.comm	_A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC,4,2 ; @A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC
	.comm	_REG_A2XX_MH_ARBITER_CONFIG,4,2 ; @REG_A2XX_MH_ARBITER_CONFIG
	.comm	_A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE,4,2 ; @A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE
	.comm	_A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE,4,2 ; @A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE
	.comm	_A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE,4,2 ; @A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE
	.comm	_A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE,4,2 ; @A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE
	.comm	_A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE,4,2 ; @A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE
	.comm	_A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE,4,2 ; @A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE
	.comm	_A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE,4,2 ; @A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE
	.comm	_A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE,4,2 ; @A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE
	.comm	_A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE,4,2 ; @A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE
	.comm	_A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE,4,2 ; @A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE
	.comm	_REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1,4,2 ; @REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1
	.comm	_REG_A2XX_SQ_VS_PROGRAM,4,2     ; @REG_A2XX_SQ_VS_PROGRAM
	.comm	_REG_A2XX_SQ_PS_PROGRAM,4,2     ; @REG_A2XX_SQ_PS_PROGRAM
	.comm	_REG_A2XX_RBBM_DEBUG,4,2        ; @REG_A2XX_RBBM_DEBUG
	.comm	_REG_A2XX_RBBM_INT_CNTL,4,2     ; @REG_A2XX_RBBM_INT_CNTL
	.comm	_A2XX_RBBM_INT_CNTL_RDERR_INT_MASK,4,2 ; @A2XX_RBBM_INT_CNTL_RDERR_INT_MASK
	.comm	_REG_AXXX_CP_INT_CNTL,4,2       ; @REG_AXXX_CP_INT_CNTL
	.comm	_AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK,4,2 ; @AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK
	.comm	_AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK,4,2 ; @AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK
	.comm	_AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK,4,2 ; @AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK
	.comm	_AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK,4,2 ; @AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK
	.comm	_AXXX_CP_INT_CNTL_IB_ERROR_MASK,4,2 ; @AXXX_CP_INT_CNTL_IB_ERROR_MASK
	.comm	_AXXX_CP_INT_CNTL_IB1_INT_MASK,4,2 ; @AXXX_CP_INT_CNTL_IB1_INT_MASK
	.comm	_AXXX_CP_INT_CNTL_RB_INT_MASK,4,2 ; @AXXX_CP_INT_CNTL_RB_INT_MASK
	.comm	_REG_A2XX_SQ_INT_CNTL,4,2       ; @REG_A2XX_SQ_INT_CNTL
	.comm	_REG_A2XX_MH_INTERRUPT_MASK,4,2 ; @REG_A2XX_MH_INTERRUPT_MASK
	.comm	_A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR,4,2 ; @A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR
	.comm	_A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR,4,2 ; @A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR
	.comm	_A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT,4,2 ; @A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT
	.comm	_SZ_16K,4,2                     ; @SZ_16K
	.comm	_REG_A2XX_RB_EDRAM_INFO,4,2     ; @REG_A2XX_RB_EDRAM_INFO
	.comm	_ADRENO_FW_PM4,8,3              ; @ADRENO_FW_PM4
l_.str.1:                               ; @.str.1
	.asciz	"loading PM4 ucode version: %x"

	.comm	_REG_AXXX_CP_DEBUG,4,2          ; @REG_AXXX_CP_DEBUG
	.comm	_AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE,4,2 ; @AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE
	.comm	_REG_AXXX_CP_ME_RAM_WADDR,4,2   ; @REG_AXXX_CP_ME_RAM_WADDR
	.comm	_REG_AXXX_CP_ME_RAM_DATA,4,2    ; @REG_AXXX_CP_ME_RAM_DATA
	.comm	_ADRENO_FW_PFP,8,3              ; @ADRENO_FW_PFP
l_.str.2:                               ; @.str.2
	.asciz	"loading PFP ucode version: %x"

	.comm	_REG_A2XX_CP_PFP_UCODE_ADDR,4,2 ; @REG_A2XX_CP_PFP_UCODE_ADDR
	.comm	_REG_A2XX_CP_PFP_UCODE_DATA,4,2 ; @REG_A2XX_CP_PFP_UCODE_DATA
	.comm	_REG_AXXX_CP_QUEUE_THRESHOLDS,4,2 ; @REG_AXXX_CP_QUEUE_THRESHOLDS
	.comm	_EINVAL,4,2                     ; @EINVAL
	.no_dead_strip	_a2xx_hw_init
.subsections_via_symbols
