	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_vcn_v2_0_jpeg_ring_emit_reg_wait ## -- Begin function vcn_v2_0_jpeg_ring_emit_reg_wait
	.p2align	4, 0x90
_vcn_v2_0_jpeg_ring_emit_reg_wait:      ## @vcn_v2_0_jpeg_ring_emit_reg_wait
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %r14d
	movl	%edx, %r12d
	movl	%esi, %r15d
	movq	%rdi, %rbx
	movq	_mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_PACKETJ_TYPE0@GOTPCREL(%rip), %r13
	movl	(%r13), %ecx
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	$20972032, %esi                 ## imm = 0x1400200
	callq	_amdgpu_ring_write
	movq	_mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r13), %ecx
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	%r12d, %esi
	callq	_amdgpu_ring_write
	movq	_mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r13), %ecx
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	leal	-65536(,%r15,4), %eax
	cmpl	$1535, %eax                     ## imm = 0x5FF
	ja	LBB0_2
## %bb.1:
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
	andl	$1073741823, %r15d              ## imm = 0x3FFFFFFF
	jmp	LBB0_3
LBB0_2:
	shll	$2, %r15d
	movq	%rbx, %rdi
	movl	%r15d, %esi
	callq	_amdgpu_ring_write
	movq	_JRBC_DEC_EXTERNAL_REG_WRITE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
LBB0_3:
	movq	_PACKETJ_TYPE3@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%r15d, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%rbx, %rdi
	movl	%r14d, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_write              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,4,2 ## @mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET
	.comm	_PACKETJ_TYPE0,4,2              ## @PACKETJ_TYPE0
	.comm	_mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,4,2 ## @mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET
	.comm	_mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,4,2 ## @mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET
	.comm	_PACKETJ_TYPE3,4,2              ## @PACKETJ_TYPE3
	.comm	_JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,4,2 ## @JRBC_DEC_EXTERNAL_REG_WRITE_ADDR
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_vcn_v2_0_jpeg_ring_emit_reg_wait ; -- Begin function vcn_v2_0_jpeg_ring_emit_reg_wait
	.p2align	2
_vcn_v2_0_jpeg_ring_emit_reg_wait:      ; @vcn_v2_0_jpeg_ring_emit_reg_wait
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x3
	mov	x23, x2
	mov	x21, x1
	mov	x20, x0
	lsl	w22, w1, #2
Lloh0:
	adrp	x8, _mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET@GOTPAGE
Lloh1:
	ldr	x8, [x8, _mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
Lloh3:
	adrp	x24, _PACKETJ_TYPE0@GOTPAGE
Lloh4:
	ldr	x24, [x24, _PACKETJ_TYPE0@GOTPAGEOFF]
	ldr	w3, [x24]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
	mov	x0, x20
	mov	w1, #512
	movk	w1, #320, lsl #16
	bl	_amdgpu_ring_write
Lloh5:
	adrp	x8, _mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET@GOTPAGE
Lloh6:
	ldr	x8, [x8, _mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh7:
	ldr	w0, [x8]
	ldr	w3, [x24]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
	mov	x0, x20
	mov	x1, x23
	bl	_amdgpu_ring_write
Lloh8:
	adrp	x8, _mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET@GOTPAGE
Lloh9:
	ldr	x8, [x8, _mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET@GOTPAGEOFF]
Lloh10:
	ldr	w0, [x8]
	ldr	w3, [x24]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
	sub	w8, w22, #16, lsl #12           ; =65536
	mov	x0, x20
	cmp	w8, #1535
	b.hi	LBB0_2
; %bb.1:
	mov	w1, #0
	bl	_amdgpu_ring_write
	and	w0, w21, #0x3fffffff
	b	LBB0_3
LBB0_2:
	mov	x1, x22
	bl	_amdgpu_ring_write
Lloh11:
	adrp	x8, _JRBC_DEC_EXTERNAL_REG_WRITE_ADDR@GOTPAGE
Lloh12:
	ldr	x8, [x8, _JRBC_DEC_EXTERNAL_REG_WRITE_ADDR@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
LBB0_3:
Lloh14:
	adrp	x8, _PACKETJ_TYPE3@GOTPAGE
Lloh15:
	ldr	x8, [x8, _PACKETJ_TYPE3@GOTPAGEOFF]
Lloh16:
	ldr	w3, [x8]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x20
	bl	_amdgpu_ring_write
	mov	x0, x20
	mov	x1, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_amdgpu_ring_write
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.cfi_endproc
                                        ; -- End function
	.comm	_mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,4,2 ; @mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET
	.comm	_PACKETJ_TYPE0,4,2              ; @PACKETJ_TYPE0
	.comm	_mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,4,2 ; @mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET
	.comm	_mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,4,2 ; @mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET
	.comm	_PACKETJ_TYPE3,4,2              ; @PACKETJ_TYPE3
	.comm	_JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,4,2 ; @JRBC_DEC_EXTERNAL_REG_WRITE_ADDR
.subsections_via_symbols
