	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v8_0_polaris_update_gfx_clock_gating
_gfx_v8_0_polaris_update_gfx_clock_gating: ## @gfx_v8_0_polaris_update_gfx_clock_gating
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %r15
	movl	(%rdi), %edx
	movq	_AMD_CG_SUPPORT_GFX_CGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_AMD_CG_SUPPORT_GFX_CGLS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, %esi
	orl	%eax, %esi
	testl	%edx, %esi
	je	LBB0_1
## %bb.2:
	andl	%edx, %ecx
	movl	%ecx, %esi
	je	LBB0_4
## %bb.3:
	movq	_PP_STATE_SUPPORT_LS@GOTPCREL(%rip), %rsi
	movq	_PP_STATE_LS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	(%rsi), %esi
LBB0_4:
	andl	%edx, %eax
	movl	%eax, %r12d
	je	LBB0_6
## %bb.5:
	movq	_PP_STATE_SUPPORT_CG@GOTPCREL(%rip), %rdx
	movq	_PP_STATE_CG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	(%rdx), %r12d
LBB0_6:
	orl	%esi, %r12d
	orl	%ecx, %eax
	movq	_AMD_CG_STATE_UNGATE@GOTPCREL(%rip), %rcx
	xorl	%ebx, %ebx
	cmpl	%r14d, (%rcx)
	cmovnel	%eax, %ebx
	movq	_PP_GROUP_GFX@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_PP_BLOCK_GFX_CG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r12d, %edx
	movl	%ebx, %ecx
	callq	_PP_CG_MSG_ID
	movq	8(%r15), %rcx
	cmpq	$0, (%rcx)
	je	LBB0_8
## %bb.7:
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_dpm_set_clockgating_by_smu
	jmp	LBB0_8
LBB0_1:
	xorl	%ebx, %ebx
	xorl	%r12d, %r12d
LBB0_8:
	movl	(%r15), %ecx
	movq	_AMD_CG_SUPPORT_GFX_3D_CGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_AMD_CG_SUPPORT_GFX_3D_CGLS@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movl	%edx, %esi
	orl	%eax, %esi
	testl	%ecx, %esi
	je	LBB0_9
## %bb.10:
	testl	%ecx, %edx
	je	LBB0_12
## %bb.11:
	movq	_PP_STATE_SUPPORT_LS@GOTPCREL(%rip), %rdx
	movq	_PP_STATE_LS@GOTPCREL(%rip), %rsi
	movl	(%rsi), %ebx
	movl	(%rdx), %r12d
LBB0_12:
	andl	%ecx, %eax
	movl	%eax, %r13d
	je	LBB0_14
## %bb.13:
	movq	_PP_STATE_SUPPORT_CG@GOTPCREL(%rip), %rcx
	movq	_PP_STATE_CG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	(%rcx), %r13d
LBB0_14:
	orl	%r12d, %r13d
	orl	%ebx, %eax
	movq	_AMD_CG_STATE_UNGATE@GOTPCREL(%rip), %rcx
	xorl	%ebx, %ebx
	cmpl	%r14d, (%rcx)
	cmovnel	%eax, %ebx
	movq	_PP_GROUP_GFX@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_PP_BLOCK_GFX_3D@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r13d, %edx
	movl	%ebx, %ecx
	callq	_PP_CG_MSG_ID
	movq	8(%r15), %rcx
	cmpq	$0, (%rcx)
	je	LBB0_16
## %bb.15:
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_dpm_set_clockgating_by_smu
	jmp	LBB0_16
LBB0_9:
	movl	%r12d, %r13d
LBB0_16:
	movl	(%r15), %ecx
	movq	_AMD_CG_SUPPORT_GFX_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_AMD_CG_SUPPORT_GFX_MGLS@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movl	%edx, %esi
	orl	%eax, %esi
	testl	%ecx, %esi
	je	LBB0_23
## %bb.17:
	testl	%ecx, %edx
	je	LBB0_19
## %bb.18:
	movq	_PP_STATE_SUPPORT_LS@GOTPCREL(%rip), %rdx
	movq	_PP_STATE_LS@GOTPCREL(%rip), %rsi
	movl	(%rsi), %ebx
	movl	(%rdx), %r13d
LBB0_19:
	andl	%ecx, %eax
	movl	%eax, %edx
	je	LBB0_21
## %bb.20:
	movq	_PP_STATE_SUPPORT_CG@GOTPCREL(%rip), %rcx
	movq	_PP_STATE_CG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	(%rcx), %edx
LBB0_21:
	orl	%r13d, %edx
	orl	%ebx, %eax
	movq	_AMD_CG_STATE_UNGATE@GOTPCREL(%rip), %rsi
	xorl	%ecx, %ecx
	cmpl	%r14d, (%rsi)
	cmovnel	%eax, %ecx
	movq	_PP_GROUP_GFX@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_PP_BLOCK_GFX_MG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_PP_CG_MSG_ID
	movq	8(%r15), %rcx
	cmpq	$0, (%rcx)
	je	LBB0_23
## %bb.22:
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_dpm_set_clockgating_by_smu
LBB0_23:
	movq	_AMD_CG_SUPPORT_GFX_RLC_LS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r15)
	je	LBB0_28
## %bb.24:
	movq	_PP_STATE_SUPPORT_LS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_AMD_CG_STATE_UNGATE@GOTPCREL(%rip), %rax
	xorl	%ecx, %ecx
	cmpl	%r14d, (%rax)
	je	LBB0_26
## %bb.25:
	movq	_PP_STATE_LS@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
LBB0_26:
	movq	_PP_GROUP_GFX@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_PP_BLOCK_GFX_RLC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_PP_CG_MSG_ID
	movq	8(%r15), %rcx
	cmpq	$0, (%rcx)
	je	LBB0_28
## %bb.27:
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_dpm_set_clockgating_by_smu
LBB0_28:
	movq	_AMD_CG_SUPPORT_GFX_CP_LS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r15)
	je	LBB0_33
## %bb.29:
	movq	_PP_STATE_SUPPORT_LS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_AMD_CG_STATE_UNGATE@GOTPCREL(%rip), %rax
	xorl	%ecx, %ecx
	cmpl	%r14d, (%rax)
	je	LBB0_31
## %bb.30:
	movq	_PP_STATE_LS@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
LBB0_31:
	movq	_PP_GROUP_GFX@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_PP_BLOCK_GFX_CP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_PP_CG_MSG_ID
	movq	8(%r15), %rcx
	cmpq	$0, (%rcx)
	je	LBB0_33
## %bb.32:
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_dpm_set_clockgating_by_smu
LBB0_33:
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_CG_SUPPORT_GFX_CGCG,4,2    ## @AMD_CG_SUPPORT_GFX_CGCG
	.comm	_AMD_CG_SUPPORT_GFX_CGLS,4,2    ## @AMD_CG_SUPPORT_GFX_CGLS
	.comm	_PP_STATE_SUPPORT_LS,4,2        ## @PP_STATE_SUPPORT_LS
	.comm	_PP_STATE_LS,4,2                ## @PP_STATE_LS
	.comm	_PP_STATE_SUPPORT_CG,4,2        ## @PP_STATE_SUPPORT_CG
	.comm	_PP_STATE_CG,4,2                ## @PP_STATE_CG
	.comm	_AMD_CG_STATE_UNGATE,4,2        ## @AMD_CG_STATE_UNGATE
	.comm	_PP_GROUP_GFX,4,2               ## @PP_GROUP_GFX
	.comm	_PP_BLOCK_GFX_CG,4,2            ## @PP_BLOCK_GFX_CG
	.comm	_AMD_CG_SUPPORT_GFX_3D_CGCG,4,2 ## @AMD_CG_SUPPORT_GFX_3D_CGCG
	.comm	_AMD_CG_SUPPORT_GFX_3D_CGLS,4,2 ## @AMD_CG_SUPPORT_GFX_3D_CGLS
	.comm	_PP_BLOCK_GFX_3D,4,2            ## @PP_BLOCK_GFX_3D
	.comm	_AMD_CG_SUPPORT_GFX_MGCG,4,2    ## @AMD_CG_SUPPORT_GFX_MGCG
	.comm	_AMD_CG_SUPPORT_GFX_MGLS,4,2    ## @AMD_CG_SUPPORT_GFX_MGLS
	.comm	_PP_BLOCK_GFX_MG,4,2            ## @PP_BLOCK_GFX_MG
	.comm	_AMD_CG_SUPPORT_GFX_RLC_LS,4,2  ## @AMD_CG_SUPPORT_GFX_RLC_LS
	.comm	_PP_BLOCK_GFX_RLC,4,2           ## @PP_BLOCK_GFX_RLC
	.comm	_AMD_CG_SUPPORT_GFX_CP_LS,4,2   ## @AMD_CG_SUPPORT_GFX_CP_LS
	.comm	_PP_BLOCK_GFX_CP,4,2            ## @PP_BLOCK_GFX_CP
	.no_dead_strip	_gfx_v8_0_polaris_update_gfx_clock_gating
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v8_0_polaris_update_gfx_clock_gating
_gfx_v8_0_polaris_update_gfx_clock_gating: ; @gfx_v8_0_polaris_update_gfx_clock_gating
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x20, x1
	mov	x19, x0
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _AMD_CG_SUPPORT_GFX_CGCG@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_CG_SUPPORT_GFX_CGCG@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
Lloh3:
	adrp	x10, _AMD_CG_SUPPORT_GFX_CGLS@GOTPAGE
Lloh4:
	ldr	x10, [x10, _AMD_CG_SUPPORT_GFX_CGLS@GOTPAGEOFF]
Lloh5:
	ldr	w10, [x10]
Lloh6:
	adrp	x25, _PP_STATE_SUPPORT_LS@GOTPAGE
Lloh7:
	ldr	x25, [x25, _PP_STATE_SUPPORT_LS@GOTPAGEOFF]
Lloh8:
	adrp	x23, _PP_STATE_LS@GOTPAGE
Lloh9:
	ldr	x23, [x23, _PP_STATE_LS@GOTPAGEOFF]
Lloh10:
	adrp	x27, _PP_STATE_SUPPORT_CG@GOTPAGE
Lloh11:
	ldr	x27, [x27, _PP_STATE_SUPPORT_CG@GOTPAGEOFF]
Lloh12:
	adrp	x28, _PP_STATE_CG@GOTPAGE
Lloh13:
	ldr	x28, [x28, _PP_STATE_CG@GOTPAGEOFF]
	orr	w11, w10, w9
Lloh14:
	adrp	x26, _AMD_CG_STATE_UNGATE@GOTPAGE
Lloh15:
	ldr	x26, [x26, _AMD_CG_STATE_UNGATE@GOTPAGEOFF]
Lloh16:
	adrp	x24, _PP_GROUP_GFX@GOTPAGE
Lloh17:
	ldr	x24, [x24, _PP_GROUP_GFX@GOTPAGEOFF]
	tst	w11, w8
	b.eq	LBB0_3
; %bb.1:
	ldr	w11, [x25]
	ldr	w12, [x23]
	tst	w10, w8
	csel	w10, wzr, w12, eq
	csel	w11, wzr, w11, eq
	ldr	w12, [x27]
	ldr	w13, [x28]
	tst	w9, w8
	csel	w8, wzr, w13, eq
	orr	w8, w8, w10
	csel	w9, wzr, w12, eq
	orr	w21, w9, w11
	ldr	w9, [x26]
	cmp	w9, w20
	csel	w22, wzr, w8, eq
	ldr	w0, [x24]
Lloh18:
	adrp	x8, _PP_BLOCK_GFX_CG@GOTPAGE
Lloh19:
	ldr	x8, [x8, _PP_BLOCK_GFX_CG@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	mov	x2, x21
	mov	x3, x22
	bl	_PP_CG_MSG_ID
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	cbz	x8, LBB0_4
; %bb.2:
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_dpm_set_clockgating_by_smu
	b	LBB0_4
LBB0_3:
	mov	w22, #0
	mov	w21, #0
LBB0_4:
	ldr	w8, [x19]
Lloh21:
	adrp	x9, _AMD_CG_SUPPORT_GFX_3D_CGCG@GOTPAGE
Lloh22:
	ldr	x9, [x9, _AMD_CG_SUPPORT_GFX_3D_CGCG@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
Lloh24:
	adrp	x10, _AMD_CG_SUPPORT_GFX_3D_CGLS@GOTPAGE
Lloh25:
	ldr	x10, [x10, _AMD_CG_SUPPORT_GFX_3D_CGLS@GOTPAGEOFF]
Lloh26:
	ldr	w10, [x10]
	orr	w11, w10, w9
	tst	w11, w8
	b.eq	LBB0_7
; %bb.5:
	ldr	w11, [x25]
	ldr	w12, [x23]
	tst	w10, w8
	csel	w10, w22, w12, eq
	csel	w11, w21, w11, eq
	ldr	w12, [x27]
	ldr	w13, [x28]
	tst	w9, w8
	csel	w8, wzr, w13, eq
	orr	w8, w8, w10
	csel	w9, wzr, w12, eq
	orr	w21, w9, w11
	ldr	w9, [x26]
	cmp	w9, w20
	csel	w22, wzr, w8, eq
	ldr	w0, [x24]
Lloh27:
	adrp	x8, _PP_BLOCK_GFX_3D@GOTPAGE
Lloh28:
	ldr	x8, [x8, _PP_BLOCK_GFX_3D@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	mov	x2, x21
	mov	x3, x22
	bl	_PP_CG_MSG_ID
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	cbz	x8, LBB0_7
; %bb.6:
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_dpm_set_clockgating_by_smu
LBB0_7:
	ldr	w8, [x19]
Lloh30:
	adrp	x9, _AMD_CG_SUPPORT_GFX_MGCG@GOTPAGE
Lloh31:
	ldr	x9, [x9, _AMD_CG_SUPPORT_GFX_MGCG@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
Lloh33:
	adrp	x10, _AMD_CG_SUPPORT_GFX_MGLS@GOTPAGE
Lloh34:
	ldr	x10, [x10, _AMD_CG_SUPPORT_GFX_MGLS@GOTPAGEOFF]
Lloh35:
	ldr	w10, [x10]
	orr	w11, w10, w9
	tst	w11, w8
	b.eq	LBB0_10
; %bb.8:
	ldr	w11, [x25]
	ldr	w12, [x23]
	tst	w10, w8
	csel	w10, w22, w12, eq
	csel	w11, w21, w11, eq
	ldr	w12, [x27]
	ldr	w13, [x28]
	tst	w9, w8
	csel	w8, wzr, w13, eq
	orr	w8, w8, w10
	csel	w9, wzr, w12, eq
	orr	w2, w9, w11
	ldr	w9, [x26]
	cmp	w9, w20
	csel	w3, wzr, w8, eq
	ldr	w0, [x24]
Lloh36:
	adrp	x8, _PP_BLOCK_GFX_MG@GOTPAGE
Lloh37:
	ldr	x8, [x8, _PP_BLOCK_GFX_MG@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
	bl	_PP_CG_MSG_ID
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	cbz	x8, LBB0_10
; %bb.9:
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_dpm_set_clockgating_by_smu
LBB0_10:
	ldr	w8, [x19]
Lloh39:
	adrp	x9, _AMD_CG_SUPPORT_GFX_RLC_LS@GOTPAGE
Lloh40:
	ldr	x9, [x9, _AMD_CG_SUPPORT_GFX_RLC_LS@GOTPAGEOFF]
Lloh41:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_13
; %bb.11:
	ldr	w2, [x25]
	ldr	w8, [x26]
	ldr	w9, [x23]
	cmp	w8, w20
	csel	w3, wzr, w9, eq
	ldr	w0, [x24]
Lloh42:
	adrp	x8, _PP_BLOCK_GFX_RLC@GOTPAGE
Lloh43:
	ldr	x8, [x8, _PP_BLOCK_GFX_RLC@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x8]
	bl	_PP_CG_MSG_ID
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	cbz	x8, LBB0_13
; %bb.12:
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_dpm_set_clockgating_by_smu
LBB0_13:
	ldr	w8, [x19]
Lloh45:
	adrp	x9, _AMD_CG_SUPPORT_GFX_CP_LS@GOTPAGE
Lloh46:
	ldr	x9, [x9, _AMD_CG_SUPPORT_GFX_CP_LS@GOTPAGEOFF]
Lloh47:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_16
; %bb.14:
	ldr	w2, [x25]
	ldr	w8, [x26]
	ldr	w9, [x23]
	cmp	w8, w20
	csel	w3, wzr, w9, eq
	ldr	w0, [x24]
Lloh48:
	adrp	x8, _PP_BLOCK_GFX_CP@GOTPAGE
Lloh49:
	ldr	x8, [x8, _PP_BLOCK_GFX_CP@GOTPAGEOFF]
Lloh50:
	ldr	w1, [x8]
	bl	_PP_CG_MSG_ID
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	cbz	x8, LBB0_16
; %bb.15:
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_dpm_set_clockgating_by_smu
LBB0_16:
	mov	w0, #0
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_CG_SUPPORT_GFX_CGCG,4,2    ; @AMD_CG_SUPPORT_GFX_CGCG
	.comm	_AMD_CG_SUPPORT_GFX_CGLS,4,2    ; @AMD_CG_SUPPORT_GFX_CGLS
	.comm	_PP_STATE_SUPPORT_LS,4,2        ; @PP_STATE_SUPPORT_LS
	.comm	_PP_STATE_LS,4,2                ; @PP_STATE_LS
	.comm	_PP_STATE_SUPPORT_CG,4,2        ; @PP_STATE_SUPPORT_CG
	.comm	_PP_STATE_CG,4,2                ; @PP_STATE_CG
	.comm	_AMD_CG_STATE_UNGATE,4,2        ; @AMD_CG_STATE_UNGATE
	.comm	_PP_GROUP_GFX,4,2               ; @PP_GROUP_GFX
	.comm	_PP_BLOCK_GFX_CG,4,2            ; @PP_BLOCK_GFX_CG
	.comm	_AMD_CG_SUPPORT_GFX_3D_CGCG,4,2 ; @AMD_CG_SUPPORT_GFX_3D_CGCG
	.comm	_AMD_CG_SUPPORT_GFX_3D_CGLS,4,2 ; @AMD_CG_SUPPORT_GFX_3D_CGLS
	.comm	_PP_BLOCK_GFX_3D,4,2            ; @PP_BLOCK_GFX_3D
	.comm	_AMD_CG_SUPPORT_GFX_MGCG,4,2    ; @AMD_CG_SUPPORT_GFX_MGCG
	.comm	_AMD_CG_SUPPORT_GFX_MGLS,4,2    ; @AMD_CG_SUPPORT_GFX_MGLS
	.comm	_PP_BLOCK_GFX_MG,4,2            ; @PP_BLOCK_GFX_MG
	.comm	_AMD_CG_SUPPORT_GFX_RLC_LS,4,2  ; @AMD_CG_SUPPORT_GFX_RLC_LS
	.comm	_PP_BLOCK_GFX_RLC,4,2           ; @PP_BLOCK_GFX_RLC
	.comm	_AMD_CG_SUPPORT_GFX_CP_LS,4,2   ; @AMD_CG_SUPPORT_GFX_CP_LS
	.comm	_PP_BLOCK_GFX_CP,4,2            ; @PP_BLOCK_GFX_CP
	.no_dead_strip	_gfx_v8_0_polaris_update_gfx_clock_gating
.subsections_via_symbols
