	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_si_set_vce_clocks              ## -- Begin function si_set_vce_clocks
	.p2align	4, 0x90
_si_set_vce_clocks:                     ## @si_set_vce_clocks
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r15d
	movl	%esi, %r12d
	movq	%rdi, %r14
	movl	$0, -52(%rbp)
	movl	$0, -48(%rbp)
	movl	$0, -44(%rbp)
	movq	_CG_VCEPLL_FUNC_CNTL_2@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	$1, %edi
	callq	_EVCLK_SRC_SEL
	movl	%eax, %ebx
	movl	$1, %edi
	callq	_ECCLK_SRC_SEL
	orl	%eax, %ebx
	movq	_EVCLK_SRC_SEL_MASK@GOTPCREL(%rip), %rax
	movq	_ECCLK_SRC_SEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	notl	%edx
	movl	%r13d, %edi
	movl	%ebx, %esi
	callq	_WREG32_SMC_P
	movq	_CG_VCEPLL_FUNC_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movq	_VCEPLL_BYPASS_EN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%esi, %edx
	notl	%edx
	callq	_WREG32_SMC_P
	testl	%r12d, %r12d
	je	LBB0_2
## %bb.1:
	testl	%r15d, %r15d
	je	LBB0_2
## %bb.3:
	subq	$8, %rsp
	leaq	-44(%rbp), %rax
	leaq	-48(%rbp), %rbx
	leaq	-52(%rbp), %r10
	movq	%r14, %rdi
	movl	%r12d, %esi
	movl	%r15d, %edx
	movl	$125000, %ecx                   ## imm = 0x1E848
	movl	$250000, %r8d                   ## imm = 0x3D090
	movl	$16384, %r9d                    ## imm = 0x4000
	pushq	%rax
	pushq	%rbx
	pushq	%r10
	pushq	$5
	pushq	$128
	pushq	$0
	pushq	$67108863                       ## imm = 0x3FFFFFF
	callq	_radeon_uvd_calc_upll_dividers
	addq	$64, %rsp
	testl	%eax, %eax
	jne	LBB0_8
## %bb.4:
	movq	_CG_VCEPLL_FUNC_CNTL_5@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RESET_ANTI_MUX_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	xorl	%esi, %esi
	callq	_WREG32_SMC_P
	movl	(%r13), %edi
	movq	_VCEPLL_VCO_MODE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%esi, %edx
	notl	%edx
	callq	_WREG32_SMC_P
	movl	(%r13), %edi
	movq	_VCEPLL_SLEEP_MASK@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movl	%esi, %edx
	notl	%edx
	callq	_WREG32_SMC_P
	movl	(%r13), %edi
	movl	(%rbx), %edx
	notl	%edx
	xorl	%esi, %esi
	callq	_WREG32_SMC_P
	movl	(%r13), %edi
	movq	_VCEPLL_RESET_MASK@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	notl	%edx
	xorl	%esi, %esi
	callq	_WREG32_SMC_P
	movl	$1, %edi
	callq	_mdelay
	movq	%r14, %rdi
	callq	_si_vce_send_vcepll_ctlreq
	testl	%eax, %eax
	jne	LBB0_8
## %bb.5:
	movl	(%r13), %edi
	movl	(%rbx), %esi
	movl	%esi, %edx
	notl	%edx
	callq	_WREG32_SMC_P
	movq	_CG_VCEPLL_SPREAD_SPECTRUM@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_SSEN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	xorl	%esi, %esi
	callq	_WREG32_SMC_P
	movq	_CG_VCEPLL_FUNC_CNTL_3@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	-52(%rbp), %edi
	callq	_VCEPLL_FB_DIV
	movq	_VCEPLL_FB_DIV_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movl	%r15d, %edi
	movl	%eax, %esi
	callq	_WREG32_SMC_P
	movl	(%r13), %edi
	movq	_VCEPLL_REF_DIV_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	xorl	%esi, %esi
	callq	_WREG32_SMC_P
	movq	_CG_VCEPLL_FUNC_CNTL_2@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	-48(%rbp), %edi
	callq	_VCEPLL_PDIV_A
	movl	%eax, %r12d
	movl	-44(%rbp), %edi
	callq	_VCEPLL_PDIV_B
	orl	%eax, %r12d
	movq	_VCEPLL_PDIV_A_MASK@GOTPCREL(%rip), %rax
	movq	_VCEPLL_PDIV_B_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	notl	%edx
	movl	%r15d, %edi
	movl	%r12d, %esi
	callq	_WREG32_SMC_P
	movl	$15, %edi
	callq	_mdelay
	movl	(%r13), %edi
	movl	(%rbx), %edx
	notl	%edx
	xorl	%esi, %esi
	callq	_WREG32_SMC_P
	movl	$15, %edi
	callq	_mdelay
	movl	(%r13), %edi
	movq	_VCEPLL_BYPASS_EN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	xorl	%esi, %esi
	callq	_WREG32_SMC_P
	movq	%r14, %rdi
	callq	_si_vce_send_vcepll_ctlreq
	testl	%eax, %eax
	jne	LBB0_8
## %bb.6:
	movq	_CG_VCEPLL_FUNC_CNTL_2@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	$16, %edi
	callq	_EVCLK_SRC_SEL
	movl	%eax, %ebx
	movl	$16, %edi
	callq	_ECCLK_SRC_SEL
	orl	%eax, %ebx
	movq	_ECCLK_SRC_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_EVCLK_SRC_SEL_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	notl	%edx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_WREG32_SMC_P
	movl	$100, %edi
	callq	_mdelay
	jmp	LBB0_7
LBB0_2:
	movl	(%r13), %edi
	movq	_VCEPLL_SLEEP_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%esi, %edx
	notl	%edx
	callq	_WREG32_SMC_P
LBB0_7:
	xorl	%eax, %eax
LBB0_8:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CG_VCEPLL_FUNC_CNTL_2,4,2      ## @CG_VCEPLL_FUNC_CNTL_2
	.comm	_EVCLK_SRC_SEL_MASK,4,2         ## @EVCLK_SRC_SEL_MASK
	.comm	_ECCLK_SRC_SEL_MASK,4,2         ## @ECCLK_SRC_SEL_MASK
	.comm	_CG_VCEPLL_FUNC_CNTL,4,2        ## @CG_VCEPLL_FUNC_CNTL
	.comm	_VCEPLL_BYPASS_EN_MASK,4,2      ## @VCEPLL_BYPASS_EN_MASK
	.comm	_VCEPLL_SLEEP_MASK,4,2          ## @VCEPLL_SLEEP_MASK
	.comm	_CG_VCEPLL_FUNC_CNTL_5,4,2      ## @CG_VCEPLL_FUNC_CNTL_5
	.comm	_RESET_ANTI_MUX_MASK,4,2        ## @RESET_ANTI_MUX_MASK
	.comm	_VCEPLL_VCO_MODE_MASK,4,2       ## @VCEPLL_VCO_MODE_MASK
	.comm	_VCEPLL_RESET_MASK,4,2          ## @VCEPLL_RESET_MASK
	.comm	_CG_VCEPLL_SPREAD_SPECTRUM,4,2  ## @CG_VCEPLL_SPREAD_SPECTRUM
	.comm	_SSEN_MASK,4,2                  ## @SSEN_MASK
	.comm	_CG_VCEPLL_FUNC_CNTL_3,4,2      ## @CG_VCEPLL_FUNC_CNTL_3
	.comm	_VCEPLL_FB_DIV_MASK,4,2         ## @VCEPLL_FB_DIV_MASK
	.comm	_VCEPLL_REF_DIV_MASK,4,2        ## @VCEPLL_REF_DIV_MASK
	.comm	_VCEPLL_PDIV_A_MASK,4,2         ## @VCEPLL_PDIV_A_MASK
	.comm	_VCEPLL_PDIV_B_MASK,4,2         ## @VCEPLL_PDIV_B_MASK
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_si_set_vce_clocks              ; -- Begin function si_set_vce_clocks
	.p2align	2
_si_set_vce_clocks:                     ; @si_set_vce_clocks
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #144
	.cfi_def_cfa_offset 144
	stp	x28, x27, [sp, #48]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #64]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #80]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #96]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #112]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #128]            ; 16-byte Folded Spill
	add	x29, sp, #128
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x20, x2
	mov	x21, x1
	mov	x19, x0
	str	xzr, [sp, #40]
	str	wzr, [sp, #36]
Lloh0:
	adrp	x24, _CG_VCEPLL_FUNC_CNTL_2@GOTPAGE
Lloh1:
	ldr	x24, [x24, _CG_VCEPLL_FUNC_CNTL_2@GOTPAGEOFF]
	ldr	w22, [x24]
	mov	w0, #1
	bl	_EVCLK_SRC_SEL
	mov	x23, x0
	mov	w0, #1
	bl	_ECCLK_SRC_SEL
	orr	w1, w0, w23
Lloh2:
	adrp	x23, _EVCLK_SRC_SEL_MASK@GOTPAGE
Lloh3:
	ldr	x23, [x23, _EVCLK_SRC_SEL_MASK@GOTPAGEOFF]
	ldr	w8, [x23]
Lloh4:
	adrp	x25, _ECCLK_SRC_SEL_MASK@GOTPAGE
Lloh5:
	ldr	x25, [x25, _ECCLK_SRC_SEL_MASK@GOTPAGEOFF]
	ldr	w9, [x25]
	orr	w8, w9, w8
	mvn	w2, w8
	mov	x0, x22
	bl	_WREG32_SMC_P
Lloh6:
	adrp	x22, _CG_VCEPLL_FUNC_CNTL@GOTPAGE
Lloh7:
	ldr	x22, [x22, _CG_VCEPLL_FUNC_CNTL@GOTPAGEOFF]
	ldr	w0, [x22]
Lloh8:
	adrp	x26, _VCEPLL_BYPASS_EN_MASK@GOTPAGE
Lloh9:
	ldr	x26, [x26, _VCEPLL_BYPASS_EN_MASK@GOTPAGEOFF]
	ldr	w1, [x26]
	mvn	w2, w1
	bl	_WREG32_SMC_P
	cbz	w21, LBB0_6
; %bb.1:
	cbz	w20, LBB0_6
; %bb.2:
	add	x8, sp, #36
	add	x9, sp, #40
	stp	x9, x8, [sp, #16]
	add	x8, sp, #44
	mov	x9, #128
	movk	x9, #5, lsl #32
	stp	x9, x8, [sp]
	mov	x0, x19
	mov	x1, x21
	mov	x2, x20
	mov	w3, #59464
	movk	w3, #1, lsl #16
	mov	w4, #53392
	movk	w4, #3, lsl #16
	mov	w5, #16384
	mov	w6, #67108863
	mov	w7, #0
	bl	_radeon_uvd_calc_upll_dividers
	cbnz	w0, LBB0_8
; %bb.3:
Lloh10:
	adrp	x8, _CG_VCEPLL_FUNC_CNTL_5@GOTPAGE
Lloh11:
	ldr	x8, [x8, _CG_VCEPLL_FUNC_CNTL_5@GOTPAGEOFF]
Lloh12:
	ldr	w0, [x8]
Lloh13:
	adrp	x8, _RESET_ANTI_MUX_MASK@GOTPAGE
Lloh14:
	ldr	x8, [x8, _RESET_ANTI_MUX_MASK@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_SMC_P
	ldr	w0, [x22]
Lloh16:
	adrp	x8, _VCEPLL_VCO_MODE_MASK@GOTPAGE
Lloh17:
	ldr	x8, [x8, _VCEPLL_VCO_MODE_MASK@GOTPAGEOFF]
Lloh18:
	ldr	w1, [x8]
	mvn	w2, w1
	bl	_WREG32_SMC_P
	ldr	w0, [x22]
Lloh19:
	adrp	x20, _VCEPLL_SLEEP_MASK@GOTPAGE
Lloh20:
	ldr	x20, [x20, _VCEPLL_SLEEP_MASK@GOTPAGEOFF]
	ldr	w1, [x20]
	mvn	w2, w1
	bl	_WREG32_SMC_P
	ldr	w0, [x22]
	ldr	w8, [x20]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_SMC_P
	ldr	w0, [x22]
Lloh21:
	adrp	x27, _VCEPLL_RESET_MASK@GOTPAGE
Lloh22:
	ldr	x27, [x27, _VCEPLL_RESET_MASK@GOTPAGEOFF]
	ldr	w8, [x27]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_SMC_P
	mov	w0, #1
	bl	_mdelay
	mov	x0, x19
	bl	_si_vce_send_vcepll_ctlreq
	cbnz	w0, LBB0_8
; %bb.4:
	ldr	w0, [x22]
	ldr	w1, [x27]
	mvn	w2, w1
	bl	_WREG32_SMC_P
Lloh23:
	adrp	x8, _CG_VCEPLL_SPREAD_SPECTRUM@GOTPAGE
Lloh24:
	ldr	x8, [x8, _CG_VCEPLL_SPREAD_SPECTRUM@GOTPAGEOFF]
Lloh25:
	ldr	w0, [x8]
Lloh26:
	adrp	x8, _SSEN_MASK@GOTPAGE
Lloh27:
	ldr	x8, [x8, _SSEN_MASK@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_SMC_P
Lloh29:
	adrp	x8, _CG_VCEPLL_FUNC_CNTL_3@GOTPAGE
Lloh30:
	ldr	x8, [x8, _CG_VCEPLL_FUNC_CNTL_3@GOTPAGEOFF]
Lloh31:
	ldr	w20, [x8]
	ldr	w0, [sp, #44]
	bl	_VCEPLL_FB_DIV
	mov	x1, x0
Lloh32:
	adrp	x8, _VCEPLL_FB_DIV_MASK@GOTPAGE
Lloh33:
	ldr	x8, [x8, _VCEPLL_FB_DIV_MASK@GOTPAGEOFF]
Lloh34:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	x0, x20
	bl	_WREG32_SMC_P
	ldr	w0, [x22]
Lloh35:
	adrp	x8, _VCEPLL_REF_DIV_MASK@GOTPAGE
Lloh36:
	ldr	x8, [x8, _VCEPLL_REF_DIV_MASK@GOTPAGEOFF]
Lloh37:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_SMC_P
	ldr	w20, [x24]
	ldr	w0, [sp, #40]
	bl	_VCEPLL_PDIV_A
	mov	x21, x0
	ldr	w0, [sp, #36]
	bl	_VCEPLL_PDIV_B
	orr	w1, w0, w21
Lloh38:
	adrp	x8, _VCEPLL_PDIV_A_MASK@GOTPAGE
Lloh39:
	ldr	x8, [x8, _VCEPLL_PDIV_A_MASK@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
Lloh41:
	adrp	x9, _VCEPLL_PDIV_B_MASK@GOTPAGE
Lloh42:
	ldr	x9, [x9, _VCEPLL_PDIV_B_MASK@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
	orr	w8, w9, w8
	mvn	w2, w8
	mov	x0, x20
	bl	_WREG32_SMC_P
	mov	w0, #15
	bl	_mdelay
	ldr	w0, [x22]
	ldr	w8, [x27]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_SMC_P
	mov	w0, #15
	bl	_mdelay
	ldr	w0, [x22]
	ldr	w8, [x26]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_SMC_P
	mov	x0, x19
	bl	_si_vce_send_vcepll_ctlreq
	cbnz	w0, LBB0_8
; %bb.5:
	ldr	w19, [x24]
	mov	w0, #16
	bl	_EVCLK_SRC_SEL
	mov	x20, x0
	mov	w0, #16
	bl	_ECCLK_SRC_SEL
	orr	w1, w0, w20
	ldr	w8, [x23]
	ldr	w9, [x25]
	orr	w8, w9, w8
	mvn	w2, w8
	mov	x0, x19
	bl	_WREG32_SMC_P
	mov	w0, #100
	bl	_mdelay
	b	LBB0_7
LBB0_6:
	ldr	w0, [x22]
Lloh44:
	adrp	x8, _VCEPLL_SLEEP_MASK@GOTPAGE
Lloh45:
	ldr	x8, [x8, _VCEPLL_SLEEP_MASK@GOTPAGEOFF]
Lloh46:
	ldr	w1, [x8]
	mvn	w2, w1
	bl	_WREG32_SMC_P
LBB0_7:
	mov	w0, #0
LBB0_8:
	ldp	x29, x30, [sp, #128]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #112]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #96]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #80]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #64]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #144
	ret
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.cfi_endproc
                                        ; -- End function
	.comm	_CG_VCEPLL_FUNC_CNTL_2,4,2      ; @CG_VCEPLL_FUNC_CNTL_2
	.comm	_EVCLK_SRC_SEL_MASK,4,2         ; @EVCLK_SRC_SEL_MASK
	.comm	_ECCLK_SRC_SEL_MASK,4,2         ; @ECCLK_SRC_SEL_MASK
	.comm	_CG_VCEPLL_FUNC_CNTL,4,2        ; @CG_VCEPLL_FUNC_CNTL
	.comm	_VCEPLL_BYPASS_EN_MASK,4,2      ; @VCEPLL_BYPASS_EN_MASK
	.comm	_VCEPLL_SLEEP_MASK,4,2          ; @VCEPLL_SLEEP_MASK
	.comm	_CG_VCEPLL_FUNC_CNTL_5,4,2      ; @CG_VCEPLL_FUNC_CNTL_5
	.comm	_RESET_ANTI_MUX_MASK,4,2        ; @RESET_ANTI_MUX_MASK
	.comm	_VCEPLL_VCO_MODE_MASK,4,2       ; @VCEPLL_VCO_MODE_MASK
	.comm	_VCEPLL_RESET_MASK,4,2          ; @VCEPLL_RESET_MASK
	.comm	_CG_VCEPLL_SPREAD_SPECTRUM,4,2  ; @CG_VCEPLL_SPREAD_SPECTRUM
	.comm	_SSEN_MASK,4,2                  ; @SSEN_MASK
	.comm	_CG_VCEPLL_FUNC_CNTL_3,4,2      ; @CG_VCEPLL_FUNC_CNTL_3
	.comm	_VCEPLL_FB_DIV_MASK,4,2         ; @VCEPLL_FB_DIV_MASK
	.comm	_VCEPLL_REF_DIV_MASK,4,2        ; @VCEPLL_REF_DIV_MASK
	.comm	_VCEPLL_PDIV_A_MASK,4,2         ; @VCEPLL_PDIV_A_MASK
	.comm	_VCEPLL_PDIV_B_MASK,4,2         ; @VCEPLL_PDIV_B_MASK
.subsections_via_symbols
