	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_uvd_init                ## -- Begin function radeon_uvd_init
	.p2align	4, 0x90
_radeon_uvd_init:                       ## @radeon_uvd_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	addq	$60, %rdi
	movq	_radeon_uvd_idle_work_handler@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_DELAYED_WORK
	movl	(%rbx), %ecx
	addl	$-128, %ecx
	cmpl	$32, %ecx
	ja	LBB0_7
## %bb.1:
	movq	_FIRMWARE_R600@GOTPCREL(%rip), %rax
	leaq	LJTI0_0(%rip), %rdx
	movslq	(%rdx,%rcx,4), %rcx
	addq	%rdx, %rcx
	jmpq	*%rcx
LBB0_5:
	movq	_FIRMWARE_SUMO@GOTPCREL(%rip), %rax
	jmp	LBB0_9
LBB0_6:
	movq	_FIRMWARE_TAHITI@GOTPCREL(%rip), %rax
	jmp	LBB0_9
LBB0_4:
	movq	_FIRMWARE_CYPRESS@GOTPCREL(%rip), %rax
	jmp	LBB0_9
LBB0_10:
	movq	_FIRMWARE_BONAIRE@GOTPCREL(%rip), %rax
	movq	(%rax), %r14
	movq	_FIRMWARE_BONAIRE_LEGACY@GOTPCREL(%rip), %rax
	movq	(%rax), %r15
	movl	$0, 8(%rbx)
	movq	_RADEON_DEFAULT_UVD_HANDLES@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	leaq	16(%rbx), %r13
	movq	%rax, 16(%rbx)
	testq	%r14, %r14
	je	LBB0_13
## %bb.11:
	leaq	72(%rbx), %r12
	movl	64(%rbx), %edx
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	_request_firmware
	testl	%eax, %eax
	je	LBB0_15
## %bb.12:
	movl	64(%rbx), %edi
	leaq	L_.str(%rip), %rsi
	movq	%r14, %rdx
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_13
LBB0_3:
	movq	_FIRMWARE_RV710@GOTPCREL(%rip), %rax
	jmp	LBB0_9
LBB0_8:
	movq	_FIRMWARE_RS780@GOTPCREL(%rip), %rax
	jmp	LBB0_9
LBB0_15:
	movq	(%r12), %rdi
	movq	8(%rdi), %r15
	callq	_radeon_ucode_validate
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	LBB0_32
## %bb.16:
	movl	$1, 8(%rbx)
	movl	(%r15), %edi
	callq	_le32_to_cpu
	movzbl	%al, %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movl	(%r15), %edi
	callq	_le32_to_cpu
	movl	%eax, %r14d
	movl	%eax, %r12d
	shrl	$24, %r12d
	movl	(%r15), %edi
	callq	_le32_to_cpu
	movzbl	%ah, %edx
	leaq	L_.str.1(%rip), %rdi
	movl	%r12d, %esi
	movl	%edx, %r15d
	movl	-44(%rbp), %ecx                 ## 4-byte Reload
	callq	_DRM_INFO
	cmpl	$16777216, %r14d                ## imm = 0x1000000
	jb	LBB0_19
## %bb.17:
	cmpl	$55, %r15d
	jb	LBB0_19
## %bb.18:
	movq	_RADEON_MAX_UVD_HANDLES@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, (%r13)
	jmp	LBB0_19
LBB0_7:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r14d, %r14d
	subl	(%rax), %r14d
	jmp	LBB0_32
LBB0_2:
	movq	_FIRMWARE_RV770@GOTPCREL(%rip), %rax
LBB0_9:
	movq	(%rax), %r15
	movl	$0, 8(%rbx)
	movq	_RADEON_DEFAULT_UVD_HANDLES@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	leaq	16(%rbx), %r13
	movq	%rax, 16(%rbx)
LBB0_13:
	leaq	72(%rbx), %rdi
	movl	64(%rbx), %edx
	movq	%r15, %rsi
	callq	_request_firmware
	testl	%eax, %eax
	je	LBB0_19
## %bb.14:
	movl	%eax, %r14d
	movl	64(%rbx), %edi
	leaq	L_.str(%rip), %rsi
	movq	%r15, %rdx
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_32
LBB0_19:
	movq	72(%rbx), %rax
	movq	(%rax), %rdi
	addq	$8, %rdi
	callq	_RADEON_GPU_PAGE_ALIGN
	movq	_RADEON_UVD_STACK_SIZE@GOTPCREL(%rip), %rcx
	addq	(%rcx), %rax
	movq	_RADEON_UVD_HEAP_SIZE@GOTPCREL(%rip), %rcx
	addq	(%rcx), %rax
	movq	_RADEON_UVD_SESSION_SIZE@GOTPCREL(%rip), %rcx
	movq	16(%rbx), %rsi
	imulq	(%rcx), %rsi
	addq	%rax, %rsi
	movq	_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_RADEON_GEM_DOMAIN_VRAM@GOTPCREL(%rip), %r12
	movl	(%r12), %r8d
	leaq	48(%rbx), %r15
	movq	%r15, 16(%rsp)
	xorps	%xmm0, %xmm0
	movups	%xmm0, (%rsp)
	movq	%rbx, %rdi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	_radeon_bo_create
	testl	%eax, %eax
	je	LBB0_22
## %bb.20:
	movl	%eax, %r14d
	movl	64(%rbx), %edi
	leaq	L_.str.2(%rip), %rsi
	jmp	LBB0_21
LBB0_22:
	movl	(%r15), %edi
	xorl	%esi, %esi
	callq	_radeon_bo_reserve
	testl	%eax, %eax
	je	LBB0_24
## %bb.23:
	movl	%eax, %r14d
	movq	%r15, %rdi
	callq	_radeon_bo_unref
	movl	64(%rbx), %edi
	leaq	L_.str.3(%rip), %rsi
	jmp	LBB0_21
LBB0_24:
	movl	48(%rbx), %edi
	movl	(%r12), %esi
	leaq	56(%rbx), %rdx
	callq	_radeon_bo_pin
	movl	48(%rbx), %edi
	testl	%eax, %eax
	je	LBB0_26
## %bb.25:
	movl	%eax, %r14d
	callq	_radeon_bo_unreserve
	movq	%r15, %rdi
	callq	_radeon_bo_unref
	movl	64(%rbx), %edi
	leaq	L_.str.4(%rip), %rsi
	jmp	LBB0_21
LBB0_26:
	leaq	52(%rbx), %rsi
	callq	_radeon_bo_kmap
	testl	%eax, %eax
	je	LBB0_28
## %bb.27:
	movl	%eax, %r14d
	movl	64(%rbx), %edi
	leaq	L_.str.5(%rip), %rsi
LBB0_21:
	movl	%r14d, %edx
	xorl	%eax, %eax
	callq	_dev_err
LBB0_32:
	movl	%r14d, %eax
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_28:
	movl	(%r15), %edi
	callq	_radeon_bo_unreserve
	cmpq	$0, (%r13)
	je	LBB0_29
## %bb.30:
	xorl	%r14d, %r14d
	xorl	%r15d, %r15d
	xorl	%r12d, %r12d
LBB0_31:                                ## =>This Inner Loop Header: Depth=1
	movq	40(%rbx), %rdi
	addq	%r15, %rdi
	xorl	%esi, %esi
	callq	_atomic_set
	movq	32(%rbx), %rax
	movq	$0, (%rax,%r15,2)
	movq	24(%rbx), %rax
	movq	$0, (%rax,%r15,2)
	incq	%r12
	addq	$4, %r15
	cmpq	%r12, 16(%rbx)
	ja	LBB0_31
	jmp	LBB0_32
LBB0_29:
	xorl	%r14d, %r14d
	jmp	LBB0_32
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_6, LBB0_6-LJTI0_0
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_2, LBB0_2-LJTI0_0
.set L0_0_set_3, LBB0_3-LJTI0_0
.set L0_0_set_9, LBB0_9-LJTI0_0
.set L0_0_set_8, LBB0_8-LJTI0_0
.set L0_0_set_4, LBB0_4-LJTI0_0
.set L0_0_set_10, LBB0_10-LJTI0_0
LJTI0_0:
	.long	L0_0_set_6
	.long	L0_0_set_5
	.long	L0_0_set_6
	.long	L0_0_set_5
	.long	L0_0_set_5
	.long	L0_0_set_2
	.long	L0_0_set_3
	.long	L0_0_set_3
	.long	L0_0_set_3
	.long	L0_0_set_9
	.long	L0_0_set_9
	.long	L0_0_set_9
	.long	L0_0_set_9
	.long	L0_0_set_9
	.long	L0_0_set_8
	.long	L0_0_set_8
	.long	L0_0_set_4
	.long	L0_0_set_6
	.long	L0_0_set_5
	.long	L0_0_set_6
	.long	L0_0_set_10
	.long	L0_0_set_10
	.long	L0_0_set_10
	.long	L0_0_set_4
	.long	L0_0_set_4
	.long	L0_0_set_10
	.long	L0_0_set_4
	.long	L0_0_set_4
	.long	L0_0_set_5
	.long	L0_0_set_5
	.long	L0_0_set_10
	.long	L0_0_set_5
	.long	L0_0_set_6
	.end_data_region
                                        ## -- End function
	.comm	_radeon_uvd_idle_work_handler,4,2 ## @radeon_uvd_idle_work_handler
	.comm	_FIRMWARE_R600,8,3              ## @FIRMWARE_R600
	.comm	_FIRMWARE_RS780,8,3             ## @FIRMWARE_RS780
	.comm	_FIRMWARE_RV770,8,3             ## @FIRMWARE_RV770
	.comm	_FIRMWARE_RV710,8,3             ## @FIRMWARE_RV710
	.comm	_FIRMWARE_CYPRESS,8,3           ## @FIRMWARE_CYPRESS
	.comm	_FIRMWARE_SUMO,8,3              ## @FIRMWARE_SUMO
	.comm	_FIRMWARE_TAHITI,8,3            ## @FIRMWARE_TAHITI
	.comm	_FIRMWARE_BONAIRE_LEGACY,8,3    ## @FIRMWARE_BONAIRE_LEGACY
	.comm	_FIRMWARE_BONAIRE,8,3           ## @FIRMWARE_BONAIRE
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_RADEON_DEFAULT_UVD_HANDLES,8,3 ## @RADEON_DEFAULT_UVD_HANDLES
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"radeon_uvd: Can't load firmware \"%s\"\n"

L_.str.1:                               ## @.str.1
	.asciz	"Found UVD firmware Version: %hu.%hu Family ID: %hu\n"

	.comm	_RADEON_MAX_UVD_HANDLES,8,3     ## @RADEON_MAX_UVD_HANDLES
	.comm	_RADEON_UVD_STACK_SIZE,8,3      ## @RADEON_UVD_STACK_SIZE
	.comm	_RADEON_UVD_HEAP_SIZE,8,3       ## @RADEON_UVD_HEAP_SIZE
	.comm	_RADEON_UVD_SESSION_SIZE,8,3    ## @RADEON_UVD_SESSION_SIZE
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
	.comm	_RADEON_GEM_DOMAIN_VRAM,4,2     ## @RADEON_GEM_DOMAIN_VRAM
L_.str.2:                               ## @.str.2
	.asciz	"(%d) failed to allocate UVD bo\n"

L_.str.3:                               ## @.str.3
	.asciz	"(%d) failed to reserve UVD bo\n"

L_.str.4:                               ## @.str.4
	.asciz	"(%d) UVD bo pin failed\n"

L_.str.5:                               ## @.str.5
	.asciz	"(%d) UVD map failed\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_uvd_init                ; -- Begin function radeon_uvd_init
	.p2align	2
_radeon_uvd_init:                       ; @radeon_uvd_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	add	x0, x0, #60
Lloh0:
	adrp	x8, _radeon_uvd_idle_work_handler@GOTPAGE
Lloh1:
	ldr	x8, [x8, _radeon_uvd_idle_work_handler@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	bl	_INIT_DELAYED_WORK
	ldr	w8, [x19]
	sub	w9, w8, #128
	cmp	w9, #32
	b.hi	LBB0_14
; %bb.1:
Lloh3:
	adrp	x8, _FIRMWARE_R600@GOTPAGE
Lloh4:
	ldr	x8, [x8, _FIRMWARE_R600@GOTPAGEOFF]
Lloh5:
	adrp	x10, lJTI0_0@PAGE
Lloh6:
	add	x10, x10, lJTI0_0@PAGEOFF
	adr	x11, LBB0_2
	ldrb	w12, [x10, x9]
	add	x11, x11, x12, lsl #2
	br	x11
LBB0_2:
Lloh7:
	adrp	x8, _FIRMWARE_SUMO@GOTPAGE
Lloh8:
	ldr	x8, [x8, _FIRMWARE_SUMO@GOTPAGEOFF]
	b	LBB0_16
LBB0_3:
Lloh9:
	adrp	x8, _FIRMWARE_TAHITI@GOTPAGE
Lloh10:
	ldr	x8, [x8, _FIRMWARE_TAHITI@GOTPAGEOFF]
	b	LBB0_16
LBB0_4:
Lloh11:
	adrp	x8, _FIRMWARE_CYPRESS@GOTPAGE
Lloh12:
	ldr	x8, [x8, _FIRMWARE_CYPRESS@GOTPAGEOFF]
	b	LBB0_16
LBB0_5:
Lloh13:
	adrp	x8, _FIRMWARE_BONAIRE@GOTPAGE
Lloh14:
	ldr	x8, [x8, _FIRMWARE_BONAIRE@GOTPAGEOFF]
Lloh15:
	ldr	x20, [x8]
Lloh16:
	adrp	x8, _FIRMWARE_BONAIRE_LEGACY@GOTPAGE
Lloh17:
	ldr	x8, [x8, _FIRMWARE_BONAIRE_LEGACY@GOTPAGEOFF]
Lloh18:
	adrp	x9, _RADEON_DEFAULT_UVD_HANDLES@GOTPAGE
Lloh19:
	ldr	x9, [x9, _RADEON_DEFAULT_UVD_HANDLES@GOTPAGEOFF]
Lloh20:
	ldr	x21, [x8]
Lloh21:
	ldr	x8, [x9]
	mov	x23, x19
	str	x8, [x23, #16]!
	stur	wzr, [x23, #-8]
	cbz	x20, LBB0_17
; %bb.6:
	add	x22, x19, #72
	ldr	w2, [x19, #64]
	mov	x0, x22
	mov	x1, x20
	bl	_request_firmware
	cbz	w0, LBB0_10
; %bb.7:
	ldr	w0, [x19, #64]
	str	x20, [sp]
Lloh22:
	adrp	x1, l_.str@PAGE
Lloh23:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
	b	LBB0_17
LBB0_8:
Lloh24:
	adrp	x8, _FIRMWARE_RV710@GOTPAGE
Lloh25:
	ldr	x8, [x8, _FIRMWARE_RV710@GOTPAGEOFF]
	b	LBB0_16
LBB0_9:
Lloh26:
	adrp	x8, _FIRMWARE_RS780@GOTPAGE
Lloh27:
	ldr	x8, [x8, _FIRMWARE_RS780@GOTPAGEOFF]
	b	LBB0_16
LBB0_10:
	ldr	x0, [x22]
	ldr	x24, [x0, #8]
	bl	_radeon_ucode_validate
	mov	x20, x0
	cbnz	w0, LBB0_28
; %bb.11:
	mov	w8, #1
	str	w8, [x19, #8]
	ldr	w0, [x24]
	bl	_le32_to_cpu
	and	w21, w0, #0xff
	ldr	w0, [x24]
	bl	_le32_to_cpu
	lsr	w22, w0, #24
	ldr	w0, [x24]
	bl	_le32_to_cpu
	ubfx	w20, w0, #8, #8
Lloh28:
	adrp	x0, l_.str.1@PAGE
Lloh29:
	add	x0, x0, l_.str.1@PAGEOFF
	mov	x1, x22
	mov	x2, x20
	mov	x3, x21
	bl	_DRM_INFO
	cbz	w22, LBB0_19
; %bb.12:
	cmp	w20, #55
	b.lo	LBB0_19
; %bb.13:
Lloh30:
	adrp	x8, _RADEON_MAX_UVD_HANDLES@GOTPAGE
Lloh31:
	ldr	x8, [x8, _RADEON_MAX_UVD_HANDLES@GOTPAGEOFF]
Lloh32:
	ldr	x8, [x8]
	str	x8, [x23]
	b	LBB0_19
LBB0_14:
Lloh33:
	adrp	x8, _EINVAL@GOTPAGE
Lloh34:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
	neg	w20, w8
	b	LBB0_28
LBB0_15:
Lloh36:
	adrp	x8, _FIRMWARE_RV770@GOTPAGE
Lloh37:
	ldr	x8, [x8, _FIRMWARE_RV770@GOTPAGEOFF]
LBB0_16:
Lloh38:
	adrp	x9, _RADEON_DEFAULT_UVD_HANDLES@GOTPAGE
Lloh39:
	ldr	x9, [x9, _RADEON_DEFAULT_UVD_HANDLES@GOTPAGEOFF]
	ldr	x21, [x8]
Lloh40:
	ldr	x8, [x9]
	mov	x23, x19
	str	x8, [x23, #16]!
	stur	wzr, [x23, #-8]
LBB0_17:
	add	x0, x19, #72
	ldr	w2, [x19, #64]
	mov	x1, x21
	bl	_request_firmware
	cbz	w0, LBB0_19
; %bb.18:
	mov	x20, x0
	ldr	w0, [x19, #64]
	str	x21, [sp]
Lloh41:
	adrp	x1, l_.str@PAGE
Lloh42:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
	b	LBB0_28
LBB0_19:
	ldr	x8, [x19, #72]
	ldr	x8, [x8]
	add	x0, x8, #8
	bl	_RADEON_GPU_PAGE_ALIGN
Lloh43:
	adrp	x8, _RADEON_UVD_STACK_SIZE@GOTPAGE
Lloh44:
	ldr	x8, [x8, _RADEON_UVD_STACK_SIZE@GOTPAGEOFF]
Lloh45:
	ldr	x8, [x8]
Lloh46:
	adrp	x9, _RADEON_UVD_HEAP_SIZE@GOTPAGE
Lloh47:
	ldr	x9, [x9, _RADEON_UVD_HEAP_SIZE@GOTPAGEOFF]
Lloh48:
	ldr	x9, [x9]
	add	x8, x8, x0
	add	x8, x8, x9
Lloh49:
	adrp	x9, _RADEON_UVD_SESSION_SIZE@GOTPAGE
Lloh50:
	ldr	x9, [x9, _RADEON_UVD_SESSION_SIZE@GOTPAGEOFF]
Lloh51:
	ldr	x9, [x9]
	ldr	x10, [x19, #16]
Lloh52:
	adrp	x11, _PAGE_SIZE@GOTPAGE
Lloh53:
	ldr	x11, [x11, _PAGE_SIZE@GOTPAGEOFF]
	madd	x1, x10, x9, x8
Lloh54:
	ldr	w2, [x11]
Lloh55:
	adrp	x22, _RADEON_GEM_DOMAIN_VRAM@GOTPAGE
Lloh56:
	ldr	x22, [x22, _RADEON_GEM_DOMAIN_VRAM@GOTPAGEOFF]
	ldr	w4, [x22]
	add	x21, x19, #48
	str	x21, [sp]
	mov	x0, x19
	mov	w3, #1
	mov	w5, #0
	mov	x6, #0
	mov	x7, #0
	bl	_radeon_bo_create
	cbz	w0, LBB0_21
; %bb.20:
	mov	x20, x0
	ldr	w0, [x19, #64]
	str	x20, [sp]
Lloh57:
	adrp	x1, l_.str.2@PAGE
Lloh58:
	add	x1, x1, l_.str.2@PAGEOFF
	bl	_dev_err
	b	LBB0_28
LBB0_21:
	ldr	w0, [x21]
	mov	w1, #0
	bl	_radeon_bo_reserve
	cbz	w0, LBB0_23
; %bb.22:
	mov	x20, x0
	mov	x0, x21
	bl	_radeon_bo_unref
	ldr	w0, [x19, #64]
	str	x20, [sp]
Lloh59:
	adrp	x1, l_.str.3@PAGE
Lloh60:
	add	x1, x1, l_.str.3@PAGEOFF
	b	LBB0_27
LBB0_23:
	ldr	w0, [x19, #48]
	ldr	w1, [x22]
	add	x2, x19, #56
	bl	_radeon_bo_pin
	mov	x20, x0
	ldr	w0, [x19, #48]
	cbz	w20, LBB0_25
; %bb.24:
	bl	_radeon_bo_unreserve
	mov	x0, x21
	bl	_radeon_bo_unref
	ldr	w0, [x19, #64]
	str	x20, [sp]
Lloh61:
	adrp	x1, l_.str.4@PAGE
Lloh62:
	add	x1, x1, l_.str.4@PAGEOFF
	b	LBB0_27
LBB0_25:
	add	x1, x19, #52
	bl	_radeon_bo_kmap
	cbz	w0, LBB0_29
; %bb.26:
	mov	x20, x0
	ldr	w0, [x19, #64]
	str	x20, [sp]
Lloh63:
	adrp	x1, l_.str.5@PAGE
Lloh64:
	add	x1, x1, l_.str.5@PAGEOFF
LBB0_27:
	bl	_dev_err
                                        ; kill: def $w20 killed $w20 killed $x20 def $x20
LBB0_28:
	mov	x0, x20
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
LBB0_29:
	ldr	w0, [x21]
	bl	_radeon_bo_unreserve
	ldr	x8, [x23]
	cbz	x8, LBB0_32
; %bb.30:
	mov	x21, #0
	mov	x22, #0
LBB0_31:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #40]
	add	x0, x8, x21
	mov	w1, #0
	bl	_atomic_set
	mov	w20, #0
	ldr	x8, [x19, #32]
	lsl	x9, x22, #3
	str	xzr, [x8, x9]
	ldr	x8, [x19, #24]
	str	xzr, [x8, x9]
	add	x22, x22, #1
	ldr	x8, [x19, #16]
	add	x21, x21, #4
	cmp	x8, x22
	b.hi	LBB0_31
	b	LBB0_28
LBB0_32:
	mov	w20, #0
	b	LBB0_28
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh20
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpAdd	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpAdd	Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpAdd	Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpAdd	Lloh57, Lloh58
	.loh AdrpAdd	Lloh59, Lloh60
	.loh AdrpAdd	Lloh61, Lloh62
	.loh AdrpAdd	Lloh63, Lloh64
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_3-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_3-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_15-LBB0_2)>>2
	.byte	(LBB0_8-LBB0_2)>>2
	.byte	(LBB0_8-LBB0_2)>>2
	.byte	(LBB0_8-LBB0_2)>>2
	.byte	(LBB0_16-LBB0_2)>>2
	.byte	(LBB0_16-LBB0_2)>>2
	.byte	(LBB0_16-LBB0_2)>>2
	.byte	(LBB0_16-LBB0_2)>>2
	.byte	(LBB0_16-LBB0_2)>>2
	.byte	(LBB0_9-LBB0_2)>>2
	.byte	(LBB0_9-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_3-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_3-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_3-LBB0_2)>>2
                                        ; -- End function
	.comm	_radeon_uvd_idle_work_handler,4,2 ; @radeon_uvd_idle_work_handler
	.comm	_FIRMWARE_R600,8,3              ; @FIRMWARE_R600
	.comm	_FIRMWARE_RS780,8,3             ; @FIRMWARE_RS780
	.comm	_FIRMWARE_RV770,8,3             ; @FIRMWARE_RV770
	.comm	_FIRMWARE_RV710,8,3             ; @FIRMWARE_RV710
	.comm	_FIRMWARE_CYPRESS,8,3           ; @FIRMWARE_CYPRESS
	.comm	_FIRMWARE_SUMO,8,3              ; @FIRMWARE_SUMO
	.comm	_FIRMWARE_TAHITI,8,3            ; @FIRMWARE_TAHITI
	.comm	_FIRMWARE_BONAIRE_LEGACY,8,3    ; @FIRMWARE_BONAIRE_LEGACY
	.comm	_FIRMWARE_BONAIRE,8,3           ; @FIRMWARE_BONAIRE
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_RADEON_DEFAULT_UVD_HANDLES,8,3 ; @RADEON_DEFAULT_UVD_HANDLES
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"radeon_uvd: Can't load firmware \"%s\"\n"

l_.str.1:                               ; @.str.1
	.asciz	"Found UVD firmware Version: %hu.%hu Family ID: %hu\n"

	.comm	_RADEON_MAX_UVD_HANDLES,8,3     ; @RADEON_MAX_UVD_HANDLES
	.comm	_RADEON_UVD_STACK_SIZE,8,3      ; @RADEON_UVD_STACK_SIZE
	.comm	_RADEON_UVD_HEAP_SIZE,8,3       ; @RADEON_UVD_HEAP_SIZE
	.comm	_RADEON_UVD_SESSION_SIZE,8,3    ; @RADEON_UVD_SESSION_SIZE
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
	.comm	_RADEON_GEM_DOMAIN_VRAM,4,2     ; @RADEON_GEM_DOMAIN_VRAM
l_.str.2:                               ; @.str.2
	.asciz	"(%d) failed to allocate UVD bo\n"

l_.str.3:                               ; @.str.3
	.asciz	"(%d) failed to reserve UVD bo\n"

l_.str.4:                               ; @.str.4
	.asciz	"(%d) UVD bo pin failed\n"

l_.str.5:                               ; @.str.5
	.asciz	"(%d) UVD map failed\n"

.subsections_via_symbols
