	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function analogix_dp_process_clock_recovery
_analogix_dp_process_clock_recovery:    ## @analogix_dp_process_clock_recovery
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -48(%rbp)
	movl	$100, %edi
	movl	$101, %esi
	callq	_usleep_range
	movl	(%r12), %r14d
	leaq	32(%r12), %r15
	movq	_DP_LANE0_1_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-64(%rbp), %rdx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	_drm_dp_dpcd_read
	testl	%eax, %eax
	js	LBB0_20
## %bb.1:
	movq	_DP_ADJUST_REQUEST_LANE0_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-80(%rbp), %rdx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	_drm_dp_dpcd_read
	testl	%eax, %eax
	js	LBB0_20
## %bb.2:
	leaq	-64(%rbp), %rdi
	movl	%r14d, %esi
	callq	_analogix_dp_clock_recovery_ok
	testq	%rax, %rax
	je	LBB0_7
## %bb.3:
	testl	%r14d, %r14d
	jle	LBB0_4
## %bb.6:
	movq	%r15, -88(%rbp)                 ## 8-byte Spill
	xorl	%ebx, %ebx
	movq	%r14, -96(%rbp)                 ## 8-byte Spill
	.p2align	4, 0x90
LBB0_13:                                ## =>This Inner Loop Header: Depth=1
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_analogix_dp_get_lane_link_training
	movq	%rax, %r14
	leaq	-80(%rbp), %r13
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_analogix_dp_get_adjust_request_voltage
	movq	%rax, %r15
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_analogix_dp_get_adjust_request_pre_emphasis
	movq	%rax, %r13
	movq	%r14, %rdi
	callq	_DPCD_VOLTAGE_SWING_GET
	cmpq	%r15, %rax
	jne	LBB0_16
## %bb.14:                              ##   in Loop: Header=BB0_13 Depth=1
	movq	%r14, %rdi
	callq	_DPCD_PRE_EMPHASIS_GET
	cmpq	%r13, %rax
	jne	LBB0_16
## %bb.15:                              ##   in Loop: Header=BB0_13 Depth=1
	movq	8(%r12), %rax
	incq	(%rax,%rbx,8)
LBB0_16:                                ##   in Loop: Header=BB0_13 Depth=1
	movq	8(%r12), %rax
	movq	(%rax,%rbx,8), %rdx
	movq	_MAX_CR_LOOP@GOTPCREL(%rip), %rax
	cmpq	(%rax), %rdx
	je	LBB0_19
## %bb.17:                              ##   in Loop: Header=BB0_13 Depth=1
	movq	_VOLTAGE_LEVEL_3@GOTPCREL(%rip), %rax
	cmpq	(%rax), %r15
	je	LBB0_19
## %bb.18:                              ##   in Loop: Header=BB0_13 Depth=1
	movq	_PRE_EMPHASIS_LEVEL_3@GOTPCREL(%rip), %rax
	cmpq	(%rax), %r13
	je	LBB0_19
## %bb.12:                              ##   in Loop: Header=BB0_13 Depth=1
	incq	%rbx
	movq	-96(%rbp), %r14                 ## 8-byte Reload
	cmpq	%rbx, %r14
	jne	LBB0_13
	jmp	LBB0_9
LBB0_7:
	movq	_TRAINING_PTN2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_analogix_dp_set_training_pattern
	movq	_DP_TRAINING_PATTERN_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DP_LINK_SCRAMBLING_DISABLE@GOTPCREL(%rip), %rax
	movq	_DP_TRAINING_PATTERN_2@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	%r15, %rdi
	callq	_drm_dp_dpcd_writeb
	testl	%eax, %eax
	js	LBB0_20
## %bb.8:
	movq	%r15, -88(%rbp)                 ## 8-byte Spill
	movl	36(%r12), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_dbg
	movq	_EQUALIZER_TRAINING@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 24(%r12)
LBB0_9:
	leaq	-80(%rbp), %rsi
	movq	%r12, %rdi
	callq	_analogix_dp_get_adjust_training_lane
	testl	%r14d, %r14d
	movq	-88(%rbp), %r15                 ## 8-byte Reload
	jle	LBB0_5
## %bb.10:
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_11:                                ## =>This Inner Loop Header: Depth=1
	movq	16(%r12), %rax
	movl	(%rax,%rbx,4), %esi
	movq	%r12, %rdi
	movl	%ebx, %edx
	callq	_analogix_dp_set_lane_link_training
	incq	%rbx
	cmpq	%rbx, %r14
	jne	LBB0_11
	jmp	LBB0_5
LBB0_4:
	leaq	-80(%rbp), %rsi
	movq	%r12, %rdi
	callq	_analogix_dp_get_adjust_training_lane
LBB0_5:
	movq	_DP_TRAINING_LANE0_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	16(%r12), %rdx
	movq	%r15, %rdi
	movl	%r14d, %ecx
	callq	_drm_dp_dpcd_write
	movl	%eax, %ecx
	sarl	$31, %eax
	andl	%ecx, %eax
	jmp	LBB0_20
LBB0_19:
	movl	36(%r12), %edi
	leaq	L_.str.1(%rip), %rsi
	movq	%r15, %rcx
	movq	%r13, %r8
	callq	_dev_err
	movq	%r12, %rdi
	callq	_analogix_dp_reduce_link_rate
	movq	_EIO@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_20:
	movq	___stack_chk_guard@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	cmpq	-48(%rbp), %rcx
	jne	LBB0_22
## %bb.21:
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_22:
	callq	___stack_chk_fail
	.cfi_endproc
                                        ## -- End function
	.comm	_DP_LANE0_1_STATUS,4,2          ## @DP_LANE0_1_STATUS
	.comm	_DP_ADJUST_REQUEST_LANE0_1,4,2  ## @DP_ADJUST_REQUEST_LANE0_1
	.comm	_TRAINING_PTN2,4,2              ## @TRAINING_PTN2
	.comm	_DP_TRAINING_PATTERN_SET,4,2    ## @DP_TRAINING_PATTERN_SET
	.comm	_DP_LINK_SCRAMBLING_DISABLE,4,2 ## @DP_LINK_SCRAMBLING_DISABLE
	.comm	_DP_TRAINING_PATTERN_2,4,2      ## @DP_TRAINING_PATTERN_2
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Link Training Clock Recovery success\n"

	.comm	_EQUALIZER_TRAINING,4,2         ## @EQUALIZER_TRAINING
	.comm	_MAX_CR_LOOP,8,3                ## @MAX_CR_LOOP
	.comm	_VOLTAGE_LEVEL_3,8,3            ## @VOLTAGE_LEVEL_3
	.comm	_PRE_EMPHASIS_LEVEL_3,8,3       ## @PRE_EMPHASIS_LEVEL_3
L_.str.1:                               ## @.str.1
	.asciz	"CR Max reached (%d,%d,%d)\n"

	.comm	_EIO,4,2                        ## @EIO
	.comm	_DP_TRAINING_LANE0_SET,4,2      ## @DP_TRAINING_LANE0_SET
	.no_dead_strip	_analogix_dp_process_clock_recovery
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function analogix_dp_process_clock_recovery
_analogix_dp_process_clock_recovery:    ; @analogix_dp_process_clock_recovery
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #144
	.cfi_def_cfa_offset 144
	stp	x28, x27, [sp, #48]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #64]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #80]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #96]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #112]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #128]            ; 16-byte Folded Spill
	add	x29, sp, #128
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
Lloh0:
	adrp	x8, ___stack_chk_guard@GOTPAGE
Lloh1:
	ldr	x8, [x8, ___stack_chk_guard@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	str	x8, [sp, #40]
	mov	w0, #100
	mov	w1, #101
	bl	_usleep_range
	mov	x21, x19
	ldr	w20, [x21], #32
Lloh3:
	adrp	x8, _DP_LANE0_1_STATUS@GOTPAGE
Lloh4:
	ldr	x8, [x8, _DP_LANE0_1_STATUS@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	add	x2, sp, #24
	mov	x0, x21
	mov	w3, #2
	bl	_drm_dp_dpcd_read
	tbnz	w0, #31, LBB0_18
; %bb.1:
Lloh6:
	adrp	x8, _DP_ADJUST_REQUEST_LANE0_1@GOTPAGE
Lloh7:
	ldr	x8, [x8, _DP_ADJUST_REQUEST_LANE0_1@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	add	x2, sp, #8
	mov	x0, x21
	mov	w3, #2
	bl	_drm_dp_dpcd_read
	tbnz	w0, #31, LBB0_18
; %bb.2:
	add	x0, sp, #24
	mov	x1, x20
	bl	_analogix_dp_clock_recovery_ok
	cbz	x0, LBB0_10
; %bb.3:
	cmp	w20, #0
	b.le	LBB0_15
; %bb.4:
	mov	x22, #0
Lloh9:
	adrp	x26, _MAX_CR_LOOP@GOTPAGE
Lloh10:
	ldr	x26, [x26, _MAX_CR_LOOP@GOTPAGEOFF]
Lloh11:
	adrp	x27, _VOLTAGE_LEVEL_3@GOTPAGE
Lloh12:
	ldr	x27, [x27, _VOLTAGE_LEVEL_3@GOTPAGEOFF]
Lloh13:
	adrp	x28, _PRE_EMPHASIS_LEVEL_3@GOTPAGE
Lloh14:
	ldr	x28, [x28, _PRE_EMPHASIS_LEVEL_3@GOTPAGEOFF]
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x19
	mov	x1, x22
	bl	_analogix_dp_get_lane_link_training
	mov	x25, x0
	add	x0, sp, #8
	mov	x1, x22
	bl	_analogix_dp_get_adjust_request_voltage
	mov	x23, x0
	add	x0, sp, #8
	mov	x1, x22
	bl	_analogix_dp_get_adjust_request_pre_emphasis
	mov	x24, x0
	mov	x0, x25
	bl	_DPCD_VOLTAGE_SWING_GET
	cmp	x0, x23
	b.ne	LBB0_8
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	mov	x0, x25
	bl	_DPCD_PRE_EMPHASIS_GET
	cmp	x0, x24
	b.ne	LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_5 Depth=1
	ldr	x8, [x19, #8]
	lsl	x9, x22, #3
	ldr	x10, [x8, x9]
	add	x10, x10, #1
	str	x10, [x8, x9]
LBB0_8:                                 ;   in Loop: Header=BB0_5 Depth=1
	ldr	x8, [x19, #8]
	ldr	x2, [x8, x22, lsl #3]
	ldr	x8, [x26]
	ldr	x9, [x27]
	ldr	x10, [x28]
	cmp	x2, x8
	ccmp	x23, x9, #4, ne
	ccmp	x24, x10, #4, ne
	b.eq	LBB0_17
; %bb.9:                                ;   in Loop: Header=BB0_5 Depth=1
	add	x22, x22, #1
	cmp	x20, x22
	b.ne	LBB0_5
	b	LBB0_12
LBB0_10:
Lloh15:
	adrp	x8, _TRAINING_PTN2@GOTPAGE
Lloh16:
	ldr	x8, [x8, _TRAINING_PTN2@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_analogix_dp_set_training_pattern
Lloh18:
	adrp	x8, _DP_TRAINING_PATTERN_SET@GOTPAGE
Lloh19:
	ldr	x8, [x8, _DP_TRAINING_PATTERN_SET@GOTPAGEOFF]
Lloh20:
	adrp	x9, _DP_LINK_SCRAMBLING_DISABLE@GOTPAGE
Lloh21:
	ldr	x9, [x9, _DP_LINK_SCRAMBLING_DISABLE@GOTPAGEOFF]
Lloh22:
	ldr	w1, [x8]
Lloh23:
	ldr	w8, [x9]
Lloh24:
	adrp	x9, _DP_TRAINING_PATTERN_2@GOTPAGE
Lloh25:
	ldr	x9, [x9, _DP_TRAINING_PATTERN_2@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x0, x21
	bl	_drm_dp_dpcd_writeb
	tbnz	w0, #31, LBB0_18
; %bb.11:
	ldr	w0, [x19, #36]
Lloh27:
	adrp	x1, l_.str@PAGE
Lloh28:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_dbg
Lloh29:
	adrp	x8, _EQUALIZER_TRAINING@GOTPAGE
Lloh30:
	ldr	x8, [x8, _EQUALIZER_TRAINING@GOTPAGEOFF]
Lloh31:
	ldr	w8, [x8]
	str	w8, [x19, #24]
LBB0_12:
	add	x1, sp, #8
	mov	x0, x19
	bl	_analogix_dp_get_adjust_training_lane
	cmp	w20, #1
	b.lt	LBB0_16
; %bb.13:
	mov	x22, #0
LBB0_14:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #16]
	ldr	w1, [x8, x22, lsl #2]
	mov	x0, x19
	mov	x2, x22
	bl	_analogix_dp_set_lane_link_training
	add	x22, x22, #1
	cmp	x20, x22
	b.ne	LBB0_14
	b	LBB0_16
LBB0_15:
	add	x1, sp, #8
	mov	x0, x19
	bl	_analogix_dp_get_adjust_training_lane
LBB0_16:
Lloh32:
	adrp	x8, _DP_TRAINING_LANE0_SET@GOTPAGE
Lloh33:
	ldr	x8, [x8, _DP_TRAINING_LANE0_SET@GOTPAGEOFF]
Lloh34:
	ldr	w1, [x8]
	ldr	x2, [x19, #16]
	mov	x0, x21
	mov	x3, x20
	bl	_drm_dp_dpcd_write
	cmp	w0, #0
	csel	w0, w0, wzr, lt
	b	LBB0_18
LBB0_17:
	ldr	w0, [x19, #36]
Lloh35:
	adrp	x1, l_.str.1@PAGE
Lloh36:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x3, x23
	mov	x4, x24
	bl	_dev_err
	mov	x0, x19
	bl	_analogix_dp_reduce_link_rate
Lloh37:
	adrp	x8, _EIO@GOTPAGE
Lloh38:
	ldr	x8, [x8, _EIO@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_18:
	ldr	x8, [sp, #40]
Lloh40:
	adrp	x9, ___stack_chk_guard@GOTPAGE
Lloh41:
	ldr	x9, [x9, ___stack_chk_guard@GOTPAGEOFF]
Lloh42:
	ldr	x9, [x9]
	cmp	x9, x8
	b.ne	LBB0_20
; %bb.19:
	ldp	x29, x30, [sp, #128]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #112]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #96]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #80]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #64]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #144
	ret
LBB0_20:
	bl	___stack_chk_fail
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh22
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpAdd	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpAdd	Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.cfi_endproc
                                        ; -- End function
	.comm	_DP_LANE0_1_STATUS,4,2          ; @DP_LANE0_1_STATUS
	.comm	_DP_ADJUST_REQUEST_LANE0_1,4,2  ; @DP_ADJUST_REQUEST_LANE0_1
	.comm	_TRAINING_PTN2,4,2              ; @TRAINING_PTN2
	.comm	_DP_TRAINING_PATTERN_SET,4,2    ; @DP_TRAINING_PATTERN_SET
	.comm	_DP_LINK_SCRAMBLING_DISABLE,4,2 ; @DP_LINK_SCRAMBLING_DISABLE
	.comm	_DP_TRAINING_PATTERN_2,4,2      ; @DP_TRAINING_PATTERN_2
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Link Training Clock Recovery success\n"

	.comm	_EQUALIZER_TRAINING,4,2         ; @EQUALIZER_TRAINING
	.comm	_MAX_CR_LOOP,8,3                ; @MAX_CR_LOOP
	.comm	_VOLTAGE_LEVEL_3,8,3            ; @VOLTAGE_LEVEL_3
	.comm	_PRE_EMPHASIS_LEVEL_3,8,3       ; @PRE_EMPHASIS_LEVEL_3
l_.str.1:                               ; @.str.1
	.asciz	"CR Max reached (%d,%d,%d)\n"

	.comm	_EIO,4,2                        ; @EIO
	.comm	_DP_TRAINING_LANE0_SET,4,2      ; @DP_TRAINING_LANE0_SET
	.no_dead_strip	_analogix_dp_process_clock_recovery
.subsections_via_symbols
