	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v1_0_jpeg_ring_emit_ib
_vcn_v1_0_jpeg_ring_emit_ib:            ## @vcn_v1_0_jpeg_ring_emit_ib
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r14
	movq	%rdi, %r15
	movq	%rsi, %rdi
	callq	_AMDGPU_JOB_GET_VMID
	movl	%eax, %r12d
	movq	_UVD@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movq	_mmUVD_LMI_JRBC_IB_VMID@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_PACKETJ_TYPE0@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	%r12d, %ebx
	shll	$4, %ebx
	orl	%r12d, %ebx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_LMI_JPEG_VMID@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_PACKETJ_TYPE0@GOTPCREL(%rip), %r12
	movl	(%r12), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r12), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	4(%r14), %edi
	callq	_lower_32_bits
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r12), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	4(%r14), %edi
	callq	_upper_32_bits
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_JRBC_IB_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r12), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	(%r14), %esi
	movq	%r15, %rdi
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r12), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	(%r15), %edi
	callq	_lower_32_bits
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r12), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movl	(%r15), %edi
	callq	_upper_32_bits
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	_PACKETJ_CONDITION_CHECK0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_PACKETJ_TYPE2@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%edi, %edi
	xorl	%esi, %esi
	callq	_PACKETJ
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_JRBC_RB_COND_RD_TIMER@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r12), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r15, %rdi
	movl	$20972032, %esi                 ## imm = 0x1400200
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_JRBC_RB_REF_DATA@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r12), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_PACKETJ
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r15, %rdi
	movl	$2, %esi
	callq	_amdgpu_ring_write
	movl	(%r13), %edi
	movq	_mmUVD_JRBC_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_PACKETJ_CONDITION_CHECK3@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_PACKETJ_TYPE3@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_PACKETJ
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_amdgpu_ring_write
	movq	%r15, %rdi
	movl	$2, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_amdgpu_ring_write              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_LMI_JRBC_IB_VMID,4,2     ## @mmUVD_LMI_JRBC_IB_VMID
	.comm	_PACKETJ_TYPE0,4,2              ## @PACKETJ_TYPE0
	.comm	_mmUVD_LMI_JPEG_VMID,4,2        ## @mmUVD_LMI_JPEG_VMID
	.comm	_mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH
	.comm	_mmUVD_JRBC_IB_SIZE,4,2         ## @mmUVD_JRBC_IB_SIZE
	.comm	_mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
	.comm	_PACKETJ_CONDITION_CHECK0,4,2   ## @PACKETJ_CONDITION_CHECK0
	.comm	_PACKETJ_TYPE2,4,2              ## @PACKETJ_TYPE2
	.comm	_mmUVD_JRBC_RB_COND_RD_TIMER,4,2 ## @mmUVD_JRBC_RB_COND_RD_TIMER
	.comm	_mmUVD_JRBC_RB_REF_DATA,4,2     ## @mmUVD_JRBC_RB_REF_DATA
	.comm	_mmUVD_JRBC_STATUS,4,2          ## @mmUVD_JRBC_STATUS
	.comm	_PACKETJ_CONDITION_CHECK3,4,2   ## @PACKETJ_CONDITION_CHECK3
	.comm	_PACKETJ_TYPE3,4,2              ## @PACKETJ_TYPE3
	.no_dead_strip	_vcn_v1_0_jpeg_ring_emit_ib
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v1_0_jpeg_ring_emit_ib
_vcn_v1_0_jpeg_ring_emit_ib:            ; @vcn_v1_0_jpeg_ring_emit_ib
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x2
	mov	x19, x0
	mov	x0, x1
	bl	_AMDGPU_JOB_GET_VMID
	mov	x21, x0
Lloh0:
	adrp	x22, _UVD@GOTPAGE
Lloh1:
	ldr	x22, [x22, _UVD@GOTPAGEOFF]
	ldr	w0, [x22]
Lloh2:
	adrp	x8, _mmUVD_LMI_JRBC_IB_VMID@GOTPAGE
Lloh3:
	ldr	x8, [x8, _mmUVD_LMI_JRBC_IB_VMID@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh5:
	adrp	x23, _PACKETJ_TYPE0@GOTPAGE
Lloh6:
	ldr	x23, [x23, _PACKETJ_TYPE0@GOTPAGEOFF]
	ldr	w3, [x23]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	orr	w21, w21, w21, lsl #4
	mov	x0, x19
	mov	x1, x21
	bl	_amdgpu_ring_write
	ldr	w0, [x22]
Lloh7:
	adrp	x8, _mmUVD_LMI_JPEG_VMID@GOTPAGE
Lloh8:
	ldr	x8, [x8, _mmUVD_LMI_JPEG_VMID@GOTPAGEOFF]
Lloh9:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w3, [x23]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	x1, x21
	bl	_amdgpu_ring_write
	ldr	w0, [x22]
Lloh10:
	adrp	x8, _mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW@GOTPAGE
Lloh11:
	ldr	x8, [x8, _mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh12:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w3, [x23]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x20, #4]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x22]
Lloh13:
	adrp	x8, _mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH@GOTPAGE
Lloh14:
	ldr	x8, [x8, _mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh15:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w3, [x23]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x20, #4]
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x22]
Lloh16:
	adrp	x8, _mmUVD_JRBC_IB_SIZE@GOTPAGE
Lloh17:
	ldr	x8, [x8, _mmUVD_JRBC_IB_SIZE@GOTPAGEOFF]
Lloh18:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w3, [x23]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w1, [x20]
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x22]
Lloh19:
	adrp	x8, _mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW@GOTPAGE
Lloh20:
	ldr	x8, [x8, _mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh21:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w3, [x23]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x19]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x22]
Lloh22:
	adrp	x8, _mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH@GOTPAGE
Lloh23:
	ldr	x8, [x8, _mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh24:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w3, [x23]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	ldr	w0, [x19]
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
Lloh25:
	adrp	x8, _PACKETJ_CONDITION_CHECK0@GOTPAGE
Lloh26:
	ldr	x8, [x8, _PACKETJ_CONDITION_CHECK0@GOTPAGEOFF]
Lloh27:
	ldr	w2, [x8]
Lloh28:
	adrp	x8, _PACKETJ_TYPE2@GOTPAGE
Lloh29:
	ldr	x8, [x8, _PACKETJ_TYPE2@GOTPAGEOFF]
Lloh30:
	ldr	w3, [x8]
	mov	w0, #0
	mov	w1, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #0
	bl	_amdgpu_ring_write
	ldr	w0, [x22]
Lloh31:
	adrp	x8, _mmUVD_JRBC_RB_COND_RD_TIMER@GOTPAGE
Lloh32:
	ldr	x8, [x8, _mmUVD_JRBC_RB_COND_RD_TIMER@GOTPAGEOFF]
Lloh33:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w3, [x23]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #512
	movk	w1, #320, lsl #16
	bl	_amdgpu_ring_write
	ldr	w0, [x22]
Lloh34:
	adrp	x8, _mmUVD_JRBC_RB_REF_DATA@GOTPAGE
Lloh35:
	ldr	x8, [x8, _mmUVD_JRBC_RB_REF_DATA@GOTPAGEOFF]
Lloh36:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w3, [x23]
	mov	w1, #0
	mov	w2, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #2
	bl	_amdgpu_ring_write
	ldr	w0, [x22]
Lloh37:
	adrp	x8, _mmUVD_JRBC_STATUS@GOTPAGE
Lloh38:
	ldr	x8, [x8, _mmUVD_JRBC_STATUS@GOTPAGEOFF]
Lloh39:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh40:
	adrp	x8, _PACKETJ_CONDITION_CHECK3@GOTPAGE
Lloh41:
	ldr	x8, [x8, _PACKETJ_CONDITION_CHECK3@GOTPAGEOFF]
Lloh42:
	ldr	w2, [x8]
Lloh43:
	adrp	x8, _PACKETJ_TYPE3@GOTPAGE
Lloh44:
	ldr	x8, [x8, _PACKETJ_TYPE3@GOTPAGEOFF]
Lloh45:
	ldr	w3, [x8]
	mov	w1, #0
	bl	_PACKETJ
	mov	x1, x0
	mov	x0, x19
	bl	_amdgpu_ring_write
	mov	x0, x19
	mov	w1, #2
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_amdgpu_ring_write
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_LMI_JRBC_IB_VMID,4,2     ; @mmUVD_LMI_JRBC_IB_VMID
	.comm	_PACKETJ_TYPE0,4,2              ; @PACKETJ_TYPE0
	.comm	_mmUVD_LMI_JPEG_VMID,4,2        ; @mmUVD_LMI_JPEG_VMID
	.comm	_mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH
	.comm	_mmUVD_JRBC_IB_SIZE,4,2         ; @mmUVD_JRBC_IB_SIZE
	.comm	_mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
	.comm	_PACKETJ_CONDITION_CHECK0,4,2   ; @PACKETJ_CONDITION_CHECK0
	.comm	_PACKETJ_TYPE2,4,2              ; @PACKETJ_TYPE2
	.comm	_mmUVD_JRBC_RB_COND_RD_TIMER,4,2 ; @mmUVD_JRBC_RB_COND_RD_TIMER
	.comm	_mmUVD_JRBC_RB_REF_DATA,4,2     ; @mmUVD_JRBC_RB_REF_DATA
	.comm	_mmUVD_JRBC_STATUS,4,2          ; @mmUVD_JRBC_STATUS
	.comm	_PACKETJ_CONDITION_CHECK3,4,2   ; @PACKETJ_CONDITION_CHECK3
	.comm	_PACKETJ_TYPE3,4,2              ; @PACKETJ_TYPE3
	.no_dead_strip	_vcn_v1_0_jpeg_ring_emit_ib
.subsections_via_symbols
