	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_ci_dpm_force_performance_level ## -- Begin function ci_dpm_force_performance_level
	.p2align	4, 0x90
_ci_dpm_force_performance_level:        ## @ci_dpm_force_performance_level
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %r15
	callq	_ci_get_pi
	movq	%rax, %r12
	movq	_RADEON_DPM_FORCED_LEVEL_HIGH@GOTPCREL(%rip), %rax
	cmpl	%r14d, (%rax)
	jne	LBB0_28
## %bb.1:
	cmpl	$0, (%r12)
	jne	LBB0_10
## %bb.2:
	movl	4(%r12), %eax
	cmpl	$2, %eax
	jae	LBB0_3
LBB0_10:
	cmpl	$0, 20(%r12)
	jne	LBB0_19
## %bb.11:
	movl	8(%r12), %eax
	cmpl	$2, %eax
	jae	LBB0_12
LBB0_19:
	cmpl	$0, 16(%r12)
	jne	LBB0_55
## %bb.20:
	movl	12(%r12), %eax
	cmpl	$2, %eax
	jb	LBB0_55
## %bb.21:
	xorl	%ebx, %ebx
	movl	%eax, %ecx
	.p2align	4, 0x90
LBB0_22:                                ## =>This Inner Loop Header: Depth=1
	sarl	%ecx
	incl	%ebx
	cmpl	$3, %eax
	movl	%ecx, %eax
	ja	LBB0_22
## %bb.23:
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_ci_dpm_force_state_mclk
	testl	%eax, %eax
	jne	LBB0_56
## %bb.24:
	cmpl	$0, (%r15)
	jle	LBB0_55
## %bb.25:
	xorl	%r12d, %r12d
	movq	_CURR_MCLK_INDEX_SHIFT@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_26:                                ## =>This Inner Loop Header: Depth=1
	movq	_TARGET_AND_CURRENT_PROFILE_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_SMC
	movq	_CURR_MCLK_INDEX_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movzbl	(%r13), %ecx
	sarl	%cl, %eax
	cmpl	%ebx, %eax
	je	LBB0_55
## %bb.27:                              ##   in Loop: Header=BB0_26 Depth=1
	movl	$1, %edi
	callq	_udelay
	incl	%r12d
	cmpl	(%r15), %r12d
	jl	LBB0_26
	jmp	LBB0_55
LBB0_28:
	movq	_RADEON_DPM_FORCED_LEVEL_LOW@GOTPCREL(%rip), %rax
	cmpl	%r14d, (%rax)
	jne	LBB0_50
## %bb.29:
	cmpl	$0, 20(%r12)
	je	LBB0_30
LBB0_36:
	cmpl	$0, 16(%r12)
	je	LBB0_37
LBB0_43:
	cmpl	$0, (%r12)
	jne	LBB0_55
## %bb.44:
	movl	4(%r12), %esi
	testl	%esi, %esi
	je	LBB0_55
## %bb.45:
	movq	%r15, %rdi
	callq	_ci_get_lowest_enabled_level
	movl	%eax, %r12d
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_ci_dpm_force_state_pcie
	testl	%eax, %eax
	jne	LBB0_56
## %bb.46:
	cmpl	$0, (%r15)
	jle	LBB0_55
## %bb.47:
	xorl	%ebx, %ebx
	movq	_CURR_PCIE_INDEX_SHIFT@GOTPCREL(%rip), %r13
LBB0_48:                                ## =>This Inner Loop Header: Depth=1
	movq	_TARGET_AND_CURRENT_PROFILE_INDEX_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_SMC
	movq	_CURR_PCIE_INDEX_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movzbl	(%r13), %ecx
	sarl	%cl, %eax
	cmpl	%r12d, %eax
	je	LBB0_55
## %bb.49:                              ##   in Loop: Header=BB0_48 Depth=1
	movl	$1, %edi
	callq	_udelay
	incl	%ebx
	cmpl	(%r15), %ebx
	jl	LBB0_48
	jmp	LBB0_55
LBB0_50:
	movq	_RADEON_DPM_FORCED_LEVEL_AUTO@GOTPCREL(%rip), %rax
	cmpl	%r14d, (%rax)
	jne	LBB0_55
## %bb.51:
	cmpl	$0, (%r12)
	jne	LBB0_54
## %bb.52:
	movq	_PPSMC_MSG_PCIeDPM_UnForceLevel@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_ci_send_msg_to_smc
	movq	_PPSMC_Result_OK@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_53
LBB0_54:
	movq	%r15, %rdi
	callq	_ci_upload_dpm_level_enable_mask
	testl	%eax, %eax
	jne	LBB0_56
LBB0_55:
	movl	%r14d, 4(%r15)
	xorl	%eax, %eax
LBB0_56:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_3:
	xorl	%ebx, %ebx
	movl	%eax, %ecx
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	sarl	%ecx
	incl	%ebx
	cmpl	$3, %eax
	movl	%ecx, %eax
	ja	LBB0_4
## %bb.5:
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_ci_dpm_force_state_pcie
	testl	%eax, %eax
	jne	LBB0_56
## %bb.6:
	cmpl	$0, (%r15)
	jle	LBB0_10
## %bb.7:
	xorl	%r13d, %r13d
	.p2align	4, 0x90
LBB0_8:                                 ## =>This Inner Loop Header: Depth=1
	movq	_TARGET_AND_CURRENT_PROFILE_INDEX_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_SMC
	movq	_CURR_PCIE_INDEX_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_CURR_PCIE_INDEX_SHIFT@GOTPCREL(%rip), %rcx
	movzbl	(%rcx), %ecx
	sarl	%cl, %eax
	cmpl	%ebx, %eax
	je	LBB0_10
## %bb.9:                               ##   in Loop: Header=BB0_8 Depth=1
	movl	$1, %edi
	callq	_udelay
	incl	%r13d
	cmpl	(%r15), %r13d
	jl	LBB0_8
	jmp	LBB0_10
LBB0_30:
	movl	8(%r12), %esi
	testl	%esi, %esi
	je	LBB0_36
## %bb.31:
	movq	%r15, %rdi
	callq	_ci_get_lowest_enabled_level
	movl	%eax, %r13d
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_ci_dpm_force_state_sclk
	testl	%eax, %eax
	jne	LBB0_56
## %bb.32:
	cmpl	$0, (%r15)
	jle	LBB0_36
## %bb.33:
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_34:                                ## =>This Inner Loop Header: Depth=1
	movq	_TARGET_AND_CURRENT_PROFILE_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_SMC
	movq	_CURR_SCLK_INDEX_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_CURR_SCLK_INDEX_SHIFT@GOTPCREL(%rip), %rcx
	movzbl	(%rcx), %ecx
	sarl	%cl, %eax
	cmpl	%r13d, %eax
	je	LBB0_36
## %bb.35:                              ##   in Loop: Header=BB0_34 Depth=1
	movl	$1, %edi
	callq	_udelay
	incl	%ebx
	cmpl	(%r15), %ebx
	jl	LBB0_34
	jmp	LBB0_36
LBB0_12:
	xorl	%ebx, %ebx
	movl	%eax, %ecx
	.p2align	4, 0x90
LBB0_13:                                ## =>This Inner Loop Header: Depth=1
	sarl	%ecx
	incl	%ebx
	cmpl	$3, %eax
	movl	%ecx, %eax
	ja	LBB0_13
## %bb.14:
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_ci_dpm_force_state_sclk
	testl	%eax, %eax
	jne	LBB0_56
## %bb.15:
	cmpl	$0, (%r15)
	jle	LBB0_19
## %bb.16:
	xorl	%r13d, %r13d
	.p2align	4, 0x90
LBB0_17:                                ## =>This Inner Loop Header: Depth=1
	movq	_TARGET_AND_CURRENT_PROFILE_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_SMC
	movq	_CURR_SCLK_INDEX_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_CURR_SCLK_INDEX_SHIFT@GOTPCREL(%rip), %rcx
	movzbl	(%rcx), %ecx
	sarl	%cl, %eax
	cmpl	%ebx, %eax
	je	LBB0_19
## %bb.18:                              ##   in Loop: Header=BB0_17 Depth=1
	movl	$1, %edi
	callq	_udelay
	incl	%r13d
	cmpl	(%r15), %r13d
	jl	LBB0_17
	jmp	LBB0_19
LBB0_37:
	movl	12(%r12), %esi
	testl	%esi, %esi
	je	LBB0_43
## %bb.38:
	movq	%r15, %rdi
	callq	_ci_get_lowest_enabled_level
	movl	%eax, %r13d
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_ci_dpm_force_state_mclk
	testl	%eax, %eax
	jne	LBB0_56
## %bb.39:
	cmpl	$0, (%r15)
	jle	LBB0_43
## %bb.40:
	xorl	%ebx, %ebx
LBB0_41:                                ## =>This Inner Loop Header: Depth=1
	movq	_TARGET_AND_CURRENT_PROFILE_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_SMC
	movq	_CURR_MCLK_INDEX_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_CURR_MCLK_INDEX_SHIFT@GOTPCREL(%rip), %rcx
	movzbl	(%rcx), %ecx
	sarl	%cl, %eax
	cmpl	%r13d, %eax
	je	LBB0_43
## %bb.42:                              ##   in Loop: Header=BB0_41 Depth=1
	movl	$1, %edi
	callq	_udelay
	incl	%ebx
	cmpl	(%r15), %ebx
	jl	LBB0_41
	jmp	LBB0_43
LBB0_53:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_56
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_DPM_FORCED_LEVEL_HIGH,4,2 ## @RADEON_DPM_FORCED_LEVEL_HIGH
	.comm	_TARGET_AND_CURRENT_PROFILE_INDEX_1,4,2 ## @TARGET_AND_CURRENT_PROFILE_INDEX_1
	.comm	_CURR_PCIE_INDEX_MASK,4,2       ## @CURR_PCIE_INDEX_MASK
	.comm	_CURR_PCIE_INDEX_SHIFT,4,2      ## @CURR_PCIE_INDEX_SHIFT
	.comm	_TARGET_AND_CURRENT_PROFILE_INDEX,4,2 ## @TARGET_AND_CURRENT_PROFILE_INDEX
	.comm	_CURR_SCLK_INDEX_MASK,4,2       ## @CURR_SCLK_INDEX_MASK
	.comm	_CURR_SCLK_INDEX_SHIFT,4,2      ## @CURR_SCLK_INDEX_SHIFT
	.comm	_CURR_MCLK_INDEX_MASK,4,2       ## @CURR_MCLK_INDEX_MASK
	.comm	_CURR_MCLK_INDEX_SHIFT,4,2      ## @CURR_MCLK_INDEX_SHIFT
	.comm	_RADEON_DPM_FORCED_LEVEL_LOW,4,2 ## @RADEON_DPM_FORCED_LEVEL_LOW
	.comm	_RADEON_DPM_FORCED_LEVEL_AUTO,4,2 ## @RADEON_DPM_FORCED_LEVEL_AUTO
	.comm	_PPSMC_MSG_PCIeDPM_UnForceLevel,4,2 ## @PPSMC_MSG_PCIeDPM_UnForceLevel
	.comm	_PPSMC_Result_OK,8,3            ## @PPSMC_Result_OK
	.comm	_EINVAL,4,2                     ## @EINVAL
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_ci_dpm_force_performance_level ; -- Begin function ci_dpm_force_performance_level
	.p2align	2
_ci_dpm_force_performance_level:        ; @ci_dpm_force_performance_level
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x1
	mov	x20, x0
	bl	_ci_get_pi
	mov	x21, x0
Lloh0:
	adrp	x8, _RADEON_DPM_FORCED_LEVEL_HIGH@GOTPAGE
Lloh1:
	ldr	x8, [x8, _RADEON_DPM_FORCED_LEVEL_HIGH@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cmp	w8, w19
	b.ne	LBB0_14
; %bb.1:
	ldr	w8, [x21]
	cbnz	w8, LBB0_3
; %bb.2:
	ldr	w8, [x21, #4]
	cmp	w8, #2
	b.hs	LBB0_30
LBB0_3:
	ldr	w8, [x21, #20]
	cbnz	w8, LBB0_5
; %bb.4:
	ldr	w8, [x21, #8]
	cmp	w8, #2
	b.hs	LBB0_43
LBB0_5:
	ldr	w8, [x21, #16]
	cbnz	w8, LBB0_28
; %bb.6:
	ldr	w8, [x21, #12]
	cmp	w8, #2
	b.lo	LBB0_28
; %bb.7:
	mov	w21, #0
LBB0_8:                                 ; =>This Inner Loop Header: Depth=1
	asr	w9, w8, #1
	add	w21, w21, #1
	cmp	w8, #3
	mov	x8, x9
	b.hi	LBB0_8
; %bb.9:
	mov	x0, x20
	mov	x1, x21
	bl	_ci_dpm_force_state_mclk
	cbnz	w0, LBB0_29
; %bb.10:
	ldr	w8, [x20]
	cmp	w8, #1
	b.lt	LBB0_28
; %bb.11:
	mov	w22, #0
Lloh3:
	adrp	x23, _TARGET_AND_CURRENT_PROFILE_INDEX@GOTPAGE
Lloh4:
	ldr	x23, [x23, _TARGET_AND_CURRENT_PROFILE_INDEX@GOTPAGEOFF]
Lloh5:
	adrp	x24, _CURR_MCLK_INDEX_MASK@GOTPAGE
Lloh6:
	ldr	x24, [x24, _CURR_MCLK_INDEX_MASK@GOTPAGEOFF]
Lloh7:
	adrp	x25, _CURR_MCLK_INDEX_SHIFT@GOTPAGE
Lloh8:
	ldr	x25, [x25, _CURR_MCLK_INDEX_SHIFT@GOTPAGEOFF]
LBB0_12:                                ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x23]
	bl	_RREG32_SMC
	ldr	w8, [x24]
	and	w8, w8, w0
	ldr	w9, [x25]
	asr	w8, w8, w9
	cmp	w8, w21
	b.eq	LBB0_28
; %bb.13:                               ;   in Loop: Header=BB0_12 Depth=1
	mov	w0, #1
	bl	_udelay
	add	w22, w22, #1
	ldr	w8, [x20]
	cmp	w22, w8
	b.lt	LBB0_12
	b	LBB0_28
LBB0_14:
Lloh9:
	adrp	x8, _RADEON_DPM_FORCED_LEVEL_LOW@GOTPAGE
Lloh10:
	ldr	x8, [x8, _RADEON_DPM_FORCED_LEVEL_LOW@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	cmp	w8, w19
	b.ne	LBB0_24
; %bb.15:
	ldr	w8, [x21, #20]
	cbz	w8, LBB0_37
LBB0_16:
	ldr	w8, [x21, #16]
	cbz	w8, LBB0_50
LBB0_17:
	ldr	w8, [x21]
	cbnz	w8, LBB0_28
; %bb.18:
	ldr	w1, [x21, #4]
	cbz	w1, LBB0_28
; %bb.19:
	mov	x0, x20
	bl	_ci_get_lowest_enabled_level
	mov	x21, x0
	mov	x0, x20
	mov	x1, x21
	bl	_ci_dpm_force_state_pcie
	cbnz	w0, LBB0_29
; %bb.20:
	ldr	w8, [x20]
	cmp	w8, #1
	b.lt	LBB0_28
; %bb.21:
	mov	w22, #0
Lloh12:
	adrp	x23, _TARGET_AND_CURRENT_PROFILE_INDEX_1@GOTPAGE
Lloh13:
	ldr	x23, [x23, _TARGET_AND_CURRENT_PROFILE_INDEX_1@GOTPAGEOFF]
Lloh14:
	adrp	x24, _CURR_PCIE_INDEX_MASK@GOTPAGE
Lloh15:
	ldr	x24, [x24, _CURR_PCIE_INDEX_MASK@GOTPAGEOFF]
Lloh16:
	adrp	x25, _CURR_PCIE_INDEX_SHIFT@GOTPAGE
Lloh17:
	ldr	x25, [x25, _CURR_PCIE_INDEX_SHIFT@GOTPAGEOFF]
LBB0_22:                                ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x23]
	bl	_RREG32_SMC
	ldr	w8, [x24]
	and	w8, w8, w0
	ldr	w9, [x25]
	asr	w8, w8, w9
	cmp	w8, w21
	b.eq	LBB0_28
; %bb.23:                               ;   in Loop: Header=BB0_22 Depth=1
	mov	w0, #1
	bl	_udelay
	add	w22, w22, #1
	ldr	w8, [x20]
	cmp	w22, w8
	b.lt	LBB0_22
	b	LBB0_28
LBB0_24:
Lloh18:
	adrp	x8, _RADEON_DPM_FORCED_LEVEL_AUTO@GOTPAGE
Lloh19:
	ldr	x8, [x8, _RADEON_DPM_FORCED_LEVEL_AUTO@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	cmp	w8, w19
	b.ne	LBB0_28
; %bb.25:
	ldr	w8, [x21]
	cbnz	w8, LBB0_27
; %bb.26:
Lloh21:
	adrp	x8, _PPSMC_MSG_PCIeDPM_UnForceLevel@GOTPAGE
Lloh22:
	ldr	x8, [x8, _PPSMC_MSG_PCIeDPM_UnForceLevel@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_ci_send_msg_to_smc
Lloh24:
	adrp	x8, _PPSMC_Result_OK@GOTPAGE
Lloh25:
	ldr	x8, [x8, _PPSMC_Result_OK@GOTPAGEOFF]
Lloh26:
	ldr	x8, [x8]
	cmp	x0, x8
	b.ne	LBB0_56
LBB0_27:
	mov	x0, x20
	bl	_ci_upload_dpm_level_enable_mask
	cbnz	w0, LBB0_29
LBB0_28:
	mov	w0, #0
	str	w19, [x20, #4]
LBB0_29:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_30:
	mov	w22, #0
LBB0_31:                                ; =>This Inner Loop Header: Depth=1
	asr	w9, w8, #1
	add	w22, w22, #1
	cmp	w8, #3
	mov	x8, x9
	b.hi	LBB0_31
; %bb.32:
	mov	x0, x20
	mov	x1, x19
	bl	_ci_dpm_force_state_pcie
	cbnz	w0, LBB0_29
; %bb.33:
	ldr	w8, [x20]
	cmp	w8, #1
	b.lt	LBB0_3
; %bb.34:
	mov	w23, #0
Lloh27:
	adrp	x24, _TARGET_AND_CURRENT_PROFILE_INDEX_1@GOTPAGE
Lloh28:
	ldr	x24, [x24, _TARGET_AND_CURRENT_PROFILE_INDEX_1@GOTPAGEOFF]
Lloh29:
	adrp	x25, _CURR_PCIE_INDEX_MASK@GOTPAGE
Lloh30:
	ldr	x25, [x25, _CURR_PCIE_INDEX_MASK@GOTPAGEOFF]
Lloh31:
	adrp	x26, _CURR_PCIE_INDEX_SHIFT@GOTPAGE
Lloh32:
	ldr	x26, [x26, _CURR_PCIE_INDEX_SHIFT@GOTPAGEOFF]
LBB0_35:                                ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x24]
	bl	_RREG32_SMC
	ldr	w8, [x25]
	and	w8, w8, w0
	ldr	w9, [x26]
	asr	w8, w8, w9
	cmp	w8, w22
	b.eq	LBB0_3
; %bb.36:                               ;   in Loop: Header=BB0_35 Depth=1
	mov	w0, #1
	bl	_udelay
	add	w23, w23, #1
	ldr	w8, [x20]
	cmp	w23, w8
	b.lt	LBB0_35
	b	LBB0_3
LBB0_37:
	ldr	w1, [x21, #8]
	cbz	w1, LBB0_16
; %bb.38:
	mov	x0, x20
	bl	_ci_get_lowest_enabled_level
	mov	x22, x0
	mov	x0, x20
	mov	x1, x22
	bl	_ci_dpm_force_state_sclk
	cbnz	w0, LBB0_29
; %bb.39:
	ldr	w8, [x20]
	cmp	w8, #1
	b.lt	LBB0_16
; %bb.40:
	mov	w23, #0
Lloh33:
	adrp	x24, _TARGET_AND_CURRENT_PROFILE_INDEX@GOTPAGE
Lloh34:
	ldr	x24, [x24, _TARGET_AND_CURRENT_PROFILE_INDEX@GOTPAGEOFF]
Lloh35:
	adrp	x25, _CURR_SCLK_INDEX_MASK@GOTPAGE
Lloh36:
	ldr	x25, [x25, _CURR_SCLK_INDEX_MASK@GOTPAGEOFF]
Lloh37:
	adrp	x26, _CURR_SCLK_INDEX_SHIFT@GOTPAGE
Lloh38:
	ldr	x26, [x26, _CURR_SCLK_INDEX_SHIFT@GOTPAGEOFF]
LBB0_41:                                ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x24]
	bl	_RREG32_SMC
	ldr	w8, [x25]
	and	w8, w8, w0
	ldr	w9, [x26]
	asr	w8, w8, w9
	cmp	w8, w22
	b.eq	LBB0_16
; %bb.42:                               ;   in Loop: Header=BB0_41 Depth=1
	mov	w0, #1
	bl	_udelay
	add	w23, w23, #1
	ldr	w8, [x20]
	cmp	w23, w8
	b.lt	LBB0_41
	b	LBB0_16
LBB0_43:
	mov	w22, #0
LBB0_44:                                ; =>This Inner Loop Header: Depth=1
	asr	w9, w8, #1
	add	w22, w22, #1
	cmp	w8, #3
	mov	x8, x9
	b.hi	LBB0_44
; %bb.45:
	mov	x0, x20
	mov	x1, x22
	bl	_ci_dpm_force_state_sclk
	cbnz	w0, LBB0_29
; %bb.46:
	ldr	w8, [x20]
	cmp	w8, #1
	b.lt	LBB0_5
; %bb.47:
	mov	w23, #0
Lloh39:
	adrp	x24, _TARGET_AND_CURRENT_PROFILE_INDEX@GOTPAGE
Lloh40:
	ldr	x24, [x24, _TARGET_AND_CURRENT_PROFILE_INDEX@GOTPAGEOFF]
Lloh41:
	adrp	x25, _CURR_SCLK_INDEX_MASK@GOTPAGE
Lloh42:
	ldr	x25, [x25, _CURR_SCLK_INDEX_MASK@GOTPAGEOFF]
Lloh43:
	adrp	x26, _CURR_SCLK_INDEX_SHIFT@GOTPAGE
Lloh44:
	ldr	x26, [x26, _CURR_SCLK_INDEX_SHIFT@GOTPAGEOFF]
LBB0_48:                                ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x24]
	bl	_RREG32_SMC
	ldr	w8, [x25]
	and	w8, w8, w0
	ldr	w9, [x26]
	asr	w8, w8, w9
	cmp	w8, w22
	b.eq	LBB0_5
; %bb.49:                               ;   in Loop: Header=BB0_48 Depth=1
	mov	w0, #1
	bl	_udelay
	add	w23, w23, #1
	ldr	w8, [x20]
	cmp	w23, w8
	b.lt	LBB0_48
	b	LBB0_5
LBB0_50:
	ldr	w1, [x21, #12]
	cbz	w1, LBB0_17
; %bb.51:
	mov	x0, x20
	bl	_ci_get_lowest_enabled_level
	mov	x22, x0
	mov	x0, x20
	mov	x1, x22
	bl	_ci_dpm_force_state_mclk
	cbnz	w0, LBB0_29
; %bb.52:
	ldr	w8, [x20]
	cmp	w8, #1
	b.lt	LBB0_17
; %bb.53:
	mov	w23, #0
Lloh45:
	adrp	x24, _TARGET_AND_CURRENT_PROFILE_INDEX@GOTPAGE
Lloh46:
	ldr	x24, [x24, _TARGET_AND_CURRENT_PROFILE_INDEX@GOTPAGEOFF]
Lloh47:
	adrp	x25, _CURR_MCLK_INDEX_MASK@GOTPAGE
Lloh48:
	ldr	x25, [x25, _CURR_MCLK_INDEX_MASK@GOTPAGEOFF]
Lloh49:
	adrp	x26, _CURR_MCLK_INDEX_SHIFT@GOTPAGE
Lloh50:
	ldr	x26, [x26, _CURR_MCLK_INDEX_SHIFT@GOTPAGEOFF]
LBB0_54:                                ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x24]
	bl	_RREG32_SMC
	ldr	w8, [x25]
	and	w8, w8, w0
	ldr	w9, [x26]
	asr	w8, w8, w9
	cmp	w8, w22
	b.eq	LBB0_17
; %bb.55:                               ;   in Loop: Header=BB0_54 Depth=1
	mov	w0, #1
	bl	_udelay
	add	w23, w23, #1
	ldr	w8, [x20]
	cmp	w23, w8
	b.lt	LBB0_54
	b	LBB0_17
LBB0_56:
Lloh51:
	adrp	x8, _EINVAL@GOTPAGE
Lloh52:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh53:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_29
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_DPM_FORCED_LEVEL_HIGH,4,2 ; @RADEON_DPM_FORCED_LEVEL_HIGH
	.comm	_TARGET_AND_CURRENT_PROFILE_INDEX_1,4,2 ; @TARGET_AND_CURRENT_PROFILE_INDEX_1
	.comm	_CURR_PCIE_INDEX_MASK,4,2       ; @CURR_PCIE_INDEX_MASK
	.comm	_CURR_PCIE_INDEX_SHIFT,4,2      ; @CURR_PCIE_INDEX_SHIFT
	.comm	_TARGET_AND_CURRENT_PROFILE_INDEX,4,2 ; @TARGET_AND_CURRENT_PROFILE_INDEX
	.comm	_CURR_SCLK_INDEX_MASK,4,2       ; @CURR_SCLK_INDEX_MASK
	.comm	_CURR_SCLK_INDEX_SHIFT,4,2      ; @CURR_SCLK_INDEX_SHIFT
	.comm	_CURR_MCLK_INDEX_MASK,4,2       ; @CURR_MCLK_INDEX_MASK
	.comm	_CURR_MCLK_INDEX_SHIFT,4,2      ; @CURR_MCLK_INDEX_SHIFT
	.comm	_RADEON_DPM_FORCED_LEVEL_LOW,4,2 ; @RADEON_DPM_FORCED_LEVEL_LOW
	.comm	_RADEON_DPM_FORCED_LEVEL_AUTO,4,2 ; @RADEON_DPM_FORCED_LEVEL_AUTO
	.comm	_PPSMC_MSG_PCIeDPM_UnForceLevel,4,2 ; @PPSMC_MSG_PCIeDPM_UnForceLevel
	.comm	_PPSMC_Result_OK,8,3            ; @PPSMC_Result_OK
	.comm	_EINVAL,4,2                     ; @EINVAL
.subsections_via_symbols
