	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ci_setup_default_pcie_tables
_ci_setup_default_pcie_tables:          ## @ci_setup_default_pcie_tables
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %r14
	callq	_ci_get_pi
	movq	%rax, %rbx
	cmpq	$0, 48(%rax)
	movq	40(%rax), %rax
	je	LBB0_1
## %bb.3:
	testq	%rax, %rax
	jne	LBB0_7
## %bb.4:
	movq	12(%rbx), %rax
	movq	%rax, 28(%rbx)
	leaq	20(%rbx), %rax
	movq	%rbx, %rcx
	addq	$4, %rcx
	jmp	LBB0_6
LBB0_1:
	testq	%rax, %rax
	je	LBB0_2
## %bb.5:
	movq	28(%rbx), %rax
	movq	%rax, 12(%rbx)
	leaq	4(%rbx), %rax
	movq	%rbx, %rcx
	addq	$20, %rcx
LBB0_6:
	movq	(%rcx), %rcx
	movq	%rcx, (%rax)
LBB0_7:
	movq	_SMU7_MAX_LEVELS_LINK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	_ci_reset_single_dpm_table
	movq	(%r14), %rax
	movq	_CHIP_BONAIRE@GOTPCREL(%rip), %rcx
	xorl	%esi, %esi
	cmpq	(%rcx), %rax
	setne	%sil
	movl	32(%rbx), %edx
	movl	20(%rbx,%rsi,4), %ecx
	xorl	%r14d, %r14d
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_ci_setup_pcie_table_entry
	movl	8(%rbx), %ecx
	movl	16(%rbx), %edx
	movq	%rbx, %rdi
	movl	$1, %esi
	callq	_ci_setup_pcie_table_entry
	movl	20(%rbx), %ecx
	movl	32(%rbx), %edx
	movq	%rbx, %rdi
	movl	$2, %esi
	callq	_ci_setup_pcie_table_entry
	movl	4(%rbx), %ecx
	movl	16(%rbx), %edx
	movq	%rbx, %rdi
	movl	$3, %esi
	callq	_ci_setup_pcie_table_entry
	movl	20(%rbx), %ecx
	movl	28(%rbx), %edx
	movq	%rbx, %rdi
	movl	$4, %esi
	callq	_ci_setup_pcie_table_entry
	movl	4(%rbx), %ecx
	movl	12(%rbx), %edx
	movq	%rbx, %rdi
	movl	$5, %esi
	callq	_ci_setup_pcie_table_entry
	movl	$6, (%rbx)
LBB0_8:
	movl	%r14d, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
LBB0_2:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r14d, %r14d
	subl	(%rax), %r14d
	jmp	LBB0_8
	.cfi_endproc
                                        ## -- End function
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_SMU7_MAX_LEVELS_LINK,4,2       ## @SMU7_MAX_LEVELS_LINK
	.comm	_CHIP_BONAIRE,8,3               ## @CHIP_BONAIRE
	.no_dead_strip	_ci_setup_default_pcie_tables
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ci_setup_default_pcie_tables
_ci_setup_default_pcie_tables:          ; @ci_setup_default_pcie_tables
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x20, x0
	bl	_ci_get_pi
	mov	x19, x0
	ldp	x8, x9, [x0, #40]
	cbz	x9, LBB0_3
; %bb.1:
	cbnz	x8, LBB0_6
; %bb.2:
	ldur	x8, [x19, #12]
	stur	x8, [x19, #28]
	add	x8, x19, #20
	add	x9, x19, #4
	b	LBB0_5
LBB0_3:
	cbz	x8, LBB0_8
; %bb.4:
	ldur	x8, [x19, #28]
	stur	x8, [x19, #12]
	add	x8, x19, #4
	add	x9, x19, #20
LBB0_5:
	ldr	x9, [x9]
	str	x9, [x8]
LBB0_6:
Lloh0:
	adrp	x8, _SMU7_MAX_LEVELS_LINK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _SMU7_MAX_LEVELS_LINK@GOTPAGEOFF]
Lloh2:
	ldr	w2, [x8]
	mov	x0, x20
	mov	x1, x19
	bl	_ci_reset_single_dpm_table
	ldr	x8, [x20]
Lloh3:
	adrp	x9, _CHIP_BONAIRE@GOTPAGE
Lloh4:
	ldr	x9, [x9, _CHIP_BONAIRE@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
	ldr	w2, [x19, #32]
	mov	w10, #24
	mov	w11, #20
	cmp	x8, x9
	csel	x8, x11, x10, eq
	ldr	w3, [x19, x8]
	mov	x0, x19
	mov	w1, #0
	bl	_ci_setup_pcie_table_entry
	ldr	w2, [x19, #16]
	ldr	w3, [x19, #8]
	mov	x0, x19
	mov	w1, #1
	bl	_ci_setup_pcie_table_entry
	ldr	w2, [x19, #32]
	ldr	w3, [x19, #20]
	mov	x0, x19
	mov	w1, #2
	bl	_ci_setup_pcie_table_entry
	ldr	w2, [x19, #16]
	ldr	w3, [x19, #4]
	mov	x0, x19
	mov	w1, #3
	bl	_ci_setup_pcie_table_entry
	ldr	w2, [x19, #28]
	ldr	w3, [x19, #20]
	mov	x0, x19
	mov	w1, #4
	bl	_ci_setup_pcie_table_entry
	ldr	w2, [x19, #12]
	ldr	w3, [x19, #4]
	mov	x0, x19
	mov	w1, #5
	bl	_ci_setup_pcie_table_entry
	mov	w0, #0
	mov	w8, #6
	str	w8, [x19]
LBB0_7:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_8:
Lloh6:
	adrp	x8, _EINVAL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_SMU7_MAX_LEVELS_LINK,4,2       ; @SMU7_MAX_LEVELS_LINK
	.comm	_CHIP_BONAIRE,8,3               ; @CHIP_BONAIRE
	.no_dead_strip	_ci_setup_default_pcie_tables
.subsections_via_symbols
