	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ad7124_setup
_ad7124_setup:                          ## @ad7124_setup
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movl	24(%rdi), %edi
	callq	_clk_get_rate
	testl	%eax, %eax
	je	LBB0_1
## %bb.2:
	movl	%eax, %ebx
	movq	_ad7124_master_clk_freq_hz@GOTPCREL(%rip), %r12
	movq	(%r12), %r14
	movq	%r14, %rdi
	callq	_ARRAY_SIZE
	movq	%r14, %rdi
	movl	%eax, %esi
	movl	%ebx, %edx
	callq	_ad7124_find_closest_match
	movl	%eax, %r14d
	movq	(%r12), %rax
	movl	%r14d, %ecx
	cmpl	(%rax,%rcx,4), %ebx
	je	LBB0_4
## %bb.3:
	movl	24(%r15), %edi
	movl	%ebx, %esi
	callq	_clk_set_rate
	testl	%eax, %eax
	jne	LBB0_11
LBB0_4:
	movq	_AD7124_ADC_CTRL_PWR_MSK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, (%r15)
	movl	%r14d, %edi
	callq	_AD7124_ADC_CTRL_PWR
	orl	(%r15), %eax
	movl	%eax, (%r15)
	leaq	8(%r15), %rdi
	movq	_AD7124_ADC_CONTROL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	%rdi, -48(%rbp)                 ## 8-byte Spill
	movl	$2, %edx
	movl	%eax, %ecx
	callq	_ad_sd_write_reg
	testl	%eax, %eax
	js	LBB0_11
## %bb.5:
	cmpl	$0, 4(%r15)
	jle	LBB0_11
## %bb.6:
	xorl	%r14d, %r14d
	xorl	%r12d, %r12d
	.p2align	4, 0x90
LBB0_7:                                 ## =>This Inner Loop Header: Depth=1
	movq	16(%r15), %rax
	movl	(%rax,%r14), %ebx
	movl	%r12d, %edi
	callq	_AD7124_CHANNEL_SETUP
	orl	%eax, %ebx
	movl	%r12d, %edi
	callq	_AD7124_CHANNEL
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movl	%eax, %esi
	movl	$2, %edx
	movl	%ebx, %ecx
	callq	_ad_sd_write_reg
	testl	%eax, %eax
	js	LBB0_11
## %bb.8:                               ##   in Loop: Header=BB0_7 Depth=1
	movq	%r15, %rdi
	movl	%r12d, %esi
	callq	_ad7124_init_channel_vref
	testl	%eax, %eax
	js	LBB0_11
## %bb.9:                               ##   in Loop: Header=BB0_7 Depth=1
	movq	16(%r15), %rax
	movl	4(%rax,%r14), %ebx
	movl	16(%rax,%r14), %edi
	addl	%ebx, %ebx
	addl	8(%rax,%r14), %ebx
	callq	_AD7124_CONFIG_BIPOLAR
	movl	%eax, %r13d
	movq	16(%r15), %rax
	movl	12(%rax,%r14), %edi
	callq	_AD7124_CONFIG_REF_SEL
	orl	%eax, %r13d
	movl	%ebx, %edi
	callq	_AD7124_CONFIG_IN_BUFF
	orl	%eax, %r13d
	movl	%r12d, %edi
	callq	_AD7124_CONFIG
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movl	%eax, %esi
	movl	$2, %edx
	movl	%r13d, %ecx
	callq	_ad_sd_write_reg
	testl	%eax, %eax
	js	LBB0_11
## %bb.10:                              ##   in Loop: Header=BB0_7 Depth=1
	movq	%r15, %rdi
	movl	%r12d, %esi
	movl	$10, %edx
	callq	_ad7124_set_channel_odr
	incq	%r12
	movslq	4(%r15), %rcx
	addq	$20, %r14
	cmpq	%rcx, %r12
	jl	LBB0_7
	jmp	LBB0_11
LBB0_1:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_11:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_ad7124_master_clk_freq_hz,8,3  ## @ad7124_master_clk_freq_hz
	.comm	_AD7124_ADC_CTRL_PWR_MSK,4,2    ## @AD7124_ADC_CTRL_PWR_MSK
	.comm	_AD7124_ADC_CONTROL,4,2         ## @AD7124_ADC_CONTROL
	.no_dead_strip	_ad7124_setup
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ad7124_setup
_ad7124_setup:                          ; @ad7124_setup
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	w0, [x0, #24]
	bl	_clk_get_rate
	cbz	w0, LBB0_10
; %bb.1:
	mov	x20, x0
Lloh0:
	adrp	x22, _ad7124_master_clk_freq_hz@GOTPAGE
Lloh1:
	ldr	x22, [x22, _ad7124_master_clk_freq_hz@GOTPAGEOFF]
	ldr	x21, [x22]
	mov	x0, x21
	bl	_ARRAY_SIZE
	mov	x1, x0
	mov	x0, x21
	mov	x2, x20
	bl	_ad7124_find_closest_match
	mov	x21, x0
	ldr	x8, [x22]
	ldr	w8, [x8, w0, uxtw #2]
	cmp	w20, w8
	b.eq	LBB0_3
; %bb.2:
	ldr	w0, [x19, #24]
	mov	x1, x20
	bl	_clk_set_rate
	cbnz	w0, LBB0_11
LBB0_3:
Lloh2:
	adrp	x8, _AD7124_ADC_CTRL_PWR_MSK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _AD7124_ADC_CTRL_PWR_MSK@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	ldr	w9, [x19]
	bic	w8, w9, w8
	str	w8, [x19]
	mov	x0, x21
	bl	_AD7124_ADC_CTRL_PWR
	ldr	w8, [x19]
	orr	w3, w8, w0
	mov	x20, x19
	str	w3, [x20], #8
Lloh5:
	adrp	x8, _AD7124_ADC_CONTROL@GOTPAGE
Lloh6:
	ldr	x8, [x8, _AD7124_ADC_CONTROL@GOTPAGEOFF]
Lloh7:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #2
	bl	_ad_sd_write_reg
	tbnz	w0, #31, LBB0_11
; %bb.4:
	ldr	w8, [x19, #4]
	cmp	w8, #1
	b.lt	LBB0_11
; %bb.5:
	mov	x24, #0
	mov	x21, #0
LBB0_6:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #16]
	ldr	w22, [x8, x24]
	mov	x0, x21
	bl	_AD7124_CHANNEL_SETUP
	orr	w22, w0, w22
	mov	x0, x21
	bl	_AD7124_CHANNEL
	mov	x1, x0
	mov	x0, x20
	mov	w2, #2
	mov	x3, x22
	bl	_ad_sd_write_reg
	tbnz	w0, #31, LBB0_11
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=1
	mov	x0, x19
	mov	x1, x21
	bl	_ad7124_init_channel_vref
	tbnz	w0, #31, LBB0_11
; %bb.8:                                ;   in Loop: Header=BB0_6 Depth=1
	ldr	x8, [x19, #16]
	add	x8, x8, x24
	ldp	w9, w10, [x8, #4]
	add	w22, w10, w9, lsl #1
	ldr	w0, [x8, #16]
	bl	_AD7124_CONFIG_BIPOLAR
	mov	x23, x0
	ldr	x8, [x19, #16]
	add	x8, x8, x24
	ldr	w0, [x8, #12]
	bl	_AD7124_CONFIG_REF_SEL
	orr	w23, w0, w23
	mov	x0, x22
	bl	_AD7124_CONFIG_IN_BUFF
	orr	w22, w23, w0
	mov	x0, x21
	bl	_AD7124_CONFIG
	mov	x1, x0
	mov	x0, x20
	mov	w2, #2
	mov	x3, x22
	bl	_ad_sd_write_reg
	tbnz	w0, #31, LBB0_11
; %bb.9:                                ;   in Loop: Header=BB0_6 Depth=1
	mov	x0, x19
	mov	x1, x21
	mov	w2, #10
	bl	_ad7124_set_channel_odr
	add	x21, x21, #1
	ldrsw	x8, [x19, #4]
	add	x24, x24, #20
	cmp	x21, x8
	b.lt	LBB0_6
	b	LBB0_11
LBB0_10:
Lloh8:
	adrp	x8, _EINVAL@GOTPAGE
Lloh9:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_11:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.cfi_endproc
                                        ; -- End function
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_ad7124_master_clk_freq_hz,8,3  ; @ad7124_master_clk_freq_hz
	.comm	_AD7124_ADC_CTRL_PWR_MSK,4,2    ; @AD7124_ADC_CTRL_PWR_MSK
	.comm	_AD7124_ADC_CONTROL,4,2         ; @AD7124_ADC_CONTROL
	.no_dead_strip	_ad7124_setup
.subsections_via_symbols
