	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function uvd_v6_0_early_init
_uvd_v6_0_early_init:                   ## @uvd_v6_0_early_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	movl	$1, 4(%rdi)
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rdi)
	je	LBB0_1
LBB0_3:
	movq	%rbx, %rdi
	callq	_uvd_v6_0_set_ring_funcs
	movq	%rbx, %rdi
	callq	_uvd_v6_0_enc_support
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	movl	$2, 8(%rbx)
	movq	%rbx, %rdi
	callq	_uvd_v6_0_set_enc_ring_funcs
LBB0_5:
	movq	%rbx, %rdi
	callq	_uvd_v6_0_set_irq_funcs
	xorl	%eax, %eax
	jmp	LBB0_6
LBB0_1:
	movq	_ixCC_HARVEST_FUSES@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32_SMC
	movq	_CC_HARVEST_FUSES__UVD_DISABLE_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_3
## %bb.2:
	movq	_ENOENT@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_6:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_ixCC_HARVEST_FUSES,4,2         ## @ixCC_HARVEST_FUSES
	.comm	_CC_HARVEST_FUSES__UVD_DISABLE_MASK,4,2 ## @CC_HARVEST_FUSES__UVD_DISABLE_MASK
	.comm	_ENOENT,4,2                     ## @ENOENT
	.no_dead_strip	_uvd_v6_0_early_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function uvd_v6_0_early_init
_uvd_v6_0_early_init:                   ; @uvd_v6_0_early_init
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	mov	w8, #1
	str	w8, [x0, #4]
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _AMD_IS_APU@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMD_IS_APU@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_4
LBB0_1:
	mov	x0, x19
	bl	_uvd_v6_0_set_ring_funcs
	mov	x0, x19
	bl	_uvd_v6_0_enc_support
	cbz	x0, LBB0_3
; %bb.2:
	mov	w8, #2
	str	w8, [x19, #8]
	mov	x0, x19
	bl	_uvd_v6_0_set_enc_ring_funcs
LBB0_3:
	mov	x0, x19
	bl	_uvd_v6_0_set_irq_funcs
	mov	w0, #0
	b	LBB0_6
LBB0_4:
Lloh3:
	adrp	x8, _ixCC_HARVEST_FUSES@GOTPAGE
Lloh4:
	ldr	x8, [x8, _ixCC_HARVEST_FUSES@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	bl	_RREG32_SMC
Lloh6:
	adrp	x8, _CC_HARVEST_FUSES__UVD_DISABLE_MASK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _CC_HARVEST_FUSES__UVD_DISABLE_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_1
; %bb.5:
Lloh9:
	adrp	x8, _ENOENT@GOTPAGE
Lloh10:
	ldr	x8, [x8, _ENOENT@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_6:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_ixCC_HARVEST_FUSES,4,2         ; @ixCC_HARVEST_FUSES
	.comm	_CC_HARVEST_FUSES__UVD_DISABLE_MASK,4,2 ; @CC_HARVEST_FUSES__UVD_DISABLE_MASK
	.comm	_ENOENT,4,2                     ; @ENOENT
	.no_dead_strip	_uvd_v6_0_early_init
.subsections_via_symbols
