	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gmc_v9_0_mc_init
_gmc_v9_0_mc_init:                      ## @gmc_v9_0_mc_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	leaq	8(%rbx), %r14
	movl	$2048, 8(%rbx)                  ## imm = 0x800
	jmp	LBB0_7
LBB0_2:
	movq	_amdgpu_emu_mode@GOTPCREL(%rip), %rax
	cmpl	$1, (%rax)
	jne	LBB0_4
## %bb.3:
	movl	8(%rbx), %eax
	jmp	LBB0_5
LBB0_4:
	movq	%rbx, %rdi
	callq	_amdgpu_atomfirmware_get_vram_width
	movl	%eax, 8(%rbx)
LBB0_5:
	leaq	8(%rbx), %r14
	testl	%eax, %eax
	jne	LBB0_7
## %bb.6:
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	xorl	%r15d, %r15d
	andl	(%rbx), %eax
	sete	%r15b
	shll	$6, %r15d
	addl	$64, %r15d
	movq	80(%rbx), %rax
	movq	%rbx, %rdi
	callq	*(%rax)
	imull	%r15d, %eax
	movl	%eax, 8(%rbx)
LBB0_7:
	movq	72(%rbx), %rax
	movq	%rbx, %rdi
	callq	*(%rax)
	shlq	$20, %rax
	movq	%rax, 16(%rbx)
	movq	%rax, 24(%rbx)
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rbx)
	je	LBB0_8
LBB0_9:
	movl	64(%rbx), %edi
	xorl	%esi, %esi
	callq	_pci_resource_start
	movl	%eax, 56(%rbx)
	movl	64(%rbx), %edi
	xorl	%esi, %esi
	callq	_pci_resource_len
	movq	%rax, 32(%rbx)
	movq	24(%rbx), %rcx
	cmpq	%rcx, %rax
	cmovbq	%rax, %rcx
	movq	%rcx, 40(%rbx)
	movq	_amdgpu_gart_size@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	cmpl	$-1, %eax
	je	LBB0_10
## %bb.13:
	shll	$20, %eax
	cltq
	movq	%rax, 48(%rbx)
	jmp	LBB0_14
LBB0_8:
	movq	%rbx, %rdi
	callq	_amdgpu_device_resize_fb_bar
	testl	%eax, %eax
	jne	LBB0_15
	jmp	LBB0_9
LBB0_10:
	movl	$-131, %eax
	addl	4(%rbx), %eax
	cmpl	$2, %eax
	jae	LBB0_11
## %bb.12:
	movq	$1073741824, 48(%rbx)           ## imm = 0x40000000
	jmp	LBB0_14
LBB0_11:
	movq	$536870912, 48(%rbx)            ## imm = 0x20000000
LBB0_14:
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	_gmc_v9_0_vram_gtt_location
	xorl	%eax, %eax
LBB0_15:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_amdgpu_emu_mode,4,2            ## @amdgpu_emu_mode
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_amdgpu_gart_size,4,2           ## @amdgpu_gart_size
	.no_dead_strip	_gmc_v9_0_mc_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gmc_v9_0_mc_init
_gmc_v9_0_mc_init:                      ; @gmc_v9_0_mc_init
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	bl	_amdgpu_sriov_vf
Lloh0:
	adrp	x21, _AMD_IS_APU@GOTPAGE
Lloh1:
	ldr	x21, [x21, _AMD_IS_APU@GOTPAGEOFF]
	cbz	x0, LBB0_2
; %bb.1:
	mov	w8, #2048
	mov	x20, x19
	str	w8, [x20, #8]!
	b	LBB0_6
LBB0_2:
Lloh2:
	adrp	x8, _amdgpu_emu_mode@GOTPAGE
Lloh3:
	ldr	x8, [x8, _amdgpu_emu_mode@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	cmp	w8, #1
	b.ne	LBB0_4
; %bb.3:
	ldr	w0, [x19, #8]
	add	x20, x19, #8
	cbnz	w0, LBB0_6
	b	LBB0_5
LBB0_4:
	mov	x0, x19
	bl	_amdgpu_atomfirmware_get_vram_width
	str	w0, [x19, #8]
	add	x20, x19, #8
	cbnz	w0, LBB0_6
LBB0_5:
	ldr	w8, [x19]
	ldr	w9, [x21]
	tst	w9, w8
	mov	w8, #64
	mov	w9, #128
	csel	w22, w9, w8, eq
	ldr	x8, [x19, #80]
	ldr	x8, [x8]
	mov	x0, x19
	blr	x8
	mul	w8, w0, w22
	str	w8, [x19, #8]
LBB0_6:
	ldr	x8, [x19, #72]
	ldr	x8, [x8]
	mov	x0, x19
	blr	x8
	lsl	x8, x0, #20
	stp	x8, x8, [x19, #16]
	ldr	w8, [x19]
	ldr	w9, [x21]
	tst	w9, w8
	b.eq	LBB0_9
LBB0_7:
	ldr	w0, [x19, #64]
	mov	w1, #0
	bl	_pci_resource_start
	str	w0, [x19, #56]
	ldr	w0, [x19, #64]
	mov	w1, #0
	bl	_pci_resource_len
	ldr	x8, [x19, #24]
	cmp	x0, x8
	csel	x8, x0, x8, lo
	stp	x0, x8, [x19, #32]
Lloh5:
	adrp	x8, _amdgpu_gart_size@GOTPAGE
Lloh6:
	ldr	x8, [x8, _amdgpu_gart_size@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	cmn	w8, #1
	b.eq	LBB0_10
; %bb.8:
	lsl	w8, w8, #20
	sxtw	x8, w8
	b	LBB0_13
LBB0_9:
	mov	x0, x19
	bl	_amdgpu_device_resize_fb_bar
	cbnz	w0, LBB0_14
	b	LBB0_7
LBB0_10:
	ldr	w8, [x19, #4]
	sub	w8, w8, #131
	cmp	w8, #2
	b.hs	LBB0_12
; %bb.11:
	mov	w8, #1073741824
	b	LBB0_13
LBB0_12:
	mov	w8, #536870912
LBB0_13:
	str	x8, [x19, #48]
	mov	x0, x19
	mov	x1, x20
	bl	_gmc_v9_0_vram_gtt_location
	mov	w0, #0
LBB0_14:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.cfi_endproc
                                        ; -- End function
	.comm	_amdgpu_emu_mode,4,2            ; @amdgpu_emu_mode
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_amdgpu_gart_size,4,2           ; @amdgpu_gart_size
	.no_dead_strip	_gmc_v9_0_mc_init
.subsections_via_symbols
