	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function si_dma_set_clockgating_state
_si_dma_set_clockgating_state:          ## @si_dma_set_clockgating_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_AMD_CG_STATE_GATE@GOTPCREL(%rip), %rax
	cmpl	%esi, (%rax)
	jne	LBB0_9
## %bb.1:
	movq	_AMD_CG_SUPPORT_SDMA_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r14)
	je	LBB0_9
## %bb.2:
	cmpl	$0, 4(%r14)
	jle	LBB0_18
## %bb.3:
	xorl	%r15d, %r15d
	movq	_DMA_POWER_CNTL@GOTPCREL(%rip), %r13
	movq	_DMA_CLK_CTRL@GOTPCREL(%rip), %r12
	jmp	LBB0_4
	.p2align	4, 0x90
LBB0_8:                                 ##   in Loop: Header=BB0_4 Depth=1
	addl	(%r12), %ebx
	movl	%ebx, %edi
	movl	$256, %esi                      ## imm = 0x100
	callq	_WREG32
	incl	%r15d
	cmpl	4(%r14), %r15d
	jge	LBB0_18
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movq	_DMA1_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	testl	%r15d, %r15d
	jne	LBB0_6
## %bb.5:                               ##   in Loop: Header=BB0_4 Depth=1
	movq	_DMA0_REGISTER_OFFSET@GOTPCREL(%rip), %rax
LBB0_6:                                 ##   in Loop: Header=BB0_4 Depth=1
	movl	(%rax), %ebx
	movl	(%r13), %edi
	addl	%ebx, %edi
	callq	_RREG32
	movq	_MEM_POWER_OVERRIDE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	cmpl	%eax, %esi
	je	LBB0_8
## %bb.7:                               ##   in Loop: Header=BB0_4 Depth=1
	movl	(%r13), %edi
	addl	%ebx, %edi
	callq	_WREG32
	jmp	LBB0_8
LBB0_9:
	cmpl	$0, 4(%r14)
	jle	LBB0_18
## %bb.10:
	xorl	%ebx, %ebx
	movq	_DMA_POWER_CNTL@GOTPCREL(%rip), %r13
	movq	_DMA_CLK_CTRL@GOTPCREL(%rip), %r12
	jmp	LBB0_11
	.p2align	4, 0x90
LBB0_17:                                ##   in Loop: Header=BB0_11 Depth=1
	incl	%ebx
	cmpl	4(%r14), %ebx
	jge	LBB0_18
LBB0_11:                                ## =>This Inner Loop Header: Depth=1
	movq	_DMA1_REGISTER_OFFSET@GOTPCREL(%rip), %rax
	testl	%ebx, %ebx
	jne	LBB0_13
## %bb.12:                              ##   in Loop: Header=BB0_11 Depth=1
	movq	_DMA0_REGISTER_OFFSET@GOTPCREL(%rip), %rax
LBB0_13:                                ##   in Loop: Header=BB0_11 Depth=1
	movl	(%rax), %r15d
	movl	(%r13), %edi
	addl	%r15d, %edi
	callq	_RREG32
	movq	_MEM_POWER_OVERRIDE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	%eax, %esi
	cmpl	%eax, %esi
	je	LBB0_15
## %bb.14:                              ##   in Loop: Header=BB0_11 Depth=1
	movl	(%r13), %edi
	addl	%r15d, %edi
	callq	_WREG32
LBB0_15:                                ##   in Loop: Header=BB0_11 Depth=1
	movl	(%r12), %edi
	addl	%r15d, %edi
	callq	_RREG32
	cmpl	$-16777216, %eax                ## imm = 0xFF000000
	je	LBB0_17
## %bb.16:                              ##   in Loop: Header=BB0_11 Depth=1
	addl	(%r12), %r15d
	movl	%r15d, %edi
	movl	$-16777216, %esi                ## imm = 0xFF000000
	callq	_WREG32
	jmp	LBB0_17
LBB0_18:
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_CG_STATE_GATE,4,2          ## @AMD_CG_STATE_GATE
	.comm	_AMD_CG_SUPPORT_SDMA_MGCG,4,2   ## @AMD_CG_SUPPORT_SDMA_MGCG
	.comm	_DMA0_REGISTER_OFFSET,4,2       ## @DMA0_REGISTER_OFFSET
	.comm	_DMA1_REGISTER_OFFSET,4,2       ## @DMA1_REGISTER_OFFSET
	.comm	_DMA_POWER_CNTL,4,2             ## @DMA_POWER_CNTL
	.comm	_MEM_POWER_OVERRIDE,4,2         ## @MEM_POWER_OVERRIDE
	.comm	_DMA_CLK_CTRL,4,2               ## @DMA_CLK_CTRL
	.no_dead_strip	_si_dma_set_clockgating_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function si_dma_set_clockgating_state
_si_dma_set_clockgating_state:          ; @si_dma_set_clockgating_state
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
Lloh0:
	adrp	x8, _AMD_CG_STATE_GATE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMD_CG_STATE_GATE@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cmp	w8, w1
	b.ne	LBB0_7
; %bb.1:
	ldr	w8, [x19]
Lloh3:
	adrp	x9, _AMD_CG_SUPPORT_SDMA_MGCG@GOTPAGE
Lloh4:
	ldr	x9, [x9, _AMD_CG_SUPPORT_SDMA_MGCG@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_7
; %bb.2:
	ldr	w8, [x19, #4]
	cmp	w8, #1
	b.lt	LBB0_14
; %bb.3:
	mov	w20, #0
Lloh6:
	adrp	x21, _DMA0_REGISTER_OFFSET@GOTPAGE
Lloh7:
	ldr	x21, [x21, _DMA0_REGISTER_OFFSET@GOTPAGEOFF]
Lloh8:
	adrp	x22, _DMA1_REGISTER_OFFSET@GOTPAGE
Lloh9:
	ldr	x22, [x22, _DMA1_REGISTER_OFFSET@GOTPAGEOFF]
Lloh10:
	adrp	x23, _DMA_POWER_CNTL@GOTPAGE
Lloh11:
	ldr	x23, [x23, _DMA_POWER_CNTL@GOTPAGEOFF]
Lloh12:
	adrp	x24, _MEM_POWER_OVERRIDE@GOTPAGE
Lloh13:
	ldr	x24, [x24, _MEM_POWER_OVERRIDE@GOTPAGEOFF]
Lloh14:
	adrp	x25, _DMA_CLK_CTRL@GOTPAGE
Lloh15:
	ldr	x25, [x25, _DMA_CLK_CTRL@GOTPAGEOFF]
	b	LBB0_5
LBB0_4:                                 ;   in Loop: Header=BB0_5 Depth=1
	ldr	w8, [x25]
	add	w0, w8, w26
	mov	w1, #256
	bl	_WREG32
	add	w20, w20, #1
	ldr	w8, [x19, #4]
	cmp	w20, w8
	b.ge	LBB0_14
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	cmp	w20, #0
	csel	x8, x21, x22, eq
	ldr	w26, [x8]
	ldr	w8, [x23]
	add	w0, w8, w26
	bl	_RREG32
	ldr	w8, [x24]
	bic	w1, w0, w8
	cmp	w1, w0
	b.eq	LBB0_4
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	ldr	w8, [x23]
	add	w0, w8, w26
	bl	_WREG32
	b	LBB0_4
LBB0_7:
	ldr	w8, [x19, #4]
	cmp	w8, #1
	b.lt	LBB0_14
; %bb.8:
	mov	w20, #0
Lloh16:
	adrp	x21, _DMA0_REGISTER_OFFSET@GOTPAGE
Lloh17:
	ldr	x21, [x21, _DMA0_REGISTER_OFFSET@GOTPAGEOFF]
Lloh18:
	adrp	x22, _DMA1_REGISTER_OFFSET@GOTPAGE
Lloh19:
	ldr	x22, [x22, _DMA1_REGISTER_OFFSET@GOTPAGEOFF]
Lloh20:
	adrp	x23, _DMA_POWER_CNTL@GOTPAGE
Lloh21:
	ldr	x23, [x23, _DMA_POWER_CNTL@GOTPAGEOFF]
Lloh22:
	adrp	x24, _MEM_POWER_OVERRIDE@GOTPAGE
Lloh23:
	ldr	x24, [x24, _MEM_POWER_OVERRIDE@GOTPAGEOFF]
	mov	w25, #-16777216
Lloh24:
	adrp	x26, _DMA_CLK_CTRL@GOTPAGE
Lloh25:
	ldr	x26, [x26, _DMA_CLK_CTRL@GOTPAGEOFF]
	b	LBB0_10
LBB0_9:                                 ;   in Loop: Header=BB0_10 Depth=1
	add	w20, w20, #1
	ldr	w8, [x19, #4]
	cmp	w20, w8
	b.ge	LBB0_14
LBB0_10:                                ; =>This Inner Loop Header: Depth=1
	cmp	w20, #0
	csel	x8, x21, x22, eq
	ldr	w27, [x8]
	ldr	w8, [x23]
	add	w0, w8, w27
	bl	_RREG32
	ldr	w8, [x24]
	orr	w1, w8, w0
	cmp	w1, w0
	b.eq	LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_10 Depth=1
	ldr	w8, [x23]
	add	w0, w8, w27
	bl	_WREG32
LBB0_12:                                ;   in Loop: Header=BB0_10 Depth=1
	ldr	w8, [x26]
	add	w0, w8, w27
	bl	_RREG32
	cmp	w0, w25
	b.eq	LBB0_9
; %bb.13:                               ;   in Loop: Header=BB0_10 Depth=1
	ldr	w8, [x26]
	add	w0, w8, w27
	mov	w1, #-16777216
	bl	_WREG32
	b	LBB0_9
LBB0_14:
	mov	w0, #0
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh16, Lloh17
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_CG_STATE_GATE,4,2          ; @AMD_CG_STATE_GATE
	.comm	_AMD_CG_SUPPORT_SDMA_MGCG,4,2   ; @AMD_CG_SUPPORT_SDMA_MGCG
	.comm	_DMA0_REGISTER_OFFSET,4,2       ; @DMA0_REGISTER_OFFSET
	.comm	_DMA1_REGISTER_OFFSET,4,2       ; @DMA1_REGISTER_OFFSET
	.comm	_DMA_POWER_CNTL,4,2             ; @DMA_POWER_CNTL
	.comm	_MEM_POWER_OVERRIDE,4,2         ; @MEM_POWER_OVERRIDE
	.comm	_DMA_CLK_CTRL,4,2               ; @DMA_CLK_CTRL
	.no_dead_strip	_si_dma_set_clockgating_state
.subsections_via_symbols
