	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v9_0_init_rlc_microcode
_gfx_v9_0_init_rlc_microcode:           ## @gfx_v9_0_init_rlc_microcode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %r15
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -48(%rbp)
	leaq	L_.str(%rip), %rsi
	movq	%r14, %rdi
	callq	_strcmp
	testl	%eax, %eax
	jne	LBB0_3
## %bb.1:
	movq	168(%r15), %rax
	movl	(%rax), %eax
	andl	$-24, %eax
	cmpl	$200, %eax
	jne	LBB0_3
## %bb.2:
	leaq	L_.str.1(%rip), %rdx
	jmp	LBB0_8
LBB0_3:
	leaq	L_.str.2(%rip), %rsi
	movq	%r14, %rdi
	callq	_strcmp
	testl	%eax, %eax
	je	LBB0_4
LBB0_7:
	leaq	L_.str.4(%rip), %rdx
LBB0_8:
	leaq	-80(%rbp), %rbx
	movq	%rbx, %rdi
	movl	$30, %esi
	movq	%r14, %rcx
	callq	_snprintf
	movl	136(%r15), %edx
	movq	%r15, %rdi
	movq	%rbx, %rsi
	callq	_request_firmware
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	LBB0_31
## %bb.9:
	movq	(%r15), %rdi
	callq	_amdgpu_ucode_validate
	movl	%eax, %r14d
	movq	(%r15), %rax
	movq	(%rax), %r12
	movl	56(%r12), %edi
	callq	_le16_to_cpu
	movl	%eax, %ebx
	movl	52(%r12), %edi
	callq	_le16_to_cpu
	cmpl	$2, %ebx
	jne	LBB0_12
## %bb.10:
	cmpl	$1, %eax
	jne	LBB0_12
## %bb.11:
	movl	$1, 8(%r15)
LBB0_12:
	movl	48(%r12), %edi
	callq	_le32_to_cpu
	movq	%rax, 128(%r15)
	movl	(%r12), %edi
	callq	_le32_to_cpu
	movq	%rax, 120(%r15)
	movl	4(%r12), %edi
	callq	_le32_to_cpu
	movq	%rax, 112(%r15)
	movl	8(%r12), %edi
	callq	_le32_to_cpu
	movq	%rax, 104(%r15)
	movl	12(%r12), %edi
	callq	_le32_to_cpu
	movq	%rax, 96(%r15)
	movl	16(%r12), %edi
	callq	_le32_to_cpu
	movq	%rax, 88(%r15)
	movl	20(%r12), %edi
	callq	_le32_to_cpu
	movq	%rax, 80(%r15)
	movl	24(%r12), %edi
	callq	_le32_to_cpu
	movq	%rax, 72(%r15)
	movl	28(%r12), %edi
	callq	_le32_to_cpu
	movq	%rax, 64(%r15)
	movl	32(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, 12(%r15)
	movl	36(%r12), %edi
	callq	_le32_to_cpu
	movl	%eax, 16(%r15)
	addl	12(%r15), %eax
	movq	_GFP_KERNEL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_kmalloc
	movq	%rax, 56(%r15)
	testq	%rax, %rax
	je	LBB0_13
## %bb.14:
	movl	40(%r12), %edi
	callq	_le32_to_cpu
	cmpl	$4, 12(%r15)
	jae	LBB0_16
## %bb.15:
	xorl	%ebx, %ebx
	jmp	LBB0_18
LBB0_4:
	leaq	-84(%rbp), %rsi
	movq	%r15, %rdi
	callq	_amdgpu_pm_load_smu_firmware
	testq	%rax, %rax
	jne	LBB0_7
## %bb.5:
	cmpl	$269866, -84(%rbp)              ## imm = 0x41E2A
	jle	LBB0_7
## %bb.6:
	leaq	L_.str.3(%rip), %rdx
	jmp	LBB0_8
LBB0_13:
	movq	_ENOMEM@GOTPCREL(%rip), %rax
	xorl	%r14d, %r14d
	subl	(%rax), %r14d
	jmp	LBB0_29
LBB0_16:
	movq	%rax, %r13
	addq	%r12, %r13
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_17:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r13,%rbx,4), %edi
	callq	_le32_to_cpu
	movq	56(%r15), %rcx
	movq	%rax, (%rcx,%rbx,8)
	incq	%rbx
	movl	12(%r15), %eax
	sarl	$2, %eax
	cmpq	%rax, %rbx
	jb	LBB0_17
LBB0_18:
	shlq	$3, %rbx
	addq	56(%r15), %rbx
	movq	%rbx, 48(%r15)
	movl	44(%r12), %edi
	callq	_le32_to_cpu
	cmpl	$4, 16(%r15)
	jb	LBB0_21
## %bb.19:
	movq	%rax, %r13
	addq	%r12, %r13
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_20:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r13,%rbx,4), %edi
	callq	_le32_to_cpu
	movq	48(%r15), %rcx
	movq	%rax, (%rcx,%rbx,8)
	incq	%rbx
	movl	16(%r15), %eax
	sarl	$2, %eax
	cmpq	%rax, %rbx
	jb	LBB0_20
LBB0_21:
	cmpl	$0, 8(%r15)
	je	LBB0_23
## %bb.22:
	movq	%r15, %rdi
	callq	_gfx_v9_0_init_rlc_ext_microcode
LBB0_23:
	movq	144(%r15), %rax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_29
## %bb.24:
	movq	160(%r15), %rax
	movq	_AMDGPU_UCODE_ID_RLC_G@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movq	(%rcx), %rax
	movl	(%rax), %edi
	callq	_le32_to_cpu
	movq	_PAGE_SIZE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%rax, %rdi
	callq	_ALIGN
	addl	%eax, 152(%r15)
	cmpl	$0, 8(%r15)
	je	LBB0_29
## %bb.25:
	movq	24(%r15), %rdi
	testq	%rdi, %rdi
	je	LBB0_29
## %bb.26:
	cmpq	$0, 32(%r15)
	je	LBB0_29
## %bb.27:
	cmpq	$0, 40(%r15)
	je	LBB0_29
## %bb.28:
	movq	160(%r15), %rax
	movq	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movl	(%rbx), %esi
	callq	_ALIGN
	addl	%eax, 152(%r15)
	movq	160(%r15), %rax
	movq	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movq	32(%r15), %rdi
	movl	(%rbx), %esi
	callq	_ALIGN
	addl	%eax, 152(%r15)
	movq	160(%r15), %rax
	movq	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rdx
	shlq	$4, %rdx
	movq	%rcx, (%rax,%rdx)
	movq	(%r15), %rcx
	movq	%rcx, 8(%rax,%rdx)
	movq	40(%r15), %rdi
	movl	(%rbx), %esi
	callq	_ALIGN
	addl	%eax, 152(%r15)
LBB0_29:
	testl	%r14d, %r14d
	je	LBB0_30
LBB0_31:
	movl	136(%r15), %edi
	leaq	L_.str.5(%rip), %rsi
	leaq	-80(%rbp), %rdx
	callq	_dev_err
	movq	(%r15), %rdi
	callq	_release_firmware
	movq	$0, (%r15)
LBB0_32:
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	cmpq	-48(%rbp), %rax
	jne	LBB0_34
## %bb.33:
	movl	%r14d, %eax
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_30:
	xorl	%r14d, %r14d
	jmp	LBB0_32
LBB0_34:
	callq	___stack_chk_fail
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"picasso"

L_.str.1:                               ## @.str.1
	.asciz	"amdgpu/%s_rlc_am4.bin"

L_.str.2:                               ## @.str.2
	.asciz	"raven"

L_.str.3:                               ## @.str.3
	.asciz	"amdgpu/%s_kicker_rlc.bin"

L_.str.4:                               ## @.str.4
	.asciz	"amdgpu/%s_rlc.bin"

	.comm	_GFP_KERNEL,4,2                 ## @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ## @ENOMEM
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_RLC_G,8,3      ## @AMDGPU_UCODE_ID_RLC_G
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
	.comm	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,8,3 ## @AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
	.comm	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,8,3 ## @AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
	.comm	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,8,3 ## @AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
L_.str.5:                               ## @.str.5
	.asciz	"gfx9: Failed to load firmware \"%s\"\n"

	.no_dead_strip	_gfx_v9_0_init_rlc_microcode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v9_0_init_rlc_microcode
_gfx_v9_0_init_rlc_microcode:           ; @gfx_v9_0_init_rlc_microcode
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x8, ___stack_chk_guard@GOTPAGE
Lloh1:
	ldr	x8, [x8, ___stack_chk_guard@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	str	x8, [sp, #40]
Lloh3:
	adrp	x1, l_.str@PAGE
Lloh4:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x20
	bl	_strcmp
	cbnz	w0, LBB0_3
; %bb.1:
	ldr	x8, [x19, #168]
	ldr	w8, [x8]
	mov	w9, #-24
	and	w8, w8, w9
	cmp	w8, #200
	b.ne	LBB0_3
; %bb.2:
Lloh5:
	adrp	x2, l_.str.1@PAGE
Lloh6:
	add	x2, x2, l_.str.1@PAGEOFF
	b	LBB0_5
LBB0_3:
Lloh7:
	adrp	x1, l_.str.2@PAGE
Lloh8:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x0, x20
	bl	_strcmp
	cbz	w0, LBB0_11
LBB0_4:
Lloh9:
	adrp	x2, l_.str.4@PAGE
Lloh10:
	add	x2, x2, l_.str.4@PAGEOFF
LBB0_5:
	add	x0, sp, #10
	mov	w1, #30
	mov	x3, x20
	bl	_snprintf
	ldr	w2, [x19, #136]
	add	x1, sp, #10
	mov	x0, x19
	bl	_request_firmware
	mov	x20, x0
	cbnz	w0, LBB0_29
; %bb.6:
	ldr	x0, [x19]
	bl	_amdgpu_ucode_validate
	mov	x20, x0
	ldr	x8, [x19]
	ldr	x22, [x8]
	ldr	w0, [x22, #56]
	bl	_le16_to_cpu
	mov	x21, x0
	ldr	w0, [x22, #52]
	bl	_le16_to_cpu
	cmp	w21, #2
	ccmp	w0, #1, #0, eq
	b.ne	LBB0_8
; %bb.7:
	mov	w8, #1
	str	w8, [x19, #8]
LBB0_8:
	ldr	w0, [x22, #48]
	bl	_le32_to_cpu
	str	x0, [x19, #128]
	ldr	w0, [x22]
	bl	_le32_to_cpu
	str	x0, [x19, #120]
	ldr	w0, [x22, #4]
	bl	_le32_to_cpu
	str	x0, [x19, #112]
	ldr	w0, [x22, #8]
	bl	_le32_to_cpu
	str	x0, [x19, #104]
	ldr	w0, [x22, #12]
	bl	_le32_to_cpu
	str	x0, [x19, #96]
	ldr	w0, [x22, #16]
	bl	_le32_to_cpu
	str	x0, [x19, #88]
	ldr	w0, [x22, #20]
	bl	_le32_to_cpu
	str	x0, [x19, #80]
	ldr	w0, [x22, #24]
	bl	_le32_to_cpu
	str	x0, [x19, #72]
	ldr	w0, [x22, #28]
	bl	_le32_to_cpu
	str	x0, [x19, #64]
	ldr	w0, [x22, #32]
	bl	_le32_to_cpu
	str	w0, [x19, #12]
	ldr	w0, [x22, #36]
	bl	_le32_to_cpu
	str	w0, [x19, #16]
	ldr	w8, [x19, #12]
	add	w0, w8, w0
Lloh11:
	adrp	x8, _GFP_KERNEL@GOTPAGE
Lloh12:
	ldr	x8, [x8, _GFP_KERNEL@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
	bl	_kmalloc
	str	x0, [x19, #56]
	cbz	x0, LBB0_14
; %bb.9:
	ldr	w0, [x22, #40]
	bl	_le32_to_cpu
	ldr	w8, [x19, #12]
	cmp	w8, #4
	b.hs	LBB0_15
; %bb.10:
	mov	x21, #0
	b	LBB0_17
LBB0_11:
	add	x1, sp, #4
	mov	x0, x19
	bl	_amdgpu_pm_load_smu_firmware
	cbnz	x0, LBB0_4
; %bb.12:
	ldr	w8, [sp, #4]
	mov	w9, #7722
	movk	w9, #4, lsl #16
	cmp	w8, w9
	b.le	LBB0_4
; %bb.13:
Lloh14:
	adrp	x2, l_.str.3@PAGE
Lloh15:
	add	x2, x2, l_.str.3@PAGEOFF
	b	LBB0_5
LBB0_14:
Lloh16:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh17:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	neg	w20, w8
	b	LBB0_28
LBB0_15:
	mov	x21, #0
	add	x23, x0, x22
LBB0_16:                                ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x23, x21, lsl #2]
	bl	_le32_to_cpu
	ldr	x8, [x19, #56]
	str	x0, [x8, x21, lsl #3]
	add	x21, x21, #1
	ldr	w8, [x19, #12]
	asr	w8, w8, #2
	cmp	x21, x8
	b.lo	LBB0_16
LBB0_17:
	ldr	x8, [x19, #56]
	add	x8, x8, x21, lsl #3
	str	x8, [x19, #48]
	ldr	w0, [x22, #44]
	bl	_le32_to_cpu
	ldr	w8, [x19, #16]
	cmp	w8, #4
	b.lo	LBB0_20
; %bb.18:
	mov	x21, #0
	add	x22, x0, x22
LBB0_19:                                ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x22, x21, lsl #2]
	bl	_le32_to_cpu
	ldr	x8, [x19, #48]
	str	x0, [x8, x21, lsl #3]
	add	x21, x21, #1
	ldr	w8, [x19, #16]
	asr	w8, w8, #2
	cmp	x21, x8
	b.lo	LBB0_19
LBB0_20:
	ldr	w8, [x19, #8]
	cbz	w8, LBB0_22
; %bb.21:
	mov	x0, x19
	bl	_gfx_v9_0_init_rlc_ext_microcode
LBB0_22:
	ldr	x8, [x19, #144]
Lloh19:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh20:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh21:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_28
; %bb.23:
	ldr	x8, [x19, #160]
Lloh22:
	adrp	x9, _AMDGPU_UCODE_ID_RLC_G@GOTPAGE
Lloh23:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_RLC_G@GOTPAGEOFF]
Lloh24:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19]
	str	x9, [x8, #8]
	ldr	x8, [x9]
	ldr	w0, [x8]
	bl	_le32_to_cpu
Lloh25:
	adrp	x21, _PAGE_SIZE@GOTPAGE
Lloh26:
	ldr	x21, [x21, _PAGE_SIZE@GOTPAGEOFF]
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #152]
	add	w8, w8, w0
	str	w8, [x19, #152]
	ldr	w8, [x19, #8]
	cbz	w8, LBB0_28
; %bb.24:
	ldr	x0, [x19, #24]
	cbz	x0, LBB0_28
; %bb.25:
	ldr	x8, [x19, #32]
	cbz	x8, LBB0_28
; %bb.26:
	ldr	x8, [x19, #40]
	cbz	x8, LBB0_28
; %bb.27:
	ldr	x8, [x19, #160]
Lloh27:
	adrp	x9, _AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL@GOTPAGE
Lloh28:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL@GOTPAGEOFF]
Lloh29:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19]
	str	x9, [x8, #8]
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #152]
	add	w8, w8, w0
	str	w8, [x19, #152]
	ldr	x8, [x19, #160]
Lloh30:
	adrp	x9, _AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM@GOTPAGE
Lloh31:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM@GOTPAGEOFF]
Lloh32:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19]
	str	x9, [x8, #8]
	ldr	x0, [x19, #32]
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #152]
	add	w8, w8, w0
	str	w8, [x19, #152]
	ldr	x8, [x19, #160]
Lloh33:
	adrp	x9, _AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM@GOTPAGE
Lloh34:
	ldr	x9, [x9, _AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM@GOTPAGEOFF]
Lloh35:
	ldr	x9, [x9]
	add	x8, x8, x9, lsl #4
	str	x9, [x8]
	ldr	x9, [x19]
	str	x9, [x8, #8]
	ldr	x0, [x19, #40]
	ldr	w1, [x21]
	bl	_ALIGN
	ldr	w8, [x19, #152]
	add	w8, w8, w0
	str	w8, [x19, #152]
LBB0_28:
	cbz	w20, LBB0_30
LBB0_29:
	ldr	w0, [x19, #136]
Lloh36:
	adrp	x1, l_.str.5@PAGE
Lloh37:
	add	x1, x1, l_.str.5@PAGEOFF
	add	x2, sp, #10
	bl	_dev_err
	ldr	x0, [x19]
	bl	_release_firmware
	str	xzr, [x19]
LBB0_30:
	ldr	x8, [sp, #40]
Lloh38:
	adrp	x9, ___stack_chk_guard@GOTPAGE
Lloh39:
	ldr	x9, [x9, ___stack_chk_guard@GOTPAGEOFF]
Lloh40:
	ldr	x9, [x9]
	cmp	x9, x8
	b.ne	LBB0_32
; %bb.31:
	mov	x0, x20
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
LBB0_32:
	bl	___stack_chk_fail
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpAdd	Lloh7, Lloh8
	.loh AdrpAdd	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpAdd	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpAdd	Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"picasso"

l_.str.1:                               ; @.str.1
	.asciz	"amdgpu/%s_rlc_am4.bin"

l_.str.2:                               ; @.str.2
	.asciz	"raven"

l_.str.3:                               ; @.str.3
	.asciz	"amdgpu/%s_kicker_rlc.bin"

l_.str.4:                               ; @.str.4
	.asciz	"amdgpu/%s_rlc.bin"

	.comm	_GFP_KERNEL,4,2                 ; @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ; @ENOMEM
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_AMDGPU_UCODE_ID_RLC_G,8,3      ; @AMDGPU_UCODE_ID_RLC_G
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
	.comm	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,8,3 ; @AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
	.comm	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,8,3 ; @AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
	.comm	_AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,8,3 ; @AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
l_.str.5:                               ; @.str.5
	.asciz	"gfx9: Failed to load firmware \"%s\"\n"

	.no_dead_strip	_gfx_v9_0_init_rlc_microcode
.subsections_via_symbols
