	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_bo_set_tiling_flags     ## -- Begin function amdgpu_bo_set_tiling_flags
	.p2align	4, 0x90
_amdgpu_bo_set_tiling_flags:            ## @amdgpu_bo_set_tiling_flags
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movl	%esi, %r14d
	movq	%rdi, %rbx
	movl	4(%rdi), %edi
	callq	_amdgpu_ttm_adev
	movq	(%rax), %rax
	movq	_AMDGPU_FAMILY_CZ@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jg	LBB0_3
## %bb.1:
	movq	_TILE_SPLIT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r14d, %edi
	callq	_AMDGPU_TILING_GET
	cmpl	$7, %eax
	jl	LBB0_3
## %bb.2:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_4
LBB0_3:
	movl	%r14d, (%rbx)
	xorl	%eax, %eax
LBB0_4:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_FAMILY_CZ,8,3           ## @AMDGPU_FAMILY_CZ
	.comm	_TILE_SPLIT,4,2                 ## @TILE_SPLIT
	.comm	_EINVAL,4,2                     ## @EINVAL
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_bo_set_tiling_flags     ; -- Begin function amdgpu_bo_set_tiling_flags
	.p2align	2
_amdgpu_bo_set_tiling_flags:            ; @amdgpu_bo_set_tiling_flags
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x1
	mov	x20, x0
	ldr	w0, [x0, #4]
	bl	_amdgpu_ttm_adev
	ldr	x8, [x0]
Lloh0:
	adrp	x9, _AMDGPU_FAMILY_CZ@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMDGPU_FAMILY_CZ@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	b.gt	LBB0_3
; %bb.1:
Lloh3:
	adrp	x8, _TILE_SPLIT@GOTPAGE
Lloh4:
	ldr	x8, [x8, _TILE_SPLIT@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_AMDGPU_TILING_GET
	cmp	w0, #7
	b.lt	LBB0_3
; %bb.2:
Lloh6:
	adrp	x8, _EINVAL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_4
LBB0_3:
	mov	w0, #0
	str	w19, [x20]
LBB0_4:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_FAMILY_CZ,8,3           ; @AMDGPU_FAMILY_CZ
	.comm	_TILE_SPLIT,4,2                 ; @TILE_SPLIT
	.comm	_EINVAL,4,2                     ; @EINVAL
.subsections_via_symbols
