	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function meson_overlay_atomic_disable
_meson_overlay_atomic_disable:          ## @meson_overlay_atomic_disable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	callq	_to_meson_overlay
	movq	(%rax), %r14
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG_DRIVER
	movl	$0, 8(%r14)
	movq	_VPU_COMPATIBLE_G12A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	(%r14), %rbx
	movq	_VD1_BLEND_SRC_CTRL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	__REG
	addq	%rax, %rbx
	xorl	%edi, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	(%r14), %rbx
	movq	_VD2_BLEND_SRC_CTRL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	__REG
	addq	%rax, %rbx
	xorl	%edi, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
	movq	(%r14), %r15
	movq	_VD1_IF0_GEN_REG@GOTPCREL(%rip), %rax
	movl	$6064, %ebx                     ## imm = 0x17B0
	movq	(%rax), %rdi
	addq	%rbx, %rdi
	callq	__REG
	addq	%rax, %r15
	xorl	%edi, %edi
	movq	%r15, %rsi
	callq	_writel_relaxed
	movq	(%r14), %r14
	movq	_VD2_IF0_GEN_REG@GOTPCREL(%rip), %rax
	addq	(%rax), %rbx
	movq	%rbx, %rdi
	callq	__REG
	addq	%rax, %r14
	xorl	%edi, %edi
	movq	%r14, %rsi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_writel_relaxed                 ## TAILCALL
LBB0_2:
	movq	_VPP_VD1_POSTBLEND@GOTPCREL(%rip), %rax
	movq	_VPP_VD1_PREBLEND@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r15d
	orl	(%rax), %r15d
	movq	(%r14), %rbx
	movq	_VPP_MISC@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	__REG
	addq	%rax, %rbx
	movl	%r15d, %edi
	xorl	%esi, %esi
	movq	%rbx, %rdx
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_writel_bits_relaxed            ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"\n"

	.comm	_VPU_COMPATIBLE_G12A,4,2        ## @VPU_COMPATIBLE_G12A
	.comm	_VD1_BLEND_SRC_CTRL,8,3         ## @VD1_BLEND_SRC_CTRL
	.comm	_VD2_BLEND_SRC_CTRL,8,3         ## @VD2_BLEND_SRC_CTRL
	.comm	_VD1_IF0_GEN_REG,8,3            ## @VD1_IF0_GEN_REG
	.comm	_VD2_IF0_GEN_REG,8,3            ## @VD2_IF0_GEN_REG
	.comm	_VPP_VD1_POSTBLEND,4,2          ## @VPP_VD1_POSTBLEND
	.comm	_VPP_VD1_PREBLEND,4,2           ## @VPP_VD1_PREBLEND
	.comm	_VPP_MISC,8,3                   ## @VPP_MISC
	.no_dead_strip	_meson_overlay_atomic_disable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function meson_overlay_atomic_disable
_meson_overlay_atomic_disable:          ; @meson_overlay_atomic_disable
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	bl	_to_meson_overlay
	ldr	x19, [x0]
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_DRIVER
	str	wzr, [x19, #8]
Lloh2:
	adrp	x8, _VPU_COMPATIBLE_G12A@GOTPAGE
Lloh3:
	ldr	x8, [x8, _VPU_COMPATIBLE_G12A@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_meson_vpu_is_compatible
	cbz	x0, LBB0_2
; %bb.1:
	ldr	x20, [x19]
Lloh5:
	adrp	x8, _VD1_BLEND_SRC_CTRL@GOTPAGE
Lloh6:
	ldr	x8, [x8, _VD1_BLEND_SRC_CTRL@GOTPAGEOFF]
Lloh7:
	ldr	x0, [x8]
	bl	__REG
	add	x1, x0, x20
	mov	w0, #0
	bl	_writel_relaxed
	ldr	x20, [x19]
Lloh8:
	adrp	x8, _VD2_BLEND_SRC_CTRL@GOTPAGE
Lloh9:
	ldr	x8, [x8, _VD2_BLEND_SRC_CTRL@GOTPAGEOFF]
Lloh10:
	ldr	x0, [x8]
	bl	__REG
	add	x1, x0, x20
	mov	w0, #0
	bl	_writel_relaxed
	ldr	x20, [x19]
Lloh11:
	adrp	x8, _VD1_IF0_GEN_REG@GOTPAGE
Lloh12:
	ldr	x8, [x8, _VD1_IF0_GEN_REG@GOTPAGEOFF]
Lloh13:
	ldr	x8, [x8]
	mov	w21, #6064
	add	x0, x8, x21
	bl	__REG
	add	x1, x0, x20
	mov	w0, #0
	bl	_writel_relaxed
	ldr	x19, [x19]
Lloh14:
	adrp	x8, _VD2_IF0_GEN_REG@GOTPAGE
Lloh15:
	ldr	x8, [x8, _VD2_IF0_GEN_REG@GOTPAGEOFF]
Lloh16:
	ldr	x8, [x8]
	add	x0, x8, x21
	bl	__REG
	add	x1, x0, x19
	mov	w0, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_writel_relaxed
LBB0_2:
Lloh17:
	adrp	x8, _VPP_VD1_POSTBLEND@GOTPAGE
Lloh18:
	ldr	x8, [x8, _VPP_VD1_POSTBLEND@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
Lloh20:
	adrp	x9, _VPP_VD1_PREBLEND@GOTPAGE
Lloh21:
	ldr	x9, [x9, _VPP_VD1_PREBLEND@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	orr	w20, w9, w8
	ldr	x19, [x19]
Lloh23:
	adrp	x8, _VPP_MISC@GOTPAGE
Lloh24:
	ldr	x8, [x8, _VPP_MISC@GOTPAGEOFF]
Lloh25:
	ldr	x0, [x8]
	bl	__REG
	add	x2, x0, x19
	mov	x0, x20
	mov	w1, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_writel_bits_relaxed
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"\n"

	.comm	_VPU_COMPATIBLE_G12A,4,2        ; @VPU_COMPATIBLE_G12A
	.comm	_VD1_BLEND_SRC_CTRL,8,3         ; @VD1_BLEND_SRC_CTRL
	.comm	_VD2_BLEND_SRC_CTRL,8,3         ; @VD2_BLEND_SRC_CTRL
	.comm	_VD1_IF0_GEN_REG,8,3            ; @VD1_IF0_GEN_REG
	.comm	_VD2_IF0_GEN_REG,8,3            ; @VD2_IF0_GEN_REG
	.comm	_VPP_VD1_POSTBLEND,4,2          ; @VPP_VD1_POSTBLEND
	.comm	_VPP_VD1_PREBLEND,4,2           ; @VPP_VD1_PREBLEND
	.comm	_VPP_MISC,8,3                   ; @VPP_MISC
	.no_dead_strip	_meson_overlay_atomic_disable
.subsections_via_symbols
