	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function df_v3_6_get_clockgating_state
_df_v3_6_get_clockgating_state:         ## @df_v3_6_get_clockgating_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rsi, %rbx
	movq	_DF@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_mmDF_PIE_AON0_DfGlobalClkGater@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_2
## %bb.1:
	movq	_AMD_CG_SUPPORT_DF_MGCG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%rbx)
LBB0_2:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DF,4,2                         ## @DF
	.comm	_mmDF_PIE_AON0_DfGlobalClkGater,4,2 ## @mmDF_PIE_AON0_DfGlobalClkGater
	.comm	_DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY,4,2 ## @DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY
	.comm	_AMD_CG_SUPPORT_DF_MGCG,4,2     ## @AMD_CG_SUPPORT_DF_MGCG
	.no_dead_strip	_df_v3_6_get_clockgating_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function df_v3_6_get_clockgating_state
_df_v3_6_get_clockgating_state:         ; @df_v3_6_get_clockgating_state
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x1
Lloh0:
	adrp	x8, _DF@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DF@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
Lloh3:
	adrp	x8, _mmDF_PIE_AON0_DfGlobalClkGater@GOTPAGE
Lloh4:
	ldr	x8, [x8, _mmDF_PIE_AON0_DfGlobalClkGater@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh6:
	adrp	x8, _DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY@GOTPAGE
Lloh7:
	ldr	x8, [x8, _DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_2
; %bb.1:
Lloh9:
	adrp	x8, _AMD_CG_SUPPORT_DF_MGCG@GOTPAGE
Lloh10:
	ldr	x8, [x8, _AMD_CG_SUPPORT_DF_MGCG@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_2:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.cfi_endproc
                                        ; -- End function
	.comm	_DF,4,2                         ; @DF
	.comm	_mmDF_PIE_AON0_DfGlobalClkGater,4,2 ; @mmDF_PIE_AON0_DfGlobalClkGater
	.comm	_DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY,4,2 ; @DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY
	.comm	_AMD_CG_SUPPORT_DF_MGCG,4,2     ; @AMD_CG_SUPPORT_DF_MGCG
	.no_dead_strip	_df_v3_6_get_clockgating_state
.subsections_via_symbols
