	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function _setup_ctl_ops
__setup_ctl_ops:                        ## @_setup_ctl_ops
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	_dpu_hw_ctl_clear_pending_flush@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 56(%rdi)
	movq	_dpu_hw_ctl_update_pending_flush@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 52(%rdi)
	movq	_dpu_hw_ctl_get_pending_flush@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 48(%rdi)
	movq	_dpu_hw_ctl_trigger_flush@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 44(%rdi)
	movq	_dpu_hw_ctl_get_flush_register@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 40(%rdi)
	movq	_dpu_hw_ctl_trigger_start@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 36(%rdi)
	movq	_dpu_hw_ctl_trigger_pending@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 32(%rdi)
	movq	_dpu_hw_ctl_intf_cfg@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 28(%rdi)
	movq	_dpu_hw_ctl_reset_control@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 24(%rdi)
	movq	_dpu_hw_ctl_wait_reset_status@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 20(%rdi)
	movq	_dpu_hw_ctl_clear_all_blendstages@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 16(%rdi)
	movq	_dpu_hw_ctl_setup_blendstage@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 12(%rdi)
	movq	_dpu_hw_ctl_get_bitmask_sspp@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 8(%rdi)
	movq	_dpu_hw_ctl_get_bitmask_mixer@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 4(%rdi)
	movq	_dpu_hw_ctl_get_bitmask_intf@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, (%rdi)
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_dpu_hw_ctl_clear_pending_flush,4,2 ## @dpu_hw_ctl_clear_pending_flush
	.comm	_dpu_hw_ctl_update_pending_flush,4,2 ## @dpu_hw_ctl_update_pending_flush
	.comm	_dpu_hw_ctl_get_pending_flush,4,2 ## @dpu_hw_ctl_get_pending_flush
	.comm	_dpu_hw_ctl_trigger_flush,4,2   ## @dpu_hw_ctl_trigger_flush
	.comm	_dpu_hw_ctl_get_flush_register,4,2 ## @dpu_hw_ctl_get_flush_register
	.comm	_dpu_hw_ctl_trigger_start,4,2   ## @dpu_hw_ctl_trigger_start
	.comm	_dpu_hw_ctl_trigger_pending,4,2 ## @dpu_hw_ctl_trigger_pending
	.comm	_dpu_hw_ctl_intf_cfg,4,2        ## @dpu_hw_ctl_intf_cfg
	.comm	_dpu_hw_ctl_reset_control,4,2   ## @dpu_hw_ctl_reset_control
	.comm	_dpu_hw_ctl_wait_reset_status,4,2 ## @dpu_hw_ctl_wait_reset_status
	.comm	_dpu_hw_ctl_clear_all_blendstages,4,2 ## @dpu_hw_ctl_clear_all_blendstages
	.comm	_dpu_hw_ctl_setup_blendstage,4,2 ## @dpu_hw_ctl_setup_blendstage
	.comm	_dpu_hw_ctl_get_bitmask_sspp,4,2 ## @dpu_hw_ctl_get_bitmask_sspp
	.comm	_dpu_hw_ctl_get_bitmask_mixer,4,2 ## @dpu_hw_ctl_get_bitmask_mixer
	.comm	_dpu_hw_ctl_get_bitmask_intf,4,2 ## @dpu_hw_ctl_get_bitmask_intf
	.no_dead_strip	__setup_ctl_ops
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function _setup_ctl_ops
__setup_ctl_ops:                        ; @_setup_ctl_ops
	.cfi_startproc
; %bb.0:
Lloh0:
	adrp	x8, _dpu_hw_ctl_clear_pending_flush@GOTPAGE
Lloh1:
	ldr	x8, [x8, _dpu_hw_ctl_clear_pending_flush@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	str	w8, [x0, #56]
Lloh3:
	adrp	x8, _dpu_hw_ctl_update_pending_flush@GOTPAGE
Lloh4:
	ldr	x8, [x8, _dpu_hw_ctl_update_pending_flush@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
Lloh6:
	adrp	x9, _dpu_hw_ctl_get_pending_flush@GOTPAGE
Lloh7:
	ldr	x9, [x9, _dpu_hw_ctl_get_pending_flush@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	stp	w9, w8, [x0, #48]
Lloh9:
	adrp	x8, _dpu_hw_ctl_trigger_flush@GOTPAGE
Lloh10:
	ldr	x8, [x8, _dpu_hw_ctl_trigger_flush@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
Lloh12:
	adrp	x9, _dpu_hw_ctl_get_flush_register@GOTPAGE
Lloh13:
	ldr	x9, [x9, _dpu_hw_ctl_get_flush_register@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	stp	w9, w8, [x0, #40]
Lloh15:
	adrp	x8, _dpu_hw_ctl_trigger_start@GOTPAGE
Lloh16:
	ldr	x8, [x8, _dpu_hw_ctl_trigger_start@GOTPAGEOFF]
Lloh17:
	adrp	x9, _dpu_hw_ctl_trigger_pending@GOTPAGE
Lloh18:
	ldr	x9, [x9, _dpu_hw_ctl_trigger_pending@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
Lloh20:
	ldr	w9, [x9]
	stp	w9, w8, [x0, #32]
Lloh21:
	adrp	x8, _dpu_hw_ctl_intf_cfg@GOTPAGE
Lloh22:
	ldr	x8, [x8, _dpu_hw_ctl_intf_cfg@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
Lloh24:
	adrp	x9, _dpu_hw_ctl_reset_control@GOTPAGE
Lloh25:
	ldr	x9, [x9, _dpu_hw_ctl_reset_control@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	stp	w9, w8, [x0, #24]
Lloh27:
	adrp	x8, _dpu_hw_ctl_wait_reset_status@GOTPAGE
Lloh28:
	ldr	x8, [x8, _dpu_hw_ctl_wait_reset_status@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
Lloh30:
	adrp	x9, _dpu_hw_ctl_clear_all_blendstages@GOTPAGE
Lloh31:
	ldr	x9, [x9, _dpu_hw_ctl_clear_all_blendstages@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	stp	w9, w8, [x0, #16]
Lloh33:
	adrp	x8, _dpu_hw_ctl_setup_blendstage@GOTPAGE
Lloh34:
	ldr	x8, [x8, _dpu_hw_ctl_setup_blendstage@GOTPAGEOFF]
Lloh35:
	adrp	x9, _dpu_hw_ctl_get_bitmask_sspp@GOTPAGE
Lloh36:
	ldr	x9, [x9, _dpu_hw_ctl_get_bitmask_sspp@GOTPAGEOFF]
Lloh37:
	ldr	w8, [x8]
Lloh38:
	ldr	w9, [x9]
	stp	w9, w8, [x0, #8]
Lloh39:
	adrp	x8, _dpu_hw_ctl_get_bitmask_mixer@GOTPAGE
Lloh40:
	ldr	x8, [x8, _dpu_hw_ctl_get_bitmask_mixer@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
Lloh42:
	adrp	x9, _dpu_hw_ctl_get_bitmask_intf@GOTPAGE
Lloh43:
	ldr	x9, [x9, _dpu_hw_ctl_get_bitmask_intf@GOTPAGEOFF]
Lloh44:
	ldr	w9, [x9]
	stp	w9, w8, [x0]
	ret
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh37
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh19
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_dpu_hw_ctl_clear_pending_flush,4,2 ; @dpu_hw_ctl_clear_pending_flush
	.comm	_dpu_hw_ctl_update_pending_flush,4,2 ; @dpu_hw_ctl_update_pending_flush
	.comm	_dpu_hw_ctl_get_pending_flush,4,2 ; @dpu_hw_ctl_get_pending_flush
	.comm	_dpu_hw_ctl_trigger_flush,4,2   ; @dpu_hw_ctl_trigger_flush
	.comm	_dpu_hw_ctl_get_flush_register,4,2 ; @dpu_hw_ctl_get_flush_register
	.comm	_dpu_hw_ctl_trigger_start,4,2   ; @dpu_hw_ctl_trigger_start
	.comm	_dpu_hw_ctl_trigger_pending,4,2 ; @dpu_hw_ctl_trigger_pending
	.comm	_dpu_hw_ctl_intf_cfg,4,2        ; @dpu_hw_ctl_intf_cfg
	.comm	_dpu_hw_ctl_reset_control,4,2   ; @dpu_hw_ctl_reset_control
	.comm	_dpu_hw_ctl_wait_reset_status,4,2 ; @dpu_hw_ctl_wait_reset_status
	.comm	_dpu_hw_ctl_clear_all_blendstages,4,2 ; @dpu_hw_ctl_clear_all_blendstages
	.comm	_dpu_hw_ctl_setup_blendstage,4,2 ; @dpu_hw_ctl_setup_blendstage
	.comm	_dpu_hw_ctl_get_bitmask_sspp,4,2 ; @dpu_hw_ctl_get_bitmask_sspp
	.comm	_dpu_hw_ctl_get_bitmask_mixer,4,2 ; @dpu_hw_ctl_get_bitmask_mixer
	.comm	_dpu_hw_ctl_get_bitmask_intf,4,2 ; @dpu_hw_ctl_get_bitmask_intf
	.no_dead_strip	__setup_ctl_ops
.subsections_via_symbols
