	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dce_v10_0_crtc_init
_dce_v10_0_crtc_init:                   ## @dce_v10_0_crtc_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r12d
	movq	%rdi, %r15
	movq	_AMDGPUFB_CONN_LIMIT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	leal	48(,%rax,8), %edi
	movq	_GFP_KERNEL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_kzalloc
	testq	%rax, %rax
	je	LBB0_1
## %bb.2:
	movq	%rax, %rbx
	movq	(%r15), %rdi
	movq	%rax, %r14
	addq	$12, %r14
	movq	_dce_v10_0_crtc_funcs@GOTPCREL(%rip), %rdx
	movq	%r14, %rsi
	callq	_drm_crtc_init
	movq	%r14, %rdi
	movl	$256, %esi                      ## imm = 0x100
	callq	_drm_mode_crtc_set_gamma_size
	movl	%r12d, (%rbx)
	movq	8(%r15), %rcx
	movslq	%r12d, %rax
	movq	%rbx, (%rcx,%rax,8)
	movabsq	$549755814016, %rcx             ## imm = 0x8000000080
	movq	%rcx, 4(%rbx)
	movq	(%r15), %rdx
	movq	%rcx, (%rdx)
	decl	%eax
	cmpl	$4, %eax
	ja	LBB0_3
## %bb.4:
	cltq
	leaq	l_switch.table.dce_v10_0_crtc_init(%rip), %rcx
	movq	(%rcx,%rax,8), %rax
	jmp	LBB0_5
LBB0_1:
	movq	_ENOMEM@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_6
LBB0_3:
	movq	_CRTC0_REGISTER_OFFSET@GOTPCREL(%rip), %rax
LBB0_5:
	movl	(%rax), %eax
	movl	%eax, 44(%rbx)
	movq	_ATOM_PPLL_INVALID@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 40(%rbx)
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rbx)
	movq	$0, 32(%rbx)
	movq	_dce_v10_0_crtc_helper_funcs@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_drm_crtc_helper_add
	xorl	%eax, %eax
LBB0_6:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPUFB_CONN_LIMIT,4,2        ## @AMDGPUFB_CONN_LIMIT
	.comm	_GFP_KERNEL,4,2                 ## @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ## @ENOMEM
	.comm	_dce_v10_0_crtc_funcs,4,2       ## @dce_v10_0_crtc_funcs
	.comm	_CRTC0_REGISTER_OFFSET,4,2      ## @CRTC0_REGISTER_OFFSET
	.comm	_CRTC1_REGISTER_OFFSET,4,2      ## @CRTC1_REGISTER_OFFSET
	.comm	_CRTC2_REGISTER_OFFSET,4,2      ## @CRTC2_REGISTER_OFFSET
	.comm	_CRTC3_REGISTER_OFFSET,4,2      ## @CRTC3_REGISTER_OFFSET
	.comm	_CRTC4_REGISTER_OFFSET,4,2      ## @CRTC4_REGISTER_OFFSET
	.comm	_CRTC5_REGISTER_OFFSET,4,2      ## @CRTC5_REGISTER_OFFSET
	.comm	_ATOM_PPLL_INVALID,4,2          ## @ATOM_PPLL_INVALID
	.comm	_dce_v10_0_crtc_helper_funcs,4,2 ## @dce_v10_0_crtc_helper_funcs
	.no_dead_strip	_dce_v10_0_crtc_init
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.dce_v10_0_crtc_init
l_switch.table.dce_v10_0_crtc_init:
	.quad	_CRTC1_REGISTER_OFFSET
	.quad	_CRTC2_REGISTER_OFFSET
	.quad	_CRTC3_REGISTER_OFFSET
	.quad	_CRTC4_REGISTER_OFFSET
	.quad	_CRTC5_REGISTER_OFFSET

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dce_v10_0_crtc_init
_dce_v10_0_crtc_init:                   ; @dce_v10_0_crtc_init
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x21, x1
	mov	x22, x0
Lloh0:
	adrp	x8, _AMDGPUFB_CONN_LIMIT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPUFB_CONN_LIMIT@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	lsl	w8, w8, #3
	add	w0, w8, #48
Lloh3:
	adrp	x8, _GFP_KERNEL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _GFP_KERNEL@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	bl	_kzalloc
	cbz	x0, LBB0_3
; %bb.1:
	mov	x19, x0
	ldr	x0, [x22]
	add	x20, x19, #12
Lloh6:
	adrp	x2, _dce_v10_0_crtc_funcs@GOTPAGE
Lloh7:
	ldr	x2, [x2, _dce_v10_0_crtc_funcs@GOTPAGEOFF]
	mov	x1, x20
	bl	_drm_crtc_init
	mov	x0, x20
	mov	w1, #256
	bl	_drm_mode_crtc_set_gamma_size
	str	w21, [x19]
	ldr	x8, [x22, #8]
	str	x19, [x8, w21, sxtw #3]
	movi.2s	v0, #128
	stur	d0, [x19, #4]
	ldr	x8, [x22]
	str	d0, [x8]
	sub	w8, w21, #1
	cmp	w8, #4
	b.hi	LBB0_4
; %bb.2:
Lloh8:
	adrp	x9, l_switch.table.dce_v10_0_crtc_init@PAGE
Lloh9:
	add	x9, x9, l_switch.table.dce_v10_0_crtc_init@PAGEOFF
	ldr	x8, [x9, w8, sxtw #3]
	b	LBB0_5
LBB0_3:
Lloh10:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh11:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_6
LBB0_4:
Lloh13:
	adrp	x8, _CRTC0_REGISTER_OFFSET@GOTPAGE
Lloh14:
	ldr	x8, [x8, _CRTC0_REGISTER_OFFSET@GOTPAGEOFF]
LBB0_5:
	ldr	w8, [x8]
Lloh15:
	adrp	x9, _ATOM_PPLL_INVALID@GOTPAGE
Lloh16:
	ldr	x9, [x9, _ATOM_PPLL_INVALID@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	stp	w9, w8, [x19, #40]
	stp	xzr, xzr, [x19, #24]
	str	xzr, [x19, #16]
Lloh18:
	adrp	x1, _dce_v10_0_crtc_helper_funcs@GOTPAGE
Lloh19:
	ldr	x1, [x1, _dce_v10_0_crtc_helper_funcs@GOTPAGEOFF]
	mov	x0, x20
	bl	_drm_crtc_helper_add
	mov	w0, #0
LBB0_6:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPUFB_CONN_LIMIT,4,2        ; @AMDGPUFB_CONN_LIMIT
	.comm	_GFP_KERNEL,4,2                 ; @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ; @ENOMEM
	.comm	_dce_v10_0_crtc_funcs,4,2       ; @dce_v10_0_crtc_funcs
	.comm	_CRTC0_REGISTER_OFFSET,4,2      ; @CRTC0_REGISTER_OFFSET
	.comm	_CRTC1_REGISTER_OFFSET,4,2      ; @CRTC1_REGISTER_OFFSET
	.comm	_CRTC2_REGISTER_OFFSET,4,2      ; @CRTC2_REGISTER_OFFSET
	.comm	_CRTC3_REGISTER_OFFSET,4,2      ; @CRTC3_REGISTER_OFFSET
	.comm	_CRTC4_REGISTER_OFFSET,4,2      ; @CRTC4_REGISTER_OFFSET
	.comm	_CRTC5_REGISTER_OFFSET,4,2      ; @CRTC5_REGISTER_OFFSET
	.comm	_ATOM_PPLL_INVALID,4,2          ; @ATOM_PPLL_INVALID
	.comm	_dce_v10_0_crtc_helper_funcs,4,2 ; @dce_v10_0_crtc_helper_funcs
	.no_dead_strip	_dce_v10_0_crtc_init
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.dce_v10_0_crtc_init
l_switch.table.dce_v10_0_crtc_init:
	.quad	_CRTC1_REGISTER_OFFSET
	.quad	_CRTC2_REGISTER_OFFSET
	.quad	_CRTC3_REGISTER_OFFSET
	.quad	_CRTC4_REGISTER_OFFSET
	.quad	_CRTC5_REGISTER_OFFSET

.subsections_via_symbols
