	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function r600_pcie_gart_disable
_r600_pcie_gart_disable:                ## @r600_pcie_gart_disable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_VM_CONTEXT0_CNTL@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%rbx), %rdi
	addq	$4, %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%rbx), %rdi
	addq	$8, %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%rbx), %rdi
	addq	$12, %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%rbx), %rdi
	addq	$16, %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%rbx), %rdi
	addq	$20, %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%rbx), %rdi
	addq	$24, %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_VM_L2_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %r15
	movq	_ENABLE_L2_FRAGMENT_PROCESSING@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$7, %edi
	callq	_EFFECTIVE_L2_QUEUE_SIZE
	orl	%eax, %ebx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_VM_L2_CNTL3@GOTPCREL(%rip), %rax
	movq	(%rax), %r15
	xorl	%edi, %edi
	callq	_BANK_SELECT_0
	movl	%eax, %ebx
	movl	$1, %edi
	callq	_BANK_SELECT_1
	orl	%eax, %ebx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movl	$5, %edi
	callq	_EFFECTIVE_L1_TLB_SIZE
	movl	%eax, %ebx
	movl	$5, %edi
	callq	_EFFECTIVE_L1_QUEUE_SIZE
	orl	%eax, %ebx
	movq	_ENABLE_WAIT_L2_QUERY@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_MC_VM_L1_TLB_MCD_RD_A_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCD_WR_A_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCD_RD_B_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCD_WR_B_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_RD_GFX_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_WR_GFX_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_RD_PDMA_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_WR_PDMA_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_RD_SEM_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_WR_SEM_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_RD_SYS_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_WR_SYS_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_RD_HDP_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_WR_HDP_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_RD_UVD_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_MC_VM_L1_TLB_MCB_WR_UVD_CNTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	%r14, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_gart_table_vram_unpin   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_VM_CONTEXT0_CNTL,8,3           ## @VM_CONTEXT0_CNTL
	.comm	_VM_L2_CNTL,8,3                 ## @VM_L2_CNTL
	.comm	_ENABLE_L2_FRAGMENT_PROCESSING,4,2 ## @ENABLE_L2_FRAGMENT_PROCESSING
	.comm	_VM_L2_CNTL3,8,3                ## @VM_L2_CNTL3
	.comm	_ENABLE_WAIT_L2_QUERY,4,2       ## @ENABLE_WAIT_L2_QUERY
	.comm	_MC_VM_L1_TLB_MCD_RD_A_CNTL,8,3 ## @MC_VM_L1_TLB_MCD_RD_A_CNTL
	.comm	_MC_VM_L1_TLB_MCD_WR_A_CNTL,8,3 ## @MC_VM_L1_TLB_MCD_WR_A_CNTL
	.comm	_MC_VM_L1_TLB_MCD_RD_B_CNTL,8,3 ## @MC_VM_L1_TLB_MCD_RD_B_CNTL
	.comm	_MC_VM_L1_TLB_MCD_WR_B_CNTL,8,3 ## @MC_VM_L1_TLB_MCD_WR_B_CNTL
	.comm	_MC_VM_L1_TLB_MCB_RD_GFX_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_RD_GFX_CNTL
	.comm	_MC_VM_L1_TLB_MCB_WR_GFX_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_WR_GFX_CNTL
	.comm	_MC_VM_L1_TLB_MCB_RD_PDMA_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
	.comm	_MC_VM_L1_TLB_MCB_WR_PDMA_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
	.comm	_MC_VM_L1_TLB_MCB_RD_SEM_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_RD_SEM_CNTL
	.comm	_MC_VM_L1_TLB_MCB_WR_SEM_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_WR_SEM_CNTL
	.comm	_MC_VM_L1_TLB_MCB_RD_SYS_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_RD_SYS_CNTL
	.comm	_MC_VM_L1_TLB_MCB_WR_SYS_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_WR_SYS_CNTL
	.comm	_MC_VM_L1_TLB_MCB_RD_HDP_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_RD_HDP_CNTL
	.comm	_MC_VM_L1_TLB_MCB_WR_HDP_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_WR_HDP_CNTL
	.comm	_MC_VM_L1_TLB_MCB_RD_UVD_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_RD_UVD_CNTL
	.comm	_MC_VM_L1_TLB_MCB_WR_UVD_CNTL,8,3 ## @MC_VM_L1_TLB_MCB_WR_UVD_CNTL
	.no_dead_strip	_r600_pcie_gart_disable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function r600_pcie_gart_disable
_r600_pcie_gart_disable:                ; @r600_pcie_gart_disable
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x20, _VM_CONTEXT0_CNTL@GOTPAGE
Lloh1:
	ldr	x20, [x20, _VM_CONTEXT0_CNTL@GOTPAGEOFF]
	ldr	x0, [x20]
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x20]
	add	x0, x8, #4
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x20]
	add	x0, x8, #8
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x20]
	add	x0, x8, #12
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x20]
	add	x0, x8, #16
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x20]
	add	x0, x8, #20
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x20]
	add	x0, x8, #24
	mov	w1, #0
	bl	_WREG32
Lloh2:
	adrp	x8, _VM_L2_CNTL@GOTPAGE
Lloh3:
	ldr	x8, [x8, _VM_L2_CNTL@GOTPAGEOFF]
Lloh4:
	ldr	x20, [x8]
Lloh5:
	adrp	x8, _ENABLE_L2_FRAGMENT_PROCESSING@GOTPAGE
Lloh6:
	ldr	x8, [x8, _ENABLE_L2_FRAGMENT_PROCESSING@GOTPAGEOFF]
Lloh7:
	ldr	w21, [x8]
	mov	w0, #7
	bl	_EFFECTIVE_L2_QUEUE_SIZE
	orr	w1, w0, w21
	mov	x0, x20
	bl	_WREG32
Lloh8:
	adrp	x8, _VM_L2_CNTL3@GOTPAGE
Lloh9:
	ldr	x8, [x8, _VM_L2_CNTL3@GOTPAGEOFF]
Lloh10:
	ldr	x20, [x8]
	mov	w0, #0
	bl	_BANK_SELECT_0
	mov	x21, x0
	mov	w0, #1
	bl	_BANK_SELECT_1
	orr	w1, w0, w21
	mov	x0, x20
	bl	_WREG32
	mov	w0, #5
	bl	_EFFECTIVE_L1_TLB_SIZE
	mov	x20, x0
	mov	w0, #5
	bl	_EFFECTIVE_L1_QUEUE_SIZE
Lloh11:
	adrp	x8, _ENABLE_WAIT_L2_QUERY@GOTPAGE
Lloh12:
	ldr	x8, [x8, _ENABLE_WAIT_L2_QUERY@GOTPAGEOFF]
	orr	w9, w0, w20
Lloh13:
	ldr	w8, [x8]
	orr	w20, w9, w8
Lloh14:
	adrp	x8, _MC_VM_L1_TLB_MCD_RD_A_CNTL@GOTPAGE
Lloh15:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCD_RD_A_CNTL@GOTPAGEOFF]
Lloh16:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh17:
	adrp	x8, _MC_VM_L1_TLB_MCD_WR_A_CNTL@GOTPAGE
Lloh18:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCD_WR_A_CNTL@GOTPAGEOFF]
Lloh19:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh20:
	adrp	x8, _MC_VM_L1_TLB_MCD_RD_B_CNTL@GOTPAGE
Lloh21:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCD_RD_B_CNTL@GOTPAGEOFF]
Lloh22:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh23:
	adrp	x8, _MC_VM_L1_TLB_MCD_WR_B_CNTL@GOTPAGE
Lloh24:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCD_WR_B_CNTL@GOTPAGEOFF]
Lloh25:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh26:
	adrp	x8, _MC_VM_L1_TLB_MCB_RD_GFX_CNTL@GOTPAGE
Lloh27:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_RD_GFX_CNTL@GOTPAGEOFF]
Lloh28:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh29:
	adrp	x8, _MC_VM_L1_TLB_MCB_WR_GFX_CNTL@GOTPAGE
Lloh30:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_WR_GFX_CNTL@GOTPAGEOFF]
Lloh31:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh32:
	adrp	x8, _MC_VM_L1_TLB_MCB_RD_PDMA_CNTL@GOTPAGE
Lloh33:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_RD_PDMA_CNTL@GOTPAGEOFF]
Lloh34:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh35:
	adrp	x8, _MC_VM_L1_TLB_MCB_WR_PDMA_CNTL@GOTPAGE
Lloh36:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_WR_PDMA_CNTL@GOTPAGEOFF]
Lloh37:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh38:
	adrp	x8, _MC_VM_L1_TLB_MCB_RD_SEM_CNTL@GOTPAGE
Lloh39:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_RD_SEM_CNTL@GOTPAGEOFF]
Lloh40:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh41:
	adrp	x8, _MC_VM_L1_TLB_MCB_WR_SEM_CNTL@GOTPAGE
Lloh42:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_WR_SEM_CNTL@GOTPAGEOFF]
Lloh43:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh44:
	adrp	x8, _MC_VM_L1_TLB_MCB_RD_SYS_CNTL@GOTPAGE
Lloh45:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_RD_SYS_CNTL@GOTPAGEOFF]
Lloh46:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh47:
	adrp	x8, _MC_VM_L1_TLB_MCB_WR_SYS_CNTL@GOTPAGE
Lloh48:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_WR_SYS_CNTL@GOTPAGEOFF]
Lloh49:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh50:
	adrp	x8, _MC_VM_L1_TLB_MCB_RD_HDP_CNTL@GOTPAGE
Lloh51:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_RD_HDP_CNTL@GOTPAGEOFF]
Lloh52:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh53:
	adrp	x8, _MC_VM_L1_TLB_MCB_WR_HDP_CNTL@GOTPAGE
Lloh54:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_WR_HDP_CNTL@GOTPAGEOFF]
Lloh55:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh56:
	adrp	x8, _MC_VM_L1_TLB_MCB_RD_UVD_CNTL@GOTPAGE
Lloh57:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_RD_UVD_CNTL@GOTPAGEOFF]
Lloh58:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh59:
	adrp	x8, _MC_VM_L1_TLB_MCB_WR_UVD_CNTL@GOTPAGE
Lloh60:
	ldr	x8, [x8, _MC_VM_L1_TLB_MCB_WR_UVD_CNTL@GOTPAGEOFF]
Lloh61:
	ldr	x0, [x8]
	mov	x1, x20
	bl	_WREG32
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_radeon_gart_table_vram_unpin
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_VM_CONTEXT0_CNTL,8,3           ; @VM_CONTEXT0_CNTL
	.comm	_VM_L2_CNTL,8,3                 ; @VM_L2_CNTL
	.comm	_ENABLE_L2_FRAGMENT_PROCESSING,4,2 ; @ENABLE_L2_FRAGMENT_PROCESSING
	.comm	_VM_L2_CNTL3,8,3                ; @VM_L2_CNTL3
	.comm	_ENABLE_WAIT_L2_QUERY,4,2       ; @ENABLE_WAIT_L2_QUERY
	.comm	_MC_VM_L1_TLB_MCD_RD_A_CNTL,8,3 ; @MC_VM_L1_TLB_MCD_RD_A_CNTL
	.comm	_MC_VM_L1_TLB_MCD_WR_A_CNTL,8,3 ; @MC_VM_L1_TLB_MCD_WR_A_CNTL
	.comm	_MC_VM_L1_TLB_MCD_RD_B_CNTL,8,3 ; @MC_VM_L1_TLB_MCD_RD_B_CNTL
	.comm	_MC_VM_L1_TLB_MCD_WR_B_CNTL,8,3 ; @MC_VM_L1_TLB_MCD_WR_B_CNTL
	.comm	_MC_VM_L1_TLB_MCB_RD_GFX_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_RD_GFX_CNTL
	.comm	_MC_VM_L1_TLB_MCB_WR_GFX_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_WR_GFX_CNTL
	.comm	_MC_VM_L1_TLB_MCB_RD_PDMA_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
	.comm	_MC_VM_L1_TLB_MCB_WR_PDMA_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
	.comm	_MC_VM_L1_TLB_MCB_RD_SEM_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_RD_SEM_CNTL
	.comm	_MC_VM_L1_TLB_MCB_WR_SEM_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_WR_SEM_CNTL
	.comm	_MC_VM_L1_TLB_MCB_RD_SYS_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_RD_SYS_CNTL
	.comm	_MC_VM_L1_TLB_MCB_WR_SYS_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_WR_SYS_CNTL
	.comm	_MC_VM_L1_TLB_MCB_RD_HDP_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_RD_HDP_CNTL
	.comm	_MC_VM_L1_TLB_MCB_WR_HDP_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_WR_HDP_CNTL
	.comm	_MC_VM_L1_TLB_MCB_RD_UVD_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_RD_UVD_CNTL
	.comm	_MC_VM_L1_TLB_MCB_WR_UVD_CNTL,8,3 ; @MC_VM_L1_TLB_MCB_WR_UVD_CNTL
	.no_dead_strip	_r600_pcie_gart_disable
.subsections_via_symbols
