	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function uvd_v7_0_start
_uvd_v7_0_start:                        ## @uvd_v7_0_start
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, -56(%rbp)                 ## 8-byte Spill
	movl	(%rdi), %eax
	testl	%eax, %eax
	jle	LBB0_5
## %bb.1:
	xorl	%ebx, %ebx
	movq	_UVD@GOTPCREL(%rip), %r14
	movq	_mmUVD_POWER_STATUS@GOTPCREL(%rip), %r15
	movq	_UVD_POWER_STATUS__UVD_PG_MODE_MASK@GOTPCREL(%rip), %r12
	jmp	LBB0_2
	.p2align	4, 0x90
LBB0_4:                                 ##   in Loop: Header=BB0_2 Depth=1
	incl	%ebx
	cmpl	%eax, %ebx
	jge	LBB0_5
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	movl	4(%rcx), %ecx
	btl	%ebx, %ecx
	jb	LBB0_4
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movl	(%r14), %edi
	movl	(%r15), %edx
	movl	%ebx, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r12), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %eax
	jmp	LBB0_4
LBB0_5:
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	callq	_uvd_v7_0_mc_resume
	movl	(%rbx), %eax
	testl	%eax, %eax
	jle	LBB0_16
## %bb.6:
	xorl	%r15d, %r15d
	movq	_UVD@GOTPCREL(%rip), %r14
	movq	_mmUVD_STATUS@GOTPCREL(%rip), %r13
	jmp	LBB0_7
	.p2align	4, 0x90
LBB0_14:                                ##   in Loop: Header=BB0_7 Depth=1
	movl	(%r14), %edi
	movq	_mmUVD_MASTINT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_MASTINT_EN__SYS_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_UVD_MASTINT_EN__VCPU_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	callq	_WREG32_P
	movl	(%r14), %edi
	movl	(%r13), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_STATUS__VCPU_REPORT__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %edx
	shll	%cl, %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	leaq	(,%r15,8), %rax
	leaq	(%rax,%rax,2), %rax
	movq	%rax, -64(%rbp)                 ## 8-byte Spill
	movq	-72(%rbp), %r13                 ## 8-byte Reload
	movl	8(%r13,%rax), %edi
	callq	_order_base_2
	movq	_UVD_RBC_RB_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_RB_BUFSZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	xorl	%edi, %edi
	movl	%eax, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_BLKSZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_NO_FETCH@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_WPTR_POLL_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_NO_UPDATE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_RB_RPTR_WR_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r14), %edi
	movq	_mmUVD_RBC_RB_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movl	%r15d, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_RBC_RB_WPTR_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %r12d
	movq	_mmUVD_RBC_RB_RPTR_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	movl	12(%r13,%rbx), %edi
	callq	_upper_32_bits
	sarl	$2, %eax
	movl	%r12d, %edi
	movl	%r15d, %esi
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %r12d
	movq	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movl	12(%r13,%rbx), %edi
	callq	_lower_32_bits
	movl	%r12d, %edi
	movl	%r15d, %esi
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %r12d
	movq	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movl	12(%r13,%rbx), %edi
	callq	_upper_32_bits
	movl	%r12d, %edi
	movl	%r15d, %esi
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_RBC_RB_RPTR@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movl	%r15d, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movl	(%r12), %edx
	movl	%r15d, %esi
	callq	_RREG32_SOC15
	movl	%eax, 16(%r13,%rbx)
	movl	(%r14), %r12d
	movq	_mmUVD_RBC_RB_WPTR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r13d
	movl	%eax, %edi
	callq	_lower_32_bits
	movl	%r12d, %edi
	movl	%r15d, %esi
	movl	%r13d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_RBC_RB_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movq	8(%rax), %rax
	movq	-64(%rbp), %rcx                 ## 8-byte Reload
	movq	(%rax,%rcx), %rbx
	movl	(%r14), %r12d
	movq	_mmUVD_RB_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	8(%rbx), %edi
	callq	_lower_32_bits
	movl	%r12d, %edi
	movl	%r15d, %esi
	movl	%r13d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %r12d
	movq	_mmUVD_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	8(%rbx), %edi
	callq	_lower_32_bits
	movl	%r12d, %edi
	movl	%r15d, %esi
	movl	%r13d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_RB_BASE_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	4(%rbx), %ecx
	movl	%r15d, %esi
	callq	_WREG32_SOC15
	movl	(%r14), %r12d
	movq	_mmUVD_RB_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	4(%rbx), %edi
	callq	_upper_32_bits
	movl	%r12d, %edi
	movl	%r15d, %esi
	movl	%r13d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_RB_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%rbx), %eax
	leal	3(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$2, %ecx
	movl	%r15d, %esi
	callq	_WREG32_SOC15
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movq	8(%rax), %rax
	movq	-64(%rbp), %rcx                 ## 8-byte Reload
	movq	(%rax,%rcx), %rbx
	movl	(%r14), %r12d
	movq	_mmUVD_RB_RPTR2@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	20(%rbx), %edi
	callq	_lower_32_bits
	movl	%r12d, %edi
	movl	%r15d, %esi
	movl	%r13d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %r12d
	movq	_mmUVD_RB_WPTR2@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	20(%rbx), %edi
	callq	_lower_32_bits
	movl	%r12d, %edi
	movl	%r15d, %esi
	movl	%r13d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_RB_BASE_LO2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	16(%rbx), %ecx
	movl	%r15d, %esi
	callq	_WREG32_SOC15
	movl	(%r14), %r12d
	movq	_mmUVD_RB_BASE_HI2@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	16(%rbx), %edi
	callq	_upper_32_bits
	movl	%r12d, %edi
	movl	%r15d, %esi
	movl	%r13d, %edx
	movq	_mmUVD_STATUS@GOTPCREL(%rip), %r13
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_RB_SIZE2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	12(%rbx), %eax
	leal	3(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$2, %ecx
	movl	%r15d, %esi
	callq	_WREG32_SOC15
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %eax
LBB0_15:                                ##   in Loop: Header=BB0_7 Depth=1
	incq	%r15
	movslq	%eax, %rcx
	cmpq	%rcx, %r15
	jge	LBB0_16
LBB0_7:                                 ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_9 Depth 2
                                        ##       Child Loop BB0_10 Depth 3
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	movl	4(%rcx), %ecx
	btl	%r15d, %ecx
	jb	LBB0_15
## %bb.8:                               ##   in Loop: Header=BB0_7 Depth=1
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movq	8(%rax), %rax
	movq	%rax, -72(%rbp)                 ## 8-byte Spill
	movl	(%r14), %edi
	movq	_mmUVD_CGC_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	xorl	%r12d, %r12d
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	(%r14), %edi
	movq	_mmUVD_MASTINT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_MASTINT_EN__VCPU_EN_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	(%r14), %edi
	movq	_mmUVD_LMI_CTRL2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	callq	_WREG32_P
	movl	$1, %edi
	callq	_mdelay
	movl	(%r14), %edi
	movq	_mmUVD_SOFT_RESET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_UVD_SOFT_RESET__RBC_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_UVD_SOFT_RESET__CSM_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_UVD_SOFT_RESET__CXW_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_UVD_SOFT_RESET__TAP_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movl	%r15d, %esi
	callq	_WREG32_SOC15
	movl	$5, %edi
	callq	_mdelay
	movq	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$64, %eax
	shll	%cl, %eax
	movl	(%r14), %edi
	movq	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_mmUVD_LMI_CTRL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_UVD_LMI_CTRL__REQ_MODE_MASK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	orl	$1048576, %eax                  ## imm = 0x100000
	movl	%r15d, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_LMI_SWAP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_MP_SWAP_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_MPC_SET_MUXA0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	movl	$67903552, %ecx                 ## imm = 0x40C2040
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_MPC_SET_MUXA1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_MPC_SET_MUXB0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	movl	$67903552, %ecx                 ## imm = 0x40C2040
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_MPC_SET_MUXB1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_MPC_SET_ALU@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_MPC_SET_MUX@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	movl	$136, %ecx
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movl	(%rbx), %edx
	movq	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%r15d, %esi
	callq	_WREG32_SOC15
	movl	$5, %edi
	callq	_mdelay
	movl	(%r14), %edi
	movq	_mmUVD_VCPU_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_UVD_VCPU_CNTL__CLK_EN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%r15d, %esi
	callq	_WREG32_SOC15
	movl	(%r14), %edi
	movq	_mmUVD_LMI_CTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	(%r14), %edi
	movl	(%rbx), %edx
	movl	%r15d, %esi
	xorl	%ecx, %ecx
	callq	_WREG32_SOC15
	movl	$10, %edi
	callq	_mdelay
LBB0_9:                                 ##   Parent Loop BB0_7 Depth=1
                                        ## =>  This Loop Header: Depth=2
                                        ##       Child Loop BB0_10 Depth 3
	movl	$100, %ebx
	.p2align	4, 0x90
LBB0_10:                                ##   Parent Loop BB0_7 Depth=1
                                        ##     Parent Loop BB0_9 Depth=2
                                        ## =>    This Inner Loop Header: Depth=3
	movl	(%r14), %edi
	movl	(%r13), %edx
	movl	%r15d, %esi
	callq	_RREG32_SOC15
	testb	$2, %al
	jne	LBB0_14
## %bb.11:                              ##   in Loop: Header=BB0_10 Depth=3
	movl	$10, %edi
	callq	_mdelay
	decl	%ebx
	jne	LBB0_10
## %bb.12:                              ##   in Loop: Header=BB0_9 Depth=2
	leaq	L_.str(%rip), %rdi
	movl	%r15d, %esi
	callq	_DRM_ERROR
	movl	(%r14), %edi
	movq	_mmUVD_SOFT_RESET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movq	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	callq	_WREG32_P
	movl	$10, %edi
	callq	_mdelay
	movl	(%r14), %edi
	movl	(%rbx), %edx
	movl	%r15d, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r13), %edx
	movq	_mmUVD_STATUS@GOTPCREL(%rip), %r13
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	$10, %edi
	callq	_mdelay
	incl	%r12d
	cmpl	$10, %r12d
	jne	LBB0_9
## %bb.13:
	leaq	L_.str.1(%rip), %rdi
	movl	%r15d, %esi
	callq	_DRM_ERROR
	movl	$-1, %eax
	jmp	LBB0_17
LBB0_16:
	xorl	%eax, %eax
LBB0_17:
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_POWER_STATUS,4,2         ## @mmUVD_POWER_STATUS
	.comm	_UVD_POWER_STATUS__UVD_PG_MODE_MASK,4,2 ## @UVD_POWER_STATUS__UVD_PG_MODE_MASK
	.comm	_mmUVD_CGC_CTRL,4,2             ## @mmUVD_CGC_CTRL
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK,4,2 ## @UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK
	.comm	_mmUVD_MASTINT_EN,4,2           ## @mmUVD_MASTINT_EN
	.comm	_UVD_MASTINT_EN__VCPU_EN_MASK,4,2 ## @UVD_MASTINT_EN__VCPU_EN_MASK
	.comm	_mmUVD_LMI_CTRL2,4,2            ## @mmUVD_LMI_CTRL2
	.comm	_UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,4,2 ## @UVD_LMI_CTRL2__STALL_ARB_UMC_MASK
	.comm	_mmUVD_SOFT_RESET,4,2           ## @mmUVD_SOFT_RESET
	.comm	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__RBC_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__RBC_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__CSM_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__CSM_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__CXW_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__CXW_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__TAP_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__TAP_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,4,2 ## @UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
	.comm	_mmUVD_LMI_CTRL,4,2             ## @mmUVD_LMI_CTRL
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT,4,2 ## @UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK,4,2 ## @UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK
	.comm	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK,4,2 ## @UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK,4,2 ## @UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__REQ_MODE_MASK,4,2 ## @UVD_LMI_CTRL__REQ_MODE_MASK
	.comm	_mmUVD_LMI_SWAP_CNTL,4,2        ## @mmUVD_LMI_SWAP_CNTL
	.comm	_mmUVD_MP_SWAP_CNTL,4,2         ## @mmUVD_MP_SWAP_CNTL
	.comm	_mmUVD_MPC_SET_MUXA0,4,2        ## @mmUVD_MPC_SET_MUXA0
	.comm	_mmUVD_MPC_SET_MUXA1,4,2        ## @mmUVD_MPC_SET_MUXA1
	.comm	_mmUVD_MPC_SET_MUXB0,4,2        ## @mmUVD_MPC_SET_MUXB0
	.comm	_mmUVD_MPC_SET_MUXB1,4,2        ## @mmUVD_MPC_SET_MUXB1
	.comm	_mmUVD_MPC_SET_ALU,4,2          ## @mmUVD_MPC_SET_ALU
	.comm	_mmUVD_MPC_SET_MUX,4,2          ## @mmUVD_MPC_SET_MUX
	.comm	_mmUVD_VCPU_CNTL,4,2            ## @mmUVD_VCPU_CNTL
	.comm	_UVD_VCPU_CNTL__CLK_EN_MASK,4,2 ## @UVD_VCPU_CNTL__CLK_EN_MASK
	.comm	_mmUVD_STATUS,4,2               ## @mmUVD_STATUS
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"UVD(%d) not responding, trying to reset the VCPU!!!\n"

L_.str.1:                               ## @.str.1
	.asciz	"UVD(%d) not responding, giving up!!!\n"

	.comm	_UVD_MASTINT_EN__SYS_EN_MASK,4,2 ## @UVD_MASTINT_EN__SYS_EN_MASK
	.comm	_UVD_STATUS__VCPU_REPORT__SHIFT,4,2 ## @UVD_STATUS__VCPU_REPORT__SHIFT
	.comm	_UVD_RBC_RB_CNTL,4,2            ## @UVD_RBC_RB_CNTL
	.comm	_RB_BUFSZ,4,2                   ## @RB_BUFSZ
	.comm	_RB_BLKSZ,4,2                   ## @RB_BLKSZ
	.comm	_RB_NO_FETCH,4,2                ## @RB_NO_FETCH
	.comm	_RB_WPTR_POLL_EN,4,2            ## @RB_WPTR_POLL_EN
	.comm	_RB_NO_UPDATE,4,2               ## @RB_NO_UPDATE
	.comm	_RB_RPTR_WR_EN,4,2              ## @RB_RPTR_WR_EN
	.comm	_mmUVD_RBC_RB_CNTL,4,2          ## @mmUVD_RBC_RB_CNTL
	.comm	_mmUVD_RBC_RB_WPTR_CNTL,4,2     ## @mmUVD_RBC_RB_WPTR_CNTL
	.comm	_mmUVD_RBC_RB_RPTR_ADDR,4,2     ## @mmUVD_RBC_RB_RPTR_ADDR
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
	.comm	_mmUVD_RBC_RB_RPTR,4,2          ## @mmUVD_RBC_RB_RPTR
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ## @mmUVD_RBC_RB_WPTR
	.comm	_UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK,4,2 ## @UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK
	.comm	_mmUVD_RB_RPTR,4,2              ## @mmUVD_RB_RPTR
	.comm	_mmUVD_RB_WPTR,4,2              ## @mmUVD_RB_WPTR
	.comm	_mmUVD_RB_BASE_LO,4,2           ## @mmUVD_RB_BASE_LO
	.comm	_mmUVD_RB_BASE_HI,4,2           ## @mmUVD_RB_BASE_HI
	.comm	_mmUVD_RB_SIZE,4,2              ## @mmUVD_RB_SIZE
	.comm	_mmUVD_RB_RPTR2,4,2             ## @mmUVD_RB_RPTR2
	.comm	_mmUVD_RB_WPTR2,4,2             ## @mmUVD_RB_WPTR2
	.comm	_mmUVD_RB_BASE_LO2,4,2          ## @mmUVD_RB_BASE_LO2
	.comm	_mmUVD_RB_BASE_HI2,4,2          ## @mmUVD_RB_BASE_HI2
	.comm	_mmUVD_RB_SIZE2,4,2             ## @mmUVD_RB_SIZE2
	.no_dead_strip	_uvd_v7_0_start
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function uvd_v7_0_start
_uvd_v7_0_start:                        ; @uvd_v7_0_start
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	w8, [x0]
Lloh0:
	adrp	x24, _UVD@GOTPAGE
Lloh1:
	ldr	x24, [x24, _UVD@GOTPAGEOFF]
	cmp	w8, #1
	b.lt	LBB0_5
; %bb.1:
	mov	w20, #0
Lloh2:
	adrp	x21, _mmUVD_POWER_STATUS@GOTPAGE
Lloh3:
	ldr	x21, [x21, _mmUVD_POWER_STATUS@GOTPAGEOFF]
Lloh4:
	adrp	x22, _UVD_POWER_STATUS__UVD_PG_MODE_MASK@GOTPAGE
Lloh5:
	ldr	x22, [x22, _UVD_POWER_STATUS__UVD_PG_MODE_MASK@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:                                 ;   in Loop: Header=BB0_3 Depth=1
	add	w20, w20, #1
	cmp	w20, w8
	b.ge	LBB0_5
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w9, [x19, #4]
	lsr	w9, w9, w20
	tbnz	w9, #0, LBB0_2
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	ldr	w0, [x24]
	ldr	w2, [x21]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x22]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w8, [x19]
	b	LBB0_2
LBB0_5:
	mov	x0, x19
	bl	_uvd_v7_0_mc_resume
	ldr	w8, [x19]
	cmp	w8, #1
	b.lt	LBB0_16
; %bb.6:
	mov	x20, #0
Lloh6:
	adrp	x27, _mmUVD_MASTINT_EN@GOTPAGE
Lloh7:
	ldr	x27, [x27, _mmUVD_MASTINT_EN@GOTPAGEOFF]
Lloh8:
	adrp	x21, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGE
Lloh9:
	ldr	x21, [x21, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGEOFF]
Lloh10:
	adrp	x28, _mmUVD_STATUS@GOTPAGE
Lloh11:
	ldr	x28, [x28, _mmUVD_STATUS@GOTPAGEOFF]
	b	LBB0_9
LBB0_7:                                 ;   in Loop: Header=BB0_9 Depth=1
	ldr	w0, [x24]
	ldr	w2, [x27]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x21]
Lloh12:
	adrp	x9, _UVD_MASTINT_EN__SYS_EN_MASK@GOTPAGE
Lloh13:
	ldr	x9, [x9, _UVD_MASTINT_EN__SYS_EN_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	orr	w1, w9, w8
	mvn	w2, w1
	bl	_WREG32_P
	ldr	w0, [x24]
	ldr	w2, [x28]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
Lloh15:
	adrp	x8, _UVD_STATUS__VCPU_REPORT__SHIFT@GOTPAGE
Lloh16:
	ldr	x8, [x8, _UVD_STATUS__VCPU_REPORT__SHIFT@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	mov	w9, #2
	lsl	w8, w9, w8
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	add	x8, x20, x20, lsl #1
	lsl	x26, x8, #3
	mov	x21, x27
	ldr	x8, [sp, #8]                    ; 8-byte Folded Reload
	add	x27, x8, x26
	ldr	w0, [x27, #8]
	bl	_order_base_2
	mov	x3, x0
Lloh18:
	adrp	x22, _UVD_RBC_RB_CNTL@GOTPAGE
Lloh19:
	ldr	x22, [x22, _UVD_RBC_RB_CNTL@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh20:
	adrp	x8, _RB_BUFSZ@GOTPAGE
Lloh21:
	ldr	x8, [x8, _RB_BUFSZ@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
	mov	w0, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x22]
Lloh23:
	adrp	x8, _RB_BLKSZ@GOTPAGE
Lloh24:
	ldr	x8, [x8, _RB_BLKSZ@GOTPAGEOFF]
Lloh25:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x22]
Lloh26:
	adrp	x8, _RB_NO_FETCH@GOTPAGE
Lloh27:
	ldr	x8, [x8, _RB_NO_FETCH@GOTPAGEOFF]
Lloh28:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x22]
Lloh29:
	adrp	x8, _RB_WPTR_POLL_EN@GOTPAGE
Lloh30:
	ldr	x8, [x8, _RB_WPTR_POLL_EN@GOTPAGEOFF]
Lloh31:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x22]
Lloh32:
	adrp	x8, _RB_NO_UPDATE@GOTPAGE
Lloh33:
	ldr	x8, [x8, _RB_NO_UPDATE@GOTPAGEOFF]
Lloh34:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w1, [x22]
Lloh35:
	adrp	x8, _RB_RPTR_WR_EN@GOTPAGE
Lloh36:
	ldr	x8, [x8, _RB_RPTR_WR_EN@GOTPAGEOFF]
Lloh37:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x24]
Lloh38:
	adrp	x25, _mmUVD_RBC_RB_CNTL@GOTPAGE
Lloh39:
	ldr	x25, [x25, _mmUVD_RBC_RB_CNTL@GOTPAGEOFF]
	ldr	w2, [x25]
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh40:
	adrp	x8, _mmUVD_RBC_RB_WPTR_CNTL@GOTPAGE
Lloh41:
	ldr	x8, [x8, _mmUVD_RBC_RB_WPTR_CNTL@GOTPAGEOFF]
Lloh42:
	ldr	w2, [x8]
	mov	x1, x20
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w22, [x24]
Lloh43:
	adrp	x8, _mmUVD_RBC_RB_RPTR_ADDR@GOTPAGE
Lloh44:
	ldr	x8, [x8, _mmUVD_RBC_RB_RPTR_ADDR@GOTPAGEOFF]
Lloh45:
	ldr	w23, [x8]
	ldr	w0, [x27, #12]
	bl	_upper_32_bits
	asr	w3, w0, #2
	mov	x0, x22
	mov	x1, x20
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w22, [x24]
Lloh46:
	adrp	x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPAGE
Lloh47:
	ldr	x8, [x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh48:
	ldr	w23, [x8]
	ldr	w0, [x27, #12]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x20
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w22, [x24]
Lloh49:
	adrp	x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPAGE
Lloh50:
	ldr	x8, [x8, _mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh51:
	ldr	w23, [x8]
	ldr	w0, [x27, #12]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x20
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh52:
	adrp	x22, _mmUVD_RBC_RB_RPTR@GOTPAGE
Lloh53:
	ldr	x22, [x22, _mmUVD_RBC_RB_RPTR@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	x1, x20
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x24]
	ldr	w2, [x22]
	mov	x1, x20
	bl	_RREG32_SOC15
	str	w0, [x27, #16]
	ldr	w22, [x24]
Lloh54:
	adrp	x8, _mmUVD_RBC_RB_WPTR@GOTPAGE
Lloh55:
	ldr	x8, [x8, _mmUVD_RBC_RB_WPTR@GOTPAGEOFF]
Lloh56:
	ldr	w23, [x8]
                                        ; kill: def $w0 killed $w0 killed $x0
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x20
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w0, [x24]
	ldr	w2, [x25]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
Lloh57:
	adrp	x8, _UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK@GOTPAGE
Lloh58:
	ldr	x8, [x8, _UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK@GOTPAGEOFF]
Lloh59:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	x8, [x19, #8]
	ldr	x27, [x8, x26]
	ldr	w22, [x24]
Lloh60:
	adrp	x8, _mmUVD_RB_RPTR@GOTPAGE
Lloh61:
	ldr	x8, [x8, _mmUVD_RB_RPTR@GOTPAGEOFF]
Lloh62:
	ldr	w23, [x8]
	ldr	w0, [x27, #8]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x20
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w22, [x24]
Lloh63:
	adrp	x8, _mmUVD_RB_WPTR@GOTPAGE
Lloh64:
	ldr	x8, [x8, _mmUVD_RB_WPTR@GOTPAGEOFF]
Lloh65:
	ldr	w23, [x8]
	ldr	w0, [x27, #8]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x20
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh66:
	adrp	x8, _mmUVD_RB_BASE_LO@GOTPAGE
Lloh67:
	ldr	x8, [x8, _mmUVD_RB_BASE_LO@GOTPAGEOFF]
Lloh68:
	ldr	w2, [x8]
	ldr	w3, [x27, #4]
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w22, [x24]
Lloh69:
	adrp	x8, _mmUVD_RB_BASE_HI@GOTPAGE
Lloh70:
	ldr	x8, [x8, _mmUVD_RB_BASE_HI@GOTPAGEOFF]
Lloh71:
	ldr	w23, [x8]
	ldr	w0, [x27, #4]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x20
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh72:
	adrp	x8, _mmUVD_RB_SIZE@GOTPAGE
Lloh73:
	ldr	x8, [x8, _mmUVD_RB_SIZE@GOTPAGEOFF]
Lloh74:
	ldr	w2, [x8]
	ldr	w8, [x27]
	mov	x27, x21
Lloh75:
	adrp	x21, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGE
Lloh76:
	ldr	x21, [x21, _UVD_MASTINT_EN__VCPU_EN_MASK@GOTPAGEOFF]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w3, w8, #2
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	x8, [x19, #8]
	ldr	x26, [x8, x26]
	ldr	w22, [x24]
Lloh77:
	adrp	x8, _mmUVD_RB_RPTR2@GOTPAGE
Lloh78:
	ldr	x8, [x8, _mmUVD_RB_RPTR2@GOTPAGEOFF]
Lloh79:
	ldr	w23, [x8]
	ldr	w0, [x26, #20]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x20
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w22, [x24]
Lloh80:
	adrp	x8, _mmUVD_RB_WPTR2@GOTPAGE
Lloh81:
	ldr	x8, [x8, _mmUVD_RB_WPTR2@GOTPAGEOFF]
Lloh82:
	ldr	w23, [x8]
	ldr	w0, [x26, #20]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x20
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh83:
	adrp	x8, _mmUVD_RB_BASE_LO2@GOTPAGE
Lloh84:
	ldr	x8, [x8, _mmUVD_RB_BASE_LO2@GOTPAGEOFF]
Lloh85:
	ldr	w2, [x8]
	ldr	w3, [x26, #16]
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w22, [x24]
Lloh86:
	adrp	x8, _mmUVD_RB_BASE_HI2@GOTPAGE
Lloh87:
	ldr	x8, [x8, _mmUVD_RB_BASE_HI2@GOTPAGEOFF]
Lloh88:
	ldr	w23, [x8]
	ldr	w0, [x26, #16]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	x1, x20
	mov	x2, x23
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh89:
	adrp	x8, _mmUVD_RB_SIZE2@GOTPAGE
Lloh90:
	ldr	x8, [x8, _mmUVD_RB_SIZE2@GOTPAGEOFF]
Lloh91:
	ldr	w2, [x8]
	ldr	w8, [x26, #12]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w3, w8, #2
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w8, [x19]
LBB0_8:                                 ;   in Loop: Header=BB0_9 Depth=1
	add	x20, x20, #1
	cmp	x20, w8, sxtw
	b.ge	LBB0_16
LBB0_9:                                 ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_11 Depth 2
                                        ;       Child Loop BB0_12 Depth 3
	ldr	w9, [x19, #4]
	lsr	w9, w9, w20
	tbnz	w9, #0, LBB0_8
; %bb.10:                               ;   in Loop: Header=BB0_9 Depth=1
	ldr	x8, [x19, #8]
	str	x8, [sp, #8]                    ; 8-byte Folded Spill
	ldr	w0, [x24]
Lloh92:
	adrp	x8, _mmUVD_CGC_CTRL@GOTPAGE
Lloh93:
	ldr	x8, [x8, _mmUVD_CGC_CTRL@GOTPAGEOFF]
Lloh94:
	ldr	w2, [x8]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
Lloh95:
	adrp	x8, _UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPAGE
Lloh96:
	ldr	x8, [x8, _UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK@GOTPAGEOFF]
Lloh97:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w0, [x24]
	ldr	w2, [x27]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x21]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w0, [x24]
Lloh98:
	adrp	x23, _mmUVD_LMI_CTRL2@GOTPAGE
Lloh99:
	ldr	x23, [x23, _mmUVD_LMI_CTRL2@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
Lloh100:
	adrp	x25, _UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPAGE
Lloh101:
	ldr	x25, [x25, _UVD_LMI_CTRL2__STALL_ARB_UMC_MASK@GOTPAGEOFF]
	ldr	w1, [x25]
	mvn	w2, w1
	bl	_WREG32_P
	mov	w0, #1
	bl	_mdelay
	ldr	w0, [x24]
Lloh102:
	adrp	x26, _mmUVD_SOFT_RESET@GOTPAGE
Lloh103:
	ldr	x26, [x26, _mmUVD_SOFT_RESET@GOTPAGEOFF]
	ldr	w2, [x26]
Lloh104:
	adrp	x8, _UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPAGE
Lloh105:
	ldr	x8, [x8, _UVD_SOFT_RESET__LMI_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh106:
	ldr	w8, [x8]
Lloh107:
	adrp	x22, _UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPAGE
Lloh108:
	ldr	x22, [x22, _UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPAGEOFF]
	ldr	w9, [x22]
	orr	w8, w9, w8
Lloh109:
	adrp	x9, _UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK@GOTPAGE
Lloh110:
	ldr	x9, [x9, _UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh111:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh112:
	adrp	x9, _UVD_SOFT_RESET__RBC_SOFT_RESET_MASK@GOTPAGE
Lloh113:
	ldr	x9, [x9, _UVD_SOFT_RESET__RBC_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh114:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh115:
	adrp	x9, _UVD_SOFT_RESET__CSM_SOFT_RESET_MASK@GOTPAGE
Lloh116:
	ldr	x9, [x9, _UVD_SOFT_RESET__CSM_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh117:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh118:
	adrp	x9, _UVD_SOFT_RESET__CXW_SOFT_RESET_MASK@GOTPAGE
Lloh119:
	ldr	x9, [x9, _UVD_SOFT_RESET__CXW_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh120:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh121:
	adrp	x9, _UVD_SOFT_RESET__TAP_SOFT_RESET_MASK@GOTPAGE
Lloh122:
	ldr	x9, [x9, _UVD_SOFT_RESET__TAP_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh123:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh124:
	adrp	x9, _UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPAGE
Lloh125:
	ldr	x9, [x9, _UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh126:
	ldr	w9, [x9]
	orr	w3, w8, w9
	mov	x1, x20
	bl	_WREG32_SOC15
	mov	w0, #5
	bl	_mdelay
	ldr	w0, [x24]
Lloh127:
	adrp	x8, _mmUVD_LMI_CTRL@GOTPAGE
Lloh128:
	ldr	x8, [x8, _mmUVD_LMI_CTRL@GOTPAGEOFF]
Lloh129:
	ldr	w2, [x8]
Lloh130:
	adrp	x8, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT@GOTPAGE
Lloh131:
	ldr	x8, [x8, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT@GOTPAGEOFF]
Lloh132:
	ldr	w8, [x8]
	mov	w9, #64
	lsl	w8, w9, w8
Lloh133:
	adrp	x9, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPAGE
Lloh134:
	ldr	x9, [x9, _UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK@GOTPAGEOFF]
Lloh135:
	ldr	w9, [x9]
Lloh136:
	adrp	x10, _UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPAGE
Lloh137:
	ldr	x10, [x10, _UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK@GOTPAGEOFF]
Lloh138:
	ldr	w10, [x10]
Lloh139:
	adrp	x11, _UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPAGE
Lloh140:
	ldr	x11, [x11, _UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK@GOTPAGEOFF]
Lloh141:
	ldr	w11, [x11]
Lloh142:
	adrp	x12, _UVD_LMI_CTRL__REQ_MODE_MASK@GOTPAGE
Lloh143:
	ldr	x12, [x12, _UVD_LMI_CTRL__REQ_MODE_MASK@GOTPAGEOFF]
Lloh144:
	ldr	w12, [x12]
	orr	w8, w9, w8
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w3, w8, #0x100000
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh145:
	adrp	x8, _mmUVD_LMI_SWAP_CNTL@GOTPAGE
Lloh146:
	ldr	x8, [x8, _mmUVD_LMI_SWAP_CNTL@GOTPAGEOFF]
Lloh147:
	ldr	w2, [x8]
	mov	x1, x20
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh148:
	adrp	x8, _mmUVD_MP_SWAP_CNTL@GOTPAGE
Lloh149:
	ldr	x8, [x8, _mmUVD_MP_SWAP_CNTL@GOTPAGEOFF]
Lloh150:
	ldr	w2, [x8]
	mov	x1, x20
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh151:
	adrp	x8, _mmUVD_MPC_SET_MUXA0@GOTPAGE
Lloh152:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXA0@GOTPAGEOFF]
Lloh153:
	ldr	w2, [x8]
	mov	x1, x20
	mov	w3, #8256
	movk	w3, #1036, lsl #16
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh154:
	adrp	x8, _mmUVD_MPC_SET_MUXA1@GOTPAGE
Lloh155:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXA1@GOTPAGEOFF]
Lloh156:
	ldr	w2, [x8]
	mov	x1, x20
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh157:
	adrp	x8, _mmUVD_MPC_SET_MUXB0@GOTPAGE
Lloh158:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXB0@GOTPAGEOFF]
Lloh159:
	ldr	w2, [x8]
	mov	x1, x20
	mov	w3, #8256
	movk	w3, #1036, lsl #16
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh160:
	adrp	x8, _mmUVD_MPC_SET_MUXB1@GOTPAGE
Lloh161:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUXB1@GOTPAGEOFF]
Lloh162:
	ldr	w2, [x8]
	mov	x1, x20
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh163:
	adrp	x8, _mmUVD_MPC_SET_ALU@GOTPAGE
Lloh164:
	ldr	x8, [x8, _mmUVD_MPC_SET_ALU@GOTPAGEOFF]
Lloh165:
	ldr	w2, [x8]
	mov	x1, x20
	mov	w3, #0
	bl	_WREG32_SOC15
	ldr	w0, [x24]
Lloh166:
	adrp	x8, _mmUVD_MPC_SET_MUX@GOTPAGE
Lloh167:
	ldr	x8, [x8, _mmUVD_MPC_SET_MUX@GOTPAGEOFF]
Lloh168:
	ldr	w2, [x8]
	mov	x1, x20
	mov	w3, #136
	bl	_WREG32_SOC15
	ldr	w0, [x24]
	ldr	w2, [x26]
	ldr	w3, [x22]
	mov	x1, x20
	bl	_WREG32_SOC15
	mov	w0, #5
	bl	_mdelay
	ldr	w0, [x24]
Lloh169:
	adrp	x8, _mmUVD_VCPU_CNTL@GOTPAGE
Lloh170:
	ldr	x8, [x8, _mmUVD_VCPU_CNTL@GOTPAGEOFF]
Lloh171:
	ldr	w2, [x8]
Lloh172:
	adrp	x8, _UVD_VCPU_CNTL__CLK_EN_MASK@GOTPAGE
Lloh173:
	ldr	x8, [x8, _UVD_VCPU_CNTL__CLK_EN_MASK@GOTPAGEOFF]
Lloh174:
	ldr	w3, [x8]
	mov	x1, x20
	bl	_WREG32_SOC15
	ldr	w0, [x24]
	ldr	w2, [x23]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x25]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	ldr	w0, [x24]
	ldr	w2, [x26]
	mov	x1, x20
	mov	w3, #0
	bl	_WREG32_SOC15
	mov	w0, #10
	bl	_mdelay
	mov	w23, #0
LBB0_11:                                ;   Parent Loop BB0_9 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_12 Depth 3
	mov	w26, #100
LBB0_12:                                ;   Parent Loop BB0_9 Depth=1
                                        ;     Parent Loop BB0_11 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	ldr	w0, [x24]
	ldr	w2, [x28]
	mov	x1, x20
	bl	_RREG32_SOC15
	tbnz	w0, #1, LBB0_7
; %bb.13:                               ;   in Loop: Header=BB0_12 Depth=3
	mov	w0, #10
	bl	_mdelay
	subs	w26, w26, #1
	b.ne	LBB0_12
; %bb.14:                               ;   in Loop: Header=BB0_11 Depth=2
Lloh175:
	adrp	x0, l_.str@PAGE
Lloh176:
	add	x0, x0, l_.str@PAGEOFF
	mov	x1, x20
	bl	_DRM_ERROR
	ldr	w0, [x24]
Lloh177:
	adrp	x25, _mmUVD_SOFT_RESET@GOTPAGE
Lloh178:
	ldr	x25, [x25, _mmUVD_SOFT_RESET@GOTPAGEOFF]
	ldr	w2, [x25]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
Lloh179:
	adrp	x22, _UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPAGE
Lloh180:
	ldr	x22, [x22, _UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK@GOTPAGEOFF]
	ldr	w1, [x22]
	mvn	w2, w1
	bl	_WREG32_P
	mov	w0, #10
	bl	_mdelay
	ldr	w0, [x24]
	ldr	w2, [x25]
	mov	x1, x20
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x22]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	mov	w0, #10
	bl	_mdelay
	add	w23, w23, #1
	cmp	w23, #10
	b.ne	LBB0_11
; %bb.15:
Lloh181:
	adrp	x0, l_.str.1@PAGE
Lloh182:
	add	x0, x0, l_.str.1@PAGEOFF
	mov	x1, x20
	bl	_DRM_ERROR
	mov	w0, #-1
	b	LBB0_17
LBB0_16:
	mov	w0, #0
LBB0_17:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGot	Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh172, Lloh173, Lloh174
	.loh AdrpLdrGotLdr	Lloh169, Lloh170, Lloh171
	.loh AdrpLdrGotLdr	Lloh166, Lloh167, Lloh168
	.loh AdrpLdrGotLdr	Lloh163, Lloh164, Lloh165
	.loh AdrpLdrGotLdr	Lloh160, Lloh161, Lloh162
	.loh AdrpLdrGotLdr	Lloh157, Lloh158, Lloh159
	.loh AdrpLdrGotLdr	Lloh154, Lloh155, Lloh156
	.loh AdrpLdrGotLdr	Lloh151, Lloh152, Lloh153
	.loh AdrpLdrGotLdr	Lloh148, Lloh149, Lloh150
	.loh AdrpLdrGotLdr	Lloh145, Lloh146, Lloh147
	.loh AdrpLdrGotLdr	Lloh142, Lloh143, Lloh144
	.loh AdrpLdrGotLdr	Lloh139, Lloh140, Lloh141
	.loh AdrpLdrGotLdr	Lloh136, Lloh137, Lloh138
	.loh AdrpLdrGotLdr	Lloh133, Lloh134, Lloh135
	.loh AdrpLdrGotLdr	Lloh130, Lloh131, Lloh132
	.loh AdrpLdrGotLdr	Lloh127, Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.loh AdrpLdrGotLdr	Lloh112, Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGot	Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGot	Lloh102, Lloh103
	.loh AdrpLdrGot	Lloh100, Lloh101
	.loh AdrpLdrGot	Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGot	Lloh179, Lloh180
	.loh AdrpLdrGot	Lloh177, Lloh178
	.loh AdrpAdd	Lloh175, Lloh176
	.loh AdrpAdd	Lloh181, Lloh182
	.cfi_endproc
                                        ; -- End function
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_POWER_STATUS,4,2         ; @mmUVD_POWER_STATUS
	.comm	_UVD_POWER_STATUS__UVD_PG_MODE_MASK,4,2 ; @UVD_POWER_STATUS__UVD_PG_MODE_MASK
	.comm	_mmUVD_CGC_CTRL,4,2             ; @mmUVD_CGC_CTRL
	.comm	_UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK,4,2 ; @UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK
	.comm	_mmUVD_MASTINT_EN,4,2           ; @mmUVD_MASTINT_EN
	.comm	_UVD_MASTINT_EN__VCPU_EN_MASK,4,2 ; @UVD_MASTINT_EN__VCPU_EN_MASK
	.comm	_mmUVD_LMI_CTRL2,4,2            ; @mmUVD_LMI_CTRL2
	.comm	_UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,4,2 ; @UVD_LMI_CTRL2__STALL_ARB_UMC_MASK
	.comm	_mmUVD_SOFT_RESET,4,2           ; @mmUVD_SOFT_RESET
	.comm	_UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__RBC_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__RBC_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__CSM_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__CSM_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__CXW_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__CXW_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__TAP_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__TAP_SOFT_RESET_MASK
	.comm	_UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,4,2 ; @UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
	.comm	_mmUVD_LMI_CTRL,4,2             ; @mmUVD_LMI_CTRL
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT,4,2 ; @UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT
	.comm	_UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK,4,2 ; @UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK
	.comm	_UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK,4,2 ; @UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK,4,2 ; @UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
	.comm	_UVD_LMI_CTRL__REQ_MODE_MASK,4,2 ; @UVD_LMI_CTRL__REQ_MODE_MASK
	.comm	_mmUVD_LMI_SWAP_CNTL,4,2        ; @mmUVD_LMI_SWAP_CNTL
	.comm	_mmUVD_MP_SWAP_CNTL,4,2         ; @mmUVD_MP_SWAP_CNTL
	.comm	_mmUVD_MPC_SET_MUXA0,4,2        ; @mmUVD_MPC_SET_MUXA0
	.comm	_mmUVD_MPC_SET_MUXA1,4,2        ; @mmUVD_MPC_SET_MUXA1
	.comm	_mmUVD_MPC_SET_MUXB0,4,2        ; @mmUVD_MPC_SET_MUXB0
	.comm	_mmUVD_MPC_SET_MUXB1,4,2        ; @mmUVD_MPC_SET_MUXB1
	.comm	_mmUVD_MPC_SET_ALU,4,2          ; @mmUVD_MPC_SET_ALU
	.comm	_mmUVD_MPC_SET_MUX,4,2          ; @mmUVD_MPC_SET_MUX
	.comm	_mmUVD_VCPU_CNTL,4,2            ; @mmUVD_VCPU_CNTL
	.comm	_UVD_VCPU_CNTL__CLK_EN_MASK,4,2 ; @UVD_VCPU_CNTL__CLK_EN_MASK
	.comm	_mmUVD_STATUS,4,2               ; @mmUVD_STATUS
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"UVD(%d) not responding, trying to reset the VCPU!!!\n"

l_.str.1:                               ; @.str.1
	.asciz	"UVD(%d) not responding, giving up!!!\n"

	.comm	_UVD_MASTINT_EN__SYS_EN_MASK,4,2 ; @UVD_MASTINT_EN__SYS_EN_MASK
	.comm	_UVD_STATUS__VCPU_REPORT__SHIFT,4,2 ; @UVD_STATUS__VCPU_REPORT__SHIFT
	.comm	_UVD_RBC_RB_CNTL,4,2            ; @UVD_RBC_RB_CNTL
	.comm	_RB_BUFSZ,4,2                   ; @RB_BUFSZ
	.comm	_RB_BLKSZ,4,2                   ; @RB_BLKSZ
	.comm	_RB_NO_FETCH,4,2                ; @RB_NO_FETCH
	.comm	_RB_WPTR_POLL_EN,4,2            ; @RB_WPTR_POLL_EN
	.comm	_RB_NO_UPDATE,4,2               ; @RB_NO_UPDATE
	.comm	_RB_RPTR_WR_EN,4,2              ; @RB_RPTR_WR_EN
	.comm	_mmUVD_RBC_RB_CNTL,4,2          ; @mmUVD_RBC_RB_CNTL
	.comm	_mmUVD_RBC_RB_WPTR_CNTL,4,2     ; @mmUVD_RBC_RB_WPTR_CNTL
	.comm	_mmUVD_RBC_RB_RPTR_ADDR,4,2     ; @mmUVD_RBC_RB_RPTR_ADDR
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
	.comm	_mmUVD_RBC_RB_RPTR,4,2          ; @mmUVD_RBC_RB_RPTR
	.comm	_mmUVD_RBC_RB_WPTR,4,2          ; @mmUVD_RBC_RB_WPTR
	.comm	_UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK,4,2 ; @UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK
	.comm	_mmUVD_RB_RPTR,4,2              ; @mmUVD_RB_RPTR
	.comm	_mmUVD_RB_WPTR,4,2              ; @mmUVD_RB_WPTR
	.comm	_mmUVD_RB_BASE_LO,4,2           ; @mmUVD_RB_BASE_LO
	.comm	_mmUVD_RB_BASE_HI,4,2           ; @mmUVD_RB_BASE_HI
	.comm	_mmUVD_RB_SIZE,4,2              ; @mmUVD_RB_SIZE
	.comm	_mmUVD_RB_RPTR2,4,2             ; @mmUVD_RB_RPTR2
	.comm	_mmUVD_RB_WPTR2,4,2             ; @mmUVD_RB_WPTR2
	.comm	_mmUVD_RB_BASE_LO2,4,2          ; @mmUVD_RB_BASE_LO2
	.comm	_mmUVD_RB_BASE_HI2,4,2          ; @mmUVD_RB_BASE_HI2
	.comm	_mmUVD_RB_SIZE2,4,2             ; @mmUVD_RB_SIZE2
	.no_dead_strip	_uvd_v7_0_start
.subsections_via_symbols
