	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function nvkm_dp_train_eq
_nvkm_dp_train_eq:                      ## @nvkm_dp_train_eq
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	8(%rdi), %rax
	movq	(%rax), %rax
	movq	_DPCD_RC02@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	_DPCD_RC02_TPS3_SUPPORTED@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	andl	(%rax,%rcx,4), %edx
	cmpl	$1, %edx
	movl	$3, %esi
	sbbl	$0, %esi
	callq	_nvkm_dp_train_pattern
	xorl	%r13d, %r13d
	.p2align	4, 0x90
LBB0_1:                                 ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_8 Depth 2
	testl	%r13d, %r13d
	je	LBB0_4
## %bb.2:                               ##   in Loop: Header=BB0_1 Depth=1
	movl	16(%r14), %esi
	movq	%r14, %rdi
	callq	_nvkm_dp_train_drive
	testq	%rax, %rax
	jne	LBB0_3
LBB0_4:                                 ##   in Loop: Header=BB0_1 Depth=1
	movl	16(%r14), %esi
	movq	%r14, %rdi
	movl	$400, %edx                      ## imm = 0x190
	callq	_nvkm_dp_train_sense
	movq	%rax, %rcx
	movl	$-1, %eax
	testq	%rcx, %rcx
	jne	LBB0_14
## %bb.5:                               ##   in Loop: Header=BB0_1 Depth=1
	movq	(%r14), %r8
	movq	8(%r14), %rsi
	movq	_DPCD_LS04_INTERLANE_ALIGN_DONE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	andl	8(%r8), %edx
	setne	%cl
	movq	8(%rsi), %rsi
	movl	(%rsi), %r9d
	movl	$1, %r12d
	testl	%r9d, %r9d
	jle	LBB0_10
## %bb.6:                               ##   in Loop: Header=BB0_1 Depth=1
	testl	%edx, %edx
	je	LBB0_10
## %bb.7:                               ##   in Loop: Header=BB0_1 Depth=1
	movq	_DPCD_LS02_LANE0_CR_DONE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r10d
	movq	_DPCD_LS02_LANE0_CHANNEL_EQ_DONE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r11d
	movq	_DPCD_LS02_LANE0_SYMBOL_LOCKED@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movl	$1, %ebx
	xorl	%edx, %edx
	movl	$1, %r12d
	.p2align	4, 0x90
LBB0_8:                                 ##   Parent Loop BB0_1 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	leal	-1(%rbx), %ecx
	shrl	%ecx
	movl	(%r8,%rcx,4), %esi
	movl	%edx, %ecx
	andb	$4, %cl
	sarl	%cl, %esi
	movl	%r12d, %ecx
	andl	$15, %esi
	movl	%esi, %r12d
	andl	%r10d, %r12d
	cmovnel	%ecx, %r12d
	testl	%r11d, %esi
	setne	%r15b
	testl	%esi, %edi
	setne	%cl
	andb	%r15b, %cl
	cmpl	%r9d, %ebx
	jge	LBB0_10
## %bb.9:                               ##   in Loop: Header=BB0_8 Depth=2
	incl	%ebx
	addl	$4, %edx
	testb	%cl, %cl
	jne	LBB0_8
LBB0_10:                                ##   in Loop: Header=BB0_1 Depth=1
	testb	%cl, %cl
	jne	LBB0_13
## %bb.11:                              ##   in Loop: Header=BB0_1 Depth=1
	testl	%r12d, %r12d
	je	LBB0_13
## %bb.12:                              ##   in Loop: Header=BB0_1 Depth=1
	incl	%r13d
	cmpl	$6, %r13d
	jne	LBB0_1
	jmp	LBB0_14
LBB0_13:
	xorb	$1, %cl
	movzbl	%cl, %eax
	negl	%eax
	jmp	LBB0_14
LBB0_3:
	movl	$-1, %eax
LBB0_14:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DPCD_RC02,8,3                  ## @DPCD_RC02
	.comm	_DPCD_RC02_TPS3_SUPPORTED,4,2   ## @DPCD_RC02_TPS3_SUPPORTED
	.comm	_DPCD_LS04_INTERLANE_ALIGN_DONE,4,2 ## @DPCD_LS04_INTERLANE_ALIGN_DONE
	.comm	_DPCD_LS02_LANE0_CR_DONE,4,2    ## @DPCD_LS02_LANE0_CR_DONE
	.comm	_DPCD_LS02_LANE0_CHANNEL_EQ_DONE,4,2 ## @DPCD_LS02_LANE0_CHANNEL_EQ_DONE
	.comm	_DPCD_LS02_LANE0_SYMBOL_LOCKED,4,2 ## @DPCD_LS02_LANE0_SYMBOL_LOCKED
	.no_dead_strip	_nvkm_dp_train_eq
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function nvkm_dp_train_eq
_nvkm_dp_train_eq:                      ; @nvkm_dp_train_eq
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	x8, [x0, #8]
	ldr	x8, [x8]
Lloh0:
	adrp	x9, _DPCD_RC02@GOTPAGE
Lloh1:
	ldr	x9, [x9, _DPCD_RC02@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	ldr	w8, [x8, x9, lsl #2]
Lloh3:
	adrp	x9, _DPCD_RC02_TPS3_SUPPORTED@GOTPAGE
Lloh4:
	ldr	x9, [x9, _DPCD_RC02_TPS3_SUPPORTED@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	tst	w9, w8
	mov	w8, #2
	cinc	w1, w8, ne
	bl	_nvkm_dp_train_pattern
	mov	w20, #0
Lloh6:
	adrp	x21, _DPCD_LS04_INTERLANE_ALIGN_DONE@GOTPAGE
Lloh7:
	ldr	x21, [x21, _DPCD_LS04_INTERLANE_ALIGN_DONE@GOTPAGEOFF]
Lloh8:
	adrp	x22, _DPCD_LS02_LANE0_CR_DONE@GOTPAGE
Lloh9:
	ldr	x22, [x22, _DPCD_LS02_LANE0_CR_DONE@GOTPAGEOFF]
Lloh10:
	adrp	x23, _DPCD_LS02_LANE0_CHANNEL_EQ_DONE@GOTPAGE
Lloh11:
	ldr	x23, [x23, _DPCD_LS02_LANE0_CHANNEL_EQ_DONE@GOTPAGEOFF]
Lloh12:
	adrp	x24, _DPCD_LS02_LANE0_SYMBOL_LOCKED@GOTPAGE
Lloh13:
	ldr	x24, [x24, _DPCD_LS02_LANE0_SYMBOL_LOCKED@GOTPAGEOFF]
LBB0_1:                                 ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
	cbz	w20, LBB0_3
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	ldr	w1, [x19, #16]
	mov	x0, x19
	bl	_nvkm_dp_train_drive
	cbnz	x0, LBB0_12
LBB0_3:                                 ;   in Loop: Header=BB0_1 Depth=1
	ldr	w1, [x19, #16]
	mov	x0, x19
	mov	w2, #400
	bl	_nvkm_dp_train_sense
	cbnz	x0, LBB0_12
; %bb.4:                                ;   in Loop: Header=BB0_1 Depth=1
	ldp	x8, x9, [x19]
	ldr	w10, [x8, #8]
	ldr	w11, [x21]
	ands	w11, w11, w10
	cset	w15, ne
	ldr	x9, [x9, #8]
	ldr	w10, [x9]
	cmp	w10, #1
	ccmp	w11, #0, #4, ge
	b.ne	LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_1 Depth=1
	mov	w9, #1
	b	LBB0_9
LBB0_6:                                 ;   in Loop: Header=BB0_1 Depth=1
	mov	w11, #0
	ldr	w12, [x22]
	ldr	w13, [x23]
	mov	w14, #1
	mov	w9, #1
	ldr	w16, [x24]
LBB0_7:                                 ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	sub	w15, w14, #1
	lsr	w15, w15, #1
	ldr	w15, [x8, w15, uxtw #2]
	and	w17, w11, #0x4
	asr	w15, w15, w17
	and	w15, w15, #0xf
	tst	w15, w12
	csel	w9, wzr, w9, eq
	tst	w15, w13
	cset	w17, ne
	tst	w16, w15
	cset	w15, ne
	and	w15, w17, w15
	cmp	w14, w10
	b.ge	LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=2
	add	w14, w14, #1
	add	w11, w11, #4
	tbnz	w15, #0, LBB0_7
LBB0_9:                                 ;   in Loop: Header=BB0_1 Depth=1
	tbnz	w15, #0, LBB0_13
; %bb.10:                               ;   in Loop: Header=BB0_1 Depth=1
	cbz	w9, LBB0_13
; %bb.11:                               ;   in Loop: Header=BB0_1 Depth=1
	add	w20, w20, #1
	cmp	w20, #6
	b.ne	LBB0_1
LBB0_12:
	mov	w0, #-1
	b	LBB0_14
LBB0_13:
	eor	w8, w15, #0x1
	sbfx	w0, w8, #0, #1
LBB0_14:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_DPCD_RC02,8,3                  ; @DPCD_RC02
	.comm	_DPCD_RC02_TPS3_SUPPORTED,4,2   ; @DPCD_RC02_TPS3_SUPPORTED
	.comm	_DPCD_LS04_INTERLANE_ALIGN_DONE,4,2 ; @DPCD_LS04_INTERLANE_ALIGN_DONE
	.comm	_DPCD_LS02_LANE0_CR_DONE,4,2    ; @DPCD_LS02_LANE0_CR_DONE
	.comm	_DPCD_LS02_LANE0_CHANNEL_EQ_DONE,4,2 ; @DPCD_LS02_LANE0_CHANNEL_EQ_DONE
	.comm	_DPCD_LS02_LANE0_SYMBOL_LOCKED,4,2 ; @DPCD_LS02_LANE0_SYMBOL_LOCKED
	.no_dead_strip	_nvkm_dp_train_eq
.subsections_via_symbols
