	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v10_0_cp_gfx_load_me_microcode
_gfx_v10_0_cp_gfx_load_me_microcode:    ## @gfx_v10_0_cp_gfx_load_me_microcode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	16(%rdi), %rax
	movq	(%rax), %rbx
	movq	%rbx, %rdi
	callq	_amdgpu_ucode_print_gfx_hdr
	movq	16(%r12), %rax
	movq	(%rax), %r15
	movl	4(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movl	(%rbx), %edi
	callq	_le32_to_cpu
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movl	(%rbx), %esi
	movq	_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_AMDGPU_GEM_DOMAIN_GTT@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	leaq	4(%r12), %rbx
	leaq	8(%r12), %r13
	movq	%r13, (%rsp)
	movq	%r12, %rdi
	movq	%rbx, %r8
	movq	%r12, %r9
	callq	_amdgpu_bo_create_reserved
	testl	%eax, %eax
	je	LBB0_2
## %bb.1:
	movl	%eax, %r14d
	movl	32(%r12), %edi
	leaq	L_.str(%rip), %rsi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_dev_err
	movq	%r12, %rdi
	callq	_gfx_v10_0_me_fini
	jmp	LBB0_9
LBB0_2:
	movq	%r12, -56(%rbp)                 ## 8-byte Spill
	movl	-44(%rbp), %eax                 ## 4-byte Reload
	addq	%rax, %r15
	movl	(%r13), %edi
	movq	%r15, %rsi
	movl	-48(%rbp), %edx                 ## 4-byte Reload
	callq	_memcpy
	movl	(%rbx), %edi
	callq	_amdgpu_bo_kunmap
	movl	(%rbx), %edi
	callq	_amdgpu_bo_unreserve
	movq	_GC@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_mmCP_ME_IC_OP_CNTL@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_CP_ME_IC_OP_CNTL@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	_INVALIDATE_CACHE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movq	%rbx, %r12
	movl	(%rbx), %edi
	movl	(%r14), %edx
	xorl	%esi, %esi
	movl	%eax, %ecx
	callq	_WREG32_SOC15
	movl	$50000, %ebx                    ## imm = 0xC350
	movq	_INVALIDATE_CACHE_COMPLETE@GOTPCREL(%rip), %r15
	.p2align	4, 0x90
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r12), %edi
	movl	(%r14), %edx
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movl	(%r13), %esi
	movl	(%r15), %edx
	movl	%eax, %edi
	callq	_REG_GET_FIELD
	cmpl	$1, %eax
	je	LBB0_6
## %bb.4:                               ##   in Loop: Header=BB0_3 Depth=1
	movl	$1, %edi
	callq	_udelay
	decl	%ebx
	jne	LBB0_3
## %bb.5:
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	32(%rax), %edi
	leaq	L_.str.1(%rip), %rsi
	xorl	%r14d, %r14d
	xorl	%eax, %eax
	callq	_dev_err
	movq	_EINVAL@GOTPCREL(%rip), %rax
	subl	(%rax), %r14d
	jmp	LBB0_9
LBB0_6:
	movq	_amdgpu_emu_mode@GOTPCREL(%rip), %rax
	cmpl	$1, (%rax)
	movq	-56(%rbp), %r13                 ## 8-byte Reload
	jne	LBB0_8
## %bb.7:
	movq	24(%r13), %rax
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	*(%rax)
LBB0_8:
	movl	(%r12), %edi
	movq	_mmCP_ME_IC_BASE_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%r14d, %r14d
	xorl	%esi, %esi
	callq	_RREG32_SOC15
	movq	_CP_ME_IC_BASE_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_VMID@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_CACHE_POLICY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_EXE_DISABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movl	(%rbx), %esi
	movq	_ADDRESS_CLAMP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r12), %edi
	movq	_mmCP_ME_IC_BASE_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	$-4096, %ecx                    ## imm = 0xF000
	andl	(%r13), %ecx
	xorl	%esi, %esi
	callq	_WREG32_SOC15
	movl	(%r12), %ebx
	movq	_mmCP_ME_IC_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	(%r13), %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r15d, %edx
	movl	%eax, %ecx
	callq	_WREG32_SOC15
LBB0_9:
	movl	%r14d, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
	.comm	_AMDGPU_GEM_DOMAIN_GTT,4,2      ## @AMDGPU_GEM_DOMAIN_GTT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"(%d) failed to create me fw bo\n"

	.comm	_GC,4,2                         ## @GC
	.comm	_mmCP_ME_IC_OP_CNTL,4,2         ## @mmCP_ME_IC_OP_CNTL
	.comm	_CP_ME_IC_OP_CNTL,4,2           ## @CP_ME_IC_OP_CNTL
	.comm	_INVALIDATE_CACHE,4,2           ## @INVALIDATE_CACHE
	.comm	_INVALIDATE_CACHE_COMPLETE,4,2  ## @INVALIDATE_CACHE_COMPLETE
L_.str.1:                               ## @.str.1
	.asciz	"failed to invalidate instruction cache\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_amdgpu_emu_mode,4,2            ## @amdgpu_emu_mode
	.comm	_mmCP_ME_IC_BASE_CNTL,4,2       ## @mmCP_ME_IC_BASE_CNTL
	.comm	_CP_ME_IC_BASE_CNTL,4,2         ## @CP_ME_IC_BASE_CNTL
	.comm	_VMID,4,2                       ## @VMID
	.comm	_CACHE_POLICY,4,2               ## @CACHE_POLICY
	.comm	_EXE_DISABLE,4,2                ## @EXE_DISABLE
	.comm	_ADDRESS_CLAMP,4,2              ## @ADDRESS_CLAMP
	.comm	_mmCP_ME_IC_BASE_LO,4,2         ## @mmCP_ME_IC_BASE_LO
	.comm	_mmCP_ME_IC_BASE_HI,4,2         ## @mmCP_ME_IC_BASE_HI
	.no_dead_strip	_gfx_v10_0_cp_gfx_load_me_microcode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v10_0_cp_gfx_load_me_microcode
_gfx_v10_0_cp_gfx_load_me_microcode:    ; @gfx_v10_0_cp_gfx_load_me_microcode
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldr	x8, [x0, #16]
	ldr	x20, [x8]
	mov	x0, x20
	bl	_amdgpu_ucode_print_gfx_hdr
	ldr	x8, [x19, #16]
	ldr	x25, [x8]
	ldr	w0, [x20, #4]
	bl	_le32_to_cpu
	mov	x21, x0
	ldr	w0, [x20]
	bl	_le32_to_cpu
	mov	x22, x0
	ldr	w1, [x20]
Lloh0:
	adrp	x8, _PAGE_SIZE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PAGE_SIZE@GOTPAGEOFF]
Lloh2:
	ldr	w2, [x8]
Lloh3:
	adrp	x8, _AMDGPU_GEM_DOMAIN_GTT@GOTPAGE
Lloh4:
	ldr	x8, [x8, _AMDGPU_GEM_DOMAIN_GTT@GOTPAGEOFF]
Lloh5:
	ldr	w3, [x8]
	add	x20, x19, #4
	add	x24, x19, #8
	mov	x0, x19
	mov	x4, x20
	mov	x5, x19
	mov	x6, x24
	bl	_amdgpu_bo_create_reserved
	cbz	w0, LBB0_2
; %bb.1:
	mov	x23, x0
	ldr	w0, [x19, #32]
	str	x23, [sp]
Lloh6:
	adrp	x1, l_.str@PAGE
Lloh7:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
	mov	x0, x19
	bl	_gfx_v10_0_me_fini
	b	LBB0_9
LBB0_2:
	add	x1, x25, w21, uxtw
	ldr	w0, [x24]
	mov	x2, x22
	bl	_memcpy
	ldr	w0, [x20]
	bl	_amdgpu_bo_kunmap
	ldr	w0, [x20]
	bl	_amdgpu_bo_unreserve
Lloh8:
	adrp	x20, _GC@GOTPAGE
Lloh9:
	ldr	x20, [x20, _GC@GOTPAGEOFF]
	ldr	w0, [x20]
Lloh10:
	adrp	x21, _mmCP_ME_IC_OP_CNTL@GOTPAGE
Lloh11:
	ldr	x21, [x21, _mmCP_ME_IC_OP_CNTL@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh12:
	adrp	x22, _CP_ME_IC_OP_CNTL@GOTPAGE
Lloh13:
	ldr	x22, [x22, _CP_ME_IC_OP_CNTL@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh14:
	adrp	x8, _INVALIDATE_CACHE@GOTPAGE
Lloh15:
	ldr	x8, [x8, _INVALIDATE_CACHE@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x3, x0
	ldr	w0, [x20]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_WREG32_SOC15
	mov	w23, #50000
Lloh17:
	adrp	x24, _INVALIDATE_CACHE_COMPLETE@GOTPAGE
Lloh18:
	ldr	x24, [x24, _INVALIDATE_CACHE_COMPLETE@GOTPAGEOFF]
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x20]
	ldr	w2, [x21]
	mov	w1, #0
	bl	_RREG32_SOC15
	ldr	w1, [x22]
	ldr	w2, [x24]
	bl	_REG_GET_FIELD
	cmp	w0, #1
	b.eq	LBB0_6
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	mov	w0, #1
	bl	_udelay
	subs	w23, w23, #1
	b.ne	LBB0_3
; %bb.5:
	ldr	w0, [x19, #32]
Lloh19:
	adrp	x1, l_.str.1@PAGE
Lloh20:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_err
Lloh21:
	adrp	x8, _EINVAL@GOTPAGE
Lloh22:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	neg	w23, w8
	b	LBB0_9
LBB0_6:
Lloh24:
	adrp	x8, _amdgpu_emu_mode@GOTPAGE
Lloh25:
	ldr	x8, [x8, _amdgpu_emu_mode@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	cmp	w8, #1
	b.ne	LBB0_8
; %bb.7:
	ldr	x8, [x19, #24]
	ldr	x8, [x8]
	mov	x0, x19
	mov	x1, #0
	blr	x8
LBB0_8:
	ldr	w0, [x20]
Lloh27:
	adrp	x8, _mmCP_ME_IC_BASE_CNTL@GOTPAGE
Lloh28:
	ldr	x8, [x8, _mmCP_ME_IC_BASE_CNTL@GOTPAGEOFF]
Lloh29:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_RREG32_SOC15
Lloh30:
	adrp	x21, _CP_ME_IC_BASE_CNTL@GOTPAGE
Lloh31:
	ldr	x21, [x21, _CP_ME_IC_BASE_CNTL@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh32:
	adrp	x8, _VMID@GOTPAGE
Lloh33:
	ldr	x8, [x8, _VMID@GOTPAGEOFF]
Lloh34:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x21]
Lloh35:
	adrp	x8, _CACHE_POLICY@GOTPAGE
Lloh36:
	ldr	x8, [x8, _CACHE_POLICY@GOTPAGEOFF]
Lloh37:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x21]
Lloh38:
	adrp	x8, _EXE_DISABLE@GOTPAGE
Lloh39:
	ldr	x8, [x8, _EXE_DISABLE@GOTPAGEOFF]
Lloh40:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_REG_SET_FIELD
	ldr	w1, [x21]
Lloh41:
	adrp	x8, _ADDRESS_CLAMP@GOTPAGE
Lloh42:
	ldr	x8, [x8, _ADDRESS_CLAMP@GOTPAGEOFF]
Lloh43:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_REG_SET_FIELD
	ldr	w0, [x20]
Lloh44:
	adrp	x8, _mmCP_ME_IC_BASE_LO@GOTPAGE
Lloh45:
	ldr	x8, [x8, _mmCP_ME_IC_BASE_LO@GOTPAGEOFF]
Lloh46:
	ldr	w2, [x8]
	ldr	w8, [x19]
	and	w3, w8, #0xfffff000
	mov	w1, #0
	bl	_WREG32_SOC15
	ldr	w20, [x20]
Lloh47:
	adrp	x8, _mmCP_ME_IC_BASE_HI@GOTPAGE
Lloh48:
	ldr	x8, [x8, _mmCP_ME_IC_BASE_HI@GOTPAGEOFF]
Lloh49:
	ldr	w21, [x8]
	ldr	w0, [x19]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	bl	_WREG32_SOC15
	mov	w23, #0
LBB0_9:
	mov	x0, x23
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpAdd	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.cfi_endproc
                                        ; -- End function
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
	.comm	_AMDGPU_GEM_DOMAIN_GTT,4,2      ; @AMDGPU_GEM_DOMAIN_GTT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"(%d) failed to create me fw bo\n"

	.comm	_GC,4,2                         ; @GC
	.comm	_mmCP_ME_IC_OP_CNTL,4,2         ; @mmCP_ME_IC_OP_CNTL
	.comm	_CP_ME_IC_OP_CNTL,4,2           ; @CP_ME_IC_OP_CNTL
	.comm	_INVALIDATE_CACHE,4,2           ; @INVALIDATE_CACHE
	.comm	_INVALIDATE_CACHE_COMPLETE,4,2  ; @INVALIDATE_CACHE_COMPLETE
l_.str.1:                               ; @.str.1
	.asciz	"failed to invalidate instruction cache\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_amdgpu_emu_mode,4,2            ; @amdgpu_emu_mode
	.comm	_mmCP_ME_IC_BASE_CNTL,4,2       ; @mmCP_ME_IC_BASE_CNTL
	.comm	_CP_ME_IC_BASE_CNTL,4,2         ; @CP_ME_IC_BASE_CNTL
	.comm	_VMID,4,2                       ; @VMID
	.comm	_CACHE_POLICY,4,2               ; @CACHE_POLICY
	.comm	_EXE_DISABLE,4,2                ; @EXE_DISABLE
	.comm	_ADDRESS_CLAMP,4,2              ; @ADDRESS_CLAMP
	.comm	_mmCP_ME_IC_BASE_LO,4,2         ; @mmCP_ME_IC_BASE_LO
	.comm	_mmCP_ME_IC_BASE_HI,4,2         ; @mmCP_ME_IC_BASE_HI
	.no_dead_strip	_gfx_v10_0_cp_gfx_load_me_microcode
.subsections_via_symbols
