	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function smu_hw_init
_smu_hw_init:                           ## @smu_hw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	leaq	16(%rdi), %r14
	movq	24(%rdi), %rax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_3
## %bb.1:
	movq	(%r15), %rax
	movq	_CHIP_NAVI10@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_3
## %bb.2:
	movq	%r14, %rdi
	callq	_smu_load_microcode
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_14
LBB0_3:
	movq	%r14, %rdi
	callq	_smu_check_fw_status
	testl	%eax, %eax
	je	LBB0_5
## %bb.4:
	movl	%eax, %ebx
	leaq	L_.str(%rip), %rdi
	callq	_pr_err
LBB0_14:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_5:
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 8(%r15)
	je	LBB0_7
## %bb.6:
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_smu_powergate_sdma
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_smu_powergate_vcn
LBB0_7:
	xorl	%ebx, %ebx
	cmpl	$0, (%r14)
	je	LBB0_14
## %bb.8:
	movq	%r14, %rdi
	callq	_smu_feature_init_dpm
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_14
## %bb.9:
	movq	%r14, %rdi
	movl	$1, %esi
	callq	_smu_smc_table_hw_init
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_14
## %bb.10:
	movq	%r14, %rdi
	callq	_smu_alloc_memory_pool
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_14
## %bb.11:
	movq	%r14, %rdi
	callq	_smu_notify_memory_pool_location
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_14
## %bb.12:
	movq	%r14, %rdi
	callq	_smu_start_thermal_control
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_14
## %bb.13:
	xorl	%eax, %eax
	cmpl	$0, 16(%r15)
	setne	%al
	movl	%eax, 12(%r15)
	leaq	L_.str.1(%rip), %rdi
	callq	_pr_info
	xorl	%ebx, %ebx
	jmp	LBB0_14
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_CHIP_NAVI10,8,3                ## @CHIP_NAVI10
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"SMC firmware status is not correct\n"

	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
L_.str.1:                               ## @.str.1
	.asciz	"SMU is initialized successfully!\n"

	.no_dead_strip	_smu_hw_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function smu_hw_init
_smu_hw_init:                           ; @smu_hw_init
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	add	x20, x0, #16
	ldr	x8, [x0, #24]
Lloh0:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_3
; %bb.1:
	ldr	x8, [x19]
Lloh3:
	adrp	x9, _CHIP_NAVI10@GOTPAGE
Lloh4:
	ldr	x9, [x9, _CHIP_NAVI10@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_3
; %bb.2:
	mov	x0, x20
	bl	_smu_load_microcode
	mov	x21, x0
	cbnz	w0, LBB0_5
LBB0_3:
	mov	x0, x20
	bl	_smu_check_fw_status
	cbz	w0, LBB0_6
; %bb.4:
	mov	x21, x0
Lloh6:
	adrp	x0, l_.str@PAGE
Lloh7:
	add	x0, x0, l_.str@PAGEOFF
	bl	_pr_err
LBB0_5:
	mov	x0, x21
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_6:
	ldr	w8, [x19, #8]
Lloh8:
	adrp	x9, _AMD_IS_APU@GOTPAGE
Lloh9:
	ldr	x9, [x9, _AMD_IS_APU@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_8
; %bb.7:
	mov	x0, x20
	mov	w1, #0
	bl	_smu_powergate_sdma
	mov	x0, x20
	mov	w1, #0
	bl	_smu_powergate_vcn
LBB0_8:
	ldr	w8, [x20]
	cbz	w8, LBB0_15
; %bb.9:
	mov	x0, x20
	bl	_smu_feature_init_dpm
	mov	x21, x0
	cbnz	w0, LBB0_5
; %bb.10:
	mov	x0, x20
	mov	w1, #1
	bl	_smu_smc_table_hw_init
	mov	x21, x0
	cbnz	w0, LBB0_5
; %bb.11:
	mov	x0, x20
	bl	_smu_alloc_memory_pool
	mov	x21, x0
	cbnz	w0, LBB0_5
; %bb.12:
	mov	x0, x20
	bl	_smu_notify_memory_pool_location
	mov	x21, x0
	cbnz	w0, LBB0_5
; %bb.13:
	mov	x0, x20
	bl	_smu_start_thermal_control
	mov	x21, x0
	cbnz	w0, LBB0_5
; %bb.14:
	ldr	w8, [x19, #16]
	cmp	w8, #0
	cset	w8, ne
	str	w8, [x19, #12]
Lloh11:
	adrp	x0, l_.str.1@PAGE
Lloh12:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_pr_info
	b	LBB0_5
LBB0_15:
	mov	w21, #0
	b	LBB0_5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpAdd	Lloh11, Lloh12
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_CHIP_NAVI10,8,3                ; @CHIP_NAVI10
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"SMC firmware status is not correct\n"

	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
l_.str.1:                               ; @.str.1
	.asciz	"SMU is initialized successfully!\n"

	.no_dead_strip	_smu_hw_init
.subsections_via_symbols
