	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_dpu_hw_csc_setup               ## -- Begin function dpu_hw_csc_setup
	.p2align	4, 0x90
_dpu_hw_csc_setup:                      ## @dpu_hw_csc_setup
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r15
	movl	%esi, %ebx
	movq	%rdi, %r14
	testl	%ecx, %ecx
	setne	%r12b
	movq	(%rdx), %rax
	movl	(%rax), %ecx
	movl	4(%rax), %edx
	shrl	$7, %ecx
	andl	$8191, %ecx                     ## imm = 0x1FFF
	shll	$9, %edx
	andl	$536805376, %edx                ## imm = 0x1FFF0000
	orl	%ecx, %edx
	callq	_DPU_REG_WRITE
	movq	(%r15), %rax
	movl	8(%rax), %ecx
	movl	12(%rax), %edx
	shrl	$7, %ecx
	andl	$8191, %ecx                     ## imm = 0x1FFF
	shll	$9, %edx
	andl	$536805376, %edx                ## imm = 0x1FFF0000
	orl	%ecx, %edx
	leal	4(%rbx), %esi
	movq	%r14, %rdi
	callq	_DPU_REG_WRITE
	movq	(%r15), %rax
	movl	16(%rax), %ecx
	movl	20(%rax), %edx
	shrl	$7, %ecx
	andl	$8191, %ecx                     ## imm = 0x1FFF
	shll	$9, %edx
	andl	$536805376, %edx                ## imm = 0x1FFF0000
	orl	%ecx, %edx
	leal	8(%rbx), %esi
	movq	%r14, %rdi
	callq	_DPU_REG_WRITE
	movq	(%r15), %rax
	movl	24(%rax), %ecx
	movl	28(%rax), %edx
	shrl	$7, %ecx
	andl	$8191, %ecx                     ## imm = 0x1FFF
	shll	$9, %edx
	andl	$536805376, %edx                ## imm = 0x1FFF0000
	orl	%ecx, %edx
	leal	12(%rbx), %esi
	movq	%r14, %rdi
	callq	_DPU_REG_WRITE
	movq	(%r15), %rax
	movl	32(%rax), %edx
	shrl	$7, %edx
	andl	$8191, %edx                     ## imm = 0x1FFF
	leal	16(%rbx), %esi
	movq	%r14, %rdi
	callq	_DPU_REG_WRITE
	movq	8(%r15), %rax
	movl	(%rax), %edx
	shlb	$3, %r12b
	addb	$8, %r12b
	movl	%r12d, %ecx
	shll	%cl, %edx
	orl	4(%rax), %edx
	leal	20(%rbx), %esi
	movq	%r14, %rdi
	callq	_DPU_REG_WRITE
	movq	8(%r15), %rax
	movl	8(%rax), %edx
	movl	%r12d, %ecx
	shll	%cl, %edx
	orl	12(%rax), %edx
	leal	24(%rbx), %esi
	movq	%r14, %rdi
	callq	_DPU_REG_WRITE
	movq	8(%r15), %rax
	movl	16(%rax), %edx
	movl	%r12d, %ecx
	shll	%cl, %edx
	orl	20(%rax), %edx
	leal	28(%rbx), %esi
	movq	%r14, %rdi
	callq	_DPU_REG_WRITE
	movq	16(%r15), %rax
	movl	(%rax), %edx
	movl	%r12d, %ecx
	shll	%cl, %edx
	orl	4(%rax), %edx
	leal	32(%rbx), %esi
	movq	%r14, %rdi
	callq	_DPU_REG_WRITE
	movq	16(%r15), %rax
	movl	8(%rax), %edx
	movl	%r12d, %ecx
	shll	%cl, %edx
	orl	12(%rax), %edx
	leal	36(%rbx), %esi
	movq	%r14, %rdi
	callq	_DPU_REG_WRITE
	movq	16(%r15), %rax
	movl	16(%rax), %edx
	movl	%r12d, %ecx
	shll	%cl, %edx
	orl	20(%rax), %edx
	leal	40(%rbx), %esi
	movq	%r14, %rdi
	callq	_DPU_REG_WRITE
	leal	44(%rbx), %esi
	movq	24(%r15), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_DPU_REG_WRITE
	leal	48(%rbx), %esi
	movq	24(%r15), %rax
	movl	4(%rax), %edx
	movq	%r14, %rdi
	callq	_DPU_REG_WRITE
	leal	52(%rbx), %esi
	movq	24(%r15), %rax
	movl	8(%rax), %edx
	movq	%r14, %rdi
	callq	_DPU_REG_WRITE
	leal	56(%rbx), %esi
	movq	32(%r15), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_DPU_REG_WRITE
	leal	60(%rbx), %esi
	movq	32(%r15), %rax
	movl	4(%rax), %edx
	movq	%r14, %rdi
	callq	_DPU_REG_WRITE
	addl	$64, %ebx
	movq	32(%r15), %rax
	movl	8(%rax), %edx
	movq	%r14, %rdi
	movl	%ebx, %esi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_DPU_REG_WRITE                  ## TAILCALL
	.cfi_endproc
                                        ## -- End function
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_dpu_hw_csc_setup               ; -- Begin function dpu_hw_csc_setup
	.p2align	2
_dpu_hw_csc_setup:                      ; @dpu_hw_csc_setup
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x2
	mov	x21, x1
	mov	x19, x0
	mov	w8, #16
	mov	w9, #8
	cmp	w3, #0
	csel	w22, w9, w8, eq
	ldr	x8, [x2]
	ldp	w9, w8, [x8]
	lsl	w8, w8, #9
	and	w2, w8, #0x1fff0000
	bfxil	w2, w9, #7, #13
	bl	_DPU_REG_WRITE
	ldr	x8, [x20]
	ldp	w9, w8, [x8, #8]
	lsl	w8, w8, #9
	and	w2, w8, #0x1fff0000
	bfxil	w2, w9, #7, #13
	add	w1, w21, #4
	mov	x0, x19
	bl	_DPU_REG_WRITE
	ldr	x8, [x20]
	ldp	w9, w8, [x8, #16]
	lsl	w8, w8, #9
	and	w2, w8, #0x1fff0000
	bfxil	w2, w9, #7, #13
	add	w1, w21, #8
	mov	x0, x19
	bl	_DPU_REG_WRITE
	ldr	x8, [x20]
	ldp	w9, w8, [x8, #24]
	lsl	w8, w8, #9
	and	w2, w8, #0x1fff0000
	bfxil	w2, w9, #7, #13
	add	w1, w21, #12
	mov	x0, x19
	bl	_DPU_REG_WRITE
	ldr	x8, [x20]
	ldr	w8, [x8, #32]
	ubfx	w2, w8, #7, #13
	add	w1, w21, #16
	mov	x0, x19
	bl	_DPU_REG_WRITE
	ldr	x8, [x20, #8]
	ldp	w9, w8, [x8]
	lsl	w9, w9, w22
	orr	w2, w9, w8
	add	w1, w21, #20
	mov	x0, x19
	bl	_DPU_REG_WRITE
	ldr	x8, [x20, #8]
	ldp	w9, w8, [x8, #8]
	lsl	w9, w9, w22
	orr	w2, w9, w8
	add	w1, w21, #24
	mov	x0, x19
	bl	_DPU_REG_WRITE
	ldr	x8, [x20, #8]
	ldp	w9, w8, [x8, #16]
	lsl	w9, w9, w22
	orr	w2, w9, w8
	add	w1, w21, #28
	mov	x0, x19
	bl	_DPU_REG_WRITE
	ldr	x8, [x20, #16]
	ldp	w9, w8, [x8]
	lsl	w9, w9, w22
	orr	w2, w9, w8
	add	w1, w21, #32
	mov	x0, x19
	bl	_DPU_REG_WRITE
	ldr	x8, [x20, #16]
	ldp	w9, w8, [x8, #8]
	lsl	w9, w9, w22
	orr	w2, w9, w8
	add	w1, w21, #36
	mov	x0, x19
	bl	_DPU_REG_WRITE
	ldr	x8, [x20, #16]
	ldp	w9, w8, [x8, #16]
	lsl	w9, w9, w22
	orr	w2, w9, w8
	add	w1, w21, #40
	mov	x0, x19
	bl	_DPU_REG_WRITE
	add	w1, w21, #44
	ldr	x8, [x20, #24]
	ldr	w2, [x8]
	mov	x0, x19
	bl	_DPU_REG_WRITE
	add	w1, w21, #48
	ldr	x8, [x20, #24]
	ldr	w2, [x8, #4]
	mov	x0, x19
	bl	_DPU_REG_WRITE
	add	w1, w21, #52
	ldr	x8, [x20, #24]
	ldr	w2, [x8, #8]
	mov	x0, x19
	bl	_DPU_REG_WRITE
	add	w1, w21, #56
	ldr	x8, [x20, #32]
	ldr	w2, [x8]
	mov	x0, x19
	bl	_DPU_REG_WRITE
	add	w1, w21, #60
	ldr	x8, [x20, #32]
	ldr	w2, [x8, #4]
	mov	x0, x19
	bl	_DPU_REG_WRITE
	add	w1, w21, #64
	ldr	x8, [x20, #32]
	ldr	w2, [x8, #8]
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_DPU_REG_WRITE
	.cfi_endproc
                                        ; -- End function
.subsections_via_symbols
