	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vega12_apply_clocks_adjust_rules
_vega12_apply_clocks_adjust_rules:      ## @vega12_apply_clocks_adjust_rules
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	8(%rdi), %rax
	movq	16(%rdi), %rbx
	cmpl	$2, (%rax)
	jl	LBB0_3
## %bb.1:
	cmpl	$0, 24(%rax)
	je	LBB0_2
LBB0_3:
	xorl	%r13d, %r13d
LBB0_4:
	movl	4(%rax), %r12d
	movq	168(%rbx), %rax
	movl	(%rax), %ecx
	movl	%ecx, 176(%rbx)
	movslq	160(%rbx), %rdx
	movl	-4(%rax,%rdx,4), %eax
	movl	%eax, 180(%rbx)
	movl	%ecx, 184(%rbx)
	movl	%eax, 188(%rbx)
	movq	_PHM_PlatformCaps_UMDPState@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_PP_CAP
	testq	%rax, %rax
	je	LBB0_11
## %bb.5:
	movq	_VEGA12_UMD_PSTATE_GFXCLK_LEVEL@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movslq	160(%rbx), %rax
	cmpq	%rax, %rcx
	jae	LBB0_7
## %bb.6:
	movq	168(%rbx), %rdx
	movl	(%rdx,%rcx,4), %ecx
	movl	%ecx, 176(%rbx)
	movl	%ecx, 180(%rbx)
LBB0_7:
	movq	(%r14), %rcx
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_9
## %bb.8:
	movq	168(%rbx), %rdx
	movl	(%rdx), %edx
	movl	%edx, 176(%rbx)
	movl	%edx, 180(%rbx)
LBB0_9:
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_11
## %bb.10:
	movq	168(%rbx), %rcx
	movl	-4(%rcx,%rax,4), %eax
	movl	%eax, 176(%rbx)
	movl	%eax, 180(%rbx)
LBB0_11:
	movq	136(%rbx), %rax
	movl	(%rax), %ecx
	movl	%ecx, 144(%rbx)
	movslq	128(%rbx), %rdx
	movl	-4(%rax,%rdx,4), %eax
	movl	%eax, 148(%rbx)
	movl	%ecx, 152(%rbx)
	movl	%eax, 156(%rbx)
	movl	(%r15), %edi
	callq	_PP_CAP
	testq	%rax, %rax
	je	LBB0_18
## %bb.12:
	movq	_VEGA12_UMD_PSTATE_MCLK_LEVEL@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movslq	128(%rbx), %rax
	cmpq	%rax, %rcx
	jae	LBB0_14
## %bb.13:
	movq	136(%rbx), %rdx
	movl	(%rdx,%rcx,4), %ecx
	movl	%ecx, 144(%rbx)
	movl	%ecx, 148(%rbx)
LBB0_14:
	movq	(%r14), %rcx
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_16
## %bb.15:
	movq	136(%rbx), %rdx
	movl	(%rdx), %edx
	movl	%edx, 144(%rbx)
	movl	%edx, 148(%rbx)
LBB0_16:
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_18
## %bb.17:
	movq	136(%rbx), %rcx
	movl	-4(%rcx,%rax,4), %eax
	movl	%eax, 144(%rbx)
	movl	%eax, 148(%rbx)
LBB0_18:
	movq	8(%r14), %r8
	movslq	8(%r8), %rax
	imulq	$1374389535, %rax, %rcx         ## imm = 0x51EB851F
	movq	%rcx, %rax
	shrq	$63, %rax
	sarq	$37, %rcx
	addl	%eax, %ecx
	cmpl	%ecx, 152(%rbx)
	jge	LBB0_20
## %bb.19:
	movl	%ecx, 152(%rbx)
LBB0_20:
	testb	%r13b, %r13b
	je	LBB0_27
## %bb.21:
	movq	136(%rbx), %r9
	movslq	128(%rbx), %rax
	movl	-4(%r9,%rax,4), %eax
	movl	%eax, 152(%rbx)
	movl	192(%rbx), %esi
	cmpl	$2, %esi
	jl	LBB0_27
## %bb.22:
	decl	%esi
	movq	200(%rbx), %rdi
	xorl	%eax, %eax
	jmp	LBB0_23
	.p2align	4, 0x90
LBB0_26:                                ##   in Loop: Header=BB0_23 Depth=1
	incq	%rax
	cmpq	%rax, %rsi
	je	LBB0_27
LBB0_23:                                ## =>This Inner Loop Header: Depth=1
	cmpl	%r12d, (%rdi,%rax,4)
	jg	LBB0_26
## %bb.24:                              ##   in Loop: Header=BB0_23 Depth=1
	movl	(%r9,%rax,4), %edx
	cmpl	%ecx, %edx
	jl	LBB0_26
## %bb.25:
	movl	%edx, 152(%rbx)
LBB0_27:
	cmpq	$0, 16(%r8)
	je	LBB0_29
## %bb.28:
	movq	136(%rbx), %rax
	movslq	128(%rbx), %rcx
	movl	-4(%rax,%rcx,4), %eax
	movl	%eax, 152(%rbx)
LBB0_29:
	movq	104(%rbx), %rax
	movl	(%rax), %ecx
	movl	%ecx, 112(%rbx)
	movslq	96(%rbx), %rdx
	movl	-4(%rax,%rdx,4), %eax
	movl	%eax, 116(%rbx)
	movl	%ecx, 120(%rbx)
	movl	%eax, 124(%rbx)
	movl	(%r15), %edi
	callq	_PP_CAP
	testq	%rax, %rax
	je	LBB0_34
## %bb.30:
	movq	_VEGA12_UMD_PSTATE_UVDCLK_LEVEL@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movslq	96(%rbx), %rax
	cmpq	%rax, %rcx
	jae	LBB0_32
## %bb.31:
	movq	104(%rbx), %rdx
	movl	(%rdx,%rcx,4), %ecx
	movl	%ecx, 112(%rbx)
	movl	%ecx, 116(%rbx)
LBB0_32:
	movq	(%r14), %rcx
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_34
## %bb.33:
	movq	104(%rbx), %rcx
	movl	-4(%rcx,%rax,4), %eax
	movl	%eax, 112(%rbx)
	movl	%eax, 116(%rbx)
LBB0_34:
	movq	72(%rbx), %rax
	movl	(%rax), %ecx
	movl	%ecx, 80(%rbx)
	movslq	64(%rbx), %rdx
	movl	-4(%rax,%rdx,4), %eax
	movl	%eax, 84(%rbx)
	movl	%ecx, 88(%rbx)
	movl	%eax, 92(%rbx)
	movl	(%r15), %edi
	callq	_PP_CAP
	testq	%rax, %rax
	je	LBB0_39
## %bb.35:
	movq	_VEGA12_UMD_PSTATE_UVDCLK_LEVEL@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movslq	64(%rbx), %rax
	cmpq	%rax, %rcx
	jae	LBB0_37
## %bb.36:
	movq	72(%rbx), %rdx
	movl	(%rdx,%rcx,4), %ecx
	movl	%ecx, 80(%rbx)
	movl	%ecx, 84(%rbx)
LBB0_37:
	movq	(%r14), %rcx
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_39
## %bb.38:
	movq	72(%rbx), %rcx
	movl	-4(%rcx,%rax,4), %eax
	movl	%eax, 80(%rbx)
	movl	%eax, 84(%rbx)
LBB0_39:
	movq	40(%rbx), %rax
	movl	(%rax), %ecx
	movl	%ecx, 48(%rbx)
	movslq	32(%rbx), %rdx
	movl	-4(%rax,%rdx,4), %eax
	movl	%eax, 52(%rbx)
	movl	%ecx, 56(%rbx)
	movl	%eax, 60(%rbx)
	movl	(%r15), %edi
	callq	_PP_CAP
	testq	%rax, %rax
	je	LBB0_44
## %bb.40:
	movq	_VEGA12_UMD_PSTATE_SOCCLK_LEVEL@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movslq	32(%rbx), %rax
	cmpq	%rax, %rcx
	jae	LBB0_42
## %bb.41:
	movq	40(%rbx), %rdx
	movl	(%rdx,%rcx,4), %ecx
	movl	%ecx, 48(%rbx)
	movl	%ecx, 52(%rbx)
LBB0_42:
	movq	(%r14), %rcx
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_44
## %bb.43:
	movq	40(%rbx), %rcx
	movl	-4(%rcx,%rax,4), %eax
	movl	%eax, 48(%rbx)
	movl	%eax, 52(%rbx)
LBB0_44:
	movq	8(%rbx), %rax
	movl	(%rax), %ecx
	movl	%ecx, 16(%rbx)
	movslq	(%rbx), %rdx
	movl	-4(%rax,%rdx,4), %eax
	movl	%eax, 20(%rbx)
	movl	%ecx, 24(%rbx)
	movl	%eax, 28(%rbx)
	movl	(%r15), %edi
	callq	_PP_CAP
	testq	%rax, %rax
	je	LBB0_49
## %bb.45:
	movq	_VEGA12_UMD_PSTATE_VCEMCLK_LEVEL@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movslq	(%rbx), %rax
	cmpq	%rax, %rcx
	jae	LBB0_47
## %bb.46:
	movq	8(%rbx), %rdx
	movl	(%rdx,%rcx,4), %ecx
	movl	%ecx, 16(%rbx)
	movl	%ecx, 20(%rbx)
LBB0_47:
	movq	(%r14), %rcx
	movq	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_49
## %bb.48:
	movq	8(%rbx), %rcx
	movl	-4(%rcx,%rax,4), %eax
	movl	%eax, 16(%rbx)
	movl	%eax, 20(%rbx)
LBB0_49:
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	movb	$1, %r13b
	jmp	LBB0_4
	.cfi_endproc
                                        ## -- End function
	.comm	_PHM_PlatformCaps_UMDPState,4,2 ## @PHM_PlatformCaps_UMDPState
	.comm	_VEGA12_UMD_PSTATE_GFXCLK_LEVEL,8,3 ## @VEGA12_UMD_PSTATE_GFXCLK_LEVEL
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK,8,3 ## @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,8,3 ## @AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
	.comm	_VEGA12_UMD_PSTATE_MCLK_LEVEL,8,3 ## @VEGA12_UMD_PSTATE_MCLK_LEVEL
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK,8,3 ## @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
	.comm	_VEGA12_UMD_PSTATE_UVDCLK_LEVEL,8,3 ## @VEGA12_UMD_PSTATE_UVDCLK_LEVEL
	.comm	_VEGA12_UMD_PSTATE_SOCCLK_LEVEL,8,3 ## @VEGA12_UMD_PSTATE_SOCCLK_LEVEL
	.comm	_VEGA12_UMD_PSTATE_VCEMCLK_LEVEL,8,3 ## @VEGA12_UMD_PSTATE_VCEMCLK_LEVEL
	.no_dead_strip	_vega12_apply_clocks_adjust_rules
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vega12_apply_clocks_adjust_rules
_vega12_apply_clocks_adjust_rules:      ; @vega12_apply_clocks_adjust_rules
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldp	x8, x20, [x0, #8]
	ldr	w9, [x8]
	cmp	w9, #2
	b.lt	LBB0_2
; %bb.1:
	ldr	w9, [x8, #24]
	cbz	w9, LBB0_49
LBB0_2:
	mov	w24, #0
LBB0_3:
	ldr	w23, [x8, #4]
	ldr	x8, [x20, #168]
	ldr	w9, [x8]
	ldrsw	x10, [x20, #160]
	add	x8, x8, x10, lsl #2
	ldur	w8, [x8, #-4]
	stp	w9, w8, [x20, #176]
	stp	w9, w8, [x20, #184]
Lloh0:
	adrp	x22, _PHM_PlatformCaps_UMDPState@GOTPAGE
Lloh1:
	ldr	x22, [x22, _PHM_PlatformCaps_UMDPState@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_PP_CAP
Lloh2:
	adrp	x21, _AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPAGE
Lloh3:
	ldr	x21, [x21, _AMD_DPM_FORCED_LEVEL_PROFILE_PEAK@GOTPAGEOFF]
	cbz	x0, LBB0_10
; %bb.4:
Lloh4:
	adrp	x8, _VEGA12_UMD_PSTATE_GFXCLK_LEVEL@GOTPAGE
Lloh5:
	ldr	x8, [x8, _VEGA12_UMD_PSTATE_GFXCLK_LEVEL@GOTPAGEOFF]
Lloh6:
	ldr	x9, [x8]
	ldrsw	x8, [x20, #160]
	cmp	x9, x8
	b.hs	LBB0_6
; %bb.5:
	ldr	x10, [x20, #168]
	ldr	w9, [x10, x9, lsl #2]
	stp	w9, w9, [x20, #176]
LBB0_6:
	ldr	x9, [x19]
Lloh7:
	adrp	x10, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK@GOTPAGE
Lloh8:
	ldr	x10, [x10, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK@GOTPAGEOFF]
Lloh9:
	ldr	x10, [x10]
	cmp	x9, x10
	b.ne	LBB0_8
; %bb.7:
	ldr	x10, [x20, #168]
	ldr	w10, [x10]
	stp	w10, w10, [x20, #176]
LBB0_8:
	ldr	x10, [x21]
	cmp	x9, x10
	b.ne	LBB0_10
; %bb.9:
	ldr	x9, [x20, #168]
	add	x8, x9, x8, lsl #2
	ldur	w8, [x8, #-4]
	stp	w8, w8, [x20, #176]
LBB0_10:
	ldr	x8, [x20, #136]
	ldr	w9, [x8]
	ldrsw	x10, [x20, #128]
	add	x8, x8, x10, lsl #2
	ldur	w8, [x8, #-4]
	stp	w9, w8, [x20, #144]
	stp	w9, w8, [x20, #152]
	ldr	w0, [x22]
	bl	_PP_CAP
	cbz	x0, LBB0_17
; %bb.11:
Lloh10:
	adrp	x8, _VEGA12_UMD_PSTATE_MCLK_LEVEL@GOTPAGE
Lloh11:
	ldr	x8, [x8, _VEGA12_UMD_PSTATE_MCLK_LEVEL@GOTPAGEOFF]
Lloh12:
	ldr	x9, [x8]
	ldrsw	x8, [x20, #128]
	cmp	x9, x8
	b.hs	LBB0_13
; %bb.12:
	ldr	x10, [x20, #136]
	ldr	w9, [x10, x9, lsl #2]
	stp	w9, w9, [x20, #144]
LBB0_13:
	ldr	x9, [x19]
Lloh13:
	adrp	x10, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK@GOTPAGE
Lloh14:
	ldr	x10, [x10, _AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK@GOTPAGEOFF]
Lloh15:
	ldr	x10, [x10]
	cmp	x9, x10
	b.ne	LBB0_15
; %bb.14:
	ldr	x10, [x20, #136]
	ldr	w10, [x10]
	stp	w10, w10, [x20, #144]
LBB0_15:
	ldr	x10, [x21]
	cmp	x9, x10
	b.ne	LBB0_17
; %bb.16:
	ldr	x9, [x20, #136]
	add	x8, x9, x8, lsl #2
	ldur	w8, [x8, #-4]
	stp	w8, w8, [x20, #144]
LBB0_17:
	ldr	w10, [x20, #152]
	ldr	x8, [x19, #8]
	ldrsw	x9, [x8, #8]
	mov	w11, #34079
	movk	w11, #20971, lsl #16
	mul	x9, x9, x11
	lsr	x11, x9, #63
	asr	x9, x9, #37
	add	w9, w9, w11
	cmp	w10, w9
	b.ge	LBB0_19
; %bb.18:
	str	w9, [x20, #152]
LBB0_19:
	cbz	w24, LBB0_26
; %bb.20:
	ldr	x10, [x20, #136]
	ldrsw	x11, [x20, #128]
	add	x11, x10, x11, lsl #2
	ldur	w11, [x11, #-4]
	str	w11, [x20, #152]
	ldr	w11, [x20, #192]
	cmp	w11, #2
	b.lt	LBB0_26
; %bb.21:
	sub	w11, w11, #1
	ldr	x12, [x20, #200]
	b	LBB0_23
LBB0_22:                                ;   in Loop: Header=BB0_23 Depth=1
	add	x12, x12, #4
	add	x10, x10, #4
	subs	x11, x11, #1
	b.eq	LBB0_26
LBB0_23:                                ; =>This Inner Loop Header: Depth=1
	ldr	w13, [x12]
	cmp	w13, w23
	b.gt	LBB0_22
; %bb.24:                               ;   in Loop: Header=BB0_23 Depth=1
	ldr	w13, [x10]
	cmp	w13, w9
	b.lt	LBB0_22
; %bb.25:
	str	w13, [x20, #152]
LBB0_26:
	ldr	x8, [x8, #16]
	cbz	x8, LBB0_28
; %bb.27:
	ldr	x8, [x20, #136]
	ldrsw	x9, [x20, #128]
	add	x8, x8, x9, lsl #2
	ldur	w8, [x8, #-4]
	str	w8, [x20, #152]
LBB0_28:
	ldr	x8, [x20, #104]
	ldr	w9, [x8]
	ldrsw	x10, [x20, #96]
	add	x8, x8, x10, lsl #2
	ldur	w8, [x8, #-4]
	stp	w9, w8, [x20, #112]
	stp	w9, w8, [x20, #120]
	ldr	w0, [x22]
	bl	_PP_CAP
Lloh16:
	adrp	x23, _VEGA12_UMD_PSTATE_UVDCLK_LEVEL@GOTPAGE
Lloh17:
	ldr	x23, [x23, _VEGA12_UMD_PSTATE_UVDCLK_LEVEL@GOTPAGEOFF]
	cbz	x0, LBB0_33
; %bb.29:
	ldr	x9, [x23]
	ldrsw	x8, [x20, #96]
	cmp	x9, x8
	b.hs	LBB0_31
; %bb.30:
	ldr	x10, [x20, #104]
	ldr	w9, [x10, x9, lsl #2]
	stp	w9, w9, [x20, #112]
LBB0_31:
	ldr	x9, [x19]
	ldr	x10, [x21]
	cmp	x9, x10
	b.ne	LBB0_33
; %bb.32:
	ldr	x9, [x20, #104]
	add	x8, x9, x8, lsl #2
	ldur	w8, [x8, #-4]
	stp	w8, w8, [x20, #112]
LBB0_33:
	ldr	x8, [x20, #72]
	ldr	w9, [x8]
	ldrsw	x10, [x20, #64]
	add	x8, x8, x10, lsl #2
	ldur	w8, [x8, #-4]
	stp	w9, w8, [x20, #80]
	stp	w9, w8, [x20, #88]
	ldr	w0, [x22]
	bl	_PP_CAP
	cbz	x0, LBB0_38
; %bb.34:
	ldr	x9, [x23]
	ldrsw	x8, [x20, #64]
	cmp	x9, x8
	b.hs	LBB0_36
; %bb.35:
	ldr	x10, [x20, #72]
	ldr	w9, [x10, x9, lsl #2]
	stp	w9, w9, [x20, #80]
LBB0_36:
	ldr	x9, [x19]
	ldr	x10, [x21]
	cmp	x9, x10
	b.ne	LBB0_38
; %bb.37:
	ldr	x9, [x20, #72]
	add	x8, x9, x8, lsl #2
	ldur	w8, [x8, #-4]
	stp	w8, w8, [x20, #80]
LBB0_38:
	ldr	x8, [x20, #40]
	ldr	w9, [x8]
	ldrsw	x10, [x20, #32]
	add	x8, x8, x10, lsl #2
	ldur	w8, [x8, #-4]
	stp	w9, w8, [x20, #48]
	stp	w9, w8, [x20, #56]
	ldr	w0, [x22]
	bl	_PP_CAP
	cbz	x0, LBB0_43
; %bb.39:
Lloh18:
	adrp	x8, _VEGA12_UMD_PSTATE_SOCCLK_LEVEL@GOTPAGE
Lloh19:
	ldr	x8, [x8, _VEGA12_UMD_PSTATE_SOCCLK_LEVEL@GOTPAGEOFF]
Lloh20:
	ldr	x9, [x8]
	ldrsw	x8, [x20, #32]
	cmp	x9, x8
	b.hs	LBB0_41
; %bb.40:
	ldr	x10, [x20, #40]
	ldr	w9, [x10, x9, lsl #2]
	stp	w9, w9, [x20, #48]
LBB0_41:
	ldr	x9, [x19]
	ldr	x10, [x21]
	cmp	x9, x10
	b.ne	LBB0_43
; %bb.42:
	ldr	x9, [x20, #40]
	add	x8, x9, x8, lsl #2
	ldur	w8, [x8, #-4]
	stp	w8, w8, [x20, #48]
LBB0_43:
	ldr	x8, [x20, #8]
	ldr	w9, [x8]
	ldrsw	x10, [x20]
	add	x8, x8, x10, lsl #2
	ldur	w8, [x8, #-4]
	stp	w9, w8, [x20, #16]
	stp	w9, w8, [x20, #24]
	ldr	w0, [x22]
	bl	_PP_CAP
	cbz	x0, LBB0_48
; %bb.44:
Lloh21:
	adrp	x8, _VEGA12_UMD_PSTATE_VCEMCLK_LEVEL@GOTPAGE
Lloh22:
	ldr	x8, [x8, _VEGA12_UMD_PSTATE_VCEMCLK_LEVEL@GOTPAGEOFF]
Lloh23:
	ldr	x9, [x8]
	ldrsw	x8, [x20]
	cmp	x9, x8
	b.hs	LBB0_46
; %bb.45:
	ldr	x10, [x20, #8]
	ldr	w9, [x10, x9, lsl #2]
	stp	w9, w9, [x20, #16]
LBB0_46:
	ldr	x9, [x19]
	ldr	x10, [x21]
	cmp	x9, x10
	b.ne	LBB0_48
; %bb.47:
	ldr	x9, [x20, #8]
	add	x8, x9, x8, lsl #2
	ldur	w8, [x8, #-4]
	stp	w8, w8, [x20, #16]
LBB0_48:
	mov	w0, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_49:
	mov	w24, #1
	b	LBB0_3
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.cfi_endproc
                                        ; -- End function
	.comm	_PHM_PlatformCaps_UMDPState,4,2 ; @PHM_PlatformCaps_UMDPState
	.comm	_VEGA12_UMD_PSTATE_GFXCLK_LEVEL,8,3 ; @VEGA12_UMD_PSTATE_GFXCLK_LEVEL
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK,8,3 ; @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,8,3 ; @AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
	.comm	_VEGA12_UMD_PSTATE_MCLK_LEVEL,8,3 ; @VEGA12_UMD_PSTATE_MCLK_LEVEL
	.comm	_AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK,8,3 ; @AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
	.comm	_VEGA12_UMD_PSTATE_UVDCLK_LEVEL,8,3 ; @VEGA12_UMD_PSTATE_UVDCLK_LEVEL
	.comm	_VEGA12_UMD_PSTATE_SOCCLK_LEVEL,8,3 ; @VEGA12_UMD_PSTATE_SOCCLK_LEVEL
	.comm	_VEGA12_UMD_PSTATE_VCEMCLK_LEVEL,8,3 ; @VEGA12_UMD_PSTATE_VCEMCLK_LEVEL
	.no_dead_strip	_vega12_apply_clocks_adjust_rules
.subsections_via_symbols
