	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function avivo_crtc_do_set_base
_avivo_crtc_do_set_base:                ## @avivo_crtc_do_set_base
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$72, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%r8d, %ebx
	movl	%ecx, -88(%rbp)                 ## 4-byte Spill
	movl	%edx, %r15d
	movq	%rsi, %r14
	movq	%rdi, %r13
	callq	_to_radeon_crtc
	movq	%rax, %r12
	movq	16(%r13), %rax
	movq	(%rax), %rcx
	movq	_R600_D1GRPH_SWAP_ENDIAN_NONE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, -104(%rbp)                ## 8-byte Spill
	movl	%ebx, -80(%rbp)                 ## 4-byte Spill
	testl	%ebx, %ebx
	jne	LBB0_3
## %bb.1:
	movq	(%r13), %rax
	movq	(%rax), %r14
	testq	%r14, %r14
	je	LBB0_2
LBB0_3:
	movl	%edx, -76(%rbp)                 ## 4-byte Spill
	movl	%r15d, -84(%rbp)                ## 4-byte Spill
	movq	%rcx, -56(%rbp)                 ## 8-byte Spill
	movq	16(%r14), %rax
	movq	(%rax), %rdi
	callq	_gem_to_radeon_bo
	movq	%rax, %r15
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	_radeon_bo_reserve
	movl	%eax, %ebx
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	callq	_unlikely
	testq	%rax, %rax
	jne	LBB0_49
## %bb.4:
	cmpl	$0, -80(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_8
## %bb.5:
	movq	%r15, %rdi
	callq	_radeon_bo_gpu_offset
	movq	%rax, -72(%rbp)
LBB0_6:
	xorl	%ebx, %ebx
	leaq	-92(%rbp), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_radeon_bo_get_tiling_flags
	movq	%r15, %rdi
	callq	_radeon_bo_unreserve
	movq	24(%r14), %rax
	movl	(%rax), %edi
	leal	-128(%rdi), %eax
	cmpl	$10, %eax
	ja	LBB0_20
## %bb.7:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_15:
	movq	_AVIVO_D1GRPH_CONTROL_DEPTH_32BPP@GOTPCREL(%rip), %rax
	movq	_AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888@GOTPCREL(%rip), %rcx
	jmp	LBB0_11
LBB0_2:
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	jmp	LBB0_48
LBB0_8:
	movq	_RADEON_GEM_DOMAIN_VRAM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-72(%rbp), %rdx
	movq	%r15, %rdi
	callq	_radeon_bo_pin
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	callq	_unlikely
	testq	%rax, %rax
	je	LBB0_6
## %bb.9:
	movq	%r15, %rdi
	callq	_radeon_bo_unreserve
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
	jmp	LBB0_49
LBB0_12:
	movq	_AVIVO_D1GRPH_CONTROL_DEPTH_16BPP@GOTPCREL(%rip), %rax
	movq	_AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444@GOTPCREL(%rip), %rcx
	jmp	LBB0_11
LBB0_21:
	movq	_AVIVO_D1GRPH_CONTROL_DEPTH_32BPP@GOTPCREL(%rip), %rax
	movq	_AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movl	$0, -44(%rbp)                   ## 4-byte Folded Spill
	jmp	LBB0_22
LBB0_16:
	movq	_AVIVO_D1GRPH_CONTROL_DEPTH_32BPP@GOTPCREL(%rip), %rax
	movq	_AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	-56(%rbp), %r15                 ## 8-byte Reload
	movq	(%r15), %rax
	movq	_CHIP_R600@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_17
## %bb.18:
	movq	_AVIVO_D1GRPH_SWAP_RB@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	jmp	LBB0_19
LBB0_20:
	leaq	-112(%rbp), %rsi
                                        ## kill: def $edi killed $edi killed $rdi
	callq	_drm_get_format_name
	leaq	L_.str.1(%rip), %rdi
	movl	%eax, %esi
	callq	_DRM_ERROR
	movq	_EINVAL@GOTPCREL(%rip), %rax
	subl	(%rax), %ebx
	jmp	LBB0_49
LBB0_13:
	movq	_AVIVO_D1GRPH_CONTROL_DEPTH_16BPP@GOTPCREL(%rip), %rax
	movq	_AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555@GOTPCREL(%rip), %rcx
	jmp	LBB0_11
LBB0_14:
	movq	_AVIVO_D1GRPH_CONTROL_DEPTH_16BPP@GOTPCREL(%rip), %rax
	movq	_AVIVO_D1GRPH_CONTROL_16BPP_RGB565@GOTPCREL(%rip), %rcx
	jmp	LBB0_11
LBB0_10:
	movq	_AVIVO_D1GRPH_CONTROL_DEPTH_8BPP@GOTPCREL(%rip), %rax
	movq	_AVIVO_D1GRPH_CONTROL_8BPP_INDEXED@GOTPCREL(%rip), %rcx
LBB0_11:
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movb	$1, %al
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
LBB0_22:
	movq	-56(%rbp), %r15                 ## 8-byte Reload
LBB0_23:
	movq	(%r15), %rdx
	movq	_CHIP_R600@GOTPCREL(%rip), %rsi
	movl	-92(%rbp), %eax
	movq	_RADEON_TILING_MACRO@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	cmpq	(%rsi), %rdx
	jge	LBB0_24
## %bb.28:
	andl	%eax, %ecx
	je	LBB0_30
## %bb.29:
	movq	_AVIVO_D1GRPH_MACRO_ADDRESS_MODE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_30:
	orl	%ecx, %ebx
	movq	_RADEON_TILING_MICRO@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_33
## %bb.31:
	movq	_AVIVO_D1GRPH_TILED@GOTPCREL(%rip), %rax
	jmp	LBB0_32
LBB0_24:
	testl	%eax, %ecx
	je	LBB0_26
## %bb.25:
	movq	_R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1@GOTPCREL(%rip), %rax
	jmp	LBB0_32
LBB0_26:
	movq	_RADEON_TILING_MICRO@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_33
## %bb.27:
	movq	_R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1@GOTPCREL(%rip), %rax
LBB0_32:
	orl	(%rax), %ebx
LBB0_33:
	cmpq	$0, (%r12)
	jne	LBB0_34
## %bb.35:
	movq	_AVIVO_D1VGA_CONTROL@GOTPCREL(%rip), %rax
	jmp	LBB0_36
LBB0_34:
	movq	_AVIVO_D2VGA_CONTROL@GOTPCREL(%rip), %rax
LBB0_36:
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_AVIVO_D1GRPH_FLIP_CONTROL@GOTPCREL(%rip), %rax
	movq	8(%r12), %rdi
	addq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%r15), %rax
	movq	_CHIP_RV770@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_38
## %bb.37:
	cmpq	$0, (%r12)
	movq	-72(%rbp), %rdi
	movq	_R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH@GOTPCREL(%rip), %rax
	cmoveq	_R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH@GOTPCREL(%rip), %rax
	movl	%ebx, -60(%rbp)                 ## 4-byte Spill
	movq	(%rax), %rbx
	movq	_R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH@GOTPCREL(%rip), %r15
	cmoveq	_R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH@GOTPCREL(%rip), %r15
	callq	_upper_32_bits
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	(%r15), %rbx
	movq	-56(%rbp), %r15                 ## 8-byte Reload
	movq	-72(%rbp), %rdi
	callq	_upper_32_bits
	movq	%rbx, %rdi
	movl	-60(%rbp), %ebx                 ## 4-byte Reload
	movl	%eax, %esi
	callq	_WREG32
LBB0_38:
	movq	_AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS@GOTPCREL(%rip), %rax
	movq	8(%r12), %rdi
	addq	(%rax), %rdi
	movl	-72(%rbp), %esi
	callq	_WREG32
	movq	_AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS@GOTPCREL(%rip), %rax
	movq	8(%r12), %rdi
	addq	(%rax), %rdi
	movl	-72(%rbp), %esi
	callq	_WREG32
	movq	_AVIVO_D1GRPH_CONTROL@GOTPCREL(%rip), %rax
	movq	8(%r12), %rdi
	addq	(%rax), %rdi
	movl	%ebx, %esi
	callq	_WREG32
	movq	(%r15), %rax
	movq	_CHIP_R600@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_40
## %bb.39:
	movq	_R600_D1GRPH_SWAP_CONTROL@GOTPCREL(%rip), %rax
	movq	8(%r12), %rdi
	addq	(%rax), %rdi
	movl	-76(%rbp), %esi                 ## 4-byte Reload
	callq	_WREG32
LBB0_40:
	movq	_AVIVO_D1GRPH_LUT_SEL@GOTPCREL(%rip), %rax
	movq	8(%r12), %rdi
	addq	(%rax), %rdi
	movq	_AVIVO_LUT_10BIT_BYPASS_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	movl	-44(%rbp), %ebx                 ## 4-byte Reload
	testb	%bl, %bl
	cmovel	%edx, %esi
	notl	%edx
	callq	_WREG32_P
	testb	%bl, %bl
	jne	LBB0_42
## %bb.41:
	leaq	L_.str.2(%rip), %rdi
	callq	_DRM_DEBUG_KMS
LBB0_42:
	movq	_AVIVO_D1GRPH_SURFACE_OFFSET_X@GOTPCREL(%rip), %rax
	movq	8(%r12), %rdi
	addq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_AVIVO_D1GRPH_SURFACE_OFFSET_Y@GOTPCREL(%rip), %rax
	movq	8(%r12), %rdi
	addq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_AVIVO_D1GRPH_X_START@GOTPCREL(%rip), %rax
	movq	8(%r12), %rdi
	addq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_AVIVO_D1GRPH_Y_START@GOTPCREL(%rip), %rax
	movq	8(%r12), %rdi
	addq	(%rax), %rdi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_AVIVO_D1GRPH_X_END@GOTPCREL(%rip), %rax
	movq	8(%r12), %rdi
	addq	(%rax), %rdi
	movl	(%r14), %esi
	callq	_WREG32
	movq	_AVIVO_D1GRPH_Y_END@GOTPCREL(%rip), %rax
	movq	8(%r12), %rdi
	addq	(%rax), %rdi
	movl	4(%r14), %esi
	callq	_WREG32
	movq	8(%r14), %rax
	movq	24(%r14), %rcx
	movl	(%rax), %eax
	movq	8(%rcx), %rcx
	cltd
	idivl	(%rcx)
	movq	_AVIVO_D1GRPH_PITCH@GOTPCREL(%rip), %rcx
	movq	8(%r12), %rdi
	addq	(%rcx), %rdi
	movl	%eax, %esi
	callq	_WREG32
	movq	_AVIVO_D1GRPH_ENABLE@GOTPCREL(%rip), %rax
	movq	8(%r12), %rdi
	addq	(%rax), %rdi
	movl	$1, %esi
	callq	_WREG32
	movq	_AVIVO_D1MODE_DESKTOP_HEIGHT@GOTPCREL(%rip), %rax
	movq	8(%r12), %rdi
	addq	(%rax), %rdi
	movl	4(%r14), %esi
	callq	_WREG32
	movq	_AVIVO_D1MODE_VIEWPORT_START@GOTPCREL(%rip), %rax
	movq	8(%r12), %rdi
	addq	(%rax), %rdi
	movl	-88(%rbp), %eax                 ## 4-byte Reload
	andl	$-2, %eax
	movl	-84(%rbp), %esi                 ## 4-byte Reload
	andl	$-4, %esi
	shll	$16, %esi
	orl	%eax, %esi
	callq	_WREG32
	movl	8(%r13), %esi
	movl	12(%r13), %eax
	incl	%eax
	andl	$-2, %eax
	movq	_AVIVO_D1MODE_VIEWPORT_SIZE@GOTPCREL(%rip), %rcx
	movq	8(%r12), %rdi
	addq	(%rcx), %rdi
	shll	$16, %esi
	orl	%eax, %esi
	callq	_WREG32
	movq	_AVIVO_D1MODE_MASTER_UPDATE_MODE@GOTPCREL(%rip), %rax
	movq	8(%r12), %rdi
	addq	(%rax), %rdi
	movl	$3, %esi
	callq	_WREG32
	movq	-104(%rbp), %rcx                ## 8-byte Reload
	testq	%rcx, %rcx
	je	LBB0_47
## %bb.43:
	cmpl	$0, -80(%rbp)                   ## 4-byte Folded Reload
	jne	LBB0_47
## %bb.44:
	movq	(%r13), %rax
	cmpq	%rcx, (%rax)
	je	LBB0_47
## %bb.45:
	movq	16(%rcx), %rax
	movq	(%rax), %rdi
	callq	_gem_to_radeon_bo
	movq	%rax, %r14
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	_radeon_bo_reserve
	movl	%eax, %ebx
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	callq	_unlikely
	testq	%rax, %rax
	jne	LBB0_49
## %bb.46:
	movq	%r14, %rdi
	callq	_radeon_bo_unpin
	movq	%r14, %rdi
	callq	_radeon_bo_unreserve
	movq	-56(%rbp), %r15                 ## 8-byte Reload
LBB0_47:
	movq	%r15, %rdi
	callq	_radeon_bandwidth_update
LBB0_48:
	xorl	%ebx, %ebx
LBB0_49:
	movl	%ebx, %eax
	addq	$72, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_17:
	movq	_R600_D1GRPH_RED_SEL_B@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_R600_D1GRPH_RED_CROSSBAR
	movl	%ebx, -60(%rbp)                 ## 4-byte Spill
	movl	%eax, %ebx
	movq	_R600_D1GRPH_BLUE_SEL_R@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_R600_D1GRPH_BLUE_CROSSBAR
	orl	%ebx, %eax
	movl	-60(%rbp), %ebx                 ## 4-byte Reload
	movl	%eax, -76(%rbp)                 ## 4-byte Spill
LBB0_19:
	movb	$1, %al
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	jmp	LBB0_23
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_15, LBB0_15-LJTI0_0
.set L0_0_set_12, LBB0_12-LJTI0_0
.set L0_0_set_21, LBB0_21-LJTI0_0
.set L0_0_set_13, LBB0_13-LJTI0_0
.set L0_0_set_16, LBB0_16-LJTI0_0
.set L0_0_set_14, LBB0_14-LJTI0_0
.set L0_0_set_10, LBB0_10-LJTI0_0
LJTI0_0:
	.long	L0_0_set_15
	.long	L0_0_set_12
	.long	L0_0_set_21
	.long	L0_0_set_13
	.long	L0_0_set_16
	.long	L0_0_set_14
	.long	L0_0_set_10
	.long	L0_0_set_15
	.long	L0_0_set_12
	.long	L0_0_set_21
	.long	L0_0_set_16
	.end_data_region
                                        ## -- End function
	.comm	_R600_D1GRPH_SWAP_ENDIAN_NONE,4,2 ## @R600_D1GRPH_SWAP_ENDIAN_NONE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"No FB bound\n"

	.comm	_RADEON_GEM_DOMAIN_VRAM,4,2     ## @RADEON_GEM_DOMAIN_VRAM
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_AVIVO_D1GRPH_CONTROL_DEPTH_8BPP,4,2 ## @AVIVO_D1GRPH_CONTROL_DEPTH_8BPP
	.comm	_AVIVO_D1GRPH_CONTROL_8BPP_INDEXED,4,2 ## @AVIVO_D1GRPH_CONTROL_8BPP_INDEXED
	.comm	_AVIVO_D1GRPH_CONTROL_DEPTH_16BPP,4,2 ## @AVIVO_D1GRPH_CONTROL_DEPTH_16BPP
	.comm	_AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444,4,2 ## @AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444
	.comm	_AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555,4,2 ## @AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555
	.comm	_AVIVO_D1GRPH_CONTROL_16BPP_RGB565,4,2 ## @AVIVO_D1GRPH_CONTROL_16BPP_RGB565
	.comm	_AVIVO_D1GRPH_CONTROL_DEPTH_32BPP,4,2 ## @AVIVO_D1GRPH_CONTROL_DEPTH_32BPP
	.comm	_AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888,4,2 ## @AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888
	.comm	_AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010,4,2 ## @AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010
	.comm	_CHIP_R600,8,3                  ## @CHIP_R600
	.comm	_R600_D1GRPH_RED_SEL_B,4,2      ## @R600_D1GRPH_RED_SEL_B
	.comm	_R600_D1GRPH_BLUE_SEL_R,4,2     ## @R600_D1GRPH_BLUE_SEL_R
	.comm	_AVIVO_D1GRPH_SWAP_RB,4,2       ## @AVIVO_D1GRPH_SWAP_RB
L_.str.1:                               ## @.str.1
	.asciz	"Unsupported screen format %s\n"

	.comm	_RADEON_TILING_MACRO,4,2        ## @RADEON_TILING_MACRO
	.comm	_R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1,4,2 ## @R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1
	.comm	_RADEON_TILING_MICRO,4,2        ## @RADEON_TILING_MICRO
	.comm	_R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1,4,2 ## @R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1
	.comm	_AVIVO_D1GRPH_MACRO_ADDRESS_MODE,4,2 ## @AVIVO_D1GRPH_MACRO_ADDRESS_MODE
	.comm	_AVIVO_D1GRPH_TILED,4,2         ## @AVIVO_D1GRPH_TILED
	.comm	_AVIVO_D1VGA_CONTROL,8,3        ## @AVIVO_D1VGA_CONTROL
	.comm	_AVIVO_D2VGA_CONTROL,8,3        ## @AVIVO_D2VGA_CONTROL
	.comm	_AVIVO_D1GRPH_FLIP_CONTROL,8,3  ## @AVIVO_D1GRPH_FLIP_CONTROL
	.comm	_CHIP_RV770,8,3                 ## @CHIP_RV770
	.comm	_R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,8,3 ## @R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
	.comm	_R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,8,3 ## @R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
	.comm	_R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,8,3 ## @R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
	.comm	_R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,8,3 ## @R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
	.comm	_AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS,8,3 ## @AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS
	.comm	_AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS,8,3 ## @AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS
	.comm	_AVIVO_D1GRPH_CONTROL,8,3       ## @AVIVO_D1GRPH_CONTROL
	.comm	_R600_D1GRPH_SWAP_CONTROL,8,3   ## @R600_D1GRPH_SWAP_CONTROL
	.comm	_AVIVO_D1GRPH_LUT_SEL,8,3       ## @AVIVO_D1GRPH_LUT_SEL
	.comm	_AVIVO_LUT_10BIT_BYPASS_EN,4,2  ## @AVIVO_LUT_10BIT_BYPASS_EN
L_.str.2:                               ## @.str.2
	.asciz	"Bypassing hardware LUT due to 10 bit fb scanout.\n"

	.comm	_AVIVO_D1GRPH_SURFACE_OFFSET_X,8,3 ## @AVIVO_D1GRPH_SURFACE_OFFSET_X
	.comm	_AVIVO_D1GRPH_SURFACE_OFFSET_Y,8,3 ## @AVIVO_D1GRPH_SURFACE_OFFSET_Y
	.comm	_AVIVO_D1GRPH_X_START,8,3       ## @AVIVO_D1GRPH_X_START
	.comm	_AVIVO_D1GRPH_Y_START,8,3       ## @AVIVO_D1GRPH_Y_START
	.comm	_AVIVO_D1GRPH_X_END,8,3         ## @AVIVO_D1GRPH_X_END
	.comm	_AVIVO_D1GRPH_Y_END,8,3         ## @AVIVO_D1GRPH_Y_END
	.comm	_AVIVO_D1GRPH_PITCH,8,3         ## @AVIVO_D1GRPH_PITCH
	.comm	_AVIVO_D1GRPH_ENABLE,8,3        ## @AVIVO_D1GRPH_ENABLE
	.comm	_AVIVO_D1MODE_DESKTOP_HEIGHT,8,3 ## @AVIVO_D1MODE_DESKTOP_HEIGHT
	.comm	_AVIVO_D1MODE_VIEWPORT_START,8,3 ## @AVIVO_D1MODE_VIEWPORT_START
	.comm	_AVIVO_D1MODE_VIEWPORT_SIZE,8,3 ## @AVIVO_D1MODE_VIEWPORT_SIZE
	.comm	_AVIVO_D1MODE_MASTER_UPDATE_MODE,8,3 ## @AVIVO_D1MODE_MASTER_UPDATE_MODE
	.comm	_R600_D1GRPH_SWAP_ENDIAN_16BIT,4,2 ## @R600_D1GRPH_SWAP_ENDIAN_16BIT
	.comm	_R600_D1GRPH_SWAP_ENDIAN_32BIT,4,2 ## @R600_D1GRPH_SWAP_ENDIAN_32BIT
	.no_dead_strip	_avivo_crtc_do_set_base
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function avivo_crtc_do_set_base
_avivo_crtc_do_set_base:                ; @avivo_crtc_do_set_base
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #144
	.cfi_def_cfa_offset 144
	stp	x28, x27, [sp, #48]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #64]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #80]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #96]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #112]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #128]            ; 16-byte Folded Spill
	add	x29, sp, #128
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x4
	mov	x26, x3
	mov	x25, x2
	mov	x24, x1
	mov	x22, x0
	bl	_to_radeon_crtc
	mov	x23, x0
	ldr	x8, [x22, #16]
	ldr	x19, [x8]
Lloh0:
	adrp	x8, _R600_D1GRPH_SWAP_ENDIAN_NONE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _R600_D1GRPH_SWAP_ENDIAN_NONE@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x8]
	mov	x20, x24
	cbnz	w21, LBB0_2
; %bb.1:
	ldr	x8, [x22]
	ldr	x20, [x8]
	cbz	x20, LBB0_8
LBB0_2:
	str	w9, [sp, #28]                   ; 4-byte Folded Spill
	ldr	x8, [x20, #16]
	ldr	x0, [x8]
	bl	_gem_to_radeon_bo
	mov	x27, x0
	mov	w1, #0
	bl	_radeon_bo_reserve
	mov	x28, x0
	cmp	w0, #0
	cset	w0, ne
	bl	_unlikely
	cbnz	x0, LBB0_43
; %bb.3:
	cbz	w21, LBB0_9
; %bb.4:
	mov	x0, x27
	bl	_radeon_bo_gpu_offset
	str	x0, [sp, #40]
LBB0_5:
	add	x1, sp, #36
	mov	x0, x27
	mov	x2, #0
	bl	_radeon_bo_get_tiling_flags
	mov	x0, x27
	bl	_radeon_bo_unreserve
	ldr	x8, [x20, #24]
	ldr	w0, [x8]
	sub	w8, w0, #128
	cmp	w8, #10
	b.hi	LBB0_15
; %bb.6:
Lloh3:
	adrp	x9, lJTI0_0@PAGE
Lloh4:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_7
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
Lloh5:
	adrp	x28, _CHIP_R600@GOTPAGE
Lloh6:
	ldr	x28, [x28, _CHIP_R600@GOTPAGEOFF]
	br	x10
LBB0_7:
Lloh7:
	adrp	x8, _AVIVO_D1GRPH_CONTROL_DEPTH_32BPP@GOTPAGE
Lloh8:
	ldr	x8, [x8, _AVIVO_D1GRPH_CONTROL_DEPTH_32BPP@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
Lloh10:
	adrp	x9, _AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888@GOTPAGE
Lloh11:
	ldr	x9, [x9, _AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888@GOTPAGEOFF]
	b	LBB0_20
LBB0_8:
Lloh12:
	adrp	x0, l_.str@PAGE
Lloh13:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_KMS
	b	LBB0_42
LBB0_9:
Lloh14:
	adrp	x8, _RADEON_GEM_DOMAIN_VRAM@GOTPAGE
Lloh15:
	ldr	x8, [x8, _RADEON_GEM_DOMAIN_VRAM@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
	add	x2, sp, #40
	mov	x0, x27
	bl	_radeon_bo_pin
	cmp	w0, #0
	cset	w0, ne
	bl	_unlikely
	cbz	x0, LBB0_5
; %bb.10:
	mov	x0, x27
	bl	_radeon_bo_unreserve
	b	LBB0_16
LBB0_11:
Lloh17:
	adrp	x8, _AVIVO_D1GRPH_CONTROL_DEPTH_16BPP@GOTPAGE
Lloh18:
	ldr	x8, [x8, _AVIVO_D1GRPH_CONTROL_DEPTH_16BPP@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
Lloh20:
	adrp	x9, _AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444@GOTPAGE
Lloh21:
	ldr	x9, [x9, _AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444@GOTPAGEOFF]
	b	LBB0_20
LBB0_12:
	mov	w27, #0
Lloh22:
	adrp	x8, _AVIVO_D1GRPH_CONTROL_DEPTH_32BPP@GOTPAGE
Lloh23:
	ldr	x8, [x8, _AVIVO_D1GRPH_CONTROL_DEPTH_32BPP@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
Lloh25:
	adrp	x9, _AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010@GOTPAGE
Lloh26:
	ldr	x9, [x9, _AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
	orr	w12, w9, w8
	b	LBB0_22
LBB0_13:
Lloh28:
	adrp	x8, _AVIVO_D1GRPH_CONTROL_DEPTH_32BPP@GOTPAGE
Lloh29:
	ldr	x8, [x8, _AVIVO_D1GRPH_CONTROL_DEPTH_32BPP@GOTPAGEOFF]
Lloh30:
	adrp	x9, _AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888@GOTPAGE
Lloh31:
	ldr	x9, [x9, _AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
Lloh33:
	ldr	w9, [x9]
	orr	w12, w9, w8
	ldr	x8, [x19]
	ldr	x9, [x28]
	cmp	x8, x9
	b.ge	LBB0_44
; %bb.14:
Lloh34:
	adrp	x8, _AVIVO_D1GRPH_SWAP_RB@GOTPAGE
Lloh35:
	ldr	x8, [x8, _AVIVO_D1GRPH_SWAP_RB@GOTPAGEOFF]
Lloh36:
	ldr	w8, [x8]
	orr	w12, w8, w12
	b	LBB0_21
LBB0_15:
	add	x1, sp, #32
	bl	_drm_get_format_name
	mov	x1, x0
Lloh37:
	adrp	x0, l_.str.1@PAGE
Lloh38:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_DRM_ERROR
LBB0_16:
Lloh39:
	adrp	x8, _EINVAL@GOTPAGE
Lloh40:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
	neg	w28, w8
	b	LBB0_43
LBB0_17:
Lloh42:
	adrp	x8, _AVIVO_D1GRPH_CONTROL_DEPTH_16BPP@GOTPAGE
Lloh43:
	ldr	x8, [x8, _AVIVO_D1GRPH_CONTROL_DEPTH_16BPP@GOTPAGEOFF]
Lloh44:
	ldr	w8, [x8]
Lloh45:
	adrp	x9, _AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555@GOTPAGE
Lloh46:
	ldr	x9, [x9, _AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555@GOTPAGEOFF]
	b	LBB0_20
LBB0_18:
Lloh47:
	adrp	x8, _AVIVO_D1GRPH_CONTROL_DEPTH_16BPP@GOTPAGE
Lloh48:
	ldr	x8, [x8, _AVIVO_D1GRPH_CONTROL_DEPTH_16BPP@GOTPAGEOFF]
Lloh49:
	ldr	w8, [x8]
Lloh50:
	adrp	x9, _AVIVO_D1GRPH_CONTROL_16BPP_RGB565@GOTPAGE
Lloh51:
	ldr	x9, [x9, _AVIVO_D1GRPH_CONTROL_16BPP_RGB565@GOTPAGEOFF]
	b	LBB0_20
LBB0_19:
Lloh52:
	adrp	x8, _AVIVO_D1GRPH_CONTROL_DEPTH_8BPP@GOTPAGE
Lloh53:
	ldr	x8, [x8, _AVIVO_D1GRPH_CONTROL_DEPTH_8BPP@GOTPAGEOFF]
Lloh54:
	ldr	w8, [x8]
Lloh55:
	adrp	x9, _AVIVO_D1GRPH_CONTROL_8BPP_INDEXED@GOTPAGE
Lloh56:
	ldr	x9, [x9, _AVIVO_D1GRPH_CONTROL_8BPP_INDEXED@GOTPAGEOFF]
LBB0_20:
	ldr	w9, [x9]
	orr	w12, w9, w8
LBB0_21:
	mov	w27, #1
LBB0_22:
	ldr	x10, [x19]
	ldr	x11, [x28]
	ldr	w8, [sp, #36]
Lloh57:
	adrp	x9, _RADEON_TILING_MACRO@GOTPAGE
Lloh58:
	ldr	x9, [x9, _RADEON_TILING_MACRO@GOTPAGEOFF]
Lloh59:
	ldr	w9, [x9]
	and	w9, w9, w8
	cmp	x10, x11
	b.ge	LBB0_25
; %bb.23:
Lloh60:
	adrp	x10, _AVIVO_D1GRPH_MACRO_ADDRESS_MODE@GOTPAGE
Lloh61:
	ldr	x10, [x10, _AVIVO_D1GRPH_MACRO_ADDRESS_MODE@GOTPAGEOFF]
Lloh62:
	ldr	w10, [x10]
	cmp	w9, #0
	csel	w9, wzr, w10, eq
	orr	w12, w9, w12
Lloh63:
	adrp	x9, _RADEON_TILING_MICRO@GOTPAGE
Lloh64:
	ldr	x9, [x9, _RADEON_TILING_MICRO@GOTPAGEOFF]
Lloh65:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_30
; %bb.24:
Lloh66:
	adrp	x8, _AVIVO_D1GRPH_TILED@GOTPAGE
Lloh67:
	ldr	x8, [x8, _AVIVO_D1GRPH_TILED@GOTPAGEOFF]
	b	LBB0_29
LBB0_25:
	cbz	w9, LBB0_27
; %bb.26:
Lloh68:
	adrp	x8, _R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1@GOTPAGE
Lloh69:
	ldr	x8, [x8, _R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1@GOTPAGEOFF]
	b	LBB0_29
LBB0_27:
Lloh70:
	adrp	x9, _RADEON_TILING_MICRO@GOTPAGE
Lloh71:
	ldr	x9, [x9, _RADEON_TILING_MICRO@GOTPAGEOFF]
Lloh72:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_30
; %bb.28:
Lloh73:
	adrp	x8, _R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1@GOTPAGE
Lloh74:
	ldr	x8, [x8, _R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1@GOTPAGEOFF]
LBB0_29:
	ldr	w8, [x8]
	orr	w12, w8, w12
LBB0_30:
	str	w12, [sp, #16]                  ; 4-byte Folded Spill
Lloh75:
	adrp	x8, _AVIVO_D1VGA_CONTROL@GOTPAGE
Lloh76:
	ldr	x8, [x8, _AVIVO_D1VGA_CONTROL@GOTPAGEOFF]
	ldr	x9, [x23]
Lloh77:
	adrp	x10, _AVIVO_D2VGA_CONTROL@GOTPAGE
Lloh78:
	ldr	x10, [x10, _AVIVO_D2VGA_CONTROL@GOTPAGEOFF]
	cmp	x9, #0
	csel	x8, x8, x10, eq
	ldr	x0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh79:
	adrp	x8, _AVIVO_D1GRPH_FLIP_CONTROL@GOTPAGE
Lloh80:
	ldr	x8, [x8, _AVIVO_D1GRPH_FLIP_CONTROL@GOTPAGEOFF]
Lloh81:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x19]
Lloh82:
	adrp	x9, _CHIP_RV770@GOTPAGE
Lloh83:
	ldr	x9, [x9, _CHIP_RV770@GOTPAGEOFF]
Lloh84:
	ldr	x9, [x9]
	cmp	x8, x9
	b.lt	LBB0_32
; %bb.31:
	ldr	x8, [x23]
Lloh85:
	adrp	x9, _R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH@GOTPAGE
Lloh86:
	ldr	x9, [x9, _R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH@GOTPAGEOFF]
	ldr	x0, [sp, #40]
Lloh87:
	adrp	x10, _R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH@GOTPAGE
Lloh88:
	ldr	x10, [x10, _R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH@GOTPAGEOFF]
	cmp	x8, #0
	csel	x8, x9, x10, eq
	ldr	x28, [x8]
Lloh89:
	adrp	x8, _R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH@GOTPAGE
Lloh90:
	ldr	x8, [x8, _R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH@GOTPAGEOFF]
Lloh91:
	adrp	x9, _R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH@GOTPAGE
Lloh92:
	ldr	x9, [x9, _R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH@GOTPAGEOFF]
	str	w21, [sp, #12]                  ; 4-byte Folded Spill
	mov	x21, x24
	mov	x24, x27
	mov	x27, x19
	mov	x19, x26
	mov	x26, x25
	csel	x25, x8, x9, eq
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x28
	bl	_WREG32
	ldr	x28, [x25]
	mov	x25, x26
	mov	x26, x19
	mov	x19, x27
	mov	x27, x24
	mov	x24, x21
	ldr	w21, [sp, #12]                  ; 4-byte Folded Reload
	ldr	x0, [sp, #40]
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x28
Lloh93:
	adrp	x28, _CHIP_R600@GOTPAGE
Lloh94:
	ldr	x28, [x28, _CHIP_R600@GOTPAGEOFF]
	bl	_WREG32
LBB0_32:
Lloh95:
	adrp	x8, _AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS@GOTPAGE
Lloh96:
	ldr	x8, [x8, _AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS@GOTPAGEOFF]
Lloh97:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	ldr	w1, [sp, #40]
	bl	_WREG32
Lloh98:
	adrp	x8, _AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS@GOTPAGE
Lloh99:
	ldr	x8, [x8, _AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS@GOTPAGEOFF]
Lloh100:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	ldr	w1, [sp, #40]
	bl	_WREG32
Lloh101:
	adrp	x8, _AVIVO_D1GRPH_CONTROL@GOTPAGE
Lloh102:
	ldr	x8, [x8, _AVIVO_D1GRPH_CONTROL@GOTPAGEOFF]
Lloh103:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	ldr	w1, [sp, #16]                   ; 4-byte Folded Reload
	bl	_WREG32
	ldr	x8, [x19]
	ldr	x9, [x28]
	cmp	x8, x9
	b.lt	LBB0_34
; %bb.33:
Lloh104:
	adrp	x8, _R600_D1GRPH_SWAP_CONTROL@GOTPAGE
Lloh105:
	ldr	x8, [x8, _R600_D1GRPH_SWAP_CONTROL@GOTPAGEOFF]
Lloh106:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	ldr	w1, [sp, #28]                   ; 4-byte Folded Reload
	bl	_WREG32
LBB0_34:
Lloh107:
	adrp	x8, _AVIVO_D1GRPH_LUT_SEL@GOTPAGE
Lloh108:
	ldr	x8, [x8, _AVIVO_D1GRPH_LUT_SEL@GOTPAGEOFF]
Lloh109:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
Lloh110:
	adrp	x8, _AVIVO_LUT_10BIT_BYPASS_EN@GOTPAGE
Lloh111:
	ldr	x8, [x8, _AVIVO_LUT_10BIT_BYPASS_EN@GOTPAGEOFF]
Lloh112:
	ldr	w8, [x8]
	cmp	w27, #0
	csel	w1, wzr, w8, ne
	mvn	w2, w8
	bl	_WREG32_P
	tbnz	w27, #0, LBB0_36
; %bb.35:
Lloh113:
	adrp	x0, l_.str.2@PAGE
Lloh114:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	_DRM_DEBUG_KMS
LBB0_36:
Lloh115:
	adrp	x8, _AVIVO_D1GRPH_SURFACE_OFFSET_X@GOTPAGE
Lloh116:
	ldr	x8, [x8, _AVIVO_D1GRPH_SURFACE_OFFSET_X@GOTPAGEOFF]
Lloh117:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
Lloh118:
	adrp	x8, _AVIVO_D1GRPH_SURFACE_OFFSET_Y@GOTPAGE
Lloh119:
	ldr	x8, [x8, _AVIVO_D1GRPH_SURFACE_OFFSET_Y@GOTPAGEOFF]
Lloh120:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
Lloh121:
	adrp	x8, _AVIVO_D1GRPH_X_START@GOTPAGE
Lloh122:
	ldr	x8, [x8, _AVIVO_D1GRPH_X_START@GOTPAGEOFF]
Lloh123:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
Lloh124:
	adrp	x8, _AVIVO_D1GRPH_Y_START@GOTPAGE
Lloh125:
	ldr	x8, [x8, _AVIVO_D1GRPH_Y_START@GOTPAGEOFF]
Lloh126:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	mov	w1, #0
	bl	_WREG32
Lloh127:
	adrp	x8, _AVIVO_D1GRPH_X_END@GOTPAGE
Lloh128:
	ldr	x8, [x8, _AVIVO_D1GRPH_X_END@GOTPAGEOFF]
Lloh129:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	ldr	w1, [x20]
	bl	_WREG32
Lloh130:
	adrp	x8, _AVIVO_D1GRPH_Y_END@GOTPAGE
Lloh131:
	ldr	x8, [x8, _AVIVO_D1GRPH_Y_END@GOTPAGEOFF]
Lloh132:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	ldr	w1, [x20, #4]
	bl	_WREG32
	ldr	x8, [x20, #8]
	ldr	w8, [x8]
	ldr	x9, [x20, #24]
	ldr	x9, [x9, #8]
	ldr	w9, [x9]
	sdiv	w1, w8, w9
Lloh133:
	adrp	x8, _AVIVO_D1GRPH_PITCH@GOTPAGE
Lloh134:
	ldr	x8, [x8, _AVIVO_D1GRPH_PITCH@GOTPAGEOFF]
Lloh135:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	bl	_WREG32
Lloh136:
	adrp	x8, _AVIVO_D1GRPH_ENABLE@GOTPAGE
Lloh137:
	ldr	x8, [x8, _AVIVO_D1GRPH_ENABLE@GOTPAGEOFF]
Lloh138:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	mov	w1, #1
	bl	_WREG32
Lloh139:
	adrp	x8, _AVIVO_D1MODE_DESKTOP_HEIGHT@GOTPAGE
Lloh140:
	ldr	x8, [x8, _AVIVO_D1MODE_DESKTOP_HEIGHT@GOTPAGEOFF]
Lloh141:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	ldr	w1, [x20, #4]
	bl	_WREG32
	and	w8, w26, #0xfffffffe
Lloh142:
	adrp	x9, _AVIVO_D1MODE_VIEWPORT_START@GOTPAGE
Lloh143:
	ldr	x9, [x9, _AVIVO_D1MODE_VIEWPORT_START@GOTPAGEOFF]
Lloh144:
	ldr	x9, [x9]
	ldr	x10, [x23, #8]
	add	x0, x10, x9
	lsl	w9, w25, #16
	and	w9, w9, #0xfffc0000
	orr	w1, w9, w8
	bl	_WREG32
	ldp	w8, w9, [x22, #8]
	add	w9, w9, #1
	and	w9, w9, #0xfffffffe
Lloh145:
	adrp	x10, _AVIVO_D1MODE_VIEWPORT_SIZE@GOTPAGE
Lloh146:
	ldr	x10, [x10, _AVIVO_D1MODE_VIEWPORT_SIZE@GOTPAGEOFF]
Lloh147:
	ldr	x10, [x10]
	ldr	x11, [x23, #8]
	add	x0, x11, x10
	orr	w1, w9, w8, lsl #16
	bl	_WREG32
Lloh148:
	adrp	x8, _AVIVO_D1MODE_MASTER_UPDATE_MODE@GOTPAGE
Lloh149:
	ldr	x8, [x8, _AVIVO_D1MODE_MASTER_UPDATE_MODE@GOTPAGEOFF]
Lloh150:
	ldr	x8, [x8]
	ldr	x9, [x23, #8]
	add	x0, x9, x8
	mov	w1, #3
	bl	_WREG32
	cbz	x24, LBB0_41
; %bb.37:
	cbnz	w21, LBB0_41
; %bb.38:
	ldr	x8, [x22]
	ldr	x8, [x8]
	cmp	x8, x24
	b.eq	LBB0_41
; %bb.39:
	ldr	x8, [x24, #16]
	ldr	x0, [x8]
	bl	_gem_to_radeon_bo
	mov	x20, x0
	mov	w1, #0
	bl	_radeon_bo_reserve
	mov	x28, x0
	cmp	w0, #0
	cset	w0, ne
	bl	_unlikely
	cbnz	x0, LBB0_43
; %bb.40:
	mov	x0, x20
	bl	_radeon_bo_unpin
	mov	x0, x20
	bl	_radeon_bo_unreserve
LBB0_41:
	mov	x0, x19
	bl	_radeon_bandwidth_update
LBB0_42:
	mov	w28, #0
LBB0_43:
	mov	x0, x28
	ldp	x29, x30, [sp, #128]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #112]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #96]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #80]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #64]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #144
	ret
LBB0_44:
Lloh151:
	adrp	x8, _R600_D1GRPH_RED_SEL_B@GOTPAGE
Lloh152:
	ldr	x8, [x8, _R600_D1GRPH_RED_SEL_B@GOTPAGEOFF]
Lloh153:
	ldr	w0, [x8]
	mov	x27, x12
	bl	_R600_D1GRPH_RED_CROSSBAR
	str	x19, [sp, #16]                  ; 8-byte Folded Spill
	mov	x19, x26
	mov	x26, x0
Lloh154:
	adrp	x8, _R600_D1GRPH_BLUE_SEL_R@GOTPAGE
Lloh155:
	ldr	x8, [x8, _R600_D1GRPH_BLUE_SEL_R@GOTPAGEOFF]
Lloh156:
	ldr	w0, [x8]
	bl	_R600_D1GRPH_BLUE_CROSSBAR
	mov	x12, x27
	orr	w8, w0, w26
	str	w8, [sp, #28]                   ; 4-byte Folded Spill
	mov	x26, x19
	ldr	x19, [sp, #16]                  ; 8-byte Folded Reload
	b	LBB0_21
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpAdd	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh32
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpAdd	Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGot	Lloh66, Lloh67
	.loh AdrpLdrGot	Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGot	Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGot	Lloh77, Lloh78
	.loh AdrpLdrGot	Lloh75, Lloh76
	.loh AdrpLdrGot	Lloh93, Lloh94
	.loh AdrpLdrGot	Lloh91, Lloh92
	.loh AdrpLdrGot	Lloh89, Lloh90
	.loh AdrpLdrGot	Lloh87, Lloh88
	.loh AdrpLdrGot	Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpAdd	Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh148, Lloh149, Lloh150
	.loh AdrpLdrGotLdr	Lloh145, Lloh146, Lloh147
	.loh AdrpLdrGotLdr	Lloh142, Lloh143, Lloh144
	.loh AdrpLdrGotLdr	Lloh139, Lloh140, Lloh141
	.loh AdrpLdrGotLdr	Lloh136, Lloh137, Lloh138
	.loh AdrpLdrGotLdr	Lloh133, Lloh134, Lloh135
	.loh AdrpLdrGotLdr	Lloh130, Lloh131, Lloh132
	.loh AdrpLdrGotLdr	Lloh127, Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.loh AdrpLdrGotLdr	Lloh154, Lloh155, Lloh156
	.loh AdrpLdrGotLdr	Lloh151, Lloh152, Lloh153
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_7-LBB0_7)>>2
	.byte	(LBB0_11-LBB0_7)>>2
	.byte	(LBB0_12-LBB0_7)>>2
	.byte	(LBB0_17-LBB0_7)>>2
	.byte	(LBB0_13-LBB0_7)>>2
	.byte	(LBB0_18-LBB0_7)>>2
	.byte	(LBB0_19-LBB0_7)>>2
	.byte	(LBB0_7-LBB0_7)>>2
	.byte	(LBB0_11-LBB0_7)>>2
	.byte	(LBB0_12-LBB0_7)>>2
	.byte	(LBB0_13-LBB0_7)>>2
                                        ; -- End function
	.comm	_R600_D1GRPH_SWAP_ENDIAN_NONE,4,2 ; @R600_D1GRPH_SWAP_ENDIAN_NONE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"No FB bound\n"

	.comm	_RADEON_GEM_DOMAIN_VRAM,4,2     ; @RADEON_GEM_DOMAIN_VRAM
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_AVIVO_D1GRPH_CONTROL_DEPTH_8BPP,4,2 ; @AVIVO_D1GRPH_CONTROL_DEPTH_8BPP
	.comm	_AVIVO_D1GRPH_CONTROL_8BPP_INDEXED,4,2 ; @AVIVO_D1GRPH_CONTROL_8BPP_INDEXED
	.comm	_AVIVO_D1GRPH_CONTROL_DEPTH_16BPP,4,2 ; @AVIVO_D1GRPH_CONTROL_DEPTH_16BPP
	.comm	_AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444,4,2 ; @AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444
	.comm	_AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555,4,2 ; @AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555
	.comm	_AVIVO_D1GRPH_CONTROL_16BPP_RGB565,4,2 ; @AVIVO_D1GRPH_CONTROL_16BPP_RGB565
	.comm	_AVIVO_D1GRPH_CONTROL_DEPTH_32BPP,4,2 ; @AVIVO_D1GRPH_CONTROL_DEPTH_32BPP
	.comm	_AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888,4,2 ; @AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888
	.comm	_AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010,4,2 ; @AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010
	.comm	_CHIP_R600,8,3                  ; @CHIP_R600
	.comm	_R600_D1GRPH_RED_SEL_B,4,2      ; @R600_D1GRPH_RED_SEL_B
	.comm	_R600_D1GRPH_BLUE_SEL_R,4,2     ; @R600_D1GRPH_BLUE_SEL_R
	.comm	_AVIVO_D1GRPH_SWAP_RB,4,2       ; @AVIVO_D1GRPH_SWAP_RB
l_.str.1:                               ; @.str.1
	.asciz	"Unsupported screen format %s\n"

	.comm	_RADEON_TILING_MACRO,4,2        ; @RADEON_TILING_MACRO
	.comm	_R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1,4,2 ; @R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1
	.comm	_RADEON_TILING_MICRO,4,2        ; @RADEON_TILING_MICRO
	.comm	_R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1,4,2 ; @R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1
	.comm	_AVIVO_D1GRPH_MACRO_ADDRESS_MODE,4,2 ; @AVIVO_D1GRPH_MACRO_ADDRESS_MODE
	.comm	_AVIVO_D1GRPH_TILED,4,2         ; @AVIVO_D1GRPH_TILED
	.comm	_AVIVO_D1VGA_CONTROL,8,3        ; @AVIVO_D1VGA_CONTROL
	.comm	_AVIVO_D2VGA_CONTROL,8,3        ; @AVIVO_D2VGA_CONTROL
	.comm	_AVIVO_D1GRPH_FLIP_CONTROL,8,3  ; @AVIVO_D1GRPH_FLIP_CONTROL
	.comm	_CHIP_RV770,8,3                 ; @CHIP_RV770
	.comm	_R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,8,3 ; @R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
	.comm	_R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,8,3 ; @R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
	.comm	_R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,8,3 ; @R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
	.comm	_R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,8,3 ; @R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
	.comm	_AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS,8,3 ; @AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS
	.comm	_AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS,8,3 ; @AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS
	.comm	_AVIVO_D1GRPH_CONTROL,8,3       ; @AVIVO_D1GRPH_CONTROL
	.comm	_R600_D1GRPH_SWAP_CONTROL,8,3   ; @R600_D1GRPH_SWAP_CONTROL
	.comm	_AVIVO_D1GRPH_LUT_SEL,8,3       ; @AVIVO_D1GRPH_LUT_SEL
	.comm	_AVIVO_LUT_10BIT_BYPASS_EN,4,2  ; @AVIVO_LUT_10BIT_BYPASS_EN
l_.str.2:                               ; @.str.2
	.asciz	"Bypassing hardware LUT due to 10 bit fb scanout.\n"

	.comm	_AVIVO_D1GRPH_SURFACE_OFFSET_X,8,3 ; @AVIVO_D1GRPH_SURFACE_OFFSET_X
	.comm	_AVIVO_D1GRPH_SURFACE_OFFSET_Y,8,3 ; @AVIVO_D1GRPH_SURFACE_OFFSET_Y
	.comm	_AVIVO_D1GRPH_X_START,8,3       ; @AVIVO_D1GRPH_X_START
	.comm	_AVIVO_D1GRPH_Y_START,8,3       ; @AVIVO_D1GRPH_Y_START
	.comm	_AVIVO_D1GRPH_X_END,8,3         ; @AVIVO_D1GRPH_X_END
	.comm	_AVIVO_D1GRPH_Y_END,8,3         ; @AVIVO_D1GRPH_Y_END
	.comm	_AVIVO_D1GRPH_PITCH,8,3         ; @AVIVO_D1GRPH_PITCH
	.comm	_AVIVO_D1GRPH_ENABLE,8,3        ; @AVIVO_D1GRPH_ENABLE
	.comm	_AVIVO_D1MODE_DESKTOP_HEIGHT,8,3 ; @AVIVO_D1MODE_DESKTOP_HEIGHT
	.comm	_AVIVO_D1MODE_VIEWPORT_START,8,3 ; @AVIVO_D1MODE_VIEWPORT_START
	.comm	_AVIVO_D1MODE_VIEWPORT_SIZE,8,3 ; @AVIVO_D1MODE_VIEWPORT_SIZE
	.comm	_AVIVO_D1MODE_MASTER_UPDATE_MODE,8,3 ; @AVIVO_D1MODE_MASTER_UPDATE_MODE
	.comm	_R600_D1GRPH_SWAP_ENDIAN_16BIT,4,2 ; @R600_D1GRPH_SWAP_ENDIAN_16BIT
	.comm	_R600_D1GRPH_SWAP_ENDIAN_32BIT,4,2 ; @R600_D1GRPH_SWAP_ENDIAN_32BIT
	.no_dead_strip	_avivo_crtc_do_set_base
.subsections_via_symbols
