	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vcn_v1_0_mc_resume_dpg_mode
_vcn_v1_0_mc_resume_dpg_mode:           ## @vcn_v1_0_mc_resume_dpg_mode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	16(%rdi), %rax
	movq	(%rax), %rdi
	addq	$4, %rdi
	callq	_AMDGPU_GPU_PAGE_ALIGN
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	24(%r14), %rax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	movq	_UVD@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r13d
	movq	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r12d
	cmpq	(%rcx), %rax
	jne	LBB0_2
## %bb.1:
	movq	32(%r14), %rax
	movq	_AMDGPU_UCODE_ID_VCN@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	(%rax,%rcx,8), %ecx
	xorl	%r15d, %r15d
	movl	%r13d, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movq	_UVD@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	32(%r14), %rax
	movq	_AMDGPU_UCODE_ID_VCN@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	4(%rax,%rcx,8), %ecx
	xorl	%esi, %esi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%rbx), %edi
	movq	_mmUVD_VCPU_CACHE_OFFSET0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	-44(%rbp), %ecx                 ## 4-byte Reload
	jmp	LBB0_3
LBB0_2:
	movq	8(%r14), %rax
	movl	(%rax), %edi
	callq	_lower_32_bits
	movl	%r13d, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movq	_UVD@GOTPCREL(%rip), %r15
	movl	(%r15), %ebx
	movq	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	8(%r14), %rax
	movl	(%rax), %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r15), %edi
	movq	_mmUVD_VCPU_CACHE_OFFSET0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_AMDGPU_UVD_FIRMWARE_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	sarl	$3, %ecx
	xorl	%esi, %esi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	-44(%rbp), %ecx                 ## 4-byte Reload
	movl	%ecx, %r15d
LBB0_3:
	movq	_UVD@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movq	_mmUVD_VCPU_CACHE_SIZE0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r13), %ebx
	movq	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	8(%r14), %rax
	movl	(%rax), %edi
	addl	%r15d, %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r13), %ebx
	movq	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	8(%r14), %rax
	movl	(%rax), %edi
	addl	%r15d, %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r13), %edi
	movq	_mmUVD_VCPU_CACHE_OFFSET1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r13), %edi
	movq	_mmUVD_VCPU_CACHE_SIZE1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_AMDGPU_VCN_STACK_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%esi, %esi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r13), %ebx
	movq	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	8(%r14), %rax
	movl	(%rax), %edi
	addl	%r15d, %edi
	movq	_AMDGPU_VCN_STACK_SIZE@GOTPCREL(%rip), %rax
	addl	(%rax), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r13), %ebx
	movq	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	8(%r14), %rax
	addl	(%rax), %r15d
	movq	_AMDGPU_VCN_STACK_SIZE@GOTPCREL(%rip), %rax
	addl	(%rax), %r15d
	movl	%r15d, %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	xorl	%esi, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r13), %edi
	movq	_mmUVD_VCPU_CACHE_OFFSET2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r13), %edi
	movq	_mmUVD_VCPU_CACHE_SIZE2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_AMDGPU_VCN_CONTEXT_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	xorl	%esi, %esi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r13), %edi
	movq	_mmUVD_UDEC_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r14), %ecx
	xorl	%esi, %esi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r13), %edi
	movq	_mmUVD_UDEC_DB_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r14), %ecx
	xorl	%esi, %esi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r13), %edi
	movq	_mmUVD_UDEC_DBW_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r14), %ecx
	xorl	%esi, %esi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r13), %edi
	movq	_mmUVD_UDEC_DBW_UV_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r14), %ecx
	xorl	%esi, %esi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r13), %edi
	movq	_mmUVD_MIF_CURR_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r14), %ecx
	xorl	%esi, %esi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r13), %edi
	movq	_mmUVD_MIF_CURR_UV_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r14), %ecx
	xorl	%esi, %esi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r13), %edi
	movq	_mmUVD_MIF_RECON1_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r14), %ecx
	xorl	%esi, %esi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r13), %edi
	movq	_mmUVD_MIF_RECON1_UV_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r14), %ecx
	xorl	%esi, %esi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r13), %edi
	movq	_mmUVD_MIF_REF_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r14), %ecx
	xorl	%esi, %esi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	_WREG32_SOC15_DPG_MODE
	movl	(%r13), %edi
	movq	_mmUVD_MIF_REF_UV_ADDR_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r14), %ecx
	xorl	%esi, %esi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WREG32_SOC15_DPG_MODE          ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_UVD,4,2                        ## @UVD
	.comm	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
	.comm	_AMDGPU_UCODE_ID_VCN,8,3        ## @AMDGPU_UCODE_ID_VCN
	.comm	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET0,4,2   ## @mmUVD_VCPU_CACHE_OFFSET0
	.comm	_AMDGPU_UVD_FIRMWARE_OFFSET,4,2 ## @AMDGPU_UVD_FIRMWARE_OFFSET
	.comm	_mmUVD_VCPU_CACHE_SIZE0,4,2     ## @mmUVD_VCPU_CACHE_SIZE0
	.comm	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET1,4,2   ## @mmUVD_VCPU_CACHE_OFFSET1
	.comm	_mmUVD_VCPU_CACHE_SIZE1,4,2     ## @mmUVD_VCPU_CACHE_SIZE1
	.comm	_AMDGPU_VCN_STACK_SIZE,4,2      ## @AMDGPU_VCN_STACK_SIZE
	.comm	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,4,2 ## @mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,4,2 ## @mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET2,4,2   ## @mmUVD_VCPU_CACHE_OFFSET2
	.comm	_mmUVD_VCPU_CACHE_SIZE2,4,2     ## @mmUVD_VCPU_CACHE_SIZE2
	.comm	_AMDGPU_VCN_CONTEXT_SIZE,4,2    ## @AMDGPU_VCN_CONTEXT_SIZE
	.comm	_mmUVD_UDEC_ADDR_CONFIG,4,2     ## @mmUVD_UDEC_ADDR_CONFIG
	.comm	_mmUVD_UDEC_DB_ADDR_CONFIG,4,2  ## @mmUVD_UDEC_DB_ADDR_CONFIG
	.comm	_mmUVD_UDEC_DBW_ADDR_CONFIG,4,2 ## @mmUVD_UDEC_DBW_ADDR_CONFIG
	.comm	_mmUVD_UDEC_DBW_UV_ADDR_CONFIG,4,2 ## @mmUVD_UDEC_DBW_UV_ADDR_CONFIG
	.comm	_mmUVD_MIF_CURR_ADDR_CONFIG,4,2 ## @mmUVD_MIF_CURR_ADDR_CONFIG
	.comm	_mmUVD_MIF_CURR_UV_ADDR_CONFIG,4,2 ## @mmUVD_MIF_CURR_UV_ADDR_CONFIG
	.comm	_mmUVD_MIF_RECON1_ADDR_CONFIG,4,2 ## @mmUVD_MIF_RECON1_ADDR_CONFIG
	.comm	_mmUVD_MIF_RECON1_UV_ADDR_CONFIG,4,2 ## @mmUVD_MIF_RECON1_UV_ADDR_CONFIG
	.comm	_mmUVD_MIF_REF_ADDR_CONFIG,4,2  ## @mmUVD_MIF_REF_ADDR_CONFIG
	.comm	_mmUVD_MIF_REF_UV_ADDR_CONFIG,4,2 ## @mmUVD_MIF_REF_UV_ADDR_CONFIG
	.no_dead_strip	_vcn_v1_0_mc_resume_dpg_mode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vcn_v1_0_mc_resume_dpg_mode
_vcn_v1_0_mc_resume_dpg_mode:           ; @vcn_v1_0_mc_resume_dpg_mode
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	x8, [x0, #16]
	ldr	x8, [x8]
	add	x0, x8, #4
	bl	_AMDGPU_GPU_PAGE_ALIGN
	mov	x20, x0
	ldr	x8, [x19, #24]
Lloh0:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh2:
	adrp	x23, _UVD@GOTPAGE
Lloh3:
	ldr	x23, [x23, _UVD@GOTPAGEOFF]
Lloh4:
	ldr	x9, [x9]
	ldr	w22, [x23]
Lloh5:
	adrp	x10, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW@GOTPAGE
Lloh6:
	ldr	x10, [x10, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh7:
	ldr	w21, [x10]
	cmp	x8, x9
	b.ne	LBB0_2
; %bb.1:
	ldr	x8, [x19, #32]
Lloh8:
	adrp	x24, _AMDGPU_UCODE_ID_VCN@GOTPAGE
Lloh9:
	ldr	x24, [x24, _AMDGPU_UCODE_ID_VCN@GOTPAGEOFF]
	ldr	x9, [x24]
	lsl	x9, x9, #3
	ldr	w3, [x8, x9]
	mov	x0, x22
	mov	w1, #0
	mov	x2, x21
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
Lloh10:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPAGE
Lloh11:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPAGEOFF]
	ldr	w0, [x23]
Lloh12:
	ldr	w2, [x8]
	ldr	x8, [x19, #32]
	ldr	x9, [x24]
	add	x8, x8, x9, lsl #3
	ldr	w3, [x8, #4]
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x23]
Lloh13:
	adrp	x8, _mmUVD_VCPU_CACHE_OFFSET0@GOTPAGE
Lloh14:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_OFFSET0@GOTPAGEOFF]
Lloh15:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	mov	w22, #0
	b	LBB0_3
LBB0_2:
	ldr	x8, [x19, #8]
	ldr	w0, [x8]
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x22
	mov	w1, #0
	mov	x2, x21
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w21, [x23]
Lloh16:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPAGE
Lloh17:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh18:
	ldr	w22, [x8]
	ldr	x8, [x19, #8]
	ldr	w0, [x8]
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x21
	mov	w1, #0
	mov	x2, x22
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
Lloh19:
	adrp	x8, _mmUVD_VCPU_CACHE_OFFSET0@GOTPAGE
Lloh20:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_OFFSET0@GOTPAGEOFF]
	ldr	w0, [x23]
Lloh21:
	ldr	w2, [x8]
Lloh22:
	adrp	x8, _AMDGPU_UVD_FIRMWARE_OFFSET@GOTPAGE
Lloh23:
	ldr	x8, [x8, _AMDGPU_UVD_FIRMWARE_OFFSET@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	asr	w3, w8, #3
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	mov	x22, x20
LBB0_3:
	ldr	w0, [x23]
Lloh25:
	adrp	x8, _mmUVD_VCPU_CACHE_SIZE0@GOTPAGE
Lloh26:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_SIZE0@GOTPAGEOFF]
Lloh27:
	ldr	w2, [x8]
	mov	w1, #0
	mov	x3, x20
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w20, [x23]
Lloh28:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW@GOTPAGE
Lloh29:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh30:
	ldr	w21, [x8]
	ldr	x8, [x19, #8]
	ldr	w8, [x8]
	add	w0, w8, w22
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w20, [x23]
Lloh31:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH@GOTPAGE
Lloh32:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh33:
	ldr	w21, [x8]
	ldr	x8, [x19, #8]
	ldr	w8, [x8]
	add	w0, w8, w22
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x23]
Lloh34:
	adrp	x8, _mmUVD_VCPU_CACHE_OFFSET1@GOTPAGE
Lloh35:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_OFFSET1@GOTPAGEOFF]
Lloh36:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x23]
Lloh37:
	adrp	x8, _mmUVD_VCPU_CACHE_SIZE1@GOTPAGE
Lloh38:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_SIZE1@GOTPAGEOFF]
Lloh39:
	ldr	w2, [x8]
Lloh40:
	adrp	x24, _AMDGPU_VCN_STACK_SIZE@GOTPAGE
Lloh41:
	ldr	x24, [x24, _AMDGPU_VCN_STACK_SIZE@GOTPAGEOFF]
	ldr	w3, [x24]
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w20, [x23]
Lloh42:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW@GOTPAGE
Lloh43:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW@GOTPAGEOFF]
Lloh44:
	ldr	w21, [x8]
	ldr	x8, [x19, #8]
	ldr	w8, [x8]
	ldr	w9, [x24]
	add	w8, w8, w22
	add	w0, w8, w9
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w20, [x23]
Lloh45:
	adrp	x8, _mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH@GOTPAGE
Lloh46:
	ldr	x8, [x8, _mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH@GOTPAGEOFF]
Lloh47:
	ldr	w21, [x8]
	ldr	x8, [x19, #8]
	ldr	w8, [x8]
	ldr	w9, [x24]
	add	w8, w8, w22
	add	w0, w8, w9
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x20
	mov	w1, #0
	mov	x2, x21
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x23]
Lloh48:
	adrp	x8, _mmUVD_VCPU_CACHE_OFFSET2@GOTPAGE
Lloh49:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_OFFSET2@GOTPAGEOFF]
Lloh50:
	ldr	w2, [x8]
	mov	w1, #0
	mov	w3, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x23]
Lloh51:
	adrp	x8, _mmUVD_VCPU_CACHE_SIZE2@GOTPAGE
Lloh52:
	ldr	x8, [x8, _mmUVD_VCPU_CACHE_SIZE2@GOTPAGEOFF]
Lloh53:
	ldr	w2, [x8]
Lloh54:
	adrp	x8, _AMDGPU_VCN_CONTEXT_SIZE@GOTPAGE
Lloh55:
	ldr	x8, [x8, _AMDGPU_VCN_CONTEXT_SIZE@GOTPAGEOFF]
Lloh56:
	ldr	w3, [x8]
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x23]
Lloh57:
	adrp	x8, _mmUVD_UDEC_ADDR_CONFIG@GOTPAGE
Lloh58:
	ldr	x8, [x8, _mmUVD_UDEC_ADDR_CONFIG@GOTPAGEOFF]
Lloh59:
	ldr	w2, [x8]
	ldr	w3, [x19]
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x23]
Lloh60:
	adrp	x8, _mmUVD_UDEC_DB_ADDR_CONFIG@GOTPAGE
Lloh61:
	ldr	x8, [x8, _mmUVD_UDEC_DB_ADDR_CONFIG@GOTPAGEOFF]
Lloh62:
	ldr	w2, [x8]
	ldr	w3, [x19]
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x23]
Lloh63:
	adrp	x8, _mmUVD_UDEC_DBW_ADDR_CONFIG@GOTPAGE
Lloh64:
	ldr	x8, [x8, _mmUVD_UDEC_DBW_ADDR_CONFIG@GOTPAGEOFF]
Lloh65:
	ldr	w2, [x8]
	ldr	w3, [x19]
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x23]
Lloh66:
	adrp	x8, _mmUVD_UDEC_DBW_UV_ADDR_CONFIG@GOTPAGE
Lloh67:
	ldr	x8, [x8, _mmUVD_UDEC_DBW_UV_ADDR_CONFIG@GOTPAGEOFF]
Lloh68:
	ldr	w2, [x8]
	ldr	w3, [x19]
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x23]
Lloh69:
	adrp	x8, _mmUVD_MIF_CURR_ADDR_CONFIG@GOTPAGE
Lloh70:
	ldr	x8, [x8, _mmUVD_MIF_CURR_ADDR_CONFIG@GOTPAGEOFF]
Lloh71:
	ldr	w2, [x8]
	ldr	w3, [x19]
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x23]
Lloh72:
	adrp	x8, _mmUVD_MIF_CURR_UV_ADDR_CONFIG@GOTPAGE
Lloh73:
	ldr	x8, [x8, _mmUVD_MIF_CURR_UV_ADDR_CONFIG@GOTPAGEOFF]
Lloh74:
	ldr	w2, [x8]
	ldr	w3, [x19]
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x23]
Lloh75:
	adrp	x8, _mmUVD_MIF_RECON1_ADDR_CONFIG@GOTPAGE
Lloh76:
	ldr	x8, [x8, _mmUVD_MIF_RECON1_ADDR_CONFIG@GOTPAGEOFF]
Lloh77:
	ldr	w2, [x8]
	ldr	w3, [x19]
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x23]
Lloh78:
	adrp	x8, _mmUVD_MIF_RECON1_UV_ADDR_CONFIG@GOTPAGE
Lloh79:
	ldr	x8, [x8, _mmUVD_MIF_RECON1_UV_ADDR_CONFIG@GOTPAGEOFF]
Lloh80:
	ldr	w2, [x8]
	ldr	w3, [x19]
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x23]
Lloh81:
	adrp	x8, _mmUVD_MIF_REF_ADDR_CONFIG@GOTPAGE
Lloh82:
	ldr	x8, [x8, _mmUVD_MIF_REF_ADDR_CONFIG@GOTPAGEOFF]
Lloh83:
	ldr	w2, [x8]
	ldr	w3, [x19]
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	bl	_WREG32_SOC15_DPG_MODE
	ldr	w0, [x23]
Lloh84:
	adrp	x8, _mmUVD_MIF_REF_UV_ADDR_CONFIG@GOTPAGE
Lloh85:
	ldr	x8, [x8, _mmUVD_MIF_REF_UV_ADDR_CONFIG@GOTPAGEOFF]
Lloh86:
	ldr	w2, [x8]
	ldr	w3, [x19]
	mov	w1, #0
	mov	w4, #-1
	mov	w5, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_WREG32_SOC15_DPG_MODE
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh4
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_UVD,4,2                        ; @UVD
	.comm	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
	.comm	_AMDGPU_UCODE_ID_VCN,8,3        ; @AMDGPU_UCODE_ID_VCN
	.comm	_mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET0,4,2   ; @mmUVD_VCPU_CACHE_OFFSET0
	.comm	_AMDGPU_UVD_FIRMWARE_OFFSET,4,2 ; @AMDGPU_UVD_FIRMWARE_OFFSET
	.comm	_mmUVD_VCPU_CACHE_SIZE0,4,2     ; @mmUVD_VCPU_CACHE_SIZE0
	.comm	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET1,4,2   ; @mmUVD_VCPU_CACHE_OFFSET1
	.comm	_mmUVD_VCPU_CACHE_SIZE1,4,2     ; @mmUVD_VCPU_CACHE_SIZE1
	.comm	_AMDGPU_VCN_STACK_SIZE,4,2      ; @AMDGPU_VCN_STACK_SIZE
	.comm	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,4,2 ; @mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW
	.comm	_mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,4,2 ; @mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH
	.comm	_mmUVD_VCPU_CACHE_OFFSET2,4,2   ; @mmUVD_VCPU_CACHE_OFFSET2
	.comm	_mmUVD_VCPU_CACHE_SIZE2,4,2     ; @mmUVD_VCPU_CACHE_SIZE2
	.comm	_AMDGPU_VCN_CONTEXT_SIZE,4,2    ; @AMDGPU_VCN_CONTEXT_SIZE
	.comm	_mmUVD_UDEC_ADDR_CONFIG,4,2     ; @mmUVD_UDEC_ADDR_CONFIG
	.comm	_mmUVD_UDEC_DB_ADDR_CONFIG,4,2  ; @mmUVD_UDEC_DB_ADDR_CONFIG
	.comm	_mmUVD_UDEC_DBW_ADDR_CONFIG,4,2 ; @mmUVD_UDEC_DBW_ADDR_CONFIG
	.comm	_mmUVD_UDEC_DBW_UV_ADDR_CONFIG,4,2 ; @mmUVD_UDEC_DBW_UV_ADDR_CONFIG
	.comm	_mmUVD_MIF_CURR_ADDR_CONFIG,4,2 ; @mmUVD_MIF_CURR_ADDR_CONFIG
	.comm	_mmUVD_MIF_CURR_UV_ADDR_CONFIG,4,2 ; @mmUVD_MIF_CURR_UV_ADDR_CONFIG
	.comm	_mmUVD_MIF_RECON1_ADDR_CONFIG,4,2 ; @mmUVD_MIF_RECON1_ADDR_CONFIG
	.comm	_mmUVD_MIF_RECON1_UV_ADDR_CONFIG,4,2 ; @mmUVD_MIF_RECON1_UV_ADDR_CONFIG
	.comm	_mmUVD_MIF_REF_ADDR_CONFIG,4,2  ; @mmUVD_MIF_REF_ADDR_CONFIG
	.comm	_mmUVD_MIF_REF_UV_ADDR_CONFIG,4,2 ; @mmUVD_MIF_REF_UV_ADDR_CONFIG
	.no_dead_strip	_vcn_v1_0_mc_resume_dpg_mode
.subsections_via_symbols
