	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_nv_set_ip_blocks               ## -- Begin function nv_set_ip_blocks
	.p2align	4, 0x90
_nv_set_ip_blocks:                      ## @nv_set_ip_blocks
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %r14
	callq	_nv_reg_base_init
	movl	%eax, %ebx
	testl	%eax, %eax
	je	LBB0_1
LBB0_26:
	movl	%ebx, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
LBB0_1:
	movq	_nbio_v2_3_funcs@GOTPCREL(%rip), %rax
	movq	%rax, 16(%r14)
	movq	%r14, %rdi
	callq	*(%rax)
	movl	(%r14), %eax
	cmpl	$130, %eax
	je	LBB0_4
## %bb.2:
	cmpl	$129, %eax
	je	LBB0_15
## %bb.3:
	cmpl	$128, %eax
	jne	LBB0_25
LBB0_4:
	movq	_nv_common_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_gmc_v10_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_navi10_ih_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_psp_v11_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
	movl	4(%r14), %eax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_7
## %bb.5:
	movq	%r14, %rdi
	callq	_is_support_sw_smu
	testl	%eax, %eax
	je	LBB0_7
## %bb.6:
	movq	_smu_v11_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
LBB0_7:
	cmpl	$0, 8(%r14)
	jne	LBB0_9
## %bb.8:
	movq	%r14, %rdi
	callq	_amdgpu_sriov_vf
	testl	%eax, %eax
	je	LBB0_10
LBB0_9:
	movq	_dce_virtual_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
LBB0_10:
	movq	_gfx_v10_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_sdma_v5_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
	movl	4(%r14), %eax
	movq	_AMDGPU_FW_LOAD_DIRECT@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_13
## %bb.11:
	movq	%r14, %rdi
	callq	_is_support_sw_smu
	testl	%eax, %eax
	je	LBB0_13
## %bb.12:
	movq	_smu_v11_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
LBB0_13:
	movq	_vcn_v2_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
	xorl	%ebx, %ebx
	cmpl	$0, 12(%r14)
	je	LBB0_26
## %bb.14:
	movq	_mes_v10_1_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
	jmp	LBB0_26
LBB0_15:
	movq	_nv_common_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_gmc_v10_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_navi10_ih_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_psp_v11_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
	movl	4(%r14), %eax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_18
## %bb.16:
	movq	%r14, %rdi
	callq	_is_support_sw_smu
	testl	%eax, %eax
	je	LBB0_18
## %bb.17:
	movq	_smu_v11_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
LBB0_18:
	cmpl	$0, 8(%r14)
	jne	LBB0_20
## %bb.19:
	movq	%r14, %rdi
	callq	_amdgpu_sriov_vf
	testl	%eax, %eax
	je	LBB0_21
LBB0_20:
	movq	_dce_virtual_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
LBB0_21:
	movq	_gfx_v10_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
	movq	_sdma_v5_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
	movl	4(%r14), %eax
	movq	_AMDGPU_FW_LOAD_DIRECT@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_24
## %bb.22:
	movq	%r14, %rdi
	callq	_is_support_sw_smu
	testl	%eax, %eax
	je	LBB0_24
## %bb.23:
	movq	_smu_v11_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
LBB0_24:
	movq	_vcn_v2_0_ip_block@GOTPCREL(%rip), %rsi
	movq	%r14, %rdi
	callq	_amdgpu_device_ip_block_add
	xorl	%ebx, %ebx
	jmp	LBB0_26
LBB0_25:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
	jmp	LBB0_26
	.cfi_endproc
                                        ## -- End function
	.comm	_nbio_v2_3_funcs,8,3            ## @nbio_v2_3_funcs
	.comm	_nv_common_ip_block,4,2         ## @nv_common_ip_block
	.comm	_gmc_v10_0_ip_block,4,2         ## @gmc_v10_0_ip_block
	.comm	_navi10_ih_ip_block,4,2         ## @navi10_ih_ip_block
	.comm	_psp_v11_0_ip_block,4,2         ## @psp_v11_0_ip_block
	.comm	_AMDGPU_FW_LOAD_PSP,4,2         ## @AMDGPU_FW_LOAD_PSP
	.comm	_smu_v11_0_ip_block,4,2         ## @smu_v11_0_ip_block
	.comm	_dce_virtual_ip_block,4,2       ## @dce_virtual_ip_block
	.comm	_gfx_v10_0_ip_block,4,2         ## @gfx_v10_0_ip_block
	.comm	_sdma_v5_0_ip_block,4,2         ## @sdma_v5_0_ip_block
	.comm	_AMDGPU_FW_LOAD_DIRECT,4,2      ## @AMDGPU_FW_LOAD_DIRECT
	.comm	_vcn_v2_0_ip_block,4,2          ## @vcn_v2_0_ip_block
	.comm	_mes_v10_1_ip_block,4,2         ## @mes_v10_1_ip_block
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_dm_ip_block,4,2                ## @dm_ip_block
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_nv_set_ip_blocks               ; -- Begin function nv_set_ip_blocks
	.p2align	2
_nv_set_ip_blocks:                      ; @nv_set_ip_blocks
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_nv_reg_base_init
	cbnz	w0, LBB0_28
; %bb.1:
Lloh0:
	adrp	x8, _nbio_v2_3_funcs@GOTPAGE
Lloh1:
	ldr	x8, [x8, _nbio_v2_3_funcs@GOTPAGEOFF]
	str	x8, [x19, #16]
	ldr	x8, [x8]
	mov	x0, x19
	blr	x8
	ldr	w8, [x19]
	cmp	w8, #130
	b.eq	LBB0_4
; %bb.2:
	cmp	w8, #129
	b.eq	LBB0_15
; %bb.3:
	cmp	w8, #128
	b.ne	LBB0_27
LBB0_4:
Lloh2:
	adrp	x1, _nv_common_ip_block@GOTPAGE
Lloh3:
	ldr	x1, [x1, _nv_common_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh4:
	adrp	x1, _gmc_v10_0_ip_block@GOTPAGE
Lloh5:
	ldr	x1, [x1, _gmc_v10_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh6:
	adrp	x1, _navi10_ih_ip_block@GOTPAGE
Lloh7:
	ldr	x1, [x1, _navi10_ih_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh8:
	adrp	x1, _psp_v11_0_ip_block@GOTPAGE
Lloh9:
	ldr	x1, [x1, _psp_v11_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
	ldr	w8, [x19, #4]
Lloh10:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh11:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_7
; %bb.5:
	mov	x0, x19
	bl	_is_support_sw_smu
	cbz	w0, LBB0_7
; %bb.6:
Lloh13:
	adrp	x1, _smu_v11_0_ip_block@GOTPAGE
Lloh14:
	ldr	x1, [x1, _smu_v11_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
LBB0_7:
	ldr	w8, [x19, #8]
	cbnz	w8, LBB0_9
; %bb.8:
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	w0, LBB0_10
LBB0_9:
Lloh15:
	adrp	x1, _dce_virtual_ip_block@GOTPAGE
Lloh16:
	ldr	x1, [x1, _dce_virtual_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
LBB0_10:
Lloh17:
	adrp	x1, _gfx_v10_0_ip_block@GOTPAGE
Lloh18:
	ldr	x1, [x1, _gfx_v10_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh19:
	adrp	x1, _sdma_v5_0_ip_block@GOTPAGE
Lloh20:
	ldr	x1, [x1, _sdma_v5_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
	ldr	w8, [x19, #4]
Lloh21:
	adrp	x9, _AMDGPU_FW_LOAD_DIRECT@GOTPAGE
Lloh22:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_DIRECT@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_13
; %bb.11:
	mov	x0, x19
	bl	_is_support_sw_smu
	cbz	w0, LBB0_13
; %bb.12:
Lloh24:
	adrp	x1, _smu_v11_0_ip_block@GOTPAGE
Lloh25:
	ldr	x1, [x1, _smu_v11_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
LBB0_13:
Lloh26:
	adrp	x1, _vcn_v2_0_ip_block@GOTPAGE
Lloh27:
	ldr	x1, [x1, _vcn_v2_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
	ldr	w8, [x19, #12]
	cbz	w8, LBB0_26
; %bb.14:
Lloh28:
	adrp	x1, _mes_v10_1_ip_block@GOTPAGE
Lloh29:
	ldr	x1, [x1, _mes_v10_1_ip_block@GOTPAGEOFF]
	b	LBB0_25
LBB0_15:
Lloh30:
	adrp	x1, _nv_common_ip_block@GOTPAGE
Lloh31:
	ldr	x1, [x1, _nv_common_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh32:
	adrp	x1, _gmc_v10_0_ip_block@GOTPAGE
Lloh33:
	ldr	x1, [x1, _gmc_v10_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh34:
	adrp	x1, _navi10_ih_ip_block@GOTPAGE
Lloh35:
	ldr	x1, [x1, _navi10_ih_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh36:
	adrp	x1, _psp_v11_0_ip_block@GOTPAGE
Lloh37:
	ldr	x1, [x1, _psp_v11_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
	ldr	w8, [x19, #4]
Lloh38:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh39:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_18
; %bb.16:
	mov	x0, x19
	bl	_is_support_sw_smu
	cbz	w0, LBB0_18
; %bb.17:
Lloh41:
	adrp	x1, _smu_v11_0_ip_block@GOTPAGE
Lloh42:
	ldr	x1, [x1, _smu_v11_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
LBB0_18:
	ldr	w8, [x19, #8]
	cbnz	w8, LBB0_20
; %bb.19:
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	w0, LBB0_21
LBB0_20:
Lloh43:
	adrp	x1, _dce_virtual_ip_block@GOTPAGE
Lloh44:
	ldr	x1, [x1, _dce_virtual_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
LBB0_21:
Lloh45:
	adrp	x1, _gfx_v10_0_ip_block@GOTPAGE
Lloh46:
	ldr	x1, [x1, _gfx_v10_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
Lloh47:
	adrp	x1, _sdma_v5_0_ip_block@GOTPAGE
Lloh48:
	ldr	x1, [x1, _sdma_v5_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
	ldr	w8, [x19, #4]
Lloh49:
	adrp	x9, _AMDGPU_FW_LOAD_DIRECT@GOTPAGE
Lloh50:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_DIRECT@GOTPAGEOFF]
Lloh51:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_24
; %bb.22:
	mov	x0, x19
	bl	_is_support_sw_smu
	cbz	w0, LBB0_24
; %bb.23:
Lloh52:
	adrp	x1, _smu_v11_0_ip_block@GOTPAGE
Lloh53:
	ldr	x1, [x1, _smu_v11_0_ip_block@GOTPAGEOFF]
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
LBB0_24:
Lloh54:
	adrp	x1, _vcn_v2_0_ip_block@GOTPAGE
Lloh55:
	ldr	x1, [x1, _vcn_v2_0_ip_block@GOTPAGEOFF]
LBB0_25:
	mov	x0, x19
	bl	_amdgpu_device_ip_block_add
LBB0_26:
	mov	w0, #0
	b	LBB0_28
LBB0_27:
Lloh56:
	adrp	x8, _EINVAL@GOTPAGE
Lloh57:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh58:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_28:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.cfi_endproc
                                        ; -- End function
	.comm	_nbio_v2_3_funcs,8,3            ; @nbio_v2_3_funcs
	.comm	_nv_common_ip_block,4,2         ; @nv_common_ip_block
	.comm	_gmc_v10_0_ip_block,4,2         ; @gmc_v10_0_ip_block
	.comm	_navi10_ih_ip_block,4,2         ; @navi10_ih_ip_block
	.comm	_psp_v11_0_ip_block,4,2         ; @psp_v11_0_ip_block
	.comm	_AMDGPU_FW_LOAD_PSP,4,2         ; @AMDGPU_FW_LOAD_PSP
	.comm	_smu_v11_0_ip_block,4,2         ; @smu_v11_0_ip_block
	.comm	_dce_virtual_ip_block,4,2       ; @dce_virtual_ip_block
	.comm	_gfx_v10_0_ip_block,4,2         ; @gfx_v10_0_ip_block
	.comm	_sdma_v5_0_ip_block,4,2         ; @sdma_v5_0_ip_block
	.comm	_AMDGPU_FW_LOAD_DIRECT,4,2      ; @AMDGPU_FW_LOAD_DIRECT
	.comm	_vcn_v2_0_ip_block,4,2          ; @vcn_v2_0_ip_block
	.comm	_mes_v10_1_ip_block,4,2         ; @mes_v10_1_ip_block
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_dm_ip_block,4,2                ; @dm_ip_block
.subsections_via_symbols
