	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_is_support_sw_smu_xgmi         ## -- Begin function is_support_sw_smu_xgmi
	.p2align	4, 0x90
_is_support_sw_smu_xgmi:                ## @is_support_sw_smu_xgmi
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	_amdgpu_dpm@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	cmpl	$1, (%rcx)
	jne	LBB0_2
## %bb.1:
	movq	(%rdi), %rcx
	movq	_CHIP_VEGA20@GOTPCREL(%rip), %rdx
	xorl	%eax, %eax
	cmpq	(%rdx), %rcx
	sete	%al
LBB0_2:
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_amdgpu_dpm,4,2                 ## @amdgpu_dpm
	.comm	_CHIP_VEGA20,8,3                ## @CHIP_VEGA20
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_is_support_sw_smu_xgmi         ; -- Begin function is_support_sw_smu_xgmi
	.p2align	2
_is_support_sw_smu_xgmi:                ; @is_support_sw_smu_xgmi
	.cfi_startproc
; %bb.0:
Lloh0:
	adrp	x8, _amdgpu_dpm@GOTPAGE
Lloh1:
	ldr	x8, [x8, _amdgpu_dpm@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cmp	w8, #1
	b.ne	LBB0_2
; %bb.1:
	ldr	x8, [x0]
Lloh3:
	adrp	x9, _CHIP_VEGA20@GOTPAGE
Lloh4:
	ldr	x9, [x9, _CHIP_VEGA20@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
	cmp	x8, x9
	cset	w0, eq
	ret
LBB0_2:
	mov	w0, #0
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_amdgpu_dpm,4,2                 ; @amdgpu_dpm
	.comm	_CHIP_VEGA20,8,3                ; @CHIP_VEGA20
.subsections_via_symbols
