	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function cik_cp_gfx_resume
_cik_cp_gfx_resume:                     ## @cik_cp_gfx_resume
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	_CP_SEM_WAIT_TIMER@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	(%rbx), %rax
	movq	_CHIP_HAWAII@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_2
## %bb.1:
	movq	_CP_SEM_INCOMPLETE_TIMER_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
LBB0_2:
	movq	_CP_RB_WPTR_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CP_RB_VMID@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_SCRATCH_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_WB_SCRATCH_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	32(%rbx), %esi
	sarl	$8, %esi
	callq	_WREG32
	movq	%rbx, -48(%rbp)                 ## 8-byte Spill
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movq	24(%rax), %r15
	movq	_RADEON_RING_TYPE_GFX_INDEX@GOTPCREL(%rip), %rax
	movq	(%rax), %r14
	shlq	$4, %r14
	movl	(%r15,%r14), %eax
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	callq	_order_base_2
	movl	%eax, %r12d
	movq	_RADEON_GPU_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	leal	7(%rax), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$3, %edi
	callq	_order_base_2
	movl	%eax, %r13d
	shll	$8, %r13d
	orl	%r12d, %r13d
	movq	_CP_RB0_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movl	%r13d, %esi
	callq	_WREG32
	movl	(%rbx), %edi
	movq	_RB_RPTR_WR_ENA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	%r13d, %esi
	callq	_WREG32
	movq	%r15, -56(%rbp)                 ## 8-byte Spill
	movl	$0, 4(%r15,%r14)
	movq	-48(%rbp), %r15                 ## 8-byte Reload
	movq	_CP_RB0_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_CP_RB0_RPTR_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_RADEON_WB_CP_RPTR_OFFSET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	addl	32(%r15), %esi
	andl	$-4, %esi
	callq	_WREG32
	movq	_CP_RB0_RPTR_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	(%rbx), %edi
	addl	32(%r15), %edi
	callq	_upper_32_bits
	movzbl	%al, %esi
	movl	%r12d, %edi
	callq	_WREG32
	movq	_SCRATCH_UMSK@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	cmpl	$0, 36(%r15)
	movl	$0, %ebx
	jne	LBB0_4
## %bb.3:
	movq	_RB_NO_UPDATE@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
LBB0_4:
	orl	%r13d, %ebx
	movl	$1, %edi
	callq	_mdelay
	movq	_CP_RB0_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	8(%rax,%r14), %ebx
	sarl	$8, %ebx
	movq	_CP_RB0_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_WREG32
	movq	_CP_RB0_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	%ebx, %edi
	callq	_upper_32_bits
	movl	%r14d, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	%r15, %rdi
	callq	_cik_cp_gfx_start
	movq	24(%r15), %rax
	movq	_RADEON_RING_TYPE_GFX_INDEX@GOTPCREL(%rip), %r14
	movq	(%r14), %rsi
	movq	%rsi, %rcx
	shlq	$4, %rcx
	leaq	(%rax,%rcx), %rdx
	movl	$1, 12(%rax,%rcx)
	movq	%r15, %rdi
	callq	_radeon_ring_test
	movl	%eax, %ebx
	testl	%eax, %eax
	je	LBB0_6
## %bb.5:
	movq	24(%r15), %rax
	movq	(%r14), %rcx
	shlq	$4, %rcx
	movl	$0, 12(%rax,%rcx)
	jmp	LBB0_8
LBB0_6:
	movq	16(%r15), %rax
	movq	(%rax), %rax
	cmpq	(%r14), %rax
	jne	LBB0_8
## %bb.7:
	movl	8(%r15), %esi
	movq	%r15, %rdi
	callq	_radeon_ttm_set_active_vram_size
LBB0_8:
	movl	%ebx, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CP_SEM_WAIT_TIMER,4,2          ## @CP_SEM_WAIT_TIMER
	.comm	_CHIP_HAWAII,8,3                ## @CHIP_HAWAII
	.comm	_CP_SEM_INCOMPLETE_TIMER_CNTL,4,2 ## @CP_SEM_INCOMPLETE_TIMER_CNTL
	.comm	_CP_RB_WPTR_DELAY,4,2           ## @CP_RB_WPTR_DELAY
	.comm	_CP_RB_VMID,4,2                 ## @CP_RB_VMID
	.comm	_SCRATCH_ADDR,4,2               ## @SCRATCH_ADDR
	.comm	_RADEON_WB_SCRATCH_OFFSET,4,2   ## @RADEON_WB_SCRATCH_OFFSET
	.comm	_RADEON_RING_TYPE_GFX_INDEX,8,3 ## @RADEON_RING_TYPE_GFX_INDEX
	.comm	_RADEON_GPU_PAGE_SIZE,4,2       ## @RADEON_GPU_PAGE_SIZE
	.comm	_CP_RB0_CNTL,4,2                ## @CP_RB0_CNTL
	.comm	_RB_RPTR_WR_ENA,4,2             ## @RB_RPTR_WR_ENA
	.comm	_CP_RB0_WPTR,4,2                ## @CP_RB0_WPTR
	.comm	_CP_RB0_RPTR_ADDR,4,2           ## @CP_RB0_RPTR_ADDR
	.comm	_RADEON_WB_CP_RPTR_OFFSET,4,2   ## @RADEON_WB_CP_RPTR_OFFSET
	.comm	_CP_RB0_RPTR_ADDR_HI,4,2        ## @CP_RB0_RPTR_ADDR_HI
	.comm	_SCRATCH_UMSK,4,2               ## @SCRATCH_UMSK
	.comm	_RB_NO_UPDATE,4,2               ## @RB_NO_UPDATE
	.comm	_CP_RB0_BASE,4,2                ## @CP_RB0_BASE
	.comm	_CP_RB0_BASE_HI,4,2             ## @CP_RB0_BASE_HI
	.comm	_BUF_SWAP_32BIT,4,2             ## @BUF_SWAP_32BIT
	.no_dead_strip	_cik_cp_gfx_resume
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cik_cp_gfx_resume
_cik_cp_gfx_resume:                     ; @cik_cp_gfx_resume
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
Lloh0:
	adrp	x8, _CP_SEM_WAIT_TIMER@GOTPAGE
Lloh1:
	ldr	x8, [x8, _CP_SEM_WAIT_TIMER@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	ldr	x8, [x19]
Lloh3:
	adrp	x9, _CHIP_HAWAII@GOTPAGE
Lloh4:
	ldr	x9, [x9, _CHIP_HAWAII@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_2
; %bb.1:
Lloh6:
	adrp	x8, _CP_SEM_INCOMPLETE_TIMER_CNTL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _CP_SEM_INCOMPLETE_TIMER_CNTL@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
LBB0_2:
Lloh9:
	adrp	x8, _CP_RB_WPTR_DELAY@GOTPAGE
Lloh10:
	ldr	x8, [x8, _CP_RB_WPTR_DELAY@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh12:
	adrp	x8, _CP_RB_VMID@GOTPAGE
Lloh13:
	ldr	x8, [x8, _CP_RB_VMID@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh15:
	adrp	x8, _SCRATCH_ADDR@GOTPAGE
Lloh16:
	ldr	x8, [x8, _SCRATCH_ADDR@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	ldr	w8, [x19, #32]
Lloh18:
	adrp	x9, _RADEON_WB_SCRATCH_OFFSET@GOTPAGE
Lloh19:
	ldr	x9, [x9, _RADEON_WB_SCRATCH_OFFSET@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	add	w8, w9, w8
	asr	w1, w8, #8
	bl	_WREG32
	ldr	x8, [x19, #24]
Lloh21:
	adrp	x22, _RADEON_RING_TYPE_GFX_INDEX@GOTPAGE
Lloh22:
	ldr	x22, [x22, _RADEON_RING_TYPE_GFX_INDEX@GOTPAGEOFF]
	ldr	x9, [x22]
	add	x23, x8, x9, lsl #4
	ldr	w8, [x23]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #3
	bl	_order_base_2
	mov	x20, x0
Lloh23:
	adrp	x8, _RADEON_GPU_PAGE_SIZE@GOTPAGE
Lloh24:
	ldr	x8, [x8, _RADEON_GPU_PAGE_SIZE@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w0, w8, #3
	bl	_order_base_2
	orr	w20, w20, w0, lsl #8
Lloh26:
	adrp	x24, _CP_RB0_CNTL@GOTPAGE
Lloh27:
	ldr	x24, [x24, _CP_RB0_CNTL@GOTPAGEOFF]
	ldr	w0, [x24]
	mov	x1, x20
	bl	_WREG32
	ldr	w0, [x24]
Lloh28:
	adrp	x8, _RB_RPTR_WR_ENA@GOTPAGE
Lloh29:
	ldr	x8, [x8, _RB_RPTR_WR_ENA@GOTPAGEOFF]
Lloh30:
	ldr	w8, [x8]
	orr	w1, w8, w20
	bl	_WREG32
	str	wzr, [x23, #4]
Lloh31:
	adrp	x8, _CP_RB0_WPTR@GOTPAGE
Lloh32:
	ldr	x8, [x8, _CP_RB0_WPTR@GOTPAGEOFF]
Lloh33:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh34:
	adrp	x8, _CP_RB0_RPTR_ADDR@GOTPAGE
Lloh35:
	ldr	x8, [x8, _CP_RB0_RPTR_ADDR@GOTPAGEOFF]
Lloh36:
	ldr	w0, [x8]
	ldr	w8, [x19, #32]
Lloh37:
	adrp	x25, _RADEON_WB_CP_RPTR_OFFSET@GOTPAGE
Lloh38:
	ldr	x25, [x25, _RADEON_WB_CP_RPTR_OFFSET@GOTPAGEOFF]
	ldr	w9, [x25]
	add	w8, w9, w8
	and	w1, w8, #0xfffffffc
	bl	_WREG32
Lloh39:
	adrp	x8, _CP_RB0_RPTR_ADDR_HI@GOTPAGE
Lloh40:
	ldr	x8, [x8, _CP_RB0_RPTR_ADDR_HI@GOTPAGEOFF]
Lloh41:
	ldr	w21, [x8]
	ldr	w8, [x19, #32]
	ldr	w9, [x25]
	add	w0, w9, w8
	bl	_upper_32_bits
	and	w1, w0, #0xff
	mov	x0, x21
	bl	_WREG32
Lloh42:
	adrp	x8, _SCRATCH_UMSK@GOTPAGE
Lloh43:
	ldr	x8, [x8, _SCRATCH_UMSK@GOTPAGEOFF]
Lloh44:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
	ldr	w8, [x19, #36]
Lloh45:
	adrp	x9, _RB_NO_UPDATE@GOTPAGE
Lloh46:
	ldr	x9, [x9, _RB_NO_UPDATE@GOTPAGEOFF]
Lloh47:
	ldr	w9, [x9]
	cmp	w8, #0
	csel	w8, w9, wzr, eq
	orr	w20, w8, w20
	mov	w25, #1
	mov	w0, #1
	bl	_mdelay
	ldr	w0, [x24]
	mov	x1, x20
	bl	_WREG32
	ldr	w8, [x23, #8]
	asr	w20, w8, #8
Lloh48:
	adrp	x8, _CP_RB0_BASE@GOTPAGE
Lloh49:
	ldr	x8, [x8, _CP_RB0_BASE@GOTPAGEOFF]
Lloh50:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_WREG32
Lloh51:
	adrp	x8, _CP_RB0_BASE_HI@GOTPAGE
Lloh52:
	ldr	x8, [x8, _CP_RB0_BASE_HI@GOTPAGEOFF]
Lloh53:
	ldr	w21, [x8]
	mov	x0, x20
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x21
	bl	_WREG32
	mov	x0, x19
	bl	_cik_cp_gfx_start
	ldr	x8, [x19, #24]
	ldr	x1, [x22]
	add	x2, x8, x1, lsl #4
	str	w25, [x2, #12]
	mov	x0, x19
	bl	_radeon_ring_test
	mov	x20, x0
	cbz	w0, LBB0_4
; %bb.3:
	ldr	x8, [x19, #24]
	ldr	x9, [x22]
	add	x8, x8, x9, lsl #4
	str	wzr, [x8, #12]
	b	LBB0_6
LBB0_4:
	ldr	x8, [x19, #16]
	ldr	x8, [x8]
	ldr	x9, [x22]
	cmp	x8, x9
	b.ne	LBB0_6
; %bb.5:
	ldr	w1, [x19, #8]
	mov	x0, x19
	bl	_radeon_ttm_set_active_vram_size
LBB0_6:
	mov	x0, x20
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.cfi_endproc
                                        ; -- End function
	.comm	_CP_SEM_WAIT_TIMER,4,2          ; @CP_SEM_WAIT_TIMER
	.comm	_CHIP_HAWAII,8,3                ; @CHIP_HAWAII
	.comm	_CP_SEM_INCOMPLETE_TIMER_CNTL,4,2 ; @CP_SEM_INCOMPLETE_TIMER_CNTL
	.comm	_CP_RB_WPTR_DELAY,4,2           ; @CP_RB_WPTR_DELAY
	.comm	_CP_RB_VMID,4,2                 ; @CP_RB_VMID
	.comm	_SCRATCH_ADDR,4,2               ; @SCRATCH_ADDR
	.comm	_RADEON_WB_SCRATCH_OFFSET,4,2   ; @RADEON_WB_SCRATCH_OFFSET
	.comm	_RADEON_RING_TYPE_GFX_INDEX,8,3 ; @RADEON_RING_TYPE_GFX_INDEX
	.comm	_RADEON_GPU_PAGE_SIZE,4,2       ; @RADEON_GPU_PAGE_SIZE
	.comm	_CP_RB0_CNTL,4,2                ; @CP_RB0_CNTL
	.comm	_RB_RPTR_WR_ENA,4,2             ; @RB_RPTR_WR_ENA
	.comm	_CP_RB0_WPTR,4,2                ; @CP_RB0_WPTR
	.comm	_CP_RB0_RPTR_ADDR,4,2           ; @CP_RB0_RPTR_ADDR
	.comm	_RADEON_WB_CP_RPTR_OFFSET,4,2   ; @RADEON_WB_CP_RPTR_OFFSET
	.comm	_CP_RB0_RPTR_ADDR_HI,4,2        ; @CP_RB0_RPTR_ADDR_HI
	.comm	_SCRATCH_UMSK,4,2               ; @SCRATCH_UMSK
	.comm	_RB_NO_UPDATE,4,2               ; @RB_NO_UPDATE
	.comm	_CP_RB0_BASE,4,2                ; @CP_RB0_BASE
	.comm	_CP_RB0_BASE_HI,4,2             ; @CP_RB0_BASE_HI
	.comm	_BUF_SWAP_32BIT,4,2             ; @BUF_SWAP_32BIT
	.no_dead_strip	_cik_cp_gfx_resume
.subsections_via_symbols
