	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function sdma_v4_0_start
_sdma_v4_0_start:                       ## @sdma_v4_0_start
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_sdma_v4_0_ctx_switch_enable
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_sdma_v4_0_enable
	cmpl	$0, 8(%r14)
	jg	LBB0_6
	jmp	LBB0_12
LBB0_2:
	movq	32(%r14), %rax
	movq	_AMDGPU_FW_LOAD_PSP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_4
## %bb.3:
	movq	%r14, %rdi
	callq	_sdma_v4_0_load_microcode
	testl	%eax, %eax
	jne	LBB0_26
LBB0_4:
	movq	%r14, %rdi
	movl	$1, %esi
	callq	_sdma_v4_0_enable
	movq	%r14, %rdi
	movl	$1, %esi
	callq	_sdma_v4_0_ctx_switch_enable
	cmpl	$0, 8(%r14)
	jle	LBB0_12
LBB0_6:
	xorl	%ebx, %ebx
	movq	_mmSDMA0_CNTL@GOTPCREL(%rip), %r12
	movq	_SDMA0_CNTL@GOTPCREL(%rip), %r13
	movq	_UTC_L1_ENABLE@GOTPCREL(%rip), %r15
	jmp	LBB0_7
	.p2align	4, 0x90
LBB0_11:                                ##   in Loop: Header=BB0_7 Depth=1
	incl	%ebx
	cmpl	8(%r14), %ebx
	jge	LBB0_12
LBB0_7:                                 ## =>This Inner Loop Header: Depth=1
	movq	_mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%ebx, %edi
	xorl	%edx, %edx
	callq	_WREG32_SDMA
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_sdma_v4_0_gfx_resume
	cmpq	$0, 24(%r14)
	je	LBB0_9
## %bb.8:                               ##   in Loop: Header=BB0_7 Depth=1
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_sdma_v4_0_page_resume
LBB0_9:                                 ##   in Loop: Header=BB0_7 Depth=1
	movl	(%r12), %esi
	movl	%ebx, %edi
	callq	_RREG32_SDMA
	movl	(%r13), %esi
	movl	(%r15), %edx
	movq	%rax, %rdi
	movl	$1, %ecx
	callq	_REG_SET_FIELD
	movl	(%r12), %esi
	movl	%ebx, %edi
	movq	%rax, %rdx
	callq	_WREG32_SDMA
	movq	%r14, %rdi
	callq	_amdgpu_sriov_vf
	testq	%rax, %rax
	jne	LBB0_11
## %bb.10:                              ##   in Loop: Header=BB0_7 Depth=1
	movq	_mmSDMA0_F32_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%ebx, %edi
	callq	_RREG32_SDMA
	movq	_SDMA0_F32_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_HALT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%rax, %rdi
	xorl	%ecx, %ecx
	callq	_REG_SET_FIELD
	movq	_mmSDMA0_F32_CNTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%ebx, %edi
	movq	%rax, %rdx
	callq	_WREG32_SDMA
	jmp	LBB0_11
LBB0_12:
	movq	%r14, %rdi
	callq	_amdgpu_sriov_vf
	movq	%r14, %rdi
	testq	%rax, %rax
	je	LBB0_14
## %bb.13:
	movl	$1, %esi
	callq	_sdma_v4_0_ctx_switch_enable
	movq	%r14, %rdi
	movl	$1, %esi
	callq	_sdma_v4_0_enable
LBB0_15:
	cmpl	$0, 8(%r14)
	jle	LBB0_25
## %bb.16:
	movl	$4, %r12d
	xorl	%r13d, %r13d
	jmp	LBB0_17
	.p2align	4, 0x90
LBB0_22:                                ##   in Loop: Header=BB0_17 Depth=1
	cmpq	(%r14), %rbx
	je	LBB0_23
LBB0_24:                                ##   in Loop: Header=BB0_17 Depth=1
	incq	%r13
	movslq	8(%r14), %rax
	addq	$8, %r12
	cmpq	%rax, %r13
	jge	LBB0_25
LBB0_17:                                ## =>This Inner Loop Header: Depth=1
	movq	16(%r14), %rbx
	addq	%r12, %rbx
	movq	%rbx, %rdi
	callq	_amdgpu_ring_test_helper
	testl	%eax, %eax
	jne	LBB0_26
## %bb.18:                              ##   in Loop: Header=BB0_17 Depth=1
	cmpq	$0, 24(%r14)
	je	LBB0_22
## %bb.19:                              ##   in Loop: Header=BB0_17 Depth=1
	movq	16(%r14), %rax
	leaq	(%rax,%r12), %r15
	addq	$-4, %r15
	movq	%r15, %rdi
	callq	_amdgpu_ring_test_helper
	testl	%eax, %eax
	jne	LBB0_26
## %bb.20:                              ##   in Loop: Header=BB0_17 Depth=1
	cmpq	(%r14), %r15
	jne	LBB0_22
## %bb.21:                              ##   in Loop: Header=BB0_17 Depth=1
	movq	%r14, %rdi
	movl	$1, %esi
	callq	_amdgpu_ttm_set_buffer_funcs_status
	jmp	LBB0_22
	.p2align	4, 0x90
LBB0_23:                                ##   in Loop: Header=BB0_17 Depth=1
	movq	%r14, %rdi
	movl	$1, %esi
	callq	_amdgpu_ttm_set_buffer_funcs_status
	jmp	LBB0_24
LBB0_25:
	xorl	%eax, %eax
	jmp	LBB0_26
LBB0_14:
	callq	_sdma_v4_0_rlc_resume
	testl	%eax, %eax
	je	LBB0_15
LBB0_26:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ## @AMDGPU_FW_LOAD_PSP
	.comm	_mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL,4,2 ## @mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
	.comm	_mmSDMA0_CNTL,4,2               ## @mmSDMA0_CNTL
	.comm	_SDMA0_CNTL,4,2                 ## @SDMA0_CNTL
	.comm	_UTC_L1_ENABLE,4,2              ## @UTC_L1_ENABLE
	.comm	_mmSDMA0_F32_CNTL,4,2           ## @mmSDMA0_F32_CNTL
	.comm	_SDMA0_F32_CNTL,4,2             ## @SDMA0_F32_CNTL
	.comm	_HALT,4,2                       ## @HALT
	.no_dead_strip	_sdma_v4_0_start
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function sdma_v4_0_start
_sdma_v4_0_start:                       ; @sdma_v4_0_start
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_2
; %bb.1:
	mov	x0, x19
	mov	w1, #0
	bl	_sdma_v4_0_ctx_switch_enable
	mov	x0, x19
	mov	w1, #0
	bl	_sdma_v4_0_enable
	b	LBB0_5
LBB0_2:
	ldr	x8, [x19, #32]
Lloh0:
	adrp	x9, _AMDGPU_FW_LOAD_PSP@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMDGPU_FW_LOAD_PSP@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_4
; %bb.3:
	mov	x0, x19
	bl	_sdma_v4_0_load_microcode
	cbnz	w0, LBB0_26
LBB0_4:
	mov	x0, x19
	mov	w1, #1
	bl	_sdma_v4_0_enable
	mov	x0, x19
	mov	w1, #1
	bl	_sdma_v4_0_ctx_switch_enable
LBB0_5:
	ldr	w8, [x19, #8]
	cmp	w8, #1
	b.lt	LBB0_12
; %bb.6:
	mov	w20, #0
Lloh3:
	adrp	x21, _mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL@GOTPAGE
Lloh4:
	ldr	x21, [x21, _mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL@GOTPAGEOFF]
Lloh5:
	adrp	x22, _mmSDMA0_CNTL@GOTPAGE
Lloh6:
	ldr	x22, [x22, _mmSDMA0_CNTL@GOTPAGEOFF]
Lloh7:
	adrp	x23, _SDMA0_CNTL@GOTPAGE
Lloh8:
	ldr	x23, [x23, _SDMA0_CNTL@GOTPAGEOFF]
Lloh9:
	adrp	x24, _UTC_L1_ENABLE@GOTPAGE
Lloh10:
	ldr	x24, [x24, _UTC_L1_ENABLE@GOTPAGEOFF]
Lloh11:
	adrp	x25, _mmSDMA0_F32_CNTL@GOTPAGE
Lloh12:
	ldr	x25, [x25, _mmSDMA0_F32_CNTL@GOTPAGEOFF]
Lloh13:
	adrp	x26, _SDMA0_F32_CNTL@GOTPAGE
Lloh14:
	ldr	x26, [x26, _SDMA0_F32_CNTL@GOTPAGEOFF]
Lloh15:
	adrp	x27, _HALT@GOTPAGE
Lloh16:
	ldr	x27, [x27, _HALT@GOTPAGEOFF]
	b	LBB0_8
LBB0_7:                                 ;   in Loop: Header=BB0_8 Depth=1
	add	w20, w20, #1
	ldr	w8, [x19, #8]
	cmp	w20, w8
	b.ge	LBB0_12
LBB0_8:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x21]
	mov	x0, x20
	mov	x2, #0
	bl	_WREG32_SDMA
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v4_0_gfx_resume
	ldr	x8, [x19, #24]
	cbz	x8, LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=1
	mov	x0, x19
	mov	x1, x20
	bl	_sdma_v4_0_page_resume
LBB0_10:                                ;   in Loop: Header=BB0_8 Depth=1
	ldr	w1, [x22]
	mov	x0, x20
	bl	_RREG32_SDMA
	ldr	w1, [x23]
	ldr	w2, [x24]
	mov	w3, #1
	bl	_REG_SET_FIELD
	mov	x2, x0
	ldr	w1, [x22]
	mov	x0, x20
	bl	_WREG32_SDMA
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbnz	x0, LBB0_7
; %bb.11:                               ;   in Loop: Header=BB0_8 Depth=1
	ldr	w1, [x25]
	mov	x0, x20
	bl	_RREG32_SDMA
	ldr	w1, [x26]
	ldr	w2, [x27]
	mov	w3, #0
	bl	_REG_SET_FIELD
	mov	x2, x0
	ldr	w1, [x25]
	mov	x0, x20
	bl	_WREG32_SDMA
	b	LBB0_7
LBB0_12:
	mov	x0, x19
	bl	_amdgpu_sriov_vf
	cbz	x0, LBB0_25
; %bb.13:
	mov	x0, x19
	mov	w1, #1
	bl	_sdma_v4_0_ctx_switch_enable
	mov	x0, x19
	mov	w1, #1
	bl	_sdma_v4_0_enable
LBB0_14:
	ldr	w8, [x19, #8]
	cmp	w8, #1
	b.lt	LBB0_24
; %bb.15:
	mov	x22, #0
	mov	w23, #4
	b	LBB0_18
LBB0_16:                                ;   in Loop: Header=BB0_18 Depth=1
	ldr	x8, [x19]
	cmp	x20, x8
	b.eq	LBB0_23
LBB0_17:                                ;   in Loop: Header=BB0_18 Depth=1
	add	x22, x22, #1
	ldrsw	x8, [x19, #8]
	add	x23, x23, #8
	cmp	x22, x8
	b.ge	LBB0_24
LBB0_18:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #16]
	add	x20, x8, x23
	mov	x0, x20
	bl	_amdgpu_ring_test_helper
	cbnz	w0, LBB0_26
; %bb.19:                               ;   in Loop: Header=BB0_18 Depth=1
	ldr	x8, [x19, #24]
	cbz	x8, LBB0_16
; %bb.20:                               ;   in Loop: Header=BB0_18 Depth=1
	ldr	x8, [x19, #16]
	add	x8, x8, x23
	sub	x21, x8, #4
	mov	x0, x21
	bl	_amdgpu_ring_test_helper
	cbnz	w0, LBB0_26
; %bb.21:                               ;   in Loop: Header=BB0_18 Depth=1
	ldr	x8, [x19]
	cmp	x21, x8
	b.ne	LBB0_16
; %bb.22:                               ;   in Loop: Header=BB0_18 Depth=1
	mov	x0, x19
	mov	w1, #1
	bl	_amdgpu_ttm_set_buffer_funcs_status
	b	LBB0_16
LBB0_23:                                ;   in Loop: Header=BB0_18 Depth=1
	mov	x0, x19
	mov	w1, #1
	bl	_amdgpu_ttm_set_buffer_funcs_status
	b	LBB0_17
LBB0_24:
	mov	w0, #0
	b	LBB0_26
LBB0_25:
	mov	x0, x19
	bl	_sdma_v4_0_rlc_resume
	cbz	w0, LBB0_14
LBB0_26:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_FW_LOAD_PSP,8,3         ; @AMDGPU_FW_LOAD_PSP
	.comm	_mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL,4,2 ; @mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
	.comm	_mmSDMA0_CNTL,4,2               ; @mmSDMA0_CNTL
	.comm	_SDMA0_CNTL,4,2                 ; @SDMA0_CNTL
	.comm	_UTC_L1_ENABLE,4,2              ; @UTC_L1_ENABLE
	.comm	_mmSDMA0_F32_CNTL,4,2           ; @mmSDMA0_F32_CNTL
	.comm	_SDMA0_F32_CNTL,4,2             ; @SDMA0_F32_CNTL
	.comm	_HALT,4,2                       ; @HALT
	.no_dead_strip	_sdma_v4_0_start
.subsections_via_symbols
