	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function etnaviv_gpu_enable_mlcg
_etnaviv_gpu_enable_mlcg:               ## @etnaviv_gpu_enable_mlcg
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_VIVS_PM_POWER_CONTROLS@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	callq	_gpu_read
	movq	_VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	$-17153, %edx                   ## imm = 0xBCFF
	addl	(%r14), %edx
	xorl	%ecx, %ecx
	cmpl	$2, %edx
	jae	LBB0_2
## %bb.1:
	movq	_VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_2:
	orl	%ecx, %eax
	movl	(%rbx), %esi
	movq	%r14, %rdi
	movl	%eax, %edx
	callq	_gpu_write
	movq	_VIVS_PM_MODULE_CONTROLS@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_gpu_read
	movl	%eax, %ebx
	movq	8(%r14), %rax
	movq	_chipModel_GC400@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_6
## %bb.3:
	movq	_chipModel_GC420@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_6
## %bb.4:
	movq	_chipMinorFeatures3_BUG_FIXES12@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 16(%r14)
	jne	LBB0_6
## %bb.5:
	movq	_VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
LBB0_6:
	movl	(%r14), %eax
	cmpl	$20479, %eax                    ## imm = 0x4FFF
	jg	LBB0_10
## %bb.7:
	movq	_chipMinorFeatures0_HZ@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 20(%r14)
	je	LBB0_11
## %bb.8:
	movq	_chipMinorFeatures1_DISABLE_PE_GATING@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 24(%r14)
	jne	LBB0_11
## %bb.9:
	movq	_VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	jmp	LBB0_11
LBB0_10:
	cmpl	$21537, %eax                    ## imm = 0x5421
	ja	LBB0_12
LBB0_11:
	movl	$15, %edi
	callq	_BIT
	orl	%eax, %ebx
LBB0_12:
	movq	_GC4000@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$21026, %edx                    ## imm = 0x5222
	callq	_etnaviv_is_model_rev
	testq	%rax, %rax
	jne	LBB0_14
## %bb.13:
	movq	_GC2000@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$20744, %edx                    ## imm = 0x5108
	callq	_etnaviv_is_model_rev
	testq	%rax, %rax
	je	LBB0_15
LBB0_14:
	movq	_VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
LBB0_15:
	movq	_VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	(%r15), %esi
	movq	%r14, %rdi
	movl	%ebx, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_gpu_write                      ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_VIVS_PM_POWER_CONTROLS,4,2     ## @VIVS_PM_POWER_CONTROLS
	.comm	_VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING,4,2 ## @VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING
	.comm	_VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING,4,2 ## @VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING
	.comm	_VIVS_PM_MODULE_CONTROLS,4,2    ## @VIVS_PM_MODULE_CONTROLS
	.comm	_chipModel_GC400,8,3            ## @chipModel_GC400
	.comm	_chipModel_GC420,8,3            ## @chipModel_GC420
	.comm	_chipMinorFeatures3_BUG_FIXES12,4,2 ## @chipMinorFeatures3_BUG_FIXES12
	.comm	_VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA,4,2 ## @VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA
	.comm	_chipMinorFeatures0_HZ,4,2      ## @chipMinorFeatures0_HZ
	.comm	_chipMinorFeatures1_DISABLE_PE_GATING,4,2 ## @chipMinorFeatures1_DISABLE_PE_GATING
	.comm	_VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE,4,2 ## @VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE
	.comm	_GC4000,4,2                     ## @GC4000
	.comm	_GC2000,4,2                     ## @GC2000
	.comm	_VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX,4,2 ## @VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX
	.comm	_VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ,4,2 ## @VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ
	.comm	_VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ,4,2 ## @VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ
	.no_dead_strip	_etnaviv_gpu_enable_mlcg
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function etnaviv_gpu_enable_mlcg
_etnaviv_gpu_enable_mlcg:               ; @etnaviv_gpu_enable_mlcg
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x20, _VIVS_PM_POWER_CONTROLS@GOTPAGE
Lloh1:
	ldr	x20, [x20, _VIVS_PM_POWER_CONTROLS@GOTPAGEOFF]
	ldr	w1, [x20]
	bl	_gpu_read
Lloh2:
	adrp	x8, _VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING@GOTPAGE
Lloh3:
	ldr	x8, [x8, _VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	orr	w8, w8, w0
	ldr	w9, [x19]
	mov	w10, #-17153
Lloh5:
	adrp	x11, _VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING@GOTPAGE
Lloh6:
	ldr	x11, [x11, _VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING@GOTPAGEOFF]
	add	w9, w9, w10
Lloh7:
	ldr	w10, [x11]
	cmp	w9, #2
	csel	w9, w10, wzr, lo
	orr	w2, w8, w9
	ldr	w1, [x20]
	mov	x0, x19
	bl	_gpu_write
Lloh8:
	adrp	x21, _VIVS_PM_MODULE_CONTROLS@GOTPAGE
Lloh9:
	ldr	x21, [x21, _VIVS_PM_MODULE_CONTROLS@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_gpu_read
	mov	x20, x0
	ldr	x8, [x19, #8]
Lloh10:
	adrp	x9, _chipModel_GC400@GOTPAGE
Lloh11:
	ldr	x9, [x9, _chipModel_GC400@GOTPAGEOFF]
Lloh12:
	ldr	x9, [x9]
Lloh13:
	adrp	x10, _chipModel_GC420@GOTPAGE
Lloh14:
	ldr	x10, [x10, _chipModel_GC420@GOTPAGEOFF]
Lloh15:
	ldr	x10, [x10]
	cmp	x8, x9
	ccmp	x8, x10, #4, ge
	b.eq	LBB0_3
; %bb.1:
	ldr	w8, [x19, #16]
Lloh16:
	adrp	x9, _chipMinorFeatures3_BUG_FIXES12@GOTPAGE
Lloh17:
	ldr	x9, [x9, _chipMinorFeatures3_BUG_FIXES12@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_3
; %bb.2:
Lloh19:
	adrp	x8, _VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA@GOTPAGE
Lloh20:
	ldr	x8, [x8, _VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
	orr	w20, w8, w20
LBB0_3:
	ldr	w8, [x19]
	cmp	w8, #5, lsl #12                 ; =20480
	b.ge	LBB0_7
; %bb.4:
	ldr	w8, [x19, #20]
Lloh22:
	adrp	x9, _chipMinorFeatures0_HZ@GOTPAGE
Lloh23:
	ldr	x9, [x9, _chipMinorFeatures0_HZ@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_8
; %bb.5:
	ldr	w8, [x19, #24]
Lloh25:
	adrp	x9, _chipMinorFeatures1_DISABLE_PE_GATING@GOTPAGE
Lloh26:
	ldr	x9, [x9, _chipMinorFeatures1_DISABLE_PE_GATING@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_8
; %bb.6:
Lloh28:
	adrp	x8, _VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE@GOTPAGE
Lloh29:
	ldr	x8, [x8, _VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE@GOTPAGEOFF]
Lloh30:
	ldr	w8, [x8]
	orr	w20, w8, w20
	b	LBB0_8
LBB0_7:
	mov	w9, #21537
	cmp	w8, w9
	b.hi	LBB0_9
LBB0_8:
	mov	w0, #15
	bl	_BIT
	orr	w20, w0, w20
LBB0_9:
Lloh31:
	adrp	x8, _GC4000@GOTPAGE
Lloh32:
	ldr	x8, [x8, _GC4000@GOTPAGEOFF]
Lloh33:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #21026
	bl	_etnaviv_is_model_rev
	cbnz	x0, LBB0_11
; %bb.10:
Lloh34:
	adrp	x8, _GC2000@GOTPAGE
Lloh35:
	ldr	x8, [x8, _GC2000@GOTPAGEOFF]
Lloh36:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #20744
	bl	_etnaviv_is_model_rev
	cbz	x0, LBB0_12
LBB0_11:
Lloh37:
	adrp	x8, _VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX@GOTPAGE
Lloh38:
	ldr	x8, [x8, _VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
	orr	w20, w8, w20
LBB0_12:
Lloh40:
	adrp	x8, _VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ@GOTPAGE
Lloh41:
	ldr	x8, [x8, _VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ@GOTPAGEOFF]
Lloh42:
	ldr	w8, [x8]
	orr	w8, w8, w20
Lloh43:
	adrp	x9, _VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ@GOTPAGE
Lloh44:
	ldr	x9, [x9, _VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ@GOTPAGEOFF]
Lloh45:
	ldr	w9, [x9]
	orr	w2, w8, w9
	ldr	w1, [x21]
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_gpu_write
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.cfi_endproc
                                        ; -- End function
	.comm	_VIVS_PM_POWER_CONTROLS,4,2     ; @VIVS_PM_POWER_CONTROLS
	.comm	_VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING,4,2 ; @VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING
	.comm	_VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING,4,2 ; @VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING
	.comm	_VIVS_PM_MODULE_CONTROLS,4,2    ; @VIVS_PM_MODULE_CONTROLS
	.comm	_chipModel_GC400,8,3            ; @chipModel_GC400
	.comm	_chipModel_GC420,8,3            ; @chipModel_GC420
	.comm	_chipMinorFeatures3_BUG_FIXES12,4,2 ; @chipMinorFeatures3_BUG_FIXES12
	.comm	_VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA,4,2 ; @VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA
	.comm	_chipMinorFeatures0_HZ,4,2      ; @chipMinorFeatures0_HZ
	.comm	_chipMinorFeatures1_DISABLE_PE_GATING,4,2 ; @chipMinorFeatures1_DISABLE_PE_GATING
	.comm	_VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE,4,2 ; @VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE
	.comm	_GC4000,4,2                     ; @GC4000
	.comm	_GC2000,4,2                     ; @GC2000
	.comm	_VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX,4,2 ; @VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX
	.comm	_VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ,4,2 ; @VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ
	.comm	_VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ,4,2 ; @VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ
	.no_dead_strip	_etnaviv_gpu_enable_mlcg
.subsections_via_symbols
