	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rs780_set_engine_clock_scaling
_rs780_set_engine_clock_scaling:        ## @rs780_set_engine_clock_scaling
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$72, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %rbx
	movq	%rdi, %r14
	movq	%rsi, %rdi
	callq	_rs780_get_ps
	movq	%rax, %r12
	movq	%rbx, %rdi
	callq	_rs780_get_ps
	movq	%rax, %r15
	movq	(%r12), %rax
	movq	8(%r12), %rdx
	cmpq	(%r15), %rax
	jne	LBB0_2
## %bb.1:
	xorl	%ebx, %ebx
	cmpq	8(%r15), %rdx
	je	LBB0_12
LBB0_2:
	movq	_COMPUTE_ENGINE_PLL_PARAM@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	leaq	-88(%rbp), %r8
	movq	%r14, %rdi
	xorl	%ecx, %ecx
	callq	_radeon_atom_get_clock_dividers
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_12
## %bb.3:
	movl	(%r13), %esi
	movq	(%r12), %rdx
	leaq	-64(%rbp), %r8
	movq	%r14, %rdi
	xorl	%ecx, %ecx
	callq	_radeon_atom_get_clock_dividers
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_12
## %bb.4:
	movl	(%r13), %esi
	movq	(%r15), %rdx
	leaq	-112(%rbp), %r8
	movq	%r14, %rdi
	xorl	%ecx, %ecx
	callq	_radeon_atom_get_clock_dividers
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_12
## %bb.5:
	movq	-88(%rbp), %rax
	cmpq	-64(%rbp), %rax
	jne	LBB0_9
## %bb.6:
	movq	-56(%rbp), %rcx
	cmpq	%rcx, -80(%rbp)
	jne	LBB0_9
## %bb.7:
	cmpq	-112(%rbp), %rax
	jne	LBB0_9
## %bb.8:
	cmpq	-104(%rbp), %rcx
	jne	LBB0_9
## %bb.10:
	movq	-48(%rbp), %rsi
	movq	%r14, %rdi
	callq	_rs780_force_fbdiv
	movq	-72(%rbp), %rdi
	xorl	%ebx, %ebx
	cmpq	%rdi, -48(%rbp)
	jle	LBB0_12
## %bb.11:
	movq	_FVTHROT_FBDIV_REG0@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	callq	_MIN_FEEDBACK_DIV
	movl	%eax, %ebx
	movq	-48(%rbp), %rdi
	callq	_MAX_FEEDBACK_DIV
	orl	%eax, %ebx
	movq	_MIN_FEEDBACK_DIV_MASK@GOTPCREL(%rip), %rax
	movq	_MAX_FEEDBACK_DIV_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	notl	%edx
	movl	%r14d, %edi
	movl	%ebx, %esi
	callq	_WREG32_P
	movq	_FVTHROT_FBDIV_REG1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_FORCE_FEEDBACK_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	xorl	%ebx, %ebx
	xorl	%esi, %esi
	callq	_WREG32_P
	jmp	LBB0_12
LBB0_9:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
LBB0_12:
	movl	%ebx, %eax
	addq	$72, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_COMPUTE_ENGINE_PLL_PARAM,4,2   ## @COMPUTE_ENGINE_PLL_PARAM
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_FVTHROT_FBDIV_REG0,4,2         ## @FVTHROT_FBDIV_REG0
	.comm	_MIN_FEEDBACK_DIV_MASK,4,2      ## @MIN_FEEDBACK_DIV_MASK
	.comm	_MAX_FEEDBACK_DIV_MASK,4,2      ## @MAX_FEEDBACK_DIV_MASK
	.comm	_FVTHROT_FBDIV_REG1,4,2         ## @FVTHROT_FBDIV_REG1
	.comm	_FORCE_FEEDBACK_DIV,4,2         ## @FORCE_FEEDBACK_DIV
	.no_dead_strip	_rs780_set_engine_clock_scaling
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rs780_set_engine_clock_scaling
_rs780_set_engine_clock_scaling:        ; @rs780_set_engine_clock_scaling
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #128
	.cfi_def_cfa_offset 128
	stp	x22, x21, [sp, #80]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #96]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #112]            ; 16-byte Folded Spill
	add	x29, sp, #112
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x2
	mov	x19, x0
	mov	x0, x1
	bl	_rs780_get_ps
	mov	x21, x0
	mov	x0, x20
	bl	_rs780_get_ps
	mov	x20, x0
	ldr	x8, [x0]
	ldp	x9, x2, [x21]
	cmp	x9, x8
	b.ne	LBB0_3
; %bb.1:
	ldr	x8, [x20, #8]
	cmp	x2, x8
	b.ne	LBB0_3
LBB0_2:
	mov	w0, #0
	b	LBB0_13
LBB0_3:
Lloh0:
	adrp	x22, _COMPUTE_ENGINE_PLL_PARAM@GOTPAGE
Lloh1:
	ldr	x22, [x22, _COMPUTE_ENGINE_PLL_PARAM@GOTPAGEOFF]
	ldr	w1, [x22]
	add	x4, sp, #56
	mov	x0, x19
	mov	w3, #0
	bl	_radeon_atom_get_clock_dividers
	cbnz	w0, LBB0_13
; %bb.4:
	ldr	w1, [x22]
	ldr	x2, [x21]
	add	x4, sp, #32
	mov	x0, x19
	mov	w3, #0
	bl	_radeon_atom_get_clock_dividers
	cbnz	w0, LBB0_13
; %bb.5:
	ldr	w1, [x22]
	ldr	x2, [x20]
	add	x4, sp, #8
	mov	x0, x19
	mov	w3, #0
	bl	_radeon_atom_get_clock_dividers
	cbnz	w0, LBB0_13
; %bb.6:
	ldr	x8, [sp, #56]
	ldr	x9, [sp, #32]
	cmp	x8, x9
	b.ne	LBB0_12
; %bb.7:
	ldr	x10, [sp, #64]
	ldr	x9, [sp, #40]
	cmp	x10, x9
	b.ne	LBB0_12
; %bb.8:
	ldr	x10, [sp, #8]
	cmp	x8, x10
	b.ne	LBB0_12
; %bb.9:
	ldr	x8, [sp, #16]
	cmp	x9, x8
	b.ne	LBB0_12
; %bb.10:
	ldr	x1, [sp, #48]
	mov	x0, x19
	bl	_rs780_force_fbdiv
	ldr	x8, [sp, #48]
	ldr	x0, [sp, #72]
	cmp	x8, x0
	b.le	LBB0_2
; %bb.11:
Lloh2:
	adrp	x8, _FVTHROT_FBDIV_REG0@GOTPAGE
Lloh3:
	ldr	x8, [x8, _FVTHROT_FBDIV_REG0@GOTPAGEOFF]
Lloh4:
	ldr	w19, [x8]
	bl	_MIN_FEEDBACK_DIV
	mov	x20, x0
	ldr	x0, [sp, #48]
	bl	_MAX_FEEDBACK_DIV
	orr	w1, w0, w20
Lloh5:
	adrp	x8, _MIN_FEEDBACK_DIV_MASK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _MIN_FEEDBACK_DIV_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
Lloh8:
	adrp	x9, _MAX_FEEDBACK_DIV_MASK@GOTPAGE
Lloh9:
	ldr	x9, [x9, _MAX_FEEDBACK_DIV_MASK@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
	orr	w8, w9, w8
	mvn	w2, w8
	mov	x0, x19
	bl	_WREG32_P
Lloh11:
	adrp	x8, _FVTHROT_FBDIV_REG1@GOTPAGE
Lloh12:
	ldr	x8, [x8, _FVTHROT_FBDIV_REG1@GOTPAGEOFF]
Lloh13:
	ldr	w0, [x8]
Lloh14:
	adrp	x8, _FORCE_FEEDBACK_DIV@GOTPAGE
Lloh15:
	ldr	x8, [x8, _FORCE_FEEDBACK_DIV@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	b	LBB0_2
LBB0_12:
Lloh17:
	adrp	x8, _EINVAL@GOTPAGE
Lloh18:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_13:
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	add	sp, sp, #128
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.cfi_endproc
                                        ; -- End function
	.comm	_COMPUTE_ENGINE_PLL_PARAM,4,2   ; @COMPUTE_ENGINE_PLL_PARAM
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_FVTHROT_FBDIV_REG0,4,2         ; @FVTHROT_FBDIV_REG0
	.comm	_MIN_FEEDBACK_DIV_MASK,4,2      ; @MIN_FEEDBACK_DIV_MASK
	.comm	_MAX_FEEDBACK_DIV_MASK,4,2      ; @MAX_FEEDBACK_DIV_MASK
	.comm	_FVTHROT_FBDIV_REG1,4,2         ; @FVTHROT_FBDIV_REG1
	.comm	_FORCE_FEEDBACK_DIV,4,2         ; @FORCE_FEEDBACK_DIV
	.no_dead_strip	_rs780_set_engine_clock_scaling
.subsections_via_symbols
