	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function meson_plane_atomic_disable
_meson_plane_atomic_disable:            ## @meson_plane_atomic_disable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	callq	_to_meson_plane
	movq	%rax, %r14
	movq	8(%rax), %r12
	movq	_VPU_COMPATIBLE_G12A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_meson_vpu_is_compatible
	testq	%rax, %rax
	movq	_VIU_OSD1_POSTBLD_SRC_OSD1@GOTPCREL(%rip), %rax
	cmoveq	_VPP_OSD1_POSTBLEND@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	8(%r12), %rbx
	movq	_OSD1_BLEND_SRC_CTRL@GOTPCREL(%rip), %rax
	cmoveq	_VPP_MISC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	__REG
	addq	%rax, %rbx
	movl	%r15d, %edi
	xorl	%esi, %esi
	movq	%rbx, %rdx
	callq	_writel_bits_relaxed
	movl	$0, (%r14)
	movl	$0, (%r12)
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_VPU_COMPATIBLE_G12A,4,2        ## @VPU_COMPATIBLE_G12A
	.comm	_VIU_OSD1_POSTBLD_SRC_OSD1,4,2  ## @VIU_OSD1_POSTBLD_SRC_OSD1
	.comm	_OSD1_BLEND_SRC_CTRL,4,2        ## @OSD1_BLEND_SRC_CTRL
	.comm	_VPP_OSD1_POSTBLEND,4,2         ## @VPP_OSD1_POSTBLEND
	.comm	_VPP_MISC,4,2                   ## @VPP_MISC
	.no_dead_strip	_meson_plane_atomic_disable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function meson_plane_atomic_disable
_meson_plane_atomic_disable:            ; @meson_plane_atomic_disable
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	bl	_to_meson_plane
	mov	x19, x0
	ldr	x20, [x0, #8]
Lloh0:
	adrp	x8, _VPU_COMPATIBLE_G12A@GOTPAGE
Lloh1:
	ldr	x8, [x8, _VPU_COMPATIBLE_G12A@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_meson_vpu_is_compatible
Lloh3:
	adrp	x8, _VPP_OSD1_POSTBLEND@GOTPAGE
Lloh4:
	ldr	x8, [x8, _VPP_OSD1_POSTBLEND@GOTPAGEOFF]
Lloh5:
	adrp	x9, _VIU_OSD1_POSTBLD_SRC_OSD1@GOTPAGE
Lloh6:
	ldr	x9, [x9, _VIU_OSD1_POSTBLD_SRC_OSD1@GOTPAGEOFF]
	cmp	x0, #0
	csel	x8, x8, x9, eq
	ldr	w21, [x8]
	ldr	x22, [x20, #8]
Lloh7:
	adrp	x8, _VPP_MISC@GOTPAGE
Lloh8:
	ldr	x8, [x8, _VPP_MISC@GOTPAGEOFF]
Lloh9:
	adrp	x9, _OSD1_BLEND_SRC_CTRL@GOTPAGE
Lloh10:
	ldr	x9, [x9, _OSD1_BLEND_SRC_CTRL@GOTPAGEOFF]
	csel	x8, x8, x9, eq
	ldr	w0, [x8]
	bl	__REG
	add	x2, x0, x22
	mov	x0, x21
	mov	w1, #0
	bl	_writel_bits_relaxed
	str	wzr, [x19]
	str	wzr, [x20]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_VPU_COMPATIBLE_G12A,4,2        ; @VPU_COMPATIBLE_G12A
	.comm	_VIU_OSD1_POSTBLD_SRC_OSD1,4,2  ; @VIU_OSD1_POSTBLD_SRC_OSD1
	.comm	_OSD1_BLEND_SRC_CTRL,4,2        ; @OSD1_BLEND_SRC_CTRL
	.comm	_VPP_OSD1_POSTBLEND,4,2         ; @VPP_OSD1_POSTBLEND
	.comm	_VPP_MISC,4,2                   ; @VPP_MISC
	.no_dead_strip	_meson_plane_atomic_disable
.subsections_via_symbols
