	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function socfpga_a10_fpga_write_init
_socfpga_a10_fpga_write_init:           ## @socfpga_a10_fpga_write_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_FPGA_MGR_PARTIAL_RECONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rsi)
	je	LBB0_4
## %bb.1:
	movq	%rcx, %r15
	movq	%rdx, %r12
	movq	%rdi, %rbx
	movq	8(%rdi), %r14
	movq	_CFGWDTH_16@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	%r14, %rdi
	callq	_socfpga_a10_fpga_read_stat
	movq	_A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	cmpl	$2, %eax
	jae	LBB0_2
## %bb.3:
	movq	%r14, %rdi
	callq	_socfpga_a10_fpga_read_stat
	movq	_A10_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN@GOTPCREL(%rip), %rcx
	movq	_A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	notl	%eax
	testl	%eax, %edx
	jne	LBB0_4
## %bb.5:
	movq	%r14, %rdi
	movl	%r13d, %esi
	callq	_socfpga_a10_fpga_set_cfg_width
	movq	%rbx, %rdi
	movl	%r13d, %esi
	movq	%r12, %rdx
	movq	%r15, %rcx
	callq	_socfpga_a10_fpga_set_cdratio
	testl	%eax, %eax
	jne	LBB0_6
## %bb.7:
	movl	(%r14), %edi
	movq	_A10_FPGAMGR_IMGCFG_CTL_01_OFST@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	callq	_regmap_write
	movl	(%r14), %edi
	movq	_A10_FPGAMGR_IMGCFG_CTL_02_OFST@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r14), %edi
	movq	_A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG@GOTPCREL(%rip), %rax
	movq	_A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	_A10_FPGAMGR_IMGCFG_CTL_00_OFST@GOTPCREL(%rip), %rax
	movq	_A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movl	(%rax), %esi
	movq	_A10_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	callq	_regmap_write
	movl	(%r14), %edi
	movl	(%rbx), %esi
	movl	(%r15), %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movq	%r14, %rdi
	movl	$256, %esi                      ## imm = 0x100
	callq	_socfpga_a10_fpga_generate_dclks
	movl	(%r14), %edi
	movl	(%rbx), %esi
	movq	_A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movq	%r14, %rdi
	movl	$2047, %esi                     ## imm = 0x7FF
	callq	_socfpga_a10_fpga_generate_dclks
	movq	%r14, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_socfpga_a10_fpga_wait_for_pr_ready ## TAILCALL
LBB0_2:
	leaq	L_.str(%rip), %rsi
	movq	%rbx, %rdi
	movl	%eax, %edx
	callq	_dev_dbg
LBB0_4:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_6:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_FPGA_MGR_PARTIAL_RECONFIG,4,2  ## @FPGA_MGR_PARTIAL_RECONFIG
	.comm	_CFGWDTH_16,4,2                 ## @CFGWDTH_16
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_MASK,4,2 ## @A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_MASK
	.comm	_A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SHIFT,4,2 ## @A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SHIFT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Fail: invalid msel=%d\n"

	.comm	_A10_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN,4,2 ## @A10_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN
	.comm	_A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN,4,2 ## @A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN
	.comm	_A10_FPGAMGR_IMGCFG_CTL_01_OFST,4,2 ## @A10_FPGAMGR_IMGCFG_CTL_01_OFST
	.comm	_A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG,4,2 ## @A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG
	.comm	_A10_FPGAMGR_IMGCFG_CTL_02_OFST,4,2 ## @A10_FPGAMGR_IMGCFG_CTL_02_OFST
	.comm	_A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL,4,2 ## @A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL
	.comm	_A10_FPGAMGR_IMGCFG_CTL_00_OFST,4,2 ## @A10_FPGAMGR_IMGCFG_CTL_00_OFST
	.comm	_A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG,4,2 ## @A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG
	.comm	_A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS,4,2 ## @A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS
	.comm	_A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE,4,2 ## @A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE
	.comm	_A10_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG,4,2 ## @A10_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG
	.comm	_A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST,4,2 ## @A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST
	.no_dead_strip	_socfpga_a10_fpga_write_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function socfpga_a10_fpga_write_init
_socfpga_a10_fpga_write_init:           ; @socfpga_a10_fpga_write_init
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	ldr	w8, [x1]
Lloh0:
	adrp	x9, _FPGA_MGR_PARTIAL_RECONFIG@GOTPAGE
Lloh1:
	ldr	x9, [x9, _FPGA_MGR_PARTIAL_RECONFIG@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_6
; %bb.1:
	mov	x20, x3
	mov	x22, x2
	mov	x21, x0
	ldr	x19, [x0, #8]
Lloh3:
	adrp	x8, _CFGWDTH_16@GOTPAGE
Lloh4:
	ldr	x8, [x8, _CFGWDTH_16@GOTPAGEOFF]
Lloh5:
	ldr	w23, [x8]
	mov	x0, x19
	bl	_socfpga_a10_fpga_read_stat
Lloh6:
	adrp	x8, _A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_MASK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh9:
	adrp	x9, _A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SHIFT@GOTPAGE
Lloh10:
	ldr	x9, [x9, _A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SHIFT@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	asr	w2, w8, w9
	cmp	w2, #2
	b.hs	LBB0_5
; %bb.2:
	mov	x0, x19
	bl	_socfpga_a10_fpga_read_stat
Lloh12:
	adrp	x8, _A10_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN@GOTPAGE
Lloh13:
	ldr	x8, [x8, _A10_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
Lloh15:
	adrp	x9, _A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN@GOTPAGE
Lloh16:
	ldr	x9, [x9, _A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bics	wzr, w8, w0
	b.ne	LBB0_6
; %bb.3:
	mov	x0, x19
	mov	x1, x23
	bl	_socfpga_a10_fpga_set_cfg_width
	mov	x0, x21
	mov	x1, x23
	mov	x2, x22
	mov	x3, x20
	bl	_socfpga_a10_fpga_set_cdratio
	cbnz	w0, LBB0_7
; %bb.4:
	ldr	w0, [x19]
Lloh18:
	adrp	x20, _A10_FPGAMGR_IMGCFG_CTL_01_OFST@GOTPAGE
Lloh19:
	ldr	x20, [x20, _A10_FPGAMGR_IMGCFG_CTL_01_OFST@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh20:
	adrp	x21, _A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG@GOTPAGE
Lloh21:
	ldr	x21, [x21, _A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG@GOTPAGEOFF]
	ldr	w2, [x21]
	bl	_regmap_write
	ldr	w0, [x19]
Lloh22:
	adrp	x8, _A10_FPGAMGR_IMGCFG_CTL_02_OFST@GOTPAGE
Lloh23:
	ldr	x8, [x8, _A10_FPGAMGR_IMGCFG_CTL_02_OFST@GOTPAGEOFF]
Lloh24:
	ldr	w1, [x8]
Lloh25:
	adrp	x8, _A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL@GOTPAGE
Lloh26:
	ldr	x8, [x8, _A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL@GOTPAGEOFF]
Lloh27:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
Lloh28:
	adrp	x8, _A10_FPGAMGR_IMGCFG_CTL_00_OFST@GOTPAGE
Lloh29:
	ldr	x8, [x8, _A10_FPGAMGR_IMGCFG_CTL_00_OFST@GOTPAGEOFF]
Lloh30:
	ldr	w1, [x8]
Lloh31:
	adrp	x8, _A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG@GOTPAGE
Lloh32:
	ldr	x8, [x8, _A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
Lloh34:
	adrp	x9, _A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS@GOTPAGE
Lloh35:
	ldr	x9, [x9, _A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS@GOTPAGEOFF]
Lloh36:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh37:
	adrp	x9, _A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE@GOTPAGE
Lloh38:
	ldr	x9, [x9, _A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE@GOTPAGEOFF]
Lloh39:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh40:
	adrp	x9, _A10_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG@GOTPAGE
Lloh41:
	ldr	x9, [x9, _A10_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG@GOTPAGEOFF]
Lloh42:
	ldr	w9, [x9]
	orr	w2, w8, w9
	bl	_regmap_write
	ldr	w0, [x19]
	ldr	w1, [x20]
	ldr	w2, [x21]
	mov	w3, #0
	bl	_regmap_update_bits
	mov	x0, x19
	mov	w1, #256
	bl	_socfpga_a10_fpga_generate_dclks
	ldr	w0, [x19]
	ldr	w1, [x20]
Lloh43:
	adrp	x8, _A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST@GOTPAGE
Lloh44:
	ldr	x8, [x8, _A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST@GOTPAGEOFF]
Lloh45:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	mov	x0, x19
	mov	w1, #2047
	bl	_socfpga_a10_fpga_generate_dclks
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_socfpga_a10_fpga_wait_for_pr_ready
LBB0_5:
Lloh46:
	adrp	x1, l_.str@PAGE
Lloh47:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x21
	bl	_dev_dbg
LBB0_6:
Lloh48:
	adrp	x8, _EINVAL@GOTPAGE
Lloh49:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh50:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_7:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpAdd	Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.cfi_endproc
                                        ; -- End function
	.comm	_FPGA_MGR_PARTIAL_RECONFIG,4,2  ; @FPGA_MGR_PARTIAL_RECONFIG
	.comm	_CFGWDTH_16,4,2                 ; @CFGWDTH_16
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_MASK,4,2 ; @A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_MASK
	.comm	_A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SHIFT,4,2 ; @A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SHIFT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Fail: invalid msel=%d\n"

	.comm	_A10_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN,4,2 ; @A10_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN
	.comm	_A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN,4,2 ; @A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN
	.comm	_A10_FPGAMGR_IMGCFG_CTL_01_OFST,4,2 ; @A10_FPGAMGR_IMGCFG_CTL_01_OFST
	.comm	_A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG,4,2 ; @A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG
	.comm	_A10_FPGAMGR_IMGCFG_CTL_02_OFST,4,2 ; @A10_FPGAMGR_IMGCFG_CTL_02_OFST
	.comm	_A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL,4,2 ; @A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL
	.comm	_A10_FPGAMGR_IMGCFG_CTL_00_OFST,4,2 ; @A10_FPGAMGR_IMGCFG_CTL_00_OFST
	.comm	_A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG,4,2 ; @A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG
	.comm	_A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS,4,2 ; @A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS
	.comm	_A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE,4,2 ; @A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE
	.comm	_A10_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG,4,2 ; @A10_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG
	.comm	_A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST,4,2 ; @A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST
	.no_dead_strip	_socfpga_a10_fpga_write_init
.subsections_via_symbols
