	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function si_notify_link_speed_change_after_state_change
_si_notify_link_speed_change_after_state_change: ## @si_notify_link_speed_change_after_state_change
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r15
	movq	%rdi, %r14
	callq	_si_get_pi
	movq	%rax, %rbx
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	_si_get_maximum_link_speed
	cmpq	$0, (%rbx)
	je	LBB0_6
## %bb.1:
	movq	_AMDGPU_PCIE_GEN3@GOTPCREL(%rip), %rdx
	movq	_AMDGPU_PCIE_GEN2@GOTPCREL(%rip), %rdi
	movq	_PCIE_PERF_REQ_PECI_GEN1@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, %rsi
	cmpl	(%rdi), %eax
	je	LBB0_2
## %bb.3:
	cmpl	(%rdx), %eax
	je	LBB0_4
LBB0_5:
	cmpq	%rcx, %rsi
	jne	LBB0_6
LBB0_7:
	movq	%r14, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_si_get_current_pcie_speed      ## TAILCALL
LBB0_2:
	movq	_PCIE_PERF_REQ_PECI_GEN2@GOTPCREL(%rip), %rsi
	movq	(%rsi), %rsi
	cmpl	(%rdx), %eax
	jne	LBB0_5
LBB0_4:
	movq	_PCIE_PERF_REQ_PECI_GEN3@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	cmpq	%rcx, %rsi
	je	LBB0_7
LBB0_6:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_PCIE_GEN3,4,2           ## @AMDGPU_PCIE_GEN3
	.comm	_PCIE_PERF_REQ_PECI_GEN3,8,3    ## @PCIE_PERF_REQ_PECI_GEN3
	.comm	_AMDGPU_PCIE_GEN2,4,2           ## @AMDGPU_PCIE_GEN2
	.comm	_PCIE_PERF_REQ_PECI_GEN2,8,3    ## @PCIE_PERF_REQ_PECI_GEN2
	.comm	_PCIE_PERF_REQ_PECI_GEN1,8,3    ## @PCIE_PERF_REQ_PECI_GEN1
	.no_dead_strip	_si_notify_link_speed_change_after_state_change
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function si_notify_link_speed_change_after_state_change
_si_notify_link_speed_change_after_state_change: ; @si_notify_link_speed_change_after_state_change
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	mov	x19, x0
	bl	_si_get_pi
	mov	x21, x0
	mov	x0, x19
	mov	x1, x20
	bl	_si_get_maximum_link_speed
	ldr	x8, [x21]
	cbz	x8, LBB0_3
; %bb.1:
Lloh0:
	adrp	x8, _AMDGPU_PCIE_GEN3@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AMDGPU_PCIE_GEN3@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _AMDGPU_PCIE_GEN2@GOTPAGE
Lloh4:
	ldr	x9, [x9, _AMDGPU_PCIE_GEN2@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
Lloh6:
	adrp	x10, _PCIE_PERF_REQ_PECI_GEN3@GOTPAGE
Lloh7:
	ldr	x10, [x10, _PCIE_PERF_REQ_PECI_GEN3@GOTPAGEOFF]
Lloh8:
	ldr	x10, [x10]
Lloh9:
	adrp	x11, _PCIE_PERF_REQ_PECI_GEN2@GOTPAGE
Lloh10:
	ldr	x11, [x11, _PCIE_PERF_REQ_PECI_GEN2@GOTPAGEOFF]
Lloh11:
	ldr	x11, [x11]
Lloh12:
	adrp	x12, _PCIE_PERF_REQ_PECI_GEN1@GOTPAGE
Lloh13:
	ldr	x12, [x12, _PCIE_PERF_REQ_PECI_GEN1@GOTPAGEOFF]
Lloh14:
	ldr	x12, [x12]
	cmp	w0, w9
	csel	x9, x11, x12, eq
	cmp	w0, w8
	csel	x8, x10, x9, eq
	cmp	x8, x12
	b.ne	LBB0_3
; %bb.2:
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_si_get_current_pcie_speed
LBB0_3:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_PCIE_GEN3,4,2           ; @AMDGPU_PCIE_GEN3
	.comm	_PCIE_PERF_REQ_PECI_GEN3,8,3    ; @PCIE_PERF_REQ_PECI_GEN3
	.comm	_AMDGPU_PCIE_GEN2,4,2           ; @AMDGPU_PCIE_GEN2
	.comm	_PCIE_PERF_REQ_PECI_GEN2,8,3    ; @PCIE_PERF_REQ_PECI_GEN2
	.comm	_PCIE_PERF_REQ_PECI_GEN1,8,3    ; @PCIE_PERF_REQ_PECI_GEN1
	.no_dead_strip	_si_notify_link_speed_change_after_state_change
.subsections_via_symbols
