	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_dcn20_clk_mgr_construct        ## -- Begin function dcn20_clk_mgr_construct
	.p2align	4, 0x90
_dcn20_clk_mgr_construct:               ## @dcn20_clk_mgr_construct
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %rbx
	movq	%rdi, 32(%rsi)
	movq	%rdx, 88(%rsi)
	movq	_dcn2_funcs@GOTPCREL(%rip), %r14
	movq	%r14, 24(%rsi)
	movq	_clk_mgr_regs@GOTPCREL(%rip), %rax
	movq	%rax, 80(%rsi)
	movq	_clk_mgr_shift@GOTPCREL(%rip), %rax
	movq	%rax, 72(%rsi)
	movq	_clk_mgr_mask@GOTPCREL(%rip), %rax
	movq	%rax, 40(%rsi)
	movq	%rcx, 64(%rsi)
	xorps	%xmm0, %xmm0
	movups	%xmm0, 48(%rsi)
	movq	$1000, (%rsi)                   ## imm = 0x3E8
	movl	$700000, 16(%rsi)               ## imm = 0xAAE60
	movl	(%rdi), %edi
	callq	_IS_FPGA_MAXIMUS_DC
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	_dcn2_update_clocks_fpga@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, (%r14)
	movl	$3850000, %ecx                  ## imm = 0x3ABF10
	jmp	LBB0_3
LBB0_2:
	movq	_CLK3_CLK2_DFS_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_REG_READ
	movl	%eax, %edi
	callq	_dentist_get_divider_from_did
	movl	%eax, %r14d
	movq	_CLK3_CLK_PLL_REQ@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_REG_READ
	movq	%rax, %r15
	movq	40(%rbx), %rax
	movl	(%rax), %edi
	andl	%r15d, %edi
	callq	_dc_fixpt_from_int
	movq	40(%rbx), %rcx
	andl	4(%rcx), %r15d
	orl	%eax, %r15d
	movl	%r15d, %edi
	movl	$100000, %esi                   ## imm = 0x186A0
	callq	_dc_fixpt_mul_int
	movl	%eax, %edi
	callq	_dc_fixpt_floor
	testl	%eax, %eax
	movl	$3850000, %ecx                  ## imm = 0x3ABF10
	cmovnel	%eax, %ecx
	movq	_DENTIST_DIVIDER_RANGE_SCALE_FACTOR@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	imull	%ecx, %eax
	cltd
	idivl	%r14d
	movl	%eax, 16(%rbx)
LBB0_3:
	movl	%ecx, 8(%rbx)
	movl	$0, 12(%rbx)
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_dce_clock_read_ss_info         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_dcn2_funcs,4,2                 ## @dcn2_funcs
	.comm	_clk_mgr_regs,4,2               ## @clk_mgr_regs
	.comm	_clk_mgr_shift,4,2              ## @clk_mgr_shift
	.comm	_clk_mgr_mask,8,2               ## @clk_mgr_mask
	.comm	_dcn2_update_clocks_fpga,4,2    ## @dcn2_update_clocks_fpga
	.comm	_CLK3_CLK2_DFS_CNTL,4,2         ## @CLK3_CLK2_DFS_CNTL
	.comm	_CLK3_CLK_PLL_REQ,4,2           ## @CLK3_CLK_PLL_REQ
	.comm	_DENTIST_DIVIDER_RANGE_SCALE_FACTOR,4,2 ## @DENTIST_DIVIDER_RANGE_SCALE_FACTOR
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3                               ; -- Begin function dcn20_clk_mgr_construct
lCPI0_0:
	.long	1000                            ; 0x3e8
	.long	0                               ; 0x0
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_dcn20_clk_mgr_construct
	.p2align	2
_dcn20_clk_mgr_construct:               ; @dcn20_clk_mgr_construct
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x1
	mov	w22, #48912
	movk	w22, #58, lsl #16
	str	x2, [x1, #88]
Lloh0:
	adrp	x20, _dcn2_funcs@GOTPAGE
Lloh1:
	ldr	x20, [x20, _dcn2_funcs@GOTPAGEOFF]
	stp	x20, x0, [x1, #24]
Lloh2:
	adrp	x8, _clk_mgr_regs@GOTPAGE
Lloh3:
	ldr	x8, [x8, _clk_mgr_regs@GOTPAGEOFF]
Lloh4:
	adrp	x9, _clk_mgr_shift@GOTPAGE
Lloh5:
	ldr	x9, [x9, _clk_mgr_shift@GOTPAGEOFF]
	stp	x9, x8, [x1, #72]
Lloh6:
	adrp	x8, _clk_mgr_mask@GOTPAGE
Lloh7:
	ldr	x8, [x8, _clk_mgr_mask@GOTPAGEOFF]
	stp	xzr, x3, [x1, #56]
	stp	x8, xzr, [x1, #40]
Lloh8:
	adrp	x8, lCPI0_0@PAGE
Lloh9:
	ldr	d0, [x8, lCPI0_0@PAGEOFF]
	str	d0, [x1]
	mov	w8, #44640
	movk	w8, #10, lsl #16
	str	w8, [x1, #16]
	ldr	w0, [x0]
	bl	_IS_FPGA_MAXIMUS_DC
	cbz	x0, LBB0_2
; %bb.1:
Lloh10:
	adrp	x8, _dcn2_update_clocks_fpga@GOTPAGE
Lloh11:
	ldr	x8, [x8, _dcn2_update_clocks_fpga@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	str	w8, [x20]
	b	LBB0_3
LBB0_2:
Lloh13:
	adrp	x8, _CLK3_CLK2_DFS_CNTL@GOTPAGE
Lloh14:
	ldr	x8, [x8, _CLK3_CLK2_DFS_CNTL@GOTPAGEOFF]
Lloh15:
	ldr	w0, [x8]
	bl	_REG_READ
                                        ; kill: def $w0 killed $w0 killed $x0
	bl	_dentist_get_divider_from_did
	mov	x20, x0
Lloh16:
	adrp	x8, _CLK3_CLK_PLL_REQ@GOTPAGE
Lloh17:
	ldr	x8, [x8, _CLK3_CLK_PLL_REQ@GOTPAGEOFF]
Lloh18:
	ldr	w0, [x8]
	bl	_REG_READ
	mov	x21, x0
	ldr	x8, [x19, #40]
	ldr	w8, [x8]
	and	w0, w8, w21
	bl	_dc_fixpt_from_int
	ldr	x8, [x19, #40]
	ldr	w8, [x8, #4]
	and	x8, x21, x8
	mov	w9, w0
	orr	x0, x8, x9
	mov	w1, #34464
	movk	w1, #1, lsl #16
	bl	_dc_fixpt_mul_int
	mov	w0, w0
	bl	_dc_fixpt_floor
	cmp	w0, #0
	csel	w22, w22, w0, eq
Lloh19:
	adrp	x8, _DENTIST_DIVIDER_RANGE_SCALE_FACTOR@GOTPAGE
Lloh20:
	ldr	x8, [x8, _DENTIST_DIVIDER_RANGE_SCALE_FACTOR@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
	mul	w8, w8, w22
	sdiv	w8, w8, w20
	str	w8, [x19, #16]
LBB0_3:
	stp	w22, wzr, [x19, #8]
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_dce_clock_read_ss_info
	.loh AdrpLdr	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.cfi_endproc
                                        ; -- End function
	.comm	_dcn2_funcs,4,2                 ; @dcn2_funcs
	.comm	_clk_mgr_regs,4,2               ; @clk_mgr_regs
	.comm	_clk_mgr_shift,4,2              ; @clk_mgr_shift
	.comm	_clk_mgr_mask,8,2               ; @clk_mgr_mask
	.comm	_dcn2_update_clocks_fpga,4,2    ; @dcn2_update_clocks_fpga
	.comm	_CLK3_CLK2_DFS_CNTL,4,2         ; @CLK3_CLK2_DFS_CNTL
	.comm	_CLK3_CLK_PLL_REQ,4,2           ; @CLK3_CLK_PLL_REQ
	.comm	_DENTIST_DIVIDER_RANGE_SCALE_FACTOR,4,2 ; @DENTIST_DIVIDER_RANGE_SCALE_FACTOR
.subsections_via_symbols
