	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function radeon_legacy_tv_dac_mode_set
_radeon_legacy_tv_dac_mode_set:         ## @radeon_legacy_tv_dac_mode_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, -88(%rbp)                 ## 8-byte Spill
	movq	%rsi, -80(%rbp)                 ## 8-byte Spill
	movq	%rdi, %r13
	movq	8(%rdi), %rax
	movq	(%rax), %r14
	movl	(%rdi), %edi
	callq	_to_radeon_crtc
	movq	%rax, -72(%rbp)                 ## 8-byte Spill
	movq	%r13, %rdi
	callq	_to_radeon_encoder
	movq	%rax, %rbx
	movq	8(%rax), %r15
	leaq	L_.str(%rip), %rdi
	callq	_DRM_DEBUG_KMS
	movq	_ATOM_DEVICE_TV_SUPPORT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%rbx), %eax
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	movq	(%r14), %rax
	movq	_CHIP_R200@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_13
## %bb.1:
	movq	_RADEON_TV_DAC_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_RREG32
	movq	(%r14), %rdx
	movq	_CHIP_R420@GOTPCREL(%rip), %rsi
	movq	_RADEON_TV_DAC_STD_MASK@GOTPCREL(%rip), %rdi
	movq	_RADEON_TV_DAC_BGADJ_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rdi), %ecx
	cmpq	(%rsi), %rdx
	je	LBB0_5
## %bb.2:
	movq	_CHIP_R423@GOTPCREL(%rip), %rsi
	cmpq	(%rsi), %rdx
	je	LBB0_5
## %bb.3:
	movq	_CHIP_RV410@GOTPCREL(%rip), %rsi
	cmpq	(%rsi), %rdx
	je	LBB0_5
## %bb.4:
	movq	_RADEON_TV_DAC_BDACPD@GOTPCREL(%rip), %rdx
	movq	_RADEON_TV_DAC_GDACPD@GOTPCREL(%rip), %rsi
	movq	_RADEON_TV_DAC_RDACPD@GOTPCREL(%rip), %rdi
	movq	_RADEON_TV_DAC_DACADJ_MASK@GOTPCREL(%rip), %rbx
	jmp	LBB0_6
LBB0_5:
	movq	_R420_TV_DAC_DACADJ_MASK@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_R420_TV_DAC_TVENABLE@GOTPCREL(%rip), %rdx
	movq	_R420_TV_DAC_BDACPD@GOTPCREL(%rip), %rsi
	movq	_R420_TV_DAC_GDACPD@GOTPCREL(%rip), %rdi
	movq	_R420_TV_DAC_RDACPD@GOTPCREL(%rip), %rbx
LBB0_6:
	orl	(%rbx), %ecx
	orl	(%rdi), %ecx
	orl	(%rsi), %ecx
	orl	(%rdx), %ecx
	notl	%ecx
	andl	%ecx, %eax
	movq	_RADEON_TV_DAC_NBLANK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RADEON_TV_DAC_NHOLD@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	cmpl	$0, -56(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_9
## %bb.7:
	movq	(%r15), %rcx
	movq	_TV_STD_NTSC@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	sete	%dl
	movq	_TV_STD_NTSC_J@GOTPCREL(%rip), %rsi
	cmpq	(%rsi), %rcx
	sete	%bl
	orb	%dl, %bl
	movl	%ebx, %edx
	movq	_TV_STD_PAL_M@GOTPCREL(%rip), %rsi
	cmpq	(%rsi), %rcx
	setne	%sil
	movq	_TV_STD_PAL_60@GOTPCREL(%rip), %rdi
	cmpq	(%rdi), %rcx
	notb	%dl
	setne	%cl
	andb	%sil, %cl
	andb	%dl, %cl
	movzbl	%cl, %ecx
	orl	8(%r15,%rcx,4), %eax
	cmpb	$1, %bl
	jne	LBB0_10
## %bb.8:
	movq	_RADEON_TV_DAC_STD_NTSC@GOTPCREL(%rip), %rcx
	jmp	LBB0_11
LBB0_9:
	movq	_RADEON_TV_DAC_STD_PS2@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	orl	16(%r15), %eax
	jmp	LBB0_12
LBB0_10:
	movq	_RADEON_TV_DAC_STD_PAL@GOTPCREL(%rip), %rcx
LBB0_11:
	orl	(%rcx), %eax
LBB0_12:
	movl	(%r12), %edi
	movl	%eax, %esi
	callq	_WREG32
LBB0_13:
	movq	%r14, %rdi
	callq	_ASIC_IS_R300
	testq	%rax, %rax
	movq	%r13, -64(%rbp)                 ## 8-byte Spill
	je	LBB0_15
## %bb.14:
	movq	_RADEON_GPIOPAD_A@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r13d
	orl	$1, %r13d
	movq	_RADEON_DISP_OUTPUT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r12d
	movl	$0, -44(%rbp)                   ## 4-byte Folded Spill
	jmp	LBB0_18
LBB0_15:
	movq	(%r14), %rax
	movq	_CHIP_R200@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_17
## %bb.16:
	movq	_RADEON_FP2_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	xorl	%r13d, %r13d
	xorl	%r12d, %r12d
	movl	$0, -44(%rbp)                   ## 4-byte Folded Spill
	jmp	LBB0_19
LBB0_17:
	movq	_RADEON_DISP_HW_DEBUG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	xorl	%r13d, %r13d
	xorl	%r12d, %r12d
LBB0_18:
	movl	$0, -48(%rbp)                   ## 4-byte Folded Spill
LBB0_19:
	movq	(%r14), %rdx
	xorl	%eax, %eax
	movq	_CHIP_R200@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rdx
	jl	LBB0_21
## %bb.20:
	movq	_RADEON_DISP_TV_OUT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
LBB0_21:
	cmpl	$0, -56(%rbp)                   ## 4-byte Folded Reload
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	je	LBB0_29
## %bb.22:
	movq	_RADEON_DAC_CNTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movq	_RADEON_DAC_TVO_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edi
	callq	_WREG32
	movq	%r14, %rdi
	callq	_ASIC_IS_R300
	testq	%rax, %rax
	je	LBB0_24
## %bb.23:
	movq	_RADEON_GPIOPAD_A@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r13d
	andl	$-2, %r13d
LBB0_24:
	movq	_RADEON_DAC_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_RADEON_DAC2_DAC2_CLK_SEL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r15d
	notl	%r15d
	andl	%eax, %r15d
	movq	-72(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rbx
	movq	%r14, %rdi
	callq	_ASIC_IS_R300
	testq	%rbx, %rbx
	je	LBB0_32
## %bb.25:
	testq	%rax, %rax
	je	LBB0_27
## %bb.26:
	movq	_RADEON_DISP_TVDAC_SOURCE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r12d
	movq	_RADEON_DISP_TV_SOURCE_CRTC@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
LBB0_27:
	movq	(%r14), %rax
	movq	_CHIP_R200@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_36
LBB0_28:
	movq	_RADEON_CRT2_DISP1_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, -44(%rbp)                 ## 4-byte Folded Spill
	jmp	LBB0_44
LBB0_29:
	movq	_RADEON_DAC_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %r15d
	movq	_RADEON_DAC2_DAC2_CLK_SEL@GOTPCREL(%rip), %rax
	orl	(%rax), %r15d
	movq	-72(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rbx
	movq	%r14, %rdi
	callq	_ASIC_IS_R300
	testq	%rbx, %rbx
	je	LBB0_37
## %bb.30:
	testq	%rax, %rax
	je	LBB0_40
## %bb.31:
	movq	_RADEON_DISP_TVDAC_SOURCE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r12d
	movq	_RADEON_DISP_TVDAC_SOURCE_CRTC2@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
	jmp	LBB0_44
LBB0_32:
	testq	%rax, %rax
	je	LBB0_34
## %bb.33:
	movq	_RADEON_DISP_TVDAC_SOURCE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r12d
	movq	_RADEON_DISP_TVDAC_SOURCE_CRTC@GOTPCREL(%rip), %rax
	movq	_RADEON_DISP_TV_SOURCE_CRTC@GOTPCREL(%rip), %rcx
	orl	(%rax), %r12d
	orl	(%rcx), %r12d
LBB0_34:
	movq	(%r14), %rax
	movq	_CHIP_R200@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_39
LBB0_35:
	movq	_RADEON_CRT2_DISP1_SEL@GOTPCREL(%rip), %rax
	movl	-44(%rbp), %ecx                 ## 4-byte Reload
	orl	(%rax), %ecx
	movl	%ecx, -44(%rbp)                 ## 4-byte Spill
	jmp	LBB0_44
LBB0_36:
	movq	_RADEON_DISP_TV_PATH_SRC_CRTC2@GOTPCREL(%rip), %rax
	movl	-52(%rbp), %ecx                 ## 4-byte Reload
	orl	(%rax), %ecx
	movl	%ecx, -52(%rbp)                 ## 4-byte Spill
	jmp	LBB0_44
LBB0_37:
	testq	%rax, %rax
	je	LBB0_42
## %bb.38:
	movq	_RADEON_DISP_TVDAC_SOURCE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r12d
	movq	_RADEON_DISP_TVDAC_SOURCE_CRTC@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
	jmp	LBB0_44
LBB0_39:
	movq	_RADEON_DISP_TV_PATH_SRC_CRTC2@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, -52(%rbp)                 ## 4-byte Folded Spill
	jmp	LBB0_44
LBB0_40:
	movq	(%r14), %rax
	movq	_CHIP_R200@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_28
## %bb.41:
	movq	_R200_FP2_SOURCE_SEL_MASK@GOTPCREL(%rip), %rax
	movq	_RADEON_FP2_DVO_RATE_SEL_SDR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	notl	%ecx
	movl	-48(%rbp), %edx                 ## 4-byte Reload
	andl	%ecx, %edx
	movq	_R200_FP2_SOURCE_SEL_CRTC2@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	%edx, -48(%rbp)                 ## 4-byte Spill
	jmp	LBB0_44
LBB0_42:
	movq	(%r14), %rax
	movq	_CHIP_R200@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_35
## %bb.43:
	movq	_R200_FP2_SOURCE_SEL_MASK@GOTPCREL(%rip), %rax
	movq	_RADEON_FP2_DVO_RATE_SEL_SDR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	notl	%ecx
	andl	%ecx, -48(%rbp)                 ## 4-byte Folded Spill
LBB0_44:
	movq	_RADEON_DAC_CNTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r15d, %esi
	callq	_WREG32
	movq	%r14, %rdi
	callq	_ASIC_IS_R300
	testq	%rax, %rax
	je	LBB0_46
## %bb.45:
	movq	_RADEON_GPIOPAD_A@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r13d, %esi
	movl	$-2, %edx
	callq	_WREG32_P
	movq	_RADEON_DISP_OUTPUT_CNTL@GOTPCREL(%rip), %rax
	jmp	LBB0_48
LBB0_46:
	movq	(%r14), %rax
	movq	_CHIP_R200@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_56
## %bb.47:
	movq	_RADEON_FP2_GEN_CNTL@GOTPCREL(%rip), %rax
	movl	-48(%rbp), %r12d                ## 4-byte Reload
LBB0_48:
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	movl	-52(%rbp), %r15d                ## 4-byte Reload
LBB0_49:
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movq	(%r14), %rax
	movq	_CHIP_R200@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_51
## %bb.50:
	movq	_RADEON_DISP_TV_OUT_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r15d, %esi
	callq	_WREG32
LBB0_51:
	cmpl	$0, -56(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_53
## %bb.52:
	movq	%rbx, %rdi
	movq	-80(%rbp), %rsi                 ## 8-byte Reload
	movq	-88(%rbp), %rdx                 ## 8-byte Reload
	callq	_radeon_legacy_tv_mode_set
LBB0_53:
	cmpq	$0, 8(%r14)
	movq	-72(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	je	LBB0_55
## %bb.54:
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_atombios_encoder_crtc_scratch_regs ## TAILCALL
LBB0_55:
	addq	$56, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_radeon_combios_encoder_crtc_scratch_regs ## TAILCALL
LBB0_56:
	movq	_RADEON_DISP_HW_DEBUG@GOTPCREL(%rip), %rax
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	movl	-52(%rbp), %r15d                ## 4-byte Reload
	movl	-44(%rbp), %r12d                ## 4-byte Reload
	jmp	LBB0_49
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"\n"

	.comm	_ATOM_DEVICE_TV_SUPPORT,4,2     ## @ATOM_DEVICE_TV_SUPPORT
	.comm	_CHIP_R200,8,3                  ## @CHIP_R200
	.comm	_RADEON_TV_DAC_CNTL,4,2         ## @RADEON_TV_DAC_CNTL
	.comm	_CHIP_R420,8,3                  ## @CHIP_R420
	.comm	_CHIP_R423,8,3                  ## @CHIP_R423
	.comm	_CHIP_RV410,8,3                 ## @CHIP_RV410
	.comm	_RADEON_TV_DAC_STD_MASK,4,2     ## @RADEON_TV_DAC_STD_MASK
	.comm	_RADEON_TV_DAC_BGADJ_MASK,4,2   ## @RADEON_TV_DAC_BGADJ_MASK
	.comm	_R420_TV_DAC_DACADJ_MASK,4,2    ## @R420_TV_DAC_DACADJ_MASK
	.comm	_R420_TV_DAC_RDACPD,4,2         ## @R420_TV_DAC_RDACPD
	.comm	_R420_TV_DAC_GDACPD,4,2         ## @R420_TV_DAC_GDACPD
	.comm	_R420_TV_DAC_BDACPD,4,2         ## @R420_TV_DAC_BDACPD
	.comm	_R420_TV_DAC_TVENABLE,4,2       ## @R420_TV_DAC_TVENABLE
	.comm	_RADEON_TV_DAC_DACADJ_MASK,4,2  ## @RADEON_TV_DAC_DACADJ_MASK
	.comm	_RADEON_TV_DAC_RDACPD,4,2       ## @RADEON_TV_DAC_RDACPD
	.comm	_RADEON_TV_DAC_GDACPD,4,2       ## @RADEON_TV_DAC_GDACPD
	.comm	_RADEON_TV_DAC_BDACPD,4,2       ## @RADEON_TV_DAC_BDACPD
	.comm	_RADEON_TV_DAC_NBLANK,4,2       ## @RADEON_TV_DAC_NBLANK
	.comm	_RADEON_TV_DAC_NHOLD,4,2        ## @RADEON_TV_DAC_NHOLD
	.comm	_TV_STD_NTSC,8,3                ## @TV_STD_NTSC
	.comm	_TV_STD_NTSC_J,8,3              ## @TV_STD_NTSC_J
	.comm	_TV_STD_PAL_M,8,3               ## @TV_STD_PAL_M
	.comm	_TV_STD_PAL_60,8,3              ## @TV_STD_PAL_60
	.comm	_RADEON_TV_DAC_STD_NTSC,4,2     ## @RADEON_TV_DAC_STD_NTSC
	.comm	_RADEON_TV_DAC_STD_PAL,4,2      ## @RADEON_TV_DAC_STD_PAL
	.comm	_RADEON_TV_DAC_STD_PS2,4,2      ## @RADEON_TV_DAC_STD_PS2
	.comm	_RADEON_GPIOPAD_A,4,2           ## @RADEON_GPIOPAD_A
	.comm	_RADEON_DISP_OUTPUT_CNTL,4,2    ## @RADEON_DISP_OUTPUT_CNTL
	.comm	_RADEON_DISP_HW_DEBUG,4,2       ## @RADEON_DISP_HW_DEBUG
	.comm	_RADEON_FP2_GEN_CNTL,4,2        ## @RADEON_FP2_GEN_CNTL
	.comm	_RADEON_DISP_TV_OUT_CNTL,4,2    ## @RADEON_DISP_TV_OUT_CNTL
	.comm	_RADEON_DAC_CNTL,4,2            ## @RADEON_DAC_CNTL
	.comm	_RADEON_DAC_TVO_EN,4,2          ## @RADEON_DAC_TVO_EN
	.comm	_RADEON_DAC_CNTL2,4,2           ## @RADEON_DAC_CNTL2
	.comm	_RADEON_DAC2_DAC2_CLK_SEL,4,2   ## @RADEON_DAC2_DAC2_CLK_SEL
	.comm	_RADEON_DISP_TVDAC_SOURCE_MASK,4,2 ## @RADEON_DISP_TVDAC_SOURCE_MASK
	.comm	_RADEON_DISP_TVDAC_SOURCE_CRTC,4,2 ## @RADEON_DISP_TVDAC_SOURCE_CRTC
	.comm	_RADEON_DISP_TV_SOURCE_CRTC,4,2 ## @RADEON_DISP_TV_SOURCE_CRTC
	.comm	_RADEON_DISP_TV_PATH_SRC_CRTC2,4,2 ## @RADEON_DISP_TV_PATH_SRC_CRTC2
	.comm	_RADEON_CRT2_DISP1_SEL,4,2      ## @RADEON_CRT2_DISP1_SEL
	.comm	_R200_FP2_SOURCE_SEL_MASK,4,2   ## @R200_FP2_SOURCE_SEL_MASK
	.comm	_RADEON_FP2_DVO_RATE_SEL_SDR,4,2 ## @RADEON_FP2_DVO_RATE_SEL_SDR
	.comm	_RADEON_DISP_TVDAC_SOURCE_CRTC2,4,2 ## @RADEON_DISP_TVDAC_SOURCE_CRTC2
	.comm	_R200_FP2_SOURCE_SEL_CRTC2,4,2  ## @R200_FP2_SOURCE_SEL_CRTC2
	.no_dead_strip	_radeon_legacy_tv_dac_mode_set
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function radeon_legacy_tv_dac_mode_set
_radeon_legacy_tv_dac_mode_set:         ; @radeon_legacy_tv_dac_mode_set
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #128
	.cfi_def_cfa_offset 128
	stp	x28, x27, [sp, #32]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #48]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #64]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #80]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #96]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #112]            ; 16-byte Folded Spill
	add	x29, sp, #112
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	stp	x1, x2, [sp, #8]                ; 16-byte Folded Spill
	mov	x19, x0
	ldr	x8, [x0, #8]
	ldr	x20, [x8]
	ldr	w0, [x0]
	bl	_to_radeon_crtc
	mov	x23, x0
	mov	x0, x19
	bl	_to_radeon_encoder
	mov	x21, x0
	ldr	x24, [x0, #8]
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_DEBUG_KMS
	ldr	w8, [x21]
Lloh2:
	adrp	x9, _ATOM_DEVICE_TV_SUPPORT@GOTPAGE
Lloh3:
	ldr	x9, [x9, _ATOM_DEVICE_TV_SUPPORT@GOTPAGEOFF]
Lloh4:
	ldr	w9, [x9]
	and	w22, w9, w8
	ldr	x8, [x20]
Lloh5:
	adrp	x28, _CHIP_R200@GOTPAGE
Lloh6:
	ldr	x28, [x28, _CHIP_R200@GOTPAGEOFF]
	ldr	x9, [x28]
	cmp	x8, x9
	b.eq	LBB0_13
; %bb.1:
Lloh7:
	adrp	x21, _RADEON_TV_DAC_CNTL@GOTPAGE
Lloh8:
	ldr	x21, [x21, _RADEON_TV_DAC_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
	ldr	x9, [x20]
Lloh9:
	adrp	x8, _CHIP_R420@GOTPAGE
Lloh10:
	ldr	x8, [x8, _CHIP_R420@GOTPAGEOFF]
Lloh11:
	ldr	x10, [x8]
Lloh12:
	adrp	x8, _RADEON_TV_DAC_STD_MASK@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RADEON_TV_DAC_STD_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
Lloh15:
	adrp	x11, _RADEON_TV_DAC_BGADJ_MASK@GOTPAGE
Lloh16:
	ldr	x11, [x11, _RADEON_TV_DAC_BGADJ_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w11, [x11]
	orr	w8, w11, w8
	cmp	x9, x10
	b.eq	LBB0_5
; %bb.2:
Lloh18:
	adrp	x10, _CHIP_R423@GOTPAGE
Lloh19:
	ldr	x10, [x10, _CHIP_R423@GOTPAGEOFF]
Lloh20:
	ldr	x10, [x10]
	cmp	x9, x10
	b.eq	LBB0_5
; %bb.3:
Lloh21:
	adrp	x10, _CHIP_RV410@GOTPAGE
Lloh22:
	ldr	x10, [x10, _CHIP_RV410@GOTPAGEOFF]
Lloh23:
	ldr	x10, [x10]
	cmp	x9, x10
	b.eq	LBB0_5
; %bb.4:
Lloh24:
	adrp	x9, _RADEON_TV_DAC_BDACPD@GOTPAGE
Lloh25:
	ldr	x9, [x9, _RADEON_TV_DAC_BDACPD@GOTPAGEOFF]
Lloh26:
	adrp	x10, _RADEON_TV_DAC_GDACPD@GOTPAGE
Lloh27:
	ldr	x10, [x10, _RADEON_TV_DAC_GDACPD@GOTPAGEOFF]
Lloh28:
	adrp	x11, _RADEON_TV_DAC_RDACPD@GOTPAGE
Lloh29:
	ldr	x11, [x11, _RADEON_TV_DAC_RDACPD@GOTPAGEOFF]
Lloh30:
	adrp	x12, _RADEON_TV_DAC_DACADJ_MASK@GOTPAGE
Lloh31:
	ldr	x12, [x12, _RADEON_TV_DAC_DACADJ_MASK@GOTPAGEOFF]
	b	LBB0_6
LBB0_5:
Lloh32:
	adrp	x9, _R420_TV_DAC_DACADJ_MASK@GOTPAGE
Lloh33:
	ldr	x9, [x9, _R420_TV_DAC_DACADJ_MASK@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh35:
	adrp	x9, _R420_TV_DAC_TVENABLE@GOTPAGE
Lloh36:
	ldr	x9, [x9, _R420_TV_DAC_TVENABLE@GOTPAGEOFF]
Lloh37:
	adrp	x10, _R420_TV_DAC_BDACPD@GOTPAGE
Lloh38:
	ldr	x10, [x10, _R420_TV_DAC_BDACPD@GOTPAGEOFF]
Lloh39:
	adrp	x11, _R420_TV_DAC_GDACPD@GOTPAGE
Lloh40:
	ldr	x11, [x11, _R420_TV_DAC_GDACPD@GOTPAGEOFF]
Lloh41:
	adrp	x12, _R420_TV_DAC_RDACPD@GOTPAGE
Lloh42:
	ldr	x12, [x12, _R420_TV_DAC_RDACPD@GOTPAGEOFF]
LBB0_6:
	ldr	w12, [x12]
	orr	w8, w8, w12
	ldr	w11, [x11]
	orr	w8, w8, w11
	ldr	w10, [x10]
	orr	w8, w8, w10
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w8, w0, w8
Lloh43:
	adrp	x9, _RADEON_TV_DAC_NBLANK@GOTPAGE
Lloh44:
	ldr	x9, [x9, _RADEON_TV_DAC_NBLANK@GOTPAGEOFF]
Lloh45:
	ldr	w9, [x9]
Lloh46:
	adrp	x10, _RADEON_TV_DAC_NHOLD@GOTPAGE
Lloh47:
	ldr	x10, [x10, _RADEON_TV_DAC_NHOLD@GOTPAGEOFF]
Lloh48:
	ldr	w10, [x10]
	orr	w8, w8, w9
	orr	w8, w8, w10
	cbz	w22, LBB0_9
; %bb.7:
	ldr	x9, [x24]
Lloh49:
	adrp	x10, _TV_STD_NTSC@GOTPAGE
Lloh50:
	ldr	x10, [x10, _TV_STD_NTSC@GOTPAGEOFF]
Lloh51:
	ldr	x10, [x10]
Lloh52:
	adrp	x11, _TV_STD_NTSC_J@GOTPAGE
Lloh53:
	ldr	x11, [x11, _TV_STD_NTSC_J@GOTPAGEOFF]
	cmp	x9, x10
Lloh54:
	ldr	x10, [x11]
	ccmp	x9, x10, #4, ne
	cset	w10, eq
Lloh55:
	adrp	x11, _TV_STD_PAL_M@GOTPAGE
Lloh56:
	ldr	x11, [x11, _TV_STD_PAL_M@GOTPAGEOFF]
Lloh57:
	ldr	x11, [x11]
	cmp	x9, x11
	cset	w11, eq
	orr	w11, w10, w11
Lloh58:
	adrp	x12, _TV_STD_PAL_60@GOTPAGE
Lloh59:
	ldr	x12, [x12, _TV_STD_PAL_60@GOTPAGEOFF]
Lloh60:
	ldr	x12, [x12]
	cmp	x9, x12
	cset	w9, eq
	orr	w9, w11, w9
	cmp	w9, #0
	mov	w9, #12
	mov	w11, #8
	csel	x9, x11, x9, ne
	ldr	w9, [x24, x9]
	orr	w8, w9, w8
	cmp	w10, #1
	b.ne	LBB0_10
; %bb.8:
Lloh61:
	adrp	x9, _RADEON_TV_DAC_STD_NTSC@GOTPAGE
Lloh62:
	ldr	x9, [x9, _RADEON_TV_DAC_STD_NTSC@GOTPAGEOFF]
	b	LBB0_11
LBB0_9:
Lloh63:
	adrp	x9, _RADEON_TV_DAC_STD_PS2@GOTPAGE
Lloh64:
	ldr	x9, [x9, _RADEON_TV_DAC_STD_PS2@GOTPAGEOFF]
Lloh65:
	ldr	w9, [x9]
	ldr	w10, [x24, #16]
	orr	w8, w9, w8
	orr	w1, w8, w10
	b	LBB0_12
LBB0_10:
Lloh66:
	adrp	x9, _RADEON_TV_DAC_STD_PAL@GOTPAGE
Lloh67:
	ldr	x9, [x9, _RADEON_TV_DAC_STD_PAL@GOTPAGEOFF]
LBB0_11:
	ldr	w9, [x9]
	orr	w1, w9, w8
LBB0_12:
	ldr	w0, [x21]
	bl	_WREG32
LBB0_13:
	mov	x0, x20
	bl	_ASIC_IS_R300
Lloh68:
	adrp	x26, _RADEON_GPIOPAD_A@GOTPAGE
Lloh69:
	ldr	x26, [x26, _RADEON_GPIOPAD_A@GOTPAGEOFF]
	cbz	x0, LBB0_15
; %bb.14:
	ldr	w0, [x26]
	bl	_RREG32
	orr	w8, w0, #0x1
	str	w8, [sp, #24]                   ; 4-byte Folded Spill
Lloh70:
	adrp	x8, _RADEON_DISP_OUTPUT_CNTL@GOTPAGE
Lloh71:
	ldr	x8, [x8, _RADEON_DISP_OUTPUT_CNTL@GOTPAGEOFF]
Lloh72:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x25, x0
	mov	w27, #0
	b	LBB0_18
LBB0_15:
	ldr	x8, [x20]
	ldr	x9, [x28]
	cmp	x8, x9
	b.ne	LBB0_17
; %bb.16:
Lloh73:
	adrp	x8, _RADEON_FP2_GEN_CNTL@GOTPAGE
Lloh74:
	ldr	x8, [x8, _RADEON_FP2_GEN_CNTL@GOTPAGEOFF]
Lloh75:
	ldr	w0, [x8]
	bl	_RREG32
	str	w0, [sp, #4]                    ; 4-byte Folded Spill
	str	wzr, [sp, #24]                  ; 4-byte Folded Spill
	mov	w25, #0
	mov	w27, #0
	b	LBB0_19
LBB0_17:
Lloh76:
	adrp	x8, _RADEON_DISP_HW_DEBUG@GOTPAGE
Lloh77:
	ldr	x8, [x8, _RADEON_DISP_HW_DEBUG@GOTPAGEOFF]
Lloh78:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x27, x0
	str	wzr, [sp, #24]                  ; 4-byte Folded Spill
	mov	w25, #0
LBB0_18:
	str	wzr, [sp, #4]                   ; 4-byte Folded Spill
LBB0_19:
	ldr	x8, [x20]
	ldr	x9, [x28]
	cmp	x8, x9
	b.ge	LBB0_21
; %bb.20:
	str	wzr, [sp, #28]                  ; 4-byte Folded Spill
	b	LBB0_22
LBB0_21:
Lloh79:
	adrp	x8, _RADEON_DISP_TV_OUT_CNTL@GOTPAGE
Lloh80:
	ldr	x8, [x8, _RADEON_DISP_TV_OUT_CNTL@GOTPAGEOFF]
Lloh81:
	ldr	w0, [x8]
	bl	_RREG32
	str	w0, [sp, #28]                   ; 4-byte Folded Spill
LBB0_22:
Lloh82:
	adrp	x28, _RADEON_DAC_CNTL2@GOTPAGE
Lloh83:
	ldr	x28, [x28, _RADEON_DAC_CNTL2@GOTPAGEOFF]
	mov	x24, x22
	cbz	w22, LBB0_30
; %bb.23:
Lloh84:
	adrp	x21, _RADEON_DAC_CNTL@GOTPAGE
Lloh85:
	ldr	x21, [x21, _RADEON_DAC_CNTL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_RREG32
Lloh86:
	adrp	x8, _RADEON_DAC_TVO_EN@GOTPAGE
Lloh87:
	ldr	x8, [x8, _RADEON_DAC_TVO_EN@GOTPAGEOFF]
Lloh88:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w0, [x21]
	bl	_WREG32
	mov	x0, x20
	bl	_ASIC_IS_R300
	cbz	x0, LBB0_25
; %bb.24:
	ldr	w0, [x26]
	bl	_RREG32
	and	w8, w0, #0xfffffffe
	str	w8, [sp, #24]                   ; 4-byte Folded Spill
LBB0_25:
	mov	x22, x28
	ldr	w0, [x28]
	bl	_RREG32
Lloh89:
	adrp	x8, _RADEON_DAC2_DAC2_CLK_SEL@GOTPAGE
Lloh90:
	ldr	x8, [x8, _RADEON_DAC2_DAC2_CLK_SEL@GOTPAGEOFF]
Lloh91:
	ldr	w8, [x8]
	bic	w21, w0, w8
	mov	x28, x23
	ldr	x23, [x23]
	mov	x0, x20
	bl	_ASIC_IS_R300
	cbz	x23, LBB0_33
; %bb.26:
	cbz	x0, LBB0_28
; %bb.27:
Lloh92:
	adrp	x8, _RADEON_DISP_TVDAC_SOURCE_MASK@GOTPAGE
Lloh93:
	ldr	x8, [x8, _RADEON_DISP_TVDAC_SOURCE_MASK@GOTPAGEOFF]
Lloh94:
	ldr	w8, [x8]
	bic	w8, w25, w8
Lloh95:
	adrp	x9, _RADEON_DISP_TV_SOURCE_CRTC@GOTPAGE
Lloh96:
	ldr	x9, [x9, _RADEON_DISP_TV_SOURCE_CRTC@GOTPAGEOFF]
Lloh97:
	ldr	w9, [x9]
	orr	w25, w8, w9
LBB0_28:
	mov	x23, x28
	ldr	x8, [x20]
Lloh98:
	adrp	x28, _CHIP_R200@GOTPAGE
Lloh99:
	ldr	x28, [x28, _CHIP_R200@GOTPAGEOFF]
	ldr	x9, [x28]
	cmp	x8, x9
	b.ge	LBB0_37
; %bb.29:
Lloh100:
	adrp	x8, _RADEON_CRT2_DISP1_SEL@GOTPAGE
Lloh101:
	ldr	x8, [x8, _RADEON_CRT2_DISP1_SEL@GOTPAGEOFF]
Lloh102:
	ldr	w8, [x8]
	bic	w27, w27, w8
	b	LBB0_44
LBB0_30:
	mov	x22, x28
	ldr	w0, [x28]
	bl	_RREG32
Lloh103:
	adrp	x8, _RADEON_DAC2_DAC2_CLK_SEL@GOTPAGE
Lloh104:
	ldr	x8, [x8, _RADEON_DAC2_DAC2_CLK_SEL@GOTPAGEOFF]
Lloh105:
	ldr	w8, [x8]
	orr	w21, w8, w0
	mov	x28, x23
	ldr	x23, [x23]
	mov	x0, x20
	bl	_ASIC_IS_R300
	cbz	x23, LBB0_38
; %bb.31:
	cbz	x0, LBB0_54
; %bb.32:
Lloh106:
	adrp	x8, _RADEON_DISP_TVDAC_SOURCE_MASK@GOTPAGE
Lloh107:
	ldr	x8, [x8, _RADEON_DISP_TVDAC_SOURCE_MASK@GOTPAGEOFF]
Lloh108:
	ldr	w8, [x8]
	bic	w8, w25, w8
Lloh109:
	adrp	x9, _RADEON_DISP_TVDAC_SOURCE_CRTC2@GOTPAGE
Lloh110:
	ldr	x9, [x9, _RADEON_DISP_TVDAC_SOURCE_CRTC2@GOTPAGEOFF]
	b	LBB0_40
LBB0_33:
	cbz	x0, LBB0_35
; %bb.34:
Lloh111:
	adrp	x8, _RADEON_DISP_TVDAC_SOURCE_MASK@GOTPAGE
Lloh112:
	ldr	x8, [x8, _RADEON_DISP_TVDAC_SOURCE_MASK@GOTPAGEOFF]
Lloh113:
	ldr	w8, [x8]
	bic	w8, w25, w8
Lloh114:
	adrp	x9, _RADEON_DISP_TVDAC_SOURCE_CRTC@GOTPAGE
Lloh115:
	ldr	x9, [x9, _RADEON_DISP_TVDAC_SOURCE_CRTC@GOTPAGEOFF]
Lloh116:
	ldr	w9, [x9]
Lloh117:
	adrp	x10, _RADEON_DISP_TV_SOURCE_CRTC@GOTPAGE
Lloh118:
	ldr	x10, [x10, _RADEON_DISP_TV_SOURCE_CRTC@GOTPAGEOFF]
Lloh119:
	ldr	w10, [x10]
	orr	w8, w8, w9
	orr	w25, w8, w10
LBB0_35:
	mov	x23, x28
Lloh120:
	adrp	x28, _CHIP_R200@GOTPAGE
Lloh121:
	ldr	x28, [x28, _CHIP_R200@GOTPAGEOFF]
	ldr	x8, [x20]
	ldr	x9, [x28]
	cmp	x8, x9
	b.ge	LBB0_42
; %bb.36:
Lloh122:
	adrp	x8, _RADEON_CRT2_DISP1_SEL@GOTPAGE
Lloh123:
	ldr	x8, [x8, _RADEON_CRT2_DISP1_SEL@GOTPAGEOFF]
Lloh124:
	ldr	w8, [x8]
	orr	w27, w8, w27
	b	LBB0_44
LBB0_37:
Lloh125:
	adrp	x8, _RADEON_DISP_TV_PATH_SRC_CRTC2@GOTPAGE
Lloh126:
	ldr	x8, [x8, _RADEON_DISP_TV_PATH_SRC_CRTC2@GOTPAGEOFF]
Lloh127:
	ldr	w8, [x8]
	ldr	w9, [sp, #28]                   ; 4-byte Folded Reload
	orr	w9, w8, w9
	b	LBB0_43
LBB0_38:
	cbz	x0, LBB0_56
; %bb.39:
Lloh128:
	adrp	x8, _RADEON_DISP_TVDAC_SOURCE_MASK@GOTPAGE
Lloh129:
	ldr	x8, [x8, _RADEON_DISP_TVDAC_SOURCE_MASK@GOTPAGEOFF]
Lloh130:
	ldr	w8, [x8]
	bic	w8, w25, w8
Lloh131:
	adrp	x9, _RADEON_DISP_TVDAC_SOURCE_CRTC@GOTPAGE
Lloh132:
	ldr	x9, [x9, _RADEON_DISP_TVDAC_SOURCE_CRTC@GOTPAGEOFF]
LBB0_40:
	ldr	w9, [x9]
	orr	w25, w8, w9
LBB0_41:
	mov	x23, x28
Lloh133:
	adrp	x28, _CHIP_R200@GOTPAGE
Lloh134:
	ldr	x28, [x28, _CHIP_R200@GOTPAGEOFF]
	b	LBB0_44
LBB0_42:
Lloh135:
	adrp	x8, _RADEON_DISP_TV_PATH_SRC_CRTC2@GOTPAGE
Lloh136:
	ldr	x8, [x8, _RADEON_DISP_TV_PATH_SRC_CRTC2@GOTPAGEOFF]
Lloh137:
	ldr	w8, [x8]
	ldr	w9, [sp, #28]                   ; 4-byte Folded Reload
	bic	w9, w9, w8
LBB0_43:
	str	w9, [sp, #28]                   ; 4-byte Folded Spill
LBB0_44:
	ldr	w0, [x22]
	mov	x1, x21
	bl	_WREG32
	mov	x0, x20
	bl	_ASIC_IS_R300
	cbz	x0, LBB0_46
; %bb.45:
	ldr	w0, [x26]
	ldr	w1, [sp, #24]                   ; 4-byte Folded Reload
	mov	w2, #-2
	bl	_WREG32_P
Lloh138:
	adrp	x8, _RADEON_DISP_OUTPUT_CNTL@GOTPAGE
Lloh139:
	ldr	x8, [x8, _RADEON_DISP_OUTPUT_CNTL@GOTPAGEOFF]
	b	LBB0_47
LBB0_46:
	ldr	x8, [x20]
Lloh140:
	adrp	x9, _RADEON_DISP_HW_DEBUG@GOTPAGE
Lloh141:
	ldr	x9, [x9, _RADEON_DISP_HW_DEBUG@GOTPAGEOFF]
	ldr	x10, [x28]
Lloh142:
	adrp	x11, _RADEON_FP2_GEN_CNTL@GOTPAGE
Lloh143:
	ldr	x11, [x11, _RADEON_FP2_GEN_CNTL@GOTPAGEOFF]
	cmp	x8, x10
	csel	x8, x11, x9, eq
	ldr	w9, [sp, #4]                    ; 4-byte Folded Reload
	csel	w25, w9, w27, eq
LBB0_47:
	ldr	w0, [x8]
	mov	x1, x25
	bl	_WREG32
	ldr	x8, [x20]
	ldr	x9, [x28]
	cmp	x8, x9
	b.lt	LBB0_49
; %bb.48:
Lloh144:
	adrp	x8, _RADEON_DISP_TV_OUT_CNTL@GOTPAGE
Lloh145:
	ldr	x8, [x8, _RADEON_DISP_TV_OUT_CNTL@GOTPAGEOFF]
Lloh146:
	ldr	w0, [x8]
	ldr	w1, [sp, #28]                   ; 4-byte Folded Reload
	bl	_WREG32
LBB0_49:
	cbz	w24, LBB0_51
; %bb.50:
	mov	x0, x19
	ldp	x1, x2, [sp, #8]                ; 16-byte Folded Reload
	bl	_radeon_legacy_tv_mode_set
LBB0_51:
	ldr	x8, [x20, #8]
	ldr	x1, [x23]
	mov	x0, x19
	cbz	x8, LBB0_53
; %bb.52:
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	b	_radeon_atombios_encoder_crtc_scratch_regs
LBB0_53:
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	b	_radeon_combios_encoder_crtc_scratch_regs
LBB0_54:
	ldr	x8, [x20]
Lloh147:
	adrp	x9, _CHIP_R200@GOTPAGE
Lloh148:
	ldr	x9, [x9, _CHIP_R200@GOTPAGEOFF]
Lloh149:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_58
; %bb.55:
Lloh150:
	adrp	x8, _R200_FP2_SOURCE_SEL_MASK@GOTPAGE
Lloh151:
	ldr	x8, [x8, _R200_FP2_SOURCE_SEL_MASK@GOTPAGEOFF]
Lloh152:
	ldr	w8, [x8]
Lloh153:
	adrp	x9, _RADEON_FP2_DVO_RATE_SEL_SDR@GOTPAGE
Lloh154:
	ldr	x9, [x9, _RADEON_FP2_DVO_RATE_SEL_SDR@GOTPAGEOFF]
Lloh155:
	ldr	w9, [x9]
	orr	w8, w9, w8
	ldr	w9, [sp, #4]                    ; 4-byte Folded Reload
	bic	w8, w9, w8
Lloh156:
	adrp	x9, _R200_FP2_SOURCE_SEL_CRTC2@GOTPAGE
Lloh157:
	ldr	x9, [x9, _R200_FP2_SOURCE_SEL_CRTC2@GOTPAGEOFF]
Lloh158:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [sp, #4]                    ; 4-byte Folded Spill
	b	LBB0_41
LBB0_56:
	ldr	x8, [x20]
Lloh159:
	adrp	x9, _CHIP_R200@GOTPAGE
Lloh160:
	ldr	x9, [x9, _CHIP_R200@GOTPAGEOFF]
Lloh161:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_59
; %bb.57:
Lloh162:
	adrp	x8, _R200_FP2_SOURCE_SEL_MASK@GOTPAGE
Lloh163:
	ldr	x8, [x8, _R200_FP2_SOURCE_SEL_MASK@GOTPAGEOFF]
Lloh164:
	ldr	w8, [x8]
Lloh165:
	adrp	x9, _RADEON_FP2_DVO_RATE_SEL_SDR@GOTPAGE
Lloh166:
	ldr	x9, [x9, _RADEON_FP2_DVO_RATE_SEL_SDR@GOTPAGEOFF]
Lloh167:
	ldr	w9, [x9]
	orr	w8, w9, w8
	ldr	w9, [sp, #4]                    ; 4-byte Folded Reload
	bic	w9, w9, w8
	str	w9, [sp, #4]                    ; 4-byte Folded Spill
	b	LBB0_41
LBB0_58:
Lloh168:
	adrp	x8, _RADEON_CRT2_DISP1_SEL@GOTPAGE
Lloh169:
	ldr	x8, [x8, _RADEON_CRT2_DISP1_SEL@GOTPAGEOFF]
Lloh170:
	ldr	w8, [x8]
	bic	w27, w27, w8
	b	LBB0_41
LBB0_59:
Lloh171:
	adrp	x8, _RADEON_CRT2_DISP1_SEL@GOTPAGE
Lloh172:
	ldr	x8, [x8, _RADEON_CRT2_DISP1_SEL@GOTPAGEOFF]
Lloh173:
	ldr	w8, [x8]
	orr	w27, w8, w27
	b	LBB0_41
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGot	Lloh66, Lloh67
	.loh AdrpLdrGot	Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGot	Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGot	Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGot	Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGot	Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGot	Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGot	Lloh131, Lloh132
	.loh AdrpLdrGotLdr	Lloh128, Lloh129, Lloh130
	.loh AdrpLdrGot	Lloh133, Lloh134
	.loh AdrpLdrGotLdr	Lloh135, Lloh136, Lloh137
	.loh AdrpLdrGot	Lloh138, Lloh139
	.loh AdrpLdrGot	Lloh142, Lloh143
	.loh AdrpLdrGot	Lloh140, Lloh141
	.loh AdrpLdrGotLdr	Lloh144, Lloh145, Lloh146
	.loh AdrpLdrGotLdr	Lloh147, Lloh148, Lloh149
	.loh AdrpLdrGotLdr	Lloh156, Lloh157, Lloh158
	.loh AdrpLdrGotLdr	Lloh153, Lloh154, Lloh155
	.loh AdrpLdrGotLdr	Lloh150, Lloh151, Lloh152
	.loh AdrpLdrGotLdr	Lloh159, Lloh160, Lloh161
	.loh AdrpLdrGotLdr	Lloh165, Lloh166, Lloh167
	.loh AdrpLdrGotLdr	Lloh162, Lloh163, Lloh164
	.loh AdrpLdrGotLdr	Lloh168, Lloh169, Lloh170
	.loh AdrpLdrGotLdr	Lloh171, Lloh172, Lloh173
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"\n"

	.comm	_ATOM_DEVICE_TV_SUPPORT,4,2     ; @ATOM_DEVICE_TV_SUPPORT
	.comm	_CHIP_R200,8,3                  ; @CHIP_R200
	.comm	_RADEON_TV_DAC_CNTL,4,2         ; @RADEON_TV_DAC_CNTL
	.comm	_CHIP_R420,8,3                  ; @CHIP_R420
	.comm	_CHIP_R423,8,3                  ; @CHIP_R423
	.comm	_CHIP_RV410,8,3                 ; @CHIP_RV410
	.comm	_RADEON_TV_DAC_STD_MASK,4,2     ; @RADEON_TV_DAC_STD_MASK
	.comm	_RADEON_TV_DAC_BGADJ_MASK,4,2   ; @RADEON_TV_DAC_BGADJ_MASK
	.comm	_R420_TV_DAC_DACADJ_MASK,4,2    ; @R420_TV_DAC_DACADJ_MASK
	.comm	_R420_TV_DAC_RDACPD,4,2         ; @R420_TV_DAC_RDACPD
	.comm	_R420_TV_DAC_GDACPD,4,2         ; @R420_TV_DAC_GDACPD
	.comm	_R420_TV_DAC_BDACPD,4,2         ; @R420_TV_DAC_BDACPD
	.comm	_R420_TV_DAC_TVENABLE,4,2       ; @R420_TV_DAC_TVENABLE
	.comm	_RADEON_TV_DAC_DACADJ_MASK,4,2  ; @RADEON_TV_DAC_DACADJ_MASK
	.comm	_RADEON_TV_DAC_RDACPD,4,2       ; @RADEON_TV_DAC_RDACPD
	.comm	_RADEON_TV_DAC_GDACPD,4,2       ; @RADEON_TV_DAC_GDACPD
	.comm	_RADEON_TV_DAC_BDACPD,4,2       ; @RADEON_TV_DAC_BDACPD
	.comm	_RADEON_TV_DAC_NBLANK,4,2       ; @RADEON_TV_DAC_NBLANK
	.comm	_RADEON_TV_DAC_NHOLD,4,2        ; @RADEON_TV_DAC_NHOLD
	.comm	_TV_STD_NTSC,8,3                ; @TV_STD_NTSC
	.comm	_TV_STD_NTSC_J,8,3              ; @TV_STD_NTSC_J
	.comm	_TV_STD_PAL_M,8,3               ; @TV_STD_PAL_M
	.comm	_TV_STD_PAL_60,8,3              ; @TV_STD_PAL_60
	.comm	_RADEON_TV_DAC_STD_NTSC,4,2     ; @RADEON_TV_DAC_STD_NTSC
	.comm	_RADEON_TV_DAC_STD_PAL,4,2      ; @RADEON_TV_DAC_STD_PAL
	.comm	_RADEON_TV_DAC_STD_PS2,4,2      ; @RADEON_TV_DAC_STD_PS2
	.comm	_RADEON_GPIOPAD_A,4,2           ; @RADEON_GPIOPAD_A
	.comm	_RADEON_DISP_OUTPUT_CNTL,4,2    ; @RADEON_DISP_OUTPUT_CNTL
	.comm	_RADEON_DISP_HW_DEBUG,4,2       ; @RADEON_DISP_HW_DEBUG
	.comm	_RADEON_FP2_GEN_CNTL,4,2        ; @RADEON_FP2_GEN_CNTL
	.comm	_RADEON_DISP_TV_OUT_CNTL,4,2    ; @RADEON_DISP_TV_OUT_CNTL
	.comm	_RADEON_DAC_CNTL,4,2            ; @RADEON_DAC_CNTL
	.comm	_RADEON_DAC_TVO_EN,4,2          ; @RADEON_DAC_TVO_EN
	.comm	_RADEON_DAC_CNTL2,4,2           ; @RADEON_DAC_CNTL2
	.comm	_RADEON_DAC2_DAC2_CLK_SEL,4,2   ; @RADEON_DAC2_DAC2_CLK_SEL
	.comm	_RADEON_DISP_TVDAC_SOURCE_MASK,4,2 ; @RADEON_DISP_TVDAC_SOURCE_MASK
	.comm	_RADEON_DISP_TVDAC_SOURCE_CRTC,4,2 ; @RADEON_DISP_TVDAC_SOURCE_CRTC
	.comm	_RADEON_DISP_TV_SOURCE_CRTC,4,2 ; @RADEON_DISP_TV_SOURCE_CRTC
	.comm	_RADEON_DISP_TV_PATH_SRC_CRTC2,4,2 ; @RADEON_DISP_TV_PATH_SRC_CRTC2
	.comm	_RADEON_CRT2_DISP1_SEL,4,2      ; @RADEON_CRT2_DISP1_SEL
	.comm	_R200_FP2_SOURCE_SEL_MASK,4,2   ; @R200_FP2_SOURCE_SEL_MASK
	.comm	_RADEON_FP2_DVO_RATE_SEL_SDR,4,2 ; @RADEON_FP2_DVO_RATE_SEL_SDR
	.comm	_RADEON_DISP_TVDAC_SOURCE_CRTC2,4,2 ; @RADEON_DISP_TVDAC_SOURCE_CRTC2
	.comm	_R200_FP2_SOURCE_SEL_CRTC2,4,2  ; @R200_FP2_SOURCE_SEL_CRTC2
	.no_dead_strip	_radeon_legacy_tv_dac_mode_set
.subsections_via_symbols
