	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v9_0_ring_emit_pipeline_sync
_gfx_v9_0_ring_emit_pipeline_sync:      ## @gfx_v9_0_ring_emit_pipeline_sync
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	8(%rdi), %rax
	movq	(%rax), %rax
	movq	_AMDGPU_RING_TYPE_GFX@GOTPCREL(%rip), %rcx
	xorl	%r14d, %r14d
	cmpq	(%rcx), %rax
	sete	%r14b
	movl	(%rdi), %r15d
	movl	4(%rdi), %r13d
	movl	%r15d, %edi
	callq	_lower_32_bits
	movl	%eax, %r12d
	movl	%r15d, %edi
	callq	_upper_32_bits
	subq	$8, %rsp
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	$1, %edx
	xorl	%ecx, %ecx
	movl	%r12d, %r8d
	movl	%eax, %r9d
	pushq	$4
	pushq	$-1
	pushq	%r13
	callq	_gfx_v9_0_wait_reg_mem
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMDGPU_RING_TYPE_GFX,8,3       ## @AMDGPU_RING_TYPE_GFX
	.no_dead_strip	_gfx_v9_0_ring_emit_pipeline_sync
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v9_0_ring_emit_pipeline_sync
_gfx_v9_0_ring_emit_pipeline_sync:      ; @gfx_v9_0_ring_emit_pipeline_sync
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	x8, [x0, #8]
Lloh0:
	adrp	x9, _AMDGPU_RING_TYPE_GFX@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AMDGPU_RING_TYPE_GFX@GOTPAGEOFF]
	ldr	x8, [x8]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	cset	w20, eq
	ldp	w22, w21, [x0]
	mov	x0, x22
	bl	_lower_32_bits
	mov	x23, x0
	mov	x0, x22
	bl	_upper_32_bits
	mov	x5, x0
	mov	w8, #4
	str	w8, [sp]
	mov	x0, x19
	mov	x1, x20
	mov	w2, #1
	mov	w3, #0
	mov	x4, x23
	mov	x6, x21
	mov	w7, #-1
	bl	_gfx_v9_0_wait_reg_mem
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_AMDGPU_RING_TYPE_GFX,8,3       ; @AMDGPU_RING_TYPE_GFX
	.no_dead_strip	_gfx_v9_0_ring_emit_pipeline_sync
.subsections_via_symbols
