	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function guc_prepare_xfer
_guc_prepare_xfer:                      ## @guc_prepare_xfer
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	_GUC_DISABLE_SRAM_INIT_TO_ZEROES@GOTPCREL(%rip), %rax
	movq	_GUC_ENABLE_READ_CACHE_LOGIC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	_GUC_ENABLE_MIA_CACHING@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	%rdi, %rbx
	movq	_GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_GUC_ENABLE_MIA_CLOCK_GATING@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_GUC_SHIM_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_intel_uncore_write
	movl	(%rbx), %edi
	callq	_IS_GEN9_LP
	testq	%rax, %rax
	jne	LBB0_1
## %bb.2:
	movq	_GEN9_GT_PM_CONFIG@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_1:
	movq	_GEN9LP_GT_PM_CONFIG@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %esi
	movq	_GT_DOORBELL_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_intel_uncore_write
	movl	(%rbx), %edi
	movl	$9, %esi
	callq	_IS_GEN
	testq	%rax, %rax
	je	LBB0_4
## %bb.5:
	movq	_GEN7_MISCCPCTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_GEN8_DOP_CLOCK_GATE_GUC_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_intel_uncore_rmw
	movq	_GUC_ARAT_C6DIS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$511, %edx                      ## imm = 0x1FF
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_intel_uncore_write             ## TAILCALL
LBB0_4:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_GUC_DISABLE_SRAM_INIT_TO_ZEROES,4,2 ## @GUC_DISABLE_SRAM_INIT_TO_ZEROES
	.comm	_GUC_ENABLE_READ_CACHE_LOGIC,4,2 ## @GUC_ENABLE_READ_CACHE_LOGIC
	.comm	_GUC_ENABLE_MIA_CACHING,4,2     ## @GUC_ENABLE_MIA_CACHING
	.comm	_GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA,4,2 ## @GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA
	.comm	_GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA,4,2 ## @GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA
	.comm	_GUC_ENABLE_MIA_CLOCK_GATING,4,2 ## @GUC_ENABLE_MIA_CLOCK_GATING
	.comm	_GUC_SHIM_CONTROL,4,2           ## @GUC_SHIM_CONTROL
	.comm	_GEN9LP_GT_PM_CONFIG,4,2        ## @GEN9LP_GT_PM_CONFIG
	.comm	_GT_DOORBELL_ENABLE,4,2         ## @GT_DOORBELL_ENABLE
	.comm	_GEN9_GT_PM_CONFIG,4,2          ## @GEN9_GT_PM_CONFIG
	.comm	_GEN7_MISCCPCTL,4,2             ## @GEN7_MISCCPCTL
	.comm	_GEN8_DOP_CLOCK_GATE_GUC_ENABLE,4,2 ## @GEN8_DOP_CLOCK_GATE_GUC_ENABLE
	.comm	_GUC_ARAT_C6DIS,4,2             ## @GUC_ARAT_C6DIS
	.no_dead_strip	_guc_prepare_xfer
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function guc_prepare_xfer
_guc_prepare_xfer:                      ; @guc_prepare_xfer
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
Lloh0:
	adrp	x8, _GUC_DISABLE_SRAM_INIT_TO_ZEROES@GOTPAGE
Lloh1:
	ldr	x8, [x8, _GUC_DISABLE_SRAM_INIT_TO_ZEROES@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _GUC_ENABLE_READ_CACHE_LOGIC@GOTPAGE
Lloh4:
	ldr	x9, [x9, _GUC_ENABLE_READ_CACHE_LOGIC@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
Lloh6:
	adrp	x10, _GUC_ENABLE_MIA_CACHING@GOTPAGE
Lloh7:
	ldr	x10, [x10, _GUC_ENABLE_MIA_CACHING@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh8:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh9:
	adrp	x9, _GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA@GOTPAGE
Lloh10:
	ldr	x9, [x9, _GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh12:
	adrp	x9, _GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA@GOTPAGE
Lloh13:
	ldr	x9, [x9, _GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
Lloh15:
	adrp	x10, _GUC_ENABLE_MIA_CLOCK_GATING@GOTPAGE
Lloh16:
	ldr	x10, [x10, _GUC_ENABLE_MIA_CLOCK_GATING@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh17:
	ldr	w9, [x10]
	orr	w2, w8, w9
Lloh18:
	adrp	x8, _GUC_SHIM_CONTROL@GOTPAGE
Lloh19:
	ldr	x8, [x8, _GUC_SHIM_CONTROL@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	bl	_intel_uncore_write
	ldr	w0, [x19]
	bl	_IS_GEN9_LP
Lloh21:
	adrp	x8, _GEN9_GT_PM_CONFIG@GOTPAGE
Lloh22:
	ldr	x8, [x8, _GEN9_GT_PM_CONFIG@GOTPAGEOFF]
Lloh23:
	adrp	x9, _GEN9LP_GT_PM_CONFIG@GOTPAGE
Lloh24:
	ldr	x9, [x9, _GEN9LP_GT_PM_CONFIG@GOTPAGEOFF]
	cmp	x0, #0
	csel	x8, x8, x9, eq
	ldr	w1, [x8]
Lloh25:
	adrp	x8, _GT_DOORBELL_ENABLE@GOTPAGE
Lloh26:
	ldr	x8, [x8, _GT_DOORBELL_ENABLE@GOTPAGEOFF]
Lloh27:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_intel_uncore_write
	ldr	w0, [x19]
	mov	w1, #9
	bl	_IS_GEN
	cbz	x0, LBB0_2
; %bb.1:
Lloh28:
	adrp	x8, _GEN7_MISCCPCTL@GOTPAGE
Lloh29:
	ldr	x8, [x8, _GEN7_MISCCPCTL@GOTPAGEOFF]
Lloh30:
	ldr	w1, [x8]
Lloh31:
	adrp	x8, _GEN8_DOP_CLOCK_GATE_GUC_ENABLE@GOTPAGE
Lloh32:
	ldr	x8, [x8, _GEN8_DOP_CLOCK_GATE_GUC_ENABLE@GOTPAGEOFF]
Lloh33:
	ldr	w3, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_intel_uncore_rmw
Lloh34:
	adrp	x8, _GUC_ARAT_C6DIS@GOTPAGE
Lloh35:
	ldr	x8, [x8, _GUC_ARAT_C6DIS@GOTPAGEOFF]
Lloh36:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #511
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_intel_uncore_write
LBB0_2:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.cfi_endproc
                                        ; -- End function
	.comm	_GUC_DISABLE_SRAM_INIT_TO_ZEROES,4,2 ; @GUC_DISABLE_SRAM_INIT_TO_ZEROES
	.comm	_GUC_ENABLE_READ_CACHE_LOGIC,4,2 ; @GUC_ENABLE_READ_CACHE_LOGIC
	.comm	_GUC_ENABLE_MIA_CACHING,4,2     ; @GUC_ENABLE_MIA_CACHING
	.comm	_GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA,4,2 ; @GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA
	.comm	_GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA,4,2 ; @GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA
	.comm	_GUC_ENABLE_MIA_CLOCK_GATING,4,2 ; @GUC_ENABLE_MIA_CLOCK_GATING
	.comm	_GUC_SHIM_CONTROL,4,2           ; @GUC_SHIM_CONTROL
	.comm	_GEN9LP_GT_PM_CONFIG,4,2        ; @GEN9LP_GT_PM_CONFIG
	.comm	_GT_DOORBELL_ENABLE,4,2         ; @GT_DOORBELL_ENABLE
	.comm	_GEN9_GT_PM_CONFIG,4,2          ; @GEN9_GT_PM_CONFIG
	.comm	_GEN7_MISCCPCTL,4,2             ; @GEN7_MISCCPCTL
	.comm	_GEN8_DOP_CLOCK_GATE_GUC_ENABLE,4,2 ; @GEN8_DOP_CLOCK_GATE_GUC_ENABLE
	.comm	_GUC_ARAT_C6DIS,4,2             ; @GUC_ARAT_C6DIS
	.no_dead_strip	_guc_prepare_xfer
.subsections_via_symbols
