	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4                               ## -- Begin function gfx_v7_0_gpu_early_init
LCPI0_0:
	.long	1                               ## 0x1
	.long	4                               ## 0x4
	.long	8                               ## 0x8
	.long	1                               ## 0x1
LCPI0_1:
	.long	4                               ## 0x4
	.long	16                              ## 0x10
	.long	11                              ## 0xb
	.long	1                               ## 0x1
LCPI0_2:
	.long	2                               ## 0x2
	.long	4                               ## 0x4
	.long	7                               ## 0x7
	.long	1                               ## 0x1
LCPI0_3:
	.long	1                               ## 0x1
	.long	2                               ## 0x2
	.long	2                               ## 0x2
	.long	1                               ## 0x1
LCPI0_4:
	.long	8                               ## 0x8
	.long	32                              ## 0x20
	.long	256                             ## 0x100
	.long	48                              ## 0x30
LCPI0_5:
	.long	3                               ## 0x3
	.long	3                               ## 0x3
	.long	3                               ## 0x3
	.long	3                               ## 0x3
LCPI0_6:
	.long	4294967291                      ## 0xfffffffb
	.long	4294967291                      ## 0xfffffffb
	.long	4294967291                      ## 0xfffffffb
	.long	4294967291                      ## 0xfffffffb
LCPI0_7:
	.long	12                              ## 0xc
	.long	12                              ## 0xc
	.long	12                              ## 0xc
	.long	12                              ## 0xc
LCPI0_8:
	.long	11                              ## 0xb
	.long	11                              ## 0xb
	.long	11                              ## 0xb
	.long	11                              ## 0xb
LCPI0_9:
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
LCPI0_10:
	.long	2                               ## 0x2
	.long	32                              ## 0x20
	.long	1                               ## 0x1
	.long	64                              ## 0x40
LCPI0_11:
	.long	1                               ## 0x1
	.long	32                              ## 0x20
	.long	1                               ## 0x1
	.long	64                              ## 0x40
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	4, 0x90
_gfx_v7_0_gpu_early_init:               ## @gfx_v7_0_gpu_early_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movl	(%rdi), %eax
	cmpl	$129, %eax
	je	LBB0_5
## %bb.1:
	cmpl	$131, %eax
	je	LBB0_4
## %bb.2:
	cmpl	$132, %eax
	jne	LBB0_6
## %bb.3:
	movaps	LCPI0_2(%rip), %xmm0            ## xmm0 = [2,4,7,1]
	movups	%xmm0, 8(%rbx)
	movl	$2, 24(%rbx)
	movq	_BONAIRE_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %rax
	movl	$32, %ecx
	movl	$4, %edx
	jmp	LBB0_7
LBB0_5:
	movl	$2, 24(%rbx)
	movaps	LCPI0_0(%rip), %xmm0            ## xmm0 = [1,4,8,1]
	movups	%xmm0, 8(%rbx)
	movq	_BONAIRE_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %rax
	movl	$16, %ecx
	movl	$4, %edx
	jmp	LBB0_7
LBB0_4:
	movaps	LCPI0_1(%rip), %xmm0            ## xmm0 = [4,16,11,1]
	movups	%xmm0, 8(%rbx)
	movl	$4, 24(%rbx)
	movq	_HAWAII_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %rax
	movl	$32, %ecx
	movl	$16, %edx
	jmp	LBB0_7
LBB0_6:
	movaps	LCPI0_3(%rip), %xmm0            ## xmm0 = [1,2,2,1]
	movups	%xmm0, 8(%rbx)
	movl	$1, 24(%rbx)
	movq	_BONAIRE_GB_ADDR_CONFIG_GOLDEN@GOTPCREL(%rip), %rax
	movl	$16, %ecx
	movl	$2, %edx
LBB0_7:
	movl	%edx, 28(%rbx)
	movl	$256, 32(%rbx)                  ## imm = 0x100
	movl	%ecx, 36(%rbx)
	movaps	LCPI0_4(%rip), %xmm0            ## xmm0 = [8,32,256,48]
	movups	%xmm0, 40(%rbx)
	movl	$304, 56(%rbx)                  ## imm = 0x130
	movl	(%rax), %r14d
	movq	_mmMC_SHARED_CHMAP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_mmMC_ARB_RAMCFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, 60(%rbx)
	movl	12(%rbx), %ecx
	movl	%ecx, 64(%rbx)
	movl	$256, 68(%rbx)                  ## imm = 0x100
	movq	_AMD_IS_APU@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, 4(%rbx)
	je	LBB0_11
## %bb.8:
	movl	%r14d, -44(%rbp)                ## 4-byte Spill
	movq	_mmMC_FUS_DRAM0_BANK_ADDR_MAPPING@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	%rax, %r15
	movq	_MC_FUS_DRAM0_BANK_ADDR_MAPPING@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	_DIMM0ADDRMAP@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	movl	%r15d, %edi
	callq	_REG_GET_FIELD
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movl	(%r12), %esi
	movq	_DIMM1ADDRMAP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r15d, %edi
	callq	_REG_GET_FIELD
	movl	%eax, %r15d
	movq	_mmMC_FUS_DRAM1_BANK_ADDR_MAPPING@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	%rax, %r12
	movq	_MC_FUS_DRAM1_BANK_ADDR_MAPPING@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movl	(%r13), %edx
	movl	%r12d, %edi
	callq	_REG_GET_FIELD
	movl	%eax, %r13d
	movl	(%r14), %esi
	movq	_DIMM1ADDRMAP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%r12d, %edi
	callq	_REG_GET_FIELD
	movd	-48(%rbp), %xmm0                ## 4-byte Folded Reload
                                        ## xmm0 = mem[0],zero,zero,zero
	pinsrd	$1, %r15d, %xmm0
	pinsrd	$2, %r13d, %xmm0
	pinsrd	$3, %eax, %xmm0
	movdqa	LCPI0_5(%rip), %xmm1            ## xmm1 = [3,3,3,3]
	pcmpeqd	%xmm0, %xmm1
	movdqa	LCPI0_6(%rip), %xmm2            ## xmm2 = [4294967291,4294967291,4294967291,4294967291]
	pand	%xmm0, %xmm2
	pxor	%xmm3, %xmm3
	pcmpeqd	%xmm2, %xmm3
	movdqa	%xmm0, %xmm2
	pcmpgtd	LCPI0_7(%rip), %xmm2
	por	%xmm1, %xmm2
	por	%xmm3, %xmm2
	pcmpeqd	LCPI0_8(%rip), %xmm0
	pxor	LCPI0_9(%rip), %xmm2
	pand	%xmm0, %xmm2
	pslld	$31, %xmm2
	movmskps	%xmm2, %eax
	testl	%eax, %eax
	je	LBB0_10
## %bb.9:
	movaps	LCPI0_10(%rip), %xmm0           ## xmm0 = [2,32,1,64]
	movups	%xmm0, 72(%rbx)
	movq	_GB_ADDR_CONFIG__ROW_SIZE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	movl	-44(%rbp), %r14d                ## 4-byte Reload
	andl	%eax, %r14d
	jmp	LBB0_15
LBB0_11:
	movq	_MC_ARB_RAMCFG__NOOFCOLS_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_MC_ARB_RAMCFG__NOOFCOLS__SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	addb	$8, %al
	movl	$4, %edx
	movl	$4, %esi
	movl	%eax, %ecx
	shll	%cl, %esi
	cmpl	$5119, %esi                     ## imm = 0x13FF
	jg	LBB0_13
## %bb.12:
	leal	1023(%rsi), %edx
	testl	%esi, %esi
	cmovnsl	%esi, %edx
	sarl	$10, %edx
LBB0_13:
	movl	%edx, 72(%rbx)
	movabsq	$4294967328, %rax               ## imm = 0x100000020
	movq	%rax, 76(%rbx)
	movl	$64, 84(%rbx)
	movq	_GB_ADDR_CONFIG__ROW_SIZE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r14d
	cmpl	$4, %edx
	je	LBB0_16
## %bb.14:
	cmpl	$2, %edx
	jne	LBB0_17
LBB0_15:
	movq	_GB_ADDR_CONFIG__ROW_SIZE__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	btsl	%eax, %r14d
	jmp	LBB0_17
LBB0_10:
	movaps	LCPI0_11(%rip), %xmm0           ## xmm0 = [1,32,1,64]
	movups	%xmm0, 72(%rbx)
	movq	_GB_ADDR_CONFIG__ROW_SIZE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	movl	-44(%rbp), %r14d                ## 4-byte Reload
	andl	%eax, %r14d
	jmp	LBB0_17
LBB0_16:
	movq	_GB_ADDR_CONFIG__ROW_SIZE__SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %eax
	shll	%cl, %eax
	orl	%eax, %r14d
LBB0_17:
	movl	%r14d, 88(%rbx)
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_BONAIRE_GB_ADDR_CONFIG_GOLDEN,4,2 ## @BONAIRE_GB_ADDR_CONFIG_GOLDEN
	.comm	_HAWAII_GB_ADDR_CONFIG_GOLDEN,4,2 ## @HAWAII_GB_ADDR_CONFIG_GOLDEN
	.comm	_mmMC_SHARED_CHMAP,4,2          ## @mmMC_SHARED_CHMAP
	.comm	_mmMC_ARB_RAMCFG,4,2            ## @mmMC_ARB_RAMCFG
	.comm	_AMD_IS_APU,4,2                 ## @AMD_IS_APU
	.comm	_mmMC_FUS_DRAM0_BANK_ADDR_MAPPING,4,2 ## @mmMC_FUS_DRAM0_BANK_ADDR_MAPPING
	.comm	_MC_FUS_DRAM0_BANK_ADDR_MAPPING,4,2 ## @MC_FUS_DRAM0_BANK_ADDR_MAPPING
	.comm	_DIMM0ADDRMAP,4,2               ## @DIMM0ADDRMAP
	.comm	_DIMM1ADDRMAP,4,2               ## @DIMM1ADDRMAP
	.comm	_mmMC_FUS_DRAM1_BANK_ADDR_MAPPING,4,2 ## @mmMC_FUS_DRAM1_BANK_ADDR_MAPPING
	.comm	_MC_FUS_DRAM1_BANK_ADDR_MAPPING,4,2 ## @MC_FUS_DRAM1_BANK_ADDR_MAPPING
	.comm	_MC_ARB_RAMCFG__NOOFCOLS_MASK,4,2 ## @MC_ARB_RAMCFG__NOOFCOLS_MASK
	.comm	_MC_ARB_RAMCFG__NOOFCOLS__SHIFT,4,2 ## @MC_ARB_RAMCFG__NOOFCOLS__SHIFT
	.comm	_GB_ADDR_CONFIG__ROW_SIZE_MASK,4,2 ## @GB_ADDR_CONFIG__ROW_SIZE_MASK
	.comm	_GB_ADDR_CONFIG__ROW_SIZE__SHIFT,4,2 ## @GB_ADDR_CONFIG__ROW_SIZE__SHIFT
	.no_dead_strip	_gfx_v7_0_gpu_early_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4                               ; -- Begin function gfx_v7_0_gpu_early_init
lCPI0_0:
	.long	1                               ; 0x1
	.long	4                               ; 0x4
	.long	8                               ; 0x8
	.long	1                               ; 0x1
lCPI0_1:
	.long	4                               ; 0x4
	.long	16                              ; 0x10
	.long	11                              ; 0xb
	.long	1                               ; 0x1
lCPI0_2:
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	1                               ; 0x1
lCPI0_3:
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	1                               ; 0x1
lCPI0_4:
	.long	8                               ; 0x8
	.long	32                              ; 0x20
	.long	256                             ; 0x100
	.long	48                              ; 0x30
lCPI0_5:
	.long	2                               ; 0x2
	.long	32                              ; 0x20
	.long	1                               ; 0x1
	.long	64                              ; 0x40
lCPI0_6:
	.long	1                               ; 0x1
	.long	32                              ; 0x20
	.long	1                               ; 0x1
	.long	64                              ; 0x40
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3
lCPI0_7:
	.long	32                              ; 0x20
	.long	1                               ; 0x1
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	2
_gfx_v7_0_gpu_early_init:               ; @gfx_v7_0_gpu_early_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldr	w8, [x0]
	cmp	w8, #129
	b.eq	LBB0_4
; %bb.1:
	cmp	w8, #131
	b.eq	LBB0_5
; %bb.2:
	cmp	w8, #132
	b.ne	LBB0_6
; %bb.3:
Lloh0:
	adrp	x8, lCPI0_2@PAGE
Lloh1:
	ldr	q0, [x8, lCPI0_2@PAGEOFF]
	stur	q0, [x19, #8]
	mov	w8, #2
	str	w8, [x19, #24]
Lloh2:
	adrp	x8, _BONAIRE_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh3:
	ldr	x8, [x8, _BONAIRE_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
	mov	w9, #32
	mov	w10, #4
	b	LBB0_7
LBB0_4:
	mov	w8, #2
	str	w8, [x19, #24]
Lloh4:
	adrp	x8, lCPI0_0@PAGE
Lloh5:
	ldr	q0, [x8, lCPI0_0@PAGEOFF]
	stur	q0, [x19, #8]
Lloh6:
	adrp	x8, _BONAIRE_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh7:
	ldr	x8, [x8, _BONAIRE_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
	mov	w9, #16
	mov	w10, #4
	b	LBB0_7
LBB0_5:
Lloh8:
	adrp	x8, lCPI0_1@PAGE
Lloh9:
	ldr	q0, [x8, lCPI0_1@PAGEOFF]
	stur	q0, [x19, #8]
	mov	w8, #4
	str	w8, [x19, #24]
Lloh10:
	adrp	x8, _HAWAII_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh11:
	ldr	x8, [x8, _HAWAII_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
	mov	w9, #32
	mov	w10, #16
	b	LBB0_7
LBB0_6:
Lloh12:
	adrp	x8, lCPI0_3@PAGE
Lloh13:
	ldr	q0, [x8, lCPI0_3@PAGEOFF]
	stur	q0, [x19, #8]
	mov	w8, #1
	str	w8, [x19, #24]
Lloh14:
	adrp	x8, _BONAIRE_GB_ADDR_CONFIG_GOLDEN@GOTPAGE
Lloh15:
	ldr	x8, [x8, _BONAIRE_GB_ADDR_CONFIG_GOLDEN@GOTPAGEOFF]
	mov	w9, #16
	mov	w10, #2
LBB0_7:
	mov	w20, #256
	stp	w10, w20, [x19, #28]
	str	w9, [x19, #36]
Lloh16:
	adrp	x9, lCPI0_4@PAGE
Lloh17:
	ldr	q0, [x9, lCPI0_4@PAGEOFF]
	stur	q0, [x19, #40]
	mov	w9, #304
	str	w9, [x19, #56]
	ldr	w24, [x8]
Lloh18:
	adrp	x8, _mmMC_SHARED_CHMAP@GOTPAGE
Lloh19:
	ldr	x8, [x8, _mmMC_SHARED_CHMAP@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
	bl	_RREG32
Lloh21:
	adrp	x8, _mmMC_ARB_RAMCFG@GOTPAGE
Lloh22:
	ldr	x8, [x8, _mmMC_ARB_RAMCFG@GOTPAGEOFF]
Lloh23:
	ldr	w0, [x8]
	bl	_RREG32
	ldr	w8, [x19, #12]
	stp	w0, w8, [x19, #60]
	str	w20, [x19, #68]
	ldr	w8, [x19, #4]
Lloh24:
	adrp	x9, _AMD_IS_APU@GOTPAGE
Lloh25:
	ldr	x9, [x9, _AMD_IS_APU@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_10
; %bb.8:
Lloh27:
	adrp	x8, _mmMC_FUS_DRAM0_BANK_ADDR_MAPPING@GOTPAGE
Lloh28:
	ldr	x8, [x8, _mmMC_FUS_DRAM0_BANK_ADDR_MAPPING@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x20, x0
Lloh30:
	adrp	x22, _MC_FUS_DRAM0_BANK_ADDR_MAPPING@GOTPAGE
Lloh31:
	ldr	x22, [x22, _MC_FUS_DRAM0_BANK_ADDR_MAPPING@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh32:
	adrp	x23, _DIMM0ADDRMAP@GOTPAGE
Lloh33:
	ldr	x23, [x23, _DIMM0ADDRMAP@GOTPAGEOFF]
	ldr	w2, [x23]
	bl	_REG_GET_FIELD
	mov	x21, x0
	ldr	w1, [x22]
Lloh34:
	adrp	x25, _DIMM1ADDRMAP@GOTPAGE
Lloh35:
	ldr	x25, [x25, _DIMM1ADDRMAP@GOTPAGEOFF]
	ldr	w2, [x25]
	mov	x0, x20
	bl	_REG_GET_FIELD
	mov	x20, x0
Lloh36:
	adrp	x8, _mmMC_FUS_DRAM1_BANK_ADDR_MAPPING@GOTPAGE
Lloh37:
	ldr	x8, [x8, _mmMC_FUS_DRAM1_BANK_ADDR_MAPPING@GOTPAGEOFF]
Lloh38:
	ldr	w0, [x8]
	bl	_RREG32
	mov	x22, x0
Lloh39:
	adrp	x26, _MC_FUS_DRAM1_BANK_ADDR_MAPPING@GOTPAGE
Lloh40:
	ldr	x26, [x26, _MC_FUS_DRAM1_BANK_ADDR_MAPPING@GOTPAGEOFF]
	ldr	w1, [x26]
	ldr	w2, [x23]
	bl	_REG_GET_FIELD
	mov	x23, x0
	ldr	w1, [x26]
	ldr	w2, [x25]
	mov	x0, x22
	bl	_REG_GET_FIELD
	fmov	s0, w21
	mov.s	v0[1], w20
	mov.s	v0[2], w23
	mov.s	v0[3], w0
	movi.4s	v1, #3
	cmeq.4s	v1, v0, v1
	movi.4s	v2, #12
	cmgt.4s	v2, v0, v2
	movi.4s	v3, #11
	cmeq.4s	v3, v0, v3
	bic.4s	v0, #4
	cmeq.4s	v0, v0, #0
	orr.16b	v0, v1, v0
	orr.16b	v0, v2, v0
	xtn.4h	v0, v0
	xtn.4h	v1, v3
	movi.4h	v2, #1
	eor.8b	v0, v0, v2
	and.8b	v0, v0, v1
	umov.h	w8, v0[0]
	umov.h	w9, v0[1]
	and	w9, w9, #0x1
	bfi	w8, w9, #1, #1
	umov.h	w9, v0[2]
	and	w9, w9, #0x1
	bfi	w8, w9, #2, #1
	umov.h	w9, v0[3]
	bfi	w8, w9, #3, #29
	tst	w8, #0xf
	b.eq	LBB0_13
; %bb.9:
Lloh41:
	adrp	x8, lCPI0_5@PAGE
Lloh42:
	ldr	q0, [x8, lCPI0_5@PAGEOFF]
	stur	q0, [x19, #72]
Lloh43:
	adrp	x8, _GB_ADDR_CONFIG__ROW_SIZE_MASK@GOTPAGE
Lloh44:
	ldr	x8, [x8, _GB_ADDR_CONFIG__ROW_SIZE_MASK@GOTPAGEOFF]
Lloh45:
	ldr	w8, [x8]
	bic	w8, w24, w8
	b	LBB0_12
LBB0_10:
Lloh46:
	adrp	x8, _MC_ARB_RAMCFG__NOOFCOLS_MASK@GOTPAGE
Lloh47:
	ldr	x8, [x8, _MC_ARB_RAMCFG__NOOFCOLS_MASK@GOTPAGEOFF]
Lloh48:
	ldr	w8, [x8]
Lloh49:
	adrp	x9, _MC_ARB_RAMCFG__NOOFCOLS__SHIFT@GOTPAGE
Lloh50:
	ldr	x9, [x9, _MC_ARB_RAMCFG__NOOFCOLS__SHIFT@GOTPAGEOFF]
	and	w8, w8, w0
Lloh51:
	ldr	w9, [x9]
	asr	w8, w8, w9
	add	w8, w8, #8
	mov	w9, #4
	lsl	w8, w9, w8
	add	w10, w8, #1023
	cmp	w8, #0
	csel	w10, w10, w8, lt
	asr	w10, w10, #10
	mov	w11, #5119
	cmp	w8, w11
	csel	w9, w9, w10, gt
	str	w9, [x19, #72]
Lloh52:
	adrp	x8, lCPI0_7@PAGE
Lloh53:
	ldr	d0, [x8, lCPI0_7@PAGEOFF]
	stur	d0, [x19, #76]
	mov	w8, #64
	str	w8, [x19, #84]
Lloh54:
	adrp	x8, _GB_ADDR_CONFIG__ROW_SIZE_MASK@GOTPAGE
Lloh55:
	ldr	x8, [x8, _GB_ADDR_CONFIG__ROW_SIZE_MASK@GOTPAGEOFF]
Lloh56:
	ldr	w8, [x8]
	bic	w8, w24, w8
	cmp	w9, #4
	b.eq	LBB0_14
; %bb.11:
	cmp	w9, #2
	b.ne	LBB0_16
LBB0_12:
Lloh57:
	adrp	x9, _GB_ADDR_CONFIG__ROW_SIZE__SHIFT@GOTPAGE
Lloh58:
	ldr	x9, [x9, _GB_ADDR_CONFIG__ROW_SIZE__SHIFT@GOTPAGEOFF]
Lloh59:
	ldr	w9, [x9]
	mov	w10, #1
	b	LBB0_15
LBB0_13:
Lloh60:
	adrp	x8, lCPI0_6@PAGE
Lloh61:
	ldr	q0, [x8, lCPI0_6@PAGEOFF]
	stur	q0, [x19, #72]
Lloh62:
	adrp	x8, _GB_ADDR_CONFIG__ROW_SIZE_MASK@GOTPAGE
Lloh63:
	ldr	x8, [x8, _GB_ADDR_CONFIG__ROW_SIZE_MASK@GOTPAGEOFF]
Lloh64:
	ldr	w8, [x8]
	bic	w8, w24, w8
	b	LBB0_16
LBB0_14:
Lloh65:
	adrp	x9, _GB_ADDR_CONFIG__ROW_SIZE__SHIFT@GOTPAGE
Lloh66:
	ldr	x9, [x9, _GB_ADDR_CONFIG__ROW_SIZE__SHIFT@GOTPAGEOFF]
Lloh67:
	ldr	w9, [x9]
	mov	w10, #2
LBB0_15:
	lsl	w9, w10, w9
	orr	w8, w9, w8
LBB0_16:
	str	w8, [x19, #88]
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdr	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpAdrp	Lloh4, Lloh6
	.loh AdrpLdr	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdr	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdr	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdr	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpAdrp	Lloh41, Lloh43
	.loh AdrpLdr	Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdr	Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpAdrp	Lloh60, Lloh62
	.loh AdrpLdr	Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.cfi_endproc
                                        ; -- End function
	.comm	_BONAIRE_GB_ADDR_CONFIG_GOLDEN,4,2 ; @BONAIRE_GB_ADDR_CONFIG_GOLDEN
	.comm	_HAWAII_GB_ADDR_CONFIG_GOLDEN,4,2 ; @HAWAII_GB_ADDR_CONFIG_GOLDEN
	.comm	_mmMC_SHARED_CHMAP,4,2          ; @mmMC_SHARED_CHMAP
	.comm	_mmMC_ARB_RAMCFG,4,2            ; @mmMC_ARB_RAMCFG
	.comm	_AMD_IS_APU,4,2                 ; @AMD_IS_APU
	.comm	_mmMC_FUS_DRAM0_BANK_ADDR_MAPPING,4,2 ; @mmMC_FUS_DRAM0_BANK_ADDR_MAPPING
	.comm	_MC_FUS_DRAM0_BANK_ADDR_MAPPING,4,2 ; @MC_FUS_DRAM0_BANK_ADDR_MAPPING
	.comm	_DIMM0ADDRMAP,4,2               ; @DIMM0ADDRMAP
	.comm	_DIMM1ADDRMAP,4,2               ; @DIMM1ADDRMAP
	.comm	_mmMC_FUS_DRAM1_BANK_ADDR_MAPPING,4,2 ; @mmMC_FUS_DRAM1_BANK_ADDR_MAPPING
	.comm	_MC_FUS_DRAM1_BANK_ADDR_MAPPING,4,2 ; @MC_FUS_DRAM1_BANK_ADDR_MAPPING
	.comm	_MC_ARB_RAMCFG__NOOFCOLS_MASK,4,2 ; @MC_ARB_RAMCFG__NOOFCOLS_MASK
	.comm	_MC_ARB_RAMCFG__NOOFCOLS__SHIFT,4,2 ; @MC_ARB_RAMCFG__NOOFCOLS__SHIFT
	.comm	_GB_ADDR_CONFIG__ROW_SIZE_MASK,4,2 ; @GB_ADDR_CONFIG__ROW_SIZE_MASK
	.comm	_GB_ADDR_CONFIG__ROW_SIZE__SHIFT,4,2 ; @GB_ADDR_CONFIG__ROW_SIZE__SHIFT
	.no_dead_strip	_gfx_v7_0_gpu_early_init
.subsections_via_symbols
