	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_vm_update_page_directory ## -- Begin function radeon_vm_update_page_directory
	.p2align	4, 0x90
_radeon_vm_update_page_directory:       ## @radeon_vm_update_page_directory
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$104, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %rbx
	movq	%rdi, %r14
	movq	16(%rsi), %r15
	movq	%r15, %rdi
	callq	_radeon_bo_gpu_offset
	movq	%rax, -128(%rbp)                ## 8-byte Spill
	movl	(%rbx), %eax
	leal	(%rax,%rax,2), %eax
	leal	(%rax,%rax), %ecx
	addl	$64, %ecx
	cmpl	$1048576, %ecx                  ## imm = 0x100000
	jb	LBB0_2
## %bb.1:
	movq	_ENOMEM@GOTPCREL(%rip), %rax
	xorl	%r14d, %r14d
	subl	(%rax), %r14d
	jmp	LBB0_22
LBB0_2:
	movq	%rbx, -64(%rbp)                 ## 8-byte Spill
	movq	_RADEON_VM_PTE_COUNT@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_R600_RING_TYPE_DMA_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leal	(,%rcx,4), %r8d
	xorl	%r13d, %r13d
	leaq	-96(%rbp), %rdx
	movq	%r14, -104(%rbp)                ## 8-byte Spill
	movq	%r14, %rdi
	movq	%rcx, %r12
	xorl	%ecx, %ecx
	callq	_radeon_ib_get
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	LBB0_22
## %bb.3:
	movq	%r12, -112(%rbp)                ## 8-byte Spill
	movq	%r15, -120(%rbp)                ## 8-byte Spill
	shll	$3, %ebx
	movl	%ebx, -52(%rbp)                 ## 4-byte Spill
	movl	$0, -96(%rbp)
	movq	$-1, -72(%rbp)                  ## 8-byte Folded Spill
	movq	$-1, -48(%rbp)                  ## 8-byte Folded Spill
	xorl	%r15d, %r15d
	xorl	%r12d, %r12d
	movq	-64(%rbp), %r14                 ## 8-byte Reload
	jmp	LBB0_9
	.p2align	4, 0x90
LBB0_4:                                 ##   in Loop: Header=BB0_9 Depth=1
	testl	%r12d, %r12d
	je	LBB0_14
## %bb.5:                               ##   in Loop: Header=BB0_9 Depth=1
	movq	_R600_PTE_VALID@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, (%rsp)
	movq	-104(%rbp), %rdi                ## 8-byte Reload
	leaq	-96(%rbp), %rsi
	movq	%rcx, %rbx
	movq	-48(%rbp), %rcx                 ## 8-byte Reload
	movl	%r12d, %r8d
	callq	_radeon_vm_set_pages
	movl	$1, %r12d
	movq	%rbx, -48(%rbp)                 ## 8-byte Spill
LBB0_6:                                 ##   in Loop: Header=BB0_9 Depth=1
	movq	%r14, -72(%rbp)                 ## 8-byte Spill
LBB0_7:                                 ##   in Loop: Header=BB0_9 Depth=1
	movq	-64(%rbp), %r14                 ## 8-byte Reload
LBB0_8:                                 ##   in Loop: Header=BB0_9 Depth=1
	incl	%r15d
	addl	$8, %r13d
	cmpl	(%r14), %r15d
	ja	LBB0_15
LBB0_9:                                 ## =>This Inner Loop Header: Depth=1
	movq	8(%r14), %rax
	movl	%r15d, %r15d
	movq	%r15, %rbx
	shlq	$4, %rbx
	movq	8(%rax,%rbx), %rdi
	testq	%rdi, %rdi
	je	LBB0_8
## %bb.10:                              ##   in Loop: Header=BB0_9 Depth=1
	callq	_radeon_bo_gpu_offset
	movq	%rax, %rcx
	movq	8(%r14), %rax
	cmpq	%rcx, (%rax,%rbx)
	je	LBB0_8
## %bb.11:                              ##   in Loop: Header=BB0_9 Depth=1
	addq	%rbx, %rax
	movq	%rcx, (%rax)
	movl	%r13d, %r14d
	addq	-128(%rbp), %r14                ## 8-byte Folded Reload
	leal	(,%r12,8), %eax
	movq	-72(%rbp), %rdx                 ## 8-byte Reload
	addq	%rdx, %rax
	cmpq	%r14, %rax
	movl	-52(%rbp), %r9d                 ## 4-byte Reload
	jne	LBB0_4
## %bb.12:                              ##   in Loop: Header=BB0_9 Depth=1
	movl	%r12d, %eax
	imull	%r9d, %eax
	addq	-48(%rbp), %rax                 ## 8-byte Folded Reload
	cmpq	%rcx, %rax
	jne	LBB0_4
## %bb.13:                              ##   in Loop: Header=BB0_9 Depth=1
	incl	%r12d
	jmp	LBB0_7
LBB0_14:                                ##   in Loop: Header=BB0_9 Depth=1
	movl	$1, %r12d
	movq	%rcx, -48(%rbp)                 ## 8-byte Spill
	jmp	LBB0_6
LBB0_15:
	testl	%r12d, %r12d
	movq	-104(%rbp), %rbx                ## 8-byte Reload
	movq	-120(%rbp), %r15                ## 8-byte Reload
	je	LBB0_17
## %bb.16:
	movq	_R600_PTE_VALID@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, (%rsp)
	leaq	-96(%rbp), %rsi
	movq	%rbx, %rdi
	movq	-72(%rbp), %rdx                 ## 8-byte Reload
	movq	-48(%rbp), %rcx                 ## 8-byte Reload
	movl	%r12d, %r8d
	movl	-52(%rbp), %r9d                 ## 4-byte Reload
	callq	_radeon_vm_set_pages
LBB0_17:
	cmpl	$0, -96(%rbp)
	je	LBB0_21
## %bb.18:
	leaq	-96(%rbp), %r14
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	_radeon_asic_vm_pad_ib
	leaq	-80(%rbp), %rsi
	movl	(%r15), %edx
	movq	%rbx, %rdi
	movl	$1, %ecx
	callq	_radeon_sync_resv
	xorl	%edi, %edi
	movq	-112(%rbp), %rax                ## 8-byte Reload
	cmpl	%eax, -96(%rbp)
	seta	%dil
	callq	_WARN_ON
	movq	%rbx, %rdi
	movq	%r14, %rsi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	callq	_radeon_ib_schedule
	testl	%eax, %eax
	je	LBB0_20
## %bb.19:
	movl	%eax, %r14d
	leaq	-96(%rbp), %rsi
	movq	%rbx, %rdi
	callq	_radeon_ib_free
	jmp	LBB0_22
LBB0_20:
	movq	-88(%rbp), %rsi
	movl	$1, (%rsi)
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_radeon_bo_fence
LBB0_21:
	leaq	-96(%rbp), %rsi
	movq	%rbx, %rdi
	callq	_radeon_ib_free
	xorl	%r14d, %r14d
LBB0_22:
	movl	%r14d, %eax
	addq	$104, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RADEON_VM_PTE_COUNT,4,2        ## @RADEON_VM_PTE_COUNT
	.comm	_ENOMEM,4,2                     ## @ENOMEM
	.comm	_R600_RING_TYPE_DMA_INDEX,4,2   ## @R600_RING_TYPE_DMA_INDEX
	.comm	_R600_PTE_VALID,4,2             ## @R600_PTE_VALID
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_vm_update_page_directory ; -- Begin function radeon_vm_update_page_directory
	.p2align	2
_radeon_vm_update_page_directory:       ; @radeon_vm_update_page_directory
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #144
	.cfi_def_cfa_offset 144
	stp	x28, x27, [sp, #48]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #64]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #80]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #96]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #112]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #128]            ; 16-byte Folded Spill
	add	x29, sp, #128
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x1
	mov	x20, x0
	ldr	x24, [x1, #16]
	mov	x0, x24
	bl	_radeon_bo_gpu_offset
	ldr	w8, [x21]
	mov	w9, #6
	orr	w10, wzr, #0x40
	madd	w25, w8, w9, w10
	cmp	w25, #256, lsl #12              ; =1048576
	b.lo	LBB0_2
; %bb.1:
Lloh0:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh1:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	neg	w23, w8
	b	LBB0_20
LBB0_2:
	mov	x22, x0
Lloh3:
	adrp	x8, _RADEON_VM_PTE_COUNT@GOTPAGE
Lloh4:
	ldr	x8, [x8, _RADEON_VM_PTE_COUNT@GOTPAGEOFF]
Lloh5:
	ldr	w19, [x8]
Lloh6:
	adrp	x8, _R600_RING_TYPE_DMA_INDEX@GOTPAGE
Lloh7:
	ldr	x8, [x8, _R600_RING_TYPE_DMA_INDEX@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	lsl	w4, w25, #2
	add	x2, sp, #24
	mov	x0, x20
	mov	x3, #0
	bl	_radeon_ib_get
	mov	x23, x0
	cbnz	w0, LBB0_20
; %bb.3:
	str	w25, [sp, #4]                   ; 4-byte Folded Spill
	stp	x24, x20, [sp, #8]              ; 16-byte Folded Spill
	mov	w20, #0
	mov	w8, #0
	mov	w24, #0
	lsl	w23, w19, #3
	str	wzr, [sp, #24]
	mov	x28, #-1
	mov	x26, #-1
	b	LBB0_6
LBB0_4:                                 ;   in Loop: Header=BB0_6 Depth=1
	mov	w24, #1
	mov	x26, x27
	mov	x28, x25
LBB0_5:                                 ;   in Loop: Header=BB0_6 Depth=1
	add	w8, w19, #1
	ldr	w9, [x21]
	add	w20, w20, #8
	cmp	w8, w9
	b.hi	LBB0_13
LBB0_6:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x9, [x21, #8]
	mov	w19, w8
	add	x8, x9, w8, uxtw #4
	ldr	x0, [x8, #8]
	cbz	x0, LBB0_5
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=1
	bl	_radeon_bo_gpu_offset
	ldr	x8, [x21, #8]
	add	x8, x8, x19, lsl #4
	ldr	x9, [x8]
	cmp	x9, x0
	b.eq	LBB0_5
; %bb.8:                                ;   in Loop: Header=BB0_6 Depth=1
	mov	x27, x0
	str	x0, [x8]
	add	x25, x22, w20, uxtw
	lsl	w8, w24, #3
	add	x8, x28, x8
	cmp	x8, x25
	b.ne	LBB0_11
; %bb.9:                                ;   in Loop: Header=BB0_6 Depth=1
	mul	w8, w24, w23
	add	x8, x26, x8
	cmp	x8, x27
	b.ne	LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_6 Depth=1
	add	w24, w24, #1
	b	LBB0_5
LBB0_11:                                ;   in Loop: Header=BB0_6 Depth=1
	cbz	w24, LBB0_4
; %bb.12:                               ;   in Loop: Header=BB0_6 Depth=1
Lloh9:
	adrp	x8, _R600_PTE_VALID@GOTPAGE
Lloh10:
	ldr	x8, [x8, _R600_PTE_VALID@GOTPAGEOFF]
Lloh11:
	ldr	w6, [x8]
	add	x1, sp, #24
	ldr	x0, [sp, #16]                   ; 8-byte Folded Reload
	mov	x2, x28
	mov	x3, x26
	mov	x4, x24
	mov	x5, x23
	bl	_radeon_vm_set_pages
	b	LBB0_4
LBB0_13:
	ldr	x20, [sp, #16]                  ; 8-byte Folded Reload
	cbz	w24, LBB0_15
; %bb.14:
Lloh12:
	adrp	x8, _R600_PTE_VALID@GOTPAGE
Lloh13:
	ldr	x8, [x8, _R600_PTE_VALID@GOTPAGEOFF]
Lloh14:
	ldr	w6, [x8]
	add	x1, sp, #24
	mov	x0, x20
	mov	x2, x28
	mov	x3, x26
	mov	x4, x24
	mov	x5, x23
	bl	_radeon_vm_set_pages
LBB0_15:
	ldr	w8, [sp, #24]
	cbz	w8, LBB0_19
; %bb.16:
	add	x19, sp, #24
	add	x1, sp, #24
	mov	x0, x20
	bl	_radeon_asic_vm_pad_ib
	add	x1, x19, #16
	ldr	x21, [sp, #8]                   ; 8-byte Folded Reload
	ldr	w2, [x21]
	mov	w19, #1
	mov	x0, x20
	mov	w3, #1
	bl	_radeon_sync_resv
	ldr	w8, [sp, #24]
	ldr	w9, [sp, #4]                    ; 4-byte Folded Reload
	cmp	w8, w9
	cset	w0, hi
	bl	_WARN_ON
	add	x1, sp, #24
	mov	x0, x20
	mov	x2, #0
	mov	w3, #0
	bl	_radeon_ib_schedule
	cbz	w0, LBB0_18
; %bb.17:
	mov	x23, x0
	add	x1, sp, #24
	mov	x0, x20
	bl	_radeon_ib_free
	b	LBB0_20
LBB0_18:
	ldr	x1, [sp, #32]
	str	w19, [x1]
	mov	x0, x21
	mov	w2, #0
	bl	_radeon_bo_fence
LBB0_19:
	add	x1, sp, #24
	mov	x0, x20
	bl	_radeon_ib_free
	mov	w23, #0
LBB0_20:
	mov	x0, x23
	ldp	x29, x30, [sp, #128]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #112]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #96]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #80]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #64]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #144
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.cfi_endproc
                                        ; -- End function
	.comm	_RADEON_VM_PTE_COUNT,4,2        ; @RADEON_VM_PTE_COUNT
	.comm	_ENOMEM,4,2                     ; @ENOMEM
	.comm	_R600_RING_TYPE_DMA_INDEX,4,2   ; @R600_RING_TYPE_DMA_INDEX
	.comm	_R600_PTE_VALID,4,2             ; @R600_PTE_VALID
.subsections_via_symbols
