	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_bo_pin_restricted       ## -- Begin function radeon_bo_pin_restricted
	.p2align	4, 0x90
_radeon_bo_pin_restricted:              ## @radeon_bo_pin_restricted
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rcx, %r15
	movq	%rdx, %r14
	movq	%rsi, %r12
	movq	%rdi, %r13
	movq	$0, -64(%rbp)
	movl	20(%rdi), %edi
	callq	_radeon_ttm_tt_has_userptr
	testq	%rax, %rax
	je	LBB0_3
## %bb.1:
	movq	_EPERM@GOTPCREL(%rip), %rax
LBB0_2:
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
LBB0_26:
	movl	%ebx, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_3:
	movl	(%r13), %eax
	testl	%eax, %eax
	je	LBB0_8
## %bb.4:
	incl	%eax
	movl	%eax, (%r13)
	testq	%r15, %r15
	je	LBB0_6
## %bb.5:
	movq	%r13, %rdi
	callq	_radeon_bo_gpu_offset
	movq	%rax, (%r15)
LBB0_6:
	xorl	%ebx, %ebx
	testq	%r14, %r14
	je	LBB0_26
## %bb.7:
	movq	_RADEON_GEM_DOMAIN_VRAM@GOTPCREL(%rip), %rax
	xorl	%ecx, %ecx
	cmpq	%r12, (%rax)
	setne	%cl
	movq	8(%r13), %rax
	movq	16(%rax,%rcx,8), %r15
	movq	%r13, %rdi
	callq	_radeon_bo_gpu_offset
	subq	%r15, %rax
	xorl	%edi, %edi
	cmpq	%r14, %rax
	setg	%dil
	callq	_WARN_ON_ONCE
	jmp	LBB0_26
LBB0_8:
	cmpq	$0, 32(%r13)
	movq	_RADEON_GEM_DOMAIN_VRAM@GOTPCREL(%rip), %rax
	je	LBB0_11
## %bb.9:
	cmpq	%r12, (%rax)
	jne	LBB0_11
## %bb.10:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	jmp	LBB0_2
LBB0_11:
	leaq	20(%r13), %rax
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
	movq	%r13, %rdi
	movq	%r12, -48(%rbp)                 ## 8-byte Spill
	movq	%r12, %rsi
	callq	_radeon_ttm_placement_from_domain
	leaq	16(%r13), %rsi
	movl	16(%r13), %eax
	testl	%eax, %eax
	jle	LBB0_19
## %bb.12:
	movq	24(%r13), %rdx
	shlq	$4, %rax
	xorl	%edi, %edi
	movq	_TTM_PL_FLAG_VRAM@GOTPCREL(%rip), %r8
	movq	_PAGE_SHIFT@GOTPCREL(%rip), %r9
	movq	_TTM_PL_FLAG_NO_EVICT@GOTPCREL(%rip), %r11
	movq	_RADEON_GEM_NO_CPU_ACCESS@GOTPCREL(%rip), %r10
	jmp	LBB0_13
	.p2align	4, 0x90
LBB0_17:                                ##   in Loop: Header=BB0_13 Depth=1
	movq	%r14, %r12
LBB0_18:                                ##   in Loop: Header=BB0_13 Depth=1
	movzbl	(%r9), %ecx
	sarq	%cl, %r12
	movq	%r12, 8(%rdx,%rdi)
	orl	(%r11), %ebx
	movl	%ebx, (%rdx,%rdi)
	addq	$16, %rdi
	cmpq	%rdi, %rax
	je	LBB0_19
LBB0_13:                                ## =>This Inner Loop Header: Depth=1
	movl	(%rdx,%rdi), %ebx
	testl	%ebx, (%r8)
	je	LBB0_17
## %bb.14:                              ##   in Loop: Header=BB0_13 Depth=1
	movl	(%r10), %ecx
	testl	%ecx, 4(%r13)
	jne	LBB0_17
## %bb.15:                              ##   in Loop: Header=BB0_13 Depth=1
	movq	8(%r13), %rcx
	movq	32(%rcx), %r12
	testq	%r14, %r14
	je	LBB0_18
## %bb.16:                              ##   in Loop: Header=BB0_13 Depth=1
	cmpq	%r14, %r12
	jge	LBB0_17
	jmp	LBB0_18
LBB0_19:
	leaq	-64(%rbp), %rdx
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_ttm_bo_validate
	movl	%eax, %ebx
	xorl	%edi, %edi
	testl	%eax, %eax
	sete	%dil
	callq	_likely
	testq	%rax, %rax
	je	LBB0_25
## %bb.20:
	movl	$1, (%r13)
	testq	%r15, %r15
	je	LBB0_22
## %bb.21:
	movq	%r13, %rdi
	callq	_radeon_bo_gpu_offset
	movq	%rax, (%r15)
LBB0_22:
	movq	_RADEON_GEM_DOMAIN_VRAM@GOTPCREL(%rip), %rax
	movq	(%rax), %r14
	movq	%r13, %rdi
	callq	_radeon_bo_size
	movq	8(%r13), %rcx
	cmpq	-48(%rbp), %r14                 ## 8-byte Folded Reload
	jne	LBB0_24
## %bb.23:
	addl	%eax, 8(%rcx)
	jmp	LBB0_26
LBB0_25:
	movq	8(%r13), %rax
	movl	(%rax), %edi
	leaq	L_.str(%rip), %rsi
	movq	%r13, %rdx
	callq	_dev_err
	jmp	LBB0_26
LBB0_24:
	addl	%eax, 4(%rcx)
	jmp	LBB0_26
	.cfi_endproc
                                        ## -- End function
	.comm	_EPERM,4,2                      ## @EPERM
	.comm	_RADEON_GEM_DOMAIN_VRAM,8,3     ## @RADEON_GEM_DOMAIN_VRAM
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_TTM_PL_FLAG_VRAM,4,2           ## @TTM_PL_FLAG_VRAM
	.comm	_RADEON_GEM_NO_CPU_ACCESS,4,2   ## @RADEON_GEM_NO_CPU_ACCESS
	.comm	_PAGE_SHIFT,8,3                 ## @PAGE_SHIFT
	.comm	_TTM_PL_FLAG_NO_EVICT,4,2       ## @TTM_PL_FLAG_NO_EVICT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"%p pin failed\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_radeon_bo_pin_restricted       ; -- Begin function radeon_bo_pin_restricted
	.p2align	2
_radeon_bo_pin_restricted:              ; @radeon_bo_pin_restricted
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x21, x3
	mov	x22, x2
	mov	x20, x1
	mov	x19, x0
	str	xzr, [sp, #8]
	mov	x23, x0
	ldr	w0, [x23, #20]!
	bl	_radeon_ttm_tt_has_userptr
	cbz	x0, LBB0_4
; %bb.1:
Lloh0:
	adrp	x8, _EPERM@GOTPAGE
Lloh1:
	ldr	x8, [x8, _EPERM@GOTPAGEOFF]
LBB0_2:
	ldr	w8, [x8]
	neg	w22, w8
LBB0_3:
	mov	x0, x22
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
LBB0_4:
	ldr	w8, [x19]
	cbz	w8, LBB0_9
; %bb.5:
	add	w8, w8, #1
	str	w8, [x19]
	cbz	x21, LBB0_7
; %bb.6:
	mov	x0, x19
	bl	_radeon_bo_gpu_offset
	str	x0, [x21]
LBB0_7:
	cbz	x22, LBB0_3
; %bb.8:
Lloh2:
	adrp	x8, _RADEON_GEM_DOMAIN_VRAM@GOTPAGE
Lloh3:
	ldr	x8, [x8, _RADEON_GEM_DOMAIN_VRAM@GOTPAGEOFF]
Lloh4:
	ldr	x8, [x8]
	ldr	x9, [x19, #8]
	mov	w10, #24
	mov	w11, #16
	cmp	x8, x20
	csel	x8, x11, x10, eq
	ldr	x20, [x9, x8]
	mov	x0, x19
	bl	_radeon_bo_gpu_offset
	sub	x8, x0, x20
	cmp	x8, x22
	cset	w0, gt
	bl	_WARN_ON_ONCE
	mov	w22, #0
	b	LBB0_3
LBB0_9:
	ldr	x8, [x19, #32]
Lloh5:
	adrp	x24, _RADEON_GEM_DOMAIN_VRAM@GOTPAGE
Lloh6:
	ldr	x24, [x24, _RADEON_GEM_DOMAIN_VRAM@GOTPAGEOFF]
	cbz	x8, LBB0_12
; %bb.10:
	ldr	x8, [x24]
	cmp	x8, x20
	b.ne	LBB0_12
; %bb.11:
Lloh7:
	adrp	x8, _EINVAL@GOTPAGE
Lloh8:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
	b	LBB0_2
LBB0_12:
	mov	x0, x19
	mov	x1, x20
	bl	_radeon_ttm_placement_from_domain
	mov	x1, x19
	ldr	w8, [x1, #16]!
	cmp	w8, #1
	b.lt	LBB0_20
; %bb.13:
	ldr	x9, [x19, #24]
Lloh9:
	adrp	x10, _TTM_PL_FLAG_VRAM@GOTPAGE
Lloh10:
	ldr	x10, [x10, _TTM_PL_FLAG_VRAM@GOTPAGEOFF]
Lloh11:
	adrp	x11, _PAGE_SHIFT@GOTPAGE
Lloh12:
	ldr	x11, [x11, _PAGE_SHIFT@GOTPAGEOFF]
Lloh13:
	adrp	x12, _TTM_PL_FLAG_NO_EVICT@GOTPAGE
Lloh14:
	ldr	x12, [x12, _TTM_PL_FLAG_NO_EVICT@GOTPAGEOFF]
Lloh15:
	adrp	x13, _RADEON_GEM_NO_CPU_ACCESS@GOTPAGE
Lloh16:
	ldr	x13, [x13, _RADEON_GEM_NO_CPU_ACCESS@GOTPAGEOFF]
	b	LBB0_16
LBB0_14:                                ;   in Loop: Header=BB0_16 Depth=1
	mov	x15, x22
LBB0_15:                                ;   in Loop: Header=BB0_16 Depth=1
	ldr	x16, [x11]
	asr	x15, x15, x16
	str	x15, [x9, #8]
	ldr	w15, [x12]
	orr	w14, w15, w14
	str	w14, [x9], #16
	subs	x8, x8, #1
	b.eq	LBB0_20
LBB0_16:                                ; =>This Inner Loop Header: Depth=1
	ldr	w14, [x9]
	ldr	w15, [x10]
	tst	w15, w14
	b.eq	LBB0_14
; %bb.17:                               ;   in Loop: Header=BB0_16 Depth=1
	ldr	w15, [x19, #4]
	ldr	w16, [x13]
	tst	w16, w15
	b.ne	LBB0_14
; %bb.18:                               ;   in Loop: Header=BB0_16 Depth=1
	ldr	x15, [x19, #8]
	ldr	x15, [x15, #32]
	cbz	x22, LBB0_15
; %bb.19:                               ;   in Loop: Header=BB0_16 Depth=1
	cmp	x15, x22
	b.ge	LBB0_14
	b	LBB0_15
LBB0_20:
	add	x2, sp, #8
	mov	x0, x23
	bl	_ttm_bo_validate
	mov	x22, x0
	cmp	w0, #0
	cset	w0, eq
	bl	_likely
	cbz	x0, LBB0_25
; %bb.21:
	mov	w8, #1
	str	w8, [x19]
	cbz	x21, LBB0_23
; %bb.22:
	mov	x0, x19
	bl	_radeon_bo_gpu_offset
	str	x0, [x21]
LBB0_23:
	ldr	x21, [x24]
	mov	x0, x19
	bl	_radeon_bo_size
	ldr	x8, [x19, #8]
	cmp	x21, x20
	b.ne	LBB0_26
; %bb.24:
	ldr	w9, [x8, #8]
	add	w9, w9, w0
	str	w9, [x8, #8]
	b	LBB0_3
LBB0_25:
	ldr	x8, [x19, #8]
	ldr	w0, [x8]
Lloh17:
	adrp	x1, l_.str@PAGE
Lloh18:
	add	x1, x1, l_.str@PAGEOFF
	mov	x2, x19
	bl	_dev_err
	b	LBB0_3
LBB0_26:
	ldr	w9, [x8, #4]
	add	w9, w9, w0
	str	w9, [x8, #4]
	b	LBB0_3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpAdd	Lloh17, Lloh18
	.cfi_endproc
                                        ; -- End function
	.comm	_EPERM,4,2                      ; @EPERM
	.comm	_RADEON_GEM_DOMAIN_VRAM,8,3     ; @RADEON_GEM_DOMAIN_VRAM
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_TTM_PL_FLAG_VRAM,4,2           ; @TTM_PL_FLAG_VRAM
	.comm	_RADEON_GEM_NO_CPU_ACCESS,4,2   ; @RADEON_GEM_NO_CPU_ACCESS
	.comm	_PAGE_SHIFT,8,3                 ; @PAGE_SHIFT
	.comm	_TTM_PL_FLAG_NO_EVICT,4,2       ; @TTM_PL_FLAG_NO_EVICT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"%p pin failed\n"

.subsections_via_symbols
