	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4                               ## -- Begin function picolcd_fb_update_tile
LCPI0_0:
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	4, 0x90
_picolcd_fb_update_tile:                ## @picolcd_fb_update_tile
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	subq	$312, %rsp                      ## imm = 0x138
	.cfi_offset %rbx, -24
                                        ## kill: def $r8d killed $r8d def $r8
                                        ## kill: def $ecx killed $ecx def $rcx
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -16(%rbp)
	cmpl	$1, %edx
	je	LBB0_5
## %bb.1:
	cmpl	$8, %edx
	jne	LBB0_29
## %bb.2:
	movdqa	-272(%rbp), %xmm13
	movdqa	-256(%rbp), %xmm15
	movaps	-240(%rbp), %xmm0
	movaps	%xmm0, -288(%rbp)               ## 16-byte Spill
	movdqa	-224(%rbp), %xmm0
	movdqa	%xmm0, -304(%rbp)               ## 16-byte Spill
	movdqa	-208(%rbp), %xmm11
	movdqa	-192(%rbp), %xmm10
	movdqa	-176(%rbp), %xmm9
	movdqa	-160(%rbp), %xmm8
	movdqa	-144(%rbp), %xmm7
	movdqa	-128(%rbp), %xmm6
	movdqa	-112(%rbp), %xmm5
	movdqa	-96(%rbp), %xmm4
	movdqa	-80(%rbp), %xmm3
	movdqa	-64(%rbp), %xmm2
	movdqa	-48(%rbp), %xmm1
	movdqa	-32(%rbp), %xmm14
	movl	%r8d, %eax
	shll	$11, %eax
	movl	%ecx, %edx
	shll	$6, %edx
	leal	(%rax,%rdx), %r9d
	addl	$1792, %r9d                     ## imm = 0x700
	xorl	%edx, %edx
	.p2align	4, 0x90
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movdqa	%xmm1, -320(%rbp)               ## 16-byte Spill
	leal	(%r9,%rdx), %eax
	cltq
	movdqa	%xmm13, %xmm12
	paddd	%xmm13, %xmm12
	movdqu	(%rsi,%rax,4), %xmm13
	psrld	$7, %xmm13
	movdqa	LCPI0_0(%rip), %xmm1            ## xmm1 = [1,1,1,1]
	pand	%xmm1, %xmm13
	por	%xmm12, %xmm13
	movdqa	%xmm15, %xmm0
	paddd	%xmm15, %xmm0
	movdqu	16(%rsi,%rax,4), %xmm15
	psrld	$7, %xmm15
	movdqa	%xmm1, %xmm12
	pand	%xmm1, %xmm15
	por	%xmm0, %xmm15
	movdqa	-288(%rbp), %xmm0               ## 16-byte Reload
	paddd	%xmm0, %xmm0
	movdqu	32(%rsi,%rax,4), %xmm1
	psrld	$7, %xmm1
	pand	%xmm12, %xmm1
	por	%xmm0, %xmm1
	movdqa	%xmm1, -288(%rbp)               ## 16-byte Spill
	movdqa	-304(%rbp), %xmm0               ## 16-byte Reload
	paddd	%xmm0, %xmm0
	movdqu	48(%rsi,%rax,4), %xmm1
	psrld	$7, %xmm1
	pand	%xmm12, %xmm1
	por	%xmm0, %xmm1
	movdqa	%xmm1, -304(%rbp)               ## 16-byte Spill
	movdqa	%xmm11, %xmm0
	paddd	%xmm11, %xmm0
	movdqu	64(%rsi,%rax,4), %xmm11
	psrld	$7, %xmm11
	pand	%xmm12, %xmm11
	por	%xmm0, %xmm11
	movdqa	%xmm10, %xmm0
	paddd	%xmm10, %xmm0
	movdqu	80(%rsi,%rax,4), %xmm10
	psrld	$7, %xmm10
	pand	%xmm12, %xmm10
	por	%xmm0, %xmm10
	movdqa	%xmm9, %xmm0
	paddd	%xmm9, %xmm0
	movdqu	96(%rsi,%rax,4), %xmm9
	psrld	$7, %xmm9
	pand	%xmm12, %xmm9
	por	%xmm0, %xmm9
	movdqa	%xmm8, %xmm0
	paddd	%xmm8, %xmm0
	movdqu	112(%rsi,%rax,4), %xmm8
	psrld	$7, %xmm8
	pand	%xmm12, %xmm8
	por	%xmm0, %xmm8
	movdqa	%xmm7, %xmm0
	paddd	%xmm7, %xmm0
	movdqu	128(%rsi,%rax,4), %xmm7
	psrld	$7, %xmm7
	pand	%xmm12, %xmm7
	por	%xmm0, %xmm7
	movdqa	%xmm6, %xmm0
	paddd	%xmm6, %xmm0
	movdqu	144(%rsi,%rax,4), %xmm6
	psrld	$7, %xmm6
	pand	%xmm12, %xmm6
	por	%xmm0, %xmm6
	movdqa	%xmm5, %xmm0
	paddd	%xmm5, %xmm0
	movdqu	160(%rsi,%rax,4), %xmm5
	psrld	$7, %xmm5
	pand	%xmm12, %xmm5
	por	%xmm0, %xmm5
	movdqa	%xmm4, %xmm0
	paddd	%xmm4, %xmm0
	movdqu	176(%rsi,%rax,4), %xmm4
	psrld	$7, %xmm4
	pand	%xmm12, %xmm4
	por	%xmm0, %xmm4
	movdqa	%xmm3, %xmm0
	paddd	%xmm3, %xmm0
	movdqu	192(%rsi,%rax,4), %xmm3
	psrld	$7, %xmm3
	pand	%xmm12, %xmm3
	por	%xmm0, %xmm3
	movdqa	%xmm2, %xmm0
	paddd	%xmm2, %xmm0
	movdqu	208(%rsi,%rax,4), %xmm2
	psrld	$7, %xmm2
	pand	%xmm12, %xmm2
	por	%xmm0, %xmm2
	movdqa	-320(%rbp), %xmm0               ## 16-byte Reload
	paddd	%xmm0, %xmm0
	movdqu	224(%rsi,%rax,4), %xmm1
	psrld	$7, %xmm1
	pand	%xmm12, %xmm1
	por	%xmm0, %xmm1
	movdqa	%xmm14, %xmm0
	paddd	%xmm14, %xmm0
	movdqu	240(%rsi,%rax,4), %xmm14
	psrld	$7, %xmm14
	pand	%xmm12, %xmm14
	por	%xmm0, %xmm14
	addq	$-256, %rdx
	cmpq	$-2048, %rdx                    ## imm = 0xF800
	jne	LBB0_3
## %bb.4:
	movdqa	%xmm13, -272(%rbp)
	movdqa	%xmm15, -256(%rbp)
	movaps	-288(%rbp), %xmm0               ## 16-byte Reload
	movaps	%xmm0, -240(%rbp)
	movaps	-304(%rbp), %xmm0               ## 16-byte Reload
	movaps	%xmm0, -224(%rbp)
	movdqa	%xmm11, -208(%rbp)
	movdqa	%xmm10, -192(%rbp)
	movdqa	%xmm9, -176(%rbp)
	movdqa	%xmm8, -160(%rbp)
	movdqa	%xmm7, -144(%rbp)
	movdqa	%xmm6, -128(%rbp)
	movdqa	%xmm5, -112(%rbp)
	movdqa	%xmm4, -96(%rbp)
	movdqa	%xmm3, -80(%rbp)
	movdqa	%xmm2, -64(%rbp)
	movdqa	%xmm1, -48(%rbp)
	movdqa	%xmm14, -32(%rbp)
	jmp	LBB0_21
LBB0_5:
	movl	%r8d, %eax
	shll	$8, %eax
	cltq
	leaq	(%rsi,%rax,4), %rax
	leal	(,%rcx,8), %edx
	movslq	%edx, %rdx
	leaq	(%rax,%rdx,4), %r9
	xorl	%edx, %edx
	.p2align	4, 0x90
LBB0_6:                                 ## =>This Inner Loop Header: Depth=1
	movq	%rdx, %rsi
	shrq	%rsi
	andl	$2147483644, %esi               ## imm = 0x7FFFFFFC
	movl	896(%r9,%rsi), %r10d
	movl	%edx, %eax
	andb	$6, %al
	movzbl	%al, %r11d
	xorl	%eax, %eax
	btl	%r11d, %r10d
	setb	%al
	movl	-272(%rbp,%rdx,4), %r10d
	movl	-268(%rbp,%rdx,4), %r11d
	leal	(%rax,%r10,2), %eax
	movl	%eax, -272(%rbp,%rdx,4)
	movl	896(%r9,%rsi), %r10d
	leal	1(%rdx), %esi
	andb	$7, %sil
	movzbl	%sil, %esi
	xorl	%eax, %eax
	btl	%esi, %r10d
	setb	%al
	leal	(%rax,%r11,2), %eax
	movl	%eax, -268(%rbp,%rdx,4)
	addq	$2, %rdx
	cmpq	$64, %rdx
	jne	LBB0_6
## %bb.7:
	leaq	768(%r9), %r10
	xorl	%esi, %esi
	.p2align	4, 0x90
LBB0_8:                                 ## =>This Inner Loop Header: Depth=1
	movq	%rsi, %rax
	shrq	%rax
	andl	$2147483644, %eax               ## imm = 0x7FFFFFFC
	movl	(%r10,%rax), %r11d
	movl	%esi, %edx
	andb	$6, %dl
	movzbl	%dl, %edx
	xorl	%ebx, %ebx
	btl	%edx, %r11d
	setb	%bl
	movl	-272(%rbp,%rsi,4), %edx
	movl	-268(%rbp,%rsi,4), %r11d
	leal	(%rbx,%rdx,2), %edx
	movl	%edx, -272(%rbp,%rsi,4)
	movl	(%r10,%rax), %eax
	leal	1(%rsi), %edx
	andb	$7, %dl
	movzbl	%dl, %edx
	xorl	%ebx, %ebx
	btl	%edx, %eax
	setb	%bl
	leal	(%rbx,%r11,2), %eax
	movl	%eax, -268(%rbp,%rsi,4)
	addq	$2, %rsi
	cmpq	$64, %rsi
	jne	LBB0_8
## %bb.9:
	leaq	640(%r9), %r10
	xorl	%esi, %esi
	.p2align	4, 0x90
LBB0_10:                                ## =>This Inner Loop Header: Depth=1
	movq	%rsi, %rax
	shrq	%rax
	andl	$2147483644, %eax               ## imm = 0x7FFFFFFC
	movl	(%r10,%rax), %r11d
	movl	%esi, %edx
	andb	$6, %dl
	movzbl	%dl, %edx
	xorl	%ebx, %ebx
	btl	%edx, %r11d
	setb	%bl
	movl	-272(%rbp,%rsi,4), %edx
	movl	-268(%rbp,%rsi,4), %r11d
	leal	(%rbx,%rdx,2), %edx
	movl	%edx, -272(%rbp,%rsi,4)
	movl	(%r10,%rax), %eax
	leal	1(%rsi), %edx
	andb	$7, %dl
	movzbl	%dl, %edx
	xorl	%ebx, %ebx
	btl	%edx, %eax
	setb	%bl
	leal	(%rbx,%r11,2), %eax
	movl	%eax, -268(%rbp,%rsi,4)
	addq	$2, %rsi
	cmpq	$64, %rsi
	jne	LBB0_10
## %bb.11:
	leaq	512(%r9), %r10
	xorl	%esi, %esi
	.p2align	4, 0x90
LBB0_12:                                ## =>This Inner Loop Header: Depth=1
	movq	%rsi, %rax
	shrq	%rax
	andl	$2147483644, %eax               ## imm = 0x7FFFFFFC
	movl	(%r10,%rax), %r11d
	movl	%esi, %edx
	andb	$6, %dl
	movzbl	%dl, %edx
	xorl	%ebx, %ebx
	btl	%edx, %r11d
	setb	%bl
	movl	-272(%rbp,%rsi,4), %edx
	movl	-268(%rbp,%rsi,4), %r11d
	leal	(%rbx,%rdx,2), %edx
	movl	%edx, -272(%rbp,%rsi,4)
	movl	(%r10,%rax), %eax
	leal	1(%rsi), %edx
	andb	$7, %dl
	movzbl	%dl, %edx
	xorl	%ebx, %ebx
	btl	%edx, %eax
	setb	%bl
	leal	(%rbx,%r11,2), %eax
	movl	%eax, -268(%rbp,%rsi,4)
	addq	$2, %rsi
	cmpq	$64, %rsi
	jne	LBB0_12
## %bb.13:
	leaq	384(%r9), %r10
	xorl	%esi, %esi
	.p2align	4, 0x90
LBB0_14:                                ## =>This Inner Loop Header: Depth=1
	movq	%rsi, %rax
	shrq	%rax
	andl	$2147483644, %eax               ## imm = 0x7FFFFFFC
	movl	(%r10,%rax), %r11d
	movl	%esi, %edx
	andb	$6, %dl
	movzbl	%dl, %edx
	xorl	%ebx, %ebx
	btl	%edx, %r11d
	setb	%bl
	movl	-272(%rbp,%rsi,4), %edx
	movl	-268(%rbp,%rsi,4), %r11d
	leal	(%rbx,%rdx,2), %edx
	movl	%edx, -272(%rbp,%rsi,4)
	movl	(%r10,%rax), %eax
	leal	1(%rsi), %edx
	andb	$7, %dl
	movzbl	%dl, %edx
	xorl	%ebx, %ebx
	btl	%edx, %eax
	setb	%bl
	leal	(%rbx,%r11,2), %eax
	movl	%eax, -268(%rbp,%rsi,4)
	addq	$2, %rsi
	cmpq	$64, %rsi
	jne	LBB0_14
## %bb.15:
	leaq	256(%r9), %r10
	xorl	%esi, %esi
	.p2align	4, 0x90
LBB0_16:                                ## =>This Inner Loop Header: Depth=1
	movq	%rsi, %rax
	shrq	%rax
	andl	$2147483644, %eax               ## imm = 0x7FFFFFFC
	movl	(%r10,%rax), %r11d
	movl	%esi, %edx
	andb	$6, %dl
	movzbl	%dl, %edx
	xorl	%ebx, %ebx
	btl	%edx, %r11d
	setb	%bl
	movl	-272(%rbp,%rsi,4), %edx
	movl	-268(%rbp,%rsi,4), %r11d
	leal	(%rbx,%rdx,2), %edx
	movl	%edx, -272(%rbp,%rsi,4)
	movl	(%r10,%rax), %eax
	leal	1(%rsi), %edx
	andb	$7, %dl
	movzbl	%dl, %edx
	xorl	%ebx, %ebx
	btl	%edx, %eax
	setb	%bl
	leal	(%rbx,%r11,2), %eax
	movl	%eax, -268(%rbp,%rsi,4)
	addq	$2, %rsi
	cmpq	$64, %rsi
	jne	LBB0_16
## %bb.17:
	leaq	128(%r9), %r10
	xorl	%esi, %esi
	.p2align	4, 0x90
LBB0_18:                                ## =>This Inner Loop Header: Depth=1
	movq	%rsi, %rax
	shrq	%rax
	andl	$2147483644, %eax               ## imm = 0x7FFFFFFC
	movl	(%r10,%rax), %r11d
	movl	%esi, %edx
	andb	$6, %dl
	movzbl	%dl, %edx
	xorl	%ebx, %ebx
	btl	%edx, %r11d
	setb	%bl
	movl	-272(%rbp,%rsi,4), %edx
	movl	-268(%rbp,%rsi,4), %r11d
	leal	(%rbx,%rdx,2), %edx
	movl	%edx, -272(%rbp,%rsi,4)
	movl	(%r10,%rax), %eax
	leal	1(%rsi), %edx
	andb	$7, %dl
	movzbl	%dl, %edx
	xorl	%ebx, %ebx
	btl	%edx, %eax
	setb	%bl
	leal	(%rbx,%r11,2), %eax
	movl	%eax, -268(%rbp,%rsi,4)
	addq	$2, %rsi
	cmpq	$64, %rsi
	jne	LBB0_18
## %bb.19:
	xorl	%edx, %edx
	.p2align	4, 0x90
LBB0_20:                                ## =>This Inner Loop Header: Depth=1
	movq	%rdx, %rax
	shrq	%rax
	andl	$2147483644, %eax               ## imm = 0x7FFFFFFC
	movl	(%r9,%rax), %r10d
	movl	%edx, %ebx
	andb	$6, %bl
	movzbl	%bl, %ebx
	xorl	%esi, %esi
	btl	%ebx, %r10d
	setb	%sil
	movl	-272(%rbp,%rdx,4), %ebx
	movl	-268(%rbp,%rdx,4), %r10d
	leal	(%rsi,%rbx,2), %esi
	movl	%esi, -272(%rbp,%rdx,4)
	movl	(%r9,%rax), %eax
	leal	1(%rdx), %esi
	andb	$7, %sil
	movzbl	%sil, %esi
	xorl	%ebx, %ebx
	btl	%esi, %eax
	setb	%bl
	leal	(%rbx,%r10,2), %eax
	movl	%eax, -268(%rbp,%rdx,4)
	addq	$2, %rdx
	cmpq	$64, %rdx
	jne	LBB0_20
LBB0_21:
	leal	(%rcx,%r8,4), %eax
	shll	$6, %eax
	cltq
	leaq	(%rdi,%rax,4), %rcx
	addq	$4, %rcx
	xorl	%edx, %edx
	xorl	%eax, %eax
	jmp	LBB0_22
	.p2align	4, 0x90
LBB0_26:                                ##   in Loop: Header=BB0_22 Depth=1
	addq	$2, %rdx
	cmpq	$64, %rdx
	je	LBB0_27
LBB0_22:                                ## =>This Inner Loop Header: Depth=1
	movl	-272(%rbp,%rdx,4), %esi
	cmpl	-4(%rcx,%rdx,4), %esi
	je	LBB0_24
## %bb.23:                              ##   in Loop: Header=BB0_22 Depth=1
	movl	%esi, -4(%rcx,%rdx,4)
	movl	$1, %eax
LBB0_24:                                ##   in Loop: Header=BB0_22 Depth=1
	movl	-268(%rbp,%rdx,4), %esi
	cmpl	(%rcx,%rdx,4), %esi
	je	LBB0_26
## %bb.25:                              ##   in Loop: Header=BB0_22 Depth=1
	movl	%esi, (%rcx,%rdx,4)
	movl	$1, %eax
	jmp	LBB0_26
LBB0_29:
	movl	$1, %edi
	callq	_WARN_ON
	xorl	%eax, %eax
LBB0_27:
	movq	___stack_chk_guard@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	cmpq	-16(%rbp), %rcx
	jne	LBB0_30
## %bb.28:
	addq	$312, %rsp                      ## imm = 0x138
	popq	%rbx
	popq	%rbp
	retq
LBB0_30:
	callq	___stack_chk_fail
	.cfi_endproc
                                        ## -- End function
	.no_dead_strip	_picolcd_fb_update_tile
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function picolcd_fb_update_tile
_picolcd_fb_update_tile:                ; @picolcd_fb_update_tile
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #304
	.cfi_def_cfa_offset 304
	stp	x28, x27, [sp, #272]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #288]            ; 16-byte Folded Spill
	add	x29, sp, #288
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w27, -24
	.cfi_offset w28, -32
Lloh0:
	adrp	x8, ___stack_chk_guard@GOTPAGE
Lloh1:
	ldr	x8, [x8, ___stack_chk_guard@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	stur	x8, [x29, #-24]
	cmp	w2, #1
	b.eq	LBB0_3
; %bb.1:
	cmp	w2, #8
	b.ne	LBB0_23
; %bb.2:
	lsl	w8, w4, #8
	ldp	q0, q1, [sp]
	add	w8, w8, w3, lsl #3
	lsl	w8, w8, #3
	add	w9, w8, #1792
	add	x9, x1, w9, sxtw #2
	ldp	q2, q3, [x9]
	ushr.4s	v2, v2, #7
	sli.4s	v2, v0, #1
	ushr.4s	v0, v3, #7
	sli.4s	v0, v1, #1
	stp	q2, q0, [sp]
	ldp	q0, q1, [x9, #32]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #32]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #32]
	ldp	q0, q1, [x9, #64]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #64]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #64]
	ldp	q0, q1, [x9, #96]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #96]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #96]
	ldp	q0, q1, [x9, #128]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #128]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #128]
	ldp	q0, q1, [x9, #160]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #160]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #160]
	ldp	q0, q1, [x9, #192]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #192]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #192]
	ldp	q0, q1, [x9, #224]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #224]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #224]
	add	w9, w8, #1536
	add	x9, x1, w9, sxtw #2
	ldp	q0, q1, [x9]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp]
	ldp	q0, q1, [x9, #32]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #32]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #32]
	ldp	q0, q1, [x9, #64]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #64]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #64]
	ldp	q0, q1, [x9, #96]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #96]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #96]
	ldp	q0, q1, [x9, #128]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #128]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #128]
	ldp	q0, q1, [x9, #160]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #160]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #160]
	ldp	q0, q1, [x9, #192]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #192]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #192]
	ldp	q0, q1, [x9, #224]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #224]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #224]
	add	w9, w8, #1280
	add	x9, x1, w9, sxtw #2
	ldp	q0, q1, [x9]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp]
	ldp	q0, q1, [x9, #32]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #32]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #32]
	ldp	q0, q1, [x9, #64]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #64]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #64]
	ldp	q0, q1, [x9, #96]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #96]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #96]
	ldp	q0, q1, [x9, #128]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #128]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #128]
	ldp	q0, q1, [x9, #160]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #160]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #160]
	ldp	q0, q1, [x9, #192]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #192]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #192]
	ldp	q0, q1, [x9, #224]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #224]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #224]
	add	w9, w8, #1024
	add	x9, x1, w9, sxtw #2
	ldp	q0, q1, [x9]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp]
	ldp	q0, q1, [x9, #32]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #32]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #32]
	ldp	q0, q1, [x9, #64]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #64]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #64]
	ldp	q0, q1, [x9, #96]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #96]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #96]
	ldp	q0, q1, [x9, #128]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #128]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #128]
	ldp	q0, q1, [x9, #160]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #160]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #160]
	ldp	q0, q1, [x9, #192]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #192]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #192]
	ldp	q0, q1, [x9, #224]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #224]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #224]
	add	w9, w8, #768
	add	x9, x1, w9, sxtw #2
	ldp	q0, q1, [x9]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp]
	ldp	q0, q1, [x9, #32]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #32]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #32]
	ldp	q0, q1, [x9, #64]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #64]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #64]
	ldp	q0, q1, [x9, #96]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #96]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #96]
	ldp	q0, q1, [x9, #128]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #128]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #128]
	ldp	q0, q1, [x9, #160]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #160]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #160]
	ldp	q0, q1, [x9, #192]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #192]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #192]
	ldp	q0, q1, [x9, #224]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #224]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #224]
	add	w9, w8, #512
	add	x9, x1, w9, sxtw #2
	ldp	q0, q1, [x9]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp]
	ldp	q0, q1, [x9, #32]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #32]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #32]
	ldp	q0, q1, [x9, #64]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #64]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #64]
	ldp	q0, q1, [x9, #96]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #96]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #96]
	ldp	q0, q1, [x9, #128]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #128]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #128]
	ldp	q0, q1, [x9, #160]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #160]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #160]
	ldp	q0, q1, [x9, #192]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #192]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #192]
	ldp	q0, q1, [x9, #224]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #224]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #224]
	add	w9, w8, #256
	add	x9, x1, w9, sxtw #2
	ldp	q0, q1, [x9]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp]
	ldp	q0, q1, [x9, #32]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #32]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #32]
	ldp	q0, q1, [x9, #64]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #64]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #64]
	ldp	q0, q1, [x9, #96]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #96]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #96]
	ldp	q0, q1, [x9, #128]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #128]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #128]
	ldp	q0, q1, [x9, #160]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #160]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #160]
	ldp	q0, q1, [x9, #192]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #192]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #192]
	ldp	q0, q1, [x9, #224]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #224]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #224]
	add	x8, x1, w8, sxtw #2
	ldp	q0, q1, [x8]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp]
	ldp	q0, q1, [x8, #32]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #32]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #32]
	ldp	q0, q1, [x8, #64]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #64]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #64]
	ldp	q0, q1, [x8, #96]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #96]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #96]
	ldp	q0, q1, [x8, #128]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #128]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #128]
	ldp	q0, q1, [x8, #160]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #160]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #160]
	ldp	q0, q1, [x8, #192]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #192]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #192]
	ldp	q0, q1, [x8, #224]
	ushr.4s	v0, v0, #7
	ldp	q2, q3, [sp, #224]
	sli.4s	v0, v2, #1
	ushr.4s	v1, v1, #7
	sli.4s	v1, v3, #1
	stp	q0, q1, [sp, #224]
	b	LBB0_19
LBB0_3:
	mov	x9, #0
	lsl	w8, w4, #8
	add	x8, x1, w8, sxtw #2
	lsl	w10, w3, #3
	add	x8, x8, w10, sxtw #2
	add	x10, x8, #896
	mov	x11, sp
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
	lsl	x12, x9, #2
	ldr	w13, [x11, x12]
	ubfx	x14, x9, #3, #29
	ldr	w14, [x10, x14, lsl #2]
	and	w15, w9, #0x7
	lsr	w14, w14, w15
	bfi	w14, w13, #1, #31
	str	w14, [x11, x12]
	add	x9, x9, #1
	cmp	x9, #64
	b.ne	LBB0_4
; %bb.5:
	mov	x9, #0
	add	x10, x8, #768
	mov	x11, sp
LBB0_6:                                 ; =>This Inner Loop Header: Depth=1
	lsl	x12, x9, #2
	ldr	w13, [x11, x12]
	ubfx	x14, x9, #3, #29
	ldr	w14, [x10, x14, lsl #2]
	and	w15, w9, #0x7
	lsr	w14, w14, w15
	bfi	w14, w13, #1, #31
	str	w14, [x11, x12]
	add	x9, x9, #1
	cmp	x9, #64
	b.ne	LBB0_6
; %bb.7:
	mov	x9, #0
	add	x10, x8, #640
	mov	x11, sp
LBB0_8:                                 ; =>This Inner Loop Header: Depth=1
	lsl	x12, x9, #2
	ldr	w13, [x11, x12]
	ubfx	x14, x9, #3, #29
	ldr	w14, [x10, x14, lsl #2]
	and	w15, w9, #0x7
	lsr	w14, w14, w15
	bfi	w14, w13, #1, #31
	str	w14, [x11, x12]
	add	x9, x9, #1
	cmp	x9, #64
	b.ne	LBB0_8
; %bb.9:
	mov	x9, #0
	add	x10, x8, #512
	mov	x11, sp
LBB0_10:                                ; =>This Inner Loop Header: Depth=1
	lsl	x12, x9, #2
	ldr	w13, [x11, x12]
	ubfx	x14, x9, #3, #29
	ldr	w14, [x10, x14, lsl #2]
	and	w15, w9, #0x7
	lsr	w14, w14, w15
	bfi	w14, w13, #1, #31
	str	w14, [x11, x12]
	add	x9, x9, #1
	cmp	x9, #64
	b.ne	LBB0_10
; %bb.11:
	mov	x9, #0
	add	x10, x8, #384
	mov	x11, sp
LBB0_12:                                ; =>This Inner Loop Header: Depth=1
	lsl	x12, x9, #2
	ldr	w13, [x11, x12]
	ubfx	x14, x9, #3, #29
	ldr	w14, [x10, x14, lsl #2]
	and	w15, w9, #0x7
	lsr	w14, w14, w15
	bfi	w14, w13, #1, #31
	str	w14, [x11, x12]
	add	x9, x9, #1
	cmp	x9, #64
	b.ne	LBB0_12
; %bb.13:
	mov	x9, #0
	add	x10, x8, #256
	mov	x11, sp
LBB0_14:                                ; =>This Inner Loop Header: Depth=1
	lsl	x12, x9, #2
	ldr	w13, [x11, x12]
	ubfx	x14, x9, #3, #29
	ldr	w14, [x10, x14, lsl #2]
	and	w15, w9, #0x7
	lsr	w14, w14, w15
	bfi	w14, w13, #1, #31
	str	w14, [x11, x12]
	add	x9, x9, #1
	cmp	x9, #64
	b.ne	LBB0_14
; %bb.15:
	mov	x9, #0
	add	x10, x8, #128
	mov	x11, sp
LBB0_16:                                ; =>This Inner Loop Header: Depth=1
	lsl	x12, x9, #2
	ldr	w13, [x11, x12]
	ubfx	x14, x9, #3, #29
	ldr	w14, [x10, x14, lsl #2]
	and	w15, w9, #0x7
	lsr	w14, w14, w15
	bfi	w14, w13, #1, #31
	str	w14, [x11, x12]
	add	x9, x9, #1
	cmp	x9, #64
	b.ne	LBB0_16
; %bb.17:
	mov	x9, #0
	mov	x10, sp
LBB0_18:                                ; =>This Inner Loop Header: Depth=1
	lsl	x11, x9, #2
	ldr	w12, [x10, x11]
	ubfx	x13, x9, #3, #29
	ldr	w13, [x8, x13, lsl #2]
	and	w14, w9, #0x7
	lsr	w13, w13, w14
	bfi	w13, w12, #1, #31
	str	w13, [x10, x11]
	add	x9, x9, #1
	cmp	x9, #64
	b.ne	LBB0_18
LBB0_19:
	mov	x9, #0
	mov	w8, #0
	add	w10, w3, w4, lsl #2
	lsl	w10, w10, #6
	add	x10, x0, w10, sxtw #2
	mov	x11, sp
	b	LBB0_21
LBB0_20:                                ;   in Loop: Header=BB0_21 Depth=1
	add	x9, x9, #4
	cmp	x9, #256
	b.eq	LBB0_24
LBB0_21:                                ; =>This Inner Loop Header: Depth=1
	ldr	w12, [x11, x9]
	ldr	w13, [x10, x9]
	cmp	w12, w13
	b.eq	LBB0_20
; %bb.22:                               ;   in Loop: Header=BB0_21 Depth=1
	str	w12, [x10, x9]
	mov	w8, #1
	b	LBB0_20
LBB0_23:
	mov	w0, #1
	bl	_WARN_ON
	mov	w8, #0
LBB0_24:
	ldur	x9, [x29, #-24]
Lloh3:
	adrp	x10, ___stack_chk_guard@GOTPAGE
Lloh4:
	ldr	x10, [x10, ___stack_chk_guard@GOTPAGEOFF]
Lloh5:
	ldr	x10, [x10]
	cmp	x10, x9
	b.ne	LBB0_26
; %bb.25:
	mov	x0, x8
	ldp	x29, x30, [sp, #288]            ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #272]            ; 16-byte Folded Reload
	add	sp, sp, #304
	ret
LBB0_26:
	bl	___stack_chk_fail
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.no_dead_strip	_picolcd_fb_update_tile
.subsections_via_symbols
