	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vce_v4_0_start
_vce_v4_0_start:                        ## @vce_v4_0_start
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	(%rdi), %r12
	movq	_VCE@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	movq	_mmVCE_RB_RPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %ebx
	movl	8(%r12), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movl	(%r15), %edi
	movq	_mmVCE_RB_WPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %ebx
	movl	8(%r12), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movl	(%r15), %edi
	movq	_mmVCE_RB_BASE_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r12), %esi
	movl	%eax, %edi
	callq	_WREG32
	movl	(%r15), %edi
	movq	_mmVCE_RB_BASE_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %ebx
	movl	(%r12), %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movl	(%r15), %edi
	movq	_mmVCE_RB_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	4(%r12), %ecx
	leal	3(%rcx), %esi
	testl	%ecx, %ecx
	cmovnsl	%ecx, %esi
	sarl	$2, %esi
	movl	%eax, %edi
	callq	_WREG32
	movq	(%r14), %r12
	movl	(%r15), %edi
	movq	_mmVCE_RB_RPTR2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %ebx
	movl	20(%r12), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movl	(%r15), %edi
	movq	_mmVCE_RB_WPTR2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %ebx
	movl	20(%r12), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movl	(%r15), %edi
	movq	_mmVCE_RB_BASE_LO2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	12(%r12), %esi
	movl	%eax, %edi
	callq	_WREG32
	movl	(%r15), %edi
	movq	_mmVCE_RB_BASE_HI2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %ebx
	movl	12(%r12), %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movl	(%r15), %edi
	movq	_mmVCE_RB_SIZE2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	16(%r12), %ecx
	leal	3(%rcx), %esi
	testl	%ecx, %ecx
	cmovnsl	%ecx, %esi
	sarl	$2, %esi
	movl	%eax, %edi
	callq	_WREG32
	movq	(%r14), %r12
	movl	(%r15), %edi
	movq	_mmVCE_RB_RPTR3@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %ebx
	movl	32(%r12), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movl	(%r15), %edi
	movq	_mmVCE_RB_WPTR3@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %ebx
	movl	32(%r12), %edi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movl	(%r15), %edi
	movq	_mmVCE_RB_BASE_LO3@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	24(%r12), %esi
	movl	%eax, %edi
	callq	_WREG32
	movl	(%r15), %edi
	movq	_mmVCE_RB_BASE_HI3@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %ebx
	movl	24(%r12), %edi
	callq	_upper_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movl	(%r15), %edi
	movq	_mmVCE_RB_SIZE3@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	28(%r12), %ecx
	leal	3(%rcx), %esi
	testl	%ecx, %ecx
	cmovnsl	%ecx, %esi
	sarl	$2, %esi
	movl	%eax, %edi
	callq	_WREG32
	movq	%r14, %rdi
	callq	_vce_v4_0_mc_resume
	movl	(%r15), %edi
	movq	_mmVCE_STATUS@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_VCE_STATUS__JOB_BUSY_MASK@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movl	%esi, %edx
	notl	%edx
	movl	%eax, %edi
	callq	_WREG32_P
	movl	(%r15), %edi
	movq	_mmVCE_VCPU_CNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	%eax, %edi
	movl	$1, %esi
	movl	$-2097154, %edx                 ## imm = 0xFFDFFFFE
	callq	_WREG32_P
	movl	(%r15), %edi
	movq	_mmVCE_SOFT_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movq	_VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	movl	$100, %edi
	callq	_mdelay
	movq	%r14, %rdi
	callq	_vce_v4_0_firmware_loaded
	movl	%eax, %ebx
	movl	(%r15), %edi
	movl	(%r12), %edx
	xorl	%esi, %esi
	callq	_SOC15_REG_OFFSET
	movl	(%r13), %edx
	notl	%edx
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_WREG32_P
	testl	%ebx, %ebx
	je	LBB0_2
## %bb.1:
	leaq	L_.str(%rip), %rdi
	callq	_DRM_ERROR
LBB0_2:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_VCE,4,2                        ## @VCE
	.comm	_mmVCE_RB_RPTR,4,2              ## @mmVCE_RB_RPTR
	.comm	_mmVCE_RB_WPTR,4,2              ## @mmVCE_RB_WPTR
	.comm	_mmVCE_RB_BASE_LO,4,2           ## @mmVCE_RB_BASE_LO
	.comm	_mmVCE_RB_BASE_HI,4,2           ## @mmVCE_RB_BASE_HI
	.comm	_mmVCE_RB_SIZE,4,2              ## @mmVCE_RB_SIZE
	.comm	_mmVCE_RB_RPTR2,4,2             ## @mmVCE_RB_RPTR2
	.comm	_mmVCE_RB_WPTR2,4,2             ## @mmVCE_RB_WPTR2
	.comm	_mmVCE_RB_BASE_LO2,4,2          ## @mmVCE_RB_BASE_LO2
	.comm	_mmVCE_RB_BASE_HI2,4,2          ## @mmVCE_RB_BASE_HI2
	.comm	_mmVCE_RB_SIZE2,4,2             ## @mmVCE_RB_SIZE2
	.comm	_mmVCE_RB_RPTR3,4,2             ## @mmVCE_RB_RPTR3
	.comm	_mmVCE_RB_WPTR3,4,2             ## @mmVCE_RB_WPTR3
	.comm	_mmVCE_RB_BASE_LO3,4,2          ## @mmVCE_RB_BASE_LO3
	.comm	_mmVCE_RB_BASE_HI3,4,2          ## @mmVCE_RB_BASE_HI3
	.comm	_mmVCE_RB_SIZE3,4,2             ## @mmVCE_RB_SIZE3
	.comm	_mmVCE_STATUS,4,2               ## @mmVCE_STATUS
	.comm	_VCE_STATUS__JOB_BUSY_MASK,4,2  ## @VCE_STATUS__JOB_BUSY_MASK
	.comm	_mmVCE_VCPU_CNTL,4,2            ## @mmVCE_VCPU_CNTL
	.comm	_mmVCE_SOFT_RESET,4,2           ## @mmVCE_SOFT_RESET
	.comm	_VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,4,2 ## @VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"VCE not responding, giving up!!!\n"

	.no_dead_strip	_vce_v4_0_start
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vce_v4_0_start
_vce_v4_0_start:                        ; @vce_v4_0_start
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x22, [x0]
Lloh0:
	adrp	x21, _VCE@GOTPAGE
Lloh1:
	ldr	x21, [x21, _VCE@GOTPAGEOFF]
	ldr	w0, [x21]
Lloh2:
	adrp	x8, _mmVCE_RB_RPTR@GOTPAGE
Lloh3:
	ldr	x8, [x8, _mmVCE_RB_RPTR@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x20, x0
	ldr	w0, [x22, #8]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
	ldr	w0, [x21]
Lloh5:
	adrp	x8, _mmVCE_RB_WPTR@GOTPAGE
Lloh6:
	ldr	x8, [x8, _mmVCE_RB_WPTR@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x20, x0
	ldr	w0, [x22, #8]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
	ldr	w0, [x21]
Lloh8:
	adrp	x8, _mmVCE_RB_BASE_LO@GOTPAGE
Lloh9:
	ldr	x8, [x8, _mmVCE_RB_BASE_LO@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w1, [x22]
	bl	_WREG32
	ldr	w0, [x21]
Lloh11:
	adrp	x8, _mmVCE_RB_BASE_HI@GOTPAGE
Lloh12:
	ldr	x8, [x8, _mmVCE_RB_BASE_HI@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x20, x0
	ldr	w0, [x22]
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
	ldr	w0, [x21]
Lloh14:
	adrp	x8, _mmVCE_RB_SIZE@GOTPAGE
Lloh15:
	ldr	x8, [x8, _mmVCE_RB_SIZE@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x22, #4]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w1, w8, #2
	bl	_WREG32
	ldr	x22, [x19]
	ldr	w0, [x21]
Lloh17:
	adrp	x8, _mmVCE_RB_RPTR2@GOTPAGE
Lloh18:
	ldr	x8, [x8, _mmVCE_RB_RPTR2@GOTPAGEOFF]
Lloh19:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x20, x0
	ldr	w0, [x22, #20]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
	ldr	w0, [x21]
Lloh20:
	adrp	x8, _mmVCE_RB_WPTR2@GOTPAGE
Lloh21:
	ldr	x8, [x8, _mmVCE_RB_WPTR2@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x20, x0
	ldr	w0, [x22, #20]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
	ldr	w0, [x21]
Lloh23:
	adrp	x8, _mmVCE_RB_BASE_LO2@GOTPAGE
Lloh24:
	ldr	x8, [x8, _mmVCE_RB_BASE_LO2@GOTPAGEOFF]
Lloh25:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w1, [x22, #12]
	bl	_WREG32
	ldr	w0, [x21]
Lloh26:
	adrp	x8, _mmVCE_RB_BASE_HI2@GOTPAGE
Lloh27:
	ldr	x8, [x8, _mmVCE_RB_BASE_HI2@GOTPAGEOFF]
Lloh28:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x20, x0
	ldr	w0, [x22, #12]
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
	ldr	w0, [x21]
Lloh29:
	adrp	x8, _mmVCE_RB_SIZE2@GOTPAGE
Lloh30:
	ldr	x8, [x8, _mmVCE_RB_SIZE2@GOTPAGEOFF]
Lloh31:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x22, #16]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w1, w8, #2
	bl	_WREG32
	ldr	x22, [x19]
	ldr	w0, [x21]
Lloh32:
	adrp	x8, _mmVCE_RB_RPTR3@GOTPAGE
Lloh33:
	ldr	x8, [x8, _mmVCE_RB_RPTR3@GOTPAGEOFF]
Lloh34:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x20, x0
	ldr	w0, [x22, #32]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
	ldr	w0, [x21]
Lloh35:
	adrp	x8, _mmVCE_RB_WPTR3@GOTPAGE
Lloh36:
	ldr	x8, [x8, _mmVCE_RB_WPTR3@GOTPAGEOFF]
Lloh37:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x20, x0
	ldr	w0, [x22, #32]
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
	ldr	w0, [x21]
Lloh38:
	adrp	x8, _mmVCE_RB_BASE_LO3@GOTPAGE
Lloh39:
	ldr	x8, [x8, _mmVCE_RB_BASE_LO3@GOTPAGEOFF]
Lloh40:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w1, [x22, #24]
	bl	_WREG32
	ldr	w0, [x21]
Lloh41:
	adrp	x8, _mmVCE_RB_BASE_HI3@GOTPAGE
Lloh42:
	ldr	x8, [x8, _mmVCE_RB_BASE_HI3@GOTPAGEOFF]
Lloh43:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	x20, x0
	ldr	w0, [x22, #24]
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
	ldr	w0, [x21]
Lloh44:
	adrp	x8, _mmVCE_RB_SIZE3@GOTPAGE
Lloh45:
	ldr	x8, [x8, _mmVCE_RB_SIZE3@GOTPAGEOFF]
Lloh46:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x22, #28]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w1, w8, #2
	bl	_WREG32
	mov	x0, x19
	bl	_vce_v4_0_mc_resume
	ldr	w0, [x21]
Lloh47:
	adrp	x20, _mmVCE_STATUS@GOTPAGE
Lloh48:
	ldr	x20, [x20, _mmVCE_STATUS@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh49:
	adrp	x22, _VCE_STATUS__JOB_BUSY_MASK@GOTPAGE
Lloh50:
	ldr	x22, [x22, _VCE_STATUS__JOB_BUSY_MASK@GOTPAGEOFF]
	ldr	w1, [x22]
	mvn	w2, w1
	bl	_WREG32_P
	ldr	w0, [x21]
Lloh51:
	adrp	x8, _mmVCE_VCPU_CNTL@GOTPAGE
Lloh52:
	ldr	x8, [x8, _mmVCE_VCPU_CNTL@GOTPAGEOFF]
Lloh53:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	mov	w1, #1
	mov	w2, #65534
	movk	w2, #65503, lsl #16
	bl	_WREG32_P
	ldr	w0, [x21]
Lloh54:
	adrp	x8, _mmVCE_SOFT_RESET@GOTPAGE
Lloh55:
	ldr	x8, [x8, _mmVCE_SOFT_RESET@GOTPAGEOFF]
Lloh56:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
Lloh57:
	adrp	x8, _VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK@GOTPAGE
Lloh58:
	ldr	x8, [x8, _VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK@GOTPAGEOFF]
Lloh59:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	mov	w0, #100
	bl	_mdelay
	mov	x0, x19
	bl	_vce_v4_0_firmware_loaded
	mov	x19, x0
	ldr	w0, [x21]
	ldr	w2, [x20]
	mov	w1, #0
	bl	_SOC15_REG_OFFSET
	ldr	w8, [x22]
	mvn	w2, w8
	mov	w1, #0
	bl	_WREG32_P
	cbz	w19, LBB0_2
; %bb.1:
Lloh60:
	adrp	x0, l_.str@PAGE
Lloh61:
	add	x0, x0, l_.str@PAGEOFF
	bl	_DRM_ERROR
LBB0_2:
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh60, Lloh61
	.cfi_endproc
                                        ; -- End function
	.comm	_VCE,4,2                        ; @VCE
	.comm	_mmVCE_RB_RPTR,4,2              ; @mmVCE_RB_RPTR
	.comm	_mmVCE_RB_WPTR,4,2              ; @mmVCE_RB_WPTR
	.comm	_mmVCE_RB_BASE_LO,4,2           ; @mmVCE_RB_BASE_LO
	.comm	_mmVCE_RB_BASE_HI,4,2           ; @mmVCE_RB_BASE_HI
	.comm	_mmVCE_RB_SIZE,4,2              ; @mmVCE_RB_SIZE
	.comm	_mmVCE_RB_RPTR2,4,2             ; @mmVCE_RB_RPTR2
	.comm	_mmVCE_RB_WPTR2,4,2             ; @mmVCE_RB_WPTR2
	.comm	_mmVCE_RB_BASE_LO2,4,2          ; @mmVCE_RB_BASE_LO2
	.comm	_mmVCE_RB_BASE_HI2,4,2          ; @mmVCE_RB_BASE_HI2
	.comm	_mmVCE_RB_SIZE2,4,2             ; @mmVCE_RB_SIZE2
	.comm	_mmVCE_RB_RPTR3,4,2             ; @mmVCE_RB_RPTR3
	.comm	_mmVCE_RB_WPTR3,4,2             ; @mmVCE_RB_WPTR3
	.comm	_mmVCE_RB_BASE_LO3,4,2          ; @mmVCE_RB_BASE_LO3
	.comm	_mmVCE_RB_BASE_HI3,4,2          ; @mmVCE_RB_BASE_HI3
	.comm	_mmVCE_RB_SIZE3,4,2             ; @mmVCE_RB_SIZE3
	.comm	_mmVCE_STATUS,4,2               ; @mmVCE_STATUS
	.comm	_VCE_STATUS__JOB_BUSY_MASK,4,2  ; @VCE_STATUS__JOB_BUSY_MASK
	.comm	_mmVCE_VCPU_CNTL,4,2            ; @mmVCE_VCPU_CNTL
	.comm	_mmVCE_SOFT_RESET,4,2           ; @mmVCE_SOFT_RESET
	.comm	_VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,4,2 ; @VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"VCE not responding, giving up!!!\n"

	.no_dead_strip	_vce_v4_0_start
.subsections_via_symbols
