	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function gfx_v7_0_set_priv_reg_fault_state
_gfx_v7_0_set_priv_reg_fault_state:     ## @gfx_v7_0_set_priv_reg_fault_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	cmpl	$128, %ecx
	je	LBB0_3
## %bb.1:
	cmpl	$129, %ecx
	jne	LBB0_5
## %bb.2:
	movq	_mmCP_INT_CNTL_RING0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movq	_CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	jmp	LBB0_4
LBB0_3:
	movq	_mmCP_INT_CNTL_RING0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RREG32
	movl	%eax, %esi
	movq	_CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
LBB0_4:
	movq	_mmCP_INT_CNTL_RING0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_WREG32
LBB0_5:
	xorl	%eax, %eax
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_mmCP_INT_CNTL_RING0,4,2        ## @mmCP_INT_CNTL_RING0
	.comm	_CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK,4,2 ## @CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK
	.no_dead_strip	_gfx_v7_0_set_priv_reg_fault_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function gfx_v7_0_set_priv_reg_fault_state
_gfx_v7_0_set_priv_reg_fault_state:     ; @gfx_v7_0_set_priv_reg_fault_state
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
Lloh0:
	adrp	x19, _mmCP_INT_CNTL_RING0@GOTPAGE
Lloh1:
	ldr	x19, [x19, _mmCP_INT_CNTL_RING0@GOTPAGEOFF]
	cmp	w3, #128
	b.eq	LBB0_3
; %bb.1:
	cmp	w3, #129
	b.ne	LBB0_5
; %bb.2:
	ldr	w0, [x19]
	bl	_RREG32
Lloh2:
	adrp	x8, _CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	bic	w1, w0, w8
	b	LBB0_4
LBB0_3:
	ldr	w0, [x19]
	bl	_RREG32
Lloh5:
	adrp	x8, _CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	orr	w1, w8, w0
LBB0_4:
	ldr	w0, [x19]
	bl	_WREG32
LBB0_5:
	mov	w0, #0
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.cfi_endproc
                                        ; -- End function
	.comm	_mmCP_INT_CNTL_RING0,4,2        ; @mmCP_INT_CNTL_RING0
	.comm	_CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK,4,2 ; @CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK
	.no_dead_strip	_gfx_v7_0_set_priv_reg_fault_state
.subsections_via_symbols
