	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_sync_resv               ## -- Begin function amdgpu_sync_resv
	.p2align	4, 0x90
_amdgpu_sync_resv:                      ## @amdgpu_sync_resv
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%r8d, -52(%rbp)                 ## 4-byte Spill
	movq	%rcx, -48(%rbp)                 ## 8-byte Spill
	testq	%rdx, %rdx
	je	LBB0_1
## %bb.2:
	movq	%rdx, %rbx
	movq	%rsi, %r14
	movq	%rdi, %r15
	movq	%rdx, %rdi
	callq	_dma_resv_get_excl
	movq	%r15, %rdi
	movq	%r14, %rsi
	movq	%rax, %rdx
	xorl	%ecx, %ecx
	callq	_amdgpu_sync_fence
	movl	%eax, %r12d
	movq	%rbx, %rdi
	callq	_dma_resv_get_list
	testq	%rax, %rax
	je	LBB0_18
## %bb.3:
	testl	%r12d, %r12d
	jne	LBB0_18
## %bb.4:
	cmpl	$0, (%rax)
	je	LBB0_17
## %bb.5:
	movq	%r15, -64(%rbp)                 ## 8-byte Spill
	movq	%r14, -72(%rbp)                 ## 8-byte Spill
	xorl	%r15d, %r15d
	movq	%rax, -80(%rbp)                 ## 8-byte Spill
	jmp	LBB0_6
	.p2align	4, 0x90
LBB0_14:                                ##   in Loop: Header=BB0_6 Depth=1
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	movq	-72(%rbp), %rsi                 ## 8-byte Reload
	movq	%r12, %rdx
	xorl	%ecx, %ecx
	callq	_amdgpu_sync_fence
	testl	%eax, %eax
	jne	LBB0_15
LBB0_16:                                ##   in Loop: Header=BB0_6 Depth=1
	incq	%r15
	movq	-80(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %ecx
	cmpq	%rcx, %r15
	movq	%r14, %rbx
	jae	LBB0_17
LBB0_6:                                 ## =>This Inner Loop Header: Depth=1
	movq	8(%rax), %rax
	movl	(%rax,%r15,4), %r12d
	movq	%rbx, %r14
	movq	%rbx, %rdi
	callq	_dma_resv_held
	movl	%r12d, %edi
	movl	%eax, %esi
	callq	_rcu_dereference_protected
	movq	%rax, %r12
	movq	%rax, %rdi
	callq	_amdgpu_sync_get_owner
	movq	%rax, %r13
	movq	_AMDGPU_FENCE_OWNER_KFD@GOTPCREL(%rip), %rax
	cmpq	(%rax), %r13
	jne	LBB0_8
## %bb.7:                               ##   in Loop: Header=BB0_6 Depth=1
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movq	_AMDGPU_FENCE_OWNER_UNDEFINED@GOTPCREL(%rip), %rcx
	cmpq	%rax, (%rcx)
	jne	LBB0_16
LBB0_8:                                 ##   in Loop: Header=BB0_6 Depth=1
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	movq	%r12, %rsi
	callq	_amdgpu_sync_same_dev
	testq	%rax, %rax
	je	LBB0_14
## %bb.9:                               ##   in Loop: Header=BB0_6 Depth=1
	movq	_AMDGPU_FENCE_OWNER_UNDEFINED@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	cmpq	-48(%rbp), %rax                 ## 8-byte Folded Reload
	je	LBB0_12
## %bb.10:                              ##   in Loop: Header=BB0_6 Depth=1
	cmpq	%rax, %r13
	je	LBB0_12
## %bb.11:                              ##   in Loop: Header=BB0_6 Depth=1
	movq	_AMDGPU_FENCE_OWNER_VM@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	cmpq	-48(%rbp), %rcx                 ## 8-byte Folded Reload
	setne	%dl
	cmpq	%rcx, %r13
	sete	%cl
	cmpb	%cl, %dl
	je	LBB0_16
LBB0_12:                                ##   in Loop: Header=BB0_6 Depth=1
	cmpl	$0, -52(%rbp)                   ## 4-byte Folded Reload
	setne	%cl
	movq	-48(%rbp), %rsi                 ## 8-byte Reload
	cmpq	%rsi, %r13
	sete	%dl
	cmpq	%rsi, %rax
	je	LBB0_14
## %bb.13:                              ##   in Loop: Header=BB0_6 Depth=1
	orb	%dl, %cl
	jne	LBB0_16
	jmp	LBB0_14
LBB0_1:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r12d, %r12d
	subl	(%rax), %r12d
	jmp	LBB0_18
LBB0_17:
	xorl	%r12d, %r12d
LBB0_18:
	movl	%r12d, %eax
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_15:
	movl	%eax, %r12d
	jmp	LBB0_18
	.cfi_endproc
                                        ## -- End function
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_AMDGPU_FENCE_OWNER_KFD,8,3     ## @AMDGPU_FENCE_OWNER_KFD
	.comm	_AMDGPU_FENCE_OWNER_UNDEFINED,8,3 ## @AMDGPU_FENCE_OWNER_UNDEFINED
	.comm	_AMDGPU_FENCE_OWNER_VM,8,3      ## @AMDGPU_FENCE_OWNER_VM
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_amdgpu_sync_resv               ; -- Begin function amdgpu_sync_resv
	.p2align	2
_amdgpu_sync_resv:                      ; @amdgpu_sync_resv
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	str	w4, [sp, #12]                   ; 4-byte Folded Spill
	cbz	x2, LBB0_13
; %bb.1:
	mov	x20, x3
	mov	x21, x2
	mov	x22, x1
	mov	x23, x0
	mov	x0, x2
	bl	_dma_resv_get_excl
	mov	x2, x0
	mov	x0, x23
	mov	x1, x22
	mov	w3, #0
	bl	_amdgpu_sync_fence
	mov	x25, x0
	mov	x0, x21
	bl	_dma_resv_get_list
	cbz	x0, LBB0_15
; %bb.2:
	cbnz	w25, LBB0_15
; %bb.3:
	mov	x24, x0
	ldr	w8, [x0]
	cbz	w8, LBB0_14
; %bb.4:
	mov	x27, #0
Lloh0:
	adrp	x28, _AMDGPU_FENCE_OWNER_KFD@GOTPAGE
Lloh1:
	ldr	x28, [x28, _AMDGPU_FENCE_OWNER_KFD@GOTPAGEOFF]
Lloh2:
	adrp	x19, _AMDGPU_FENCE_OWNER_UNDEFINED@GOTPAGE
Lloh3:
	ldr	x19, [x19, _AMDGPU_FENCE_OWNER_UNDEFINED@GOTPAGEOFF]
	b	LBB0_7
LBB0_5:                                 ;   in Loop: Header=BB0_7 Depth=1
	mov	x0, x23
	mov	x1, x22
	mov	x2, x25
	mov	w3, #0
	bl	_amdgpu_sync_fence
	cbnz	w0, LBB0_16
LBB0_6:                                 ;   in Loop: Header=BB0_7 Depth=1
	add	x27, x27, #1
	ldr	w8, [x24]
	cmp	x27, x8
	b.hs	LBB0_14
LBB0_7:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x24, #8]
	ldr	w25, [x8, x27, lsl #2]
	mov	x0, x21
	bl	_dma_resv_held
	mov	x1, x0
	mov	x0, x25
	bl	_rcu_dereference_protected
	mov	x25, x0
	bl	_amdgpu_sync_get_owner
	ldr	x8, [x28]
	ldr	x9, [x19]
	cmp	x0, x8
	ccmp	x9, x20, #4, eq
	b.ne	LBB0_6
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=1
	mov	x26, x0
	mov	x0, x23
	mov	x1, x25
	bl	_amdgpu_sync_same_dev
	cbz	x0, LBB0_5
; %bb.9:                                ;   in Loop: Header=BB0_7 Depth=1
	ldr	x8, [x19]
	cmp	x8, x20
	ccmp	x26, x8, #4, ne
	b.eq	LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_7 Depth=1
Lloh4:
	adrp	x9, _AMDGPU_FENCE_OWNER_VM@GOTPAGE
Lloh5:
	ldr	x9, [x9, _AMDGPU_FENCE_OWNER_VM@GOTPAGEOFF]
Lloh6:
	ldr	x9, [x9]
	cmp	x9, x20
	cset	w10, ne
	cmp	x26, x9
	cset	w9, eq
	cmp	w10, w9
	b.eq	LBB0_6
LBB0_11:                                ;   in Loop: Header=BB0_7 Depth=1
	ldr	w9, [sp, #12]                   ; 4-byte Folded Reload
	cmp	w9, #0
	ccmp	x26, x20, #4, eq
	cset	w9, eq
	cmp	x8, x20
	b.eq	LBB0_5
; %bb.12:                               ;   in Loop: Header=BB0_7 Depth=1
	tbnz	w9, #0, LBB0_6
	b	LBB0_5
LBB0_13:
Lloh7:
	adrp	x8, _EINVAL@GOTPAGE
Lloh8:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	neg	w25, w8
	b	LBB0_15
LBB0_14:
	mov	w25, #0
LBB0_15:
	mov	x0, x25
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
LBB0_16:
	mov	x25, x0
	b	LBB0_15
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.cfi_endproc
                                        ; -- End function
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_AMDGPU_FENCE_OWNER_KFD,8,3     ; @AMDGPU_FENCE_OWNER_KFD
	.comm	_AMDGPU_FENCE_OWNER_UNDEFINED,8,3 ; @AMDGPU_FENCE_OWNER_UNDEFINED
	.comm	_AMDGPU_FENCE_OWNER_VM,8,3      ; @AMDGPU_FENCE_OWNER_VM
.subsections_via_symbols
