	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function goya_set_pll_refclk
_goya_set_pll_refclk:                   ## @goya_set_pll_refclk
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	_mmCPU_PLL_DIV_SEL_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmCPU_PLL_DIV_SEL_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmCPU_PLL_DIV_SEL_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmCPU_PLL_DIV_SEL_3@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmIC_PLL_DIV_SEL_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmIC_PLL_DIV_SEL_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmIC_PLL_DIV_SEL_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmIC_PLL_DIV_SEL_3@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmMC_PLL_DIV_SEL_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmMC_PLL_DIV_SEL_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmMC_PLL_DIV_SEL_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmMC_PLL_DIV_SEL_3@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmPSOC_MME_PLL_DIV_SEL_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmPSOC_MME_PLL_DIV_SEL_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmPSOC_MME_PLL_DIV_SEL_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmPSOC_MME_PLL_DIV_SEL_3@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmPSOC_PCI_PLL_DIV_SEL_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmPSOC_PCI_PLL_DIV_SEL_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmPSOC_PCI_PLL_DIV_SEL_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmPSOC_PCI_PLL_DIV_SEL_3@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmPSOC_EMMC_PLL_DIV_SEL_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmPSOC_EMMC_PLL_DIV_SEL_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmPSOC_EMMC_PLL_DIV_SEL_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmPSOC_EMMC_PLL_DIV_SEL_3@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmTPC_PLL_DIV_SEL_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmTPC_PLL_DIV_SEL_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmTPC_PLL_DIV_SEL_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	callq	_WREG32
	movq	_mmTPC_PLL_DIV_SEL_3@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	xorl	%esi, %esi
	popq	%rbp
	jmp	_WREG32                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_mmCPU_PLL_DIV_SEL_0,4,2        ## @mmCPU_PLL_DIV_SEL_0
	.comm	_mmCPU_PLL_DIV_SEL_1,4,2        ## @mmCPU_PLL_DIV_SEL_1
	.comm	_mmCPU_PLL_DIV_SEL_2,4,2        ## @mmCPU_PLL_DIV_SEL_2
	.comm	_mmCPU_PLL_DIV_SEL_3,4,2        ## @mmCPU_PLL_DIV_SEL_3
	.comm	_mmIC_PLL_DIV_SEL_0,4,2         ## @mmIC_PLL_DIV_SEL_0
	.comm	_mmIC_PLL_DIV_SEL_1,4,2         ## @mmIC_PLL_DIV_SEL_1
	.comm	_mmIC_PLL_DIV_SEL_2,4,2         ## @mmIC_PLL_DIV_SEL_2
	.comm	_mmIC_PLL_DIV_SEL_3,4,2         ## @mmIC_PLL_DIV_SEL_3
	.comm	_mmMC_PLL_DIV_SEL_0,4,2         ## @mmMC_PLL_DIV_SEL_0
	.comm	_mmMC_PLL_DIV_SEL_1,4,2         ## @mmMC_PLL_DIV_SEL_1
	.comm	_mmMC_PLL_DIV_SEL_2,4,2         ## @mmMC_PLL_DIV_SEL_2
	.comm	_mmMC_PLL_DIV_SEL_3,4,2         ## @mmMC_PLL_DIV_SEL_3
	.comm	_mmPSOC_MME_PLL_DIV_SEL_0,4,2   ## @mmPSOC_MME_PLL_DIV_SEL_0
	.comm	_mmPSOC_MME_PLL_DIV_SEL_1,4,2   ## @mmPSOC_MME_PLL_DIV_SEL_1
	.comm	_mmPSOC_MME_PLL_DIV_SEL_2,4,2   ## @mmPSOC_MME_PLL_DIV_SEL_2
	.comm	_mmPSOC_MME_PLL_DIV_SEL_3,4,2   ## @mmPSOC_MME_PLL_DIV_SEL_3
	.comm	_mmPSOC_PCI_PLL_DIV_SEL_0,4,2   ## @mmPSOC_PCI_PLL_DIV_SEL_0
	.comm	_mmPSOC_PCI_PLL_DIV_SEL_1,4,2   ## @mmPSOC_PCI_PLL_DIV_SEL_1
	.comm	_mmPSOC_PCI_PLL_DIV_SEL_2,4,2   ## @mmPSOC_PCI_PLL_DIV_SEL_2
	.comm	_mmPSOC_PCI_PLL_DIV_SEL_3,4,2   ## @mmPSOC_PCI_PLL_DIV_SEL_3
	.comm	_mmPSOC_EMMC_PLL_DIV_SEL_0,4,2  ## @mmPSOC_EMMC_PLL_DIV_SEL_0
	.comm	_mmPSOC_EMMC_PLL_DIV_SEL_1,4,2  ## @mmPSOC_EMMC_PLL_DIV_SEL_1
	.comm	_mmPSOC_EMMC_PLL_DIV_SEL_2,4,2  ## @mmPSOC_EMMC_PLL_DIV_SEL_2
	.comm	_mmPSOC_EMMC_PLL_DIV_SEL_3,4,2  ## @mmPSOC_EMMC_PLL_DIV_SEL_3
	.comm	_mmTPC_PLL_DIV_SEL_0,4,2        ## @mmTPC_PLL_DIV_SEL_0
	.comm	_mmTPC_PLL_DIV_SEL_1,4,2        ## @mmTPC_PLL_DIV_SEL_1
	.comm	_mmTPC_PLL_DIV_SEL_2,4,2        ## @mmTPC_PLL_DIV_SEL_2
	.comm	_mmTPC_PLL_DIV_SEL_3,4,2        ## @mmTPC_PLL_DIV_SEL_3
	.no_dead_strip	_goya_set_pll_refclk
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function goya_set_pll_refclk
_goya_set_pll_refclk:                   ; @goya_set_pll_refclk
	.cfi_startproc
; %bb.0:
	stp	x29, x30, [sp, #-16]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 16
	mov	x29, sp
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
Lloh0:
	adrp	x8, _mmCPU_PLL_DIV_SEL_0@GOTPAGE
Lloh1:
	ldr	x8, [x8, _mmCPU_PLL_DIV_SEL_0@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh3:
	adrp	x8, _mmCPU_PLL_DIV_SEL_1@GOTPAGE
Lloh4:
	ldr	x8, [x8, _mmCPU_PLL_DIV_SEL_1@GOTPAGEOFF]
Lloh5:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh6:
	adrp	x8, _mmCPU_PLL_DIV_SEL_2@GOTPAGE
Lloh7:
	ldr	x8, [x8, _mmCPU_PLL_DIV_SEL_2@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh9:
	adrp	x8, _mmCPU_PLL_DIV_SEL_3@GOTPAGE
Lloh10:
	ldr	x8, [x8, _mmCPU_PLL_DIV_SEL_3@GOTPAGEOFF]
Lloh11:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh12:
	adrp	x8, _mmIC_PLL_DIV_SEL_0@GOTPAGE
Lloh13:
	ldr	x8, [x8, _mmIC_PLL_DIV_SEL_0@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh15:
	adrp	x8, _mmIC_PLL_DIV_SEL_1@GOTPAGE
Lloh16:
	ldr	x8, [x8, _mmIC_PLL_DIV_SEL_1@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh18:
	adrp	x8, _mmIC_PLL_DIV_SEL_2@GOTPAGE
Lloh19:
	ldr	x8, [x8, _mmIC_PLL_DIV_SEL_2@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh21:
	adrp	x8, _mmIC_PLL_DIV_SEL_3@GOTPAGE
Lloh22:
	ldr	x8, [x8, _mmIC_PLL_DIV_SEL_3@GOTPAGEOFF]
Lloh23:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh24:
	adrp	x8, _mmMC_PLL_DIV_SEL_0@GOTPAGE
Lloh25:
	ldr	x8, [x8, _mmMC_PLL_DIV_SEL_0@GOTPAGEOFF]
Lloh26:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh27:
	adrp	x8, _mmMC_PLL_DIV_SEL_1@GOTPAGE
Lloh28:
	ldr	x8, [x8, _mmMC_PLL_DIV_SEL_1@GOTPAGEOFF]
Lloh29:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh30:
	adrp	x8, _mmMC_PLL_DIV_SEL_2@GOTPAGE
Lloh31:
	ldr	x8, [x8, _mmMC_PLL_DIV_SEL_2@GOTPAGEOFF]
Lloh32:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh33:
	adrp	x8, _mmMC_PLL_DIV_SEL_3@GOTPAGE
Lloh34:
	ldr	x8, [x8, _mmMC_PLL_DIV_SEL_3@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh36:
	adrp	x8, _mmPSOC_MME_PLL_DIV_SEL_0@GOTPAGE
Lloh37:
	ldr	x8, [x8, _mmPSOC_MME_PLL_DIV_SEL_0@GOTPAGEOFF]
Lloh38:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh39:
	adrp	x8, _mmPSOC_MME_PLL_DIV_SEL_1@GOTPAGE
Lloh40:
	ldr	x8, [x8, _mmPSOC_MME_PLL_DIV_SEL_1@GOTPAGEOFF]
Lloh41:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh42:
	adrp	x8, _mmPSOC_MME_PLL_DIV_SEL_2@GOTPAGE
Lloh43:
	ldr	x8, [x8, _mmPSOC_MME_PLL_DIV_SEL_2@GOTPAGEOFF]
Lloh44:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh45:
	adrp	x8, _mmPSOC_MME_PLL_DIV_SEL_3@GOTPAGE
Lloh46:
	ldr	x8, [x8, _mmPSOC_MME_PLL_DIV_SEL_3@GOTPAGEOFF]
Lloh47:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh48:
	adrp	x8, _mmPSOC_PCI_PLL_DIV_SEL_0@GOTPAGE
Lloh49:
	ldr	x8, [x8, _mmPSOC_PCI_PLL_DIV_SEL_0@GOTPAGEOFF]
Lloh50:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh51:
	adrp	x8, _mmPSOC_PCI_PLL_DIV_SEL_1@GOTPAGE
Lloh52:
	ldr	x8, [x8, _mmPSOC_PCI_PLL_DIV_SEL_1@GOTPAGEOFF]
Lloh53:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh54:
	adrp	x8, _mmPSOC_PCI_PLL_DIV_SEL_2@GOTPAGE
Lloh55:
	ldr	x8, [x8, _mmPSOC_PCI_PLL_DIV_SEL_2@GOTPAGEOFF]
Lloh56:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh57:
	adrp	x8, _mmPSOC_PCI_PLL_DIV_SEL_3@GOTPAGE
Lloh58:
	ldr	x8, [x8, _mmPSOC_PCI_PLL_DIV_SEL_3@GOTPAGEOFF]
Lloh59:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh60:
	adrp	x8, _mmPSOC_EMMC_PLL_DIV_SEL_0@GOTPAGE
Lloh61:
	ldr	x8, [x8, _mmPSOC_EMMC_PLL_DIV_SEL_0@GOTPAGEOFF]
Lloh62:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh63:
	adrp	x8, _mmPSOC_EMMC_PLL_DIV_SEL_1@GOTPAGE
Lloh64:
	ldr	x8, [x8, _mmPSOC_EMMC_PLL_DIV_SEL_1@GOTPAGEOFF]
Lloh65:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh66:
	adrp	x8, _mmPSOC_EMMC_PLL_DIV_SEL_2@GOTPAGE
Lloh67:
	ldr	x8, [x8, _mmPSOC_EMMC_PLL_DIV_SEL_2@GOTPAGEOFF]
Lloh68:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh69:
	adrp	x8, _mmPSOC_EMMC_PLL_DIV_SEL_3@GOTPAGE
Lloh70:
	ldr	x8, [x8, _mmPSOC_EMMC_PLL_DIV_SEL_3@GOTPAGEOFF]
Lloh71:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh72:
	adrp	x8, _mmTPC_PLL_DIV_SEL_0@GOTPAGE
Lloh73:
	ldr	x8, [x8, _mmTPC_PLL_DIV_SEL_0@GOTPAGEOFF]
Lloh74:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh75:
	adrp	x8, _mmTPC_PLL_DIV_SEL_1@GOTPAGE
Lloh76:
	ldr	x8, [x8, _mmTPC_PLL_DIV_SEL_1@GOTPAGEOFF]
Lloh77:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh78:
	adrp	x8, _mmTPC_PLL_DIV_SEL_2@GOTPAGE
Lloh79:
	ldr	x8, [x8, _mmTPC_PLL_DIV_SEL_2@GOTPAGEOFF]
Lloh80:
	ldr	w0, [x8]
	mov	w1, #0
	bl	_WREG32
Lloh81:
	adrp	x8, _mmTPC_PLL_DIV_SEL_3@GOTPAGE
Lloh82:
	ldr	x8, [x8, _mmTPC_PLL_DIV_SEL_3@GOTPAGEOFF]
Lloh83:
	ldr	w0, [x8]
	mov	w1, #0
	ldp	x29, x30, [sp], #16             ; 16-byte Folded Reload
	b	_WREG32
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_mmCPU_PLL_DIV_SEL_0,4,2        ; @mmCPU_PLL_DIV_SEL_0
	.comm	_mmCPU_PLL_DIV_SEL_1,4,2        ; @mmCPU_PLL_DIV_SEL_1
	.comm	_mmCPU_PLL_DIV_SEL_2,4,2        ; @mmCPU_PLL_DIV_SEL_2
	.comm	_mmCPU_PLL_DIV_SEL_3,4,2        ; @mmCPU_PLL_DIV_SEL_3
	.comm	_mmIC_PLL_DIV_SEL_0,4,2         ; @mmIC_PLL_DIV_SEL_0
	.comm	_mmIC_PLL_DIV_SEL_1,4,2         ; @mmIC_PLL_DIV_SEL_1
	.comm	_mmIC_PLL_DIV_SEL_2,4,2         ; @mmIC_PLL_DIV_SEL_2
	.comm	_mmIC_PLL_DIV_SEL_3,4,2         ; @mmIC_PLL_DIV_SEL_3
	.comm	_mmMC_PLL_DIV_SEL_0,4,2         ; @mmMC_PLL_DIV_SEL_0
	.comm	_mmMC_PLL_DIV_SEL_1,4,2         ; @mmMC_PLL_DIV_SEL_1
	.comm	_mmMC_PLL_DIV_SEL_2,4,2         ; @mmMC_PLL_DIV_SEL_2
	.comm	_mmMC_PLL_DIV_SEL_3,4,2         ; @mmMC_PLL_DIV_SEL_3
	.comm	_mmPSOC_MME_PLL_DIV_SEL_0,4,2   ; @mmPSOC_MME_PLL_DIV_SEL_0
	.comm	_mmPSOC_MME_PLL_DIV_SEL_1,4,2   ; @mmPSOC_MME_PLL_DIV_SEL_1
	.comm	_mmPSOC_MME_PLL_DIV_SEL_2,4,2   ; @mmPSOC_MME_PLL_DIV_SEL_2
	.comm	_mmPSOC_MME_PLL_DIV_SEL_3,4,2   ; @mmPSOC_MME_PLL_DIV_SEL_3
	.comm	_mmPSOC_PCI_PLL_DIV_SEL_0,4,2   ; @mmPSOC_PCI_PLL_DIV_SEL_0
	.comm	_mmPSOC_PCI_PLL_DIV_SEL_1,4,2   ; @mmPSOC_PCI_PLL_DIV_SEL_1
	.comm	_mmPSOC_PCI_PLL_DIV_SEL_2,4,2   ; @mmPSOC_PCI_PLL_DIV_SEL_2
	.comm	_mmPSOC_PCI_PLL_DIV_SEL_3,4,2   ; @mmPSOC_PCI_PLL_DIV_SEL_3
	.comm	_mmPSOC_EMMC_PLL_DIV_SEL_0,4,2  ; @mmPSOC_EMMC_PLL_DIV_SEL_0
	.comm	_mmPSOC_EMMC_PLL_DIV_SEL_1,4,2  ; @mmPSOC_EMMC_PLL_DIV_SEL_1
	.comm	_mmPSOC_EMMC_PLL_DIV_SEL_2,4,2  ; @mmPSOC_EMMC_PLL_DIV_SEL_2
	.comm	_mmPSOC_EMMC_PLL_DIV_SEL_3,4,2  ; @mmPSOC_EMMC_PLL_DIV_SEL_3
	.comm	_mmTPC_PLL_DIV_SEL_0,4,2        ; @mmTPC_PLL_DIV_SEL_0
	.comm	_mmTPC_PLL_DIV_SEL_1,4,2        ; @mmTPC_PLL_DIV_SEL_1
	.comm	_mmTPC_PLL_DIV_SEL_2,4,2        ; @mmTPC_PLL_DIV_SEL_2
	.comm	_mmTPC_PLL_DIV_SEL_3,4,2        ; @mmTPC_PLL_DIV_SEL_3
	.no_dead_strip	_goya_set_pll_refclk
.subsections_via_symbols
