	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_qib_pcie_params                ## -- Begin function qib_pcie_params
	.p2align	4, 0x90
_qib_pcie_params:                       ## @qib_pcie_params
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r12
	movl	%esi, %r14d
	movq	%rdi, %r13
	movq	_PCI_IRQ_MSIX@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_PCI_IRQ_MSI@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	16(%rdi), %rdi
	callq	_pci_is_pcie
	testl	%eax, %eax
	je	LBB0_1
## %bb.2:
	orl	%r15d, %ebx
	movq	_QIB_HAS_INTX@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	8(%r13), %eax
	je	LBB0_4
## %bb.3:
	movq	_PCI_IRQ_LEGACY@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_4:
	orl	%eax, %ebx
	testq	%r12, %r12
	je	LBB0_5
## %bb.7:
	movl	(%r12), %edx
	testl	%edx, %edx
	movl	$1, %eax
	cmovel	%eax, %edx
	movq	16(%r13), %rdi
	movl	$1, %esi
	movl	%ebx, %ecx
	callq	_pci_alloc_irq_vectors
	movl	%eax, %r15d
	testl	%eax, %eax
	js	LBB0_15
## %bb.8:
	movq	16(%r13), %rdi
	movl	16(%rdi), %eax
	testl	%eax, %eax
	movl	%r15d, %ecx
	cmovel	%eax, %ecx
	movl	%ecx, (%r12)
	cmpq	$0, 8(%rdi)
	je	LBB0_11
LBB0_10:
	movl	(%rdi), %esi
	movq	%r13, %rdi
	callq	_qib_cache_msi_info
	movq	16(%r13), %rdi
LBB0_11:
	movq	_PCI_EXP_LNKSTA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-44(%rbp), %rdx
	callq	_pcie_capability_read_word
	movl	-44(%rbp), %edx
	movl	%edx, %eax
	andl	$15, %eax
	shrl	$4, %edx
	andl	$31, %edx
	movl	%edx, -44(%rbp)
	movl	%edx, (%r13)
	cmpl	$2, %eax
	movl	$5000, %ecx                     ## imm = 0x1388
	movl	$2500, %esi                     ## imm = 0x9C4
	cmovnel	%esi, %ecx
	cmpl	$1, %eax
	cmovel	%esi, %ecx
	movl	%ecx, 4(%r13)
	testl	%r14d, %r14d
	je	LBB0_14
## %bb.12:
	cmpl	%r14d, %edx
	jge	LBB0_14
## %bb.13:
	leaq	L_.str.1(%rip), %rsi
	movq	%r13, %rdi
	movl	%r14d, %ecx
	xorl	%eax, %eax
	callq	_qib_dev_err
LBB0_14:
	movq	%r13, %rdi
	callq	_qib_tune_pcie_caps
	movq	%r13, %rdi
	callq	_qib_tune_pcie_coalesce
	jmp	LBB0_15
LBB0_1:
	leaq	L_.str(%rip), %rsi
	movq	%r13, %rdi
	xorl	%eax, %eax
	callq	_qib_dev_err
	movabsq	$10737418240001, %rax           ## imm = 0x9C400000001
	movq	%rax, (%r13)
	movl	$-1, %r15d
LBB0_15:
	movl	12(%r13), %edi
	movl	(%r13), %r8d
	movl	4(%r13), %ecx
	leaq	L_.str.2(%rip), %rdx
	movl	$4, %esi
	callq	_snprintf
	movl	%r15d, %eax
	sarl	$31, %eax
	andl	%r15d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_5:
	movq	16(%r13), %rdi
	movl	$1, %esi
	movl	$1, %edx
	movl	%ebx, %ecx
	callq	_pci_alloc_irq_vectors
	movl	%eax, %r15d
	testl	%eax, %eax
	js	LBB0_15
## %bb.6:
	movq	16(%r13), %rdi
	cmpq	$0, 8(%rdi)
	jne	LBB0_10
	jmp	LBB0_11
	.cfi_endproc
                                        ## -- End function
	.comm	_PCI_IRQ_MSIX,4,2               ## @PCI_IRQ_MSIX
	.comm	_PCI_IRQ_MSI,4,2                ## @PCI_IRQ_MSI
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Can't find PCI Express capability!\n"

	.comm	_QIB_HAS_INTX,4,2               ## @QIB_HAS_INTX
	.comm	_PCI_IRQ_LEGACY,4,2             ## @PCI_IRQ_LEGACY
	.comm	_PCI_EXP_LNKSTA,4,2             ## @PCI_EXP_LNKSTA
L_.str.1:                               ## @.str.1
	.asciz	"PCIe width %u (x%u HCA), performance reduced\n"

L_.str.2:                               ## @.str.2
	.asciz	"PCIe,%uMHz,x%u\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3                               ; -- Begin function qib_pcie_params
lCPI0_0:
	.long	1                               ; 0x1
	.long	2500                            ; 0x9c4
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_qib_pcie_params
	.p2align	2
_qib_pcie_params:                       ; @qib_pcie_params
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x22, x2
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x8, _PCI_IRQ_MSIX@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCI_IRQ_MSIX@GOTPAGEOFF]
Lloh2:
	ldr	w21, [x8]
Lloh3:
	adrp	x8, _PCI_IRQ_MSI@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCI_IRQ_MSI@GOTPAGEOFF]
Lloh5:
	ldr	w23, [x8]
	ldr	x0, [x0, #16]
	bl	_pci_is_pcie
	cbz	w0, LBB0_9
; %bb.1:
	orr	w8, w23, w21
	ldr	w9, [x19, #8]
Lloh6:
	adrp	x10, _QIB_HAS_INTX@GOTPAGE
Lloh7:
	ldr	x10, [x10, _QIB_HAS_INTX@GOTPAGEOFF]
Lloh8:
	ldr	w10, [x10]
Lloh9:
	adrp	x11, _PCI_IRQ_LEGACY@GOTPAGE
Lloh10:
	ldr	x11, [x11, _PCI_IRQ_LEGACY@GOTPAGEOFF]
Lloh11:
	ldr	w11, [x11]
	tst	w10, w9
	csel	w9, wzr, w11, eq
	orr	w3, w8, w9
	cbz	x22, LBB0_11
; %bb.2:
	ldr	w8, [x22]
	cmp	w8, #0
	csinc	w2, w8, wzr, ne
	ldr	x0, [x19, #16]
	mov	w1, #1
	bl	_pci_alloc_irq_vectors
	mov	x21, x0
	tbnz	w0, #31, LBB0_10
; %bb.3:
	ldr	x0, [x19, #16]
	ldr	w8, [x0, #16]
	cmp	w8, #0
	csel	w8, wzr, w21, eq
	str	w8, [x22]
	ldr	x8, [x0, #8]
	cbz	x8, LBB0_5
LBB0_4:
	ldr	w1, [x0]
	mov	x0, x19
	bl	_qib_cache_msi_info
	ldr	x0, [x19, #16]
LBB0_5:
Lloh12:
	adrp	x8, _PCI_EXP_LNKSTA@GOTPAGE
Lloh13:
	ldr	x8, [x8, _PCI_EXP_LNKSTA@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	add	x2, sp, #28
	bl	_pcie_capability_read_word
	ldr	w8, [sp, #28]
	and	w9, w8, #0xf
	ubfx	w8, w8, #4, #5
	str	w8, [sp, #28]
	mov	w10, #2500
	mov	w11, #5000
	cmp	w9, #2
	csel	w11, w11, w10, eq
	cmp	w9, #1
	csel	w9, w10, w11, eq
	stp	w8, w9, [x19]
	cbz	w20, LBB0_8
; %bb.6:
	cmp	w8, w20
	b.ge	LBB0_8
; %bb.7:
	stp	x8, x20, [sp]
Lloh15:
	adrp	x1, l_.str.1@PAGE
Lloh16:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x19
	bl	_qib_dev_err
LBB0_8:
	mov	x0, x19
	bl	_qib_tune_pcie_caps
	mov	x0, x19
	bl	_qib_tune_pcie_coalesce
	b	LBB0_10
LBB0_9:
Lloh17:
	adrp	x1, l_.str@PAGE
Lloh18:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x19
	bl	_qib_dev_err
Lloh19:
	adrp	x8, lCPI0_0@PAGE
Lloh20:
	ldr	d0, [x8, lCPI0_0@PAGEOFF]
	str	d0, [x19]
	mov	w21, #-1
LBB0_10:
	ldr	w0, [x19, #12]
	ldp	w4, w3, [x19]
Lloh21:
	adrp	x2, l_.str.2@PAGE
Lloh22:
	add	x2, x2, l_.str.2@PAGEOFF
	mov	w1, #4
	bl	_snprintf
	cmp	w21, #0
	csel	w0, w21, wzr, lt
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_11:
	ldr	x0, [x19, #16]
	mov	w1, #1
	mov	w2, #1
	bl	_pci_alloc_irq_vectors
	mov	x21, x0
	tbnz	w0, #31, LBB0_10
; %bb.12:
	ldr	x0, [x19, #16]
	ldr	x8, [x0, #8]
	cbnz	x8, LBB0_4
	b	LBB0_5
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdr	Lloh19, Lloh20
	.loh AdrpAdd	Lloh17, Lloh18
	.loh AdrpAdd	Lloh21, Lloh22
	.cfi_endproc
                                        ; -- End function
	.comm	_PCI_IRQ_MSIX,4,2               ; @PCI_IRQ_MSIX
	.comm	_PCI_IRQ_MSI,4,2                ; @PCI_IRQ_MSI
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Can't find PCI Express capability!\n"

	.comm	_QIB_HAS_INTX,4,2               ; @QIB_HAS_INTX
	.comm	_PCI_IRQ_LEGACY,4,2             ; @PCI_IRQ_LEGACY
	.comm	_PCI_EXP_LNKSTA,4,2             ; @PCI_EXP_LNKSTA
l_.str.1:                               ; @.str.1
	.asciz	"PCIe width %u (x%u HCA), performance reduced\n"

l_.str.2:                               ; @.str.2
	.asciz	"PCIe,%uMHz,x%u\n"

.subsections_via_symbols
