	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function xenon_set_uhs_signaling
_xenon_set_uhs_signaling:               ## @xenon_set_uhs_signaling
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %ebx
	movq	%rdi, %r14
	movq	_SDHCI_HOST_CONTROL2@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	callq	_sdhci_readw
	movq	_SDHCI_CTRL_UHS_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_MMC_TIMING_MMC_HS200@GOTPCREL(%rip), %rax
	cmpl	%ebx, (%rax)
	jne	LBB0_2
## %bb.1:
	movq	_XENON_CTRL_HS200@GOTPCREL(%rip), %rax
	jmp	LBB0_15
LBB0_2:
	movq	_MMC_TIMING_UHS_SDR104@GOTPCREL(%rip), %rax
	cmpl	%ebx, (%rax)
	jne	LBB0_4
## %bb.3:
	movq	_SDHCI_CTRL_UHS_SDR104@GOTPCREL(%rip), %rax
	jmp	LBB0_15
LBB0_4:
	movq	_MMC_TIMING_UHS_SDR12@GOTPCREL(%rip), %rax
	cmpl	%ebx, (%rax)
	jne	LBB0_6
## %bb.5:
	movq	_SDHCI_CTRL_UHS_SDR12@GOTPCREL(%rip), %rax
	jmp	LBB0_15
LBB0_6:
	movq	_MMC_TIMING_UHS_SDR25@GOTPCREL(%rip), %rax
	cmpl	%ebx, (%rax)
	jne	LBB0_8
## %bb.7:
	movq	_SDHCI_CTRL_UHS_SDR25@GOTPCREL(%rip), %rax
	jmp	LBB0_15
LBB0_8:
	movq	_MMC_TIMING_UHS_SDR50@GOTPCREL(%rip), %rax
	cmpl	%ebx, (%rax)
	jne	LBB0_10
## %bb.9:
	movq	_SDHCI_CTRL_UHS_SDR50@GOTPCREL(%rip), %rax
	jmp	LBB0_15
LBB0_10:
	movq	_MMC_TIMING_UHS_DDR50@GOTPCREL(%rip), %rax
	cmpl	%ebx, (%rax)
	je	LBB0_12
## %bb.11:
	movq	_MMC_TIMING_MMC_DDR52@GOTPCREL(%rip), %rax
	cmpl	%ebx, (%rax)
	je	LBB0_12
## %bb.13:
	movq	_MMC_TIMING_MMC_HS400@GOTPCREL(%rip), %rax
	cmpl	%ebx, (%rax)
	jne	LBB0_16
## %bb.14:
	movq	_XENON_CTRL_HS400@GOTPCREL(%rip), %rax
	jmp	LBB0_15
LBB0_12:
	movq	_SDHCI_CTRL_UHS_DDR50@GOTPCREL(%rip), %rax
LBB0_15:
	orl	(%rax), %esi
LBB0_16:
	movl	(%r15), %edx
	movq	%r14, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_sdhci_writew                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_SDHCI_HOST_CONTROL2,4,2        ## @SDHCI_HOST_CONTROL2
	.comm	_SDHCI_CTRL_UHS_MASK,4,2        ## @SDHCI_CTRL_UHS_MASK
	.comm	_MMC_TIMING_MMC_HS200,4,2       ## @MMC_TIMING_MMC_HS200
	.comm	_XENON_CTRL_HS200,4,2           ## @XENON_CTRL_HS200
	.comm	_MMC_TIMING_UHS_SDR104,4,2      ## @MMC_TIMING_UHS_SDR104
	.comm	_SDHCI_CTRL_UHS_SDR104,4,2      ## @SDHCI_CTRL_UHS_SDR104
	.comm	_MMC_TIMING_UHS_SDR12,4,2       ## @MMC_TIMING_UHS_SDR12
	.comm	_SDHCI_CTRL_UHS_SDR12,4,2       ## @SDHCI_CTRL_UHS_SDR12
	.comm	_MMC_TIMING_UHS_SDR25,4,2       ## @MMC_TIMING_UHS_SDR25
	.comm	_SDHCI_CTRL_UHS_SDR25,4,2       ## @SDHCI_CTRL_UHS_SDR25
	.comm	_MMC_TIMING_UHS_SDR50,4,2       ## @MMC_TIMING_UHS_SDR50
	.comm	_SDHCI_CTRL_UHS_SDR50,4,2       ## @SDHCI_CTRL_UHS_SDR50
	.comm	_MMC_TIMING_UHS_DDR50,4,2       ## @MMC_TIMING_UHS_DDR50
	.comm	_MMC_TIMING_MMC_DDR52,4,2       ## @MMC_TIMING_MMC_DDR52
	.comm	_SDHCI_CTRL_UHS_DDR50,4,2       ## @SDHCI_CTRL_UHS_DDR50
	.comm	_MMC_TIMING_MMC_HS400,4,2       ## @MMC_TIMING_MMC_HS400
	.comm	_XENON_CTRL_HS400,4,2           ## @XENON_CTRL_HS400
	.no_dead_strip	_xenon_set_uhs_signaling
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function xenon_set_uhs_signaling
_xenon_set_uhs_signaling:               ; @xenon_set_uhs_signaling
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x21, _SDHCI_HOST_CONTROL2@GOTPAGE
Lloh1:
	ldr	x21, [x21, _SDHCI_HOST_CONTROL2@GOTPAGEOFF]
	ldr	w1, [x21]
	bl	_sdhci_readw
Lloh2:
	adrp	x8, _SDHCI_CTRL_UHS_MASK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _SDHCI_CTRL_UHS_MASK@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	bic	w1, w0, w8
Lloh5:
	adrp	x8, _MMC_TIMING_MMC_HS200@GOTPAGE
Lloh6:
	ldr	x8, [x8, _MMC_TIMING_MMC_HS200@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	cmp	w8, w20
	b.ne	LBB0_2
; %bb.1:
Lloh8:
	adrp	x8, _XENON_CTRL_HS200@GOTPAGE
Lloh9:
	ldr	x8, [x8, _XENON_CTRL_HS200@GOTPAGEOFF]
	b	LBB0_14
LBB0_2:
Lloh10:
	adrp	x8, _MMC_TIMING_UHS_SDR104@GOTPAGE
Lloh11:
	ldr	x8, [x8, _MMC_TIMING_UHS_SDR104@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	cmp	w8, w20
	b.ne	LBB0_4
; %bb.3:
Lloh13:
	adrp	x8, _SDHCI_CTRL_UHS_SDR104@GOTPAGE
Lloh14:
	ldr	x8, [x8, _SDHCI_CTRL_UHS_SDR104@GOTPAGEOFF]
	b	LBB0_14
LBB0_4:
Lloh15:
	adrp	x8, _MMC_TIMING_UHS_SDR12@GOTPAGE
Lloh16:
	ldr	x8, [x8, _MMC_TIMING_UHS_SDR12@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	cmp	w8, w20
	b.ne	LBB0_6
; %bb.5:
Lloh18:
	adrp	x8, _SDHCI_CTRL_UHS_SDR12@GOTPAGE
Lloh19:
	ldr	x8, [x8, _SDHCI_CTRL_UHS_SDR12@GOTPAGEOFF]
	b	LBB0_14
LBB0_6:
Lloh20:
	adrp	x8, _MMC_TIMING_UHS_SDR25@GOTPAGE
Lloh21:
	ldr	x8, [x8, _MMC_TIMING_UHS_SDR25@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
	cmp	w8, w20
	b.ne	LBB0_8
; %bb.7:
Lloh23:
	adrp	x8, _SDHCI_CTRL_UHS_SDR25@GOTPAGE
Lloh24:
	ldr	x8, [x8, _SDHCI_CTRL_UHS_SDR25@GOTPAGEOFF]
	b	LBB0_14
LBB0_8:
Lloh25:
	adrp	x8, _MMC_TIMING_UHS_SDR50@GOTPAGE
Lloh26:
	ldr	x8, [x8, _MMC_TIMING_UHS_SDR50@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
	cmp	w8, w20
	b.ne	LBB0_10
; %bb.9:
Lloh28:
	adrp	x8, _SDHCI_CTRL_UHS_SDR50@GOTPAGE
Lloh29:
	ldr	x8, [x8, _SDHCI_CTRL_UHS_SDR50@GOTPAGEOFF]
	b	LBB0_14
LBB0_10:
Lloh30:
	adrp	x8, _MMC_TIMING_UHS_DDR50@GOTPAGE
Lloh31:
	ldr	x8, [x8, _MMC_TIMING_UHS_DDR50@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
Lloh33:
	adrp	x9, _MMC_TIMING_MMC_DDR52@GOTPAGE
Lloh34:
	ldr	x9, [x9, _MMC_TIMING_MMC_DDR52@GOTPAGEOFF]
Lloh35:
	ldr	w9, [x9]
	cmp	w8, w20
	ccmp	w9, w20, #4, ne
	b.ne	LBB0_12
; %bb.11:
Lloh36:
	adrp	x8, _SDHCI_CTRL_UHS_DDR50@GOTPAGE
Lloh37:
	ldr	x8, [x8, _SDHCI_CTRL_UHS_DDR50@GOTPAGEOFF]
	b	LBB0_14
LBB0_12:
Lloh38:
	adrp	x8, _MMC_TIMING_MMC_HS400@GOTPAGE
Lloh39:
	ldr	x8, [x8, _MMC_TIMING_MMC_HS400@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
	cmp	w8, w20
	b.ne	LBB0_15
; %bb.13:
Lloh41:
	adrp	x8, _XENON_CTRL_HS400@GOTPAGE
Lloh42:
	ldr	x8, [x8, _XENON_CTRL_HS400@GOTPAGEOFF]
LBB0_14:
	ldr	w8, [x8]
	orr	w1, w8, w1
LBB0_15:
	ldr	w2, [x21]
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_sdhci_writew
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh41, Lloh42
	.cfi_endproc
                                        ; -- End function
	.comm	_SDHCI_HOST_CONTROL2,4,2        ; @SDHCI_HOST_CONTROL2
	.comm	_SDHCI_CTRL_UHS_MASK,4,2        ; @SDHCI_CTRL_UHS_MASK
	.comm	_MMC_TIMING_MMC_HS200,4,2       ; @MMC_TIMING_MMC_HS200
	.comm	_XENON_CTRL_HS200,4,2           ; @XENON_CTRL_HS200
	.comm	_MMC_TIMING_UHS_SDR104,4,2      ; @MMC_TIMING_UHS_SDR104
	.comm	_SDHCI_CTRL_UHS_SDR104,4,2      ; @SDHCI_CTRL_UHS_SDR104
	.comm	_MMC_TIMING_UHS_SDR12,4,2       ; @MMC_TIMING_UHS_SDR12
	.comm	_SDHCI_CTRL_UHS_SDR12,4,2       ; @SDHCI_CTRL_UHS_SDR12
	.comm	_MMC_TIMING_UHS_SDR25,4,2       ; @MMC_TIMING_UHS_SDR25
	.comm	_SDHCI_CTRL_UHS_SDR25,4,2       ; @SDHCI_CTRL_UHS_SDR25
	.comm	_MMC_TIMING_UHS_SDR50,4,2       ; @MMC_TIMING_UHS_SDR50
	.comm	_SDHCI_CTRL_UHS_SDR50,4,2       ; @SDHCI_CTRL_UHS_SDR50
	.comm	_MMC_TIMING_UHS_DDR50,4,2       ; @MMC_TIMING_UHS_DDR50
	.comm	_MMC_TIMING_MMC_DDR52,4,2       ; @MMC_TIMING_MMC_DDR52
	.comm	_SDHCI_CTRL_UHS_DDR50,4,2       ; @SDHCI_CTRL_UHS_DDR50
	.comm	_MMC_TIMING_MMC_HS400,4,2       ; @MMC_TIMING_MMC_HS400
	.comm	_XENON_CTRL_HS400,4,2           ; @XENON_CTRL_HS400
	.no_dead_strip	_xenon_set_uhs_signaling
.subsections_via_symbols
