	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function atl1c_configure_des_ring
_atl1c_configure_des_ring:              ## @atl1c_configure_des_ring
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	leaq	32(%rdi), %rbx
	movq	8(%rdi), %r12
	movq	_REG_TX_BASE_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_AT_WRITE_REG
	movq	_REG_TPD_PRI0_ADDR_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_atl1c_trans_normal@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_AT_DMA_LO_ADDR_MASK@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	andl	(%r12,%rax,8), %edx
	movq	%rbx, %rdi
	callq	_AT_WRITE_REG
	movq	_REG_TPD_PRI1_ADDR_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_atl1c_trans_high@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movl	(%r15), %edx
	andl	(%r12,%rax,8), %edx
	movq	%rbx, %rdi
	callq	_AT_WRITE_REG
	movq	_REG_TPD_RING_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_TPD_RING_SIZE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	andl	4(%r12), %edx
	movq	%rbx, %rdi
	callq	_AT_WRITE_REG
	movq	_REG_RX_BASE_ADDR_HI@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_AT_WRITE_REG
	movq	_REG_RFD0_HEAD_ADDR_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r15), %edx
	andl	24(%r14), %edx
	movq	%rbx, %rdi
	callq	_AT_WRITE_REG
	movq	_REG_RFD_RING_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_RFD_RING_SIZE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	andl	28(%r14), %edx
	movq	%rbx, %rdi
	callq	_AT_WRITE_REG
	movq	_REG_RX_BUF_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_RX_BUF_SIZE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	andl	(%r14), %edx
	movq	%rbx, %rdi
	callq	_AT_WRITE_REG
	movq	_REG_RRD0_HEAD_ADDR_LO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r15), %edx
	andl	16(%r14), %edx
	movq	%rbx, %rdi
	callq	_AT_WRITE_REG
	movq	_REG_RRD_RING_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_RRD_RING_SIZE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	andl	20(%r14), %edx
	movq	%rbx, %rdi
	callq	_AT_WRITE_REG
	movq	32(%r14), %rax
	movq	_athr_l2c_b@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_2
## %bb.1:
	movq	_REG_SRAM_RXF_LEN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$672, %edx                      ## imm = 0x2A0
	callq	_AT_WRITE_REG
	movq	_REG_SRAM_TXF_LEN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$256, %edx                      ## imm = 0x100
	callq	_AT_WRITE_REG
	movq	_REG_SRAM_RXF_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$43974656, %edx                 ## imm = 0x29F0000
	callq	_AT_WRITE_REG
	movq	_REG_SRAM_RFD0_INFO@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$46072480, %edx                 ## imm = 0x2BF02A0
	callq	_AT_WRITE_REG
	movq	_REG_SRAM_TXF_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$62849728, %edx                 ## imm = 0x3BF02C0
	callq	_AT_WRITE_REG
	movq	_REG_SRAM_TRD_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$64947136, %edx                 ## imm = 0x3DF03C0
	callq	_AT_WRITE_REG
	movq	_REG_TXF_WATER_MARK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_AT_WRITE_REG
	movq	_REG_RXD_DMA_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_AT_WRITE_REG
LBB0_2:
	movq	_REG_LOAD_PTR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_AT_WRITE_REG                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_REG_TX_BASE_ADDR_HI,4,2        ## @REG_TX_BASE_ADDR_HI
	.comm	_atl1c_trans_normal,8,3         ## @atl1c_trans_normal
	.comm	_AT_DMA_HI_ADDR_MASK,4,2        ## @AT_DMA_HI_ADDR_MASK
	.comm	_REG_TPD_PRI0_ADDR_LO,4,2       ## @REG_TPD_PRI0_ADDR_LO
	.comm	_AT_DMA_LO_ADDR_MASK,4,2        ## @AT_DMA_LO_ADDR_MASK
	.comm	_REG_TPD_PRI1_ADDR_LO,4,2       ## @REG_TPD_PRI1_ADDR_LO
	.comm	_atl1c_trans_high,8,3           ## @atl1c_trans_high
	.comm	_REG_TPD_RING_SIZE,4,2          ## @REG_TPD_RING_SIZE
	.comm	_TPD_RING_SIZE_MASK,4,2         ## @TPD_RING_SIZE_MASK
	.comm	_REG_RX_BASE_ADDR_HI,4,2        ## @REG_RX_BASE_ADDR_HI
	.comm	_REG_RFD0_HEAD_ADDR_LO,4,2      ## @REG_RFD0_HEAD_ADDR_LO
	.comm	_REG_RFD_RING_SIZE,4,2          ## @REG_RFD_RING_SIZE
	.comm	_RFD_RING_SIZE_MASK,4,2         ## @RFD_RING_SIZE_MASK
	.comm	_REG_RX_BUF_SIZE,4,2            ## @REG_RX_BUF_SIZE
	.comm	_RX_BUF_SIZE_MASK,4,2           ## @RX_BUF_SIZE_MASK
	.comm	_REG_RRD0_HEAD_ADDR_LO,4,2      ## @REG_RRD0_HEAD_ADDR_LO
	.comm	_REG_RRD_RING_SIZE,4,2          ## @REG_RRD_RING_SIZE
	.comm	_RRD_RING_SIZE_MASK,4,2         ## @RRD_RING_SIZE_MASK
	.comm	_athr_l2c_b,8,3                 ## @athr_l2c_b
	.comm	_REG_SRAM_RXF_LEN,4,2           ## @REG_SRAM_RXF_LEN
	.comm	_REG_SRAM_TXF_LEN,4,2           ## @REG_SRAM_TXF_LEN
	.comm	_REG_SRAM_RXF_ADDR,4,2          ## @REG_SRAM_RXF_ADDR
	.comm	_REG_SRAM_RFD0_INFO,4,2         ## @REG_SRAM_RFD0_INFO
	.comm	_REG_SRAM_TXF_ADDR,4,2          ## @REG_SRAM_TXF_ADDR
	.comm	_REG_SRAM_TRD_ADDR,4,2          ## @REG_SRAM_TRD_ADDR
	.comm	_REG_TXF_WATER_MARK,4,2         ## @REG_TXF_WATER_MARK
	.comm	_REG_RXD_DMA_CTRL,4,2           ## @REG_RXD_DMA_CTRL
	.comm	_REG_LOAD_PTR,4,2               ## @REG_LOAD_PTR
	.no_dead_strip	_atl1c_configure_des_ring
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function atl1c_configure_des_ring
_atl1c_configure_des_ring:              ; @atl1c_configure_des_ring
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x0
	add	x19, x0, #32
	ldr	x22, [x0, #8]
Lloh0:
	adrp	x8, _REG_TX_BASE_ADDR_HI@GOTPAGE
Lloh1:
	ldr	x8, [x8, _REG_TX_BASE_ADDR_HI@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_AT_WRITE_REG
Lloh3:
	adrp	x8, _REG_TPD_PRI0_ADDR_LO@GOTPAGE
Lloh4:
	ldr	x8, [x8, _REG_TPD_PRI0_ADDR_LO@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
Lloh6:
	adrp	x8, _atl1c_trans_normal@GOTPAGE
Lloh7:
	ldr	x8, [x8, _atl1c_trans_normal@GOTPAGEOFF]
Lloh8:
	ldr	x8, [x8]
	lsl	x8, x8, #3
	ldr	w8, [x22, x8]
Lloh9:
	adrp	x21, _AT_DMA_LO_ADDR_MASK@GOTPAGE
Lloh10:
	ldr	x21, [x21, _AT_DMA_LO_ADDR_MASK@GOTPAGEOFF]
	ldr	w9, [x21]
	and	w2, w9, w8
	mov	x0, x19
	bl	_AT_WRITE_REG
Lloh11:
	adrp	x8, _REG_TPD_PRI1_ADDR_LO@GOTPAGE
Lloh12:
	ldr	x8, [x8, _REG_TPD_PRI1_ADDR_LO@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
Lloh14:
	adrp	x8, _atl1c_trans_high@GOTPAGE
Lloh15:
	ldr	x8, [x8, _atl1c_trans_high@GOTPAGEOFF]
Lloh16:
	ldr	x8, [x8]
	lsl	x8, x8, #3
	ldr	w8, [x22, x8]
	ldr	w9, [x21]
	and	w2, w9, w8
	mov	x0, x19
	bl	_AT_WRITE_REG
Lloh17:
	adrp	x8, _REG_TPD_RING_SIZE@GOTPAGE
Lloh18:
	ldr	x8, [x8, _REG_TPD_RING_SIZE@GOTPAGEOFF]
Lloh19:
	ldr	w1, [x8]
	ldr	w8, [x22, #4]
Lloh20:
	adrp	x9, _TPD_RING_SIZE_MASK@GOTPAGE
Lloh21:
	ldr	x9, [x9, _TPD_RING_SIZE_MASK@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	and	w2, w9, w8
	mov	x0, x19
	bl	_AT_WRITE_REG
Lloh23:
	adrp	x8, _REG_RX_BASE_ADDR_HI@GOTPAGE
Lloh24:
	ldr	x8, [x8, _REG_RX_BASE_ADDR_HI@GOTPAGEOFF]
Lloh25:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_AT_WRITE_REG
Lloh26:
	adrp	x8, _REG_RFD0_HEAD_ADDR_LO@GOTPAGE
Lloh27:
	ldr	x8, [x8, _REG_RFD0_HEAD_ADDR_LO@GOTPAGEOFF]
Lloh28:
	ldr	w1, [x8]
	ldr	w8, [x20, #24]
	ldr	w9, [x21]
	and	w2, w9, w8
	mov	x0, x19
	bl	_AT_WRITE_REG
Lloh29:
	adrp	x8, _REG_RFD_RING_SIZE@GOTPAGE
Lloh30:
	ldr	x8, [x8, _REG_RFD_RING_SIZE@GOTPAGEOFF]
Lloh31:
	ldr	w1, [x8]
	ldr	w8, [x20, #28]
Lloh32:
	adrp	x9, _RFD_RING_SIZE_MASK@GOTPAGE
Lloh33:
	ldr	x9, [x9, _RFD_RING_SIZE_MASK@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	and	w2, w9, w8
	mov	x0, x19
	bl	_AT_WRITE_REG
Lloh35:
	adrp	x8, _REG_RX_BUF_SIZE@GOTPAGE
Lloh36:
	ldr	x8, [x8, _REG_RX_BUF_SIZE@GOTPAGEOFF]
Lloh37:
	ldr	w1, [x8]
	ldr	w8, [x20]
Lloh38:
	adrp	x9, _RX_BUF_SIZE_MASK@GOTPAGE
Lloh39:
	ldr	x9, [x9, _RX_BUF_SIZE_MASK@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
	and	w2, w9, w8
	mov	x0, x19
	bl	_AT_WRITE_REG
Lloh41:
	adrp	x8, _REG_RRD0_HEAD_ADDR_LO@GOTPAGE
Lloh42:
	ldr	x8, [x8, _REG_RRD0_HEAD_ADDR_LO@GOTPAGEOFF]
Lloh43:
	ldr	w1, [x8]
	ldr	w8, [x20, #16]
	ldr	w9, [x21]
	and	w2, w9, w8
	mov	x0, x19
	bl	_AT_WRITE_REG
Lloh44:
	adrp	x8, _REG_RRD_RING_SIZE@GOTPAGE
Lloh45:
	ldr	x8, [x8, _REG_RRD_RING_SIZE@GOTPAGEOFF]
Lloh46:
	ldr	w1, [x8]
	ldr	w8, [x20, #20]
Lloh47:
	adrp	x9, _RRD_RING_SIZE_MASK@GOTPAGE
Lloh48:
	ldr	x9, [x9, _RRD_RING_SIZE_MASK@GOTPAGEOFF]
Lloh49:
	ldr	w9, [x9]
	and	w2, w9, w8
	mov	x0, x19
	bl	_AT_WRITE_REG
	ldr	x8, [x20, #32]
Lloh50:
	adrp	x9, _athr_l2c_b@GOTPAGE
Lloh51:
	ldr	x9, [x9, _athr_l2c_b@GOTPAGEOFF]
Lloh52:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_2
; %bb.1:
Lloh53:
	adrp	x8, _REG_SRAM_RXF_LEN@GOTPAGE
Lloh54:
	ldr	x8, [x8, _REG_SRAM_RXF_LEN@GOTPAGEOFF]
Lloh55:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #672
	bl	_AT_WRITE_REG
Lloh56:
	adrp	x8, _REG_SRAM_TXF_LEN@GOTPAGE
Lloh57:
	ldr	x8, [x8, _REG_SRAM_TXF_LEN@GOTPAGEOFF]
Lloh58:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #256
	bl	_AT_WRITE_REG
Lloh59:
	adrp	x8, _REG_SRAM_RXF_ADDR@GOTPAGE
Lloh60:
	ldr	x8, [x8, _REG_SRAM_RXF_ADDR@GOTPAGEOFF]
Lloh61:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #43974656
	bl	_AT_WRITE_REG
Lloh62:
	adrp	x8, _REG_SRAM_RFD0_INFO@GOTPAGE
Lloh63:
	ldr	x8, [x8, _REG_SRAM_RFD0_INFO@GOTPAGEOFF]
Lloh64:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #672
	movk	w2, #703, lsl #16
	bl	_AT_WRITE_REG
Lloh65:
	adrp	x8, _REG_SRAM_TXF_ADDR@GOTPAGE
Lloh66:
	ldr	x8, [x8, _REG_SRAM_TXF_ADDR@GOTPAGEOFF]
Lloh67:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #704
	movk	w2, #959, lsl #16
	bl	_AT_WRITE_REG
Lloh68:
	adrp	x8, _REG_SRAM_TRD_ADDR@GOTPAGE
Lloh69:
	ldr	x8, [x8, _REG_SRAM_TRD_ADDR@GOTPAGEOFF]
Lloh70:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #960
	movk	w2, #991, lsl #16
	bl	_AT_WRITE_REG
Lloh71:
	adrp	x8, _REG_TXF_WATER_MARK@GOTPAGE
Lloh72:
	ldr	x8, [x8, _REG_TXF_WATER_MARK@GOTPAGEOFF]
Lloh73:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_AT_WRITE_REG
Lloh74:
	adrp	x8, _REG_RXD_DMA_CTRL@GOTPAGE
Lloh75:
	ldr	x8, [x8, _REG_RXD_DMA_CTRL@GOTPAGEOFF]
Lloh76:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_AT_WRITE_REG
LBB0_2:
Lloh77:
	adrp	x8, _REG_LOAD_PTR@GOTPAGE
Lloh78:
	ldr	x8, [x8, _REG_LOAD_PTR@GOTPAGEOFF]
Lloh79:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_AT_WRITE_REG
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.cfi_endproc
                                        ; -- End function
	.comm	_REG_TX_BASE_ADDR_HI,4,2        ; @REG_TX_BASE_ADDR_HI
	.comm	_atl1c_trans_normal,8,3         ; @atl1c_trans_normal
	.comm	_AT_DMA_HI_ADDR_MASK,4,2        ; @AT_DMA_HI_ADDR_MASK
	.comm	_REG_TPD_PRI0_ADDR_LO,4,2       ; @REG_TPD_PRI0_ADDR_LO
	.comm	_AT_DMA_LO_ADDR_MASK,4,2        ; @AT_DMA_LO_ADDR_MASK
	.comm	_REG_TPD_PRI1_ADDR_LO,4,2       ; @REG_TPD_PRI1_ADDR_LO
	.comm	_atl1c_trans_high,8,3           ; @atl1c_trans_high
	.comm	_REG_TPD_RING_SIZE,4,2          ; @REG_TPD_RING_SIZE
	.comm	_TPD_RING_SIZE_MASK,4,2         ; @TPD_RING_SIZE_MASK
	.comm	_REG_RX_BASE_ADDR_HI,4,2        ; @REG_RX_BASE_ADDR_HI
	.comm	_REG_RFD0_HEAD_ADDR_LO,4,2      ; @REG_RFD0_HEAD_ADDR_LO
	.comm	_REG_RFD_RING_SIZE,4,2          ; @REG_RFD_RING_SIZE
	.comm	_RFD_RING_SIZE_MASK,4,2         ; @RFD_RING_SIZE_MASK
	.comm	_REG_RX_BUF_SIZE,4,2            ; @REG_RX_BUF_SIZE
	.comm	_RX_BUF_SIZE_MASK,4,2           ; @RX_BUF_SIZE_MASK
	.comm	_REG_RRD0_HEAD_ADDR_LO,4,2      ; @REG_RRD0_HEAD_ADDR_LO
	.comm	_REG_RRD_RING_SIZE,4,2          ; @REG_RRD_RING_SIZE
	.comm	_RRD_RING_SIZE_MASK,4,2         ; @RRD_RING_SIZE_MASK
	.comm	_athr_l2c_b,8,3                 ; @athr_l2c_b
	.comm	_REG_SRAM_RXF_LEN,4,2           ; @REG_SRAM_RXF_LEN
	.comm	_REG_SRAM_TXF_LEN,4,2           ; @REG_SRAM_TXF_LEN
	.comm	_REG_SRAM_RXF_ADDR,4,2          ; @REG_SRAM_RXF_ADDR
	.comm	_REG_SRAM_RFD0_INFO,4,2         ; @REG_SRAM_RFD0_INFO
	.comm	_REG_SRAM_TXF_ADDR,4,2          ; @REG_SRAM_TXF_ADDR
	.comm	_REG_SRAM_TRD_ADDR,4,2          ; @REG_SRAM_TRD_ADDR
	.comm	_REG_TXF_WATER_MARK,4,2         ; @REG_TXF_WATER_MARK
	.comm	_REG_RXD_DMA_CTRL,4,2           ; @REG_RXD_DMA_CTRL
	.comm	_REG_LOAD_PTR,4,2               ; @REG_LOAD_PTR
	.no_dead_strip	_atl1c_configure_des_ring
.subsections_via_symbols
