	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_octeon_mem_access_ok           ## -- Begin function octeon_mem_access_ok
	.p2align	4, 0x90
_octeon_mem_access_ok:                  ## @octeon_mem_access_ok
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %r14
	callq	_OCTEON_CN23XX_PF
	testq	%rax, %rax
	movq	_CN23XX_LMC0_RESET_CTL@GOTPCREL(%rip), %rax
	cmoveq	_CN6XXX_LMC0_RESET_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_CN23XX_LMC0_RESET_CTL_DDR3RST_MASK@GOTPCREL(%rip), %rbx
	cmoveq	_CN6XXX_LMC0_RESET_CTL_DDR3RST_MASK@GOTPCREL(%rip), %rbx
	movq	%r14, %rdi
	callq	_lio_pci_readq
	xorl	%ecx, %ecx
	testl	%eax, (%rbx)
	sete	%cl
	movl	%ecx, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CN23XX_LMC0_RESET_CTL,4,2      ## @CN23XX_LMC0_RESET_CTL
	.comm	_CN23XX_LMC0_RESET_CTL_DDR3RST_MASK,4,2 ## @CN23XX_LMC0_RESET_CTL_DDR3RST_MASK
	.comm	_CN6XXX_LMC0_RESET_CTL,4,2      ## @CN6XXX_LMC0_RESET_CTL
	.comm	_CN6XXX_LMC0_RESET_CTL_DDR3RST_MASK,4,2 ## @CN6XXX_LMC0_RESET_CTL_DDR3RST_MASK
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_octeon_mem_access_ok           ; -- Begin function octeon_mem_access_ok
	.p2align	2
_octeon_mem_access_ok:                  ; @octeon_mem_access_ok
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_OCTEON_CN23XX_PF
Lloh0:
	adrp	x8, _CN6XXX_LMC0_RESET_CTL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _CN6XXX_LMC0_RESET_CTL@GOTPAGEOFF]
Lloh2:
	adrp	x9, _CN23XX_LMC0_RESET_CTL@GOTPAGE
Lloh3:
	ldr	x9, [x9, _CN23XX_LMC0_RESET_CTL@GOTPAGEOFF]
	cmp	x0, #0
	csel	x8, x8, x9, eq
	ldr	w1, [x8]
Lloh4:
	adrp	x8, _CN6XXX_LMC0_RESET_CTL_DDR3RST_MASK@GOTPAGE
Lloh5:
	ldr	x8, [x8, _CN6XXX_LMC0_RESET_CTL_DDR3RST_MASK@GOTPAGEOFF]
Lloh6:
	adrp	x9, _CN23XX_LMC0_RESET_CTL_DDR3RST_MASK@GOTPAGE
Lloh7:
	ldr	x9, [x9, _CN23XX_LMC0_RESET_CTL_DDR3RST_MASK@GOTPAGEOFF]
	csel	x20, x8, x9, eq
	mov	x0, x19
	bl	_lio_pci_readq
	ldr	w8, [x20]
	tst	w8, w0
	cset	w0, eq
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_CN23XX_LMC0_RESET_CTL,4,2      ; @CN23XX_LMC0_RESET_CTL
	.comm	_CN23XX_LMC0_RESET_CTL_DDR3RST_MASK,4,2 ; @CN23XX_LMC0_RESET_CTL_DDR3RST_MASK
	.comm	_CN6XXX_LMC0_RESET_CTL,4,2      ; @CN6XXX_LMC0_RESET_CTL
	.comm	_CN6XXX_LMC0_RESET_CTL_DDR3RST_MASK,4,2 ; @CN6XXX_LMC0_RESET_CTL_DDR3RST_MASK
.subsections_via_symbols
