	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rts525a_extra_init_hw
_rts525a_extra_init_hw:                 ## @rts525a_extra_init_hw
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	callq	_rts5249_extra_init_hw
	movq	_PCLK_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PCLK_MODE_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%ecx, %edx
	callq	_rtsx_pci_write_register
	movq	_IC_VER_A@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	movl	$21082, %esi                    ## imm = 0x525A
	callq	_is_version
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	_L1SUB_CONFIG2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_L1SUB_AUTO_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%ecx, %edx
	callq	_rtsx_pci_write_register
	movq	_RREF_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_RREF_VBGSEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_RREF_VBGSEL_1V25@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	callq	_rtsx_pci_write_register
	movq	_LDO_VIO_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_LDO_VIO_TUNE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_LDO_VIO_1V7@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	callq	_rtsx_pci_write_register
	movq	_LDO_DV12S_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_LDO_D12_TUNE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_LDO_D12_TUNE_DF@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	callq	_rtsx_pci_write_register
	movq	_LDO_AV12S_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_LDO_AV12S_TUNE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_LDO_AV12S_TUNE_DF@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	callq	_rtsx_pci_write_register
	movq	_LDO_VCC_CFG0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_LDO_VCC_LMTVTH_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_LDO_VCC_LMTVTH_2A@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	callq	_rtsx_pci_write_register
	movq	_OOBS_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_OOBS_AUTOK_DIS@GOTPCREL(%rip), %rax
	movq	_OOBS_VAL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	%rbx, %rdi
	movl	$137, %ecx
	callq	_rtsx_pci_write_register
LBB0_2:
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PCLK_CTL,4,2                   ## @PCLK_CTL
	.comm	_PCLK_MODE_SEL,4,2              ## @PCLK_MODE_SEL
	.comm	_IC_VER_A,4,2                   ## @IC_VER_A
	.comm	_L1SUB_CONFIG2,4,2              ## @L1SUB_CONFIG2
	.comm	_L1SUB_AUTO_CFG,4,2             ## @L1SUB_AUTO_CFG
	.comm	_RREF_CFG,4,2                   ## @RREF_CFG
	.comm	_RREF_VBGSEL_MASK,4,2           ## @RREF_VBGSEL_MASK
	.comm	_RREF_VBGSEL_1V25,4,2           ## @RREF_VBGSEL_1V25
	.comm	_LDO_VIO_CFG,4,2                ## @LDO_VIO_CFG
	.comm	_LDO_VIO_TUNE_MASK,4,2          ## @LDO_VIO_TUNE_MASK
	.comm	_LDO_VIO_1V7,4,2                ## @LDO_VIO_1V7
	.comm	_LDO_DV12S_CFG,4,2              ## @LDO_DV12S_CFG
	.comm	_LDO_D12_TUNE_MASK,4,2          ## @LDO_D12_TUNE_MASK
	.comm	_LDO_D12_TUNE_DF,4,2            ## @LDO_D12_TUNE_DF
	.comm	_LDO_AV12S_CFG,4,2              ## @LDO_AV12S_CFG
	.comm	_LDO_AV12S_TUNE_MASK,4,2        ## @LDO_AV12S_TUNE_MASK
	.comm	_LDO_AV12S_TUNE_DF,4,2          ## @LDO_AV12S_TUNE_DF
	.comm	_LDO_VCC_CFG0,4,2               ## @LDO_VCC_CFG0
	.comm	_LDO_VCC_LMTVTH_MASK,4,2        ## @LDO_VCC_LMTVTH_MASK
	.comm	_LDO_VCC_LMTVTH_2A,4,2          ## @LDO_VCC_LMTVTH_2A
	.comm	_OOBS_CONFIG,4,2                ## @OOBS_CONFIG
	.comm	_OOBS_AUTOK_DIS,4,2             ## @OOBS_AUTOK_DIS
	.comm	_OOBS_VAL_MASK,4,2              ## @OOBS_VAL_MASK
	.no_dead_strip	_rts525a_extra_init_hw
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rts525a_extra_init_hw
_rts525a_extra_init_hw:                 ; @rts525a_extra_init_hw
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_rts5249_extra_init_hw
Lloh0:
	adrp	x8, _PCLK_CTL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCLK_CTL@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
Lloh3:
	adrp	x8, _PCLK_MODE_SEL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCLK_MODE_SEL@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x3, x2
	bl	_rtsx_pci_write_register
Lloh6:
	adrp	x8, _IC_VER_A@GOTPAGE
Lloh7:
	ldr	x8, [x8, _IC_VER_A@GOTPAGEOFF]
Lloh8:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w1, #21082
	bl	_is_version
	cbz	x0, LBB0_2
; %bb.1:
Lloh9:
	adrp	x8, _L1SUB_CONFIG2@GOTPAGE
Lloh10:
	ldr	x8, [x8, _L1SUB_CONFIG2@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
Lloh12:
	adrp	x8, _L1SUB_AUTO_CFG@GOTPAGE
Lloh13:
	ldr	x8, [x8, _L1SUB_AUTO_CFG@GOTPAGEOFF]
Lloh14:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x3, x2
	bl	_rtsx_pci_write_register
Lloh15:
	adrp	x8, _RREF_CFG@GOTPAGE
Lloh16:
	ldr	x8, [x8, _RREF_CFG@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
Lloh18:
	adrp	x8, _RREF_VBGSEL_MASK@GOTPAGE
Lloh19:
	ldr	x8, [x8, _RREF_VBGSEL_MASK@GOTPAGEOFF]
Lloh20:
	ldr	w2, [x8]
Lloh21:
	adrp	x8, _RREF_VBGSEL_1V25@GOTPAGE
Lloh22:
	ldr	x8, [x8, _RREF_VBGSEL_1V25@GOTPAGEOFF]
Lloh23:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_rtsx_pci_write_register
Lloh24:
	adrp	x8, _LDO_VIO_CFG@GOTPAGE
Lloh25:
	ldr	x8, [x8, _LDO_VIO_CFG@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
Lloh27:
	adrp	x8, _LDO_VIO_TUNE_MASK@GOTPAGE
Lloh28:
	ldr	x8, [x8, _LDO_VIO_TUNE_MASK@GOTPAGEOFF]
Lloh29:
	ldr	w2, [x8]
Lloh30:
	adrp	x8, _LDO_VIO_1V7@GOTPAGE
Lloh31:
	ldr	x8, [x8, _LDO_VIO_1V7@GOTPAGEOFF]
Lloh32:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_rtsx_pci_write_register
Lloh33:
	adrp	x8, _LDO_DV12S_CFG@GOTPAGE
Lloh34:
	ldr	x8, [x8, _LDO_DV12S_CFG@GOTPAGEOFF]
Lloh35:
	ldr	w1, [x8]
Lloh36:
	adrp	x8, _LDO_D12_TUNE_MASK@GOTPAGE
Lloh37:
	ldr	x8, [x8, _LDO_D12_TUNE_MASK@GOTPAGEOFF]
Lloh38:
	ldr	w2, [x8]
Lloh39:
	adrp	x8, _LDO_D12_TUNE_DF@GOTPAGE
Lloh40:
	ldr	x8, [x8, _LDO_D12_TUNE_DF@GOTPAGEOFF]
Lloh41:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_rtsx_pci_write_register
Lloh42:
	adrp	x8, _LDO_AV12S_CFG@GOTPAGE
Lloh43:
	ldr	x8, [x8, _LDO_AV12S_CFG@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x8]
Lloh45:
	adrp	x8, _LDO_AV12S_TUNE_MASK@GOTPAGE
Lloh46:
	ldr	x8, [x8, _LDO_AV12S_TUNE_MASK@GOTPAGEOFF]
Lloh47:
	ldr	w2, [x8]
Lloh48:
	adrp	x8, _LDO_AV12S_TUNE_DF@GOTPAGE
Lloh49:
	ldr	x8, [x8, _LDO_AV12S_TUNE_DF@GOTPAGEOFF]
Lloh50:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_rtsx_pci_write_register
Lloh51:
	adrp	x8, _LDO_VCC_CFG0@GOTPAGE
Lloh52:
	ldr	x8, [x8, _LDO_VCC_CFG0@GOTPAGEOFF]
Lloh53:
	ldr	w1, [x8]
Lloh54:
	adrp	x8, _LDO_VCC_LMTVTH_MASK@GOTPAGE
Lloh55:
	ldr	x8, [x8, _LDO_VCC_LMTVTH_MASK@GOTPAGEOFF]
Lloh56:
	ldr	w2, [x8]
Lloh57:
	adrp	x8, _LDO_VCC_LMTVTH_2A@GOTPAGE
Lloh58:
	ldr	x8, [x8, _LDO_VCC_LMTVTH_2A@GOTPAGEOFF]
Lloh59:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_rtsx_pci_write_register
Lloh60:
	adrp	x8, _OOBS_CONFIG@GOTPAGE
Lloh61:
	ldr	x8, [x8, _OOBS_CONFIG@GOTPAGEOFF]
Lloh62:
	adrp	x9, _OOBS_AUTOK_DIS@GOTPAGE
Lloh63:
	ldr	x9, [x9, _OOBS_AUTOK_DIS@GOTPAGEOFF]
Lloh64:
	ldr	w1, [x8]
Lloh65:
	ldr	w8, [x9]
Lloh66:
	adrp	x9, _OOBS_VAL_MASK@GOTPAGE
Lloh67:
	ldr	x9, [x9, _OOBS_VAL_MASK@GOTPAGEOFF]
Lloh68:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x0, x19
	mov	w3, #137
	bl	_rtsx_pci_write_register
LBB0_2:
	mov	w0, #0
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh64
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.cfi_endproc
                                        ; -- End function
	.comm	_PCLK_CTL,4,2                   ; @PCLK_CTL
	.comm	_PCLK_MODE_SEL,4,2              ; @PCLK_MODE_SEL
	.comm	_IC_VER_A,4,2                   ; @IC_VER_A
	.comm	_L1SUB_CONFIG2,4,2              ; @L1SUB_CONFIG2
	.comm	_L1SUB_AUTO_CFG,4,2             ; @L1SUB_AUTO_CFG
	.comm	_RREF_CFG,4,2                   ; @RREF_CFG
	.comm	_RREF_VBGSEL_MASK,4,2           ; @RREF_VBGSEL_MASK
	.comm	_RREF_VBGSEL_1V25,4,2           ; @RREF_VBGSEL_1V25
	.comm	_LDO_VIO_CFG,4,2                ; @LDO_VIO_CFG
	.comm	_LDO_VIO_TUNE_MASK,4,2          ; @LDO_VIO_TUNE_MASK
	.comm	_LDO_VIO_1V7,4,2                ; @LDO_VIO_1V7
	.comm	_LDO_DV12S_CFG,4,2              ; @LDO_DV12S_CFG
	.comm	_LDO_D12_TUNE_MASK,4,2          ; @LDO_D12_TUNE_MASK
	.comm	_LDO_D12_TUNE_DF,4,2            ; @LDO_D12_TUNE_DF
	.comm	_LDO_AV12S_CFG,4,2              ; @LDO_AV12S_CFG
	.comm	_LDO_AV12S_TUNE_MASK,4,2        ; @LDO_AV12S_TUNE_MASK
	.comm	_LDO_AV12S_TUNE_DF,4,2          ; @LDO_AV12S_TUNE_DF
	.comm	_LDO_VCC_CFG0,4,2               ; @LDO_VCC_CFG0
	.comm	_LDO_VCC_LMTVTH_MASK,4,2        ; @LDO_VCC_LMTVTH_MASK
	.comm	_LDO_VCC_LMTVTH_2A,4,2          ; @LDO_VCC_LMTVTH_2A
	.comm	_OOBS_CONFIG,4,2                ; @OOBS_CONFIG
	.comm	_OOBS_AUTOK_DIS,4,2             ; @OOBS_AUTOK_DIS
	.comm	_OOBS_VAL_MASK,4,2              ; @OOBS_VAL_MASK
	.no_dead_strip	_rts525a_extra_init_hw
.subsections_via_symbols
