	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_cxl_invalidate_all_psl8        ## -- Begin function cxl_invalidate_all_psl8
	.p2align	4, 0x90
_cxl_invalidate_all_psl8:               ## @cxl_invalidate_all_psl8
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	_jiffies@GOTPCREL(%rip), %rdx
	movq	_HZ@GOTPCREL(%rip), %rax
	movq	_CXL_TIMEOUT@GOTPCREL(%rip), %rcx
	movq	(%rcx), %r14
	imulq	(%rax), %r14
	addq	(%rdx), %r14
	leaq	L_.str(%rip), %rdi
	callq	_pr_devel
	movq	_CXL_PSL_AFUSEL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_CXL_PSL_AFUSEL_A@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_cxl_p1_write
	movq	_CXL_PSL_TLBIA@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_CXL_TLB_SLB_IQ_ALL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_cxl_p1_write
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_cxl_p1_read
	movq	_CXL_TLB_SLB_P@GOTPCREL(%rip), %r13
	testl	%eax, (%r13)
	je	LBB0_9
## %bb.1:
	movq	_cxl_ops@GOTPCREL(%rip), %r12
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	_jiffies@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movq	%r14, %rsi
	callq	_time_after_eq
	testq	%rax, %rax
	jne	LBB0_3
## %bb.5:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	(%r12), %rax
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	*(%rax)
	testl	%eax, %eax
	je	LBB0_6
## %bb.8:                               ##   in Loop: Header=BB0_2 Depth=1
	xorl	%eax, %eax
	callq	_cpu_relax
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_cxl_p1_read
	testl	%eax, (%r13)
	jne	LBB0_2
LBB0_9:
	movq	_CXL_PSL_SLBIA@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	_CXL_TLB_SLB_IQ_ALL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_cxl_p1_write
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_cxl_p1_read
	testl	%eax, (%r13)
	je	LBB0_10
## %bb.11:
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_12:                                ## =>This Inner Loop Header: Depth=1
	movq	_jiffies@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	movq	%r14, %rsi
	callq	_time_after_eq
	testq	%rax, %rax
	jne	LBB0_13
## %bb.14:                              ##   in Loop: Header=BB0_12 Depth=1
	movq	_cxl_ops@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	*(%rax)
	testl	%eax, %eax
	je	LBB0_6
## %bb.15:                              ##   in Loop: Header=BB0_12 Depth=1
	xorl	%eax, %eax
	callq	_cpu_relax
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_cxl_p1_read
	testl	%eax, (%r13)
	jne	LBB0_12
	jmp	LBB0_16
LBB0_6:
	movq	_EIO@GOTPCREL(%rip), %rax
	jmp	LBB0_7
LBB0_3:
	leaq	L_.str.1(%rip), %rsi
	jmp	LBB0_4
LBB0_10:
	xorl	%ebx, %ebx
	jmp	LBB0_16
LBB0_13:
	leaq	L_.str.2(%rip), %rsi
LBB0_4:
	movq	%r15, %rdi
	callq	_dev_warn
	movq	_EBUSY@GOTPCREL(%rip), %rax
LBB0_7:
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
LBB0_16:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_jiffies,8,3                    ## @jiffies
	.comm	_HZ,8,3                         ## @HZ
	.comm	_CXL_TIMEOUT,8,3                ## @CXL_TIMEOUT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"CXL adapter wide TLBIA & SLBIA\n"

	.comm	_CXL_PSL_AFUSEL,4,2             ## @CXL_PSL_AFUSEL
	.comm	_CXL_PSL_AFUSEL_A,4,2           ## @CXL_PSL_AFUSEL_A
	.comm	_CXL_PSL_TLBIA,4,2              ## @CXL_PSL_TLBIA
	.comm	_CXL_TLB_SLB_IQ_ALL,4,2         ## @CXL_TLB_SLB_IQ_ALL
	.comm	_CXL_TLB_SLB_P,4,2              ## @CXL_TLB_SLB_P
L_.str.1:                               ## @.str.1
	.asciz	"WARNING: CXL adapter wide TLBIA timed out!\n"

	.comm	_EBUSY,4,2                      ## @EBUSY
	.comm	_cxl_ops,8,3                    ## @cxl_ops
	.comm	_EIO,4,2                        ## @EIO
	.comm	_CXL_PSL_SLBIA,4,2              ## @CXL_PSL_SLBIA
L_.str.2:                               ## @.str.2
	.asciz	"WARNING: CXL adapter wide SLBIA timed out!\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_cxl_invalidate_all_psl8        ; -- Begin function cxl_invalidate_all_psl8
	.p2align	2
_cxl_invalidate_all_psl8:               ; @cxl_invalidate_all_psl8
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
Lloh0:
	adrp	x21, _jiffies@GOTPAGE
Lloh1:
	ldr	x21, [x21, _jiffies@GOTPAGEOFF]
Lloh2:
	adrp	x8, _HZ@GOTPAGE
Lloh3:
	ldr	x8, [x8, _HZ@GOTPAGEOFF]
	ldr	x9, [x21]
Lloh4:
	ldr	x8, [x8]
Lloh5:
	adrp	x10, _CXL_TIMEOUT@GOTPAGE
Lloh6:
	ldr	x10, [x10, _CXL_TIMEOUT@GOTPAGEOFF]
Lloh7:
	ldr	x10, [x10]
	madd	x20, x10, x8, x9
Lloh8:
	adrp	x0, l_.str@PAGE
Lloh9:
	add	x0, x0, l_.str@PAGEOFF
	bl	_pr_devel
Lloh10:
	adrp	x8, _CXL_PSL_AFUSEL@GOTPAGE
Lloh11:
	ldr	x8, [x8, _CXL_PSL_AFUSEL@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
Lloh13:
	adrp	x8, _CXL_PSL_AFUSEL_A@GOTPAGE
Lloh14:
	ldr	x8, [x8, _CXL_PSL_AFUSEL_A@GOTPAGEOFF]
Lloh15:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_cxl_p1_write
Lloh16:
	adrp	x24, _CXL_PSL_TLBIA@GOTPAGE
Lloh17:
	ldr	x24, [x24, _CXL_PSL_TLBIA@GOTPAGEOFF]
	ldr	w1, [x24]
Lloh18:
	adrp	x23, _CXL_TLB_SLB_IQ_ALL@GOTPAGE
Lloh19:
	ldr	x23, [x23, _CXL_TLB_SLB_IQ_ALL@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	x0, x19
	bl	_cxl_p1_write
	ldr	w1, [x24]
	mov	x0, x19
	bl	_cxl_p1_read
Lloh20:
	adrp	x22, _CXL_TLB_SLB_P@GOTPAGE
Lloh21:
	ldr	x22, [x22, _CXL_TLB_SLB_P@GOTPAGEOFF]
	ldr	w8, [x22]
	tst	w8, w0
	b.eq	LBB0_5
; %bb.1:
Lloh22:
	adrp	x25, _cxl_ops@GOTPAGE
Lloh23:
	ldr	x25, [x25, _cxl_ops@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x0, [x21]
	mov	x1, x20
	bl	_time_after_eq
	cbnz	x0, LBB0_12
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	ldr	x8, [x25]
	ldr	x8, [x8]
	mov	x0, x19
	mov	x1, #0
	blr	x8
	cbz	w0, LBB0_11
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	bl	_cpu_relax
	ldr	w1, [x24]
	mov	x0, x19
	bl	_cxl_p1_read
	ldr	w8, [x22]
	tst	w8, w0
	b.ne	LBB0_2
LBB0_5:
Lloh24:
	adrp	x24, _CXL_PSL_SLBIA@GOTPAGE
Lloh25:
	ldr	x24, [x24, _CXL_PSL_SLBIA@GOTPAGEOFF]
	ldr	w1, [x24]
	ldr	w2, [x23]
	mov	x0, x19
	bl	_cxl_p1_write
	ldr	w1, [x24]
	mov	x0, x19
	bl	_cxl_p1_read
	ldr	w8, [x22]
	tst	w8, w0
	b.eq	LBB0_10
; %bb.6:
Lloh26:
	adrp	x23, _cxl_ops@GOTPAGE
Lloh27:
	ldr	x23, [x23, _cxl_ops@GOTPAGEOFF]
LBB0_7:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x0, [x21]
	mov	x1, x20
	bl	_time_after_eq
	cbnz	x0, LBB0_13
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=1
	ldr	x8, [x23]
	ldr	x8, [x8]
	mov	x0, x19
	mov	x1, #0
	blr	x8
	cbz	w0, LBB0_11
; %bb.9:                                ;   in Loop: Header=BB0_7 Depth=1
	bl	_cpu_relax
	ldr	w1, [x24]
	mov	x0, x19
	bl	_cxl_p1_read
	ldr	w8, [x22]
	tst	w8, w0
	b.ne	LBB0_7
LBB0_10:
	mov	w0, #0
	b	LBB0_16
LBB0_11:
Lloh28:
	adrp	x8, _EIO@GOTPAGE
Lloh29:
	ldr	x8, [x8, _EIO@GOTPAGEOFF]
	b	LBB0_15
LBB0_12:
Lloh30:
	adrp	x1, l_.str.1@PAGE
Lloh31:
	add	x1, x1, l_.str.1@PAGEOFF
	b	LBB0_14
LBB0_13:
Lloh32:
	adrp	x1, l_.str.2@PAGE
Lloh33:
	add	x1, x1, l_.str.2@PAGEOFF
LBB0_14:
	mov	x0, x19
	bl	_dev_warn
Lloh34:
	adrp	x8, _EBUSY@GOTPAGE
Lloh35:
	ldr	x8, [x8, _EBUSY@GOTPAGEOFF]
LBB0_15:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_16:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpAdd	Lloh30, Lloh31
	.loh AdrpAdd	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh34, Lloh35
	.cfi_endproc
                                        ; -- End function
	.comm	_jiffies,8,3                    ; @jiffies
	.comm	_HZ,8,3                         ; @HZ
	.comm	_CXL_TIMEOUT,8,3                ; @CXL_TIMEOUT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"CXL adapter wide TLBIA & SLBIA\n"

	.comm	_CXL_PSL_AFUSEL,4,2             ; @CXL_PSL_AFUSEL
	.comm	_CXL_PSL_AFUSEL_A,4,2           ; @CXL_PSL_AFUSEL_A
	.comm	_CXL_PSL_TLBIA,4,2              ; @CXL_PSL_TLBIA
	.comm	_CXL_TLB_SLB_IQ_ALL,4,2         ; @CXL_TLB_SLB_IQ_ALL
	.comm	_CXL_TLB_SLB_P,4,2              ; @CXL_TLB_SLB_P
l_.str.1:                               ; @.str.1
	.asciz	"WARNING: CXL adapter wide TLBIA timed out!\n"

	.comm	_EBUSY,4,2                      ; @EBUSY
	.comm	_cxl_ops,8,3                    ; @cxl_ops
	.comm	_EIO,4,2                        ; @EIO
	.comm	_CXL_PSL_SLBIA,4,2              ; @CXL_PSL_SLBIA
l_.str.2:                               ; @.str.2
	.asciz	"WARNING: CXL adapter wide SLBIA timed out!\n"

.subsections_via_symbols
