	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function sh_veu_configure
_sh_veu_configure:                      ## @sh_veu_configure
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r13
	movq	_VEU_BSRR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$256, %edx                      ## imm = 0x100
	callq	_sh_veu_reg_write
	movl	20(%r13), %r15d
	movl	24(%r13), %r12d
	movl	%r15d, %edi
	movl	$16, %esi
	callq	_ALIGN
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movl	8(%r13), %eax
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movl	12(%r13), %ecx
	movl	16(%r13), %r14d
	movq	%r13, %rdi
	movl	%r15d, %esi
	movl	%ecx, %edx
	callq	_sh_veu_scale_h
	movl	%eax, %r15d
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%r14d, %edx
	movl	%r14d, %ecx
	callq	_sh_veu_scale_v
	movl	%eax, %ebx
	movq	_VEU_SWR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	callq	_sh_veu_reg_write
	movq	_VEU_SSR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	shll	$16, %ebx
	orl	%r15d, %ebx
	movq	%r13, %rdi
	movl	%ebx, %edx
	callq	_sh_veu_reg_write
	movq	_VEU_BSSR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	xorl	%edx, %edx
	callq	_sh_veu_reg_write
	movq	_VEU_EDWR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	-48(%rbp), %edx                 ## 4-byte Reload
	callq	_sh_veu_reg_write
	movq	_VEU_DACR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	xorl	%edx, %edx
	callq	_sh_veu_reg_write
	movq	_VEU_SWPR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$103, %edx
	callq	_sh_veu_reg_write
	movq	_VEU_TRCR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$393222, %edx                   ## imm = 0x60006
	callq	_sh_veu_reg_write
	cmpq	$0, (%r13)
	je	LBB0_1
## %bb.2:
	movq	_VEU_MCR00@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$3269, %edx                     ## imm = 0xCC5
	callq	_sh_veu_reg_write
	movq	_VEU_MCR01@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$2384, %edx                     ## imm = 0x950
	callq	_sh_veu_reg_write
	movq	_VEU_MCR02@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	xorl	%edx, %edx
	callq	_sh_veu_reg_write
	movq	_VEU_MCR10@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$14719, %edx                    ## imm = 0x397F
	callq	_sh_veu_reg_write
	movq	_VEU_MCR11@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$2384, %edx                     ## imm = 0x950
	callq	_sh_veu_reg_write
	movq	_VEU_MCR12@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$15565, %edx                    ## imm = 0x3CCD
	callq	_sh_veu_reg_write
	movq	_VEU_MCR20@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	xorl	%edx, %edx
	callq	_sh_veu_reg_write
	movq	_VEU_MCR21@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$2384, %edx                     ## imm = 0x950
	callq	_sh_veu_reg_write
	movq	_VEU_MCR22@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$4131, %edx                     ## imm = 0x1023
	callq	_sh_veu_reg_write
	movq	_VEU_COFFR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$8388624, %edx                  ## imm = 0x800010
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_sh_veu_reg_write               ## TAILCALL
LBB0_1:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_VEU_BSRR,4,2                   ## @VEU_BSRR
	.comm	_VEU_SWR,4,2                    ## @VEU_SWR
	.comm	_VEU_SSR,4,2                    ## @VEU_SSR
	.comm	_VEU_BSSR,4,2                   ## @VEU_BSSR
	.comm	_VEU_EDWR,4,2                   ## @VEU_EDWR
	.comm	_VEU_DACR,4,2                   ## @VEU_DACR
	.comm	_VEU_SWPR,4,2                   ## @VEU_SWPR
	.comm	_VEU_TRCR,4,2                   ## @VEU_TRCR
	.comm	_VEU_MCR00,4,2                  ## @VEU_MCR00
	.comm	_VEU_MCR01,4,2                  ## @VEU_MCR01
	.comm	_VEU_MCR02,4,2                  ## @VEU_MCR02
	.comm	_VEU_MCR10,4,2                  ## @VEU_MCR10
	.comm	_VEU_MCR11,4,2                  ## @VEU_MCR11
	.comm	_VEU_MCR12,4,2                  ## @VEU_MCR12
	.comm	_VEU_MCR20,4,2                  ## @VEU_MCR20
	.comm	_VEU_MCR21,4,2                  ## @VEU_MCR21
	.comm	_VEU_MCR22,4,2                  ## @VEU_MCR22
	.comm	_VEU_COFFR,4,2                  ## @VEU_COFFR
	.no_dead_strip	_sh_veu_configure
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function sh_veu_configure
_sh_veu_configure:                      ; @sh_veu_configure
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x8, _VEU_BSRR@GOTPAGE
Lloh1:
	ldr	x8, [x8, _VEU_BSRR@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	w2, #256
	bl	_sh_veu_reg_write
	ldp	w20, w21, [x19, #20]
	mov	x0, x20
	mov	w1, #16
	bl	_ALIGN
	mov	x22, x0
	ldp	w2, w23, [x19, #12]
	ldr	w24, [x19, #8]
	mov	x0, x19
	mov	x1, x20
	mov	x3, x2
	bl	_sh_veu_scale_h
	mov	x20, x0
	mov	x0, x19
	mov	x1, x21
	mov	x2, x23
	mov	x3, x23
	bl	_sh_veu_scale_v
	mov	x21, x0
Lloh3:
	adrp	x8, _VEU_SWR@GOTPAGE
Lloh4:
	ldr	x8, [x8, _VEU_SWR@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x22
	bl	_sh_veu_reg_write
Lloh6:
	adrp	x8, _VEU_SSR@GOTPAGE
Lloh7:
	ldr	x8, [x8, _VEU_SSR@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	orr	w2, w20, w21, lsl #16
	mov	x0, x19
	bl	_sh_veu_reg_write
Lloh9:
	adrp	x8, _VEU_BSSR@GOTPAGE
Lloh10:
	ldr	x8, [x8, _VEU_BSSR@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_sh_veu_reg_write
Lloh12:
	adrp	x8, _VEU_EDWR@GOTPAGE
Lloh13:
	ldr	x8, [x8, _VEU_EDWR@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x24
	bl	_sh_veu_reg_write
Lloh15:
	adrp	x8, _VEU_DACR@GOTPAGE
Lloh16:
	ldr	x8, [x8, _VEU_DACR@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_sh_veu_reg_write
Lloh18:
	adrp	x8, _VEU_SWPR@GOTPAGE
Lloh19:
	ldr	x8, [x8, _VEU_SWPR@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #103
	bl	_sh_veu_reg_write
Lloh21:
	adrp	x8, _VEU_TRCR@GOTPAGE
Lloh22:
	ldr	x8, [x8, _VEU_TRCR@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #393222
	bl	_sh_veu_reg_write
	ldr	x8, [x19]
	cbz	x8, LBB0_2
; %bb.1:
Lloh24:
	adrp	x8, _VEU_MCR00@GOTPAGE
Lloh25:
	ldr	x8, [x8, _VEU_MCR00@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #3269
	bl	_sh_veu_reg_write
Lloh27:
	adrp	x8, _VEU_MCR01@GOTPAGE
Lloh28:
	ldr	x8, [x8, _VEU_MCR01@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #2384
	bl	_sh_veu_reg_write
Lloh30:
	adrp	x8, _VEU_MCR02@GOTPAGE
Lloh31:
	ldr	x8, [x8, _VEU_MCR02@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_sh_veu_reg_write
Lloh33:
	adrp	x8, _VEU_MCR10@GOTPAGE
Lloh34:
	ldr	x8, [x8, _VEU_MCR10@GOTPAGEOFF]
Lloh35:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #14719
	bl	_sh_veu_reg_write
Lloh36:
	adrp	x8, _VEU_MCR11@GOTPAGE
Lloh37:
	ldr	x8, [x8, _VEU_MCR11@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #2384
	bl	_sh_veu_reg_write
Lloh39:
	adrp	x8, _VEU_MCR12@GOTPAGE
Lloh40:
	ldr	x8, [x8, _VEU_MCR12@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #15565
	bl	_sh_veu_reg_write
Lloh42:
	adrp	x8, _VEU_MCR20@GOTPAGE
Lloh43:
	ldr	x8, [x8, _VEU_MCR20@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_sh_veu_reg_write
Lloh45:
	adrp	x8, _VEU_MCR21@GOTPAGE
Lloh46:
	ldr	x8, [x8, _VEU_MCR21@GOTPAGEOFF]
Lloh47:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #2384
	bl	_sh_veu_reg_write
Lloh48:
	adrp	x8, _VEU_MCR22@GOTPAGE
Lloh49:
	ldr	x8, [x8, _VEU_MCR22@GOTPAGEOFF]
Lloh50:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #4131
	bl	_sh_veu_reg_write
Lloh51:
	adrp	x8, _VEU_COFFR@GOTPAGE
Lloh52:
	ldr	x8, [x8, _VEU_COFFR@GOTPAGEOFF]
Lloh53:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #16
	movk	w2, #128, lsl #16
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_sh_veu_reg_write
LBB0_2:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.cfi_endproc
                                        ; -- End function
	.comm	_VEU_BSRR,4,2                   ; @VEU_BSRR
	.comm	_VEU_SWR,4,2                    ; @VEU_SWR
	.comm	_VEU_SSR,4,2                    ; @VEU_SSR
	.comm	_VEU_BSSR,4,2                   ; @VEU_BSSR
	.comm	_VEU_EDWR,4,2                   ; @VEU_EDWR
	.comm	_VEU_DACR,4,2                   ; @VEU_DACR
	.comm	_VEU_SWPR,4,2                   ; @VEU_SWPR
	.comm	_VEU_TRCR,4,2                   ; @VEU_TRCR
	.comm	_VEU_MCR00,4,2                  ; @VEU_MCR00
	.comm	_VEU_MCR01,4,2                  ; @VEU_MCR01
	.comm	_VEU_MCR02,4,2                  ; @VEU_MCR02
	.comm	_VEU_MCR10,4,2                  ; @VEU_MCR10
	.comm	_VEU_MCR11,4,2                  ; @VEU_MCR11
	.comm	_VEU_MCR12,4,2                  ; @VEU_MCR12
	.comm	_VEU_MCR20,4,2                  ; @VEU_MCR20
	.comm	_VEU_MCR21,4,2                  ; @VEU_MCR21
	.comm	_VEU_MCR22,4,2                  ; @VEU_MCR22
	.comm	_VEU_COFFR,4,2                  ; @VEU_COFFR
	.no_dead_strip	_sh_veu_configure
.subsections_via_symbols
