	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_cclock_to_ns                   ## -- Begin function cclock_to_ns
	.p2align	4, 0x90
_cclock_to_ns:                          ## @cclock_to_ns
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	(%rdi), %rax
	movq	_ICODE_FPGA_EMULATION@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_1
## %bb.2:
	movq	_FPGA_CCLOCK_PS@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_1:
	movq	_ASIC_CCLOCK_PS@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %eax
	imull	%esi, %eax
	cltq
	imulq	$274877907, %rax, %rcx          ## imm = 0x10624DD3
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$38, %rcx
	addl	%edx, %ecx
	addl	$-1000, %eax                    ## imm = 0xFC18
	cmpl	$-1999, %eax                    ## imm = 0xF831
	movl	$1, %eax
	cmovbl	%ecx, %eax
	testl	%esi, %esi
	cmovel	%ecx, %eax
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_ICODE_FPGA_EMULATION,8,3       ## @ICODE_FPGA_EMULATION
	.comm	_FPGA_CCLOCK_PS,4,2             ## @FPGA_CCLOCK_PS
	.comm	_ASIC_CCLOCK_PS,4,2             ## @ASIC_CCLOCK_PS
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_cclock_to_ns                   ; -- Begin function cclock_to_ns
	.p2align	2
_cclock_to_ns:                          ; @cclock_to_ns
	.cfi_startproc
; %bb.0:
	ldr	x8, [x0]
Lloh0:
	adrp	x9, _ICODE_FPGA_EMULATION@GOTPAGE
Lloh1:
	ldr	x9, [x9, _ICODE_FPGA_EMULATION@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
Lloh3:
	adrp	x10, _FPGA_CCLOCK_PS@GOTPAGE
Lloh4:
	ldr	x10, [x10, _FPGA_CCLOCK_PS@GOTPAGEOFF]
Lloh5:
	adrp	x11, _ASIC_CCLOCK_PS@GOTPAGE
Lloh6:
	ldr	x11, [x11, _ASIC_CCLOCK_PS@GOTPAGEOFF]
	cmp	x8, x9
	csel	x8, x10, x11, eq
	ldr	w8, [x8]
	mul	w8, w8, w1
	mov	w9, #19923
	movk	w9, #4194, lsl #16
	smull	x9, w8, w9
	lsr	x10, x9, #63
	asr	x9, x9, #38
	add	w9, w9, w10
	sub	w8, w8, #1000
	cmn	w8, #1999
	ccmp	w1, #0, #4, hs
	csinc	w0, w9, wzr, eq
	ret
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_ICODE_FPGA_EMULATION,8,3       ; @ICODE_FPGA_EMULATION
	.comm	_FPGA_CCLOCK_PS,4,2             ; @FPGA_CCLOCK_PS
	.comm	_ASIC_CCLOCK_PS,4,2             ; @ASIC_CCLOCK_PS
.subsections_via_symbols
