	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function atmel_smc_nand_prepare_smcconf
_atmel_smc_nand_prepare_smcconf:        ## @atmel_smc_nand_prepare_smcconf
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r13
	movq	%rsi, %r14
	movq	%rdi, %r15
	movl	4(%rdi), %edi
	callq	_to_nand_controller
	movq	%rax, %rbx
	movq	(%r14), %rax
	movq	_NAND_SDR_IFACE@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_1
## %bb.2:
	cmpl	$29999, 8(%r14)                 ## imm = 0x752F
	jg	LBB0_3
LBB0_1:
	movq	_ENOTSUPP@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_20:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_3:
	movq	%r13, %rdi
	callq	_atmel_smc_cs_conf_init
	movq	_NSEC_PER_SEC@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	(%rbx), %edi
	callq	_clk_get_rate
	movl	%eax, %ecx
	movl	%r12d, %eax
	cltd
	idivl	%ecx
	imull	$1000, %eax, %esi               ## imm = 0x3E8
	movl	12(%r14), %edi
	movl	%esi, -44(%rbp)                 ## 4-byte Spill
	callq	_DIV_ROUND_UP
	movq	%r13, %rdi
	movl	%eax, %r13d
	movq	_ATMEL_SMC_NWE_SHIFT@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%rdi, -56(%rbp)                 ## 8-byte Spill
	movl	%eax, %edx
	callq	_atmel_smc_cs_conf_set_pulse
	testl	%eax, %eax
	jne	LBB0_20
## %bb.4:
	movl	88(%r14), %esi
	movl	16(%r14), %edi
	movl	84(%r14), %edx
	callq	_max3
	movl	20(%r14), %esi
	movl	%eax, %edi
	callq	_max
	movl	%eax, %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_DIV_ROUND_UP
	movl	%eax, %r12d
	xorl	%eax, %eax
	subl	%r13d, %r12d
	cmovlel	%eax, %r12d
	movl	(%rbx), %esi
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	movl	%r12d, %edx
	callq	_atmel_smc_cs_conf_set_setup
	testl	%eax, %eax
	jne	LBB0_20
## %bb.5:
	addl	%r13d, %r12d
	movl	80(%r14), %esi
	movl	24(%r14), %edi
	movl	76(%r14), %edx
	callq	_max3
	movl	68(%r14), %edx
	movl	72(%r14), %esi
	movl	%eax, %edi
	callq	_max3
	movl	%eax, %edi
	movq	%rbx, %r13
	movl	-44(%rbp), %ebx                 ## 4-byte Reload
	movl	%ebx, %esi
	callq	_DIV_ROUND_UP
	addl	%eax, %r12d
	movl	28(%r14), %edi
	movl	%ebx, %esi
	callq	_DIV_ROUND_UP
	movl	%r12d, %edi
	movl	%eax, %esi
	callq	_max
	movl	%eax, %r12d
	movl	(%r13), %esi
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	movl	%eax, %edx
	callq	_atmel_smc_cs_conf_set_cycle
	testl	%eax, %eax
	jne	LBB0_20
## %bb.6:
	movq	_ATMEL_SMC_NCS_WR_SHIFT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	movl	%r12d, %edx
	callq	_atmel_smc_cs_conf_set_pulse
	testl	%eax, %eax
	jne	LBB0_20
## %bb.7:
	movl	32(%r14), %edi
	movl	36(%r14), %esi
	callq	_max
	movl	%eax, %edi
	movl	-44(%rbp), %r13d                ## 4-byte Reload
	movl	%r13d, %esi
	callq	_DIV_ROUND_UP
	movl	%eax, %r12d
	movl	40(%r14), %edi
	movl	%r13d, %esi
	callq	_DIV_ROUND_UP
	subl	%r12d, %eax
	movq	_ATMEL_SMC_MODE_TDF_MAX@GOTPCREL(%rip), %rcx
	movq	_ATMEL_SMC_MODE_TDF_MIN@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edi
	cmpl	%edi, %eax
	cmovgl	%eax, %edi
	movl	(%rcx), %ecx
	cmpl	%ecx, %eax
	cmovgl	%ecx, %edi
	callq	_ATMEL_SMC_MODE_TDF
	movq	_ATMEL_SMC_MODE_TDFMODE_OPTIMIZED@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	orl	%eax, (%rbx)
	movl	44(%r14), %edi
	movl	%r13d, %esi
	callq	_DIV_ROUND_UP
	movl	%eax, %r13d
	movq	_ATMEL_SMC_NRD_SHIFT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	%r13d, %edx
	callq	_atmel_smc_cs_conf_set_pulse
	testl	%eax, %eax
	jne	LBB0_20
## %bb.8:
	addl	%r12d, %r13d
	movl	8(%r14), %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_DIV_ROUND_UP
	movl	%r13d, %edi
	movl	%eax, %esi
	callq	_max
	movl	%eax, %r12d
	movq	_ATMEL_SMC_NRD_SHIFT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	movl	%r12d, %edx
	callq	_atmel_smc_cs_conf_set_cycle
	testl	%eax, %eax
	jne	LBB0_20
## %bb.9:
	movq	_ATMEL_SMC_NCS_RD_SHIFT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	movl	%r12d, %edx
	callq	_atmel_smc_cs_conf_set_pulse
	testl	%eax, %eax
	jne	LBB0_20
## %bb.10:
	movl	48(%r14), %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_DIV_ROUND_UP
	movq	_ATMEL_HSMC_TIMINGS_TCLR_SHIFT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	movl	%eax, %edx
	callq	_atmel_smc_cs_conf_set_timing
	testl	%eax, %eax
	jne	LBB0_20
## %bb.11:
	movl	52(%r14), %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_DIV_ROUND_UP
	movq	_ATMEL_HSMC_TIMINGS_TADL_SHIFT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	movl	%eax, %edx
	callq	_atmel_smc_cs_conf_set_timing
	testl	%eax, %eax
	je	LBB0_13
## %bb.12:
	movq	_ERANGE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	addl	%eax, %ecx
	jne	LBB0_20
LBB0_13:
	movl	56(%r14), %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_DIV_ROUND_UP
	movq	_ATMEL_HSMC_TIMINGS_TAR_SHIFT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	movl	%eax, %edx
	callq	_atmel_smc_cs_conf_set_timing
	testl	%eax, %eax
	jne	LBB0_20
## %bb.14:
	movl	60(%r14), %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_DIV_ROUND_UP
	movq	_ATMEL_HSMC_TIMINGS_TRR_SHIFT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	movl	%eax, %edx
	callq	_atmel_smc_cs_conf_set_timing
	testl	%eax, %eax
	jne	LBB0_20
## %bb.15:
	movl	64(%r14), %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_DIV_ROUND_UP
	movq	_ATMEL_HSMC_TIMINGS_TWB_SHIFT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	movl	%eax, %edx
	callq	_atmel_smc_cs_conf_set_timing
	testl	%eax, %eax
	jne	LBB0_20
## %bb.16:
	movq	_ATMEL_HSMC_TIMINGS_NFSEL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	movq	%rcx, %rsi
	orl	%eax, 4(%rcx)
	movq	_NAND_BUSWIDTH_16@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r15)
	je	LBB0_17
## %bb.18:
	movq	_ATMEL_SMC_MODE_DBW_16@GOTPCREL(%rip), %rcx
	movq	%rsi, %rdx
	movl	(%rsi), %eax
	orl	(%rcx), %eax
	movl	%eax, (%rsi)
	jmp	LBB0_19
LBB0_17:
	movl	(%rsi), %eax
LBB0_19:
	movq	_ATMEL_SMC_MODE_READMODE_NRD@GOTPCREL(%rip), %rcx
	movq	_ATMEL_SMC_MODE_WRITEMODE_NWE@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	orl	%eax, %edx
	movl	%edx, (%rsi)
	xorl	%eax, %eax
	jmp	LBB0_20
	.cfi_endproc
                                        ## -- End function
	.comm	_NAND_SDR_IFACE,8,3             ## @NAND_SDR_IFACE
	.comm	_ENOTSUPP,4,2                   ## @ENOTSUPP
	.comm	_NSEC_PER_SEC,4,2               ## @NSEC_PER_SEC
	.comm	_ATMEL_SMC_NWE_SHIFT,4,2        ## @ATMEL_SMC_NWE_SHIFT
	.comm	_ATMEL_SMC_NCS_WR_SHIFT,4,2     ## @ATMEL_SMC_NCS_WR_SHIFT
	.comm	_ATMEL_SMC_MODE_TDF_MAX,4,2     ## @ATMEL_SMC_MODE_TDF_MAX
	.comm	_ATMEL_SMC_MODE_TDF_MIN,4,2     ## @ATMEL_SMC_MODE_TDF_MIN
	.comm	_ATMEL_SMC_MODE_TDFMODE_OPTIMIZED,4,2 ## @ATMEL_SMC_MODE_TDFMODE_OPTIMIZED
	.comm	_ATMEL_SMC_NRD_SHIFT,4,2        ## @ATMEL_SMC_NRD_SHIFT
	.comm	_ATMEL_SMC_NCS_RD_SHIFT,4,2     ## @ATMEL_SMC_NCS_RD_SHIFT
	.comm	_ATMEL_HSMC_TIMINGS_TCLR_SHIFT,4,2 ## @ATMEL_HSMC_TIMINGS_TCLR_SHIFT
	.comm	_ATMEL_HSMC_TIMINGS_TADL_SHIFT,4,2 ## @ATMEL_HSMC_TIMINGS_TADL_SHIFT
	.comm	_ERANGE,4,2                     ## @ERANGE
	.comm	_ATMEL_HSMC_TIMINGS_TAR_SHIFT,4,2 ## @ATMEL_HSMC_TIMINGS_TAR_SHIFT
	.comm	_ATMEL_HSMC_TIMINGS_TRR_SHIFT,4,2 ## @ATMEL_HSMC_TIMINGS_TRR_SHIFT
	.comm	_ATMEL_HSMC_TIMINGS_TWB_SHIFT,4,2 ## @ATMEL_HSMC_TIMINGS_TWB_SHIFT
	.comm	_ATMEL_HSMC_TIMINGS_NFSEL,4,2   ## @ATMEL_HSMC_TIMINGS_NFSEL
	.comm	_NAND_BUSWIDTH_16,4,2           ## @NAND_BUSWIDTH_16
	.comm	_ATMEL_SMC_MODE_DBW_16,4,2      ## @ATMEL_SMC_MODE_DBW_16
	.comm	_ATMEL_SMC_MODE_READMODE_NRD,4,2 ## @ATMEL_SMC_MODE_READMODE_NRD
	.comm	_ATMEL_SMC_MODE_WRITEMODE_NWE,4,2 ## @ATMEL_SMC_MODE_WRITEMODE_NWE
	.no_dead_strip	_atmel_smc_nand_prepare_smcconf
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function atmel_smc_nand_prepare_smcconf
_atmel_smc_nand_prepare_smcconf:        ; @atmel_smc_nand_prepare_smcconf
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x2
	mov	x21, x1
	mov	x20, x0
	ldr	w0, [x0, #4]
	bl	_to_nand_controller
	ldr	x8, [x21]
Lloh0:
	adrp	x9, _NAND_SDR_IFACE@GOTPAGE
Lloh1:
	ldr	x9, [x9, _NAND_SDR_IFACE@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_2
; %bb.1:
	ldr	w8, [x21, #8]
	mov	w9, #29999
	cmp	w8, w9
	b.gt	LBB0_4
LBB0_2:
Lloh3:
	adrp	x8, _ENOTSUPP@GOTPAGE
Lloh4:
	ldr	x8, [x8, _ENOTSUPP@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_3:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_4:
	mov	x22, x0
	mov	x0, x19
	bl	_atmel_smc_cs_conf_init
Lloh6:
	adrp	x8, _NSEC_PER_SEC@GOTPAGE
Lloh7:
	ldr	x8, [x8, _NSEC_PER_SEC@GOTPAGEOFF]
Lloh8:
	ldr	w23, [x8]
	ldr	w0, [x22]
	bl	_clk_get_rate
	sdiv	w8, w23, w0
	mov	w9, #1000
	mul	w22, w8, w9
	ldr	w0, [x21, #12]
	mov	x1, x22
	bl	_DIV_ROUND_UP
	mov	x23, x0
Lloh9:
	adrp	x25, _ATMEL_SMC_NWE_SHIFT@GOTPAGE
Lloh10:
	ldr	x25, [x25, _ATMEL_SMC_NWE_SHIFT@GOTPAGEOFF]
	ldr	w1, [x25]
	mov	x0, x19
	mov	x2, x23
	bl	_atmel_smc_cs_conf_set_pulse
	cbnz	w0, LBB0_3
; %bb.5:
	ldr	w0, [x21, #16]
	ldp	w2, w1, [x21, #84]
	bl	_max3
	ldr	w1, [x21, #20]
	bl	_max
	mov	x1, x22
	bl	_DIV_ROUND_UP
	subs	w8, w0, w23
	csel	w24, w8, wzr, gt
	ldr	w1, [x25]
	mov	x0, x19
	mov	x2, x24
	bl	_atmel_smc_cs_conf_set_setup
	cbnz	w0, LBB0_3
; %bb.6:
	add	w23, w24, w23
	ldr	w0, [x21, #24]
	ldp	w2, w1, [x21, #76]
	bl	_max3
	ldp	w2, w1, [x21, #68]
	bl	_max3
	mov	x1, x22
	bl	_DIV_ROUND_UP
	add	w23, w23, w0
	ldr	w0, [x21, #28]
	mov	x1, x22
	bl	_DIV_ROUND_UP
	mov	x1, x0
	mov	x0, x23
	bl	_max
	mov	x23, x0
	ldr	w1, [x25]
	mov	x0, x19
	mov	x2, x23
	bl	_atmel_smc_cs_conf_set_cycle
	cbnz	w0, LBB0_3
; %bb.7:
Lloh11:
	adrp	x8, _ATMEL_SMC_NCS_WR_SHIFT@GOTPAGE
Lloh12:
	ldr	x8, [x8, _ATMEL_SMC_NCS_WR_SHIFT@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x23
	bl	_atmel_smc_cs_conf_set_pulse
	cbnz	w0, LBB0_3
; %bb.8:
	ldp	w0, w1, [x21, #32]
	bl	_max
	mov	x1, x22
	bl	_DIV_ROUND_UP
	mov	x23, x0
	ldr	w0, [x21, #40]
	mov	x1, x22
	bl	_DIV_ROUND_UP
Lloh14:
	adrp	x8, _ATMEL_SMC_MODE_TDF_MAX@GOTPAGE
Lloh15:
	ldr	x8, [x8, _ATMEL_SMC_MODE_TDF_MAX@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
Lloh17:
	adrp	x9, _ATMEL_SMC_MODE_TDF_MIN@GOTPAGE
Lloh18:
	ldr	x9, [x9, _ATMEL_SMC_MODE_TDF_MIN@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	sub	w10, w0, w23
	cmp	w10, w9
	csel	w9, w10, w9, gt
	cmp	w10, w8
	csel	w0, w8, w9, gt
	bl	_ATMEL_SMC_MODE_TDF
Lloh20:
	adrp	x8, _ATMEL_SMC_MODE_TDFMODE_OPTIMIZED@GOTPAGE
Lloh21:
	ldr	x8, [x8, _ATMEL_SMC_MODE_TDFMODE_OPTIMIZED@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
	orr	w8, w8, w0
	ldr	w9, [x19]
	orr	w8, w8, w9
	str	w8, [x19]
	ldr	w0, [x21, #44]
	mov	x1, x22
	bl	_DIV_ROUND_UP
	mov	x24, x0
Lloh23:
	adrp	x25, _ATMEL_SMC_NRD_SHIFT@GOTPAGE
Lloh24:
	ldr	x25, [x25, _ATMEL_SMC_NRD_SHIFT@GOTPAGEOFF]
	ldr	w1, [x25]
	mov	x0, x19
	mov	x2, x24
	bl	_atmel_smc_cs_conf_set_pulse
	cbnz	w0, LBB0_3
; %bb.9:
	add	w23, w24, w23
	ldr	w0, [x21, #8]
	mov	x1, x22
	bl	_DIV_ROUND_UP
	mov	x1, x0
	mov	x0, x23
	bl	_max
	mov	x23, x0
	ldr	w1, [x25]
	mov	x0, x19
	mov	x2, x23
	bl	_atmel_smc_cs_conf_set_cycle
	cbnz	w0, LBB0_3
; %bb.10:
Lloh25:
	adrp	x8, _ATMEL_SMC_NCS_RD_SHIFT@GOTPAGE
Lloh26:
	ldr	x8, [x8, _ATMEL_SMC_NCS_RD_SHIFT@GOTPAGEOFF]
Lloh27:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x23
	bl	_atmel_smc_cs_conf_set_pulse
	cbnz	w0, LBB0_3
; %bb.11:
	ldr	w0, [x21, #48]
	mov	x1, x22
	bl	_DIV_ROUND_UP
	mov	x2, x0
Lloh28:
	adrp	x8, _ATMEL_HSMC_TIMINGS_TCLR_SHIFT@GOTPAGE
Lloh29:
	ldr	x8, [x8, _ATMEL_HSMC_TIMINGS_TCLR_SHIFT@GOTPAGEOFF]
Lloh30:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_atmel_smc_cs_conf_set_timing
	cbnz	w0, LBB0_3
; %bb.12:
	ldr	w0, [x21, #52]
	mov	x1, x22
	bl	_DIV_ROUND_UP
	mov	x2, x0
Lloh31:
	adrp	x8, _ATMEL_HSMC_TIMINGS_TADL_SHIFT@GOTPAGE
Lloh32:
	ldr	x8, [x8, _ATMEL_HSMC_TIMINGS_TADL_SHIFT@GOTPAGEOFF]
Lloh33:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_atmel_smc_cs_conf_set_timing
	cbz	w0, LBB0_14
; %bb.13:
Lloh34:
	adrp	x8, _ERANGE@GOTPAGE
Lloh35:
	ldr	x8, [x8, _ERANGE@GOTPAGEOFF]
Lloh36:
	ldr	w8, [x8]
	cmn	w0, w8
	b.ne	LBB0_3
LBB0_14:
	ldr	w0, [x21, #56]
	mov	x1, x22
	bl	_DIV_ROUND_UP
	mov	x2, x0
Lloh37:
	adrp	x8, _ATMEL_HSMC_TIMINGS_TAR_SHIFT@GOTPAGE
Lloh38:
	ldr	x8, [x8, _ATMEL_HSMC_TIMINGS_TAR_SHIFT@GOTPAGEOFF]
Lloh39:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_atmel_smc_cs_conf_set_timing
	cbnz	w0, LBB0_3
; %bb.15:
	ldr	w0, [x21, #60]
	mov	x1, x22
	bl	_DIV_ROUND_UP
	mov	x2, x0
Lloh40:
	adrp	x8, _ATMEL_HSMC_TIMINGS_TRR_SHIFT@GOTPAGE
Lloh41:
	ldr	x8, [x8, _ATMEL_HSMC_TIMINGS_TRR_SHIFT@GOTPAGEOFF]
Lloh42:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_atmel_smc_cs_conf_set_timing
	cbnz	w0, LBB0_3
; %bb.16:
	ldr	w0, [x21, #64]
	mov	x1, x22
	bl	_DIV_ROUND_UP
	mov	x2, x0
Lloh43:
	adrp	x8, _ATMEL_HSMC_TIMINGS_TWB_SHIFT@GOTPAGE
Lloh44:
	ldr	x8, [x8, _ATMEL_HSMC_TIMINGS_TWB_SHIFT@GOTPAGEOFF]
Lloh45:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_atmel_smc_cs_conf_set_timing
	cbnz	w0, LBB0_3
; %bb.17:
Lloh46:
	adrp	x8, _ATMEL_HSMC_TIMINGS_NFSEL@GOTPAGE
Lloh47:
	ldr	x8, [x8, _ATMEL_HSMC_TIMINGS_NFSEL@GOTPAGEOFF]
Lloh48:
	ldr	w8, [x8]
	ldr	w9, [x19, #4]
	orr	w8, w9, w8
	str	w8, [x19, #4]
	ldr	w8, [x20]
Lloh49:
	adrp	x9, _NAND_BUSWIDTH_16@GOTPAGE
Lloh50:
	ldr	x9, [x9, _NAND_BUSWIDTH_16@GOTPAGEOFF]
Lloh51:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_19
; %bb.18:
Lloh52:
	adrp	x8, _ATMEL_SMC_MODE_DBW_16@GOTPAGE
Lloh53:
	ldr	x8, [x8, _ATMEL_SMC_MODE_DBW_16@GOTPAGEOFF]
Lloh54:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
	b	LBB0_20
LBB0_19:
	ldr	w8, [x19]
LBB0_20:
	mov	w0, #0
Lloh55:
	adrp	x9, _ATMEL_SMC_MODE_READMODE_NRD@GOTPAGE
Lloh56:
	ldr	x9, [x9, _ATMEL_SMC_MODE_READMODE_NRD@GOTPAGEOFF]
Lloh57:
	ldr	w9, [x9]
Lloh58:
	adrp	x10, _ATMEL_SMC_MODE_WRITEMODE_NWE@GOTPAGE
Lloh59:
	ldr	x10, [x10, _ATMEL_SMC_MODE_WRITEMODE_NWE@GOTPAGEOFF]
Lloh60:
	ldr	w10, [x10]
	orr	w9, w10, w9
	orr	w8, w9, w8
	str	w8, [x19]
	b	LBB0_3
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.cfi_endproc
                                        ; -- End function
	.comm	_NAND_SDR_IFACE,8,3             ; @NAND_SDR_IFACE
	.comm	_ENOTSUPP,4,2                   ; @ENOTSUPP
	.comm	_NSEC_PER_SEC,4,2               ; @NSEC_PER_SEC
	.comm	_ATMEL_SMC_NWE_SHIFT,4,2        ; @ATMEL_SMC_NWE_SHIFT
	.comm	_ATMEL_SMC_NCS_WR_SHIFT,4,2     ; @ATMEL_SMC_NCS_WR_SHIFT
	.comm	_ATMEL_SMC_MODE_TDF_MAX,4,2     ; @ATMEL_SMC_MODE_TDF_MAX
	.comm	_ATMEL_SMC_MODE_TDF_MIN,4,2     ; @ATMEL_SMC_MODE_TDF_MIN
	.comm	_ATMEL_SMC_MODE_TDFMODE_OPTIMIZED,4,2 ; @ATMEL_SMC_MODE_TDFMODE_OPTIMIZED
	.comm	_ATMEL_SMC_NRD_SHIFT,4,2        ; @ATMEL_SMC_NRD_SHIFT
	.comm	_ATMEL_SMC_NCS_RD_SHIFT,4,2     ; @ATMEL_SMC_NCS_RD_SHIFT
	.comm	_ATMEL_HSMC_TIMINGS_TCLR_SHIFT,4,2 ; @ATMEL_HSMC_TIMINGS_TCLR_SHIFT
	.comm	_ATMEL_HSMC_TIMINGS_TADL_SHIFT,4,2 ; @ATMEL_HSMC_TIMINGS_TADL_SHIFT
	.comm	_ERANGE,4,2                     ; @ERANGE
	.comm	_ATMEL_HSMC_TIMINGS_TAR_SHIFT,4,2 ; @ATMEL_HSMC_TIMINGS_TAR_SHIFT
	.comm	_ATMEL_HSMC_TIMINGS_TRR_SHIFT,4,2 ; @ATMEL_HSMC_TIMINGS_TRR_SHIFT
	.comm	_ATMEL_HSMC_TIMINGS_TWB_SHIFT,4,2 ; @ATMEL_HSMC_TIMINGS_TWB_SHIFT
	.comm	_ATMEL_HSMC_TIMINGS_NFSEL,4,2   ; @ATMEL_HSMC_TIMINGS_NFSEL
	.comm	_NAND_BUSWIDTH_16,4,2           ; @NAND_BUSWIDTH_16
	.comm	_ATMEL_SMC_MODE_DBW_16,4,2      ; @ATMEL_SMC_MODE_DBW_16
	.comm	_ATMEL_SMC_MODE_READMODE_NRD,4,2 ; @ATMEL_SMC_MODE_READMODE_NRD
	.comm	_ATMEL_SMC_MODE_WRITEMODE_NWE,4,2 ; @ATMEL_SMC_MODE_WRITEMODE_NWE
	.no_dead_strip	_atmel_smc_nand_prepare_smcconf
.subsections_via_symbols
