	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function xgene_sgmac_set_speed
_xgene_sgmac_set_speed:                 ## @xgene_sgmac_set_speed
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	callq	_xgene_sgmii_reset
	movq	(%rbx), %rax
	movq	_XGENE_ENET1@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_2
## %bb.1:
	movq	_ICM_CONFIG0_REG_0_ADDR@GOTPCREL(%rip), %rax
	movl	8(%rbx), %r14d
	movq	_OFFSET_8@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r15d
	imull	%r14d, %r15d
	addl	(%rax), %r15d
	movq	_OFFSET_4@GOTPCREL(%rip), %rax
	imull	(%rax), %r14d
	movq	_ICM_CONFIG2_REG_0_ADDR@GOTPCREL(%rip), %rax
	addl	(%rax), %r14d
	movq	_DEBUG_REG_ADDR@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_2:
	movq	_XG_MCX_ICM_CONFIG0_REG_0_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_XG_MCX_ICM_CONFIG2_REG_0_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_XG_DEBUG_REG_ADDR@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %r13d
	movq	%rbx, %rdi
	movl	%r15d, %esi
	callq	_xgene_enet_rd_mcx_csr
	movl	%eax, -52(%rbp)
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_xgene_enet_rd_mcx_csr
	movl	%eax, -48(%rbp)
	movq	_MAC_CONFIG_2_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_xgene_enet_rd_mac
	movl	%eax, -44(%rbp)
	movq	_INTERFACE_CONTROL_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_xgene_enet_rd_mac
	movl	%eax, %r12d
	movl	12(%rbx), %eax
	leaq	-44(%rbp), %rdi
	cmpl	$128, %eax
	je	LBB0_6
## %bb.4:
	cmpl	$129, %eax
	jne	LBB0_7
## %bb.5:
	movl	$1, %esi
	callq	_ENET_INTERFACE_MODE2_SET
	movq	_ENET_LHD_MODE@GOTPCREL(%rip), %rax
	movq	_ENET_GHD_MODE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	notl	%ecx
	andl	%ecx, %r12d
	leaq	-52(%rbp), %rdi
	xorl	%esi, %esi
	callq	_CFG_MACMODE_SET
	leaq	-48(%rbp), %rdi
	movl	$500, %esi                      ## imm = 0x1F4
	callq	_CFG_WAITASYNCRD_SET
	jmp	LBB0_8
LBB0_6:
	movl	$1, %esi
	callq	_ENET_INTERFACE_MODE2_SET
	movq	_ENET_GHD_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r12d
	movq	_ENET_LHD_MODE@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
	leaq	-52(%rbp), %rdi
	movl	$1, %esi
	callq	_CFG_MACMODE_SET
	leaq	-48(%rbp), %rdi
	movl	$80, %esi
	callq	_CFG_WAITASYNCRD_SET
	jmp	LBB0_8
LBB0_7:
	movl	$2, %esi
	callq	_ENET_INTERFACE_MODE2_SET
	movq	_ENET_LHD_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r12d
	movq	_ENET_GHD_MODE@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
	leaq	-52(%rbp), %rdi
	movl	$2, %esi
	callq	_CFG_MACMODE_SET
	leaq	-48(%rbp), %rdi
	movl	$16, %esi
	callq	_CFG_WAITASYNCRD_SET
	movq	%rbx, %rdi
	movl	%r13d, %esi
	callq	_xgene_enet_rd_csr
	movq	_CFG_BYPASS_UNISEC_TX@GOTPCREL(%rip), %rcx
	movq	_CFG_BYPASS_UNISEC_RX@GOTPCREL(%rip), %rdx
	orl	(%rcx), %eax
	orl	(%rdx), %eax
	movq	%rbx, %rdi
	movl	%r13d, %esi
	movl	%eax, %edx
	callq	_xgene_enet_wr_csr
LBB0_8:
	movq	_FULL_DUPLEX2@GOTPCREL(%rip), %rax
	movq	_PAD_CRC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	orl	-44(%rbp), %edx
	movl	%edx, -44(%rbp)
	movq	_MAC_CONFIG_2_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_xgene_enet_wr_mac
	movq	_INTERFACE_CONTROL_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	%r12d, %edx
	callq	_xgene_enet_wr_mac
	movl	-52(%rbp), %edx
	movq	%rbx, %rdi
	movl	%r15d, %esi
	callq	_xgene_enet_wr_mcx_csr
	movl	-48(%rbp), %edx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_xgene_enet_wr_mcx_csr
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_XGENE_ENET1,8,3                ## @XGENE_ENET1
	.comm	_ICM_CONFIG0_REG_0_ADDR,4,2     ## @ICM_CONFIG0_REG_0_ADDR
	.comm	_OFFSET_8,4,2                   ## @OFFSET_8
	.comm	_ICM_CONFIG2_REG_0_ADDR,4,2     ## @ICM_CONFIG2_REG_0_ADDR
	.comm	_OFFSET_4,4,2                   ## @OFFSET_4
	.comm	_DEBUG_REG_ADDR,4,2             ## @DEBUG_REG_ADDR
	.comm	_XG_MCX_ICM_CONFIG0_REG_0_ADDR,4,2 ## @XG_MCX_ICM_CONFIG0_REG_0_ADDR
	.comm	_XG_MCX_ICM_CONFIG2_REG_0_ADDR,4,2 ## @XG_MCX_ICM_CONFIG2_REG_0_ADDR
	.comm	_XG_DEBUG_REG_ADDR,4,2          ## @XG_DEBUG_REG_ADDR
	.comm	_MAC_CONFIG_2_ADDR,4,2          ## @MAC_CONFIG_2_ADDR
	.comm	_INTERFACE_CONTROL_ADDR,4,2     ## @INTERFACE_CONTROL_ADDR
	.comm	_ENET_LHD_MODE,4,2              ## @ENET_LHD_MODE
	.comm	_ENET_GHD_MODE,4,2              ## @ENET_GHD_MODE
	.comm	_CFG_BYPASS_UNISEC_TX,4,2       ## @CFG_BYPASS_UNISEC_TX
	.comm	_CFG_BYPASS_UNISEC_RX,4,2       ## @CFG_BYPASS_UNISEC_RX
	.comm	_FULL_DUPLEX2,4,2               ## @FULL_DUPLEX2
	.comm	_PAD_CRC,4,2                    ## @PAD_CRC
	.no_dead_strip	_xgene_sgmac_set_speed
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function xgene_sgmac_set_speed
_xgene_sgmac_set_speed:                 ; @xgene_sgmac_set_speed
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	bl	_xgene_sgmii_reset
	ldr	x8, [x19]
Lloh0:
	adrp	x9, _XGENE_ENET1@GOTPAGE
Lloh1:
	ldr	x9, [x9, _XGENE_ENET1@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_2
; %bb.1:
Lloh3:
	adrp	x8, _ICM_CONFIG0_REG_0_ADDR@GOTPAGE
Lloh4:
	ldr	x8, [x8, _ICM_CONFIG0_REG_0_ADDR@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
Lloh6:
	adrp	x9, _OFFSET_8@GOTPAGE
Lloh7:
	ldr	x9, [x9, _OFFSET_8@GOTPAGEOFF]
	ldr	w10, [x19, #8]
Lloh8:
	ldr	w9, [x9]
	madd	w20, w9, w10, w8
Lloh9:
	adrp	x8, _ICM_CONFIG2_REG_0_ADDR@GOTPAGE
Lloh10:
	ldr	x8, [x8, _ICM_CONFIG2_REG_0_ADDR@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
Lloh12:
	adrp	x9, _OFFSET_4@GOTPAGE
Lloh13:
	ldr	x9, [x9, _OFFSET_4@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	madd	w21, w9, w10, w8
Lloh15:
	adrp	x8, _DEBUG_REG_ADDR@GOTPAGE
Lloh16:
	ldr	x8, [x8, _DEBUG_REG_ADDR@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:
Lloh17:
	adrp	x8, _XG_MCX_ICM_CONFIG0_REG_0_ADDR@GOTPAGE
Lloh18:
	ldr	x8, [x8, _XG_MCX_ICM_CONFIG0_REG_0_ADDR@GOTPAGEOFF]
Lloh19:
	ldr	w20, [x8]
Lloh20:
	adrp	x8, _XG_MCX_ICM_CONFIG2_REG_0_ADDR@GOTPAGE
Lloh21:
	ldr	x8, [x8, _XG_MCX_ICM_CONFIG2_REG_0_ADDR@GOTPAGEOFF]
Lloh22:
	ldr	w21, [x8]
Lloh23:
	adrp	x8, _XG_DEBUG_REG_ADDR@GOTPAGE
Lloh24:
	ldr	x8, [x8, _XG_DEBUG_REG_ADDR@GOTPAGEOFF]
LBB0_3:
	ldr	w23, [x8]
	mov	x0, x19
	mov	x1, x20
	bl	_xgene_enet_rd_mcx_csr
	str	w0, [sp, #12]
	mov	x0, x19
	mov	x1, x21
	bl	_xgene_enet_rd_mcx_csr
	str	w0, [sp, #8]
Lloh25:
	adrp	x24, _MAC_CONFIG_2_ADDR@GOTPAGE
Lloh26:
	ldr	x24, [x24, _MAC_CONFIG_2_ADDR@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	x0, x19
	bl	_xgene_enet_rd_mac
	str	w0, [sp, #4]
Lloh27:
	adrp	x25, _INTERFACE_CONTROL_ADDR@GOTPAGE
Lloh28:
	ldr	x25, [x25, _INTERFACE_CONTROL_ADDR@GOTPAGEOFF]
	ldr	w1, [x25]
	mov	x0, x19
	bl	_xgene_enet_rd_mac
	mov	x22, x0
	ldr	w8, [x19, #12]
	add	x0, sp, #4
	cmp	w8, #128
	b.eq	LBB0_6
; %bb.4:
	cmp	w8, #129
	b.ne	LBB0_7
; %bb.5:
	mov	w1, #1
	bl	_ENET_INTERFACE_MODE2_SET
Lloh29:
	adrp	x8, _ENET_LHD_MODE@GOTPAGE
Lloh30:
	ldr	x8, [x8, _ENET_LHD_MODE@GOTPAGEOFF]
Lloh31:
	ldr	w8, [x8]
Lloh32:
	adrp	x9, _ENET_GHD_MODE@GOTPAGE
Lloh33:
	ldr	x9, [x9, _ENET_GHD_MODE@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w22, w22, w8
	add	x0, sp, #12
	mov	w1, #0
	bl	_CFG_MACMODE_SET
	add	x0, sp, #8
	mov	w1, #500
	bl	_CFG_WAITASYNCRD_SET
	b	LBB0_8
LBB0_6:
	mov	w1, #1
	bl	_ENET_INTERFACE_MODE2_SET
Lloh35:
	adrp	x8, _ENET_GHD_MODE@GOTPAGE
Lloh36:
	ldr	x8, [x8, _ENET_GHD_MODE@GOTPAGEOFF]
Lloh37:
	ldr	w8, [x8]
	bic	w8, w22, w8
Lloh38:
	adrp	x9, _ENET_LHD_MODE@GOTPAGE
Lloh39:
	ldr	x9, [x9, _ENET_LHD_MODE@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
	orr	w22, w8, w9
	add	x0, sp, #12
	mov	w1, #1
	bl	_CFG_MACMODE_SET
	add	x0, sp, #8
	mov	w1, #80
	bl	_CFG_WAITASYNCRD_SET
	b	LBB0_8
LBB0_7:
	mov	w1, #2
	bl	_ENET_INTERFACE_MODE2_SET
Lloh41:
	adrp	x8, _ENET_LHD_MODE@GOTPAGE
Lloh42:
	ldr	x8, [x8, _ENET_LHD_MODE@GOTPAGEOFF]
Lloh43:
	ldr	w8, [x8]
	bic	w8, w22, w8
Lloh44:
	adrp	x9, _ENET_GHD_MODE@GOTPAGE
Lloh45:
	ldr	x9, [x9, _ENET_GHD_MODE@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
	orr	w22, w8, w9
	add	x0, sp, #12
	mov	w1, #2
	bl	_CFG_MACMODE_SET
	add	x0, sp, #8
	mov	w1, #16
	bl	_CFG_WAITASYNCRD_SET
	mov	x0, x19
	mov	x1, x23
	bl	_xgene_enet_rd_csr
Lloh47:
	adrp	x8, _CFG_BYPASS_UNISEC_TX@GOTPAGE
Lloh48:
	ldr	x8, [x8, _CFG_BYPASS_UNISEC_TX@GOTPAGEOFF]
Lloh49:
	ldr	w8, [x8]
Lloh50:
	adrp	x9, _CFG_BYPASS_UNISEC_RX@GOTPAGE
Lloh51:
	ldr	x9, [x9, _CFG_BYPASS_UNISEC_RX@GOTPAGEOFF]
Lloh52:
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w2, w8, w9
	mov	x0, x19
	mov	x1, x23
	bl	_xgene_enet_wr_csr
LBB0_8:
Lloh53:
	adrp	x8, _FULL_DUPLEX2@GOTPAGE
Lloh54:
	ldr	x8, [x8, _FULL_DUPLEX2@GOTPAGEOFF]
Lloh55:
	ldr	w8, [x8]
Lloh56:
	adrp	x9, _PAD_CRC@GOTPAGE
Lloh57:
	ldr	x9, [x9, _PAD_CRC@GOTPAGEOFF]
Lloh58:
	ldr	w9, [x9]
	orr	w8, w9, w8
	ldr	w9, [sp, #4]
	orr	w2, w8, w9
	str	w2, [sp, #4]
	ldr	w1, [x24]
	mov	x0, x19
	bl	_xgene_enet_wr_mac
	ldr	w1, [x25]
	mov	x0, x19
	mov	x2, x22
	bl	_xgene_enet_wr_mac
	ldr	w2, [sp, #12]
	mov	x0, x19
	mov	x1, x20
	bl	_xgene_enet_wr_mcx_csr
	ldr	w2, [sp, #8]
	mov	x0, x19
	mov	x1, x21
	bl	_xgene_enet_wr_mcx_csr
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.cfi_endproc
                                        ; -- End function
	.comm	_XGENE_ENET1,8,3                ; @XGENE_ENET1
	.comm	_ICM_CONFIG0_REG_0_ADDR,4,2     ; @ICM_CONFIG0_REG_0_ADDR
	.comm	_OFFSET_8,4,2                   ; @OFFSET_8
	.comm	_ICM_CONFIG2_REG_0_ADDR,4,2     ; @ICM_CONFIG2_REG_0_ADDR
	.comm	_OFFSET_4,4,2                   ; @OFFSET_4
	.comm	_DEBUG_REG_ADDR,4,2             ; @DEBUG_REG_ADDR
	.comm	_XG_MCX_ICM_CONFIG0_REG_0_ADDR,4,2 ; @XG_MCX_ICM_CONFIG0_REG_0_ADDR
	.comm	_XG_MCX_ICM_CONFIG2_REG_0_ADDR,4,2 ; @XG_MCX_ICM_CONFIG2_REG_0_ADDR
	.comm	_XG_DEBUG_REG_ADDR,4,2          ; @XG_DEBUG_REG_ADDR
	.comm	_MAC_CONFIG_2_ADDR,4,2          ; @MAC_CONFIG_2_ADDR
	.comm	_INTERFACE_CONTROL_ADDR,4,2     ; @INTERFACE_CONTROL_ADDR
	.comm	_ENET_LHD_MODE,4,2              ; @ENET_LHD_MODE
	.comm	_ENET_GHD_MODE,4,2              ; @ENET_GHD_MODE
	.comm	_CFG_BYPASS_UNISEC_TX,4,2       ; @CFG_BYPASS_UNISEC_TX
	.comm	_CFG_BYPASS_UNISEC_RX,4,2       ; @CFG_BYPASS_UNISEC_RX
	.comm	_FULL_DUPLEX2,4,2               ; @FULL_DUPLEX2
	.comm	_PAD_CRC,4,2                    ; @PAD_CRC
	.no_dead_strip	_xgene_sgmac_set_speed
.subsections_via_symbols
