	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function sunxi_mmc_clk_set_phase
_sunxi_mmc_clk_set_phase:               ## @sunxi_mmc_clk_set_phase
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	xorl	%r14d, %r14d
	cmpq	$0, 24(%rdi)
	jne	LBB0_14
## %bb.1:
	movq	%rdi, %rbx
	movq	(%rdi), %rax
	movq	(%rax), %rax
	testq	%rax, %rax
	je	LBB0_14
## %bb.2:
	cmpl	$400001, %edx                   ## imm = 0x61A81
	jge	LBB0_4
## %bb.3:
	movq	_SDXC_CLK_400K@GOTPCREL(%rip), %rcx
	jmp	LBB0_13
LBB0_4:
	cmpl	$25000001, %edx                 ## imm = 0x17D7841
	jae	LBB0_6
## %bb.5:
	movq	_SDXC_CLK_25M@GOTPCREL(%rip), %rcx
LBB0_13:
	movslq	(%rcx), %r15
	movl	12(%rbx), %edi
	movl	4(%rax,%r15,8), %esi
	callq	_clk_set_phase
	movl	8(%rbx), %edi
	movq	(%rbx), %rax
	movq	(%rax), %rax
	movl	(%rax,%r15,8), %esi
	callq	_clk_set_phase
LBB0_14:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_6:
	cmpl	$52000000, %edx                 ## imm = 0x3197500
	ja	LBB0_15
## %bb.7:
	movq	(%rsi), %rcx
	movq	_MMC_TIMING_UHS_DDR50@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	je	LBB0_10
## %bb.8:
	movq	_MMC_TIMING_MMC_DDR52@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	je	LBB0_10
## %bb.9:
	movq	_SDXC_CLK_50M@GOTPCREL(%rip), %rcx
	jmp	LBB0_13
LBB0_15:
	movl	16(%rbx), %edi
	callq	_mmc_dev
	leaq	L_.str(%rip), %rsi
	movl	%eax, %edi
	callq	_dev_dbg
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r14d, %r14d
	subl	(%rax), %r14d
	jmp	LBB0_14
LBB0_10:
	movq	8(%rsi), %rcx
	movq	_MMC_BUS_WIDTH_8@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_11
## %bb.12:
	movq	_SDXC_CLK_50M_DDR_8BIT@GOTPCREL(%rip), %rcx
	jmp	LBB0_13
LBB0_11:
	movq	_SDXC_CLK_50M_DDR@GOTPCREL(%rip), %rcx
	jmp	LBB0_13
	.cfi_endproc
                                        ## -- End function
	.comm	_SDXC_CLK_400K,4,2              ## @SDXC_CLK_400K
	.comm	_SDXC_CLK_25M,4,2               ## @SDXC_CLK_25M
	.comm	_MMC_TIMING_UHS_DDR50,8,3       ## @MMC_TIMING_UHS_DDR50
	.comm	_MMC_TIMING_MMC_DDR52,8,3       ## @MMC_TIMING_MMC_DDR52
	.comm	_SDXC_CLK_50M,4,2               ## @SDXC_CLK_50M
	.comm	_MMC_BUS_WIDTH_8,8,3            ## @MMC_BUS_WIDTH_8
	.comm	_SDXC_CLK_50M_DDR_8BIT,4,2      ## @SDXC_CLK_50M_DDR_8BIT
	.comm	_SDXC_CLK_50M_DDR,4,2           ## @SDXC_CLK_50M_DDR
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Invalid clock... returning\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.no_dead_strip	_sunxi_mmc_clk_set_phase
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function sunxi_mmc_clk_set_phase
_sunxi_mmc_clk_set_phase:               ; @sunxi_mmc_clk_set_phase
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	x8, [x0, #24]
	cbnz	x8, LBB0_12
; %bb.1:
	mov	x19, x0
	ldr	x8, [x0]
	ldr	x8, [x8]
	cbz	x8, LBB0_12
; %bb.2:
	mov	w9, #6785
	movk	w9, #6, lsl #16
	cmp	w2, w9
	b.ge	LBB0_4
; %bb.3:
Lloh0:
	adrp	x9, _SDXC_CLK_400K@GOTPAGE
Lloh1:
	ldr	x9, [x9, _SDXC_CLK_400K@GOTPAGEOFF]
	b	LBB0_11
LBB0_4:
	mov	w9, #30785
	movk	w9, #381, lsl #16
	cmp	w2, w9
	b.hs	LBB0_6
; %bb.5:
Lloh2:
	adrp	x9, _SDXC_CLK_25M@GOTPAGE
Lloh3:
	ldr	x9, [x9, _SDXC_CLK_25M@GOTPAGEOFF]
	b	LBB0_11
LBB0_6:
	mov	w9, #29952
	movk	w9, #793, lsl #16
	cmp	w2, w9
	b.hi	LBB0_9
; %bb.7:
	ldr	x9, [x1]
Lloh4:
	adrp	x10, _MMC_TIMING_UHS_DDR50@GOTPAGE
Lloh5:
	ldr	x10, [x10, _MMC_TIMING_UHS_DDR50@GOTPAGEOFF]
Lloh6:
	ldr	x10, [x10]
Lloh7:
	adrp	x11, _MMC_TIMING_MMC_DDR52@GOTPAGE
Lloh8:
	ldr	x11, [x11, _MMC_TIMING_MMC_DDR52@GOTPAGEOFF]
Lloh9:
	ldr	x11, [x11]
	cmp	x9, x10
	ccmp	x9, x11, #4, ne
	b.ne	LBB0_10
; %bb.8:
	ldr	x9, [x1, #8]
Lloh10:
	adrp	x10, _MMC_BUS_WIDTH_8@GOTPAGE
Lloh11:
	ldr	x10, [x10, _MMC_BUS_WIDTH_8@GOTPAGEOFF]
Lloh12:
	ldr	x10, [x10]
Lloh13:
	adrp	x11, _SDXC_CLK_50M_DDR@GOTPAGE
Lloh14:
	ldr	x11, [x11, _SDXC_CLK_50M_DDR@GOTPAGEOFF]
Lloh15:
	adrp	x12, _SDXC_CLK_50M_DDR_8BIT@GOTPAGE
Lloh16:
	ldr	x12, [x12, _SDXC_CLK_50M_DDR_8BIT@GOTPAGEOFF]
	cmp	x9, x10
	csel	x9, x12, x11, eq
	b	LBB0_11
LBB0_9:
	ldr	w0, [x19, #16]
	bl	_mmc_dev
Lloh17:
	adrp	x1, l_.str@PAGE
Lloh18:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_dbg
Lloh19:
	adrp	x8, _EINVAL@GOTPAGE
Lloh20:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_13
LBB0_10:
Lloh22:
	adrp	x9, _SDXC_CLK_50M@GOTPAGE
Lloh23:
	ldr	x9, [x9, _SDXC_CLK_50M@GOTPAGEOFF]
LBB0_11:
	ldrsw	x9, [x9]
	ldr	w0, [x19, #12]
	lsl	x20, x9, #3
	add	x8, x8, x20
	ldr	w1, [x8, #4]
	bl	_clk_set_phase
	ldr	w0, [x19, #8]
	ldr	x8, [x19]
	ldr	x8, [x8]
	ldr	w1, [x8, x20]
	bl	_clk_set_phase
LBB0_12:
	mov	w0, #0
LBB0_13:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpAdd	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh22, Lloh23
	.cfi_endproc
                                        ; -- End function
	.comm	_SDXC_CLK_400K,4,2              ; @SDXC_CLK_400K
	.comm	_SDXC_CLK_25M,4,2               ; @SDXC_CLK_25M
	.comm	_MMC_TIMING_UHS_DDR50,8,3       ; @MMC_TIMING_UHS_DDR50
	.comm	_MMC_TIMING_MMC_DDR52,8,3       ; @MMC_TIMING_MMC_DDR52
	.comm	_SDXC_CLK_50M,4,2               ; @SDXC_CLK_50M
	.comm	_MMC_BUS_WIDTH_8,8,3            ; @MMC_BUS_WIDTH_8
	.comm	_SDXC_CLK_50M_DDR_8BIT,4,2      ; @SDXC_CLK_50M_DDR_8BIT
	.comm	_SDXC_CLK_50M_DDR,4,2           ; @SDXC_CLK_50M_DDR
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Invalid clock... returning\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.no_dead_strip	_sunxi_mmc_clk_set_phase
.subsections_via_symbols
