	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function cim_intr_handler
_cim_intr_handler:                      ## @cim_intr_handler
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	_PCIE_FW_A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_t4_read_reg
	movl	%eax, %r14d
	movq	_PCIE_FW_ERR_F@GOTPCREL(%rip), %r12
	testl	%eax, (%r12)
	je	LBB0_2
## %bb.1:
	movq	%rbx, %rdi
	callq	_t4_report_fw_error
LBB0_2:
	movq	_CIM_HOST_INT_CAUSE_A@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_t4_read_reg
	testb	$-128, %al
	je	LBB0_6
## %bb.3:
	testl	%r14d, (%r12)
	je	LBB0_5
## %bb.4:
	movl	%r14d, %edi
	callq	_PCIE_FW_EVAL_G
	movq	_PCIE_FW_EVAL_CRASH@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_6
LBB0_5:
	movl	(%r15), %esi
	movq	%rbx, %rdi
	movl	$128, %edx
	callq	_t4_write_reg
LBB0_6:
	movl	(%r15), %esi
	leaq	_cim_intr_handler.cim_intr_info(%rip), %rdx
	movq	%rbx, %rdi
	callq	_t4_handle_intr_status
	movl	%eax, %r14d
	movq	_CIM_HOST_UPACC_INT_CAUSE_A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	_cim_intr_handler.cim_upintr_info(%rip), %rdx
	movq	%rbx, %rdi
	callq	_t4_handle_intr_status
	addl	%r14d, %eax
	jne	LBB0_8
## %bb.7:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_8:
	movq	%rbx, %rdi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_t4_fatal_err                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.section	__DATA,__const
	.p2align	4                               ## @cim_intr_handler.cim_intr_info
_cim_intr_handler.cim_intr_info:
	.long	146                             ## 0x92
	.space	4
	.quad	L_.str
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	154                             ## 0x9a
	.space	4
	.quad	L_.str.1
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	155                             ## 0x9b
	.space	4
	.quad	L_.str.2
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	147                             ## 0x93
	.space	4
	.quad	L_.str.3
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	148                             ## 0x94
	.space	4
	.quad	L_.str.4
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	132                             ## 0x84
	.space	4
	.quad	L_.str.5
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	131                             ## 0x83
	.space	4
	.quad	L_.str.6
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	128                             ## 0x80
	.space	4
	.quad	L_.str.7
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.space	24

	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"CIM control register prefetch drop"

L_.str.1:                               ## @.str.1
	.asciz	"CIM OBQ parity error"

L_.str.2:                               ## @.str.2
	.asciz	"CIM IBQ parity error"

L_.str.3:                               ## @.str.3
	.asciz	"CIM mailbox uP parity error"

L_.str.4:                               ## @.str.4
	.asciz	"CIM mailbox host parity error"

L_.str.5:                               ## @.str.5
	.asciz	"CIM TIEQ outgoing parity error"

L_.str.6:                               ## @.str.6
	.asciz	"CIM TIEQ incoming parity error"

L_.str.7:                               ## @.str.7
	.asciz	"CIM TIMER0 interrupt"

	.section	__DATA,__const
	.p2align	4                               ## @cim_intr_handler.cim_upintr_info
_cim_intr_handler.cim_upintr_info:
	.long	143                             ## 0x8f
	.space	4
	.quad	L_.str.8
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	151                             ## 0x97
	.space	4
	.quad	L_.str.9
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	149                             ## 0x95
	.space	4
	.quad	L_.str.10
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	152                             ## 0x98
	.space	4
	.quad	L_.str.11
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	153                             ## 0x99
	.space	4
	.quad	L_.str.12
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	150                             ## 0x96
	.space	4
	.quad	L_.str.13
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	142                             ## 0x8e
	.space	4
	.quad	L_.str.14
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	137                             ## 0x89
	.space	4
	.quad	L_.str.15
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	160                             ## 0xa0
	.space	4
	.quad	L_.str.16
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	139                             ## 0x8b
	.space	4
	.quad	L_.str.17
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	134                             ## 0x86
	.space	4
	.quad	L_.str.18
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	157                             ## 0x9d
	.space	4
	.quad	L_.str.19
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	140                             ## 0x8c
	.space	4
	.quad	L_.str.20
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	135                             ## 0x87
	.space	4
	.quad	L_.str.21
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	162                             ## 0xa2
	.space	4
	.quad	L_.str.22
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	158                             ## 0x9e
	.space	4
	.quad	L_.str.23
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	141                             ## 0x8d
	.space	4
	.quad	L_.str.24
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	136                             ## 0x88
	.space	4
	.quad	L_.str.25
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	163                             ## 0xa3
	.space	4
	.quad	L_.str.26
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	159                             ## 0x9f
	.space	4
	.quad	L_.str.27
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	138                             ## 0x8a
	.space	4
	.quad	L_.str.28
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	133                             ## 0x85
	.space	4
	.quad	L_.str.29
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	161                             ## 0xa1
	.space	4
	.quad	L_.str.30
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	156                             ## 0x9c
	.space	4
	.quad	L_.str.31
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	145                             ## 0x91
	.space	4
	.quad	L_.str.32
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	144                             ## 0x90
	.space	4
	.quad	L_.str.33
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	130                             ## 0x82
	.space	4
	.quad	L_.str.34
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.long	129                             ## 0x81
	.space	4
	.quad	L_.str.35
	.long	4294967295                      ## 0xffffffff
	.long	1                               ## 0x1
	.space	24

	.section	__TEXT,__cstring,cstring_literals
L_.str.8:                               ## @.str.8
	.asciz	"CIM reserved space access"

L_.str.9:                               ## @.str.9
	.asciz	"CIM illegal transaction"

L_.str.10:                              ## @.str.10
	.asciz	"CIM illegal write"

L_.str.11:                              ## @.str.11
	.asciz	"CIM illegal read"

L_.str.12:                              ## @.str.12
	.asciz	"CIM illegal read BE"

L_.str.13:                              ## @.str.13
	.asciz	"CIM illegal write BE"

L_.str.14:                              ## @.str.14
	.asciz	"CIM single read from boot space"

L_.str.15:                              ## @.str.15
	.asciz	"CIM single write to boot space"

L_.str.16:                              ## @.str.16
	.asciz	"CIM block write to boot space"

L_.str.17:                              ## @.str.17
	.asciz	"CIM single read from flash space"

L_.str.18:                              ## @.str.18
	.asciz	"CIM single write to flash space"

L_.str.19:                              ## @.str.19
	.asciz	"CIM block write to flash space"

L_.str.20:                              ## @.str.20
	.asciz	"CIM single EEPROM read"

L_.str.21:                              ## @.str.21
	.asciz	"CIM single EEPROM write"

L_.str.22:                              ## @.str.22
	.asciz	"CIM block EEPROM read"

L_.str.23:                              ## @.str.23
	.asciz	"CIM block EEPROM write"

L_.str.24:                              ## @.str.24
	.asciz	"CIM single read from CTL space"

L_.str.25:                              ## @.str.25
	.asciz	"CIM single write to CTL space"

L_.str.26:                              ## @.str.26
	.asciz	"CIM block read from CTL space"

L_.str.27:                              ## @.str.27
	.asciz	"CIM block write to CTL space"

L_.str.28:                              ## @.str.28
	.asciz	"CIM single read from PL space"

L_.str.29:                              ## @.str.29
	.asciz	"CIM single write to PL space"

L_.str.30:                              ## @.str.30
	.asciz	"CIM block read from PL space"

L_.str.31:                              ## @.str.31
	.asciz	"CIM block write to PL space"

L_.str.32:                              ## @.str.32
	.asciz	"CIM request FIFO overwrite"

L_.str.33:                              ## @.str.33
	.asciz	"CIM response FIFO overwrite"

L_.str.34:                              ## @.str.34
	.asciz	"CIM PIF timeout"

L_.str.35:                              ## @.str.35
	.asciz	"CIM PIF MA timeout"

	.comm	_PCIE_FW_A,4,2                  ## @PCIE_FW_A
	.comm	_PCIE_FW_ERR_F,4,2              ## @PCIE_FW_ERR_F
	.comm	_CIM_HOST_INT_CAUSE_A,4,2       ## @CIM_HOST_INT_CAUSE_A
	.comm	_PCIE_FW_EVAL_CRASH,8,3         ## @PCIE_FW_EVAL_CRASH
	.comm	_CIM_HOST_UPACC_INT_CAUSE_A,4,2 ## @CIM_HOST_UPACC_INT_CAUSE_A
	.no_dead_strip	_cim_intr_handler
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cim_intr_handler
_cim_intr_handler:                      ; @cim_intr_handler
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, _PCIE_FW_A@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCIE_FW_A@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	bl	_t4_read_reg
	mov	x20, x0
Lloh3:
	adrp	x22, _PCIE_FW_ERR_F@GOTPAGE
Lloh4:
	ldr	x22, [x22, _PCIE_FW_ERR_F@GOTPAGEOFF]
	ldr	w8, [x22]
	tst	w8, w0
	b.eq	LBB0_2
; %bb.1:
	mov	x0, x19
	bl	_t4_report_fw_error
LBB0_2:
Lloh5:
	adrp	x21, _CIM_HOST_INT_CAUSE_A@GOTPAGE
Lloh6:
	ldr	x21, [x21, _CIM_HOST_INT_CAUSE_A@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_t4_read_reg
	tbz	w0, #7, LBB0_6
; %bb.3:
	ldr	w8, [x22]
	tst	w8, w20
	b.eq	LBB0_5
; %bb.4:
	mov	x0, x20
	bl	_PCIE_FW_EVAL_G
Lloh7:
	adrp	x8, _PCIE_FW_EVAL_CRASH@GOTPAGE
Lloh8:
	ldr	x8, [x8, _PCIE_FW_EVAL_CRASH@GOTPAGEOFF]
Lloh9:
	ldr	x8, [x8]
	cmp	x0, x8
	b.eq	LBB0_6
LBB0_5:
	ldr	w1, [x21]
	mov	x0, x19
	mov	w2, #128
	bl	_t4_write_reg
LBB0_6:
	ldr	w1, [x21]
Lloh10:
	adrp	x2, _cim_intr_handler.cim_intr_info@PAGE
Lloh11:
	add	x2, x2, _cim_intr_handler.cim_intr_info@PAGEOFF
	mov	x0, x19
	bl	_t4_handle_intr_status
	mov	x20, x0
Lloh12:
	adrp	x8, _CIM_HOST_UPACC_INT_CAUSE_A@GOTPAGE
Lloh13:
	ldr	x8, [x8, _CIM_HOST_UPACC_INT_CAUSE_A@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
Lloh15:
	adrp	x2, _cim_intr_handler.cim_upintr_info@PAGE
Lloh16:
	add	x2, x2, _cim_intr_handler.cim_upintr_info@PAGEOFF
	mov	x0, x19
	bl	_t4_handle_intr_status
	cmn	w20, w0
	b.ne	LBB0_8
; %bb.7:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_8:
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_t4_fatal_err
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpAdd	Lloh10, Lloh11
	.cfi_endproc
                                        ; -- End function
	.section	__DATA,__const
	.p2align	3                               ; @cim_intr_handler.cim_intr_info
_cim_intr_handler.cim_intr_info:
	.long	146                             ; 0x92
	.space	4
	.quad	l_.str
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	154                             ; 0x9a
	.space	4
	.quad	l_.str.1
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	155                             ; 0x9b
	.space	4
	.quad	l_.str.2
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	147                             ; 0x93
	.space	4
	.quad	l_.str.3
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	148                             ; 0x94
	.space	4
	.quad	l_.str.4
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	132                             ; 0x84
	.space	4
	.quad	l_.str.5
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	131                             ; 0x83
	.space	4
	.quad	l_.str.6
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	128                             ; 0x80
	.space	4
	.quad	l_.str.7
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.space	24

	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"CIM control register prefetch drop"

l_.str.1:                               ; @.str.1
	.asciz	"CIM OBQ parity error"

l_.str.2:                               ; @.str.2
	.asciz	"CIM IBQ parity error"

l_.str.3:                               ; @.str.3
	.asciz	"CIM mailbox uP parity error"

l_.str.4:                               ; @.str.4
	.asciz	"CIM mailbox host parity error"

l_.str.5:                               ; @.str.5
	.asciz	"CIM TIEQ outgoing parity error"

l_.str.6:                               ; @.str.6
	.asciz	"CIM TIEQ incoming parity error"

l_.str.7:                               ; @.str.7
	.asciz	"CIM TIMER0 interrupt"

	.section	__DATA,__const
	.p2align	3                               ; @cim_intr_handler.cim_upintr_info
_cim_intr_handler.cim_upintr_info:
	.long	143                             ; 0x8f
	.space	4
	.quad	l_.str.8
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	151                             ; 0x97
	.space	4
	.quad	l_.str.9
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	149                             ; 0x95
	.space	4
	.quad	l_.str.10
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	152                             ; 0x98
	.space	4
	.quad	l_.str.11
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	153                             ; 0x99
	.space	4
	.quad	l_.str.12
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	150                             ; 0x96
	.space	4
	.quad	l_.str.13
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	142                             ; 0x8e
	.space	4
	.quad	l_.str.14
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	137                             ; 0x89
	.space	4
	.quad	l_.str.15
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	160                             ; 0xa0
	.space	4
	.quad	l_.str.16
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	139                             ; 0x8b
	.space	4
	.quad	l_.str.17
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	134                             ; 0x86
	.space	4
	.quad	l_.str.18
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	157                             ; 0x9d
	.space	4
	.quad	l_.str.19
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	140                             ; 0x8c
	.space	4
	.quad	l_.str.20
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	135                             ; 0x87
	.space	4
	.quad	l_.str.21
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	162                             ; 0xa2
	.space	4
	.quad	l_.str.22
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	158                             ; 0x9e
	.space	4
	.quad	l_.str.23
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	141                             ; 0x8d
	.space	4
	.quad	l_.str.24
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	136                             ; 0x88
	.space	4
	.quad	l_.str.25
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	163                             ; 0xa3
	.space	4
	.quad	l_.str.26
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	159                             ; 0x9f
	.space	4
	.quad	l_.str.27
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	138                             ; 0x8a
	.space	4
	.quad	l_.str.28
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	133                             ; 0x85
	.space	4
	.quad	l_.str.29
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	161                             ; 0xa1
	.space	4
	.quad	l_.str.30
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	156                             ; 0x9c
	.space	4
	.quad	l_.str.31
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	145                             ; 0x91
	.space	4
	.quad	l_.str.32
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	144                             ; 0x90
	.space	4
	.quad	l_.str.33
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	130                             ; 0x82
	.space	4
	.quad	l_.str.34
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	129                             ; 0x81
	.space	4
	.quad	l_.str.35
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.space	24

	.section	__TEXT,__cstring,cstring_literals
l_.str.8:                               ; @.str.8
	.asciz	"CIM reserved space access"

l_.str.9:                               ; @.str.9
	.asciz	"CIM illegal transaction"

l_.str.10:                              ; @.str.10
	.asciz	"CIM illegal write"

l_.str.11:                              ; @.str.11
	.asciz	"CIM illegal read"

l_.str.12:                              ; @.str.12
	.asciz	"CIM illegal read BE"

l_.str.13:                              ; @.str.13
	.asciz	"CIM illegal write BE"

l_.str.14:                              ; @.str.14
	.asciz	"CIM single read from boot space"

l_.str.15:                              ; @.str.15
	.asciz	"CIM single write to boot space"

l_.str.16:                              ; @.str.16
	.asciz	"CIM block write to boot space"

l_.str.17:                              ; @.str.17
	.asciz	"CIM single read from flash space"

l_.str.18:                              ; @.str.18
	.asciz	"CIM single write to flash space"

l_.str.19:                              ; @.str.19
	.asciz	"CIM block write to flash space"

l_.str.20:                              ; @.str.20
	.asciz	"CIM single EEPROM read"

l_.str.21:                              ; @.str.21
	.asciz	"CIM single EEPROM write"

l_.str.22:                              ; @.str.22
	.asciz	"CIM block EEPROM read"

l_.str.23:                              ; @.str.23
	.asciz	"CIM block EEPROM write"

l_.str.24:                              ; @.str.24
	.asciz	"CIM single read from CTL space"

l_.str.25:                              ; @.str.25
	.asciz	"CIM single write to CTL space"

l_.str.26:                              ; @.str.26
	.asciz	"CIM block read from CTL space"

l_.str.27:                              ; @.str.27
	.asciz	"CIM block write to CTL space"

l_.str.28:                              ; @.str.28
	.asciz	"CIM single read from PL space"

l_.str.29:                              ; @.str.29
	.asciz	"CIM single write to PL space"

l_.str.30:                              ; @.str.30
	.asciz	"CIM block read from PL space"

l_.str.31:                              ; @.str.31
	.asciz	"CIM block write to PL space"

l_.str.32:                              ; @.str.32
	.asciz	"CIM request FIFO overwrite"

l_.str.33:                              ; @.str.33
	.asciz	"CIM response FIFO overwrite"

l_.str.34:                              ; @.str.34
	.asciz	"CIM PIF timeout"

l_.str.35:                              ; @.str.35
	.asciz	"CIM PIF MA timeout"

	.comm	_PCIE_FW_A,4,2                  ; @PCIE_FW_A
	.comm	_PCIE_FW_ERR_F,4,2              ; @PCIE_FW_ERR_F
	.comm	_CIM_HOST_INT_CAUSE_A,4,2       ; @CIM_HOST_INT_CAUSE_A
	.comm	_PCIE_FW_EVAL_CRASH,8,3         ; @PCIE_FW_EVAL_CRASH
	.comm	_CIM_HOST_UPACC_INT_CAUSE_A,4,2 ; @CIM_HOST_UPACC_INT_CAUSE_A
	.no_dead_strip	_cim_intr_handler
.subsections_via_symbols
