	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_sdhci_set_uhs_signaling        ## -- Begin function sdhci_set_uhs_signaling
	.p2align	4, 0x90
_sdhci_set_uhs_signaling:               ## @sdhci_set_uhs_signaling
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %ebx
	movq	%rdi, %r14
	movq	_SDHCI_HOST_CONTROL2@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	callq	_sdhci_readw
	movq	_SDHCI_CTRL_UHS_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_MMC_TIMING_MMC_HS200@GOTPCREL(%rip), %rax
	cmpl	%ebx, (%rax)
	je	LBB0_2
## %bb.1:
	movq	_MMC_TIMING_UHS_SDR104@GOTPCREL(%rip), %rax
	cmpl	%ebx, (%rax)
	je	LBB0_2
## %bb.3:
	movq	_MMC_TIMING_UHS_SDR12@GOTPCREL(%rip), %rax
	cmpl	%ebx, (%rax)
	jne	LBB0_5
## %bb.4:
	movq	_SDHCI_CTRL_UHS_SDR12@GOTPCREL(%rip), %rax
	jmp	LBB0_16
LBB0_2:
	movq	_SDHCI_CTRL_UHS_SDR104@GOTPCREL(%rip), %rax
	jmp	LBB0_16
LBB0_5:
	movq	_MMC_TIMING_SD_HS@GOTPCREL(%rip), %rax
	cmpl	%ebx, (%rax)
	je	LBB0_8
## %bb.6:
	movq	_MMC_TIMING_MMC_HS@GOTPCREL(%rip), %rax
	cmpl	%ebx, (%rax)
	je	LBB0_8
## %bb.7:
	movq	_MMC_TIMING_UHS_SDR25@GOTPCREL(%rip), %rax
	cmpl	%ebx, (%rax)
	je	LBB0_8
## %bb.9:
	movq	_MMC_TIMING_UHS_SDR50@GOTPCREL(%rip), %rax
	cmpl	%ebx, (%rax)
	jne	LBB0_11
## %bb.10:
	movq	_SDHCI_CTRL_UHS_SDR50@GOTPCREL(%rip), %rax
	jmp	LBB0_16
LBB0_8:
	movq	_SDHCI_CTRL_UHS_SDR25@GOTPCREL(%rip), %rax
	jmp	LBB0_16
LBB0_11:
	movq	_MMC_TIMING_UHS_DDR50@GOTPCREL(%rip), %rax
	cmpl	%ebx, (%rax)
	je	LBB0_13
## %bb.12:
	movq	_MMC_TIMING_MMC_DDR52@GOTPCREL(%rip), %rax
	cmpl	%ebx, (%rax)
	je	LBB0_13
## %bb.14:
	movq	_MMC_TIMING_MMC_HS400@GOTPCREL(%rip), %rax
	cmpl	%ebx, (%rax)
	jne	LBB0_17
## %bb.15:
	movq	_SDHCI_CTRL_HS400@GOTPCREL(%rip), %rax
	jmp	LBB0_16
LBB0_13:
	movq	_SDHCI_CTRL_UHS_DDR50@GOTPCREL(%rip), %rax
LBB0_16:
	orl	(%rax), %esi
LBB0_17:
	movl	(%r15), %edx
	movq	%r14, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_sdhci_writew                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_SDHCI_HOST_CONTROL2,4,2        ## @SDHCI_HOST_CONTROL2
	.comm	_SDHCI_CTRL_UHS_MASK,4,2        ## @SDHCI_CTRL_UHS_MASK
	.comm	_MMC_TIMING_MMC_HS200,4,2       ## @MMC_TIMING_MMC_HS200
	.comm	_MMC_TIMING_UHS_SDR104,4,2      ## @MMC_TIMING_UHS_SDR104
	.comm	_SDHCI_CTRL_UHS_SDR104,4,2      ## @SDHCI_CTRL_UHS_SDR104
	.comm	_MMC_TIMING_UHS_SDR12,4,2       ## @MMC_TIMING_UHS_SDR12
	.comm	_SDHCI_CTRL_UHS_SDR12,4,2       ## @SDHCI_CTRL_UHS_SDR12
	.comm	_MMC_TIMING_SD_HS,4,2           ## @MMC_TIMING_SD_HS
	.comm	_MMC_TIMING_MMC_HS,4,2          ## @MMC_TIMING_MMC_HS
	.comm	_MMC_TIMING_UHS_SDR25,4,2       ## @MMC_TIMING_UHS_SDR25
	.comm	_SDHCI_CTRL_UHS_SDR25,4,2       ## @SDHCI_CTRL_UHS_SDR25
	.comm	_MMC_TIMING_UHS_SDR50,4,2       ## @MMC_TIMING_UHS_SDR50
	.comm	_SDHCI_CTRL_UHS_SDR50,4,2       ## @SDHCI_CTRL_UHS_SDR50
	.comm	_MMC_TIMING_UHS_DDR50,4,2       ## @MMC_TIMING_UHS_DDR50
	.comm	_MMC_TIMING_MMC_DDR52,4,2       ## @MMC_TIMING_MMC_DDR52
	.comm	_SDHCI_CTRL_UHS_DDR50,4,2       ## @SDHCI_CTRL_UHS_DDR50
	.comm	_MMC_TIMING_MMC_HS400,4,2       ## @MMC_TIMING_MMC_HS400
	.comm	_SDHCI_CTRL_HS400,4,2           ## @SDHCI_CTRL_HS400
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_sdhci_set_uhs_signaling        ; -- Begin function sdhci_set_uhs_signaling
	.p2align	2
_sdhci_set_uhs_signaling:               ; @sdhci_set_uhs_signaling
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x21, _SDHCI_HOST_CONTROL2@GOTPAGE
Lloh1:
	ldr	x21, [x21, _SDHCI_HOST_CONTROL2@GOTPAGEOFF]
	ldr	w1, [x21]
	bl	_sdhci_readw
Lloh2:
	adrp	x8, _SDHCI_CTRL_UHS_MASK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _SDHCI_CTRL_UHS_MASK@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	bic	w1, w0, w8
Lloh5:
	adrp	x8, _MMC_TIMING_MMC_HS200@GOTPAGE
Lloh6:
	ldr	x8, [x8, _MMC_TIMING_MMC_HS200@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
Lloh8:
	adrp	x9, _MMC_TIMING_UHS_SDR104@GOTPAGE
Lloh9:
	ldr	x9, [x9, _MMC_TIMING_UHS_SDR104@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
	cmp	w8, w20
	ccmp	w9, w20, #4, ne
	b.ne	LBB0_2
; %bb.1:
Lloh11:
	adrp	x8, _SDHCI_CTRL_UHS_SDR104@GOTPAGE
Lloh12:
	ldr	x8, [x8, _SDHCI_CTRL_UHS_SDR104@GOTPAGEOFF]
	b	LBB0_13
LBB0_2:
Lloh13:
	adrp	x8, _MMC_TIMING_UHS_SDR12@GOTPAGE
Lloh14:
	ldr	x8, [x8, _MMC_TIMING_UHS_SDR12@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
	cmp	w8, w20
	b.ne	LBB0_4
; %bb.3:
Lloh16:
	adrp	x8, _SDHCI_CTRL_UHS_SDR12@GOTPAGE
Lloh17:
	ldr	x8, [x8, _SDHCI_CTRL_UHS_SDR12@GOTPAGEOFF]
	b	LBB0_13
LBB0_4:
Lloh18:
	adrp	x8, _MMC_TIMING_SD_HS@GOTPAGE
Lloh19:
	ldr	x8, [x8, _MMC_TIMING_SD_HS@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
Lloh21:
	adrp	x9, _MMC_TIMING_MMC_HS@GOTPAGE
Lloh22:
	ldr	x9, [x9, _MMC_TIMING_MMC_HS@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
Lloh24:
	adrp	x10, _MMC_TIMING_UHS_SDR25@GOTPAGE
Lloh25:
	ldr	x10, [x10, _MMC_TIMING_UHS_SDR25@GOTPAGEOFF]
Lloh26:
	ldr	w10, [x10]
	cmp	w8, w20
	ccmp	w9, w20, #4, ne
	ccmp	w10, w20, #4, ne
	b.ne	LBB0_6
; %bb.5:
Lloh27:
	adrp	x8, _SDHCI_CTRL_UHS_SDR25@GOTPAGE
Lloh28:
	ldr	x8, [x8, _SDHCI_CTRL_UHS_SDR25@GOTPAGEOFF]
	b	LBB0_13
LBB0_6:
Lloh29:
	adrp	x8, _MMC_TIMING_UHS_SDR50@GOTPAGE
Lloh30:
	ldr	x8, [x8, _MMC_TIMING_UHS_SDR50@GOTPAGEOFF]
Lloh31:
	ldr	w8, [x8]
	cmp	w8, w20
	b.ne	LBB0_8
; %bb.7:
Lloh32:
	adrp	x8, _SDHCI_CTRL_UHS_SDR50@GOTPAGE
Lloh33:
	ldr	x8, [x8, _SDHCI_CTRL_UHS_SDR50@GOTPAGEOFF]
	b	LBB0_13
LBB0_8:
Lloh34:
	adrp	x8, _MMC_TIMING_UHS_DDR50@GOTPAGE
Lloh35:
	ldr	x8, [x8, _MMC_TIMING_UHS_DDR50@GOTPAGEOFF]
Lloh36:
	ldr	w8, [x8]
	cmp	w8, w20
	b.eq	LBB0_12
; %bb.9:
Lloh37:
	adrp	x8, _MMC_TIMING_MMC_DDR52@GOTPAGE
Lloh38:
	ldr	x8, [x8, _MMC_TIMING_MMC_DDR52@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
	cmp	w8, w20
	b.eq	LBB0_12
; %bb.10:
Lloh40:
	adrp	x8, _MMC_TIMING_MMC_HS400@GOTPAGE
Lloh41:
	ldr	x8, [x8, _MMC_TIMING_MMC_HS400@GOTPAGEOFF]
Lloh42:
	ldr	w8, [x8]
	cmp	w8, w20
	b.ne	LBB0_14
; %bb.11:
Lloh43:
	adrp	x8, _SDHCI_CTRL_HS400@GOTPAGE
Lloh44:
	ldr	x8, [x8, _SDHCI_CTRL_HS400@GOTPAGEOFF]
	b	LBB0_13
LBB0_12:
Lloh45:
	adrp	x8, _SDHCI_CTRL_UHS_DDR50@GOTPAGE
Lloh46:
	ldr	x8, [x8, _SDHCI_CTRL_UHS_DDR50@GOTPAGEOFF]
LBB0_13:
	ldr	w8, [x8]
	orr	w1, w8, w1
LBB0_14:
	ldr	w2, [x21]
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_sdhci_writew
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh45, Lloh46
	.cfi_endproc
                                        ; -- End function
	.comm	_SDHCI_HOST_CONTROL2,4,2        ; @SDHCI_HOST_CONTROL2
	.comm	_SDHCI_CTRL_UHS_MASK,4,2        ; @SDHCI_CTRL_UHS_MASK
	.comm	_MMC_TIMING_MMC_HS200,4,2       ; @MMC_TIMING_MMC_HS200
	.comm	_MMC_TIMING_UHS_SDR104,4,2      ; @MMC_TIMING_UHS_SDR104
	.comm	_SDHCI_CTRL_UHS_SDR104,4,2      ; @SDHCI_CTRL_UHS_SDR104
	.comm	_MMC_TIMING_UHS_SDR12,4,2       ; @MMC_TIMING_UHS_SDR12
	.comm	_SDHCI_CTRL_UHS_SDR12,4,2       ; @SDHCI_CTRL_UHS_SDR12
	.comm	_MMC_TIMING_SD_HS,4,2           ; @MMC_TIMING_SD_HS
	.comm	_MMC_TIMING_MMC_HS,4,2          ; @MMC_TIMING_MMC_HS
	.comm	_MMC_TIMING_UHS_SDR25,4,2       ; @MMC_TIMING_UHS_SDR25
	.comm	_SDHCI_CTRL_UHS_SDR25,4,2       ; @SDHCI_CTRL_UHS_SDR25
	.comm	_MMC_TIMING_UHS_SDR50,4,2       ; @MMC_TIMING_UHS_SDR50
	.comm	_SDHCI_CTRL_UHS_SDR50,4,2       ; @SDHCI_CTRL_UHS_SDR50
	.comm	_MMC_TIMING_UHS_DDR50,4,2       ; @MMC_TIMING_UHS_DDR50
	.comm	_MMC_TIMING_MMC_DDR52,4,2       ; @MMC_TIMING_MMC_DDR52
	.comm	_SDHCI_CTRL_UHS_DDR50,4,2       ; @SDHCI_CTRL_UHS_DDR50
	.comm	_MMC_TIMING_MMC_HS400,4,2       ; @MMC_TIMING_MMC_HS400
	.comm	_SDHCI_CTRL_HS400,4,2           ; @SDHCI_CTRL_HS400
.subsections_via_symbols
