	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function xgene_xgmac_init
_xgene_xgmac_init:                      ## @xgene_xgmac_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	callq	_xgene_xgmac_reset
	movq	_AXGMAC_CONFIG_1@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_xgene_enet_rd_mac
	movq	_HSTPPEN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_HSTLENCHK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movl	%edx, -28(%rbp)
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_xgene_enet_wr_mac
	movq	%rbx, %rdi
	callq	_xgene_xgmac_set_mac_addr
	movq	_XG_RSIF_CONFIG_REG_ADDR@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	leaq	-28(%rbp), %r14
	movq	%rbx, %rdi
	movq	%r14, %rdx
	callq	_xgene_enet_rd_csr
	movq	_CFG_RSIF_FPBUFF_TIMEOUT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, -28(%rbp)
	movq	_XG_RSIF_CLE_BUFF_THRESH@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_RSIF_CLE_BUFF_THRESH_SET
	movl	(%r15), %esi
	movl	-28(%rbp), %edx
	movq	%rbx, %rdi
	callq	_xgene_enet_wr_csr
	movq	_XG_RSIF_CONFIG1_REG_ADDR@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	callq	_xgene_enet_rd_csr
	movq	_XG_RSIF_PLC_CLE_BUFF_THRESH@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_RSIF_PLC_CLE_BUFF_THRESH_SET
	movl	(%r15), %esi
	movl	-28(%rbp), %edx
	movq	%rbx, %rdi
	callq	_xgene_enet_wr_csr
	movq	_XG_ENET_SPARE_CFG_REG_ADDR@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	callq	_xgene_enet_rd_csr
	movl	$12, %edi
	callq	_BIT
	orl	-28(%rbp), %eax
	movl	%eax, -28(%rbp)
	movl	(%r15), %esi
	movq	%rbx, %rdi
	movl	%eax, %edx
	callq	_xgene_enet_wr_csr
	movq	_XG_ENET_SPARE_CFG_REG_1_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$130, %edx
	callq	_xgene_enet_wr_csr
	movq	_XGENET_RX_DV_GATE_REG_0_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_xgene_enet_wr_csr
	movq	_XG_CFG_BYPASS_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_RESUME_TX@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_xgene_enet_wr_csr
	movq	_XGENET_CSR_MULTI_DPF0_ADDR@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	callq	_xgene_enet_rd_axg_csr
	movq	_DEF_QUANTA@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	shll	$16, %eax
	movzwl	-28(%rbp), %edx
	orl	%eax, %edx
	movl	%edx, -28(%rbp)
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_xgene_enet_wr_axg_csr
	movq	(%rbx), %rax
	movq	_XGENE_ENET1@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_2
## %bb.1:
	movq	_XGENET_CSR_MULTI_DPF1_ADDR@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	leaq	-28(%rbp), %rdx
	movq	%rbx, %rdi
	callq	_xgene_enet_rd_axg_csr
	movq	_NORM_PAUSE_OPCODE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	shll	$16, %eax
	movzwl	-28(%rbp), %edx
	orl	%eax, %edx
	movl	%edx, -28(%rbp)
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_xgene_enet_wr_axg_csr
LBB0_2:
	movq	_XG_DEF_PAUSE_OFF_THRES@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	shll	$16, %edx
	movq	_XG_DEF_PAUSE_THRES@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	%edx, -28(%rbp)
	movq	_XG_RXBUF_PAUSE_THRESH@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_xgene_enet_wr_csr
	movl	12(%rbx), %esi
	movq	%rbx, %rdi
	callq	_xgene_xgmac_flowctl_tx
	movl	8(%rbx), %esi
	movq	%rbx, %rdi
	callq	_xgene_xgmac_flowctl_rx
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AXGMAC_CONFIG_1,4,2            ## @AXGMAC_CONFIG_1
	.comm	_HSTPPEN,4,2                    ## @HSTPPEN
	.comm	_HSTLENCHK,4,2                  ## @HSTLENCHK
	.comm	_XG_RSIF_CONFIG_REG_ADDR,4,2    ## @XG_RSIF_CONFIG_REG_ADDR
	.comm	_CFG_RSIF_FPBUFF_TIMEOUT_EN,4,2 ## @CFG_RSIF_FPBUFF_TIMEOUT_EN
	.comm	_XG_RSIF_CLE_BUFF_THRESH,4,2    ## @XG_RSIF_CLE_BUFF_THRESH
	.comm	_XG_RSIF_CONFIG1_REG_ADDR,4,2   ## @XG_RSIF_CONFIG1_REG_ADDR
	.comm	_XG_RSIF_PLC_CLE_BUFF_THRESH,4,2 ## @XG_RSIF_PLC_CLE_BUFF_THRESH
	.comm	_XG_ENET_SPARE_CFG_REG_ADDR,4,2 ## @XG_ENET_SPARE_CFG_REG_ADDR
	.comm	_XG_ENET_SPARE_CFG_REG_1_ADDR,4,2 ## @XG_ENET_SPARE_CFG_REG_1_ADDR
	.comm	_XGENET_RX_DV_GATE_REG_0_ADDR,4,2 ## @XGENET_RX_DV_GATE_REG_0_ADDR
	.comm	_XG_CFG_BYPASS_ADDR,4,2         ## @XG_CFG_BYPASS_ADDR
	.comm	_RESUME_TX,4,2                  ## @RESUME_TX
	.comm	_XGENET_CSR_MULTI_DPF0_ADDR,4,2 ## @XGENET_CSR_MULTI_DPF0_ADDR
	.comm	_DEF_QUANTA,4,2                 ## @DEF_QUANTA
	.comm	_XGENE_ENET1,8,3                ## @XGENE_ENET1
	.comm	_XGENET_CSR_MULTI_DPF1_ADDR,4,2 ## @XGENET_CSR_MULTI_DPF1_ADDR
	.comm	_NORM_PAUSE_OPCODE,4,2          ## @NORM_PAUSE_OPCODE
	.comm	_XG_DEF_PAUSE_OFF_THRES,4,2     ## @XG_DEF_PAUSE_OFF_THRES
	.comm	_XG_DEF_PAUSE_THRES,4,2         ## @XG_DEF_PAUSE_THRES
	.comm	_XG_RXBUF_PAUSE_THRESH,4,2      ## @XG_RXBUF_PAUSE_THRESH
	.no_dead_strip	_xgene_xgmac_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function xgene_xgmac_init
_xgene_xgmac_init:                      ; @xgene_xgmac_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #48
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_xgene_xgmac_reset
Lloh0:
	adrp	x20, _AXGMAC_CONFIG_1@GOTPAGE
Lloh1:
	ldr	x20, [x20, _AXGMAC_CONFIG_1@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_xgene_enet_rd_mac
Lloh2:
	adrp	x8, _HSTPPEN@GOTPAGE
Lloh3:
	ldr	x8, [x8, _HSTPPEN@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh5:
	adrp	x9, _HSTLENCHK@GOTPAGE
Lloh6:
	ldr	x9, [x9, _HSTLENCHK@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	bic	w2, w8, w9
	str	w2, [sp, #12]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_xgene_enet_wr_mac
	mov	x0, x19
	bl	_xgene_xgmac_set_mac_addr
Lloh8:
	adrp	x20, _XG_RSIF_CONFIG_REG_ADDR@GOTPAGE
Lloh9:
	ldr	x20, [x20, _XG_RSIF_CONFIG_REG_ADDR@GOTPAGEOFF]
	ldr	w1, [x20]
	add	x2, sp, #12
	mov	x0, x19
	bl	_xgene_enet_rd_csr
Lloh10:
	adrp	x8, _CFG_RSIF_FPBUFF_TIMEOUT_EN@GOTPAGE
Lloh11:
	ldr	x8, [x8, _CFG_RSIF_FPBUFF_TIMEOUT_EN@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	orr	w8, w9, w8
	str	w8, [sp, #12]
Lloh13:
	adrp	x8, _XG_RSIF_CLE_BUFF_THRESH@GOTPAGE
Lloh14:
	ldr	x8, [x8, _XG_RSIF_CLE_BUFF_THRESH@GOTPAGEOFF]
Lloh15:
	ldr	w1, [x8]
	add	x0, sp, #12
	bl	_RSIF_CLE_BUFF_THRESH_SET
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_xgene_enet_wr_csr
Lloh16:
	adrp	x20, _XG_RSIF_CONFIG1_REG_ADDR@GOTPAGE
Lloh17:
	ldr	x20, [x20, _XG_RSIF_CONFIG1_REG_ADDR@GOTPAGEOFF]
	ldr	w1, [x20]
	add	x2, sp, #12
	mov	x0, x19
	bl	_xgene_enet_rd_csr
Lloh18:
	adrp	x8, _XG_RSIF_PLC_CLE_BUFF_THRESH@GOTPAGE
Lloh19:
	ldr	x8, [x8, _XG_RSIF_PLC_CLE_BUFF_THRESH@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	add	x0, sp, #12
	bl	_RSIF_PLC_CLE_BUFF_THRESH_SET
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_xgene_enet_wr_csr
Lloh21:
	adrp	x20, _XG_ENET_SPARE_CFG_REG_ADDR@GOTPAGE
Lloh22:
	ldr	x20, [x20, _XG_ENET_SPARE_CFG_REG_ADDR@GOTPAGEOFF]
	ldr	w1, [x20]
	add	x2, sp, #12
	mov	x0, x19
	bl	_xgene_enet_rd_csr
	mov	w0, #12
	bl	_BIT
	ldr	w8, [sp, #12]
	orr	w2, w8, w0
	str	w2, [sp, #12]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_xgene_enet_wr_csr
Lloh23:
	adrp	x8, _XG_ENET_SPARE_CFG_REG_1_ADDR@GOTPAGE
Lloh24:
	ldr	x8, [x8, _XG_ENET_SPARE_CFG_REG_1_ADDR@GOTPAGEOFF]
Lloh25:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #130
	bl	_xgene_enet_wr_csr
Lloh26:
	adrp	x8, _XGENET_RX_DV_GATE_REG_0_ADDR@GOTPAGE
Lloh27:
	ldr	x8, [x8, _XGENET_RX_DV_GATE_REG_0_ADDR@GOTPAGEOFF]
Lloh28:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_xgene_enet_wr_csr
Lloh29:
	adrp	x8, _XG_CFG_BYPASS_ADDR@GOTPAGE
Lloh30:
	ldr	x8, [x8, _XG_CFG_BYPASS_ADDR@GOTPAGEOFF]
Lloh31:
	ldr	w1, [x8]
Lloh32:
	adrp	x8, _RESUME_TX@GOTPAGE
Lloh33:
	ldr	x8, [x8, _RESUME_TX@GOTPAGEOFF]
Lloh34:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_xgene_enet_wr_csr
Lloh35:
	adrp	x20, _XGENET_CSR_MULTI_DPF0_ADDR@GOTPAGE
Lloh36:
	ldr	x20, [x20, _XGENET_CSR_MULTI_DPF0_ADDR@GOTPAGEOFF]
	ldr	w1, [x20]
	add	x2, sp, #12
	mov	x0, x19
	bl	_xgene_enet_rd_axg_csr
Lloh37:
	adrp	x8, _DEF_QUANTA@GOTPAGE
Lloh38:
	ldr	x8, [x8, _DEF_QUANTA@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
	ldrh	w2, [sp, #12]
	bfi	w2, w8, #16, #16
	str	w2, [sp, #12]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_xgene_enet_wr_axg_csr
	ldr	x8, [x19]
Lloh40:
	adrp	x9, _XGENE_ENET1@GOTPAGE
Lloh41:
	ldr	x9, [x9, _XGENE_ENET1@GOTPAGEOFF]
Lloh42:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_2
; %bb.1:
Lloh43:
	adrp	x20, _XGENET_CSR_MULTI_DPF1_ADDR@GOTPAGE
Lloh44:
	ldr	x20, [x20, _XGENET_CSR_MULTI_DPF1_ADDR@GOTPAGEOFF]
	ldr	w1, [x20]
	add	x2, sp, #12
	mov	x0, x19
	bl	_xgene_enet_rd_axg_csr
Lloh45:
	adrp	x8, _NORM_PAUSE_OPCODE@GOTPAGE
Lloh46:
	ldr	x8, [x8, _NORM_PAUSE_OPCODE@GOTPAGEOFF]
Lloh47:
	ldr	w8, [x8]
	ldrh	w2, [sp, #12]
	bfi	w2, w8, #16, #16
	str	w2, [sp, #12]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_xgene_enet_wr_axg_csr
LBB0_2:
Lloh48:
	adrp	x8, _XG_DEF_PAUSE_OFF_THRES@GOTPAGE
Lloh49:
	ldr	x8, [x8, _XG_DEF_PAUSE_OFF_THRES@GOTPAGEOFF]
Lloh50:
	ldr	w8, [x8]
Lloh51:
	adrp	x9, _XG_DEF_PAUSE_THRES@GOTPAGE
Lloh52:
	ldr	x9, [x9, _XG_DEF_PAUSE_THRES@GOTPAGEOFF]
Lloh53:
	ldr	w9, [x9]
	orr	w2, w9, w8, lsl #16
	str	w2, [sp, #12]
Lloh54:
	adrp	x8, _XG_RXBUF_PAUSE_THRESH@GOTPAGE
Lloh55:
	ldr	x8, [x8, _XG_RXBUF_PAUSE_THRESH@GOTPAGEOFF]
Lloh56:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_xgene_enet_wr_csr
	ldr	w1, [x19, #12]
	mov	x0, x19
	bl	_xgene_xgmac_flowctl_tx
	ldr	w1, [x19, #8]
	mov	x0, x19
	bl	_xgene_xgmac_flowctl_rx
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	ret
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.cfi_endproc
                                        ; -- End function
	.comm	_AXGMAC_CONFIG_1,4,2            ; @AXGMAC_CONFIG_1
	.comm	_HSTPPEN,4,2                    ; @HSTPPEN
	.comm	_HSTLENCHK,4,2                  ; @HSTLENCHK
	.comm	_XG_RSIF_CONFIG_REG_ADDR,4,2    ; @XG_RSIF_CONFIG_REG_ADDR
	.comm	_CFG_RSIF_FPBUFF_TIMEOUT_EN,4,2 ; @CFG_RSIF_FPBUFF_TIMEOUT_EN
	.comm	_XG_RSIF_CLE_BUFF_THRESH,4,2    ; @XG_RSIF_CLE_BUFF_THRESH
	.comm	_XG_RSIF_CONFIG1_REG_ADDR,4,2   ; @XG_RSIF_CONFIG1_REG_ADDR
	.comm	_XG_RSIF_PLC_CLE_BUFF_THRESH,4,2 ; @XG_RSIF_PLC_CLE_BUFF_THRESH
	.comm	_XG_ENET_SPARE_CFG_REG_ADDR,4,2 ; @XG_ENET_SPARE_CFG_REG_ADDR
	.comm	_XG_ENET_SPARE_CFG_REG_1_ADDR,4,2 ; @XG_ENET_SPARE_CFG_REG_1_ADDR
	.comm	_XGENET_RX_DV_GATE_REG_0_ADDR,4,2 ; @XGENET_RX_DV_GATE_REG_0_ADDR
	.comm	_XG_CFG_BYPASS_ADDR,4,2         ; @XG_CFG_BYPASS_ADDR
	.comm	_RESUME_TX,4,2                  ; @RESUME_TX
	.comm	_XGENET_CSR_MULTI_DPF0_ADDR,4,2 ; @XGENET_CSR_MULTI_DPF0_ADDR
	.comm	_DEF_QUANTA,4,2                 ; @DEF_QUANTA
	.comm	_XGENE_ENET1,8,3                ; @XGENE_ENET1
	.comm	_XGENET_CSR_MULTI_DPF1_ADDR,4,2 ; @XGENET_CSR_MULTI_DPF1_ADDR
	.comm	_NORM_PAUSE_OPCODE,4,2          ; @NORM_PAUSE_OPCODE
	.comm	_XG_DEF_PAUSE_OFF_THRES,4,2     ; @XG_DEF_PAUSE_OFF_THRES
	.comm	_XG_DEF_PAUSE_THRES,4,2         ; @XG_DEF_PAUSE_THRES
	.comm	_XG_RXBUF_PAUSE_THRESH,4,2      ; @XG_RXBUF_PAUSE_THRESH
	.no_dead_strip	_xgene_xgmac_init
.subsections_via_symbols
