	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function cxgb4_get_entity_length
_cxgb4_get_entity_length:               ## @cxgb4_get_entity_length
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	subq	$16, %rsp
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
                                        ## kill: def $esi killed $esi def $rsi
	movq	$0, -32(%rbp)
	movl	$0, -20(%rbp)
	xorl	%ebx, %ebx
	addl	$-128, %esi
	cmpl	$51, %esi
	ja	LBB0_72
## %bb.1:
	movq	%rdi, %r14
	leaq	LJTI0_0(%rip), %rax
	movslq	(%rax,%rsi,4), %rcx
	addq	%rax, %rcx
	jmpq	*%rcx
LBB0_2:
	movl	$4, -20(%rbp)
	movl	$4, %ebx
	jmp	LBB0_72
LBB0_3:
	movq	_CIM_IBQ_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	shll	$4, %ebx
	jmp	LBB0_72
LBB0_4:
	movl	$8, -20(%rbp)
	movl	$8, %ebx
	jmp	LBB0_72
LBB0_5:
	movl	4(%r14), %edi
	callq	_is_t5
	testl	%eax, %eax
	jne	LBB0_7
## %bb.6:
	movl	4(%r14), %edi
	callq	_is_t6
	testl	%eax, %eax
	je	LBB0_73
LBB0_7:
	movq	_IREG_NUM_ELEM@GOTPCREL(%rip), %rax
	movslq	(%rax), %rax
	leaq	4(,%rax,4), %rcx
	cmpq	$4, %rcx
	ja	LBB0_69
## %bb.8:
	movl	$4, %eax
	xorl	%edx, %edx
	divl	%ecx
	movl	%eax, %ebx
	jmp	LBB0_70
LBB0_9:
	movq	_TPLA_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	leal	4(,%rax,4), %ebx
	jmp	LBB0_71
LBB0_10:
	movl	4(%r14), %edi
	callq	_CHELSIO_CHIP_VERSION
	andl	$-2, %eax
	xorl	%ebx, %ebx
	cmpl	$180, %eax
	movl	$12, %eax
	cmovneq	%rbx, %rax
	movq	_IREG_NUM_ELEM@GOTPCREL(%rip), %rcx
	movslq	(%rcx), %rcx
	shlq	$2, %rcx
	cmpq	%rcx, %rax
	jb	LBB0_70
## %bb.11:
                                        ## kill: def $eax killed $eax killed $rax
	jmp	LBB0_37
LBB0_12:
	movl	$12, -20(%rbp)
	movl	$12, %ebx
	jmp	LBB0_72
LBB0_13:
	movl	8(%r14), %ebx
	jmp	LBB0_70
LBB0_14:
	movq	%r14, %rdi
	callq	_t4_chip_rss_size
	jmp	LBB0_38
LBB0_15:
	movl	4(%r14), %edi
	callq	_CHELSIO_CHIP_VERSION
                                        ## kill: def $eax killed $eax def $rax
	leal	-180(%rax), %ecx
	cmpl	$2, %ecx
	jae	LBB0_65
## %bb.16:
	movq	_T5_REGMAP_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	jmp	LBB0_72
LBB0_17:
	leaq	-20(%rbp), %rdx
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_cudbg_fill_qdesc_num_and_size
	movl	-20(%rbp), %ebx
	jmp	LBB0_72
LBB0_21:
	movq	_CUDBG_NUM_PCIE_CONFIG_REGS@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	jmp	LBB0_70
LBB0_22:
	movq	_NMTUS@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	jmp	LBB0_70
LBB0_23:
	movl	12(%r14), %ebx
	jmp	LBB0_70
LBB0_24:
	movq	_MA_TARGET_MEM_ENABLE_A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_t4_read_reg
	movq	_EXT_MEM1_ENABLE_F@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	jne	LBB0_40
	jmp	LBB0_25
LBB0_26:
	movq	_MA_TARGET_MEM_ENABLE_A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_t4_read_reg
	movq	_EXT_MEM0_ENABLE_F@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_25
## %bb.27:
	movq	_MA_EXT_MEMORY0_BAR_A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_t4_read_reg
	movl	%eax, %edi
	callq	_EXT_MEM0_SIZE_G
	jmp	LBB0_45
LBB0_28:
	movq	24(%r14), %rax
	movl	(%rax), %ebx
	jmp	LBB0_70
LBB0_29:
	movl	4(%r14), %edi
	callq	_CHELSIO_CHIP_VERSION
	cmpl	$182, %eax
	jl	LBB0_72
LBB0_19:
	movq	_IREG_NUM_ELEM@GOTPCREL(%rip), %rax
	movslq	(%rax), %rcx
	shlq	$2, %rcx
	cmpq	$4, %rcx
	ja	LBB0_20
## %bb.31:
	movl	$4, %eax
	xorl	%edx, %edx
	divl	%ecx
	movl	%eax, %ebx
	jmp	LBB0_32
LBB0_20:
	xorl	%ebx, %ebx
LBB0_32:
	shll	$3, %ebx
	jmp	LBB0_71
LBB0_33:
	leaq	-32(%rbp), %rsi
	movq	%r14, %rdi
	callq	_cudbg_fill_le_tcam_info
	movl	-32(%rbp), %eax
	leal	8(,%rax,4), %ebx
	jmp	LBB0_71
LBB0_34:
	movl	4(%r14), %edi
	callq	_CHELSIO_CHIP_VERSION
	cmpl	$182, %eax
	jl	LBB0_72
## %bb.35:
	movq	_IREG_NUM_ELEM@GOTPCREL(%rip), %rax
	movslq	(%rax), %rcx
	shlq	$2, %rcx
	cmpq	$4, %rcx
	ja	LBB0_69
## %bb.36:
	movl	$4, %eax
LBB0_37:
	xorl	%edx, %edx
	divl	%ecx
LBB0_38:
	movl	%eax, %ebx
	jmp	LBB0_70
LBB0_39:
	movq	_MA_TARGET_MEM_ENABLE_A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_t4_read_reg
	movq	_HMA_MUX_F@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_25
LBB0_40:
	movq	_MA_EXT_MEMORY1_BAR_A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_t4_read_reg
	movl	%eax, %edi
	callq	_EXT_MEM1_SIZE_G
	jmp	LBB0_45
LBB0_41:
	movq	_MA_TARGET_MEM_ENABLE_A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_t4_read_reg
	movq	_EDRAM1_ENABLE_F@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_25
## %bb.42:
	movq	_MA_EDRAM1_BAR_A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_t4_read_reg
	movl	%eax, %edi
	callq	_EDRAM1_SIZE_G
	jmp	LBB0_45
LBB0_43:
	movq	_MA_TARGET_MEM_ENABLE_A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_t4_read_reg
	movq	_EDRAM0_ENABLE_F@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_25
## %bb.44:
	movq	_MA_EDRAM0_BAR_A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_t4_read_reg
	movl	%eax, %edi
	callq	_EDRAM0_SIZE_G
LBB0_45:
	movl	%eax, %edi
	jmp	LBB0_46
LBB0_25:
	xorl	%edi, %edi
LBB0_46:
	callq	_cudbg_mbytes_to_bytes
LBB0_47:
	movl	%eax, %ebx
	movl	%eax, -20(%rbp)
	jmp	LBB0_72
LBB0_48:
	movq	%r14, %rdi
	callq	_cudbg_dump_context_size
	jmp	LBB0_47
LBB0_49:
	movl	16(%r14), %ebx
	jmp	LBB0_72
LBB0_50:
	movl	$4, %ebx
	jmp	LBB0_72
LBB0_51:
	movq	_CIM_PIFLA_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	shll	$4, %eax
	leal	(%rax,%rax,2), %ebx
	orl	$4, %ebx
	jmp	LBB0_71
LBB0_52:
	movq	%r14, %rdi
	movl	$3, %esi
	jmp	LBB0_60
LBB0_53:
	movq	%r14, %rdi
	movl	$2, %esi
	jmp	LBB0_60
LBB0_54:
	movq	%r14, %rdi
	movl	$1, %esi
	jmp	LBB0_60
LBB0_55:
	movq	%r14, %rdi
	xorl	%esi, %esi
	jmp	LBB0_60
LBB0_56:
	movq	%r14, %rdi
	movl	$4, %esi
	jmp	LBB0_60
LBB0_57:
	movq	%r14, %rdi
	movl	$7, %esi
	callq	_cudbg_cim_obq_size
	jmp	LBB0_47
LBB0_58:
	movq	%r14, %rdi
	movl	$6, %esi
	jmp	LBB0_60
LBB0_59:
	movq	%r14, %rdi
	movl	$5, %esi
LBB0_60:
	addq	$16, %rsp
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_cudbg_cim_obq_size             ## TAILCALL
LBB0_61:
	movq	_CIM_MALA_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	shll	$3, %eax
	leal	(%rax,%rax,4), %ebx
	jmp	LBB0_72
LBB0_62:
	movl	4(%r14), %edi
	callq	_is_t6
	movl	(%r14), %ecx
	testl	%eax, %eax
	je	LBB0_68
## %bb.63:
	movslq	%ecx, %rax
	imulq	$1717986919, %rax, %rax         ## imm = 0x66666667
	movq	%rax, %rcx
	shrq	$63, %rcx
	sarq	$34, %rax
	addl	%ecx, %eax
	leal	(%rax,%rax,4), %eax
	leal	40(,%rax,8), %ebx
	addl	$4, %ebx
	jmp	LBB0_72
LBB0_64:
	movq	_NMTUS@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_NCCTRL_WIN@GOTPCREL(%rip), %rax
	imull	(%rax), %ebx
	jmp	LBB0_70
LBB0_69:
	xorl	%ebx, %ebx
LBB0_70:
	shll	$2, %ebx
LBB0_71:
	movl	%ebx, -20(%rbp)
LBB0_72:
	movl	%ebx, %eax
	addq	$16, %rsp
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
LBB0_65:
	cmpl	$182, %eax
	jne	LBB0_72
## %bb.66:
	movq	_T4_REGMAP_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	jmp	LBB0_72
LBB0_68:
	leal	7(%rcx), %ebx
	testl	%ecx, %ecx
	cmovnsl	%ecx, %ebx
	shll	$2, %ebx
	andl	$-32, %ebx
	addl	$4, %ebx
	jmp	LBB0_72
LBB0_73:
	xorl	%ebx, %ebx
	jmp	LBB0_71
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_2, LBB0_2-LJTI0_0
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_4, LBB0_4-LJTI0_0
.set L0_0_set_9, LBB0_9-LJTI0_0
.set L0_0_set_10, LBB0_10-LJTI0_0
.set L0_0_set_12, LBB0_12-LJTI0_0
.set L0_0_set_13, LBB0_13-LJTI0_0
.set L0_0_set_14, LBB0_14-LJTI0_0
.set L0_0_set_15, LBB0_15-LJTI0_0
.set L0_0_set_17, LBB0_17-LJTI0_0
.set L0_0_set_19, LBB0_19-LJTI0_0
.set L0_0_set_21, LBB0_21-LJTI0_0
.set L0_0_set_22, LBB0_22-LJTI0_0
.set L0_0_set_23, LBB0_23-LJTI0_0
.set L0_0_set_24, LBB0_24-LJTI0_0
.set L0_0_set_26, LBB0_26-LJTI0_0
.set L0_0_set_28, LBB0_28-LJTI0_0
.set L0_0_set_29, LBB0_29-LJTI0_0
.set L0_0_set_33, LBB0_33-LJTI0_0
.set L0_0_set_34, LBB0_34-LJTI0_0
.set L0_0_set_39, LBB0_39-LJTI0_0
.set L0_0_set_41, LBB0_41-LJTI0_0
.set L0_0_set_43, LBB0_43-LJTI0_0
.set L0_0_set_48, LBB0_48-LJTI0_0
.set L0_0_set_49, LBB0_49-LJTI0_0
.set L0_0_set_50, LBB0_50-LJTI0_0
.set L0_0_set_51, LBB0_51-LJTI0_0
.set L0_0_set_52, LBB0_52-LJTI0_0
.set L0_0_set_53, LBB0_53-LJTI0_0
.set L0_0_set_54, LBB0_54-LJTI0_0
.set L0_0_set_55, LBB0_55-LJTI0_0
.set L0_0_set_56, LBB0_56-LJTI0_0
.set L0_0_set_57, LBB0_57-LJTI0_0
.set L0_0_set_58, LBB0_58-LJTI0_0
.set L0_0_set_59, LBB0_59-LJTI0_0
.set L0_0_set_61, LBB0_61-LJTI0_0
.set L0_0_set_62, LBB0_62-LJTI0_0
.set L0_0_set_3, LBB0_3-LJTI0_0
.set L0_0_set_64, LBB0_64-LJTI0_0
LJTI0_0:
	.long	L0_0_set_2
	.long	L0_0_set_5
	.long	L0_0_set_4
	.long	L0_0_set_2
	.long	L0_0_set_9
	.long	L0_0_set_10
	.long	L0_0_set_2
	.long	L0_0_set_12
	.long	L0_0_set_13
	.long	L0_0_set_14
	.long	L0_0_set_15
	.long	L0_0_set_17
	.long	L0_0_set_2
	.long	L0_0_set_19
	.long	L0_0_set_19
	.long	L0_0_set_21
	.long	L0_0_set_2
	.long	L0_0_set_22
	.long	L0_0_set_23
	.long	L0_0_set_4
	.long	L0_0_set_24
	.long	L0_0_set_26
	.long	L0_0_set_28
	.long	L0_0_set_29
	.long	L0_0_set_33
	.long	L0_0_set_2
	.long	L0_0_set_34
	.long	L0_0_set_39
	.long	L0_0_set_41
	.long	L0_0_set_43
	.long	L0_0_set_48
	.long	L0_0_set_49
	.long	L0_0_set_2
	.long	L0_0_set_50
	.long	L0_0_set_51
	.long	L0_0_set_52
	.long	L0_0_set_53
	.long	L0_0_set_54
	.long	L0_0_set_55
	.long	L0_0_set_56
	.long	L0_0_set_57
	.long	L0_0_set_58
	.long	L0_0_set_59
	.long	L0_0_set_61
	.long	L0_0_set_62
	.long	L0_0_set_3
	.long	L0_0_set_3
	.long	L0_0_set_3
	.long	L0_0_set_3
	.long	L0_0_set_3
	.long	L0_0_set_3
	.long	L0_0_set_64
	.end_data_region
                                        ## -- End function
	.comm	_T4_REGMAP_SIZE,4,2             ## @T4_REGMAP_SIZE
	.comm	_T5_REGMAP_SIZE,4,2             ## @T5_REGMAP_SIZE
	.comm	_CIM_MALA_SIZE,4,2              ## @CIM_MALA_SIZE
	.comm	_CIM_IBQ_SIZE,4,2               ## @CIM_IBQ_SIZE
	.comm	_MA_TARGET_MEM_ENABLE_A,4,2     ## @MA_TARGET_MEM_ENABLE_A
	.comm	_EDRAM0_ENABLE_F,4,2            ## @EDRAM0_ENABLE_F
	.comm	_MA_EDRAM0_BAR_A,4,2            ## @MA_EDRAM0_BAR_A
	.comm	_EDRAM1_ENABLE_F,4,2            ## @EDRAM1_ENABLE_F
	.comm	_MA_EDRAM1_BAR_A,4,2            ## @MA_EDRAM1_BAR_A
	.comm	_EXT_MEM0_ENABLE_F,4,2          ## @EXT_MEM0_ENABLE_F
	.comm	_MA_EXT_MEMORY0_BAR_A,4,2       ## @MA_EXT_MEMORY0_BAR_A
	.comm	_EXT_MEM1_ENABLE_F,4,2          ## @EXT_MEM1_ENABLE_F
	.comm	_MA_EXT_MEMORY1_BAR_A,4,2       ## @MA_EXT_MEMORY1_BAR_A
	.comm	_NMTUS,4,2                      ## @NMTUS
	.comm	_IREG_NUM_ELEM,4,2              ## @IREG_NUM_ELEM
	.comm	_TPLA_SIZE,4,2                  ## @TPLA_SIZE
	.comm	_CIM_PIFLA_SIZE,4,2             ## @CIM_PIFLA_SIZE
	.comm	_CUDBG_NUM_PCIE_CONFIG_REGS,4,2 ## @CUDBG_NUM_PCIE_CONFIG_REGS
	.comm	_NCCTRL_WIN,4,2                 ## @NCCTRL_WIN
	.comm	_HMA_MUX_F,4,2                  ## @HMA_MUX_F
	.no_dead_strip	_cxgb4_get_entity_length
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cxgb4_get_entity_length
_cxgb4_get_entity_length:               ; @cxgb4_get_entity_length
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #48
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	str	xzr, [sp, #8]
	str	wzr, [sp, #4]
	sub	w8, w1, #128
	cmp	w8, #51
	b.hi	LBB0_60
; %bb.1:
	mov	x19, x0
Lloh0:
	adrp	x9, lJTI0_0@PAGE
Lloh1:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_2
	ldrh	w11, [x9, x8, lsl #1]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_2:
	mov	w0, #4
	b	LBB0_55
LBB0_3:
Lloh2:
	adrp	x8, _CIM_IBQ_SIZE@GOTPAGE
Lloh3:
	ldr	x8, [x8, _CIM_IBQ_SIZE@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	lsl	w0, w8, #4
	b	LBB0_56
LBB0_4:
	mov	w0, #8
	b	LBB0_55
LBB0_5:
	ldr	w0, [x19, #4]
	bl	_is_t5
	cbnz	w0, LBB0_7
; %bb.6:
	ldr	w0, [x19, #4]
	bl	_is_t6
	cbz	w0, LBB0_55
LBB0_7:
Lloh5:
	adrp	x8, _IREG_NUM_ELEM@GOTPAGE
Lloh6:
	ldr	x8, [x8, _IREG_NUM_ELEM@GOTPAGEOFF]
Lloh7:
	ldrsw	x8, [x8]
	lsl	x8, x8, #2
	add	x8, x8, #4
	mov	w9, #4
	udiv	x8, x9, x8
	lsl	w0, w8, #2
	b	LBB0_55
LBB0_8:
Lloh8:
	adrp	x8, _TPLA_SIZE@GOTPAGE
Lloh9:
	ldr	x8, [x8, _TPLA_SIZE@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	lsl	w8, w8, #2
	add	w0, w8, #4
	b	LBB0_55
LBB0_9:
	ldr	w0, [x19, #4]
	bl	_CHELSIO_CHIP_VERSION
	and	w8, w0, #0xfffffffe
	cmp	w8, #180
	mov	w8, #12
Lloh11:
	adrp	x9, _IREG_NUM_ELEM@GOTPAGE
Lloh12:
	ldr	x9, [x9, _IREG_NUM_ELEM@GOTPAGEOFF]
	csel	x8, x8, xzr, eq
Lloh13:
	ldrsw	x9, [x9]
	lsl	x9, x9, #2
	udiv	x8, x8, x9
	b	LBB0_20
LBB0_10:
	mov	w0, #12
	b	LBB0_55
LBB0_11:
	ldr	w8, [x19, #8]
	b	LBB0_54
LBB0_12:
	mov	x0, x19
	bl	_t4_chip_rss_size
	lsl	w0, w0, #2
	b	LBB0_55
LBB0_13:
	add	x2, sp, #4
	mov	x0, x19
	mov	x1, #0
	bl	_cudbg_fill_qdesc_num_and_size
	ldr	w0, [sp, #4]
	b	LBB0_56
LBB0_14:
Lloh14:
	adrp	x8, _CUDBG_NUM_PCIE_CONFIG_REGS@GOTPAGE
Lloh15:
	ldr	x8, [x8, _CUDBG_NUM_PCIE_CONFIG_REGS@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
	b	LBB0_54
LBB0_15:
	ldr	x8, [x19, #24]
	ldr	w8, [x8]
	b	LBB0_54
LBB0_16:
	ldr	w0, [x19, #4]
	bl	_CHELSIO_CHIP_VERSION
	cmp	w0, #182
	b.lt	LBB0_60
LBB0_17:
Lloh17:
	adrp	x8, _IREG_NUM_ELEM@GOTPAGE
Lloh18:
	ldr	x8, [x8, _IREG_NUM_ELEM@GOTPAGEOFF]
Lloh19:
	ldrsw	x8, [x8]
	lsl	x8, x8, #2
	mov	w9, #4
	udiv	x8, x9, x8
	lsl	w0, w8, #3
	b	LBB0_55
LBB0_18:
	ldr	w0, [x19, #4]
	bl	_CHELSIO_CHIP_VERSION
	cmp	w0, #182
	b.lt	LBB0_60
; %bb.19:
Lloh20:
	adrp	x8, _IREG_NUM_ELEM@GOTPAGE
Lloh21:
	ldr	x8, [x8, _IREG_NUM_ELEM@GOTPAGEOFF]
Lloh22:
	ldrsw	x8, [x8]
	lsl	x8, x8, #2
	mov	w9, #4
	udiv	x8, x9, x8
LBB0_20:
	lsl	w0, w8, #2
	b	LBB0_55
LBB0_21:
	mov	x0, x19
	bl	_cudbg_dump_context_size
	b	LBB0_55
LBB0_22:
	mov	w0, #4
	b	LBB0_56
LBB0_23:
Lloh23:
	adrp	x8, _CIM_PIFLA_SIZE@GOTPAGE
Lloh24:
	ldr	x8, [x8, _CIM_PIFLA_SIZE@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
	add	w8, w8, w8, lsl #1
	mov	w0, #4
	bfi	w0, w8, #4, #28
	b	LBB0_55
LBB0_24:
	mov	x0, x19
	mov	w1, #3
	b	LBB0_52
LBB0_25:
	mov	x0, x19
	mov	w1, #2
	b	LBB0_52
LBB0_26:
	mov	x0, x19
	mov	w1, #1
	b	LBB0_52
LBB0_27:
	mov	x0, x19
	mov	w1, #7
	bl	_cudbg_cim_obq_size
	b	LBB0_55
LBB0_28:
Lloh26:
	adrp	x8, _CIM_MALA_SIZE@GOTPAGE
Lloh27:
	ldr	x8, [x8, _CIM_MALA_SIZE@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
	add	w8, w8, w8, lsl #2
	lsl	w0, w8, #3
	b	LBB0_56
LBB0_29:
	ldr	w0, [x19, #4]
	bl	_is_t6
	ldr	w8, [x19]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w9, w9, w8, lt
	lsl	w9, w9, #2
	and	w9, w9, #0xffffffe0
	mov	w10, #26215
	movk	w10, #26214, lsl #16
	smull	x8, w8, w10
	lsr	x10, x8, #63
	asr	x8, x8, #34
	add	w8, w8, w10
	mov	w10, #40
	mul	w8, w8, w10
	add	w8, w8, #40
	cmp	w0, #0
	csel	w8, w9, w8, eq
	add	w0, w8, #4
	b	LBB0_56
LBB0_30:
	ldr	w0, [x19, #4]
	bl	_CHELSIO_CHIP_VERSION
	sub	w8, w0, #180
	cmp	w8, #2
	b.hs	LBB0_57
; %bb.31:
Lloh29:
	adrp	x8, _T5_REGMAP_SIZE@GOTPAGE
Lloh30:
	ldr	x8, [x8, _T5_REGMAP_SIZE@GOTPAGEOFF]
	b	LBB0_59
LBB0_32:
Lloh31:
	adrp	x8, _NMTUS@GOTPAGE
Lloh32:
	ldr	x8, [x8, _NMTUS@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
	b	LBB0_54
LBB0_33:
	ldr	w8, [x19, #12]
	b	LBB0_54
LBB0_34:
Lloh34:
	adrp	x8, _MA_TARGET_MEM_ENABLE_A@GOTPAGE
Lloh35:
	ldr	x8, [x8, _MA_TARGET_MEM_ENABLE_A@GOTPAGEOFF]
Lloh36:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_t4_read_reg
Lloh37:
	adrp	x8, _EXT_MEM1_ENABLE_F@GOTPAGE
Lloh38:
	ldr	x8, [x8, _EXT_MEM1_ENABLE_F@GOTPAGEOFF]
	b	LBB0_39
LBB0_35:
Lloh39:
	adrp	x8, _MA_TARGET_MEM_ENABLE_A@GOTPAGE
Lloh40:
	ldr	x8, [x8, _MA_TARGET_MEM_ENABLE_A@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_t4_read_reg
Lloh42:
	adrp	x8, _EXT_MEM0_ENABLE_F@GOTPAGE
Lloh43:
	ldr	x8, [x8, _EXT_MEM0_ENABLE_F@GOTPAGEOFF]
Lloh44:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_45
; %bb.36:
Lloh45:
	adrp	x8, _MA_EXT_MEMORY0_BAR_A@GOTPAGE
Lloh46:
	ldr	x8, [x8, _MA_EXT_MEMORY0_BAR_A@GOTPAGEOFF]
Lloh47:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_t4_read_reg
	bl	_EXT_MEM0_SIZE_G
	b	LBB0_46
LBB0_37:
	add	x1, sp, #8
	mov	x0, x19
	bl	_cudbg_fill_le_tcam_info
	ldr	w8, [sp, #8]
	lsl	w8, w8, #2
	add	w0, w8, #8
	b	LBB0_55
LBB0_38:
Lloh48:
	adrp	x8, _MA_TARGET_MEM_ENABLE_A@GOTPAGE
Lloh49:
	ldr	x8, [x8, _MA_TARGET_MEM_ENABLE_A@GOTPAGEOFF]
Lloh50:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_t4_read_reg
Lloh51:
	adrp	x8, _HMA_MUX_F@GOTPAGE
Lloh52:
	ldr	x8, [x8, _HMA_MUX_F@GOTPAGEOFF]
LBB0_39:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_45
; %bb.40:
Lloh53:
	adrp	x8, _MA_EXT_MEMORY1_BAR_A@GOTPAGE
Lloh54:
	ldr	x8, [x8, _MA_EXT_MEMORY1_BAR_A@GOTPAGEOFF]
Lloh55:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_t4_read_reg
	bl	_EXT_MEM1_SIZE_G
	b	LBB0_46
LBB0_41:
Lloh56:
	adrp	x8, _MA_TARGET_MEM_ENABLE_A@GOTPAGE
Lloh57:
	ldr	x8, [x8, _MA_TARGET_MEM_ENABLE_A@GOTPAGEOFF]
Lloh58:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_t4_read_reg
Lloh59:
	adrp	x8, _EDRAM1_ENABLE_F@GOTPAGE
Lloh60:
	ldr	x8, [x8, _EDRAM1_ENABLE_F@GOTPAGEOFF]
Lloh61:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_45
; %bb.42:
Lloh62:
	adrp	x8, _MA_EDRAM1_BAR_A@GOTPAGE
Lloh63:
	ldr	x8, [x8, _MA_EDRAM1_BAR_A@GOTPAGEOFF]
Lloh64:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_t4_read_reg
	bl	_EDRAM1_SIZE_G
	b	LBB0_46
LBB0_43:
Lloh65:
	adrp	x8, _MA_TARGET_MEM_ENABLE_A@GOTPAGE
Lloh66:
	ldr	x8, [x8, _MA_TARGET_MEM_ENABLE_A@GOTPAGEOFF]
Lloh67:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_t4_read_reg
Lloh68:
	adrp	x8, _EDRAM0_ENABLE_F@GOTPAGE
Lloh69:
	ldr	x8, [x8, _EDRAM0_ENABLE_F@GOTPAGEOFF]
Lloh70:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_45
; %bb.44:
Lloh71:
	adrp	x8, _MA_EDRAM0_BAR_A@GOTPAGE
Lloh72:
	ldr	x8, [x8, _MA_EDRAM0_BAR_A@GOTPAGEOFF]
Lloh73:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_t4_read_reg
	bl	_EDRAM0_SIZE_G
	b	LBB0_46
LBB0_45:
	mov	w0, #0
LBB0_46:
	bl	_cudbg_mbytes_to_bytes
	b	LBB0_55
LBB0_47:
	ldr	w0, [x19, #16]
	b	LBB0_56
LBB0_48:
	mov	x0, x19
	mov	w1, #0
	b	LBB0_52
LBB0_49:
	mov	x0, x19
	mov	w1, #4
	b	LBB0_52
LBB0_50:
	mov	x0, x19
	mov	w1, #6
	b	LBB0_52
LBB0_51:
	mov	x0, x19
	mov	w1, #5
LBB0_52:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	b	_cudbg_cim_obq_size
LBB0_53:
Lloh74:
	adrp	x8, _NMTUS@GOTPAGE
Lloh75:
	ldr	x8, [x8, _NMTUS@GOTPAGEOFF]
Lloh76:
	ldr	w8, [x8]
Lloh77:
	adrp	x9, _NCCTRL_WIN@GOTPAGE
Lloh78:
	ldr	x9, [x9, _NCCTRL_WIN@GOTPAGEOFF]
Lloh79:
	ldr	w9, [x9]
	mul	w8, w8, w9
LBB0_54:
	lsl	w0, w8, #2
LBB0_55:
	str	w0, [sp, #4]
LBB0_56:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	ret
LBB0_57:
	cmp	w0, #182
	b.ne	LBB0_60
; %bb.58:
Lloh80:
	adrp	x8, _T4_REGMAP_SIZE@GOTPAGE
Lloh81:
	ldr	x8, [x8, _T4_REGMAP_SIZE@GOTPAGEOFF]
LBB0_59:
	ldr	w0, [x8]
	b	LBB0_56
LBB0_60:
	mov	w0, #0
	b	LBB0_56
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGot	Lloh80, Lloh81
	.cfi_endproc
	.section	__TEXT,__const
	.p2align	1
lJTI0_0:
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_5-LBB0_2)>>2
	.short	(LBB0_4-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_8-LBB0_2)>>2
	.short	(LBB0_9-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_10-LBB0_2)>>2
	.short	(LBB0_11-LBB0_2)>>2
	.short	(LBB0_12-LBB0_2)>>2
	.short	(LBB0_30-LBB0_2)>>2
	.short	(LBB0_13-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_17-LBB0_2)>>2
	.short	(LBB0_17-LBB0_2)>>2
	.short	(LBB0_14-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_32-LBB0_2)>>2
	.short	(LBB0_33-LBB0_2)>>2
	.short	(LBB0_4-LBB0_2)>>2
	.short	(LBB0_34-LBB0_2)>>2
	.short	(LBB0_35-LBB0_2)>>2
	.short	(LBB0_15-LBB0_2)>>2
	.short	(LBB0_16-LBB0_2)>>2
	.short	(LBB0_37-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_18-LBB0_2)>>2
	.short	(LBB0_38-LBB0_2)>>2
	.short	(LBB0_41-LBB0_2)>>2
	.short	(LBB0_43-LBB0_2)>>2
	.short	(LBB0_21-LBB0_2)>>2
	.short	(LBB0_47-LBB0_2)>>2
	.short	(LBB0_2-LBB0_2)>>2
	.short	(LBB0_22-LBB0_2)>>2
	.short	(LBB0_23-LBB0_2)>>2
	.short	(LBB0_24-LBB0_2)>>2
	.short	(LBB0_25-LBB0_2)>>2
	.short	(LBB0_26-LBB0_2)>>2
	.short	(LBB0_48-LBB0_2)>>2
	.short	(LBB0_49-LBB0_2)>>2
	.short	(LBB0_27-LBB0_2)>>2
	.short	(LBB0_50-LBB0_2)>>2
	.short	(LBB0_51-LBB0_2)>>2
	.short	(LBB0_28-LBB0_2)>>2
	.short	(LBB0_29-LBB0_2)>>2
	.short	(LBB0_3-LBB0_2)>>2
	.short	(LBB0_3-LBB0_2)>>2
	.short	(LBB0_3-LBB0_2)>>2
	.short	(LBB0_3-LBB0_2)>>2
	.short	(LBB0_3-LBB0_2)>>2
	.short	(LBB0_3-LBB0_2)>>2
	.short	(LBB0_53-LBB0_2)>>2
                                        ; -- End function
	.comm	_T4_REGMAP_SIZE,4,2             ; @T4_REGMAP_SIZE
	.comm	_T5_REGMAP_SIZE,4,2             ; @T5_REGMAP_SIZE
	.comm	_CIM_MALA_SIZE,4,2              ; @CIM_MALA_SIZE
	.comm	_CIM_IBQ_SIZE,4,2               ; @CIM_IBQ_SIZE
	.comm	_MA_TARGET_MEM_ENABLE_A,4,2     ; @MA_TARGET_MEM_ENABLE_A
	.comm	_EDRAM0_ENABLE_F,4,2            ; @EDRAM0_ENABLE_F
	.comm	_MA_EDRAM0_BAR_A,4,2            ; @MA_EDRAM0_BAR_A
	.comm	_EDRAM1_ENABLE_F,4,2            ; @EDRAM1_ENABLE_F
	.comm	_MA_EDRAM1_BAR_A,4,2            ; @MA_EDRAM1_BAR_A
	.comm	_EXT_MEM0_ENABLE_F,4,2          ; @EXT_MEM0_ENABLE_F
	.comm	_MA_EXT_MEMORY0_BAR_A,4,2       ; @MA_EXT_MEMORY0_BAR_A
	.comm	_EXT_MEM1_ENABLE_F,4,2          ; @EXT_MEM1_ENABLE_F
	.comm	_MA_EXT_MEMORY1_BAR_A,4,2       ; @MA_EXT_MEMORY1_BAR_A
	.comm	_NMTUS,4,2                      ; @NMTUS
	.comm	_IREG_NUM_ELEM,4,2              ; @IREG_NUM_ELEM
	.comm	_TPLA_SIZE,4,2                  ; @TPLA_SIZE
	.comm	_CIM_PIFLA_SIZE,4,2             ; @CIM_PIFLA_SIZE
	.comm	_CUDBG_NUM_PCIE_CONFIG_REGS,4,2 ; @CUDBG_NUM_PCIE_CONFIG_REGS
	.comm	_NCCTRL_WIN,4,2                 ; @NCCTRL_WIN
	.comm	_HMA_MUX_F,4,2                  ; @HMA_MUX_F
	.no_dead_strip	_cxgb4_get_entity_length
.subsections_via_symbols
