	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function __iommu_set_twl
___iommu_set_twl:                       ## @__iommu_set_twl
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r15d
	movq	%rdi, %r14
	movq	_MMU_CNTL@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	callq	_iommu_read_reg
	movl	%eax, %ebx
	testl	%r15d, %r15d
	jne	LBB0_1
## %bb.2:
	movq	_MMU_IRQ_TLB_MISS_MASK@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_1:
	movq	_MMU_IRQ_TWL_MASK@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %esi
	movq	_MMU_IRQENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_iommu_write_reg
	movq	_MMU_CNTL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	_MMU_CNTL_MMU_EN@GOTPCREL(%rip), %rax
	testl	%r15d, %r15d
	je	LBB0_5
## %bb.4:
	movq	_MMU_CNTL_TWL_EN@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r15d
LBB0_5:
	notl	%ecx
	andl	%ecx, %ebx
	orl	(%rax), %ebx
	orl	%r15d, %ebx
	movl	(%r12), %edx
	movq	%r14, %rdi
	movl	%ebx, %esi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_iommu_write_reg                ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_MMU_CNTL,4,2                   ## @MMU_CNTL
	.comm	_MMU_IRQ_TWL_MASK,4,2           ## @MMU_IRQ_TWL_MASK
	.comm	_MMU_IRQENABLE,4,2              ## @MMU_IRQENABLE
	.comm	_MMU_IRQ_TLB_MISS_MASK,4,2      ## @MMU_IRQ_TLB_MISS_MASK
	.comm	_MMU_CNTL_MASK,4,2              ## @MMU_CNTL_MASK
	.comm	_MMU_CNTL_MMU_EN,4,2            ## @MMU_CNTL_MMU_EN
	.comm	_MMU_CNTL_TWL_EN,4,2            ## @MMU_CNTL_TWL_EN
	.no_dead_strip	___iommu_set_twl
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function __iommu_set_twl
___iommu_set_twl:                       ; @__iommu_set_twl
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x1
	mov	x20, x0
Lloh0:
	adrp	x22, _MMU_CNTL@GOTPAGE
Lloh1:
	ldr	x22, [x22, _MMU_CNTL@GOTPAGEOFF]
	ldr	w1, [x22]
	bl	_iommu_read_reg
	mov	x21, x0
Lloh2:
	adrp	x8, _MMU_IRQ_TLB_MISS_MASK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _MMU_IRQ_TLB_MISS_MASK@GOTPAGEOFF]
Lloh4:
	adrp	x9, _MMU_IRQ_TWL_MASK@GOTPAGE
Lloh5:
	ldr	x9, [x9, _MMU_IRQ_TWL_MASK@GOTPAGEOFF]
	cmp	w19, #0
	csel	x8, x8, x9, eq
	ldr	w1, [x8]
Lloh6:
	adrp	x8, _MMU_IRQENABLE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _MMU_IRQENABLE@GOTPAGEOFF]
Lloh8:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_iommu_write_reg
Lloh9:
	adrp	x8, _MMU_CNTL_MASK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _MMU_CNTL_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
Lloh12:
	adrp	x9, _MMU_CNTL_MMU_EN@GOTPAGE
Lloh13:
	ldr	x9, [x9, _MMU_CNTL_MMU_EN@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
Lloh15:
	adrp	x10, _MMU_CNTL_TWL_EN@GOTPAGE
Lloh16:
	ldr	x10, [x10, _MMU_CNTL_TWL_EN@GOTPAGEOFF]
Lloh17:
	ldr	w10, [x10]
	cmp	w19, #0
	csel	w10, wzr, w10, eq
	bic	w8, w21, w8
	orr	w8, w8, w9
	orr	w1, w8, w10
	ldr	w2, [x22]
	mov	x0, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_iommu_write_reg
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_MMU_CNTL,4,2                   ; @MMU_CNTL
	.comm	_MMU_IRQ_TWL_MASK,4,2           ; @MMU_IRQ_TWL_MASK
	.comm	_MMU_IRQENABLE,4,2              ; @MMU_IRQENABLE
	.comm	_MMU_IRQ_TLB_MISS_MASK,4,2      ; @MMU_IRQ_TLB_MISS_MASK
	.comm	_MMU_CNTL_MASK,4,2              ; @MMU_CNTL_MASK
	.comm	_MMU_CNTL_MMU_EN,4,2            ; @MMU_CNTL_MMU_EN
	.comm	_MMU_CNTL_TWL_EN,4,2            ; @MMU_CNTL_TWL_EN
	.no_dead_strip	___iommu_set_twl
.subsections_via_symbols
