	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_sdhci_reset
_tegra_sdhci_reset:                     ## @tegra_sdhci_reset
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %ebx
	movq	%rdi, %r15
	callq	_sdhci_priv
	movq	%rax, %rdi
	callq	_sdhci_pltfm_priv
	movq	%rax, %r14
	movq	16(%rax), %rax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_sdhci_reset
	movq	_SDHCI_RESET_ALL@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_15
## %bb.1:
	movl	12(%r14), %esi
	movq	%r15, %rdi
	callq	_tegra_sdhci_set_tap
	movq	_SDHCI_TEGRA_VENDOR_MISC_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_sdhci_readl
	movl	%eax, %ebx
	movq	_SDHCI_TEGRA_VENDOR_CLOCK_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_sdhci_readl
	movq	_SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300@GOTPCREL(%rip), %rdx
	movq	_SDHCI_MISC_CTRL_ENABLE_SDR50@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r12d
	orl	(%rdx), %r12d
	movq	_SDHCI_MISC_CTRL_ENABLE_DDR50@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r12d
	movq	_SDHCI_MISC_CTRL_ENABLE_SDR104@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r12d
	notl	%r12d
	andl	%ebx, %r12d
	movq	_SDHCI_CLOCK_CTRL_TRIM_MASK@GOTPCREL(%rip), %rcx
	movq	_SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r13d
	orl	(%rcx), %r13d
	notl	%r13d
	andl	%eax, %r13d
	movq	%r15, %rdi
	callq	_tegra_sdhci_is_pad_and_regulator_valid
	testq	%rax, %rax
	je	LBB0_2
## %bb.3:
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %eax
	movq	_NVQUIRK_ENABLE_SDHCI_SPEC_300@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	andl	%eax, %esi
	je	LBB0_5
## %bb.4:
	movq	_SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
LBB0_5:
	orl	%r12d, %esi
	movq	_NVQUIRK_ENABLE_SDR50@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	andl	%eax, %edx
	movq	_SDHCI_MISC_CTRL_ENABLE_SDR50@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	cmovnel	%ecx, %edx
	movq	_NVQUIRK_ENABLE_DDR50@GOTPCREL(%rip), %rdi
	movl	(%rdi), %edi
	andl	%eax, %edi
	je	LBB0_7
## %bb.6:
	movq	_SDHCI_MISC_CTRL_ENABLE_DDR50@GOTPCREL(%rip), %rdi
	movl	(%rdi), %edi
LBB0_7:
	orl	%edi, %edx
	orl	%edx, %esi
	movq	_NVQUIRK_ENABLE_SDR104@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	andl	%eax, %edx
	movq	_SDHCI_TEGRA_VENDOR_CLOCK_CTRL@GOTPCREL(%rip), %r12
	je	LBB0_9
## %bb.8:
	movq	_SDHCI_MISC_CTRL_ENABLE_SDR104@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
LBB0_9:
	orl	%edx, %esi
	testl	%eax, %ecx
	je	LBB0_11
## %bb.10:
	movq	_SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
LBB0_11:
	movq	_SDHCI_TEGRA_VENDOR_MISC_CTRL@GOTPCREL(%rip), %rdx
	jmp	LBB0_12
LBB0_2:
	movl	%r12d, %esi
	movq	_SDHCI_TEGRA_VENDOR_MISC_CTRL@GOTPCREL(%rip), %rdx
	movq	_SDHCI_TEGRA_VENDOR_CLOCK_CTRL@GOTPCREL(%rip), %r12
LBB0_12:
	movl	(%r14), %ebx
	movq	_SDHCI_CLOCK_CTRL_TRIM_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %ebx
	orl	%r13d, %ebx
	movl	(%rdx), %edx
	movq	%r15, %rdi
	callq	_sdhci_writel
	movl	(%r12), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_sdhci_writel
	movq	_NVQUIRK_HAS_PADCALIB@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	-48(%rbp), %rcx                 ## 8-byte Reload
	testl	%eax, (%rcx)
	je	LBB0_14
## %bb.13:
	movq	_SDHCI_TEGRA_SDMEM_COMP_PADCTRL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_sdhci_readl
	movq	_SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	(%rbx), %edx
	movq	%r15, %rdi
	callq	_sdhci_writel
	movl	$1, 4(%r14)
LBB0_14:
	movl	$0, 8(%r14)
LBB0_15:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_SDHCI_RESET_ALL,4,2            ## @SDHCI_RESET_ALL
	.comm	_SDHCI_TEGRA_VENDOR_MISC_CTRL,4,2 ## @SDHCI_TEGRA_VENDOR_MISC_CTRL
	.comm	_SDHCI_TEGRA_VENDOR_CLOCK_CTRL,4,2 ## @SDHCI_TEGRA_VENDOR_CLOCK_CTRL
	.comm	_SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300,4,2 ## @SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300
	.comm	_SDHCI_MISC_CTRL_ENABLE_SDR50,4,2 ## @SDHCI_MISC_CTRL_ENABLE_SDR50
	.comm	_SDHCI_MISC_CTRL_ENABLE_DDR50,4,2 ## @SDHCI_MISC_CTRL_ENABLE_DDR50
	.comm	_SDHCI_MISC_CTRL_ENABLE_SDR104,4,2 ## @SDHCI_MISC_CTRL_ENABLE_SDR104
	.comm	_SDHCI_CLOCK_CTRL_TRIM_MASK,4,2 ## @SDHCI_CLOCK_CTRL_TRIM_MASK
	.comm	_SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE,4,2 ## @SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE
	.comm	_NVQUIRK_ENABLE_SDHCI_SPEC_300,4,2 ## @NVQUIRK_ENABLE_SDHCI_SPEC_300
	.comm	_NVQUIRK_ENABLE_SDR50,4,2       ## @NVQUIRK_ENABLE_SDR50
	.comm	_NVQUIRK_ENABLE_DDR50,4,2       ## @NVQUIRK_ENABLE_DDR50
	.comm	_NVQUIRK_ENABLE_SDR104,4,2      ## @NVQUIRK_ENABLE_SDR104
	.comm	_SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE,4,2 ## @SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE
	.comm	_SDHCI_CLOCK_CTRL_TRIM_SHIFT,4,2 ## @SDHCI_CLOCK_CTRL_TRIM_SHIFT
	.comm	_NVQUIRK_HAS_PADCALIB,4,2       ## @NVQUIRK_HAS_PADCALIB
	.comm	_SDHCI_TEGRA_SDMEM_COMP_PADCTRL,4,2 ## @SDHCI_TEGRA_SDMEM_COMP_PADCTRL
	.comm	_SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK,4,2 ## @SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK
	.comm	_SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL,4,2 ## @SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL
	.no_dead_strip	_tegra_sdhci_reset
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_sdhci_reset
_tegra_sdhci_reset:                     ; @tegra_sdhci_reset
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x1
	mov	x19, x0
	bl	_sdhci_priv
	bl	_sdhci_pltfm_priv
	mov	x20, x0
	ldr	x23, [x0, #16]
	mov	x0, x19
	mov	x1, x21
	bl	_sdhci_reset
Lloh0:
	adrp	x8, _SDHCI_RESET_ALL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _SDHCI_RESET_ALL@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	tst	w8, w21
	b.eq	LBB0_7
; %bb.1:
	ldr	w1, [x20, #12]
	mov	x0, x19
	bl	_tegra_sdhci_set_tap
Lloh3:
	adrp	x8, _SDHCI_TEGRA_VENDOR_MISC_CTRL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _SDHCI_TEGRA_VENDOR_MISC_CTRL@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_sdhci_readl
	mov	x21, x0
Lloh6:
	adrp	x25, _SDHCI_TEGRA_VENDOR_CLOCK_CTRL@GOTPAGE
Lloh7:
	ldr	x25, [x25, _SDHCI_TEGRA_VENDOR_CLOCK_CTRL@GOTPAGEOFF]
	ldr	w1, [x25]
	mov	x0, x19
	bl	_sdhci_readl
Lloh8:
	adrp	x24, _SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300@GOTPAGE
Lloh9:
	ldr	x24, [x24, _SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300@GOTPAGEOFF]
	ldr	w8, [x24]
Lloh10:
	adrp	x28, _SDHCI_MISC_CTRL_ENABLE_SDR50@GOTPAGE
Lloh11:
	ldr	x28, [x28, _SDHCI_MISC_CTRL_ENABLE_SDR50@GOTPAGEOFF]
	ldr	w9, [x28]
	orr	w8, w9, w8
Lloh12:
	adrp	x27, _SDHCI_MISC_CTRL_ENABLE_DDR50@GOTPAGE
Lloh13:
	ldr	x27, [x27, _SDHCI_MISC_CTRL_ENABLE_DDR50@GOTPAGEOFF]
	ldr	w9, [x27]
Lloh14:
	adrp	x26, _SDHCI_MISC_CTRL_ENABLE_SDR104@GOTPAGE
Lloh15:
	ldr	x26, [x26, _SDHCI_MISC_CTRL_ENABLE_SDR104@GOTPAGEOFF]
	orr	w8, w8, w9
	ldr	w9, [x26]
	orr	w8, w8, w9
	bic	w21, w21, w8
Lloh16:
	adrp	x8, _SDHCI_CLOCK_CTRL_TRIM_MASK@GOTPAGE
Lloh17:
	ldr	x8, [x8, _SDHCI_CLOCK_CTRL_TRIM_MASK@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
Lloh19:
	adrp	x9, _SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE@GOTPAGE
Lloh20:
	ldr	x9, [x9, _SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w22, w0, w8
	mov	x0, x19
	bl	_tegra_sdhci_is_pad_and_regulator_valid
	cbz	x0, LBB0_4
; %bb.2:
	ldr	w8, [x23]
Lloh22:
	adrp	x9, _NVQUIRK_ENABLE_SDHCI_SPEC_300@GOTPAGE
Lloh23:
	ldr	x9, [x9, _NVQUIRK_ENABLE_SDHCI_SPEC_300@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	ldr	w10, [x24]
	tst	w9, w8
	csel	w9, wzr, w10, eq
	orr	w9, w9, w21
Lloh25:
	adrp	x10, _NVQUIRK_ENABLE_SDR50@GOTPAGE
Lloh26:
	ldr	x10, [x10, _NVQUIRK_ENABLE_SDR50@GOTPAGEOFF]
Lloh27:
	ldr	w10, [x10]
	ldr	w11, [x28]
	tst	w10, w8
	csel	w10, wzr, w11, eq
	orr	w9, w9, w10
Lloh28:
	adrp	x10, _NVQUIRK_ENABLE_DDR50@GOTPAGE
Lloh29:
	ldr	x10, [x10, _NVQUIRK_ENABLE_DDR50@GOTPAGEOFF]
Lloh30:
	ldr	w10, [x10]
	ldr	w12, [x27]
	tst	w10, w8
	csel	w10, wzr, w12, eq
	orr	w9, w9, w10
Lloh31:
	adrp	x10, _NVQUIRK_ENABLE_SDR104@GOTPAGE
Lloh32:
	ldr	x10, [x10, _NVQUIRK_ENABLE_SDR104@GOTPAGEOFF]
Lloh33:
	ldr	w10, [x10]
	ldr	w12, [x26]
	tst	w10, w8
	csel	w10, wzr, w12, eq
	orr	w21, w9, w10
	tst	w11, w8
	b.eq	LBB0_4
; %bb.3:
Lloh34:
	adrp	x8, _SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE@GOTPAGE
Lloh35:
	ldr	x8, [x8, _SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE@GOTPAGEOFF]
Lloh36:
	ldr	w8, [x8]
	orr	w22, w8, w22
LBB0_4:
Lloh37:
	adrp	x10, _SDHCI_TEGRA_VENDOR_MISC_CTRL@GOTPAGE
Lloh38:
	ldr	x10, [x10, _SDHCI_TEGRA_VENDOR_MISC_CTRL@GOTPAGEOFF]
	ldr	w8, [x20]
Lloh39:
	adrp	x9, _SDHCI_CLOCK_CTRL_TRIM_SHIFT@GOTPAGE
Lloh40:
	ldr	x9, [x9, _SDHCI_CLOCK_CTRL_TRIM_SHIFT@GOTPAGEOFF]
Lloh41:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	orr	w22, w8, w22
Lloh42:
	ldr	w2, [x10]
	mov	x0, x19
	mov	x1, x21
	bl	_sdhci_writel
	ldr	w2, [x25]
	mov	x0, x19
	mov	x1, x22
	bl	_sdhci_writel
	ldr	w8, [x23]
Lloh43:
	adrp	x9, _NVQUIRK_HAS_PADCALIB@GOTPAGE
Lloh44:
	ldr	x9, [x9, _NVQUIRK_HAS_PADCALIB@GOTPAGEOFF]
Lloh45:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_6
; %bb.5:
Lloh46:
	adrp	x21, _SDHCI_TEGRA_SDMEM_COMP_PADCTRL@GOTPAGE
Lloh47:
	ldr	x21, [x21, _SDHCI_TEGRA_SDMEM_COMP_PADCTRL@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_sdhci_readl
Lloh48:
	adrp	x8, _SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK@GOTPAGE
Lloh49:
	ldr	x8, [x8, _SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK@GOTPAGEOFF]
Lloh50:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh51:
	adrp	x9, _SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL@GOTPAGE
Lloh52:
	ldr	x9, [x9, _SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL@GOTPAGEOFF]
Lloh53:
	ldr	w9, [x9]
	orr	w1, w8, w9
	ldr	w2, [x21]
	mov	x0, x19
	bl	_sdhci_writel
	mov	w8, #1
	str	w8, [x20, #4]
LBB0_6:
	str	wzr, [x20, #8]
LBB0_7:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh42
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh46, Lloh47
	.cfi_endproc
                                        ; -- End function
	.comm	_SDHCI_RESET_ALL,4,2            ; @SDHCI_RESET_ALL
	.comm	_SDHCI_TEGRA_VENDOR_MISC_CTRL,4,2 ; @SDHCI_TEGRA_VENDOR_MISC_CTRL
	.comm	_SDHCI_TEGRA_VENDOR_CLOCK_CTRL,4,2 ; @SDHCI_TEGRA_VENDOR_CLOCK_CTRL
	.comm	_SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300,4,2 ; @SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300
	.comm	_SDHCI_MISC_CTRL_ENABLE_SDR50,4,2 ; @SDHCI_MISC_CTRL_ENABLE_SDR50
	.comm	_SDHCI_MISC_CTRL_ENABLE_DDR50,4,2 ; @SDHCI_MISC_CTRL_ENABLE_DDR50
	.comm	_SDHCI_MISC_CTRL_ENABLE_SDR104,4,2 ; @SDHCI_MISC_CTRL_ENABLE_SDR104
	.comm	_SDHCI_CLOCK_CTRL_TRIM_MASK,4,2 ; @SDHCI_CLOCK_CTRL_TRIM_MASK
	.comm	_SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE,4,2 ; @SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE
	.comm	_NVQUIRK_ENABLE_SDHCI_SPEC_300,4,2 ; @NVQUIRK_ENABLE_SDHCI_SPEC_300
	.comm	_NVQUIRK_ENABLE_SDR50,4,2       ; @NVQUIRK_ENABLE_SDR50
	.comm	_NVQUIRK_ENABLE_DDR50,4,2       ; @NVQUIRK_ENABLE_DDR50
	.comm	_NVQUIRK_ENABLE_SDR104,4,2      ; @NVQUIRK_ENABLE_SDR104
	.comm	_SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE,4,2 ; @SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE
	.comm	_SDHCI_CLOCK_CTRL_TRIM_SHIFT,4,2 ; @SDHCI_CLOCK_CTRL_TRIM_SHIFT
	.comm	_NVQUIRK_HAS_PADCALIB,4,2       ; @NVQUIRK_HAS_PADCALIB
	.comm	_SDHCI_TEGRA_SDMEM_COMP_PADCTRL,4,2 ; @SDHCI_TEGRA_SDMEM_COMP_PADCTRL
	.comm	_SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK,4,2 ; @SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK
	.comm	_SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL,4,2 ; @SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL
	.no_dead_strip	_tegra_sdhci_reset
.subsections_via_symbols
