	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dw_mci_hi3798cv200_set_ios
_dw_mci_hi3798cv200_set_ios:            ## @dw_mci_hi3798cv200_set_ios
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %rbx
	movq	(%rdi), %r15
	movq	_UHS_REG@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	callq	_mci_readl
	movq	(%r14), %rcx
	movq	_MMC_TIMING_MMC_DDR52@GOTPCREL(%rip), %r12
	movq	_MMC_TIMING_UHS_DDR50@GOTPCREL(%rip), %rsi
	movq	_SDMMC_UHS_DDR@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movl	%edx, %edi
	orl	%eax, %edi
	notl	%edx
	andl	%eax, %edx
	cmpq	(%rsi), %rcx
	cmovel	%edi, %edx
	cmpq	(%r12), %rcx
	cmovel	%edi, %edx
	movl	(%r13), %esi
	movq	%rbx, %rdi
	callq	_mci_writel
	movq	_ENABLE_SHIFT@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%rbx, %rdi
	callq	_mci_readl
	movq	(%r14), %rcx
	movq	_SDMMC_ENABLE_PHASE@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movl	%edx, %esi
	orl	%eax, %esi
	notl	%edx
	andl	%eax, %edx
	cmpq	(%r12), %rcx
	cmovel	%esi, %edx
	movl	(%r13), %esi
	movq	%rbx, %rdi
	callq	_mci_writel
	movq	_DDR_REG@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%rbx, %rdi
	callq	_mci_readl
	movq	(%r14), %rcx
	movq	_MMC_TIMING_MMC_HS400@GOTPCREL(%rip), %rsi
	movq	_SDMMC_DDR_HS400@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movl	%edx, %edi
	orl	%eax, %edi
	notl	%edx
	andl	%eax, %edx
	cmpq	(%rsi), %rcx
	cmovel	%edi, %edx
	movl	(%r12), %esi
	movq	%rbx, %rdi
	callq	_mci_writel
	movq	(%r14), %rax
	movq	_MMC_TIMING_MMC_HS@GOTPCREL(%rip), %rcx
	movl	$180, %esi
	cmpq	(%rcx), %rax
	je	LBB0_4
## %bb.1:
	movq	_MMC_TIMING_LEGACY@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_4
## %bb.2:
	movq	_MMC_TIMING_MMC_HS200@GOTPCREL(%rip), %rcx
	movl	$135, %esi
	cmpq	(%rcx), %rax
	jne	LBB0_3
LBB0_4:
	movl	(%r15), %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_clk_set_phase                  ## TAILCALL
LBB0_3:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_UHS_REG,4,2                    ## @UHS_REG
	.comm	_MMC_TIMING_MMC_DDR52,8,3       ## @MMC_TIMING_MMC_DDR52
	.comm	_MMC_TIMING_UHS_DDR50,8,3       ## @MMC_TIMING_UHS_DDR50
	.comm	_SDMMC_UHS_DDR,4,2              ## @SDMMC_UHS_DDR
	.comm	_ENABLE_SHIFT,4,2               ## @ENABLE_SHIFT
	.comm	_SDMMC_ENABLE_PHASE,4,2         ## @SDMMC_ENABLE_PHASE
	.comm	_DDR_REG,4,2                    ## @DDR_REG
	.comm	_MMC_TIMING_MMC_HS400,8,3       ## @MMC_TIMING_MMC_HS400
	.comm	_SDMMC_DDR_HS400,4,2            ## @SDMMC_DDR_HS400
	.comm	_MMC_TIMING_MMC_HS,8,3          ## @MMC_TIMING_MMC_HS
	.comm	_MMC_TIMING_LEGACY,8,3          ## @MMC_TIMING_LEGACY
	.comm	_MMC_TIMING_MMC_HS200,8,3       ## @MMC_TIMING_MMC_HS200
	.no_dead_strip	_dw_mci_hi3798cv200_set_ios
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dw_mci_hi3798cv200_set_ios
_dw_mci_hi3798cv200_set_ios:            ; @dw_mci_hi3798cv200_set_ios
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x1
	mov	x20, x0
	ldr	x21, [x0]
Lloh0:
	adrp	x22, _UHS_REG@GOTPAGE
Lloh1:
	ldr	x22, [x22, _UHS_REG@GOTPAGEOFF]
	ldr	w1, [x22]
	bl	_mci_readl
	ldr	x8, [x19]
Lloh2:
	adrp	x23, _MMC_TIMING_MMC_DDR52@GOTPAGE
Lloh3:
	ldr	x23, [x23, _MMC_TIMING_MMC_DDR52@GOTPAGEOFF]
	ldr	x9, [x23]
Lloh4:
	adrp	x10, _MMC_TIMING_UHS_DDR50@GOTPAGE
Lloh5:
	ldr	x10, [x10, _MMC_TIMING_UHS_DDR50@GOTPAGEOFF]
Lloh6:
	ldr	x10, [x10]
	cmp	x8, x10
Lloh7:
	adrp	x10, _SDMMC_UHS_DDR@GOTPAGE
Lloh8:
	ldr	x10, [x10, _SDMMC_UHS_DDR@GOTPAGEOFF]
	ccmp	x8, x9, #4, ne
Lloh9:
	ldr	w8, [x10]
	orr	w9, w8, w0
	bic	w8, w0, w8
	csel	w2, w9, w8, eq
	ldr	w1, [x22]
	mov	x0, x20
	bl	_mci_writel
Lloh10:
	adrp	x22, _ENABLE_SHIFT@GOTPAGE
Lloh11:
	ldr	x22, [x22, _ENABLE_SHIFT@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x20
	bl	_mci_readl
	ldr	x8, [x19]
	ldr	x9, [x23]
Lloh12:
	adrp	x10, _SDMMC_ENABLE_PHASE@GOTPAGE
Lloh13:
	ldr	x10, [x10, _SDMMC_ENABLE_PHASE@GOTPAGEOFF]
Lloh14:
	ldr	w10, [x10]
	orr	w11, w10, w0
	bic	w10, w0, w10
	cmp	x8, x9
	csel	w2, w11, w10, eq
	ldr	w1, [x22]
	mov	x0, x20
	bl	_mci_writel
Lloh15:
	adrp	x22, _DDR_REG@GOTPAGE
Lloh16:
	ldr	x22, [x22, _DDR_REG@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x20
	bl	_mci_readl
	ldr	x8, [x19]
Lloh17:
	adrp	x9, _MMC_TIMING_MMC_HS400@GOTPAGE
Lloh18:
	ldr	x9, [x9, _MMC_TIMING_MMC_HS400@GOTPAGEOFF]
Lloh19:
	ldr	x9, [x9]
Lloh20:
	adrp	x10, _SDMMC_DDR_HS400@GOTPAGE
Lloh21:
	ldr	x10, [x10, _SDMMC_DDR_HS400@GOTPAGEOFF]
Lloh22:
	ldr	w10, [x10]
	orr	w11, w10, w0
	bic	w10, w0, w10
	cmp	x8, x9
	csel	w2, w11, w10, eq
	ldr	w1, [x22]
	mov	x0, x20
	bl	_mci_writel
	ldr	x8, [x19]
Lloh23:
	adrp	x9, _MMC_TIMING_MMC_HS@GOTPAGE
Lloh24:
	ldr	x9, [x9, _MMC_TIMING_MMC_HS@GOTPAGEOFF]
Lloh25:
	ldr	x9, [x9]
	mov	w1, #180
	cmp	x8, x9
	b.eq	LBB0_4
; %bb.1:
Lloh26:
	adrp	x9, _MMC_TIMING_LEGACY@GOTPAGE
Lloh27:
	ldr	x9, [x9, _MMC_TIMING_LEGACY@GOTPAGEOFF]
Lloh28:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_4
; %bb.2:
Lloh29:
	adrp	x9, _MMC_TIMING_MMC_HS200@GOTPAGE
Lloh30:
	ldr	x9, [x9, _MMC_TIMING_MMC_HS200@GOTPAGEOFF]
Lloh31:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_5
; %bb.3:
	mov	w1, #135
LBB0_4:
	ldr	w0, [x21]
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_clk_set_phase
LBB0_5:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.cfi_endproc
                                        ; -- End function
	.comm	_UHS_REG,4,2                    ; @UHS_REG
	.comm	_MMC_TIMING_MMC_DDR52,8,3       ; @MMC_TIMING_MMC_DDR52
	.comm	_MMC_TIMING_UHS_DDR50,8,3       ; @MMC_TIMING_UHS_DDR50
	.comm	_SDMMC_UHS_DDR,4,2              ; @SDMMC_UHS_DDR
	.comm	_ENABLE_SHIFT,4,2               ; @ENABLE_SHIFT
	.comm	_SDMMC_ENABLE_PHASE,4,2         ; @SDMMC_ENABLE_PHASE
	.comm	_DDR_REG,4,2                    ; @DDR_REG
	.comm	_MMC_TIMING_MMC_HS400,8,3       ; @MMC_TIMING_MMC_HS400
	.comm	_SDMMC_DDR_HS400,4,2            ; @SDMMC_DDR_HS400
	.comm	_MMC_TIMING_MMC_HS,8,3          ; @MMC_TIMING_MMC_HS
	.comm	_MMC_TIMING_LEGACY,8,3          ; @MMC_TIMING_LEGACY
	.comm	_MMC_TIMING_MMC_HS200,8,3       ; @MMC_TIMING_MMC_HS200
	.no_dead_strip	_dw_mci_hi3798cv200_set_ios
.subsections_via_symbols
