	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function atl2_configure
_atl2_configure:                        ## @atl2_configure
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	leaq	24(%rdi), %r14
	movq	_REG_ISR@GOTPCREL(%rip), %r15
	movq	(%r15), %rsi
	movq	%r14, %rdi
	movl	$-1, %edx
	callq	_ATL2_WRITE_REG
	movq	88(%rbx), %rax
	movl	16(%rax), %ecx
	movl	24(%rax), %esi
	shll	$24, %ecx
	shll	$16, %esi
	orl	%ecx, %esi
	movl	32(%rax), %edx
	shll	$8, %edx
	orl	%esi, %edx
	orl	40(%rax), %edx
	movq	_REG_MAC_STA_ADDR@GOTPCREL(%rip), %r12
	movq	(%r12), %rsi
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REG
	movq	88(%rbx), %rax
	movl	(%rax), %edx
	shll	$8, %edx
	orl	8(%rax), %edx
	movq	(%r12), %rsi
	addq	$4, %rsi
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REG
	movq	_REG_DESC_BASE_ADDR_HI@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movl	(%rbx), %edx
	sarl	$31, %edx
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REG
	movq	_REG_TXD_BASE_ADDR_LO@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movl	4(%rbx), %edx
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REG
	movq	_REG_TXS_BASE_ADDR_LO@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movl	8(%rbx), %edx
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REG
	movq	_REG_RXD_BASE_ADDR_LO@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movl	12(%rbx), %edx
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REG
	movq	_REG_TXD_MEM_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	16(%rbx), %eax
	leal	3(%rax), %edx
	testl	%eax, %eax
	cmovnsl	%eax, %edx
	sarl	$2, %edx
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REGW
	movq	_REG_TXS_MEM_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	136(%rbx), %edx
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REGW
	movq	_REG_RXD_BUF_NUM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	128(%rbx), %edx
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REGW
	movq	_MAC_IPG_IFG_IPGT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	andl	80(%rbx), %edx
	movq	_MAC_IPG_IFG_IPGT_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %edx
	movq	_MAC_IPG_IFG_MIFG_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	72(%rbx), %eax
	movq	_MAC_IPG_IFG_MIFG_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	orl	%edx, %eax
	movq	_MAC_IPG_IFG_IPGR1_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	andl	64(%rbx), %esi
	movq	_MAC_IPG_IFG_IPGR1_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %esi
	movq	_MAC_IPG_IFG_IPGR2_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	andl	56(%rbx), %edx
	movq	_MAC_IPG_IFG_IPGR2_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	orl	%esi, %edx
	orl	%eax, %edx
	movq	_REG_MAC_IPG_IFG@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REG
	movq	_MAC_HALF_DUPLX_CTRL_LCOL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	andl	48(%rbx), %edx
	movq	_MAC_HALF_DUPLX_CTRL_RETRY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	40(%rbx), %eax
	movq	_MAC_HALF_DUPLX_CTRL_RETRY_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	orl	%edx, %eax
	movq	_MAC_HALF_DUPLX_CTRL_EXC_DEF_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$10, %esi
	shll	%cl, %esi
	movq	_MAC_HALF_DUPLX_CTRL_JAMIPG_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	andl	32(%rbx), %edx
	movq	_MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	orl	%esi, %edx
	orl	%eax, %edx
	movq	_REG_MAC_HALF_DUPLX_CTRL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REG
	movq	_REG_IRQ_MODU_TIMER_INIT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	124(%rbx), %edx
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REGW
	movq	_REG_MASTER_CTRL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_MASTER_CTRL_ITIMER_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REG
	movq	_REG_CMBDISDMA_TIMER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	120(%rbx), %edx
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REGW
	movq	112(%rbx), %rax
	movq	_ETH_HLEN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	addl	(%rax), %edx
	movq	_REG_MTU@GOTPCREL(%rip), %rax
	movq	_VLAN_HLEN@GOTPCREL(%rip), %rcx
	addl	(%rcx), %edx
	movq	(%rax), %rsi
	movq	_ETH_FCS_LEN@GOTPCREL(%rip), %rax
	addl	(%rax), %edx
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REG
	movq	_REG_TX_CUT_THRESH@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r14, %rdi
	movl	$375, %edx                      ## imm = 0x177
	callq	_ATL2_WRITE_REG
	movq	_REG_PAUSE_ON_TH@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	28(%rbx), %edx
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REGW
	movq	_REG_PAUSE_OFF_TH@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	24(%rbx), %edx
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REGW
	movq	_REG_MB_TXD_WR_IDX@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	104(%rbx), %edx
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REGW
	movq	_REG_MB_RXD_RD_IDX@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	96(%rbx), %edx
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REGW
	movq	_REG_DMAR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DMAR_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REGB
	movq	_REG_DMAW@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DMAW_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_ATL2_WRITE_REGB
	movq	(%r15), %rsi
	movq	%r14, %rdi
	callq	_ATL2_READ_REG
	movq	_ISR_PHY_LINKDOWN@GOTPCREL(%rip), %rcx
	xorl	%ebx, %ebx
	andl	(%rcx), %eax
	setne	%bl
	movq	(%r15), %rsi
	movq	%r14, %rdi
	movl	$1073741823, %edx               ## imm = 0x3FFFFFFF
	callq	_ATL2_WRITE_REG
	movq	(%r15), %rsi
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	_ATL2_WRITE_REG
	movl	%ebx, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_REG_ISR,8,3                    ## @REG_ISR
	.comm	_REG_MAC_STA_ADDR,8,3           ## @REG_MAC_STA_ADDR
	.comm	_REG_DESC_BASE_ADDR_HI,8,3      ## @REG_DESC_BASE_ADDR_HI
	.comm	_REG_TXD_BASE_ADDR_LO,8,3       ## @REG_TXD_BASE_ADDR_LO
	.comm	_REG_TXS_BASE_ADDR_LO,8,3       ## @REG_TXS_BASE_ADDR_LO
	.comm	_REG_RXD_BASE_ADDR_LO,8,3       ## @REG_RXD_BASE_ADDR_LO
	.comm	_REG_TXD_MEM_SIZE,4,2           ## @REG_TXD_MEM_SIZE
	.comm	_REG_TXS_MEM_SIZE,4,2           ## @REG_TXS_MEM_SIZE
	.comm	_REG_RXD_BUF_NUM,4,2            ## @REG_RXD_BUF_NUM
	.comm	_MAC_IPG_IFG_IPGT_MASK,4,2      ## @MAC_IPG_IFG_IPGT_MASK
	.comm	_MAC_IPG_IFG_IPGT_SHIFT,4,2     ## @MAC_IPG_IFG_IPGT_SHIFT
	.comm	_MAC_IPG_IFG_MIFG_MASK,4,2      ## @MAC_IPG_IFG_MIFG_MASK
	.comm	_MAC_IPG_IFG_MIFG_SHIFT,4,2     ## @MAC_IPG_IFG_MIFG_SHIFT
	.comm	_MAC_IPG_IFG_IPGR1_MASK,4,2     ## @MAC_IPG_IFG_IPGR1_MASK
	.comm	_MAC_IPG_IFG_IPGR1_SHIFT,4,2    ## @MAC_IPG_IFG_IPGR1_SHIFT
	.comm	_MAC_IPG_IFG_IPGR2_MASK,4,2     ## @MAC_IPG_IFG_IPGR2_MASK
	.comm	_MAC_IPG_IFG_IPGR2_SHIFT,4,2    ## @MAC_IPG_IFG_IPGR2_SHIFT
	.comm	_REG_MAC_IPG_IFG,8,3            ## @REG_MAC_IPG_IFG
	.comm	_MAC_HALF_DUPLX_CTRL_LCOL_MASK,4,2 ## @MAC_HALF_DUPLX_CTRL_LCOL_MASK
	.comm	_MAC_HALF_DUPLX_CTRL_RETRY_MASK,4,2 ## @MAC_HALF_DUPLX_CTRL_RETRY_MASK
	.comm	_MAC_HALF_DUPLX_CTRL_RETRY_SHIFT,4,2 ## @MAC_HALF_DUPLX_CTRL_RETRY_SHIFT
	.comm	_MAC_HALF_DUPLX_CTRL_EXC_DEF_EN,4,2 ## @MAC_HALF_DUPLX_CTRL_EXC_DEF_EN
	.comm	_MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT,4,2 ## @MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT
	.comm	_MAC_HALF_DUPLX_CTRL_JAMIPG_MASK,4,2 ## @MAC_HALF_DUPLX_CTRL_JAMIPG_MASK
	.comm	_MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT,4,2 ## @MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT
	.comm	_REG_MAC_HALF_DUPLX_CTRL,8,3    ## @REG_MAC_HALF_DUPLX_CTRL
	.comm	_REG_IRQ_MODU_TIMER_INIT,4,2    ## @REG_IRQ_MODU_TIMER_INIT
	.comm	_REG_MASTER_CTRL,8,3            ## @REG_MASTER_CTRL
	.comm	_MASTER_CTRL_ITIMER_EN,4,2      ## @MASTER_CTRL_ITIMER_EN
	.comm	_REG_CMBDISDMA_TIMER,4,2        ## @REG_CMBDISDMA_TIMER
	.comm	_REG_MTU,8,3                    ## @REG_MTU
	.comm	_ETH_HLEN,4,2                   ## @ETH_HLEN
	.comm	_VLAN_HLEN,4,2                  ## @VLAN_HLEN
	.comm	_ETH_FCS_LEN,4,2                ## @ETH_FCS_LEN
	.comm	_REG_TX_CUT_THRESH,8,3          ## @REG_TX_CUT_THRESH
	.comm	_REG_PAUSE_ON_TH,4,2            ## @REG_PAUSE_ON_TH
	.comm	_REG_PAUSE_OFF_TH,4,2           ## @REG_PAUSE_OFF_TH
	.comm	_REG_MB_TXD_WR_IDX,4,2          ## @REG_MB_TXD_WR_IDX
	.comm	_REG_MB_RXD_RD_IDX,4,2          ## @REG_MB_RXD_RD_IDX
	.comm	_REG_DMAR,4,2                   ## @REG_DMAR
	.comm	_DMAR_EN,4,2                    ## @DMAR_EN
	.comm	_REG_DMAW,4,2                   ## @REG_DMAW
	.comm	_DMAW_EN,4,2                    ## @DMAW_EN
	.comm	_ISR_PHY_LINKDOWN,4,2           ## @ISR_PHY_LINKDOWN
	.no_dead_strip	_atl2_configure
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function atl2_configure
_atl2_configure:                        ; @atl2_configure
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x0
	add	x19, x0, #24
Lloh0:
	adrp	x21, _REG_ISR@GOTPAGE
Lloh1:
	ldr	x21, [x21, _REG_ISR@GOTPAGEOFF]
	ldr	x1, [x21]
	mov	x0, x19
	mov	w2, #-1
	bl	_ATL2_WRITE_REG
	ldr	x8, [x20, #88]
	ldr	w9, [x8, #16]
	ldr	w10, [x8, #24]
	lsl	w10, w10, #16
	orr	w9, w10, w9, lsl #24
	ldr	w10, [x8, #32]
	orr	w9, w9, w10, lsl #8
	ldr	w8, [x8, #40]
	orr	w2, w9, w8
Lloh2:
	adrp	x22, _REG_MAC_STA_ADDR@GOTPAGE
Lloh3:
	ldr	x22, [x22, _REG_MAC_STA_ADDR@GOTPAGEOFF]
	ldr	x1, [x22]
	mov	x0, x19
	bl	_ATL2_WRITE_REG
	ldr	x8, [x20, #88]
	ldr	w9, [x8]
	ldr	w8, [x8, #8]
	orr	w2, w8, w9, lsl #8
	ldr	x8, [x22]
	add	x1, x8, #4
	mov	x0, x19
	bl	_ATL2_WRITE_REG
Lloh4:
	adrp	x8, _REG_DESC_BASE_ADDR_HI@GOTPAGE
Lloh5:
	ldr	x8, [x8, _REG_DESC_BASE_ADDR_HI@GOTPAGEOFF]
Lloh6:
	ldr	x1, [x8]
	ldr	w8, [x20]
	asr	w2, w8, #31
	mov	x0, x19
	bl	_ATL2_WRITE_REG
Lloh7:
	adrp	x8, _REG_TXD_BASE_ADDR_LO@GOTPAGE
Lloh8:
	ldr	x8, [x8, _REG_TXD_BASE_ADDR_LO@GOTPAGEOFF]
Lloh9:
	ldr	x1, [x8]
	ldr	w2, [x20, #4]
	mov	x0, x19
	bl	_ATL2_WRITE_REG
Lloh10:
	adrp	x8, _REG_TXS_BASE_ADDR_LO@GOTPAGE
Lloh11:
	ldr	x8, [x8, _REG_TXS_BASE_ADDR_LO@GOTPAGEOFF]
Lloh12:
	ldr	x1, [x8]
	ldr	w2, [x20, #8]
	mov	x0, x19
	bl	_ATL2_WRITE_REG
Lloh13:
	adrp	x8, _REG_RXD_BASE_ADDR_LO@GOTPAGE
Lloh14:
	ldr	x8, [x8, _REG_RXD_BASE_ADDR_LO@GOTPAGEOFF]
Lloh15:
	ldr	x1, [x8]
	ldr	w2, [x20, #12]
	mov	x0, x19
	bl	_ATL2_WRITE_REG
Lloh16:
	adrp	x8, _REG_TXD_MEM_SIZE@GOTPAGE
Lloh17:
	ldr	x8, [x8, _REG_TXD_MEM_SIZE@GOTPAGEOFF]
Lloh18:
	ldr	w1, [x8]
	ldr	w8, [x20, #16]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w2, w8, #2
	mov	x0, x19
	bl	_ATL2_WRITE_REGW
Lloh19:
	adrp	x8, _REG_TXS_MEM_SIZE@GOTPAGE
Lloh20:
	ldr	x8, [x8, _REG_TXS_MEM_SIZE@GOTPAGEOFF]
Lloh21:
	ldr	w1, [x8]
	ldr	w2, [x20, #136]
	mov	x0, x19
	bl	_ATL2_WRITE_REGW
Lloh22:
	adrp	x8, _REG_RXD_BUF_NUM@GOTPAGE
Lloh23:
	ldr	x8, [x8, _REG_RXD_BUF_NUM@GOTPAGEOFF]
Lloh24:
	ldr	w1, [x8]
	ldr	w2, [x20, #128]
	mov	x0, x19
	bl	_ATL2_WRITE_REGW
	ldr	w8, [x20, #80]
Lloh25:
	adrp	x9, _MAC_IPG_IFG_IPGT_MASK@GOTPAGE
Lloh26:
	ldr	x9, [x9, _MAC_IPG_IFG_IPGT_MASK@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
Lloh28:
	adrp	x10, _MAC_IPG_IFG_IPGT_SHIFT@GOTPAGE
Lloh29:
	ldr	x10, [x10, _MAC_IPG_IFG_IPGT_SHIFT@GOTPAGEOFF]
	and	w8, w9, w8
Lloh30:
	ldr	w9, [x10]
	lsl	w8, w8, w9
	ldr	w9, [x20, #72]
Lloh31:
	adrp	x10, _MAC_IPG_IFG_MIFG_MASK@GOTPAGE
Lloh32:
	ldr	x10, [x10, _MAC_IPG_IFG_MIFG_MASK@GOTPAGEOFF]
Lloh33:
	ldr	w10, [x10]
	and	w9, w10, w9
Lloh34:
	adrp	x10, _MAC_IPG_IFG_MIFG_SHIFT@GOTPAGE
Lloh35:
	ldr	x10, [x10, _MAC_IPG_IFG_MIFG_SHIFT@GOTPAGEOFF]
Lloh36:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w8, w9, w8
	ldr	w9, [x20, #64]
Lloh37:
	adrp	x10, _MAC_IPG_IFG_IPGR1_MASK@GOTPAGE
Lloh38:
	ldr	x10, [x10, _MAC_IPG_IFG_IPGR1_MASK@GOTPAGEOFF]
Lloh39:
	ldr	w10, [x10]
	and	w9, w10, w9
Lloh40:
	adrp	x10, _MAC_IPG_IFG_IPGR1_SHIFT@GOTPAGE
Lloh41:
	ldr	x10, [x10, _MAC_IPG_IFG_IPGR1_SHIFT@GOTPAGEOFF]
Lloh42:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w8, w8, w9
	ldr	w9, [x20, #56]
Lloh43:
	adrp	x10, _MAC_IPG_IFG_IPGR2_MASK@GOTPAGE
Lloh44:
	ldr	x10, [x10, _MAC_IPG_IFG_IPGR2_MASK@GOTPAGEOFF]
Lloh45:
	ldr	w10, [x10]
	and	w9, w10, w9
Lloh46:
	adrp	x10, _MAC_IPG_IFG_IPGR2_SHIFT@GOTPAGE
Lloh47:
	ldr	x10, [x10, _MAC_IPG_IFG_IPGR2_SHIFT@GOTPAGEOFF]
Lloh48:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w2, w8, w9
Lloh49:
	adrp	x8, _REG_MAC_IPG_IFG@GOTPAGE
Lloh50:
	ldr	x8, [x8, _REG_MAC_IPG_IFG@GOTPAGEOFF]
Lloh51:
	ldr	x1, [x8]
	mov	x0, x19
	bl	_ATL2_WRITE_REG
Lloh52:
	adrp	x8, _MAC_HALF_DUPLX_CTRL_LCOL_MASK@GOTPAGE
Lloh53:
	ldr	x8, [x8, _MAC_HALF_DUPLX_CTRL_LCOL_MASK@GOTPAGEOFF]
	ldr	w9, [x20, #48]
Lloh54:
	ldr	w8, [x8]
	and	w8, w8, w9
	ldr	w9, [x20, #40]
Lloh55:
	adrp	x10, _MAC_HALF_DUPLX_CTRL_RETRY_MASK@GOTPAGE
Lloh56:
	ldr	x10, [x10, _MAC_HALF_DUPLX_CTRL_RETRY_MASK@GOTPAGEOFF]
Lloh57:
	ldr	w10, [x10]
	and	w9, w10, w9
Lloh58:
	adrp	x10, _MAC_HALF_DUPLX_CTRL_RETRY_SHIFT@GOTPAGE
Lloh59:
	ldr	x10, [x10, _MAC_HALF_DUPLX_CTRL_RETRY_SHIFT@GOTPAGEOFF]
Lloh60:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w8, w9, w8
Lloh61:
	adrp	x9, _MAC_HALF_DUPLX_CTRL_EXC_DEF_EN@GOTPAGE
Lloh62:
	ldr	x9, [x9, _MAC_HALF_DUPLX_CTRL_EXC_DEF_EN@GOTPAGEOFF]
Lloh63:
	ldr	w9, [x9]
Lloh64:
	adrp	x10, _MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT@GOTPAGE
Lloh65:
	ldr	x10, [x10, _MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh66:
	ldr	w9, [x10]
	mov	w10, #10
	lsl	w9, w10, w9
	orr	w8, w8, w9
	ldr	w9, [x20, #32]
Lloh67:
	adrp	x10, _MAC_HALF_DUPLX_CTRL_JAMIPG_MASK@GOTPAGE
Lloh68:
	ldr	x10, [x10, _MAC_HALF_DUPLX_CTRL_JAMIPG_MASK@GOTPAGEOFF]
Lloh69:
	ldr	w10, [x10]
	and	w9, w10, w9
Lloh70:
	adrp	x10, _MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT@GOTPAGE
Lloh71:
	ldr	x10, [x10, _MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT@GOTPAGEOFF]
Lloh72:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w2, w8, w9
Lloh73:
	adrp	x8, _REG_MAC_HALF_DUPLX_CTRL@GOTPAGE
Lloh74:
	ldr	x8, [x8, _REG_MAC_HALF_DUPLX_CTRL@GOTPAGEOFF]
Lloh75:
	ldr	x1, [x8]
	mov	x0, x19
	bl	_ATL2_WRITE_REG
Lloh76:
	adrp	x8, _REG_IRQ_MODU_TIMER_INIT@GOTPAGE
Lloh77:
	ldr	x8, [x8, _REG_IRQ_MODU_TIMER_INIT@GOTPAGEOFF]
Lloh78:
	ldr	w1, [x8]
	ldr	w2, [x20, #124]
	mov	x0, x19
	bl	_ATL2_WRITE_REGW
Lloh79:
	adrp	x8, _REG_MASTER_CTRL@GOTPAGE
Lloh80:
	ldr	x8, [x8, _REG_MASTER_CTRL@GOTPAGEOFF]
Lloh81:
	ldr	x1, [x8]
Lloh82:
	adrp	x8, _MASTER_CTRL_ITIMER_EN@GOTPAGE
Lloh83:
	ldr	x8, [x8, _MASTER_CTRL_ITIMER_EN@GOTPAGEOFF]
Lloh84:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_ATL2_WRITE_REG
Lloh85:
	adrp	x8, _REG_CMBDISDMA_TIMER@GOTPAGE
Lloh86:
	ldr	x8, [x8, _REG_CMBDISDMA_TIMER@GOTPAGEOFF]
Lloh87:
	ldr	w1, [x8]
	ldr	w2, [x20, #120]
	mov	x0, x19
	bl	_ATL2_WRITE_REGW
Lloh88:
	adrp	x8, _REG_MTU@GOTPAGE
Lloh89:
	ldr	x8, [x8, _REG_MTU@GOTPAGEOFF]
Lloh90:
	ldr	x1, [x8]
	ldr	x8, [x20, #112]
	ldr	w8, [x8]
Lloh91:
	adrp	x9, _ETH_HLEN@GOTPAGE
Lloh92:
	ldr	x9, [x9, _ETH_HLEN@GOTPAGEOFF]
Lloh93:
	ldr	w9, [x9]
Lloh94:
	adrp	x10, _VLAN_HLEN@GOTPAGE
Lloh95:
	ldr	x10, [x10, _VLAN_HLEN@GOTPAGEOFF]
Lloh96:
	ldr	w10, [x10]
	add	w8, w9, w8
	add	w8, w8, w10
Lloh97:
	adrp	x9, _ETH_FCS_LEN@GOTPAGE
Lloh98:
	ldr	x9, [x9, _ETH_FCS_LEN@GOTPAGEOFF]
Lloh99:
	ldr	w9, [x9]
	add	w2, w8, w9
	mov	x0, x19
	bl	_ATL2_WRITE_REG
Lloh100:
	adrp	x8, _REG_TX_CUT_THRESH@GOTPAGE
Lloh101:
	ldr	x8, [x8, _REG_TX_CUT_THRESH@GOTPAGEOFF]
Lloh102:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #375
	bl	_ATL2_WRITE_REG
Lloh103:
	adrp	x8, _REG_PAUSE_ON_TH@GOTPAGE
Lloh104:
	ldr	x8, [x8, _REG_PAUSE_ON_TH@GOTPAGEOFF]
Lloh105:
	ldr	w1, [x8]
	ldr	w2, [x20, #28]
	mov	x0, x19
	bl	_ATL2_WRITE_REGW
Lloh106:
	adrp	x8, _REG_PAUSE_OFF_TH@GOTPAGE
Lloh107:
	ldr	x8, [x8, _REG_PAUSE_OFF_TH@GOTPAGEOFF]
Lloh108:
	ldr	w1, [x8]
	ldr	w2, [x20, #24]
	mov	x0, x19
	bl	_ATL2_WRITE_REGW
Lloh109:
	adrp	x8, _REG_MB_TXD_WR_IDX@GOTPAGE
Lloh110:
	ldr	x8, [x8, _REG_MB_TXD_WR_IDX@GOTPAGEOFF]
Lloh111:
	ldr	w1, [x8]
	ldr	w2, [x20, #104]
	mov	x0, x19
	bl	_ATL2_WRITE_REGW
Lloh112:
	adrp	x8, _REG_MB_RXD_RD_IDX@GOTPAGE
Lloh113:
	ldr	x8, [x8, _REG_MB_RXD_RD_IDX@GOTPAGEOFF]
Lloh114:
	ldr	w1, [x8]
	ldr	w2, [x20, #96]
	mov	x0, x19
	bl	_ATL2_WRITE_REGW
Lloh115:
	adrp	x8, _REG_DMAR@GOTPAGE
Lloh116:
	ldr	x8, [x8, _REG_DMAR@GOTPAGEOFF]
Lloh117:
	ldr	w1, [x8]
Lloh118:
	adrp	x8, _DMAR_EN@GOTPAGE
Lloh119:
	ldr	x8, [x8, _DMAR_EN@GOTPAGEOFF]
Lloh120:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_ATL2_WRITE_REGB
Lloh121:
	adrp	x8, _REG_DMAW@GOTPAGE
Lloh122:
	ldr	x8, [x8, _REG_DMAW@GOTPAGEOFF]
Lloh123:
	ldr	w1, [x8]
Lloh124:
	adrp	x8, _DMAW_EN@GOTPAGE
Lloh125:
	ldr	x8, [x8, _DMAW_EN@GOTPAGEOFF]
Lloh126:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_ATL2_WRITE_REGB
	ldr	x1, [x21]
	mov	x0, x19
	bl	_ATL2_READ_REG
Lloh127:
	adrp	x8, _ISR_PHY_LINKDOWN@GOTPAGE
Lloh128:
	ldr	x8, [x8, _ISR_PHY_LINKDOWN@GOTPAGEOFF]
Lloh129:
	ldr	w8, [x8]
	tst	w8, w0
	cset	w20, ne
	ldr	x1, [x21]
	mov	x0, x19
	mov	w2, #1073741823
	bl	_ATL2_WRITE_REG
	ldr	x1, [x21]
	mov	x0, x19
	mov	w2, #0
	bl	_ATL2_WRITE_REG
	mov	x0, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh127, Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.loh AdrpLdrGotLdr	Lloh112, Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_REG_ISR,8,3                    ; @REG_ISR
	.comm	_REG_MAC_STA_ADDR,8,3           ; @REG_MAC_STA_ADDR
	.comm	_REG_DESC_BASE_ADDR_HI,8,3      ; @REG_DESC_BASE_ADDR_HI
	.comm	_REG_TXD_BASE_ADDR_LO,8,3       ; @REG_TXD_BASE_ADDR_LO
	.comm	_REG_TXS_BASE_ADDR_LO,8,3       ; @REG_TXS_BASE_ADDR_LO
	.comm	_REG_RXD_BASE_ADDR_LO,8,3       ; @REG_RXD_BASE_ADDR_LO
	.comm	_REG_TXD_MEM_SIZE,4,2           ; @REG_TXD_MEM_SIZE
	.comm	_REG_TXS_MEM_SIZE,4,2           ; @REG_TXS_MEM_SIZE
	.comm	_REG_RXD_BUF_NUM,4,2            ; @REG_RXD_BUF_NUM
	.comm	_MAC_IPG_IFG_IPGT_MASK,4,2      ; @MAC_IPG_IFG_IPGT_MASK
	.comm	_MAC_IPG_IFG_IPGT_SHIFT,4,2     ; @MAC_IPG_IFG_IPGT_SHIFT
	.comm	_MAC_IPG_IFG_MIFG_MASK,4,2      ; @MAC_IPG_IFG_MIFG_MASK
	.comm	_MAC_IPG_IFG_MIFG_SHIFT,4,2     ; @MAC_IPG_IFG_MIFG_SHIFT
	.comm	_MAC_IPG_IFG_IPGR1_MASK,4,2     ; @MAC_IPG_IFG_IPGR1_MASK
	.comm	_MAC_IPG_IFG_IPGR1_SHIFT,4,2    ; @MAC_IPG_IFG_IPGR1_SHIFT
	.comm	_MAC_IPG_IFG_IPGR2_MASK,4,2     ; @MAC_IPG_IFG_IPGR2_MASK
	.comm	_MAC_IPG_IFG_IPGR2_SHIFT,4,2    ; @MAC_IPG_IFG_IPGR2_SHIFT
	.comm	_REG_MAC_IPG_IFG,8,3            ; @REG_MAC_IPG_IFG
	.comm	_MAC_HALF_DUPLX_CTRL_LCOL_MASK,4,2 ; @MAC_HALF_DUPLX_CTRL_LCOL_MASK
	.comm	_MAC_HALF_DUPLX_CTRL_RETRY_MASK,4,2 ; @MAC_HALF_DUPLX_CTRL_RETRY_MASK
	.comm	_MAC_HALF_DUPLX_CTRL_RETRY_SHIFT,4,2 ; @MAC_HALF_DUPLX_CTRL_RETRY_SHIFT
	.comm	_MAC_HALF_DUPLX_CTRL_EXC_DEF_EN,4,2 ; @MAC_HALF_DUPLX_CTRL_EXC_DEF_EN
	.comm	_MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT,4,2 ; @MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT
	.comm	_MAC_HALF_DUPLX_CTRL_JAMIPG_MASK,4,2 ; @MAC_HALF_DUPLX_CTRL_JAMIPG_MASK
	.comm	_MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT,4,2 ; @MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT
	.comm	_REG_MAC_HALF_DUPLX_CTRL,8,3    ; @REG_MAC_HALF_DUPLX_CTRL
	.comm	_REG_IRQ_MODU_TIMER_INIT,4,2    ; @REG_IRQ_MODU_TIMER_INIT
	.comm	_REG_MASTER_CTRL,8,3            ; @REG_MASTER_CTRL
	.comm	_MASTER_CTRL_ITIMER_EN,4,2      ; @MASTER_CTRL_ITIMER_EN
	.comm	_REG_CMBDISDMA_TIMER,4,2        ; @REG_CMBDISDMA_TIMER
	.comm	_REG_MTU,8,3                    ; @REG_MTU
	.comm	_ETH_HLEN,4,2                   ; @ETH_HLEN
	.comm	_VLAN_HLEN,4,2                  ; @VLAN_HLEN
	.comm	_ETH_FCS_LEN,4,2                ; @ETH_FCS_LEN
	.comm	_REG_TX_CUT_THRESH,8,3          ; @REG_TX_CUT_THRESH
	.comm	_REG_PAUSE_ON_TH,4,2            ; @REG_PAUSE_ON_TH
	.comm	_REG_PAUSE_OFF_TH,4,2           ; @REG_PAUSE_OFF_TH
	.comm	_REG_MB_TXD_WR_IDX,4,2          ; @REG_MB_TXD_WR_IDX
	.comm	_REG_MB_RXD_RD_IDX,4,2          ; @REG_MB_RXD_RD_IDX
	.comm	_REG_DMAR,4,2                   ; @REG_DMAR
	.comm	_DMAR_EN,4,2                    ; @DMAR_EN
	.comm	_REG_DMAW,4,2                   ; @REG_DMAW
	.comm	_DMAW_EN,4,2                    ; @DMAW_EN
	.comm	_ISR_PHY_LINKDOWN,4,2           ; @ISR_PHY_LINKDOWN
	.no_dead_strip	_atl2_configure
.subsections_via_symbols
