	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function msm_get_clock_rate_for_bus_mode
_msm_get_clock_rate_for_bus_mode:       ## @msm_get_clock_rate_for_bus_mode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movl	%esi, %eax
	movq	8(%rdi), %rcx
	movq	(%rcx), %rcx
	movq	_MMC_TIMING_UHS_DDR50@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	je	LBB0_4
## %bb.1:
	movq	_MMC_TIMING_MMC_DDR52@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	je	LBB0_4
## %bb.2:
	movq	_MMC_TIMING_MMC_HS400@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	je	LBB0_4
## %bb.3:
	movq	_SDHCI_HS400_TUNING@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, (%rdi)
	je	LBB0_5
LBB0_4:
	addl	%eax, %eax
LBB0_5:
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MMC_TIMING_UHS_DDR50,8,3       ## @MMC_TIMING_UHS_DDR50
	.comm	_MMC_TIMING_MMC_DDR52,8,3       ## @MMC_TIMING_MMC_DDR52
	.comm	_MMC_TIMING_MMC_HS400,8,3       ## @MMC_TIMING_MMC_HS400
	.comm	_SDHCI_HS400_TUNING,4,2         ## @SDHCI_HS400_TUNING
	.no_dead_strip	_msm_get_clock_rate_for_bus_mode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function msm_get_clock_rate_for_bus_mode
_msm_get_clock_rate_for_bus_mode:       ; @msm_get_clock_rate_for_bus_mode
	.cfi_startproc
; %bb.0:
	ldr	x8, [x0, #8]
	ldr	x8, [x8]
Lloh0:
	adrp	x9, _MMC_TIMING_UHS_DDR50@GOTPAGE
Lloh1:
	ldr	x9, [x9, _MMC_TIMING_UHS_DDR50@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
Lloh3:
	adrp	x10, _MMC_TIMING_MMC_DDR52@GOTPAGE
Lloh4:
	ldr	x10, [x10, _MMC_TIMING_MMC_DDR52@GOTPAGEOFF]
Lloh5:
	ldr	x10, [x10]
Lloh6:
	adrp	x11, _MMC_TIMING_MMC_HS400@GOTPAGE
Lloh7:
	ldr	x11, [x11, _MMC_TIMING_MMC_HS400@GOTPAGEOFF]
Lloh8:
	ldr	x11, [x11]
	cmp	x8, x9
	ccmp	x8, x10, #4, ne
	ccmp	x8, x11, #4, ne
	b.eq	LBB0_2
; %bb.1:
	ldr	w8, [x0]
Lloh9:
	adrp	x9, _SDHCI_HS400_TUNING@GOTPAGE
Lloh10:
	ldr	x9, [x9, _SDHCI_HS400_TUNING@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_3
LBB0_2:
	lsl	w1, w1, #1
LBB0_3:
	mov	x0, x1
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.cfi_endproc
                                        ; -- End function
	.comm	_MMC_TIMING_UHS_DDR50,8,3       ; @MMC_TIMING_UHS_DDR50
	.comm	_MMC_TIMING_MMC_DDR52,8,3       ; @MMC_TIMING_MMC_DDR52
	.comm	_MMC_TIMING_MMC_HS400,8,3       ; @MMC_TIMING_MMC_HS400
	.comm	_SDHCI_HS400_TUNING,4,2         ; @SDHCI_HS400_TUNING
	.no_dead_strip	_msm_get_clock_rate_for_bus_mode
.subsections_via_symbols
