	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function sunxi_mmc_clk_set_rate
_sunxi_mmc_clk_set_rate:                ## @sunxi_mmc_clk_set_rate
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r15
	movq	%rdi, %r12
	movq	24(%rdi), %r14
	movl	(%rsi), %r13d
	xorl	%esi, %esi
	callq	_sunxi_mmc_oclk_onoff
	movl	%eax, %ebx
	testl	%eax, %eax
	je	LBB0_1
LBB0_25:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_1:
	movq	$0, (%r14)
	cmpl	$0, (%r15)
	je	LBB0_24
## %bb.2:
	movq	8(%r15), %rcx
	movq	_MMC_TIMING_MMC_DDR52@GOTPCREL(%rip), %rdx
	movq	(%r12), %rax
	movl	$1, %esi
	cmpq	(%rdx), %rcx
	jne	LBB0_9
## %bb.3:
	testq	%rax, %rax
	jne	LBB0_8
## %bb.4:
	movq	16(%r15), %rcx
	movq	_MMC_BUS_WIDTH_8@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_5
LBB0_8:
	addl	%r13d, %r13d
	movl	$2, %esi
LBB0_9:
	testq	%rax, %rax
	movq	%rsi, -48(%rbp)                 ## 8-byte Spill
	je	LBB0_6
## %bb.10:
	movq	16(%r12), %rax
	cmpq	$0, (%rax)
	je	LBB0_6
## %bb.11:
	movl	8(%r12), %edi
	movl	$1, %esi
	callq	_sunxi_ccu_set_mmc_timing_mode
	testl	%eax, %eax
	je	LBB0_6
## %bb.12:
	movl	%eax, %ebx
	movq	%r14, %rdi
	callq	_mmc_dev
	leaq	L_.str(%rip), %rsi
	movl	%eax, %edi
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_25
LBB0_5:
	movl	$1, %eax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
LBB0_6:
	movl	8(%r12), %edi
	movl	%r13d, %esi
	callq	_clk_round_rate
	movq	%rax, %rbx
	movq	%r14, %rdi
	callq	_mmc_dev
	testq	%rbx, %rbx
	js	LBB0_7
## %bb.13:
	leaq	L_.str.2(%rip), %rsi
	movl	%eax, %edi
	movl	%r13d, %edx
	movq	%rbx, %rcx
	callq	_dev_dbg
	movl	8(%r12), %edi
	movq	%rbx, %rsi
	callq	_clk_set_rate
	testl	%eax, %eax
	je	LBB0_15
## %bb.14:
	movl	%eax, %r13d
	movq	%r14, %rdi
	callq	_mmc_dev
	leaq	L_.str.3(%rip), %rsi
	movl	%eax, %edi
	movq	%rbx, %rdx
	movl	%r13d, %ecx
	xorl	%eax, %eax
	callq	_dev_err
	movl	%r13d, %ebx
	jmp	LBB0_25
LBB0_7:
	leaq	L_.str.1(%rip), %rsi
	movl	%eax, %edi
	movl	%r13d, %edx
	movq	%rbx, %rcx
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_25
LBB0_15:
	movq	_REG_CLKCR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_mmc_readl
	andl	$-256, %eax
	movq	-48(%rbp), %r13                 ## 8-byte Reload
	leal	-1(%r13), %edx
	orl	%eax, %edx
	movq	_REG_CLKCR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_mmc_writel
	movl	%r13d, %ecx
	movq	%rbx, %rax
	shrq	$32, %rax
	je	LBB0_16
## %bb.17:
	movq	%rbx, %rax
	xorl	%edx, %edx
	divq	%rcx
	movq	%rax, %r13
	jmp	LBB0_18
LBB0_16:
	movl	%ebx, %eax
	xorl	%edx, %edx
	divl	%ecx
	movl	%eax, %r13d
LBB0_18:
	cmpq	$0, (%r12)
	je	LBB0_20
## %bb.19:
	movq	_REG_SD_NTSR@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_mmc_readl
	movq	_SDXC_2X_TIMING_MODE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %esi
	movq	%r12, %rdi
	movl	%eax, %edx
	callq	_mmc_writel
LBB0_20:
	movq	%r12, %rdi
	movq	%r15, %rsi
	movq	%r13, %rdx
	callq	_sunxi_mmc_clk_set_phase
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_25
## %bb.21:
	movq	_SDXC_REG_SAMP_DL_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_sunxi_mmc_calibrate
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_25
## %bb.22:
	movq	%r12, %rdi
	movl	$1, %esi
	callq	_sunxi_mmc_oclk_onoff
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_25
## %bb.23:
	movq	%r13, (%r14)
LBB0_24:
	xorl	%ebx, %ebx
	jmp	LBB0_25
	.cfi_endproc
                                        ## -- End function
	.comm	_MMC_TIMING_MMC_DDR52,8,3       ## @MMC_TIMING_MMC_DDR52
	.comm	_MMC_BUS_WIDTH_8,8,3            ## @MMC_BUS_WIDTH_8
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"error setting new timing mode\n"

L_.str.1:                               ## @.str.1
	.asciz	"error rounding clk to %d: %ld\n"

L_.str.2:                               ## @.str.2
	.asciz	"setting clk to %d, rounded %ld\n"

L_.str.3:                               ## @.str.3
	.asciz	"error setting clk to %ld: %d\n"

	.comm	_REG_CLKCR,4,2                  ## @REG_CLKCR
	.comm	_REG_SD_NTSR,4,2                ## @REG_SD_NTSR
	.comm	_SDXC_2X_TIMING_MODE,4,2        ## @SDXC_2X_TIMING_MODE
	.comm	_SDXC_REG_SAMP_DL_REG,4,2       ## @SDXC_REG_SAMP_DL_REG
	.no_dead_strip	_sunxi_mmc_clk_set_rate
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function sunxi_mmc_clk_set_rate
_sunxi_mmc_clk_set_rate:                ; @sunxi_mmc_clk_set_rate
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x21, x1
	mov	x20, x0
	ldr	x19, [x0, #24]
	ldr	w23, [x1]
	mov	w1, #0
	bl	_sunxi_mmc_oclk_onoff
	mov	x22, x0
	cbz	w0, LBB0_2
LBB0_1:
	mov	x0, x22
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
LBB0_2:
	str	xzr, [x19]
	ldr	w8, [x21]
	cbz	w8, LBB0_7
; %bb.3:
	ldr	x9, [x21, #8]
Lloh0:
	adrp	x8, _MMC_TIMING_MMC_DDR52@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MMC_TIMING_MMC_DDR52@GOTPAGEOFF]
Lloh2:
	ldr	x10, [x8]
	ldr	x8, [x20]
	cmp	x9, x10
	b.ne	LBB0_8
; %bb.4:
	cbnz	x8, LBB0_6
; %bb.5:
	ldr	x9, [x21, #16]
Lloh3:
	adrp	x10, _MMC_BUS_WIDTH_8@GOTPAGE
Lloh4:
	ldr	x10, [x10, _MMC_BUS_WIDTH_8@GOTPAGEOFF]
Lloh5:
	ldr	x10, [x10]
	cmp	x9, x10
	b.ne	LBB0_12
LBB0_6:
	lsl	w23, w23, #1
	mov	w24, #2
	cbnz	x8, LBB0_9
	b	LBB0_13
LBB0_7:
	mov	w22, #0
	b	LBB0_1
LBB0_8:
	mov	w24, #1
	cbz	x8, LBB0_13
LBB0_9:
	ldr	x8, [x20, #16]
	ldr	x8, [x8]
	cbz	x8, LBB0_13
; %bb.10:
	ldr	w0, [x20, #8]
	mov	w1, #1
	bl	_sunxi_ccu_set_mmc_timing_mode
	cbz	w0, LBB0_13
; %bb.11:
	mov	x22, x0
	mov	x0, x19
	bl	_mmc_dev
Lloh6:
	adrp	x1, l_.str@PAGE
Lloh7:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
	b	LBB0_1
LBB0_12:
	mov	w24, #1
LBB0_13:
	ldr	w0, [x20, #8]
	mov	x1, x23
	bl	_clk_round_rate
	mov	x22, x0
	mov	x0, x19
	bl	_mmc_dev
	tbnz	x22, #63, LBB0_16
; %bb.14:
Lloh8:
	adrp	x1, l_.str.2@PAGE
Lloh9:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x2, x23
	mov	x3, x22
	bl	_dev_dbg
	ldr	w0, [x20, #8]
	mov	x1, x22
	bl	_clk_set_rate
	cbz	w0, LBB0_17
; %bb.15:
	mov	x23, x0
	mov	x0, x19
	bl	_mmc_dev
	stp	x22, x23, [sp]
Lloh10:
	adrp	x1, l_.str.3@PAGE
Lloh11:
	add	x1, x1, l_.str.3@PAGEOFF
	bl	_dev_err
	mov	x22, x23
	b	LBB0_1
LBB0_16:
	stp	x23, x22, [sp]
Lloh12:
	adrp	x1, l_.str.1@PAGE
Lloh13:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_err
	b	LBB0_1
LBB0_17:
Lloh14:
	adrp	x23, _REG_CLKCR@GOTPAGE
Lloh15:
	ldr	x23, [x23, _REG_CLKCR@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x20
	bl	_mmc_readl
	and	w8, w0, #0xffffff00
	sub	w9, w24, #1
	orr	w2, w8, w9
	ldr	w1, [x23]
	mov	x0, x20
	bl	_mmc_writel
	mov	w8, w24
	ldr	x9, [x20]
	udiv	x23, x22, x8
	cbz	x9, LBB0_19
; %bb.18:
Lloh16:
	adrp	x22, _REG_SD_NTSR@GOTPAGE
Lloh17:
	ldr	x22, [x22, _REG_SD_NTSR@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x20
	bl	_mmc_readl
Lloh18:
	adrp	x8, _SDXC_2X_TIMING_MODE@GOTPAGE
Lloh19:
	ldr	x8, [x8, _SDXC_2X_TIMING_MODE@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	orr	w2, w8, w0
	ldr	w1, [x22]
	mov	x0, x20
	bl	_mmc_writel
LBB0_19:
	mov	x0, x20
	mov	x1, x21
	mov	x2, x23
	bl	_sunxi_mmc_clk_set_phase
	mov	x22, x0
	cbnz	w0, LBB0_1
; %bb.20:
Lloh21:
	adrp	x8, _SDXC_REG_SAMP_DL_REG@GOTPAGE
Lloh22:
	ldr	x8, [x8, _SDXC_REG_SAMP_DL_REG@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_sunxi_mmc_calibrate
	mov	x22, x0
	cbnz	w0, LBB0_1
; %bb.21:
	mov	x0, x20
	mov	w1, #1
	bl	_sunxi_mmc_oclk_onoff
	mov	x22, x0
	cbnz	w0, LBB0_1
; %bb.22:
	str	x23, [x19]
	b	LBB0_1
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpAdd	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.cfi_endproc
                                        ; -- End function
	.comm	_MMC_TIMING_MMC_DDR52,8,3       ; @MMC_TIMING_MMC_DDR52
	.comm	_MMC_BUS_WIDTH_8,8,3            ; @MMC_BUS_WIDTH_8
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"error setting new timing mode\n"

l_.str.1:                               ; @.str.1
	.asciz	"error rounding clk to %d: %ld\n"

l_.str.2:                               ; @.str.2
	.asciz	"setting clk to %d, rounded %ld\n"

l_.str.3:                               ; @.str.3
	.asciz	"error setting clk to %ld: %d\n"

	.comm	_REG_CLKCR,4,2                  ; @REG_CLKCR
	.comm	_REG_SD_NTSR,4,2                ; @REG_SD_NTSR
	.comm	_SDXC_2X_TIMING_MODE,4,2        ; @SDXC_2X_TIMING_MODE
	.comm	_SDXC_REG_SAMP_DL_REG,4,2       ; @SDXC_REG_SAMP_DL_REG
	.no_dead_strip	_sunxi_mmc_clk_set_rate
.subsections_via_symbols
