	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_cxl_irq_psl8                   ## -- Begin function cxl_irq_psl8
	.p2align	4, 0x90
_cxl_irq_psl8:                          ## @cxl_irq_psl8
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r15
	movq	%rsi, %r14
	movl	%edi, %ebx
	movl	(%rdx), %r13d
	movl	4(%rdx), %r12d
	movq	%rsi, %rdi
	movl	%ebx, %esi
	movl	%r13d, %edx
	movl	%r12d, %ecx
	callq	_trace_cxl_psl_irq
	movl	16(%r14), %edx
	leaq	L_.str(%rip), %rdi
	movl	%ebx, %esi
	movl	%r13d, %ecx
	movl	%r12d, %r8d
	xorl	%eax, %eax
	callq	_pr_devel
	movq	_CXL_PSL_DSISR_An_DS@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_3
## %bb.1:
	movl	16(%r14), %esi
	leaq	L_.str.1(%rip), %rdi
	jmp	LBB0_2
LBB0_3:
	movq	_CXL_PSL_DSISR_An_M@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_5
## %bb.4:
	leaq	L_.str.2(%rip), %rdi
	xorl	%eax, %eax
	callq	_pr_devel
LBB0_5:
	movq	_CXL_PSL_DSISR_An_P@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_7
## %bb.6:
	leaq	L_.str.3(%rip), %rdi
	xorl	%eax, %eax
	callq	_pr_devel
LBB0_7:
	movq	_CXL_PSL_DSISR_An_A@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_9
## %bb.8:
	leaq	L_.str.4(%rip), %rdi
	xorl	%eax, %eax
	callq	_pr_devel
LBB0_9:
	movq	_CXL_PSL_DSISR_An_S@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_11
## %bb.10:
	leaq	L_.str.5(%rip), %rdi
	xorl	%eax, %eax
	callq	_pr_devel
LBB0_11:
	movq	_CXL_PSL_DSISR_An_K@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_13
## %bb.12:
	leaq	L_.str.6(%rip), %rdi
	xorl	%eax, %eax
	callq	_pr_devel
LBB0_13:
	movq	_CXL_PSL_DSISR_An_DM@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_15
## %bb.14:
	movl	16(%r14), %esi
	leaq	L_.str.7(%rip), %rdi
LBB0_2:
	xorl	%eax, %eax
	callq	_pr_devel
	movq	%r14, %rdi
	movl	%r13d, %esi
	movl	%r12d, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_schedule_cxl_fault             ## TAILCALL
LBB0_15:
	movq	_CXL_PSL_DSISR_An_ST@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_17
## %bb.16:
	leaq	L_.str.8(%rip), %rsi
	movl	$1, %edi
	callq	_WARN
LBB0_17:
	movq	_CXL_PSL_DSISR_An_UR@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_19
## %bb.18:
	leaq	L_.str.9(%rip), %rdi
	xorl	%eax, %eax
	callq	_pr_devel
LBB0_19:
	movq	_CXL_PSL_DSISR_An_PE@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_20
## %bb.29:
	movq	_cxl_ops@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	8(%rax), %rax
	movl	12(%r15), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmpq	*%rax                           ## TAILCALL
LBB0_20:
	movq	_CXL_PSL_DSISR_An_AE@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_25
## %bb.21:
	movl	8(%r15), %esi
	leaq	L_.str.10(%rip), %rdi
	xorl	%eax, %eax
	callq	_pr_devel
	cmpl	$0, (%r14)
	je	LBB0_23
## %bb.22:
	movq	24(%r14), %rdi
	movl	16(%r14), %edx
	movl	8(%r15), %ecx
	leaq	L_.str.11(%rip), %rsi
	callq	_dev_err_ratelimited
	jmp	LBB0_24
LBB0_25:
	movq	_CXL_PSL_DSISR_An_OC@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_27
## %bb.26:
	leaq	L_.str.12(%rip), %rdi
	xorl	%eax, %eax
	callq	_pr_devel
LBB0_27:
	leaq	L_.str.13(%rip), %rsi
	movl	$1, %edi
	callq	_WARN
	jmp	LBB0_28
LBB0_23:
	leaq	8(%r14), %rbx
	movq	%rbx, %rdi
	callq	_spin_lock
	movl	8(%r15), %eax
	movl	%eax, 12(%r14)
	movl	$1, (%r14)
	movq	%rbx, %rdi
	callq	_spin_unlock
	leaq	4(%r14), %rdi
	callq	_wake_up_all
LBB0_24:
	movq	_cxl_ops@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_CXL_PSL_TFC_An_A@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	*(%rax)
LBB0_28:
	movq	_IRQ_HANDLED@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n"

	.comm	_CXL_PSL_DSISR_An_DS,4,2        ## @CXL_PSL_DSISR_An_DS
L_.str.1:                               ## @.str.1
	.asciz	"Scheduling segment miss handling for later pe: %i\n"

	.comm	_CXL_PSL_DSISR_An_M,4,2         ## @CXL_PSL_DSISR_An_M
L_.str.2:                               ## @.str.2
	.asciz	"CXL interrupt: PTE not found\n"

	.comm	_CXL_PSL_DSISR_An_P,4,2         ## @CXL_PSL_DSISR_An_P
L_.str.3:                               ## @.str.3
	.asciz	"CXL interrupt: Storage protection violation\n"

	.comm	_CXL_PSL_DSISR_An_A,4,2         ## @CXL_PSL_DSISR_An_A
L_.str.4:                               ## @.str.4
	.asciz	"CXL interrupt: AFU lock access to write through or cache inhibited storage\n"

	.comm	_CXL_PSL_DSISR_An_S,4,2         ## @CXL_PSL_DSISR_An_S
L_.str.5:                               ## @.str.5
	.asciz	"CXL interrupt: Access was afu_wr or afu_zero\n"

	.comm	_CXL_PSL_DSISR_An_K,4,2         ## @CXL_PSL_DSISR_An_K
L_.str.6:                               ## @.str.6
	.asciz	"CXL interrupt: Access not permitted by virtual page class key protection\n"

	.comm	_CXL_PSL_DSISR_An_DM,4,2        ## @CXL_PSL_DSISR_An_DM
L_.str.7:                               ## @.str.7
	.asciz	"Scheduling page fault handling for later pe: %i\n"

	.comm	_CXL_PSL_DSISR_An_ST,4,2        ## @CXL_PSL_DSISR_An_ST
L_.str.8:                               ## @.str.8
	.asciz	"CXL interrupt: Segment Table PTE not found\n"

	.comm	_CXL_PSL_DSISR_An_UR,4,2        ## @CXL_PSL_DSISR_An_UR
L_.str.9:                               ## @.str.9
	.asciz	"CXL interrupt: AURP PTE not found\n"

	.comm	_CXL_PSL_DSISR_An_PE,4,2        ## @CXL_PSL_DSISR_An_PE
	.comm	_cxl_ops,8,3                    ## @cxl_ops
	.comm	_CXL_PSL_DSISR_An_AE,4,2        ## @CXL_PSL_DSISR_An_AE
L_.str.10:                              ## @.str.10
	.asciz	"CXL interrupt: AFU Error 0x%016llx\n"

L_.str.11:                              ## @.str.11
	.asciz	"CXL AFU Error undelivered to pe %i: 0x%016llx\n"

	.comm	_CXL_PSL_TFC_An_A,4,2           ## @CXL_PSL_TFC_An_A
	.comm	_IRQ_HANDLED,4,2                ## @IRQ_HANDLED
	.comm	_CXL_PSL_DSISR_An_OC,4,2        ## @CXL_PSL_DSISR_An_OC
L_.str.12:                              ## @.str.12
	.asciz	"CXL interrupt: OS Context Warning\n"

L_.str.13:                              ## @.str.13
	.asciz	"Unhandled CXL PSL IRQ\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_cxl_irq_psl8                   ; -- Begin function cxl_irq_psl8
	.p2align	2
_cxl_irq_psl8:                          ; @cxl_irq_psl8
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x21, x2
	mov	x19, x1
	mov	x23, x0
	ldp	w20, w22, [x2]
	mov	x0, x1
	mov	x1, x23
	mov	x2, x20
	mov	x3, x22
	bl	_trace_cxl_psl_irq
	ldr	w8, [x19, #16]
	stp	x20, x22, [sp, #16]
	stp	x23, x8, [sp]
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_pr_devel
Lloh2:
	adrp	x8, _CXL_PSL_DSISR_An_DS@GOTPAGE
Lloh3:
	ldr	x8, [x8, _CXL_PSL_DSISR_An_DS@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_2
; %bb.1:
	ldr	w8, [x19, #16]
	str	x8, [sp]
Lloh5:
	adrp	x0, l_.str.1@PAGE
Lloh6:
	add	x0, x0, l_.str.1@PAGEOFF
	b	LBB0_14
LBB0_2:
Lloh7:
	adrp	x8, _CXL_PSL_DSISR_An_M@GOTPAGE
Lloh8:
	ldr	x8, [x8, _CXL_PSL_DSISR_An_M@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_4
; %bb.3:
Lloh10:
	adrp	x0, l_.str.2@PAGE
Lloh11:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	_pr_devel
LBB0_4:
Lloh12:
	adrp	x8, _CXL_PSL_DSISR_An_P@GOTPAGE
Lloh13:
	ldr	x8, [x8, _CXL_PSL_DSISR_An_P@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_6
; %bb.5:
Lloh15:
	adrp	x0, l_.str.3@PAGE
Lloh16:
	add	x0, x0, l_.str.3@PAGEOFF
	bl	_pr_devel
LBB0_6:
Lloh17:
	adrp	x8, _CXL_PSL_DSISR_An_A@GOTPAGE
Lloh18:
	ldr	x8, [x8, _CXL_PSL_DSISR_An_A@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_8
; %bb.7:
Lloh20:
	adrp	x0, l_.str.4@PAGE
Lloh21:
	add	x0, x0, l_.str.4@PAGEOFF
	bl	_pr_devel
LBB0_8:
Lloh22:
	adrp	x8, _CXL_PSL_DSISR_An_S@GOTPAGE
Lloh23:
	ldr	x8, [x8, _CXL_PSL_DSISR_An_S@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_10
; %bb.9:
Lloh25:
	adrp	x0, l_.str.5@PAGE
Lloh26:
	add	x0, x0, l_.str.5@PAGEOFF
	bl	_pr_devel
LBB0_10:
Lloh27:
	adrp	x8, _CXL_PSL_DSISR_An_K@GOTPAGE
Lloh28:
	ldr	x8, [x8, _CXL_PSL_DSISR_An_K@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_12
; %bb.11:
Lloh30:
	adrp	x0, l_.str.6@PAGE
Lloh31:
	add	x0, x0, l_.str.6@PAGEOFF
	bl	_pr_devel
LBB0_12:
Lloh32:
	adrp	x8, _CXL_PSL_DSISR_An_DM@GOTPAGE
Lloh33:
	ldr	x8, [x8, _CXL_PSL_DSISR_An_DM@GOTPAGEOFF]
Lloh34:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_15
; %bb.13:
	ldr	w8, [x19, #16]
	str	x8, [sp]
Lloh35:
	adrp	x0, l_.str.7@PAGE
Lloh36:
	add	x0, x0, l_.str.7@PAGEOFF
LBB0_14:
	bl	_pr_devel
	mov	x0, x19
	mov	x1, x20
	mov	x2, x22
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #96
	b	_schedule_cxl_fault
LBB0_15:
Lloh37:
	adrp	x8, _CXL_PSL_DSISR_An_ST@GOTPAGE
Lloh38:
	ldr	x8, [x8, _CXL_PSL_DSISR_An_ST@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_17
; %bb.16:
Lloh40:
	adrp	x1, l_.str.8@PAGE
Lloh41:
	add	x1, x1, l_.str.8@PAGEOFF
	mov	w0, #1
	bl	_WARN
LBB0_17:
Lloh42:
	adrp	x8, _CXL_PSL_DSISR_An_UR@GOTPAGE
Lloh43:
	ldr	x8, [x8, _CXL_PSL_DSISR_An_UR@GOTPAGEOFF]
Lloh44:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_19
; %bb.18:
Lloh45:
	adrp	x0, l_.str.9@PAGE
Lloh46:
	add	x0, x0, l_.str.9@PAGEOFF
	bl	_pr_devel
LBB0_19:
Lloh47:
	adrp	x8, _CXL_PSL_DSISR_An_PE@GOTPAGE
Lloh48:
	ldr	x8, [x8, _CXL_PSL_DSISR_An_PE@GOTPAGEOFF]
Lloh49:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_21
; %bb.20:
Lloh50:
	adrp	x8, _cxl_ops@GOTPAGE
Lloh51:
	ldr	x8, [x8, _cxl_ops@GOTPAGEOFF]
Lloh52:
	ldr	x8, [x8]
	ldr	x3, [x8, #8]
	ldr	w2, [x21, #12]
	mov	x0, x19
	mov	x1, x20
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #96
	br	x3
LBB0_21:
Lloh53:
	adrp	x8, _CXL_PSL_DSISR_An_AE@GOTPAGE
Lloh54:
	ldr	x8, [x8, _CXL_PSL_DSISR_An_AE@GOTPAGEOFF]
Lloh55:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_24
; %bb.22:
	ldr	w8, [x21, #8]
	str	x8, [sp]
Lloh56:
	adrp	x0, l_.str.10@PAGE
Lloh57:
	add	x0, x0, l_.str.10@PAGEOFF
	bl	_pr_devel
	ldr	w8, [x19]
	cbz	w8, LBB0_27
; %bb.23:
	ldr	x0, [x19, #24]
	ldr	w2, [x19, #16]
	ldr	w3, [x21, #8]
Lloh58:
	adrp	x1, l_.str.11@PAGE
Lloh59:
	add	x1, x1, l_.str.11@PAGEOFF
	bl	_dev_err_ratelimited
	b	LBB0_28
LBB0_24:
Lloh60:
	adrp	x8, _CXL_PSL_DSISR_An_OC@GOTPAGE
Lloh61:
	ldr	x8, [x8, _CXL_PSL_DSISR_An_OC@GOTPAGEOFF]
Lloh62:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_26
; %bb.25:
Lloh63:
	adrp	x0, l_.str.12@PAGE
Lloh64:
	add	x0, x0, l_.str.12@PAGEOFF
	bl	_pr_devel
LBB0_26:
Lloh65:
	adrp	x1, l_.str.13@PAGE
Lloh66:
	add	x1, x1, l_.str.13@PAGEOFF
	mov	w0, #1
	bl	_WARN
	b	LBB0_29
LBB0_27:
	add	x20, x19, #8
	mov	x0, x20
	bl	_spin_lock
	ldr	w8, [x21, #8]
	str	w8, [x19, #12]
	mov	w8, #1
	str	w8, [x19]
	mov	x0, x20
	bl	_spin_unlock
	add	x0, x19, #4
	bl	_wake_up_all
LBB0_28:
Lloh67:
	adrp	x8, _cxl_ops@GOTPAGE
Lloh68:
	ldr	x8, [x8, _cxl_ops@GOTPAGEOFF]
Lloh69:
	ldr	x8, [x8]
	ldr	x8, [x8]
Lloh70:
	adrp	x9, _CXL_PSL_TFC_An_A@GOTPAGE
Lloh71:
	ldr	x9, [x9, _CXL_PSL_TFC_An_A@GOTPAGEOFF]
Lloh72:
	ldr	w1, [x9]
	mov	x0, x19
	mov	w2, #0
	blr	x8
LBB0_29:
Lloh73:
	adrp	x8, _IRQ_HANDLED@GOTPAGE
Lloh74:
	ldr	x8, [x8, _IRQ_HANDLED@GOTPAGEOFF]
Lloh75:
	ldr	w0, [x8]
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpAdd	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpAdd	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpAdd	Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpAdd	Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpAdd	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpAdd	Lloh56, Lloh57
	.loh AdrpAdd	Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpAdd	Lloh63, Lloh64
	.loh AdrpAdd	Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n"

	.comm	_CXL_PSL_DSISR_An_DS,4,2        ; @CXL_PSL_DSISR_An_DS
l_.str.1:                               ; @.str.1
	.asciz	"Scheduling segment miss handling for later pe: %i\n"

	.comm	_CXL_PSL_DSISR_An_M,4,2         ; @CXL_PSL_DSISR_An_M
l_.str.2:                               ; @.str.2
	.asciz	"CXL interrupt: PTE not found\n"

	.comm	_CXL_PSL_DSISR_An_P,4,2         ; @CXL_PSL_DSISR_An_P
l_.str.3:                               ; @.str.3
	.asciz	"CXL interrupt: Storage protection violation\n"

	.comm	_CXL_PSL_DSISR_An_A,4,2         ; @CXL_PSL_DSISR_An_A
l_.str.4:                               ; @.str.4
	.asciz	"CXL interrupt: AFU lock access to write through or cache inhibited storage\n"

	.comm	_CXL_PSL_DSISR_An_S,4,2         ; @CXL_PSL_DSISR_An_S
l_.str.5:                               ; @.str.5
	.asciz	"CXL interrupt: Access was afu_wr or afu_zero\n"

	.comm	_CXL_PSL_DSISR_An_K,4,2         ; @CXL_PSL_DSISR_An_K
l_.str.6:                               ; @.str.6
	.asciz	"CXL interrupt: Access not permitted by virtual page class key protection\n"

	.comm	_CXL_PSL_DSISR_An_DM,4,2        ; @CXL_PSL_DSISR_An_DM
l_.str.7:                               ; @.str.7
	.asciz	"Scheduling page fault handling for later pe: %i\n"

	.comm	_CXL_PSL_DSISR_An_ST,4,2        ; @CXL_PSL_DSISR_An_ST
l_.str.8:                               ; @.str.8
	.asciz	"CXL interrupt: Segment Table PTE not found\n"

	.comm	_CXL_PSL_DSISR_An_UR,4,2        ; @CXL_PSL_DSISR_An_UR
l_.str.9:                               ; @.str.9
	.asciz	"CXL interrupt: AURP PTE not found\n"

	.comm	_CXL_PSL_DSISR_An_PE,4,2        ; @CXL_PSL_DSISR_An_PE
	.comm	_cxl_ops,8,3                    ; @cxl_ops
	.comm	_CXL_PSL_DSISR_An_AE,4,2        ; @CXL_PSL_DSISR_An_AE
l_.str.10:                              ; @.str.10
	.asciz	"CXL interrupt: AFU Error 0x%016llx\n"

l_.str.11:                              ; @.str.11
	.asciz	"CXL AFU Error undelivered to pe %i: 0x%016llx\n"

	.comm	_CXL_PSL_TFC_An_A,4,2           ; @CXL_PSL_TFC_An_A
	.comm	_IRQ_HANDLED,4,2                ; @IRQ_HANDLED
	.comm	_CXL_PSL_DSISR_An_OC,4,2        ; @CXL_PSL_DSISR_An_OC
l_.str.12:                              ; @.str.12
	.asciz	"CXL interrupt: OS Context Warning\n"

l_.str.13:                              ; @.str.13
	.asciz	"Unhandled CXL PSL IRQ\n"

.subsections_via_symbols
