	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function bnx2_init_nvram
_bnx2_init_nvram:                       ## @bnx2_init_nvram
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	callq	_BNX2_CHIP
	movq	_BNX2_CHIP_5709@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_2
## %bb.1:
	movq	_flash_5709@GOTPCREL(%rip), %rax
	movq	%rax, 8(%r14)
LBB0_19:
	movq	_BNX2_SHARED_HW_CFG_CONFIG2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_bnx2_shmem_rd
	movq	_BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	jne	LBB0_21
## %bb.20:
	movq	8(%r14), %rax
	movl	20(%rax), %eax
LBB0_21:
	movl	%eax, (%r14)
	xorl	%eax, %eax
	jmp	LBB0_22
LBB0_2:
	movq	_BNX2_NVM_CFG1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_BNX2_RD
	movl	%eax, %r12d
	movq	_flash_table@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	callq	_ARRAY_SIZE
	movl	%eax, %r15d
	testl	$1073741824, %r12d              ## imm = 0x40000000
	jne	LBB0_6
## %bb.3:
	testl	$8388608, %r12d                 ## imm = 0x800000
	jne	LBB0_10
## %bb.4:
	movq	_FLASH_STRAP_MASK@GOTPCREL(%rip), %rax
	testl	%r15d, %r15d
	jg	LBB0_11
	jmp	LBB0_14
LBB0_6:
	testl	%r15d, %r15d
	jle	LBB0_14
## %bb.7:
	movq	(%rbx), %rax
	movq	_FLASH_BACKUP_STRAP_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_8:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%rax), %edx
	xorl	%r12d, %edx
	testl	%ecx, %edx
	je	LBB0_15
## %bb.9:                               ##   in Loop: Header=BB0_8 Depth=1
	incl	%ebx
	addq	$24, %rax
	cmpl	%ebx, %r15d
	jne	LBB0_8
	jmp	LBB0_16
LBB0_10:
	movq	_FLASH_BACKUP_STRAP_MASK@GOTPCREL(%rip), %rax
	testl	%r15d, %r15d
	jle	LBB0_14
LBB0_11:
	movl	(%rax), %eax
	movq	(%rbx), %r13
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_12:                                ## =>This Inner Loop Header: Depth=1
	movl	4(%r13), %ecx
	xorl	%r12d, %ecx
	testl	%eax, %ecx
	je	LBB0_17
## %bb.13:                              ##   in Loop: Header=BB0_12 Depth=1
	incl	%ebx
	addq	$24, %r13
	cmpl	%ebx, %r15d
	jne	LBB0_12
	jmp	LBB0_16
LBB0_14:
	xorl	%ebx, %ebx
	cmpl	%r15d, %ebx
	je	LBB0_16
	jmp	LBB0_19
LBB0_15:
	movq	%rax, 8(%r14)
	cmpl	%r15d, %ebx
	jne	LBB0_19
	jmp	LBB0_16
LBB0_17:
	movq	%r13, 8(%r14)
	movq	%r14, %rdi
	callq	_bnx2_acquire_nvram_lock
	testl	%eax, %eax
	jne	LBB0_22
## %bb.18:
	movq	%r14, %rdi
	callq	_bnx2_enable_nvram_access
	movq	_BNX2_NVM_CFG1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r13), %edx
	movq	%r14, %rdi
	callq	_BNX2_WR
	movq	_BNX2_NVM_CFG2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	8(%r13), %edx
	movq	%r14, %rdi
	callq	_BNX2_WR
	movq	_BNX2_NVM_CFG3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	12(%r13), %edx
	movq	%r14, %rdi
	callq	_BNX2_WR
	movq	_BNX2_NVM_WRITE1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	16(%r13), %edx
	movq	%r14, %rdi
	callq	_BNX2_WR
	movq	%r14, %rdi
	callq	_bnx2_disable_nvram_access
	movq	%r14, %rdi
	callq	_bnx2_release_nvram_lock
	cmpl	%r15d, %ebx
	jne	LBB0_19
LBB0_16:
	movq	$0, 8(%r14)
	leaq	L_.str(%rip), %rdi
	callq	_pr_alert
	movq	_ENODEV@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_22:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_BNX2_CHIP_5709,8,3             ## @BNX2_CHIP_5709
	.comm	_flash_5709,24,2                ## @flash_5709
	.comm	_BNX2_NVM_CFG1,4,2              ## @BNX2_NVM_CFG1
	.comm	_flash_table,8,3                ## @flash_table
	.comm	_FLASH_BACKUP_STRAP_MASK,4,2    ## @FLASH_BACKUP_STRAP_MASK
	.comm	_FLASH_STRAP_MASK,4,2           ## @FLASH_STRAP_MASK
	.comm	_BNX2_NVM_CFG2,4,2              ## @BNX2_NVM_CFG2
	.comm	_BNX2_NVM_CFG3,4,2              ## @BNX2_NVM_CFG3
	.comm	_BNX2_NVM_WRITE1,4,2            ## @BNX2_NVM_WRITE1
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Unknown flash/EEPROM type\n"

	.comm	_ENODEV,4,2                     ## @ENODEV
	.comm	_BNX2_SHARED_HW_CFG_CONFIG2,4,2 ## @BNX2_SHARED_HW_CFG_CONFIG2
	.comm	_BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK,4,2 ## @BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK
	.no_dead_strip	_bnx2_init_nvram
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function bnx2_init_nvram
_bnx2_init_nvram:                       ; @bnx2_init_nvram
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	bl	_BNX2_CHIP
Lloh0:
	adrp	x8, _BNX2_CHIP_5709@GOTPAGE
Lloh1:
	ldr	x8, [x8, _BNX2_CHIP_5709@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	cmp	x0, x8
	b.ne	LBB0_4
; %bb.1:
Lloh3:
	adrp	x8, _flash_5709@GOTPAGE
Lloh4:
	ldr	x8, [x8, _flash_5709@GOTPAGEOFF]
	str	x8, [x19, #8]
LBB0_2:
Lloh5:
	adrp	x8, _BNX2_SHARED_HW_CFG_CONFIG2@GOTPAGE
Lloh6:
	ldr	x8, [x8, _BNX2_SHARED_HW_CFG_CONFIG2@GOTPAGEOFF]
Lloh7:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_bnx2_shmem_rd
Lloh8:
	adrp	x8, _BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK@GOTPAGE
Lloh9:
	ldr	x8, [x8, _BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	ands	w8, w8, w0
	b.eq	LBB0_13
; %bb.3:
	mov	w0, #0
	b	LBB0_14
LBB0_4:
Lloh11:
	adrp	x24, _BNX2_NVM_CFG1@GOTPAGE
Lloh12:
	ldr	x24, [x24, _BNX2_NVM_CFG1@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	x0, x19
	bl	_BNX2_RD
	mov	x21, x0
Lloh13:
	adrp	x23, _flash_table@GOTPAGE
Lloh14:
	ldr	x23, [x23, _flash_table@GOTPAGEOFF]
	ldr	x0, [x23]
	bl	_ARRAY_SIZE
	mov	x20, x0
	tbnz	w21, #30, LBB0_9
; %bb.5:
Lloh15:
	adrp	x8, _FLASH_STRAP_MASK@GOTPAGE
Lloh16:
	ldr	x8, [x8, _FLASH_STRAP_MASK@GOTPAGEOFF]
Lloh17:
	adrp	x9, _FLASH_BACKUP_STRAP_MASK@GOTPAGE
Lloh18:
	ldr	x9, [x9, _FLASH_BACKUP_STRAP_MASK@GOTPAGEOFF]
	tst	w21, #0x800000
	csel	x8, x8, x9, eq
	cmp	w20, #1
	b.lt	LBB0_15
; %bb.6:
	mov	w22, #0
	ldr	w8, [x8]
	ldr	x23, [x23]
LBB0_7:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w9, [x23, #4]
	eor	w9, w9, w21
	tst	w9, w8
	b.eq	LBB0_16
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=1
	add	w22, w22, #1
	add	x23, x23, #24
	cmp	w20, w22
	b.ne	LBB0_7
	b	LBB0_19
LBB0_9:
	cmp	w20, #1
	b.lt	LBB0_15
; %bb.10:
	mov	w22, #0
	ldr	x8, [x23]
Lloh19:
	adrp	x9, _FLASH_BACKUP_STRAP_MASK@GOTPAGE
Lloh20:
	ldr	x9, [x9, _FLASH_BACKUP_STRAP_MASK@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
LBB0_11:                                ; =>This Inner Loop Header: Depth=1
	ldr	w10, [x8]
	eor	w10, w10, w21
	tst	w10, w9
	b.eq	LBB0_18
; %bb.12:                               ;   in Loop: Header=BB0_11 Depth=1
	add	w22, w22, #1
	add	x8, x8, #24
	cmp	w20, w22
	b.ne	LBB0_11
	b	LBB0_19
LBB0_13:
	mov	w0, #0
	ldr	x8, [x19, #8]
	ldr	w8, [x8, #20]
LBB0_14:
	str	w8, [x19]
	b	LBB0_20
LBB0_15:
	mov	w22, #0
	cmp	w22, w20
	b.ne	LBB0_2
	b	LBB0_19
LBB0_16:
	str	x23, [x19, #8]
	mov	x0, x19
	bl	_bnx2_acquire_nvram_lock
	cbnz	w0, LBB0_20
; %bb.17:
	mov	x0, x19
	bl	_bnx2_enable_nvram_access
	ldr	w1, [x24]
	ldr	w2, [x23]
	mov	x0, x19
	bl	_BNX2_WR
Lloh22:
	adrp	x8, _BNX2_NVM_CFG2@GOTPAGE
Lloh23:
	ldr	x8, [x8, _BNX2_NVM_CFG2@GOTPAGEOFF]
Lloh24:
	ldr	w1, [x8]
	ldr	w2, [x23, #8]
	mov	x0, x19
	bl	_BNX2_WR
Lloh25:
	adrp	x8, _BNX2_NVM_CFG3@GOTPAGE
Lloh26:
	ldr	x8, [x8, _BNX2_NVM_CFG3@GOTPAGEOFF]
Lloh27:
	ldr	w1, [x8]
	ldr	w2, [x23, #12]
	mov	x0, x19
	bl	_BNX2_WR
Lloh28:
	adrp	x8, _BNX2_NVM_WRITE1@GOTPAGE
Lloh29:
	ldr	x8, [x8, _BNX2_NVM_WRITE1@GOTPAGEOFF]
Lloh30:
	ldr	w1, [x8]
	ldr	w2, [x23, #16]
	mov	x0, x19
	bl	_BNX2_WR
	mov	x0, x19
	bl	_bnx2_disable_nvram_access
	mov	x0, x19
	bl	_bnx2_release_nvram_lock
	cmp	w22, w20
	b.eq	LBB0_19
	b	LBB0_2
LBB0_18:
	str	x8, [x19, #8]
	cmp	w22, w20
	b.ne	LBB0_2
LBB0_19:
	str	xzr, [x19, #8]
Lloh31:
	adrp	x0, l_.str@PAGE
Lloh32:
	add	x0, x0, l_.str@PAGEOFF
	bl	_pr_alert
Lloh33:
	adrp	x8, _ENODEV@GOTPAGE
Lloh34:
	ldr	x8, [x8, _ENODEV@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_20:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpAdd	Lloh31, Lloh32
	.cfi_endproc
                                        ; -- End function
	.comm	_BNX2_CHIP_5709,8,3             ; @BNX2_CHIP_5709
	.comm	_flash_5709,24,2                ; @flash_5709
	.comm	_BNX2_NVM_CFG1,4,2              ; @BNX2_NVM_CFG1
	.comm	_flash_table,8,3                ; @flash_table
	.comm	_FLASH_BACKUP_STRAP_MASK,4,2    ; @FLASH_BACKUP_STRAP_MASK
	.comm	_FLASH_STRAP_MASK,4,2           ; @FLASH_STRAP_MASK
	.comm	_BNX2_NVM_CFG2,4,2              ; @BNX2_NVM_CFG2
	.comm	_BNX2_NVM_CFG3,4,2              ; @BNX2_NVM_CFG3
	.comm	_BNX2_NVM_WRITE1,4,2            ; @BNX2_NVM_WRITE1
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Unknown flash/EEPROM type\n"

	.comm	_ENODEV,4,2                     ; @ENODEV
	.comm	_BNX2_SHARED_HW_CFG_CONFIG2,4,2 ; @BNX2_SHARED_HW_CFG_CONFIG2
	.comm	_BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK,4,2 ; @BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK
	.no_dead_strip	_bnx2_init_nvram
.subsections_via_symbols
