	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_tegra_emc_complete_timing_change ## -- Begin function tegra_emc_complete_timing_change
	.p2align	4, 0x90
_tegra_emc_complete_timing_change:      ## @tegra_emc_complete_timing_change
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	callq	_tegra_emc_find_timing
	testq	%rax, %rax
	je	LBB0_13
## %bb.1:
	movq	%rax, %r14
	movq	%rbx, %rdi
	callq	_emc_seq_wait_clkchange
	movq	(%r14), %rax
	cmpq	8(%rbx), %rax
	je	LBB0_3
## %bb.2:
	movl	8(%r14), %edi
	movq	_EMC_AUTO_CAL_INTERVAL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%rbx), %rsi
	callq	_writel
LBB0_3:
	movl	12(%r14), %edi
	movq	_EMC_CFG_PWR_MASK@GOTPCREL(%rip), %rax
	testl	%edi, (%rax)
	je	LBB0_5
## %bb.4:
	movq	_EMC_CFG@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%rbx), %rsi
	callq	_writel
LBB0_5:
	leaq	8(%rbx), %r15
	movl	16(%r14), %edi
	movq	_EMC_ZCAL_WAIT_CNT@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%rbx), %rsi
	callq	_writel
	movq	(%rbx), %rax
	movq	_DRAM_TYPE_LPDDR3@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_8
## %bb.6:
	movl	20(%r14), %edi
	movq	_EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX@GOTPCREL(%rip), %rcx
	testl	%edi, (%rcx)
	je	LBB0_8
## %bb.7:
	movq	_EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	_EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	_EMC_BGBIAS_CTL0@GOTPCREL(%rip), %rax
	jmp	LBB0_12
LBB0_8:
	movq	_DRAM_TYPE_DDR3@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_11
## %bb.9:
	movq	_EMC_BGBIAS_CTL0@GOTPCREL(%rip), %r12
	movq	(%r12), %rdi
	addq	40(%rbx), %rdi
	callq	_readl
	movl	20(%r14), %edi
	cmpl	%edi, %eax
	je	LBB0_11
## %bb.10:
	movq	(%r12), %rsi
	addq	40(%rbx), %rsi
	callq	_writel
LBB0_11:
	movl	8(%r14), %edi
	movq	_EMC_AUTO_CAL_INTERVAL@GOTPCREL(%rip), %rax
LBB0_12:
	movq	(%rax), %rsi
	addq	40(%rbx), %rsi
	callq	_writel
	movl	$2, %edi
	callq	_udelay
	movl	24(%r14), %edi
	movq	_EMC_SEL_DPD_CTRL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%rbx), %rsi
	callq	_writel
	movq	%rbx, %rdi
	callq	_emc_seq_update_timing
	movups	(%r14), %xmm0
	movups	16(%r14), %xmm1
	movups	%xmm0, (%r15)
	movups	%xmm1, 16(%r15)
LBB0_13:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_EMC_AUTO_CAL_INTERVAL,8,3      ## @EMC_AUTO_CAL_INTERVAL
	.comm	_EMC_CFG_PWR_MASK,4,2           ## @EMC_CFG_PWR_MASK
	.comm	_EMC_CFG,8,3                    ## @EMC_CFG
	.comm	_EMC_ZCAL_WAIT_CNT,8,3          ## @EMC_ZCAL_WAIT_CNT
	.comm	_DRAM_TYPE_LPDDR3,8,3           ## @DRAM_TYPE_LPDDR3
	.comm	_EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX,4,2 ## @EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX
	.comm	_EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN,4,2 ## @EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN
	.comm	_EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD,4,2 ## @EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD
	.comm	_EMC_BGBIAS_CTL0,8,3            ## @EMC_BGBIAS_CTL0
	.comm	_DRAM_TYPE_DDR3,8,3             ## @DRAM_TYPE_DDR3
	.comm	_EMC_SEL_DPD_CTRL,8,3           ## @EMC_SEL_DPD_CTRL
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_tegra_emc_complete_timing_change ; -- Begin function tegra_emc_complete_timing_change
	.p2align	2
_tegra_emc_complete_timing_change:      ; @tegra_emc_complete_timing_change
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	bl	_tegra_emc_find_timing
	cbz	x0, LBB0_13
; %bb.1:
	mov	x20, x0
	mov	x0, x19
	bl	_emc_seq_wait_clkchange
	ldr	x8, [x20]
	ldr	x9, [x19, #8]
	cmp	x8, x9
	b.eq	LBB0_3
; %bb.2:
	ldr	w0, [x20, #8]
	ldr	x8, [x19, #40]
Lloh0:
	adrp	x9, _EMC_AUTO_CAL_INTERVAL@GOTPAGE
Lloh1:
	ldr	x9, [x9, _EMC_AUTO_CAL_INTERVAL@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
LBB0_3:
	ldr	w0, [x20, #12]
Lloh3:
	adrp	x8, _EMC_CFG_PWR_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _EMC_CFG_PWR_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_5
; %bb.4:
	ldr	x8, [x19, #40]
Lloh6:
	adrp	x9, _EMC_CFG@GOTPAGE
Lloh7:
	ldr	x9, [x9, _EMC_CFG@GOTPAGEOFF]
Lloh8:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
LBB0_5:
	add	x21, x19, #8
	ldr	w0, [x20, #16]
	ldr	x8, [x19, #40]
Lloh9:
	adrp	x9, _EMC_ZCAL_WAIT_CNT@GOTPAGE
Lloh10:
	ldr	x9, [x9, _EMC_ZCAL_WAIT_CNT@GOTPAGEOFF]
Lloh11:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
	ldr	x8, [x19]
Lloh12:
	adrp	x9, _DRAM_TYPE_LPDDR3@GOTPAGE
Lloh13:
	ldr	x9, [x9, _DRAM_TYPE_LPDDR3@GOTPAGEOFF]
Lloh14:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_8
; %bb.6:
	ldr	w9, [x20, #20]
Lloh15:
	adrp	x10, _EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX@GOTPAGE
Lloh16:
	ldr	x10, [x10, _EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX@GOTPAGEOFF]
Lloh17:
	ldr	w10, [x10]
	tst	w10, w9
	b.eq	LBB0_8
; %bb.7:
Lloh18:
	adrp	x8, _EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN@GOTPAGE
Lloh19:
	ldr	x8, [x8, _EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	orr	w8, w8, w9
Lloh21:
	adrp	x9, _EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD@GOTPAGE
Lloh22:
	ldr	x9, [x9, _EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	orr	w0, w8, w9
Lloh24:
	adrp	x8, _EMC_BGBIAS_CTL0@GOTPAGE
Lloh25:
	ldr	x8, [x8, _EMC_BGBIAS_CTL0@GOTPAGEOFF]
	b	LBB0_12
LBB0_8:
Lloh26:
	adrp	x9, _DRAM_TYPE_DDR3@GOTPAGE
Lloh27:
	ldr	x9, [x9, _DRAM_TYPE_DDR3@GOTPAGEOFF]
Lloh28:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_11
; %bb.9:
	ldr	x8, [x19, #40]
Lloh29:
	adrp	x22, _EMC_BGBIAS_CTL0@GOTPAGE
Lloh30:
	ldr	x22, [x22, _EMC_BGBIAS_CTL0@GOTPAGEOFF]
	ldr	x9, [x22]
	add	x0, x9, x8
	bl	_readl
	mov	x8, x0
	ldr	w0, [x20, #20]
	cmp	w8, w0
	b.eq	LBB0_11
; %bb.10:
	ldr	x8, [x19, #40]
	ldr	x9, [x22]
	add	x1, x9, x8
	bl	_writel
LBB0_11:
	ldr	w0, [x20, #8]
Lloh31:
	adrp	x8, _EMC_AUTO_CAL_INTERVAL@GOTPAGE
Lloh32:
	ldr	x8, [x8, _EMC_AUTO_CAL_INTERVAL@GOTPAGEOFF]
LBB0_12:
	ldr	x9, [x19, #40]
	ldr	x8, [x8]
	add	x1, x8, x9
	bl	_writel
	mov	w0, #2
	bl	_udelay
	ldr	w0, [x20, #24]
	ldr	x8, [x19, #40]
Lloh33:
	adrp	x9, _EMC_SEL_DPD_CTRL@GOTPAGE
Lloh34:
	ldr	x9, [x9, _EMC_SEL_DPD_CTRL@GOTPAGEOFF]
Lloh35:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
	mov	x0, x19
	bl	_emc_seq_update_timing
	ldp	q1, q0, [x20]
	stp	q1, q0, [x21]
LBB0_13:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.cfi_endproc
                                        ; -- End function
	.comm	_EMC_AUTO_CAL_INTERVAL,8,3      ; @EMC_AUTO_CAL_INTERVAL
	.comm	_EMC_CFG_PWR_MASK,4,2           ; @EMC_CFG_PWR_MASK
	.comm	_EMC_CFG,8,3                    ; @EMC_CFG
	.comm	_EMC_ZCAL_WAIT_CNT,8,3          ; @EMC_ZCAL_WAIT_CNT
	.comm	_DRAM_TYPE_LPDDR3,8,3           ; @DRAM_TYPE_LPDDR3
	.comm	_EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX,4,2 ; @EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX
	.comm	_EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN,4,2 ; @EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN
	.comm	_EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD,4,2 ; @EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD
	.comm	_EMC_BGBIAS_CTL0,8,3            ; @EMC_BGBIAS_CTL0
	.comm	_DRAM_TYPE_DDR3,8,3             ; @DRAM_TYPE_DDR3
	.comm	_EMC_SEL_DPD_CTRL,8,3           ; @EMC_SEL_DPD_CTRL
.subsections_via_symbols
