	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function amd8111e_probe_one
_amd8111e_probe_one:                    ## @amd8111e_probe_one
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	callq	_pci_enable_device
	testl	%eax, %eax
	je	LBB0_2
## %bb.1:
	movl	%eax, %ebx
	leaq	L_.str(%rip), %rsi
	movq	%r12, %rdi
	callq	_dev_err
	jmp	LBB0_33
LBB0_2:
	xorl	%ebx, %ebx
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	_pci_resource_flags
	movq	_IORESOURCE_MEM@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_3
## %bb.4:
	movq	_MODULE_NAME@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_pci_request_regions
	testl	%eax, %eax
	je	LBB0_6
## %bb.5:
	movl	%eax, %ebx
	leaq	L_.str.2(%rip), %rsi
	movq	%r12, %rdi
	callq	_dev_err
	jmp	LBB0_32
LBB0_3:
	leaq	L_.str.1(%rip), %rsi
	movq	%r12, %rdi
	callq	_dev_err
	movq	_ENODEV@GOTPCREL(%rip), %rax
	subl	(%rax), %ebx
	jmp	LBB0_32
LBB0_6:
	movq	%r12, %rdi
	callq	_pci_set_master
	cmpq	$0, 8(%r12)
	je	LBB0_7
## %bb.9:
	movl	$32, %edi
	callq	_DMA_BIT_MASK
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_pci_set_dma_mask
	testq	%rax, %rax
	js	LBB0_10
## %bb.11:
	xorl	%ebx, %ebx
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	_pci_resource_start
	movq	%rax, %r15
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	_pci_resource_len
	movq	%rax, %r13
	movl	$104, %edi
	callq	_alloc_etherdev
	testq	%rax, %rax
	je	LBB0_12
## %bb.13:
	movq	%rax, %r14
	movq	%rax, %rdi
	movq	%r12, %rsi
	callq	_SET_NETDEV_DEV
	movq	%r14, %rdi
	callq	_netdev_priv
	movq	%r15, %rbx
	movq	%rax, %r15
	movq	%r12, 96(%rax)
	movq	%r14, 88(%rax)
	movq	8(%r12), %rax
	movq	%rax, 80(%r15)
	leaq	72(%r15), %rdi
	callq	_spin_lock_init
	movq	%r12, %rdi
	movq	%rbx, %rsi
	movq	%r13, %rdx
	callq	_devm_ioremap
	movq	%rax, 16(%r15)
	testq	%rax, %rax
	je	LBB0_29
## %bb.14:
	movq	_ETH_ALEN@GOTPCREL(%rip), %rbx
	cmpl	$0, (%rbx)
	jle	LBB0_18
## %bb.15:
	movq	_PADR@GOTPCREL(%rip), %rcx
	addq	(%rcx), %rax
	movq	%rax, %rdi
	callq	_readb
	movq	8(%r14), %rcx
	movl	%eax, (%rcx)
	cmpl	$2, (%rbx)
	jl	LBB0_18
## %bb.16:
	movl	$1, %r13d
LBB0_17:                                ## =>This Inner Loop Header: Depth=1
	movq	16(%r15), %rdi
	movq	_PADR@GOTPCREL(%rip), %rax
	addq	(%rax), %rdi
	addq	%r13, %rdi
	callq	_readb
	movq	8(%r14), %rcx
	movl	%eax, (%rcx,%r13,4)
	incq	%r13
	movslq	(%rbx), %rax
	cmpq	%rax, %r13
	jl	LBB0_17
LBB0_18:
	movq	_speed_duplex@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	_card_idx@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rax
	movl	(%rdx,%rax,4), %edx
	movl	%edx, 68(%r15)
	movq	_coalesce@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdx
	cmpq	$0, (%rdx,%rax,8)
	je	LBB0_20
## %bb.19:
	movq	_OPTION_INTR_COAL_ENABLE@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	%edx, (%r15)
LBB0_20:
	movq	_dynamic_ipg@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdx
	leaq	1(%rax), %rsi
	movq	%rsi, (%rcx)
	cmpq	$0, (%rdx,%rax,8)
	je	LBB0_22
## %bb.21:
	movq	_OPTION_DYN_IPG_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r15)
LBB0_22:
	movq	_amd8111e_netdev_ops@GOTPCREL(%rip), %rax
	movq	%rax, 40(%r14)
	movq	_ops@GOTPCREL(%rip), %rax
	movq	%rax, 32(%r14)
	movl	4(%r12), %eax
	movl	%eax, 28(%r14)
	movq	_AMD8111E_TX_TIMEOUT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 24(%r14)
	movq	_AMD8111E_MIN_MTU@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 20(%r14)
	movq	_AMD8111E_MAX_MTU@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 16(%r14)
	leaq	64(%r15), %rsi
	movq	_amd8111e_rx_poll@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	movl	$32, %ecx
	callq	_netif_napi_add
	movq	%r14, %rdi
	callq	_amd8111e_probe_ext_phy
	movq	%r14, 56(%r15)
	movq	_amd8111e_mdio_read@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 48(%r15)
	movq	_amd8111e_mdio_write@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 44(%r15)
	movl	8(%r15), %eax
	movl	%eax, 40(%r15)
	movq	%r14, %rdi
	callq	_amd8111e_set_rx_buff_len
	movq	%r14, %rdi
	callq	_register_netdev
	testl	%eax, %eax
	je	LBB0_24
## %bb.23:
	movl	%eax, %ebx
	leaq	L_.str.6(%rip), %rsi
	movq	%r12, %rdi
	callq	_dev_err
	jmp	LBB0_30
LBB0_7:
	leaq	L_.str.3(%rip), %rsi
	jmp	LBB0_8
LBB0_10:
	leaq	L_.str.4(%rip), %rsi
LBB0_8:
	movq	%r12, %rdi
	callq	_dev_err
	movq	_ENODEV@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
	jmp	LBB0_31
LBB0_12:
	movq	_ENOMEM@GOTPCREL(%rip), %rax
	subl	(%rax), %ebx
	jmp	LBB0_31
LBB0_29:
	leaq	L_.str.5(%rip), %rsi
	movq	%r12, %rdi
	callq	_dev_err
	movq	_ENOMEM@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
LBB0_30:
	movq	%r14, %rdi
	callq	_free_netdev
LBB0_31:
	movq	%r12, %rdi
	callq	_pci_release_regions
LBB0_32:
	movq	%r12, %rdi
	callq	_pci_disable_device
LBB0_33:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_24:
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	_pci_set_drvdata
	movq	_OPTION_DYN_IPG_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r15)
	je	LBB0_26
## %bb.25:
	movq	%r15, %rdi
	addq	$32, %rdi
	movq	_amd8111e_config_ipg@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_timer_setup
	movq	_jiffies@GOTPCREL(%rip), %rax
	movq	_IPG_CONVERGE_JIFFIES@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	addq	(%rax), %rcx
	movq	%rcx, 32(%r15)
	movq	_DEFAULT_IPG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 28(%r15)
	movq	_CSTATE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 24(%r15)
LBB0_26:
	movq	_CHIPID@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	16(%r15), %rdi
	callq	_readl
	shrl	$28, %eax
	movq	_chip_version@GOTPCREL(%rip), %r13
	movl	%eax, (%r13)
	movq	_MODULE_VERS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	leaq	L_.str.7(%rip), %rsi
	xorl	%ebx, %ebx
	movq	%r12, %rdi
	xorl	%eax, %eax
	callq	_dev_info
	movl	(%r13), %edx
	movq	8(%r14), %rcx
	leaq	L_.str.8(%rip), %rsi
	movq	%r12, %rdi
	xorl	%eax, %eax
	callq	_dev_info
	movl	4(%r15), %edx
	testl	%edx, %edx
	je	LBB0_28
## %bb.27:
	movl	8(%r15), %ecx
	leaq	L_.str.9(%rip), %rsi
	movq	%r12, %rdi
	xorl	%eax, %eax
	callq	_dev_info
	jmp	LBB0_33
LBB0_28:
	leaq	L_.str.10(%rip), %rsi
	xorl	%ebx, %ebx
	movq	%r12, %rdi
	xorl	%eax, %eax
	callq	_dev_info
	jmp	LBB0_33
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Cannot enable new PCI device\n"

	.comm	_IORESOURCE_MEM,4,2             ## @IORESOURCE_MEM
L_.str.1:                               ## @.str.1
	.asciz	"Cannot find PCI base address\n"

	.comm	_ENODEV,4,2                     ## @ENODEV
	.comm	_MODULE_NAME,4,2                ## @MODULE_NAME
L_.str.2:                               ## @.str.2
	.asciz	"Cannot obtain PCI resources\n"

L_.str.3:                               ## @.str.3
	.asciz	"No Power Management capability\n"

L_.str.4:                               ## @.str.4
	.asciz	"DMA not supported\n"

	.comm	_ENOMEM,4,2                     ## @ENOMEM
L_.str.5:                               ## @.str.5
	.asciz	"Cannot map device registers\n"

	.comm	_ETH_ALEN,4,2                   ## @ETH_ALEN
	.comm	_PADR,8,3                       ## @PADR
	.comm	_speed_duplex,8,3               ## @speed_duplex
	.comm	_card_idx,8,3                   ## @card_idx
	.comm	_coalesce,8,3                   ## @coalesce
	.comm	_OPTION_INTR_COAL_ENABLE,4,2    ## @OPTION_INTR_COAL_ENABLE
	.comm	_dynamic_ipg,8,3                ## @dynamic_ipg
	.comm	_OPTION_DYN_IPG_ENABLE,4,2      ## @OPTION_DYN_IPG_ENABLE
	.comm	_amd8111e_netdev_ops,4,2        ## @amd8111e_netdev_ops
	.comm	_ops,4,2                        ## @ops
	.comm	_AMD8111E_TX_TIMEOUT,4,2        ## @AMD8111E_TX_TIMEOUT
	.comm	_AMD8111E_MIN_MTU,4,2           ## @AMD8111E_MIN_MTU
	.comm	_AMD8111E_MAX_MTU,4,2           ## @AMD8111E_MAX_MTU
	.comm	_amd8111e_rx_poll,4,2           ## @amd8111e_rx_poll
	.comm	_amd8111e_mdio_read,4,2         ## @amd8111e_mdio_read
	.comm	_amd8111e_mdio_write,4,2        ## @amd8111e_mdio_write
L_.str.6:                               ## @.str.6
	.asciz	"Cannot register net device\n"

	.comm	_amd8111e_config_ipg,4,2        ## @amd8111e_config_ipg
	.comm	_jiffies,8,3                    ## @jiffies
	.comm	_IPG_CONVERGE_JIFFIES,8,3       ## @IPG_CONVERGE_JIFFIES
	.comm	_DEFAULT_IPG,4,2                ## @DEFAULT_IPG
	.comm	_CSTATE,4,2                     ## @CSTATE
	.comm	_CHIPID,8,3                     ## @CHIPID
	.comm	_chip_version,4,2               ## @chip_version
L_.str.7:                               ## @.str.7
	.asciz	"AMD-8111e Driver Version: %s\n"

	.comm	_MODULE_VERS,4,2                ## @MODULE_VERS
L_.str.8:                               ## @.str.8
	.asciz	"[ Rev %x ] PCI 10/100BaseT Ethernet %pM\n"

L_.str.9:                               ## @.str.9
	.asciz	"Found MII PHY ID 0x%08x at address 0x%02x\n"

L_.str.10:                              ## @.str.10
	.asciz	"Couldn't detect MII PHY, assuming address 0x01\n"

	.comm	_NETIF_F_HW_VLAN_CTAG_RX,4,2    ## @NETIF_F_HW_VLAN_CTAG_RX
	.comm	_NETIF_F_HW_VLAN_CTAG_TX,4,2    ## @NETIF_F_HW_VLAN_CTAG_TX
	.no_dead_strip	_amd8111e_probe_one
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function amd8111e_probe_one
_amd8111e_probe_one:                    ; @amd8111e_probe_one
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	bl	_pci_enable_device
	cbz	w0, LBB0_2
; %bb.1:
	mov	x22, x0
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x19
	bl	_dev_err
	b	LBB0_26
LBB0_2:
	mov	x0, x19
	mov	w1, #0
	bl	_pci_resource_flags
Lloh2:
	adrp	x8, _IORESOURCE_MEM@GOTPAGE
Lloh3:
	ldr	x8, [x8, _IORESOURCE_MEM@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_5
; %bb.3:
Lloh5:
	adrp	x8, _MODULE_NAME@GOTPAGE
Lloh6:
	ldr	x8, [x8, _MODULE_NAME@GOTPAGEOFF]
Lloh7:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_pci_request_regions
	cbz	w0, LBB0_6
; %bb.4:
	mov	x22, x0
Lloh8:
	adrp	x1, l_.str.2@PAGE
Lloh9:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x0, x19
	bl	_dev_err
	b	LBB0_25
LBB0_5:
Lloh10:
	adrp	x1, l_.str.1@PAGE
Lloh11:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x19
	bl	_dev_err
Lloh12:
	adrp	x8, _ENODEV@GOTPAGE
Lloh13:
	ldr	x8, [x8, _ENODEV@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	neg	w22, w8
	b	LBB0_25
LBB0_6:
	mov	x0, x19
	bl	_pci_set_master
	ldr	x8, [x19, #8]
	cbz	x8, LBB0_20
; %bb.7:
	mov	w0, #32
	bl	_DMA_BIT_MASK
	mov	x1, x0
	mov	x0, x19
	bl	_pci_set_dma_mask
	tbnz	x0, #63, LBB0_21
; %bb.8:
	mov	x0, x19
	mov	w1, #0
	bl	_pci_resource_start
	mov	x22, x0
	mov	x0, x19
	mov	w1, #0
	bl	_pci_resource_len
	mov	x23, x0
	mov	w0, #104
	bl	_alloc_etherdev
	cbz	x0, LBB0_27
; %bb.9:
	mov	x20, x0
	mov	x1, x19
	bl	_SET_NETDEV_DEV
	mov	x0, x20
	bl	_netdev_priv
	mov	x21, x0
	str	x19, [x0, #96]
	ldr	x8, [x19, #8]
	stp	x8, x20, [x0, #80]
	add	x0, x0, #72
	bl	_spin_lock_init
	mov	x0, x19
	mov	x1, x22
	mov	x2, x23
	bl	_devm_ioremap
	str	x0, [x21, #16]
	cbz	x0, LBB0_28
; %bb.10:
Lloh15:
	adrp	x22, _ETH_ALEN@GOTPAGE
Lloh16:
	ldr	x22, [x22, _ETH_ALEN@GOTPAGEOFF]
	ldr	w8, [x22]
	cmp	w8, #1
	b.lt	LBB0_14
; %bb.11:
Lloh17:
	adrp	x23, _PADR@GOTPAGE
Lloh18:
	ldr	x23, [x23, _PADR@GOTPAGEOFF]
	ldr	x8, [x23]
	add	x0, x0, x8
	bl	_readb
	ldr	x8, [x20, #8]
	str	w0, [x8]
	ldr	w8, [x22]
	cmp	w8, #2
	b.lt	LBB0_14
; %bb.12:
	mov	w24, #1
LBB0_13:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x21, #16]
	ldr	x9, [x23]
	add	x8, x8, x9
	add	x0, x24, x8
	bl	_readb
	ldr	x8, [x20, #8]
	str	w0, [x8, x24, lsl #2]
	add	x24, x24, #1
	ldrsw	x8, [x22]
	cmp	x24, x8
	b.lt	LBB0_13
LBB0_14:
Lloh19:
	adrp	x8, _speed_duplex@GOTPAGE
Lloh20:
	ldr	x8, [x8, _speed_duplex@GOTPAGEOFF]
Lloh21:
	ldr	x10, [x8]
Lloh22:
	adrp	x9, _card_idx@GOTPAGE
Lloh23:
	ldr	x9, [x9, _card_idx@GOTPAGEOFF]
	ldr	x8, [x9]
	ldr	w10, [x10, x8, lsl #2]
	str	w10, [x21, #68]
Lloh24:
	adrp	x10, _coalesce@GOTPAGE
Lloh25:
	ldr	x10, [x10, _coalesce@GOTPAGEOFF]
Lloh26:
	ldr	x10, [x10]
	ldr	x10, [x10, x8, lsl #3]
	cbz	x10, LBB0_16
; %bb.15:
Lloh27:
	adrp	x10, _OPTION_INTR_COAL_ENABLE@GOTPAGE
Lloh28:
	ldr	x10, [x10, _OPTION_INTR_COAL_ENABLE@GOTPAGEOFF]
Lloh29:
	ldr	w10, [x10]
	ldr	w11, [x21]
	orr	w10, w11, w10
	str	w10, [x21]
LBB0_16:
Lloh30:
	adrp	x10, _dynamic_ipg@GOTPAGE
Lloh31:
	ldr	x10, [x10, _dynamic_ipg@GOTPAGEOFF]
Lloh32:
	ldr	x10, [x10]
	add	x11, x8, #1
	str	x11, [x9]
	ldr	x8, [x10, x8, lsl #3]
Lloh33:
	adrp	x23, _OPTION_DYN_IPG_ENABLE@GOTPAGE
Lloh34:
	ldr	x23, [x23, _OPTION_DYN_IPG_ENABLE@GOTPAGEOFF]
	cbz	x8, LBB0_18
; %bb.17:
	ldr	w8, [x23]
	ldr	w9, [x21]
	orr	w8, w9, w8
	str	w8, [x21]
LBB0_18:
Lloh35:
	adrp	x8, _amd8111e_netdev_ops@GOTPAGE
Lloh36:
	ldr	x8, [x8, _amd8111e_netdev_ops@GOTPAGEOFF]
Lloh37:
	adrp	x9, _ops@GOTPAGE
Lloh38:
	ldr	x9, [x9, _ops@GOTPAGEOFF]
	stp	x9, x8, [x20, #32]
	ldr	w8, [x19, #4]
Lloh39:
	adrp	x9, _AMD8111E_TX_TIMEOUT@GOTPAGE
Lloh40:
	ldr	x9, [x9, _AMD8111E_TX_TIMEOUT@GOTPAGEOFF]
Lloh41:
	ldr	w9, [x9]
	stp	w9, w8, [x20, #24]
Lloh42:
	adrp	x8, _AMD8111E_MIN_MTU@GOTPAGE
Lloh43:
	ldr	x8, [x8, _AMD8111E_MIN_MTU@GOTPAGEOFF]
Lloh44:
	ldr	w8, [x8]
Lloh45:
	adrp	x9, _AMD8111E_MAX_MTU@GOTPAGE
Lloh46:
	ldr	x9, [x9, _AMD8111E_MAX_MTU@GOTPAGEOFF]
Lloh47:
	ldr	w9, [x9]
	stp	w9, w8, [x20, #16]
	add	x1, x21, #64
Lloh48:
	adrp	x8, _amd8111e_rx_poll@GOTPAGE
Lloh49:
	ldr	x8, [x8, _amd8111e_rx_poll@GOTPAGEOFF]
Lloh50:
	ldr	w2, [x8]
	mov	x0, x20
	mov	w3, #32
	bl	_netif_napi_add
	mov	x0, x20
	bl	_amd8111e_probe_ext_phy
	str	x20, [x21, #56]
Lloh51:
	adrp	x8, _amd8111e_mdio_read@GOTPAGE
Lloh52:
	ldr	x8, [x8, _amd8111e_mdio_read@GOTPAGEOFF]
Lloh53:
	ldr	w8, [x8]
	str	w8, [x21, #48]
Lloh54:
	adrp	x8, _amd8111e_mdio_write@GOTPAGE
Lloh55:
	ldr	x8, [x8, _amd8111e_mdio_write@GOTPAGEOFF]
Lloh56:
	ldr	w8, [x8]
	ldr	w9, [x21, #8]
	stp	w9, w8, [x21, #40]
	mov	x0, x20
	bl	_amd8111e_set_rx_buff_len
	mov	x0, x20
	bl	_register_netdev
	cbz	w0, LBB0_30
; %bb.19:
	mov	x22, x0
Lloh57:
	adrp	x1, l_.str.6@PAGE
Lloh58:
	add	x1, x1, l_.str.6@PAGEOFF
	mov	x0, x19
	bl	_dev_err
	b	LBB0_29
LBB0_20:
Lloh59:
	adrp	x1, l_.str.3@PAGE
Lloh60:
	add	x1, x1, l_.str.3@PAGEOFF
	b	LBB0_22
LBB0_21:
Lloh61:
	adrp	x1, l_.str.4@PAGE
Lloh62:
	add	x1, x1, l_.str.4@PAGEOFF
LBB0_22:
	mov	x0, x19
	bl	_dev_err
Lloh63:
	adrp	x8, _ENODEV@GOTPAGE
Lloh64:
	ldr	x8, [x8, _ENODEV@GOTPAGEOFF]
LBB0_23:
	ldr	w8, [x8]
	neg	w22, w8
LBB0_24:
	mov	x0, x19
	bl	_pci_release_regions
LBB0_25:
	mov	x0, x19
	bl	_pci_disable_device
LBB0_26:
	mov	x0, x22
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
LBB0_27:
Lloh65:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh66:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
	b	LBB0_23
LBB0_28:
Lloh67:
	adrp	x1, l_.str.5@PAGE
Lloh68:
	add	x1, x1, l_.str.5@PAGEOFF
	mov	x0, x19
	bl	_dev_err
Lloh69:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh70:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
Lloh71:
	ldr	w8, [x8]
	neg	w22, w8
LBB0_29:
	mov	x0, x20
	bl	_free_netdev
	b	LBB0_24
LBB0_30:
	mov	x0, x19
	mov	x1, x20
	bl	_pci_set_drvdata
	ldr	w8, [x21]
	ldr	w9, [x23]
	tst	w9, w8
	b.eq	LBB0_32
; %bb.31:
	add	x0, x21, #32
Lloh72:
	adrp	x8, _amd8111e_config_ipg@GOTPAGE
Lloh73:
	ldr	x8, [x8, _amd8111e_config_ipg@GOTPAGEOFF]
Lloh74:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_timer_setup
Lloh75:
	adrp	x8, _jiffies@GOTPAGE
Lloh76:
	ldr	x8, [x8, _jiffies@GOTPAGEOFF]
Lloh77:
	adrp	x9, _IPG_CONVERGE_JIFFIES@GOTPAGE
Lloh78:
	ldr	x9, [x9, _IPG_CONVERGE_JIFFIES@GOTPAGEOFF]
Lloh79:
	ldr	x8, [x8]
Lloh80:
	ldr	x9, [x9]
	add	x8, x9, x8
	str	x8, [x21, #32]
Lloh81:
	adrp	x8, _DEFAULT_IPG@GOTPAGE
Lloh82:
	ldr	x8, [x8, _DEFAULT_IPG@GOTPAGEOFF]
Lloh83:
	ldr	w8, [x8]
Lloh84:
	adrp	x9, _CSTATE@GOTPAGE
Lloh85:
	ldr	x9, [x9, _CSTATE@GOTPAGEOFF]
Lloh86:
	ldr	w9, [x9]
	stp	w9, w8, [x21, #24]
LBB0_32:
	ldr	x8, [x21, #16]
Lloh87:
	adrp	x9, _CHIPID@GOTPAGE
Lloh88:
	ldr	x9, [x9, _CHIPID@GOTPAGEOFF]
Lloh89:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_readl
	lsr	w8, w0, #28
Lloh90:
	adrp	x22, _chip_version@GOTPAGE
Lloh91:
	ldr	x22, [x22, _chip_version@GOTPAGEOFF]
	str	w8, [x22]
Lloh92:
	adrp	x8, _MODULE_VERS@GOTPAGE
Lloh93:
	ldr	x8, [x8, _MODULE_VERS@GOTPAGEOFF]
Lloh94:
	ldr	w8, [x8]
	str	x8, [sp]
Lloh95:
	adrp	x1, l_.str.7@PAGE
Lloh96:
	add	x1, x1, l_.str.7@PAGEOFF
	mov	x0, x19
	bl	_dev_info
	ldr	x8, [x20, #8]
	ldr	w9, [x22]
	stp	x9, x8, [sp]
Lloh97:
	adrp	x1, l_.str.8@PAGE
Lloh98:
	add	x1, x1, l_.str.8@PAGEOFF
	mov	x0, x19
	bl	_dev_info
	ldr	w8, [x21, #4]
	cbz	w8, LBB0_34
; %bb.33:
	ldr	w9, [x21, #8]
	stp	x8, x9, [sp]
Lloh99:
	adrp	x1, l_.str.9@PAGE
Lloh100:
	add	x1, x1, l_.str.9@PAGEOFF
	b	LBB0_35
LBB0_34:
Lloh101:
	adrp	x1, l_.str.10@PAGE
Lloh102:
	add	x1, x1, l_.str.10@PAGEOFF
LBB0_35:
	mov	x0, x19
	bl	_dev_info
	mov	w22, #0
	b	LBB0_26
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpAdd	Lloh57, Lloh58
	.loh AdrpAdd	Lloh59, Lloh60
	.loh AdrpAdd	Lloh61, Lloh62
	.loh AdrpLdrGot	Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpAdd	Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh79
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpAdd	Lloh97, Lloh98
	.loh AdrpAdd	Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGot	Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpAdd	Lloh99, Lloh100
	.loh AdrpAdd	Lloh101, Lloh102
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Cannot enable new PCI device\n"

	.comm	_IORESOURCE_MEM,4,2             ; @IORESOURCE_MEM
l_.str.1:                               ; @.str.1
	.asciz	"Cannot find PCI base address\n"

	.comm	_ENODEV,4,2                     ; @ENODEV
	.comm	_MODULE_NAME,4,2                ; @MODULE_NAME
l_.str.2:                               ; @.str.2
	.asciz	"Cannot obtain PCI resources\n"

l_.str.3:                               ; @.str.3
	.asciz	"No Power Management capability\n"

l_.str.4:                               ; @.str.4
	.asciz	"DMA not supported\n"

	.comm	_ENOMEM,4,2                     ; @ENOMEM
l_.str.5:                               ; @.str.5
	.asciz	"Cannot map device registers\n"

	.comm	_ETH_ALEN,4,2                   ; @ETH_ALEN
	.comm	_PADR,8,3                       ; @PADR
	.comm	_speed_duplex,8,3               ; @speed_duplex
	.comm	_card_idx,8,3                   ; @card_idx
	.comm	_coalesce,8,3                   ; @coalesce
	.comm	_OPTION_INTR_COAL_ENABLE,4,2    ; @OPTION_INTR_COAL_ENABLE
	.comm	_dynamic_ipg,8,3                ; @dynamic_ipg
	.comm	_OPTION_DYN_IPG_ENABLE,4,2      ; @OPTION_DYN_IPG_ENABLE
	.comm	_amd8111e_netdev_ops,4,2        ; @amd8111e_netdev_ops
	.comm	_ops,4,2                        ; @ops
	.comm	_AMD8111E_TX_TIMEOUT,4,2        ; @AMD8111E_TX_TIMEOUT
	.comm	_AMD8111E_MIN_MTU,4,2           ; @AMD8111E_MIN_MTU
	.comm	_AMD8111E_MAX_MTU,4,2           ; @AMD8111E_MAX_MTU
	.comm	_amd8111e_rx_poll,4,2           ; @amd8111e_rx_poll
	.comm	_amd8111e_mdio_read,4,2         ; @amd8111e_mdio_read
	.comm	_amd8111e_mdio_write,4,2        ; @amd8111e_mdio_write
l_.str.6:                               ; @.str.6
	.asciz	"Cannot register net device\n"

	.comm	_amd8111e_config_ipg,4,2        ; @amd8111e_config_ipg
	.comm	_jiffies,8,3                    ; @jiffies
	.comm	_IPG_CONVERGE_JIFFIES,8,3       ; @IPG_CONVERGE_JIFFIES
	.comm	_DEFAULT_IPG,4,2                ; @DEFAULT_IPG
	.comm	_CSTATE,4,2                     ; @CSTATE
	.comm	_CHIPID,8,3                     ; @CHIPID
	.comm	_chip_version,4,2               ; @chip_version
l_.str.7:                               ; @.str.7
	.asciz	"AMD-8111e Driver Version: %s\n"

	.comm	_MODULE_VERS,4,2                ; @MODULE_VERS
l_.str.8:                               ; @.str.8
	.asciz	"[ Rev %x ] PCI 10/100BaseT Ethernet %pM\n"

l_.str.9:                               ; @.str.9
	.asciz	"Found MII PHY ID 0x%08x at address 0x%02x\n"

l_.str.10:                              ; @.str.10
	.asciz	"Couldn't detect MII PHY, assuming address 0x01\n"

	.comm	_NETIF_F_HW_VLAN_CTAG_RX,4,2    ; @NETIF_F_HW_VLAN_CTAG_RX
	.comm	_NETIF_F_HW_VLAN_CTAG_TX,4,2    ; @NETIF_F_HW_VLAN_CTAG_TX
	.no_dead_strip	_amd8111e_probe_one
.subsections_via_symbols
