	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_t1_tp_intr_disable             ## -- Begin function t1_tp_intr_disable
	.p2align	4, 0x90
_t1_tp_intr_disable:                    ## @t1_tp_intr_disable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	(%rdi), %rax
	movq	_A_PL_ENABLE@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	addq	(%rax), %rdi
	callq	_readl
	movl	%eax, %r14d
	movq	(%rbx), %rax
	movq	_A_TP_INT_ENABLE@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rsi
	addq	(%rax), %rsi
	xorl	%edi, %edi
	callq	_writel
	movq	_F_PL_INTR_TP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	notl	%edi
	andl	%r14d, %edi
	movq	(%rbx), %rax
	movq	(%r15), %rsi
	addq	(%rax), %rsi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_writel                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_A_PL_ENABLE,8,3                ## @A_PL_ENABLE
	.comm	_A_TP_INT_ENABLE,8,3            ## @A_TP_INT_ENABLE
	.comm	_F_PL_INTR_TP,4,2               ## @F_PL_INTR_TP
	.comm	_FPGA_PCIX_INTERRUPT_TP,4,2     ## @FPGA_PCIX_INTERRUPT_TP
	.comm	_FPGA_TP_ADDR_INTERRUPT_ENABLE,8,3 ## @FPGA_TP_ADDR_INTERRUPT_ENABLE
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_t1_tp_intr_disable             ; -- Begin function t1_tp_intr_disable
	.p2align	2
_t1_tp_intr_disable:                    ; @t1_tp_intr_disable
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x8, [x0]
	ldr	x8, [x8]
Lloh0:
	adrp	x21, _A_PL_ENABLE@GOTPAGE
Lloh1:
	ldr	x21, [x21, _A_PL_ENABLE@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_readl
	mov	x20, x0
	ldr	x8, [x19]
	ldr	x8, [x8]
Lloh2:
	adrp	x9, _A_TP_INT_ENABLE@GOTPAGE
Lloh3:
	ldr	x9, [x9, _A_TP_INT_ENABLE@GOTPAGEOFF]
Lloh4:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #0
	bl	_writel
Lloh5:
	adrp	x8, _F_PL_INTR_TP@GOTPAGE
Lloh6:
	ldr	x8, [x8, _F_PL_INTR_TP@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	bic	w0, w20, w8
	ldr	x8, [x19]
	ldr	x8, [x8]
	ldr	x9, [x21]
	add	x1, x9, x8
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_writel
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_A_PL_ENABLE,8,3                ; @A_PL_ENABLE
	.comm	_A_TP_INT_ENABLE,8,3            ; @A_TP_INT_ENABLE
	.comm	_F_PL_INTR_TP,4,2               ; @F_PL_INTR_TP
	.comm	_FPGA_PCIX_INTERRUPT_TP,4,2     ; @FPGA_PCIX_INTERRUPT_TP
	.comm	_FPGA_TP_ADDR_INTERRUPT_ENABLE,8,3 ; @FPGA_TP_ADDR_INTERRUPT_ENABLE
.subsections_via_symbols
