	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function goya_pldm_init_cpu
_goya_pldm_init_cpu:                    ## @goya_pldm_init_cpu
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	callq	_goya_init_golden_registers
	movq	_mmCPU_CA53_CFG_ARM_RST_CONTROL@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	movq	_CPU_RESET_ASSERT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_WREG32
	movl	(%r15), %edi
	callq	_RREG32
	movq	_mmPSOC_GLOBAL_CONF_UNIT_RST_N@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_RREG32
	movl	%eax, %r12d
	movl	(%rbx), %edi
	movq	_CA53_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_WREG32
	movl	(%rbx), %edi
	callq	_RREG32
	movl	(%rbx), %edi
	movl	%r12d, %esi
	callq	_WREG32
	movl	(%rbx), %edi
	callq	_RREG32
	movq	%r14, %rdi
	callq	_goya_push_uboot_to_device
	testl	%eax, %eax
	jne	LBB0_3
## %bb.1:
	movq	%r14, %rdi
	callq	_goya_push_linux_to_device
	testl	%eax, %eax
	jne	LBB0_3
## %bb.2:
	movq	_mmPSOC_GLOBAL_CONF_UBOOT_MAGIC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_KMD_MSG_FIT_RDY@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_WREG32
	movq	_mmPSOC_GLOBAL_CONF_WARM_REBOOT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_CPU_BOOT_STATUS_NA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_WREG32
	movq	_mmCPU_CA53_CFG_RST_ADDR_LSB_0@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_SRAM_BASE_ADDR@GOTPCREL(%rip), %r14
	movq	_UBOOT_FW_OFFSET@GOTPCREL(%rip), %r12
	movq	(%r12), %rdi
	addq	(%r14), %rdi
	callq	_lower_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_mmCPU_CA53_CFG_RST_ADDR_MSB_0@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	(%r12), %rdi
	addq	(%r14), %rdi
	callq	_upper_32_bits
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movl	(%r15), %edi
	movq	_CPU_RESET_CORE0_DEASSERT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_WREG32
	movl	(%r15), %edi
	callq	_RREG32
	xorl	%eax, %eax
LBB0_3:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_mmCPU_CA53_CFG_ARM_RST_CONTROL,4,2 ## @mmCPU_CA53_CFG_ARM_RST_CONTROL
	.comm	_CPU_RESET_ASSERT,4,2           ## @CPU_RESET_ASSERT
	.comm	_mmPSOC_GLOBAL_CONF_UNIT_RST_N,4,2 ## @mmPSOC_GLOBAL_CONF_UNIT_RST_N
	.comm	_CA53_RESET,4,2                 ## @CA53_RESET
	.comm	_mmPSOC_GLOBAL_CONF_UBOOT_MAGIC,4,2 ## @mmPSOC_GLOBAL_CONF_UBOOT_MAGIC
	.comm	_KMD_MSG_FIT_RDY,4,2            ## @KMD_MSG_FIT_RDY
	.comm	_mmPSOC_GLOBAL_CONF_WARM_REBOOT,4,2 ## @mmPSOC_GLOBAL_CONF_WARM_REBOOT
	.comm	_CPU_BOOT_STATUS_NA,4,2         ## @CPU_BOOT_STATUS_NA
	.comm	_mmCPU_CA53_CFG_RST_ADDR_LSB_0,4,2 ## @mmCPU_CA53_CFG_RST_ADDR_LSB_0
	.comm	_SRAM_BASE_ADDR,8,3             ## @SRAM_BASE_ADDR
	.comm	_UBOOT_FW_OFFSET,8,3            ## @UBOOT_FW_OFFSET
	.comm	_mmCPU_CA53_CFG_RST_ADDR_MSB_0,4,2 ## @mmCPU_CA53_CFG_RST_ADDR_MSB_0
	.comm	_CPU_RESET_CORE0_DEASSERT,4,2   ## @CPU_RESET_CORE0_DEASSERT
	.no_dead_strip	_goya_pldm_init_cpu
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function goya_pldm_init_cpu
_goya_pldm_init_cpu:                    ; @goya_pldm_init_cpu
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	bl	_goya_init_golden_registers
Lloh0:
	adrp	x21, _mmCPU_CA53_CFG_ARM_RST_CONTROL@GOTPAGE
Lloh1:
	ldr	x21, [x21, _mmCPU_CA53_CFG_ARM_RST_CONTROL@GOTPAGEOFF]
	ldr	w0, [x21]
Lloh2:
	adrp	x8, _CPU_RESET_ASSERT@GOTPAGE
Lloh3:
	ldr	x8, [x8, _CPU_RESET_ASSERT@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
	bl	_WREG32
	ldr	w0, [x21]
	bl	_RREG32
Lloh5:
	adrp	x22, _mmPSOC_GLOBAL_CONF_UNIT_RST_N@GOTPAGE
Lloh6:
	ldr	x22, [x22, _mmPSOC_GLOBAL_CONF_UNIT_RST_N@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_RREG32
	mov	x20, x0
	ldr	w0, [x22]
Lloh7:
	adrp	x8, _CA53_RESET@GOTPAGE
Lloh8:
	ldr	x8, [x8, _CA53_RESET@GOTPAGEOFF]
Lloh9:
	ldr	w1, [x8]
	bl	_WREG32
	ldr	w0, [x22]
	bl	_RREG32
	ldr	w0, [x22]
	mov	x1, x20
	bl	_WREG32
	ldr	w0, [x22]
	bl	_RREG32
	mov	x0, x19
	bl	_goya_push_uboot_to_device
	cbnz	w0, LBB0_3
; %bb.1:
	mov	x0, x19
	bl	_goya_push_linux_to_device
	cbnz	w0, LBB0_3
; %bb.2:
Lloh10:
	adrp	x8, _mmPSOC_GLOBAL_CONF_UBOOT_MAGIC@GOTPAGE
Lloh11:
	ldr	x8, [x8, _mmPSOC_GLOBAL_CONF_UBOOT_MAGIC@GOTPAGEOFF]
Lloh12:
	ldr	w0, [x8]
Lloh13:
	adrp	x8, _KMD_MSG_FIT_RDY@GOTPAGE
Lloh14:
	ldr	x8, [x8, _KMD_MSG_FIT_RDY@GOTPAGEOFF]
Lloh15:
	ldr	w1, [x8]
	bl	_WREG32
Lloh16:
	adrp	x8, _mmPSOC_GLOBAL_CONF_WARM_REBOOT@GOTPAGE
Lloh17:
	ldr	x8, [x8, _mmPSOC_GLOBAL_CONF_WARM_REBOOT@GOTPAGEOFF]
Lloh18:
	ldr	w0, [x8]
Lloh19:
	adrp	x8, _CPU_BOOT_STATUS_NA@GOTPAGE
Lloh20:
	ldr	x8, [x8, _CPU_BOOT_STATUS_NA@GOTPAGEOFF]
Lloh21:
	ldr	w1, [x8]
	bl	_WREG32
Lloh22:
	adrp	x8, _mmCPU_CA53_CFG_RST_ADDR_LSB_0@GOTPAGE
Lloh23:
	ldr	x8, [x8, _mmCPU_CA53_CFG_RST_ADDR_LSB_0@GOTPAGEOFF]
Lloh24:
	adrp	x20, _SRAM_BASE_ADDR@GOTPAGE
Lloh25:
	ldr	x20, [x20, _SRAM_BASE_ADDR@GOTPAGEOFF]
Lloh26:
	ldr	w19, [x8]
	ldr	x8, [x20]
Lloh27:
	adrp	x22, _UBOOT_FW_OFFSET@GOTPAGE
Lloh28:
	ldr	x22, [x22, _UBOOT_FW_OFFSET@GOTPAGEOFF]
	ldr	x9, [x22]
	add	x0, x9, x8
	bl	_lower_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_WREG32
Lloh29:
	adrp	x8, _mmCPU_CA53_CFG_RST_ADDR_MSB_0@GOTPAGE
Lloh30:
	ldr	x8, [x8, _mmCPU_CA53_CFG_RST_ADDR_MSB_0@GOTPAGEOFF]
Lloh31:
	ldr	w19, [x8]
	ldr	x8, [x20]
	ldr	x9, [x22]
	add	x0, x9, x8
	bl	_upper_32_bits
	mov	x1, x0
	mov	x0, x19
	bl	_WREG32
	ldr	w0, [x21]
Lloh32:
	adrp	x8, _CPU_RESET_CORE0_DEASSERT@GOTPAGE
Lloh33:
	ldr	x8, [x8, _CPU_RESET_CORE0_DEASSERT@GOTPAGEOFF]
Lloh34:
	ldr	w1, [x8]
	bl	_WREG32
	ldr	w0, [x21]
	bl	_RREG32
	mov	w0, #0
LBB0_3:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh26
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.cfi_endproc
                                        ; -- End function
	.comm	_mmCPU_CA53_CFG_ARM_RST_CONTROL,4,2 ; @mmCPU_CA53_CFG_ARM_RST_CONTROL
	.comm	_CPU_RESET_ASSERT,4,2           ; @CPU_RESET_ASSERT
	.comm	_mmPSOC_GLOBAL_CONF_UNIT_RST_N,4,2 ; @mmPSOC_GLOBAL_CONF_UNIT_RST_N
	.comm	_CA53_RESET,4,2                 ; @CA53_RESET
	.comm	_mmPSOC_GLOBAL_CONF_UBOOT_MAGIC,4,2 ; @mmPSOC_GLOBAL_CONF_UBOOT_MAGIC
	.comm	_KMD_MSG_FIT_RDY,4,2            ; @KMD_MSG_FIT_RDY
	.comm	_mmPSOC_GLOBAL_CONF_WARM_REBOOT,4,2 ; @mmPSOC_GLOBAL_CONF_WARM_REBOOT
	.comm	_CPU_BOOT_STATUS_NA,4,2         ; @CPU_BOOT_STATUS_NA
	.comm	_mmCPU_CA53_CFG_RST_ADDR_LSB_0,4,2 ; @mmCPU_CA53_CFG_RST_ADDR_LSB_0
	.comm	_SRAM_BASE_ADDR,8,3             ; @SRAM_BASE_ADDR
	.comm	_UBOOT_FW_OFFSET,8,3            ; @UBOOT_FW_OFFSET
	.comm	_mmCPU_CA53_CFG_RST_ADDR_MSB_0,4,2 ; @mmCPU_CA53_CFG_RST_ADDR_MSB_0
	.comm	_CPU_RESET_CORE0_DEASSERT,4,2   ; @CPU_RESET_CORE0_DEASSERT
	.no_dead_strip	_goya_pldm_init_cpu
.subsections_via_symbols
