	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function lio_cn6xxx_setup_device_regs
_lio_cn6xxx_setup_device_regs:          ## @lio_cn6xxx_setup_device_regs
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	movq	_PCIE_MPS_DEFAULT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_lio_cn6xxx_setup_pcie_mps
	movq	_PCIE_MRRS_512B@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_lio_cn6xxx_setup_pcie_mrrs
	movq	%rbx, %rdi
	callq	_lio_cn6xxx_enable_error_reporting
	movq	%rbx, %rdi
	callq	_lio_cn6xxx_setup_global_input_regs
	movq	%rbx, %rdi
	callq	_lio_cn66xx_setup_pkt_ctl_regs
	movq	%rbx, %rdi
	callq	_lio_cn6xxx_setup_global_output_regs
	movq	_CN6XXX_SLI_WINDOW_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$2097152, %edx                  ## imm = 0x200000
	callq	_octeon_write_csr64
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PCIE_MPS_DEFAULT,4,2           ## @PCIE_MPS_DEFAULT
	.comm	_PCIE_MRRS_512B,4,2             ## @PCIE_MRRS_512B
	.comm	_CN6XXX_SLI_WINDOW_CTL,4,2      ## @CN6XXX_SLI_WINDOW_CTL
	.no_dead_strip	_lio_cn6xxx_setup_device_regs
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function lio_cn6xxx_setup_device_regs
_lio_cn6xxx_setup_device_regs:          ; @lio_cn6xxx_setup_device_regs
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
Lloh0:
	adrp	x8, _PCIE_MPS_DEFAULT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCIE_MPS_DEFAULT@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	bl	_lio_cn6xxx_setup_pcie_mps
Lloh3:
	adrp	x8, _PCIE_MRRS_512B@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCIE_MRRS_512B@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_lio_cn6xxx_setup_pcie_mrrs
	mov	x0, x19
	bl	_lio_cn6xxx_enable_error_reporting
	mov	x0, x19
	bl	_lio_cn6xxx_setup_global_input_regs
	mov	x0, x19
	bl	_lio_cn66xx_setup_pkt_ctl_regs
	mov	x0, x19
	bl	_lio_cn6xxx_setup_global_output_regs
Lloh6:
	adrp	x8, _CN6XXX_SLI_WINDOW_CTL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _CN6XXX_SLI_WINDOW_CTL@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #2097152
	bl	_octeon_write_csr64
	mov	w0, #0
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_PCIE_MPS_DEFAULT,4,2           ; @PCIE_MPS_DEFAULT
	.comm	_PCIE_MRRS_512B,4,2             ; @PCIE_MRRS_512B
	.comm	_CN6XXX_SLI_WINDOW_CTL,4,2      ; @CN6XXX_SLI_WINDOW_CTL
	.no_dead_strip	_lio_cn6xxx_setup_device_regs
.subsections_via_symbols
