	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function stv0367_pll_setup
_stv0367_pll_setup:                     ## @stv0367_pll_setup
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	cmpl	$128, %esi
	jne	LBB0_2
## %bb.1:
	leaq	L_.str(%rip), %rdi
	callq	_dprintk
	movl	$232, %r14d
	movl	$27, %edx
	jmp	LBB0_9
LBB0_2:
	cmpl	$16000000, %edx                 ## imm = 0xF42400
	je	LBB0_3
## %bb.4:
	cmpl	$30000000, %edx                 ## imm = 0x1C9C380
	je	LBB0_8
## %bb.5:
	cmpl	$25000000, %edx                 ## imm = 0x17D7840
	jne	LBB0_7
## %bb.6:
	movl	$85, %r14d
	movl	$10, %edx
	jmp	LBB0_9
LBB0_3:
	movl	$27, %r14d
	movl	$2, %edx
	jmp	LBB0_9
LBB0_8:
	movl	$85, %r14d
	movl	$12, %edx
	jmp	LBB0_9
LBB0_7:
	leaq	L_.str.1(%rip), %rdi
	callq	_dprintk
	movl	$8, %r14d
	movl	$1, %edx
LBB0_9:
	movq	_R367TER_PLLMDIV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_stv0367_writereg
	movq	_R367TER_PLLNDIV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	%r14d, %edx
	callq	_stv0367_writereg
	movq	_R367TER_PLLSETUP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$24, %edx
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_stv0367_writereg               ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"STV0367 SetCLKgen for 58MHz IC and 27Mhz crystal\n"

	.comm	_R367TER_PLLMDIV,4,2            ## @R367TER_PLLMDIV
	.comm	_R367TER_PLLNDIV,4,2            ## @R367TER_PLLNDIV
L_.str.1:                               ## @.str.1
	.asciz	"FE_STV0367TER_SetCLKgen for 27Mhz\n"

	.comm	_R367TER_PLLSETUP,4,2           ## @R367TER_PLLSETUP
	.no_dead_strip	_stv0367_pll_setup
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function stv0367_pll_setup
_stv0367_pll_setup:                     ; @stv0367_pll_setup
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	cmp	w1, #128
	b.ne	LBB0_2
; %bb.1:
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_dprintk
	mov	w20, #232
	mov	w2, #27
	b	LBB0_9
LBB0_2:
	mov	w8, #9216
	movk	w8, #244, lsl #16
	cmp	w2, w8
	b.eq	LBB0_6
; %bb.3:
	mov	w8, #50048
	movk	w8, #457, lsl #16
	cmp	w2, w8
	b.eq	LBB0_7
; %bb.4:
	mov	w8, #30784
	movk	w8, #381, lsl #16
	cmp	w2, w8
	b.ne	LBB0_8
; %bb.5:
	mov	w20, #85
	mov	w2, #10
	b	LBB0_9
LBB0_6:
	mov	w20, #27
	mov	w2, #2
	b	LBB0_9
LBB0_7:
	mov	w20, #85
	mov	w2, #12
	b	LBB0_9
LBB0_8:
Lloh2:
	adrp	x0, l_.str.1@PAGE
Lloh3:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_dprintk
	mov	w20, #8
	mov	w2, #1
LBB0_9:
Lloh4:
	adrp	x8, _R367TER_PLLMDIV@GOTPAGE
Lloh5:
	ldr	x8, [x8, _R367TER_PLLMDIV@GOTPAGEOFF]
Lloh6:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_stv0367_writereg
Lloh7:
	adrp	x8, _R367TER_PLLNDIV@GOTPAGE
Lloh8:
	ldr	x8, [x8, _R367TER_PLLNDIV@GOTPAGEOFF]
Lloh9:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_stv0367_writereg
Lloh10:
	adrp	x8, _R367TER_PLLSETUP@GOTPAGE
Lloh11:
	ldr	x8, [x8, _R367TER_PLLSETUP@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #24
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_stv0367_writereg
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"STV0367 SetCLKgen for 58MHz IC and 27Mhz crystal\n"

	.comm	_R367TER_PLLMDIV,4,2            ; @R367TER_PLLMDIV
	.comm	_R367TER_PLLNDIV,4,2            ; @R367TER_PLLNDIV
l_.str.1:                               ; @.str.1
	.asciz	"FE_STV0367TER_SetCLKgen for 27Mhz\n"

	.comm	_R367TER_PLLSETUP,4,2           ; @R367TER_PLLSETUP
	.no_dead_strip	_stv0367_pll_setup
.subsections_via_symbols
