	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4                               ## -- Begin function bnx2_init_board
LCPI0_0:
	.long	2                               ## 0x2
	.long	20                              ## 0x14
	.long	18                              ## 0x12
	.long	80                              ## 0x50
LCPI0_1:
	.long	2                               ## 0x2
	.long	12                              ## 0xc
	.long	18                              ## 0x12
	.long	18                              ## 0x12
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	4, 0x90
_bnx2_init_board:                       ## @bnx2_init_board
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r12
	movq	%rdi, %r14
	leaq	24(%rdi), %r13
	movq	%rsi, %rdi
	movq	%r13, %rsi
	callq	_SET_NETDEV_DEV
	movq	%r12, %rdi
	callq	_netdev_priv
	movq	%rax, %r15
	movq	$0, (%rax)
	movq	_GFP_KERNEL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$4, %edi
	callq	_kzalloc
	movl	%eax, 108(%r15)
	testl	%eax, %eax
	je	LBB0_1
## %bb.2:
	movq	%r14, %rdi
	callq	_pci_enable_device
	testl	%eax, %eax
	je	LBB0_5
## %bb.3:
	movl	%eax, %ebx
	leaq	L_.str(%rip), %rsi
	movq	%r13, %rdi
	callq	_dev_err
	jmp	LBB0_4
LBB0_1:
	movq	_ENOMEM@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
	jmp	LBB0_4
LBB0_5:
	xorl	%ebx, %ebx
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_pci_resource_flags
	movq	_IORESOURCE_MEM@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_6
## %bb.7:
	movq	_DRV_MODULE_NAME@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_pci_request_regions
	testl	%eax, %eax
	je	LBB0_10
## %bb.8:
	movl	%eax, %ebx
	leaq	L_.str.2(%rip), %rsi
	movq	%r13, %rdi
	callq	_dev_err
	jmp	LBB0_9
LBB0_6:
	leaq	L_.str.1(%rip), %rsi
	movq	%r13, %rdi
	callq	_dev_err
	movq	_ENODEV@GOTPCREL(%rip), %rax
	subl	(%rax), %ebx
	jmp	LBB0_9
LBB0_10:
	movq	%r14, %rdi
	callq	_pci_set_master
	movq	(%r14), %rax
	movq	%rax, 8(%r15)
	testq	%rax, %rax
	je	LBB0_11
## %bb.12:
	movq	%r12, 200(%r15)
	movq	%r14, 160(%r15)
	leaq	192(%r15), %rdi
	callq	_spin_lock_init
	leaq	188(%r15), %rdi
	callq	_spin_lock_init
	leaq	180(%r15), %rdi
	movq	_bnx2_reset_task@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_WORK
	movq	_TX_TSS_CID@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_TX_MAX_TSS_RINGS@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	leaq	(%rax,%rcx), %rdi
	incq	%rdi
	callq	_MB_GET_CID_ADDR
	xorl	%ebx, %ebx
	movq	%r14, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_pci_iomap
	movq	%rax, 112(%r15)
	testq	%rax, %rax
	je	LBB0_13
## %bb.14:
	movq	_BNX2_PCICFG_MISC_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA@GOTPCREL(%rip), %rax
	movq	_BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	%r15, %rdi
	callq	_BNX2_WR
	movq	_BNX2_MISC_ID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_BNX2_RD
	movl	%eax, 16(%r15)
	movq	%r15, %rdi
	callq	_BNX2_CHIP
	movq	_BNX2_CHIP_5709@GOTPCREL(%rip), %rbx
	cmpq	(%rbx), %rax
	jne	LBB0_23
## %bb.15:
	movq	%r14, %rdi
	callq	_pci_is_pcie
	testl	%eax, %eax
	je	LBB0_16
## %bb.19:
	movq	_BNX2_FLAG_PCIE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r15)
	movq	%r15, %rdi
	callq	_BNX2_CHIP_REV
	movq	_BNX2_CHIP_REV_Ax@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_21
## %bb.20:
	movq	_BNX2_FLAG_JUMBO_BROKEN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r15)
LBB0_21:
	movq	%r14, %rdi
	callq	_pci_enable_pcie_error_reporting
	testl	%eax, %eax
	jne	LBB0_26
## %bb.22:
	movq	_BNX2_FLAG_AER_ENABLED@GOTPCREL(%rip), %rax
	jmp	LBB0_25
LBB0_11:
	leaq	L_.str.3(%rip), %rsi
	movq	%r13, %rdi
	callq	_dev_err
	movq	_EIO@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
	jmp	LBB0_54
LBB0_13:
	leaq	L_.str.4(%rip), %rsi
	movq	%r13, %rdi
	callq	_dev_err
	movq	_ENOMEM@GOTPCREL(%rip), %rax
	subl	(%rax), %ebx
	jmp	LBB0_54
LBB0_23:
	movq	_PCI_CAP_ID_PCIX@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_pci_find_capability
	movq	%rax, 24(%r15)
	testq	%rax, %rax
	je	LBB0_122
## %bb.24:
	movq	_BNX2_FLAG_BROKEN_STATS@GOTPCREL(%rip), %rax
LBB0_25:
	movl	(%rax), %eax
	orl	%eax, (%r15)
LBB0_26:
	movq	%r15, %rdi
	callq	_BNX2_CHIP
	cmpq	(%rbx), %rax
	jne	LBB0_30
## %bb.27:
	movq	%r15, %rdi
	callq	_BNX2_CHIP_REV
	movq	_BNX2_CHIP_REV_Ax@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_30
## %bb.28:
	cmpq	$0, 40(%r14)
	je	LBB0_30
## %bb.29:
	movq	_BNX2_FLAG_MSIX_CAP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r15)
LBB0_30:
	movq	%r15, %rdi
	callq	_BNX2_CHIP_ID
	movq	_BNX2_CHIP_ID_5706_A0@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_34
## %bb.31:
	movq	%r15, %rdi
	callq	_BNX2_CHIP_ID
	movq	_BNX2_CHIP_ID_5706_A1@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_34
## %bb.32:
	cmpq	$0, 32(%r14)
	je	LBB0_34
## %bb.33:
	movq	_BNX2_FLAG_MSI_CAP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r15)
LBB0_34:
	movq	%r15, %rdi
	callq	_BNX2_CHIP
	movq	_BNX2_CHIP_5708@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	movl	$40, %eax
	movl	$64, %edi
	cmovel	%eax, %edi
	callq	_DMA_BIT_MASK
	movl	%eax, %ebx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_pci_set_dma_mask
	testq	%rax, %rax
	je	LBB0_35
## %bb.37:
	movl	$32, %edi
	callq	_DMA_BIT_MASK
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_pci_set_dma_mask
	movq	%rax, %rbx
	testl	%ebx, %ebx
	je	LBB0_40
## %bb.38:
	leaq	L_.str.8(%rip), %rsi
	jmp	LBB0_39
LBB0_35:
	movq	_NETIF_F_HIGHDMA@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r12)
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_pci_set_consistent_dma_mask
	testl	%eax, %eax
	je	LBB0_40
## %bb.36:
	movl	%eax, %ebx
	leaq	L_.str.7(%rip), %rsi
LBB0_39:
	movq	%r13, %rdi
	callq	_dev_err
	jmp	LBB0_51
LBB0_40:
	movq	_BNX2_FLAG_PCIE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r15)
	jne	LBB0_42
## %bb.41:
	movq	%r15, %rdi
	callq	_bnx2_get_pci_speed
LBB0_42:
	movq	%r15, %rdi
	callq	_BNX2_CHIP_ID
	movq	_BNX2_CHIP_ID_5706_A0@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_48
## %bb.43:
	movq	_PCI_COMMAND@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_BNX2_RD
	movq	_PCI_COMMAND_SERR@GOTPCREL(%rip), %rcx
	movq	_PCI_COMMAND_PARITY@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	movl	%eax, -44(%rbp)
	notl	%edx
	andl	%eax, %edx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_BNX2_WR
	jmp	LBB0_44
LBB0_16:
	leaq	L_.str.5(%rip), %rsi
	jmp	LBB0_17
LBB0_122:
	leaq	L_.str.6(%rip), %rsi
LBB0_17:
	movq	%r13, %rdi
	callq	_dev_err
	movq	_EIO@GOTPCREL(%rip), %rax
	jmp	LBB0_18
LBB0_48:
	movq	%r15, %rdi
	callq	_BNX2_CHIP_ID
	movq	_BNX2_CHIP_ID_5706_A1@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_44
## %bb.49:
	movq	_BNX2_FLAG_PCIX@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r15)
	je	LBB0_50
LBB0_44:
	movq	%r15, %rdi
	callq	_bnx2_init_nvram
	movq	_BNX2_SHM_HDR_SIGNATURE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_bnx2_reg_rd_ind
	movl	%eax, %ebx
	movq	_BNX2_MCP_TOE_ID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_bnx2_reg_rd_ind
	movq	_BNX2_MCP_TOE_ID_FUNCTION_ID@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_46
## %bb.45:
	movl	$1, 32(%r15)
LBB0_46:
	movq	_BNX2_SHM_HDR_SIGNATURE_SIG_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %ebx
	movq	_BNX2_SHM_HDR_SIGNATURE_SIG@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	jne	LBB0_55
## %bb.47:
	movl	32(%r15), %esi
	shll	$2, %esi
	movq	_BNX2_SHM_HDR_ADDR_0@GOTPCREL(%rip), %rax
	addl	(%rax), %esi
	movq	%r15, %rdi
	callq	_bnx2_reg_rd_ind
	jmp	LBB0_56
LBB0_55:
	movq	_HOST_VIEW_SHMEM_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_56:
	movl	%eax, 36(%r15)
	movq	_BNX2_DEV_INFO_SIGNATURE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_bnx2_shmem_rd
	movl	%eax, -44(%rbp)
	movq	_BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_BNX2_DEV_INFO_SIGNATURE_MAGIC@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_57
## %bb.58:
	movq	%r15, %rdi
	callq	_bnx2_read_vpd_fw_ver
	movq	40(%r15), %rdi
	callq	_strlen
	movl	%eax, %ebx
	movq	_BNX2_DEV_INFO_BC_REV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_bnx2_shmem_rd
	movl	%eax, -44(%rbp)
	cmpl	$23, %ebx
	jg	LBB0_59
## %bb.60:
	movl	$24, %ecx
LBB0_61:                                ## =>This Inner Loop Header: Depth=1
	cmpl	$24, %ecx
	jne	LBB0_63
## %bb.62:                              ##   in Loop: Header=BB0_61 Depth=1
	movq	40(%r15), %rax
	movslq	%ebx, %rdx
	movb	$98, (%rax,%rdx)
	movq	40(%r15), %rax
	movb	$99, 1(%rdx,%rax)
	movq	40(%r15), %rax
	leal	3(%rdx), %ebx
	movb	$32, 2(%rdx,%rax)
LBB0_63:                                ##   in Loop: Header=BB0_61 Depth=1
	movl	-44(%rbp), %eax
	sarl	%cl, %eax
	cmpl	$100, %eax
	jl	LBB0_65
## %bb.64:                              ##   in Loop: Header=BB0_61 Depth=1
	movl	%eax, %edx
	imulq	$1374389535, %rdx, %rdx         ## imm = 0x51EB851F
	shrq	$37, %rdx
	leal	48(%rdx), %r8d
	movq	40(%r15), %rdi
	movslq	%ebx, %rsi
	incl	%ebx
	movb	%r8b, (%rdi,%rsi)
	imull	$100, %edx, %edx
	subl	%edx, %eax
	jmp	LBB0_66
LBB0_65:                                ##   in Loop: Header=BB0_61 Depth=1
	movslq	%eax, %rdx
	imulq	$1374389535, %rdx, %rdx         ## imm = 0x51EB851F
	movq	%rdx, %rsi
	shrq	$63, %rsi
	sarq	$37, %rdx
	addl	%esi, %edx
	imull	$100, %edx, %edx
	subl	%edx, %eax
	cmpl	$10, %eax
	jl	LBB0_67
LBB0_66:                                ##   in Loop: Header=BB0_61 Depth=1
	movsbl	%al, %edx
	imull	$103, %edx, %edx
	movzwl	%dx, %edx
	movswl	%dx, %esi
	shrl	$15, %edx
	shrl	$10, %esi
	addb	%dl, %sil
	addb	$48, %sil
	movq	40(%r15), %rdx
	movslq	%ebx, %rdi
	incl	%ebx
	movb	%sil, (%rdx,%rdi)
LBB0_67:                                ##   in Loop: Header=BB0_61 Depth=1
	movsbl	%al, %edx
	imull	$103, %edx, %edx
	movzwl	%dx, %edx
	movswl	%dx, %esi
	shrl	$15, %edx
	shrl	$10, %esi
	addb	%dl, %sil
	movzbl	%sil, %edx
	addl	%edx, %edx
	leal	(%rdx,%rdx,4), %edx
	subb	%dl, %al
	addb	$48, %al
	movq	40(%r15), %rsi
	movslq	%ebx, %rdx
	movb	%al, (%rsi,%rdx)
	incq	%rdx
	addl	$-8, %ecx
	je	LBB0_68
## %bb.69:                              ##   in Loop: Header=BB0_61 Depth=1
	movq	40(%r15), %rax
	leal	2(%rbx), %r13d
	movb	$46, (%rax,%rdx)
	cmpl	$22, %ebx
	movl	%r13d, %ebx
	jl	LBB0_61
	jmp	LBB0_70
LBB0_57:
	leaq	L_.str.10(%rip), %rsi
	movq	%r13, %rdi
	callq	_dev_err
	movq	_ENODEV@GOTPCREL(%rip), %rax
LBB0_18:
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
LBB0_51:
	movq	_BNX2_FLAG_AER_ENABLED@GOTPCREL(%rip), %r12
	movl	(%r12), %eax
	testl	%eax, (%r15)
	je	LBB0_53
## %bb.52:
	movq	%r14, %rdi
	callq	_pci_disable_pcie_error_reporting
	movl	(%r12), %eax
	notl	%eax
	andl	%eax, (%r15)
LBB0_53:
	movq	112(%r15), %rsi
	movq	%r14, %rdi
	callq	_pci_iounmap
	movq	$0, 112(%r15)
LBB0_54:
	movq	%r14, %rdi
	callq	_pci_release_regions
LBB0_9:
	movq	%r14, %rdi
	callq	_pci_disable_device
LBB0_4:
	movl	108(%r15), %edi
	callq	_kfree
LBB0_121:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_59:
	movl	%ebx, %r13d
	jmp	LBB0_70
LBB0_68:
	movl	%edx, %r13d
LBB0_70:
	movq	_BNX2_PORT_FEATURE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_bnx2_shmem_rd
	movq	_BNX2_PORT_FEATURE_WOL_ENABLED@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_72
## %bb.71:
	movl	$1, 48(%r15)
LBB0_72:
	movq	_BNX2_PORT_FEATURE_ASF_ENABLED@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_76
## %bb.73:
	movq	_BNX2_FLAG_ASF_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r15)
	movl	$30, %ebx
LBB0_74:                                ## =>This Inner Loop Header: Depth=1
	movq	_BNX2_BC_STATE_CONDITION@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_bnx2_shmem_rd
	movq	_BNX2_CONDITION_MFW_RUN_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	jne	LBB0_76
## %bb.75:                              ##   in Loop: Header=BB0_74 Depth=1
	movl	$10, %edi
	callq	_msleep
	decl	%ebx
	jne	LBB0_74
LBB0_76:
	movq	_BNX2_BC_STATE_CONDITION@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_bnx2_shmem_rd
	movq	_BNX2_CONDITION_MFW_RUN_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movl	%eax, -44(%rbp)
	movq	_BNX2_CONDITION_MFW_RUN_UNKNOWN@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_83
## %bb.77:
	movq	_BNX2_CONDITION_MFW_RUN_NONE@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_83
## %bb.78:
	movq	_BNX2_MFW_VER_PTR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_bnx2_shmem_rd
	cmpl	$31, %r13d
	jg	LBB0_83
## %bb.79:
	movq	40(%r15), %rdx
	movslq	%r13d, %rcx
	movb	$32, (%rdx,%rcx)
	cmpl	$26, %r13d
	jg	LBB0_83
## %bb.80:
	incl	%r13d
	movslq	%r13d, %rbx
	xorl	%r13d, %r13d
LBB0_81:                                ## =>This Inner Loop Header: Depth=1
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	%r15, %rdi
	movl	-48(%rbp), %esi                 ## 4-byte Reload
	callq	_bnx2_reg_rd_ind
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	callq	_be32_to_cpu
	movl	%eax, -44(%rbp)
	movq	40(%r15), %rdi
	addq	%rbx, %rdi
	leaq	-44(%rbp), %rsi
	movl	$4, %edx
	callq	_memcpy
	movl	-48(%rbp), %eax                 ## 4-byte Reload
	cmpl	$1, %r13d
	ja	LBB0_83
## %bb.82:                              ##   in Loop: Header=BB0_81 Depth=1
	leaq	4(%rbx), %rcx
	incl	%r13d
	addl	$4, %eax
	cmpq	$24, %rbx
	movq	%rcx, %rbx
	jl	LBB0_81
LBB0_83:
	movq	_BNX2_PORT_HW_CFG_MAC_UPPER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_bnx2_shmem_rd
	movl	%eax, -44(%rbp)
	sarl	$8, %eax
	movq	56(%r15), %rcx
	movl	%eax, (%rcx)
	movl	-44(%rbp), %eax
	movl	%eax, 4(%rcx)
	movq	_BNX2_PORT_HW_CFG_MAC_LOWER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_bnx2_shmem_rd
	movl	%eax, -44(%rbp)
	movl	%eax, %ecx
	sarl	$24, %ecx
	movq	56(%r15), %rdx
	movl	%ecx, 8(%rdx)
	movl	%eax, %ecx
	sarl	$16, %ecx
	movl	%ecx, 12(%rdx)
	movl	%eax, %ecx
	sarl	$8, %ecx
	movl	%ecx, 16(%rdx)
	movl	%eax, 20(%rdx)
	movq	_BNX2_MAX_TX_DESC_CNT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 176(%r15)
	movq	%r15, %rdi
	movl	$255, %esi
	callq	_bnx2_set_rx_ring_size
	movaps	LCPI0_0(%rip), %xmm0            ## xmm0 = [2,20,18,80]
	movups	%xmm0, 64(%r15)
	movaps	LCPI0_1(%rip), %xmm0            ## xmm0 = [2,12,18,18]
	movups	%xmm0, 80(%r15)
	movq	_USEC_PER_SEC@GOTPCREL(%rip), %rax
	movq	_BNX2_HC_STATS_TICKS_HC_STAT_TICKS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	(%rax), %ecx
	movl	%ecx, 96(%r15)
	movq	_BNX2_TIMER_INTERVAL@GOTPCREL(%rip), %r13
	movl	(%r13), %eax
	movl	%eax, 172(%r15)
	movl	$1, 100(%r15)
	movq	%r12, %rdi
	callq	_bnx2_alloc_stats_blk
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_51
## %bb.84:
	movq	%r15, %rdi
	callq	_BNX2_CHIP
	movq	_BNX2_CHIP_5709@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_86
## %bb.85:
	movq	%r15, %rdi
	callq	_bnx2_get_5709_media
	jmp	LBB0_88
LBB0_50:
	leaq	L_.str.9(%rip), %rsi
	movq	%r13, %rdi
	callq	_dev_err
	xorl	%ebx, %ebx
	jmp	LBB0_51
LBB0_86:
	movq	%r15, %rdi
	callq	_BNX2_CHIP_BOND
	movq	_BNX2_CHIP_BOND_SERDES_BIT@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_88
## %bb.87:
	movq	_BNX2_PHY_FLAG_SERDES@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, 4(%r15)
LBB0_88:
	movq	_PORT_TP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 168(%r15)
	movq	_BNX2_PHY_FLAG_SERDES@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 4(%r15)
	je	LBB0_97
## %bb.89:
	movq	_PORT_FIBRE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 168(%r15)
	movq	_BNX2_SHARED_HW_CFG_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_bnx2_shmem_rd
	movl	%eax, -44(%rbp)
	movq	_BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	jne	LBB0_91
## %bb.90:
	movq	_BNX2_FLAG_NO_WOL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r15)
	movl	$0, 48(%r15)
LBB0_91:
	movq	%r15, %rdi
	callq	_BNX2_CHIP
	movq	_BNX2_CHIP_5706@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_95
## %bb.92:
	movq	8(%r14), %rax
	movq	_PCI_VENDOR_ID_HP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_103
## %bb.93:
	cmpl	$12556, 16(%r14)                ## imm = 0x310C
	jne	LBB0_103
## %bb.94:
	movq	_BNX2_PHY_FLAG_NO_PARALLEL@GOTPCREL(%rip), %rbx
	jmp	LBB0_102
LBB0_97:
	movq	%r15, %rdi
	callq	_BNX2_CHIP
	movq	_BNX2_CHIP_5706@GOTPCREL(%rip), %rcx
	movq	_BNX2_PHY_FLAG_CRC_FIX@GOTPCREL(%rip), %rbx
	cmpq	(%rcx), %rax
	je	LBB0_102
## %bb.98:
	movq	%r15, %rdi
	callq	_BNX2_CHIP
	movq	_BNX2_CHIP_5708@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_102
## %bb.99:
	movq	%r15, %rdi
	callq	_BNX2_CHIP
	movq	_BNX2_CHIP_5709@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_103
## %bb.100:
	movq	%r15, %rdi
	callq	_BNX2_CHIP_REV
	movq	_BNX2_CHIP_REV_Ax@GOTPCREL(%rip), %rcx
	movq	_BNX2_PHY_FLAG_DIS_EARLY_DAC@GOTPCREL(%rip), %rbx
	cmpq	(%rcx), %rax
	je	LBB0_102
## %bb.101:
	movq	%r15, %rdi
	callq	_BNX2_CHIP_REV
	movq	_BNX2_CHIP_REV_Bx@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_102
	jmp	LBB0_103
LBB0_95:
	movl	$2, 100(%r15)
	movq	_BNX2_SHARED_HW_CFG_PHY_2_5G@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, -44(%rbp)
	je	LBB0_103
## %bb.96:
	movq	_BNX2_PHY_FLAG_2_5G_CAPABLE@GOTPCREL(%rip), %rbx
LBB0_102:
	movl	(%rbx), %eax
	orl	%eax, 4(%r15)
LBB0_103:
	movq	%r15, %rdi
	callq	_bnx2_init_fw_cap
	movq	%r15, %rdi
	callq	_BNX2_CHIP_ID
	movq	_BNX2_CHIP_ID_5708_A0@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_108
## %bb.104:
	movq	%r15, %rdi
	callq	_BNX2_CHIP_ID
	movq	_BNX2_CHIP_ID_5708_B0@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_108
## %bb.105:
	movq	%r15, %rdi
	callq	_BNX2_CHIP_ID
	movq	_BNX2_CHIP_ID_5708_B1@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_108
## %bb.106:
	movq	_BNX2_PCI_CONFIG_3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_BNX2_RD
	movq	_BNX2_PCI_CONFIG_3_VAUX_PRESET@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_108
## %bb.107:
	movl	(%r15), %eax
	jmp	LBB0_109
LBB0_108:
	movq	_BNX2_FLAG_NO_WOL@GOTPCREL(%rip), %rcx
	movl	(%r15), %eax
	orl	(%rcx), %eax
	movl	%eax, (%r15)
	movl	$0, 48(%r15)
LBB0_109:
	movq	_BNX2_FLAG_NO_WOL@GOTPCREL(%rip), %rcx
	movq	160(%r15), %rdi
	addq	$24, %rdi
	testl	%eax, (%rcx)
	je	LBB0_111
## %bb.110:
	movq	%r13, %r12
	xorl	%esi, %esi
	callq	_device_set_wakeup_capable
	jmp	LBB0_112
LBB0_111:
	movq	%r13, %r12
	movl	48(%r15), %esi
	callq	_device_set_wakeup_enable
LBB0_112:
	movq	%r15, %rdi
	callq	_BNX2_CHIP_ID
	movq	_BNX2_CHIP_ID_5706_A0@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_114
## %bb.113:
	movl	68(%r15), %eax
	movl	76(%r15), %ecx
	movl	%eax, 64(%r15)
	movl	%ecx, 72(%r15)
	movl	84(%r15), %eax
	movl	%eax, 80(%r15)
	movl	92(%r15), %eax
	movl	%eax, 88(%r15)
	movl	148(%r15), %eax
	movl	%eax, 152(%r15)
	movl	140(%r15), %eax
	movl	%eax, 144(%r15)
	movl	132(%r15), %eax
	movl	%eax, 136(%r15)
LBB0_114:
	movq	%r15, %rdi
	callq	_BNX2_CHIP
	movq	_BNX2_CHIP_5706@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_120
## %bb.115:
	movq	_disable_msi@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	jne	LBB0_120
## %bb.116:
	xorl	%eax, %eax
	movq	_PCI_VENDOR_ID_AMD@GOTPCREL(%rip), %rbx
	movq	_PCI_DEVICE_ID_AMD_8132_BRIDGE@GOTPCREL(%rip), %r13
LBB0_117:                               ## =>This Inner Loop Header: Depth=1
	movl	(%rbx), %edi
	movl	(%r13), %esi
	movq	%rax, %rdx
	callq	_pci_get_device
	testq	%rax, %rax
	je	LBB0_120
## %bb.118:                             ##   in Loop: Header=BB0_117 Depth=1
	movl	20(%rax), %ecx
	andl	$-4, %ecx
	cmpl	$16, %ecx
	jne	LBB0_117
## %bb.119:
	movq	_disable_msi@GOTPCREL(%rip), %rcx
	movl	$1, (%rcx)
	movq	%rax, %rdi
	callq	_pci_dev_put
LBB0_120:
	movq	%r15, %rdi
	callq	_bnx2_set_default_link
	movq	_FLOW_CTRL_RX@GOTPCREL(%rip), %rax
	movq	_FLOW_CTRL_TX@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movl	%ecx, 104(%r15)
	movq	%r15, %rdi
	subq	$-128, %rdi
	movq	_bnx2_timer@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%ebx, %ebx
	xorl	%edx, %edx
	callq	_timer_setup
	movl	(%r12), %edi
	callq	_RUN_AT
	movl	%eax, 128(%r15)
	movq	%r14, %rdi
	callq	_pci_save_state
	jmp	LBB0_121
	.cfi_endproc
                                        ## -- End function
	.comm	_GFP_KERNEL,4,2                 ## @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ## @ENOMEM
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Cannot enable PCI device, aborting\n"

	.comm	_IORESOURCE_MEM,4,2             ## @IORESOURCE_MEM
L_.str.1:                               ## @.str.1
	.asciz	"Cannot find PCI device base address, aborting\n"

	.comm	_ENODEV,4,2                     ## @ENODEV
	.comm	_DRV_MODULE_NAME,4,2            ## @DRV_MODULE_NAME
L_.str.2:                               ## @.str.2
	.asciz	"Cannot obtain PCI resources, aborting\n"

L_.str.3:                               ## @.str.3
	.asciz	"Cannot find power management capability, aborting\n"

	.comm	_EIO,4,2                        ## @EIO
	.comm	_bnx2_reset_task,4,2            ## @bnx2_reset_task
	.comm	_TX_TSS_CID,8,3                 ## @TX_TSS_CID
	.comm	_TX_MAX_TSS_RINGS,8,3           ## @TX_MAX_TSS_RINGS
L_.str.4:                               ## @.str.4
	.asciz	"Cannot map register space, aborting\n"

	.comm	_BNX2_PCICFG_MISC_CONFIG,4,2    ## @BNX2_PCICFG_MISC_CONFIG
	.comm	_BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA,4,2 ## @BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA
	.comm	_BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP,4,2 ## @BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP
	.comm	_BNX2_MISC_ID,4,2               ## @BNX2_MISC_ID
	.comm	_BNX2_CHIP_5709,8,3             ## @BNX2_CHIP_5709
L_.str.5:                               ## @.str.5
	.asciz	"Not PCIE, aborting\n"

	.comm	_BNX2_FLAG_PCIE,4,2             ## @BNX2_FLAG_PCIE
	.comm	_BNX2_CHIP_REV_Ax,8,3           ## @BNX2_CHIP_REV_Ax
	.comm	_BNX2_FLAG_JUMBO_BROKEN,4,2     ## @BNX2_FLAG_JUMBO_BROKEN
	.comm	_BNX2_FLAG_AER_ENABLED,4,2      ## @BNX2_FLAG_AER_ENABLED
	.comm	_PCI_CAP_ID_PCIX,4,2            ## @PCI_CAP_ID_PCIX
L_.str.6:                               ## @.str.6
	.asciz	"Cannot find PCIX capability, aborting\n"

	.comm	_BNX2_FLAG_BROKEN_STATS,4,2     ## @BNX2_FLAG_BROKEN_STATS
	.comm	_BNX2_FLAG_MSIX_CAP,4,2         ## @BNX2_FLAG_MSIX_CAP
	.comm	_BNX2_CHIP_ID_5706_A0,8,3       ## @BNX2_CHIP_ID_5706_A0
	.comm	_BNX2_CHIP_ID_5706_A1,8,3       ## @BNX2_CHIP_ID_5706_A1
	.comm	_BNX2_FLAG_MSI_CAP,4,2          ## @BNX2_FLAG_MSI_CAP
	.comm	_BNX2_CHIP_5708,8,3             ## @BNX2_CHIP_5708
	.comm	_NETIF_F_HIGHDMA,4,2            ## @NETIF_F_HIGHDMA
L_.str.7:                               ## @.str.7
	.asciz	"pci_set_consistent_dma_mask failed, aborting\n"

L_.str.8:                               ## @.str.8
	.asciz	"System does not support DMA, aborting\n"

	.comm	_PCI_COMMAND,4,2                ## @PCI_COMMAND
	.comm	_PCI_COMMAND_SERR,4,2           ## @PCI_COMMAND_SERR
	.comm	_PCI_COMMAND_PARITY,4,2         ## @PCI_COMMAND_PARITY
	.comm	_BNX2_FLAG_PCIX,4,2             ## @BNX2_FLAG_PCIX
L_.str.9:                               ## @.str.9
	.asciz	"5706 A1 can only be used in a PCIX bus, aborting\n"

	.comm	_BNX2_SHM_HDR_SIGNATURE,4,2     ## @BNX2_SHM_HDR_SIGNATURE
	.comm	_BNX2_MCP_TOE_ID,4,2            ## @BNX2_MCP_TOE_ID
	.comm	_BNX2_MCP_TOE_ID_FUNCTION_ID,4,2 ## @BNX2_MCP_TOE_ID_FUNCTION_ID
	.comm	_BNX2_SHM_HDR_SIGNATURE_SIG_MASK,4,2 ## @BNX2_SHM_HDR_SIGNATURE_SIG_MASK
	.comm	_BNX2_SHM_HDR_SIGNATURE_SIG,4,2 ## @BNX2_SHM_HDR_SIGNATURE_SIG
	.comm	_BNX2_SHM_HDR_ADDR_0,4,2        ## @BNX2_SHM_HDR_ADDR_0
	.comm	_HOST_VIEW_SHMEM_BASE,4,2       ## @HOST_VIEW_SHMEM_BASE
	.comm	_BNX2_DEV_INFO_SIGNATURE,4,2    ## @BNX2_DEV_INFO_SIGNATURE
	.comm	_BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK,4,2 ## @BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK
	.comm	_BNX2_DEV_INFO_SIGNATURE_MAGIC,4,2 ## @BNX2_DEV_INFO_SIGNATURE_MAGIC
L_.str.10:                              ## @.str.10
	.asciz	"Firmware not running, aborting\n"

	.comm	_BNX2_DEV_INFO_BC_REV,4,2       ## @BNX2_DEV_INFO_BC_REV
	.comm	_BNX2_PORT_FEATURE,4,2          ## @BNX2_PORT_FEATURE
	.comm	_BNX2_PORT_FEATURE_WOL_ENABLED,4,2 ## @BNX2_PORT_FEATURE_WOL_ENABLED
	.comm	_BNX2_PORT_FEATURE_ASF_ENABLED,4,2 ## @BNX2_PORT_FEATURE_ASF_ENABLED
	.comm	_BNX2_FLAG_ASF_ENABLE,4,2       ## @BNX2_FLAG_ASF_ENABLE
	.comm	_BNX2_BC_STATE_CONDITION,4,2    ## @BNX2_BC_STATE_CONDITION
	.comm	_BNX2_CONDITION_MFW_RUN_MASK,4,2 ## @BNX2_CONDITION_MFW_RUN_MASK
	.comm	_BNX2_CONDITION_MFW_RUN_UNKNOWN,4,2 ## @BNX2_CONDITION_MFW_RUN_UNKNOWN
	.comm	_BNX2_CONDITION_MFW_RUN_NONE,4,2 ## @BNX2_CONDITION_MFW_RUN_NONE
	.comm	_BNX2_MFW_VER_PTR,4,2           ## @BNX2_MFW_VER_PTR
	.comm	_BNX2_PORT_HW_CFG_MAC_UPPER,4,2 ## @BNX2_PORT_HW_CFG_MAC_UPPER
	.comm	_BNX2_PORT_HW_CFG_MAC_LOWER,4,2 ## @BNX2_PORT_HW_CFG_MAC_LOWER
	.comm	_BNX2_MAX_TX_DESC_CNT,4,2       ## @BNX2_MAX_TX_DESC_CNT
	.comm	_USEC_PER_SEC,4,2               ## @USEC_PER_SEC
	.comm	_BNX2_HC_STATS_TICKS_HC_STAT_TICKS,4,2 ## @BNX2_HC_STATS_TICKS_HC_STAT_TICKS
	.comm	_BNX2_TIMER_INTERVAL,4,2        ## @BNX2_TIMER_INTERVAL
	.comm	_BNX2_CHIP_BOND_SERDES_BIT,4,2  ## @BNX2_CHIP_BOND_SERDES_BIT
	.comm	_BNX2_PHY_FLAG_SERDES,4,2       ## @BNX2_PHY_FLAG_SERDES
	.comm	_PORT_TP,4,2                    ## @PORT_TP
	.comm	_PORT_FIBRE,4,2                 ## @PORT_FIBRE
	.comm	_BNX2_SHARED_HW_CFG_CONFIG,4,2  ## @BNX2_SHARED_HW_CFG_CONFIG
	.comm	_BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX,4,2 ## @BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX
	.comm	_BNX2_FLAG_NO_WOL,4,2           ## @BNX2_FLAG_NO_WOL
	.comm	_BNX2_CHIP_5706,8,3             ## @BNX2_CHIP_5706
	.comm	_PCI_VENDOR_ID_HP,8,3           ## @PCI_VENDOR_ID_HP
	.comm	_BNX2_PHY_FLAG_NO_PARALLEL,4,2  ## @BNX2_PHY_FLAG_NO_PARALLEL
	.comm	_BNX2_SHARED_HW_CFG_PHY_2_5G,4,2 ## @BNX2_SHARED_HW_CFG_PHY_2_5G
	.comm	_BNX2_PHY_FLAG_2_5G_CAPABLE,4,2 ## @BNX2_PHY_FLAG_2_5G_CAPABLE
	.comm	_BNX2_PHY_FLAG_CRC_FIX,4,2      ## @BNX2_PHY_FLAG_CRC_FIX
	.comm	_BNX2_CHIP_REV_Bx,8,3           ## @BNX2_CHIP_REV_Bx
	.comm	_BNX2_PHY_FLAG_DIS_EARLY_DAC,4,2 ## @BNX2_PHY_FLAG_DIS_EARLY_DAC
	.comm	_BNX2_CHIP_ID_5708_A0,8,3       ## @BNX2_CHIP_ID_5708_A0
	.comm	_BNX2_CHIP_ID_5708_B0,8,3       ## @BNX2_CHIP_ID_5708_B0
	.comm	_BNX2_CHIP_ID_5708_B1,8,3       ## @BNX2_CHIP_ID_5708_B1
	.comm	_BNX2_PCI_CONFIG_3,4,2          ## @BNX2_PCI_CONFIG_3
	.comm	_BNX2_PCI_CONFIG_3_VAUX_PRESET,4,2 ## @BNX2_PCI_CONFIG_3_VAUX_PRESET
	.comm	_disable_msi,4,2                ## @disable_msi
	.comm	_PCI_VENDOR_ID_AMD,4,2          ## @PCI_VENDOR_ID_AMD
	.comm	_PCI_DEVICE_ID_AMD_8132_BRIDGE,4,2 ## @PCI_DEVICE_ID_AMD_8132_BRIDGE
	.comm	_FLOW_CTRL_RX,4,2               ## @FLOW_CTRL_RX
	.comm	_FLOW_CTRL_TX,4,2               ## @FLOW_CTRL_TX
	.comm	_bnx2_timer,4,2                 ## @bnx2_timer
	.comm	_BNX2_ISCSI_INITIATOR,4,2       ## @BNX2_ISCSI_INITIATOR
	.comm	_BNX2_ISCSI_INITIATOR_EN,4,2    ## @BNX2_ISCSI_INITIATOR_EN
	.comm	_BNX2_ISCSI_MAX_CONN,4,2        ## @BNX2_ISCSI_MAX_CONN
	.comm	_BNX2_ISCSI_MAX_CONN_MASK,4,2   ## @BNX2_ISCSI_MAX_CONN_MASK
	.comm	_BNX2_ISCSI_MAX_CONN_SHIFT,4,2  ## @BNX2_ISCSI_MAX_CONN_SHIFT
	.comm	_bnx2_cnic_probe,4,2            ## @bnx2_cnic_probe
	.no_dead_strip	_bnx2_init_board
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3                               ; -- Begin function bnx2_init_board
lCPI0_0:
	.long	4294967272                      ; 0xffffffe8
	.long	4294967280                      ; 0xfffffff0
	.section	__TEXT,__literal16,16byte_literals
	.p2align	4
lCPI0_1:
	.long	2                               ; 0x2
	.long	20                              ; 0x14
	.long	18                              ; 0x12
	.long	80                              ; 0x50
lCPI0_2:
	.long	2                               ; 0x2
	.long	12                              ; 0xc
	.long	18                              ; 0x12
	.long	18                              ; 0x12
	.section	__TEXT,__text,regular,pure_instructions
	.p2align	2
_bnx2_init_board:                       ; @bnx2_init_board
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x1
	mov	x20, x0
	add	x22, x0, #24
	mov	x0, x1
	mov	x1, x22
	bl	_SET_NETDEV_DEV
	mov	x0, x21
	bl	_netdev_priv
	mov	x19, x0
	str	xzr, [x0]
Lloh0:
	adrp	x8, _GFP_KERNEL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _GFP_KERNEL@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	w0, #4
	bl	_kzalloc
	str	w0, [x19, #108]
	cbz	w0, LBB0_3
; %bb.1:
	mov	x0, x20
	bl	_pci_enable_device
	cbz	w0, LBB0_4
; %bb.2:
	mov	x23, x0
Lloh3:
	adrp	x1, l_.str@PAGE
Lloh4:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x22
	bl	_dev_err
	b	LBB0_61
LBB0_3:
Lloh5:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh6:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	neg	w23, w8
	b	LBB0_61
LBB0_4:
	mov	x0, x20
	mov	w1, #0
	bl	_pci_resource_flags
Lloh8:
	adrp	x8, _IORESOURCE_MEM@GOTPAGE
Lloh9:
	ldr	x8, [x8, _IORESOURCE_MEM@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_7
; %bb.5:
Lloh11:
	adrp	x8, _DRV_MODULE_NAME@GOTPAGE
Lloh12:
	ldr	x8, [x8, _DRV_MODULE_NAME@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_pci_request_regions
	cbz	w0, LBB0_8
; %bb.6:
	mov	x23, x0
Lloh14:
	adrp	x1, l_.str.2@PAGE
Lloh15:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x0, x22
	bl	_dev_err
	b	LBB0_60
LBB0_7:
Lloh16:
	adrp	x1, l_.str.1@PAGE
Lloh17:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x22
	bl	_dev_err
Lloh18:
	adrp	x8, _ENODEV@GOTPAGE
Lloh19:
	ldr	x8, [x8, _ENODEV@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	neg	w23, w8
	b	LBB0_60
LBB0_8:
	mov	x0, x20
	bl	_pci_set_master
	ldr	x8, [x20]
	str	x8, [x19, #8]
	cbz	x8, LBB0_16
; %bb.9:
	str	x21, [x19, #200]
	str	x20, [x19, #160]
	add	x0, x19, #192
	bl	_spin_lock_init
	add	x0, x19, #188
	bl	_spin_lock_init
	add	x0, x19, #180
Lloh21:
	adrp	x8, _bnx2_reset_task@GOTPAGE
Lloh22:
	ldr	x8, [x8, _bnx2_reset_task@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	bl	_INIT_WORK
Lloh24:
	adrp	x8, _TX_TSS_CID@GOTPAGE
Lloh25:
	ldr	x8, [x8, _TX_TSS_CID@GOTPAGEOFF]
Lloh26:
	ldr	x8, [x8]
Lloh27:
	adrp	x9, _TX_MAX_TSS_RINGS@GOTPAGE
Lloh28:
	ldr	x9, [x9, _TX_MAX_TSS_RINGS@GOTPAGEOFF]
Lloh29:
	ldr	x9, [x9]
	add	x8, x8, x9
	add	x0, x8, #1
	bl	_MB_GET_CID_ADDR
	mov	x2, x0
	mov	x0, x20
	mov	w1, #0
	bl	_pci_iomap
	str	x0, [x19, #112]
	cbz	x0, LBB0_17
; %bb.10:
Lloh30:
	adrp	x8, _BNX2_PCICFG_MISC_CONFIG@GOTPAGE
Lloh31:
	ldr	x8, [x8, _BNX2_PCICFG_MISC_CONFIG@GOTPAGEOFF]
Lloh32:
	adrp	x9, _BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA@GOTPAGE
Lloh33:
	ldr	x9, [x9, _BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA@GOTPAGEOFF]
Lloh34:
	ldr	w1, [x8]
Lloh35:
	ldr	w8, [x9]
Lloh36:
	adrp	x9, _BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP@GOTPAGE
Lloh37:
	ldr	x9, [x9, _BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP@GOTPAGEOFF]
Lloh38:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_BNX2_WR
Lloh39:
	adrp	x8, _BNX2_MISC_ID@GOTPAGE
Lloh40:
	ldr	x8, [x8, _BNX2_MISC_ID@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_BNX2_RD
	str	w0, [x19, #16]
	mov	x0, x19
	bl	_BNX2_CHIP
Lloh42:
	adrp	x25, _BNX2_CHIP_5709@GOTPAGE
Lloh43:
	ldr	x25, [x25, _BNX2_CHIP_5709@GOTPAGEOFF]
	ldr	x8, [x25]
	cmp	x0, x8
	b.ne	LBB0_19
; %bb.11:
	mov	x0, x20
	bl	_pci_is_pcie
	cbz	w0, LBB0_40
; %bb.12:
Lloh44:
	adrp	x8, _BNX2_FLAG_PCIE@GOTPAGE
Lloh45:
	ldr	x8, [x8, _BNX2_FLAG_PCIE@GOTPAGEOFF]
Lloh46:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
	mov	x0, x19
	bl	_BNX2_CHIP_REV
Lloh47:
	adrp	x8, _BNX2_CHIP_REV_Ax@GOTPAGE
Lloh48:
	ldr	x8, [x8, _BNX2_CHIP_REV_Ax@GOTPAGEOFF]
Lloh49:
	ldr	x8, [x8]
	cmp	x0, x8
	b.ne	LBB0_14
; %bb.13:
Lloh50:
	adrp	x8, _BNX2_FLAG_JUMBO_BROKEN@GOTPAGE
Lloh51:
	ldr	x8, [x8, _BNX2_FLAG_JUMBO_BROKEN@GOTPAGEOFF]
Lloh52:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_14:
	mov	x0, x20
	bl	_pci_enable_pcie_error_reporting
	cbnz	w0, LBB0_22
; %bb.15:
Lloh53:
	adrp	x8, _BNX2_FLAG_AER_ENABLED@GOTPAGE
Lloh54:
	ldr	x8, [x8, _BNX2_FLAG_AER_ENABLED@GOTPAGEOFF]
	b	LBB0_21
LBB0_16:
Lloh55:
	adrp	x1, l_.str.3@PAGE
Lloh56:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x0, x22
	bl	_dev_err
Lloh57:
	adrp	x8, _EIO@GOTPAGE
Lloh58:
	ldr	x8, [x8, _EIO@GOTPAGEOFF]
	b	LBB0_18
LBB0_17:
Lloh59:
	adrp	x1, l_.str.4@PAGE
Lloh60:
	add	x1, x1, l_.str.4@PAGEOFF
	mov	x0, x22
	bl	_dev_err
Lloh61:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh62:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
LBB0_18:
	ldr	w8, [x8]
	neg	w23, w8
	b	LBB0_59
LBB0_19:
Lloh63:
	adrp	x8, _PCI_CAP_ID_PCIX@GOTPAGE
Lloh64:
	ldr	x8, [x8, _PCI_CAP_ID_PCIX@GOTPAGEOFF]
Lloh65:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_pci_find_capability
	str	x0, [x19, #24]
	cbz	x0, LBB0_41
; %bb.20:
Lloh66:
	adrp	x8, _BNX2_FLAG_BROKEN_STATS@GOTPAGE
Lloh67:
	ldr	x8, [x8, _BNX2_FLAG_BROKEN_STATS@GOTPAGEOFF]
LBB0_21:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_22:
	mov	x0, x19
	bl	_BNX2_CHIP
	ldr	x8, [x25]
	cmp	x0, x8
	b.ne	LBB0_26
; %bb.23:
	mov	x0, x19
	bl	_BNX2_CHIP_REV
Lloh68:
	adrp	x8, _BNX2_CHIP_REV_Ax@GOTPAGE
Lloh69:
	ldr	x8, [x8, _BNX2_CHIP_REV_Ax@GOTPAGEOFF]
Lloh70:
	ldr	x8, [x8]
	cmp	x0, x8
	b.eq	LBB0_26
; %bb.24:
	ldr	x8, [x20, #40]
	cbz	x8, LBB0_26
; %bb.25:
Lloh71:
	adrp	x8, _BNX2_FLAG_MSIX_CAP@GOTPAGE
Lloh72:
	ldr	x8, [x8, _BNX2_FLAG_MSIX_CAP@GOTPAGEOFF]
Lloh73:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_26:
	mov	x0, x19
	bl	_BNX2_CHIP_ID
Lloh74:
	adrp	x24, _BNX2_CHIP_ID_5706_A0@GOTPAGE
Lloh75:
	ldr	x24, [x24, _BNX2_CHIP_ID_5706_A0@GOTPAGEOFF]
	ldr	x8, [x24]
	cmp	x0, x8
	b.eq	LBB0_30
; %bb.27:
	mov	x0, x19
	bl	_BNX2_CHIP_ID
Lloh76:
	adrp	x8, _BNX2_CHIP_ID_5706_A1@GOTPAGE
Lloh77:
	ldr	x8, [x8, _BNX2_CHIP_ID_5706_A1@GOTPAGEOFF]
Lloh78:
	ldr	x8, [x8]
	cmp	x0, x8
	b.eq	LBB0_30
; %bb.28:
	ldr	x8, [x20, #32]
	cbz	x8, LBB0_30
; %bb.29:
Lloh79:
	adrp	x8, _BNX2_FLAG_MSI_CAP@GOTPAGE
Lloh80:
	ldr	x8, [x8, _BNX2_FLAG_MSI_CAP@GOTPAGEOFF]
Lloh81:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_30:
	mov	x0, x19
	bl	_BNX2_CHIP
Lloh82:
	adrp	x26, _BNX2_CHIP_5708@GOTPAGE
Lloh83:
	ldr	x26, [x26, _BNX2_CHIP_5708@GOTPAGEOFF]
	ldr	x8, [x26]
	cmp	x0, x8
	mov	w8, #64
	mov	w9, #40
	csel	w0, w9, w8, eq
	bl	_DMA_BIT_MASK
	mov	x23, x0
	mov	x0, x20
	mov	x1, x23
	bl	_pci_set_dma_mask
	cbz	x0, LBB0_33
; %bb.31:
	mov	w0, #32
	bl	_DMA_BIT_MASK
	mov	x1, x0
	mov	x0, x20
	bl	_pci_set_dma_mask
	mov	x23, x0
	cbz	w23, LBB0_36
; %bb.32:
Lloh84:
	adrp	x1, l_.str.8@PAGE
Lloh85:
	add	x1, x1, l_.str.8@PAGEOFF
	b	LBB0_35
LBB0_33:
Lloh86:
	adrp	x8, _NETIF_F_HIGHDMA@GOTPAGE
Lloh87:
	ldr	x8, [x8, _NETIF_F_HIGHDMA@GOTPAGEOFF]
Lloh88:
	ldr	w8, [x8]
	ldr	w9, [x21]
	orr	w8, w9, w8
	str	w8, [x21]
	mov	x0, x20
	mov	x1, x23
	bl	_pci_set_consistent_dma_mask
	cbz	w0, LBB0_36
; %bb.34:
	mov	x23, x0
Lloh89:
	adrp	x1, l_.str.7@PAGE
Lloh90:
	add	x1, x1, l_.str.7@PAGEOFF
LBB0_35:
	mov	x0, x22
	bl	_dev_err
	b	LBB0_56
LBB0_36:
	ldr	w8, [x19]
Lloh91:
	adrp	x9, _BNX2_FLAG_PCIE@GOTPAGE
Lloh92:
	ldr	x9, [x9, _BNX2_FLAG_PCIE@GOTPAGEOFF]
Lloh93:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_38
; %bb.37:
	mov	x0, x19
	bl	_bnx2_get_pci_speed
LBB0_38:
	mov	x0, x19
	bl	_BNX2_CHIP_ID
	ldr	x8, [x24]
	cmp	x0, x8
	b.ne	LBB0_43
; %bb.39:
Lloh94:
	adrp	x23, _PCI_COMMAND@GOTPAGE
Lloh95:
	ldr	x23, [x23, _PCI_COMMAND@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x19
	bl	_BNX2_RD
	str	w0, [sp, #12]
Lloh96:
	adrp	x8, _PCI_COMMAND_SERR@GOTPAGE
Lloh97:
	ldr	x8, [x8, _PCI_COMMAND_SERR@GOTPAGEOFF]
Lloh98:
	ldr	w8, [x8]
Lloh99:
	adrp	x9, _PCI_COMMAND_PARITY@GOTPAGE
Lloh100:
	ldr	x9, [x9, _PCI_COMMAND_PARITY@GOTPAGEOFF]
Lloh101:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w2, w0, w8
	ldr	w1, [x23]
	mov	x0, x19
	bl	_BNX2_WR
	b	LBB0_45
LBB0_40:
Lloh102:
	adrp	x1, l_.str.5@PAGE
Lloh103:
	add	x1, x1, l_.str.5@PAGEOFF
	b	LBB0_42
LBB0_41:
Lloh104:
	adrp	x1, l_.str.6@PAGE
Lloh105:
	add	x1, x1, l_.str.6@PAGEOFF
LBB0_42:
	mov	x0, x22
	bl	_dev_err
Lloh106:
	adrp	x8, _EIO@GOTPAGE
Lloh107:
	ldr	x8, [x8, _EIO@GOTPAGEOFF]
	b	LBB0_55
LBB0_43:
	mov	x0, x19
	bl	_BNX2_CHIP_ID
Lloh108:
	adrp	x8, _BNX2_CHIP_ID_5706_A1@GOTPAGE
Lloh109:
	ldr	x8, [x8, _BNX2_CHIP_ID_5706_A1@GOTPAGEOFF]
Lloh110:
	ldr	x8, [x8]
	cmp	x0, x8
	b.ne	LBB0_45
; %bb.44:
	ldr	w8, [x19]
Lloh111:
	adrp	x9, _BNX2_FLAG_PCIX@GOTPAGE
Lloh112:
	ldr	x9, [x9, _BNX2_FLAG_PCIX@GOTPAGEOFF]
Lloh113:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_68
LBB0_45:
	mov	x0, x19
	bl	_bnx2_init_nvram
Lloh114:
	adrp	x8, _BNX2_SHM_HDR_SIGNATURE@GOTPAGE
Lloh115:
	ldr	x8, [x8, _BNX2_SHM_HDR_SIGNATURE@GOTPAGEOFF]
Lloh116:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_bnx2_reg_rd_ind
	mov	x23, x0
Lloh117:
	adrp	x8, _BNX2_MCP_TOE_ID@GOTPAGE
Lloh118:
	ldr	x8, [x8, _BNX2_MCP_TOE_ID@GOTPAGEOFF]
Lloh119:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_bnx2_reg_rd_ind
Lloh120:
	adrp	x8, _BNX2_MCP_TOE_ID_FUNCTION_ID@GOTPAGE
Lloh121:
	ldr	x8, [x8, _BNX2_MCP_TOE_ID_FUNCTION_ID@GOTPAGEOFF]
Lloh122:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_47
; %bb.46:
	mov	w8, #1
	str	w8, [x19, #32]
LBB0_47:
Lloh123:
	adrp	x8, _BNX2_SHM_HDR_SIGNATURE_SIG_MASK@GOTPAGE
Lloh124:
	ldr	x8, [x8, _BNX2_SHM_HDR_SIGNATURE_SIG_MASK@GOTPAGEOFF]
Lloh125:
	ldr	w8, [x8]
	and	w8, w8, w23
Lloh126:
	adrp	x9, _BNX2_SHM_HDR_SIGNATURE_SIG@GOTPAGE
Lloh127:
	ldr	x9, [x9, _BNX2_SHM_HDR_SIGNATURE_SIG@GOTPAGEOFF]
Lloh128:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_49
; %bb.48:
	ldr	w8, [x19, #32]
Lloh129:
	adrp	x9, _BNX2_SHM_HDR_ADDR_0@GOTPAGE
Lloh130:
	ldr	x9, [x9, _BNX2_SHM_HDR_ADDR_0@GOTPAGEOFF]
Lloh131:
	ldr	w9, [x9]
	add	w1, w9, w8, lsl #2
	mov	x0, x19
	bl	_bnx2_reg_rd_ind
	b	LBB0_50
LBB0_49:
Lloh132:
	adrp	x8, _HOST_VIEW_SHMEM_BASE@GOTPAGE
Lloh133:
	ldr	x8, [x8, _HOST_VIEW_SHMEM_BASE@GOTPAGEOFF]
Lloh134:
	ldr	w0, [x8]
LBB0_50:
	str	w0, [x19, #36]
Lloh135:
	adrp	x8, _BNX2_DEV_INFO_SIGNATURE@GOTPAGE
Lloh136:
	ldr	x8, [x8, _BNX2_DEV_INFO_SIGNATURE@GOTPAGEOFF]
Lloh137:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_bnx2_shmem_rd
	str	w0, [sp, #12]
Lloh138:
	adrp	x8, _BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK@GOTPAGE
Lloh139:
	ldr	x8, [x8, _BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK@GOTPAGEOFF]
Lloh140:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh141:
	adrp	x9, _BNX2_DEV_INFO_SIGNATURE_MAGIC@GOTPAGE
Lloh142:
	ldr	x9, [x9, _BNX2_DEV_INFO_SIGNATURE_MAGIC@GOTPAGEOFF]
Lloh143:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_54
; %bb.51:
	mov	x0, x19
	bl	_bnx2_read_vpd_fw_ver
	ldr	x0, [x19, #40]
	bl	_strlen
	mov	x22, x0
Lloh144:
	adrp	x8, _BNX2_DEV_INFO_BC_REV@GOTPAGE
Lloh145:
	ldr	x8, [x8, _BNX2_DEV_INFO_BC_REV@GOTPAGEOFF]
Lloh146:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_bnx2_shmem_rd
	str	w0, [sp, #12]
	cmp	w22, #23
	b.gt	LBB0_78
; %bb.52:
	ldr	x8, [x19, #40]
	mov	x9, x22
	sxtw	x9, w9
	mov	w10, #98
	strb	w10, [x8, x9]
	ldr	x8, [x19, #40]
	add	x8, x9, x8
	mov	w10, #99
	strb	w10, [x8, #1]
	ldr	x8, [x19, #40]
	add	x10, x9, x8
	add	x8, x9, #3
	mov	w9, #32
	strb	w9, [x10, #2]
	ldr	w9, [sp, #12]
	mov	w10, #1677721600
	cmp	w9, w10
	b.lt	LBB0_63
; %bb.53:
	asr	w10, w9, #24
	mov	w11, #41
	mul	w10, w10, w11
	ubfx	w11, w10, #15, #1
	add	w10, w11, w10, asr #12
	add	w11, w10, #48
	ldr	x12, [x19, #40]
	strb	w11, [x12, x8]
	lsr	w8, w9, #24
	add	w9, w22, #4
	mov	w11, #100
	msub	w8, w10, w11, w8
	sxtb	w10, w8
	mov	x8, x9
	b	LBB0_64
LBB0_54:
Lloh147:
	adrp	x1, l_.str.10@PAGE
Lloh148:
	add	x1, x1, l_.str.10@PAGEOFF
	mov	x0, x22
	bl	_dev_err
Lloh149:
	adrp	x8, _ENODEV@GOTPAGE
Lloh150:
	ldr	x8, [x8, _ENODEV@GOTPAGEOFF]
LBB0_55:
	ldr	w8, [x8]
	neg	w23, w8
LBB0_56:
	ldr	w8, [x19]
Lloh151:
	adrp	x21, _BNX2_FLAG_AER_ENABLED@GOTPAGE
Lloh152:
	ldr	x21, [x21, _BNX2_FLAG_AER_ENABLED@GOTPAGEOFF]
	ldr	w9, [x21]
	tst	w9, w8
	b.eq	LBB0_58
; %bb.57:
	mov	x0, x20
	bl	_pci_disable_pcie_error_reporting
	ldr	w8, [x21]
	ldr	w9, [x19]
	bic	w8, w9, w8
	str	w8, [x19]
LBB0_58:
	ldr	x1, [x19, #112]
	mov	x0, x20
	bl	_pci_iounmap
	str	xzr, [x19, #112]
LBB0_59:
	mov	x0, x20
	bl	_pci_release_regions
LBB0_60:
	mov	x0, x20
	bl	_pci_disable_device
LBB0_61:
	ldr	w0, [x19, #108]
	bl	_kfree
LBB0_62:
	mov	x0, x23
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
LBB0_63:
	lsr	w10, w9, #24
	asr	w9, w9, #24
	mov	w11, #41
	mul	w9, w9, w11
	ubfx	w11, w9, #15, #1
	add	w9, w11, w9, lsr #12
	mov	w11, #100
	msub	w9, w9, w11, w10
	sxtb	w10, w9
	mov	x9, x8
	cmp	w10, #10
	b.lt	LBB0_65
LBB0_64:
	mov	w9, #103
	mul	w9, w10, w9
	ubfx	w11, w9, #15, #1
	add	w9, w11, w9, lsr #10
	add	w11, w9, #48
	ldr	x12, [x19, #40]
	add	w9, w8, #1
	strb	w11, [x12, w8, sxtw]
LBB0_65:
	mov	w8, #103
	mul	w8, w10, w8
	ubfx	w11, w8, #15, #1
	add	w8, w11, w8, lsr #10
	mov	w11, #10
	msub	w8, w8, w11, w10
	add	w8, w8, #48
	ldr	x10, [x19, #40]
	sxtw	x11, w9
	strb	w8, [x10, x11]
	ldr	x8, [x19, #40]
	add	x8, x11, x8
	add	x22, x11, #2
	mov	w10, #46
	strb	w10, [x8, #1]
	cmp	w9, #21
	b.gt	LBB0_78
; %bb.66:
	ldr	w10, [sp, #12]
	asr	w8, w10, #16
	cmp	w10, #1600, lsl #12             ; =6553600
	b.lt	LBB0_69
; %bb.67:
	mov	w10, #34079
	movk	w10, #20971, lsl #16
	umull	x10, w8, w10
	lsr	x10, x10, #37
	add	w11, w10, #48
	ldr	x12, [x19, #40]
	strb	w11, [x12, x22]
	add	w9, w9, #3
	mov	w11, #100
	msub	w8, w10, w11, w8
	mov	x22, x9
	b	LBB0_70
LBB0_68:
Lloh153:
	adrp	x1, l_.str.9@PAGE
Lloh154:
	add	x1, x1, l_.str.9@PAGEOFF
	mov	x0, x22
	bl	_dev_err
	mov	w23, #0
	b	LBB0_56
LBB0_69:
	mov	w9, #34079
	movk	w9, #20971, lsl #16
	smull	x9, w8, w9
	lsr	x10, x9, #63
	asr	x9, x9, #37
	add	w9, w9, w10
	mov	w10, #100
	msub	w8, w9, w10, w8
	cmp	w8, #10
	b.lt	LBB0_71
LBB0_70:
	sxtb	w9, w8
	mov	w10, #103
	mul	w9, w9, w10
	ubfx	w10, w9, #15, #1
	add	w9, w10, w9, lsr #10
	add	w9, w9, #48
	ldr	x10, [x19, #40]
	strb	w9, [x10, w22, sxtw]
	add	w9, w22, #1
	mov	x22, x9
LBB0_71:
	sxtb	w9, w8
	mov	w10, #103
	mul	w9, w9, w10
	ubfx	w10, w9, #15, #1
	add	w9, w10, w9, lsr #10
	mov	w10, #10
	msub	w8, w9, w10, w8
	add	w8, w8, #48
	ldr	x9, [x19, #40]
	mov	x10, x22
	sxtw	x10, w10
	strb	w8, [x9, x10]
	ldr	x8, [x19, #40]
	add	x9, x10, x8
	add	x8, x10, #2
	mov	w10, #46
	strb	w10, [x9, #1]
	cmp	w22, #21
	b.gt	LBB0_74
; %bb.72:
	ldr	w10, [sp, #12]
	asr	w9, w10, #8
	mov	w11, #25599
	cmp	w10, w11
	b.le	LBB0_75
; %bb.73:
	mov	w10, #34079
	movk	w10, #20971, lsl #16
	umull	x10, w9, w10
	lsr	x10, x10, #37
	add	w11, w10, #48
	ldr	x12, [x19, #40]
	strb	w11, [x12, x8]
	add	w8, w22, #3
	mov	w11, #100
	msub	w9, w10, w11, w9
                                        ; kill: def $w8 killed $w8 def $x8
	b	LBB0_76
LBB0_74:
	mov	x22, x8
	b	LBB0_78
LBB0_75:
	mov	w10, #34079
	movk	w10, #20971, lsl #16
	smull	x10, w9, w10
	lsr	x11, x10, #63
	asr	x10, x10, #37
	add	w10, w10, w11
	mov	w11, #100
	msub	w9, w10, w11, w9
	cmp	w9, #9
	b.le	LBB0_77
LBB0_76:
	sxtb	w10, w9
	mov	w11, #103
	mul	w10, w10, w11
	ubfx	w11, w10, #15, #1
	add	w10, w11, w10, lsr #10
	add	w10, w10, #48
	ldr	x11, [x19, #40]
	strb	w10, [x11, w8, sxtw]
	add	w8, w8, #1
                                        ; kill: def $w8 killed $w8 def $x8
LBB0_77:
	sxtb	w10, w9
	mov	w11, #103
	mul	w10, w10, w11
	ubfx	w11, w10, #15, #1
	add	w10, w11, w10, lsr #10
	mov	w11, #10
	msub	w9, w10, w11, w9
	add	w9, w9, #48
	ldr	x10, [x19, #40]
	add	w22, w8, #1
	strb	w9, [x10, w8, sxtw]
LBB0_78:
Lloh155:
	adrp	x8, _BNX2_PORT_FEATURE@GOTPAGE
Lloh156:
	ldr	x8, [x8, _BNX2_PORT_FEATURE@GOTPAGEOFF]
Lloh157:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_bnx2_shmem_rd
Lloh158:
	adrp	x8, _BNX2_PORT_FEATURE_WOL_ENABLED@GOTPAGE
Lloh159:
	ldr	x8, [x8, _BNX2_PORT_FEATURE_WOL_ENABLED@GOTPAGEOFF]
Lloh160:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_80
; %bb.79:
	mov	w8, #1
	str	w8, [x19, #48]
LBB0_80:
Lloh161:
	adrp	x8, _BNX2_PORT_FEATURE_ASF_ENABLED@GOTPAGE
Lloh162:
	ldr	x8, [x8, _BNX2_PORT_FEATURE_ASF_ENABLED@GOTPAGEOFF]
Lloh163:
	ldr	w8, [x8]
Lloh164:
	adrp	x27, _BNX2_BC_STATE_CONDITION@GOTPAGE
Lloh165:
	ldr	x27, [x27, _BNX2_BC_STATE_CONDITION@GOTPAGEOFF]
Lloh166:
	adrp	x23, _BNX2_CONDITION_MFW_RUN_MASK@GOTPAGE
Lloh167:
	ldr	x23, [x23, _BNX2_CONDITION_MFW_RUN_MASK@GOTPAGEOFF]
	tst	w8, w0
	b.eq	LBB0_84
; %bb.81:
Lloh168:
	adrp	x8, _BNX2_FLAG_ASF_ENABLE@GOTPAGE
Lloh169:
	ldr	x8, [x8, _BNX2_FLAG_ASF_ENABLE@GOTPAGEOFF]
Lloh170:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
	mov	w28, #30
LBB0_82:                                ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x27]
	mov	x0, x19
	bl	_bnx2_shmem_rd
	ldr	w8, [x23]
	tst	w8, w0
	b.ne	LBB0_84
; %bb.83:                               ;   in Loop: Header=BB0_82 Depth=1
	mov	w0, #10
	bl	_msleep
	subs	w28, w28, #1
	b.ne	LBB0_82
LBB0_84:
	ldr	w1, [x27]
	mov	x0, x19
	bl	_bnx2_shmem_rd
	ldr	w8, [x23]
	and	w8, w8, w0
	str	w8, [sp, #12]
Lloh171:
	adrp	x9, _BNX2_CONDITION_MFW_RUN_UNKNOWN@GOTPAGE
Lloh172:
	ldr	x9, [x9, _BNX2_CONDITION_MFW_RUN_UNKNOWN@GOTPAGEOFF]
Lloh173:
	ldr	w9, [x9]
Lloh174:
	adrp	x10, _BNX2_CONDITION_MFW_RUN_NONE@GOTPAGE
Lloh175:
	ldr	x10, [x10, _BNX2_CONDITION_MFW_RUN_NONE@GOTPAGEOFF]
Lloh176:
	ldr	w10, [x10]
	cmp	w8, w9
	ccmp	w8, w10, #4, ne
	b.eq	LBB0_90
; %bb.85:
Lloh177:
	adrp	x8, _BNX2_MFW_VER_PTR@GOTPAGE
Lloh178:
	ldr	x8, [x8, _BNX2_MFW_VER_PTR@GOTPAGEOFF]
Lloh179:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_bnx2_shmem_rd
	cmp	w22, #31
	b.gt	LBB0_90
; %bb.86:
	ldr	x9, [x19, #40]
	mov	x8, x22
	sxtw	x8, w8
	mov	w10, #32
	strb	w10, [x9, x8]
	cmp	w22, #26
	b.gt	LBB0_90
; %bb.87:
	mov	x23, x0
	add	x27, x8, #1
	mov	x0, x19
	mov	x1, x23
	bl	_bnx2_reg_rd_ind
	str	w0, [sp, #12]
	bl	_be32_to_cpu
	str	w0, [sp, #12]
	ldr	x8, [x19, #40]
	add	x0, x8, x27
	add	x1, sp, #12
	mov	w2, #4
	bl	_memcpy
	cmp	w22, #22
	b.gt	LBB0_90
; %bb.88:
	add	w1, w23, #4
	mov	x0, x19
	bl	_bnx2_reg_rd_ind
	str	w0, [sp, #12]
	bl	_be32_to_cpu
	ldr	x8, [x19, #40]
	add	x8, x27, x8
	str	w0, [sp, #12]
	add	x0, x8, #4
	add	x1, sp, #12
	mov	w2, #4
	bl	_memcpy
	cmp	w22, #18
	b.gt	LBB0_90
; %bb.89:
	add	w1, w23, #8
	mov	x0, x19
	bl	_bnx2_reg_rd_ind
	str	w0, [sp, #12]
	bl	_be32_to_cpu
	ldr	x8, [x19, #40]
	add	x8, x27, x8
	str	w0, [sp, #12]
	add	x0, x8, #8
	add	x1, sp, #12
	mov	w2, #4
	bl	_memcpy
LBB0_90:
Lloh180:
	adrp	x8, _BNX2_PORT_HW_CFG_MAC_UPPER@GOTPAGE
Lloh181:
	ldr	x8, [x8, _BNX2_PORT_HW_CFG_MAC_UPPER@GOTPAGEOFF]
Lloh182:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_bnx2_shmem_rd
	str	w0, [sp, #12]
	asr	w8, w0, #8
	ldr	x9, [x19, #56]
	str	w8, [x9]
	ldr	w8, [sp, #12]
	str	w8, [x9, #4]
Lloh183:
	adrp	x8, _BNX2_PORT_HW_CFG_MAC_LOWER@GOTPAGE
Lloh184:
	ldr	x8, [x8, _BNX2_PORT_HW_CFG_MAC_LOWER@GOTPAGEOFF]
Lloh185:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_bnx2_shmem_rd
	str	w0, [sp, #12]
	dup.2s	v0, w0
	ldr	x8, [x19, #56]
Lloh186:
	adrp	x9, lCPI0_0@PAGE
Lloh187:
	ldr	d1, [x9, lCPI0_0@PAGEOFF]
	sshl.2s	v0, v0, v1
	str	d0, [x8, #8]
	asr	w9, w0, #8
	stp	w9, w0, [x8, #16]
Lloh188:
	adrp	x8, _BNX2_MAX_TX_DESC_CNT@GOTPAGE
Lloh189:
	ldr	x8, [x8, _BNX2_MAX_TX_DESC_CNT@GOTPAGEOFF]
Lloh190:
	ldr	w8, [x8]
	str	w8, [x19, #176]
	mov	x0, x19
	mov	w1, #255
	bl	_bnx2_set_rx_ring_size
Lloh191:
	adrp	x8, lCPI0_1@PAGE
Lloh192:
	ldr	q0, [x8, lCPI0_1@PAGEOFF]
Lloh193:
	adrp	x8, lCPI0_2@PAGE
Lloh194:
	ldr	q1, [x8, lCPI0_2@PAGEOFF]
	stp	q0, q1, [x19, #64]
Lloh195:
	adrp	x8, _USEC_PER_SEC@GOTPAGE
Lloh196:
	ldr	x8, [x8, _USEC_PER_SEC@GOTPAGEOFF]
Lloh197:
	ldr	w8, [x8]
Lloh198:
	adrp	x9, _BNX2_HC_STATS_TICKS_HC_STAT_TICKS@GOTPAGE
Lloh199:
	ldr	x9, [x9, _BNX2_HC_STATS_TICKS_HC_STAT_TICKS@GOTPAGEOFF]
Lloh200:
	ldr	w9, [x9]
Lloh201:
	adrp	x22, _BNX2_TIMER_INTERVAL@GOTPAGE
Lloh202:
	ldr	x22, [x22, _BNX2_TIMER_INTERVAL@GOTPAGEOFF]
	and	w8, w9, w8
	ldr	w9, [x22]
	str	w9, [x19, #172]
	mov	w9, #1
	stp	w8, w9, [x19, #96]
	mov	x0, x21
	bl	_bnx2_alloc_stats_blk
	mov	x23, x0
	cbnz	w0, LBB0_56
; %bb.91:
	mov	x0, x19
	bl	_BNX2_CHIP
	ldr	x8, [x25]
Lloh203:
	adrp	x21, _BNX2_PHY_FLAG_SERDES@GOTPAGE
Lloh204:
	ldr	x21, [x21, _BNX2_PHY_FLAG_SERDES@GOTPAGEOFF]
	cmp	x0, x8
	b.ne	LBB0_93
; %bb.92:
	mov	x0, x19
	bl	_bnx2_get_5709_media
	b	LBB0_95
LBB0_93:
	mov	x0, x19
	bl	_BNX2_CHIP_BOND
Lloh205:
	adrp	x8, _BNX2_CHIP_BOND_SERDES_BIT@GOTPAGE
Lloh206:
	ldr	x8, [x8, _BNX2_CHIP_BOND_SERDES_BIT@GOTPAGEOFF]
Lloh207:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_95
; %bb.94:
	ldr	w8, [x21]
	ldr	w9, [x19, #4]
	orr	w8, w9, w8
	str	w8, [x19, #4]
LBB0_95:
Lloh208:
	adrp	x8, _PORT_TP@GOTPAGE
Lloh209:
	ldr	x8, [x8, _PORT_TP@GOTPAGEOFF]
Lloh210:
	ldr	w8, [x8]
	str	w8, [x19, #168]
	ldr	w8, [x19, #4]
	ldr	w9, [x21]
Lloh211:
	adrp	x23, _BNX2_FLAG_NO_WOL@GOTPAGE
Lloh212:
	ldr	x23, [x23, _BNX2_FLAG_NO_WOL@GOTPAGEOFF]
Lloh213:
	adrp	x21, _BNX2_CHIP_5706@GOTPAGE
Lloh214:
	ldr	x21, [x21, _BNX2_CHIP_5706@GOTPAGEOFF]
	tst	w9, w8
	b.eq	LBB0_102
; %bb.96:
Lloh215:
	adrp	x8, _PORT_FIBRE@GOTPAGE
Lloh216:
	ldr	x8, [x8, _PORT_FIBRE@GOTPAGEOFF]
Lloh217:
	ldr	w8, [x8]
	str	w8, [x19, #168]
Lloh218:
	adrp	x8, _BNX2_SHARED_HW_CFG_CONFIG@GOTPAGE
Lloh219:
	ldr	x8, [x8, _BNX2_SHARED_HW_CFG_CONFIG@GOTPAGEOFF]
Lloh220:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_bnx2_shmem_rd
	str	w0, [sp, #12]
Lloh221:
	adrp	x8, _BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX@GOTPAGE
Lloh222:
	ldr	x8, [x8, _BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX@GOTPAGEOFF]
Lloh223:
	ldr	w8, [x8]
	tst	w8, w0
	b.ne	LBB0_98
; %bb.97:
	ldr	w8, [x23]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
	str	wzr, [x19, #48]
LBB0_98:
	mov	x0, x19
	bl	_BNX2_CHIP
	ldr	x8, [x21]
	cmp	x0, x8
	b.ne	LBB0_105
; %bb.99:
	ldr	x8, [x20, #8]
Lloh224:
	adrp	x9, _PCI_VENDOR_ID_HP@GOTPAGE
Lloh225:
	ldr	x9, [x9, _PCI_VENDOR_ID_HP@GOTPAGEOFF]
Lloh226:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_108
; %bb.100:
	ldr	w8, [x20, #16]
	mov	w9, #12556
	cmp	w8, w9
	b.ne	LBB0_108
; %bb.101:
Lloh227:
	adrp	x8, _BNX2_PHY_FLAG_NO_PARALLEL@GOTPAGE
Lloh228:
	ldr	x8, [x8, _BNX2_PHY_FLAG_NO_PARALLEL@GOTPAGEOFF]
	b	LBB0_107
LBB0_102:
	mov	x0, x19
	bl	_BNX2_CHIP
	ldr	x8, [x21]
	cmp	x0, x8
	b.eq	LBB0_104
; %bb.103:
	mov	x0, x19
	bl	_BNX2_CHIP
	ldr	x8, [x26]
	cmp	x0, x8
	b.ne	LBB0_126
LBB0_104:
Lloh229:
	adrp	x8, _BNX2_PHY_FLAG_CRC_FIX@GOTPAGE
Lloh230:
	ldr	x8, [x8, _BNX2_PHY_FLAG_CRC_FIX@GOTPAGEOFF]
	b	LBB0_107
LBB0_105:
	mov	w8, #2
	str	w8, [x19, #100]
	ldr	w8, [sp, #12]
Lloh231:
	adrp	x9, _BNX2_SHARED_HW_CFG_PHY_2_5G@GOTPAGE
Lloh232:
	ldr	x9, [x9, _BNX2_SHARED_HW_CFG_PHY_2_5G@GOTPAGEOFF]
Lloh233:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_108
; %bb.106:
Lloh234:
	adrp	x8, _BNX2_PHY_FLAG_2_5G_CAPABLE@GOTPAGE
Lloh235:
	ldr	x8, [x8, _BNX2_PHY_FLAG_2_5G_CAPABLE@GOTPAGEOFF]
LBB0_107:
	ldr	w8, [x8]
	ldr	w9, [x19, #4]
	orr	w8, w9, w8
	str	w8, [x19, #4]
LBB0_108:
	mov	x0, x19
	bl	_bnx2_init_fw_cap
	mov	x0, x19
	bl	_BNX2_CHIP_ID
Lloh236:
	adrp	x8, _BNX2_CHIP_ID_5708_A0@GOTPAGE
Lloh237:
	ldr	x8, [x8, _BNX2_CHIP_ID_5708_A0@GOTPAGEOFF]
Lloh238:
	ldr	x8, [x8]
	cmp	x0, x8
	b.eq	LBB0_113
; %bb.109:
	mov	x0, x19
	bl	_BNX2_CHIP_ID
Lloh239:
	adrp	x8, _BNX2_CHIP_ID_5708_B0@GOTPAGE
Lloh240:
	ldr	x8, [x8, _BNX2_CHIP_ID_5708_B0@GOTPAGEOFF]
Lloh241:
	ldr	x8, [x8]
	cmp	x0, x8
	b.eq	LBB0_113
; %bb.110:
	mov	x0, x19
	bl	_BNX2_CHIP_ID
Lloh242:
	adrp	x8, _BNX2_CHIP_ID_5708_B1@GOTPAGE
Lloh243:
	ldr	x8, [x8, _BNX2_CHIP_ID_5708_B1@GOTPAGEOFF]
Lloh244:
	ldr	x8, [x8]
	cmp	x0, x8
	b.eq	LBB0_113
; %bb.111:
Lloh245:
	adrp	x8, _BNX2_PCI_CONFIG_3@GOTPAGE
Lloh246:
	ldr	x8, [x8, _BNX2_PCI_CONFIG_3@GOTPAGEOFF]
Lloh247:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_BNX2_RD
Lloh248:
	adrp	x8, _BNX2_PCI_CONFIG_3_VAUX_PRESET@GOTPAGE
Lloh249:
	ldr	x8, [x8, _BNX2_PCI_CONFIG_3_VAUX_PRESET@GOTPAGEOFF]
Lloh250:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_113
; %bb.112:
	ldr	w8, [x19]
	b	LBB0_114
LBB0_113:
	ldr	w8, [x23]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
	str	wzr, [x19, #48]
LBB0_114:
	ldr	w9, [x23]
	ldr	x10, [x19, #160]
	add	x0, x10, #24
	tst	w9, w8
	b.eq	LBB0_116
; %bb.115:
	mov	w1, #0
	bl	_device_set_wakeup_capable
	b	LBB0_117
LBB0_116:
	ldr	w1, [x19, #48]
	bl	_device_set_wakeup_enable
LBB0_117:
	mov	x0, x19
	bl	_BNX2_CHIP_ID
	ldr	x8, [x24]
	cmp	x0, x8
	b.ne	LBB0_119
; %bb.118:
	ldr	w8, [x19, #68]
	str	w8, [x19, #64]
	ldr	w8, [x19, #76]
	str	w8, [x19, #72]
	ldr	w8, [x19, #84]
	str	w8, [x19, #80]
	ldr	w8, [x19, #92]
	str	w8, [x19, #88]
	ldr	w8, [x19, #148]
	str	w8, [x19, #152]
	ldr	w8, [x19, #140]
	str	w8, [x19, #144]
	ldr	w8, [x19, #132]
	str	w8, [x19, #136]
LBB0_119:
	mov	x0, x19
	bl	_BNX2_CHIP
	ldr	x8, [x21]
	cmp	x0, x8
	b.ne	LBB0_125
; %bb.120:
Lloh251:
	adrp	x21, _disable_msi@GOTPAGE
Lloh252:
	ldr	x21, [x21, _disable_msi@GOTPAGEOFF]
	ldr	w8, [x21]
	cbnz	w8, LBB0_125
; %bb.121:
	mov	x2, #0
Lloh253:
	adrp	x23, _PCI_VENDOR_ID_AMD@GOTPAGE
Lloh254:
	ldr	x23, [x23, _PCI_VENDOR_ID_AMD@GOTPAGEOFF]
Lloh255:
	adrp	x24, _PCI_DEVICE_ID_AMD_8132_BRIDGE@GOTPAGE
Lloh256:
	ldr	x24, [x24, _PCI_DEVICE_ID_AMD_8132_BRIDGE@GOTPAGEOFF]
LBB0_122:                               ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x23]
	ldr	w1, [x24]
	bl	_pci_get_device
	cbz	x0, LBB0_125
; %bb.123:                              ;   in Loop: Header=BB0_122 Depth=1
	mov	x2, x0
	ldr	w8, [x0, #20]
	and	w8, w8, #0xfffffffc
	cmp	w8, #16
	b.ne	LBB0_122
; %bb.124:
	mov	w8, #1
	str	w8, [x21]
	mov	x0, x2
	bl	_pci_dev_put
LBB0_125:
	mov	x0, x19
	bl	_bnx2_set_default_link
Lloh257:
	adrp	x8, _FLOW_CTRL_RX@GOTPAGE
Lloh258:
	ldr	x8, [x8, _FLOW_CTRL_RX@GOTPAGEOFF]
Lloh259:
	ldr	w8, [x8]
Lloh260:
	adrp	x9, _FLOW_CTRL_TX@GOTPAGE
Lloh261:
	ldr	x9, [x9, _FLOW_CTRL_TX@GOTPAGEOFF]
Lloh262:
	ldr	w9, [x9]
	orr	w8, w9, w8
	str	w8, [x19, #104]
	add	x0, x19, #128
Lloh263:
	adrp	x8, _bnx2_timer@GOTPAGE
Lloh264:
	ldr	x8, [x8, _bnx2_timer@GOTPAGEOFF]
Lloh265:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_timer_setup
	ldr	w0, [x22]
	bl	_RUN_AT
	str	w0, [x19, #128]
	mov	x0, x20
	bl	_pci_save_state
	mov	w23, #0
	b	LBB0_62
LBB0_126:
	mov	x0, x19
	bl	_BNX2_CHIP
	ldr	x8, [x25]
	cmp	x0, x8
	b.ne	LBB0_108
; %bb.127:
	mov	x0, x19
	bl	_BNX2_CHIP_REV
Lloh266:
	adrp	x8, _BNX2_CHIP_REV_Ax@GOTPAGE
Lloh267:
	ldr	x8, [x8, _BNX2_CHIP_REV_Ax@GOTPAGEOFF]
Lloh268:
	ldr	x8, [x8]
	cmp	x0, x8
	b.eq	LBB0_129
; %bb.128:
	mov	x0, x19
	bl	_BNX2_CHIP_REV
Lloh269:
	adrp	x8, _BNX2_CHIP_REV_Bx@GOTPAGE
Lloh270:
	ldr	x8, [x8, _BNX2_CHIP_REV_Bx@GOTPAGEOFF]
Lloh271:
	ldr	x8, [x8]
	cmp	x0, x8
	b.ne	LBB0_108
LBB0_129:
Lloh272:
	adrp	x8, _BNX2_PHY_FLAG_DIS_EARLY_DAC@GOTPAGE
Lloh273:
	ldr	x8, [x8, _BNX2_PHY_FLAG_DIS_EARLY_DAC@GOTPAGEOFF]
	b	LBB0_107
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpAdd	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpAdd	Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh34
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpAdd	Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpAdd	Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGot	Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGot	Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGot	Lloh82, Lloh83
	.loh AdrpAdd	Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpAdd	Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGot	Lloh94, Lloh95
	.loh AdrpAdd	Lloh102, Lloh103
	.loh AdrpAdd	Lloh104, Lloh105
	.loh AdrpLdrGot	Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh120, Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh126, Lloh127, Lloh128
	.loh AdrpLdrGotLdr	Lloh123, Lloh124, Lloh125
	.loh AdrpLdrGotLdr	Lloh129, Lloh130, Lloh131
	.loh AdrpLdrGotLdr	Lloh132, Lloh133, Lloh134
	.loh AdrpLdrGotLdr	Lloh141, Lloh142, Lloh143
	.loh AdrpLdrGotLdr	Lloh138, Lloh139, Lloh140
	.loh AdrpLdrGotLdr	Lloh135, Lloh136, Lloh137
	.loh AdrpLdrGotLdr	Lloh144, Lloh145, Lloh146
	.loh AdrpLdrGot	Lloh149, Lloh150
	.loh AdrpAdd	Lloh147, Lloh148
	.loh AdrpLdrGot	Lloh151, Lloh152
	.loh AdrpAdd	Lloh153, Lloh154
	.loh AdrpLdrGotLdr	Lloh158, Lloh159, Lloh160
	.loh AdrpLdrGotLdr	Lloh155, Lloh156, Lloh157
	.loh AdrpLdrGot	Lloh166, Lloh167
	.loh AdrpLdrGot	Lloh164, Lloh165
	.loh AdrpLdrGotLdr	Lloh161, Lloh162, Lloh163
	.loh AdrpLdrGotLdr	Lloh168, Lloh169, Lloh170
	.loh AdrpLdrGotLdr	Lloh174, Lloh175, Lloh176
	.loh AdrpLdrGotLdr	Lloh171, Lloh172, Lloh173
	.loh AdrpLdrGotLdr	Lloh177, Lloh178, Lloh179
	.loh AdrpLdrGot	Lloh201, Lloh202
	.loh AdrpLdrGotLdr	Lloh198, Lloh199, Lloh200
	.loh AdrpLdrGotLdr	Lloh195, Lloh196, Lloh197
	.loh AdrpAdrp	Lloh193, Lloh195
	.loh AdrpLdr	Lloh193, Lloh194
	.loh AdrpAdrp	Lloh191, Lloh193
	.loh AdrpLdr	Lloh191, Lloh192
	.loh AdrpLdrGotLdr	Lloh188, Lloh189, Lloh190
	.loh AdrpLdr	Lloh186, Lloh187
	.loh AdrpLdrGotLdr	Lloh183, Lloh184, Lloh185
	.loh AdrpLdrGotLdr	Lloh180, Lloh181, Lloh182
	.loh AdrpLdrGot	Lloh203, Lloh204
	.loh AdrpLdrGotLdr	Lloh205, Lloh206, Lloh207
	.loh AdrpLdrGot	Lloh213, Lloh214
	.loh AdrpLdrGot	Lloh211, Lloh212
	.loh AdrpLdrGotLdr	Lloh208, Lloh209, Lloh210
	.loh AdrpLdrGotLdr	Lloh221, Lloh222, Lloh223
	.loh AdrpLdrGotLdr	Lloh218, Lloh219, Lloh220
	.loh AdrpLdrGotLdr	Lloh215, Lloh216, Lloh217
	.loh AdrpLdrGotLdr	Lloh224, Lloh225, Lloh226
	.loh AdrpLdrGot	Lloh227, Lloh228
	.loh AdrpLdrGot	Lloh229, Lloh230
	.loh AdrpLdrGotLdr	Lloh231, Lloh232, Lloh233
	.loh AdrpLdrGot	Lloh234, Lloh235
	.loh AdrpLdrGotLdr	Lloh236, Lloh237, Lloh238
	.loh AdrpLdrGotLdr	Lloh239, Lloh240, Lloh241
	.loh AdrpLdrGotLdr	Lloh242, Lloh243, Lloh244
	.loh AdrpLdrGotLdr	Lloh248, Lloh249, Lloh250
	.loh AdrpLdrGotLdr	Lloh245, Lloh246, Lloh247
	.loh AdrpLdrGot	Lloh251, Lloh252
	.loh AdrpLdrGot	Lloh255, Lloh256
	.loh AdrpLdrGot	Lloh253, Lloh254
	.loh AdrpLdrGotLdr	Lloh263, Lloh264, Lloh265
	.loh AdrpLdrGotLdr	Lloh260, Lloh261, Lloh262
	.loh AdrpLdrGotLdr	Lloh257, Lloh258, Lloh259
	.loh AdrpLdrGotLdr	Lloh266, Lloh267, Lloh268
	.loh AdrpLdrGotLdr	Lloh269, Lloh270, Lloh271
	.loh AdrpLdrGot	Lloh272, Lloh273
	.cfi_endproc
                                        ; -- End function
	.comm	_GFP_KERNEL,4,2                 ; @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ; @ENOMEM
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Cannot enable PCI device, aborting\n"

	.comm	_IORESOURCE_MEM,4,2             ; @IORESOURCE_MEM
l_.str.1:                               ; @.str.1
	.asciz	"Cannot find PCI device base address, aborting\n"

	.comm	_ENODEV,4,2                     ; @ENODEV
	.comm	_DRV_MODULE_NAME,4,2            ; @DRV_MODULE_NAME
l_.str.2:                               ; @.str.2
	.asciz	"Cannot obtain PCI resources, aborting\n"

l_.str.3:                               ; @.str.3
	.asciz	"Cannot find power management capability, aborting\n"

	.comm	_EIO,4,2                        ; @EIO
	.comm	_bnx2_reset_task,4,2            ; @bnx2_reset_task
	.comm	_TX_TSS_CID,8,3                 ; @TX_TSS_CID
	.comm	_TX_MAX_TSS_RINGS,8,3           ; @TX_MAX_TSS_RINGS
l_.str.4:                               ; @.str.4
	.asciz	"Cannot map register space, aborting\n"

	.comm	_BNX2_PCICFG_MISC_CONFIG,4,2    ; @BNX2_PCICFG_MISC_CONFIG
	.comm	_BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA,4,2 ; @BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA
	.comm	_BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP,4,2 ; @BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP
	.comm	_BNX2_MISC_ID,4,2               ; @BNX2_MISC_ID
	.comm	_BNX2_CHIP_5709,8,3             ; @BNX2_CHIP_5709
l_.str.5:                               ; @.str.5
	.asciz	"Not PCIE, aborting\n"

	.comm	_BNX2_FLAG_PCIE,4,2             ; @BNX2_FLAG_PCIE
	.comm	_BNX2_CHIP_REV_Ax,8,3           ; @BNX2_CHIP_REV_Ax
	.comm	_BNX2_FLAG_JUMBO_BROKEN,4,2     ; @BNX2_FLAG_JUMBO_BROKEN
	.comm	_BNX2_FLAG_AER_ENABLED,4,2      ; @BNX2_FLAG_AER_ENABLED
	.comm	_PCI_CAP_ID_PCIX,4,2            ; @PCI_CAP_ID_PCIX
l_.str.6:                               ; @.str.6
	.asciz	"Cannot find PCIX capability, aborting\n"

	.comm	_BNX2_FLAG_BROKEN_STATS,4,2     ; @BNX2_FLAG_BROKEN_STATS
	.comm	_BNX2_FLAG_MSIX_CAP,4,2         ; @BNX2_FLAG_MSIX_CAP
	.comm	_BNX2_CHIP_ID_5706_A0,8,3       ; @BNX2_CHIP_ID_5706_A0
	.comm	_BNX2_CHIP_ID_5706_A1,8,3       ; @BNX2_CHIP_ID_5706_A1
	.comm	_BNX2_FLAG_MSI_CAP,4,2          ; @BNX2_FLAG_MSI_CAP
	.comm	_BNX2_CHIP_5708,8,3             ; @BNX2_CHIP_5708
	.comm	_NETIF_F_HIGHDMA,4,2            ; @NETIF_F_HIGHDMA
l_.str.7:                               ; @.str.7
	.asciz	"pci_set_consistent_dma_mask failed, aborting\n"

l_.str.8:                               ; @.str.8
	.asciz	"System does not support DMA, aborting\n"

	.comm	_PCI_COMMAND,4,2                ; @PCI_COMMAND
	.comm	_PCI_COMMAND_SERR,4,2           ; @PCI_COMMAND_SERR
	.comm	_PCI_COMMAND_PARITY,4,2         ; @PCI_COMMAND_PARITY
	.comm	_BNX2_FLAG_PCIX,4,2             ; @BNX2_FLAG_PCIX
l_.str.9:                               ; @.str.9
	.asciz	"5706 A1 can only be used in a PCIX bus, aborting\n"

	.comm	_BNX2_SHM_HDR_SIGNATURE,4,2     ; @BNX2_SHM_HDR_SIGNATURE
	.comm	_BNX2_MCP_TOE_ID,4,2            ; @BNX2_MCP_TOE_ID
	.comm	_BNX2_MCP_TOE_ID_FUNCTION_ID,4,2 ; @BNX2_MCP_TOE_ID_FUNCTION_ID
	.comm	_BNX2_SHM_HDR_SIGNATURE_SIG_MASK,4,2 ; @BNX2_SHM_HDR_SIGNATURE_SIG_MASK
	.comm	_BNX2_SHM_HDR_SIGNATURE_SIG,4,2 ; @BNX2_SHM_HDR_SIGNATURE_SIG
	.comm	_BNX2_SHM_HDR_ADDR_0,4,2        ; @BNX2_SHM_HDR_ADDR_0
	.comm	_HOST_VIEW_SHMEM_BASE,4,2       ; @HOST_VIEW_SHMEM_BASE
	.comm	_BNX2_DEV_INFO_SIGNATURE,4,2    ; @BNX2_DEV_INFO_SIGNATURE
	.comm	_BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK,4,2 ; @BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK
	.comm	_BNX2_DEV_INFO_SIGNATURE_MAGIC,4,2 ; @BNX2_DEV_INFO_SIGNATURE_MAGIC
l_.str.10:                              ; @.str.10
	.asciz	"Firmware not running, aborting\n"

	.comm	_BNX2_DEV_INFO_BC_REV,4,2       ; @BNX2_DEV_INFO_BC_REV
	.comm	_BNX2_PORT_FEATURE,4,2          ; @BNX2_PORT_FEATURE
	.comm	_BNX2_PORT_FEATURE_WOL_ENABLED,4,2 ; @BNX2_PORT_FEATURE_WOL_ENABLED
	.comm	_BNX2_PORT_FEATURE_ASF_ENABLED,4,2 ; @BNX2_PORT_FEATURE_ASF_ENABLED
	.comm	_BNX2_FLAG_ASF_ENABLE,4,2       ; @BNX2_FLAG_ASF_ENABLE
	.comm	_BNX2_BC_STATE_CONDITION,4,2    ; @BNX2_BC_STATE_CONDITION
	.comm	_BNX2_CONDITION_MFW_RUN_MASK,4,2 ; @BNX2_CONDITION_MFW_RUN_MASK
	.comm	_BNX2_CONDITION_MFW_RUN_UNKNOWN,4,2 ; @BNX2_CONDITION_MFW_RUN_UNKNOWN
	.comm	_BNX2_CONDITION_MFW_RUN_NONE,4,2 ; @BNX2_CONDITION_MFW_RUN_NONE
	.comm	_BNX2_MFW_VER_PTR,4,2           ; @BNX2_MFW_VER_PTR
	.comm	_BNX2_PORT_HW_CFG_MAC_UPPER,4,2 ; @BNX2_PORT_HW_CFG_MAC_UPPER
	.comm	_BNX2_PORT_HW_CFG_MAC_LOWER,4,2 ; @BNX2_PORT_HW_CFG_MAC_LOWER
	.comm	_BNX2_MAX_TX_DESC_CNT,4,2       ; @BNX2_MAX_TX_DESC_CNT
	.comm	_USEC_PER_SEC,4,2               ; @USEC_PER_SEC
	.comm	_BNX2_HC_STATS_TICKS_HC_STAT_TICKS,4,2 ; @BNX2_HC_STATS_TICKS_HC_STAT_TICKS
	.comm	_BNX2_TIMER_INTERVAL,4,2        ; @BNX2_TIMER_INTERVAL
	.comm	_BNX2_CHIP_BOND_SERDES_BIT,4,2  ; @BNX2_CHIP_BOND_SERDES_BIT
	.comm	_BNX2_PHY_FLAG_SERDES,4,2       ; @BNX2_PHY_FLAG_SERDES
	.comm	_PORT_TP,4,2                    ; @PORT_TP
	.comm	_PORT_FIBRE,4,2                 ; @PORT_FIBRE
	.comm	_BNX2_SHARED_HW_CFG_CONFIG,4,2  ; @BNX2_SHARED_HW_CFG_CONFIG
	.comm	_BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX,4,2 ; @BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX
	.comm	_BNX2_FLAG_NO_WOL,4,2           ; @BNX2_FLAG_NO_WOL
	.comm	_BNX2_CHIP_5706,8,3             ; @BNX2_CHIP_5706
	.comm	_PCI_VENDOR_ID_HP,8,3           ; @PCI_VENDOR_ID_HP
	.comm	_BNX2_PHY_FLAG_NO_PARALLEL,4,2  ; @BNX2_PHY_FLAG_NO_PARALLEL
	.comm	_BNX2_SHARED_HW_CFG_PHY_2_5G,4,2 ; @BNX2_SHARED_HW_CFG_PHY_2_5G
	.comm	_BNX2_PHY_FLAG_2_5G_CAPABLE,4,2 ; @BNX2_PHY_FLAG_2_5G_CAPABLE
	.comm	_BNX2_PHY_FLAG_CRC_FIX,4,2      ; @BNX2_PHY_FLAG_CRC_FIX
	.comm	_BNX2_CHIP_REV_Bx,8,3           ; @BNX2_CHIP_REV_Bx
	.comm	_BNX2_PHY_FLAG_DIS_EARLY_DAC,4,2 ; @BNX2_PHY_FLAG_DIS_EARLY_DAC
	.comm	_BNX2_CHIP_ID_5708_A0,8,3       ; @BNX2_CHIP_ID_5708_A0
	.comm	_BNX2_CHIP_ID_5708_B0,8,3       ; @BNX2_CHIP_ID_5708_B0
	.comm	_BNX2_CHIP_ID_5708_B1,8,3       ; @BNX2_CHIP_ID_5708_B1
	.comm	_BNX2_PCI_CONFIG_3,4,2          ; @BNX2_PCI_CONFIG_3
	.comm	_BNX2_PCI_CONFIG_3_VAUX_PRESET,4,2 ; @BNX2_PCI_CONFIG_3_VAUX_PRESET
	.comm	_disable_msi,4,2                ; @disable_msi
	.comm	_PCI_VENDOR_ID_AMD,4,2          ; @PCI_VENDOR_ID_AMD
	.comm	_PCI_DEVICE_ID_AMD_8132_BRIDGE,4,2 ; @PCI_DEVICE_ID_AMD_8132_BRIDGE
	.comm	_FLOW_CTRL_RX,4,2               ; @FLOW_CTRL_RX
	.comm	_FLOW_CTRL_TX,4,2               ; @FLOW_CTRL_TX
	.comm	_bnx2_timer,4,2                 ; @bnx2_timer
	.comm	_BNX2_ISCSI_INITIATOR,4,2       ; @BNX2_ISCSI_INITIATOR
	.comm	_BNX2_ISCSI_INITIATOR_EN,4,2    ; @BNX2_ISCSI_INITIATOR_EN
	.comm	_BNX2_ISCSI_MAX_CONN,4,2        ; @BNX2_ISCSI_MAX_CONN
	.comm	_BNX2_ISCSI_MAX_CONN_MASK,4,2   ; @BNX2_ISCSI_MAX_CONN_MASK
	.comm	_BNX2_ISCSI_MAX_CONN_SHIFT,4,2  ; @BNX2_ISCSI_MAX_CONN_SHIFT
	.comm	_bnx2_cnic_probe,4,2            ; @bnx2_cnic_probe
	.no_dead_strip	_bnx2_init_board
.subsections_via_symbols
