	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mmci_sdmmc_set_clkreg
_mmci_sdmmc_set_clkreg:                 ## @mmci_sdmmc_set_clkreg
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %r14
	movq	16(%rdi), %rcx
	movq	8(%rcx), %rax
	movq	_MMC_TIMING_MMC_DDR52@GOTPCREL(%rip), %rdx
	movq	_MMC_TIMING_UHS_DDR50@GOTPCREL(%rip), %rdi
	xorl	%ebx, %ebx
	cmpq	(%rdi), %rax
	movq	_MCI_STM32_CLK_DDR@GOTPCREL(%rip), %rdi
	movl	(%rdi), %edi
	cmovel	%edi, %ebx
	cmpq	(%rdx), %rax
	cmovel	%edi, %ebx
	testl	%esi, %esi
	je	LBB0_5
## %bb.1:
	movl	(%r14), %eax
	cmpl	%esi, %eax
	ja	LBB0_4
## %bb.2:
	testl	%ebx, %ebx
	jne	LBB0_4
## %bb.3:
	movl	%eax, 4(%r14)
	xorl	%esi, %esi
	jmp	LBB0_6
LBB0_5:
	movq	_MCI_STM32_CLK_CLKDIV_MSK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r14), %eax
	leal	(%rsi,%rsi), %edi
	xorl	%edx, %edx
	divl	%edi
	movl	%eax, 4(%r14)
	jmp	LBB0_6
LBB0_4:
	addl	%esi, %esi
	movl	%eax, %edi
	callq	_DIV_ROUND_UP
	movq	_MCI_STM32_CLK_CLKDIV_MSK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	cmpl	%esi, %eax
	cmovbl	%eax, %esi
	movl	(%r14), %eax
	leal	(%rsi,%rsi), %ecx
	xorl	%edx, %edx
	divl	%ecx
	movl	%eax, 4(%r14)
	movq	16(%r14), %rcx
LBB0_6:
	movq	8(%rcx), %r8
	movq	16(%rcx), %rdx
	movq	_MMC_POWER_ON@GOTPCREL(%rip), %r9
	xorl	%edi, %edi
	cmpq	(%r9), %rdx
	cmovnel	%edi, %eax
	movl	%eax, (%rcx)
	movq	24(%rcx), %rcx
	movq	_MMC_BUS_WIDTH_4@GOTPCREL(%rip), %rdx
	movl	$0, %eax
	cmpq	(%rdx), %rcx
	jne	LBB0_8
## %bb.7:
	movq	_MCI_STM32_CLK_WIDEBUS_4@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_8:
	movq	_MMC_BUS_WIDTH_8@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	jne	LBB0_10
## %bb.9:
	movq	_MCI_STM32_CLK_WIDEBUS_8@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
LBB0_10:
	movq	_MCI_STM32_CLK_HWFCEN@GOTPCREL(%rip), %rcx
	orl	%ebx, %esi
	orl	%eax, %esi
	orl	%edi, %esi
	orl	(%rcx), %esi
	orl	8(%r14), %esi
	movq	_MMC_TIMING_UHS_SDR50@GOTPCREL(%rip), %rax
	cmpq	(%rax), %r8
	jl	LBB0_13
## %bb.11:
	movq	_MCI_STM32_CLK_BUSSPEED@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movq	_MMC_TIMING_UHS_SDR104@GOTPCREL(%rip), %rax
	cmpq	(%rax), %r8
	jne	LBB0_13
## %bb.12:
	movq	_MCI_STM32_CLK_SEL_MSK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %esi
	movq	_MCI_STM32_CLK_SELFBCK@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
LBB0_13:
	movq	%r14, %rdi
                                        ## kill: def $esi killed $esi killed $rsi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_mmci_write_clkreg              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_MMC_TIMING_MMC_DDR52,8,3       ## @MMC_TIMING_MMC_DDR52
	.comm	_MMC_TIMING_UHS_DDR50,8,3       ## @MMC_TIMING_UHS_DDR50
	.comm	_MCI_STM32_CLK_DDR,4,2          ## @MCI_STM32_CLK_DDR
	.comm	_MCI_STM32_CLK_CLKDIV_MSK,4,2   ## @MCI_STM32_CLK_CLKDIV_MSK
	.comm	_MMC_POWER_ON,8,3               ## @MMC_POWER_ON
	.comm	_MMC_BUS_WIDTH_4,8,3            ## @MMC_BUS_WIDTH_4
	.comm	_MCI_STM32_CLK_WIDEBUS_4,4,2    ## @MCI_STM32_CLK_WIDEBUS_4
	.comm	_MMC_BUS_WIDTH_8,8,3            ## @MMC_BUS_WIDTH_8
	.comm	_MCI_STM32_CLK_WIDEBUS_8,4,2    ## @MCI_STM32_CLK_WIDEBUS_8
	.comm	_MCI_STM32_CLK_HWFCEN,4,2       ## @MCI_STM32_CLK_HWFCEN
	.comm	_MMC_TIMING_UHS_SDR50,8,3       ## @MMC_TIMING_UHS_SDR50
	.comm	_MCI_STM32_CLK_BUSSPEED,4,2     ## @MCI_STM32_CLK_BUSSPEED
	.comm	_MMC_TIMING_UHS_SDR104,8,3      ## @MMC_TIMING_UHS_SDR104
	.comm	_MCI_STM32_CLK_SEL_MSK,4,2      ## @MCI_STM32_CLK_SEL_MSK
	.comm	_MCI_STM32_CLK_SELFBCK,4,2      ## @MCI_STM32_CLK_SELFBCK
	.no_dead_strip	_mmci_sdmmc_set_clkreg
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mmci_sdmmc_set_clkreg
_mmci_sdmmc_set_clkreg:                 ; @mmci_sdmmc_set_clkreg
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	x8, [x0, #16]
	ldr	x9, [x8, #8]
Lloh0:
	adrp	x10, _MMC_TIMING_MMC_DDR52@GOTPAGE
Lloh1:
	ldr	x10, [x10, _MMC_TIMING_MMC_DDR52@GOTPAGEOFF]
Lloh2:
	ldr	x10, [x10]
Lloh3:
	adrp	x11, _MMC_TIMING_UHS_DDR50@GOTPAGE
Lloh4:
	ldr	x11, [x11, _MMC_TIMING_UHS_DDR50@GOTPAGEOFF]
Lloh5:
	ldr	x11, [x11]
	cmp	x9, x11
	ccmp	x9, x10, #4, ne
Lloh6:
	adrp	x9, _MCI_STM32_CLK_DDR@GOTPAGE
Lloh7:
	ldr	x9, [x9, _MCI_STM32_CLK_DDR@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	csel	w20, w9, wzr, eq
	cbz	w1, LBB0_3
; %bb.1:
	ldr	w0, [x19]
	cmp	w0, w1
	ccmp	w20, #0, #0, ls
	b.eq	LBB0_4
; %bb.2:
	lsl	w1, w1, #1
	bl	_DIV_ROUND_UP
Lloh9:
	adrp	x8, _MCI_STM32_CLK_CLKDIV_MSK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _MCI_STM32_CLK_CLKDIV_MSK@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	cmp	w0, w8
	csel	w9, w0, w8, lo
	ldr	w8, [x19]
	lsl	w10, w9, #1
	udiv	w0, w8, w10
	str	w0, [x19, #4]
	ldr	x8, [x19, #16]
	b	LBB0_6
LBB0_3:
Lloh12:
	adrp	x9, _MCI_STM32_CLK_CLKDIV_MSK@GOTPAGE
Lloh13:
	ldr	x9, [x9, _MCI_STM32_CLK_CLKDIV_MSK@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	ldr	w10, [x19]
	lsl	w11, w9, #1
	udiv	w0, w10, w11
	b	LBB0_5
LBB0_4:
	mov	w9, #0
LBB0_5:
	str	w0, [x19, #4]
LBB0_6:
Lloh15:
	adrp	x10, _MMC_POWER_ON@GOTPAGE
Lloh16:
	ldr	x10, [x10, _MMC_POWER_ON@GOTPAGEOFF]
Lloh17:
	ldr	x11, [x10]
	ldp	x10, x12, [x8, #8]
	cmp	x12, x11
	csel	w11, w0, wzr, eq
	str	w11, [x8]
	ldr	x8, [x8, #24]
Lloh18:
	adrp	x11, _MMC_BUS_WIDTH_4@GOTPAGE
Lloh19:
	ldr	x11, [x11, _MMC_BUS_WIDTH_4@GOTPAGEOFF]
Lloh20:
	ldr	x11, [x11]
Lloh21:
	adrp	x12, _MCI_STM32_CLK_WIDEBUS_4@GOTPAGE
Lloh22:
	ldr	x12, [x12, _MCI_STM32_CLK_WIDEBUS_4@GOTPAGEOFF]
Lloh23:
	ldr	w12, [x12]
	cmp	x8, x11
	csel	w11, w12, wzr, eq
Lloh24:
	adrp	x12, _MMC_BUS_WIDTH_8@GOTPAGE
Lloh25:
	ldr	x12, [x12, _MMC_BUS_WIDTH_8@GOTPAGEOFF]
Lloh26:
	ldr	x12, [x12]
Lloh27:
	adrp	x13, _MCI_STM32_CLK_WIDEBUS_8@GOTPAGE
Lloh28:
	ldr	x13, [x13, _MCI_STM32_CLK_WIDEBUS_8@GOTPAGEOFF]
Lloh29:
	ldr	w13, [x13]
	cmp	x8, x12
Lloh30:
	adrp	x8, _MCI_STM32_CLK_HWFCEN@GOTPAGE
Lloh31:
	ldr	x8, [x8, _MCI_STM32_CLK_HWFCEN@GOTPAGEOFF]
	csel	w12, w13, wzr, eq
Lloh32:
	ldr	w8, [x8]
	ldr	w13, [x19, #8]
	orr	w9, w9, w20
	orr	w9, w9, w11
	orr	w9, w9, w12
	orr	w8, w9, w8
	orr	w1, w8, w13
Lloh33:
	adrp	x8, _MMC_TIMING_UHS_SDR50@GOTPAGE
Lloh34:
	ldr	x8, [x8, _MMC_TIMING_UHS_SDR50@GOTPAGEOFF]
Lloh35:
	ldr	x8, [x8]
	cmp	x10, x8
	b.lt	LBB0_9
; %bb.7:
Lloh36:
	adrp	x8, _MCI_STM32_CLK_BUSSPEED@GOTPAGE
Lloh37:
	ldr	x8, [x8, _MCI_STM32_CLK_BUSSPEED@GOTPAGEOFF]
Lloh38:
	ldr	w8, [x8]
	orr	w1, w8, w1
Lloh39:
	adrp	x8, _MMC_TIMING_UHS_SDR104@GOTPAGE
Lloh40:
	ldr	x8, [x8, _MMC_TIMING_UHS_SDR104@GOTPAGEOFF]
Lloh41:
	ldr	x8, [x8]
	cmp	x10, x8
	b.ne	LBB0_9
; %bb.8:
Lloh42:
	adrp	x8, _MCI_STM32_CLK_SEL_MSK@GOTPAGE
Lloh43:
	ldr	x8, [x8, _MCI_STM32_CLK_SEL_MSK@GOTPAGEOFF]
Lloh44:
	ldr	w8, [x8]
	bic	w8, w1, w8
Lloh45:
	adrp	x9, _MCI_STM32_CLK_SELFBCK@GOTPAGE
Lloh46:
	ldr	x9, [x9, _MCI_STM32_CLK_SELFBCK@GOTPAGEOFF]
Lloh47:
	ldr	w9, [x9]
	orr	w1, w8, w9
LBB0_9:
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_mmci_write_clkreg
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.cfi_endproc
                                        ; -- End function
	.comm	_MMC_TIMING_MMC_DDR52,8,3       ; @MMC_TIMING_MMC_DDR52
	.comm	_MMC_TIMING_UHS_DDR50,8,3       ; @MMC_TIMING_UHS_DDR50
	.comm	_MCI_STM32_CLK_DDR,4,2          ; @MCI_STM32_CLK_DDR
	.comm	_MCI_STM32_CLK_CLKDIV_MSK,4,2   ; @MCI_STM32_CLK_CLKDIV_MSK
	.comm	_MMC_POWER_ON,8,3               ; @MMC_POWER_ON
	.comm	_MMC_BUS_WIDTH_4,8,3            ; @MMC_BUS_WIDTH_4
	.comm	_MCI_STM32_CLK_WIDEBUS_4,4,2    ; @MCI_STM32_CLK_WIDEBUS_4
	.comm	_MMC_BUS_WIDTH_8,8,3            ; @MMC_BUS_WIDTH_8
	.comm	_MCI_STM32_CLK_WIDEBUS_8,4,2    ; @MCI_STM32_CLK_WIDEBUS_8
	.comm	_MCI_STM32_CLK_HWFCEN,4,2       ; @MCI_STM32_CLK_HWFCEN
	.comm	_MMC_TIMING_UHS_SDR50,8,3       ; @MMC_TIMING_UHS_SDR50
	.comm	_MCI_STM32_CLK_BUSSPEED,4,2     ; @MCI_STM32_CLK_BUSSPEED
	.comm	_MMC_TIMING_UHS_SDR104,8,3      ; @MMC_TIMING_UHS_SDR104
	.comm	_MCI_STM32_CLK_SEL_MSK,4,2      ; @MCI_STM32_CLK_SEL_MSK
	.comm	_MCI_STM32_CLK_SELFBCK,4,2      ; @MCI_STM32_CLK_SELFBCK
	.no_dead_strip	_mmci_sdmmc_set_clkreg
.subsections_via_symbols
