	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_mc_setup_latency_allowance
_tegra_mc_setup_latency_allowance:      ## @tegra_mc_setup_latency_allowance
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	16(%rdi), %r14
	movl	8(%rdi), %edi
	callq	_clk_get_rate
	imulq	%rax, %r14
	movq	_NSEC_PER_SEC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_do_div
	movq	_MC_EMEM_ARB_CFG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_mc_readl
	movq	_MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r15d
	notl	%r15d
	andl	%eax, %r15d
	movq	%r14, %rdi
	callq	_MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE
	orl	%eax, %r15d
	movl	(%rbx), %edx
	movq	%r12, %rdi
	movl	%r15d, %esi
	callq	_mc_writel
	movq	(%r12), %rax
	cmpl	$0, (%rax)
	je	LBB0_3
## %bb.1:
	movl	$12, %ebx
	xorl	%r14d, %r14d
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	8(%rax), %r15
	movl	(%r15,%rbx), %esi
	movq	%r12, %rdi
	callq	_mc_readl
	movl	-12(%r15,%rbx), %esi
	movzbl	-8(%r15,%rbx), %ecx
	movl	%esi, %edx
	shll	%cl, %edx
	andl	-4(%r15,%rbx), %esi
	shll	%cl, %esi
	notl	%edx
	andl	%eax, %edx
	orl	%edx, %esi
	movl	(%r15,%rbx), %edx
	movq	%r12, %rdi
	callq	_mc_writel
	incq	%r14
	movq	(%r12), %rax
	movl	(%rax), %ecx
	addq	$16, %rbx
	cmpq	%rcx, %r14
	jb	LBB0_2
LBB0_3:
	movq	_MC_TIMING_UPDATE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MC_TIMING_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_mc_writel
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_NSEC_PER_SEC,4,2               ## @NSEC_PER_SEC
	.comm	_MC_EMEM_ARB_CFG,4,2            ## @MC_EMEM_ARB_CFG
	.comm	_MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK,4,2 ## @MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK
	.comm	_MC_TIMING_UPDATE,4,2           ## @MC_TIMING_UPDATE
	.comm	_MC_TIMING_CONTROL,4,2          ## @MC_TIMING_CONTROL
	.no_dead_strip	_tegra_mc_setup_latency_allowance
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_mc_setup_latency_allowance
_tegra_mc_setup_latency_allowance:      ; @tegra_mc_setup_latency_allowance
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x20, [x0, #16]
	ldr	w0, [x0, #8]
	bl	_clk_get_rate
	mul	x20, x0, x20
Lloh0:
	adrp	x8, _NSEC_PER_SEC@GOTPAGE
Lloh1:
	ldr	x8, [x8, _NSEC_PER_SEC@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_do_div
Lloh3:
	adrp	x21, _MC_EMEM_ARB_CFG@GOTPAGE
Lloh4:
	ldr	x21, [x21, _MC_EMEM_ARB_CFG@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_mc_readl
Lloh5:
	adrp	x8, _MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	bic	w22, w0, w8
	mov	x0, x20
	bl	_MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE
	orr	w1, w22, w0
	ldr	w2, [x21]
	mov	x0, x19
	bl	_mc_writel
	ldr	x8, [x19]
	ldr	w9, [x8]
	cbz	w9, LBB0_3
; %bb.1:
	mov	x20, #0
	mov	x21, #0
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x8, #8]
	add	x22, x8, x20
	ldr	w1, [x22, #12]
	mov	x0, x19
	bl	_mc_readl
	ldp	w8, w9, [x22]
	lsl	w10, w8, w9
	bic	w10, w0, w10
	ldp	w11, w2, [x22, #8]
	and	w8, w11, w8
	lsl	w8, w8, w9
	orr	w1, w8, w10
	mov	x0, x19
	bl	_mc_writel
	add	x21, x21, #1
	ldr	x8, [x19]
	ldr	w9, [x8]
	add	x20, x20, #16
	cmp	x21, x9
	b.lo	LBB0_2
LBB0_3:
Lloh8:
	adrp	x8, _MC_TIMING_UPDATE@GOTPAGE
Lloh9:
	ldr	x8, [x8, _MC_TIMING_UPDATE@GOTPAGEOFF]
Lloh10:
	ldr	w1, [x8]
Lloh11:
	adrp	x8, _MC_TIMING_CONTROL@GOTPAGE
Lloh12:
	ldr	x8, [x8, _MC_TIMING_CONTROL@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mc_writel
	mov	w0, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.cfi_endproc
                                        ; -- End function
	.comm	_NSEC_PER_SEC,4,2               ; @NSEC_PER_SEC
	.comm	_MC_EMEM_ARB_CFG,4,2            ; @MC_EMEM_ARB_CFG
	.comm	_MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK,4,2 ; @MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK
	.comm	_MC_TIMING_UPDATE,4,2           ; @MC_TIMING_UPDATE
	.comm	_MC_TIMING_CONTROL,4,2          ; @MC_TIMING_CONTROL
	.no_dead_strip	_tegra_mc_setup_latency_allowance
.subsections_via_symbols
