	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function arm_smmu_device_cfg_probe
_arm_smmu_device_cfg_probe:             ## @arm_smmu_device_cfg_probe
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	_ARM_SMMU_FEAT_COHERENT_WALK@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	andl	(%rdi), %r13d
	movl	64(%rdi), %edi
	leaq	L_.str(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_notice
	movl	64(%r12), %edi
	movq	8(%r12), %rax
	movq	_ARM_SMMU_V2@GOTPCREL(%rip), %rbx
	xorl	%edx, %edx
	cmpq	(%rbx), %rax
	sete	%dl
	incl	%edx
	leaq	L_.str.1(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_notice
	movq	_ARM_SMMU_GR0_ID0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_arm_smmu_gr0_read
	movl	%eax, %r14d
	movq	_force_stage@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	cmpl	$2, %eax
	je	LBB0_3
## %bb.1:
	cmpl	$1, %eax
	jne	LBB0_5
## %bb.2:
	movq	_ID0_S2TS@GOTPCREL(%rip), %rax
	jmp	LBB0_4
LBB0_3:
	movq	_ID0_S1TS@GOTPCREL(%rip), %rax
LBB0_4:
	movq	_ID0_NTS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	notl	%ecx
	andl	%ecx, %r14d
LBB0_5:
	movq	_ID0_S1TS@GOTPCREL(%rip), %r15
	testl	%r14d, (%r15)
	je	LBB0_7
## %bb.6:
	movq	_ARM_SMMU_FEAT_TRANS_S1@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r12)
	movl	64(%r12), %edi
	leaq	L_.str.2(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_notice
LBB0_7:
	movq	_ID0_S2TS@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_9
## %bb.8:
	movq	_ARM_SMMU_FEAT_TRANS_S2@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r12)
	movl	64(%r12), %edi
	leaq	L_.str.3(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_notice
LBB0_9:
	movq	_ID0_NTS@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_11
## %bb.10:
	movq	_ARM_SMMU_FEAT_TRANS_NESTED@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r12)
	movl	64(%r12), %edi
	leaq	L_.str.4(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_notice
LBB0_11:
	movl	(%r12), %eax
	movq	_ARM_SMMU_FEAT_TRANS_S1@GOTPCREL(%rip), %rdx
	movq	_ARM_SMMU_FEAT_TRANS_S2@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rdx), %ecx
	testl	%eax, %ecx
	je	LBB0_31
## %bb.12:
	testl	%r14d, (%r15)
	je	LBB0_16
## %bb.13:
	movq	8(%r12), %rcx
	cmpq	(%rbx), %rcx
	jl	LBB0_15
## %bb.14:
	movq	_ID0_ATOSNS@GOTPCREL(%rip), %rcx
	testl	%r14d, (%rcx)
	jne	LBB0_16
LBB0_15:
	movq	_ARM_SMMU_FEAT_TRANS_OPS@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r12)
	movl	64(%r12), %edi
	leaq	L_.str.6(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_notice
LBB0_16:
	movq	_ID0_CTTW@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	movl	(%rax), %eax
	andl	%r14d, %eax
	setne	%bl
	orl	%r13d, %eax
	je	LBB0_18
## %bb.17:
	testl	%r13d, %r13d
	movl	64(%r12), %edi
	leaq	L_.str.8(%rip), %rax
	leaq	L_.str.9(%rip), %rdx
	cmovneq	%rax, %rdx
	leaq	L_.str.7(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_notice
LBB0_18:
	cmpl	%ebx, %r13d
	je	LBB0_20
## %bb.19:
	movl	64(%r12), %edi
	leaq	L_.str.10(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_notice
LBB0_20:
	movq	8(%r12), %rax
	movq	_ARM_SMMU_V2@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_23
## %bb.21:
	movq	_ID0_EXIDS@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_23
## %bb.22:
	movq	_ARM_SMMU_FEAT_EXIDS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r12)
	movl	$65536, %r15d                   ## imm = 0x10000
	jmp	LBB0_24
LBB0_23:
	movq	_ID0_NUMSIDB@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_FIELD_GET
	movl	$1, %r15d
	movl	%eax, %ecx
	shll	%cl, %r15d
LBB0_24:
	leal	-1(%r15), %eax
	movl	%eax, 16(%r12)
	movq	_ID0_SMS@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_28
## %bb.25:
	movq	_ARM_SMMU_FEAT_STREAM_MATCH@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r12)
	movq	_ID0_NUMSMRG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_FIELD_GET
	movl	64(%r12), %edi
	testl	%eax, %eax
	je	LBB0_33
## %bb.26:
	movl	%eax, %r15d
	movq	_GFP_KERNEL@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%r15d, %esi
	movl	$1, %edx
	callq	_devm_kcalloc
	movq	%rax, 96(%r12)
	testq	%rax, %rax
	je	LBB0_32
## %bb.27:
	movl	64(%r12), %edi
	leaq	L_.str.12(%rip), %rsi
	movl	%r15d, %edx
	xorl	%eax, %eax
	callq	_dev_notice
LBB0_28:
	movl	64(%r12), %edi
	movq	_GFP_KERNEL@GOTPCREL(%rip), %r13
	movl	(%r13), %ecx
	movl	%r15d, %esi
	movl	$4, %edx
	callq	_devm_kmalloc_array
	movq	%rax, 88(%r12)
	testq	%rax, %rax
	je	LBB0_32
## %bb.29:
	cmpl	$2, %r15d
	movl	$1, %ecx
	cmovael	%r15d, %ecx
	cmpl	$8, %ecx
	jb	LBB0_30
## %bb.34:
	movq	_s2cr_init_val@GOTPCREL(%rip), %r8
	leaq	4(%r8), %rdx
	cmpq	%rdx, %rax
	jae	LBB0_37
## %bb.35:
	leaq	(%rax,%rcx,4), %rdx
	cmpq	_s2cr_init_val@GOTPCREL(%rip), %rdx
	jbe	LBB0_37
LBB0_30:
	xorl	%edx, %edx
LBB0_43:
	movq	%rdx, %r8
	notq	%r8
	addq	%rcx, %r8
	movq	%rcx, %rdi
	andq	$3, %rdi
	je	LBB0_46
## %bb.44:
	movq	_s2cr_init_val@GOTPCREL(%rip), %rbx
	.p2align	4, 0x90
LBB0_45:                                ## =>This Inner Loop Header: Depth=1
	movl	(%rbx), %esi
	movl	%esi, (%rax,%rdx,4)
	incq	%rdx
	decq	%rdi
	jne	LBB0_45
LBB0_46:
	cmpq	$3, %r8
	movq	_ARM_SMMU_V2@GOTPCREL(%rip), %rbx
	jb	LBB0_49
## %bb.47:
	movq	_s2cr_init_val@GOTPCREL(%rip), %rsi
	.p2align	4, 0x90
LBB0_48:                                ## =>This Inner Loop Header: Depth=1
	movl	(%rsi), %edi
	movl	%edi, (%rax,%rdx,4)
	movl	(%rsi), %edi
	movl	%edi, 4(%rax,%rdx,4)
	movl	(%rsi), %edi
	movl	%edi, 8(%rax,%rdx,4)
	movl	(%rsi), %edi
	movl	%edi, 12(%rax,%rdx,4)
	addq	$4, %rdx
	cmpq	%rdx, %rcx
	jne	LBB0_48
	jmp	LBB0_49
LBB0_31:
	movl	64(%r12), %edi
	leaq	L_.str.5(%rip), %rsi
	jmp	LBB0_57
LBB0_32:
	movq	_ENOMEM@GOTPCREL(%rip), %rax
	jmp	LBB0_58
LBB0_33:
	leaq	L_.str.11(%rip), %rsi
	jmp	LBB0_57
LBB0_37:
	movl	%ecx, %edx
	andl	$-8, %edx
	leaq	-8(%rdx), %rdi
	movq	%rdi, %rsi
	shrq	$3, %rsi
	incq	%rsi
	testq	%rdi, %rdi
	je	LBB0_90
## %bb.38:
	movq	%rsi, %rdi
	andq	$-2, %rdi
	movd	(%r8), %xmm0                    ## xmm0 = mem[0],zero,zero,zero
	pshufd	$0, %xmm0, %xmm0                ## xmm0 = xmm0[0,0,0,0]
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_39:                                ## =>This Inner Loop Header: Depth=1
	movdqu	%xmm0, (%rax,%rbx,4)
	movdqu	%xmm0, 16(%rax,%rbx,4)
	movdqu	%xmm0, 32(%rax,%rbx,4)
	movdqu	%xmm0, 48(%rax,%rbx,4)
	addq	$16, %rbx
	addq	$-2, %rdi
	jne	LBB0_39
## %bb.40:
	testb	$1, %sil
	je	LBB0_42
LBB0_41:
	movd	(%r8), %xmm0                    ## xmm0 = mem[0],zero,zero,zero
	pshufd	$0, %xmm0, %xmm0                ## xmm0 = xmm0[0,0,0,0]
	movdqu	%xmm0, (%rax,%rbx,4)
	movdqu	%xmm0, 16(%rax,%rbx,4)
LBB0_42:
	cmpq	%rcx, %rdx
	movq	_ARM_SMMU_V2@GOTPCREL(%rip), %rbx
	jne	LBB0_43
LBB0_49:
	movl	%r15d, 20(%r12)
	leaq	84(%r12), %rdi
	callq	_mutex_init
	leaq	80(%r12), %rdi
	callq	_spin_lock_init
	movq	8(%r12), %rax
	cmpq	(%rbx), %rax
	jl	LBB0_51
## %bb.50:
	movq	_ID0_PTFS_NO_AARCH32@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	jne	LBB0_53
LBB0_51:
	movq	_ARM_SMMU_FEAT_FMT_AARCH32_L@GOTPCREL(%rip), %rcx
	movl	(%r12), %eax
	orl	(%rcx), %eax
	movl	%eax, (%r12)
	movq	_ID0_PTFS_NO_AARCH32S@GOTPCREL(%rip), %rcx
	testl	%r14d, (%rcx)
	jne	LBB0_53
## %bb.52:
	movq	_ARM_SMMU_FEAT_FMT_AARCH32_S@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r12)
LBB0_53:
	movq	_ARM_SMMU_GR0_ID1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_arm_smmu_gr0_read
	movl	%eax, %r14d
	movq	_ID1_PAGESIZE@GOTPCREL(%rip), %rax
	xorl	%ecx, %ecx
	movl	(%rax), %eax
	andl	%r14d, %eax
	setne	%cl
	leal	12(,%rcx,4), %eax
	movl	%eax, 24(%r12)
	movq	_ID1_NUMPAGENDXB@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_FIELD_GET
                                        ## kill: def $eax killed $eax def $rax
	leal	1(%rax), %ecx
	movl	$1, %ebx
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %ebx
	movl	28(%r12), %eax
	leal	(%rbx,%rbx), %edx
	movb	24(%r12), %cl
	shll	%cl, %edx
	cmpl	%edx, %eax
	je	LBB0_55
## %bb.54:
	movl	64(%r12), %edi
	leaq	L_.str.13(%rip), %rsi
	movl	%eax, %ecx
	xorl	%eax, %eax
	callq	_dev_warn
LBB0_55:
	movl	%ebx, 28(%r12)
	movq	_ID1_NUMS2CB@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_FIELD_GET
	movl	%eax, 32(%r12)
	movq	_ID1_NUMCB@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_FIELD_GET
	movl	%eax, 36(%r12)
	movl	32(%r12), %ecx
	movl	64(%r12), %edi
	cmpl	%eax, %ecx
	jbe	LBB0_61
## %bb.56:
	leaq	L_.str.14(%rip), %rsi
LBB0_57:
	callq	_dev_err
	movq	_ENODEV@GOTPCREL(%rip), %rax
LBB0_58:
	xorl	%ebx, %ebx
LBB0_59:
	subl	(%rax), %ebx
LBB0_60:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_61:
	leaq	L_.str.15(%rip), %rsi
	xorl	%ebx, %ebx
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_dev_notice
	movl	36(%r12), %esi
	movl	64(%r12), %edi
	movl	(%r13), %ecx
	movl	$1, %edx
	callq	_devm_kcalloc
	movq	%rax, 72(%r12)
	testq	%rax, %rax
	je	LBB0_68
## %bb.62:
	movq	_ARM_SMMU_GR0_ID2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_arm_smmu_gr0_read
	movl	%eax, %r14d
	movq	_ID2_IAS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_FIELD_GET
	movl	%eax, %edi
	callq	_arm_smmu_id_size_to_bits
	movl	%eax, 40(%r12)
	movq	_ID2_OAS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_FIELD_GET
	movl	%eax, %edi
	callq	_arm_smmu_id_size_to_bits
	movl	%eax, 44(%r12)
	movq	_ID2_VMID16@GOTPCREL(%rip), %rcx
	testl	%r14d, (%rcx)
	je	LBB0_64
## %bb.63:
	movq	_ARM_SMMU_FEAT_VMID16@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	%ecx, (%r12)
LBB0_64:
	movl	64(%r12), %ebx
	movl	%eax, %edi
	callq	_DMA_BIT_MASK
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_dma_set_mask_and_coherent
	testq	%rax, %rax
	je	LBB0_66
## %bb.65:
	movl	64(%r12), %edi
	leaq	L_.str.16(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_warn
LBB0_66:
	movq	8(%r12), %rax
	movq	_ARM_SMMU_V2@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	movq	_ARM_SMMU_FEAT_TRANS_S2@GOTPCREL(%rip), %rbx
	jge	LBB0_69
## %bb.67:
	movl	40(%r12), %ecx
	movl	%ecx, 48(%r12)
	movq	_ARM_SMMU_V1_64K@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_74
	jmp	LBB0_75
LBB0_68:
	movq	_ENOMEM@GOTPCREL(%rip), %rax
	jmp	LBB0_59
LBB0_69:
	movq	_ID2_UBS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r14d, %esi
	callq	_FIELD_GET
	movl	%eax, %edi
	callq	_arm_smmu_id_size_to_bits
	movl	%eax, 48(%r12)
	movq	_ID2_PTFS_4K@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_71
## %bb.70:
	movq	_ARM_SMMU_FEAT_FMT_AARCH64_4K@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r12)
LBB0_71:
	movq	_ID2_PTFS_16K@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_73
## %bb.72:
	movq	_ARM_SMMU_FEAT_FMT_AARCH64_16K@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r12)
LBB0_73:
	movq	_ID2_PTFS_64K@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_75
LBB0_74:
	movq	_ARM_SMMU_FEAT_FMT_AARCH64_64K@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r12)
LBB0_75:
	movl	(%r12), %eax
	movq	_ARM_SMMU_FEAT_FMT_AARCH32_S@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_77
## %bb.76:
	movq	_SZ_4K@GOTPCREL(%rip), %rcx
	movq	_SZ_64K@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	movq	_SZ_1M@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	_SZ_16M@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	orl	%edx, 52(%r12)
LBB0_77:
	movq	_ARM_SMMU_FEAT_FMT_AARCH32_L@GOTPCREL(%rip), %rcx
	movq	_ARM_SMMU_FEAT_FMT_AARCH64_4K@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	testl	%eax, %edx
	je	LBB0_79
## %bb.78:
	movq	_SZ_4K@GOTPCREL(%rip), %rcx
	movq	_SZ_2M@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	movq	_SZ_1G@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	orl	%edx, 52(%r12)
LBB0_79:
	movq	_ARM_SMMU_FEAT_FMT_AARCH64_16K@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_81
## %bb.80:
	movq	_SZ_16K@GOTPCREL(%rip), %rcx
	movq	_SZ_32M@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	orl	%edx, 52(%r12)
LBB0_81:
	movq	_ARM_SMMU_FEAT_FMT_AARCH64_64K@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_83
## %bb.82:
	movq	_SZ_64K@GOTPCREL(%rip), %rax
	movq	_SZ_512M@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	orl	%ecx, 52(%r12)
LBB0_83:
	movq	_arm_smmu_ops@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	cmpq	$-1, %rcx
	movl	$0, %esi
	cmovneq	%rcx, %rsi
	movslq	52(%r12), %rdx
	orq	%rdx, %rsi
	movq	%rsi, (%rax)
	movl	64(%r12), %edi
	leaq	L_.str.17(%rip), %rsi
                                        ## kill: def $edx killed $edx killed $rdx
	xorl	%eax, %eax
	callq	_dev_notice
	movl	(%r12), %eax
	movq	_ARM_SMMU_FEAT_TRANS_S1@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_85
## %bb.84:
	movl	64(%r12), %edi
	movl	40(%r12), %ecx
	movl	48(%r12), %edx
	leaq	L_.str.18(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_notice
	movl	(%r12), %eax
LBB0_85:
	testl	%eax, (%rbx)
	je	LBB0_87
## %bb.86:
	movl	64(%r12), %edi
	movl	40(%r12), %edx
	movl	44(%r12), %ecx
	leaq	L_.str.19(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_notice
LBB0_87:
	movq	56(%r12), %rax
	xorl	%ebx, %ebx
	testq	%rax, %rax
	je	LBB0_60
## %bb.88:
	movq	(%rax), %rax
	testq	%rax, %rax
	je	LBB0_60
## %bb.89:
	movq	%r12, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmpq	*%rax                           ## TAILCALL
LBB0_90:
	xorl	%ebx, %ebx
	testb	$1, %sil
	jne	LBB0_41
	jmp	LBB0_42
	.cfi_endproc
                                        ## -- End function
	.comm	_ARM_SMMU_FEAT_COHERENT_WALK,4,2 ## @ARM_SMMU_FEAT_COHERENT_WALK
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"probing hardware configuration...\n"

L_.str.1:                               ## @.str.1
	.asciz	"SMMUv%d with:\n"

	.comm	_ARM_SMMU_V2,8,3                ## @ARM_SMMU_V2
	.comm	_ARM_SMMU_GR0_ID0,4,2           ## @ARM_SMMU_GR0_ID0
	.comm	_force_stage,4,2                ## @force_stage
	.comm	_ID0_S2TS,4,2                   ## @ID0_S2TS
	.comm	_ID0_NTS,4,2                    ## @ID0_NTS
	.comm	_ID0_S1TS,4,2                   ## @ID0_S1TS
	.comm	_ARM_SMMU_FEAT_TRANS_S1,4,2     ## @ARM_SMMU_FEAT_TRANS_S1
L_.str.2:                               ## @.str.2
	.asciz	"\tstage 1 translation\n"

	.comm	_ARM_SMMU_FEAT_TRANS_S2,4,2     ## @ARM_SMMU_FEAT_TRANS_S2
L_.str.3:                               ## @.str.3
	.asciz	"\tstage 2 translation\n"

	.comm	_ARM_SMMU_FEAT_TRANS_NESTED,4,2 ## @ARM_SMMU_FEAT_TRANS_NESTED
L_.str.4:                               ## @.str.4
	.asciz	"\tnested translation\n"

L_.str.5:                               ## @.str.5
	.asciz	"\tno translation support!\n"

	.comm	_ENODEV,4,2                     ## @ENODEV
	.comm	_ID0_ATOSNS,4,2                 ## @ID0_ATOSNS
	.comm	_ARM_SMMU_FEAT_TRANS_OPS,4,2    ## @ARM_SMMU_FEAT_TRANS_OPS
L_.str.6:                               ## @.str.6
	.asciz	"\taddress translation ops\n"

	.comm	_ID0_CTTW,4,2                   ## @ID0_CTTW
L_.str.7:                               ## @.str.7
	.asciz	"\t%scoherent table walk\n"

L_.str.8:                               ## @.str.8
	.space	1

L_.str.9:                               ## @.str.9
	.asciz	"non-"

L_.str.10:                              ## @.str.10
	.asciz	"\t(IDR0.CTTW overridden by FW configuration)\n"

	.comm	_ID0_EXIDS,4,2                  ## @ID0_EXIDS
	.comm	_ARM_SMMU_FEAT_EXIDS,4,2        ## @ARM_SMMU_FEAT_EXIDS
	.comm	_ID0_NUMSIDB,4,2                ## @ID0_NUMSIDB
	.comm	_ID0_SMS,4,2                    ## @ID0_SMS
	.comm	_ARM_SMMU_FEAT_STREAM_MATCH,4,2 ## @ARM_SMMU_FEAT_STREAM_MATCH
	.comm	_ID0_NUMSMRG,4,2                ## @ID0_NUMSMRG
L_.str.11:                              ## @.str.11
	.asciz	"stream-matching supported, but no SMRs present!\n"

	.comm	_GFP_KERNEL,4,2                 ## @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ## @ENOMEM
L_.str.12:                              ## @.str.12
	.asciz	"\tstream matching with %u register groups"

	.comm	_s2cr_init_val,4,2              ## @s2cr_init_val
	.comm	_ID0_PTFS_NO_AARCH32,4,2        ## @ID0_PTFS_NO_AARCH32
	.comm	_ARM_SMMU_FEAT_FMT_AARCH32_L,4,2 ## @ARM_SMMU_FEAT_FMT_AARCH32_L
	.comm	_ID0_PTFS_NO_AARCH32S,4,2       ## @ID0_PTFS_NO_AARCH32S
	.comm	_ARM_SMMU_FEAT_FMT_AARCH32_S,4,2 ## @ARM_SMMU_FEAT_FMT_AARCH32_S
	.comm	_ARM_SMMU_GR0_ID1,4,2           ## @ARM_SMMU_GR0_ID1
	.comm	_ID1_PAGESIZE,4,2               ## @ID1_PAGESIZE
	.comm	_ID1_NUMPAGENDXB,4,2            ## @ID1_NUMPAGENDXB
L_.str.13:                              ## @.str.13
	.asciz	"SMMU address space size (0x%x) differs from mapped region size (0x%x)!\n"

	.comm	_ID1_NUMS2CB,4,2                ## @ID1_NUMS2CB
	.comm	_ID1_NUMCB,4,2                  ## @ID1_NUMCB
L_.str.14:                              ## @.str.14
	.asciz	"impossible number of S2 context banks!\n"

L_.str.15:                              ## @.str.15
	.asciz	"\t%u context banks (%u stage-2 only)\n"

	.comm	_ARM_SMMU_GR0_ID2,4,2           ## @ARM_SMMU_GR0_ID2
	.comm	_ID2_IAS,4,2                    ## @ID2_IAS
	.comm	_ID2_OAS,4,2                    ## @ID2_OAS
	.comm	_ID2_VMID16,4,2                 ## @ID2_VMID16
	.comm	_ARM_SMMU_FEAT_VMID16,4,2       ## @ARM_SMMU_FEAT_VMID16
L_.str.16:                              ## @.str.16
	.asciz	"failed to set DMA mask for table walker\n"

	.comm	_ARM_SMMU_V1_64K,8,3            ## @ARM_SMMU_V1_64K
	.comm	_ARM_SMMU_FEAT_FMT_AARCH64_64K,4,2 ## @ARM_SMMU_FEAT_FMT_AARCH64_64K
	.comm	_ID2_UBS,4,2                    ## @ID2_UBS
	.comm	_ID2_PTFS_4K,4,2                ## @ID2_PTFS_4K
	.comm	_ARM_SMMU_FEAT_FMT_AARCH64_4K,4,2 ## @ARM_SMMU_FEAT_FMT_AARCH64_4K
	.comm	_ID2_PTFS_16K,4,2               ## @ID2_PTFS_16K
	.comm	_ARM_SMMU_FEAT_FMT_AARCH64_16K,4,2 ## @ARM_SMMU_FEAT_FMT_AARCH64_16K
	.comm	_ID2_PTFS_64K,4,2               ## @ID2_PTFS_64K
	.comm	_SZ_4K,4,2                      ## @SZ_4K
	.comm	_SZ_64K,4,2                     ## @SZ_64K
	.comm	_SZ_1M,4,2                      ## @SZ_1M
	.comm	_SZ_16M,4,2                     ## @SZ_16M
	.comm	_SZ_2M,4,2                      ## @SZ_2M
	.comm	_SZ_1G,4,2                      ## @SZ_1G
	.comm	_SZ_16K,4,2                     ## @SZ_16K
	.comm	_SZ_32M,4,2                     ## @SZ_32M
	.comm	_SZ_512M,4,2                    ## @SZ_512M
	.comm	_arm_smmu_ops,8,3               ## @arm_smmu_ops
L_.str.17:                              ## @.str.17
	.asciz	"\tSupported page sizes: 0x%08lx\n"

L_.str.18:                              ## @.str.18
	.asciz	"\tStage-1: %lu-bit VA -> %lu-bit IPA\n"

L_.str.19:                              ## @.str.19
	.asciz	"\tStage-2: %lu-bit IPA -> %lu-bit PA\n"

	.no_dead_strip	_arm_smmu_device_cfg_probe
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function arm_smmu_device_cfg_probe
_arm_smmu_device_cfg_probe:             ; @arm_smmu_device_cfg_probe
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	w21, [x0]
Lloh0:
	adrp	x8, _ARM_SMMU_FEAT_COHERENT_WALK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _ARM_SMMU_FEAT_COHERENT_WALK@GOTPAGEOFF]
Lloh2:
	ldr	w25, [x8]
	ldr	w0, [x0, #64]
Lloh3:
	adrp	x1, l_.str@PAGE
Lloh4:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_notice
	ldr	w0, [x19, #64]
	ldr	x8, [x19, #8]
Lloh5:
	adrp	x24, _ARM_SMMU_V2@GOTPAGE
Lloh6:
	ldr	x24, [x24, _ARM_SMMU_V2@GOTPAGEOFF]
	ldr	x9, [x24]
	cmp	x8, x9
	mov	w8, #1
	cinc	x8, x8, eq
	str	x8, [sp]
Lloh7:
	adrp	x1, l_.str.1@PAGE
Lloh8:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_notice
Lloh9:
	adrp	x8, _ARM_SMMU_GR0_ID0@GOTPAGE
Lloh10:
	ldr	x8, [x8, _ARM_SMMU_GR0_ID0@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_arm_smmu_gr0_read
	mov	x20, x0
Lloh12:
	adrp	x8, _force_stage@GOTPAGE
Lloh13:
	ldr	x8, [x8, _force_stage@GOTPAGEOFF]
Lloh14:
	adrp	x22, _ID0_S2TS@GOTPAGE
Lloh15:
	ldr	x22, [x22, _ID0_S2TS@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
Lloh17:
	adrp	x27, _ID0_NTS@GOTPAGE
Lloh18:
	ldr	x27, [x27, _ID0_NTS@GOTPAGEOFF]
Lloh19:
	adrp	x26, _ID0_S1TS@GOTPAGE
Lloh20:
	ldr	x26, [x26, _ID0_S1TS@GOTPAGEOFF]
	cmp	w8, #2
	b.eq	LBB0_3
; %bb.1:
	cmp	w8, #1
	b.ne	LBB0_5
; %bb.2:
	ldr	w8, [x22]
	b	LBB0_4
LBB0_3:
	ldr	w8, [x26]
LBB0_4:
	ldr	w9, [x27]
	orr	w8, w9, w8
	bic	w20, w20, w8
LBB0_5:
	ldr	w8, [x26]
Lloh21:
	adrp	x23, _ARM_SMMU_FEAT_TRANS_S1@GOTPAGE
Lloh22:
	ldr	x23, [x23, _ARM_SMMU_FEAT_TRANS_S1@GOTPAGEOFF]
	tst	w8, w20
	b.eq	LBB0_7
; %bb.6:
	ldr	w8, [x23]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
	ldr	w0, [x19, #64]
Lloh23:
	adrp	x1, l_.str.2@PAGE
Lloh24:
	add	x1, x1, l_.str.2@PAGEOFF
	bl	_dev_notice
LBB0_7:
	ldr	w8, [x22]
Lloh25:
	adrp	x22, _ARM_SMMU_FEAT_TRANS_S2@GOTPAGE
Lloh26:
	ldr	x22, [x22, _ARM_SMMU_FEAT_TRANS_S2@GOTPAGEOFF]
	tst	w8, w20
	b.eq	LBB0_9
; %bb.8:
	ldr	w8, [x22]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
	ldr	w0, [x19, #64]
Lloh27:
	adrp	x1, l_.str.3@PAGE
Lloh28:
	add	x1, x1, l_.str.3@PAGEOFF
	bl	_dev_notice
LBB0_9:
	ldr	w8, [x27]
	tst	w8, w20
	b.eq	LBB0_11
; %bb.10:
Lloh29:
	adrp	x8, _ARM_SMMU_FEAT_TRANS_NESTED@GOTPAGE
Lloh30:
	ldr	x8, [x8, _ARM_SMMU_FEAT_TRANS_NESTED@GOTPAGEOFF]
Lloh31:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
	ldr	w0, [x19, #64]
Lloh32:
	adrp	x1, l_.str.4@PAGE
Lloh33:
	add	x1, x1, l_.str.4@PAGEOFF
	bl	_dev_notice
LBB0_11:
	ldr	w8, [x19]
	ldr	w9, [x23]
	ldr	w10, [x22]
	orr	w9, w10, w9
	tst	w9, w8
	b.eq	LBB0_43
; %bb.12:
	and	w21, w25, w21
	ldr	w9, [x26]
	tst	w9, w20
	b.eq	LBB0_16
; %bb.13:
	ldr	x9, [x19, #8]
	ldr	x10, [x24]
	cmp	x9, x10
	b.lt	LBB0_15
; %bb.14:
Lloh34:
	adrp	x9, _ID0_ATOSNS@GOTPAGE
Lloh35:
	ldr	x9, [x9, _ID0_ATOSNS@GOTPAGEOFF]
Lloh36:
	ldr	w9, [x9]
	tst	w9, w20
	b.ne	LBB0_16
LBB0_15:
Lloh37:
	adrp	x9, _ARM_SMMU_FEAT_TRANS_OPS@GOTPAGE
Lloh38:
	ldr	x9, [x9, _ARM_SMMU_FEAT_TRANS_OPS@GOTPAGEOFF]
Lloh39:
	ldr	w9, [x9]
	orr	w8, w9, w8
	str	w8, [x19]
	ldr	w0, [x19, #64]
Lloh40:
	adrp	x1, l_.str.6@PAGE
Lloh41:
	add	x1, x1, l_.str.6@PAGEOFF
	bl	_dev_notice
LBB0_16:
Lloh42:
	adrp	x8, _ID0_CTTW@GOTPAGE
Lloh43:
	ldr	x8, [x8, _ID0_CTTW@GOTPAGEOFF]
Lloh44:
	ldr	w8, [x8]
	ands	w8, w8, w20
	cset	w25, ne
	orr	w8, w21, w8
	cbz	w8, LBB0_18
; %bb.17:
	ldr	w0, [x19, #64]
Lloh45:
	adrp	x8, l_.str.9@PAGE
Lloh46:
	add	x8, x8, l_.str.9@PAGEOFF
Lloh47:
	adrp	x9, l_.str.8@PAGE
Lloh48:
	add	x9, x9, l_.str.8@PAGEOFF
	cmp	w21, #0
	csel	x8, x9, x8, ne
	str	x8, [sp]
Lloh49:
	adrp	x1, l_.str.7@PAGE
Lloh50:
	add	x1, x1, l_.str.7@PAGEOFF
	bl	_dev_notice
LBB0_18:
	cmp	w21, w25
	b.eq	LBB0_20
; %bb.19:
	ldr	w0, [x19, #64]
Lloh51:
	adrp	x1, l_.str.10@PAGE
Lloh52:
	add	x1, x1, l_.str.10@PAGEOFF
	bl	_dev_notice
LBB0_20:
	ldr	x8, [x19, #8]
	ldr	x9, [x24]
	cmp	x8, x9
	b.ne	LBB0_23
; %bb.21:
Lloh53:
	adrp	x8, _ID0_EXIDS@GOTPAGE
Lloh54:
	ldr	x8, [x8, _ID0_EXIDS@GOTPAGEOFF]
Lloh55:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_23
; %bb.22:
Lloh56:
	adrp	x8, _ARM_SMMU_FEAT_EXIDS@GOTPAGE
Lloh57:
	ldr	x8, [x8, _ARM_SMMU_FEAT_EXIDS@GOTPAGEOFF]
Lloh58:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
	mov	w21, #65536
	b	LBB0_24
LBB0_23:
Lloh59:
	adrp	x8, _ID0_NUMSIDB@GOTPAGE
Lloh60:
	ldr	x8, [x8, _ID0_NUMSIDB@GOTPAGEOFF]
Lloh61:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_FIELD_GET
	mov	w8, #1
	lsl	w21, w8, w0
LBB0_24:
	sub	w8, w21, #1
	str	w8, [x19, #16]
Lloh62:
	adrp	x8, _ID0_SMS@GOTPAGE
Lloh63:
	ldr	x8, [x8, _ID0_SMS@GOTPAGEOFF]
Lloh64:
	ldr	w8, [x8]
Lloh65:
	adrp	x26, _GFP_KERNEL@GOTPAGE
Lloh66:
	ldr	x26, [x26, _GFP_KERNEL@GOTPAGEOFF]
	tst	w8, w20
	b.eq	LBB0_28
; %bb.25:
Lloh67:
	adrp	x8, _ARM_SMMU_FEAT_STREAM_MATCH@GOTPAGE
Lloh68:
	ldr	x8, [x8, _ARM_SMMU_FEAT_STREAM_MATCH@GOTPAGEOFF]
Lloh69:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
Lloh70:
	adrp	x8, _ID0_NUMSMRG@GOTPAGE
Lloh71:
	ldr	x8, [x8, _ID0_NUMSMRG@GOTPAGEOFF]
Lloh72:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_FIELD_GET
	mov	x21, x0
	ldr	w0, [x19, #64]
	cbz	w21, LBB0_44
; %bb.26:
	ldr	w3, [x26]
	mov	x1, x21
	mov	w2, #1
	bl	_devm_kcalloc
	str	x0, [x19, #96]
	cbz	x0, LBB0_53
; %bb.27:
	ldr	w0, [x19, #64]
	str	x21, [sp]
Lloh73:
	adrp	x1, l_.str.12@PAGE
Lloh74:
	add	x1, x1, l_.str.12@PAGEOFF
	bl	_dev_notice
LBB0_28:
	ldr	w0, [x19, #64]
	ldr	w3, [x26]
	mov	x1, x21
	mov	w2, #4
	bl	_devm_kmalloc_array
	str	x0, [x19, #88]
	cbz	x0, LBB0_53
; %bb.29:
	cmp	w21, #1
	csinc	w9, w21, wzr, hi
Lloh75:
	adrp	x8, _s2cr_init_val@GOTPAGE
Lloh76:
	ldr	x8, [x8, _s2cr_init_val@GOTPAGEOFF]
	cmp	w9, #16
	b.lo	LBB0_32
; %bb.30:
	add	x10, x8, #4
	cmp	x0, x10
	b.hs	LBB0_56
; %bb.31:
	add	x10, x0, x9, lsl #2
	cmp	x10, x8
	b.ls	LBB0_56
LBB0_32:
	mov	x10, #0
LBB0_33:
	add	x11, x0, x10, lsl #2
	sub	x9, x9, x10
LBB0_34:                                ; =>This Inner Loop Header: Depth=1
	ldr	w10, [x8]
	str	w10, [x11], #4
	subs	x9, x9, #1
	b.ne	LBB0_34
LBB0_35:
	str	w21, [x19, #20]
	add	x0, x19, #84
	bl	_mutex_init
	add	x0, x19, #80
	bl	_spin_lock_init
	ldr	x8, [x19, #8]
	ldr	x9, [x24]
Lloh77:
	adrp	x25, _ARM_SMMU_FEAT_FMT_AARCH32_L@GOTPAGE
Lloh78:
	ldr	x25, [x25, _ARM_SMMU_FEAT_FMT_AARCH32_L@GOTPAGEOFF]
	cmp	x8, x9
	b.lt	LBB0_37
; %bb.36:
Lloh79:
	adrp	x8, _ID0_PTFS_NO_AARCH32@GOTPAGE
Lloh80:
	ldr	x8, [x8, _ID0_PTFS_NO_AARCH32@GOTPAGEOFF]
Lloh81:
	ldr	w8, [x8]
	tst	w8, w20
	b.ne	LBB0_39
LBB0_37:
	ldr	w8, [x25]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
Lloh82:
	adrp	x9, _ID0_PTFS_NO_AARCH32S@GOTPAGE
Lloh83:
	ldr	x9, [x9, _ID0_PTFS_NO_AARCH32S@GOTPAGEOFF]
Lloh84:
	ldr	w9, [x9]
	tst	w9, w20
	b.ne	LBB0_39
; %bb.38:
Lloh85:
	adrp	x9, _ARM_SMMU_FEAT_FMT_AARCH32_S@GOTPAGE
Lloh86:
	ldr	x9, [x9, _ARM_SMMU_FEAT_FMT_AARCH32_S@GOTPAGEOFF]
Lloh87:
	ldr	w9, [x9]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_39:
Lloh88:
	adrp	x8, _ARM_SMMU_GR0_ID1@GOTPAGE
Lloh89:
	ldr	x8, [x8, _ARM_SMMU_GR0_ID1@GOTPAGEOFF]
Lloh90:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_arm_smmu_gr0_read
	mov	x20, x0
Lloh91:
	adrp	x8, _ID1_PAGESIZE@GOTPAGE
Lloh92:
	ldr	x8, [x8, _ID1_PAGESIZE@GOTPAGEOFF]
Lloh93:
	ldr	w8, [x8]
	tst	w8, w0
	mov	w8, #16
	mov	w9, #12
	csel	w8, w9, w8, eq
	str	w8, [x19, #24]
Lloh94:
	adrp	x8, _ID1_NUMPAGENDXB@GOTPAGE
Lloh95:
	ldr	x8, [x8, _ID1_NUMPAGENDXB@GOTPAGEOFF]
Lloh96:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_FIELD_GET
	add	w8, w0, #1
	mov	w9, #1
	lsl	w21, w9, w8
	lsl	w9, w21, #1
	ldp	w10, w8, [x19, #24]
	lsl	w9, w9, w10
	cmp	w8, w9
	b.eq	LBB0_41
; %bb.40:
	ldr	w0, [x19, #64]
	stp	x9, x8, [sp]
Lloh97:
	adrp	x1, l_.str.13@PAGE
Lloh98:
	add	x1, x1, l_.str.13@PAGEOFF
	bl	_dev_warn
LBB0_41:
	str	w21, [x19, #28]
Lloh99:
	adrp	x8, _ID1_NUMS2CB@GOTPAGE
Lloh100:
	ldr	x8, [x8, _ID1_NUMS2CB@GOTPAGEOFF]
Lloh101:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_FIELD_GET
	str	w0, [x19, #32]
Lloh102:
	adrp	x8, _ID1_NUMCB@GOTPAGE
Lloh103:
	ldr	x8, [x8, _ID1_NUMCB@GOTPAGEOFF]
Lloh104:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_FIELD_GET
	mov	x8, x0
	str	w0, [x19, #36]
	ldr	w9, [x19, #32]
	ldr	w0, [x19, #64]
	cmp	w9, w8
	b.ls	LBB0_46
; %bb.42:
Lloh105:
	adrp	x1, l_.str.14@PAGE
Lloh106:
	add	x1, x1, l_.str.14@PAGEOFF
	b	LBB0_45
LBB0_43:
	ldr	w0, [x19, #64]
Lloh107:
	adrp	x1, l_.str.5@PAGE
Lloh108:
	add	x1, x1, l_.str.5@PAGEOFF
	b	LBB0_45
LBB0_44:
Lloh109:
	adrp	x1, l_.str.11@PAGE
Lloh110:
	add	x1, x1, l_.str.11@PAGEOFF
LBB0_45:
	bl	_dev_err
Lloh111:
	adrp	x8, _ENODEV@GOTPAGE
Lloh112:
	ldr	x8, [x8, _ENODEV@GOTPAGEOFF]
	b	LBB0_54
LBB0_46:
	stp	x8, x9, [sp]
Lloh113:
	adrp	x1, l_.str.15@PAGE
Lloh114:
	add	x1, x1, l_.str.15@PAGEOFF
	bl	_dev_notice
	ldr	w0, [x19, #64]
	ldr	w1, [x19, #36]
	ldr	w3, [x26]
	mov	w2, #1
	bl	_devm_kcalloc
	str	x0, [x19, #72]
	cbz	x0, LBB0_53
; %bb.47:
Lloh115:
	adrp	x8, _ARM_SMMU_GR0_ID2@GOTPAGE
Lloh116:
	ldr	x8, [x8, _ARM_SMMU_GR0_ID2@GOTPAGEOFF]
Lloh117:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_arm_smmu_gr0_read
	mov	x20, x0
Lloh118:
	adrp	x8, _ID2_IAS@GOTPAGE
Lloh119:
	ldr	x8, [x8, _ID2_IAS@GOTPAGEOFF]
Lloh120:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_FIELD_GET
	bl	_arm_smmu_id_size_to_bits
	str	w0, [x19, #40]
Lloh121:
	adrp	x8, _ID2_OAS@GOTPAGE
Lloh122:
	ldr	x8, [x8, _ID2_OAS@GOTPAGEOFF]
Lloh123:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_FIELD_GET
	bl	_arm_smmu_id_size_to_bits
	str	w0, [x19, #44]
Lloh124:
	adrp	x8, _ID2_VMID16@GOTPAGE
Lloh125:
	ldr	x8, [x8, _ID2_VMID16@GOTPAGEOFF]
Lloh126:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_49
; %bb.48:
Lloh127:
	adrp	x8, _ARM_SMMU_FEAT_VMID16@GOTPAGE
Lloh128:
	ldr	x8, [x8, _ARM_SMMU_FEAT_VMID16@GOTPAGEOFF]
Lloh129:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_49:
	ldr	w21, [x19, #64]
                                        ; kill: def $w0 killed $w0 killed $x0
	bl	_DMA_BIT_MASK
	mov	x1, x0
	mov	x0, x21
	bl	_dma_set_mask_and_coherent
	cbz	x0, LBB0_51
; %bb.50:
	ldr	w0, [x19, #64]
Lloh130:
	adrp	x1, l_.str.16@PAGE
Lloh131:
	add	x1, x1, l_.str.16@PAGEOFF
	bl	_dev_warn
LBB0_51:
	ldr	x8, [x19, #8]
Lloh132:
	adrp	x26, _ARM_SMMU_FEAT_FMT_AARCH64_4K@GOTPAGE
Lloh133:
	ldr	x26, [x26, _ARM_SMMU_FEAT_FMT_AARCH64_4K@GOTPAGEOFF]
	ldr	x9, [x24]
Lloh134:
	adrp	x24, _ARM_SMMU_FEAT_FMT_AARCH64_16K@GOTPAGE
Lloh135:
	ldr	x24, [x24, _ARM_SMMU_FEAT_FMT_AARCH64_16K@GOTPAGEOFF]
Lloh136:
	adrp	x21, _ARM_SMMU_FEAT_FMT_AARCH64_64K@GOTPAGE
Lloh137:
	ldr	x21, [x21, _ARM_SMMU_FEAT_FMT_AARCH64_64K@GOTPAGEOFF]
	cmp	x8, x9
	b.ge	LBB0_59
; %bb.52:
	ldr	w9, [x19, #40]
	str	w9, [x19, #48]
Lloh138:
	adrp	x9, _ARM_SMMU_V1_64K@GOTPAGE
Lloh139:
	ldr	x9, [x9, _ARM_SMMU_V1_64K@GOTPAGEOFF]
Lloh140:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_64
	b	LBB0_65
LBB0_53:
Lloh141:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh142:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
LBB0_54:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_55:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
LBB0_56:
	and	x10, x9, #0xfffffff0
	ld1r.4s	{ v0 }, [x8]
	add	x11, x0, #32
	mov	x12, x10
LBB0_57:                                ; =>This Inner Loop Header: Depth=1
	stp	q0, q0, [x11, #-32]
	stp	q0, q0, [x11], #64
	subs	x12, x12, #16
	b.ne	LBB0_57
; %bb.58:
	cmp	x10, x9
	b.eq	LBB0_35
	b	LBB0_33
LBB0_59:
Lloh143:
	adrp	x8, _ID2_UBS@GOTPAGE
Lloh144:
	ldr	x8, [x8, _ID2_UBS@GOTPAGEOFF]
Lloh145:
	ldr	w0, [x8]
	mov	x1, x20
	bl	_FIELD_GET
	bl	_arm_smmu_id_size_to_bits
	str	w0, [x19, #48]
Lloh146:
	adrp	x8, _ID2_PTFS_4K@GOTPAGE
Lloh147:
	ldr	x8, [x8, _ID2_PTFS_4K@GOTPAGEOFF]
Lloh148:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_61
; %bb.60:
	ldr	w8, [x26]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_61:
Lloh149:
	adrp	x8, _ID2_PTFS_16K@GOTPAGE
Lloh150:
	ldr	x8, [x8, _ID2_PTFS_16K@GOTPAGEOFF]
Lloh151:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_63
; %bb.62:
	ldr	w8, [x24]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_63:
Lloh152:
	adrp	x8, _ID2_PTFS_64K@GOTPAGE
Lloh153:
	ldr	x8, [x8, _ID2_PTFS_64K@GOTPAGEOFF]
Lloh154:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_65
LBB0_64:
	ldr	w8, [x21]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_65:
	ldr	w9, [x19]
Lloh155:
	adrp	x8, _ARM_SMMU_FEAT_FMT_AARCH32_S@GOTPAGE
Lloh156:
	ldr	x8, [x8, _ARM_SMMU_FEAT_FMT_AARCH32_S@GOTPAGEOFF]
Lloh157:
	ldr	w11, [x8]
Lloh158:
	adrp	x10, _SZ_4K@GOTPAGE
Lloh159:
	ldr	x10, [x10, _SZ_4K@GOTPAGEOFF]
Lloh160:
	adrp	x8, _SZ_64K@GOTPAGE
Lloh161:
	ldr	x8, [x8, _SZ_64K@GOTPAGEOFF]
	tst	w11, w9
	b.eq	LBB0_67
; %bb.66:
	ldr	w11, [x10]
	ldr	w12, [x8]
	orr	w11, w12, w11
Lloh162:
	adrp	x12, _SZ_1M@GOTPAGE
Lloh163:
	ldr	x12, [x12, _SZ_1M@GOTPAGEOFF]
Lloh164:
	ldr	w12, [x12]
Lloh165:
	adrp	x13, _SZ_16M@GOTPAGE
Lloh166:
	ldr	x13, [x13, _SZ_16M@GOTPAGEOFF]
	orr	w11, w11, w12
Lloh167:
	ldr	w12, [x13]
	orr	w11, w11, w12
	ldr	w12, [x19, #52]
	orr	w11, w11, w12
	str	w11, [x19, #52]
LBB0_67:
	ldr	w11, [x25]
	ldr	w12, [x26]
	orr	w11, w12, w11
	tst	w11, w9
	b.eq	LBB0_69
; %bb.68:
	ldr	w10, [x10]
Lloh168:
	adrp	x11, _SZ_2M@GOTPAGE
Lloh169:
	ldr	x11, [x11, _SZ_2M@GOTPAGEOFF]
Lloh170:
	ldr	w11, [x11]
Lloh171:
	adrp	x12, _SZ_1G@GOTPAGE
Lloh172:
	ldr	x12, [x12, _SZ_1G@GOTPAGEOFF]
	orr	w10, w11, w10
Lloh173:
	ldr	w11, [x12]
	orr	w10, w10, w11
	ldr	w11, [x19, #52]
	orr	w10, w10, w11
	str	w10, [x19, #52]
LBB0_69:
	ldr	w10, [x24]
	tst	w10, w9
	b.eq	LBB0_71
; %bb.70:
Lloh174:
	adrp	x10, _SZ_16K@GOTPAGE
Lloh175:
	ldr	x10, [x10, _SZ_16K@GOTPAGEOFF]
Lloh176:
	adrp	x11, _SZ_32M@GOTPAGE
Lloh177:
	ldr	x11, [x11, _SZ_32M@GOTPAGEOFF]
Lloh178:
	ldr	w10, [x10]
Lloh179:
	ldr	w11, [x11]
	orr	w10, w11, w10
	ldr	w11, [x19, #52]
	orr	w10, w10, w11
	str	w10, [x19, #52]
LBB0_71:
	ldr	w10, [x21]
	tst	w10, w9
	b.eq	LBB0_73
; %bb.72:
Lloh180:
	adrp	x9, _SZ_512M@GOTPAGE
Lloh181:
	ldr	x9, [x9, _SZ_512M@GOTPAGEOFF]
	ldr	w8, [x8]
Lloh182:
	ldr	w9, [x9]
	orr	w8, w9, w8
	ldr	w9, [x19, #52]
	orr	w8, w8, w9
	str	w8, [x19, #52]
LBB0_73:
Lloh183:
	adrp	x8, _arm_smmu_ops@GOTPAGE
Lloh184:
	ldr	x8, [x8, _arm_smmu_ops@GOTPAGEOFF]
	ldr	x9, [x8]
	ldrsw	x10, [x19, #52]
	cmn	x9, #1
	csel	x9, xzr, x9, eq
	orr	x9, x9, x10
	str	x9, [x8]
	ldr	w0, [x19, #64]
	str	x10, [sp]
Lloh185:
	adrp	x1, l_.str.17@PAGE
Lloh186:
	add	x1, x1, l_.str.17@PAGEOFF
	bl	_dev_notice
	ldr	w8, [x19]
	ldr	w9, [x23]
	tst	w9, w8
	b.eq	LBB0_75
; %bb.74:
	ldr	w0, [x19, #64]
	ldr	w8, [x19, #48]
	ldr	w9, [x19, #40]
	stp	x8, x9, [sp]
Lloh187:
	adrp	x1, l_.str.18@PAGE
Lloh188:
	add	x1, x1, l_.str.18@PAGEOFF
	bl	_dev_notice
	ldr	w8, [x19]
LBB0_75:
	ldr	w9, [x22]
	tst	w9, w8
	b.eq	LBB0_77
; %bb.76:
	ldr	w0, [x19, #64]
	ldp	w8, w9, [x19, #40]
	stp	x8, x9, [sp]
Lloh189:
	adrp	x1, l_.str.19@PAGE
Lloh190:
	add	x1, x1, l_.str.19@PAGEOFF
	bl	_dev_notice
LBB0_77:
	ldr	x8, [x19, #56]
	cbz	x8, LBB0_80
; %bb.78:
	ldr	x1, [x8]
	cbz	x1, LBB0_80
; %bb.79:
	mov	x0, x19
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	br	x1
LBB0_80:
	mov	w0, #0
	b	LBB0_55
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh16
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpAdd	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpAdd	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpAdd	Lloh27, Lloh28
	.loh AdrpAdd	Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpAdd	Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpAdd	Lloh49, Lloh50
	.loh AdrpAdd	Lloh47, Lloh48
	.loh AdrpAdd	Lloh45, Lloh46
	.loh AdrpAdd	Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpAdd	Lloh73, Lloh74
	.loh AdrpLdrGot	Lloh75, Lloh76
	.loh AdrpLdrGot	Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpAdd	Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpAdd	Lloh105, Lloh106
	.loh AdrpAdd	Lloh107, Lloh108
	.loh AdrpAdd	Lloh109, Lloh110
	.loh AdrpLdrGot	Lloh111, Lloh112
	.loh AdrpAdd	Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.loh AdrpLdrGotLdr	Lloh127, Lloh128, Lloh129
	.loh AdrpAdd	Lloh130, Lloh131
	.loh AdrpLdrGot	Lloh136, Lloh137
	.loh AdrpLdrGot	Lloh134, Lloh135
	.loh AdrpLdrGot	Lloh132, Lloh133
	.loh AdrpLdrGotLdr	Lloh138, Lloh139, Lloh140
	.loh AdrpLdrGot	Lloh141, Lloh142
	.loh AdrpLdrGotLdr	Lloh146, Lloh147, Lloh148
	.loh AdrpLdrGotLdr	Lloh143, Lloh144, Lloh145
	.loh AdrpLdrGotLdr	Lloh149, Lloh150, Lloh151
	.loh AdrpLdrGotLdr	Lloh152, Lloh153, Lloh154
	.loh AdrpLdrGot	Lloh160, Lloh161
	.loh AdrpLdrGot	Lloh158, Lloh159
	.loh AdrpLdrGotLdr	Lloh155, Lloh156, Lloh157
	.loh AdrpLdrGotLdr	Lloh165, Lloh166, Lloh167
	.loh AdrpLdrGotLdr	Lloh162, Lloh163, Lloh164
	.loh AdrpLdrGotLdr	Lloh171, Lloh172, Lloh173
	.loh AdrpLdrGotLdr	Lloh168, Lloh169, Lloh170
	.loh AdrpLdrGotLdr	Lloh176, Lloh177, Lloh179
	.loh AdrpLdrGotLdr	Lloh174, Lloh175, Lloh178
	.loh AdrpLdrGotLdr	Lloh180, Lloh181, Lloh182
	.loh AdrpAdd	Lloh185, Lloh186
	.loh AdrpLdrGot	Lloh183, Lloh184
	.loh AdrpAdd	Lloh187, Lloh188
	.loh AdrpAdd	Lloh189, Lloh190
	.cfi_endproc
                                        ; -- End function
	.comm	_ARM_SMMU_FEAT_COHERENT_WALK,4,2 ; @ARM_SMMU_FEAT_COHERENT_WALK
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"probing hardware configuration...\n"

l_.str.1:                               ; @.str.1
	.asciz	"SMMUv%d with:\n"

	.comm	_ARM_SMMU_V2,8,3                ; @ARM_SMMU_V2
	.comm	_ARM_SMMU_GR0_ID0,4,2           ; @ARM_SMMU_GR0_ID0
	.comm	_force_stage,4,2                ; @force_stage
	.comm	_ID0_S2TS,4,2                   ; @ID0_S2TS
	.comm	_ID0_NTS,4,2                    ; @ID0_NTS
	.comm	_ID0_S1TS,4,2                   ; @ID0_S1TS
	.comm	_ARM_SMMU_FEAT_TRANS_S1,4,2     ; @ARM_SMMU_FEAT_TRANS_S1
l_.str.2:                               ; @.str.2
	.asciz	"\tstage 1 translation\n"

	.comm	_ARM_SMMU_FEAT_TRANS_S2,4,2     ; @ARM_SMMU_FEAT_TRANS_S2
l_.str.3:                               ; @.str.3
	.asciz	"\tstage 2 translation\n"

	.comm	_ARM_SMMU_FEAT_TRANS_NESTED,4,2 ; @ARM_SMMU_FEAT_TRANS_NESTED
l_.str.4:                               ; @.str.4
	.asciz	"\tnested translation\n"

l_.str.5:                               ; @.str.5
	.asciz	"\tno translation support!\n"

	.comm	_ENODEV,4,2                     ; @ENODEV
	.comm	_ID0_ATOSNS,4,2                 ; @ID0_ATOSNS
	.comm	_ARM_SMMU_FEAT_TRANS_OPS,4,2    ; @ARM_SMMU_FEAT_TRANS_OPS
l_.str.6:                               ; @.str.6
	.asciz	"\taddress translation ops\n"

	.comm	_ID0_CTTW,4,2                   ; @ID0_CTTW
l_.str.7:                               ; @.str.7
	.asciz	"\t%scoherent table walk\n"

l_.str.8:                               ; @.str.8
	.space	1

l_.str.9:                               ; @.str.9
	.asciz	"non-"

l_.str.10:                              ; @.str.10
	.asciz	"\t(IDR0.CTTW overridden by FW configuration)\n"

	.comm	_ID0_EXIDS,4,2                  ; @ID0_EXIDS
	.comm	_ARM_SMMU_FEAT_EXIDS,4,2        ; @ARM_SMMU_FEAT_EXIDS
	.comm	_ID0_NUMSIDB,4,2                ; @ID0_NUMSIDB
	.comm	_ID0_SMS,4,2                    ; @ID0_SMS
	.comm	_ARM_SMMU_FEAT_STREAM_MATCH,4,2 ; @ARM_SMMU_FEAT_STREAM_MATCH
	.comm	_ID0_NUMSMRG,4,2                ; @ID0_NUMSMRG
l_.str.11:                              ; @.str.11
	.asciz	"stream-matching supported, but no SMRs present!\n"

	.comm	_GFP_KERNEL,4,2                 ; @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ; @ENOMEM
l_.str.12:                              ; @.str.12
	.asciz	"\tstream matching with %u register groups"

	.comm	_s2cr_init_val,4,2              ; @s2cr_init_val
	.comm	_ID0_PTFS_NO_AARCH32,4,2        ; @ID0_PTFS_NO_AARCH32
	.comm	_ARM_SMMU_FEAT_FMT_AARCH32_L,4,2 ; @ARM_SMMU_FEAT_FMT_AARCH32_L
	.comm	_ID0_PTFS_NO_AARCH32S,4,2       ; @ID0_PTFS_NO_AARCH32S
	.comm	_ARM_SMMU_FEAT_FMT_AARCH32_S,4,2 ; @ARM_SMMU_FEAT_FMT_AARCH32_S
	.comm	_ARM_SMMU_GR0_ID1,4,2           ; @ARM_SMMU_GR0_ID1
	.comm	_ID1_PAGESIZE,4,2               ; @ID1_PAGESIZE
	.comm	_ID1_NUMPAGENDXB,4,2            ; @ID1_NUMPAGENDXB
l_.str.13:                              ; @.str.13
	.asciz	"SMMU address space size (0x%x) differs from mapped region size (0x%x)!\n"

	.comm	_ID1_NUMS2CB,4,2                ; @ID1_NUMS2CB
	.comm	_ID1_NUMCB,4,2                  ; @ID1_NUMCB
l_.str.14:                              ; @.str.14
	.asciz	"impossible number of S2 context banks!\n"

l_.str.15:                              ; @.str.15
	.asciz	"\t%u context banks (%u stage-2 only)\n"

	.comm	_ARM_SMMU_GR0_ID2,4,2           ; @ARM_SMMU_GR0_ID2
	.comm	_ID2_IAS,4,2                    ; @ID2_IAS
	.comm	_ID2_OAS,4,2                    ; @ID2_OAS
	.comm	_ID2_VMID16,4,2                 ; @ID2_VMID16
	.comm	_ARM_SMMU_FEAT_VMID16,4,2       ; @ARM_SMMU_FEAT_VMID16
l_.str.16:                              ; @.str.16
	.asciz	"failed to set DMA mask for table walker\n"

	.comm	_ARM_SMMU_V1_64K,8,3            ; @ARM_SMMU_V1_64K
	.comm	_ARM_SMMU_FEAT_FMT_AARCH64_64K,4,2 ; @ARM_SMMU_FEAT_FMT_AARCH64_64K
	.comm	_ID2_UBS,4,2                    ; @ID2_UBS
	.comm	_ID2_PTFS_4K,4,2                ; @ID2_PTFS_4K
	.comm	_ARM_SMMU_FEAT_FMT_AARCH64_4K,4,2 ; @ARM_SMMU_FEAT_FMT_AARCH64_4K
	.comm	_ID2_PTFS_16K,4,2               ; @ID2_PTFS_16K
	.comm	_ARM_SMMU_FEAT_FMT_AARCH64_16K,4,2 ; @ARM_SMMU_FEAT_FMT_AARCH64_16K
	.comm	_ID2_PTFS_64K,4,2               ; @ID2_PTFS_64K
	.comm	_SZ_4K,4,2                      ; @SZ_4K
	.comm	_SZ_64K,4,2                     ; @SZ_64K
	.comm	_SZ_1M,4,2                      ; @SZ_1M
	.comm	_SZ_16M,4,2                     ; @SZ_16M
	.comm	_SZ_2M,4,2                      ; @SZ_2M
	.comm	_SZ_1G,4,2                      ; @SZ_1G
	.comm	_SZ_16K,4,2                     ; @SZ_16K
	.comm	_SZ_32M,4,2                     ; @SZ_32M
	.comm	_SZ_512M,4,2                    ; @SZ_512M
	.comm	_arm_smmu_ops,8,3               ; @arm_smmu_ops
l_.str.17:                              ; @.str.17
	.asciz	"\tSupported page sizes: 0x%08lx\n"

l_.str.18:                              ; @.str.18
	.asciz	"\tStage-1: %lu-bit VA -> %lu-bit IPA\n"

l_.str.19:                              ; @.str.19
	.asciz	"\tStage-2: %lu-bit IPA -> %lu-bit PA\n"

	.no_dead_strip	_arm_smmu_device_cfg_probe
.subsections_via_symbols
