	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function bnx2x_hw_enable_status
_bnx2x_hw_enable_status:                ## @bnx2x_hw_enable_status
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	movq	_CFC_REG_WEAK_ENABLE_PF@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_REG_RD
	movq	_BNX2X_MSG_SP@GOTPCREL(%rip), %r14
	movl	(%r14), %edi
	leaq	L_.str(%rip), %rsi
	movl	%eax, %edx
	callq	_DP
	movq	_PBF_REG_DISABLE_PF@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_REG_RD
	movl	(%r14), %edi
	leaq	L_.str.1(%rip), %rsi
	movl	%eax, %edx
	callq	_DP
	movq	_IGU_REG_PCI_PF_MSI_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_REG_RD
	movl	(%r14), %edi
	leaq	L_.str.2(%rip), %rsi
	movl	%eax, %edx
	callq	_DP
	movq	_IGU_REG_PCI_PF_MSIX_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_REG_RD
	movl	(%r14), %edi
	leaq	L_.str.3(%rip), %rsi
	movl	%eax, %edx
	callq	_DP
	movq	_IGU_REG_PCI_PF_MSIX_FUNC_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_REG_RD
	movl	(%r14), %edi
	leaq	L_.str.4(%rip), %rsi
	movl	%eax, %edx
	callq	_DP
	movq	_PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_REG_RD
	movl	(%r14), %edi
	leaq	L_.str.5(%rip), %rsi
	movl	%eax, %edx
	callq	_DP
	movq	_PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_REG_RD
	movl	(%r14), %edi
	leaq	L_.str.6(%rip), %rsi
	movl	%eax, %edx
	callq	_DP
	movq	_PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_REG_RD
	movl	(%r14), %edi
	leaq	L_.str.7(%rip), %rsi
	movl	%eax, %edx
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_DP                             ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_CFC_REG_WEAK_ENABLE_PF,4,2     ## @CFC_REG_WEAK_ENABLE_PF
	.comm	_BNX2X_MSG_SP,4,2               ## @BNX2X_MSG_SP
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"CFC_REG_WEAK_ENABLE_PF is 0x%x\n"

	.comm	_PBF_REG_DISABLE_PF,4,2         ## @PBF_REG_DISABLE_PF
L_.str.1:                               ## @.str.1
	.asciz	"PBF_REG_DISABLE_PF is 0x%x\n"

	.comm	_IGU_REG_PCI_PF_MSI_EN,4,2      ## @IGU_REG_PCI_PF_MSI_EN
L_.str.2:                               ## @.str.2
	.asciz	"IGU_REG_PCI_PF_MSI_EN is 0x%x\n"

	.comm	_IGU_REG_PCI_PF_MSIX_EN,4,2     ## @IGU_REG_PCI_PF_MSIX_EN
L_.str.3:                               ## @.str.3
	.asciz	"IGU_REG_PCI_PF_MSIX_EN is 0x%x\n"

	.comm	_IGU_REG_PCI_PF_MSIX_FUNC_MASK,4,2 ## @IGU_REG_PCI_PF_MSIX_FUNC_MASK
L_.str.4:                               ## @.str.4
	.asciz	"IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n"

	.comm	_PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR,4,2 ## @PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR
L_.str.5:                               ## @.str.5
	.asciz	"PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n"

	.comm	_PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR,4,2 ## @PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR
L_.str.6:                               ## @.str.6
	.asciz	"PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n"

	.comm	_PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,4,2 ## @PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
L_.str.7:                               ## @.str.7
	.asciz	"PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n"

	.no_dead_strip	_bnx2x_hw_enable_status
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function bnx2x_hw_enable_status
_bnx2x_hw_enable_status:                ; @bnx2x_hw_enable_status
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
Lloh0:
	adrp	x8, _CFC_REG_WEAK_ENABLE_PF@GOTPAGE
Lloh1:
	ldr	x8, [x8, _CFC_REG_WEAK_ENABLE_PF@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	bl	_REG_RD
	mov	x2, x0
Lloh3:
	adrp	x20, _BNX2X_MSG_SP@GOTPAGE
Lloh4:
	ldr	x20, [x20, _BNX2X_MSG_SP@GOTPAGEOFF]
	ldr	w0, [x20]
Lloh5:
	adrp	x1, l_.str@PAGE
Lloh6:
	add	x1, x1, l_.str@PAGEOFF
	bl	_DP
Lloh7:
	adrp	x8, _PBF_REG_DISABLE_PF@GOTPAGE
Lloh8:
	ldr	x8, [x8, _PBF_REG_DISABLE_PF@GOTPAGEOFF]
Lloh9:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_REG_RD
	mov	x2, x0
	ldr	w0, [x20]
Lloh10:
	adrp	x1, l_.str.1@PAGE
Lloh11:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_DP
Lloh12:
	adrp	x8, _IGU_REG_PCI_PF_MSI_EN@GOTPAGE
Lloh13:
	ldr	x8, [x8, _IGU_REG_PCI_PF_MSI_EN@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_REG_RD
	mov	x2, x0
	ldr	w0, [x20]
Lloh15:
	adrp	x1, l_.str.2@PAGE
Lloh16:
	add	x1, x1, l_.str.2@PAGEOFF
	bl	_DP
Lloh17:
	adrp	x8, _IGU_REG_PCI_PF_MSIX_EN@GOTPAGE
Lloh18:
	ldr	x8, [x8, _IGU_REG_PCI_PF_MSIX_EN@GOTPAGEOFF]
Lloh19:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_REG_RD
	mov	x2, x0
	ldr	w0, [x20]
Lloh20:
	adrp	x1, l_.str.3@PAGE
Lloh21:
	add	x1, x1, l_.str.3@PAGEOFF
	bl	_DP
Lloh22:
	adrp	x8, _IGU_REG_PCI_PF_MSIX_FUNC_MASK@GOTPAGE
Lloh23:
	ldr	x8, [x8, _IGU_REG_PCI_PF_MSIX_FUNC_MASK@GOTPAGEOFF]
Lloh24:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_REG_RD
	mov	x2, x0
	ldr	w0, [x20]
Lloh25:
	adrp	x1, l_.str.4@PAGE
Lloh26:
	add	x1, x1, l_.str.4@PAGEOFF
	bl	_DP
Lloh27:
	adrp	x8, _PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR@GOTPAGE
Lloh28:
	ldr	x8, [x8, _PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_REG_RD
	mov	x2, x0
	ldr	w0, [x20]
Lloh30:
	adrp	x1, l_.str.5@PAGE
Lloh31:
	add	x1, x1, l_.str.5@PAGEOFF
	bl	_DP
Lloh32:
	adrp	x8, _PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR@GOTPAGE
Lloh33:
	ldr	x8, [x8, _PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR@GOTPAGEOFF]
Lloh34:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_REG_RD
	mov	x2, x0
	ldr	w0, [x20]
Lloh35:
	adrp	x1, l_.str.6@PAGE
Lloh36:
	add	x1, x1, l_.str.6@PAGEOFF
	bl	_DP
Lloh37:
	adrp	x8, _PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER@GOTPAGE
Lloh38:
	ldr	x8, [x8, _PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER@GOTPAGEOFF]
Lloh39:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_REG_RD
	mov	x2, x0
	ldr	w0, [x20]
Lloh40:
	adrp	x1, l_.str.7@PAGE
Lloh41:
	add	x1, x1, l_.str.7@PAGEOFF
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_DP
	.loh AdrpAdd	Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpAdd	Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpAdd	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpAdd	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_CFC_REG_WEAK_ENABLE_PF,4,2     ; @CFC_REG_WEAK_ENABLE_PF
	.comm	_BNX2X_MSG_SP,4,2               ; @BNX2X_MSG_SP
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"CFC_REG_WEAK_ENABLE_PF is 0x%x\n"

	.comm	_PBF_REG_DISABLE_PF,4,2         ; @PBF_REG_DISABLE_PF
l_.str.1:                               ; @.str.1
	.asciz	"PBF_REG_DISABLE_PF is 0x%x\n"

	.comm	_IGU_REG_PCI_PF_MSI_EN,4,2      ; @IGU_REG_PCI_PF_MSI_EN
l_.str.2:                               ; @.str.2
	.asciz	"IGU_REG_PCI_PF_MSI_EN is 0x%x\n"

	.comm	_IGU_REG_PCI_PF_MSIX_EN,4,2     ; @IGU_REG_PCI_PF_MSIX_EN
l_.str.3:                               ; @.str.3
	.asciz	"IGU_REG_PCI_PF_MSIX_EN is 0x%x\n"

	.comm	_IGU_REG_PCI_PF_MSIX_FUNC_MASK,4,2 ; @IGU_REG_PCI_PF_MSIX_FUNC_MASK
l_.str.4:                               ; @.str.4
	.asciz	"IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n"

	.comm	_PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR,4,2 ; @PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR
l_.str.5:                               ; @.str.5
	.asciz	"PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n"

	.comm	_PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR,4,2 ; @PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR
l_.str.6:                               ; @.str.6
	.asciz	"PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n"

	.comm	_PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,4,2 ; @PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
l_.str.7:                               ; @.str.7
	.asciz	"PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n"

	.no_dead_strip	_bnx2x_hw_enable_status
.subsections_via_symbols
