	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function arm_smmu_device_reset
_arm_smmu_device_reset:                 ## @arm_smmu_device_reset
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %r12
	movq	_ARM_SMMU_CR0@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	24(%r12), %rdi
	callq	_readl_relaxed
	movq	_CR0_SMMUEN@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_2
## %bb.1:
	movl	4(%r12), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_warn
	xorl	%eax, %eax
	callq	_is_kdump_kernel
	testq	%rax, %rax
	setne	%al
	movq	_disable_bypass@GOTPCREL(%rip), %rcx
	cmpq	$0, (%rcx)
	sete	%cl
	andb	%al, %cl
	movzbl	%cl, %edi
	callq	_WARN_ON
	movq	_GBPA_ABORT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_arm_smmu_update_gbpa
LBB0_2:
	movq	%r12, %rdi
	callq	_arm_smmu_device_disable
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_27
## %bb.3:
	movl	%r14d, -52(%rbp)                ## 4-byte Spill
	movq	_CR1_TABLE_SH@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_ARM_SMMU_SH_ISH@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	callq	_FIELD_PREP
	movl	%eax, %r15d
	movq	_CR1_TABLE_OC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_CR1_CACHE_WB@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	callq	_FIELD_PREP
	orl	%eax, %r15d
	movq	_CR1_TABLE_IC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r14), %esi
	callq	_FIELD_PREP
	movl	%eax, %r13d
	movq	_CR1_QUEUE_SH@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%rbx), %esi
	callq	_FIELD_PREP
	orl	%eax, %r13d
	orl	%r15d, %r13d
	movq	_CR1_QUEUE_OC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r14), %esi
	callq	_FIELD_PREP
	movl	%eax, %ebx
	movq	_CR1_QUEUE_IC@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%r14), %esi
	movq	_ARM_SMMU_CR0@GOTPCREL(%rip), %r14
	callq	_FIELD_PREP
	orl	%eax, %ebx
	orl	%r13d, %ebx
	movq	_ARM_SMMU_CR1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	24(%r12), %rsi
	movl	%ebx, %edi
	callq	_writel_relaxed
	movq	_CR2_PTM@GOTPCREL(%rip), %rax
	movq	_CR2_RECINVSID@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	orl	(%rax), %edi
	movq	_CR2_E2H@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	_ARM_SMMU_CR2@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	24(%r12), %rsi
	callq	_writel_relaxed
	movl	60(%r12), %edi
	movq	_ARM_SMMU_STRTAB_BASE@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	24(%r12), %rsi
	callq	_writeq_relaxed
	movl	56(%r12), %edi
	movq	_ARM_SMMU_STRTAB_BASE_CFG@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	24(%r12), %rsi
	callq	_writel_relaxed
	movl	52(%r12), %edi
	movq	_ARM_SMMU_CMDQ_BASE@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	24(%r12), %rsi
	callq	_writeq_relaxed
	movl	44(%r12), %edi
	movq	_ARM_SMMU_CMDQ_PROD@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	24(%r12), %rsi
	callq	_writel_relaxed
	movl	48(%r12), %edi
	movq	_ARM_SMMU_CMDQ_CONS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	24(%r12), %rsi
	callq	_writel_relaxed
	movq	_CR0_CMDQEN@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	(%r14), %rdx
	movq	_ARM_SMMU_CR0ACK@GOTPCREL(%rip), %r13
	movl	(%r13), %ecx
	movq	%r12, %rdi
	movl	%r15d, %esi
	callq	_arm_smmu_write_reg_sync
	testl	%eax, %eax
	je	LBB0_5
## %bb.4:
	movl	%eax, %ebx
	movl	4(%r12), %edi
	leaq	L_.str.1(%rip), %rsi
	jmp	LBB0_26
LBB0_5:
	movq	_CMDQ_OP_CFGI_ALL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -48(%rbp)
	leaq	-48(%rbp), %rsi
	movq	%r12, %rdi
	callq	_arm_smmu_cmdq_issue_cmd
	movq	%r12, %rdi
	callq	_arm_smmu_cmdq_issue_sync
	movq	_ARM_SMMU_FEAT_HYP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r12)
	je	LBB0_7
## %bb.6:
	movq	_CMDQ_OP_TLBI_EL2_ALL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -48(%rbp)
	leaq	-48(%rbp), %rsi
	movq	%r12, %rdi
	callq	_arm_smmu_cmdq_issue_cmd
LBB0_7:
	movq	_CMDQ_OP_TLBI_NSNH_ALL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -48(%rbp)
	leaq	-48(%rbp), %rsi
	movq	%r12, %rdi
	callq	_arm_smmu_cmdq_issue_cmd
	movq	%r12, %rdi
	callq	_arm_smmu_cmdq_issue_sync
	movl	40(%r12), %edi
	movq	_ARM_SMMU_EVTQ_BASE@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	24(%r12), %rsi
	callq	_writeq_relaxed
	movl	32(%r12), %ebx
	movq	_ARM_SMMU_EVTQ_PROD@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	%r12, %rsi
	callq	_arm_smmu_page1_fixup
	movl	%ebx, %edi
	movq	%rax, %rsi
	callq	_writel_relaxed
	movl	36(%r12), %ebx
	movq	_ARM_SMMU_EVTQ_CONS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	%r12, %rsi
	callq	_arm_smmu_page1_fixup
	movl	%ebx, %edi
	movq	%rax, %rsi
	callq	_writel_relaxed
	movq	_CR0_EVTQEN@GOTPCREL(%rip), %rax
	orl	(%rax), %r15d
	movq	(%r14), %rdx
	movl	(%r13), %ecx
	movq	%r12, %rdi
	movl	%r15d, %esi
	callq	_arm_smmu_write_reg_sync
	testl	%eax, %eax
	je	LBB0_9
## %bb.8:
	movl	%eax, %ebx
	movl	4(%r12), %edi
	leaq	L_.str.2(%rip), %rsi
LBB0_26:
	callq	_dev_err
LBB0_27:
	movl	%ebx, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_9:
	movl	(%r12), %eax
	movq	_ARM_SMMU_FEAT_PRI@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_12
## %bb.10:
	movl	16(%r12), %edi
	movq	_ARM_SMMU_PRIQ_BASE@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	24(%r12), %rsi
	callq	_writeq_relaxed
	movl	8(%r12), %ebx
	movq	_ARM_SMMU_PRIQ_PROD@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	%r12, %rsi
	callq	_arm_smmu_page1_fixup
	movl	%ebx, %edi
	movq	%rax, %rsi
	callq	_writel_relaxed
	movl	12(%r12), %ebx
	movq	_ARM_SMMU_PRIQ_CONS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	%r12, %rsi
	callq	_arm_smmu_page1_fixup
	movl	%ebx, %edi
	movq	%rax, %rsi
	callq	_writel_relaxed
	movq	_CR0_PRIQEN@GOTPCREL(%rip), %rax
	orl	(%rax), %r15d
	movq	(%r14), %rdx
	movl	(%r13), %ecx
	movq	%r12, %rdi
	movl	%r15d, %esi
	callq	_arm_smmu_write_reg_sync
	testl	%eax, %eax
	je	LBB0_11
## %bb.28:
	movl	%eax, %ebx
	movl	4(%r12), %edi
	leaq	L_.str.3(%rip), %rsi
	jmp	LBB0_26
LBB0_11:
	movl	(%r12), %eax
LBB0_12:
	movq	_ARM_SMMU_FEAT_ATS@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_15
## %bb.13:
	movq	_CR0_ATSCHK@GOTPCREL(%rip), %rax
	orl	(%rax), %r15d
	movq	(%r14), %rdx
	movl	(%r13), %ecx
	movq	%r12, %rdi
	movl	%r15d, %esi
	callq	_arm_smmu_write_reg_sync
	testl	%eax, %eax
	je	LBB0_15
## %bb.14:
	movl	%eax, %ebx
	movl	4(%r12), %edi
	leaq	L_.str.4(%rip), %rsi
	jmp	LBB0_26
LBB0_15:
	movq	%r12, %rdi
	callq	_arm_smmu_setup_irqs
	testl	%eax, %eax
	je	LBB0_17
## %bb.16:
	movl	%eax, %ebx
	movl	4(%r12), %edi
	leaq	L_.str.5(%rip), %rsi
	jmp	LBB0_26
LBB0_17:
	xorl	%eax, %eax
	callq	_is_kdump_kernel
	testq	%rax, %rax
	je	LBB0_19
## %bb.18:
	movq	_CR0_PRIQEN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_CR0_EVTQEN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	notl	%eax
	andl	%eax, %r15d
LBB0_19:
	cmpl	$0, -52(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_21
## %bb.20:
	movq	_disable_bypass@GOTPCREL(%rip), %rax
	cmpq	$0, (%rax)
	jne	LBB0_21
## %bb.22:
	movq	_GBPA_ABORT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	_arm_smmu_update_gbpa
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_27
	jmp	LBB0_23
LBB0_21:
	movq	_CR0_SMMUEN@GOTPCREL(%rip), %rax
	orl	(%rax), %r15d
LBB0_23:
	movq	(%r14), %rdx
	movl	(%r13), %ecx
	movq	%r12, %rdi
	movl	%r15d, %esi
	callq	_arm_smmu_write_reg_sync
	testl	%eax, %eax
	je	LBB0_24
## %bb.25:
	movl	%eax, %ebx
	movl	4(%r12), %edi
	leaq	L_.str.6(%rip), %rsi
	jmp	LBB0_26
LBB0_24:
	xorl	%ebx, %ebx
	jmp	LBB0_27
	.cfi_endproc
                                        ## -- End function
	.comm	_ARM_SMMU_CR0,8,3               ## @ARM_SMMU_CR0
	.comm	_CR0_SMMUEN,4,2                 ## @CR0_SMMUEN
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"SMMU currently enabled! Resetting...\n"

	.comm	_disable_bypass,8,3             ## @disable_bypass
	.comm	_GBPA_ABORT,4,2                 ## @GBPA_ABORT
	.comm	_CR1_TABLE_SH,4,2               ## @CR1_TABLE_SH
	.comm	_ARM_SMMU_SH_ISH,4,2            ## @ARM_SMMU_SH_ISH
	.comm	_CR1_TABLE_OC,4,2               ## @CR1_TABLE_OC
	.comm	_CR1_CACHE_WB,4,2               ## @CR1_CACHE_WB
	.comm	_CR1_TABLE_IC,4,2               ## @CR1_TABLE_IC
	.comm	_CR1_QUEUE_SH,4,2               ## @CR1_QUEUE_SH
	.comm	_CR1_QUEUE_OC,4,2               ## @CR1_QUEUE_OC
	.comm	_CR1_QUEUE_IC,4,2               ## @CR1_QUEUE_IC
	.comm	_ARM_SMMU_CR1,8,3               ## @ARM_SMMU_CR1
	.comm	_CR2_PTM,4,2                    ## @CR2_PTM
	.comm	_CR2_RECINVSID,4,2              ## @CR2_RECINVSID
	.comm	_CR2_E2H,4,2                    ## @CR2_E2H
	.comm	_ARM_SMMU_CR2,8,3               ## @ARM_SMMU_CR2
	.comm	_ARM_SMMU_STRTAB_BASE,8,3       ## @ARM_SMMU_STRTAB_BASE
	.comm	_ARM_SMMU_STRTAB_BASE_CFG,8,3   ## @ARM_SMMU_STRTAB_BASE_CFG
	.comm	_ARM_SMMU_CMDQ_BASE,8,3         ## @ARM_SMMU_CMDQ_BASE
	.comm	_ARM_SMMU_CMDQ_PROD,8,3         ## @ARM_SMMU_CMDQ_PROD
	.comm	_ARM_SMMU_CMDQ_CONS,8,3         ## @ARM_SMMU_CMDQ_CONS
	.comm	_CR0_CMDQEN,4,2                 ## @CR0_CMDQEN
	.comm	_ARM_SMMU_CR0ACK,4,2            ## @ARM_SMMU_CR0ACK
L_.str.1:                               ## @.str.1
	.asciz	"failed to enable command queue\n"

	.comm	_CMDQ_OP_CFGI_ALL,4,2           ## @CMDQ_OP_CFGI_ALL
	.comm	_ARM_SMMU_FEAT_HYP,4,2          ## @ARM_SMMU_FEAT_HYP
	.comm	_CMDQ_OP_TLBI_EL2_ALL,4,2       ## @CMDQ_OP_TLBI_EL2_ALL
	.comm	_CMDQ_OP_TLBI_NSNH_ALL,4,2      ## @CMDQ_OP_TLBI_NSNH_ALL
	.comm	_ARM_SMMU_EVTQ_BASE,8,3         ## @ARM_SMMU_EVTQ_BASE
	.comm	_ARM_SMMU_EVTQ_PROD,4,2         ## @ARM_SMMU_EVTQ_PROD
	.comm	_ARM_SMMU_EVTQ_CONS,4,2         ## @ARM_SMMU_EVTQ_CONS
	.comm	_CR0_EVTQEN,4,2                 ## @CR0_EVTQEN
L_.str.2:                               ## @.str.2
	.asciz	"failed to enable event queue\n"

	.comm	_ARM_SMMU_FEAT_PRI,4,2          ## @ARM_SMMU_FEAT_PRI
	.comm	_ARM_SMMU_PRIQ_BASE,8,3         ## @ARM_SMMU_PRIQ_BASE
	.comm	_ARM_SMMU_PRIQ_PROD,4,2         ## @ARM_SMMU_PRIQ_PROD
	.comm	_ARM_SMMU_PRIQ_CONS,4,2         ## @ARM_SMMU_PRIQ_CONS
	.comm	_CR0_PRIQEN,4,2                 ## @CR0_PRIQEN
L_.str.3:                               ## @.str.3
	.asciz	"failed to enable PRI queue\n"

	.comm	_ARM_SMMU_FEAT_ATS,4,2          ## @ARM_SMMU_FEAT_ATS
	.comm	_CR0_ATSCHK,4,2                 ## @CR0_ATSCHK
L_.str.4:                               ## @.str.4
	.asciz	"failed to enable ATS check\n"

L_.str.5:                               ## @.str.5
	.asciz	"failed to setup irqs\n"

L_.str.6:                               ## @.str.6
	.asciz	"failed to enable SMMU interface\n"

	.no_dead_strip	_arm_smmu_device_reset
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function arm_smmu_device_reset
_arm_smmu_device_reset:                 ; @arm_smmu_device_reset
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x1
	mov	x19, x0
	ldr	x8, [x0, #24]
Lloh0:
	adrp	x23, _ARM_SMMU_CR0@GOTPAGE
Lloh1:
	ldr	x23, [x23, _ARM_SMMU_CR0@GOTPAGEOFF]
	ldr	x9, [x23]
	add	x0, x9, x8
	bl	_readl_relaxed
Lloh2:
	adrp	x24, _CR0_SMMUEN@GOTPAGE
Lloh3:
	ldr	x24, [x24, _CR0_SMMUEN@GOTPAGEOFF]
	ldr	w8, [x24]
	tst	w8, w0
	b.eq	LBB0_2
; %bb.1:
	ldr	w0, [x19, #4]
Lloh4:
	adrp	x1, l_.str@PAGE
Lloh5:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_warn
	bl	_is_kdump_kernel
	cmp	x0, #0
Lloh6:
	adrp	x8, _disable_bypass@GOTPAGE
Lloh7:
	ldr	x8, [x8, _disable_bypass@GOTPAGEOFF]
Lloh8:
	ldr	x8, [x8]
	ccmp	x8, #0, #0, ne
	cset	w0, eq
	bl	_WARN_ON
Lloh9:
	adrp	x8, _GBPA_ABORT@GOTPAGE
Lloh10:
	ldr	x8, [x8, _GBPA_ABORT@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_arm_smmu_update_gbpa
LBB0_2:
	mov	x0, x19
	bl	_arm_smmu_device_disable
	mov	x22, x0
	cbnz	w0, LBB0_10
; %bb.3:
Lloh12:
	adrp	x8, _CR1_TABLE_SH@GOTPAGE
Lloh13:
	ldr	x8, [x8, _CR1_TABLE_SH@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
Lloh15:
	adrp	x22, _ARM_SMMU_SH_ISH@GOTPAGE
Lloh16:
	ldr	x22, [x22, _ARM_SMMU_SH_ISH@GOTPAGEOFF]
	ldr	w1, [x22]
	bl	_FIELD_PREP
	mov	x21, x0
Lloh17:
	adrp	x8, _CR1_TABLE_OC@GOTPAGE
Lloh18:
	ldr	x8, [x8, _CR1_TABLE_OC@GOTPAGEOFF]
Lloh19:
	ldr	w0, [x8]
Lloh20:
	adrp	x25, _CR1_CACHE_WB@GOTPAGE
Lloh21:
	ldr	x25, [x25, _CR1_CACHE_WB@GOTPAGEOFF]
	ldr	w1, [x25]
	bl	_FIELD_PREP
	orr	w21, w0, w21
Lloh22:
	adrp	x8, _CR1_TABLE_IC@GOTPAGE
Lloh23:
	ldr	x8, [x8, _CR1_TABLE_IC@GOTPAGEOFF]
Lloh24:
	ldr	w0, [x8]
	ldr	w1, [x25]
	bl	_FIELD_PREP
	orr	w21, w21, w0
Lloh25:
	adrp	x8, _CR1_QUEUE_SH@GOTPAGE
Lloh26:
	ldr	x8, [x8, _CR1_QUEUE_SH@GOTPAGEOFF]
Lloh27:
	ldr	w0, [x8]
	ldr	w1, [x22]
	bl	_FIELD_PREP
	orr	w21, w21, w0
Lloh28:
	adrp	x8, _CR1_QUEUE_OC@GOTPAGE
Lloh29:
	ldr	x8, [x8, _CR1_QUEUE_OC@GOTPAGEOFF]
Lloh30:
	ldr	w0, [x8]
	ldr	w1, [x25]
	bl	_FIELD_PREP
	orr	w21, w21, w0
Lloh31:
	adrp	x8, _CR1_QUEUE_IC@GOTPAGE
Lloh32:
	ldr	x8, [x8, _CR1_QUEUE_IC@GOTPAGEOFF]
Lloh33:
	ldr	w0, [x8]
	ldr	w1, [x25]
	bl	_FIELD_PREP
	orr	w0, w21, w0
	ldr	x8, [x19, #24]
Lloh34:
	adrp	x9, _ARM_SMMU_CR1@GOTPAGE
Lloh35:
	ldr	x9, [x9, _ARM_SMMU_CR1@GOTPAGEOFF]
Lloh36:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
Lloh37:
	adrp	x8, _CR2_PTM@GOTPAGE
Lloh38:
	ldr	x8, [x8, _CR2_PTM@GOTPAGEOFF]
Lloh39:
	adrp	x9, _CR2_RECINVSID@GOTPAGE
Lloh40:
	ldr	x9, [x9, _CR2_RECINVSID@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
Lloh42:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh43:
	adrp	x9, _CR2_E2H@GOTPAGE
Lloh44:
	ldr	x9, [x9, _CR2_E2H@GOTPAGEOFF]
Lloh45:
	ldr	w9, [x9]
	orr	w0, w8, w9
	ldr	x8, [x19, #24]
Lloh46:
	adrp	x9, _ARM_SMMU_CR2@GOTPAGE
Lloh47:
	ldr	x9, [x9, _ARM_SMMU_CR2@GOTPAGEOFF]
Lloh48:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w0, [x19, #60]
	ldr	x8, [x19, #24]
Lloh49:
	adrp	x9, _ARM_SMMU_STRTAB_BASE@GOTPAGE
Lloh50:
	ldr	x9, [x9, _ARM_SMMU_STRTAB_BASE@GOTPAGEOFF]
Lloh51:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writeq_relaxed
	ldr	w0, [x19, #56]
	ldr	x8, [x19, #24]
Lloh52:
	adrp	x9, _ARM_SMMU_STRTAB_BASE_CFG@GOTPAGE
Lloh53:
	ldr	x9, [x9, _ARM_SMMU_STRTAB_BASE_CFG@GOTPAGEOFF]
Lloh54:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w0, [x19, #52]
	ldr	x8, [x19, #24]
Lloh55:
	adrp	x9, _ARM_SMMU_CMDQ_BASE@GOTPAGE
Lloh56:
	ldr	x9, [x9, _ARM_SMMU_CMDQ_BASE@GOTPAGEOFF]
Lloh57:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writeq_relaxed
	ldr	w0, [x19, #44]
	ldr	x8, [x19, #24]
Lloh58:
	adrp	x9, _ARM_SMMU_CMDQ_PROD@GOTPAGE
Lloh59:
	ldr	x9, [x9, _ARM_SMMU_CMDQ_PROD@GOTPAGEOFF]
Lloh60:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w0, [x19, #48]
	ldr	x8, [x19, #24]
Lloh61:
	adrp	x9, _ARM_SMMU_CMDQ_CONS@GOTPAGE
Lloh62:
	ldr	x9, [x9, _ARM_SMMU_CMDQ_CONS@GOTPAGEOFF]
Lloh63:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
Lloh64:
	adrp	x8, _CR0_CMDQEN@GOTPAGE
Lloh65:
	ldr	x8, [x8, _CR0_CMDQEN@GOTPAGEOFF]
Lloh66:
	ldr	w21, [x8]
	ldr	x2, [x23]
Lloh67:
	adrp	x25, _ARM_SMMU_CR0ACK@GOTPAGE
Lloh68:
	ldr	x25, [x25, _ARM_SMMU_CR0ACK@GOTPAGEOFF]
	ldr	w3, [x25]
	mov	x0, x19
	mov	x1, x21
	bl	_arm_smmu_write_reg_sync
	cbz	w0, LBB0_5
; %bb.4:
	mov	x22, x0
	ldr	w0, [x19, #4]
Lloh69:
	adrp	x1, l_.str.1@PAGE
Lloh70:
	add	x1, x1, l_.str.1@PAGEOFF
	b	LBB0_9
LBB0_5:
Lloh71:
	adrp	x8, _CMDQ_OP_CFGI_ALL@GOTPAGE
Lloh72:
	ldr	x8, [x8, _CMDQ_OP_CFGI_ALL@GOTPAGEOFF]
Lloh73:
	ldr	w8, [x8]
	str	w8, [sp, #8]
	add	x1, sp, #8
	mov	x0, x19
	bl	_arm_smmu_cmdq_issue_cmd
	mov	x0, x19
	bl	_arm_smmu_cmdq_issue_sync
	ldr	w8, [x19]
Lloh74:
	adrp	x9, _ARM_SMMU_FEAT_HYP@GOTPAGE
Lloh75:
	ldr	x9, [x9, _ARM_SMMU_FEAT_HYP@GOTPAGEOFF]
Lloh76:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_7
; %bb.6:
Lloh77:
	adrp	x8, _CMDQ_OP_TLBI_EL2_ALL@GOTPAGE
Lloh78:
	ldr	x8, [x8, _CMDQ_OP_TLBI_EL2_ALL@GOTPAGEOFF]
Lloh79:
	ldr	w8, [x8]
	str	w8, [sp, #8]
	add	x1, sp, #8
	mov	x0, x19
	bl	_arm_smmu_cmdq_issue_cmd
LBB0_7:
Lloh80:
	adrp	x8, _CMDQ_OP_TLBI_NSNH_ALL@GOTPAGE
Lloh81:
	ldr	x8, [x8, _CMDQ_OP_TLBI_NSNH_ALL@GOTPAGEOFF]
Lloh82:
	ldr	w8, [x8]
	str	w8, [sp, #8]
	add	x1, sp, #8
	mov	x0, x19
	bl	_arm_smmu_cmdq_issue_cmd
	mov	x0, x19
	bl	_arm_smmu_cmdq_issue_sync
	ldr	w0, [x19, #40]
	ldr	x8, [x19, #24]
Lloh83:
	adrp	x9, _ARM_SMMU_EVTQ_BASE@GOTPAGE
Lloh84:
	ldr	x9, [x9, _ARM_SMMU_EVTQ_BASE@GOTPAGEOFF]
Lloh85:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writeq_relaxed
	ldr	w22, [x19, #32]
Lloh86:
	adrp	x8, _ARM_SMMU_EVTQ_PROD@GOTPAGE
Lloh87:
	ldr	x8, [x8, _ARM_SMMU_EVTQ_PROD@GOTPAGEOFF]
Lloh88:
	ldr	w0, [x8]
	mov	x1, x19
	bl	_arm_smmu_page1_fixup
	mov	x1, x0
	mov	x0, x22
	bl	_writel_relaxed
	ldr	w22, [x19, #36]
Lloh89:
	adrp	x8, _ARM_SMMU_EVTQ_CONS@GOTPAGE
Lloh90:
	ldr	x8, [x8, _ARM_SMMU_EVTQ_CONS@GOTPAGEOFF]
Lloh91:
	ldr	w0, [x8]
	mov	x1, x19
	bl	_arm_smmu_page1_fixup
	mov	x1, x0
	mov	x0, x22
	bl	_writel_relaxed
Lloh92:
	adrp	x26, _CR0_EVTQEN@GOTPAGE
Lloh93:
	ldr	x26, [x26, _CR0_EVTQEN@GOTPAGEOFF]
	ldr	w8, [x26]
	orr	w21, w8, w21
	ldr	x2, [x23]
	ldr	w3, [x25]
	mov	x0, x19
	mov	x1, x21
	bl	_arm_smmu_write_reg_sync
	cbz	w0, LBB0_11
; %bb.8:
	mov	x22, x0
	ldr	w0, [x19, #4]
Lloh94:
	adrp	x1, l_.str.2@PAGE
Lloh95:
	add	x1, x1, l_.str.2@PAGEOFF
LBB0_9:
	bl	_dev_err
LBB0_10:
	mov	x0, x22
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_11:
	ldr	w8, [x19]
Lloh96:
	adrp	x9, _ARM_SMMU_FEAT_PRI@GOTPAGE
Lloh97:
	ldr	x9, [x9, _ARM_SMMU_FEAT_PRI@GOTPAGEOFF]
Lloh98:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_15
; %bb.12:
	ldr	w0, [x19, #16]
	ldr	x8, [x19, #24]
Lloh99:
	adrp	x9, _ARM_SMMU_PRIQ_BASE@GOTPAGE
Lloh100:
	ldr	x9, [x9, _ARM_SMMU_PRIQ_BASE@GOTPAGEOFF]
Lloh101:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writeq_relaxed
	ldr	w22, [x19, #8]
Lloh102:
	adrp	x8, _ARM_SMMU_PRIQ_PROD@GOTPAGE
Lloh103:
	ldr	x8, [x8, _ARM_SMMU_PRIQ_PROD@GOTPAGEOFF]
Lloh104:
	ldr	w0, [x8]
	mov	x1, x19
	bl	_arm_smmu_page1_fixup
	mov	x1, x0
	mov	x0, x22
	bl	_writel_relaxed
	ldr	w22, [x19, #12]
Lloh105:
	adrp	x8, _ARM_SMMU_PRIQ_CONS@GOTPAGE
Lloh106:
	ldr	x8, [x8, _ARM_SMMU_PRIQ_CONS@GOTPAGEOFF]
Lloh107:
	ldr	w0, [x8]
	mov	x1, x19
	bl	_arm_smmu_page1_fixup
	mov	x1, x0
	mov	x0, x22
	bl	_writel_relaxed
Lloh108:
	adrp	x8, _CR0_PRIQEN@GOTPAGE
Lloh109:
	ldr	x8, [x8, _CR0_PRIQEN@GOTPAGEOFF]
Lloh110:
	ldr	w8, [x8]
	orr	w21, w8, w21
	ldr	x2, [x23]
	ldr	w3, [x25]
	mov	x0, x19
	mov	x1, x21
	bl	_arm_smmu_write_reg_sync
	cbz	w0, LBB0_14
; %bb.13:
	mov	x22, x0
	ldr	w0, [x19, #4]
Lloh111:
	adrp	x1, l_.str.3@PAGE
Lloh112:
	add	x1, x1, l_.str.3@PAGEOFF
	b	LBB0_9
LBB0_14:
	ldr	w8, [x19]
LBB0_15:
Lloh113:
	adrp	x9, _ARM_SMMU_FEAT_ATS@GOTPAGE
Lloh114:
	ldr	x9, [x9, _ARM_SMMU_FEAT_ATS@GOTPAGEOFF]
Lloh115:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_18
; %bb.16:
Lloh116:
	adrp	x8, _CR0_ATSCHK@GOTPAGE
Lloh117:
	ldr	x8, [x8, _CR0_ATSCHK@GOTPAGEOFF]
Lloh118:
	ldr	w8, [x8]
	orr	w21, w8, w21
	ldr	x2, [x23]
	ldr	w3, [x25]
	mov	x0, x19
	mov	x1, x21
	bl	_arm_smmu_write_reg_sync
	cbz	w0, LBB0_18
; %bb.17:
	mov	x22, x0
	ldr	w0, [x19, #4]
Lloh119:
	adrp	x1, l_.str.4@PAGE
Lloh120:
	add	x1, x1, l_.str.4@PAGEOFF
	b	LBB0_9
LBB0_18:
	mov	x0, x19
	bl	_arm_smmu_setup_irqs
	cbz	w0, LBB0_20
; %bb.19:
	mov	x22, x0
	ldr	w0, [x19, #4]
Lloh121:
	adrp	x1, l_.str.5@PAGE
Lloh122:
	add	x1, x1, l_.str.5@PAGEOFF
	b	LBB0_9
LBB0_20:
	bl	_is_kdump_kernel
	cbz	x0, LBB0_22
; %bb.21:
	ldr	w8, [x26]
Lloh123:
	adrp	x9, _CR0_PRIQEN@GOTPAGE
Lloh124:
	ldr	x9, [x9, _CR0_PRIQEN@GOTPAGEOFF]
Lloh125:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w21, w21, w8
LBB0_22:
	cbz	w20, LBB0_25
; %bb.23:
Lloh126:
	adrp	x8, _disable_bypass@GOTPAGE
Lloh127:
	ldr	x8, [x8, _disable_bypass@GOTPAGEOFF]
Lloh128:
	ldr	x8, [x8]
	cbnz	x8, LBB0_25
; %bb.24:
Lloh129:
	adrp	x8, _GBPA_ABORT@GOTPAGE
Lloh130:
	ldr	x8, [x8, _GBPA_ABORT@GOTPAGEOFF]
Lloh131:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w1, #0
	bl	_arm_smmu_update_gbpa
	mov	x22, x0
	cbnz	w0, LBB0_10
	b	LBB0_26
LBB0_25:
	ldr	w8, [x24]
	orr	w21, w8, w21
LBB0_26:
	ldr	x2, [x23]
	ldr	w3, [x25]
	mov	x0, x19
	mov	x1, x21
	bl	_arm_smmu_write_reg_sync
	mov	x22, x0
	cbz	w0, LBB0_10
; %bb.27:
	ldr	w0, [x19, #4]
Lloh132:
	adrp	x1, l_.str.6@PAGE
Lloh133:
	add	x1, x1, l_.str.6@PAGEOFF
	b	LBB0_9
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh41
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpAdd	Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGot	Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpAdd	Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpAdd	Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpAdd	Lloh119, Lloh120
	.loh AdrpAdd	Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh123, Lloh124, Lloh125
	.loh AdrpLdrGotLdr	Lloh126, Lloh127, Lloh128
	.loh AdrpLdrGotLdr	Lloh129, Lloh130, Lloh131
	.loh AdrpAdd	Lloh132, Lloh133
	.cfi_endproc
                                        ; -- End function
	.comm	_ARM_SMMU_CR0,8,3               ; @ARM_SMMU_CR0
	.comm	_CR0_SMMUEN,4,2                 ; @CR0_SMMUEN
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"SMMU currently enabled! Resetting...\n"

	.comm	_disable_bypass,8,3             ; @disable_bypass
	.comm	_GBPA_ABORT,4,2                 ; @GBPA_ABORT
	.comm	_CR1_TABLE_SH,4,2               ; @CR1_TABLE_SH
	.comm	_ARM_SMMU_SH_ISH,4,2            ; @ARM_SMMU_SH_ISH
	.comm	_CR1_TABLE_OC,4,2               ; @CR1_TABLE_OC
	.comm	_CR1_CACHE_WB,4,2               ; @CR1_CACHE_WB
	.comm	_CR1_TABLE_IC,4,2               ; @CR1_TABLE_IC
	.comm	_CR1_QUEUE_SH,4,2               ; @CR1_QUEUE_SH
	.comm	_CR1_QUEUE_OC,4,2               ; @CR1_QUEUE_OC
	.comm	_CR1_QUEUE_IC,4,2               ; @CR1_QUEUE_IC
	.comm	_ARM_SMMU_CR1,8,3               ; @ARM_SMMU_CR1
	.comm	_CR2_PTM,4,2                    ; @CR2_PTM
	.comm	_CR2_RECINVSID,4,2              ; @CR2_RECINVSID
	.comm	_CR2_E2H,4,2                    ; @CR2_E2H
	.comm	_ARM_SMMU_CR2,8,3               ; @ARM_SMMU_CR2
	.comm	_ARM_SMMU_STRTAB_BASE,8,3       ; @ARM_SMMU_STRTAB_BASE
	.comm	_ARM_SMMU_STRTAB_BASE_CFG,8,3   ; @ARM_SMMU_STRTAB_BASE_CFG
	.comm	_ARM_SMMU_CMDQ_BASE,8,3         ; @ARM_SMMU_CMDQ_BASE
	.comm	_ARM_SMMU_CMDQ_PROD,8,3         ; @ARM_SMMU_CMDQ_PROD
	.comm	_ARM_SMMU_CMDQ_CONS,8,3         ; @ARM_SMMU_CMDQ_CONS
	.comm	_CR0_CMDQEN,4,2                 ; @CR0_CMDQEN
	.comm	_ARM_SMMU_CR0ACK,4,2            ; @ARM_SMMU_CR0ACK
l_.str.1:                               ; @.str.1
	.asciz	"failed to enable command queue\n"

	.comm	_CMDQ_OP_CFGI_ALL,4,2           ; @CMDQ_OP_CFGI_ALL
	.comm	_ARM_SMMU_FEAT_HYP,4,2          ; @ARM_SMMU_FEAT_HYP
	.comm	_CMDQ_OP_TLBI_EL2_ALL,4,2       ; @CMDQ_OP_TLBI_EL2_ALL
	.comm	_CMDQ_OP_TLBI_NSNH_ALL,4,2      ; @CMDQ_OP_TLBI_NSNH_ALL
	.comm	_ARM_SMMU_EVTQ_BASE,8,3         ; @ARM_SMMU_EVTQ_BASE
	.comm	_ARM_SMMU_EVTQ_PROD,4,2         ; @ARM_SMMU_EVTQ_PROD
	.comm	_ARM_SMMU_EVTQ_CONS,4,2         ; @ARM_SMMU_EVTQ_CONS
	.comm	_CR0_EVTQEN,4,2                 ; @CR0_EVTQEN
l_.str.2:                               ; @.str.2
	.asciz	"failed to enable event queue\n"

	.comm	_ARM_SMMU_FEAT_PRI,4,2          ; @ARM_SMMU_FEAT_PRI
	.comm	_ARM_SMMU_PRIQ_BASE,8,3         ; @ARM_SMMU_PRIQ_BASE
	.comm	_ARM_SMMU_PRIQ_PROD,4,2         ; @ARM_SMMU_PRIQ_PROD
	.comm	_ARM_SMMU_PRIQ_CONS,4,2         ; @ARM_SMMU_PRIQ_CONS
	.comm	_CR0_PRIQEN,4,2                 ; @CR0_PRIQEN
l_.str.3:                               ; @.str.3
	.asciz	"failed to enable PRI queue\n"

	.comm	_ARM_SMMU_FEAT_ATS,4,2          ; @ARM_SMMU_FEAT_ATS
	.comm	_CR0_ATSCHK,4,2                 ; @CR0_ATSCHK
l_.str.4:                               ; @.str.4
	.asciz	"failed to enable ATS check\n"

l_.str.5:                               ; @.str.5
	.asciz	"failed to setup irqs\n"

l_.str.6:                               ; @.str.6
	.asciz	"failed to enable SMMU interface\n"

	.no_dead_strip	_arm_smmu_device_reset
.subsections_via_symbols
