	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_v4l2_detect_cvt                ## -- Begin function v4l2_detect_cvt
	.p2align	4, 0x90
_v4l2_detect_cvt:                       ## @v4l2_detect_cvt
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
                                        ## kill: def $ecx killed $ecx def $rcx
	movl	%edx, %r10d
	leal	-9(%r10), %edx
	xorl	%eax, %eax
	cmpl	$-5, %edx
	jb	LBB0_30
## %bb.1:
	movq	_V4L2_DV_VSYNC_POS_POL@GOTPCREL(%rip), %rdx
	movq	(%rdx), %r11
	cmpq	%r8, %r11
	je	LBB0_3
## %bb.2:
	movq	_V4L2_DV_HSYNC_POS_POL@GOTPCREL(%rip), %rdx
	cmpq	%r8, (%rdx)
	jne	LBB0_30
LBB0_3:
	cmpq	%r8, %r11
	sete	%r15b
	cmpl	$8, %r10d
	setne	%r14b
	setae	%dl
	testl	%ecx, %ecx
	setne	%bl
	testl	%esi, %esi
	je	LBB0_30
## %bb.4:
	orb	%r15b, %r14b
	andb	%r14b, %dl
	jne	LBB0_30
## %bb.5:
	orb	%r14b, %bl
	je	LBB0_30
## %bb.6:
	cmpq	%r8, %r11
	jne	LBB0_8
## %bb.7:
	movq	_CVT_MIN_V_PORCH_RND@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r15d
	movq	_CVT_MIN_VSYNC_BP@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	imull	%esi, %edx
	imulq	$1125899907, %rdx, %rbx         ## imm = 0x431BDE83
	shrq	$50, %rbx
	subl	%r10d, %ebx
	incl	%ebx
	movq	_CVT_MIN_V_BPORCH@GOTPCREL(%rip), %rdx
	jmp	LBB0_10
LBB0_8:
	testb	%r14b, %r14b
	je	LBB0_12
## %bb.9:
	movq	_CVT_RB_V_FPORCH@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r15d
	movq	_CVT_RB_MIN_V_BLANK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	imull	%esi, %edx
	imulq	$1125899907, %rdx, %rbx         ## imm = 0x431BDE83
	shrq	$50, %rbx
	subl	%r15d, %ebx
	subl	%r10d, %ebx
	incl	%ebx
	movq	_CVT_RB_MIN_V_BPORCH@GOTPCREL(%rip), %rdx
LBB0_10:
	movl	(%rdx), %edx
	cmpl	%edx, %ebx
	cmovlel	%edx, %ebx
	testl	%r9d, %r9d
	je	LBB0_13
LBB0_11:
	addl	%r15d, %ebx
	addl	%r10d, %ebx
	addl	%ebx, %ebx
	movl	%edi, %r13d
	subl	%ebx, %r13d
	andl	$-2, %r13d
	jns	LBB0_14
	jmp	LBB0_30
LBB0_12:
	movq	_CVT_RB_V_BPORCH@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	movq	_CVT_RB_MIN_V_BLANK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	imull	%esi, %edx
	imulq	$1125899907, %rdx, %r15         ## imm = 0x431BDE83
	shrq	$50, %r15
	subl	%ebx, %r15d
	addl	$-7, %r15d
	movq	_CVT_RB_V2_MIN_V_FPORCH@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	cmpl	%edx, %r15d
	cmovlel	%edx, %r15d
	testl	%r9d, %r9d
	jne	LBB0_11
LBB0_13:
	addl	%r10d, %ebx
	addl	%r15d, %ebx
	movl	%edi, %r13d
	subl	%ebx, %r13d
	incl	%r13d
	andl	$-2, %r13d
	js	LBB0_30
LBB0_14:
	leal	-4(%r10), %edx
	cmpl	$4, %edx
	ja	LBB0_30
## %bb.15:
	leaq	LJTI0_0(%rip), %rbx
	movslq	(%rbx,%rdx,4), %rdx
	addq	%rbx, %rdx
	jmpq	*%rdx
LBB0_16:
	leal	(,%r13,4), %eax
	cltq
	imulq	$1431655766, %rax, %rcx         ## imm = 0x55555556
	movq	%rcx, %rax
	shrq	$63, %rax
	shrq	$32, %rcx
	jmp	LBB0_21
LBB0_17:
	movl	$1280, %ecx                     ## imm = 0x500
	cmpl	$1024, %r13d                    ## imm = 0x400
	je	LBB0_22
## %bb.18:
	cmpl	$768, %r13d                     ## imm = 0x300
	je	LBB0_22
	jmp	LBB0_30
LBB0_19:
	movl	%r13d, %eax
	shll	$4, %eax
	cltq
	imulq	$954437177, %rax, %rcx          ## imm = 0x38E38E39
	movq	%rcx, %rax
	shrq	$63, %rax
	sarq	$33, %rcx
	jmp	LBB0_21
LBB0_20:
	movl	%r13d, %eax
	shll	$4, %eax
	cltq
	imulq	$1717986919, %rax, %rcx         ## imm = 0x66666667
	movq	%rcx, %rax
	shrq	$63, %rax
	sarq	$34, %rcx
LBB0_21:
	addl	%eax, %ecx
LBB0_22:
	movl	%ecx, %r12d
	andl	$-8, %r12d
	testb	%r14b, %r14b
	cmovel	%ecx, %r12d
	cmpq	%r8, %r11
	jne	LBB0_24
## %bb.23:
	movq	_CVT_C_PRIME@GOTPCREL(%rip), %rax
	imull	$100, (%rax), %ecx
	movq	_CVT_M_PRIME@GOTPCREL(%rip), %rax
	imull	$100000, (%rax), %eax           ## imm = 0x186A0
	xorl	%edx, %edx
	divl	%esi
	subl	%eax, %ecx
	cmpl	$2001, %ecx                     ## imm = 0x7D1
	movl	$2000, %eax                     ## imm = 0x7D0
	cmovael	%ecx, %eax
	movl	$10000, %ecx                    ## imm = 0x2710
	subl	%eax, %ecx
	imull	%r12d, %eax
	xorl	%edx, %edx
	divl	%ecx
	movq	_CVT_CELL_GRAN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	movq	%rbx, -48(%rbp)                 ## 8-byte Spill
	leal	(%rbx,%rbx), %ecx
	cltd
	idivl	%ecx
                                        ## kill: def $eax killed $eax def $rax
	imull	%ebx, %eax
	leal	(%r12,%rax,2), %r14d
	movl	%eax, %ebx
	imull	%r14d, %esi
	movq	_CVT_PXL_CLK_GRAN@GOTPCREL(%rip), %rcx
	movl	%esi, %eax
	xorl	%edx, %edx
	divl	(%rcx)
	addl	%ebx, %ebx
	subl	%edx, %esi
	movq	%r15, -56(%rbp)                 ## 8-byte Spill
	movl	%ebx, %r15d
	sarl	%r15d
	movq	_CVT_HSYNC_PERCENT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	imull	%r14d, %eax
	cltq
	imulq	$1374389535, %rax, %rcx         ## imm = 0x51EB851F
	movq	%rcx, %rax
	shrq	$63, %rax
	sarq	$37, %rcx
	addl	%eax, %ecx
	movl	%ecx, %eax
	cltd
	idivl	-48(%rbp)                       ## 4-byte Folded Reload
	subl	%edx, %ecx
	movq	16(%rbp), %rdx
	subl	%r15d, %ebx
	movq	-56(%rbp), %r15                 ## 8-byte Reload
	jmp	LBB0_25
LBB0_24:
	movq	_CVT_RB_V2_H_BLANK@GOTPCREL(%rip), %rax
	testb	%r14b, %r14b
	cmovneq	_CVT_RB_H_BLANK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_CVT_PXL_CLK_GRAN_RB_V2@GOTPCREL(%rip), %rcx
	cmovneq	_CVT_PXL_CLK_GRAN@GOTPCREL(%rip), %rcx
	leal	(%rbx,%r12), %r14d
	imull	%r14d, %esi
	movl	%esi, %eax
	xorl	%edx, %edx
	divl	(%rcx)
	subl	%edx, %esi
	movq	16(%rbp), %rdx
	movl	%ebx, %eax
	shrl	$31, %eax
	addl	%ebx, %eax
	sarl	%eax
	movq	_CVT_RB_H_SYNC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	subl	%eax, %ebx
LBB0_25:
	subl	%ecx, %ebx
	leal	(%rcx,%r12), %eax
	addl	%ebx, %eax
	subl	%eax, %r14d
	movq	_V4L2_DV_BT_656_1120@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 72(%rdx)
	leal	(%r15,%r10), %eax
	movq	%r8, 64(%rdx)
	movl	%r12d, (%rdx)
	movl	%r13d, 4(%rdx)
	movl	%ebx, 8(%rdx)
	movl	%r15d, 12(%rdx)
	movl	%ecx, 16(%rdx)
	movl	%r10d, 20(%rdx)
	movl	%r14d, 24(%rdx)
	testl	%r9d, %r9d
	je	LBB0_27
## %bb.26:
	addl	%eax, %eax
	subl	%eax, %edi
	subl	%r13d, %edi
	movl	%edi, %ecx
	shrl	%ecx
	subl	%ecx, %edi
	movl	%edi, 32(%rdx)
	movl	%r15d, 36(%rdx)
	movl	%r10d, 40(%rdx)
	movq	_V4L2_DV_FL_HALF_LINE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, 48(%rdx)
	movq	_V4L2_DV_INTERLACED@GOTPCREL(%rip), %rax
	movl	%ecx, %edi
	jmp	LBB0_28
LBB0_27:
	addl	%r13d, %eax
	subl	%eax, %edi
	movq	_V4L2_DV_PROGRESSIVE@GOTPCREL(%rip), %rax
LBB0_28:
	movl	(%rax), %eax
	movl	%edi, 28(%rdx)
	movl	%eax, 56(%rdx)
	movl	%esi, 44(%rdx)
	movq	_V4L2_DV_BT_STD_CVT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 52(%rdx)
	movl	$1, %eax
	cmpq	%r8, %r11
	je	LBB0_30
## %bb.29:
	movq	_V4L2_DV_FL_REDUCED_BLANKING@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	%ecx, 48(%rdx)
LBB0_30:
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_16, LBB0_16-LJTI0_0
.set L0_0_set_19, LBB0_19-LJTI0_0
.set L0_0_set_20, LBB0_20-LJTI0_0
.set L0_0_set_17, LBB0_17-LJTI0_0
.set L0_0_set_22, LBB0_22-LJTI0_0
LJTI0_0:
	.long	L0_0_set_16
	.long	L0_0_set_19
	.long	L0_0_set_20
	.long	L0_0_set_17
	.long	L0_0_set_22
	.end_data_region
                                        ## -- End function
	.comm	_V4L2_DV_VSYNC_POS_POL,8,3      ## @V4L2_DV_VSYNC_POS_POL
	.comm	_V4L2_DV_HSYNC_POS_POL,8,3      ## @V4L2_DV_HSYNC_POS_POL
	.comm	_CVT_RB_V_BPORCH,4,2            ## @CVT_RB_V_BPORCH
	.comm	_CVT_RB_MIN_V_BLANK,4,2         ## @CVT_RB_MIN_V_BLANK
	.comm	_CVT_RB_V2_MIN_V_FPORCH,4,2     ## @CVT_RB_V2_MIN_V_FPORCH
	.comm	_CVT_RB_V_FPORCH,4,2            ## @CVT_RB_V_FPORCH
	.comm	_CVT_RB_MIN_V_BPORCH,4,2        ## @CVT_RB_MIN_V_BPORCH
	.comm	_CVT_MIN_V_PORCH_RND,4,2        ## @CVT_MIN_V_PORCH_RND
	.comm	_CVT_MIN_VSYNC_BP,4,2           ## @CVT_MIN_VSYNC_BP
	.comm	_CVT_MIN_V_BPORCH,4,2           ## @CVT_MIN_V_BPORCH
	.comm	_CVT_RB_V2_H_BLANK,4,2          ## @CVT_RB_V2_H_BLANK
	.comm	_CVT_RB_H_BLANK,4,2             ## @CVT_RB_H_BLANK
	.comm	_CVT_PXL_CLK_GRAN_RB_V2,4,2     ## @CVT_PXL_CLK_GRAN_RB_V2
	.comm	_CVT_PXL_CLK_GRAN,4,2           ## @CVT_PXL_CLK_GRAN
	.comm	_CVT_RB_H_SYNC,4,2              ## @CVT_RB_H_SYNC
	.comm	_CVT_C_PRIME,4,2                ## @CVT_C_PRIME
	.comm	_CVT_M_PRIME,4,2                ## @CVT_M_PRIME
	.comm	_CVT_CELL_GRAN,4,2              ## @CVT_CELL_GRAN
	.comm	_CVT_HSYNC_PERCENT,4,2          ## @CVT_HSYNC_PERCENT
	.comm	_V4L2_DV_BT_656_1120,4,2        ## @V4L2_DV_BT_656_1120
	.comm	_V4L2_DV_PROGRESSIVE,4,2        ## @V4L2_DV_PROGRESSIVE
	.comm	_V4L2_DV_FL_HALF_LINE,4,2       ## @V4L2_DV_FL_HALF_LINE
	.comm	_V4L2_DV_INTERLACED,4,2         ## @V4L2_DV_INTERLACED
	.comm	_V4L2_DV_BT_STD_CVT,4,2         ## @V4L2_DV_BT_STD_CVT
	.comm	_V4L2_DV_FL_REDUCED_BLANKING,4,2 ## @V4L2_DV_FL_REDUCED_BLANKING
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_v4l2_detect_cvt                ; -- Begin function v4l2_detect_cvt
	.p2align	2
_v4l2_detect_cvt:                       ; @v4l2_detect_cvt
	.cfi_startproc
; %bb.0:
	sub	w8, w2, #9
	cmn	w8, #5
	b.lo	LBB0_30
; %bb.1:
Lloh0:
	adrp	x8, _V4L2_DV_VSYNC_POS_POL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _V4L2_DV_VSYNC_POS_POL@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x8]
Lloh3:
	adrp	x8, _V4L2_DV_HSYNC_POS_POL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _V4L2_DV_HSYNC_POS_POL@GOTPAGEOFF]
Lloh5:
	ldr	x8, [x8]
	cmp	x9, x4
	ccmp	x8, x4, #4, ne
	b.ne	LBB0_30
; %bb.2:
	mov	w8, #0
	cmp	w2, #8
	ccmp	x9, x4, #4, eq
	cset	w11, eq
	cmp	w3, #0
	cset	w10, ne
	cmp	w2, #7
	cset	w12, hi
	cbz	w1, LBB0_27
; %bb.3:
	and	w12, w12, w11
	tbnz	w12, #0, LBB0_27
; %bb.4:
	orr	w10, w10, w11
	cbz	w10, LBB0_27
; %bb.5:
	mov	w12, #16960
	movk	w12, #15, lsl #16
	cmp	x9, x4
	b.ne	LBB0_7
; %bb.6:
Lloh6:
	adrp	x8, _CVT_MIN_V_PORCH_RND@GOTPAGE
Lloh7:
	ldr	x8, [x8, _CVT_MIN_V_PORCH_RND@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
Lloh9:
	adrp	x10, _CVT_MIN_VSYNC_BP@GOTPAGE
Lloh10:
	ldr	x10, [x10, _CVT_MIN_VSYNC_BP@GOTPAGEOFF]
Lloh11:
	ldr	w10, [x10]
	mul	w10, w10, w1
	udiv	w10, w10, w12
	sub	w10, w10, w2
	add	w12, w10, #1
Lloh12:
	adrp	x13, _CVT_MIN_V_BPORCH@GOTPAGE
Lloh13:
	ldr	x13, [x13, _CVT_MIN_V_BPORCH@GOTPAGEOFF]
	b	LBB0_9
LBB0_7:
	tbz	w11, #0, LBB0_10
; %bb.8:
Lloh14:
	adrp	x8, _CVT_RB_V_FPORCH@GOTPAGE
Lloh15:
	ldr	x8, [x8, _CVT_RB_V_FPORCH@GOTPAGEOFF]
Lloh16:
	adrp	x10, _CVT_RB_MIN_V_BLANK@GOTPAGE
Lloh17:
	ldr	x10, [x10, _CVT_RB_MIN_V_BLANK@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
Lloh19:
	ldr	w10, [x10]
	mul	w10, w10, w1
	udiv	w10, w10, w12
	add	w12, w8, w2
	sub	w10, w10, w12
	add	w12, w10, #1
Lloh20:
	adrp	x13, _CVT_RB_MIN_V_BPORCH@GOTPAGE
Lloh21:
	ldr	x13, [x13, _CVT_RB_MIN_V_BPORCH@GOTPAGEOFF]
LBB0_9:
	ldr	w13, [x13]
	cmp	w12, w13
	csinc	w10, w13, w10, le
	b	LBB0_11
LBB0_10:
Lloh22:
	adrp	x8, _CVT_RB_V_BPORCH@GOTPAGE
Lloh23:
	ldr	x8, [x8, _CVT_RB_V_BPORCH@GOTPAGEOFF]
Lloh24:
	ldr	w10, [x8]
Lloh25:
	adrp	x8, _CVT_RB_MIN_V_BLANK@GOTPAGE
Lloh26:
	ldr	x8, [x8, _CVT_RB_MIN_V_BLANK@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
	mul	w8, w8, w1
	udiv	w8, w8, w12
	sub	w8, w8, w10
	sub	w8, w8, #7
Lloh28:
	adrp	x12, _CVT_RB_V2_MIN_V_FPORCH@GOTPAGE
Lloh29:
	ldr	x12, [x12, _CVT_RB_V2_MIN_V_FPORCH@GOTPAGEOFF]
Lloh30:
	ldr	w12, [x12]
	cmp	w8, w12
	csel	w8, w8, w12, gt
LBB0_11:
	add	w12, w10, w2
	add	w12, w12, w8
	sub	w12, w0, w12
	add	w13, w8, w2
	add	w10, w13, w10
	sub	w10, w0, w10, lsl #1
	cmp	w5, #0
	csinc	w10, w10, w12, ne
	ands	w10, w10, #0xfffffffe
	b.lt	LBB0_30
; %bb.12:
	sub	w12, w2, #4
	cmp	w12, #4
	b.hi	LBB0_30
; %bb.13:
Lloh31:
	adrp	x13, lJTI0_0@PAGE
Lloh32:
	add	x13, x13, lJTI0_0@PAGEOFF
	adr	x14, LBB0_14
	ldrb	w15, [x13, x12]
	add	x14, x14, x15, lsl #2
	br	x14
LBB0_14:
	lsl	w12, w10, #2
	mov	w13, #21846
	movk	w13, #21845, lsl #16
	smull	x12, w12, w13
	lsr	x13, x12, #63
	lsr	x12, x12, #32
	b	LBB0_17
LBB0_15:
	lsl	w12, w10, #4
	mov	w13, #36409
	movk	w13, #14563, lsl #16
	smull	x12, w12, w13
	lsr	x13, x12, #63
	asr	x12, x12, #33
	b	LBB0_17
LBB0_16:
	lsl	w12, w10, #4
	mov	w13, #26215
	movk	w13, #26214, lsl #16
	smull	x12, w12, w13
	lsr	x13, x12, #63
	asr	x12, x12, #34
LBB0_17:
	add	w3, w12, w13
LBB0_18:
	and	w12, w3, #0xfffffff8
	cmp	w11, #0
	csel	w12, w12, w3, ne
	cmp	x9, x4
	b.ne	LBB0_20
; %bb.19:
Lloh33:
	adrp	x11, _CVT_C_PRIME@GOTPAGE
Lloh34:
	ldr	x11, [x11, _CVT_C_PRIME@GOTPAGEOFF]
Lloh35:
	ldr	w11, [x11]
	mov	w13, #100
	mul	w11, w11, w13
Lloh36:
	adrp	x13, _CVT_M_PRIME@GOTPAGE
Lloh37:
	ldr	x13, [x13, _CVT_M_PRIME@GOTPAGEOFF]
Lloh38:
	ldr	w13, [x13]
	mov	w14, #34464
	movk	w14, #1, lsl #16
	mul	w13, w13, w14
	udiv	w13, w13, w1
	sub	w11, w11, w13
	mov	w13, #2000
	cmp	w11, #2000
	csel	w11, w11, w13, hi
	mul	w13, w11, w12
	mov	w14, #10000
	sub	w11, w14, w11
Lloh39:
	adrp	x14, _CVT_CELL_GRAN@GOTPAGE
Lloh40:
	ldr	x14, [x14, _CVT_CELL_GRAN@GOTPAGEOFF]
	udiv	w11, w13, w11
Lloh41:
	ldr	w14, [x14]
	lsl	w13, w14, #1
	sdiv	w11, w11, w13
	mul	w15, w11, w14
	lsl	w16, w15, #1
	add	w13, w16, w12
	mul	w11, w13, w1
Lloh42:
	adrp	x17, _CVT_PXL_CLK_GRAN@GOTPAGE
Lloh43:
	ldr	x17, [x17, _CVT_PXL_CLK_GRAN@GOTPAGEOFF]
Lloh44:
	ldr	w17, [x17]
	udiv	w11, w11, w17
	mul	w11, w11, w17
	mov	w17, #1
	bfi	w17, w15, #1, #31
Lloh45:
	adrp	x15, _CVT_HSYNC_PERCENT@GOTPAGE
Lloh46:
	ldr	x15, [x15, _CVT_HSYNC_PERCENT@GOTPAGEOFF]
	cmp	w16, #0
	csel	w17, w17, w16, lt
Lloh47:
	ldr	w15, [x15]
	mul	w15, w13, w15
	mov	w1, #34079
	movk	w1, #20971, lsl #16
	smull	x15, w15, w1
	lsr	x1, x15, #63
	asr	x15, x15, #37
	add	w15, w15, w1
	sdiv	w15, w15, w14
	mul	w14, w15, w14
	sub	w15, w16, w17, asr #1
	b	LBB0_21
LBB0_20:
Lloh48:
	adrp	x13, _CVT_RB_V2_H_BLANK@GOTPAGE
Lloh49:
	ldr	x13, [x13, _CVT_RB_V2_H_BLANK@GOTPAGEOFF]
Lloh50:
	adrp	x14, _CVT_RB_H_BLANK@GOTPAGE
Lloh51:
	ldr	x14, [x14, _CVT_RB_H_BLANK@GOTPAGEOFF]
	cmp	w11, #0
	csel	x11, x14, x13, ne
	ldr	w15, [x11]
Lloh52:
	adrp	x11, _CVT_PXL_CLK_GRAN_RB_V2@GOTPAGE
Lloh53:
	ldr	x11, [x11, _CVT_PXL_CLK_GRAN_RB_V2@GOTPAGEOFF]
Lloh54:
	adrp	x13, _CVT_PXL_CLK_GRAN@GOTPAGE
Lloh55:
	ldr	x13, [x13, _CVT_PXL_CLK_GRAN@GOTPAGEOFF]
	csel	x11, x13, x11, ne
	ldr	w11, [x11]
	add	w13, w15, w12
	mul	w14, w13, w1
	udiv	w14, w14, w11
	mul	w11, w14, w11
	cmp	w15, #0
	cinc	w16, w15, lt
Lloh56:
	adrp	x14, _CVT_RB_H_SYNC@GOTPAGE
Lloh57:
	ldr	x14, [x14, _CVT_RB_H_SYNC@GOTPAGEOFF]
Lloh58:
	ldr	w14, [x14]
	sub	w15, w15, w16, asr #1
LBB0_21:
	sub	w15, w15, w14
Lloh59:
	adrp	x16, _V4L2_DV_BT_656_1120@GOTPAGE
Lloh60:
	ldr	x16, [x16, _V4L2_DV_BT_656_1120@GOTPAGEOFF]
Lloh61:
	ldr	w16, [x16]
	str	w16, [x6, #72]
	str	x4, [x6, #64]
	stp	w12, w10, [x6]
	stp	w15, w8, [x6, #8]
	stp	w14, w2, [x6, #16]
	add	w12, w14, w12
	add	w12, w12, w15
	sub	w12, w13, w12
	str	w12, [x6, #24]
	add	w12, w8, w2
	cbz	w5, LBB0_23
; %bb.22:
	sub	w12, w0, w12, lsl #1
	sub	w12, w12, w10
	lsr	w10, w12, #1
	sub	w12, w12, w10
	stp	w12, w8, [x6, #32]
	str	w2, [x6, #40]
Lloh62:
	adrp	x8, _V4L2_DV_FL_HALF_LINE@GOTPAGE
Lloh63:
	ldr	x8, [x8, _V4L2_DV_FL_HALF_LINE@GOTPAGEOFF]
Lloh64:
	ldr	w8, [x8]
	ldr	w12, [x6, #48]
	orr	w8, w12, w8
	str	w8, [x6, #48]
Lloh65:
	adrp	x8, _V4L2_DV_INTERLACED@GOTPAGE
Lloh66:
	ldr	x8, [x8, _V4L2_DV_INTERLACED@GOTPAGEOFF]
	b	LBB0_24
LBB0_23:
	add	w8, w12, w10
	sub	w10, w0, w8
Lloh67:
	adrp	x8, _V4L2_DV_PROGRESSIVE@GOTPAGE
Lloh68:
	ldr	x8, [x8, _V4L2_DV_PROGRESSIVE@GOTPAGEOFF]
LBB0_24:
	ldr	w8, [x8]
	str	w10, [x6, #28]
	str	w11, [x6, #44]
Lloh69:
	adrp	x10, _V4L2_DV_BT_STD_CVT@GOTPAGE
Lloh70:
	ldr	x10, [x10, _V4L2_DV_BT_STD_CVT@GOTPAGEOFF]
Lloh71:
	ldr	w10, [x10]
	stp	w10, w8, [x6, #52]
	cmp	x9, x4
	b.eq	LBB0_26
; %bb.25:
Lloh72:
	adrp	x8, _V4L2_DV_FL_REDUCED_BLANKING@GOTPAGE
Lloh73:
	ldr	x8, [x8, _V4L2_DV_FL_REDUCED_BLANKING@GOTPAGEOFF]
Lloh74:
	ldr	w8, [x8]
	ldr	w9, [x6, #48]
	orr	w8, w9, w8
	str	w8, [x6, #48]
LBB0_26:
	mov	w8, #1
LBB0_27:
	mov	x0, x8
	ret
LBB0_28:
	mov	w3, #1280
	cmp	w10, #1024
	b.eq	LBB0_18
; %bb.29:
	cmp	w10, #768
	b.eq	LBB0_18
LBB0_30:
	mov	w0, #0
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh18
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpAdd	Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGot	Lloh54, Lloh55
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_14-LBB0_14)>>2
	.byte	(LBB0_15-LBB0_14)>>2
	.byte	(LBB0_16-LBB0_14)>>2
	.byte	(LBB0_28-LBB0_14)>>2
	.byte	(LBB0_18-LBB0_14)>>2
                                        ; -- End function
	.comm	_V4L2_DV_VSYNC_POS_POL,8,3      ; @V4L2_DV_VSYNC_POS_POL
	.comm	_V4L2_DV_HSYNC_POS_POL,8,3      ; @V4L2_DV_HSYNC_POS_POL
	.comm	_CVT_RB_V_BPORCH,4,2            ; @CVT_RB_V_BPORCH
	.comm	_CVT_RB_MIN_V_BLANK,4,2         ; @CVT_RB_MIN_V_BLANK
	.comm	_CVT_RB_V2_MIN_V_FPORCH,4,2     ; @CVT_RB_V2_MIN_V_FPORCH
	.comm	_CVT_RB_V_FPORCH,4,2            ; @CVT_RB_V_FPORCH
	.comm	_CVT_RB_MIN_V_BPORCH,4,2        ; @CVT_RB_MIN_V_BPORCH
	.comm	_CVT_MIN_V_PORCH_RND,4,2        ; @CVT_MIN_V_PORCH_RND
	.comm	_CVT_MIN_VSYNC_BP,4,2           ; @CVT_MIN_VSYNC_BP
	.comm	_CVT_MIN_V_BPORCH,4,2           ; @CVT_MIN_V_BPORCH
	.comm	_CVT_RB_V2_H_BLANK,4,2          ; @CVT_RB_V2_H_BLANK
	.comm	_CVT_RB_H_BLANK,4,2             ; @CVT_RB_H_BLANK
	.comm	_CVT_PXL_CLK_GRAN_RB_V2,4,2     ; @CVT_PXL_CLK_GRAN_RB_V2
	.comm	_CVT_PXL_CLK_GRAN,4,2           ; @CVT_PXL_CLK_GRAN
	.comm	_CVT_RB_H_SYNC,4,2              ; @CVT_RB_H_SYNC
	.comm	_CVT_C_PRIME,4,2                ; @CVT_C_PRIME
	.comm	_CVT_M_PRIME,4,2                ; @CVT_M_PRIME
	.comm	_CVT_CELL_GRAN,4,2              ; @CVT_CELL_GRAN
	.comm	_CVT_HSYNC_PERCENT,4,2          ; @CVT_HSYNC_PERCENT
	.comm	_V4L2_DV_BT_656_1120,4,2        ; @V4L2_DV_BT_656_1120
	.comm	_V4L2_DV_PROGRESSIVE,4,2        ; @V4L2_DV_PROGRESSIVE
	.comm	_V4L2_DV_FL_HALF_LINE,4,2       ; @V4L2_DV_FL_HALF_LINE
	.comm	_V4L2_DV_INTERLACED,4,2         ; @V4L2_DV_INTERLACED
	.comm	_V4L2_DV_BT_STD_CVT,4,2         ; @V4L2_DV_BT_STD_CVT
	.comm	_V4L2_DV_FL_REDUCED_BLANKING,4,2 ; @V4L2_DV_FL_REDUCED_BLANKING
.subsections_via_symbols
