	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_mv88e6352_port_set_policy      ## -- Begin function mv88e6352_port_set_policy
	.p2align	4, 0x90
_mv88e6352_port_set_policy:             ## @mv88e6352_port_set_policy
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	addl	$-128, %edx
	cmpl	$8, %edx
	jae	LBB0_1
## %bb.2:
	movl	%ecx, %ebx
	movl	%esi, %r14d
	movq	%rdi, %r15
	movslq	%edx, %rax
	leaq	l_switch.table.mv88e6352_port_set_policy(%rip), %rcx
	movq	(%rcx,%rax,8), %r13
	movl	(%r13), %edi
	callq	___bf_shf
	addl	$-136, %ebx
	cmpl	$4, %ebx
	jae	LBB0_1
## %bb.3:
	movl	%eax, %r12d
	movl	(%r13), %r13d
	movslq	%ebx, %rax
	leaq	l_switch.table.mv88e6352_port_set_policy.1(%rip), %rcx
	movq	(%rcx,%rax,8), %rax
	movl	(%rax), %ebx
	movq	_MV88E6XXX_PORT_POLICY_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	leaq	-44(%rbp), %rcx
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_mv88e6xxx_port_read
	testl	%eax, %eax
	jne	LBB0_5
## %bb.4:
	movl	-44(%rbp), %eax
	movl	%r12d, %ecx
	shll	%cl, %ebx
	xorl	%eax, %ebx
	andl	%r13d, %ebx
	xorl	%eax, %ebx
	movl	%ebx, -44(%rbp)
	movq	_MV88E6XXX_PORT_POLICY_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%ebx, %ecx
	callq	_mv88e6xxx_port_write
	jmp	LBB0_5
LBB0_1:
	movq	_EOPNOTSUPP@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_5:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MV88E6XXX_PORT_POLICY_CTL_DA_MASK,4,2 ## @MV88E6XXX_PORT_POLICY_CTL_DA_MASK
	.comm	_MV88E6XXX_PORT_POLICY_CTL_SA_MASK,4,2 ## @MV88E6XXX_PORT_POLICY_CTL_SA_MASK
	.comm	_MV88E6XXX_PORT_POLICY_CTL_VTU_MASK,4,2 ## @MV88E6XXX_PORT_POLICY_CTL_VTU_MASK
	.comm	_MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK,4,2 ## @MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK
	.comm	_MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK,4,2 ## @MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK
	.comm	_MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK,4,2 ## @MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK
	.comm	_MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK,4,2 ## @MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK
	.comm	_MV88E6XXX_PORT_POLICY_CTL_UDP_MASK,4,2 ## @MV88E6XXX_PORT_POLICY_CTL_UDP_MASK
	.comm	_EOPNOTSUPP,4,2                 ## @EOPNOTSUPP
	.comm	_MV88E6XXX_PORT_POLICY_CTL_NORMAL,4,2 ## @MV88E6XXX_PORT_POLICY_CTL_NORMAL
	.comm	_MV88E6XXX_PORT_POLICY_CTL_MIRROR,4,2 ## @MV88E6XXX_PORT_POLICY_CTL_MIRROR
	.comm	_MV88E6XXX_PORT_POLICY_CTL_TRAP,4,2 ## @MV88E6XXX_PORT_POLICY_CTL_TRAP
	.comm	_MV88E6XXX_PORT_POLICY_CTL_DISCARD,4,2 ## @MV88E6XXX_PORT_POLICY_CTL_DISCARD
	.comm	_MV88E6XXX_PORT_POLICY_CTL,4,2  ## @MV88E6XXX_PORT_POLICY_CTL
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.mv88e6352_port_set_policy
l_switch.table.mv88e6352_port_set_policy:
	.quad	_MV88E6XXX_PORT_POLICY_CTL_VTU_MASK
	.quad	_MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK
	.quad	_MV88E6XXX_PORT_POLICY_CTL_UDP_MASK
	.quad	_MV88E6XXX_PORT_POLICY_CTL_SA_MASK
	.quad	_MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK
	.quad	_MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK
	.quad	_MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK
	.quad	_MV88E6XXX_PORT_POLICY_CTL_DA_MASK

	.p2align	3                               ## @switch.table.mv88e6352_port_set_policy.1
l_switch.table.mv88e6352_port_set_policy.1:
	.quad	_MV88E6XXX_PORT_POLICY_CTL_TRAP
	.quad	_MV88E6XXX_PORT_POLICY_CTL_NORMAL
	.quad	_MV88E6XXX_PORT_POLICY_CTL_MIRROR
	.quad	_MV88E6XXX_PORT_POLICY_CTL_DISCARD

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_mv88e6352_port_set_policy      ; -- Begin function mv88e6352_port_set_policy
	.p2align	2
_mv88e6352_port_set_policy:             ; @mv88e6352_port_set_policy
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	sub	w8, w2, #128
	cmp	w8, #8
	b.hs	LBB0_4
; %bb.1:
	mov	x22, x3
	mov	x19, x1
	mov	x20, x0
Lloh0:
	adrp	x9, l_switch.table.mv88e6352_port_set_policy@PAGE
Lloh1:
	add	x9, x9, l_switch.table.mv88e6352_port_set_policy@PAGEOFF
	ldr	x23, [x9, w8, sxtw #3]
	ldr	w0, [x23]
	bl	___bf_shf
	sub	w8, w22, #136
	cmp	w8, #4
	b.hs	LBB0_4
; %bb.2:
	mov	x21, x0
	ldr	w22, [x23]
Lloh2:
	adrp	x9, l_switch.table.mv88e6352_port_set_policy.1@PAGE
Lloh3:
	add	x9, x9, l_switch.table.mv88e6352_port_set_policy.1@PAGEOFF
	ldr	x8, [x9, w8, sxtw #3]
	ldr	w24, [x8]
Lloh4:
	adrp	x23, _MV88E6XXX_PORT_POLICY_CTL@GOTPAGE
Lloh5:
	ldr	x23, [x23, _MV88E6XXX_PORT_POLICY_CTL@GOTPAGEOFF]
	ldr	w2, [x23]
	add	x3, sp, #12
	mov	x0, x20
	mov	x1, x19
	bl	_mv88e6xxx_port_read
	cbnz	w0, LBB0_5
; %bb.3:
	ldr	w8, [sp, #12]
	bic	w8, w8, w22
	lsl	w9, w24, w21
	and	w9, w9, w22
	orr	w3, w8, w9
	str	w3, [sp, #12]
	ldr	w2, [x23]
	mov	x0, x20
	mov	x1, x19
	bl	_mv88e6xxx_port_write
	b	LBB0_5
LBB0_4:
Lloh6:
	adrp	x8, _EOPNOTSUPP@GOTPAGE
Lloh7:
	ldr	x8, [x8, _EOPNOTSUPP@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_5:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_MV88E6XXX_PORT_POLICY_CTL_DA_MASK,4,2 ; @MV88E6XXX_PORT_POLICY_CTL_DA_MASK
	.comm	_MV88E6XXX_PORT_POLICY_CTL_SA_MASK,4,2 ; @MV88E6XXX_PORT_POLICY_CTL_SA_MASK
	.comm	_MV88E6XXX_PORT_POLICY_CTL_VTU_MASK,4,2 ; @MV88E6XXX_PORT_POLICY_CTL_VTU_MASK
	.comm	_MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK,4,2 ; @MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK
	.comm	_MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK,4,2 ; @MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK
	.comm	_MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK,4,2 ; @MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK
	.comm	_MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK,4,2 ; @MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK
	.comm	_MV88E6XXX_PORT_POLICY_CTL_UDP_MASK,4,2 ; @MV88E6XXX_PORT_POLICY_CTL_UDP_MASK
	.comm	_EOPNOTSUPP,4,2                 ; @EOPNOTSUPP
	.comm	_MV88E6XXX_PORT_POLICY_CTL_NORMAL,4,2 ; @MV88E6XXX_PORT_POLICY_CTL_NORMAL
	.comm	_MV88E6XXX_PORT_POLICY_CTL_MIRROR,4,2 ; @MV88E6XXX_PORT_POLICY_CTL_MIRROR
	.comm	_MV88E6XXX_PORT_POLICY_CTL_TRAP,4,2 ; @MV88E6XXX_PORT_POLICY_CTL_TRAP
	.comm	_MV88E6XXX_PORT_POLICY_CTL_DISCARD,4,2 ; @MV88E6XXX_PORT_POLICY_CTL_DISCARD
	.comm	_MV88E6XXX_PORT_POLICY_CTL,4,2  ; @MV88E6XXX_PORT_POLICY_CTL
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.mv88e6352_port_set_policy
l_switch.table.mv88e6352_port_set_policy:
	.quad	_MV88E6XXX_PORT_POLICY_CTL_VTU_MASK
	.quad	_MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK
	.quad	_MV88E6XXX_PORT_POLICY_CTL_UDP_MASK
	.quad	_MV88E6XXX_PORT_POLICY_CTL_SA_MASK
	.quad	_MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK
	.quad	_MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK
	.quad	_MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK
	.quad	_MV88E6XXX_PORT_POLICY_CTL_DA_MASK

	.p2align	3                               ; @switch.table.mv88e6352_port_set_policy.1
l_switch.table.mv88e6352_port_set_policy.1:
	.quad	_MV88E6XXX_PORT_POLICY_CTL_TRAP
	.quad	_MV88E6XXX_PORT_POLICY_CTL_NORMAL
	.quad	_MV88E6XXX_PORT_POLICY_CTL_MIRROR
	.quad	_MV88E6XXX_PORT_POLICY_CTL_DISCARD

.subsections_via_symbols
