	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function xenon_emmc_phy_set
_xenon_emmc_phy_set:                    ## @xenon_emmc_phy_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, -44(%rbp)                 ## 4-byte Spill
	movq	%rdi, %r15
	callq	_sdhci_priv
	movq	%rax, %rdi
	callq	_sdhci_pltfm_priv
	movq	%rax, %r14
	movq	16(%rax), %rbx
	movq	24(%rax), %rax
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
	movl	(%r15), %edi
	callq	_mmc_dev
	leaq	L_.str(%rip), %rsi
	movl	%eax, %edi
	callq	_dev_dbg
	movl	20(%rbx), %esi
	movq	%r15, %rdi
	callq	_sdhci_readl
	movq	_XENON_FC_DQ_RECEN@GOTPCREL(%rip), %rcx
	movq	_XENON_FC_CMD_RECEN@GOTPCREL(%rip), %rdx
	movq	_XENON_FC_QSP_RECEN@GOTPCREL(%rip), %rsi
	movq	_XENON_OEN_QSN@GOTPCREL(%rip), %rdi
	orl	(%rcx), %eax
	orl	(%rdx), %eax
	orl	(%rsi), %eax
	orl	(%rdi), %eax
	movq	_XENON_FC_ALL_CMOS_RECEIVER@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	%rbx, -64(%rbp)                 ## 8-byte Spill
	movl	20(%rbx), %edx
	movq	%r14, %rbx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_sdhci_writel
	movq	(%r14), %r14
	movq	_EMMC_5_0_PHY@GOTPCREL(%rip), %rax
	movq	(%rax), %r12
	cmpq	%r12, %r14
	jne	LBB0_1
## %bb.2:
	movq	_XENON_EMMC_5_0_PHY_PAD_CONTROL@GOTPCREL(%rip), %r13
	jmp	LBB0_3
LBB0_1:
	movq	_XENON_EMMC_PHY_PAD_CONTROL1@GOTPCREL(%rip), %r13
LBB0_3:
	movl	(%r13), %esi
	movq	%r15, %rdi
	callq	_sdhci_readl
	movq	_XENON_EMMC5_FC_CMD_PD@GOTPCREL(%rip), %rcx
	movq	_XENON_EMMC5_1_FC_CMD_PD@GOTPCREL(%rip), %rdx
	movq	_XENON_EMMC5_FC_DQ_PD@GOTPCREL(%rip), %rsi
	movl	(%rsi), %edi
	movq	_XENON_EMMC5_1_FC_DQ_PD@GOTPCREL(%rip), %rsi
	orl	(%rcx), %edi
	movl	(%rsi), %esi
	orl	(%rdx), %esi
	cmpq	%r12, %r14
	movq	_XENON_EMMC5_1_FC_CMD_PU@GOTPCREL(%rip), %rcx
	cmoveq	_XENON_EMMC5_FC_CMD_PU@GOTPCREL(%rip), %rcx
	movq	_XENON_EMMC5_1_FC_DQ_PU@GOTPCREL(%rip), %rdx
	cmoveq	_XENON_EMMC5_FC_DQ_PU@GOTPCREL(%rip), %rdx
	cmovel	%edi, %esi
	orl	(%rcx), %eax
	orl	(%rdx), %eax
	notl	%esi
	andl	%eax, %esi
	movl	(%r13), %edx
	movq	%r15, %rdi
	callq	_sdhci_writel
	movq	_MMC_TIMING_LEGACY@GOTPCREL(%rip), %rax
	movl	-44(%rbp), %r14d                ## 4-byte Reload
	cmpb	%r14b, (%rax)
	jne	LBB0_5
## %bb.4:
	movzbl	%r14b, %esi
	movq	%r15, %rdi
	callq	_xenon_emmc_phy_slow_mode
	jmp	LBB0_15
LBB0_5:
	movq	-64(%rbp), %r12                 ## 8-byte Reload
	movl	16(%r12), %esi
	movq	%r15, %rdi
	callq	_sdhci_readl
	movq	8(%rbx), %rcx
	movq	_MMC_TYPE_SDIO@GOTPCREL(%rip), %rdx
	movq	_XENON_TIMING_ADJUST_SDIO_MODE@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	movl	%esi, %edi
	orl	%eax, %edi
	notl	%esi
	andl	%eax, %esi
	cmpq	(%rdx), %rcx
	cmovel	%edi, %esi
	movl	16(%r12), %edx
	movq	%r15, %rdi
	callq	_sdhci_writel
	movzbl	%r14b, %esi
	movq	%r15, %rdi
	callq	_xenon_emmc_phy_slow_mode
	testq	%rax, %rax
	jne	LBB0_15
## %bb.6:
	movl	12(%r12), %esi
	movq	%r15, %rdi
	callq	_sdhci_readl
	movq	_XENON_ZNR_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_XENON_ZNR_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	movq	_XENON_ZPR_MASK@GOTPCREL(%rip), %rsi
	orl	(%rsi), %edx
	notl	%edx
	andl	%eax, %edx
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %esi
	shll	%cl, %esi
	orl	4(%rax), %esi
	orl	%edx, %esi
	movl	12(%r12), %edx
	movq	%r15, %rdi
	callq	_sdhci_writel
	movq	_SDHCI_CLOCK_CONTROL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_sdhci_readl
	movq	_SDHCI_CLOCK_CARD_EN@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edx
	movq	%r15, %rdi
	callq	_sdhci_writew
	movl	8(%r12), %esi
	movq	%r15, %rdi
	callq	_sdhci_readl
	cmpb	$-128, %r14b
	je	LBB0_10
## %bb.7:
	cmpb	$-126, %r14b
	je	LBB0_10
## %bb.8:
	movq	_XENON_DQ_DDR_MODE_MASK@GOTPCREL(%rip), %rcx
	cmpb	$-127, %r14b
	jne	LBB0_11
## %bb.9:
	movl	(%rcx), %edx
	movq	_XENON_DQ_DDR_MODE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	movq	_XENON_CMD_DDR_MODE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	%eax, %ecx
	orl	%edx, %ecx
	movq	_XENON_DQ_ASYNC_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	%ecx, %esi
	jmp	LBB0_12
LBB0_10:
	movq	_XENON_DQ_DDR_MODE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_XENON_DQ_DDR_MODE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	movq	_XENON_CMD_DDR_MODE@GOTPCREL(%rip), %rcx
	movq	_XENON_DQ_ASYNC_MODE@GOTPCREL(%rip), %rdi
	movl	(%rcx), %esi
	orl	%eax, %esi
	orl	%edx, %esi
	orl	(%rdi), %esi
	jmp	LBB0_12
LBB0_11:
	movl	(%rcx), %edx
	movq	_XENON_DQ_DDR_MODE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	movq	_XENON_CMD_DDR_MODE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	notl	%edx
	andl	%edx, %eax
	movq	_XENON_DQ_ASYNC_MODE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, %esi
LBB0_12:
	movl	8(%r12), %edx
	movq	%r15, %rdi
	callq	_sdhci_writel
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_sdhci_readl
	orl	(%r13), %eax
	movl	(%rbx), %edx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_sdhci_writew
	cmpb	$-127, %r14b
	jne	LBB0_14
## %bb.13:
	movl	(%r12), %esi
	movl	4(%r12), %edx
	movq	%r15, %rdi
	callq	_sdhci_writel
	jmp	LBB0_15
LBB0_14:
	movq	%r15, %rdi
	callq	_xenon_emmc_phy_disable_strobe
LBB0_15:
	movq	%r15, %rdi
	callq	_xenon_emmc_phy_init
	movl	(%r15), %edi
	callq	_mmc_dev
	leaq	L_.str.1(%rip), %rsi
	movl	%eax, %edi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_dev_dbg                        ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"eMMC PHY setting starts\n"

	.comm	_XENON_FC_DQ_RECEN,4,2          ## @XENON_FC_DQ_RECEN
	.comm	_XENON_FC_CMD_RECEN,4,2         ## @XENON_FC_CMD_RECEN
	.comm	_XENON_FC_QSP_RECEN,4,2         ## @XENON_FC_QSP_RECEN
	.comm	_XENON_OEN_QSN,4,2              ## @XENON_OEN_QSN
	.comm	_XENON_FC_ALL_CMOS_RECEIVER,4,2 ## @XENON_FC_ALL_CMOS_RECEIVER
	.comm	_EMMC_5_0_PHY,8,3               ## @EMMC_5_0_PHY
	.comm	_XENON_EMMC_5_0_PHY_PAD_CONTROL,4,2 ## @XENON_EMMC_5_0_PHY_PAD_CONTROL
	.comm	_XENON_EMMC5_FC_CMD_PU,4,2      ## @XENON_EMMC5_FC_CMD_PU
	.comm	_XENON_EMMC5_FC_DQ_PU,4,2       ## @XENON_EMMC5_FC_DQ_PU
	.comm	_XENON_EMMC5_FC_CMD_PD,4,2      ## @XENON_EMMC5_FC_CMD_PD
	.comm	_XENON_EMMC5_FC_DQ_PD,4,2       ## @XENON_EMMC5_FC_DQ_PD
	.comm	_XENON_EMMC_PHY_PAD_CONTROL1,4,2 ## @XENON_EMMC_PHY_PAD_CONTROL1
	.comm	_XENON_EMMC5_1_FC_CMD_PU,4,2    ## @XENON_EMMC5_1_FC_CMD_PU
	.comm	_XENON_EMMC5_1_FC_DQ_PU,4,2     ## @XENON_EMMC5_1_FC_DQ_PU
	.comm	_XENON_EMMC5_1_FC_CMD_PD,4,2    ## @XENON_EMMC5_1_FC_CMD_PD
	.comm	_XENON_EMMC5_1_FC_DQ_PD,4,2     ## @XENON_EMMC5_1_FC_DQ_PD
	.comm	_MMC_TIMING_LEGACY,1,0          ## @MMC_TIMING_LEGACY
	.comm	_MMC_TYPE_SDIO,8,3              ## @MMC_TYPE_SDIO
	.comm	_XENON_TIMING_ADJUST_SDIO_MODE,4,2 ## @XENON_TIMING_ADJUST_SDIO_MODE
	.comm	_XENON_ZNR_MASK,4,2             ## @XENON_ZNR_MASK
	.comm	_XENON_ZNR_SHIFT,4,2            ## @XENON_ZNR_SHIFT
	.comm	_XENON_ZPR_MASK,4,2             ## @XENON_ZPR_MASK
	.comm	_SDHCI_CLOCK_CONTROL,4,2        ## @SDHCI_CLOCK_CONTROL
	.comm	_SDHCI_CLOCK_CARD_EN,4,2        ## @SDHCI_CLOCK_CARD_EN
	.comm	_XENON_DQ_DDR_MODE_MASK,4,2     ## @XENON_DQ_DDR_MODE_MASK
	.comm	_XENON_DQ_DDR_MODE_SHIFT,4,2    ## @XENON_DQ_DDR_MODE_SHIFT
	.comm	_XENON_CMD_DDR_MODE,4,2         ## @XENON_CMD_DDR_MODE
	.comm	_XENON_DQ_ASYNC_MODE,4,2        ## @XENON_DQ_ASYNC_MODE
L_.str.1:                               ## @.str.1
	.asciz	"eMMC PHY setting completes\n"

	.no_dead_strip	_xenon_emmc_phy_set
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function xenon_emmc_phy_set
_xenon_emmc_phy_set:                    ; @xenon_emmc_phy_set
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x1
	mov	x19, x0
	bl	_sdhci_priv
	bl	_sdhci_pltfm_priv
	mov	x21, x0
	ldp	x22, x23, [x0, #16]
	ldr	w0, [x19]
	bl	_mmc_dev
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_dbg
	ldr	w1, [x22, #20]
	mov	x0, x19
	bl	_sdhci_readl
Lloh2:
	adrp	x8, _XENON_FC_DQ_RECEN@GOTPAGE
Lloh3:
	ldr	x8, [x8, _XENON_FC_DQ_RECEN@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
Lloh5:
	adrp	x9, _XENON_FC_CMD_RECEN@GOTPAGE
Lloh6:
	ldr	x9, [x9, _XENON_FC_CMD_RECEN@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
Lloh8:
	adrp	x10, _XENON_FC_QSP_RECEN@GOTPAGE
Lloh9:
	ldr	x10, [x10, _XENON_FC_QSP_RECEN@GOTPAGEOFF]
Lloh10:
	ldr	w10, [x10]
Lloh11:
	adrp	x11, _XENON_OEN_QSN@GOTPAGE
Lloh12:
	ldr	x11, [x11, _XENON_OEN_QSN@GOTPAGEOFF]
Lloh13:
	ldr	w11, [x11]
Lloh14:
	adrp	x12, _XENON_FC_ALL_CMOS_RECEIVER@GOTPAGE
Lloh15:
	ldr	x12, [x12, _XENON_FC_ALL_CMOS_RECEIVER@GOTPAGEOFF]
Lloh16:
	ldr	w12, [x12]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w1, w8, w12
	ldr	w2, [x22, #20]
	mov	x0, x19
	bl	_sdhci_writel
	ldr	x24, [x21]
Lloh17:
	adrp	x8, _EMMC_5_0_PHY@GOTPAGE
Lloh18:
	ldr	x8, [x8, _EMMC_5_0_PHY@GOTPAGEOFF]
Lloh19:
	adrp	x9, _XENON_EMMC_PHY_PAD_CONTROL1@GOTPAGE
Lloh20:
	ldr	x9, [x9, _XENON_EMMC_PHY_PAD_CONTROL1@GOTPAGEOFF]
Lloh21:
	ldr	x25, [x8]
Lloh22:
	adrp	x8, _XENON_EMMC_5_0_PHY_PAD_CONTROL@GOTPAGE
Lloh23:
	ldr	x8, [x8, _XENON_EMMC_5_0_PHY_PAD_CONTROL@GOTPAGEOFF]
	cmp	x24, x25
	csel	x26, x8, x9, eq
	ldr	w1, [x26]
	mov	x0, x19
	bl	_sdhci_readl
Lloh24:
	adrp	x8, _XENON_EMMC5_FC_CMD_PU@GOTPAGE
Lloh25:
	ldr	x8, [x8, _XENON_EMMC5_FC_CMD_PU@GOTPAGEOFF]
Lloh26:
	adrp	x9, _XENON_EMMC5_1_FC_CMD_PU@GOTPAGE
Lloh27:
	ldr	x9, [x9, _XENON_EMMC5_1_FC_CMD_PU@GOTPAGEOFF]
	cmp	x24, x25
	csel	x8, x8, x9, eq
Lloh28:
	adrp	x9, _XENON_EMMC5_FC_DQ_PU@GOTPAGE
Lloh29:
	ldr	x9, [x9, _XENON_EMMC5_FC_DQ_PU@GOTPAGEOFF]
	ldr	w8, [x8]
Lloh30:
	adrp	x10, _XENON_EMMC5_1_FC_DQ_PU@GOTPAGE
Lloh31:
	ldr	x10, [x10, _XENON_EMMC5_1_FC_DQ_PU@GOTPAGEOFF]
	csel	x9, x9, x10, eq
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w8, w8, w9
Lloh32:
	adrp	x9, _XENON_EMMC5_FC_CMD_PD@GOTPAGE
Lloh33:
	ldr	x9, [x9, _XENON_EMMC5_FC_CMD_PD@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
Lloh35:
	adrp	x10, _XENON_EMMC5_1_FC_CMD_PD@GOTPAGE
Lloh36:
	ldr	x10, [x10, _XENON_EMMC5_1_FC_CMD_PD@GOTPAGEOFF]
Lloh37:
	ldr	w10, [x10]
Lloh38:
	adrp	x11, _XENON_EMMC5_FC_DQ_PD@GOTPAGE
Lloh39:
	ldr	x11, [x11, _XENON_EMMC5_FC_DQ_PD@GOTPAGEOFF]
Lloh40:
	ldr	w11, [x11]
Lloh41:
	adrp	x12, _XENON_EMMC5_1_FC_DQ_PD@GOTPAGE
Lloh42:
	ldr	x12, [x12, _XENON_EMMC5_1_FC_DQ_PD@GOTPAGEOFF]
Lloh43:
	ldr	w12, [x12]
	orr	w9, w11, w9
	orr	w10, w12, w10
	csel	w9, w9, w10, eq
	bic	w1, w8, w9
	ldr	w2, [x26]
	mov	x0, x19
	bl	_sdhci_writel
Lloh44:
	adrp	x8, _MMC_TIMING_LEGACY@GOTPAGE
Lloh45:
	ldr	x8, [x8, _MMC_TIMING_LEGACY@GOTPAGEOFF]
	ldrb	w8, [x8]
	cmp	w8, w20
	b.ne	LBB0_2
; %bb.1:
	mov	x0, x19
	mov	x1, x20
	bl	_xenon_emmc_phy_slow_mode
	b	LBB0_12
LBB0_2:
	ldr	w1, [x22, #16]
	mov	x0, x19
	bl	_sdhci_readl
	ldr	x8, [x21, #8]
Lloh46:
	adrp	x9, _MMC_TYPE_SDIO@GOTPAGE
Lloh47:
	ldr	x9, [x9, _MMC_TYPE_SDIO@GOTPAGEOFF]
Lloh48:
	ldr	x9, [x9]
Lloh49:
	adrp	x10, _XENON_TIMING_ADJUST_SDIO_MODE@GOTPAGE
Lloh50:
	ldr	x10, [x10, _XENON_TIMING_ADJUST_SDIO_MODE@GOTPAGEOFF]
Lloh51:
	ldr	w10, [x10]
	orr	w11, w10, w0
	bic	w10, w0, w10
	cmp	x8, x9
	csel	w1, w11, w10, eq
	ldr	w2, [x22, #16]
	mov	x0, x19
	bl	_sdhci_writel
	mov	x0, x19
	mov	x1, x20
	bl	_xenon_emmc_phy_slow_mode
	cbnz	x0, LBB0_12
; %bb.3:
	ldr	w1, [x22, #12]
	mov	x0, x19
	bl	_sdhci_readl
Lloh52:
	adrp	x8, _XENON_ZNR_MASK@GOTPAGE
Lloh53:
	ldr	x8, [x8, _XENON_ZNR_MASK@GOTPAGEOFF]
Lloh54:
	ldr	w8, [x8]
Lloh55:
	adrp	x9, _XENON_ZNR_SHIFT@GOTPAGE
Lloh56:
	ldr	x9, [x9, _XENON_ZNR_SHIFT@GOTPAGEOFF]
Lloh57:
	ldr	w9, [x9]
	lsl	w8, w8, w9
Lloh58:
	adrp	x10, _XENON_ZPR_MASK@GOTPAGE
Lloh59:
	ldr	x10, [x10, _XENON_ZPR_MASK@GOTPAGEOFF]
Lloh60:
	ldr	w10, [x10]
	orr	w8, w8, w10
	bic	w8, w0, w8
	ldp	w10, w11, [x23]
	lsl	w9, w10, w9
	orr	w9, w9, w11
	orr	w1, w9, w8
	ldr	w2, [x22, #12]
	mov	x0, x19
	bl	_sdhci_writel
Lloh61:
	adrp	x21, _SDHCI_CLOCK_CONTROL@GOTPAGE
Lloh62:
	ldr	x21, [x21, _SDHCI_CLOCK_CONTROL@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_sdhci_readl
Lloh63:
	adrp	x23, _SDHCI_CLOCK_CARD_EN@GOTPAGE
Lloh64:
	ldr	x23, [x23, _SDHCI_CLOCK_CARD_EN@GOTPAGEOFF]
	ldr	w8, [x23]
	bic	w1, w0, w8
	ldr	w2, [x21]
	mov	x0, x19
	bl	_sdhci_writew
	ldr	w1, [x22, #8]
	mov	x0, x19
	bl	_sdhci_readl
	cmp	w20, #128
	b.eq	LBB0_7
; %bb.4:
	cmp	w20, #130
	b.eq	LBB0_7
; %bb.5:
Lloh65:
	adrp	x8, _XENON_DQ_DDR_MODE_MASK@GOTPAGE
Lloh66:
	ldr	x8, [x8, _XENON_DQ_DDR_MODE_MASK@GOTPAGEOFF]
Lloh67:
	adrp	x9, _XENON_DQ_DDR_MODE_SHIFT@GOTPAGE
Lloh68:
	ldr	x9, [x9, _XENON_DQ_DDR_MODE_SHIFT@GOTPAGEOFF]
	cmp	w20, #129
	b.ne	LBB0_8
; %bb.6:
	ldr	w8, [x8]
	ldr	w9, [x9]
	lsl	w8, w8, w9
Lloh69:
	adrp	x9, _XENON_CMD_DDR_MODE@GOTPAGE
Lloh70:
	ldr	x9, [x9, _XENON_CMD_DDR_MODE@GOTPAGEOFF]
Lloh71:
	ldr	w9, [x9]
	orr	w9, w9, w0
	orr	w8, w9, w8
Lloh72:
	adrp	x9, _XENON_DQ_ASYNC_MODE@GOTPAGE
Lloh73:
	ldr	x9, [x9, _XENON_DQ_ASYNC_MODE@GOTPAGEOFF]
Lloh74:
	ldr	w9, [x9]
	bic	w1, w8, w9
	b	LBB0_9
LBB0_7:
Lloh75:
	adrp	x8, _XENON_DQ_DDR_MODE_MASK@GOTPAGE
Lloh76:
	ldr	x8, [x8, _XENON_DQ_DDR_MODE_MASK@GOTPAGEOFF]
Lloh77:
	adrp	x9, _XENON_DQ_DDR_MODE_SHIFT@GOTPAGE
Lloh78:
	ldr	x9, [x9, _XENON_DQ_DDR_MODE_SHIFT@GOTPAGEOFF]
Lloh79:
	ldr	w8, [x8]
Lloh80:
	ldr	w9, [x9]
	lsl	w8, w8, w9
Lloh81:
	adrp	x9, _XENON_CMD_DDR_MODE@GOTPAGE
Lloh82:
	ldr	x9, [x9, _XENON_CMD_DDR_MODE@GOTPAGEOFF]
Lloh83:
	ldr	w9, [x9]
Lloh84:
	adrp	x10, _XENON_DQ_ASYNC_MODE@GOTPAGE
Lloh85:
	ldr	x10, [x10, _XENON_DQ_ASYNC_MODE@GOTPAGEOFF]
Lloh86:
	ldr	w10, [x10]
	orr	w9, w9, w0
	orr	w8, w9, w8
	orr	w1, w8, w10
	b	LBB0_9
LBB0_8:
	ldr	w8, [x8]
	ldr	w9, [x9]
	lsl	w8, w8, w9
Lloh87:
	adrp	x9, _XENON_CMD_DDR_MODE@GOTPAGE
Lloh88:
	ldr	x9, [x9, _XENON_CMD_DDR_MODE@GOTPAGEOFF]
Lloh89:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w8, w0, w8
Lloh90:
	adrp	x9, _XENON_DQ_ASYNC_MODE@GOTPAGE
Lloh91:
	ldr	x9, [x9, _XENON_DQ_ASYNC_MODE@GOTPAGEOFF]
Lloh92:
	ldr	w9, [x9]
	orr	w1, w8, w9
LBB0_9:
	ldr	w2, [x22, #8]
	mov	x0, x19
	bl	_sdhci_writel
	ldr	w1, [x21]
	mov	x0, x19
	bl	_sdhci_readl
	ldr	w8, [x23]
	orr	w1, w8, w0
	ldr	w2, [x21]
	mov	x0, x19
	bl	_sdhci_writew
	cmp	w20, #129
	b.ne	LBB0_11
; %bb.10:
	ldp	w1, w2, [x22]
	mov	x0, x19
	bl	_sdhci_writel
	b	LBB0_12
LBB0_11:
	mov	x0, x19
	bl	_xenon_emmc_phy_disable_strobe
LBB0_12:
	mov	x0, x19
	bl	_xenon_emmc_phy_init
	ldr	w0, [x19]
	bl	_mmc_dev
Lloh93:
	adrp	x1, l_.str.1@PAGE
Lloh94:
	add	x1, x1, l_.str.1@PAGEOFF
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_dev_dbg
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh21
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh67, Lloh68
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh79
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpAdd	Lloh93, Lloh94
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"eMMC PHY setting starts\n"

	.comm	_XENON_FC_DQ_RECEN,4,2          ; @XENON_FC_DQ_RECEN
	.comm	_XENON_FC_CMD_RECEN,4,2         ; @XENON_FC_CMD_RECEN
	.comm	_XENON_FC_QSP_RECEN,4,2         ; @XENON_FC_QSP_RECEN
	.comm	_XENON_OEN_QSN,4,2              ; @XENON_OEN_QSN
	.comm	_XENON_FC_ALL_CMOS_RECEIVER,4,2 ; @XENON_FC_ALL_CMOS_RECEIVER
	.comm	_EMMC_5_0_PHY,8,3               ; @EMMC_5_0_PHY
	.comm	_XENON_EMMC_5_0_PHY_PAD_CONTROL,4,2 ; @XENON_EMMC_5_0_PHY_PAD_CONTROL
	.comm	_XENON_EMMC5_FC_CMD_PU,4,2      ; @XENON_EMMC5_FC_CMD_PU
	.comm	_XENON_EMMC5_FC_DQ_PU,4,2       ; @XENON_EMMC5_FC_DQ_PU
	.comm	_XENON_EMMC5_FC_CMD_PD,4,2      ; @XENON_EMMC5_FC_CMD_PD
	.comm	_XENON_EMMC5_FC_DQ_PD,4,2       ; @XENON_EMMC5_FC_DQ_PD
	.comm	_XENON_EMMC_PHY_PAD_CONTROL1,4,2 ; @XENON_EMMC_PHY_PAD_CONTROL1
	.comm	_XENON_EMMC5_1_FC_CMD_PU,4,2    ; @XENON_EMMC5_1_FC_CMD_PU
	.comm	_XENON_EMMC5_1_FC_DQ_PU,4,2     ; @XENON_EMMC5_1_FC_DQ_PU
	.comm	_XENON_EMMC5_1_FC_CMD_PD,4,2    ; @XENON_EMMC5_1_FC_CMD_PD
	.comm	_XENON_EMMC5_1_FC_DQ_PD,4,2     ; @XENON_EMMC5_1_FC_DQ_PD
	.comm	_MMC_TIMING_LEGACY,1,0          ; @MMC_TIMING_LEGACY
	.comm	_MMC_TYPE_SDIO,8,3              ; @MMC_TYPE_SDIO
	.comm	_XENON_TIMING_ADJUST_SDIO_MODE,4,2 ; @XENON_TIMING_ADJUST_SDIO_MODE
	.comm	_XENON_ZNR_MASK,4,2             ; @XENON_ZNR_MASK
	.comm	_XENON_ZNR_SHIFT,4,2            ; @XENON_ZNR_SHIFT
	.comm	_XENON_ZPR_MASK,4,2             ; @XENON_ZPR_MASK
	.comm	_SDHCI_CLOCK_CONTROL,4,2        ; @SDHCI_CLOCK_CONTROL
	.comm	_SDHCI_CLOCK_CARD_EN,4,2        ; @SDHCI_CLOCK_CARD_EN
	.comm	_XENON_DQ_DDR_MODE_MASK,4,2     ; @XENON_DQ_DDR_MODE_MASK
	.comm	_XENON_DQ_DDR_MODE_SHIFT,4,2    ; @XENON_DQ_DDR_MODE_SHIFT
	.comm	_XENON_CMD_DDR_MODE,4,2         ; @XENON_CMD_DDR_MODE
	.comm	_XENON_DQ_ASYNC_MODE,4,2        ; @XENON_DQ_ASYNC_MODE
l_.str.1:                               ; @.str.1
	.asciz	"eMMC PHY setting completes\n"

	.no_dead_strip	_xenon_emmc_phy_set
.subsections_via_symbols
