	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_pl353_smc_set_cycles           ## -- Begin function pl353_smc_set_cycles
	.p2align	4, 0x90
_pl353_smc_set_cycles:                  ## @pl353_smc_set_cycles
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	_PL353_SMC_SET_CYCLES_T0_MASK@GOTPCREL(%rip), %rax
	movl	(%rdi), %r8d
	andl	(%rax), %r8d
	movl	%r8d, (%rdi)
	movq	_PL353_SMC_SET_CYCLES_T1_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %r10d
	andl	4(%rdi), %r10d
	movq	_PL353_SMC_SET_CYCLES_T1_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r10d
	movl	%r10d, 4(%rdi)
	movq	_PL353_SMC_SET_CYCLES_T2_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %r9d
	andl	8(%rdi), %r9d
	movq	_PL353_SMC_SET_CYCLES_T2_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r9d
	movl	%r9d, 8(%rdi)
	movq	_PL353_SMC_SET_CYCLES_T3_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	andl	12(%rdi), %edx
	movq	_PL353_SMC_SET_CYCLES_T3_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %edx
	movl	%edx, 12(%rdi)
	movq	_PL353_SMC_SET_CYCLES_T4_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %r11d
	andl	16(%rdi), %r11d
	movq	_PL353_SMC_SET_CYCLES_T4_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r11d
	movl	%r11d, 16(%rdi)
	movq	_PL353_SMC_SET_CYCLES_T5_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	20(%rdi), %eax
	movq	_PL353_SMC_SET_CYCLES_T5_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	movl	%eax, 20(%rdi)
	movq	_PL353_SMC_SET_CYCLES_T6_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	andl	24(%rdi), %esi
	movq	_PL353_SMC_SET_CYCLES_T6_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %esi
	movl	%esi, 24(%rdi)
	orl	%r8d, %r10d
	orl	%r9d, %edx
	orl	%r10d, %edx
	orl	%r11d, %eax
	orl	%esi, %eax
	orl	%edx, %eax
	movl	%eax, (%rdi)
	movq	_pl353_smc_base@GOTPCREL(%rip), %rbx
	movq	_PL353_SMC_SET_CYCLES_OFFS@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rsi
	addq	(%rbx), %rsi
	movl	%eax, %edi
	callq	_writel
	movq	_PL353_SMC_DC_UPT_NAND_REGS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_PL353_SMC_DIRECT_CMD_OFFS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%rbx), %rsi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_writel                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PL353_SMC_SET_CYCLES_T0_MASK,4,2 ## @PL353_SMC_SET_CYCLES_T0_MASK
	.comm	_PL353_SMC_SET_CYCLES_T1_MASK,4,2 ## @PL353_SMC_SET_CYCLES_T1_MASK
	.comm	_PL353_SMC_SET_CYCLES_T1_SHIFT,4,2 ## @PL353_SMC_SET_CYCLES_T1_SHIFT
	.comm	_PL353_SMC_SET_CYCLES_T2_MASK,4,2 ## @PL353_SMC_SET_CYCLES_T2_MASK
	.comm	_PL353_SMC_SET_CYCLES_T2_SHIFT,4,2 ## @PL353_SMC_SET_CYCLES_T2_SHIFT
	.comm	_PL353_SMC_SET_CYCLES_T3_MASK,4,2 ## @PL353_SMC_SET_CYCLES_T3_MASK
	.comm	_PL353_SMC_SET_CYCLES_T3_SHIFT,4,2 ## @PL353_SMC_SET_CYCLES_T3_SHIFT
	.comm	_PL353_SMC_SET_CYCLES_T4_MASK,4,2 ## @PL353_SMC_SET_CYCLES_T4_MASK
	.comm	_PL353_SMC_SET_CYCLES_T4_SHIFT,4,2 ## @PL353_SMC_SET_CYCLES_T4_SHIFT
	.comm	_PL353_SMC_SET_CYCLES_T5_MASK,4,2 ## @PL353_SMC_SET_CYCLES_T5_MASK
	.comm	_PL353_SMC_SET_CYCLES_T5_SHIFT,4,2 ## @PL353_SMC_SET_CYCLES_T5_SHIFT
	.comm	_PL353_SMC_SET_CYCLES_T6_MASK,4,2 ## @PL353_SMC_SET_CYCLES_T6_MASK
	.comm	_PL353_SMC_SET_CYCLES_T6_SHIFT,4,2 ## @PL353_SMC_SET_CYCLES_T6_SHIFT
	.comm	_pl353_smc_base,8,3             ## @pl353_smc_base
	.comm	_PL353_SMC_SET_CYCLES_OFFS,8,3  ## @PL353_SMC_SET_CYCLES_OFFS
	.comm	_PL353_SMC_DC_UPT_NAND_REGS,4,2 ## @PL353_SMC_DC_UPT_NAND_REGS
	.comm	_PL353_SMC_DIRECT_CMD_OFFS,8,3  ## @PL353_SMC_DIRECT_CMD_OFFS
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_pl353_smc_set_cycles           ; -- Begin function pl353_smc_set_cycles
	.p2align	2
_pl353_smc_set_cycles:                  ; @pl353_smc_set_cycles
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
Lloh0:
	adrp	x8, _PL353_SMC_SET_CYCLES_T0_MASK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PL353_SMC_SET_CYCLES_T0_MASK@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	ldp	w9, w10, [x0]
	and	w8, w9, w8
Lloh3:
	adrp	x9, _PL353_SMC_SET_CYCLES_T1_MASK@GOTPAGE
Lloh4:
	ldr	x9, [x9, _PL353_SMC_SET_CYCLES_T1_MASK@GOTPAGEOFF]
	str	w8, [x0]
Lloh5:
	ldr	w9, [x9]
	and	w9, w9, w10
Lloh6:
	adrp	x10, _PL353_SMC_SET_CYCLES_T1_SHIFT@GOTPAGE
Lloh7:
	ldr	x10, [x10, _PL353_SMC_SET_CYCLES_T1_SHIFT@GOTPAGEOFF]
Lloh8:
	ldr	w10, [x10]
	lsl	w9, w9, w10
Lloh9:
	adrp	x10, _PL353_SMC_SET_CYCLES_T2_MASK@GOTPAGE
Lloh10:
	ldr	x10, [x10, _PL353_SMC_SET_CYCLES_T2_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w10, [x10]
	ldp	w11, w12, [x0, #8]
	and	w10, w10, w11
Lloh12:
	adrp	x11, _PL353_SMC_SET_CYCLES_T2_SHIFT@GOTPAGE
Lloh13:
	ldr	x11, [x11, _PL353_SMC_SET_CYCLES_T2_SHIFT@GOTPAGEOFF]
Lloh14:
	ldr	w11, [x11]
Lloh15:
	adrp	x13, _PL353_SMC_SET_CYCLES_T3_MASK@GOTPAGE
Lloh16:
	ldr	x13, [x13, _PL353_SMC_SET_CYCLES_T3_MASK@GOTPAGEOFF]
	lsl	w10, w10, w11
Lloh17:
	ldr	w11, [x13]
	and	w11, w11, w12
Lloh18:
	adrp	x12, _PL353_SMC_SET_CYCLES_T3_SHIFT@GOTPAGE
Lloh19:
	ldr	x12, [x12, _PL353_SMC_SET_CYCLES_T3_SHIFT@GOTPAGEOFF]
Lloh20:
	ldr	w12, [x12]
	lsl	w11, w11, w12
	stp	w10, w11, [x0, #8]
Lloh21:
	adrp	x12, _PL353_SMC_SET_CYCLES_T4_MASK@GOTPAGE
Lloh22:
	ldr	x12, [x12, _PL353_SMC_SET_CYCLES_T4_MASK@GOTPAGEOFF]
Lloh23:
	ldr	w12, [x12]
	ldp	w13, w14, [x0, #16]
	and	w12, w12, w13
Lloh24:
	adrp	x13, _PL353_SMC_SET_CYCLES_T4_SHIFT@GOTPAGE
Lloh25:
	ldr	x13, [x13, _PL353_SMC_SET_CYCLES_T4_SHIFT@GOTPAGEOFF]
Lloh26:
	ldr	w13, [x13]
	lsl	w12, w12, w13
Lloh27:
	adrp	x13, _PL353_SMC_SET_CYCLES_T5_MASK@GOTPAGE
Lloh28:
	ldr	x13, [x13, _PL353_SMC_SET_CYCLES_T5_MASK@GOTPAGEOFF]
Lloh29:
	ldr	w13, [x13]
Lloh30:
	adrp	x15, _PL353_SMC_SET_CYCLES_T5_SHIFT@GOTPAGE
Lloh31:
	ldr	x15, [x15, _PL353_SMC_SET_CYCLES_T5_SHIFT@GOTPAGEOFF]
	and	w13, w13, w14
Lloh32:
	ldr	w14, [x15]
	lsl	w13, w13, w14
	stp	w12, w13, [x0, #16]
	ldr	w14, [x0, #24]
Lloh33:
	adrp	x15, _PL353_SMC_SET_CYCLES_T6_MASK@GOTPAGE
Lloh34:
	ldr	x15, [x15, _PL353_SMC_SET_CYCLES_T6_MASK@GOTPAGEOFF]
Lloh35:
	ldr	w15, [x15]
	and	w14, w15, w14
Lloh36:
	adrp	x15, _PL353_SMC_SET_CYCLES_T6_SHIFT@GOTPAGE
Lloh37:
	ldr	x15, [x15, _PL353_SMC_SET_CYCLES_T6_SHIFT@GOTPAGEOFF]
Lloh38:
	ldr	w15, [x15]
	lsl	w14, w14, w15
	str	w14, [x0, #24]
	orr	w8, w9, w8
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w8, w8, w13
	orr	w8, w8, w14
Lloh39:
	adrp	x19, _pl353_smc_base@GOTPAGE
Lloh40:
	ldr	x19, [x19, _pl353_smc_base@GOTPAGEOFF]
	stp	w8, w9, [x0]
	ldr	x9, [x19]
Lloh41:
	adrp	x10, _PL353_SMC_SET_CYCLES_OFFS@GOTPAGE
Lloh42:
	ldr	x10, [x10, _PL353_SMC_SET_CYCLES_OFFS@GOTPAGEOFF]
Lloh43:
	ldr	x10, [x10]
	add	x1, x10, x9
	mov	x0, x8
	bl	_writel
Lloh44:
	adrp	x8, _PL353_SMC_DC_UPT_NAND_REGS@GOTPAGE
Lloh45:
	ldr	x8, [x8, _PL353_SMC_DC_UPT_NAND_REGS@GOTPAGEOFF]
Lloh46:
	ldr	w0, [x8]
	ldr	x8, [x19]
Lloh47:
	adrp	x9, _PL353_SMC_DIRECT_CMD_OFFS@GOTPAGE
Lloh48:
	ldr	x9, [x9, _PL353_SMC_DIRECT_CMD_OFFS@GOTPAGEOFF]
Lloh49:
	ldr	x9, [x9]
	add	x1, x9, x8
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_writel
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_PL353_SMC_SET_CYCLES_T0_MASK,4,2 ; @PL353_SMC_SET_CYCLES_T0_MASK
	.comm	_PL353_SMC_SET_CYCLES_T1_MASK,4,2 ; @PL353_SMC_SET_CYCLES_T1_MASK
	.comm	_PL353_SMC_SET_CYCLES_T1_SHIFT,4,2 ; @PL353_SMC_SET_CYCLES_T1_SHIFT
	.comm	_PL353_SMC_SET_CYCLES_T2_MASK,4,2 ; @PL353_SMC_SET_CYCLES_T2_MASK
	.comm	_PL353_SMC_SET_CYCLES_T2_SHIFT,4,2 ; @PL353_SMC_SET_CYCLES_T2_SHIFT
	.comm	_PL353_SMC_SET_CYCLES_T3_MASK,4,2 ; @PL353_SMC_SET_CYCLES_T3_MASK
	.comm	_PL353_SMC_SET_CYCLES_T3_SHIFT,4,2 ; @PL353_SMC_SET_CYCLES_T3_SHIFT
	.comm	_PL353_SMC_SET_CYCLES_T4_MASK,4,2 ; @PL353_SMC_SET_CYCLES_T4_MASK
	.comm	_PL353_SMC_SET_CYCLES_T4_SHIFT,4,2 ; @PL353_SMC_SET_CYCLES_T4_SHIFT
	.comm	_PL353_SMC_SET_CYCLES_T5_MASK,4,2 ; @PL353_SMC_SET_CYCLES_T5_MASK
	.comm	_PL353_SMC_SET_CYCLES_T5_SHIFT,4,2 ; @PL353_SMC_SET_CYCLES_T5_SHIFT
	.comm	_PL353_SMC_SET_CYCLES_T6_MASK,4,2 ; @PL353_SMC_SET_CYCLES_T6_MASK
	.comm	_PL353_SMC_SET_CYCLES_T6_SHIFT,4,2 ; @PL353_SMC_SET_CYCLES_T6_SHIFT
	.comm	_pl353_smc_base,8,3             ; @pl353_smc_base
	.comm	_PL353_SMC_SET_CYCLES_OFFS,8,3  ; @PL353_SMC_SET_CYCLES_OFFS
	.comm	_PL353_SMC_DC_UPT_NAND_REGS,4,2 ; @PL353_SMC_DC_UPT_NAND_REGS
	.comm	_PL353_SMC_DIRECT_CMD_OFFS,8,3  ; @PL353_SMC_DIRECT_CMD_OFFS
.subsections_via_symbols
