	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_lio_cn6xxx_setup_pcie_mrrs     ## -- Begin function lio_cn6xxx_setup_pcie_mrrs
	.p2align	4, 0x90
_lio_cn6xxx_setup_pcie_mrrs:            ## @lio_cn6xxx_setup_pcie_mrrs
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %r15
	movl	4(%rdi), %edi
	movq	_CN6XXX_PCIE_DEVCTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	leaq	-28(%rbp), %rdx
	callq	_pci_read_config_dword
	movq	_PCIE_MRRS_DEFAULT@GOTPCREL(%rip), %rcx
	movl	-28(%rbp), %eax
	cmpl	%r14d, (%rcx)
	jne	LBB0_2
## %bb.1:
	shrl	$12, %eax
	andl	$7, %eax
	movl	%eax, %r14d
	jmp	LBB0_3
LBB0_2:
	andl	$-28673, %eax                   ## imm = 0x8FFF
	movl	%r14d, %edx
	shll	$12, %edx
	orl	%eax, %edx
	movl	%edx, -28(%rbp)
	movl	4(%r15), %edi
	movl	(%rbx), %esi
	callq	_pci_write_config_dword
LBB0_3:
	movl	(%r15), %edi
	callq	_CN6XXX_SLI_S2M_PORTX_CTL
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_octeon_read_csr64
	movl	%eax, %ebx
	orl	%r14d, %ebx
	movl	(%r15), %edi
	callq	_CN6XXX_SLI_S2M_PORTX_CTL
	movq	%r15, %rdi
	movl	%eax, %esi
	movl	%ebx, %edx
	callq	_octeon_write_csr64
	movl	(%r15), %edi
	callq	_CN6XXX_DPI_SLI_PRTX_CFG
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_lio_pci_readq
	orl	%eax, %r14d
	movl	(%r15), %edi
	callq	_CN6XXX_DPI_SLI_PRTX_CFG
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_lio_pci_writeq
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CN6XXX_PCIE_DEVCTL,4,2         ## @CN6XXX_PCIE_DEVCTL
	.comm	_PCIE_MRRS_DEFAULT,4,2          ## @PCIE_MRRS_DEFAULT
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_lio_cn6xxx_setup_pcie_mrrs     ; -- Begin function lio_cn6xxx_setup_pcie_mrrs
	.p2align	2
_lio_cn6xxx_setup_pcie_mrrs:            ; @lio_cn6xxx_setup_pcie_mrrs
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	mov	x19, x0
	ldr	w0, [x0, #4]
Lloh0:
	adrp	x21, _CN6XXX_PCIE_DEVCTL@GOTPAGE
Lloh1:
	ldr	x21, [x21, _CN6XXX_PCIE_DEVCTL@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x2, sp, #12
	bl	_pci_read_config_dword
Lloh2:
	adrp	x8, _PCIE_MRRS_DEFAULT@GOTPAGE
Lloh3:
	ldr	x8, [x8, _PCIE_MRRS_DEFAULT@GOTPAGEOFF]
Lloh4:
	ldr	w9, [x8]
	ldr	w8, [sp, #12]
	cmp	w9, w20
	b.ne	LBB0_2
; %bb.1:
	ubfx	w20, w8, #12, #3
	b	LBB0_3
LBB0_2:
	and	w8, w8, #0xffff8fff
	orr	w2, w8, w20, lsl #12
	str	w2, [sp, #12]
	ldr	w0, [x19, #4]
	ldr	w1, [x21]
	bl	_pci_write_config_dword
LBB0_3:
	ldr	w0, [x19]
	bl	_CN6XXX_SLI_S2M_PORTX_CTL
	mov	x1, x0
	mov	x0, x19
	bl	_octeon_read_csr64
	orr	w21, w0, w20
	ldr	w0, [x19]
	bl	_CN6XXX_SLI_S2M_PORTX_CTL
	mov	x1, x0
	mov	x0, x19
	mov	x2, x21
	bl	_octeon_write_csr64
	ldr	w0, [x19]
	bl	_CN6XXX_DPI_SLI_PRTX_CFG
	mov	x1, x0
	mov	x0, x19
	bl	_lio_pci_readq
	orr	w20, w0, w20
	ldr	w0, [x19]
	bl	_CN6XXX_DPI_SLI_PRTX_CFG
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_lio_pci_writeq
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_CN6XXX_PCIE_DEVCTL,4,2         ; @CN6XXX_PCIE_DEVCTL
	.comm	_PCIE_MRRS_DEFAULT,4,2          ; @PCIE_MRRS_DEFAULT
.subsections_via_symbols
