	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function bnx2x_init_hw_port
_bnx2x_init_hw_port:                    ## @bnx2x_init_hw_port
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	callq	_BP_PORT
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	LBB0_1
## %bb.2:
	movq	_PHASE_PORT0@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_1:
	movq	_PHASE_PORT1@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %r12d
	movq	_NETIF_MSG_HW@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	leaq	L_.str(%rip), %rsi
	movl	%r15d, %edx
	callq	_DP
	movq	_NIG_REG_MASK_INTERRUPT_PORT0@GOTPCREL(%rip), %rax
	leal	(,%r15,4), %r13d
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_BLOCK_MISC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_PXP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_PXP2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	%r14, %rdi
	callq	_CHIP_IS_E1x
	testq	%rax, %rax
	jne	LBB0_5
## %bb.4:
	movq	_PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$1, %edx
	callq	_REG_WR
LBB0_5:
	movq	_BLOCK_ATC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_DMAE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_PGLUE_B@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_QM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_TCM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_UCM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_CCM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_XCM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movl	24(%r14), %esi
	movq	_INITOP_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_bnx2x_qm_init_cid_count
	movq	%r14, %rdi
	callq	_CNIC_SUPPORT
	testq	%rax, %rax
	je	LBB0_7
## %bb.6:
	movq	_BLOCK_TM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_TM_REG_LIN0_SCAN_TIME@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	%r14, %rdi
	movl	$20, %edx
	callq	_REG_WR
	movq	_TM_REG_LIN0_MAX_ACTIVE_CID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	%r14, %rdi
	movl	$31, %edx
	callq	_REG_WR
LBB0_7:
	movq	_BLOCK_DORQ@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_BRB1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	%r14, %rdi
	callq	_CHIP_IS_E1
	testq	%rax, %rax
	movl	%r13d, -44(%rbp)                ## 4-byte Spill
	jne	LBB0_9
## %bb.8:
	movq	%r14, %rdi
	callq	_CHIP_IS_E1H
	testq	%rax, %rax
	je	LBB0_17
LBB0_9:
	movq	%r14, %rdi
	callq	_IS_MF
	testl	%eax, %eax
	je	LBB0_11
## %bb.10:
	movq	_ONE_PORT_FLAG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r14)
	movl	$246, %eax
	movl	$160, %edx
	jmp	LBB0_15
LBB0_11:
	movq	16(%r14), %rax
	movl	(%rax), %eax
	movq	_ONE_PORT_FLAG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	(%r14), %ecx
	cmpl	$4097, %eax                     ## imm = 0x1001
	jl	LBB0_14
## %bb.12:
	movl	$160, %edx
	testl	%ecx, %ecx
	jne	LBB0_16
## %bb.13:
	movl	%eax, %edx
	shrl	$6, %edx
	andl	$63, %eax
	cmpl	$1, %eax
	sbbl	$-1, %edx
	addl	$96, %edx
	jmp	LBB0_16
LBB0_14:
	testl	%ecx, %ecx
	movl	$160, %eax
	movl	$80, %edx
LBB0_15:
	cmovel	%eax, %edx
LBB0_16:
	leal	56(%rdx), %r13d
	movq	_BRB1_REG_PAUSE_LOW_THRESHOLD_0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-44(%rbp), %ebx                 ## 4-byte Reload
	addl	%ebx, %esi
	movq	%r14, %rdi
                                        ## kill: def $edx killed $edx killed $rdx
	callq	_REG_WR
	movq	_BRB1_REG_PAUSE_HIGH_THRESHOLD_0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%ebx, %esi
	movq	%r14, %rdi
	movl	%r13d, %edx
	movl	%ebx, %r13d
	callq	_REG_WR
LBB0_17:
	movq	%r14, %rdi
	callq	_CHIP_MODE_IS_4_PORT
	testq	%rax, %rax
	je	LBB0_22
## %bb.18:
	movq	%r14, %rdi
	callq	_BP_PORT
	testl	%eax, %eax
	jne	LBB0_19
## %bb.20:
	movq	_BRB1_REG_MAC_GUARANTIED_0@GOTPCREL(%rip), %rax
	jmp	LBB0_21
LBB0_19:
	movq	_BRB1_REG_MAC_GUARANTIED_1@GOTPCREL(%rip), %rax
LBB0_21:
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$40, %edx
	callq	_REG_WR
LBB0_22:
	movq	_BLOCK_PRS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	%r14, %rdi
	callq	_CHIP_IS_E3B0
	testq	%rax, %rax
	je	LBB0_35
## %bb.23:
	movq	%r14, %rdi
	callq	_IS_MF_AFEX
	movq	%rax, %r13
	movq	%r14, %rdi
	callq	_BP_PORT
	testl	%eax, %eax
	jne	LBB0_24
## %bb.25:
	movq	_PRS_REG_HDRS_AFTER_BASIC_PORT_0@GOTPCREL(%rip), %rax
	jmp	LBB0_26
LBB0_24:
	movq	_PRS_REG_HDRS_AFTER_BASIC_PORT_1@GOTPCREL(%rip), %rax
LBB0_26:
	movl	(%rax), %esi
	testq	%r13, %r13
	je	LBB0_34
## %bb.27:
	movq	%r14, %rdi
	movl	$14, %edx
	callq	_REG_WR
	movq	%r14, %rdi
	callq	_BP_PORT
	testl	%eax, %eax
	movl	-44(%rbp), %r13d                ## 4-byte Reload
	jne	LBB0_28
## %bb.29:
	movq	_PRS_REG_HDRS_AFTER_TAG_0_PORT_0@GOTPCREL(%rip), %rax
	jmp	LBB0_30
LBB0_34:
	cmpq	$1, 8(%r14)
	movl	$7, %edx
	sbbl	$0, %edx
	movq	%r14, %rdi
	callq	_REG_WR
	movl	-44(%rbp), %r13d                ## 4-byte Reload
	jmp	LBB0_35
LBB0_28:
	movq	_PRS_REG_HDRS_AFTER_TAG_0_PORT_1@GOTPCREL(%rip), %rax
LBB0_30:
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$6, %edx
	callq	_REG_WR
	movq	%r14, %rdi
	callq	_BP_PORT
	testl	%eax, %eax
	jne	LBB0_31
## %bb.32:
	movq	_PRS_REG_MUST_HAVE_HDRS_PORT_0@GOTPCREL(%rip), %rax
	jmp	LBB0_33
LBB0_31:
	movq	_PRS_REG_MUST_HAVE_HDRS_PORT_1@GOTPCREL(%rip), %rax
LBB0_33:
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$10, %edx
	callq	_REG_WR
LBB0_35:
	movq	_BLOCK_TSDM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_CSDM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_USDM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_XSDM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_TSEM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_USEM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_CSEM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_XSEM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_UPB@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_XPB@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_PBF@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	%r14, %rdi
	callq	_CHIP_IS_E1x
	testq	%rax, %rax
	je	LBB0_37
## %bb.36:
	movq	_PBF_REG_P0_PAUSE_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_PBF_REG_P0_ARB_THRSH@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	%r14, %rdi
	movl	$565, %edx                      ## imm = 0x235
	callq	_REG_WR
	movq	_PBF_REG_P0_INIT_CRD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	%r14, %rdi
	movl	$1096, %edx                     ## imm = 0x448
	callq	_REG_WR
	movq	_PBF_REG_INIT_P0@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	addl	%r13d, %esi
	movq	%r14, %rdi
	movl	$1, %edx
	callq	_REG_WR
	movl	$50, %edi
	callq	_udelay
	movl	(%rbx), %esi
	addl	%r13d, %esi
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
LBB0_37:
	movq	%r14, %rdi
	callq	_CNIC_SUPPORT
	testq	%rax, %rax
	je	LBB0_39
## %bb.38:
	movq	_BLOCK_SRC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
LBB0_39:
	movq	_BLOCK_CDU@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_CFC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	%r14, %rdi
	callq	_CHIP_IS_E1
	testq	%rax, %rax
	je	LBB0_41
## %bb.40:
	movq	_HC_REG_LEADING_EDGE_0@GOTPCREL(%rip), %rax
	leal	(,%r15,8), %ebx
	movl	(%rax), %esi
	addl	%ebx, %esi
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_HC_REG_TRAILING_EDGE_0@GOTPCREL(%rip), %rax
	addl	(%rax), %ebx
	movq	%r14, %rdi
	movl	%ebx, %esi
	xorl	%edx, %edx
	callq	_REG_WR
LBB0_41:
	movq	_BLOCK_HC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_IGU@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	_BLOCK_MISC_AEU@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	%r14, %rdi
	callq	_IS_MF
	testl	%eax, %eax
	movl	$7, %eax
	movl	$247, %ebx
	cmovel	%eax, %ebx
	movq	%r14, %rdi
	callq	_CHIP_IS_E1
	xorl	%edx, %edx
	testq	%rax, %rax
	sete	%dl
	shll	$4, %edx
	orl	%ebx, %edx
	movq	_MISC_REG_AEU_MASK_ATTN_FUNC_0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	%r14, %rdi
	callq	_REG_WR
	movq	%r15, -56(%rbp)                 ## 8-byte Spill
	testl	%r15d, %r15d
	movq	_MISC_REG_AEU_ENABLE4_NIG_1@GOTPCREL(%rip), %rax
	cmoveq	_MISC_REG_AEU_ENABLE4_NIG_0@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	_MISC_REG_AEU_ENABLE4_PXP_1@GOTPCREL(%rip), %rbx
	cmoveq	_MISC_REG_AEU_ENABLE4_PXP_0@GOTPCREL(%rip), %rbx
	movq	%r14, %rdi
	movl	%r13d, %esi
	callq	_REG_RD
	movq	_AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	notl	%edx
	andl	%eax, %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	callq	_REG_WR
	movl	(%rbx), %ebx
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_REG_RD
	movl	(%r15), %edx
	notl	%edx
	andl	%eax, %edx
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_REG_WR
	movq	_BLOCK_NIG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_bnx2x_init_block
	movq	%r14, %rdi
	callq	_CHIP_IS_E1x
	testq	%rax, %rax
	jne	LBB0_52
## %bb.42:
	movq	%r14, %rdi
	callq	_IS_MF_AFEX
	movq	%rax, %r13
	movq	%r14, %rdi
	callq	_BP_PORT
	testl	%eax, %eax
	jne	LBB0_43
## %bb.44:
	movq	_NIG_REG_P0_HDRS_AFTER_BASIC@GOTPCREL(%rip), %rax
	jmp	LBB0_45
LBB0_43:
	movq	_NIG_REG_P1_HDRS_AFTER_BASIC@GOTPCREL(%rip), %rax
LBB0_45:
	movl	(%rax), %r12d
	movl	$14, %edx
	testq	%r13, %r13
	jne	LBB0_47
## %bb.46:
	movq	%r14, %rdi
	callq	_IS_MF_SD
	cmpq	$1, %rax
	movl	$7, %edx
	sbbl	$0, %edx
LBB0_47:
	movq	%r14, %rdi
	movl	%r12d, %esi
	callq	_REG_WR
	movq	%r14, %rdi
	callq	_CHIP_IS_E3
	testq	%rax, %rax
	je	LBB0_52
## %bb.48:
	movq	%r14, %rdi
	callq	_BP_PORT
	testl	%eax, %eax
	jne	LBB0_49
## %bb.50:
	movq	_NIG_REG_LLH_MF_MODE@GOTPCREL(%rip), %rax
	jmp	LBB0_51
LBB0_49:
	movq	_NIG_REG_LLH1_MF_MODE@GOTPCREL(%rip), %rax
LBB0_51:
	movl	(%rax), %ebx
	movq	%r14, %rdi
	callq	_IS_MF
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_REG_WR
LBB0_52:
	movq	%r14, %rdi
	callq	_CHIP_IS_E3
	testq	%rax, %rax
	movl	-44(%rbp), %r13d                ## 4-byte Reload
	jne	LBB0_54
## %bb.53:
	movq	_NIG_REG_XGXS_SERDES0_MODE_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	%r14, %rdi
	movl	$1, %edx
	callq	_REG_WR
LBB0_54:
	movq	%r14, %rdi
	callq	_CHIP_IS_E1
	testq	%rax, %rax
	movq	-56(%rbp), %r15                 ## 8-byte Reload
	jne	LBB0_63
## %bb.55:
	movq	_NIG_REG_LLH0_BRB1_DRV_MASK_MF@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	addl	%r13d, %ebx
	movq	%r14, %rdi
	callq	_IS_MF_SD
	xorl	%r12d, %r12d
	cmpq	$1, %rax
	movl	$0, %edx
	adcl	$1, %edx
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_REG_WR
	movq	%r14, %rdi
	callq	_CHIP_IS_E1x
	testq	%rax, %rax
	jne	LBB0_62
## %bb.56:
	movl	4(%r14), %eax
	addl	$-128, %eax
	cmpl	$2, %eax
	ja	LBB0_58
## %bb.57:
	cltq
	leaq	l_switch.table.bnx2x_init_hw_port(%rip), %rcx
	movl	(%rcx,%rax,4), %r12d
LBB0_58:
	movq	%r14, %rdi
	callq	_BP_PORT
	testl	%eax, %eax
	jne	LBB0_59
## %bb.60:
	movq	_NIG_REG_LLH0_CLS_TYPE@GOTPCREL(%rip), %rax
	jmp	LBB0_61
LBB0_59:
	movq	_NIG_REG_LLH1_CLS_TYPE@GOTPCREL(%rip), %rax
LBB0_61:
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_REG_WR
LBB0_62:
	movq	_NIG_REG_LLFC_ENABLE_0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_NIG_REG_LLFC_OUT_EN_0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%r13d, %esi
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_NIG_REG_PAUSE_ENABLE_0@GOTPCREL(%rip), %rax
	addl	(%rax), %r13d
	movq	%r14, %rdi
	movl	%r13d, %esi
	movl	$1, %edx
	callq	_REG_WR
LBB0_63:
	movq	_MISC_REG_SPIO_EVENT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_REG_RD
	movq	_MISC_SPIO_SPIO5@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_68
## %bb.64:
	testl	%r15d, %r15d
	jne	LBB0_65
## %bb.66:
	movq	_MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0@GOTPCREL(%rip), %rax
	jmp	LBB0_67
LBB0_65:
	movq	_MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0@GOTPCREL(%rip), %rax
LBB0_67:
	movl	(%rax), %ebx
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_REG_RD
	movq	_AEU_INPUTS_ATTN_BITS_SPIO5@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_REG_WR
LBB0_68:
	movq	%r14, %rdi
	callq	_CHIP_IS_E3B0
	testq	%rax, %rax
	je	LBB0_70
## %bb.69:
	movq	_PTP_SUPPORTED@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, (%r14)
LBB0_70:
	xorl	%eax, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PHASE_PORT1,4,2                ## @PHASE_PORT1
	.comm	_PHASE_PORT0,4,2                ## @PHASE_PORT0
	.comm	_NETIF_MSG_HW,4,2               ## @NETIF_MSG_HW
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"starting port init  port %d\n"

	.comm	_NIG_REG_MASK_INTERRUPT_PORT0,4,2 ## @NIG_REG_MASK_INTERRUPT_PORT0
	.comm	_BLOCK_MISC,4,2                 ## @BLOCK_MISC
	.comm	_BLOCK_PXP,4,2                  ## @BLOCK_PXP
	.comm	_BLOCK_PXP2,4,2                 ## @BLOCK_PXP2
	.comm	_PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,4,2 ## @PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
	.comm	_BLOCK_ATC,4,2                  ## @BLOCK_ATC
	.comm	_BLOCK_DMAE,4,2                 ## @BLOCK_DMAE
	.comm	_BLOCK_PGLUE_B,4,2              ## @BLOCK_PGLUE_B
	.comm	_BLOCK_QM,4,2                   ## @BLOCK_QM
	.comm	_BLOCK_TCM,4,2                  ## @BLOCK_TCM
	.comm	_BLOCK_UCM,4,2                  ## @BLOCK_UCM
	.comm	_BLOCK_CCM,4,2                  ## @BLOCK_CCM
	.comm	_BLOCK_XCM,4,2                  ## @BLOCK_XCM
	.comm	_INITOP_SET,4,2                 ## @INITOP_SET
	.comm	_BLOCK_TM,4,2                   ## @BLOCK_TM
	.comm	_TM_REG_LIN0_SCAN_TIME,4,2      ## @TM_REG_LIN0_SCAN_TIME
	.comm	_TM_REG_LIN0_MAX_ACTIVE_CID,4,2 ## @TM_REG_LIN0_MAX_ACTIVE_CID
	.comm	_BLOCK_DORQ,4,2                 ## @BLOCK_DORQ
	.comm	_BLOCK_BRB1,4,2                 ## @BLOCK_BRB1
	.comm	_ONE_PORT_FLAG,4,2              ## @ONE_PORT_FLAG
	.comm	_BRB1_REG_PAUSE_LOW_THRESHOLD_0,4,2 ## @BRB1_REG_PAUSE_LOW_THRESHOLD_0
	.comm	_BRB1_REG_PAUSE_HIGH_THRESHOLD_0,4,2 ## @BRB1_REG_PAUSE_HIGH_THRESHOLD_0
	.comm	_BRB1_REG_MAC_GUARANTIED_1,4,2  ## @BRB1_REG_MAC_GUARANTIED_1
	.comm	_BRB1_REG_MAC_GUARANTIED_0,4,2  ## @BRB1_REG_MAC_GUARANTIED_0
	.comm	_BLOCK_PRS,4,2                  ## @BLOCK_PRS
	.comm	_PRS_REG_HDRS_AFTER_BASIC_PORT_1,4,2 ## @PRS_REG_HDRS_AFTER_BASIC_PORT_1
	.comm	_PRS_REG_HDRS_AFTER_BASIC_PORT_0,4,2 ## @PRS_REG_HDRS_AFTER_BASIC_PORT_0
	.comm	_PRS_REG_HDRS_AFTER_TAG_0_PORT_1,4,2 ## @PRS_REG_HDRS_AFTER_TAG_0_PORT_1
	.comm	_PRS_REG_HDRS_AFTER_TAG_0_PORT_0,4,2 ## @PRS_REG_HDRS_AFTER_TAG_0_PORT_0
	.comm	_PRS_REG_MUST_HAVE_HDRS_PORT_1,4,2 ## @PRS_REG_MUST_HAVE_HDRS_PORT_1
	.comm	_PRS_REG_MUST_HAVE_HDRS_PORT_0,4,2 ## @PRS_REG_MUST_HAVE_HDRS_PORT_0
	.comm	_BLOCK_TSDM,4,2                 ## @BLOCK_TSDM
	.comm	_BLOCK_CSDM,4,2                 ## @BLOCK_CSDM
	.comm	_BLOCK_USDM,4,2                 ## @BLOCK_USDM
	.comm	_BLOCK_XSDM,4,2                 ## @BLOCK_XSDM
	.comm	_BLOCK_TSEM,4,2                 ## @BLOCK_TSEM
	.comm	_BLOCK_USEM,4,2                 ## @BLOCK_USEM
	.comm	_BLOCK_CSEM,4,2                 ## @BLOCK_CSEM
	.comm	_BLOCK_XSEM,4,2                 ## @BLOCK_XSEM
	.comm	_BLOCK_UPB,4,2                  ## @BLOCK_UPB
	.comm	_BLOCK_XPB,4,2                  ## @BLOCK_XPB
	.comm	_BLOCK_PBF,4,2                  ## @BLOCK_PBF
	.comm	_PBF_REG_P0_PAUSE_ENABLE,4,2    ## @PBF_REG_P0_PAUSE_ENABLE
	.comm	_PBF_REG_P0_ARB_THRSH,4,2       ## @PBF_REG_P0_ARB_THRSH
	.comm	_PBF_REG_P0_INIT_CRD,4,2        ## @PBF_REG_P0_INIT_CRD
	.comm	_PBF_REG_INIT_P0,4,2            ## @PBF_REG_INIT_P0
	.comm	_BLOCK_SRC,4,2                  ## @BLOCK_SRC
	.comm	_BLOCK_CDU,4,2                  ## @BLOCK_CDU
	.comm	_BLOCK_CFC,4,2                  ## @BLOCK_CFC
	.comm	_HC_REG_LEADING_EDGE_0,4,2      ## @HC_REG_LEADING_EDGE_0
	.comm	_HC_REG_TRAILING_EDGE_0,4,2     ## @HC_REG_TRAILING_EDGE_0
	.comm	_BLOCK_HC,4,2                   ## @BLOCK_HC
	.comm	_BLOCK_IGU,4,2                  ## @BLOCK_IGU
	.comm	_BLOCK_MISC_AEU,4,2             ## @BLOCK_MISC_AEU
	.comm	_MISC_REG_AEU_MASK_ATTN_FUNC_0,4,2 ## @MISC_REG_AEU_MASK_ATTN_FUNC_0
	.comm	_MISC_REG_AEU_ENABLE4_NIG_1,4,2 ## @MISC_REG_AEU_ENABLE4_NIG_1
	.comm	_MISC_REG_AEU_ENABLE4_NIG_0,4,2 ## @MISC_REG_AEU_ENABLE4_NIG_0
	.comm	_AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY,4,2 ## @AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY
	.comm	_MISC_REG_AEU_ENABLE4_PXP_1,4,2 ## @MISC_REG_AEU_ENABLE4_PXP_1
	.comm	_MISC_REG_AEU_ENABLE4_PXP_0,4,2 ## @MISC_REG_AEU_ENABLE4_PXP_0
	.comm	_BLOCK_NIG,4,2                  ## @BLOCK_NIG
	.comm	_NIG_REG_P1_HDRS_AFTER_BASIC,4,2 ## @NIG_REG_P1_HDRS_AFTER_BASIC
	.comm	_NIG_REG_P0_HDRS_AFTER_BASIC,4,2 ## @NIG_REG_P0_HDRS_AFTER_BASIC
	.comm	_NIG_REG_LLH1_MF_MODE,4,2       ## @NIG_REG_LLH1_MF_MODE
	.comm	_NIG_REG_LLH_MF_MODE,4,2        ## @NIG_REG_LLH_MF_MODE
	.comm	_NIG_REG_XGXS_SERDES0_MODE_SEL,4,2 ## @NIG_REG_XGXS_SERDES0_MODE_SEL
	.comm	_NIG_REG_LLH0_BRB1_DRV_MASK_MF,4,2 ## @NIG_REG_LLH0_BRB1_DRV_MASK_MF
	.comm	_NIG_REG_LLH1_CLS_TYPE,4,2      ## @NIG_REG_LLH1_CLS_TYPE
	.comm	_NIG_REG_LLH0_CLS_TYPE,4,2      ## @NIG_REG_LLH0_CLS_TYPE
	.comm	_NIG_REG_LLFC_ENABLE_0,4,2      ## @NIG_REG_LLFC_ENABLE_0
	.comm	_NIG_REG_LLFC_OUT_EN_0,4,2      ## @NIG_REG_LLFC_OUT_EN_0
	.comm	_NIG_REG_PAUSE_ENABLE_0,4,2     ## @NIG_REG_PAUSE_ENABLE_0
	.comm	_MISC_REG_SPIO_EVENT_EN,4,2     ## @MISC_REG_SPIO_EVENT_EN
	.comm	_MISC_SPIO_SPIO5,4,2            ## @MISC_SPIO_SPIO5
	.comm	_MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0,4,2 ## @MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
	.comm	_MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0,4,2 ## @MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
	.comm	_AEU_INPUTS_ATTN_BITS_SPIO5,4,2 ## @AEU_INPUTS_ATTN_BITS_SPIO5
	.comm	_PTP_SUPPORTED,4,2              ## @PTP_SUPPORTED
	.no_dead_strip	_bnx2x_init_hw_port
	.section	__TEXT,__const
	.p2align	2                               ## @switch.table.bnx2x_init_hw_port
l_switch.table.bnx2x_init_hw_port:
	.long	2                               ## 0x2
	.long	1                               ## 0x1
	.long	2                               ## 0x2

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function bnx2x_init_hw_port
_bnx2x_init_hw_port:                    ; @bnx2x_init_hw_port
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	bl	_BP_PORT
	mov	x20, x0
Lloh0:
	adrp	x8, _PHASE_PORT1@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PHASE_PORT1@GOTPAGEOFF]
Lloh2:
	adrp	x9, _PHASE_PORT0@GOTPAGE
Lloh3:
	ldr	x9, [x9, _PHASE_PORT0@GOTPAGEOFF]
	cmp	w0, #0
	csel	x8, x9, x8, eq
	ldr	w21, [x8]
Lloh4:
	adrp	x8, _NETIF_MSG_HW@GOTPAGE
Lloh5:
	ldr	x8, [x8, _NETIF_MSG_HW@GOTPAGEOFF]
Lloh6:
	ldr	w0, [x8]
Lloh7:
	adrp	x1, l_.str@PAGE
Lloh8:
	add	x1, x1, l_.str@PAGEOFF
	mov	x2, x20
	bl	_DP
Lloh9:
	adrp	x8, _NIG_REG_MASK_INTERRUPT_PORT0@GOTPAGE
Lloh10:
	ldr	x8, [x8, _NIG_REG_MASK_INTERRUPT_PORT0@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	lsl	w23, w20, #2
	add	w1, w8, w23
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh12:
	adrp	x8, _BLOCK_MISC@GOTPAGE
Lloh13:
	ldr	x8, [x8, _BLOCK_MISC@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh15:
	adrp	x8, _BLOCK_PXP@GOTPAGE
Lloh16:
	ldr	x8, [x8, _BLOCK_PXP@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh18:
	adrp	x8, _BLOCK_PXP2@GOTPAGE
Lloh19:
	ldr	x8, [x8, _BLOCK_PXP2@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
	mov	x0, x19
	bl	_CHIP_IS_E1x
	cbnz	x0, LBB0_2
; %bb.1:
Lloh21:
	adrp	x8, _PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER@GOTPAGE
Lloh22:
	ldr	x8, [x8, _PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_REG_WR
LBB0_2:
Lloh24:
	adrp	x8, _BLOCK_ATC@GOTPAGE
Lloh25:
	ldr	x8, [x8, _BLOCK_ATC@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh27:
	adrp	x8, _BLOCK_DMAE@GOTPAGE
Lloh28:
	ldr	x8, [x8, _BLOCK_DMAE@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh30:
	adrp	x8, _BLOCK_PGLUE_B@GOTPAGE
Lloh31:
	ldr	x8, [x8, _BLOCK_PGLUE_B@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh33:
	adrp	x8, _BLOCK_QM@GOTPAGE
Lloh34:
	ldr	x8, [x8, _BLOCK_QM@GOTPAGEOFF]
Lloh35:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh36:
	adrp	x8, _BLOCK_TCM@GOTPAGE
Lloh37:
	ldr	x8, [x8, _BLOCK_TCM@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh39:
	adrp	x8, _BLOCK_UCM@GOTPAGE
Lloh40:
	ldr	x8, [x8, _BLOCK_UCM@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh42:
	adrp	x8, _BLOCK_CCM@GOTPAGE
Lloh43:
	ldr	x8, [x8, _BLOCK_CCM@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh45:
	adrp	x8, _BLOCK_XCM@GOTPAGE
Lloh46:
	ldr	x8, [x8, _BLOCK_XCM@GOTPAGEOFF]
Lloh47:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
	ldr	w1, [x19, #24]
Lloh48:
	adrp	x8, _INITOP_SET@GOTPAGE
Lloh49:
	ldr	x8, [x8, _INITOP_SET@GOTPAGEOFF]
Lloh50:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_bnx2x_qm_init_cid_count
	mov	x0, x19
	bl	_CNIC_SUPPORT
	cbz	x0, LBB0_4
; %bb.3:
Lloh51:
	adrp	x8, _BLOCK_TM@GOTPAGE
Lloh52:
	ldr	x8, [x8, _BLOCK_TM@GOTPAGEOFF]
Lloh53:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh54:
	adrp	x8, _TM_REG_LIN0_SCAN_TIME@GOTPAGE
Lloh55:
	ldr	x8, [x8, _TM_REG_LIN0_SCAN_TIME@GOTPAGEOFF]
Lloh56:
	ldr	w8, [x8]
	add	w1, w8, w23
	mov	x0, x19
	mov	w2, #20
	bl	_REG_WR
Lloh57:
	adrp	x8, _TM_REG_LIN0_MAX_ACTIVE_CID@GOTPAGE
Lloh58:
	ldr	x8, [x8, _TM_REG_LIN0_MAX_ACTIVE_CID@GOTPAGEOFF]
Lloh59:
	ldr	w8, [x8]
	add	w1, w8, w23
	mov	x0, x19
	mov	w2, #31
	bl	_REG_WR
LBB0_4:
Lloh60:
	adrp	x8, _BLOCK_DORQ@GOTPAGE
Lloh61:
	ldr	x8, [x8, _BLOCK_DORQ@GOTPAGEOFF]
Lloh62:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh63:
	adrp	x8, _BLOCK_BRB1@GOTPAGE
Lloh64:
	ldr	x8, [x8, _BLOCK_BRB1@GOTPAGEOFF]
Lloh65:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
	mov	x0, x19
	bl	_CHIP_IS_E1
	cbnz	x0, LBB0_6
; %bb.5:
	mov	x0, x19
	bl	_CHIP_IS_E1H
	cbz	x0, LBB0_10
LBB0_6:
	mov	x0, x19
	bl	_IS_MF
Lloh66:
	adrp	x8, _ONE_PORT_FLAG@GOTPAGE
Lloh67:
	ldr	x8, [x8, _ONE_PORT_FLAG@GOTPAGEOFF]
	cbz	w0, LBB0_8
; %bb.7:
	ldr	w9, [x19]
	ldr	w8, [x8]
	tst	w8, w9
	mov	w8, #160
	mov	w9, #246
	csel	w2, w9, w8, eq
	b	LBB0_9
LBB0_8:
	ldr	x9, [x19, #16]
	ldr	w9, [x9]
	ldr	w10, [x19]
	ldr	w8, [x8]
	and	w8, w8, w10
	mov	w10, #80
	mov	w11, #160
	cmp	w8, #0
	csel	w10, w11, w10, eq
	mov	w11, #160
	lsr	w12, w9, #6
	tst	w9, #0x3f
	cinc	w12, w12, ne
	add	w12, w12, #96
	cmp	w8, #0
	csel	w8, w11, w12, ne
	cmp	w9, #1, lsl #12                 ; =4096
	csel	w2, w10, w8, le
LBB0_9:
	add	w22, w2, #56
Lloh68:
	adrp	x8, _BRB1_REG_PAUSE_LOW_THRESHOLD_0@GOTPAGE
Lloh69:
	ldr	x8, [x8, _BRB1_REG_PAUSE_LOW_THRESHOLD_0@GOTPAGEOFF]
Lloh70:
	ldr	w8, [x8]
	add	w1, w8, w23
	mov	x0, x19
	bl	_REG_WR
Lloh71:
	adrp	x8, _BRB1_REG_PAUSE_HIGH_THRESHOLD_0@GOTPAGE
Lloh72:
	ldr	x8, [x8, _BRB1_REG_PAUSE_HIGH_THRESHOLD_0@GOTPAGEOFF]
Lloh73:
	ldr	w8, [x8]
	add	w1, w8, w23
	mov	x0, x19
	mov	x2, x22
	bl	_REG_WR
LBB0_10:
	mov	x0, x19
	bl	_CHIP_MODE_IS_4_PORT
	cbz	x0, LBB0_12
; %bb.11:
	mov	x0, x19
	bl	_BP_PORT
Lloh74:
	adrp	x8, _BRB1_REG_MAC_GUARANTIED_1@GOTPAGE
Lloh75:
	ldr	x8, [x8, _BRB1_REG_MAC_GUARANTIED_1@GOTPAGEOFF]
Lloh76:
	adrp	x9, _BRB1_REG_MAC_GUARANTIED_0@GOTPAGE
Lloh77:
	ldr	x9, [x9, _BRB1_REG_MAC_GUARANTIED_0@GOTPAGEOFF]
	cmp	w0, #0
	csel	x8, x9, x8, eq
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #40
	bl	_REG_WR
LBB0_12:
Lloh78:
	adrp	x8, _BLOCK_PRS@GOTPAGE
Lloh79:
	ldr	x8, [x8, _BLOCK_PRS@GOTPAGEOFF]
Lloh80:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
	mov	x0, x19
	bl	_CHIP_IS_E3B0
	cbz	x0, LBB0_17
; %bb.13:
	mov	x0, x19
	bl	_IS_MF_AFEX
	mov	x22, x0
	mov	x0, x19
	bl	_BP_PORT
Lloh81:
	adrp	x8, _PRS_REG_HDRS_AFTER_BASIC_PORT_1@GOTPAGE
Lloh82:
	ldr	x8, [x8, _PRS_REG_HDRS_AFTER_BASIC_PORT_1@GOTPAGEOFF]
Lloh83:
	adrp	x9, _PRS_REG_HDRS_AFTER_BASIC_PORT_0@GOTPAGE
Lloh84:
	ldr	x9, [x9, _PRS_REG_HDRS_AFTER_BASIC_PORT_0@GOTPAGEOFF]
	cmp	w0, #0
	csel	x8, x9, x8, eq
	ldr	w1, [x8]
	cbz	x22, LBB0_15
; %bb.14:
	mov	x0, x19
	mov	w2, #14
	bl	_REG_WR
	mov	x0, x19
	bl	_BP_PORT
Lloh85:
	adrp	x8, _PRS_REG_HDRS_AFTER_TAG_0_PORT_1@GOTPAGE
Lloh86:
	ldr	x8, [x8, _PRS_REG_HDRS_AFTER_TAG_0_PORT_1@GOTPAGEOFF]
Lloh87:
	adrp	x9, _PRS_REG_HDRS_AFTER_TAG_0_PORT_0@GOTPAGE
Lloh88:
	ldr	x9, [x9, _PRS_REG_HDRS_AFTER_TAG_0_PORT_0@GOTPAGEOFF]
	cmp	w0, #0
	csel	x8, x9, x8, eq
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #6
	bl	_REG_WR
	mov	x0, x19
	bl	_BP_PORT
Lloh89:
	adrp	x8, _PRS_REG_MUST_HAVE_HDRS_PORT_1@GOTPAGE
Lloh90:
	ldr	x8, [x8, _PRS_REG_MUST_HAVE_HDRS_PORT_1@GOTPAGEOFF]
Lloh91:
	adrp	x9, _PRS_REG_MUST_HAVE_HDRS_PORT_0@GOTPAGE
Lloh92:
	ldr	x9, [x9, _PRS_REG_MUST_HAVE_HDRS_PORT_0@GOTPAGEOFF]
	cmp	w0, #0
	csel	x8, x9, x8, eq
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #10
	b	LBB0_16
LBB0_15:
	ldr	x8, [x19, #8]
	cmp	x8, #0
	mov	w8, #6
	cinc	w2, w8, ne
	mov	x0, x19
LBB0_16:
	bl	_REG_WR
LBB0_17:
Lloh93:
	adrp	x8, _BLOCK_TSDM@GOTPAGE
Lloh94:
	ldr	x8, [x8, _BLOCK_TSDM@GOTPAGEOFF]
Lloh95:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh96:
	adrp	x8, _BLOCK_CSDM@GOTPAGE
Lloh97:
	ldr	x8, [x8, _BLOCK_CSDM@GOTPAGEOFF]
Lloh98:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh99:
	adrp	x8, _BLOCK_USDM@GOTPAGE
Lloh100:
	ldr	x8, [x8, _BLOCK_USDM@GOTPAGEOFF]
Lloh101:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh102:
	adrp	x8, _BLOCK_XSDM@GOTPAGE
Lloh103:
	ldr	x8, [x8, _BLOCK_XSDM@GOTPAGEOFF]
Lloh104:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh105:
	adrp	x8, _BLOCK_TSEM@GOTPAGE
Lloh106:
	ldr	x8, [x8, _BLOCK_TSEM@GOTPAGEOFF]
Lloh107:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh108:
	adrp	x8, _BLOCK_USEM@GOTPAGE
Lloh109:
	ldr	x8, [x8, _BLOCK_USEM@GOTPAGEOFF]
Lloh110:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh111:
	adrp	x8, _BLOCK_CSEM@GOTPAGE
Lloh112:
	ldr	x8, [x8, _BLOCK_CSEM@GOTPAGEOFF]
Lloh113:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh114:
	adrp	x8, _BLOCK_XSEM@GOTPAGE
Lloh115:
	ldr	x8, [x8, _BLOCK_XSEM@GOTPAGEOFF]
Lloh116:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh117:
	adrp	x8, _BLOCK_UPB@GOTPAGE
Lloh118:
	ldr	x8, [x8, _BLOCK_UPB@GOTPAGEOFF]
Lloh119:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh120:
	adrp	x8, _BLOCK_XPB@GOTPAGE
Lloh121:
	ldr	x8, [x8, _BLOCK_XPB@GOTPAGEOFF]
Lloh122:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh123:
	adrp	x8, _BLOCK_PBF@GOTPAGE
Lloh124:
	ldr	x8, [x8, _BLOCK_PBF@GOTPAGEOFF]
Lloh125:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
	mov	x0, x19
	bl	_CHIP_IS_E1x
	cbz	x0, LBB0_19
; %bb.18:
Lloh126:
	adrp	x8, _PBF_REG_P0_PAUSE_ENABLE@GOTPAGE
Lloh127:
	ldr	x8, [x8, _PBF_REG_P0_PAUSE_ENABLE@GOTPAGEOFF]
Lloh128:
	ldr	w8, [x8]
	add	w1, w8, w23
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh129:
	adrp	x8, _PBF_REG_P0_ARB_THRSH@GOTPAGE
Lloh130:
	ldr	x8, [x8, _PBF_REG_P0_ARB_THRSH@GOTPAGEOFF]
Lloh131:
	ldr	w8, [x8]
	add	w1, w8, w23
	mov	x0, x19
	mov	w2, #565
	bl	_REG_WR
Lloh132:
	adrp	x8, _PBF_REG_P0_INIT_CRD@GOTPAGE
Lloh133:
	ldr	x8, [x8, _PBF_REG_P0_INIT_CRD@GOTPAGEOFF]
Lloh134:
	ldr	w8, [x8]
	add	w1, w8, w23
	mov	x0, x19
	mov	w2, #1096
	bl	_REG_WR
Lloh135:
	adrp	x22, _PBF_REG_INIT_P0@GOTPAGE
Lloh136:
	ldr	x22, [x22, _PBF_REG_INIT_P0@GOTPAGEOFF]
	ldr	w8, [x22]
	add	w1, w8, w23
	mov	x0, x19
	mov	w2, #1
	bl	_REG_WR
	mov	w0, #50
	bl	_udelay
	ldr	w8, [x22]
	add	w1, w8, w23
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
LBB0_19:
	mov	x0, x19
	bl	_CNIC_SUPPORT
	cbz	x0, LBB0_21
; %bb.20:
Lloh137:
	adrp	x8, _BLOCK_SRC@GOTPAGE
Lloh138:
	ldr	x8, [x8, _BLOCK_SRC@GOTPAGEOFF]
Lloh139:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
LBB0_21:
Lloh140:
	adrp	x8, _BLOCK_CDU@GOTPAGE
Lloh141:
	ldr	x8, [x8, _BLOCK_CDU@GOTPAGEOFF]
Lloh142:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh143:
	adrp	x8, _BLOCK_CFC@GOTPAGE
Lloh144:
	ldr	x8, [x8, _BLOCK_CFC@GOTPAGEOFF]
Lloh145:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
	mov	x0, x19
	bl	_CHIP_IS_E1
	cbz	x0, LBB0_23
; %bb.22:
Lloh146:
	adrp	x8, _HC_REG_LEADING_EDGE_0@GOTPAGE
Lloh147:
	ldr	x8, [x8, _HC_REG_LEADING_EDGE_0@GOTPAGEOFF]
Lloh148:
	ldr	w8, [x8]
	lsl	w22, w20, #3
	add	w1, w8, w22
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh149:
	adrp	x8, _HC_REG_TRAILING_EDGE_0@GOTPAGE
Lloh150:
	ldr	x8, [x8, _HC_REG_TRAILING_EDGE_0@GOTPAGEOFF]
Lloh151:
	ldr	w8, [x8]
	add	w1, w8, w22
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
LBB0_23:
Lloh152:
	adrp	x8, _BLOCK_HC@GOTPAGE
Lloh153:
	ldr	x8, [x8, _BLOCK_HC@GOTPAGEOFF]
Lloh154:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh155:
	adrp	x8, _BLOCK_IGU@GOTPAGE
Lloh156:
	ldr	x8, [x8, _BLOCK_IGU@GOTPAGEOFF]
Lloh157:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
Lloh158:
	adrp	x8, _BLOCK_MISC_AEU@GOTPAGE
Lloh159:
	ldr	x8, [x8, _BLOCK_MISC_AEU@GOTPAGEOFF]
Lloh160:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
	mov	x0, x19
	bl	_IS_MF
	mov	w8, #247
	mov	w9, #7
	cmp	w0, #0
	csel	w22, w9, w8, eq
	mov	x0, x19
	bl	_CHIP_IS_E1
	cmp	x0, #0
	cset	w8, eq
	orr	w2, w22, w8, lsl #4
Lloh161:
	adrp	x8, _MISC_REG_AEU_MASK_ATTN_FUNC_0@GOTPAGE
Lloh162:
	ldr	x8, [x8, _MISC_REG_AEU_MASK_ATTN_FUNC_0@GOTPAGEOFF]
Lloh163:
	ldr	w8, [x8]
	add	w1, w8, w23
	mov	x0, x19
	bl	_REG_WR
Lloh164:
	adrp	x8, _MISC_REG_AEU_ENABLE4_NIG_1@GOTPAGE
Lloh165:
	ldr	x8, [x8, _MISC_REG_AEU_ENABLE4_NIG_1@GOTPAGEOFF]
Lloh166:
	adrp	x9, _MISC_REG_AEU_ENABLE4_NIG_0@GOTPAGE
Lloh167:
	ldr	x9, [x9, _MISC_REG_AEU_ENABLE4_NIG_0@GOTPAGEOFF]
	cmp	w20, #0
	csel	x8, x9, x8, eq
	ldr	w22, [x8]
Lloh168:
	adrp	x8, _MISC_REG_AEU_ENABLE4_PXP_1@GOTPAGE
Lloh169:
	ldr	x8, [x8, _MISC_REG_AEU_ENABLE4_PXP_1@GOTPAGEOFF]
Lloh170:
	adrp	x9, _MISC_REG_AEU_ENABLE4_PXP_0@GOTPAGE
Lloh171:
	ldr	x9, [x9, _MISC_REG_AEU_ENABLE4_PXP_0@GOTPAGEOFF]
	csel	x24, x9, x8, eq
	mov	x0, x19
	mov	x1, x22
	bl	_REG_RD
Lloh172:
	adrp	x25, _AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY@GOTPAGE
Lloh173:
	ldr	x25, [x25, _AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY@GOTPAGEOFF]
	ldr	w8, [x25]
	bic	w2, w0, w8
	mov	x0, x19
	mov	x1, x22
	bl	_REG_WR
	ldr	w22, [x24]
	mov	x0, x19
	mov	x1, x22
	bl	_REG_RD
	ldr	w8, [x25]
	bic	w2, w0, w8
	mov	x0, x19
	mov	x1, x22
	bl	_REG_WR
Lloh174:
	adrp	x8, _BLOCK_NIG@GOTPAGE
Lloh175:
	ldr	x8, [x8, _BLOCK_NIG@GOTPAGEOFF]
Lloh176:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_bnx2x_init_block
	mov	x0, x19
	bl	_CHIP_IS_E1x
	cbnz	x0, LBB0_29
; %bb.24:
	mov	x0, x19
	bl	_IS_MF_AFEX
	mov	x22, x0
	mov	x0, x19
	bl	_BP_PORT
Lloh177:
	adrp	x8, _NIG_REG_P1_HDRS_AFTER_BASIC@GOTPAGE
Lloh178:
	ldr	x8, [x8, _NIG_REG_P1_HDRS_AFTER_BASIC@GOTPAGEOFF]
Lloh179:
	adrp	x9, _NIG_REG_P0_HDRS_AFTER_BASIC@GOTPAGE
Lloh180:
	ldr	x9, [x9, _NIG_REG_P0_HDRS_AFTER_BASIC@GOTPAGEOFF]
	cmp	w0, #0
	csel	x8, x9, x8, eq
	ldr	w21, [x8]
	cbz	x22, LBB0_26
; %bb.25:
	mov	w2, #14
	b	LBB0_27
LBB0_26:
	mov	x0, x19
	bl	_IS_MF_SD
	cmp	x0, #0
	mov	w8, #6
	cinc	w2, w8, ne
LBB0_27:
	mov	x0, x19
	mov	x1, x21
	bl	_REG_WR
	mov	x0, x19
	bl	_CHIP_IS_E3
	cbz	x0, LBB0_29
; %bb.28:
	mov	x0, x19
	bl	_BP_PORT
Lloh181:
	adrp	x8, _NIG_REG_LLH1_MF_MODE@GOTPAGE
Lloh182:
	ldr	x8, [x8, _NIG_REG_LLH1_MF_MODE@GOTPAGEOFF]
Lloh183:
	adrp	x9, _NIG_REG_LLH_MF_MODE@GOTPAGE
Lloh184:
	ldr	x9, [x9, _NIG_REG_LLH_MF_MODE@GOTPAGEOFF]
	cmp	w0, #0
	csel	x8, x9, x8, eq
	ldr	w21, [x8]
	mov	x0, x19
	bl	_IS_MF
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_REG_WR
LBB0_29:
	mov	x0, x19
	bl	_CHIP_IS_E3
	cbnz	x0, LBB0_31
; %bb.30:
Lloh185:
	adrp	x8, _NIG_REG_XGXS_SERDES0_MODE_SEL@GOTPAGE
Lloh186:
	ldr	x8, [x8, _NIG_REG_XGXS_SERDES0_MODE_SEL@GOTPAGEOFF]
Lloh187:
	ldr	w8, [x8]
	add	w1, w8, w23
	mov	x0, x19
	mov	w2, #1
	bl	_REG_WR
LBB0_31:
	mov	x0, x19
	bl	_CHIP_IS_E1
	cbnz	x0, LBB0_38
; %bb.32:
Lloh188:
	adrp	x8, _NIG_REG_LLH0_BRB1_DRV_MASK_MF@GOTPAGE
Lloh189:
	ldr	x8, [x8, _NIG_REG_LLH0_BRB1_DRV_MASK_MF@GOTPAGEOFF]
Lloh190:
	ldr	w8, [x8]
	add	w21, w8, w23
	mov	x0, x19
	bl	_IS_MF_SD
	cmp	x0, #0
	mov	w8, #1
	cinc	w2, w8, eq
	mov	x0, x19
	mov	x1, x21
	bl	_REG_WR
	mov	x0, x19
	bl	_CHIP_IS_E1x
	cbnz	x0, LBB0_37
; %bb.33:
	ldr	w8, [x19, #4]
	sub	w8, w8, #128
	cmp	w8, #2
	b.hi	LBB0_35
; %bb.34:
Lloh191:
	adrp	x9, l_switch.table.bnx2x_init_hw_port@PAGE
Lloh192:
	add	x9, x9, l_switch.table.bnx2x_init_hw_port@PAGEOFF
	ldr	w21, [x9, w8, sxtw #2]
	b	LBB0_36
LBB0_35:
	mov	w21, #0
LBB0_36:
	mov	x0, x19
	bl	_BP_PORT
Lloh193:
	adrp	x8, _NIG_REG_LLH1_CLS_TYPE@GOTPAGE
Lloh194:
	ldr	x8, [x8, _NIG_REG_LLH1_CLS_TYPE@GOTPAGEOFF]
Lloh195:
	adrp	x9, _NIG_REG_LLH0_CLS_TYPE@GOTPAGE
Lloh196:
	ldr	x9, [x9, _NIG_REG_LLH0_CLS_TYPE@GOTPAGEOFF]
	cmp	w0, #0
	csel	x8, x9, x8, eq
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_REG_WR
LBB0_37:
Lloh197:
	adrp	x8, _NIG_REG_LLFC_ENABLE_0@GOTPAGE
Lloh198:
	ldr	x8, [x8, _NIG_REG_LLFC_ENABLE_0@GOTPAGEOFF]
Lloh199:
	ldr	w8, [x8]
	add	w1, w8, w23
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh200:
	adrp	x8, _NIG_REG_LLFC_OUT_EN_0@GOTPAGE
Lloh201:
	ldr	x8, [x8, _NIG_REG_LLFC_OUT_EN_0@GOTPAGEOFF]
Lloh202:
	ldr	w8, [x8]
	add	w1, w8, w23
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh203:
	adrp	x8, _NIG_REG_PAUSE_ENABLE_0@GOTPAGE
Lloh204:
	ldr	x8, [x8, _NIG_REG_PAUSE_ENABLE_0@GOTPAGEOFF]
Lloh205:
	ldr	w8, [x8]
	add	w1, w8, w23
	mov	x0, x19
	mov	w2, #1
	bl	_REG_WR
LBB0_38:
Lloh206:
	adrp	x8, _MISC_REG_SPIO_EVENT_EN@GOTPAGE
Lloh207:
	ldr	x8, [x8, _MISC_REG_SPIO_EVENT_EN@GOTPAGEOFF]
Lloh208:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_REG_RD
Lloh209:
	adrp	x8, _MISC_SPIO_SPIO5@GOTPAGE
Lloh210:
	ldr	x8, [x8, _MISC_SPIO_SPIO5@GOTPAGEOFF]
Lloh211:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_40
; %bb.39:
Lloh212:
	adrp	x8, _MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0@GOTPAGE
Lloh213:
	ldr	x8, [x8, _MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0@GOTPAGEOFF]
Lloh214:
	adrp	x9, _MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0@GOTPAGE
Lloh215:
	ldr	x9, [x9, _MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0@GOTPAGEOFF]
	cmp	w20, #0
	csel	x8, x9, x8, eq
	ldr	w20, [x8]
	mov	x0, x19
	mov	x1, x20
	bl	_REG_RD
Lloh216:
	adrp	x8, _AEU_INPUTS_ATTN_BITS_SPIO5@GOTPAGE
Lloh217:
	ldr	x8, [x8, _AEU_INPUTS_ATTN_BITS_SPIO5@GOTPAGEOFF]
Lloh218:
	ldr	w8, [x8]
	orr	w2, w8, w0
	mov	x0, x19
	mov	x1, x20
	bl	_REG_WR
LBB0_40:
	mov	x0, x19
	bl	_CHIP_IS_E3B0
	cbz	x0, LBB0_42
; %bb.41:
Lloh219:
	adrp	x8, _PTP_SUPPORTED@GOTPAGE
Lloh220:
	ldr	x8, [x8, _PTP_SUPPORTED@GOTPAGEOFF]
Lloh221:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_42:
	mov	w0, #0
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpAdd	Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGot	Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGot	Lloh76, Lloh77
	.loh AdrpLdrGot	Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGot	Lloh83, Lloh84
	.loh AdrpLdrGot	Lloh81, Lloh82
	.loh AdrpLdrGot	Lloh91, Lloh92
	.loh AdrpLdrGot	Lloh89, Lloh90
	.loh AdrpLdrGot	Lloh87, Lloh88
	.loh AdrpLdrGot	Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh123, Lloh124, Lloh125
	.loh AdrpLdrGotLdr	Lloh120, Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGot	Lloh135, Lloh136
	.loh AdrpLdrGotLdr	Lloh132, Lloh133, Lloh134
	.loh AdrpLdrGotLdr	Lloh129, Lloh130, Lloh131
	.loh AdrpLdrGotLdr	Lloh126, Lloh127, Lloh128
	.loh AdrpLdrGotLdr	Lloh137, Lloh138, Lloh139
	.loh AdrpLdrGotLdr	Lloh143, Lloh144, Lloh145
	.loh AdrpLdrGotLdr	Lloh140, Lloh141, Lloh142
	.loh AdrpLdrGotLdr	Lloh149, Lloh150, Lloh151
	.loh AdrpLdrGotLdr	Lloh146, Lloh147, Lloh148
	.loh AdrpLdrGotLdr	Lloh174, Lloh175, Lloh176
	.loh AdrpLdrGot	Lloh172, Lloh173
	.loh AdrpLdrGot	Lloh170, Lloh171
	.loh AdrpLdrGot	Lloh168, Lloh169
	.loh AdrpLdrGot	Lloh166, Lloh167
	.loh AdrpLdrGot	Lloh164, Lloh165
	.loh AdrpLdrGotLdr	Lloh161, Lloh162, Lloh163
	.loh AdrpLdrGotLdr	Lloh158, Lloh159, Lloh160
	.loh AdrpLdrGotLdr	Lloh155, Lloh156, Lloh157
	.loh AdrpLdrGotLdr	Lloh152, Lloh153, Lloh154
	.loh AdrpLdrGot	Lloh179, Lloh180
	.loh AdrpLdrGot	Lloh177, Lloh178
	.loh AdrpLdrGot	Lloh183, Lloh184
	.loh AdrpLdrGot	Lloh181, Lloh182
	.loh AdrpLdrGotLdr	Lloh185, Lloh186, Lloh187
	.loh AdrpLdrGotLdr	Lloh188, Lloh189, Lloh190
	.loh AdrpAdd	Lloh191, Lloh192
	.loh AdrpLdrGot	Lloh195, Lloh196
	.loh AdrpLdrGot	Lloh193, Lloh194
	.loh AdrpLdrGotLdr	Lloh203, Lloh204, Lloh205
	.loh AdrpLdrGotLdr	Lloh200, Lloh201, Lloh202
	.loh AdrpLdrGotLdr	Lloh197, Lloh198, Lloh199
	.loh AdrpLdrGotLdr	Lloh209, Lloh210, Lloh211
	.loh AdrpLdrGotLdr	Lloh206, Lloh207, Lloh208
	.loh AdrpLdrGotLdr	Lloh216, Lloh217, Lloh218
	.loh AdrpLdrGot	Lloh214, Lloh215
	.loh AdrpLdrGot	Lloh212, Lloh213
	.loh AdrpLdrGotLdr	Lloh219, Lloh220, Lloh221
	.cfi_endproc
                                        ; -- End function
	.comm	_PHASE_PORT1,4,2                ; @PHASE_PORT1
	.comm	_PHASE_PORT0,4,2                ; @PHASE_PORT0
	.comm	_NETIF_MSG_HW,4,2               ; @NETIF_MSG_HW
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"starting port init  port %d\n"

	.comm	_NIG_REG_MASK_INTERRUPT_PORT0,4,2 ; @NIG_REG_MASK_INTERRUPT_PORT0
	.comm	_BLOCK_MISC,4,2                 ; @BLOCK_MISC
	.comm	_BLOCK_PXP,4,2                  ; @BLOCK_PXP
	.comm	_BLOCK_PXP2,4,2                 ; @BLOCK_PXP2
	.comm	_PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,4,2 ; @PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
	.comm	_BLOCK_ATC,4,2                  ; @BLOCK_ATC
	.comm	_BLOCK_DMAE,4,2                 ; @BLOCK_DMAE
	.comm	_BLOCK_PGLUE_B,4,2              ; @BLOCK_PGLUE_B
	.comm	_BLOCK_QM,4,2                   ; @BLOCK_QM
	.comm	_BLOCK_TCM,4,2                  ; @BLOCK_TCM
	.comm	_BLOCK_UCM,4,2                  ; @BLOCK_UCM
	.comm	_BLOCK_CCM,4,2                  ; @BLOCK_CCM
	.comm	_BLOCK_XCM,4,2                  ; @BLOCK_XCM
	.comm	_INITOP_SET,4,2                 ; @INITOP_SET
	.comm	_BLOCK_TM,4,2                   ; @BLOCK_TM
	.comm	_TM_REG_LIN0_SCAN_TIME,4,2      ; @TM_REG_LIN0_SCAN_TIME
	.comm	_TM_REG_LIN0_MAX_ACTIVE_CID,4,2 ; @TM_REG_LIN0_MAX_ACTIVE_CID
	.comm	_BLOCK_DORQ,4,2                 ; @BLOCK_DORQ
	.comm	_BLOCK_BRB1,4,2                 ; @BLOCK_BRB1
	.comm	_ONE_PORT_FLAG,4,2              ; @ONE_PORT_FLAG
	.comm	_BRB1_REG_PAUSE_LOW_THRESHOLD_0,4,2 ; @BRB1_REG_PAUSE_LOW_THRESHOLD_0
	.comm	_BRB1_REG_PAUSE_HIGH_THRESHOLD_0,4,2 ; @BRB1_REG_PAUSE_HIGH_THRESHOLD_0
	.comm	_BRB1_REG_MAC_GUARANTIED_1,4,2  ; @BRB1_REG_MAC_GUARANTIED_1
	.comm	_BRB1_REG_MAC_GUARANTIED_0,4,2  ; @BRB1_REG_MAC_GUARANTIED_0
	.comm	_BLOCK_PRS,4,2                  ; @BLOCK_PRS
	.comm	_PRS_REG_HDRS_AFTER_BASIC_PORT_1,4,2 ; @PRS_REG_HDRS_AFTER_BASIC_PORT_1
	.comm	_PRS_REG_HDRS_AFTER_BASIC_PORT_0,4,2 ; @PRS_REG_HDRS_AFTER_BASIC_PORT_0
	.comm	_PRS_REG_HDRS_AFTER_TAG_0_PORT_1,4,2 ; @PRS_REG_HDRS_AFTER_TAG_0_PORT_1
	.comm	_PRS_REG_HDRS_AFTER_TAG_0_PORT_0,4,2 ; @PRS_REG_HDRS_AFTER_TAG_0_PORT_0
	.comm	_PRS_REG_MUST_HAVE_HDRS_PORT_1,4,2 ; @PRS_REG_MUST_HAVE_HDRS_PORT_1
	.comm	_PRS_REG_MUST_HAVE_HDRS_PORT_0,4,2 ; @PRS_REG_MUST_HAVE_HDRS_PORT_0
	.comm	_BLOCK_TSDM,4,2                 ; @BLOCK_TSDM
	.comm	_BLOCK_CSDM,4,2                 ; @BLOCK_CSDM
	.comm	_BLOCK_USDM,4,2                 ; @BLOCK_USDM
	.comm	_BLOCK_XSDM,4,2                 ; @BLOCK_XSDM
	.comm	_BLOCK_TSEM,4,2                 ; @BLOCK_TSEM
	.comm	_BLOCK_USEM,4,2                 ; @BLOCK_USEM
	.comm	_BLOCK_CSEM,4,2                 ; @BLOCK_CSEM
	.comm	_BLOCK_XSEM,4,2                 ; @BLOCK_XSEM
	.comm	_BLOCK_UPB,4,2                  ; @BLOCK_UPB
	.comm	_BLOCK_XPB,4,2                  ; @BLOCK_XPB
	.comm	_BLOCK_PBF,4,2                  ; @BLOCK_PBF
	.comm	_PBF_REG_P0_PAUSE_ENABLE,4,2    ; @PBF_REG_P0_PAUSE_ENABLE
	.comm	_PBF_REG_P0_ARB_THRSH,4,2       ; @PBF_REG_P0_ARB_THRSH
	.comm	_PBF_REG_P0_INIT_CRD,4,2        ; @PBF_REG_P0_INIT_CRD
	.comm	_PBF_REG_INIT_P0,4,2            ; @PBF_REG_INIT_P0
	.comm	_BLOCK_SRC,4,2                  ; @BLOCK_SRC
	.comm	_BLOCK_CDU,4,2                  ; @BLOCK_CDU
	.comm	_BLOCK_CFC,4,2                  ; @BLOCK_CFC
	.comm	_HC_REG_LEADING_EDGE_0,4,2      ; @HC_REG_LEADING_EDGE_0
	.comm	_HC_REG_TRAILING_EDGE_0,4,2     ; @HC_REG_TRAILING_EDGE_0
	.comm	_BLOCK_HC,4,2                   ; @BLOCK_HC
	.comm	_BLOCK_IGU,4,2                  ; @BLOCK_IGU
	.comm	_BLOCK_MISC_AEU,4,2             ; @BLOCK_MISC_AEU
	.comm	_MISC_REG_AEU_MASK_ATTN_FUNC_0,4,2 ; @MISC_REG_AEU_MASK_ATTN_FUNC_0
	.comm	_MISC_REG_AEU_ENABLE4_NIG_1,4,2 ; @MISC_REG_AEU_ENABLE4_NIG_1
	.comm	_MISC_REG_AEU_ENABLE4_NIG_0,4,2 ; @MISC_REG_AEU_ENABLE4_NIG_0
	.comm	_AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY,4,2 ; @AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY
	.comm	_MISC_REG_AEU_ENABLE4_PXP_1,4,2 ; @MISC_REG_AEU_ENABLE4_PXP_1
	.comm	_MISC_REG_AEU_ENABLE4_PXP_0,4,2 ; @MISC_REG_AEU_ENABLE4_PXP_0
	.comm	_BLOCK_NIG,4,2                  ; @BLOCK_NIG
	.comm	_NIG_REG_P1_HDRS_AFTER_BASIC,4,2 ; @NIG_REG_P1_HDRS_AFTER_BASIC
	.comm	_NIG_REG_P0_HDRS_AFTER_BASIC,4,2 ; @NIG_REG_P0_HDRS_AFTER_BASIC
	.comm	_NIG_REG_LLH1_MF_MODE,4,2       ; @NIG_REG_LLH1_MF_MODE
	.comm	_NIG_REG_LLH_MF_MODE,4,2        ; @NIG_REG_LLH_MF_MODE
	.comm	_NIG_REG_XGXS_SERDES0_MODE_SEL,4,2 ; @NIG_REG_XGXS_SERDES0_MODE_SEL
	.comm	_NIG_REG_LLH0_BRB1_DRV_MASK_MF,4,2 ; @NIG_REG_LLH0_BRB1_DRV_MASK_MF
	.comm	_NIG_REG_LLH1_CLS_TYPE,4,2      ; @NIG_REG_LLH1_CLS_TYPE
	.comm	_NIG_REG_LLH0_CLS_TYPE,4,2      ; @NIG_REG_LLH0_CLS_TYPE
	.comm	_NIG_REG_LLFC_ENABLE_0,4,2      ; @NIG_REG_LLFC_ENABLE_0
	.comm	_NIG_REG_LLFC_OUT_EN_0,4,2      ; @NIG_REG_LLFC_OUT_EN_0
	.comm	_NIG_REG_PAUSE_ENABLE_0,4,2     ; @NIG_REG_PAUSE_ENABLE_0
	.comm	_MISC_REG_SPIO_EVENT_EN,4,2     ; @MISC_REG_SPIO_EVENT_EN
	.comm	_MISC_SPIO_SPIO5,4,2            ; @MISC_SPIO_SPIO5
	.comm	_MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0,4,2 ; @MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
	.comm	_MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0,4,2 ; @MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
	.comm	_AEU_INPUTS_ATTN_BITS_SPIO5,4,2 ; @AEU_INPUTS_ATTN_BITS_SPIO5
	.comm	_PTP_SUPPORTED,4,2              ; @PTP_SUPPORTED
	.no_dead_strip	_bnx2x_init_hw_port
	.section	__TEXT,__const
	.p2align	2                               ; @switch.table.bnx2x_init_hw_port
l_switch.table.bnx2x_init_hw_port:
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	2                               ; 0x2

.subsections_via_symbols
