	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_goya_get_fixed_properties      ## -- Begin function goya_get_fixed_properties
	.p2align	4, 0x90
_goya_get_fixed_properties:             ## @goya_get_fixed_properties
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	_NUMBER_OF_EXT_HW_QUEUES@GOTPCREL(%rip), %r10
	movl	(%r10), %esi
	testl	%esi, %esi
	jle	LBB0_1
## %bb.14:
	movq	176(%rdi), %rdx
	xorl	%eax, %eax
	movq	_QUEUE_TYPE_EXT@GOTPCREL(%rip), %rcx
	.p2align	4, 0x90
LBB0_15:                                ## =>This Inner Loop Header: Depth=1
	movl	(%rcx), %esi
	movl	%esi, 4(%rdx,%rax,8)
	movl	$0, (%rdx,%rax,8)
	incq	%rax
	movslq	(%r10), %rsi
	cmpq	%rsi, %rax
	jl	LBB0_15
	jmp	LBB0_2
LBB0_1:
	xorl	%eax, %eax
LBB0_2:
	movq	_NUMBER_OF_CPU_HW_QUEUES@GOTPCREL(%rip), %r9
	addl	(%r9), %esi
	cmpl	%esi, %eax
	jge	LBB0_5
## %bb.3:
	movq	176(%rdi), %rdx
	movl	%eax, %eax
	movq	_QUEUE_TYPE_CPU@GOTPCREL(%rip), %r8
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r8), %ecx
	movl	%ecx, 4(%rdx,%rax,8)
	movl	$1, (%rdx,%rax,8)
	incq	%rax
	movl	(%r9), %esi
	addl	(%r10), %esi
	cmpl	%eax, %esi
	jg	LBB0_4
LBB0_5:
	movq	_NUMBER_OF_INT_HW_QUEUES@GOTPCREL(%rip), %r8
	addl	(%r8), %esi
	cmpl	%esi, %eax
	jge	LBB0_8
## %bb.6:
	movq	176(%rdi), %rsi
	movl	%eax, %eax
	movq	_QUEUE_TYPE_INT@GOTPCREL(%rip), %rdx
	.p2align	4, 0x90
LBB0_7:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%rdx), %ecx
	movl	%ecx, 4(%rsi,%rax,8)
	movl	$0, (%rsi,%rax,8)
	movl	(%r9), %ecx
	addl	(%r10), %ecx
	incq	%rax
	addl	(%r8), %ecx
	cmpl	%eax, %ecx
	jg	LBB0_7
LBB0_8:
	movq	_HL_MAX_QUEUES@GOTPCREL(%rip), %r8
	cmpl	(%r8), %eax
	jge	LBB0_11
## %bb.9:
	movq	176(%rdi), %rdx
	movl	%eax, %eax
	movq	_QUEUE_TYPE_NA@GOTPCREL(%rip), %rsi
	.p2align	4, 0x90
LBB0_10:                                ## =>This Inner Loop Header: Depth=1
	movl	(%rsi), %ecx
	movl	%ecx, 4(%rdx,%rax,8)
	incq	%rax
	cmpl	%eax, (%r8)
	jg	LBB0_10
LBB0_11:
	movq	_NUMBER_OF_CMPLT_QUEUES@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 168(%rdi)
	movq	_DRAM_PHYS_BASE@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 152(%rdi)
	movq	_DRAM_PHYS_DEFAULT_SIZE@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, 144(%rdi)
	addq	%rax, %rcx
	movq	%rcx, 160(%rdi)
	movq	_DRAM_BASE_ADDR_USER@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 136(%rdi)
	movq	_SRAM_BASE_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 104(%rdi)
	movq	_SRAM_SIZE@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movq	%rcx, 120(%rdi)
	addq	%rax, %rcx
	movq	%rcx, 128(%rdi)
	movq	_SRAM_USER_BASE_OFFSET@GOTPCREL(%rip), %rcx
	addq	(%rcx), %rax
	movq	%rax, 112(%rdi)
	movq	_MMU_PAGE_TABLES_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 100(%rdi)
	movq	_MMU_DRAM_DEFAULT_PAGE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 96(%rdi)
	cmpq	$0, (%rdi)
	movl	$8388608, %eax                  ## imm = 0x800000
	jne	LBB0_13
## %bb.12:
	movq	_MMU_PAGE_TABLES_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_13:
	movl	%eax, 8(%rdi)
	movq	_HL_PTE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 92(%rdi)
	movq	_HOP_TABLE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 88(%rdi)
	movq	_HOP0_TABLES_TOTAL_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 84(%rdi)
	movq	_PAGE_SIZE_2MB@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 80(%rdi)
	movq	_VA_HOST_SPACE_START@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 76(%rdi)
	movq	_VA_HOST_SPACE_END@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 72(%rdi)
	movq	_VA_DDR_SPACE_START@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 68(%rdi)
	movq	_VA_DDR_SPACE_END@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 60(%rdi)
	movl	%eax, 64(%rdi)
	movq	_CFG_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 56(%rdi)
	movq	_MAX_ASID@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 52(%rdi)
	movq	_GOYA_ASYNC_EVENT_ID_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 48(%rdi)
	movq	_PLL_HIGH_DEFAULT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 44(%rdi)
	movq	_GOYA_CB_POOL_CB_CNT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 40(%rdi)
	movq	_GOYA_CB_POOL_CB_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 36(%rdi)
	movq	_MAX_POWER_DEFAULT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 32(%rdi)
	movq	_TPC_ENABLED_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 28(%rdi)
	movq	_mmPCIE_DBI_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 24(%rdi)
	movq	_CFG_BASE@GOTPCREL(%rip), %rax
	movq	_mmPCIE_AUX_DBI@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	addq	(%rax), %rcx
	movq	%rcx, 16(%rdi)
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_NUMBER_OF_EXT_HW_QUEUES,4,2    ## @NUMBER_OF_EXT_HW_QUEUES
	.comm	_QUEUE_TYPE_EXT,4,2             ## @QUEUE_TYPE_EXT
	.comm	_NUMBER_OF_CPU_HW_QUEUES,4,2    ## @NUMBER_OF_CPU_HW_QUEUES
	.comm	_QUEUE_TYPE_CPU,4,2             ## @QUEUE_TYPE_CPU
	.comm	_NUMBER_OF_INT_HW_QUEUES,4,2    ## @NUMBER_OF_INT_HW_QUEUES
	.comm	_QUEUE_TYPE_INT,4,2             ## @QUEUE_TYPE_INT
	.comm	_HL_MAX_QUEUES,4,2              ## @HL_MAX_QUEUES
	.comm	_QUEUE_TYPE_NA,4,2              ## @QUEUE_TYPE_NA
	.comm	_NUMBER_OF_CMPLT_QUEUES,4,2     ## @NUMBER_OF_CMPLT_QUEUES
	.comm	_DRAM_PHYS_BASE,8,3             ## @DRAM_PHYS_BASE
	.comm	_DRAM_PHYS_DEFAULT_SIZE,8,3     ## @DRAM_PHYS_DEFAULT_SIZE
	.comm	_DRAM_BASE_ADDR_USER,4,2        ## @DRAM_BASE_ADDR_USER
	.comm	_SRAM_BASE_ADDR,8,3             ## @SRAM_BASE_ADDR
	.comm	_SRAM_SIZE,8,3                  ## @SRAM_SIZE
	.comm	_SRAM_USER_BASE_OFFSET,8,3      ## @SRAM_USER_BASE_OFFSET
	.comm	_MMU_PAGE_TABLES_ADDR,4,2       ## @MMU_PAGE_TABLES_ADDR
	.comm	_MMU_DRAM_DEFAULT_PAGE_ADDR,4,2 ## @MMU_DRAM_DEFAULT_PAGE_ADDR
	.comm	_MMU_PAGE_TABLES_SIZE,4,2       ## @MMU_PAGE_TABLES_SIZE
	.comm	_HL_PTE_SIZE,4,2                ## @HL_PTE_SIZE
	.comm	_HOP_TABLE_SIZE,4,2             ## @HOP_TABLE_SIZE
	.comm	_HOP0_TABLES_TOTAL_SIZE,4,2     ## @HOP0_TABLES_TOTAL_SIZE
	.comm	_PAGE_SIZE_2MB,4,2              ## @PAGE_SIZE_2MB
	.comm	_VA_HOST_SPACE_START,4,2        ## @VA_HOST_SPACE_START
	.comm	_VA_HOST_SPACE_END,4,2          ## @VA_HOST_SPACE_END
	.comm	_VA_DDR_SPACE_START,4,2         ## @VA_DDR_SPACE_START
	.comm	_VA_DDR_SPACE_END,4,2           ## @VA_DDR_SPACE_END
	.comm	_CFG_SIZE,4,2                   ## @CFG_SIZE
	.comm	_MAX_ASID,4,2                   ## @MAX_ASID
	.comm	_GOYA_ASYNC_EVENT_ID_SIZE,4,2   ## @GOYA_ASYNC_EVENT_ID_SIZE
	.comm	_PLL_HIGH_DEFAULT,4,2           ## @PLL_HIGH_DEFAULT
	.comm	_GOYA_CB_POOL_CB_CNT,4,2        ## @GOYA_CB_POOL_CB_CNT
	.comm	_GOYA_CB_POOL_CB_SIZE,4,2       ## @GOYA_CB_POOL_CB_SIZE
	.comm	_MAX_POWER_DEFAULT,4,2          ## @MAX_POWER_DEFAULT
	.comm	_TPC_ENABLED_MASK,4,2           ## @TPC_ENABLED_MASK
	.comm	_mmPCIE_DBI_BASE,4,2            ## @mmPCIE_DBI_BASE
	.comm	_CFG_BASE,8,3                   ## @CFG_BASE
	.comm	_mmPCIE_AUX_DBI,8,3             ## @mmPCIE_AUX_DBI
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_goya_get_fixed_properties      ; -- Begin function goya_get_fixed_properties
	.p2align	2
_goya_get_fixed_properties:             ; @goya_get_fixed_properties
	.cfi_startproc
; %bb.0:
Lloh0:
	adrp	x9, _NUMBER_OF_EXT_HW_QUEUES@GOTPAGE
Lloh1:
	ldr	x9, [x9, _NUMBER_OF_EXT_HW_QUEUES@GOTPAGEOFF]
	ldr	w11, [x9]
	cmp	w11, #1
	b.lt	LBB0_3
; %bb.1:
	mov	x8, #0
	ldr	x10, [x0, #176]
	add	x10, x10, #4
Lloh2:
	adrp	x12, _QUEUE_TYPE_EXT@GOTPAGE
Lloh3:
	ldr	x12, [x12, _QUEUE_TYPE_EXT@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w11, [x12]
	stp	wzr, w11, [x10, #-4]
	add	x8, x8, #1
	ldrsw	x11, [x9]
	add	x10, x10, #8
	cmp	x8, x11
	b.lt	LBB0_2
	b	LBB0_4
LBB0_3:
	mov	w8, #0
LBB0_4:
Lloh4:
	adrp	x10, _NUMBER_OF_CPU_HW_QUEUES@GOTPAGE
Lloh5:
	ldr	x10, [x10, _NUMBER_OF_CPU_HW_QUEUES@GOTPAGEOFF]
	ldr	w12, [x10]
	add	w12, w12, w11
	cmp	w8, w12
	b.ge	LBB0_7
; %bb.5:
	ldr	x11, [x0, #176]
	add	x11, x11, w8, uxtw #3
	add	x11, x11, #4
Lloh6:
	adrp	x13, _QUEUE_TYPE_CPU@GOTPAGE
Lloh7:
	ldr	x13, [x13, _QUEUE_TYPE_CPU@GOTPAGEOFF]
	mov	w14, #1
LBB0_6:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w12, [x13]
	stp	w14, w12, [x11, #-4]
	ldr	w12, [x9]
	ldr	w15, [x10]
	add	x11, x11, #8
	add	w8, w8, #1
	add	w12, w15, w12
	cmp	w12, w8
	b.gt	LBB0_6
LBB0_7:
Lloh8:
	adrp	x11, _NUMBER_OF_INT_HW_QUEUES@GOTPAGE
Lloh9:
	ldr	x11, [x11, _NUMBER_OF_INT_HW_QUEUES@GOTPAGEOFF]
	ldr	w13, [x11]
	add	w12, w12, w13
	cmp	w8, w12
	b.ge	LBB0_10
; %bb.8:
	ldr	x12, [x0, #176]
	add	x12, x12, w8, uxtw #3
	add	x12, x12, #4
Lloh10:
	adrp	x13, _QUEUE_TYPE_INT@GOTPAGE
Lloh11:
	ldr	x13, [x13, _QUEUE_TYPE_INT@GOTPAGEOFF]
LBB0_9:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w14, [x13]
	stp	wzr, w14, [x12, #-4]
	ldr	w14, [x9]
	ldr	w15, [x10]
	ldr	w16, [x11]
	add	w14, w15, w14
	add	w14, w14, w16
	add	x12, x12, #8
	add	w8, w8, #1
	cmp	w14, w8
	b.gt	LBB0_9
LBB0_10:
Lloh12:
	adrp	x9, _HL_MAX_QUEUES@GOTPAGE
Lloh13:
	ldr	x9, [x9, _HL_MAX_QUEUES@GOTPAGEOFF]
	ldr	w10, [x9]
	cmp	w8, w10
	b.ge	LBB0_13
; %bb.11:
	ldr	x10, [x0, #176]
	add	x10, x10, w8, uxtw #3
	add	x10, x10, #4
Lloh14:
	adrp	x11, _QUEUE_TYPE_NA@GOTPAGE
Lloh15:
	ldr	x11, [x11, _QUEUE_TYPE_NA@GOTPAGEOFF]
LBB0_12:                                ; =>This Inner Loop Header: Depth=1
	ldr	w12, [x11]
	str	w12, [x10], #8
	ldr	w12, [x9]
	add	w8, w8, #1
	cmp	w12, w8
	b.gt	LBB0_12
LBB0_13:
Lloh16:
	adrp	x8, _NUMBER_OF_CMPLT_QUEUES@GOTPAGE
Lloh17:
	ldr	x8, [x8, _NUMBER_OF_CMPLT_QUEUES@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	str	w8, [x0, #168]
Lloh19:
	adrp	x8, _DRAM_PHYS_BASE@GOTPAGE
Lloh20:
	ldr	x8, [x8, _DRAM_PHYS_BASE@GOTPAGEOFF]
Lloh21:
	ldr	x8, [x8]
Lloh22:
	adrp	x9, _DRAM_PHYS_DEFAULT_SIZE@GOTPAGE
Lloh23:
	ldr	x9, [x9, _DRAM_PHYS_DEFAULT_SIZE@GOTPAGEOFF]
Lloh24:
	ldr	x9, [x9]
	stp	x9, x8, [x0, #144]
	add	x8, x9, x8
	str	x8, [x0, #160]
Lloh25:
	adrp	x8, _DRAM_BASE_ADDR_USER@GOTPAGE
Lloh26:
	ldr	x8, [x8, _DRAM_BASE_ADDR_USER@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
	str	w8, [x0, #136]
Lloh28:
	adrp	x8, _SRAM_BASE_ADDR@GOTPAGE
Lloh29:
	ldr	x8, [x8, _SRAM_BASE_ADDR@GOTPAGEOFF]
Lloh30:
	ldr	x8, [x8]
Lloh31:
	adrp	x9, _SRAM_SIZE@GOTPAGE
Lloh32:
	ldr	x9, [x9, _SRAM_SIZE@GOTPAGEOFF]
Lloh33:
	ldr	x9, [x9]
	add	x10, x9, x8
	stp	x9, x10, [x0, #120]
Lloh34:
	adrp	x9, _SRAM_USER_BASE_OFFSET@GOTPAGE
Lloh35:
	ldr	x9, [x9, _SRAM_USER_BASE_OFFSET@GOTPAGEOFF]
Lloh36:
	ldr	x9, [x9]
	add	x9, x9, x8
	stp	x8, x9, [x0, #104]
Lloh37:
	adrp	x8, _MMU_PAGE_TABLES_ADDR@GOTPAGE
Lloh38:
	ldr	x8, [x8, _MMU_PAGE_TABLES_ADDR@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
Lloh40:
	adrp	x9, _MMU_DRAM_DEFAULT_PAGE_ADDR@GOTPAGE
Lloh41:
	ldr	x9, [x9, _MMU_DRAM_DEFAULT_PAGE_ADDR@GOTPAGEOFF]
Lloh42:
	ldr	w9, [x9]
	stp	w9, w8, [x0, #96]
	ldr	x8, [x0]
Lloh43:
	adrp	x9, _MMU_PAGE_TABLES_SIZE@GOTPAGE
Lloh44:
	ldr	x9, [x9, _MMU_PAGE_TABLES_SIZE@GOTPAGEOFF]
Lloh45:
	ldr	w9, [x9]
	cmp	x8, #0
	mov	w8, #8388608
	csel	w8, w9, w8, eq
	str	w8, [x0, #8]
Lloh46:
	adrp	x8, _HL_PTE_SIZE@GOTPAGE
Lloh47:
	ldr	x8, [x8, _HL_PTE_SIZE@GOTPAGEOFF]
Lloh48:
	ldr	w8, [x8]
Lloh49:
	adrp	x9, _HOP_TABLE_SIZE@GOTPAGE
Lloh50:
	ldr	x9, [x9, _HOP_TABLE_SIZE@GOTPAGEOFF]
Lloh51:
	ldr	w9, [x9]
	stp	w9, w8, [x0, #88]
Lloh52:
	adrp	x8, _HOP0_TABLES_TOTAL_SIZE@GOTPAGE
Lloh53:
	ldr	x8, [x8, _HOP0_TABLES_TOTAL_SIZE@GOTPAGEOFF]
Lloh54:
	ldr	w8, [x8]
Lloh55:
	adrp	x9, _PAGE_SIZE_2MB@GOTPAGE
Lloh56:
	ldr	x9, [x9, _PAGE_SIZE_2MB@GOTPAGEOFF]
Lloh57:
	ldr	w9, [x9]
Lloh58:
	adrp	x10, _VA_HOST_SPACE_START@GOTPAGE
Lloh59:
	ldr	x10, [x10, _VA_HOST_SPACE_START@GOTPAGEOFF]
	stp	w9, w8, [x0, #80]
Lloh60:
	ldr	w8, [x10]
Lloh61:
	adrp	x9, _VA_HOST_SPACE_END@GOTPAGE
Lloh62:
	ldr	x9, [x9, _VA_HOST_SPACE_END@GOTPAGEOFF]
Lloh63:
	ldr	w9, [x9]
	stp	w9, w8, [x0, #72]
Lloh64:
	adrp	x8, _VA_DDR_SPACE_START@GOTPAGE
Lloh65:
	ldr	x8, [x8, _VA_DDR_SPACE_START@GOTPAGEOFF]
Lloh66:
	ldr	w8, [x8]
Lloh67:
	adrp	x9, _VA_DDR_SPACE_END@GOTPAGE
Lloh68:
	ldr	x9, [x9, _VA_DDR_SPACE_END@GOTPAGEOFF]
Lloh69:
	ldr	w9, [x9]
	stp	w9, w8, [x0, #64]
Lloh70:
	adrp	x8, _CFG_SIZE@GOTPAGE
Lloh71:
	ldr	x8, [x8, _CFG_SIZE@GOTPAGEOFF]
Lloh72:
	ldr	w8, [x8]
	stp	w8, w9, [x0, #56]
Lloh73:
	adrp	x8, _MAX_ASID@GOTPAGE
Lloh74:
	ldr	x8, [x8, _MAX_ASID@GOTPAGEOFF]
Lloh75:
	adrp	x9, _GOYA_ASYNC_EVENT_ID_SIZE@GOTPAGE
Lloh76:
	ldr	x9, [x9, _GOYA_ASYNC_EVENT_ID_SIZE@GOTPAGEOFF]
Lloh77:
	ldr	w8, [x8]
Lloh78:
	ldr	w9, [x9]
	stp	w9, w8, [x0, #48]
Lloh79:
	adrp	x8, _PLL_HIGH_DEFAULT@GOTPAGE
Lloh80:
	ldr	x8, [x8, _PLL_HIGH_DEFAULT@GOTPAGEOFF]
Lloh81:
	ldr	w8, [x8]
Lloh82:
	adrp	x9, _GOYA_CB_POOL_CB_CNT@GOTPAGE
Lloh83:
	ldr	x9, [x9, _GOYA_CB_POOL_CB_CNT@GOTPAGEOFF]
Lloh84:
	ldr	w9, [x9]
	stp	w9, w8, [x0, #40]
Lloh85:
	adrp	x8, _GOYA_CB_POOL_CB_SIZE@GOTPAGE
Lloh86:
	ldr	x8, [x8, _GOYA_CB_POOL_CB_SIZE@GOTPAGEOFF]
Lloh87:
	ldr	w8, [x8]
Lloh88:
	adrp	x9, _MAX_POWER_DEFAULT@GOTPAGE
Lloh89:
	ldr	x9, [x9, _MAX_POWER_DEFAULT@GOTPAGEOFF]
Lloh90:
	ldr	w9, [x9]
	stp	w9, w8, [x0, #32]
Lloh91:
	adrp	x8, _TPC_ENABLED_MASK@GOTPAGE
Lloh92:
	ldr	x8, [x8, _TPC_ENABLED_MASK@GOTPAGEOFF]
Lloh93:
	adrp	x9, _mmPCIE_DBI_BASE@GOTPAGE
Lloh94:
	ldr	x9, [x9, _mmPCIE_DBI_BASE@GOTPAGEOFF]
Lloh95:
	ldr	w8, [x8]
Lloh96:
	ldr	w9, [x9]
	stp	w9, w8, [x0, #24]
Lloh97:
	adrp	x8, _CFG_BASE@GOTPAGE
Lloh98:
	ldr	x8, [x8, _CFG_BASE@GOTPAGEOFF]
Lloh99:
	ldr	x8, [x8]
Lloh100:
	adrp	x9, _mmPCIE_AUX_DBI@GOTPAGE
Lloh101:
	ldr	x9, [x9, _mmPCIE_AUX_DBI@GOTPAGEOFF]
Lloh102:
	ldr	x9, [x9]
	add	x8, x9, x8
	str	x8, [x0, #16]
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh95
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh77
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.cfi_endproc
                                        ; -- End function
	.comm	_NUMBER_OF_EXT_HW_QUEUES,4,2    ; @NUMBER_OF_EXT_HW_QUEUES
	.comm	_QUEUE_TYPE_EXT,4,2             ; @QUEUE_TYPE_EXT
	.comm	_NUMBER_OF_CPU_HW_QUEUES,4,2    ; @NUMBER_OF_CPU_HW_QUEUES
	.comm	_QUEUE_TYPE_CPU,4,2             ; @QUEUE_TYPE_CPU
	.comm	_NUMBER_OF_INT_HW_QUEUES,4,2    ; @NUMBER_OF_INT_HW_QUEUES
	.comm	_QUEUE_TYPE_INT,4,2             ; @QUEUE_TYPE_INT
	.comm	_HL_MAX_QUEUES,4,2              ; @HL_MAX_QUEUES
	.comm	_QUEUE_TYPE_NA,4,2              ; @QUEUE_TYPE_NA
	.comm	_NUMBER_OF_CMPLT_QUEUES,4,2     ; @NUMBER_OF_CMPLT_QUEUES
	.comm	_DRAM_PHYS_BASE,8,3             ; @DRAM_PHYS_BASE
	.comm	_DRAM_PHYS_DEFAULT_SIZE,8,3     ; @DRAM_PHYS_DEFAULT_SIZE
	.comm	_DRAM_BASE_ADDR_USER,4,2        ; @DRAM_BASE_ADDR_USER
	.comm	_SRAM_BASE_ADDR,8,3             ; @SRAM_BASE_ADDR
	.comm	_SRAM_SIZE,8,3                  ; @SRAM_SIZE
	.comm	_SRAM_USER_BASE_OFFSET,8,3      ; @SRAM_USER_BASE_OFFSET
	.comm	_MMU_PAGE_TABLES_ADDR,4,2       ; @MMU_PAGE_TABLES_ADDR
	.comm	_MMU_DRAM_DEFAULT_PAGE_ADDR,4,2 ; @MMU_DRAM_DEFAULT_PAGE_ADDR
	.comm	_MMU_PAGE_TABLES_SIZE,4,2       ; @MMU_PAGE_TABLES_SIZE
	.comm	_HL_PTE_SIZE,4,2                ; @HL_PTE_SIZE
	.comm	_HOP_TABLE_SIZE,4,2             ; @HOP_TABLE_SIZE
	.comm	_HOP0_TABLES_TOTAL_SIZE,4,2     ; @HOP0_TABLES_TOTAL_SIZE
	.comm	_PAGE_SIZE_2MB,4,2              ; @PAGE_SIZE_2MB
	.comm	_VA_HOST_SPACE_START,4,2        ; @VA_HOST_SPACE_START
	.comm	_VA_HOST_SPACE_END,4,2          ; @VA_HOST_SPACE_END
	.comm	_VA_DDR_SPACE_START,4,2         ; @VA_DDR_SPACE_START
	.comm	_VA_DDR_SPACE_END,4,2           ; @VA_DDR_SPACE_END
	.comm	_CFG_SIZE,4,2                   ; @CFG_SIZE
	.comm	_MAX_ASID,4,2                   ; @MAX_ASID
	.comm	_GOYA_ASYNC_EVENT_ID_SIZE,4,2   ; @GOYA_ASYNC_EVENT_ID_SIZE
	.comm	_PLL_HIGH_DEFAULT,4,2           ; @PLL_HIGH_DEFAULT
	.comm	_GOYA_CB_POOL_CB_CNT,4,2        ; @GOYA_CB_POOL_CB_CNT
	.comm	_GOYA_CB_POOL_CB_SIZE,4,2       ; @GOYA_CB_POOL_CB_SIZE
	.comm	_MAX_POWER_DEFAULT,4,2          ; @MAX_POWER_DEFAULT
	.comm	_TPC_ENABLED_MASK,4,2           ; @TPC_ENABLED_MASK
	.comm	_mmPCIE_DBI_BASE,4,2            ; @mmPCIE_DBI_BASE
	.comm	_CFG_BASE,8,3                   ; @CFG_BASE
	.comm	_mmPCIE_AUX_DBI,8,3             ; @mmPCIE_AUX_DBI
.subsections_via_symbols
