	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function bnx2x_warpcore_link_reset
_bnx2x_warpcore_link_reset:             ## @bnx2x_warpcore_link_reset
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %rbx
	movq	(%rsi), %r15
	movq	%rsi, %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	_bnx2x_sfp_e3_set_transmitter
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_bnx2x_set_mdio_emac_per_phy
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	_bnx2x_set_aer_mmd
	movq	%r15, %rdi
	movq	%rbx, %rsi
	movl	$1, %edx
	callq	_bnx2x_warpcore_reset_lane
	movq	_MDIO_WC_DEVAD@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	movq	_MDIO_WC_REG_COMBO_IEEE0_MIICTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r15, %rdi
	movq	%rbx, %rsi
	movl	$49151, %r8d                    ## imm = 0xBFFF
	callq	_bnx2x_cl45_read_and_write
	movl	(%r13), %edx
	movq	_MDIO_WC_REG_IEEE0BLK_MIICNTL@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r15, %rdi
	movq	%rbx, %rsi
	movl	$65534, %r8d                    ## imm = 0xFFFE
	callq	_bnx2x_cl45_read_and_write
	movq	_MDIO_REG_BANK_AER_BLOCK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_MDIO_AER_BLOCK_AER_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r15, %rdi
	movq	%rbx, %rsi
	xorl	%r8d, %r8d
	callq	_CL22_WR_OVER_CL45
	movl	(%r13), %edx
	movq	_MDIO_WC_REG_XGXSBLK0_XGXSCONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r15, %rdi
	movq	%rbx, %rsi
	movl	$-17, %r8d
	callq	_bnx2x_cl45_read_and_write
	movl	(%r13), %edx
	movq	_MDIO_WC_REG_XGXSBLK1_LANECTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r15, %rdi
	movq	%rbx, %rsi
	movl	$65280, %r8d                    ## imm = 0xFF00
	callq	_bnx2x_cl45_read_and_write
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	_bnx2x_get_warpcore_lane
	movl	%eax, %r12d
	movl	(%r13), %edx
	movq	_MDIO_WC_REG_XGXSBLK1_LANECTRL0@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	leaq	-44(%rbp), %r8
	movq	%r15, %rdi
	movq	%rbx, %rsi
	callq	_bnx2x_cl45_read
	movl	$17, %r8d
	movl	%r12d, %ecx
	shll	%cl, %r8d
	orl	-44(%rbp), %r8d
	movl	%r8d, -44(%rbp)
	movq	_FLAGS_WC_DUAL_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rbx)
	je	LBB0_2
## %bb.1:
	movl	$34, %eax
	movl	%r12d, %ecx
	shll	%cl, %eax
	orl	%eax, %r8d
	movl	%r8d, -44(%rbp)
LBB0_2:
	movq	_MDIO_WC_DEVAD@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	movq	_MDIO_WC_REG_XGXSBLK1_LANECTRL0@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r15, %rdi
	movq	%rbx, %rsi
	callq	_bnx2x_cl45_write
	movl	(%r13), %edx
	movq	_MDIO_WC_REG_XGXSBLK1_LANECTRL1@GOTPCREL(%rip), %r13
	movl	(%r13), %ecx
	leaq	-44(%rbp), %r8
	movq	%r15, %rdi
	movq	%rbx, %rsi
	callq	_bnx2x_cl45_read
	addl	%r12d, %r12d
	movl	$771, %eax                      ## imm = 0x303
	movl	%r12d, %ecx
	shll	%cl, %eax
	notl	%eax
	andl	-44(%rbp), %eax
	movl	$257, %r8d                      ## imm = 0x101
	shll	%cl, %r8d
	orl	%eax, %r8d
	movl	%r8d, -44(%rbp)
	movq	_FLAGS_WC_DUAL_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%rbx)
	je	LBB0_4
## %bb.3:
	movl	$3084, %eax                     ## imm = 0xC0C
	movl	%r12d, %ecx
	shll	%cl, %eax
	movl	$1028, %edx                     ## imm = 0x404
	shll	%cl, %edx
	notl	%eax
	andl	%eax, %r8d
	orl	%edx, %r8d
	movl	%r8d, -44(%rbp)
LBB0_4:
	movq	_MDIO_WC_DEVAD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r13), %ecx
	movq	%r15, %rdi
	movq	%rbx, %rsi
	callq	_bnx2x_cl45_write
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	_bnx2x_set_aer_mmd
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MDIO_WC_DEVAD,4,2              ## @MDIO_WC_DEVAD
	.comm	_MDIO_WC_REG_COMBO_IEEE0_MIICTRL,4,2 ## @MDIO_WC_REG_COMBO_IEEE0_MIICTRL
	.comm	_MDIO_WC_REG_IEEE0BLK_MIICNTL,4,2 ## @MDIO_WC_REG_IEEE0BLK_MIICNTL
	.comm	_MDIO_REG_BANK_AER_BLOCK,4,2    ## @MDIO_REG_BANK_AER_BLOCK
	.comm	_MDIO_AER_BLOCK_AER_REG,4,2     ## @MDIO_AER_BLOCK_AER_REG
	.comm	_MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,4,2 ## @MDIO_WC_REG_XGXSBLK0_XGXSCONTROL
	.comm	_MDIO_WC_REG_XGXSBLK1_LANECTRL2,4,2 ## @MDIO_WC_REG_XGXSBLK1_LANECTRL2
	.comm	_MDIO_WC_REG_XGXSBLK1_LANECTRL0,4,2 ## @MDIO_WC_REG_XGXSBLK1_LANECTRL0
	.comm	_FLAGS_WC_DUAL_MODE,4,2         ## @FLAGS_WC_DUAL_MODE
	.comm	_MDIO_WC_REG_XGXSBLK1_LANECTRL1,4,2 ## @MDIO_WC_REG_XGXSBLK1_LANECTRL1
	.no_dead_strip	_bnx2x_warpcore_link_reset
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function bnx2x_warpcore_link_reset
_bnx2x_warpcore_link_reset:             ; @bnx2x_warpcore_link_reset
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x1
	mov	x19, x0
	ldr	x21, [x1]
	mov	x0, x1
	mov	x1, x19
	mov	w2, #0
	bl	_bnx2x_sfp_e3_set_transmitter
	mov	x0, x21
	mov	x1, x20
	bl	_bnx2x_set_mdio_emac_per_phy
	mov	x0, x20
	mov	x1, x19
	bl	_bnx2x_set_aer_mmd
	mov	x0, x21
	mov	x1, x19
	mov	w2, #1
	bl	_bnx2x_warpcore_reset_lane
Lloh0:
	adrp	x23, _MDIO_WC_DEVAD@GOTPAGE
Lloh1:
	ldr	x23, [x23, _MDIO_WC_DEVAD@GOTPAGEOFF]
	ldr	w2, [x23]
Lloh2:
	adrp	x8, _MDIO_WC_REG_COMBO_IEEE0_MIICTRL@GOTPAGE
Lloh3:
	ldr	x8, [x8, _MDIO_WC_REG_COMBO_IEEE0_MIICTRL@GOTPAGEOFF]
Lloh4:
	ldr	w3, [x8]
	mov	x0, x21
	mov	x1, x19
	mov	w4, #49151
	bl	_bnx2x_cl45_read_and_write
	ldr	w2, [x23]
Lloh5:
	adrp	x8, _MDIO_WC_REG_IEEE0BLK_MIICNTL@GOTPAGE
Lloh6:
	ldr	x8, [x8, _MDIO_WC_REG_IEEE0BLK_MIICNTL@GOTPAGEOFF]
Lloh7:
	ldr	w3, [x8]
	mov	x0, x21
	mov	x1, x19
	mov	w4, #65534
	bl	_bnx2x_cl45_read_and_write
Lloh8:
	adrp	x8, _MDIO_REG_BANK_AER_BLOCK@GOTPAGE
Lloh9:
	ldr	x8, [x8, _MDIO_REG_BANK_AER_BLOCK@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
Lloh11:
	adrp	x8, _MDIO_AER_BLOCK_AER_REG@GOTPAGE
Lloh12:
	ldr	x8, [x8, _MDIO_AER_BLOCK_AER_REG@GOTPAGEOFF]
Lloh13:
	ldr	w3, [x8]
	mov	x0, x21
	mov	x1, x19
	mov	w4, #0
	bl	_CL22_WR_OVER_CL45
	ldr	w2, [x23]
Lloh14:
	adrp	x8, _MDIO_WC_REG_XGXSBLK0_XGXSCONTROL@GOTPAGE
Lloh15:
	ldr	x8, [x8, _MDIO_WC_REG_XGXSBLK0_XGXSCONTROL@GOTPAGEOFF]
Lloh16:
	ldr	w3, [x8]
	mov	x0, x21
	mov	x1, x19
	mov	w4, #-17
	bl	_bnx2x_cl45_read_and_write
	ldr	w2, [x23]
Lloh17:
	adrp	x8, _MDIO_WC_REG_XGXSBLK1_LANECTRL2@GOTPAGE
Lloh18:
	ldr	x8, [x8, _MDIO_WC_REG_XGXSBLK1_LANECTRL2@GOTPAGEOFF]
Lloh19:
	ldr	w3, [x8]
	mov	x0, x21
	mov	x1, x19
	mov	w4, #65280
	bl	_bnx2x_cl45_read_and_write
	mov	x0, x19
	mov	x1, x20
	bl	_bnx2x_get_warpcore_lane
	mov	x22, x0
	ldr	w2, [x23]
Lloh20:
	adrp	x25, _MDIO_WC_REG_XGXSBLK1_LANECTRL0@GOTPAGE
Lloh21:
	ldr	x25, [x25, _MDIO_WC_REG_XGXSBLK1_LANECTRL0@GOTPAGEOFF]
	ldr	w3, [x25]
	add	x4, sp, #12
	mov	x0, x21
	mov	x1, x19
	bl	_bnx2x_cl45_read
	mov	w8, #17
	lsl	w8, w8, w22
	ldr	w9, [sp, #12]
	orr	w4, w9, w8
	str	w4, [sp, #12]
	ldr	w8, [x19]
Lloh22:
	adrp	x24, _FLAGS_WC_DUAL_MODE@GOTPAGE
Lloh23:
	ldr	x24, [x24, _FLAGS_WC_DUAL_MODE@GOTPAGEOFF]
	ldr	w9, [x24]
	tst	w9, w8
	b.eq	LBB0_2
; %bb.1:
	mov	w8, #34
	lsl	w8, w8, w22
	orr	w4, w4, w8
	str	w4, [sp, #12]
LBB0_2:
	ldr	w2, [x23]
	ldr	w3, [x25]
	mov	x0, x21
	mov	x1, x19
	bl	_bnx2x_cl45_write
	ldr	w2, [x23]
Lloh24:
	adrp	x25, _MDIO_WC_REG_XGXSBLK1_LANECTRL1@GOTPAGE
Lloh25:
	ldr	x25, [x25, _MDIO_WC_REG_XGXSBLK1_LANECTRL1@GOTPAGEOFF]
	ldr	w3, [x25]
	add	x4, sp, #12
	mov	x0, x21
	mov	x1, x19
	bl	_bnx2x_cl45_read
	lsl	w8, w22, #1
	mov	w9, #771
	lsl	w9, w9, w8
	ldr	w10, [sp, #12]
	bic	w9, w10, w9
	mov	w10, #257
	lsl	w10, w10, w8
	orr	w4, w9, w10
	str	w4, [sp, #12]
	ldr	w9, [x19]
	ldr	w10, [x24]
	tst	w10, w9
	b.eq	LBB0_4
; %bb.3:
	mov	w9, #3084
	lsl	w9, w9, w8
	bic	w9, w4, w9
	mov	w10, #1028
	lsl	w8, w10, w8
	orr	w4, w9, w8
	str	w4, [sp, #12]
LBB0_4:
	ldr	w2, [x23]
	ldr	w3, [x25]
	mov	x0, x21
	mov	x1, x19
	bl	_bnx2x_cl45_write
	mov	x0, x20
	mov	x1, x19
	bl	_bnx2x_set_aer_mmd
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh24, Lloh25
	.cfi_endproc
                                        ; -- End function
	.comm	_MDIO_WC_DEVAD,4,2              ; @MDIO_WC_DEVAD
	.comm	_MDIO_WC_REG_COMBO_IEEE0_MIICTRL,4,2 ; @MDIO_WC_REG_COMBO_IEEE0_MIICTRL
	.comm	_MDIO_WC_REG_IEEE0BLK_MIICNTL,4,2 ; @MDIO_WC_REG_IEEE0BLK_MIICNTL
	.comm	_MDIO_REG_BANK_AER_BLOCK,4,2    ; @MDIO_REG_BANK_AER_BLOCK
	.comm	_MDIO_AER_BLOCK_AER_REG,4,2     ; @MDIO_AER_BLOCK_AER_REG
	.comm	_MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,4,2 ; @MDIO_WC_REG_XGXSBLK0_XGXSCONTROL
	.comm	_MDIO_WC_REG_XGXSBLK1_LANECTRL2,4,2 ; @MDIO_WC_REG_XGXSBLK1_LANECTRL2
	.comm	_MDIO_WC_REG_XGXSBLK1_LANECTRL0,4,2 ; @MDIO_WC_REG_XGXSBLK1_LANECTRL0
	.comm	_FLAGS_WC_DUAL_MODE,4,2         ; @FLAGS_WC_DUAL_MODE
	.comm	_MDIO_WC_REG_XGXSBLK1_LANECTRL1,4,2 ; @MDIO_WC_REG_XGXSBLK1_LANECTRL1
	.no_dead_strip	_bnx2x_warpcore_link_reset
.subsections_via_symbols
