	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rtl8411_do_switch_output_voltage
_rtl8411_do_switch_output_voltage:      ## @rtl8411_do_switch_output_voltage
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %r12d
	movl	%edx, %r14d
	movq	_BPP_REG_TUNED18@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%r14d, %ecx
	shll	%cl, %ebx
	movq	_BPP_PAD_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	%rdi, %r15
	movq	_OUTPUT_3V3@GOTPCREL(%rip), %rax
	cmpq	%rsi, (%rax)
	jne	LBB0_3
## %bb.1:
	movq	_SD30_DRIVE_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	(%r15), %rcx
	movl	$7, %edx
	movq	%r15, %rdi
	callq	_rtsx_pci_write_register
	testl	%eax, %eax
	js	LBB0_8
## %bb.2:
	movq	_BPP_ASIC_3V3@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%r14d, %ecx
	shll	%cl, %eax
	movq	_BPP_PAD_3V3@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r12d
	jmp	LBB0_6
LBB0_3:
	movq	_OUTPUT_1V8@GOTPCREL(%rip), %rax
	cmpq	%rsi, (%rax)
	jne	LBB0_7
## %bb.4:
	movq	_SD30_DRIVE_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	8(%r15), %rcx
	movl	$7, %edx
	movq	%r15, %rdi
	callq	_rtsx_pci_write_register
	testl	%eax, %eax
	js	LBB0_8
## %bb.5:
	movl	%r14d, %ecx
	shll	%cl, %r12d
	movq	_BPP_PAD_1V8@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_6:
	orl	%eax, %r12d
	movslq	%ebx, %rdx
	movslq	%r12d, %rcx
	movq	_LDO_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_rtsx_pci_write_register        ## TAILCALL
LBB0_7:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_8:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_BPP_REG_TUNED18,4,2            ## @BPP_REG_TUNED18
	.comm	_BPP_PAD_MASK,4,2               ## @BPP_PAD_MASK
	.comm	_OUTPUT_3V3,8,3                 ## @OUTPUT_3V3
	.comm	_SD30_DRIVE_SEL,4,2             ## @SD30_DRIVE_SEL
	.comm	_BPP_ASIC_3V3,4,2               ## @BPP_ASIC_3V3
	.comm	_BPP_PAD_3V3,4,2                ## @BPP_PAD_3V3
	.comm	_OUTPUT_1V8,8,3                 ## @OUTPUT_1V8
	.comm	_BPP_PAD_1V8,4,2                ## @BPP_PAD_1V8
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_LDO_CTL,4,2                    ## @LDO_CTL
	.no_dead_strip	_rtl8411_do_switch_output_voltage
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rtl8411_do_switch_output_voltage
_rtl8411_do_switch_output_voltage:      ; @rtl8411_do_switch_output_voltage
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x2
	mov	x19, x0
Lloh0:
	adrp	x8, _BPP_REG_TUNED18@GOTPAGE
Lloh1:
	ldr	x8, [x8, _BPP_REG_TUNED18@GOTPAGEOFF]
Lloh2:
	adrp	x9, _BPP_PAD_MASK@GOTPAGE
Lloh3:
	ldr	x9, [x9, _BPP_PAD_MASK@GOTPAGEOFF]
Lloh4:
	ldr	w23, [x8]
Lloh5:
	ldr	w22, [x9]
Lloh6:
	adrp	x8, _OUTPUT_3V3@GOTPAGE
Lloh7:
	ldr	x8, [x8, _OUTPUT_3V3@GOTPAGEOFF]
Lloh8:
	ldr	x8, [x8]
	cmp	x8, x1
	b.ne	LBB0_3
; %bb.1:
Lloh9:
	adrp	x8, _SD30_DRIVE_SEL@GOTPAGE
Lloh10:
	ldr	x8, [x8, _SD30_DRIVE_SEL@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	ldr	x3, [x19]
	mov	x0, x19
	mov	w2, #7
	bl	_rtsx_pci_write_register
	tbnz	w0, #31, LBB0_8
; %bb.2:
Lloh12:
	adrp	x8, _BPP_ASIC_3V3@GOTPAGE
Lloh13:
	ldr	x8, [x8, _BPP_ASIC_3V3@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	lsl	w9, w8, w20
Lloh15:
	adrp	x8, _BPP_PAD_3V3@GOTPAGE
Lloh16:
	ldr	x8, [x8, _BPP_PAD_3V3@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	b	LBB0_6
LBB0_3:
Lloh18:
	adrp	x8, _OUTPUT_1V8@GOTPAGE
Lloh19:
	ldr	x8, [x8, _OUTPUT_1V8@GOTPAGEOFF]
Lloh20:
	ldr	x8, [x8]
	cmp	x8, x1
	b.ne	LBB0_7
; %bb.4:
	mov	x21, x3
Lloh21:
	adrp	x8, _SD30_DRIVE_SEL@GOTPAGE
Lloh22:
	ldr	x8, [x8, _SD30_DRIVE_SEL@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	ldr	x3, [x19, #8]
	mov	x0, x19
	mov	w2, #7
	bl	_rtsx_pci_write_register
	tbnz	w0, #31, LBB0_8
; %bb.5:
	lsl	w8, w21, w20
Lloh24:
	adrp	x9, _BPP_PAD_1V8@GOTPAGE
Lloh25:
	ldr	x9, [x9, _BPP_PAD_1V8@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
LBB0_6:
	lsl	w10, w23, w20
	orr	w10, w10, w22
	sxtw	x2, w10
	orr	w8, w9, w8
Lloh27:
	adrp	x9, _LDO_CTL@GOTPAGE
Lloh28:
	ldr	x9, [x9, _LDO_CTL@GOTPAGEOFF]
	sxtw	x3, w8
Lloh29:
	ldr	w1, [x9]
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_rtsx_pci_write_register
LBB0_7:
Lloh30:
	adrp	x8, _EINVAL@GOTPAGE
Lloh31:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_8:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh4
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.cfi_endproc
                                        ; -- End function
	.comm	_BPP_REG_TUNED18,4,2            ; @BPP_REG_TUNED18
	.comm	_BPP_PAD_MASK,4,2               ; @BPP_PAD_MASK
	.comm	_OUTPUT_3V3,8,3                 ; @OUTPUT_3V3
	.comm	_SD30_DRIVE_SEL,4,2             ; @SD30_DRIVE_SEL
	.comm	_BPP_ASIC_3V3,4,2               ; @BPP_ASIC_3V3
	.comm	_BPP_PAD_3V3,4,2                ; @BPP_PAD_3V3
	.comm	_OUTPUT_1V8,8,3                 ; @OUTPUT_1V8
	.comm	_BPP_PAD_1V8,4,2                ; @BPP_PAD_1V8
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_LDO_CTL,4,2                    ; @LDO_CTL
	.no_dead_strip	_rtl8411_do_switch_output_voltage
.subsections_via_symbols
