	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function genwqe_pci_fundamental_reset
_genwqe_pci_fundamental_reset:          ## @genwqe_pci_fundamental_reset
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	callq	_pci_cfg_access_lock
	movq	%rbx, %rdi
	callq	_pci_save_state
	movq	_pcie_warm_reset@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_pci_set_pcie_reset_state
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	LBB0_2
## %bb.1:
	movl	$250, %edi
	callq	_msleep
	movq	_pcie_deassert_reset@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_pci_set_pcie_reset_state
	movl	$2000, %edi                     ## imm = 0x7D0
	callq	_msleep
LBB0_2:
	movq	%rbx, %rdi
	callq	_pci_restore_state
	movq	%rbx, %rdi
	callq	_pci_cfg_access_unlock
	movl	%r14d, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_pcie_warm_reset,4,2            ## @pcie_warm_reset
	.comm	_pcie_deassert_reset,4,2        ## @pcie_deassert_reset
	.no_dead_strip	_genwqe_pci_fundamental_reset
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function genwqe_pci_fundamental_reset
_genwqe_pci_fundamental_reset:          ; @genwqe_pci_fundamental_reset
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_pci_cfg_access_lock
	mov	x0, x19
	bl	_pci_save_state
Lloh0:
	adrp	x8, _pcie_warm_reset@GOTPAGE
Lloh1:
	ldr	x8, [x8, _pcie_warm_reset@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_pci_set_pcie_reset_state
	mov	x20, x0
	cbnz	w0, LBB0_2
; %bb.1:
	mov	w0, #250
	bl	_msleep
Lloh3:
	adrp	x8, _pcie_deassert_reset@GOTPAGE
Lloh4:
	ldr	x8, [x8, _pcie_deassert_reset@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_pci_set_pcie_reset_state
	mov	w0, #2000
	bl	_msleep
LBB0_2:
	mov	x0, x19
	bl	_pci_restore_state
	mov	x0, x19
	bl	_pci_cfg_access_unlock
	mov	x0, x20
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_pcie_warm_reset,4,2            ; @pcie_warm_reset
	.comm	_pcie_deassert_reset,4,2        ; @pcie_deassert_reset
	.no_dead_strip	_genwqe_pci_fundamental_reset
.subsections_via_symbols
