	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function amd_config_tuning_phase
_amd_config_tuning_phase:               ## @amd_config_tuning_phase
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %ebx
	movq	%rdi, %r14
	movq	_AMD_SD_AUTO_PATTERN@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	leaq	-28(%rbp), %rdx
	callq	_pci_read_config_dword
	movq	_AMD_BIT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	-28(%rbp), %eax
	movq	_AMD_AUTO_TUNE_SEL@GOTPCREL(%rip), %rcx
	addl	%ebx, %ebx
	orl	%eax, %ebx
	orl	(%rcx), %ebx
	movl	%ebx, -28(%rbp)
	movl	(%r15), %esi
	movq	%r14, %rdi
	movl	%ebx, %edx
	callq	_pci_write_config_dword
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AMD_SD_AUTO_PATTERN,4,2        ## @AMD_SD_AUTO_PATTERN
	.comm	_AMD_BIT_MASK,4,2               ## @AMD_BIT_MASK
	.comm	_AMD_AUTO_TUNE_SEL,4,2          ## @AMD_AUTO_TUNE_SEL
	.no_dead_strip	_amd_config_tuning_phase
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function amd_config_tuning_phase
_amd_config_tuning_phase:               ; @amd_config_tuning_phase
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x1
	mov	x20, x0
Lloh0:
	adrp	x21, _AMD_SD_AUTO_PATTERN@GOTPAGE
Lloh1:
	ldr	x21, [x21, _AMD_SD_AUTO_PATTERN@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x2, sp, #12
	bl	_pci_read_config_dword
Lloh2:
	adrp	x8, _AMD_BIT_MASK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _AMD_BIT_MASK@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
Lloh5:
	adrp	x10, _AMD_AUTO_TUNE_SEL@GOTPAGE
Lloh6:
	ldr	x10, [x10, _AMD_AUTO_TUNE_SEL@GOTPAGEOFF]
	bic	w8, w9, w8
Lloh7:
	ldr	w9, [x10]
	orr	w8, w8, w19, lsl #1
	orr	w2, w8, w9
	str	w2, [sp, #12]
	ldr	w1, [x21]
	mov	x0, x20
	bl	_pci_write_config_dword
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_AMD_SD_AUTO_PATTERN,4,2        ; @AMD_SD_AUTO_PATTERN
	.comm	_AMD_BIT_MASK,4,2               ; @AMD_BIT_MASK
	.comm	_AMD_AUTO_TUNE_SEL,4,2          ; @AMD_AUTO_TUNE_SEL
	.no_dead_strip	_amd_config_tuning_phase
.subsections_via_symbols
