	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function cobalt_setup_pci
_cobalt_setup_pci:                      ## @cobalt_setup_pci
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r15
	movq	%rdi, %r14
	leaq	L_.str(%rip), %rsi
	movl	$1, %edi
	callq	_cobalt_dbg
	movq	%r15, %rdi
	callq	_pci_enable_device
	testl	%eax, %eax
	je	LBB0_2
## %bb.1:
	movl	%eax, %ebx
	leaq	L_.str.1(%rip), %rdi
	xorl	%eax, %eax
	callq	_cobalt_err
	jmp	LBB0_24
LBB0_2:
	movq	%r15, %rdi
	callq	_pci_set_master
	movq	_PCI_CLASS_REVISION@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	32(%r14), %rdx
	movq	%r15, %rdi
	callq	_pci_read_config_byte
	movq	_PCI_DEVICE_ID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movq	%r14, %rdx
	callq	_pci_read_config_word
	cmpl	$128, (%r14)
	leaq	L_.str.2(%rip), %rax
	leaq	L_.str.3(%rip), %rdi
	cmoveq	%rax, %rdi
	callq	_cobalt_info
	movq	%r14, %rdi
	callq	_pcie_link_get_lanes
	cmpl	$8, %eax
	je	LBB0_7
## %bb.3:
	movq	%r14, %rdi
	callq	_pcie_link_get_lanes
	leaq	L_.str.4(%rip), %rdi
	movl	%eax, %esi
	callq	_cobalt_warn
	movq	%r14, %rdi
	callq	_pcie_bus_link_get_lanes
	cmpl	$7, %eax
	jg	LBB0_5
## %bb.4:
	movq	%r14, %rdi
	callq	_pcie_bus_link_get_lanes
	leaq	L_.str.5(%rip), %rdi
	movl	%eax, %esi
	callq	_cobalt_warn
LBB0_5:
	movq	%r14, %rdi
	callq	_pcie_link_get_lanes
	movl	%eax, %ebx
	movq	%r14, %rdi
	callq	_pcie_bus_link_get_lanes
	cmpl	%eax, %ebx
	jne	LBB0_6
LBB0_7:
	movl	$64, %edi
	callq	_DMA_BIT_MASK
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_pci_set_dma_mask
	testl	%eax, %eax
	je	LBB0_11
## %bb.8:
	movl	$32, %edi
	callq	_DMA_BIT_MASK
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_pci_set_dma_mask
	testl	%eax, %eax
	je	LBB0_11
## %bb.9:
	movl	%eax, %ebx
	leaq	L_.str.7(%rip), %rdi
	jmp	LBB0_10
LBB0_11:
	leaq	L_.str.8(%rip), %rsi
	movq	%r15, %rdi
	callq	_pci_request_regions
	testl	%eax, %eax
	je	LBB0_13
## %bb.12:
	movl	%eax, %ebx
	leaq	L_.str.9(%rip), %rdi
LBB0_10:
	xorl	%eax, %eax
	callq	_cobalt_err
	jmp	LBB0_23
LBB0_6:
	leaq	L_.str.6(%rip), %rdi
	xorl	%ebx, %ebx
	xorl	%eax, %eax
	callq	_cobalt_err
	movq	_EIO@GOTPCREL(%rip), %rax
	subl	(%rax), %ebx
	jmp	LBB0_23
LBB0_13:
	movq	%r14, %rdi
	callq	_cobalt_pcie_status_show
	movq	%r15, %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_pci_iomap
	movq	%rax, 24(%r14)
	movq	%r15, %rdi
	movl	$1, %esi
	xorl	%edx, %edx
	callq	_pci_iomap
	movq	%rax, 16(%r14)
	testq	%rax, %rax
	jne	LBB0_15
## %bb.14:
	movq	%r15, %rdi
	movl	$2, %esi
	xorl	%edx, %edx
	callq	_pci_iomap
	movq	%rax, 16(%r14)
	leaq	L_.str.10(%rip), %rdi
	callq	_cobalt_info
LBB0_15:
	cmpq	$0, 24(%r14)
	je	LBB0_17
## %bb.16:
	cmpq	$0, 16(%r14)
	je	LBB0_17
## %bb.18:
	movq	_COBALT_SYS_CTRL_BASE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_cobalt_read_bar1
	movl	(%rbx), %esi
	andl	$-3841, %eax                    ## imm = 0xF0FF
	movq	%r14, %rdi
	movl	%eax, %edx
	callq	_cobalt_write_bar1
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_cobalt_set_interrupt
	movq	_PCI_IRQ_MSI@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r15, %rdi
	movl	$1, %esi
	movl	$1, %edx
	callq	_pci_alloc_irq_vectors
	testl	%eax, %eax
	jle	LBB0_19
## %bb.20:
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	_msi_config_show
	movl	(%r15), %edi
	movq	_cobalt_irq_handler@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_IRQF_SHARED@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	8(%r14), %ecx
	movq	%r14, %r8
	callq	_request_irq
	testq	%rax, %rax
	je	LBB0_25
## %bb.21:
	movl	(%r15), %esi
	leaq	L_.str.12(%rip), %rdi
	xorl	%eax, %eax
	callq	_cobalt_err
	movq	_EIO@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	%r15, %rdi
	callq	_pci_disable_msi
	jmp	LBB0_22
LBB0_19:
	leaq	L_.str.11(%rip), %rdi
	xorl	%eax, %eax
	callq	_cobalt_err
LBB0_17:
	movq	_EIO@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
LBB0_22:
	negl	%ebx
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	_cobalt_pci_iounmap
	movq	%r15, %rdi
	callq	_pci_release_regions
LBB0_23:
	movl	4(%r14), %edi
	callq	_pci_disable_device
LBB0_24:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_25:
	movq	%r14, %rdi
	callq	_omni_sg_dma_init
	xorl	%ebx, %ebx
	jmp	LBB0_24
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"enabling pci device\n"

L_.str.1:                               ## @.str.1
	.asciz	"can't enable device\n"

	.comm	_PCI_CLASS_REVISION,4,2         ## @PCI_CLASS_REVISION
	.comm	_PCI_DEVICE_ID,4,2              ## @PCI_DEVICE_ID
L_.str.2:                               ## @.str.2
	.asciz	"PCI Express interface from Omnitek\n"

L_.str.3:                               ## @.str.3
	.asciz	"PCI Express interface provider is unknown!\n"

L_.str.4:                               ## @.str.4
	.asciz	"PCI Express link width is %d lanes.\n"

L_.str.5:                               ## @.str.5
	.asciz	"The current slot only supports %d lanes, for best performance 8 are needed\n"

L_.str.6:                               ## @.str.6
	.asciz	"The card is most likely not seated correctly in the PCIe slot\n"

	.comm	_EIO,4,2                        ## @EIO
L_.str.7:                               ## @.str.7
	.asciz	"no suitable DMA available\n"

L_.str.8:                               ## @.str.8
	.asciz	"cobalt"

L_.str.9:                               ## @.str.9
	.asciz	"error requesting regions\n"

L_.str.10:                              ## @.str.10
	.asciz	"64-bit BAR\n"

	.comm	_COBALT_SYS_CTRL_BASE,4,2       ## @COBALT_SYS_CTRL_BASE
	.comm	_PCI_IRQ_MSI,4,2                ## @PCI_IRQ_MSI
L_.str.11:                              ## @.str.11
	.asciz	"Could not enable MSI\n"

	.comm	_cobalt_irq_handler,4,2         ## @cobalt_irq_handler
	.comm	_IRQF_SHARED,4,2                ## @IRQF_SHARED
L_.str.12:                              ## @.str.12
	.asciz	"Failed to register irq %d\n"

	.no_dead_strip	_cobalt_setup_pci
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cobalt_setup_pci
_cobalt_setup_pci:                      ; @cobalt_setup_pci
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	mov	w0, #1
	bl	_cobalt_dbg
	mov	x0, x20
	bl	_pci_enable_device
	cbz	w0, LBB0_2
; %bb.1:
	mov	x21, x0
Lloh2:
	adrp	x0, l_.str.1@PAGE
Lloh3:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_cobalt_err
	b	LBB0_23
LBB0_2:
	mov	x0, x20
	bl	_pci_set_master
Lloh4:
	adrp	x8, _PCI_CLASS_REVISION@GOTPAGE
Lloh5:
	ldr	x8, [x8, _PCI_CLASS_REVISION@GOTPAGEOFF]
Lloh6:
	ldr	w1, [x8]
	add	x2, x19, #32
	mov	x0, x20
	bl	_pci_read_config_byte
Lloh7:
	adrp	x8, _PCI_DEVICE_ID@GOTPAGE
Lloh8:
	ldr	x8, [x8, _PCI_DEVICE_ID@GOTPAGEOFF]
Lloh9:
	ldr	w1, [x8]
	mov	x0, x20
	mov	x2, x19
	bl	_pci_read_config_word
	ldr	w8, [x19]
Lloh10:
	adrp	x9, l_.str.3@PAGE
Lloh11:
	add	x9, x9, l_.str.3@PAGEOFF
Lloh12:
	adrp	x10, l_.str.2@PAGE
Lloh13:
	add	x10, x10, l_.str.2@PAGEOFF
	cmp	w8, #128
	csel	x0, x10, x9, eq
	bl	_cobalt_info
	mov	x0, x19
	bl	_pcie_link_get_lanes
	cmp	w0, #8
	b.eq	LBB0_6
; %bb.3:
	mov	x0, x19
	bl	_pcie_link_get_lanes
	mov	x1, x0
Lloh14:
	adrp	x0, l_.str.4@PAGE
Lloh15:
	add	x0, x0, l_.str.4@PAGEOFF
	bl	_cobalt_warn
	mov	x0, x19
	bl	_pcie_bus_link_get_lanes
	cmp	w0, #7
	b.gt	LBB0_5
; %bb.4:
	mov	x0, x19
	bl	_pcie_bus_link_get_lanes
	mov	x1, x0
Lloh16:
	adrp	x0, l_.str.5@PAGE
Lloh17:
	add	x0, x0, l_.str.5@PAGEOFF
	bl	_cobalt_warn
LBB0_5:
	mov	x0, x19
	bl	_pcie_link_get_lanes
	mov	x21, x0
	mov	x0, x19
	bl	_pcie_bus_link_get_lanes
	cmp	w21, w0
	b.ne	LBB0_11
LBB0_6:
	mov	w0, #64
	bl	_DMA_BIT_MASK
	mov	x1, x0
	mov	x0, x20
	bl	_pci_set_dma_mask
	cbz	w0, LBB0_9
; %bb.7:
	mov	w0, #32
	bl	_DMA_BIT_MASK
	mov	x1, x0
	mov	x0, x20
	bl	_pci_set_dma_mask
	cbz	w0, LBB0_9
; %bb.8:
	mov	x21, x0
Lloh18:
	adrp	x0, l_.str.7@PAGE
Lloh19:
	add	x0, x0, l_.str.7@PAGEOFF
	bl	_cobalt_err
	b	LBB0_22
LBB0_9:
Lloh20:
	adrp	x1, l_.str.8@PAGE
Lloh21:
	add	x1, x1, l_.str.8@PAGEOFF
	mov	x0, x20
	bl	_pci_request_regions
	cbz	w0, LBB0_12
; %bb.10:
	mov	x21, x0
Lloh22:
	adrp	x0, l_.str.9@PAGE
Lloh23:
	add	x0, x0, l_.str.9@PAGEOFF
	bl	_cobalt_err
	b	LBB0_22
LBB0_11:
Lloh24:
	adrp	x0, l_.str.6@PAGE
Lloh25:
	add	x0, x0, l_.str.6@PAGEOFF
	bl	_cobalt_err
Lloh26:
	adrp	x8, _EIO@GOTPAGE
Lloh27:
	ldr	x8, [x8, _EIO@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
	neg	w21, w8
	b	LBB0_22
LBB0_12:
	mov	x0, x19
	bl	_cobalt_pcie_status_show
	mov	x0, x20
	mov	w1, #0
	mov	w2, #0
	bl	_pci_iomap
	str	x0, [x19, #24]
	mov	x0, x20
	mov	w1, #1
	mov	w2, #0
	bl	_pci_iomap
	str	x0, [x19, #16]
	cbnz	x0, LBB0_14
; %bb.13:
	mov	x0, x20
	mov	w1, #2
	mov	w2, #0
	bl	_pci_iomap
	str	x0, [x19, #16]
Lloh29:
	adrp	x0, l_.str.10@PAGE
Lloh30:
	add	x0, x0, l_.str.10@PAGEOFF
	bl	_cobalt_info
LBB0_14:
	ldr	x8, [x19, #24]
	cbz	x8, LBB0_20
; %bb.15:
	ldr	x8, [x19, #16]
	cbz	x8, LBB0_20
; %bb.16:
Lloh31:
	adrp	x21, _COBALT_SYS_CTRL_BASE@GOTPAGE
Lloh32:
	ldr	x21, [x21, _COBALT_SYS_CTRL_BASE@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_cobalt_read_bar1
	ldr	w1, [x21]
	and	w2, w0, #0xfffff0ff
	mov	x0, x19
	bl	_cobalt_write_bar1
	mov	x0, x19
	mov	w1, #0
	bl	_cobalt_set_interrupt
Lloh33:
	adrp	x8, _PCI_IRQ_MSI@GOTPAGE
Lloh34:
	ldr	x8, [x8, _PCI_IRQ_MSI@GOTPAGEOFF]
Lloh35:
	ldr	w3, [x8]
	mov	x0, x20
	mov	w1, #1
	mov	w2, #1
	bl	_pci_alloc_irq_vectors
	cmp	w0, #0
	b.le	LBB0_19
; %bb.17:
	mov	x0, x19
	mov	x1, x20
	bl	_msi_config_show
Lloh36:
	adrp	x8, _cobalt_irq_handler@GOTPAGE
Lloh37:
	ldr	x8, [x8, _cobalt_irq_handler@GOTPAGEOFF]
	ldr	w0, [x20]
Lloh38:
	ldr	w1, [x8]
Lloh39:
	adrp	x8, _IRQF_SHARED@GOTPAGE
Lloh40:
	ldr	x8, [x8, _IRQF_SHARED@GOTPAGEOFF]
Lloh41:
	ldr	w2, [x8]
	ldr	w3, [x19, #8]
	mov	x4, x19
	bl	_request_irq
	cbz	x0, LBB0_24
; %bb.18:
	ldr	w8, [x20]
	str	x8, [sp]
Lloh42:
	adrp	x0, l_.str.12@PAGE
Lloh43:
	add	x0, x0, l_.str.12@PAGEOFF
	bl	_cobalt_err
Lloh44:
	adrp	x8, _EIO@GOTPAGE
Lloh45:
	ldr	x8, [x8, _EIO@GOTPAGEOFF]
Lloh46:
	ldr	w21, [x8]
	mov	x0, x20
	bl	_pci_disable_msi
	b	LBB0_21
LBB0_19:
Lloh47:
	adrp	x0, l_.str.11@PAGE
Lloh48:
	add	x0, x0, l_.str.11@PAGEOFF
	bl	_cobalt_err
LBB0_20:
Lloh49:
	adrp	x8, _EIO@GOTPAGE
Lloh50:
	ldr	x8, [x8, _EIO@GOTPAGEOFF]
Lloh51:
	ldr	w21, [x8]
LBB0_21:
	neg	w21, w21
	mov	x0, x19
	mov	x1, x20
	bl	_cobalt_pci_iounmap
	mov	x0, x20
	bl	_pci_release_regions
LBB0_22:
	ldr	w0, [x19, #4]
	bl	_pci_disable_device
LBB0_23:
	mov	x0, x21
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
LBB0_24:
	mov	x0, x19
	bl	_omni_sg_dma_init
	mov	w21, #0
	b	LBB0_23
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpAdd	Lloh12, Lloh13
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpAdd	Lloh14, Lloh15
	.loh AdrpAdd	Lloh16, Lloh17
	.loh AdrpAdd	Lloh18, Lloh19
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpAdd	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpAdd	Lloh24, Lloh25
	.loh AdrpAdd	Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpAdd	Lloh42, Lloh43
	.loh AdrpAdd	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"enabling pci device\n"

l_.str.1:                               ; @.str.1
	.asciz	"can't enable device\n"

	.comm	_PCI_CLASS_REVISION,4,2         ; @PCI_CLASS_REVISION
	.comm	_PCI_DEVICE_ID,4,2              ; @PCI_DEVICE_ID
l_.str.2:                               ; @.str.2
	.asciz	"PCI Express interface from Omnitek\n"

l_.str.3:                               ; @.str.3
	.asciz	"PCI Express interface provider is unknown!\n"

l_.str.4:                               ; @.str.4
	.asciz	"PCI Express link width is %d lanes.\n"

l_.str.5:                               ; @.str.5
	.asciz	"The current slot only supports %d lanes, for best performance 8 are needed\n"

l_.str.6:                               ; @.str.6
	.asciz	"The card is most likely not seated correctly in the PCIe slot\n"

	.comm	_EIO,4,2                        ; @EIO
l_.str.7:                               ; @.str.7
	.asciz	"no suitable DMA available\n"

l_.str.8:                               ; @.str.8
	.asciz	"cobalt"

l_.str.9:                               ; @.str.9
	.asciz	"error requesting regions\n"

l_.str.10:                              ; @.str.10
	.asciz	"64-bit BAR\n"

	.comm	_COBALT_SYS_CTRL_BASE,4,2       ; @COBALT_SYS_CTRL_BASE
	.comm	_PCI_IRQ_MSI,4,2                ; @PCI_IRQ_MSI
l_.str.11:                              ; @.str.11
	.asciz	"Could not enable MSI\n"

	.comm	_cobalt_irq_handler,4,2         ; @cobalt_irq_handler
	.comm	_IRQF_SHARED,4,2                ; @IRQF_SHARED
l_.str.12:                              ; @.str.12
	.asciz	"Failed to register irq %d\n"

	.no_dead_strip	_cobalt_setup_pci
.subsections_via_symbols
