	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function xenon_execute_tuning
_xenon_execute_tuning:                  ## @xenon_execute_tuning
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movl	%esi, %r14d
	movq	%rdi, %rbx
	callq	_mmc_priv
	movq	(%rax), %rcx
	movq	_MMC_TIMING_UHS_DDR50@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	je	LBB0_5
## %bb.1:
	movq	_MMC_TIMING_MMC_DDR52@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	je	LBB0_5
## %bb.2:
	movq	8(%rax), %rcx
	movq	_SDHCI_TUNING_MODE_1@GOTPCREL(%rip), %rdx
	cmpq	(%rdx), %rcx
	je	LBB0_4
## %bb.3:
	movq	%rax, %rdi
	callq	_xenon_retune_setup
LBB0_4:
	movq	%rbx, %rdi
	movl	%r14d, %esi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_sdhci_execute_tuning           ## TAILCALL
LBB0_5:
	xorl	%eax, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MMC_TIMING_UHS_DDR50,8,3       ## @MMC_TIMING_UHS_DDR50
	.comm	_MMC_TIMING_MMC_DDR52,8,3       ## @MMC_TIMING_MMC_DDR52
	.comm	_SDHCI_TUNING_MODE_1,8,3        ## @SDHCI_TUNING_MODE_1
	.no_dead_strip	_xenon_execute_tuning
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function xenon_execute_tuning
_xenon_execute_tuning:                  ; @xenon_execute_tuning
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x1
	mov	x20, x0
	bl	_mmc_priv
	ldr	x8, [x0]
Lloh0:
	adrp	x9, _MMC_TIMING_UHS_DDR50@GOTPAGE
Lloh1:
	ldr	x9, [x9, _MMC_TIMING_UHS_DDR50@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
Lloh3:
	adrp	x10, _MMC_TIMING_MMC_DDR52@GOTPAGE
Lloh4:
	ldr	x10, [x10, _MMC_TIMING_MMC_DDR52@GOTPAGEOFF]
Lloh5:
	ldr	x10, [x10]
	cmp	x8, x9
	ccmp	x8, x10, #4, ne
	b.ne	LBB0_2
; %bb.1:
	mov	w0, #0
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_2:
	ldr	x8, [x0, #8]
Lloh6:
	adrp	x9, _SDHCI_TUNING_MODE_1@GOTPAGE
Lloh7:
	ldr	x9, [x9, _SDHCI_TUNING_MODE_1@GOTPAGEOFF]
Lloh8:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_4
; %bb.3:
	bl	_xenon_retune_setup
LBB0_4:
	mov	x0, x20
	mov	x1, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_sdhci_execute_tuning
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_MMC_TIMING_UHS_DDR50,8,3       ; @MMC_TIMING_UHS_DDR50
	.comm	_MMC_TIMING_MMC_DDR52,8,3       ; @MMC_TIMING_MMC_DDR52
	.comm	_SDHCI_TUNING_MODE_1,8,3        ; @SDHCI_TUNING_MODE_1
	.no_dead_strip	_xenon_execute_tuning
.subsections_via_symbols
