	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function xgene_gmac_set_speed
_xgene_gmac_set_speed:                  ## @xgene_gmac_set_speed
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	_ICM_CONFIG0_REG_0_ADDR@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	leaq	-56(%rbp), %rdx
	callq	_xgene_enet_rd_mcx_csr
	movq	_ICM_CONFIG2_REG_0_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-52(%rbp), %rdx
	movq	%rbx, %rdi
	callq	_xgene_enet_rd_mcx_csr
	movq	_MAC_CONFIG_2_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_xgene_enet_rd_mac
	movl	%eax, -48(%rbp)
	movq	_INTERFACE_CONTROL_ADDR@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%rbx, %rdi
	callq	_xgene_enet_rd_mac
	movl	%eax, %r14d
	movq	_RGMII_REG_0_ADDR@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	leaq	-44(%rbp), %rdx
	movq	%rbx, %rdi
	callq	_xgene_enet_rd_csr
	movl	(%rbx), %eax
	leaq	-48(%rbp), %rdi
	cmpl	$128, %eax
	je	LBB0_4
## %bb.1:
	cmpl	$129, %eax
	jne	LBB0_5
## %bb.2:
	movl	$1, %esi
	callq	_ENET_INTERFACE_MODE2_SET
	movq	_ENET_LHD_MODE@GOTPCREL(%rip), %rax
	movq	_ENET_GHD_MODE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	notl	%ecx
	andl	%ecx, %r14d
	leaq	-56(%rbp), %rdi
	xorl	%esi, %esi
	callq	_CFG_MACMODE_SET
	leaq	-52(%rbp), %rdi
	movl	$500, %esi                      ## imm = 0x1F4
	jmp	LBB0_3
LBB0_4:
	movl	$1, %esi
	callq	_ENET_INTERFACE_MODE2_SET
	movq	_ENET_GHD_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r14d
	movq	_ENET_LHD_MODE@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
	leaq	-56(%rbp), %rdi
	movl	$1, %esi
	callq	_CFG_MACMODE_SET
	leaq	-52(%rbp), %rdi
	movl	$80, %esi
LBB0_3:
	callq	_CFG_WAITASYNCRD_SET
	movq	_CFG_SPEED_1250@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, -44(%rbp)
	jmp	LBB0_6
LBB0_5:
	movl	$2, %esi
	callq	_ENET_INTERFACE_MODE2_SET
	movq	_ENET_LHD_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r14d
	movq	_ENET_GHD_MODE@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
	leaq	-56(%rbp), %rdi
	movl	$2, %esi
	callq	_CFG_MACMODE_SET
	leaq	-52(%rbp), %rdi
	xorl	%esi, %esi
	callq	_CFG_WAITASYNCRD_SET
	movl	8(%rbx), %esi
	leaq	-44(%rbp), %r15
	movq	%r15, %rdi
	callq	_CFG_TXCLK_MUXSEL0_SET
	movl	4(%rbx), %esi
	movq	%r15, %rdi
	callq	_CFG_RXCLK_MUXSEL0_SET
	movq	_CFG_SPEED_1250@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, -44(%rbp)
	movq	_DEBUG_REG_ADDR@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	leaq	-60(%rbp), %rdx
	movq	%rbx, %rdi
	callq	_xgene_enet_rd_csr
	movq	_CFG_BYPASS_UNISEC_TX@GOTPCREL(%rip), %rax
	movq	_CFG_BYPASS_UNISEC_RX@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	orl	-60(%rbp), %edx
	movl	%edx, -60(%rbp)
	movl	(%r15), %esi
	movq	_ICM_CONFIG0_REG_0_ADDR@GOTPCREL(%rip), %r15
	movq	%rbx, %rdi
	callq	_xgene_enet_wr_csr
LBB0_6:
	movq	_FULL_DUPLEX2@GOTPCREL(%rip), %rax
	movq	_PAD_CRC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	_LENGTH_CHK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	orl	-48(%rbp), %edx
	movl	%edx, -48(%rbp)
	movq	_MAC_CONFIG_2_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_xgene_enet_wr_mac
	movl	(%r13), %esi
	movq	%rbx, %rdi
	movl	%r14d, %edx
	callq	_xgene_enet_wr_mac
	movl	(%r12), %esi
	movl	-44(%rbp), %edx
	movq	%rbx, %rdi
	callq	_xgene_enet_wr_csr
	movq	%rbx, %rdi
	callq	_xgene_enet_configure_clock
	movl	(%r15), %esi
	movl	-56(%rbp), %edx
	movq	%rbx, %rdi
	callq	_xgene_enet_wr_mcx_csr
	movq	_ICM_CONFIG2_REG_0_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-52(%rbp), %edx
	movq	%rbx, %rdi
	callq	_xgene_enet_wr_mcx_csr
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_ICM_CONFIG0_REG_0_ADDR,4,2     ## @ICM_CONFIG0_REG_0_ADDR
	.comm	_ICM_CONFIG2_REG_0_ADDR,4,2     ## @ICM_CONFIG2_REG_0_ADDR
	.comm	_MAC_CONFIG_2_ADDR,4,2          ## @MAC_CONFIG_2_ADDR
	.comm	_INTERFACE_CONTROL_ADDR,4,2     ## @INTERFACE_CONTROL_ADDR
	.comm	_RGMII_REG_0_ADDR,4,2           ## @RGMII_REG_0_ADDR
	.comm	_ENET_LHD_MODE,4,2              ## @ENET_LHD_MODE
	.comm	_ENET_GHD_MODE,4,2              ## @ENET_GHD_MODE
	.comm	_CFG_SPEED_1250,4,2             ## @CFG_SPEED_1250
	.comm	_DEBUG_REG_ADDR,4,2             ## @DEBUG_REG_ADDR
	.comm	_CFG_BYPASS_UNISEC_TX,4,2       ## @CFG_BYPASS_UNISEC_TX
	.comm	_CFG_BYPASS_UNISEC_RX,4,2       ## @CFG_BYPASS_UNISEC_RX
	.comm	_FULL_DUPLEX2,4,2               ## @FULL_DUPLEX2
	.comm	_PAD_CRC,4,2                    ## @PAD_CRC
	.comm	_LENGTH_CHK,4,2                 ## @LENGTH_CHK
	.no_dead_strip	_xgene_gmac_set_speed
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function xgene_gmac_set_speed
_xgene_gmac_set_speed:                  ; @xgene_gmac_set_speed
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
Lloh0:
	adrp	x21, _ICM_CONFIG0_REG_0_ADDR@GOTPAGE
Lloh1:
	ldr	x21, [x21, _ICM_CONFIG0_REG_0_ADDR@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x2, sp, #28
	bl	_xgene_enet_rd_mcx_csr
Lloh2:
	adrp	x22, _ICM_CONFIG2_REG_0_ADDR@GOTPAGE
Lloh3:
	ldr	x22, [x22, _ICM_CONFIG2_REG_0_ADDR@GOTPAGEOFF]
	ldr	w1, [x22]
	add	x2, sp, #24
	mov	x0, x19
	bl	_xgene_enet_rd_mcx_csr
Lloh4:
	adrp	x23, _MAC_CONFIG_2_ADDR@GOTPAGE
Lloh5:
	ldr	x23, [x23, _MAC_CONFIG_2_ADDR@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x19
	bl	_xgene_enet_rd_mac
	str	w0, [sp, #20]
Lloh6:
	adrp	x24, _INTERFACE_CONTROL_ADDR@GOTPAGE
Lloh7:
	ldr	x24, [x24, _INTERFACE_CONTROL_ADDR@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	x0, x19
	bl	_xgene_enet_rd_mac
	mov	x20, x0
Lloh8:
	adrp	x25, _RGMII_REG_0_ADDR@GOTPAGE
Lloh9:
	ldr	x25, [x25, _RGMII_REG_0_ADDR@GOTPAGEOFF]
	ldr	w1, [x25]
	add	x2, sp, #16
	mov	x0, x19
	bl	_xgene_enet_rd_csr
	ldr	w8, [x19]
	add	x0, sp, #20
	cmp	w8, #128
	b.eq	LBB0_3
; %bb.1:
	cmp	w8, #129
	b.ne	LBB0_5
; %bb.2:
	mov	w1, #1
	bl	_ENET_INTERFACE_MODE2_SET
Lloh10:
	adrp	x8, _ENET_LHD_MODE@GOTPAGE
Lloh11:
	ldr	x8, [x8, _ENET_LHD_MODE@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
Lloh13:
	adrp	x9, _ENET_GHD_MODE@GOTPAGE
Lloh14:
	ldr	x9, [x9, _ENET_GHD_MODE@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w20, w20, w8
	add	x0, sp, #28
	mov	w1, #0
	bl	_CFG_MACMODE_SET
	add	x0, sp, #24
	mov	w1, #500
	b	LBB0_4
LBB0_3:
	mov	w1, #1
	bl	_ENET_INTERFACE_MODE2_SET
Lloh16:
	adrp	x8, _ENET_GHD_MODE@GOTPAGE
Lloh17:
	ldr	x8, [x8, _ENET_GHD_MODE@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	bic	w8, w20, w8
Lloh19:
	adrp	x9, _ENET_LHD_MODE@GOTPAGE
Lloh20:
	ldr	x9, [x9, _ENET_LHD_MODE@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	orr	w20, w8, w9
	add	x0, sp, #28
	mov	w1, #1
	bl	_CFG_MACMODE_SET
	add	x0, sp, #24
	mov	w1, #80
LBB0_4:
	bl	_CFG_WAITASYNCRD_SET
Lloh22:
	adrp	x8, _CFG_SPEED_1250@GOTPAGE
Lloh23:
	ldr	x8, [x8, _CFG_SPEED_1250@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	ldr	w9, [sp, #16]
	bic	w8, w9, w8
	str	w8, [sp, #16]
	b	LBB0_6
LBB0_5:
	mov	w1, #2
	bl	_ENET_INTERFACE_MODE2_SET
Lloh25:
	adrp	x8, _ENET_LHD_MODE@GOTPAGE
Lloh26:
	ldr	x8, [x8, _ENET_LHD_MODE@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
	bic	w8, w20, w8
Lloh28:
	adrp	x9, _ENET_GHD_MODE@GOTPAGE
Lloh29:
	ldr	x9, [x9, _ENET_GHD_MODE@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
	orr	w20, w8, w9
	add	x0, sp, #28
	mov	w1, #2
	bl	_CFG_MACMODE_SET
	add	x0, sp, #24
	mov	w1, #0
	bl	_CFG_WAITASYNCRD_SET
	ldr	w1, [x19, #8]
	add	x0, sp, #16
	bl	_CFG_TXCLK_MUXSEL0_SET
	ldr	w1, [x19, #4]
	add	x0, sp, #16
	bl	_CFG_RXCLK_MUXSEL0_SET
Lloh31:
	adrp	x8, _CFG_SPEED_1250@GOTPAGE
Lloh32:
	ldr	x8, [x8, _CFG_SPEED_1250@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
	ldr	w9, [sp, #16]
	orr	w8, w9, w8
	str	w8, [sp, #16]
Lloh34:
	adrp	x26, _DEBUG_REG_ADDR@GOTPAGE
Lloh35:
	ldr	x26, [x26, _DEBUG_REG_ADDR@GOTPAGEOFF]
	ldr	w1, [x26]
	add	x2, sp, #12
	mov	x0, x19
	bl	_xgene_enet_rd_csr
Lloh36:
	adrp	x8, _CFG_BYPASS_UNISEC_TX@GOTPAGE
Lloh37:
	ldr	x8, [x8, _CFG_BYPASS_UNISEC_TX@GOTPAGEOFF]
Lloh38:
	ldr	w8, [x8]
Lloh39:
	adrp	x9, _CFG_BYPASS_UNISEC_RX@GOTPAGE
Lloh40:
	ldr	x9, [x9, _CFG_BYPASS_UNISEC_RX@GOTPAGEOFF]
Lloh41:
	ldr	w9, [x9]
	orr	w8, w9, w8
	ldr	w9, [sp, #12]
	orr	w2, w8, w9
	str	w2, [sp, #12]
	ldr	w1, [x26]
	mov	x0, x19
	bl	_xgene_enet_wr_csr
LBB0_6:
Lloh42:
	adrp	x8, _FULL_DUPLEX2@GOTPAGE
Lloh43:
	ldr	x8, [x8, _FULL_DUPLEX2@GOTPAGEOFF]
Lloh44:
	ldr	w8, [x8]
Lloh45:
	adrp	x9, _PAD_CRC@GOTPAGE
Lloh46:
	ldr	x9, [x9, _PAD_CRC@GOTPAGEOFF]
Lloh47:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh48:
	adrp	x9, _LENGTH_CHK@GOTPAGE
Lloh49:
	ldr	x9, [x9, _LENGTH_CHK@GOTPAGEOFF]
Lloh50:
	ldr	w9, [x9]
	orr	w8, w8, w9
	ldr	w9, [sp, #20]
	orr	w2, w8, w9
	str	w2, [sp, #20]
	ldr	w1, [x23]
	mov	x0, x19
	bl	_xgene_enet_wr_mac
	ldr	w1, [x24]
	mov	x0, x19
	mov	x2, x20
	bl	_xgene_enet_wr_mac
	ldr	w1, [x25]
	ldr	w2, [sp, #16]
	mov	x0, x19
	bl	_xgene_enet_wr_csr
	mov	x0, x19
	bl	_xgene_enet_configure_clock
	ldr	w1, [x21]
	ldr	w2, [sp, #28]
	mov	x0, x19
	bl	_xgene_enet_wr_mcx_csr
	ldr	w1, [x22]
	ldr	w2, [sp, #24]
	mov	x0, x19
	bl	_xgene_enet_wr_mcx_csr
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.cfi_endproc
                                        ; -- End function
	.comm	_ICM_CONFIG0_REG_0_ADDR,4,2     ; @ICM_CONFIG0_REG_0_ADDR
	.comm	_ICM_CONFIG2_REG_0_ADDR,4,2     ; @ICM_CONFIG2_REG_0_ADDR
	.comm	_MAC_CONFIG_2_ADDR,4,2          ; @MAC_CONFIG_2_ADDR
	.comm	_INTERFACE_CONTROL_ADDR,4,2     ; @INTERFACE_CONTROL_ADDR
	.comm	_RGMII_REG_0_ADDR,4,2           ; @RGMII_REG_0_ADDR
	.comm	_ENET_LHD_MODE,4,2              ; @ENET_LHD_MODE
	.comm	_ENET_GHD_MODE,4,2              ; @ENET_GHD_MODE
	.comm	_CFG_SPEED_1250,4,2             ; @CFG_SPEED_1250
	.comm	_DEBUG_REG_ADDR,4,2             ; @DEBUG_REG_ADDR
	.comm	_CFG_BYPASS_UNISEC_TX,4,2       ; @CFG_BYPASS_UNISEC_TX
	.comm	_CFG_BYPASS_UNISEC_RX,4,2       ; @CFG_BYPASS_UNISEC_RX
	.comm	_FULL_DUPLEX2,4,2               ; @FULL_DUPLEX2
	.comm	_PAD_CRC,4,2                    ; @PAD_CRC
	.comm	_LENGTH_CHK,4,2                 ; @LENGTH_CHK
	.no_dead_strip	_xgene_gmac_set_speed
.subsections_via_symbols
