	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rvin_set_coeff
_rvin_set_coeff:                        ## @rvin_set_coeff
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %rbx
	movq	_vin_coeff_set@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	callq	_ARRAY_SIZE
	testl	%eax, %eax
	jle	LBB0_1
## %bb.2:
	movq	(%r15), %r13
	cmpw	%r14w, (%r13)
	jbe	LBB0_4
## %bb.3:
	xorl	%r15d, %r15d
	testq	%r15, %r15
	jne	LBB0_11
	jmp	LBB0_12
LBB0_1:
	xorl	%r13d, %r13d
	jmp	LBB0_12
LBB0_4:
	movl	%r14d, -44(%rbp)                ## 4-byte Spill
	movq	%rbx, -56(%rbp)                 ## 8-byte Spill
	xorl	%r12d, %r12d
	movq	%r13, %rax
	xorl	%r15d, %r15d
	xorl	%r14d, %r14d
	.p2align	4, 0x90
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	movq	%rax, %rbx
	incq	%r14
	movq	%r13, %rdi
	callq	_ARRAY_SIZE
	cltq
	cmpq	%rax, %r14
	jge	LBB0_6
## %bb.7:                               ##   in Loop: Header=BB0_5 Depth=1
	leaq	16(%r12), %rcx
	movq	_vin_coeff_set@GOTPCREL(%rip), %rax
	movq	(%rax), %r13
	movq	%r14, %rax
	shlq	$4, %rax
	addq	%r13, %rax
	movq	%rbx, %r15
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	cmpw	%dx, 16(%r13,%r12)
	movq	%rcx, %r12
	jbe	LBB0_5
## %bb.8:
	addq	%rcx, %r13
	movq	%rbx, %r15
	jmp	LBB0_9
LBB0_6:
	movq	%rbx, %r13
LBB0_9:
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movl	-44(%rbp), %r14d                ## 4-byte Reload
	testq	%r15, %r15
	je	LBB0_12
LBB0_11:
	movzwl	%r14w, %eax
	movzwl	(%r15), %ecx
	movzwl	(%r13), %edx
	subl	%eax, %edx
	subl	%ecx, %eax
	cmpl	%edx, %eax
	cmovlq	%r15, %r13
LBB0_12:
	movq	8(%r13), %rax
	movl	(%rax), %esi
	movq	_VNC1A_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	4(%rax), %esi
	movq	_VNC1B_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	8(%rax), %esi
	movq	_VNC1C_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	12(%rax), %esi
	movq	_VNC2A_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	16(%rax), %esi
	movq	_VNC2B_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	20(%rax), %esi
	movq	_VNC2C_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	24(%rax), %esi
	movq	_VNC3A_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	28(%rax), %esi
	movq	_VNC3B_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	32(%rax), %esi
	movq	_VNC3C_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	36(%rax), %esi
	movq	_VNC4A_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	40(%rax), %esi
	movq	_VNC4B_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	44(%rax), %esi
	movq	_VNC4C_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	48(%rax), %esi
	movq	_VNC5A_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	52(%rax), %esi
	movq	_VNC5B_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	56(%rax), %esi
	movq	_VNC5C_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	60(%rax), %esi
	movq	_VNC6A_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	64(%rax), %esi
	movq	_VNC6B_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	68(%rax), %esi
	movq	_VNC6C_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	72(%rax), %esi
	movq	_VNC7A_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	76(%rax), %esi
	movq	_VNC7B_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	80(%rax), %esi
	movq	_VNC7C_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	84(%rax), %esi
	movq	_VNC8A_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	88(%rax), %esi
	movq	_VNC8B_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rvin_write
	movq	8(%r13), %rax
	movl	92(%rax), %esi
	movq	_VNC8C_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_rvin_write                     ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_vin_coeff_set,8,3              ## @vin_coeff_set
	.comm	_VNC1A_REG,4,2                  ## @VNC1A_REG
	.comm	_VNC1B_REG,4,2                  ## @VNC1B_REG
	.comm	_VNC1C_REG,4,2                  ## @VNC1C_REG
	.comm	_VNC2A_REG,4,2                  ## @VNC2A_REG
	.comm	_VNC2B_REG,4,2                  ## @VNC2B_REG
	.comm	_VNC2C_REG,4,2                  ## @VNC2C_REG
	.comm	_VNC3A_REG,4,2                  ## @VNC3A_REG
	.comm	_VNC3B_REG,4,2                  ## @VNC3B_REG
	.comm	_VNC3C_REG,4,2                  ## @VNC3C_REG
	.comm	_VNC4A_REG,4,2                  ## @VNC4A_REG
	.comm	_VNC4B_REG,4,2                  ## @VNC4B_REG
	.comm	_VNC4C_REG,4,2                  ## @VNC4C_REG
	.comm	_VNC5A_REG,4,2                  ## @VNC5A_REG
	.comm	_VNC5B_REG,4,2                  ## @VNC5B_REG
	.comm	_VNC5C_REG,4,2                  ## @VNC5C_REG
	.comm	_VNC6A_REG,4,2                  ## @VNC6A_REG
	.comm	_VNC6B_REG,4,2                  ## @VNC6B_REG
	.comm	_VNC6C_REG,4,2                  ## @VNC6C_REG
	.comm	_VNC7A_REG,4,2                  ## @VNC7A_REG
	.comm	_VNC7B_REG,4,2                  ## @VNC7B_REG
	.comm	_VNC7C_REG,4,2                  ## @VNC7C_REG
	.comm	_VNC8A_REG,4,2                  ## @VNC8A_REG
	.comm	_VNC8B_REG,4,2                  ## @VNC8B_REG
	.comm	_VNC8C_REG,4,2                  ## @VNC8C_REG
	.no_dead_strip	_rvin_set_coeff
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rvin_set_coeff
_rvin_set_coeff:                        ; @rvin_set_coeff
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x1
	mov	x19, x0
Lloh0:
	adrp	x22, _vin_coeff_set@GOTPAGE
Lloh1:
	ldr	x22, [x22, _vin_coeff_set@GOTPAGEOFF]
	ldr	x0, [x22]
	bl	_ARRAY_SIZE
	cmp	w0, #1
	b.lt	LBB0_3
; %bb.1:
	ldr	x20, [x22]
	ldrh	w8, [x20]
	cmp	w8, w21
	b.ls	LBB0_4
; %bb.2:
	mov	x24, #0
	b	LBB0_8
LBB0_3:
	mov	x20, #0
	b	LBB0_10
LBB0_4:
	mov	x26, #0
	mov	x24, #0
	mov	x25, #0
	mov	x23, x20
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	mov	x27, x23
	add	x25, x25, #1
	mov	x0, x20
	bl	_ARRAY_SIZE
	cmp	x25, w0, sxtw
	b.ge	LBB0_11
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	add	x8, x26, #16
	ldr	x20, [x22]
	add	x23, x20, x25, lsl #4
	add	x9, x20, x26
	ldrh	w9, [x9, #16]
	mov	x26, x8
	mov	x24, x27
	cmp	w9, w21
	b.ls	LBB0_5
; %bb.7:
	add	x20, x20, x8
	mov	x24, x27
LBB0_8:
	mov	x23, x20
	cbz	x24, LBB0_10
LBB0_9:
	ldrh	w8, [x24]
	sub	w8, w21, w8
	ldrh	w9, [x23]
	sub	w9, w9, w21
	cmp	w8, w9
	csel	x20, x24, x20, lt
LBB0_10:
	ldr	x8, [x20, #8]
	ldr	w1, [x8]
Lloh2:
	adrp	x8, _VNC1A_REG@GOTPAGE
Lloh3:
	ldr	x8, [x8, _VNC1A_REG@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #4]
Lloh5:
	adrp	x8, _VNC1B_REG@GOTPAGE
Lloh6:
	ldr	x8, [x8, _VNC1B_REG@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #8]
Lloh8:
	adrp	x8, _VNC1C_REG@GOTPAGE
Lloh9:
	ldr	x8, [x8, _VNC1C_REG@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #12]
Lloh11:
	adrp	x8, _VNC2A_REG@GOTPAGE
Lloh12:
	ldr	x8, [x8, _VNC2A_REG@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #16]
Lloh14:
	adrp	x8, _VNC2B_REG@GOTPAGE
Lloh15:
	ldr	x8, [x8, _VNC2B_REG@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #20]
Lloh17:
	adrp	x8, _VNC2C_REG@GOTPAGE
Lloh18:
	ldr	x8, [x8, _VNC2C_REG@GOTPAGEOFF]
Lloh19:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #24]
Lloh20:
	adrp	x8, _VNC3A_REG@GOTPAGE
Lloh21:
	ldr	x8, [x8, _VNC3A_REG@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #28]
Lloh23:
	adrp	x8, _VNC3B_REG@GOTPAGE
Lloh24:
	ldr	x8, [x8, _VNC3B_REG@GOTPAGEOFF]
Lloh25:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #32]
Lloh26:
	adrp	x8, _VNC3C_REG@GOTPAGE
Lloh27:
	ldr	x8, [x8, _VNC3C_REG@GOTPAGEOFF]
Lloh28:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #36]
Lloh29:
	adrp	x8, _VNC4A_REG@GOTPAGE
Lloh30:
	ldr	x8, [x8, _VNC4A_REG@GOTPAGEOFF]
Lloh31:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #40]
Lloh32:
	adrp	x8, _VNC4B_REG@GOTPAGE
Lloh33:
	ldr	x8, [x8, _VNC4B_REG@GOTPAGEOFF]
Lloh34:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #44]
Lloh35:
	adrp	x8, _VNC4C_REG@GOTPAGE
Lloh36:
	ldr	x8, [x8, _VNC4C_REG@GOTPAGEOFF]
Lloh37:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #48]
Lloh38:
	adrp	x8, _VNC5A_REG@GOTPAGE
Lloh39:
	ldr	x8, [x8, _VNC5A_REG@GOTPAGEOFF]
Lloh40:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #52]
Lloh41:
	adrp	x8, _VNC5B_REG@GOTPAGE
Lloh42:
	ldr	x8, [x8, _VNC5B_REG@GOTPAGEOFF]
Lloh43:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #56]
Lloh44:
	adrp	x8, _VNC5C_REG@GOTPAGE
Lloh45:
	ldr	x8, [x8, _VNC5C_REG@GOTPAGEOFF]
Lloh46:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #60]
Lloh47:
	adrp	x8, _VNC6A_REG@GOTPAGE
Lloh48:
	ldr	x8, [x8, _VNC6A_REG@GOTPAGEOFF]
Lloh49:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #64]
Lloh50:
	adrp	x8, _VNC6B_REG@GOTPAGE
Lloh51:
	ldr	x8, [x8, _VNC6B_REG@GOTPAGEOFF]
Lloh52:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #68]
Lloh53:
	adrp	x8, _VNC6C_REG@GOTPAGE
Lloh54:
	ldr	x8, [x8, _VNC6C_REG@GOTPAGEOFF]
Lloh55:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #72]
Lloh56:
	adrp	x8, _VNC7A_REG@GOTPAGE
Lloh57:
	ldr	x8, [x8, _VNC7A_REG@GOTPAGEOFF]
Lloh58:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #76]
Lloh59:
	adrp	x8, _VNC7B_REG@GOTPAGE
Lloh60:
	ldr	x8, [x8, _VNC7B_REG@GOTPAGEOFF]
Lloh61:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #80]
Lloh62:
	adrp	x8, _VNC7C_REG@GOTPAGE
Lloh63:
	ldr	x8, [x8, _VNC7C_REG@GOTPAGEOFF]
Lloh64:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #84]
Lloh65:
	adrp	x8, _VNC8A_REG@GOTPAGE
Lloh66:
	ldr	x8, [x8, _VNC8A_REG@GOTPAGEOFF]
Lloh67:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #88]
Lloh68:
	adrp	x8, _VNC8B_REG@GOTPAGE
Lloh69:
	ldr	x8, [x8, _VNC8B_REG@GOTPAGEOFF]
Lloh70:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_rvin_write
	ldr	x8, [x20, #8]
	ldr	w1, [x8, #92]
Lloh71:
	adrp	x8, _VNC8C_REG@GOTPAGE
Lloh72:
	ldr	x8, [x8, _VNC8C_REG@GOTPAGEOFF]
Lloh73:
	ldr	w2, [x8]
	mov	x0, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_rvin_write
LBB0_11:
	mov	x20, x27
	cbnz	x24, LBB0_9
	b	LBB0_10
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_vin_coeff_set,8,3              ; @vin_coeff_set
	.comm	_VNC1A_REG,4,2                  ; @VNC1A_REG
	.comm	_VNC1B_REG,4,2                  ; @VNC1B_REG
	.comm	_VNC1C_REG,4,2                  ; @VNC1C_REG
	.comm	_VNC2A_REG,4,2                  ; @VNC2A_REG
	.comm	_VNC2B_REG,4,2                  ; @VNC2B_REG
	.comm	_VNC2C_REG,4,2                  ; @VNC2C_REG
	.comm	_VNC3A_REG,4,2                  ; @VNC3A_REG
	.comm	_VNC3B_REG,4,2                  ; @VNC3B_REG
	.comm	_VNC3C_REG,4,2                  ; @VNC3C_REG
	.comm	_VNC4A_REG,4,2                  ; @VNC4A_REG
	.comm	_VNC4B_REG,4,2                  ; @VNC4B_REG
	.comm	_VNC4C_REG,4,2                  ; @VNC4C_REG
	.comm	_VNC5A_REG,4,2                  ; @VNC5A_REG
	.comm	_VNC5B_REG,4,2                  ; @VNC5B_REG
	.comm	_VNC5C_REG,4,2                  ; @VNC5C_REG
	.comm	_VNC6A_REG,4,2                  ; @VNC6A_REG
	.comm	_VNC6B_REG,4,2                  ; @VNC6B_REG
	.comm	_VNC6C_REG,4,2                  ; @VNC6C_REG
	.comm	_VNC7A_REG,4,2                  ; @VNC7A_REG
	.comm	_VNC7B_REG,4,2                  ; @VNC7B_REG
	.comm	_VNC7C_REG,4,2                  ; @VNC7C_REG
	.comm	_VNC8A_REG,4,2                  ; @VNC8A_REG
	.comm	_VNC8B_REG,4,2                  ; @VNC8B_REG
	.comm	_VNC8C_REG,4,2                  ; @VNC8C_REG
	.no_dead_strip	_rvin_set_coeff
.subsections_via_symbols
