	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tps65218_voltage_set_uvlo
_tps65218_voltage_set_uvlo:             ## @tps65218_voltage_set_uvlo
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	subq	$16, %rsp
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	movq	(%rdi), %rax
	movl	(%rax), %edi
	leaq	L_.str(%rip), %rsi
	leaq	-20(%rbp), %rdx
	callq	_of_property_read_u32
	xorl	%r14d, %r14d
	testq	%rax, %rax
	jne	LBB0_11
## %bb.1:
	movl	-20(%rbp), %eax
	cmpl	$3249999, %eax                  ## imm = 0x31974F
	jg	LBB0_4
## %bb.2:
	cmpl	$2750000, %eax                  ## imm = 0x29F630
	je	LBB0_3
## %bb.7:
	cmpl	$2950000, %eax                  ## imm = 0x2D0370
	jne	LBB0_8
## %bb.9:
	movq	_TPS65218_CONFIG1_UVLO_2950000@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_4:
	cmpl	$3250000, %eax                  ## imm = 0x319750
	je	LBB0_12
## %bb.5:
	cmpl	$3350000, %eax                  ## imm = 0x331DF0
	jne	LBB0_8
## %bb.6:
	movq	_TPS65218_CONFIG1_UVLO_3350000@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_3:
	movq	_TPS65218_CONFIG1_UVLO_2750000@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_12:
	movq	_TPS65218_CONFIG1_UVLO_3250000@GOTPCREL(%rip), %rax
LBB0_10:
	movl	(%rax), %ecx
	movq	_TPS65218_REG_CONFIG1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_TPS65218_CONFIG1_UVLO_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_TPS65218_PROTECT_L1@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	movq	%rbx, %rdi
	callq	_tps65218_update_bits
	jmp	LBB0_11
LBB0_8:
	movq	(%rbx), %rdi
	leaq	L_.str.1(%rip), %rsi
	callq	_dev_err
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r14d, %r14d
	subl	(%rax), %r14d
LBB0_11:
	movl	%r14d, %eax
	addq	$16, %rsp
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"ti,under-voltage-limit-microvolt"

	.comm	_TPS65218_CONFIG1_UVLO_2750000,4,2 ## @TPS65218_CONFIG1_UVLO_2750000
	.comm	_TPS65218_CONFIG1_UVLO_2950000,4,2 ## @TPS65218_CONFIG1_UVLO_2950000
	.comm	_TPS65218_CONFIG1_UVLO_3250000,4,2 ## @TPS65218_CONFIG1_UVLO_3250000
	.comm	_TPS65218_CONFIG1_UVLO_3350000,4,2 ## @TPS65218_CONFIG1_UVLO_3350000
L_.str.1:                               ## @.str.1
	.asciz	"Invalid ti,under-voltage-limit-microvolt value\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_TPS65218_REG_CONFIG1,4,2       ## @TPS65218_REG_CONFIG1
	.comm	_TPS65218_CONFIG1_UVLO_MASK,4,2 ## @TPS65218_CONFIG1_UVLO_MASK
	.comm	_TPS65218_PROTECT_L1,4,2        ## @TPS65218_PROTECT_L1
	.no_dead_strip	_tps65218_voltage_set_uvlo
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tps65218_voltage_set_uvlo
_tps65218_voltage_set_uvlo:             ; @tps65218_voltage_set_uvlo
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #48
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	x8, [x0]
	ldr	w0, [x8]
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	add	x2, sp, #12
	bl	_of_property_read_u32
	cbnz	x0, LBB0_11
; %bb.1:
	ldr	w8, [sp, #12]
	mov	w9, #38735
	movk	w9, #49, lsl #16
	cmp	w8, w9
	b.gt	LBB0_5
; %bb.2:
	mov	w9, #63024
	movk	w9, #41, lsl #16
	cmp	w8, w9
	b.eq	LBB0_8
; %bb.3:
	mov	w9, #880
	movk	w9, #45, lsl #16
	cmp	w8, w9
	b.ne	LBB0_13
; %bb.4:
Lloh2:
	adrp	x8, _TPS65218_CONFIG1_UVLO_2950000@GOTPAGE
Lloh3:
	ldr	x8, [x8, _TPS65218_CONFIG1_UVLO_2950000@GOTPAGEOFF]
	b	LBB0_10
LBB0_5:
	mov	w9, #38736
	movk	w9, #49, lsl #16
	cmp	w8, w9
	b.eq	LBB0_9
; %bb.6:
	mov	w9, #7664
	movk	w9, #51, lsl #16
	cmp	w8, w9
	b.ne	LBB0_13
; %bb.7:
Lloh4:
	adrp	x8, _TPS65218_CONFIG1_UVLO_3350000@GOTPAGE
Lloh5:
	ldr	x8, [x8, _TPS65218_CONFIG1_UVLO_3350000@GOTPAGEOFF]
	b	LBB0_10
LBB0_8:
Lloh6:
	adrp	x8, _TPS65218_CONFIG1_UVLO_2750000@GOTPAGE
Lloh7:
	ldr	x8, [x8, _TPS65218_CONFIG1_UVLO_2750000@GOTPAGEOFF]
	b	LBB0_10
LBB0_9:
Lloh8:
	adrp	x8, _TPS65218_CONFIG1_UVLO_3250000@GOTPAGE
Lloh9:
	ldr	x8, [x8, _TPS65218_CONFIG1_UVLO_3250000@GOTPAGEOFF]
LBB0_10:
	ldr	w3, [x8]
Lloh10:
	adrp	x8, _TPS65218_REG_CONFIG1@GOTPAGE
Lloh11:
	ldr	x8, [x8, _TPS65218_REG_CONFIG1@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
Lloh13:
	adrp	x8, _TPS65218_CONFIG1_UVLO_MASK@GOTPAGE
Lloh14:
	ldr	x8, [x8, _TPS65218_CONFIG1_UVLO_MASK@GOTPAGEOFF]
Lloh15:
	ldr	w2, [x8]
Lloh16:
	adrp	x8, _TPS65218_PROTECT_L1@GOTPAGE
Lloh17:
	ldr	x8, [x8, _TPS65218_PROTECT_L1@GOTPAGEOFF]
Lloh18:
	ldr	w4, [x8]
	mov	x0, x19
	bl	_tps65218_update_bits
LBB0_11:
	mov	w0, #0
LBB0_12:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	ret
LBB0_13:
	ldr	x0, [x19]
Lloh19:
	adrp	x1, l_.str.1@PAGE
Lloh20:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_err
Lloh21:
	adrp	x8, _EINVAL@GOTPAGE
Lloh22:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_12
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpAdd	Lloh19, Lloh20
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"ti,under-voltage-limit-microvolt"

	.comm	_TPS65218_CONFIG1_UVLO_2750000,4,2 ; @TPS65218_CONFIG1_UVLO_2750000
	.comm	_TPS65218_CONFIG1_UVLO_2950000,4,2 ; @TPS65218_CONFIG1_UVLO_2950000
	.comm	_TPS65218_CONFIG1_UVLO_3250000,4,2 ; @TPS65218_CONFIG1_UVLO_3250000
	.comm	_TPS65218_CONFIG1_UVLO_3350000,4,2 ; @TPS65218_CONFIG1_UVLO_3350000
l_.str.1:                               ; @.str.1
	.asciz	"Invalid ti,under-voltage-limit-microvolt value\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_TPS65218_REG_CONFIG1,4,2       ; @TPS65218_REG_CONFIG1
	.comm	_TPS65218_CONFIG1_UVLO_MASK,4,2 ; @TPS65218_CONFIG1_UVLO_MASK
	.comm	_TPS65218_PROTECT_L1,4,2        ; @TPS65218_PROTECT_L1
	.no_dead_strip	_tps65218_voltage_set_uvlo
.subsections_via_symbols
