	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function bnx2_wait_dma_complete
_bnx2_wait_dma_complete:                ## @bnx2_wait_dma_complete
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	callq	_BNX2_CHIP
	movq	_BNX2_CHIP_5706@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_6
## %bb.1:
	movq	%r14, %rdi
	callq	_BNX2_CHIP
	movq	_BNX2_CHIP_5708@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_2
LBB0_6:
	movq	_BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE@GOTPCREL(%rip), %rax
	movq	_BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	_BNX2_MISC_ENABLE_CLR_BITS@GOTPCREL(%rip), %rbx
	movq	_BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	(%rbx), %esi
	movq	_BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	%r14, %rdi
	callq	_BNX2_WR
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_BNX2_RD
	movl	$5, %edi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_udelay                         ## TAILCALL
LBB0_2:
	movq	_BNX2_MISC_NEW_CORE_CTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_BNX2_RD
	movq	_BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_BNX2_WR
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_BNX2_RD
	movl	$99, %ebx
	movq	_BNX2_PCICFG_DEVICE_CONTROL@GOTPCREL(%rip), %r15
	movq	_BNX2_PCICFG_DEVICE_STATUS_NO_PEND@GOTPCREL(%rip), %r12
	.p2align	4, 0x90
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movl	$1, %edi
	callq	_msleep
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_BNX2_RD
	subl	$1, %ebx
	setb	%cl
	testl	%eax, (%r12)
	je	LBB0_5
## %bb.4:                               ##   in Loop: Header=BB0_3 Depth=1
	testb	%cl, %cl
	je	LBB0_3
LBB0_5:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_BNX2_CHIP_5706,8,3             ## @BNX2_CHIP_5706
	.comm	_BNX2_CHIP_5708,8,3             ## @BNX2_CHIP_5708
	.comm	_BNX2_MISC_ENABLE_CLR_BITS,4,2  ## @BNX2_MISC_ENABLE_CLR_BITS
	.comm	_BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE,4,2 ## @BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE
	.comm	_BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE,4,2 ## @BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE
	.comm	_BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE,4,2 ## @BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE
	.comm	_BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE,4,2 ## @BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE
	.comm	_BNX2_MISC_NEW_CORE_CTL,4,2     ## @BNX2_MISC_NEW_CORE_CTL
	.comm	_BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE,4,2 ## @BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE
	.comm	_BNX2_PCICFG_DEVICE_CONTROL,4,2 ## @BNX2_PCICFG_DEVICE_CONTROL
	.comm	_BNX2_PCICFG_DEVICE_STATUS_NO_PEND,4,2 ## @BNX2_PCICFG_DEVICE_STATUS_NO_PEND
	.no_dead_strip	_bnx2_wait_dma_complete
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function bnx2_wait_dma_complete
_bnx2_wait_dma_complete:                ; @bnx2_wait_dma_complete
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	bl	_BNX2_CHIP
Lloh0:
	adrp	x8, _BNX2_CHIP_5706@GOTPAGE
Lloh1:
	ldr	x8, [x8, _BNX2_CHIP_5706@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	cmp	x0, x8
	b.eq	LBB0_2
; %bb.1:
	mov	x0, x19
	bl	_BNX2_CHIP
Lloh3:
	adrp	x8, _BNX2_CHIP_5708@GOTPAGE
Lloh4:
	ldr	x8, [x8, _BNX2_CHIP_5708@GOTPAGEOFF]
Lloh5:
	ldr	x8, [x8]
	cmp	x0, x8
	b.ne	LBB0_3
LBB0_2:
Lloh6:
	adrp	x20, _BNX2_MISC_ENABLE_CLR_BITS@GOTPAGE
Lloh7:
	ldr	x20, [x20, _BNX2_MISC_ENABLE_CLR_BITS@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh8:
	adrp	x8, _BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE@GOTPAGE
Lloh9:
	ldr	x8, [x8, _BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
Lloh11:
	adrp	x9, _BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE@GOTPAGE
Lloh12:
	ldr	x9, [x9, _BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh14:
	adrp	x9, _BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE@GOTPAGE
Lloh15:
	ldr	x9, [x9, _BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh17:
	adrp	x9, _BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE@GOTPAGE
Lloh18:
	ldr	x9, [x9, _BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x19
	bl	_BNX2_WR
	ldr	w1, [x20]
	mov	x0, x19
	bl	_BNX2_RD
	mov	w0, #5
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_udelay
LBB0_3:
Lloh20:
	adrp	x20, _BNX2_MISC_NEW_CORE_CTL@GOTPAGE
Lloh21:
	ldr	x20, [x20, _BNX2_MISC_NEW_CORE_CTL@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_BNX2_RD
Lloh22:
	adrp	x8, _BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE@GOTPAGE
Lloh23:
	ldr	x8, [x8, _BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	bic	w2, w0, w8
	ldr	w1, [x20]
	mov	x0, x19
	bl	_BNX2_WR
	ldr	w1, [x20]
	mov	x0, x19
	bl	_BNX2_RD
	mov	w20, #99
Lloh25:
	adrp	x21, _BNX2_PCICFG_DEVICE_CONTROL@GOTPAGE
Lloh26:
	ldr	x21, [x21, _BNX2_PCICFG_DEVICE_CONTROL@GOTPAGEOFF]
Lloh27:
	adrp	x22, _BNX2_PCICFG_DEVICE_STATUS_NO_PEND@GOTPAGE
Lloh28:
	ldr	x22, [x22, _BNX2_PCICFG_DEVICE_STATUS_NO_PEND@GOTPAGEOFF]
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
	mov	w0, #1
	bl	_msleep
	ldr	w1, [x21]
	mov	x0, x19
	bl	_BNX2_RD
	ldr	w8, [x22]
	and	w8, w8, w0
	cmp	w8, #0
	ccmp	w20, #0, #4, ne
	sub	w20, w20, #1
	b.ne	LBB0_4
; %bb.5:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh20, Lloh21
	.cfi_endproc
                                        ; -- End function
	.comm	_BNX2_CHIP_5706,8,3             ; @BNX2_CHIP_5706
	.comm	_BNX2_CHIP_5708,8,3             ; @BNX2_CHIP_5708
	.comm	_BNX2_MISC_ENABLE_CLR_BITS,4,2  ; @BNX2_MISC_ENABLE_CLR_BITS
	.comm	_BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE,4,2 ; @BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE
	.comm	_BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE,4,2 ; @BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE
	.comm	_BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE,4,2 ; @BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE
	.comm	_BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE,4,2 ; @BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE
	.comm	_BNX2_MISC_NEW_CORE_CTL,4,2     ; @BNX2_MISC_NEW_CORE_CTL
	.comm	_BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE,4,2 ; @BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE
	.comm	_BNX2_PCICFG_DEVICE_CONTROL,4,2 ; @BNX2_PCICFG_DEVICE_CONTROL
	.comm	_BNX2_PCICFG_DEVICE_STATUS_NO_PEND,4,2 ; @BNX2_PCICFG_DEVICE_STATUS_NO_PEND
	.no_dead_strip	_bnx2_wait_dma_complete
.subsections_via_symbols
