	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_sdhci_set_ios                  ## -- Begin function sdhci_set_ios
	.p2align	4, 0x90
_sdhci_set_ios:                         ## @sdhci_set_ios
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %r15
	callq	_mmc_priv
	movq	%rax, %rbx
	movl	16(%r14), %eax
	movq	_MMC_POWER_UNDEFINED@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_52
## %bb.1:
	movq	_SDHCI_DEVICE_DEAD@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, (%rbx)
	je	LBB0_5
## %bb.2:
	movl	(%r15), %edi
	callq	_IS_ERR
	testl	%eax, %eax
	jne	LBB0_52
## %bb.3:
	movl	16(%r14), %eax
	movq	_MMC_POWER_OFF@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_52
## %bb.4:
	movl	(%r15), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_mmc_regulator_set_ocr          ## TAILCALL
LBB0_5:
	movq	_MMC_POWER_OFF@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_7
## %bb.6:
	movq	_SDHCI_SIGNAL_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_sdhci_writel
	movq	%rbx, %rdi
	callq	_sdhci_reinit
LBB0_7:
	movq	8(%rbx), %rax
	movq	_SDHCI_SPEC_300@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_11
## %bb.8:
	movl	16(%r14), %eax
	movq	_MMC_POWER_UP@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_11
## %bb.9:
	movq	_SDHCI_QUIRK2_PRESET_VALUE_BROKEN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 16(%rbx)
	jne	LBB0_11
## %bb.10:
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_sdhci_enable_preset_value
LBB0_11:
	movl	(%r14), %esi
	testl	%esi, %esi
	je	LBB0_13
## %bb.12:
	cmpl	20(%rbx), %esi
	je	LBB0_19
LBB0_13:
	movq	32(%rbx), %rax
	movq	%rbx, %rdi
	callq	*8(%rax)
	movl	(%r14), %eax
	movl	%eax, 20(%rbx)
	movq	_SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, 24(%rbx)
	je	LBB0_19
## %bb.14:
	testl	%eax, %eax
	je	LBB0_19
## %bb.15:
	movq	32(%rbx), %rdx
	movq	48(%rbx), %rcx
	movl	(%rcx), %esi
	testl	%esi, %esi
	cmovnel	%esi, %eax
	cltq
	imulq	$274877907, %rax, %rsi          ## imm = 0x10624DD3
	movq	%rsi, %rax
	shrq	$63, %rax
	sarq	$38, %rsi
	addl	%eax, %esi
	movl	%esi, 28(%rbx)
	movq	(%rdx), %rdx
	testq	%rdx, %rdx
	je	LBB0_16
## %bb.17:
	movq	%rbx, %rdi
	callq	*%rdx
	movq	48(%rbx), %rcx
	movl	28(%rbx), %esi
	jmp	LBB0_18
LBB0_16:
	movl	$134217728, %eax                ## imm = 0x8000000
LBB0_18:
	cltd
	idivl	%esi
	movl	%eax, 4(%rcx)
LBB0_19:
	movq	32(%rbx), %rax
	movq	40(%rax), %rax
	movl	16(%r14), %esi
	movl	20(%r14), %edx
	movq	%rbx, %rdi
	testq	%rax, %rax
	je	LBB0_21
## %bb.20:
	callq	*%rax
	jmp	LBB0_22
LBB0_21:
	callq	_sdhci_set_power
LBB0_22:
	movq	32(%rbx), %rcx
	movq	32(%rcx), %rax
	testq	%rax, %rax
	je	LBB0_24
## %bb.23:
	movl	16(%r14), %esi
	movq	%rbx, %rdi
	callq	*%rax
	movq	32(%rbx), %rcx
LBB0_24:
	movl	12(%r14), %esi
	movq	%rbx, %rdi
	callq	*24(%rcx)
	movq	_SDHCI_HOST_CONTROL@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%rbx, %rdi
	callq	_sdhci_readb
	movl	%eax, %r12d
	movq	_SDHCI_QUIRK_NO_HISPD_BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 24(%rbx)
	jne	LBB0_29
## %bb.25:
	movl	8(%r14), %eax
	movq	_MMC_TIMING_SD_HS@GOTPCREL(%rip), %rcx
	movq	_MMC_TIMING_MMC_HS@GOTPCREL(%rip), %rdx
	movq	_MMC_TIMING_MMC_HS400@GOTPCREL(%rip), %rsi
	movq	_MMC_TIMING_MMC_HS200@GOTPCREL(%rip), %rdi
	movq	_MMC_TIMING_MMC_DDR52@GOTPCREL(%rip), %r8
	movq	_MMC_TIMING_UHS_SDR50@GOTPCREL(%rip), %r9
	movq	_MMC_TIMING_UHS_SDR104@GOTPCREL(%rip), %r10
	movq	_MMC_TIMING_UHS_DDR50@GOTPCREL(%rip), %r11
	movd	%eax, %xmm0
	movd	(%rcx), %xmm1                   ## xmm1 = mem[0],zero,zero,zero
	pinsrd	$1, (%rdx), %xmm1
	pinsrd	$2, (%rsi), %xmm1
	pinsrd	$3, (%rdi), %xmm1
	pshufd	$0, %xmm0, %xmm0                ## xmm0 = xmm0[0,0,0,0]
	movd	(%r8), %xmm2                    ## xmm2 = mem[0],zero,zero,zero
	pinsrd	$1, (%r9), %xmm2
	pinsrd	$2, (%r10), %xmm2
	pinsrd	$3, (%r11), %xmm2
	pcmpeqd	%xmm0, %xmm2
	pcmpeqd	%xmm0, %xmm1
	packssdw	%xmm2, %xmm1
	psllw	$15, %xmm1
	pmovmskb	%xmm1, %edx
	movq	_SDHCI_CTRL_HISPD@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	$43690, %edx                    ## imm = 0xAAAA
	jne	LBB0_27
## %bb.26:
	movq	_MMC_TIMING_UHS_SDR25@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %eax
	je	LBB0_27
## %bb.28:
	notl	%ecx
	andl	%ecx, %r12d
	jmp	LBB0_29
LBB0_27:
	orl	%ecx, %r12d
LBB0_29:
	movq	8(%rbx), %rax
	movq	_SDHCI_SPEC_300@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_30
## %bb.50:
	movl	(%r13), %edx
	movq	%rbx, %rdi
	movl	%r12d, %esi
	callq	_sdhci_writeb
	jmp	LBB0_51
LBB0_30:
	cmpl	$0, 44(%rbx)
	je	LBB0_31
## %bb.40:
	movq	_SDHCI_CLOCK_CONTROL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_sdhci_readw
	movq	_SDHCI_CLOCK_CARD_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r15), %edx
	movq	%rbx, %rdi
	callq	_sdhci_writew
	movl	(%r13), %edx
	movq	%rbx, %rdi
	movl	%r12d, %esi
	callq	_sdhci_writeb
	movq	32(%rbx), %rax
	movl	20(%rbx), %esi
	movq	%rbx, %rdi
	callq	*8(%rax)
	jmp	LBB0_41
LBB0_31:
	movl	(%r13), %edx
	movq	%rbx, %rdi
	movl	%r12d, %esi
	callq	_sdhci_writeb
	movq	_SDHCI_HOST_CONTROL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_sdhci_readw
	movq	_SDHCI_CTRL_DRV_TYPE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r12d
	notl	%r12d
	andl	%eax, %r12d
	movl	4(%r14), %eax
	movq	_MMC_SET_DRIVER_TYPE_A@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_33
## %bb.32:
	movq	_SDHCI_CTRL_DRV_TYPE_A@GOTPCREL(%rip), %r13
	jmp	LBB0_39
LBB0_33:
	movq	_MMC_SET_DRIVER_TYPE_B@GOTPCREL(%rip), %rcx
	movq	_SDHCI_CTRL_DRV_TYPE_B@GOTPCREL(%rip), %r13
	cmpl	(%rcx), %eax
	je	LBB0_39
## %bb.34:
	movq	_MMC_SET_DRIVER_TYPE_C@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_36
## %bb.35:
	movq	_SDHCI_CTRL_DRV_TYPE_C@GOTPCREL(%rip), %r13
	jmp	LBB0_39
LBB0_36:
	movq	_MMC_SET_DRIVER_TYPE_D@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_38
## %bb.37:
	movq	_SDHCI_CTRL_DRV_TYPE_D@GOTPCREL(%rip), %r13
	jmp	LBB0_39
LBB0_38:
	movq	%r15, %rdi
	callq	_mmc_hostname
	leaq	L_.str(%rip), %rdi
	movl	%eax, %esi
	callq	_pr_warn
LBB0_39:
	movq	_SDHCI_HOST_CONTROL2@GOTPCREL(%rip), %rax
	orl	(%r13), %r12d
	movl	(%rax), %edx
	movq	%rbx, %rdi
	movl	%r12d, %esi
	callq	_sdhci_writew
LBB0_41:
	movq	_SDHCI_CLOCK_CONTROL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_sdhci_readw
	movq	_SDHCI_CLOCK_CARD_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r15), %edx
	movq	%rbx, %rdi
	callq	_sdhci_writew
	movq	32(%rbx), %rax
	movl	8(%r14), %esi
	movq	%rbx, %rdi
	callq	*16(%rax)
	movl	8(%r14), %eax
	movl	%eax, 40(%rbx)
	movq	_SDHCI_QUIRK2_PRESET_VALUE_BROKEN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, 16(%rbx)
	jne	LBB0_49
## %bb.42:
	movq	_MMC_TIMING_UHS_SDR12@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_48
## %bb.43:
	movq	_MMC_TIMING_UHS_SDR25@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_48
## %bb.44:
	movq	_MMC_TIMING_UHS_SDR50@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_48
## %bb.45:
	movq	_MMC_TIMING_UHS_SDR104@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_48
## %bb.46:
	movq	_MMC_TIMING_UHS_DDR50@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_48
## %bb.47:
	movq	_MMC_TIMING_MMC_DDR52@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_49
LBB0_48:
	movq	%rbx, %rdi
	movl	$1, %esi
	callq	_sdhci_enable_preset_value
	movq	%rbx, %rdi
	callq	_sdhci_get_preset_value
	movq	_SDHCI_PRESET_DRV_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_SDHCI_PRESET_DRV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	movl	%eax, 4(%r14)
LBB0_49:
	movq	32(%rbx), %rax
	movl	20(%rbx), %esi
	movq	%rbx, %rdi
	callq	*8(%rax)
LBB0_51:
	movq	_SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 24(%rbx)
	je	LBB0_52
## %bb.53:
	movq	_SDHCI_RESET_CMD@GOTPCREL(%rip), %rax
	movq	_SDHCI_RESET_DATA@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_sdhci_do_reset                 ## TAILCALL
LBB0_52:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MMC_POWER_UNDEFINED,4,2        ## @MMC_POWER_UNDEFINED
	.comm	_SDHCI_DEVICE_DEAD,4,2          ## @SDHCI_DEVICE_DEAD
	.comm	_MMC_POWER_OFF,4,2              ## @MMC_POWER_OFF
	.comm	_SDHCI_SIGNAL_ENABLE,4,2        ## @SDHCI_SIGNAL_ENABLE
	.comm	_SDHCI_SPEC_300,8,3             ## @SDHCI_SPEC_300
	.comm	_MMC_POWER_UP,4,2               ## @MMC_POWER_UP
	.comm	_SDHCI_QUIRK2_PRESET_VALUE_BROKEN,4,2 ## @SDHCI_QUIRK2_PRESET_VALUE_BROKEN
	.comm	_SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,4,2 ## @SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
	.comm	_SDHCI_HOST_CONTROL,4,2         ## @SDHCI_HOST_CONTROL
	.comm	_SDHCI_QUIRK_NO_HISPD_BIT,4,2   ## @SDHCI_QUIRK_NO_HISPD_BIT
	.comm	_MMC_TIMING_SD_HS,4,2           ## @MMC_TIMING_SD_HS
	.comm	_MMC_TIMING_MMC_HS,4,2          ## @MMC_TIMING_MMC_HS
	.comm	_MMC_TIMING_MMC_HS400,4,2       ## @MMC_TIMING_MMC_HS400
	.comm	_MMC_TIMING_MMC_HS200,4,2       ## @MMC_TIMING_MMC_HS200
	.comm	_MMC_TIMING_MMC_DDR52,4,2       ## @MMC_TIMING_MMC_DDR52
	.comm	_MMC_TIMING_UHS_SDR50,4,2       ## @MMC_TIMING_UHS_SDR50
	.comm	_MMC_TIMING_UHS_SDR104,4,2      ## @MMC_TIMING_UHS_SDR104
	.comm	_MMC_TIMING_UHS_DDR50,4,2       ## @MMC_TIMING_UHS_DDR50
	.comm	_MMC_TIMING_UHS_SDR25,4,2       ## @MMC_TIMING_UHS_SDR25
	.comm	_SDHCI_CTRL_HISPD,4,2           ## @SDHCI_CTRL_HISPD
	.comm	_SDHCI_HOST_CONTROL2,4,2        ## @SDHCI_HOST_CONTROL2
	.comm	_SDHCI_CTRL_DRV_TYPE_MASK,4,2   ## @SDHCI_CTRL_DRV_TYPE_MASK
	.comm	_MMC_SET_DRIVER_TYPE_A,4,2      ## @MMC_SET_DRIVER_TYPE_A
	.comm	_SDHCI_CTRL_DRV_TYPE_A,4,2      ## @SDHCI_CTRL_DRV_TYPE_A
	.comm	_MMC_SET_DRIVER_TYPE_B,4,2      ## @MMC_SET_DRIVER_TYPE_B
	.comm	_SDHCI_CTRL_DRV_TYPE_B,4,2      ## @SDHCI_CTRL_DRV_TYPE_B
	.comm	_MMC_SET_DRIVER_TYPE_C,4,2      ## @MMC_SET_DRIVER_TYPE_C
	.comm	_SDHCI_CTRL_DRV_TYPE_C,4,2      ## @SDHCI_CTRL_DRV_TYPE_C
	.comm	_MMC_SET_DRIVER_TYPE_D,4,2      ## @MMC_SET_DRIVER_TYPE_D
	.comm	_SDHCI_CTRL_DRV_TYPE_D,4,2      ## @SDHCI_CTRL_DRV_TYPE_D
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"%s: invalid driver type, default to driver type B\n"

	.comm	_SDHCI_CLOCK_CONTROL,4,2        ## @SDHCI_CLOCK_CONTROL
	.comm	_SDHCI_CLOCK_CARD_EN,4,2        ## @SDHCI_CLOCK_CARD_EN
	.comm	_MMC_TIMING_UHS_SDR12,4,2       ## @MMC_TIMING_UHS_SDR12
	.comm	_SDHCI_PRESET_DRV_MASK,4,2      ## @SDHCI_PRESET_DRV_MASK
	.comm	_SDHCI_PRESET_DRV_SHIFT,4,2     ## @SDHCI_PRESET_DRV_SHIFT
	.comm	_SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,4,2 ## @SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS
	.comm	_SDHCI_RESET_CMD,4,2            ## @SDHCI_RESET_CMD
	.comm	_SDHCI_RESET_DATA,4,2           ## @SDHCI_RESET_DATA
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_sdhci_set_ios                  ; -- Begin function sdhci_set_ios
	.p2align	2
_sdhci_set_ios:                         ; @sdhci_set_ios
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x1
	mov	x21, x0
	bl	_mmc_priv
	ldr	w8, [x20, #16]
Lloh0:
	adrp	x9, _MMC_POWER_UNDEFINED@GOTPAGE
Lloh1:
	ldr	x9, [x9, _MMC_POWER_UNDEFINED@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	cmp	w8, w9
	b.eq	LBB0_60
; %bb.1:
	mov	x19, x0
	ldr	w9, [x0]
Lloh3:
	adrp	x10, _SDHCI_DEVICE_DEAD@GOTPAGE
Lloh4:
	ldr	x10, [x10, _SDHCI_DEVICE_DEAD@GOTPAGEOFF]
Lloh5:
	ldr	w10, [x10]
	tst	w10, w9
	b.eq	LBB0_5
; %bb.2:
	ldr	w0, [x21]
	bl	_IS_ERR
	cbnz	w0, LBB0_60
; %bb.3:
	ldr	w8, [x20, #16]
Lloh6:
	adrp	x9, _MMC_POWER_OFF@GOTPAGE
Lloh7:
	ldr	x9, [x9, _MMC_POWER_OFF@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_60
; %bb.4:
	ldr	w1, [x21]
	mov	x0, x21
	mov	w2, #0
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_mmc_regulator_set_ocr
LBB0_5:
Lloh9:
	adrp	x9, _MMC_POWER_OFF@GOTPAGE
Lloh10:
	ldr	x9, [x9, _MMC_POWER_OFF@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_7
; %bb.6:
Lloh12:
	adrp	x8, _SDHCI_SIGNAL_ENABLE@GOTPAGE
Lloh13:
	ldr	x8, [x8, _SDHCI_SIGNAL_ENABLE@GOTPAGEOFF]
Lloh14:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w1, #0
	bl	_sdhci_writel
	mov	x0, x19
	bl	_sdhci_reinit
LBB0_7:
	ldr	x8, [x19, #8]
Lloh15:
	adrp	x23, _SDHCI_SPEC_300@GOTPAGE
Lloh16:
	ldr	x23, [x23, _SDHCI_SPEC_300@GOTPAGEOFF]
	ldr	x9, [x23]
	cmp	x8, x9
	b.lt	LBB0_11
; %bb.8:
	ldr	w8, [x20, #16]
Lloh17:
	adrp	x9, _MMC_POWER_UP@GOTPAGE
Lloh18:
	ldr	x9, [x9, _MMC_POWER_UP@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_11
; %bb.9:
	ldr	w8, [x19, #16]
Lloh20:
	adrp	x9, _SDHCI_QUIRK2_PRESET_VALUE_BROKEN@GOTPAGE
Lloh21:
	ldr	x9, [x9, _SDHCI_QUIRK2_PRESET_VALUE_BROKEN@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_11
; %bb.10:
	mov	x0, x19
	mov	w1, #0
	bl	_sdhci_enable_preset_value
LBB0_11:
	ldr	w1, [x20]
	cbz	w1, LBB0_13
; %bb.12:
	ldr	w8, [x19, #20]
	cmp	w1, w8
	b.eq	LBB0_18
LBB0_13:
	ldr	x8, [x19, #32]
	ldr	x8, [x8, #8]
	mov	x0, x19
	blr	x8
	ldr	w9, [x20]
	str	w9, [x19, #20]
	ldr	w8, [x19, #24]
Lloh23:
	adrp	x10, _SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK@GOTPAGE
Lloh24:
	ldr	x10, [x10, _SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK@GOTPAGEOFF]
Lloh25:
	ldr	w10, [x10]
	and	w8, w10, w8
	cmp	w8, #0
	ccmp	w9, #0, #4, ne
	b.eq	LBB0_18
; %bb.14:
	ldr	x8, [x19, #48]
	ldr	w10, [x8]
	cmp	w10, #0
	csel	w9, w9, w10, eq
	mov	w10, #19923
	movk	w10, #4194, lsl #16
	smull	x9, w9, w10
	lsr	x10, x9, #32
	lsr	x9, x9, #63
	add	w9, w9, w10, asr #6
	str	w9, [x19, #28]
	ldr	x10, [x19, #32]
	ldr	x10, [x10]
	cbz	x10, LBB0_16
; %bb.15:
	mov	x0, x19
	blr	x10
	ldr	x8, [x19, #48]
	ldr	w9, [x19, #28]
	b	LBB0_17
LBB0_16:
	mov	w0, #134217728
LBB0_17:
	sdiv	w9, w0, w9
	str	w9, [x8, #4]
LBB0_18:
	ldr	x8, [x19, #32]
	ldr	x8, [x8, #40]
	ldp	w1, w2, [x20, #16]
	mov	x0, x19
	cbz	x8, LBB0_20
; %bb.19:
	blr	x8
	b	LBB0_21
LBB0_20:
	bl	_sdhci_set_power
LBB0_21:
	ldr	x8, [x19, #32]
	ldr	x9, [x8, #32]
	cbz	x9, LBB0_23
; %bb.22:
	ldr	w1, [x20, #16]
	mov	x0, x19
	blr	x9
	ldr	x8, [x19, #32]
LBB0_23:
	ldr	x8, [x8, #24]
	ldr	w1, [x20, #12]
	mov	x0, x19
	blr	x8
Lloh26:
	adrp	x25, _SDHCI_HOST_CONTROL@GOTPAGE
Lloh27:
	ldr	x25, [x25, _SDHCI_HOST_CONTROL@GOTPAGEOFF]
	ldr	w1, [x25]
	mov	x0, x19
	bl	_sdhci_readb
	mov	x22, x0
	ldr	w8, [x19, #24]
Lloh28:
	adrp	x9, _SDHCI_QUIRK_NO_HISPD_BIT@GOTPAGE
Lloh29:
	ldr	x9, [x9, _SDHCI_QUIRK_NO_HISPD_BIT@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_35
; %bb.24:
Lloh31:
	adrp	x8, _MMC_TIMING_SD_HS@GOTPAGE
Lloh32:
	ldr	x8, [x8, _MMC_TIMING_SD_HS@GOTPAGEOFF]
	ldr	w9, [x20, #8]
Lloh33:
	ldr	w10, [x8]
Lloh34:
	adrp	x8, _SDHCI_CTRL_HISPD@GOTPAGE
Lloh35:
	ldr	x8, [x8, _SDHCI_CTRL_HISPD@GOTPAGEOFF]
Lloh36:
	ldr	w8, [x8]
	cmp	w9, w10
	b.eq	LBB0_34
; %bb.25:
Lloh37:
	adrp	x10, _MMC_TIMING_MMC_HS@GOTPAGE
Lloh38:
	ldr	x10, [x10, _MMC_TIMING_MMC_HS@GOTPAGEOFF]
Lloh39:
	ldr	w10, [x10]
	cmp	w9, w10
	b.eq	LBB0_34
; %bb.26:
Lloh40:
	adrp	x10, _MMC_TIMING_MMC_HS400@GOTPAGE
Lloh41:
	ldr	x10, [x10, _MMC_TIMING_MMC_HS400@GOTPAGEOFF]
Lloh42:
	ldr	w10, [x10]
	cmp	w9, w10
	b.eq	LBB0_34
; %bb.27:
Lloh43:
	adrp	x10, _MMC_TIMING_MMC_HS200@GOTPAGE
Lloh44:
	ldr	x10, [x10, _MMC_TIMING_MMC_HS200@GOTPAGEOFF]
Lloh45:
	ldr	w10, [x10]
	cmp	w9, w10
	b.eq	LBB0_34
; %bb.28:
Lloh46:
	adrp	x10, _MMC_TIMING_MMC_DDR52@GOTPAGE
Lloh47:
	ldr	x10, [x10, _MMC_TIMING_MMC_DDR52@GOTPAGEOFF]
Lloh48:
	ldr	w10, [x10]
	cmp	w9, w10
	b.eq	LBB0_34
; %bb.29:
Lloh49:
	adrp	x10, _MMC_TIMING_UHS_SDR50@GOTPAGE
Lloh50:
	ldr	x10, [x10, _MMC_TIMING_UHS_SDR50@GOTPAGEOFF]
Lloh51:
	ldr	w10, [x10]
	cmp	w9, w10
	b.eq	LBB0_34
; %bb.30:
Lloh52:
	adrp	x10, _MMC_TIMING_UHS_SDR104@GOTPAGE
Lloh53:
	ldr	x10, [x10, _MMC_TIMING_UHS_SDR104@GOTPAGEOFF]
Lloh54:
	ldr	w10, [x10]
	cmp	w9, w10
	b.eq	LBB0_34
; %bb.31:
Lloh55:
	adrp	x10, _MMC_TIMING_UHS_DDR50@GOTPAGE
Lloh56:
	ldr	x10, [x10, _MMC_TIMING_UHS_DDR50@GOTPAGEOFF]
Lloh57:
	ldr	w10, [x10]
	cmp	w9, w10
	b.eq	LBB0_34
; %bb.32:
Lloh58:
	adrp	x10, _MMC_TIMING_UHS_SDR25@GOTPAGE
Lloh59:
	ldr	x10, [x10, _MMC_TIMING_UHS_SDR25@GOTPAGEOFF]
Lloh60:
	ldr	w10, [x10]
	cmp	w9, w10
	b.eq	LBB0_34
; %bb.33:
	bic	w22, w22, w8
	b	LBB0_35
LBB0_34:
	orr	w22, w8, w22
LBB0_35:
	ldr	x8, [x19, #8]
	ldr	x9, [x23]
	cmp	x8, x9
	b.ge	LBB0_37
; %bb.36:
	ldr	w2, [x25]
	mov	x0, x19
	mov	x1, x22
	bl	_sdhci_writeb
	b	LBB0_58
LBB0_37:
	ldr	w8, [x19, #44]
Lloh61:
	adrp	x23, _SDHCI_CLOCK_CONTROL@GOTPAGE
Lloh62:
	ldr	x23, [x23, _SDHCI_CLOCK_CONTROL@GOTPAGEOFF]
Lloh63:
	adrp	x24, _SDHCI_CLOCK_CARD_EN@GOTPAGE
Lloh64:
	ldr	x24, [x24, _SDHCI_CLOCK_CARD_EN@GOTPAGEOFF]
	cbz	w8, LBB0_39
; %bb.38:
	ldr	w1, [x23]
	mov	x0, x19
	bl	_sdhci_readw
	ldr	w8, [x24]
	bic	w1, w0, w8
	ldr	w2, [x23]
	mov	x0, x19
	bl	_sdhci_writew
	ldr	w2, [x25]
	mov	x0, x19
	mov	x1, x22
	bl	_sdhci_writeb
	ldr	x8, [x19, #32]
	ldr	x8, [x8, #8]
	ldr	w1, [x19, #20]
	mov	x0, x19
	blr	x8
	b	LBB0_49
LBB0_39:
	ldr	w2, [x25]
	mov	x0, x19
	mov	x1, x22
	bl	_sdhci_writeb
Lloh65:
	adrp	x22, _SDHCI_HOST_CONTROL2@GOTPAGE
Lloh66:
	ldr	x22, [x22, _SDHCI_HOST_CONTROL2@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x19
	bl	_sdhci_readw
Lloh67:
	adrp	x8, _SDHCI_CTRL_DRV_TYPE_MASK@GOTPAGE
Lloh68:
	ldr	x8, [x8, _SDHCI_CTRL_DRV_TYPE_MASK@GOTPAGEOFF]
Lloh69:
	ldr	w8, [x8]
	bic	w25, w0, w8
	ldr	w8, [x20, #4]
Lloh70:
	adrp	x9, _MMC_SET_DRIVER_TYPE_A@GOTPAGE
Lloh71:
	ldr	x9, [x9, _MMC_SET_DRIVER_TYPE_A@GOTPAGEOFF]
Lloh72:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_41
; %bb.40:
Lloh73:
	adrp	x8, _SDHCI_CTRL_DRV_TYPE_A@GOTPAGE
Lloh74:
	ldr	x8, [x8, _SDHCI_CTRL_DRV_TYPE_A@GOTPAGEOFF]
	b	LBB0_48
LBB0_41:
Lloh75:
	adrp	x9, _MMC_SET_DRIVER_TYPE_B@GOTPAGE
Lloh76:
	ldr	x9, [x9, _MMC_SET_DRIVER_TYPE_B@GOTPAGEOFF]
Lloh77:
	ldr	w9, [x9]
	cmp	w8, w9
	b.eq	LBB0_47
; %bb.42:
Lloh78:
	adrp	x9, _MMC_SET_DRIVER_TYPE_C@GOTPAGE
Lloh79:
	ldr	x9, [x9, _MMC_SET_DRIVER_TYPE_C@GOTPAGEOFF]
Lloh80:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_44
; %bb.43:
Lloh81:
	adrp	x8, _SDHCI_CTRL_DRV_TYPE_C@GOTPAGE
Lloh82:
	ldr	x8, [x8, _SDHCI_CTRL_DRV_TYPE_C@GOTPAGEOFF]
	b	LBB0_48
LBB0_44:
Lloh83:
	adrp	x9, _MMC_SET_DRIVER_TYPE_D@GOTPAGE
Lloh84:
	ldr	x9, [x9, _MMC_SET_DRIVER_TYPE_D@GOTPAGEOFF]
Lloh85:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_46
; %bb.45:
Lloh86:
	adrp	x8, _SDHCI_CTRL_DRV_TYPE_D@GOTPAGE
Lloh87:
	ldr	x8, [x8, _SDHCI_CTRL_DRV_TYPE_D@GOTPAGEOFF]
	b	LBB0_48
LBB0_46:
	mov	x0, x21
	bl	_mmc_hostname
	mov	x1, x0
Lloh88:
	adrp	x0, l_.str@PAGE
Lloh89:
	add	x0, x0, l_.str@PAGEOFF
	bl	_pr_warn
LBB0_47:
Lloh90:
	adrp	x8, _SDHCI_CTRL_DRV_TYPE_B@GOTPAGE
Lloh91:
	ldr	x8, [x8, _SDHCI_CTRL_DRV_TYPE_B@GOTPAGEOFF]
LBB0_48:
	ldr	w8, [x8]
	orr	w1, w8, w25
	ldr	w2, [x22]
	mov	x0, x19
	bl	_sdhci_writew
LBB0_49:
	ldr	w1, [x23]
	mov	x0, x19
	bl	_sdhci_readw
	ldr	w8, [x24]
	bic	w1, w0, w8
	ldr	w2, [x23]
	mov	x0, x19
	bl	_sdhci_writew
	ldr	x8, [x19, #32]
	ldr	x8, [x8, #16]
	ldr	w1, [x20, #8]
	mov	x0, x19
	blr	x8
	ldr	w8, [x20, #8]
	str	w8, [x19, #40]
	ldr	w9, [x19, #16]
Lloh92:
	adrp	x10, _SDHCI_QUIRK2_PRESET_VALUE_BROKEN@GOTPAGE
Lloh93:
	ldr	x10, [x10, _SDHCI_QUIRK2_PRESET_VALUE_BROKEN@GOTPAGEOFF]
Lloh94:
	ldr	w10, [x10]
	tst	w10, w9
	b.ne	LBB0_57
; %bb.50:
Lloh95:
	adrp	x9, _MMC_TIMING_UHS_SDR12@GOTPAGE
Lloh96:
	ldr	x9, [x9, _MMC_TIMING_UHS_SDR12@GOTPAGEOFF]
Lloh97:
	ldr	w9, [x9]
	cmp	w8, w9
	b.eq	LBB0_56
; %bb.51:
Lloh98:
	adrp	x9, _MMC_TIMING_UHS_SDR25@GOTPAGE
Lloh99:
	ldr	x9, [x9, _MMC_TIMING_UHS_SDR25@GOTPAGEOFF]
Lloh100:
	ldr	w9, [x9]
	cmp	w8, w9
	b.eq	LBB0_56
; %bb.52:
Lloh101:
	adrp	x9, _MMC_TIMING_UHS_SDR50@GOTPAGE
Lloh102:
	ldr	x9, [x9, _MMC_TIMING_UHS_SDR50@GOTPAGEOFF]
Lloh103:
	ldr	w9, [x9]
	cmp	w8, w9
	b.eq	LBB0_56
; %bb.53:
Lloh104:
	adrp	x9, _MMC_TIMING_UHS_SDR104@GOTPAGE
Lloh105:
	ldr	x9, [x9, _MMC_TIMING_UHS_SDR104@GOTPAGEOFF]
Lloh106:
	ldr	w9, [x9]
	cmp	w8, w9
	b.eq	LBB0_56
; %bb.54:
Lloh107:
	adrp	x9, _MMC_TIMING_UHS_DDR50@GOTPAGE
Lloh108:
	ldr	x9, [x9, _MMC_TIMING_UHS_DDR50@GOTPAGEOFF]
Lloh109:
	ldr	w9, [x9]
	cmp	w8, w9
	b.eq	LBB0_56
; %bb.55:
Lloh110:
	adrp	x9, _MMC_TIMING_MMC_DDR52@GOTPAGE
Lloh111:
	ldr	x9, [x9, _MMC_TIMING_MMC_DDR52@GOTPAGEOFF]
Lloh112:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_57
LBB0_56:
	mov	x0, x19
	mov	w1, #1
	bl	_sdhci_enable_preset_value
	mov	x0, x19
	bl	_sdhci_get_preset_value
Lloh113:
	adrp	x8, _SDHCI_PRESET_DRV_MASK@GOTPAGE
Lloh114:
	ldr	x8, [x8, _SDHCI_PRESET_DRV_MASK@GOTPAGEOFF]
Lloh115:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh116:
	adrp	x9, _SDHCI_PRESET_DRV_SHIFT@GOTPAGE
Lloh117:
	ldr	x9, [x9, _SDHCI_PRESET_DRV_SHIFT@GOTPAGEOFF]
Lloh118:
	ldr	w9, [x9]
	asr	w8, w8, w9
	str	w8, [x20, #4]
LBB0_57:
	ldr	x8, [x19, #32]
	ldr	x8, [x8, #8]
	ldr	w1, [x19, #20]
	mov	x0, x19
	blr	x8
LBB0_58:
	ldr	w8, [x19, #24]
Lloh119:
	adrp	x9, _SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS@GOTPAGE
Lloh120:
	ldr	x9, [x9, _SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS@GOTPAGEOFF]
Lloh121:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_60
; %bb.59:
Lloh122:
	adrp	x8, _SDHCI_RESET_CMD@GOTPAGE
Lloh123:
	ldr	x8, [x8, _SDHCI_RESET_CMD@GOTPAGEOFF]
Lloh124:
	ldr	w8, [x8]
Lloh125:
	adrp	x9, _SDHCI_RESET_DATA@GOTPAGE
Lloh126:
	ldr	x9, [x9, _SDHCI_RESET_DATA@GOTPAGEOFF]
Lloh127:
	ldr	w9, [x9]
	orr	w1, w9, w8
	mov	x0, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_sdhci_do_reset
LBB0_60:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGot	Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGot	Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGot	Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGot	Lloh86, Lloh87
	.loh AdrpAdd	Lloh88, Lloh89
	.loh AdrpLdrGot	Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.cfi_endproc
                                        ; -- End function
	.comm	_MMC_POWER_UNDEFINED,4,2        ; @MMC_POWER_UNDEFINED
	.comm	_SDHCI_DEVICE_DEAD,4,2          ; @SDHCI_DEVICE_DEAD
	.comm	_MMC_POWER_OFF,4,2              ; @MMC_POWER_OFF
	.comm	_SDHCI_SIGNAL_ENABLE,4,2        ; @SDHCI_SIGNAL_ENABLE
	.comm	_SDHCI_SPEC_300,8,3             ; @SDHCI_SPEC_300
	.comm	_MMC_POWER_UP,4,2               ; @MMC_POWER_UP
	.comm	_SDHCI_QUIRK2_PRESET_VALUE_BROKEN,4,2 ; @SDHCI_QUIRK2_PRESET_VALUE_BROKEN
	.comm	_SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,4,2 ; @SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
	.comm	_SDHCI_HOST_CONTROL,4,2         ; @SDHCI_HOST_CONTROL
	.comm	_SDHCI_QUIRK_NO_HISPD_BIT,4,2   ; @SDHCI_QUIRK_NO_HISPD_BIT
	.comm	_MMC_TIMING_SD_HS,4,2           ; @MMC_TIMING_SD_HS
	.comm	_MMC_TIMING_MMC_HS,4,2          ; @MMC_TIMING_MMC_HS
	.comm	_MMC_TIMING_MMC_HS400,4,2       ; @MMC_TIMING_MMC_HS400
	.comm	_MMC_TIMING_MMC_HS200,4,2       ; @MMC_TIMING_MMC_HS200
	.comm	_MMC_TIMING_MMC_DDR52,4,2       ; @MMC_TIMING_MMC_DDR52
	.comm	_MMC_TIMING_UHS_SDR50,4,2       ; @MMC_TIMING_UHS_SDR50
	.comm	_MMC_TIMING_UHS_SDR104,4,2      ; @MMC_TIMING_UHS_SDR104
	.comm	_MMC_TIMING_UHS_DDR50,4,2       ; @MMC_TIMING_UHS_DDR50
	.comm	_MMC_TIMING_UHS_SDR25,4,2       ; @MMC_TIMING_UHS_SDR25
	.comm	_SDHCI_CTRL_HISPD,4,2           ; @SDHCI_CTRL_HISPD
	.comm	_SDHCI_HOST_CONTROL2,4,2        ; @SDHCI_HOST_CONTROL2
	.comm	_SDHCI_CTRL_DRV_TYPE_MASK,4,2   ; @SDHCI_CTRL_DRV_TYPE_MASK
	.comm	_MMC_SET_DRIVER_TYPE_A,4,2      ; @MMC_SET_DRIVER_TYPE_A
	.comm	_SDHCI_CTRL_DRV_TYPE_A,4,2      ; @SDHCI_CTRL_DRV_TYPE_A
	.comm	_MMC_SET_DRIVER_TYPE_B,4,2      ; @MMC_SET_DRIVER_TYPE_B
	.comm	_SDHCI_CTRL_DRV_TYPE_B,4,2      ; @SDHCI_CTRL_DRV_TYPE_B
	.comm	_MMC_SET_DRIVER_TYPE_C,4,2      ; @MMC_SET_DRIVER_TYPE_C
	.comm	_SDHCI_CTRL_DRV_TYPE_C,4,2      ; @SDHCI_CTRL_DRV_TYPE_C
	.comm	_MMC_SET_DRIVER_TYPE_D,4,2      ; @MMC_SET_DRIVER_TYPE_D
	.comm	_SDHCI_CTRL_DRV_TYPE_D,4,2      ; @SDHCI_CTRL_DRV_TYPE_D
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"%s: invalid driver type, default to driver type B\n"

	.comm	_SDHCI_CLOCK_CONTROL,4,2        ; @SDHCI_CLOCK_CONTROL
	.comm	_SDHCI_CLOCK_CARD_EN,4,2        ; @SDHCI_CLOCK_CARD_EN
	.comm	_MMC_TIMING_UHS_SDR12,4,2       ; @MMC_TIMING_UHS_SDR12
	.comm	_SDHCI_PRESET_DRV_MASK,4,2      ; @SDHCI_PRESET_DRV_MASK
	.comm	_SDHCI_PRESET_DRV_SHIFT,4,2     ; @SDHCI_PRESET_DRV_SHIFT
	.comm	_SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,4,2 ; @SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS
	.comm	_SDHCI_RESET_CMD,4,2            ; @SDHCI_RESET_CMD
	.comm	_SDHCI_RESET_DATA,4,2           ; @SDHCI_RESET_DATA
.subsections_via_symbols
