	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mmci_set_clkreg
_mmci_set_clkreg:                       ## @mmci_set_clkreg
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	16(%rdi), %r15
	movl	(%r15), %ecx
	movl	$0, (%rdi)
	xorl	%ebx, %ebx
	testl	%esi, %esi
	je	LBB0_1
## %bb.2:
	cmpq	$0, 24(%r15)
	movl	4(%r14), %edi
	jne	LBB0_11
## %bb.3:
	cmpl	%esi, %edi
	jbe	LBB0_4
## %bb.7:
	cmpq	$0, 16(%r15)
	je	LBB0_9
## %bb.8:
	callq	_DIV_ROUND_UP
	cmpl	$257, %eax                      ## imm = 0x101
	movl	$257, %esi                      ## imm = 0x101
	cmovll	%eax, %esi
	leal	-2(%rsi), %ecx
	movl	4(%r14), %eax
	cltd
	idivl	%esi
	jmp	LBB0_10
LBB0_1:
	xorl	%edi, %edi
	jmp	LBB0_12
LBB0_4:
	movq	_MCI_CLK_BYPASS@GOTPCREL(%rip), %rax
	xorl	%ecx, %ecx
	cmpq	$0, 16(%r15)
	je	LBB0_6
## %bb.5:
	movq	_MCI_ST_UX500_NEG_EDGE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_6:
	orl	(%rax), %ecx
	jmp	LBB0_11
LBB0_9:
	addl	%esi, %esi
	movl	%edi, %eax
	xorl	%edx, %edx
	divl	%esi
	decl	%eax
	cmpl	$255, %eax
	movl	$255, %ecx
	cmovll	%eax, %ecx
	leal	(%rcx,%rcx), %esi
	addl	$2, %esi
	movl	%edi, %eax
	cltd
	idivl	%esi
LBB0_10:
	movl	%eax, %edi
LBB0_11:
	movl	%edi, (%r14)
	orl	4(%r15), %ecx
	movq	_MCI_CLK_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
LBB0_12:
	movq	8(%r14), %rax
	movl	%edi, (%rax)
	movq	8(%rax), %rdx
	movq	_MMC_BUS_WIDTH_4@GOTPCREL(%rip), %rsi
	cmpq	(%rsi), %rdx
	jne	LBB0_14
## %bb.13:
	movq	_MCI_4BIT_BUS@GOTPCREL(%rip), %rsi
	movl	(%rsi), %ebx
LBB0_14:
	orl	%ecx, %ebx
	movq	_MMC_BUS_WIDTH_8@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rdx
	jne	LBB0_16
## %bb.15:
	orl	8(%r15), %ebx
LBB0_16:
	movq	16(%rax), %rax
	movq	_MMC_TIMING_UHS_DDR50@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_18
## %bb.17:
	movq	_MMC_TIMING_MMC_DDR52@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_19
LBB0_18:
	orl	12(%r15), %ebx
LBB0_19:
	movq	%r14, %rdi
	movl	%ebx, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_mmci_write_clkreg              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_MCI_CLK_BYPASS,4,2             ## @MCI_CLK_BYPASS
	.comm	_MCI_ST_UX500_NEG_EDGE,4,2      ## @MCI_ST_UX500_NEG_EDGE
	.comm	_MCI_CLK_ENABLE,4,2             ## @MCI_CLK_ENABLE
	.comm	_MMC_BUS_WIDTH_4,8,3            ## @MMC_BUS_WIDTH_4
	.comm	_MCI_4BIT_BUS,4,2               ## @MCI_4BIT_BUS
	.comm	_MMC_BUS_WIDTH_8,8,3            ## @MMC_BUS_WIDTH_8
	.comm	_MMC_TIMING_UHS_DDR50,8,3       ## @MMC_TIMING_UHS_DDR50
	.comm	_MMC_TIMING_MMC_DDR52,8,3       ## @MMC_TIMING_MMC_DDR52
	.no_dead_strip	_mmci_set_clkreg
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mmci_set_clkreg
_mmci_set_clkreg:                       ; @mmci_set_clkreg
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	x20, [x0, #16]
	ldr	w8, [x20]
	str	wzr, [x0]
	cbz	w1, LBB0_5
; %bb.1:
	ldr	x9, [x20, #24]
	ldr	w0, [x19, #4]
	cbnz	x9, LBB0_8
; %bb.2:
	cmp	w0, w1
	b.ls	LBB0_6
; %bb.3:
	ldr	x8, [x20, #16]
	cbz	x8, LBB0_7
; %bb.4:
	bl	_DIV_ROUND_UP
	mov	w8, #257
	cmp	w0, #257
	csel	w9, w0, w8, lt
	sub	w8, w9, #2
	ldr	w10, [x19, #4]
	sdiv	w0, w10, w9
	b	LBB0_8
LBB0_5:
	mov	w0, #0
	b	LBB0_9
LBB0_6:
Lloh0:
	adrp	x8, _MCI_CLK_BYPASS@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MCI_CLK_BYPASS@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	ldr	x9, [x20, #16]
Lloh3:
	adrp	x10, _MCI_ST_UX500_NEG_EDGE@GOTPAGE
Lloh4:
	ldr	x10, [x10, _MCI_ST_UX500_NEG_EDGE@GOTPAGEOFF]
Lloh5:
	ldr	w10, [x10]
	cmp	x9, #0
	csel	w9, wzr, w10, eq
	orr	w8, w9, w8
	b	LBB0_8
LBB0_7:
	lsl	w8, w1, #1
	udiv	w8, w0, w8
	sub	w8, w8, #1
	mov	w9, #255
	cmp	w8, #255
	csel	w8, w8, w9, lt
	lsl	w9, w8, #1
	add	w9, w9, #2
	sdiv	w0, w0, w9
LBB0_8:
	str	w0, [x19]
	ldr	w9, [x20, #4]
	orr	w8, w9, w8
Lloh6:
	adrp	x9, _MCI_CLK_ENABLE@GOTPAGE
Lloh7:
	ldr	x9, [x9, _MCI_CLK_ENABLE@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	orr	w8, w8, w9
LBB0_9:
	ldr	x9, [x19, #8]
	str	w0, [x9]
Lloh9:
	adrp	x10, _MMC_BUS_WIDTH_4@GOTPAGE
Lloh10:
	ldr	x10, [x10, _MMC_BUS_WIDTH_4@GOTPAGEOFF]
	ldr	x11, [x9, #8]
Lloh11:
	ldr	x10, [x10]
Lloh12:
	adrp	x12, _MCI_4BIT_BUS@GOTPAGE
Lloh13:
	ldr	x12, [x12, _MCI_4BIT_BUS@GOTPAGEOFF]
Lloh14:
	ldr	w12, [x12]
	cmp	x11, x10
	csel	w10, w12, wzr, eq
	orr	w1, w10, w8
Lloh15:
	adrp	x8, _MMC_BUS_WIDTH_8@GOTPAGE
Lloh16:
	ldr	x8, [x8, _MMC_BUS_WIDTH_8@GOTPAGEOFF]
Lloh17:
	ldr	x8, [x8]
	cmp	x11, x8
	b.ne	LBB0_11
; %bb.10:
	ldr	w8, [x20, #8]
	orr	w1, w8, w1
LBB0_11:
	ldr	x8, [x9, #16]
Lloh18:
	adrp	x9, _MMC_TIMING_UHS_DDR50@GOTPAGE
Lloh19:
	ldr	x9, [x9, _MMC_TIMING_UHS_DDR50@GOTPAGEOFF]
Lloh20:
	ldr	x9, [x9]
Lloh21:
	adrp	x10, _MMC_TIMING_MMC_DDR52@GOTPAGE
Lloh22:
	ldr	x10, [x10, _MMC_TIMING_MMC_DDR52@GOTPAGEOFF]
Lloh23:
	ldr	x10, [x10]
	cmp	x8, x9
	ccmp	x8, x10, #4, ne
	b.ne	LBB0_13
; %bb.12:
	ldr	w8, [x20, #12]
	orr	w1, w8, w1
LBB0_13:
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_mmci_write_clkreg
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.cfi_endproc
                                        ; -- End function
	.comm	_MCI_CLK_BYPASS,4,2             ; @MCI_CLK_BYPASS
	.comm	_MCI_ST_UX500_NEG_EDGE,4,2      ; @MCI_ST_UX500_NEG_EDGE
	.comm	_MCI_CLK_ENABLE,4,2             ; @MCI_CLK_ENABLE
	.comm	_MMC_BUS_WIDTH_4,8,3            ; @MMC_BUS_WIDTH_4
	.comm	_MCI_4BIT_BUS,4,2               ; @MCI_4BIT_BUS
	.comm	_MMC_BUS_WIDTH_8,8,3            ; @MMC_BUS_WIDTH_8
	.comm	_MMC_TIMING_UHS_DDR50,8,3       ; @MMC_TIMING_UHS_DDR50
	.comm	_MMC_TIMING_MMC_DDR52,8,3       ; @MMC_TIMING_MMC_DDR52
	.no_dead_strip	_mmci_set_clkreg
.subsections_via_symbols
