	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function xgene_enet_cle_bypass
_xgene_enet_cle_bypass:                 ## @xgene_enet_cle_bypass
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %r12d
	movl	%edx, %r13d
	movl	%esi, %ebx
	movq	%rdi, %r14
	movq	_MAC_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	8(%rdi), %rax
	movq	_XGENE_ENET1@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	movq	_XCLE_BYPASS_REG0_ADDR@GOTPCREL(%rip), %rax
	cmoveq	_CLE_BYPASS_REG0_0_ADDR@GOTPCREL(%rip), %rax
	movq	_XCLE_BYPASS_REG1_ADDR@GOTPCREL(%rip), %rcx
	cmoveq	_CLE_BYPASS_REG1_0_ADDR@GOTPCREL(%rip), %rcx
	imull	(%rdi), %r15d
	movq	_CFG_CLE_BYPASS_EN0@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movl	(%rax), %esi
	addl	%r15d, %esi
	addl	(%rcx), %r15d
	callq	_xgene_enet_wr_csr
	movl	%r13d, %edi
	callq	_xgene_enet_get_fpsel
	movl	%eax, %r13d
	movl	%r12d, %edi
	callq	_xgene_enet_get_fpsel
	movl	%eax, %r12d
	movl	%ebx, %edi
	callq	_CFG_CLE_DSTQID0
	movl	%eax, %ebx
	movl	%r13d, %edi
	callq	_CFG_CLE_FPSEL0
	orl	%eax, %ebx
	movl	%r12d, %edi
	callq	_CFG_CLE_NXTFPSEL0
	orl	%eax, %ebx
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_xgene_enet_wr_csr              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_MAC_OFFSET,4,2                 ## @MAC_OFFSET
	.comm	_XGENE_ENET1,8,3                ## @XGENE_ENET1
	.comm	_CLE_BYPASS_REG0_0_ADDR,4,2     ## @CLE_BYPASS_REG0_0_ADDR
	.comm	_CLE_BYPASS_REG1_0_ADDR,4,2     ## @CLE_BYPASS_REG1_0_ADDR
	.comm	_XCLE_BYPASS_REG0_ADDR,4,2      ## @XCLE_BYPASS_REG0_ADDR
	.comm	_XCLE_BYPASS_REG1_ADDR,4,2      ## @XCLE_BYPASS_REG1_ADDR
	.comm	_CFG_CLE_BYPASS_EN0,4,2         ## @CFG_CLE_BYPASS_EN0
	.no_dead_strip	_xgene_enet_cle_bypass
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function xgene_enet_cle_bypass
_xgene_enet_cle_bypass:                 ; @xgene_enet_cle_bypass
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x3
	mov	x20, x2
	mov	x21, x1
	mov	x22, x0
Lloh0:
	adrp	x8, _MAC_OFFSET@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MAC_OFFSET@GOTPAGEOFF]
	ldr	w9, [x0]
Lloh2:
	ldr	w8, [x8]
	ldr	x10, [x0, #8]
Lloh3:
	adrp	x11, _XGENE_ENET1@GOTPAGE
Lloh4:
	ldr	x11, [x11, _XGENE_ENET1@GOTPAGEOFF]
Lloh5:
	ldr	x11, [x11]
Lloh6:
	adrp	x12, _CLE_BYPASS_REG0_0_ADDR@GOTPAGE
Lloh7:
	ldr	x12, [x12, _CLE_BYPASS_REG0_0_ADDR@GOTPAGEOFF]
Lloh8:
	adrp	x13, _XCLE_BYPASS_REG0_ADDR@GOTPAGE
Lloh9:
	ldr	x13, [x13, _XCLE_BYPASS_REG0_ADDR@GOTPAGEOFF]
	cmp	x10, x11
	csel	x10, x12, x13, eq
	ldr	w10, [x10]
Lloh10:
	adrp	x11, _CLE_BYPASS_REG1_0_ADDR@GOTPAGE
Lloh11:
	ldr	x11, [x11, _CLE_BYPASS_REG1_0_ADDR@GOTPAGEOFF]
Lloh12:
	adrp	x12, _XCLE_BYPASS_REG1_ADDR@GOTPAGE
Lloh13:
	ldr	x12, [x12, _XCLE_BYPASS_REG1_ADDR@GOTPAGEOFF]
	csel	x11, x11, x12, eq
	ldr	w23, [x11]
	mul	w24, w8, w9
Lloh14:
	adrp	x8, _CFG_CLE_BYPASS_EN0@GOTPAGE
Lloh15:
	ldr	x8, [x8, _CFG_CLE_BYPASS_EN0@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	add	w1, w10, w24
	bl	_xgene_enet_wr_csr
	mov	x0, x20
	bl	_xgene_enet_get_fpsel
	mov	x20, x0
	mov	x0, x19
	bl	_xgene_enet_get_fpsel
	mov	x19, x0
	mov	x0, x21
	bl	_CFG_CLE_DSTQID0
	mov	x21, x0
	mov	x0, x20
	bl	_CFG_CLE_FPSEL0
	orr	w20, w0, w21
	mov	x0, x19
	bl	_CFG_CLE_NXTFPSEL0
	orr	w2, w20, w0
	add	w1, w23, w24
	mov	x0, x22
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_xgene_enet_wr_csr
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_MAC_OFFSET,4,2                 ; @MAC_OFFSET
	.comm	_XGENE_ENET1,8,3                ; @XGENE_ENET1
	.comm	_CLE_BYPASS_REG0_0_ADDR,4,2     ; @CLE_BYPASS_REG0_0_ADDR
	.comm	_CLE_BYPASS_REG1_0_ADDR,4,2     ; @CLE_BYPASS_REG1_0_ADDR
	.comm	_XCLE_BYPASS_REG0_ADDR,4,2      ; @XCLE_BYPASS_REG0_ADDR
	.comm	_XCLE_BYPASS_REG1_ADDR,4,2      ; @XCLE_BYPASS_REG1_ADDR
	.comm	_CFG_CLE_BYPASS_EN0,4,2         ; @CFG_CLE_BYPASS_EN0
	.no_dead_strip	_xgene_enet_cle_bypass
.subsections_via_symbols
