	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function sdhci_omap_config_iodelay_pinctrl_state
_sdhci_omap_config_iodelay_pinctrl_state: ## @sdhci_omap_config_iodelay_pinctrl_state
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_SDHCI_OMAP_REQUIRE_IODELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	xorl	%r14d, %r14d
	testl	%eax, (%rdi)
	je	LBB0_28
## %bb.1:
	movq	%rdi, %r13
	movq	24(%rdi), %rbx
	movq	32(%rdi), %rax
	movq	(%rax), %r12
	movq	_MMC_TIMING_MMC_HS200@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	incl	%esi
	movq	_GFP_KERNEL@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	$8, %edx
	callq	_devm_kcalloc
	testq	%rax, %rax
	je	LBB0_2
## %bb.3:
	movq	%rax, %r15
	movq	24(%r13), %rdi
	callq	_devm_pinctrl_get
	movq	%rax, 16(%r13)
	movq	%rax, %rdi
	callq	_IS_ERR
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	leaq	L_.str(%rip), %rsi
	movq	%rbx, %rdi
	callq	_dev_err
	movq	16(%r13), %rdi
	jmp	LBB0_7
LBB0_2:
	movq	_ENOMEM@GOTPCREL(%rip), %rax
	xorl	%r14d, %r14d
	subl	(%rax), %r14d
LBB0_28:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_5:
	movq	%r12, -48(%rbp)                 ## 8-byte Spill
	movq	16(%r13), %rdi
	leaq	L_.str.1(%rip), %rsi
	callq	_pinctrl_lookup_state
	movq	%rax, %r12
	movq	%rax, %rdi
	callq	_IS_ERR
	testq	%rax, %rax
	je	LBB0_8
## %bb.6:
	leaq	L_.str.2(%rip), %rsi
	movq	%rbx, %rdi
	callq	_dev_err
	movq	%r12, %rdi
LBB0_7:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_PTR_ERR                        ## TAILCALL
LBB0_8:
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	leaq	4(%rax), %rcx
	movq	_MMC_TIMING_LEGACY@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%r12, (%r15,%rax,8)
	movq	%rcx, %r12
	movq	_MMC_CAP_UHS_SDR104@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	leaq	L_.str.3(%rip), %rsi
	movq	%r13, %rdi
	movq	%r12, %rdx
	callq	_sdhci_omap_iodelay_pinctrl_state
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	_IS_ERR
	testq	%rax, %rax
	jne	LBB0_10
## %bb.9:
	movq	_MMC_TIMING_UHS_SDR104@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rbx, (%r15,%rax,8)
LBB0_10:
	movq	_MMC_CAP_UHS_DDR50@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	leaq	L_.str.4(%rip), %rsi
	movq	%r13, %rdi
	movq	%r12, %rdx
	callq	_sdhci_omap_iodelay_pinctrl_state
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	_IS_ERR
	testq	%rax, %rax
	jne	LBB0_12
## %bb.11:
	movq	_MMC_TIMING_UHS_DDR50@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rbx, (%r15,%rax,8)
LBB0_12:
	movq	_MMC_CAP_UHS_SDR50@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	leaq	L_.str.5(%rip), %rsi
	movq	%r13, %rdi
	movq	%r12, %rdx
	callq	_sdhci_omap_iodelay_pinctrl_state
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	_IS_ERR
	testq	%rax, %rax
	jne	LBB0_14
## %bb.13:
	movq	_MMC_TIMING_UHS_SDR50@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rbx, (%r15,%rax,8)
LBB0_14:
	movq	_MMC_CAP_UHS_SDR25@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	leaq	L_.str.6(%rip), %rsi
	movq	%r13, %rdi
	movq	%r12, %rdx
	callq	_sdhci_omap_iodelay_pinctrl_state
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	_IS_ERR
	testq	%rax, %rax
	jne	LBB0_16
## %bb.15:
	movq	_MMC_TIMING_UHS_SDR25@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rbx, (%r15,%rax,8)
LBB0_16:
	movq	_MMC_CAP_UHS_SDR12@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	leaq	L_.str.7(%rip), %rsi
	movq	%r13, %rdi
	movq	%r12, %rdx
	callq	_sdhci_omap_iodelay_pinctrl_state
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	_IS_ERR
	testq	%rax, %rax
	jne	LBB0_18
## %bb.17:
	movq	_MMC_TIMING_UHS_SDR12@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rbx, (%r15,%rax,8)
LBB0_18:
	movq	_MMC_CAP_1_8V_DDR@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	leaq	L_.str.8(%rip), %rsi
	movq	%r13, %rdi
	movq	%r12, %rdx
	callq	_sdhci_omap_iodelay_pinctrl_state
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	_IS_ERR
	testq	%rax, %rax
	je	LBB0_20
## %bb.19:
	movq	_MMC_CAP_3_3V_DDR@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	leaq	L_.str.9(%rip), %rsi
	movq	%r13, %rdi
	movq	%r12, %rdx
	callq	_sdhci_omap_iodelay_pinctrl_state
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	_IS_ERR
	testq	%rax, %rax
	jne	LBB0_21
LBB0_20:
	movq	_MMC_TIMING_MMC_DDR52@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rbx, (%r15,%rax,8)
LBB0_21:
	movq	_MMC_CAP_SD_HIGHSPEED@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	leaq	L_.str.10(%rip), %rsi
	movq	%r13, %rdi
	movq	%r12, %rdx
	callq	_sdhci_omap_iodelay_pinctrl_state
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	_IS_ERR
	testq	%rax, %rax
	jne	LBB0_23
## %bb.22:
	movq	_MMC_TIMING_SD_HS@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rbx, (%r15,%rax,8)
LBB0_23:
	movq	_MMC_CAP_MMC_HIGHSPEED@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	leaq	L_.str.10(%rip), %rsi
	movq	%r13, %rdi
	movq	%r12, %rdx
	callq	_sdhci_omap_iodelay_pinctrl_state
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	_IS_ERR
	testq	%rax, %rax
	jne	LBB0_25
## %bb.24:
	movq	_MMC_TIMING_MMC_HS@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rbx, (%r15,%rax,8)
LBB0_25:
	movq	_MMC_CAP2_HS200_1_8V_SDR@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	leaq	L_.str.11(%rip), %rsi
	movq	%r13, %rdi
	movq	-48(%rbp), %rdx                 ## 8-byte Reload
	callq	_sdhci_omap_iodelay_pinctrl_state
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	_IS_ERR
	testq	%rax, %rax
	jne	LBB0_27
## %bb.26:
	movq	_MMC_TIMING_MMC_HS200@GOTPCREL(%rip), %rax
	movslq	(%rax), %rax
	movq	%rbx, (%r15,%rax,8)
LBB0_27:
	movq	%r15, 8(%r13)
	jmp	LBB0_28
	.cfi_endproc
                                        ## -- End function
	.comm	_SDHCI_OMAP_REQUIRE_IODELAY,4,2 ## @SDHCI_OMAP_REQUIRE_IODELAY
	.comm	_MMC_TIMING_MMC_HS200,4,2       ## @MMC_TIMING_MMC_HS200
	.comm	_GFP_KERNEL,4,2                 ## @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ## @ENOMEM
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Cannot get pinctrl\n"

L_.str.1:                               ## @.str.1
	.asciz	"default"

L_.str.2:                               ## @.str.2
	.asciz	"no pinctrl state for default mode\n"

	.comm	_MMC_TIMING_LEGACY,8,3          ## @MMC_TIMING_LEGACY
L_.str.3:                               ## @.str.3
	.asciz	"sdr104"

	.comm	_MMC_CAP_UHS_SDR104,4,2         ## @MMC_CAP_UHS_SDR104
	.comm	_MMC_TIMING_UHS_SDR104,8,3      ## @MMC_TIMING_UHS_SDR104
L_.str.4:                               ## @.str.4
	.asciz	"ddr50"

	.comm	_MMC_CAP_UHS_DDR50,4,2          ## @MMC_CAP_UHS_DDR50
	.comm	_MMC_TIMING_UHS_DDR50,8,3       ## @MMC_TIMING_UHS_DDR50
L_.str.5:                               ## @.str.5
	.asciz	"sdr50"

	.comm	_MMC_CAP_UHS_SDR50,4,2          ## @MMC_CAP_UHS_SDR50
	.comm	_MMC_TIMING_UHS_SDR50,8,3       ## @MMC_TIMING_UHS_SDR50
L_.str.6:                               ## @.str.6
	.asciz	"sdr25"

	.comm	_MMC_CAP_UHS_SDR25,4,2          ## @MMC_CAP_UHS_SDR25
	.comm	_MMC_TIMING_UHS_SDR25,8,3       ## @MMC_TIMING_UHS_SDR25
L_.str.7:                               ## @.str.7
	.asciz	"sdr12"

	.comm	_MMC_CAP_UHS_SDR12,4,2          ## @MMC_CAP_UHS_SDR12
	.comm	_MMC_TIMING_UHS_SDR12,8,3       ## @MMC_TIMING_UHS_SDR12
L_.str.8:                               ## @.str.8
	.asciz	"ddr_1_8v"

	.comm	_MMC_CAP_1_8V_DDR,4,2           ## @MMC_CAP_1_8V_DDR
	.comm	_MMC_TIMING_MMC_DDR52,8,3       ## @MMC_TIMING_MMC_DDR52
L_.str.9:                               ## @.str.9
	.asciz	"ddr_3_3v"

	.comm	_MMC_CAP_3_3V_DDR,4,2           ## @MMC_CAP_3_3V_DDR
L_.str.10:                              ## @.str.10
	.asciz	"hs"

	.comm	_MMC_CAP_SD_HIGHSPEED,4,2       ## @MMC_CAP_SD_HIGHSPEED
	.comm	_MMC_TIMING_SD_HS,8,3           ## @MMC_TIMING_SD_HS
	.comm	_MMC_CAP_MMC_HIGHSPEED,4,2      ## @MMC_CAP_MMC_HIGHSPEED
	.comm	_MMC_TIMING_MMC_HS,8,3          ## @MMC_TIMING_MMC_HS
L_.str.11:                              ## @.str.11
	.asciz	"hs200_1_8v"

	.comm	_MMC_CAP2_HS200_1_8V_SDR,4,2    ## @MMC_CAP2_HS200_1_8V_SDR
	.no_dead_strip	_sdhci_omap_config_iodelay_pinctrl_state
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function sdhci_omap_config_iodelay_pinctrl_state
_sdhci_omap_config_iodelay_pinctrl_state: ; @sdhci_omap_config_iodelay_pinctrl_state
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _SDHCI_OMAP_REQUIRE_IODELAY@GOTPAGE
Lloh1:
	ldr	x9, [x9, _SDHCI_OMAP_REQUIRE_IODELAY@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_4
; %bb.1:
	mov	x19, x0
	ldp	x22, x8, [x0, #24]
Lloh3:
	adrp	x24, _MMC_TIMING_MMC_HS200@GOTPAGE
Lloh4:
	ldr	x24, [x24, _MMC_TIMING_MMC_HS200@GOTPAGEOFF]
	ldr	x21, [x8]
	ldr	w8, [x24]
	add	w1, w8, #1
Lloh5:
	adrp	x8, _GFP_KERNEL@GOTPAGE
Lloh6:
	ldr	x8, [x8, _GFP_KERNEL@GOTPAGEOFF]
Lloh7:
	ldr	w3, [x8]
	mov	x0, x22
	mov	w2, #8
	bl	_devm_kcalloc
	cbz	x0, LBB0_5
; %bb.2:
	mov	x20, x0
	ldr	x0, [x19, #24]
	bl	_devm_pinctrl_get
	str	x0, [x19, #16]
	bl	_IS_ERR
	cbz	x0, LBB0_7
; %bb.3:
Lloh8:
	adrp	x1, l_.str@PAGE
Lloh9:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x22
	bl	_dev_err
	ldr	x0, [x19, #16]
	b	LBB0_9
LBB0_4:
	mov	w0, #0
	b	LBB0_6
LBB0_5:
Lloh10:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh11:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_6:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_7:
	ldr	x0, [x19, #16]
Lloh13:
	adrp	x1, l_.str.1@PAGE
Lloh14:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_pinctrl_lookup_state
	mov	x23, x0
	bl	_IS_ERR
	cbz	x0, LBB0_10
; %bb.8:
Lloh15:
	adrp	x1, l_.str.2@PAGE
Lloh16:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x0, x22
	bl	_dev_err
	mov	x0, x23
LBB0_9:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_PTR_ERR
LBB0_10:
	add	x22, x21, #4
Lloh17:
	adrp	x8, _MMC_TIMING_LEGACY@GOTPAGE
Lloh18:
	ldr	x8, [x8, _MMC_TIMING_LEGACY@GOTPAGEOFF]
Lloh19:
	ldr	x8, [x8]
	str	x23, [x20, x8, lsl #3]
Lloh20:
	adrp	x8, _MMC_CAP_UHS_SDR104@GOTPAGE
Lloh21:
	ldr	x8, [x8, _MMC_CAP_UHS_SDR104@GOTPAGEOFF]
Lloh22:
	ldr	w3, [x8]
Lloh23:
	adrp	x1, l_.str.3@PAGE
Lloh24:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x0, x19
	mov	x2, x22
	bl	_sdhci_omap_iodelay_pinctrl_state
	mov	x23, x0
	bl	_IS_ERR
	cbnz	x0, LBB0_12
; %bb.11:
Lloh25:
	adrp	x8, _MMC_TIMING_UHS_SDR104@GOTPAGE
Lloh26:
	ldr	x8, [x8, _MMC_TIMING_UHS_SDR104@GOTPAGEOFF]
Lloh27:
	ldr	x8, [x8]
	str	x23, [x20, x8, lsl #3]
LBB0_12:
Lloh28:
	adrp	x8, _MMC_CAP_UHS_DDR50@GOTPAGE
Lloh29:
	ldr	x8, [x8, _MMC_CAP_UHS_DDR50@GOTPAGEOFF]
Lloh30:
	ldr	w3, [x8]
Lloh31:
	adrp	x1, l_.str.4@PAGE
Lloh32:
	add	x1, x1, l_.str.4@PAGEOFF
	mov	x0, x19
	mov	x2, x22
	bl	_sdhci_omap_iodelay_pinctrl_state
	mov	x23, x0
	bl	_IS_ERR
	cbnz	x0, LBB0_14
; %bb.13:
Lloh33:
	adrp	x8, _MMC_TIMING_UHS_DDR50@GOTPAGE
Lloh34:
	ldr	x8, [x8, _MMC_TIMING_UHS_DDR50@GOTPAGEOFF]
Lloh35:
	ldr	x8, [x8]
	str	x23, [x20, x8, lsl #3]
LBB0_14:
Lloh36:
	adrp	x8, _MMC_CAP_UHS_SDR50@GOTPAGE
Lloh37:
	ldr	x8, [x8, _MMC_CAP_UHS_SDR50@GOTPAGEOFF]
Lloh38:
	ldr	w3, [x8]
Lloh39:
	adrp	x1, l_.str.5@PAGE
Lloh40:
	add	x1, x1, l_.str.5@PAGEOFF
	mov	x0, x19
	mov	x2, x22
	bl	_sdhci_omap_iodelay_pinctrl_state
	mov	x23, x0
	bl	_IS_ERR
	cbnz	x0, LBB0_16
; %bb.15:
Lloh41:
	adrp	x8, _MMC_TIMING_UHS_SDR50@GOTPAGE
Lloh42:
	ldr	x8, [x8, _MMC_TIMING_UHS_SDR50@GOTPAGEOFF]
Lloh43:
	ldr	x8, [x8]
	str	x23, [x20, x8, lsl #3]
LBB0_16:
Lloh44:
	adrp	x8, _MMC_CAP_UHS_SDR25@GOTPAGE
Lloh45:
	ldr	x8, [x8, _MMC_CAP_UHS_SDR25@GOTPAGEOFF]
Lloh46:
	ldr	w3, [x8]
Lloh47:
	adrp	x1, l_.str.6@PAGE
Lloh48:
	add	x1, x1, l_.str.6@PAGEOFF
	mov	x0, x19
	mov	x2, x22
	bl	_sdhci_omap_iodelay_pinctrl_state
	mov	x23, x0
	bl	_IS_ERR
	cbnz	x0, LBB0_18
; %bb.17:
Lloh49:
	adrp	x8, _MMC_TIMING_UHS_SDR25@GOTPAGE
Lloh50:
	ldr	x8, [x8, _MMC_TIMING_UHS_SDR25@GOTPAGEOFF]
Lloh51:
	ldr	x8, [x8]
	str	x23, [x20, x8, lsl #3]
LBB0_18:
Lloh52:
	adrp	x8, _MMC_CAP_UHS_SDR12@GOTPAGE
Lloh53:
	ldr	x8, [x8, _MMC_CAP_UHS_SDR12@GOTPAGEOFF]
Lloh54:
	ldr	w3, [x8]
Lloh55:
	adrp	x1, l_.str.7@PAGE
Lloh56:
	add	x1, x1, l_.str.7@PAGEOFF
	mov	x0, x19
	mov	x2, x22
	bl	_sdhci_omap_iodelay_pinctrl_state
	mov	x23, x0
	bl	_IS_ERR
	cbnz	x0, LBB0_20
; %bb.19:
Lloh57:
	adrp	x8, _MMC_TIMING_UHS_SDR12@GOTPAGE
Lloh58:
	ldr	x8, [x8, _MMC_TIMING_UHS_SDR12@GOTPAGEOFF]
Lloh59:
	ldr	x8, [x8]
	str	x23, [x20, x8, lsl #3]
LBB0_20:
Lloh60:
	adrp	x8, _MMC_CAP_1_8V_DDR@GOTPAGE
Lloh61:
	ldr	x8, [x8, _MMC_CAP_1_8V_DDR@GOTPAGEOFF]
Lloh62:
	ldr	w3, [x8]
Lloh63:
	adrp	x1, l_.str.8@PAGE
Lloh64:
	add	x1, x1, l_.str.8@PAGEOFF
	mov	x0, x19
	mov	x2, x22
	bl	_sdhci_omap_iodelay_pinctrl_state
	mov	x23, x0
	bl	_IS_ERR
	cbz	x0, LBB0_22
; %bb.21:
Lloh65:
	adrp	x8, _MMC_CAP_3_3V_DDR@GOTPAGE
Lloh66:
	ldr	x8, [x8, _MMC_CAP_3_3V_DDR@GOTPAGEOFF]
Lloh67:
	ldr	w3, [x8]
Lloh68:
	adrp	x1, l_.str.9@PAGE
Lloh69:
	add	x1, x1, l_.str.9@PAGEOFF
	mov	x0, x19
	mov	x2, x22
	bl	_sdhci_omap_iodelay_pinctrl_state
	mov	x23, x0
	bl	_IS_ERR
	cbnz	x0, LBB0_23
LBB0_22:
Lloh70:
	adrp	x8, _MMC_TIMING_MMC_DDR52@GOTPAGE
Lloh71:
	ldr	x8, [x8, _MMC_TIMING_MMC_DDR52@GOTPAGEOFF]
Lloh72:
	ldr	x8, [x8]
	str	x23, [x20, x8, lsl #3]
LBB0_23:
Lloh73:
	adrp	x8, _MMC_CAP_SD_HIGHSPEED@GOTPAGE
Lloh74:
	ldr	x8, [x8, _MMC_CAP_SD_HIGHSPEED@GOTPAGEOFF]
Lloh75:
	ldr	w3, [x8]
Lloh76:
	adrp	x1, l_.str.10@PAGE
Lloh77:
	add	x1, x1, l_.str.10@PAGEOFF
	mov	x0, x19
	mov	x2, x22
	bl	_sdhci_omap_iodelay_pinctrl_state
	mov	x23, x0
	bl	_IS_ERR
	cbnz	x0, LBB0_25
; %bb.24:
Lloh78:
	adrp	x8, _MMC_TIMING_SD_HS@GOTPAGE
Lloh79:
	ldr	x8, [x8, _MMC_TIMING_SD_HS@GOTPAGEOFF]
Lloh80:
	ldr	x8, [x8]
	str	x23, [x20, x8, lsl #3]
LBB0_25:
Lloh81:
	adrp	x8, _MMC_CAP_MMC_HIGHSPEED@GOTPAGE
Lloh82:
	ldr	x8, [x8, _MMC_CAP_MMC_HIGHSPEED@GOTPAGEOFF]
Lloh83:
	ldr	w3, [x8]
Lloh84:
	adrp	x1, l_.str.10@PAGE
Lloh85:
	add	x1, x1, l_.str.10@PAGEOFF
	mov	x0, x19
	mov	x2, x22
	bl	_sdhci_omap_iodelay_pinctrl_state
	mov	x22, x0
	bl	_IS_ERR
	cbnz	x0, LBB0_27
; %bb.26:
Lloh86:
	adrp	x8, _MMC_TIMING_MMC_HS@GOTPAGE
Lloh87:
	ldr	x8, [x8, _MMC_TIMING_MMC_HS@GOTPAGEOFF]
Lloh88:
	ldr	x8, [x8]
	str	x22, [x20, x8, lsl #3]
LBB0_27:
Lloh89:
	adrp	x8, _MMC_CAP2_HS200_1_8V_SDR@GOTPAGE
Lloh90:
	ldr	x8, [x8, _MMC_CAP2_HS200_1_8V_SDR@GOTPAGEOFF]
Lloh91:
	ldr	w3, [x8]
Lloh92:
	adrp	x1, l_.str.11@PAGE
Lloh93:
	add	x1, x1, l_.str.11@PAGEOFF
	mov	x0, x19
	mov	x2, x21
	bl	_sdhci_omap_iodelay_pinctrl_state
	mov	x21, x0
	bl	_IS_ERR
	cbnz	x0, LBB0_29
; %bb.28:
	ldrsw	x8, [x24]
	str	x21, [x20, x8, lsl #3]
LBB0_29:
	mov	w0, #0
	str	x20, [x19, #8]
	b	LBB0_6
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpAdd	Lloh13, Lloh14
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpAdd	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpAdd	Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpAdd	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpAdd	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpAdd	Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpAdd	Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpAdd	Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpAdd	Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpAdd	Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpAdd	Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.cfi_endproc
                                        ; -- End function
	.comm	_SDHCI_OMAP_REQUIRE_IODELAY,4,2 ; @SDHCI_OMAP_REQUIRE_IODELAY
	.comm	_MMC_TIMING_MMC_HS200,4,2       ; @MMC_TIMING_MMC_HS200
	.comm	_GFP_KERNEL,4,2                 ; @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ; @ENOMEM
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Cannot get pinctrl\n"

l_.str.1:                               ; @.str.1
	.asciz	"default"

l_.str.2:                               ; @.str.2
	.asciz	"no pinctrl state for default mode\n"

	.comm	_MMC_TIMING_LEGACY,8,3          ; @MMC_TIMING_LEGACY
l_.str.3:                               ; @.str.3
	.asciz	"sdr104"

	.comm	_MMC_CAP_UHS_SDR104,4,2         ; @MMC_CAP_UHS_SDR104
	.comm	_MMC_TIMING_UHS_SDR104,8,3      ; @MMC_TIMING_UHS_SDR104
l_.str.4:                               ; @.str.4
	.asciz	"ddr50"

	.comm	_MMC_CAP_UHS_DDR50,4,2          ; @MMC_CAP_UHS_DDR50
	.comm	_MMC_TIMING_UHS_DDR50,8,3       ; @MMC_TIMING_UHS_DDR50
l_.str.5:                               ; @.str.5
	.asciz	"sdr50"

	.comm	_MMC_CAP_UHS_SDR50,4,2          ; @MMC_CAP_UHS_SDR50
	.comm	_MMC_TIMING_UHS_SDR50,8,3       ; @MMC_TIMING_UHS_SDR50
l_.str.6:                               ; @.str.6
	.asciz	"sdr25"

	.comm	_MMC_CAP_UHS_SDR25,4,2          ; @MMC_CAP_UHS_SDR25
	.comm	_MMC_TIMING_UHS_SDR25,8,3       ; @MMC_TIMING_UHS_SDR25
l_.str.7:                               ; @.str.7
	.asciz	"sdr12"

	.comm	_MMC_CAP_UHS_SDR12,4,2          ; @MMC_CAP_UHS_SDR12
	.comm	_MMC_TIMING_UHS_SDR12,8,3       ; @MMC_TIMING_UHS_SDR12
l_.str.8:                               ; @.str.8
	.asciz	"ddr_1_8v"

	.comm	_MMC_CAP_1_8V_DDR,4,2           ; @MMC_CAP_1_8V_DDR
	.comm	_MMC_TIMING_MMC_DDR52,8,3       ; @MMC_TIMING_MMC_DDR52
l_.str.9:                               ; @.str.9
	.asciz	"ddr_3_3v"

	.comm	_MMC_CAP_3_3V_DDR,4,2           ; @MMC_CAP_3_3V_DDR
l_.str.10:                              ; @.str.10
	.asciz	"hs"

	.comm	_MMC_CAP_SD_HIGHSPEED,4,2       ; @MMC_CAP_SD_HIGHSPEED
	.comm	_MMC_TIMING_SD_HS,8,3           ; @MMC_TIMING_SD_HS
	.comm	_MMC_CAP_MMC_HIGHSPEED,4,2      ; @MMC_CAP_MMC_HIGHSPEED
	.comm	_MMC_TIMING_MMC_HS,8,3          ; @MMC_TIMING_MMC_HS
l_.str.11:                              ; @.str.11
	.asciz	"hs200_1_8v"

	.comm	_MMC_CAP2_HS200_1_8V_SDR,4,2    ; @MMC_CAP2_HS200_1_8V_SDR
	.no_dead_strip	_sdhci_omap_config_iodelay_pinctrl_state
.subsections_via_symbols
