	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function sd_set_timing
_sd_set_timing:                         ## @sd_set_timing
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %ebx
	movq	(%rdi), %r14
	movq	%r14, %rdi
	callq	_rtsx_pci_init_cmd
	addb	$-128, %bl
	cmpb	$5, %bl
	ja	LBB0_5
## %bb.1:
	movzbl	%bl, %eax
	movl	$3, %ecx
	btl	%eax, %ecx
	jb	LBB0_8
## %bb.2:
	movl	$24, %ecx
	movq	_WRITE_REG_CMD@GOTPCREL(%rip), %rbx
	btl	%eax, %ecx
	jae	LBB0_3
## %bb.4:
	movl	(%rbx), %esi
	movq	_SD_CFG1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_SD_20_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	movq	%r14, %rdi
	movl	$12, %ecx
	callq	_rtsx_pci_add_cmd
	movl	(%rbx), %esi
	movq	_CLK_CTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	movq	_CLK_LOW_FREQ@GOTPCREL(%rip), %r12
	movl	(%r12), %ecx
	movq	%r14, %rdi
	movl	%ecx, %r8d
	callq	_rtsx_pci_add_cmd
	movl	(%rbx), %esi
	movq	_CARD_CLK_SOURCE@GOTPCREL(%rip), %rax
	movq	_CRC_FIX_CLK@GOTPCREL(%rip), %rcx
	movq	_SD30_VAR_CLK0@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r8d
	orl	(%rcx), %r8d
	movl	(%rax), %edx
	movq	_SAMPLE_VAR_CLK1@GOTPCREL(%rip), %rax
	orl	(%rax), %r8d
	movq	%r14, %rdi
	movl	$255, %ecx
	callq	_rtsx_pci_add_cmd
	movl	(%rbx), %esi
	movl	(%r15), %edx
	movl	(%r12), %ecx
	movq	%r14, %rdi
	xorl	%r8d, %r8d
	callq	_rtsx_pci_add_cmd
	movl	(%rbx), %esi
	movq	_SD_PUSH_POINT_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_SD20_TX_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	_SD20_TX_14_AHEAD@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	movq	%r14, %rdi
	callq	_rtsx_pci_add_cmd
	movl	(%rbx), %esi
	movq	_SD_SAMPLE_POINT_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_SD20_RX_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	_SD20_RX_14_DELAY@GOTPCREL(%rip), %rax
	jmp	LBB0_6
LBB0_8:
	movq	_WRITE_REG_CMD@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_SD_CFG1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_SD_ASYNC_FIFO_NOT_RST@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	movl	%r8d, %ecx
	orl	$12, %ecx
	movq	_SD_30_MODE@GOTPCREL(%rip), %rax
	orl	(%rax), %r8d
	movq	%r14, %rdi
	callq	_rtsx_pci_add_cmd
	movl	(%rbx), %esi
	movq	_CLK_CTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	movq	_CLK_LOW_FREQ@GOTPCREL(%rip), %r12
	movl	(%r12), %ecx
	movq	%r14, %rdi
	movl	%ecx, %r8d
	callq	_rtsx_pci_add_cmd
	movl	(%rbx), %esi
	movq	_CARD_CLK_SOURCE@GOTPCREL(%rip), %rax
	movq	_CRC_VAR_CLK0@GOTPCREL(%rip), %rcx
	movq	_SD30_FIX_CLK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r8d
	orl	(%rcx), %r8d
	movl	(%rax), %edx
	movq	_SAMPLE_VAR_CLK1@GOTPCREL(%rip), %rax
	orl	(%rax), %r8d
	movq	%r14, %rdi
	movl	$255, %ecx
	callq	_rtsx_pci_add_cmd
	movl	(%rbx), %esi
	movl	(%r15), %edx
	movl	(%r12), %ecx
	movq	%r14, %rdi
	xorl	%r8d, %r8d
	jmp	LBB0_7
LBB0_3:
	movl	(%rbx), %esi
	movq	_SD_CFG1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_SD_ASYNC_FIFO_NOT_RST@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	movl	%r8d, %ecx
	orl	$12, %ecx
	movq	_SD_DDR_MODE@GOTPCREL(%rip), %rax
	orl	(%rax), %r8d
	movq	%r14, %rdi
	callq	_rtsx_pci_add_cmd
	movl	(%rbx), %esi
	movq	_CLK_CTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	movq	_CLK_LOW_FREQ@GOTPCREL(%rip), %r12
	movl	(%r12), %ecx
	movq	%r14, %rdi
	movl	%ecx, %r8d
	callq	_rtsx_pci_add_cmd
	movl	(%rbx), %esi
	movq	_CARD_CLK_SOURCE@GOTPCREL(%rip), %rax
	movq	_CRC_VAR_CLK0@GOTPCREL(%rip), %rcx
	movq	_SD30_FIX_CLK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r8d
	orl	(%rcx), %r8d
	movl	(%rax), %edx
	movq	_SAMPLE_VAR_CLK1@GOTPCREL(%rip), %rax
	orl	(%rax), %r8d
	movq	%r14, %rdi
	movl	$255, %ecx
	callq	_rtsx_pci_add_cmd
	movl	(%rbx), %esi
	movl	(%r15), %edx
	movl	(%r12), %ecx
	movq	%r14, %rdi
	xorl	%r8d, %r8d
	callq	_rtsx_pci_add_cmd
	movl	(%rbx), %esi
	movq	_SD_PUSH_POINT_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_DDR_VAR_TX_CMD_DAT@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r14, %rdi
	movl	%ecx, %r8d
	callq	_rtsx_pci_add_cmd
	movl	(%rbx), %esi
	movq	_SD_SAMPLE_POINT_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_DDR_VAR_RX_DAT@GOTPCREL(%rip), %rax
	movq	_DDR_VAR_RX_CMD@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	%r14, %rdi
	movl	%ecx, %r8d
	jmp	LBB0_7
LBB0_5:
	movq	_WRITE_REG_CMD@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_SD_CFG1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_SD_20_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	movq	%r14, %rdi
	movl	$12, %ecx
	callq	_rtsx_pci_add_cmd
	movl	(%rbx), %esi
	movq	_CLK_CTL@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	movq	_CLK_LOW_FREQ@GOTPCREL(%rip), %r12
	movl	(%r12), %ecx
	movq	%r14, %rdi
	movl	%ecx, %r8d
	callq	_rtsx_pci_add_cmd
	movl	(%rbx), %esi
	movq	_CARD_CLK_SOURCE@GOTPCREL(%rip), %rax
	movq	_CRC_FIX_CLK@GOTPCREL(%rip), %rcx
	movq	_SD30_VAR_CLK0@GOTPCREL(%rip), %rdx
	movl	(%rdx), %r8d
	orl	(%rcx), %r8d
	movl	(%rax), %edx
	movq	_SAMPLE_VAR_CLK1@GOTPCREL(%rip), %rax
	orl	(%rax), %r8d
	movq	%r14, %rdi
	movl	$255, %ecx
	callq	_rtsx_pci_add_cmd
	movl	(%rbx), %esi
	movl	(%r15), %edx
	movl	(%r12), %ecx
	movq	%r14, %rdi
	xorl	%r8d, %r8d
	callq	_rtsx_pci_add_cmd
	movl	(%rbx), %esi
	movq	_SD_PUSH_POINT_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	movl	$255, %ecx
	xorl	%r8d, %r8d
	callq	_rtsx_pci_add_cmd
	movl	(%rbx), %esi
	movq	_SD_SAMPLE_POINT_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_SD20_RX_SEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	_SD20_RX_POS_EDGE@GOTPCREL(%rip), %rax
LBB0_6:
	movl	(%rax), %r8d
	movq	%r14, %rdi
LBB0_7:
	callq	_rtsx_pci_add_cmd
	movq	%r14, %rdi
	movl	$100, %esi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_rtsx_pci_send_cmd              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_WRITE_REG_CMD,4,2              ## @WRITE_REG_CMD
	.comm	_SD_CFG1,4,2                    ## @SD_CFG1
	.comm	_SD_ASYNC_FIFO_NOT_RST,4,2      ## @SD_ASYNC_FIFO_NOT_RST
	.comm	_SD_30_MODE,4,2                 ## @SD_30_MODE
	.comm	_CLK_CTL,4,2                    ## @CLK_CTL
	.comm	_CLK_LOW_FREQ,4,2               ## @CLK_LOW_FREQ
	.comm	_CARD_CLK_SOURCE,4,2            ## @CARD_CLK_SOURCE
	.comm	_CRC_VAR_CLK0,4,2               ## @CRC_VAR_CLK0
	.comm	_SD30_FIX_CLK,4,2               ## @SD30_FIX_CLK
	.comm	_SAMPLE_VAR_CLK1,4,2            ## @SAMPLE_VAR_CLK1
	.comm	_SD_DDR_MODE,4,2                ## @SD_DDR_MODE
	.comm	_SD_PUSH_POINT_CTL,4,2          ## @SD_PUSH_POINT_CTL
	.comm	_DDR_VAR_TX_CMD_DAT,4,2         ## @DDR_VAR_TX_CMD_DAT
	.comm	_SD_SAMPLE_POINT_CTL,4,2        ## @SD_SAMPLE_POINT_CTL
	.comm	_DDR_VAR_RX_DAT,4,2             ## @DDR_VAR_RX_DAT
	.comm	_DDR_VAR_RX_CMD,4,2             ## @DDR_VAR_RX_CMD
	.comm	_SD_20_MODE,4,2                 ## @SD_20_MODE
	.comm	_CRC_FIX_CLK,4,2                ## @CRC_FIX_CLK
	.comm	_SD30_VAR_CLK0,4,2              ## @SD30_VAR_CLK0
	.comm	_SD20_TX_SEL_MASK,4,2           ## @SD20_TX_SEL_MASK
	.comm	_SD20_TX_14_AHEAD,4,2           ## @SD20_TX_14_AHEAD
	.comm	_SD20_RX_SEL_MASK,4,2           ## @SD20_RX_SEL_MASK
	.comm	_SD20_RX_14_DELAY,4,2           ## @SD20_RX_14_DELAY
	.comm	_SD20_RX_POS_EDGE,4,2           ## @SD20_RX_POS_EDGE
	.no_dead_strip	_sd_set_timing
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function sd_set_timing
_sd_set_timing:                         ; @sd_set_timing
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	ldr	x19, [x0]
	mov	x0, x19
	bl	_rtsx_pci_init_cmd
	sub	w8, w20, #128
	cmp	w8, #5
	b.hi	LBB0_6
; %bb.1:
	mov	w9, #1
	lsl	w8, w9, w8
Lloh0:
	adrp	x20, _WRITE_REG_CMD@GOTPAGE
Lloh1:
	ldr	x20, [x20, _WRITE_REG_CMD@GOTPAGEOFF]
	tst	w8, #0x3
	b.ne	LBB0_4
; %bb.2:
	tst	w8, #0x18
	b.eq	LBB0_5
; %bb.3:
	ldr	w1, [x20]
Lloh2:
	adrp	x8, _SD_CFG1@GOTPAGE
Lloh3:
	ldr	x8, [x8, _SD_CFG1@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
Lloh5:
	adrp	x8, _SD_20_MODE@GOTPAGE
Lloh6:
	ldr	x8, [x8, _SD_20_MODE@GOTPAGEOFF]
Lloh7:
	ldr	w4, [x8]
	mov	x0, x19
	mov	w3, #12
	bl	_rtsx_pci_add_cmd
	ldr	w1, [x20]
Lloh8:
	adrp	x21, _CLK_CTL@GOTPAGE
Lloh9:
	ldr	x21, [x21, _CLK_CTL@GOTPAGEOFF]
	ldr	w2, [x21]
Lloh10:
	adrp	x22, _CLK_LOW_FREQ@GOTPAGE
Lloh11:
	ldr	x22, [x22, _CLK_LOW_FREQ@GOTPAGEOFF]
	ldr	w3, [x22]
	mov	x0, x19
	mov	x4, x3
	bl	_rtsx_pci_add_cmd
	ldr	w1, [x20]
Lloh12:
	adrp	x8, _CARD_CLK_SOURCE@GOTPAGE
Lloh13:
	ldr	x8, [x8, _CARD_CLK_SOURCE@GOTPAGEOFF]
Lloh14:
	ldr	w2, [x8]
Lloh15:
	adrp	x8, _CRC_FIX_CLK@GOTPAGE
Lloh16:
	ldr	x8, [x8, _CRC_FIX_CLK@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
Lloh18:
	adrp	x9, _SD30_VAR_CLK0@GOTPAGE
Lloh19:
	ldr	x9, [x9, _SD30_VAR_CLK0@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh21:
	adrp	x9, _SAMPLE_VAR_CLK1@GOTPAGE
Lloh22:
	ldr	x9, [x9, _SAMPLE_VAR_CLK1@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	orr	w4, w8, w9
	mov	x0, x19
	mov	w3, #255
	bl	_rtsx_pci_add_cmd
	ldr	w1, [x20]
	ldr	w2, [x21]
	ldr	w3, [x22]
	mov	x0, x19
	mov	w4, #0
	bl	_rtsx_pci_add_cmd
	ldr	w1, [x20]
Lloh24:
	adrp	x8, _SD_PUSH_POINT_CTL@GOTPAGE
Lloh25:
	ldr	x8, [x8, _SD_PUSH_POINT_CTL@GOTPAGEOFF]
Lloh26:
	ldr	w2, [x8]
Lloh27:
	adrp	x8, _SD20_TX_SEL_MASK@GOTPAGE
Lloh28:
	ldr	x8, [x8, _SD20_TX_SEL_MASK@GOTPAGEOFF]
Lloh29:
	ldr	w3, [x8]
Lloh30:
	adrp	x8, _SD20_TX_14_AHEAD@GOTPAGE
Lloh31:
	ldr	x8, [x8, _SD20_TX_14_AHEAD@GOTPAGEOFF]
Lloh32:
	ldr	w4, [x8]
	mov	x0, x19
	bl	_rtsx_pci_add_cmd
	ldr	w1, [x20]
Lloh33:
	adrp	x8, _SD_SAMPLE_POINT_CTL@GOTPAGE
Lloh34:
	ldr	x8, [x8, _SD_SAMPLE_POINT_CTL@GOTPAGEOFF]
Lloh35:
	ldr	w2, [x8]
Lloh36:
	adrp	x8, _SD20_RX_SEL_MASK@GOTPAGE
Lloh37:
	ldr	x8, [x8, _SD20_RX_SEL_MASK@GOTPAGEOFF]
Lloh38:
	ldr	w3, [x8]
Lloh39:
	adrp	x8, _SD20_RX_14_DELAY@GOTPAGE
Lloh40:
	ldr	x8, [x8, _SD20_RX_14_DELAY@GOTPAGEOFF]
	b	LBB0_7
LBB0_4:
	ldr	w1, [x20]
Lloh41:
	adrp	x8, _SD_CFG1@GOTPAGE
Lloh42:
	ldr	x8, [x8, _SD_CFG1@GOTPAGEOFF]
Lloh43:
	ldr	w2, [x8]
Lloh44:
	adrp	x8, _SD_ASYNC_FIFO_NOT_RST@GOTPAGE
Lloh45:
	ldr	x8, [x8, _SD_ASYNC_FIFO_NOT_RST@GOTPAGEOFF]
Lloh46:
	ldr	w8, [x8]
	orr	w3, w8, #0xc
Lloh47:
	adrp	x9, _SD_30_MODE@GOTPAGE
Lloh48:
	ldr	x9, [x9, _SD_30_MODE@GOTPAGEOFF]
Lloh49:
	ldr	w9, [x9]
	orr	w4, w9, w8
	mov	x0, x19
	bl	_rtsx_pci_add_cmd
	ldr	w1, [x20]
Lloh50:
	adrp	x21, _CLK_CTL@GOTPAGE
Lloh51:
	ldr	x21, [x21, _CLK_CTL@GOTPAGEOFF]
	ldr	w2, [x21]
Lloh52:
	adrp	x22, _CLK_LOW_FREQ@GOTPAGE
Lloh53:
	ldr	x22, [x22, _CLK_LOW_FREQ@GOTPAGEOFF]
	ldr	w3, [x22]
	mov	x0, x19
	mov	x4, x3
	bl	_rtsx_pci_add_cmd
	ldr	w1, [x20]
Lloh54:
	adrp	x8, _CARD_CLK_SOURCE@GOTPAGE
Lloh55:
	ldr	x8, [x8, _CARD_CLK_SOURCE@GOTPAGEOFF]
Lloh56:
	ldr	w2, [x8]
Lloh57:
	adrp	x8, _CRC_VAR_CLK0@GOTPAGE
Lloh58:
	ldr	x8, [x8, _CRC_VAR_CLK0@GOTPAGEOFF]
Lloh59:
	ldr	w8, [x8]
Lloh60:
	adrp	x9, _SD30_FIX_CLK@GOTPAGE
Lloh61:
	ldr	x9, [x9, _SD30_FIX_CLK@GOTPAGEOFF]
Lloh62:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh63:
	adrp	x9, _SAMPLE_VAR_CLK1@GOTPAGE
Lloh64:
	ldr	x9, [x9, _SAMPLE_VAR_CLK1@GOTPAGEOFF]
Lloh65:
	ldr	w9, [x9]
	orr	w4, w8, w9
	mov	x0, x19
	mov	w3, #255
	bl	_rtsx_pci_add_cmd
	ldr	w1, [x20]
	ldr	w2, [x21]
	ldr	w3, [x22]
	mov	x0, x19
	mov	w4, #0
	b	LBB0_8
LBB0_5:
	ldr	w1, [x20]
Lloh66:
	adrp	x8, _SD_CFG1@GOTPAGE
Lloh67:
	ldr	x8, [x8, _SD_CFG1@GOTPAGEOFF]
Lloh68:
	ldr	w2, [x8]
Lloh69:
	adrp	x8, _SD_ASYNC_FIFO_NOT_RST@GOTPAGE
Lloh70:
	ldr	x8, [x8, _SD_ASYNC_FIFO_NOT_RST@GOTPAGEOFF]
Lloh71:
	ldr	w8, [x8]
	orr	w3, w8, #0xc
Lloh72:
	adrp	x9, _SD_DDR_MODE@GOTPAGE
Lloh73:
	ldr	x9, [x9, _SD_DDR_MODE@GOTPAGEOFF]
Lloh74:
	ldr	w9, [x9]
	orr	w4, w9, w8
	mov	x0, x19
	bl	_rtsx_pci_add_cmd
	ldr	w1, [x20]
Lloh75:
	adrp	x21, _CLK_CTL@GOTPAGE
Lloh76:
	ldr	x21, [x21, _CLK_CTL@GOTPAGEOFF]
	ldr	w2, [x21]
Lloh77:
	adrp	x22, _CLK_LOW_FREQ@GOTPAGE
Lloh78:
	ldr	x22, [x22, _CLK_LOW_FREQ@GOTPAGEOFF]
	ldr	w3, [x22]
	mov	x0, x19
	mov	x4, x3
	bl	_rtsx_pci_add_cmd
	ldr	w1, [x20]
Lloh79:
	adrp	x8, _CARD_CLK_SOURCE@GOTPAGE
Lloh80:
	ldr	x8, [x8, _CARD_CLK_SOURCE@GOTPAGEOFF]
Lloh81:
	ldr	w2, [x8]
Lloh82:
	adrp	x8, _CRC_VAR_CLK0@GOTPAGE
Lloh83:
	ldr	x8, [x8, _CRC_VAR_CLK0@GOTPAGEOFF]
Lloh84:
	ldr	w8, [x8]
Lloh85:
	adrp	x9, _SD30_FIX_CLK@GOTPAGE
Lloh86:
	ldr	x9, [x9, _SD30_FIX_CLK@GOTPAGEOFF]
Lloh87:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh88:
	adrp	x9, _SAMPLE_VAR_CLK1@GOTPAGE
Lloh89:
	ldr	x9, [x9, _SAMPLE_VAR_CLK1@GOTPAGEOFF]
Lloh90:
	ldr	w9, [x9]
	orr	w4, w8, w9
	mov	x0, x19
	mov	w3, #255
	bl	_rtsx_pci_add_cmd
	ldr	w1, [x20]
	ldr	w2, [x21]
	ldr	w3, [x22]
	mov	x0, x19
	mov	w4, #0
	bl	_rtsx_pci_add_cmd
	ldr	w1, [x20]
Lloh91:
	adrp	x8, _SD_PUSH_POINT_CTL@GOTPAGE
Lloh92:
	ldr	x8, [x8, _SD_PUSH_POINT_CTL@GOTPAGEOFF]
Lloh93:
	ldr	w2, [x8]
Lloh94:
	adrp	x8, _DDR_VAR_TX_CMD_DAT@GOTPAGE
Lloh95:
	ldr	x8, [x8, _DDR_VAR_TX_CMD_DAT@GOTPAGEOFF]
Lloh96:
	ldr	w3, [x8]
	mov	x0, x19
	mov	x4, x3
	bl	_rtsx_pci_add_cmd
	ldr	w1, [x20]
Lloh97:
	adrp	x8, _SD_SAMPLE_POINT_CTL@GOTPAGE
Lloh98:
	ldr	x8, [x8, _SD_SAMPLE_POINT_CTL@GOTPAGEOFF]
Lloh99:
	adrp	x9, _DDR_VAR_RX_DAT@GOTPAGE
Lloh100:
	ldr	x9, [x9, _DDR_VAR_RX_DAT@GOTPAGEOFF]
Lloh101:
	ldr	w2, [x8]
Lloh102:
	ldr	w8, [x9]
Lloh103:
	adrp	x9, _DDR_VAR_RX_CMD@GOTPAGE
Lloh104:
	ldr	x9, [x9, _DDR_VAR_RX_CMD@GOTPAGEOFF]
Lloh105:
	ldr	w9, [x9]
	orr	w3, w9, w8
	mov	x0, x19
	mov	x4, x3
	b	LBB0_8
LBB0_6:
Lloh106:
	adrp	x20, _WRITE_REG_CMD@GOTPAGE
Lloh107:
	ldr	x20, [x20, _WRITE_REG_CMD@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh108:
	adrp	x8, _SD_CFG1@GOTPAGE
Lloh109:
	ldr	x8, [x8, _SD_CFG1@GOTPAGEOFF]
Lloh110:
	ldr	w2, [x8]
Lloh111:
	adrp	x8, _SD_20_MODE@GOTPAGE
Lloh112:
	ldr	x8, [x8, _SD_20_MODE@GOTPAGEOFF]
Lloh113:
	ldr	w4, [x8]
	mov	x0, x19
	mov	w3, #12
	bl	_rtsx_pci_add_cmd
	ldr	w1, [x20]
Lloh114:
	adrp	x21, _CLK_CTL@GOTPAGE
Lloh115:
	ldr	x21, [x21, _CLK_CTL@GOTPAGEOFF]
	ldr	w2, [x21]
Lloh116:
	adrp	x22, _CLK_LOW_FREQ@GOTPAGE
Lloh117:
	ldr	x22, [x22, _CLK_LOW_FREQ@GOTPAGEOFF]
	ldr	w3, [x22]
	mov	x0, x19
	mov	x4, x3
	bl	_rtsx_pci_add_cmd
	ldr	w1, [x20]
Lloh118:
	adrp	x8, _CARD_CLK_SOURCE@GOTPAGE
Lloh119:
	ldr	x8, [x8, _CARD_CLK_SOURCE@GOTPAGEOFF]
Lloh120:
	ldr	w2, [x8]
Lloh121:
	adrp	x8, _CRC_FIX_CLK@GOTPAGE
Lloh122:
	ldr	x8, [x8, _CRC_FIX_CLK@GOTPAGEOFF]
Lloh123:
	ldr	w8, [x8]
Lloh124:
	adrp	x9, _SD30_VAR_CLK0@GOTPAGE
Lloh125:
	ldr	x9, [x9, _SD30_VAR_CLK0@GOTPAGEOFF]
Lloh126:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh127:
	adrp	x9, _SAMPLE_VAR_CLK1@GOTPAGE
Lloh128:
	ldr	x9, [x9, _SAMPLE_VAR_CLK1@GOTPAGEOFF]
Lloh129:
	ldr	w9, [x9]
	orr	w4, w8, w9
	mov	x0, x19
	mov	w3, #255
	bl	_rtsx_pci_add_cmd
	ldr	w1, [x20]
	ldr	w2, [x21]
	ldr	w3, [x22]
	mov	x0, x19
	mov	w4, #0
	bl	_rtsx_pci_add_cmd
	ldr	w1, [x20]
Lloh130:
	adrp	x8, _SD_PUSH_POINT_CTL@GOTPAGE
Lloh131:
	ldr	x8, [x8, _SD_PUSH_POINT_CTL@GOTPAGEOFF]
Lloh132:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #255
	mov	w4, #0
	bl	_rtsx_pci_add_cmd
	ldr	w1, [x20]
Lloh133:
	adrp	x8, _SD_SAMPLE_POINT_CTL@GOTPAGE
Lloh134:
	ldr	x8, [x8, _SD_SAMPLE_POINT_CTL@GOTPAGEOFF]
Lloh135:
	ldr	w2, [x8]
Lloh136:
	adrp	x8, _SD20_RX_SEL_MASK@GOTPAGE
Lloh137:
	ldr	x8, [x8, _SD20_RX_SEL_MASK@GOTPAGEOFF]
Lloh138:
	ldr	w3, [x8]
Lloh139:
	adrp	x8, _SD20_RX_POS_EDGE@GOTPAGE
Lloh140:
	ldr	x8, [x8, _SD20_RX_POS_EDGE@GOTPAGEOFF]
LBB0_7:
	ldr	w4, [x8]
	mov	x0, x19
LBB0_8:
	bl	_rtsx_pci_add_cmd
	mov	x0, x19
	mov	w1, #100
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_rtsx_pci_send_cmd
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh101
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGot	Lloh77, Lloh78
	.loh AdrpLdrGot	Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGot	Lloh139, Lloh140
	.loh AdrpLdrGotLdr	Lloh136, Lloh137, Lloh138
	.loh AdrpLdrGotLdr	Lloh133, Lloh134, Lloh135
	.loh AdrpLdrGotLdr	Lloh130, Lloh131, Lloh132
	.loh AdrpLdrGotLdr	Lloh127, Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGot	Lloh116, Lloh117
	.loh AdrpLdrGot	Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGot	Lloh106, Lloh107
	.cfi_endproc
                                        ; -- End function
	.comm	_WRITE_REG_CMD,4,2              ; @WRITE_REG_CMD
	.comm	_SD_CFG1,4,2                    ; @SD_CFG1
	.comm	_SD_ASYNC_FIFO_NOT_RST,4,2      ; @SD_ASYNC_FIFO_NOT_RST
	.comm	_SD_30_MODE,4,2                 ; @SD_30_MODE
	.comm	_CLK_CTL,4,2                    ; @CLK_CTL
	.comm	_CLK_LOW_FREQ,4,2               ; @CLK_LOW_FREQ
	.comm	_CARD_CLK_SOURCE,4,2            ; @CARD_CLK_SOURCE
	.comm	_CRC_VAR_CLK0,4,2               ; @CRC_VAR_CLK0
	.comm	_SD30_FIX_CLK,4,2               ; @SD30_FIX_CLK
	.comm	_SAMPLE_VAR_CLK1,4,2            ; @SAMPLE_VAR_CLK1
	.comm	_SD_DDR_MODE,4,2                ; @SD_DDR_MODE
	.comm	_SD_PUSH_POINT_CTL,4,2          ; @SD_PUSH_POINT_CTL
	.comm	_DDR_VAR_TX_CMD_DAT,4,2         ; @DDR_VAR_TX_CMD_DAT
	.comm	_SD_SAMPLE_POINT_CTL,4,2        ; @SD_SAMPLE_POINT_CTL
	.comm	_DDR_VAR_RX_DAT,4,2             ; @DDR_VAR_RX_DAT
	.comm	_DDR_VAR_RX_CMD,4,2             ; @DDR_VAR_RX_CMD
	.comm	_SD_20_MODE,4,2                 ; @SD_20_MODE
	.comm	_CRC_FIX_CLK,4,2                ; @CRC_FIX_CLK
	.comm	_SD30_VAR_CLK0,4,2              ; @SD30_VAR_CLK0
	.comm	_SD20_TX_SEL_MASK,4,2           ; @SD20_TX_SEL_MASK
	.comm	_SD20_TX_14_AHEAD,4,2           ; @SD20_TX_14_AHEAD
	.comm	_SD20_RX_SEL_MASK,4,2           ; @SD20_RX_SEL_MASK
	.comm	_SD20_RX_14_DELAY,4,2           ; @SD20_RX_14_DELAY
	.comm	_SD20_RX_POS_EDGE,4,2           ; @SD20_RX_POS_EDGE
	.no_dead_strip	_sd_set_timing
.subsections_via_symbols
