	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function jz4740_mmc_set_clock_rate
_jz4740_mmc_set_clock_rate:             ## @jz4740_mmc_set_clock_rate
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %r15
	callq	_jz4740_mmc_clock_disable
	movl	8(%r15), %edi
	movq	16(%r15), %rax
	movl	(%rax), %esi
	callq	_clk_set_rate
	movl	8(%r15), %edi
	callq	_clk_get_rate
	cmpl	%r14d, %eax
	jle	LBB0_1
## %bb.2:
	movl	%eax, %ebx
	sarl	%ebx
	movl	$1, %edi
	cmpl	%r14d, %ebx
	jle	LBB0_9
## %bb.3:
	movl	%eax, %ebx
	sarl	$2, %ebx
	movl	$2, %edi
	cmpl	%r14d, %ebx
	jle	LBB0_9
## %bb.4:
	movl	%eax, %ebx
	sarl	$3, %ebx
	movl	$3, %edi
	cmpl	%r14d, %ebx
	jle	LBB0_9
## %bb.5:
	movl	%eax, %ebx
	sarl	$4, %ebx
	movl	$4, %edi
	cmpl	%r14d, %ebx
	jle	LBB0_9
## %bb.6:
	movl	%eax, %ebx
	sarl	$5, %ebx
	movl	$5, %edi
	cmpl	%r14d, %ebx
	jle	LBB0_9
## %bb.7:
	movl	%eax, %ecx
	sarl	$6, %ecx
	sarl	$7, %eax
	xorl	%edi, %edi
	cmpl	%r14d, %ecx
	setg	%dil
	cmovlel	%ecx, %eax
	orl	$6, %edi
	jmp	LBB0_8
LBB0_1:
	xorl	%edi, %edi
LBB0_8:
	movl	%eax, %ebx
LBB0_9:
	movq	_JZ_REG_MMC_CLKRT@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%r15), %rsi
	callq	_writew
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_JZ_REG_MMC_CLKRT,8,3           ## @JZ_REG_MMC_CLKRT
	.no_dead_strip	_jz4740_mmc_set_clock_rate
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function jz4740_mmc_set_clock_rate
_jz4740_mmc_set_clock_rate:             ; @jz4740_mmc_set_clock_rate
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	mov	x19, x0
	bl	_jz4740_mmc_clock_disable
	ldr	w0, [x19, #8]
	ldr	x8, [x19, #16]
	ldr	w1, [x8]
	bl	_clk_set_rate
	ldr	w0, [x19, #8]
	bl	_clk_get_rate
	mov	x21, x0
	cmp	w0, w20
	b.le	LBB0_3
; %bb.1:
	asr	w8, w21, #1
	cmp	w8, w20
	b.le	LBB0_4
; %bb.2:
	asr	w8, w21, #2
	mov	w9, #2
	asr	w10, w21, #3
	mov	w11, #3
	asr	w12, w21, #4
	mov	w13, #4
	asr	w14, w21, #5
	mov	w15, #5
	asr	w16, w21, #6
	asr	w17, w21, #7
	mov	w0, #6
	cmp	w16, w20
	csel	w16, w17, w16, gt
	cinc	w17, w0, gt
	cmp	w14, w20
	csel	w15, w15, w17, le
	csel	w14, w14, w16, le
	cmp	w12, w20
	csel	w13, w13, w15, le
	csel	w12, w12, w14, le
	cmp	w10, w20
	csel	w11, w11, w13, le
	csel	w10, w10, w12, le
	cmp	w8, w20
	csel	w0, w9, w11, le
	csel	w21, w8, w10, le
	b	LBB0_5
LBB0_3:
	mov	w0, #0
	b	LBB0_5
LBB0_4:
	mov	w0, #1
	mov	x21, x8
LBB0_5:
	ldr	x8, [x19]
Lloh0:
	adrp	x9, _JZ_REG_MMC_CLKRT@GOTPAGE
Lloh1:
	ldr	x9, [x9, _JZ_REG_MMC_CLKRT@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writew
	mov	x0, x21
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_JZ_REG_MMC_CLKRT,8,3           ; @JZ_REG_MMC_CLKRT
	.no_dead_strip	_jz4740_mmc_set_clock_rate
.subsections_via_symbols
