	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_cec_adap_enable
_tegra_cec_adap_enable:                 ## @tegra_cec_adap_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %ebx
	movq	(%rdi), %r14
	xorps	%xmm0, %xmm0
	movups	%xmm0, (%r14)
	movq	$0, 16(%r14)
	movq	_TEGRA_CEC_HW_CONTROL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	_cec_write
	movq	_TEGRA_CEC_INT_MASK@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	_cec_write
	movq	_TEGRA_CEC_INT_STAT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$-1, %edx
	callq	_cec_write
	movq	_TEGRA_CEC_SW_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	_cec_write
	testl	%ebx, %ebx
	je	LBB0_2
## %bb.1:
	movq	_TEGRA_CEC_INPUT_FILTER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$-2147483616, %edx              ## imm = 0x80000020
	callq	_cec_write
	movq	_TEGRA_CEC_RX_TIM0_START_BIT_MAX_LO_TIME_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$122, %eax
	shll	%cl, %eax
	movq	_TEGRA_CEC_RX_TIM0_START_BIT_MIN_LO_TIME_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$109, %edi
	shll	%cl, %edi
	movq	_TEGRA_CEC_RX_TIM0_START_BIT_MAX_DURATION_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$147, %ebx
	shll	%cl, %ebx
	orl	%eax, %edi
	movq	_TEGRA_CEC_RX_TIM0_START_BIT_MIN_DURATION_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$134, %edx
	shll	%cl, %edx
	movq	_TEGRA_CEC_RX_TIMING_0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	%ebx, %edx
	orl	%edi, %edx
	movq	%r14, %rdi
	callq	_cec_write
	movq	_TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_LO_TIME_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$53, %eax
	shll	%cl, %eax
	movq	_TEGRA_CEC_RX_TIM1_DATA_BIT_SAMPLE_TIME_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$33, %edi
	shll	%cl, %edi
	movq	_TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_DURATION_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$86, %ebx
	shll	%cl, %ebx
	movq	_TEGRA_CEC_RX_TIMING_1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_TEGRA_CEC_RX_TIM1_DATA_BIT_MIN_DURATION_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$64, %edx
	shll	%cl, %edx
	orl	%eax, %edi
	movl	$33, %r13d
	orl	%ebx, %edx
	orl	%edi, %edx
	movq	%r14, %rdi
	callq	_cec_write
	movq	_TEGRA_CEC_RX_TIMING_2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_TEGRA_CEC_RX_TIM2_END_OF_BLOCK_TIME_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$80, %edx
	shll	%cl, %edx
	movq	%r14, %rdi
	callq	_cec_write
	movq	_TEGRA_CEC_TX_TIM0_START_BIT_LO_TIME_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$116, %eax
	shll	%cl, %eax
	movq	_TEGRA_CEC_TX_TIM0_START_BIT_DURATION_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$141, %edi
	shll	%cl, %edi
	movq	_TEGRA_CEC_TX_TIM0_BUS_XITION_TIME_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$8, %ebx
	shll	%cl, %ebx
	orl	%eax, %edi
	movq	_TEGRA_CEC_TX_TIM0_BUS_ERROR_LO_TIME_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$113, %edx
	shll	%cl, %edx
	movq	_TEGRA_CEC_TX_TIMING_0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	%ebx, %edx
	orl	%edi, %edx
	movq	%r14, %rdi
	callq	_cec_write
	movq	_TEGRA_CEC_TX_TIM1_LO_DATA_BIT_LO_TIME_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$47, %eax
	shll	%cl, %eax
	movq	_TEGRA_CEC_TX_TIM1_HI_DATA_BIT_LO_TIME_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$19, %edx
	shll	%cl, %edx
	movq	_TEGRA_CEC_TX_TIM1_DATA_BIT_DURATION_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$75, %edi
	shll	%cl, %edi
	movq	_TEGRA_CEC_TX_TIM1_ACK_NAK_BIT_SAMPLE_TIME_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movq	_TEGRA_CEC_TX_TIMING_1@GOTPCREL(%rip), %rsi
	shll	%cl, %r13d
	movl	(%rsi), %esi
	orl	%eax, %edx
	orl	%edi, %r13d
	orl	%edx, %r13d
	movq	%r14, %rdi
	movl	%r13d, %edx
	callq	_cec_write
	movq	_TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_ADDITIONAL_FRAME_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$7, %eax
	shll	%cl, %eax
	movq	_TEGRA_CEC_TX_TIMING_2@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_NEW_FRAME_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$5, %edi
	shll	%cl, %edi
	orl	%eax, %edi
	movq	_TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_RETRY_FRAME_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$3, %edx
	shll	%cl, %edx
	orl	%edi, %edx
	movq	%r14, %rdi
	callq	_cec_write
	movq	_TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN@GOTPCREL(%rip), %rax
	movq	_TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	_TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_TEGRA_CEC_INT_MASK_RX_REGISTER_FULL@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	(%r12), %esi
	movq	_TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	%r14, %rdi
	callq	_cec_write
	movl	(%r15), %esi
	movq	_TEGRA_CEC_HWCTRL_TX_RX_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_cec_write
LBB0_2:
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_TEGRA_CEC_HW_CONTROL,4,2       ## @TEGRA_CEC_HW_CONTROL
	.comm	_TEGRA_CEC_INT_MASK,4,2         ## @TEGRA_CEC_INT_MASK
	.comm	_TEGRA_CEC_INT_STAT,4,2         ## @TEGRA_CEC_INT_STAT
	.comm	_TEGRA_CEC_SW_CONTROL,4,2       ## @TEGRA_CEC_SW_CONTROL
	.comm	_TEGRA_CEC_INPUT_FILTER,4,2     ## @TEGRA_CEC_INPUT_FILTER
	.comm	_TEGRA_CEC_RX_TIMING_0,4,2      ## @TEGRA_CEC_RX_TIMING_0
	.comm	_TEGRA_CEC_RX_TIM0_START_BIT_MAX_LO_TIME_SHIFT,4,2 ## @TEGRA_CEC_RX_TIM0_START_BIT_MAX_LO_TIME_SHIFT
	.comm	_TEGRA_CEC_RX_TIM0_START_BIT_MIN_LO_TIME_SHIFT,4,2 ## @TEGRA_CEC_RX_TIM0_START_BIT_MIN_LO_TIME_SHIFT
	.comm	_TEGRA_CEC_RX_TIM0_START_BIT_MAX_DURATION_SHIFT,4,2 ## @TEGRA_CEC_RX_TIM0_START_BIT_MAX_DURATION_SHIFT
	.comm	_TEGRA_CEC_RX_TIM0_START_BIT_MIN_DURATION_SHIFT,4,2 ## @TEGRA_CEC_RX_TIM0_START_BIT_MIN_DURATION_SHIFT
	.comm	_TEGRA_CEC_RX_TIMING_1,4,2      ## @TEGRA_CEC_RX_TIMING_1
	.comm	_TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_LO_TIME_SHIFT,4,2 ## @TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_LO_TIME_SHIFT
	.comm	_TEGRA_CEC_RX_TIM1_DATA_BIT_SAMPLE_TIME_SHIFT,4,2 ## @TEGRA_CEC_RX_TIM1_DATA_BIT_SAMPLE_TIME_SHIFT
	.comm	_TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_DURATION_SHIFT,4,2 ## @TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_DURATION_SHIFT
	.comm	_TEGRA_CEC_RX_TIM1_DATA_BIT_MIN_DURATION_SHIFT,4,2 ## @TEGRA_CEC_RX_TIM1_DATA_BIT_MIN_DURATION_SHIFT
	.comm	_TEGRA_CEC_RX_TIMING_2,4,2      ## @TEGRA_CEC_RX_TIMING_2
	.comm	_TEGRA_CEC_RX_TIM2_END_OF_BLOCK_TIME_SHIFT,4,2 ## @TEGRA_CEC_RX_TIM2_END_OF_BLOCK_TIME_SHIFT
	.comm	_TEGRA_CEC_TX_TIMING_0,4,2      ## @TEGRA_CEC_TX_TIMING_0
	.comm	_TEGRA_CEC_TX_TIM0_START_BIT_LO_TIME_SHIFT,4,2 ## @TEGRA_CEC_TX_TIM0_START_BIT_LO_TIME_SHIFT
	.comm	_TEGRA_CEC_TX_TIM0_START_BIT_DURATION_SHIFT,4,2 ## @TEGRA_CEC_TX_TIM0_START_BIT_DURATION_SHIFT
	.comm	_TEGRA_CEC_TX_TIM0_BUS_XITION_TIME_SHIFT,4,2 ## @TEGRA_CEC_TX_TIM0_BUS_XITION_TIME_SHIFT
	.comm	_TEGRA_CEC_TX_TIM0_BUS_ERROR_LO_TIME_SHIFT,4,2 ## @TEGRA_CEC_TX_TIM0_BUS_ERROR_LO_TIME_SHIFT
	.comm	_TEGRA_CEC_TX_TIMING_1,4,2      ## @TEGRA_CEC_TX_TIMING_1
	.comm	_TEGRA_CEC_TX_TIM1_LO_DATA_BIT_LO_TIME_SHIFT,4,2 ## @TEGRA_CEC_TX_TIM1_LO_DATA_BIT_LO_TIME_SHIFT
	.comm	_TEGRA_CEC_TX_TIM1_HI_DATA_BIT_LO_TIME_SHIFT,4,2 ## @TEGRA_CEC_TX_TIM1_HI_DATA_BIT_LO_TIME_SHIFT
	.comm	_TEGRA_CEC_TX_TIM1_DATA_BIT_DURATION_SHIFT,4,2 ## @TEGRA_CEC_TX_TIM1_DATA_BIT_DURATION_SHIFT
	.comm	_TEGRA_CEC_TX_TIM1_ACK_NAK_BIT_SAMPLE_TIME_SHIFT,4,2 ## @TEGRA_CEC_TX_TIM1_ACK_NAK_BIT_SAMPLE_TIME_SHIFT
	.comm	_TEGRA_CEC_TX_TIMING_2,4,2      ## @TEGRA_CEC_TX_TIMING_2
	.comm	_TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_ADDITIONAL_FRAME_SHIFT,4,2 ## @TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_ADDITIONAL_FRAME_SHIFT
	.comm	_TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_NEW_FRAME_SHIFT,4,2 ## @TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_NEW_FRAME_SHIFT
	.comm	_TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_RETRY_FRAME_SHIFT,4,2 ## @TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_RETRY_FRAME_SHIFT
	.comm	_TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN,4,2 ## @TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN
	.comm	_TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD,4,2 ## @TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD
	.comm	_TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED,4,2 ## @TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED
	.comm	_TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED,4,2 ## @TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED
	.comm	_TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED,4,2 ## @TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED
	.comm	_TEGRA_CEC_INT_MASK_RX_REGISTER_FULL,4,2 ## @TEGRA_CEC_INT_MASK_RX_REGISTER_FULL
	.comm	_TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED,4,2 ## @TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED
	.comm	_TEGRA_CEC_HWCTRL_TX_RX_MODE,4,2 ## @TEGRA_CEC_HWCTRL_TX_RX_MODE
	.no_dead_strip	_tegra_cec_adap_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_cec_adap_enable
_tegra_cec_adap_enable:                 ; @tegra_cec_adap_enable
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	ldr	x19, [x0]
	stp	xzr, xzr, [x19]
	str	xzr, [x19, #16]
Lloh0:
	adrp	x21, _TEGRA_CEC_HW_CONTROL@GOTPAGE
Lloh1:
	ldr	x21, [x21, _TEGRA_CEC_HW_CONTROL@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	mov	w2, #0
	bl	_cec_write
Lloh2:
	adrp	x22, _TEGRA_CEC_INT_MASK@GOTPAGE
Lloh3:
	ldr	x22, [x22, _TEGRA_CEC_INT_MASK@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x19
	mov	w2, #0
	bl	_cec_write
Lloh4:
	adrp	x8, _TEGRA_CEC_INT_STAT@GOTPAGE
Lloh5:
	ldr	x8, [x8, _TEGRA_CEC_INT_STAT@GOTPAGEOFF]
Lloh6:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1
	bl	_cec_write
Lloh7:
	adrp	x8, _TEGRA_CEC_SW_CONTROL@GOTPAGE
Lloh8:
	ldr	x8, [x8, _TEGRA_CEC_SW_CONTROL@GOTPAGEOFF]
Lloh9:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_cec_write
	cbz	w20, LBB0_2
; %bb.1:
Lloh10:
	adrp	x8, _TEGRA_CEC_INPUT_FILTER@GOTPAGE
Lloh11:
	ldr	x8, [x8, _TEGRA_CEC_INPUT_FILTER@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #32
	movk	w2, #32768, lsl #16
	bl	_cec_write
Lloh13:
	adrp	x8, _TEGRA_CEC_RX_TIMING_0@GOTPAGE
Lloh14:
	ldr	x8, [x8, _TEGRA_CEC_RX_TIMING_0@GOTPAGEOFF]
Lloh15:
	ldr	w1, [x8]
Lloh16:
	adrp	x8, _TEGRA_CEC_RX_TIM0_START_BIT_MAX_LO_TIME_SHIFT@GOTPAGE
Lloh17:
	ldr	x8, [x8, _TEGRA_CEC_RX_TIM0_START_BIT_MAX_LO_TIME_SHIFT@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	mov	w9, #122
	lsl	w8, w9, w8
Lloh19:
	adrp	x9, _TEGRA_CEC_RX_TIM0_START_BIT_MIN_LO_TIME_SHIFT@GOTPAGE
Lloh20:
	ldr	x9, [x9, _TEGRA_CEC_RX_TIM0_START_BIT_MIN_LO_TIME_SHIFT@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	mov	w10, #109
	lsl	w9, w10, w9
	orr	w8, w9, w8
Lloh22:
	adrp	x9, _TEGRA_CEC_RX_TIM0_START_BIT_MAX_DURATION_SHIFT@GOTPAGE
Lloh23:
	ldr	x9, [x9, _TEGRA_CEC_RX_TIM0_START_BIT_MAX_DURATION_SHIFT@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	mov	w10, #147
	lsl	w9, w10, w9
	orr	w8, w8, w9
Lloh25:
	adrp	x9, _TEGRA_CEC_RX_TIM0_START_BIT_MIN_DURATION_SHIFT@GOTPAGE
Lloh26:
	ldr	x9, [x9, _TEGRA_CEC_RX_TIM0_START_BIT_MIN_DURATION_SHIFT@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
	mov	w10, #134
	lsl	w9, w10, w9
	orr	w2, w8, w9
	mov	x0, x19
	bl	_cec_write
Lloh28:
	adrp	x8, _TEGRA_CEC_RX_TIMING_1@GOTPAGE
Lloh29:
	ldr	x8, [x8, _TEGRA_CEC_RX_TIMING_1@GOTPAGEOFF]
Lloh30:
	ldr	w1, [x8]
Lloh31:
	adrp	x8, _TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_LO_TIME_SHIFT@GOTPAGE
Lloh32:
	ldr	x8, [x8, _TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_LO_TIME_SHIFT@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
	mov	w9, #53
	lsl	w8, w9, w8
Lloh34:
	adrp	x9, _TEGRA_CEC_RX_TIM1_DATA_BIT_SAMPLE_TIME_SHIFT@GOTPAGE
Lloh35:
	ldr	x9, [x9, _TEGRA_CEC_RX_TIM1_DATA_BIT_SAMPLE_TIME_SHIFT@GOTPAGEOFF]
Lloh36:
	ldr	w9, [x9]
	mov	w20, #33
	lsl	w9, w20, w9
	orr	w8, w9, w8
Lloh37:
	adrp	x9, _TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_DURATION_SHIFT@GOTPAGE
Lloh38:
	ldr	x9, [x9, _TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_DURATION_SHIFT@GOTPAGEOFF]
Lloh39:
	ldr	w9, [x9]
	mov	w10, #86
	lsl	w9, w10, w9
	orr	w8, w8, w9
Lloh40:
	adrp	x9, _TEGRA_CEC_RX_TIM1_DATA_BIT_MIN_DURATION_SHIFT@GOTPAGE
Lloh41:
	ldr	x9, [x9, _TEGRA_CEC_RX_TIM1_DATA_BIT_MIN_DURATION_SHIFT@GOTPAGEOFF]
Lloh42:
	ldr	w9, [x9]
	mov	w10, #64
	lsl	w9, w10, w9
	orr	w2, w8, w9
	mov	x0, x19
	bl	_cec_write
Lloh43:
	adrp	x8, _TEGRA_CEC_RX_TIMING_2@GOTPAGE
Lloh44:
	ldr	x8, [x8, _TEGRA_CEC_RX_TIMING_2@GOTPAGEOFF]
Lloh45:
	ldr	w1, [x8]
Lloh46:
	adrp	x8, _TEGRA_CEC_RX_TIM2_END_OF_BLOCK_TIME_SHIFT@GOTPAGE
Lloh47:
	ldr	x8, [x8, _TEGRA_CEC_RX_TIM2_END_OF_BLOCK_TIME_SHIFT@GOTPAGEOFF]
Lloh48:
	ldr	w8, [x8]
	mov	w9, #80
	lsl	w2, w9, w8
	mov	x0, x19
	bl	_cec_write
Lloh49:
	adrp	x8, _TEGRA_CEC_TX_TIMING_0@GOTPAGE
Lloh50:
	ldr	x8, [x8, _TEGRA_CEC_TX_TIMING_0@GOTPAGEOFF]
Lloh51:
	ldr	w1, [x8]
Lloh52:
	adrp	x8, _TEGRA_CEC_TX_TIM0_START_BIT_LO_TIME_SHIFT@GOTPAGE
Lloh53:
	ldr	x8, [x8, _TEGRA_CEC_TX_TIM0_START_BIT_LO_TIME_SHIFT@GOTPAGEOFF]
Lloh54:
	ldr	w8, [x8]
	mov	w9, #116
	lsl	w8, w9, w8
Lloh55:
	adrp	x9, _TEGRA_CEC_TX_TIM0_START_BIT_DURATION_SHIFT@GOTPAGE
Lloh56:
	ldr	x9, [x9, _TEGRA_CEC_TX_TIM0_START_BIT_DURATION_SHIFT@GOTPAGEOFF]
Lloh57:
	ldr	w9, [x9]
	mov	w10, #141
	lsl	w9, w10, w9
	orr	w8, w9, w8
Lloh58:
	adrp	x9, _TEGRA_CEC_TX_TIM0_BUS_XITION_TIME_SHIFT@GOTPAGE
Lloh59:
	ldr	x9, [x9, _TEGRA_CEC_TX_TIM0_BUS_XITION_TIME_SHIFT@GOTPAGEOFF]
Lloh60:
	ldr	w9, [x9]
	mov	w10, #8
	lsl	w9, w10, w9
	orr	w8, w8, w9
Lloh61:
	adrp	x9, _TEGRA_CEC_TX_TIM0_BUS_ERROR_LO_TIME_SHIFT@GOTPAGE
Lloh62:
	ldr	x9, [x9, _TEGRA_CEC_TX_TIM0_BUS_ERROR_LO_TIME_SHIFT@GOTPAGEOFF]
Lloh63:
	ldr	w9, [x9]
	mov	w10, #113
	lsl	w9, w10, w9
	orr	w2, w8, w9
	mov	x0, x19
	bl	_cec_write
Lloh64:
	adrp	x8, _TEGRA_CEC_TX_TIMING_1@GOTPAGE
Lloh65:
	ldr	x8, [x8, _TEGRA_CEC_TX_TIMING_1@GOTPAGEOFF]
Lloh66:
	ldr	w1, [x8]
Lloh67:
	adrp	x8, _TEGRA_CEC_TX_TIM1_LO_DATA_BIT_LO_TIME_SHIFT@GOTPAGE
Lloh68:
	ldr	x8, [x8, _TEGRA_CEC_TX_TIM1_LO_DATA_BIT_LO_TIME_SHIFT@GOTPAGEOFF]
Lloh69:
	ldr	w8, [x8]
	mov	w9, #47
	lsl	w8, w9, w8
Lloh70:
	adrp	x9, _TEGRA_CEC_TX_TIM1_HI_DATA_BIT_LO_TIME_SHIFT@GOTPAGE
Lloh71:
	ldr	x9, [x9, _TEGRA_CEC_TX_TIM1_HI_DATA_BIT_LO_TIME_SHIFT@GOTPAGEOFF]
Lloh72:
	ldr	w9, [x9]
	mov	w10, #19
	lsl	w9, w10, w9
	orr	w8, w9, w8
Lloh73:
	adrp	x9, _TEGRA_CEC_TX_TIM1_DATA_BIT_DURATION_SHIFT@GOTPAGE
Lloh74:
	ldr	x9, [x9, _TEGRA_CEC_TX_TIM1_DATA_BIT_DURATION_SHIFT@GOTPAGEOFF]
Lloh75:
	ldr	w9, [x9]
	mov	w10, #75
	lsl	w9, w10, w9
	orr	w8, w8, w9
Lloh76:
	adrp	x9, _TEGRA_CEC_TX_TIM1_ACK_NAK_BIT_SAMPLE_TIME_SHIFT@GOTPAGE
Lloh77:
	ldr	x9, [x9, _TEGRA_CEC_TX_TIM1_ACK_NAK_BIT_SAMPLE_TIME_SHIFT@GOTPAGEOFF]
Lloh78:
	ldr	w9, [x9]
	lsl	w9, w20, w9
	orr	w2, w8, w9
	mov	x0, x19
	bl	_cec_write
Lloh79:
	adrp	x8, _TEGRA_CEC_TX_TIMING_2@GOTPAGE
Lloh80:
	ldr	x8, [x8, _TEGRA_CEC_TX_TIMING_2@GOTPAGEOFF]
Lloh81:
	ldr	w1, [x8]
Lloh82:
	adrp	x8, _TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_ADDITIONAL_FRAME_SHIFT@GOTPAGE
Lloh83:
	ldr	x8, [x8, _TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_ADDITIONAL_FRAME_SHIFT@GOTPAGEOFF]
Lloh84:
	ldr	w8, [x8]
	mov	w9, #7
	lsl	w8, w9, w8
Lloh85:
	adrp	x9, _TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_NEW_FRAME_SHIFT@GOTPAGE
Lloh86:
	ldr	x9, [x9, _TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_NEW_FRAME_SHIFT@GOTPAGEOFF]
Lloh87:
	ldr	w9, [x9]
	mov	w10, #5
	lsl	w9, w10, w9
	orr	w8, w9, w8
Lloh88:
	adrp	x9, _TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_RETRY_FRAME_SHIFT@GOTPAGE
Lloh89:
	ldr	x9, [x9, _TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_RETRY_FRAME_SHIFT@GOTPAGEOFF]
Lloh90:
	ldr	w9, [x9]
	mov	w10, #3
	lsl	w9, w10, w9
	orr	w2, w8, w9
	mov	x0, x19
	bl	_cec_write
	ldr	w1, [x22]
Lloh91:
	adrp	x8, _TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN@GOTPAGE
Lloh92:
	ldr	x8, [x8, _TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN@GOTPAGEOFF]
Lloh93:
	ldr	w8, [x8]
Lloh94:
	adrp	x9, _TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD@GOTPAGE
Lloh95:
	ldr	x9, [x9, _TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD@GOTPAGEOFF]
Lloh96:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh97:
	adrp	x9, _TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED@GOTPAGE
Lloh98:
	ldr	x9, [x9, _TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED@GOTPAGEOFF]
Lloh99:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh100:
	adrp	x9, _TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED@GOTPAGE
Lloh101:
	ldr	x9, [x9, _TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED@GOTPAGEOFF]
Lloh102:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh103:
	adrp	x9, _TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED@GOTPAGE
Lloh104:
	ldr	x9, [x9, _TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED@GOTPAGEOFF]
Lloh105:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh106:
	adrp	x9, _TEGRA_CEC_INT_MASK_RX_REGISTER_FULL@GOTPAGE
Lloh107:
	ldr	x9, [x9, _TEGRA_CEC_INT_MASK_RX_REGISTER_FULL@GOTPAGEOFF]
Lloh108:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh109:
	adrp	x9, _TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED@GOTPAGE
Lloh110:
	ldr	x9, [x9, _TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED@GOTPAGEOFF]
Lloh111:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x19
	bl	_cec_write
	ldr	w1, [x21]
Lloh112:
	adrp	x8, _TEGRA_CEC_HWCTRL_TX_RX_MODE@GOTPAGE
Lloh113:
	ldr	x8, [x8, _TEGRA_CEC_HWCTRL_TX_RX_MODE@GOTPAGEOFF]
Lloh114:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_cec_write
LBB0_2:
	mov	w0, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh112, Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.cfi_endproc
                                        ; -- End function
	.comm	_TEGRA_CEC_HW_CONTROL,4,2       ; @TEGRA_CEC_HW_CONTROL
	.comm	_TEGRA_CEC_INT_MASK,4,2         ; @TEGRA_CEC_INT_MASK
	.comm	_TEGRA_CEC_INT_STAT,4,2         ; @TEGRA_CEC_INT_STAT
	.comm	_TEGRA_CEC_SW_CONTROL,4,2       ; @TEGRA_CEC_SW_CONTROL
	.comm	_TEGRA_CEC_INPUT_FILTER,4,2     ; @TEGRA_CEC_INPUT_FILTER
	.comm	_TEGRA_CEC_RX_TIMING_0,4,2      ; @TEGRA_CEC_RX_TIMING_0
	.comm	_TEGRA_CEC_RX_TIM0_START_BIT_MAX_LO_TIME_SHIFT,4,2 ; @TEGRA_CEC_RX_TIM0_START_BIT_MAX_LO_TIME_SHIFT
	.comm	_TEGRA_CEC_RX_TIM0_START_BIT_MIN_LO_TIME_SHIFT,4,2 ; @TEGRA_CEC_RX_TIM0_START_BIT_MIN_LO_TIME_SHIFT
	.comm	_TEGRA_CEC_RX_TIM0_START_BIT_MAX_DURATION_SHIFT,4,2 ; @TEGRA_CEC_RX_TIM0_START_BIT_MAX_DURATION_SHIFT
	.comm	_TEGRA_CEC_RX_TIM0_START_BIT_MIN_DURATION_SHIFT,4,2 ; @TEGRA_CEC_RX_TIM0_START_BIT_MIN_DURATION_SHIFT
	.comm	_TEGRA_CEC_RX_TIMING_1,4,2      ; @TEGRA_CEC_RX_TIMING_1
	.comm	_TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_LO_TIME_SHIFT,4,2 ; @TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_LO_TIME_SHIFT
	.comm	_TEGRA_CEC_RX_TIM1_DATA_BIT_SAMPLE_TIME_SHIFT,4,2 ; @TEGRA_CEC_RX_TIM1_DATA_BIT_SAMPLE_TIME_SHIFT
	.comm	_TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_DURATION_SHIFT,4,2 ; @TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_DURATION_SHIFT
	.comm	_TEGRA_CEC_RX_TIM1_DATA_BIT_MIN_DURATION_SHIFT,4,2 ; @TEGRA_CEC_RX_TIM1_DATA_BIT_MIN_DURATION_SHIFT
	.comm	_TEGRA_CEC_RX_TIMING_2,4,2      ; @TEGRA_CEC_RX_TIMING_2
	.comm	_TEGRA_CEC_RX_TIM2_END_OF_BLOCK_TIME_SHIFT,4,2 ; @TEGRA_CEC_RX_TIM2_END_OF_BLOCK_TIME_SHIFT
	.comm	_TEGRA_CEC_TX_TIMING_0,4,2      ; @TEGRA_CEC_TX_TIMING_0
	.comm	_TEGRA_CEC_TX_TIM0_START_BIT_LO_TIME_SHIFT,4,2 ; @TEGRA_CEC_TX_TIM0_START_BIT_LO_TIME_SHIFT
	.comm	_TEGRA_CEC_TX_TIM0_START_BIT_DURATION_SHIFT,4,2 ; @TEGRA_CEC_TX_TIM0_START_BIT_DURATION_SHIFT
	.comm	_TEGRA_CEC_TX_TIM0_BUS_XITION_TIME_SHIFT,4,2 ; @TEGRA_CEC_TX_TIM0_BUS_XITION_TIME_SHIFT
	.comm	_TEGRA_CEC_TX_TIM0_BUS_ERROR_LO_TIME_SHIFT,4,2 ; @TEGRA_CEC_TX_TIM0_BUS_ERROR_LO_TIME_SHIFT
	.comm	_TEGRA_CEC_TX_TIMING_1,4,2      ; @TEGRA_CEC_TX_TIMING_1
	.comm	_TEGRA_CEC_TX_TIM1_LO_DATA_BIT_LO_TIME_SHIFT,4,2 ; @TEGRA_CEC_TX_TIM1_LO_DATA_BIT_LO_TIME_SHIFT
	.comm	_TEGRA_CEC_TX_TIM1_HI_DATA_BIT_LO_TIME_SHIFT,4,2 ; @TEGRA_CEC_TX_TIM1_HI_DATA_BIT_LO_TIME_SHIFT
	.comm	_TEGRA_CEC_TX_TIM1_DATA_BIT_DURATION_SHIFT,4,2 ; @TEGRA_CEC_TX_TIM1_DATA_BIT_DURATION_SHIFT
	.comm	_TEGRA_CEC_TX_TIM1_ACK_NAK_BIT_SAMPLE_TIME_SHIFT,4,2 ; @TEGRA_CEC_TX_TIM1_ACK_NAK_BIT_SAMPLE_TIME_SHIFT
	.comm	_TEGRA_CEC_TX_TIMING_2,4,2      ; @TEGRA_CEC_TX_TIMING_2
	.comm	_TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_ADDITIONAL_FRAME_SHIFT,4,2 ; @TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_ADDITIONAL_FRAME_SHIFT
	.comm	_TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_NEW_FRAME_SHIFT,4,2 ; @TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_NEW_FRAME_SHIFT
	.comm	_TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_RETRY_FRAME_SHIFT,4,2 ; @TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_RETRY_FRAME_SHIFT
	.comm	_TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN,4,2 ; @TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN
	.comm	_TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD,4,2 ; @TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD
	.comm	_TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED,4,2 ; @TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED
	.comm	_TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED,4,2 ; @TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED
	.comm	_TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED,4,2 ; @TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED
	.comm	_TEGRA_CEC_INT_MASK_RX_REGISTER_FULL,4,2 ; @TEGRA_CEC_INT_MASK_RX_REGISTER_FULL
	.comm	_TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED,4,2 ; @TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED
	.comm	_TEGRA_CEC_HWCTRL_TX_RX_MODE,4,2 ; @TEGRA_CEC_HWCTRL_TX_RX_MODE
	.no_dead_strip	_tegra_cec_adap_enable
.subsections_via_symbols
