	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function set_reg_umr_segment
_set_reg_umr_segment:                   ## @set_reg_umr_segment
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %r12d
	movq	%rdx, %r15
	movq	%rsi, %r14
	movq	%rdi, %rbx
	movq	%rdx, %rdi
	callq	_umr_wr
	movq	%rax, %r13
	movq	%r14, %rdi
	xorl	%esi, %esi
	movl	$32, %edx
	callq	_memset
	cmpl	$0, 8(%r13)
	jne	LBB0_5
## %bb.1:
	movq	_MLX5_IB_SEND_UMR_FAIL_IF_FREE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%r15), %eax
	jne	LBB0_2
## %bb.3:
	movq	_MLX5_UMR_CHECK_NOT_FREE@GOTPCREL(%rip), %rax
	jmp	LBB0_4
LBB0_2:
	movq	_MLX5_UMR_CHECK_FREE@GOTPCREL(%rip), %rax
LBB0_4:
	movl	(%rax), %eax
	movl	%eax, 4(%r14)
LBB0_5:
	movl	4(%r13), %edi
	callq	_get_xlt_octo
	movl	%eax, %edi
	callq	_cpu_to_be16
	movq	%rax, 24(%r14)
	movl	(%r15), %eax
	movq	_MLX5_IB_SEND_UMR_UPDATE_XLT@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_7
## %bb.6:
	movl	(%r13), %edi
	callq	_get_xlt_octo
	movq	%rbx, %r13
	movl	%eax, %ebx
	movzwl	%bx, %edi
	callq	_cpu_to_be16
	movq	%rax, 16(%r14)
	sarl	$16, %ebx
	movl	%ebx, %edi
	movq	%r13, %rbx
	callq	_cpu_to_be32
	movl	%eax, 8(%r14)
	movq	_MLX5_UMR_TRANSLATION_OFFSET_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, 4(%r14)
	movl	(%r15), %eax
LBB0_7:
	movq	_MLX5_IB_SEND_UMR_UPDATE_TRANSLATION@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_9
## %bb.8:
	xorl	%eax, %eax
	callq	_get_umr_update_translation_mask
	orl	%eax, (%r14)
	movl	(%r15), %eax
LBB0_9:
	movq	_MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_11
## %bb.10:
	movl	%r12d, %edi
	callq	_get_umr_update_access_mask
	orl	%eax, (%r14)
	xorl	%eax, %eax
	callq	_get_umr_update_pd_mask
	orl	%eax, (%r14)
	movl	(%r15), %eax
LBB0_11:
	movq	_MLX5_IB_SEND_UMR_ENABLE_MR@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_13
## %bb.12:
	xorl	%eax, %eax
	callq	_get_umr_enable_mr_mask
	orl	%eax, (%r14)
	movl	(%r15), %eax
LBB0_13:
	movq	_MLX5_IB_SEND_UMR_DISABLE_MR@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_15
## %bb.14:
	xorl	%eax, %eax
	callq	_get_umr_disable_mr_mask
	orl	%eax, (%r14)
LBB0_15:
	cmpl	$0, 4(%r15)
	jne	LBB0_17
## %bb.16:
	movq	_MLX5_UMR_INLINE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, 4(%r14)
LBB0_17:
	movl	(%r14), %edi
	callq	_be64_to_cpu
	movq	%rbx, %rdi
	movl	%eax, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_umr_check_mkey_mask            ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_MLX5_IB_SEND_UMR_FAIL_IF_FREE,4,2 ## @MLX5_IB_SEND_UMR_FAIL_IF_FREE
	.comm	_MLX5_UMR_CHECK_FREE,4,2        ## @MLX5_UMR_CHECK_FREE
	.comm	_MLX5_UMR_CHECK_NOT_FREE,4,2    ## @MLX5_UMR_CHECK_NOT_FREE
	.comm	_MLX5_IB_SEND_UMR_UPDATE_XLT,4,2 ## @MLX5_IB_SEND_UMR_UPDATE_XLT
	.comm	_MLX5_UMR_TRANSLATION_OFFSET_EN,4,2 ## @MLX5_UMR_TRANSLATION_OFFSET_EN
	.comm	_MLX5_IB_SEND_UMR_UPDATE_TRANSLATION,4,2 ## @MLX5_IB_SEND_UMR_UPDATE_TRANSLATION
	.comm	_MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS,4,2 ## @MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS
	.comm	_MLX5_IB_SEND_UMR_ENABLE_MR,4,2 ## @MLX5_IB_SEND_UMR_ENABLE_MR
	.comm	_MLX5_IB_SEND_UMR_DISABLE_MR,4,2 ## @MLX5_IB_SEND_UMR_DISABLE_MR
	.comm	_MLX5_UMR_INLINE,4,2            ## @MLX5_UMR_INLINE
	.no_dead_strip	_set_reg_umr_segment
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function set_reg_umr_segment
_set_reg_umr_segment:                   ; @set_reg_umr_segment
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x22, x3
	mov	x21, x2
	mov	x20, x1
	mov	x19, x0
	mov	x0, x2
	bl	_umr_wr
	mov	x23, x0
	mov	x0, x20
	mov	w1, #0
	mov	w2, #32
	bl	_memset
	ldr	w8, [x23, #8]
	cbnz	w8, LBB0_2
; %bb.1:
	ldr	w8, [x21]
Lloh0:
	adrp	x9, _MLX5_IB_SEND_UMR_FAIL_IF_FREE@GOTPAGE
Lloh1:
	ldr	x9, [x9, _MLX5_IB_SEND_UMR_FAIL_IF_FREE@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
Lloh3:
	adrp	x10, _MLX5_UMR_CHECK_NOT_FREE@GOTPAGE
Lloh4:
	ldr	x10, [x10, _MLX5_UMR_CHECK_NOT_FREE@GOTPAGEOFF]
Lloh5:
	adrp	x11, _MLX5_UMR_CHECK_FREE@GOTPAGE
Lloh6:
	ldr	x11, [x11, _MLX5_UMR_CHECK_FREE@GOTPAGEOFF]
	tst	w9, w8
	csel	x8, x10, x11, eq
	ldr	w8, [x8]
	str	w8, [x20, #4]
LBB0_2:
	ldr	w0, [x23, #4]
	bl	_get_xlt_octo
	bl	_cpu_to_be16
	str	x0, [x20, #24]
	ldr	w8, [x21]
Lloh7:
	adrp	x9, _MLX5_IB_SEND_UMR_UPDATE_XLT@GOTPAGE
Lloh8:
	ldr	x9, [x9, _MLX5_IB_SEND_UMR_UPDATE_XLT@GOTPAGEOFF]
Lloh9:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_4
; %bb.3:
	ldr	w0, [x23]
	bl	_get_xlt_octo
	mov	x23, x0
	and	w0, w0, #0xffff
	bl	_cpu_to_be16
	str	x0, [x20, #16]
	asr	w0, w23, #16
	bl	_cpu_to_be32
Lloh10:
	adrp	x8, _MLX5_UMR_TRANSLATION_OFFSET_EN@GOTPAGE
Lloh11:
	ldr	x8, [x8, _MLX5_UMR_TRANSLATION_OFFSET_EN@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	ldr	w9, [x20, #4]
	orr	w8, w9, w8
	stp	w8, w0, [x20, #4]
	ldr	w8, [x21]
LBB0_4:
Lloh13:
	adrp	x9, _MLX5_IB_SEND_UMR_UPDATE_TRANSLATION@GOTPAGE
Lloh14:
	ldr	x9, [x9, _MLX5_IB_SEND_UMR_UPDATE_TRANSLATION@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_6
; %bb.5:
	bl	_get_umr_update_translation_mask
	ldr	w8, [x20]
	orr	w8, w8, w0
	str	w8, [x20]
	ldr	w8, [x21]
LBB0_6:
Lloh16:
	adrp	x9, _MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS@GOTPAGE
Lloh17:
	ldr	x9, [x9, _MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_8
; %bb.7:
	mov	x0, x22
	bl	_get_umr_update_access_mask
	ldr	w8, [x20]
	orr	w8, w8, w0
	str	w8, [x20]
	bl	_get_umr_update_pd_mask
	ldr	w8, [x20]
	orr	w8, w8, w0
	str	w8, [x20]
	ldr	w8, [x21]
LBB0_8:
Lloh19:
	adrp	x9, _MLX5_IB_SEND_UMR_ENABLE_MR@GOTPAGE
Lloh20:
	ldr	x9, [x9, _MLX5_IB_SEND_UMR_ENABLE_MR@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_10
; %bb.9:
	bl	_get_umr_enable_mr_mask
	ldr	w8, [x20]
	orr	w8, w8, w0
	str	w8, [x20]
	ldr	w8, [x21]
LBB0_10:
Lloh22:
	adrp	x9, _MLX5_IB_SEND_UMR_DISABLE_MR@GOTPAGE
Lloh23:
	ldr	x9, [x9, _MLX5_IB_SEND_UMR_DISABLE_MR@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_12
; %bb.11:
	bl	_get_umr_disable_mr_mask
	ldr	w8, [x20]
	orr	w8, w8, w0
	str	w8, [x20]
LBB0_12:
	ldr	w8, [x21, #4]
	cbnz	w8, LBB0_14
; %bb.13:
Lloh25:
	adrp	x8, _MLX5_UMR_INLINE@GOTPAGE
Lloh26:
	ldr	x8, [x8, _MLX5_UMR_INLINE@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
	ldr	w9, [x20, #4]
	orr	w8, w9, w8
	str	w8, [x20, #4]
LBB0_14:
	ldr	w0, [x20]
	bl	_be64_to_cpu
	mov	x1, x0
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_umr_check_mkey_mask
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.cfi_endproc
                                        ; -- End function
	.comm	_MLX5_IB_SEND_UMR_FAIL_IF_FREE,4,2 ; @MLX5_IB_SEND_UMR_FAIL_IF_FREE
	.comm	_MLX5_UMR_CHECK_FREE,4,2        ; @MLX5_UMR_CHECK_FREE
	.comm	_MLX5_UMR_CHECK_NOT_FREE,4,2    ; @MLX5_UMR_CHECK_NOT_FREE
	.comm	_MLX5_IB_SEND_UMR_UPDATE_XLT,4,2 ; @MLX5_IB_SEND_UMR_UPDATE_XLT
	.comm	_MLX5_UMR_TRANSLATION_OFFSET_EN,4,2 ; @MLX5_UMR_TRANSLATION_OFFSET_EN
	.comm	_MLX5_IB_SEND_UMR_UPDATE_TRANSLATION,4,2 ; @MLX5_IB_SEND_UMR_UPDATE_TRANSLATION
	.comm	_MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS,4,2 ; @MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS
	.comm	_MLX5_IB_SEND_UMR_ENABLE_MR,4,2 ; @MLX5_IB_SEND_UMR_ENABLE_MR
	.comm	_MLX5_IB_SEND_UMR_DISABLE_MR,4,2 ; @MLX5_IB_SEND_UMR_DISABLE_MR
	.comm	_MLX5_UMR_INLINE,4,2            ; @MLX5_UMR_INLINE
	.no_dead_strip	_set_reg_umr_segment
.subsections_via_symbols
