	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function bnx2x_hc_int_enable
_bnx2x_hc_int_enable:                   ## @bnx2x_hc_int_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	callq	_BP_PORT
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	LBB0_1
## %bb.2:
	movq	_HC_REG_CONFIG_0@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_1:
	movq	_HC_REG_CONFIG_1@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %r15d
	movq	%r12, %rdi
	movl	%r15d, %esi
	callq	_REG_RD
	movl	%eax, %ebx
	movl	(%r12), %r13d
	movq	_USING_MSIX_FLAG@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	_USING_MSI_FLAG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%r13d, %ecx
	movl	%ecx, -48(%rbp)                 ## 4-byte Spill
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	je	LBB0_5
## %bb.4:
	movq	_USING_SINGLE_MSIX_FLAG@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r13d, %eax
	movq	_HC_CONFIG_0_REG_SINGLE_ISR_EN_0@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	_HC_CONFIG_0_REG_INT_LINE_EN_0@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	%ecx, %edx
	notl	%edx
	andl	%edx, %ebx
	testl	%eax, %eax
	movq	_HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0@GOTPCREL(%rip), %rdx
	cmovnel	%ecx, %eax
	orl	(%rdx), %eax
	movq	_HC_CONFIG_0_REG_ATTN_BIT_EN_0@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	orl	%eax, %ebx
	jmp	LBB0_9
LBB0_5:
	testl	%r13d, %eax
	je	LBB0_7
## %bb.6:
	movq	_HC_CONFIG_0_REG_INT_LINE_EN_0@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %ebx
	movq	_HC_CONFIG_0_REG_SINGLE_ISR_EN_0@GOTPCREL(%rip), %rax
	movq	_HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0@GOTPCREL(%rip), %rcx
	movq	_HC_CONFIG_0_REG_ATTN_BIT_EN_0@GOTPCREL(%rip), %rdx
	orl	(%rax), %ebx
	orl	(%rcx), %ebx
	orl	(%rdx), %ebx
	jmp	LBB0_9
LBB0_7:
	movq	_HC_CONFIG_0_REG_SINGLE_ISR_EN_0@GOTPCREL(%rip), %rax
	movq	_HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0@GOTPCREL(%rip), %rsi
	movq	_HC_CONFIG_0_REG_INT_LINE_EN_0@GOTPCREL(%rip), %rcx
	movq	_HC_CONFIG_0_REG_ATTN_BIT_EN_0@GOTPCREL(%rip), %rdx
	orl	(%rax), %ebx
	orl	(%rsi), %ebx
	orl	(%rcx), %ebx
	orl	(%rdx), %ebx
	movq	%r12, %rdi
	callq	_CHIP_IS_E1
	testq	%rax, %rax
	jne	LBB0_9
## %bb.8:
	movq	_NETIF_MSG_IFUP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	leaq	L_.str(%rip), %rsi
	movl	%ebx, %edx
	movl	%r14d, %ecx
	movl	%r15d, %r8d
	xorl	%eax, %eax
	callq	_DP
	movq	%r12, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_REG_WR
	movq	_HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %ebx
LBB0_9:
	movq	%r12, %rdi
	callq	_CHIP_IS_E1
	testq	%rax, %rax
	je	LBB0_11
## %bb.10:
	movq	_HC_REG_INT_MASK@GOTPCREL(%rip), %rax
	leal	(,%r14,4), %esi
	addl	(%rax), %esi
	movq	%r12, %rdi
	movl	$131071, %edx                   ## imm = 0x1FFFF
	callq	_REG_WR
LBB0_11:
	testl	%r13d, -44(%rbp)                ## 4-byte Folded Reload
	leaq	L_.str.4(%rip), %rax
	leaq	L_.str.3(%rip), %rcx
	cmoveq	%rax, %rcx
	testl	%r13d, -48(%rbp)                ## 4-byte Folded Reload
	movq	_NETIF_MSG_IFUP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	leaq	L_.str.2(%rip), %r9
	cmoveq	%rcx, %r9
	leaq	L_.str.1(%rip), %rsi
	movl	%ebx, %edx
	movl	%r14d, %ecx
	movl	%r15d, %r8d
	xorl	%eax, %eax
	callq	_DP
	movq	%r12, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_REG_WR
	xorl	%eax, %eax
	callq	_barrier
	movq	%r12, %rdi
	callq	_CHIP_IS_E1
	testq	%rax, %rax
	je	LBB0_12
## %bb.16:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_12:
	movq	%r12, %rdi
	callq	_IS_MF
	testq	%rax, %rax
	je	LBB0_13
## %bb.14:
	movq	%r12, %rdi
	callq	_BP_VN
	addb	$4, %al
	cmpq	$0, 8(%r12)
	movl	$60943, %ecx                    ## imm = 0xEE0F
	movl	$65295, %ebx                    ## imm = 0xFF0F
	cmovel	%ecx, %ebx
	btsl	%eax, %ebx
	jmp	LBB0_15
LBB0_13:
	movl	$65535, %ebx                    ## imm = 0xFFFF
LBB0_15:
	movq	_HC_REG_TRAILING_EDGE_0@GOTPCREL(%rip), %rax
	shll	$3, %r14d
	movl	(%rax), %esi
	addl	%r14d, %esi
	movq	%r12, %rdi
	movl	%ebx, %edx
	callq	_REG_WR
	movq	_HC_REG_LEADING_EDGE_0@GOTPCREL(%rip), %rax
	addl	(%rax), %r14d
	movq	%r12, %rdi
	movl	%r14d, %esi
	movl	%ebx, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_REG_WR                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_HC_REG_CONFIG_1,4,2            ## @HC_REG_CONFIG_1
	.comm	_HC_REG_CONFIG_0,4,2            ## @HC_REG_CONFIG_0
	.comm	_USING_MSIX_FLAG,4,2            ## @USING_MSIX_FLAG
	.comm	_USING_SINGLE_MSIX_FLAG,4,2     ## @USING_SINGLE_MSIX_FLAG
	.comm	_USING_MSI_FLAG,4,2             ## @USING_MSI_FLAG
	.comm	_HC_CONFIG_0_REG_SINGLE_ISR_EN_0,4,2 ## @HC_CONFIG_0_REG_SINGLE_ISR_EN_0
	.comm	_HC_CONFIG_0_REG_INT_LINE_EN_0,4,2 ## @HC_CONFIG_0_REG_INT_LINE_EN_0
	.comm	_HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0,4,2 ## @HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
	.comm	_HC_CONFIG_0_REG_ATTN_BIT_EN_0,4,2 ## @HC_CONFIG_0_REG_ATTN_BIT_EN_0
	.comm	_NETIF_MSG_IFUP,4,2             ## @NETIF_MSG_IFUP
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"write %x to HC %d (addr 0x%x)\n"

	.comm	_HC_REG_INT_MASK,4,2            ## @HC_REG_INT_MASK
L_.str.1:                               ## @.str.1
	.asciz	"write %x to HC %d (addr 0x%x) mode %s\n"

L_.str.2:                               ## @.str.2
	.asciz	"MSI-X"

L_.str.3:                               ## @.str.3
	.asciz	"MSI"

L_.str.4:                               ## @.str.4
	.asciz	"INTx"

	.comm	_HC_REG_TRAILING_EDGE_0,4,2     ## @HC_REG_TRAILING_EDGE_0
	.comm	_HC_REG_LEADING_EDGE_0,4,2      ## @HC_REG_LEADING_EDGE_0
	.no_dead_strip	_bnx2x_hc_int_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function bnx2x_hc_int_enable
_bnx2x_hc_int_enable:                   ; @bnx2x_hc_int_enable
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	bl	_BP_PORT
	mov	x20, x0
Lloh0:
	adrp	x8, _HC_REG_CONFIG_1@GOTPAGE
Lloh1:
	ldr	x8, [x8, _HC_REG_CONFIG_1@GOTPAGEOFF]
Lloh2:
	adrp	x9, _HC_REG_CONFIG_0@GOTPAGE
Lloh3:
	ldr	x9, [x9, _HC_REG_CONFIG_0@GOTPAGEOFF]
	cmp	w0, #0
	csel	x8, x9, x8, eq
	ldr	w21, [x8]
	mov	x0, x19
	mov	x1, x21
	bl	_REG_RD
	ldr	w8, [x19]
Lloh4:
	adrp	x9, _USING_MSIX_FLAG@GOTPAGE
Lloh5:
	ldr	x9, [x9, _USING_MSIX_FLAG@GOTPAGEOFF]
Lloh6:
	adrp	x10, _USING_MSI_FLAG@GOTPAGE
Lloh7:
	ldr	x10, [x10, _USING_MSI_FLAG@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
Lloh9:
	ldr	w10, [x10]
	and	w24, w10, w8
Lloh10:
	adrp	x25, _NETIF_MSG_IFUP@GOTPAGE
Lloh11:
	ldr	x25, [x25, _NETIF_MSG_IFUP@GOTPAGEOFF]
	ands	w23, w9, w8
	b.eq	LBB0_2
; %bb.1:
Lloh12:
	adrp	x9, _USING_SINGLE_MSIX_FLAG@GOTPAGE
Lloh13:
	ldr	x9, [x9, _USING_SINGLE_MSIX_FLAG@GOTPAGEOFF]
Lloh14:
	adrp	x10, _HC_CONFIG_0_REG_SINGLE_ISR_EN_0@GOTPAGE
Lloh15:
	ldr	x10, [x10, _HC_CONFIG_0_REG_SINGLE_ISR_EN_0@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
Lloh17:
	ldr	w10, [x10]
Lloh18:
	adrp	x11, _HC_CONFIG_0_REG_INT_LINE_EN_0@GOTPAGE
Lloh19:
	ldr	x11, [x11, _HC_CONFIG_0_REG_INT_LINE_EN_0@GOTPAGEOFF]
Lloh20:
	ldr	w11, [x11]
	orr	w11, w11, w10
	bic	w11, w0, w11
Lloh21:
	adrp	x12, _HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0@GOTPAGE
Lloh22:
	ldr	x12, [x12, _HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0@GOTPAGEOFF]
Lloh23:
	ldr	w12, [x12]
Lloh24:
	adrp	x13, _HC_CONFIG_0_REG_ATTN_BIT_EN_0@GOTPAGE
Lloh25:
	ldr	x13, [x13, _HC_CONFIG_0_REG_ATTN_BIT_EN_0@GOTPAGEOFF]
Lloh26:
	ldr	w13, [x13]
	tst	w9, w8
	csel	w8, wzr, w10, eq
	orr	w8, w8, w12
	orr	w8, w8, w13
	orr	w22, w8, w11
	b	LBB0_6
LBB0_2:
	cbz	w24, LBB0_4
; %bb.3:
Lloh27:
	adrp	x8, _HC_CONFIG_0_REG_INT_LINE_EN_0@GOTPAGE
Lloh28:
	ldr	x8, [x8, _HC_CONFIG_0_REG_INT_LINE_EN_0@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh30:
	adrp	x9, _HC_CONFIG_0_REG_SINGLE_ISR_EN_0@GOTPAGE
Lloh31:
	ldr	x9, [x9, _HC_CONFIG_0_REG_SINGLE_ISR_EN_0@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
Lloh33:
	adrp	x10, _HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0@GOTPAGE
Lloh34:
	ldr	x10, [x10, _HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0@GOTPAGEOFF]
Lloh35:
	ldr	w10, [x10]
Lloh36:
	adrp	x11, _HC_CONFIG_0_REG_ATTN_BIT_EN_0@GOTPAGE
Lloh37:
	ldr	x11, [x11, _HC_CONFIG_0_REG_ATTN_BIT_EN_0@GOTPAGEOFF]
Lloh38:
	ldr	w11, [x11]
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w22, w8, w11
	b	LBB0_6
LBB0_4:
Lloh39:
	adrp	x8, _HC_CONFIG_0_REG_SINGLE_ISR_EN_0@GOTPAGE
Lloh40:
	ldr	x8, [x8, _HC_CONFIG_0_REG_SINGLE_ISR_EN_0@GOTPAGEOFF]
Lloh41:
	adrp	x26, _HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0@GOTPAGE
Lloh42:
	ldr	x26, [x26, _HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0@GOTPAGEOFF]
Lloh43:
	ldr	w8, [x8]
	ldr	w9, [x26]
Lloh44:
	adrp	x10, _HC_CONFIG_0_REG_INT_LINE_EN_0@GOTPAGE
Lloh45:
	ldr	x10, [x10, _HC_CONFIG_0_REG_INT_LINE_EN_0@GOTPAGEOFF]
Lloh46:
	adrp	x11, _HC_CONFIG_0_REG_ATTN_BIT_EN_0@GOTPAGE
Lloh47:
	ldr	x11, [x11, _HC_CONFIG_0_REG_ATTN_BIT_EN_0@GOTPAGEOFF]
Lloh48:
	ldr	w10, [x10]
Lloh49:
	ldr	w11, [x11]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w22, w8, w11
	mov	x0, x19
	bl	_CHIP_IS_E1
	cbnz	x0, LBB0_6
; %bb.5:
	ldr	w0, [x25]
Lloh50:
	adrp	x1, l_.str@PAGE
Lloh51:
	add	x1, x1, l_.str@PAGEOFF
	mov	x2, x22
	mov	x3, x20
	mov	x4, x21
	bl	_DP
	mov	x0, x19
	mov	x1, x21
	mov	x2, x22
	bl	_REG_WR
	ldr	w8, [x26]
	bic	w22, w22, w8
LBB0_6:
	mov	x0, x19
	bl	_CHIP_IS_E1
	cbz	x0, LBB0_8
; %bb.7:
Lloh52:
	adrp	x8, _HC_REG_INT_MASK@GOTPAGE
Lloh53:
	ldr	x8, [x8, _HC_REG_INT_MASK@GOTPAGEOFF]
Lloh54:
	ldr	w8, [x8]
	add	w1, w8, w20, lsl #2
	mov	x0, x19
	mov	w2, #131071
	bl	_REG_WR
LBB0_8:
	ldr	w0, [x25]
Lloh55:
	adrp	x8, l_.str.3@PAGE
Lloh56:
	add	x8, x8, l_.str.3@PAGEOFF
Lloh57:
	adrp	x9, l_.str.4@PAGE
Lloh58:
	add	x9, x9, l_.str.4@PAGEOFF
	cmp	w24, #0
	csel	x8, x9, x8, eq
Lloh59:
	adrp	x9, l_.str.2@PAGE
Lloh60:
	add	x9, x9, l_.str.2@PAGEOFF
	cmp	w23, #0
	csel	x8, x8, x9, eq
Lloh61:
	adrp	x1, l_.str.1@PAGE
Lloh62:
	add	x1, x1, l_.str.1@PAGEOFF
	str	x8, [sp]
	mov	x2, x22
	mov	x3, x20
	mov	x4, x21
	bl	_DP
	mov	x0, x19
	mov	x1, x21
	mov	x2, x22
	bl	_REG_WR
	bl	_barrier
	mov	x0, x19
	bl	_CHIP_IS_E1
	cbz	x0, LBB0_10
; %bb.9:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_10:
	mov	x0, x19
	bl	_IS_MF
	cbz	x0, LBB0_12
; %bb.11:
	mov	x0, x19
	bl	_BP_VN
	add	w8, w0, #4
	mov	w9, #1
	lsl	w8, w9, w8
	ldr	x9, [x19, #8]
	cmp	x9, #0
	mov	w9, #65295
	mov	w10, #60943
	csel	w9, w10, w9, eq
	orr	w21, w9, w8
	b	LBB0_13
LBB0_12:
	mov	w21, #65535
LBB0_13:
Lloh63:
	adrp	x8, _HC_REG_TRAILING_EDGE_0@GOTPAGE
Lloh64:
	ldr	x8, [x8, _HC_REG_TRAILING_EDGE_0@GOTPAGEOFF]
Lloh65:
	ldr	w8, [x8]
	lsl	w20, w20, #3
	add	w1, w8, w20
	mov	x0, x19
	mov	x2, x21
	bl	_REG_WR
Lloh66:
	adrp	x8, _HC_REG_LEADING_EDGE_0@GOTPAGE
Lloh67:
	ldr	x8, [x8, _HC_REG_LEADING_EDGE_0@GOTPAGEOFF]
Lloh68:
	ldr	w8, [x8]
	add	w1, w8, w20
	mov	x0, x19
	mov	x2, x21
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	b	_REG_WR
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh8
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh16
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh48
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh43
	.loh AdrpAdd	Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpAdd	Lloh61, Lloh62
	.loh AdrpAdd	Lloh59, Lloh60
	.loh AdrpAdd	Lloh57, Lloh58
	.loh AdrpAdd	Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.cfi_endproc
                                        ; -- End function
	.comm	_HC_REG_CONFIG_1,4,2            ; @HC_REG_CONFIG_1
	.comm	_HC_REG_CONFIG_0,4,2            ; @HC_REG_CONFIG_0
	.comm	_USING_MSIX_FLAG,4,2            ; @USING_MSIX_FLAG
	.comm	_USING_SINGLE_MSIX_FLAG,4,2     ; @USING_SINGLE_MSIX_FLAG
	.comm	_USING_MSI_FLAG,4,2             ; @USING_MSI_FLAG
	.comm	_HC_CONFIG_0_REG_SINGLE_ISR_EN_0,4,2 ; @HC_CONFIG_0_REG_SINGLE_ISR_EN_0
	.comm	_HC_CONFIG_0_REG_INT_LINE_EN_0,4,2 ; @HC_CONFIG_0_REG_INT_LINE_EN_0
	.comm	_HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0,4,2 ; @HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
	.comm	_HC_CONFIG_0_REG_ATTN_BIT_EN_0,4,2 ; @HC_CONFIG_0_REG_ATTN_BIT_EN_0
	.comm	_NETIF_MSG_IFUP,4,2             ; @NETIF_MSG_IFUP
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"write %x to HC %d (addr 0x%x)\n"

	.comm	_HC_REG_INT_MASK,4,2            ; @HC_REG_INT_MASK
l_.str.1:                               ; @.str.1
	.asciz	"write %x to HC %d (addr 0x%x) mode %s\n"

l_.str.2:                               ; @.str.2
	.asciz	"MSI-X"

l_.str.3:                               ; @.str.3
	.asciz	"MSI"

l_.str.4:                               ; @.str.4
	.asciz	"INTx"

	.comm	_HC_REG_TRAILING_EDGE_0,4,2     ; @HC_REG_TRAILING_EDGE_0
	.comm	_HC_REG_LEADING_EDGE_0,4,2      ; @HC_REG_LEADING_EDGE_0
	.no_dead_strip	_bnx2x_hc_int_enable
.subsections_via_symbols
