	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_goya_late_init                 ## -- Begin function goya_late_init
	.p2align	4, 0x90
_goya_late_init:                        ## @goya_late_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %r14
	callq	_goya_fetch_psoc_frequency
	movq	%r14, %rdi
	callq	_goya_mmu_clear_pgt_range
	testl	%eax, %eax
	je	LBB0_3
## %bb.1:
	movl	%eax, %ebx
	movl	(%r14), %edi
	leaq	L_.str(%rip), %rsi
	jmp	LBB0_2
LBB0_3:
	movq	%r14, %rdi
	callq	_goya_mmu_set_dram_default_page
	testl	%eax, %eax
	je	LBB0_5
## %bb.4:
	movl	%eax, %ebx
	movl	(%r14), %edi
	leaq	L_.str.1(%rip), %rsi
LBB0_2:
	movl	%ebx, %edx
	callq	_dev_err
LBB0_13:
	movl	%ebx, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
LBB0_5:
	movq	%r14, %rdi
	callq	_goya_mmu_add_mappings_for_device_cpu
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_13
## %bb.6:
	movq	%r14, %rdi
	callq	_goya_init_cpu_queues
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_13
## %bb.7:
	movq	%r14, %rdi
	callq	_goya_test_cpu_queue
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_13
## %bb.8:
	movq	%r14, %rdi
	callq	_goya_armcp_info_get
	testl	%eax, %eax
	je	LBB0_10
## %bb.9:
	movl	%eax, %ebx
	movl	(%r14), %edi
	leaq	L_.str.2(%rip), %rsi
	jmp	LBB0_2
LBB0_10:
	movq	_mmMMU_LOG2_DDR_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	4(%r14), %edi
	callq	_ilog2
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_WREG32
	movq	_ARMCP_PACKET_ENABLE_PCI_ACCESS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_hl_fw_send_pci_access_msg
	testl	%eax, %eax
	je	LBB0_12
## %bb.11:
	movl	%eax, %ebx
	movl	(%r14), %edi
	leaq	L_.str.3(%rip), %rsi
	jmp	LBB0_2
LBB0_12:
	movq	_mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_GOYA_ASYNC_EVENT_ID_INTS_REGISTER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_WREG32
	xorl	%ebx, %ebx
	jmp	LBB0_13
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Failed to clear MMU page tables range %d\n"

L_.str.1:                               ## @.str.1
	.asciz	"Failed to set DRAM default page %d\n"

L_.str.2:                               ## @.str.2
	.asciz	"Failed to get armcp info %d\n"

	.comm	_mmMMU_LOG2_DDR_SIZE,4,2        ## @mmMMU_LOG2_DDR_SIZE
	.comm	_ARMCP_PACKET_ENABLE_PCI_ACCESS,4,2 ## @ARMCP_PACKET_ENABLE_PCI_ACCESS
L_.str.3:                               ## @.str.3
	.asciz	"Failed to enable PCI access from CPU %d\n"

	.comm	_mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,4,2 ## @mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR
	.comm	_GOYA_ASYNC_EVENT_ID_INTS_REGISTER,4,2 ## @GOYA_ASYNC_EVENT_ID_INTS_REGISTER
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_goya_late_init                 ; -- Begin function goya_late_init
	.p2align	2
_goya_late_init:                        ; @goya_late_init
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_goya_fetch_psoc_frequency
	mov	x0, x19
	bl	_goya_mmu_clear_pgt_range
	cbz	w0, LBB0_2
; %bb.1:
	mov	x20, x0
	ldr	w0, [x19]
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	b	LBB0_4
LBB0_2:
	mov	x0, x19
	bl	_goya_mmu_set_dram_default_page
	cbz	w0, LBB0_6
; %bb.3:
	mov	x20, x0
	ldr	w0, [x19]
Lloh2:
	adrp	x1, l_.str.1@PAGE
Lloh3:
	add	x1, x1, l_.str.1@PAGEOFF
LBB0_4:
	mov	x2, x20
	bl	_dev_err
LBB0_5:
	mov	x0, x20
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_6:
	mov	x0, x19
	bl	_goya_mmu_add_mappings_for_device_cpu
	mov	x20, x0
	cbnz	w0, LBB0_5
; %bb.7:
	mov	x0, x19
	bl	_goya_init_cpu_queues
	mov	x20, x0
	cbnz	w0, LBB0_5
; %bb.8:
	mov	x0, x19
	bl	_goya_test_cpu_queue
	mov	x20, x0
	cbnz	w0, LBB0_5
; %bb.9:
	mov	x0, x19
	bl	_goya_armcp_info_get
	cbz	w0, LBB0_11
; %bb.10:
	mov	x20, x0
	ldr	w0, [x19]
Lloh4:
	adrp	x1, l_.str.2@PAGE
Lloh5:
	add	x1, x1, l_.str.2@PAGEOFF
	b	LBB0_4
LBB0_11:
Lloh6:
	adrp	x8, _mmMMU_LOG2_DDR_SIZE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _mmMMU_LOG2_DDR_SIZE@GOTPAGEOFF]
Lloh8:
	ldr	w20, [x8]
	ldr	w0, [x19, #4]
	bl	_ilog2
	mov	x1, x0
	mov	x0, x20
	bl	_WREG32
Lloh9:
	adrp	x8, _ARMCP_PACKET_ENABLE_PCI_ACCESS@GOTPAGE
Lloh10:
	ldr	x8, [x8, _ARMCP_PACKET_ENABLE_PCI_ACCESS@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_hl_fw_send_pci_access_msg
	mov	x20, x0
	cbz	w0, LBB0_13
; %bb.12:
	ldr	w0, [x19]
Lloh12:
	adrp	x1, l_.str.3@PAGE
Lloh13:
	add	x1, x1, l_.str.3@PAGEOFF
	b	LBB0_4
LBB0_13:
Lloh14:
	adrp	x8, _mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR@GOTPAGE
Lloh15:
	ldr	x8, [x8, _mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
Lloh17:
	adrp	x8, _GOYA_ASYNC_EVENT_ID_INTS_REGISTER@GOTPAGE
Lloh18:
	ldr	x8, [x8, _GOYA_ASYNC_EVENT_ID_INTS_REGISTER@GOTPAGEOFF]
Lloh19:
	ldr	w1, [x8]
	bl	_WREG32
	b	LBB0_5
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpAdd	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Failed to clear MMU page tables range %d\n"

l_.str.1:                               ; @.str.1
	.asciz	"Failed to set DRAM default page %d\n"

l_.str.2:                               ; @.str.2
	.asciz	"Failed to get armcp info %d\n"

	.comm	_mmMMU_LOG2_DDR_SIZE,4,2        ; @mmMMU_LOG2_DDR_SIZE
	.comm	_ARMCP_PACKET_ENABLE_PCI_ACCESS,4,2 ; @ARMCP_PACKET_ENABLE_PCI_ACCESS
l_.str.3:                               ; @.str.3
	.asciz	"Failed to enable PCI access from CPU %d\n"

	.comm	_mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,4,2 ; @mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR
	.comm	_GOYA_ASYNC_EVENT_ID_INTS_REGISTER,4,2 ; @GOYA_ASYNC_EVENT_ID_INTS_REGISTER
.subsections_via_symbols
