	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function write_8051
_write_8051:                            ## @write_8051
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%r8d, %ebx
	movq	%rcx, -56(%rbp)                 ## 8-byte Spill
	movl	%edx, %r12d
	movl	%esi, %edx
	movq	%rdi, %r15
	movq	_DC_DC8051_CFG_RAM_ACCESS_SETUP_AUTO_INCR_ADDR_SMASK@GOTPCREL(%rip), %rax
	testl	%esi, %esi
	je	LBB0_2
## %bb.1:
	movq	_DC_DC8051_CFG_RAM_ACCESS_SETUP_RAM_SEL_SMASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
LBB0_2:
	orl	(%rax), %edx
	movq	_DC_DC8051_CFG_RAM_ACCESS_SETUP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_write_csr
	movq	_DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %r12d
	movq	_DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r12d
	movq	_DC_DC8051_CFG_RAM_ACCESS_CTRL_WRITE_ENA_SMASK@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
	movl	%r12d, -44(%rbp)
	movq	_DC_DC8051_CFG_RAM_ACCESS_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%r12d, %edx
	callq	_write_csr
	testl	%ebx, %ebx
	jle	LBB0_16
## %bb.3:
	xorl	%r13d, %r13d
	movq	_DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK@GOTPCREL(%rip), %r12
	movl	%ebx, -48(%rbp)                 ## 4-byte Spill
	jmp	LBB0_4
	.p2align	4, 0x90
LBB0_15:                                ##   in Loop: Header=BB0_4 Depth=1
	addq	$8, %r13
	movl	-48(%rbp), %ebx                 ## 4-byte Reload
	cmpl	%ebx, %r13d
	jge	LBB0_16
LBB0_4:                                 ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_12 Depth 2
	subl	%r13d, %ebx
	cmpl	$7, %ebx
	jg	LBB0_6
## %bb.5:                               ##   in Loop: Header=BB0_4 Depth=1
	movl	$0, -44(%rbp)
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	leaq	(%rax,%r13,4), %rsi
	leaq	-44(%rbp), %rdi
	movl	%ebx, %edx
	jmp	LBB0_9
	.p2align	4, 0x90
LBB0_6:                                 ##   in Loop: Header=BB0_4 Depth=1
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	leaq	(%rax,%r13,4), %rsi
	testb	$7, %al
	je	LBB0_7
## %bb.8:                               ##   in Loop: Header=BB0_4 Depth=1
	leaq	-44(%rbp), %rdi
	movl	$8, %edx
LBB0_9:                                 ##   in Loop: Header=BB0_4 Depth=1
	callq	_memcpy
LBB0_10:                                ##   in Loop: Header=BB0_4 Depth=1
	movq	_DC_DC8051_CFG_RAM_ACCESS_STATUS@GOTPCREL(%rip), %rbx
	movq	_DC_DC8051_CFG_RAM_ACCESS_WR_DATA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-44(%rbp), %edx
	movq	%r15, %rdi
	callq	_write_csr
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_read_csr
	testl	%eax, (%r12)
	jne	LBB0_15
## %bb.11:                              ##   in Loop: Header=BB0_4 Depth=1
	movl	$-1, %r14d
	.p2align	4, 0x90
LBB0_12:                                ##   Parent Loop BB0_4 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	incl	%r14d
	movq	_DC8051_ACCESS_TIMEOUT@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r14d
	jge	LBB0_13
## %bb.14:                              ##   in Loop: Header=BB0_12 Depth=2
	movl	$1, %edi
	callq	_udelay
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_read_csr
	testl	%eax, (%r12)
	je	LBB0_12
	jmp	LBB0_15
LBB0_7:                                 ##   in Loop: Header=BB0_4 Depth=1
	movl	(%rsi), %eax
	movl	%eax, -44(%rbp)
	jmp	LBB0_10
LBB0_13:
	leaq	L_.str(%rip), %rsi
	movq	%r15, %rdi
	callq	_dd_dev_err
	movq	_ENXIO@GOTPCREL(%rip), %rax
	xorl	%r14d, %r14d
	subl	(%rax), %r14d
	jmp	LBB0_17
LBB0_16:
	movq	_DC_DC8051_CFG_RAM_ACCESS_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%r14d, %r14d
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_write_csr
	movq	_DC_DC8051_CFG_RAM_ACCESS_SETUP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_write_csr
LBB0_17:
	movl	%r14d, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DC_DC8051_CFG_RAM_ACCESS_SETUP_RAM_SEL_SMASK,8,3 ## @DC_DC8051_CFG_RAM_ACCESS_SETUP_RAM_SEL_SMASK
	.comm	_DC_DC8051_CFG_RAM_ACCESS_SETUP_AUTO_INCR_ADDR_SMASK,8,3 ## @DC_DC8051_CFG_RAM_ACCESS_SETUP_AUTO_INCR_ADDR_SMASK
	.comm	_DC_DC8051_CFG_RAM_ACCESS_SETUP,4,2 ## @DC_DC8051_CFG_RAM_ACCESS_SETUP
	.comm	_DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK,4,2 ## @DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK
	.comm	_DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT,4,2 ## @DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT
	.comm	_DC_DC8051_CFG_RAM_ACCESS_CTRL_WRITE_ENA_SMASK,4,2 ## @DC_DC8051_CFG_RAM_ACCESS_CTRL_WRITE_ENA_SMASK
	.comm	_DC_DC8051_CFG_RAM_ACCESS_CTRL,4,2 ## @DC_DC8051_CFG_RAM_ACCESS_CTRL
	.comm	_DC_DC8051_CFG_RAM_ACCESS_WR_DATA,4,2 ## @DC_DC8051_CFG_RAM_ACCESS_WR_DATA
	.comm	_DC_DC8051_CFG_RAM_ACCESS_STATUS,4,2 ## @DC_DC8051_CFG_RAM_ACCESS_STATUS
	.comm	_DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK,4,2 ## @DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK
	.comm	_DC8051_ACCESS_TIMEOUT,4,2      ## @DC8051_ACCESS_TIMEOUT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"timeout writing 8051 data\n"

	.comm	_ENXIO,4,2                      ## @ENXIO
	.no_dead_strip	_write_8051
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function write_8051
_write_8051:                            ; @write_8051
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x20, x4
	mov	x21, x3
	mov	x22, x2
	mov	x19, x0
Lloh0:
	adrp	x8, _DC_DC8051_CFG_RAM_ACCESS_SETUP_RAM_SEL_SMASK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DC_DC8051_CFG_RAM_ACCESS_SETUP_RAM_SEL_SMASK@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _DC_DC8051_CFG_RAM_ACCESS_SETUP_AUTO_INCR_ADDR_SMASK@GOTPAGE
Lloh4:
	ldr	x9, [x9, _DC_DC8051_CFG_RAM_ACCESS_SETUP_AUTO_INCR_ADDR_SMASK@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	cmp	w1, #0
	csel	w8, wzr, w8, eq
	orr	w2, w8, w9
Lloh6:
	adrp	x8, _DC_DC8051_CFG_RAM_ACCESS_SETUP@GOTPAGE
Lloh7:
	ldr	x8, [x8, _DC_DC8051_CFG_RAM_ACCESS_SETUP@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	bl	_write_csr
Lloh9:
	adrp	x8, _DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	and	w8, w8, w22
Lloh12:
	adrp	x9, _DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT@GOTPAGE
Lloh13:
	ldr	x9, [x9, _DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	lsl	w8, w8, w9
Lloh15:
	adrp	x9, _DC_DC8051_CFG_RAM_ACCESS_CTRL_WRITE_ENA_SMASK@GOTPAGE
Lloh16:
	ldr	x9, [x9, _DC_DC8051_CFG_RAM_ACCESS_CTRL_WRITE_ENA_SMASK@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	orr	w2, w8, w9
	str	w2, [sp, #12]
Lloh18:
	adrp	x8, _DC_DC8051_CFG_RAM_ACCESS_CTRL@GOTPAGE
Lloh19:
	ldr	x8, [x8, _DC_DC8051_CFG_RAM_ACCESS_CTRL@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_write_csr
	cmp	w20, #1
	b.lt	LBB0_14
; %bb.1:
	mov	x24, #0
	and	x25, x21, #0x7
Lloh21:
	adrp	x26, _DC_DC8051_CFG_RAM_ACCESS_WR_DATA@GOTPAGE
Lloh22:
	ldr	x26, [x26, _DC_DC8051_CFG_RAM_ACCESS_WR_DATA@GOTPAGEOFF]
Lloh23:
	adrp	x27, _DC_DC8051_CFG_RAM_ACCESS_STATUS@GOTPAGE
Lloh24:
	ldr	x27, [x27, _DC_DC8051_CFG_RAM_ACCESS_STATUS@GOTPAGEOFF]
Lloh25:
	adrp	x28, _DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK@GOTPAGE
Lloh26:
	ldr	x28, [x28, _DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK@GOTPAGEOFF]
Lloh27:
	adrp	x23, _DC8051_ACCESS_TIMEOUT@GOTPAGE
Lloh28:
	ldr	x23, [x23, _DC8051_ACCESS_TIMEOUT@GOTPAGEOFF]
	b	LBB0_3
LBB0_2:                                 ;   in Loop: Header=BB0_3 Depth=1
	add	x24, x24, #8
	cmp	w24, w20
	b.ge	LBB0_14
LBB0_3:                                 ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_10 Depth 2
	sub	w2, w20, w24
	cmp	w2, #7
	b.gt	LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	str	wzr, [sp, #12]
	add	x1, x21, x24, lsl #2
	add	x0, sp, #12
	b	LBB0_7
LBB0_5:                                 ;   in Loop: Header=BB0_3 Depth=1
	add	x1, x21, x24, lsl #2
	cbz	x25, LBB0_12
; %bb.6:                                ;   in Loop: Header=BB0_3 Depth=1
	add	x0, sp, #12
	mov	w2, #8
LBB0_7:                                 ;   in Loop: Header=BB0_3 Depth=1
	bl	_memcpy
LBB0_8:                                 ;   in Loop: Header=BB0_3 Depth=1
	ldr	w1, [x26]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_write_csr
	ldr	w1, [x27]
	mov	x0, x19
	bl	_read_csr
	ldr	w8, [x28]
	tst	w8, w0
	b.ne	LBB0_2
; %bb.9:                                ;   in Loop: Header=BB0_3 Depth=1
	mov	w22, #-1
LBB0_10:                                ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ldr	w8, [x23]
	add	w22, w22, #1
	cmp	w22, w8
	b.ge	LBB0_13
; %bb.11:                               ;   in Loop: Header=BB0_10 Depth=2
	mov	w0, #1
	bl	_udelay
	ldr	w1, [x27]
	mov	x0, x19
	bl	_read_csr
	ldr	w8, [x28]
	tst	w8, w0
	b.eq	LBB0_10
	b	LBB0_2
LBB0_12:                                ;   in Loop: Header=BB0_3 Depth=1
	ldr	w8, [x1]
	str	w8, [sp, #12]
	b	LBB0_8
LBB0_13:
Lloh29:
	adrp	x1, l_.str@PAGE
Lloh30:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x19
	bl	_dd_dev_err
Lloh31:
	adrp	x8, _ENXIO@GOTPAGE
Lloh32:
	ldr	x8, [x8, _ENXIO@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_15
LBB0_14:
Lloh34:
	adrp	x8, _DC_DC8051_CFG_RAM_ACCESS_CTRL@GOTPAGE
Lloh35:
	ldr	x8, [x8, _DC_DC8051_CFG_RAM_ACCESS_CTRL@GOTPAGEOFF]
Lloh36:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_write_csr
Lloh37:
	adrp	x8, _DC_DC8051_CFG_RAM_ACCESS_SETUP@GOTPAGE
Lloh38:
	ldr	x8, [x8, _DC_DC8051_CFG_RAM_ACCESS_SETUP@GOTPAGEOFF]
Lloh39:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_write_csr
	mov	w0, #0
LBB0_15:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpAdd	Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.cfi_endproc
                                        ; -- End function
	.comm	_DC_DC8051_CFG_RAM_ACCESS_SETUP_RAM_SEL_SMASK,8,3 ; @DC_DC8051_CFG_RAM_ACCESS_SETUP_RAM_SEL_SMASK
	.comm	_DC_DC8051_CFG_RAM_ACCESS_SETUP_AUTO_INCR_ADDR_SMASK,8,3 ; @DC_DC8051_CFG_RAM_ACCESS_SETUP_AUTO_INCR_ADDR_SMASK
	.comm	_DC_DC8051_CFG_RAM_ACCESS_SETUP,4,2 ; @DC_DC8051_CFG_RAM_ACCESS_SETUP
	.comm	_DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK,4,2 ; @DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK
	.comm	_DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT,4,2 ; @DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT
	.comm	_DC_DC8051_CFG_RAM_ACCESS_CTRL_WRITE_ENA_SMASK,4,2 ; @DC_DC8051_CFG_RAM_ACCESS_CTRL_WRITE_ENA_SMASK
	.comm	_DC_DC8051_CFG_RAM_ACCESS_CTRL,4,2 ; @DC_DC8051_CFG_RAM_ACCESS_CTRL
	.comm	_DC_DC8051_CFG_RAM_ACCESS_WR_DATA,4,2 ; @DC_DC8051_CFG_RAM_ACCESS_WR_DATA
	.comm	_DC_DC8051_CFG_RAM_ACCESS_STATUS,4,2 ; @DC_DC8051_CFG_RAM_ACCESS_STATUS
	.comm	_DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK,4,2 ; @DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK
	.comm	_DC8051_ACCESS_TIMEOUT,4,2      ; @DC8051_ACCESS_TIMEOUT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"timeout writing 8051 data\n"

	.comm	_ENXIO,4,2                      ; @ENXIO
	.no_dead_strip	_write_8051
.subsections_via_symbols
