	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function set_ts_clk_mode_and_freq
_set_ts_clk_mode_and_freq:              ## @set_ts_clk_mode_and_freq
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	testq	%rdi, %rdi
	je	LBB0_1
## %bb.2:
	movl	%esi, %r14d
	movq	%rdi, %r12
	movq	24(%rdi), %rdi
	movq	_CXD2880_IO_TGT_DMD@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	xorl	%ebx, %ebx
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	callq	*(%rdi)
	testl	%eax, %eax
	jne	LBB0_13
## %bb.3:
	movq	24(%r12), %rdi
	movq	32(%r12), %rax
	xorl	%r13d, %r13d
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
	testq	%rax, %rax
	setne	%r13b
	cmpl	$0, (%r12)
	setne	-41(%rbp)                       ## 1-byte Folded Spill
	cmovel	%r13d, %ebx
	movl	(%r15), %esi
	movl	$211, %edx
	movl	%ebx, %ecx
	movl	$1, %r8d
	callq	_cxd2880_io_set_reg_bits
	testl	%eax, %eax
	jne	LBB0_13
## %bb.4:
	movq	24(%r12), %rdi
	movl	(%r15), %esi
	movl	$222, %edx
	movl	%r13d, %ecx
	movl	$1, %r8d
	callq	_cxd2880_io_set_reg_bits
	testl	%eax, %eax
	jne	LBB0_13
## %bb.5:
	xorl	%ecx, %ecx
	movb	-41(%rbp), %al                  ## 1-byte Reload
	movb	%al, %cl
	movq	24(%r12), %rdi
	movl	(%r15), %esi
	movl	$218, %edx
	movl	$1, %r8d
	callq	_cxd2880_io_set_reg_bits
	testl	%eax, %eax
	jne	LBB0_13
## %bb.6:
	movq	%r15, %rsi
	movq	8(%r12), %rax
	movq	16(%r12), %rcx
	leaq	(%rax,%rax,8), %rax
	leaq	_set_ts_clk_mode_and_freq.srl_ts_clk_stgs(%rip), %rdx
	leaq	(%rdx,%rax,8), %r13
	leaq	(%rcx,%rcx,8), %rbx
	movl	4(%r13,%rbx,4), %ecx
	movl	(%r12), %r15d
	testl	%r15d, %r15d
	jne	LBB0_8
## %bb.7:
	movl	(%r13,%rbx,4), %r15d
LBB0_8:
	movq	24(%r12), %rdi
	movl	(%rsi), %esi
	movl	$196, %edx
	movl	$3, %r8d
	callq	_cxd2880_io_set_reg_bits
	testl	%eax, %eax
	jne	LBB0_13
## %bb.9:
	movl	8(%r13,%rbx,4), %ecx
	movq	24(%r12), %rdi
	movq	_CXD2880_IO_TGT_DMD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$209, %edx
	movl	$3, %r8d
	callq	_cxd2880_io_set_reg_bits
	testl	%eax, %eax
	jne	LBB0_13
## %bb.10:
	movq	24(%r12), %rdi
	movq	_CXD2880_IO_TGT_DMD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$217, %edx
	movl	%r15d, %ecx
	callq	*(%rdi)
	testl	%eax, %eax
	jne	LBB0_13
## %bb.11:
	xorl	%r15d, %r15d
	cmpq	$0, -56(%rbp)                   ## 8-byte Folded Reload
	sete	%bl
	movq	_CXD2880_DTV_SYS_DVBT@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	cmpl	%r14d, (%rcx)
	jne	LBB0_13
## %bb.12:
	movq	24(%r12), %rdi
	movq	_CXD2880_IO_TGT_DMD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	movl	$16, %ecx
	callq	*(%rdi)
	testl	%eax, %eax
	jne	LBB0_13
## %bb.14:
	movb	%bl, %r15b
	movq	24(%r12), %rdi
	movq	_CXD2880_IO_TGT_DMD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$102, %edx
	movl	%r15d, %ecx
	movl	$1, %r8d
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_cxd2880_io_set_reg_bits        ## TAILCALL
LBB0_1:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_13:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__const
	.p2align	4                               ## @set_ts_clk_mode_and_freq.srl_ts_clk_stgs
_set_ts_clk_mode_and_freq.srl_ts_clk_stgs:
	.long	3                               ## 0x3
	.long	1                               ## 0x1
	.long	8                               ## 0x8
	.space	12
	.space	12
	.long	0                               ## 0x0
	.long	2                               ## 0x2
	.long	16                              ## 0x10
	.space	12
	.space	12
	.long	1                               ## 0x1
	.long	1                               ## 0x1
	.long	8                               ## 0x8
	.space	12
	.space	12
	.long	2                               ## 0x2
	.long	2                               ## 0x2
	.long	16                              ## 0x10
	.space	12
	.space	12

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_CXD2880_IO_TGT_DMD,4,2         ## @CXD2880_IO_TGT_DMD
	.comm	_CXD2880_DTV_SYS_DVBT,4,2       ## @CXD2880_DTV_SYS_DVBT
	.no_dead_strip	_set_ts_clk_mode_and_freq
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function set_ts_clk_mode_and_freq
_set_ts_clk_mode_and_freq:              ; @set_ts_clk_mode_and_freq
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	cbz	x0, LBB0_11
; %bb.1:
	mov	x20, x1
	mov	x19, x0
	ldr	x0, [x0, #24]
	ldr	x8, [x0]
Lloh0:
	adrp	x23, _CXD2880_IO_TGT_DMD@GOTPAGE
Lloh1:
	ldr	x23, [x23, _CXD2880_IO_TGT_DMD@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	w2, #0
	mov	w3, #0
	blr	x8
	cbnz	w0, LBB0_12
; %bb.2:
	ldp	x0, x24, [x19, #24]
	cmp	x24, #0
	cset	w22, ne
	ldr	w8, [x19]
	cmp	w8, #0
	csel	w3, w22, wzr, eq
	cset	w21, ne
	ldr	w1, [x23]
	mov	w2, #211
	mov	w4, #1
	bl	_cxd2880_io_set_reg_bits
	cbnz	w0, LBB0_12
; %bb.3:
	ldr	x0, [x19, #24]
	ldr	w1, [x23]
	mov	w2, #222
	mov	x3, x22
	mov	w4, #1
	bl	_cxd2880_io_set_reg_bits
	cbnz	w0, LBB0_12
; %bb.4:
	ldr	x0, [x19, #24]
	ldr	w1, [x23]
	mov	w2, #218
	mov	x3, x21
	mov	w4, #1
	bl	_cxd2880_io_set_reg_bits
	cbnz	w0, LBB0_12
; %bb.5:
	ldp	x8, x9, [x19, #8]
	mov	w10, #36
	mov	w11, #72
Lloh2:
	adrp	x12, _set_ts_clk_mode_and_freq.srl_ts_clk_stgs@PAGE
Lloh3:
	add	x12, x12, _set_ts_clk_mode_and_freq.srl_ts_clk_stgs@PAGEOFF
	madd	x8, x8, x11, x12
	madd	x22, x9, x10, x8
	ldp	w8, w3, [x22]
	ldr	w9, [x19]
	cmp	w9, #0
	csel	w21, w8, w9, eq
	ldr	x0, [x19, #24]
	ldr	w1, [x23]
	mov	w2, #196
	mov	w4, #3
	bl	_cxd2880_io_set_reg_bits
	cbnz	w0, LBB0_12
; %bb.6:
	ldr	w3, [x22, #8]
	ldr	x0, [x19, #24]
	ldr	w1, [x23]
	mov	w2, #209
	mov	w4, #3
	bl	_cxd2880_io_set_reg_bits
	cbnz	w0, LBB0_12
; %bb.7:
	ldr	x0, [x19, #24]
	ldr	x8, [x0]
	ldr	w1, [x23]
	mov	w2, #217
	mov	x3, x21
	blr	x8
	cbnz	w0, LBB0_12
; %bb.8:
	cmp	x24, #0
	cset	w21, eq
Lloh4:
	adrp	x8, _CXD2880_DTV_SYS_DVBT@GOTPAGE
Lloh5:
	ldr	x8, [x8, _CXD2880_DTV_SYS_DVBT@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
	cmp	w8, w20
	b.ne	LBB0_13
; %bb.9:
	ldr	x0, [x19, #24]
	ldr	x8, [x0]
	ldr	w1, [x23]
	mov	w2, #0
	mov	w3, #16
	blr	x8
	cbnz	w0, LBB0_12
; %bb.10:
	ldr	x0, [x19, #24]
	ldr	w1, [x23]
	mov	w2, #102
	mov	x3, x21
	mov	w4, #1
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_cxd2880_io_set_reg_bits
LBB0_11:
Lloh7:
	adrp	x8, _EINVAL@GOTPAGE
Lloh8:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_12:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_13:
	mov	w0, #0
	b	LBB0_12
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__const
	.p2align	2                               ; @set_ts_clk_mode_and_freq.srl_ts_clk_stgs
_set_ts_clk_mode_and_freq.srl_ts_clk_stgs:
	.long	3                               ; 0x3
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.space	12
	.space	12
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	16                              ; 0x10
	.space	12
	.space	12
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.space	12
	.space	12
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	16                              ; 0x10
	.space	12
	.space	12

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_CXD2880_IO_TGT_DMD,4,2         ; @CXD2880_IO_TGT_DMD
	.comm	_CXD2880_DTV_SYS_DVBT,4,2       ; @CXD2880_DTV_SYS_DVBT
	.no_dead_strip	_set_ts_clk_mode_and_freq
.subsections_via_symbols
