	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function aspm_hw_set_l1_ent_latency
_aspm_hw_set_l1_ent_latency:            ## @aspm_hw_set_l1_ent_latency
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	subq	$16, %rsp
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	movl	(%rdi), %edi
	movq	_PCIE_CFG_REG_PL3@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	leaq	-20(%rbp), %rdx
	callq	_pci_read_config_dword
	movq	_PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SMASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	-20(%rbp), %eax
	movq	_PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$4, %edx
	shll	%cl, %edx
	orl	%eax, %edx
	movl	%edx, -20(%rbp)
	movl	(%rbx), %edi
	movl	(%r14), %esi
	callq	_pci_write_config_dword
	addq	$16, %rsp
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PCIE_CFG_REG_PL3,4,2           ## @PCIE_CFG_REG_PL3
	.comm	_PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SMASK,4,2 ## @PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SMASK
	.comm	_PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SHIFT,4,2 ## @PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SHIFT
	.no_dead_strip	_aspm_hw_set_l1_ent_latency
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function aspm_hw_set_l1_ent_latency
_aspm_hw_set_l1_ent_latency:            ; @aspm_hw_set_l1_ent_latency
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #48
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	w0, [x0]
Lloh0:
	adrp	x20, _PCIE_CFG_REG_PL3@GOTPAGE
Lloh1:
	ldr	x20, [x20, _PCIE_CFG_REG_PL3@GOTPAGEOFF]
	ldr	w1, [x20]
	add	x2, sp, #12
	bl	_pci_read_config_dword
Lloh2:
	adrp	x8, _PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SMASK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SMASK@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	bic	w8, w9, w8
Lloh5:
	adrp	x9, _PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SHIFT@GOTPAGE
Lloh6:
	ldr	x9, [x9, _PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SHIFT@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	mov	w10, #4
	lsl	w9, w10, w9
	orr	w2, w9, w8
	str	w2, [sp, #12]
	ldr	w0, [x19]
	ldr	w1, [x20]
	bl	_pci_write_config_dword
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	ret
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_PCIE_CFG_REG_PL3,4,2           ; @PCIE_CFG_REG_PL3
	.comm	_PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SMASK,4,2 ; @PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SMASK
	.comm	_PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SHIFT,4,2 ; @PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SHIFT
	.no_dead_strip	_aspm_hw_set_l1_ent_latency
.subsections_via_symbols
