	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tg3_setup_eee
_tg3_setup_eee:                         ## @tg3_setup_eee
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_TG3_CPMU_EEE_LNKIDL_PCIE_NL0@GOTPCREL(%rip), %rax
	movq	_TG3_CPMU_EEE_LNKIDL_UART_IDL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	callq	_tg3_chip_rev_id
	movq	_CHIPREV_ID_57765_A0@GOTPCREL(%rip), %rdx
	xorl	%r15d, %r15d
	movl	$0, %ecx
	cmpq	(%rdx), %rax
	jne	LBB0_2
## %bb.1:
	movq	_TG3_CPMU_EEE_LNKIDL_APE_TX_MT@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
LBB0_2:
	orl	%ecx, %ebx
	movq	_TG3_CPMU_EEE_LNKIDL_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%ebx, %esi
	callq	_tw32_f
	movq	_TG3_CPMU_EEE_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_TG3_CPMU_EEE_CTRL_EXIT_20_1_US@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_tw32_f
	movq	_TG3_CPMU_EEEMD_ERLY_L1_XIT_DET@GOTPCREL(%rip), %rax
	cmpq	$0, 16(%r14)
	movl	$0, %ebx
	je	LBB0_4
## %bb.3:
	movq	_TG3_CPMU_EEEMD_LPI_IN_TX@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
LBB0_4:
	orl	(%rax), %ebx
	movq	_TG3_CPMU_EEEMD_LPI_IN_RX@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_TG3_CPMU_EEEMD_EEE_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	%r14, %rdi
	callq	_tg3_asic_rev
	movq	_ASIC_REV_5717@GOTPCREL(%rip), %rdx
	movl	$0, %ecx
	cmpq	(%rdx), %rax
	je	LBB0_6
## %bb.5:
	movq	_TG3_CPMU_EEEMD_SND_IDX_DET_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
LBB0_6:
	orl	%ecx, %ebx
	movq	_ENABLE_APE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_tg3_flag
	movl	$0, %ecx
	testq	%rax, %rax
	je	LBB0_8
## %bb.7:
	movq	_TG3_CPMU_EEEMD_APE_TX_DET_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
LBB0_8:
	orl	%ecx, %ebx
	movq	_TG3_CPMU_EEE_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	cmpq	$0, 8(%r14)
	cmovel	%r15d, %ebx
	movl	%ebx, %esi
	callq	_tw32_f
	movq	_TG3_CPMU_EEE_DBTMR1@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_TG3_CPMU_DBTMR1_PCIEXIT_2047US@GOTPCREL(%rip), %rax
	movzwl	(%r14), %esi
	orl	(%rax), %esi
	callq	_tw32_f
	movq	_TG3_CPMU_EEE_DBTMR2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_TG3_CPMU_DBTMR2_APE_TX_2047US@GOTPCREL(%rip), %rax
	movq	_TG3_CPMU_DBTMR2_TXIDXEQ_2047US@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_tw32_f                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_TG3_CPMU_EEE_LNKIDL_PCIE_NL0,4,2 ## @TG3_CPMU_EEE_LNKIDL_PCIE_NL0
	.comm	_TG3_CPMU_EEE_LNKIDL_UART_IDL,4,2 ## @TG3_CPMU_EEE_LNKIDL_UART_IDL
	.comm	_CHIPREV_ID_57765_A0,8,3        ## @CHIPREV_ID_57765_A0
	.comm	_TG3_CPMU_EEE_LNKIDL_APE_TX_MT,4,2 ## @TG3_CPMU_EEE_LNKIDL_APE_TX_MT
	.comm	_TG3_CPMU_EEE_LNKIDL_CTRL,4,2   ## @TG3_CPMU_EEE_LNKIDL_CTRL
	.comm	_TG3_CPMU_EEE_CTRL,4,2          ## @TG3_CPMU_EEE_CTRL
	.comm	_TG3_CPMU_EEE_CTRL_EXIT_20_1_US,4,2 ## @TG3_CPMU_EEE_CTRL_EXIT_20_1_US
	.comm	_TG3_CPMU_EEEMD_ERLY_L1_XIT_DET,4,2 ## @TG3_CPMU_EEEMD_ERLY_L1_XIT_DET
	.comm	_TG3_CPMU_EEEMD_LPI_IN_TX,4,2   ## @TG3_CPMU_EEEMD_LPI_IN_TX
	.comm	_TG3_CPMU_EEEMD_LPI_IN_RX,4,2   ## @TG3_CPMU_EEEMD_LPI_IN_RX
	.comm	_TG3_CPMU_EEEMD_EEE_ENABLE,4,2  ## @TG3_CPMU_EEEMD_EEE_ENABLE
	.comm	_ASIC_REV_5717,8,3              ## @ASIC_REV_5717
	.comm	_TG3_CPMU_EEEMD_SND_IDX_DET_EN,4,2 ## @TG3_CPMU_EEEMD_SND_IDX_DET_EN
	.comm	_ENABLE_APE,4,2                 ## @ENABLE_APE
	.comm	_TG3_CPMU_EEEMD_APE_TX_DET_EN,4,2 ## @TG3_CPMU_EEEMD_APE_TX_DET_EN
	.comm	_TG3_CPMU_EEE_MODE,4,2          ## @TG3_CPMU_EEE_MODE
	.comm	_TG3_CPMU_EEE_DBTMR1,4,2        ## @TG3_CPMU_EEE_DBTMR1
	.comm	_TG3_CPMU_DBTMR1_PCIEXIT_2047US,4,2 ## @TG3_CPMU_DBTMR1_PCIEXIT_2047US
	.comm	_TG3_CPMU_EEE_DBTMR2,4,2        ## @TG3_CPMU_EEE_DBTMR2
	.comm	_TG3_CPMU_DBTMR2_APE_TX_2047US,4,2 ## @TG3_CPMU_DBTMR2_APE_TX_2047US
	.comm	_TG3_CPMU_DBTMR2_TXIDXEQ_2047US,4,2 ## @TG3_CPMU_DBTMR2_TXIDXEQ_2047US
	.no_dead_strip	_tg3_setup_eee
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tg3_setup_eee
_tg3_setup_eee:                         ; @tg3_setup_eee
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
Lloh0:
	adrp	x8, _TG3_CPMU_EEE_LNKIDL_PCIE_NL0@GOTPAGE
Lloh1:
	ldr	x8, [x8, _TG3_CPMU_EEE_LNKIDL_PCIE_NL0@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _TG3_CPMU_EEE_LNKIDL_UART_IDL@GOTPAGE
Lloh4:
	ldr	x9, [x9, _TG3_CPMU_EEE_LNKIDL_UART_IDL@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	orr	w20, w9, w8
	bl	_tg3_chip_rev_id
Lloh6:
	adrp	x8, _CHIPREV_ID_57765_A0@GOTPAGE
Lloh7:
	ldr	x8, [x8, _CHIPREV_ID_57765_A0@GOTPAGEOFF]
Lloh8:
	ldr	x8, [x8]
Lloh9:
	adrp	x9, _TG3_CPMU_EEE_LNKIDL_APE_TX_MT@GOTPAGE
Lloh10:
	ldr	x9, [x9, _TG3_CPMU_EEE_LNKIDL_APE_TX_MT@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	cmp	x0, x8
	csel	w8, w9, wzr, eq
	orr	w1, w20, w8
Lloh12:
	adrp	x8, _TG3_CPMU_EEE_LNKIDL_CTRL@GOTPAGE
Lloh13:
	ldr	x8, [x8, _TG3_CPMU_EEE_LNKIDL_CTRL@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	bl	_tw32_f
Lloh15:
	adrp	x8, _TG3_CPMU_EEE_CTRL@GOTPAGE
Lloh16:
	ldr	x8, [x8, _TG3_CPMU_EEE_CTRL@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
Lloh18:
	adrp	x8, _TG3_CPMU_EEE_CTRL_EXIT_20_1_US@GOTPAGE
Lloh19:
	ldr	x8, [x8, _TG3_CPMU_EEE_CTRL_EXIT_20_1_US@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	bl	_tw32_f
Lloh21:
	adrp	x8, _TG3_CPMU_EEEMD_ERLY_L1_XIT_DET@GOTPAGE
Lloh22:
	ldr	x8, [x8, _TG3_CPMU_EEEMD_ERLY_L1_XIT_DET@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	ldr	x9, [x19, #16]
Lloh24:
	adrp	x10, _TG3_CPMU_EEEMD_LPI_IN_TX@GOTPAGE
Lloh25:
	ldr	x10, [x10, _TG3_CPMU_EEEMD_LPI_IN_TX@GOTPAGEOFF]
Lloh26:
	ldr	w10, [x10]
	cmp	x9, #0
	csel	w9, wzr, w10, eq
	orr	w8, w9, w8
Lloh27:
	adrp	x9, _TG3_CPMU_EEEMD_LPI_IN_RX@GOTPAGE
Lloh28:
	ldr	x9, [x9, _TG3_CPMU_EEEMD_LPI_IN_RX@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh30:
	adrp	x9, _TG3_CPMU_EEEMD_EEE_ENABLE@GOTPAGE
Lloh31:
	ldr	x9, [x9, _TG3_CPMU_EEEMD_EEE_ENABLE@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	orr	w20, w8, w9
	mov	x0, x19
	bl	_tg3_asic_rev
Lloh33:
	adrp	x8, _ASIC_REV_5717@GOTPAGE
Lloh34:
	ldr	x8, [x8, _ASIC_REV_5717@GOTPAGEOFF]
Lloh35:
	ldr	x8, [x8]
Lloh36:
	adrp	x9, _TG3_CPMU_EEEMD_SND_IDX_DET_EN@GOTPAGE
Lloh37:
	ldr	x9, [x9, _TG3_CPMU_EEEMD_SND_IDX_DET_EN@GOTPAGEOFF]
Lloh38:
	ldr	w9, [x9]
	cmp	x0, x8
	csel	w8, wzr, w9, eq
	orr	w20, w20, w8
Lloh39:
	adrp	x8, _ENABLE_APE@GOTPAGE
Lloh40:
	ldr	x8, [x8, _ENABLE_APE@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_tg3_flag
Lloh42:
	adrp	x8, _TG3_CPMU_EEEMD_APE_TX_DET_EN@GOTPAGE
Lloh43:
	ldr	x8, [x8, _TG3_CPMU_EEEMD_APE_TX_DET_EN@GOTPAGEOFF]
Lloh44:
	ldr	w8, [x8]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w8, w20, w8
Lloh45:
	adrp	x9, _TG3_CPMU_EEE_MODE@GOTPAGE
Lloh46:
	ldr	x9, [x9, _TG3_CPMU_EEE_MODE@GOTPAGEOFF]
Lloh47:
	ldr	w0, [x9]
	ldr	x9, [x19, #8]
	cmp	x9, #0
	csel	w1, wzr, w8, eq
	bl	_tw32_f
Lloh48:
	adrp	x8, _TG3_CPMU_EEE_DBTMR1@GOTPAGE
Lloh49:
	ldr	x8, [x8, _TG3_CPMU_EEE_DBTMR1@GOTPAGEOFF]
Lloh50:
	ldr	w0, [x8]
Lloh51:
	adrp	x8, _TG3_CPMU_DBTMR1_PCIEXIT_2047US@GOTPAGE
Lloh52:
	ldr	x8, [x8, _TG3_CPMU_DBTMR1_PCIEXIT_2047US@GOTPAGEOFF]
Lloh53:
	ldr	w8, [x8]
	ldrh	w9, [x19]
	orr	w1, w9, w8
	bl	_tw32_f
Lloh54:
	adrp	x8, _TG3_CPMU_EEE_DBTMR2@GOTPAGE
Lloh55:
	ldr	x8, [x8, _TG3_CPMU_EEE_DBTMR2@GOTPAGEOFF]
Lloh56:
	ldr	w0, [x8]
Lloh57:
	adrp	x8, _TG3_CPMU_DBTMR2_APE_TX_2047US@GOTPAGE
Lloh58:
	ldr	x8, [x8, _TG3_CPMU_DBTMR2_APE_TX_2047US@GOTPAGEOFF]
Lloh59:
	ldr	w8, [x8]
Lloh60:
	adrp	x9, _TG3_CPMU_DBTMR2_TXIDXEQ_2047US@GOTPAGE
Lloh61:
	ldr	x9, [x9, _TG3_CPMU_DBTMR2_TXIDXEQ_2047US@GOTPAGEOFF]
Lloh62:
	ldr	w9, [x9]
	orr	w1, w9, w8
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_tw32_f
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_TG3_CPMU_EEE_LNKIDL_PCIE_NL0,4,2 ; @TG3_CPMU_EEE_LNKIDL_PCIE_NL0
	.comm	_TG3_CPMU_EEE_LNKIDL_UART_IDL,4,2 ; @TG3_CPMU_EEE_LNKIDL_UART_IDL
	.comm	_CHIPREV_ID_57765_A0,8,3        ; @CHIPREV_ID_57765_A0
	.comm	_TG3_CPMU_EEE_LNKIDL_APE_TX_MT,4,2 ; @TG3_CPMU_EEE_LNKIDL_APE_TX_MT
	.comm	_TG3_CPMU_EEE_LNKIDL_CTRL,4,2   ; @TG3_CPMU_EEE_LNKIDL_CTRL
	.comm	_TG3_CPMU_EEE_CTRL,4,2          ; @TG3_CPMU_EEE_CTRL
	.comm	_TG3_CPMU_EEE_CTRL_EXIT_20_1_US,4,2 ; @TG3_CPMU_EEE_CTRL_EXIT_20_1_US
	.comm	_TG3_CPMU_EEEMD_ERLY_L1_XIT_DET,4,2 ; @TG3_CPMU_EEEMD_ERLY_L1_XIT_DET
	.comm	_TG3_CPMU_EEEMD_LPI_IN_TX,4,2   ; @TG3_CPMU_EEEMD_LPI_IN_TX
	.comm	_TG3_CPMU_EEEMD_LPI_IN_RX,4,2   ; @TG3_CPMU_EEEMD_LPI_IN_RX
	.comm	_TG3_CPMU_EEEMD_EEE_ENABLE,4,2  ; @TG3_CPMU_EEEMD_EEE_ENABLE
	.comm	_ASIC_REV_5717,8,3              ; @ASIC_REV_5717
	.comm	_TG3_CPMU_EEEMD_SND_IDX_DET_EN,4,2 ; @TG3_CPMU_EEEMD_SND_IDX_DET_EN
	.comm	_ENABLE_APE,4,2                 ; @ENABLE_APE
	.comm	_TG3_CPMU_EEEMD_APE_TX_DET_EN,4,2 ; @TG3_CPMU_EEEMD_APE_TX_DET_EN
	.comm	_TG3_CPMU_EEE_MODE,4,2          ; @TG3_CPMU_EEE_MODE
	.comm	_TG3_CPMU_EEE_DBTMR1,4,2        ; @TG3_CPMU_EEE_DBTMR1
	.comm	_TG3_CPMU_DBTMR1_PCIEXIT_2047US,4,2 ; @TG3_CPMU_DBTMR1_PCIEXIT_2047US
	.comm	_TG3_CPMU_EEE_DBTMR2,4,2        ; @TG3_CPMU_EEE_DBTMR2
	.comm	_TG3_CPMU_DBTMR2_APE_TX_2047US,4,2 ; @TG3_CPMU_DBTMR2_APE_TX_2047US
	.comm	_TG3_CPMU_DBTMR2_TXIDXEQ_2047US,4,2 ; @TG3_CPMU_DBTMR2_TXIDXEQ_2047US
	.no_dead_strip	_tg3_setup_eee
.subsections_via_symbols
