	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tg3_power_down_phy
_tg3_power_down_phy:                    ## @tg3_power_down_phy
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	subq	$16, %rsp
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	(%rdi), %ebx
	movq	_TG3_PHYFLG_KEEP_LINK_ON_PWRDN@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_1
LBB0_10:
	addq	$16, %rsp
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_1:
	movl	%esi, %r15d
	movq	%rdi, %r14
	movq	_TG3_PHYFLG_PHY_SERDES@GOTPCREL(%rip), %rax
	andl	(%rax), %ebx
	callq	_tg3_asic_rev
	testl	%ebx, %ebx
	je	LBB0_4
## %bb.2:
	movq	_ASIC_REV_5704@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_10
## %bb.3:
	movq	_SG_DIG_CTRL@GOTPCREL(%rip), %r15
	movl	(%r15), %edi
	callq	_tr32
	movl	%eax, %ebx
	movq	_MAC_SERDES_CFG@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_tr32
	movl	%eax, %r14d
	movq	_SG_DIG_USING_HW_AUTONEG@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SG_DIG_SOFT_RESET@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	(%r15), %edi
	movl	%ebx, %esi
	callq	_tw32
	movl	(%r12), %edi
	orl	$32768, %r14d                   ## imm = 0x8000
	movl	%r14d, %esi
	addq	$16, %rsp
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_tw32                           ## TAILCALL
LBB0_4:
	movq	_ASIC_REV_5906@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_5
## %bb.20:
	movq	%r14, %rdi
	callq	_tg3_bmcr_reset
	movq	_GRC_MISC_CFG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_tr32
	movl	(%rbx), %edi
	movq	_GRC_MISC_CFG_EPHY_IDDQ@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, %esi
	callq	_tw32_f
	movl	$40, %edi
	addq	$16, %rsp
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_udelay                         ## TAILCALL
LBB0_5:
	movq	_TG3_PHYFLG_IS_FET@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r14)
	je	LBB0_11
## %bb.6:
	movq	_MII_TG3_FET_TEST@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	leaq	-40(%rbp), %rdx
	movq	%r14, %rdi
	callq	_tg3_readphy
	testl	%eax, %eax
	jne	LBB0_10
## %bb.7:
	movq	_MII_ADVERTISE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	_tg3_writephy
	movq	_MII_BMCR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_BMCR_ANENABLE@GOTPCREL(%rip), %rax
	movq	_BMCR_ANRESTART@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	%r14, %rdi
	callq	_tg3_writephy
	movl	(%rbx), %esi
	movq	_MII_TG3_FET_SHADOW_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	orl	-40(%rbp), %edx
	movq	%r14, %rdi
	callq	_tg3_writephy
	movq	_MII_TG3_FET_SHDW_AUXMODE4@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	leaq	-36(%rbp), %rdx
	movq	%r14, %rdi
	callq	_tg3_readphy
	testl	%eax, %eax
	jne	LBB0_9
## %bb.8:
	movq	_MII_TG3_FET_SHDW_AUXMODE4_SBPD@GOTPCREL(%rip), %rax
	movl	-36(%rbp), %edx
	orl	(%rax), %edx
	movl	%edx, -36(%rbp)
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_tg3_writephy
LBB0_9:
	movl	(%rbx), %esi
	movl	-40(%rbp), %edx
	movq	%r14, %rdi
	callq	_tg3_writephy
	jmp	LBB0_10
LBB0_11:
	testl	%r15d, %r15d
	je	LBB0_15
## %bb.12:
	movq	%r14, %rdi
	callq	_tg3_phy_led_bug
	testl	%eax, %eax
	jne	LBB0_14
## %bb.13:
	movq	_MII_TG3_EXT_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MII_TG3_EXT_CTRL_FORCE_LED_OFF@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_tg3_writephy
LBB0_14:
	movq	_MII_TG3_AUXCTL_PCTL_100TX_LPWR@GOTPCREL(%rip), %rax
	movq	_MII_TG3_AUXCTL_PCTL_SPR_ISOLATE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	_MII_TG3_AUXCTL_PCTL_VREG_11V@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_MII_TG3_AUXCTL_SHDWSEL_PWRCTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_tg3_phy_auxctl_write
LBB0_15:
	movq	%r14, %rdi
	callq	_tg3_phy_power_bug
	testq	%rax, %rax
	jne	LBB0_10
## %bb.16:
	movq	%r14, %rdi
	callq	_tg3_chip_rev
	movq	_CHIPREV_5784_AX@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_18
## %bb.17:
	movq	%r14, %rdi
	callq	_tg3_chip_rev
	movq	_CHIPREV_5761_AX@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_19
LBB0_18:
	movq	_TG3_CPMU_LSPD_1000MB_CLK@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	callq	_tr32
	movq	_CPMU_LSPD_1000MB_MACCLK_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movq	_CPMU_LSPD_1000MB_MACCLK_12_5@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	(%rbx), %edi
	callq	_tw32_f
LBB0_19:
	movq	_MII_BMCR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_BMCR_PDOWN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	addq	$16, %rsp
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_tg3_writephy                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_TG3_PHYFLG_KEEP_LINK_ON_PWRDN,4,2 ## @TG3_PHYFLG_KEEP_LINK_ON_PWRDN
	.comm	_TG3_PHYFLG_PHY_SERDES,4,2      ## @TG3_PHYFLG_PHY_SERDES
	.comm	_ASIC_REV_5704,8,3              ## @ASIC_REV_5704
	.comm	_SG_DIG_CTRL,4,2                ## @SG_DIG_CTRL
	.comm	_MAC_SERDES_CFG,4,2             ## @MAC_SERDES_CFG
	.comm	_SG_DIG_USING_HW_AUTONEG,4,2    ## @SG_DIG_USING_HW_AUTONEG
	.comm	_SG_DIG_SOFT_RESET,4,2          ## @SG_DIG_SOFT_RESET
	.comm	_ASIC_REV_5906,8,3              ## @ASIC_REV_5906
	.comm	_GRC_MISC_CFG,4,2               ## @GRC_MISC_CFG
	.comm	_GRC_MISC_CFG_EPHY_IDDQ,4,2     ## @GRC_MISC_CFG_EPHY_IDDQ
	.comm	_TG3_PHYFLG_IS_FET,4,2          ## @TG3_PHYFLG_IS_FET
	.comm	_MII_TG3_FET_TEST,4,2           ## @MII_TG3_FET_TEST
	.comm	_MII_ADVERTISE,4,2              ## @MII_ADVERTISE
	.comm	_MII_BMCR,4,2                   ## @MII_BMCR
	.comm	_BMCR_ANENABLE,4,2              ## @BMCR_ANENABLE
	.comm	_BMCR_ANRESTART,4,2             ## @BMCR_ANRESTART
	.comm	_MII_TG3_FET_SHADOW_EN,4,2      ## @MII_TG3_FET_SHADOW_EN
	.comm	_MII_TG3_FET_SHDW_AUXMODE4,4,2  ## @MII_TG3_FET_SHDW_AUXMODE4
	.comm	_MII_TG3_FET_SHDW_AUXMODE4_SBPD,4,2 ## @MII_TG3_FET_SHDW_AUXMODE4_SBPD
	.comm	_MII_TG3_EXT_CTRL,4,2           ## @MII_TG3_EXT_CTRL
	.comm	_MII_TG3_EXT_CTRL_FORCE_LED_OFF,4,2 ## @MII_TG3_EXT_CTRL_FORCE_LED_OFF
	.comm	_MII_TG3_AUXCTL_PCTL_100TX_LPWR,4,2 ## @MII_TG3_AUXCTL_PCTL_100TX_LPWR
	.comm	_MII_TG3_AUXCTL_PCTL_SPR_ISOLATE,4,2 ## @MII_TG3_AUXCTL_PCTL_SPR_ISOLATE
	.comm	_MII_TG3_AUXCTL_PCTL_VREG_11V,4,2 ## @MII_TG3_AUXCTL_PCTL_VREG_11V
	.comm	_MII_TG3_AUXCTL_SHDWSEL_PWRCTL,4,2 ## @MII_TG3_AUXCTL_SHDWSEL_PWRCTL
	.comm	_CHIPREV_5784_AX,8,3            ## @CHIPREV_5784_AX
	.comm	_CHIPREV_5761_AX,8,3            ## @CHIPREV_5761_AX
	.comm	_TG3_CPMU_LSPD_1000MB_CLK,4,2   ## @TG3_CPMU_LSPD_1000MB_CLK
	.comm	_CPMU_LSPD_1000MB_MACCLK_MASK,4,2 ## @CPMU_LSPD_1000MB_MACCLK_MASK
	.comm	_CPMU_LSPD_1000MB_MACCLK_12_5,4,2 ## @CPMU_LSPD_1000MB_MACCLK_12_5
	.comm	_BMCR_PDOWN,4,2                 ## @BMCR_PDOWN
	.no_dead_strip	_tg3_power_down_phy
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tg3_power_down_phy
_tg3_power_down_phy:                    ; @tg3_power_down_phy
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	ldr	w8, [x0]
Lloh0:
	adrp	x9, _TG3_PHYFLG_KEEP_LINK_ON_PWRDN@GOTPAGE
Lloh1:
	ldr	x9, [x9, _TG3_PHYFLG_KEEP_LINK_ON_PWRDN@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_2
LBB0_1:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
LBB0_2:
	mov	x20, x1
	mov	x19, x0
Lloh3:
	adrp	x9, _TG3_PHYFLG_PHY_SERDES@GOTPAGE
Lloh4:
	ldr	x9, [x9, _TG3_PHYFLG_PHY_SERDES@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	and	w21, w9, w8
	bl	_tg3_asic_rev
	cbz	w21, LBB0_5
; %bb.3:
Lloh6:
	adrp	x8, _ASIC_REV_5704@GOTPAGE
Lloh7:
	ldr	x8, [x8, _ASIC_REV_5704@GOTPAGEOFF]
Lloh8:
	ldr	x8, [x8]
	cmp	x0, x8
	b.ne	LBB0_1
; %bb.4:
Lloh9:
	adrp	x21, _SG_DIG_CTRL@GOTPAGE
Lloh10:
	ldr	x21, [x21, _SG_DIG_CTRL@GOTPAGEOFF]
	ldr	w0, [x21]
	bl	_tr32
	mov	x19, x0
Lloh11:
	adrp	x22, _MAC_SERDES_CFG@GOTPAGE
Lloh12:
	ldr	x22, [x22, _MAC_SERDES_CFG@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_tr32
	mov	x20, x0
Lloh13:
	adrp	x8, _SG_DIG_USING_HW_AUTONEG@GOTPAGE
Lloh14:
	ldr	x8, [x8, _SG_DIG_USING_HW_AUTONEG@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
Lloh16:
	adrp	x9, _SG_DIG_SOFT_RESET@GOTPAGE
Lloh17:
	ldr	x9, [x9, _SG_DIG_SOFT_RESET@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	orr	w8, w8, w19
	orr	w1, w8, w9
	ldr	w0, [x21]
	bl	_tw32
	ldr	w0, [x22]
	orr	w1, w20, #0x8000
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	b	_tw32
LBB0_5:
Lloh19:
	adrp	x8, _ASIC_REV_5906@GOTPAGE
Lloh20:
	ldr	x8, [x8, _ASIC_REV_5906@GOTPAGEOFF]
Lloh21:
	ldr	x8, [x8]
	cmp	x0, x8
	b.ne	LBB0_7
; %bb.6:
	mov	x0, x19
	bl	_tg3_bmcr_reset
Lloh22:
	adrp	x19, _GRC_MISC_CFG@GOTPAGE
Lloh23:
	ldr	x19, [x19, _GRC_MISC_CFG@GOTPAGEOFF]
	ldr	w0, [x19]
	bl	_tr32
	ldr	w8, [x19]
Lloh24:
	adrp	x9, _GRC_MISC_CFG_EPHY_IDDQ@GOTPAGE
Lloh25:
	ldr	x9, [x9, _GRC_MISC_CFG_EPHY_IDDQ@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	orr	w1, w9, w0
	mov	x0, x8
	bl	_tw32_f
	mov	w0, #40
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	b	_udelay
LBB0_7:
	ldr	w8, [x19]
Lloh27:
	adrp	x9, _TG3_PHYFLG_IS_FET@GOTPAGE
Lloh28:
	ldr	x9, [x9, _TG3_PHYFLG_IS_FET@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_12
; %bb.8:
Lloh30:
	adrp	x20, _MII_TG3_FET_TEST@GOTPAGE
Lloh31:
	ldr	x20, [x20, _MII_TG3_FET_TEST@GOTPAGEOFF]
	ldr	w1, [x20]
	add	x2, sp, #12
	mov	x0, x19
	bl	_tg3_readphy
	cbnz	w0, LBB0_1
; %bb.9:
Lloh32:
	adrp	x8, _MII_ADVERTISE@GOTPAGE
Lloh33:
	ldr	x8, [x8, _MII_ADVERTISE@GOTPAGEOFF]
Lloh34:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_tg3_writephy
Lloh35:
	adrp	x8, _MII_BMCR@GOTPAGE
Lloh36:
	ldr	x8, [x8, _MII_BMCR@GOTPAGEOFF]
Lloh37:
	adrp	x9, _BMCR_ANENABLE@GOTPAGE
Lloh38:
	ldr	x9, [x9, _BMCR_ANENABLE@GOTPAGEOFF]
Lloh39:
	ldr	w1, [x8]
Lloh40:
	ldr	w8, [x9]
Lloh41:
	adrp	x9, _BMCR_ANRESTART@GOTPAGE
Lloh42:
	ldr	x9, [x9, _BMCR_ANRESTART@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_tg3_writephy
	ldr	w1, [x20]
	ldr	w8, [sp, #12]
Lloh44:
	adrp	x9, _MII_TG3_FET_SHADOW_EN@GOTPAGE
Lloh45:
	ldr	x9, [x9, _MII_TG3_FET_SHADOW_EN@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_tg3_writephy
Lloh47:
	adrp	x21, _MII_TG3_FET_SHDW_AUXMODE4@GOTPAGE
Lloh48:
	ldr	x21, [x21, _MII_TG3_FET_SHDW_AUXMODE4@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x2, sp, #8
	mov	x0, x19
	bl	_tg3_readphy
	cbnz	w0, LBB0_11
; %bb.10:
Lloh49:
	adrp	x8, _MII_TG3_FET_SHDW_AUXMODE4_SBPD@GOTPAGE
Lloh50:
	ldr	x8, [x8, _MII_TG3_FET_SHDW_AUXMODE4_SBPD@GOTPAGEOFF]
Lloh51:
	ldr	w8, [x8]
	ldr	w9, [sp, #8]
	orr	w2, w9, w8
	str	w2, [sp, #8]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_tg3_writephy
LBB0_11:
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_tg3_writephy
	b	LBB0_1
LBB0_12:
	cbz	w20, LBB0_16
; %bb.13:
	mov	x0, x19
	bl	_tg3_phy_led_bug
	cbnz	w0, LBB0_15
; %bb.14:
Lloh52:
	adrp	x8, _MII_TG3_EXT_CTRL@GOTPAGE
Lloh53:
	ldr	x8, [x8, _MII_TG3_EXT_CTRL@GOTPAGEOFF]
Lloh54:
	ldr	w1, [x8]
Lloh55:
	adrp	x8, _MII_TG3_EXT_CTRL_FORCE_LED_OFF@GOTPAGE
Lloh56:
	ldr	x8, [x8, _MII_TG3_EXT_CTRL_FORCE_LED_OFF@GOTPAGEOFF]
Lloh57:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_tg3_writephy
LBB0_15:
Lloh58:
	adrp	x8, _MII_TG3_AUXCTL_PCTL_100TX_LPWR@GOTPAGE
Lloh59:
	ldr	x8, [x8, _MII_TG3_AUXCTL_PCTL_100TX_LPWR@GOTPAGEOFF]
Lloh60:
	ldr	w8, [x8]
Lloh61:
	adrp	x9, _MII_TG3_AUXCTL_PCTL_SPR_ISOLATE@GOTPAGE
Lloh62:
	ldr	x9, [x9, _MII_TG3_AUXCTL_PCTL_SPR_ISOLATE@GOTPAGEOFF]
Lloh63:
	ldr	w9, [x9]
Lloh64:
	adrp	x10, _MII_TG3_AUXCTL_PCTL_VREG_11V@GOTPAGE
Lloh65:
	ldr	x10, [x10, _MII_TG3_AUXCTL_PCTL_VREG_11V@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh66:
	ldr	w9, [x10]
	orr	w2, w8, w9
Lloh67:
	adrp	x8, _MII_TG3_AUXCTL_SHDWSEL_PWRCTL@GOTPAGE
Lloh68:
	ldr	x8, [x8, _MII_TG3_AUXCTL_SHDWSEL_PWRCTL@GOTPAGEOFF]
Lloh69:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_tg3_phy_auxctl_write
LBB0_16:
	mov	x0, x19
	bl	_tg3_phy_power_bug
	cbnz	x0, LBB0_1
; %bb.17:
	mov	x0, x19
	bl	_tg3_chip_rev
Lloh70:
	adrp	x8, _CHIPREV_5784_AX@GOTPAGE
Lloh71:
	ldr	x8, [x8, _CHIPREV_5784_AX@GOTPAGEOFF]
Lloh72:
	ldr	x8, [x8]
	cmp	x0, x8
	b.eq	LBB0_19
; %bb.18:
	mov	x0, x19
	bl	_tg3_chip_rev
Lloh73:
	adrp	x8, _CHIPREV_5761_AX@GOTPAGE
Lloh74:
	ldr	x8, [x8, _CHIPREV_5761_AX@GOTPAGEOFF]
Lloh75:
	ldr	x8, [x8]
	cmp	x0, x8
	b.ne	LBB0_20
LBB0_19:
Lloh76:
	adrp	x20, _TG3_CPMU_LSPD_1000MB_CLK@GOTPAGE
Lloh77:
	ldr	x20, [x20, _TG3_CPMU_LSPD_1000MB_CLK@GOTPAGEOFF]
	ldr	w0, [x20]
	bl	_tr32
Lloh78:
	adrp	x8, _CPMU_LSPD_1000MB_MACCLK_MASK@GOTPAGE
Lloh79:
	ldr	x8, [x8, _CPMU_LSPD_1000MB_MACCLK_MASK@GOTPAGEOFF]
Lloh80:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh81:
	adrp	x9, _CPMU_LSPD_1000MB_MACCLK_12_5@GOTPAGE
Lloh82:
	ldr	x9, [x9, _CPMU_LSPD_1000MB_MACCLK_12_5@GOTPAGEOFF]
Lloh83:
	ldr	w9, [x9]
	orr	w1, w8, w9
	ldr	w0, [x20]
	bl	_tw32_f
LBB0_20:
Lloh84:
	adrp	x8, _MII_BMCR@GOTPAGE
Lloh85:
	ldr	x8, [x8, _MII_BMCR@GOTPAGEOFF]
Lloh86:
	ldr	w1, [x8]
Lloh87:
	adrp	x8, _BMCR_PDOWN@GOTPAGE
Lloh88:
	ldr	x8, [x8, _BMCR_PDOWN@GOTPAGEOFF]
Lloh89:
	ldr	w2, [x8]
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	b	_tg3_writephy
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh39
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGot	Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.cfi_endproc
                                        ; -- End function
	.comm	_TG3_PHYFLG_KEEP_LINK_ON_PWRDN,4,2 ; @TG3_PHYFLG_KEEP_LINK_ON_PWRDN
	.comm	_TG3_PHYFLG_PHY_SERDES,4,2      ; @TG3_PHYFLG_PHY_SERDES
	.comm	_ASIC_REV_5704,8,3              ; @ASIC_REV_5704
	.comm	_SG_DIG_CTRL,4,2                ; @SG_DIG_CTRL
	.comm	_MAC_SERDES_CFG,4,2             ; @MAC_SERDES_CFG
	.comm	_SG_DIG_USING_HW_AUTONEG,4,2    ; @SG_DIG_USING_HW_AUTONEG
	.comm	_SG_DIG_SOFT_RESET,4,2          ; @SG_DIG_SOFT_RESET
	.comm	_ASIC_REV_5906,8,3              ; @ASIC_REV_5906
	.comm	_GRC_MISC_CFG,4,2               ; @GRC_MISC_CFG
	.comm	_GRC_MISC_CFG_EPHY_IDDQ,4,2     ; @GRC_MISC_CFG_EPHY_IDDQ
	.comm	_TG3_PHYFLG_IS_FET,4,2          ; @TG3_PHYFLG_IS_FET
	.comm	_MII_TG3_FET_TEST,4,2           ; @MII_TG3_FET_TEST
	.comm	_MII_ADVERTISE,4,2              ; @MII_ADVERTISE
	.comm	_MII_BMCR,4,2                   ; @MII_BMCR
	.comm	_BMCR_ANENABLE,4,2              ; @BMCR_ANENABLE
	.comm	_BMCR_ANRESTART,4,2             ; @BMCR_ANRESTART
	.comm	_MII_TG3_FET_SHADOW_EN,4,2      ; @MII_TG3_FET_SHADOW_EN
	.comm	_MII_TG3_FET_SHDW_AUXMODE4,4,2  ; @MII_TG3_FET_SHDW_AUXMODE4
	.comm	_MII_TG3_FET_SHDW_AUXMODE4_SBPD,4,2 ; @MII_TG3_FET_SHDW_AUXMODE4_SBPD
	.comm	_MII_TG3_EXT_CTRL,4,2           ; @MII_TG3_EXT_CTRL
	.comm	_MII_TG3_EXT_CTRL_FORCE_LED_OFF,4,2 ; @MII_TG3_EXT_CTRL_FORCE_LED_OFF
	.comm	_MII_TG3_AUXCTL_PCTL_100TX_LPWR,4,2 ; @MII_TG3_AUXCTL_PCTL_100TX_LPWR
	.comm	_MII_TG3_AUXCTL_PCTL_SPR_ISOLATE,4,2 ; @MII_TG3_AUXCTL_PCTL_SPR_ISOLATE
	.comm	_MII_TG3_AUXCTL_PCTL_VREG_11V,4,2 ; @MII_TG3_AUXCTL_PCTL_VREG_11V
	.comm	_MII_TG3_AUXCTL_SHDWSEL_PWRCTL,4,2 ; @MII_TG3_AUXCTL_SHDWSEL_PWRCTL
	.comm	_CHIPREV_5784_AX,8,3            ; @CHIPREV_5784_AX
	.comm	_CHIPREV_5761_AX,8,3            ; @CHIPREV_5761_AX
	.comm	_TG3_CPMU_LSPD_1000MB_CLK,4,2   ; @TG3_CPMU_LSPD_1000MB_CLK
	.comm	_CPMU_LSPD_1000MB_MACCLK_MASK,4,2 ; @CPMU_LSPD_1000MB_MACCLK_MASK
	.comm	_CPMU_LSPD_1000MB_MACCLK_12_5,4,2 ; @CPMU_LSPD_1000MB_MACCLK_12_5
	.comm	_BMCR_PDOWN,4,2                 ; @BMCR_PDOWN
	.no_dead_strip	_tg3_power_down_phy
.subsections_via_symbols
