	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function arm_smmu_write_context_bank
_arm_smmu_write_context_bank:           ## @arm_smmu_write_context_bank
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %ebx
	movq	%rdi, %r15
	movq	16(%rdi), %rax
	movslq	%esi, %rcx
	shlq	$5, %rcx
	movq	%rcx, -80(%rbp)                 ## 8-byte Spill
	movq	24(%rax,%rcx), %r14
	testq	%r14, %r14
	je	LBB0_1
## %bb.2:
	movq	%rax, -64(%rbp)                 ## 8-byte Spill
	movq	(%r14), %r13
	movq	_CBAR_TYPE_S2_TRANS@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movq	(%r15), %rax
	movq	_ARM_SMMU_V1@GOTPCREL(%rip), %rcx
	movq	%r13, %rsi
	cmpq	(%rcx), %rax
	jle	LBB0_8
## %bb.3:
	movq	8(%r14), %rax
	movq	_ARM_SMMU_CTX_FMT_AARCH64@GOTPCREL(%rip), %rcx
	xorl	%r12d, %r12d
	cmpq	(%rcx), %rax
	jne	LBB0_5
## %bb.4:
	movq	_CBA2R_VA64@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
LBB0_5:
	movq	_ARM_SMMU_FEAT_VMID16@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 8(%r15)
	je	LBB0_7
## %bb.6:
	movq	_CBA2R_VMID16@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	16(%r14), %rsi
	callq	_FIELD_PREP
	orl	%eax, %r12d
LBB0_7:
	movl	%ebx, %edi
	callq	_ARM_SMMU_GR1_CBA2R
	movq	%r15, %rdi
	movl	%eax, %esi
	movl	%r12d, %edx
	callq	_arm_smmu_gr1_write
	movq	(%r14), %rsi
LBB0_8:
	movl	%ebx, -52(%rbp)                 ## 4-byte Spill
	movq	_CBAR_TYPE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_FIELD_PREP
	movl	%eax, %r12d
	movq	(%r15), %rax
	movq	_ARM_SMMU_V2@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_10
## %bb.9:
	movq	_CBAR_IRPTNDX@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	24(%r14), %rsi
	callq	_FIELD_PREP
	orl	%eax, %r12d
LBB0_10:
	cmpq	-48(%rbp), %r13                 ## 8-byte Folded Reload
	movq	%r13, -72(%rbp)                 ## 8-byte Spill
	jne	LBB0_11
## %bb.12:
	movq	_ARM_SMMU_FEAT_VMID16@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 8(%r15)
	jne	LBB0_14
## %bb.13:
	movq	_CBAR_VMID@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	16(%r14), %rsi
	callq	_FIELD_PREP
	orl	%eax, %r12d
	jmp	LBB0_14
LBB0_1:
	xorl	%r14d, %r14d
	jmp	LBB0_27
LBB0_11:
	movq	_CBAR_S1_BPSHCFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_CBAR_S1_BPSHCFG_NSH@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	callq	_FIELD_PREP
	movl	%eax, %ebx
	movq	_CBAR_S1_MEMATTR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_CBAR_S1_MEMATTR_WB@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	callq	_FIELD_PREP
	orl	%r12d, %ebx
	orl	%eax, %ebx
	movl	%ebx, %r12d
LBB0_14:
	movq	-64(%rbp), %rax                 ## 8-byte Reload
	movq	-80(%rbp), %rcx                 ## 8-byte Reload
	leaq	(%rax,%rcx), %r13
	movl	-52(%rbp), %ebx                 ## 4-byte Reload
	movl	%ebx, %edi
	callq	_ARM_SMMU_GR1_CBAR
	movq	%r15, %rdi
	movl	%eax, %esi
	movl	%r12d, %edx
	movl	%ebx, %r12d
	callq	_arm_smmu_gr1_write
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	cmpq	%rax, -72(%rbp)                 ## 8-byte Folded Reload
	je	LBB0_17
## %bb.15:
	movq	(%r15), %rax
	movq	_ARM_SMMU_V1@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jle	LBB0_17
## %bb.16:
	movq	_ARM_SMMU_CB_TCR2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	(%r13), %rax
	movl	4(%rax), %ecx
	movq	%r15, %rdi
	movl	%r12d, %esi
	callq	_arm_smmu_cb_write
LBB0_17:
	movq	_ARM_SMMU_CB_TCR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	(%r13), %rax
	movl	(%rax), %ecx
	movq	%r15, %rdi
	movl	%r12d, %esi
	callq	_arm_smmu_cb_write
	movq	8(%r14), %rax
	movq	_ARM_SMMU_CTX_FMT_AARCH32_S@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_18
## %bb.20:
	movq	_ARM_SMMU_CB_CONTEXTIDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	32(%r14), %ecx
	movq	%r15, %rdi
	movl	%r12d, %esi
	callq	_arm_smmu_cb_write
	movq	_ARM_SMMU_CB_TTBR0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	-64(%rbp), %r14                 ## 8-byte Reload
	movq	-80(%rbp), %rbx                 ## 8-byte Reload
	movq	8(%r14,%rbx), %rax
	movl	(%rax), %ecx
	movq	%r15, %rdi
	movl	%r12d, %esi
	callq	_arm_smmu_cb_write
	movq	_ARM_SMMU_CB_TTBR1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	8(%r14,%rbx), %rax
	movl	4(%rax), %ecx
	movq	%r15, %rdi
	movl	%r12d, %esi
	callq	_arm_smmu_cb_write
	movq	-72(%rbp), %r13                 ## 8-byte Reload
	cmpq	-48(%rbp), %r13                 ## 8-byte Folded Reload
	jne	LBB0_21
	jmp	LBB0_22
LBB0_18:
	movq	_ARM_SMMU_CB_TTBR0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	-64(%rbp), %r14                 ## 8-byte Reload
	movq	-80(%rbp), %rbx                 ## 8-byte Reload
	movq	8(%r14,%rbx), %rax
	movl	(%rax), %ecx
	movq	%r15, %rdi
	movl	%r12d, %esi
	callq	_arm_smmu_cb_writeq
	movq	-72(%rbp), %r13                 ## 8-byte Reload
	cmpq	-48(%rbp), %r13                 ## 8-byte Folded Reload
	je	LBB0_22
## %bb.19:
	leaq	(%r14,%rbx), %rax
	addq	$8, %rax
	movq	_ARM_SMMU_CB_TTBR1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	(%rax), %rax
	movl	4(%rax), %ecx
	movq	%r15, %rdi
	movl	%r12d, %esi
	callq	_arm_smmu_cb_writeq
LBB0_21:
	movq	_ARM_SMMU_CB_S1_MAIR0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	16(%r14,%rbx), %rax
	movl	(%rax), %ecx
	movq	%r15, %rdi
	movl	%r12d, %esi
	callq	_arm_smmu_cb_write
	movq	_ARM_SMMU_CB_S1_MAIR1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	16(%r14,%rbx), %rax
	movl	4(%rax), %ecx
	movq	%r15, %rdi
	movl	%r12d, %esi
	callq	_arm_smmu_cb_write
LBB0_22:
	movq	_SCTLR_CFIE@GOTPCREL(%rip), %rax
	movq	_SCTLR_CFRE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	_SCTLR_AFE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SCTLR_TRE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SCTLR_M@GOTPCREL(%rip), %rax
	xorl	%r12d, %r12d
	movl	$0, %r14d
	cmpq	-48(%rbp), %r13                 ## 8-byte Folded Reload
	je	LBB0_24
## %bb.23:
	movq	_SCTLR_S1_ASIDPNE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r14d
LBB0_24:
	orl	(%rax), %ebx
	movq	_CONFIG_CPU_BIG_ENDIAN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_IS_ENABLED
	testq	%rax, %rax
	je	LBB0_26
## %bb.25:
	movq	_SCTLR_E@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
LBB0_26:
	orl	%r12d, %ebx
	orl	%ebx, %r14d
	movl	-52(%rbp), %ebx                 ## 4-byte Reload
LBB0_27:
	movq	_ARM_SMMU_CB_SCTLR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	movl	%r14d, %ecx
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_arm_smmu_cb_write              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_ARM_SMMU_CB_SCTLR,4,2          ## @ARM_SMMU_CB_SCTLR
	.comm	_CBAR_TYPE_S2_TRANS,8,3         ## @CBAR_TYPE_S2_TRANS
	.comm	_ARM_SMMU_V1,8,3                ## @ARM_SMMU_V1
	.comm	_ARM_SMMU_CTX_FMT_AARCH64,8,3   ## @ARM_SMMU_CTX_FMT_AARCH64
	.comm	_CBA2R_VA64,4,2                 ## @CBA2R_VA64
	.comm	_ARM_SMMU_FEAT_VMID16,4,2       ## @ARM_SMMU_FEAT_VMID16
	.comm	_CBA2R_VMID16,4,2               ## @CBA2R_VMID16
	.comm	_CBAR_TYPE,4,2                  ## @CBAR_TYPE
	.comm	_ARM_SMMU_V2,8,3                ## @ARM_SMMU_V2
	.comm	_CBAR_IRPTNDX,4,2               ## @CBAR_IRPTNDX
	.comm	_CBAR_S1_BPSHCFG,4,2            ## @CBAR_S1_BPSHCFG
	.comm	_CBAR_S1_BPSHCFG_NSH,8,3        ## @CBAR_S1_BPSHCFG_NSH
	.comm	_CBAR_S1_MEMATTR,4,2            ## @CBAR_S1_MEMATTR
	.comm	_CBAR_S1_MEMATTR_WB,8,3         ## @CBAR_S1_MEMATTR_WB
	.comm	_CBAR_VMID,4,2                  ## @CBAR_VMID
	.comm	_ARM_SMMU_CB_TCR2,4,2           ## @ARM_SMMU_CB_TCR2
	.comm	_ARM_SMMU_CB_TCR,4,2            ## @ARM_SMMU_CB_TCR
	.comm	_ARM_SMMU_CTX_FMT_AARCH32_S,8,3 ## @ARM_SMMU_CTX_FMT_AARCH32_S
	.comm	_ARM_SMMU_CB_CONTEXTIDR,4,2     ## @ARM_SMMU_CB_CONTEXTIDR
	.comm	_ARM_SMMU_CB_TTBR0,4,2          ## @ARM_SMMU_CB_TTBR0
	.comm	_ARM_SMMU_CB_TTBR1,4,2          ## @ARM_SMMU_CB_TTBR1
	.comm	_ARM_SMMU_CB_S1_MAIR0,4,2       ## @ARM_SMMU_CB_S1_MAIR0
	.comm	_ARM_SMMU_CB_S1_MAIR1,4,2       ## @ARM_SMMU_CB_S1_MAIR1
	.comm	_SCTLR_CFIE,4,2                 ## @SCTLR_CFIE
	.comm	_SCTLR_CFRE,4,2                 ## @SCTLR_CFRE
	.comm	_SCTLR_AFE,4,2                  ## @SCTLR_AFE
	.comm	_SCTLR_TRE,4,2                  ## @SCTLR_TRE
	.comm	_SCTLR_M,4,2                    ## @SCTLR_M
	.comm	_SCTLR_S1_ASIDPNE,4,2           ## @SCTLR_S1_ASIDPNE
	.comm	_CONFIG_CPU_BIG_ENDIAN,4,2      ## @CONFIG_CPU_BIG_ENDIAN
	.comm	_SCTLR_E,4,2                    ## @SCTLR_E
	.no_dead_strip	_arm_smmu_write_context_bank
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function arm_smmu_write_context_bank
_arm_smmu_write_context_bank:           ; @arm_smmu_write_context_bank
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x1
	mov	x20, x0
	ldr	x25, [x0, #16]
	sxtw	x26, w19
	add	x28, x25, x26, lsl #5
	ldr	x27, [x28, #24]
	cbz	x27, LBB0_5
; %bb.1:
	ldr	x23, [x27]
Lloh0:
	adrp	x8, _CBAR_TYPE_S2_TRANS@GOTPAGE
Lloh1:
	ldr	x8, [x8, _CBAR_TYPE_S2_TRANS@GOTPAGEOFF]
Lloh2:
	ldr	x24, [x8]
	ldr	x8, [x20]
Lloh3:
	adrp	x9, _ARM_SMMU_V1@GOTPAGE
Lloh4:
	ldr	x9, [x9, _ARM_SMMU_V1@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
Lloh6:
	adrp	x22, _ARM_SMMU_FEAT_VMID16@GOTPAGE
Lloh7:
	ldr	x22, [x22, _ARM_SMMU_FEAT_VMID16@GOTPAGEOFF]
	cmp	x8, x9
	b.le	LBB0_6
; %bb.2:
	ldr	x8, [x27, #8]
Lloh8:
	adrp	x9, _ARM_SMMU_CTX_FMT_AARCH64@GOTPAGE
Lloh9:
	ldr	x9, [x9, _ARM_SMMU_CTX_FMT_AARCH64@GOTPAGEOFF]
Lloh10:
	ldr	x9, [x9]
Lloh11:
	adrp	x10, _CBA2R_VA64@GOTPAGE
Lloh12:
	ldr	x10, [x10, _CBA2R_VA64@GOTPAGEOFF]
Lloh13:
	ldr	w10, [x10]
	cmp	x8, x9
	csel	w21, w10, wzr, eq
	ldr	w8, [x20, #8]
	ldr	w9, [x22]
	tst	w9, w8
	b.eq	LBB0_4
; %bb.3:
Lloh14:
	adrp	x8, _CBA2R_VMID16@GOTPAGE
Lloh15:
	ldr	x8, [x8, _CBA2R_VMID16@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
	ldr	x1, [x27, #16]
	bl	_FIELD_PREP
	orr	w21, w0, w21
LBB0_4:
	mov	x0, x19
	bl	_ARM_SMMU_GR1_CBA2R
	mov	x1, x0
	mov	x0, x20
	mov	x2, x21
	bl	_arm_smmu_gr1_write
	ldr	x1, [x27]
	b	LBB0_7
LBB0_5:
	mov	w3, #0
	b	LBB0_22
LBB0_6:
	mov	x1, x23
LBB0_7:
Lloh17:
	adrp	x8, _CBAR_TYPE@GOTPAGE
Lloh18:
	ldr	x8, [x8, _CBAR_TYPE@GOTPAGEOFF]
Lloh19:
	ldr	w0, [x8]
	bl	_FIELD_PREP
	mov	x21, x0
	ldr	x8, [x20]
Lloh20:
	adrp	x9, _ARM_SMMU_V2@GOTPAGE
Lloh21:
	ldr	x9, [x9, _ARM_SMMU_V2@GOTPAGEOFF]
Lloh22:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_9
; %bb.8:
Lloh23:
	adrp	x8, _CBAR_IRPTNDX@GOTPAGE
Lloh24:
	ldr	x8, [x8, _CBAR_IRPTNDX@GOTPAGEOFF]
Lloh25:
	ldr	w0, [x8]
	ldr	x1, [x27, #24]
	bl	_FIELD_PREP
	orr	w21, w0, w21
LBB0_9:
	cmp	x23, x24
	b.ne	LBB0_12
; %bb.10:
	ldr	w8, [x20, #8]
	ldr	w9, [x22]
	tst	w9, w8
	b.ne	LBB0_13
; %bb.11:
Lloh26:
	adrp	x8, _CBAR_VMID@GOTPAGE
Lloh27:
	ldr	x8, [x8, _CBAR_VMID@GOTPAGEOFF]
Lloh28:
	ldr	w0, [x8]
	ldr	x1, [x27, #16]
	bl	_FIELD_PREP
	orr	w21, w0, w21
	b	LBB0_13
LBB0_12:
Lloh29:
	adrp	x8, _CBAR_S1_BPSHCFG@GOTPAGE
Lloh30:
	ldr	x8, [x8, _CBAR_S1_BPSHCFG@GOTPAGEOFF]
Lloh31:
	ldr	w0, [x8]
Lloh32:
	adrp	x8, _CBAR_S1_BPSHCFG_NSH@GOTPAGE
Lloh33:
	ldr	x8, [x8, _CBAR_S1_BPSHCFG_NSH@GOTPAGEOFF]
Lloh34:
	ldr	x1, [x8]
	bl	_FIELD_PREP
	mov	x22, x0
Lloh35:
	adrp	x8, _CBAR_S1_MEMATTR@GOTPAGE
Lloh36:
	ldr	x8, [x8, _CBAR_S1_MEMATTR@GOTPAGEOFF]
Lloh37:
	ldr	w0, [x8]
Lloh38:
	adrp	x8, _CBAR_S1_MEMATTR_WB@GOTPAGE
Lloh39:
	ldr	x8, [x8, _CBAR_S1_MEMATTR_WB@GOTPAGEOFF]
Lloh40:
	ldr	x1, [x8]
	bl	_FIELD_PREP
	orr	w8, w22, w21
	orr	w21, w8, w0
LBB0_13:
	mov	x0, x19
	bl	_ARM_SMMU_GR1_CBAR
	mov	x1, x0
	mov	x0, x20
	mov	x2, x21
	bl	_arm_smmu_gr1_write
	cmp	x23, x24
	b.eq	LBB0_16
; %bb.14:
	ldr	x8, [x20]
Lloh41:
	adrp	x9, _ARM_SMMU_V1@GOTPAGE
Lloh42:
	ldr	x9, [x9, _ARM_SMMU_V1@GOTPAGEOFF]
Lloh43:
	ldr	x9, [x9]
	cmp	x8, x9
	b.le	LBB0_16
; %bb.15:
Lloh44:
	adrp	x8, _ARM_SMMU_CB_TCR2@GOTPAGE
Lloh45:
	ldr	x8, [x8, _ARM_SMMU_CB_TCR2@GOTPAGEOFF]
Lloh46:
	ldr	w2, [x8]
	ldr	x8, [x28]
	ldr	w3, [x8, #4]
	mov	x0, x20
	mov	x1, x19
	bl	_arm_smmu_cb_write
LBB0_16:
Lloh47:
	adrp	x8, _ARM_SMMU_CB_TCR@GOTPAGE
Lloh48:
	ldr	x8, [x8, _ARM_SMMU_CB_TCR@GOTPAGEOFF]
Lloh49:
	ldr	w2, [x8]
	ldr	x8, [x28]
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	bl	_arm_smmu_cb_write
	ldr	x8, [x27, #8]
Lloh50:
	adrp	x9, _ARM_SMMU_CTX_FMT_AARCH32_S@GOTPAGE
Lloh51:
	ldr	x9, [x9, _ARM_SMMU_CTX_FMT_AARCH32_S@GOTPAGEOFF]
Lloh52:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_18
; %bb.17:
Lloh53:
	adrp	x8, _ARM_SMMU_CB_CONTEXTIDR@GOTPAGE
Lloh54:
	ldr	x8, [x8, _ARM_SMMU_CB_CONTEXTIDR@GOTPAGEOFF]
Lloh55:
	ldr	w2, [x8]
	ldr	w3, [x27, #32]
	mov	x0, x20
	mov	x1, x19
	bl	_arm_smmu_cb_write
Lloh56:
	adrp	x8, _ARM_SMMU_CB_TTBR0@GOTPAGE
Lloh57:
	ldr	x8, [x8, _ARM_SMMU_CB_TTBR0@GOTPAGEOFF]
Lloh58:
	ldr	w2, [x8]
	add	x21, x25, x26, lsl #5
	ldr	x8, [x21, #8]
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	bl	_arm_smmu_cb_write
Lloh59:
	adrp	x8, _ARM_SMMU_CB_TTBR1@GOTPAGE
Lloh60:
	ldr	x8, [x8, _ARM_SMMU_CB_TTBR1@GOTPAGEOFF]
Lloh61:
	ldr	w2, [x8]
	ldr	x8, [x21, #8]
	ldr	w3, [x8, #4]
	mov	x0, x20
	mov	x1, x19
	bl	_arm_smmu_cb_write
	cmp	x23, x24
	b.ne	LBB0_20
	b	LBB0_21
LBB0_18:
Lloh62:
	adrp	x8, _ARM_SMMU_CB_TTBR0@GOTPAGE
Lloh63:
	ldr	x8, [x8, _ARM_SMMU_CB_TTBR0@GOTPAGEOFF]
Lloh64:
	ldr	w2, [x8]
	add	x21, x25, x26, lsl #5
	ldr	x8, [x21, #8]!
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	bl	_arm_smmu_cb_writeq
	cmp	x23, x24
	b.eq	LBB0_21
; %bb.19:
Lloh65:
	adrp	x8, _ARM_SMMU_CB_TTBR1@GOTPAGE
Lloh66:
	ldr	x8, [x8, _ARM_SMMU_CB_TTBR1@GOTPAGEOFF]
Lloh67:
	ldr	w2, [x8]
	ldr	x8, [x21]
	ldr	w3, [x8, #4]
	mov	x0, x20
	mov	x1, x19
	bl	_arm_smmu_cb_writeq
LBB0_20:
Lloh68:
	adrp	x8, _ARM_SMMU_CB_S1_MAIR0@GOTPAGE
Lloh69:
	ldr	x8, [x8, _ARM_SMMU_CB_S1_MAIR0@GOTPAGEOFF]
Lloh70:
	ldr	w2, [x8]
	add	x21, x25, x26, lsl #5
	ldr	x8, [x21, #16]
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	bl	_arm_smmu_cb_write
Lloh71:
	adrp	x8, _ARM_SMMU_CB_S1_MAIR1@GOTPAGE
Lloh72:
	ldr	x8, [x8, _ARM_SMMU_CB_S1_MAIR1@GOTPAGEOFF]
Lloh73:
	ldr	w2, [x8]
	ldr	x8, [x21, #16]
	ldr	w3, [x8, #4]
	mov	x0, x20
	mov	x1, x19
	bl	_arm_smmu_cb_write
LBB0_21:
Lloh74:
	adrp	x8, _SCTLR_CFIE@GOTPAGE
Lloh75:
	ldr	x8, [x8, _SCTLR_CFIE@GOTPAGEOFF]
Lloh76:
	adrp	x9, _SCTLR_CFRE@GOTPAGE
Lloh77:
	ldr	x9, [x9, _SCTLR_CFRE@GOTPAGEOFF]
Lloh78:
	ldr	w8, [x8]
Lloh79:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh80:
	adrp	x9, _SCTLR_AFE@GOTPAGE
Lloh81:
	ldr	x9, [x9, _SCTLR_AFE@GOTPAGEOFF]
Lloh82:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh83:
	adrp	x9, _SCTLR_TRE@GOTPAGE
Lloh84:
	ldr	x9, [x9, _SCTLR_TRE@GOTPAGEOFF]
Lloh85:
	ldr	w9, [x9]
Lloh86:
	adrp	x10, _SCTLR_M@GOTPAGE
Lloh87:
	ldr	x10, [x10, _SCTLR_M@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh88:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh89:
	adrp	x9, _SCTLR_S1_ASIDPNE@GOTPAGE
Lloh90:
	ldr	x9, [x9, _SCTLR_S1_ASIDPNE@GOTPAGEOFF]
Lloh91:
	ldr	w9, [x9]
	cmp	x23, x24
	csel	w9, wzr, w9, eq
	orr	w21, w8, w9
Lloh92:
	adrp	x8, _CONFIG_CPU_BIG_ENDIAN@GOTPAGE
Lloh93:
	ldr	x8, [x8, _CONFIG_CPU_BIG_ENDIAN@GOTPAGEOFF]
Lloh94:
	ldr	w0, [x8]
	bl	_IS_ENABLED
Lloh95:
	adrp	x8, _SCTLR_E@GOTPAGE
Lloh96:
	ldr	x8, [x8, _SCTLR_E@GOTPAGEOFF]
Lloh97:
	ldr	w8, [x8]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w3, w21, w8
LBB0_22:
Lloh98:
	adrp	x8, _ARM_SMMU_CB_SCTLR@GOTPAGE
Lloh99:
	ldr	x8, [x8, _ARM_SMMU_CB_SCTLR@GOTPAGEOFF]
Lloh100:
	ldr	w2, [x8]
	mov	x0, x20
	mov	x1, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_arm_smmu_cb_write
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh78
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.cfi_endproc
                                        ; -- End function
	.comm	_ARM_SMMU_CB_SCTLR,4,2          ; @ARM_SMMU_CB_SCTLR
	.comm	_CBAR_TYPE_S2_TRANS,8,3         ; @CBAR_TYPE_S2_TRANS
	.comm	_ARM_SMMU_V1,8,3                ; @ARM_SMMU_V1
	.comm	_ARM_SMMU_CTX_FMT_AARCH64,8,3   ; @ARM_SMMU_CTX_FMT_AARCH64
	.comm	_CBA2R_VA64,4,2                 ; @CBA2R_VA64
	.comm	_ARM_SMMU_FEAT_VMID16,4,2       ; @ARM_SMMU_FEAT_VMID16
	.comm	_CBA2R_VMID16,4,2               ; @CBA2R_VMID16
	.comm	_CBAR_TYPE,4,2                  ; @CBAR_TYPE
	.comm	_ARM_SMMU_V2,8,3                ; @ARM_SMMU_V2
	.comm	_CBAR_IRPTNDX,4,2               ; @CBAR_IRPTNDX
	.comm	_CBAR_S1_BPSHCFG,4,2            ; @CBAR_S1_BPSHCFG
	.comm	_CBAR_S1_BPSHCFG_NSH,8,3        ; @CBAR_S1_BPSHCFG_NSH
	.comm	_CBAR_S1_MEMATTR,4,2            ; @CBAR_S1_MEMATTR
	.comm	_CBAR_S1_MEMATTR_WB,8,3         ; @CBAR_S1_MEMATTR_WB
	.comm	_CBAR_VMID,4,2                  ; @CBAR_VMID
	.comm	_ARM_SMMU_CB_TCR2,4,2           ; @ARM_SMMU_CB_TCR2
	.comm	_ARM_SMMU_CB_TCR,4,2            ; @ARM_SMMU_CB_TCR
	.comm	_ARM_SMMU_CTX_FMT_AARCH32_S,8,3 ; @ARM_SMMU_CTX_FMT_AARCH32_S
	.comm	_ARM_SMMU_CB_CONTEXTIDR,4,2     ; @ARM_SMMU_CB_CONTEXTIDR
	.comm	_ARM_SMMU_CB_TTBR0,4,2          ; @ARM_SMMU_CB_TTBR0
	.comm	_ARM_SMMU_CB_TTBR1,4,2          ; @ARM_SMMU_CB_TTBR1
	.comm	_ARM_SMMU_CB_S1_MAIR0,4,2       ; @ARM_SMMU_CB_S1_MAIR0
	.comm	_ARM_SMMU_CB_S1_MAIR1,4,2       ; @ARM_SMMU_CB_S1_MAIR1
	.comm	_SCTLR_CFIE,4,2                 ; @SCTLR_CFIE
	.comm	_SCTLR_CFRE,4,2                 ; @SCTLR_CFRE
	.comm	_SCTLR_AFE,4,2                  ; @SCTLR_AFE
	.comm	_SCTLR_TRE,4,2                  ; @SCTLR_TRE
	.comm	_SCTLR_M,4,2                    ; @SCTLR_M
	.comm	_SCTLR_S1_ASIDPNE,4,2           ; @SCTLR_S1_ASIDPNE
	.comm	_CONFIG_CPU_BIG_ENDIAN,4,2      ; @CONFIG_CPU_BIG_ENDIAN
	.comm	_SCTLR_E,4,2                    ; @SCTLR_E
	.no_dead_strip	_arm_smmu_write_context_bank
.subsections_via_symbols
