	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_tegra_emc_prepare_timing_change ## -- Begin function tegra_emc_prepare_timing_change
	.p2align	4, 0x90
_tegra_emc_prepare_timing_change:       ## @tegra_emc_prepare_timing_change
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	callq	_tegra_emc_find_timing
	testq	%rax, %rax
	je	LBB0_3
## %bb.1:
	movq	%rax, %r14
	movl	32(%r12), %eax
	andl	$1, %eax
	movl	(%r14), %edx
	andl	$1, %edx
	jne	LBB0_4
## %bb.2:
	movq	_DLL_CHANGE_OFF@GOTPCREL(%rip), %rcx
	cmpl	%edx, %eax
	je	LBB0_5
	jmp	LBB0_6
LBB0_3:
	movq	_ENOENT@GOTPCREL(%rip), %rax
	xorl	%r15d, %r15d
	subl	(%rax), %r15d
	jmp	LBB0_71
LBB0_4:
	movq	_DLL_CHANGE_ON@GOTPCREL(%rip), %rcx
	cmpl	%edx, %eax
	jne	LBB0_6
LBB0_5:
	movq	_DLL_CHANGE_NONE@GOTPCREL(%rip), %rcx
LBB0_6:
	movl	(%rcx), %r13d
	movq	_EMC_INTSTATUS_CLKCHANGE_COMPLETE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_EMC_INTSTATUS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	16(%r12), %rsi
	callq	_writel
	movq	_EMC_CFG@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	addq	16(%r12), %rdi
	callq	_readl
	movq	_EMC_CFG_PWR_MASK@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_8
## %bb.7:
	movq	_EMC_CFG_POWER_FEATURES_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%ecx, %eax
	movq	(%rbx), %rsi
	addq	16(%r12), %rsi
	movl	%eax, %edi
	callq	_writel
	movl	$5, %r15d
	jmp	LBB0_9
LBB0_8:
	xorl	%r15d, %r15d
LBB0_9:
	movq	(%r12), %rax
	movq	_DRAM_TYPE_DDR3@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	movl	%r13d, -44(%rbp)                ## 4-byte Spill
	jne	LBB0_11
## %bb.10:
	movq	_EMC_SEL_DPD_CTRL_DDR3_MASK@GOTPCREL(%rip), %rax
	jmp	LBB0_12
LBB0_11:
	movq	_EMC_SEL_DPD_CTRL_MASK@GOTPCREL(%rip), %rax
LBB0_12:
	movl	(%rax), %ebx
	movq	_EMC_SEL_DPD_CTRL@GOTPCREL(%rip), %r13
	movq	(%r13), %rdi
	addq	16(%r12), %rdi
	callq	_readl
	testl	%ebx, %eax
	je	LBB0_14
## %bb.13:
	notl	%ebx
	andl	%ebx, %eax
	movq	(%r13), %rsi
	addq	16(%r12), %rsi
	movl	%eax, %edi
	callq	_writel
LBB0_14:
	movq	_EMC_BGBIAS_CTL0@GOTPCREL(%rip), %r13
	movq	(%r13), %rdi
	addq	16(%r12), %rdi
	callq	_readl
	movq	_EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	testl	%edx, 4(%r14)
	setne	%bl
	testl	%eax, %edx
	sete	%cl
	orb	%bl, %cl
	notl	%edx
	movl	$-1, %edi
	cmovel	%edx, %edi
	andl	36(%r12), %edi
	movq	_EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD@GOTPCREL(%rip), %rdx
	testl	%eax, (%rdx)
	jne	LBB0_16
## %bb.15:
	movq	_EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN@GOTPCREL(%rip), %rdx
	testl	%eax, (%rdx)
	sete	%al
	testb	%cl, %al
	jne	LBB0_17
LBB0_16:
	movq	(%r13), %rsi
	addq	16(%r12), %rsi
	callq	_writel
	movl	$5, %r15d
LBB0_17:
	movq	_EMC_XM2DQSPADCTRL2@GOTPCREL(%rip), %r13
	movq	(%r13), %rdi
	addq	16(%r12), %rdi
	callq	_readl
	movl	8(%r14), %esi
	movq	_EMC_XM2DQSPADCTRL2_VREF_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%esi, %ecx
	setne	%bl
	testl	%eax, %ecx
	sete	%dl
	xorl	%edi, %edi
	andb	%bl, %dl
	cmovel	%edi, %ecx
	orl	%eax, %ecx
	movq	_EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%esi, %eax
	setne	%sil
	testl	%eax, %ecx
	sete	%bl
	andb	%sil, %bl
	jne	LBB0_20
## %bb.18:
	testb	%dl, %dl
	jne	LBB0_20
## %bb.19:
	testl	%r15d, %r15d
	jne	LBB0_21
	jmp	LBB0_22
LBB0_20:
	testb	%bl, %bl
	cmovnel	%eax, %edi
	orl	%ecx, %edi
	movq	(%r13), %rsi
	addq	16(%r12), %rsi
	callq	_writel
	movl	$30, %r15d
LBB0_21:
	movq	%r12, %rdi
	callq	_emc_seq_update_timing
	movl	%r15d, %edi
	callq	_udelay
LBB0_22:
	movl	44(%r12), %eax
	cmpl	12(%r14), %eax
	je	LBB0_24
## %bb.23:
	movq	%r12, %rdi
	callq	_emc_seq_disable_auto_cal
	movl	12(%r14), %edi
	movq	_EMC_CTT_TERM_CTRL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	16(%r12), %rsi
	callq	_writel
	movq	%r12, %rdi
	callq	_emc_seq_update_timing
LBB0_24:
	movq	16(%r14), %rdi
	callq	_ARRAY_SIZE
	testl	%eax, %eax
	je	LBB0_27
## %bb.25:
	xorl	%ebx, %ebx
	movq	_emc_burst_regs@GOTPCREL(%rip), %r15
	.p2align	4, 0x90
LBB0_26:                                ## =>This Inner Loop Header: Depth=1
	movq	16(%r14), %rax
	movl	(%rax,%rbx,4), %edi
	movq	(%r15), %rax
	movq	(%rax,%rbx,8), %rsi
	addq	16(%r12), %rsi
	callq	_writel
	incq	%rbx
	movq	16(%r14), %rdi
	callq	_ARRAY_SIZE
	movl	%eax, %eax
	cmpq	%rax, %rbx
	jb	LBB0_26
LBB0_27:
	movl	8(%r14), %edi
	movq	(%r13), %rsi
	addq	16(%r12), %rsi
	callq	_writel
	movl	24(%r14), %edi
	movq	_EMC_ZCAL_INTERVAL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	16(%r12), %rsi
	callq	_writel
	movl	24(%r12), %edi
	movl	64(%r14), %esi
	callq	_tegra_mc_write_emem_configuration
	movq	_EMC_CFG_POWER_FEATURES_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	28(%r14), %esi
	movq	_EMC_CFG@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r12, %rdi
	callq	_emc_ccfifo_writel
	movl	32(%r14), %esi
	cmpl	64(%r12), %esi
	je	LBB0_29
## %bb.28:
	movq	_EMC_AUTO_CAL_CONFIG2@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r12, %rdi
	callq	_emc_ccfifo_writel
LBB0_29:
	movl	36(%r14), %esi
	cmpl	68(%r12), %esi
	movl	-44(%rbp), %r13d                ## 4-byte Reload
	je	LBB0_31
## %bb.30:
	movq	_EMC_AUTO_CAL_CONFIG3@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r12, %rdi
	callq	_emc_ccfifo_writel
LBB0_31:
	movl	40(%r14), %esi
	cmpl	72(%r12), %esi
	je	LBB0_33
## %bb.32:
	movq	_EMC_AUTO_CAL_CONFIG_AUTO_CAL_START@GOTPCREL(%rip), %rax
	andl	(%rax), %esi
	movq	_EMC_AUTO_CAL_CONFIG@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r12, %rdi
	callq	_emc_ccfifo_writel
LBB0_33:
	movq	(%r12), %rax
	movq	_DLL_CHANGE_ON@GOTPCREL(%rip), %rdx
	movq	_DRAM_TYPE_DDR3@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_39
## %bb.34:
	cmpl	(%rdx), %r13d
	jne	LBB0_39
## %bb.35:
	movl	$512, %eax                      ## imm = 0x200
	cmpl	$0, 24(%r14)
	je	LBB0_38
## %bb.36:
	cmpl	$0, 56(%r12)
	jne	LBB0_38
## %bb.37:
	movl	8(%r12), %ecx
	shll	$8, %ecx
	movl	$512, %eax                      ## imm = 0x200
	subl	%ecx, %eax
LBB0_38:
	movl	44(%r14), %edx
	movq	_EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	andl	%edx, %edi
	movq	_EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %edi
	cmpl	%edi, %eax
	cmovgl	%eax, %edi
	movq	_EMC_MRS_WAIT_CNT_LONG_WAIT_MASK@GOTPCREL(%rip), %rax
	movq	_EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edi
	xorl	%edx, %edi
	andl	(%rax), %edi
	xorl	%edx, %edi
	movq	_EMC_MRS_WAIT_CNT@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	16(%r12), %rsi
	callq	_writel
LBB0_39:
	movq	_EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	48(%r14), %esi
	movq	_EMC_CFG_2@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r12, %rdi
	callq	_emc_ccfifo_writel
	movq	(%r12), %rax
	movq	_DRAM_TYPE_DDR3@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_42
## %bb.40:
	movq	_DLL_CHANGE_OFF@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r13d
	jne	LBB0_42
## %bb.41:
	movl	(%r14), %esi
	movq	_EMC_EMRS@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r12, %rdi
	callq	_emc_ccfifo_writel
LBB0_42:
	movl	8(%r12), %edi
	callq	_EMC_REFCTRL_DEV_SEL
	movq	_EMC_REFCTRL@GOTPCREL(%rip), %r15
	movq	(%r15), %rdx
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_emc_ccfifo_writel
	movq	(%r12), %rax
	movq	_DRAM_TYPE_DDR3@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_44
## %bb.43:
	movl	8(%r12), %edi
	callq	_EMC_DRAM_DEV_SEL
	movq	_EMC_SELF_REF_CMD_ENABLED@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_EMC_SELF_REF@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rdx
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_emc_ccfifo_writel
LBB0_44:
	movq	_EMC_STALL_THEN_EXE_AFTER_CLKCHANGE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r12, %rdi
	movl	$1, %esi
	callq	_emc_ccfifo_writel
	movq	(%r12), %rax
	movq	_DRAM_TYPE_DDR3@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_46
## %bb.45:
	movl	8(%r12), %edi
	callq	_EMC_DRAM_DEV_SEL
	movq	_EMC_SELF_REF@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rdx
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_emc_ccfifo_writel
LBB0_46:
	movl	8(%r12), %edi
	callq	_EMC_REFCTRL_DEV_SEL
	movq	_EMC_REFCTRL_ENABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	(%r15), %rdx
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_emc_ccfifo_writel
	movq	(%r12), %rax
	movq	_DRAM_TYPE_DDR3@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_55
## %bb.47:
	movl	(%r14), %esi
	cmpl	32(%r12), %esi
	je	LBB0_49
## %bb.48:
	movq	_EMC_EMRS@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r12, %rdi
	callq	_emc_ccfifo_writel
LBB0_49:
	movl	52(%r14), %esi
	cmpl	84(%r12), %esi
	movq	_DLL_CHANGE_ON@GOTPCREL(%rip), %rbx
	je	LBB0_51
## %bb.50:
	movq	_EMC_EMRS2@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r12, %rdi
	callq	_emc_ccfifo_writel
LBB0_51:
	movl	56(%r14), %eax
	movl	(%rbx), %ecx
	cmpl	88(%r12), %eax
	jne	LBB0_53
## %bb.52:
	cmpl	%ecx, %r13d
	jne	LBB0_64
LBB0_53:
	movq	_EMC_MODE_SET_DLL_RESET@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
	cmpl	%ecx, %r13d
	jne	LBB0_61
## %bb.54:
	orl	%eax, %esi
	movq	_EMC_MODE_SET_LONG_CNT@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	jmp	LBB0_62
LBB0_55:
	movl	52(%r14), %esi
	cmpl	84(%r12), %esi
	je	LBB0_57
## %bb.56:
	movq	_EMC_MRW2@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r12, %rdi
	callq	_emc_ccfifo_writel
LBB0_57:
	movl	(%r14), %esi
	cmpl	32(%r12), %esi
	je	LBB0_59
## %bb.58:
	movq	_EMC_MRW@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r12, %rdi
	callq	_emc_ccfifo_writel
LBB0_59:
	movl	60(%r14), %esi
	cmpl	92(%r12), %esi
	je	LBB0_64
## %bb.60:
	movq	_EMC_MRW4@GOTPCREL(%rip), %rax
	jmp	LBB0_63
LBB0_61:
	notl	%esi
	andl	%eax, %esi
LBB0_62:
	movq	_EMC_MRS@GOTPCREL(%rip), %rax
LBB0_63:
	movq	(%rax), %rdx
	movq	%r12, %rdi
	callq	_emc_ccfifo_writel
LBB0_64:
	cmpl	$0, 24(%r14)
	je	LBB0_68
## %bb.65:
	cmpl	$0, 56(%r12)
	jne	LBB0_68
## %bb.66:
	movq	_EMC_ZQ_CAL_LONG_CMD_DEV0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_EMC_ZQ_CAL@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdx
	movq	%r12, %rdi
	callq	_emc_ccfifo_writel
	cmpl	$2, 8(%r12)
	jl	LBB0_68
## %bb.67:
	movq	_EMC_ZQ_CAL_LONG_CMD_DEV1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	(%rbx), %rdx
	movq	%r12, %rdi
	callq	_emc_ccfifo_writel
LBB0_68:
	movq	_EMC_CCFIFO_STATUS@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	xorl	%r15d, %r15d
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	_emc_ccfifo_writel
	movl	48(%r14), %esi
	movq	_EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR@GOTPCREL(%rip), %rax
	testl	%esi, (%rax)
	je	LBB0_70
## %bb.69:
	movq	_EMC_CFG_2@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r12, %rdi
	callq	_emc_ccfifo_writel
LBB0_70:
	movq	%r12, %rdi
	callq	_emc_seq_disable_auto_cal
	movq	_EMC_INTSTATUS@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	16(%r12), %rdi
	callq	_readl
LBB0_71:
	movl	%r15d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_ENOENT,4,2                     ## @ENOENT
	.comm	_DLL_CHANGE_NONE,4,2            ## @DLL_CHANGE_NONE
	.comm	_DLL_CHANGE_ON,4,2              ## @DLL_CHANGE_ON
	.comm	_DLL_CHANGE_OFF,4,2             ## @DLL_CHANGE_OFF
	.comm	_EMC_INTSTATUS_CLKCHANGE_COMPLETE,4,2 ## @EMC_INTSTATUS_CLKCHANGE_COMPLETE
	.comm	_EMC_INTSTATUS,8,3              ## @EMC_INTSTATUS
	.comm	_EMC_CFG,8,3                    ## @EMC_CFG
	.comm	_EMC_CFG_PWR_MASK,4,2           ## @EMC_CFG_PWR_MASK
	.comm	_EMC_CFG_POWER_FEATURES_MASK,4,2 ## @EMC_CFG_POWER_FEATURES_MASK
	.comm	_DRAM_TYPE_DDR3,8,3             ## @DRAM_TYPE_DDR3
	.comm	_EMC_SEL_DPD_CTRL_DDR3_MASK,4,2 ## @EMC_SEL_DPD_CTRL_DDR3_MASK
	.comm	_EMC_SEL_DPD_CTRL_MASK,4,2      ## @EMC_SEL_DPD_CTRL_MASK
	.comm	_EMC_SEL_DPD_CTRL,8,3           ## @EMC_SEL_DPD_CTRL
	.comm	_EMC_BGBIAS_CTL0,8,3            ## @EMC_BGBIAS_CTL0
	.comm	_EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX,4,2 ## @EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX
	.comm	_EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD,4,2 ## @EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD
	.comm	_EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN,4,2 ## @EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN
	.comm	_EMC_XM2DQSPADCTRL2,8,3         ## @EMC_XM2DQSPADCTRL2
	.comm	_EMC_XM2DQSPADCTRL2_VREF_ENABLE,4,2 ## @EMC_XM2DQSPADCTRL2_VREF_ENABLE
	.comm	_EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE,4,2 ## @EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE
	.comm	_EMC_CTT_TERM_CTRL,8,3          ## @EMC_CTT_TERM_CTRL
	.comm	_emc_burst_regs,8,3             ## @emc_burst_regs
	.comm	_EMC_ZCAL_INTERVAL,8,3          ## @EMC_ZCAL_INTERVAL
	.comm	_EMC_AUTO_CAL_CONFIG2,8,3       ## @EMC_AUTO_CAL_CONFIG2
	.comm	_EMC_AUTO_CAL_CONFIG3,8,3       ## @EMC_AUTO_CAL_CONFIG3
	.comm	_EMC_AUTO_CAL_CONFIG_AUTO_CAL_START,4,2 ## @EMC_AUTO_CAL_CONFIG_AUTO_CAL_START
	.comm	_EMC_AUTO_CAL_CONFIG,8,3        ## @EMC_AUTO_CAL_CONFIG
	.comm	_EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK,4,2 ## @EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK
	.comm	_EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT,4,2 ## @EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT
	.comm	_EMC_MRS_WAIT_CNT_LONG_WAIT_MASK,4,2 ## @EMC_MRS_WAIT_CNT_LONG_WAIT_MASK
	.comm	_EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT,4,2 ## @EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT
	.comm	_EMC_MRS_WAIT_CNT,8,3           ## @EMC_MRS_WAIT_CNT
	.comm	_EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR,4,2 ## @EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR
	.comm	_EMC_CFG_2,8,3                  ## @EMC_CFG_2
	.comm	_EMC_EMRS,8,3                   ## @EMC_EMRS
	.comm	_EMC_REFCTRL,8,3                ## @EMC_REFCTRL
	.comm	_EMC_SELF_REF_CMD_ENABLED,4,2   ## @EMC_SELF_REF_CMD_ENABLED
	.comm	_EMC_SELF_REF,8,3               ## @EMC_SELF_REF
	.comm	_EMC_STALL_THEN_EXE_AFTER_CLKCHANGE,8,3 ## @EMC_STALL_THEN_EXE_AFTER_CLKCHANGE
	.comm	_EMC_REFCTRL_ENABLE,4,2         ## @EMC_REFCTRL_ENABLE
	.comm	_EMC_EMRS2,8,3                  ## @EMC_EMRS2
	.comm	_EMC_MODE_SET_DLL_RESET,4,2     ## @EMC_MODE_SET_DLL_RESET
	.comm	_EMC_MODE_SET_LONG_CNT,4,2      ## @EMC_MODE_SET_LONG_CNT
	.comm	_EMC_MRS,8,3                    ## @EMC_MRS
	.comm	_EMC_MRW2,8,3                   ## @EMC_MRW2
	.comm	_EMC_MRW,8,3                    ## @EMC_MRW
	.comm	_EMC_MRW4,8,3                   ## @EMC_MRW4
	.comm	_EMC_ZQ_CAL_LONG_CMD_DEV0,4,2   ## @EMC_ZQ_CAL_LONG_CMD_DEV0
	.comm	_EMC_ZQ_CAL,8,3                 ## @EMC_ZQ_CAL
	.comm	_EMC_ZQ_CAL_LONG_CMD_DEV1,4,2   ## @EMC_ZQ_CAL_LONG_CMD_DEV1
	.comm	_EMC_CCFIFO_STATUS,8,3          ## @EMC_CCFIFO_STATUS
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_tegra_emc_prepare_timing_change ; -- Begin function tegra_emc_prepare_timing_change
	.p2align	2
_tegra_emc_prepare_timing_change:       ; @tegra_emc_prepare_timing_change
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	bl	_tegra_emc_find_timing
	cbz	x0, LBB0_3
; %bb.1:
	mov	x20, x0
	ldr	w8, [x19, #32]
	and	w8, w8, #0x1
Lloh0:
	adrp	x9, _DLL_CHANGE_NONE@GOTPAGE
Lloh1:
	ldr	x9, [x9, _DLL_CHANGE_NONE@GOTPAGEOFF]
	ldr	w10, [x0]
Lloh2:
	adrp	x11, _DLL_CHANGE_OFF@GOTPAGE
Lloh3:
	ldr	x11, [x11, _DLL_CHANGE_OFF@GOTPAGEOFF]
Lloh4:
	adrp	x26, _DLL_CHANGE_ON@GOTPAGE
Lloh5:
	ldr	x26, [x26, _DLL_CHANGE_ON@GOTPAGEOFF]
	ands	w10, w10, #0x1
	csel	x11, x11, x26, eq
	cmp	w8, w10
	csel	x8, x9, x11, eq
	ldr	w23, [x8]
Lloh6:
	adrp	x8, _EMC_INTSTATUS_CLKCHANGE_COMPLETE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _EMC_INTSTATUS_CLKCHANGE_COMPLETE@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	ldr	x8, [x19, #16]
Lloh9:
	adrp	x9, _EMC_INTSTATUS@GOTPAGE
Lloh10:
	ldr	x9, [x9, _EMC_INTSTATUS@GOTPAGEOFF]
Lloh11:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
	ldr	x8, [x19, #16]
Lloh12:
	adrp	x27, _EMC_CFG@GOTPAGE
Lloh13:
	ldr	x27, [x27, _EMC_CFG@GOTPAGEOFF]
	ldr	x9, [x27]
	add	x0, x9, x8
	bl	_readl
Lloh14:
	adrp	x8, _EMC_CFG_PWR_MASK@GOTPAGE
Lloh15:
	ldr	x8, [x8, _EMC_CFG_PWR_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
Lloh17:
	adrp	x28, _EMC_CFG_POWER_FEATURES_MASK@GOTPAGE
Lloh18:
	ldr	x28, [x28, _EMC_CFG_POWER_FEATURES_MASK@GOTPAGEOFF]
	tst	w8, w0
	b.eq	LBB0_4
; %bb.2:
	ldr	w8, [x28]
	bic	w0, w0, w8
	ldr	x8, [x19, #16]
	ldr	x9, [x27]
	add	x1, x9, x8
	bl	_writel
	mov	w21, #5
	b	LBB0_5
LBB0_3:
Lloh19:
	adrp	x8, _ENOENT@GOTPAGE
Lloh20:
	ldr	x8, [x8, _ENOENT@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_65
LBB0_4:
	mov	w21, #0
LBB0_5:
	ldr	x8, [x19]
Lloh22:
	adrp	x25, _DRAM_TYPE_DDR3@GOTPAGE
Lloh23:
	ldr	x25, [x25, _DRAM_TYPE_DDR3@GOTPAGEOFF]
	ldr	x9, [x25]
Lloh24:
	adrp	x10, _EMC_SEL_DPD_CTRL_DDR3_MASK@GOTPAGE
Lloh25:
	ldr	x10, [x10, _EMC_SEL_DPD_CTRL_DDR3_MASK@GOTPAGEOFF]
Lloh26:
	adrp	x11, _EMC_SEL_DPD_CTRL_MASK@GOTPAGE
Lloh27:
	ldr	x11, [x11, _EMC_SEL_DPD_CTRL_MASK@GOTPAGEOFF]
	cmp	x8, x9
	csel	x8, x10, x11, eq
	ldr	w22, [x8]
	ldr	x8, [x19, #16]
Lloh28:
	adrp	x24, _EMC_SEL_DPD_CTRL@GOTPAGE
Lloh29:
	ldr	x24, [x24, _EMC_SEL_DPD_CTRL@GOTPAGEOFF]
	ldr	x9, [x24]
	add	x0, x9, x8
	bl	_readl
	tst	w0, w22
	b.eq	LBB0_7
; %bb.6:
	bic	w0, w0, w22
	ldr	x8, [x19, #16]
	ldr	x9, [x24]
	add	x1, x9, x8
	bl	_writel
LBB0_7:
	ldr	x8, [x19, #16]
Lloh30:
	adrp	x22, _EMC_BGBIAS_CTL0@GOTPAGE
Lloh31:
	ldr	x22, [x22, _EMC_BGBIAS_CTL0@GOTPAGEOFF]
	ldr	x9, [x22]
	add	x0, x9, x8
	bl	_readl
	ldr	w8, [x19, #36]
	ldr	w9, [x20, #4]
Lloh32:
	adrp	x10, _EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX@GOTPAGE
Lloh33:
	ldr	x10, [x10, _EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX@GOTPAGEOFF]
Lloh34:
	ldr	w11, [x10]
	tst	w11, w9
	cset	w9, ne
	tst	w11, w0
	cset	w10, eq
	orr	w10, w9, w10
	cmp	w10, #0
	mov	w9, #-1
	csinv	w9, w9, w11, ne
Lloh35:
	adrp	x11, _EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD@GOTPAGE
Lloh36:
	ldr	x11, [x11, _EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD@GOTPAGEOFF]
Lloh37:
	ldr	w11, [x11]
	tst	w11, w0
	b.ne	LBB0_9
; %bb.8:
Lloh38:
	adrp	x11, _EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN@GOTPAGE
Lloh39:
	ldr	x11, [x11, _EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN@GOTPAGEOFF]
Lloh40:
	ldr	w11, [x11]
	tst	w11, w0
	cset	w11, eq
	and	w10, w11, w10
	tbnz	w10, #0, LBB0_10
LBB0_9:
	and	w0, w9, w8
	ldr	x8, [x19, #16]
	ldr	x9, [x22]
	add	x1, x9, x8
	bl	_writel
	mov	w21, #5
LBB0_10:
	ldr	x8, [x19, #16]
Lloh41:
	adrp	x22, _EMC_XM2DQSPADCTRL2@GOTPAGE
Lloh42:
	ldr	x22, [x22, _EMC_XM2DQSPADCTRL2@GOTPAGEOFF]
	ldr	x9, [x22]
	add	x0, x9, x8
	bl	_readl
	ldr	w11, [x20, #8]
Lloh43:
	adrp	x8, _EMC_XM2DQSPADCTRL2_VREF_ENABLE@GOTPAGE
Lloh44:
	ldr	x8, [x8, _EMC_XM2DQSPADCTRL2_VREF_ENABLE@GOTPAGEOFF]
Lloh45:
	ldr	w8, [x8]
	tst	w8, w11
	cset	w9, ne
	tst	w8, w0
	cset	w10, eq
	ands	w9, w9, w10
	csel	w8, w8, wzr, ne
	orr	w8, w8, w0
Lloh46:
	adrp	x10, _EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE@GOTPAGE
Lloh47:
	ldr	x10, [x10, _EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE@GOTPAGEOFF]
Lloh48:
	ldr	w10, [x10]
	tst	w10, w11
	cset	w11, ne
	tst	w8, w10
	cset	w12, eq
	and	w11, w11, w12
	tbnz	w11, #0, LBB0_13
; %bb.11:
	tbnz	w9, #0, LBB0_13
; %bb.12:
	cbnz	w21, LBB0_14
	b	LBB0_15
LBB0_13:
	cmp	w11, #0
	csel	w9, w10, wzr, ne
	orr	w0, w9, w8
	ldr	x8, [x19, #16]
	ldr	x9, [x22]
	add	x1, x9, x8
	bl	_writel
	mov	w21, #30
LBB0_14:
	mov	x0, x19
	bl	_emc_seq_update_timing
	mov	x0, x21
	bl	_udelay
LBB0_15:
	ldr	w8, [x19, #44]
	ldr	w9, [x20, #12]
	cmp	w8, w9
	b.eq	LBB0_17
; %bb.16:
	mov	x0, x19
	bl	_emc_seq_disable_auto_cal
	ldr	w0, [x20, #12]
	ldr	x8, [x19, #16]
Lloh49:
	adrp	x9, _EMC_CTT_TERM_CTRL@GOTPAGE
Lloh50:
	ldr	x9, [x9, _EMC_CTT_TERM_CTRL@GOTPAGEOFF]
Lloh51:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
	mov	x0, x19
	bl	_emc_seq_update_timing
LBB0_17:
	ldr	x0, [x20, #16]
	bl	_ARRAY_SIZE
	cbz	w0, LBB0_20
; %bb.18:
	mov	x21, #0
Lloh52:
	adrp	x24, _emc_burst_regs@GOTPAGE
Lloh53:
	ldr	x24, [x24, _emc_burst_regs@GOTPAGEOFF]
LBB0_19:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x20, #16]
	ldr	w0, [x8, x21, lsl #2]
	ldr	x8, [x19, #16]
	ldr	x9, [x24]
	ldr	x9, [x9, x21, lsl #3]
	add	x1, x9, x8
	bl	_writel
	add	x21, x21, #1
	ldr	x0, [x20, #16]
	bl	_ARRAY_SIZE
	cmp	x21, w0, uxtw
	b.lo	LBB0_19
LBB0_20:
	ldr	w0, [x20, #8]
	ldr	x8, [x19, #16]
	ldr	x9, [x22]
	add	x1, x9, x8
	bl	_writel
	ldr	w0, [x20, #24]
	ldr	x8, [x19, #16]
Lloh54:
	adrp	x9, _EMC_ZCAL_INTERVAL@GOTPAGE
Lloh55:
	ldr	x9, [x9, _EMC_ZCAL_INTERVAL@GOTPAGEOFF]
Lloh56:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
	ldr	w0, [x19, #24]
	ldr	w1, [x20, #64]
	bl	_tegra_mc_write_emem_configuration
	ldr	w8, [x20, #28]
	ldr	w9, [x28]
	bic	w1, w8, w9
	ldr	x2, [x27]
	mov	x0, x19
	bl	_emc_ccfifo_writel
	ldr	w1, [x20, #32]
	ldr	w8, [x19, #64]
	cmp	w1, w8
	b.eq	LBB0_22
; %bb.21:
Lloh57:
	adrp	x8, _EMC_AUTO_CAL_CONFIG2@GOTPAGE
Lloh58:
	ldr	x8, [x8, _EMC_AUTO_CAL_CONFIG2@GOTPAGEOFF]
Lloh59:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_emc_ccfifo_writel
LBB0_22:
	ldr	w1, [x20, #36]
	ldr	w8, [x19, #68]
	cmp	w1, w8
	mov	x24, x26
	b.eq	LBB0_24
; %bb.23:
Lloh60:
	adrp	x8, _EMC_AUTO_CAL_CONFIG3@GOTPAGE
Lloh61:
	ldr	x8, [x8, _EMC_AUTO_CAL_CONFIG3@GOTPAGEOFF]
Lloh62:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_emc_ccfifo_writel
LBB0_24:
	ldr	w8, [x20, #40]
	ldr	w9, [x19, #72]
	cmp	w8, w9
	b.eq	LBB0_26
; %bb.25:
Lloh63:
	adrp	x9, _EMC_AUTO_CAL_CONFIG_AUTO_CAL_START@GOTPAGE
Lloh64:
	ldr	x9, [x9, _EMC_AUTO_CAL_CONFIG_AUTO_CAL_START@GOTPAGEOFF]
Lloh65:
	ldr	w9, [x9]
	and	w1, w9, w8
Lloh66:
	adrp	x8, _EMC_AUTO_CAL_CONFIG@GOTPAGE
Lloh67:
	ldr	x8, [x8, _EMC_AUTO_CAL_CONFIG@GOTPAGEOFF]
Lloh68:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_emc_ccfifo_writel
LBB0_26:
	ldr	x8, [x19]
	ldr	x9, [x25]
	cmp	x8, x9
	b.ne	LBB0_33
; %bb.27:
	ldr	w8, [x24]
	cmp	w23, w8
	b.ne	LBB0_33
; %bb.28:
	ldr	w8, [x20, #24]
	cbz	w8, LBB0_31
; %bb.29:
	ldr	w9, [x19, #56]
	mov	w8, #512
	cbnz	w9, LBB0_32
; %bb.30:
	ldr	w9, [x19, #8]
	sub	w8, w8, w9, lsl #8
	b	LBB0_32
LBB0_31:
	mov	w8, #512
LBB0_32:
Lloh69:
	adrp	x9, _EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK@GOTPAGE
Lloh70:
	ldr	x9, [x9, _EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK@GOTPAGEOFF]
	ldr	w10, [x20, #44]
Lloh71:
	ldr	w9, [x9]
	and	w9, w9, w10
Lloh72:
	adrp	x11, _EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT@GOTPAGE
Lloh73:
	ldr	x11, [x11, _EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT@GOTPAGEOFF]
Lloh74:
	ldr	w11, [x11]
	asr	w9, w9, w11
	cmp	w8, w9
	csel	w8, w8, w9, gt
Lloh75:
	adrp	x9, _EMC_MRS_WAIT_CNT_LONG_WAIT_MASK@GOTPAGE
Lloh76:
	ldr	x9, [x9, _EMC_MRS_WAIT_CNT_LONG_WAIT_MASK@GOTPAGEOFF]
Lloh77:
	ldr	w9, [x9]
	bic	w10, w10, w9
Lloh78:
	adrp	x11, _EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT@GOTPAGE
Lloh79:
	ldr	x11, [x11, _EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT@GOTPAGEOFF]
Lloh80:
	ldr	w11, [x11]
	lsl	w8, w8, w11
	and	w8, w8, w9
	orr	w0, w8, w10
	ldr	x8, [x19, #16]
Lloh81:
	adrp	x9, _EMC_MRS_WAIT_CNT@GOTPAGE
Lloh82:
	ldr	x9, [x9, _EMC_MRS_WAIT_CNT@GOTPAGEOFF]
Lloh83:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
LBB0_33:
Lloh84:
	adrp	x27, _EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR@GOTPAGE
Lloh85:
	ldr	x27, [x27, _EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR@GOTPAGEOFF]
	ldr	w8, [x20, #48]
	ldr	w9, [x27]
	bic	w1, w8, w9
Lloh86:
	adrp	x21, _EMC_CFG_2@GOTPAGE
Lloh87:
	ldr	x21, [x21, _EMC_CFG_2@GOTPAGEOFF]
	ldr	x2, [x21]
	mov	x0, x19
	bl	_emc_ccfifo_writel
	ldr	x8, [x19]
	ldr	x9, [x25]
	cmp	x8, x9
	b.ne	LBB0_36
; %bb.34:
Lloh88:
	adrp	x8, _DLL_CHANGE_OFF@GOTPAGE
Lloh89:
	ldr	x8, [x8, _DLL_CHANGE_OFF@GOTPAGEOFF]
Lloh90:
	ldr	w8, [x8]
	cmp	w23, w8
	b.ne	LBB0_36
; %bb.35:
	ldr	w1, [x20]
Lloh91:
	adrp	x8, _EMC_EMRS@GOTPAGE
Lloh92:
	ldr	x8, [x8, _EMC_EMRS@GOTPAGEOFF]
Lloh93:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_emc_ccfifo_writel
LBB0_36:
	ldr	w0, [x19, #8]
	bl	_EMC_REFCTRL_DEV_SEL
	mov	x1, x0
Lloh94:
	adrp	x22, _EMC_REFCTRL@GOTPAGE
Lloh95:
	ldr	x22, [x22, _EMC_REFCTRL@GOTPAGEOFF]
	ldr	x2, [x22]
	mov	x0, x19
	bl	_emc_ccfifo_writel
	ldr	x8, [x19]
	ldr	x9, [x25]
Lloh96:
	adrp	x26, _EMC_SELF_REF@GOTPAGE
Lloh97:
	ldr	x26, [x26, _EMC_SELF_REF@GOTPAGEOFF]
	cmp	x8, x9
	b.ne	LBB0_38
; %bb.37:
	ldr	w0, [x19, #8]
	bl	_EMC_DRAM_DEV_SEL
Lloh98:
	adrp	x8, _EMC_SELF_REF_CMD_ENABLED@GOTPAGE
Lloh99:
	ldr	x8, [x8, _EMC_SELF_REF_CMD_ENABLED@GOTPAGEOFF]
Lloh100:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	x2, [x26]
	mov	x0, x19
	bl	_emc_ccfifo_writel
LBB0_38:
Lloh101:
	adrp	x8, _EMC_STALL_THEN_EXE_AFTER_CLKCHANGE@GOTPAGE
Lloh102:
	ldr	x8, [x8, _EMC_STALL_THEN_EXE_AFTER_CLKCHANGE@GOTPAGEOFF]
Lloh103:
	ldr	x2, [x8]
	mov	x0, x19
	mov	w1, #1
	bl	_emc_ccfifo_writel
	ldr	x8, [x19]
	ldr	x9, [x25]
	cmp	x8, x9
	b.ne	LBB0_40
; %bb.39:
	ldr	w0, [x19, #8]
	bl	_EMC_DRAM_DEV_SEL
	mov	x1, x0
	ldr	x2, [x26]
	mov	x0, x19
	bl	_emc_ccfifo_writel
LBB0_40:
	ldr	w0, [x19, #8]
	bl	_EMC_REFCTRL_DEV_SEL
Lloh104:
	adrp	x8, _EMC_REFCTRL_ENABLE@GOTPAGE
Lloh105:
	ldr	x8, [x8, _EMC_REFCTRL_ENABLE@GOTPAGEOFF]
Lloh106:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	x2, [x22]
	mov	x0, x19
	bl	_emc_ccfifo_writel
	ldr	x8, [x19]
	ldr	x9, [x25]
	cmp	x8, x9
	b.ne	LBB0_49
; %bb.41:
	ldr	w1, [x20]
	ldr	w8, [x19, #32]
	cmp	w1, w8
	b.eq	LBB0_43
; %bb.42:
Lloh107:
	adrp	x8, _EMC_EMRS@GOTPAGE
Lloh108:
	ldr	x8, [x8, _EMC_EMRS@GOTPAGEOFF]
Lloh109:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_emc_ccfifo_writel
LBB0_43:
	ldr	w1, [x20, #52]
	ldr	w8, [x19, #84]
	cmp	w1, w8
	b.eq	LBB0_45
; %bb.44:
Lloh110:
	adrp	x8, _EMC_EMRS2@GOTPAGE
Lloh111:
	ldr	x8, [x8, _EMC_EMRS2@GOTPAGEOFF]
Lloh112:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_emc_ccfifo_writel
LBB0_45:
	ldr	w8, [x20, #56]
	ldr	w10, [x19, #88]
	ldr	w9, [x24]
	cmp	w8, w10
	b.ne	LBB0_47
; %bb.46:
	cmp	w23, w9
	b.ne	LBB0_58
LBB0_47:
Lloh113:
	adrp	x10, _EMC_MODE_SET_DLL_RESET@GOTPAGE
Lloh114:
	ldr	x10, [x10, _EMC_MODE_SET_DLL_RESET@GOTPAGEOFF]
Lloh115:
	ldr	w10, [x10]
	cmp	w23, w9
	b.ne	LBB0_55
; %bb.48:
	orr	w8, w10, w8
Lloh116:
	adrp	x9, _EMC_MODE_SET_LONG_CNT@GOTPAGE
Lloh117:
	ldr	x9, [x9, _EMC_MODE_SET_LONG_CNT@GOTPAGEOFF]
Lloh118:
	ldr	w9, [x9]
	orr	w1, w8, w9
	b	LBB0_56
LBB0_49:
	ldr	w1, [x20, #52]
	ldr	w8, [x19, #84]
	cmp	w1, w8
	b.eq	LBB0_51
; %bb.50:
Lloh119:
	adrp	x8, _EMC_MRW2@GOTPAGE
Lloh120:
	ldr	x8, [x8, _EMC_MRW2@GOTPAGEOFF]
Lloh121:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_emc_ccfifo_writel
LBB0_51:
	ldr	w1, [x20]
	ldr	w8, [x19, #32]
	cmp	w1, w8
	b.eq	LBB0_53
; %bb.52:
Lloh122:
	adrp	x8, _EMC_MRW@GOTPAGE
Lloh123:
	ldr	x8, [x8, _EMC_MRW@GOTPAGEOFF]
Lloh124:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_emc_ccfifo_writel
LBB0_53:
	ldr	w1, [x20, #60]
	ldr	w8, [x19, #92]
	cmp	w1, w8
	b.eq	LBB0_58
; %bb.54:
Lloh125:
	adrp	x8, _EMC_MRW4@GOTPAGE
Lloh126:
	ldr	x8, [x8, _EMC_MRW4@GOTPAGEOFF]
	b	LBB0_57
LBB0_55:
	bic	w1, w8, w10
LBB0_56:
Lloh127:
	adrp	x8, _EMC_MRS@GOTPAGE
Lloh128:
	ldr	x8, [x8, _EMC_MRS@GOTPAGEOFF]
LBB0_57:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_emc_ccfifo_writel
LBB0_58:
	ldr	w8, [x20, #24]
	cbz	w8, LBB0_62
; %bb.59:
	ldr	w8, [x19, #56]
	cbnz	w8, LBB0_62
; %bb.60:
Lloh129:
	adrp	x8, _EMC_ZQ_CAL_LONG_CMD_DEV0@GOTPAGE
Lloh130:
	ldr	x8, [x8, _EMC_ZQ_CAL_LONG_CMD_DEV0@GOTPAGEOFF]
Lloh131:
	ldr	w1, [x8]
Lloh132:
	adrp	x22, _EMC_ZQ_CAL@GOTPAGE
Lloh133:
	ldr	x22, [x22, _EMC_ZQ_CAL@GOTPAGEOFF]
	ldr	x2, [x22]
	mov	x0, x19
	bl	_emc_ccfifo_writel
	ldr	w8, [x19, #8]
	cmp	w8, #2
	b.lt	LBB0_62
; %bb.61:
Lloh134:
	adrp	x8, _EMC_ZQ_CAL_LONG_CMD_DEV1@GOTPAGE
Lloh135:
	ldr	x8, [x8, _EMC_ZQ_CAL_LONG_CMD_DEV1@GOTPAGEOFF]
Lloh136:
	ldr	w1, [x8]
	ldr	x2, [x22]
	mov	x0, x19
	bl	_emc_ccfifo_writel
LBB0_62:
Lloh137:
	adrp	x8, _EMC_CCFIFO_STATUS@GOTPAGE
Lloh138:
	ldr	x8, [x8, _EMC_CCFIFO_STATUS@GOTPAGEOFF]
Lloh139:
	ldr	x2, [x8]
	mov	x0, x19
	mov	w1, #0
	bl	_emc_ccfifo_writel
	ldr	w1, [x20, #48]
	ldr	w8, [x27]
	tst	w8, w1
	b.eq	LBB0_64
; %bb.63:
	ldr	x2, [x21]
	mov	x0, x19
	bl	_emc_ccfifo_writel
LBB0_64:
	mov	x0, x19
	bl	_emc_seq_disable_auto_cal
	ldr	x8, [x19, #16]
Lloh140:
	adrp	x9, _EMC_INTSTATUS@GOTPAGE
Lloh141:
	ldr	x9, [x9, _EMC_INTSTATUS@GOTPAGEOFF]
Lloh142:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_readl
	mov	w0, #0
LBB0_65:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGot	Lloh86, Lloh87
	.loh AdrpLdrGot	Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGot	Lloh96, Lloh97
	.loh AdrpLdrGot	Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGot	Lloh125, Lloh126
	.loh AdrpLdrGot	Lloh127, Lloh128
	.loh AdrpLdrGot	Lloh132, Lloh133
	.loh AdrpLdrGotLdr	Lloh129, Lloh130, Lloh131
	.loh AdrpLdrGotLdr	Lloh134, Lloh135, Lloh136
	.loh AdrpLdrGotLdr	Lloh137, Lloh138, Lloh139
	.loh AdrpLdrGotLdr	Lloh140, Lloh141, Lloh142
	.cfi_endproc
                                        ; -- End function
	.comm	_ENOENT,4,2                     ; @ENOENT
	.comm	_DLL_CHANGE_NONE,4,2            ; @DLL_CHANGE_NONE
	.comm	_DLL_CHANGE_ON,4,2              ; @DLL_CHANGE_ON
	.comm	_DLL_CHANGE_OFF,4,2             ; @DLL_CHANGE_OFF
	.comm	_EMC_INTSTATUS_CLKCHANGE_COMPLETE,4,2 ; @EMC_INTSTATUS_CLKCHANGE_COMPLETE
	.comm	_EMC_INTSTATUS,8,3              ; @EMC_INTSTATUS
	.comm	_EMC_CFG,8,3                    ; @EMC_CFG
	.comm	_EMC_CFG_PWR_MASK,4,2           ; @EMC_CFG_PWR_MASK
	.comm	_EMC_CFG_POWER_FEATURES_MASK,4,2 ; @EMC_CFG_POWER_FEATURES_MASK
	.comm	_DRAM_TYPE_DDR3,8,3             ; @DRAM_TYPE_DDR3
	.comm	_EMC_SEL_DPD_CTRL_DDR3_MASK,4,2 ; @EMC_SEL_DPD_CTRL_DDR3_MASK
	.comm	_EMC_SEL_DPD_CTRL_MASK,4,2      ; @EMC_SEL_DPD_CTRL_MASK
	.comm	_EMC_SEL_DPD_CTRL,8,3           ; @EMC_SEL_DPD_CTRL
	.comm	_EMC_BGBIAS_CTL0,8,3            ; @EMC_BGBIAS_CTL0
	.comm	_EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX,4,2 ; @EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX
	.comm	_EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD,4,2 ; @EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD
	.comm	_EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN,4,2 ; @EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN
	.comm	_EMC_XM2DQSPADCTRL2,8,3         ; @EMC_XM2DQSPADCTRL2
	.comm	_EMC_XM2DQSPADCTRL2_VREF_ENABLE,4,2 ; @EMC_XM2DQSPADCTRL2_VREF_ENABLE
	.comm	_EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE,4,2 ; @EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE
	.comm	_EMC_CTT_TERM_CTRL,8,3          ; @EMC_CTT_TERM_CTRL
	.comm	_emc_burst_regs,8,3             ; @emc_burst_regs
	.comm	_EMC_ZCAL_INTERVAL,8,3          ; @EMC_ZCAL_INTERVAL
	.comm	_EMC_AUTO_CAL_CONFIG2,8,3       ; @EMC_AUTO_CAL_CONFIG2
	.comm	_EMC_AUTO_CAL_CONFIG3,8,3       ; @EMC_AUTO_CAL_CONFIG3
	.comm	_EMC_AUTO_CAL_CONFIG_AUTO_CAL_START,4,2 ; @EMC_AUTO_CAL_CONFIG_AUTO_CAL_START
	.comm	_EMC_AUTO_CAL_CONFIG,8,3        ; @EMC_AUTO_CAL_CONFIG
	.comm	_EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK,4,2 ; @EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK
	.comm	_EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT,4,2 ; @EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT
	.comm	_EMC_MRS_WAIT_CNT_LONG_WAIT_MASK,4,2 ; @EMC_MRS_WAIT_CNT_LONG_WAIT_MASK
	.comm	_EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT,4,2 ; @EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT
	.comm	_EMC_MRS_WAIT_CNT,8,3           ; @EMC_MRS_WAIT_CNT
	.comm	_EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR,4,2 ; @EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR
	.comm	_EMC_CFG_2,8,3                  ; @EMC_CFG_2
	.comm	_EMC_EMRS,8,3                   ; @EMC_EMRS
	.comm	_EMC_REFCTRL,8,3                ; @EMC_REFCTRL
	.comm	_EMC_SELF_REF_CMD_ENABLED,4,2   ; @EMC_SELF_REF_CMD_ENABLED
	.comm	_EMC_SELF_REF,8,3               ; @EMC_SELF_REF
	.comm	_EMC_STALL_THEN_EXE_AFTER_CLKCHANGE,8,3 ; @EMC_STALL_THEN_EXE_AFTER_CLKCHANGE
	.comm	_EMC_REFCTRL_ENABLE,4,2         ; @EMC_REFCTRL_ENABLE
	.comm	_EMC_EMRS2,8,3                  ; @EMC_EMRS2
	.comm	_EMC_MODE_SET_DLL_RESET,4,2     ; @EMC_MODE_SET_DLL_RESET
	.comm	_EMC_MODE_SET_LONG_CNT,4,2      ; @EMC_MODE_SET_LONG_CNT
	.comm	_EMC_MRS,8,3                    ; @EMC_MRS
	.comm	_EMC_MRW2,8,3                   ; @EMC_MRW2
	.comm	_EMC_MRW,8,3                    ; @EMC_MRW
	.comm	_EMC_MRW4,8,3                   ; @EMC_MRW4
	.comm	_EMC_ZQ_CAL_LONG_CMD_DEV0,4,2   ; @EMC_ZQ_CAL_LONG_CMD_DEV0
	.comm	_EMC_ZQ_CAL,8,3                 ; @EMC_ZQ_CAL
	.comm	_EMC_ZQ_CAL_LONG_CMD_DEV1,4,2   ; @EMC_ZQ_CAL_LONG_CMD_DEV1
	.comm	_EMC_CCFIFO_STATUS,8,3          ; @EMC_CCFIFO_STATUS
.subsections_via_symbols
