	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function wbcir_init_hw
_wbcir_init_hw:                         ## @wbcir_init_hw
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	_WBCIR_IRQ_NONE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_wbcir_set_irqmask
	movq	_WBCIR_REG_WCEIR_CTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	48(%rbx), %rdi
	movq	_invert@GOTPCREL(%rip), %r15
	xorl	%esi, %esi
	cmpq	$0, (%r15)
	setne	%sil
	shll	$3, %esi
	movl	$9, %edx
	callq	_wbcir_set_bits
	movq	_WBCIR_REG_WCEIR_STS@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	48(%rbx), %rdi
	movl	$23, %esi
	movl	$23, %edx
	callq	_wbcir_set_bits
	movq	_WBCIR_REG_WCEIR_EV_EN@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	48(%rbx), %rdi
	xorl	%r14d, %r14d
	xorl	%esi, %esi
	movl	$7, %edx
	callq	_wbcir_set_bits
	movq	_WBCIR_REG_WCEIR_CFG1@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	48(%rbx), %rdi
	movl	$74, %esi
	movl	$127, %edx
	callq	_wbcir_set_bits
	cmpq	$0, (%r15)
	je	LBB0_2
## %bb.1:
	movq	_WBCIR_IRTX_INV@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
LBB0_2:
	movq	_WBCIR_REG_ECEIR_CCTL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%rbx), %rsi
	movl	%r14d, %edi
	callq	_outb
	movq	_WBCIR_REG_ECEIR_CTS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	40(%rbx), %rsi
	movl	$16, %edi
	callq	_outb
	movl	$1, (%rbx)
	movq	_WBCIR_BANK_2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_wbcir_select_bank
	movq	_WBCIR_EXT_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_WBCIR_REG_SP3_EXCR1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	32(%rbx), %rsi
	callq	_outb
	movq	_WBCIR_REG_SP3_EXCR2@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	32(%rbx), %rsi
	movl	$48, %edi
	callq	_outb
	movq	_WBCIR_REG_SP3_BGDL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	32(%rbx), %rsi
	movl	$15, %edi
	callq	_outb
	movq	_WBCIR_REG_SP3_BGDH@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	32(%rbx), %rsi
	xorl	%edi, %edi
	callq	_outb
	movq	_WBCIR_BANK_0@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_wbcir_select_bank
	movq	_WBCIR_REG_SP3_MCR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	32(%rbx), %rsi
	movl	$192, %edi
	callq	_outb
	movq	_WBCIR_REG_SP3_LSR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	32(%rbx), %rdi
	callq	_inb
	movq	_WBCIR_REG_SP3_MSR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	32(%rbx), %rdi
	callq	_inb
	movq	_WBCIR_BANK_7@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%rbx, %rdi
	callq	_wbcir_select_bank
	movq	_WBCIR_REG_SP3_RCCFG@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	32(%rbx), %rsi
	movl	$144, %edi
	callq	_outb
	movq	_WBCIR_BANK_4@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_wbcir_select_bank
	movq	_WBCIR_REG_SP3_IRCR1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	32(%rbx), %rsi
	xorl	%edi, %edi
	callq	_outb
	movq	_WBCIR_BANK_5@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_wbcir_select_bank
	movq	_txandrx@GOTPCREL(%rip), %rax
	cmpq	$1, (%rax)
	movl	$3, %edi
	sbbl	$0, %edi
	movq	_WBCIR_REG_SP3_IRCR2@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	32(%rbx), %rsi
	callq	_outb
	movq	_WBCIR_BANK_6@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_wbcir_select_bank
	movq	_WBCIR_REG_SP3_IRCR3@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	32(%rbx), %rsi
	movl	$32, %edi
	callq	_outb
	movl	(%r12), %esi
	movq	%rbx, %rdi
	callq	_wbcir_select_bank
	movq	_WBCIR_REG_SP3_IRRXDC@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	32(%rbx), %rsi
	movl	$242, %edi
	callq	_outb
	movq	_WBCIR_REG_SP3_IRTXMC@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	32(%rbx), %rsi
	movl	$105, %edi
	callq	_outb
	movl	$36000, 4(%rbx)                 ## imm = 0x8CA0
	xorl	%edi, %edi
	cmpq	$0, (%r15)
	setne	%dil
	shll	$4, %edi
	movq	_WBCIR_REG_SP3_IRCFG4@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	32(%rbx), %rsi
	callq	_outb
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_wbcir_select_bank
	movq	_WBCIR_REG_SP3_FCR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	32(%rbx), %rsi
	movl	$151, %edi
	callq	_outb
	movq	_WBCIR_REG_SP3_ASCR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	32(%rbx), %rsi
	movl	$224, %edi
	callq	_outb
	movq	_WBCIR_RXSTATE_INACTIVE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 28(%rbx)
	movl	24(%rbx), %edi
	movl	$1, %esi
	callq	_wbcir_idle_rx
	movq	8(%rbx), %rax
	movq	_WBCIR_TXSTATE_ACTIVE@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_4
## %bb.3:
	movq	16(%rbx), %rdi
	callq	_kfree
	movq	$0, 16(%rbx)
	movq	_WBCIR_TXSTATE_INACTIVE@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 8(%rbx)
LBB0_4:
	movq	_WBCIR_IRQ_RX@GOTPCREL(%rip), %rax
	movq	_WBCIR_IRQ_ERR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movq	%rbx, %rdi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_wbcir_set_irqmask              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_WBCIR_IRQ_NONE,4,2             ## @WBCIR_IRQ_NONE
	.comm	_WBCIR_REG_WCEIR_CTL,8,3        ## @WBCIR_REG_WCEIR_CTL
	.comm	_invert,8,3                     ## @invert
	.comm	_WBCIR_REG_WCEIR_STS,8,3        ## @WBCIR_REG_WCEIR_STS
	.comm	_WBCIR_REG_WCEIR_EV_EN,8,3      ## @WBCIR_REG_WCEIR_EV_EN
	.comm	_WBCIR_REG_WCEIR_CFG1,8,3       ## @WBCIR_REG_WCEIR_CFG1
	.comm	_WBCIR_IRTX_INV,4,2             ## @WBCIR_IRTX_INV
	.comm	_WBCIR_REG_ECEIR_CCTL,8,3       ## @WBCIR_REG_ECEIR_CCTL
	.comm	_WBCIR_REG_ECEIR_CTS,8,3        ## @WBCIR_REG_ECEIR_CTS
	.comm	_WBCIR_BANK_2,4,2               ## @WBCIR_BANK_2
	.comm	_WBCIR_EXT_ENABLE,4,2           ## @WBCIR_EXT_ENABLE
	.comm	_WBCIR_REG_SP3_EXCR1,8,3        ## @WBCIR_REG_SP3_EXCR1
	.comm	_WBCIR_REG_SP3_EXCR2,8,3        ## @WBCIR_REG_SP3_EXCR2
	.comm	_WBCIR_REG_SP3_BGDL,8,3         ## @WBCIR_REG_SP3_BGDL
	.comm	_WBCIR_REG_SP3_BGDH,8,3         ## @WBCIR_REG_SP3_BGDH
	.comm	_WBCIR_BANK_0,4,2               ## @WBCIR_BANK_0
	.comm	_WBCIR_REG_SP3_MCR,8,3          ## @WBCIR_REG_SP3_MCR
	.comm	_WBCIR_REG_SP3_LSR,8,3          ## @WBCIR_REG_SP3_LSR
	.comm	_WBCIR_REG_SP3_MSR,8,3          ## @WBCIR_REG_SP3_MSR
	.comm	_WBCIR_BANK_7,4,2               ## @WBCIR_BANK_7
	.comm	_WBCIR_REG_SP3_RCCFG,8,3        ## @WBCIR_REG_SP3_RCCFG
	.comm	_WBCIR_BANK_4,4,2               ## @WBCIR_BANK_4
	.comm	_WBCIR_REG_SP3_IRCR1,8,3        ## @WBCIR_REG_SP3_IRCR1
	.comm	_WBCIR_BANK_5,4,2               ## @WBCIR_BANK_5
	.comm	_txandrx,8,3                    ## @txandrx
	.comm	_WBCIR_REG_SP3_IRCR2,8,3        ## @WBCIR_REG_SP3_IRCR2
	.comm	_WBCIR_BANK_6,4,2               ## @WBCIR_BANK_6
	.comm	_WBCIR_REG_SP3_IRCR3,8,3        ## @WBCIR_REG_SP3_IRCR3
	.comm	_WBCIR_REG_SP3_IRRXDC,8,3       ## @WBCIR_REG_SP3_IRRXDC
	.comm	_WBCIR_REG_SP3_IRTXMC,8,3       ## @WBCIR_REG_SP3_IRTXMC
	.comm	_WBCIR_REG_SP3_IRCFG4,8,3       ## @WBCIR_REG_SP3_IRCFG4
	.comm	_WBCIR_REG_SP3_FCR,8,3          ## @WBCIR_REG_SP3_FCR
	.comm	_WBCIR_REG_SP3_ASCR,8,3         ## @WBCIR_REG_SP3_ASCR
	.comm	_WBCIR_RXSTATE_INACTIVE,4,2     ## @WBCIR_RXSTATE_INACTIVE
	.comm	_WBCIR_TXSTATE_ACTIVE,8,3       ## @WBCIR_TXSTATE_ACTIVE
	.comm	_WBCIR_TXSTATE_INACTIVE,8,3     ## @WBCIR_TXSTATE_INACTIVE
	.comm	_WBCIR_IRQ_RX,4,2               ## @WBCIR_IRQ_RX
	.comm	_WBCIR_IRQ_ERR,4,2              ## @WBCIR_IRQ_ERR
	.no_dead_strip	_wbcir_init_hw
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function wbcir_init_hw
_wbcir_init_hw:                         ; @wbcir_init_hw
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, _WBCIR_IRQ_NONE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _WBCIR_IRQ_NONE@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	bl	_wbcir_set_irqmask
	ldr	x8, [x19, #48]
Lloh3:
	adrp	x9, _WBCIR_REG_WCEIR_CTL@GOTPAGE
Lloh4:
	ldr	x9, [x9, _WBCIR_REG_WCEIR_CTL@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
	add	x0, x9, x8
Lloh6:
	adrp	x20, _invert@GOTPAGE
Lloh7:
	ldr	x20, [x20, _invert@GOTPAGEOFF]
	ldr	x8, [x20]
	cmp	x8, #0
	cset	w8, ne
	lsl	w1, w8, #3
	mov	w2, #9
	bl	_wbcir_set_bits
	ldr	x8, [x19, #48]
Lloh8:
	adrp	x9, _WBCIR_REG_WCEIR_STS@GOTPAGE
Lloh9:
	ldr	x9, [x9, _WBCIR_REG_WCEIR_STS@GOTPAGEOFF]
Lloh10:
	ldr	x9, [x9]
	add	x0, x9, x8
	mov	w1, #23
	mov	w2, #23
	bl	_wbcir_set_bits
	ldr	x8, [x19, #48]
Lloh11:
	adrp	x9, _WBCIR_REG_WCEIR_EV_EN@GOTPAGE
Lloh12:
	ldr	x9, [x9, _WBCIR_REG_WCEIR_EV_EN@GOTPAGEOFF]
Lloh13:
	ldr	x9, [x9]
	add	x0, x9, x8
	mov	w1, #0
	mov	w2, #7
	bl	_wbcir_set_bits
	ldr	x8, [x19, #48]
Lloh14:
	adrp	x9, _WBCIR_REG_WCEIR_CFG1@GOTPAGE
Lloh15:
	ldr	x9, [x9, _WBCIR_REG_WCEIR_CFG1@GOTPAGEOFF]
Lloh16:
	ldr	x9, [x9]
	add	x0, x9, x8
	mov	w1, #74
	mov	w2, #127
	bl	_wbcir_set_bits
	ldr	x8, [x20]
Lloh17:
	adrp	x9, _WBCIR_IRTX_INV@GOTPAGE
Lloh18:
	ldr	x9, [x9, _WBCIR_IRTX_INV@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	cmp	x8, #0
	csel	w0, wzr, w9, eq
	ldr	x8, [x19, #40]
Lloh20:
	adrp	x9, _WBCIR_REG_ECEIR_CCTL@GOTPAGE
Lloh21:
	ldr	x9, [x9, _WBCIR_REG_ECEIR_CCTL@GOTPAGEOFF]
Lloh22:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_outb
	ldr	x8, [x19, #40]
Lloh23:
	adrp	x9, _WBCIR_REG_ECEIR_CTS@GOTPAGE
Lloh24:
	ldr	x9, [x9, _WBCIR_REG_ECEIR_CTS@GOTPAGEOFF]
Lloh25:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #16
	bl	_outb
	mov	w8, #1
	str	w8, [x19]
Lloh26:
	adrp	x8, _WBCIR_BANK_2@GOTPAGE
Lloh27:
	ldr	x8, [x8, _WBCIR_BANK_2@GOTPAGEOFF]
Lloh28:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_wbcir_select_bank
Lloh29:
	adrp	x8, _WBCIR_EXT_ENABLE@GOTPAGE
Lloh30:
	ldr	x8, [x8, _WBCIR_EXT_ENABLE@GOTPAGEOFF]
Lloh31:
	ldr	w0, [x8]
	ldr	x8, [x19, #32]
Lloh32:
	adrp	x9, _WBCIR_REG_SP3_EXCR1@GOTPAGE
Lloh33:
	ldr	x9, [x9, _WBCIR_REG_SP3_EXCR1@GOTPAGEOFF]
Lloh34:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_outb
	ldr	x8, [x19, #32]
Lloh35:
	adrp	x9, _WBCIR_REG_SP3_EXCR2@GOTPAGE
Lloh36:
	ldr	x9, [x9, _WBCIR_REG_SP3_EXCR2@GOTPAGEOFF]
Lloh37:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #48
	bl	_outb
	ldr	x8, [x19, #32]
Lloh38:
	adrp	x9, _WBCIR_REG_SP3_BGDL@GOTPAGE
Lloh39:
	ldr	x9, [x9, _WBCIR_REG_SP3_BGDL@GOTPAGEOFF]
Lloh40:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #15
	bl	_outb
	ldr	x8, [x19, #32]
Lloh41:
	adrp	x9, _WBCIR_REG_SP3_BGDH@GOTPAGE
Lloh42:
	ldr	x9, [x9, _WBCIR_REG_SP3_BGDH@GOTPAGEOFF]
Lloh43:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #0
	bl	_outb
Lloh44:
	adrp	x21, _WBCIR_BANK_0@GOTPAGE
Lloh45:
	ldr	x21, [x21, _WBCIR_BANK_0@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_wbcir_select_bank
	ldr	x8, [x19, #32]
Lloh46:
	adrp	x9, _WBCIR_REG_SP3_MCR@GOTPAGE
Lloh47:
	ldr	x9, [x9, _WBCIR_REG_SP3_MCR@GOTPAGEOFF]
Lloh48:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #192
	bl	_outb
	ldr	x8, [x19, #32]
Lloh49:
	adrp	x9, _WBCIR_REG_SP3_LSR@GOTPAGE
Lloh50:
	ldr	x9, [x9, _WBCIR_REG_SP3_LSR@GOTPAGEOFF]
Lloh51:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_inb
	ldr	x8, [x19, #32]
Lloh52:
	adrp	x9, _WBCIR_REG_SP3_MSR@GOTPAGE
Lloh53:
	ldr	x9, [x9, _WBCIR_REG_SP3_MSR@GOTPAGEOFF]
Lloh54:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_inb
Lloh55:
	adrp	x22, _WBCIR_BANK_7@GOTPAGE
Lloh56:
	ldr	x22, [x22, _WBCIR_BANK_7@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x19
	bl	_wbcir_select_bank
	ldr	x8, [x19, #32]
Lloh57:
	adrp	x9, _WBCIR_REG_SP3_RCCFG@GOTPAGE
Lloh58:
	ldr	x9, [x9, _WBCIR_REG_SP3_RCCFG@GOTPAGEOFF]
Lloh59:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #144
	bl	_outb
Lloh60:
	adrp	x8, _WBCIR_BANK_4@GOTPAGE
Lloh61:
	ldr	x8, [x8, _WBCIR_BANK_4@GOTPAGEOFF]
Lloh62:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_wbcir_select_bank
	ldr	x8, [x19, #32]
Lloh63:
	adrp	x9, _WBCIR_REG_SP3_IRCR1@GOTPAGE
Lloh64:
	ldr	x9, [x9, _WBCIR_REG_SP3_IRCR1@GOTPAGEOFF]
Lloh65:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #0
	bl	_outb
Lloh66:
	adrp	x8, _WBCIR_BANK_5@GOTPAGE
Lloh67:
	ldr	x8, [x8, _WBCIR_BANK_5@GOTPAGEOFF]
Lloh68:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_wbcir_select_bank
Lloh69:
	adrp	x8, _txandrx@GOTPAGE
Lloh70:
	ldr	x8, [x8, _txandrx@GOTPAGEOFF]
Lloh71:
	ldr	x8, [x8]
	cmp	x8, #0
	mov	w8, #2
	cinc	w0, w8, ne
	ldr	x8, [x19, #32]
Lloh72:
	adrp	x9, _WBCIR_REG_SP3_IRCR2@GOTPAGE
Lloh73:
	ldr	x9, [x9, _WBCIR_REG_SP3_IRCR2@GOTPAGEOFF]
Lloh74:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_outb
Lloh75:
	adrp	x8, _WBCIR_BANK_6@GOTPAGE
Lloh76:
	ldr	x8, [x8, _WBCIR_BANK_6@GOTPAGEOFF]
Lloh77:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_wbcir_select_bank
	ldr	x8, [x19, #32]
Lloh78:
	adrp	x9, _WBCIR_REG_SP3_IRCR3@GOTPAGE
Lloh79:
	ldr	x9, [x9, _WBCIR_REG_SP3_IRCR3@GOTPAGEOFF]
Lloh80:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #32
	bl	_outb
	ldr	w1, [x22]
	mov	x0, x19
	bl	_wbcir_select_bank
	ldr	x8, [x19, #32]
Lloh81:
	adrp	x9, _WBCIR_REG_SP3_IRRXDC@GOTPAGE
Lloh82:
	ldr	x9, [x9, _WBCIR_REG_SP3_IRRXDC@GOTPAGEOFF]
Lloh83:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #242
	bl	_outb
	ldr	x8, [x19, #32]
Lloh84:
	adrp	x9, _WBCIR_REG_SP3_IRTXMC@GOTPAGE
Lloh85:
	ldr	x9, [x9, _WBCIR_REG_SP3_IRTXMC@GOTPAGEOFF]
Lloh86:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #105
	bl	_outb
	mov	w8, #36000
	str	w8, [x19, #4]
	ldr	x8, [x20]
	cmp	x8, #0
	cset	w8, ne
	lsl	w0, w8, #4
	ldr	x8, [x19, #32]
Lloh87:
	adrp	x9, _WBCIR_REG_SP3_IRCFG4@GOTPAGE
Lloh88:
	ldr	x9, [x9, _WBCIR_REG_SP3_IRCFG4@GOTPAGEOFF]
Lloh89:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_outb
	ldr	w1, [x21]
	mov	x0, x19
	bl	_wbcir_select_bank
	ldr	x8, [x19, #32]
Lloh90:
	adrp	x9, _WBCIR_REG_SP3_FCR@GOTPAGE
Lloh91:
	ldr	x9, [x9, _WBCIR_REG_SP3_FCR@GOTPAGEOFF]
Lloh92:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #151
	bl	_outb
	ldr	x8, [x19, #32]
Lloh93:
	adrp	x9, _WBCIR_REG_SP3_ASCR@GOTPAGE
Lloh94:
	ldr	x9, [x9, _WBCIR_REG_SP3_ASCR@GOTPAGEOFF]
Lloh95:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #224
	bl	_outb
Lloh96:
	adrp	x8, _WBCIR_RXSTATE_INACTIVE@GOTPAGE
Lloh97:
	ldr	x8, [x8, _WBCIR_RXSTATE_INACTIVE@GOTPAGEOFF]
Lloh98:
	ldr	w8, [x8]
	str	w8, [x19, #28]
	ldr	w0, [x19, #24]
	mov	w1, #1
	bl	_wbcir_idle_rx
	ldr	x8, [x19, #8]
Lloh99:
	adrp	x9, _WBCIR_TXSTATE_ACTIVE@GOTPAGE
Lloh100:
	ldr	x9, [x9, _WBCIR_TXSTATE_ACTIVE@GOTPAGEOFF]
Lloh101:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_2
; %bb.1:
	ldr	x0, [x19, #16]
	bl	_kfree
Lloh102:
	adrp	x8, _WBCIR_TXSTATE_INACTIVE@GOTPAGE
Lloh103:
	ldr	x8, [x8, _WBCIR_TXSTATE_INACTIVE@GOTPAGEOFF]
Lloh104:
	ldr	x8, [x8]
	stp	x8, xzr, [x19, #8]
LBB0_2:
Lloh105:
	adrp	x8, _WBCIR_IRQ_RX@GOTPAGE
Lloh106:
	ldr	x8, [x8, _WBCIR_IRQ_RX@GOTPAGEOFF]
Lloh107:
	ldr	w8, [x8]
Lloh108:
	adrp	x9, _WBCIR_IRQ_ERR@GOTPAGE
Lloh109:
	ldr	x9, [x9, _WBCIR_IRQ_ERR@GOTPAGEOFF]
Lloh110:
	ldr	w9, [x9]
	orr	w1, w9, w8
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_wbcir_set_irqmask
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.cfi_endproc
                                        ; -- End function
	.comm	_WBCIR_IRQ_NONE,4,2             ; @WBCIR_IRQ_NONE
	.comm	_WBCIR_REG_WCEIR_CTL,8,3        ; @WBCIR_REG_WCEIR_CTL
	.comm	_invert,8,3                     ; @invert
	.comm	_WBCIR_REG_WCEIR_STS,8,3        ; @WBCIR_REG_WCEIR_STS
	.comm	_WBCIR_REG_WCEIR_EV_EN,8,3      ; @WBCIR_REG_WCEIR_EV_EN
	.comm	_WBCIR_REG_WCEIR_CFG1,8,3       ; @WBCIR_REG_WCEIR_CFG1
	.comm	_WBCIR_IRTX_INV,4,2             ; @WBCIR_IRTX_INV
	.comm	_WBCIR_REG_ECEIR_CCTL,8,3       ; @WBCIR_REG_ECEIR_CCTL
	.comm	_WBCIR_REG_ECEIR_CTS,8,3        ; @WBCIR_REG_ECEIR_CTS
	.comm	_WBCIR_BANK_2,4,2               ; @WBCIR_BANK_2
	.comm	_WBCIR_EXT_ENABLE,4,2           ; @WBCIR_EXT_ENABLE
	.comm	_WBCIR_REG_SP3_EXCR1,8,3        ; @WBCIR_REG_SP3_EXCR1
	.comm	_WBCIR_REG_SP3_EXCR2,8,3        ; @WBCIR_REG_SP3_EXCR2
	.comm	_WBCIR_REG_SP3_BGDL,8,3         ; @WBCIR_REG_SP3_BGDL
	.comm	_WBCIR_REG_SP3_BGDH,8,3         ; @WBCIR_REG_SP3_BGDH
	.comm	_WBCIR_BANK_0,4,2               ; @WBCIR_BANK_0
	.comm	_WBCIR_REG_SP3_MCR,8,3          ; @WBCIR_REG_SP3_MCR
	.comm	_WBCIR_REG_SP3_LSR,8,3          ; @WBCIR_REG_SP3_LSR
	.comm	_WBCIR_REG_SP3_MSR,8,3          ; @WBCIR_REG_SP3_MSR
	.comm	_WBCIR_BANK_7,4,2               ; @WBCIR_BANK_7
	.comm	_WBCIR_REG_SP3_RCCFG,8,3        ; @WBCIR_REG_SP3_RCCFG
	.comm	_WBCIR_BANK_4,4,2               ; @WBCIR_BANK_4
	.comm	_WBCIR_REG_SP3_IRCR1,8,3        ; @WBCIR_REG_SP3_IRCR1
	.comm	_WBCIR_BANK_5,4,2               ; @WBCIR_BANK_5
	.comm	_txandrx,8,3                    ; @txandrx
	.comm	_WBCIR_REG_SP3_IRCR2,8,3        ; @WBCIR_REG_SP3_IRCR2
	.comm	_WBCIR_BANK_6,4,2               ; @WBCIR_BANK_6
	.comm	_WBCIR_REG_SP3_IRCR3,8,3        ; @WBCIR_REG_SP3_IRCR3
	.comm	_WBCIR_REG_SP3_IRRXDC,8,3       ; @WBCIR_REG_SP3_IRRXDC
	.comm	_WBCIR_REG_SP3_IRTXMC,8,3       ; @WBCIR_REG_SP3_IRTXMC
	.comm	_WBCIR_REG_SP3_IRCFG4,8,3       ; @WBCIR_REG_SP3_IRCFG4
	.comm	_WBCIR_REG_SP3_FCR,8,3          ; @WBCIR_REG_SP3_FCR
	.comm	_WBCIR_REG_SP3_ASCR,8,3         ; @WBCIR_REG_SP3_ASCR
	.comm	_WBCIR_RXSTATE_INACTIVE,4,2     ; @WBCIR_RXSTATE_INACTIVE
	.comm	_WBCIR_TXSTATE_ACTIVE,8,3       ; @WBCIR_TXSTATE_ACTIVE
	.comm	_WBCIR_TXSTATE_INACTIVE,8,3     ; @WBCIR_TXSTATE_INACTIVE
	.comm	_WBCIR_IRQ_RX,4,2               ; @WBCIR_IRQ_RX
	.comm	_WBCIR_IRQ_ERR,4,2              ; @WBCIR_IRQ_ERR
	.no_dead_strip	_wbcir_init_hw
.subsections_via_symbols
