	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function intel_spi_hw_cycle
_intel_spi_hw_cycle:                    ## @intel_spi_hw_cycle
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r15d
	movl	%esi, %ebx
	movq	%rdi, %r14
	movq	_HSFSTS_CTL@GOTPCREL(%rip), %r12
	movq	(%r12), %rdi
	addq	(%r14), %rdi
	callq	_readl
	addl	$-128, %ebx
	cmpl	$3, %ebx
	jae	LBB0_1
## %bb.2:
	movq	_INTEL_SPI_FIFO_SZ@GOTPCREL(%rip), %rcx
	cmpl	%r15d, (%rcx)
	jge	LBB0_3
LBB0_1:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
LBB0_9:
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_10:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_3:
	movq	_HSFSTS_CTL_FCYCLE_MASK@GOTPCREL(%rip), %rcx
	movq	_HSFSTS_CTL_FDBC_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	notl	%edx
	andl	%edx, %eax
	movslq	%ebx, %rcx
	leaq	l_switch.table.intel_spi_hw_cycle(%rip), %rdx
	movq	(%rdx,%rcx,8), %rdx
	decl	%r15d
	movq	_HSFSTS_CTL_FDBC_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r15d
	movq	_HSFSTS_CTL_FCERR@GOTPCREL(%rip), %rbx
	movq	_HSFSTS_CTL_FDONE@GOTPCREL(%rip), %rcx
	orl	(%rdx), %eax
	movq	_HSFSTS_CTL_FGO@GOTPCREL(%rip), %rdx
	orl	%r15d, %eax
	orl	(%rbx), %eax
	orl	(%rcx), %eax
	orl	(%rdx), %eax
	movq	(%r12), %rsi
	addq	(%r14), %rsi
	movl	%eax, %edi
	callq	_writel
	movq	%r14, %rdi
	callq	_intel_spi_wait_hw_busy
	testl	%eax, %eax
	jne	LBB0_10
## %bb.4:
	movq	(%r12), %rdi
	addq	(%r14), %rdi
	callq	_readl
	testl	%eax, (%rbx)
	je	LBB0_6
## %bb.5:
	movq	_EIO@GOTPCREL(%rip), %rcx
	jmp	LBB0_9
LBB0_6:
	movq	_HSFSTS_CTL_AEL@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_7
## %bb.8:
	movq	_EACCES@GOTPCREL(%rip), %rcx
	jmp	LBB0_9
LBB0_7:
	xorl	%eax, %eax
	jmp	LBB0_10
	.cfi_endproc
                                        ## -- End function
	.comm	_HSFSTS_CTL,8,3                 ## @HSFSTS_CTL
	.comm	_HSFSTS_CTL_FCYCLE_MASK,4,2     ## @HSFSTS_CTL_FCYCLE_MASK
	.comm	_HSFSTS_CTL_FDBC_MASK,4,2       ## @HSFSTS_CTL_FDBC_MASK
	.comm	_HSFSTS_CTL_FCYCLE_RDID,4,2     ## @HSFSTS_CTL_FCYCLE_RDID
	.comm	_HSFSTS_CTL_FCYCLE_WRSR,4,2     ## @HSFSTS_CTL_FCYCLE_WRSR
	.comm	_HSFSTS_CTL_FCYCLE_RDSR,4,2     ## @HSFSTS_CTL_FCYCLE_RDSR
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_INTEL_SPI_FIFO_SZ,4,2          ## @INTEL_SPI_FIFO_SZ
	.comm	_HSFSTS_CTL_FDBC_SHIFT,4,2      ## @HSFSTS_CTL_FDBC_SHIFT
	.comm	_HSFSTS_CTL_FCERR,4,2           ## @HSFSTS_CTL_FCERR
	.comm	_HSFSTS_CTL_FDONE,4,2           ## @HSFSTS_CTL_FDONE
	.comm	_HSFSTS_CTL_FGO,4,2             ## @HSFSTS_CTL_FGO
	.comm	_EIO,4,2                        ## @EIO
	.comm	_HSFSTS_CTL_AEL,4,2             ## @HSFSTS_CTL_AEL
	.comm	_EACCES,4,2                     ## @EACCES
	.no_dead_strip	_intel_spi_hw_cycle
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.intel_spi_hw_cycle
l_switch.table.intel_spi_hw_cycle:
	.quad	_HSFSTS_CTL_FCYCLE_WRSR
	.quad	_HSFSTS_CTL_FCYCLE_RDSR
	.quad	_HSFSTS_CTL_FCYCLE_RDID

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function intel_spi_hw_cycle
_intel_spi_hw_cycle:                    ; @intel_spi_hw_cycle
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x2
	mov	x21, x1
	mov	x19, x0
	ldr	x8, [x0]
Lloh0:
	adrp	x22, _HSFSTS_CTL@GOTPAGE
Lloh1:
	ldr	x22, [x22, _HSFSTS_CTL@GOTPAGEOFF]
	ldr	x9, [x22]
	add	x0, x9, x8
	bl	_readl
	sub	w8, w21, #128
	cmp	w8, #3
	b.hs	LBB0_2
; %bb.1:
Lloh2:
	adrp	x9, _INTEL_SPI_FIFO_SZ@GOTPAGE
Lloh3:
	ldr	x9, [x9, _INTEL_SPI_FIFO_SZ@GOTPAGEOFF]
Lloh4:
	ldr	w9, [x9]
	cmp	w9, w20
	b.ge	LBB0_5
LBB0_2:
Lloh5:
	adrp	x8, _EINVAL@GOTPAGE
Lloh6:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
LBB0_3:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_4:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_5:
Lloh7:
	adrp	x9, _HSFSTS_CTL_FCYCLE_MASK@GOTPAGE
Lloh8:
	ldr	x9, [x9, _HSFSTS_CTL_FCYCLE_MASK@GOTPAGEOFF]
Lloh9:
	ldr	w9, [x9]
Lloh10:
	adrp	x10, _HSFSTS_CTL_FDBC_MASK@GOTPAGE
Lloh11:
	ldr	x10, [x10, _HSFSTS_CTL_FDBC_MASK@GOTPAGEOFF]
Lloh12:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh13:
	adrp	x10, l_switch.table.intel_spi_hw_cycle@PAGE
Lloh14:
	add	x10, x10, l_switch.table.intel_spi_hw_cycle@PAGEOFF
	ldr	x8, [x10, w8, sxtw #3]
	bic	w9, w0, w9
	ldr	w8, [x8]
	sub	w10, w20, #1
Lloh15:
	adrp	x11, _HSFSTS_CTL_FDBC_SHIFT@GOTPAGE
Lloh16:
	ldr	x11, [x11, _HSFSTS_CTL_FDBC_SHIFT@GOTPAGEOFF]
Lloh17:
	ldr	w11, [x11]
	lsl	w10, w10, w11
Lloh18:
	adrp	x20, _HSFSTS_CTL_FCERR@GOTPAGE
Lloh19:
	ldr	x20, [x20, _HSFSTS_CTL_FCERR@GOTPAGEOFF]
	ldr	w11, [x20]
Lloh20:
	adrp	x12, _HSFSTS_CTL_FDONE@GOTPAGE
Lloh21:
	ldr	x12, [x12, _HSFSTS_CTL_FDONE@GOTPAGEOFF]
Lloh22:
	ldr	w12, [x12]
Lloh23:
	adrp	x13, _HSFSTS_CTL_FGO@GOTPAGE
Lloh24:
	ldr	x13, [x13, _HSFSTS_CTL_FGO@GOTPAGEOFF]
Lloh25:
	ldr	w13, [x13]
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w0, w8, w13
	ldr	x8, [x19]
	ldr	x9, [x22]
	add	x1, x9, x8
	bl	_writel
	mov	x0, x19
	bl	_intel_spi_wait_hw_busy
	cbnz	w0, LBB0_4
; %bb.6:
	ldr	x8, [x19]
	ldr	x9, [x22]
	add	x0, x9, x8
	bl	_readl
	ldr	w8, [x20]
	tst	w8, w0
	b.eq	LBB0_8
; %bb.7:
Lloh26:
	adrp	x8, _EIO@GOTPAGE
Lloh27:
	ldr	x8, [x8, _EIO@GOTPAGEOFF]
	b	LBB0_3
LBB0_8:
Lloh28:
	adrp	x8, _HSFSTS_CTL_AEL@GOTPAGE
Lloh29:
	ldr	x8, [x8, _HSFSTS_CTL_AEL@GOTPAGEOFF]
Lloh30:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_10
; %bb.9:
Lloh31:
	adrp	x8, _EACCES@GOTPAGE
Lloh32:
	ldr	x8, [x8, _EACCES@GOTPAGEOFF]
	b	LBB0_3
LBB0_10:
	mov	w0, #0
	b	LBB0_4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpAdd	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh31, Lloh32
	.cfi_endproc
                                        ; -- End function
	.comm	_HSFSTS_CTL,8,3                 ; @HSFSTS_CTL
	.comm	_HSFSTS_CTL_FCYCLE_MASK,4,2     ; @HSFSTS_CTL_FCYCLE_MASK
	.comm	_HSFSTS_CTL_FDBC_MASK,4,2       ; @HSFSTS_CTL_FDBC_MASK
	.comm	_HSFSTS_CTL_FCYCLE_RDID,4,2     ; @HSFSTS_CTL_FCYCLE_RDID
	.comm	_HSFSTS_CTL_FCYCLE_WRSR,4,2     ; @HSFSTS_CTL_FCYCLE_WRSR
	.comm	_HSFSTS_CTL_FCYCLE_RDSR,4,2     ; @HSFSTS_CTL_FCYCLE_RDSR
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_INTEL_SPI_FIFO_SZ,4,2          ; @INTEL_SPI_FIFO_SZ
	.comm	_HSFSTS_CTL_FDBC_SHIFT,4,2      ; @HSFSTS_CTL_FDBC_SHIFT
	.comm	_HSFSTS_CTL_FCERR,4,2           ; @HSFSTS_CTL_FCERR
	.comm	_HSFSTS_CTL_FDONE,4,2           ; @HSFSTS_CTL_FDONE
	.comm	_HSFSTS_CTL_FGO,4,2             ; @HSFSTS_CTL_FGO
	.comm	_EIO,4,2                        ; @EIO
	.comm	_HSFSTS_CTL_AEL,4,2             ; @HSFSTS_CTL_AEL
	.comm	_EACCES,4,2                     ; @EACCES
	.no_dead_strip	_intel_spi_hw_cycle
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.intel_spi_hw_cycle
l_switch.table.intel_spi_hw_cycle:
	.quad	_HSFSTS_CTL_FCYCLE_WRSR
	.quad	_HSFSTS_CTL_FCYCLE_RDSR
	.quad	_HSFSTS_CTL_FCYCLE_RDID

.subsections_via_symbols
