	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_cudbg_collect_sge_indirect     ## -- Begin function cudbg_collect_sge_indirect
	.p2align	4, 0x90
_cudbg_collect_sge_indirect:            ## @cudbg_collect_sge_indirect
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %r15
	movq	(%rdi), %r12
	xorps	%xmm0, %xmm0
	movaps	%xmm0, -64(%rbp)
	leaq	-64(%rbp), %rcx
	movl	$104, %edx
	callq	_cudbg_get_buff
	testl	%eax, %eax
	jne	LBB0_18
## %bb.1:
	movq	-64(%rbp), %r13
	movq	(%r13), %rcx
	movq	_t5_sge_dbg_index_array@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rax
	movq	(%rax), %rdx
	movq	(%rdx), %rsi
	movq	%rsi, 32(%r13)
	movq	(%rax), %rdx
	movq	8(%rdx), %rdx
	movq	%rdx, 24(%r13)
	movq	(%rax), %rdi
	movq	16(%rdi), %r9
	movq	%r9, 8(%r13)
	movq	(%rax), %rax
	movq	24(%rax), %r8
	movq	%r8, 16(%r13)
	movq	%r12, %rdi
	callq	_t4_read_indirect
	movq	40(%r13), %rcx
	movq	(%rbx), %rax
	movq	8(%rax), %rdx
	movq	(%rdx), %rsi
	movq	%rsi, 72(%r13)
	movq	8(%rax), %rdx
	movq	8(%rdx), %rdx
	movq	%rdx, 64(%r13)
	movq	8(%rax), %rdi
	movq	16(%rdi), %r9
	movq	%r9, 48(%r13)
	movq	8(%rax), %rax
	movq	24(%rax), %r8
	movq	%r8, 56(%r13)
	movq	%r12, %rdi
	callq	_t4_read_indirect
	movl	4(%r12), %edi
	callq	_CHELSIO_CHIP_VERSION
	movq	_CHELSIO_T5@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jle	LBB0_17
## %bb.2:
	movq	_t6_sge_qbase_index_array@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	(%rcx), %rdx
	movq	%rdx, 96(%r13)
	movq	_SGE_QBASE_DATA_REG_NUM@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edi
	testl	%edi, %edi
	jle	LBB0_10
## %bb.3:
	movq	8(%rcx), %rcx
	movq	88(%r13), %rdx
	movq	%rcx, (%rdx)
	cmpl	$1, %edi
	je	LBB0_10
## %bb.4:
	leaq	-1(%rdi), %rsi
	addq	$-2, %rdi
	movl	%esi, %ecx
	andl	$3, %ecx
	movl	$1, %edx
	cmpq	$3, %rdi
	jb	LBB0_8
## %bb.5:
	andq	$-4, %rsi
	xorl	%edx, %edx
	.p2align	4, 0x90
LBB0_6:                                 ## =>This Inner Loop Header: Depth=1
	movq	(%rax), %rdi
	movq	16(%rdi,%rdx,8), %rdi
	movq	88(%r13), %rbx
	movq	%rdi, 8(%rbx,%rdx,8)
	movq	(%rax), %rdi
	movq	24(%rdi,%rdx,8), %rdi
	movq	88(%r13), %rbx
	movq	%rdi, 16(%rbx,%rdx,8)
	movq	(%rax), %rdi
	movq	32(%rdi,%rdx,8), %rdi
	movq	88(%r13), %rbx
	movq	%rdi, 24(%rbx,%rdx,8)
	movq	(%rax), %rdi
	movq	40(%rdi,%rdx,8), %rdi
	movq	88(%r13), %rbx
	movq	%rdi, 32(%rbx,%rdx,8)
	addq	$4, %rdx
	cmpq	%rdx, %rsi
	jne	LBB0_6
## %bb.7:
	incq	%rdx
LBB0_8:
	testq	%rcx, %rcx
	je	LBB0_10
	.p2align	4, 0x90
LBB0_9:                                 ## =>This Inner Loop Header: Depth=1
	movq	(%rax), %rsi
	movq	8(%rsi,%rdx,8), %rsi
	movq	88(%r13), %rdi
	movq	%rsi, (%rdi,%rdx,8)
	incq	%rdx
	decq	%rcx
	jne	LBB0_9
LBB0_10:
	movq	%r14, -72(%rbp)                 ## 8-byte Spill
	addq	$80, %r13
	movq	_PCIE_FW_MASTER_M@GOTPCREL(%rip), %r14
	cmpl	$0, (%r14)
	js	LBB0_13
## %bb.11:
	movl	$-1, %ebx
	.p2align	4, 0x90
LBB0_12:                                ## =>This Inner Loop Header: Depth=1
	incl	%ebx
	movq	%r12, %rdi
	movq	%r13, %rsi
	movl	%ebx, %edx
	movl	$1, %ecx
	callq	_cudbg_read_sge_qbase_indirect_reg
	cmpl	(%r14), %ebx
	jl	LBB0_12
LBB0_13:
	movl	(%r12), %eax
	testl	%eax, %eax
	movq	-72(%rbp), %r14                 ## 8-byte Reload
	jle	LBB0_16
## %bb.14:
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_15:                                ## =>This Inner Loop Header: Depth=1
	movq	%r12, %rdi
	movq	%r13, %rsi
	movl	%ebx, %edx
	xorl	%ecx, %ecx
	callq	_cudbg_read_sge_qbase_indirect_reg
	incl	%ebx
	movl	(%r12), %eax
	cmpl	%eax, %ebx
	jl	LBB0_15
LBB0_16:
	movl	%eax, (%r13)
LBB0_17:
	leaq	-64(%rbp), %rsi
	movq	%r15, %rdi
	movq	%r14, %rdx
	callq	_cudbg_write_and_release_buff
LBB0_18:
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_t5_sge_dbg_index_array,8,3     ## @t5_sge_dbg_index_array
	.comm	_CHELSIO_T5,8,3                 ## @CHELSIO_T5
	.comm	_t6_sge_qbase_index_array,8,3   ## @t6_sge_qbase_index_array
	.comm	_SGE_QBASE_DATA_REG_NUM,4,2     ## @SGE_QBASE_DATA_REG_NUM
	.comm	_PCIE_FW_MASTER_M,4,2           ## @PCIE_FW_MASTER_M
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_cudbg_collect_sge_indirect     ; -- Begin function cudbg_collect_sge_indirect
	.p2align	2
_cudbg_collect_sge_indirect:            ; @cudbg_collect_sge_indirect
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x1
	mov	x20, x0
	ldr	x21, [x0]
	stp	xzr, xzr, [sp]
	mov	x3, sp
	mov	w2, #104
	bl	_cudbg_get_buff
	cbnz	w0, LBB0_14
; %bb.1:
	ldr	x22, [sp]
	ldr	x3, [x22]
Lloh0:
	adrp	x23, _t5_sge_dbg_index_array@GOTPAGE
Lloh1:
	ldr	x23, [x23, _t5_sge_dbg_index_array@GOTPAGEOFF]
	ldr	x8, [x23]
	ldr	x9, [x8]
	ldr	x1, [x9]
	str	x1, [x22, #32]
	ldr	x9, [x8]
	ldr	x2, [x9, #8]
	str	x2, [x22, #24]
	ldr	x9, [x8]
	ldr	x5, [x9, #16]
	str	x5, [x22, #8]
	ldr	x8, [x8]
	ldr	x4, [x8, #24]
	str	x4, [x22, #16]
	mov	x0, x21
	bl	_t4_read_indirect
	ldr	x3, [x22, #40]
	ldr	x8, [x23]
	ldr	x9, [x8, #8]
	ldr	x1, [x9]
	str	x1, [x22, #72]
	ldr	x9, [x8, #8]
	ldr	x2, [x9, #8]
	str	x2, [x22, #64]
	ldr	x9, [x8, #8]
	ldr	x5, [x9, #16]
	str	x5, [x22, #48]
	ldr	x8, [x8, #8]
	ldr	x4, [x8, #24]
	str	x4, [x22, #56]
	mov	x0, x21
	bl	_t4_read_indirect
	ldr	w0, [x21, #4]
	bl	_CHELSIO_CHIP_VERSION
Lloh2:
	adrp	x8, _CHELSIO_T5@GOTPAGE
Lloh3:
	ldr	x8, [x8, _CHELSIO_T5@GOTPAGEOFF]
Lloh4:
	ldr	x8, [x8]
	cmp	x0, x8
	b.le	LBB0_13
; %bb.2:
Lloh5:
	adrp	x8, _t6_sge_qbase_index_array@GOTPAGE
Lloh6:
	ldr	x8, [x8, _t6_sge_qbase_index_array@GOTPAGEOFF]
	ldr	x9, [x8]
	ldr	x10, [x9]
	str	x10, [x22, #96]
Lloh7:
	adrp	x10, _SGE_QBASE_DATA_REG_NUM@GOTPAGE
Lloh8:
	ldr	x10, [x10, _SGE_QBASE_DATA_REG_NUM@GOTPAGEOFF]
Lloh9:
	ldr	w10, [x10]
	cmp	w10, #1
	b.lt	LBB0_6
; %bb.3:
	ldr	x9, [x9, #8]
	ldr	x11, [x22, #88]
	str	x9, [x11]
	cmp	w10, #1
	b.eq	LBB0_6
; %bb.4:
	mov	x9, #0
	sub	x10, x10, #1
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x11, [x8]
	lsl	x12, x9, #3
	add	x11, x11, x12
	ldr	x11, [x11, #16]
	ldr	x13, [x22, #88]
	add	x12, x13, x12
	str	x11, [x12, #8]
	add	x9, x9, #1
	cmp	x10, x9
	b.ne	LBB0_5
LBB0_6:
	add	x22, x22, #80
Lloh10:
	adrp	x24, _PCIE_FW_MASTER_M@GOTPAGE
Lloh11:
	ldr	x24, [x24, _PCIE_FW_MASTER_M@GOTPAGEOFF]
	ldr	w8, [x24]
	tbnz	w8, #31, LBB0_9
; %bb.7:
	mov	w23, #-1
LBB0_8:                                 ; =>This Inner Loop Header: Depth=1
	add	w23, w23, #1
	mov	x0, x21
	mov	x1, x22
	mov	x2, x23
	mov	w3, #1
	bl	_cudbg_read_sge_qbase_indirect_reg
	ldr	w8, [x24]
	cmp	w23, w8
	b.lt	LBB0_8
LBB0_9:
	ldr	w8, [x21]
	cmp	w8, #1
	b.lt	LBB0_12
; %bb.10:
	mov	w23, #0
LBB0_11:                                ; =>This Inner Loop Header: Depth=1
	mov	x0, x21
	mov	x1, x22
	mov	x2, x23
	mov	w3, #0
	bl	_cudbg_read_sge_qbase_indirect_reg
	add	w23, w23, #1
	ldr	w8, [x21]
	cmp	w23, w8
	b.lt	LBB0_11
LBB0_12:
	str	w8, [x22]
LBB0_13:
	mov	x1, sp
	mov	x0, x20
	mov	x2, x19
	bl	_cudbg_write_and_release_buff
LBB0_14:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh10, Lloh11
	.cfi_endproc
                                        ; -- End function
	.comm	_t5_sge_dbg_index_array,8,3     ; @t5_sge_dbg_index_array
	.comm	_CHELSIO_T5,8,3                 ; @CHELSIO_T5
	.comm	_t6_sge_qbase_index_array,8,3   ; @t6_sge_qbase_index_array
	.comm	_SGE_QBASE_DATA_REG_NUM,4,2     ; @SGE_QBASE_DATA_REG_NUM
	.comm	_PCIE_FW_MASTER_M,4,2           ; @PCIE_FW_MASTER_M
.subsections_via_symbols
