	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mtk_iommu_hw_init
_mtk_iommu_hw_init:                     ## @mtk_iommu_hw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movl	16(%rdi), %edi
	callq	_clk_prepare_enable
	testl	%eax, %eax
	je	LBB0_2
## %bb.1:
	movl	%eax, %ebx
	movl	12(%r14), %edi
	leaq	L_.str(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_err
	jmp	LBB0_15
LBB0_2:
	movq	32(%r14), %rax
	movq	(%rax), %rax
	movq	_M4U_MT8173@GOTPCREL(%rip), %rbx
	cmpq	(%rbx), %rax
	je	LBB0_3
## %bb.4:
	movq	_F_MMU_TF_PROT_TO_PROGRAM_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	jmp	LBB0_5
LBB0_3:
	movq	_F_MMU_PREFETCH_RT_REPLACE_MOD@GOTPCREL(%rip), %rax
	movq	_F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	orl	(%rax), %edi
LBB0_5:
	movq	_REG_MMU_CTRL_REG@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	24(%r14), %rsi
	callq	_writel_relaxed
	movq	_F_L2_MULIT_HIT_EN@GOTPCREL(%rip), %rax
	movq	_F_TABLE_WALK_FAULT_INT_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	orl	(%rax), %edi
	movq	_F_PREETCH_FIFO_OVERFLOW_INT_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	_F_MISS_FIFO_OVERFLOW_INT_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	_F_PREFETCH_FIFO_ERR_INT_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	_F_MISS_FIFO_ERR_INT_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	_REG_MMU_INT_CONTROL0@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	24(%r14), %rsi
	callq	_writel_relaxed
	movq	_F_INT_TRANSLATION_FAULT@GOTPCREL(%rip), %rax
	movq	_F_INT_MAIN_MULTI_HIT_FAULT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	orl	(%rax), %edi
	movq	_F_INT_INVALID_PA_FAULT@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	_F_INT_ENTRY_REPLACEMENT_FAULT@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	_F_INT_TLB_MISS_FAULT@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	_F_INT_MISS_TRANSACTION_FIFO_FAULT@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	_F_INT_PRETETCH_TRANSATION_FIFO_FAULT@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	_REG_MMU_INT_MAIN_CONTROL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	24(%r14), %rsi
	callq	_writel_relaxed
	movq	32(%r14), %rax
	movq	(%rax), %rcx
	movl	(%r14), %eax
	cmpq	(%rbx), %rcx
	jne	LBB0_7
## %bb.6:
	sarl	%eax
	movl	4(%r14), %edi
	shll	$31, %edi
	orl	%eax, %edi
	jmp	LBB0_8
LBB0_7:
	movl	%eax, %edi
	callq	_lower_32_bits
	movl	%eax, %ebx
	movl	(%r14), %edi
	callq	_upper_32_bits
	movl	%eax, %edi
	orl	%ebx, %edi
LBB0_8:
	movq	_REG_MMU_IVRP_PADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	24(%r14), %rsi
	callq	_writel_relaxed
	cmpl	$0, 4(%r14)
	je	LBB0_11
## %bb.9:
	movq	32(%r14), %rax
	cmpq	$0, 16(%rax)
	je	LBB0_11
## %bb.10:
	movl	$7, %edi
	movl	$4, %esi
	callq	_F_MMU_VLD_PA_RNG
	movq	_REG_MMU_VLD_PA_RNG@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rsi
	addq	24(%r14), %rsi
	movl	%eax, %edi
	callq	_writel_relaxed
LBB0_11:
	movq	_REG_MMU_DCM_DIS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	24(%r14), %rsi
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	_writel_relaxed
	movq	32(%r14), %rax
	cmpq	$0, 8(%rax)
	je	LBB0_13
## %bb.12:
	movq	_REG_MMU_STANDARD_AXI_MODE@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	24(%r14), %rsi
	xorl	%edi, %edi
	callq	_writel_relaxed
LBB0_13:
	movl	8(%r14), %r15d
	movl	12(%r14), %r12d
	movq	_mtk_iommu_isr@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movl	%r12d, %edi
	callq	_dev_name
	movl	%r12d, %edi
	movl	%r15d, %esi
	movl	%r13d, %edx
	xorl	%ecx, %ecx
	movl	%eax, %r8d
	movq	%r14, %r9
	callq	_devm_request_irq
	testq	%rax, %rax
	je	LBB0_15
## %bb.14:
	movq	_REG_MMU_PT_BASE_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	24(%r14), %rsi
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	_writel_relaxed
	movl	16(%r14), %edi
	callq	_clk_disable_unprepare
	movl	8(%r14), %edx
	movl	12(%r14), %edi
	leaq	L_.str.1(%rip), %rsi
	callq	_dev_err
	movq	_ENODEV@GOTPCREL(%rip), %rax
	subl	(%rax), %ebx
LBB0_15:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Failed to enable iommu bclk(%d)\n"

	.comm	_M4U_MT8173,8,3                 ## @M4U_MT8173
	.comm	_F_MMU_PREFETCH_RT_REPLACE_MOD,4,2 ## @F_MMU_PREFETCH_RT_REPLACE_MOD
	.comm	_F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173,4,2 ## @F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173
	.comm	_F_MMU_TF_PROT_TO_PROGRAM_ADDR,4,2 ## @F_MMU_TF_PROT_TO_PROGRAM_ADDR
	.comm	_REG_MMU_CTRL_REG,8,3           ## @REG_MMU_CTRL_REG
	.comm	_F_L2_MULIT_HIT_EN,4,2          ## @F_L2_MULIT_HIT_EN
	.comm	_F_TABLE_WALK_FAULT_INT_EN,4,2  ## @F_TABLE_WALK_FAULT_INT_EN
	.comm	_F_PREETCH_FIFO_OVERFLOW_INT_EN,4,2 ## @F_PREETCH_FIFO_OVERFLOW_INT_EN
	.comm	_F_MISS_FIFO_OVERFLOW_INT_EN,4,2 ## @F_MISS_FIFO_OVERFLOW_INT_EN
	.comm	_F_PREFETCH_FIFO_ERR_INT_EN,4,2 ## @F_PREFETCH_FIFO_ERR_INT_EN
	.comm	_F_MISS_FIFO_ERR_INT_EN,4,2     ## @F_MISS_FIFO_ERR_INT_EN
	.comm	_REG_MMU_INT_CONTROL0,8,3       ## @REG_MMU_INT_CONTROL0
	.comm	_F_INT_TRANSLATION_FAULT,4,2    ## @F_INT_TRANSLATION_FAULT
	.comm	_F_INT_MAIN_MULTI_HIT_FAULT,4,2 ## @F_INT_MAIN_MULTI_HIT_FAULT
	.comm	_F_INT_INVALID_PA_FAULT,4,2     ## @F_INT_INVALID_PA_FAULT
	.comm	_F_INT_ENTRY_REPLACEMENT_FAULT,4,2 ## @F_INT_ENTRY_REPLACEMENT_FAULT
	.comm	_F_INT_TLB_MISS_FAULT,4,2       ## @F_INT_TLB_MISS_FAULT
	.comm	_F_INT_MISS_TRANSACTION_FIFO_FAULT,4,2 ## @F_INT_MISS_TRANSACTION_FIFO_FAULT
	.comm	_F_INT_PRETETCH_TRANSATION_FIFO_FAULT,4,2 ## @F_INT_PRETETCH_TRANSATION_FIFO_FAULT
	.comm	_REG_MMU_INT_MAIN_CONTROL,8,3   ## @REG_MMU_INT_MAIN_CONTROL
	.comm	_REG_MMU_IVRP_PADDR,8,3         ## @REG_MMU_IVRP_PADDR
	.comm	_REG_MMU_VLD_PA_RNG,8,3         ## @REG_MMU_VLD_PA_RNG
	.comm	_REG_MMU_DCM_DIS,8,3            ## @REG_MMU_DCM_DIS
	.comm	_REG_MMU_STANDARD_AXI_MODE,8,3  ## @REG_MMU_STANDARD_AXI_MODE
	.comm	_mtk_iommu_isr,4,2              ## @mtk_iommu_isr
	.comm	_REG_MMU_PT_BASE_ADDR,8,3       ## @REG_MMU_PT_BASE_ADDR
L_.str.1:                               ## @.str.1
	.asciz	"Failed @ IRQ-%d Request\n"

	.comm	_ENODEV,4,2                     ## @ENODEV
	.no_dead_strip	_mtk_iommu_hw_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mtk_iommu_hw_init
_mtk_iommu_hw_init:                     ; @mtk_iommu_hw_init
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	w0, [x0, #16]
	bl	_clk_prepare_enable
	cbz	w0, LBB0_2
; %bb.1:
	mov	x20, x0
	ldr	w0, [x19, #12]
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	mov	x2, x20
	bl	_dev_err
	b	LBB0_13
LBB0_2:
Lloh2:
	adrp	x20, _M4U_MT8173@GOTPAGE
Lloh3:
	ldr	x20, [x20, _M4U_MT8173@GOTPAGEOFF]
	ldp	x9, x8, [x19, #24]
	ldr	x8, [x8]
Lloh4:
	adrp	x10, _F_MMU_PREFETCH_RT_REPLACE_MOD@GOTPAGE
Lloh5:
	ldr	x10, [x10, _F_MMU_PREFETCH_RT_REPLACE_MOD@GOTPAGEOFF]
Lloh6:
	ldr	w10, [x10]
Lloh7:
	adrp	x11, _F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173@GOTPAGE
Lloh8:
	ldr	x11, [x11, _F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173@GOTPAGEOFF]
Lloh9:
	ldr	w11, [x11]
	orr	w10, w11, w10
	ldr	x11, [x20]
	cmp	x8, x11
Lloh10:
	adrp	x8, _F_MMU_TF_PROT_TO_PROGRAM_ADDR@GOTPAGE
Lloh11:
	ldr	x8, [x8, _F_MMU_TF_PROT_TO_PROGRAM_ADDR@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	csel	w0, w10, w8, eq
Lloh13:
	adrp	x8, _REG_MMU_CTRL_REG@GOTPAGE
Lloh14:
	ldr	x8, [x8, _REG_MMU_CTRL_REG@GOTPAGEOFF]
Lloh15:
	ldr	x8, [x8]
	add	x1, x8, x9
	bl	_writel_relaxed
Lloh16:
	adrp	x8, _F_L2_MULIT_HIT_EN@GOTPAGE
Lloh17:
	ldr	x8, [x8, _F_L2_MULIT_HIT_EN@GOTPAGEOFF]
Lloh18:
	adrp	x9, _F_TABLE_WALK_FAULT_INT_EN@GOTPAGE
Lloh19:
	ldr	x9, [x9, _F_TABLE_WALK_FAULT_INT_EN@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
Lloh21:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh22:
	adrp	x9, _F_PREETCH_FIFO_OVERFLOW_INT_EN@GOTPAGE
Lloh23:
	ldr	x9, [x9, _F_PREETCH_FIFO_OVERFLOW_INT_EN@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh25:
	adrp	x9, _F_MISS_FIFO_OVERFLOW_INT_EN@GOTPAGE
Lloh26:
	ldr	x9, [x9, _F_MISS_FIFO_OVERFLOW_INT_EN@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
Lloh28:
	adrp	x10, _F_PREFETCH_FIFO_ERR_INT_EN@GOTPAGE
Lloh29:
	ldr	x10, [x10, _F_PREFETCH_FIFO_ERR_INT_EN@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh30:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh31:
	adrp	x9, _F_MISS_FIFO_ERR_INT_EN@GOTPAGE
Lloh32:
	ldr	x9, [x9, _F_MISS_FIFO_ERR_INT_EN@GOTPAGEOFF]
Lloh33:
	ldr	w9, [x9]
	orr	w0, w8, w9
	ldr	x8, [x19, #24]
Lloh34:
	adrp	x9, _REG_MMU_INT_CONTROL0@GOTPAGE
Lloh35:
	ldr	x9, [x9, _REG_MMU_INT_CONTROL0@GOTPAGEOFF]
Lloh36:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
Lloh37:
	adrp	x8, _F_INT_TRANSLATION_FAULT@GOTPAGE
Lloh38:
	ldr	x8, [x8, _F_INT_TRANSLATION_FAULT@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
Lloh40:
	adrp	x9, _F_INT_MAIN_MULTI_HIT_FAULT@GOTPAGE
Lloh41:
	ldr	x9, [x9, _F_INT_MAIN_MULTI_HIT_FAULT@GOTPAGEOFF]
Lloh42:
	ldr	w9, [x9]
Lloh43:
	adrp	x10, _F_INT_INVALID_PA_FAULT@GOTPAGE
Lloh44:
	ldr	x10, [x10, _F_INT_INVALID_PA_FAULT@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh45:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh46:
	adrp	x9, _F_INT_ENTRY_REPLACEMENT_FAULT@GOTPAGE
Lloh47:
	ldr	x9, [x9, _F_INT_ENTRY_REPLACEMENT_FAULT@GOTPAGEOFF]
Lloh48:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh49:
	adrp	x9, _F_INT_TLB_MISS_FAULT@GOTPAGE
Lloh50:
	ldr	x9, [x9, _F_INT_TLB_MISS_FAULT@GOTPAGEOFF]
Lloh51:
	ldr	w9, [x9]
Lloh52:
	adrp	x10, _F_INT_MISS_TRANSACTION_FIFO_FAULT@GOTPAGE
Lloh53:
	ldr	x10, [x10, _F_INT_MISS_TRANSACTION_FIFO_FAULT@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh54:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh55:
	adrp	x9, _F_INT_PRETETCH_TRANSATION_FIFO_FAULT@GOTPAGE
Lloh56:
	ldr	x9, [x9, _F_INT_PRETETCH_TRANSATION_FIFO_FAULT@GOTPAGEOFF]
Lloh57:
	ldr	w9, [x9]
	orr	w0, w8, w9
	ldr	x8, [x19, #24]
Lloh58:
	adrp	x9, _REG_MMU_INT_MAIN_CONTROL@GOTPAGE
Lloh59:
	ldr	x9, [x9, _REG_MMU_INT_MAIN_CONTROL@GOTPAGEOFF]
Lloh60:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	x8, [x19, #32]
	ldr	x8, [x8]
	ldr	x9, [x20]
	ldr	w0, [x19]
	cmp	x8, x9
	b.ne	LBB0_4
; %bb.3:
	ldr	w8, [x19, #4]
	lsl	w8, w8, #31
	orr	w0, w8, w0, asr #1
	b	LBB0_5
LBB0_4:
	bl	_lower_32_bits
	mov	x20, x0
	ldr	w0, [x19]
	bl	_upper_32_bits
	orr	w0, w0, w20
LBB0_5:
	ldr	x8, [x19, #24]
Lloh61:
	adrp	x9, _REG_MMU_IVRP_PADDR@GOTPAGE
Lloh62:
	ldr	x9, [x9, _REG_MMU_IVRP_PADDR@GOTPAGEOFF]
Lloh63:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	w8, [x19, #4]
	cbz	w8, LBB0_8
; %bb.6:
	ldr	x8, [x19, #32]
	ldr	x8, [x8, #16]
	cbz	x8, LBB0_8
; %bb.7:
	mov	w0, #7
	mov	w1, #4
	bl	_F_MMU_VLD_PA_RNG
	ldr	x8, [x19, #24]
Lloh64:
	adrp	x9, _REG_MMU_VLD_PA_RNG@GOTPAGE
Lloh65:
	ldr	x9, [x9, _REG_MMU_VLD_PA_RNG@GOTPAGEOFF]
Lloh66:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
LBB0_8:
	ldr	x8, [x19, #24]
Lloh67:
	adrp	x9, _REG_MMU_DCM_DIS@GOTPAGE
Lloh68:
	ldr	x9, [x9, _REG_MMU_DCM_DIS@GOTPAGEOFF]
Lloh69:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #0
	bl	_writel_relaxed
	ldr	x8, [x19, #32]
	ldr	x8, [x8, #8]
	cbz	x8, LBB0_10
; %bb.9:
	ldr	x8, [x19, #24]
Lloh70:
	adrp	x9, _REG_MMU_STANDARD_AXI_MODE@GOTPAGE
Lloh71:
	ldr	x9, [x9, _REG_MMU_STANDARD_AXI_MODE@GOTPAGEOFF]
Lloh72:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #0
	bl	_writel_relaxed
LBB0_10:
	ldp	w21, w20, [x19, #8]
Lloh73:
	adrp	x8, _mtk_iommu_isr@GOTPAGE
Lloh74:
	ldr	x8, [x8, _mtk_iommu_isr@GOTPAGEOFF]
Lloh75:
	ldr	w22, [x8]
	mov	x0, x20
	bl	_dev_name
	mov	x4, x0
	mov	x0, x20
	mov	x1, x21
	mov	x2, x22
	mov	w3, #0
	mov	x5, x19
	bl	_devm_request_irq
	cbz	x0, LBB0_12
; %bb.11:
	ldr	x8, [x19, #24]
Lloh76:
	adrp	x9, _REG_MMU_PT_BASE_ADDR@GOTPAGE
Lloh77:
	ldr	x9, [x9, _REG_MMU_PT_BASE_ADDR@GOTPAGEOFF]
Lloh78:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #0
	bl	_writel_relaxed
	ldr	w0, [x19, #16]
	bl	_clk_disable_unprepare
	ldp	w2, w0, [x19, #8]
Lloh79:
	adrp	x1, l_.str.1@PAGE
Lloh80:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_err
Lloh81:
	adrp	x8, _ENODEV@GOTPAGE
Lloh82:
	ldr	x8, [x8, _ENODEV@GOTPAGEOFF]
Lloh83:
	ldr	w8, [x8]
	neg	w20, w8
	b	LBB0_13
LBB0_12:
	mov	w20, #0
LBB0_13:
	mov	x0, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh20
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpAdd	Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Failed to enable iommu bclk(%d)\n"

	.comm	_M4U_MT8173,8,3                 ; @M4U_MT8173
	.comm	_F_MMU_PREFETCH_RT_REPLACE_MOD,4,2 ; @F_MMU_PREFETCH_RT_REPLACE_MOD
	.comm	_F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173,4,2 ; @F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173
	.comm	_F_MMU_TF_PROT_TO_PROGRAM_ADDR,4,2 ; @F_MMU_TF_PROT_TO_PROGRAM_ADDR
	.comm	_REG_MMU_CTRL_REG,8,3           ; @REG_MMU_CTRL_REG
	.comm	_F_L2_MULIT_HIT_EN,4,2          ; @F_L2_MULIT_HIT_EN
	.comm	_F_TABLE_WALK_FAULT_INT_EN,4,2  ; @F_TABLE_WALK_FAULT_INT_EN
	.comm	_F_PREETCH_FIFO_OVERFLOW_INT_EN,4,2 ; @F_PREETCH_FIFO_OVERFLOW_INT_EN
	.comm	_F_MISS_FIFO_OVERFLOW_INT_EN,4,2 ; @F_MISS_FIFO_OVERFLOW_INT_EN
	.comm	_F_PREFETCH_FIFO_ERR_INT_EN,4,2 ; @F_PREFETCH_FIFO_ERR_INT_EN
	.comm	_F_MISS_FIFO_ERR_INT_EN,4,2     ; @F_MISS_FIFO_ERR_INT_EN
	.comm	_REG_MMU_INT_CONTROL0,8,3       ; @REG_MMU_INT_CONTROL0
	.comm	_F_INT_TRANSLATION_FAULT,4,2    ; @F_INT_TRANSLATION_FAULT
	.comm	_F_INT_MAIN_MULTI_HIT_FAULT,4,2 ; @F_INT_MAIN_MULTI_HIT_FAULT
	.comm	_F_INT_INVALID_PA_FAULT,4,2     ; @F_INT_INVALID_PA_FAULT
	.comm	_F_INT_ENTRY_REPLACEMENT_FAULT,4,2 ; @F_INT_ENTRY_REPLACEMENT_FAULT
	.comm	_F_INT_TLB_MISS_FAULT,4,2       ; @F_INT_TLB_MISS_FAULT
	.comm	_F_INT_MISS_TRANSACTION_FIFO_FAULT,4,2 ; @F_INT_MISS_TRANSACTION_FIFO_FAULT
	.comm	_F_INT_PRETETCH_TRANSATION_FIFO_FAULT,4,2 ; @F_INT_PRETETCH_TRANSATION_FIFO_FAULT
	.comm	_REG_MMU_INT_MAIN_CONTROL,8,3   ; @REG_MMU_INT_MAIN_CONTROL
	.comm	_REG_MMU_IVRP_PADDR,8,3         ; @REG_MMU_IVRP_PADDR
	.comm	_REG_MMU_VLD_PA_RNG,8,3         ; @REG_MMU_VLD_PA_RNG
	.comm	_REG_MMU_DCM_DIS,8,3            ; @REG_MMU_DCM_DIS
	.comm	_REG_MMU_STANDARD_AXI_MODE,8,3  ; @REG_MMU_STANDARD_AXI_MODE
	.comm	_mtk_iommu_isr,4,2              ; @mtk_iommu_isr
	.comm	_REG_MMU_PT_BASE_ADDR,8,3       ; @REG_MMU_PT_BASE_ADDR
l_.str.1:                               ; @.str.1
	.asciz	"Failed @ IRQ-%d Request\n"

	.comm	_ENODEV,4,2                     ; @ENODEV
	.no_dead_strip	_mtk_iommu_hw_init
.subsections_via_symbols
