	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rts524a_extra_init_hw
_rts524a_extra_init_hw:                 ## @rts524a_extra_init_hw
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	callq	_rts5249_extra_init_hw
	movq	_FUNC_FORCE_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_FORCE_ASPM_L1_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%ecx, %edx
	callq	_rtsx_pci_write_register
	movq	_PM_EVENT_DEBUG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PME_DEBUG_0@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%ecx, %edx
	callq	_rtsx_pci_write_register
	movq	_LDO_VCC_CFG1@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	_LDO_VCC_LMT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%ecx, %edx
	callq	_rtsx_pci_write_register
	movq	_PCLK_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PCLK_MODE_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%ecx, %edx
	callq	_rtsx_pci_write_register
	movq	_IC_VER_A@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	movl	$21066, %esi                    ## imm = 0x524A
	callq	_is_version
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	_LDO_DV18_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_LDO_DV18_SR_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_LDO_DV18_SR_DF@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	callq	_rtsx_pci_write_register
	movl	(%r14), %esi
	movq	_LDO_VCC_REF_TUNE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_LDO_VCC_REF_1V2@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	callq	_rtsx_pci_write_register
	movq	_LDO_VIO_CFG@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	_LDO_VIO_REF_TUNE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_LDO_VIO_REF_1V2@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	callq	_rtsx_pci_write_register
	movl	(%r14), %esi
	movq	_LDO_VIO_SR_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_LDO_VIO_SR_DF@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	callq	_rtsx_pci_write_register
	movq	_LDO_DV12S_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_LDO_REF12_TUNE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_LDO_REF12_TUNE_DF@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	callq	_rtsx_pci_write_register
	movq	_SD40_LDO_CTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SD40_VIO_TUNE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_SD40_VIO_TUNE_1V7@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	callq	_rtsx_pci_write_register
LBB0_2:
	xorl	%eax, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_FUNC_FORCE_CTL,4,2             ## @FUNC_FORCE_CTL
	.comm	_FORCE_ASPM_L1_EN,4,2           ## @FORCE_ASPM_L1_EN
	.comm	_PM_EVENT_DEBUG,4,2             ## @PM_EVENT_DEBUG
	.comm	_PME_DEBUG_0,4,2                ## @PME_DEBUG_0
	.comm	_LDO_VCC_CFG1,4,2               ## @LDO_VCC_CFG1
	.comm	_LDO_VCC_LMT_EN,4,2             ## @LDO_VCC_LMT_EN
	.comm	_PCLK_CTL,4,2                   ## @PCLK_CTL
	.comm	_PCLK_MODE_SEL,4,2              ## @PCLK_MODE_SEL
	.comm	_IC_VER_A,4,2                   ## @IC_VER_A
	.comm	_LDO_DV18_CFG,4,2               ## @LDO_DV18_CFG
	.comm	_LDO_DV18_SR_MASK,4,2           ## @LDO_DV18_SR_MASK
	.comm	_LDO_DV18_SR_DF,4,2             ## @LDO_DV18_SR_DF
	.comm	_LDO_VCC_REF_TUNE_MASK,4,2      ## @LDO_VCC_REF_TUNE_MASK
	.comm	_LDO_VCC_REF_1V2,4,2            ## @LDO_VCC_REF_1V2
	.comm	_LDO_VIO_CFG,4,2                ## @LDO_VIO_CFG
	.comm	_LDO_VIO_REF_TUNE_MASK,4,2      ## @LDO_VIO_REF_TUNE_MASK
	.comm	_LDO_VIO_REF_1V2,4,2            ## @LDO_VIO_REF_1V2
	.comm	_LDO_VIO_SR_MASK,4,2            ## @LDO_VIO_SR_MASK
	.comm	_LDO_VIO_SR_DF,4,2              ## @LDO_VIO_SR_DF
	.comm	_LDO_DV12S_CFG,4,2              ## @LDO_DV12S_CFG
	.comm	_LDO_REF12_TUNE_MASK,4,2        ## @LDO_REF12_TUNE_MASK
	.comm	_LDO_REF12_TUNE_DF,4,2          ## @LDO_REF12_TUNE_DF
	.comm	_SD40_LDO_CTL1,4,2              ## @SD40_LDO_CTL1
	.comm	_SD40_VIO_TUNE_MASK,4,2         ## @SD40_VIO_TUNE_MASK
	.comm	_SD40_VIO_TUNE_1V7,4,2          ## @SD40_VIO_TUNE_1V7
	.no_dead_strip	_rts524a_extra_init_hw
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rts524a_extra_init_hw
_rts524a_extra_init_hw:                 ; @rts524a_extra_init_hw
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_rts5249_extra_init_hw
Lloh0:
	adrp	x8, _FUNC_FORCE_CTL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _FUNC_FORCE_CTL@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
Lloh3:
	adrp	x8, _FORCE_ASPM_L1_EN@GOTPAGE
Lloh4:
	ldr	x8, [x8, _FORCE_ASPM_L1_EN@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x3, x2
	bl	_rtsx_pci_write_register
Lloh6:
	adrp	x8, _PM_EVENT_DEBUG@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PM_EVENT_DEBUG@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
Lloh9:
	adrp	x8, _PME_DEBUG_0@GOTPAGE
Lloh10:
	ldr	x8, [x8, _PME_DEBUG_0@GOTPAGEOFF]
Lloh11:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x3, x2
	bl	_rtsx_pci_write_register
Lloh12:
	adrp	x20, _LDO_VCC_CFG1@GOTPAGE
Lloh13:
	ldr	x20, [x20, _LDO_VCC_CFG1@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh14:
	adrp	x8, _LDO_VCC_LMT_EN@GOTPAGE
Lloh15:
	ldr	x8, [x8, _LDO_VCC_LMT_EN@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x3, x2
	bl	_rtsx_pci_write_register
Lloh17:
	adrp	x8, _PCLK_CTL@GOTPAGE
Lloh18:
	ldr	x8, [x8, _PCLK_CTL@GOTPAGEOFF]
Lloh19:
	ldr	w1, [x8]
Lloh20:
	adrp	x8, _PCLK_MODE_SEL@GOTPAGE
Lloh21:
	ldr	x8, [x8, _PCLK_MODE_SEL@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x3, x2
	bl	_rtsx_pci_write_register
Lloh23:
	adrp	x8, _IC_VER_A@GOTPAGE
Lloh24:
	ldr	x8, [x8, _IC_VER_A@GOTPAGEOFF]
Lloh25:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w1, #21066
	bl	_is_version
	cbz	x0, LBB0_2
; %bb.1:
Lloh26:
	adrp	x8, _LDO_DV18_CFG@GOTPAGE
Lloh27:
	ldr	x8, [x8, _LDO_DV18_CFG@GOTPAGEOFF]
Lloh28:
	ldr	w1, [x8]
Lloh29:
	adrp	x8, _LDO_DV18_SR_MASK@GOTPAGE
Lloh30:
	ldr	x8, [x8, _LDO_DV18_SR_MASK@GOTPAGEOFF]
Lloh31:
	ldr	w2, [x8]
Lloh32:
	adrp	x8, _LDO_DV18_SR_DF@GOTPAGE
Lloh33:
	ldr	x8, [x8, _LDO_DV18_SR_DF@GOTPAGEOFF]
Lloh34:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_rtsx_pci_write_register
	ldr	w1, [x20]
Lloh35:
	adrp	x8, _LDO_VCC_REF_TUNE_MASK@GOTPAGE
Lloh36:
	ldr	x8, [x8, _LDO_VCC_REF_TUNE_MASK@GOTPAGEOFF]
Lloh37:
	ldr	w2, [x8]
Lloh38:
	adrp	x8, _LDO_VCC_REF_1V2@GOTPAGE
Lloh39:
	ldr	x8, [x8, _LDO_VCC_REF_1V2@GOTPAGEOFF]
Lloh40:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_rtsx_pci_write_register
Lloh41:
	adrp	x20, _LDO_VIO_CFG@GOTPAGE
Lloh42:
	ldr	x20, [x20, _LDO_VIO_CFG@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh43:
	adrp	x8, _LDO_VIO_REF_TUNE_MASK@GOTPAGE
Lloh44:
	ldr	x8, [x8, _LDO_VIO_REF_TUNE_MASK@GOTPAGEOFF]
Lloh45:
	ldr	w2, [x8]
Lloh46:
	adrp	x8, _LDO_VIO_REF_1V2@GOTPAGE
Lloh47:
	ldr	x8, [x8, _LDO_VIO_REF_1V2@GOTPAGEOFF]
Lloh48:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_rtsx_pci_write_register
	ldr	w1, [x20]
Lloh49:
	adrp	x8, _LDO_VIO_SR_MASK@GOTPAGE
Lloh50:
	ldr	x8, [x8, _LDO_VIO_SR_MASK@GOTPAGEOFF]
Lloh51:
	ldr	w2, [x8]
Lloh52:
	adrp	x8, _LDO_VIO_SR_DF@GOTPAGE
Lloh53:
	ldr	x8, [x8, _LDO_VIO_SR_DF@GOTPAGEOFF]
Lloh54:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_rtsx_pci_write_register
Lloh55:
	adrp	x8, _LDO_DV12S_CFG@GOTPAGE
Lloh56:
	ldr	x8, [x8, _LDO_DV12S_CFG@GOTPAGEOFF]
Lloh57:
	ldr	w1, [x8]
Lloh58:
	adrp	x8, _LDO_REF12_TUNE_MASK@GOTPAGE
Lloh59:
	ldr	x8, [x8, _LDO_REF12_TUNE_MASK@GOTPAGEOFF]
Lloh60:
	ldr	w2, [x8]
Lloh61:
	adrp	x8, _LDO_REF12_TUNE_DF@GOTPAGE
Lloh62:
	ldr	x8, [x8, _LDO_REF12_TUNE_DF@GOTPAGEOFF]
Lloh63:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_rtsx_pci_write_register
Lloh64:
	adrp	x8, _SD40_LDO_CTL1@GOTPAGE
Lloh65:
	ldr	x8, [x8, _SD40_LDO_CTL1@GOTPAGEOFF]
Lloh66:
	ldr	w1, [x8]
Lloh67:
	adrp	x8, _SD40_VIO_TUNE_MASK@GOTPAGE
Lloh68:
	ldr	x8, [x8, _SD40_VIO_TUNE_MASK@GOTPAGEOFF]
Lloh69:
	ldr	w2, [x8]
Lloh70:
	adrp	x8, _SD40_VIO_TUNE_1V7@GOTPAGE
Lloh71:
	ldr	x8, [x8, _SD40_VIO_TUNE_1V7@GOTPAGEOFF]
Lloh72:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_rtsx_pci_write_register
LBB0_2:
	mov	w0, #0
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.cfi_endproc
                                        ; -- End function
	.comm	_FUNC_FORCE_CTL,4,2             ; @FUNC_FORCE_CTL
	.comm	_FORCE_ASPM_L1_EN,4,2           ; @FORCE_ASPM_L1_EN
	.comm	_PM_EVENT_DEBUG,4,2             ; @PM_EVENT_DEBUG
	.comm	_PME_DEBUG_0,4,2                ; @PME_DEBUG_0
	.comm	_LDO_VCC_CFG1,4,2               ; @LDO_VCC_CFG1
	.comm	_LDO_VCC_LMT_EN,4,2             ; @LDO_VCC_LMT_EN
	.comm	_PCLK_CTL,4,2                   ; @PCLK_CTL
	.comm	_PCLK_MODE_SEL,4,2              ; @PCLK_MODE_SEL
	.comm	_IC_VER_A,4,2                   ; @IC_VER_A
	.comm	_LDO_DV18_CFG,4,2               ; @LDO_DV18_CFG
	.comm	_LDO_DV18_SR_MASK,4,2           ; @LDO_DV18_SR_MASK
	.comm	_LDO_DV18_SR_DF,4,2             ; @LDO_DV18_SR_DF
	.comm	_LDO_VCC_REF_TUNE_MASK,4,2      ; @LDO_VCC_REF_TUNE_MASK
	.comm	_LDO_VCC_REF_1V2,4,2            ; @LDO_VCC_REF_1V2
	.comm	_LDO_VIO_CFG,4,2                ; @LDO_VIO_CFG
	.comm	_LDO_VIO_REF_TUNE_MASK,4,2      ; @LDO_VIO_REF_TUNE_MASK
	.comm	_LDO_VIO_REF_1V2,4,2            ; @LDO_VIO_REF_1V2
	.comm	_LDO_VIO_SR_MASK,4,2            ; @LDO_VIO_SR_MASK
	.comm	_LDO_VIO_SR_DF,4,2              ; @LDO_VIO_SR_DF
	.comm	_LDO_DV12S_CFG,4,2              ; @LDO_DV12S_CFG
	.comm	_LDO_REF12_TUNE_MASK,4,2        ; @LDO_REF12_TUNE_MASK
	.comm	_LDO_REF12_TUNE_DF,4,2          ; @LDO_REF12_TUNE_DF
	.comm	_SD40_LDO_CTL1,4,2              ; @SD40_LDO_CTL1
	.comm	_SD40_VIO_TUNE_MASK,4,2         ; @SD40_VIO_TUNE_MASK
	.comm	_SD40_VIO_TUNE_1V7,4,2          ; @SD40_VIO_TUNE_1V7
	.no_dead_strip	_rts524a_extra_init_hw
.subsections_via_symbols
