	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function clock_rate
_clock_rate:                            ## @clock_rate
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_ROOT_CLOCK_RATE@GOTPCREL(%rip), %rax
	movq	(%rax), %r12
	movq	_prcmu_base@GOTPCREL(%rip), %rax
	movq	_clk_mgt@GOTPCREL(%rip), %r15
	movq	(%r15), %rcx
	leaq	(%rdi,%rdi,2), %rbx
	movq	16(%rcx,%rbx,8), %rdi
	addq	(%rax), %rdi
	callq	_readl
	movq	_PRCM_CLK_MGT_CLK38@GOTPCREL(%rip), %rdx
	movq	(%r15), %rcx
	testl	%eax, (%rdx)
	je	LBB0_3
## %bb.1:
	cmpq	$0, 8(%rcx,%rbx,8)
	je	LBB0_18
## %bb.2:
	movq	_PRCM_CLK_MGT_CLK38DIV@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	setne	%cl
	shrq	%cl, %r12
	jmp	LBB0_18
LBB0_3:
	movl	(%rcx,%rbx,8), %r15d
	orl	%eax, %r15d
	movq	_PRCM_CLK_MGT_CLKPLLSW_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%r15d, %eax
	movq	_PRCM_CLK_MGT_CLKPLLSW_SOC0@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %eax
	jne	LBB0_5
## %bb.4:
	movq	_PRCM_PLLSOC0_FREQ@GOTPCREL(%rip), %rax
	jmp	LBB0_9
LBB0_5:
	movq	_PRCM_CLK_MGT_CLKPLLSW_SOC1@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %eax
	jne	LBB0_7
## %bb.6:
	movq	_PRCM_PLLSOC1_FREQ@GOTPCREL(%rip), %rax
	jmp	LBB0_9
LBB0_7:
	movq	_PRCM_CLK_MGT_CLKPLLSW_DDR@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %eax
	jne	LBB0_17
## %bb.8:
	movq	_PRCM_PLLDDR_FREQ@GOTPCREL(%rip), %rax
LBB0_9:
	movl	(%rax), %edi
	movl	4(%rcx,%rbx,8), %edx
	movq	%r12, %rsi
	callq	_pll_rate
	movq	_PRCMU_SGACLK@GOTPCREL(%rip), %rcx
	cmpq	%r14, (%rcx)
	jne	LBB0_12
## %bb.10:
	movq	_PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_12
## %bb.11:
	addq	%rax, %rax
	leaq	(%rax,%rax,4), %r12
	movq	%r12, %rdi
	movl	$25, %esi
	callq	_do_div
	jmp	LBB0_18
LBB0_12:
	movslq	%r15d, %rdx
	movq	_PRCM_CLK_MGT_CLKPLLDIV_MASK@GOTPCREL(%rip), %rcx
	movslq	(%rcx), %rcx
	andq	%rdx, %rcx
	testl	%ecx, %ecx
	je	LBB0_17
## %bb.13:
	movq	%rax, %rdx
	orq	%rcx, %rdx
	shrq	$32, %rdx
	je	LBB0_16
## %bb.14:
	xorl	%edx, %edx
	divq	%rcx
	movq	%rax, %r12
	jmp	LBB0_18
LBB0_17:
	xorl	%r12d, %r12d
	jmp	LBB0_18
LBB0_16:
                                        ## kill: def $eax killed $eax killed $rax
	xorl	%edx, %edx
	divl	%ecx
	movl	%eax, %r12d
LBB0_18:
	movq	%r12, %rax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_ROOT_CLOCK_RATE,8,3            ## @ROOT_CLOCK_RATE
	.comm	_prcmu_base,8,3                 ## @prcmu_base
	.comm	_clk_mgt,8,3                    ## @clk_mgt
	.comm	_PRCM_CLK_MGT_CLK38,4,2         ## @PRCM_CLK_MGT_CLK38
	.comm	_PRCM_CLK_MGT_CLK38DIV,4,2      ## @PRCM_CLK_MGT_CLK38DIV
	.comm	_PRCM_CLK_MGT_CLKPLLSW_MASK,4,2 ## @PRCM_CLK_MGT_CLKPLLSW_MASK
	.comm	_PRCM_CLK_MGT_CLKPLLSW_SOC0,4,2 ## @PRCM_CLK_MGT_CLKPLLSW_SOC0
	.comm	_PRCM_PLLSOC0_FREQ,4,2          ## @PRCM_PLLSOC0_FREQ
	.comm	_PRCM_CLK_MGT_CLKPLLSW_SOC1,4,2 ## @PRCM_CLK_MGT_CLKPLLSW_SOC1
	.comm	_PRCM_PLLSOC1_FREQ,4,2          ## @PRCM_PLLSOC1_FREQ
	.comm	_PRCM_CLK_MGT_CLKPLLSW_DDR,4,2  ## @PRCM_CLK_MGT_CLKPLLSW_DDR
	.comm	_PRCM_PLLDDR_FREQ,4,2           ## @PRCM_PLLDDR_FREQ
	.comm	_PRCMU_SGACLK,8,3               ## @PRCMU_SGACLK
	.comm	_PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN,4,2 ## @PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN
	.comm	_PRCM_CLK_MGT_CLKPLLDIV_MASK,4,2 ## @PRCM_CLK_MGT_CLKPLLDIV_MASK
	.no_dead_strip	_clock_rate
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function clock_rate
_clock_rate:                            ; @clock_rate
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x0
Lloh0:
	adrp	x8, _ROOT_CLOCK_RATE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _ROOT_CLOCK_RATE@GOTPAGEOFF]
Lloh2:
	ldr	x19, [x8]
Lloh3:
	adrp	x8, _prcmu_base@GOTPAGE
Lloh4:
	ldr	x8, [x8, _prcmu_base@GOTPAGEOFF]
Lloh5:
	adrp	x21, _clk_mgt@GOTPAGE
Lloh6:
	ldr	x21, [x21, _clk_mgt@GOTPAGEOFF]
Lloh7:
	ldr	x8, [x8]
	ldr	x9, [x21]
	mov	w10, #24
	madd	x9, x0, x10, x9
	ldr	x9, [x9, #16]
	add	x0, x9, x8
	bl	_readl
Lloh8:
	adrp	x8, _PRCM_CLK_MGT_CLK38@GOTPAGE
Lloh9:
	ldr	x8, [x8, _PRCM_CLK_MGT_CLK38@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x8]
	ldr	x8, [x21]
	tst	w9, w0
	b.eq	LBB0_3
; %bb.1:
	mov	w9, #24
	madd	x8, x20, x9, x8
	ldr	x8, [x8, #8]
	cbz	x8, LBB0_15
; %bb.2:
Lloh11:
	adrp	x8, _PRCM_CLK_MGT_CLK38DIV@GOTPAGE
Lloh12:
	ldr	x8, [x8, _PRCM_CLK_MGT_CLK38DIV@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
	tst	w8, w0
	cset	w8, ne
	lsr	x19, x19, x8
	b	LBB0_15
LBB0_3:
	mov	w9, #24
	mul	x9, x20, x9
	ldr	w9, [x8, x9]
	orr	w21, w9, w0
Lloh14:
	adrp	x9, _PRCM_CLK_MGT_CLKPLLSW_MASK@GOTPAGE
Lloh15:
	ldr	x9, [x9, _PRCM_CLK_MGT_CLKPLLSW_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
	and	w9, w21, w9
Lloh17:
	adrp	x10, _PRCM_CLK_MGT_CLKPLLSW_SOC0@GOTPAGE
Lloh18:
	ldr	x10, [x10, _PRCM_CLK_MGT_CLKPLLSW_SOC0@GOTPAGEOFF]
Lloh19:
	ldr	w10, [x10]
	cmp	w9, w10
	b.ne	LBB0_5
; %bb.4:
Lloh20:
	adrp	x9, _PRCM_PLLSOC0_FREQ@GOTPAGE
Lloh21:
	ldr	x9, [x9, _PRCM_PLLSOC0_FREQ@GOTPAGEOFF]
	b	LBB0_9
LBB0_5:
Lloh22:
	adrp	x10, _PRCM_CLK_MGT_CLKPLLSW_SOC1@GOTPAGE
Lloh23:
	ldr	x10, [x10, _PRCM_CLK_MGT_CLKPLLSW_SOC1@GOTPAGEOFF]
Lloh24:
	ldr	w10, [x10]
	cmp	w9, w10
	b.ne	LBB0_7
; %bb.6:
Lloh25:
	adrp	x9, _PRCM_PLLSOC1_FREQ@GOTPAGE
Lloh26:
	ldr	x9, [x9, _PRCM_PLLSOC1_FREQ@GOTPAGEOFF]
	b	LBB0_9
LBB0_7:
Lloh27:
	adrp	x10, _PRCM_CLK_MGT_CLKPLLSW_DDR@GOTPAGE
Lloh28:
	ldr	x10, [x10, _PRCM_CLK_MGT_CLKPLLSW_DDR@GOTPAGEOFF]
Lloh29:
	ldr	w10, [x10]
	cmp	w9, w10
	b.ne	LBB0_14
; %bb.8:
Lloh30:
	adrp	x9, _PRCM_PLLDDR_FREQ@GOTPAGE
Lloh31:
	ldr	x9, [x9, _PRCM_PLLDDR_FREQ@GOTPAGEOFF]
LBB0_9:
	ldr	w0, [x9]
	mov	w9, #24
	madd	x8, x20, x9, x8
	ldr	w2, [x8, #4]
	mov	x1, x19
	bl	_pll_rate
Lloh32:
	adrp	x8, _PRCMU_SGACLK@GOTPAGE
Lloh33:
	ldr	x8, [x8, _PRCMU_SGACLK@GOTPAGEOFF]
Lloh34:
	ldr	x8, [x8]
	cmp	x8, x20
	b.ne	LBB0_12
; %bb.10:
Lloh35:
	adrp	x8, _PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN@GOTPAGE
Lloh36:
	ldr	x8, [x8, _PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN@GOTPAGEOFF]
Lloh37:
	ldr	w8, [x8]
	tst	w8, w21
	b.eq	LBB0_12
; %bb.11:
	add	x8, x0, x0, lsl #2
	lsl	x19, x8, #1
	mov	x0, x19
	mov	w1, #25
	bl	_do_div
	b	LBB0_15
LBB0_12:
	sxtw	x8, w21
Lloh38:
	adrp	x9, _PRCM_CLK_MGT_CLKPLLDIV_MASK@GOTPAGE
Lloh39:
	ldr	x9, [x9, _PRCM_CLK_MGT_CLKPLLDIV_MASK@GOTPAGEOFF]
Lloh40:
	ldrsw	x9, [x9]
	and	x8, x9, x8
	cbz	w8, LBB0_14
; %bb.13:
	udiv	x19, x0, x8
	b	LBB0_15
LBB0_14:
	mov	x19, #0
LBB0_15:
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh7
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.cfi_endproc
                                        ; -- End function
	.comm	_ROOT_CLOCK_RATE,8,3            ; @ROOT_CLOCK_RATE
	.comm	_prcmu_base,8,3                 ; @prcmu_base
	.comm	_clk_mgt,8,3                    ; @clk_mgt
	.comm	_PRCM_CLK_MGT_CLK38,4,2         ; @PRCM_CLK_MGT_CLK38
	.comm	_PRCM_CLK_MGT_CLK38DIV,4,2      ; @PRCM_CLK_MGT_CLK38DIV
	.comm	_PRCM_CLK_MGT_CLKPLLSW_MASK,4,2 ; @PRCM_CLK_MGT_CLKPLLSW_MASK
	.comm	_PRCM_CLK_MGT_CLKPLLSW_SOC0,4,2 ; @PRCM_CLK_MGT_CLKPLLSW_SOC0
	.comm	_PRCM_PLLSOC0_FREQ,4,2          ; @PRCM_PLLSOC0_FREQ
	.comm	_PRCM_CLK_MGT_CLKPLLSW_SOC1,4,2 ; @PRCM_CLK_MGT_CLKPLLSW_SOC1
	.comm	_PRCM_PLLSOC1_FREQ,4,2          ; @PRCM_PLLSOC1_FREQ
	.comm	_PRCM_CLK_MGT_CLKPLLSW_DDR,4,2  ; @PRCM_CLK_MGT_CLKPLLSW_DDR
	.comm	_PRCM_PLLDDR_FREQ,4,2           ; @PRCM_PLLDDR_FREQ
	.comm	_PRCMU_SGACLK,8,3               ; @PRCMU_SGACLK
	.comm	_PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN,4,2 ; @PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN
	.comm	_PRCM_CLK_MGT_CLKPLLDIV_MASK,4,2 ; @PRCM_CLK_MGT_CLKPLLDIV_MASK
	.no_dead_strip	_clock_rate
.subsections_via_symbols
