	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ispif_config_irq
_ispif_config_irq:                      ## @ispif_config_irq
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
                                        ## kill: def $esi killed $esi def $rsi
	movq	%rdi, %r15
	addl	$-128, %esi
	cmpl	$4, %esi
	ja	LBB0_16
## %bb.1:
	movl	%ecx, %ebx
	movl	%edx, %r14d
	leaq	LJTI0_0(%rip), %rax
	movslq	(%rax,%rsi,4), %rcx
	addq	%rax, %rcx
	jmpq	*%rcx
LBB0_12:
	movq	(%r15), %r12
	movl	%r14d, %edi
	callq	_ISPIF_VFE_m_IRQ_MASK_2
	addq	%rax, %r12
	movq	%r12, %rdi
	callq	_readl_relaxed
	movq	_ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movq	_ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE@GOTPCREL(%rip), %r13
	testl	%ebx, %ebx
	je	LBB0_14
## %bb.13:
	movl	(%r13), %ebx
LBB0_14:
	orl	%ecx, %ebx
	movq	(%r15), %r12
	movl	%r14d, %edi
	callq	_ISPIF_VFE_m_IRQ_MASK_2
	addq	%rax, %r12
	movl	%ebx, %edi
	movq	%r12, %rsi
	callq	_writel_relaxed
	movl	(%r13), %r12d
	movq	(%r15), %rbx
	movl	%r14d, %edi
	callq	_ISPIF_VFE_m_IRQ_CLEAR_2
	jmp	LBB0_15
LBB0_6:
	movq	(%r15), %r12
	movl	%r14d, %edi
	callq	_ISPIF_VFE_m_IRQ_MASK_0
	addq	%rax, %r12
	movq	%r12, %rdi
	callq	_readl_relaxed
	movq	_ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movq	_ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE@GOTPCREL(%rip), %r13
	testl	%ebx, %ebx
	jne	LBB0_4
	jmp	LBB0_5
LBB0_7:
	movq	(%r15), %r12
	movl	%r14d, %edi
	callq	_ISPIF_VFE_m_IRQ_MASK_1
	addq	%rax, %r12
	movq	%r12, %rdi
	callq	_readl_relaxed
	movq	_ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movq	_ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE@GOTPCREL(%rip), %r13
	testl	%ebx, %ebx
	je	LBB0_10
LBB0_9:
	movl	(%r13), %ebx
LBB0_10:
	orl	%ecx, %ebx
	movq	(%r15), %r12
	movl	%r14d, %edi
	callq	_ISPIF_VFE_m_IRQ_MASK_1
	addq	%rax, %r12
	movl	%ebx, %edi
	movq	%r12, %rsi
	callq	_writel_relaxed
	movl	(%r13), %r12d
	movq	(%r15), %rbx
	movl	%r14d, %edi
	callq	_ISPIF_VFE_m_IRQ_CLEAR_1
	jmp	LBB0_15
LBB0_2:
	movq	(%r15), %r12
	movl	%r14d, %edi
	callq	_ISPIF_VFE_m_IRQ_MASK_0
	addq	%rax, %r12
	movq	%r12, %rdi
	callq	_readl_relaxed
	movq	_ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movq	_ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE@GOTPCREL(%rip), %r13
	testl	%ebx, %ebx
	je	LBB0_5
LBB0_4:
	movl	(%r13), %ebx
LBB0_5:
	orl	%ecx, %ebx
	movq	(%r15), %r12
	movl	%r14d, %edi
	callq	_ISPIF_VFE_m_IRQ_MASK_0
	addq	%rax, %r12
	movl	%ebx, %edi
	movq	%r12, %rsi
	callq	_writel_relaxed
	movl	(%r13), %r12d
	movq	(%r15), %rbx
	movl	%r14d, %edi
	callq	_ISPIF_VFE_m_IRQ_CLEAR_0
LBB0_15:
	addq	%rax, %rbx
	movl	%r12d, %edi
	movq	%rbx, %rsi
	callq	_writel_relaxed
LBB0_16:
	movq	_ISPIF_IRQ_GLOBAL_CLEAR_CMD@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%r15), %rsi
	movl	$1, %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_writel                         ## TAILCALL
LBB0_11:
	movq	(%r15), %r12
	movl	%r14d, %edi
	callq	_ISPIF_VFE_m_IRQ_MASK_1
	addq	%rax, %r12
	movq	%r12, %rdi
	callq	_readl_relaxed
	movq	_ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movq	_ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE@GOTPCREL(%rip), %r13
	testl	%ebx, %ebx
	jne	LBB0_9
	jmp	LBB0_10
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_12, LBB0_12-LJTI0_0
.set L0_0_set_11, LBB0_11-LJTI0_0
.set L0_0_set_6, LBB0_6-LJTI0_0
.set L0_0_set_7, LBB0_7-LJTI0_0
.set L0_0_set_2, LBB0_2-LJTI0_0
LJTI0_0:
	.long	L0_0_set_12
	.long	L0_0_set_11
	.long	L0_0_set_6
	.long	L0_0_set_7
	.long	L0_0_set_2
	.end_data_region
                                        ## -- End function
	.comm	_ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK,4,2 ## @ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK
	.comm	_ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE,4,2 ## @ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE
	.comm	_ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK,4,2 ## @ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK
	.comm	_ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE,4,2 ## @ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE
	.comm	_ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK,4,2 ## @ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK
	.comm	_ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE,4,2 ## @ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE
	.comm	_ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK,4,2 ## @ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK
	.comm	_ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE,4,2 ## @ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE
	.comm	_ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK,4,2 ## @ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK
	.comm	_ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE,4,2 ## @ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE
	.comm	_ISPIF_IRQ_GLOBAL_CLEAR_CMD,8,3 ## @ISPIF_IRQ_GLOBAL_CLEAR_CMD
	.no_dead_strip	_ispif_config_irq
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ispif_config_irq
_ispif_config_irq:                      ; @ispif_config_irq
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	sub	w8, w1, #128
	cmp	w8, #4
	b.hi	LBB0_10
; %bb.1:
	mov	x21, x3
	mov	x20, x2
Lloh0:
	adrp	x9, lJTI0_0@PAGE
Lloh1:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_2
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_2:
	ldr	x22, [x19]
	mov	x0, x20
	bl	_ISPIF_VFE_m_IRQ_MASK_2
	add	x0, x0, x22
	bl	_readl_relaxed
Lloh2:
	adrp	x8, _ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
Lloh5:
	adrp	x22, _ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE@GOTPAGE
Lloh6:
	ldr	x22, [x22, _ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE@GOTPAGEOFF]
	bic	w8, w0, w8
	ldr	w9, [x22]
	cmp	w21, #0
	csel	w9, wzr, w9, eq
	orr	w21, w9, w8
	ldr	x23, [x19]
	mov	x0, x20
	bl	_ISPIF_VFE_m_IRQ_MASK_2
	add	x1, x0, x23
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x22]
	ldr	x22, [x19]
	mov	x0, x20
	bl	_ISPIF_VFE_m_IRQ_CLEAR_2
	b	LBB0_9
LBB0_3:
	ldr	x22, [x19]
	mov	x0, x20
	bl	_ISPIF_VFE_m_IRQ_MASK_1
	add	x0, x0, x22
	bl	_readl_relaxed
Lloh7:
	adrp	x8, _ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK@GOTPAGE
Lloh8:
	ldr	x8, [x8, _ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
Lloh10:
	adrp	x22, _ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE@GOTPAGE
Lloh11:
	ldr	x22, [x22, _ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE@GOTPAGEOFF]
	b	LBB0_6
LBB0_4:
	ldr	x22, [x19]
	mov	x0, x20
	bl	_ISPIF_VFE_m_IRQ_MASK_0
	add	x0, x0, x22
	bl	_readl_relaxed
Lloh12:
	adrp	x8, _ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK@GOTPAGE
Lloh13:
	ldr	x8, [x8, _ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
Lloh15:
	adrp	x22, _ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE@GOTPAGE
Lloh16:
	ldr	x22, [x22, _ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE@GOTPAGEOFF]
	b	LBB0_8
LBB0_5:
	ldr	x22, [x19]
	mov	x0, x20
	bl	_ISPIF_VFE_m_IRQ_MASK_1
	add	x0, x0, x22
	bl	_readl_relaxed
Lloh17:
	adrp	x8, _ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK@GOTPAGE
Lloh18:
	ldr	x8, [x8, _ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
Lloh20:
	adrp	x22, _ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE@GOTPAGE
Lloh21:
	ldr	x22, [x22, _ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE@GOTPAGEOFF]
LBB0_6:
	bic	w8, w0, w8
	ldr	w9, [x22]
	cmp	w21, #0
	csel	w9, wzr, w9, eq
	orr	w21, w9, w8
	ldr	x23, [x19]
	mov	x0, x20
	bl	_ISPIF_VFE_m_IRQ_MASK_1
	add	x1, x0, x23
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x22]
	ldr	x22, [x19]
	mov	x0, x20
	bl	_ISPIF_VFE_m_IRQ_CLEAR_1
	b	LBB0_9
LBB0_7:
	ldr	x22, [x19]
	mov	x0, x20
	bl	_ISPIF_VFE_m_IRQ_MASK_0
	add	x0, x0, x22
	bl	_readl_relaxed
Lloh22:
	adrp	x8, _ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK@GOTPAGE
Lloh23:
	ldr	x8, [x8, _ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
Lloh25:
	adrp	x22, _ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE@GOTPAGE
Lloh26:
	ldr	x22, [x22, _ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE@GOTPAGEOFF]
LBB0_8:
	bic	w8, w0, w8
	ldr	w9, [x22]
	cmp	w21, #0
	csel	w9, wzr, w9, eq
	orr	w21, w9, w8
	ldr	x23, [x19]
	mov	x0, x20
	bl	_ISPIF_VFE_m_IRQ_MASK_0
	add	x1, x0, x23
	mov	x0, x21
	bl	_writel_relaxed
	ldr	w21, [x22]
	ldr	x22, [x19]
	mov	x0, x20
	bl	_ISPIF_VFE_m_IRQ_CLEAR_0
LBB0_9:
	add	x1, x0, x22
	mov	x0, x21
	bl	_writel_relaxed
LBB0_10:
	ldr	x8, [x19]
Lloh27:
	adrp	x9, _ISPIF_IRQ_GLOBAL_CLEAR_CMD@GOTPAGE
Lloh28:
	ldr	x9, [x9, _ISPIF_IRQ_GLOBAL_CLEAR_CMD@GOTPAGEOFF]
Lloh29:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #1
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_writel
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_3-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_7-LBB0_2)>>2
                                        ; -- End function
	.comm	_ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK,4,2 ; @ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK
	.comm	_ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE,4,2 ; @ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE
	.comm	_ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK,4,2 ; @ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK
	.comm	_ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE,4,2 ; @ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE
	.comm	_ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK,4,2 ; @ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK
	.comm	_ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE,4,2 ; @ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE
	.comm	_ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK,4,2 ; @ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK
	.comm	_ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE,4,2 ; @ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE
	.comm	_ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK,4,2 ; @ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK
	.comm	_ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE,4,2 ; @ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE
	.comm	_ISPIF_IRQ_GLOBAL_CLEAR_CMD,8,3 ; @ISPIF_IRQ_GLOBAL_CLEAR_CMD
	.no_dead_strip	_ispif_config_irq
.subsections_via_symbols
