	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function bnx2x_enable_blocks_attention
_bnx2x_enable_blocks_attention:         ## @bnx2x_enable_blocks_attention
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	_PXP_REG_PXP_INT_MASK_0@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	xorl	%r14d, %r14d
	xorl	%edx, %edx
	callq	_REG_WR
	movq	%r15, %rdi
	callq	_CHIP_IS_E1x
	xorl	%edx, %edx
	testl	%eax, %eax
	sete	%dl
	movq	_PXP_REG_PXP_INT_MASK_1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	shll	$6, %edx
	movq	%r15, %rdi
	callq	_REG_WR
	movq	_DORQ_REG_DORQ_INT_MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_CFC_REG_CFC_INT_MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_BRB1_REG_BRB1_INT_MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	movl	$64512, %edx                    ## imm = 0xFC00
	callq	_REG_WR
	movq	_QM_REG_QM_INT_MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_TM_REG_TM_INT_MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_XSDM_REG_XSDM_INT_MASK_0@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_XSDM_REG_XSDM_INT_MASK_1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_XCM_REG_XCM_INT_MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_USDM_REG_USDM_INT_MASK_0@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_USDM_REG_USDM_INT_MASK_1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_UCM_REG_UCM_INT_MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_GRCBASE_UPB@GOTPCREL(%rip), %rax
	movq	_PB_REG_PB_INT_MASK@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rsi
	addq	(%rax), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_CSDM_REG_CSDM_INT_MASK_0@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_CSDM_REG_CSDM_INT_MASK_1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_CCM_REG_CCM_INT_MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT@GOTPCREL(%rip), %rax
	movq	_PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	_PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	%r15, %rdi
	callq	_CHIP_IS_E1x
	movq	_PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED@GOTPCREL(%rip), %rcx
	movq	_PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	testl	%eax, %eax
	cmovnel	%r14d, %edx
	orl	%ebx, %edx
	movq	_PXP2_REG_PXP2_INT_MASK_0@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	callq	_REG_WR
	movq	_TSDM_REG_TSDM_INT_MASK_0@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_TSDM_REG_TSDM_INT_MASK_1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_TCM_REG_TCM_INT_MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	%r15, %rdi
	callq	_CHIP_IS_E1x
	testl	%eax, %eax
	jne	LBB0_2
## %bb.1:
	movq	_TSEM_REG_TSEM_INT_MASK_1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	movl	$2047, %edx                     ## imm = 0x7FF
	callq	_REG_WR
LBB0_2:
	movq	_CDU_REG_CDU_INT_MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_DMAE_REG_DMAE_INT_MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_REG_WR
	movq	_PBF_REG_PBF_INT_MASK@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r15, %rdi
	movl	$24, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_REG_WR                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PXP_REG_PXP_INT_MASK_0,8,3     ## @PXP_REG_PXP_INT_MASK_0
	.comm	_PXP_REG_PXP_INT_MASK_1,8,3     ## @PXP_REG_PXP_INT_MASK_1
	.comm	_DORQ_REG_DORQ_INT_MASK,8,3     ## @DORQ_REG_DORQ_INT_MASK
	.comm	_CFC_REG_CFC_INT_MASK,8,3       ## @CFC_REG_CFC_INT_MASK
	.comm	_BRB1_REG_BRB1_INT_MASK,8,3     ## @BRB1_REG_BRB1_INT_MASK
	.comm	_QM_REG_QM_INT_MASK,8,3         ## @QM_REG_QM_INT_MASK
	.comm	_TM_REG_TM_INT_MASK,8,3         ## @TM_REG_TM_INT_MASK
	.comm	_XSDM_REG_XSDM_INT_MASK_0,8,3   ## @XSDM_REG_XSDM_INT_MASK_0
	.comm	_XSDM_REG_XSDM_INT_MASK_1,8,3   ## @XSDM_REG_XSDM_INT_MASK_1
	.comm	_XCM_REG_XCM_INT_MASK,8,3       ## @XCM_REG_XCM_INT_MASK
	.comm	_USDM_REG_USDM_INT_MASK_0,8,3   ## @USDM_REG_USDM_INT_MASK_0
	.comm	_USDM_REG_USDM_INT_MASK_1,8,3   ## @USDM_REG_USDM_INT_MASK_1
	.comm	_UCM_REG_UCM_INT_MASK,8,3       ## @UCM_REG_UCM_INT_MASK
	.comm	_GRCBASE_UPB,8,3                ## @GRCBASE_UPB
	.comm	_PB_REG_PB_INT_MASK,8,3         ## @PB_REG_PB_INT_MASK
	.comm	_CSDM_REG_CSDM_INT_MASK_0,8,3   ## @CSDM_REG_CSDM_INT_MASK_0
	.comm	_CSDM_REG_CSDM_INT_MASK_1,8,3   ## @CSDM_REG_CSDM_INT_MASK_1
	.comm	_CCM_REG_CCM_INT_MASK,8,3       ## @CCM_REG_CCM_INT_MASK
	.comm	_PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT,4,2 ## @PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
	.comm	_PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF,4,2 ## @PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
	.comm	_PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN,4,2 ## @PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
	.comm	_PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED,4,2 ## @PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
	.comm	_PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED,4,2 ## @PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED
	.comm	_PXP2_REG_PXP2_INT_MASK_0,8,3   ## @PXP2_REG_PXP2_INT_MASK_0
	.comm	_TSDM_REG_TSDM_INT_MASK_0,8,3   ## @TSDM_REG_TSDM_INT_MASK_0
	.comm	_TSDM_REG_TSDM_INT_MASK_1,8,3   ## @TSDM_REG_TSDM_INT_MASK_1
	.comm	_TCM_REG_TCM_INT_MASK,8,3       ## @TCM_REG_TCM_INT_MASK
	.comm	_TSEM_REG_TSEM_INT_MASK_1,8,3   ## @TSEM_REG_TSEM_INT_MASK_1
	.comm	_CDU_REG_CDU_INT_MASK,8,3       ## @CDU_REG_CDU_INT_MASK
	.comm	_DMAE_REG_DMAE_INT_MASK,8,3     ## @DMAE_REG_DMAE_INT_MASK
	.comm	_PBF_REG_PBF_INT_MASK,8,3       ## @PBF_REG_PBF_INT_MASK
	.no_dead_strip	_bnx2x_enable_blocks_attention
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function bnx2x_enable_blocks_attention
_bnx2x_enable_blocks_attention:         ; @bnx2x_enable_blocks_attention
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
Lloh0:
	adrp	x8, _PXP_REG_PXP_INT_MASK_0@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PXP_REG_PXP_INT_MASK_0@GOTPAGEOFF]
Lloh2:
	ldr	x1, [x8]
	mov	w2, #0
	bl	_REG_WR
	mov	x0, x19
	bl	_CHIP_IS_E1x
	cmp	w0, #0
	cset	w8, eq
Lloh3:
	adrp	x9, _PXP_REG_PXP_INT_MASK_1@GOTPAGE
Lloh4:
	ldr	x9, [x9, _PXP_REG_PXP_INT_MASK_1@GOTPAGEOFF]
Lloh5:
	ldr	x1, [x9]
	lsl	w2, w8, #6
	mov	x0, x19
	bl	_REG_WR
Lloh6:
	adrp	x8, _DORQ_REG_DORQ_INT_MASK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _DORQ_REG_DORQ_INT_MASK@GOTPAGEOFF]
Lloh8:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh9:
	adrp	x8, _CFC_REG_CFC_INT_MASK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _CFC_REG_CFC_INT_MASK@GOTPAGEOFF]
Lloh11:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh12:
	adrp	x8, _BRB1_REG_BRB1_INT_MASK@GOTPAGE
Lloh13:
	ldr	x8, [x8, _BRB1_REG_BRB1_INT_MASK@GOTPAGEOFF]
Lloh14:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #64512
	bl	_REG_WR
Lloh15:
	adrp	x8, _QM_REG_QM_INT_MASK@GOTPAGE
Lloh16:
	ldr	x8, [x8, _QM_REG_QM_INT_MASK@GOTPAGEOFF]
Lloh17:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh18:
	adrp	x8, _TM_REG_TM_INT_MASK@GOTPAGE
Lloh19:
	ldr	x8, [x8, _TM_REG_TM_INT_MASK@GOTPAGEOFF]
Lloh20:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh21:
	adrp	x8, _XSDM_REG_XSDM_INT_MASK_0@GOTPAGE
Lloh22:
	ldr	x8, [x8, _XSDM_REG_XSDM_INT_MASK_0@GOTPAGEOFF]
Lloh23:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh24:
	adrp	x8, _XSDM_REG_XSDM_INT_MASK_1@GOTPAGE
Lloh25:
	ldr	x8, [x8, _XSDM_REG_XSDM_INT_MASK_1@GOTPAGEOFF]
Lloh26:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh27:
	adrp	x8, _XCM_REG_XCM_INT_MASK@GOTPAGE
Lloh28:
	ldr	x8, [x8, _XCM_REG_XCM_INT_MASK@GOTPAGEOFF]
Lloh29:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh30:
	adrp	x8, _USDM_REG_USDM_INT_MASK_0@GOTPAGE
Lloh31:
	ldr	x8, [x8, _USDM_REG_USDM_INT_MASK_0@GOTPAGEOFF]
Lloh32:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh33:
	adrp	x8, _USDM_REG_USDM_INT_MASK_1@GOTPAGE
Lloh34:
	ldr	x8, [x8, _USDM_REG_USDM_INT_MASK_1@GOTPAGEOFF]
Lloh35:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh36:
	adrp	x8, _UCM_REG_UCM_INT_MASK@GOTPAGE
Lloh37:
	ldr	x8, [x8, _UCM_REG_UCM_INT_MASK@GOTPAGEOFF]
Lloh38:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh39:
	adrp	x8, _GRCBASE_UPB@GOTPAGE
Lloh40:
	ldr	x8, [x8, _GRCBASE_UPB@GOTPAGEOFF]
Lloh41:
	ldr	x8, [x8]
Lloh42:
	adrp	x9, _PB_REG_PB_INT_MASK@GOTPAGE
Lloh43:
	ldr	x9, [x9, _PB_REG_PB_INT_MASK@GOTPAGEOFF]
Lloh44:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh45:
	adrp	x8, _CSDM_REG_CSDM_INT_MASK_0@GOTPAGE
Lloh46:
	ldr	x8, [x8, _CSDM_REG_CSDM_INT_MASK_0@GOTPAGEOFF]
Lloh47:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh48:
	adrp	x8, _CSDM_REG_CSDM_INT_MASK_1@GOTPAGE
Lloh49:
	ldr	x8, [x8, _CSDM_REG_CSDM_INT_MASK_1@GOTPAGEOFF]
Lloh50:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh51:
	adrp	x8, _CCM_REG_CCM_INT_MASK@GOTPAGE
Lloh52:
	ldr	x8, [x8, _CCM_REG_CCM_INT_MASK@GOTPAGEOFF]
Lloh53:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh54:
	adrp	x8, _PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT@GOTPAGE
Lloh55:
	ldr	x8, [x8, _PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT@GOTPAGEOFF]
Lloh56:
	ldr	w8, [x8]
Lloh57:
	adrp	x9, _PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF@GOTPAGE
Lloh58:
	ldr	x9, [x9, _PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF@GOTPAGEOFF]
Lloh59:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh60:
	adrp	x9, _PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN@GOTPAGE
Lloh61:
	ldr	x9, [x9, _PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN@GOTPAGEOFF]
Lloh62:
	ldr	w9, [x9]
	orr	w20, w8, w9
	mov	x0, x19
	bl	_CHIP_IS_E1x
Lloh63:
	adrp	x8, _PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED@GOTPAGE
Lloh64:
	ldr	x8, [x8, _PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED@GOTPAGEOFF]
Lloh65:
	ldr	w8, [x8]
Lloh66:
	adrp	x9, _PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED@GOTPAGE
Lloh67:
	ldr	x9, [x9, _PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED@GOTPAGEOFF]
Lloh68:
	ldr	w9, [x9]
	orr	w8, w9, w8
	cmp	w0, #0
	csel	w8, w8, wzr, eq
	orr	w2, w20, w8
Lloh69:
	adrp	x8, _PXP2_REG_PXP2_INT_MASK_0@GOTPAGE
Lloh70:
	ldr	x8, [x8, _PXP2_REG_PXP2_INT_MASK_0@GOTPAGEOFF]
Lloh71:
	ldr	x1, [x8]
	mov	x0, x19
	bl	_REG_WR
Lloh72:
	adrp	x8, _TSDM_REG_TSDM_INT_MASK_0@GOTPAGE
Lloh73:
	ldr	x8, [x8, _TSDM_REG_TSDM_INT_MASK_0@GOTPAGEOFF]
Lloh74:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh75:
	adrp	x8, _TSDM_REG_TSDM_INT_MASK_1@GOTPAGE
Lloh76:
	ldr	x8, [x8, _TSDM_REG_TSDM_INT_MASK_1@GOTPAGEOFF]
Lloh77:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh78:
	adrp	x8, _TCM_REG_TCM_INT_MASK@GOTPAGE
Lloh79:
	ldr	x8, [x8, _TCM_REG_TCM_INT_MASK@GOTPAGEOFF]
Lloh80:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
	mov	x0, x19
	bl	_CHIP_IS_E1x
	cbnz	w0, LBB0_2
; %bb.1:
Lloh81:
	adrp	x8, _TSEM_REG_TSEM_INT_MASK_1@GOTPAGE
Lloh82:
	ldr	x8, [x8, _TSEM_REG_TSEM_INT_MASK_1@GOTPAGEOFF]
Lloh83:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #2047
	bl	_REG_WR
LBB0_2:
Lloh84:
	adrp	x8, _CDU_REG_CDU_INT_MASK@GOTPAGE
Lloh85:
	ldr	x8, [x8, _CDU_REG_CDU_INT_MASK@GOTPAGEOFF]
Lloh86:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh87:
	adrp	x8, _DMAE_REG_DMAE_INT_MASK@GOTPAGE
Lloh88:
	ldr	x8, [x8, _DMAE_REG_DMAE_INT_MASK@GOTPAGEOFF]
Lloh89:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WR
Lloh90:
	adrp	x8, _PBF_REG_PBF_INT_MASK@GOTPAGE
Lloh91:
	ldr	x8, [x8, _PBF_REG_PBF_INT_MASK@GOTPAGEOFF]
Lloh92:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #24
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_REG_WR
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.cfi_endproc
                                        ; -- End function
	.comm	_PXP_REG_PXP_INT_MASK_0,8,3     ; @PXP_REG_PXP_INT_MASK_0
	.comm	_PXP_REG_PXP_INT_MASK_1,8,3     ; @PXP_REG_PXP_INT_MASK_1
	.comm	_DORQ_REG_DORQ_INT_MASK,8,3     ; @DORQ_REG_DORQ_INT_MASK
	.comm	_CFC_REG_CFC_INT_MASK,8,3       ; @CFC_REG_CFC_INT_MASK
	.comm	_BRB1_REG_BRB1_INT_MASK,8,3     ; @BRB1_REG_BRB1_INT_MASK
	.comm	_QM_REG_QM_INT_MASK,8,3         ; @QM_REG_QM_INT_MASK
	.comm	_TM_REG_TM_INT_MASK,8,3         ; @TM_REG_TM_INT_MASK
	.comm	_XSDM_REG_XSDM_INT_MASK_0,8,3   ; @XSDM_REG_XSDM_INT_MASK_0
	.comm	_XSDM_REG_XSDM_INT_MASK_1,8,3   ; @XSDM_REG_XSDM_INT_MASK_1
	.comm	_XCM_REG_XCM_INT_MASK,8,3       ; @XCM_REG_XCM_INT_MASK
	.comm	_USDM_REG_USDM_INT_MASK_0,8,3   ; @USDM_REG_USDM_INT_MASK_0
	.comm	_USDM_REG_USDM_INT_MASK_1,8,3   ; @USDM_REG_USDM_INT_MASK_1
	.comm	_UCM_REG_UCM_INT_MASK,8,3       ; @UCM_REG_UCM_INT_MASK
	.comm	_GRCBASE_UPB,8,3                ; @GRCBASE_UPB
	.comm	_PB_REG_PB_INT_MASK,8,3         ; @PB_REG_PB_INT_MASK
	.comm	_CSDM_REG_CSDM_INT_MASK_0,8,3   ; @CSDM_REG_CSDM_INT_MASK_0
	.comm	_CSDM_REG_CSDM_INT_MASK_1,8,3   ; @CSDM_REG_CSDM_INT_MASK_1
	.comm	_CCM_REG_CCM_INT_MASK,8,3       ; @CCM_REG_CCM_INT_MASK
	.comm	_PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT,4,2 ; @PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
	.comm	_PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF,4,2 ; @PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
	.comm	_PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN,4,2 ; @PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
	.comm	_PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED,4,2 ; @PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
	.comm	_PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED,4,2 ; @PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED
	.comm	_PXP2_REG_PXP2_INT_MASK_0,8,3   ; @PXP2_REG_PXP2_INT_MASK_0
	.comm	_TSDM_REG_TSDM_INT_MASK_0,8,3   ; @TSDM_REG_TSDM_INT_MASK_0
	.comm	_TSDM_REG_TSDM_INT_MASK_1,8,3   ; @TSDM_REG_TSDM_INT_MASK_1
	.comm	_TCM_REG_TCM_INT_MASK,8,3       ; @TCM_REG_TCM_INT_MASK
	.comm	_TSEM_REG_TSEM_INT_MASK_1,8,3   ; @TSEM_REG_TSEM_INT_MASK_1
	.comm	_CDU_REG_CDU_INT_MASK,8,3       ; @CDU_REG_CDU_INT_MASK
	.comm	_DMAE_REG_DMAE_INT_MASK,8,3     ; @DMAE_REG_DMAE_INT_MASK
	.comm	_PBF_REG_PBF_INT_MASK,8,3       ; @PBF_REG_PBF_INT_MASK
	.no_dead_strip	_bnx2x_enable_blocks_attention
.subsections_via_symbols
