	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function isc_configure
_isc_configure:                         ## @isc_configure
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	_ISC_DCFG_YMBSIZE_BEATS8@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	orl	8(%rdi), %r14d
	movq	32(%rdi), %rax
	movq	_ISC_DCFG_CMBSIZE_BEATS8@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r14d
	movq	16(%rdi), %rdx
	movl	(%rax), %ecx
	orl	(%rdx), %ecx
	movq	_ISC_PFE_CFG0_MODE_PROGRESSIVE@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_ISC_PFE_CFG0_BPS_MASK@GOTPCREL(%rip), %rax
	movq	_ISC_PFE_CFG0_HPOL_LOW@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rax), %edx
	movq	40(%rdi), %r12
	movq	_ISC_PFE_CFG0_VPOL_LOW@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	(%rdi), %r13d
	movq	_ISC_PFE_CFG0_PPOL_LOW@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	4(%rdi), %r15d
	movq	_ISC_PFE_CFG0_MODE_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_ISC_PFE_CFG0_CCIR_CRC@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_ISC_PFE_CFG0_CCIR656@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_ISC_PFE_CFG0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_regmap_update_bits
	movq	_ISC_RLP_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_ISC_RLP_CFG_MODE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r13d, %ecx
	callq	_regmap_update_bits
	movq	_ISC_DCFG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	%r14d, %edx
	callq	_regmap_write
	movq	%rbx, %rdi
	movl	%r15d, %esi
	callq	_isc_set_pipeline
	cmpq	$0, 24(%rbx)
	je	LBB0_2
## %bb.1:
	movq	16(%rbx), %rax
	movl	4(%rax), %edi
	callq	_ISC_IS_FORMAT_RAW
	movl	$1, %esi
	testq	%rax, %rax
	jne	LBB0_3
LBB0_2:
	xorl	%esi, %esi
LBB0_3:
	movq	%rbx, %rdi
	callq	_isc_set_histogram
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_isc_update_profile             ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_ISC_DCFG_YMBSIZE_BEATS8,4,2    ## @ISC_DCFG_YMBSIZE_BEATS8
	.comm	_ISC_DCFG_CMBSIZE_BEATS8,4,2    ## @ISC_DCFG_CMBSIZE_BEATS8
	.comm	_ISC_PFE_CFG0_MODE_PROGRESSIVE,4,2 ## @ISC_PFE_CFG0_MODE_PROGRESSIVE
	.comm	_ISC_PFE_CFG0_BPS_MASK,4,2      ## @ISC_PFE_CFG0_BPS_MASK
	.comm	_ISC_PFE_CFG0_HPOL_LOW,4,2      ## @ISC_PFE_CFG0_HPOL_LOW
	.comm	_ISC_PFE_CFG0_VPOL_LOW,4,2      ## @ISC_PFE_CFG0_VPOL_LOW
	.comm	_ISC_PFE_CFG0_PPOL_LOW,4,2      ## @ISC_PFE_CFG0_PPOL_LOW
	.comm	_ISC_PFE_CFG0_MODE_MASK,4,2     ## @ISC_PFE_CFG0_MODE_MASK
	.comm	_ISC_PFE_CFG0_CCIR_CRC,4,2      ## @ISC_PFE_CFG0_CCIR_CRC
	.comm	_ISC_PFE_CFG0_CCIR656,4,2       ## @ISC_PFE_CFG0_CCIR656
	.comm	_ISC_PFE_CFG0,4,2               ## @ISC_PFE_CFG0
	.comm	_ISC_RLP_CFG,4,2                ## @ISC_RLP_CFG
	.comm	_ISC_RLP_CFG_MODE_MASK,4,2      ## @ISC_RLP_CFG_MODE_MASK
	.comm	_ISC_DCFG,4,2                   ## @ISC_DCFG
	.no_dead_strip	_isc_configure
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function isc_configure
_isc_configure:                         ; @isc_configure
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldp	x8, x20, [x0, #32]
	ldr	x9, [x0, #16]
	ldr	w9, [x9]
	ldr	w10, [x0, #8]
Lloh0:
	adrp	x11, _ISC_DCFG_YMBSIZE_BEATS8@GOTPAGE
Lloh1:
	ldr	x11, [x11, _ISC_DCFG_YMBSIZE_BEATS8@GOTPAGEOFF]
Lloh2:
	ldr	w11, [x11]
	orr	w10, w11, w10
Lloh3:
	adrp	x11, _ISC_DCFG_CMBSIZE_BEATS8@GOTPAGE
Lloh4:
	ldr	x11, [x11, _ISC_DCFG_CMBSIZE_BEATS8@GOTPAGEOFF]
Lloh5:
	ldr	w11, [x11]
	orr	w21, w10, w11
Lloh6:
	adrp	x10, _ISC_PFE_CFG0_MODE_PROGRESSIVE@GOTPAGE
Lloh7:
	ldr	x10, [x10, _ISC_PFE_CFG0_MODE_PROGRESSIVE@GOTPAGEOFF]
	ldr	w8, [x8]
Lloh8:
	ldr	w10, [x10]
	orr	w8, w8, w9
	orr	w3, w8, w10
Lloh9:
	adrp	x8, _ISC_PFE_CFG0_BPS_MASK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _ISC_PFE_CFG0_BPS_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
Lloh12:
	adrp	x9, _ISC_PFE_CFG0_HPOL_LOW@GOTPAGE
Lloh13:
	ldr	x9, [x9, _ISC_PFE_CFG0_HPOL_LOW@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
Lloh15:
	adrp	x10, _ISC_PFE_CFG0_VPOL_LOW@GOTPAGE
Lloh16:
	ldr	x10, [x10, _ISC_PFE_CFG0_VPOL_LOW@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh17:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh18:
	adrp	x9, _ISC_PFE_CFG0_PPOL_LOW@GOTPAGE
Lloh19:
	ldr	x9, [x9, _ISC_PFE_CFG0_PPOL_LOW@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh21:
	adrp	x9, _ISC_PFE_CFG0_MODE_MASK@GOTPAGE
Lloh22:
	ldr	x9, [x9, _ISC_PFE_CFG0_MODE_MASK@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
Lloh24:
	adrp	x10, _ISC_PFE_CFG0_CCIR_CRC@GOTPAGE
Lloh25:
	ldr	x10, [x10, _ISC_PFE_CFG0_CCIR_CRC@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh26:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh27:
	adrp	x9, _ISC_PFE_CFG0_CCIR656@GOTPAGE
Lloh28:
	ldr	x9, [x9, _ISC_PFE_CFG0_CCIR656@GOTPAGEOFF]
	ldp	w22, w23, [x0]
Lloh29:
	ldr	w9, [x9]
	orr	w2, w8, w9
Lloh30:
	adrp	x8, _ISC_PFE_CFG0@GOTPAGE
Lloh31:
	ldr	x8, [x8, _ISC_PFE_CFG0@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_regmap_update_bits
Lloh33:
	adrp	x8, _ISC_RLP_CFG@GOTPAGE
Lloh34:
	ldr	x8, [x8, _ISC_RLP_CFG@GOTPAGEOFF]
Lloh35:
	ldr	w1, [x8]
Lloh36:
	adrp	x8, _ISC_RLP_CFG_MODE_MASK@GOTPAGE
Lloh37:
	ldr	x8, [x8, _ISC_RLP_CFG_MODE_MASK@GOTPAGEOFF]
Lloh38:
	ldr	w2, [x8]
	mov	x0, x20
	mov	x3, x22
	bl	_regmap_update_bits
Lloh39:
	adrp	x8, _ISC_DCFG@GOTPAGE
Lloh40:
	ldr	x8, [x8, _ISC_DCFG@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	mov	x0, x20
	mov	x2, x21
	bl	_regmap_write
	mov	x0, x19
	mov	x1, x23
	bl	_isc_set_pipeline
	ldr	x8, [x19, #24]
	cbz	x8, LBB0_3
; %bb.1:
	ldr	x8, [x19, #16]
	ldr	w0, [x8, #4]
	bl	_ISC_IS_FORMAT_RAW
	cbz	x0, LBB0_3
; %bb.2:
	mov	w1, #1
	b	LBB0_4
LBB0_3:
	mov	w1, #0
LBB0_4:
	mov	x0, x19
	bl	_isc_set_histogram
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_isc_update_profile
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_ISC_DCFG_YMBSIZE_BEATS8,4,2    ; @ISC_DCFG_YMBSIZE_BEATS8
	.comm	_ISC_DCFG_CMBSIZE_BEATS8,4,2    ; @ISC_DCFG_CMBSIZE_BEATS8
	.comm	_ISC_PFE_CFG0_MODE_PROGRESSIVE,4,2 ; @ISC_PFE_CFG0_MODE_PROGRESSIVE
	.comm	_ISC_PFE_CFG0_BPS_MASK,4,2      ; @ISC_PFE_CFG0_BPS_MASK
	.comm	_ISC_PFE_CFG0_HPOL_LOW,4,2      ; @ISC_PFE_CFG0_HPOL_LOW
	.comm	_ISC_PFE_CFG0_VPOL_LOW,4,2      ; @ISC_PFE_CFG0_VPOL_LOW
	.comm	_ISC_PFE_CFG0_PPOL_LOW,4,2      ; @ISC_PFE_CFG0_PPOL_LOW
	.comm	_ISC_PFE_CFG0_MODE_MASK,4,2     ; @ISC_PFE_CFG0_MODE_MASK
	.comm	_ISC_PFE_CFG0_CCIR_CRC,4,2      ; @ISC_PFE_CFG0_CCIR_CRC
	.comm	_ISC_PFE_CFG0_CCIR656,4,2       ; @ISC_PFE_CFG0_CCIR656
	.comm	_ISC_PFE_CFG0,4,2               ; @ISC_PFE_CFG0
	.comm	_ISC_RLP_CFG,4,2                ; @ISC_RLP_CFG
	.comm	_ISC_RLP_CFG_MODE_MASK,4,2      ; @ISC_RLP_CFG_MODE_MASK
	.comm	_ISC_DCFG,4,2                   ; @ISC_DCFG
	.no_dead_strip	_isc_configure
.subsections_via_symbols
