	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function goya_init_protection_bits
_goya_init_protection_bits:             ## @goya_init_protection_bits
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	movq	_mmPCI_NRTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_goya_pb_set_block
	movq	_mmPCI_RD_REGULATOR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmPCI_WR_REGULATOR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y0_X0_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y0_X0_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y0_X1_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y0_X1_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y0_X2_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y0_X2_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y0_X3_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y0_X3_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y0_X4_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y0_X4_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y1_X0_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y1_X0_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y1_X1_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y1_X1_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y1_X2_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y1_X2_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y1_X3_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y1_X3_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y1_X4_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y1_X4_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y2_X0_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y2_X0_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y2_X1_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y2_X1_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y2_X2_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y2_X2_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y2_X3_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y2_X3_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y2_X4_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y2_X4_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y3_X0_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y3_X0_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y3_X1_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y3_X1_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y3_X2_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y3_X2_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y3_X3_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y3_X3_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y3_X4_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y3_X4_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y4_X0_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y4_X0_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y4_X1_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y4_X1_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y4_X2_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y4_X2_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y4_X3_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y4_X3_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y4_X4_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y4_X4_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y5_X0_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y5_X0_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y5_X1_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y5_X1_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y5_X2_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y5_X2_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y5_X3_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y5_X3_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y5_X4_BANK_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmSRAM_Y5_X4_RTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmPCIE_WRAP_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmPCIE_CORE_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmPCIE_DB_CFG_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmPCIE_DB_CMD_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmPCIE_AUX_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmPCIE_DB_RSV_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmPCIE_PHY_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmTPC0_NRTR_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmTPC_PLL_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_goya_pb_set_block
	movq	_mmTPC_PLL_CLK_RLX_0@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %eax
	andl	$-4096, %eax                    ## imm = 0xF000
	movq	_PROT_BITS_OFFS@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edi
	addl	%edi, %eax
	andl	%ecx, %edi
	sarl	$5, %edi
	andl	$-4, %edi
	addl	%eax, %edi
	shrb	$2, %cl
	movl	$1, %esi
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %esi
	callq	_WREG32
	movq	%rbx, %rdi
	callq	_goya_init_mme_protection_bits
	movq	%rbx, %rdi
	callq	_goya_init_dma_protection_bits
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_goya_init_tpc_protection_bits  ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_mmPCI_NRTR_BASE,4,2            ## @mmPCI_NRTR_BASE
	.comm	_mmPCI_RD_REGULATOR_BASE,4,2    ## @mmPCI_RD_REGULATOR_BASE
	.comm	_mmPCI_WR_REGULATOR_BASE,4,2    ## @mmPCI_WR_REGULATOR_BASE
	.comm	_mmSRAM_Y0_X0_BANK_BASE,4,2     ## @mmSRAM_Y0_X0_BANK_BASE
	.comm	_mmSRAM_Y0_X0_RTR_BASE,4,2      ## @mmSRAM_Y0_X0_RTR_BASE
	.comm	_mmSRAM_Y0_X1_BANK_BASE,4,2     ## @mmSRAM_Y0_X1_BANK_BASE
	.comm	_mmSRAM_Y0_X1_RTR_BASE,4,2      ## @mmSRAM_Y0_X1_RTR_BASE
	.comm	_mmSRAM_Y0_X2_BANK_BASE,4,2     ## @mmSRAM_Y0_X2_BANK_BASE
	.comm	_mmSRAM_Y0_X2_RTR_BASE,4,2      ## @mmSRAM_Y0_X2_RTR_BASE
	.comm	_mmSRAM_Y0_X3_BANK_BASE,4,2     ## @mmSRAM_Y0_X3_BANK_BASE
	.comm	_mmSRAM_Y0_X3_RTR_BASE,4,2      ## @mmSRAM_Y0_X3_RTR_BASE
	.comm	_mmSRAM_Y0_X4_BANK_BASE,4,2     ## @mmSRAM_Y0_X4_BANK_BASE
	.comm	_mmSRAM_Y0_X4_RTR_BASE,4,2      ## @mmSRAM_Y0_X4_RTR_BASE
	.comm	_mmSRAM_Y1_X0_BANK_BASE,4,2     ## @mmSRAM_Y1_X0_BANK_BASE
	.comm	_mmSRAM_Y1_X0_RTR_BASE,4,2      ## @mmSRAM_Y1_X0_RTR_BASE
	.comm	_mmSRAM_Y1_X1_BANK_BASE,4,2     ## @mmSRAM_Y1_X1_BANK_BASE
	.comm	_mmSRAM_Y1_X1_RTR_BASE,4,2      ## @mmSRAM_Y1_X1_RTR_BASE
	.comm	_mmSRAM_Y1_X2_BANK_BASE,4,2     ## @mmSRAM_Y1_X2_BANK_BASE
	.comm	_mmSRAM_Y1_X2_RTR_BASE,4,2      ## @mmSRAM_Y1_X2_RTR_BASE
	.comm	_mmSRAM_Y1_X3_BANK_BASE,4,2     ## @mmSRAM_Y1_X3_BANK_BASE
	.comm	_mmSRAM_Y1_X3_RTR_BASE,4,2      ## @mmSRAM_Y1_X3_RTR_BASE
	.comm	_mmSRAM_Y1_X4_BANK_BASE,4,2     ## @mmSRAM_Y1_X4_BANK_BASE
	.comm	_mmSRAM_Y1_X4_RTR_BASE,4,2      ## @mmSRAM_Y1_X4_RTR_BASE
	.comm	_mmSRAM_Y2_X0_BANK_BASE,4,2     ## @mmSRAM_Y2_X0_BANK_BASE
	.comm	_mmSRAM_Y2_X0_RTR_BASE,4,2      ## @mmSRAM_Y2_X0_RTR_BASE
	.comm	_mmSRAM_Y2_X1_BANK_BASE,4,2     ## @mmSRAM_Y2_X1_BANK_BASE
	.comm	_mmSRAM_Y2_X1_RTR_BASE,4,2      ## @mmSRAM_Y2_X1_RTR_BASE
	.comm	_mmSRAM_Y2_X2_BANK_BASE,4,2     ## @mmSRAM_Y2_X2_BANK_BASE
	.comm	_mmSRAM_Y2_X2_RTR_BASE,4,2      ## @mmSRAM_Y2_X2_RTR_BASE
	.comm	_mmSRAM_Y2_X3_BANK_BASE,4,2     ## @mmSRAM_Y2_X3_BANK_BASE
	.comm	_mmSRAM_Y2_X3_RTR_BASE,4,2      ## @mmSRAM_Y2_X3_RTR_BASE
	.comm	_mmSRAM_Y2_X4_BANK_BASE,4,2     ## @mmSRAM_Y2_X4_BANK_BASE
	.comm	_mmSRAM_Y2_X4_RTR_BASE,4,2      ## @mmSRAM_Y2_X4_RTR_BASE
	.comm	_mmSRAM_Y3_X0_BANK_BASE,4,2     ## @mmSRAM_Y3_X0_BANK_BASE
	.comm	_mmSRAM_Y3_X0_RTR_BASE,4,2      ## @mmSRAM_Y3_X0_RTR_BASE
	.comm	_mmSRAM_Y3_X1_BANK_BASE,4,2     ## @mmSRAM_Y3_X1_BANK_BASE
	.comm	_mmSRAM_Y3_X1_RTR_BASE,4,2      ## @mmSRAM_Y3_X1_RTR_BASE
	.comm	_mmSRAM_Y3_X2_BANK_BASE,4,2     ## @mmSRAM_Y3_X2_BANK_BASE
	.comm	_mmSRAM_Y3_X2_RTR_BASE,4,2      ## @mmSRAM_Y3_X2_RTR_BASE
	.comm	_mmSRAM_Y3_X3_BANK_BASE,4,2     ## @mmSRAM_Y3_X3_BANK_BASE
	.comm	_mmSRAM_Y3_X3_RTR_BASE,4,2      ## @mmSRAM_Y3_X3_RTR_BASE
	.comm	_mmSRAM_Y3_X4_BANK_BASE,4,2     ## @mmSRAM_Y3_X4_BANK_BASE
	.comm	_mmSRAM_Y3_X4_RTR_BASE,4,2      ## @mmSRAM_Y3_X4_RTR_BASE
	.comm	_mmSRAM_Y4_X0_BANK_BASE,4,2     ## @mmSRAM_Y4_X0_BANK_BASE
	.comm	_mmSRAM_Y4_X0_RTR_BASE,4,2      ## @mmSRAM_Y4_X0_RTR_BASE
	.comm	_mmSRAM_Y4_X1_BANK_BASE,4,2     ## @mmSRAM_Y4_X1_BANK_BASE
	.comm	_mmSRAM_Y4_X1_RTR_BASE,4,2      ## @mmSRAM_Y4_X1_RTR_BASE
	.comm	_mmSRAM_Y4_X2_BANK_BASE,4,2     ## @mmSRAM_Y4_X2_BANK_BASE
	.comm	_mmSRAM_Y4_X2_RTR_BASE,4,2      ## @mmSRAM_Y4_X2_RTR_BASE
	.comm	_mmSRAM_Y4_X3_BANK_BASE,4,2     ## @mmSRAM_Y4_X3_BANK_BASE
	.comm	_mmSRAM_Y4_X3_RTR_BASE,4,2      ## @mmSRAM_Y4_X3_RTR_BASE
	.comm	_mmSRAM_Y4_X4_BANK_BASE,4,2     ## @mmSRAM_Y4_X4_BANK_BASE
	.comm	_mmSRAM_Y4_X4_RTR_BASE,4,2      ## @mmSRAM_Y4_X4_RTR_BASE
	.comm	_mmSRAM_Y5_X0_BANK_BASE,4,2     ## @mmSRAM_Y5_X0_BANK_BASE
	.comm	_mmSRAM_Y5_X0_RTR_BASE,4,2      ## @mmSRAM_Y5_X0_RTR_BASE
	.comm	_mmSRAM_Y5_X1_BANK_BASE,4,2     ## @mmSRAM_Y5_X1_BANK_BASE
	.comm	_mmSRAM_Y5_X1_RTR_BASE,4,2      ## @mmSRAM_Y5_X1_RTR_BASE
	.comm	_mmSRAM_Y5_X2_BANK_BASE,4,2     ## @mmSRAM_Y5_X2_BANK_BASE
	.comm	_mmSRAM_Y5_X2_RTR_BASE,4,2      ## @mmSRAM_Y5_X2_RTR_BASE
	.comm	_mmSRAM_Y5_X3_BANK_BASE,4,2     ## @mmSRAM_Y5_X3_BANK_BASE
	.comm	_mmSRAM_Y5_X3_RTR_BASE,4,2      ## @mmSRAM_Y5_X3_RTR_BASE
	.comm	_mmSRAM_Y5_X4_BANK_BASE,4,2     ## @mmSRAM_Y5_X4_BANK_BASE
	.comm	_mmSRAM_Y5_X4_RTR_BASE,4,2      ## @mmSRAM_Y5_X4_RTR_BASE
	.comm	_mmPCIE_WRAP_BASE,4,2           ## @mmPCIE_WRAP_BASE
	.comm	_mmPCIE_CORE_BASE,4,2           ## @mmPCIE_CORE_BASE
	.comm	_mmPCIE_DB_CFG_BASE,4,2         ## @mmPCIE_DB_CFG_BASE
	.comm	_mmPCIE_DB_CMD_BASE,4,2         ## @mmPCIE_DB_CMD_BASE
	.comm	_mmPCIE_AUX_BASE,4,2            ## @mmPCIE_AUX_BASE
	.comm	_mmPCIE_DB_RSV_BASE,4,2         ## @mmPCIE_DB_RSV_BASE
	.comm	_mmPCIE_PHY_BASE,4,2            ## @mmPCIE_PHY_BASE
	.comm	_mmTPC0_NRTR_BASE,4,2           ## @mmTPC0_NRTR_BASE
	.comm	_mmTPC_PLL_BASE,4,2             ## @mmTPC_PLL_BASE
	.comm	_mmTPC_PLL_CLK_RLX_0,4,2        ## @mmTPC_PLL_CLK_RLX_0
	.comm	_PROT_BITS_OFFS,4,2             ## @PROT_BITS_OFFS
	.no_dead_strip	_goya_init_protection_bits
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function goya_init_protection_bits
_goya_init_protection_bits:             ; @goya_init_protection_bits
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
Lloh0:
	adrp	x8, _mmPCI_NRTR_BASE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _mmPCI_NRTR_BASE@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	bl	_goya_pb_set_block
Lloh3:
	adrp	x8, _mmPCI_RD_REGULATOR_BASE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _mmPCI_RD_REGULATOR_BASE@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh6:
	adrp	x8, _mmPCI_WR_REGULATOR_BASE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _mmPCI_WR_REGULATOR_BASE@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh9:
	adrp	x8, _mmSRAM_Y0_X0_BANK_BASE@GOTPAGE
Lloh10:
	ldr	x8, [x8, _mmSRAM_Y0_X0_BANK_BASE@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh12:
	adrp	x8, _mmSRAM_Y0_X0_RTR_BASE@GOTPAGE
Lloh13:
	ldr	x8, [x8, _mmSRAM_Y0_X0_RTR_BASE@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh15:
	adrp	x8, _mmSRAM_Y0_X1_BANK_BASE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _mmSRAM_Y0_X1_BANK_BASE@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh18:
	adrp	x8, _mmSRAM_Y0_X1_RTR_BASE@GOTPAGE
Lloh19:
	ldr	x8, [x8, _mmSRAM_Y0_X1_RTR_BASE@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh21:
	adrp	x8, _mmSRAM_Y0_X2_BANK_BASE@GOTPAGE
Lloh22:
	ldr	x8, [x8, _mmSRAM_Y0_X2_BANK_BASE@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh24:
	adrp	x8, _mmSRAM_Y0_X2_RTR_BASE@GOTPAGE
Lloh25:
	ldr	x8, [x8, _mmSRAM_Y0_X2_RTR_BASE@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh27:
	adrp	x8, _mmSRAM_Y0_X3_BANK_BASE@GOTPAGE
Lloh28:
	ldr	x8, [x8, _mmSRAM_Y0_X3_BANK_BASE@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh30:
	adrp	x8, _mmSRAM_Y0_X3_RTR_BASE@GOTPAGE
Lloh31:
	ldr	x8, [x8, _mmSRAM_Y0_X3_RTR_BASE@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh33:
	adrp	x8, _mmSRAM_Y0_X4_BANK_BASE@GOTPAGE
Lloh34:
	ldr	x8, [x8, _mmSRAM_Y0_X4_BANK_BASE@GOTPAGEOFF]
Lloh35:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh36:
	adrp	x8, _mmSRAM_Y0_X4_RTR_BASE@GOTPAGE
Lloh37:
	ldr	x8, [x8, _mmSRAM_Y0_X4_RTR_BASE@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh39:
	adrp	x8, _mmSRAM_Y1_X0_BANK_BASE@GOTPAGE
Lloh40:
	ldr	x8, [x8, _mmSRAM_Y1_X0_BANK_BASE@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh42:
	adrp	x8, _mmSRAM_Y1_X0_RTR_BASE@GOTPAGE
Lloh43:
	ldr	x8, [x8, _mmSRAM_Y1_X0_RTR_BASE@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh45:
	adrp	x8, _mmSRAM_Y1_X1_BANK_BASE@GOTPAGE
Lloh46:
	ldr	x8, [x8, _mmSRAM_Y1_X1_BANK_BASE@GOTPAGEOFF]
Lloh47:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh48:
	adrp	x8, _mmSRAM_Y1_X1_RTR_BASE@GOTPAGE
Lloh49:
	ldr	x8, [x8, _mmSRAM_Y1_X1_RTR_BASE@GOTPAGEOFF]
Lloh50:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh51:
	adrp	x8, _mmSRAM_Y1_X2_BANK_BASE@GOTPAGE
Lloh52:
	ldr	x8, [x8, _mmSRAM_Y1_X2_BANK_BASE@GOTPAGEOFF]
Lloh53:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh54:
	adrp	x8, _mmSRAM_Y1_X2_RTR_BASE@GOTPAGE
Lloh55:
	ldr	x8, [x8, _mmSRAM_Y1_X2_RTR_BASE@GOTPAGEOFF]
Lloh56:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh57:
	adrp	x8, _mmSRAM_Y1_X3_BANK_BASE@GOTPAGE
Lloh58:
	ldr	x8, [x8, _mmSRAM_Y1_X3_BANK_BASE@GOTPAGEOFF]
Lloh59:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh60:
	adrp	x8, _mmSRAM_Y1_X3_RTR_BASE@GOTPAGE
Lloh61:
	ldr	x8, [x8, _mmSRAM_Y1_X3_RTR_BASE@GOTPAGEOFF]
Lloh62:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh63:
	adrp	x8, _mmSRAM_Y1_X4_BANK_BASE@GOTPAGE
Lloh64:
	ldr	x8, [x8, _mmSRAM_Y1_X4_BANK_BASE@GOTPAGEOFF]
Lloh65:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh66:
	adrp	x8, _mmSRAM_Y1_X4_RTR_BASE@GOTPAGE
Lloh67:
	ldr	x8, [x8, _mmSRAM_Y1_X4_RTR_BASE@GOTPAGEOFF]
Lloh68:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh69:
	adrp	x8, _mmSRAM_Y2_X0_BANK_BASE@GOTPAGE
Lloh70:
	ldr	x8, [x8, _mmSRAM_Y2_X0_BANK_BASE@GOTPAGEOFF]
Lloh71:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh72:
	adrp	x8, _mmSRAM_Y2_X0_RTR_BASE@GOTPAGE
Lloh73:
	ldr	x8, [x8, _mmSRAM_Y2_X0_RTR_BASE@GOTPAGEOFF]
Lloh74:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh75:
	adrp	x8, _mmSRAM_Y2_X1_BANK_BASE@GOTPAGE
Lloh76:
	ldr	x8, [x8, _mmSRAM_Y2_X1_BANK_BASE@GOTPAGEOFF]
Lloh77:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh78:
	adrp	x8, _mmSRAM_Y2_X1_RTR_BASE@GOTPAGE
Lloh79:
	ldr	x8, [x8, _mmSRAM_Y2_X1_RTR_BASE@GOTPAGEOFF]
Lloh80:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh81:
	adrp	x8, _mmSRAM_Y2_X2_BANK_BASE@GOTPAGE
Lloh82:
	ldr	x8, [x8, _mmSRAM_Y2_X2_BANK_BASE@GOTPAGEOFF]
Lloh83:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh84:
	adrp	x8, _mmSRAM_Y2_X2_RTR_BASE@GOTPAGE
Lloh85:
	ldr	x8, [x8, _mmSRAM_Y2_X2_RTR_BASE@GOTPAGEOFF]
Lloh86:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh87:
	adrp	x8, _mmSRAM_Y2_X3_BANK_BASE@GOTPAGE
Lloh88:
	ldr	x8, [x8, _mmSRAM_Y2_X3_BANK_BASE@GOTPAGEOFF]
Lloh89:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh90:
	adrp	x8, _mmSRAM_Y2_X3_RTR_BASE@GOTPAGE
Lloh91:
	ldr	x8, [x8, _mmSRAM_Y2_X3_RTR_BASE@GOTPAGEOFF]
Lloh92:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh93:
	adrp	x8, _mmSRAM_Y2_X4_BANK_BASE@GOTPAGE
Lloh94:
	ldr	x8, [x8, _mmSRAM_Y2_X4_BANK_BASE@GOTPAGEOFF]
Lloh95:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh96:
	adrp	x8, _mmSRAM_Y2_X4_RTR_BASE@GOTPAGE
Lloh97:
	ldr	x8, [x8, _mmSRAM_Y2_X4_RTR_BASE@GOTPAGEOFF]
Lloh98:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh99:
	adrp	x8, _mmSRAM_Y3_X0_BANK_BASE@GOTPAGE
Lloh100:
	ldr	x8, [x8, _mmSRAM_Y3_X0_BANK_BASE@GOTPAGEOFF]
Lloh101:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh102:
	adrp	x8, _mmSRAM_Y3_X0_RTR_BASE@GOTPAGE
Lloh103:
	ldr	x8, [x8, _mmSRAM_Y3_X0_RTR_BASE@GOTPAGEOFF]
Lloh104:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh105:
	adrp	x8, _mmSRAM_Y3_X1_BANK_BASE@GOTPAGE
Lloh106:
	ldr	x8, [x8, _mmSRAM_Y3_X1_BANK_BASE@GOTPAGEOFF]
Lloh107:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh108:
	adrp	x8, _mmSRAM_Y3_X1_RTR_BASE@GOTPAGE
Lloh109:
	ldr	x8, [x8, _mmSRAM_Y3_X1_RTR_BASE@GOTPAGEOFF]
Lloh110:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh111:
	adrp	x8, _mmSRAM_Y3_X2_BANK_BASE@GOTPAGE
Lloh112:
	ldr	x8, [x8, _mmSRAM_Y3_X2_BANK_BASE@GOTPAGEOFF]
Lloh113:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh114:
	adrp	x8, _mmSRAM_Y3_X2_RTR_BASE@GOTPAGE
Lloh115:
	ldr	x8, [x8, _mmSRAM_Y3_X2_RTR_BASE@GOTPAGEOFF]
Lloh116:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh117:
	adrp	x8, _mmSRAM_Y3_X3_BANK_BASE@GOTPAGE
Lloh118:
	ldr	x8, [x8, _mmSRAM_Y3_X3_BANK_BASE@GOTPAGEOFF]
Lloh119:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh120:
	adrp	x8, _mmSRAM_Y3_X3_RTR_BASE@GOTPAGE
Lloh121:
	ldr	x8, [x8, _mmSRAM_Y3_X3_RTR_BASE@GOTPAGEOFF]
Lloh122:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh123:
	adrp	x8, _mmSRAM_Y3_X4_BANK_BASE@GOTPAGE
Lloh124:
	ldr	x8, [x8, _mmSRAM_Y3_X4_BANK_BASE@GOTPAGEOFF]
Lloh125:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh126:
	adrp	x8, _mmSRAM_Y3_X4_RTR_BASE@GOTPAGE
Lloh127:
	ldr	x8, [x8, _mmSRAM_Y3_X4_RTR_BASE@GOTPAGEOFF]
Lloh128:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh129:
	adrp	x8, _mmSRAM_Y4_X0_BANK_BASE@GOTPAGE
Lloh130:
	ldr	x8, [x8, _mmSRAM_Y4_X0_BANK_BASE@GOTPAGEOFF]
Lloh131:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh132:
	adrp	x8, _mmSRAM_Y4_X0_RTR_BASE@GOTPAGE
Lloh133:
	ldr	x8, [x8, _mmSRAM_Y4_X0_RTR_BASE@GOTPAGEOFF]
Lloh134:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh135:
	adrp	x8, _mmSRAM_Y4_X1_BANK_BASE@GOTPAGE
Lloh136:
	ldr	x8, [x8, _mmSRAM_Y4_X1_BANK_BASE@GOTPAGEOFF]
Lloh137:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh138:
	adrp	x8, _mmSRAM_Y4_X1_RTR_BASE@GOTPAGE
Lloh139:
	ldr	x8, [x8, _mmSRAM_Y4_X1_RTR_BASE@GOTPAGEOFF]
Lloh140:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh141:
	adrp	x8, _mmSRAM_Y4_X2_BANK_BASE@GOTPAGE
Lloh142:
	ldr	x8, [x8, _mmSRAM_Y4_X2_BANK_BASE@GOTPAGEOFF]
Lloh143:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh144:
	adrp	x8, _mmSRAM_Y4_X2_RTR_BASE@GOTPAGE
Lloh145:
	ldr	x8, [x8, _mmSRAM_Y4_X2_RTR_BASE@GOTPAGEOFF]
Lloh146:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh147:
	adrp	x8, _mmSRAM_Y4_X3_BANK_BASE@GOTPAGE
Lloh148:
	ldr	x8, [x8, _mmSRAM_Y4_X3_BANK_BASE@GOTPAGEOFF]
Lloh149:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh150:
	adrp	x8, _mmSRAM_Y4_X3_RTR_BASE@GOTPAGE
Lloh151:
	ldr	x8, [x8, _mmSRAM_Y4_X3_RTR_BASE@GOTPAGEOFF]
Lloh152:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh153:
	adrp	x8, _mmSRAM_Y4_X4_BANK_BASE@GOTPAGE
Lloh154:
	ldr	x8, [x8, _mmSRAM_Y4_X4_BANK_BASE@GOTPAGEOFF]
Lloh155:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh156:
	adrp	x8, _mmSRAM_Y4_X4_RTR_BASE@GOTPAGE
Lloh157:
	ldr	x8, [x8, _mmSRAM_Y4_X4_RTR_BASE@GOTPAGEOFF]
Lloh158:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh159:
	adrp	x8, _mmSRAM_Y5_X0_BANK_BASE@GOTPAGE
Lloh160:
	ldr	x8, [x8, _mmSRAM_Y5_X0_BANK_BASE@GOTPAGEOFF]
Lloh161:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh162:
	adrp	x8, _mmSRAM_Y5_X0_RTR_BASE@GOTPAGE
Lloh163:
	ldr	x8, [x8, _mmSRAM_Y5_X0_RTR_BASE@GOTPAGEOFF]
Lloh164:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh165:
	adrp	x8, _mmSRAM_Y5_X1_BANK_BASE@GOTPAGE
Lloh166:
	ldr	x8, [x8, _mmSRAM_Y5_X1_BANK_BASE@GOTPAGEOFF]
Lloh167:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh168:
	adrp	x8, _mmSRAM_Y5_X1_RTR_BASE@GOTPAGE
Lloh169:
	ldr	x8, [x8, _mmSRAM_Y5_X1_RTR_BASE@GOTPAGEOFF]
Lloh170:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh171:
	adrp	x8, _mmSRAM_Y5_X2_BANK_BASE@GOTPAGE
Lloh172:
	ldr	x8, [x8, _mmSRAM_Y5_X2_BANK_BASE@GOTPAGEOFF]
Lloh173:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh174:
	adrp	x8, _mmSRAM_Y5_X2_RTR_BASE@GOTPAGE
Lloh175:
	ldr	x8, [x8, _mmSRAM_Y5_X2_RTR_BASE@GOTPAGEOFF]
Lloh176:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh177:
	adrp	x8, _mmSRAM_Y5_X3_BANK_BASE@GOTPAGE
Lloh178:
	ldr	x8, [x8, _mmSRAM_Y5_X3_BANK_BASE@GOTPAGEOFF]
Lloh179:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh180:
	adrp	x8, _mmSRAM_Y5_X3_RTR_BASE@GOTPAGE
Lloh181:
	ldr	x8, [x8, _mmSRAM_Y5_X3_RTR_BASE@GOTPAGEOFF]
Lloh182:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh183:
	adrp	x8, _mmSRAM_Y5_X4_BANK_BASE@GOTPAGE
Lloh184:
	ldr	x8, [x8, _mmSRAM_Y5_X4_BANK_BASE@GOTPAGEOFF]
Lloh185:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh186:
	adrp	x8, _mmSRAM_Y5_X4_RTR_BASE@GOTPAGE
Lloh187:
	ldr	x8, [x8, _mmSRAM_Y5_X4_RTR_BASE@GOTPAGEOFF]
Lloh188:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh189:
	adrp	x8, _mmPCIE_WRAP_BASE@GOTPAGE
Lloh190:
	ldr	x8, [x8, _mmPCIE_WRAP_BASE@GOTPAGEOFF]
Lloh191:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh192:
	adrp	x8, _mmPCIE_CORE_BASE@GOTPAGE
Lloh193:
	ldr	x8, [x8, _mmPCIE_CORE_BASE@GOTPAGEOFF]
Lloh194:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh195:
	adrp	x8, _mmPCIE_DB_CFG_BASE@GOTPAGE
Lloh196:
	ldr	x8, [x8, _mmPCIE_DB_CFG_BASE@GOTPAGEOFF]
Lloh197:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh198:
	adrp	x8, _mmPCIE_DB_CMD_BASE@GOTPAGE
Lloh199:
	ldr	x8, [x8, _mmPCIE_DB_CMD_BASE@GOTPAGEOFF]
Lloh200:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh201:
	adrp	x8, _mmPCIE_AUX_BASE@GOTPAGE
Lloh202:
	ldr	x8, [x8, _mmPCIE_AUX_BASE@GOTPAGEOFF]
Lloh203:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh204:
	adrp	x8, _mmPCIE_DB_RSV_BASE@GOTPAGE
Lloh205:
	ldr	x8, [x8, _mmPCIE_DB_RSV_BASE@GOTPAGEOFF]
Lloh206:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh207:
	adrp	x8, _mmPCIE_PHY_BASE@GOTPAGE
Lloh208:
	ldr	x8, [x8, _mmPCIE_PHY_BASE@GOTPAGEOFF]
Lloh209:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh210:
	adrp	x8, _mmTPC0_NRTR_BASE@GOTPAGE
Lloh211:
	ldr	x8, [x8, _mmTPC0_NRTR_BASE@GOTPAGEOFF]
Lloh212:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh213:
	adrp	x8, _mmTPC_PLL_BASE@GOTPAGE
Lloh214:
	ldr	x8, [x8, _mmTPC_PLL_BASE@GOTPAGEOFF]
Lloh215:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_goya_pb_set_block
Lloh216:
	adrp	x8, _mmTPC_PLL_CLK_RLX_0@GOTPAGE
Lloh217:
	ldr	x8, [x8, _mmTPC_PLL_CLK_RLX_0@GOTPAGEOFF]
Lloh218:
	ldr	w8, [x8]
	and	w9, w8, #0xfffff000
Lloh219:
	adrp	x10, _PROT_BITS_OFFS@GOTPAGE
Lloh220:
	ldr	x10, [x10, _PROT_BITS_OFFS@GOTPAGEOFF]
Lloh221:
	ldr	w10, [x10]
	and	w11, w10, w8
	asr	w11, w11, #5
	and	w11, w11, #0xfffffffc
	lsr	w8, w8, #2
	mov	w12, #1
	lsl	w1, w12, w8
	add	w8, w9, w10
	add	w0, w8, w11
	bl	_WREG32
	mov	x0, x19
	bl	_goya_init_mme_protection_bits
	mov	x0, x19
	bl	_goya_init_dma_protection_bits
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_goya_init_tpc_protection_bits
	.loh AdrpLdrGotLdr	Lloh219, Lloh220, Lloh221
	.loh AdrpLdrGotLdr	Lloh216, Lloh217, Lloh218
	.loh AdrpLdrGotLdr	Lloh213, Lloh214, Lloh215
	.loh AdrpLdrGotLdr	Lloh210, Lloh211, Lloh212
	.loh AdrpLdrGotLdr	Lloh207, Lloh208, Lloh209
	.loh AdrpLdrGotLdr	Lloh204, Lloh205, Lloh206
	.loh AdrpLdrGotLdr	Lloh201, Lloh202, Lloh203
	.loh AdrpLdrGotLdr	Lloh198, Lloh199, Lloh200
	.loh AdrpLdrGotLdr	Lloh195, Lloh196, Lloh197
	.loh AdrpLdrGotLdr	Lloh192, Lloh193, Lloh194
	.loh AdrpLdrGotLdr	Lloh189, Lloh190, Lloh191
	.loh AdrpLdrGotLdr	Lloh186, Lloh187, Lloh188
	.loh AdrpLdrGotLdr	Lloh183, Lloh184, Lloh185
	.loh AdrpLdrGotLdr	Lloh180, Lloh181, Lloh182
	.loh AdrpLdrGotLdr	Lloh177, Lloh178, Lloh179
	.loh AdrpLdrGotLdr	Lloh174, Lloh175, Lloh176
	.loh AdrpLdrGotLdr	Lloh171, Lloh172, Lloh173
	.loh AdrpLdrGotLdr	Lloh168, Lloh169, Lloh170
	.loh AdrpLdrGotLdr	Lloh165, Lloh166, Lloh167
	.loh AdrpLdrGotLdr	Lloh162, Lloh163, Lloh164
	.loh AdrpLdrGotLdr	Lloh159, Lloh160, Lloh161
	.loh AdrpLdrGotLdr	Lloh156, Lloh157, Lloh158
	.loh AdrpLdrGotLdr	Lloh153, Lloh154, Lloh155
	.loh AdrpLdrGotLdr	Lloh150, Lloh151, Lloh152
	.loh AdrpLdrGotLdr	Lloh147, Lloh148, Lloh149
	.loh AdrpLdrGotLdr	Lloh144, Lloh145, Lloh146
	.loh AdrpLdrGotLdr	Lloh141, Lloh142, Lloh143
	.loh AdrpLdrGotLdr	Lloh138, Lloh139, Lloh140
	.loh AdrpLdrGotLdr	Lloh135, Lloh136, Lloh137
	.loh AdrpLdrGotLdr	Lloh132, Lloh133, Lloh134
	.loh AdrpLdrGotLdr	Lloh129, Lloh130, Lloh131
	.loh AdrpLdrGotLdr	Lloh126, Lloh127, Lloh128
	.loh AdrpLdrGotLdr	Lloh123, Lloh124, Lloh125
	.loh AdrpLdrGotLdr	Lloh120, Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_mmPCI_NRTR_BASE,4,2            ; @mmPCI_NRTR_BASE
	.comm	_mmPCI_RD_REGULATOR_BASE,4,2    ; @mmPCI_RD_REGULATOR_BASE
	.comm	_mmPCI_WR_REGULATOR_BASE,4,2    ; @mmPCI_WR_REGULATOR_BASE
	.comm	_mmSRAM_Y0_X0_BANK_BASE,4,2     ; @mmSRAM_Y0_X0_BANK_BASE
	.comm	_mmSRAM_Y0_X0_RTR_BASE,4,2      ; @mmSRAM_Y0_X0_RTR_BASE
	.comm	_mmSRAM_Y0_X1_BANK_BASE,4,2     ; @mmSRAM_Y0_X1_BANK_BASE
	.comm	_mmSRAM_Y0_X1_RTR_BASE,4,2      ; @mmSRAM_Y0_X1_RTR_BASE
	.comm	_mmSRAM_Y0_X2_BANK_BASE,4,2     ; @mmSRAM_Y0_X2_BANK_BASE
	.comm	_mmSRAM_Y0_X2_RTR_BASE,4,2      ; @mmSRAM_Y0_X2_RTR_BASE
	.comm	_mmSRAM_Y0_X3_BANK_BASE,4,2     ; @mmSRAM_Y0_X3_BANK_BASE
	.comm	_mmSRAM_Y0_X3_RTR_BASE,4,2      ; @mmSRAM_Y0_X3_RTR_BASE
	.comm	_mmSRAM_Y0_X4_BANK_BASE,4,2     ; @mmSRAM_Y0_X4_BANK_BASE
	.comm	_mmSRAM_Y0_X4_RTR_BASE,4,2      ; @mmSRAM_Y0_X4_RTR_BASE
	.comm	_mmSRAM_Y1_X0_BANK_BASE,4,2     ; @mmSRAM_Y1_X0_BANK_BASE
	.comm	_mmSRAM_Y1_X0_RTR_BASE,4,2      ; @mmSRAM_Y1_X0_RTR_BASE
	.comm	_mmSRAM_Y1_X1_BANK_BASE,4,2     ; @mmSRAM_Y1_X1_BANK_BASE
	.comm	_mmSRAM_Y1_X1_RTR_BASE,4,2      ; @mmSRAM_Y1_X1_RTR_BASE
	.comm	_mmSRAM_Y1_X2_BANK_BASE,4,2     ; @mmSRAM_Y1_X2_BANK_BASE
	.comm	_mmSRAM_Y1_X2_RTR_BASE,4,2      ; @mmSRAM_Y1_X2_RTR_BASE
	.comm	_mmSRAM_Y1_X3_BANK_BASE,4,2     ; @mmSRAM_Y1_X3_BANK_BASE
	.comm	_mmSRAM_Y1_X3_RTR_BASE,4,2      ; @mmSRAM_Y1_X3_RTR_BASE
	.comm	_mmSRAM_Y1_X4_BANK_BASE,4,2     ; @mmSRAM_Y1_X4_BANK_BASE
	.comm	_mmSRAM_Y1_X4_RTR_BASE,4,2      ; @mmSRAM_Y1_X4_RTR_BASE
	.comm	_mmSRAM_Y2_X0_BANK_BASE,4,2     ; @mmSRAM_Y2_X0_BANK_BASE
	.comm	_mmSRAM_Y2_X0_RTR_BASE,4,2      ; @mmSRAM_Y2_X0_RTR_BASE
	.comm	_mmSRAM_Y2_X1_BANK_BASE,4,2     ; @mmSRAM_Y2_X1_BANK_BASE
	.comm	_mmSRAM_Y2_X1_RTR_BASE,4,2      ; @mmSRAM_Y2_X1_RTR_BASE
	.comm	_mmSRAM_Y2_X2_BANK_BASE,4,2     ; @mmSRAM_Y2_X2_BANK_BASE
	.comm	_mmSRAM_Y2_X2_RTR_BASE,4,2      ; @mmSRAM_Y2_X2_RTR_BASE
	.comm	_mmSRAM_Y2_X3_BANK_BASE,4,2     ; @mmSRAM_Y2_X3_BANK_BASE
	.comm	_mmSRAM_Y2_X3_RTR_BASE,4,2      ; @mmSRAM_Y2_X3_RTR_BASE
	.comm	_mmSRAM_Y2_X4_BANK_BASE,4,2     ; @mmSRAM_Y2_X4_BANK_BASE
	.comm	_mmSRAM_Y2_X4_RTR_BASE,4,2      ; @mmSRAM_Y2_X4_RTR_BASE
	.comm	_mmSRAM_Y3_X0_BANK_BASE,4,2     ; @mmSRAM_Y3_X0_BANK_BASE
	.comm	_mmSRAM_Y3_X0_RTR_BASE,4,2      ; @mmSRAM_Y3_X0_RTR_BASE
	.comm	_mmSRAM_Y3_X1_BANK_BASE,4,2     ; @mmSRAM_Y3_X1_BANK_BASE
	.comm	_mmSRAM_Y3_X1_RTR_BASE,4,2      ; @mmSRAM_Y3_X1_RTR_BASE
	.comm	_mmSRAM_Y3_X2_BANK_BASE,4,2     ; @mmSRAM_Y3_X2_BANK_BASE
	.comm	_mmSRAM_Y3_X2_RTR_BASE,4,2      ; @mmSRAM_Y3_X2_RTR_BASE
	.comm	_mmSRAM_Y3_X3_BANK_BASE,4,2     ; @mmSRAM_Y3_X3_BANK_BASE
	.comm	_mmSRAM_Y3_X3_RTR_BASE,4,2      ; @mmSRAM_Y3_X3_RTR_BASE
	.comm	_mmSRAM_Y3_X4_BANK_BASE,4,2     ; @mmSRAM_Y3_X4_BANK_BASE
	.comm	_mmSRAM_Y3_X4_RTR_BASE,4,2      ; @mmSRAM_Y3_X4_RTR_BASE
	.comm	_mmSRAM_Y4_X0_BANK_BASE,4,2     ; @mmSRAM_Y4_X0_BANK_BASE
	.comm	_mmSRAM_Y4_X0_RTR_BASE,4,2      ; @mmSRAM_Y4_X0_RTR_BASE
	.comm	_mmSRAM_Y4_X1_BANK_BASE,4,2     ; @mmSRAM_Y4_X1_BANK_BASE
	.comm	_mmSRAM_Y4_X1_RTR_BASE,4,2      ; @mmSRAM_Y4_X1_RTR_BASE
	.comm	_mmSRAM_Y4_X2_BANK_BASE,4,2     ; @mmSRAM_Y4_X2_BANK_BASE
	.comm	_mmSRAM_Y4_X2_RTR_BASE,4,2      ; @mmSRAM_Y4_X2_RTR_BASE
	.comm	_mmSRAM_Y4_X3_BANK_BASE,4,2     ; @mmSRAM_Y4_X3_BANK_BASE
	.comm	_mmSRAM_Y4_X3_RTR_BASE,4,2      ; @mmSRAM_Y4_X3_RTR_BASE
	.comm	_mmSRAM_Y4_X4_BANK_BASE,4,2     ; @mmSRAM_Y4_X4_BANK_BASE
	.comm	_mmSRAM_Y4_X4_RTR_BASE,4,2      ; @mmSRAM_Y4_X4_RTR_BASE
	.comm	_mmSRAM_Y5_X0_BANK_BASE,4,2     ; @mmSRAM_Y5_X0_BANK_BASE
	.comm	_mmSRAM_Y5_X0_RTR_BASE,4,2      ; @mmSRAM_Y5_X0_RTR_BASE
	.comm	_mmSRAM_Y5_X1_BANK_BASE,4,2     ; @mmSRAM_Y5_X1_BANK_BASE
	.comm	_mmSRAM_Y5_X1_RTR_BASE,4,2      ; @mmSRAM_Y5_X1_RTR_BASE
	.comm	_mmSRAM_Y5_X2_BANK_BASE,4,2     ; @mmSRAM_Y5_X2_BANK_BASE
	.comm	_mmSRAM_Y5_X2_RTR_BASE,4,2      ; @mmSRAM_Y5_X2_RTR_BASE
	.comm	_mmSRAM_Y5_X3_BANK_BASE,4,2     ; @mmSRAM_Y5_X3_BANK_BASE
	.comm	_mmSRAM_Y5_X3_RTR_BASE,4,2      ; @mmSRAM_Y5_X3_RTR_BASE
	.comm	_mmSRAM_Y5_X4_BANK_BASE,4,2     ; @mmSRAM_Y5_X4_BANK_BASE
	.comm	_mmSRAM_Y5_X4_RTR_BASE,4,2      ; @mmSRAM_Y5_X4_RTR_BASE
	.comm	_mmPCIE_WRAP_BASE,4,2           ; @mmPCIE_WRAP_BASE
	.comm	_mmPCIE_CORE_BASE,4,2           ; @mmPCIE_CORE_BASE
	.comm	_mmPCIE_DB_CFG_BASE,4,2         ; @mmPCIE_DB_CFG_BASE
	.comm	_mmPCIE_DB_CMD_BASE,4,2         ; @mmPCIE_DB_CMD_BASE
	.comm	_mmPCIE_AUX_BASE,4,2            ; @mmPCIE_AUX_BASE
	.comm	_mmPCIE_DB_RSV_BASE,4,2         ; @mmPCIE_DB_RSV_BASE
	.comm	_mmPCIE_PHY_BASE,4,2            ; @mmPCIE_PHY_BASE
	.comm	_mmTPC0_NRTR_BASE,4,2           ; @mmTPC0_NRTR_BASE
	.comm	_mmTPC_PLL_BASE,4,2             ; @mmTPC_PLL_BASE
	.comm	_mmTPC_PLL_CLK_RLX_0,4,2        ; @mmTPC_PLL_CLK_RLX_0
	.comm	_PROT_BITS_OFFS,4,2             ; @PROT_BITS_OFFS
	.no_dead_strip	_goya_init_protection_bits
.subsections_via_symbols
